Fix date in revision 1.220. (Was 2008-04-23, should have been 2009-04-23).
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH
23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH
38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM
44#endif
45
29b0f896
AM
46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM
50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L
58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L
85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
6305a203
L
153/* x86 arch names, types and features */
154typedef struct
155{
156 const char *name; /* arch name */
157 enum processor_type type; /* arch type */
158 i386_cpu_flags flags; /* cpu feature flags */
159}
160arch_entry;
161
e3bb37b5
L
162static void set_code_flag (int);
163static void set_16bit_gcc_code_flag (int);
164static void set_intel_syntax (int);
1efbbeb4 165static void set_intel_mnemonic (int);
db51cc60 166static void set_allow_index_reg (int);
cb19c032 167static void set_sse_check (int);
e3bb37b5 168static void set_cpu_arch (int);
6482c264 169#ifdef TE_PE
e3bb37b5 170static void pe_directive_secrel (int);
6482c264 171#endif
e3bb37b5
L
172static void signed_cons (int);
173static char *output_invalid (int c);
ee86248c
JB
174static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
175 const char *);
176static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
177 const char *);
a7619375 178static int i386_att_operand (char *);
e3bb37b5 179static int i386_intel_operand (char *, int);
ee86248c
JB
180static int i386_intel_simplify (expressionS *);
181static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L
182static const reg_entry *parse_register (char *, char **);
183static char *parse_insn (char *, char *);
184static char *parse_operands (char *, const char *);
185static void swap_operands (void);
4d456e3d 186static void swap_2_operands (int, int);
e3bb37b5
L
187static void optimize_imm (void);
188static void optimize_disp (void);
fa99fab2 189static const template *match_template (void);
e3bb37b5
L
190static int check_string (void);
191static int process_suffix (void);
192static int check_byte_reg (void);
193static int check_long_reg (void);
194static int check_qword_reg (void);
195static int check_word_reg (void);
196static int finalize_imm (void);
85f10a01 197static void process_drex (void);
e3bb37b5
L
198static int process_operands (void);
199static const seg_entry *build_modrm_byte (void);
200static void output_insn (void);
201static void output_imm (fragS *, offsetT);
202static void output_disp (fragS *, offsetT);
29b0f896 203#ifndef I386COFF
e3bb37b5 204static void s_bss (int);
252b5132 205#endif
17d4e2a2
L
206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
207static void handle_large_common (int small ATTRIBUTE_UNUSED);
208#endif
252b5132 209
a847613f 210static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 211
c0f3af97
L
212/* VEX prefix. */
213typedef struct
214{
215 /* VEX prefix is either 2 byte or 3 byte. */
216 unsigned char bytes[3];
217 unsigned int length;
218 /* Destination or source register specifier. */
219 const reg_entry *register_specifier;
220} vex_prefix;
221
252b5132 222/* 'md_assemble ()' gathers together information and puts it into a
47926f60 223 i386_insn. */
252b5132 224
520dc8e8
AM
225union i386_op
226 {
227 expressionS *disps;
228 expressionS *imms;
229 const reg_entry *regs;
230 };
231
252b5132
RH
232struct _i386_insn
233 {
47926f60 234 /* TM holds the template for the insn were currently assembling. */
252b5132
RH
235 template tm;
236
7d5e4556
L
237 /* SUFFIX holds the instruction size suffix for byte, word, dword
238 or qword, if given. */
252b5132
RH
239 char suffix;
240
47926f60 241 /* OPERANDS gives the number of given operands. */
252b5132
RH
242 unsigned int operands;
243
244 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
245 of given register, displacement, memory operands and immediate
47926f60 246 operands. */
252b5132
RH
247 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
248
249 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 250 use OP[i] for the corresponding operand. */
40fb9820 251 i386_operand_type types[MAX_OPERANDS];
252b5132 252
520dc8e8
AM
253 /* Displacement expression, immediate expression, or register for each
254 operand. */
255 union i386_op op[MAX_OPERANDS];
252b5132 256
3e73aa7c
JH
257 /* Flags for operands. */
258 unsigned int flags[MAX_OPERANDS];
259#define Operand_PCrel 1
260
252b5132 261 /* Relocation type for operand */
f86103b7 262 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 263
252b5132
RH
264 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
265 the base index byte below. */
266 const reg_entry *base_reg;
267 const reg_entry *index_reg;
268 unsigned int log2_scale_factor;
269
270 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 271 explicit segment overrides are given. */
ce8a8b2f 272 const seg_entry *seg[2];
252b5132
RH
273
274 /* PREFIX holds all the given prefix opcodes (usually null).
275 PREFIXES is the number of prefix opcodes. */
276 unsigned int prefixes;
277 unsigned char prefix[MAX_PREFIXES];
278
279 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM
280 addressing modes of this insn are encoded. DREX is the byte
281 added by the SSE5 instructions. */
252b5132
RH
282
283 modrm_byte rm;
3e73aa7c 284 rex_byte rex;
252b5132 285 sib_byte sib;
85f10a01 286 drex_byte drex;
c0f3af97 287 vex_prefix vex;
b6169b20
L
288
289 /* Swap operand in encoding. */
290 unsigned int swap_operand : 1;
252b5132
RH
291 };
292
293typedef struct _i386_insn i386_insn;
294
295/* List of chars besides those in app.c:symbol_chars that can start an
296 operand. Used to prevent the scrubber eating vital white-space. */
32137342 297const char extra_symbol_chars[] = "*%-(["
252b5132 298#ifdef LEX_AT
32137342
NC
299 "@"
300#endif
301#ifdef LEX_QM
302 "?"
252b5132 303#endif
32137342 304 ;
252b5132 305
29b0f896
AM
306#if (defined (TE_I386AIX) \
307 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 308 && !defined (TE_GNU) \
29b0f896 309 && !defined (TE_LINUX) \
32137342 310 && !defined (TE_NETWARE) \
29b0f896
AM
311 && !defined (TE_FreeBSD) \
312 && !defined (TE_NetBSD)))
252b5132 313/* This array holds the chars that always start a comment. If the
b3b91714
AM
314 pre-processor is disabled, these aren't very useful. The option
315 --divide will remove '/' from this list. */
316const char *i386_comment_chars = "#/";
317#define SVR4_COMMENT_CHARS 1
252b5132 318#define PREFIX_SEPARATOR '\\'
252b5132 319
b3b91714
AM
320#else
321const char *i386_comment_chars = "#";
322#define PREFIX_SEPARATOR '/'
323#endif
324
252b5132
RH
325/* This array holds the chars that only start a comment at the beginning of
326 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM
327 .line and .file directives will appear in the pre-processed output.
328 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 329 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM
330 #NO_APP at the beginning of its output.
331 Also note that comments started like this one will always work if
252b5132 332 '/' isn't otherwise defined. */
b3b91714 333const char line_comment_chars[] = "#/";
252b5132 334
63a0b638 335const char line_separator_chars[] = ";";
252b5132 336
ce8a8b2f
AM
337/* Chars that can be used to separate mant from exp in floating point
338 nums. */
252b5132
RH
339const char EXP_CHARS[] = "eE";
340
ce8a8b2f
AM
341/* Chars that mean this number is a floating point constant
342 As in 0f12.456
343 or 0d1.2345e12. */
252b5132
RH
344const char FLT_CHARS[] = "fFdDxX";
345
ce8a8b2f 346/* Tables for lexical analysis. */
252b5132
RH
347static char mnemonic_chars[256];
348static char register_chars[256];
349static char operand_chars[256];
350static char identifier_chars[256];
351static char digit_chars[256];
352
ce8a8b2f 353/* Lexical macros. */
252b5132
RH
354#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
355#define is_operand_char(x) (operand_chars[(unsigned char) x])
356#define is_register_char(x) (register_chars[(unsigned char) x])
357#define is_space_char(x) ((x) == ' ')
358#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
359#define is_digit_char(x) (digit_chars[(unsigned char) x])
360
0234cb7c 361/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH
362static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
363
364/* md_assemble() always leaves the strings it's passed unaltered. To
365 effect this we maintain a stack of saved characters that we've smashed
366 with '\0's (indicating end of strings for various sub-fields of the
47926f60 367 assembler instruction). */
252b5132 368static char save_stack[32];
ce8a8b2f 369static char *save_stack_p;
252b5132
RH
370#define END_STRING_AND_SAVE(s) \
371 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
372#define RESTORE_END_STRING(s) \
373 do { *(s) = *--save_stack_p; } while (0)
374
47926f60 375/* The instruction we're assembling. */
252b5132
RH
376static i386_insn i;
377
378/* Possible templates for current insn. */
379static const templates *current_templates;
380
31b2323c
L
381/* Per instruction expressionS buffers: max displacements & immediates. */
382static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
383static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 384
47926f60 385/* Current operand we are working on. */
ee86248c 386static int this_operand = -1;
252b5132 387
3e73aa7c
JH
388/* We support four different modes. FLAG_CODE variable is used to distinguish
389 these. */
390
391enum flag_code {
392 CODE_32BIT,
393 CODE_16BIT,
394 CODE_64BIT };
395
396static enum flag_code flag_code;
4fa24527 397static unsigned int object_64bit;
3e73aa7c
JH
398static int use_rela_relocations = 0;
399
400/* The names used to print error messages. */
b77a7acd 401static const char *flag_code_names[] =
3e73aa7c
JH
402 {
403 "32",
404 "16",
405 "64"
406 };
252b5132 407
47926f60
KH
408/* 1 for intel syntax,
409 0 if att syntax. */
410static int intel_syntax = 0;
252b5132 411
1efbbeb4
L
412/* 1 for intel mnemonic,
413 0 if att mnemonic. */
414static int intel_mnemonic = !SYSV386_COMPAT;
415
5209009a 416/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L
417static int old_gcc = OLDGCC_COMPAT;
418
a60de03c
JB
419/* 1 if pseudo registers are permitted. */
420static int allow_pseudo_reg = 0;
421
47926f60
KH
422/* 1 if register prefix % not required. */
423static int allow_naked_reg = 0;
252b5132 424
ba104c83 425/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L
426static int allow_index_reg = 0;
427
daf50ae7
L
428static enum
429 {
430 sse_check_none = 0,
431 sse_check_warning,
432 sse_check_error
433 }
434sse_check;
435
2ca3ace5
L
436/* Register prefix used for error message. */
437static const char *register_prefix = "%";
438
47926f60
KH
439/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
440 leave, push, and pop instructions so that gcc has the same stack
441 frame as in 32 bit mode. */
442static char stackop_size = '\0';
eecb386c 443
12b55ccc
L
444/* Non-zero to optimize code alignment. */
445int optimize_align_code = 1;
446
47926f60
KH
447/* Non-zero to quieten some warnings. */
448static int quiet_warnings = 0;
a38cf1db 449
47926f60
KH
450/* CPU name. */
451static const char *cpu_arch_name = NULL;
6305a203 452static char *cpu_sub_arch_name = NULL;
a38cf1db 453
47926f60 454/* CPU feature flags. */
40fb9820
L
455static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
456
ccc9c027
L
457/* If we have selected a cpu we are generating instructions for. */
458static int cpu_arch_tune_set = 0;
459
9103f4f4 460/* Cpu we are generating instructions for. */
fbf3f584 461enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L
462
463/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 464static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 465
ccc9c027 466/* CPU instruction set architecture used. */
fbf3f584 467enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 468
9103f4f4 469/* CPU feature flags of instruction set architecture used. */
fbf3f584 470i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 471
fddf5b5b
AM
472/* If set, conditional jumps are not automatically promoted to handle
473 larger than a byte offset. */
474static unsigned int no_cond_jump_promotion = 0;
475
c0f3af97
L
476/* Encode SSE instructions with VEX prefix. */
477static unsigned int sse2avx;
478
29b0f896 479/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 480static symbolS *GOT_symbol;
29b0f896 481
a4447b93
RH
482/* The dwarf2 return column, adjusted for 32 or 64 bit. */
483unsigned int x86_dwarf2_return_column;
484
485/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
486int x86_cie_data_alignment;
487
252b5132 488/* Interface to relax_segment.
fddf5b5b
AM
489 There are 3 major relax states for 386 jump insns because the
490 different types of jumps add different sizes to frags when we're
491 figuring out what sort of jump to choose to reach a given label. */
252b5132 492
47926f60 493/* Types. */
93c2a809
AM
494#define UNCOND_JUMP 0
495#define COND_JUMP 1
496#define COND_JUMP86 2
fddf5b5b 497
47926f60 498/* Sizes. */
252b5132
RH
499#define CODE16 1
500#define SMALL 0
29b0f896 501#define SMALL16 (SMALL | CODE16)
252b5132 502#define BIG 2
29b0f896 503#define BIG16 (BIG | CODE16)
252b5132
RH
504
505#ifndef INLINE
506#ifdef __GNUC__
507#define INLINE __inline__
508#else
509#define INLINE
510#endif
511#endif
512
fddf5b5b
AM
513#define ENCODE_RELAX_STATE(type, size) \
514 ((relax_substateT) (((type) << 2) | (size)))
515#define TYPE_FROM_RELAX_STATE(s) \
516 ((s) >> 2)
517#define DISP_SIZE_FROM_RELAX_STATE(s) \
518 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH
519
520/* This table is used by relax_frag to promote short jumps to long
521 ones where necessary. SMALL (short) jumps may be promoted to BIG
522 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
523 don't allow a short jump in a 32 bit code segment to be promoted to
524 a 16 bit offset jump because it's slower (requires data size
525 prefix), and doesn't work, unless the destination is in the bottom
526 64k of the code segment (The top 16 bits of eip are zeroed). */
527
528const relax_typeS md_relax_table[] =
529{
24eab124
AM
530 /* The fields are:
531 1) most positive reach of this state,
532 2) most negative reach of this state,
93c2a809 533 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 534 4) which index into the table to try if we can't fit into this one. */
252b5132 535
fddf5b5b 536 /* UNCOND_JUMP states. */
93c2a809
AM
537 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
538 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
539 /* dword jmp adds 4 bytes to frag:
540 0 extra opcode bytes, 4 displacement bytes. */
252b5132 541 {0, 0, 4, 0},
93c2a809
AM
542 /* word jmp adds 2 byte2 to frag:
543 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH
544 {0, 0, 2, 0},
545
93c2a809
AM
546 /* COND_JUMP states. */
547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
549 /* dword conditionals adds 5 bytes to frag:
550 1 extra opcode byte, 4 displacement bytes. */
551 {0, 0, 5, 0},
fddf5b5b 552 /* word conditionals add 3 bytes to frag:
93c2a809
AM
553 1 extra opcode byte, 2 displacement bytes. */
554 {0, 0, 3, 0},
555
556 /* COND_JUMP86 states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
559 /* dword conditionals adds 5 bytes to frag:
560 1 extra opcode byte, 4 displacement bytes. */
561 {0, 0, 5, 0},
562 /* word conditionals add 4 bytes to frag:
563 1 displacement byte and a 3 byte long branch insn. */
564 {0, 0, 4, 0}
252b5132
RH
565};
566
9103f4f4
L
567static const arch_entry cpu_arch[] =
568{
6305a203
L
569 { "generic32", PROCESSOR_GENERIC32,
570 CPU_GENERIC32_FLAGS },
571 { "generic64", PROCESSOR_GENERIC64,
572 CPU_GENERIC64_FLAGS },
573 { "i8086", PROCESSOR_UNKNOWN,
574 CPU_NONE_FLAGS },
575 { "i186", PROCESSOR_UNKNOWN,
576 CPU_I186_FLAGS },
577 { "i286", PROCESSOR_UNKNOWN,
578 CPU_I286_FLAGS },
579 { "i386", PROCESSOR_I386,
580 CPU_I386_FLAGS },
581 { "i486", PROCESSOR_I486,
582 CPU_I486_FLAGS },
583 { "i586", PROCESSOR_PENTIUM,
584 CPU_I586_FLAGS },
585 { "i686", PROCESSOR_PENTIUMPRO,
586 CPU_I686_FLAGS },
587 { "pentium", PROCESSOR_PENTIUM,
588 CPU_I586_FLAGS },
589 { "pentiumpro", PROCESSOR_PENTIUMPRO,
590 CPU_I686_FLAGS },
591 { "pentiumii", PROCESSOR_PENTIUMPRO,
592 CPU_P2_FLAGS },
593 { "pentiumiii",PROCESSOR_PENTIUMPRO,
594 CPU_P3_FLAGS },
595 { "pentium4", PROCESSOR_PENTIUM4,
596 CPU_P4_FLAGS },
597 { "prescott", PROCESSOR_NOCONA,
598 CPU_CORE_FLAGS },
599 { "nocona", PROCESSOR_NOCONA,
600 CPU_NOCONA_FLAGS },
601 { "yonah", PROCESSOR_CORE,
602 CPU_CORE_FLAGS },
603 { "core", PROCESSOR_CORE,
604 CPU_CORE_FLAGS },
605 { "merom", PROCESSOR_CORE2,
606 CPU_CORE2_FLAGS },
607 { "core2", PROCESSOR_CORE2,
608 CPU_CORE2_FLAGS },
bd5295b2
L
609 { "corei7", PROCESSOR_COREI7,
610 CPU_COREI7_FLAGS },
6305a203
L
611 { "k6", PROCESSOR_K6,
612 CPU_K6_FLAGS },
613 { "k6_2", PROCESSOR_K6,
614 CPU_K6_2_FLAGS },
615 { "athlon", PROCESSOR_ATHLON,
616 CPU_ATHLON_FLAGS },
617 { "sledgehammer", PROCESSOR_K8,
618 CPU_K8_FLAGS },
619 { "opteron", PROCESSOR_K8,
620 CPU_K8_FLAGS },
621 { "k8", PROCESSOR_K8,
622 CPU_K8_FLAGS },
623 { "amdfam10", PROCESSOR_AMDFAM10,
624 CPU_AMDFAM10_FLAGS },
625 { ".mmx", PROCESSOR_UNKNOWN,
626 CPU_MMX_FLAGS },
627 { ".sse", PROCESSOR_UNKNOWN,
628 CPU_SSE_FLAGS },
629 { ".sse2", PROCESSOR_UNKNOWN,
630 CPU_SSE2_FLAGS },
631 { ".sse3", PROCESSOR_UNKNOWN,
632 CPU_SSE3_FLAGS },
633 { ".ssse3", PROCESSOR_UNKNOWN,
634 CPU_SSSE3_FLAGS },
635 { ".sse4.1", PROCESSOR_UNKNOWN,
636 CPU_SSE4_1_FLAGS },
637 { ".sse4.2", PROCESSOR_UNKNOWN,
638 CPU_SSE4_2_FLAGS },
639 { ".sse4", PROCESSOR_UNKNOWN,
640 CPU_SSE4_2_FLAGS },
c0f3af97
L
641 { ".avx", PROCESSOR_UNKNOWN,
642 CPU_AVX_FLAGS },
6305a203
L
643 { ".vmx", PROCESSOR_UNKNOWN,
644 CPU_VMX_FLAGS },
645 { ".smx", PROCESSOR_UNKNOWN,
646 CPU_SMX_FLAGS },
f03fe4c1
L
647 { ".xsave", PROCESSOR_UNKNOWN,
648 CPU_XSAVE_FLAGS },
c0f3af97
L
649 { ".aes", PROCESSOR_UNKNOWN,
650 CPU_AES_FLAGS },
594ab6a3
L
651 { ".pclmul", PROCESSOR_UNKNOWN,
652 CPU_PCLMUL_FLAGS },
c0f3af97 653 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 654 CPU_PCLMUL_FLAGS },
c0f3af97
L
655 { ".fma", PROCESSOR_UNKNOWN,
656 CPU_FMA_FLAGS },
f1f8f695
L
657 { ".movbe", PROCESSOR_UNKNOWN,
658 CPU_MOVBE_FLAGS },
659 { ".ept", PROCESSOR_UNKNOWN,
660 CPU_EPT_FLAGS },
bd5295b2
L
661 { ".clflush", PROCESSOR_UNKNOWN,
662 CPU_CLFLUSH_FLAGS },
663 { ".syscall", PROCESSOR_UNKNOWN,
664 CPU_SYSCALL_FLAGS },
1b7f3fb0
L
665 { ".rdtscp", PROCESSOR_UNKNOWN,
666 CPU_RDTSCP_FLAGS },
6305a203
L
667 { ".3dnow", PROCESSOR_UNKNOWN,
668 CPU_3DNOW_FLAGS },
669 { ".3dnowa", PROCESSOR_UNKNOWN,
670 CPU_3DNOWA_FLAGS },
671 { ".padlock", PROCESSOR_UNKNOWN,
672 CPU_PADLOCK_FLAGS },
673 { ".pacifica", PROCESSOR_UNKNOWN,
674 CPU_SVME_FLAGS },
675 { ".svme", PROCESSOR_UNKNOWN,
676 CPU_SVME_FLAGS },
677 { ".sse4a", PROCESSOR_UNKNOWN,
678 CPU_SSE4A_FLAGS },
679 { ".abm", PROCESSOR_UNKNOWN,
680 CPU_ABM_FLAGS },
681 { ".sse5", PROCESSOR_UNKNOWN,
682 CPU_SSE5_FLAGS },
e413e4e9
AM
683};
684
704209c0 685#ifdef I386COFF
a6c24e68
NC
686/* Like s_lcomm_internal in gas/read.c but the alignment string
687 is allowed to be optional. */
688
689static symbolS *
690pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
691{
692 addressT align = 0;
693
694 SKIP_WHITESPACE ();
695
696 if (needs_align
697 && *input_line_pointer == ',')
698 {
699 align = parse_align (needs_align - 1);
700
701 if (align == (addressT) -1)
702 return NULL;
703 }
704 else
705 {
706 if (size >= 8)
707 align = 3;
708 else if (size >= 4)
709 align = 2;
710 else if (size >= 2)
711 align = 1;
712 else
713 align = 0;
714 }
715
716 bss_alloc (symbolP, size, align);
717 return symbolP;
718}
719
704209c0 720static void
a6c24e68
NC
721pe_lcomm (int needs_align)
722{
723 s_comm_internal (needs_align * 2, pe_lcomm_internal);
724}
704209c0 725#endif
a6c24e68 726
29b0f896
AM
727const pseudo_typeS md_pseudo_table[] =
728{
729#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
730 {"align", s_align_bytes, 0},
731#else
732 {"align", s_align_ptwo, 0},
733#endif
734 {"arch", set_cpu_arch, 0},
735#ifndef I386COFF
736 {"bss", s_bss, 0},
a6c24e68
NC
737#else
738 {"lcomm", pe_lcomm, 1},
29b0f896
AM
739#endif
740 {"ffloat", float_cons, 'f'},
741 {"dfloat", float_cons, 'd'},
742 {"tfloat", float_cons, 'x'},
743 {"value", cons, 2},
d182319b 744 {"slong", signed_cons, 4},
29b0f896
AM
745 {"noopt", s_ignore, 0},
746 {"optim", s_ignore, 0},
747 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
748 {"code16", set_code_flag, CODE_16BIT},
749 {"code32", set_code_flag, CODE_32BIT},
750 {"code64", set_code_flag, CODE_64BIT},
751 {"intel_syntax", set_intel_syntax, 1},
752 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L
753 {"intel_mnemonic", set_intel_mnemonic, 1},
754 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L
755 {"allow_index_reg", set_allow_index_reg, 1},
756 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 757 {"sse_check", set_sse_check, 0},
3b22753a
L
758#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
759 {"largecomm", handle_large_common, 0},
07a53e5c 760#else
e3bb37b5 761 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH
762 {"loc", dwarf2_directive_loc, 0},
763 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 764#endif
6482c264
NC
765#ifdef TE_PE
766 {"secrel32", pe_directive_secrel, 0},
767#endif
29b0f896
AM
768 {0, 0, 0}
769};
770
771/* For interface with expression (). */
772extern char *input_line_pointer;
773
774/* Hash table for instruction mnemonic lookup. */
775static struct hash_control *op_hash;
776
777/* Hash table for register lookup. */
778static struct hash_control *reg_hash;
779\f
252b5132 780void
e3bb37b5 781i386_align_code (fragS *fragP, int count)
252b5132 782{
ce8a8b2f
AM
783 /* Various efficient no-op patterns for aligning code labels.
784 Note: Don't try to assemble the instructions in the comments.
785 0L and 0w are not legal. */
252b5132
RH
786 static const char f32_1[] =
787 {0x90}; /* nop */
788 static const char f32_2[] =
ccc9c027 789 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH
790 static const char f32_3[] =
791 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
792 static const char f32_4[] =
793 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
794 static const char f32_5[] =
795 {0x90, /* nop */
796 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
797 static const char f32_6[] =
798 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
799 static const char f32_7[] =
800 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
801 static const char f32_8[] =
802 {0x90, /* nop */
803 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
804 static const char f32_9[] =
805 {0x89,0xf6, /* movl %esi,%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_10[] =
808 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
809 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
810 static const char f32_11[] =
811 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_12[] =
814 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
815 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
816 static const char f32_13[] =
817 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
818 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
819 static const char f32_14[] =
820 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
821 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM
822 static const char f16_3[] =
823 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH
824 static const char f16_4[] =
825 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
826 static const char f16_5[] =
827 {0x90, /* nop */
828 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
829 static const char f16_6[] =
830 {0x89,0xf6, /* mov %si,%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
832 static const char f16_7[] =
833 {0x8d,0x74,0x00, /* lea 0(%si),%si */
834 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
835 static const char f16_8[] =
836 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
837 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L
838 static const char jump_31[] =
839 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
840 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
841 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
842 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH
843 static const char *const f32_patt[] = {
844 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 845 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH
846 };
847 static const char *const f16_patt[] = {
76bc74dc 848 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 849 };
ccc9c027
L
850 /* nopl (%[re]ax) */
851 static const char alt_3[] =
852 {0x0f,0x1f,0x00};
853 /* nopl 0(%[re]ax) */
854 static const char alt_4[] =
855 {0x0f,0x1f,0x40,0x00};
856 /* nopl 0(%[re]ax,%[re]ax,1) */
857 static const char alt_5[] =
858 {0x0f,0x1f,0x44,0x00,0x00};
859 /* nopw 0(%[re]ax,%[re]ax,1) */
860 static const char alt_6[] =
861 {0x66,0x0f,0x1f,0x44,0x00,0x00};
862 /* nopl 0L(%[re]ax) */
863 static const char alt_7[] =
864 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
865 /* nopl 0L(%[re]ax,%[re]ax,1) */
866 static const char alt_8[] =
867 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 /* nopw 0L(%[re]ax,%[re]ax,1) */
869 static const char alt_9[] =
870 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
872 static const char alt_10[] =
873 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
874 /* data16
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_11[] =
877 {0x66,
878 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
879 /* data16
880 data16
881 nopw %cs:0L(%[re]ax,%[re]ax,1) */
882 static const char alt_long_12[] =
883 {0x66,
884 0x66,
885 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
886 /* data16
887 data16
888 data16
889 nopw %cs:0L(%[re]ax,%[re]ax,1) */
890 static const char alt_long_13[] =
891 {0x66,
892 0x66,
893 0x66,
894 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
895 /* data16
896 data16
897 data16
898 data16
899 nopw %cs:0L(%[re]ax,%[re]ax,1) */
900 static const char alt_long_14[] =
901 {0x66,
902 0x66,
903 0x66,
904 0x66,
905 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
906 /* data16
907 data16
908 data16
909 data16
910 data16
911 nopw %cs:0L(%[re]ax,%[re]ax,1) */
912 static const char alt_long_15[] =
913 {0x66,
914 0x66,
915 0x66,
916 0x66,
917 0x66,
918 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
919 /* nopl 0(%[re]ax,%[re]ax,1)
920 nopw 0(%[re]ax,%[re]ax,1) */
921 static const char alt_short_11[] =
922 {0x0f,0x1f,0x44,0x00,0x00,
923 0x66,0x0f,0x1f,0x44,0x00,0x00};
924 /* nopw 0(%[re]ax,%[re]ax,1)
925 nopw 0(%[re]ax,%[re]ax,1) */
926 static const char alt_short_12[] =
927 {0x66,0x0f,0x1f,0x44,0x00,0x00,
928 0x66,0x0f,0x1f,0x44,0x00,0x00};
929 /* nopw 0(%[re]ax,%[re]ax,1)
930 nopl 0L(%[re]ax) */
931 static const char alt_short_13[] =
932 {0x66,0x0f,0x1f,0x44,0x00,0x00,
933 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
934 /* nopl 0L(%[re]ax)
935 nopl 0L(%[re]ax) */
936 static const char alt_short_14[] =
937 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
938 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
939 /* nopl 0L(%[re]ax)
940 nopl 0L(%[re]ax,%[re]ax,1) */
941 static const char alt_short_15[] =
942 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
943 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
944 static const char *const alt_short_patt[] = {
945 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
946 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
947 alt_short_14, alt_short_15
948 };
949 static const char *const alt_long_patt[] = {
950 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
951 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
952 alt_long_14, alt_long_15
953 };
252b5132 954
76bc74dc
L
955 /* Only align for at least a positive non-zero boundary. */
956 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 957 return;
3e73aa7c 958
ccc9c027
L
959 /* We need to decide which NOP sequence to use for 32bit and
960 64bit. When -mtune= is used:
4eed87de 961
76bc74dc
L
962 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
963 PROCESSOR_GENERIC32, f32_patt will be used.
964 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L
965 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
966 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L
967 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
968 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 969
76bc74dc
L
970 When -mtune= isn't used, alt_long_patt will be used if
971 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
972 be used.
ccc9c027
L
973
974 When -march= or .arch is used, we can't use anything beyond
975 cpu_arch_isa_flags. */
976
977 if (flag_code == CODE_16BIT)
978 {
ccc9c027 979 if (count > 8)
33fef721 980 {
76bc74dc
L
981 memcpy (fragP->fr_literal + fragP->fr_fix,
982 jump_31, count);
983 /* Adjust jump offset. */
984 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 985 }
76bc74dc
L
986 else
987 memcpy (fragP->fr_literal + fragP->fr_fix,
988 f16_patt[count - 1], count);
252b5132 989 }
33fef721 990 else
ccc9c027
L
991 {
992 const char *const *patt = NULL;
993
fbf3f584 994 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L
995 {
996 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
997 switch (cpu_arch_tune)
998 {
999 case PROCESSOR_UNKNOWN:
1000 /* We use cpu_arch_isa_flags to check if we SHOULD
1001 optimize for Cpu686. */
fbf3f584 1002 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 1003 patt = alt_long_patt;
ccc9c027
L
1004 else
1005 patt = f32_patt;
1006 break;
ccc9c027
L
1007 case PROCESSOR_PENTIUMPRO:
1008 case PROCESSOR_PENTIUM4:
1009 case PROCESSOR_NOCONA:
ef05d495 1010 case PROCESSOR_CORE:
76bc74dc 1011 case PROCESSOR_CORE2:
bd5295b2 1012 case PROCESSOR_COREI7:
76bc74dc
L
1013 case PROCESSOR_GENERIC64:
1014 patt = alt_long_patt;
1015 break;
ccc9c027
L
1016 case PROCESSOR_K6:
1017 case PROCESSOR_ATHLON:
1018 case PROCESSOR_K8:
4eed87de 1019 case PROCESSOR_AMDFAM10:
ccc9c027
L
1020 patt = alt_short_patt;
1021 break;
76bc74dc 1022 case PROCESSOR_I386:
ccc9c027
L
1023 case PROCESSOR_I486:
1024 case PROCESSOR_PENTIUM:
1025 case PROCESSOR_GENERIC32:
1026 patt = f32_patt;
1027 break;
4eed87de 1028 }
ccc9c027
L
1029 }
1030 else
1031 {
fbf3f584 1032 switch (fragP->tc_frag_data.tune)
ccc9c027
L
1033 {
1034 case PROCESSOR_UNKNOWN:
e6a14101 1035 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L
1036 PROCESSOR_UNKNOWN. */
1037 abort ();
1038 break;
1039
76bc74dc 1040 case PROCESSOR_I386:
ccc9c027
L
1041 case PROCESSOR_I486:
1042 case PROCESSOR_PENTIUM:
ccc9c027
L
1043 case PROCESSOR_K6:
1044 case PROCESSOR_ATHLON:
1045 case PROCESSOR_K8:
4eed87de 1046 case PROCESSOR_AMDFAM10:
ccc9c027
L
1047 case PROCESSOR_GENERIC32:
1048 /* We use cpu_arch_isa_flags to check if we CAN optimize
1049 for Cpu686. */
fbf3f584 1050 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L
1051 patt = alt_short_patt;
1052 else
1053 patt = f32_patt;
1054 break;
76bc74dc
L
1055 case PROCESSOR_PENTIUMPRO:
1056 case PROCESSOR_PENTIUM4:
1057 case PROCESSOR_NOCONA:
1058 case PROCESSOR_CORE:
ef05d495 1059 case PROCESSOR_CORE2:
bd5295b2 1060 case PROCESSOR_COREI7:
fbf3f584 1061 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L
1062 patt = alt_long_patt;
1063 else
1064 patt = f32_patt;
1065 break;
1066 case PROCESSOR_GENERIC64:
76bc74dc 1067 patt = alt_long_patt;
ccc9c027 1068 break;
4eed87de 1069 }
ccc9c027
L
1070 }
1071
76bc74dc
L
1072 if (patt == f32_patt)
1073 {
1074 /* If the padding is less than 15 bytes, we use the normal
1075 ones. Otherwise, we use a jump instruction and adjust
1076 its offset. */
1077 if (count < 15)
1078 memcpy (fragP->fr_literal + fragP->fr_fix,
1079 patt[count - 1], count);
1080 else
1081 {
1082 memcpy (fragP->fr_literal + fragP->fr_fix,
1083 jump_31, count);
1084 /* Adjust jump offset. */
1085 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1086 }
1087 }
1088 else
1089 {
1090 /* Maximum length of an instruction is 15 byte. If the
1091 padding is greater than 15 bytes and we don't use jump,
1092 we have to break it into smaller pieces. */
1093 int padding = count;
1094 while (padding > 15)
1095 {
1096 padding -= 15;
1097 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1098 patt [14], 15);
1099 }
1100
1101 if (padding)
1102 memcpy (fragP->fr_literal + fragP->fr_fix,
1103 patt [padding - 1], padding);
1104 }
ccc9c027 1105 }
33fef721 1106 fragP->fr_var = count;
252b5132
RH
1107}
1108
c6fb90c8 1109static INLINE int
0dfbf9d7 1110operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1111{
0dfbf9d7 1112 switch (ARRAY_SIZE(x->array))
c6fb90c8
L
1113 {
1114 case 3:
0dfbf9d7 1115 if (x->array[2])
c6fb90c8
L
1116 return 0;
1117 case 2:
0dfbf9d7 1118 if (x->array[1])
c6fb90c8
L
1119 return 0;
1120 case 1:
0dfbf9d7 1121 return !x->array[0];
c6fb90c8
L
1122 default:
1123 abort ();
1124 }
40fb9820
L
1125}
1126
c6fb90c8 1127static INLINE void
0dfbf9d7 1128operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1129{
0dfbf9d7 1130 switch (ARRAY_SIZE(x->array))
c6fb90c8
L
1131 {
1132 case 3:
0dfbf9d7 1133 x->array[2] = v;
c6fb90c8 1134 case 2:
0dfbf9d7 1135 x->array[1] = v;
c6fb90c8 1136 case 1:
0dfbf9d7 1137 x->array[0] = v;
c6fb90c8
L
1138 break;
1139 default:
1140 abort ();
1141 }
1142}
40fb9820 1143
c6fb90c8 1144static INLINE int
0dfbf9d7
L
1145operand_type_equal (const union i386_operand_type *x,
1146 const union i386_operand_type *y)
c6fb90c8 1147{
0dfbf9d7 1148 switch (ARRAY_SIZE(x->array))
c6fb90c8
L
1149 {
1150 case 3:
0dfbf9d7 1151 if (x->array[2] != y->array[2])
c6fb90c8
L
1152 return 0;
1153 case 2:
0dfbf9d7 1154 if (x->array[1] != y->array[1])
c6fb90c8
L
1155 return 0;
1156 case 1:
0dfbf9d7 1157 return x->array[0] == y->array[0];
c6fb90c8
L
1158 break;
1159 default:
1160 abort ();
1161 }
1162}
40fb9820 1163
0dfbf9d7
L
1164static INLINE int
1165cpu_flags_all_zero (const union i386_cpu_flags *x)
1166{
1167 switch (ARRAY_SIZE(x->array))
1168 {
1169 case 3:
1170 if (x->array[2])
1171 return 0;
1172 case 2:
1173 if (x->array[1])
1174 return 0;
1175 case 1:
1176 return !x->array[0];
1177 default:
1178 abort ();
1179 }
1180}
1181
1182static INLINE void
1183cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1184{
1185 switch (ARRAY_SIZE(x->array))
1186 {
1187 case 3:
1188 x->array[2] = v;
1189 case 2:
1190 x->array[1] = v;
1191 case 1:
1192 x->array[0] = v;
1193 break;
1194 default:
1195 abort ();
1196 }
1197}
1198
1199static INLINE int
1200cpu_flags_equal (const union i386_cpu_flags *x,
1201 const union i386_cpu_flags *y)
1202{
1203 switch (ARRAY_SIZE(x->array))
1204 {
1205 case 3:
1206 if (x->array[2] != y->array[2])
1207 return 0;
1208 case 2:
1209 if (x->array[1] != y->array[1])
1210 return 0;
1211 case 1:
1212 return x->array[0] == y->array[0];
1213 break;
1214 default:
1215 abort ();
1216 }
1217}
c6fb90c8
L
1218
1219static INLINE int
1220cpu_flags_check_cpu64 (i386_cpu_flags f)
1221{
1222 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1223 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L
1224}
1225
c6fb90c8
L
1226static INLINE i386_cpu_flags
1227cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1228{
c6fb90c8
L
1229 switch (ARRAY_SIZE (x.array))
1230 {
1231 case 3:
1232 x.array [2] &= y.array [2];
1233 case 2:
1234 x.array [1] &= y.array [1];
1235 case 1:
1236 x.array [0] &= y.array [0];
1237 break;
1238 default:
1239 abort ();
1240 }
1241 return x;
1242}
40fb9820 1243
c6fb90c8
L
1244static INLINE i386_cpu_flags
1245cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1246{
c6fb90c8 1247 switch (ARRAY_SIZE (x.array))
40fb9820 1248 {
c6fb90c8
L
1249 case 3:
1250 x.array [2] |= y.array [2];
1251 case 2:
1252 x.array [1] |= y.array [1];
1253 case 1:
1254 x.array [0] |= y.array [0];
40fb9820
L
1255 break;
1256 default:
1257 abort ();
1258 }
40fb9820
L
1259 return x;
1260}
1261
c0f3af97
L
1262#define CPU_FLAGS_ARCH_MATCH 0x1
1263#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1264#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L
1265#define CPU_FLAGS_PCLMUL_MATCH 0x8
1266#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1267
a5ff0eb2 1268#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L
1269 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1270 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L
1271#define CPU_FLAGS_PERFECT_MATCH \
1272 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1273
1274/* Return CPU flags match bits. */
3629bb00 1275
40fb9820 1276static int
c0f3af97 1277cpu_flags_match (const template *t)
40fb9820 1278{
c0f3af97
L
1279 i386_cpu_flags x = t->cpu_flags;
1280 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L
1281
1282 x.bitfield.cpu64 = 0;
1283 x.bitfield.cpuno64 = 0;
1284
0dfbf9d7 1285 if (cpu_flags_all_zero (&x))
c0f3af97
L
1286 {
1287 /* This instruction is available on all archs. */
1288 match |= CPU_FLAGS_32BIT_MATCH;
1289 }
3629bb00
L
1290 else
1291 {
c0f3af97 1292 /* This instruction is available only on some archs. */
3629bb00
L
1293 i386_cpu_flags cpu = cpu_arch_flags;
1294
1295 cpu.bitfield.cpu64 = 0;
1296 cpu.bitfield.cpuno64 = 0;
1297 cpu = cpu_flags_and (x, cpu);
c0f3af97
L
1298 if (!cpu_flags_all_zero (&cpu))
1299 {
a5ff0eb2
L
1300 if (x.bitfield.cpuavx)
1301 {
ce2f5b3c 1302 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L
1303 if (cpu.bitfield.cpuavx)
1304 {
1305 /* Check SSE2AVX. */
1306 if (!t->opcode_modifier.sse2avx|| sse2avx)
1307 {
1308 match |= (CPU_FLAGS_ARCH_MATCH
1309 | CPU_FLAGS_AVX_MATCH);
1310 /* Check AES. */
1311 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1312 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L
1313 /* Check PCLMUL. */
1314 if (!x.bitfield.cpupclmul
1315 || cpu.bitfield.cpupclmul)
1316 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L
1317 }
1318 }
1319 else
1320 match |= CPU_FLAGS_ARCH_MATCH;
1321 }
1322 else
c0f3af97
L
1323 match |= CPU_FLAGS_32BIT_MATCH;
1324 }
3629bb00 1325 }
c0f3af97 1326 return match;
40fb9820
L
1327}
1328
c6fb90c8
L
1329static INLINE i386_operand_type
1330operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1331{
c6fb90c8
L
1332 switch (ARRAY_SIZE (x.array))
1333 {
1334 case 3:
1335 x.array [2] &= y.array [2];
1336 case 2:
1337 x.array [1] &= y.array [1];
1338 case 1:
1339 x.array [0] &= y.array [0];
1340 break;
1341 default:
1342 abort ();
1343 }
1344 return x;
40fb9820
L
1345}
1346
c6fb90c8
L
1347static INLINE i386_operand_type
1348operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1349{
c6fb90c8 1350 switch (ARRAY_SIZE (x.array))
40fb9820 1351 {
c6fb90c8
L
1352 case 3:
1353 x.array [2] |= y.array [2];
1354 case 2:
1355 x.array [1] |= y.array [1];
1356 case 1:
1357 x.array [0] |= y.array [0];
40fb9820
L
1358 break;
1359 default:
1360 abort ();
1361 }
c6fb90c8
L
1362 return x;
1363}
40fb9820 1364
c6fb90c8
L
1365static INLINE i386_operand_type
1366operand_type_xor (i386_operand_type x, i386_operand_type y)
1367{
1368 switch (ARRAY_SIZE (x.array))
1369 {
1370 case 3:
1371 x.array [2] ^= y.array [2];
1372 case 2:
1373 x.array [1] ^= y.array [1];
1374 case 1:
1375 x.array [0] ^= y.array [0];
1376 break;
1377 default:
1378 abort ();
1379 }
40fb9820
L
1380 return x;
1381}
1382
1383static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1384static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1385static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L
1386static const i386_operand_type inoutportreg
1387 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L
1388static const i386_operand_type reg16_inoutportreg
1389 = OPERAND_TYPE_REG16_INOUTPORTREG;
1390static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1391static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1392static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1393static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1394static const i386_operand_type anydisp
1395 = OPERAND_TYPE_ANYDISP;
40fb9820 1396static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1397static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L
1398static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1399static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1400static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1401static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1402static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1403static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1404static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1405static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1406static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1407
1408enum operand_type
1409{
1410 reg,
40fb9820
L
1411 imm,
1412 disp,
1413 anymem
1414};
1415
c6fb90c8 1416static INLINE int
40fb9820
L
1417operand_type_check (i386_operand_type t, enum operand_type c)
1418{
1419 switch (c)
1420 {
1421 case reg:
1422 return (t.bitfield.reg8
1423 || t.bitfield.reg16
1424 || t.bitfield.reg32
1425 || t.bitfield.reg64);
1426
40fb9820
L
1427 case imm:
1428 return (t.bitfield.imm8
1429 || t.bitfield.imm8s
1430 || t.bitfield.imm16
1431 || t.bitfield.imm32
1432 || t.bitfield.imm32s
1433 || t.bitfield.imm64);
1434
1435 case disp:
1436 return (t.bitfield.disp8
1437 || t.bitfield.disp16
1438 || t.bitfield.disp32
1439 || t.bitfield.disp32s
1440 || t.bitfield.disp64);
1441
1442 case anymem:
1443 return (t.bitfield.disp8
1444 || t.bitfield.disp16
1445 || t.bitfield.disp32
1446 || t.bitfield.disp32s
1447 || t.bitfield.disp64
1448 || t.bitfield.baseindex);
1449
1450 default:
1451 abort ();
1452 }
2cfe26b6
AM
1453
1454 return 0;
40fb9820
L
1455}
1456
5c07affc
L
1457/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1458 operand J for instruction template T. */
1459
1460static INLINE int
1461match_reg_size (const template *t, unsigned int j)
1462{
1463 return !((i.types[j].bitfield.byte
1464 && !t->operand_types[j].bitfield.byte)
1465 || (i.types[j].bitfield.word
1466 && !t->operand_types[j].bitfield.word)
1467 || (i.types[j].bitfield.dword
1468 && !t->operand_types[j].bitfield.dword)
1469 || (i.types[j].bitfield.qword
1470 && !t->operand_types[j].bitfield.qword));
1471}
1472
1473/* Return 1 if there is no conflict in any size on operand J for
1474 instruction template T. */
1475
1476static INLINE int
1477match_mem_size (const template *t, unsigned int j)
1478{
1479 return (match_reg_size (t, j)
1480 && !((i.types[j].bitfield.unspecified
1481 && !t->operand_types[j].bitfield.unspecified)
1482 || (i.types[j].bitfield.fword
1483 && !t->operand_types[j].bitfield.fword)
1484 || (i.types[j].bitfield.tbyte
1485 && !t->operand_types[j].bitfield.tbyte)
1486 || (i.types[j].bitfield.xmmword
c0f3af97
L
1487 && !t->operand_types[j].bitfield.xmmword)
1488 || (i.types[j].bitfield.ymmword
1489 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L
1490}
1491
1492/* Return 1 if there is no size conflict on any operands for
1493 instruction template T. */
1494
1495static INLINE int
1496operand_size_match (const template *t)
1497{
1498 unsigned int j;
1499 int match = 1;
1500
1501 /* Don't check jump instructions. */
1502 if (t->opcode_modifier.jump
1503 || t->opcode_modifier.jumpbyte
1504 || t->opcode_modifier.jumpdword
1505 || t->opcode_modifier.jumpintersegment)
1506 return match;
1507
1508 /* Check memory and accumulator operand size. */
1509 for (j = 0; j < i.operands; j++)
1510 {
1511 if (t->operand_types[j].bitfield.anysize)
1512 continue;
1513
1514 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1515 {
1516 match = 0;
1517 break;
1518 }
1519
1520 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1521 {
1522 match = 0;
1523 break;
1524 }
1525 }
1526
1527 if (match
1528 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1529 return match;
1530
1531 /* Check reverse. */
1532 assert (i.operands == 2);
1533
1534 match = 1;
1535 for (j = 0; j < 2; j++)
1536 {
1537 if (t->operand_types[j].bitfield.acc
1538 && !match_reg_size (t, j ? 0 : 1))
1539 {
1540 match = 0;
1541 break;
1542 }
1543
1544 if (i.types[j].bitfield.mem
1545 && !match_mem_size (t, j ? 0 : 1))
1546 {
1547 match = 0;
1548 break;
1549 }
1550 }
1551
1552 return match;
1553}
1554
c6fb90c8 1555static INLINE int
40fb9820
L
1556operand_type_match (i386_operand_type overlap,
1557 i386_operand_type given)
1558{
1559 i386_operand_type temp = overlap;
1560
1561 temp.bitfield.jumpabsolute = 0;
7d5e4556 1562 temp.bitfield.unspecified = 0;
5c07affc
L
1563 temp.bitfield.byte = 0;
1564 temp.bitfield.word = 0;
1565 temp.bitfield.dword = 0;
1566 temp.bitfield.fword = 0;
1567 temp.bitfield.qword = 0;
1568 temp.bitfield.tbyte = 0;
1569 temp.bitfield.xmmword = 0;
c0f3af97 1570 temp.bitfield.ymmword = 0;
0dfbf9d7 1571 if (operand_type_all_zero (&temp))
40fb9820
L
1572 return 0;
1573
1574 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1575 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1576}
1577
7d5e4556 1578/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L
1579 unless the expected operand type register overlap is null.
1580 Note that Acc in a template matches every size of reg. */
1581
c6fb90c8 1582static INLINE int
40fb9820
L
1583operand_type_register_match (i386_operand_type m0,
1584 i386_operand_type g0,
1585 i386_operand_type t0,
1586 i386_operand_type m1,
1587 i386_operand_type g1,
1588 i386_operand_type t1)
1589{
1590 if (!operand_type_check (g0, reg))
1591 return 1;
1592
1593 if (!operand_type_check (g1, reg))
1594 return 1;
1595
1596 if (g0.bitfield.reg8 == g1.bitfield.reg8
1597 && g0.bitfield.reg16 == g1.bitfield.reg16
1598 && g0.bitfield.reg32 == g1.bitfield.reg32
1599 && g0.bitfield.reg64 == g1.bitfield.reg64)
1600 return 1;
1601
1602 if (m0.bitfield.acc)
1603 {
1604 t0.bitfield.reg8 = 1;
1605 t0.bitfield.reg16 = 1;
1606 t0.bitfield.reg32 = 1;
1607 t0.bitfield.reg64 = 1;
1608 }
1609
1610 if (m1.bitfield.acc)
1611 {
1612 t1.bitfield.reg8 = 1;
1613 t1.bitfield.reg16 = 1;
1614 t1.bitfield.reg32 = 1;
1615 t1.bitfield.reg64 = 1;
1616 }
1617
1618 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1619 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1620 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1621 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1622}
1623
252b5132 1624static INLINE unsigned int
40fb9820 1625mode_from_disp_size (i386_operand_type t)
252b5132 1626{
40fb9820
L
1627 if (t.bitfield.disp8)
1628 return 1;
1629 else if (t.bitfield.disp16
1630 || t.bitfield.disp32
1631 || t.bitfield.disp32s)
1632 return 2;
1633 else
1634 return 0;
252b5132
RH
1635}
1636
1637static INLINE int
e3bb37b5 1638fits_in_signed_byte (offsetT num)
252b5132
RH
1639{
1640 return (num >= -128) && (num <= 127);
47926f60 1641}
252b5132
RH
1642
1643static INLINE int
e3bb37b5 1644fits_in_unsigned_byte (offsetT num)
252b5132
RH
1645{
1646 return (num & 0xff) == num;
47926f60 1647}
252b5132
RH
1648
1649static INLINE int
e3bb37b5 1650fits_in_unsigned_word (offsetT num)
252b5132
RH
1651{
1652 return (num & 0xffff) == num;
47926f60 1653}
252b5132
RH
1654
1655static INLINE int
e3bb37b5 1656fits_in_signed_word (offsetT num)
252b5132
RH
1657{
1658 return (-32768 <= num) && (num <= 32767);
47926f60 1659}
2a962e6d 1660
3e73aa7c 1661static INLINE int
e3bb37b5 1662fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH
1663{
1664#ifndef BFD64
1665 return 1;
1666#else
1667 return (!(((offsetT) -1 << 31) & num)
1668 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1669#endif
1670} /* fits_in_signed_long() */
2a962e6d 1671
3e73aa7c 1672static INLINE int
e3bb37b5 1673fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH
1674{
1675#ifndef BFD64
1676 return 1;
1677#else
1678 return (num & (((offsetT) 2 << 31) - 1)) == num;
1679#endif
1680} /* fits_in_unsigned_long() */
252b5132 1681
40fb9820 1682static i386_operand_type
e3bb37b5 1683smallest_imm_type (offsetT num)
252b5132 1684{
40fb9820
L
1685 i386_operand_type t;
1686
0dfbf9d7 1687 operand_type_set (&t, 0);
40fb9820
L
1688 t.bitfield.imm64 = 1;
1689
1690 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM
1691 {
1692 /* This code is disabled on the 486 because all the Imm1 forms
1693 in the opcode table are slower on the i486. They're the
1694 versions with the implicitly specified single-position
1695 displacement, which has another syntax if you really want to
1696 use that form. */
40fb9820
L
1697 t.bitfield.imm1 = 1;
1698 t.bitfield.imm8 = 1;
1699 t.bitfield.imm8s = 1;
1700 t.bitfield.imm16 = 1;
1701 t.bitfield.imm32 = 1;
1702 t.bitfield.imm32s = 1;
1703 }
1704 else if (fits_in_signed_byte (num))
1705 {
1706 t.bitfield.imm8 = 1;
1707 t.bitfield.imm8s = 1;
1708 t.bitfield.imm16 = 1;
1709 t.bitfield.imm32 = 1;
1710 t.bitfield.imm32s = 1;
1711 }
1712 else if (fits_in_unsigned_byte (num))
1713 {
1714 t.bitfield.imm8 = 1;
1715 t.bitfield.imm16 = 1;
1716 t.bitfield.imm32 = 1;
1717 t.bitfield.imm32s = 1;
1718 }
1719 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1720 {
1721 t.bitfield.imm16 = 1;
1722 t.bitfield.imm32 = 1;
1723 t.bitfield.imm32s = 1;
1724 }
1725 else if (fits_in_signed_long (num))
1726 {
1727 t.bitfield.imm32 = 1;
1728 t.bitfield.imm32s = 1;
1729 }
1730 else if (fits_in_unsigned_long (num))
1731 t.bitfield.imm32 = 1;
1732
1733 return t;
47926f60 1734}
252b5132 1735
847f7ad4 1736static offsetT
e3bb37b5 1737offset_in_range (offsetT val, int size)
847f7ad4 1738{
508866be 1739 addressT mask;
ba2adb93 1740
847f7ad4
AM
1741 switch (size)
1742 {
508866be
L
1743 case 1: mask = ((addressT) 1 << 8) - 1; break;
1744 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1745 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH
1746#ifdef BFD64
1747 case 8: mask = ((addressT) 2 << 63) - 1; break;
1748#endif
47926f60 1749 default: abort ();
847f7ad4
AM
1750 }
1751
ba2adb93 1752 /* If BFD64, sign extend val. */
3e73aa7c
JH
1753 if (!use_rela_relocations)
1754 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1755 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1756
47926f60 1757 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM
1758 {
1759 char buf1[40], buf2[40];
1760
1761 sprint_value (buf1, val);
1762 sprint_value (buf2, val & mask);
1763 as_warn (_("%s shortened to %s"), buf1, buf2);
1764 }
1765 return val & mask;
1766}
1767
252b5132
RH
1768/* Returns 0 if attempting to add a prefix where one from the same
1769 class already exists, 1 if non rep/repne added, 2 if rep/repne
1770 added. */
1771static int
e3bb37b5 1772add_prefix (unsigned int prefix)
252b5132
RH
1773{
1774 int ret = 1;
b1905489 1775 unsigned int q;
252b5132 1776
29b0f896
AM
1777 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1778 && flag_code == CODE_64BIT)
b1905489 1779 {
161a04f6
L
1780 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1781 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1782 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB
1783 ret = 0;
1784 q = REX_PREFIX;
1785 }
3e73aa7c 1786 else
b1905489
JB
1787 {
1788 switch (prefix)
1789 {
1790 default:
1791 abort ();
1792
1793 case CS_PREFIX_OPCODE:
1794 case DS_PREFIX_OPCODE:
1795 case ES_PREFIX_OPCODE:
1796 case FS_PREFIX_OPCODE:
1797 case GS_PREFIX_OPCODE:
1798 case SS_PREFIX_OPCODE:
1799 q = SEG_PREFIX;
1800 break;
1801
1802 case REPNE_PREFIX_OPCODE:
1803 case REPE_PREFIX_OPCODE:
1804 ret = 2;
1805 /* fall thru */
1806 case LOCK_PREFIX_OPCODE:
1807 q = LOCKREP_PREFIX;
1808 break;
1809
1810 case FWAIT_OPCODE:
1811 q = WAIT_PREFIX;
1812 break;
1813
1814 case ADDR_PREFIX_OPCODE:
1815 q = ADDR_PREFIX;
1816 break;
1817
1818 case DATA_PREFIX_OPCODE:
1819 q = DATA_PREFIX;
1820 break;
1821 }
1822 if (i.prefix[q] != 0)
1823 ret = 0;
1824 }
252b5132 1825
b1905489 1826 if (ret)
252b5132 1827 {
b1905489
JB
1828 if (!i.prefix[q])
1829 ++i.prefixes;
1830 i.prefix[q] |= prefix;
252b5132 1831 }
b1905489
JB
1832 else
1833 as_bad (_("same type of prefix used twice"));
252b5132 1834
252b5132
RH
1835 return ret;
1836}
1837
1838static void
e3bb37b5 1839set_code_flag (int value)
eecb386c 1840{
3e73aa7c 1841 flag_code = value;
40fb9820
L
1842 if (flag_code == CODE_64BIT)
1843 {
1844 cpu_arch_flags.bitfield.cpu64 = 1;
1845 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L
1846 }
1847 else
1848 {
1849 cpu_arch_flags.bitfield.cpu64 = 0;
1850 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L
1851 }
1852 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH
1853 {
1854 as_bad (_("64bit mode not supported on this CPU."));
1855 }
40fb9820 1856 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH
1857 {
1858 as_bad (_("32bit mode not supported on this CPU."));
1859 }
eecb386c
AM
1860 stackop_size = '\0';
1861}
1862
1863static void
e3bb37b5 1864set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1865{
3e73aa7c 1866 flag_code = new_code_flag;
40fb9820
L
1867 if (flag_code != CODE_16BIT)
1868 abort ();
1869 cpu_arch_flags.bitfield.cpu64 = 0;
1870 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1871 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH
1872}
1873
1874static void
e3bb37b5 1875set_intel_syntax (int syntax_flag)
252b5132
RH
1876{
1877 /* Find out if register prefixing is specified. */
1878 int ask_naked_reg = 0;
1879
1880 SKIP_WHITESPACE ();
29b0f896 1881 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH
1882 {
1883 char *string = input_line_pointer;
1884 int e = get_symbol_end ();
1885
47926f60 1886 if (strcmp (string, "prefix") == 0)
252b5132 1887 ask_naked_reg = 1;
47926f60 1888 else if (strcmp (string, "noprefix") == 0)
252b5132
RH
1889 ask_naked_reg = -1;
1890 else
d0b47220 1891 as_bad (_("bad argument to syntax directive."));
252b5132
RH
1892 *input_line_pointer = e;
1893 }
1894 demand_empty_rest_of_line ();
c3332e24 1895
252b5132
RH
1896 intel_syntax = syntax_flag;
1897
1898 if (ask_naked_reg == 0)
f86103b7
AM
1899 allow_naked_reg = (intel_syntax
1900 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH
1901 else
1902 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1903
ee86248c
JB
1904 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
1905
e4a3b5a4 1906 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1907 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1908 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH
1909}
1910
1efbbeb4
L
1911static void
1912set_intel_mnemonic (int mnemonic_flag)
1913{
e1d4d893 1914 intel_mnemonic = mnemonic_flag;
1efbbeb4
L
1915}
1916
db51cc60
L
1917static void
1918set_allow_index_reg (int flag)
1919{
1920 allow_index_reg = flag;
1921}
1922
cb19c032
L
1923static void
1924set_sse_check (int dummy ATTRIBUTE_UNUSED)
1925{
1926 SKIP_WHITESPACE ();
1927
1928 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1929 {
1930 char *string = input_line_pointer;
1931 int e = get_symbol_end ();
1932
1933 if (strcmp (string, "none") == 0)
1934 sse_check = sse_check_none;
1935 else if (strcmp (string, "warning") == 0)
1936 sse_check = sse_check_warning;
1937 else if (strcmp (string, "error") == 0)
1938 sse_check = sse_check_error;
1939 else
1940 as_bad (_("bad argument to sse_check directive."));
1941 *input_line_pointer = e;
1942 }
1943 else
1944 as_bad (_("missing argument for sse_check directive"));
1945
1946 demand_empty_rest_of_line ();
1947}
1948
e413e4e9 1949static void
e3bb37b5 1950set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1951{
47926f60 1952 SKIP_WHITESPACE ();
e413e4e9 1953
29b0f896 1954 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM
1955 {
1956 char *string = input_line_pointer;
1957 int e = get_symbol_end ();
9103f4f4 1958 unsigned int i;
40fb9820 1959 i386_cpu_flags flags;
e413e4e9 1960
9103f4f4 1961 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM
1962 {
1963 if (strcmp (string, cpu_arch[i].name) == 0)
1964 {
5c6af06e
JB
1965 if (*string != '.')
1966 {
1967 cpu_arch_name = cpu_arch[i].name;
1968 cpu_sub_arch_name = NULL;
40fb9820
L
1969 cpu_arch_flags = cpu_arch[i].flags;
1970 if (flag_code == CODE_64BIT)
1971 {
1972 cpu_arch_flags.bitfield.cpu64 = 1;
1973 cpu_arch_flags.bitfield.cpuno64 = 0;
1974 }
1975 else
1976 {
1977 cpu_arch_flags.bitfield.cpu64 = 0;
1978 cpu_arch_flags.bitfield.cpuno64 = 1;
1979 }
ccc9c027 1980 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1981 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L
1982 if (!cpu_arch_tune_set)
1983 {
1984 cpu_arch_tune = cpu_arch_isa;
1985 cpu_arch_tune_flags = cpu_arch_isa_flags;
1986 }
5c6af06e
JB
1987 break;
1988 }
40fb9820 1989
c6fb90c8
L
1990 flags = cpu_flags_or (cpu_arch_flags,
1991 cpu_arch[i].flags);
0dfbf9d7 1992 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1993 {
6305a203
L
1994 if (cpu_sub_arch_name)
1995 {
1996 char *name = cpu_sub_arch_name;
1997 cpu_sub_arch_name = concat (name,
1998 cpu_arch[i].name,
1bf57e9f 1999 (const char *) NULL);
6305a203
L
2000 free (name);
2001 }
2002 else
2003 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 2004 cpu_arch_flags = flags;
5c6af06e
JB
2005 }
2006 *input_line_pointer = e;
2007 demand_empty_rest_of_line ();
2008 return;
e413e4e9
AM
2009 }
2010 }
9103f4f4 2011 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM
2012 as_bad (_("no such architecture: `%s'"), string);
2013
2014 *input_line_pointer = e;
2015 }
2016 else
2017 as_bad (_("missing cpu architecture"));
2018
fddf5b5b
AM
2019 no_cond_jump_promotion = 0;
2020 if (*input_line_pointer == ','
29b0f896 2021 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM
2022 {
2023 char *string = ++input_line_pointer;
2024 int e = get_symbol_end ();
2025
2026 if (strcmp (string, "nojumps") == 0)
2027 no_cond_jump_promotion = 1;
2028 else if (strcmp (string, "jumps") == 0)
2029 ;
2030 else
2031 as_bad (_("no such architecture modifier: `%s'"), string);
2032
2033 *input_line_pointer = e;
2034 }
2035
e413e4e9
AM
2036 demand_empty_rest_of_line ();
2037}
2038
b9d79e03
JH
2039unsigned long
2040i386_mach ()
2041{
2042 if (!strcmp (default_arch, "x86_64"))
2043 return bfd_mach_x86_64;
2044 else if (!strcmp (default_arch, "i386"))
2045 return bfd_mach_i386_i386;
2046 else
2047 as_fatal (_("Unknown architecture"));
2048}
b9d79e03 2049\f
252b5132
RH
2050void
2051md_begin ()
2052{
2053 const char *hash_err;
2054
47926f60 2055 /* Initialize op_hash hash table. */
252b5132
RH
2056 op_hash = hash_new ();
2057
2058 {
29b0f896
AM
2059 const template *optab;
2060 templates *core_optab;
252b5132 2061
47926f60
KH
2062 /* Setup for loop. */
2063 optab = i386_optab;
252b5132
RH
2064 core_optab = (templates *) xmalloc (sizeof (templates));
2065 core_optab->start = optab;
2066
2067 while (1)
2068 {
2069 ++optab;
2070 if (optab->name == NULL
2071 || strcmp (optab->name, (optab - 1)->name) != 0)
2072 {
2073 /* different name --> ship out current template list;
47926f60 2074 add to hash table; & begin anew. */
252b5132
RH
2075 core_optab->end = optab;
2076 hash_err = hash_insert (op_hash,
2077 (optab - 1)->name,
5a49b8ac 2078 (void *) core_optab);
252b5132
RH
2079 if (hash_err)
2080 {
252b5132
RH
2081 as_fatal (_("Internal Error: Can't hash %s: %s"),
2082 (optab - 1)->name,
2083 hash_err);
2084 }
2085 if (optab->name == NULL)
2086 break;
2087 core_optab = (templates *) xmalloc (sizeof (templates));
2088 core_optab->start = optab;
2089 }
2090 }
2091 }
2092
47926f60 2093 /* Initialize reg_hash hash table. */
252b5132
RH
2094 reg_hash = hash_new ();
2095 {
29b0f896 2096 const reg_entry *regtab;
c3fe08fa 2097 unsigned int regtab_size = i386_regtab_size;
252b5132 2098
c3fe08fa 2099 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2100 {
5a49b8ac 2101 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2102 if (hash_err)
3e73aa7c
JH
2103 as_fatal (_("Internal Error: Can't hash %s: %s"),
2104 regtab->reg_name,
2105 hash_err);
252b5132
RH
2106 }
2107 }
2108
47926f60 2109 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2110 {
29b0f896
AM
2111 int c;
2112 char *p;
252b5132
RH
2113
2114 for (c = 0; c < 256; c++)
2115 {
3882b010 2116 if (ISDIGIT (c))
252b5132
RH
2117 {
2118 digit_chars[c] = c;
2119 mnemonic_chars[c] = c;
2120 register_chars[c] = c;
2121 operand_chars[c] = c;
2122 }
3882b010 2123 else if (ISLOWER (c))
252b5132
RH
2124 {
2125 mnemonic_chars[c] = c;
2126 register_chars[c] = c;
2127 operand_chars[c] = c;
2128 }
3882b010 2129 else if (ISUPPER (c))
252b5132 2130 {
3882b010 2131 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH
2132 register_chars[c] = mnemonic_chars[c];
2133 operand_chars[c] = c;
2134 }
2135
3882b010 2136 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH
2137 identifier_chars[c] = c;
2138 else if (c >= 128)
2139 {
2140 identifier_chars[c] = c;
2141 operand_chars[c] = c;
2142 }
2143 }
2144
2145#ifdef LEX_AT
2146 identifier_chars['@'] = '@';
32137342
NC
2147#endif
2148#ifdef LEX_QM
2149 identifier_chars['?'] = '?';
2150 operand_chars['?'] = '?';
252b5132 2151#endif
252b5132 2152 digit_chars['-'] = '-';
c0f3af97 2153 mnemonic_chars['_'] = '_';
791fe849 2154 mnemonic_chars['-'] = '-';
0003779b 2155 mnemonic_chars['.'] = '.';
252b5132
RH
2156 identifier_chars['_'] = '_';
2157 identifier_chars['.'] = '.';
2158
2159 for (p = operand_special_chars; *p != '\0'; p++)
2160 operand_chars[(unsigned char) *p] = *p;
2161 }
2162
2163#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2164 if (IS_ELF)
252b5132
RH
2165 {
2166 record_alignment (text_section, 2);
2167 record_alignment (data_section, 2);
2168 record_alignment (bss_section, 2);
2169 }
2170#endif
a4447b93
RH
2171
2172 if (flag_code == CODE_64BIT)
2173 {
2174 x86_dwarf2_return_column = 16;
2175 x86_cie_data_alignment = -8;
2176 }
2177 else
2178 {
2179 x86_dwarf2_return_column = 8;
2180 x86_cie_data_alignment = -4;
2181 }
252b5132
RH
2182}
2183
2184void
e3bb37b5 2185i386_print_statistics (FILE *file)
252b5132
RH
2186{
2187 hash_print_statistics (file, "i386 opcode", op_hash);
2188 hash_print_statistics (file, "i386 register", reg_hash);
2189}
2190\f
252b5132
RH
2191#ifdef DEBUG386
2192
ce8a8b2f 2193/* Debugging routines for md_assemble. */
e3bb37b5 2194static void pte (template *);
40fb9820 2195static void pt (i386_operand_type);
e3bb37b5
L
2196static void pe (expressionS *);
2197static void ps (symbolS *);
252b5132
RH
2198
2199static void
e3bb37b5 2200pi (char *line, i386_insn *x)
252b5132 2201{
09f131f2 2202 unsigned int i;
252b5132
RH
2203
2204 fprintf (stdout, "%s: template ", line);
2205 pte (&x->tm);
09f131f2
JH
2206 fprintf (stdout, " address: base %s index %s scale %x\n",
2207 x->base_reg ? x->base_reg->reg_name : "none",
2208 x->index_reg ? x->index_reg->reg_name : "none",
2209 x->log2_scale_factor);
2210 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2211 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH
2212 fprintf (stdout, " sib: base %x index %x scale %x\n",
2213 x->sib.base, x->sib.index, x->sib.scale);
2214 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L
2215 (x->rex & REX_W) != 0,
2216 (x->rex & REX_R) != 0,
2217 (x->rex & REX_X) != 0,
2218 (x->rex & REX_B) != 0);
85f10a01
MM
2219 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2220 x->drex.reg, x->drex.rex);
252b5132
RH
2221 for (i = 0; i < x->operands; i++)
2222 {
2223 fprintf (stdout, " #%d: ", i + 1);
2224 pt (x->types[i]);
2225 fprintf (stdout, "\n");
40fb9820
L
2226 if (x->types[i].bitfield.reg8
2227 || x->types[i].bitfield.reg16
2228 || x->types[i].bitfield.reg32
2229 || x->types[i].bitfield.reg64
2230 || x->types[i].bitfield.regmmx
2231 || x->types[i].bitfield.regxmm
c0f3af97 2232 || x->types[i].bitfield.regymm
40fb9820
L
2233 || x->types[i].bitfield.sreg2
2234 || x->types[i].bitfield.sreg3
2235 || x->types[i].bitfield.control
2236 || x->types[i].bitfield.debug
2237 || x->types[i].bitfield.test)
520dc8e8 2238 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2239 if (operand_type_check (x->types[i], imm))
520dc8e8 2240 pe (x->op[i].imms);
40fb9820 2241 if (operand_type_check (x->types[i], disp))
520dc8e8 2242 pe (x->op[i].disps);
252b5132
RH
2243 }
2244}
2245
2246static void
e3bb37b5 2247pte (template *t)
252b5132 2248{
09f131f2 2249 unsigned int i;
252b5132 2250 fprintf (stdout, " %d operands ", t->operands);
47926f60 2251 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH
2252 if (t->extension_opcode != None)
2253 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2254 if (t->opcode_modifier.d)
252b5132 2255 fprintf (stdout, "D");
40fb9820 2256 if (t->opcode_modifier.w)
252b5132
RH
2257 fprintf (stdout, "W");
2258 fprintf (stdout, "\n");
2259 for (i = 0; i < t->operands; i++)
2260 {
2261 fprintf (stdout, " #%d type ", i + 1);
2262 pt (t->operand_types[i]);
2263 fprintf (stdout, "\n");
2264 }
2265}
2266
2267static void
e3bb37b5 2268pe (expressionS *e)
252b5132 2269{
24eab124 2270 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM
2271 fprintf (stdout, " add_number %ld (%lx)\n",
2272 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH
2273 if (e->X_add_symbol)
2274 {
2275 fprintf (stdout, " add_symbol ");
2276 ps (e->X_add_symbol);
2277 fprintf (stdout, "\n");
2278 }
2279 if (e->X_op_symbol)
2280 {
2281 fprintf (stdout, " op_symbol ");
2282 ps (e->X_op_symbol);
2283 fprintf (stdout, "\n");
2284 }
2285}
2286
2287static void
e3bb37b5 2288ps (symbolS *s)
252b5132
RH
2289{
2290 fprintf (stdout, "%s type %s%s",
2291 S_GET_NAME (s),
2292 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2293 segment_name (S_GET_SEGMENT (s)));
2294}
2295
7b81dfbb 2296static struct type_name
252b5132 2297 {
40fb9820
L
2298 i386_operand_type mask;
2299 const char *name;
252b5132 2300 }
7b81dfbb 2301const type_names[] =
252b5132 2302{
40fb9820
L
2303 { OPERAND_TYPE_REG8, "r8" },
2304 { OPERAND_TYPE_REG16, "r16" },
2305 { OPERAND_TYPE_REG32, "r32" },
2306 { OPERAND_TYPE_REG64, "r64" },
2307 { OPERAND_TYPE_IMM8, "i8" },
2308 { OPERAND_TYPE_IMM8, "i8s" },
2309 { OPERAND_TYPE_IMM16, "i16" },
2310 { OPERAND_TYPE_IMM32, "i32" },
2311 { OPERAND_TYPE_IMM32S, "i32s" },
2312 { OPERAND_TYPE_IMM64, "i64" },
2313 { OPERAND_TYPE_IMM1, "i1" },
2314 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2315 { OPERAND_TYPE_DISP8, "d8" },
2316 { OPERAND_TYPE_DISP16, "d16" },
2317 { OPERAND_TYPE_DISP32, "d32" },
2318 { OPERAND_TYPE_DISP32S, "d32s" },
2319 { OPERAND_TYPE_DISP64, "d64" },
2320 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2321 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2322 { OPERAND_TYPE_CONTROL, "control reg" },
2323 { OPERAND_TYPE_TEST, "test reg" },
2324 { OPERAND_TYPE_DEBUG, "debug reg" },
2325 { OPERAND_TYPE_FLOATREG, "FReg" },
2326 { OPERAND_TYPE_FLOATACC, "FAcc" },
2327 { OPERAND_TYPE_SREG2, "SReg2" },
2328 { OPERAND_TYPE_SREG3, "SReg3" },
2329 { OPERAND_TYPE_ACC, "Acc" },
2330 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2331 { OPERAND_TYPE_REGMMX, "rMMX" },
2332 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2333 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2334 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH
2335};
2336
2337static void
40fb9820 2338pt (i386_operand_type t)
252b5132 2339{
40fb9820 2340 unsigned int j;
c6fb90c8 2341 i386_operand_type a;
252b5132 2342
40fb9820 2343 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L
2344 {
2345 a = operand_type_and (t, type_names[j].mask);
0349dc08 2346 if (!operand_type_all_zero (&a))
c6fb90c8
L
2347 fprintf (stdout, "%s, ", type_names[j].name);
2348 }
252b5132
RH
2349 fflush (stdout);
2350}
2351
2352#endif /* DEBUG386 */
2353\f
252b5132 2354static bfd_reloc_code_real_type
3956db08 2355reloc (unsigned int size,
64e74474
AM
2356 int pcrel,
2357 int sign,
2358 bfd_reloc_code_real_type other)
252b5132 2359{
47926f60 2360 if (other != NO_RELOC)
3956db08
JB
2361 {
2362 reloc_howto_type *reloc;
2363
2364 if (size == 8)
2365 switch (other)
2366 {
64e74474
AM
2367 case BFD_RELOC_X86_64_GOT32:
2368 return BFD_RELOC_X86_64_GOT64;
2369 break;
2370 case BFD_RELOC_X86_64_PLTOFF64:
2371 return BFD_RELOC_X86_64_PLTOFF64;
2372 break;
2373 case BFD_RELOC_X86_64_GOTPC32:
2374 other = BFD_RELOC_X86_64_GOTPC64;
2375 break;
2376 case BFD_RELOC_X86_64_GOTPCREL:
2377 other = BFD_RELOC_X86_64_GOTPCREL64;
2378 break;
2379 case BFD_RELOC_X86_64_TPOFF32:
2380 other = BFD_RELOC_X86_64_TPOFF64;
2381 break;
2382 case BFD_RELOC_X86_64_DTPOFF32:
2383 other = BFD_RELOC_X86_64_DTPOFF64;
2384 break;
2385 default:
2386 break;
3956db08 2387 }
e05278af
JB
2388
2389 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2390 if (size == 4 && flag_code != CODE_64BIT)
2391 sign = -1;
2392
3956db08
JB
2393 reloc = bfd_reloc_type_lookup (stdoutput, other);
2394 if (!reloc)
2395 as_bad (_("unknown relocation (%u)"), other);
2396 else if (size != bfd_get_reloc_size (reloc))
2397 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2398 bfd_get_reloc_size (reloc),
2399 size);
2400 else if (pcrel && !reloc->pc_relative)
2401 as_bad (_("non-pc-relative relocation for pc-relative field"));
2402 else if ((reloc->complain_on_overflow == complain_overflow_signed
2403 && !sign)
2404 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2405 && sign > 0))
3956db08
JB
2406 as_bad (_("relocated field and relocation type differ in signedness"));
2407 else
2408 return other;
2409 return NO_RELOC;
2410 }
252b5132
RH
2411
2412 if (pcrel)
2413 {
3e73aa7c 2414 if (!sign)
3956db08 2415 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH
2416 switch (size)
2417 {
2418 case 1: return BFD_RELOC_8_PCREL;
2419 case 2: return BFD_RELOC_16_PCREL;
2420 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2421 case 8: return BFD_RELOC_64_PCREL;
252b5132 2422 }
3956db08 2423 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH
2424 }
2425 else
2426 {
3956db08 2427 if (sign > 0)
e5cb08ac 2428 switch (size)
3e73aa7c
JH
2429 {
2430 case 4: return BFD_RELOC_X86_64_32S;
2431 }
2432 else
2433 switch (size)
2434 {
2435 case 1: return BFD_RELOC_8;
2436 case 2: return BFD_RELOC_16;
2437 case 4: return BFD_RELOC_32;
2438 case 8: return BFD_RELOC_64;
2439 }
3956db08
JB
2440 as_bad (_("cannot do %s %u byte relocation"),
2441 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH
2442 }
2443
0cc9e1d3 2444 return NO_RELOC;
252b5132
RH
2445}
2446
47926f60
KH
2447/* Here we decide which fixups can be adjusted to make them relative to
2448 the beginning of the section instead of the symbol. Basically we need
2449 to make sure that the dynamic relocations are done correctly, so in
2450 some cases we force the original symbol to be used. */
2451
252b5132 2452int
e3bb37b5 2453tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2454{
6d249963 2455#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2456 if (!IS_ELF)
31312f95
AM
2457 return 1;
2458
a161fe53
AM
2459 /* Don't adjust pc-relative references to merge sections in 64-bit
2460 mode. */
2461 if (use_rela_relocations
2462 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2463 && fixP->fx_pcrel)
252b5132 2464 return 0;
31312f95 2465
8d01d9a9
AJ
2466 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2467 and changed later by validate_fix. */
2468 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2469 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2470 return 0;
2471
ce8a8b2f 2472 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH
2473 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2474 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2475 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ
2476 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2477 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2478 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2479 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ
2480 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2481 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ
2482 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2483 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO
2484 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2485 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH
2486 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2487 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2488 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ
2489 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2490 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2491 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2492 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ
2493 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2494 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB
2495 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2496 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO
2497 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2498 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH
2499 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2500 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2501 return 0;
31312f95 2502#endif
252b5132
RH
2503 return 1;
2504}
252b5132 2505
b4cac588 2506static int
e3bb37b5 2507intel_float_operand (const char *mnemonic)
252b5132 2508{
9306ca4a
JB
2509 /* Note that the value returned is meaningful only for opcodes with (memory)
2510 operands, hence the code here is free to improperly handle opcodes that
2511 have no operands (for better performance and smaller code). */
2512
2513 if (mnemonic[0] != 'f')
2514 return 0; /* non-math */
2515
2516 switch (mnemonic[1])
2517 {
2518 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2519 the fs segment override prefix not currently handled because no
2520 call path can make opcodes without operands get here */
2521 case 'i':
2522 return 2 /* integer op */;
2523 case 'l':
2524 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2525 return 3; /* fldcw/fldenv */
2526 break;
2527 case 'n':
2528 if (mnemonic[2] != 'o' /* fnop */)
2529 return 3; /* non-waiting control op */
2530 break;
2531 case 'r':
2532 if (mnemonic[2] == 's')
2533 return 3; /* frstor/frstpm */
2534 break;
2535 case 's':
2536 if (mnemonic[2] == 'a')
2537 return 3; /* fsave */
2538 if (mnemonic[2] == 't')
2539 {
2540 switch (mnemonic[3])
2541 {
2542 case 'c': /* fstcw */
2543 case 'd': /* fstdw */
2544 case 'e': /* fstenv */
2545 case 's': /* fsts[gw] */
2546 return 3;
2547 }
2548 }
2549 break;
2550 case 'x':
2551 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2552 return 0; /* fxsave/fxrstor are not really math ops */
2553 break;
2554 }
252b5132 2555
9306ca4a 2556 return 1;
252b5132
RH
2557}
2558
c0f3af97
L
2559/* Build the VEX prefix. */
2560
2561static void
fa99fab2 2562build_vex_prefix (const template *t)
c0f3af97
L
2563{
2564 unsigned int register_specifier;
2565 unsigned int implied_prefix;
2566 unsigned int vector_length;
2567
2568 /* Check register specifier. */
2569 if (i.vex.register_specifier)
2570 {
2571 register_specifier = i.vex.register_specifier->reg_num;
2572 if ((i.vex.register_specifier->reg_flags & RegRex))
2573 register_specifier += 8;
2574 register_specifier = ~register_specifier & 0xf;
2575 }
2576 else
2577 register_specifier = 0xf;
2578
fa99fab2
L
2579 /* Use 2-byte VEX prefix by swappping destination and source
2580 operand. */
2581 if (!i.swap_operand
2582 && i.operands == i.reg_operands
2583 && i.tm.opcode_modifier.vex0f
2584 && i.tm.opcode_modifier.s
2585 && i.rex == REX_B)
2586 {
2587 unsigned int xchg = i.operands - 1;
2588 union i386_op temp_op;
2589 i386_operand_type temp_type;
2590
2591 temp_type = i.types[xchg];
2592 i.types[xchg] = i.types[0];
2593 i.types[0] = temp_type;
2594 temp_op = i.op[xchg];
2595 i.op[xchg] = i.op[0];
2596 i.op[0] = temp_op;
2597
2598 assert (i.rm.mode == 3);
2599
2600 i.rex = REX_R;
2601 xchg = i.rm.regmem;
2602 i.rm.regmem = i.rm.reg;
2603 i.rm.reg = xchg;
2604
2605 /* Use the next insn. */
2606 i.tm = t[1];
2607 }
2608
c0f3af97
L
2609 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2610
2611 switch ((i.tm.base_opcode >> 8) & 0xff)
2612 {
2613 case 0:
2614 implied_prefix = 0;
2615 break;
2616 case DATA_PREFIX_OPCODE:
2617 implied_prefix = 1;
2618 break;
2619 case REPE_PREFIX_OPCODE:
2620 implied_prefix = 2;
2621 break;
2622 case REPNE_PREFIX_OPCODE:
2623 implied_prefix = 3;
2624 break;
2625 default:
2626 abort ();
2627 }
2628
2629 /* Use 2-byte VEX prefix if possible. */
2630 if (i.tm.opcode_modifier.vex0f
2631 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2632 {
2633 /* 2-byte VEX prefix. */
2634 unsigned int r;
2635
2636 i.vex.length = 2;
2637 i.vex.bytes[0] = 0xc5;
2638
2639 /* Check the REX.R bit. */
2640 r = (i.rex & REX_R) ? 0 : 1;
2641 i.vex.bytes[1] = (r << 7
2642 | register_specifier << 3
2643 | vector_length << 2
2644 | implied_prefix);
2645 }
2646 else
2647 {
2648 /* 3-byte VEX prefix. */
2649 unsigned int m, w;
2650
2651 if (i.tm.opcode_modifier.vex0f)
2652 m = 0x1;
2653 else if (i.tm.opcode_modifier.vex0f38)
2654 m = 0x2;
2655 else if (i.tm.opcode_modifier.vex0f3a)
2656 m = 0x3;
2657 else
2658 abort ();
2659
2660 i.vex.length = 3;
2661 i.vex.bytes[0] = 0xc4;
2662
2663 /* The high 3 bits of the second VEX byte are 1's compliment
2664 of RXB bits from REX. */
2665 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2666
2667 /* Check the REX.W bit. */
2668 w = (i.rex & REX_W) ? 1 : 0;
2669 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2670 {
2671 if (w)
2672 abort ();
2673
2674 if (i.tm.opcode_modifier.vexw1)
2675 w = 1;
2676 }
2677
2678 i.vex.bytes[2] = (w << 7
2679 | register_specifier << 3
2680 | vector_length << 2
2681 | implied_prefix);
2682 }
2683}
2684
65da13b5
L
2685static void
2686process_immext (void)
2687{
2688 expressionS *exp;
2689
2690 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2691 {
1fed0ba1
L
2692 /* SSE3 Instructions have the fixed operands with an opcode
2693 suffix which is coded in the same place as an 8-bit immediate
2694 field would be. Here we check those operands and remove them
2695 afterwards. */
65da13b5
L
2696 unsigned int x;
2697
2698 for (x = 0; x < i.operands; x++)
2699 if (i.op[x].regs->reg_num != x)
2700 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L
2701 register_prefix, i.op[x].regs->reg_name, x + 1,
2702 i.tm.name);
2703
2704 i.operands = 0;
65da13b5
L
2705 }
2706
c0f3af97 2707 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L
2708 which is coded in the same place as an 8-bit immediate field
2709 would be. Here we fake an 8-bit immediate operand from the
2710 opcode suffix stored in tm.extension_opcode.
2711
c0f3af97
L
2712 SSE5 and AVX instructions also use this encoding, for some of
2713 3 argument instructions. */
65da13b5
L
2714
2715 assert (i.imm_operands == 0
2716 && (i.operands <= 2
2717 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L
2718 && i.operands <= 3)
2719 || (i.tm.opcode_modifier.vex
2720 && i.operands <= 4)));
65da13b5
L
2721
2722 exp = &im_expressions[i.imm_operands++];
2723 i.op[i.operands].imms = exp;
2724 i.types[i.operands] = imm8;
2725 i.operands++;
2726 exp->X_op = O_constant;
2727 exp->X_add_number = i.tm.extension_opcode;
2728 i.tm.extension_opcode = None;
2729}
2730
252b5132
RH
2731/* This is the guts of the machine-dependent assembler. LINE points to a
2732 machine dependent instruction. This function is supposed to emit
2733 the frags/bytes it assembles to. */
2734
2735void
65da13b5 2736md_assemble (char *line)
252b5132 2737{
40fb9820 2738 unsigned int j;
252b5132 2739 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2740 const template *t;
252b5132 2741
47926f60 2742 /* Initialize globals. */
252b5132
RH
2743 memset (&i, '\0', sizeof (i));
2744 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2745 i.reloc[j] = NO_RELOC;
252b5132
RH
2746 memset (disp_expressions, '\0', sizeof (disp_expressions));
2747 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2748 save_stack_p = save_stack;
252b5132
RH
2749
2750 /* First parse an instruction mnemonic & call i386_operand for the operands.
2751 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2752 start of a (possibly prefixed) mnemonic. */
252b5132 2753
29b0f896
AM
2754 line = parse_insn (line, mnemonic);
2755 if (line == NULL)
2756 return;
252b5132 2757
29b0f896 2758 line = parse_operands (line, mnemonic);
ee86248c 2759 this_operand = -1;
29b0f896
AM
2760 if (line == NULL)
2761 return;
252b5132 2762
29b0f896
AM
2763 /* Now we've parsed the mnemonic into a set of templates, and have the
2764 operands at hand. */
2765
2766 /* All intel opcodes have reversed operands except for "bound" and
2767 "enter". We also don't reverse intersegment "jmp" and "call"
2768 instructions with 2 immediate operands so that the immediate segment
050dfa73 2769 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L
2770 if (intel_syntax
2771 && i.operands > 1
29b0f896 2772 && (strcmp (mnemonic, "bound") != 0)
30123838 2773 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L
2774 && !(operand_type_check (i.types[0], imm)
2775 && operand_type_check (i.types[1], imm)))
29b0f896
AM
2776 swap_operands ();
2777
ec56d5c0
JB
2778 /* The order of the immediates should be reversed
2779 for 2 immediates extrq and insertq instructions */
2780 if (i.imm_operands == 2
2781 && (strcmp (mnemonic, "extrq") == 0
2782 || strcmp (mnemonic, "insertq") == 0))
2783 swap_2_operands (0, 1);
2784
29b0f896
AM
2785 if (i.imm_operands)
2786 optimize_imm ();
2787
b300c311
L
2788 /* Don't optimize displacement for movabs since it only takes 64bit
2789 displacement. */
2790 if (i.disp_operands
2791 && (flag_code != CODE_64BIT
2792 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM
2793 optimize_disp ();
2794
2795 /* Next, we find a template that matches the given insn,
2796 making sure the overlap of the given operands types is consistent
2797 with the template operand types. */
252b5132 2798
fa99fab2 2799 if (!(t = match_template ()))
29b0f896 2800 return;
252b5132 2801
daf50ae7 2802 if (sse_check != sse_check_none
81f8a913 2803 && !i.tm.opcode_modifier.noavx
daf50ae7
L
2804 && (i.tm.cpu_flags.bitfield.cpusse
2805 || i.tm.cpu_flags.bitfield.cpusse2
2806 || i.tm.cpu_flags.bitfield.cpusse3
2807 || i.tm.cpu_flags.bitfield.cpussse3
2808 || i.tm.cpu_flags.bitfield.cpusse4_1
2809 || i.tm.cpu_flags.bitfield.cpusse4_2))
2810 {
2811 (sse_check == sse_check_warning
2812 ? as_warn
2813 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2814 }
2815
321fd21e
L
2816 /* Zap movzx and movsx suffix. The suffix has been set from
2817 "word ptr" or "byte ptr" on the source operand in Intel syntax
2818 or extracted from mnemonic in AT&T syntax. But we'll use
2819 the destination register to choose the suffix for encoding. */
2820 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2821 {
321fd21e
L
2822 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2823 there is no suffix, the default will be byte extension. */
2824 if (i.reg_operands != 2
2825 && !i.suffix
2826 && intel_syntax)
2827 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2828
2829 i.suffix = 0;
cd61ebfe 2830 }
24eab124 2831
40fb9820 2832 if (i.tm.opcode_modifier.fwait)
29b0f896
AM
2833 if (!add_prefix (FWAIT_OPCODE))
2834 return;
252b5132 2835
29b0f896 2836 /* Check string instruction segment overrides. */
40fb9820 2837 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM
2838 {
2839 if (!check_string ())
5dd0794d 2840 return;
fc0763e6 2841 i.disp_operands = 0;
29b0f896 2842 }
5dd0794d 2843
29b0f896
AM
2844 if (!process_suffix ())
2845 return;
e413e4e9 2846
29b0f896
AM
2847 /* Make still unresolved immediate matches conform to size of immediate
2848 given in i.suffix. */
2849 if (!finalize_imm ())
2850 return;
252b5132 2851
40fb9820 2852 if (i.types[0].bitfield.imm1)
29b0f896 2853 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2854
40fb9820 2855 for (j = 0; j < 3; j++)
c6fb90c8
L
2856 if (i.types[j].bitfield.inoutportreg
2857 || i.types[j].bitfield.shiftcount
2858 || i.types[j].bitfield.acc
2859 || i.types[j].bitfield.floatacc)
40fb9820
L
2860 i.reg_operands--;
2861
c0f3af97
L
2862 /* ImmExt should be processed after SSE2AVX. */
2863 if (!i.tm.opcode_modifier.sse2avx
2864 && i.tm.opcode_modifier.immext)
65da13b5 2865 process_immext ();
252b5132 2866
29b0f896
AM
2867 /* For insns with operands there are more diddles to do to the opcode. */
2868 if (i.operands)
2869 {
2870 if (!process_operands ())
2871 return;
2872 }
40fb9820 2873 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM
2874 {
2875 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2876 as_warn (_("translating to `%sp'"), i.tm.name);
2877 }
252b5132 2878
c0f3af97 2879 if (i.tm.opcode_modifier.vex)
fa99fab2 2880 build_vex_prefix (t);
c0f3af97 2881
29b0f896
AM
2882 /* Handle conversion of 'int $3' --> special int3 insn. */
2883 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2884 {
2885 i.tm.base_opcode = INT3_OPCODE;
2886 i.imm_operands = 0;
2887 }
252b5132 2888
40fb9820
L
2889 if ((i.tm.opcode_modifier.jump
2890 || i.tm.opcode_modifier.jumpbyte
2891 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM
2892 && i.op[0].disps->X_op == O_constant)
2893 {
2894 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2895 the absolute address given by the constant. Since ix86 jumps and
2896 calls are pc relative, we need to generate a reloc. */
2897 i.op[0].disps->X_add_symbol = &abs_symbol;
2898 i.op[0].disps->X_op = O_symbol;
2899 }
252b5132 2900
40fb9820 2901 if (i.tm.opcode_modifier.rex64)
161a04f6 2902 i.rex |= REX_W;
252b5132 2903
29b0f896
AM
2904 /* For 8 bit registers we need an empty rex prefix. Also if the
2905 instruction already has a prefix, we need to convert old
2906 registers to new ones. */
773f551c 2907
40fb9820 2908 if ((i.types[0].bitfield.reg8
29b0f896 2909 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2910 || (i.types[1].bitfield.reg8
29b0f896 2911 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L
2912 || ((i.types[0].bitfield.reg8
2913 || i.types[1].bitfield.reg8)
29b0f896
AM
2914 && i.rex != 0))
2915 {
2916 int x;
726c5dcd 2917
29b0f896
AM
2918 i.rex |= REX_OPCODE;
2919 for (x = 0; x < 2; x++)
2920 {
2921 /* Look for 8 bit operand that uses old registers. */
40fb9820 2922 if (i.types[x].bitfield.reg8
29b0f896 2923 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2924 {
29b0f896
AM
2925 /* In case it is "hi" register, give up. */
2926 if (i.op[x].regs->reg_num > 3)
a540244d 2927 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2928 "instruction requiring REX prefix."),
a540244d 2929 register_prefix, i.op[x].regs->reg_name);
773f551c 2930
29b0f896
AM
2931 /* Otherwise it is equivalent to the extended register.
2932 Since the encoding doesn't change this is merely
2933 cosmetic cleanup for debug output. */
2934
2935 i.op[x].regs = i.op[x].regs + 8;
773f551c 2936 }
29b0f896
AM
2937 }
2938 }
773f551c 2939
85f10a01
MM
2940 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2941 REX prefix. */
2942 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2943 {
2944 i.drex.rex = i.rex;
2945 i.rex = 0;
2946 }
2947 else if (i.rex != 0)
29b0f896
AM
2948 add_prefix (REX_OPCODE | i.rex);
2949
2950 /* We are ready to output the insn. */
2951 output_insn ();
2952}
2953
2954static char *
e3bb37b5 2955parse_insn (char *line, char *mnemonic)
29b0f896
AM
2956{
2957 char *l = line;
2958 char *token_start = l;
2959 char *mnem_p;
5c6af06e
JB
2960 int supported;
2961 const template *t;
b6169b20 2962 char *dot_p = NULL;
29b0f896
AM
2963
2964 /* Non-zero if we found a prefix only acceptable with string insns. */
2965 const char *expecting_string_instruction = NULL;
45288df1 2966
29b0f896
AM
2967 while (1)
2968 {
2969 mnem_p = mnemonic;
2970 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2971 {
b6169b20
L
2972 if (*mnem_p == '.')
2973 dot_p = mnem_p;
29b0f896
AM
2974 mnem_p++;
2975 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2976 {
29b0f896
AM
2977 as_bad (_("no such instruction: `%s'"), token_start);
2978 return NULL;
2979 }
2980 l++;
2981 }
2982 if (!is_space_char (*l)
2983 && *l != END_OF_INSN
e44823cf
JB
2984 && (intel_syntax
2985 || (*l != PREFIX_SEPARATOR
2986 && *l != ',')))
29b0f896
AM
2987 {
2988 as_bad (_("invalid character %s in mnemonic"),
2989 output_invalid (*l));
2990 return NULL;
2991 }
2992 if (token_start == l)
2993 {
e44823cf 2994 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM
2995 as_bad (_("expecting prefix; got nothing"));
2996 else
2997 as_bad (_("expecting mnemonic; got nothing"));
2998 return NULL;
2999 }
45288df1 3000
29b0f896
AM
3001 /* Look up instruction (or prefix) via hash table. */
3002 current_templates = hash_find (op_hash, mnemonic);
47926f60 3003
29b0f896
AM
3004 if (*l != END_OF_INSN
3005 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3006 && current_templates
40fb9820 3007 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3008 {
c6fb90c8 3009 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB
3010 {
3011 as_bad ((flag_code != CODE_64BIT
3012 ? _("`%s' is only supported in 64-bit mode")
3013 : _("`%s' is not supported in 64-bit mode")),
3014 current_templates->start->name);
3015 return NULL;
3016 }
29b0f896
AM
3017 /* If we are in 16-bit mode, do not allow addr16 or data16.
3018 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L
3019 if ((current_templates->start->opcode_modifier.size16
3020 || current_templates->start->opcode_modifier.size32)
29b0f896 3021 && flag_code != CODE_64BIT
40fb9820 3022 && (current_templates->start->opcode_modifier.size32
29b0f896
AM
3023 ^ (flag_code == CODE_16BIT)))
3024 {
3025 as_bad (_("redundant %s prefix"),
3026 current_templates->start->name);
3027 return NULL;
45288df1 3028 }
29b0f896
AM
3029 /* Add prefix, checking for repeated prefixes. */
3030 switch (add_prefix (current_templates->start->base_opcode))
3031 {
3032 case 0:
3033 return NULL;
3034 case 2:
3035 expecting_string_instruction = current_templates->start->name;
3036 break;
3037 }
3038 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3039 token_start = ++l;
3040 }
3041 else
3042 break;
3043 }
45288df1 3044
30a55f88 3045 if (!current_templates)
b6169b20 3046 {
30a55f88
L
3047 /* Check if we should swap operand in encoding. */
3048 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3049 i.swap_operand = 1;
3050 else
3051 goto check_suffix;
3052 mnem_p = dot_p;
3053 *dot_p = '\0';
3054 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L
3055 }
3056
29b0f896
AM
3057 if (!current_templates)
3058 {
b6169b20 3059check_suffix:
29b0f896
AM
3060 /* See if we can get a match by trimming off a suffix. */
3061 switch (mnem_p[-1])
3062 {
3063 case WORD_MNEM_SUFFIX:
9306ca4a
JB
3064 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3065 i.suffix = SHORT_MNEM_SUFFIX;
3066 else
29b0f896
AM
3067 case BYTE_MNEM_SUFFIX:
3068 case QWORD_MNEM_SUFFIX:
3069 i.suffix = mnem_p[-1];
3070 mnem_p[-1] = '\0';
3071 current_templates = hash_find (op_hash, mnemonic);
3072 break;
3073 case SHORT_MNEM_SUFFIX:
3074 case LONG_MNEM_SUFFIX:
3075 if (!intel_syntax)
3076 {
3077 i.suffix = mnem_p[-1];
3078 mnem_p[-1] = '\0';
3079 current_templates = hash_find (op_hash, mnemonic);
3080 }
3081 break;
252b5132 3082
29b0f896
AM
3083 /* Intel Syntax. */
3084 case 'd':
3085 if (intel_syntax)
3086 {
9306ca4a 3087 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM
3088 i.suffix = SHORT_MNEM_SUFFIX;
3089 else
3090 i.suffix = LONG_MNEM_SUFFIX;
3091 mnem_p[-1] = '\0';
3092 current_templates = hash_find (op_hash, mnemonic);
3093 }
3094 break;
3095 }
3096 if (!current_templates)
3097 {
3098 as_bad (_("no such instruction: `%s'"), token_start);
3099 return NULL;
3100 }
3101 }
252b5132 3102
40fb9820
L
3103 if (current_templates->start->opcode_modifier.jump
3104 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM
3105 {
3106 /* Check for a branch hint. We allow ",pt" and ",pn" for
3107 predict taken and predict not taken respectively.
3108 I'm not sure that branch hints actually do anything on loop
3109 and jcxz insns (JumpByte) for current Pentium4 chips. They
3110 may work in the future and it doesn't hurt to accept them
3111 now. */
3112 if (l[0] == ',' && l[1] == 'p')
3113 {
3114 if (l[2] == 't')
3115 {
3116 if (!add_prefix (DS_PREFIX_OPCODE))
3117 return NULL;
3118 l += 3;
3119 }
3120 else if (l[2] == 'n')
3121 {
3122 if (!add_prefix (CS_PREFIX_OPCODE))
3123 return NULL;
3124 l += 3;
3125 }
3126 }
3127 }
3128 /* Any other comma loses. */
3129 if (*l == ',')
3130 {
3131 as_bad (_("invalid character %s in mnemonic"),
3132 output_invalid (*l));
3133 return NULL;
3134 }
252b5132 3135
29b0f896 3136 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB
3137 supported = 0;
3138 for (t = current_templates->start; t < current_templates->end; ++t)
3139 {
c0f3af97
L
3140 supported |= cpu_flags_match (t);
3141 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3142 goto skip;
5c6af06e 3143 }
3629bb00 3144
c0f3af97 3145 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB
3146 {
3147 as_bad (flag_code == CODE_64BIT
3148 ? _("`%s' is not supported in 64-bit mode")
3149 : _("`%s' is only supported in 64-bit mode"),
3150 current_templates->start->name);
3151 return NULL;
3152 }
c0f3af97 3153 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3154 {
3629bb00 3155 as_bad (_("`%s' is not supported on `%s%s'"),
41aacd83
L
3156 current_templates->start->name,
3157 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L
3158 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3159 return NULL;
29b0f896 3160 }
3629bb00
L
3161
3162skip:
3163 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3164 && (flag_code != CODE_16BIT))
29b0f896
AM
3165 {
3166 as_warn (_("use .code16 to ensure correct addressing mode"));
3167 }
252b5132 3168
29b0f896 3169 /* Check for rep/repne without a string instruction. */
f41bbced 3170 if (expecting_string_instruction)
29b0f896 3171 {
f41bbced
JB
3172 static templates override;
3173
3174 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3175 if (t->opcode_modifier.isstring)
f41bbced
JB
3176 break;
3177 if (t >= current_templates->end)
3178 {
3179 as_bad (_("expecting string instruction after `%s'"),
64e74474 3180 expecting_string_instruction);
f41bbced
JB
3181 return NULL;
3182 }
3183 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3184 if (!t->opcode_modifier.isstring)
f41bbced
JB
3185 break;
3186 override.end = t;
3187 current_templates = &override;
29b0f896 3188 }
252b5132 3189
29b0f896
AM
3190 return l;
3191}
252b5132 3192
29b0f896 3193static char *
e3bb37b5 3194parse_operands (char *l, const char *mnemonic)
29b0f896
AM
3195{
3196 char *token_start;
3138f287 3197
29b0f896
AM
3198 /* 1 if operand is pending after ','. */
3199 unsigned int expecting_operand = 0;
252b5132 3200
29b0f896
AM
3201 /* Non-zero if operand parens not balanced. */
3202 unsigned int paren_not_balanced;
3203
3204 while (*l != END_OF_INSN)
3205 {
3206 /* Skip optional white space before operand. */
3207 if (is_space_char (*l))
3208 ++l;
3209 if (!is_operand_char (*l) && *l != END_OF_INSN)
3210 {
3211 as_bad (_("invalid character %s before operand %d"),
3212 output_invalid (*l),
3213 i.operands + 1);
3214 return NULL;
3215 }
3216 token_start = l; /* after white space */
3217 paren_not_balanced = 0;
3218 while (paren_not_balanced || *l != ',')
3219 {
3220 if (*l == END_OF_INSN)
3221 {
3222 if (paren_not_balanced)
3223 {
3224 if (!intel_syntax)
3225 as_bad (_("unbalanced parenthesis in operand %d."),
3226 i.operands + 1);
3227 else
3228 as_bad (_("unbalanced brackets in operand %d."),
3229 i.operands + 1);
3230 return NULL;
3231 }
3232 else
3233 break; /* we are done */
3234 }
3235 else if (!is_operand_char (*l) && !is_space_char (*l))
3236 {
3237 as_bad (_("invalid character %s in operand %d"),
3238 output_invalid (*l),
3239 i.operands + 1);
3240 return NULL;
3241 }
3242 if (!intel_syntax)
3243 {
3244 if (*l == '(')
3245 ++paren_not_balanced;
3246 if (*l == ')')
3247 --paren_not_balanced;
3248 }
3249 else
3250 {
3251 if (*l == '[')
3252 ++paren_not_balanced;
3253 if (*l == ']')
3254 --paren_not_balanced;
3255 }
3256 l++;
3257 }
3258 if (l != token_start)
3259 { /* Yes, we've read in another operand. */
3260 unsigned int operand_ok;
3261 this_operand = i.operands++;
7d5e4556 3262 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM
3263 if (i.operands > MAX_OPERANDS)
3264 {
3265 as_bad (_("spurious operands; (%d operands/instruction max)"),
3266 MAX_OPERANDS);
3267 return NULL;
3268 }
3269 /* Now parse operand adding info to 'i' as we go along. */
3270 END_STRING_AND_SAVE (l);
3271
3272 if (intel_syntax)
3273 operand_ok =
3274 i386_intel_operand (token_start,
3275 intel_float_operand (mnemonic));
3276 else
a7619375 3277 operand_ok = i386_att_operand (token_start);
29b0f896
AM
3278
3279 RESTORE_END_STRING (l);
3280 if (!operand_ok)
3281 return NULL;
3282 }
3283 else
3284 {
3285 if (expecting_operand)
3286 {
3287 expecting_operand_after_comma:
3288 as_bad (_("expecting operand after ','; got nothing"));
3289 return NULL;
3290 }
3291 if (*l == ',')
3292 {
3293 as_bad (_("expecting operand before ','; got nothing"));
3294 return NULL;
3295 }
3296 }
7f3f1ea2 3297
29b0f896
AM
3298 /* Now *l must be either ',' or END_OF_INSN. */
3299 if (*l == ',')
3300 {
3301 if (*++l == END_OF_INSN)
3302 {
3303 /* Just skip it, if it's \n complain. */
3304 goto expecting_operand_after_comma;
3305 }
3306 expecting_operand = 1;
3307 }
3308 }
3309 return l;
3310}
7f3f1ea2 3311
050dfa73 3312static void
4d456e3d 3313swap_2_operands (int xchg1, int xchg2)
050dfa73
MM
3314{
3315 union i386_op temp_op;
40fb9820 3316 i386_operand_type temp_type;
050dfa73 3317 enum bfd_reloc_code_real temp_reloc;
4eed87de 3318
050dfa73
MM
3319 temp_type = i.types[xchg2];
3320 i.types[xchg2] = i.types[xchg1];
3321 i.types[xchg1] = temp_type;
3322 temp_op = i.op[xchg2];
3323 i.op[xchg2] = i.op[xchg1];
3324 i.op[xchg1] = temp_op;
3325 temp_reloc = i.reloc[xchg2];
3326 i.reloc[xchg2] = i.reloc[xchg1];
3327 i.reloc[xchg1] = temp_reloc;
3328}
3329
29b0f896 3330static void
e3bb37b5 3331swap_operands (void)
29b0f896 3332{
b7c61d9a 3333 switch (i.operands)
050dfa73 3334 {
c0f3af97 3335 case 5:
b7c61d9a 3336 case 4:
4d456e3d 3337 swap_2_operands (1, i.operands - 2);
b7c61d9a
L
3338 case 3:
3339 case 2:
4d456e3d 3340 swap_2_operands (0, i.operands - 1);
b7c61d9a
L
3341 break;
3342 default:
3343 abort ();
29b0f896 3344 }
29b0f896
AM
3345
3346 if (i.mem_operands == 2)
3347 {
3348 const seg_entry *temp_seg;
3349 temp_seg = i.seg[0];
3350 i.seg[0] = i.seg[1];
3351 i.seg[1] = temp_seg;
3352 }
3353}
252b5132 3354
29b0f896
AM
3355/* Try to ensure constant immediates are represented in the smallest
3356 opcode possible. */
3357static void
e3bb37b5 3358optimize_imm (void)
29b0f896
AM
3359{
3360 char guess_suffix = 0;
3361 int op;
252b5132 3362
29b0f896
AM
3363 if (i.suffix)
3364 guess_suffix = i.suffix;
3365 else if (i.reg_operands)
3366 {
3367 /* Figure out a suffix from the last register operand specified.
3368 We can't do this properly yet, ie. excluding InOutPortReg,
3369 but the following works for instructions with immediates.
3370 In any case, we can't set i.suffix yet. */
3371 for (op = i.operands; --op >= 0;)
40fb9820
L
3372 if (i.types[op].bitfield.reg8)
3373 {
3374 guess_suffix = BYTE_MNEM_SUFFIX;
3375 break;
3376 }
3377 else if (i.types[op].bitfield.reg16)
252b5132 3378 {
40fb9820
L
3379 guess_suffix = WORD_MNEM_SUFFIX;
3380 break;
3381 }
3382 else if (i.types[op].bitfield.reg32)
3383 {
3384 guess_suffix = LONG_MNEM_SUFFIX;
3385 break;
3386 }
3387 else if (i.types[op].bitfield.reg64)
3388 {
3389 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3390 break;
252b5132 3391 }
29b0f896
AM
3392 }
3393 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3394 guess_suffix = WORD_MNEM_SUFFIX;
3395
3396 for (op = i.operands; --op >= 0;)
40fb9820 3397 if (operand_type_check (i.types[op], imm))
29b0f896
AM
3398 {
3399 switch (i.op[op].imms->X_op)
252b5132 3400 {
29b0f896
AM
3401 case O_constant:
3402 /* If a suffix is given, this operand may be shortened. */
3403 switch (guess_suffix)
252b5132 3404 {
29b0f896 3405 case LONG_MNEM_SUFFIX:
40fb9820
L
3406 i.types[op].bitfield.imm32 = 1;
3407 i.types[op].bitfield.imm64 = 1;
29b0f896
AM
3408 break;
3409 case WORD_MNEM_SUFFIX:
40fb9820
L
3410 i.types[op].bitfield.imm16 = 1;
3411 i.types[op].bitfield.imm32 = 1;
3412 i.types[op].bitfield.imm32s = 1;
3413 i.types[op].bitfield.imm64 = 1;
29b0f896
AM
3414 break;
3415 case BYTE_MNEM_SUFFIX:
40fb9820
L
3416 i.types[op].bitfield.imm8 = 1;
3417 i.types[op].bitfield.imm8s = 1;
3418 i.types[op].bitfield.imm16 = 1;
3419 i.types[op].bitfield.imm32 = 1;
3420 i.types[op].bitfield.imm32s = 1;
3421 i.types[op].bitfield.imm64 = 1;
29b0f896 3422 break;
252b5132 3423 }
252b5132 3424
29b0f896
AM
3425 /* If this operand is at most 16 bits, convert it
3426 to a signed 16 bit number before trying to see
3427 whether it will fit in an even smaller size.
3428 This allows a 16-bit operand such as $0xffe0 to
3429 be recognised as within Imm8S range. */
40fb9820 3430 if ((i.types[op].bitfield.imm16)
29b0f896 3431 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3432 {
29b0f896
AM
3433 i.op[op].imms->X_add_number =
3434 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3435 }
40fb9820 3436 if ((i.types[op].bitfield.imm32)
29b0f896
AM
3437 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3438 == 0))
3439 {
3440 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3441 ^ ((offsetT) 1 << 31))
3442 - ((offsetT) 1 << 31));
3443 }
40fb9820 3444 i.types[op]
c6fb90c8
L
3445 = operand_type_or (i.types[op],
3446 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3447
29b0f896
AM
3448 /* We must avoid matching of Imm32 templates when 64bit
3449 only immediate is available. */
3450 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3451 i.types[op].bitfield.imm32 = 0;
29b0f896 3452 break;
252b5132 3453
29b0f896
AM
3454 case O_absent:
3455 case O_register:
3456 abort ();
3457
3458 /* Symbols and expressions. */
3459 default:
9cd96992
JB
3460 /* Convert symbolic operand to proper sizes for matching, but don't
3461 prevent matching a set of insns that only supports sizes other
3462 than those matching the insn suffix. */
3463 {
40fb9820 3464 i386_operand_type mask, allowed;
9cd96992
JB
3465 const template *t;
3466
0dfbf9d7
L
3467 operand_type_set (&mask, 0);
3468 operand_type_set (&allowed, 0);
40fb9820 3469
4eed87de
AM
3470 for (t = current_templates->start;
3471 t < current_templates->end;
3472 ++t)
c6fb90c8
L
3473 allowed = operand_type_or (allowed,
3474 t->operand_types[op]);
9cd96992
JB
3475 switch (guess_suffix)
3476 {
3477 case QWORD_MNEM_SUFFIX:
40fb9820
L
3478 mask.bitfield.imm64 = 1;
3479 mask.bitfield.imm32s = 1;
9cd96992
JB
3480 break;
3481 case LONG_MNEM_SUFFIX:
40fb9820 3482 mask.bitfield.imm32 = 1;
9cd96992
JB
3483 break;
3484 case WORD_MNEM_SUFFIX:
40fb9820 3485 mask.bitfield.imm16 = 1;
9cd96992
JB
3486 break;
3487 case BYTE_MNEM_SUFFIX:
40fb9820 3488 mask.bitfield.imm8 = 1;
9cd96992
JB
3489 break;
3490 default:
9cd96992
JB
3491 break;
3492 }
c6fb90c8 3493 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3494 if (!operand_type_all_zero (&allowed))
c6fb90c8 3495 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3496 }
29b0f896 3497 break;
252b5132 3498 }
29b0f896
AM
3499 }
3500}
47926f60 3501
29b0f896
AM
3502/* Try to use the smallest displacement type too. */
3503static void
e3bb37b5 3504optimize_disp (void)
29b0f896
AM
3505{
3506 int op;
3e73aa7c 3507
29b0f896 3508 for (op = i.operands; --op >= 0;)
40fb9820 3509 if (operand_type_check (i.types[op], disp))
252b5132 3510 {
b300c311 3511 if (i.op[op].disps->X_op == O_constant)
252b5132 3512 {
b300c311 3513 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3514
40fb9820 3515 if (i.types[op].bitfield.disp16
b300c311
L
3516 && (disp & ~(offsetT) 0xffff) == 0)
3517 {
3518 /* If this operand is at most 16 bits, convert
3519 to a signed 16 bit number and don't use 64bit
3520 displacement. */
3521 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3522 i.types[op].bitfield.disp64 = 0;
b300c311 3523 }
40fb9820 3524 if (i.types[op].bitfield.disp32
b300c311
L
3525 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3526 {
3527 /* If this operand is at most 32 bits, convert
3528 to a signed 32 bit number and don't use 64bit
3529 displacement. */
3530 disp &= (((offsetT) 2 << 31) - 1);
3531 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3532 i.types[op].bitfield.disp64 = 0;
b300c311 3533 }
40fb9820 3534 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3535 {
40fb9820
L
3536 i.types[op].bitfield.disp8 = 0;
3537 i.types[op].bitfield.disp16 = 0;
3538 i.types[op].bitfield.disp32 = 0;
3539 i.types[op].bitfield.disp32s = 0;
3540 i.types[op].bitfield.disp64 = 0;
b300c311
L
3541 i.op[op].disps = 0;
3542 i.disp_operands--;
3543 }
3544 else if (flag_code == CODE_64BIT)
3545 {
3546 if (fits_in_signed_long (disp))
28a9d8f5 3547 {
40fb9820
L
3548 i.types[op].bitfield.disp64 = 0;
3549 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3550 }
b300c311 3551 if (fits_in_unsigned_long (disp))
40fb9820 3552 i.types[op].bitfield.disp32 = 1;
b300c311 3553 }
40fb9820
L
3554 if ((i.types[op].bitfield.disp32
3555 || i.types[op].bitfield.disp32s
3556 || i.types[op].bitfield.disp16)
b300c311 3557 && fits_in_signed_byte (disp))
40fb9820 3558 i.types[op].bitfield.disp8 = 1;
252b5132 3559 }
67a4f2b7
AO
3560 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3561 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3562 {
3563 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3564 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L
3565 i.types[op].bitfield.disp8 = 0;
3566 i.types[op].bitfield.disp16 = 0;
3567 i.types[op].bitfield.disp32 = 0;
3568 i.types[op].bitfield.disp32s = 0;
3569 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO
3570 }
3571 else
b300c311 3572 /* We only support 64bit displacement on constants. */
40fb9820 3573 i.types[op].bitfield.disp64 = 0;
252b5132 3574 }
29b0f896
AM
3575}
3576
fa99fab2 3577static const template *
e3bb37b5 3578match_template (void)
29b0f896
AM
3579{
3580 /* Points to template once we've found it. */
3581 const template *t;
40fb9820 3582 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3583 i386_operand_type overlap4;
29b0f896 3584 unsigned int found_reverse_match;
40fb9820
L
3585 i386_opcode_modifier suffix_check;
3586 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3587 int addr_prefix_disp;
a5c311ca 3588 unsigned int j;
3629bb00 3589 unsigned int found_cpu_match;
45664ddb 3590 unsigned int check_register;
29b0f896 3591
c0f3af97
L
3592#if MAX_OPERANDS != 5
3593# error "MAX_OPERANDS must be 5."
f48ff2ae
L
3594#endif
3595
29b0f896 3596 found_reverse_match = 0;
539e75ad 3597 addr_prefix_disp = -1;
40fb9820
L
3598
3599 memset (&suffix_check, 0, sizeof (suffix_check));
3600 if (i.suffix == BYTE_MNEM_SUFFIX)
3601 suffix_check.no_bsuf = 1;
3602 else if (i.suffix == WORD_MNEM_SUFFIX)
3603 suffix_check.no_wsuf = 1;
3604 else if (i.suffix == SHORT_MNEM_SUFFIX)
3605 suffix_check.no_ssuf = 1;
3606 else if (i.suffix == LONG_MNEM_SUFFIX)
3607 suffix_check.no_lsuf = 1;
3608 else if (i.suffix == QWORD_MNEM_SUFFIX)
3609 suffix_check.no_qsuf = 1;
3610 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3611 suffix_check.no_ldsuf = 1;
29b0f896 3612
45aa61fe 3613 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3614 {
539e75ad
L
3615 addr_prefix_disp = -1;
3616
29b0f896
AM
3617 /* Must have right number of operands. */
3618 if (i.operands != t->operands)
3619 continue;
3620
50aecf8c 3621 /* Check processor support. */
c0f3af97
L
3622 found_cpu_match = (cpu_flags_match (t)
3623 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L
3624 if (!found_cpu_match)
3625 continue;
3626
e1d4d893
L
3627 /* Check old gcc support. */
3628 if (!old_gcc && t->opcode_modifier.oldgcc)
3629 continue;
3630
3631 /* Check AT&T mnemonic. */
3632 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L
3633 continue;
3634
5c07affc
L
3635 /* Check AT&T syntax Intel syntax. */
3636 if ((intel_syntax && t->opcode_modifier.attsyntax)
3637 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L
3638 continue;
3639
20592a94 3640 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L
3641 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3642 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3643 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3644 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3645 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3646 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3647 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM
3648 continue;
3649
5c07affc 3650 if (!operand_size_match (t))
7d5e4556 3651 continue;
539e75ad 3652
5c07affc
L
3653 for (j = 0; j < MAX_OPERANDS; j++)
3654 operand_types[j] = t->operand_types[j];
3655
45aa61fe
AM
3656 /* In general, don't allow 64-bit operands in 32-bit mode. */
3657 if (i.suffix == QWORD_MNEM_SUFFIX
3658 && flag_code != CODE_64BIT
3659 && (intel_syntax
40fb9820 3660 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM
3661 && !intel_float_operand (t->name))
3662 : intel_float_operand (t->name) != 2)
40fb9820 3663 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L
3664 && !operand_types[0].bitfield.regxmm
3665 && !operand_types[0].bitfield.regymm)
40fb9820 3666 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L
3667 && !!operand_types[t->operands > 1].bitfield.regxmm
3668 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM
3669 && (t->base_opcode != 0x0fc7
3670 || t->extension_opcode != 1 /* cmpxchg8b */))
3671 continue;
3672
192dc9c6
JB
3673 /* In general, don't allow 32-bit operands on pre-386. */
3674 else if (i.suffix == LONG_MNEM_SUFFIX
3675 && !cpu_arch_flags.bitfield.cpui386
3676 && (intel_syntax
3677 ? (!t->opcode_modifier.ignoresize
3678 && !intel_float_operand (t->name))
3679 : intel_float_operand (t->name) != 2)
3680 && ((!operand_types[0].bitfield.regmmx
3681 && !operand_types[0].bitfield.regxmm)
3682 || (!operand_types[t->operands > 1].bitfield.regmmx
3683 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3684 continue;
3685
29b0f896 3686 /* Do not verify operands when there are none. */
50aecf8c 3687 else
29b0f896 3688 {
c6fb90c8 3689 if (!t->operands)
2dbab7d5
L
3690 /* We've found a match; break out of loop. */
3691 break;
29b0f896 3692 }
252b5132 3693
539e75ad
L
3694 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3695 into Disp32/Disp16/Disp32 operand. */
3696 if (i.prefix[ADDR_PREFIX] != 0)
3697 {
40fb9820 3698 /* There should be only one Disp operand. */
539e75ad
L
3699 switch (flag_code)
3700 {
3701 case CODE_16BIT:
40fb9820
L
3702 for (j = 0; j < MAX_OPERANDS; j++)
3703 {
3704 if (operand_types[j].bitfield.disp16)
3705 {
3706 addr_prefix_disp = j;
3707 operand_types[j].bitfield.disp32 = 1;
3708 operand_types[j].bitfield.disp16 = 0;
3709 break;
3710 }
3711 }
539e75ad
L
3712 break;
3713 case CODE_32BIT:
40fb9820
L
3714 for (j = 0; j < MAX_OPERANDS; j++)
3715 {
3716 if (operand_types[j].bitfield.disp32)
3717 {
3718 addr_prefix_disp = j;
3719 operand_types[j].bitfield.disp32 = 0;
3720 operand_types[j].bitfield.disp16 = 1;
3721 break;
3722 }
3723 }
539e75ad
L
3724 break;
3725 case CODE_64BIT:
40fb9820
L
3726 for (j = 0; j < MAX_OPERANDS; j++)
3727 {
3728 if (operand_types[j].bitfield.disp64)
3729 {
3730 addr_prefix_disp = j;
3731 operand_types[j].bitfield.disp64 = 0;
3732 operand_types[j].bitfield.disp32 = 1;
3733 break;
3734 }
3735 }
539e75ad
L
3736 break;
3737 }
539e75ad
L
3738 }
3739
45664ddb
L
3740 /* We check register size only if size of operands can be
3741 encoded the canonical way. */
3742 check_register = t->opcode_modifier.w;
c6fb90c8 3743 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM
3744 switch (t->operands)
3745 {
3746 case 1:
40fb9820 3747 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM
3748 continue;
3749 break;
3750 case 2:
8b38ad71
L
3751 /* xchg %eax, %eax is a special case. It is an aliase for nop
3752 only in 32bit mode and we can use opcode 0x90. In 64bit
3753 mode, we can't use 0x90 for xchg %eax, %eax since it should
3754 zero-extend %eax to %rax. */
3755 if (flag_code == CODE_64BIT
3756 && t->base_opcode == 0x90
0dfbf9d7
L
3757 && operand_type_equal (&i.types [0], &acc32)
3758 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3759 continue;
b6169b20
L
3760 if (i.swap_operand)
3761 {
3762 /* If we swap operand in encoding, we either match
3763 the next one or reverse direction of operands. */
3764 if (t->opcode_modifier.s)
3765 continue;
3766 else if (t->opcode_modifier.d)
3767 goto check_reverse;
3768 }
3769
29b0f896 3770 case 3:
fa99fab2
L
3771 /* If we swap operand in encoding, we match the next one. */
3772 if (i.swap_operand && t->opcode_modifier.s)
3773 continue;
f48ff2ae 3774 case 4:
c0f3af97 3775 case 5:
c6fb90c8 3776 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L
3777 if (!operand_type_match (overlap0, i.types[0])
3778 || !operand_type_match (overlap1, i.types[1])
45664ddb
L
3779 || (check_register
3780 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L
3781 operand_types[0],
3782 overlap1, i.types[1],
3783 operand_types[1])))
29b0f896
AM
3784 {
3785 /* Check if other direction is valid ... */
40fb9820 3786 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM
3787 continue;
3788
b6169b20 3789check_reverse:
29b0f896 3790 /* Try reversing direction of operands. */
c6fb90c8
L
3791 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3792 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L
3793 if (!operand_type_match (overlap0, i.types[0])
3794 || !operand_type_match (overlap1, i.types[1])
45664ddb
L
3795 || (check_register
3796 && !operand_type_register_match (overlap0,
3797 i.types[0],
3798 operand_types[1],
3799 overlap1,
3800 i.types[1],
3801 operand_types[0])))
29b0f896
AM
3802 {
3803 /* Does not match either direction. */
3804 continue;
3805 }
3806 /* found_reverse_match holds which of D or FloatDR
3807 we've found. */
40fb9820 3808 if (t->opcode_modifier.d)
8a2ed489 3809 found_reverse_match = Opcode_D;
40fb9820 3810 else if (t->opcode_modifier.floatd)
8a2ed489
L
3811 found_reverse_match = Opcode_FloatD;
3812 else
3813 found_reverse_match = 0;
40fb9820 3814 if (t->opcode_modifier.floatr)
8a2ed489 3815 found_reverse_match |= Opcode_FloatR;
29b0f896 3816 }
f48ff2ae 3817 else
29b0f896 3818 {
f48ff2ae 3819 /* Found a forward 2 operand match here. */
d1cbb4db
L
3820 switch (t->operands)
3821 {
c0f3af97
L
3822 case 5:
3823 overlap4 = operand_type_and (i.types[4],
3824 operand_types[4]);
d1cbb4db 3825 case 4:
c6fb90c8
L
3826 overlap3 = operand_type_and (i.types[3],
3827 operand_types[3]);
d1cbb4db 3828 case 3:
c6fb90c8
L
3829 overlap2 = operand_type_and (i.types[2],
3830 operand_types[2]);
d1cbb4db
L
3831 break;
3832 }
29b0f896 3833
f48ff2ae
L
3834 switch (t->operands)
3835 {
c0f3af97
L
3836 case 5:
3837 if (!operand_type_match (overlap4, i.types[4])
3838 || !operand_type_register_match (overlap3,
3839 i.types[3],
3840 operand_types[3],
3841 overlap4,
3842 i.types[4],
3843 operand_types[4]))
3844 continue;
f48ff2ae 3845 case 4:
40fb9820 3846 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L
3847 || (check_register
3848 && !operand_type_register_match (overlap2,
3849 i.types[2],
3850 operand_types[2],
3851 overlap3,
3852 i.types[3],
3853 operand_types[3])))
f48ff2ae
L
3854 continue;
3855 case 3:
3856 /* Here we make use of the fact that there are no
3857 reverse match 3 operand instructions, and all 3
3858 operand instructions only need to be checked for
3859 register consistency between operands 2 and 3. */
40fb9820 3860 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L
3861 || (check_register
3862 && !operand_type_register_match (overlap1,
3863 i.types[1],
3864 operand_types[1],
3865 overlap2,
3866 i.types[2],
3867 operand_types[2])))
f48ff2ae
L
3868 continue;
3869 break;
3870 }
29b0f896 3871 }
f48ff2ae 3872 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM
3873 slip through to break. */
3874 }
3629bb00 3875 if (!found_cpu_match)
29b0f896
AM
3876 {
3877 found_reverse_match = 0;
3878 continue;
3879 }
c0f3af97 3880
29b0f896
AM
3881 /* We've found a match; break out of loop. */
3882 break;
3883 }
3884
3885 if (t == current_templates->end)
3886 {
3887 /* We found no match. */
95f283e8
L
3888 if (intel_syntax)
3889 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3890 current_templates->start->name);
3891 else
3892 as_bad (_("suffix or operands invalid for `%s'"),
3893 current_templates->start->name);
fa99fab2 3894 return NULL;
29b0f896 3895 }
252b5132 3896
29b0f896
AM
3897 if (!quiet_warnings)
3898 {
3899 if (!intel_syntax
40fb9820
L
3900 && (i.types[0].bitfield.jumpabsolute
3901 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM
3902 {
3903 as_warn (_("indirect %s without `*'"), t->name);
3904 }
3905
40fb9820
L
3906 if (t->opcode_modifier.isprefix
3907 && t->opcode_modifier.ignoresize)
29b0f896
AM
3908 {
3909 /* Warn them that a data or address size prefix doesn't
3910 affect assembly of the next line of code. */
3911 as_warn (_("stand-alone `%s' prefix"), t->name);
3912 }
3913 }
3914
3915 /* Copy the template we found. */
3916 i.tm = *t;
539e75ad
L
3917
3918 if (addr_prefix_disp != -1)
3919 i.tm.operand_types[addr_prefix_disp]
3920 = operand_types[addr_prefix_disp];
3921
29b0f896
AM
3922 if (found_reverse_match)
3923 {
3924 /* If we found a reverse match we must alter the opcode
3925 direction bit. found_reverse_match holds bits to change
3926 (different for int & float insns). */
3927
3928 i.tm.base_opcode ^= found_reverse_match;
3929
539e75ad
L
3930 i.tm.operand_types[0] = operand_types[1];
3931 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM
3932 }
3933
fa99fab2 3934 return t;
29b0f896
AM
3935}
3936
3937static int
e3bb37b5 3938check_string (void)
29b0f896 3939{
40fb9820
L
3940 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3941 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM
3942 {
3943 if (i.seg[0] != NULL && i.seg[0] != &es)
3944 {
a87af027 3945 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3946 i.tm.name,
a87af027
JB
3947 mem_op + 1,
3948 register_prefix);
29b0f896
AM
3949 return 0;
3950 }
3951 /* There's only ever one segment override allowed per instruction.
3952 This instruction possibly has a legal segment override on the
3953 second operand, so copy the segment to where non-string
3954 instructions store it, allowing common code. */
3955 i.seg[0] = i.seg[1];
3956 }
40fb9820 3957 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM
3958 {
3959 if (i.seg[1] != NULL && i.seg[1] != &es)
3960 {
a87af027 3961 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3962 i.tm.name,
a87af027
JB
3963 mem_op + 2,
3964 register_prefix);
29b0f896
AM
3965 return 0;
3966 }
3967 }
3968 return 1;
3969}
3970
3971static int
543613e9 3972process_suffix (void)
29b0f896
AM
3973{
3974 /* If matched instruction specifies an explicit instruction mnemonic
3975 suffix, use it. */
40fb9820
L
3976 if (i.tm.opcode_modifier.size16)
3977 i.suffix = WORD_MNEM_SUFFIX;
3978 else if (i.tm.opcode_modifier.size32)
3979 i.suffix = LONG_MNEM_SUFFIX;
3980 else if (i.tm.opcode_modifier.size64)
3981 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM
3982 else if (i.reg_operands)
3983 {
3984 /* If there's no instruction mnemonic suffix we try to invent one
3985 based on register operands. */
3986 if (!i.suffix)
3987 {
3988 /* We take i.suffix from the last register operand specified,
3989 Destination register type is more significant than source
381d071f
L
3990 register type. crc32 in SSE4.2 prefers source register
3991 type. */
3992 if (i.tm.base_opcode == 0xf20f38f1)
3993 {
40fb9820
L
3994 if (i.types[0].bitfield.reg16)
3995 i.suffix = WORD_MNEM_SUFFIX;
3996 else if (i.types[0].bitfield.reg32)
3997 i.suffix = LONG_MNEM_SUFFIX;
3998 else if (i.types[0].bitfield.reg64)
3999 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4000 }
9344ff29 4001 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4002 {
40fb9820 4003 if (i.types[0].bitfield.reg8)
20592a94
L
4004 i.suffix = BYTE_MNEM_SUFFIX;
4005 }
381d071f
L
4006
4007 if (!i.suffix)
4008 {
4009 int op;
4010
20592a94
L
4011 if (i.tm.base_opcode == 0xf20f38f1
4012 || i.tm.base_opcode == 0xf20f38f0)
4013 {
4014 /* We have to know the operand size for crc32. */
4015 as_bad (_("ambiguous memory operand size for `%s`"),
4016 i.tm.name);
4017 return 0;
4018 }
4019
381d071f 4020 for (op = i.operands; --op >= 0;)
40fb9820 4021 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4022 {
40fb9820
L
4023 if (i.types[op].bitfield.reg8)
4024 {
4025 i.suffix = BYTE_MNEM_SUFFIX;
4026 break;
4027 }
4028 else if (i.types[op].bitfield.reg16)
4029 {
4030 i.suffix = WORD_MNEM_SUFFIX;
4031 break;
4032 }
4033 else if (i.types[op].bitfield.reg32)
4034 {
4035 i.suffix = LONG_MNEM_SUFFIX;
4036 break;
4037 }
4038 else if (i.types[op].bitfield.reg64)
4039 {
4040 i.suffix = QWORD_MNEM_SUFFIX;
4041 break;
4042 }
381d071f
L
4043 }
4044 }
29b0f896
AM
4045 }
4046 else if (i.suffix == BYTE_MNEM_SUFFIX)
4047 {
4048 if (!check_byte_reg ())
4049 return 0;
4050 }
4051 else if (i.suffix == LONG_MNEM_SUFFIX)
4052 {
4053 if (!check_long_reg ())
4054 return 0;
4055 }
4056 else if (i.suffix == QWORD_MNEM_SUFFIX)
4057 {
955e1e6a
L
4058 if (intel_syntax
4059 && i.tm.opcode_modifier.ignoresize
4060 && i.tm.opcode_modifier.no_qsuf)
4061 i.suffix = 0;
4062 else if (!check_qword_reg ())
29b0f896
AM
4063 return 0;
4064 }
4065 else if (i.suffix == WORD_MNEM_SUFFIX)
4066 {
4067 if (!check_word_reg ())
4068 return 0;
4069 }
c0f3af97
L
4070 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4071 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4072 {
c0f3af97 4073 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L
4074 should check if it is a valid suffix. */
4075 }
40fb9820 4076 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM
4077 /* Do nothing if the instruction is going to ignore the prefix. */
4078 ;
4079 else
4080 abort ();
4081 }
40fb9820 4082 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB
4083 && !i.suffix
4084 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4085 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM
4086 {
4087 i.suffix = stackop_size;
4088 }
9306ca4a
JB
4089 else if (intel_syntax
4090 && !i.suffix
40fb9820
L
4091 && (i.tm.operand_types[0].bitfield.jumpabsolute
4092 || i.tm.opcode_modifier.jumpbyte
4093 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM
4094 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4095 && i.tm.extension_opcode <= 3)))
9306ca4a
JB
4096 {
4097 switch (flag_code)
4098 {
4099 case CODE_64BIT:
40fb9820 4100 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB
4101 {
4102 i.suffix = QWORD_MNEM_SUFFIX;
4103 break;
4104 }
4105 case CODE_32BIT:
40fb9820 4106 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB
4107 i.suffix = LONG_MNEM_SUFFIX;
4108 break;
4109 case CODE_16BIT:
40fb9820 4110 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB
4111 i.suffix = WORD_MNEM_SUFFIX;
4112 break;
4113 }
4114 }
252b5132 4115
9306ca4a 4116 if (!i.suffix)
29b0f896 4117 {
9306ca4a
JB
4118 if (!intel_syntax)
4119 {
40fb9820 4120 if (i.tm.opcode_modifier.w)
9306ca4a 4121 {
4eed87de
AM
4122 as_bad (_("no instruction mnemonic suffix given and "
4123 "no register operands; can't size instruction"));
9306ca4a
JB
4124 return 0;
4125 }
4126 }
4127 else
4128 {
40fb9820
L
4129 unsigned int suffixes;
4130
4131 suffixes = !i.tm.opcode_modifier.no_bsuf;
4132 if (!i.tm.opcode_modifier.no_wsuf)
4133 suffixes |= 1 << 1;
4134 if (!i.tm.opcode_modifier.no_lsuf)
4135 suffixes |= 1 << 2;
fc4adea1 4136 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L
4137 suffixes |= 1 << 3;
4138 if (!i.tm.opcode_modifier.no_ssuf)
4139 suffixes |= 1 << 4;
4140 if (!i.tm.opcode_modifier.no_qsuf)
4141 suffixes |= 1 << 5;
4142
4143 /* There are more than suffix matches. */
4144 if (i.tm.opcode_modifier.w
9306ca4a 4145 || ((suffixes & (suffixes - 1))
40fb9820
L
4146 && !i.tm.opcode_modifier.defaultsize
4147 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB
4148 {
4149 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4150 return 0;
4151 }
4152 }
29b0f896 4153 }
252b5132 4154
9306ca4a
JB
4155 /* Change the opcode based on the operand size given by i.suffix;
4156 We don't need to change things for byte insns. */
4157
582d5edd
L
4158 if (i.suffix
4159 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L
4160 && i.suffix != XMMWORD_MNEM_SUFFIX
4161 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM
4162 {
4163 /* It's not a byte, select word/dword operation. */
40fb9820 4164 if (i.tm.opcode_modifier.w)
29b0f896 4165 {
40fb9820 4166 if (i.tm.opcode_modifier.shortform)
29b0f896
AM
4167 i.tm.base_opcode |= 8;
4168 else
4169 i.tm.base_opcode |= 1;
4170 }
0f3f3d8b 4171
29b0f896
AM
4172 /* Now select between word & dword operations via the operand
4173 size prefix, except for instructions that will ignore this
4174 prefix anyway. */
ca61edf2 4175 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4176 {
ca61edf2
L
4177 /* The address size override prefix changes the size of the
4178 first operand. */
40fb9820
L
4179 if ((flag_code == CODE_32BIT
4180 && i.op->regs[0].reg_type.bitfield.reg16)
4181 || (flag_code != CODE_32BIT
4182 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L
4183 if (!add_prefix (ADDR_PREFIX_OPCODE))
4184 return 0;
4185 }
4186 else if (i.suffix != QWORD_MNEM_SUFFIX
4187 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L
4188 && !i.tm.opcode_modifier.ignoresize
4189 && !i.tm.opcode_modifier.floatmf
cb712a9e
L
4190 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4191 || (flag_code == CODE_64BIT
40fb9820 4192 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM
4193 {
4194 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4195
40fb9820 4196 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4197 prefix = ADDR_PREFIX_OPCODE;
252b5132 4198
29b0f896
AM
4199 if (!add_prefix (prefix))
4200 return 0;
24eab124 4201 }
252b5132 4202
29b0f896
AM
4203 /* Set mode64 for an operand. */
4204 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4205 && flag_code == CODE_64BIT
40fb9820 4206 && !i.tm.opcode_modifier.norex64)
46e883c5
L
4207 {
4208 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L
4209 need rex64. cmpxchg8b is also a special case. */
4210 if (! (i.operands == 2
4211 && i.tm.base_opcode == 0x90
4212 && i.tm.extension_opcode == None
0dfbf9d7
L
4213 && operand_type_equal (&i.types [0], &acc64)
4214 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L
4215 && ! (i.operands == 1
4216 && i.tm.base_opcode == 0xfc7
4217 && i.tm.extension_opcode == 1
40fb9820
L
4218 && !operand_type_check (i.types [0], reg)
4219 && operand_type_check (i.types [0], anymem)))
f6bee062 4220 i.rex |= REX_W;
46e883c5 4221 }
3e73aa7c 4222
29b0f896
AM
4223 /* Size floating point instruction. */
4224 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4225 if (i.tm.opcode_modifier.floatmf)
543613e9 4226 i.tm.base_opcode ^= 4;
29b0f896 4227 }
7ecd2f8b 4228
29b0f896
AM
4229 return 1;
4230}
3e73aa7c 4231
29b0f896 4232static int
543613e9 4233check_byte_reg (void)
29b0f896
AM
4234{
4235 int op;
543613e9 4236
29b0f896
AM
4237 for (op = i.operands; --op >= 0;)
4238 {
4239 /* If this is an eight bit register, it's OK. If it's the 16 or
4240 32 bit version of an eight bit register, we will just use the
4241 low portion, and that's OK too. */
40fb9820 4242 if (i.types[op].bitfield.reg8)
29b0f896
AM
4243 continue;
4244
ca61edf2
L
4245 /* Don't generate this warning if not needed. */
4246 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM
4247 continue;
4248
9344ff29
L
4249 /* crc32 doesn't generate this warning. */
4250 if (i.tm.base_opcode == 0xf20f38f0)
4251 continue;
4252
40fb9820
L
4253 if ((i.types[op].bitfield.reg16
4254 || i.types[op].bitfield.reg32
4255 || i.types[op].bitfield.reg64)
4256 && i.op[op].regs->reg_num < 4)
29b0f896
AM
4257 {
4258 /* Prohibit these changes in the 64bit mode, since the
4259 lowering is more complicated. */
4260 if (flag_code == CODE_64BIT
40fb9820 4261 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4262 {
2ca3ace5
L
4263 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4264 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM
4265 i.suffix);
4266 return 0;
4267 }
4268#if REGISTER_WARNINGS
4269 if (!quiet_warnings
40fb9820 4270 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L
4271 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4272 register_prefix,
40fb9820 4273 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM
4274 ? REGNAM_AL - REGNAM_AX
4275 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4276 register_prefix,
29b0f896
AM
4277 i.op[op].regs->reg_name,
4278 i.suffix);
4279#endif
4280 continue;
4281 }
4282 /* Any other register is bad. */
40fb9820
L
4283 if (i.types[op].bitfield.reg16
4284 || i.types[op].bitfield.reg32
4285 || i.types[op].bitfield.reg64
4286 || i.types[op].bitfield.regmmx
4287 || i.types[op].bitfield.regxmm
c0f3af97 4288 || i.types[op].bitfield.regymm
40fb9820
L
4289 || i.types[op].bitfield.sreg2
4290 || i.types[op].bitfield.sreg3
4291 || i.types[op].bitfield.control
4292 || i.types[op].bitfield.debug
4293 || i.types[op].bitfield.test
4294 || i.types[op].bitfield.floatreg
4295 || i.types[op].bitfield.floatacc)
29b0f896 4296 {
a540244d
L
4297 as_bad (_("`%s%s' not allowed with `%s%c'"),
4298 register_prefix,
29b0f896
AM
4299 i.op[op].regs->reg_name,
4300 i.tm.name,
4301 i.suffix);
4302 return 0;
4303 }
4304 }
4305 return 1;
4306}
4307
4308static int
e3bb37b5 4309check_long_reg (void)
29b0f896
AM
4310{
4311 int op;
4312
4313 for (op = i.operands; --op >= 0;)
4314 /* Reject eight bit registers, except where the template requires
4315 them. (eg. movzb) */
40fb9820
L
4316 if (i.types[op].bitfield.reg8
4317 && (i.tm.operand_types[op].bitfield.reg16
4318 || i.tm.operand_types[op].bitfield.reg32
4319 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4320 {
a540244d
L
4321 as_bad (_("`%s%s' not allowed with `%s%c'"),
4322 register_prefix,
29b0f896
AM
4323 i.op[op].regs->reg_name,
4324 i.tm.name,
4325 i.suffix);
4326 return 0;
4327 }
4328 /* Warn if the e prefix on a general reg is missing. */
4329 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L
4330 && i.types[op].bitfield.reg16
4331 && (i.tm.operand_types[op].bitfield.reg32
4332 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM
4333 {
4334 /* Prohibit these changes in the 64bit mode, since the
4335 lowering is more complicated. */
4336 if (flag_code == CODE_64BIT)
252b5132 4337 {
2ca3ace5
L
4338 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4339 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM
4340 i.suffix);
4341 return 0;
252b5132 4342 }
29b0f896
AM
4343#if REGISTER_WARNINGS
4344 else
a540244d
L
4345 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4346 register_prefix,
29b0f896 4347 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4348 register_prefix,
29b0f896
AM
4349 i.op[op].regs->reg_name,
4350 i.suffix);
4351#endif
252b5132 4352 }
29b0f896 4353 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L
4354 else if (i.types[op].bitfield.reg64
4355 && (i.tm.operand_types[op].bitfield.reg32
4356 || i.tm.operand_types[op].bitfield.acc))
252b5132 4357 {
34828aad 4358 if (intel_syntax
ca61edf2 4359 && i.tm.opcode_modifier.toqword
40fb9820 4360 && !i.types[0].bitfield.regxmm)
34828aad 4361 {
ca61edf2 4362 /* Convert to QWORD. We want REX byte. */
34828aad
L
4363 i.suffix = QWORD_MNEM_SUFFIX;
4364 }
4365 else
4366 {
4367 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4368 register_prefix, i.op[op].regs->reg_name,
4369 i.suffix);
4370 return 0;
4371 }
29b0f896
AM
4372 }
4373 return 1;
4374}
252b5132 4375
29b0f896 4376static int
e3bb37b5 4377check_qword_reg (void)
29b0f896
AM
4378{
4379 int op;
252b5132 4380
29b0f896
AM
4381 for (op = i.operands; --op >= 0; )
4382 /* Reject eight bit registers, except where the template requires
4383 them. (eg. movzb) */
40fb9820
L
4384 if (i.types[op].bitfield.reg8
4385 && (i.tm.operand_types[op].bitfield.reg16
4386 || i.tm.operand_types[op].bitfield.reg32
4387 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4388 {
a540244d
L
4389 as_bad (_("`%s%s' not allowed with `%s%c'"),
4390 register_prefix,
29b0f896
AM
4391 i.op[op].regs->reg_name,
4392 i.tm.name,
4393 i.suffix);
4394 return 0;
4395 }
4396 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L
4397 else if ((i.types[op].bitfield.reg16
4398 || i.types[op].bitfield.reg32)
4399 && (i.tm.operand_types[op].bitfield.reg32
4400 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM
4401 {
4402 /* Prohibit these changes in the 64bit mode, since the
4403 lowering is more complicated. */
34828aad 4404 if (intel_syntax
ca61edf2 4405 && i.tm.opcode_modifier.todword
40fb9820 4406 && !i.types[0].bitfield.regxmm)
34828aad 4407 {
ca61edf2 4408 /* Convert to DWORD. We don't want REX byte. */
34828aad
L
4409 i.suffix = LONG_MNEM_SUFFIX;
4410 }
4411 else
4412 {
4413 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4414 register_prefix, i.op[op].regs->reg_name,
4415 i.suffix);
4416 return 0;
4417 }
252b5132 4418 }
29b0f896
AM
4419 return 1;
4420}
252b5132 4421
29b0f896 4422static int
e3bb37b5 4423check_word_reg (void)
29b0f896
AM
4424{
4425 int op;
4426 for (op = i.operands; --op >= 0;)
4427 /* Reject eight bit registers, except where the template requires
4428 them. (eg. movzb) */
40fb9820
L
4429 if (i.types[op].bitfield.reg8
4430 && (i.tm.operand_types[op].bitfield.reg16
4431 || i.tm.operand_types[op].bitfield.reg32
4432 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4433 {
a540244d
L
4434 as_bad (_("`%s%s' not allowed with `%s%c'"),
4435 register_prefix,
29b0f896
AM
4436 i.op[op].regs->reg_name,
4437 i.tm.name,
4438 i.suffix);
4439 return 0;
4440 }
4441 /* Warn if the e prefix on a general reg is present. */
4442 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L
4443 && i.types[op].bitfield.reg32
4444 && (i.tm.operand_types[op].bitfield.reg16
4445 || i.tm.operand_types[op].bitfield.acc))
252b5132 4446 {
29b0f896
AM
4447 /* Prohibit these changes in the 64bit mode, since the
4448 lowering is more complicated. */
4449 if (flag_code == CODE_64BIT)
252b5132 4450 {
2ca3ace5
L
4451 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4452 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM
4453 i.suffix);
4454 return 0;
252b5132 4455 }
29b0f896
AM
4456 else
4457#if REGISTER_WARNINGS
a540244d
L
4458 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4459 register_prefix,
29b0f896 4460 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4461 register_prefix,
29b0f896
AM
4462 i.op[op].regs->reg_name,
4463 i.suffix);
4464#endif
4465 }
4466 return 1;
4467}
252b5132 4468
29b0f896 4469static int
40fb9820 4470update_imm (unsigned int j)
29b0f896 4471{
40fb9820
L
4472 i386_operand_type overlap;
4473
c6fb90c8 4474 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L
4475 if ((overlap.bitfield.imm8
4476 || overlap.bitfield.imm8s
4477 || overlap.bitfield.imm16
4478 || overlap.bitfield.imm32
4479 || overlap.bitfield.imm32s
4480 || overlap.bitfield.imm64)
0dfbf9d7
L
4481 && !operand_type_equal (&overlap, &imm8)
4482 && !operand_type_equal (&overlap, &imm8s)
4483 && !operand_type_equal (&overlap, &imm16)
4484 && !operand_type_equal (&overlap, &imm32)
4485 && !operand_type_equal (&overlap, &imm32s)
4486 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM
4487 {
4488 if (i.suffix)
4489 {
40fb9820
L
4490 i386_operand_type temp;
4491
0dfbf9d7 4492 operand_type_set (&temp, 0);
40fb9820
L
4493 if (i.suffix == BYTE_MNEM_SUFFIX)
4494 {
4495 temp.bitfield.imm8 = overlap.bitfield.imm8;
4496 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4497 }
4498 else if (i.suffix == WORD_MNEM_SUFFIX)
4499 temp.bitfield.imm16 = overlap.bitfield.imm16;
4500 else if (i.suffix == QWORD_MNEM_SUFFIX)
4501 {
4502 temp.bitfield.imm64 = overlap.bitfield.imm64;
4503 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4504 }
4505 else
4506 temp.bitfield.imm32 = overlap.bitfield.imm32;
4507 overlap = temp;
29b0f896 4508 }
0dfbf9d7
L
4509 else if (operand_type_equal (&overlap, &imm16_32_32s)
4510 || operand_type_equal (&overlap, &imm16_32)
4511 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4512 {
40fb9820 4513 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4514 overlap = imm16;
40fb9820 4515 else
65da13b5 4516 overlap = imm32s;
29b0f896 4517 }
0dfbf9d7
L
4518 if (!operand_type_equal (&overlap, &imm8)
4519 && !operand_type_equal (&overlap, &imm8s)
4520 && !operand_type_equal (&overlap, &imm16)
4521 && !operand_type_equal (&overlap, &imm32)
4522 && !operand_type_equal (&overlap, &imm32s)
4523 && !operand_type_equal (&overlap, &imm64))
29b0f896 4524 {
4eed87de
AM
4525 as_bad (_("no instruction mnemonic suffix given; "
4526 "can't determine immediate size"));
29b0f896
AM
4527 return 0;
4528 }
4529 }
40fb9820 4530 i.types[j] = overlap;
29b0f896 4531
40fb9820
L
4532 return 1;
4533}
4534
4535static int
4536finalize_imm (void)
4537{
4538 unsigned int j;
29b0f896 4539
40fb9820
L
4540 for (j = 0; j < 2; j++)
4541 if (update_imm (j) == 0)
4542 return 0;
4543
c6fb90c8 4544 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4545 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM
4546
4547 return 1;
4548}
4549
85f10a01
MM
4550static void
4551process_drex (void)
4552{
5dd15031
JJ
4553 i.drex.modrm_reg = 0;
4554 i.drex.modrm_regmem = 0;
85f10a01
MM
4555
4556 /* SSE5 4 operand instructions must have the destination the same as
4557 one of the inputs. Figure out the destination register and cache
4558 it away in the drex field, and remember which fields to use for
4559 the modrm byte. */
4560 if (i.tm.opcode_modifier.drex
4561 && i.tm.opcode_modifier.drexv
4562 && i.operands == 4)
4563 {
4564 i.tm.extension_opcode = None;
4565
4566 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4567 if (i.types[0].bitfield.regxmm != 0
4568 && i.types[1].bitfield.regxmm != 0
4569 && i.types[2].bitfield.regxmm != 0
4570 && i.types[3].bitfield.regxmm != 0
4571 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4572 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4573 {
4574 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L
4575 operand_type_set (&i.types[0], 0);
4576 operand_type_set (&i.types[3], 0);
85f10a01
MM
4577 i.reg_operands -= 2;
4578
4579 /* There are two different ways to encode a 4 operand
4580 instruction with all registers that uses OC1 set to
4581 0 or 1. Favor setting OC1 to 0 since this mimics the
4582 actions of other SSE5 assemblers. Use modrm encoding 2
4583 for register/register. Include the high order bit that
4584 is normally stored in the REX byte in the register
4585 field. */
4586 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4587 i.drex.modrm_reg = 2;
4588 i.drex.modrm_regmem = 1;
4589 i.drex.reg = (i.op[3].regs->reg_num
4590 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4591 }
4592
4593 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4594 else if (i.types[0].bitfield.regxmm != 0
4595 && i.types[1].bitfield.regxmm != 0
4596 && (i.types[2].bitfield.regxmm
4597 || operand_type_check (i.types[2], anymem))
4598 && i.types[3].bitfield.regxmm != 0
4599 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4600 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4601 {
4602 /* clear the arguments that are stored in drex */
0dfbf9d7
L
4603 operand_type_set (&i.types[0], 0);
4604 operand_type_set (&i.types[3], 0);
85f10a01
MM
4605 i.reg_operands -= 2;
4606
4607 /* Specify the modrm encoding for memory addressing. Include
4608 the high order bit that is normally stored in the REX byte
4609 in the register field. */
4610 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4611 i.drex.modrm_reg = 1;
4612 i.drex.modrm_regmem = 2;
4613 i.drex.reg = (i.op[3].regs->reg_num
4614 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4615 }
4616
4617 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4618 else if (i.types[0].bitfield.regxmm != 0
4619 && operand_type_check (i.types[1], anymem) != 0
4620 && i.types[2].bitfield.regxmm != 0
4621 && i.types[3].bitfield.regxmm != 0
4622 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4623 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4624 {
4625 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L
4626 operand_type_set (&i.types[0], 0);
4627 operand_type_set (&i.types[3], 0);
85f10a01
MM
4628 i.reg_operands -= 2;
4629
4630 /* Specify the modrm encoding for memory addressing. Include
4631 the high order bit that is normally stored in the REX byte
4632 in the register field. */
4633 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4634 i.drex.modrm_reg = 2;
4635 i.drex.modrm_regmem = 1;
4636 i.drex.reg = (i.op[3].regs->reg_num
4637 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4638 }
4639
4640 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4641 else if (i.types[0].bitfield.regxmm != 0
4642 && i.types[1].bitfield.regxmm != 0
4643 && i.types[2].bitfield.regxmm != 0
4644 && i.types[3].bitfield.regxmm != 0
4645 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4646 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4647 {
4648 /* clear the arguments that are stored in drex */
0dfbf9d7
L
4649 operand_type_set (&i.types[2], 0);
4650 operand_type_set (&i.types[3], 0);
85f10a01
MM
4651 i.reg_operands -= 2;
4652
4653 /* There are two different ways to encode a 4 operand
4654 instruction with all registers that uses OC1 set to
4655 0 or 1. Favor setting OC1 to 0 since this mimics the
4656 actions of other SSE5 assemblers. Use modrm encoding
4657 2 for register/register. Include the high order bit that
4658 is normally stored in the REX byte in the register
4659 field. */
4660 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4661 i.drex.modrm_reg = 1;
4662 i.drex.modrm_regmem = 0;
4663
4664 /* Remember the register, including the upper bits */
4665 i.drex.reg = (i.op[3].regs->reg_num
4666 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4667 }
4668
4669 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4670 else if (i.types[0].bitfield.regxmm != 0
4671 && (i.types[1].bitfield.regxmm
4672 || operand_type_check (i.types[1], anymem))
4673 && i.types[2].bitfield.regxmm != 0
4674 && i.types[3].bitfield.regxmm != 0
4675 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4676 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4677 {
4678 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L
4679 operand_type_set (&i.types[2], 0);
4680 operand_type_set (&i.types[3], 0);
85f10a01
MM
4681 i.reg_operands -= 2;
4682
4683 /* Specify the modrm encoding and remember the register
4684 including the bits normally stored in the REX byte. */
4685 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4686 i.drex.modrm_reg = 0;
4687 i.drex.modrm_regmem = 1;
4688 i.drex.reg = (i.op[3].regs->reg_num
4689 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4690 }
4691
4692 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4693 else if (operand_type_check (i.types[0], anymem) != 0
4694 && i.types[1].bitfield.regxmm != 0
4695 && i.types[2].bitfield.regxmm != 0
4696 && i.types[3].bitfield.regxmm != 0
4697 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4698 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4699 {
4700 /* clear the arguments that are stored in drex */
0dfbf9d7
L
4701 operand_type_set (&i.types[2], 0);
4702 operand_type_set (&i.types[3], 0);
85f10a01
MM
4703 i.reg_operands -= 2;
4704
4705 /* Specify the modrm encoding and remember the register
4706 including the bits normally stored in the REX byte. */
4707 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4708 i.drex.modrm_reg = 1;
4709 i.drex.modrm_regmem = 0;
4710 i.drex.reg = (i.op[3].regs->reg_num
4711 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4712 }
4713
4714 else
4715 as_bad (_("Incorrect operands for the '%s' instruction"),
4716 i.tm.name);
4717 }
4718
4719 /* SSE5 instructions with the DREX byte where the only memory operand
4720 is in the 2nd argument, and the first and last xmm register must
4721 match, and is encoded in the DREX byte. */
4722 else if (i.tm.opcode_modifier.drex
4723 && !i.tm.opcode_modifier.drexv
4724 && i.operands == 4)
4725 {
4726 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4727 if (i.types[0].bitfield.regxmm != 0
4728 && (i.types[1].bitfield.regxmm
4729 || operand_type_check(i.types[1], anymem))
4730 && i.types[2].bitfield.regxmm != 0
4731 && i.types[3].bitfield.regxmm != 0
4732 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4733 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4734 {
4735 /* clear the arguments that are stored in drex */
0dfbf9d7
L
4736 operand_type_set (&i.types[0], 0);
4737 operand_type_set (&i.types[3], 0);
85f10a01
MM
4738 i.reg_operands -= 2;
4739
4740 /* Specify the modrm encoding and remember the register
4741 including the high bit normally stored in the REX
4742 byte. */
4743 i.drex.modrm_reg = 2;
4744 i.drex.modrm_regmem = 1;
4745 i.drex.reg = (i.op[3].regs->reg_num
4746 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4747 }
4748
4749 else
4750 as_bad (_("Incorrect operands for the '%s' instruction"),
4751 i.tm.name);
4752 }
4753
4754 /* SSE5 3 operand instructions that the result is a register, being
4755 either operand can be a memory operand, using OC0 to note which
4756 one is the memory. */
4757 else if (i.tm.opcode_modifier.drex
4758 && i.tm.opcode_modifier.drexv
4759 && i.operands == 3)
4760 {
4761 i.tm.extension_opcode = None;
4762
4763 /* Case 1: 3 operand insn, src1 = register. */
4764 if (i.types[0].bitfield.regxmm != 0
4765 && i.types[1].bitfield.regxmm != 0
4766 && i.types[2].bitfield.regxmm != 0)
4767 {
4768 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4769 operand_type_set (&i.types[2], 0);
85f10a01
MM
4770 i.reg_operands--;
4771
4772 /* Specify the modrm encoding and remember the register
4773 including the high bit normally stored in the REX byte. */
4774 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4775 i.drex.modrm_reg = 1;
4776 i.drex.modrm_regmem = 0;
4777 i.drex.reg = (i.op[2].regs->reg_num
4778 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4779 }
4780
4781 /* Case 2: 3 operand insn, src1 = memory. */
4782 else if (operand_type_check (i.types[0], anymem) != 0
4783 && i.types[1].bitfield.regxmm != 0
4784 && i.types[2].bitfield.regxmm != 0)
4785 {
4786 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4787 operand_type_set (&i.types[2], 0);
85f10a01
MM
4788 i.reg_operands--;
4789
4790 /* Specify the modrm encoding and remember the register
4791 including the high bit normally stored in the REX
4792 byte. */
4793 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4794 i.drex.modrm_reg = 1;
4795 i.drex.modrm_regmem = 0;
4796 i.drex.reg = (i.op[2].regs->reg_num
4797 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4798 }
4799
4800 /* Case 3: 3 operand insn, src2 = memory. */
4801 else if (i.types[0].bitfield.regxmm != 0
4802 && operand_type_check (i.types[1], anymem) != 0
4803 && i.types[2].bitfield.regxmm != 0)
4804 {
4805 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4806 operand_type_set (&i.types[2], 0);
85f10a01
MM
4807 i.reg_operands--;
4808
4809 /* Specify the modrm encoding and remember the register
4810 including the high bit normally stored in the REX byte. */
4811 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4812 i.drex.modrm_reg = 0;
4813 i.drex.modrm_regmem = 1;
4814 i.drex.reg = (i.op[2].regs->reg_num
4815 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4816 }
4817
4818 else
4819 as_bad (_("Incorrect operands for the '%s' instruction"),
4820 i.tm.name);
4821 }
4822
4823 /* SSE5 4 operand instructions that are the comparison instructions
4824 where the first operand is the immediate value of the comparison
4825 to be done. */
4826 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4827 {
4828 /* Case 1: 4 operand insn, src1 = reg/memory. */
4829 if (operand_type_check (i.types[0], imm) != 0
4830 && (i.types[1].bitfield.regxmm
4831 || operand_type_check (i.types[1], anymem))
4832 && i.types[2].bitfield.regxmm != 0
4833 && i.types[3].bitfield.regxmm != 0)
4834 {
4835 /* clear the arguments that are stored in drex */
0dfbf9d7 4836 operand_type_set (&i.types[3], 0);
85f10a01
MM
4837 i.reg_operands--;
4838
4839 /* Specify the modrm encoding and remember the register
4840 including the high bit normally stored in the REX byte. */
4841 i.drex.modrm_reg = 2;
4842 i.drex.modrm_regmem = 1;
4843 i.drex.reg = (i.op[3].regs->reg_num
4844 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4845 }
4846
4847 /* Case 2: 3 operand insn with ImmExt that places the
4848 opcode_extension as an immediate argument. This is used for
4849 all of the varients of comparison that supplies the appropriate
4850 value as part of the instruction. */
4851 else if ((i.types[0].bitfield.regxmm
4852 || operand_type_check (i.types[0], anymem))
4853 && i.types[1].bitfield.regxmm != 0
4854 && i.types[2].bitfield.regxmm != 0
4855 && operand_type_check (i.types[3], imm) != 0)
4856 {
4857 /* clear the arguments that are stored in drex */
0dfbf9d7 4858 operand_type_set (&i.types[2], 0);
85f10a01
MM
4859 i.reg_operands--;
4860
4861 /* Specify the modrm encoding and remember the register
4862 including the high bit normally stored in the REX byte. */
4863 i.drex.modrm_reg = 1;
4864 i.drex.modrm_regmem = 0;
4865 i.drex.reg = (i.op[2].regs->reg_num
4866 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4867 }
4868
4869 else
4870 as_bad (_("Incorrect operands for the '%s' instruction"),
4871 i.tm.name);
4872 }
4873
4874 else if (i.tm.opcode_modifier.drex
4875 || i.tm.opcode_modifier.drexv
4876 || i.tm.opcode_modifier.drexc)
4877 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4878}
4879
c0f3af97
L
4880static int
4881bad_implicit_operand (int xmm)
4882{
4883 const char *reg = xmm ? "xmm0" : "ymm0";
4884 if (intel_syntax)
4885 as_bad (_("the last operand of `%s' must be `%s%s'"),
4886 i.tm.name, register_prefix, reg);
4887 else
4888 as_bad (_("the first operand of `%s' must be `%s%s'"),
4889 i.tm.name, register_prefix, reg);
4890 return 0;
4891}
4892
29b0f896 4893static int
e3bb37b5 4894process_operands (void)
29b0f896
AM
4895{
4896 /* Default segment register this instruction will use for memory
4897 accesses. 0 means unknown. This is only for optimizing out
4898 unnecessary segment overrides. */
4899 const seg_entry *default_seg = 0;
4900
85f10a01
MM
4901 /* Handle all of the DREX munging that SSE5 needs. */
4902 if (i.tm.opcode_modifier.drex
4903 || i.tm.opcode_modifier.drexv
4904 || i.tm.opcode_modifier.drexc)
4905 process_drex ();
4906
c0f3af97
L
4907 if (i.tm.opcode_modifier.sse2avx
4908 && (i.tm.opcode_modifier.vexnds
4909 || i.tm.opcode_modifier.vexndd))
29b0f896 4910 {
c0f3af97
L
4911 unsigned int dup = i.operands;
4912 unsigned int dest = dup - 1;
9fcfb3d7
L
4913 unsigned int j;
4914
c0f3af97 4915 /* The destination must be an xmm register. */
0dfbf9d7 4916 assert (i.reg_operands
c0f3af97
L
4917 && MAX_OPERANDS > dup
4918 && operand_type_equal (&i.types[dest], &regxmm));
4919
4920 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4921 {
c0f3af97
L
4922 /* The first operand is implicit and must be xmm0. */
4923 assert (operand_type_equal (&i.types[0], &regxmm));
4924 if (i.op[0].regs->reg_num != 0)
4925 return bad_implicit_operand (1);
4926
4927 if (i.tm.opcode_modifier.vex3sources)
4928 {
4929 /* Keep xmm0 for instructions with VEX prefix and 3
4930 sources. */
4931 goto duplicate;
4932 }
e2ec9d29 4933 else
c0f3af97
L
4934 {
4935 /* We remove the first xmm0 and keep the number of
4936 operands unchanged, which in fact duplicates the
4937 destination. */
4938 for (j = 1; j < i.operands; j++)
4939 {
4940 i.op[j - 1] = i.op[j];
4941 i.types[j - 1] = i.types[j];
4942 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4943 }
4944 }
4945 }
4946 else if (i.tm.opcode_modifier.implicit1stxmm0)
4947 {
4948 assert ((MAX_OPERANDS - 1) > dup
4949 && i.tm.opcode_modifier.vex3sources);
4950
4951 /* Add the implicit xmm0 for instructions with VEX prefix
4952 and 3 sources. */
4953 for (j = i.operands; j > 0; j--)
4954 {
4955 i.op[j] = i.op[j - 1];
4956 i.types[j] = i.types[j - 1];
4957 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4958 }
4959 i.op[0].regs
4960 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4961 i.types[0] = regxmm;
4962 i.tm.operand_types[0] = regxmm;
4963
4964 i.operands += 2;
4965 i.reg_operands += 2;
4966 i.tm.operands += 2;
4967
4968 dup++;
4969 dest++;
4970 i.op[dup] = i.op[dest];
4971 i.types[dup] = i.types[dest];
4972 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4973 }
c0f3af97
L
4974 else
4975 {
4976duplicate:
4977 i.operands++;
4978 i.reg_operands++;
4979 i.tm.operands++;
4980
4981 i.op[dup] = i.op[dest];
4982 i.types[dup] = i.types[dest];
4983 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4984 }
4985
4986 if (i.tm.opcode_modifier.immext)
4987 process_immext ();
4988 }
4989 else if (i.tm.opcode_modifier.firstxmm0)
4990 {
4991 unsigned int j;
4992
4993 /* The first operand is implicit and must be xmm0/ymm0. */
4994 assert (i.reg_operands
4995 && (operand_type_equal (&i.types[0], &regxmm)
4996 || operand_type_equal (&i.types[0], &regymm)));
4997 if (i.op[0].regs->reg_num != 0)
4998 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L
4999
5000 for (j = 1; j < i.operands; j++)
5001 {
5002 i.op[j - 1] = i.op[j];
5003 i.types[j - 1] = i.types[j];
5004
5005 /* We need to adjust fields in i.tm since they are used by
5006 build_modrm_byte. */
5007 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5008 }
5009
e2ec9d29
L
5010 i.operands--;
5011 i.reg_operands--;
e2ec9d29
L
5012 i.tm.operands--;
5013 }
5014 else if (i.tm.opcode_modifier.regkludge)
5015 {
5016 /* The imul $imm, %reg instruction is converted into
5017 imul $imm, %reg, %reg, and the clr %reg instruction
5018 is converted into xor %reg, %reg. */
5019
5020 unsigned int first_reg_op;
5021
5022 if (operand_type_check (i.types[0], reg))
5023 first_reg_op = 0;
5024 else
5025 first_reg_op = 1;
5026 /* Pretend we saw the extra register operand. */
5027 assert (i.reg_operands == 1
5028 && i.op[first_reg_op + 1].regs == 0);
5029 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5030 i.types[first_reg_op + 1] = i.types[first_reg_op];
5031 i.operands++;
5032 i.reg_operands++;
29b0f896
AM
5033 }
5034
40fb9820 5035 if (i.tm.opcode_modifier.shortform)
29b0f896 5036 {
40fb9820
L
5037 if (i.types[0].bitfield.sreg2
5038 || i.types[0].bitfield.sreg3)
29b0f896 5039 {
4eed87de
AM
5040 if (i.tm.base_opcode == POP_SEG_SHORT
5041 && i.op[0].regs->reg_num == 1)
29b0f896 5042 {
a87af027 5043 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5044 return 0;
29b0f896 5045 }
4eed87de
AM
5046 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5047 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5048 i.rex |= REX_B;
4eed87de
AM
5049 }
5050 else
5051 {
85f10a01
MM
5052 /* The register or float register operand is in operand
5053 0 or 1. */
40fb9820
L
5054 unsigned int op;
5055
5056 if (i.types[0].bitfield.floatreg
5057 || operand_type_check (i.types[0], reg))
5058 op = 0;
5059 else
5060 op = 1;
4eed87de
AM
5061 /* Register goes in low 3 bits of opcode. */
5062 i.tm.base_opcode |= i.op[op].regs->reg_num;
5063 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5064 i.rex |= REX_B;
40fb9820 5065 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5066 {
4eed87de
AM
5067 /* Warn about some common errors, but press on regardless.
5068 The first case can be generated by gcc (<= 2.8.1). */
5069 if (i.operands == 2)
5070 {
5071 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5072 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB
5073 register_prefix, i.op[!intel_syntax].regs->reg_name,
5074 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM
5075 }
5076 else
5077 {
5078 /* Extraneous `l' suffix on fp insn. */
a540244d
L
5079 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5080 register_prefix, i.op[0].regs->reg_name);
4eed87de 5081 }
29b0f896
AM
5082 }
5083 }
5084 }
40fb9820 5085 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM
5086 {
5087 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM
5088 must be put into the modrm byte). Now, we make the modrm and
5089 index base bytes based on all the info we've collected. */
29b0f896
AM
5090
5091 default_seg = build_modrm_byte ();
5092 }
8a2ed489 5093 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM
5094 {
5095 default_seg = &ds;
5096 }
40fb9820 5097 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM
5098 {
5099 /* For the string instructions that allow a segment override
5100 on one of their operands, the default segment is ds. */
5101 default_seg = &ds;
5102 }
5103
75178d9d
L
5104 if (i.tm.base_opcode == 0x8d /* lea */
5105 && i.seg[0]
5106 && !quiet_warnings)
30123838 5107 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM
5108
5109 /* If a segment was explicitly specified, and the specified segment
5110 is not the default, use an opcode prefix to select it. If we
5111 never figured out what the default segment is, then default_seg
5112 will be zero at this point, and the specified segment prefix will
5113 always be used. */
29b0f896
AM
5114 if ((i.seg[0]) && (i.seg[0] != default_seg))
5115 {
5116 if (!add_prefix (i.seg[0]->seg_prefix))
5117 return 0;
5118 }
5119 return 1;
5120}
5121
5122static const seg_entry *
e3bb37b5 5123build_modrm_byte (void)
29b0f896
AM
5124{
5125 const seg_entry *default_seg = 0;
c0f3af97
L
5126 unsigned int source, dest;
5127 int vex_3_sources;
5128
5129 /* The first operand of instructions with VEX prefix and 3 sources
5130 must be VEX_Imm4. */
5131 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5132 if (vex_3_sources)
5133 {
5134 unsigned int nds, reg;
5135
0bfee649 5136 dest = i.operands - 1;
c0f3af97 5137 nds = dest - 1;
0bfee649
L
5138 source = 1;
5139 reg = 0;
5140
5141 /* This instruction must have 4 operands: 4 register operands
5142 or 3 register operands plus 1 memory operand. It must have
5143 VexNDS and VexImmExt. */
5144 assert (i.operands == 4
5145 && (i.reg_operands == 4
5146 || (i.reg_operands == 3 && i.mem_operands == 1))
5147 && i.tm.opcode_modifier.vexnds
5148 && i.tm.opcode_modifier.veximmext
5149 && (operand_type_equal (&i.tm.operand_types[dest],
5150 &regxmm)
5151 || operand_type_equal (&i.tm.operand_types[dest],
5152 &regymm))
5153 && (operand_type_equal (&i.tm.operand_types[nds],
5154 &regxmm)
5155 || operand_type_equal (&i.tm.operand_types[nds],
5156 &regymm))
5157 && (operand_type_equal (&i.tm.operand_types[reg],
5158 &regxmm)
c0f3af97 5159 || operand_type_equal (&i.tm.operand_types[reg],
0bfee649 5160 &regymm)));
c0f3af97 5161
0bfee649
L
5162 /* Generate an 8bit immediate operand to encode the register
5163 operand. */
5164 expressionS *exp = &im_expressions[i.imm_operands++];
5165 i.op[i.operands].imms = exp;
5166 i.types[i.operands] = imm8;
5167 i.operands++;
5168 exp->X_op = O_constant;
5169 exp->X_add_number
5170 = ((i.op[0].regs->reg_num
5171 + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 5172
dae39acc 5173 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L
5174 }
5175 else
5176 source = dest = 0;
29b0f896 5177
85f10a01
MM
5178 /* SSE5 4 operand instructions are encoded in such a way that one of
5179 the inputs must match the destination register. Process_drex hides
5180 the 3rd argument in the drex field, so that by the time we get
5181 here, it looks to GAS as if this is a 2 operand instruction. */
5182 if ((i.tm.opcode_modifier.drex
5183 || i.tm.opcode_modifier.drexv
b5016f89 5184 || i.tm.opcode_modifier.drexc)
85f10a01
MM
5185 && i.reg_operands == 2)
5186 {
5187 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5188 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5189
5190 i.rm.reg = reg->reg_num;
5191 i.rm.regmem = regmem->reg_num;
5192 i.rm.mode = 3;
5193 if ((reg->reg_flags & RegRex) != 0)
5194 i.rex |= REX_R;
5195 if ((regmem->reg_flags & RegRex) != 0)
5196 i.rex |= REX_B;
5197 }
5198
29b0f896 5199 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L
5200 implicit registers do not count. If there are 3 register
5201 operands, it must be a instruction with VexNDS. For a
5202 instruction with VexNDD, the destination register is encoded
5203 in VEX prefix. If there are 4 register operands, it must be
5204 a instruction with VEX prefix and 3 sources. */
5205 else if (i.mem_operands == 0
5206 && ((i.reg_operands == 2
5207 && !i.tm.opcode_modifier.vexndd)
5208 || (i.reg_operands == 3
5209 && i.tm.opcode_modifier.vexnds)
5210 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5211 {
cab737b9
L
5212 switch (i.operands)
5213 {
5214 case 2:
5215 source = 0;
5216 break;
5217 case 3:
c81128dc
L
5218 /* When there are 3 operands, one of them may be immediate,
5219 which may be the first or the last operand. Otherwise,
c0f3af97
L
5220 the first operand must be shift count register (cl) or it
5221 is an instruction with VexNDS. */
c81128dc
L
5222 assert (i.imm_operands == 1
5223 || (i.imm_operands == 0
c0f3af97
L
5224 && (i.tm.opcode_modifier.vexnds
5225 || i.types[0].bitfield.shiftcount)));
40fb9820
L
5226 if (operand_type_check (i.types[0], imm)
5227 || i.types[0].bitfield.shiftcount)
5228 source = 1;
5229 else
5230 source = 0;
cab737b9
L
5231 break;
5232 case 4:
368d64cc
L
5233 /* When there are 4 operands, the first two must be 8bit
5234 immediate operands. The source operand will be the 3rd
c0f3af97
L
5235 one.
5236
5237 For instructions with VexNDS, if the first operand
5238 an imm8, the source operand is the 2nd one. If the last
5239 operand is imm8, the source operand is the first one. */
5240 assert ((i.imm_operands == 2
5241 && i.types[0].bitfield.imm8
5242 && i.types[1].bitfield.imm8)
5243 || (i.tm.opcode_modifier.vexnds
5244 && i.imm_operands == 1
5245 && (i.types[0].bitfield.imm8
5246 || i.types[i.operands - 1].bitfield.imm8)));
5247 if (i.tm.opcode_modifier.vexnds)
5248 {
5249 if (i.types[0].bitfield.imm8)
5250 source = 1;
5251 else
5252 source = 0;
5253 }
5254 else
5255 source = 2;
5256 break;
5257 case 5:
cab737b9
L
5258 break;
5259 default:
5260 abort ();
5261 }
5262
c0f3af97
L
5263 if (!vex_3_sources)
5264 {
5265 dest = source + 1;
5266
5267 if (i.tm.opcode_modifier.vexnds)
5268 {
5269 /* For instructions with VexNDS, the register-only
5270 source operand must be XMM or YMM register. It is
fa99fab2
L
5271 encoded in VEX prefix. We need to clear RegMem bit
5272 before calling operand_type_equal. */
5273 i386_operand_type op = i.tm.operand_types[dest];
5274 op.bitfield.regmem = 0;
c0f3af97 5275 if ((dest + 1) >= i.operands
fa99fab2
L
5276 || (!operand_type_equal (&op, &regxmm)
5277 && !operand_type_equal (&op, &regymm)))
c0f3af97
L
5278 abort ();
5279 i.vex.register_specifier = i.op[dest].regs;
5280 dest++;
5281 }
5282 }
29b0f896
AM
5283
5284 i.rm.mode = 3;
5285 /* One of the register operands will be encoded in the i.tm.reg
5286 field, the other in the combined i.tm.mode and i.tm.regmem
5287 fields. If no form of this instruction supports a memory
5288 destination operand, then we assume the source operand may
5289 sometimes be a memory operand and so we need to store the
5290 destination in the i.rm.reg field. */
40fb9820
L
5291 if (!i.tm.operand_types[dest].bitfield.regmem
5292 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM
5293 {
5294 i.rm.reg = i.op[dest].regs->reg_num;
5295 i.rm.regmem = i.op[source].regs->reg_num;
5296 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5297 i.rex |= REX_R;
29b0f896 5298 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5299 i.rex |= REX_B;
29b0f896
AM
5300 }
5301 else
5302 {
5303 i.rm.reg = i.op[source].regs->reg_num;
5304 i.rm.regmem = i.op[dest].regs->reg_num;
5305 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5306 i.rex |= REX_B;
29b0f896 5307 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5308 i.rex |= REX_R;
29b0f896 5309 }
161a04f6 5310 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5311 {
40fb9820
L
5312 if (!i.types[0].bitfield.control
5313 && !i.types[1].bitfield.control)
c4a530c5 5314 abort ();
161a04f6 5315 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB
5316 add_prefix (LOCK_PREFIX_OPCODE);
5317 }
29b0f896
AM
5318 }
5319 else
5320 { /* If it's not 2 reg operands... */
c0f3af97
L
5321 unsigned int mem;
5322
29b0f896
AM
5323 if (i.mem_operands)
5324 {
5325 unsigned int fake_zero_displacement = 0;
99018f42 5326 unsigned int op;
4eed87de 5327
85f10a01
MM
5328 /* This has been precalculated for SSE5 instructions
5329 that have a DREX field earlier in process_drex. */
b5016f89
L
5330 if (i.tm.opcode_modifier.drex
5331 || i.tm.opcode_modifier.drexv
5332 || i.tm.opcode_modifier.drexc)
85f10a01
MM
5333 op = i.drex.modrm_regmem;
5334 else
5335 {
c0209578
L
5336 for (op = 0; op < i.operands; op++)
5337 if (operand_type_check (i.types[op], anymem))
5338 break;
5339 assert (op < i.operands);
85f10a01 5340 }
29b0f896
AM
5341
5342 default_seg = &ds;
5343
5344 if (i.base_reg == 0)
5345 {
5346 i.rm.mode = 0;
5347 if (!i.disp_operands)
5348 fake_zero_displacement = 1;
5349 if (i.index_reg == 0)
5350 {
5351 /* Operand is just <disp> */
20f0a1fc 5352 if (flag_code == CODE_64BIT)
29b0f896
AM
5353 {
5354 /* 64bit mode overwrites the 32bit absolute
5355 addressing by RIP relative addressing and
5356 absolute addressing is encoded by one of the
5357 redundant SIB forms. */
5358 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5359 i.sib.base = NO_BASE_REGISTER;
5360 i.sib.index = NO_INDEX_REGISTER;
fc225355 5361 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5362 ? disp32s : disp32);
20f0a1fc 5363 }
fc225355
L
5364 else if ((flag_code == CODE_16BIT)
5365 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC
5366 {
5367 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5368 i.types[op] = disp16;
20f0a1fc
NC
5369 }
5370 else
5371 {
5372 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5373 i.types[op] = disp32;
29b0f896
AM
5374 }
5375 }
5376 else /* !i.base_reg && i.index_reg */
5377 {
db51cc60
L
5378 if (i.index_reg->reg_num == RegEiz
5379 || i.index_reg->reg_num == RegRiz)
5380 i.sib.index = NO_INDEX_REGISTER;
5381 else
5382 i.sib.index = i.index_reg->reg_num;
29b0f896
AM
5383 i.sib.base = NO_BASE_REGISTER;
5384 i.sib.scale = i.log2_scale_factor;
5385 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L
5386 i.types[op].bitfield.disp8 = 0;
5387 i.types[op].bitfield.disp16 = 0;
5388 i.types[op].bitfield.disp64 = 0;
29b0f896 5389 if (flag_code != CODE_64BIT)
40fb9820
L
5390 {
5391 /* Must be 32 bit */
5392 i.types[op].bitfield.disp32 = 1;
5393 i.types[op].bitfield.disp32s = 0;
5394 }
29b0f896 5395 else
40fb9820
L
5396 {
5397 i.types[op].bitfield.disp32 = 0;
5398 i.types[op].bitfield.disp32s = 1;
5399 }
29b0f896 5400 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5401 i.rex |= REX_X;
29b0f896
AM
5402 }
5403 }
5404 /* RIP addressing for 64bit mode. */
9a04903e
JB
5405 else if (i.base_reg->reg_num == RegRip ||
5406 i.base_reg->reg_num == RegEip)
29b0f896
AM
5407 {
5408 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L
5409 i.types[op].bitfield.disp8 = 0;
5410 i.types[op].bitfield.disp16 = 0;
5411 i.types[op].bitfield.disp32 = 0;
5412 i.types[op].bitfield.disp32s = 1;
5413 i.types[op].bitfield.disp64 = 0;
71903a11 5414 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC
5415 if (! i.disp_operands)
5416 fake_zero_displacement = 1;
29b0f896 5417 }
40fb9820 5418 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM
5419 {
5420 switch (i.base_reg->reg_num)
5421 {
5422 case 3: /* (%bx) */
5423 if (i.index_reg == 0)
5424 i.rm.regmem = 7;
5425 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5426 i.rm.regmem = i.index_reg->reg_num - 6;
5427 break;
5428 case 5: /* (%bp) */
5429 default_seg = &ss;
5430 if (i.index_reg == 0)
5431 {
5432 i.rm.regmem = 6;
40fb9820 5433 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM
5434 {
5435 /* fake (%bp) into 0(%bp) */
40fb9820 5436 i.types[op].bitfield.disp8 = 1;
252b5132 5437 fake_zero_displacement = 1;
29b0f896
AM
5438 }
5439 }
5440 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5441 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5442 break;
5443 default: /* (%si) -> 4 or (%di) -> 5 */
5444 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5445 }
5446 i.rm.mode = mode_from_disp_size (i.types[op]);
5447 }
5448 else /* i.base_reg and 32/64 bit mode */
5449 {
5450 if (flag_code == CODE_64BIT
40fb9820
L
5451 && operand_type_check (i.types[op], disp))
5452 {
5453 i386_operand_type temp;
0dfbf9d7 5454 operand_type_set (&temp, 0);
40fb9820
L
5455 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5456 i.types[op] = temp;
5457 if (i.prefix[ADDR_PREFIX] == 0)
5458 i.types[op].bitfield.disp32s = 1;
5459 else
5460 i.types[op].bitfield.disp32 = 1;
5461 }
20f0a1fc 5462
29b0f896
AM
5463 i.rm.regmem = i.base_reg->reg_num;
5464 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5465 i.rex |= REX_B;
29b0f896
AM
5466 i.sib.base = i.base_reg->reg_num;
5467 /* x86-64 ignores REX prefix bit here to avoid decoder
5468 complications. */
5469 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5470 {
5471 default_seg = &ss;
5472 if (i.disp_operands == 0)
5473 {
5474 fake_zero_displacement = 1;
40fb9820 5475 i.types[op].bitfield.disp8 = 1;
29b0f896
AM
5476 }
5477 }
5478 else if (i.base_reg->reg_num == ESP_REG_NUM)
5479 {
5480 default_seg = &ss;
5481 }
5482 i.sib.scale = i.log2_scale_factor;
5483 if (i.index_reg == 0)
5484 {
5485 /* <disp>(%esp) becomes two byte modrm with no index
5486 register. We've already stored the code for esp
5487 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5488 Any base register besides %esp will not use the
5489 extra modrm byte. */
5490 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM
5491 }
5492 else
5493 {
db51cc60
L
5494 if (i.index_reg->reg_num == RegEiz
5495 || i.index_reg->reg_num == RegRiz)
5496 i.sib.index = NO_INDEX_REGISTER;
5497 else
5498 i.sib.index = i.index_reg->reg_num;
29b0f896
AM
5499 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5500 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5501 i.rex |= REX_X;
29b0f896 5502 }
67a4f2b7
AO
5503
5504 if (i.disp_operands
5505 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5506 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5507 i.rm.mode = 0;
5508 else
5509 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5510 }
252b5132 5511
29b0f896
AM
5512 if (fake_zero_displacement)
5513 {
5514 /* Fakes a zero displacement assuming that i.types[op]
5515 holds the correct displacement size. */
5516 expressionS *exp;
5517
5518 assert (i.op[op].disps == 0);
5519 exp = &disp_expressions[i.disp_operands++];
5520 i.op[op].disps = exp;
5521 exp->X_op = O_constant;
5522 exp->X_add_number = 0;
5523 exp->X_add_symbol = (symbolS *) 0;
5524 exp->X_op_symbol = (symbolS *) 0;
5525 }
c0f3af97
L
5526
5527 mem = op;
29b0f896 5528 }
c0f3af97
L
5529 else
5530 mem = ~0;
252b5132 5531
29b0f896
AM
5532 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5533 (if any) based on i.tm.extension_opcode. Again, we must be
5534 careful to make sure that segment/control/debug/test/MMX
5535 registers are coded into the i.rm.reg field. */
5536 if (i.reg_operands)
5537 {
99018f42
L
5538 unsigned int op;
5539
85f10a01
MM
5540 /* This has been precalculated for SSE5 instructions
5541 that have a DREX field earlier in process_drex. */
b5016f89
L
5542 if (i.tm.opcode_modifier.drex
5543 || i.tm.opcode_modifier.drexv
5544 || i.tm.opcode_modifier.drexc)
85f10a01
MM
5545 {
5546 op = i.drex.modrm_reg;
5547 i.rm.reg = i.op[op].regs->reg_num;
5548 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5549 i.rex |= REX_R;
5550 }
5551 else
5552 {
c0f3af97
L
5553 unsigned int vex_reg = ~0;
5554
c0209578
L
5555 for (op = 0; op < i.operands; op++)
5556 if (i.types[op].bitfield.reg8
5557 || i.types[op].bitfield.reg16
5558 || i.types[op].bitfield.reg32
5559 || i.types[op].bitfield.reg64
5560 || i.types[op].bitfield.regmmx
5561 || i.types[op].bitfield.regxmm
c0f3af97 5562 || i.types[op].bitfield.regymm
c0209578
L
5563 || i.types[op].bitfield.sreg2
5564 || i.types[op].bitfield.sreg3
5565 || i.types[op].bitfield.control
5566 || i.types[op].bitfield.debug
5567 || i.types[op].bitfield.test)
5568 break;
5569
c0f3af97
L
5570 if (vex_3_sources)
5571 op = dest;
5572 else if (i.tm.opcode_modifier.vexnds)
5573 {
5574 /* For instructions with VexNDS, the register-only
5575 source operand is encoded in VEX prefix. */
5576 assert (mem != (unsigned int) ~0);
5577
5578 if (op > mem)
5579 {
5580 vex_reg = op++;
5581 assert (op < i.operands);
5582 }
5583 else
5584 {
5585 vex_reg = op + 1;
5586 assert (vex_reg < i.operands);
5587 }
5588 }
5589 else if (i.tm.opcode_modifier.vexndd)
5590 {
5591 /* For instructions with VexNDD, there should be
5592 no memory operand and the register destination
5593 is encoded in VEX prefix. */
5594 assert (i.mem_operands == 0
5595 && (op + 2) == i.operands);
5596 vex_reg = op + 1;
5597 }
5598 else
5599 assert (op < i.operands);
5600
5601 if (vex_reg != (unsigned int) ~0)
5602 {
5603 assert (i.reg_operands == 2);
5604
5605 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5606 & regxmm)
5607 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5608 &regymm))
5609 abort ();
5610 i.vex.register_specifier = i.op[vex_reg].regs;
5611 }
99018f42 5612
85f10a01
MM
5613 /* If there is an extension opcode to put here, the
5614 register number must be put into the regmem field. */
c0209578
L
5615 if (i.tm.extension_opcode != None)
5616 {
5617 i.rm.regmem = i.op[op].regs->reg_num;
5618 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5619 i.rex |= REX_B;
5620 }
5621 else
5622 {
5623 i.rm.reg = i.op[op].regs->reg_num;
5624 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5625 i.rex |= REX_R;
5626 }
85f10a01 5627 }
252b5132 5628
29b0f896
AM
5629 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5630 must set it to 3 to indicate this is a register operand
5631 in the regmem field. */
5632 if (!i.mem_operands)
5633 i.rm.mode = 3;
5634 }
252b5132 5635
29b0f896 5636 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM
5637 if (i.tm.extension_opcode != None
5638 && !(i.tm.opcode_modifier.drex
5639 || i.tm.opcode_modifier.drexv
5640 || i.tm.opcode_modifier.drexc))
29b0f896
AM
5641 i.rm.reg = i.tm.extension_opcode;
5642 }
5643 return default_seg;
5644}
252b5132 5645
29b0f896 5646static void
e3bb37b5 5647output_branch (void)
29b0f896
AM
5648{
5649 char *p;
5650 int code16;
5651 int prefix;
5652 relax_substateT subtype;
5653 symbolS *sym;
5654 offsetT off;
5655
5656 code16 = 0;
5657 if (flag_code == CODE_16BIT)
5658 code16 = CODE16;
5659
5660 prefix = 0;
5661 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5662 {
29b0f896
AM
5663 prefix = 1;
5664 i.prefixes -= 1;
5665 code16 ^= CODE16;
252b5132 5666 }
29b0f896
AM
5667 /* Pentium4 branch hints. */
5668 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5669 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5670 {
29b0f896
AM
5671 prefix++;
5672 i.prefixes--;
5673 }
5674 if (i.prefix[REX_PREFIX] != 0)
5675 {
5676 prefix++;
5677 i.prefixes--;
2f66722d
AM
5678 }
5679
29b0f896
AM
5680 if (i.prefixes != 0 && !intel_syntax)
5681 as_warn (_("skipping prefixes on this instruction"));
5682
5683 /* It's always a symbol; End frag & setup for relax.
5684 Make sure there is enough room in this frag for the largest
5685 instruction we may generate in md_convert_frag. This is 2
5686 bytes for the opcode and room for the prefix and largest
5687 displacement. */
5688 frag_grow (prefix + 2 + 4);
5689 /* Prefix and 1 opcode byte go in fr_fix. */
5690 p = frag_more (prefix + 1);
5691 if (i.prefix[DATA_PREFIX] != 0)
5692 *p++ = DATA_PREFIX_OPCODE;
5693 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5694 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5695 *p++ = i.prefix[SEG_PREFIX];
5696 if (i.prefix[REX_PREFIX] != 0)
5697 *p++ = i.prefix[REX_PREFIX];
5698 *p = i.tm.base_opcode;
5699
5700 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5701 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5702 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM
5703 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5704 else
5705 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5706 subtype |= code16;
3e73aa7c 5707
29b0f896
AM
5708 sym = i.op[0].disps->X_add_symbol;
5709 off = i.op[0].disps->X_add_number;
3e73aa7c 5710
29b0f896
AM
5711 if (i.op[0].disps->X_op != O_constant
5712 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5713 {
29b0f896
AM
5714 /* Handle complex expressions. */
5715 sym = make_expr_symbol (i.op[0].disps);
5716 off = 0;
5717 }
3e73aa7c 5718
29b0f896
AM
5719 /* 1 possible extra opcode + 4 byte displacement go in var part.
5720 Pass reloc in fr_var. */
5721 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5722}
3e73aa7c 5723
29b0f896 5724static void
e3bb37b5 5725output_jump (void)
29b0f896
AM
5726{
5727 char *p;
5728 int size;
3e02c1cc 5729 fixS *fixP;
29b0f896 5730
40fb9820 5731 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM
5732 {
5733 /* This is a loop or jecxz type instruction. */
5734 size = 1;
5735 if (i.prefix[ADDR_PREFIX] != 0)
5736 {
5737 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5738 i.prefixes -= 1;
5739 }
5740 /* Pentium4 branch hints. */
5741 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5742 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5743 {
5744 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5745 i.prefixes--;
3e73aa7c
JH
5746 }
5747 }
29b0f896
AM
5748 else
5749 {
5750 int code16;
3e73aa7c 5751
29b0f896
AM
5752 code16 = 0;
5753 if (flag_code == CODE_16BIT)
5754 code16 = CODE16;
3e73aa7c 5755
29b0f896
AM
5756 if (i.prefix[DATA_PREFIX] != 0)
5757 {
5758 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5759 i.prefixes -= 1;
5760 code16 ^= CODE16;
5761 }
252b5132 5762
29b0f896
AM
5763 size = 4;
5764 if (code16)
5765 size = 2;
5766 }
9fcc94b6 5767
29b0f896
AM
5768 if (i.prefix[REX_PREFIX] != 0)
5769 {
5770 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5771 i.prefixes -= 1;
5772 }
252b5132 5773
29b0f896
AM
5774 if (i.prefixes != 0 && !intel_syntax)
5775 as_warn (_("skipping prefixes on this instruction"));
e0890092 5776
29b0f896
AM
5777 p = frag_more (1 + size);
5778 *p++ = i.tm.base_opcode;
e0890092 5779
3e02c1cc
AM
5780 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5781 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5782
5783 /* All jumps handled here are signed, but don't use a signed limit
5784 check for 32 and 16 bit jumps as we want to allow wrap around at
5785 4G and 64k respectively. */
5786 if (size == 1)
5787 fixP->fx_signed = 1;
29b0f896 5788}
e0890092 5789
29b0f896 5790static void
e3bb37b5 5791output_interseg_jump (void)
29b0f896
AM
5792{
5793 char *p;
5794 int size;
5795 int prefix;
5796 int code16;
252b5132 5797
29b0f896
AM
5798 code16 = 0;
5799 if (flag_code == CODE_16BIT)
5800 code16 = CODE16;
a217f122 5801
29b0f896
AM
5802 prefix = 0;
5803 if (i.prefix[DATA_PREFIX] != 0)
5804 {
5805 prefix = 1;
5806 i.prefixes -= 1;
5807 code16 ^= CODE16;
5808 }
5809 if (i.prefix[REX_PREFIX] != 0)
5810 {
5811 prefix++;
5812 i.prefixes -= 1;
5813 }
252b5132 5814
29b0f896
AM
5815 size = 4;
5816 if (code16)
5817 size = 2;
252b5132 5818
29b0f896
AM
5819 if (i.prefixes != 0 && !intel_syntax)
5820 as_warn (_("skipping prefixes on this instruction"));
252b5132 5821
29b0f896
AM
5822 /* 1 opcode; 2 segment; offset */
5823 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5824
29b0f896
AM
5825 if (i.prefix[DATA_PREFIX] != 0)
5826 *p++ = DATA_PREFIX_OPCODE;
252b5132 5827
29b0f896
AM
5828 if (i.prefix[REX_PREFIX] != 0)
5829 *p++ = i.prefix[REX_PREFIX];
252b5132 5830
29b0f896
AM
5831 *p++ = i.tm.base_opcode;
5832 if (i.op[1].imms->X_op == O_constant)
5833 {
5834 offsetT n = i.op[1].imms->X_add_number;
252b5132 5835
29b0f896
AM
5836 if (size == 2
5837 && !fits_in_unsigned_word (n)
5838 && !fits_in_signed_word (n))
5839 {
5840 as_bad (_("16-bit jump out of range"));
5841 return;
5842 }
5843 md_number_to_chars (p, n, size);
5844 }
5845 else
5846 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5847 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5848 if (i.op[0].imms->X_op != O_constant)
5849 as_bad (_("can't handle non absolute segment in `%s'"),
5850 i.tm.name);
5851 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5852}
a217f122 5853
29b0f896 5854static void
e3bb37b5 5855output_insn (void)
29b0f896 5856{
2bbd9c25
JJ
5857 fragS *insn_start_frag;
5858 offsetT insn_start_off;
5859
29b0f896
AM
5860 /* Tie dwarf2 debug info to the address at the start of the insn.
5861 We can't do this after the insn has been output as the current
5862 frag may have been closed off. eg. by frag_var. */
5863 dwarf2_emit_insn (0);
5864
2bbd9c25
JJ
5865 insn_start_frag = frag_now;
5866 insn_start_off = frag_now_fix ();
5867
29b0f896 5868 /* Output jumps. */
40fb9820 5869 if (i.tm.opcode_modifier.jump)
29b0f896 5870 output_branch ();
40fb9820
L
5871 else if (i.tm.opcode_modifier.jumpbyte
5872 || i.tm.opcode_modifier.jumpdword)
29b0f896 5873 output_jump ();
40fb9820 5874 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM
5875 output_interseg_jump ();
5876 else
5877 {
5878 /* Output normal instructions here. */
5879 char *p;
5880 unsigned char *q;
47465058 5881 unsigned int j;
331d2d0d 5882 unsigned int prefix;
4dffcebc 5883
c0f3af97
L
5884 /* Since the VEX prefix contains the implicit prefix, we don't
5885 need the explicit prefix. */
5886 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5887 {
c0f3af97 5888 switch (i.tm.opcode_length)
bc4bd9ab 5889 {
c0f3af97
L
5890 case 3:
5891 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5892 {
c0f3af97
L
5893 prefix = (i.tm.base_opcode >> 24) & 0xff;
5894 goto check_prefix;
5895 }
5896 break;
5897 case 2:
5898 if ((i.tm.base_opcode & 0xff0000) != 0)
5899 {
5900 prefix = (i.tm.base_opcode >> 16) & 0xff;
5901 if (i.tm.cpu_flags.bitfield.cpupadlock)
5902 {
4dffcebc 5903check_prefix:
c0f3af97
L
5904 if (prefix != REPE_PREFIX_OPCODE
5905 || (i.prefix[LOCKREP_PREFIX]
5906 != REPE_PREFIX_OPCODE))
5907 add_prefix (prefix);
5908 }
5909 else
4dffcebc
L
5910 add_prefix (prefix);
5911 }
c0f3af97
L
5912 break;
5913 case 1:
5914 break;
5915 default:
5916 abort ();
bc4bd9ab 5917 }
c0f3af97
L
5918
5919 /* The prefix bytes. */
5920 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5921 if (*q)
5922 FRAG_APPEND_1_CHAR (*q);
0f10071e 5923 }
252b5132 5924
c0f3af97
L
5925 if (i.tm.opcode_modifier.vex)
5926 {
5927 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5928 if (*q)
5929 switch (j)
5930 {
5931 case REX_PREFIX:
5932 /* REX byte is encoded in VEX prefix. */
5933 break;
5934 case SEG_PREFIX:
5935 case ADDR_PREFIX:
5936 FRAG_APPEND_1_CHAR (*q);
5937 break;
5938 default:
5939 /* There should be no other prefixes for instructions
5940 with VEX prefix. */
5941 abort ();
5942 }
5943
5944 /* Now the VEX prefix. */
5945 p = frag_more (i.vex.length);
5946 for (j = 0; j < i.vex.length; j++)
5947 p[j] = i.vex.bytes[j];
5948 }
252b5132 5949
29b0f896 5950 /* Now the opcode; be careful about word order here! */
4dffcebc 5951 if (i.tm.opcode_length == 1)
29b0f896
AM
5952 {
5953 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5954 }
5955 else
5956 {
4dffcebc 5957 switch (i.tm.opcode_length)
331d2d0d 5958 {
4dffcebc 5959 case 3:
331d2d0d
L
5960 p = frag_more (3);
5961 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L
5962 break;
5963 case 2:
5964 p = frag_more (2);
5965 break;
5966 default:
5967 abort ();
5968 break;
331d2d0d 5969 }
0f10071e 5970
29b0f896
AM
5971 /* Put out high byte first: can't use md_number_to_chars! */
5972 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5973 *p = i.tm.base_opcode & 0xff;
85f10a01
MM
5974
5975 /* On SSE5, encode the OC1 bit in the DREX field if this
5976 encoding has multiple formats. */
5977 if (i.tm.opcode_modifier.drex
5978 && i.tm.opcode_modifier.drexv
5979 && DREX_OC1 (i.tm.extension_opcode))
5980 *p |= DREX_OC1_MASK;
29b0f896 5981 }
3e73aa7c 5982
29b0f896 5983 /* Now the modrm byte and sib byte (if present). */
40fb9820 5984 if (i.tm.opcode_modifier.modrm)
29b0f896 5985 {
4a3523fa
L
5986 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5987 | i.rm.reg << 3
5988 | i.rm.mode << 6));
29b0f896
AM
5989 /* If i.rm.regmem == ESP (4)
5990 && i.rm.mode != (Register mode)
5991 && not 16 bit
5992 ==> need second modrm byte. */
5993 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5994 && i.rm.mode != 3
40fb9820 5995 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L
5996 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5997 | i.sib.index << 3
5998 | i.sib.scale << 6));
29b0f896 5999 }
3e73aa7c 6000
85f10a01
MM
6001 /* Write the DREX byte if needed. */
6002 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
6003 {
6004 p = frag_more (1);
6005 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
6006
6007 /* Encode the OC0 bit if this encoding has multiple
6008 formats. */
6009 if ((i.tm.opcode_modifier.drex
6010 || i.tm.opcode_modifier.drexv)
6011 && DREX_OC0 (i.tm.extension_opcode))
6012 *p |= DREX_OC0_MASK;
6013 }
6014
29b0f896 6015 if (i.disp_operands)
2bbd9c25 6016 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6017
29b0f896 6018 if (i.imm_operands)
2bbd9c25 6019 output_imm (insn_start_frag, insn_start_off);
29b0f896 6020 }
252b5132 6021
29b0f896
AM
6022#ifdef DEBUG386
6023 if (flag_debug)
6024 {
7b81dfbb 6025 pi ("" /*line*/, &i);
29b0f896
AM
6026 }
6027#endif /* DEBUG386 */
6028}
252b5132 6029
e205caa7
L
6030/* Return the size of the displacement operand N. */
6031
6032static int
6033disp_size (unsigned int n)
6034{
6035 int size = 4;
40fb9820
L
6036 if (i.types[n].bitfield.disp64)
6037 size = 8;
6038 else if (i.types[n].bitfield.disp8)
6039 size = 1;
6040 else if (i.types[n].bitfield.disp16)
6041 size = 2;
e205caa7
L
6042 return size;
6043}
6044
6045/* Return the size of the immediate operand N. */
6046
6047static int
6048imm_size (unsigned int n)
6049{
6050 int size = 4;
40fb9820
L
6051 if (i.types[n].bitfield.imm64)
6052 size = 8;
6053 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6054 size = 1;
6055 else if (i.types[n].bitfield.imm16)
6056 size = 2;
e205caa7
L
6057 return size;
6058}
6059
29b0f896 6060static void
64e74474 6061output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM
6062{
6063 char *p;
6064 unsigned int n;
252b5132 6065
29b0f896
AM
6066 for (n = 0; n < i.operands; n++)
6067 {
40fb9820 6068 if (operand_type_check (i.types[n], disp))
29b0f896
AM
6069 {
6070 if (i.op[n].disps->X_op == O_constant)
6071 {
e205caa7 6072 int size = disp_size (n);
29b0f896 6073 offsetT val;
252b5132 6074
29b0f896
AM
6075 val = offset_in_range (i.op[n].disps->X_add_number,
6076 size);
6077 p = frag_more (size);
6078 md_number_to_chars (p, val, size);
6079 }
6080 else
6081 {
f86103b7 6082 enum bfd_reloc_code_real reloc_type;
e205caa7 6083 int size = disp_size (n);
40fb9820 6084 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM
6085 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6086
e205caa7 6087 /* We can't have 8 bit displacement here. */
40fb9820 6088 assert (!i.types[n].bitfield.disp8);
e205caa7 6089
29b0f896
AM
6090 /* The PC relative address is computed relative
6091 to the instruction boundary, so in case immediate
6092 fields follows, we need to adjust the value. */
6093 if (pcrel && i.imm_operands)
6094 {
29b0f896 6095 unsigned int n1;
e205caa7 6096 int sz = 0;
252b5132 6097
29b0f896 6098 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6099 if (operand_type_check (i.types[n1], imm))
252b5132 6100 {
e205caa7
L
6101 /* Only one immediate is allowed for PC
6102 relative address. */
6103 assert (sz == 0);
6104 sz = imm_size (n1);
6105 i.op[n].disps->X_add_number -= sz;
252b5132 6106 }
29b0f896 6107 /* We should find the immediate. */
e205caa7 6108 assert (sz != 0);
29b0f896 6109 }
520dc8e8 6110
29b0f896 6111 p = frag_more (size);
2bbd9c25 6112 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6113 if (GOT_symbol
2bbd9c25 6114 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6115 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ
6116 || reloc_type == BFD_RELOC_X86_64_32S
6117 || (reloc_type == BFD_RELOC_64
6118 && object_64bit))
d6ab8113
JB
6119 && (i.op[n].disps->X_op == O_symbol
6120 || (i.op[n].disps->X_op == O_add
6121 && ((symbol_get_value_expression
6122 (i.op[n].disps->X_op_symbol)->X_op)
6123 == O_subtract))))
6124 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ
6125 {
6126 offsetT add;
6127
6128 if (insn_start_frag == frag_now)
6129 add = (p - frag_now->fr_literal) - insn_start_off;
6130 else
6131 {
6132 fragS *fr;
6133
6134 add = insn_start_frag->fr_fix - insn_start_off;
6135 for (fr = insn_start_frag->fr_next;
6136 fr && fr != frag_now; fr = fr->fr_next)
6137 add += fr->fr_fix;
6138 add += p - frag_now->fr_literal;
6139 }
6140
4fa24527 6141 if (!object_64bit)
7b81dfbb
AJ
6142 {
6143 reloc_type = BFD_RELOC_386_GOTPC;
6144 i.op[n].imms->X_add_number += add;
6145 }
6146 else if (reloc_type == BFD_RELOC_64)
6147 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6148 else
7b81dfbb
AJ
6149 /* Don't do the adjustment for x86-64, as there
6150 the pcrel addressing is relative to the _next_
6151 insn, and that is taken care of in other code. */
d6ab8113 6152 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6153 }
062cd5e7 6154 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6155 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM
6156 }
6157 }
6158 }
6159}
252b5132 6160
29b0f896 6161static void
64e74474 6162output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM
6163{
6164 char *p;
6165 unsigned int n;
252b5132 6166
29b0f896
AM
6167 for (n = 0; n < i.operands; n++)
6168 {
40fb9820 6169 if (operand_type_check (i.types[n], imm))
29b0f896
AM
6170 {
6171 if (i.op[n].imms->X_op == O_constant)
6172 {
e205caa7 6173 int size = imm_size (n);
29b0f896 6174 offsetT val;
b4cac588 6175
29b0f896
AM
6176 val = offset_in_range (i.op[n].imms->X_add_number,
6177 size);
6178 p = frag_more (size);
6179 md_number_to_chars (p, val, size);
6180 }
6181 else
6182 {
6183 /* Not absolute_section.
6184 Need a 32-bit fixup (don't support 8bit
6185 non-absolute imms). Try to support other
6186 sizes ... */
f86103b7 6187 enum bfd_reloc_code_real reloc_type;
e205caa7
L
6188 int size = imm_size (n);
6189 int sign;
29b0f896 6190
40fb9820 6191 if (i.types[n].bitfield.imm32s
a7d61044 6192 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6193 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6194 sign = 1;
e205caa7
L
6195 else
6196 sign = 0;
520dc8e8 6197
29b0f896
AM
6198 p = frag_more (size);
6199 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6200
2bbd9c25
JJ
6201 /* This is tough to explain. We end up with this one if we
6202 * have operands that look like
6203 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6204 * obtain the absolute address of the GOT, and it is strongly
6205 * preferable from a performance point of view to avoid using
6206 * a runtime relocation for this. The actual sequence of
6207 * instructions often look something like:
6208 *
6209 * call .L66
6210 * .L66:
6211 * popl %ebx
6212 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6213 *
6214 * The call and pop essentially return the absolute address
6215 * of the label .L66 and store it in %ebx. The linker itself
6216 * will ultimately change the first operand of the addl so
6217 * that %ebx points to the GOT, but to keep things simple, the
6218 * .o file must have this operand set so that it generates not
6219 * the absolute address of .L66, but the absolute address of
6220 * itself. This allows the linker itself simply treat a GOTPC
6221 * relocation as asking for a pcrel offset to the GOT to be
6222 * added in, and the addend of the relocation is stored in the
6223 * operand field for the instruction itself.
6224 *
6225 * Our job here is to fix the operand so that it would add
6226 * the correct offset so that %ebx would point to itself. The
6227 * thing that is tricky is that .-.L66 will point to the
6228 * beginning of the instruction, so we need to further modify
6229 * the operand so that it will point to itself. There are
6230 * other cases where you have something like:
6231 *
6232 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6233 *
6234 * and here no correction would be required. Internally in
6235 * the assembler we treat operands of this form as not being
6236 * pcrel since the '.' is explicitly mentioned, and I wonder
6237 * whether it would simplify matters to do it this way. Who
6238 * knows. In earlier versions of the PIC patches, the
6239 * pcrel_adjust field was used to store the correction, but
6240 * since the expression is not pcrel, I felt it would be
6241 * confusing to do it this way. */
6242
d6ab8113 6243 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ
6244 || reloc_type == BFD_RELOC_X86_64_32S
6245 || reloc_type == BFD_RELOC_64)
29b0f896
AM
6246 && GOT_symbol
6247 && GOT_symbol == i.op[n].imms->X_add_symbol
6248 && (i.op[n].imms->X_op == O_symbol
6249 || (i.op[n].imms->X_op == O_add
6250 && ((symbol_get_value_expression
6251 (i.op[n].imms->X_op_symbol)->X_op)
6252 == O_subtract))))
6253 {
2bbd9c25
JJ
6254 offsetT add;
6255
6256 if (insn_start_frag == frag_now)
6257 add = (p - frag_now->fr_literal) - insn_start_off;
6258 else
6259 {
6260 fragS *fr;
6261
6262 add = insn_start_frag->fr_fix - insn_start_off;
6263 for (fr = insn_start_frag->fr_next;
6264 fr && fr != frag_now; fr = fr->fr_next)
6265 add += fr->fr_fix;
6266 add += p - frag_now->fr_literal;
6267 }
6268
4fa24527 6269 if (!object_64bit)
d6ab8113 6270 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6271 else if (size == 4)
d6ab8113 6272 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ
6273 else if (size == 8)
6274 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6275 i.op[n].imms->X_add_number += add;
29b0f896 6276 }
29b0f896
AM
6277 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6278 i.op[n].imms, 0, reloc_type);
6279 }
6280 }
6281 }
252b5132
RH
6282}
6283\f
d182319b
JB
6284/* x86_cons_fix_new is called via the expression parsing code when a
6285 reloc is needed. We use this hook to get the correct .got reloc. */
6286static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6287static int cons_sign = -1;
6288
6289void
e3bb37b5 6290x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6291 expressionS *exp)
d182319b
JB
6292{
6293 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6294
6295 got_reloc = NO_RELOC;
6296
6297#ifdef TE_PE
6298 if (exp->X_op == O_secrel)
6299 {
6300 exp->X_op = O_symbol;
6301 r = BFD_RELOC_32_SECREL;
6302 }
6303#endif
6304
6305 fix_new_exp (frag, off, len, exp, 0, r);
6306}
6307
718ddfc0
JB
6308#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6309# define lex_got(reloc, adjust, types) NULL
6310#else
f3c180ae
AM
6311/* Parse operands of the form
6312 <symbol>@GOTOFF+<nnn>
6313 and similar .plt or .got references.
6314
6315 If we find one, set up the correct relocation in RELOC and copy the
6316 input string, minus the `@GOTOFF' into a malloc'd buffer for
6317 parsing by the calling routine. Return this buffer, and if ADJUST
6318 is non-null set it to the length of the string we removed from the
6319 input line. Otherwise return NULL. */
6320static char *
3956db08 6321lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6322 int *adjust,
40fb9820 6323 i386_operand_type *types)
f3c180ae 6324{
7b81dfbb
AJ
6325 /* Some of the relocations depend on the size of what field is to
6326 be relocated. But in our callers i386_immediate and i386_displacement
6327 we don't yet know the operand size (this will be set by insn
6328 matching). Hence we record the word32 relocation here,
6329 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM
6330 static const struct {
6331 const char *str;
4fa24527 6332 const enum bfd_reloc_code_real rel[2];
40fb9820 6333 const i386_operand_type types64;
f3c180ae 6334 } gotrel[] = {
4eed87de
AM
6335 { "PLTOFF", { 0,
6336 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6337 OPERAND_TYPE_IMM64 },
4eed87de
AM
6338 { "PLT", { BFD_RELOC_386_PLT32,
6339 BFD_RELOC_X86_64_PLT32 },
40fb9820 6340 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM
6341 { "GOTPLT", { 0,
6342 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6343 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM
6344 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6345 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6346 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM
6347 { "GOTPCREL", { 0,
6348 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6349 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM
6350 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6351 BFD_RELOC_X86_64_TLSGD },
40fb9820 6352 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM
6353 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6354 0 },
40fb9820 6355 OPERAND_TYPE_NONE },
4eed87de
AM
6356 { "TLSLD", { 0,
6357 BFD_RELOC_X86_64_TLSLD },
40fb9820 6358 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM
6359 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6360 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6361 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM
6362 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6363 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6364 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM
6365 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6366 0 },
40fb9820 6367 OPERAND_TYPE_NONE },
4eed87de
AM
6368 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6369 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L
6370
6371 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM
6372 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6373 0 },
40fb9820 6374 OPERAND_TYPE_NONE },
4eed87de
AM
6375 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6376 0 },
40fb9820 6377 OPERAND_TYPE_NONE },
4eed87de
AM
6378 { "GOT", { BFD_RELOC_386_GOT32,
6379 BFD_RELOC_X86_64_GOT32 },
40fb9820 6380 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM
6381 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6382 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6383 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM
6384 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6385 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6386 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM
6387 };
6388 char *cp;
6389 unsigned int j;
6390
718ddfc0
JB
6391 if (!IS_ELF)
6392 return NULL;
6393
f3c180ae 6394 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6395 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM
6396 return NULL;
6397
47465058 6398 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM
6399 {
6400 int len;
6401
6402 len = strlen (gotrel[j].str);
28f81592 6403 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6404 {
4fa24527 6405 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6406 {
28f81592
AM
6407 int first, second;
6408 char *tmpbuf, *past_reloc;
f3c180ae 6409
4fa24527 6410 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM
6411 if (adjust)
6412 *adjust = len;
f3c180ae 6413
3956db08
JB
6414 if (types)
6415 {
6416 if (flag_code != CODE_64BIT)
40fb9820
L
6417 {
6418 types->bitfield.imm32 = 1;
6419 types->bitfield.disp32 = 1;
6420 }
3956db08
JB
6421 else
6422 *types = gotrel[j].types64;
6423 }
6424
f3c180ae
AM
6425 if (GOT_symbol == NULL)
6426 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6427
28f81592 6428 /* The length of the first part of our input line. */
f3c180ae 6429 first = cp - input_line_pointer;
28f81592
AM
6430
6431 /* The second part goes from after the reloc token until
67c11a9b 6432 (and including) an end_of_line char or comma. */
28f81592 6433 past_reloc = cp + 1 + len;
67c11a9b
AM
6434 cp = past_reloc;
6435 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6436 ++cp;
6437 second = cp + 1 - past_reloc;
28f81592
AM
6438
6439 /* Allocate and copy string. The trailing NUL shouldn't
6440 be necessary, but be safe. */
6441 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6442 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM
6443 if (second != 0 && *past_reloc != ' ')
6444 /* Replace the relocation token with ' ', so that
6445 errors like foo@GOTOFF1 will be detected. */
6446 tmpbuf[first++] = ' ';
6447 memcpy (tmpbuf + first, past_reloc, second);
6448 tmpbuf[first + second] = '\0';
f3c180ae
AM
6449 return tmpbuf;
6450 }
6451
4fa24527
JB
6452 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6453 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM
6454 return NULL;
6455 }
6456 }
6457
6458 /* Might be a symbol version string. Don't as_bad here. */
6459 return NULL;
6460}
6461
f3c180ae 6462void
e3bb37b5 6463x86_cons (expressionS *exp, int size)
f3c180ae 6464{
ee86248c
JB
6465 intel_syntax = -intel_syntax;
6466
4fa24527 6467 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM
6468 {
6469 /* Handle @GOTOFF and the like in an expression. */
6470 char *save;
6471 char *gotfree_input_line;
6472 int adjust;
6473
6474 save = input_line_pointer;
3956db08 6475 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM
6476 if (gotfree_input_line)
6477 input_line_pointer = gotfree_input_line;
6478
6479 expression (exp);
6480
6481 if (gotfree_input_line)
6482 {
6483 /* expression () has merrily parsed up to the end of line,
6484 or a comma - in the wrong buffer. Transfer how far
6485 input_line_pointer has moved to the right buffer. */
6486 input_line_pointer = (save
6487 + (input_line_pointer - gotfree_input_line)
6488 + adjust);
6489 free (gotfree_input_line);
3992d3b7
AM
6490 if (exp->X_op == O_constant
6491 || exp->X_op == O_absent
6492 || exp->X_op == O_illegal
6493 || exp->X_op == O_register
6494 || exp->X_op == O_big)
6495 {
6496 char c = *input_line_pointer;
6497 *input_line_pointer = 0;
6498 as_bad (_("missing or invalid expression `%s'"), save);
6499 *input_line_pointer = c;
6500 }
f3c180ae
AM
6501 }
6502 }
6503 else
6504 expression (exp);
ee86248c
JB
6505
6506 intel_syntax = -intel_syntax;
6507
6508 if (intel_syntax)
6509 i386_intel_simplify (exp);
f3c180ae
AM
6510}
6511#endif
6512
d182319b 6513static void signed_cons (int size)
6482c264 6514{
d182319b
JB
6515 if (flag_code == CODE_64BIT)
6516 cons_sign = 1;
6517 cons (size);
6518 cons_sign = -1;
6482c264
NC
6519}
6520
d182319b 6521#ifdef TE_PE
6482c264
NC
6522static void
6523pe_directive_secrel (dummy)
6524 int dummy ATTRIBUTE_UNUSED;
6525{
6526 expressionS exp;
6527
6528 do
6529 {
6530 expression (&exp);
6531 if (exp.X_op == O_symbol)
6532 exp.X_op = O_secrel;
6533
6534 emit_expr (&exp, 4);
6535 }
6536 while (*input_line_pointer++ == ',');
6537
6538 input_line_pointer--;
6539 demand_empty_rest_of_line ();
6540}
6482c264
NC
6541#endif
6542
252b5132 6543static int
70e41ade 6544i386_immediate (char *imm_start)
252b5132
RH
6545{
6546 char *save_input_line_pointer;
f3c180ae 6547 char *gotfree_input_line;
252b5132 6548 segT exp_seg = 0;
47926f60 6549 expressionS *exp;
40fb9820
L
6550 i386_operand_type types;
6551
0dfbf9d7 6552 operand_type_set (&types, ~0);
252b5132
RH
6553
6554 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6555 {
31b2323c
L
6556 as_bad (_("at most %d immediate operands are allowed"),
6557 MAX_IMMEDIATE_OPERANDS);
252b5132
RH
6558 return 0;
6559 }
6560
6561 exp = &im_expressions[i.imm_operands++];
520dc8e8 6562 i.op[this_operand].imms = exp;
252b5132
RH
6563
6564 if (is_space_char (*imm_start))
6565 ++imm_start;
6566
6567 save_input_line_pointer = input_line_pointer;
6568 input_line_pointer = imm_start;
6569
3956db08 6570 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM
6571 if (gotfree_input_line)
6572 input_line_pointer = gotfree_input_line;
252b5132
RH
6573
6574 exp_seg = expression (exp);
6575
83183c0c 6576 SKIP_WHITESPACE ();
252b5132 6577 if (*input_line_pointer)
f3c180ae 6578 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH
6579
6580 input_line_pointer = save_input_line_pointer;
f3c180ae 6581 if (gotfree_input_line)
ee86248c
JB
6582 {
6583 free (gotfree_input_line);
6584
6585 if (exp->X_op == O_constant || exp->X_op == O_register)
6586 exp->X_op = O_illegal;
6587 }
6588
6589 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6590}
252b5132 6591
ee86248c
JB
6592static int
6593i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6594 i386_operand_type types, const char *imm_start)
6595{
6596 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6597 {
3992d3b7 6598 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6599 imm_start);
3992d3b7 6600 return 0;
252b5132 6601 }
3e73aa7c 6602 else if (exp->X_op == O_constant)
252b5132 6603 {
47926f60 6604 /* Size it properly later. */
40fb9820 6605 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6606 /* If BFD64, sign extend val. */
4eed87de
AM
6607 if (!use_rela_relocations
6608 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6609 exp->X_add_number
6610 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6611 }
4c63da97 6612#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6613 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6614 && exp_seg != absolute_section
47926f60 6615 && exp_seg != text_section
24eab124
AM
6616 && exp_seg != data_section
6617 && exp_seg != bss_section
6618 && exp_seg != undefined_section
f86103b7 6619 && !bfd_is_com_section (exp_seg))
252b5132 6620 {
d0b47220 6621 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH
6622 return 0;
6623 }
6624#endif
bb8f5920
L
6625 else if (!intel_syntax && exp->X_op == O_register)
6626 {
6627 as_bad (_("illegal immediate register operand %s"), imm_start);
6628 return 0;
6629 }
252b5132
RH
6630 else
6631 {
6632 /* This is an address. The size of the address will be
24eab124 6633 determined later, depending on destination register,
3e73aa7c 6634 suffix, or the default for the section. */
40fb9820
L
6635 i.types[this_operand].bitfield.imm8 = 1;
6636 i.types[this_operand].bitfield.imm16 = 1;
6637 i.types[this_operand].bitfield.imm32 = 1;
6638 i.types[this_operand].bitfield.imm32s = 1;
6639 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L
6640 i.types[this_operand] = operand_type_and (i.types[this_operand],
6641 types);
252b5132
RH
6642 }
6643
6644 return 1;
6645}
6646
551c1ca1 6647static char *
e3bb37b5 6648i386_scale (char *scale)
252b5132 6649{
551c1ca1
AM
6650 offsetT val;
6651 char *save = input_line_pointer;
252b5132 6652
551c1ca1
AM
6653 input_line_pointer = scale;
6654 val = get_absolute_expression ();
6655
6656 switch (val)
252b5132 6657 {
551c1ca1 6658 case 1:
252b5132
RH
6659 i.log2_scale_factor = 0;
6660 break;
551c1ca1 6661 case 2:
252b5132
RH
6662 i.log2_scale_factor = 1;
6663 break;
551c1ca1 6664 case 4:
252b5132
RH
6665 i.log2_scale_factor = 2;
6666 break;
551c1ca1 6667 case 8:
252b5132
RH
6668 i.log2_scale_factor = 3;
6669 break;
6670 default:
a724f0f4
JB
6671 {
6672 char sep = *input_line_pointer;
6673
6674 *input_line_pointer = '\0';
6675 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6676 scale);
6677 *input_line_pointer = sep;
6678 input_line_pointer = save;
6679 return NULL;
6680 }
252b5132 6681 }
29b0f896 6682 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH
6683 {
6684 as_warn (_("scale factor of %d without an index register"),
24eab124 6685 1 << i.log2_scale_factor);
252b5132 6686 i.log2_scale_factor = 0;
252b5132 6687 }
551c1ca1
AM
6688 scale = input_line_pointer;
6689 input_line_pointer = save;
6690 return scale;
252b5132
RH
6691}
6692
252b5132 6693static int
e3bb37b5 6694i386_displacement (char *disp_start, char *disp_end)
252b5132 6695{
29b0f896 6696 expressionS *exp;
252b5132
RH
6697 segT exp_seg = 0;
6698 char *save_input_line_pointer;
f3c180ae 6699 char *gotfree_input_line;
40fb9820
L
6700 int override;
6701 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6702 int ret;
252b5132 6703
31b2323c
L
6704 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6705 {
6706 as_bad (_("at most %d displacement operands are allowed"),
6707 MAX_MEMORY_OPERANDS);
6708 return 0;
6709 }
6710
0dfbf9d7 6711 operand_type_set (&bigdisp, 0);
40fb9820
L
6712 if ((i.types[this_operand].bitfield.jumpabsolute)
6713 || (!current_templates->start->opcode_modifier.jump
6714 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6715 {
40fb9820 6716 bigdisp.bitfield.disp32 = 1;
e05278af 6717 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L
6718 if (flag_code == CODE_64BIT)
6719 {
6720 if (!override)
6721 {
6722 bigdisp.bitfield.disp32s = 1;
6723 bigdisp.bitfield.disp64 = 1;
6724 }
6725 }
6726 else if ((flag_code == CODE_16BIT) ^ override)
6727 {
6728 bigdisp.bitfield.disp32 = 0;
6729 bigdisp.bitfield.disp16 = 1;
6730 }
e05278af
JB
6731 }
6732 else
6733 {
6734 /* For PC-relative branches, the width of the displacement
6735 is dependent upon data size, not address size. */
e05278af 6736 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L
6737 if (flag_code == CODE_64BIT)
6738 {
6739 if (override || i.suffix == WORD_MNEM_SUFFIX)
6740 bigdisp.bitfield.disp16 = 1;
6741 else
6742 {
6743 bigdisp.bitfield.disp32 = 1;
6744 bigdisp.bitfield.disp32s = 1;
6745 }
6746 }
6747 else
e05278af
JB
6748 {
6749 if (!override)
6750 override = (i.suffix == (flag_code != CODE_16BIT
6751 ? WORD_MNEM_SUFFIX
6752 : LONG_MNEM_SUFFIX));
40fb9820
L
6753 bigdisp.bitfield.disp32 = 1;
6754 if ((flag_code == CODE_16BIT) ^ override)
6755 {
6756 bigdisp.bitfield.disp32 = 0;
6757 bigdisp.bitfield.disp16 = 1;
6758 }
e05278af 6759 }
e05278af 6760 }
c6fb90c8
L
6761 i.types[this_operand] = operand_type_or (i.types[this_operand],
6762 bigdisp);
252b5132
RH
6763
6764 exp = &disp_expressions[i.disp_operands];
520dc8e8 6765 i.op[this_operand].disps = exp;
252b5132
RH
6766 i.disp_operands++;
6767 save_input_line_pointer = input_line_pointer;
6768 input_line_pointer = disp_start;
6769 END_STRING_AND_SAVE (disp_end);
6770
6771#ifndef GCC_ASM_O_HACK
6772#define GCC_ASM_O_HACK 0
6773#endif
6774#if GCC_ASM_O_HACK
6775 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6776 if (i.types[this_operand].bitfield.baseIndex
24eab124 6777 && displacement_string_end[-1] == '+')
252b5132
RH
6778 {
6779 /* This hack is to avoid a warning when using the "o"
24eab124
AM
6780 constraint within gcc asm statements.
6781 For instance:
6782
6783 #define _set_tssldt_desc(n,addr,limit,type) \
6784 __asm__ __volatile__ ( \
6785 "movw %w2,%0\n\t" \
6786 "movw %w1,2+%0\n\t" \
6787 "rorl $16,%1\n\t" \
6788 "movb %b1,4+%0\n\t" \
6789 "movb %4,5+%0\n\t" \
6790 "movb $0,6+%0\n\t" \
6791 "movb %h1,7+%0\n\t" \
6792 "rorl $16,%1" \
6793 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6794
6795 This works great except that the output assembler ends
6796 up looking a bit weird if it turns out that there is
6797 no offset. You end up producing code that looks like:
6798
6799 #APP
6800 movw $235,(%eax)
6801 movw %dx,2+(%eax)
6802 rorl $16,%edx
6803 movb %dl,4+(%eax)
6804 movb $137,5+(%eax)
6805 movb $0,6+(%eax)
6806 movb %dh,7+(%eax)
6807 rorl $16,%edx
6808 #NO_APP
6809
47926f60 6810 So here we provide the missing zero. */
24eab124
AM
6811
6812 *displacement_string_end = '0';
252b5132
RH
6813 }
6814#endif
3956db08 6815 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM
6816 if (gotfree_input_line)
6817 input_line_pointer = gotfree_input_line;
252b5132 6818
24eab124 6819 exp_seg = expression (exp);
252b5132 6820
636c26b0
AM
6821 SKIP_WHITESPACE ();
6822 if (*input_line_pointer)
6823 as_bad (_("junk `%s' after expression"), input_line_pointer);
6824#if GCC_ASM_O_HACK
6825 RESTORE_END_STRING (disp_end + 1);
6826#endif
636c26b0 6827 input_line_pointer = save_input_line_pointer;
636c26b0 6828 if (gotfree_input_line)
ee86248c
JB
6829 {
6830 free (gotfree_input_line);
6831
6832 if (exp->X_op == O_constant || exp->X_op == O_register)
6833 exp->X_op = O_illegal;
6834 }
6835
6836 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6837
6838 RESTORE_END_STRING (disp_end);
6839
6840 return ret;
6841}
6842
6843static int
6844i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6845 i386_operand_type types, const char *disp_start)
6846{
6847 i386_operand_type bigdisp;
6848 int ret = 1;
636c26b0 6849
24eab124
AM
6850 /* We do this to make sure that the section symbol is in
6851 the symbol table. We will ultimately change the relocation
47926f60 6852 to be relative to the beginning of the section. */
1ae12ab7 6853 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB
6854 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6855 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6856 {
636c26b0 6857 if (exp->X_op != O_symbol)
3992d3b7 6858 goto inv_disp;
636c26b0 6859
e5cb08ac 6860 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM
6861 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6862 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM
6863 exp->X_op = O_subtract;
6864 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6865 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6866 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB
6867 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6868 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6869 else
29b0f896 6870 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6871 }
252b5132 6872
3992d3b7
AM
6873 else if (exp->X_op == O_absent
6874 || exp->X_op == O_illegal
ee86248c 6875 || exp->X_op == O_big)
2daf4fd8 6876 {
3992d3b7
AM
6877 inv_disp:
6878 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6879 disp_start);
3992d3b7 6880 ret = 0;
2daf4fd8
AM
6881 }
6882
4c63da97 6883#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM
6884 else if (exp->X_op != O_constant
6885 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6886 && exp_seg != absolute_section
6887 && exp_seg != text_section
6888 && exp_seg != data_section
6889 && exp_seg != bss_section
6890 && exp_seg != undefined_section
6891 && !bfd_is_com_section (exp_seg))
24eab124 6892 {
d0b47220 6893 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6894 ret = 0;
24eab124 6895 }
252b5132 6896#endif
3956db08 6897
40fb9820
L
6898 /* Check if this is a displacement only operand. */
6899 bigdisp = i.types[this_operand];
6900 bigdisp.bitfield.disp8 = 0;
6901 bigdisp.bitfield.disp16 = 0;
6902 bigdisp.bitfield.disp32 = 0;
6903 bigdisp.bitfield.disp32s = 0;
6904 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6905 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L
6906 i.types[this_operand] = operand_type_and (i.types[this_operand],
6907 types);
3956db08 6908
3992d3b7 6909 return ret;
252b5132
RH
6910}
6911
eecb386c 6912/* Make sure the memory operand we've been dealt is valid.
47926f60
KH
6913 Return 1 on success, 0 on a failure. */
6914
252b5132 6915static int
e3bb37b5 6916i386_index_check (const char *operand_string)
252b5132 6917{
3e73aa7c 6918 int ok;
fc0763e6 6919 const char *kind = "base/index";
24eab124 6920#if INFER_ADDR_PREFIX
eecb386c
AM
6921 int fudged = 0;
6922
24eab124
AM
6923 tryprefix:
6924#endif
3e73aa7c 6925 ok = 1;
fc0763e6
JB
6926 if (current_templates->start->opcode_modifier.isstring
6927 && !current_templates->start->opcode_modifier.immext
6928 && (current_templates->end[-1].opcode_modifier.isstring
6929 || i.mem_operands))
6930 {
6931 /* Memory operands of string insns are special in that they only allow
6932 a single register (rDI, rSI, or rBX) as their memory address. */
6933 unsigned int expected;
6934
6935 kind = "string address";
6936
6937 if (current_templates->start->opcode_modifier.w)
6938 {
6939 i386_operand_type type = current_templates->end[-1].operand_types[0];
6940
6941 if (!type.bitfield.baseindex
6942 || ((!i.mem_operands != !intel_syntax)
6943 && current_templates->end[-1].operand_types[1]
6944 .bitfield.baseindex))
6945 type = current_templates->end[-1].operand_types[1];
6946 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6947 }
6948 else
6949 expected = 3 /* rBX */;
6950
6951 if (!i.base_reg || i.index_reg
6952 || operand_type_check (i.types[this_operand], disp))
6953 ok = -1;
6954 else if (!(flag_code == CODE_64BIT
6955 ? i.prefix[ADDR_PREFIX]
6956 ? i.base_reg->reg_type.bitfield.reg32
6957 : i.base_reg->reg_type.bitfield.reg64
6958 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6959 ? i.base_reg->reg_type.bitfield.reg32
6960 : i.base_reg->reg_type.bitfield.reg16))
6961 ok = 0;
6962 else if (i.base_reg->reg_num != expected)
6963 ok = -1;
6964
6965 if (ok < 0)
6966 {
6967 unsigned int j;
6968
6969 for (j = 0; j < i386_regtab_size; ++j)
6970 if ((flag_code == CODE_64BIT
6971 ? i.prefix[ADDR_PREFIX]
6972 ? i386_regtab[j].reg_type.bitfield.reg32
6973 : i386_regtab[j].reg_type.bitfield.reg64
6974 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6975 ? i386_regtab[j].reg_type.bitfield.reg32
6976 : i386_regtab[j].reg_type.bitfield.reg16)
6977 && i386_regtab[j].reg_num == expected)
6978 break;
6979 assert (j < i386_regtab_size);
6980 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6981 operand_string,
6982 intel_syntax ? '[' : '(',
6983 register_prefix,
6984 i386_regtab[j].reg_name,
6985 intel_syntax ? ']' : ')');
6986 ok = 1;
6987 }
6988 }
6989 else if (flag_code == CODE_64BIT)
64e74474 6990 {
64e74474 6991 if ((i.base_reg
40fb9820
L
6992 && ((i.prefix[ADDR_PREFIX] == 0
6993 && !i.base_reg->reg_type.bitfield.reg64)
6994 || (i.prefix[ADDR_PREFIX]
6995 && !i.base_reg->reg_type.bitfield.reg32))
6996 && (i.index_reg
9a04903e
JB
6997 || i.base_reg->reg_num !=
6998 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6999 || (i.index_reg
40fb9820
L
7000 && (!i.index_reg->reg_type.bitfield.baseindex
7001 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L
7002 && i.index_reg->reg_num != RegRiz
7003 && !i.index_reg->reg_type.bitfield.reg64
7004 )
40fb9820 7005 || (i.prefix[ADDR_PREFIX]
db51cc60 7006 && i.index_reg->reg_num != RegEiz
40fb9820 7007 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7008 ok = 0;
3e73aa7c
JH
7009 }
7010 else
7011 {
7012 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7013 {
7014 /* 16bit checks. */
7015 if ((i.base_reg
40fb9820
L
7016 && (!i.base_reg->reg_type.bitfield.reg16
7017 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7018 || (i.index_reg
40fb9820
L
7019 && (!i.index_reg->reg_type.bitfield.reg16
7020 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM
7021 || !(i.base_reg
7022 && i.base_reg->reg_num < 6
7023 && i.index_reg->reg_num >= 6
7024 && i.log2_scale_factor == 0))))
3e73aa7c
JH
7025 ok = 0;
7026 }
7027 else
e5cb08ac 7028 {
3e73aa7c
JH
7029 /* 32bit checks. */
7030 if ((i.base_reg
40fb9820 7031 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7032 || (i.index_reg
db51cc60
L
7033 && ((!i.index_reg->reg_type.bitfield.reg32
7034 && i.index_reg->reg_num != RegEiz)
40fb9820 7035 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7036 ok = 0;
3e73aa7c
JH
7037 }
7038 }
7039 if (!ok)
24eab124
AM
7040 {
7041#if INFER_ADDR_PREFIX
fc0763e6 7042 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM
7043 {
7044 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7045 i.prefixes += 1;
b23bac36
AM
7046 /* Change the size of any displacement too. At most one of
7047 Disp16 or Disp32 is set.
7048 FIXME. There doesn't seem to be any real need for separate
7049 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7050 Removing them would probably clean up the code quite a lot. */
4eed87de 7051 if (flag_code != CODE_64BIT
40fb9820
L
7052 && (i.types[this_operand].bitfield.disp16
7053 || i.types[this_operand].bitfield.disp32))
7054 i.types[this_operand]
c6fb90c8 7055 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7056 fudged = 1;
24eab124
AM
7057 goto tryprefix;
7058 }
eecb386c 7059 if (fudged)
fc0763e6
JB
7060 as_bad (_("`%s' is not a valid %s expression"),
7061 operand_string,
7062 kind);
eecb386c 7063 else
c388dee8 7064#endif
fc0763e6 7065 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7066 operand_string,
fc0763e6
JB
7067 flag_code_names[i.prefix[ADDR_PREFIX]
7068 ? flag_code == CODE_32BIT
7069 ? CODE_16BIT
7070 : CODE_32BIT
7071 : flag_code],
7072 kind);
24eab124 7073 }
20f0a1fc 7074 return ok;
24eab124 7075}
252b5132 7076
fc0763e6 7077/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7078 on error. */
252b5132 7079
252b5132 7080static int
a7619375 7081i386_att_operand (char *operand_string)
252b5132 7082{
af6bdddf
AM
7083 const reg_entry *r;
7084 char *end_op;
24eab124 7085 char *op_string = operand_string;
252b5132 7086
24eab124 7087 if (is_space_char (*op_string))
252b5132
RH
7088 ++op_string;
7089
24eab124 7090 /* We check for an absolute prefix (differentiating,
47926f60 7091 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM
7092 if (*op_string == ABSOLUTE_PREFIX)
7093 {
7094 ++op_string;
7095 if (is_space_char (*op_string))
7096 ++op_string;
40fb9820 7097 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7098 }
252b5132 7099
47926f60 7100 /* Check if operand is a register. */
4d1bb795 7101 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7102 {
40fb9820
L
7103 i386_operand_type temp;
7104
24eab124
AM
7105 /* Check for a segment override by searching for ':' after a
7106 segment register. */
7107 op_string = end_op;
7108 if (is_space_char (*op_string))
7109 ++op_string;
40fb9820
L
7110 if (*op_string == ':'
7111 && (r->reg_type.bitfield.sreg2
7112 || r->reg_type.bitfield.sreg3))
24eab124
AM
7113 {
7114 switch (r->reg_num)
7115 {
7116 case 0:
7117 i.seg[i.mem_operands] = &es;
7118 break;
7119 case 1:
7120 i.seg[i.mem_operands] = &cs;
7121 break;
7122 case 2:
7123 i.seg[i.mem_operands] = &ss;
7124 break;
7125 case 3:
7126 i.seg[i.mem_operands] = &ds;
7127 break;
7128 case 4:
7129 i.seg[i.mem_operands] = &fs;
7130 break;
7131 case 5:
7132 i.seg[i.mem_operands] = &gs;
7133 break;
7134 }
252b5132 7135
24eab124 7136 /* Skip the ':' and whitespace. */
252b5132
RH
7137 ++op_string;
7138 if (is_space_char (*op_string))
24eab124 7139 ++op_string;
252b5132 7140
24eab124
AM
7141 if (!is_digit_char (*op_string)
7142 && !is_identifier_char (*op_string)
7143 && *op_string != '('
7144 && *op_string != ABSOLUTE_PREFIX)
7145 {
7146 as_bad (_("bad memory operand `%s'"), op_string);
7147 return 0;
7148 }
47926f60 7149 /* Handle case of %es:*foo. */
24eab124
AM
7150 if (*op_string == ABSOLUTE_PREFIX)
7151 {
7152 ++op_string;
7153 if (is_space_char (*op_string))
7154 ++op_string;
40fb9820 7155 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM
7156 }
7157 goto do_memory_reference;
7158 }
7159 if (*op_string)
7160 {
d0b47220 7161 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM
7162 return 0;
7163 }
40fb9820
L
7164 temp = r->reg_type;
7165 temp.bitfield.baseindex = 0;
c6fb90c8
L
7166 i.types[this_operand] = operand_type_or (i.types[this_operand],
7167 temp);
7d5e4556 7168 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7169 i.op[this_operand].regs = r;
24eab124
AM
7170 i.reg_operands++;
7171 }
af6bdddf
AM
7172 else if (*op_string == REGISTER_PREFIX)
7173 {
7174 as_bad (_("bad register name `%s'"), op_string);
7175 return 0;
7176 }
24eab124 7177 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7178 {
24eab124 7179 ++op_string;
40fb9820 7180 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7181 {
d0b47220 7182 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM
7183 return 0;
7184 }
7185 if (!i386_immediate (op_string))
7186 return 0;
7187 }
7188 else if (is_digit_char (*op_string)
7189 || is_identifier_char (*op_string)
e5cb08ac 7190 || *op_string == '(')
24eab124 7191 {
47926f60 7192 /* This is a memory reference of some sort. */
af6bdddf 7193 char *base_string;
252b5132 7194
47926f60 7195 /* Start and end of displacement string expression (if found). */
eecb386c
AM
7196 char *displacement_string_start;
7197 char *displacement_string_end;
252b5132 7198
24eab124 7199 do_memory_reference:
24eab124 7200 if ((i.mem_operands == 1
40fb9820 7201 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM
7202 || i.mem_operands == 2)
7203 {
7204 as_bad (_("too many memory references for `%s'"),
7205 current_templates->start->name);
7206 return 0;
7207 }
252b5132 7208
24eab124
AM
7209 /* Check for base index form. We detect the base index form by
7210 looking for an ')' at the end of the operand, searching
7211 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7212 after the '('. */
af6bdddf 7213 base_string = op_string + strlen (op_string);
c3332e24 7214
af6bdddf
AM
7215 --base_string;
7216 if (is_space_char (*base_string))
7217 --base_string;
252b5132 7218
47926f60 7219 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM
7220 displacement_string_start = op_string;
7221 displacement_string_end = base_string + 1;
252b5132 7222
24eab124
AM
7223 if (*base_string == ')')
7224 {
af6bdddf 7225 char *temp_string;
24eab124
AM
7226 unsigned int parens_balanced = 1;
7227 /* We've already checked that the number of left & right ()'s are
47926f60 7228 equal, so this loop will not be infinite. */
24eab124
AM
7229 do
7230 {
7231 base_string--;
7232 if (*base_string == ')')
7233 parens_balanced++;
7234 if (*base_string == '(')
7235 parens_balanced--;
7236 }
7237 while (parens_balanced);
c3332e24 7238
af6bdddf 7239 temp_string = base_string;
c3332e24 7240
24eab124 7241 /* Skip past '(' and whitespace. */
252b5132
RH
7242 ++base_string;
7243 if (is_space_char (*base_string))
24eab124 7244 ++base_string;
252b5132 7245
af6bdddf 7246 if (*base_string == ','
4eed87de
AM
7247 || ((i.base_reg = parse_register (base_string, &end_op))
7248 != NULL))
252b5132 7249 {
af6bdddf 7250 displacement_string_end = temp_string;
252b5132 7251
40fb9820 7252 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7253
af6bdddf 7254 if (i.base_reg)
24eab124 7255 {
24eab124
AM
7256 base_string = end_op;
7257 if (is_space_char (*base_string))
7258 ++base_string;
af6bdddf
AM
7259 }
7260
7261 /* There may be an index reg or scale factor here. */
7262 if (*base_string == ',')
7263 {
7264 ++base_string;
7265 if (is_space_char (*base_string))
7266 ++base_string;
7267
4eed87de
AM
7268 if ((i.index_reg = parse_register (base_string, &end_op))
7269 != NULL)
24eab124 7270 {
af6bdddf 7271 base_string = end_op;
24eab124
AM
7272 if (is_space_char (*base_string))
7273 ++base_string;
af6bdddf
AM
7274 if (*base_string == ',')
7275 {
7276 ++base_string;
7277 if (is_space_char (*base_string))
7278 ++base_string;
7279 }
e5cb08ac 7280 else if (*base_string != ')')
af6bdddf 7281 {
4eed87de
AM
7282 as_bad (_("expecting `,' or `)' "
7283 "after index register in `%s'"),
af6bdddf
AM
7284 operand_string);
7285 return 0;
7286 }
24eab124 7287 }
af6bdddf 7288 else if (*base_string == REGISTER_PREFIX)
24eab124 7289 {
af6bdddf 7290 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM
7291 return 0;
7292 }
252b5132 7293
47926f60 7294 /* Check for scale factor. */
551c1ca1 7295 if (*base_string != ')')
af6bdddf 7296 {
551c1ca1
AM
7297 char *end_scale = i386_scale (base_string);
7298
7299 if (!end_scale)
af6bdddf 7300 return 0;
24eab124 7301
551c1ca1 7302 base_string = end_scale;
af6bdddf
AM
7303 if (is_space_char (*base_string))
7304 ++base_string;
7305 if (*base_string != ')')
7306 {
4eed87de
AM
7307 as_bad (_("expecting `)' "
7308 "after scale factor in `%s'"),
af6bdddf
AM
7309 operand_string);
7310 return 0;
7311 }
7312 }
7313 else if (!i.index_reg)
24eab124 7314 {
4eed87de
AM
7315 as_bad (_("expecting index register or scale factor "
7316 "after `,'; got '%c'"),
af6bdddf 7317 *base_string);
24eab124
AM
7318 return 0;
7319 }
7320 }
af6bdddf 7321 else if (*base_string != ')')
24eab124 7322 {
4eed87de
AM
7323 as_bad (_("expecting `,' or `)' "
7324 "after base register in `%s'"),
af6bdddf 7325 operand_string);
24eab124
AM
7326 return 0;
7327 }
c3332e24 7328 }
af6bdddf 7329 else if (*base_string == REGISTER_PREFIX)
c3332e24 7330 {
af6bdddf 7331 as_bad (_("bad register name `%s'"), base_string);
24eab124 7332 return 0;
c3332e24 7333 }
24eab124
AM
7334 }
7335
7336 /* If there's an expression beginning the operand, parse it,
7337 assuming displacement_string_start and
7338 displacement_string_end are meaningful. */
7339 if (displacement_string_start != displacement_string_end)
7340 {
7341 if (!i386_displacement (displacement_string_start,
7342 displacement_string_end))
7343 return 0;
7344 }
7345
7346 /* Special case for (%dx) while doing input/output op. */
7347 if (i.base_reg
0dfbf9d7
L
7348 && operand_type_equal (&i.base_reg->reg_type,
7349 &reg16_inoutportreg)
24eab124
AM
7350 && i.index_reg == 0
7351 && i.log2_scale_factor == 0
7352 && i.seg[i.mem_operands] == 0
40fb9820 7353 && !operand_type_check (i.types[this_operand], disp))
24eab124 7354 {
65da13b5 7355 i.types[this_operand] = inoutportreg;
24eab124
AM
7356 return 1;
7357 }
7358
eecb386c
AM
7359 if (i386_index_check (operand_string) == 0)
7360 return 0;
5c07affc 7361 i.types[this_operand].bitfield.mem = 1;
24eab124
AM
7362 i.mem_operands++;
7363 }
7364 else
ce8a8b2f
AM
7365 {
7366 /* It's not a memory operand; argh! */
24eab124
AM
7367 as_bad (_("invalid char %s beginning operand %d `%s'"),
7368 output_invalid (*op_string),
7369 this_operand + 1,
7370 op_string);
7371 return 0;
7372 }
47926f60 7373 return 1; /* Normal return. */
252b5132
RH
7374}
7375\f
ee7fcc42
AM
7376/* md_estimate_size_before_relax()
7377
7378 Called just before relax() for rs_machine_dependent frags. The x86
7379 assembler uses these frags to handle variable size jump
7380 instructions.
7381
7382 Any symbol that is now undefined will not become defined.
7383 Return the correct fr_subtype in the frag.
7384 Return the initial "guess for variable size of frag" to caller.
7385 The guess is actually the growth beyond the fixed part. Whatever
7386 we do to grow the fixed or variable part contributes to our
7387 returned value. */
7388
252b5132
RH
7389int
7390md_estimate_size_before_relax (fragP, segment)
29b0f896
AM
7391 fragS *fragP;
7392 segT segment;
252b5132 7393{
252b5132 7394 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM
7395 check for un-relaxable symbols. On an ELF system, we can't relax
7396 an externally visible symbol, because it may be overridden by a
7397 shared library. */
7398 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7399#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7400 || (IS_ELF
31312f95
AM
7401 && (S_IS_EXTERNAL (fragP->fr_symbol)
7402 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM
7403#endif
7404 )
252b5132 7405 {
b98ef147
AM
7406 /* Symbol is undefined in this segment, or we need to keep a
7407 reloc so that weak symbols can be overridden. */
7408 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7409 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM
7410 unsigned char *opcode;
7411 int old_fr_fix;
f6af82bd 7412
ee7fcc42
AM
7413 if (fragP->fr_var != NO_RELOC)
7414 reloc_type = fragP->fr_var;
b98ef147 7415 else if (size == 2)
f6af82bd
AM
7416 reloc_type = BFD_RELOC_16_PCREL;
7417 else
7418 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7419
ee7fcc42
AM
7420 old_fr_fix = fragP->fr_fix;
7421 opcode = (unsigned char *) fragP->fr_opcode;
7422
fddf5b5b 7423 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7424 {
fddf5b5b
AM
7425 case UNCOND_JUMP:
7426 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7427 opcode[0] = 0xe9;
252b5132 7428 fragP->fr_fix += size;
062cd5e7
AS
7429 fix_new (fragP, old_fr_fix, size,
7430 fragP->fr_symbol,
7431 fragP->fr_offset, 1,
7432 reloc_type);
252b5132
RH
7433 break;
7434
fddf5b5b 7435 case COND_JUMP86:
412167cb
AM
7436 if (size == 2
7437 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM
7438 {
7439 /* Negate the condition, and branch past an
7440 unconditional jump. */
7441 opcode[0] ^= 1;
7442 opcode[1] = 3;
7443 /* Insert an unconditional jump. */
7444 opcode[2] = 0xe9;
7445 /* We added two extra opcode bytes, and have a two byte
7446 offset. */
7447 fragP->fr_fix += 2 + 2;
062cd5e7
AS
7448 fix_new (fragP, old_fr_fix + 2, 2,
7449 fragP->fr_symbol,
7450 fragP->fr_offset, 1,
7451 reloc_type);
fddf5b5b
AM
7452 break;
7453 }
7454 /* Fall through. */
7455
7456 case COND_JUMP:
412167cb
AM
7457 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7458 {
3e02c1cc
AM
7459 fixS *fixP;
7460
412167cb 7461 fragP->fr_fix += 1;
3e02c1cc
AM
7462 fixP = fix_new (fragP, old_fr_fix, 1,
7463 fragP->fr_symbol,
7464 fragP->fr_offset, 1,
7465 BFD_RELOC_8_PCREL);
7466 fixP->fx_signed = 1;
412167cb
AM
7467 break;
7468 }
93c2a809 7469
24eab124 7470 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7471 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7472 opcode[1] = opcode[0] + 0x10;
f6af82bd 7473 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH
7474 /* We've added an opcode byte. */
7475 fragP->fr_fix += 1 + size;
062cd5e7
AS
7476 fix_new (fragP, old_fr_fix + 1, size,
7477 fragP->fr_symbol,
7478 fragP->fr_offset, 1,
7479 reloc_type);
252b5132 7480 break;
fddf5b5b
AM
7481
7482 default:
7483 BAD_CASE (fragP->fr_subtype);
7484 break;
252b5132
RH
7485 }
7486 frag_wane (fragP);
ee7fcc42 7487 return fragP->fr_fix - old_fr_fix;
252b5132 7488 }
93c2a809 7489
93c2a809
AM
7490 /* Guess size depending on current relax state. Initially the relax
7491 state will correspond to a short jump and we return 1, because
7492 the variable part of the frag (the branch offset) is one byte
7493 long. However, we can relax a section more than once and in that
7494 case we must either set fr_subtype back to the unrelaxed state,
7495 or return the value for the appropriate branch. */
7496 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM
7497}
7498
47926f60
KH
7499/* Called after relax() is finished.
7500
7501 In: Address of frag.
7502 fr_type == rs_machine_dependent.
7503 fr_subtype is what the address relaxed to.
7504
7505 Out: Any fixSs and constants are set up.
7506 Caller will turn frag into a ".space 0". */
7507
252b5132
RH
7508void
7509md_convert_frag (abfd, sec, fragP)
ab9da554
ILT
7510 bfd *abfd ATTRIBUTE_UNUSED;
7511 segT sec ATTRIBUTE_UNUSED;
29b0f896 7512 fragS *fragP;
252b5132 7513{
29b0f896 7514 unsigned char *opcode;
252b5132 7515 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM
7516 offsetT target_address;
7517 offsetT opcode_address;
252b5132 7518 unsigned int extension = 0;
847f7ad4 7519 offsetT displacement_from_opcode_start;
252b5132
RH
7520
7521 opcode = (unsigned char *) fragP->fr_opcode;
7522
47926f60 7523 /* Address we want to reach in file space. */
252b5132 7524 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7525
47926f60 7526 /* Address opcode resides at in file space. */
252b5132
RH
7527 opcode_address = fragP->fr_address + fragP->fr_fix;
7528
47926f60 7529 /* Displacement from opcode start to fill into instruction. */
252b5132
RH
7530 displacement_from_opcode_start = target_address - opcode_address;
7531
fddf5b5b 7532 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7533 {
47926f60
KH
7534 /* Don't have to change opcode. */
7535 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7536 where_to_put_displacement = &opcode[1];
fddf5b5b
AM
7537 }
7538 else
7539 {
7540 if (no_cond_jump_promotion
7541 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM
7542 as_warn_where (fragP->fr_file, fragP->fr_line,
7543 _("long jump required"));
252b5132 7544
fddf5b5b
AM
7545 switch (fragP->fr_subtype)
7546 {
7547 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7548 extension = 4; /* 1 opcode + 4 displacement */
7549 opcode[0] = 0xe9;
7550 where_to_put_displacement = &opcode[1];
7551 break;
252b5132 7552
fddf5b5b
AM
7553 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7554 extension = 2; /* 1 opcode + 2 displacement */
7555 opcode[0] = 0xe9;
7556 where_to_put_displacement = &opcode[1];
7557 break;
252b5132 7558
fddf5b5b
AM
7559 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7560 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7561 extension = 5; /* 2 opcode + 4 displacement */
7562 opcode[1] = opcode[0] + 0x10;
7563 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7564 where_to_put_displacement = &opcode[2];
7565 break;
252b5132 7566
fddf5b5b
AM
7567 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7568 extension = 3; /* 2 opcode + 2 displacement */
7569 opcode[1] = opcode[0] + 0x10;
7570 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7571 where_to_put_displacement = &opcode[2];
7572 break;
252b5132 7573
fddf5b5b
AM
7574 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7575 extension = 4;
7576 opcode[0] ^= 1;
7577 opcode[1] = 3;
7578 opcode[2] = 0xe9;
7579 where_to_put_displacement = &opcode[3];
7580 break;
7581
7582 default:
7583 BAD_CASE (fragP->fr_subtype);
7584 break;
7585 }
252b5132 7586 }
fddf5b5b 7587
7b81dfbb
AJ
7588 /* If size if less then four we are sure that the operand fits,
7589 but if it's 4, then it could be that the displacement is larger
7590 then -/+ 2GB. */
7591 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7592 && object_64bit
7593 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM
7594 + ((addressT) 1 << 31))
7595 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ
7596 {
7597 as_bad_where (fragP->fr_file, fragP->fr_line,
7598 _("jump target out of range"));
7599 /* Make us emit 0. */
7600 displacement_from_opcode_start = extension;
7601 }
47926f60 7602 /* Now put displacement after opcode. */
252b5132
RH
7603 md_number_to_chars ((char *) where_to_put_displacement,
7604 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7605 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH
7606 fragP->fr_fix += extension;
7607}
7608\f
252b5132
RH
7609/* Apply a fixup (fixS) to segment data, once it has been determined
7610 by our caller that we have all the info we need to fix it up.
7611
7612 On the 386, immediates, displacements, and data pointers are all in
7613 the same (little-endian) format, so we don't need to care about which
7614 we are handling. */
7615
94f592af 7616void
55cf6793 7617md_apply_fix (fixP, valP, seg)
47926f60
KH
7618 /* The fix we're to put in. */
7619 fixS *fixP;
47926f60 7620 /* Pointer to the value of the bits. */
c6682705 7621 valueT *valP;
47926f60
KH
7622 /* Segment fix is from. */
7623 segT seg ATTRIBUTE_UNUSED;
252b5132 7624{
94f592af 7625 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7626 valueT value = *valP;
252b5132 7627
f86103b7 7628#if !defined (TE_Mach)
93382f6d
AM
7629 if (fixP->fx_pcrel)
7630 {
7631 switch (fixP->fx_r_type)
7632 {
5865bb77
ILT
7633 default:
7634 break;
7635
d6ab8113
JB
7636 case BFD_RELOC_64:
7637 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7638 break;
93382f6d 7639 case BFD_RELOC_32:
ae8887b5 7640 case BFD_RELOC_X86_64_32S:
93382f6d
AM
7641 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7642 break;
7643 case BFD_RELOC_16:
7644 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7645 break;
7646 case BFD_RELOC_8:
7647 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7648 break;
7649 }
7650 }
252b5132 7651
a161fe53 7652 if (fixP->fx_addsy != NULL
31312f95 7653 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7654 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM
7655 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7656 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7657 && !use_rela_relocations)
252b5132 7658 {
31312f95
AM
7659 /* This is a hack. There should be a better way to handle this.
7660 This covers for the fact that bfd_install_relocation will
7661 subtract the current location (for partial_inplace, PC relative
7662 relocations); see more below. */
252b5132 7663#ifndef OBJ_AOUT
718ddfc0 7664 if (IS_ELF
252b5132
RH
7665#ifdef TE_PE
7666 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7667#endif
7668 )
7669 value += fixP->fx_where + fixP->fx_frag->fr_address;
7670#endif
7671#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7672 if (IS_ELF)
252b5132 7673 {
6539b54b 7674 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7675
6539b54b 7676 if ((sym_seg == seg
2f66722d 7677 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7678 && sym_seg != absolute_section))
ae6063d4 7679 && !generic_force_reloc (fixP))
2f66722d
AM
7680 {
7681 /* Yes, we add the values in twice. This is because
6539b54b
AM
7682 bfd_install_relocation subtracts them out again. I think
7683 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM
7684 it. FIXME. */
7685 value += fixP->fx_where + fixP->fx_frag->fr_address;
7686 }
252b5132
RH
7687 }
7688#endif
7689#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC
7690 /* For some reason, the PE format does not store a
7691 section address offset for a PC relative symbol. */
7692 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7693 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH
7694 value += md_pcrel_from (fixP);
7695#endif
7696 }
7697
7698 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7699 and we must not disappoint it. */
252b5132 7700#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7701 if (IS_ELF && fixP->fx_addsy)
47926f60
KH
7702 switch (fixP->fx_r_type)
7703 {
7704 case BFD_RELOC_386_PLT32:
3e73aa7c 7705 case BFD_RELOC_X86_64_PLT32:
47926f60
KH
7706 /* Make the jump instruction point to the address of the operand. At
7707 runtime we merely add the offset to the actual PLT entry. */
7708 value = -4;
7709 break;
31312f95 7710
13ae64f3
JJ
7711 case BFD_RELOC_386_TLS_GD:
7712 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7713 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ
7714 case BFD_RELOC_386_TLS_IE:
7715 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7716 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ
7717 case BFD_RELOC_X86_64_TLSGD:
7718 case BFD_RELOC_X86_64_TLSLD:
7719 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7720 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ
7721 value = 0; /* Fully resolved at runtime. No addend. */
7722 /* Fallthrough */
7723 case BFD_RELOC_386_TLS_LE:
7724 case BFD_RELOC_386_TLS_LDO_32:
7725 case BFD_RELOC_386_TLS_LE_32:
7726 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7727 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7728 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7729 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ
7730 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7731 break;
7732
67a4f2b7
AO
7733 case BFD_RELOC_386_TLS_DESC_CALL:
7734 case BFD_RELOC_X86_64_TLSDESC_CALL:
7735 value = 0; /* Fully resolved at runtime. No addend. */
7736 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7737 fixP->fx_done = 0;
7738 return;
7739
00f7efb6
JJ
7740 case BFD_RELOC_386_GOT32:
7741 case BFD_RELOC_X86_64_GOT32:
47926f60
KH
7742 value = 0; /* Fully resolved at runtime. No addend. */
7743 break;
47926f60
KH
7744
7745 case BFD_RELOC_VTABLE_INHERIT:
7746 case BFD_RELOC_VTABLE_ENTRY:
7747 fixP->fx_done = 0;
94f592af 7748 return;
47926f60
KH
7749
7750 default:
7751 break;
7752 }
7753#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7754 *valP = value;
f86103b7 7755#endif /* !defined (TE_Mach) */
3e73aa7c 7756
3e73aa7c 7757 /* Are we finished with this relocation now? */
c6682705 7758 if (fixP->fx_addsy == NULL)
3e73aa7c
JH
7759 fixP->fx_done = 1;
7760 else if (use_rela_relocations)
7761 {
7762 fixP->fx_no_overflow = 1;
062cd5e7
AS
7763 /* Remember value for tc_gen_reloc. */
7764 fixP->fx_addnumber = value;
3e73aa7c
JH
7765 value = 0;
7766 }
f86103b7 7767
94f592af 7768 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7769}
252b5132 7770\f
252b5132 7771char *
499ac353 7772md_atof (int type, char *litP, int *sizeP)
252b5132 7773{
499ac353
NC
7774 /* This outputs the LITTLENUMs in REVERSE order;
7775 in accord with the bigendian 386. */
7776 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH
7777}
7778\f
2d545b82 7779static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7780
252b5132 7781static char *
e3bb37b5 7782output_invalid (int c)
252b5132 7783{
3882b010 7784 if (ISPRINT (c))
f9f21a03
L
7785 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7786 "'%c'", c);
252b5132 7787 else
f9f21a03 7788 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7789 "(0x%x)", (unsigned char) c);
252b5132
RH
7790 return output_invalid_buf;
7791}
7792
af6bdddf 7793/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH
7794
7795static const reg_entry *
4d1bb795 7796parse_real_register (char *reg_string, char **end_op)
252b5132 7797{
af6bdddf
AM
7798 char *s = reg_string;
7799 char *p;
252b5132
RH
7800 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7801 const reg_entry *r;
7802
7803 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7804 if (*s == REGISTER_PREFIX)
7805 ++s;
7806
7807 if (is_space_char (*s))
7808 ++s;
7809
7810 p = reg_name_given;
af6bdddf 7811 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH
7812 {
7813 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM
7814 return (const reg_entry *) NULL;
7815 s++;
252b5132
RH
7816 }
7817
6588847e
DN
7818 /* For naked regs, make sure that we are not dealing with an identifier.
7819 This prevents confusing an identifier like `eax_var' with register
7820 `eax'. */
7821 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7822 return (const reg_entry *) NULL;
7823
af6bdddf 7824 *end_op = s;
252b5132
RH
7825
7826 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7827
5f47d35b 7828 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7829 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7830 {
5f47d35b
AM
7831 if (is_space_char (*s))
7832 ++s;
7833 if (*s == '(')
7834 {
af6bdddf 7835 ++s;
5f47d35b
AM
7836 if (is_space_char (*s))
7837 ++s;
7838 if (*s >= '0' && *s <= '7')
7839 {
db557034 7840 int fpr = *s - '0';
af6bdddf 7841 ++s;
5f47d35b
AM
7842 if (is_space_char (*s))
7843 ++s;
7844 if (*s == ')')
7845 {
7846 *end_op = s + 1;
db557034
AM
7847 r = hash_find (reg_hash, "st(0)");
7848 know (r);
7849 return r + fpr;
5f47d35b 7850 }
5f47d35b 7851 }
47926f60 7852 /* We have "%st(" then garbage. */
5f47d35b
AM
7853 return (const reg_entry *) NULL;
7854 }
7855 }
7856
a60de03c
JB
7857 if (r == NULL || allow_pseudo_reg)
7858 return r;
7859
0dfbf9d7 7860 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB
7861 return (const reg_entry *) NULL;
7862
192dc9c6
JB
7863 if ((r->reg_type.bitfield.reg32
7864 || r->reg_type.bitfield.sreg3
7865 || r->reg_type.bitfield.control
7866 || r->reg_type.bitfield.debug
7867 || r->reg_type.bitfield.test)
7868 && !cpu_arch_flags.bitfield.cpui386)
7869 return (const reg_entry *) NULL;
7870
7871 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7872 return (const reg_entry *) NULL;
7873
7874 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7875 return (const reg_entry *) NULL;
7876
40f12533
L
7877 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7878 return (const reg_entry *) NULL;
7879
db51cc60 7880 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7881 if (!allow_index_reg
db51cc60
L
7882 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7883 return (const reg_entry *) NULL;
7884
a60de03c
JB
7885 if (((r->reg_flags & (RegRex64 | RegRex))
7886 || r->reg_type.bitfield.reg64)
40fb9820 7887 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7888 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7889 && flag_code != CODE_64BIT)
20f0a1fc 7890 return (const reg_entry *) NULL;
1ae00879 7891
b7240065
JB
7892 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7893 return (const reg_entry *) NULL;
7894
252b5132
RH
7895 return r;
7896}
4d1bb795
JB
7897
7898/* REG_STRING starts *before* REGISTER_PREFIX. */
7899
7900static const reg_entry *
7901parse_register (char *reg_string, char **end_op)
7902{
7903 const reg_entry *r;
7904
7905 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7906 r = parse_real_register (reg_string, end_op);
7907 else
7908 r = NULL;
7909 if (!r)
7910 {
7911 char *save = input_line_pointer;
7912 char c;
7913 symbolS *symbolP;
7914
7915 input_line_pointer = reg_string;
7916 c = get_symbol_end ();
7917 symbolP = symbol_find (reg_string);
7918 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7919 {
7920 const expressionS *e = symbol_get_value_expression (symbolP);
7921
7922 know (e->X_op == O_register);
4eed87de 7923 know (e->X_add_number >= 0
c3fe08fa 7924 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB
7925 r = i386_regtab + e->X_add_number;
7926 *end_op = input_line_pointer;
7927 }
7928 *input_line_pointer = c;
7929 input_line_pointer = save;
7930 }
7931 return r;
7932}
7933
7934int
7935i386_parse_name (char *name, expressionS *e, char *nextcharP)
7936{
7937 const reg_entry *r;
7938 char *end = input_line_pointer;
7939
7940 *end = *nextcharP;
7941 r = parse_register (name, &input_line_pointer);
7942 if (r && end <= input_line_pointer)
7943 {
7944 *nextcharP = *input_line_pointer;
7945 *input_line_pointer = 0;
7946 e->X_op = O_register;
7947 e->X_add_number = r - i386_regtab;
7948 return 1;
7949 }
7950 input_line_pointer = end;
7951 *end = 0;
ee86248c 7952 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB
7953}
7954
7955void
7956md_operand (expressionS *e)
7957{
ee86248c
JB
7958 char *end;
7959 const reg_entry *r;
4d1bb795 7960
ee86248c
JB
7961 switch (*input_line_pointer)
7962 {
7963 case REGISTER_PREFIX:
7964 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB
7965 if (r)
7966 {
7967 e->X_op = O_register;
7968 e->X_add_number = r - i386_regtab;
7969 input_line_pointer = end;
7970 }
ee86248c
JB
7971 break;
7972
7973 case '[':
7974 assert (intel_syntax);
7975 end = input_line_pointer++;
7976 expression (e);
7977 if (*input_line_pointer == ']')
7978 {
7979 ++input_line_pointer;
7980 e->X_op_symbol = make_expr_symbol (e);
7981 e->X_add_symbol = NULL;
7982 e->X_add_number = 0;
7983 e->X_op = O_index;
7984 }
7985 else
7986 {
7987 e->X_op = O_absent;
7988 input_line_pointer = end;
7989 }
7990 break;
4d1bb795
JB
7991 }
7992}
7993
252b5132 7994\f
4cc782b5 7995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7996const char *md_shortopts = "kVQ:sqn";
252b5132 7997#else
12b55ccc 7998const char *md_shortopts = "qn";
252b5132 7999#endif
6e0b89ee 8000
3e73aa7c 8001#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM
8002#define OPTION_64 (OPTION_MD_BASE + 1)
8003#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L
8004#define OPTION_MARCH (OPTION_MD_BASE + 3)
8005#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L
8006#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8007#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8008#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8009#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8010#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8011#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8012#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 8013
99ad8390
NC
8014struct option md_longopts[] =
8015{
3e73aa7c 8016 {"32", no_argument, NULL, OPTION_32},
99ad8390 8017#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 8018 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 8019#endif
b3b91714 8020 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L
8021 {"march", required_argument, NULL, OPTION_MARCH},
8022 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L
8023 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8024 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8025 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8026 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8027 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8028 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8029 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH
8030 {NULL, no_argument, NULL, 0}
8031};
8032size_t md_longopts_size = sizeof (md_longopts);
8033
8034int
9103f4f4 8035md_parse_option (int c, char *arg)
252b5132 8036{
9103f4f4 8037 unsigned int i;
6305a203 8038 char *arch, *next;
9103f4f4 8039
252b5132
RH
8040 switch (c)
8041 {
12b55ccc
L
8042 case 'n':
8043 optimize_align_code = 0;
8044 break;
8045
a38cf1db
AM
8046 case 'q':
8047 quiet_warnings = 1;
252b5132
RH
8048 break;
8049
8050#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM
8051 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8052 should be emitted or not. FIXME: Not implemented. */
8053 case 'Q':
252b5132
RH
8054 break;
8055
8056 /* -V: SVR4 argument to print version ID. */
8057 case 'V':
8058 print_version_id ();
8059 break;
8060
a38cf1db
AM
8061 /* -k: Ignore for FreeBSD compatibility. */
8062 case 'k':
252b5132 8063 break;
4cc782b5
ILT
8064
8065 case 's':
8066 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8067 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8068 break;
99ad8390
NC
8069#endif
8070#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH
8071 case OPTION_64:
8072 {
8073 const char **list, **l;
8074
3e73aa7c
JH
8075 list = bfd_target_list ();
8076 for (l = list; *l != NULL; l++)
8620418b 8077 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC
8078 || strcmp (*l, "coff-x86-64") == 0
8079 || strcmp (*l, "pe-x86-64") == 0
8080 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM
8081 {
8082 default_arch = "x86_64";
8083 break;
8084 }
3e73aa7c 8085 if (*l == NULL)
6e0b89ee 8086 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH
8087 free (list);
8088 }
8089 break;
8090#endif
252b5132 8091
6e0b89ee
AM
8092 case OPTION_32:
8093 default_arch = "i386";
8094 break;
8095
b3b91714
AM
8096 case OPTION_DIVIDE:
8097#ifdef SVR4_COMMENT_CHARS
8098 {
8099 char *n, *t;
8100 const char *s;
8101
8102 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8103 t = n;
8104 for (s = i386_comment_chars; *s != '\0'; s++)
8105 if (*s != '/')
8106 *t++ = *s;
8107 *t = '\0';
8108 i386_comment_chars = n;
8109 }
8110#endif
8111 break;
8112
9103f4f4 8113 case OPTION_MARCH:
6305a203
L
8114 arch = xstrdup (arg);
8115 do
9103f4f4 8116 {
6305a203
L
8117 if (*arch == '.')
8118 as_fatal (_("Invalid -march= option: `%s'"), arg);
8119 next = strchr (arch, '+');
8120 if (next)
8121 *next++ = '\0';
8122 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 8123 {
6305a203 8124 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 8125 {
6305a203
L
8126 /* Processor. */
8127 cpu_arch_name = cpu_arch[i].name;
8128 cpu_sub_arch_name = NULL;
8129 cpu_arch_flags = cpu_arch[i].flags;
8130 cpu_arch_isa = cpu_arch[i].type;
8131 cpu_arch_isa_flags = cpu_arch[i].flags;
8132 if (!cpu_arch_tune_set)
8133 {
8134 cpu_arch_tune = cpu_arch_isa;
8135 cpu_arch_tune_flags = cpu_arch_isa_flags;
8136 }
8137 break;
8138 }
8139 else if (*cpu_arch [i].name == '.'
8140 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8141 {
8142 /* ISA entension. */
8143 i386_cpu_flags flags;
8144 flags = cpu_flags_or (cpu_arch_flags,
8145 cpu_arch[i].flags);
0dfbf9d7 8146 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L
8147 {
8148 if (cpu_sub_arch_name)
8149 {
8150 char *name = cpu_sub_arch_name;
8151 cpu_sub_arch_name = concat (name,
8152 cpu_arch[i].name,
1bf57e9f 8153 (const char *) NULL);
6305a203
L
8154 free (name);
8155 }
8156 else
8157 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8158 cpu_arch_flags = flags;
8159 }
8160 break;
ccc9c027 8161 }
9103f4f4 8162 }
6305a203
L
8163
8164 if (i >= ARRAY_SIZE (cpu_arch))
8165 as_fatal (_("Invalid -march= option: `%s'"), arg);
8166
8167 arch = next;
9103f4f4 8168 }
6305a203 8169 while (next != NULL );
9103f4f4
L
8170 break;
8171
8172 case OPTION_MTUNE:
8173 if (*arg == '.')
8174 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8175 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8176 {
8177 if (strcmp (arg, cpu_arch [i].name) == 0)
8178 {
ccc9c027 8179 cpu_arch_tune_set = 1;
9103f4f4
L
8180 cpu_arch_tune = cpu_arch [i].type;
8181 cpu_arch_tune_flags = cpu_arch[i].flags;
8182 break;
8183 }
8184 }
8185 if (i >= ARRAY_SIZE (cpu_arch))
8186 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8187 break;
8188
1efbbeb4
L
8189 case OPTION_MMNEMONIC:
8190 if (strcasecmp (arg, "att") == 0)
8191 intel_mnemonic = 0;
8192 else if (strcasecmp (arg, "intel") == 0)
8193 intel_mnemonic = 1;
8194 else
8195 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8196 break;
8197
8198 case OPTION_MSYNTAX:
8199 if (strcasecmp (arg, "att") == 0)
8200 intel_syntax = 0;
8201 else if (strcasecmp (arg, "intel") == 0)
8202 intel_syntax = 1;
8203 else
8204 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8205 break;
8206
8207 case OPTION_MINDEX_REG:
8208 allow_index_reg = 1;
8209 break;
8210
8211 case OPTION_MNAKED_REG:
8212 allow_naked_reg = 1;
8213 break;
8214
8215 case OPTION_MOLD_GCC:
8216 old_gcc = 1;
1efbbeb4
L
8217 break;
8218
c0f3af97
L
8219 case OPTION_MSSE2AVX:
8220 sse2avx = 1;
8221 break;
8222
daf50ae7
L
8223 case OPTION_MSSE_CHECK:
8224 if (strcasecmp (arg, "error") == 0)
8225 sse_check = sse_check_error;
8226 else if (strcasecmp (arg, "warning") == 0)
8227 sse_check = sse_check_warning;
8228 else if (strcasecmp (arg, "none") == 0)
8229 sse_check = sse_check_none;
8230 else
8231 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8232 break;
8233
252b5132
RH
8234 default:
8235 return 0;
8236 }
8237 return 1;
8238}
8239
8240void
8241md_show_usage (stream)
8242 FILE *stream;
8243{
4cc782b5
ILT
8244#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8245 fprintf (stream, _("\
a38cf1db
AM
8246 -Q ignored\n\
8247 -V print assembler version number\n\
b3b91714
AM
8248 -k ignored\n"));
8249#endif
8250 fprintf (stream, _("\
12b55ccc 8251 -n Do not optimize code alignment\n\
b3b91714
AM
8252 -q quieten some warnings\n"));
8253#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8254 fprintf (stream, _("\
a38cf1db 8255 -s ignored\n"));
b3b91714 8256#endif
751d281c
L
8257#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8258 fprintf (stream, _("\
8259 --32/--64 generate 32bit/64bit code\n"));
8260#endif
b3b91714
AM
8261#ifdef SVR4_COMMENT_CHARS
8262 fprintf (stream, _("\
8263 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM
8264#else
8265 fprintf (stream, _("\
b3b91714 8266 --divide ignored\n"));
4cc782b5 8267#endif
9103f4f4 8268 fprintf (stream, _("\
6305a203
L
8269 -march=CPU[,+EXTENSION...]\n\
8270 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L
8271 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8272 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8273 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8274 generic32, generic64\n\
599121aa
L
8275 EXTENSION is combination of:\n\
8276 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695 8277 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2
L
8278 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8279 sse5, svme, abm, padlock\n"));
6305a203 8280 fprintf (stream, _("\
2cb4f3d5
L
8281 -mtune=CPU optimize for CPU, CPU is one of:\n\
8282 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8283 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8284 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8285 generic32, generic64\n"));
ba104c83 8286 fprintf (stream, _("\
c0f3af97
L
8287 -msse2avx encode SSE instructions with VEX prefix\n"));
8288 fprintf (stream, _("\
daf50ae7
L
8289 -msse-check=[none|error|warning]\n\
8290 check SSE instructions\n"));
8291 fprintf (stream, _("\
ba104c83
L
8292 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8293 fprintf (stream, _("\
8294 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8295 fprintf (stream, _("\
8296 -mindex-reg support pseudo index registers\n"));
8297 fprintf (stream, _("\
8298 -mnaked-reg don't require `%%' prefix for registers\n"));
8299 fprintf (stream, _("\
8300 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH
8301}
8302
3e73aa7c 8303#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8304 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH
8305
8306/* Pick the target format to use. */
8307
47926f60 8308const char *
e3bb37b5 8309i386_target_format (void)
252b5132 8310{
3e73aa7c 8311 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L
8312 {
8313 set_code_flag (CODE_64BIT);
0dfbf9d7 8314 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L
8315 {
8316 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8317 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8318 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8319 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8320 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8321 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8322 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8323 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L
8324 cpu_arch_isa_flags.bitfield.cpusse = 1;
8325 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8326 }
0dfbf9d7 8327 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L
8328 {
8329 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8330 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8331 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8332 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8333 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8334 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8335 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8336 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L
8337 cpu_arch_tune_flags.bitfield.cpusse = 1;
8338 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8339 }
9103f4f4 8340 }
3e73aa7c 8341 else if (!strcmp (default_arch, "i386"))
9103f4f4
L
8342 {
8343 set_code_flag (CODE_32BIT);
0dfbf9d7 8344 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L
8345 {
8346 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8347 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8348 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8349 }
0dfbf9d7 8350 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L
8351 {
8352 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8353 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8354 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8355 }
9103f4f4 8356 }
3e73aa7c
JH
8357 else
8358 as_fatal (_("Unknown architecture"));
252b5132
RH
8359 switch (OUTPUT_FLAVOR)
8360 {
872ce6ff
L
8361#ifdef TE_PEP
8362 case bfd_target_coff_flavour:
b01ee69d 8363 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "pe-i386";
872ce6ff
L
8364 break;
8365#endif
4c63da97
AM
8366#ifdef OBJ_MAYBE_AOUT
8367 case bfd_target_aout_flavour:
47926f60 8368 return AOUT_TARGET_FORMAT;
4c63da97
AM
8369#endif
8370#ifdef OBJ_MAYBE_COFF
252b5132
RH
8371 case bfd_target_coff_flavour:
8372 return "coff-i386";
4c63da97 8373#endif
3e73aa7c 8374#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8375 case bfd_target_elf_flavour:
3e73aa7c 8376 {
e5cb08ac 8377 if (flag_code == CODE_64BIT)
4fa24527
JB
8378 {
8379 object_64bit = 1;
8380 use_rela_relocations = 1;
8381 }
9d7cbccd 8382 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8383 }
4c63da97 8384#endif
252b5132
RH
8385 default:
8386 abort ();
8387 return NULL;
8388 }
8389}
8390
47926f60 8391#endif /* OBJ_MAYBE_ more than one */
a847613f
AM
8392
8393#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L
8394void
8395i386_elf_emit_arch_note (void)
a847613f 8396{
718ddfc0 8397 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM
8398 {
8399 char *p;
8400 asection *seg = now_seg;
8401 subsegT subseg = now_subseg;
8402 Elf_Internal_Note i_note;
8403 Elf_External_Note e_note;
8404 asection *note_secp;
8405 int len;
8406
8407 /* Create the .note section. */
8408 note_secp = subseg_new (".note", 0);
8409 bfd_set_section_flags (stdoutput,
8410 note_secp,
8411 SEC_HAS_CONTENTS | SEC_READONLY);
8412
8413 /* Process the arch string. */
8414 len = strlen (cpu_arch_name);
8415
8416 i_note.namesz = len + 1;
8417 i_note.descsz = 0;
8418 i_note.type = NT_ARCH;
8419 p = frag_more (sizeof (e_note.namesz));
8420 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8421 p = frag_more (sizeof (e_note.descsz));
8422 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8423 p = frag_more (sizeof (e_note.type));
8424 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8425 p = frag_more (len + 1);
8426 strcpy (p, cpu_arch_name);
8427
8428 frag_align (2, 0, 0);
8429
8430 subseg_set (seg, subseg);
8431 }
8432}
8433#endif
252b5132 8434\f
252b5132
RH
8435symbolS *
8436md_undefined_symbol (name)
8437 char *name;
8438{
18dc2407
ILT
8439 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8440 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8441 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8442 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM
8443 {
8444 if (!GOT_symbol)
8445 {
8446 if (symbol_find (name))
8447 as_bad (_("GOT already in symbol table"));
8448 GOT_symbol = symbol_new (name, undefined_section,
8449 (valueT) 0, &zero_address_frag);
8450 };
8451 return GOT_symbol;
8452 }
252b5132
RH
8453 return 0;
8454}
8455
8456/* Round up a section size to the appropriate boundary. */
47926f60 8457
252b5132
RH
8458valueT
8459md_section_align (segment, size)
ab9da554 8460 segT segment ATTRIBUTE_UNUSED;
252b5132
RH
8461 valueT size;
8462{
4c63da97
AM
8463#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8464 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8465 {
8466 /* For a.out, force the section size to be aligned. If we don't do
8467 this, BFD will align it for us, but it will not write out the
8468 final bytes of the section. This may be a bug in BFD, but it is
8469 easier to fix it here since that is how the other a.out targets
8470 work. */
8471 int align;
8472
8473 align = bfd_get_section_alignment (stdoutput, segment);
8474 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8475 }
252b5132
RH
8476#endif
8477
8478 return size;
8479}
8480
8481/* On the i386, PC-relative offsets are relative to the start of the
8482 next instruction. That is, the address of the offset, plus its
8483 size, since the offset is always the last part of the insn. */
8484
8485long
e3bb37b5 8486md_pcrel_from (fixS *fixP)
252b5132
RH
8487{
8488 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8489}
8490
8491#ifndef I386COFF
8492
8493static void
e3bb37b5 8494s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8495{
29b0f896 8496 int temp;
252b5132 8497
8a75718c
JB
8498#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8499 if (IS_ELF)
8500 obj_elf_section_change_hook ();
8501#endif
252b5132
RH
8502 temp = get_absolute_expression ();
8503 subseg_set (bss_section, (subsegT) temp);
8504 demand_empty_rest_of_line ();
8505}
8506
8507#endif
8508
252b5132 8509void
e3bb37b5 8510i386_validate_fix (fixS *fixp)
252b5132
RH
8511{
8512 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8513 {
23df1078
JH
8514 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8515 {
4fa24527 8516 if (!object_64bit)
23df1078
JH
8517 abort ();
8518 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8519 }
8520 else
8521 {
4fa24527 8522 if (!object_64bit)
d6ab8113
JB
8523 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8524 else
8525 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8526 }
252b5132
RH
8527 fixp->fx_subsy = 0;
8528 }
8529}
8530
252b5132
RH
8531arelent *
8532tc_gen_reloc (section, fixp)
ab9da554 8533 asection *section ATTRIBUTE_UNUSED;
252b5132
RH
8534 fixS *fixp;
8535{
8536 arelent *rel;
8537 bfd_reloc_code_real_type code;
8538
8539 switch (fixp->fx_r_type)
8540 {
3e73aa7c
JH
8541 case BFD_RELOC_X86_64_PLT32:
8542 case BFD_RELOC_X86_64_GOT32:
8543 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH
8544 case BFD_RELOC_386_PLT32:
8545 case BFD_RELOC_386_GOT32:
8546 case BFD_RELOC_386_GOTOFF:
8547 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ
8548 case BFD_RELOC_386_TLS_GD:
8549 case BFD_RELOC_386_TLS_LDM:
8550 case BFD_RELOC_386_TLS_LDO_32:
8551 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ
8552 case BFD_RELOC_386_TLS_IE:
8553 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ
8554 case BFD_RELOC_386_TLS_LE_32:
8555 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO
8556 case BFD_RELOC_386_TLS_GOTDESC:
8557 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ
8558 case BFD_RELOC_X86_64_TLSGD:
8559 case BFD_RELOC_X86_64_TLSLD:
8560 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8561 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ
8562 case BFD_RELOC_X86_64_GOTTPOFF:
8563 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB
8564 case BFD_RELOC_X86_64_TPOFF64:
8565 case BFD_RELOC_X86_64_GOTOFF64:
8566 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ
8567 case BFD_RELOC_X86_64_GOT64:
8568 case BFD_RELOC_X86_64_GOTPCREL64:
8569 case BFD_RELOC_X86_64_GOTPC64:
8570 case BFD_RELOC_X86_64_GOTPLT64:
8571 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO
8572 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8573 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH
8574 case BFD_RELOC_RVA:
8575 case BFD_RELOC_VTABLE_ENTRY:
8576 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC
8577#ifdef TE_PE
8578 case BFD_RELOC_32_SECREL:
8579#endif
252b5132
RH
8580 code = fixp->fx_r_type;
8581 break;
dbbaec26
L
8582 case BFD_RELOC_X86_64_32S:
8583 if (!fixp->fx_pcrel)
8584 {
8585 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8586 code = fixp->fx_r_type;
8587 break;
8588 }
252b5132 8589 default:
93382f6d 8590 if (fixp->fx_pcrel)
252b5132 8591 {
93382f6d
AM
8592 switch (fixp->fx_size)
8593 {
8594 default:
b091f402
AM
8595 as_bad_where (fixp->fx_file, fixp->fx_line,
8596 _("can not do %d byte pc-relative relocation"),
8597 fixp->fx_size);
93382f6d
AM
8598 code = BFD_RELOC_32_PCREL;
8599 break;
8600 case 1: code = BFD_RELOC_8_PCREL; break;
8601 case 2: code = BFD_RELOC_16_PCREL; break;
8602 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB
8603#ifdef BFD64
8604 case 8: code = BFD_RELOC_64_PCREL; break;
8605#endif
93382f6d
AM
8606 }
8607 }
8608 else
8609 {
8610 switch (fixp->fx_size)
8611 {
8612 default:
b091f402
AM
8613 as_bad_where (fixp->fx_file, fixp->fx_line,
8614 _("can not do %d byte relocation"),
8615 fixp->fx_size);
93382f6d
AM
8616 code = BFD_RELOC_32;
8617 break;
8618 case 1: code = BFD_RELOC_8; break;
8619 case 2: code = BFD_RELOC_16; break;
8620 case 4: code = BFD_RELOC_32; break;
937149dd 8621#ifdef BFD64
3e73aa7c 8622 case 8: code = BFD_RELOC_64; break;
937149dd 8623#endif
93382f6d 8624 }
252b5132
RH
8625 }
8626 break;
8627 }
252b5132 8628
d182319b
JB
8629 if ((code == BFD_RELOC_32
8630 || code == BFD_RELOC_32_PCREL
8631 || code == BFD_RELOC_X86_64_32S)
252b5132
RH
8632 && GOT_symbol
8633 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8634 {
4fa24527 8635 if (!object_64bit)
d6ab8113
JB
8636 code = BFD_RELOC_386_GOTPC;
8637 else
8638 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8639 }
7b81dfbb
AJ
8640 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8641 && GOT_symbol
8642 && fixp->fx_addsy == GOT_symbol)
8643 {
8644 code = BFD_RELOC_X86_64_GOTPC64;
8645 }
252b5132
RH
8646
8647 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT
8648 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8649 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
8650
8651 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8652
3e73aa7c
JH
8653 if (!use_rela_relocations)
8654 {
8655 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8656 vtable entry to be used in the relocation's section offset. */
8657 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8658 rel->address = fixp->fx_offset;
252b5132 8659
c6682705 8660 rel->addend = 0;
3e73aa7c
JH
8661 }
8662 /* Use the rela in 64bit mode. */
252b5132 8663 else
3e73aa7c 8664 {
062cd5e7
AS
8665 if (!fixp->fx_pcrel)
8666 rel->addend = fixp->fx_offset;
8667 else
8668 switch (code)
8669 {
8670 case BFD_RELOC_X86_64_PLT32:
8671 case BFD_RELOC_X86_64_GOT32:
8672 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ
8673 case BFD_RELOC_X86_64_TLSGD:
8674 case BFD_RELOC_X86_64_TLSLD:
8675 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO
8676 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8677 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS
8678 rel->addend = fixp->fx_offset - fixp->fx_size;
8679 break;
8680 default:
8681 rel->addend = (section->vma
8682 - fixp->fx_size
8683 + fixp->fx_addnumber
8684 + md_pcrel_from (fixp));
8685 break;
8686 }
3e73aa7c
JH
8687 }
8688
252b5132
RH
8689 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8690 if (rel->howto == NULL)
8691 {
8692 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8693 _("cannot represent relocation type %s"),
252b5132
RH
8694 bfd_get_reloc_code_name (code));
8695 /* Set howto to a garbage value so that we can keep going. */
8696 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8697 assert (rel->howto != NULL);
8698 }
8699
8700 return rel;
8701}
8702
ee86248c 8703#include "tc-i386-intel.c"
54cfded0 8704
a60de03c
JB
8705void
8706tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8707{
a60de03c
JB
8708 int saved_naked_reg;
8709 char saved_register_dot;
54cfded0 8710
a60de03c
JB
8711 saved_naked_reg = allow_naked_reg;
8712 allow_naked_reg = 1;
8713 saved_register_dot = register_chars['.'];
8714 register_chars['.'] = '.';
8715 allow_pseudo_reg = 1;
8716 expression_and_evaluate (exp);
8717 allow_pseudo_reg = 0;
8718 register_chars['.'] = saved_register_dot;
8719 allow_naked_reg = saved_naked_reg;
8720
8721 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8722 {
a60de03c
JB
8723 if ((addressT) exp->X_add_number < i386_regtab_size)
8724 {
8725 exp->X_op = O_constant;
8726 exp->X_add_number = i386_regtab[exp->X_add_number]
8727 .dw2_regnum[flag_code >> 1];
8728 }
8729 else
8730 exp->X_op = O_illegal;
54cfded0 8731 }
54cfded0
AM
8732}
8733
8734void
8735tc_x86_frame_initial_instructions (void)
8736{
a60de03c
JB
8737 static unsigned int sp_regno[2];
8738
8739 if (!sp_regno[flag_code >> 1])
8740 {
8741 char *saved_input = input_line_pointer;
8742 char sp[][4] = {"esp", "rsp"};
8743 expressionS exp;
a4447b93 8744
a60de03c
JB
8745 input_line_pointer = sp[flag_code >> 1];
8746 tc_x86_parse_to_dw2regnum (&exp);
8747 assert (exp.X_op == O_constant);
8748 sp_regno[flag_code >> 1] = exp.X_add_number;
8749 input_line_pointer = saved_input;
8750 }
a4447b93 8751
a60de03c 8752 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8753 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8754}
d2b2c203
DJ
8755
8756int
8757i386_elf_section_type (const char *str, size_t len)
8758{
8759 if (flag_code == CODE_64BIT
8760 && len == sizeof ("unwind") - 1
8761 && strncmp (str, "unwind", 6) == 0)
8762 return SHT_X86_64_UNWIND;
8763
8764 return -1;
8765}
bb41ade5 8766
ad5fec3b
EB
8767#ifdef TE_SOLARIS
8768void
8769i386_solaris_fix_up_eh_frame (segT sec)
8770{
8771 if (flag_code == CODE_64BIT)
8772 elf_section_type (sec) = SHT_X86_64_UNWIND;
8773}
8774#endif
8775
bb41ade5
AM
8776#ifdef TE_PE
8777void
8778tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8779{
8780 expressionS expr;
8781
8782 expr.X_op = O_secrel;
8783 expr.X_add_symbol = symbol;
8784 expr.X_add_number = 0;
8785 emit_expr (&expr, size);
8786}
8787#endif
3b22753a
L
8788
8789#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8790/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8791
01e1a5bc 8792bfd_vma
3b22753a
L
8793x86_64_section_letter (int letter, char **ptr_msg)
8794{
8795 if (flag_code == CODE_64BIT)
8796 {
8797 if (letter == 'l')
8798 return SHF_X86_64_LARGE;
8799
8800 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8801 }
3b22753a 8802 else
64e74474 8803 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L
8804 return -1;
8805}
8806
01e1a5bc 8807bfd_vma
3b22753a
L
8808x86_64_section_word (char *str, size_t len)
8809{
8620418b 8810 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L
8811 return SHF_X86_64_LARGE;
8812
8813 return -1;
8814}
8815
8816static void
8817handle_large_common (int small ATTRIBUTE_UNUSED)
8818{
8819 if (flag_code != CODE_64BIT)
8820 {
8821 s_comm_internal (0, elf_common_parse);
8822 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8823 }
8824 else
8825 {
8826 static segT lbss_section;
8827 asection *saved_com_section_ptr = elf_com_section_ptr;
8828 asection *saved_bss_section = bss_section;
8829
8830 if (lbss_section == NULL)
8831 {
8832 flagword applicable;
8833 segT seg = now_seg;
8834 subsegT subseg = now_subseg;
8835
8836 /* The .lbss section is for local .largecomm symbols. */
8837 lbss_section = subseg_new (".lbss", 0);
8838 applicable = bfd_applicable_section_flags (stdoutput);
8839 bfd_set_section_flags (stdoutput, lbss_section,
8840 applicable & SEC_ALLOC);
8841 seg_info (lbss_section)->bss = 1;
8842
8843 subseg_set (seg, subseg);
8844 }
8845
8846 elf_com_section_ptr = &_bfd_elf_large_com_section;
8847 bss_section = lbss_section;
8848
8849 s_comm_internal (0, elf_common_parse);
8850
8851 elf_com_section_ptr = saved_com_section_ptr;
8852 bss_section = saved_bss_section;
8853 }
8854}
8855#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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