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x86: drop Vec_Disp8
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
a65babc9
L		 284 };
285
252b5132
RH		 286struct _i386_insn
287 {
47926f60 288 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 289 insn_template tm;
252b5132 290
7d5e4556
L		 291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
252b5132
RH		 293 char suffix;
294
47926f60 295 /* OPERANDS gives the number of given operands. */
252b5132
RH		 296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
47926f60 300 operands. */
252b5132
RH		 301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 304 use OP[i] for the corresponding operand. */
40fb9820 305 i386_operand_type types[MAX_OPERANDS];
252b5132 306
520dc8e8
AM		 307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
252b5132 310
3e73aa7c
JH		 311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313#define Operand_PCrel 1
314
252b5132 315 /* Relocation type for operand */
f86103b7 316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 317
252b5132
RH		 318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 325 explicit segment overrides are given. */
ce8a8b2f 326 const seg_entry *seg[2];
252b5132 327
8325cc63
JB		 328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
252b5132
RH		 331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 337 addressing modes of this insn are encoded. */
252b5132 338 modrm_byte rm;
3e73aa7c 339 rex_byte rex;
43234a1e 340 rex_byte vrex;
252b5132 341 sib_byte sib;
c0f3af97 342 vex_prefix vex;
b6169b20 343
43234a1e
L		 344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
86fa6981
L		 356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
891edac4 363
a501d77e
L		 364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
f8a5c266 371
86fa6981
L		 372 /* How to encode vector instructions. */
373 enum
374 {
375 vex_encoding_default = 0,
376 vex_encoding_vex2,
377 vex_encoding_vex3,
378 vex_encoding_evex
379 } vec_encoding;
380
d5de92cf
L		 381 /* REP prefix. */
382 const char *rep_prefix;
383
165de32a
L		 384 /* HLE prefix. */
385 const char *hle_prefix;
42164a71 386
7e8b059b
L		 387 /* Have BND prefix. */
388 const char *bnd_prefix;
389
04ef582a
L		 390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix;
392
891edac4 393 /* Error message. */
a65babc9 394 enum i386_error error;
252b5132
RH		 395 };
396
397typedef struct _i386_insn i386_insn;
398
43234a1e
L		 399/* Link RC type with corresponding string, that'll be looked for in
400 asm. */
401struct RC_name
402{
403 enum rc_type type;
404 const char *name;
405 unsigned int len;
406};
407
408static const struct RC_name RC_NamesTable[] =
409{
410 { rne, STRING_COMMA_LEN ("rn-sae") },
411 { rd, STRING_COMMA_LEN ("rd-sae") },
412 { ru, STRING_COMMA_LEN ("ru-sae") },
413 { rz, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly, STRING_COMMA_LEN ("sae") },
415};
416
252b5132
RH		 417/* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 419const char extra_symbol_chars[] = "*%-([{}"
252b5132 420#ifdef LEX_AT
32137342
NC		 421 "@"
422#endif
423#ifdef LEX_QM
424 "?"
252b5132 425#endif
32137342 426 ;
252b5132 427
29b0f896
AM		 428#if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 430 && !defined (TE_GNU) \
29b0f896 431 && !defined (TE_LINUX) \
8d63c93e
RM		 432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
29b0f896 434 && !defined (TE_FreeBSD) \
5b806d27 435 && !defined (TE_DragonFly) \
29b0f896 436 && !defined (TE_NetBSD)))
252b5132 437/* This array holds the chars that always start a comment. If the
b3b91714
AM		 438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440const char *i386_comment_chars = "#/";
441#define SVR4_COMMENT_CHARS 1
252b5132 442#define PREFIX_SEPARATOR '\\'
252b5132 443
b3b91714
AM		 444#else
445const char *i386_comment_chars = "#";
446#define PREFIX_SEPARATOR '/'
447#endif
448
252b5132
RH		 449/* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 453 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
252b5132 456 '/' isn't otherwise defined. */
b3b91714 457const char line_comment_chars[] = "#/";
252b5132 458
63a0b638 459const char line_separator_chars[] = ";";
252b5132 460
ce8a8b2f
AM		 461/* Chars that can be used to separate mant from exp in floating point
462 nums. */
252b5132
RH		 463const char EXP_CHARS[] = "eE";
464
ce8a8b2f
AM		 465/* Chars that mean this number is a floating point constant
466 As in 0f12.456
467 or 0d1.2345e12. */
252b5132
RH		 468const char FLT_CHARS[] = "fFdDxX";
469
ce8a8b2f 470/* Tables for lexical analysis. */
252b5132
RH		 471static char mnemonic_chars[256];
472static char register_chars[256];
473static char operand_chars[256];
474static char identifier_chars[256];
475static char digit_chars[256];
476
ce8a8b2f 477/* Lexical macros. */
252b5132
RH		 478#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479#define is_operand_char(x) (operand_chars[(unsigned char) x])
480#define is_register_char(x) (register_chars[(unsigned char) x])
481#define is_space_char(x) ((x) == ' ')
482#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483#define is_digit_char(x) (digit_chars[(unsigned char) x])
484
0234cb7c 485/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 486static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
487
488/* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
47926f60 491 assembler instruction). */
252b5132 492static char save_stack[32];
ce8a8b2f 493static char *save_stack_p;
252b5132
RH		 494#define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496#define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
498
47926f60 499/* The instruction we're assembling. */
252b5132
RH		 500static i386_insn i;
501
502/* Possible templates for current insn. */
503static const templates *current_templates;
504
31b2323c
L		 505/* Per instruction expressionS buffers: max displacements & immediates. */
506static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 508
47926f60 509/* Current operand we are working on. */
ee86248c 510static int this_operand = -1;
252b5132 511
3e73aa7c
JH		 512/* We support four different modes. FLAG_CODE variable is used to distinguish
513 these. */
514
515enum flag_code {
516 CODE_32BIT,
517 CODE_16BIT,
518 CODE_64BIT };
519
520static enum flag_code flag_code;
4fa24527 521static unsigned int object_64bit;
862be3fb 522static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 523static int use_rela_relocations = 0;
524
7af8ed2d
NC		 525#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
528
351f65ca
L		 529/* The ELF ABI to use. */
530enum x86_elf_abi
531{
532 I386_ABI,
7f56bc95
L		 533 X86_64_ABI,
534 X86_64_X32_ABI
351f65ca
L		 535};
536
537static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 538#endif
351f65ca 539
167ad85b
TG		 540#if defined (TE_PE) || defined (TE_PEP)
541/* Use big object file format. */
542static int use_big_obj = 0;
543#endif
544
8dcea932
L		 545#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546/* 1 if generating code for a shared library. */
547static int shared = 0;
548#endif
549
47926f60
KH		 550/* 1 for intel syntax,
551 0 if att syntax. */
552static int intel_syntax = 0;
252b5132 553
e89c5eaa
L		 554/* 1 for Intel64 ISA,
555 0 if AMD64 ISA. */
556static int intel64;
557
1efbbeb4
L		 558/* 1 for intel mnemonic,
559 0 if att mnemonic. */
560static int intel_mnemonic = !SYSV386_COMPAT;
561
5209009a 562/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 563static int old_gcc = OLDGCC_COMPAT;
564
a60de03c
JB		 565/* 1 if pseudo registers are permitted. */
566static int allow_pseudo_reg = 0;
567
47926f60
KH		 568/* 1 if register prefix % not required. */
569static int allow_naked_reg = 0;
252b5132 570
33eaf5de 571/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 572 instructions supporting it, even if this prefix wasn't specified
573 explicitly. */
574static int add_bnd_prefix = 0;
575
ba104c83 576/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 577static int allow_index_reg = 0;
578
d022bddd
IT		 579/* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581static int omit_lock_prefix = 0;
582
e4e00185
AS		 583/* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585static int avoid_fence = 0;
586
0cb4071e
L		 587/* 1 if the assembler should generate relax relocations. */
588
589static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591
7bab8ab5 592static enum check_kind
daf50ae7 593 {
7bab8ab5
JB		 594 check_none = 0,
595 check_warning,
596 check_error
daf50ae7 597 }
7bab8ab5 598sse_check, operand_check = check_warning;
daf50ae7 599
2ca3ace5
L		 600/* Register prefix used for error message. */
601static const char *register_prefix = "%";
602
47926f60
KH		 603/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606static char stackop_size = '\0';
eecb386c 607
12b55ccc
L		 608/* Non-zero to optimize code alignment. */
609int optimize_align_code = 1;
610
47926f60
KH		 611/* Non-zero to quieten some warnings. */
612static int quiet_warnings = 0;
a38cf1db 613
47926f60
KH		 614/* CPU name. */
615static const char *cpu_arch_name = NULL;
6305a203 616static char *cpu_sub_arch_name = NULL;
a38cf1db 617
47926f60 618/* CPU feature flags. */
40fb9820
L		 619static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
620
ccc9c027
L		 621/* If we have selected a cpu we are generating instructions for. */
622static int cpu_arch_tune_set = 0;
623
9103f4f4 624/* Cpu we are generating instructions for. */
fbf3f584 625enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 626
627/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 628static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 629
ccc9c027 630/* CPU instruction set architecture used. */
fbf3f584 631enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 632
9103f4f4 633/* CPU feature flags of instruction set architecture used. */
fbf3f584 634i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 635
fddf5b5b
AM		 636/* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638static unsigned int no_cond_jump_promotion = 0;
639
c0f3af97
L		 640/* Encode SSE instructions with VEX prefix. */
641static unsigned int sse2avx;
642
539f890d
L		 643/* Encode scalar AVX instructions with specific vector length. */
644static enum
645 {
646 vex128 = 0,
647 vex256
648 } avxscalar;
649
43234a1e
L		 650/* Encode scalar EVEX LIG instructions with specific vector length. */
651static enum
652 {
653 evexl128 = 0,
654 evexl256,
655 evexl512
656 } evexlig;
657
658/* Encode EVEX WIG instructions with specific evex.w. */
659static enum
660 {
661 evexw0 = 0,
662 evexw1
663 } evexwig;
664
d3d3c6db
IT		 665/* Value to encode in EVEX RC bits, for SAE-only instructions. */
666static enum rc_type evexrcig = rne;
667
29b0f896 668/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 669static symbolS *GOT_symbol;
29b0f896 670
a4447b93
RH		 671/* The dwarf2 return column, adjusted for 32 or 64 bit. */
672unsigned int x86_dwarf2_return_column;
673
674/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675int x86_cie_data_alignment;
676
252b5132 677/* Interface to relax_segment.
fddf5b5b
AM		 678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
252b5132 681
47926f60 682/* Types. */
93c2a809
AM		 683#define UNCOND_JUMP 0
684#define COND_JUMP 1
685#define COND_JUMP86 2
fddf5b5b 686
47926f60 687/* Sizes. */
252b5132
RH		 688#define CODE16 1
689#define SMALL 0
29b0f896 690#define SMALL16 (SMALL | CODE16)
252b5132 691#define BIG 2
29b0f896 692#define BIG16 (BIG | CODE16)
252b5132
RH		 693
694#ifndef INLINE
695#ifdef __GNUC__
696#define INLINE __inline__
697#else
698#define INLINE
699#endif
700#endif
701
fddf5b5b
AM		 702#define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704#define TYPE_FROM_RELAX_STATE(s) \
705 ((s) >> 2)
706#define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 708
709/* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
716
717const relax_typeS md_relax_table[] =
718{
24eab124
AM		 719 /* The fields are:
720 1) most positive reach of this state,
721 2) most negative reach of this state,
93c2a809 722 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 723 4) which index into the table to try if we can't fit into this one. */
252b5132 724
fddf5b5b 725 /* UNCOND_JUMP states. */
93c2a809
AM		 726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
252b5132 730 {0, 0, 4, 0},
93c2a809
AM		 731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 733 {0, 0, 2, 0},
734
93c2a809
AM		 735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
740 {0, 0, 5, 0},
fddf5b5b 741 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 742 1 extra opcode byte, 2 displacement bytes. */
743 {0, 0, 3, 0},
744
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
750 {0, 0, 5, 0},
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
753 {0, 0, 4, 0}
252b5132
RH		 754};
755
9103f4f4
L		 756static const arch_entry cpu_arch[] =
757{
89507696
JB		 758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
8a2c8fef 760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 761 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 763 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 765 CPU_NONE_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 767 CPU_I186_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 769 CPU_I286_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 771 CPU_I386_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 773 CPU_I486_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 775 CPU_I586_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 777 CPU_I686_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 779 CPU_I586_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 781 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 783 CPU_P2_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 785 CPU_P3_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 787 CPU_P4_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 789 CPU_CORE_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 791 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 793 CPU_CORE_FLAGS, 1 },
8a2c8fef 794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 795 CPU_CORE_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 797 CPU_CORE2_FLAGS, 1 },
8a2c8fef 798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 799 CPU_CORE2_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 801 CPU_COREI7_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 803 CPU_L1OM_FLAGS, 0 },
7a9068fe 804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 805 CPU_K1OM_FLAGS, 0 },
81486035 806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 807 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 809 CPU_K6_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 811 CPU_K6_2_FLAGS, 0 },
8a2c8fef 812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 813 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 815 CPU_K8_FLAGS, 1 },
8a2c8fef 816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 817 CPU_K8_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 819 CPU_K8_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 821 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 823 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 825 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 827 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 829 CPU_BDVER4_FLAGS, 0 },
029f3522 830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 831 CPU_ZNVER1_FLAGS, 0 },
7b458c12 832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 833 CPU_BTVER1_FLAGS, 0 },
7b458c12 834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 835 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_8087_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_287_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_387_FLAGS, 0 },
1848e567
L		 842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
843 CPU_687_FLAGS, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_MMX_FLAGS, 0 },
8a2c8fef 846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_SSE_FLAGS, 0 },
8a2c8fef 848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_SSE2_FLAGS, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_SSE3_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_AVX_FLAGS, 0 },
6c30d220 862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_AVX2_FLAGS, 0 },
43234a1e 864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_AVX512F_FLAGS, 0 },
43234a1e 866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_AVX512CD_FLAGS, 0 },
43234a1e 868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_AVX512ER_FLAGS, 0 },
43234a1e 870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_VMX_FLAGS, 0 },
8729a6f6 880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_SMX_FLAGS, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AES_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_F16C_FLAGS, 0 },
6c30d220 904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_BMI2_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_FMA_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_FMA4_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_XOP_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_LWP_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_MOVBE_FLAGS, 0 },
60aa667e 916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_CX16_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_EPT_FLAGS, 0 },
6c30d220 920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_LZCNT_FLAGS, 0 },
42164a71 922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_HLE_FLAGS, 0 },
42164a71 924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_RTM_FLAGS, 0 },
6c30d220 926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_CLFLUSH_FLAGS, 0 },
22109423 930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_NOP_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SVME_FLAGS, 1 },
8a2c8fef 944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_SVME_FLAGS, 0 },
8a2c8fef 946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_ABM_FLAGS, 0 },
87973e9f 950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_BMI_FLAGS, 0 },
2a2a0f38 952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_TBM_FLAGS, 0 },
e2e1fcde 954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_ADX_FLAGS, 0 },
e2e1fcde 956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_PRFCHW_FLAGS, 0 },
5c111e37 960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SMAP_FLAGS, 0 },
7e8b059b 962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_MPX_FLAGS, 0 },
a0046408 964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_SHA_FLAGS, 0 },
963f3586 966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_SE1_FLAGS, 0 },
c5e7287a 972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
983 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
985 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
987 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
989 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_CLZERO_FLAGS, 0 },
9916071f 992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_MWAITX_FLAGS, 0 },
8eab4136 994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 995 CPU_OSPKE_FLAGS, 0 },
8bc52696 996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 997 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
999 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 1000 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
1001 CPU_CET_FLAGS, 0 },
48521003
IT		 1002 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1003 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1004 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1005 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1006 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1007 CPU_VPCLMULQDQ_FLAGS, 0 },
293f5f65
L		 1008};
1009
1010static const noarch_entry cpu_noarch[] =
1011{
1012 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1013 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1014 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1015 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1016 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1017 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1018 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1019 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1020 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1021 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1022 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1023 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1024 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1025 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1026 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1035 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1036 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1037 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1038 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1039 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1040 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
e413e4e9
AM		 1041};
1042
704209c0 1043#ifdef I386COFF
a6c24e68
NC		 1044/* Like s_lcomm_internal in gas/read.c but the alignment string
1045 is allowed to be optional. */
1046
1047static symbolS *
1048pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1049{
1050 addressT align = 0;
1051
1052 SKIP_WHITESPACE ();
1053
7ab9ffdd 1054 if (needs_align
a6c24e68
NC		 1055 && *input_line_pointer == ',')
1056 {
1057 align = parse_align (needs_align - 1);
7ab9ffdd 1058
a6c24e68
NC		 1059 if (align == (addressT) -1)
1060 return NULL;
1061 }
1062 else
1063 {
1064 if (size >= 8)
1065 align = 3;
1066 else if (size >= 4)
1067 align = 2;
1068 else if (size >= 2)
1069 align = 1;
1070 else
1071 align = 0;
1072 }
1073
1074 bss_alloc (symbolP, size, align);
1075 return symbolP;
1076}
1077
704209c0 1078static void
a6c24e68
NC		 1079pe_lcomm (int needs_align)
1080{
1081 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1082}
704209c0 1083#endif
a6c24e68 1084
29b0f896
AM		 1085const pseudo_typeS md_pseudo_table[] =
1086{
1087#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1088 {"align", s_align_bytes, 0},
1089#else
1090 {"align", s_align_ptwo, 0},
1091#endif
1092 {"arch", set_cpu_arch, 0},
1093#ifndef I386COFF
1094 {"bss", s_bss, 0},
a6c24e68
NC		 1095#else
1096 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1097#endif
1098 {"ffloat", float_cons, 'f'},
1099 {"dfloat", float_cons, 'd'},
1100 {"tfloat", float_cons, 'x'},
1101 {"value", cons, 2},
d182319b 1102 {"slong", signed_cons, 4},
29b0f896
AM		 1103 {"noopt", s_ignore, 0},
1104 {"optim", s_ignore, 0},
1105 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1106 {"code16", set_code_flag, CODE_16BIT},
1107 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1108#ifdef BFD64
29b0f896 1109 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1110#endif
29b0f896
AM		 1111 {"intel_syntax", set_intel_syntax, 1},
1112 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1113 {"intel_mnemonic", set_intel_mnemonic, 1},
1114 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1115 {"allow_index_reg", set_allow_index_reg, 1},
1116 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1117 {"sse_check", set_check, 0},
1118 {"operand_check", set_check, 1},
3b22753a
L		 1119#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1120 {"largecomm", handle_large_common, 0},
07a53e5c 1121#else
e3bb37b5 1122 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1123 {"loc", dwarf2_directive_loc, 0},
1124 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1125#endif
6482c264
NC		 1126#ifdef TE_PE
1127 {"secrel32", pe_directive_secrel, 0},
1128#endif
29b0f896
AM		 1129 {0, 0, 0}
1130};
1131
1132/* For interface with expression (). */
1133extern char *input_line_pointer;
1134
1135/* Hash table for instruction mnemonic lookup. */
1136static struct hash_control *op_hash;
1137
1138/* Hash table for register lookup. */
1139static struct hash_control *reg_hash;
1140\f
252b5132 1141void
e3bb37b5 1142i386_align_code (fragS *fragP, int count)
252b5132 1143{
ce8a8b2f
AM		 1144 /* Various efficient no-op patterns for aligning code labels.
1145 Note: Don't try to assemble the instructions in the comments.
1146 0L and 0w are not legal. */
bad6e36d 1147 static const unsigned char f32_1[] =
252b5132 1148 {0x90}; /* nop */
bad6e36d 1149 static const unsigned char f32_2[] =
ccc9c027 1150 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1151 static const unsigned char f32_3[] =
252b5132 1152 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1153 static const unsigned char f32_4[] =
252b5132 1154 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1155 static const unsigned char f32_5[] =
252b5132
RH		 1156 {0x90, /* nop */
1157 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1158 static const unsigned char f32_6[] =
252b5132 1159 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1160 static const unsigned char f32_7[] =
252b5132 1161 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1162 static const unsigned char f32_8[] =
252b5132
RH		 1163 {0x90, /* nop */
1164 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1165 static const unsigned char f32_9[] =
252b5132
RH		 1166 {0x89,0xf6, /* movl %esi,%esi */
1167 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1168 static const unsigned char f32_10[] =
252b5132
RH		 1169 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1170 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1171 static const unsigned char f32_11[] =
252b5132
RH		 1172 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1173 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1174 static const unsigned char f32_12[] =
252b5132
RH		 1175 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1176 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1177 static const unsigned char f32_13[] =
252b5132
RH		 1178 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1179 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1180 static const unsigned char f32_14[] =
252b5132
RH		 1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1182 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1183 static const unsigned char f16_3[] =
c3332e24 1184 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1185 static const unsigned char f16_4[] =
252b5132 1186 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1187 static const unsigned char f16_5[] =
252b5132
RH		 1188 {0x90, /* nop */
1189 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1190 static const unsigned char f16_6[] =
252b5132
RH		 1191 {0x89,0xf6, /* mov %si,%si */
1192 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1193 static const unsigned char f16_7[] =
252b5132
RH		 1194 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1195 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1196 static const unsigned char f16_8[] =
252b5132
RH		 1197 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1198 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1199 static const unsigned char jump_31[] =
76bc74dc
L		 1200 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1201 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1204 static const unsigned char *const f32_patt[] = {
252b5132 1205 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1206 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1207 };
bad6e36d 1208 static const unsigned char *const f16_patt[] = {
76bc74dc 1209 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1210 };
ccc9c027 1211 /* nopl (%[re]ax) */
bad6e36d 1212 static const unsigned char alt_3[] =
ccc9c027
L		 1213 {0x0f,0x1f,0x00};
1214 /* nopl 0(%[re]ax) */
bad6e36d 1215 static const unsigned char alt_4[] =
ccc9c027
L		 1216 {0x0f,0x1f,0x40,0x00};
1217 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1218 static const unsigned char alt_5[] =
ccc9c027
L		 1219 {0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1221 static const unsigned char alt_6[] =
ccc9c027
L		 1222 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1223 /* nopl 0L(%[re]ax) */
bad6e36d 1224 static const unsigned char alt_7[] =
ccc9c027
L		 1225 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1226 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1227 static const unsigned char alt_8[] =
ccc9c027
L		 1228 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1230 static const unsigned char alt_9[] =
ccc9c027
L		 1231 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1233 static const unsigned char alt_10[] =
ccc9c027 1234 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1235 static const unsigned char *const alt_patt[] = {
ccc9c027 1236 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1237 alt_9, alt_10
ccc9c027 1238 };
252b5132 1239
76bc74dc
L		 1240 /* Only align for at least a positive non-zero boundary. */
1241 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1242 return;
3e73aa7c 1243
ccc9c027
L		 1244 /* We need to decide which NOP sequence to use for 32bit and
1245 64bit. When -mtune= is used:
4eed87de 1246
76bc74dc
L		 1247 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1248 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1249 2. For the rest, alt_patt will be used.
1250
1251 When -mtune= isn't used, alt_patt will be used if
22109423 1252 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1253 be used.
ccc9c027
L		 1254
1255 When -march= or .arch is used, we can't use anything beyond
1256 cpu_arch_isa_flags. */
1257
1258 if (flag_code == CODE_16BIT)
1259 {
ccc9c027 1260 if (count > 8)
33fef721 1261 {
76bc74dc
L		 1262 memcpy (fragP->fr_literal + fragP->fr_fix,
1263 jump_31, count);
1264 /* Adjust jump offset. */
1265 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1266 }
76bc74dc
L		 1267 else
1268 memcpy (fragP->fr_literal + fragP->fr_fix,
1269 f16_patt[count - 1], count);
252b5132 1270 }
33fef721 1271 else
ccc9c027 1272 {
bad6e36d 1273 const unsigned char *const *patt = NULL;
ccc9c027 1274
fbf3f584 1275 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1276 {
1277 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1278 switch (cpu_arch_tune)
1279 {
1280 case PROCESSOR_UNKNOWN:
1281 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1282 optimize with nops. */
1283 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1284 patt = alt_patt;
ccc9c027
L		 1285 else
1286 patt = f32_patt;
1287 break;
ccc9c027
L		 1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
ef05d495 1290 case PROCESSOR_CORE:
76bc74dc 1291 case PROCESSOR_CORE2:
bd5295b2 1292 case PROCESSOR_COREI7:
3632d14b 1293 case PROCESSOR_L1OM:
7a9068fe 1294 case PROCESSOR_K1OM:
76bc74dc 1295 case PROCESSOR_GENERIC64:
ccc9c027
L		 1296 case PROCESSOR_K6:
1297 case PROCESSOR_ATHLON:
1298 case PROCESSOR_K8:
4eed87de 1299 case PROCESSOR_AMDFAM10:
8aedb9fe 1300 case PROCESSOR_BD:
029f3522 1301 case PROCESSOR_ZNVER:
7b458c12 1302 case PROCESSOR_BT:
80b8656c 1303 patt = alt_patt;
ccc9c027 1304 break;
76bc74dc 1305 case PROCESSOR_I386:
ccc9c027
L		 1306 case PROCESSOR_I486:
1307 case PROCESSOR_PENTIUM:
2dde1948 1308 case PROCESSOR_PENTIUMPRO:
81486035 1309 case PROCESSOR_IAMCU:
ccc9c027
L		 1310 case PROCESSOR_GENERIC32:
1311 patt = f32_patt;
1312 break;
4eed87de 1313 }
ccc9c027
L		 1314 }
1315 else
1316 {
fbf3f584 1317 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1318 {
1319 case PROCESSOR_UNKNOWN:
e6a14101 1320 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1321 PROCESSOR_UNKNOWN. */
1322 abort ();
1323 break;
1324
76bc74dc 1325 case PROCESSOR_I386:
ccc9c027
L		 1326 case PROCESSOR_I486:
1327 case PROCESSOR_PENTIUM:
81486035 1328 case PROCESSOR_IAMCU:
ccc9c027
L		 1329 case PROCESSOR_K6:
1330 case PROCESSOR_ATHLON:
1331 case PROCESSOR_K8:
4eed87de 1332 case PROCESSOR_AMDFAM10:
8aedb9fe 1333 case PROCESSOR_BD:
029f3522 1334 case PROCESSOR_ZNVER:
7b458c12 1335 case PROCESSOR_BT:
ccc9c027
L		 1336 case PROCESSOR_GENERIC32:
1337 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1338 with nops. */
1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1340 patt = alt_patt;
ccc9c027
L		 1341 else
1342 patt = f32_patt;
1343 break;
76bc74dc
L		 1344 case PROCESSOR_PENTIUMPRO:
1345 case PROCESSOR_PENTIUM4:
1346 case PROCESSOR_NOCONA:
1347 case PROCESSOR_CORE:
ef05d495 1348 case PROCESSOR_CORE2:
bd5295b2 1349 case PROCESSOR_COREI7:
3632d14b 1350 case PROCESSOR_L1OM:
7a9068fe 1351 case PROCESSOR_K1OM:
22109423 1352 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1353 patt = alt_patt;
ccc9c027
L		 1354 else
1355 patt = f32_patt;
1356 break;
1357 case PROCESSOR_GENERIC64:
80b8656c 1358 patt = alt_patt;
ccc9c027 1359 break;
4eed87de 1360 }
ccc9c027
L		 1361 }
1362
76bc74dc
L		 1363 if (patt == f32_patt)
1364 {
1365 /* If the padding is less than 15 bytes, we use the normal
1366 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1367 its offset. */
1368 int limit;
76ba9986 1369
711eedef
L		 1370 /* For 64bit, the limit is 3 bytes. */
1371 if (flag_code == CODE_64BIT
1372 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1373 limit = 3;
1374 else
1375 limit = 15;
1376 if (count < limit)
76bc74dc
L		 1377 memcpy (fragP->fr_literal + fragP->fr_fix,
1378 patt[count - 1], count);
1379 else
1380 {
1381 memcpy (fragP->fr_literal + fragP->fr_fix,
1382 jump_31, count);
1383 /* Adjust jump offset. */
1384 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1385 }
1386 }
1387 else
1388 {
80b8656c
L		 1389 /* Maximum length of an instruction is 10 byte. If the
1390 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1391 we have to break it into smaller pieces. */
1392 int padding = count;
80b8656c 1393 while (padding > 10)
76bc74dc 1394 {
80b8656c 1395 padding -= 10;
76bc74dc 1396 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1397 patt [9], 10);
76bc74dc
L		 1398 }
1399
1400 if (padding)
1401 memcpy (fragP->fr_literal + fragP->fr_fix,
1402 patt [padding - 1], padding);
1403 }
ccc9c027 1404 }
33fef721 1405 fragP->fr_var = count;
252b5132
RH		 1406}
1407
c6fb90c8 1408static INLINE int
0dfbf9d7 1409operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1410{
0dfbf9d7 1411 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1412 {
1413 case 3:
0dfbf9d7 1414 if (x->array[2])
c6fb90c8 1415 return 0;
1a0670f3 1416 /* Fall through. */
c6fb90c8 1417 case 2:
0dfbf9d7 1418 if (x->array[1])
c6fb90c8 1419 return 0;
1a0670f3 1420 /* Fall through. */
c6fb90c8 1421 case 1:
0dfbf9d7 1422 return !x->array[0];
c6fb90c8
L		 1423 default:
1424 abort ();
1425 }
40fb9820
L		 1426}
1427
c6fb90c8 1428static INLINE void
0dfbf9d7 1429operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1430{
0dfbf9d7 1431 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1432 {
1433 case 3:
0dfbf9d7 1434 x->array[2] = v;
1a0670f3 1435 /* Fall through. */
c6fb90c8 1436 case 2:
0dfbf9d7 1437 x->array[1] = v;
1a0670f3 1438 /* Fall through. */
c6fb90c8 1439 case 1:
0dfbf9d7 1440 x->array[0] = v;
1a0670f3 1441 /* Fall through. */
c6fb90c8
L		 1442 break;
1443 default:
1444 abort ();
1445 }
1446}
40fb9820 1447
c6fb90c8 1448static INLINE int
0dfbf9d7
L		 1449operand_type_equal (const union i386_operand_type *x,
1450 const union i386_operand_type *y)
c6fb90c8 1451{
0dfbf9d7 1452 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1453 {
1454 case 3:
0dfbf9d7 1455 if (x->array[2] != y->array[2])
c6fb90c8 1456 return 0;
1a0670f3 1457 /* Fall through. */
c6fb90c8 1458 case 2:
0dfbf9d7 1459 if (x->array[1] != y->array[1])
c6fb90c8 1460 return 0;
1a0670f3 1461 /* Fall through. */
c6fb90c8 1462 case 1:
0dfbf9d7 1463 return x->array[0] == y->array[0];
c6fb90c8
L		 1464 break;
1465 default:
1466 abort ();
1467 }
1468}
40fb9820 1469
0dfbf9d7
L		 1470static INLINE int
1471cpu_flags_all_zero (const union i386_cpu_flags *x)
1472{
1473 switch (ARRAY_SIZE(x->array))
1474 {
53467f57
IT		 1475 case 4:
1476 if (x->array[3])
1477 return 0;
1478 /* Fall through. */
0dfbf9d7
L		 1479 case 3:
1480 if (x->array[2])
1481 return 0;
1a0670f3 1482 /* Fall through. */
0dfbf9d7
L		 1483 case 2:
1484 if (x->array[1])
1485 return 0;
1a0670f3 1486 /* Fall through. */
0dfbf9d7
L		 1487 case 1:
1488 return !x->array[0];
1489 default:
1490 abort ();
1491 }
1492}
1493
0dfbf9d7
L		 1494static INLINE int
1495cpu_flags_equal (const union i386_cpu_flags *x,
1496 const union i386_cpu_flags *y)
1497{
1498 switch (ARRAY_SIZE(x->array))
1499 {
53467f57
IT		 1500 case 4:
1501 if (x->array[3] != y->array[3])
1502 return 0;
1503 /* Fall through. */
0dfbf9d7
L		 1504 case 3:
1505 if (x->array[2] != y->array[2])
1506 return 0;
1a0670f3 1507 /* Fall through. */
0dfbf9d7
L		 1508 case 2:
1509 if (x->array[1] != y->array[1])
1510 return 0;
1a0670f3 1511 /* Fall through. */
0dfbf9d7
L		 1512 case 1:
1513 return x->array[0] == y->array[0];
1514 break;
1515 default:
1516 abort ();
1517 }
1518}
c6fb90c8
L		 1519
1520static INLINE int
1521cpu_flags_check_cpu64 (i386_cpu_flags f)
1522{
1523 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1524 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1525}
1526
c6fb90c8
L		 1527static INLINE i386_cpu_flags
1528cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1529{
c6fb90c8
L		 1530 switch (ARRAY_SIZE (x.array))
1531 {
53467f57
IT		 1532 case 4:
1533 x.array [3] &= y.array [3];
1534 /* Fall through. */
c6fb90c8
L		 1535 case 3:
1536 x.array [2] &= y.array [2];
1a0670f3 1537 /* Fall through. */
c6fb90c8
L		 1538 case 2:
1539 x.array [1] &= y.array [1];
1a0670f3 1540 /* Fall through. */
c6fb90c8
L		 1541 case 1:
1542 x.array [0] &= y.array [0];
1543 break;
1544 default:
1545 abort ();
1546 }
1547 return x;
1548}
40fb9820 1549
c6fb90c8
L		 1550static INLINE i386_cpu_flags
1551cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1552{
c6fb90c8 1553 switch (ARRAY_SIZE (x.array))
40fb9820 1554 {
53467f57
IT		 1555 case 4:
1556 x.array [3] |= y.array [3];
1557 /* Fall through. */
c6fb90c8
L		 1558 case 3:
1559 x.array [2] |= y.array [2];
1a0670f3 1560 /* Fall through. */
c6fb90c8
L		 1561 case 2:
1562 x.array [1] |= y.array [1];
1a0670f3 1563 /* Fall through. */
c6fb90c8
L		 1564 case 1:
1565 x.array [0] |= y.array [0];
40fb9820
L		 1566 break;
1567 default:
1568 abort ();
1569 }
40fb9820
L		 1570 return x;
1571}
1572
309d3373
JB		 1573static INLINE i386_cpu_flags
1574cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1575{
1576 switch (ARRAY_SIZE (x.array))
1577 {
53467f57
IT		 1578 case 4:
1579 x.array [3] &= ~y.array [3];
1580 /* Fall through. */
309d3373
JB		 1581 case 3:
1582 x.array [2] &= ~y.array [2];
1a0670f3 1583 /* Fall through. */
309d3373
JB		 1584 case 2:
1585 x.array [1] &= ~y.array [1];
1a0670f3 1586 /* Fall through. */
309d3373
JB		 1587 case 1:
1588 x.array [0] &= ~y.array [0];
1589 break;
1590 default:
1591 abort ();
1592 }
1593 return x;
1594}
1595
c0f3af97
L		 1596#define CPU_FLAGS_ARCH_MATCH 0x1
1597#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1598#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1599#define CPU_FLAGS_PCLMUL_MATCH 0x8
1600#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1601
a5ff0eb2 1602#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1603 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1604 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1605#define CPU_FLAGS_PERFECT_MATCH \
1606 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1607
1608/* Return CPU flags match bits. */
3629bb00 1609
40fb9820 1610static int
d3ce72d0 1611cpu_flags_match (const insn_template *t)
40fb9820 1612{
c0f3af97
L		 1613 i386_cpu_flags x = t->cpu_flags;
1614 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1615
1616 x.bitfield.cpu64 = 0;
1617 x.bitfield.cpuno64 = 0;
1618
0dfbf9d7 1619 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1620 {
1621 /* This instruction is available on all archs. */
1622 match |= CPU_FLAGS_32BIT_MATCH;
1623 }
3629bb00
L		 1624 else
1625 {
c0f3af97 1626 /* This instruction is available only on some archs. */
3629bb00
L		 1627 i386_cpu_flags cpu = cpu_arch_flags;
1628
3629bb00 1629 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1630 if (!cpu_flags_all_zero (&cpu))
1631 {
a5ff0eb2
L		 1632 if (x.bitfield.cpuavx)
1633 {
ce2f5b3c 1634 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1635 if (cpu.bitfield.cpuavx)
1636 {
1637 /* Check SSE2AVX. */
1638 if (!t->opcode_modifier.sse2avx|| sse2avx)
1639 {
1640 match |= (CPU_FLAGS_ARCH_MATCH
1641 | CPU_FLAGS_AVX_MATCH);
1642 /* Check AES. */
1643 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1644 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1645 /* Check PCLMUL. */
1646 if (!x.bitfield.cpupclmul
1647 || cpu.bitfield.cpupclmul)
1648 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1649 }
1650 }
1651 else
1652 match |= CPU_FLAGS_ARCH_MATCH;
1653 }
73b090a9
L		 1654 else if (x.bitfield.cpuavx512vl)
1655 {
1656 /* Match AVX512VL. */
1657 if (cpu.bitfield.cpuavx512vl)
1658 {
1659 /* Need another match. */
1660 cpu.bitfield.cpuavx512vl = 0;
1661 if (!cpu_flags_all_zero (&cpu))
1662 match |= CPU_FLAGS_32BIT_MATCH;
1663 else
1664 match |= CPU_FLAGS_ARCH_MATCH;
1665 }
1666 else
1667 match |= CPU_FLAGS_ARCH_MATCH;
1668 }
a5ff0eb2 1669 else
c0f3af97
L		 1670 match |= CPU_FLAGS_32BIT_MATCH;
1671 }
3629bb00 1672 }
c0f3af97 1673 return match;
40fb9820
L		 1674}
1675
c6fb90c8
L		 1676static INLINE i386_operand_type
1677operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1678{
c6fb90c8
L		 1679 switch (ARRAY_SIZE (x.array))
1680 {
1681 case 3:
1682 x.array [2] &= y.array [2];
1a0670f3 1683 /* Fall through. */
c6fb90c8
L		 1684 case 2:
1685 x.array [1] &= y.array [1];
1a0670f3 1686 /* Fall through. */
c6fb90c8
L		 1687 case 1:
1688 x.array [0] &= y.array [0];
1689 break;
1690 default:
1691 abort ();
1692 }
1693 return x;
40fb9820
L		 1694}
1695
c6fb90c8
L		 1696static INLINE i386_operand_type
1697operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1698{
c6fb90c8 1699 switch (ARRAY_SIZE (x.array))
40fb9820 1700 {
c6fb90c8
L		 1701 case 3:
1702 x.array [2] |= y.array [2];
1a0670f3 1703 /* Fall through. */
c6fb90c8
L		 1704 case 2:
1705 x.array [1] |= y.array [1];
1a0670f3 1706 /* Fall through. */
c6fb90c8
L		 1707 case 1:
1708 x.array [0] |= y.array [0];
40fb9820
L		 1709 break;
1710 default:
1711 abort ();
1712 }
c6fb90c8
L		 1713 return x;
1714}
40fb9820 1715
c6fb90c8
L		 1716static INLINE i386_operand_type
1717operand_type_xor (i386_operand_type x, i386_operand_type y)
1718{
1719 switch (ARRAY_SIZE (x.array))
1720 {
1721 case 3:
1722 x.array [2] ^= y.array [2];
1a0670f3 1723 /* Fall through. */
c6fb90c8
L		 1724 case 2:
1725 x.array [1] ^= y.array [1];
1a0670f3 1726 /* Fall through. */
c6fb90c8
L		 1727 case 1:
1728 x.array [0] ^= y.array [0];
1729 break;
1730 default:
1731 abort ();
1732 }
40fb9820
L		 1733 return x;
1734}
1735
1736static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1737static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1738static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1739static const i386_operand_type inoutportreg
1740 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1741static const i386_operand_type reg16_inoutportreg
1742 = OPERAND_TYPE_REG16_INOUTPORTREG;
1743static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1744static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1745static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1746static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1747static const i386_operand_type anydisp
1748 = OPERAND_TYPE_ANYDISP;
40fb9820 1749static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1750static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1751static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1752static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1753static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1754static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1755static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1756static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1757static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1758static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1759static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1760static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1761static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1762static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1763
1764enum operand_type
1765{
1766 reg,
40fb9820
L		 1767 imm,
1768 disp,
1769 anymem
1770};
1771
c6fb90c8 1772static INLINE int
40fb9820
L		 1773operand_type_check (i386_operand_type t, enum operand_type c)
1774{
1775 switch (c)
1776 {
1777 case reg:
1778 return (t.bitfield.reg8
1779 || t.bitfield.reg16
1780 || t.bitfield.reg32
1781 || t.bitfield.reg64);
1782
40fb9820
L		 1783 case imm:
1784 return (t.bitfield.imm8
1785 || t.bitfield.imm8s
1786 || t.bitfield.imm16
1787 || t.bitfield.imm32
1788 || t.bitfield.imm32s
1789 || t.bitfield.imm64);
1790
1791 case disp:
1792 return (t.bitfield.disp8
1793 || t.bitfield.disp16
1794 || t.bitfield.disp32
1795 || t.bitfield.disp32s
1796 || t.bitfield.disp64);
1797
1798 case anymem:
1799 return (t.bitfield.disp8
1800 || t.bitfield.disp16
1801 || t.bitfield.disp32
1802 || t.bitfield.disp32s
1803 || t.bitfield.disp64
1804 || t.bitfield.baseindex);
1805
1806 default:
1807 abort ();
1808 }
2cfe26b6
AM		 1809
1810 return 0;
40fb9820
L		 1811}
1812
5c07affc
L		 1813/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1814 operand J for instruction template T. */
1815
1816static INLINE int
d3ce72d0 1817match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1818{
1819 return !((i.types[j].bitfield.byte
1820 && !t->operand_types[j].bitfield.byte)
1821 || (i.types[j].bitfield.word
1822 && !t->operand_types[j].bitfield.word)
1823 || (i.types[j].bitfield.dword
1824 && !t->operand_types[j].bitfield.dword)
1825 || (i.types[j].bitfield.qword
1826 && !t->operand_types[j].bitfield.qword));
1827}
1828
1829/* Return 1 if there is no conflict in any size on operand J for
1830 instruction template T. */
1831
1832static INLINE int
d3ce72d0 1833match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1834{
1835 return (match_reg_size (t, j)
1836 && !((i.types[j].bitfield.unspecified
af508cb9 1837 && !i.broadcast
5c07affc
L		 1838 && !t->operand_types[j].bitfield.unspecified)
1839 || (i.types[j].bitfield.fword
1840 && !t->operand_types[j].bitfield.fword)
1841 || (i.types[j].bitfield.tbyte
1842 && !t->operand_types[j].bitfield.tbyte)
1843 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1844 && !t->operand_types[j].bitfield.xmmword)
1845 || (i.types[j].bitfield.ymmword
43234a1e
L		 1846 && !t->operand_types[j].bitfield.ymmword)
1847 || (i.types[j].bitfield.zmmword
1848 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1849}
1850
1851/* Return 1 if there is no size conflict on any operands for
1852 instruction template T. */
1853
1854static INLINE int
d3ce72d0 1855operand_size_match (const insn_template *t)
5c07affc
L		 1856{
1857 unsigned int j;
1858 int match = 1;
1859
1860 /* Don't check jump instructions. */
1861 if (t->opcode_modifier.jump
1862 || t->opcode_modifier.jumpbyte
1863 || t->opcode_modifier.jumpdword
1864 || t->opcode_modifier.jumpintersegment)
1865 return match;
1866
1867 /* Check memory and accumulator operand size. */
1868 for (j = 0; j < i.operands; j++)
1869 {
1870 if (t->operand_types[j].bitfield.anysize)
1871 continue;
1872
1873 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1874 {
1875 match = 0;
1876 break;
1877 }
1878
1879 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1880 {
1881 match = 0;
1882 break;
1883 }
1884 }
1885
891edac4 1886 if (match)
5c07affc 1887 return match;
891edac4
L		 1888 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1889 {
1890mismatch:
86e026a4 1891 i.error = operand_size_mismatch;
891edac4
L		 1892 return 0;
1893 }
5c07affc
L		 1894
1895 /* Check reverse. */
9c2799c2 1896 gas_assert (i.operands == 2);
5c07affc
L		 1897
1898 match = 1;
1899 for (j = 0; j < 2; j++)
1900 {
1901 if (t->operand_types[j].bitfield.acc
1902 && !match_reg_size (t, j ? 0 : 1))
891edac4 1903 goto mismatch;
5c07affc
L		 1904
1905 if (i.types[j].bitfield.mem
1906 && !match_mem_size (t, j ? 0 : 1))
891edac4 1907 goto mismatch;
5c07affc
L		 1908 }
1909
1910 return match;
1911}
1912
c6fb90c8 1913static INLINE int
40fb9820
L		 1914operand_type_match (i386_operand_type overlap,
1915 i386_operand_type given)
1916{
1917 i386_operand_type temp = overlap;
1918
1919 temp.bitfield.jumpabsolute = 0;
7d5e4556 1920 temp.bitfield.unspecified = 0;
5c07affc
L		 1921 temp.bitfield.byte = 0;
1922 temp.bitfield.word = 0;
1923 temp.bitfield.dword = 0;
1924 temp.bitfield.fword = 0;
1925 temp.bitfield.qword = 0;
1926 temp.bitfield.tbyte = 0;
1927 temp.bitfield.xmmword = 0;
c0f3af97 1928 temp.bitfield.ymmword = 0;
43234a1e 1929 temp.bitfield.zmmword = 0;
0dfbf9d7 1930 if (operand_type_all_zero (&temp))
891edac4 1931 goto mismatch;
40fb9820 1932
891edac4
L		 1933 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1934 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1935 return 1;
1936
1937mismatch:
a65babc9 1938 i.error = operand_type_mismatch;
891edac4 1939 return 0;
40fb9820
L		 1940}
1941
7d5e4556 1942/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1943 unless the expected operand type register overlap is null.
1944 Note that Acc in a template matches every size of reg. */
1945
c6fb90c8 1946static INLINE int
40fb9820
L		 1947operand_type_register_match (i386_operand_type m0,
1948 i386_operand_type g0,
1949 i386_operand_type t0,
1950 i386_operand_type m1,
1951 i386_operand_type g1,
1952 i386_operand_type t1)
1953{
1954 if (!operand_type_check (g0, reg))
1955 return 1;
1956
1957 if (!operand_type_check (g1, reg))
1958 return 1;
1959
1960 if (g0.bitfield.reg8 == g1.bitfield.reg8
1961 && g0.bitfield.reg16 == g1.bitfield.reg16
1962 && g0.bitfield.reg32 == g1.bitfield.reg32
1963 && g0.bitfield.reg64 == g1.bitfield.reg64)
1964 return 1;
1965
1966 if (m0.bitfield.acc)
1967 {
1968 t0.bitfield.reg8 = 1;
1969 t0.bitfield.reg16 = 1;
1970 t0.bitfield.reg32 = 1;
1971 t0.bitfield.reg64 = 1;
1972 }
1973
1974 if (m1.bitfield.acc)
1975 {
1976 t1.bitfield.reg8 = 1;
1977 t1.bitfield.reg16 = 1;
1978 t1.bitfield.reg32 = 1;
1979 t1.bitfield.reg64 = 1;
1980 }
1981
891edac4
L		 1982 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1983 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1984 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1985 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1986 return 1;
1987
a65babc9 1988 i.error = register_type_mismatch;
891edac4
L		 1989
1990 return 0;
40fb9820
L		 1991}
1992
4c692bc7
JB		 1993static INLINE unsigned int
1994register_number (const reg_entry *r)
1995{
1996 unsigned int nr = r->reg_num;
1997
1998 if (r->reg_flags & RegRex)
1999 nr += 8;
2000
200cbe0f
L		 2001 if (r->reg_flags & RegVRex)
2002 nr += 16;
2003
4c692bc7
JB		 2004 return nr;
2005}
2006
252b5132 2007static INLINE unsigned int
40fb9820 2008mode_from_disp_size (i386_operand_type t)
252b5132 2009{
b5014f7a 2010 if (t.bitfield.disp8)
40fb9820
L		 2011 return 1;
2012 else if (t.bitfield.disp16
2013 || t.bitfield.disp32
2014 || t.bitfield.disp32s)
2015 return 2;
2016 else
2017 return 0;
252b5132
RH		 2018}
2019
2020static INLINE int
65879393 2021fits_in_signed_byte (addressT num)
252b5132 2022{
65879393 2023 return num + 0x80 <= 0xff;
47926f60 2024}
252b5132
RH		 2025
2026static INLINE int
65879393 2027fits_in_unsigned_byte (addressT num)
252b5132 2028{
65879393 2029 return num <= 0xff;
47926f60 2030}
252b5132
RH		 2031
2032static INLINE int
65879393 2033fits_in_unsigned_word (addressT num)
252b5132 2034{
65879393 2035 return num <= 0xffff;
47926f60 2036}
252b5132
RH		 2037
2038static INLINE int
65879393 2039fits_in_signed_word (addressT num)
252b5132 2040{
65879393 2041 return num + 0x8000 <= 0xffff;
47926f60 2042}
2a962e6d 2043
3e73aa7c 2044static INLINE int
65879393 2045fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2046{
2047#ifndef BFD64
2048 return 1;
2049#else
65879393 2050 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2051#endif
2052} /* fits_in_signed_long() */
2a962e6d 2053
3e73aa7c 2054static INLINE int
65879393 2055fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2056{
2057#ifndef BFD64
2058 return 1;
2059#else
65879393 2060 return num <= 0xffffffff;
3e73aa7c
JH		 2061#endif
2062} /* fits_in_unsigned_long() */
252b5132 2063
43234a1e 2064static INLINE int
b5014f7a 2065fits_in_disp8 (offsetT num)
43234a1e
L		 2066{
2067 int shift = i.memshift;
2068 unsigned int mask;
2069
2070 if (shift == -1)
2071 abort ();
2072
2073 mask = (1 << shift) - 1;
2074
2075 /* Return 0 if NUM isn't properly aligned. */
2076 if ((num & mask))
2077 return 0;
2078
2079 /* Check if NUM will fit in 8bit after shift. */
2080 return fits_in_signed_byte (num >> shift);
2081}
2082
a683cc34
SP		 2083static INLINE int
2084fits_in_imm4 (offsetT num)
2085{
2086 return (num & 0xf) == num;
2087}
2088
40fb9820 2089static i386_operand_type
e3bb37b5 2090smallest_imm_type (offsetT num)
252b5132 2091{
40fb9820 2092 i386_operand_type t;
7ab9ffdd 2093
0dfbf9d7 2094 operand_type_set (&t, 0);
40fb9820
L		 2095 t.bitfield.imm64 = 1;
2096
2097 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2098 {
2099 /* This code is disabled on the 486 because all the Imm1 forms
2100 in the opcode table are slower on the i486. They're the
2101 versions with the implicitly specified single-position
2102 displacement, which has another syntax if you really want to
2103 use that form. */
40fb9820
L		 2104 t.bitfield.imm1 = 1;
2105 t.bitfield.imm8 = 1;
2106 t.bitfield.imm8s = 1;
2107 t.bitfield.imm16 = 1;
2108 t.bitfield.imm32 = 1;
2109 t.bitfield.imm32s = 1;
2110 }
2111 else if (fits_in_signed_byte (num))
2112 {
2113 t.bitfield.imm8 = 1;
2114 t.bitfield.imm8s = 1;
2115 t.bitfield.imm16 = 1;
2116 t.bitfield.imm32 = 1;
2117 t.bitfield.imm32s = 1;
2118 }
2119 else if (fits_in_unsigned_byte (num))
2120 {
2121 t.bitfield.imm8 = 1;
2122 t.bitfield.imm16 = 1;
2123 t.bitfield.imm32 = 1;
2124 t.bitfield.imm32s = 1;
2125 }
2126 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2127 {
2128 t.bitfield.imm16 = 1;
2129 t.bitfield.imm32 = 1;
2130 t.bitfield.imm32s = 1;
2131 }
2132 else if (fits_in_signed_long (num))
2133 {
2134 t.bitfield.imm32 = 1;
2135 t.bitfield.imm32s = 1;
2136 }
2137 else if (fits_in_unsigned_long (num))
2138 t.bitfield.imm32 = 1;
2139
2140 return t;
47926f60 2141}
252b5132 2142
847f7ad4 2143static offsetT
e3bb37b5 2144offset_in_range (offsetT val, int size)
847f7ad4 2145{
508866be 2146 addressT mask;
ba2adb93 2147
847f7ad4
AM		 2148 switch (size)
2149 {
508866be
L		 2150 case 1: mask = ((addressT) 1 << 8) - 1; break;
2151 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2152 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2153#ifdef BFD64
2154 case 8: mask = ((addressT) 2 << 63) - 1; break;
2155#endif
47926f60 2156 default: abort ();
847f7ad4
AM		 2157 }
2158
9de868bf
L		 2159#ifdef BFD64
2160 /* If BFD64, sign extend val for 32bit address mode. */
2161 if (flag_code != CODE_64BIT
2162 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2163 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2164 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2165#endif
ba2adb93 2166
47926f60 2167 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2168 {
2169 char buf1[40], buf2[40];
2170
2171 sprint_value (buf1, val);
2172 sprint_value (buf2, val & mask);
2173 as_warn (_("%s shortened to %s"), buf1, buf2);
2174 }
2175 return val & mask;
2176}
2177
c32fa91d
L		 2178enum PREFIX_GROUP
2179{
2180 PREFIX_EXIST = 0,
2181 PREFIX_LOCK,
2182 PREFIX_REP,
04ef582a 2183 PREFIX_DS,
c32fa91d
L		 2184 PREFIX_OTHER
2185};
2186
2187/* Returns
2188 a. PREFIX_EXIST if attempting to add a prefix where one from the
2189 same class already exists.
2190 b. PREFIX_LOCK if lock prefix is added.
2191 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2192 d. PREFIX_DS if ds prefix is added.
2193 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2194 */
2195
2196static enum PREFIX_GROUP
e3bb37b5 2197add_prefix (unsigned int prefix)
252b5132 2198{
c32fa91d 2199 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2200 unsigned int q;
252b5132 2201
29b0f896
AM		 2202 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2203 && flag_code == CODE_64BIT)
b1905489 2204 {
161a04f6
L		 2205 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2206 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2207 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2208 ret = PREFIX_EXIST;
b1905489
JB		 2209 q = REX_PREFIX;
2210 }
3e73aa7c 2211 else
b1905489
JB		 2212 {
2213 switch (prefix)
2214 {
2215 default:
2216 abort ();
2217
b1905489 2218 case DS_PREFIX_OPCODE:
04ef582a
L		 2219 ret = PREFIX_DS;
2220 /* Fall through. */
2221 case CS_PREFIX_OPCODE:
b1905489
JB		 2222 case ES_PREFIX_OPCODE:
2223 case FS_PREFIX_OPCODE:
2224 case GS_PREFIX_OPCODE:
2225 case SS_PREFIX_OPCODE:
2226 q = SEG_PREFIX;
2227 break;
2228
2229 case REPNE_PREFIX_OPCODE:
2230 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2231 q = REP_PREFIX;
2232 ret = PREFIX_REP;
2233 break;
2234
b1905489 2235 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2236 q = LOCK_PREFIX;
2237 ret = PREFIX_LOCK;
b1905489
JB		 2238 break;
2239
2240 case FWAIT_OPCODE:
2241 q = WAIT_PREFIX;
2242 break;
2243
2244 case ADDR_PREFIX_OPCODE:
2245 q = ADDR_PREFIX;
2246 break;
2247
2248 case DATA_PREFIX_OPCODE:
2249 q = DATA_PREFIX;
2250 break;
2251 }
2252 if (i.prefix[q] != 0)
c32fa91d 2253 ret = PREFIX_EXIST;
b1905489 2254 }
252b5132 2255
b1905489 2256 if (ret)
252b5132 2257 {
b1905489
JB		 2258 if (!i.prefix[q])
2259 ++i.prefixes;
2260 i.prefix[q] |= prefix;
252b5132 2261 }
b1905489
JB		 2262 else
2263 as_bad (_("same type of prefix used twice"));
252b5132 2264
252b5132
RH		 2265 return ret;
2266}
2267
2268static void
78f12dd3 2269update_code_flag (int value, int check)
eecb386c 2270{
78f12dd3
L		 2271 PRINTF_LIKE ((*as_error));
2272
1e9cc1c2 2273 flag_code = (enum flag_code) value;
40fb9820
L		 2274 if (flag_code == CODE_64BIT)
2275 {
2276 cpu_arch_flags.bitfield.cpu64 = 1;
2277 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2278 }
2279 else
2280 {
2281 cpu_arch_flags.bitfield.cpu64 = 0;
2282 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2283 }
2284 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2285 {
78f12dd3
L		 2286 if (check)
2287 as_error = as_fatal;
2288 else
2289 as_error = as_bad;
2290 (*as_error) (_("64bit mode not supported on `%s'."),
2291 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2292 }
40fb9820 2293 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2294 {
78f12dd3
L		 2295 if (check)
2296 as_error = as_fatal;
2297 else
2298 as_error = as_bad;
2299 (*as_error) (_("32bit mode not supported on `%s'."),
2300 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2301 }
eecb386c
AM		 2302 stackop_size = '\0';
2303}
2304
78f12dd3
L		 2305static void
2306set_code_flag (int value)
2307{
2308 update_code_flag (value, 0);
2309}
2310
eecb386c 2311static void
e3bb37b5 2312set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2313{
1e9cc1c2 2314 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2315 if (flag_code != CODE_16BIT)
2316 abort ();
2317 cpu_arch_flags.bitfield.cpu64 = 0;
2318 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2319 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2320}
2321
2322static void
e3bb37b5 2323set_intel_syntax (int syntax_flag)
252b5132
RH		 2324{
2325 /* Find out if register prefixing is specified. */
2326 int ask_naked_reg = 0;
2327
2328 SKIP_WHITESPACE ();
29b0f896 2329 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2330 {
d02603dc
NC		 2331 char *string;
2332 int e = get_symbol_name (&string);
252b5132 2333
47926f60 2334 if (strcmp (string, "prefix") == 0)
252b5132 2335 ask_naked_reg = 1;
47926f60 2336 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2337 ask_naked_reg = -1;
2338 else
d0b47220 2339 as_bad (_("bad argument to syntax directive."));
d02603dc 2340 (void) restore_line_pointer (e);
252b5132
RH		 2341 }
2342 demand_empty_rest_of_line ();
c3332e24 2343
252b5132
RH		 2344 intel_syntax = syntax_flag;
2345
2346 if (ask_naked_reg == 0)
f86103b7
AM		 2347 allow_naked_reg = (intel_syntax
2348 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2349 else
2350 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2351
ee86248c 2352 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2353
e4a3b5a4 2354 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2355 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2356 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2357}
2358
1efbbeb4
L		 2359static void
2360set_intel_mnemonic (int mnemonic_flag)
2361{
e1d4d893 2362 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2363}
2364
db51cc60
L		 2365static void
2366set_allow_index_reg (int flag)
2367{
2368 allow_index_reg = flag;
2369}
2370
cb19c032 2371static void
7bab8ab5 2372set_check (int what)
cb19c032 2373{
7bab8ab5
JB		 2374 enum check_kind *kind;
2375 const char *str;
2376
2377 if (what)
2378 {
2379 kind = &operand_check;
2380 str = "operand";
2381 }
2382 else
2383 {
2384 kind = &sse_check;
2385 str = "sse";
2386 }
2387
cb19c032
L		 2388 SKIP_WHITESPACE ();
2389
2390 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2391 {
d02603dc
NC		 2392 char *string;
2393 int e = get_symbol_name (&string);
cb19c032
L		 2394
2395 if (strcmp (string, "none") == 0)
7bab8ab5 2396 *kind = check_none;
cb19c032 2397 else if (strcmp (string, "warning") == 0)
7bab8ab5 2398 *kind = check_warning;
cb19c032 2399 else if (strcmp (string, "error") == 0)
7bab8ab5 2400 *kind = check_error;
cb19c032 2401 else
7bab8ab5 2402 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2403 (void) restore_line_pointer (e);
cb19c032
L		 2404 }
2405 else
7bab8ab5 2406 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2407
2408 demand_empty_rest_of_line ();
2409}
2410
8a9036a4
L		 2411static void
2412check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2413 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2414{
2415#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2416 static const char *arch;
2417
2418 /* Intel LIOM is only supported on ELF. */
2419 if (!IS_ELF)
2420 return;
2421
2422 if (!arch)
2423 {
2424 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2425 use default_arch. */
2426 arch = cpu_arch_name;
2427 if (!arch)
2428 arch = default_arch;
2429 }
2430
81486035
L		 2431 /* If we are targeting Intel MCU, we must enable it. */
2432 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2433 || new_flag.bitfield.cpuiamcu)
2434 return;
2435
3632d14b 2436 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2437 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2438 || new_flag.bitfield.cpul1om)
8a9036a4 2439 return;
76ba9986 2440
7a9068fe
L		 2441 /* If we are targeting Intel K1OM, we must enable it. */
2442 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2443 || new_flag.bitfield.cpuk1om)
2444 return;
2445
8a9036a4
L		 2446 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2447#endif
2448}
2449
e413e4e9 2450static void
e3bb37b5 2451set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2452{
47926f60 2453 SKIP_WHITESPACE ();
e413e4e9 2454
29b0f896 2455 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2456 {
d02603dc
NC		 2457 char *string;
2458 int e = get_symbol_name (&string);
91d6fa6a 2459 unsigned int j;
40fb9820 2460 i386_cpu_flags flags;
e413e4e9 2461
91d6fa6a 2462 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2463 {
91d6fa6a 2464 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2465 {
91d6fa6a 2466 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2467
5c6af06e
JB		 2468 if (*string != '.')
2469 {
91d6fa6a 2470 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2471 cpu_sub_arch_name = NULL;
91d6fa6a 2472 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2473 if (flag_code == CODE_64BIT)
2474 {
2475 cpu_arch_flags.bitfield.cpu64 = 1;
2476 cpu_arch_flags.bitfield.cpuno64 = 0;
2477 }
2478 else
2479 {
2480 cpu_arch_flags.bitfield.cpu64 = 0;
2481 cpu_arch_flags.bitfield.cpuno64 = 1;
2482 }
91d6fa6a
NC		 2483 cpu_arch_isa = cpu_arch[j].type;
2484 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2485 if (!cpu_arch_tune_set)
2486 {
2487 cpu_arch_tune = cpu_arch_isa;
2488 cpu_arch_tune_flags = cpu_arch_isa_flags;
2489 }
5c6af06e
JB		 2490 break;
2491 }
40fb9820 2492
293f5f65
L		 2493 flags = cpu_flags_or (cpu_arch_flags,
2494 cpu_arch[j].flags);
81486035 2495
5b64d091 2496 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2497 {
6305a203
L		 2498 if (cpu_sub_arch_name)
2499 {
2500 char *name = cpu_sub_arch_name;
2501 cpu_sub_arch_name = concat (name,
91d6fa6a 2502 cpu_arch[j].name,
1bf57e9f 2503 (const char *) NULL);
6305a203
L		 2504 free (name);
2505 }
2506 else
91d6fa6a 2507 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2508 cpu_arch_flags = flags;
a586129e 2509 cpu_arch_isa_flags = flags;
5c6af06e 2510 }
d02603dc 2511 (void) restore_line_pointer (e);
5c6af06e
JB		 2512 demand_empty_rest_of_line ();
2513 return;
e413e4e9
AM		 2514 }
2515 }
293f5f65
L		 2516
2517 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2518 {
33eaf5de 2519 /* Disable an ISA extension. */
293f5f65
L		 2520 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2521 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2522 {
2523 flags = cpu_flags_and_not (cpu_arch_flags,
2524 cpu_noarch[j].flags);
2525 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2526 {
2527 if (cpu_sub_arch_name)
2528 {
2529 char *name = cpu_sub_arch_name;
2530 cpu_sub_arch_name = concat (name, string,
2531 (const char *) NULL);
2532 free (name);
2533 }
2534 else
2535 cpu_sub_arch_name = xstrdup (string);
2536 cpu_arch_flags = flags;
2537 cpu_arch_isa_flags = flags;
2538 }
2539 (void) restore_line_pointer (e);
2540 demand_empty_rest_of_line ();
2541 return;
2542 }
2543
2544 j = ARRAY_SIZE (cpu_arch);
2545 }
2546
91d6fa6a 2547 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2548 as_bad (_("no such architecture: `%s'"), string);
2549
2550 *input_line_pointer = e;
2551 }
2552 else
2553 as_bad (_("missing cpu architecture"));
2554
fddf5b5b
AM		 2555 no_cond_jump_promotion = 0;
2556 if (*input_line_pointer == ','
29b0f896 2557 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2558 {
d02603dc
NC		 2559 char *string;
2560 char e;
2561
2562 ++input_line_pointer;
2563 e = get_symbol_name (&string);
fddf5b5b
AM		 2564
2565 if (strcmp (string, "nojumps") == 0)
2566 no_cond_jump_promotion = 1;
2567 else if (strcmp (string, "jumps") == 0)
2568 ;
2569 else
2570 as_bad (_("no such architecture modifier: `%s'"), string);
2571
d02603dc 2572 (void) restore_line_pointer (e);
fddf5b5b
AM		 2573 }
2574
e413e4e9
AM		 2575 demand_empty_rest_of_line ();
2576}
2577
8a9036a4
L		 2578enum bfd_architecture
2579i386_arch (void)
2580{
3632d14b 2581 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2582 {
2583 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2584 || flag_code != CODE_64BIT)
2585 as_fatal (_("Intel L1OM is 64bit ELF only"));
2586 return bfd_arch_l1om;
2587 }
7a9068fe
L		 2588 else if (cpu_arch_isa == PROCESSOR_K1OM)
2589 {
2590 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2591 || flag_code != CODE_64BIT)
2592 as_fatal (_("Intel K1OM is 64bit ELF only"));
2593 return bfd_arch_k1om;
2594 }
81486035
L		 2595 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2596 {
2597 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2598 || flag_code == CODE_64BIT)
2599 as_fatal (_("Intel MCU is 32bit ELF only"));
2600 return bfd_arch_iamcu;
2601 }
8a9036a4
L		 2602 else
2603 return bfd_arch_i386;
2604}
2605
b9d79e03 2606unsigned long
7016a5d5 2607i386_mach (void)
b9d79e03 2608{
351f65ca 2609 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2610 {
3632d14b 2611 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2612 {
351f65ca
L		 2613 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2614 || default_arch[6] != '\0')
8a9036a4
L		 2615 as_fatal (_("Intel L1OM is 64bit ELF only"));
2616 return bfd_mach_l1om;
2617 }
7a9068fe
L		 2618 else if (cpu_arch_isa == PROCESSOR_K1OM)
2619 {
2620 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2621 || default_arch[6] != '\0')
2622 as_fatal (_("Intel K1OM is 64bit ELF only"));
2623 return bfd_mach_k1om;
2624 }
351f65ca 2625 else if (default_arch[6] == '\0')
8a9036a4 2626 return bfd_mach_x86_64;
351f65ca
L		 2627 else
2628 return bfd_mach_x64_32;
8a9036a4 2629 }
5197d474
L		 2630 else if (!strcmp (default_arch, "i386")
2631 || !strcmp (default_arch, "iamcu"))
81486035
L		 2632 {
2633 if (cpu_arch_isa == PROCESSOR_IAMCU)
2634 {
2635 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2636 as_fatal (_("Intel MCU is 32bit ELF only"));
2637 return bfd_mach_i386_iamcu;
2638 }
2639 else
2640 return bfd_mach_i386_i386;
2641 }
b9d79e03 2642 else
2b5d6a91 2643 as_fatal (_("unknown architecture"));
b9d79e03 2644}
b9d79e03 2645\f
252b5132 2646void
7016a5d5 2647md_begin (void)
252b5132
RH		 2648{
2649 const char *hash_err;
2650
86fa6981
L		 2651 /* Support pseudo prefixes like {disp32}. */
2652 lex_type ['{'] = LEX_BEGIN_NAME;
2653
47926f60 2654 /* Initialize op_hash hash table. */
252b5132
RH		 2655 op_hash = hash_new ();
2656
2657 {
d3ce72d0 2658 const insn_template *optab;
29b0f896 2659 templates *core_optab;
252b5132 2660
47926f60
KH		 2661 /* Setup for loop. */
2662 optab = i386_optab;
add39d23 2663 core_optab = XNEW (templates);
252b5132
RH		 2664 core_optab->start = optab;
2665
2666 while (1)
2667 {
2668 ++optab;
2669 if (optab->name == NULL
2670 || strcmp (optab->name, (optab - 1)->name) != 0)
2671 {
2672 /* different name --> ship out current template list;
47926f60 2673 add to hash table; & begin anew. */
252b5132
RH		 2674 core_optab->end = optab;
2675 hash_err = hash_insert (op_hash,
2676 (optab - 1)->name,
5a49b8ac 2677 (void *) core_optab);
252b5132
RH		 2678 if (hash_err)
2679 {
b37df7c4 2680 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2681 (optab - 1)->name,
2682 hash_err);
2683 }
2684 if (optab->name == NULL)
2685 break;
add39d23 2686 core_optab = XNEW (templates);
252b5132
RH		 2687 core_optab->start = optab;
2688 }
2689 }
2690 }
2691
47926f60 2692 /* Initialize reg_hash hash table. */
252b5132
RH		 2693 reg_hash = hash_new ();
2694 {
29b0f896 2695 const reg_entry *regtab;
c3fe08fa 2696 unsigned int regtab_size = i386_regtab_size;
252b5132 2697
c3fe08fa 2698 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2699 {
5a49b8ac 2700 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2701 if (hash_err)
b37df7c4 2702 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2703 regtab->reg_name,
2704 hash_err);
252b5132
RH		 2705 }
2706 }
2707
47926f60 2708 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2709 {
29b0f896
AM		 2710 int c;
2711 char *p;
252b5132
RH		 2712
2713 for (c = 0; c < 256; c++)
2714 {
3882b010 2715 if (ISDIGIT (c))
252b5132
RH		 2716 {
2717 digit_chars[c] = c;
2718 mnemonic_chars[c] = c;
2719 register_chars[c] = c;
2720 operand_chars[c] = c;
2721 }
3882b010 2722 else if (ISLOWER (c))
252b5132
RH		 2723 {
2724 mnemonic_chars[c] = c;
2725 register_chars[c] = c;
2726 operand_chars[c] = c;
2727 }
3882b010 2728 else if (ISUPPER (c))
252b5132 2729 {
3882b010 2730 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2731 register_chars[c] = mnemonic_chars[c];
2732 operand_chars[c] = c;
2733 }
43234a1e 2734 else if (c == '{' || c == '}')
86fa6981
L		 2735 {
2736 mnemonic_chars[c] = c;
2737 operand_chars[c] = c;
2738 }
252b5132 2739
3882b010 2740 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2741 identifier_chars[c] = c;
2742 else if (c >= 128)
2743 {
2744 identifier_chars[c] = c;
2745 operand_chars[c] = c;
2746 }
2747 }
2748
2749#ifdef LEX_AT
2750 identifier_chars['@'] = '@';
32137342
NC		 2751#endif
2752#ifdef LEX_QM
2753 identifier_chars['?'] = '?';
2754 operand_chars['?'] = '?';
252b5132 2755#endif
252b5132 2756 digit_chars['-'] = '-';
c0f3af97 2757 mnemonic_chars['_'] = '_';
791fe849 2758 mnemonic_chars['-'] = '-';
0003779b 2759 mnemonic_chars['.'] = '.';
252b5132
RH		 2760 identifier_chars['_'] = '_';
2761 identifier_chars['.'] = '.';
2762
2763 for (p = operand_special_chars; *p != '\0'; p++)
2764 operand_chars[(unsigned char) *p] = *p;
2765 }
2766
a4447b93
RH		 2767 if (flag_code == CODE_64BIT)
2768 {
ca19b261
KT		 2769#if defined (OBJ_COFF) && defined (TE_PE)
2770 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2771 ? 32 : 16);
2772#else
a4447b93 2773 x86_dwarf2_return_column = 16;
ca19b261 2774#endif
61ff971f 2775 x86_cie_data_alignment = -8;
a4447b93
RH		 2776 }
2777 else
2778 {
2779 x86_dwarf2_return_column = 8;
2780 x86_cie_data_alignment = -4;
2781 }
252b5132
RH		 2782}
2783
2784void
e3bb37b5 2785i386_print_statistics (FILE *file)
252b5132
RH		 2786{
2787 hash_print_statistics (file, "i386 opcode", op_hash);
2788 hash_print_statistics (file, "i386 register", reg_hash);
2789}
2790\f
252b5132
RH		 2791#ifdef DEBUG386
2792
ce8a8b2f 2793/* Debugging routines for md_assemble. */
d3ce72d0 2794static void pte (insn_template *);
40fb9820 2795static void pt (i386_operand_type);
e3bb37b5
L		 2796static void pe (expressionS *);
2797static void ps (symbolS *);
252b5132
RH		 2798
2799static void
e3bb37b5 2800pi (char *line, i386_insn *x)
252b5132 2801{
09137c09 2802 unsigned int j;
252b5132
RH		 2803
2804 fprintf (stdout, "%s: template ", line);
2805 pte (&x->tm);
09f131f2
JH		 2806 fprintf (stdout, " address: base %s index %s scale %x\n",
2807 x->base_reg ? x->base_reg->reg_name : "none",
2808 x->index_reg ? x->index_reg->reg_name : "none",
2809 x->log2_scale_factor);
2810 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2811 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2812 fprintf (stdout, " sib: base %x index %x scale %x\n",
2813 x->sib.base, x->sib.index, x->sib.scale);
2814 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2815 (x->rex & REX_W) != 0,
2816 (x->rex & REX_R) != 0,
2817 (x->rex & REX_X) != 0,
2818 (x->rex & REX_B) != 0);
09137c09 2819 for (j = 0; j < x->operands; j++)
252b5132 2820 {
09137c09
SP		 2821 fprintf (stdout, " #%d: ", j + 1);
2822 pt (x->types[j]);
252b5132 2823 fprintf (stdout, "\n");
09137c09
SP		 2824 if (x->types[j].bitfield.reg8
2825 || x->types[j].bitfield.reg16
2826 || x->types[j].bitfield.reg32
2827 || x->types[j].bitfield.reg64
2828 || x->types[j].bitfield.regmmx
2829 || x->types[j].bitfield.regxmm
2830 || x->types[j].bitfield.regymm
43234a1e 2831 || x->types[j].bitfield.regzmm
09137c09
SP		 2832 || x->types[j].bitfield.sreg2
2833 || x->types[j].bitfield.sreg3
2834 || x->types[j].bitfield.control
2835 || x->types[j].bitfield.debug
2836 || x->types[j].bitfield.test)
2837 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2838 if (operand_type_check (x->types[j], imm))
2839 pe (x->op[j].imms);
2840 if (operand_type_check (x->types[j], disp))
2841 pe (x->op[j].disps);
252b5132
RH		 2842 }
2843}
2844
2845static void
d3ce72d0 2846pte (insn_template *t)
252b5132 2847{
09137c09 2848 unsigned int j;
252b5132 2849 fprintf (stdout, " %d operands ", t->operands);
47926f60 2850 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2851 if (t->extension_opcode != None)
2852 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2853 if (t->opcode_modifier.d)
252b5132 2854 fprintf (stdout, "D");
40fb9820 2855 if (t->opcode_modifier.w)
252b5132
RH		 2856 fprintf (stdout, "W");
2857 fprintf (stdout, "\n");
09137c09 2858 for (j = 0; j < t->operands; j++)
252b5132 2859 {
09137c09
SP		 2860 fprintf (stdout, " #%d type ", j + 1);
2861 pt (t->operand_types[j]);
252b5132
RH		 2862 fprintf (stdout, "\n");
2863 }
2864}
2865
2866static void
e3bb37b5 2867pe (expressionS *e)
252b5132 2868{
24eab124 2869 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2870 fprintf (stdout, " add_number %ld (%lx)\n",
2871 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2872 if (e->X_add_symbol)
2873 {
2874 fprintf (stdout, " add_symbol ");
2875 ps (e->X_add_symbol);
2876 fprintf (stdout, "\n");
2877 }
2878 if (e->X_op_symbol)
2879 {
2880 fprintf (stdout, " op_symbol ");
2881 ps (e->X_op_symbol);
2882 fprintf (stdout, "\n");
2883 }
2884}
2885
2886static void
e3bb37b5 2887ps (symbolS *s)
252b5132
RH		 2888{
2889 fprintf (stdout, "%s type %s%s",
2890 S_GET_NAME (s),
2891 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2892 segment_name (S_GET_SEGMENT (s)));
2893}
2894
7b81dfbb 2895static struct type_name
252b5132 2896 {
40fb9820
L		 2897 i386_operand_type mask;
2898 const char *name;
252b5132 2899 }
7b81dfbb 2900const type_names[] =
252b5132 2901{
40fb9820
L		 2902 { OPERAND_TYPE_REG8, "r8" },
2903 { OPERAND_TYPE_REG16, "r16" },
2904 { OPERAND_TYPE_REG32, "r32" },
2905 { OPERAND_TYPE_REG64, "r64" },
2906 { OPERAND_TYPE_IMM8, "i8" },
2907 { OPERAND_TYPE_IMM8, "i8s" },
2908 { OPERAND_TYPE_IMM16, "i16" },
2909 { OPERAND_TYPE_IMM32, "i32" },
2910 { OPERAND_TYPE_IMM32S, "i32s" },
2911 { OPERAND_TYPE_IMM64, "i64" },
2912 { OPERAND_TYPE_IMM1, "i1" },
2913 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2914 { OPERAND_TYPE_DISP8, "d8" },
2915 { OPERAND_TYPE_DISP16, "d16" },
2916 { OPERAND_TYPE_DISP32, "d32" },
2917 { OPERAND_TYPE_DISP32S, "d32s" },
2918 { OPERAND_TYPE_DISP64, "d64" },
2919 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2920 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2921 { OPERAND_TYPE_CONTROL, "control reg" },
2922 { OPERAND_TYPE_TEST, "test reg" },
2923 { OPERAND_TYPE_DEBUG, "debug reg" },
2924 { OPERAND_TYPE_FLOATREG, "FReg" },
2925 { OPERAND_TYPE_FLOATACC, "FAcc" },
2926 { OPERAND_TYPE_SREG2, "SReg2" },
2927 { OPERAND_TYPE_SREG3, "SReg3" },
2928 { OPERAND_TYPE_ACC, "Acc" },
2929 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2930 { OPERAND_TYPE_REGMMX, "rMMX" },
2931 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2932 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2933 { OPERAND_TYPE_REGZMM, "rZMM" },
2934 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2935 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2936};
2937
2938static void
40fb9820 2939pt (i386_operand_type t)
252b5132 2940{
40fb9820 2941 unsigned int j;
c6fb90c8 2942 i386_operand_type a;
252b5132 2943
40fb9820 2944 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2945 {
2946 a = operand_type_and (t, type_names[j].mask);
0349dc08 2947 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2948 fprintf (stdout, "%s, ", type_names[j].name);
2949 }
252b5132
RH		 2950 fflush (stdout);
2951}
2952
2953#endif /* DEBUG386 */
2954\f
252b5132 2955static bfd_reloc_code_real_type
3956db08 2956reloc (unsigned int size,
64e74474
AM		 2957 int pcrel,
2958 int sign,
2959 bfd_reloc_code_real_type other)
252b5132 2960{
47926f60 2961 if (other != NO_RELOC)
3956db08 2962 {
91d6fa6a 2963 reloc_howto_type *rel;
3956db08
JB		 2964
2965 if (size == 8)
2966 switch (other)
2967 {
64e74474
AM		 2968 case BFD_RELOC_X86_64_GOT32:
2969 return BFD_RELOC_X86_64_GOT64;
2970 break;
553d1284
L		 2971 case BFD_RELOC_X86_64_GOTPLT64:
2972 return BFD_RELOC_X86_64_GOTPLT64;
2973 break;
64e74474
AM		 2974 case BFD_RELOC_X86_64_PLTOFF64:
2975 return BFD_RELOC_X86_64_PLTOFF64;
2976 break;
2977 case BFD_RELOC_X86_64_GOTPC32:
2978 other = BFD_RELOC_X86_64_GOTPC64;
2979 break;
2980 case BFD_RELOC_X86_64_GOTPCREL:
2981 other = BFD_RELOC_X86_64_GOTPCREL64;
2982 break;
2983 case BFD_RELOC_X86_64_TPOFF32:
2984 other = BFD_RELOC_X86_64_TPOFF64;
2985 break;
2986 case BFD_RELOC_X86_64_DTPOFF32:
2987 other = BFD_RELOC_X86_64_DTPOFF64;
2988 break;
2989 default:
2990 break;
3956db08 2991 }
e05278af 2992
8ce3d284 2993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2994 if (other == BFD_RELOC_SIZE32)
2995 {
2996 if (size == 8)
1ab668bf 2997 other = BFD_RELOC_SIZE64;
8fd4256d 2998 if (pcrel)
1ab668bf
AM		 2999 {
3000 as_bad (_("there are no pc-relative size relocations"));
3001 return NO_RELOC;
3002 }
8fd4256d 3003 }
8ce3d284 3004#endif
8fd4256d 3005
e05278af 3006 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3007 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3008 sign = -1;
3009
91d6fa6a
NC		 3010 rel = bfd_reloc_type_lookup (stdoutput, other);
3011 if (!rel)
3956db08 3012 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3013 else if (size != bfd_get_reloc_size (rel))
3956db08 3014 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3015 bfd_get_reloc_size (rel),
3956db08 3016 size);
91d6fa6a 3017 else if (pcrel && !rel->pc_relative)
3956db08 3018 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3019 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3020 && !sign)
91d6fa6a 3021 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3022 && sign > 0))
3956db08
JB		 3023 as_bad (_("relocated field and relocation type differ in signedness"));
3024 else
3025 return other;
3026 return NO_RELOC;
3027 }
252b5132
RH		 3028
3029 if (pcrel)
3030 {
3e73aa7c 3031 if (!sign)
3956db08 3032 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3033 switch (size)
3034 {
3035 case 1: return BFD_RELOC_8_PCREL;
3036 case 2: return BFD_RELOC_16_PCREL;
d258b828 3037 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3038 case 8: return BFD_RELOC_64_PCREL;
252b5132 3039 }
3956db08 3040 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3041 }
3042 else
3043 {
3956db08 3044 if (sign > 0)
e5cb08ac 3045 switch (size)
3e73aa7c
JH		 3046 {
3047 case 4: return BFD_RELOC_X86_64_32S;
3048 }
3049 else
3050 switch (size)
3051 {
3052 case 1: return BFD_RELOC_8;
3053 case 2: return BFD_RELOC_16;
3054 case 4: return BFD_RELOC_32;
3055 case 8: return BFD_RELOC_64;
3056 }
3956db08
JB		 3057 as_bad (_("cannot do %s %u byte relocation"),
3058 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3059 }
3060
0cc9e1d3 3061 return NO_RELOC;
252b5132
RH		 3062}
3063
47926f60
KH		 3064/* Here we decide which fixups can be adjusted to make them relative to
3065 the beginning of the section instead of the symbol. Basically we need
3066 to make sure that the dynamic relocations are done correctly, so in
3067 some cases we force the original symbol to be used. */
3068
252b5132 3069int
e3bb37b5 3070tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3071{
6d249963 3072#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3073 if (!IS_ELF)
31312f95
AM		 3074 return 1;
3075
a161fe53
AM		 3076 /* Don't adjust pc-relative references to merge sections in 64-bit
3077 mode. */
3078 if (use_rela_relocations
3079 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3080 && fixP->fx_pcrel)
252b5132 3081 return 0;
31312f95 3082
8d01d9a9
AJ		 3083 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3084 and changed later by validate_fix. */
3085 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3086 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3087 return 0;
3088
8fd4256d
L		 3089 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3090 for size relocations. */
3091 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3092 || fixP->fx_r_type == BFD_RELOC_SIZE64
3093 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3094 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3095 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3096 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3097 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3098 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3099 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3100 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3101 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3102 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3103 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3104 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3105 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3106 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3107 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3108 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3109 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3110 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3111 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3112 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3113 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3114 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3115 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3116 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3117 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3118 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3119 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3120 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3121 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3122 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3123 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3124 return 0;
31312f95 3125#endif
252b5132
RH		 3126 return 1;
3127}
252b5132 3128
b4cac588 3129static int
e3bb37b5 3130intel_float_operand (const char *mnemonic)
252b5132 3131{
9306ca4a
JB		 3132 /* Note that the value returned is meaningful only for opcodes with (memory)
3133 operands, hence the code here is free to improperly handle opcodes that
3134 have no operands (for better performance and smaller code). */
3135
3136 if (mnemonic[0] != 'f')
3137 return 0; /* non-math */
3138
3139 switch (mnemonic[1])
3140 {
3141 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3142 the fs segment override prefix not currently handled because no
3143 call path can make opcodes without operands get here */
3144 case 'i':
3145 return 2 /* integer op */;
3146 case 'l':
3147 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3148 return 3; /* fldcw/fldenv */
3149 break;
3150 case 'n':
3151 if (mnemonic[2] != 'o' /* fnop */)
3152 return 3; /* non-waiting control op */
3153 break;
3154 case 'r':
3155 if (mnemonic[2] == 's')
3156 return 3; /* frstor/frstpm */
3157 break;
3158 case 's':
3159 if (mnemonic[2] == 'a')
3160 return 3; /* fsave */
3161 if (mnemonic[2] == 't')
3162 {
3163 switch (mnemonic[3])
3164 {
3165 case 'c': /* fstcw */
3166 case 'd': /* fstdw */
3167 case 'e': /* fstenv */
3168 case 's': /* fsts[gw] */
3169 return 3;
3170 }
3171 }
3172 break;
3173 case 'x':
3174 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3175 return 0; /* fxsave/fxrstor are not really math ops */
3176 break;
3177 }
252b5132 3178
9306ca4a 3179 return 1;
252b5132
RH		 3180}
3181
c0f3af97
L		 3182/* Build the VEX prefix. */
3183
3184static void
d3ce72d0 3185build_vex_prefix (const insn_template *t)
c0f3af97
L		 3186{
3187 unsigned int register_specifier;
3188 unsigned int implied_prefix;
3189 unsigned int vector_length;
3190
3191 /* Check register specifier. */
3192 if (i.vex.register_specifier)
43234a1e
L		 3193 {
3194 register_specifier =
3195 ~register_number (i.vex.register_specifier) & 0xf;
3196 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3197 }
c0f3af97
L		 3198 else
3199 register_specifier = 0xf;
3200
33eaf5de 3201 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3202 operand. */
86fa6981
L		 3203 if (i.vec_encoding != vex_encoding_vex3
3204 && i.dir_encoding == dir_encoding_default
fa99fab2 3205 && i.operands == i.reg_operands
7f399153 3206 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3207 && i.tm.opcode_modifier.load
fa99fab2
L		 3208 && i.rex == REX_B)
3209 {
3210 unsigned int xchg = i.operands - 1;
3211 union i386_op temp_op;
3212 i386_operand_type temp_type;
3213
3214 temp_type = i.types[xchg];
3215 i.types[xchg] = i.types[0];
3216 i.types[0] = temp_type;
3217 temp_op = i.op[xchg];
3218 i.op[xchg] = i.op[0];
3219 i.op[0] = temp_op;
3220
9c2799c2 3221 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3222
3223 i.rex = REX_R;
3224 xchg = i.rm.regmem;
3225 i.rm.regmem = i.rm.reg;
3226 i.rm.reg = xchg;
3227
3228 /* Use the next insn. */
3229 i.tm = t[1];
3230 }
3231
539f890d
L		 3232 if (i.tm.opcode_modifier.vex == VEXScalar)
3233 vector_length = avxscalar;
3234 else
3235 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3236
3237 switch ((i.tm.base_opcode >> 8) & 0xff)
3238 {
3239 case 0:
3240 implied_prefix = 0;
3241 break;
3242 case DATA_PREFIX_OPCODE:
3243 implied_prefix = 1;
3244 break;
3245 case REPE_PREFIX_OPCODE:
3246 implied_prefix = 2;
3247 break;
3248 case REPNE_PREFIX_OPCODE:
3249 implied_prefix = 3;
3250 break;
3251 default:
3252 abort ();
3253 }
3254
3255 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3256 if (i.vec_encoding != vex_encoding_vex3
3257 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3258 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3259 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3260 {
3261 /* 2-byte VEX prefix. */
3262 unsigned int r;
3263
3264 i.vex.length = 2;
3265 i.vex.bytes[0] = 0xc5;
3266
3267 /* Check the REX.R bit. */
3268 r = (i.rex & REX_R) ? 0 : 1;
3269 i.vex.bytes[1] = (r << 7
3270 | register_specifier << 3
3271 | vector_length << 2
3272 | implied_prefix);
3273 }
3274 else
3275 {
3276 /* 3-byte VEX prefix. */
3277 unsigned int m, w;
3278
f88c9eb0 3279 i.vex.length = 3;
f88c9eb0 3280
7f399153 3281 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3282 {
7f399153
L		 3283 case VEX0F:
3284 m = 0x1;
80de6e00 3285 i.vex.bytes[0] = 0xc4;
7f399153
L		 3286 break;
3287 case VEX0F38:
3288 m = 0x2;
80de6e00 3289 i.vex.bytes[0] = 0xc4;
7f399153
L		 3290 break;
3291 case VEX0F3A:
3292 m = 0x3;
80de6e00 3293 i.vex.bytes[0] = 0xc4;
7f399153
L		 3294 break;
3295 case XOP08:
5dd85c99
SP		 3296 m = 0x8;
3297 i.vex.bytes[0] = 0x8f;
7f399153
L		 3298 break;
3299 case XOP09:
f88c9eb0
SP		 3300 m = 0x9;
3301 i.vex.bytes[0] = 0x8f;
7f399153
L		 3302 break;
3303 case XOP0A:
f88c9eb0
SP		 3304 m = 0xa;
3305 i.vex.bytes[0] = 0x8f;
7f399153
L		 3306 break;
3307 default:
3308 abort ();
f88c9eb0 3309 }
c0f3af97 3310
c0f3af97
L		 3311 /* The high 3 bits of the second VEX byte are 1's compliment
3312 of RXB bits from REX. */
3313 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3314
3315 /* Check the REX.W bit. */
3316 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3317 if (i.tm.opcode_modifier.vexw == VEXW1)
3318 w = 1;
c0f3af97
L		 3319
3320 i.vex.bytes[2] = (w << 7
3321 | register_specifier << 3
3322 | vector_length << 2
3323 | implied_prefix);
3324 }
3325}
3326
43234a1e
L		 3327/* Build the EVEX prefix. */
3328
3329static void
3330build_evex_prefix (void)
3331{
3332 unsigned int register_specifier;
3333 unsigned int implied_prefix;
3334 unsigned int m, w;
3335 rex_byte vrex_used = 0;
3336
3337 /* Check register specifier. */
3338 if (i.vex.register_specifier)
3339 {
3340 gas_assert ((i.vrex & REX_X) == 0);
3341
3342 register_specifier = i.vex.register_specifier->reg_num;
3343 if ((i.vex.register_specifier->reg_flags & RegRex))
3344 register_specifier += 8;
3345 /* The upper 16 registers are encoded in the fourth byte of the
3346 EVEX prefix. */
3347 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3348 i.vex.bytes[3] = 0x8;
3349 register_specifier = ~register_specifier & 0xf;
3350 }
3351 else
3352 {
3353 register_specifier = 0xf;
3354
3355 /* Encode upper 16 vector index register in the fourth byte of
3356 the EVEX prefix. */
3357 if (!(i.vrex & REX_X))
3358 i.vex.bytes[3] = 0x8;
3359 else
3360 vrex_used |= REX_X;
3361 }
3362
3363 switch ((i.tm.base_opcode >> 8) & 0xff)
3364 {
3365 case 0:
3366 implied_prefix = 0;
3367 break;
3368 case DATA_PREFIX_OPCODE:
3369 implied_prefix = 1;
3370 break;
3371 case REPE_PREFIX_OPCODE:
3372 implied_prefix = 2;
3373 break;
3374 case REPNE_PREFIX_OPCODE:
3375 implied_prefix = 3;
3376 break;
3377 default:
3378 abort ();
3379 }
3380
3381 /* 4 byte EVEX prefix. */
3382 i.vex.length = 4;
3383 i.vex.bytes[0] = 0x62;
3384
3385 /* mmmm bits. */
3386 switch (i.tm.opcode_modifier.vexopcode)
3387 {
3388 case VEX0F:
3389 m = 1;
3390 break;
3391 case VEX0F38:
3392 m = 2;
3393 break;
3394 case VEX0F3A:
3395 m = 3;
3396 break;
3397 default:
3398 abort ();
3399 break;
3400 }
3401
3402 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3403 bits from REX. */
3404 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3405
3406 /* The fifth bit of the second EVEX byte is 1's compliment of the
3407 REX_R bit in VREX. */
3408 if (!(i.vrex & REX_R))
3409 i.vex.bytes[1] |= 0x10;
3410 else
3411 vrex_used |= REX_R;
3412
3413 if ((i.reg_operands + i.imm_operands) == i.operands)
3414 {
3415 /* When all operands are registers, the REX_X bit in REX is not
3416 used. We reuse it to encode the upper 16 registers, which is
3417 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3418 as 1's compliment. */
3419 if ((i.vrex & REX_B))
3420 {
3421 vrex_used |= REX_B;
3422 i.vex.bytes[1] &= ~0x40;
3423 }
3424 }
3425
3426 /* EVEX instructions shouldn't need the REX prefix. */
3427 i.vrex &= ~vrex_used;
3428 gas_assert (i.vrex == 0);
3429
3430 /* Check the REX.W bit. */
3431 w = (i.rex & REX_W) ? 1 : 0;
3432 if (i.tm.opcode_modifier.vexw)
3433 {
3434 if (i.tm.opcode_modifier.vexw == VEXW1)
3435 w = 1;
3436 }
3437 /* If w is not set it means we are dealing with WIG instruction. */
3438 else if (!w)
3439 {
3440 if (evexwig == evexw1)
3441 w = 1;
3442 }
3443
3444 /* Encode the U bit. */
3445 implied_prefix |= 0x4;
3446
3447 /* The third byte of the EVEX prefix. */
3448 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3449
3450 /* The fourth byte of the EVEX prefix. */
3451 /* The zeroing-masking bit. */
3452 if (i.mask && i.mask->zeroing)
3453 i.vex.bytes[3] |= 0x80;
3454
3455 /* Don't always set the broadcast bit if there is no RC. */
3456 if (!i.rounding)
3457 {
3458 /* Encode the vector length. */
3459 unsigned int vec_length;
3460
3461 switch (i.tm.opcode_modifier.evex)
3462 {
3463 case EVEXLIG: /* LL' is ignored */
3464 vec_length = evexlig << 5;
3465 break;
3466 case EVEX128:
3467 vec_length = 0 << 5;
3468 break;
3469 case EVEX256:
3470 vec_length = 1 << 5;
3471 break;
3472 case EVEX512:
3473 vec_length = 2 << 5;
3474 break;
3475 default:
3476 abort ();
3477 break;
3478 }
3479 i.vex.bytes[3] |= vec_length;
3480 /* Encode the broadcast bit. */
3481 if (i.broadcast)
3482 i.vex.bytes[3] |= 0x10;
3483 }
3484 else
3485 {
3486 if (i.rounding->type != saeonly)
3487 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3488 else
d3d3c6db 3489 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3490 }
3491
3492 if (i.mask && i.mask->mask)
3493 i.vex.bytes[3] |= i.mask->mask->reg_num;
3494}
3495
65da13b5
L		 3496static void
3497process_immext (void)
3498{
3499 expressionS *exp;
3500
4c692bc7
JB		 3501 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3502 && i.operands > 0)
65da13b5 3503 {
4c692bc7
JB		 3504 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3505 with an opcode suffix which is coded in the same place as an
3506 8-bit immediate field would be.
3507 Here we check those operands and remove them afterwards. */
65da13b5
L		 3508 unsigned int x;
3509
3510 for (x = 0; x < i.operands; x++)
4c692bc7 3511 if (register_number (i.op[x].regs) != x)
65da13b5 3512 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3513 register_prefix, i.op[x].regs->reg_name, x + 1,
3514 i.tm.name);
3515
3516 i.operands = 0;
65da13b5
L		 3517 }
3518
9916071f
AP		 3519 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3520 {
3521 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3522 suffix which is coded in the same place as an 8-bit immediate
3523 field would be.
3524 Here we check those operands and remove them afterwards. */
3525 unsigned int x;
3526
3527 if (i.operands != 3)
3528 abort();
3529
3530 for (x = 0; x < 2; x++)
3531 if (register_number (i.op[x].regs) != x)
3532 goto bad_register_operand;
3533
3534 /* Check for third operand for mwaitx/monitorx insn. */
3535 if (register_number (i.op[x].regs)
3536 != (x + (i.tm.extension_opcode == 0xfb)))
3537 {
3538bad_register_operand:
3539 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3540 register_prefix, i.op[x].regs->reg_name, x+1,
3541 i.tm.name);
3542 }
3543
3544 i.operands = 0;
3545 }
3546
c0f3af97 3547 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3548 which is coded in the same place as an 8-bit immediate field
3549 would be. Here we fake an 8-bit immediate operand from the
3550 opcode suffix stored in tm.extension_opcode.
3551
c1e679ec 3552 AVX instructions also use this encoding, for some of
c0f3af97 3553 3 argument instructions. */
65da13b5 3554
43234a1e 3555 gas_assert (i.imm_operands <= 1
7ab9ffdd 3556 && (i.operands <= 2
43234a1e
L		 3557 || ((i.tm.opcode_modifier.vex
3558 || i.tm.opcode_modifier.evex)
7ab9ffdd 3559 && i.operands <= 4)));
65da13b5
L		 3560
3561 exp = &im_expressions[i.imm_operands++];
3562 i.op[i.operands].imms = exp;
3563 i.types[i.operands] = imm8;
3564 i.operands++;
3565 exp->X_op = O_constant;
3566 exp->X_add_number = i.tm.extension_opcode;
3567 i.tm.extension_opcode = None;
3568}
3569
42164a71
L		 3570
3571static int
3572check_hle (void)
3573{
3574 switch (i.tm.opcode_modifier.hleprefixok)
3575 {
3576 default:
3577 abort ();
82c2def5 3578 case HLEPrefixNone:
165de32a
L		 3579 as_bad (_("invalid instruction `%s' after `%s'"),
3580 i.tm.name, i.hle_prefix);
42164a71 3581 return 0;
82c2def5 3582 case HLEPrefixLock:
42164a71
L		 3583 if (i.prefix[LOCK_PREFIX])
3584 return 1;
165de32a 3585 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3586 return 0;
82c2def5 3587 case HLEPrefixAny:
42164a71 3588 return 1;
82c2def5 3589 case HLEPrefixRelease:
42164a71
L		 3590 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3591 {
3592 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3593 i.tm.name);
3594 return 0;
3595 }
3596 if (i.mem_operands == 0
3597 || !operand_type_check (i.types[i.operands - 1], anymem))
3598 {
3599 as_bad (_("memory destination needed for instruction `%s'"
3600 " after `xrelease'"), i.tm.name);
3601 return 0;
3602 }
3603 return 1;
3604 }
3605}
3606
252b5132
RH		 3607/* This is the guts of the machine-dependent assembler. LINE points to a
3608 machine dependent instruction. This function is supposed to emit
3609 the frags/bytes it assembles to. */
3610
3611void
65da13b5 3612md_assemble (char *line)
252b5132 3613{
40fb9820 3614 unsigned int j;
83b16ac6 3615 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3616 const insn_template *t;
252b5132 3617
47926f60 3618 /* Initialize globals. */
252b5132
RH		 3619 memset (&i, '\0', sizeof (i));
3620 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3621 i.reloc[j] = NO_RELOC;
252b5132
RH		 3622 memset (disp_expressions, '\0', sizeof (disp_expressions));
3623 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3624 save_stack_p = save_stack;
252b5132
RH		 3625
3626 /* First parse an instruction mnemonic & call i386_operand for the operands.
3627 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3628 start of a (possibly prefixed) mnemonic. */
252b5132 3629
29b0f896
AM		 3630 line = parse_insn (line, mnemonic);
3631 if (line == NULL)
3632 return;
83b16ac6 3633 mnem_suffix = i.suffix;
252b5132 3634
29b0f896 3635 line = parse_operands (line, mnemonic);
ee86248c 3636 this_operand = -1;
8325cc63
JB		 3637 xfree (i.memop1_string);
3638 i.memop1_string = NULL;
29b0f896
AM		 3639 if (line == NULL)
3640 return;
252b5132 3641
29b0f896
AM		 3642 /* Now we've parsed the mnemonic into a set of templates, and have the
3643 operands at hand. */
3644
3645 /* All intel opcodes have reversed operands except for "bound" and
3646 "enter". We also don't reverse intersegment "jmp" and "call"
3647 instructions with 2 immediate operands so that the immediate segment
050dfa73 3648 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3649 if (intel_syntax
3650 && i.operands > 1
29b0f896 3651 && (strcmp (mnemonic, "bound") != 0)
30123838 3652 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3653 && !(operand_type_check (i.types[0], imm)
3654 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3655 swap_operands ();
3656
ec56d5c0
JB		 3657 /* The order of the immediates should be reversed
3658 for 2 immediates extrq and insertq instructions */
3659 if (i.imm_operands == 2
3660 && (strcmp (mnemonic, "extrq") == 0
3661 || strcmp (mnemonic, "insertq") == 0))
3662 swap_2_operands (0, 1);
3663
29b0f896
AM		 3664 if (i.imm_operands)
3665 optimize_imm ();
3666
b300c311
L		 3667 /* Don't optimize displacement for movabs since it only takes 64bit
3668 displacement. */
3669 if (i.disp_operands
a501d77e 3670 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3671 && (flag_code != CODE_64BIT
3672 || strcmp (mnemonic, "movabs") != 0))
3673 optimize_disp ();
29b0f896
AM		 3674
3675 /* Next, we find a template that matches the given insn,
3676 making sure the overlap of the given operands types is consistent
3677 with the template operand types. */
252b5132 3678
83b16ac6 3679 if (!(t = match_template (mnem_suffix)))
29b0f896 3680 return;
252b5132 3681
7bab8ab5 3682 if (sse_check != check_none
81f8a913 3683 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3684 && (i.tm.cpu_flags.bitfield.cpusse
3685 || i.tm.cpu_flags.bitfield.cpusse2
3686 || i.tm.cpu_flags.bitfield.cpusse3
3687 || i.tm.cpu_flags.bitfield.cpussse3
3688 || i.tm.cpu_flags.bitfield.cpusse4_1
3689 || i.tm.cpu_flags.bitfield.cpusse4_2))
3690 {
7bab8ab5 3691 (sse_check == check_warning
daf50ae7
L		 3692 ? as_warn
3693 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3694 }
3695
321fd21e
L		 3696 /* Zap movzx and movsx suffix. The suffix has been set from
3697 "word ptr" or "byte ptr" on the source operand in Intel syntax
3698 or extracted from mnemonic in AT&T syntax. But we'll use
3699 the destination register to choose the suffix for encoding. */
3700 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3701 {
321fd21e
L		 3702 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3703 there is no suffix, the default will be byte extension. */
3704 if (i.reg_operands != 2
3705 && !i.suffix
7ab9ffdd 3706 && intel_syntax)
321fd21e
L		 3707 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3708
3709 i.suffix = 0;
cd61ebfe 3710 }
24eab124 3711
40fb9820 3712 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3713 if (!add_prefix (FWAIT_OPCODE))
3714 return;
252b5132 3715
d5de92cf
L		 3716 /* Check if REP prefix is OK. */
3717 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3718 {
3719 as_bad (_("invalid instruction `%s' after `%s'"),
3720 i.tm.name, i.rep_prefix);
3721 return;
3722 }
3723
c1ba0266
L		 3724 /* Check for lock without a lockable instruction. Destination operand
3725 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3726 if (i.prefix[LOCK_PREFIX]
3727 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3728 || i.mem_operands == 0
3729 || (i.tm.base_opcode != 0x86
3730 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3731 {
3732 as_bad (_("expecting lockable instruction after `lock'"));
3733 return;
3734 }
3735
42164a71 3736 /* Check if HLE prefix is OK. */
165de32a 3737 if (i.hle_prefix && !check_hle ())
42164a71
L		 3738 return;
3739
7e8b059b
L		 3740 /* Check BND prefix. */
3741 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3742 as_bad (_("expecting valid branch instruction after `bnd'"));
3743
04ef582a 3744 /* Check NOTRACK prefix. */
9fef80d6
L		 3745 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3746 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3747
327e8c42
JB		 3748 if (i.tm.cpu_flags.bitfield.cpumpx)
3749 {
3750 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3751 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3752 else if (flag_code != CODE_16BIT
3753 ? i.prefix[ADDR_PREFIX]
3754 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3755 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3756 }
7e8b059b
L		 3757
3758 /* Insert BND prefix. */
3759 if (add_bnd_prefix
3760 && i.tm.opcode_modifier.bndprefixok
3761 && !i.prefix[BND_PREFIX])
3762 add_prefix (BND_PREFIX_OPCODE);
3763
29b0f896 3764 /* Check string instruction segment overrides. */
40fb9820 3765 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3766 {
3767 if (!check_string ())
5dd0794d 3768 return;
fc0763e6 3769 i.disp_operands = 0;
29b0f896 3770 }
5dd0794d 3771
29b0f896
AM		 3772 if (!process_suffix ())
3773 return;
e413e4e9 3774
bc0844ae
L		 3775 /* Update operand types. */
3776 for (j = 0; j < i.operands; j++)
3777 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3778
29b0f896
AM		 3779 /* Make still unresolved immediate matches conform to size of immediate
3780 given in i.suffix. */
3781 if (!finalize_imm ())
3782 return;
252b5132 3783
40fb9820 3784 if (i.types[0].bitfield.imm1)
29b0f896 3785 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3786
9afe6eb8
L		 3787 /* We only need to check those implicit registers for instructions
3788 with 3 operands or less. */
3789 if (i.operands <= 3)
3790 for (j = 0; j < i.operands; j++)
3791 if (i.types[j].bitfield.inoutportreg
3792 || i.types[j].bitfield.shiftcount
3793 || i.types[j].bitfield.acc
3794 || i.types[j].bitfield.floatacc)
3795 i.reg_operands--;
40fb9820 3796
c0f3af97
L		 3797 /* ImmExt should be processed after SSE2AVX. */
3798 if (!i.tm.opcode_modifier.sse2avx
3799 && i.tm.opcode_modifier.immext)
65da13b5 3800 process_immext ();
252b5132 3801
29b0f896
AM		 3802 /* For insns with operands there are more diddles to do to the opcode. */
3803 if (i.operands)
3804 {
3805 if (!process_operands ())
3806 return;
3807 }
40fb9820 3808 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3809 {
3810 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3811 as_warn (_("translating to `%sp'"), i.tm.name);
3812 }
252b5132 3813
9e5e5283
L		 3814 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3815 {
3816 if (flag_code == CODE_16BIT)
3817 {
3818 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3819 i.tm.name);
3820 return;
3821 }
c0f3af97 3822
9e5e5283
L		 3823 if (i.tm.opcode_modifier.vex)
3824 build_vex_prefix (t);
3825 else
3826 build_evex_prefix ();
3827 }
43234a1e 3828
5dd85c99
SP		 3829 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3830 instructions may define INT_OPCODE as well, so avoid this corner
3831 case for those instructions that use MODRM. */
3832 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3833 && !i.tm.opcode_modifier.modrm
3834 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3835 {
3836 i.tm.base_opcode = INT3_OPCODE;
3837 i.imm_operands = 0;
3838 }
252b5132 3839
40fb9820
L		 3840 if ((i.tm.opcode_modifier.jump
3841 || i.tm.opcode_modifier.jumpbyte
3842 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3843 && i.op[0].disps->X_op == O_constant)
3844 {
3845 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3846 the absolute address given by the constant. Since ix86 jumps and
3847 calls are pc relative, we need to generate a reloc. */
3848 i.op[0].disps->X_add_symbol = &abs_symbol;
3849 i.op[0].disps->X_op = O_symbol;
3850 }
252b5132 3851
40fb9820 3852 if (i.tm.opcode_modifier.rex64)
161a04f6 3853 i.rex |= REX_W;
252b5132 3854
29b0f896
AM		 3855 /* For 8 bit registers we need an empty rex prefix. Also if the
3856 instruction already has a prefix, we need to convert old
3857 registers to new ones. */
773f551c 3858
40fb9820 3859 if ((i.types[0].bitfield.reg8
29b0f896 3860 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3861 || (i.types[1].bitfield.reg8
29b0f896 3862 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3863 || ((i.types[0].bitfield.reg8
3864 || i.types[1].bitfield.reg8)
29b0f896
AM		 3865 && i.rex != 0))
3866 {
3867 int x;
726c5dcd 3868
29b0f896
AM		 3869 i.rex |= REX_OPCODE;
3870 for (x = 0; x < 2; x++)
3871 {
3872 /* Look for 8 bit operand that uses old registers. */
40fb9820 3873 if (i.types[x].bitfield.reg8
29b0f896 3874 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3875 {
29b0f896
AM		 3876 /* In case it is "hi" register, give up. */
3877 if (i.op[x].regs->reg_num > 3)
a540244d 3878 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3879 "instruction requiring REX prefix."),
a540244d 3880 register_prefix, i.op[x].regs->reg_name);
773f551c 3881
29b0f896
AM		 3882 /* Otherwise it is equivalent to the extended register.
3883 Since the encoding doesn't change this is merely
3884 cosmetic cleanup for debug output. */
3885
3886 i.op[x].regs = i.op[x].regs + 8;
773f551c 3887 }
29b0f896
AM		 3888 }
3889 }
773f551c 3890
7ab9ffdd 3891 if (i.rex != 0)
29b0f896
AM		 3892 add_prefix (REX_OPCODE | i.rex);
3893
3894 /* We are ready to output the insn. */
3895 output_insn ();
3896}
3897
3898static char *
e3bb37b5 3899parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3900{
3901 char *l = line;
3902 char *token_start = l;
3903 char *mnem_p;
5c6af06e 3904 int supported;
d3ce72d0 3905 const insn_template *t;
b6169b20 3906 char *dot_p = NULL;
29b0f896 3907
29b0f896
AM		 3908 while (1)
3909 {
3910 mnem_p = mnemonic;
3911 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3912 {
b6169b20
L		 3913 if (*mnem_p == '.')
3914 dot_p = mnem_p;
29b0f896
AM		 3915 mnem_p++;
3916 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3917 {
29b0f896
AM		 3918 as_bad (_("no such instruction: `%s'"), token_start);
3919 return NULL;
3920 }
3921 l++;
3922 }
3923 if (!is_space_char (*l)
3924 && *l != END_OF_INSN
e44823cf
JB		 3925 && (intel_syntax
3926 || (*l != PREFIX_SEPARATOR
3927 && *l != ',')))
29b0f896
AM		 3928 {
3929 as_bad (_("invalid character %s in mnemonic"),
3930 output_invalid (*l));
3931 return NULL;
3932 }
3933 if (token_start == l)
3934 {
e44823cf 3935 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3936 as_bad (_("expecting prefix; got nothing"));
3937 else
3938 as_bad (_("expecting mnemonic; got nothing"));
3939 return NULL;
3940 }
45288df1 3941
29b0f896 3942 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3943 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3944
29b0f896
AM		 3945 if (*l != END_OF_INSN
3946 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3947 && current_templates
40fb9820 3948 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3949 {
c6fb90c8 3950 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3951 {
3952 as_bad ((flag_code != CODE_64BIT
3953 ? _("`%s' is only supported in 64-bit mode")
3954 : _("`%s' is not supported in 64-bit mode")),
3955 current_templates->start->name);
3956 return NULL;
3957 }
29b0f896
AM		 3958 /* If we are in 16-bit mode, do not allow addr16 or data16.
3959 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3960 if ((current_templates->start->opcode_modifier.size16
3961 || current_templates->start->opcode_modifier.size32)
29b0f896 3962 && flag_code != CODE_64BIT
40fb9820 3963 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3964 ^ (flag_code == CODE_16BIT)))
3965 {
3966 as_bad (_("redundant %s prefix"),
3967 current_templates->start->name);
3968 return NULL;
45288df1 3969 }
86fa6981 3970 if (current_templates->start->opcode_length == 0)
29b0f896 3971 {
86fa6981
L		 3972 /* Handle pseudo prefixes. */
3973 switch (current_templates->start->base_opcode)
3974 {
3975 case 0x0:
3976 /* {disp8} */
3977 i.disp_encoding = disp_encoding_8bit;
3978 break;
3979 case 0x1:
3980 /* {disp32} */
3981 i.disp_encoding = disp_encoding_32bit;
3982 break;
3983 case 0x2:
3984 /* {load} */
3985 i.dir_encoding = dir_encoding_load;
3986 break;
3987 case 0x3:
3988 /* {store} */
3989 i.dir_encoding = dir_encoding_store;
3990 break;
3991 case 0x4:
3992 /* {vex2} */
3993 i.vec_encoding = vex_encoding_vex2;
3994 break;
3995 case 0x5:
3996 /* {vex3} */
3997 i.vec_encoding = vex_encoding_vex3;
3998 break;
3999 case 0x6:
4000 /* {evex} */
4001 i.vec_encoding = vex_encoding_evex;
4002 break;
4003 default:
4004 abort ();
4005 }
4006 }
4007 else
4008 {
4009 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4010 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4011 {
4e9ac44a
L		 4012 case PREFIX_EXIST:
4013 return NULL;
4014 case PREFIX_DS:
4015 if (current_templates->start->cpu_flags.bitfield.cpucet)
4016 i.notrack_prefix = current_templates->start->name;
4017 break;
4018 case PREFIX_REP:
4019 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4020 i.hle_prefix = current_templates->start->name;
4021 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4022 i.bnd_prefix = current_templates->start->name;
4023 else
4024 i.rep_prefix = current_templates->start->name;
4025 break;
4026 default:
4027 break;
86fa6981 4028 }
29b0f896
AM		 4029 }
4030 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4031 token_start = ++l;
4032 }
4033 else
4034 break;
4035 }
45288df1 4036
30a55f88 4037 if (!current_templates)
b6169b20 4038 {
f8a5c266
L		 4039 /* Check if we should swap operand or force 32bit displacement in
4040 encoding. */
30a55f88 4041 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4042 i.dir_encoding = dir_encoding_store;
8d63c93e 4043 else if (mnem_p - 3 == dot_p
a501d77e
L		 4044 && dot_p[1] == 'd'
4045 && dot_p[2] == '8')
4046 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4047 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4048 && dot_p[1] == 'd'
4049 && dot_p[2] == '3'
4050 && dot_p[3] == '2')
a501d77e 4051 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4052 else
4053 goto check_suffix;
4054 mnem_p = dot_p;
4055 *dot_p = '\0';
d3ce72d0 4056 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4057 }
4058
29b0f896
AM		 4059 if (!current_templates)
4060 {
b6169b20 4061check_suffix:
29b0f896
AM		 4062 /* See if we can get a match by trimming off a suffix. */
4063 switch (mnem_p[-1])
4064 {
4065 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4066 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4067 i.suffix = SHORT_MNEM_SUFFIX;
4068 else
1a0670f3 4069 /* Fall through. */
29b0f896
AM		 4070 case BYTE_MNEM_SUFFIX:
4071 case QWORD_MNEM_SUFFIX:
4072 i.suffix = mnem_p[-1];
4073 mnem_p[-1] = '\0';
d3ce72d0
NC		 4074 current_templates = (const templates *) hash_find (op_hash,
4075 mnemonic);
29b0f896
AM		 4076 break;
4077 case SHORT_MNEM_SUFFIX:
4078 case LONG_MNEM_SUFFIX:
4079 if (!intel_syntax)
4080 {
4081 i.suffix = mnem_p[-1];
4082 mnem_p[-1] = '\0';
d3ce72d0
NC		 4083 current_templates = (const templates *) hash_find (op_hash,
4084 mnemonic);
29b0f896
AM		 4085 }
4086 break;
252b5132 4087
29b0f896
AM		 4088 /* Intel Syntax. */
4089 case 'd':
4090 if (intel_syntax)
4091 {
9306ca4a 4092 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4093 i.suffix = SHORT_MNEM_SUFFIX;
4094 else
4095 i.suffix = LONG_MNEM_SUFFIX;
4096 mnem_p[-1] = '\0';
d3ce72d0
NC		 4097 current_templates = (const templates *) hash_find (op_hash,
4098 mnemonic);
29b0f896
AM		 4099 }
4100 break;
4101 }
4102 if (!current_templates)
4103 {
4104 as_bad (_("no such instruction: `%s'"), token_start);
4105 return NULL;
4106 }
4107 }
252b5132 4108
40fb9820
L		 4109 if (current_templates->start->opcode_modifier.jump
4110 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4111 {
4112 /* Check for a branch hint. We allow ",pt" and ",pn" for
4113 predict taken and predict not taken respectively.
4114 I'm not sure that branch hints actually do anything on loop
4115 and jcxz insns (JumpByte) for current Pentium4 chips. They
4116 may work in the future and it doesn't hurt to accept them
4117 now. */
4118 if (l[0] == ',' && l[1] == 'p')
4119 {
4120 if (l[2] == 't')
4121 {
4122 if (!add_prefix (DS_PREFIX_OPCODE))
4123 return NULL;
4124 l += 3;
4125 }
4126 else if (l[2] == 'n')
4127 {
4128 if (!add_prefix (CS_PREFIX_OPCODE))
4129 return NULL;
4130 l += 3;
4131 }
4132 }
4133 }
4134 /* Any other comma loses. */
4135 if (*l == ',')
4136 {
4137 as_bad (_("invalid character %s in mnemonic"),
4138 output_invalid (*l));
4139 return NULL;
4140 }
252b5132 4141
29b0f896 4142 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4143 supported = 0;
4144 for (t = current_templates->start; t < current_templates->end; ++t)
4145 {
c0f3af97
L		 4146 supported |= cpu_flags_match (t);
4147 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4148 goto skip;
5c6af06e 4149 }
3629bb00 4150
c0f3af97 4151 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4152 {
4153 as_bad (flag_code == CODE_64BIT
4154 ? _("`%s' is not supported in 64-bit mode")
4155 : _("`%s' is only supported in 64-bit mode"),
4156 current_templates->start->name);
4157 return NULL;
4158 }
c0f3af97 4159 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4160 {
3629bb00 4161 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4162 current_templates->start->name,
41aacd83 4163 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4164 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4165 return NULL;
29b0f896 4166 }
3629bb00
L		 4167
4168skip:
4169 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4170 && (flag_code != CODE_16BIT))
29b0f896
AM		 4171 {
4172 as_warn (_("use .code16 to ensure correct addressing mode"));
4173 }
252b5132 4174
29b0f896
AM		 4175 return l;
4176}
252b5132 4177
29b0f896 4178static char *
e3bb37b5 4179parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4180{
4181 char *token_start;
3138f287 4182
29b0f896
AM		 4183 /* 1 if operand is pending after ','. */
4184 unsigned int expecting_operand = 0;
252b5132 4185
29b0f896
AM		 4186 /* Non-zero if operand parens not balanced. */
4187 unsigned int paren_not_balanced;
4188
4189 while (*l != END_OF_INSN)
4190 {
4191 /* Skip optional white space before operand. */
4192 if (is_space_char (*l))
4193 ++l;
d02603dc 4194 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4195 {
4196 as_bad (_("invalid character %s before operand %d"),
4197 output_invalid (*l),
4198 i.operands + 1);
4199 return NULL;
4200 }
d02603dc 4201 token_start = l; /* After white space. */
29b0f896
AM		 4202 paren_not_balanced = 0;
4203 while (paren_not_balanced || *l != ',')
4204 {
4205 if (*l == END_OF_INSN)
4206 {
4207 if (paren_not_balanced)
4208 {
4209 if (!intel_syntax)
4210 as_bad (_("unbalanced parenthesis in operand %d."),
4211 i.operands + 1);
4212 else
4213 as_bad (_("unbalanced brackets in operand %d."),
4214 i.operands + 1);
4215 return NULL;
4216 }
4217 else
4218 break; /* we are done */
4219 }
d02603dc 4220 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4221 {
4222 as_bad (_("invalid character %s in operand %d"),
4223 output_invalid (*l),
4224 i.operands + 1);
4225 return NULL;
4226 }
4227 if (!intel_syntax)
4228 {
4229 if (*l == '(')
4230 ++paren_not_balanced;
4231 if (*l == ')')
4232 --paren_not_balanced;
4233 }
4234 else
4235 {
4236 if (*l == '[')
4237 ++paren_not_balanced;
4238 if (*l == ']')
4239 --paren_not_balanced;
4240 }
4241 l++;
4242 }
4243 if (l != token_start)
4244 { /* Yes, we've read in another operand. */
4245 unsigned int operand_ok;
4246 this_operand = i.operands++;
4247 if (i.operands > MAX_OPERANDS)
4248 {
4249 as_bad (_("spurious operands; (%d operands/instruction max)"),
4250 MAX_OPERANDS);
4251 return NULL;
4252 }
9d46ce34 4253 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4254 /* Now parse operand adding info to 'i' as we go along. */
4255 END_STRING_AND_SAVE (l);
4256
4257 if (intel_syntax)
4258 operand_ok =
4259 i386_intel_operand (token_start,
4260 intel_float_operand (mnemonic));
4261 else
a7619375 4262 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4263
4264 RESTORE_END_STRING (l);
4265 if (!operand_ok)
4266 return NULL;
4267 }
4268 else
4269 {
4270 if (expecting_operand)
4271 {
4272 expecting_operand_after_comma:
4273 as_bad (_("expecting operand after ','; got nothing"));
4274 return NULL;
4275 }
4276 if (*l == ',')
4277 {
4278 as_bad (_("expecting operand before ','; got nothing"));
4279 return NULL;
4280 }
4281 }
7f3f1ea2 4282
29b0f896
AM		 4283 /* Now *l must be either ',' or END_OF_INSN. */
4284 if (*l == ',')
4285 {
4286 if (*++l == END_OF_INSN)
4287 {
4288 /* Just skip it, if it's \n complain. */
4289 goto expecting_operand_after_comma;
4290 }
4291 expecting_operand = 1;
4292 }
4293 }
4294 return l;
4295}
7f3f1ea2 4296
050dfa73 4297static void
4d456e3d 4298swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4299{
4300 union i386_op temp_op;
40fb9820 4301 i386_operand_type temp_type;
050dfa73 4302 enum bfd_reloc_code_real temp_reloc;
4eed87de 4303
050dfa73
MM		 4304 temp_type = i.types[xchg2];
4305 i.types[xchg2] = i.types[xchg1];
4306 i.types[xchg1] = temp_type;
4307 temp_op = i.op[xchg2];
4308 i.op[xchg2] = i.op[xchg1];
4309 i.op[xchg1] = temp_op;
4310 temp_reloc = i.reloc[xchg2];
4311 i.reloc[xchg2] = i.reloc[xchg1];
4312 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4313
4314 if (i.mask)
4315 {
4316 if (i.mask->operand == xchg1)
4317 i.mask->operand = xchg2;
4318 else if (i.mask->operand == xchg2)
4319 i.mask->operand = xchg1;
4320 }
4321 if (i.broadcast)
4322 {
4323 if (i.broadcast->operand == xchg1)
4324 i.broadcast->operand = xchg2;
4325 else if (i.broadcast->operand == xchg2)
4326 i.broadcast->operand = xchg1;
4327 }
4328 if (i.rounding)
4329 {
4330 if (i.rounding->operand == xchg1)
4331 i.rounding->operand = xchg2;
4332 else if (i.rounding->operand == xchg2)
4333 i.rounding->operand = xchg1;
4334 }
050dfa73
MM		 4335}
4336
29b0f896 4337static void
e3bb37b5 4338swap_operands (void)
29b0f896 4339{
b7c61d9a 4340 switch (i.operands)
050dfa73 4341 {
c0f3af97 4342 case 5:
b7c61d9a 4343 case 4:
4d456e3d 4344 swap_2_operands (1, i.operands - 2);
1a0670f3 4345 /* Fall through. */
b7c61d9a
L		 4346 case 3:
4347 case 2:
4d456e3d 4348 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4349 break;
4350 default:
4351 abort ();
29b0f896 4352 }
29b0f896
AM		 4353
4354 if (i.mem_operands == 2)
4355 {
4356 const seg_entry *temp_seg;
4357 temp_seg = i.seg[0];
4358 i.seg[0] = i.seg[1];
4359 i.seg[1] = temp_seg;
4360 }
4361}
252b5132 4362
29b0f896
AM		 4363/* Try to ensure constant immediates are represented in the smallest
4364 opcode possible. */
4365static void
e3bb37b5 4366optimize_imm (void)
29b0f896
AM		 4367{
4368 char guess_suffix = 0;
4369 int op;
252b5132 4370
29b0f896
AM		 4371 if (i.suffix)
4372 guess_suffix = i.suffix;
4373 else if (i.reg_operands)
4374 {
4375 /* Figure out a suffix from the last register operand specified.
4376 We can't do this properly yet, ie. excluding InOutPortReg,
4377 but the following works for instructions with immediates.
4378 In any case, we can't set i.suffix yet. */
4379 for (op = i.operands; --op >= 0;)
40fb9820 4380 if (i.types[op].bitfield.reg8)
7ab9ffdd 4381 {
40fb9820
L		 4382 guess_suffix = BYTE_MNEM_SUFFIX;
4383 break;
4384 }
4385 else if (i.types[op].bitfield.reg16)
252b5132 4386 {
40fb9820
L		 4387 guess_suffix = WORD_MNEM_SUFFIX;
4388 break;
4389 }
4390 else if (i.types[op].bitfield.reg32)
4391 {
4392 guess_suffix = LONG_MNEM_SUFFIX;
4393 break;
4394 }
4395 else if (i.types[op].bitfield.reg64)
4396 {
4397 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4398 break;
252b5132 4399 }
29b0f896
AM		 4400 }
4401 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4402 guess_suffix = WORD_MNEM_SUFFIX;
4403
4404 for (op = i.operands; --op >= 0;)
40fb9820 4405 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4406 {
4407 switch (i.op[op].imms->X_op)
252b5132 4408 {
29b0f896
AM		 4409 case O_constant:
4410 /* If a suffix is given, this operand may be shortened. */
4411 switch (guess_suffix)
252b5132 4412 {
29b0f896 4413 case LONG_MNEM_SUFFIX:
40fb9820
L		 4414 i.types[op].bitfield.imm32 = 1;
4415 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4416 break;
4417 case WORD_MNEM_SUFFIX:
40fb9820
L		 4418 i.types[op].bitfield.imm16 = 1;
4419 i.types[op].bitfield.imm32 = 1;
4420 i.types[op].bitfield.imm32s = 1;
4421 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4422 break;
4423 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4424 i.types[op].bitfield.imm8 = 1;
4425 i.types[op].bitfield.imm8s = 1;
4426 i.types[op].bitfield.imm16 = 1;
4427 i.types[op].bitfield.imm32 = 1;
4428 i.types[op].bitfield.imm32s = 1;
4429 i.types[op].bitfield.imm64 = 1;
29b0f896 4430 break;
252b5132 4431 }
252b5132 4432
29b0f896
AM		 4433 /* If this operand is at most 16 bits, convert it
4434 to a signed 16 bit number before trying to see
4435 whether it will fit in an even smaller size.
4436 This allows a 16-bit operand such as $0xffe0 to
4437 be recognised as within Imm8S range. */
40fb9820 4438 if ((i.types[op].bitfield.imm16)
29b0f896 4439 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4440 {
29b0f896
AM		 4441 i.op[op].imms->X_add_number =
4442 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4443 }
a28def75
L		 4444#ifdef BFD64
4445 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4446 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4447 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4448 == 0))
4449 {
4450 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4451 ^ ((offsetT) 1 << 31))
4452 - ((offsetT) 1 << 31));
4453 }
a28def75 4454#endif
40fb9820 4455 i.types[op]
c6fb90c8
L		 4456 = operand_type_or (i.types[op],
4457 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4458
29b0f896
AM		 4459 /* We must avoid matching of Imm32 templates when 64bit
4460 only immediate is available. */
4461 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4462 i.types[op].bitfield.imm32 = 0;
29b0f896 4463 break;
252b5132 4464
29b0f896
AM		 4465 case O_absent:
4466 case O_register:
4467 abort ();
4468
4469 /* Symbols and expressions. */
4470 default:
9cd96992
JB		 4471 /* Convert symbolic operand to proper sizes for matching, but don't
4472 prevent matching a set of insns that only supports sizes other
4473 than those matching the insn suffix. */
4474 {
40fb9820 4475 i386_operand_type mask, allowed;
d3ce72d0 4476 const insn_template *t;
9cd96992 4477
0dfbf9d7
L		 4478 operand_type_set (&mask, 0);
4479 operand_type_set (&allowed, 0);
40fb9820 4480
4eed87de
AM		 4481 for (t = current_templates->start;
4482 t < current_templates->end;
4483 ++t)
c6fb90c8
L		 4484 allowed = operand_type_or (allowed,
4485 t->operand_types[op]);
9cd96992
JB		 4486 switch (guess_suffix)
4487 {
4488 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4489 mask.bitfield.imm64 = 1;
4490 mask.bitfield.imm32s = 1;
9cd96992
JB		 4491 break;
4492 case LONG_MNEM_SUFFIX:
40fb9820 4493 mask.bitfield.imm32 = 1;
9cd96992
JB		 4494 break;
4495 case WORD_MNEM_SUFFIX:
40fb9820 4496 mask.bitfield.imm16 = 1;
9cd96992
JB		 4497 break;
4498 case BYTE_MNEM_SUFFIX:
40fb9820 4499 mask.bitfield.imm8 = 1;
9cd96992
JB		 4500 break;
4501 default:
9cd96992
JB		 4502 break;
4503 }
c6fb90c8 4504 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4505 if (!operand_type_all_zero (&allowed))
c6fb90c8 4506 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4507 }
29b0f896 4508 break;
252b5132 4509 }
29b0f896
AM		 4510 }
4511}
47926f60 4512
29b0f896
AM		 4513/* Try to use the smallest displacement type too. */
4514static void
e3bb37b5 4515optimize_disp (void)
29b0f896
AM		 4516{
4517 int op;
3e73aa7c 4518
29b0f896 4519 for (op = i.operands; --op >= 0;)
40fb9820 4520 if (operand_type_check (i.types[op], disp))
252b5132 4521 {
b300c311 4522 if (i.op[op].disps->X_op == O_constant)
252b5132 4523 {
91d6fa6a 4524 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4525
40fb9820 4526 if (i.types[op].bitfield.disp16
91d6fa6a 4527 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4528 {
4529 /* If this operand is at most 16 bits, convert
4530 to a signed 16 bit number and don't use 64bit
4531 displacement. */
91d6fa6a 4532 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4533 i.types[op].bitfield.disp64 = 0;
b300c311 4534 }
a28def75
L		 4535#ifdef BFD64
4536 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4537 if (i.types[op].bitfield.disp32
91d6fa6a 4538 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4539 {
4540 /* If this operand is at most 32 bits, convert
4541 to a signed 32 bit number and don't use 64bit
4542 displacement. */
91d6fa6a
NC		 4543 op_disp &= (((offsetT) 2 << 31) - 1);
4544 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4545 i.types[op].bitfield.disp64 = 0;
b300c311 4546 }
a28def75 4547#endif
91d6fa6a 4548 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4549 {
40fb9820
L		 4550 i.types[op].bitfield.disp8 = 0;
4551 i.types[op].bitfield.disp16 = 0;
4552 i.types[op].bitfield.disp32 = 0;
4553 i.types[op].bitfield.disp32s = 0;
4554 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4555 i.op[op].disps = 0;
4556 i.disp_operands--;
4557 }
4558 else if (flag_code == CODE_64BIT)
4559 {
91d6fa6a 4560 if (fits_in_signed_long (op_disp))
28a9d8f5 4561 {
40fb9820
L		 4562 i.types[op].bitfield.disp64 = 0;
4563 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4564 }
0e1147d9 4565 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4566 && fits_in_unsigned_long (op_disp))
40fb9820 4567 i.types[op].bitfield.disp32 = 1;
b300c311 4568 }
40fb9820
L		 4569 if ((i.types[op].bitfield.disp32
4570 || i.types[op].bitfield.disp32s
4571 || i.types[op].bitfield.disp16)
b5014f7a 4572 && fits_in_disp8 (op_disp))
40fb9820 4573 i.types[op].bitfield.disp8 = 1;
252b5132 4574 }
67a4f2b7
AO		 4575 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4576 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4577 {
4578 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4579 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4580 i.types[op].bitfield.disp8 = 0;
4581 i.types[op].bitfield.disp16 = 0;
4582 i.types[op].bitfield.disp32 = 0;
4583 i.types[op].bitfield.disp32s = 0;
4584 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4585 }
4586 else
b300c311 4587 /* We only support 64bit displacement on constants. */
40fb9820 4588 i.types[op].bitfield.disp64 = 0;
252b5132 4589 }
29b0f896
AM		 4590}
4591
6c30d220
L		 4592/* Check if operands are valid for the instruction. */
4593
4594static int
4595check_VecOperands (const insn_template *t)
4596{
43234a1e
L		 4597 unsigned int op;
4598
6c30d220
L		 4599 /* Without VSIB byte, we can't have a vector register for index. */
4600 if (!t->opcode_modifier.vecsib
4601 && i.index_reg
4602 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4603 || i.index_reg->reg_type.bitfield.regymm
4604 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4605 {
4606 i.error = unsupported_vector_index_register;
4607 return 1;
4608 }
4609
ad8ecc81
MZ		 4610 /* Check if default mask is allowed. */
4611 if (t->opcode_modifier.nodefmask
4612 && (!i.mask || i.mask->mask->reg_num == 0))
4613 {
4614 i.error = no_default_mask;
4615 return 1;
4616 }
4617
7bab8ab5
JB		 4618 /* For VSIB byte, we need a vector register for index, and all vector
4619 registers must be distinct. */
4620 if (t->opcode_modifier.vecsib)
4621 {
4622 if (!i.index_reg
6c30d220
L		 4623 || !((t->opcode_modifier.vecsib == VecSIB128
4624 && i.index_reg->reg_type.bitfield.regxmm)
4625 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4626 && i.index_reg->reg_type.bitfield.regymm)
4627 || (t->opcode_modifier.vecsib == VecSIB512
4628 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4629 {
4630 i.error = invalid_vsib_address;
4631 return 1;
4632 }
4633
43234a1e
L		 4634 gas_assert (i.reg_operands == 2 || i.mask);
4635 if (i.reg_operands == 2 && !i.mask)
4636 {
4637 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4638 || i.types[0].bitfield.regymm);
43234a1e 4639 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4640 || i.types[2].bitfield.regymm);
43234a1e
L		 4641 if (operand_check == check_none)
4642 return 0;
4643 if (register_number (i.op[0].regs)
4644 != register_number (i.index_reg)
4645 && register_number (i.op[2].regs)
4646 != register_number (i.index_reg)
4647 && register_number (i.op[0].regs)
4648 != register_number (i.op[2].regs))
4649 return 0;
4650 if (operand_check == check_error)
4651 {
4652 i.error = invalid_vector_register_set;
4653 return 1;
4654 }
4655 as_warn (_("mask, index, and destination registers should be distinct"));
4656 }
8444f82a
MZ		 4657 else if (i.reg_operands == 1 && i.mask)
4658 {
514f6023
L		 4659 if ((i.types[1].bitfield.regxmm
4660 || i.types[1].bitfield.regymm
8444f82a
MZ		 4661 || i.types[1].bitfield.regzmm)
4662 && (register_number (i.op[1].regs)
4663 == register_number (i.index_reg)))
4664 {
4665 if (operand_check == check_error)
4666 {
4667 i.error = invalid_vector_register_set;
4668 return 1;
4669 }
4670 if (operand_check != check_none)
4671 as_warn (_("index and destination registers should be distinct"));
4672 }
4673 }
43234a1e 4674 }
7bab8ab5 4675
43234a1e
L		 4676 /* Check if broadcast is supported by the instruction and is applied
4677 to the memory operand. */
4678 if (i.broadcast)
4679 {
4680 int broadcasted_opnd_size;
4681
4682 /* Check if specified broadcast is supported in this instruction,
4683 and it's applied to memory operand of DWORD or QWORD type,
4684 depending on VecESize. */
4685 if (i.broadcast->type != t->opcode_modifier.broadcast
4686 || !i.types[i.broadcast->operand].bitfield.mem
4687 || (t->opcode_modifier.vecesize == 0
4688 && !i.types[i.broadcast->operand].bitfield.dword
4689 && !i.types[i.broadcast->operand].bitfield.unspecified)
4690 || (t->opcode_modifier.vecesize == 1
4691 && !i.types[i.broadcast->operand].bitfield.qword
4692 && !i.types[i.broadcast->operand].bitfield.unspecified))
4693 goto bad_broadcast;
4694
4695 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4696 if (i.broadcast->type == BROADCAST_1TO16)
4697 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4698 else if (i.broadcast->type == BROADCAST_1TO8)
4699 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4700 else if (i.broadcast->type == BROADCAST_1TO4)
4701 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4702 else if (i.broadcast->type == BROADCAST_1TO2)
4703 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4704 else
4705 goto bad_broadcast;
4706
4707 if ((broadcasted_opnd_size == 256
4708 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4709 || (broadcasted_opnd_size == 512
4710 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4711 {
4712 bad_broadcast:
4713 i.error = unsupported_broadcast;
4714 return 1;
4715 }
4716 }
4717 /* If broadcast is supported in this instruction, we need to check if
4718 operand of one-element size isn't specified without broadcast. */
4719 else if (t->opcode_modifier.broadcast && i.mem_operands)
4720 {
4721 /* Find memory operand. */
4722 for (op = 0; op < i.operands; op++)
4723 if (operand_type_check (i.types[op], anymem))
4724 break;
4725 gas_assert (op < i.operands);
4726 /* Check size of the memory operand. */
4727 if ((t->opcode_modifier.vecesize == 0
4728 && i.types[op].bitfield.dword)
4729 || (t->opcode_modifier.vecesize == 1
4730 && i.types[op].bitfield.qword))
4731 {
4732 i.error = broadcast_needed;
4733 return 1;
4734 }
4735 }
4736
4737 /* Check if requested masking is supported. */
4738 if (i.mask
4739 && (!t->opcode_modifier.masking
4740 || (i.mask->zeroing
4741 && t->opcode_modifier.masking == MERGING_MASKING)))
4742 {
4743 i.error = unsupported_masking;
4744 return 1;
4745 }
4746
4747 /* Check if masking is applied to dest operand. */
4748 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4749 {
4750 i.error = mask_not_on_destination;
4751 return 1;
4752 }
4753
43234a1e
L		 4754 /* Check RC/SAE. */
4755 if (i.rounding)
4756 {
4757 if ((i.rounding->type != saeonly
4758 && !t->opcode_modifier.staticrounding)
4759 || (i.rounding->type == saeonly
4760 && (t->opcode_modifier.staticrounding
4761 || !t->opcode_modifier.sae)))
4762 {
4763 i.error = unsupported_rc_sae;
4764 return 1;
4765 }
4766 /* If the instruction has several immediate operands and one of
4767 them is rounding, the rounding operand should be the last
4768 immediate operand. */
4769 if (i.imm_operands > 1
4770 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4771 {
43234a1e 4772 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4773 return 1;
4774 }
6c30d220
L		 4775 }
4776
43234a1e 4777 /* Check vector Disp8 operand. */
b5014f7a
JB		 4778 if (t->opcode_modifier.disp8memshift
4779 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 4780 {
4781 if (i.broadcast)
4782 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4783 else
4784 i.memshift = t->opcode_modifier.disp8memshift;
4785
4786 for (op = 0; op < i.operands; op++)
4787 if (operand_type_check (i.types[op], disp)
4788 && i.op[op].disps->X_op == O_constant)
4789 {
b5014f7a 4790 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 4791 {
b5014f7a
JB		 4792 i.types[op].bitfield.disp8 = 1;
4793 return 0;
43234a1e 4794 }
b5014f7a 4795 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 4796 }
4797 }
b5014f7a
JB		 4798
4799 i.memshift = 0;
43234a1e 4800
6c30d220
L		 4801 return 0;
4802}
4803
43f3e2ee 4804/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4805 operand types. */
4806
4807static int
4808VEX_check_operands (const insn_template *t)
4809{
86fa6981 4810 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4811 {
86fa6981
L		 4812 /* This instruction must be encoded with EVEX prefix. */
4813 if (!t->opcode_modifier.evex)
4814 {
4815 i.error = unsupported;
4816 return 1;
4817 }
4818 return 0;
43234a1e
L		 4819 }
4820
a683cc34 4821 if (!t->opcode_modifier.vex)
86fa6981
L		 4822 {
4823 /* This instruction template doesn't have VEX prefix. */
4824 if (i.vec_encoding != vex_encoding_default)
4825 {
4826 i.error = unsupported;
4827 return 1;
4828 }
4829 return 0;
4830 }
a683cc34
SP		 4831
4832 /* Only check VEX_Imm4, which must be the first operand. */
4833 if (t->operand_types[0].bitfield.vec_imm4)
4834 {
4835 if (i.op[0].imms->X_op != O_constant
4836 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4837 {
a65babc9 4838 i.error = bad_imm4;
891edac4
L		 4839 return 1;
4840 }
a683cc34
SP		 4841
4842 /* Turn off Imm8 so that update_imm won't complain. */
4843 i.types[0] = vec_imm4;
4844 }
4845
4846 return 0;
4847}
4848
d3ce72d0 4849static const insn_template *
83b16ac6 4850match_template (char mnem_suffix)
29b0f896
AM		 4851{
4852 /* Points to template once we've found it. */
d3ce72d0 4853 const insn_template *t;
40fb9820 4854 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4855 i386_operand_type overlap4;
29b0f896 4856 unsigned int found_reverse_match;
83b16ac6 4857 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4858 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4859 int addr_prefix_disp;
a5c311ca 4860 unsigned int j;
3629bb00 4861 unsigned int found_cpu_match;
45664ddb 4862 unsigned int check_register;
5614d22c 4863 enum i386_error specific_error = 0;
29b0f896 4864
c0f3af97
L		 4865#if MAX_OPERANDS != 5
4866# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4867#endif
4868
29b0f896 4869 found_reverse_match = 0;
539e75ad 4870 addr_prefix_disp = -1;
40fb9820
L		 4871
4872 memset (&suffix_check, 0, sizeof (suffix_check));
4873 if (i.suffix == BYTE_MNEM_SUFFIX)
4874 suffix_check.no_bsuf = 1;
4875 else if (i.suffix == WORD_MNEM_SUFFIX)
4876 suffix_check.no_wsuf = 1;
4877 else if (i.suffix == SHORT_MNEM_SUFFIX)
4878 suffix_check.no_ssuf = 1;
4879 else if (i.suffix == LONG_MNEM_SUFFIX)
4880 suffix_check.no_lsuf = 1;
4881 else if (i.suffix == QWORD_MNEM_SUFFIX)
4882 suffix_check.no_qsuf = 1;
4883 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4884 suffix_check.no_ldsuf = 1;
29b0f896 4885
83b16ac6
JB		 4886 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4887 if (intel_syntax)
4888 {
4889 switch (mnem_suffix)
4890 {
4891 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4892 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4893 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4894 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4895 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4896 }
4897 }
4898
01559ecc
L		 4899 /* Must have right number of operands. */
4900 i.error = number_of_operands_mismatch;
4901
45aa61fe 4902 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4903 {
539e75ad
L		 4904 addr_prefix_disp = -1;
4905
29b0f896
AM		 4906 if (i.operands != t->operands)
4907 continue;
4908
50aecf8c 4909 /* Check processor support. */
a65babc9 4910 i.error = unsupported;
c0f3af97
L		 4911 found_cpu_match = (cpu_flags_match (t)
4912 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4913 if (!found_cpu_match)
4914 continue;
4915
e1d4d893 4916 /* Check old gcc support. */
a65babc9 4917 i.error = old_gcc_only;
e1d4d893
L		 4918 if (!old_gcc && t->opcode_modifier.oldgcc)
4919 continue;
4920
4921 /* Check AT&T mnemonic. */
a65babc9 4922 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4923 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4924 continue;
4925
e92bae62 4926 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4927 i.error = unsupported_syntax;
5c07affc 4928 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4929 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4930 || (intel64 && t->opcode_modifier.amd64)
4931 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4932 continue;
4933
20592a94 4934 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4935 i.error = invalid_instruction_suffix;
567e4e96
L		 4936 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4937 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4938 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4939 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4940 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4941 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4942 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4943 continue;
83b16ac6
JB		 4944 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4945 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4946 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4947 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4948 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4949 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4950 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4951 continue;
29b0f896 4952
5c07affc 4953 if (!operand_size_match (t))
7d5e4556 4954 continue;
539e75ad 4955
5c07affc
L		 4956 for (j = 0; j < MAX_OPERANDS; j++)
4957 operand_types[j] = t->operand_types[j];
4958
45aa61fe
AM		 4959 /* In general, don't allow 64-bit operands in 32-bit mode. */
4960 if (i.suffix == QWORD_MNEM_SUFFIX
4961 && flag_code != CODE_64BIT
4962 && (intel_syntax
40fb9820 4963 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4964 && !intel_float_operand (t->name))
4965 : intel_float_operand (t->name) != 2)
40fb9820 4966 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4967 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4968 && !operand_types[0].bitfield.regymm
4969 && !operand_types[0].bitfield.regzmm)
40fb9820 4970 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4971 && operand_types[t->operands > 1].bitfield.regxmm
4972 && operand_types[t->operands > 1].bitfield.regymm
4973 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4974 && (t->base_opcode != 0x0fc7
4975 || t->extension_opcode != 1 /* cmpxchg8b */))
4976 continue;
4977
192dc9c6
JB		 4978 /* In general, don't allow 32-bit operands on pre-386. */
4979 else if (i.suffix == LONG_MNEM_SUFFIX
4980 && !cpu_arch_flags.bitfield.cpui386
4981 && (intel_syntax
4982 ? (!t->opcode_modifier.ignoresize
4983 && !intel_float_operand (t->name))
4984 : intel_float_operand (t->name) != 2)
4985 && ((!operand_types[0].bitfield.regmmx
4986 && !operand_types[0].bitfield.regxmm)
4987 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4988 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4989 continue;
4990
29b0f896 4991 /* Do not verify operands when there are none. */
50aecf8c 4992 else
29b0f896 4993 {
c6fb90c8 4994 if (!t->operands)
2dbab7d5
L		 4995 /* We've found a match; break out of loop. */
4996 break;
29b0f896 4997 }
252b5132 4998
539e75ad
L		 4999 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5000 into Disp32/Disp16/Disp32 operand. */
5001 if (i.prefix[ADDR_PREFIX] != 0)
5002 {
40fb9820 5003 /* There should be only one Disp operand. */
539e75ad
L		 5004 switch (flag_code)
5005 {
5006 case CODE_16BIT:
40fb9820
L		 5007 for (j = 0; j < MAX_OPERANDS; j++)
5008 {
5009 if (operand_types[j].bitfield.disp16)
5010 {
5011 addr_prefix_disp = j;
5012 operand_types[j].bitfield.disp32 = 1;
5013 operand_types[j].bitfield.disp16 = 0;
5014 break;
5015 }
5016 }
539e75ad
L		 5017 break;
5018 case CODE_32BIT:
40fb9820
L		 5019 for (j = 0; j < MAX_OPERANDS; j++)
5020 {
5021 if (operand_types[j].bitfield.disp32)
5022 {
5023 addr_prefix_disp = j;
5024 operand_types[j].bitfield.disp32 = 0;
5025 operand_types[j].bitfield.disp16 = 1;
5026 break;
5027 }
5028 }
539e75ad
L		 5029 break;
5030 case CODE_64BIT:
40fb9820
L		 5031 for (j = 0; j < MAX_OPERANDS; j++)
5032 {
5033 if (operand_types[j].bitfield.disp64)
5034 {
5035 addr_prefix_disp = j;
5036 operand_types[j].bitfield.disp64 = 0;
5037 operand_types[j].bitfield.disp32 = 1;
5038 break;
5039 }
5040 }
539e75ad
L		 5041 break;
5042 }
539e75ad
L		 5043 }
5044
02a86693
L		 5045 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5046 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5047 continue;
5048
56ffb741
L		 5049 /* We check register size if needed. */
5050 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5051 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5052 switch (t->operands)
5053 {
5054 case 1:
40fb9820 5055 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5056 continue;
5057 break;
5058 case 2:
33eaf5de 5059 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5060 only in 32bit mode and we can use opcode 0x90. In 64bit
5061 mode, we can't use 0x90 for xchg %eax, %eax since it should
5062 zero-extend %eax to %rax. */
5063 if (flag_code == CODE_64BIT
5064 && t->base_opcode == 0x90
0dfbf9d7
L		 5065 && operand_type_equal (&i.types [0], &acc32)
5066 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5067 continue;
86fa6981
L		 5068 /* If we want store form, we reverse direction of operands. */
5069 if (i.dir_encoding == dir_encoding_store
5070 && t->opcode_modifier.d)
5071 goto check_reverse;
1a0670f3 5072 /* Fall through. */
b6169b20 5073
29b0f896 5074 case 3:
86fa6981
L		 5075 /* If we want store form, we skip the current load. */
5076 if (i.dir_encoding == dir_encoding_store
5077 && i.mem_operands == 0
5078 && t->opcode_modifier.load)
fa99fab2 5079 continue;
1a0670f3 5080 /* Fall through. */
f48ff2ae 5081 case 4:
c0f3af97 5082 case 5:
c6fb90c8 5083 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5084 if (!operand_type_match (overlap0, i.types[0])
5085 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5086 || (check_register
5087 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 5088 operand_types[0],
5089 overlap1, i.types[1],
5090 operand_types[1])))
29b0f896
AM		 5091 {
5092 /* Check if other direction is valid ... */
40fb9820 5093 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5094 continue;
5095
b6169b20 5096check_reverse:
29b0f896 5097 /* Try reversing direction of operands. */
c6fb90c8
L		 5098 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5099 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5100 if (!operand_type_match (overlap0, i.types[0])
5101 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5102 || (check_register
5103 && !operand_type_register_match (overlap0,
5104 i.types[0],
5105 operand_types[1],
5106 overlap1,
5107 i.types[1],
5108 operand_types[0])))
29b0f896
AM		 5109 {
5110 /* Does not match either direction. */
5111 continue;
5112 }
5113 /* found_reverse_match holds which of D or FloatDR
5114 we've found. */
40fb9820 5115 if (t->opcode_modifier.d)
8a2ed489 5116 found_reverse_match = Opcode_D;
40fb9820 5117 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5118 found_reverse_match = Opcode_FloatD;
5119 else
5120 found_reverse_match = 0;
40fb9820 5121 if (t->opcode_modifier.floatr)
8a2ed489 5122 found_reverse_match |= Opcode_FloatR;
29b0f896 5123 }
f48ff2ae 5124 else
29b0f896 5125 {
f48ff2ae 5126 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5127 switch (t->operands)
5128 {
c0f3af97
L		 5129 case 5:
5130 overlap4 = operand_type_and (i.types[4],
5131 operand_types[4]);
1a0670f3 5132 /* Fall through. */
d1cbb4db 5133 case 4:
c6fb90c8
L		 5134 overlap3 = operand_type_and (i.types[3],
5135 operand_types[3]);
1a0670f3 5136 /* Fall through. */
d1cbb4db 5137 case 3:
c6fb90c8
L		 5138 overlap2 = operand_type_and (i.types[2],
5139 operand_types[2]);
d1cbb4db
L		 5140 break;
5141 }
29b0f896 5142
f48ff2ae
L		 5143 switch (t->operands)
5144 {
c0f3af97
L		 5145 case 5:
5146 if (!operand_type_match (overlap4, i.types[4])
5147 || !operand_type_register_match (overlap3,
5148 i.types[3],
5149 operand_types[3],
5150 overlap4,
5151 i.types[4],
5152 operand_types[4]))
5153 continue;
1a0670f3 5154 /* Fall through. */
f48ff2ae 5155 case 4:
40fb9820 5156 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5157 || (check_register
5158 && !operand_type_register_match (overlap2,
5159 i.types[2],
5160 operand_types[2],
5161 overlap3,
5162 i.types[3],
5163 operand_types[3])))
f48ff2ae 5164 continue;
1a0670f3 5165 /* Fall through. */
f48ff2ae
L		 5166 case 3:
5167 /* Here we make use of the fact that there are no
5168 reverse match 3 operand instructions, and all 3
5169 operand instructions only need to be checked for
5170 register consistency between operands 2 and 3. */
40fb9820 5171 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5172 || (check_register
5173 && !operand_type_register_match (overlap1,
5174 i.types[1],
5175 operand_types[1],
5176 overlap2,
5177 i.types[2],
5178 operand_types[2])))
f48ff2ae
L		 5179 continue;
5180 break;
5181 }
29b0f896 5182 }
f48ff2ae 5183 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5184 slip through to break. */
5185 }
3629bb00 5186 if (!found_cpu_match)
29b0f896
AM		 5187 {
5188 found_reverse_match = 0;
5189 continue;
5190 }
c0f3af97 5191
5614d22c
JB		 5192 /* Check if vector and VEX operands are valid. */
5193 if (check_VecOperands (t) || VEX_check_operands (t))
5194 {
5195 specific_error = i.error;
5196 continue;
5197 }
a683cc34 5198
29b0f896
AM		 5199 /* We've found a match; break out of loop. */
5200 break;
5201 }
5202
5203 if (t == current_templates->end)
5204 {
5205 /* We found no match. */
a65babc9 5206 const char *err_msg;
5614d22c 5207 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5208 {
5209 default:
5210 abort ();
86e026a4 5211 case operand_size_mismatch:
a65babc9
L		 5212 err_msg = _("operand size mismatch");
5213 break;
5214 case operand_type_mismatch:
5215 err_msg = _("operand type mismatch");
5216 break;
5217 case register_type_mismatch:
5218 err_msg = _("register type mismatch");
5219 break;
5220 case number_of_operands_mismatch:
5221 err_msg = _("number of operands mismatch");
5222 break;
5223 case invalid_instruction_suffix:
5224 err_msg = _("invalid instruction suffix");
5225 break;
5226 case bad_imm4:
4a2608e3 5227 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5228 break;
5229 case old_gcc_only:
5230 err_msg = _("only supported with old gcc");
5231 break;
5232 case unsupported_with_intel_mnemonic:
5233 err_msg = _("unsupported with Intel mnemonic");
5234 break;
5235 case unsupported_syntax:
5236 err_msg = _("unsupported syntax");
5237 break;
5238 case unsupported:
35262a23 5239 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5240 current_templates->start->name);
5241 return NULL;
6c30d220
L		 5242 case invalid_vsib_address:
5243 err_msg = _("invalid VSIB address");
5244 break;
7bab8ab5
JB		 5245 case invalid_vector_register_set:
5246 err_msg = _("mask, index, and destination registers must be distinct");
5247 break;
6c30d220
L		 5248 case unsupported_vector_index_register:
5249 err_msg = _("unsupported vector index register");
5250 break;
43234a1e
L		 5251 case unsupported_broadcast:
5252 err_msg = _("unsupported broadcast");
5253 break;
5254 case broadcast_not_on_src_operand:
5255 err_msg = _("broadcast not on source memory operand");
5256 break;
5257 case broadcast_needed:
5258 err_msg = _("broadcast is needed for operand of such type");
5259 break;
5260 case unsupported_masking:
5261 err_msg = _("unsupported masking");
5262 break;
5263 case mask_not_on_destination:
5264 err_msg = _("mask not on destination operand");
5265 break;
5266 case no_default_mask:
5267 err_msg = _("default mask isn't allowed");
5268 break;
5269 case unsupported_rc_sae:
5270 err_msg = _("unsupported static rounding/sae");
5271 break;
5272 case rc_sae_operand_not_last_imm:
5273 if (intel_syntax)
5274 err_msg = _("RC/SAE operand must precede immediate operands");
5275 else
5276 err_msg = _("RC/SAE operand must follow immediate operands");
5277 break;
5278 case invalid_register_operand:
5279 err_msg = _("invalid register operand");
5280 break;
a65babc9
L		 5281 }
5282 as_bad (_("%s for `%s'"), err_msg,
891edac4 5283 current_templates->start->name);
fa99fab2 5284 return NULL;
29b0f896 5285 }
252b5132 5286
29b0f896
AM		 5287 if (!quiet_warnings)
5288 {
5289 if (!intel_syntax
40fb9820
L		 5290 && (i.types[0].bitfield.jumpabsolute
5291 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5292 {
5293 as_warn (_("indirect %s without `*'"), t->name);
5294 }
5295
40fb9820
L		 5296 if (t->opcode_modifier.isprefix
5297 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5298 {
5299 /* Warn them that a data or address size prefix doesn't
5300 affect assembly of the next line of code. */
5301 as_warn (_("stand-alone `%s' prefix"), t->name);
5302 }
5303 }
5304
5305 /* Copy the template we found. */
5306 i.tm = *t;
539e75ad
L		 5307
5308 if (addr_prefix_disp != -1)
5309 i.tm.operand_types[addr_prefix_disp]
5310 = operand_types[addr_prefix_disp];
5311
29b0f896
AM		 5312 if (found_reverse_match)
5313 {
5314 /* If we found a reverse match we must alter the opcode
5315 direction bit. found_reverse_match holds bits to change
5316 (different for int & float insns). */
5317
5318 i.tm.base_opcode ^= found_reverse_match;
5319
539e75ad
L		 5320 i.tm.operand_types[0] = operand_types[1];
5321 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5322 }
5323
fa99fab2 5324 return t;
29b0f896
AM		 5325}
5326
5327static int
e3bb37b5 5328check_string (void)
29b0f896 5329{
40fb9820
L		 5330 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5331 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5332 {
5333 if (i.seg[0] != NULL && i.seg[0] != &es)
5334 {
a87af027 5335 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5336 i.tm.name,
a87af027
JB		 5337 mem_op + 1,
5338 register_prefix);
29b0f896
AM		 5339 return 0;
5340 }
5341 /* There's only ever one segment override allowed per instruction.
5342 This instruction possibly has a legal segment override on the
5343 second operand, so copy the segment to where non-string
5344 instructions store it, allowing common code. */
5345 i.seg[0] = i.seg[1];
5346 }
40fb9820 5347 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5348 {
5349 if (i.seg[1] != NULL && i.seg[1] != &es)
5350 {
a87af027 5351 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5352 i.tm.name,
a87af027
JB		 5353 mem_op + 2,
5354 register_prefix);
29b0f896
AM		 5355 return 0;
5356 }
5357 }
5358 return 1;
5359}
5360
5361static int
543613e9 5362process_suffix (void)
29b0f896
AM		 5363{
5364 /* If matched instruction specifies an explicit instruction mnemonic
5365 suffix, use it. */
40fb9820
L		 5366 if (i.tm.opcode_modifier.size16)
5367 i.suffix = WORD_MNEM_SUFFIX;
5368 else if (i.tm.opcode_modifier.size32)
5369 i.suffix = LONG_MNEM_SUFFIX;
5370 else if (i.tm.opcode_modifier.size64)
5371 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5372 else if (i.reg_operands)
5373 {
5374 /* If there's no instruction mnemonic suffix we try to invent one
5375 based on register operands. */
5376 if (!i.suffix)
5377 {
5378 /* We take i.suffix from the last register operand specified,
5379 Destination register type is more significant than source
381d071f
L		 5380 register type. crc32 in SSE4.2 prefers source register
5381 type. */
5382 if (i.tm.base_opcode == 0xf20f38f1)
5383 {
40fb9820
L		 5384 if (i.types[0].bitfield.reg16)
5385 i.suffix = WORD_MNEM_SUFFIX;
5386 else if (i.types[0].bitfield.reg32)
5387 i.suffix = LONG_MNEM_SUFFIX;
5388 else if (i.types[0].bitfield.reg64)
5389 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5390 }
9344ff29 5391 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5392 {
40fb9820 5393 if (i.types[0].bitfield.reg8)
20592a94
L		 5394 i.suffix = BYTE_MNEM_SUFFIX;
5395 }
381d071f
L		 5396
5397 if (!i.suffix)
5398 {
5399 int op;
5400
20592a94
L		 5401 if (i.tm.base_opcode == 0xf20f38f1
5402 || i.tm.base_opcode == 0xf20f38f0)
5403 {
5404 /* We have to know the operand size for crc32. */
5405 as_bad (_("ambiguous memory operand size for `%s`"),
5406 i.tm.name);
5407 return 0;
5408 }
5409
381d071f 5410 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5411 if (!i.tm.operand_types[op].bitfield.inoutportreg
5412 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5413 {
40fb9820
L		 5414 if (i.types[op].bitfield.reg8)
5415 {
5416 i.suffix = BYTE_MNEM_SUFFIX;
5417 break;
5418 }
5419 else if (i.types[op].bitfield.reg16)
5420 {
5421 i.suffix = WORD_MNEM_SUFFIX;
5422 break;
5423 }
5424 else if (i.types[op].bitfield.reg32)
5425 {
5426 i.suffix = LONG_MNEM_SUFFIX;
5427 break;
5428 }
5429 else if (i.types[op].bitfield.reg64)
5430 {
5431 i.suffix = QWORD_MNEM_SUFFIX;
5432 break;
5433 }
381d071f
L		 5434 }
5435 }
29b0f896
AM		 5436 }
5437 else if (i.suffix == BYTE_MNEM_SUFFIX)
5438 {
2eb952a4
L		 5439 if (intel_syntax
5440 && i.tm.opcode_modifier.ignoresize
5441 && i.tm.opcode_modifier.no_bsuf)
5442 i.suffix = 0;
5443 else if (!check_byte_reg ())
29b0f896
AM		 5444 return 0;
5445 }
5446 else if (i.suffix == LONG_MNEM_SUFFIX)
5447 {
2eb952a4
L		 5448 if (intel_syntax
5449 && i.tm.opcode_modifier.ignoresize
5450 && i.tm.opcode_modifier.no_lsuf)
5451 i.suffix = 0;
5452 else if (!check_long_reg ())
29b0f896
AM		 5453 return 0;
5454 }
5455 else if (i.suffix == QWORD_MNEM_SUFFIX)
5456 {
955e1e6a
L		 5457 if (intel_syntax
5458 && i.tm.opcode_modifier.ignoresize
5459 && i.tm.opcode_modifier.no_qsuf)
5460 i.suffix = 0;
5461 else if (!check_qword_reg ())
29b0f896
AM		 5462 return 0;
5463 }
5464 else if (i.suffix == WORD_MNEM_SUFFIX)
5465 {
2eb952a4
L		 5466 if (intel_syntax
5467 && i.tm.opcode_modifier.ignoresize
5468 && i.tm.opcode_modifier.no_wsuf)
5469 i.suffix = 0;
5470 else if (!check_word_reg ())
29b0f896
AM		 5471 return 0;
5472 }
c0f3af97 5473 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5474 || i.suffix == YMMWORD_MNEM_SUFFIX
5475 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5476 {
43234a1e 5477 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5478 should check if it is a valid suffix. */
5479 }
40fb9820 5480 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5481 /* Do nothing if the instruction is going to ignore the prefix. */
5482 ;
5483 else
5484 abort ();
5485 }
40fb9820 5486 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5487 && !i.suffix
5488 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5489 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5490 {
5491 i.suffix = stackop_size;
5492 }
9306ca4a
JB		 5493 else if (intel_syntax
5494 && !i.suffix
40fb9820
L		 5495 && (i.tm.operand_types[0].bitfield.jumpabsolute
5496 || i.tm.opcode_modifier.jumpbyte
5497 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5498 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5499 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5500 {
5501 switch (flag_code)
5502 {
5503 case CODE_64BIT:
40fb9820 5504 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5505 {
5506 i.suffix = QWORD_MNEM_SUFFIX;
5507 break;
5508 }
1a0670f3 5509 /* Fall through. */
9306ca4a 5510 case CODE_32BIT:
40fb9820 5511 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5512 i.suffix = LONG_MNEM_SUFFIX;
5513 break;
5514 case CODE_16BIT:
40fb9820 5515 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5516 i.suffix = WORD_MNEM_SUFFIX;
5517 break;
5518 }
5519 }
252b5132 5520
9306ca4a 5521 if (!i.suffix)
29b0f896 5522 {
9306ca4a
JB		 5523 if (!intel_syntax)
5524 {
40fb9820 5525 if (i.tm.opcode_modifier.w)
9306ca4a 5526 {
4eed87de
AM		 5527 as_bad (_("no instruction mnemonic suffix given and "
5528 "no register operands; can't size instruction"));
9306ca4a
JB		 5529 return 0;
5530 }
5531 }
5532 else
5533 {
40fb9820 5534 unsigned int suffixes;
7ab9ffdd 5535
40fb9820
L		 5536 suffixes = !i.tm.opcode_modifier.no_bsuf;
5537 if (!i.tm.opcode_modifier.no_wsuf)
5538 suffixes |= 1 << 1;
5539 if (!i.tm.opcode_modifier.no_lsuf)
5540 suffixes |= 1 << 2;
fc4adea1 5541 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5542 suffixes |= 1 << 3;
5543 if (!i.tm.opcode_modifier.no_ssuf)
5544 suffixes |= 1 << 4;
c2b9da16 5545 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5546 suffixes |= 1 << 5;
5547
5548 /* There are more than suffix matches. */
5549 if (i.tm.opcode_modifier.w
9306ca4a 5550 || ((suffixes & (suffixes - 1))
40fb9820
L		 5551 && !i.tm.opcode_modifier.defaultsize
5552 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5553 {
5554 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5555 return 0;
5556 }
5557 }
29b0f896 5558 }
252b5132 5559
9306ca4a
JB		 5560 /* Change the opcode based on the operand size given by i.suffix;
5561 We don't need to change things for byte insns. */
5562
582d5edd
L		 5563 if (i.suffix
5564 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5565 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5566 && i.suffix != YMMWORD_MNEM_SUFFIX
5567 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5568 {
5569 /* It's not a byte, select word/dword operation. */
40fb9820 5570 if (i.tm.opcode_modifier.w)
29b0f896 5571 {
40fb9820 5572 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5573 i.tm.base_opcode |= 8;
5574 else
5575 i.tm.base_opcode |= 1;
5576 }
0f3f3d8b 5577
29b0f896
AM		 5578 /* Now select between word & dword operations via the operand
5579 size prefix, except for instructions that will ignore this
5580 prefix anyway. */
ca61edf2 5581 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5582 {
ca61edf2
L		 5583 /* The address size override prefix changes the size of the
5584 first operand. */
40fb9820
L		 5585 if ((flag_code == CODE_32BIT
5586 && i.op->regs[0].reg_type.bitfield.reg16)
5587 || (flag_code != CODE_32BIT
5588 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5589 if (!add_prefix (ADDR_PREFIX_OPCODE))
5590 return 0;
5591 }
5592 else if (i.suffix != QWORD_MNEM_SUFFIX
5593 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5594 && !i.tm.opcode_modifier.ignoresize
5595 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5596 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5597 || (flag_code == CODE_64BIT
40fb9820 5598 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5599 {
5600 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5601
40fb9820 5602 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5603 prefix = ADDR_PREFIX_OPCODE;
252b5132 5604
29b0f896
AM		 5605 if (!add_prefix (prefix))
5606 return 0;
24eab124 5607 }
252b5132 5608
29b0f896
AM		 5609 /* Set mode64 for an operand. */
5610 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5611 && flag_code == CODE_64BIT
40fb9820 5612 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5613 {
5614 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5615 need rex64. cmpxchg8b is also a special case. */
5616 if (! (i.operands == 2
5617 && i.tm.base_opcode == 0x90
5618 && i.tm.extension_opcode == None
0dfbf9d7
L		 5619 && operand_type_equal (&i.types [0], &acc64)
5620 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5621 && ! (i.operands == 1
5622 && i.tm.base_opcode == 0xfc7
5623 && i.tm.extension_opcode == 1
40fb9820
L		 5624 && !operand_type_check (i.types [0], reg)
5625 && operand_type_check (i.types [0], anymem)))
f6bee062 5626 i.rex |= REX_W;
46e883c5 5627 }
3e73aa7c 5628
29b0f896
AM		 5629 /* Size floating point instruction. */
5630 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5631 if (i.tm.opcode_modifier.floatmf)
543613e9 5632 i.tm.base_opcode ^= 4;
29b0f896 5633 }
7ecd2f8b 5634
29b0f896
AM		 5635 return 1;
5636}
3e73aa7c 5637
29b0f896 5638static int
543613e9 5639check_byte_reg (void)
29b0f896
AM		 5640{
5641 int op;
543613e9 5642
29b0f896
AM		 5643 for (op = i.operands; --op >= 0;)
5644 {
5645 /* If this is an eight bit register, it's OK. If it's the 16 or
5646 32 bit version of an eight bit register, we will just use the
5647 low portion, and that's OK too. */
40fb9820 5648 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5649 continue;
5650
5a819eb9
JB		 5651 /* I/O port address operands are OK too. */
5652 if (i.tm.operand_types[op].bitfield.inoutportreg)
5653 continue;
5654
9344ff29
L		 5655 /* crc32 doesn't generate this warning. */
5656 if (i.tm.base_opcode == 0xf20f38f0)
5657 continue;
5658
40fb9820
L		 5659 if ((i.types[op].bitfield.reg16
5660 || i.types[op].bitfield.reg32
5661 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5662 && i.op[op].regs->reg_num < 4
5663 /* Prohibit these changes in 64bit mode, since the lowering
5664 would be more complicated. */
5665 && flag_code != CODE_64BIT)
29b0f896 5666 {
29b0f896 5667#if REGISTER_WARNINGS
5a819eb9 5668 if (!quiet_warnings)
a540244d
L		 5669 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5670 register_prefix,
40fb9820 5671 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5672 ? REGNAM_AL - REGNAM_AX
5673 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5674 register_prefix,
29b0f896
AM		 5675 i.op[op].regs->reg_name,
5676 i.suffix);
5677#endif
5678 continue;
5679 }
5680 /* Any other register is bad. */
40fb9820
L		 5681 if (i.types[op].bitfield.reg16
5682 || i.types[op].bitfield.reg32
5683 || i.types[op].bitfield.reg64
5684 || i.types[op].bitfield.regmmx
5685 || i.types[op].bitfield.regxmm
c0f3af97 5686 || i.types[op].bitfield.regymm
43234a1e 5687 || i.types[op].bitfield.regzmm
40fb9820
L		 5688 || i.types[op].bitfield.sreg2
5689 || i.types[op].bitfield.sreg3
5690 || i.types[op].bitfield.control
5691 || i.types[op].bitfield.debug
5692 || i.types[op].bitfield.test
5693 || i.types[op].bitfield.floatreg
5694 || i.types[op].bitfield.floatacc)
29b0f896 5695 {
a540244d
L		 5696 as_bad (_("`%s%s' not allowed with `%s%c'"),
5697 register_prefix,
29b0f896
AM		 5698 i.op[op].regs->reg_name,
5699 i.tm.name,
5700 i.suffix);
5701 return 0;
5702 }
5703 }
5704 return 1;
5705}
5706
5707static int
e3bb37b5 5708check_long_reg (void)
29b0f896
AM		 5709{
5710 int op;
5711
5712 for (op = i.operands; --op >= 0;)
5713 /* Reject eight bit registers, except where the template requires
5714 them. (eg. movzb) */
40fb9820
L		 5715 if (i.types[op].bitfield.reg8
5716 && (i.tm.operand_types[op].bitfield.reg16
5717 || i.tm.operand_types[op].bitfield.reg32
5718 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5719 {
a540244d
L		 5720 as_bad (_("`%s%s' not allowed with `%s%c'"),
5721 register_prefix,
29b0f896
AM		 5722 i.op[op].regs->reg_name,
5723 i.tm.name,
5724 i.suffix);
5725 return 0;
5726 }
e4630f71 5727 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5728 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5729 && i.types[op].bitfield.reg16
5730 && (i.tm.operand_types[op].bitfield.reg32
5731 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5732 {
5733 /* Prohibit these changes in the 64bit mode, since the
5734 lowering is more complicated. */
5735 if (flag_code == CODE_64BIT)
252b5132 5736 {
2b5d6a91 5737 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5738 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5739 i.suffix);
5740 return 0;
252b5132 5741 }
29b0f896 5742#if REGISTER_WARNINGS
cecf1424
JB		 5743 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5744 register_prefix,
5745 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5746 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5747#endif
252b5132 5748 }
e4630f71 5749 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5750 else if (i.types[op].bitfield.reg64
5751 && (i.tm.operand_types[op].bitfield.reg32
5752 || i.tm.operand_types[op].bitfield.acc))
252b5132 5753 {
34828aad 5754 if (intel_syntax
ca61edf2 5755 && i.tm.opcode_modifier.toqword
40fb9820 5756 && !i.types[0].bitfield.regxmm)
34828aad 5757 {
ca61edf2 5758 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5759 i.suffix = QWORD_MNEM_SUFFIX;
5760 }
5761 else
5762 {
2b5d6a91 5763 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5764 register_prefix, i.op[op].regs->reg_name,
5765 i.suffix);
5766 return 0;
5767 }
29b0f896
AM		 5768 }
5769 return 1;
5770}
252b5132 5771
29b0f896 5772static int
e3bb37b5 5773check_qword_reg (void)
29b0f896
AM		 5774{
5775 int op;
252b5132 5776
29b0f896
AM		 5777 for (op = i.operands; --op >= 0; )
5778 /* Reject eight bit registers, except where the template requires
5779 them. (eg. movzb) */
40fb9820
L		 5780 if (i.types[op].bitfield.reg8
5781 && (i.tm.operand_types[op].bitfield.reg16
5782 || i.tm.operand_types[op].bitfield.reg32
5783 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5784 {
a540244d
L		 5785 as_bad (_("`%s%s' not allowed with `%s%c'"),
5786 register_prefix,
29b0f896
AM		 5787 i.op[op].regs->reg_name,
5788 i.tm.name,
5789 i.suffix);
5790 return 0;
5791 }
e4630f71 5792 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5793 else if ((i.types[op].bitfield.reg16
5794 || i.types[op].bitfield.reg32)
33d0ab95 5795 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5796 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5797 {
5798 /* Prohibit these changes in the 64bit mode, since the
5799 lowering is more complicated. */
34828aad 5800 if (intel_syntax
ca61edf2 5801 && i.tm.opcode_modifier.todword
40fb9820 5802 && !i.types[0].bitfield.regxmm)
34828aad 5803 {
ca61edf2 5804 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5805 i.suffix = LONG_MNEM_SUFFIX;
5806 }
5807 else
5808 {
2b5d6a91 5809 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5810 register_prefix, i.op[op].regs->reg_name,
5811 i.suffix);
5812 return 0;
5813 }
252b5132 5814 }
29b0f896
AM		 5815 return 1;
5816}
252b5132 5817
29b0f896 5818static int
e3bb37b5 5819check_word_reg (void)
29b0f896
AM		 5820{
5821 int op;
5822 for (op = i.operands; --op >= 0;)
5823 /* Reject eight bit registers, except where the template requires
5824 them. (eg. movzb) */
40fb9820
L		 5825 if (i.types[op].bitfield.reg8
5826 && (i.tm.operand_types[op].bitfield.reg16
5827 || i.tm.operand_types[op].bitfield.reg32
5828 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5829 {
a540244d
L		 5830 as_bad (_("`%s%s' not allowed with `%s%c'"),
5831 register_prefix,
29b0f896
AM		 5832 i.op[op].regs->reg_name,
5833 i.tm.name,
5834 i.suffix);
5835 return 0;
5836 }
e4630f71 5837 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5838 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5839 && (i.types[op].bitfield.reg32
5840 || i.types[op].bitfield.reg64)
40fb9820
L		 5841 && (i.tm.operand_types[op].bitfield.reg16
5842 || i.tm.operand_types[op].bitfield.acc))
252b5132 5843 {
29b0f896
AM		 5844 /* Prohibit these changes in the 64bit mode, since the
5845 lowering is more complicated. */
5846 if (flag_code == CODE_64BIT)
252b5132 5847 {
2b5d6a91 5848 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5849 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5850 i.suffix);
5851 return 0;
252b5132 5852 }
29b0f896 5853#if REGISTER_WARNINGS
cecf1424
JB		 5854 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5855 register_prefix,
5856 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5857 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5858#endif
5859 }
5860 return 1;
5861}
252b5132 5862
29b0f896 5863static int
40fb9820 5864update_imm (unsigned int j)
29b0f896 5865{
bc0844ae 5866 i386_operand_type overlap = i.types[j];
40fb9820
L		 5867 if ((overlap.bitfield.imm8
5868 || overlap.bitfield.imm8s
5869 || overlap.bitfield.imm16
5870 || overlap.bitfield.imm32
5871 || overlap.bitfield.imm32s
5872 || overlap.bitfield.imm64)
0dfbf9d7
L		 5873 && !operand_type_equal (&overlap, &imm8)
5874 && !operand_type_equal (&overlap, &imm8s)
5875 && !operand_type_equal (&overlap, &imm16)
5876 && !operand_type_equal (&overlap, &imm32)
5877 && !operand_type_equal (&overlap, &imm32s)
5878 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5879 {
5880 if (i.suffix)
5881 {
40fb9820
L		 5882 i386_operand_type temp;
5883
0dfbf9d7 5884 operand_type_set (&temp, 0);
7ab9ffdd 5885 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5886 {
5887 temp.bitfield.imm8 = overlap.bitfield.imm8;
5888 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5889 }
5890 else if (i.suffix == WORD_MNEM_SUFFIX)
5891 temp.bitfield.imm16 = overlap.bitfield.imm16;
5892 else if (i.suffix == QWORD_MNEM_SUFFIX)
5893 {
5894 temp.bitfield.imm64 = overlap.bitfield.imm64;
5895 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5896 }
5897 else
5898 temp.bitfield.imm32 = overlap.bitfield.imm32;
5899 overlap = temp;
29b0f896 5900 }
0dfbf9d7
L		 5901 else if (operand_type_equal (&overlap, &imm16_32_32s)
5902 || operand_type_equal (&overlap, &imm16_32)
5903 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5904 {
40fb9820 5905 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5906 overlap = imm16;
40fb9820 5907 else
65da13b5 5908 overlap = imm32s;
29b0f896 5909 }
0dfbf9d7
L		 5910 if (!operand_type_equal (&overlap, &imm8)
5911 && !operand_type_equal (&overlap, &imm8s)
5912 && !operand_type_equal (&overlap, &imm16)
5913 && !operand_type_equal (&overlap, &imm32)
5914 && !operand_type_equal (&overlap, &imm32s)
5915 && !operand_type_equal (&overlap, &imm64))
29b0f896 5916 {
4eed87de
AM		 5917 as_bad (_("no instruction mnemonic suffix given; "
5918 "can't determine immediate size"));
29b0f896
AM		 5919 return 0;
5920 }
5921 }
40fb9820 5922 i.types[j] = overlap;
29b0f896 5923
40fb9820
L		 5924 return 1;
5925}
5926
5927static int
5928finalize_imm (void)
5929{
bc0844ae 5930 unsigned int j, n;
29b0f896 5931
bc0844ae
L		 5932 /* Update the first 2 immediate operands. */
5933 n = i.operands > 2 ? 2 : i.operands;
5934 if (n)
5935 {
5936 for (j = 0; j < n; j++)
5937 if (update_imm (j) == 0)
5938 return 0;
40fb9820 5939
bc0844ae
L		 5940 /* The 3rd operand can't be immediate operand. */
5941 gas_assert (operand_type_check (i.types[2], imm) == 0);
5942 }
29b0f896
AM		 5943
5944 return 1;
5945}
5946
c0f3af97
L		 5947static int
5948bad_implicit_operand (int xmm)
5949{
91d6fa6a
NC		 5950 const char *ireg = xmm ? "xmm0" : "ymm0";
5951
c0f3af97
L		 5952 if (intel_syntax)
5953 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5954 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5955 else
5956 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5957 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5958 return 0;
5959}
5960
29b0f896 5961static int
e3bb37b5 5962process_operands (void)
29b0f896
AM		 5963{
5964 /* Default segment register this instruction will use for memory
5965 accesses. 0 means unknown. This is only for optimizing out
5966 unnecessary segment overrides. */
5967 const seg_entry *default_seg = 0;
5968
2426c15f 5969 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5970 {
91d6fa6a
NC		 5971 unsigned int dupl = i.operands;
5972 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5973 unsigned int j;
5974
c0f3af97 5975 /* The destination must be an xmm register. */
9c2799c2 5976 gas_assert (i.reg_operands
91d6fa6a 5977 && MAX_OPERANDS > dupl
7ab9ffdd 5978 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5979
5980 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5981 {
c0f3af97 5982 /* The first operand is implicit and must be xmm0. */
9c2799c2 5983 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5984 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5985 return bad_implicit_operand (1);
5986
8cd7925b 5987 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5988 {
5989 /* Keep xmm0 for instructions with VEX prefix and 3
5990 sources. */
5991 goto duplicate;
5992 }
e2ec9d29 5993 else
c0f3af97
L		 5994 {
5995 /* We remove the first xmm0 and keep the number of
5996 operands unchanged, which in fact duplicates the
5997 destination. */
5998 for (j = 1; j < i.operands; j++)
5999 {
6000 i.op[j - 1] = i.op[j];
6001 i.types[j - 1] = i.types[j];
6002 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6003 }
6004 }
6005 }
6006 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6007 {
91d6fa6a 6008 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6009 && (i.tm.opcode_modifier.vexsources
6010 == VEX3SOURCES));
c0f3af97
L		 6011
6012 /* Add the implicit xmm0 for instructions with VEX prefix
6013 and 3 sources. */
6014 for (j = i.operands; j > 0; j--)
6015 {
6016 i.op[j] = i.op[j - 1];
6017 i.types[j] = i.types[j - 1];
6018 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6019 }
6020 i.op[0].regs
6021 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6022 i.types[0] = regxmm;
c0f3af97
L		 6023 i.tm.operand_types[0] = regxmm;
6024
6025 i.operands += 2;
6026 i.reg_operands += 2;
6027 i.tm.operands += 2;
6028
91d6fa6a 6029 dupl++;
c0f3af97 6030 dest++;
91d6fa6a
NC		 6031 i.op[dupl] = i.op[dest];
6032 i.types[dupl] = i.types[dest];
6033 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6034 }
c0f3af97
L		 6035 else
6036 {
6037duplicate:
6038 i.operands++;
6039 i.reg_operands++;
6040 i.tm.operands++;
6041
91d6fa6a
NC		 6042 i.op[dupl] = i.op[dest];
6043 i.types[dupl] = i.types[dest];
6044 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6045 }
6046
6047 if (i.tm.opcode_modifier.immext)
6048 process_immext ();
6049 }
6050 else if (i.tm.opcode_modifier.firstxmm0)
6051 {
6052 unsigned int j;
6053
43234a1e 6054 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 6055 gas_assert (i.reg_operands
7ab9ffdd 6056 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 6057 || operand_type_equal (&i.types[0], &regymm)
6058 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 6059 if (register_number (i.op[0].regs) != 0)
c0f3af97 6060 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 6061
6062 for (j = 1; j < i.operands; j++)
6063 {
6064 i.op[j - 1] = i.op[j];
6065 i.types[j - 1] = i.types[j];
6066
6067 /* We need to adjust fields in i.tm since they are used by
6068 build_modrm_byte. */
6069 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6070 }
6071
e2ec9d29
L		 6072 i.operands--;
6073 i.reg_operands--;
e2ec9d29
L		 6074 i.tm.operands--;
6075 }
920d2ddc
IT		 6076 else if (i.tm.opcode_modifier.implicitquadgroup)
6077 {
6078 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6079 gas_assert (i.operands >= 2
6080 && (operand_type_equal (&i.types[1], &regxmm)
6081 || operand_type_equal (&i.types[1], &regymm)
6082 || operand_type_equal (&i.types[1], &regzmm)));
6083 unsigned int regnum = register_number (i.op[1].regs);
6084 unsigned int first_reg_in_group = regnum & ~3;
6085 unsigned int last_reg_in_group = first_reg_in_group + 3;
6086 if (regnum != first_reg_in_group) {
6087 as_warn (_("the second source register `%s%s' implicitly denotes"
6088 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6089 register_prefix, i.op[1].regs->reg_name,
6090 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6091 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6092 i.tm.name);
6093 }
6094 }
e2ec9d29
L		 6095 else if (i.tm.opcode_modifier.regkludge)
6096 {
6097 /* The imul $imm, %reg instruction is converted into
6098 imul $imm, %reg, %reg, and the clr %reg instruction
6099 is converted into xor %reg, %reg. */
6100
6101 unsigned int first_reg_op;
6102
6103 if (operand_type_check (i.types[0], reg))
6104 first_reg_op = 0;
6105 else
6106 first_reg_op = 1;
6107 /* Pretend we saw the extra register operand. */
9c2799c2 6108 gas_assert (i.reg_operands == 1
7ab9ffdd 6109 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6110 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6111 i.types[first_reg_op + 1] = i.types[first_reg_op];
6112 i.operands++;
6113 i.reg_operands++;
29b0f896
AM		 6114 }
6115
40fb9820 6116 if (i.tm.opcode_modifier.shortform)
29b0f896 6117 {
40fb9820
L		 6118 if (i.types[0].bitfield.sreg2
6119 || i.types[0].bitfield.sreg3)
29b0f896 6120 {
4eed87de
AM		 6121 if (i.tm.base_opcode == POP_SEG_SHORT
6122 && i.op[0].regs->reg_num == 1)
29b0f896 6123 {
a87af027 6124 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6125 return 0;
29b0f896 6126 }
4eed87de
AM		 6127 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6128 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6129 i.rex |= REX_B;
4eed87de
AM		 6130 }
6131 else
6132 {
7ab9ffdd 6133 /* The register or float register operand is in operand
85f10a01 6134 0 or 1. */
40fb9820 6135 unsigned int op;
7ab9ffdd
L		 6136
6137 if (i.types[0].bitfield.floatreg
6138 || operand_type_check (i.types[0], reg))
6139 op = 0;
6140 else
6141 op = 1;
4eed87de
AM		 6142 /* Register goes in low 3 bits of opcode. */
6143 i.tm.base_opcode |= i.op[op].regs->reg_num;
6144 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6145 i.rex |= REX_B;
40fb9820 6146 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6147 {
4eed87de
AM		 6148 /* Warn about some common errors, but press on regardless.
6149 The first case can be generated by gcc (<= 2.8.1). */
6150 if (i.operands == 2)
6151 {
6152 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6153 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6154 register_prefix, i.op[!intel_syntax].regs->reg_name,
6155 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6156 }
6157 else
6158 {
6159 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6160 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6161 register_prefix, i.op[0].regs->reg_name);
4eed87de 6162 }
29b0f896
AM		 6163 }
6164 }
6165 }
40fb9820 6166 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6167 {
6168 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6169 must be put into the modrm byte). Now, we make the modrm and
6170 index base bytes based on all the info we've collected. */
29b0f896
AM		 6171
6172 default_seg = build_modrm_byte ();
6173 }
8a2ed489 6174 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6175 {
6176 default_seg = &ds;
6177 }
40fb9820 6178 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6179 {
6180 /* For the string instructions that allow a segment override
6181 on one of their operands, the default segment is ds. */
6182 default_seg = &ds;
6183 }
6184
75178d9d
L		 6185 if (i.tm.base_opcode == 0x8d /* lea */
6186 && i.seg[0]
6187 && !quiet_warnings)
30123838 6188 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6189
6190 /* If a segment was explicitly specified, and the specified segment
6191 is not the default, use an opcode prefix to select it. If we
6192 never figured out what the default segment is, then default_seg
6193 will be zero at this point, and the specified segment prefix will
6194 always be used. */
29b0f896
AM		 6195 if ((i.seg[0]) && (i.seg[0] != default_seg))
6196 {
6197 if (!add_prefix (i.seg[0]->seg_prefix))
6198 return 0;
6199 }
6200 return 1;
6201}
6202
6203static const seg_entry *
e3bb37b5 6204build_modrm_byte (void)
29b0f896
AM		 6205{
6206 const seg_entry *default_seg = 0;
c0f3af97 6207 unsigned int source, dest;
8cd7925b 6208 int vex_3_sources;
c0f3af97
L		 6209
6210 /* The first operand of instructions with VEX prefix and 3 sources
6211 must be VEX_Imm4. */
8cd7925b 6212 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6213 if (vex_3_sources)
6214 {
91d6fa6a 6215 unsigned int nds, reg_slot;
4c2c6516 6216 expressionS *exp;
c0f3af97 6217
922d8de8 6218 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6219 && i.tm.opcode_modifier.immext)
6220 {
6221 dest = i.operands - 2;
6222 gas_assert (dest == 3);
6223 }
922d8de8 6224 else
a683cc34 6225 dest = i.operands - 1;
c0f3af97 6226 nds = dest - 1;
922d8de8 6227
a683cc34
SP		 6228 /* There are 2 kinds of instructions:
6229 1. 5 operands: 4 register operands or 3 register operands
6230 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6231 VexW0 or VexW1. The destination must be either XMM, YMM or
6232 ZMM register.
a683cc34
SP		 6233 2. 4 operands: 4 register operands or 3 register operands
6234 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6235 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6236 || (i.reg_operands == 3 && i.mem_operands == 1))
6237 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6238 && (i.tm.opcode_modifier.veximmext
6239 || (i.imm_operands == 1
6240 && i.types[0].bitfield.vec_imm4
6241 && (i.tm.opcode_modifier.vexw == VEXW0
6242 || i.tm.opcode_modifier.vexw == VEXW1)
6243 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6244 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6245 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6246
6247 if (i.imm_operands == 0)
6248 {
6249 /* When there is no immediate operand, generate an 8bit
6250 immediate operand to encode the first operand. */
6251 exp = &im_expressions[i.imm_operands++];
6252 i.op[i.operands].imms = exp;
6253 i.types[i.operands] = imm8;
6254 i.operands++;
6255 /* If VexW1 is set, the first operand is the source and
6256 the second operand is encoded in the immediate operand. */
6257 if (i.tm.opcode_modifier.vexw == VEXW1)
6258 {
6259 source = 0;
6260 reg_slot = 1;
6261 }
6262 else
6263 {
6264 source = 1;
6265 reg_slot = 0;
6266 }
6267
6268 /* FMA swaps REG and NDS. */
6269 if (i.tm.cpu_flags.bitfield.cpufma)
6270 {
6271 unsigned int tmp;
6272 tmp = reg_slot;
6273 reg_slot = nds;
6274 nds = tmp;
6275 }
6276
24981e7b
L		 6277 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6278 &regxmm)
a683cc34 6279 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6280 &regymm)
6281 || operand_type_equal (&i.tm.operand_types[reg_slot],
6282 &regzmm));
a683cc34 6283 exp->X_op = O_constant;
4c692bc7 6284 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6285 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6286 }
922d8de8 6287 else
a683cc34
SP		 6288 {
6289 unsigned int imm_slot;
6290
6291 if (i.tm.opcode_modifier.vexw == VEXW0)
6292 {
6293 /* If VexW0 is set, the third operand is the source and
6294 the second operand is encoded in the immediate
6295 operand. */
6296 source = 2;
6297 reg_slot = 1;
6298 }
6299 else
6300 {
6301 /* VexW1 is set, the second operand is the source and
6302 the third operand is encoded in the immediate
6303 operand. */
6304 source = 1;
6305 reg_slot = 2;
6306 }
6307
6308 if (i.tm.opcode_modifier.immext)
6309 {
33eaf5de 6310 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6311 operand. */
6312 imm_slot = i.operands - 1;
6313 source--;
6314 reg_slot--;
6315 }
6316 else
6317 {
6318 imm_slot = 0;
6319
6320 /* Turn on Imm8 so that output_imm will generate it. */
6321 i.types[imm_slot].bitfield.imm8 = 1;
6322 }
6323
24981e7b
L		 6324 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6325 &regxmm)
6326 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6327 &regymm)
6328 || operand_type_equal (&i.tm.operand_types[reg_slot],
6329 &regzmm));
a683cc34 6330 i.op[imm_slot].imms->X_add_number
4c692bc7 6331 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6332 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6333 }
6334
6335 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6336 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6337 &regymm)
6338 || operand_type_equal (&i.tm.operand_types[nds],
6339 &regzmm));
dae39acc 6340 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6341 }
6342 else
6343 source = dest = 0;
29b0f896
AM		 6344
6345 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6346 implicit registers do not count. If there are 3 register
6347 operands, it must be a instruction with VexNDS. For a
6348 instruction with VexNDD, the destination register is encoded
6349 in VEX prefix. If there are 4 register operands, it must be
6350 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6351 if (i.mem_operands == 0
6352 && ((i.reg_operands == 2
2426c15f 6353 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6354 || (i.reg_operands == 3
2426c15f 6355 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6356 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6357 {
cab737b9
L		 6358 switch (i.operands)
6359 {
6360 case 2:
6361 source = 0;
6362 break;
6363 case 3:
c81128dc
L		 6364 /* When there are 3 operands, one of them may be immediate,
6365 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6366 the first operand must be shift count register (cl) or it
6367 is an instruction with VexNDS. */
9c2799c2 6368 gas_assert (i.imm_operands == 1
7ab9ffdd 6369 || (i.imm_operands == 0
2426c15f 6370 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6371 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6372 if (operand_type_check (i.types[0], imm)
6373 || i.types[0].bitfield.shiftcount)
6374 source = 1;
6375 else
6376 source = 0;
cab737b9
L		 6377 break;
6378 case 4:
368d64cc
L		 6379 /* When there are 4 operands, the first two must be 8bit
6380 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6381 one.
6382
6383 For instructions with VexNDS, if the first operand
6384 an imm8, the source operand is the 2nd one. If the last
6385 operand is imm8, the source operand is the first one. */
9c2799c2 6386 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6387 && i.types[0].bitfield.imm8
6388 && i.types[1].bitfield.imm8)
2426c15f 6389 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6390 && i.imm_operands == 1
6391 && (i.types[0].bitfield.imm8
43234a1e
L		 6392 || i.types[i.operands - 1].bitfield.imm8
6393 || i.rounding)));
9f2670f2
L		 6394 if (i.imm_operands == 2)
6395 source = 2;
6396 else
c0f3af97
L		 6397 {
6398 if (i.types[0].bitfield.imm8)
6399 source = 1;
6400 else
6401 source = 0;
6402 }
c0f3af97
L		 6403 break;
6404 case 5:
43234a1e
L		 6405 if (i.tm.opcode_modifier.evex)
6406 {
6407 /* For EVEX instructions, when there are 5 operands, the
6408 first one must be immediate operand. If the second one
6409 is immediate operand, the source operand is the 3th
6410 one. If the last one is immediate operand, the source
6411 operand is the 2nd one. */
6412 gas_assert (i.imm_operands == 2
6413 && i.tm.opcode_modifier.sae
6414 && operand_type_check (i.types[0], imm));
6415 if (operand_type_check (i.types[1], imm))
6416 source = 2;
6417 else if (operand_type_check (i.types[4], imm))
6418 source = 1;
6419 else
6420 abort ();
6421 }
cab737b9
L		 6422 break;
6423 default:
6424 abort ();
6425 }
6426
c0f3af97
L		 6427 if (!vex_3_sources)
6428 {
6429 dest = source + 1;
6430
43234a1e
L		 6431 /* RC/SAE operand could be between DEST and SRC. That happens
6432 when one operand is GPR and the other one is XMM/YMM/ZMM
6433 register. */
6434 if (i.rounding && i.rounding->operand == (int) dest)
6435 dest++;
6436
2426c15f 6437 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6438 {
43234a1e
L		 6439 /* For instructions with VexNDS, the register-only source
6440 operand must be 32/64bit integer, XMM, YMM or ZMM
6441 register. It is encoded in VEX prefix. We need to
6442 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6443
6444 i386_operand_type op;
6445 unsigned int vvvv;
6446
6447 /* Check register-only source operand when two source
6448 operands are swapped. */
6449 if (!i.tm.operand_types[source].bitfield.baseindex
6450 && i.tm.operand_types[dest].bitfield.baseindex)
6451 {
6452 vvvv = source;
6453 source = dest;
6454 }
6455 else
6456 vvvv = dest;
6457
6458 op = i.tm.operand_types[vvvv];
fa99fab2 6459 op.bitfield.regmem = 0;
c0f3af97 6460 if ((dest + 1) >= i.operands
ac4eb736
AM		 6461 || (!op.bitfield.reg32
6462 && op.bitfield.reg64
f12dc422 6463 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6464 && !operand_type_equal (&op, &regymm)
6465 && !operand_type_equal (&op, &regzmm)
6466 && !operand_type_equal (&op, &regmask)))
c0f3af97 6467 abort ();
f12dc422 6468 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6469 dest++;
6470 }
6471 }
29b0f896
AM		 6472
6473 i.rm.mode = 3;
6474 /* One of the register operands will be encoded in the i.tm.reg
6475 field, the other in the combined i.tm.mode and i.tm.regmem
6476 fields. If no form of this instruction supports a memory
6477 destination operand, then we assume the source operand may
6478 sometimes be a memory operand and so we need to store the
6479 destination in the i.rm.reg field. */
40fb9820
L		 6480 if (!i.tm.operand_types[dest].bitfield.regmem
6481 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6482 {
6483 i.rm.reg = i.op[dest].regs->reg_num;
6484 i.rm.regmem = i.op[source].regs->reg_num;
6485 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6486 i.rex |= REX_R;
43234a1e
L		 6487 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6488 i.vrex |= REX_R;
29b0f896 6489 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6490 i.rex |= REX_B;
43234a1e
L		 6491 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6492 i.vrex |= REX_B;
29b0f896
AM		 6493 }
6494 else
6495 {
6496 i.rm.reg = i.op[source].regs->reg_num;
6497 i.rm.regmem = i.op[dest].regs->reg_num;
6498 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6499 i.rex |= REX_B;
43234a1e
L		 6500 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6501 i.vrex |= REX_B;
29b0f896 6502 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6503 i.rex |= REX_R;
43234a1e
L		 6504 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6505 i.vrex |= REX_R;
29b0f896 6506 }
161a04f6 6507 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6508 {
40fb9820
L		 6509 if (!i.types[0].bitfield.control
6510 && !i.types[1].bitfield.control)
c4a530c5 6511 abort ();
161a04f6 6512 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6513 add_prefix (LOCK_PREFIX_OPCODE);
6514 }
29b0f896
AM		 6515 }
6516 else
6517 { /* If it's not 2 reg operands... */
c0f3af97
L		 6518 unsigned int mem;
6519
29b0f896
AM		 6520 if (i.mem_operands)
6521 {
6522 unsigned int fake_zero_displacement = 0;
99018f42 6523 unsigned int op;
4eed87de 6524
7ab9ffdd
L		 6525 for (op = 0; op < i.operands; op++)
6526 if (operand_type_check (i.types[op], anymem))
6527 break;
7ab9ffdd 6528 gas_assert (op < i.operands);
29b0f896 6529
6c30d220
L		 6530 if (i.tm.opcode_modifier.vecsib)
6531 {
6532 if (i.index_reg->reg_num == RegEiz
6533 || i.index_reg->reg_num == RegRiz)
6534 abort ();
6535
6536 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6537 if (!i.base_reg)
6538 {
6539 i.sib.base = NO_BASE_REGISTER;
6540 i.sib.scale = i.log2_scale_factor;
6541 i.types[op].bitfield.disp8 = 0;
6542 i.types[op].bitfield.disp16 = 0;
6543 i.types[op].bitfield.disp64 = 0;
43083a50 6544 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6545 {
6546 /* Must be 32 bit */
6547 i.types[op].bitfield.disp32 = 1;
6548 i.types[op].bitfield.disp32s = 0;
6549 }
6550 else
6551 {
6552 i.types[op].bitfield.disp32 = 0;
6553 i.types[op].bitfield.disp32s = 1;
6554 }
6555 }
6556 i.sib.index = i.index_reg->reg_num;
6557 if ((i.index_reg->reg_flags & RegRex) != 0)
6558 i.rex |= REX_X;
43234a1e
L		 6559 if ((i.index_reg->reg_flags & RegVRex) != 0)
6560 i.vrex |= REX_X;
6c30d220
L		 6561 }
6562
29b0f896
AM		 6563 default_seg = &ds;
6564
6565 if (i.base_reg == 0)
6566 {
6567 i.rm.mode = 0;
6568 if (!i.disp_operands)
9bb129e8 6569 fake_zero_displacement = 1;
29b0f896
AM		 6570 if (i.index_reg == 0)
6571 {
6c30d220 6572 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6573 /* Operand is just <disp> */
20f0a1fc 6574 if (flag_code == CODE_64BIT)
29b0f896
AM		 6575 {
6576 /* 64bit mode overwrites the 32bit absolute
6577 addressing by RIP relative addressing and
6578 absolute addressing is encoded by one of the
6579 redundant SIB forms. */
6580 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6581 i.sib.base = NO_BASE_REGISTER;
6582 i.sib.index = NO_INDEX_REGISTER;
fc225355 6583 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6584 ? disp32s : disp32);
20f0a1fc 6585 }
fc225355
L		 6586 else if ((flag_code == CODE_16BIT)
6587 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6588 {
6589 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6590 i.types[op] = disp16;
20f0a1fc
NC		 6591 }
6592 else
6593 {
6594 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6595 i.types[op] = disp32;
29b0f896
AM		 6596 }
6597 }
6c30d220 6598 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6599 {
6c30d220 6600 /* !i.base_reg && i.index_reg */
db51cc60
L		 6601 if (i.index_reg->reg_num == RegEiz
6602 || i.index_reg->reg_num == RegRiz)
6603 i.sib.index = NO_INDEX_REGISTER;
6604 else
6605 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6606 i.sib.base = NO_BASE_REGISTER;
6607 i.sib.scale = i.log2_scale_factor;
6608 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6609 i.types[op].bitfield.disp8 = 0;
6610 i.types[op].bitfield.disp16 = 0;
6611 i.types[op].bitfield.disp64 = 0;
43083a50 6612 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6613 {
6614 /* Must be 32 bit */
6615 i.types[op].bitfield.disp32 = 1;
6616 i.types[op].bitfield.disp32s = 0;
6617 }
29b0f896 6618 else
40fb9820
L		 6619 {
6620 i.types[op].bitfield.disp32 = 0;
6621 i.types[op].bitfield.disp32s = 1;
6622 }
29b0f896 6623 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6624 i.rex |= REX_X;
29b0f896
AM		 6625 }
6626 }
6627 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6628 else if (i.base_reg->reg_num == RegRip ||
6629 i.base_reg->reg_num == RegEip)
29b0f896 6630 {
6c30d220 6631 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6632 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6633 i.types[op].bitfield.disp8 = 0;
6634 i.types[op].bitfield.disp16 = 0;
6635 i.types[op].bitfield.disp32 = 0;
6636 i.types[op].bitfield.disp32s = 1;
6637 i.types[op].bitfield.disp64 = 0;
71903a11 6638 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6639 if (! i.disp_operands)
6640 fake_zero_displacement = 1;
29b0f896 6641 }
40fb9820 6642 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6643 {
6c30d220 6644 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6645 switch (i.base_reg->reg_num)
6646 {
6647 case 3: /* (%bx) */
6648 if (i.index_reg == 0)
6649 i.rm.regmem = 7;
6650 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6651 i.rm.regmem = i.index_reg->reg_num - 6;
6652 break;
6653 case 5: /* (%bp) */
6654 default_seg = &ss;
6655 if (i.index_reg == 0)
6656 {
6657 i.rm.regmem = 6;
40fb9820 6658 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6659 {
6660 /* fake (%bp) into 0(%bp) */
b5014f7a 6661 i.types[op].bitfield.disp8 = 1;
252b5132 6662 fake_zero_displacement = 1;
29b0f896
AM		 6663 }
6664 }
6665 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6666 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6667 break;
6668 default: /* (%si) -> 4 or (%di) -> 5 */
6669 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6670 }
6671 i.rm.mode = mode_from_disp_size (i.types[op]);
6672 }
6673 else /* i.base_reg and 32/64 bit mode */
6674 {
6675 if (flag_code == CODE_64BIT
40fb9820
L		 6676 && operand_type_check (i.types[op], disp))
6677 {
6678 i386_operand_type temp;
0dfbf9d7 6679 operand_type_set (&temp, 0);
40fb9820
L		 6680 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6681 i.types[op] = temp;
6682 if (i.prefix[ADDR_PREFIX] == 0)
6683 i.types[op].bitfield.disp32s = 1;
6684 else
6685 i.types[op].bitfield.disp32 = 1;
6686 }
20f0a1fc 6687
6c30d220
L		 6688 if (!i.tm.opcode_modifier.vecsib)
6689 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6690 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6691 i.rex |= REX_B;
29b0f896
AM		 6692 i.sib.base = i.base_reg->reg_num;
6693 /* x86-64 ignores REX prefix bit here to avoid decoder
6694 complications. */
848930b2
JB		 6695 if (!(i.base_reg->reg_flags & RegRex)
6696 && (i.base_reg->reg_num == EBP_REG_NUM
6697 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6698 default_seg = &ss;
848930b2 6699 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6700 {
848930b2 6701 fake_zero_displacement = 1;
b5014f7a 6702 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6703 }
6704 i.sib.scale = i.log2_scale_factor;
6705 if (i.index_reg == 0)
6706 {
6c30d220 6707 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6708 /* <disp>(%esp) becomes two byte modrm with no index
6709 register. We've already stored the code for esp
6710 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6711 Any base register besides %esp will not use the
6712 extra modrm byte. */
6713 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6714 }
6c30d220 6715 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6716 {
db51cc60
L		 6717 if (i.index_reg->reg_num == RegEiz
6718 || i.index_reg->reg_num == RegRiz)
6719 i.sib.index = NO_INDEX_REGISTER;
6720 else
6721 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6722 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6723 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6724 i.rex |= REX_X;
29b0f896 6725 }
67a4f2b7
AO		 6726
6727 if (i.disp_operands
6728 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6729 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6730 i.rm.mode = 0;
6731 else
a501d77e
L		 6732 {
6733 if (!fake_zero_displacement
6734 && !i.disp_operands
6735 && i.disp_encoding)
6736 {
6737 fake_zero_displacement = 1;
6738 if (i.disp_encoding == disp_encoding_8bit)
6739 i.types[op].bitfield.disp8 = 1;
6740 else
6741 i.types[op].bitfield.disp32 = 1;
6742 }
6743 i.rm.mode = mode_from_disp_size (i.types[op]);
6744 }
29b0f896 6745 }
252b5132 6746
29b0f896
AM		 6747 if (fake_zero_displacement)
6748 {
6749 /* Fakes a zero displacement assuming that i.types[op]
6750 holds the correct displacement size. */
6751 expressionS *exp;
6752
9c2799c2 6753 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6754 exp = &disp_expressions[i.disp_operands++];
6755 i.op[op].disps = exp;
6756 exp->X_op = O_constant;
6757 exp->X_add_number = 0;
6758 exp->X_add_symbol = (symbolS *) 0;
6759 exp->X_op_symbol = (symbolS *) 0;
6760 }
c0f3af97
L		 6761
6762 mem = op;
29b0f896 6763 }
c0f3af97
L		 6764 else
6765 mem = ~0;
252b5132 6766
8c43a48b 6767 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6768 {
6769 if (operand_type_check (i.types[0], imm))
6770 i.vex.register_specifier = NULL;
6771 else
6772 {
6773 /* VEX.vvvv encodes one of the sources when the first
6774 operand is not an immediate. */
1ef99a7b 6775 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6776 i.vex.register_specifier = i.op[0].regs;
6777 else
6778 i.vex.register_specifier = i.op[1].regs;
6779 }
6780
6781 /* Destination is a XMM register encoded in the ModRM.reg
6782 and VEX.R bit. */
6783 i.rm.reg = i.op[2].regs->reg_num;
6784 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6785 i.rex |= REX_R;
6786
6787 /* ModRM.rm and VEX.B encodes the other source. */
6788 if (!i.mem_operands)
6789 {
6790 i.rm.mode = 3;
6791
1ef99a7b 6792 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6793 i.rm.regmem = i.op[1].regs->reg_num;
6794 else
6795 i.rm.regmem = i.op[0].regs->reg_num;
6796
6797 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6798 i.rex |= REX_B;
6799 }
6800 }
2426c15f 6801 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6802 {
6803 i.vex.register_specifier = i.op[2].regs;
6804 if (!i.mem_operands)
6805 {
6806 i.rm.mode = 3;
6807 i.rm.regmem = i.op[1].regs->reg_num;
6808 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6809 i.rex |= REX_B;
6810 }
6811 }
29b0f896
AM		 6812 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6813 (if any) based on i.tm.extension_opcode. Again, we must be
6814 careful to make sure that segment/control/debug/test/MMX
6815 registers are coded into the i.rm.reg field. */
f88c9eb0 6816 else if (i.reg_operands)
29b0f896 6817 {
99018f42 6818 unsigned int op;
7ab9ffdd
L		 6819 unsigned int vex_reg = ~0;
6820
6821 for (op = 0; op < i.operands; op++)
6822 if (i.types[op].bitfield.reg8
6823 || i.types[op].bitfield.reg16
6824 || i.types[op].bitfield.reg32
6825 || i.types[op].bitfield.reg64
6826 || i.types[op].bitfield.regmmx
6827 || i.types[op].bitfield.regxmm
6828 || i.types[op].bitfield.regymm
7e8b059b 6829 || i.types[op].bitfield.regbnd
43234a1e
L		 6830 || i.types[op].bitfield.regzmm
6831 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6832 || i.types[op].bitfield.sreg2
6833 || i.types[op].bitfield.sreg3
6834 || i.types[op].bitfield.control
6835 || i.types[op].bitfield.debug
6836 || i.types[op].bitfield.test)
6837 break;
c0209578 6838
7ab9ffdd
L		 6839 if (vex_3_sources)
6840 op = dest;
2426c15f 6841 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6842 {
6843 /* For instructions with VexNDS, the register-only
6844 source operand is encoded in VEX prefix. */
6845 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6846
7ab9ffdd 6847 if (op > mem)
c0f3af97 6848 {
7ab9ffdd
L		 6849 vex_reg = op++;
6850 gas_assert (op < i.operands);
c0f3af97
L		 6851 }
6852 else
c0f3af97 6853 {
f12dc422
L		 6854 /* Check register-only source operand when two source
6855 operands are swapped. */
6856 if (!i.tm.operand_types[op].bitfield.baseindex
6857 && i.tm.operand_types[op + 1].bitfield.baseindex)
6858 {
6859 vex_reg = op;
6860 op += 2;
6861 gas_assert (mem == (vex_reg + 1)
6862 && op < i.operands);
6863 }
6864 else
6865 {
6866 vex_reg = op + 1;
6867 gas_assert (vex_reg < i.operands);
6868 }
c0f3af97 6869 }
7ab9ffdd 6870 }
2426c15f 6871 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6872 {
f12dc422 6873 /* For instructions with VexNDD, the register destination
7ab9ffdd 6874 is encoded in VEX prefix. */
f12dc422
L		 6875 if (i.mem_operands == 0)
6876 {
6877 /* There is no memory operand. */
6878 gas_assert ((op + 2) == i.operands);
6879 vex_reg = op + 1;
6880 }
6881 else
8d63c93e 6882 {
f12dc422
L		 6883 /* There are only 2 operands. */
6884 gas_assert (op < 2 && i.operands == 2);
6885 vex_reg = 1;
6886 }
7ab9ffdd
L		 6887 }
6888 else
6889 gas_assert (op < i.operands);
99018f42 6890
7ab9ffdd
L		 6891 if (vex_reg != (unsigned int) ~0)
6892 {
f12dc422 6893 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6894
f12dc422
L		 6895 if (type->bitfield.reg32 != 1
6896 && type->bitfield.reg64 != 1
6897 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6898 && !operand_type_equal (type, &regymm)
6899 && !operand_type_equal (type, &regzmm)
6900 && !operand_type_equal (type, &regmask))
7ab9ffdd 6901 abort ();
f88c9eb0 6902
7ab9ffdd
L		 6903 i.vex.register_specifier = i.op[vex_reg].regs;
6904 }
6905
1b9f0c97
L		 6906 /* Don't set OP operand twice. */
6907 if (vex_reg != op)
7ab9ffdd 6908 {
1b9f0c97
L		 6909 /* If there is an extension opcode to put here, the
6910 register number must be put into the regmem field. */
6911 if (i.tm.extension_opcode != None)
6912 {
6913 i.rm.regmem = i.op[op].regs->reg_num;
6914 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6915 i.rex |= REX_B;
43234a1e
L		 6916 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6917 i.vrex |= REX_B;
1b9f0c97
L		 6918 }
6919 else
6920 {
6921 i.rm.reg = i.op[op].regs->reg_num;
6922 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6923 i.rex |= REX_R;
43234a1e
L		 6924 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6925 i.vrex |= REX_R;
1b9f0c97 6926 }
7ab9ffdd 6927 }
252b5132 6928
29b0f896
AM		 6929 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6930 must set it to 3 to indicate this is a register operand
6931 in the regmem field. */
6932 if (!i.mem_operands)
6933 i.rm.mode = 3;
6934 }
252b5132 6935
29b0f896 6936 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6937 if (i.tm.extension_opcode != None)
29b0f896
AM		 6938 i.rm.reg = i.tm.extension_opcode;
6939 }
6940 return default_seg;
6941}
252b5132 6942
29b0f896 6943static void
e3bb37b5 6944output_branch (void)
29b0f896
AM		 6945{
6946 char *p;
f8a5c266 6947 int size;
29b0f896
AM		 6948 int code16;
6949 int prefix;
6950 relax_substateT subtype;
6951 symbolS *sym;
6952 offsetT off;
6953
f8a5c266 6954 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6955 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6956
6957 prefix = 0;
6958 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6959 {
29b0f896
AM		 6960 prefix = 1;
6961 i.prefixes -= 1;
6962 code16 ^= CODE16;
252b5132 6963 }
29b0f896
AM		 6964 /* Pentium4 branch hints. */
6965 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6966 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6967 {
29b0f896
AM		 6968 prefix++;
6969 i.prefixes--;
6970 }
6971 if (i.prefix[REX_PREFIX] != 0)
6972 {
6973 prefix++;
6974 i.prefixes--;
2f66722d
AM		 6975 }
6976
7e8b059b
L		 6977 /* BND prefixed jump. */
6978 if (i.prefix[BND_PREFIX] != 0)
6979 {
6980 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6981 i.prefixes -= 1;
6982 }
6983
29b0f896
AM		 6984 if (i.prefixes != 0 && !intel_syntax)
6985 as_warn (_("skipping prefixes on this instruction"));
6986
6987 /* It's always a symbol; End frag & setup for relax.
6988 Make sure there is enough room in this frag for the largest
6989 instruction we may generate in md_convert_frag. This is 2
6990 bytes for the opcode and room for the prefix and largest
6991 displacement. */
6992 frag_grow (prefix + 2 + 4);
6993 /* Prefix and 1 opcode byte go in fr_fix. */
6994 p = frag_more (prefix + 1);
6995 if (i.prefix[DATA_PREFIX] != 0)
6996 *p++ = DATA_PREFIX_OPCODE;
6997 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6998 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6999 *p++ = i.prefix[SEG_PREFIX];
7000 if (i.prefix[REX_PREFIX] != 0)
7001 *p++ = i.prefix[REX_PREFIX];
7002 *p = i.tm.base_opcode;
7003
7004 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7005 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7006 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7007 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7008 else
f8a5c266 7009 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7010 subtype |= code16;
3e73aa7c 7011
29b0f896
AM		 7012 sym = i.op[0].disps->X_add_symbol;
7013 off = i.op[0].disps->X_add_number;
3e73aa7c 7014
29b0f896
AM		 7015 if (i.op[0].disps->X_op != O_constant
7016 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7017 {
29b0f896
AM		 7018 /* Handle complex expressions. */
7019 sym = make_expr_symbol (i.op[0].disps);
7020 off = 0;
7021 }
3e73aa7c 7022
29b0f896
AM		 7023 /* 1 possible extra opcode + 4 byte displacement go in var part.
7024 Pass reloc in fr_var. */
d258b828 7025 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7026}
3e73aa7c 7027
29b0f896 7028static void
e3bb37b5 7029output_jump (void)
29b0f896
AM		 7030{
7031 char *p;
7032 int size;
3e02c1cc 7033 fixS *fixP;
29b0f896 7034
40fb9820 7035 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7036 {
7037 /* This is a loop or jecxz type instruction. */
7038 size = 1;
7039 if (i.prefix[ADDR_PREFIX] != 0)
7040 {
7041 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7042 i.prefixes -= 1;
7043 }
7044 /* Pentium4 branch hints. */
7045 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7046 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7047 {
7048 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7049 i.prefixes--;
3e73aa7c
JH		 7050 }
7051 }
29b0f896
AM		 7052 else
7053 {
7054 int code16;
3e73aa7c 7055
29b0f896
AM		 7056 code16 = 0;
7057 if (flag_code == CODE_16BIT)
7058 code16 = CODE16;
3e73aa7c 7059
29b0f896
AM		 7060 if (i.prefix[DATA_PREFIX] != 0)
7061 {
7062 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7063 i.prefixes -= 1;
7064 code16 ^= CODE16;
7065 }
252b5132 7066
29b0f896
AM		 7067 size = 4;
7068 if (code16)
7069 size = 2;
7070 }
9fcc94b6 7071
29b0f896
AM		 7072 if (i.prefix[REX_PREFIX] != 0)
7073 {
7074 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7075 i.prefixes -= 1;
7076 }
252b5132 7077
7e8b059b
L		 7078 /* BND prefixed jump. */
7079 if (i.prefix[BND_PREFIX] != 0)
7080 {
7081 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7082 i.prefixes -= 1;
7083 }
7084
29b0f896
AM		 7085 if (i.prefixes != 0 && !intel_syntax)
7086 as_warn (_("skipping prefixes on this instruction"));
e0890092 7087
42164a71
L		 7088 p = frag_more (i.tm.opcode_length + size);
7089 switch (i.tm.opcode_length)
7090 {
7091 case 2:
7092 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7093 /* Fall through. */
42164a71
L		 7094 case 1:
7095 *p++ = i.tm.base_opcode;
7096 break;
7097 default:
7098 abort ();
7099 }
e0890092 7100
3e02c1cc 7101 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7102 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7103
7104 /* All jumps handled here are signed, but don't use a signed limit
7105 check for 32 and 16 bit jumps as we want to allow wrap around at
7106 4G and 64k respectively. */
7107 if (size == 1)
7108 fixP->fx_signed = 1;
29b0f896 7109}
e0890092 7110
29b0f896 7111static void
e3bb37b5 7112output_interseg_jump (void)
29b0f896
AM		 7113{
7114 char *p;
7115 int size;
7116 int prefix;
7117 int code16;
252b5132 7118
29b0f896
AM		 7119 code16 = 0;
7120 if (flag_code == CODE_16BIT)
7121 code16 = CODE16;
a217f122 7122
29b0f896
AM		 7123 prefix = 0;
7124 if (i.prefix[DATA_PREFIX] != 0)
7125 {
7126 prefix = 1;
7127 i.prefixes -= 1;
7128 code16 ^= CODE16;
7129 }
7130 if (i.prefix[REX_PREFIX] != 0)
7131 {
7132 prefix++;
7133 i.prefixes -= 1;
7134 }
252b5132 7135
29b0f896
AM		 7136 size = 4;
7137 if (code16)
7138 size = 2;
252b5132 7139
29b0f896
AM		 7140 if (i.prefixes != 0 && !intel_syntax)
7141 as_warn (_("skipping prefixes on this instruction"));
252b5132 7142
29b0f896
AM		 7143 /* 1 opcode; 2 segment; offset */
7144 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7145
29b0f896
AM		 7146 if (i.prefix[DATA_PREFIX] != 0)
7147 *p++ = DATA_PREFIX_OPCODE;
252b5132 7148
29b0f896
AM		 7149 if (i.prefix[REX_PREFIX] != 0)
7150 *p++ = i.prefix[REX_PREFIX];
252b5132 7151
29b0f896
AM		 7152 *p++ = i.tm.base_opcode;
7153 if (i.op[1].imms->X_op == O_constant)
7154 {
7155 offsetT n = i.op[1].imms->X_add_number;
252b5132 7156
29b0f896
AM		 7157 if (size == 2
7158 && !fits_in_unsigned_word (n)
7159 && !fits_in_signed_word (n))
7160 {
7161 as_bad (_("16-bit jump out of range"));
7162 return;
7163 }
7164 md_number_to_chars (p, n, size);
7165 }
7166 else
7167 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7168 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7169 if (i.op[0].imms->X_op != O_constant)
7170 as_bad (_("can't handle non absolute segment in `%s'"),
7171 i.tm.name);
7172 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7173}
a217f122 7174
29b0f896 7175static void
e3bb37b5 7176output_insn (void)
29b0f896 7177{
2bbd9c25
JJ		 7178 fragS *insn_start_frag;
7179 offsetT insn_start_off;
7180
29b0f896
AM		 7181 /* Tie dwarf2 debug info to the address at the start of the insn.
7182 We can't do this after the insn has been output as the current
7183 frag may have been closed off. eg. by frag_var. */
7184 dwarf2_emit_insn (0);
7185
2bbd9c25
JJ		 7186 insn_start_frag = frag_now;
7187 insn_start_off = frag_now_fix ();
7188
29b0f896 7189 /* Output jumps. */
40fb9820 7190 if (i.tm.opcode_modifier.jump)
29b0f896 7191 output_branch ();
40fb9820
L		 7192 else if (i.tm.opcode_modifier.jumpbyte
7193 || i.tm.opcode_modifier.jumpdword)
29b0f896 7194 output_jump ();
40fb9820 7195 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7196 output_interseg_jump ();
7197 else
7198 {
7199 /* Output normal instructions here. */
7200 char *p;
7201 unsigned char *q;
47465058 7202 unsigned int j;
331d2d0d 7203 unsigned int prefix;
4dffcebc 7204
e4e00185
AS		 7205 if (avoid_fence
7206 && i.tm.base_opcode == 0xfae
7207 && i.operands == 1
7208 && i.imm_operands == 1
7209 && (i.op[0].imms->X_add_number == 0xe8
7210 || i.op[0].imms->X_add_number == 0xf0
7211 || i.op[0].imms->X_add_number == 0xf8))
7212 {
7213 /* Encode lfence, mfence, and sfence as
7214 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7215 offsetT val = 0x240483f0ULL;
7216 p = frag_more (5);
7217 md_number_to_chars (p, val, 5);
7218 return;
7219 }
7220
d022bddd
IT		 7221 /* Some processors fail on LOCK prefix. This options makes
7222 assembler ignore LOCK prefix and serves as a workaround. */
7223 if (omit_lock_prefix)
7224 {
7225 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7226 return;
7227 i.prefix[LOCK_PREFIX] = 0;
7228 }
7229
43234a1e
L		 7230 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7231 don't need the explicit prefix. */
7232 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7233 {
c0f3af97 7234 switch (i.tm.opcode_length)
bc4bd9ab 7235 {
c0f3af97
L		 7236 case 3:
7237 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7238 {
c0f3af97
L		 7239 prefix = (i.tm.base_opcode >> 24) & 0xff;
7240 goto check_prefix;
7241 }
7242 break;
7243 case 2:
7244 if ((i.tm.base_opcode & 0xff0000) != 0)
7245 {
7246 prefix = (i.tm.base_opcode >> 16) & 0xff;
7247 if (i.tm.cpu_flags.bitfield.cpupadlock)
7248 {
4dffcebc 7249check_prefix:
c0f3af97 7250 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7251 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7252 != REPE_PREFIX_OPCODE))
7253 add_prefix (prefix);
7254 }
7255 else
4dffcebc
L		 7256 add_prefix (prefix);
7257 }
c0f3af97
L		 7258 break;
7259 case 1:
7260 break;
7261 default:
7262 abort ();
bc4bd9ab 7263 }
c0f3af97 7264
6d19a37a 7265#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7266 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7267 R_X86_64_GOTTPOFF relocation so that linker can safely
7268 perform IE->LE optimization. */
7269 if (x86_elf_abi == X86_64_X32_ABI
7270 && i.operands == 2
7271 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7272 && i.prefix[REX_PREFIX] == 0)
7273 add_prefix (REX_OPCODE);
6d19a37a 7274#endif
cf61b747 7275
c0f3af97
L		 7276 /* The prefix bytes. */
7277 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7278 if (*q)
7279 FRAG_APPEND_1_CHAR (*q);
0f10071e 7280 }
ae5c1c7b 7281 else
c0f3af97
L		 7282 {
7283 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7284 if (*q)
7285 switch (j)
7286 {
7287 case REX_PREFIX:
7288 /* REX byte is encoded in VEX prefix. */
7289 break;
7290 case SEG_PREFIX:
7291 case ADDR_PREFIX:
7292 FRAG_APPEND_1_CHAR (*q);
7293 break;
7294 default:
7295 /* There should be no other prefixes for instructions
7296 with VEX prefix. */
7297 abort ();
7298 }
7299
43234a1e
L		 7300 /* For EVEX instructions i.vrex should become 0 after
7301 build_evex_prefix. For VEX instructions upper 16 registers
7302 aren't available, so VREX should be 0. */
7303 if (i.vrex)
7304 abort ();
c0f3af97
L		 7305 /* Now the VEX prefix. */
7306 p = frag_more (i.vex.length);
7307 for (j = 0; j < i.vex.length; j++)
7308 p[j] = i.vex.bytes[j];
7309 }
252b5132 7310
29b0f896 7311 /* Now the opcode; be careful about word order here! */
4dffcebc 7312 if (i.tm.opcode_length == 1)
29b0f896
AM		 7313 {
7314 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7315 }
7316 else
7317 {
4dffcebc 7318 switch (i.tm.opcode_length)
331d2d0d 7319 {
43234a1e
L		 7320 case 4:
7321 p = frag_more (4);
7322 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7323 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7324 break;
4dffcebc 7325 case 3:
331d2d0d
L		 7326 p = frag_more (3);
7327 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7328 break;
7329 case 2:
7330 p = frag_more (2);
7331 break;
7332 default:
7333 abort ();
7334 break;
331d2d0d 7335 }
0f10071e 7336
29b0f896
AM		 7337 /* Put out high byte first: can't use md_number_to_chars! */
7338 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7339 *p = i.tm.base_opcode & 0xff;
7340 }
3e73aa7c 7341
29b0f896 7342 /* Now the modrm byte and sib byte (if present). */
40fb9820 7343 if (i.tm.opcode_modifier.modrm)
29b0f896 7344 {
4a3523fa
L		 7345 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7346 | i.rm.reg << 3
7347 | i.rm.mode << 6));
29b0f896
AM		 7348 /* If i.rm.regmem == ESP (4)
7349 && i.rm.mode != (Register mode)
7350 && not 16 bit
7351 ==> need second modrm byte. */
7352 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7353 && i.rm.mode != 3
40fb9820 7354 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7355 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7356 | i.sib.index << 3
7357 | i.sib.scale << 6));
29b0f896 7358 }
3e73aa7c 7359
29b0f896 7360 if (i.disp_operands)
2bbd9c25 7361 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7362
29b0f896 7363 if (i.imm_operands)
2bbd9c25 7364 output_imm (insn_start_frag, insn_start_off);
29b0f896 7365 }
252b5132 7366
29b0f896
AM		 7367#ifdef DEBUG386
7368 if (flag_debug)
7369 {
7b81dfbb 7370 pi ("" /*line*/, &i);
29b0f896
AM		 7371 }
7372#endif /* DEBUG386 */
7373}
252b5132 7374
e205caa7
L		 7375/* Return the size of the displacement operand N. */
7376
7377static int
7378disp_size (unsigned int n)
7379{
7380 int size = 4;
43234a1e 7381
b5014f7a 7382 if (i.types[n].bitfield.disp64)
40fb9820
L		 7383 size = 8;
7384 else if (i.types[n].bitfield.disp8)
7385 size = 1;
7386 else if (i.types[n].bitfield.disp16)
7387 size = 2;
e205caa7
L		 7388 return size;
7389}
7390
7391/* Return the size of the immediate operand N. */
7392
7393static int
7394imm_size (unsigned int n)
7395{
7396 int size = 4;
40fb9820
L		 7397 if (i.types[n].bitfield.imm64)
7398 size = 8;
7399 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7400 size = 1;
7401 else if (i.types[n].bitfield.imm16)
7402 size = 2;
e205caa7
L		 7403 return size;
7404}
7405
29b0f896 7406static void
64e74474 7407output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7408{
7409 char *p;
7410 unsigned int n;
252b5132 7411
29b0f896
AM		 7412 for (n = 0; n < i.operands; n++)
7413 {
b5014f7a 7414 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7415 {
7416 if (i.op[n].disps->X_op == O_constant)
7417 {
e205caa7 7418 int size = disp_size (n);
43234a1e 7419 offsetT val = i.op[n].disps->X_add_number;
252b5132 7420
b5014f7a 7421 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7422 p = frag_more (size);
7423 md_number_to_chars (p, val, size);
7424 }
7425 else
7426 {
f86103b7 7427 enum bfd_reloc_code_real reloc_type;
e205caa7 7428 int size = disp_size (n);
40fb9820 7429 int sign = i.types[n].bitfield.disp32s;
29b0f896 7430 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7431 fixS *fixP;
29b0f896 7432
e205caa7 7433 /* We can't have 8 bit displacement here. */
9c2799c2 7434 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7435
29b0f896
AM		 7436 /* The PC relative address is computed relative
7437 to the instruction boundary, so in case immediate
7438 fields follows, we need to adjust the value. */
7439 if (pcrel && i.imm_operands)
7440 {
29b0f896 7441 unsigned int n1;
e205caa7 7442 int sz = 0;
252b5132 7443
29b0f896 7444 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7445 if (operand_type_check (i.types[n1], imm))
252b5132 7446 {
e205caa7
L		 7447 /* Only one immediate is allowed for PC
7448 relative address. */
9c2799c2 7449 gas_assert (sz == 0);
e205caa7
L		 7450 sz = imm_size (n1);
7451 i.op[n].disps->X_add_number -= sz;
252b5132 7452 }
29b0f896 7453 /* We should find the immediate. */
9c2799c2 7454 gas_assert (sz != 0);
29b0f896 7455 }
520dc8e8 7456
29b0f896 7457 p = frag_more (size);
d258b828 7458 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7459 if (GOT_symbol
2bbd9c25 7460 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7461 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7462 || reloc_type == BFD_RELOC_X86_64_32S
7463 || (reloc_type == BFD_RELOC_64
7464 && object_64bit))
d6ab8113
JB		 7465 && (i.op[n].disps->X_op == O_symbol
7466 || (i.op[n].disps->X_op == O_add
7467 && ((symbol_get_value_expression
7468 (i.op[n].disps->X_op_symbol)->X_op)
7469 == O_subtract))))
7470 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7471 {
7472 offsetT add;
7473
7474 if (insn_start_frag == frag_now)
7475 add = (p - frag_now->fr_literal) - insn_start_off;
7476 else
7477 {
7478 fragS *fr;
7479
7480 add = insn_start_frag->fr_fix - insn_start_off;
7481 for (fr = insn_start_frag->fr_next;
7482 fr && fr != frag_now; fr = fr->fr_next)
7483 add += fr->fr_fix;
7484 add += p - frag_now->fr_literal;
7485 }
7486
4fa24527 7487 if (!object_64bit)
7b81dfbb
AJ		 7488 {
7489 reloc_type = BFD_RELOC_386_GOTPC;
7490 i.op[n].imms->X_add_number += add;
7491 }
7492 else if (reloc_type == BFD_RELOC_64)
7493 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7494 else
7b81dfbb
AJ		 7495 /* Don't do the adjustment for x86-64, as there
7496 the pcrel addressing is relative to the _next_
7497 insn, and that is taken care of in other code. */
d6ab8113 7498 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7499 }
02a86693
L		 7500 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7501 size, i.op[n].disps, pcrel,
7502 reloc_type);
7503 /* Check for "call/jmp *mem", "mov mem, %reg",
7504 "test %reg, mem" and "binop mem, %reg" where binop
7505 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7506 instructions. Always generate R_386_GOT32X for
7507 "sym*GOT" operand in 32-bit mode. */
7508 if ((generate_relax_relocations
7509 || (!object_64bit
7510 && i.rm.mode == 0
7511 && i.rm.regmem == 5))
7512 && (i.rm.mode == 2
7513 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7514 && ((i.operands == 1
7515 && i.tm.base_opcode == 0xff
7516 && (i.rm.reg == 2 || i.rm.reg == 4))
7517 || (i.operands == 2
7518 && (i.tm.base_opcode == 0x8b
7519 || i.tm.base_opcode == 0x85
7520 || (i.tm.base_opcode & 0xc7) == 0x03))))
7521 {
7522 if (object_64bit)
7523 {
7524 fixP->fx_tcbit = i.rex != 0;
7525 if (i.base_reg
7526 && (i.base_reg->reg_num == RegRip
7527 || i.base_reg->reg_num == RegEip))
7528 fixP->fx_tcbit2 = 1;
7529 }
7530 else
7531 fixP->fx_tcbit2 = 1;
7532 }
29b0f896
AM		 7533 }
7534 }
7535 }
7536}
252b5132 7537
29b0f896 7538static void
64e74474 7539output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7540{
7541 char *p;
7542 unsigned int n;
252b5132 7543
29b0f896
AM		 7544 for (n = 0; n < i.operands; n++)
7545 {
43234a1e
L		 7546 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7547 if (i.rounding && (int) n == i.rounding->operand)
7548 continue;
7549
40fb9820 7550 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7551 {
7552 if (i.op[n].imms->X_op == O_constant)
7553 {
e205caa7 7554 int size = imm_size (n);
29b0f896 7555 offsetT val;
b4cac588 7556
29b0f896
AM		 7557 val = offset_in_range (i.op[n].imms->X_add_number,
7558 size);
7559 p = frag_more (size);
7560 md_number_to_chars (p, val, size);
7561 }
7562 else
7563 {
7564 /* Not absolute_section.
7565 Need a 32-bit fixup (don't support 8bit
7566 non-absolute imms). Try to support other
7567 sizes ... */
f86103b7 7568 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7569 int size = imm_size (n);
7570 int sign;
29b0f896 7571
40fb9820 7572 if (i.types[n].bitfield.imm32s
a7d61044 7573 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7574 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7575 sign = 1;
e205caa7
L		 7576 else
7577 sign = 0;
520dc8e8 7578
29b0f896 7579 p = frag_more (size);
d258b828 7580 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7581
2bbd9c25
JJ		 7582 /* This is tough to explain. We end up with this one if we
7583 * have operands that look like
7584 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7585 * obtain the absolute address of the GOT, and it is strongly
7586 * preferable from a performance point of view to avoid using
7587 * a runtime relocation for this. The actual sequence of
7588 * instructions often look something like:
7589 *
7590 * call .L66
7591 * .L66:
7592 * popl %ebx
7593 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7594 *
7595 * The call and pop essentially return the absolute address
7596 * of the label .L66 and store it in %ebx. The linker itself
7597 * will ultimately change the first operand of the addl so
7598 * that %ebx points to the GOT, but to keep things simple, the
7599 * .o file must have this operand set so that it generates not
7600 * the absolute address of .L66, but the absolute address of
7601 * itself. This allows the linker itself simply treat a GOTPC
7602 * relocation as asking for a pcrel offset to the GOT to be
7603 * added in, and the addend of the relocation is stored in the
7604 * operand field for the instruction itself.
7605 *
7606 * Our job here is to fix the operand so that it would add
7607 * the correct offset so that %ebx would point to itself. The
7608 * thing that is tricky is that .-.L66 will point to the
7609 * beginning of the instruction, so we need to further modify
7610 * the operand so that it will point to itself. There are
7611 * other cases where you have something like:
7612 *
7613 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7614 *
7615 * and here no correction would be required. Internally in
7616 * the assembler we treat operands of this form as not being
7617 * pcrel since the '.' is explicitly mentioned, and I wonder
7618 * whether it would simplify matters to do it this way. Who
7619 * knows. In earlier versions of the PIC patches, the
7620 * pcrel_adjust field was used to store the correction, but
7621 * since the expression is not pcrel, I felt it would be
7622 * confusing to do it this way. */
7623
d6ab8113 7624 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7625 || reloc_type == BFD_RELOC_X86_64_32S
7626 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7627 && GOT_symbol
7628 && GOT_symbol == i.op[n].imms->X_add_symbol
7629 && (i.op[n].imms->X_op == O_symbol
7630 || (i.op[n].imms->X_op == O_add
7631 && ((symbol_get_value_expression
7632 (i.op[n].imms->X_op_symbol)->X_op)
7633 == O_subtract))))
7634 {
2bbd9c25
JJ		 7635 offsetT add;
7636
7637 if (insn_start_frag == frag_now)
7638 add = (p - frag_now->fr_literal) - insn_start_off;
7639 else
7640 {
7641 fragS *fr;
7642
7643 add = insn_start_frag->fr_fix - insn_start_off;
7644 for (fr = insn_start_frag->fr_next;
7645 fr && fr != frag_now; fr = fr->fr_next)
7646 add += fr->fr_fix;
7647 add += p - frag_now->fr_literal;
7648 }
7649
4fa24527 7650 if (!object_64bit)
d6ab8113 7651 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7652 else if (size == 4)
d6ab8113 7653 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7654 else if (size == 8)
7655 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7656 i.op[n].imms->X_add_number += add;
29b0f896 7657 }
29b0f896
AM		 7658 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7659 i.op[n].imms, 0, reloc_type);
7660 }
7661 }
7662 }
252b5132
RH		 7663}
7664\f
d182319b
JB		 7665/* x86_cons_fix_new is called via the expression parsing code when a
7666 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7667static int cons_sign = -1;
7668
7669void
e3bb37b5 7670x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7671 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7672{
d258b828 7673 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7674
7675#ifdef TE_PE
7676 if (exp->X_op == O_secrel)
7677 {
7678 exp->X_op = O_symbol;
7679 r = BFD_RELOC_32_SECREL;
7680 }
7681#endif
7682
7683 fix_new_exp (frag, off, len, exp, 0, r);
7684}
7685
357d1bd8
L		 7686/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7687 purpose of the `.dc.a' internal pseudo-op. */
7688
7689int
7690x86_address_bytes (void)
7691{
7692 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7693 return 4;
7694 return stdoutput->arch_info->bits_per_address / 8;
7695}
7696
d382c579
TG		 7697#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7698 || defined (LEX_AT)
d258b828 7699# define lex_got(reloc, adjust, types) NULL
718ddfc0 7700#else
f3c180ae
AM		 7701/* Parse operands of the form
7702 <symbol>@GOTOFF+<nnn>
7703 and similar .plt or .got references.
7704
7705 If we find one, set up the correct relocation in RELOC and copy the
7706 input string, minus the `@GOTOFF' into a malloc'd buffer for
7707 parsing by the calling routine. Return this buffer, and if ADJUST
7708 is non-null set it to the length of the string we removed from the
7709 input line. Otherwise return NULL. */
7710static char *
91d6fa6a 7711lex_got (enum bfd_reloc_code_real *rel,
64e74474 7712 int *adjust,
d258b828 7713 i386_operand_type *types)
f3c180ae 7714{
7b81dfbb
AJ		 7715 /* Some of the relocations depend on the size of what field is to
7716 be relocated. But in our callers i386_immediate and i386_displacement
7717 we don't yet know the operand size (this will be set by insn
7718 matching). Hence we record the word32 relocation here,
7719 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7720 static const struct {
7721 const char *str;
cff8d58a 7722 int len;
4fa24527 7723 const enum bfd_reloc_code_real rel[2];
40fb9820 7724 const i386_operand_type types64;
f3c180ae 7725 } gotrel[] = {
8ce3d284 7726#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7727 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7728 BFD_RELOC_SIZE32 },
7729 OPERAND_TYPE_IMM32_64 },
8ce3d284 7730#endif
cff8d58a
L		 7731 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7732 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7733 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7734 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7735 BFD_RELOC_X86_64_PLT32 },
40fb9820 7736 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7737 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7738 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7739 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7740 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7741 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7742 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7743 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7744 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7745 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7746 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7747 BFD_RELOC_X86_64_TLSGD },
40fb9820 7748 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7749 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7750 _dummy_first_bfd_reloc_code_real },
40fb9820 7751 OPERAND_TYPE_NONE },
cff8d58a
L		 7752 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7753 BFD_RELOC_X86_64_TLSLD },
40fb9820 7754 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7755 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7756 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7757 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7758 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7759 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7760 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7761 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7762 _dummy_first_bfd_reloc_code_real },
40fb9820 7763 OPERAND_TYPE_NONE },
cff8d58a
L		 7764 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7765 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7766 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7767 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7768 _dummy_first_bfd_reloc_code_real },
40fb9820 7769 OPERAND_TYPE_NONE },
cff8d58a
L		 7770 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7771 _dummy_first_bfd_reloc_code_real },
40fb9820 7772 OPERAND_TYPE_NONE },
cff8d58a
L		 7773 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7774 BFD_RELOC_X86_64_GOT32 },
40fb9820 7775 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7776 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7777 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7778 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7779 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7780 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7781 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7782 };
7783 char *cp;
7784 unsigned int j;
7785
d382c579 7786#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7787 if (!IS_ELF)
7788 return NULL;
d382c579 7789#endif
718ddfc0 7790
f3c180ae 7791 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7792 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7793 return NULL;
7794
47465058 7795 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7796 {
cff8d58a 7797 int len = gotrel[j].len;
28f81592 7798 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7799 {
4fa24527 7800 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7801 {
28f81592
AM		 7802 int first, second;
7803 char *tmpbuf, *past_reloc;
f3c180ae 7804
91d6fa6a 7805 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7806
3956db08
JB		 7807 if (types)
7808 {
7809 if (flag_code != CODE_64BIT)
40fb9820
L		 7810 {
7811 types->bitfield.imm32 = 1;
7812 types->bitfield.disp32 = 1;
7813 }
3956db08
JB		 7814 else
7815 *types = gotrel[j].types64;
7816 }
7817
8fd4256d 7818 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7819 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7820
28f81592 7821 /* The length of the first part of our input line. */
f3c180ae 7822 first = cp - input_line_pointer;
28f81592
AM		 7823
7824 /* The second part goes from after the reloc token until
67c11a9b 7825 (and including) an end_of_line char or comma. */
28f81592 7826 past_reloc = cp + 1 + len;
67c11a9b
AM		 7827 cp = past_reloc;
7828 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7829 ++cp;
7830 second = cp + 1 - past_reloc;
28f81592
AM		 7831
7832 /* Allocate and copy string. The trailing NUL shouldn't
7833 be necessary, but be safe. */
add39d23 7834 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7835 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7836 if (second != 0 && *past_reloc != ' ')
7837 /* Replace the relocation token with ' ', so that
7838 errors like foo@GOTOFF1 will be detected. */
7839 tmpbuf[first++] = ' ';
af89796a
L		 7840 else
7841 /* Increment length by 1 if the relocation token is
7842 removed. */
7843 len++;
7844 if (adjust)
7845 *adjust = len;
0787a12d
AM		 7846 memcpy (tmpbuf + first, past_reloc, second);
7847 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7848 return tmpbuf;
7849 }
7850
4fa24527
JB		 7851 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7852 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7853 return NULL;
7854 }
7855 }
7856
7857 /* Might be a symbol version string. Don't as_bad here. */
7858 return NULL;
7859}
4e4f7c87 7860#endif
f3c180ae 7861
a988325c
NC		 7862#ifdef TE_PE
7863#ifdef lex_got
7864#undef lex_got
7865#endif
7866/* Parse operands of the form
7867 <symbol>@SECREL32+<nnn>
7868
7869 If we find one, set up the correct relocation in RELOC and copy the
7870 input string, minus the `@SECREL32' into a malloc'd buffer for
7871 parsing by the calling routine. Return this buffer, and if ADJUST
7872 is non-null set it to the length of the string we removed from the
34bca508
L		 7873 input line. Otherwise return NULL.
7874
a988325c
NC		 7875 This function is copied from the ELF version above adjusted for PE targets. */
7876
7877static char *
7878lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7879 int *adjust ATTRIBUTE_UNUSED,
d258b828 7880 i386_operand_type *types)
a988325c
NC		 7881{
7882 static const struct
7883 {
7884 const char *str;
7885 int len;
7886 const enum bfd_reloc_code_real rel[2];
7887 const i386_operand_type types64;
7888 }
7889 gotrel[] =
7890 {
7891 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7892 BFD_RELOC_32_SECREL },
7893 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7894 };
7895
7896 char *cp;
7897 unsigned j;
7898
7899 for (cp = input_line_pointer; *cp != '@'; cp++)
7900 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7901 return NULL;
7902
7903 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7904 {
7905 int len = gotrel[j].len;
7906
7907 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7908 {
7909 if (gotrel[j].rel[object_64bit] != 0)
7910 {
7911 int first, second;
7912 char *tmpbuf, *past_reloc;
7913
7914 *rel = gotrel[j].rel[object_64bit];
7915 if (adjust)
7916 *adjust = len;
7917
7918 if (types)
7919 {
7920 if (flag_code != CODE_64BIT)
7921 {
7922 types->bitfield.imm32 = 1;
7923 types->bitfield.disp32 = 1;
7924 }
7925 else
7926 *types = gotrel[j].types64;
7927 }
7928
7929 /* The length of the first part of our input line. */
7930 first = cp - input_line_pointer;
7931
7932 /* The second part goes from after the reloc token until
7933 (and including) an end_of_line char or comma. */
7934 past_reloc = cp + 1 + len;
7935 cp = past_reloc;
7936 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7937 ++cp;
7938 second = cp + 1 - past_reloc;
7939
7940 /* Allocate and copy string. The trailing NUL shouldn't
7941 be necessary, but be safe. */
add39d23 7942 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7943 memcpy (tmpbuf, input_line_pointer, first);
7944 if (second != 0 && *past_reloc != ' ')
7945 /* Replace the relocation token with ' ', so that
7946 errors like foo@SECLREL321 will be detected. */
7947 tmpbuf[first++] = ' ';
7948 memcpy (tmpbuf + first, past_reloc, second);
7949 tmpbuf[first + second] = '\0';
7950 return tmpbuf;
7951 }
7952
7953 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7954 gotrel[j].str, 1 << (5 + object_64bit));
7955 return NULL;
7956 }
7957 }
7958
7959 /* Might be a symbol version string. Don't as_bad here. */
7960 return NULL;
7961}
7962
7963#endif /* TE_PE */
7964
62ebcb5c 7965bfd_reloc_code_real_type
e3bb37b5 7966x86_cons (expressionS *exp, int size)
f3c180ae 7967{
62ebcb5c
AM		 7968 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7969
ee86248c
JB		 7970 intel_syntax = -intel_syntax;
7971
3c7b9c2c 7972 exp->X_md = 0;
4fa24527 7973 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7974 {
7975 /* Handle @GOTOFF and the like in an expression. */
7976 char *save;
7977 char *gotfree_input_line;
4a57f2cf 7978 int adjust = 0;
f3c180ae
AM		 7979
7980 save = input_line_pointer;
d258b828 7981 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7982 if (gotfree_input_line)
7983 input_line_pointer = gotfree_input_line;
7984
7985 expression (exp);
7986
7987 if (gotfree_input_line)
7988 {
7989 /* expression () has merrily parsed up to the end of line,
7990 or a comma - in the wrong buffer. Transfer how far
7991 input_line_pointer has moved to the right buffer. */
7992 input_line_pointer = (save
7993 + (input_line_pointer - gotfree_input_line)
7994 + adjust);
7995 free (gotfree_input_line);
3992d3b7
AM		 7996 if (exp->X_op == O_constant
7997 || exp->X_op == O_absent
7998 || exp->X_op == O_illegal
0398aac5 7999 || exp->X_op == O_register
3992d3b7
AM		 8000 || exp->X_op == O_big)
8001 {
8002 char c = *input_line_pointer;
8003 *input_line_pointer = 0;
8004 as_bad (_("missing or invalid expression `%s'"), save);
8005 *input_line_pointer = c;
8006 }
f3c180ae
AM		 8007 }
8008 }
8009 else
8010 expression (exp);
ee86248c
JB		 8011
8012 intel_syntax = -intel_syntax;
8013
8014 if (intel_syntax)
8015 i386_intel_simplify (exp);
62ebcb5c
AM		 8016
8017 return got_reloc;
f3c180ae 8018}
f3c180ae 8019
9f32dd5b
L		 8020static void
8021signed_cons (int size)
6482c264 8022{
d182319b
JB		 8023 if (flag_code == CODE_64BIT)
8024 cons_sign = 1;
8025 cons (size);
8026 cons_sign = -1;
6482c264
NC		 8027}
8028
d182319b 8029#ifdef TE_PE
6482c264 8030static void
7016a5d5 8031pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8032{
8033 expressionS exp;
8034
8035 do
8036 {
8037 expression (&exp);
8038 if (exp.X_op == O_symbol)
8039 exp.X_op = O_secrel;
8040
8041 emit_expr (&exp, 4);
8042 }
8043 while (*input_line_pointer++ == ',');
8044
8045 input_line_pointer--;
8046 demand_empty_rest_of_line ();
8047}
6482c264
NC		 8048#endif
8049
43234a1e
L		 8050/* Handle Vector operations. */
8051
8052static char *
8053check_VecOperations (char *op_string, char *op_end)
8054{
8055 const reg_entry *mask;
8056 const char *saved;
8057 char *end_op;
8058
8059 while (*op_string
8060 && (op_end == NULL || op_string < op_end))
8061 {
8062 saved = op_string;
8063 if (*op_string == '{')
8064 {
8065 op_string++;
8066
8067 /* Check broadcasts. */
8068 if (strncmp (op_string, "1to", 3) == 0)
8069 {
8070 int bcst_type;
8071
8072 if (i.broadcast)
8073 goto duplicated_vec_op;
8074
8075 op_string += 3;
8076 if (*op_string == '8')
8077 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8078 else if (*op_string == '4')
8079 bcst_type = BROADCAST_1TO4;
8080 else if (*op_string == '2')
8081 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8082 else if (*op_string == '1'
8083 && *(op_string+1) == '6')
8084 {
8085 bcst_type = BROADCAST_1TO16;
8086 op_string++;
8087 }
8088 else
8089 {
8090 as_bad (_("Unsupported broadcast: `%s'"), saved);
8091 return NULL;
8092 }
8093 op_string++;
8094
8095 broadcast_op.type = bcst_type;
8096 broadcast_op.operand = this_operand;
8097 i.broadcast = &broadcast_op;
8098 }
8099 /* Check masking operation. */
8100 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8101 {
8102 /* k0 can't be used for write mask. */
6d2cd6b2 8103 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8104 {
6d2cd6b2
JB		 8105 as_bad (_("`%s%s' can't be used for write mask"),
8106 register_prefix, mask->reg_name);
43234a1e
L		 8107 return NULL;
8108 }
8109
8110 if (!i.mask)
8111 {
8112 mask_op.mask = mask;
8113 mask_op.zeroing = 0;
8114 mask_op.operand = this_operand;
8115 i.mask = &mask_op;
8116 }
8117 else
8118 {
8119 if (i.mask->mask)
8120 goto duplicated_vec_op;
8121
8122 i.mask->mask = mask;
8123
8124 /* Only "{z}" is allowed here. No need to check
8125 zeroing mask explicitly. */
8126 if (i.mask->operand != this_operand)
8127 {
8128 as_bad (_("invalid write mask `%s'"), saved);
8129 return NULL;
8130 }
8131 }
8132
8133 op_string = end_op;
8134 }
8135 /* Check zeroing-flag for masking operation. */
8136 else if (*op_string == 'z')
8137 {
8138 if (!i.mask)
8139 {
8140 mask_op.mask = NULL;
8141 mask_op.zeroing = 1;
8142 mask_op.operand = this_operand;
8143 i.mask = &mask_op;
8144 }
8145 else
8146 {
8147 if (i.mask->zeroing)
8148 {
8149 duplicated_vec_op:
8150 as_bad (_("duplicated `%s'"), saved);
8151 return NULL;
8152 }
8153
8154 i.mask->zeroing = 1;
8155
8156 /* Only "{%k}" is allowed here. No need to check mask
8157 register explicitly. */
8158 if (i.mask->operand != this_operand)
8159 {
8160 as_bad (_("invalid zeroing-masking `%s'"),
8161 saved);
8162 return NULL;
8163 }
8164 }
8165
8166 op_string++;
8167 }
8168 else
8169 goto unknown_vec_op;
8170
8171 if (*op_string != '}')
8172 {
8173 as_bad (_("missing `}' in `%s'"), saved);
8174 return NULL;
8175 }
8176 op_string++;
8177 continue;
8178 }
8179 unknown_vec_op:
8180 /* We don't know this one. */
8181 as_bad (_("unknown vector operation: `%s'"), saved);
8182 return NULL;
8183 }
8184
6d2cd6b2
JB		 8185 if (i.mask && i.mask->zeroing && !i.mask->mask)
8186 {
8187 as_bad (_("zeroing-masking only allowed with write mask"));
8188 return NULL;
8189 }
8190
43234a1e
L		 8191 return op_string;
8192}
8193
252b5132 8194static int
70e41ade 8195i386_immediate (char *imm_start)
252b5132
RH		 8196{
8197 char *save_input_line_pointer;
f3c180ae 8198 char *gotfree_input_line;
252b5132 8199 segT exp_seg = 0;
47926f60 8200 expressionS *exp;
40fb9820
L		 8201 i386_operand_type types;
8202
0dfbf9d7 8203 operand_type_set (&types, ~0);
252b5132
RH		 8204
8205 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8206 {
31b2323c
L		 8207 as_bad (_("at most %d immediate operands are allowed"),
8208 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8209 return 0;
8210 }
8211
8212 exp = &im_expressions[i.imm_operands++];
520dc8e8 8213 i.op[this_operand].imms = exp;
252b5132
RH		 8214
8215 if (is_space_char (*imm_start))
8216 ++imm_start;
8217
8218 save_input_line_pointer = input_line_pointer;
8219 input_line_pointer = imm_start;
8220
d258b828 8221 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8222 if (gotfree_input_line)
8223 input_line_pointer = gotfree_input_line;
252b5132
RH		 8224
8225 exp_seg = expression (exp);
8226
83183c0c 8227 SKIP_WHITESPACE ();
43234a1e
L		 8228
8229 /* Handle vector operations. */
8230 if (*input_line_pointer == '{')
8231 {
8232 input_line_pointer = check_VecOperations (input_line_pointer,
8233 NULL);
8234 if (input_line_pointer == NULL)
8235 return 0;
8236 }
8237
252b5132 8238 if (*input_line_pointer)
f3c180ae 8239 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8240
8241 input_line_pointer = save_input_line_pointer;
f3c180ae 8242 if (gotfree_input_line)
ee86248c
JB		 8243 {
8244 free (gotfree_input_line);
8245
8246 if (exp->X_op == O_constant || exp->X_op == O_register)
8247 exp->X_op = O_illegal;
8248 }
8249
8250 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8251}
252b5132 8252
ee86248c
JB		 8253static int
8254i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8255 i386_operand_type types, const char *imm_start)
8256{
8257 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8258 {
313c53d1
L		 8259 if (imm_start)
8260 as_bad (_("missing or invalid immediate expression `%s'"),
8261 imm_start);
3992d3b7 8262 return 0;
252b5132 8263 }
3e73aa7c 8264 else if (exp->X_op == O_constant)
252b5132 8265 {
47926f60 8266 /* Size it properly later. */
40fb9820 8267 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8268 /* If not 64bit, sign extend val. */
8269 if (flag_code != CODE_64BIT
4eed87de
AM		 8270 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8271 exp->X_add_number
8272 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8273 }
4c63da97 8274#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8275 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8276 && exp_seg != absolute_section
47926f60 8277 && exp_seg != text_section
24eab124
AM		 8278 && exp_seg != data_section
8279 && exp_seg != bss_section
8280 && exp_seg != undefined_section
f86103b7 8281 && !bfd_is_com_section (exp_seg))
252b5132 8282 {
d0b47220 8283 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8284 return 0;
8285 }
8286#endif
a841bdf5 8287 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8288 {
313c53d1
L		 8289 if (imm_start)
8290 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8291 return 0;
8292 }
252b5132
RH		 8293 else
8294 {
8295 /* This is an address. The size of the address will be
24eab124 8296 determined later, depending on destination register,
3e73aa7c 8297 suffix, or the default for the section. */
40fb9820
L		 8298 i.types[this_operand].bitfield.imm8 = 1;
8299 i.types[this_operand].bitfield.imm16 = 1;
8300 i.types[this_operand].bitfield.imm32 = 1;
8301 i.types[this_operand].bitfield.imm32s = 1;
8302 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8303 i.types[this_operand] = operand_type_and (i.types[this_operand],
8304 types);
252b5132
RH		 8305 }
8306
8307 return 1;
8308}
8309
551c1ca1 8310static char *
e3bb37b5 8311i386_scale (char *scale)
252b5132 8312{
551c1ca1
AM		 8313 offsetT val;
8314 char *save = input_line_pointer;
252b5132 8315
551c1ca1
AM		 8316 input_line_pointer = scale;
8317 val = get_absolute_expression ();
8318
8319 switch (val)
252b5132 8320 {
551c1ca1 8321 case 1:
252b5132
RH		 8322 i.log2_scale_factor = 0;
8323 break;
551c1ca1 8324 case 2:
252b5132
RH		 8325 i.log2_scale_factor = 1;
8326 break;
551c1ca1 8327 case 4:
252b5132
RH		 8328 i.log2_scale_factor = 2;
8329 break;
551c1ca1 8330 case 8:
252b5132
RH		 8331 i.log2_scale_factor = 3;
8332 break;
8333 default:
a724f0f4
JB		 8334 {
8335 char sep = *input_line_pointer;
8336
8337 *input_line_pointer = '\0';
8338 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8339 scale);
8340 *input_line_pointer = sep;
8341 input_line_pointer = save;
8342 return NULL;
8343 }
252b5132 8344 }
29b0f896 8345 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8346 {
8347 as_warn (_("scale factor of %d without an index register"),
24eab124 8348 1 << i.log2_scale_factor);
252b5132 8349 i.log2_scale_factor = 0;
252b5132 8350 }
551c1ca1
AM		 8351 scale = input_line_pointer;
8352 input_line_pointer = save;
8353 return scale;
252b5132
RH		 8354}
8355
252b5132 8356static int
e3bb37b5 8357i386_displacement (char *disp_start, char *disp_end)
252b5132 8358{
29b0f896 8359 expressionS *exp;
252b5132
RH		 8360 segT exp_seg = 0;
8361 char *save_input_line_pointer;
f3c180ae 8362 char *gotfree_input_line;
40fb9820
L		 8363 int override;
8364 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8365 int ret;
252b5132 8366
31b2323c
L		 8367 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8368 {
8369 as_bad (_("at most %d displacement operands are allowed"),
8370 MAX_MEMORY_OPERANDS);
8371 return 0;
8372 }
8373
0dfbf9d7 8374 operand_type_set (&bigdisp, 0);
40fb9820
L		 8375 if ((i.types[this_operand].bitfield.jumpabsolute)
8376 || (!current_templates->start->opcode_modifier.jump
8377 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8378 {
40fb9820 8379 bigdisp.bitfield.disp32 = 1;
e05278af 8380 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8381 if (flag_code == CODE_64BIT)
8382 {
8383 if (!override)
8384 {
8385 bigdisp.bitfield.disp32s = 1;
8386 bigdisp.bitfield.disp64 = 1;
8387 }
8388 }
8389 else if ((flag_code == CODE_16BIT) ^ override)
8390 {
8391 bigdisp.bitfield.disp32 = 0;
8392 bigdisp.bitfield.disp16 = 1;
8393 }
e05278af
JB		 8394 }
8395 else
8396 {
8397 /* For PC-relative branches, the width of the displacement
8398 is dependent upon data size, not address size. */
e05278af 8399 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8400 if (flag_code == CODE_64BIT)
8401 {
8402 if (override || i.suffix == WORD_MNEM_SUFFIX)
8403 bigdisp.bitfield.disp16 = 1;
8404 else
8405 {
8406 bigdisp.bitfield.disp32 = 1;
8407 bigdisp.bitfield.disp32s = 1;
8408 }
8409 }
8410 else
e05278af
JB		 8411 {
8412 if (!override)
8413 override = (i.suffix == (flag_code != CODE_16BIT
8414 ? WORD_MNEM_SUFFIX
8415 : LONG_MNEM_SUFFIX));
40fb9820
L		 8416 bigdisp.bitfield.disp32 = 1;
8417 if ((flag_code == CODE_16BIT) ^ override)
8418 {
8419 bigdisp.bitfield.disp32 = 0;
8420 bigdisp.bitfield.disp16 = 1;
8421 }
e05278af 8422 }
e05278af 8423 }
c6fb90c8
L		 8424 i.types[this_operand] = operand_type_or (i.types[this_operand],
8425 bigdisp);
252b5132
RH		 8426
8427 exp = &disp_expressions[i.disp_operands];
520dc8e8 8428 i.op[this_operand].disps = exp;
252b5132
RH		 8429 i.disp_operands++;
8430 save_input_line_pointer = input_line_pointer;
8431 input_line_pointer = disp_start;
8432 END_STRING_AND_SAVE (disp_end);
8433
8434#ifndef GCC_ASM_O_HACK
8435#define GCC_ASM_O_HACK 0
8436#endif
8437#if GCC_ASM_O_HACK
8438 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8439 if (i.types[this_operand].bitfield.baseIndex
24eab124 8440 && displacement_string_end[-1] == '+')
252b5132
RH		 8441 {
8442 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8443 constraint within gcc asm statements.
8444 For instance:
8445
8446 #define _set_tssldt_desc(n,addr,limit,type) \
8447 __asm__ __volatile__ ( \
8448 "movw %w2,%0\n\t" \
8449 "movw %w1,2+%0\n\t" \
8450 "rorl $16,%1\n\t" \
8451 "movb %b1,4+%0\n\t" \
8452 "movb %4,5+%0\n\t" \
8453 "movb $0,6+%0\n\t" \
8454 "movb %h1,7+%0\n\t" \
8455 "rorl $16,%1" \
8456 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8457
8458 This works great except that the output assembler ends
8459 up looking a bit weird if it turns out that there is
8460 no offset. You end up producing code that looks like:
8461
8462 #APP
8463 movw $235,(%eax)
8464 movw %dx,2+(%eax)
8465 rorl $16,%edx
8466 movb %dl,4+(%eax)
8467 movb $137,5+(%eax)
8468 movb $0,6+(%eax)
8469 movb %dh,7+(%eax)
8470 rorl $16,%edx
8471 #NO_APP
8472
47926f60 8473 So here we provide the missing zero. */
24eab124
AM		 8474
8475 *displacement_string_end = '0';
252b5132
RH		 8476 }
8477#endif
d258b828 8478 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8479 if (gotfree_input_line)
8480 input_line_pointer = gotfree_input_line;
252b5132 8481
24eab124 8482 exp_seg = expression (exp);
252b5132 8483
636c26b0
AM		 8484 SKIP_WHITESPACE ();
8485 if (*input_line_pointer)
8486 as_bad (_("junk `%s' after expression"), input_line_pointer);
8487#if GCC_ASM_O_HACK
8488 RESTORE_END_STRING (disp_end + 1);
8489#endif
636c26b0 8490 input_line_pointer = save_input_line_pointer;
636c26b0 8491 if (gotfree_input_line)
ee86248c
JB		 8492 {
8493 free (gotfree_input_line);
8494
8495 if (exp->X_op == O_constant || exp->X_op == O_register)
8496 exp->X_op = O_illegal;
8497 }
8498
8499 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8500
8501 RESTORE_END_STRING (disp_end);
8502
8503 return ret;
8504}
8505
8506static int
8507i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8508 i386_operand_type types, const char *disp_start)
8509{
8510 i386_operand_type bigdisp;
8511 int ret = 1;
636c26b0 8512
24eab124
AM		 8513 /* We do this to make sure that the section symbol is in
8514 the symbol table. We will ultimately change the relocation
47926f60 8515 to be relative to the beginning of the section. */
1ae12ab7 8516 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8517 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8518 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8519 {
636c26b0 8520 if (exp->X_op != O_symbol)
3992d3b7 8521 goto inv_disp;
636c26b0 8522
e5cb08ac 8523 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8524 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8525 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8526 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8527 exp->X_op = O_subtract;
8528 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8529 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8530 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8531 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8532 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8533 else
29b0f896 8534 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8535 }
252b5132 8536
3992d3b7
AM		 8537 else if (exp->X_op == O_absent
8538 || exp->X_op == O_illegal
ee86248c 8539 || exp->X_op == O_big)
2daf4fd8 8540 {
3992d3b7
AM		 8541 inv_disp:
8542 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8543 disp_start);
3992d3b7 8544 ret = 0;
2daf4fd8
AM		 8545 }
8546
0e1147d9
L		 8547 else if (flag_code == CODE_64BIT
8548 && !i.prefix[ADDR_PREFIX]
8549 && exp->X_op == O_constant)
8550 {
8551 /* Since displacement is signed extended to 64bit, don't allow
8552 disp32 and turn off disp32s if they are out of range. */
8553 i.types[this_operand].bitfield.disp32 = 0;
8554 if (!fits_in_signed_long (exp->X_add_number))
8555 {
8556 i.types[this_operand].bitfield.disp32s = 0;
8557 if (i.types[this_operand].bitfield.baseindex)
8558 {
8559 as_bad (_("0x%lx out range of signed 32bit displacement"),
8560 (long) exp->X_add_number);
8561 ret = 0;
8562 }
8563 }
8564 }
8565
4c63da97 8566#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8567 else if (exp->X_op != O_constant
8568 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8569 && exp_seg != absolute_section
8570 && exp_seg != text_section
8571 && exp_seg != data_section
8572 && exp_seg != bss_section
8573 && exp_seg != undefined_section
8574 && !bfd_is_com_section (exp_seg))
24eab124 8575 {
d0b47220 8576 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8577 ret = 0;
24eab124 8578 }
252b5132 8579#endif
3956db08 8580
40fb9820
L		 8581 /* Check if this is a displacement only operand. */
8582 bigdisp = i.types[this_operand];
8583 bigdisp.bitfield.disp8 = 0;
8584 bigdisp.bitfield.disp16 = 0;
8585 bigdisp.bitfield.disp32 = 0;
8586 bigdisp.bitfield.disp32s = 0;
8587 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8588 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8589 i.types[this_operand] = operand_type_and (i.types[this_operand],
8590 types);
3956db08 8591
3992d3b7 8592 return ret;
252b5132
RH		 8593}
8594
2abc2bec
JB		 8595/* Return the active addressing mode, taking address override and
8596 registers forming the address into consideration. Update the
8597 address override prefix if necessary. */
47926f60 8598
2abc2bec
JB		 8599static enum flag_code
8600i386_addressing_mode (void)
252b5132 8601{
be05d201
L		 8602 enum flag_code addr_mode;
8603
8604 if (i.prefix[ADDR_PREFIX])
8605 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8606 else
8607 {
8608 addr_mode = flag_code;
8609
24eab124 8610#if INFER_ADDR_PREFIX
be05d201
L		 8611 if (i.mem_operands == 0)
8612 {
8613 /* Infer address prefix from the first memory operand. */
8614 const reg_entry *addr_reg = i.base_reg;
8615
8616 if (addr_reg == NULL)
8617 addr_reg = i.index_reg;
eecb386c 8618
be05d201
L		 8619 if (addr_reg)
8620 {
8621 if (addr_reg->reg_num == RegEip
8622 || addr_reg->reg_num == RegEiz
8623 || addr_reg->reg_type.bitfield.reg32)
8624 addr_mode = CODE_32BIT;
8625 else if (flag_code != CODE_64BIT
8626 && addr_reg->reg_type.bitfield.reg16)
8627 addr_mode = CODE_16BIT;
8628
8629 if (addr_mode != flag_code)
8630 {
8631 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8632 i.prefixes += 1;
8633 /* Change the size of any displacement too. At most one
8634 of Disp16 or Disp32 is set.
8635 FIXME. There doesn't seem to be any real need for
8636 separate Disp16 and Disp32 flags. The same goes for
8637 Imm16 and Imm32. Removing them would probably clean
8638 up the code quite a lot. */
8639 if (flag_code != CODE_64BIT
8640 && (i.types[this_operand].bitfield.disp16
8641 || i.types[this_operand].bitfield.disp32))
8642 i.types[this_operand]
8643 = operand_type_xor (i.types[this_operand], disp16_32);
8644 }
8645 }
8646 }
24eab124 8647#endif
be05d201
L		 8648 }
8649
2abc2bec
JB		 8650 return addr_mode;
8651}
8652
8653/* Make sure the memory operand we've been dealt is valid.
8654 Return 1 on success, 0 on a failure. */
8655
8656static int
8657i386_index_check (const char *operand_string)
8658{
8659 const char *kind = "base/index";
8660 enum flag_code addr_mode = i386_addressing_mode ();
8661
fc0763e6
JB		 8662 if (current_templates->start->opcode_modifier.isstring
8663 && !current_templates->start->opcode_modifier.immext
8664 && (current_templates->end[-1].opcode_modifier.isstring
8665 || i.mem_operands))
8666 {
8667 /* Memory operands of string insns are special in that they only allow
8668 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8669 const reg_entry *expected_reg;
8670 static const char *di_si[][2] =
8671 {
8672 { "esi", "edi" },
8673 { "si", "di" },
8674 { "rsi", "rdi" }
8675 };
8676 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8677
8678 kind = "string address";
8679
8325cc63 8680 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8681 {
8682 i386_operand_type type = current_templates->end[-1].operand_types[0];
8683
8684 if (!type.bitfield.baseindex
8685 || ((!i.mem_operands != !intel_syntax)
8686 && current_templates->end[-1].operand_types[1]
8687 .bitfield.baseindex))
8688 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8689 expected_reg = hash_find (reg_hash,
8690 di_si[addr_mode][type.bitfield.esseg]);
8691
fc0763e6
JB		 8692 }
8693 else
be05d201 8694 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8695
be05d201
L		 8696 if (i.base_reg != expected_reg
8697 || i.index_reg
fc0763e6 8698 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8699 {
be05d201
L		 8700 /* The second memory operand must have the same size as
8701 the first one. */
8702 if (i.mem_operands
8703 && i.base_reg
8704 && !((addr_mode == CODE_64BIT
8705 && i.base_reg->reg_type.bitfield.reg64)
8706 || (addr_mode == CODE_32BIT
8707 ? i.base_reg->reg_type.bitfield.reg32
8708 : i.base_reg->reg_type.bitfield.reg16)))
8709 goto bad_address;
8710
fc0763e6
JB		 8711 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8712 operand_string,
8713 intel_syntax ? '[' : '(',
8714 register_prefix,
be05d201 8715 expected_reg->reg_name,
fc0763e6 8716 intel_syntax ? ']' : ')');
be05d201 8717 return 1;
fc0763e6 8718 }
be05d201
L		 8719 else
8720 return 1;
8721
8722bad_address:
8723 as_bad (_("`%s' is not a valid %s expression"),
8724 operand_string, kind);
8725 return 0;
3e73aa7c
JH		 8726 }
8727 else
8728 {
be05d201
L		 8729 if (addr_mode != CODE_16BIT)
8730 {
8731 /* 32-bit/64-bit checks. */
8732 if ((i.base_reg
8733 && (addr_mode == CODE_64BIT
8734 ? !i.base_reg->reg_type.bitfield.reg64
8735 : !i.base_reg->reg_type.bitfield.reg32)
8736 && (i.index_reg
8737 || (i.base_reg->reg_num
8738 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8739 || (i.index_reg
8740 && !i.index_reg->reg_type.bitfield.regxmm
8741 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8742 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8743 && ((addr_mode == CODE_64BIT
8744 ? !(i.index_reg->reg_type.bitfield.reg64
8745 || i.index_reg->reg_num == RegRiz)
8746 : !(i.index_reg->reg_type.bitfield.reg32
8747 || i.index_reg->reg_num == RegEiz))
8748 || !i.index_reg->reg_type.bitfield.baseindex)))
8749 goto bad_address;
8178be5b
JB		 8750
8751 /* bndmk, bndldx, and bndstx have special restrictions. */
8752 if (current_templates->start->base_opcode == 0xf30f1b
8753 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8754 {
8755 /* They cannot use RIP-relative addressing. */
8756 if (i.base_reg && i.base_reg->reg_num == RegRip)
8757 {
8758 as_bad (_("`%s' cannot be used here"), operand_string);
8759 return 0;
8760 }
8761
8762 /* bndldx and bndstx ignore their scale factor. */
8763 if (current_templates->start->base_opcode != 0xf30f1b
8764 && i.log2_scale_factor)
8765 as_warn (_("register scaling is being ignored here"));
8766 }
be05d201
L		 8767 }
8768 else
3e73aa7c 8769 {
be05d201 8770 /* 16-bit checks. */
3e73aa7c 8771 if ((i.base_reg
40fb9820
L		 8772 && (!i.base_reg->reg_type.bitfield.reg16
8773 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8774 || (i.index_reg
40fb9820
L		 8775 && (!i.index_reg->reg_type.bitfield.reg16
8776 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8777 || !(i.base_reg
8778 && i.base_reg->reg_num < 6
8779 && i.index_reg->reg_num >= 6
8780 && i.log2_scale_factor == 0))))
be05d201 8781 goto bad_address;
3e73aa7c
JH		 8782 }
8783 }
be05d201 8784 return 1;
24eab124 8785}
252b5132 8786
43234a1e
L		 8787/* Handle vector immediates. */
8788
8789static int
8790RC_SAE_immediate (const char *imm_start)
8791{
8792 unsigned int match_found, j;
8793 const char *pstr = imm_start;
8794 expressionS *exp;
8795
8796 if (*pstr != '{')
8797 return 0;
8798
8799 pstr++;
8800 match_found = 0;
8801 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8802 {
8803 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8804 {
8805 if (!i.rounding)
8806 {
8807 rc_op.type = RC_NamesTable[j].type;
8808 rc_op.operand = this_operand;
8809 i.rounding = &rc_op;
8810 }
8811 else
8812 {
8813 as_bad (_("duplicated `%s'"), imm_start);
8814 return 0;
8815 }
8816 pstr += RC_NamesTable[j].len;
8817 match_found = 1;
8818 break;
8819 }
8820 }
8821 if (!match_found)
8822 return 0;
8823
8824 if (*pstr++ != '}')
8825 {
8826 as_bad (_("Missing '}': '%s'"), imm_start);
8827 return 0;
8828 }
8829 /* RC/SAE immediate string should contain nothing more. */;
8830 if (*pstr != 0)
8831 {
8832 as_bad (_("Junk after '}': '%s'"), imm_start);
8833 return 0;
8834 }
8835
8836 exp = &im_expressions[i.imm_operands++];
8837 i.op[this_operand].imms = exp;
8838
8839 exp->X_op = O_constant;
8840 exp->X_add_number = 0;
8841 exp->X_add_symbol = (symbolS *) 0;
8842 exp->X_op_symbol = (symbolS *) 0;
8843
8844 i.types[this_operand].bitfield.imm8 = 1;
8845 return 1;
8846}
8847
8325cc63
JB		 8848/* Only string instructions can have a second memory operand, so
8849 reduce current_templates to just those if it contains any. */
8850static int
8851maybe_adjust_templates (void)
8852{
8853 const insn_template *t;
8854
8855 gas_assert (i.mem_operands == 1);
8856
8857 for (t = current_templates->start; t < current_templates->end; ++t)
8858 if (t->opcode_modifier.isstring)
8859 break;
8860
8861 if (t < current_templates->end)
8862 {
8863 static templates aux_templates;
8864 bfd_boolean recheck;
8865
8866 aux_templates.start = t;
8867 for (; t < current_templates->end; ++t)
8868 if (!t->opcode_modifier.isstring)
8869 break;
8870 aux_templates.end = t;
8871
8872 /* Determine whether to re-check the first memory operand. */
8873 recheck = (aux_templates.start != current_templates->start
8874 || t != current_templates->end);
8875
8876 current_templates = &aux_templates;
8877
8878 if (recheck)
8879 {
8880 i.mem_operands = 0;
8881 if (i.memop1_string != NULL
8882 && i386_index_check (i.memop1_string) == 0)
8883 return 0;
8884 i.mem_operands = 1;
8885 }
8886 }
8887
8888 return 1;
8889}
8890
fc0763e6 8891/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8892 on error. */
252b5132 8893
252b5132 8894static int
a7619375 8895i386_att_operand (char *operand_string)
252b5132 8896{
af6bdddf
AM		 8897 const reg_entry *r;
8898 char *end_op;
24eab124 8899 char *op_string = operand_string;
252b5132 8900
24eab124 8901 if (is_space_char (*op_string))
252b5132
RH		 8902 ++op_string;
8903
24eab124 8904 /* We check for an absolute prefix (differentiating,
47926f60 8905 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8906 if (*op_string == ABSOLUTE_PREFIX)
8907 {
8908 ++op_string;
8909 if (is_space_char (*op_string))
8910 ++op_string;
40fb9820 8911 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8912 }
252b5132 8913
47926f60 8914 /* Check if operand is a register. */
4d1bb795 8915 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8916 {
40fb9820
L		 8917 i386_operand_type temp;
8918
24eab124
AM		 8919 /* Check for a segment override by searching for ':' after a
8920 segment register. */
8921 op_string = end_op;
8922 if (is_space_char (*op_string))
8923 ++op_string;
40fb9820
L		 8924 if (*op_string == ':'
8925 && (r->reg_type.bitfield.sreg2
8926 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8927 {
8928 switch (r->reg_num)
8929 {
8930 case 0:
8931 i.seg[i.mem_operands] = &es;
8932 break;
8933 case 1:
8934 i.seg[i.mem_operands] = &cs;
8935 break;
8936 case 2:
8937 i.seg[i.mem_operands] = &ss;
8938 break;
8939 case 3:
8940 i.seg[i.mem_operands] = &ds;
8941 break;
8942 case 4:
8943 i.seg[i.mem_operands] = &fs;
8944 break;
8945 case 5:
8946 i.seg[i.mem_operands] = &gs;
8947 break;
8948 }
252b5132 8949
24eab124 8950 /* Skip the ':' and whitespace. */
252b5132
RH		 8951 ++op_string;
8952 if (is_space_char (*op_string))
24eab124 8953 ++op_string;
252b5132 8954
24eab124
AM		 8955 if (!is_digit_char (*op_string)
8956 && !is_identifier_char (*op_string)
8957 && *op_string != '('
8958 && *op_string != ABSOLUTE_PREFIX)
8959 {
8960 as_bad (_("bad memory operand `%s'"), op_string);
8961 return 0;
8962 }
47926f60 8963 /* Handle case of %es:*foo. */
24eab124
AM		 8964 if (*op_string == ABSOLUTE_PREFIX)
8965 {
8966 ++op_string;
8967 if (is_space_char (*op_string))
8968 ++op_string;
40fb9820 8969 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8970 }
8971 goto do_memory_reference;
8972 }
43234a1e
L		 8973
8974 /* Handle vector operations. */
8975 if (*op_string == '{')
8976 {
8977 op_string = check_VecOperations (op_string, NULL);
8978 if (op_string == NULL)
8979 return 0;
8980 }
8981
24eab124
AM		 8982 if (*op_string)
8983 {
d0b47220 8984 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8985 return 0;
8986 }
40fb9820
L		 8987 temp = r->reg_type;
8988 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8989 i.types[this_operand] = operand_type_or (i.types[this_operand],
8990 temp);
7d5e4556 8991 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8992 i.op[this_operand].regs = r;
24eab124
AM		 8993 i.reg_operands++;
8994 }
af6bdddf
AM		 8995 else if (*op_string == REGISTER_PREFIX)
8996 {
8997 as_bad (_("bad register name `%s'"), op_string);
8998 return 0;
8999 }
24eab124 9000 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9001 {
24eab124 9002 ++op_string;
40fb9820 9003 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9004 {
d0b47220 9005 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9006 return 0;
9007 }
9008 if (!i386_immediate (op_string))
9009 return 0;
9010 }
43234a1e
L		 9011 else if (RC_SAE_immediate (operand_string))
9012 {
9013 /* If it is a RC or SAE immediate, do nothing. */
9014 ;
9015 }
24eab124
AM		 9016 else if (is_digit_char (*op_string)
9017 || is_identifier_char (*op_string)
d02603dc 9018 || *op_string == '"'
e5cb08ac 9019 || *op_string == '(')
24eab124 9020 {
47926f60 9021 /* This is a memory reference of some sort. */
af6bdddf 9022 char *base_string;
252b5132 9023
47926f60 9024 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9025 char *displacement_string_start;
9026 char *displacement_string_end;
43234a1e 9027 char *vop_start;
252b5132 9028
24eab124 9029 do_memory_reference:
8325cc63
JB		 9030 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9031 return 0;
24eab124 9032 if ((i.mem_operands == 1
40fb9820 9033 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9034 || i.mem_operands == 2)
9035 {
9036 as_bad (_("too many memory references for `%s'"),
9037 current_templates->start->name);
9038 return 0;
9039 }
252b5132 9040
24eab124
AM		 9041 /* Check for base index form. We detect the base index form by
9042 looking for an ')' at the end of the operand, searching
9043 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9044 after the '('. */
af6bdddf 9045 base_string = op_string + strlen (op_string);
c3332e24 9046
43234a1e
L		 9047 /* Handle vector operations. */
9048 vop_start = strchr (op_string, '{');
9049 if (vop_start && vop_start < base_string)
9050 {
9051 if (check_VecOperations (vop_start, base_string) == NULL)
9052 return 0;
9053 base_string = vop_start;
9054 }
9055
af6bdddf
AM		 9056 --base_string;
9057 if (is_space_char (*base_string))
9058 --base_string;
252b5132 9059
47926f60 9060 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9061 displacement_string_start = op_string;
9062 displacement_string_end = base_string + 1;
252b5132 9063
24eab124
AM		 9064 if (*base_string == ')')
9065 {
af6bdddf 9066 char *temp_string;
24eab124
AM		 9067 unsigned int parens_balanced = 1;
9068 /* We've already checked that the number of left & right ()'s are
47926f60 9069 equal, so this loop will not be infinite. */
24eab124
AM		 9070 do
9071 {
9072 base_string--;
9073 if (*base_string == ')')
9074 parens_balanced++;
9075 if (*base_string == '(')
9076 parens_balanced--;
9077 }
9078 while (parens_balanced);
c3332e24 9079
af6bdddf 9080 temp_string = base_string;
c3332e24 9081
24eab124 9082 /* Skip past '(' and whitespace. */
252b5132
RH		 9083 ++base_string;
9084 if (is_space_char (*base_string))
24eab124 9085 ++base_string;
252b5132 9086
af6bdddf 9087 if (*base_string == ','
4eed87de
AM		 9088 || ((i.base_reg = parse_register (base_string, &end_op))
9089 != NULL))
252b5132 9090 {
af6bdddf 9091 displacement_string_end = temp_string;
252b5132 9092
40fb9820 9093 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9094
af6bdddf 9095 if (i.base_reg)
24eab124 9096 {
24eab124
AM		 9097 base_string = end_op;
9098 if (is_space_char (*base_string))
9099 ++base_string;
af6bdddf
AM		 9100 }
9101
9102 /* There may be an index reg or scale factor here. */
9103 if (*base_string == ',')
9104 {
9105 ++base_string;
9106 if (is_space_char (*base_string))
9107 ++base_string;
9108
4eed87de
AM		 9109 if ((i.index_reg = parse_register (base_string, &end_op))
9110 != NULL)
24eab124 9111 {
af6bdddf 9112 base_string = end_op;
24eab124
AM		 9113 if (is_space_char (*base_string))
9114 ++base_string;
af6bdddf
AM		 9115 if (*base_string == ',')
9116 {
9117 ++base_string;
9118 if (is_space_char (*base_string))
9119 ++base_string;
9120 }
e5cb08ac 9121 else if (*base_string != ')')
af6bdddf 9122 {
4eed87de
AM		 9123 as_bad (_("expecting `,' or `)' "
9124 "after index register in `%s'"),
af6bdddf
AM		 9125 operand_string);
9126 return 0;
9127 }
24eab124 9128 }
af6bdddf 9129 else if (*base_string == REGISTER_PREFIX)
24eab124 9130 {
f76bf5e0
L		 9131 end_op = strchr (base_string, ',');
9132 if (end_op)
9133 *end_op = '\0';
af6bdddf 9134 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9135 return 0;
9136 }
252b5132 9137
47926f60 9138 /* Check for scale factor. */
551c1ca1 9139 if (*base_string != ')')
af6bdddf 9140 {
551c1ca1
AM		 9141 char *end_scale = i386_scale (base_string);
9142
9143 if (!end_scale)
af6bdddf 9144 return 0;
24eab124 9145
551c1ca1 9146 base_string = end_scale;
af6bdddf
AM		 9147 if (is_space_char (*base_string))
9148 ++base_string;
9149 if (*base_string != ')')
9150 {
4eed87de
AM		 9151 as_bad (_("expecting `)' "
9152 "after scale factor in `%s'"),
af6bdddf
AM		 9153 operand_string);
9154 return 0;
9155 }
9156 }
9157 else if (!i.index_reg)
24eab124 9158 {
4eed87de
AM		 9159 as_bad (_("expecting index register or scale factor "
9160 "after `,'; got '%c'"),
af6bdddf 9161 *base_string);
24eab124
AM		 9162 return 0;
9163 }
9164 }
af6bdddf 9165 else if (*base_string != ')')
24eab124 9166 {
4eed87de
AM		 9167 as_bad (_("expecting `,' or `)' "
9168 "after base register in `%s'"),
af6bdddf 9169 operand_string);
24eab124
AM		 9170 return 0;
9171 }
c3332e24 9172 }
af6bdddf 9173 else if (*base_string == REGISTER_PREFIX)
c3332e24 9174 {
f76bf5e0
L		 9175 end_op = strchr (base_string, ',');
9176 if (end_op)
9177 *end_op = '\0';
af6bdddf 9178 as_bad (_("bad register name `%s'"), base_string);
24eab124 9179 return 0;
c3332e24 9180 }
24eab124
AM		 9181 }
9182
9183 /* If there's an expression beginning the operand, parse it,
9184 assuming displacement_string_start and
9185 displacement_string_end are meaningful. */
9186 if (displacement_string_start != displacement_string_end)
9187 {
9188 if (!i386_displacement (displacement_string_start,
9189 displacement_string_end))
9190 return 0;
9191 }
9192
9193 /* Special case for (%dx) while doing input/output op. */
9194 if (i.base_reg
0dfbf9d7
L		 9195 && operand_type_equal (&i.base_reg->reg_type,
9196 &reg16_inoutportreg)
24eab124
AM		 9197 && i.index_reg == 0
9198 && i.log2_scale_factor == 0
9199 && i.seg[i.mem_operands] == 0
40fb9820 9200 && !operand_type_check (i.types[this_operand], disp))
24eab124 9201 {
65da13b5 9202 i.types[this_operand] = inoutportreg;
24eab124
AM		 9203 return 1;
9204 }
9205
eecb386c
AM		 9206 if (i386_index_check (operand_string) == 0)
9207 return 0;
5c07affc 9208 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9209 if (i.mem_operands == 0)
9210 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9211 i.mem_operands++;
9212 }
9213 else
ce8a8b2f
AM		 9214 {
9215 /* It's not a memory operand; argh! */
24eab124
AM		 9216 as_bad (_("invalid char %s beginning operand %d `%s'"),
9217 output_invalid (*op_string),
9218 this_operand + 1,
9219 op_string);
9220 return 0;
9221 }
47926f60 9222 return 1; /* Normal return. */
252b5132
RH		 9223}
9224\f
fa94de6b
RM		 9225/* Calculate the maximum variable size (i.e., excluding fr_fix)
9226 that an rs_machine_dependent frag may reach. */
9227
9228unsigned int
9229i386_frag_max_var (fragS *frag)
9230{
9231 /* The only relaxable frags are for jumps.
9232 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9233 gas_assert (frag->fr_type == rs_machine_dependent);
9234 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9235}
9236
b084df0b
L		 9237#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9238static int
8dcea932 9239elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9240{
9241 /* STT_GNU_IFUNC symbol must go through PLT. */
9242 if ((symbol_get_bfdsym (fr_symbol)->flags
9243 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9244 return 0;
9245
9246 if (!S_IS_EXTERNAL (fr_symbol))
9247 /* Symbol may be weak or local. */
9248 return !S_IS_WEAK (fr_symbol);
9249
8dcea932
L		 9250 /* Global symbols with non-default visibility can't be preempted. */
9251 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9252 return 1;
9253
9254 if (fr_var != NO_RELOC)
9255 switch ((enum bfd_reloc_code_real) fr_var)
9256 {
9257 case BFD_RELOC_386_PLT32:
9258 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9259 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9260 return 0;
9261 default:
9262 abort ();
9263 }
9264
b084df0b
L		 9265 /* Global symbols with default visibility in a shared library may be
9266 preempted by another definition. */
8dcea932 9267 return !shared;
b084df0b
L		 9268}
9269#endif
9270
ee7fcc42
AM		 9271/* md_estimate_size_before_relax()
9272
9273 Called just before relax() for rs_machine_dependent frags. The x86
9274 assembler uses these frags to handle variable size jump
9275 instructions.
9276
9277 Any symbol that is now undefined will not become defined.
9278 Return the correct fr_subtype in the frag.
9279 Return the initial "guess for variable size of frag" to caller.
9280 The guess is actually the growth beyond the fixed part. Whatever
9281 we do to grow the fixed or variable part contributes to our
9282 returned value. */
9283
252b5132 9284int
7016a5d5 9285md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9286{
252b5132 9287 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9288 check for un-relaxable symbols. On an ELF system, we can't relax
9289 an externally visible symbol, because it may be overridden by a
9290 shared library. */
9291 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9292#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9293 || (IS_ELF
8dcea932
L		 9294 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9295 fragP->fr_var))
fbeb56a4
DK		 9296#endif
9297#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9298 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9299 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9300#endif
9301 )
252b5132 9302 {
b98ef147
AM		 9303 /* Symbol is undefined in this segment, or we need to keep a
9304 reloc so that weak symbols can be overridden. */
9305 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9306 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9307 unsigned char *opcode;
9308 int old_fr_fix;
f6af82bd 9309
ee7fcc42 9310 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9311 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9312 else if (size == 2)
f6af82bd
AM		 9313 reloc_type = BFD_RELOC_16_PCREL;
9314 else
9315 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9316
ee7fcc42
AM		 9317 old_fr_fix = fragP->fr_fix;
9318 opcode = (unsigned char *) fragP->fr_opcode;
9319
fddf5b5b 9320 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9321 {
fddf5b5b
AM		 9322 case UNCOND_JUMP:
9323 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9324 opcode[0] = 0xe9;
252b5132 9325 fragP->fr_fix += size;
062cd5e7
AS		 9326 fix_new (fragP, old_fr_fix, size,
9327 fragP->fr_symbol,
9328 fragP->fr_offset, 1,
9329 reloc_type);
252b5132
RH		 9330 break;
9331
fddf5b5b 9332 case COND_JUMP86:
412167cb
AM		 9333 if (size == 2
9334 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9335 {
9336 /* Negate the condition, and branch past an
9337 unconditional jump. */
9338 opcode[0] ^= 1;
9339 opcode[1] = 3;
9340 /* Insert an unconditional jump. */
9341 opcode[2] = 0xe9;
9342 /* We added two extra opcode bytes, and have a two byte
9343 offset. */
9344 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9345 fix_new (fragP, old_fr_fix + 2, 2,
9346 fragP->fr_symbol,
9347 fragP->fr_offset, 1,
9348 reloc_type);
fddf5b5b
AM		 9349 break;
9350 }
9351 /* Fall through. */
9352
9353 case COND_JUMP:
412167cb
AM		 9354 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9355 {
3e02c1cc
AM		 9356 fixS *fixP;
9357
412167cb 9358 fragP->fr_fix += 1;
3e02c1cc
AM		 9359 fixP = fix_new (fragP, old_fr_fix, 1,
9360 fragP->fr_symbol,
9361 fragP->fr_offset, 1,
9362 BFD_RELOC_8_PCREL);
9363 fixP->fx_signed = 1;
412167cb
AM		 9364 break;
9365 }
93c2a809 9366
24eab124 9367 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9368 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9369 opcode[1] = opcode[0] + 0x10;
f6af82bd 9370 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9371 /* We've added an opcode byte. */
9372 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9373 fix_new (fragP, old_fr_fix + 1, size,
9374 fragP->fr_symbol,
9375 fragP->fr_offset, 1,
9376 reloc_type);
252b5132 9377 break;
fddf5b5b
AM		 9378
9379 default:
9380 BAD_CASE (fragP->fr_subtype);
9381 break;
252b5132
RH		 9382 }
9383 frag_wane (fragP);
ee7fcc42 9384 return fragP->fr_fix - old_fr_fix;
252b5132 9385 }
93c2a809 9386
93c2a809
AM		 9387 /* Guess size depending on current relax state. Initially the relax
9388 state will correspond to a short jump and we return 1, because
9389 the variable part of the frag (the branch offset) is one byte
9390 long. However, we can relax a section more than once and in that
9391 case we must either set fr_subtype back to the unrelaxed state,
9392 or return the value for the appropriate branch. */
9393 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9394}
9395
47926f60
KH		 9396/* Called after relax() is finished.
9397
9398 In: Address of frag.
9399 fr_type == rs_machine_dependent.
9400 fr_subtype is what the address relaxed to.
9401
9402 Out: Any fixSs and constants are set up.
9403 Caller will turn frag into a ".space 0". */
9404
252b5132 9405void
7016a5d5
TG		 9406md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9407 fragS *fragP)
252b5132 9408{
29b0f896 9409 unsigned char *opcode;
252b5132 9410 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9411 offsetT target_address;
9412 offsetT opcode_address;
252b5132 9413 unsigned int extension = 0;
847f7ad4 9414 offsetT displacement_from_opcode_start;
252b5132
RH		 9415
9416 opcode = (unsigned char *) fragP->fr_opcode;
9417
47926f60 9418 /* Address we want to reach in file space. */
252b5132 9419 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9420
47926f60 9421 /* Address opcode resides at in file space. */
252b5132
RH		 9422 opcode_address = fragP->fr_address + fragP->fr_fix;
9423
47926f60 9424 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9425 displacement_from_opcode_start = target_address - opcode_address;
9426
fddf5b5b 9427 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9428 {
47926f60
KH		 9429 /* Don't have to change opcode. */
9430 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9431 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9432 }
9433 else
9434 {
9435 if (no_cond_jump_promotion
9436 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9437 as_warn_where (fragP->fr_file, fragP->fr_line,
9438 _("long jump required"));
252b5132 9439
fddf5b5b
AM		 9440 switch (fragP->fr_subtype)
9441 {
9442 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9443 extension = 4; /* 1 opcode + 4 displacement */
9444 opcode[0] = 0xe9;
9445 where_to_put_displacement = &opcode[1];
9446 break;
252b5132 9447
fddf5b5b
AM		 9448 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9449 extension = 2; /* 1 opcode + 2 displacement */
9450 opcode[0] = 0xe9;
9451 where_to_put_displacement = &opcode[1];
9452 break;
252b5132 9453
fddf5b5b
AM		 9454 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9455 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9456 extension = 5; /* 2 opcode + 4 displacement */
9457 opcode[1] = opcode[0] + 0x10;
9458 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9459 where_to_put_displacement = &opcode[2];
9460 break;
252b5132 9461
fddf5b5b
AM		 9462 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9463 extension = 3; /* 2 opcode + 2 displacement */
9464 opcode[1] = opcode[0] + 0x10;
9465 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9466 where_to_put_displacement = &opcode[2];
9467 break;
252b5132 9468
fddf5b5b
AM		 9469 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9470 extension = 4;
9471 opcode[0] ^= 1;
9472 opcode[1] = 3;
9473 opcode[2] = 0xe9;
9474 where_to_put_displacement = &opcode[3];
9475 break;
9476
9477 default:
9478 BAD_CASE (fragP->fr_subtype);
9479 break;
9480 }
252b5132 9481 }
fddf5b5b 9482
7b81dfbb
AJ		 9483 /* If size if less then four we are sure that the operand fits,
9484 but if it's 4, then it could be that the displacement is larger
9485 then -/+ 2GB. */
9486 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9487 && object_64bit
9488 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9489 + ((addressT) 1 << 31))
9490 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9491 {
9492 as_bad_where (fragP->fr_file, fragP->fr_line,
9493 _("jump target out of range"));
9494 /* Make us emit 0. */
9495 displacement_from_opcode_start = extension;
9496 }
47926f60 9497 /* Now put displacement after opcode. */
252b5132
RH		 9498 md_number_to_chars ((char *) where_to_put_displacement,
9499 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9500 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9501 fragP->fr_fix += extension;
9502}
9503\f
7016a5d5 9504/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9505 by our caller that we have all the info we need to fix it up.
9506
7016a5d5
TG		 9507 Parameter valP is the pointer to the value of the bits.
9508
252b5132
RH		 9509 On the 386, immediates, displacements, and data pointers are all in
9510 the same (little-endian) format, so we don't need to care about which
9511 we are handling. */
9512
94f592af 9513void
7016a5d5 9514md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9515{
94f592af 9516 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9517 valueT value = *valP;
252b5132 9518
f86103b7 9519#if !defined (TE_Mach)
93382f6d
AM		 9520 if (fixP->fx_pcrel)
9521 {
9522 switch (fixP->fx_r_type)
9523 {
5865bb77
ILT		 9524 default:
9525 break;
9526
d6ab8113
JB		 9527 case BFD_RELOC_64:
9528 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9529 break;
93382f6d 9530 case BFD_RELOC_32:
ae8887b5 9531 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9532 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9533 break;
9534 case BFD_RELOC_16:
9535 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9536 break;
9537 case BFD_RELOC_8:
9538 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9539 break;
9540 }
9541 }
252b5132 9542
a161fe53 9543 if (fixP->fx_addsy != NULL
31312f95 9544 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9545 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9546 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9547 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9548 && !use_rela_relocations)
252b5132 9549 {
31312f95
AM		 9550 /* This is a hack. There should be a better way to handle this.
9551 This covers for the fact that bfd_install_relocation will
9552 subtract the current location (for partial_inplace, PC relative
9553 relocations); see more below. */
252b5132 9554#ifndef OBJ_AOUT
718ddfc0 9555 if (IS_ELF
252b5132
RH		 9556#ifdef TE_PE
9557 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9558#endif
9559 )
9560 value += fixP->fx_where + fixP->fx_frag->fr_address;
9561#endif
9562#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9563 if (IS_ELF)
252b5132 9564 {
6539b54b 9565 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9566
6539b54b 9567 if ((sym_seg == seg
2f66722d 9568 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9569 && sym_seg != absolute_section))
af65af87 9570 && !generic_force_reloc (fixP))
2f66722d
AM		 9571 {
9572 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9573 bfd_install_relocation subtracts them out again. I think
9574 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9575 it. FIXME. */
9576 value += fixP->fx_where + fixP->fx_frag->fr_address;
9577 }
252b5132
RH		 9578 }
9579#endif
9580#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9581 /* For some reason, the PE format does not store a
9582 section address offset for a PC relative symbol. */
9583 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9584 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9585 value += md_pcrel_from (fixP);
9586#endif
9587 }
fbeb56a4 9588#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9589 if (fixP->fx_addsy != NULL
9590 && S_IS_WEAK (fixP->fx_addsy)
9591 /* PR 16858: Do not modify weak function references. */
9592 && ! fixP->fx_pcrel)
fbeb56a4 9593 {
296a8689
NC		 9594#if !defined (TE_PEP)
9595 /* For x86 PE weak function symbols are neither PC-relative
9596 nor do they set S_IS_FUNCTION. So the only reliable way
9597 to detect them is to check the flags of their containing
9598 section. */
9599 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9600 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9601 ;
9602 else
9603#endif
fbeb56a4
DK		 9604 value -= S_GET_VALUE (fixP->fx_addsy);
9605 }
9606#endif
252b5132
RH		 9607
9608 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9609 and we must not disappoint it. */
252b5132 9610#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9611 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9612 switch (fixP->fx_r_type)
9613 {
9614 case BFD_RELOC_386_PLT32:
3e73aa7c 9615 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9616 /* Make the jump instruction point to the address of the operand. At
9617 runtime we merely add the offset to the actual PLT entry. */
9618 value = -4;
9619 break;
31312f95 9620
13ae64f3
JJ		 9621 case BFD_RELOC_386_TLS_GD:
9622 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9623 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9624 case BFD_RELOC_386_TLS_IE:
9625 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9626 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9627 case BFD_RELOC_X86_64_TLSGD:
9628 case BFD_RELOC_X86_64_TLSLD:
9629 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9630 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9631 value = 0; /* Fully resolved at runtime. No addend. */
9632 /* Fallthrough */
9633 case BFD_RELOC_386_TLS_LE:
9634 case BFD_RELOC_386_TLS_LDO_32:
9635 case BFD_RELOC_386_TLS_LE_32:
9636 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9637 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9638 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9639 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9640 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9641 break;
9642
67a4f2b7
AO		 9643 case BFD_RELOC_386_TLS_DESC_CALL:
9644 case BFD_RELOC_X86_64_TLSDESC_CALL:
9645 value = 0; /* Fully resolved at runtime. No addend. */
9646 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9647 fixP->fx_done = 0;
9648 return;
9649
47926f60
KH		 9650 case BFD_RELOC_VTABLE_INHERIT:
9651 case BFD_RELOC_VTABLE_ENTRY:
9652 fixP->fx_done = 0;
94f592af 9653 return;
47926f60
KH		 9654
9655 default:
9656 break;
9657 }
9658#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9659 *valP = value;
f86103b7 9660#endif /* !defined (TE_Mach) */
3e73aa7c 9661
3e73aa7c 9662 /* Are we finished with this relocation now? */
c6682705 9663 if (fixP->fx_addsy == NULL)
3e73aa7c 9664 fixP->fx_done = 1;
fbeb56a4
DK		 9665#if defined (OBJ_COFF) && defined (TE_PE)
9666 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9667 {
9668 fixP->fx_done = 0;
9669 /* Remember value for tc_gen_reloc. */
9670 fixP->fx_addnumber = value;
9671 /* Clear out the frag for now. */
9672 value = 0;
9673 }
9674#endif
3e73aa7c
JH		 9675 else if (use_rela_relocations)
9676 {
9677 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9678 /* Remember value for tc_gen_reloc. */
9679 fixP->fx_addnumber = value;
3e73aa7c
JH		 9680 value = 0;
9681 }
f86103b7 9682
94f592af 9683 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9684}
252b5132 9685\f
6d4af3c2 9686const char *
499ac353 9687md_atof (int type, char *litP, int *sizeP)
252b5132 9688{
499ac353
NC		 9689 /* This outputs the LITTLENUMs in REVERSE order;
9690 in accord with the bigendian 386. */
9691 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9692}
9693\f
2d545b82 9694static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9695
252b5132 9696static char *
e3bb37b5 9697output_invalid (int c)
252b5132 9698{
3882b010 9699 if (ISPRINT (c))
f9f21a03
L		 9700 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9701 "'%c'", c);
252b5132 9702 else
f9f21a03 9703 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9704 "(0x%x)", (unsigned char) c);
252b5132
RH		 9705 return output_invalid_buf;
9706}
9707
af6bdddf 9708/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9709
9710static const reg_entry *
4d1bb795 9711parse_real_register (char *reg_string, char **end_op)
252b5132 9712{
af6bdddf
AM		 9713 char *s = reg_string;
9714 char *p;
252b5132
RH		 9715 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9716 const reg_entry *r;
9717
9718 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9719 if (*s == REGISTER_PREFIX)
9720 ++s;
9721
9722 if (is_space_char (*s))
9723 ++s;
9724
9725 p = reg_name_given;
af6bdddf 9726 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9727 {
9728 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9729 return (const reg_entry *) NULL;
9730 s++;
252b5132
RH		 9731 }
9732
6588847e
DN		 9733 /* For naked regs, make sure that we are not dealing with an identifier.
9734 This prevents confusing an identifier like `eax_var' with register
9735 `eax'. */
9736 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9737 return (const reg_entry *) NULL;
9738
af6bdddf 9739 *end_op = s;
252b5132
RH		 9740
9741 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9742
5f47d35b 9743 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9744 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9745 {
5f47d35b
AM		 9746 if (is_space_char (*s))
9747 ++s;
9748 if (*s == '(')
9749 {
af6bdddf 9750 ++s;
5f47d35b
AM		 9751 if (is_space_char (*s))
9752 ++s;
9753 if (*s >= '0' && *s <= '7')
9754 {
db557034 9755 int fpr = *s - '0';
af6bdddf 9756 ++s;
5f47d35b
AM		 9757 if (is_space_char (*s))
9758 ++s;
9759 if (*s == ')')
9760 {
9761 *end_op = s + 1;
1e9cc1c2 9762 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9763 know (r);
9764 return r + fpr;
5f47d35b 9765 }
5f47d35b 9766 }
47926f60 9767 /* We have "%st(" then garbage. */
5f47d35b
AM		 9768 return (const reg_entry *) NULL;
9769 }
9770 }
9771
a60de03c
JB		 9772 if (r == NULL || allow_pseudo_reg)
9773 return r;
9774
0dfbf9d7 9775 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9776 return (const reg_entry *) NULL;
9777
192dc9c6
JB		 9778 if ((r->reg_type.bitfield.reg32
9779 || r->reg_type.bitfield.sreg3
9780 || r->reg_type.bitfield.control
9781 || r->reg_type.bitfield.debug
9782 || r->reg_type.bitfield.test)
9783 && !cpu_arch_flags.bitfield.cpui386)
9784 return (const reg_entry *) NULL;
9785
309d3373
JB		 9786 if (r->reg_type.bitfield.floatreg
9787 && !cpu_arch_flags.bitfield.cpu8087
9788 && !cpu_arch_flags.bitfield.cpu287
9789 && !cpu_arch_flags.bitfield.cpu387)
9790 return (const reg_entry *) NULL;
9791
1848e567 9792 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9793 return (const reg_entry *) NULL;
9794
1848e567 9795 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9796 return (const reg_entry *) NULL;
9797
1848e567 9798 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9799 return (const reg_entry *) NULL;
9800
1848e567
L		 9801 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9802 return (const reg_entry *) NULL;
9803
9804 if (r->reg_type.bitfield.regmask
9805 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9806 return (const reg_entry *) NULL;
9807
db51cc60 9808 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9809 if (!allow_index_reg
db51cc60
L		 9810 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9811 return (const reg_entry *) NULL;
9812
43234a1e
L		 9813 /* Upper 16 vector register is only available with VREX in 64bit
9814 mode. */
9815 if ((r->reg_flags & RegVRex))
9816 {
86fa6981
L		 9817 if (i.vec_encoding == vex_encoding_default)
9818 i.vec_encoding = vex_encoding_evex;
9819
43234a1e 9820 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9821 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9822 || flag_code != CODE_64BIT)
9823 return (const reg_entry *) NULL;
43234a1e
L		 9824 }
9825
a60de03c
JB		 9826 if (((r->reg_flags & (RegRex64 | RegRex))
9827 || r->reg_type.bitfield.reg64)
40fb9820 9828 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9829 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9830 && flag_code != CODE_64BIT)
20f0a1fc 9831 return (const reg_entry *) NULL;
1ae00879 9832
b7240065
JB		 9833 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9834 return (const reg_entry *) NULL;
9835
252b5132
RH		 9836 return r;
9837}
4d1bb795
JB		 9838
9839/* REG_STRING starts *before* REGISTER_PREFIX. */
9840
9841static const reg_entry *
9842parse_register (char *reg_string, char **end_op)
9843{
9844 const reg_entry *r;
9845
9846 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9847 r = parse_real_register (reg_string, end_op);
9848 else
9849 r = NULL;
9850 if (!r)
9851 {
9852 char *save = input_line_pointer;
9853 char c;
9854 symbolS *symbolP;
9855
9856 input_line_pointer = reg_string;
d02603dc 9857 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9858 symbolP = symbol_find (reg_string);
9859 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9860 {
9861 const expressionS *e = symbol_get_value_expression (symbolP);
9862
0398aac5 9863 know (e->X_op == O_register);
4eed87de 9864 know (e->X_add_number >= 0
c3fe08fa 9865 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9866 r = i386_regtab + e->X_add_number;
d3bb6b49 9867 if ((r->reg_flags & RegVRex))
86fa6981 9868 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9869 *end_op = input_line_pointer;
9870 }
9871 *input_line_pointer = c;
9872 input_line_pointer = save;
9873 }
9874 return r;
9875}
9876
9877int
9878i386_parse_name (char *name, expressionS *e, char *nextcharP)
9879{
9880 const reg_entry *r;
9881 char *end = input_line_pointer;
9882
9883 *end = *nextcharP;
9884 r = parse_register (name, &input_line_pointer);
9885 if (r && end <= input_line_pointer)
9886 {
9887 *nextcharP = *input_line_pointer;
9888 *input_line_pointer = 0;
9889 e->X_op = O_register;
9890 e->X_add_number = r - i386_regtab;
9891 return 1;
9892 }
9893 input_line_pointer = end;
9894 *end = 0;
ee86248c 9895 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9896}
9897
9898void
9899md_operand (expressionS *e)
9900{
ee86248c
JB		 9901 char *end;
9902 const reg_entry *r;
4d1bb795 9903
ee86248c
JB		 9904 switch (*input_line_pointer)
9905 {
9906 case REGISTER_PREFIX:
9907 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9908 if (r)
9909 {
9910 e->X_op = O_register;
9911 e->X_add_number = r - i386_regtab;
9912 input_line_pointer = end;
9913 }
ee86248c
JB		 9914 break;
9915
9916 case '[':
9c2799c2 9917 gas_assert (intel_syntax);
ee86248c
JB		 9918 end = input_line_pointer++;
9919 expression (e);
9920 if (*input_line_pointer == ']')
9921 {
9922 ++input_line_pointer;
9923 e->X_op_symbol = make_expr_symbol (e);
9924 e->X_add_symbol = NULL;
9925 e->X_add_number = 0;
9926 e->X_op = O_index;
9927 }
9928 else
9929 {
9930 e->X_op = O_absent;
9931 input_line_pointer = end;
9932 }
9933 break;
4d1bb795
JB		 9934 }
9935}
9936
252b5132 9937\f
4cc782b5 9938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9939const char *md_shortopts = "kVQ:sqn";
252b5132 9940#else
12b55ccc 9941const char *md_shortopts = "qn";
252b5132 9942#endif
6e0b89ee 9943
3e73aa7c 9944#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9945#define OPTION_64 (OPTION_MD_BASE + 1)
9946#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9947#define OPTION_MARCH (OPTION_MD_BASE + 3)
9948#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9949#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9950#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9951#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9952#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9953#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9954#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9955#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9956#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9957#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9958#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9959#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9960#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9961#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9962#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9963#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9964#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9965#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9966#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9967#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9968#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9969#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9970
99ad8390
NC		 9971struct option md_longopts[] =
9972{
3e73aa7c 9973 {"32", no_argument, NULL, OPTION_32},
321098a5 9974#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9975 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9976 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9977#endif
9978#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9979 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9980 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9981#endif
b3b91714 9982 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9983 {"march", required_argument, NULL, OPTION_MARCH},
9984 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9985 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9986 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9987 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9988 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9989 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9990 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9991 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9992 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9993 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9994 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9995 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9996 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9997# if defined (TE_PE) || defined (TE_PEP)
9998 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9999#endif
d1982f93 10000 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10001 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10002 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10003 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10004 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10005 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10006 {NULL, no_argument, NULL, 0}
10007};
10008size_t md_longopts_size = sizeof (md_longopts);
10009
10010int
17b9d67d 10011md_parse_option (int c, const char *arg)
252b5132 10012{
91d6fa6a 10013 unsigned int j;
293f5f65 10014 char *arch, *next, *saved;
9103f4f4 10015
252b5132
RH		 10016 switch (c)
10017 {
12b55ccc
L		 10018 case 'n':
10019 optimize_align_code = 0;
10020 break;
10021
a38cf1db
AM		 10022 case 'q':
10023 quiet_warnings = 1;
252b5132
RH		 10024 break;
10025
10026#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10027 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10028 should be emitted or not. FIXME: Not implemented. */
10029 case 'Q':
252b5132
RH		 10030 break;
10031
10032 /* -V: SVR4 argument to print version ID. */
10033 case 'V':
10034 print_version_id ();
10035 break;
10036
a38cf1db
AM		 10037 /* -k: Ignore for FreeBSD compatibility. */
10038 case 'k':
252b5132 10039 break;
4cc782b5
ILT		 10040
10041 case 's':
10042 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10043 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10044 break;
8dcea932
L		 10045
10046 case OPTION_MSHARED:
10047 shared = 1;
10048 break;
99ad8390 10049#endif
321098a5 10050#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10051 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10052 case OPTION_64:
10053 {
10054 const char **list, **l;
10055
3e73aa7c
JH		 10056 list = bfd_target_list ();
10057 for (l = list; *l != NULL; l++)
8620418b 10058 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10059 || strcmp (*l, "coff-x86-64") == 0
10060 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10061 || strcmp (*l, "pei-x86-64") == 0
10062 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10063 {
10064 default_arch = "x86_64";
10065 break;
10066 }
3e73aa7c 10067 if (*l == NULL)
2b5d6a91 10068 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10069 free (list);
10070 }
10071 break;
10072#endif
252b5132 10073
351f65ca 10074#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10075 case OPTION_X32:
351f65ca
L		 10076 if (IS_ELF)
10077 {
10078 const char **list, **l;
10079
10080 list = bfd_target_list ();
10081 for (l = list; *l != NULL; l++)
10082 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10083 {
10084 default_arch = "x86_64:32";
10085 break;
10086 }
10087 if (*l == NULL)
2b5d6a91 10088 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10089 free (list);
10090 }
10091 else
10092 as_fatal (_("32bit x86_64 is only supported for ELF"));
10093 break;
10094#endif
10095
6e0b89ee
AM		 10096 case OPTION_32:
10097 default_arch = "i386";
10098 break;
10099
b3b91714
AM		 10100 case OPTION_DIVIDE:
10101#ifdef SVR4_COMMENT_CHARS
10102 {
10103 char *n, *t;
10104 const char *s;
10105
add39d23 10106 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10107 t = n;
10108 for (s = i386_comment_chars; *s != '\0'; s++)
10109 if (*s != '/')
10110 *t++ = *s;
10111 *t = '\0';
10112 i386_comment_chars = n;
10113 }
10114#endif
10115 break;
10116
9103f4f4 10117 case OPTION_MARCH:
293f5f65
L		 10118 saved = xstrdup (arg);
10119 arch = saved;
10120 /* Allow -march=+nosse. */
10121 if (*arch == '+')
10122 arch++;
6305a203 10123 do
9103f4f4 10124 {
6305a203 10125 if (*arch == '.')
2b5d6a91 10126 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10127 next = strchr (arch, '+');
10128 if (next)
10129 *next++ = '\0';
91d6fa6a 10130 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10131 {
91d6fa6a 10132 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10133 {
6305a203 10134 /* Processor. */
1ded5609
JB		 10135 if (! cpu_arch[j].flags.bitfield.cpui386)
10136 continue;
10137
91d6fa6a 10138 cpu_arch_name = cpu_arch[j].name;
6305a203 10139 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10140 cpu_arch_flags = cpu_arch[j].flags;
10141 cpu_arch_isa = cpu_arch[j].type;
10142 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10143 if (!cpu_arch_tune_set)
10144 {
10145 cpu_arch_tune = cpu_arch_isa;
10146 cpu_arch_tune_flags = cpu_arch_isa_flags;
10147 }
10148 break;
10149 }
91d6fa6a
NC		 10150 else if (*cpu_arch [j].name == '.'
10151 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10152 {
33eaf5de 10153 /* ISA extension. */
6305a203 10154 i386_cpu_flags flags;
309d3373 10155
293f5f65
L		 10156 flags = cpu_flags_or (cpu_arch_flags,
10157 cpu_arch[j].flags);
81486035 10158
5b64d091 10159 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10160 {
10161 if (cpu_sub_arch_name)
10162 {
10163 char *name = cpu_sub_arch_name;
10164 cpu_sub_arch_name = concat (name,
91d6fa6a 10165 cpu_arch[j].name,
1bf57e9f 10166 (const char *) NULL);
6305a203
L		 10167 free (name);
10168 }
10169 else
91d6fa6a 10170 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10171 cpu_arch_flags = flags;
a586129e 10172 cpu_arch_isa_flags = flags;
6305a203
L		 10173 }
10174 break;
ccc9c027 10175 }
9103f4f4 10176 }
6305a203 10177
293f5f65
L		 10178 if (j >= ARRAY_SIZE (cpu_arch))
10179 {
33eaf5de 10180 /* Disable an ISA extension. */
293f5f65
L		 10181 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10182 if (strcmp (arch, cpu_noarch [j].name) == 0)
10183 {
10184 i386_cpu_flags flags;
10185
10186 flags = cpu_flags_and_not (cpu_arch_flags,
10187 cpu_noarch[j].flags);
10188 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10189 {
10190 if (cpu_sub_arch_name)
10191 {
10192 char *name = cpu_sub_arch_name;
10193 cpu_sub_arch_name = concat (arch,
10194 (const char *) NULL);
10195 free (name);
10196 }
10197 else
10198 cpu_sub_arch_name = xstrdup (arch);
10199 cpu_arch_flags = flags;
10200 cpu_arch_isa_flags = flags;
10201 }
10202 break;
10203 }
10204
10205 if (j >= ARRAY_SIZE (cpu_noarch))
10206 j = ARRAY_SIZE (cpu_arch);
10207 }
10208
91d6fa6a 10209 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10210 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10211
10212 arch = next;
9103f4f4 10213 }
293f5f65
L		 10214 while (next != NULL);
10215 free (saved);
9103f4f4
L		 10216 break;
10217
10218 case OPTION_MTUNE:
10219 if (*arg == '.')
2b5d6a91 10220 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10221 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10222 {
91d6fa6a 10223 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10224 {
ccc9c027 10225 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10226 cpu_arch_tune = cpu_arch [j].type;
10227 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10228 break;
10229 }
10230 }
91d6fa6a 10231 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10232 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10233 break;
10234
1efbbeb4
L		 10235 case OPTION_MMNEMONIC:
10236 if (strcasecmp (arg, "att") == 0)
10237 intel_mnemonic = 0;
10238 else if (strcasecmp (arg, "intel") == 0)
10239 intel_mnemonic = 1;
10240 else
2b5d6a91 10241 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10242 break;
10243
10244 case OPTION_MSYNTAX:
10245 if (strcasecmp (arg, "att") == 0)
10246 intel_syntax = 0;
10247 else if (strcasecmp (arg, "intel") == 0)
10248 intel_syntax = 1;
10249 else
2b5d6a91 10250 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10251 break;
10252
10253 case OPTION_MINDEX_REG:
10254 allow_index_reg = 1;
10255 break;
10256
10257 case OPTION_MNAKED_REG:
10258 allow_naked_reg = 1;
10259 break;
10260
10261 case OPTION_MOLD_GCC:
10262 old_gcc = 1;
1efbbeb4
L		 10263 break;
10264
c0f3af97
L		 10265 case OPTION_MSSE2AVX:
10266 sse2avx = 1;
10267 break;
10268
daf50ae7
L		 10269 case OPTION_MSSE_CHECK:
10270 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10271 sse_check = check_error;
daf50ae7 10272 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10273 sse_check = check_warning;
daf50ae7 10274 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10275 sse_check = check_none;
daf50ae7 10276 else
2b5d6a91 10277 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10278 break;
10279
7bab8ab5
JB		 10280 case OPTION_MOPERAND_CHECK:
10281 if (strcasecmp (arg, "error") == 0)
10282 operand_check = check_error;
10283 else if (strcasecmp (arg, "warning") == 0)
10284 operand_check = check_warning;
10285 else if (strcasecmp (arg, "none") == 0)
10286 operand_check = check_none;
10287 else
10288 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10289 break;
10290
539f890d
L		 10291 case OPTION_MAVXSCALAR:
10292 if (strcasecmp (arg, "128") == 0)
10293 avxscalar = vex128;
10294 else if (strcasecmp (arg, "256") == 0)
10295 avxscalar = vex256;
10296 else
2b5d6a91 10297 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10298 break;
10299
7e8b059b
L		 10300 case OPTION_MADD_BND_PREFIX:
10301 add_bnd_prefix = 1;
10302 break;
10303
43234a1e
L		 10304 case OPTION_MEVEXLIG:
10305 if (strcmp (arg, "128") == 0)
10306 evexlig = evexl128;
10307 else if (strcmp (arg, "256") == 0)
10308 evexlig = evexl256;
10309 else if (strcmp (arg, "512") == 0)
10310 evexlig = evexl512;
10311 else
10312 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10313 break;
10314
d3d3c6db
IT		 10315 case OPTION_MEVEXRCIG:
10316 if (strcmp (arg, "rne") == 0)
10317 evexrcig = rne;
10318 else if (strcmp (arg, "rd") == 0)
10319 evexrcig = rd;
10320 else if (strcmp (arg, "ru") == 0)
10321 evexrcig = ru;
10322 else if (strcmp (arg, "rz") == 0)
10323 evexrcig = rz;
10324 else
10325 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10326 break;
10327
43234a1e
L		 10328 case OPTION_MEVEXWIG:
10329 if (strcmp (arg, "0") == 0)
10330 evexwig = evexw0;
10331 else if (strcmp (arg, "1") == 0)
10332 evexwig = evexw1;
10333 else
10334 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10335 break;
10336
167ad85b
TG		 10337# if defined (TE_PE) || defined (TE_PEP)
10338 case OPTION_MBIG_OBJ:
10339 use_big_obj = 1;
10340 break;
10341#endif
10342
d1982f93 10343 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10344 if (strcasecmp (arg, "yes") == 0)
10345 omit_lock_prefix = 1;
10346 else if (strcasecmp (arg, "no") == 0)
10347 omit_lock_prefix = 0;
10348 else
10349 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10350 break;
10351
e4e00185
AS		 10352 case OPTION_MFENCE_AS_LOCK_ADD:
10353 if (strcasecmp (arg, "yes") == 0)
10354 avoid_fence = 1;
10355 else if (strcasecmp (arg, "no") == 0)
10356 avoid_fence = 0;
10357 else
10358 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10359 break;
10360
0cb4071e
L		 10361 case OPTION_MRELAX_RELOCATIONS:
10362 if (strcasecmp (arg, "yes") == 0)
10363 generate_relax_relocations = 1;
10364 else if (strcasecmp (arg, "no") == 0)
10365 generate_relax_relocations = 0;
10366 else
10367 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10368 break;
10369
5db04b09 10370 case OPTION_MAMD64:
e89c5eaa 10371 intel64 = 0;
5db04b09
L		 10372 break;
10373
10374 case OPTION_MINTEL64:
e89c5eaa 10375 intel64 = 1;
5db04b09
L		 10376 break;
10377
252b5132
RH		 10378 default:
10379 return 0;
10380 }
10381 return 1;
10382}
10383
8a2c8fef
L		 10384#define MESSAGE_TEMPLATE \
10385" "
10386
293f5f65
L		 10387static char *
10388output_message (FILE *stream, char *p, char *message, char *start,
10389 int *left_p, const char *name, int len)
10390{
10391 int size = sizeof (MESSAGE_TEMPLATE);
10392 int left = *left_p;
10393
10394 /* Reserve 2 spaces for ", " or ",\0" */
10395 left -= len + 2;
10396
10397 /* Check if there is any room. */
10398 if (left >= 0)
10399 {
10400 if (p != start)
10401 {
10402 *p++ = ',';
10403 *p++ = ' ';
10404 }
10405 p = mempcpy (p, name, len);
10406 }
10407 else
10408 {
10409 /* Output the current message now and start a new one. */
10410 *p++ = ',';
10411 *p = '\0';
10412 fprintf (stream, "%s\n", message);
10413 p = start;
10414 left = size - (start - message) - len - 2;
10415
10416 gas_assert (left >= 0);
10417
10418 p = mempcpy (p, name, len);
10419 }
10420
10421 *left_p = left;
10422 return p;
10423}
10424
8a2c8fef 10425static void
1ded5609 10426show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10427{
10428 static char message[] = MESSAGE_TEMPLATE;
10429 char *start = message + 27;
10430 char *p;
10431 int size = sizeof (MESSAGE_TEMPLATE);
10432 int left;
10433 const char *name;
10434 int len;
10435 unsigned int j;
10436
10437 p = start;
10438 left = size - (start - message);
10439 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10440 {
10441 /* Should it be skipped? */
10442 if (cpu_arch [j].skip)
10443 continue;
10444
10445 name = cpu_arch [j].name;
10446 len = cpu_arch [j].len;
10447 if (*name == '.')
10448 {
10449 /* It is an extension. Skip if we aren't asked to show it. */
10450 if (ext)
10451 {
10452 name++;
10453 len--;
10454 }
10455 else
10456 continue;
10457 }
10458 else if (ext)
10459 {
10460 /* It is an processor. Skip if we show only extension. */
10461 continue;
10462 }
1ded5609
JB		 10463 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10464 {
10465 /* It is an impossible processor - skip. */
10466 continue;
10467 }
8a2c8fef 10468
293f5f65 10469 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10470 }
10471
293f5f65
L		 10472 /* Display disabled extensions. */
10473 if (ext)
10474 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10475 {
10476 name = cpu_noarch [j].name;
10477 len = cpu_noarch [j].len;
10478 p = output_message (stream, p, message, start, &left, name,
10479 len);
10480 }
10481
8a2c8fef
L		 10482 *p = '\0';
10483 fprintf (stream, "%s\n", message);
10484}
10485
252b5132 10486void
8a2c8fef 10487md_show_usage (FILE *stream)
252b5132 10488{
4cc782b5
ILT		 10489#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10490 fprintf (stream, _("\
a38cf1db
AM		 10491 -Q ignored\n\
10492 -V print assembler version number\n\
b3b91714
AM		 10493 -k ignored\n"));
10494#endif
10495 fprintf (stream, _("\
12b55ccc 10496 -n Do not optimize code alignment\n\
b3b91714
AM		 10497 -q quieten some warnings\n"));
10498#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10499 fprintf (stream, _("\
a38cf1db 10500 -s ignored\n"));
b3b91714 10501#endif
321098a5
L		 10502#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10503 || defined (TE_PE) || defined (TE_PEP))
751d281c 10504 fprintf (stream, _("\
570561f7 10505 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10506#endif
b3b91714
AM		 10507#ifdef SVR4_COMMENT_CHARS
10508 fprintf (stream, _("\
10509 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10510#else
10511 fprintf (stream, _("\
b3b91714 10512 --divide ignored\n"));
4cc782b5 10513#endif
9103f4f4 10514 fprintf (stream, _("\
6305a203 10515 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10516 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10517 show_arch (stream, 0, 1);
8a2c8fef
L		 10518 fprintf (stream, _("\
10519 EXTENSION is combination of:\n"));
1ded5609 10520 show_arch (stream, 1, 0);
6305a203 10521 fprintf (stream, _("\
8a2c8fef 10522 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10523 show_arch (stream, 0, 0);
ba104c83 10524 fprintf (stream, _("\
c0f3af97
L		 10525 -msse2avx encode SSE instructions with VEX prefix\n"));
10526 fprintf (stream, _("\
daf50ae7
L		 10527 -msse-check=[none|error|warning]\n\
10528 check SSE instructions\n"));
10529 fprintf (stream, _("\
7bab8ab5
JB		 10530 -moperand-check=[none|error|warning]\n\
10531 check operand combinations for validity\n"));
10532 fprintf (stream, _("\
539f890d
L		 10533 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10534 length\n"));
10535 fprintf (stream, _("\
43234a1e
L		 10536 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10537 length\n"));
10538 fprintf (stream, _("\
10539 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10540 for EVEX.W bit ignored instructions\n"));
10541 fprintf (stream, _("\
d3d3c6db
IT		 10542 -mevexrcig=[rne|rd|ru|rz]\n\
10543 encode EVEX instructions with specific EVEX.RC value\n\
10544 for SAE-only ignored instructions\n"));
10545 fprintf (stream, _("\
ba104c83
L		 10546 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10547 fprintf (stream, _("\
10548 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10549 fprintf (stream, _("\
10550 -mindex-reg support pseudo index registers\n"));
10551 fprintf (stream, _("\
10552 -mnaked-reg don't require `%%' prefix for registers\n"));
10553 fprintf (stream, _("\
10554 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10555 fprintf (stream, _("\
10556 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10557 fprintf (stream, _("\
10558 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10559# if defined (TE_PE) || defined (TE_PEP)
10560 fprintf (stream, _("\
10561 -mbig-obj generate big object files\n"));
10562#endif
d022bddd
IT		 10563 fprintf (stream, _("\
10564 -momit-lock-prefix=[no|yes]\n\
10565 strip all lock prefixes\n"));
5db04b09 10566 fprintf (stream, _("\
e4e00185
AS		 10567 -mfence-as-lock-add=[no|yes]\n\
10568 encode lfence, mfence and sfence as\n\
10569 lock addl $0x0, (%%{re}sp)\n"));
10570 fprintf (stream, _("\
0cb4071e
L		 10571 -mrelax-relocations=[no|yes]\n\
10572 generate relax relocations\n"));
10573 fprintf (stream, _("\
5db04b09
L		 10574 -mamd64 accept only AMD64 ISA\n"));
10575 fprintf (stream, _("\
10576 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10577}
10578
3e73aa7c 10579#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10580 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10581 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10582
10583/* Pick the target format to use. */
10584
47926f60 10585const char *
e3bb37b5 10586i386_target_format (void)
252b5132 10587{
351f65ca
L		 10588 if (!strncmp (default_arch, "x86_64", 6))
10589 {
10590 update_code_flag (CODE_64BIT, 1);
10591 if (default_arch[6] == '\0')
7f56bc95 10592 x86_elf_abi = X86_64_ABI;
351f65ca 10593 else
7f56bc95 10594 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10595 }
3e73aa7c 10596 else if (!strcmp (default_arch, "i386"))
78f12dd3 10597 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10598 else if (!strcmp (default_arch, "iamcu"))
10599 {
10600 update_code_flag (CODE_32BIT, 1);
10601 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10602 {
10603 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10604 cpu_arch_name = "iamcu";
10605 cpu_sub_arch_name = NULL;
10606 cpu_arch_flags = iamcu_flags;
10607 cpu_arch_isa = PROCESSOR_IAMCU;
10608 cpu_arch_isa_flags = iamcu_flags;
10609 if (!cpu_arch_tune_set)
10610 {
10611 cpu_arch_tune = cpu_arch_isa;
10612 cpu_arch_tune_flags = cpu_arch_isa_flags;
10613 }
10614 }
8d471ec1 10615 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10616 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10617 cpu_arch_name);
10618 }
3e73aa7c 10619 else
2b5d6a91 10620 as_fatal (_("unknown architecture"));
89507696
JB		 10621
10622 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10623 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10624 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10625 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10626
252b5132
RH		 10627 switch (OUTPUT_FLAVOR)
10628 {
9384f2ff 10629#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10630 case bfd_target_aout_flavour:
47926f60 10631 return AOUT_TARGET_FORMAT;
4c63da97 10632#endif
9384f2ff
AM		 10633#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10634# if defined (TE_PE) || defined (TE_PEP)
10635 case bfd_target_coff_flavour:
167ad85b
TG		 10636 if (flag_code == CODE_64BIT)
10637 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10638 else
10639 return "pe-i386";
9384f2ff 10640# elif defined (TE_GO32)
0561d57c
JK		 10641 case bfd_target_coff_flavour:
10642 return "coff-go32";
9384f2ff 10643# else
252b5132
RH		 10644 case bfd_target_coff_flavour:
10645 return "coff-i386";
9384f2ff 10646# endif
4c63da97 10647#endif
3e73aa7c 10648#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10649 case bfd_target_elf_flavour:
3e73aa7c 10650 {
351f65ca
L		 10651 const char *format;
10652
10653 switch (x86_elf_abi)
4fa24527 10654 {
351f65ca
L		 10655 default:
10656 format = ELF_TARGET_FORMAT;
10657 break;
7f56bc95 10658 case X86_64_ABI:
351f65ca 10659 use_rela_relocations = 1;
4fa24527 10660 object_64bit = 1;
351f65ca
L		 10661 format = ELF_TARGET_FORMAT64;
10662 break;
7f56bc95 10663 case X86_64_X32_ABI:
4fa24527 10664 use_rela_relocations = 1;
351f65ca 10665 object_64bit = 1;
862be3fb 10666 disallow_64bit_reloc = 1;
351f65ca
L		 10667 format = ELF_TARGET_FORMAT32;
10668 break;
4fa24527 10669 }
3632d14b 10670 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10671 {
7f56bc95 10672 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10673 as_fatal (_("Intel L1OM is 64bit only"));
10674 return ELF_TARGET_L1OM_FORMAT;
10675 }
b49f93f6 10676 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10677 {
10678 if (x86_elf_abi != X86_64_ABI)
10679 as_fatal (_("Intel K1OM is 64bit only"));
10680 return ELF_TARGET_K1OM_FORMAT;
10681 }
81486035
L		 10682 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10683 {
10684 if (x86_elf_abi != I386_ABI)
10685 as_fatal (_("Intel MCU is 32bit only"));
10686 return ELF_TARGET_IAMCU_FORMAT;
10687 }
8a9036a4 10688 else
351f65ca 10689 return format;
3e73aa7c 10690 }
e57f8c65
TG		 10691#endif
10692#if defined (OBJ_MACH_O)
10693 case bfd_target_mach_o_flavour:
d382c579
TG		 10694 if (flag_code == CODE_64BIT)
10695 {
10696 use_rela_relocations = 1;
10697 object_64bit = 1;
10698 return "mach-o-x86-64";
10699 }
10700 else
10701 return "mach-o-i386";
4c63da97 10702#endif
252b5132
RH		 10703 default:
10704 abort ();
10705 return NULL;
10706 }
10707}
10708
47926f60 10709#endif /* OBJ_MAYBE_ more than one */
252b5132 10710\f
252b5132 10711symbolS *
7016a5d5 10712md_undefined_symbol (char *name)
252b5132 10713{
18dc2407
ILT		 10714 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10715 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10716 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10717 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10718 {
10719 if (!GOT_symbol)
10720 {
10721 if (symbol_find (name))
10722 as_bad (_("GOT already in symbol table"));
10723 GOT_symbol = symbol_new (name, undefined_section,
10724 (valueT) 0, &zero_address_frag);
10725 };
10726 return GOT_symbol;
10727 }
252b5132
RH		 10728 return 0;
10729}
10730
10731/* Round up a section size to the appropriate boundary. */
47926f60 10732
252b5132 10733valueT
7016a5d5 10734md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10735{
4c63da97
AM		 10736#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10737 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10738 {
10739 /* For a.out, force the section size to be aligned. If we don't do
10740 this, BFD will align it for us, but it will not write out the
10741 final bytes of the section. This may be a bug in BFD, but it is
10742 easier to fix it here since that is how the other a.out targets
10743 work. */
10744 int align;
10745
10746 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10747 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10748 }
252b5132
RH		 10749#endif
10750
10751 return size;
10752}
10753
10754/* On the i386, PC-relative offsets are relative to the start of the
10755 next instruction. That is, the address of the offset, plus its
10756 size, since the offset is always the last part of the insn. */
10757
10758long
e3bb37b5 10759md_pcrel_from (fixS *fixP)
252b5132
RH		 10760{
10761 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10762}
10763
10764#ifndef I386COFF
10765
10766static void
e3bb37b5 10767s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10768{
29b0f896 10769 int temp;
252b5132 10770
8a75718c
JB		 10771#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10772 if (IS_ELF)
10773 obj_elf_section_change_hook ();
10774#endif
252b5132
RH		 10775 temp = get_absolute_expression ();
10776 subseg_set (bss_section, (subsegT) temp);
10777 demand_empty_rest_of_line ();
10778}
10779
10780#endif
10781
252b5132 10782void
e3bb37b5 10783i386_validate_fix (fixS *fixp)
252b5132 10784{
02a86693 10785 if (fixp->fx_subsy)
252b5132 10786 {
02a86693 10787 if (fixp->fx_subsy == GOT_symbol)
23df1078 10788 {
02a86693
L		 10789 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10790 {
10791 if (!object_64bit)
10792 abort ();
10793#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10794 if (fixp->fx_tcbit2)
56ceb5b5
L		 10795 fixp->fx_r_type = (fixp->fx_tcbit
10796 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10797 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10798 else
10799#endif
10800 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10801 }
d6ab8113 10802 else
02a86693
L		 10803 {
10804 if (!object_64bit)
10805 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10806 else
10807 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10808 }
10809 fixp->fx_subsy = 0;
23df1078 10810 }
252b5132 10811 }
02a86693
L		 10812#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10813 else if (!object_64bit)
10814 {
10815 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10816 && fixp->fx_tcbit2)
10817 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10818 }
10819#endif
252b5132
RH		 10820}
10821
252b5132 10822arelent *
7016a5d5 10823tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10824{
10825 arelent *rel;
10826 bfd_reloc_code_real_type code;
10827
10828 switch (fixp->fx_r_type)
10829 {
8ce3d284 10830#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10831 case BFD_RELOC_SIZE32:
10832 case BFD_RELOC_SIZE64:
10833 if (S_IS_DEFINED (fixp->fx_addsy)
10834 && !S_IS_EXTERNAL (fixp->fx_addsy))
10835 {
10836 /* Resolve size relocation against local symbol to size of
10837 the symbol plus addend. */
10838 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10839 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10840 && !fits_in_unsigned_long (value))
10841 as_bad_where (fixp->fx_file, fixp->fx_line,
10842 _("symbol size computation overflow"));
10843 fixp->fx_addsy = NULL;
10844 fixp->fx_subsy = NULL;
10845 md_apply_fix (fixp, (valueT *) &value, NULL);
10846 return NULL;
10847 }
8ce3d284 10848#endif
1a0670f3 10849 /* Fall through. */
8fd4256d 10850
3e73aa7c
JH		 10851 case BFD_RELOC_X86_64_PLT32:
10852 case BFD_RELOC_X86_64_GOT32:
10853 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10854 case BFD_RELOC_X86_64_GOTPCRELX:
10855 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10856 case BFD_RELOC_386_PLT32:
10857 case BFD_RELOC_386_GOT32:
02a86693 10858 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10859 case BFD_RELOC_386_GOTOFF:
10860 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10861 case BFD_RELOC_386_TLS_GD:
10862 case BFD_RELOC_386_TLS_LDM:
10863 case BFD_RELOC_386_TLS_LDO_32:
10864 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10865 case BFD_RELOC_386_TLS_IE:
10866 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10867 case BFD_RELOC_386_TLS_LE_32:
10868 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10869 case BFD_RELOC_386_TLS_GOTDESC:
10870 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10871 case BFD_RELOC_X86_64_TLSGD:
10872 case BFD_RELOC_X86_64_TLSLD:
10873 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10874 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10875 case BFD_RELOC_X86_64_GOTTPOFF:
10876 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10877 case BFD_RELOC_X86_64_TPOFF64:
10878 case BFD_RELOC_X86_64_GOTOFF64:
10879 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10880 case BFD_RELOC_X86_64_GOT64:
10881 case BFD_RELOC_X86_64_GOTPCREL64:
10882 case BFD_RELOC_X86_64_GOTPC64:
10883 case BFD_RELOC_X86_64_GOTPLT64:
10884 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10885 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10886 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10887 case BFD_RELOC_RVA:
10888 case BFD_RELOC_VTABLE_ENTRY:
10889 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10890#ifdef TE_PE
10891 case BFD_RELOC_32_SECREL:
10892#endif
252b5132
RH		 10893 code = fixp->fx_r_type;
10894 break;
dbbaec26
L		 10895 case BFD_RELOC_X86_64_32S:
10896 if (!fixp->fx_pcrel)
10897 {
10898 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10899 code = fixp->fx_r_type;
10900 break;
10901 }
1a0670f3 10902 /* Fall through. */
252b5132 10903 default:
93382f6d 10904 if (fixp->fx_pcrel)
252b5132 10905 {
93382f6d
AM		 10906 switch (fixp->fx_size)
10907 {
10908 default:
b091f402
AM		 10909 as_bad_where (fixp->fx_file, fixp->fx_line,
10910 _("can not do %d byte pc-relative relocation"),
10911 fixp->fx_size);
93382f6d
AM		 10912 code = BFD_RELOC_32_PCREL;
10913 break;
10914 case 1: code = BFD_RELOC_8_PCREL; break;
10915 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10916 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10917#ifdef BFD64
10918 case 8: code = BFD_RELOC_64_PCREL; break;
10919#endif
93382f6d
AM		 10920 }
10921 }
10922 else
10923 {
10924 switch (fixp->fx_size)
10925 {
10926 default:
b091f402
AM		 10927 as_bad_where (fixp->fx_file, fixp->fx_line,
10928 _("can not do %d byte relocation"),
10929 fixp->fx_size);
93382f6d
AM		 10930 code = BFD_RELOC_32;
10931 break;
10932 case 1: code = BFD_RELOC_8; break;
10933 case 2: code = BFD_RELOC_16; break;
10934 case 4: code = BFD_RELOC_32; break;
937149dd 10935#ifdef BFD64
3e73aa7c 10936 case 8: code = BFD_RELOC_64; break;
937149dd 10937#endif
93382f6d 10938 }
252b5132
RH		 10939 }
10940 break;
10941 }
252b5132 10942
d182319b
JB		 10943 if ((code == BFD_RELOC_32
10944 || code == BFD_RELOC_32_PCREL
10945 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10946 && GOT_symbol
10947 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10948 {
4fa24527 10949 if (!object_64bit)
d6ab8113
JB		 10950 code = BFD_RELOC_386_GOTPC;
10951 else
10952 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10953 }
7b81dfbb
AJ		 10954 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10955 && GOT_symbol
10956 && fixp->fx_addsy == GOT_symbol)
10957 {
10958 code = BFD_RELOC_X86_64_GOTPC64;
10959 }
252b5132 10960
add39d23
TS		 10961 rel = XNEW (arelent);
10962 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10963 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10964
10965 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10966
3e73aa7c
JH		 10967 if (!use_rela_relocations)
10968 {
10969 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10970 vtable entry to be used in the relocation's section offset. */
10971 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10972 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10973#if defined (OBJ_COFF) && defined (TE_PE)
10974 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10975 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10976 else
10977#endif
c6682705 10978 rel->addend = 0;
3e73aa7c
JH		 10979 }
10980 /* Use the rela in 64bit mode. */
252b5132 10981 else
3e73aa7c 10982 {
862be3fb
L		 10983 if (disallow_64bit_reloc)
10984 switch (code)
10985 {
862be3fb
L		 10986 case BFD_RELOC_X86_64_DTPOFF64:
10987 case BFD_RELOC_X86_64_TPOFF64:
10988 case BFD_RELOC_64_PCREL:
10989 case BFD_RELOC_X86_64_GOTOFF64:
10990 case BFD_RELOC_X86_64_GOT64:
10991 case BFD_RELOC_X86_64_GOTPCREL64:
10992 case BFD_RELOC_X86_64_GOTPC64:
10993 case BFD_RELOC_X86_64_GOTPLT64:
10994 case BFD_RELOC_X86_64_PLTOFF64:
10995 as_bad_where (fixp->fx_file, fixp->fx_line,
10996 _("cannot represent relocation type %s in x32 mode"),
10997 bfd_get_reloc_code_name (code));
10998 break;
10999 default:
11000 break;
11001 }
11002
062cd5e7
AS		 11003 if (!fixp->fx_pcrel)
11004 rel->addend = fixp->fx_offset;
11005 else
11006 switch (code)
11007 {
11008 case BFD_RELOC_X86_64_PLT32:
11009 case BFD_RELOC_X86_64_GOT32:
11010 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11011 case BFD_RELOC_X86_64_GOTPCRELX:
11012 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11013 case BFD_RELOC_X86_64_TLSGD:
11014 case BFD_RELOC_X86_64_TLSLD:
11015 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11016 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11017 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11018 rel->addend = fixp->fx_offset - fixp->fx_size;
11019 break;
11020 default:
11021 rel->addend = (section->vma
11022 - fixp->fx_size
11023 + fixp->fx_addnumber
11024 + md_pcrel_from (fixp));
11025 break;
11026 }
3e73aa7c
JH		 11027 }
11028
252b5132
RH		 11029 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11030 if (rel->howto == NULL)
11031 {
11032 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11033 _("cannot represent relocation type %s"),
252b5132
RH		 11034 bfd_get_reloc_code_name (code));
11035 /* Set howto to a garbage value so that we can keep going. */
11036 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11037 gas_assert (rel->howto != NULL);
252b5132
RH		 11038 }
11039
11040 return rel;
11041}
11042
ee86248c 11043#include "tc-i386-intel.c"
54cfded0 11044
a60de03c
JB		 11045void
11046tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11047{
a60de03c
JB		 11048 int saved_naked_reg;
11049 char saved_register_dot;
54cfded0 11050
a60de03c
JB		 11051 saved_naked_reg = allow_naked_reg;
11052 allow_naked_reg = 1;
11053 saved_register_dot = register_chars['.'];
11054 register_chars['.'] = '.';
11055 allow_pseudo_reg = 1;
11056 expression_and_evaluate (exp);
11057 allow_pseudo_reg = 0;
11058 register_chars['.'] = saved_register_dot;
11059 allow_naked_reg = saved_naked_reg;
11060
e96d56a1 11061 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11062 {
a60de03c
JB		 11063 if ((addressT) exp->X_add_number < i386_regtab_size)
11064 {
11065 exp->X_op = O_constant;
11066 exp->X_add_number = i386_regtab[exp->X_add_number]
11067 .dw2_regnum[flag_code >> 1];
11068 }
11069 else
11070 exp->X_op = O_illegal;
54cfded0 11071 }
54cfded0
AM		 11072}
11073
11074void
11075tc_x86_frame_initial_instructions (void)
11076{
a60de03c
JB		 11077 static unsigned int sp_regno[2];
11078
11079 if (!sp_regno[flag_code >> 1])
11080 {
11081 char *saved_input = input_line_pointer;
11082 char sp[][4] = {"esp", "rsp"};
11083 expressionS exp;
a4447b93 11084
a60de03c
JB		 11085 input_line_pointer = sp[flag_code >> 1];
11086 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11087 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11088 sp_regno[flag_code >> 1] = exp.X_add_number;
11089 input_line_pointer = saved_input;
11090 }
a4447b93 11091
61ff971f
L		 11092 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11093 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11094}
d2b2c203 11095
d7921315
L		 11096int
11097x86_dwarf2_addr_size (void)
11098{
11099#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11100 if (x86_elf_abi == X86_64_X32_ABI)
11101 return 4;
11102#endif
11103 return bfd_arch_bits_per_address (stdoutput) / 8;
11104}
11105
d2b2c203
DJ		 11106int
11107i386_elf_section_type (const char *str, size_t len)
11108{
11109 if (flag_code == CODE_64BIT
11110 && len == sizeof ("unwind") - 1
11111 && strncmp (str, "unwind", 6) == 0)
11112 return SHT_X86_64_UNWIND;
11113
11114 return -1;
11115}
bb41ade5 11116
ad5fec3b
EB		 11117#ifdef TE_SOLARIS
11118void
11119i386_solaris_fix_up_eh_frame (segT sec)
11120{
11121 if (flag_code == CODE_64BIT)
11122 elf_section_type (sec) = SHT_X86_64_UNWIND;
11123}
11124#endif
11125
bb41ade5
AM		 11126#ifdef TE_PE
11127void
11128tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11129{
91d6fa6a 11130 expressionS exp;
bb41ade5 11131
91d6fa6a
NC		 11132 exp.X_op = O_secrel;
11133 exp.X_add_symbol = symbol;
11134 exp.X_add_number = 0;
11135 emit_expr (&exp, size);
bb41ade5
AM		 11136}
11137#endif
3b22753a
L		 11138
11139#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11140/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11141
01e1a5bc 11142bfd_vma
6d4af3c2 11143x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11144{
11145 if (flag_code == CODE_64BIT)
11146 {
11147 if (letter == 'l')
11148 return SHF_X86_64_LARGE;
11149
8f3bae45 11150 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11151 }
3b22753a 11152 else
8f3bae45 11153 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11154 return -1;
11155}
11156
01e1a5bc 11157bfd_vma
3b22753a
L		 11158x86_64_section_word (char *str, size_t len)
11159{
8620418b 11160 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11161 return SHF_X86_64_LARGE;
11162
11163 return -1;
11164}
11165
11166static void
11167handle_large_common (int small ATTRIBUTE_UNUSED)
11168{
11169 if (flag_code != CODE_64BIT)
11170 {
11171 s_comm_internal (0, elf_common_parse);
11172 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11173 }
11174 else
11175 {
11176 static segT lbss_section;
11177 asection *saved_com_section_ptr = elf_com_section_ptr;
11178 asection *saved_bss_section = bss_section;
11179
11180 if (lbss_section == NULL)
11181 {
11182 flagword applicable;
11183 segT seg = now_seg;
11184 subsegT subseg = now_subseg;
11185
11186 /* The .lbss section is for local .largecomm symbols. */
11187 lbss_section = subseg_new (".lbss", 0);
11188 applicable = bfd_applicable_section_flags (stdoutput);
11189 bfd_set_section_flags (stdoutput, lbss_section,
11190 applicable & SEC_ALLOC);
11191 seg_info (lbss_section)->bss = 1;
11192
11193 subseg_set (seg, subseg);
11194 }
11195
11196 elf_com_section_ptr = &_bfd_elf_large_com_section;
11197 bss_section = lbss_section;
11198
11199 s_comm_internal (0, elf_common_parse);
11200
11201 elf_com_section_ptr = saved_com_section_ptr;
11202 bss_section = saved_bss_section;
11203 }
11204}
11205#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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