projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Handle weak alias for PIE with copy reloc
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
d022bddd
IT		 546/* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548static int omit_lock_prefix = 0;
549
7bab8ab5 550static enum check_kind
daf50ae7 551 {
7bab8ab5
JB		 552 check_none = 0,
553 check_warning,
554 check_error
daf50ae7 555 }
7bab8ab5 556sse_check, operand_check = check_warning;
daf50ae7 557
2ca3ace5
L		 558/* Register prefix used for error message. */
559static const char *register_prefix = "%";
560
47926f60
KH		 561/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564static char stackop_size = '\0';
eecb386c 565
12b55ccc
L		 566/* Non-zero to optimize code alignment. */
567int optimize_align_code = 1;
568
47926f60
KH		 569/* Non-zero to quieten some warnings. */
570static int quiet_warnings = 0;
a38cf1db 571
47926f60
KH		 572/* CPU name. */
573static const char *cpu_arch_name = NULL;
6305a203 574static char *cpu_sub_arch_name = NULL;
a38cf1db 575
47926f60 576/* CPU feature flags. */
40fb9820
L		 577static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
578
ccc9c027
L		 579/* If we have selected a cpu we are generating instructions for. */
580static int cpu_arch_tune_set = 0;
581
9103f4f4 582/* Cpu we are generating instructions for. */
fbf3f584 583enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 584
585/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 586static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 587
ccc9c027 588/* CPU instruction set architecture used. */
fbf3f584 589enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 590
9103f4f4 591/* CPU feature flags of instruction set architecture used. */
fbf3f584 592i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 593
fddf5b5b
AM		 594/* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596static unsigned int no_cond_jump_promotion = 0;
597
c0f3af97
L		 598/* Encode SSE instructions with VEX prefix. */
599static unsigned int sse2avx;
600
539f890d
L		 601/* Encode scalar AVX instructions with specific vector length. */
602static enum
603 {
604 vex128 = 0,
605 vex256
606 } avxscalar;
607
43234a1e
L		 608/* Encode scalar EVEX LIG instructions with specific vector length. */
609static enum
610 {
611 evexl128 = 0,
612 evexl256,
613 evexl512
614 } evexlig;
615
616/* Encode EVEX WIG instructions with specific evex.w. */
617static enum
618 {
619 evexw0 = 0,
620 evexw1
621 } evexwig;
622
d3d3c6db
IT		 623/* Value to encode in EVEX RC bits, for SAE-only instructions. */
624static enum rc_type evexrcig = rne;
625
29b0f896 626/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 627static symbolS *GOT_symbol;
29b0f896 628
a4447b93
RH		 629/* The dwarf2 return column, adjusted for 32 or 64 bit. */
630unsigned int x86_dwarf2_return_column;
631
632/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633int x86_cie_data_alignment;
634
252b5132 635/* Interface to relax_segment.
fddf5b5b
AM		 636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
252b5132 639
47926f60 640/* Types. */
93c2a809
AM		 641#define UNCOND_JUMP 0
642#define COND_JUMP 1
643#define COND_JUMP86 2
fddf5b5b 644
47926f60 645/* Sizes. */
252b5132
RH		 646#define CODE16 1
647#define SMALL 0
29b0f896 648#define SMALL16 (SMALL | CODE16)
252b5132 649#define BIG 2
29b0f896 650#define BIG16 (BIG | CODE16)
252b5132
RH		 651
652#ifndef INLINE
653#ifdef __GNUC__
654#define INLINE __inline__
655#else
656#define INLINE
657#endif
658#endif
659
fddf5b5b
AM		 660#define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662#define TYPE_FROM_RELAX_STATE(s) \
663 ((s) >> 2)
664#define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 666
667/* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
674
675const relax_typeS md_relax_table[] =
676{
24eab124
AM		 677 /* The fields are:
678 1) most positive reach of this state,
679 2) most negative reach of this state,
93c2a809 680 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 681 4) which index into the table to try if we can't fit into this one. */
252b5132 682
fddf5b5b 683 /* UNCOND_JUMP states. */
93c2a809
AM		 684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
252b5132 688 {0, 0, 4, 0},
93c2a809
AM		 689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 691 {0, 0, 2, 0},
692
93c2a809
AM		 693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
698 {0, 0, 5, 0},
fddf5b5b 699 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 700 1 extra opcode byte, 2 displacement bytes. */
701 {0, 0, 3, 0},
702
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
708 {0, 0, 5, 0},
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
711 {0, 0, 4, 0}
252b5132
RH		 712};
713
9103f4f4
L		 714static const arch_entry cpu_arch[] =
715{
89507696
JB		 716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
8a2c8fef 718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 719 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 721 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 723 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 725 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 727 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 729 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 731 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 733 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 735 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 737 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 739 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 741 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 743 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 745 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 747 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 749 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 751 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 753 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 755 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 757 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 759 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 761 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
763 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 765 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 767 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 769 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 771 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 773 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 775 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 777 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 779 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 781 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
783 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
785 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
787 CPU_BTVER1_FLAGS, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
789 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 791 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 793 CPU_287_FLAGS, 0, 0 },
8a2c8fef 794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 795 CPU_387_FLAGS, 0, 0 },
8a2c8fef 796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 797 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 799 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 801 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 803 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 805 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 807 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 809 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 811 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 813 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 815 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 817 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 819 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
821 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
823 CPU_AVX512F_FLAGS, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
825 CPU_AVX512CD_FLAGS, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
827 CPU_AVX512ER_FLAGS, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
829 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
831 CPU_AVX512DQ_FLAGS, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
833 CPU_AVX512BW_FLAGS, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
835 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 837 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 839 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
841 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 843 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 845 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 847 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
849 CPU_XSAVEC_FLAGS, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
851 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 853 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 855 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 857 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 859 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 861 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 863 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
865 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 867 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 869 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 871 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 873 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 875 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
877 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 879 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
881 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
883 CPU_HLE_FLAGS, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
885 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
887 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 889 CPU_CLFLUSH_FLAGS, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
891 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 893 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 895 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 897 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 899 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 901 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 903 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 905 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 907 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 909 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
911 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
913 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
915 CPU_ADX_FLAGS, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
917 CPU_RDSEED_FLAGS, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
919 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
921 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
923 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
925 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
927 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
929 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
931 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
933 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
935 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
937 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 938 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
939 CPU_AVX512VBMI_FLAGS, 0, 0 },
e413e4e9
AM		 940};
941
704209c0 942#ifdef I386COFF
a6c24e68
NC		 943/* Like s_lcomm_internal in gas/read.c but the alignment string
944 is allowed to be optional. */
945
946static symbolS *
947pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
948{
949 addressT align = 0;
950
951 SKIP_WHITESPACE ();
952
7ab9ffdd 953 if (needs_align
a6c24e68
NC		 954 && *input_line_pointer == ',')
955 {
956 align = parse_align (needs_align - 1);
7ab9ffdd 957
a6c24e68
NC		 958 if (align == (addressT) -1)
959 return NULL;
960 }
961 else
962 {
963 if (size >= 8)
964 align = 3;
965 else if (size >= 4)
966 align = 2;
967 else if (size >= 2)
968 align = 1;
969 else
970 align = 0;
971 }
972
973 bss_alloc (symbolP, size, align);
974 return symbolP;
975}
976
704209c0 977static void
a6c24e68
NC		 978pe_lcomm (int needs_align)
979{
980 s_comm_internal (needs_align * 2, pe_lcomm_internal);
981}
704209c0 982#endif
a6c24e68 983
29b0f896
AM		 984const pseudo_typeS md_pseudo_table[] =
985{
986#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
987 {"align", s_align_bytes, 0},
988#else
989 {"align", s_align_ptwo, 0},
990#endif
991 {"arch", set_cpu_arch, 0},
992#ifndef I386COFF
993 {"bss", s_bss, 0},
a6c24e68
NC		 994#else
995 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 996#endif
997 {"ffloat", float_cons, 'f'},
998 {"dfloat", float_cons, 'd'},
999 {"tfloat", float_cons, 'x'},
1000 {"value", cons, 2},
d182319b 1001 {"slong", signed_cons, 4},
29b0f896
AM		 1002 {"noopt", s_ignore, 0},
1003 {"optim", s_ignore, 0},
1004 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1005 {"code16", set_code_flag, CODE_16BIT},
1006 {"code32", set_code_flag, CODE_32BIT},
1007 {"code64", set_code_flag, CODE_64BIT},
1008 {"intel_syntax", set_intel_syntax, 1},
1009 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1010 {"intel_mnemonic", set_intel_mnemonic, 1},
1011 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1012 {"allow_index_reg", set_allow_index_reg, 1},
1013 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1014 {"sse_check", set_check, 0},
1015 {"operand_check", set_check, 1},
3b22753a
L		 1016#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1017 {"largecomm", handle_large_common, 0},
07a53e5c 1018#else
e3bb37b5 1019 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1020 {"loc", dwarf2_directive_loc, 0},
1021 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1022#endif
6482c264
NC		 1023#ifdef TE_PE
1024 {"secrel32", pe_directive_secrel, 0},
1025#endif
29b0f896
AM		 1026 {0, 0, 0}
1027};
1028
1029/* For interface with expression (). */
1030extern char *input_line_pointer;
1031
1032/* Hash table for instruction mnemonic lookup. */
1033static struct hash_control *op_hash;
1034
1035/* Hash table for register lookup. */
1036static struct hash_control *reg_hash;
1037\f
252b5132 1038void
e3bb37b5 1039i386_align_code (fragS *fragP, int count)
252b5132 1040{
ce8a8b2f
AM		 1041 /* Various efficient no-op patterns for aligning code labels.
1042 Note: Don't try to assemble the instructions in the comments.
1043 0L and 0w are not legal. */
252b5132
RH		 1044 static const char f32_1[] =
1045 {0x90}; /* nop */
1046 static const char f32_2[] =
ccc9c027 1047 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1048 static const char f32_3[] =
1049 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1050 static const char f32_4[] =
1051 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1052 static const char f32_5[] =
1053 {0x90, /* nop */
1054 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1055 static const char f32_6[] =
1056 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1057 static const char f32_7[] =
1058 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1059 static const char f32_8[] =
1060 {0x90, /* nop */
1061 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1062 static const char f32_9[] =
1063 {0x89,0xf6, /* movl %esi,%esi */
1064 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1065 static const char f32_10[] =
1066 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1067 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1068 static const char f32_11[] =
1069 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1070 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1071 static const char f32_12[] =
1072 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1073 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1074 static const char f32_13[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_14[] =
1078 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1080 static const char f16_3[] =
1081 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1082 static const char f16_4[] =
1083 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1084 static const char f16_5[] =
1085 {0x90, /* nop */
1086 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1087 static const char f16_6[] =
1088 {0x89,0xf6, /* mov %si,%si */
1089 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1090 static const char f16_7[] =
1091 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1092 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1093 static const char f16_8[] =
1094 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1095 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1096 static const char jump_31[] =
1097 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1098 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1099 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1100 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1101 static const char *const f32_patt[] = {
1102 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1103 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1104 };
1105 static const char *const f16_patt[] = {
76bc74dc 1106 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1107 };
ccc9c027
L		 1108 /* nopl (%[re]ax) */
1109 static const char alt_3[] =
1110 {0x0f,0x1f,0x00};
1111 /* nopl 0(%[re]ax) */
1112 static const char alt_4[] =
1113 {0x0f,0x1f,0x40,0x00};
1114 /* nopl 0(%[re]ax,%[re]ax,1) */
1115 static const char alt_5[] =
1116 {0x0f,0x1f,0x44,0x00,0x00};
1117 /* nopw 0(%[re]ax,%[re]ax,1) */
1118 static const char alt_6[] =
1119 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1120 /* nopl 0L(%[re]ax) */
1121 static const char alt_7[] =
1122 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1123 /* nopl 0L(%[re]ax,%[re]ax,1) */
1124 static const char alt_8[] =
1125 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 /* nopw 0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_9[] =
1128 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1129 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_10[] =
1131 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1132 /* data16
1133 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1134 static const char alt_long_11[] =
1135 {0x66,
1136 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1137 /* data16
1138 data16
1139 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_long_12[] =
1141 {0x66,
1142 0x66,
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* data16
1145 data16
1146 data16
1147 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1148 static const char alt_long_13[] =
1149 {0x66,
1150 0x66,
1151 0x66,
1152 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1153 /* data16
1154 data16
1155 data16
1156 data16
1157 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1158 static const char alt_long_14[] =
1159 {0x66,
1160 0x66,
1161 0x66,
1162 0x66,
1163 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1164 /* data16
1165 data16
1166 data16
1167 data16
1168 data16
1169 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1170 static const char alt_long_15[] =
1171 {0x66,
1172 0x66,
1173 0x66,
1174 0x66,
1175 0x66,
1176 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1177 /* nopl 0(%[re]ax,%[re]ax,1)
1178 nopw 0(%[re]ax,%[re]ax,1) */
1179 static const char alt_short_11[] =
1180 {0x0f,0x1f,0x44,0x00,0x00,
1181 0x66,0x0f,0x1f,0x44,0x00,0x00};
1182 /* nopw 0(%[re]ax,%[re]ax,1)
1183 nopw 0(%[re]ax,%[re]ax,1) */
1184 static const char alt_short_12[] =
1185 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1186 0x66,0x0f,0x1f,0x44,0x00,0x00};
1187 /* nopw 0(%[re]ax,%[re]ax,1)
1188 nopl 0L(%[re]ax) */
1189 static const char alt_short_13[] =
1190 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1191 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1192 /* nopl 0L(%[re]ax)
1193 nopl 0L(%[re]ax) */
1194 static const char alt_short_14[] =
1195 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1196 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1197 /* nopl 0L(%[re]ax)
1198 nopl 0L(%[re]ax,%[re]ax,1) */
1199 static const char alt_short_15[] =
1200 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1201 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1202 static const char *const alt_short_patt[] = {
1203 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1204 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1205 alt_short_14, alt_short_15
1206 };
1207 static const char *const alt_long_patt[] = {
1208 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1209 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1210 alt_long_14, alt_long_15
1211 };
252b5132 1212
76bc74dc
L		 1213 /* Only align for at least a positive non-zero boundary. */
1214 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1215 return;
3e73aa7c 1216
ccc9c027
L		 1217 /* We need to decide which NOP sequence to use for 32bit and
1218 64bit. When -mtune= is used:
4eed87de 1219
76bc74dc
L		 1220 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1221 PROCESSOR_GENERIC32, f32_patt will be used.
1222 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1223 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1224 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1225 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1226 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1227 will be used.
ccc9c027 1228
76bc74dc 1229 When -mtune= isn't used, alt_long_patt will be used if
22109423 1230 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1231 be used.
ccc9c027
L		 1232
1233 When -march= or .arch is used, we can't use anything beyond
1234 cpu_arch_isa_flags. */
1235
1236 if (flag_code == CODE_16BIT)
1237 {
ccc9c027 1238 if (count > 8)
33fef721 1239 {
76bc74dc
L		 1240 memcpy (fragP->fr_literal + fragP->fr_fix,
1241 jump_31, count);
1242 /* Adjust jump offset. */
1243 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1244 }
76bc74dc
L		 1245 else
1246 memcpy (fragP->fr_literal + fragP->fr_fix,
1247 f16_patt[count - 1], count);
252b5132 1248 }
33fef721 1249 else
ccc9c027
L		 1250 {
1251 const char *const *patt = NULL;
1252
fbf3f584 1253 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1254 {
1255 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1256 switch (cpu_arch_tune)
1257 {
1258 case PROCESSOR_UNKNOWN:
1259 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1260 optimize with nops. */
1261 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1262 patt = alt_long_patt;
ccc9c027
L		 1263 else
1264 patt = f32_patt;
1265 break;
ccc9c027
L		 1266 case PROCESSOR_PENTIUM4:
1267 case PROCESSOR_NOCONA:
ef05d495 1268 case PROCESSOR_CORE:
76bc74dc 1269 case PROCESSOR_CORE2:
bd5295b2 1270 case PROCESSOR_COREI7:
3632d14b 1271 case PROCESSOR_L1OM:
7a9068fe 1272 case PROCESSOR_K1OM:
76bc74dc
L		 1273 case PROCESSOR_GENERIC64:
1274 patt = alt_long_patt;
1275 break;
ccc9c027
L		 1276 case PROCESSOR_K6:
1277 case PROCESSOR_ATHLON:
1278 case PROCESSOR_K8:
4eed87de 1279 case PROCESSOR_AMDFAM10:
8aedb9fe 1280 case PROCESSOR_BD:
7b458c12 1281 case PROCESSOR_BT:
ccc9c027
L		 1282 patt = alt_short_patt;
1283 break;
76bc74dc 1284 case PROCESSOR_I386:
ccc9c027
L		 1285 case PROCESSOR_I486:
1286 case PROCESSOR_PENTIUM:
2dde1948 1287 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1288 case PROCESSOR_GENERIC32:
1289 patt = f32_patt;
1290 break;
4eed87de 1291 }
ccc9c027
L		 1292 }
1293 else
1294 {
fbf3f584 1295 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1296 {
1297 case PROCESSOR_UNKNOWN:
e6a14101 1298 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1299 PROCESSOR_UNKNOWN. */
1300 abort ();
1301 break;
1302
76bc74dc 1303 case PROCESSOR_I386:
ccc9c027
L		 1304 case PROCESSOR_I486:
1305 case PROCESSOR_PENTIUM:
ccc9c027
L		 1306 case PROCESSOR_K6:
1307 case PROCESSOR_ATHLON:
1308 case PROCESSOR_K8:
4eed87de 1309 case PROCESSOR_AMDFAM10:
8aedb9fe 1310 case PROCESSOR_BD:
7b458c12 1311 case PROCESSOR_BT:
ccc9c027
L		 1312 case PROCESSOR_GENERIC32:
1313 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1314 with nops. */
1315 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1316 patt = alt_short_patt;
1317 else
1318 patt = f32_patt;
1319 break;
76bc74dc
L		 1320 case PROCESSOR_PENTIUMPRO:
1321 case PROCESSOR_PENTIUM4:
1322 case PROCESSOR_NOCONA:
1323 case PROCESSOR_CORE:
ef05d495 1324 case PROCESSOR_CORE2:
bd5295b2 1325 case PROCESSOR_COREI7:
3632d14b 1326 case PROCESSOR_L1OM:
7a9068fe 1327 case PROCESSOR_K1OM:
22109423 1328 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1329 patt = alt_long_patt;
1330 else
1331 patt = f32_patt;
1332 break;
1333 case PROCESSOR_GENERIC64:
76bc74dc 1334 patt = alt_long_patt;
ccc9c027 1335 break;
4eed87de 1336 }
ccc9c027
L		 1337 }
1338
76bc74dc
L		 1339 if (patt == f32_patt)
1340 {
1341 /* If the padding is less than 15 bytes, we use the normal
1342 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1343 its offset. */
1344 int limit;
76ba9986 1345
711eedef
L		 1346 /* For 64bit, the limit is 3 bytes. */
1347 if (flag_code == CODE_64BIT
1348 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1349 limit = 3;
1350 else
1351 limit = 15;
1352 if (count < limit)
76bc74dc
L		 1353 memcpy (fragP->fr_literal + fragP->fr_fix,
1354 patt[count - 1], count);
1355 else
1356 {
1357 memcpy (fragP->fr_literal + fragP->fr_fix,
1358 jump_31, count);
1359 /* Adjust jump offset. */
1360 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1361 }
1362 }
1363 else
1364 {
1365 /* Maximum length of an instruction is 15 byte. If the
1366 padding is greater than 15 bytes and we don't use jump,
1367 we have to break it into smaller pieces. */
1368 int padding = count;
1369 while (padding > 15)
1370 {
1371 padding -= 15;
1372 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1373 patt [14], 15);
1374 }
1375
1376 if (padding)
1377 memcpy (fragP->fr_literal + fragP->fr_fix,
1378 patt [padding - 1], padding);
1379 }
ccc9c027 1380 }
33fef721 1381 fragP->fr_var = count;
252b5132
RH		 1382}
1383
c6fb90c8 1384static INLINE int
0dfbf9d7 1385operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1386{
0dfbf9d7 1387 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1388 {
1389 case 3:
0dfbf9d7 1390 if (x->array[2])
c6fb90c8
L		 1391 return 0;
1392 case 2:
0dfbf9d7 1393 if (x->array[1])
c6fb90c8
L		 1394 return 0;
1395 case 1:
0dfbf9d7 1396 return !x->array[0];
c6fb90c8
L		 1397 default:
1398 abort ();
1399 }
40fb9820
L		 1400}
1401
c6fb90c8 1402static INLINE void
0dfbf9d7 1403operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1404{
0dfbf9d7 1405 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1406 {
1407 case 3:
0dfbf9d7 1408 x->array[2] = v;
c6fb90c8 1409 case 2:
0dfbf9d7 1410 x->array[1] = v;
c6fb90c8 1411 case 1:
0dfbf9d7 1412 x->array[0] = v;
c6fb90c8
L		 1413 break;
1414 default:
1415 abort ();
1416 }
1417}
40fb9820 1418
c6fb90c8 1419static INLINE int
0dfbf9d7
L		 1420operand_type_equal (const union i386_operand_type *x,
1421 const union i386_operand_type *y)
c6fb90c8 1422{
0dfbf9d7 1423 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1424 {
1425 case 3:
0dfbf9d7 1426 if (x->array[2] != y->array[2])
c6fb90c8
L		 1427 return 0;
1428 case 2:
0dfbf9d7 1429 if (x->array[1] != y->array[1])
c6fb90c8
L		 1430 return 0;
1431 case 1:
0dfbf9d7 1432 return x->array[0] == y->array[0];
c6fb90c8
L		 1433 break;
1434 default:
1435 abort ();
1436 }
1437}
40fb9820 1438
0dfbf9d7
L		 1439static INLINE int
1440cpu_flags_all_zero (const union i386_cpu_flags *x)
1441{
1442 switch (ARRAY_SIZE(x->array))
1443 {
1444 case 3:
1445 if (x->array[2])
1446 return 0;
1447 case 2:
1448 if (x->array[1])
1449 return 0;
1450 case 1:
1451 return !x->array[0];
1452 default:
1453 abort ();
1454 }
1455}
1456
1457static INLINE void
1458cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1459{
1460 switch (ARRAY_SIZE(x->array))
1461 {
1462 case 3:
1463 x->array[2] = v;
1464 case 2:
1465 x->array[1] = v;
1466 case 1:
1467 x->array[0] = v;
1468 break;
1469 default:
1470 abort ();
1471 }
1472}
1473
1474static INLINE int
1475cpu_flags_equal (const union i386_cpu_flags *x,
1476 const union i386_cpu_flags *y)
1477{
1478 switch (ARRAY_SIZE(x->array))
1479 {
1480 case 3:
1481 if (x->array[2] != y->array[2])
1482 return 0;
1483 case 2:
1484 if (x->array[1] != y->array[1])
1485 return 0;
1486 case 1:
1487 return x->array[0] == y->array[0];
1488 break;
1489 default:
1490 abort ();
1491 }
1492}
c6fb90c8
L		 1493
1494static INLINE int
1495cpu_flags_check_cpu64 (i386_cpu_flags f)
1496{
1497 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1498 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1499}
1500
c6fb90c8
L		 1501static INLINE i386_cpu_flags
1502cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1503{
c6fb90c8
L		 1504 switch (ARRAY_SIZE (x.array))
1505 {
1506 case 3:
1507 x.array [2] &= y.array [2];
1508 case 2:
1509 x.array [1] &= y.array [1];
1510 case 1:
1511 x.array [0] &= y.array [0];
1512 break;
1513 default:
1514 abort ();
1515 }
1516 return x;
1517}
40fb9820 1518
c6fb90c8
L		 1519static INLINE i386_cpu_flags
1520cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1521{
c6fb90c8 1522 switch (ARRAY_SIZE (x.array))
40fb9820 1523 {
c6fb90c8
L		 1524 case 3:
1525 x.array [2] |= y.array [2];
1526 case 2:
1527 x.array [1] |= y.array [1];
1528 case 1:
1529 x.array [0] |= y.array [0];
40fb9820
L		 1530 break;
1531 default:
1532 abort ();
1533 }
40fb9820
L		 1534 return x;
1535}
1536
309d3373
JB		 1537static INLINE i386_cpu_flags
1538cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1539{
1540 switch (ARRAY_SIZE (x.array))
1541 {
1542 case 3:
1543 x.array [2] &= ~y.array [2];
1544 case 2:
1545 x.array [1] &= ~y.array [1];
1546 case 1:
1547 x.array [0] &= ~y.array [0];
1548 break;
1549 default:
1550 abort ();
1551 }
1552 return x;
1553}
1554
c0f3af97
L		 1555#define CPU_FLAGS_ARCH_MATCH 0x1
1556#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1557#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1558#define CPU_FLAGS_PCLMUL_MATCH 0x8
1559#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1560
a5ff0eb2 1561#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1562 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1563 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1564#define CPU_FLAGS_PERFECT_MATCH \
1565 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1566
1567/* Return CPU flags match bits. */
3629bb00 1568
40fb9820 1569static int
d3ce72d0 1570cpu_flags_match (const insn_template *t)
40fb9820 1571{
c0f3af97
L		 1572 i386_cpu_flags x = t->cpu_flags;
1573 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1574
1575 x.bitfield.cpu64 = 0;
1576 x.bitfield.cpuno64 = 0;
1577
0dfbf9d7 1578 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1579 {
1580 /* This instruction is available on all archs. */
1581 match |= CPU_FLAGS_32BIT_MATCH;
1582 }
3629bb00
L		 1583 else
1584 {
c0f3af97 1585 /* This instruction is available only on some archs. */
3629bb00
L		 1586 i386_cpu_flags cpu = cpu_arch_flags;
1587
1588 cpu.bitfield.cpu64 = 0;
1589 cpu.bitfield.cpuno64 = 0;
1590 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1591 if (!cpu_flags_all_zero (&cpu))
1592 {
a5ff0eb2
L		 1593 if (x.bitfield.cpuavx)
1594 {
ce2f5b3c 1595 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1596 if (cpu.bitfield.cpuavx)
1597 {
1598 /* Check SSE2AVX. */
1599 if (!t->opcode_modifier.sse2avx|| sse2avx)
1600 {
1601 match |= (CPU_FLAGS_ARCH_MATCH
1602 | CPU_FLAGS_AVX_MATCH);
1603 /* Check AES. */
1604 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1605 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1606 /* Check PCLMUL. */
1607 if (!x.bitfield.cpupclmul
1608 || cpu.bitfield.cpupclmul)
1609 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1610 }
1611 }
1612 else
1613 match |= CPU_FLAGS_ARCH_MATCH;
1614 }
1615 else
c0f3af97
L		 1616 match |= CPU_FLAGS_32BIT_MATCH;
1617 }
3629bb00 1618 }
c0f3af97 1619 return match;
40fb9820
L		 1620}
1621
c6fb90c8
L		 1622static INLINE i386_operand_type
1623operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1624{
c6fb90c8
L		 1625 switch (ARRAY_SIZE (x.array))
1626 {
1627 case 3:
1628 x.array [2] &= y.array [2];
1629 case 2:
1630 x.array [1] &= y.array [1];
1631 case 1:
1632 x.array [0] &= y.array [0];
1633 break;
1634 default:
1635 abort ();
1636 }
1637 return x;
40fb9820
L		 1638}
1639
c6fb90c8
L		 1640static INLINE i386_operand_type
1641operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1642{
c6fb90c8 1643 switch (ARRAY_SIZE (x.array))
40fb9820 1644 {
c6fb90c8
L		 1645 case 3:
1646 x.array [2] |= y.array [2];
1647 case 2:
1648 x.array [1] |= y.array [1];
1649 case 1:
1650 x.array [0] |= y.array [0];
40fb9820
L		 1651 break;
1652 default:
1653 abort ();
1654 }
c6fb90c8
L		 1655 return x;
1656}
40fb9820 1657
c6fb90c8
L		 1658static INLINE i386_operand_type
1659operand_type_xor (i386_operand_type x, i386_operand_type y)
1660{
1661 switch (ARRAY_SIZE (x.array))
1662 {
1663 case 3:
1664 x.array [2] ^= y.array [2];
1665 case 2:
1666 x.array [1] ^= y.array [1];
1667 case 1:
1668 x.array [0] ^= y.array [0];
1669 break;
1670 default:
1671 abort ();
1672 }
40fb9820
L		 1673 return x;
1674}
1675
1676static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1677static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1678static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1679static const i386_operand_type inoutportreg
1680 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1681static const i386_operand_type reg16_inoutportreg
1682 = OPERAND_TYPE_REG16_INOUTPORTREG;
1683static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1684static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1685static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1686static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1687static const i386_operand_type anydisp
1688 = OPERAND_TYPE_ANYDISP;
40fb9820 1689static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1690static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1691static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1692static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1693static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1694static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1695static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1696static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1697static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1698static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1699static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1700static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1701static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1702static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1703
1704enum operand_type
1705{
1706 reg,
40fb9820
L		 1707 imm,
1708 disp,
1709 anymem
1710};
1711
c6fb90c8 1712static INLINE int
40fb9820
L		 1713operand_type_check (i386_operand_type t, enum operand_type c)
1714{
1715 switch (c)
1716 {
1717 case reg:
1718 return (t.bitfield.reg8
1719 || t.bitfield.reg16
1720 || t.bitfield.reg32
1721 || t.bitfield.reg64);
1722
40fb9820
L		 1723 case imm:
1724 return (t.bitfield.imm8
1725 || t.bitfield.imm8s
1726 || t.bitfield.imm16
1727 || t.bitfield.imm32
1728 || t.bitfield.imm32s
1729 || t.bitfield.imm64);
1730
1731 case disp:
1732 return (t.bitfield.disp8
1733 || t.bitfield.disp16
1734 || t.bitfield.disp32
1735 || t.bitfield.disp32s
1736 || t.bitfield.disp64);
1737
1738 case anymem:
1739 return (t.bitfield.disp8
1740 || t.bitfield.disp16
1741 || t.bitfield.disp32
1742 || t.bitfield.disp32s
1743 || t.bitfield.disp64
1744 || t.bitfield.baseindex);
1745
1746 default:
1747 abort ();
1748 }
2cfe26b6
AM		 1749
1750 return 0;
40fb9820
L		 1751}
1752
5c07affc
L		 1753/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1754 operand J for instruction template T. */
1755
1756static INLINE int
d3ce72d0 1757match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1758{
1759 return !((i.types[j].bitfield.byte
1760 && !t->operand_types[j].bitfield.byte)
1761 || (i.types[j].bitfield.word
1762 && !t->operand_types[j].bitfield.word)
1763 || (i.types[j].bitfield.dword
1764 && !t->operand_types[j].bitfield.dword)
1765 || (i.types[j].bitfield.qword
1766 && !t->operand_types[j].bitfield.qword));
1767}
1768
1769/* Return 1 if there is no conflict in any size on operand J for
1770 instruction template T. */
1771
1772static INLINE int
d3ce72d0 1773match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1774{
1775 return (match_reg_size (t, j)
1776 && !((i.types[j].bitfield.unspecified
1777 && !t->operand_types[j].bitfield.unspecified)
1778 || (i.types[j].bitfield.fword
1779 && !t->operand_types[j].bitfield.fword)
1780 || (i.types[j].bitfield.tbyte
1781 && !t->operand_types[j].bitfield.tbyte)
1782 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1783 && !t->operand_types[j].bitfield.xmmword)
1784 || (i.types[j].bitfield.ymmword
43234a1e
L		 1785 && !t->operand_types[j].bitfield.ymmword)
1786 || (i.types[j].bitfield.zmmword
1787 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1788}
1789
1790/* Return 1 if there is no size conflict on any operands for
1791 instruction template T. */
1792
1793static INLINE int
d3ce72d0 1794operand_size_match (const insn_template *t)
5c07affc
L		 1795{
1796 unsigned int j;
1797 int match = 1;
1798
1799 /* Don't check jump instructions. */
1800 if (t->opcode_modifier.jump
1801 || t->opcode_modifier.jumpbyte
1802 || t->opcode_modifier.jumpdword
1803 || t->opcode_modifier.jumpintersegment)
1804 return match;
1805
1806 /* Check memory and accumulator operand size. */
1807 for (j = 0; j < i.operands; j++)
1808 {
1809 if (t->operand_types[j].bitfield.anysize)
1810 continue;
1811
1812 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1813 {
1814 match = 0;
1815 break;
1816 }
1817
1818 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1819 {
1820 match = 0;
1821 break;
1822 }
1823 }
1824
891edac4 1825 if (match)
5c07affc 1826 return match;
891edac4
L		 1827 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1828 {
1829mismatch:
86e026a4 1830 i.error = operand_size_mismatch;
891edac4
L		 1831 return 0;
1832 }
5c07affc
L		 1833
1834 /* Check reverse. */
9c2799c2 1835 gas_assert (i.operands == 2);
5c07affc
L		 1836
1837 match = 1;
1838 for (j = 0; j < 2; j++)
1839 {
1840 if (t->operand_types[j].bitfield.acc
1841 && !match_reg_size (t, j ? 0 : 1))
891edac4 1842 goto mismatch;
5c07affc
L		 1843
1844 if (i.types[j].bitfield.mem
1845 && !match_mem_size (t, j ? 0 : 1))
891edac4 1846 goto mismatch;
5c07affc
L		 1847 }
1848
1849 return match;
1850}
1851
c6fb90c8 1852static INLINE int
40fb9820
L		 1853operand_type_match (i386_operand_type overlap,
1854 i386_operand_type given)
1855{
1856 i386_operand_type temp = overlap;
1857
1858 temp.bitfield.jumpabsolute = 0;
7d5e4556 1859 temp.bitfield.unspecified = 0;
5c07affc
L		 1860 temp.bitfield.byte = 0;
1861 temp.bitfield.word = 0;
1862 temp.bitfield.dword = 0;
1863 temp.bitfield.fword = 0;
1864 temp.bitfield.qword = 0;
1865 temp.bitfield.tbyte = 0;
1866 temp.bitfield.xmmword = 0;
c0f3af97 1867 temp.bitfield.ymmword = 0;
43234a1e 1868 temp.bitfield.zmmword = 0;
0dfbf9d7 1869 if (operand_type_all_zero (&temp))
891edac4 1870 goto mismatch;
40fb9820 1871
891edac4
L		 1872 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1873 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1874 return 1;
1875
1876mismatch:
a65babc9 1877 i.error = operand_type_mismatch;
891edac4 1878 return 0;
40fb9820
L		 1879}
1880
7d5e4556 1881/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1882 unless the expected operand type register overlap is null.
1883 Note that Acc in a template matches every size of reg. */
1884
c6fb90c8 1885static INLINE int
40fb9820
L		 1886operand_type_register_match (i386_operand_type m0,
1887 i386_operand_type g0,
1888 i386_operand_type t0,
1889 i386_operand_type m1,
1890 i386_operand_type g1,
1891 i386_operand_type t1)
1892{
1893 if (!operand_type_check (g0, reg))
1894 return 1;
1895
1896 if (!operand_type_check (g1, reg))
1897 return 1;
1898
1899 if (g0.bitfield.reg8 == g1.bitfield.reg8
1900 && g0.bitfield.reg16 == g1.bitfield.reg16
1901 && g0.bitfield.reg32 == g1.bitfield.reg32
1902 && g0.bitfield.reg64 == g1.bitfield.reg64)
1903 return 1;
1904
1905 if (m0.bitfield.acc)
1906 {
1907 t0.bitfield.reg8 = 1;
1908 t0.bitfield.reg16 = 1;
1909 t0.bitfield.reg32 = 1;
1910 t0.bitfield.reg64 = 1;
1911 }
1912
1913 if (m1.bitfield.acc)
1914 {
1915 t1.bitfield.reg8 = 1;
1916 t1.bitfield.reg16 = 1;
1917 t1.bitfield.reg32 = 1;
1918 t1.bitfield.reg64 = 1;
1919 }
1920
891edac4
L		 1921 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1922 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1923 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1924 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1925 return 1;
1926
a65babc9 1927 i.error = register_type_mismatch;
891edac4
L		 1928
1929 return 0;
40fb9820
L		 1930}
1931
4c692bc7
JB		 1932static INLINE unsigned int
1933register_number (const reg_entry *r)
1934{
1935 unsigned int nr = r->reg_num;
1936
1937 if (r->reg_flags & RegRex)
1938 nr += 8;
1939
1940 return nr;
1941}
1942
252b5132 1943static INLINE unsigned int
40fb9820 1944mode_from_disp_size (i386_operand_type t)
252b5132 1945{
43234a1e 1946 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1947 return 1;
1948 else if (t.bitfield.disp16
1949 || t.bitfield.disp32
1950 || t.bitfield.disp32s)
1951 return 2;
1952 else
1953 return 0;
252b5132
RH		 1954}
1955
1956static INLINE int
65879393 1957fits_in_signed_byte (addressT num)
252b5132 1958{
65879393 1959 return num + 0x80 <= 0xff;
47926f60 1960}
252b5132
RH		 1961
1962static INLINE int
65879393 1963fits_in_unsigned_byte (addressT num)
252b5132 1964{
65879393 1965 return num <= 0xff;
47926f60 1966}
252b5132
RH		 1967
1968static INLINE int
65879393 1969fits_in_unsigned_word (addressT num)
252b5132 1970{
65879393 1971 return num <= 0xffff;
47926f60 1972}
252b5132
RH		 1973
1974static INLINE int
65879393 1975fits_in_signed_word (addressT num)
252b5132 1976{
65879393 1977 return num + 0x8000 <= 0xffff;
47926f60 1978}
2a962e6d 1979
3e73aa7c 1980static INLINE int
65879393 1981fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1982{
1983#ifndef BFD64
1984 return 1;
1985#else
65879393 1986 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1987#endif
1988} /* fits_in_signed_long() */
2a962e6d 1989
3e73aa7c 1990static INLINE int
65879393 1991fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1992{
1993#ifndef BFD64
1994 return 1;
1995#else
65879393 1996 return num <= 0xffffffff;
3e73aa7c
JH		 1997#endif
1998} /* fits_in_unsigned_long() */
252b5132 1999
43234a1e
L		 2000static INLINE int
2001fits_in_vec_disp8 (offsetT num)
2002{
2003 int shift = i.memshift;
2004 unsigned int mask;
2005
2006 if (shift == -1)
2007 abort ();
2008
2009 mask = (1 << shift) - 1;
2010
2011 /* Return 0 if NUM isn't properly aligned. */
2012 if ((num & mask))
2013 return 0;
2014
2015 /* Check if NUM will fit in 8bit after shift. */
2016 return fits_in_signed_byte (num >> shift);
2017}
2018
a683cc34
SP		 2019static INLINE int
2020fits_in_imm4 (offsetT num)
2021{
2022 return (num & 0xf) == num;
2023}
2024
40fb9820 2025static i386_operand_type
e3bb37b5 2026smallest_imm_type (offsetT num)
252b5132 2027{
40fb9820 2028 i386_operand_type t;
7ab9ffdd 2029
0dfbf9d7 2030 operand_type_set (&t, 0);
40fb9820
L		 2031 t.bitfield.imm64 = 1;
2032
2033 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2034 {
2035 /* This code is disabled on the 486 because all the Imm1 forms
2036 in the opcode table are slower on the i486. They're the
2037 versions with the implicitly specified single-position
2038 displacement, which has another syntax if you really want to
2039 use that form. */
40fb9820
L		 2040 t.bitfield.imm1 = 1;
2041 t.bitfield.imm8 = 1;
2042 t.bitfield.imm8s = 1;
2043 t.bitfield.imm16 = 1;
2044 t.bitfield.imm32 = 1;
2045 t.bitfield.imm32s = 1;
2046 }
2047 else if (fits_in_signed_byte (num))
2048 {
2049 t.bitfield.imm8 = 1;
2050 t.bitfield.imm8s = 1;
2051 t.bitfield.imm16 = 1;
2052 t.bitfield.imm32 = 1;
2053 t.bitfield.imm32s = 1;
2054 }
2055 else if (fits_in_unsigned_byte (num))
2056 {
2057 t.bitfield.imm8 = 1;
2058 t.bitfield.imm16 = 1;
2059 t.bitfield.imm32 = 1;
2060 t.bitfield.imm32s = 1;
2061 }
2062 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2063 {
2064 t.bitfield.imm16 = 1;
2065 t.bitfield.imm32 = 1;
2066 t.bitfield.imm32s = 1;
2067 }
2068 else if (fits_in_signed_long (num))
2069 {
2070 t.bitfield.imm32 = 1;
2071 t.bitfield.imm32s = 1;
2072 }
2073 else if (fits_in_unsigned_long (num))
2074 t.bitfield.imm32 = 1;
2075
2076 return t;
47926f60 2077}
252b5132 2078
847f7ad4 2079static offsetT
e3bb37b5 2080offset_in_range (offsetT val, int size)
847f7ad4 2081{
508866be 2082 addressT mask;
ba2adb93 2083
847f7ad4
AM		 2084 switch (size)
2085 {
508866be
L		 2086 case 1: mask = ((addressT) 1 << 8) - 1; break;
2087 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2088 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2089#ifdef BFD64
2090 case 8: mask = ((addressT) 2 << 63) - 1; break;
2091#endif
47926f60 2092 default: abort ();
847f7ad4
AM		 2093 }
2094
9de868bf
L		 2095#ifdef BFD64
2096 /* If BFD64, sign extend val for 32bit address mode. */
2097 if (flag_code != CODE_64BIT
2098 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2099 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2100 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2101#endif
ba2adb93 2102
47926f60 2103 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2104 {
2105 char buf1[40], buf2[40];
2106
2107 sprint_value (buf1, val);
2108 sprint_value (buf2, val & mask);
2109 as_warn (_("%s shortened to %s"), buf1, buf2);
2110 }
2111 return val & mask;
2112}
2113
c32fa91d
L		 2114enum PREFIX_GROUP
2115{
2116 PREFIX_EXIST = 0,
2117 PREFIX_LOCK,
2118 PREFIX_REP,
2119 PREFIX_OTHER
2120};
2121
2122/* Returns
2123 a. PREFIX_EXIST if attempting to add a prefix where one from the
2124 same class already exists.
2125 b. PREFIX_LOCK if lock prefix is added.
2126 c. PREFIX_REP if rep/repne prefix is added.
2127 d. PREFIX_OTHER if other prefix is added.
2128 */
2129
2130static enum PREFIX_GROUP
e3bb37b5 2131add_prefix (unsigned int prefix)
252b5132 2132{
c32fa91d 2133 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2134 unsigned int q;
252b5132 2135
29b0f896
AM		 2136 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2137 && flag_code == CODE_64BIT)
b1905489 2138 {
161a04f6
L		 2139 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2140 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2141 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2142 ret = PREFIX_EXIST;
b1905489
JB		 2143 q = REX_PREFIX;
2144 }
3e73aa7c 2145 else
b1905489
JB		 2146 {
2147 switch (prefix)
2148 {
2149 default:
2150 abort ();
2151
2152 case CS_PREFIX_OPCODE:
2153 case DS_PREFIX_OPCODE:
2154 case ES_PREFIX_OPCODE:
2155 case FS_PREFIX_OPCODE:
2156 case GS_PREFIX_OPCODE:
2157 case SS_PREFIX_OPCODE:
2158 q = SEG_PREFIX;
2159 break;
2160
2161 case REPNE_PREFIX_OPCODE:
2162 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2163 q = REP_PREFIX;
2164 ret = PREFIX_REP;
2165 break;
2166
b1905489 2167 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2168 q = LOCK_PREFIX;
2169 ret = PREFIX_LOCK;
b1905489
JB		 2170 break;
2171
2172 case FWAIT_OPCODE:
2173 q = WAIT_PREFIX;
2174 break;
2175
2176 case ADDR_PREFIX_OPCODE:
2177 q = ADDR_PREFIX;
2178 break;
2179
2180 case DATA_PREFIX_OPCODE:
2181 q = DATA_PREFIX;
2182 break;
2183 }
2184 if (i.prefix[q] != 0)
c32fa91d 2185 ret = PREFIX_EXIST;
b1905489 2186 }
252b5132 2187
b1905489 2188 if (ret)
252b5132 2189 {
b1905489
JB		 2190 if (!i.prefix[q])
2191 ++i.prefixes;
2192 i.prefix[q] |= prefix;
252b5132 2193 }
b1905489
JB		 2194 else
2195 as_bad (_("same type of prefix used twice"));
252b5132 2196
252b5132
RH		 2197 return ret;
2198}
2199
2200static void
78f12dd3 2201update_code_flag (int value, int check)
eecb386c 2202{
78f12dd3
L		 2203 PRINTF_LIKE ((*as_error));
2204
1e9cc1c2 2205 flag_code = (enum flag_code) value;
40fb9820
L		 2206 if (flag_code == CODE_64BIT)
2207 {
2208 cpu_arch_flags.bitfield.cpu64 = 1;
2209 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2210 }
2211 else
2212 {
2213 cpu_arch_flags.bitfield.cpu64 = 0;
2214 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2215 }
2216 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2217 {
78f12dd3
L		 2218 if (check)
2219 as_error = as_fatal;
2220 else
2221 as_error = as_bad;
2222 (*as_error) (_("64bit mode not supported on `%s'."),
2223 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2224 }
40fb9820 2225 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2226 {
78f12dd3
L		 2227 if (check)
2228 as_error = as_fatal;
2229 else
2230 as_error = as_bad;
2231 (*as_error) (_("32bit mode not supported on `%s'."),
2232 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2233 }
eecb386c
AM		 2234 stackop_size = '\0';
2235}
2236
78f12dd3
L		 2237static void
2238set_code_flag (int value)
2239{
2240 update_code_flag (value, 0);
2241}
2242
eecb386c 2243static void
e3bb37b5 2244set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2245{
1e9cc1c2 2246 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2247 if (flag_code != CODE_16BIT)
2248 abort ();
2249 cpu_arch_flags.bitfield.cpu64 = 0;
2250 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2251 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2252}
2253
2254static void
e3bb37b5 2255set_intel_syntax (int syntax_flag)
252b5132
RH		 2256{
2257 /* Find out if register prefixing is specified. */
2258 int ask_naked_reg = 0;
2259
2260 SKIP_WHITESPACE ();
29b0f896 2261 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2262 {
2263 char *string = input_line_pointer;
2264 int e = get_symbol_end ();
2265
47926f60 2266 if (strcmp (string, "prefix") == 0)
252b5132 2267 ask_naked_reg = 1;
47926f60 2268 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2269 ask_naked_reg = -1;
2270 else
d0b47220 2271 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2272 *input_line_pointer = e;
2273 }
2274 demand_empty_rest_of_line ();
c3332e24 2275
252b5132
RH		 2276 intel_syntax = syntax_flag;
2277
2278 if (ask_naked_reg == 0)
f86103b7
AM		 2279 allow_naked_reg = (intel_syntax
2280 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2281 else
2282 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2283
ee86248c 2284 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2285
e4a3b5a4 2286 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2287 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2288 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2289}
2290
1efbbeb4
L		 2291static void
2292set_intel_mnemonic (int mnemonic_flag)
2293{
e1d4d893 2294 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2295}
2296
db51cc60
L		 2297static void
2298set_allow_index_reg (int flag)
2299{
2300 allow_index_reg = flag;
2301}
2302
cb19c032 2303static void
7bab8ab5 2304set_check (int what)
cb19c032 2305{
7bab8ab5
JB		 2306 enum check_kind *kind;
2307 const char *str;
2308
2309 if (what)
2310 {
2311 kind = &operand_check;
2312 str = "operand";
2313 }
2314 else
2315 {
2316 kind = &sse_check;
2317 str = "sse";
2318 }
2319
cb19c032
L		 2320 SKIP_WHITESPACE ();
2321
2322 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2323 {
2324 char *string = input_line_pointer;
2325 int e = get_symbol_end ();
2326
2327 if (strcmp (string, "none") == 0)
7bab8ab5 2328 *kind = check_none;
cb19c032 2329 else if (strcmp (string, "warning") == 0)
7bab8ab5 2330 *kind = check_warning;
cb19c032 2331 else if (strcmp (string, "error") == 0)
7bab8ab5 2332 *kind = check_error;
cb19c032 2333 else
7bab8ab5 2334 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2335 *input_line_pointer = e;
2336 }
2337 else
7bab8ab5 2338 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2339
2340 demand_empty_rest_of_line ();
2341}
2342
8a9036a4
L		 2343static void
2344check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2345 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2346{
2347#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2348 static const char *arch;
2349
2350 /* Intel LIOM is only supported on ELF. */
2351 if (!IS_ELF)
2352 return;
2353
2354 if (!arch)
2355 {
2356 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2357 use default_arch. */
2358 arch = cpu_arch_name;
2359 if (!arch)
2360 arch = default_arch;
2361 }
2362
3632d14b 2363 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2364 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2365 || new_flag.bitfield.cpul1om)
8a9036a4 2366 return;
76ba9986 2367
7a9068fe
L		 2368 /* If we are targeting Intel K1OM, we must enable it. */
2369 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2370 || new_flag.bitfield.cpuk1om)
2371 return;
2372
8a9036a4
L		 2373 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2374#endif
2375}
2376
e413e4e9 2377static void
e3bb37b5 2378set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2379{
47926f60 2380 SKIP_WHITESPACE ();
e413e4e9 2381
29b0f896 2382 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2383 {
2384 char *string = input_line_pointer;
2385 int e = get_symbol_end ();
91d6fa6a 2386 unsigned int j;
40fb9820 2387 i386_cpu_flags flags;
e413e4e9 2388
91d6fa6a 2389 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2390 {
91d6fa6a 2391 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2392 {
91d6fa6a 2393 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2394
5c6af06e
JB		 2395 if (*string != '.')
2396 {
91d6fa6a 2397 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2398 cpu_sub_arch_name = NULL;
91d6fa6a 2399 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2400 if (flag_code == CODE_64BIT)
2401 {
2402 cpu_arch_flags.bitfield.cpu64 = 1;
2403 cpu_arch_flags.bitfield.cpuno64 = 0;
2404 }
2405 else
2406 {
2407 cpu_arch_flags.bitfield.cpu64 = 0;
2408 cpu_arch_flags.bitfield.cpuno64 = 1;
2409 }
91d6fa6a
NC		 2410 cpu_arch_isa = cpu_arch[j].type;
2411 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2412 if (!cpu_arch_tune_set)
2413 {
2414 cpu_arch_tune = cpu_arch_isa;
2415 cpu_arch_tune_flags = cpu_arch_isa_flags;
2416 }
5c6af06e
JB		 2417 break;
2418 }
40fb9820 2419
22109423 2420 if (!cpu_arch[j].negated)
309d3373 2421 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2422 cpu_arch[j].flags);
309d3373
JB		 2423 else
2424 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2425 cpu_arch[j].flags);
0dfbf9d7 2426 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2427 {
6305a203
L		 2428 if (cpu_sub_arch_name)
2429 {
2430 char *name = cpu_sub_arch_name;
2431 cpu_sub_arch_name = concat (name,
91d6fa6a 2432 cpu_arch[j].name,
1bf57e9f 2433 (const char *) NULL);
6305a203
L		 2434 free (name);
2435 }
2436 else
91d6fa6a 2437 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2438 cpu_arch_flags = flags;
a586129e 2439 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2440 }
2441 *input_line_pointer = e;
2442 demand_empty_rest_of_line ();
2443 return;
e413e4e9
AM		 2444 }
2445 }
91d6fa6a 2446 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2447 as_bad (_("no such architecture: `%s'"), string);
2448
2449 *input_line_pointer = e;
2450 }
2451 else
2452 as_bad (_("missing cpu architecture"));
2453
fddf5b5b
AM		 2454 no_cond_jump_promotion = 0;
2455 if (*input_line_pointer == ','
29b0f896 2456 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2457 {
2458 char *string = ++input_line_pointer;
2459 int e = get_symbol_end ();
2460
2461 if (strcmp (string, "nojumps") == 0)
2462 no_cond_jump_promotion = 1;
2463 else if (strcmp (string, "jumps") == 0)
2464 ;
2465 else
2466 as_bad (_("no such architecture modifier: `%s'"), string);
2467
2468 *input_line_pointer = e;
2469 }
2470
e413e4e9
AM		 2471 demand_empty_rest_of_line ();
2472}
2473
8a9036a4
L		 2474enum bfd_architecture
2475i386_arch (void)
2476{
3632d14b 2477 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2478 {
2479 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2480 || flag_code != CODE_64BIT)
2481 as_fatal (_("Intel L1OM is 64bit ELF only"));
2482 return bfd_arch_l1om;
2483 }
7a9068fe
L		 2484 else if (cpu_arch_isa == PROCESSOR_K1OM)
2485 {
2486 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2487 || flag_code != CODE_64BIT)
2488 as_fatal (_("Intel K1OM is 64bit ELF only"));
2489 return bfd_arch_k1om;
2490 }
8a9036a4
L		 2491 else
2492 return bfd_arch_i386;
2493}
2494
b9d79e03 2495unsigned long
7016a5d5 2496i386_mach (void)
b9d79e03 2497{
351f65ca 2498 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2499 {
3632d14b 2500 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2501 {
351f65ca
L		 2502 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2503 || default_arch[6] != '\0')
8a9036a4
L		 2504 as_fatal (_("Intel L1OM is 64bit ELF only"));
2505 return bfd_mach_l1om;
2506 }
7a9068fe
L		 2507 else if (cpu_arch_isa == PROCESSOR_K1OM)
2508 {
2509 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2510 || default_arch[6] != '\0')
2511 as_fatal (_("Intel K1OM is 64bit ELF only"));
2512 return bfd_mach_k1om;
2513 }
351f65ca 2514 else if (default_arch[6] == '\0')
8a9036a4 2515 return bfd_mach_x86_64;
351f65ca
L		 2516 else
2517 return bfd_mach_x64_32;
8a9036a4 2518 }
b9d79e03
JH		 2519 else if (!strcmp (default_arch, "i386"))
2520 return bfd_mach_i386_i386;
2521 else
2b5d6a91 2522 as_fatal (_("unknown architecture"));
b9d79e03 2523}
b9d79e03 2524\f
252b5132 2525void
7016a5d5 2526md_begin (void)
252b5132
RH		 2527{
2528 const char *hash_err;
2529
47926f60 2530 /* Initialize op_hash hash table. */
252b5132
RH		 2531 op_hash = hash_new ();
2532
2533 {
d3ce72d0 2534 const insn_template *optab;
29b0f896 2535 templates *core_optab;
252b5132 2536
47926f60
KH		 2537 /* Setup for loop. */
2538 optab = i386_optab;
252b5132
RH		 2539 core_optab = (templates *) xmalloc (sizeof (templates));
2540 core_optab->start = optab;
2541
2542 while (1)
2543 {
2544 ++optab;
2545 if (optab->name == NULL
2546 || strcmp (optab->name, (optab - 1)->name) != 0)
2547 {
2548 /* different name --> ship out current template list;
47926f60 2549 add to hash table; & begin anew. */
252b5132
RH		 2550 core_optab->end = optab;
2551 hash_err = hash_insert (op_hash,
2552 (optab - 1)->name,
5a49b8ac 2553 (void *) core_optab);
252b5132
RH		 2554 if (hash_err)
2555 {
b37df7c4 2556 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2557 (optab - 1)->name,
2558 hash_err);
2559 }
2560 if (optab->name == NULL)
2561 break;
2562 core_optab = (templates *) xmalloc (sizeof (templates));
2563 core_optab->start = optab;
2564 }
2565 }
2566 }
2567
47926f60 2568 /* Initialize reg_hash hash table. */
252b5132
RH		 2569 reg_hash = hash_new ();
2570 {
29b0f896 2571 const reg_entry *regtab;
c3fe08fa 2572 unsigned int regtab_size = i386_regtab_size;
252b5132 2573
c3fe08fa 2574 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2575 {
5a49b8ac 2576 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2577 if (hash_err)
b37df7c4 2578 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2579 regtab->reg_name,
2580 hash_err);
252b5132
RH		 2581 }
2582 }
2583
47926f60 2584 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2585 {
29b0f896
AM		 2586 int c;
2587 char *p;
252b5132
RH		 2588
2589 for (c = 0; c < 256; c++)
2590 {
3882b010 2591 if (ISDIGIT (c))
252b5132
RH		 2592 {
2593 digit_chars[c] = c;
2594 mnemonic_chars[c] = c;
2595 register_chars[c] = c;
2596 operand_chars[c] = c;
2597 }
3882b010 2598 else if (ISLOWER (c))
252b5132
RH		 2599 {
2600 mnemonic_chars[c] = c;
2601 register_chars[c] = c;
2602 operand_chars[c] = c;
2603 }
3882b010 2604 else if (ISUPPER (c))
252b5132 2605 {
3882b010 2606 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2607 register_chars[c] = mnemonic_chars[c];
2608 operand_chars[c] = c;
2609 }
43234a1e
L		 2610 else if (c == '{' || c == '}')
2611 operand_chars[c] = c;
252b5132 2612
3882b010 2613 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2614 identifier_chars[c] = c;
2615 else if (c >= 128)
2616 {
2617 identifier_chars[c] = c;
2618 operand_chars[c] = c;
2619 }
2620 }
2621
2622#ifdef LEX_AT
2623 identifier_chars['@'] = '@';
32137342
NC		 2624#endif
2625#ifdef LEX_QM
2626 identifier_chars['?'] = '?';
2627 operand_chars['?'] = '?';
252b5132 2628#endif
252b5132 2629 digit_chars['-'] = '-';
c0f3af97 2630 mnemonic_chars['_'] = '_';
791fe849 2631 mnemonic_chars['-'] = '-';
0003779b 2632 mnemonic_chars['.'] = '.';
252b5132
RH		 2633 identifier_chars['_'] = '_';
2634 identifier_chars['.'] = '.';
2635
2636 for (p = operand_special_chars; *p != '\0'; p++)
2637 operand_chars[(unsigned char) *p] = *p;
2638 }
2639
a4447b93
RH		 2640 if (flag_code == CODE_64BIT)
2641 {
ca19b261
KT		 2642#if defined (OBJ_COFF) && defined (TE_PE)
2643 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2644 ? 32 : 16);
2645#else
a4447b93 2646 x86_dwarf2_return_column = 16;
ca19b261 2647#endif
61ff971f 2648 x86_cie_data_alignment = -8;
a4447b93
RH		 2649 }
2650 else
2651 {
2652 x86_dwarf2_return_column = 8;
2653 x86_cie_data_alignment = -4;
2654 }
252b5132
RH		 2655}
2656
2657void
e3bb37b5 2658i386_print_statistics (FILE *file)
252b5132
RH		 2659{
2660 hash_print_statistics (file, "i386 opcode", op_hash);
2661 hash_print_statistics (file, "i386 register", reg_hash);
2662}
2663\f
252b5132
RH		 2664#ifdef DEBUG386
2665
ce8a8b2f 2666/* Debugging routines for md_assemble. */
d3ce72d0 2667static void pte (insn_template *);
40fb9820 2668static void pt (i386_operand_type);
e3bb37b5
L		 2669static void pe (expressionS *);
2670static void ps (symbolS *);
252b5132
RH		 2671
2672static void
e3bb37b5 2673pi (char *line, i386_insn *x)
252b5132 2674{
09137c09 2675 unsigned int j;
252b5132
RH		 2676
2677 fprintf (stdout, "%s: template ", line);
2678 pte (&x->tm);
09f131f2
JH		 2679 fprintf (stdout, " address: base %s index %s scale %x\n",
2680 x->base_reg ? x->base_reg->reg_name : "none",
2681 x->index_reg ? x->index_reg->reg_name : "none",
2682 x->log2_scale_factor);
2683 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2684 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2685 fprintf (stdout, " sib: base %x index %x scale %x\n",
2686 x->sib.base, x->sib.index, x->sib.scale);
2687 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2688 (x->rex & REX_W) != 0,
2689 (x->rex & REX_R) != 0,
2690 (x->rex & REX_X) != 0,
2691 (x->rex & REX_B) != 0);
09137c09 2692 for (j = 0; j < x->operands; j++)
252b5132 2693 {
09137c09
SP		 2694 fprintf (stdout, " #%d: ", j + 1);
2695 pt (x->types[j]);
252b5132 2696 fprintf (stdout, "\n");
09137c09
SP		 2697 if (x->types[j].bitfield.reg8
2698 || x->types[j].bitfield.reg16
2699 || x->types[j].bitfield.reg32
2700 || x->types[j].bitfield.reg64
2701 || x->types[j].bitfield.regmmx
2702 || x->types[j].bitfield.regxmm
2703 || x->types[j].bitfield.regymm
43234a1e 2704 || x->types[j].bitfield.regzmm
09137c09
SP		 2705 || x->types[j].bitfield.sreg2
2706 || x->types[j].bitfield.sreg3
2707 || x->types[j].bitfield.control
2708 || x->types[j].bitfield.debug
2709 || x->types[j].bitfield.test)
2710 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2711 if (operand_type_check (x->types[j], imm))
2712 pe (x->op[j].imms);
2713 if (operand_type_check (x->types[j], disp))
2714 pe (x->op[j].disps);
252b5132
RH		 2715 }
2716}
2717
2718static void
d3ce72d0 2719pte (insn_template *t)
252b5132 2720{
09137c09 2721 unsigned int j;
252b5132 2722 fprintf (stdout, " %d operands ", t->operands);
47926f60 2723 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2724 if (t->extension_opcode != None)
2725 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2726 if (t->opcode_modifier.d)
252b5132 2727 fprintf (stdout, "D");
40fb9820 2728 if (t->opcode_modifier.w)
252b5132
RH		 2729 fprintf (stdout, "W");
2730 fprintf (stdout, "\n");
09137c09 2731 for (j = 0; j < t->operands; j++)
252b5132 2732 {
09137c09
SP		 2733 fprintf (stdout, " #%d type ", j + 1);
2734 pt (t->operand_types[j]);
252b5132
RH		 2735 fprintf (stdout, "\n");
2736 }
2737}
2738
2739static void
e3bb37b5 2740pe (expressionS *e)
252b5132 2741{
24eab124 2742 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2743 fprintf (stdout, " add_number %ld (%lx)\n",
2744 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2745 if (e->X_add_symbol)
2746 {
2747 fprintf (stdout, " add_symbol ");
2748 ps (e->X_add_symbol);
2749 fprintf (stdout, "\n");
2750 }
2751 if (e->X_op_symbol)
2752 {
2753 fprintf (stdout, " op_symbol ");
2754 ps (e->X_op_symbol);
2755 fprintf (stdout, "\n");
2756 }
2757}
2758
2759static void
e3bb37b5 2760ps (symbolS *s)
252b5132
RH		 2761{
2762 fprintf (stdout, "%s type %s%s",
2763 S_GET_NAME (s),
2764 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2765 segment_name (S_GET_SEGMENT (s)));
2766}
2767
7b81dfbb 2768static struct type_name
252b5132 2769 {
40fb9820
L		 2770 i386_operand_type mask;
2771 const char *name;
252b5132 2772 }
7b81dfbb 2773const type_names[] =
252b5132 2774{
40fb9820
L		 2775 { OPERAND_TYPE_REG8, "r8" },
2776 { OPERAND_TYPE_REG16, "r16" },
2777 { OPERAND_TYPE_REG32, "r32" },
2778 { OPERAND_TYPE_REG64, "r64" },
2779 { OPERAND_TYPE_IMM8, "i8" },
2780 { OPERAND_TYPE_IMM8, "i8s" },
2781 { OPERAND_TYPE_IMM16, "i16" },
2782 { OPERAND_TYPE_IMM32, "i32" },
2783 { OPERAND_TYPE_IMM32S, "i32s" },
2784 { OPERAND_TYPE_IMM64, "i64" },
2785 { OPERAND_TYPE_IMM1, "i1" },
2786 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2787 { OPERAND_TYPE_DISP8, "d8" },
2788 { OPERAND_TYPE_DISP16, "d16" },
2789 { OPERAND_TYPE_DISP32, "d32" },
2790 { OPERAND_TYPE_DISP32S, "d32s" },
2791 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2792 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2793 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2794 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2795 { OPERAND_TYPE_CONTROL, "control reg" },
2796 { OPERAND_TYPE_TEST, "test reg" },
2797 { OPERAND_TYPE_DEBUG, "debug reg" },
2798 { OPERAND_TYPE_FLOATREG, "FReg" },
2799 { OPERAND_TYPE_FLOATACC, "FAcc" },
2800 { OPERAND_TYPE_SREG2, "SReg2" },
2801 { OPERAND_TYPE_SREG3, "SReg3" },
2802 { OPERAND_TYPE_ACC, "Acc" },
2803 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2804 { OPERAND_TYPE_REGMMX, "rMMX" },
2805 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2806 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2807 { OPERAND_TYPE_REGZMM, "rZMM" },
2808 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2809 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2810};
2811
2812static void
40fb9820 2813pt (i386_operand_type t)
252b5132 2814{
40fb9820 2815 unsigned int j;
c6fb90c8 2816 i386_operand_type a;
252b5132 2817
40fb9820 2818 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2819 {
2820 a = operand_type_and (t, type_names[j].mask);
0349dc08 2821 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2822 fprintf (stdout, "%s, ", type_names[j].name);
2823 }
252b5132
RH		 2824 fflush (stdout);
2825}
2826
2827#endif /* DEBUG386 */
2828\f
252b5132 2829static bfd_reloc_code_real_type
3956db08 2830reloc (unsigned int size,
64e74474
AM		 2831 int pcrel,
2832 int sign,
2833 bfd_reloc_code_real_type other)
252b5132 2834{
47926f60 2835 if (other != NO_RELOC)
3956db08 2836 {
91d6fa6a 2837 reloc_howto_type *rel;
3956db08
JB		 2838
2839 if (size == 8)
2840 switch (other)
2841 {
64e74474
AM		 2842 case BFD_RELOC_X86_64_GOT32:
2843 return BFD_RELOC_X86_64_GOT64;
2844 break;
553d1284
L		 2845 case BFD_RELOC_X86_64_GOTPLT64:
2846 return BFD_RELOC_X86_64_GOTPLT64;
2847 break;
64e74474
AM		 2848 case BFD_RELOC_X86_64_PLTOFF64:
2849 return BFD_RELOC_X86_64_PLTOFF64;
2850 break;
2851 case BFD_RELOC_X86_64_GOTPC32:
2852 other = BFD_RELOC_X86_64_GOTPC64;
2853 break;
2854 case BFD_RELOC_X86_64_GOTPCREL:
2855 other = BFD_RELOC_X86_64_GOTPCREL64;
2856 break;
2857 case BFD_RELOC_X86_64_TPOFF32:
2858 other = BFD_RELOC_X86_64_TPOFF64;
2859 break;
2860 case BFD_RELOC_X86_64_DTPOFF32:
2861 other = BFD_RELOC_X86_64_DTPOFF64;
2862 break;
2863 default:
2864 break;
3956db08 2865 }
e05278af 2866
8ce3d284 2867#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2868 if (other == BFD_RELOC_SIZE32)
2869 {
2870 if (size == 8)
1ab668bf 2871 other = BFD_RELOC_SIZE64;
8fd4256d 2872 if (pcrel)
1ab668bf
AM		 2873 {
2874 as_bad (_("there are no pc-relative size relocations"));
2875 return NO_RELOC;
2876 }
8fd4256d 2877 }
8ce3d284 2878#endif
8fd4256d 2879
e05278af 2880 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2881 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2882 sign = -1;
2883
91d6fa6a
NC		 2884 rel = bfd_reloc_type_lookup (stdoutput, other);
2885 if (!rel)
3956db08 2886 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2887 else if (size != bfd_get_reloc_size (rel))
3956db08 2888 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2889 bfd_get_reloc_size (rel),
3956db08 2890 size);
91d6fa6a 2891 else if (pcrel && !rel->pc_relative)
3956db08 2892 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2893 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2894 && !sign)
91d6fa6a 2895 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2896 && sign > 0))
3956db08
JB		 2897 as_bad (_("relocated field and relocation type differ in signedness"));
2898 else
2899 return other;
2900 return NO_RELOC;
2901 }
252b5132
RH		 2902
2903 if (pcrel)
2904 {
3e73aa7c 2905 if (!sign)
3956db08 2906 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2907 switch (size)
2908 {
2909 case 1: return BFD_RELOC_8_PCREL;
2910 case 2: return BFD_RELOC_16_PCREL;
d258b828 2911 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2912 case 8: return BFD_RELOC_64_PCREL;
252b5132 2913 }
3956db08 2914 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2915 }
2916 else
2917 {
3956db08 2918 if (sign > 0)
e5cb08ac 2919 switch (size)
3e73aa7c
JH		 2920 {
2921 case 4: return BFD_RELOC_X86_64_32S;
2922 }
2923 else
2924 switch (size)
2925 {
2926 case 1: return BFD_RELOC_8;
2927 case 2: return BFD_RELOC_16;
2928 case 4: return BFD_RELOC_32;
2929 case 8: return BFD_RELOC_64;
2930 }
3956db08
JB		 2931 as_bad (_("cannot do %s %u byte relocation"),
2932 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2933 }
2934
0cc9e1d3 2935 return NO_RELOC;
252b5132
RH		 2936}
2937
47926f60
KH		 2938/* Here we decide which fixups can be adjusted to make them relative to
2939 the beginning of the section instead of the symbol. Basically we need
2940 to make sure that the dynamic relocations are done correctly, so in
2941 some cases we force the original symbol to be used. */
2942
252b5132 2943int
e3bb37b5 2944tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2945{
6d249963 2946#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2947 if (!IS_ELF)
31312f95
AM		 2948 return 1;
2949
a161fe53
AM		 2950 /* Don't adjust pc-relative references to merge sections in 64-bit
2951 mode. */
2952 if (use_rela_relocations
2953 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2954 && fixP->fx_pcrel)
252b5132 2955 return 0;
31312f95 2956
8d01d9a9
AJ		 2957 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2958 and changed later by validate_fix. */
2959 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2960 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2961 return 0;
2962
8fd4256d
L		 2963 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2964 for size relocations. */
2965 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2966 || fixP->fx_r_type == BFD_RELOC_SIZE64
2967 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2968 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2969 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2970 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2971 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2972 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2973 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2974 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2975 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2976 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2977 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2978 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2979 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2980 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2981 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2982 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2983 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2984 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2985 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2986 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2987 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2988 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2989 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2990 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2991 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2992 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2993 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2994 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2995 return 0;
31312f95 2996#endif
252b5132
RH		 2997 return 1;
2998}
252b5132 2999
b4cac588 3000static int
e3bb37b5 3001intel_float_operand (const char *mnemonic)
252b5132 3002{
9306ca4a
JB		 3003 /* Note that the value returned is meaningful only for opcodes with (memory)
3004 operands, hence the code here is free to improperly handle opcodes that
3005 have no operands (for better performance and smaller code). */
3006
3007 if (mnemonic[0] != 'f')
3008 return 0; /* non-math */
3009
3010 switch (mnemonic[1])
3011 {
3012 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3013 the fs segment override prefix not currently handled because no
3014 call path can make opcodes without operands get here */
3015 case 'i':
3016 return 2 /* integer op */;
3017 case 'l':
3018 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3019 return 3; /* fldcw/fldenv */
3020 break;
3021 case 'n':
3022 if (mnemonic[2] != 'o' /* fnop */)
3023 return 3; /* non-waiting control op */
3024 break;
3025 case 'r':
3026 if (mnemonic[2] == 's')
3027 return 3; /* frstor/frstpm */
3028 break;
3029 case 's':
3030 if (mnemonic[2] == 'a')
3031 return 3; /* fsave */
3032 if (mnemonic[2] == 't')
3033 {
3034 switch (mnemonic[3])
3035 {
3036 case 'c': /* fstcw */
3037 case 'd': /* fstdw */
3038 case 'e': /* fstenv */
3039 case 's': /* fsts[gw] */
3040 return 3;
3041 }
3042 }
3043 break;
3044 case 'x':
3045 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3046 return 0; /* fxsave/fxrstor are not really math ops */
3047 break;
3048 }
252b5132 3049
9306ca4a 3050 return 1;
252b5132
RH		 3051}
3052
c0f3af97
L		 3053/* Build the VEX prefix. */
3054
3055static void
d3ce72d0 3056build_vex_prefix (const insn_template *t)
c0f3af97
L		 3057{
3058 unsigned int register_specifier;
3059 unsigned int implied_prefix;
3060 unsigned int vector_length;
3061
3062 /* Check register specifier. */
3063 if (i.vex.register_specifier)
43234a1e
L		 3064 {
3065 register_specifier =
3066 ~register_number (i.vex.register_specifier) & 0xf;
3067 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3068 }
c0f3af97
L		 3069 else
3070 register_specifier = 0xf;
3071
fa99fab2
L		 3072 /* Use 2-byte VEX prefix by swappping destination and source
3073 operand. */
3074 if (!i.swap_operand
3075 && i.operands == i.reg_operands
7f399153 3076 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3077 && i.tm.opcode_modifier.s
3078 && i.rex == REX_B)
3079 {
3080 unsigned int xchg = i.operands - 1;
3081 union i386_op temp_op;
3082 i386_operand_type temp_type;
3083
3084 temp_type = i.types[xchg];
3085 i.types[xchg] = i.types[0];
3086 i.types[0] = temp_type;
3087 temp_op = i.op[xchg];
3088 i.op[xchg] = i.op[0];
3089 i.op[0] = temp_op;
3090
9c2799c2 3091 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3092
3093 i.rex = REX_R;
3094 xchg = i.rm.regmem;
3095 i.rm.regmem = i.rm.reg;
3096 i.rm.reg = xchg;
3097
3098 /* Use the next insn. */
3099 i.tm = t[1];
3100 }
3101
539f890d
L		 3102 if (i.tm.opcode_modifier.vex == VEXScalar)
3103 vector_length = avxscalar;
3104 else
3105 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3106
3107 switch ((i.tm.base_opcode >> 8) & 0xff)
3108 {
3109 case 0:
3110 implied_prefix = 0;
3111 break;
3112 case DATA_PREFIX_OPCODE:
3113 implied_prefix = 1;
3114 break;
3115 case REPE_PREFIX_OPCODE:
3116 implied_prefix = 2;
3117 break;
3118 case REPNE_PREFIX_OPCODE:
3119 implied_prefix = 3;
3120 break;
3121 default:
3122 abort ();
3123 }
3124
3125 /* Use 2-byte VEX prefix if possible. */
7f399153 3126 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3127 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3128 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3129 {
3130 /* 2-byte VEX prefix. */
3131 unsigned int r;
3132
3133 i.vex.length = 2;
3134 i.vex.bytes[0] = 0xc5;
3135
3136 /* Check the REX.R bit. */
3137 r = (i.rex & REX_R) ? 0 : 1;
3138 i.vex.bytes[1] = (r << 7
3139 | register_specifier << 3
3140 | vector_length << 2
3141 | implied_prefix);
3142 }
3143 else
3144 {
3145 /* 3-byte VEX prefix. */
3146 unsigned int m, w;
3147
f88c9eb0 3148 i.vex.length = 3;
f88c9eb0 3149
7f399153 3150 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3151 {
7f399153
L		 3152 case VEX0F:
3153 m = 0x1;
80de6e00 3154 i.vex.bytes[0] = 0xc4;
7f399153
L		 3155 break;
3156 case VEX0F38:
3157 m = 0x2;
80de6e00 3158 i.vex.bytes[0] = 0xc4;
7f399153
L		 3159 break;
3160 case VEX0F3A:
3161 m = 0x3;
80de6e00 3162 i.vex.bytes[0] = 0xc4;
7f399153
L		 3163 break;
3164 case XOP08:
5dd85c99
SP		 3165 m = 0x8;
3166 i.vex.bytes[0] = 0x8f;
7f399153
L		 3167 break;
3168 case XOP09:
f88c9eb0
SP		 3169 m = 0x9;
3170 i.vex.bytes[0] = 0x8f;
7f399153
L		 3171 break;
3172 case XOP0A:
f88c9eb0
SP		 3173 m = 0xa;
3174 i.vex.bytes[0] = 0x8f;
7f399153
L		 3175 break;
3176 default:
3177 abort ();
f88c9eb0 3178 }
c0f3af97 3179
c0f3af97
L		 3180 /* The high 3 bits of the second VEX byte are 1's compliment
3181 of RXB bits from REX. */
3182 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3183
3184 /* Check the REX.W bit. */
3185 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3186 if (i.tm.opcode_modifier.vexw == VEXW1)
3187 w = 1;
c0f3af97
L		 3188
3189 i.vex.bytes[2] = (w << 7
3190 | register_specifier << 3
3191 | vector_length << 2
3192 | implied_prefix);
3193 }
3194}
3195
43234a1e
L		 3196/* Build the EVEX prefix. */
3197
3198static void
3199build_evex_prefix (void)
3200{
3201 unsigned int register_specifier;
3202 unsigned int implied_prefix;
3203 unsigned int m, w;
3204 rex_byte vrex_used = 0;
3205
3206 /* Check register specifier. */
3207 if (i.vex.register_specifier)
3208 {
3209 gas_assert ((i.vrex & REX_X) == 0);
3210
3211 register_specifier = i.vex.register_specifier->reg_num;
3212 if ((i.vex.register_specifier->reg_flags & RegRex))
3213 register_specifier += 8;
3214 /* The upper 16 registers are encoded in the fourth byte of the
3215 EVEX prefix. */
3216 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3217 i.vex.bytes[3] = 0x8;
3218 register_specifier = ~register_specifier & 0xf;
3219 }
3220 else
3221 {
3222 register_specifier = 0xf;
3223
3224 /* Encode upper 16 vector index register in the fourth byte of
3225 the EVEX prefix. */
3226 if (!(i.vrex & REX_X))
3227 i.vex.bytes[3] = 0x8;
3228 else
3229 vrex_used |= REX_X;
3230 }
3231
3232 switch ((i.tm.base_opcode >> 8) & 0xff)
3233 {
3234 case 0:
3235 implied_prefix = 0;
3236 break;
3237 case DATA_PREFIX_OPCODE:
3238 implied_prefix = 1;
3239 break;
3240 case REPE_PREFIX_OPCODE:
3241 implied_prefix = 2;
3242 break;
3243 case REPNE_PREFIX_OPCODE:
3244 implied_prefix = 3;
3245 break;
3246 default:
3247 abort ();
3248 }
3249
3250 /* 4 byte EVEX prefix. */
3251 i.vex.length = 4;
3252 i.vex.bytes[0] = 0x62;
3253
3254 /* mmmm bits. */
3255 switch (i.tm.opcode_modifier.vexopcode)
3256 {
3257 case VEX0F:
3258 m = 1;
3259 break;
3260 case VEX0F38:
3261 m = 2;
3262 break;
3263 case VEX0F3A:
3264 m = 3;
3265 break;
3266 default:
3267 abort ();
3268 break;
3269 }
3270
3271 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3272 bits from REX. */
3273 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3274
3275 /* The fifth bit of the second EVEX byte is 1's compliment of the
3276 REX_R bit in VREX. */
3277 if (!(i.vrex & REX_R))
3278 i.vex.bytes[1] |= 0x10;
3279 else
3280 vrex_used |= REX_R;
3281
3282 if ((i.reg_operands + i.imm_operands) == i.operands)
3283 {
3284 /* When all operands are registers, the REX_X bit in REX is not
3285 used. We reuse it to encode the upper 16 registers, which is
3286 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3287 as 1's compliment. */
3288 if ((i.vrex & REX_B))
3289 {
3290 vrex_used |= REX_B;
3291 i.vex.bytes[1] &= ~0x40;
3292 }
3293 }
3294
3295 /* EVEX instructions shouldn't need the REX prefix. */
3296 i.vrex &= ~vrex_used;
3297 gas_assert (i.vrex == 0);
3298
3299 /* Check the REX.W bit. */
3300 w = (i.rex & REX_W) ? 1 : 0;
3301 if (i.tm.opcode_modifier.vexw)
3302 {
3303 if (i.tm.opcode_modifier.vexw == VEXW1)
3304 w = 1;
3305 }
3306 /* If w is not set it means we are dealing with WIG instruction. */
3307 else if (!w)
3308 {
3309 if (evexwig == evexw1)
3310 w = 1;
3311 }
3312
3313 /* Encode the U bit. */
3314 implied_prefix |= 0x4;
3315
3316 /* The third byte of the EVEX prefix. */
3317 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3318
3319 /* The fourth byte of the EVEX prefix. */
3320 /* The zeroing-masking bit. */
3321 if (i.mask && i.mask->zeroing)
3322 i.vex.bytes[3] |= 0x80;
3323
3324 /* Don't always set the broadcast bit if there is no RC. */
3325 if (!i.rounding)
3326 {
3327 /* Encode the vector length. */
3328 unsigned int vec_length;
3329
3330 switch (i.tm.opcode_modifier.evex)
3331 {
3332 case EVEXLIG: /* LL' is ignored */
3333 vec_length = evexlig << 5;
3334 break;
3335 case EVEX128:
3336 vec_length = 0 << 5;
3337 break;
3338 case EVEX256:
3339 vec_length = 1 << 5;
3340 break;
3341 case EVEX512:
3342 vec_length = 2 << 5;
3343 break;
3344 default:
3345 abort ();
3346 break;
3347 }
3348 i.vex.bytes[3] |= vec_length;
3349 /* Encode the broadcast bit. */
3350 if (i.broadcast)
3351 i.vex.bytes[3] |= 0x10;
3352 }
3353 else
3354 {
3355 if (i.rounding->type != saeonly)
3356 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3357 else
d3d3c6db 3358 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3359 }
3360
3361 if (i.mask && i.mask->mask)
3362 i.vex.bytes[3] |= i.mask->mask->reg_num;
3363}
3364
65da13b5
L		 3365static void
3366process_immext (void)
3367{
3368 expressionS *exp;
3369
4c692bc7
JB		 3370 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3371 && i.operands > 0)
65da13b5 3372 {
4c692bc7
JB		 3373 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3374 with an opcode suffix which is coded in the same place as an
3375 8-bit immediate field would be.
3376 Here we check those operands and remove them afterwards. */
65da13b5
L		 3377 unsigned int x;
3378
3379 for (x = 0; x < i.operands; x++)
4c692bc7 3380 if (register_number (i.op[x].regs) != x)
65da13b5 3381 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3382 register_prefix, i.op[x].regs->reg_name, x + 1,
3383 i.tm.name);
3384
3385 i.operands = 0;
65da13b5
L		 3386 }
3387
c0f3af97 3388 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3389 which is coded in the same place as an 8-bit immediate field
3390 would be. Here we fake an 8-bit immediate operand from the
3391 opcode suffix stored in tm.extension_opcode.
3392
c1e679ec 3393 AVX instructions also use this encoding, for some of
c0f3af97 3394 3 argument instructions. */
65da13b5 3395
43234a1e 3396 gas_assert (i.imm_operands <= 1
7ab9ffdd 3397 && (i.operands <= 2
43234a1e
L		 3398 || ((i.tm.opcode_modifier.vex
3399 || i.tm.opcode_modifier.evex)
7ab9ffdd 3400 && i.operands <= 4)));
65da13b5
L		 3401
3402 exp = &im_expressions[i.imm_operands++];
3403 i.op[i.operands].imms = exp;
3404 i.types[i.operands] = imm8;
3405 i.operands++;
3406 exp->X_op = O_constant;
3407 exp->X_add_number = i.tm.extension_opcode;
3408 i.tm.extension_opcode = None;
3409}
3410
42164a71
L		 3411
3412static int
3413check_hle (void)
3414{
3415 switch (i.tm.opcode_modifier.hleprefixok)
3416 {
3417 default:
3418 abort ();
82c2def5 3419 case HLEPrefixNone:
165de32a
L		 3420 as_bad (_("invalid instruction `%s' after `%s'"),
3421 i.tm.name, i.hle_prefix);
42164a71 3422 return 0;
82c2def5 3423 case HLEPrefixLock:
42164a71
L		 3424 if (i.prefix[LOCK_PREFIX])
3425 return 1;
165de32a 3426 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3427 return 0;
82c2def5 3428 case HLEPrefixAny:
42164a71 3429 return 1;
82c2def5 3430 case HLEPrefixRelease:
42164a71
L		 3431 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3432 {
3433 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3434 i.tm.name);
3435 return 0;
3436 }
3437 if (i.mem_operands == 0
3438 || !operand_type_check (i.types[i.operands - 1], anymem))
3439 {
3440 as_bad (_("memory destination needed for instruction `%s'"
3441 " after `xrelease'"), i.tm.name);
3442 return 0;
3443 }
3444 return 1;
3445 }
3446}
3447
252b5132
RH		 3448/* This is the guts of the machine-dependent assembler. LINE points to a
3449 machine dependent instruction. This function is supposed to emit
3450 the frags/bytes it assembles to. */
3451
3452void
65da13b5 3453md_assemble (char *line)
252b5132 3454{
40fb9820 3455 unsigned int j;
252b5132 3456 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3457 const insn_template *t;
252b5132 3458
47926f60 3459 /* Initialize globals. */
252b5132
RH		 3460 memset (&i, '\0', sizeof (i));
3461 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3462 i.reloc[j] = NO_RELOC;
252b5132
RH		 3463 memset (disp_expressions, '\0', sizeof (disp_expressions));
3464 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3465 save_stack_p = save_stack;
252b5132
RH		 3466
3467 /* First parse an instruction mnemonic & call i386_operand for the operands.
3468 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3469 start of a (possibly prefixed) mnemonic. */
252b5132 3470
29b0f896
AM		 3471 line = parse_insn (line, mnemonic);
3472 if (line == NULL)
3473 return;
252b5132 3474
29b0f896 3475 line = parse_operands (line, mnemonic);
ee86248c 3476 this_operand = -1;
29b0f896
AM		 3477 if (line == NULL)
3478 return;
252b5132 3479
29b0f896
AM		 3480 /* Now we've parsed the mnemonic into a set of templates, and have the
3481 operands at hand. */
3482
3483 /* All intel opcodes have reversed operands except for "bound" and
3484 "enter". We also don't reverse intersegment "jmp" and "call"
3485 instructions with 2 immediate operands so that the immediate segment
050dfa73 3486 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3487 if (intel_syntax
3488 && i.operands > 1
29b0f896 3489 && (strcmp (mnemonic, "bound") != 0)
30123838 3490 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3491 && !(operand_type_check (i.types[0], imm)
3492 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3493 swap_operands ();
3494
ec56d5c0
JB		 3495 /* The order of the immediates should be reversed
3496 for 2 immediates extrq and insertq instructions */
3497 if (i.imm_operands == 2
3498 && (strcmp (mnemonic, "extrq") == 0
3499 || strcmp (mnemonic, "insertq") == 0))
3500 swap_2_operands (0, 1);
3501
29b0f896
AM		 3502 if (i.imm_operands)
3503 optimize_imm ();
3504
b300c311
L		 3505 /* Don't optimize displacement for movabs since it only takes 64bit
3506 displacement. */
3507 if (i.disp_operands
a501d77e 3508 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3509 && (flag_code != CODE_64BIT
3510 || strcmp (mnemonic, "movabs") != 0))
3511 optimize_disp ();
29b0f896
AM		 3512
3513 /* Next, we find a template that matches the given insn,
3514 making sure the overlap of the given operands types is consistent
3515 with the template operand types. */
252b5132 3516
fa99fab2 3517 if (!(t = match_template ()))
29b0f896 3518 return;
252b5132 3519
7bab8ab5 3520 if (sse_check != check_none
81f8a913 3521 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3522 && (i.tm.cpu_flags.bitfield.cpusse
3523 || i.tm.cpu_flags.bitfield.cpusse2
3524 || i.tm.cpu_flags.bitfield.cpusse3
3525 || i.tm.cpu_flags.bitfield.cpussse3
3526 || i.tm.cpu_flags.bitfield.cpusse4_1
3527 || i.tm.cpu_flags.bitfield.cpusse4_2))
3528 {
7bab8ab5 3529 (sse_check == check_warning
daf50ae7
L		 3530 ? as_warn
3531 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3532 }
3533
321fd21e
L		 3534 /* Zap movzx and movsx suffix. The suffix has been set from
3535 "word ptr" or "byte ptr" on the source operand in Intel syntax
3536 or extracted from mnemonic in AT&T syntax. But we'll use
3537 the destination register to choose the suffix for encoding. */
3538 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3539 {
321fd21e
L		 3540 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3541 there is no suffix, the default will be byte extension. */
3542 if (i.reg_operands != 2
3543 && !i.suffix
7ab9ffdd 3544 && intel_syntax)
321fd21e
L		 3545 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3546
3547 i.suffix = 0;
cd61ebfe 3548 }
24eab124 3549
40fb9820 3550 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3551 if (!add_prefix (FWAIT_OPCODE))
3552 return;
252b5132 3553
d5de92cf
L		 3554 /* Check if REP prefix is OK. */
3555 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3556 {
3557 as_bad (_("invalid instruction `%s' after `%s'"),
3558 i.tm.name, i.rep_prefix);
3559 return;
3560 }
3561
c1ba0266
L		 3562 /* Check for lock without a lockable instruction. Destination operand
3563 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3564 if (i.prefix[LOCK_PREFIX]
3565 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3566 || i.mem_operands == 0
3567 || (i.tm.base_opcode != 0x86
3568 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3569 {
3570 as_bad (_("expecting lockable instruction after `lock'"));
3571 return;
3572 }
3573
42164a71 3574 /* Check if HLE prefix is OK. */
165de32a 3575 if (i.hle_prefix && !check_hle ())
42164a71
L		 3576 return;
3577
7e8b059b
L		 3578 /* Check BND prefix. */
3579 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3580 as_bad (_("expecting valid branch instruction after `bnd'"));
3581
3582 if (i.tm.cpu_flags.bitfield.cpumpx
3583 && flag_code == CODE_64BIT
3584 && i.prefix[ADDR_PREFIX])
3585 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3586
3587 /* Insert BND prefix. */
3588 if (add_bnd_prefix
3589 && i.tm.opcode_modifier.bndprefixok
3590 && !i.prefix[BND_PREFIX])
3591 add_prefix (BND_PREFIX_OPCODE);
3592
29b0f896 3593 /* Check string instruction segment overrides. */
40fb9820 3594 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3595 {
3596 if (!check_string ())
5dd0794d 3597 return;
fc0763e6 3598 i.disp_operands = 0;
29b0f896 3599 }
5dd0794d 3600
29b0f896
AM		 3601 if (!process_suffix ())
3602 return;
e413e4e9 3603
bc0844ae
L		 3604 /* Update operand types. */
3605 for (j = 0; j < i.operands; j++)
3606 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3607
29b0f896
AM		 3608 /* Make still unresolved immediate matches conform to size of immediate
3609 given in i.suffix. */
3610 if (!finalize_imm ())
3611 return;
252b5132 3612
40fb9820 3613 if (i.types[0].bitfield.imm1)
29b0f896 3614 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3615
9afe6eb8
L		 3616 /* We only need to check those implicit registers for instructions
3617 with 3 operands or less. */
3618 if (i.operands <= 3)
3619 for (j = 0; j < i.operands; j++)
3620 if (i.types[j].bitfield.inoutportreg
3621 || i.types[j].bitfield.shiftcount
3622 || i.types[j].bitfield.acc
3623 || i.types[j].bitfield.floatacc)
3624 i.reg_operands--;
40fb9820 3625
c0f3af97
L		 3626 /* ImmExt should be processed after SSE2AVX. */
3627 if (!i.tm.opcode_modifier.sse2avx
3628 && i.tm.opcode_modifier.immext)
65da13b5 3629 process_immext ();
252b5132 3630
29b0f896
AM		 3631 /* For insns with operands there are more diddles to do to the opcode. */
3632 if (i.operands)
3633 {
3634 if (!process_operands ())
3635 return;
3636 }
40fb9820 3637 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3638 {
3639 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3640 as_warn (_("translating to `%sp'"), i.tm.name);
3641 }
252b5132 3642
9e5e5283
L		 3643 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3644 {
3645 if (flag_code == CODE_16BIT)
3646 {
3647 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3648 i.tm.name);
3649 return;
3650 }
c0f3af97 3651
9e5e5283
L		 3652 if (i.tm.opcode_modifier.vex)
3653 build_vex_prefix (t);
3654 else
3655 build_evex_prefix ();
3656 }
43234a1e 3657
5dd85c99
SP		 3658 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3659 instructions may define INT_OPCODE as well, so avoid this corner
3660 case for those instructions that use MODRM. */
3661 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3662 && !i.tm.opcode_modifier.modrm
3663 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3664 {
3665 i.tm.base_opcode = INT3_OPCODE;
3666 i.imm_operands = 0;
3667 }
252b5132 3668
40fb9820
L		 3669 if ((i.tm.opcode_modifier.jump
3670 || i.tm.opcode_modifier.jumpbyte
3671 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3672 && i.op[0].disps->X_op == O_constant)
3673 {
3674 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3675 the absolute address given by the constant. Since ix86 jumps and
3676 calls are pc relative, we need to generate a reloc. */
3677 i.op[0].disps->X_add_symbol = &abs_symbol;
3678 i.op[0].disps->X_op = O_symbol;
3679 }
252b5132 3680
40fb9820 3681 if (i.tm.opcode_modifier.rex64)
161a04f6 3682 i.rex |= REX_W;
252b5132 3683
29b0f896
AM		 3684 /* For 8 bit registers we need an empty rex prefix. Also if the
3685 instruction already has a prefix, we need to convert old
3686 registers to new ones. */
773f551c 3687
40fb9820 3688 if ((i.types[0].bitfield.reg8
29b0f896 3689 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3690 || (i.types[1].bitfield.reg8
29b0f896 3691 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3692 || ((i.types[0].bitfield.reg8
3693 || i.types[1].bitfield.reg8)
29b0f896
AM		 3694 && i.rex != 0))
3695 {
3696 int x;
726c5dcd 3697
29b0f896
AM		 3698 i.rex |= REX_OPCODE;
3699 for (x = 0; x < 2; x++)
3700 {
3701 /* Look for 8 bit operand that uses old registers. */
40fb9820 3702 if (i.types[x].bitfield.reg8
29b0f896 3703 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3704 {
29b0f896
AM		 3705 /* In case it is "hi" register, give up. */
3706 if (i.op[x].regs->reg_num > 3)
a540244d 3707 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3708 "instruction requiring REX prefix."),
a540244d 3709 register_prefix, i.op[x].regs->reg_name);
773f551c 3710
29b0f896
AM		 3711 /* Otherwise it is equivalent to the extended register.
3712 Since the encoding doesn't change this is merely
3713 cosmetic cleanup for debug output. */
3714
3715 i.op[x].regs = i.op[x].regs + 8;
773f551c 3716 }
29b0f896
AM		 3717 }
3718 }
773f551c 3719
7ab9ffdd 3720 if (i.rex != 0)
29b0f896
AM		 3721 add_prefix (REX_OPCODE | i.rex);
3722
3723 /* We are ready to output the insn. */
3724 output_insn ();
3725}
3726
3727static char *
e3bb37b5 3728parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3729{
3730 char *l = line;
3731 char *token_start = l;
3732 char *mnem_p;
5c6af06e 3733 int supported;
d3ce72d0 3734 const insn_template *t;
b6169b20 3735 char *dot_p = NULL;
29b0f896 3736
29b0f896
AM		 3737 while (1)
3738 {
3739 mnem_p = mnemonic;
3740 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3741 {
b6169b20
L		 3742 if (*mnem_p == '.')
3743 dot_p = mnem_p;
29b0f896
AM		 3744 mnem_p++;
3745 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3746 {
29b0f896
AM		 3747 as_bad (_("no such instruction: `%s'"), token_start);
3748 return NULL;
3749 }
3750 l++;
3751 }
3752 if (!is_space_char (*l)
3753 && *l != END_OF_INSN
e44823cf
JB		 3754 && (intel_syntax
3755 || (*l != PREFIX_SEPARATOR
3756 && *l != ',')))
29b0f896
AM		 3757 {
3758 as_bad (_("invalid character %s in mnemonic"),
3759 output_invalid (*l));
3760 return NULL;
3761 }
3762 if (token_start == l)
3763 {
e44823cf 3764 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3765 as_bad (_("expecting prefix; got nothing"));
3766 else
3767 as_bad (_("expecting mnemonic; got nothing"));
3768 return NULL;
3769 }
45288df1 3770
29b0f896 3771 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3772 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3773
29b0f896
AM		 3774 if (*l != END_OF_INSN
3775 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3776 && current_templates
40fb9820 3777 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3778 {
c6fb90c8 3779 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3780 {
3781 as_bad ((flag_code != CODE_64BIT
3782 ? _("`%s' is only supported in 64-bit mode")
3783 : _("`%s' is not supported in 64-bit mode")),
3784 current_templates->start->name);
3785 return NULL;
3786 }
29b0f896
AM		 3787 /* If we are in 16-bit mode, do not allow addr16 or data16.
3788 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3789 if ((current_templates->start->opcode_modifier.size16
3790 || current_templates->start->opcode_modifier.size32)
29b0f896 3791 && flag_code != CODE_64BIT
40fb9820 3792 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3793 ^ (flag_code == CODE_16BIT)))
3794 {
3795 as_bad (_("redundant %s prefix"),
3796 current_templates->start->name);
3797 return NULL;
45288df1 3798 }
29b0f896
AM		 3799 /* Add prefix, checking for repeated prefixes. */
3800 switch (add_prefix (current_templates->start->base_opcode))
3801 {
c32fa91d 3802 case PREFIX_EXIST:
29b0f896 3803 return NULL;
c32fa91d 3804 case PREFIX_REP:
42164a71 3805 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3806 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3807 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3808 i.bnd_prefix = current_templates->start->name;
42164a71 3809 else
d5de92cf 3810 i.rep_prefix = current_templates->start->name;
29b0f896 3811 break;
c32fa91d
L		 3812 default:
3813 break;
29b0f896
AM		 3814 }
3815 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3816 token_start = ++l;
3817 }
3818 else
3819 break;
3820 }
45288df1 3821
30a55f88 3822 if (!current_templates)
b6169b20 3823 {
f8a5c266
L		 3824 /* Check if we should swap operand or force 32bit displacement in
3825 encoding. */
30a55f88
L		 3826 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3827 i.swap_operand = 1;
8d63c93e 3828 else if (mnem_p - 3 == dot_p
a501d77e
L		 3829 && dot_p[1] == 'd'
3830 && dot_p[2] == '8')
3831 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3832 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3833 && dot_p[1] == 'd'
3834 && dot_p[2] == '3'
3835 && dot_p[3] == '2')
a501d77e 3836 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3837 else
3838 goto check_suffix;
3839 mnem_p = dot_p;
3840 *dot_p = '\0';
d3ce72d0 3841 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3842 }
3843
29b0f896
AM		 3844 if (!current_templates)
3845 {
b6169b20 3846check_suffix:
29b0f896
AM		 3847 /* See if we can get a match by trimming off a suffix. */
3848 switch (mnem_p[-1])
3849 {
3850 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3851 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3852 i.suffix = SHORT_MNEM_SUFFIX;
3853 else
29b0f896
AM		 3854 case BYTE_MNEM_SUFFIX:
3855 case QWORD_MNEM_SUFFIX:
3856 i.suffix = mnem_p[-1];
3857 mnem_p[-1] = '\0';
d3ce72d0
NC		 3858 current_templates = (const templates *) hash_find (op_hash,
3859 mnemonic);
29b0f896
AM		 3860 break;
3861 case SHORT_MNEM_SUFFIX:
3862 case LONG_MNEM_SUFFIX:
3863 if (!intel_syntax)
3864 {
3865 i.suffix = mnem_p[-1];
3866 mnem_p[-1] = '\0';
d3ce72d0
NC		 3867 current_templates = (const templates *) hash_find (op_hash,
3868 mnemonic);
29b0f896
AM		 3869 }
3870 break;
252b5132 3871
29b0f896
AM		 3872 /* Intel Syntax. */
3873 case 'd':
3874 if (intel_syntax)
3875 {
9306ca4a 3876 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3877 i.suffix = SHORT_MNEM_SUFFIX;
3878 else
3879 i.suffix = LONG_MNEM_SUFFIX;
3880 mnem_p[-1] = '\0';
d3ce72d0
NC		 3881 current_templates = (const templates *) hash_find (op_hash,
3882 mnemonic);
29b0f896
AM		 3883 }
3884 break;
3885 }
3886 if (!current_templates)
3887 {
3888 as_bad (_("no such instruction: `%s'"), token_start);
3889 return NULL;
3890 }
3891 }
252b5132 3892
40fb9820
L		 3893 if (current_templates->start->opcode_modifier.jump
3894 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3895 {
3896 /* Check for a branch hint. We allow ",pt" and ",pn" for
3897 predict taken and predict not taken respectively.
3898 I'm not sure that branch hints actually do anything on loop
3899 and jcxz insns (JumpByte) for current Pentium4 chips. They
3900 may work in the future and it doesn't hurt to accept them
3901 now. */
3902 if (l[0] == ',' && l[1] == 'p')
3903 {
3904 if (l[2] == 't')
3905 {
3906 if (!add_prefix (DS_PREFIX_OPCODE))
3907 return NULL;
3908 l += 3;
3909 }
3910 else if (l[2] == 'n')
3911 {
3912 if (!add_prefix (CS_PREFIX_OPCODE))
3913 return NULL;
3914 l += 3;
3915 }
3916 }
3917 }
3918 /* Any other comma loses. */
3919 if (*l == ',')
3920 {
3921 as_bad (_("invalid character %s in mnemonic"),
3922 output_invalid (*l));
3923 return NULL;
3924 }
252b5132 3925
29b0f896 3926 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3927 supported = 0;
3928 for (t = current_templates->start; t < current_templates->end; ++t)
3929 {
c0f3af97
L		 3930 supported |= cpu_flags_match (t);
3931 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3932 goto skip;
5c6af06e 3933 }
3629bb00 3934
c0f3af97 3935 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3936 {
3937 as_bad (flag_code == CODE_64BIT
3938 ? _("`%s' is not supported in 64-bit mode")
3939 : _("`%s' is only supported in 64-bit mode"),
3940 current_templates->start->name);
3941 return NULL;
3942 }
c0f3af97 3943 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3944 {
3629bb00 3945 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3946 current_templates->start->name,
41aacd83 3947 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3948 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3949 return NULL;
29b0f896 3950 }
3629bb00
L		 3951
3952skip:
3953 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3954 && (flag_code != CODE_16BIT))
29b0f896
AM		 3955 {
3956 as_warn (_("use .code16 to ensure correct addressing mode"));
3957 }
252b5132 3958
29b0f896
AM		 3959 return l;
3960}
252b5132 3961
29b0f896 3962static char *
e3bb37b5 3963parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3964{
3965 char *token_start;
3138f287 3966
29b0f896
AM		 3967 /* 1 if operand is pending after ','. */
3968 unsigned int expecting_operand = 0;
252b5132 3969
29b0f896
AM		 3970 /* Non-zero if operand parens not balanced. */
3971 unsigned int paren_not_balanced;
3972
3973 while (*l != END_OF_INSN)
3974 {
3975 /* Skip optional white space before operand. */
3976 if (is_space_char (*l))
3977 ++l;
3978 if (!is_operand_char (*l) && *l != END_OF_INSN)
3979 {
3980 as_bad (_("invalid character %s before operand %d"),
3981 output_invalid (*l),
3982 i.operands + 1);
3983 return NULL;
3984 }
3985 token_start = l; /* after white space */
3986 paren_not_balanced = 0;
3987 while (paren_not_balanced || *l != ',')
3988 {
3989 if (*l == END_OF_INSN)
3990 {
3991 if (paren_not_balanced)
3992 {
3993 if (!intel_syntax)
3994 as_bad (_("unbalanced parenthesis in operand %d."),
3995 i.operands + 1);
3996 else
3997 as_bad (_("unbalanced brackets in operand %d."),
3998 i.operands + 1);
3999 return NULL;
4000 }
4001 else
4002 break; /* we are done */
4003 }
4004 else if (!is_operand_char (*l) && !is_space_char (*l))
4005 {
4006 as_bad (_("invalid character %s in operand %d"),
4007 output_invalid (*l),
4008 i.operands + 1);
4009 return NULL;
4010 }
4011 if (!intel_syntax)
4012 {
4013 if (*l == '(')
4014 ++paren_not_balanced;
4015 if (*l == ')')
4016 --paren_not_balanced;
4017 }
4018 else
4019 {
4020 if (*l == '[')
4021 ++paren_not_balanced;
4022 if (*l == ']')
4023 --paren_not_balanced;
4024 }
4025 l++;
4026 }
4027 if (l != token_start)
4028 { /* Yes, we've read in another operand. */
4029 unsigned int operand_ok;
4030 this_operand = i.operands++;
7d5e4556 4031 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4032 if (i.operands > MAX_OPERANDS)
4033 {
4034 as_bad (_("spurious operands; (%d operands/instruction max)"),
4035 MAX_OPERANDS);
4036 return NULL;
4037 }
4038 /* Now parse operand adding info to 'i' as we go along. */
4039 END_STRING_AND_SAVE (l);
4040
4041 if (intel_syntax)
4042 operand_ok =
4043 i386_intel_operand (token_start,
4044 intel_float_operand (mnemonic));
4045 else
a7619375 4046 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4047
4048 RESTORE_END_STRING (l);
4049 if (!operand_ok)
4050 return NULL;
4051 }
4052 else
4053 {
4054 if (expecting_operand)
4055 {
4056 expecting_operand_after_comma:
4057 as_bad (_("expecting operand after ','; got nothing"));
4058 return NULL;
4059 }
4060 if (*l == ',')
4061 {
4062 as_bad (_("expecting operand before ','; got nothing"));
4063 return NULL;
4064 }
4065 }
7f3f1ea2 4066
29b0f896
AM		 4067 /* Now *l must be either ',' or END_OF_INSN. */
4068 if (*l == ',')
4069 {
4070 if (*++l == END_OF_INSN)
4071 {
4072 /* Just skip it, if it's \n complain. */
4073 goto expecting_operand_after_comma;
4074 }
4075 expecting_operand = 1;
4076 }
4077 }
4078 return l;
4079}
7f3f1ea2 4080
050dfa73 4081static void
4d456e3d 4082swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4083{
4084 union i386_op temp_op;
40fb9820 4085 i386_operand_type temp_type;
050dfa73 4086 enum bfd_reloc_code_real temp_reloc;
4eed87de 4087
050dfa73
MM		 4088 temp_type = i.types[xchg2];
4089 i.types[xchg2] = i.types[xchg1];
4090 i.types[xchg1] = temp_type;
4091 temp_op = i.op[xchg2];
4092 i.op[xchg2] = i.op[xchg1];
4093 i.op[xchg1] = temp_op;
4094 temp_reloc = i.reloc[xchg2];
4095 i.reloc[xchg2] = i.reloc[xchg1];
4096 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4097
4098 if (i.mask)
4099 {
4100 if (i.mask->operand == xchg1)
4101 i.mask->operand = xchg2;
4102 else if (i.mask->operand == xchg2)
4103 i.mask->operand = xchg1;
4104 }
4105 if (i.broadcast)
4106 {
4107 if (i.broadcast->operand == xchg1)
4108 i.broadcast->operand = xchg2;
4109 else if (i.broadcast->operand == xchg2)
4110 i.broadcast->operand = xchg1;
4111 }
4112 if (i.rounding)
4113 {
4114 if (i.rounding->operand == xchg1)
4115 i.rounding->operand = xchg2;
4116 else if (i.rounding->operand == xchg2)
4117 i.rounding->operand = xchg1;
4118 }
050dfa73
MM		 4119}
4120
29b0f896 4121static void
e3bb37b5 4122swap_operands (void)
29b0f896 4123{
b7c61d9a 4124 switch (i.operands)
050dfa73 4125 {
c0f3af97 4126 case 5:
b7c61d9a 4127 case 4:
4d456e3d 4128 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4129 case 3:
4130 case 2:
4d456e3d 4131 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4132 break;
4133 default:
4134 abort ();
29b0f896 4135 }
29b0f896
AM		 4136
4137 if (i.mem_operands == 2)
4138 {
4139 const seg_entry *temp_seg;
4140 temp_seg = i.seg[0];
4141 i.seg[0] = i.seg[1];
4142 i.seg[1] = temp_seg;
4143 }
4144}
252b5132 4145
29b0f896
AM		 4146/* Try to ensure constant immediates are represented in the smallest
4147 opcode possible. */
4148static void
e3bb37b5 4149optimize_imm (void)
29b0f896
AM		 4150{
4151 char guess_suffix = 0;
4152 int op;
252b5132 4153
29b0f896
AM		 4154 if (i.suffix)
4155 guess_suffix = i.suffix;
4156 else if (i.reg_operands)
4157 {
4158 /* Figure out a suffix from the last register operand specified.
4159 We can't do this properly yet, ie. excluding InOutPortReg,
4160 but the following works for instructions with immediates.
4161 In any case, we can't set i.suffix yet. */
4162 for (op = i.operands; --op >= 0;)
40fb9820 4163 if (i.types[op].bitfield.reg8)
7ab9ffdd 4164 {
40fb9820
L		 4165 guess_suffix = BYTE_MNEM_SUFFIX;
4166 break;
4167 }
4168 else if (i.types[op].bitfield.reg16)
252b5132 4169 {
40fb9820
L		 4170 guess_suffix = WORD_MNEM_SUFFIX;
4171 break;
4172 }
4173 else if (i.types[op].bitfield.reg32)
4174 {
4175 guess_suffix = LONG_MNEM_SUFFIX;
4176 break;
4177 }
4178 else if (i.types[op].bitfield.reg64)
4179 {
4180 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4181 break;
252b5132 4182 }
29b0f896
AM		 4183 }
4184 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4185 guess_suffix = WORD_MNEM_SUFFIX;
4186
4187 for (op = i.operands; --op >= 0;)
40fb9820 4188 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4189 {
4190 switch (i.op[op].imms->X_op)
252b5132 4191 {
29b0f896
AM		 4192 case O_constant:
4193 /* If a suffix is given, this operand may be shortened. */
4194 switch (guess_suffix)
252b5132 4195 {
29b0f896 4196 case LONG_MNEM_SUFFIX:
40fb9820
L		 4197 i.types[op].bitfield.imm32 = 1;
4198 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4199 break;
4200 case WORD_MNEM_SUFFIX:
40fb9820
L		 4201 i.types[op].bitfield.imm16 = 1;
4202 i.types[op].bitfield.imm32 = 1;
4203 i.types[op].bitfield.imm32s = 1;
4204 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4205 break;
4206 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4207 i.types[op].bitfield.imm8 = 1;
4208 i.types[op].bitfield.imm8s = 1;
4209 i.types[op].bitfield.imm16 = 1;
4210 i.types[op].bitfield.imm32 = 1;
4211 i.types[op].bitfield.imm32s = 1;
4212 i.types[op].bitfield.imm64 = 1;
29b0f896 4213 break;
252b5132 4214 }
252b5132 4215
29b0f896
AM		 4216 /* If this operand is at most 16 bits, convert it
4217 to a signed 16 bit number before trying to see
4218 whether it will fit in an even smaller size.
4219 This allows a 16-bit operand such as $0xffe0 to
4220 be recognised as within Imm8S range. */
40fb9820 4221 if ((i.types[op].bitfield.imm16)
29b0f896 4222 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4223 {
29b0f896
AM		 4224 i.op[op].imms->X_add_number =
4225 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4226 }
40fb9820 4227 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4228 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4229 == 0))
4230 {
4231 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4232 ^ ((offsetT) 1 << 31))
4233 - ((offsetT) 1 << 31));
4234 }
40fb9820 4235 i.types[op]
c6fb90c8
L		 4236 = operand_type_or (i.types[op],
4237 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4238
29b0f896
AM		 4239 /* We must avoid matching of Imm32 templates when 64bit
4240 only immediate is available. */
4241 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4242 i.types[op].bitfield.imm32 = 0;
29b0f896 4243 break;
252b5132 4244
29b0f896
AM		 4245 case O_absent:
4246 case O_register:
4247 abort ();
4248
4249 /* Symbols and expressions. */
4250 default:
9cd96992
JB		 4251 /* Convert symbolic operand to proper sizes for matching, but don't
4252 prevent matching a set of insns that only supports sizes other
4253 than those matching the insn suffix. */
4254 {
40fb9820 4255 i386_operand_type mask, allowed;
d3ce72d0 4256 const insn_template *t;
9cd96992 4257
0dfbf9d7
L		 4258 operand_type_set (&mask, 0);
4259 operand_type_set (&allowed, 0);
40fb9820 4260
4eed87de
AM		 4261 for (t = current_templates->start;
4262 t < current_templates->end;
4263 ++t)
c6fb90c8
L		 4264 allowed = operand_type_or (allowed,
4265 t->operand_types[op]);
9cd96992
JB		 4266 switch (guess_suffix)
4267 {
4268 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4269 mask.bitfield.imm64 = 1;
4270 mask.bitfield.imm32s = 1;
9cd96992
JB		 4271 break;
4272 case LONG_MNEM_SUFFIX:
40fb9820 4273 mask.bitfield.imm32 = 1;
9cd96992
JB		 4274 break;
4275 case WORD_MNEM_SUFFIX:
40fb9820 4276 mask.bitfield.imm16 = 1;
9cd96992
JB		 4277 break;
4278 case BYTE_MNEM_SUFFIX:
40fb9820 4279 mask.bitfield.imm8 = 1;
9cd96992
JB		 4280 break;
4281 default:
9cd96992
JB		 4282 break;
4283 }
c6fb90c8 4284 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4285 if (!operand_type_all_zero (&allowed))
c6fb90c8 4286 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4287 }
29b0f896 4288 break;
252b5132 4289 }
29b0f896
AM		 4290 }
4291}
47926f60 4292
29b0f896
AM		 4293/* Try to use the smallest displacement type too. */
4294static void
e3bb37b5 4295optimize_disp (void)
29b0f896
AM		 4296{
4297 int op;
3e73aa7c 4298
29b0f896 4299 for (op = i.operands; --op >= 0;)
40fb9820 4300 if (operand_type_check (i.types[op], disp))
252b5132 4301 {
b300c311 4302 if (i.op[op].disps->X_op == O_constant)
252b5132 4303 {
91d6fa6a 4304 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4305
40fb9820 4306 if (i.types[op].bitfield.disp16
91d6fa6a 4307 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4308 {
4309 /* If this operand is at most 16 bits, convert
4310 to a signed 16 bit number and don't use 64bit
4311 displacement. */
91d6fa6a 4312 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4313 i.types[op].bitfield.disp64 = 0;
b300c311 4314 }
40fb9820 4315 if (i.types[op].bitfield.disp32
91d6fa6a 4316 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4317 {
4318 /* If this operand is at most 32 bits, convert
4319 to a signed 32 bit number and don't use 64bit
4320 displacement. */
91d6fa6a
NC		 4321 op_disp &= (((offsetT) 2 << 31) - 1);
4322 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4323 i.types[op].bitfield.disp64 = 0;
b300c311 4324 }
91d6fa6a 4325 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4326 {
40fb9820
L		 4327 i.types[op].bitfield.disp8 = 0;
4328 i.types[op].bitfield.disp16 = 0;
4329 i.types[op].bitfield.disp32 = 0;
4330 i.types[op].bitfield.disp32s = 0;
4331 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4332 i.op[op].disps = 0;
4333 i.disp_operands--;
4334 }
4335 else if (flag_code == CODE_64BIT)
4336 {
91d6fa6a 4337 if (fits_in_signed_long (op_disp))
28a9d8f5 4338 {
40fb9820
L		 4339 i.types[op].bitfield.disp64 = 0;
4340 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4341 }
0e1147d9 4342 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4343 && fits_in_unsigned_long (op_disp))
40fb9820 4344 i.types[op].bitfield.disp32 = 1;
b300c311 4345 }
40fb9820
L		 4346 if ((i.types[op].bitfield.disp32
4347 || i.types[op].bitfield.disp32s
4348 || i.types[op].bitfield.disp16)
91d6fa6a 4349 && fits_in_signed_byte (op_disp))
40fb9820 4350 i.types[op].bitfield.disp8 = 1;
252b5132 4351 }
67a4f2b7
AO		 4352 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4353 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4354 {
4355 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4356 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4357 i.types[op].bitfield.disp8 = 0;
4358 i.types[op].bitfield.disp16 = 0;
4359 i.types[op].bitfield.disp32 = 0;
4360 i.types[op].bitfield.disp32s = 0;
4361 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4362 }
4363 else
b300c311 4364 /* We only support 64bit displacement on constants. */
40fb9820 4365 i.types[op].bitfield.disp64 = 0;
252b5132 4366 }
29b0f896
AM		 4367}
4368
6c30d220
L		 4369/* Check if operands are valid for the instruction. */
4370
4371static int
4372check_VecOperands (const insn_template *t)
4373{
43234a1e
L		 4374 unsigned int op;
4375
6c30d220
L		 4376 /* Without VSIB byte, we can't have a vector register for index. */
4377 if (!t->opcode_modifier.vecsib
4378 && i.index_reg
4379 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4380 || i.index_reg->reg_type.bitfield.regymm
4381 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4382 {
4383 i.error = unsupported_vector_index_register;
4384 return 1;
4385 }
4386
ad8ecc81
MZ		 4387 /* Check if default mask is allowed. */
4388 if (t->opcode_modifier.nodefmask
4389 && (!i.mask || i.mask->mask->reg_num == 0))
4390 {
4391 i.error = no_default_mask;
4392 return 1;
4393 }
4394
7bab8ab5
JB		 4395 /* For VSIB byte, we need a vector register for index, and all vector
4396 registers must be distinct. */
4397 if (t->opcode_modifier.vecsib)
4398 {
4399 if (!i.index_reg
6c30d220
L		 4400 || !((t->opcode_modifier.vecsib == VecSIB128
4401 && i.index_reg->reg_type.bitfield.regxmm)
4402 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4403 && i.index_reg->reg_type.bitfield.regymm)
4404 || (t->opcode_modifier.vecsib == VecSIB512
4405 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4406 {
4407 i.error = invalid_vsib_address;
4408 return 1;
4409 }
4410
43234a1e
L		 4411 gas_assert (i.reg_operands == 2 || i.mask);
4412 if (i.reg_operands == 2 && !i.mask)
4413 {
4414 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4415 || i.types[0].bitfield.regymm);
43234a1e 4416 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4417 || i.types[2].bitfield.regymm);
43234a1e
L		 4418 if (operand_check == check_none)
4419 return 0;
4420 if (register_number (i.op[0].regs)
4421 != register_number (i.index_reg)
4422 && register_number (i.op[2].regs)
4423 != register_number (i.index_reg)
4424 && register_number (i.op[0].regs)
4425 != register_number (i.op[2].regs))
4426 return 0;
4427 if (operand_check == check_error)
4428 {
4429 i.error = invalid_vector_register_set;
4430 return 1;
4431 }
4432 as_warn (_("mask, index, and destination registers should be distinct"));
4433 }
8444f82a
MZ		 4434 else if (i.reg_operands == 1 && i.mask)
4435 {
4436 if ((i.types[1].bitfield.regymm
4437 || i.types[1].bitfield.regzmm)
4438 && (register_number (i.op[1].regs)
4439 == register_number (i.index_reg)))
4440 {
4441 if (operand_check == check_error)
4442 {
4443 i.error = invalid_vector_register_set;
4444 return 1;
4445 }
4446 if (operand_check != check_none)
4447 as_warn (_("index and destination registers should be distinct"));
4448 }
4449 }
43234a1e 4450 }
7bab8ab5 4451
43234a1e
L		 4452 /* Check if broadcast is supported by the instruction and is applied
4453 to the memory operand. */
4454 if (i.broadcast)
4455 {
4456 int broadcasted_opnd_size;
4457
4458 /* Check if specified broadcast is supported in this instruction,
4459 and it's applied to memory operand of DWORD or QWORD type,
4460 depending on VecESize. */
4461 if (i.broadcast->type != t->opcode_modifier.broadcast
4462 || !i.types[i.broadcast->operand].bitfield.mem
4463 || (t->opcode_modifier.vecesize == 0
4464 && !i.types[i.broadcast->operand].bitfield.dword
4465 && !i.types[i.broadcast->operand].bitfield.unspecified)
4466 || (t->opcode_modifier.vecesize == 1
4467 && !i.types[i.broadcast->operand].bitfield.qword
4468 && !i.types[i.broadcast->operand].bitfield.unspecified))
4469 goto bad_broadcast;
4470
4471 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4472 if (i.broadcast->type == BROADCAST_1TO16)
4473 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4474 else if (i.broadcast->type == BROADCAST_1TO8)
4475 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4476 else if (i.broadcast->type == BROADCAST_1TO4)
4477 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4478 else if (i.broadcast->type == BROADCAST_1TO2)
4479 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4480 else
4481 goto bad_broadcast;
4482
4483 if ((broadcasted_opnd_size == 256
4484 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4485 || (broadcasted_opnd_size == 512
4486 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4487 {
4488 bad_broadcast:
4489 i.error = unsupported_broadcast;
4490 return 1;
4491 }
4492 }
4493 /* If broadcast is supported in this instruction, we need to check if
4494 operand of one-element size isn't specified without broadcast. */
4495 else if (t->opcode_modifier.broadcast && i.mem_operands)
4496 {
4497 /* Find memory operand. */
4498 for (op = 0; op < i.operands; op++)
4499 if (operand_type_check (i.types[op], anymem))
4500 break;
4501 gas_assert (op < i.operands);
4502 /* Check size of the memory operand. */
4503 if ((t->opcode_modifier.vecesize == 0
4504 && i.types[op].bitfield.dword)
4505 || (t->opcode_modifier.vecesize == 1
4506 && i.types[op].bitfield.qword))
4507 {
4508 i.error = broadcast_needed;
4509 return 1;
4510 }
4511 }
4512
4513 /* Check if requested masking is supported. */
4514 if (i.mask
4515 && (!t->opcode_modifier.masking
4516 || (i.mask->zeroing
4517 && t->opcode_modifier.masking == MERGING_MASKING)))
4518 {
4519 i.error = unsupported_masking;
4520 return 1;
4521 }
4522
4523 /* Check if masking is applied to dest operand. */
4524 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4525 {
4526 i.error = mask_not_on_destination;
4527 return 1;
4528 }
4529
43234a1e
L		 4530 /* Check RC/SAE. */
4531 if (i.rounding)
4532 {
4533 if ((i.rounding->type != saeonly
4534 && !t->opcode_modifier.staticrounding)
4535 || (i.rounding->type == saeonly
4536 && (t->opcode_modifier.staticrounding
4537 || !t->opcode_modifier.sae)))
4538 {
4539 i.error = unsupported_rc_sae;
4540 return 1;
4541 }
4542 /* If the instruction has several immediate operands and one of
4543 them is rounding, the rounding operand should be the last
4544 immediate operand. */
4545 if (i.imm_operands > 1
4546 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4547 {
43234a1e 4548 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4549 return 1;
4550 }
6c30d220
L		 4551 }
4552
43234a1e
L		 4553 /* Check vector Disp8 operand. */
4554 if (t->opcode_modifier.disp8memshift)
4555 {
4556 if (i.broadcast)
4557 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4558 else
4559 i.memshift = t->opcode_modifier.disp8memshift;
4560
4561 for (op = 0; op < i.operands; op++)
4562 if (operand_type_check (i.types[op], disp)
4563 && i.op[op].disps->X_op == O_constant)
4564 {
4565 offsetT value = i.op[op].disps->X_add_number;
4566 int vec_disp8_ok = fits_in_vec_disp8 (value);
4567 if (t->operand_types [op].bitfield.vec_disp8)
4568 {
4569 if (vec_disp8_ok)
4570 i.types[op].bitfield.vec_disp8 = 1;
4571 else
4572 {
4573 /* Vector insn can only have Vec_Disp8/Disp32 in
4574 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4575 mode. */
4576 i.types[op].bitfield.disp8 = 0;
4577 if (flag_code != CODE_16BIT)
4578 i.types[op].bitfield.disp16 = 0;
4579 }
4580 }
4581 else if (flag_code != CODE_16BIT)
4582 {
4583 /* One form of this instruction supports vector Disp8.
4584 Try vector Disp8 if we need to use Disp32. */
4585 if (vec_disp8_ok && !fits_in_signed_byte (value))
4586 {
4587 i.error = try_vector_disp8;
4588 return 1;
4589 }
4590 }
4591 }
4592 }
4593 else
4594 i.memshift = -1;
4595
6c30d220
L		 4596 return 0;
4597}
4598
43f3e2ee 4599/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4600 operand types. */
4601
4602static int
4603VEX_check_operands (const insn_template *t)
4604{
43234a1e
L		 4605 /* VREX is only valid with EVEX prefix. */
4606 if (i.need_vrex && !t->opcode_modifier.evex)
4607 {
4608 i.error = invalid_register_operand;
4609 return 1;
4610 }
4611
a683cc34
SP		 4612 if (!t->opcode_modifier.vex)
4613 return 0;
4614
4615 /* Only check VEX_Imm4, which must be the first operand. */
4616 if (t->operand_types[0].bitfield.vec_imm4)
4617 {
4618 if (i.op[0].imms->X_op != O_constant
4619 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4620 {
a65babc9 4621 i.error = bad_imm4;
891edac4
L		 4622 return 1;
4623 }
a683cc34
SP		 4624
4625 /* Turn off Imm8 so that update_imm won't complain. */
4626 i.types[0] = vec_imm4;
4627 }
4628
4629 return 0;
4630}
4631
d3ce72d0 4632static const insn_template *
e3bb37b5 4633match_template (void)
29b0f896
AM		 4634{
4635 /* Points to template once we've found it. */
d3ce72d0 4636 const insn_template *t;
40fb9820 4637 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4638 i386_operand_type overlap4;
29b0f896 4639 unsigned int found_reverse_match;
40fb9820
L		 4640 i386_opcode_modifier suffix_check;
4641 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4642 int addr_prefix_disp;
a5c311ca 4643 unsigned int j;
3629bb00 4644 unsigned int found_cpu_match;
45664ddb 4645 unsigned int check_register;
5614d22c 4646 enum i386_error specific_error = 0;
29b0f896 4647
c0f3af97
L		 4648#if MAX_OPERANDS != 5
4649# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4650#endif
4651
29b0f896 4652 found_reverse_match = 0;
539e75ad 4653 addr_prefix_disp = -1;
40fb9820
L		 4654
4655 memset (&suffix_check, 0, sizeof (suffix_check));
4656 if (i.suffix == BYTE_MNEM_SUFFIX)
4657 suffix_check.no_bsuf = 1;
4658 else if (i.suffix == WORD_MNEM_SUFFIX)
4659 suffix_check.no_wsuf = 1;
4660 else if (i.suffix == SHORT_MNEM_SUFFIX)
4661 suffix_check.no_ssuf = 1;
4662 else if (i.suffix == LONG_MNEM_SUFFIX)
4663 suffix_check.no_lsuf = 1;
4664 else if (i.suffix == QWORD_MNEM_SUFFIX)
4665 suffix_check.no_qsuf = 1;
4666 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4667 suffix_check.no_ldsuf = 1;
29b0f896 4668
01559ecc
L		 4669 /* Must have right number of operands. */
4670 i.error = number_of_operands_mismatch;
4671
45aa61fe 4672 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4673 {
539e75ad
L		 4674 addr_prefix_disp = -1;
4675
29b0f896
AM		 4676 if (i.operands != t->operands)
4677 continue;
4678
50aecf8c 4679 /* Check processor support. */
a65babc9 4680 i.error = unsupported;
c0f3af97
L		 4681 found_cpu_match = (cpu_flags_match (t)
4682 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4683 if (!found_cpu_match)
4684 continue;
4685
e1d4d893 4686 /* Check old gcc support. */
a65babc9 4687 i.error = old_gcc_only;
e1d4d893
L		 4688 if (!old_gcc && t->opcode_modifier.oldgcc)
4689 continue;
4690
4691 /* Check AT&T mnemonic. */
a65babc9 4692 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4693 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4694 continue;
4695
891edac4 4696 /* Check AT&T/Intel syntax. */
a65babc9 4697 i.error = unsupported_syntax;
5c07affc
L		 4698 if ((intel_syntax && t->opcode_modifier.attsyntax)
4699 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4700 continue;
4701
20592a94 4702 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4703 i.error = invalid_instruction_suffix;
567e4e96
L		 4704 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4705 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4706 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4707 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4708 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4709 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4710 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4711 continue;
4712
5c07affc 4713 if (!operand_size_match (t))
7d5e4556 4714 continue;
539e75ad 4715
5c07affc
L		 4716 for (j = 0; j < MAX_OPERANDS; j++)
4717 operand_types[j] = t->operand_types[j];
4718
45aa61fe
AM		 4719 /* In general, don't allow 64-bit operands in 32-bit mode. */
4720 if (i.suffix == QWORD_MNEM_SUFFIX
4721 && flag_code != CODE_64BIT
4722 && (intel_syntax
40fb9820 4723 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4724 && !intel_float_operand (t->name))
4725 : intel_float_operand (t->name) != 2)
40fb9820 4726 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4727 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4728 && !operand_types[0].bitfield.regymm
4729 && !operand_types[0].bitfield.regzmm)
40fb9820 4730 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4731 && operand_types[t->operands > 1].bitfield.regxmm
4732 && operand_types[t->operands > 1].bitfield.regymm
4733 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4734 && (t->base_opcode != 0x0fc7
4735 || t->extension_opcode != 1 /* cmpxchg8b */))
4736 continue;
4737
192dc9c6
JB		 4738 /* In general, don't allow 32-bit operands on pre-386. */
4739 else if (i.suffix == LONG_MNEM_SUFFIX
4740 && !cpu_arch_flags.bitfield.cpui386
4741 && (intel_syntax
4742 ? (!t->opcode_modifier.ignoresize
4743 && !intel_float_operand (t->name))
4744 : intel_float_operand (t->name) != 2)
4745 && ((!operand_types[0].bitfield.regmmx
4746 && !operand_types[0].bitfield.regxmm)
4747 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4748 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4749 continue;
4750
29b0f896 4751 /* Do not verify operands when there are none. */
50aecf8c 4752 else
29b0f896 4753 {
c6fb90c8 4754 if (!t->operands)
2dbab7d5
L		 4755 /* We've found a match; break out of loop. */
4756 break;
29b0f896 4757 }
252b5132 4758
539e75ad
L		 4759 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4760 into Disp32/Disp16/Disp32 operand. */
4761 if (i.prefix[ADDR_PREFIX] != 0)
4762 {
40fb9820 4763 /* There should be only one Disp operand. */
539e75ad
L		 4764 switch (flag_code)
4765 {
4766 case CODE_16BIT:
40fb9820
L		 4767 for (j = 0; j < MAX_OPERANDS; j++)
4768 {
4769 if (operand_types[j].bitfield.disp16)
4770 {
4771 addr_prefix_disp = j;
4772 operand_types[j].bitfield.disp32 = 1;
4773 operand_types[j].bitfield.disp16 = 0;
4774 break;
4775 }
4776 }
539e75ad
L		 4777 break;
4778 case CODE_32BIT:
40fb9820
L		 4779 for (j = 0; j < MAX_OPERANDS; j++)
4780 {
4781 if (operand_types[j].bitfield.disp32)
4782 {
4783 addr_prefix_disp = j;
4784 operand_types[j].bitfield.disp32 = 0;
4785 operand_types[j].bitfield.disp16 = 1;
4786 break;
4787 }
4788 }
539e75ad
L		 4789 break;
4790 case CODE_64BIT:
40fb9820
L		 4791 for (j = 0; j < MAX_OPERANDS; j++)
4792 {
4793 if (operand_types[j].bitfield.disp64)
4794 {
4795 addr_prefix_disp = j;
4796 operand_types[j].bitfield.disp64 = 0;
4797 operand_types[j].bitfield.disp32 = 1;
4798 break;
4799 }
4800 }
539e75ad
L		 4801 break;
4802 }
539e75ad
L		 4803 }
4804
56ffb741
L		 4805 /* We check register size if needed. */
4806 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4807 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4808 switch (t->operands)
4809 {
4810 case 1:
40fb9820 4811 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4812 continue;
4813 break;
4814 case 2:
8b38ad71
L		 4815 /* xchg %eax, %eax is a special case. It is an aliase for nop
4816 only in 32bit mode and we can use opcode 0x90. In 64bit
4817 mode, we can't use 0x90 for xchg %eax, %eax since it should
4818 zero-extend %eax to %rax. */
4819 if (flag_code == CODE_64BIT
4820 && t->base_opcode == 0x90
0dfbf9d7
L		 4821 && operand_type_equal (&i.types [0], &acc32)
4822 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4823 continue;
b6169b20
L		 4824 if (i.swap_operand)
4825 {
4826 /* If we swap operand in encoding, we either match
4827 the next one or reverse direction of operands. */
4828 if (t->opcode_modifier.s)
4829 continue;
4830 else if (t->opcode_modifier.d)
4831 goto check_reverse;
4832 }
4833
29b0f896 4834 case 3:
fa99fab2
L		 4835 /* If we swap operand in encoding, we match the next one. */
4836 if (i.swap_operand && t->opcode_modifier.s)
4837 continue;
f48ff2ae 4838 case 4:
c0f3af97 4839 case 5:
c6fb90c8 4840 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4841 if (!operand_type_match (overlap0, i.types[0])
4842 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4843 || (check_register
4844 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4845 operand_types[0],
4846 overlap1, i.types[1],
4847 operand_types[1])))
29b0f896
AM		 4848 {
4849 /* Check if other direction is valid ... */
40fb9820 4850 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4851 continue;
4852
b6169b20 4853check_reverse:
29b0f896 4854 /* Try reversing direction of operands. */
c6fb90c8
L		 4855 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4856 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4857 if (!operand_type_match (overlap0, i.types[0])
4858 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4859 || (check_register
4860 && !operand_type_register_match (overlap0,
4861 i.types[0],
4862 operand_types[1],
4863 overlap1,
4864 i.types[1],
4865 operand_types[0])))
29b0f896
AM		 4866 {
4867 /* Does not match either direction. */
4868 continue;
4869 }
4870 /* found_reverse_match holds which of D or FloatDR
4871 we've found. */
40fb9820 4872 if (t->opcode_modifier.d)
8a2ed489 4873 found_reverse_match = Opcode_D;
40fb9820 4874 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4875 found_reverse_match = Opcode_FloatD;
4876 else
4877 found_reverse_match = 0;
40fb9820 4878 if (t->opcode_modifier.floatr)
8a2ed489 4879 found_reverse_match |= Opcode_FloatR;
29b0f896 4880 }
f48ff2ae 4881 else
29b0f896 4882 {
f48ff2ae 4883 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4884 switch (t->operands)
4885 {
c0f3af97
L		 4886 case 5:
4887 overlap4 = operand_type_and (i.types[4],
4888 operand_types[4]);
d1cbb4db 4889 case 4:
c6fb90c8
L		 4890 overlap3 = operand_type_and (i.types[3],
4891 operand_types[3]);
d1cbb4db 4892 case 3:
c6fb90c8
L		 4893 overlap2 = operand_type_and (i.types[2],
4894 operand_types[2]);
d1cbb4db
L		 4895 break;
4896 }
29b0f896 4897
f48ff2ae
L		 4898 switch (t->operands)
4899 {
c0f3af97
L		 4900 case 5:
4901 if (!operand_type_match (overlap4, i.types[4])
4902 || !operand_type_register_match (overlap3,
4903 i.types[3],
4904 operand_types[3],
4905 overlap4,
4906 i.types[4],
4907 operand_types[4]))
4908 continue;
f48ff2ae 4909 case 4:
40fb9820 4910 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4911 || (check_register
4912 && !operand_type_register_match (overlap2,
4913 i.types[2],
4914 operand_types[2],
4915 overlap3,
4916 i.types[3],
4917 operand_types[3])))
f48ff2ae
L		 4918 continue;
4919 case 3:
4920 /* Here we make use of the fact that there are no
4921 reverse match 3 operand instructions, and all 3
4922 operand instructions only need to be checked for
4923 register consistency between operands 2 and 3. */
40fb9820 4924 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4925 || (check_register
4926 && !operand_type_register_match (overlap1,
4927 i.types[1],
4928 operand_types[1],
4929 overlap2,
4930 i.types[2],
4931 operand_types[2])))
f48ff2ae
L		 4932 continue;
4933 break;
4934 }
29b0f896 4935 }
f48ff2ae 4936 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4937 slip through to break. */
4938 }
3629bb00 4939 if (!found_cpu_match)
29b0f896
AM		 4940 {
4941 found_reverse_match = 0;
4942 continue;
4943 }
c0f3af97 4944
5614d22c
JB		 4945 /* Check if vector and VEX operands are valid. */
4946 if (check_VecOperands (t) || VEX_check_operands (t))
4947 {
4948 specific_error = i.error;
4949 continue;
4950 }
a683cc34 4951
29b0f896
AM		 4952 /* We've found a match; break out of loop. */
4953 break;
4954 }
4955
4956 if (t == current_templates->end)
4957 {
4958 /* We found no match. */
a65babc9 4959 const char *err_msg;
5614d22c 4960 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4961 {
4962 default:
4963 abort ();
86e026a4 4964 case operand_size_mismatch:
a65babc9
L		 4965 err_msg = _("operand size mismatch");
4966 break;
4967 case operand_type_mismatch:
4968 err_msg = _("operand type mismatch");
4969 break;
4970 case register_type_mismatch:
4971 err_msg = _("register type mismatch");
4972 break;
4973 case number_of_operands_mismatch:
4974 err_msg = _("number of operands mismatch");
4975 break;
4976 case invalid_instruction_suffix:
4977 err_msg = _("invalid instruction suffix");
4978 break;
4979 case bad_imm4:
4a2608e3 4980 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4981 break;
4982 case old_gcc_only:
4983 err_msg = _("only supported with old gcc");
4984 break;
4985 case unsupported_with_intel_mnemonic:
4986 err_msg = _("unsupported with Intel mnemonic");
4987 break;
4988 case unsupported_syntax:
4989 err_msg = _("unsupported syntax");
4990 break;
4991 case unsupported:
35262a23 4992 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4993 current_templates->start->name);
4994 return NULL;
6c30d220
L		 4995 case invalid_vsib_address:
4996 err_msg = _("invalid VSIB address");
4997 break;
7bab8ab5
JB		 4998 case invalid_vector_register_set:
4999 err_msg = _("mask, index, and destination registers must be distinct");
5000 break;
6c30d220
L		 5001 case unsupported_vector_index_register:
5002 err_msg = _("unsupported vector index register");
5003 break;
43234a1e
L		 5004 case unsupported_broadcast:
5005 err_msg = _("unsupported broadcast");
5006 break;
5007 case broadcast_not_on_src_operand:
5008 err_msg = _("broadcast not on source memory operand");
5009 break;
5010 case broadcast_needed:
5011 err_msg = _("broadcast is needed for operand of such type");
5012 break;
5013 case unsupported_masking:
5014 err_msg = _("unsupported masking");
5015 break;
5016 case mask_not_on_destination:
5017 err_msg = _("mask not on destination operand");
5018 break;
5019 case no_default_mask:
5020 err_msg = _("default mask isn't allowed");
5021 break;
5022 case unsupported_rc_sae:
5023 err_msg = _("unsupported static rounding/sae");
5024 break;
5025 case rc_sae_operand_not_last_imm:
5026 if (intel_syntax)
5027 err_msg = _("RC/SAE operand must precede immediate operands");
5028 else
5029 err_msg = _("RC/SAE operand must follow immediate operands");
5030 break;
5031 case invalid_register_operand:
5032 err_msg = _("invalid register operand");
5033 break;
a65babc9
L		 5034 }
5035 as_bad (_("%s for `%s'"), err_msg,
891edac4 5036 current_templates->start->name);
fa99fab2 5037 return NULL;
29b0f896 5038 }
252b5132 5039
29b0f896
AM		 5040 if (!quiet_warnings)
5041 {
5042 if (!intel_syntax
40fb9820
L		 5043 && (i.types[0].bitfield.jumpabsolute
5044 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5045 {
5046 as_warn (_("indirect %s without `*'"), t->name);
5047 }
5048
40fb9820
L		 5049 if (t->opcode_modifier.isprefix
5050 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5051 {
5052 /* Warn them that a data or address size prefix doesn't
5053 affect assembly of the next line of code. */
5054 as_warn (_("stand-alone `%s' prefix"), t->name);
5055 }
5056 }
5057
5058 /* Copy the template we found. */
5059 i.tm = *t;
539e75ad
L		 5060
5061 if (addr_prefix_disp != -1)
5062 i.tm.operand_types[addr_prefix_disp]
5063 = operand_types[addr_prefix_disp];
5064
29b0f896
AM		 5065 if (found_reverse_match)
5066 {
5067 /* If we found a reverse match we must alter the opcode
5068 direction bit. found_reverse_match holds bits to change
5069 (different for int & float insns). */
5070
5071 i.tm.base_opcode ^= found_reverse_match;
5072
539e75ad
L		 5073 i.tm.operand_types[0] = operand_types[1];
5074 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5075 }
5076
fa99fab2 5077 return t;
29b0f896
AM		 5078}
5079
5080static int
e3bb37b5 5081check_string (void)
29b0f896 5082{
40fb9820
L		 5083 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5084 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5085 {
5086 if (i.seg[0] != NULL && i.seg[0] != &es)
5087 {
a87af027 5088 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5089 i.tm.name,
a87af027
JB		 5090 mem_op + 1,
5091 register_prefix);
29b0f896
AM		 5092 return 0;
5093 }
5094 /* There's only ever one segment override allowed per instruction.
5095 This instruction possibly has a legal segment override on the
5096 second operand, so copy the segment to where non-string
5097 instructions store it, allowing common code. */
5098 i.seg[0] = i.seg[1];
5099 }
40fb9820 5100 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5101 {
5102 if (i.seg[1] != NULL && i.seg[1] != &es)
5103 {
a87af027 5104 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5105 i.tm.name,
a87af027
JB		 5106 mem_op + 2,
5107 register_prefix);
29b0f896
AM		 5108 return 0;
5109 }
5110 }
5111 return 1;
5112}
5113
5114static int
543613e9 5115process_suffix (void)
29b0f896
AM		 5116{
5117 /* If matched instruction specifies an explicit instruction mnemonic
5118 suffix, use it. */
40fb9820
L		 5119 if (i.tm.opcode_modifier.size16)
5120 i.suffix = WORD_MNEM_SUFFIX;
5121 else if (i.tm.opcode_modifier.size32)
5122 i.suffix = LONG_MNEM_SUFFIX;
5123 else if (i.tm.opcode_modifier.size64)
5124 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5125 else if (i.reg_operands)
5126 {
5127 /* If there's no instruction mnemonic suffix we try to invent one
5128 based on register operands. */
5129 if (!i.suffix)
5130 {
5131 /* We take i.suffix from the last register operand specified,
5132 Destination register type is more significant than source
381d071f
L		 5133 register type. crc32 in SSE4.2 prefers source register
5134 type. */
5135 if (i.tm.base_opcode == 0xf20f38f1)
5136 {
40fb9820
L		 5137 if (i.types[0].bitfield.reg16)
5138 i.suffix = WORD_MNEM_SUFFIX;
5139 else if (i.types[0].bitfield.reg32)
5140 i.suffix = LONG_MNEM_SUFFIX;
5141 else if (i.types[0].bitfield.reg64)
5142 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5143 }
9344ff29 5144 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5145 {
40fb9820 5146 if (i.types[0].bitfield.reg8)
20592a94
L		 5147 i.suffix = BYTE_MNEM_SUFFIX;
5148 }
381d071f
L		 5149
5150 if (!i.suffix)
5151 {
5152 int op;
5153
20592a94
L		 5154 if (i.tm.base_opcode == 0xf20f38f1
5155 || i.tm.base_opcode == 0xf20f38f0)
5156 {
5157 /* We have to know the operand size for crc32. */
5158 as_bad (_("ambiguous memory operand size for `%s`"),
5159 i.tm.name);
5160 return 0;
5161 }
5162
381d071f 5163 for (op = i.operands; --op >= 0;)
40fb9820 5164 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5165 {
40fb9820
L		 5166 if (i.types[op].bitfield.reg8)
5167 {
5168 i.suffix = BYTE_MNEM_SUFFIX;
5169 break;
5170 }
5171 else if (i.types[op].bitfield.reg16)
5172 {
5173 i.suffix = WORD_MNEM_SUFFIX;
5174 break;
5175 }
5176 else if (i.types[op].bitfield.reg32)
5177 {
5178 i.suffix = LONG_MNEM_SUFFIX;
5179 break;
5180 }
5181 else if (i.types[op].bitfield.reg64)
5182 {
5183 i.suffix = QWORD_MNEM_SUFFIX;
5184 break;
5185 }
381d071f
L		 5186 }
5187 }
29b0f896
AM		 5188 }
5189 else if (i.suffix == BYTE_MNEM_SUFFIX)
5190 {
2eb952a4
L		 5191 if (intel_syntax
5192 && i.tm.opcode_modifier.ignoresize
5193 && i.tm.opcode_modifier.no_bsuf)
5194 i.suffix = 0;
5195 else if (!check_byte_reg ())
29b0f896
AM		 5196 return 0;
5197 }
5198 else if (i.suffix == LONG_MNEM_SUFFIX)
5199 {
2eb952a4
L		 5200 if (intel_syntax
5201 && i.tm.opcode_modifier.ignoresize
5202 && i.tm.opcode_modifier.no_lsuf)
5203 i.suffix = 0;
5204 else if (!check_long_reg ())
29b0f896
AM		 5205 return 0;
5206 }
5207 else if (i.suffix == QWORD_MNEM_SUFFIX)
5208 {
955e1e6a
L		 5209 if (intel_syntax
5210 && i.tm.opcode_modifier.ignoresize
5211 && i.tm.opcode_modifier.no_qsuf)
5212 i.suffix = 0;
5213 else if (!check_qword_reg ())
29b0f896
AM		 5214 return 0;
5215 }
5216 else if (i.suffix == WORD_MNEM_SUFFIX)
5217 {
2eb952a4
L		 5218 if (intel_syntax
5219 && i.tm.opcode_modifier.ignoresize
5220 && i.tm.opcode_modifier.no_wsuf)
5221 i.suffix = 0;
5222 else if (!check_word_reg ())
29b0f896
AM		 5223 return 0;
5224 }
c0f3af97 5225 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5226 || i.suffix == YMMWORD_MNEM_SUFFIX
5227 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5228 {
43234a1e 5229 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5230 should check if it is a valid suffix. */
5231 }
40fb9820 5232 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5233 /* Do nothing if the instruction is going to ignore the prefix. */
5234 ;
5235 else
5236 abort ();
5237 }
40fb9820 5238 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5239 && !i.suffix
5240 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5241 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5242 {
5243 i.suffix = stackop_size;
5244 }
9306ca4a
JB		 5245 else if (intel_syntax
5246 && !i.suffix
40fb9820
L		 5247 && (i.tm.operand_types[0].bitfield.jumpabsolute
5248 || i.tm.opcode_modifier.jumpbyte
5249 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5250 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5251 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5252 {
5253 switch (flag_code)
5254 {
5255 case CODE_64BIT:
40fb9820 5256 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5257 {
5258 i.suffix = QWORD_MNEM_SUFFIX;
5259 break;
5260 }
5261 case CODE_32BIT:
40fb9820 5262 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5263 i.suffix = LONG_MNEM_SUFFIX;
5264 break;
5265 case CODE_16BIT:
40fb9820 5266 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5267 i.suffix = WORD_MNEM_SUFFIX;
5268 break;
5269 }
5270 }
252b5132 5271
9306ca4a 5272 if (!i.suffix)
29b0f896 5273 {
9306ca4a
JB		 5274 if (!intel_syntax)
5275 {
40fb9820 5276 if (i.tm.opcode_modifier.w)
9306ca4a 5277 {
4eed87de
AM		 5278 as_bad (_("no instruction mnemonic suffix given and "
5279 "no register operands; can't size instruction"));
9306ca4a
JB		 5280 return 0;
5281 }
5282 }
5283 else
5284 {
40fb9820 5285 unsigned int suffixes;
7ab9ffdd 5286
40fb9820
L		 5287 suffixes = !i.tm.opcode_modifier.no_bsuf;
5288 if (!i.tm.opcode_modifier.no_wsuf)
5289 suffixes |= 1 << 1;
5290 if (!i.tm.opcode_modifier.no_lsuf)
5291 suffixes |= 1 << 2;
fc4adea1 5292 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5293 suffixes |= 1 << 3;
5294 if (!i.tm.opcode_modifier.no_ssuf)
5295 suffixes |= 1 << 4;
5296 if (!i.tm.opcode_modifier.no_qsuf)
5297 suffixes |= 1 << 5;
5298
5299 /* There are more than suffix matches. */
5300 if (i.tm.opcode_modifier.w
9306ca4a 5301 || ((suffixes & (suffixes - 1))
40fb9820
L		 5302 && !i.tm.opcode_modifier.defaultsize
5303 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5304 {
5305 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5306 return 0;
5307 }
5308 }
29b0f896 5309 }
252b5132 5310
9306ca4a
JB		 5311 /* Change the opcode based on the operand size given by i.suffix;
5312 We don't need to change things for byte insns. */
5313
582d5edd
L		 5314 if (i.suffix
5315 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5316 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5317 && i.suffix != YMMWORD_MNEM_SUFFIX
5318 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5319 {
5320 /* It's not a byte, select word/dword operation. */
40fb9820 5321 if (i.tm.opcode_modifier.w)
29b0f896 5322 {
40fb9820 5323 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5324 i.tm.base_opcode |= 8;
5325 else
5326 i.tm.base_opcode |= 1;
5327 }
0f3f3d8b 5328
29b0f896
AM		 5329 /* Now select between word & dword operations via the operand
5330 size prefix, except for instructions that will ignore this
5331 prefix anyway. */
ca61edf2 5332 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5333 {
ca61edf2
L		 5334 /* The address size override prefix changes the size of the
5335 first operand. */
40fb9820
L		 5336 if ((flag_code == CODE_32BIT
5337 && i.op->regs[0].reg_type.bitfield.reg16)
5338 || (flag_code != CODE_32BIT
5339 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5340 if (!add_prefix (ADDR_PREFIX_OPCODE))
5341 return 0;
5342 }
5343 else if (i.suffix != QWORD_MNEM_SUFFIX
5344 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5345 && !i.tm.opcode_modifier.ignoresize
5346 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5347 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5348 || (flag_code == CODE_64BIT
40fb9820 5349 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5350 {
5351 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5352
40fb9820 5353 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5354 prefix = ADDR_PREFIX_OPCODE;
252b5132 5355
29b0f896
AM		 5356 if (!add_prefix (prefix))
5357 return 0;
24eab124 5358 }
252b5132 5359
29b0f896
AM		 5360 /* Set mode64 for an operand. */
5361 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5362 && flag_code == CODE_64BIT
40fb9820 5363 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5364 {
5365 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5366 need rex64. cmpxchg8b is also a special case. */
5367 if (! (i.operands == 2
5368 && i.tm.base_opcode == 0x90
5369 && i.tm.extension_opcode == None
0dfbf9d7
L		 5370 && operand_type_equal (&i.types [0], &acc64)
5371 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5372 && ! (i.operands == 1
5373 && i.tm.base_opcode == 0xfc7
5374 && i.tm.extension_opcode == 1
40fb9820
L		 5375 && !operand_type_check (i.types [0], reg)
5376 && operand_type_check (i.types [0], anymem)))
f6bee062 5377 i.rex |= REX_W;
46e883c5 5378 }
3e73aa7c 5379
29b0f896
AM		 5380 /* Size floating point instruction. */
5381 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5382 if (i.tm.opcode_modifier.floatmf)
543613e9 5383 i.tm.base_opcode ^= 4;
29b0f896 5384 }
7ecd2f8b 5385
29b0f896
AM		 5386 return 1;
5387}
3e73aa7c 5388
29b0f896 5389static int
543613e9 5390check_byte_reg (void)
29b0f896
AM		 5391{
5392 int op;
543613e9 5393
29b0f896
AM		 5394 for (op = i.operands; --op >= 0;)
5395 {
5396 /* If this is an eight bit register, it's OK. If it's the 16 or
5397 32 bit version of an eight bit register, we will just use the
5398 low portion, and that's OK too. */
40fb9820 5399 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5400 continue;
5401
5a819eb9
JB		 5402 /* I/O port address operands are OK too. */
5403 if (i.tm.operand_types[op].bitfield.inoutportreg)
5404 continue;
5405
9344ff29
L		 5406 /* crc32 doesn't generate this warning. */
5407 if (i.tm.base_opcode == 0xf20f38f0)
5408 continue;
5409
40fb9820
L		 5410 if ((i.types[op].bitfield.reg16
5411 || i.types[op].bitfield.reg32
5412 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5413 && i.op[op].regs->reg_num < 4
5414 /* Prohibit these changes in 64bit mode, since the lowering
5415 would be more complicated. */
5416 && flag_code != CODE_64BIT)
29b0f896 5417 {
29b0f896 5418#if REGISTER_WARNINGS
5a819eb9 5419 if (!quiet_warnings)
a540244d
L		 5420 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5421 register_prefix,
40fb9820 5422 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5423 ? REGNAM_AL - REGNAM_AX
5424 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5425 register_prefix,
29b0f896
AM		 5426 i.op[op].regs->reg_name,
5427 i.suffix);
5428#endif
5429 continue;
5430 }
5431 /* Any other register is bad. */
40fb9820
L		 5432 if (i.types[op].bitfield.reg16
5433 || i.types[op].bitfield.reg32
5434 || i.types[op].bitfield.reg64
5435 || i.types[op].bitfield.regmmx
5436 || i.types[op].bitfield.regxmm
c0f3af97 5437 || i.types[op].bitfield.regymm
43234a1e 5438 || i.types[op].bitfield.regzmm
40fb9820
L		 5439 || i.types[op].bitfield.sreg2
5440 || i.types[op].bitfield.sreg3
5441 || i.types[op].bitfield.control
5442 || i.types[op].bitfield.debug
5443 || i.types[op].bitfield.test
5444 || i.types[op].bitfield.floatreg
5445 || i.types[op].bitfield.floatacc)
29b0f896 5446 {
a540244d
L		 5447 as_bad (_("`%s%s' not allowed with `%s%c'"),
5448 register_prefix,
29b0f896
AM		 5449 i.op[op].regs->reg_name,
5450 i.tm.name,
5451 i.suffix);
5452 return 0;
5453 }
5454 }
5455 return 1;
5456}
5457
5458static int
e3bb37b5 5459check_long_reg (void)
29b0f896
AM		 5460{
5461 int op;
5462
5463 for (op = i.operands; --op >= 0;)
5464 /* Reject eight bit registers, except where the template requires
5465 them. (eg. movzb) */
40fb9820
L		 5466 if (i.types[op].bitfield.reg8
5467 && (i.tm.operand_types[op].bitfield.reg16
5468 || i.tm.operand_types[op].bitfield.reg32
5469 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5470 {
a540244d
L		 5471 as_bad (_("`%s%s' not allowed with `%s%c'"),
5472 register_prefix,
29b0f896
AM		 5473 i.op[op].regs->reg_name,
5474 i.tm.name,
5475 i.suffix);
5476 return 0;
5477 }
e4630f71 5478 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5479 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5480 && i.types[op].bitfield.reg16
5481 && (i.tm.operand_types[op].bitfield.reg32
5482 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5483 {
5484 /* Prohibit these changes in the 64bit mode, since the
5485 lowering is more complicated. */
5486 if (flag_code == CODE_64BIT)
252b5132 5487 {
2b5d6a91 5488 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5489 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5490 i.suffix);
5491 return 0;
252b5132 5492 }
29b0f896 5493#if REGISTER_WARNINGS
cecf1424
JB		 5494 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5495 register_prefix,
5496 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5497 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5498#endif
252b5132 5499 }
e4630f71 5500 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5501 else if (i.types[op].bitfield.reg64
5502 && (i.tm.operand_types[op].bitfield.reg32
5503 || i.tm.operand_types[op].bitfield.acc))
252b5132 5504 {
34828aad 5505 if (intel_syntax
ca61edf2 5506 && i.tm.opcode_modifier.toqword
40fb9820 5507 && !i.types[0].bitfield.regxmm)
34828aad 5508 {
ca61edf2 5509 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5510 i.suffix = QWORD_MNEM_SUFFIX;
5511 }
5512 else
5513 {
2b5d6a91 5514 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5515 register_prefix, i.op[op].regs->reg_name,
5516 i.suffix);
5517 return 0;
5518 }
29b0f896
AM		 5519 }
5520 return 1;
5521}
252b5132 5522
29b0f896 5523static int
e3bb37b5 5524check_qword_reg (void)
29b0f896
AM		 5525{
5526 int op;
252b5132 5527
29b0f896
AM		 5528 for (op = i.operands; --op >= 0; )
5529 /* Reject eight bit registers, except where the template requires
5530 them. (eg. movzb) */
40fb9820
L		 5531 if (i.types[op].bitfield.reg8
5532 && (i.tm.operand_types[op].bitfield.reg16
5533 || i.tm.operand_types[op].bitfield.reg32
5534 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5535 {
a540244d
L		 5536 as_bad (_("`%s%s' not allowed with `%s%c'"),
5537 register_prefix,
29b0f896
AM		 5538 i.op[op].regs->reg_name,
5539 i.tm.name,
5540 i.suffix);
5541 return 0;
5542 }
e4630f71 5543 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5544 else if ((i.types[op].bitfield.reg16
5545 || i.types[op].bitfield.reg32)
5546 && (i.tm.operand_types[op].bitfield.reg32
5547 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5548 {
5549 /* Prohibit these changes in the 64bit mode, since the
5550 lowering is more complicated. */
34828aad 5551 if (intel_syntax
ca61edf2 5552 && i.tm.opcode_modifier.todword
40fb9820 5553 && !i.types[0].bitfield.regxmm)
34828aad 5554 {
ca61edf2 5555 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5556 i.suffix = LONG_MNEM_SUFFIX;
5557 }
5558 else
5559 {
2b5d6a91 5560 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5561 register_prefix, i.op[op].regs->reg_name,
5562 i.suffix);
5563 return 0;
5564 }
252b5132 5565 }
29b0f896
AM		 5566 return 1;
5567}
252b5132 5568
29b0f896 5569static int
e3bb37b5 5570check_word_reg (void)
29b0f896
AM		 5571{
5572 int op;
5573 for (op = i.operands; --op >= 0;)
5574 /* Reject eight bit registers, except where the template requires
5575 them. (eg. movzb) */
40fb9820
L		 5576 if (i.types[op].bitfield.reg8
5577 && (i.tm.operand_types[op].bitfield.reg16
5578 || i.tm.operand_types[op].bitfield.reg32
5579 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5580 {
a540244d
L		 5581 as_bad (_("`%s%s' not allowed with `%s%c'"),
5582 register_prefix,
29b0f896
AM		 5583 i.op[op].regs->reg_name,
5584 i.tm.name,
5585 i.suffix);
5586 return 0;
5587 }
e4630f71 5588 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5589 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5590 && (i.types[op].bitfield.reg32
5591 || i.types[op].bitfield.reg64)
40fb9820
L		 5592 && (i.tm.operand_types[op].bitfield.reg16
5593 || i.tm.operand_types[op].bitfield.acc))
252b5132 5594 {
29b0f896
AM		 5595 /* Prohibit these changes in the 64bit mode, since the
5596 lowering is more complicated. */
5597 if (flag_code == CODE_64BIT)
252b5132 5598 {
2b5d6a91 5599 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5600 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5601 i.suffix);
5602 return 0;
252b5132 5603 }
29b0f896 5604#if REGISTER_WARNINGS
cecf1424
JB		 5605 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5606 register_prefix,
5607 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5608 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5609#endif
5610 }
5611 return 1;
5612}
252b5132 5613
29b0f896 5614static int
40fb9820 5615update_imm (unsigned int j)
29b0f896 5616{
bc0844ae 5617 i386_operand_type overlap = i.types[j];
40fb9820
L		 5618 if ((overlap.bitfield.imm8
5619 || overlap.bitfield.imm8s
5620 || overlap.bitfield.imm16
5621 || overlap.bitfield.imm32
5622 || overlap.bitfield.imm32s
5623 || overlap.bitfield.imm64)
0dfbf9d7
L		 5624 && !operand_type_equal (&overlap, &imm8)
5625 && !operand_type_equal (&overlap, &imm8s)
5626 && !operand_type_equal (&overlap, &imm16)
5627 && !operand_type_equal (&overlap, &imm32)
5628 && !operand_type_equal (&overlap, &imm32s)
5629 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5630 {
5631 if (i.suffix)
5632 {
40fb9820
L		 5633 i386_operand_type temp;
5634
0dfbf9d7 5635 operand_type_set (&temp, 0);
7ab9ffdd 5636 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5637 {
5638 temp.bitfield.imm8 = overlap.bitfield.imm8;
5639 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5640 }
5641 else if (i.suffix == WORD_MNEM_SUFFIX)
5642 temp.bitfield.imm16 = overlap.bitfield.imm16;
5643 else if (i.suffix == QWORD_MNEM_SUFFIX)
5644 {
5645 temp.bitfield.imm64 = overlap.bitfield.imm64;
5646 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5647 }
5648 else
5649 temp.bitfield.imm32 = overlap.bitfield.imm32;
5650 overlap = temp;
29b0f896 5651 }
0dfbf9d7
L		 5652 else if (operand_type_equal (&overlap, &imm16_32_32s)
5653 || operand_type_equal (&overlap, &imm16_32)
5654 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5655 {
40fb9820 5656 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5657 overlap = imm16;
40fb9820 5658 else
65da13b5 5659 overlap = imm32s;
29b0f896 5660 }
0dfbf9d7
L		 5661 if (!operand_type_equal (&overlap, &imm8)
5662 && !operand_type_equal (&overlap, &imm8s)
5663 && !operand_type_equal (&overlap, &imm16)
5664 && !operand_type_equal (&overlap, &imm32)
5665 && !operand_type_equal (&overlap, &imm32s)
5666 && !operand_type_equal (&overlap, &imm64))
29b0f896 5667 {
4eed87de
AM		 5668 as_bad (_("no instruction mnemonic suffix given; "
5669 "can't determine immediate size"));
29b0f896
AM		 5670 return 0;
5671 }
5672 }
40fb9820 5673 i.types[j] = overlap;
29b0f896 5674
40fb9820
L		 5675 return 1;
5676}
5677
5678static int
5679finalize_imm (void)
5680{
bc0844ae 5681 unsigned int j, n;
29b0f896 5682
bc0844ae
L		 5683 /* Update the first 2 immediate operands. */
5684 n = i.operands > 2 ? 2 : i.operands;
5685 if (n)
5686 {
5687 for (j = 0; j < n; j++)
5688 if (update_imm (j) == 0)
5689 return 0;
40fb9820 5690
bc0844ae
L		 5691 /* The 3rd operand can't be immediate operand. */
5692 gas_assert (operand_type_check (i.types[2], imm) == 0);
5693 }
29b0f896
AM		 5694
5695 return 1;
5696}
5697
c0f3af97
L		 5698static int
5699bad_implicit_operand (int xmm)
5700{
91d6fa6a
NC		 5701 const char *ireg = xmm ? "xmm0" : "ymm0";
5702
c0f3af97
L		 5703 if (intel_syntax)
5704 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5705 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5706 else
5707 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5708 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5709 return 0;
5710}
5711
29b0f896 5712static int
e3bb37b5 5713process_operands (void)
29b0f896
AM		 5714{
5715 /* Default segment register this instruction will use for memory
5716 accesses. 0 means unknown. This is only for optimizing out
5717 unnecessary segment overrides. */
5718 const seg_entry *default_seg = 0;
5719
2426c15f 5720 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5721 {
91d6fa6a
NC		 5722 unsigned int dupl = i.operands;
5723 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5724 unsigned int j;
5725
c0f3af97 5726 /* The destination must be an xmm register. */
9c2799c2 5727 gas_assert (i.reg_operands
91d6fa6a 5728 && MAX_OPERANDS > dupl
7ab9ffdd 5729 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5730
5731 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5732 {
c0f3af97 5733 /* The first operand is implicit and must be xmm0. */
9c2799c2 5734 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5735 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5736 return bad_implicit_operand (1);
5737
8cd7925b 5738 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5739 {
5740 /* Keep xmm0 for instructions with VEX prefix and 3
5741 sources. */
5742 goto duplicate;
5743 }
e2ec9d29 5744 else
c0f3af97
L		 5745 {
5746 /* We remove the first xmm0 and keep the number of
5747 operands unchanged, which in fact duplicates the
5748 destination. */
5749 for (j = 1; j < i.operands; j++)
5750 {
5751 i.op[j - 1] = i.op[j];
5752 i.types[j - 1] = i.types[j];
5753 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5754 }
5755 }
5756 }
5757 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5758 {
91d6fa6a 5759 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5760 && (i.tm.opcode_modifier.vexsources
5761 == VEX3SOURCES));
c0f3af97
L		 5762
5763 /* Add the implicit xmm0 for instructions with VEX prefix
5764 and 3 sources. */
5765 for (j = i.operands; j > 0; j--)
5766 {
5767 i.op[j] = i.op[j - 1];
5768 i.types[j] = i.types[j - 1];
5769 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5770 }
5771 i.op[0].regs
5772 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5773 i.types[0] = regxmm;
c0f3af97
L		 5774 i.tm.operand_types[0] = regxmm;
5775
5776 i.operands += 2;
5777 i.reg_operands += 2;
5778 i.tm.operands += 2;
5779
91d6fa6a 5780 dupl++;
c0f3af97 5781 dest++;
91d6fa6a
NC		 5782 i.op[dupl] = i.op[dest];
5783 i.types[dupl] = i.types[dest];
5784 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5785 }
c0f3af97
L		 5786 else
5787 {
5788duplicate:
5789 i.operands++;
5790 i.reg_operands++;
5791 i.tm.operands++;
5792
91d6fa6a
NC		 5793 i.op[dupl] = i.op[dest];
5794 i.types[dupl] = i.types[dest];
5795 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5796 }
5797
5798 if (i.tm.opcode_modifier.immext)
5799 process_immext ();
5800 }
5801 else if (i.tm.opcode_modifier.firstxmm0)
5802 {
5803 unsigned int j;
5804
43234a1e 5805 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5806 gas_assert (i.reg_operands
7ab9ffdd 5807 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5808 || operand_type_equal (&i.types[0], &regymm)
5809 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5810 if (register_number (i.op[0].regs) != 0)
c0f3af97 5811 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5812
5813 for (j = 1; j < i.operands; j++)
5814 {
5815 i.op[j - 1] = i.op[j];
5816 i.types[j - 1] = i.types[j];
5817
5818 /* We need to adjust fields in i.tm since they are used by
5819 build_modrm_byte. */
5820 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5821 }
5822
e2ec9d29
L		 5823 i.operands--;
5824 i.reg_operands--;
e2ec9d29
L		 5825 i.tm.operands--;
5826 }
5827 else if (i.tm.opcode_modifier.regkludge)
5828 {
5829 /* The imul $imm, %reg instruction is converted into
5830 imul $imm, %reg, %reg, and the clr %reg instruction
5831 is converted into xor %reg, %reg. */
5832
5833 unsigned int first_reg_op;
5834
5835 if (operand_type_check (i.types[0], reg))
5836 first_reg_op = 0;
5837 else
5838 first_reg_op = 1;
5839 /* Pretend we saw the extra register operand. */
9c2799c2 5840 gas_assert (i.reg_operands == 1
7ab9ffdd 5841 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5842 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5843 i.types[first_reg_op + 1] = i.types[first_reg_op];
5844 i.operands++;
5845 i.reg_operands++;
29b0f896
AM		 5846 }
5847
40fb9820 5848 if (i.tm.opcode_modifier.shortform)
29b0f896 5849 {
40fb9820
L		 5850 if (i.types[0].bitfield.sreg2
5851 || i.types[0].bitfield.sreg3)
29b0f896 5852 {
4eed87de
AM		 5853 if (i.tm.base_opcode == POP_SEG_SHORT
5854 && i.op[0].regs->reg_num == 1)
29b0f896 5855 {
a87af027 5856 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5857 return 0;
29b0f896 5858 }
4eed87de
AM		 5859 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5860 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5861 i.rex |= REX_B;
4eed87de
AM		 5862 }
5863 else
5864 {
7ab9ffdd 5865 /* The register or float register operand is in operand
85f10a01 5866 0 or 1. */
40fb9820 5867 unsigned int op;
7ab9ffdd
L		 5868
5869 if (i.types[0].bitfield.floatreg
5870 || operand_type_check (i.types[0], reg))
5871 op = 0;
5872 else
5873 op = 1;
4eed87de
AM		 5874 /* Register goes in low 3 bits of opcode. */
5875 i.tm.base_opcode |= i.op[op].regs->reg_num;
5876 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5877 i.rex |= REX_B;
40fb9820 5878 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5879 {
4eed87de
AM		 5880 /* Warn about some common errors, but press on regardless.
5881 The first case can be generated by gcc (<= 2.8.1). */
5882 if (i.operands == 2)
5883 {
5884 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5885 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5886 register_prefix, i.op[!intel_syntax].regs->reg_name,
5887 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5888 }
5889 else
5890 {
5891 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5892 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5893 register_prefix, i.op[0].regs->reg_name);
4eed87de 5894 }
29b0f896
AM		 5895 }
5896 }
5897 }
40fb9820 5898 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5899 {
5900 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5901 must be put into the modrm byte). Now, we make the modrm and
5902 index base bytes based on all the info we've collected. */
29b0f896
AM		 5903
5904 default_seg = build_modrm_byte ();
5905 }
8a2ed489 5906 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5907 {
5908 default_seg = &ds;
5909 }
40fb9820 5910 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5911 {
5912 /* For the string instructions that allow a segment override
5913 on one of their operands, the default segment is ds. */
5914 default_seg = &ds;
5915 }
5916
75178d9d
L		 5917 if (i.tm.base_opcode == 0x8d /* lea */
5918 && i.seg[0]
5919 && !quiet_warnings)
30123838 5920 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5921
5922 /* If a segment was explicitly specified, and the specified segment
5923 is not the default, use an opcode prefix to select it. If we
5924 never figured out what the default segment is, then default_seg
5925 will be zero at this point, and the specified segment prefix will
5926 always be used. */
29b0f896
AM		 5927 if ((i.seg[0]) && (i.seg[0] != default_seg))
5928 {
5929 if (!add_prefix (i.seg[0]->seg_prefix))
5930 return 0;
5931 }
5932 return 1;
5933}
5934
5935static const seg_entry *
e3bb37b5 5936build_modrm_byte (void)
29b0f896
AM		 5937{
5938 const seg_entry *default_seg = 0;
c0f3af97 5939 unsigned int source, dest;
8cd7925b 5940 int vex_3_sources;
c0f3af97
L		 5941
5942 /* The first operand of instructions with VEX prefix and 3 sources
5943 must be VEX_Imm4. */
8cd7925b 5944 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5945 if (vex_3_sources)
5946 {
91d6fa6a 5947 unsigned int nds, reg_slot;
4c2c6516 5948 expressionS *exp;
c0f3af97 5949
922d8de8 5950 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5951 && i.tm.opcode_modifier.immext)
5952 {
5953 dest = i.operands - 2;
5954 gas_assert (dest == 3);
5955 }
922d8de8 5956 else
a683cc34 5957 dest = i.operands - 1;
c0f3af97 5958 nds = dest - 1;
922d8de8 5959
a683cc34
SP		 5960 /* There are 2 kinds of instructions:
5961 1. 5 operands: 4 register operands or 3 register operands
5962 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5963 VexW0 or VexW1. The destination must be either XMM, YMM or
5964 ZMM register.
a683cc34
SP		 5965 2. 4 operands: 4 register operands or 3 register operands
5966 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5967 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5968 || (i.reg_operands == 3 && i.mem_operands == 1))
5969 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5970 && (i.tm.opcode_modifier.veximmext
5971 || (i.imm_operands == 1
5972 && i.types[0].bitfield.vec_imm4
5973 && (i.tm.opcode_modifier.vexw == VEXW0
5974 || i.tm.opcode_modifier.vexw == VEXW1)
5975 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5976 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5977 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5978
5979 if (i.imm_operands == 0)
5980 {
5981 /* When there is no immediate operand, generate an 8bit
5982 immediate operand to encode the first operand. */
5983 exp = &im_expressions[i.imm_operands++];
5984 i.op[i.operands].imms = exp;
5985 i.types[i.operands] = imm8;
5986 i.operands++;
5987 /* If VexW1 is set, the first operand is the source and
5988 the second operand is encoded in the immediate operand. */
5989 if (i.tm.opcode_modifier.vexw == VEXW1)
5990 {
5991 source = 0;
5992 reg_slot = 1;
5993 }
5994 else
5995 {
5996 source = 1;
5997 reg_slot = 0;
5998 }
5999
6000 /* FMA swaps REG and NDS. */
6001 if (i.tm.cpu_flags.bitfield.cpufma)
6002 {
6003 unsigned int tmp;
6004 tmp = reg_slot;
6005 reg_slot = nds;
6006 nds = tmp;
6007 }
6008
24981e7b
L		 6009 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6010 &regxmm)
a683cc34 6011 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6012 &regymm)
6013 || operand_type_equal (&i.tm.operand_types[reg_slot],
6014 &regzmm));
a683cc34 6015 exp->X_op = O_constant;
4c692bc7 6016 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6017 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6018 }
922d8de8 6019 else
a683cc34
SP		 6020 {
6021 unsigned int imm_slot;
6022
6023 if (i.tm.opcode_modifier.vexw == VEXW0)
6024 {
6025 /* If VexW0 is set, the third operand is the source and
6026 the second operand is encoded in the immediate
6027 operand. */
6028 source = 2;
6029 reg_slot = 1;
6030 }
6031 else
6032 {
6033 /* VexW1 is set, the second operand is the source and
6034 the third operand is encoded in the immediate
6035 operand. */
6036 source = 1;
6037 reg_slot = 2;
6038 }
6039
6040 if (i.tm.opcode_modifier.immext)
6041 {
6042 /* When ImmExt is set, the immdiate byte is the last
6043 operand. */
6044 imm_slot = i.operands - 1;
6045 source--;
6046 reg_slot--;
6047 }
6048 else
6049 {
6050 imm_slot = 0;
6051
6052 /* Turn on Imm8 so that output_imm will generate it. */
6053 i.types[imm_slot].bitfield.imm8 = 1;
6054 }
6055
24981e7b
L		 6056 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6057 &regxmm)
6058 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6059 &regymm)
6060 || operand_type_equal (&i.tm.operand_types[reg_slot],
6061 &regzmm));
a683cc34 6062 i.op[imm_slot].imms->X_add_number
4c692bc7 6063 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6064 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6065 }
6066
6067 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6068 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6069 &regymm)
6070 || operand_type_equal (&i.tm.operand_types[nds],
6071 &regzmm));
dae39acc 6072 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6073 }
6074 else
6075 source = dest = 0;
29b0f896
AM		 6076
6077 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6078 implicit registers do not count. If there are 3 register
6079 operands, it must be a instruction with VexNDS. For a
6080 instruction with VexNDD, the destination register is encoded
6081 in VEX prefix. If there are 4 register operands, it must be
6082 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6083 if (i.mem_operands == 0
6084 && ((i.reg_operands == 2
2426c15f 6085 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6086 || (i.reg_operands == 3
2426c15f 6087 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6088 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6089 {
cab737b9
L		 6090 switch (i.operands)
6091 {
6092 case 2:
6093 source = 0;
6094 break;
6095 case 3:
c81128dc
L		 6096 /* When there are 3 operands, one of them may be immediate,
6097 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6098 the first operand must be shift count register (cl) or it
6099 is an instruction with VexNDS. */
9c2799c2 6100 gas_assert (i.imm_operands == 1
7ab9ffdd 6101 || (i.imm_operands == 0
2426c15f 6102 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6103 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6104 if (operand_type_check (i.types[0], imm)
6105 || i.types[0].bitfield.shiftcount)
6106 source = 1;
6107 else
6108 source = 0;
cab737b9
L		 6109 break;
6110 case 4:
368d64cc
L		 6111 /* When there are 4 operands, the first two must be 8bit
6112 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6113 one.
6114
6115 For instructions with VexNDS, if the first operand
6116 an imm8, the source operand is the 2nd one. If the last
6117 operand is imm8, the source operand is the first one. */
9c2799c2 6118 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6119 && i.types[0].bitfield.imm8
6120 && i.types[1].bitfield.imm8)
2426c15f 6121 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6122 && i.imm_operands == 1
6123 && (i.types[0].bitfield.imm8
43234a1e
L		 6124 || i.types[i.operands - 1].bitfield.imm8
6125 || i.rounding)));
9f2670f2
L		 6126 if (i.imm_operands == 2)
6127 source = 2;
6128 else
c0f3af97
L		 6129 {
6130 if (i.types[0].bitfield.imm8)
6131 source = 1;
6132 else
6133 source = 0;
6134 }
c0f3af97
L		 6135 break;
6136 case 5:
43234a1e
L		 6137 if (i.tm.opcode_modifier.evex)
6138 {
6139 /* For EVEX instructions, when there are 5 operands, the
6140 first one must be immediate operand. If the second one
6141 is immediate operand, the source operand is the 3th
6142 one. If the last one is immediate operand, the source
6143 operand is the 2nd one. */
6144 gas_assert (i.imm_operands == 2
6145 && i.tm.opcode_modifier.sae
6146 && operand_type_check (i.types[0], imm));
6147 if (operand_type_check (i.types[1], imm))
6148 source = 2;
6149 else if (operand_type_check (i.types[4], imm))
6150 source = 1;
6151 else
6152 abort ();
6153 }
cab737b9
L		 6154 break;
6155 default:
6156 abort ();
6157 }
6158
c0f3af97
L		 6159 if (!vex_3_sources)
6160 {
6161 dest = source + 1;
6162
43234a1e
L		 6163 /* RC/SAE operand could be between DEST and SRC. That happens
6164 when one operand is GPR and the other one is XMM/YMM/ZMM
6165 register. */
6166 if (i.rounding && i.rounding->operand == (int) dest)
6167 dest++;
6168
2426c15f 6169 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6170 {
43234a1e
L		 6171 /* For instructions with VexNDS, the register-only source
6172 operand must be 32/64bit integer, XMM, YMM or ZMM
6173 register. It is encoded in VEX prefix. We need to
6174 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6175
6176 i386_operand_type op;
6177 unsigned int vvvv;
6178
6179 /* Check register-only source operand when two source
6180 operands are swapped. */
6181 if (!i.tm.operand_types[source].bitfield.baseindex
6182 && i.tm.operand_types[dest].bitfield.baseindex)
6183 {
6184 vvvv = source;
6185 source = dest;
6186 }
6187 else
6188 vvvv = dest;
6189
6190 op = i.tm.operand_types[vvvv];
fa99fab2 6191 op.bitfield.regmem = 0;
c0f3af97 6192 if ((dest + 1) >= i.operands
ac4eb736
AM		 6193 || (!op.bitfield.reg32
6194 && op.bitfield.reg64
f12dc422 6195 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6196 && !operand_type_equal (&op, &regymm)
6197 && !operand_type_equal (&op, &regzmm)
6198 && !operand_type_equal (&op, &regmask)))
c0f3af97 6199 abort ();
f12dc422 6200 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6201 dest++;
6202 }
6203 }
29b0f896
AM		 6204
6205 i.rm.mode = 3;
6206 /* One of the register operands will be encoded in the i.tm.reg
6207 field, the other in the combined i.tm.mode and i.tm.regmem
6208 fields. If no form of this instruction supports a memory
6209 destination operand, then we assume the source operand may
6210 sometimes be a memory operand and so we need to store the
6211 destination in the i.rm.reg field. */
40fb9820
L		 6212 if (!i.tm.operand_types[dest].bitfield.regmem
6213 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6214 {
6215 i.rm.reg = i.op[dest].regs->reg_num;
6216 i.rm.regmem = i.op[source].regs->reg_num;
6217 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6218 i.rex |= REX_R;
43234a1e
L		 6219 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6220 i.vrex |= REX_R;
29b0f896 6221 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6222 i.rex |= REX_B;
43234a1e
L		 6223 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6224 i.vrex |= REX_B;
29b0f896
AM		 6225 }
6226 else
6227 {
6228 i.rm.reg = i.op[source].regs->reg_num;
6229 i.rm.regmem = i.op[dest].regs->reg_num;
6230 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6231 i.rex |= REX_B;
43234a1e
L		 6232 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6233 i.vrex |= REX_B;
29b0f896 6234 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6235 i.rex |= REX_R;
43234a1e
L		 6236 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6237 i.vrex |= REX_R;
29b0f896 6238 }
161a04f6 6239 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6240 {
40fb9820
L		 6241 if (!i.types[0].bitfield.control
6242 && !i.types[1].bitfield.control)
c4a530c5 6243 abort ();
161a04f6 6244 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6245 add_prefix (LOCK_PREFIX_OPCODE);
6246 }
29b0f896
AM		 6247 }
6248 else
6249 { /* If it's not 2 reg operands... */
c0f3af97
L		 6250 unsigned int mem;
6251
29b0f896
AM		 6252 if (i.mem_operands)
6253 {
6254 unsigned int fake_zero_displacement = 0;
99018f42 6255 unsigned int op;
4eed87de 6256
7ab9ffdd
L		 6257 for (op = 0; op < i.operands; op++)
6258 if (operand_type_check (i.types[op], anymem))
6259 break;
7ab9ffdd 6260 gas_assert (op < i.operands);
29b0f896 6261
6c30d220
L		 6262 if (i.tm.opcode_modifier.vecsib)
6263 {
6264 if (i.index_reg->reg_num == RegEiz
6265 || i.index_reg->reg_num == RegRiz)
6266 abort ();
6267
6268 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6269 if (!i.base_reg)
6270 {
6271 i.sib.base = NO_BASE_REGISTER;
6272 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6273 /* No Vec_Disp8 if there is no base. */
6274 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6275 i.types[op].bitfield.disp8 = 0;
6276 i.types[op].bitfield.disp16 = 0;
6277 i.types[op].bitfield.disp64 = 0;
6278 if (flag_code != CODE_64BIT)
6279 {
6280 /* Must be 32 bit */
6281 i.types[op].bitfield.disp32 = 1;
6282 i.types[op].bitfield.disp32s = 0;
6283 }
6284 else
6285 {
6286 i.types[op].bitfield.disp32 = 0;
6287 i.types[op].bitfield.disp32s = 1;
6288 }
6289 }
6290 i.sib.index = i.index_reg->reg_num;
6291 if ((i.index_reg->reg_flags & RegRex) != 0)
6292 i.rex |= REX_X;
43234a1e
L		 6293 if ((i.index_reg->reg_flags & RegVRex) != 0)
6294 i.vrex |= REX_X;
6c30d220
L		 6295 }
6296
29b0f896
AM		 6297 default_seg = &ds;
6298
6299 if (i.base_reg == 0)
6300 {
6301 i.rm.mode = 0;
6302 if (!i.disp_operands)
6c30d220
L		 6303 {
6304 fake_zero_displacement = 1;
6305 /* Instructions with VSIB byte need 32bit displacement
6306 if there is no base register. */
6307 if (i.tm.opcode_modifier.vecsib)
6308 i.types[op].bitfield.disp32 = 1;
6309 }
29b0f896
AM		 6310 if (i.index_reg == 0)
6311 {
6c30d220 6312 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6313 /* Operand is just <disp> */
20f0a1fc 6314 if (flag_code == CODE_64BIT)
29b0f896
AM		 6315 {
6316 /* 64bit mode overwrites the 32bit absolute
6317 addressing by RIP relative addressing and
6318 absolute addressing is encoded by one of the
6319 redundant SIB forms. */
6320 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6321 i.sib.base = NO_BASE_REGISTER;
6322 i.sib.index = NO_INDEX_REGISTER;
fc225355 6323 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6324 ? disp32s : disp32);
20f0a1fc 6325 }
fc225355
L		 6326 else if ((flag_code == CODE_16BIT)
6327 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6328 {
6329 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6330 i.types[op] = disp16;
20f0a1fc
NC		 6331 }
6332 else
6333 {
6334 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6335 i.types[op] = disp32;
29b0f896
AM		 6336 }
6337 }
6c30d220 6338 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6339 {
6c30d220 6340 /* !i.base_reg && i.index_reg */
db51cc60
L		 6341 if (i.index_reg->reg_num == RegEiz
6342 || i.index_reg->reg_num == RegRiz)
6343 i.sib.index = NO_INDEX_REGISTER;
6344 else
6345 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6346 i.sib.base = NO_BASE_REGISTER;
6347 i.sib.scale = i.log2_scale_factor;
6348 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6349 /* No Vec_Disp8 if there is no base. */
6350 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6351 i.types[op].bitfield.disp8 = 0;
6352 i.types[op].bitfield.disp16 = 0;
6353 i.types[op].bitfield.disp64 = 0;
29b0f896 6354 if (flag_code != CODE_64BIT)
40fb9820
L		 6355 {
6356 /* Must be 32 bit */
6357 i.types[op].bitfield.disp32 = 1;
6358 i.types[op].bitfield.disp32s = 0;
6359 }
29b0f896 6360 else
40fb9820
L		 6361 {
6362 i.types[op].bitfield.disp32 = 0;
6363 i.types[op].bitfield.disp32s = 1;
6364 }
29b0f896 6365 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6366 i.rex |= REX_X;
29b0f896
AM		 6367 }
6368 }
6369 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6370 else if (i.base_reg->reg_num == RegRip ||
6371 i.base_reg->reg_num == RegEip)
29b0f896 6372 {
6c30d220 6373 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6374 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6375 i.types[op].bitfield.disp8 = 0;
6376 i.types[op].bitfield.disp16 = 0;
6377 i.types[op].bitfield.disp32 = 0;
6378 i.types[op].bitfield.disp32s = 1;
6379 i.types[op].bitfield.disp64 = 0;
43234a1e 6380 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6381 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6382 if (! i.disp_operands)
6383 fake_zero_displacement = 1;
29b0f896 6384 }
40fb9820 6385 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6386 {
6c30d220 6387 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6388 switch (i.base_reg->reg_num)
6389 {
6390 case 3: /* (%bx) */
6391 if (i.index_reg == 0)
6392 i.rm.regmem = 7;
6393 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6394 i.rm.regmem = i.index_reg->reg_num - 6;
6395 break;
6396 case 5: /* (%bp) */
6397 default_seg = &ss;
6398 if (i.index_reg == 0)
6399 {
6400 i.rm.regmem = 6;
40fb9820 6401 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6402 {
6403 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6404 if (i.tm.operand_types[op].bitfield.vec_disp8)
6405 i.types[op].bitfield.vec_disp8 = 1;
6406 else
6407 i.types[op].bitfield.disp8 = 1;
252b5132 6408 fake_zero_displacement = 1;
29b0f896
AM		 6409 }
6410 }
6411 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6412 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6413 break;
6414 default: /* (%si) -> 4 or (%di) -> 5 */
6415 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6416 }
6417 i.rm.mode = mode_from_disp_size (i.types[op]);
6418 }
6419 else /* i.base_reg and 32/64 bit mode */
6420 {
6421 if (flag_code == CODE_64BIT
40fb9820
L		 6422 && operand_type_check (i.types[op], disp))
6423 {
6424 i386_operand_type temp;
0dfbf9d7 6425 operand_type_set (&temp, 0);
40fb9820 6426 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6427 temp.bitfield.vec_disp8
6428 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6429 i.types[op] = temp;
6430 if (i.prefix[ADDR_PREFIX] == 0)
6431 i.types[op].bitfield.disp32s = 1;
6432 else
6433 i.types[op].bitfield.disp32 = 1;
6434 }
20f0a1fc 6435
6c30d220
L		 6436 if (!i.tm.opcode_modifier.vecsib)
6437 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6438 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6439 i.rex |= REX_B;
29b0f896
AM		 6440 i.sib.base = i.base_reg->reg_num;
6441 /* x86-64 ignores REX prefix bit here to avoid decoder
6442 complications. */
848930b2
JB		 6443 if (!(i.base_reg->reg_flags & RegRex)
6444 && (i.base_reg->reg_num == EBP_REG_NUM
6445 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6446 default_seg = &ss;
848930b2 6447 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6448 {
848930b2 6449 fake_zero_displacement = 1;
43234a1e
L		 6450 if (i.tm.operand_types [op].bitfield.vec_disp8)
6451 i.types[op].bitfield.vec_disp8 = 1;
6452 else
6453 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6454 }
6455 i.sib.scale = i.log2_scale_factor;
6456 if (i.index_reg == 0)
6457 {
6c30d220 6458 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6459 /* <disp>(%esp) becomes two byte modrm with no index
6460 register. We've already stored the code for esp
6461 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6462 Any base register besides %esp will not use the
6463 extra modrm byte. */
6464 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6465 }
6c30d220 6466 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6467 {
db51cc60
L		 6468 if (i.index_reg->reg_num == RegEiz
6469 || i.index_reg->reg_num == RegRiz)
6470 i.sib.index = NO_INDEX_REGISTER;
6471 else
6472 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6473 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6474 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6475 i.rex |= REX_X;
29b0f896 6476 }
67a4f2b7
AO		 6477
6478 if (i.disp_operands
6479 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6480 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6481 i.rm.mode = 0;
6482 else
a501d77e
L		 6483 {
6484 if (!fake_zero_displacement
6485 && !i.disp_operands
6486 && i.disp_encoding)
6487 {
6488 fake_zero_displacement = 1;
6489 if (i.disp_encoding == disp_encoding_8bit)
6490 i.types[op].bitfield.disp8 = 1;
6491 else
6492 i.types[op].bitfield.disp32 = 1;
6493 }
6494 i.rm.mode = mode_from_disp_size (i.types[op]);
6495 }
29b0f896 6496 }
252b5132 6497
29b0f896
AM		 6498 if (fake_zero_displacement)
6499 {
6500 /* Fakes a zero displacement assuming that i.types[op]
6501 holds the correct displacement size. */
6502 expressionS *exp;
6503
9c2799c2 6504 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6505 exp = &disp_expressions[i.disp_operands++];
6506 i.op[op].disps = exp;
6507 exp->X_op = O_constant;
6508 exp->X_add_number = 0;
6509 exp->X_add_symbol = (symbolS *) 0;
6510 exp->X_op_symbol = (symbolS *) 0;
6511 }
c0f3af97
L		 6512
6513 mem = op;
29b0f896 6514 }
c0f3af97
L		 6515 else
6516 mem = ~0;
252b5132 6517
8c43a48b 6518 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6519 {
6520 if (operand_type_check (i.types[0], imm))
6521 i.vex.register_specifier = NULL;
6522 else
6523 {
6524 /* VEX.vvvv encodes one of the sources when the first
6525 operand is not an immediate. */
1ef99a7b 6526 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6527 i.vex.register_specifier = i.op[0].regs;
6528 else
6529 i.vex.register_specifier = i.op[1].regs;
6530 }
6531
6532 /* Destination is a XMM register encoded in the ModRM.reg
6533 and VEX.R bit. */
6534 i.rm.reg = i.op[2].regs->reg_num;
6535 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6536 i.rex |= REX_R;
6537
6538 /* ModRM.rm and VEX.B encodes the other source. */
6539 if (!i.mem_operands)
6540 {
6541 i.rm.mode = 3;
6542
1ef99a7b 6543 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6544 i.rm.regmem = i.op[1].regs->reg_num;
6545 else
6546 i.rm.regmem = i.op[0].regs->reg_num;
6547
6548 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6549 i.rex |= REX_B;
6550 }
6551 }
2426c15f 6552 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6553 {
6554 i.vex.register_specifier = i.op[2].regs;
6555 if (!i.mem_operands)
6556 {
6557 i.rm.mode = 3;
6558 i.rm.regmem = i.op[1].regs->reg_num;
6559 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6560 i.rex |= REX_B;
6561 }
6562 }
29b0f896
AM		 6563 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6564 (if any) based on i.tm.extension_opcode. Again, we must be
6565 careful to make sure that segment/control/debug/test/MMX
6566 registers are coded into the i.rm.reg field. */
f88c9eb0 6567 else if (i.reg_operands)
29b0f896 6568 {
99018f42 6569 unsigned int op;
7ab9ffdd
L		 6570 unsigned int vex_reg = ~0;
6571
6572 for (op = 0; op < i.operands; op++)
6573 if (i.types[op].bitfield.reg8
6574 || i.types[op].bitfield.reg16
6575 || i.types[op].bitfield.reg32
6576 || i.types[op].bitfield.reg64
6577 || i.types[op].bitfield.regmmx
6578 || i.types[op].bitfield.regxmm
6579 || i.types[op].bitfield.regymm
7e8b059b 6580 || i.types[op].bitfield.regbnd
43234a1e
L		 6581 || i.types[op].bitfield.regzmm
6582 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6583 || i.types[op].bitfield.sreg2
6584 || i.types[op].bitfield.sreg3
6585 || i.types[op].bitfield.control
6586 || i.types[op].bitfield.debug
6587 || i.types[op].bitfield.test)
6588 break;
c0209578 6589
7ab9ffdd
L		 6590 if (vex_3_sources)
6591 op = dest;
2426c15f 6592 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6593 {
6594 /* For instructions with VexNDS, the register-only
6595 source operand is encoded in VEX prefix. */
6596 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6597
7ab9ffdd 6598 if (op > mem)
c0f3af97 6599 {
7ab9ffdd
L		 6600 vex_reg = op++;
6601 gas_assert (op < i.operands);
c0f3af97
L		 6602 }
6603 else
c0f3af97 6604 {
f12dc422
L		 6605 /* Check register-only source operand when two source
6606 operands are swapped. */
6607 if (!i.tm.operand_types[op].bitfield.baseindex
6608 && i.tm.operand_types[op + 1].bitfield.baseindex)
6609 {
6610 vex_reg = op;
6611 op += 2;
6612 gas_assert (mem == (vex_reg + 1)
6613 && op < i.operands);
6614 }
6615 else
6616 {
6617 vex_reg = op + 1;
6618 gas_assert (vex_reg < i.operands);
6619 }
c0f3af97 6620 }
7ab9ffdd 6621 }
2426c15f 6622 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6623 {
f12dc422 6624 /* For instructions with VexNDD, the register destination
7ab9ffdd 6625 is encoded in VEX prefix. */
f12dc422
L		 6626 if (i.mem_operands == 0)
6627 {
6628 /* There is no memory operand. */
6629 gas_assert ((op + 2) == i.operands);
6630 vex_reg = op + 1;
6631 }
6632 else
8d63c93e 6633 {
f12dc422
L		 6634 /* There are only 2 operands. */
6635 gas_assert (op < 2 && i.operands == 2);
6636 vex_reg = 1;
6637 }
7ab9ffdd
L		 6638 }
6639 else
6640 gas_assert (op < i.operands);
99018f42 6641
7ab9ffdd
L		 6642 if (vex_reg != (unsigned int) ~0)
6643 {
f12dc422 6644 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6645
f12dc422
L		 6646 if (type->bitfield.reg32 != 1
6647 && type->bitfield.reg64 != 1
6648 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6649 && !operand_type_equal (type, &regymm)
6650 && !operand_type_equal (type, &regzmm)
6651 && !operand_type_equal (type, &regmask))
7ab9ffdd 6652 abort ();
f88c9eb0 6653
7ab9ffdd
L		 6654 i.vex.register_specifier = i.op[vex_reg].regs;
6655 }
6656
1b9f0c97
L		 6657 /* Don't set OP operand twice. */
6658 if (vex_reg != op)
7ab9ffdd 6659 {
1b9f0c97
L		 6660 /* If there is an extension opcode to put here, the
6661 register number must be put into the regmem field. */
6662 if (i.tm.extension_opcode != None)
6663 {
6664 i.rm.regmem = i.op[op].regs->reg_num;
6665 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6666 i.rex |= REX_B;
43234a1e
L		 6667 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6668 i.vrex |= REX_B;
1b9f0c97
L		 6669 }
6670 else
6671 {
6672 i.rm.reg = i.op[op].regs->reg_num;
6673 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6674 i.rex |= REX_R;
43234a1e
L		 6675 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6676 i.vrex |= REX_R;
1b9f0c97 6677 }
7ab9ffdd 6678 }
252b5132 6679
29b0f896
AM		 6680 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6681 must set it to 3 to indicate this is a register operand
6682 in the regmem field. */
6683 if (!i.mem_operands)
6684 i.rm.mode = 3;
6685 }
252b5132 6686
29b0f896 6687 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6688 if (i.tm.extension_opcode != None)
29b0f896
AM		 6689 i.rm.reg = i.tm.extension_opcode;
6690 }
6691 return default_seg;
6692}
252b5132 6693
29b0f896 6694static void
e3bb37b5 6695output_branch (void)
29b0f896
AM		 6696{
6697 char *p;
f8a5c266 6698 int size;
29b0f896
AM		 6699 int code16;
6700 int prefix;
6701 relax_substateT subtype;
6702 symbolS *sym;
6703 offsetT off;
6704
f8a5c266 6705 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6706 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6707
6708 prefix = 0;
6709 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6710 {
29b0f896
AM		 6711 prefix = 1;
6712 i.prefixes -= 1;
6713 code16 ^= CODE16;
252b5132 6714 }
29b0f896
AM		 6715 /* Pentium4 branch hints. */
6716 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6717 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6718 {
29b0f896
AM		 6719 prefix++;
6720 i.prefixes--;
6721 }
6722 if (i.prefix[REX_PREFIX] != 0)
6723 {
6724 prefix++;
6725 i.prefixes--;
2f66722d
AM		 6726 }
6727
7e8b059b
L		 6728 /* BND prefixed jump. */
6729 if (i.prefix[BND_PREFIX] != 0)
6730 {
6731 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6732 i.prefixes -= 1;
6733 }
6734
29b0f896
AM		 6735 if (i.prefixes != 0 && !intel_syntax)
6736 as_warn (_("skipping prefixes on this instruction"));
6737
6738 /* It's always a symbol; End frag & setup for relax.
6739 Make sure there is enough room in this frag for the largest
6740 instruction we may generate in md_convert_frag. This is 2
6741 bytes for the opcode and room for the prefix and largest
6742 displacement. */
6743 frag_grow (prefix + 2 + 4);
6744 /* Prefix and 1 opcode byte go in fr_fix. */
6745 p = frag_more (prefix + 1);
6746 if (i.prefix[DATA_PREFIX] != 0)
6747 *p++ = DATA_PREFIX_OPCODE;
6748 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6749 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6750 *p++ = i.prefix[SEG_PREFIX];
6751 if (i.prefix[REX_PREFIX] != 0)
6752 *p++ = i.prefix[REX_PREFIX];
6753 *p = i.tm.base_opcode;
6754
6755 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6756 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6757 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6758 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6759 else
f8a5c266 6760 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6761 subtype |= code16;
3e73aa7c 6762
29b0f896
AM		 6763 sym = i.op[0].disps->X_add_symbol;
6764 off = i.op[0].disps->X_add_number;
3e73aa7c 6765
29b0f896
AM		 6766 if (i.op[0].disps->X_op != O_constant
6767 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6768 {
29b0f896
AM		 6769 /* Handle complex expressions. */
6770 sym = make_expr_symbol (i.op[0].disps);
6771 off = 0;
6772 }
3e73aa7c 6773
29b0f896
AM		 6774 /* 1 possible extra opcode + 4 byte displacement go in var part.
6775 Pass reloc in fr_var. */
d258b828 6776 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6777}
3e73aa7c 6778
29b0f896 6779static void
e3bb37b5 6780output_jump (void)
29b0f896
AM		 6781{
6782 char *p;
6783 int size;
3e02c1cc 6784 fixS *fixP;
29b0f896 6785
40fb9820 6786 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6787 {
6788 /* This is a loop or jecxz type instruction. */
6789 size = 1;
6790 if (i.prefix[ADDR_PREFIX] != 0)
6791 {
6792 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6793 i.prefixes -= 1;
6794 }
6795 /* Pentium4 branch hints. */
6796 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6797 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6798 {
6799 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6800 i.prefixes--;
3e73aa7c
JH		 6801 }
6802 }
29b0f896
AM		 6803 else
6804 {
6805 int code16;
3e73aa7c 6806
29b0f896
AM		 6807 code16 = 0;
6808 if (flag_code == CODE_16BIT)
6809 code16 = CODE16;
3e73aa7c 6810
29b0f896
AM		 6811 if (i.prefix[DATA_PREFIX] != 0)
6812 {
6813 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6814 i.prefixes -= 1;
6815 code16 ^= CODE16;
6816 }
252b5132 6817
29b0f896
AM		 6818 size = 4;
6819 if (code16)
6820 size = 2;
6821 }
9fcc94b6 6822
29b0f896
AM		 6823 if (i.prefix[REX_PREFIX] != 0)
6824 {
6825 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6826 i.prefixes -= 1;
6827 }
252b5132 6828
7e8b059b
L		 6829 /* BND prefixed jump. */
6830 if (i.prefix[BND_PREFIX] != 0)
6831 {
6832 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6833 i.prefixes -= 1;
6834 }
6835
29b0f896
AM		 6836 if (i.prefixes != 0 && !intel_syntax)
6837 as_warn (_("skipping prefixes on this instruction"));
e0890092 6838
42164a71
L		 6839 p = frag_more (i.tm.opcode_length + size);
6840 switch (i.tm.opcode_length)
6841 {
6842 case 2:
6843 *p++ = i.tm.base_opcode >> 8;
6844 case 1:
6845 *p++ = i.tm.base_opcode;
6846 break;
6847 default:
6848 abort ();
6849 }
e0890092 6850
3e02c1cc 6851 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6852 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6853
6854 /* All jumps handled here are signed, but don't use a signed limit
6855 check for 32 and 16 bit jumps as we want to allow wrap around at
6856 4G and 64k respectively. */
6857 if (size == 1)
6858 fixP->fx_signed = 1;
29b0f896 6859}
e0890092 6860
29b0f896 6861static void
e3bb37b5 6862output_interseg_jump (void)
29b0f896
AM		 6863{
6864 char *p;
6865 int size;
6866 int prefix;
6867 int code16;
252b5132 6868
29b0f896
AM		 6869 code16 = 0;
6870 if (flag_code == CODE_16BIT)
6871 code16 = CODE16;
a217f122 6872
29b0f896
AM		 6873 prefix = 0;
6874 if (i.prefix[DATA_PREFIX] != 0)
6875 {
6876 prefix = 1;
6877 i.prefixes -= 1;
6878 code16 ^= CODE16;
6879 }
6880 if (i.prefix[REX_PREFIX] != 0)
6881 {
6882 prefix++;
6883 i.prefixes -= 1;
6884 }
252b5132 6885
29b0f896
AM		 6886 size = 4;
6887 if (code16)
6888 size = 2;
252b5132 6889
29b0f896
AM		 6890 if (i.prefixes != 0 && !intel_syntax)
6891 as_warn (_("skipping prefixes on this instruction"));
252b5132 6892
29b0f896
AM		 6893 /* 1 opcode; 2 segment; offset */
6894 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6895
29b0f896
AM		 6896 if (i.prefix[DATA_PREFIX] != 0)
6897 *p++ = DATA_PREFIX_OPCODE;
252b5132 6898
29b0f896
AM		 6899 if (i.prefix[REX_PREFIX] != 0)
6900 *p++ = i.prefix[REX_PREFIX];
252b5132 6901
29b0f896
AM		 6902 *p++ = i.tm.base_opcode;
6903 if (i.op[1].imms->X_op == O_constant)
6904 {
6905 offsetT n = i.op[1].imms->X_add_number;
252b5132 6906
29b0f896
AM		 6907 if (size == 2
6908 && !fits_in_unsigned_word (n)
6909 && !fits_in_signed_word (n))
6910 {
6911 as_bad (_("16-bit jump out of range"));
6912 return;
6913 }
6914 md_number_to_chars (p, n, size);
6915 }
6916 else
6917 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6918 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6919 if (i.op[0].imms->X_op != O_constant)
6920 as_bad (_("can't handle non absolute segment in `%s'"),
6921 i.tm.name);
6922 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6923}
a217f122 6924
29b0f896 6925static void
e3bb37b5 6926output_insn (void)
29b0f896 6927{
2bbd9c25
JJ		 6928 fragS *insn_start_frag;
6929 offsetT insn_start_off;
6930
29b0f896
AM		 6931 /* Tie dwarf2 debug info to the address at the start of the insn.
6932 We can't do this after the insn has been output as the current
6933 frag may have been closed off. eg. by frag_var. */
6934 dwarf2_emit_insn (0);
6935
2bbd9c25
JJ		 6936 insn_start_frag = frag_now;
6937 insn_start_off = frag_now_fix ();
6938
29b0f896 6939 /* Output jumps. */
40fb9820 6940 if (i.tm.opcode_modifier.jump)
29b0f896 6941 output_branch ();
40fb9820
L		 6942 else if (i.tm.opcode_modifier.jumpbyte
6943 || i.tm.opcode_modifier.jumpdword)
29b0f896 6944 output_jump ();
40fb9820 6945 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6946 output_interseg_jump ();
6947 else
6948 {
6949 /* Output normal instructions here. */
6950 char *p;
6951 unsigned char *q;
47465058 6952 unsigned int j;
331d2d0d 6953 unsigned int prefix;
4dffcebc 6954
d022bddd
IT		 6955 /* Some processors fail on LOCK prefix. This options makes
6956 assembler ignore LOCK prefix and serves as a workaround. */
6957 if (omit_lock_prefix)
6958 {
6959 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6960 return;
6961 i.prefix[LOCK_PREFIX] = 0;
6962 }
6963
43234a1e
L		 6964 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6965 don't need the explicit prefix. */
6966 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6967 {
c0f3af97 6968 switch (i.tm.opcode_length)
bc4bd9ab 6969 {
c0f3af97
L		 6970 case 3:
6971 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6972 {
c0f3af97
L		 6973 prefix = (i.tm.base_opcode >> 24) & 0xff;
6974 goto check_prefix;
6975 }
6976 break;
6977 case 2:
6978 if ((i.tm.base_opcode & 0xff0000) != 0)
6979 {
6980 prefix = (i.tm.base_opcode >> 16) & 0xff;
6981 if (i.tm.cpu_flags.bitfield.cpupadlock)
6982 {
4dffcebc 6983check_prefix:
c0f3af97 6984 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6985 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6986 != REPE_PREFIX_OPCODE))
6987 add_prefix (prefix);
6988 }
6989 else
4dffcebc
L		 6990 add_prefix (prefix);
6991 }
c0f3af97
L		 6992 break;
6993 case 1:
6994 break;
6995 default:
6996 abort ();
bc4bd9ab 6997 }
c0f3af97 6998
6d19a37a 6999#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7000 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7001 R_X86_64_GOTTPOFF relocation so that linker can safely
7002 perform IE->LE optimization. */
7003 if (x86_elf_abi == X86_64_X32_ABI
7004 && i.operands == 2
7005 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7006 && i.prefix[REX_PREFIX] == 0)
7007 add_prefix (REX_OPCODE);
6d19a37a 7008#endif
cf61b747 7009
c0f3af97
L		 7010 /* The prefix bytes. */
7011 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7012 if (*q)
7013 FRAG_APPEND_1_CHAR (*q);
0f10071e 7014 }
ae5c1c7b 7015 else
c0f3af97
L		 7016 {
7017 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7018 if (*q)
7019 switch (j)
7020 {
7021 case REX_PREFIX:
7022 /* REX byte is encoded in VEX prefix. */
7023 break;
7024 case SEG_PREFIX:
7025 case ADDR_PREFIX:
7026 FRAG_APPEND_1_CHAR (*q);
7027 break;
7028 default:
7029 /* There should be no other prefixes for instructions
7030 with VEX prefix. */
7031 abort ();
7032 }
7033
43234a1e
L		 7034 /* For EVEX instructions i.vrex should become 0 after
7035 build_evex_prefix. For VEX instructions upper 16 registers
7036 aren't available, so VREX should be 0. */
7037 if (i.vrex)
7038 abort ();
c0f3af97
L		 7039 /* Now the VEX prefix. */
7040 p = frag_more (i.vex.length);
7041 for (j = 0; j < i.vex.length; j++)
7042 p[j] = i.vex.bytes[j];
7043 }
252b5132 7044
29b0f896 7045 /* Now the opcode; be careful about word order here! */
4dffcebc 7046 if (i.tm.opcode_length == 1)
29b0f896
AM		 7047 {
7048 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7049 }
7050 else
7051 {
4dffcebc 7052 switch (i.tm.opcode_length)
331d2d0d 7053 {
43234a1e
L		 7054 case 4:
7055 p = frag_more (4);
7056 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7057 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7058 break;
4dffcebc 7059 case 3:
331d2d0d
L		 7060 p = frag_more (3);
7061 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7062 break;
7063 case 2:
7064 p = frag_more (2);
7065 break;
7066 default:
7067 abort ();
7068 break;
331d2d0d 7069 }
0f10071e 7070
29b0f896
AM		 7071 /* Put out high byte first: can't use md_number_to_chars! */
7072 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7073 *p = i.tm.base_opcode & 0xff;
7074 }
3e73aa7c 7075
29b0f896 7076 /* Now the modrm byte and sib byte (if present). */
40fb9820 7077 if (i.tm.opcode_modifier.modrm)
29b0f896 7078 {
4a3523fa
L		 7079 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7080 | i.rm.reg << 3
7081 | i.rm.mode << 6));
29b0f896
AM		 7082 /* If i.rm.regmem == ESP (4)
7083 && i.rm.mode != (Register mode)
7084 && not 16 bit
7085 ==> need second modrm byte. */
7086 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7087 && i.rm.mode != 3
40fb9820 7088 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7089 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7090 | i.sib.index << 3
7091 | i.sib.scale << 6));
29b0f896 7092 }
3e73aa7c 7093
29b0f896 7094 if (i.disp_operands)
2bbd9c25 7095 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7096
29b0f896 7097 if (i.imm_operands)
2bbd9c25 7098 output_imm (insn_start_frag, insn_start_off);
29b0f896 7099 }
252b5132 7100
29b0f896
AM		 7101#ifdef DEBUG386
7102 if (flag_debug)
7103 {
7b81dfbb 7104 pi ("" /*line*/, &i);
29b0f896
AM		 7105 }
7106#endif /* DEBUG386 */
7107}
252b5132 7108
e205caa7
L		 7109/* Return the size of the displacement operand N. */
7110
7111static int
7112disp_size (unsigned int n)
7113{
7114 int size = 4;
43234a1e
L		 7115
7116 /* Vec_Disp8 has to be 8bit. */
7117 if (i.types[n].bitfield.vec_disp8)
7118 size = 1;
7119 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7120 size = 8;
7121 else if (i.types[n].bitfield.disp8)
7122 size = 1;
7123 else if (i.types[n].bitfield.disp16)
7124 size = 2;
e205caa7
L		 7125 return size;
7126}
7127
7128/* Return the size of the immediate operand N. */
7129
7130static int
7131imm_size (unsigned int n)
7132{
7133 int size = 4;
40fb9820
L		 7134 if (i.types[n].bitfield.imm64)
7135 size = 8;
7136 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7137 size = 1;
7138 else if (i.types[n].bitfield.imm16)
7139 size = 2;
e205caa7
L		 7140 return size;
7141}
7142
29b0f896 7143static void
64e74474 7144output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7145{
7146 char *p;
7147 unsigned int n;
252b5132 7148
29b0f896
AM		 7149 for (n = 0; n < i.operands; n++)
7150 {
43234a1e
L		 7151 if (i.types[n].bitfield.vec_disp8
7152 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7153 {
7154 if (i.op[n].disps->X_op == O_constant)
7155 {
e205caa7 7156 int size = disp_size (n);
43234a1e 7157 offsetT val = i.op[n].disps->X_add_number;
252b5132 7158
43234a1e
L		 7159 if (i.types[n].bitfield.vec_disp8)
7160 val >>= i.memshift;
7161 val = offset_in_range (val, size);
29b0f896
AM		 7162 p = frag_more (size);
7163 md_number_to_chars (p, val, size);
7164 }
7165 else
7166 {
f86103b7 7167 enum bfd_reloc_code_real reloc_type;
e205caa7 7168 int size = disp_size (n);
40fb9820 7169 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7170 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7171
e205caa7 7172 /* We can't have 8 bit displacement here. */
9c2799c2 7173 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7174
29b0f896
AM		 7175 /* The PC relative address is computed relative
7176 to the instruction boundary, so in case immediate
7177 fields follows, we need to adjust the value. */
7178 if (pcrel && i.imm_operands)
7179 {
29b0f896 7180 unsigned int n1;
e205caa7 7181 int sz = 0;
252b5132 7182
29b0f896 7183 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7184 if (operand_type_check (i.types[n1], imm))
252b5132 7185 {
e205caa7
L		 7186 /* Only one immediate is allowed for PC
7187 relative address. */
9c2799c2 7188 gas_assert (sz == 0);
e205caa7
L		 7189 sz = imm_size (n1);
7190 i.op[n].disps->X_add_number -= sz;
252b5132 7191 }
29b0f896 7192 /* We should find the immediate. */
9c2799c2 7193 gas_assert (sz != 0);
29b0f896 7194 }
520dc8e8 7195
29b0f896 7196 p = frag_more (size);
d258b828 7197 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7198 if (GOT_symbol
2bbd9c25 7199 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7200 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7201 || reloc_type == BFD_RELOC_X86_64_32S
7202 || (reloc_type == BFD_RELOC_64
7203 && object_64bit))
d6ab8113
JB		 7204 && (i.op[n].disps->X_op == O_symbol
7205 || (i.op[n].disps->X_op == O_add
7206 && ((symbol_get_value_expression
7207 (i.op[n].disps->X_op_symbol)->X_op)
7208 == O_subtract))))
7209 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7210 {
7211 offsetT add;
7212
7213 if (insn_start_frag == frag_now)
7214 add = (p - frag_now->fr_literal) - insn_start_off;
7215 else
7216 {
7217 fragS *fr;
7218
7219 add = insn_start_frag->fr_fix - insn_start_off;
7220 for (fr = insn_start_frag->fr_next;
7221 fr && fr != frag_now; fr = fr->fr_next)
7222 add += fr->fr_fix;
7223 add += p - frag_now->fr_literal;
7224 }
7225
4fa24527 7226 if (!object_64bit)
7b81dfbb
AJ		 7227 {
7228 reloc_type = BFD_RELOC_386_GOTPC;
7229 i.op[n].imms->X_add_number += add;
7230 }
7231 else if (reloc_type == BFD_RELOC_64)
7232 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7233 else
7b81dfbb
AJ		 7234 /* Don't do the adjustment for x86-64, as there
7235 the pcrel addressing is relative to the _next_
7236 insn, and that is taken care of in other code. */
d6ab8113 7237 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7238 }
062cd5e7 7239 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7240 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7241 }
7242 }
7243 }
7244}
252b5132 7245
29b0f896 7246static void
64e74474 7247output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7248{
7249 char *p;
7250 unsigned int n;
252b5132 7251
29b0f896
AM		 7252 for (n = 0; n < i.operands; n++)
7253 {
43234a1e
L		 7254 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7255 if (i.rounding && (int) n == i.rounding->operand)
7256 continue;
7257
40fb9820 7258 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7259 {
7260 if (i.op[n].imms->X_op == O_constant)
7261 {
e205caa7 7262 int size = imm_size (n);
29b0f896 7263 offsetT val;
b4cac588 7264
29b0f896
AM		 7265 val = offset_in_range (i.op[n].imms->X_add_number,
7266 size);
7267 p = frag_more (size);
7268 md_number_to_chars (p, val, size);
7269 }
7270 else
7271 {
7272 /* Not absolute_section.
7273 Need a 32-bit fixup (don't support 8bit
7274 non-absolute imms). Try to support other
7275 sizes ... */
f86103b7 7276 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7277 int size = imm_size (n);
7278 int sign;
29b0f896 7279
40fb9820 7280 if (i.types[n].bitfield.imm32s
a7d61044 7281 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7282 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7283 sign = 1;
e205caa7
L		 7284 else
7285 sign = 0;
520dc8e8 7286
29b0f896 7287 p = frag_more (size);
d258b828 7288 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7289
2bbd9c25
JJ		 7290 /* This is tough to explain. We end up with this one if we
7291 * have operands that look like
7292 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7293 * obtain the absolute address of the GOT, and it is strongly
7294 * preferable from a performance point of view to avoid using
7295 * a runtime relocation for this. The actual sequence of
7296 * instructions often look something like:
7297 *
7298 * call .L66
7299 * .L66:
7300 * popl %ebx
7301 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7302 *
7303 * The call and pop essentially return the absolute address
7304 * of the label .L66 and store it in %ebx. The linker itself
7305 * will ultimately change the first operand of the addl so
7306 * that %ebx points to the GOT, but to keep things simple, the
7307 * .o file must have this operand set so that it generates not
7308 * the absolute address of .L66, but the absolute address of
7309 * itself. This allows the linker itself simply treat a GOTPC
7310 * relocation as asking for a pcrel offset to the GOT to be
7311 * added in, and the addend of the relocation is stored in the
7312 * operand field for the instruction itself.
7313 *
7314 * Our job here is to fix the operand so that it would add
7315 * the correct offset so that %ebx would point to itself. The
7316 * thing that is tricky is that .-.L66 will point to the
7317 * beginning of the instruction, so we need to further modify
7318 * the operand so that it will point to itself. There are
7319 * other cases where you have something like:
7320 *
7321 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7322 *
7323 * and here no correction would be required. Internally in
7324 * the assembler we treat operands of this form as not being
7325 * pcrel since the '.' is explicitly mentioned, and I wonder
7326 * whether it would simplify matters to do it this way. Who
7327 * knows. In earlier versions of the PIC patches, the
7328 * pcrel_adjust field was used to store the correction, but
7329 * since the expression is not pcrel, I felt it would be
7330 * confusing to do it this way. */
7331
d6ab8113 7332 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7333 || reloc_type == BFD_RELOC_X86_64_32S
7334 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7335 && GOT_symbol
7336 && GOT_symbol == i.op[n].imms->X_add_symbol
7337 && (i.op[n].imms->X_op == O_symbol
7338 || (i.op[n].imms->X_op == O_add
7339 && ((symbol_get_value_expression
7340 (i.op[n].imms->X_op_symbol)->X_op)
7341 == O_subtract))))
7342 {
2bbd9c25
JJ		 7343 offsetT add;
7344
7345 if (insn_start_frag == frag_now)
7346 add = (p - frag_now->fr_literal) - insn_start_off;
7347 else
7348 {
7349 fragS *fr;
7350
7351 add = insn_start_frag->fr_fix - insn_start_off;
7352 for (fr = insn_start_frag->fr_next;
7353 fr && fr != frag_now; fr = fr->fr_next)
7354 add += fr->fr_fix;
7355 add += p - frag_now->fr_literal;
7356 }
7357
4fa24527 7358 if (!object_64bit)
d6ab8113 7359 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7360 else if (size == 4)
d6ab8113 7361 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7362 else if (size == 8)
7363 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7364 i.op[n].imms->X_add_number += add;
29b0f896 7365 }
29b0f896
AM		 7366 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7367 i.op[n].imms, 0, reloc_type);
7368 }
7369 }
7370 }
252b5132
RH		 7371}
7372\f
d182319b
JB		 7373/* x86_cons_fix_new is called via the expression parsing code when a
7374 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7375static int cons_sign = -1;
7376
7377void
e3bb37b5 7378x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7379 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7380{
d258b828 7381 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7382
7383#ifdef TE_PE
7384 if (exp->X_op == O_secrel)
7385 {
7386 exp->X_op = O_symbol;
7387 r = BFD_RELOC_32_SECREL;
7388 }
7389#endif
7390
7391 fix_new_exp (frag, off, len, exp, 0, r);
7392}
7393
357d1bd8
L		 7394/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7395 purpose of the `.dc.a' internal pseudo-op. */
7396
7397int
7398x86_address_bytes (void)
7399{
7400 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7401 return 4;
7402 return stdoutput->arch_info->bits_per_address / 8;
7403}
7404
d382c579
TG		 7405#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7406 || defined (LEX_AT)
d258b828 7407# define lex_got(reloc, adjust, types) NULL
718ddfc0 7408#else
f3c180ae
AM		 7409/* Parse operands of the form
7410 <symbol>@GOTOFF+<nnn>
7411 and similar .plt or .got references.
7412
7413 If we find one, set up the correct relocation in RELOC and copy the
7414 input string, minus the `@GOTOFF' into a malloc'd buffer for
7415 parsing by the calling routine. Return this buffer, and if ADJUST
7416 is non-null set it to the length of the string we removed from the
7417 input line. Otherwise return NULL. */
7418static char *
91d6fa6a 7419lex_got (enum bfd_reloc_code_real *rel,
64e74474 7420 int *adjust,
d258b828 7421 i386_operand_type *types)
f3c180ae 7422{
7b81dfbb
AJ		 7423 /* Some of the relocations depend on the size of what field is to
7424 be relocated. But in our callers i386_immediate and i386_displacement
7425 we don't yet know the operand size (this will be set by insn
7426 matching). Hence we record the word32 relocation here,
7427 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7428 static const struct {
7429 const char *str;
cff8d58a 7430 int len;
4fa24527 7431 const enum bfd_reloc_code_real rel[2];
40fb9820 7432 const i386_operand_type types64;
f3c180ae 7433 } gotrel[] = {
8ce3d284 7434#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7435 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7436 BFD_RELOC_SIZE32 },
7437 OPERAND_TYPE_IMM32_64 },
8ce3d284 7438#endif
cff8d58a
L		 7439 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7440 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7441 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7442 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7443 BFD_RELOC_X86_64_PLT32 },
40fb9820 7444 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7445 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7446 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7447 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7448 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7449 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7450 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7451 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7452 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7453 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7454 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7455 BFD_RELOC_X86_64_TLSGD },
40fb9820 7456 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7457 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7458 _dummy_first_bfd_reloc_code_real },
40fb9820 7459 OPERAND_TYPE_NONE },
cff8d58a
L		 7460 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7461 BFD_RELOC_X86_64_TLSLD },
40fb9820 7462 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7463 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7464 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7465 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7466 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7467 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7468 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7469 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7470 _dummy_first_bfd_reloc_code_real },
40fb9820 7471 OPERAND_TYPE_NONE },
cff8d58a
L		 7472 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7473 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7474 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7475 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7476 _dummy_first_bfd_reloc_code_real },
40fb9820 7477 OPERAND_TYPE_NONE },
cff8d58a
L		 7478 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7479 _dummy_first_bfd_reloc_code_real },
40fb9820 7480 OPERAND_TYPE_NONE },
cff8d58a
L		 7481 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7482 BFD_RELOC_X86_64_GOT32 },
40fb9820 7483 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7484 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7485 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7486 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7487 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7488 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7489 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7490 };
7491 char *cp;
7492 unsigned int j;
7493
d382c579 7494#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7495 if (!IS_ELF)
7496 return NULL;
d382c579 7497#endif
718ddfc0 7498
f3c180ae 7499 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7500 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7501 return NULL;
7502
47465058 7503 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7504 {
cff8d58a 7505 int len = gotrel[j].len;
28f81592 7506 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7507 {
4fa24527 7508 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7509 {
28f81592
AM		 7510 int first, second;
7511 char *tmpbuf, *past_reloc;
f3c180ae 7512
91d6fa6a 7513 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7514
3956db08
JB		 7515 if (types)
7516 {
7517 if (flag_code != CODE_64BIT)
40fb9820
L		 7518 {
7519 types->bitfield.imm32 = 1;
7520 types->bitfield.disp32 = 1;
7521 }
3956db08
JB		 7522 else
7523 *types = gotrel[j].types64;
7524 }
7525
8fd4256d 7526 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7527 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7528
28f81592 7529 /* The length of the first part of our input line. */
f3c180ae 7530 first = cp - input_line_pointer;
28f81592
AM		 7531
7532 /* The second part goes from after the reloc token until
67c11a9b 7533 (and including) an end_of_line char or comma. */
28f81592 7534 past_reloc = cp + 1 + len;
67c11a9b
AM		 7535 cp = past_reloc;
7536 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7537 ++cp;
7538 second = cp + 1 - past_reloc;
28f81592
AM		 7539
7540 /* Allocate and copy string. The trailing NUL shouldn't
7541 be necessary, but be safe. */
1e9cc1c2 7542 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7543 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7544 if (second != 0 && *past_reloc != ' ')
7545 /* Replace the relocation token with ' ', so that
7546 errors like foo@GOTOFF1 will be detected. */
7547 tmpbuf[first++] = ' ';
af89796a
L		 7548 else
7549 /* Increment length by 1 if the relocation token is
7550 removed. */
7551 len++;
7552 if (adjust)
7553 *adjust = len;
0787a12d
AM		 7554 memcpy (tmpbuf + first, past_reloc, second);
7555 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7556 return tmpbuf;
7557 }
7558
4fa24527
JB		 7559 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7560 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7561 return NULL;
7562 }
7563 }
7564
7565 /* Might be a symbol version string. Don't as_bad here. */
7566 return NULL;
7567}
4e4f7c87 7568#endif
f3c180ae 7569
a988325c
NC		 7570#ifdef TE_PE
7571#ifdef lex_got
7572#undef lex_got
7573#endif
7574/* Parse operands of the form
7575 <symbol>@SECREL32+<nnn>
7576
7577 If we find one, set up the correct relocation in RELOC and copy the
7578 input string, minus the `@SECREL32' into a malloc'd buffer for
7579 parsing by the calling routine. Return this buffer, and if ADJUST
7580 is non-null set it to the length of the string we removed from the
34bca508
L		 7581 input line. Otherwise return NULL.
7582
a988325c
NC		 7583 This function is copied from the ELF version above adjusted for PE targets. */
7584
7585static char *
7586lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7587 int *adjust ATTRIBUTE_UNUSED,
d258b828 7588 i386_operand_type *types)
a988325c
NC		 7589{
7590 static const struct
7591 {
7592 const char *str;
7593 int len;
7594 const enum bfd_reloc_code_real rel[2];
7595 const i386_operand_type types64;
7596 }
7597 gotrel[] =
7598 {
7599 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7600 BFD_RELOC_32_SECREL },
7601 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7602 };
7603
7604 char *cp;
7605 unsigned j;
7606
7607 for (cp = input_line_pointer; *cp != '@'; cp++)
7608 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7609 return NULL;
7610
7611 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7612 {
7613 int len = gotrel[j].len;
7614
7615 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7616 {
7617 if (gotrel[j].rel[object_64bit] != 0)
7618 {
7619 int first, second;
7620 char *tmpbuf, *past_reloc;
7621
7622 *rel = gotrel[j].rel[object_64bit];
7623 if (adjust)
7624 *adjust = len;
7625
7626 if (types)
7627 {
7628 if (flag_code != CODE_64BIT)
7629 {
7630 types->bitfield.imm32 = 1;
7631 types->bitfield.disp32 = 1;
7632 }
7633 else
7634 *types = gotrel[j].types64;
7635 }
7636
7637 /* The length of the first part of our input line. */
7638 first = cp - input_line_pointer;
7639
7640 /* The second part goes from after the reloc token until
7641 (and including) an end_of_line char or comma. */
7642 past_reloc = cp + 1 + len;
7643 cp = past_reloc;
7644 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7645 ++cp;
7646 second = cp + 1 - past_reloc;
7647
7648 /* Allocate and copy string. The trailing NUL shouldn't
7649 be necessary, but be safe. */
7650 tmpbuf = (char *) xmalloc (first + second + 2);
7651 memcpy (tmpbuf, input_line_pointer, first);
7652 if (second != 0 && *past_reloc != ' ')
7653 /* Replace the relocation token with ' ', so that
7654 errors like foo@SECLREL321 will be detected. */
7655 tmpbuf[first++] = ' ';
7656 memcpy (tmpbuf + first, past_reloc, second);
7657 tmpbuf[first + second] = '\0';
7658 return tmpbuf;
7659 }
7660
7661 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7662 gotrel[j].str, 1 << (5 + object_64bit));
7663 return NULL;
7664 }
7665 }
7666
7667 /* Might be a symbol version string. Don't as_bad here. */
7668 return NULL;
7669}
7670
7671#endif /* TE_PE */
7672
62ebcb5c 7673bfd_reloc_code_real_type
e3bb37b5 7674x86_cons (expressionS *exp, int size)
f3c180ae 7675{
62ebcb5c
AM		 7676 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7677
ee86248c
JB		 7678 intel_syntax = -intel_syntax;
7679
3c7b9c2c 7680 exp->X_md = 0;
4fa24527 7681 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7682 {
7683 /* Handle @GOTOFF and the like in an expression. */
7684 char *save;
7685 char *gotfree_input_line;
4a57f2cf 7686 int adjust = 0;
f3c180ae
AM		 7687
7688 save = input_line_pointer;
d258b828 7689 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7690 if (gotfree_input_line)
7691 input_line_pointer = gotfree_input_line;
7692
7693 expression (exp);
7694
7695 if (gotfree_input_line)
7696 {
7697 /* expression () has merrily parsed up to the end of line,
7698 or a comma - in the wrong buffer. Transfer how far
7699 input_line_pointer has moved to the right buffer. */
7700 input_line_pointer = (save
7701 + (input_line_pointer - gotfree_input_line)
7702 + adjust);
7703 free (gotfree_input_line);
3992d3b7
AM		 7704 if (exp->X_op == O_constant
7705 || exp->X_op == O_absent
7706 || exp->X_op == O_illegal
0398aac5 7707 || exp->X_op == O_register
3992d3b7
AM		 7708 || exp->X_op == O_big)
7709 {
7710 char c = *input_line_pointer;
7711 *input_line_pointer = 0;
7712 as_bad (_("missing or invalid expression `%s'"), save);
7713 *input_line_pointer = c;
7714 }
f3c180ae
AM		 7715 }
7716 }
7717 else
7718 expression (exp);
ee86248c
JB		 7719
7720 intel_syntax = -intel_syntax;
7721
7722 if (intel_syntax)
7723 i386_intel_simplify (exp);
62ebcb5c
AM		 7724
7725 return got_reloc;
f3c180ae 7726}
f3c180ae 7727
9f32dd5b
L		 7728static void
7729signed_cons (int size)
6482c264 7730{
d182319b
JB		 7731 if (flag_code == CODE_64BIT)
7732 cons_sign = 1;
7733 cons (size);
7734 cons_sign = -1;
6482c264
NC		 7735}
7736
d182319b 7737#ifdef TE_PE
6482c264 7738static void
7016a5d5 7739pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7740{
7741 expressionS exp;
7742
7743 do
7744 {
7745 expression (&exp);
7746 if (exp.X_op == O_symbol)
7747 exp.X_op = O_secrel;
7748
7749 emit_expr (&exp, 4);
7750 }
7751 while (*input_line_pointer++ == ',');
7752
7753 input_line_pointer--;
7754 demand_empty_rest_of_line ();
7755}
6482c264
NC		 7756#endif
7757
43234a1e
L		 7758/* Handle Vector operations. */
7759
7760static char *
7761check_VecOperations (char *op_string, char *op_end)
7762{
7763 const reg_entry *mask;
7764 const char *saved;
7765 char *end_op;
7766
7767 while (*op_string
7768 && (op_end == NULL || op_string < op_end))
7769 {
7770 saved = op_string;
7771 if (*op_string == '{')
7772 {
7773 op_string++;
7774
7775 /* Check broadcasts. */
7776 if (strncmp (op_string, "1to", 3) == 0)
7777 {
7778 int bcst_type;
7779
7780 if (i.broadcast)
7781 goto duplicated_vec_op;
7782
7783 op_string += 3;
7784 if (*op_string == '8')
7785 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7786 else if (*op_string == '4')
7787 bcst_type = BROADCAST_1TO4;
7788 else if (*op_string == '2')
7789 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7790 else if (*op_string == '1'
7791 && *(op_string+1) == '6')
7792 {
7793 bcst_type = BROADCAST_1TO16;
7794 op_string++;
7795 }
7796 else
7797 {
7798 as_bad (_("Unsupported broadcast: `%s'"), saved);
7799 return NULL;
7800 }
7801 op_string++;
7802
7803 broadcast_op.type = bcst_type;
7804 broadcast_op.operand = this_operand;
7805 i.broadcast = &broadcast_op;
7806 }
7807 /* Check masking operation. */
7808 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7809 {
7810 /* k0 can't be used for write mask. */
7811 if (mask->reg_num == 0)
7812 {
7813 as_bad (_("`%s' can't be used for write mask"),
7814 op_string);
7815 return NULL;
7816 }
7817
7818 if (!i.mask)
7819 {
7820 mask_op.mask = mask;
7821 mask_op.zeroing = 0;
7822 mask_op.operand = this_operand;
7823 i.mask = &mask_op;
7824 }
7825 else
7826 {
7827 if (i.mask->mask)
7828 goto duplicated_vec_op;
7829
7830 i.mask->mask = mask;
7831
7832 /* Only "{z}" is allowed here. No need to check
7833 zeroing mask explicitly. */
7834 if (i.mask->operand != this_operand)
7835 {
7836 as_bad (_("invalid write mask `%s'"), saved);
7837 return NULL;
7838 }
7839 }
7840
7841 op_string = end_op;
7842 }
7843 /* Check zeroing-flag for masking operation. */
7844 else if (*op_string == 'z')
7845 {
7846 if (!i.mask)
7847 {
7848 mask_op.mask = NULL;
7849 mask_op.zeroing = 1;
7850 mask_op.operand = this_operand;
7851 i.mask = &mask_op;
7852 }
7853 else
7854 {
7855 if (i.mask->zeroing)
7856 {
7857 duplicated_vec_op:
7858 as_bad (_("duplicated `%s'"), saved);
7859 return NULL;
7860 }
7861
7862 i.mask->zeroing = 1;
7863
7864 /* Only "{%k}" is allowed here. No need to check mask
7865 register explicitly. */
7866 if (i.mask->operand != this_operand)
7867 {
7868 as_bad (_("invalid zeroing-masking `%s'"),
7869 saved);
7870 return NULL;
7871 }
7872 }
7873
7874 op_string++;
7875 }
7876 else
7877 goto unknown_vec_op;
7878
7879 if (*op_string != '}')
7880 {
7881 as_bad (_("missing `}' in `%s'"), saved);
7882 return NULL;
7883 }
7884 op_string++;
7885 continue;
7886 }
7887 unknown_vec_op:
7888 /* We don't know this one. */
7889 as_bad (_("unknown vector operation: `%s'"), saved);
7890 return NULL;
7891 }
7892
7893 return op_string;
7894}
7895
252b5132 7896static int
70e41ade 7897i386_immediate (char *imm_start)
252b5132
RH		 7898{
7899 char *save_input_line_pointer;
f3c180ae 7900 char *gotfree_input_line;
252b5132 7901 segT exp_seg = 0;
47926f60 7902 expressionS *exp;
40fb9820
L		 7903 i386_operand_type types;
7904
0dfbf9d7 7905 operand_type_set (&types, ~0);
252b5132
RH		 7906
7907 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7908 {
31b2323c
L		 7909 as_bad (_("at most %d immediate operands are allowed"),
7910 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7911 return 0;
7912 }
7913
7914 exp = &im_expressions[i.imm_operands++];
520dc8e8 7915 i.op[this_operand].imms = exp;
252b5132
RH		 7916
7917 if (is_space_char (*imm_start))
7918 ++imm_start;
7919
7920 save_input_line_pointer = input_line_pointer;
7921 input_line_pointer = imm_start;
7922
d258b828 7923 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7924 if (gotfree_input_line)
7925 input_line_pointer = gotfree_input_line;
252b5132
RH		 7926
7927 exp_seg = expression (exp);
7928
83183c0c 7929 SKIP_WHITESPACE ();
43234a1e
L		 7930
7931 /* Handle vector operations. */
7932 if (*input_line_pointer == '{')
7933 {
7934 input_line_pointer = check_VecOperations (input_line_pointer,
7935 NULL);
7936 if (input_line_pointer == NULL)
7937 return 0;
7938 }
7939
252b5132 7940 if (*input_line_pointer)
f3c180ae 7941 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7942
7943 input_line_pointer = save_input_line_pointer;
f3c180ae 7944 if (gotfree_input_line)
ee86248c
JB		 7945 {
7946 free (gotfree_input_line);
7947
7948 if (exp->X_op == O_constant || exp->X_op == O_register)
7949 exp->X_op = O_illegal;
7950 }
7951
7952 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7953}
252b5132 7954
ee86248c
JB		 7955static int
7956i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7957 i386_operand_type types, const char *imm_start)
7958{
7959 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7960 {
313c53d1
L		 7961 if (imm_start)
7962 as_bad (_("missing or invalid immediate expression `%s'"),
7963 imm_start);
3992d3b7 7964 return 0;
252b5132 7965 }
3e73aa7c 7966 else if (exp->X_op == O_constant)
252b5132 7967 {
47926f60 7968 /* Size it properly later. */
40fb9820 7969 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7970 /* If not 64bit, sign extend val. */
7971 if (flag_code != CODE_64BIT
4eed87de
AM		 7972 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7973 exp->X_add_number
7974 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7975 }
4c63da97 7976#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7977 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7978 && exp_seg != absolute_section
47926f60 7979 && exp_seg != text_section
24eab124
AM		 7980 && exp_seg != data_section
7981 && exp_seg != bss_section
7982 && exp_seg != undefined_section
f86103b7 7983 && !bfd_is_com_section (exp_seg))
252b5132 7984 {
d0b47220 7985 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7986 return 0;
7987 }
7988#endif
a841bdf5 7989 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7990 {
313c53d1
L		 7991 if (imm_start)
7992 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7993 return 0;
7994 }
252b5132
RH		 7995 else
7996 {
7997 /* This is an address. The size of the address will be
24eab124 7998 determined later, depending on destination register,
3e73aa7c 7999 suffix, or the default for the section. */
40fb9820
L		 8000 i.types[this_operand].bitfield.imm8 = 1;
8001 i.types[this_operand].bitfield.imm16 = 1;
8002 i.types[this_operand].bitfield.imm32 = 1;
8003 i.types[this_operand].bitfield.imm32s = 1;
8004 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8005 i.types[this_operand] = operand_type_and (i.types[this_operand],
8006 types);
252b5132
RH		 8007 }
8008
8009 return 1;
8010}
8011
551c1ca1 8012static char *
e3bb37b5 8013i386_scale (char *scale)
252b5132 8014{
551c1ca1
AM		 8015 offsetT val;
8016 char *save = input_line_pointer;
252b5132 8017
551c1ca1
AM		 8018 input_line_pointer = scale;
8019 val = get_absolute_expression ();
8020
8021 switch (val)
252b5132 8022 {
551c1ca1 8023 case 1:
252b5132
RH		 8024 i.log2_scale_factor = 0;
8025 break;
551c1ca1 8026 case 2:
252b5132
RH		 8027 i.log2_scale_factor = 1;
8028 break;
551c1ca1 8029 case 4:
252b5132
RH		 8030 i.log2_scale_factor = 2;
8031 break;
551c1ca1 8032 case 8:
252b5132
RH		 8033 i.log2_scale_factor = 3;
8034 break;
8035 default:
a724f0f4
JB		 8036 {
8037 char sep = *input_line_pointer;
8038
8039 *input_line_pointer = '\0';
8040 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8041 scale);
8042 *input_line_pointer = sep;
8043 input_line_pointer = save;
8044 return NULL;
8045 }
252b5132 8046 }
29b0f896 8047 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8048 {
8049 as_warn (_("scale factor of %d without an index register"),
24eab124 8050 1 << i.log2_scale_factor);
252b5132 8051 i.log2_scale_factor = 0;
252b5132 8052 }
551c1ca1
AM		 8053 scale = input_line_pointer;
8054 input_line_pointer = save;
8055 return scale;
252b5132
RH		 8056}
8057
252b5132 8058static int
e3bb37b5 8059i386_displacement (char *disp_start, char *disp_end)
252b5132 8060{
29b0f896 8061 expressionS *exp;
252b5132
RH		 8062 segT exp_seg = 0;
8063 char *save_input_line_pointer;
f3c180ae 8064 char *gotfree_input_line;
40fb9820
L		 8065 int override;
8066 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8067 int ret;
252b5132 8068
31b2323c
L		 8069 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8070 {
8071 as_bad (_("at most %d displacement operands are allowed"),
8072 MAX_MEMORY_OPERANDS);
8073 return 0;
8074 }
8075
0dfbf9d7 8076 operand_type_set (&bigdisp, 0);
40fb9820
L		 8077 if ((i.types[this_operand].bitfield.jumpabsolute)
8078 || (!current_templates->start->opcode_modifier.jump
8079 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8080 {
40fb9820 8081 bigdisp.bitfield.disp32 = 1;
e05278af 8082 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8083 if (flag_code == CODE_64BIT)
8084 {
8085 if (!override)
8086 {
8087 bigdisp.bitfield.disp32s = 1;
8088 bigdisp.bitfield.disp64 = 1;
8089 }
8090 }
8091 else if ((flag_code == CODE_16BIT) ^ override)
8092 {
8093 bigdisp.bitfield.disp32 = 0;
8094 bigdisp.bitfield.disp16 = 1;
8095 }
e05278af
JB		 8096 }
8097 else
8098 {
8099 /* For PC-relative branches, the width of the displacement
8100 is dependent upon data size, not address size. */
e05278af 8101 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8102 if (flag_code == CODE_64BIT)
8103 {
8104 if (override || i.suffix == WORD_MNEM_SUFFIX)
8105 bigdisp.bitfield.disp16 = 1;
8106 else
8107 {
8108 bigdisp.bitfield.disp32 = 1;
8109 bigdisp.bitfield.disp32s = 1;
8110 }
8111 }
8112 else
e05278af
JB		 8113 {
8114 if (!override)
8115 override = (i.suffix == (flag_code != CODE_16BIT
8116 ? WORD_MNEM_SUFFIX
8117 : LONG_MNEM_SUFFIX));
40fb9820
L		 8118 bigdisp.bitfield.disp32 = 1;
8119 if ((flag_code == CODE_16BIT) ^ override)
8120 {
8121 bigdisp.bitfield.disp32 = 0;
8122 bigdisp.bitfield.disp16 = 1;
8123 }
e05278af 8124 }
e05278af 8125 }
c6fb90c8
L		 8126 i.types[this_operand] = operand_type_or (i.types[this_operand],
8127 bigdisp);
252b5132
RH		 8128
8129 exp = &disp_expressions[i.disp_operands];
520dc8e8 8130 i.op[this_operand].disps = exp;
252b5132
RH		 8131 i.disp_operands++;
8132 save_input_line_pointer = input_line_pointer;
8133 input_line_pointer = disp_start;
8134 END_STRING_AND_SAVE (disp_end);
8135
8136#ifndef GCC_ASM_O_HACK
8137#define GCC_ASM_O_HACK 0
8138#endif
8139#if GCC_ASM_O_HACK
8140 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8141 if (i.types[this_operand].bitfield.baseIndex
24eab124 8142 && displacement_string_end[-1] == '+')
252b5132
RH		 8143 {
8144 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8145 constraint within gcc asm statements.
8146 For instance:
8147
8148 #define _set_tssldt_desc(n,addr,limit,type) \
8149 __asm__ __volatile__ ( \
8150 "movw %w2,%0\n\t" \
8151 "movw %w1,2+%0\n\t" \
8152 "rorl $16,%1\n\t" \
8153 "movb %b1,4+%0\n\t" \
8154 "movb %4,5+%0\n\t" \
8155 "movb $0,6+%0\n\t" \
8156 "movb %h1,7+%0\n\t" \
8157 "rorl $16,%1" \
8158 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8159
8160 This works great except that the output assembler ends
8161 up looking a bit weird if it turns out that there is
8162 no offset. You end up producing code that looks like:
8163
8164 #APP
8165 movw $235,(%eax)
8166 movw %dx,2+(%eax)
8167 rorl $16,%edx
8168 movb %dl,4+(%eax)
8169 movb $137,5+(%eax)
8170 movb $0,6+(%eax)
8171 movb %dh,7+(%eax)
8172 rorl $16,%edx
8173 #NO_APP
8174
47926f60 8175 So here we provide the missing zero. */
24eab124
AM		 8176
8177 *displacement_string_end = '0';
252b5132
RH		 8178 }
8179#endif
d258b828 8180 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8181 if (gotfree_input_line)
8182 input_line_pointer = gotfree_input_line;
252b5132 8183
24eab124 8184 exp_seg = expression (exp);
252b5132 8185
636c26b0
AM		 8186 SKIP_WHITESPACE ();
8187 if (*input_line_pointer)
8188 as_bad (_("junk `%s' after expression"), input_line_pointer);
8189#if GCC_ASM_O_HACK
8190 RESTORE_END_STRING (disp_end + 1);
8191#endif
636c26b0 8192 input_line_pointer = save_input_line_pointer;
636c26b0 8193 if (gotfree_input_line)
ee86248c
JB		 8194 {
8195 free (gotfree_input_line);
8196
8197 if (exp->X_op == O_constant || exp->X_op == O_register)
8198 exp->X_op = O_illegal;
8199 }
8200
8201 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8202
8203 RESTORE_END_STRING (disp_end);
8204
8205 return ret;
8206}
8207
8208static int
8209i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8210 i386_operand_type types, const char *disp_start)
8211{
8212 i386_operand_type bigdisp;
8213 int ret = 1;
636c26b0 8214
24eab124
AM		 8215 /* We do this to make sure that the section symbol is in
8216 the symbol table. We will ultimately change the relocation
47926f60 8217 to be relative to the beginning of the section. */
1ae12ab7 8218 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8219 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8220 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8221 {
636c26b0 8222 if (exp->X_op != O_symbol)
3992d3b7 8223 goto inv_disp;
636c26b0 8224
e5cb08ac 8225 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8226 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8227 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8228 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8229 exp->X_op = O_subtract;
8230 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8231 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8232 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8233 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8234 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8235 else
29b0f896 8236 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8237 }
252b5132 8238
3992d3b7
AM		 8239 else if (exp->X_op == O_absent
8240 || exp->X_op == O_illegal
ee86248c 8241 || exp->X_op == O_big)
2daf4fd8 8242 {
3992d3b7
AM		 8243 inv_disp:
8244 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8245 disp_start);
3992d3b7 8246 ret = 0;
2daf4fd8
AM		 8247 }
8248
0e1147d9
L		 8249 else if (flag_code == CODE_64BIT
8250 && !i.prefix[ADDR_PREFIX]
8251 && exp->X_op == O_constant)
8252 {
8253 /* Since displacement is signed extended to 64bit, don't allow
8254 disp32 and turn off disp32s if they are out of range. */
8255 i.types[this_operand].bitfield.disp32 = 0;
8256 if (!fits_in_signed_long (exp->X_add_number))
8257 {
8258 i.types[this_operand].bitfield.disp32s = 0;
8259 if (i.types[this_operand].bitfield.baseindex)
8260 {
8261 as_bad (_("0x%lx out range of signed 32bit displacement"),
8262 (long) exp->X_add_number);
8263 ret = 0;
8264 }
8265 }
8266 }
8267
4c63da97 8268#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8269 else if (exp->X_op != O_constant
8270 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8271 && exp_seg != absolute_section
8272 && exp_seg != text_section
8273 && exp_seg != data_section
8274 && exp_seg != bss_section
8275 && exp_seg != undefined_section
8276 && !bfd_is_com_section (exp_seg))
24eab124 8277 {
d0b47220 8278 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8279 ret = 0;
24eab124 8280 }
252b5132 8281#endif
3956db08 8282
40fb9820
L		 8283 /* Check if this is a displacement only operand. */
8284 bigdisp = i.types[this_operand];
8285 bigdisp.bitfield.disp8 = 0;
8286 bigdisp.bitfield.disp16 = 0;
8287 bigdisp.bitfield.disp32 = 0;
8288 bigdisp.bitfield.disp32s = 0;
8289 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8290 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8291 i.types[this_operand] = operand_type_and (i.types[this_operand],
8292 types);
3956db08 8293
3992d3b7 8294 return ret;
252b5132
RH		 8295}
8296
eecb386c 8297/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8298 Return 1 on success, 0 on a failure. */
8299
252b5132 8300static int
e3bb37b5 8301i386_index_check (const char *operand_string)
252b5132 8302{
fc0763e6 8303 const char *kind = "base/index";
be05d201
L		 8304 enum flag_code addr_mode;
8305
8306 if (i.prefix[ADDR_PREFIX])
8307 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8308 else
8309 {
8310 addr_mode = flag_code;
8311
24eab124 8312#if INFER_ADDR_PREFIX
be05d201
L		 8313 if (i.mem_operands == 0)
8314 {
8315 /* Infer address prefix from the first memory operand. */
8316 const reg_entry *addr_reg = i.base_reg;
8317
8318 if (addr_reg == NULL)
8319 addr_reg = i.index_reg;
eecb386c 8320
be05d201
L		 8321 if (addr_reg)
8322 {
8323 if (addr_reg->reg_num == RegEip
8324 || addr_reg->reg_num == RegEiz
8325 || addr_reg->reg_type.bitfield.reg32)
8326 addr_mode = CODE_32BIT;
8327 else if (flag_code != CODE_64BIT
8328 && addr_reg->reg_type.bitfield.reg16)
8329 addr_mode = CODE_16BIT;
8330
8331 if (addr_mode != flag_code)
8332 {
8333 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8334 i.prefixes += 1;
8335 /* Change the size of any displacement too. At most one
8336 of Disp16 or Disp32 is set.
8337 FIXME. There doesn't seem to be any real need for
8338 separate Disp16 and Disp32 flags. The same goes for
8339 Imm16 and Imm32. Removing them would probably clean
8340 up the code quite a lot. */
8341 if (flag_code != CODE_64BIT
8342 && (i.types[this_operand].bitfield.disp16
8343 || i.types[this_operand].bitfield.disp32))
8344 i.types[this_operand]
8345 = operand_type_xor (i.types[this_operand], disp16_32);
8346 }
8347 }
8348 }
24eab124 8349#endif
be05d201
L		 8350 }
8351
fc0763e6
JB		 8352 if (current_templates->start->opcode_modifier.isstring
8353 && !current_templates->start->opcode_modifier.immext
8354 && (current_templates->end[-1].opcode_modifier.isstring
8355 || i.mem_operands))
8356 {
8357 /* Memory operands of string insns are special in that they only allow
8358 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8359 const reg_entry *expected_reg;
8360 static const char *di_si[][2] =
8361 {
8362 { "esi", "edi" },
8363 { "si", "di" },
8364 { "rsi", "rdi" }
8365 };
8366 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8367
8368 kind = "string address";
8369
8370 if (current_templates->start->opcode_modifier.w)
8371 {
8372 i386_operand_type type = current_templates->end[-1].operand_types[0];
8373
8374 if (!type.bitfield.baseindex
8375 || ((!i.mem_operands != !intel_syntax)
8376 && current_templates->end[-1].operand_types[1]
8377 .bitfield.baseindex))
8378 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8379 expected_reg = hash_find (reg_hash,
8380 di_si[addr_mode][type.bitfield.esseg]);
8381
fc0763e6
JB		 8382 }
8383 else
be05d201 8384 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8385
be05d201
L		 8386 if (i.base_reg != expected_reg
8387 || i.index_reg
fc0763e6 8388 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8389 {
be05d201
L		 8390 /* The second memory operand must have the same size as
8391 the first one. */
8392 if (i.mem_operands
8393 && i.base_reg
8394 && !((addr_mode == CODE_64BIT
8395 && i.base_reg->reg_type.bitfield.reg64)
8396 || (addr_mode == CODE_32BIT
8397 ? i.base_reg->reg_type.bitfield.reg32
8398 : i.base_reg->reg_type.bitfield.reg16)))
8399 goto bad_address;
8400
fc0763e6
JB		 8401 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8402 operand_string,
8403 intel_syntax ? '[' : '(',
8404 register_prefix,
be05d201 8405 expected_reg->reg_name,
fc0763e6 8406 intel_syntax ? ']' : ')');
be05d201 8407 return 1;
fc0763e6 8408 }
be05d201
L		 8409 else
8410 return 1;
8411
8412bad_address:
8413 as_bad (_("`%s' is not a valid %s expression"),
8414 operand_string, kind);
8415 return 0;
3e73aa7c
JH		 8416 }
8417 else
8418 {
be05d201
L		 8419 if (addr_mode != CODE_16BIT)
8420 {
8421 /* 32-bit/64-bit checks. */
8422 if ((i.base_reg
8423 && (addr_mode == CODE_64BIT
8424 ? !i.base_reg->reg_type.bitfield.reg64
8425 : !i.base_reg->reg_type.bitfield.reg32)
8426 && (i.index_reg
8427 || (i.base_reg->reg_num
8428 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8429 || (i.index_reg
8430 && !i.index_reg->reg_type.bitfield.regxmm
8431 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8432 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8433 && ((addr_mode == CODE_64BIT
8434 ? !(i.index_reg->reg_type.bitfield.reg64
8435 || i.index_reg->reg_num == RegRiz)
8436 : !(i.index_reg->reg_type.bitfield.reg32
8437 || i.index_reg->reg_num == RegEiz))
8438 || !i.index_reg->reg_type.bitfield.baseindex)))
8439 goto bad_address;
8440 }
8441 else
3e73aa7c 8442 {
be05d201 8443 /* 16-bit checks. */
3e73aa7c 8444 if ((i.base_reg
40fb9820
L		 8445 && (!i.base_reg->reg_type.bitfield.reg16
8446 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8447 || (i.index_reg
40fb9820
L		 8448 && (!i.index_reg->reg_type.bitfield.reg16
8449 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8450 || !(i.base_reg
8451 && i.base_reg->reg_num < 6
8452 && i.index_reg->reg_num >= 6
8453 && i.log2_scale_factor == 0))))
be05d201 8454 goto bad_address;
3e73aa7c
JH		 8455 }
8456 }
be05d201 8457 return 1;
24eab124 8458}
252b5132 8459
43234a1e
L		 8460/* Handle vector immediates. */
8461
8462static int
8463RC_SAE_immediate (const char *imm_start)
8464{
8465 unsigned int match_found, j;
8466 const char *pstr = imm_start;
8467 expressionS *exp;
8468
8469 if (*pstr != '{')
8470 return 0;
8471
8472 pstr++;
8473 match_found = 0;
8474 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8475 {
8476 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8477 {
8478 if (!i.rounding)
8479 {
8480 rc_op.type = RC_NamesTable[j].type;
8481 rc_op.operand = this_operand;
8482 i.rounding = &rc_op;
8483 }
8484 else
8485 {
8486 as_bad (_("duplicated `%s'"), imm_start);
8487 return 0;
8488 }
8489 pstr += RC_NamesTable[j].len;
8490 match_found = 1;
8491 break;
8492 }
8493 }
8494 if (!match_found)
8495 return 0;
8496
8497 if (*pstr++ != '}')
8498 {
8499 as_bad (_("Missing '}': '%s'"), imm_start);
8500 return 0;
8501 }
8502 /* RC/SAE immediate string should contain nothing more. */;
8503 if (*pstr != 0)
8504 {
8505 as_bad (_("Junk after '}': '%s'"), imm_start);
8506 return 0;
8507 }
8508
8509 exp = &im_expressions[i.imm_operands++];
8510 i.op[this_operand].imms = exp;
8511
8512 exp->X_op = O_constant;
8513 exp->X_add_number = 0;
8514 exp->X_add_symbol = (symbolS *) 0;
8515 exp->X_op_symbol = (symbolS *) 0;
8516
8517 i.types[this_operand].bitfield.imm8 = 1;
8518 return 1;
8519}
8520
fc0763e6 8521/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8522 on error. */
252b5132 8523
252b5132 8524static int
a7619375 8525i386_att_operand (char *operand_string)
252b5132 8526{
af6bdddf
AM		 8527 const reg_entry *r;
8528 char *end_op;
24eab124 8529 char *op_string = operand_string;
252b5132 8530
24eab124 8531 if (is_space_char (*op_string))
252b5132
RH		 8532 ++op_string;
8533
24eab124 8534 /* We check for an absolute prefix (differentiating,
47926f60 8535 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8536 if (*op_string == ABSOLUTE_PREFIX)
8537 {
8538 ++op_string;
8539 if (is_space_char (*op_string))
8540 ++op_string;
40fb9820 8541 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8542 }
252b5132 8543
47926f60 8544 /* Check if operand is a register. */
4d1bb795 8545 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8546 {
40fb9820
L		 8547 i386_operand_type temp;
8548
24eab124
AM		 8549 /* Check for a segment override by searching for ':' after a
8550 segment register. */
8551 op_string = end_op;
8552 if (is_space_char (*op_string))
8553 ++op_string;
40fb9820
L		 8554 if (*op_string == ':'
8555 && (r->reg_type.bitfield.sreg2
8556 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8557 {
8558 switch (r->reg_num)
8559 {
8560 case 0:
8561 i.seg[i.mem_operands] = &es;
8562 break;
8563 case 1:
8564 i.seg[i.mem_operands] = &cs;
8565 break;
8566 case 2:
8567 i.seg[i.mem_operands] = &ss;
8568 break;
8569 case 3:
8570 i.seg[i.mem_operands] = &ds;
8571 break;
8572 case 4:
8573 i.seg[i.mem_operands] = &fs;
8574 break;
8575 case 5:
8576 i.seg[i.mem_operands] = &gs;
8577 break;
8578 }
252b5132 8579
24eab124 8580 /* Skip the ':' and whitespace. */
252b5132
RH		 8581 ++op_string;
8582 if (is_space_char (*op_string))
24eab124 8583 ++op_string;
252b5132 8584
24eab124
AM		 8585 if (!is_digit_char (*op_string)
8586 && !is_identifier_char (*op_string)
8587 && *op_string != '('
8588 && *op_string != ABSOLUTE_PREFIX)
8589 {
8590 as_bad (_("bad memory operand `%s'"), op_string);
8591 return 0;
8592 }
47926f60 8593 /* Handle case of %es:*foo. */
24eab124
AM		 8594 if (*op_string == ABSOLUTE_PREFIX)
8595 {
8596 ++op_string;
8597 if (is_space_char (*op_string))
8598 ++op_string;
40fb9820 8599 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8600 }
8601 goto do_memory_reference;
8602 }
43234a1e
L		 8603
8604 /* Handle vector operations. */
8605 if (*op_string == '{')
8606 {
8607 op_string = check_VecOperations (op_string, NULL);
8608 if (op_string == NULL)
8609 return 0;
8610 }
8611
24eab124
AM		 8612 if (*op_string)
8613 {
d0b47220 8614 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8615 return 0;
8616 }
40fb9820
L		 8617 temp = r->reg_type;
8618 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8619 i.types[this_operand] = operand_type_or (i.types[this_operand],
8620 temp);
7d5e4556 8621 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8622 i.op[this_operand].regs = r;
24eab124
AM		 8623 i.reg_operands++;
8624 }
af6bdddf
AM		 8625 else if (*op_string == REGISTER_PREFIX)
8626 {
8627 as_bad (_("bad register name `%s'"), op_string);
8628 return 0;
8629 }
24eab124 8630 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8631 {
24eab124 8632 ++op_string;
40fb9820 8633 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8634 {
d0b47220 8635 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8636 return 0;
8637 }
8638 if (!i386_immediate (op_string))
8639 return 0;
8640 }
43234a1e
L		 8641 else if (RC_SAE_immediate (operand_string))
8642 {
8643 /* If it is a RC or SAE immediate, do nothing. */
8644 ;
8645 }
24eab124
AM		 8646 else if (is_digit_char (*op_string)
8647 || is_identifier_char (*op_string)
e5cb08ac 8648 || *op_string == '(')
24eab124 8649 {
47926f60 8650 /* This is a memory reference of some sort. */
af6bdddf 8651 char *base_string;
252b5132 8652
47926f60 8653 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8654 char *displacement_string_start;
8655 char *displacement_string_end;
43234a1e 8656 char *vop_start;
252b5132 8657
24eab124 8658 do_memory_reference:
24eab124 8659 if ((i.mem_operands == 1
40fb9820 8660 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8661 || i.mem_operands == 2)
8662 {
8663 as_bad (_("too many memory references for `%s'"),
8664 current_templates->start->name);
8665 return 0;
8666 }
252b5132 8667
24eab124
AM		 8668 /* Check for base index form. We detect the base index form by
8669 looking for an ')' at the end of the operand, searching
8670 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8671 after the '('. */
af6bdddf 8672 base_string = op_string + strlen (op_string);
c3332e24 8673
43234a1e
L		 8674 /* Handle vector operations. */
8675 vop_start = strchr (op_string, '{');
8676 if (vop_start && vop_start < base_string)
8677 {
8678 if (check_VecOperations (vop_start, base_string) == NULL)
8679 return 0;
8680 base_string = vop_start;
8681 }
8682
af6bdddf
AM		 8683 --base_string;
8684 if (is_space_char (*base_string))
8685 --base_string;
252b5132 8686
47926f60 8687 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8688 displacement_string_start = op_string;
8689 displacement_string_end = base_string + 1;
252b5132 8690
24eab124
AM		 8691 if (*base_string == ')')
8692 {
af6bdddf 8693 char *temp_string;
24eab124
AM		 8694 unsigned int parens_balanced = 1;
8695 /* We've already checked that the number of left & right ()'s are
47926f60 8696 equal, so this loop will not be infinite. */
24eab124
AM		 8697 do
8698 {
8699 base_string--;
8700 if (*base_string == ')')
8701 parens_balanced++;
8702 if (*base_string == '(')
8703 parens_balanced--;
8704 }
8705 while (parens_balanced);
c3332e24 8706
af6bdddf 8707 temp_string = base_string;
c3332e24 8708
24eab124 8709 /* Skip past '(' and whitespace. */
252b5132
RH		 8710 ++base_string;
8711 if (is_space_char (*base_string))
24eab124 8712 ++base_string;
252b5132 8713
af6bdddf 8714 if (*base_string == ','
4eed87de
AM		 8715 || ((i.base_reg = parse_register (base_string, &end_op))
8716 != NULL))
252b5132 8717 {
af6bdddf 8718 displacement_string_end = temp_string;
252b5132 8719
40fb9820 8720 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8721
af6bdddf 8722 if (i.base_reg)
24eab124 8723 {
24eab124
AM		 8724 base_string = end_op;
8725 if (is_space_char (*base_string))
8726 ++base_string;
af6bdddf
AM		 8727 }
8728
8729 /* There may be an index reg or scale factor here. */
8730 if (*base_string == ',')
8731 {
8732 ++base_string;
8733 if (is_space_char (*base_string))
8734 ++base_string;
8735
4eed87de
AM		 8736 if ((i.index_reg = parse_register (base_string, &end_op))
8737 != NULL)
24eab124 8738 {
af6bdddf 8739 base_string = end_op;
24eab124
AM		 8740 if (is_space_char (*base_string))
8741 ++base_string;
af6bdddf
AM		 8742 if (*base_string == ',')
8743 {
8744 ++base_string;
8745 if (is_space_char (*base_string))
8746 ++base_string;
8747 }
e5cb08ac 8748 else if (*base_string != ')')
af6bdddf 8749 {
4eed87de
AM		 8750 as_bad (_("expecting `,' or `)' "
8751 "after index register in `%s'"),
af6bdddf
AM		 8752 operand_string);
8753 return 0;
8754 }
24eab124 8755 }
af6bdddf 8756 else if (*base_string == REGISTER_PREFIX)
24eab124 8757 {
f76bf5e0
L		 8758 end_op = strchr (base_string, ',');
8759 if (end_op)
8760 *end_op = '\0';
af6bdddf 8761 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8762 return 0;
8763 }
252b5132 8764
47926f60 8765 /* Check for scale factor. */
551c1ca1 8766 if (*base_string != ')')
af6bdddf 8767 {
551c1ca1
AM		 8768 char *end_scale = i386_scale (base_string);
8769
8770 if (!end_scale)
af6bdddf 8771 return 0;
24eab124 8772
551c1ca1 8773 base_string = end_scale;
af6bdddf
AM		 8774 if (is_space_char (*base_string))
8775 ++base_string;
8776 if (*base_string != ')')
8777 {
4eed87de
AM		 8778 as_bad (_("expecting `)' "
8779 "after scale factor in `%s'"),
af6bdddf
AM		 8780 operand_string);
8781 return 0;
8782 }
8783 }
8784 else if (!i.index_reg)
24eab124 8785 {
4eed87de
AM		 8786 as_bad (_("expecting index register or scale factor "
8787 "after `,'; got '%c'"),
af6bdddf 8788 *base_string);
24eab124
AM		 8789 return 0;
8790 }
8791 }
af6bdddf 8792 else if (*base_string != ')')
24eab124 8793 {
4eed87de
AM		 8794 as_bad (_("expecting `,' or `)' "
8795 "after base register in `%s'"),
af6bdddf 8796 operand_string);
24eab124
AM		 8797 return 0;
8798 }
c3332e24 8799 }
af6bdddf 8800 else if (*base_string == REGISTER_PREFIX)
c3332e24 8801 {
f76bf5e0
L		 8802 end_op = strchr (base_string, ',');
8803 if (end_op)
8804 *end_op = '\0';
af6bdddf 8805 as_bad (_("bad register name `%s'"), base_string);
24eab124 8806 return 0;
c3332e24 8807 }
24eab124
AM		 8808 }
8809
8810 /* If there's an expression beginning the operand, parse it,
8811 assuming displacement_string_start and
8812 displacement_string_end are meaningful. */
8813 if (displacement_string_start != displacement_string_end)
8814 {
8815 if (!i386_displacement (displacement_string_start,
8816 displacement_string_end))
8817 return 0;
8818 }
8819
8820 /* Special case for (%dx) while doing input/output op. */
8821 if (i.base_reg
0dfbf9d7
L		 8822 && operand_type_equal (&i.base_reg->reg_type,
8823 &reg16_inoutportreg)
24eab124
AM		 8824 && i.index_reg == 0
8825 && i.log2_scale_factor == 0
8826 && i.seg[i.mem_operands] == 0
40fb9820 8827 && !operand_type_check (i.types[this_operand], disp))
24eab124 8828 {
65da13b5 8829 i.types[this_operand] = inoutportreg;
24eab124
AM		 8830 return 1;
8831 }
8832
eecb386c
AM		 8833 if (i386_index_check (operand_string) == 0)
8834 return 0;
5c07affc 8835 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8836 i.mem_operands++;
8837 }
8838 else
ce8a8b2f
AM		 8839 {
8840 /* It's not a memory operand; argh! */
24eab124
AM		 8841 as_bad (_("invalid char %s beginning operand %d `%s'"),
8842 output_invalid (*op_string),
8843 this_operand + 1,
8844 op_string);
8845 return 0;
8846 }
47926f60 8847 return 1; /* Normal return. */
252b5132
RH		 8848}
8849\f
fa94de6b
RM		 8850/* Calculate the maximum variable size (i.e., excluding fr_fix)
8851 that an rs_machine_dependent frag may reach. */
8852
8853unsigned int
8854i386_frag_max_var (fragS *frag)
8855{
8856 /* The only relaxable frags are for jumps.
8857 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8858 gas_assert (frag->fr_type == rs_machine_dependent);
8859 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8860}
8861
ee7fcc42
AM		 8862/* md_estimate_size_before_relax()
8863
8864 Called just before relax() for rs_machine_dependent frags. The x86
8865 assembler uses these frags to handle variable size jump
8866 instructions.
8867
8868 Any symbol that is now undefined will not become defined.
8869 Return the correct fr_subtype in the frag.
8870 Return the initial "guess for variable size of frag" to caller.
8871 The guess is actually the growth beyond the fixed part. Whatever
8872 we do to grow the fixed or variable part contributes to our
8873 returned value. */
8874
252b5132 8875int
7016a5d5 8876md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8877{
252b5132 8878 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8879 check for un-relaxable symbols. On an ELF system, we can't relax
8880 an externally visible symbol, because it may be overridden by a
8881 shared library. */
8882 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8883#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8884 || (IS_ELF
31312f95 8885 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8886 || S_IS_WEAK (fragP->fr_symbol)
8887 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8888 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8889#endif
8890#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8891 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8892 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8893#endif
8894 )
252b5132 8895 {
b98ef147
AM		 8896 /* Symbol is undefined in this segment, or we need to keep a
8897 reloc so that weak symbols can be overridden. */
8898 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8899 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8900 unsigned char *opcode;
8901 int old_fr_fix;
f6af82bd 8902
ee7fcc42 8903 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8904 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8905 else if (size == 2)
f6af82bd
AM		 8906 reloc_type = BFD_RELOC_16_PCREL;
8907 else
8908 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8909
ee7fcc42
AM		 8910 old_fr_fix = fragP->fr_fix;
8911 opcode = (unsigned char *) fragP->fr_opcode;
8912
fddf5b5b 8913 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8914 {
fddf5b5b
AM		 8915 case UNCOND_JUMP:
8916 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8917 opcode[0] = 0xe9;
252b5132 8918 fragP->fr_fix += size;
062cd5e7
AS		 8919 fix_new (fragP, old_fr_fix, size,
8920 fragP->fr_symbol,
8921 fragP->fr_offset, 1,
8922 reloc_type);
252b5132
RH		 8923 break;
8924
fddf5b5b 8925 case COND_JUMP86:
412167cb
AM		 8926 if (size == 2
8927 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8928 {
8929 /* Negate the condition, and branch past an
8930 unconditional jump. */
8931 opcode[0] ^= 1;
8932 opcode[1] = 3;
8933 /* Insert an unconditional jump. */
8934 opcode[2] = 0xe9;
8935 /* We added two extra opcode bytes, and have a two byte
8936 offset. */
8937 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8938 fix_new (fragP, old_fr_fix + 2, 2,
8939 fragP->fr_symbol,
8940 fragP->fr_offset, 1,
8941 reloc_type);
fddf5b5b
AM		 8942 break;
8943 }
8944 /* Fall through. */
8945
8946 case COND_JUMP:
412167cb
AM		 8947 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8948 {
3e02c1cc
AM		 8949 fixS *fixP;
8950
412167cb 8951 fragP->fr_fix += 1;
3e02c1cc
AM		 8952 fixP = fix_new (fragP, old_fr_fix, 1,
8953 fragP->fr_symbol,
8954 fragP->fr_offset, 1,
8955 BFD_RELOC_8_PCREL);
8956 fixP->fx_signed = 1;
412167cb
AM		 8957 break;
8958 }
93c2a809 8959
24eab124 8960 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8961 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8962 opcode[1] = opcode[0] + 0x10;
f6af82bd 8963 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8964 /* We've added an opcode byte. */
8965 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8966 fix_new (fragP, old_fr_fix + 1, size,
8967 fragP->fr_symbol,
8968 fragP->fr_offset, 1,
8969 reloc_type);
252b5132 8970 break;
fddf5b5b
AM		 8971
8972 default:
8973 BAD_CASE (fragP->fr_subtype);
8974 break;
252b5132
RH		 8975 }
8976 frag_wane (fragP);
ee7fcc42 8977 return fragP->fr_fix - old_fr_fix;
252b5132 8978 }
93c2a809 8979
93c2a809
AM		 8980 /* Guess size depending on current relax state. Initially the relax
8981 state will correspond to a short jump and we return 1, because
8982 the variable part of the frag (the branch offset) is one byte
8983 long. However, we can relax a section more than once and in that
8984 case we must either set fr_subtype back to the unrelaxed state,
8985 or return the value for the appropriate branch. */
8986 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8987}
8988
47926f60
KH		 8989/* Called after relax() is finished.
8990
8991 In: Address of frag.
8992 fr_type == rs_machine_dependent.
8993 fr_subtype is what the address relaxed to.
8994
8995 Out: Any fixSs and constants are set up.
8996 Caller will turn frag into a ".space 0". */
8997
252b5132 8998void
7016a5d5
TG		 8999md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9000 fragS *fragP)
252b5132 9001{
29b0f896 9002 unsigned char *opcode;
252b5132 9003 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9004 offsetT target_address;
9005 offsetT opcode_address;
252b5132 9006 unsigned int extension = 0;
847f7ad4 9007 offsetT displacement_from_opcode_start;
252b5132
RH		 9008
9009 opcode = (unsigned char *) fragP->fr_opcode;
9010
47926f60 9011 /* Address we want to reach in file space. */
252b5132 9012 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9013
47926f60 9014 /* Address opcode resides at in file space. */
252b5132
RH		 9015 opcode_address = fragP->fr_address + fragP->fr_fix;
9016
47926f60 9017 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9018 displacement_from_opcode_start = target_address - opcode_address;
9019
fddf5b5b 9020 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9021 {
47926f60
KH		 9022 /* Don't have to change opcode. */
9023 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9024 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9025 }
9026 else
9027 {
9028 if (no_cond_jump_promotion
9029 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9030 as_warn_where (fragP->fr_file, fragP->fr_line,
9031 _("long jump required"));
252b5132 9032
fddf5b5b
AM		 9033 switch (fragP->fr_subtype)
9034 {
9035 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9036 extension = 4; /* 1 opcode + 4 displacement */
9037 opcode[0] = 0xe9;
9038 where_to_put_displacement = &opcode[1];
9039 break;
252b5132 9040
fddf5b5b
AM		 9041 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9042 extension = 2; /* 1 opcode + 2 displacement */
9043 opcode[0] = 0xe9;
9044 where_to_put_displacement = &opcode[1];
9045 break;
252b5132 9046
fddf5b5b
AM		 9047 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9048 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9049 extension = 5; /* 2 opcode + 4 displacement */
9050 opcode[1] = opcode[0] + 0x10;
9051 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9052 where_to_put_displacement = &opcode[2];
9053 break;
252b5132 9054
fddf5b5b
AM		 9055 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9056 extension = 3; /* 2 opcode + 2 displacement */
9057 opcode[1] = opcode[0] + 0x10;
9058 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9059 where_to_put_displacement = &opcode[2];
9060 break;
252b5132 9061
fddf5b5b
AM		 9062 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9063 extension = 4;
9064 opcode[0] ^= 1;
9065 opcode[1] = 3;
9066 opcode[2] = 0xe9;
9067 where_to_put_displacement = &opcode[3];
9068 break;
9069
9070 default:
9071 BAD_CASE (fragP->fr_subtype);
9072 break;
9073 }
252b5132 9074 }
fddf5b5b 9075
7b81dfbb
AJ		 9076 /* If size if less then four we are sure that the operand fits,
9077 but if it's 4, then it could be that the displacement is larger
9078 then -/+ 2GB. */
9079 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9080 && object_64bit
9081 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9082 + ((addressT) 1 << 31))
9083 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9084 {
9085 as_bad_where (fragP->fr_file, fragP->fr_line,
9086 _("jump target out of range"));
9087 /* Make us emit 0. */
9088 displacement_from_opcode_start = extension;
9089 }
47926f60 9090 /* Now put displacement after opcode. */
252b5132
RH		 9091 md_number_to_chars ((char *) where_to_put_displacement,
9092 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9093 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9094 fragP->fr_fix += extension;
9095}
9096\f
7016a5d5 9097/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9098 by our caller that we have all the info we need to fix it up.
9099
7016a5d5
TG		 9100 Parameter valP is the pointer to the value of the bits.
9101
252b5132
RH		 9102 On the 386, immediates, displacements, and data pointers are all in
9103 the same (little-endian) format, so we don't need to care about which
9104 we are handling. */
9105
94f592af 9106void
7016a5d5 9107md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9108{
94f592af 9109 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9110 valueT value = *valP;
252b5132 9111
f86103b7 9112#if !defined (TE_Mach)
93382f6d
AM		 9113 if (fixP->fx_pcrel)
9114 {
9115 switch (fixP->fx_r_type)
9116 {
5865bb77
ILT		 9117 default:
9118 break;
9119
d6ab8113
JB		 9120 case BFD_RELOC_64:
9121 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9122 break;
93382f6d 9123 case BFD_RELOC_32:
ae8887b5 9124 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9125 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9126 break;
9127 case BFD_RELOC_16:
9128 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9129 break;
9130 case BFD_RELOC_8:
9131 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9132 break;
9133 }
9134 }
252b5132 9135
a161fe53 9136 if (fixP->fx_addsy != NULL
31312f95 9137 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9138 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9139 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9140 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9141 && !use_rela_relocations)
252b5132 9142 {
31312f95
AM		 9143 /* This is a hack. There should be a better way to handle this.
9144 This covers for the fact that bfd_install_relocation will
9145 subtract the current location (for partial_inplace, PC relative
9146 relocations); see more below. */
252b5132 9147#ifndef OBJ_AOUT
718ddfc0 9148 if (IS_ELF
252b5132
RH		 9149#ifdef TE_PE
9150 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9151#endif
9152 )
9153 value += fixP->fx_where + fixP->fx_frag->fr_address;
9154#endif
9155#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9156 if (IS_ELF)
252b5132 9157 {
6539b54b 9158 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9159
6539b54b 9160 if ((sym_seg == seg
2f66722d 9161 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9162 && sym_seg != absolute_section))
af65af87 9163 && !generic_force_reloc (fixP))
2f66722d
AM		 9164 {
9165 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9166 bfd_install_relocation subtracts them out again. I think
9167 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9168 it. FIXME. */
9169 value += fixP->fx_where + fixP->fx_frag->fr_address;
9170 }
252b5132
RH		 9171 }
9172#endif
9173#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9174 /* For some reason, the PE format does not store a
9175 section address offset for a PC relative symbol. */
9176 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9177 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9178 value += md_pcrel_from (fixP);
9179#endif
9180 }
fbeb56a4 9181#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9182 if (fixP->fx_addsy != NULL
9183 && S_IS_WEAK (fixP->fx_addsy)
9184 /* PR 16858: Do not modify weak function references. */
9185 && ! fixP->fx_pcrel)
fbeb56a4 9186 {
296a8689
NC		 9187#if !defined (TE_PEP)
9188 /* For x86 PE weak function symbols are neither PC-relative
9189 nor do they set S_IS_FUNCTION. So the only reliable way
9190 to detect them is to check the flags of their containing
9191 section. */
9192 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9193 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9194 ;
9195 else
9196#endif
fbeb56a4
DK		 9197 value -= S_GET_VALUE (fixP->fx_addsy);
9198 }
9199#endif
252b5132
RH		 9200
9201 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9202 and we must not disappoint it. */
252b5132 9203#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9204 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9205 switch (fixP->fx_r_type)
9206 {
9207 case BFD_RELOC_386_PLT32:
3e73aa7c 9208 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9209 /* Make the jump instruction point to the address of the operand. At
9210 runtime we merely add the offset to the actual PLT entry. */
9211 value = -4;
9212 break;
31312f95 9213
13ae64f3
JJ		 9214 case BFD_RELOC_386_TLS_GD:
9215 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9216 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9217 case BFD_RELOC_386_TLS_IE:
9218 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9219 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9220 case BFD_RELOC_X86_64_TLSGD:
9221 case BFD_RELOC_X86_64_TLSLD:
9222 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9223 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9224 value = 0; /* Fully resolved at runtime. No addend. */
9225 /* Fallthrough */
9226 case BFD_RELOC_386_TLS_LE:
9227 case BFD_RELOC_386_TLS_LDO_32:
9228 case BFD_RELOC_386_TLS_LE_32:
9229 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9230 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9231 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9232 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9233 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9234 break;
9235
67a4f2b7
AO		 9236 case BFD_RELOC_386_TLS_DESC_CALL:
9237 case BFD_RELOC_X86_64_TLSDESC_CALL:
9238 value = 0; /* Fully resolved at runtime. No addend. */
9239 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9240 fixP->fx_done = 0;
9241 return;
9242
00f7efb6
JJ		 9243 case BFD_RELOC_386_GOT32:
9244 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9245 value = 0; /* Fully resolved at runtime. No addend. */
9246 break;
47926f60
KH		 9247
9248 case BFD_RELOC_VTABLE_INHERIT:
9249 case BFD_RELOC_VTABLE_ENTRY:
9250 fixP->fx_done = 0;
94f592af 9251 return;
47926f60
KH		 9252
9253 default:
9254 break;
9255 }
9256#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9257 *valP = value;
f86103b7 9258#endif /* !defined (TE_Mach) */
3e73aa7c 9259
3e73aa7c 9260 /* Are we finished with this relocation now? */
c6682705 9261 if (fixP->fx_addsy == NULL)
3e73aa7c 9262 fixP->fx_done = 1;
fbeb56a4
DK		 9263#if defined (OBJ_COFF) && defined (TE_PE)
9264 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9265 {
9266 fixP->fx_done = 0;
9267 /* Remember value for tc_gen_reloc. */
9268 fixP->fx_addnumber = value;
9269 /* Clear out the frag for now. */
9270 value = 0;
9271 }
9272#endif
3e73aa7c
JH		 9273 else if (use_rela_relocations)
9274 {
9275 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9276 /* Remember value for tc_gen_reloc. */
9277 fixP->fx_addnumber = value;
3e73aa7c
JH		 9278 value = 0;
9279 }
f86103b7 9280
94f592af 9281 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9282}
252b5132 9283\f
252b5132 9284char *
499ac353 9285md_atof (int type, char *litP, int *sizeP)
252b5132 9286{
499ac353
NC		 9287 /* This outputs the LITTLENUMs in REVERSE order;
9288 in accord with the bigendian 386. */
9289 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9290}
9291\f
2d545b82 9292static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9293
252b5132 9294static char *
e3bb37b5 9295output_invalid (int c)
252b5132 9296{
3882b010 9297 if (ISPRINT (c))
f9f21a03
L		 9298 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9299 "'%c'", c);
252b5132 9300 else
f9f21a03 9301 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9302 "(0x%x)", (unsigned char) c);
252b5132
RH		 9303 return output_invalid_buf;
9304}
9305
af6bdddf 9306/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9307
9308static const reg_entry *
4d1bb795 9309parse_real_register (char *reg_string, char **end_op)
252b5132 9310{
af6bdddf
AM		 9311 char *s = reg_string;
9312 char *p;
252b5132
RH		 9313 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9314 const reg_entry *r;
9315
9316 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9317 if (*s == REGISTER_PREFIX)
9318 ++s;
9319
9320 if (is_space_char (*s))
9321 ++s;
9322
9323 p = reg_name_given;
af6bdddf 9324 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9325 {
9326 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9327 return (const reg_entry *) NULL;
9328 s++;
252b5132
RH		 9329 }
9330
6588847e
DN		 9331 /* For naked regs, make sure that we are not dealing with an identifier.
9332 This prevents confusing an identifier like `eax_var' with register
9333 `eax'. */
9334 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9335 return (const reg_entry *) NULL;
9336
af6bdddf 9337 *end_op = s;
252b5132
RH		 9338
9339 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9340
5f47d35b 9341 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9342 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9343 {
5f47d35b
AM		 9344 if (is_space_char (*s))
9345 ++s;
9346 if (*s == '(')
9347 {
af6bdddf 9348 ++s;
5f47d35b
AM		 9349 if (is_space_char (*s))
9350 ++s;
9351 if (*s >= '0' && *s <= '7')
9352 {
db557034 9353 int fpr = *s - '0';
af6bdddf 9354 ++s;
5f47d35b
AM		 9355 if (is_space_char (*s))
9356 ++s;
9357 if (*s == ')')
9358 {
9359 *end_op = s + 1;
1e9cc1c2 9360 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9361 know (r);
9362 return r + fpr;
5f47d35b 9363 }
5f47d35b 9364 }
47926f60 9365 /* We have "%st(" then garbage. */
5f47d35b
AM		 9366 return (const reg_entry *) NULL;
9367 }
9368 }
9369
a60de03c
JB		 9370 if (r == NULL || allow_pseudo_reg)
9371 return r;
9372
0dfbf9d7 9373 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9374 return (const reg_entry *) NULL;
9375
192dc9c6
JB		 9376 if ((r->reg_type.bitfield.reg32
9377 || r->reg_type.bitfield.sreg3
9378 || r->reg_type.bitfield.control
9379 || r->reg_type.bitfield.debug
9380 || r->reg_type.bitfield.test)
9381 && !cpu_arch_flags.bitfield.cpui386)
9382 return (const reg_entry *) NULL;
9383
309d3373
JB		 9384 if (r->reg_type.bitfield.floatreg
9385 && !cpu_arch_flags.bitfield.cpu8087
9386 && !cpu_arch_flags.bitfield.cpu287
9387 && !cpu_arch_flags.bitfield.cpu387)
9388 return (const reg_entry *) NULL;
9389
192dc9c6
JB		 9390 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9391 return (const reg_entry *) NULL;
9392
9393 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9394 return (const reg_entry *) NULL;
9395
40f12533
L		 9396 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9397 return (const reg_entry *) NULL;
9398
43234a1e
L		 9399 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9400 && !cpu_arch_flags.bitfield.cpuavx512f)
9401 return (const reg_entry *) NULL;
9402
db51cc60 9403 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9404 if (!allow_index_reg
db51cc60
L		 9405 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9406 return (const reg_entry *) NULL;
9407
43234a1e
L		 9408 /* Upper 16 vector register is only available with VREX in 64bit
9409 mode. */
9410 if ((r->reg_flags & RegVRex))
9411 {
9412 if (!cpu_arch_flags.bitfield.cpuvrex
9413 || flag_code != CODE_64BIT)
9414 return (const reg_entry *) NULL;
9415
9416 i.need_vrex = 1;
9417 }
9418
a60de03c
JB		 9419 if (((r->reg_flags & (RegRex64 | RegRex))
9420 || r->reg_type.bitfield.reg64)
40fb9820 9421 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9422 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9423 && flag_code != CODE_64BIT)
20f0a1fc 9424 return (const reg_entry *) NULL;
1ae00879 9425
b7240065
JB		 9426 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9427 return (const reg_entry *) NULL;
9428
252b5132
RH		 9429 return r;
9430}
4d1bb795
JB		 9431
9432/* REG_STRING starts *before* REGISTER_PREFIX. */
9433
9434static const reg_entry *
9435parse_register (char *reg_string, char **end_op)
9436{
9437 const reg_entry *r;
9438
9439 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9440 r = parse_real_register (reg_string, end_op);
9441 else
9442 r = NULL;
9443 if (!r)
9444 {
9445 char *save = input_line_pointer;
9446 char c;
9447 symbolS *symbolP;
9448
9449 input_line_pointer = reg_string;
9450 c = get_symbol_end ();
9451 symbolP = symbol_find (reg_string);
9452 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9453 {
9454 const expressionS *e = symbol_get_value_expression (symbolP);
9455
0398aac5 9456 know (e->X_op == O_register);
4eed87de 9457 know (e->X_add_number >= 0
c3fe08fa 9458 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9459 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9460 if ((r->reg_flags & RegVRex))
9461 i.need_vrex = 1;
4d1bb795
JB		 9462 *end_op = input_line_pointer;
9463 }
9464 *input_line_pointer = c;
9465 input_line_pointer = save;
9466 }
9467 return r;
9468}
9469
9470int
9471i386_parse_name (char *name, expressionS *e, char *nextcharP)
9472{
9473 const reg_entry *r;
9474 char *end = input_line_pointer;
9475
9476 *end = *nextcharP;
9477 r = parse_register (name, &input_line_pointer);
9478 if (r && end <= input_line_pointer)
9479 {
9480 *nextcharP = *input_line_pointer;
9481 *input_line_pointer = 0;
9482 e->X_op = O_register;
9483 e->X_add_number = r - i386_regtab;
9484 return 1;
9485 }
9486 input_line_pointer = end;
9487 *end = 0;
ee86248c 9488 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9489}
9490
9491void
9492md_operand (expressionS *e)
9493{
ee86248c
JB		 9494 char *end;
9495 const reg_entry *r;
4d1bb795 9496
ee86248c
JB		 9497 switch (*input_line_pointer)
9498 {
9499 case REGISTER_PREFIX:
9500 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9501 if (r)
9502 {
9503 e->X_op = O_register;
9504 e->X_add_number = r - i386_regtab;
9505 input_line_pointer = end;
9506 }
ee86248c
JB		 9507 break;
9508
9509 case '[':
9c2799c2 9510 gas_assert (intel_syntax);
ee86248c
JB		 9511 end = input_line_pointer++;
9512 expression (e);
9513 if (*input_line_pointer == ']')
9514 {
9515 ++input_line_pointer;
9516 e->X_op_symbol = make_expr_symbol (e);
9517 e->X_add_symbol = NULL;
9518 e->X_add_number = 0;
9519 e->X_op = O_index;
9520 }
9521 else
9522 {
9523 e->X_op = O_absent;
9524 input_line_pointer = end;
9525 }
9526 break;
4d1bb795
JB		 9527 }
9528}
9529
252b5132 9530\f
4cc782b5 9531#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9532const char *md_shortopts = "kVQ:sqn";
252b5132 9533#else
12b55ccc 9534const char *md_shortopts = "qn";
252b5132 9535#endif
6e0b89ee 9536
3e73aa7c 9537#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9538#define OPTION_64 (OPTION_MD_BASE + 1)
9539#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9540#define OPTION_MARCH (OPTION_MD_BASE + 3)
9541#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9542#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9543#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9544#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9545#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9546#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9547#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9548#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9549#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9550#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9551#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9552#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9553#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9554#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9555#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9556#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9557#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9558
99ad8390
NC		 9559struct option md_longopts[] =
9560{
3e73aa7c 9561 {"32", no_argument, NULL, OPTION_32},
321098a5 9562#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9563 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9564 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9565#endif
9566#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9567 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9568#endif
b3b91714 9569 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9570 {"march", required_argument, NULL, OPTION_MARCH},
9571 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9572 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9573 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9574 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9575 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9576 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9577 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9578 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9579 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9580 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9581 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9582 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9583 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9584# if defined (TE_PE) || defined (TE_PEP)
9585 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9586#endif
a5094208 9587 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9588 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9589 {NULL, no_argument, NULL, 0}
9590};
9591size_t md_longopts_size = sizeof (md_longopts);
9592
9593int
9103f4f4 9594md_parse_option (int c, char *arg)
252b5132 9595{
91d6fa6a 9596 unsigned int j;
6305a203 9597 char *arch, *next;
9103f4f4 9598
252b5132
RH		 9599 switch (c)
9600 {
12b55ccc
L		 9601 case 'n':
9602 optimize_align_code = 0;
9603 break;
9604
a38cf1db
AM		 9605 case 'q':
9606 quiet_warnings = 1;
252b5132
RH		 9607 break;
9608
9609#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9610 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9611 should be emitted or not. FIXME: Not implemented. */
9612 case 'Q':
252b5132
RH		 9613 break;
9614
9615 /* -V: SVR4 argument to print version ID. */
9616 case 'V':
9617 print_version_id ();
9618 break;
9619
a38cf1db
AM		 9620 /* -k: Ignore for FreeBSD compatibility. */
9621 case 'k':
252b5132 9622 break;
4cc782b5
ILT		 9623
9624 case 's':
9625 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9626 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9627 break;
99ad8390 9628#endif
321098a5 9629#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9630 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9631 case OPTION_64:
9632 {
9633 const char **list, **l;
9634
3e73aa7c
JH		 9635 list = bfd_target_list ();
9636 for (l = list; *l != NULL; l++)
8620418b 9637 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9638 || strcmp (*l, "coff-x86-64") == 0
9639 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9640 || strcmp (*l, "pei-x86-64") == 0
9641 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9642 {
9643 default_arch = "x86_64";
9644 break;
9645 }
3e73aa7c 9646 if (*l == NULL)
2b5d6a91 9647 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9648 free (list);
9649 }
9650 break;
9651#endif
252b5132 9652
351f65ca 9653#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9654 case OPTION_X32:
351f65ca
L		 9655 if (IS_ELF)
9656 {
9657 const char **list, **l;
9658
9659 list = bfd_target_list ();
9660 for (l = list; *l != NULL; l++)
9661 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9662 {
9663 default_arch = "x86_64:32";
9664 break;
9665 }
9666 if (*l == NULL)
2b5d6a91 9667 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9668 free (list);
9669 }
9670 else
9671 as_fatal (_("32bit x86_64 is only supported for ELF"));
9672 break;
9673#endif
9674
6e0b89ee
AM		 9675 case OPTION_32:
9676 default_arch = "i386";
9677 break;
9678
b3b91714
AM		 9679 case OPTION_DIVIDE:
9680#ifdef SVR4_COMMENT_CHARS
9681 {
9682 char *n, *t;
9683 const char *s;
9684
9685 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9686 t = n;
9687 for (s = i386_comment_chars; *s != '\0'; s++)
9688 if (*s != '/')
9689 *t++ = *s;
9690 *t = '\0';
9691 i386_comment_chars = n;
9692 }
9693#endif
9694 break;
9695
9103f4f4 9696 case OPTION_MARCH:
6305a203
L		 9697 arch = xstrdup (arg);
9698 do
9103f4f4 9699 {
6305a203 9700 if (*arch == '.')
2b5d6a91 9701 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9702 next = strchr (arch, '+');
9703 if (next)
9704 *next++ = '\0';
91d6fa6a 9705 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9706 {
91d6fa6a 9707 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9708 {
6305a203 9709 /* Processor. */
1ded5609
JB		 9710 if (! cpu_arch[j].flags.bitfield.cpui386)
9711 continue;
9712
91d6fa6a 9713 cpu_arch_name = cpu_arch[j].name;
6305a203 9714 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9715 cpu_arch_flags = cpu_arch[j].flags;
9716 cpu_arch_isa = cpu_arch[j].type;
9717 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9718 if (!cpu_arch_tune_set)
9719 {
9720 cpu_arch_tune = cpu_arch_isa;
9721 cpu_arch_tune_flags = cpu_arch_isa_flags;
9722 }
9723 break;
9724 }
91d6fa6a
NC		 9725 else if (*cpu_arch [j].name == '.'
9726 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9727 {
9728 /* ISA entension. */
9729 i386_cpu_flags flags;
309d3373 9730
49021df2 9731 if (!cpu_arch[j].negated)
309d3373 9732 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9733 cpu_arch[j].flags);
309d3373
JB		 9734 else
9735 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9736 cpu_arch[j].flags);
0dfbf9d7 9737 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9738 {
9739 if (cpu_sub_arch_name)
9740 {
9741 char *name = cpu_sub_arch_name;
9742 cpu_sub_arch_name = concat (name,
91d6fa6a 9743 cpu_arch[j].name,
1bf57e9f 9744 (const char *) NULL);
6305a203
L		 9745 free (name);
9746 }
9747 else
91d6fa6a 9748 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9749 cpu_arch_flags = flags;
a586129e 9750 cpu_arch_isa_flags = flags;
6305a203
L		 9751 }
9752 break;
ccc9c027 9753 }
9103f4f4 9754 }
6305a203 9755
91d6fa6a 9756 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9757 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9758
9759 arch = next;
9103f4f4 9760 }
6305a203 9761 while (next != NULL );
9103f4f4
L		 9762 break;
9763
9764 case OPTION_MTUNE:
9765 if (*arg == '.')
2b5d6a91 9766 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9767 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9768 {
91d6fa6a 9769 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9770 {
ccc9c027 9771 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9772 cpu_arch_tune = cpu_arch [j].type;
9773 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9774 break;
9775 }
9776 }
91d6fa6a 9777 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9778 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9779 break;
9780
1efbbeb4
L		 9781 case OPTION_MMNEMONIC:
9782 if (strcasecmp (arg, "att") == 0)
9783 intel_mnemonic = 0;
9784 else if (strcasecmp (arg, "intel") == 0)
9785 intel_mnemonic = 1;
9786 else
2b5d6a91 9787 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9788 break;
9789
9790 case OPTION_MSYNTAX:
9791 if (strcasecmp (arg, "att") == 0)
9792 intel_syntax = 0;
9793 else if (strcasecmp (arg, "intel") == 0)
9794 intel_syntax = 1;
9795 else
2b5d6a91 9796 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9797 break;
9798
9799 case OPTION_MINDEX_REG:
9800 allow_index_reg = 1;
9801 break;
9802
9803 case OPTION_MNAKED_REG:
9804 allow_naked_reg = 1;
9805 break;
9806
9807 case OPTION_MOLD_GCC:
9808 old_gcc = 1;
1efbbeb4
L		 9809 break;
9810
c0f3af97
L		 9811 case OPTION_MSSE2AVX:
9812 sse2avx = 1;
9813 break;
9814
daf50ae7
L		 9815 case OPTION_MSSE_CHECK:
9816 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9817 sse_check = check_error;
daf50ae7 9818 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9819 sse_check = check_warning;
daf50ae7 9820 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9821 sse_check = check_none;
daf50ae7 9822 else
2b5d6a91 9823 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9824 break;
9825
7bab8ab5
JB		 9826 case OPTION_MOPERAND_CHECK:
9827 if (strcasecmp (arg, "error") == 0)
9828 operand_check = check_error;
9829 else if (strcasecmp (arg, "warning") == 0)
9830 operand_check = check_warning;
9831 else if (strcasecmp (arg, "none") == 0)
9832 operand_check = check_none;
9833 else
9834 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9835 break;
9836
539f890d
L		 9837 case OPTION_MAVXSCALAR:
9838 if (strcasecmp (arg, "128") == 0)
9839 avxscalar = vex128;
9840 else if (strcasecmp (arg, "256") == 0)
9841 avxscalar = vex256;
9842 else
2b5d6a91 9843 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9844 break;
9845
7e8b059b
L		 9846 case OPTION_MADD_BND_PREFIX:
9847 add_bnd_prefix = 1;
9848 break;
9849
43234a1e
L		 9850 case OPTION_MEVEXLIG:
9851 if (strcmp (arg, "128") == 0)
9852 evexlig = evexl128;
9853 else if (strcmp (arg, "256") == 0)
9854 evexlig = evexl256;
9855 else if (strcmp (arg, "512") == 0)
9856 evexlig = evexl512;
9857 else
9858 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9859 break;
9860
d3d3c6db
IT		 9861 case OPTION_MEVEXRCIG:
9862 if (strcmp (arg, "rne") == 0)
9863 evexrcig = rne;
9864 else if (strcmp (arg, "rd") == 0)
9865 evexrcig = rd;
9866 else if (strcmp (arg, "ru") == 0)
9867 evexrcig = ru;
9868 else if (strcmp (arg, "rz") == 0)
9869 evexrcig = rz;
9870 else
9871 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9872 break;
9873
43234a1e
L		 9874 case OPTION_MEVEXWIG:
9875 if (strcmp (arg, "0") == 0)
9876 evexwig = evexw0;
9877 else if (strcmp (arg, "1") == 0)
9878 evexwig = evexw1;
9879 else
9880 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9881 break;
9882
167ad85b
TG		 9883# if defined (TE_PE) || defined (TE_PEP)
9884 case OPTION_MBIG_OBJ:
9885 use_big_obj = 1;
9886 break;
9887#endif
9888
a5094208 9889 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9890 if (strcasecmp (arg, "yes") == 0)
9891 omit_lock_prefix = 1;
9892 else if (strcasecmp (arg, "no") == 0)
9893 omit_lock_prefix = 0;
9894 else
9895 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9896 break;
9897
252b5132
RH		 9898 default:
9899 return 0;
9900 }
9901 return 1;
9902}
9903
8a2c8fef
L		 9904#define MESSAGE_TEMPLATE \
9905" "
9906
9907static void
1ded5609 9908show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9909{
9910 static char message[] = MESSAGE_TEMPLATE;
9911 char *start = message + 27;
9912 char *p;
9913 int size = sizeof (MESSAGE_TEMPLATE);
9914 int left;
9915 const char *name;
9916 int len;
9917 unsigned int j;
9918
9919 p = start;
9920 left = size - (start - message);
9921 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9922 {
9923 /* Should it be skipped? */
9924 if (cpu_arch [j].skip)
9925 continue;
9926
9927 name = cpu_arch [j].name;
9928 len = cpu_arch [j].len;
9929 if (*name == '.')
9930 {
9931 /* It is an extension. Skip if we aren't asked to show it. */
9932 if (ext)
9933 {
9934 name++;
9935 len--;
9936 }
9937 else
9938 continue;
9939 }
9940 else if (ext)
9941 {
9942 /* It is an processor. Skip if we show only extension. */
9943 continue;
9944 }
1ded5609
JB		 9945 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9946 {
9947 /* It is an impossible processor - skip. */
9948 continue;
9949 }
8a2c8fef
L		 9950
9951 /* Reserve 2 spaces for ", " or ",\0" */
9952 left -= len + 2;
9953
9954 /* Check if there is any room. */
9955 if (left >= 0)
9956 {
9957 if (p != start)
9958 {
9959 *p++ = ',';
9960 *p++ = ' ';
9961 }
9962 p = mempcpy (p, name, len);
9963 }
9964 else
9965 {
9966 /* Output the current message now and start a new one. */
9967 *p++ = ',';
9968 *p = '\0';
9969 fprintf (stream, "%s\n", message);
9970 p = start;
9971 left = size - (start - message) - len - 2;
8d63c93e 9972
8a2c8fef
L		 9973 gas_assert (left >= 0);
9974
9975 p = mempcpy (p, name, len);
9976 }
9977 }
9978
9979 *p = '\0';
9980 fprintf (stream, "%s\n", message);
9981}
9982
252b5132 9983void
8a2c8fef 9984md_show_usage (FILE *stream)
252b5132 9985{
4cc782b5
ILT		 9986#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9987 fprintf (stream, _("\
a38cf1db
AM		 9988 -Q ignored\n\
9989 -V print assembler version number\n\
b3b91714
AM		 9990 -k ignored\n"));
9991#endif
9992 fprintf (stream, _("\
12b55ccc 9993 -n Do not optimize code alignment\n\
b3b91714
AM		 9994 -q quieten some warnings\n"));
9995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9996 fprintf (stream, _("\
a38cf1db 9997 -s ignored\n"));
b3b91714 9998#endif
321098a5
L		 9999#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10000 || defined (TE_PE) || defined (TE_PEP))
751d281c 10001 fprintf (stream, _("\
570561f7 10002 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10003#endif
b3b91714
AM		 10004#ifdef SVR4_COMMENT_CHARS
10005 fprintf (stream, _("\
10006 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10007#else
10008 fprintf (stream, _("\
b3b91714 10009 --divide ignored\n"));
4cc782b5 10010#endif
9103f4f4 10011 fprintf (stream, _("\
6305a203 10012 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10013 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10014 show_arch (stream, 0, 1);
8a2c8fef
L		 10015 fprintf (stream, _("\
10016 EXTENSION is combination of:\n"));
1ded5609 10017 show_arch (stream, 1, 0);
6305a203 10018 fprintf (stream, _("\
8a2c8fef 10019 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10020 show_arch (stream, 0, 0);
ba104c83 10021 fprintf (stream, _("\
c0f3af97
L		 10022 -msse2avx encode SSE instructions with VEX prefix\n"));
10023 fprintf (stream, _("\
daf50ae7
L		 10024 -msse-check=[none|error|warning]\n\
10025 check SSE instructions\n"));
10026 fprintf (stream, _("\
7bab8ab5
JB		 10027 -moperand-check=[none|error|warning]\n\
10028 check operand combinations for validity\n"));
10029 fprintf (stream, _("\
539f890d
L		 10030 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10031 length\n"));
10032 fprintf (stream, _("\
43234a1e
L		 10033 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10034 length\n"));
10035 fprintf (stream, _("\
10036 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10037 for EVEX.W bit ignored instructions\n"));
10038 fprintf (stream, _("\
d3d3c6db
IT		 10039 -mevexrcig=[rne|rd|ru|rz]\n\
10040 encode EVEX instructions with specific EVEX.RC value\n\
10041 for SAE-only ignored instructions\n"));
10042 fprintf (stream, _("\
ba104c83
L		 10043 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10044 fprintf (stream, _("\
10045 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10046 fprintf (stream, _("\
10047 -mindex-reg support pseudo index registers\n"));
10048 fprintf (stream, _("\
10049 -mnaked-reg don't require `%%' prefix for registers\n"));
10050 fprintf (stream, _("\
10051 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10052 fprintf (stream, _("\
10053 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 10054# if defined (TE_PE) || defined (TE_PEP)
10055 fprintf (stream, _("\
10056 -mbig-obj generate big object files\n"));
10057#endif
d022bddd
IT		 10058 fprintf (stream, _("\
10059 -momit-lock-prefix=[no|yes]\n\
10060 strip all lock prefixes\n"));
252b5132
RH		 10061}
10062
3e73aa7c 10063#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10064 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10065 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10066
10067/* Pick the target format to use. */
10068
47926f60 10069const char *
e3bb37b5 10070i386_target_format (void)
252b5132 10071{
351f65ca
L		 10072 if (!strncmp (default_arch, "x86_64", 6))
10073 {
10074 update_code_flag (CODE_64BIT, 1);
10075 if (default_arch[6] == '\0')
7f56bc95 10076 x86_elf_abi = X86_64_ABI;
351f65ca 10077 else
7f56bc95 10078 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10079 }
3e73aa7c 10080 else if (!strcmp (default_arch, "i386"))
78f12dd3 10081 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10082 else
2b5d6a91 10083 as_fatal (_("unknown architecture"));
89507696
JB		 10084
10085 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10086 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10087 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10088 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10089
252b5132
RH		 10090 switch (OUTPUT_FLAVOR)
10091 {
9384f2ff 10092#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10093 case bfd_target_aout_flavour:
47926f60 10094 return AOUT_TARGET_FORMAT;
4c63da97 10095#endif
9384f2ff
AM		 10096#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10097# if defined (TE_PE) || defined (TE_PEP)
10098 case bfd_target_coff_flavour:
167ad85b
TG		 10099 if (flag_code == CODE_64BIT)
10100 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10101 else
10102 return "pe-i386";
9384f2ff 10103# elif defined (TE_GO32)
0561d57c
JK		 10104 case bfd_target_coff_flavour:
10105 return "coff-go32";
9384f2ff 10106# else
252b5132
RH		 10107 case bfd_target_coff_flavour:
10108 return "coff-i386";
9384f2ff 10109# endif
4c63da97 10110#endif
3e73aa7c 10111#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10112 case bfd_target_elf_flavour:
3e73aa7c 10113 {
351f65ca
L		 10114 const char *format;
10115
10116 switch (x86_elf_abi)
4fa24527 10117 {
351f65ca
L		 10118 default:
10119 format = ELF_TARGET_FORMAT;
10120 break;
7f56bc95 10121 case X86_64_ABI:
351f65ca 10122 use_rela_relocations = 1;
4fa24527 10123 object_64bit = 1;
351f65ca
L		 10124 format = ELF_TARGET_FORMAT64;
10125 break;
7f56bc95 10126 case X86_64_X32_ABI:
4fa24527 10127 use_rela_relocations = 1;
351f65ca 10128 object_64bit = 1;
862be3fb 10129 disallow_64bit_reloc = 1;
351f65ca
L		 10130 format = ELF_TARGET_FORMAT32;
10131 break;
4fa24527 10132 }
3632d14b 10133 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10134 {
7f56bc95 10135 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10136 as_fatal (_("Intel L1OM is 64bit only"));
10137 return ELF_TARGET_L1OM_FORMAT;
10138 }
7a9068fe
L		 10139 if (cpu_arch_isa == PROCESSOR_K1OM)
10140 {
10141 if (x86_elf_abi != X86_64_ABI)
10142 as_fatal (_("Intel K1OM is 64bit only"));
10143 return ELF_TARGET_K1OM_FORMAT;
10144 }
8a9036a4 10145 else
351f65ca 10146 return format;
3e73aa7c 10147 }
e57f8c65
TG		 10148#endif
10149#if defined (OBJ_MACH_O)
10150 case bfd_target_mach_o_flavour:
d382c579
TG		 10151 if (flag_code == CODE_64BIT)
10152 {
10153 use_rela_relocations = 1;
10154 object_64bit = 1;
10155 return "mach-o-x86-64";
10156 }
10157 else
10158 return "mach-o-i386";
4c63da97 10159#endif
252b5132
RH		 10160 default:
10161 abort ();
10162 return NULL;
10163 }
10164}
10165
47926f60 10166#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10167
10168#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10169void
10170i386_elf_emit_arch_note (void)
a847613f 10171{
718ddfc0 10172 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10173 {
10174 char *p;
10175 asection *seg = now_seg;
10176 subsegT subseg = now_subseg;
10177 Elf_Internal_Note i_note;
10178 Elf_External_Note e_note;
10179 asection *note_secp;
10180 int len;
10181
10182 /* Create the .note section. */
10183 note_secp = subseg_new (".note", 0);
10184 bfd_set_section_flags (stdoutput,
10185 note_secp,
10186 SEC_HAS_CONTENTS | SEC_READONLY);
10187
10188 /* Process the arch string. */
10189 len = strlen (cpu_arch_name);
10190
10191 i_note.namesz = len + 1;
10192 i_note.descsz = 0;
10193 i_note.type = NT_ARCH;
10194 p = frag_more (sizeof (e_note.namesz));
10195 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10196 p = frag_more (sizeof (e_note.descsz));
10197 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10198 p = frag_more (sizeof (e_note.type));
10199 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10200 p = frag_more (len + 1);
10201 strcpy (p, cpu_arch_name);
10202
10203 frag_align (2, 0, 0);
10204
10205 subseg_set (seg, subseg);
10206 }
10207}
10208#endif
252b5132 10209\f
252b5132 10210symbolS *
7016a5d5 10211md_undefined_symbol (char *name)
252b5132 10212{
18dc2407
ILT		 10213 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10214 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10215 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10216 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10217 {
10218 if (!GOT_symbol)
10219 {
10220 if (symbol_find (name))
10221 as_bad (_("GOT already in symbol table"));
10222 GOT_symbol = symbol_new (name, undefined_section,
10223 (valueT) 0, &zero_address_frag);
10224 };
10225 return GOT_symbol;
10226 }
252b5132
RH		 10227 return 0;
10228}
10229
10230/* Round up a section size to the appropriate boundary. */
47926f60 10231
252b5132 10232valueT
7016a5d5 10233md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10234{
4c63da97
AM		 10235#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10236 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10237 {
10238 /* For a.out, force the section size to be aligned. If we don't do
10239 this, BFD will align it for us, but it will not write out the
10240 final bytes of the section. This may be a bug in BFD, but it is
10241 easier to fix it here since that is how the other a.out targets
10242 work. */
10243 int align;
10244
10245 align = bfd_get_section_alignment (stdoutput, segment);
10246 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10247 }
252b5132
RH		 10248#endif
10249
10250 return size;
10251}
10252
10253/* On the i386, PC-relative offsets are relative to the start of the
10254 next instruction. That is, the address of the offset, plus its
10255 size, since the offset is always the last part of the insn. */
10256
10257long
e3bb37b5 10258md_pcrel_from (fixS *fixP)
252b5132
RH		 10259{
10260 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10261}
10262
10263#ifndef I386COFF
10264
10265static void
e3bb37b5 10266s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10267{
29b0f896 10268 int temp;
252b5132 10269
8a75718c
JB		 10270#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10271 if (IS_ELF)
10272 obj_elf_section_change_hook ();
10273#endif
252b5132
RH		 10274 temp = get_absolute_expression ();
10275 subseg_set (bss_section, (subsegT) temp);
10276 demand_empty_rest_of_line ();
10277}
10278
10279#endif
10280
252b5132 10281void
e3bb37b5 10282i386_validate_fix (fixS *fixp)
252b5132
RH		 10283{
10284 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10285 {
23df1078
JH		 10286 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10287 {
4fa24527 10288 if (!object_64bit)
23df1078
JH		 10289 abort ();
10290 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10291 }
10292 else
10293 {
4fa24527 10294 if (!object_64bit)
d6ab8113
JB		 10295 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10296 else
10297 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10298 }
252b5132
RH		 10299 fixp->fx_subsy = 0;
10300 }
10301}
10302
252b5132 10303arelent *
7016a5d5 10304tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10305{
10306 arelent *rel;
10307 bfd_reloc_code_real_type code;
10308
10309 switch (fixp->fx_r_type)
10310 {
8ce3d284 10311#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10312 case BFD_RELOC_SIZE32:
10313 case BFD_RELOC_SIZE64:
10314 if (S_IS_DEFINED (fixp->fx_addsy)
10315 && !S_IS_EXTERNAL (fixp->fx_addsy))
10316 {
10317 /* Resolve size relocation against local symbol to size of
10318 the symbol plus addend. */
10319 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10320 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10321 && !fits_in_unsigned_long (value))
10322 as_bad_where (fixp->fx_file, fixp->fx_line,
10323 _("symbol size computation overflow"));
10324 fixp->fx_addsy = NULL;
10325 fixp->fx_subsy = NULL;
10326 md_apply_fix (fixp, (valueT *) &value, NULL);
10327 return NULL;
10328 }
8ce3d284 10329#endif
8fd4256d 10330
3e73aa7c
JH		 10331 case BFD_RELOC_X86_64_PLT32:
10332 case BFD_RELOC_X86_64_GOT32:
10333 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10334 case BFD_RELOC_386_PLT32:
10335 case BFD_RELOC_386_GOT32:
10336 case BFD_RELOC_386_GOTOFF:
10337 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10338 case BFD_RELOC_386_TLS_GD:
10339 case BFD_RELOC_386_TLS_LDM:
10340 case BFD_RELOC_386_TLS_LDO_32:
10341 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10342 case BFD_RELOC_386_TLS_IE:
10343 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10344 case BFD_RELOC_386_TLS_LE_32:
10345 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10346 case BFD_RELOC_386_TLS_GOTDESC:
10347 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10348 case BFD_RELOC_X86_64_TLSGD:
10349 case BFD_RELOC_X86_64_TLSLD:
10350 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10351 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10352 case BFD_RELOC_X86_64_GOTTPOFF:
10353 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10354 case BFD_RELOC_X86_64_TPOFF64:
10355 case BFD_RELOC_X86_64_GOTOFF64:
10356 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10357 case BFD_RELOC_X86_64_GOT64:
10358 case BFD_RELOC_X86_64_GOTPCREL64:
10359 case BFD_RELOC_X86_64_GOTPC64:
10360 case BFD_RELOC_X86_64_GOTPLT64:
10361 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10362 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10363 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10364 case BFD_RELOC_RVA:
10365 case BFD_RELOC_VTABLE_ENTRY:
10366 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10367#ifdef TE_PE
10368 case BFD_RELOC_32_SECREL:
10369#endif
252b5132
RH		 10370 code = fixp->fx_r_type;
10371 break;
dbbaec26
L		 10372 case BFD_RELOC_X86_64_32S:
10373 if (!fixp->fx_pcrel)
10374 {
10375 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10376 code = fixp->fx_r_type;
10377 break;
10378 }
252b5132 10379 default:
93382f6d 10380 if (fixp->fx_pcrel)
252b5132 10381 {
93382f6d
AM		 10382 switch (fixp->fx_size)
10383 {
10384 default:
b091f402
AM		 10385 as_bad_where (fixp->fx_file, fixp->fx_line,
10386 _("can not do %d byte pc-relative relocation"),
10387 fixp->fx_size);
93382f6d
AM		 10388 code = BFD_RELOC_32_PCREL;
10389 break;
10390 case 1: code = BFD_RELOC_8_PCREL; break;
10391 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10392 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10393#ifdef BFD64
10394 case 8: code = BFD_RELOC_64_PCREL; break;
10395#endif
93382f6d
AM		 10396 }
10397 }
10398 else
10399 {
10400 switch (fixp->fx_size)
10401 {
10402 default:
b091f402
AM		 10403 as_bad_where (fixp->fx_file, fixp->fx_line,
10404 _("can not do %d byte relocation"),
10405 fixp->fx_size);
93382f6d
AM		 10406 code = BFD_RELOC_32;
10407 break;
10408 case 1: code = BFD_RELOC_8; break;
10409 case 2: code = BFD_RELOC_16; break;
10410 case 4: code = BFD_RELOC_32; break;
937149dd 10411#ifdef BFD64
3e73aa7c 10412 case 8: code = BFD_RELOC_64; break;
937149dd 10413#endif
93382f6d 10414 }
252b5132
RH		 10415 }
10416 break;
10417 }
252b5132 10418
d182319b
JB		 10419 if ((code == BFD_RELOC_32
10420 || code == BFD_RELOC_32_PCREL
10421 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10422 && GOT_symbol
10423 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10424 {
4fa24527 10425 if (!object_64bit)
d6ab8113
JB		 10426 code = BFD_RELOC_386_GOTPC;
10427 else
10428 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10429 }
7b81dfbb
AJ		 10430 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10431 && GOT_symbol
10432 && fixp->fx_addsy == GOT_symbol)
10433 {
10434 code = BFD_RELOC_X86_64_GOTPC64;
10435 }
252b5132
RH		 10436
10437 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10438 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10439 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10440
10441 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10442
3e73aa7c
JH		 10443 if (!use_rela_relocations)
10444 {
10445 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10446 vtable entry to be used in the relocation's section offset. */
10447 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10448 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10449#if defined (OBJ_COFF) && defined (TE_PE)
10450 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10451 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10452 else
10453#endif
c6682705 10454 rel->addend = 0;
3e73aa7c
JH		 10455 }
10456 /* Use the rela in 64bit mode. */
252b5132 10457 else
3e73aa7c 10458 {
862be3fb
L		 10459 if (disallow_64bit_reloc)
10460 switch (code)
10461 {
862be3fb
L		 10462 case BFD_RELOC_X86_64_DTPOFF64:
10463 case BFD_RELOC_X86_64_TPOFF64:
10464 case BFD_RELOC_64_PCREL:
10465 case BFD_RELOC_X86_64_GOTOFF64:
10466 case BFD_RELOC_X86_64_GOT64:
10467 case BFD_RELOC_X86_64_GOTPCREL64:
10468 case BFD_RELOC_X86_64_GOTPC64:
10469 case BFD_RELOC_X86_64_GOTPLT64:
10470 case BFD_RELOC_X86_64_PLTOFF64:
10471 as_bad_where (fixp->fx_file, fixp->fx_line,
10472 _("cannot represent relocation type %s in x32 mode"),
10473 bfd_get_reloc_code_name (code));
10474 break;
10475 default:
10476 break;
10477 }
10478
062cd5e7
AS		 10479 if (!fixp->fx_pcrel)
10480 rel->addend = fixp->fx_offset;
10481 else
10482 switch (code)
10483 {
10484 case BFD_RELOC_X86_64_PLT32:
10485 case BFD_RELOC_X86_64_GOT32:
10486 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10487 case BFD_RELOC_X86_64_TLSGD:
10488 case BFD_RELOC_X86_64_TLSLD:
10489 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10490 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10491 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10492 rel->addend = fixp->fx_offset - fixp->fx_size;
10493 break;
10494 default:
10495 rel->addend = (section->vma
10496 - fixp->fx_size
10497 + fixp->fx_addnumber
10498 + md_pcrel_from (fixp));
10499 break;
10500 }
3e73aa7c
JH		 10501 }
10502
252b5132
RH		 10503 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10504 if (rel->howto == NULL)
10505 {
10506 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10507 _("cannot represent relocation type %s"),
252b5132
RH		 10508 bfd_get_reloc_code_name (code));
10509 /* Set howto to a garbage value so that we can keep going. */
10510 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10511 gas_assert (rel->howto != NULL);
252b5132
RH		 10512 }
10513
10514 return rel;
10515}
10516
ee86248c 10517#include "tc-i386-intel.c"
54cfded0 10518
a60de03c
JB		 10519void
10520tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10521{
a60de03c
JB		 10522 int saved_naked_reg;
10523 char saved_register_dot;
54cfded0 10524
a60de03c
JB		 10525 saved_naked_reg = allow_naked_reg;
10526 allow_naked_reg = 1;
10527 saved_register_dot = register_chars['.'];
10528 register_chars['.'] = '.';
10529 allow_pseudo_reg = 1;
10530 expression_and_evaluate (exp);
10531 allow_pseudo_reg = 0;
10532 register_chars['.'] = saved_register_dot;
10533 allow_naked_reg = saved_naked_reg;
10534
e96d56a1 10535 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10536 {
a60de03c
JB		 10537 if ((addressT) exp->X_add_number < i386_regtab_size)
10538 {
10539 exp->X_op = O_constant;
10540 exp->X_add_number = i386_regtab[exp->X_add_number]
10541 .dw2_regnum[flag_code >> 1];
10542 }
10543 else
10544 exp->X_op = O_illegal;
54cfded0 10545 }
54cfded0
AM		 10546}
10547
10548void
10549tc_x86_frame_initial_instructions (void)
10550{
a60de03c
JB		 10551 static unsigned int sp_regno[2];
10552
10553 if (!sp_regno[flag_code >> 1])
10554 {
10555 char *saved_input = input_line_pointer;
10556 char sp[][4] = {"esp", "rsp"};
10557 expressionS exp;
a4447b93 10558
a60de03c
JB		 10559 input_line_pointer = sp[flag_code >> 1];
10560 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10561 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10562 sp_regno[flag_code >> 1] = exp.X_add_number;
10563 input_line_pointer = saved_input;
10564 }
a4447b93 10565
61ff971f
L		 10566 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10567 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10568}
d2b2c203 10569
d7921315
L		 10570int
10571x86_dwarf2_addr_size (void)
10572{
10573#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10574 if (x86_elf_abi == X86_64_X32_ABI)
10575 return 4;
10576#endif
10577 return bfd_arch_bits_per_address (stdoutput) / 8;
10578}
10579
d2b2c203
DJ		 10580int
10581i386_elf_section_type (const char *str, size_t len)
10582{
10583 if (flag_code == CODE_64BIT
10584 && len == sizeof ("unwind") - 1
10585 && strncmp (str, "unwind", 6) == 0)
10586 return SHT_X86_64_UNWIND;
10587
10588 return -1;
10589}
bb41ade5 10590
ad5fec3b
EB		 10591#ifdef TE_SOLARIS
10592void
10593i386_solaris_fix_up_eh_frame (segT sec)
10594{
10595 if (flag_code == CODE_64BIT)
10596 elf_section_type (sec) = SHT_X86_64_UNWIND;
10597}
10598#endif
10599
bb41ade5
AM		 10600#ifdef TE_PE
10601void
10602tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10603{
91d6fa6a 10604 expressionS exp;
bb41ade5 10605
91d6fa6a
NC		 10606 exp.X_op = O_secrel;
10607 exp.X_add_symbol = symbol;
10608 exp.X_add_number = 0;
10609 emit_expr (&exp, size);
bb41ade5
AM		 10610}
10611#endif
3b22753a
L		 10612
10613#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10614/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10615
01e1a5bc 10616bfd_vma
3b22753a
L		 10617x86_64_section_letter (int letter, char **ptr_msg)
10618{
10619 if (flag_code == CODE_64BIT)
10620 {
10621 if (letter == 'l')
10622 return SHF_X86_64_LARGE;
10623
8f3bae45 10624 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10625 }
3b22753a 10626 else
8f3bae45 10627 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10628 return -1;
10629}
10630
01e1a5bc 10631bfd_vma
3b22753a
L		 10632x86_64_section_word (char *str, size_t len)
10633{
8620418b 10634 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10635 return SHF_X86_64_LARGE;
10636
10637 return -1;
10638}
10639
10640static void
10641handle_large_common (int small ATTRIBUTE_UNUSED)
10642{
10643 if (flag_code != CODE_64BIT)
10644 {
10645 s_comm_internal (0, elf_common_parse);
10646 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10647 }
10648 else
10649 {
10650 static segT lbss_section;
10651 asection *saved_com_section_ptr = elf_com_section_ptr;
10652 asection *saved_bss_section = bss_section;
10653
10654 if (lbss_section == NULL)
10655 {
10656 flagword applicable;
10657 segT seg = now_seg;
10658 subsegT subseg = now_subseg;
10659
10660 /* The .lbss section is for local .largecomm symbols. */
10661 lbss_section = subseg_new (".lbss", 0);
10662 applicable = bfd_applicable_section_flags (stdoutput);
10663 bfd_set_section_flags (stdoutput, lbss_section,
10664 applicable & SEC_ALLOC);
10665 seg_info (lbss_section)->bss = 1;
10666
10667 subseg_set (seg, subseg);
10668 }
10669
10670 elf_com_section_ptr = &_bfd_elf_large_com_section;
10671 bss_section = lbss_section;
10672
10673 s_comm_internal (0, elf_common_parse);
10674
10675 elf_com_section_ptr = saved_com_section_ptr;
10676 bss_section = saved_bss_section;
10677 }
10678}
10679#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.648502 seconds and 4 git commands to generate.