projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
2009-02-23 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
6305a203
L		 153/* x86 arch names, types and features */
154typedef struct
155{
156 const char *name; /* arch name */
157 enum processor_type type; /* arch type */
158 i386_cpu_flags flags; /* cpu feature flags */
159}
160arch_entry;
161
e3bb37b5
L		 162static void set_code_flag (int);
163static void set_16bit_gcc_code_flag (int);
164static void set_intel_syntax (int);
1efbbeb4 165static void set_intel_mnemonic (int);
db51cc60 166static void set_allow_index_reg (int);
cb19c032 167static void set_sse_check (int);
e3bb37b5 168static void set_cpu_arch (int);
6482c264 169#ifdef TE_PE
e3bb37b5 170static void pe_directive_secrel (int);
6482c264 171#endif
e3bb37b5
L		 172static void signed_cons (int);
173static char *output_invalid (int c);
a7619375 174static int i386_att_operand (char *);
e3bb37b5
L		 175static int i386_intel_operand (char *, int);
176static const reg_entry *parse_register (char *, char **);
177static char *parse_insn (char *, char *);
178static char *parse_operands (char *, const char *);
179static void swap_operands (void);
4d456e3d 180static void swap_2_operands (int, int);
e3bb37b5
L		 181static void optimize_imm (void);
182static void optimize_disp (void);
fa99fab2 183static const template *match_template (void);
e3bb37b5
L		 184static int check_string (void);
185static int process_suffix (void);
186static int check_byte_reg (void);
187static int check_long_reg (void);
188static int check_qword_reg (void);
189static int check_word_reg (void);
190static int finalize_imm (void);
85f10a01 191static void process_drex (void);
e3bb37b5
L		 192static int process_operands (void);
193static const seg_entry *build_modrm_byte (void);
194static void output_insn (void);
195static void output_imm (fragS *, offsetT);
196static void output_disp (fragS *, offsetT);
29b0f896 197#ifndef I386COFF
e3bb37b5 198static void s_bss (int);
252b5132 199#endif
17d4e2a2
L		 200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201static void handle_large_common (int small ATTRIBUTE_UNUSED);
202#endif
252b5132 203
a847613f 204static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 205
c0f3af97
L		 206/* VEX prefix. */
207typedef struct
208{
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes[3];
211 unsigned int length;
212 /* Destination or source register specifier. */
213 const reg_entry *register_specifier;
214} vex_prefix;
215
252b5132 216/* 'md_assemble ()' gathers together information and puts it into a
47926f60 217 i386_insn. */
252b5132 218
520dc8e8
AM		 219union i386_op
220 {
221 expressionS *disps;
222 expressionS *imms;
223 const reg_entry *regs;
224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 229 template tm;
230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
252b5132
RH		 276
277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
85f10a01 280 drex_byte drex;
c0f3af97 281 vex_prefix vex;
b6169b20
L		 282
283 /* Swap operand in encoding. */
284 unsigned int swap_operand : 1;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60
KH		 379/* Current operand we are working on. */
380static int this_operand;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
394/* The names used to print error messages. */
b77a7acd 395static const char *flag_code_names[] =
3e73aa7c
JH		 396 {
397 "32",
398 "16",
399 "64"
400 };
252b5132 401
47926f60
KH		 402/* 1 for intel syntax,
403 0 if att syntax. */
404static int intel_syntax = 0;
252b5132 405
1efbbeb4
L		 406/* 1 for intel mnemonic,
407 0 if att mnemonic. */
408static int intel_mnemonic = !SYSV386_COMPAT;
409
5209009a 410/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 411static int old_gcc = OLDGCC_COMPAT;
412
a60de03c
JB		 413/* 1 if pseudo registers are permitted. */
414static int allow_pseudo_reg = 0;
415
47926f60
KH		 416/* 1 if register prefix % not required. */
417static int allow_naked_reg = 0;
252b5132 418
ba104c83 419/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 420static int allow_index_reg = 0;
421
daf50ae7
L		 422static enum
423 {
424 sse_check_none = 0,
425 sse_check_warning,
426 sse_check_error
427 }
428sse_check;
429
2ca3ace5
L		 430/* Register prefix used for error message. */
431static const char *register_prefix = "%";
432
47926f60
KH		 433/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436static char stackop_size = '\0';
eecb386c 437
12b55ccc
L		 438/* Non-zero to optimize code alignment. */
439int optimize_align_code = 1;
440
47926f60
KH		 441/* Non-zero to quieten some warnings. */
442static int quiet_warnings = 0;
a38cf1db 443
47926f60
KH		 444/* CPU name. */
445static const char *cpu_arch_name = NULL;
6305a203 446static char *cpu_sub_arch_name = NULL;
a38cf1db 447
47926f60 448/* CPU feature flags. */
40fb9820
L		 449static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
450
ccc9c027
L		 451/* If we have selected a cpu we are generating instructions for. */
452static int cpu_arch_tune_set = 0;
453
9103f4f4 454/* Cpu we are generating instructions for. */
fbf3f584 455enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 456
457/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 458static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 459
ccc9c027 460/* CPU instruction set architecture used. */
fbf3f584 461enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 462
9103f4f4 463/* CPU feature flags of instruction set architecture used. */
fbf3f584 464i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 465
fddf5b5b
AM		 466/* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468static unsigned int no_cond_jump_promotion = 0;
469
c0f3af97
L		 470/* Encode SSE instructions with VEX prefix. */
471static unsigned int sse2avx;
472
29b0f896 473/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 474static symbolS *GOT_symbol;
29b0f896 475
a4447b93
RH		 476/* The dwarf2 return column, adjusted for 32 or 64 bit. */
477unsigned int x86_dwarf2_return_column;
478
479/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480int x86_cie_data_alignment;
481
252b5132 482/* Interface to relax_segment.
fddf5b5b
AM		 483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
252b5132 486
47926f60 487/* Types. */
93c2a809
AM		 488#define UNCOND_JUMP 0
489#define COND_JUMP 1
490#define COND_JUMP86 2
fddf5b5b 491
47926f60 492/* Sizes. */
252b5132
RH		 493#define CODE16 1
494#define SMALL 0
29b0f896 495#define SMALL16 (SMALL | CODE16)
252b5132 496#define BIG 2
29b0f896 497#define BIG16 (BIG | CODE16)
252b5132
RH		 498
499#ifndef INLINE
500#ifdef __GNUC__
501#define INLINE __inline__
502#else
503#define INLINE
504#endif
505#endif
506
fddf5b5b
AM		 507#define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509#define TYPE_FROM_RELAX_STATE(s) \
510 ((s) >> 2)
511#define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 513
514/* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
521
522const relax_typeS md_relax_table[] =
523{
24eab124
AM		 524 /* The fields are:
525 1) most positive reach of this state,
526 2) most negative reach of this state,
93c2a809 527 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 528 4) which index into the table to try if we can't fit into this one. */
252b5132 529
fddf5b5b 530 /* UNCOND_JUMP states. */
93c2a809
AM		 531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
252b5132 535 {0, 0, 4, 0},
93c2a809
AM		 536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 538 {0, 0, 2, 0},
539
93c2a809
AM		 540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
545 {0, 0, 5, 0},
fddf5b5b 546 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 547 1 extra opcode byte, 2 displacement bytes. */
548 {0, 0, 3, 0},
549
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
555 {0, 0, 5, 0},
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
558 {0, 0, 4, 0}
252b5132
RH		 559};
560
9103f4f4
L		 561static const arch_entry cpu_arch[] =
562{
6305a203
L		 563 { "generic32", PROCESSOR_GENERIC32,
564 CPU_GENERIC32_FLAGS },
565 { "generic64", PROCESSOR_GENERIC64,
566 CPU_GENERIC64_FLAGS },
567 { "i8086", PROCESSOR_UNKNOWN,
568 CPU_NONE_FLAGS },
569 { "i186", PROCESSOR_UNKNOWN,
570 CPU_I186_FLAGS },
571 { "i286", PROCESSOR_UNKNOWN,
572 CPU_I286_FLAGS },
573 { "i386", PROCESSOR_I386,
574 CPU_I386_FLAGS },
575 { "i486", PROCESSOR_I486,
576 CPU_I486_FLAGS },
577 { "i586", PROCESSOR_PENTIUM,
578 CPU_I586_FLAGS },
579 { "i686", PROCESSOR_PENTIUMPRO,
580 CPU_I686_FLAGS },
581 { "pentium", PROCESSOR_PENTIUM,
582 CPU_I586_FLAGS },
583 { "pentiumpro", PROCESSOR_PENTIUMPRO,
584 CPU_I686_FLAGS },
585 { "pentiumii", PROCESSOR_PENTIUMPRO,
586 CPU_P2_FLAGS },
587 { "pentiumiii",PROCESSOR_PENTIUMPRO,
588 CPU_P3_FLAGS },
589 { "pentium4", PROCESSOR_PENTIUM4,
590 CPU_P4_FLAGS },
591 { "prescott", PROCESSOR_NOCONA,
592 CPU_CORE_FLAGS },
593 { "nocona", PROCESSOR_NOCONA,
594 CPU_NOCONA_FLAGS },
595 { "yonah", PROCESSOR_CORE,
596 CPU_CORE_FLAGS },
597 { "core", PROCESSOR_CORE,
598 CPU_CORE_FLAGS },
599 { "merom", PROCESSOR_CORE2,
600 CPU_CORE2_FLAGS },
601 { "core2", PROCESSOR_CORE2,
602 CPU_CORE2_FLAGS },
bd5295b2
L		 603 { "corei7", PROCESSOR_COREI7,
604 CPU_COREI7_FLAGS },
6305a203
L		 605 { "k6", PROCESSOR_K6,
606 CPU_K6_FLAGS },
607 { "k6_2", PROCESSOR_K6,
608 CPU_K6_2_FLAGS },
609 { "athlon", PROCESSOR_ATHLON,
610 CPU_ATHLON_FLAGS },
611 { "sledgehammer", PROCESSOR_K8,
612 CPU_K8_FLAGS },
613 { "opteron", PROCESSOR_K8,
614 CPU_K8_FLAGS },
615 { "k8", PROCESSOR_K8,
616 CPU_K8_FLAGS },
617 { "amdfam10", PROCESSOR_AMDFAM10,
618 CPU_AMDFAM10_FLAGS },
619 { ".mmx", PROCESSOR_UNKNOWN,
620 CPU_MMX_FLAGS },
621 { ".sse", PROCESSOR_UNKNOWN,
622 CPU_SSE_FLAGS },
623 { ".sse2", PROCESSOR_UNKNOWN,
624 CPU_SSE2_FLAGS },
625 { ".sse3", PROCESSOR_UNKNOWN,
626 CPU_SSE3_FLAGS },
627 { ".ssse3", PROCESSOR_UNKNOWN,
628 CPU_SSSE3_FLAGS },
629 { ".sse4.1", PROCESSOR_UNKNOWN,
630 CPU_SSE4_1_FLAGS },
631 { ".sse4.2", PROCESSOR_UNKNOWN,
632 CPU_SSE4_2_FLAGS },
633 { ".sse4", PROCESSOR_UNKNOWN,
634 CPU_SSE4_2_FLAGS },
c0f3af97
L		 635 { ".avx", PROCESSOR_UNKNOWN,
636 CPU_AVX_FLAGS },
6305a203
L		 637 { ".vmx", PROCESSOR_UNKNOWN,
638 CPU_VMX_FLAGS },
639 { ".smx", PROCESSOR_UNKNOWN,
640 CPU_SMX_FLAGS },
f03fe4c1
L		 641 { ".xsave", PROCESSOR_UNKNOWN,
642 CPU_XSAVE_FLAGS },
c0f3af97
L		 643 { ".aes", PROCESSOR_UNKNOWN,
644 CPU_AES_FLAGS },
594ab6a3
L		 645 { ".pclmul", PROCESSOR_UNKNOWN,
646 CPU_PCLMUL_FLAGS },
c0f3af97 647 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 648 CPU_PCLMUL_FLAGS },
c0f3af97
L		 649 { ".fma", PROCESSOR_UNKNOWN,
650 CPU_FMA_FLAGS },
f1f8f695
L		 651 { ".movbe", PROCESSOR_UNKNOWN,
652 CPU_MOVBE_FLAGS },
653 { ".ept", PROCESSOR_UNKNOWN,
654 CPU_EPT_FLAGS },
bd5295b2
L		 655 { ".clflush", PROCESSOR_UNKNOWN,
656 CPU_CLFLUSH_FLAGS },
657 { ".syscall", PROCESSOR_UNKNOWN,
658 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 659 { ".rdtscp", PROCESSOR_UNKNOWN,
660 CPU_RDTSCP_FLAGS },
6305a203
L		 661 { ".3dnow", PROCESSOR_UNKNOWN,
662 CPU_3DNOW_FLAGS },
663 { ".3dnowa", PROCESSOR_UNKNOWN,
664 CPU_3DNOWA_FLAGS },
665 { ".padlock", PROCESSOR_UNKNOWN,
666 CPU_PADLOCK_FLAGS },
667 { ".pacifica", PROCESSOR_UNKNOWN,
668 CPU_SVME_FLAGS },
669 { ".svme", PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS },
671 { ".sse4a", PROCESSOR_UNKNOWN,
672 CPU_SSE4A_FLAGS },
673 { ".abm", PROCESSOR_UNKNOWN,
674 CPU_ABM_FLAGS },
675 { ".sse5", PROCESSOR_UNKNOWN,
676 CPU_SSE5_FLAGS },
e413e4e9
AM		 677};
678
704209c0 679#ifdef I386COFF
a6c24e68
NC		 680/* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
682
683static symbolS *
684pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
685{
686 addressT align = 0;
687
688 SKIP_WHITESPACE ();
689
690 if (needs_align
691 && *input_line_pointer == ',')
692 {
693 align = parse_align (needs_align - 1);
694
695 if (align == (addressT) -1)
696 return NULL;
697 }
698 else
699 {
700 if (size >= 8)
701 align = 3;
702 else if (size >= 4)
703 align = 2;
704 else if (size >= 2)
705 align = 1;
706 else
707 align = 0;
708 }
709
710 bss_alloc (symbolP, size, align);
711 return symbolP;
712}
713
704209c0 714static void
a6c24e68
NC		 715pe_lcomm (int needs_align)
716{
717 s_comm_internal (needs_align * 2, pe_lcomm_internal);
718}
704209c0 719#endif
a6c24e68 720
29b0f896
AM		 721const pseudo_typeS md_pseudo_table[] =
722{
723#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes, 0},
725#else
726 {"align", s_align_ptwo, 0},
727#endif
728 {"arch", set_cpu_arch, 0},
729#ifndef I386COFF
730 {"bss", s_bss, 0},
a6c24e68
NC		 731#else
732 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 733#endif
734 {"ffloat", float_cons, 'f'},
735 {"dfloat", float_cons, 'd'},
736 {"tfloat", float_cons, 'x'},
737 {"value", cons, 2},
d182319b 738 {"slong", signed_cons, 4},
29b0f896
AM		 739 {"noopt", s_ignore, 0},
740 {"optim", s_ignore, 0},
741 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
742 {"code16", set_code_flag, CODE_16BIT},
743 {"code32", set_code_flag, CODE_32BIT},
744 {"code64", set_code_flag, CODE_64BIT},
745 {"intel_syntax", set_intel_syntax, 1},
746 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 747 {"intel_mnemonic", set_intel_mnemonic, 1},
748 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 749 {"allow_index_reg", set_allow_index_reg, 1},
750 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 751 {"sse_check", set_sse_check, 0},
3b22753a
L		 752#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common, 0},
07a53e5c 754#else
e3bb37b5 755 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 756 {"loc", dwarf2_directive_loc, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 758#endif
6482c264
NC		 759#ifdef TE_PE
760 {"secrel32", pe_directive_secrel, 0},
761#endif
29b0f896
AM		 762 {0, 0, 0}
763};
764
765/* For interface with expression (). */
766extern char *input_line_pointer;
767
768/* Hash table for instruction mnemonic lookup. */
769static struct hash_control *op_hash;
770
771/* Hash table for register lookup. */
772static struct hash_control *reg_hash;
773\f
252b5132 774void
e3bb37b5 775i386_align_code (fragS *fragP, int count)
252b5132 776{
ce8a8b2f
AM		 777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
252b5132
RH		 780 static const char f32_1[] =
781 {0x90}; /* nop */
782 static const char f32_2[] =
ccc9c027 783 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 784 static const char f32_3[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5[] =
789 {0x90, /* nop */
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8[] =
796 {0x90, /* nop */
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 816 static const char f16_3[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 818 static const char f16_4[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5[] =
821 {0x90, /* nop */
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 832 static const char jump_31[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 837 static const char *const f32_patt[] = {
838 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 839 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 840 };
841 static const char *const f16_patt[] = {
76bc74dc 842 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 843 };
ccc9c027
L		 844 /* nopl (%[re]ax) */
845 static const char alt_3[] =
846 {0x0f,0x1f,0x00};
847 /* nopl 0(%[re]ax) */
848 static const char alt_4[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 /* data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11[] =
871 {0x66,
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 /* data16
874 data16
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12[] =
877 {0x66,
878 0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 data16
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13[] =
885 {0x66,
886 0x66,
887 0x66,
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* data16
890 data16
891 data16
892 data16
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14[] =
895 {0x66,
896 0x66,
897 0x66,
898 0x66,
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* data16
901 data16
902 data16
903 data16
904 data16
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15[] =
907 {0x66,
908 0x66,
909 0x66,
910 0x66,
911 0x66,
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
924 nopl 0L(%[re]ax) */
925 static const char alt_short_13[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 /* nopl 0L(%[re]ax)
929 nopl 0L(%[re]ax) */
930 static const char alt_short_14[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
933 /* nopl 0L(%[re]ax)
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt[] = {
939 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
940 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
941 alt_short_14, alt_short_15
942 };
943 static const char *const alt_long_patt[] = {
944 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
945 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
946 alt_long_14, alt_long_15
947 };
252b5132 948
76bc74dc
L		 949 /* Only align for at least a positive non-zero boundary. */
950 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 951 return;
3e73aa7c 952
ccc9c027
L		 953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
4eed87de 955
76bc74dc
L		 956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 963
76bc74dc
L		 964 When -mtune= isn't used, alt_long_patt will be used if
965 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
966 be used.
ccc9c027
L		 967
968 When -march= or .arch is used, we can't use anything beyond
969 cpu_arch_isa_flags. */
970
971 if (flag_code == CODE_16BIT)
972 {
ccc9c027 973 if (count > 8)
33fef721 974 {
76bc74dc
L		 975 memcpy (fragP->fr_literal + fragP->fr_fix,
976 jump_31, count);
977 /* Adjust jump offset. */
978 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 979 }
76bc74dc
L		 980 else
981 memcpy (fragP->fr_literal + fragP->fr_fix,
982 f16_patt[count - 1], count);
252b5132 983 }
33fef721 984 else
ccc9c027
L		 985 {
986 const char *const *patt = NULL;
987
fbf3f584 988 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 989 {
990 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
991 switch (cpu_arch_tune)
992 {
993 case PROCESSOR_UNKNOWN:
994 /* We use cpu_arch_isa_flags to check if we SHOULD
995 optimize for Cpu686. */
fbf3f584 996 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 997 patt = alt_long_patt;
ccc9c027
L		 998 else
999 patt = f32_patt;
1000 break;
ccc9c027
L		 1001 case PROCESSOR_PENTIUMPRO:
1002 case PROCESSOR_PENTIUM4:
1003 case PROCESSOR_NOCONA:
ef05d495 1004 case PROCESSOR_CORE:
76bc74dc 1005 case PROCESSOR_CORE2:
bd5295b2 1006 case PROCESSOR_COREI7:
76bc74dc
L		 1007 case PROCESSOR_GENERIC64:
1008 patt = alt_long_patt;
1009 break;
ccc9c027
L		 1010 case PROCESSOR_K6:
1011 case PROCESSOR_ATHLON:
1012 case PROCESSOR_K8:
4eed87de 1013 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1014 patt = alt_short_patt;
1015 break;
76bc74dc 1016 case PROCESSOR_I386:
ccc9c027
L		 1017 case PROCESSOR_I486:
1018 case PROCESSOR_PENTIUM:
1019 case PROCESSOR_GENERIC32:
1020 patt = f32_patt;
1021 break;
4eed87de 1022 }
ccc9c027
L		 1023 }
1024 else
1025 {
fbf3f584 1026 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1027 {
1028 case PROCESSOR_UNKNOWN:
e6a14101 1029 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1030 PROCESSOR_UNKNOWN. */
1031 abort ();
1032 break;
1033
76bc74dc 1034 case PROCESSOR_I386:
ccc9c027
L		 1035 case PROCESSOR_I486:
1036 case PROCESSOR_PENTIUM:
ccc9c027
L		 1037 case PROCESSOR_K6:
1038 case PROCESSOR_ATHLON:
1039 case PROCESSOR_K8:
4eed87de 1040 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1041 case PROCESSOR_GENERIC32:
1042 /* We use cpu_arch_isa_flags to check if we CAN optimize
1043 for Cpu686. */
fbf3f584 1044 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1045 patt = alt_short_patt;
1046 else
1047 patt = f32_patt;
1048 break;
76bc74dc
L		 1049 case PROCESSOR_PENTIUMPRO:
1050 case PROCESSOR_PENTIUM4:
1051 case PROCESSOR_NOCONA:
1052 case PROCESSOR_CORE:
ef05d495 1053 case PROCESSOR_CORE2:
bd5295b2 1054 case PROCESSOR_COREI7:
fbf3f584 1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1056 patt = alt_long_patt;
1057 else
1058 patt = f32_patt;
1059 break;
1060 case PROCESSOR_GENERIC64:
76bc74dc 1061 patt = alt_long_patt;
ccc9c027 1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065
76bc74dc
L		 1066 if (patt == f32_patt)
1067 {
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1070 its offset. */
1071 if (count < 15)
1072 memcpy (fragP->fr_literal + fragP->fr_fix,
1073 patt[count - 1], count);
1074 else
1075 {
1076 memcpy (fragP->fr_literal + fragP->fr_fix,
1077 jump_31, count);
1078 /* Adjust jump offset. */
1079 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1080 }
1081 }
1082 else
1083 {
1084 /* Maximum length of an instruction is 15 byte. If the
1085 padding is greater than 15 bytes and we don't use jump,
1086 we have to break it into smaller pieces. */
1087 int padding = count;
1088 while (padding > 15)
1089 {
1090 padding -= 15;
1091 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1092 patt [14], 15);
1093 }
1094
1095 if (padding)
1096 memcpy (fragP->fr_literal + fragP->fr_fix,
1097 patt [padding - 1], padding);
1098 }
ccc9c027 1099 }
33fef721 1100 fragP->fr_var = count;
252b5132
RH		 1101}
1102
c6fb90c8 1103static INLINE int
0dfbf9d7 1104operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1105{
0dfbf9d7 1106 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1107 {
1108 case 3:
0dfbf9d7 1109 if (x->array[2])
c6fb90c8
L		 1110 return 0;
1111 case 2:
0dfbf9d7 1112 if (x->array[1])
c6fb90c8
L		 1113 return 0;
1114 case 1:
0dfbf9d7 1115 return !x->array[0];
c6fb90c8
L		 1116 default:
1117 abort ();
1118 }
40fb9820
L		 1119}
1120
c6fb90c8 1121static INLINE void
0dfbf9d7 1122operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1123{
0dfbf9d7 1124 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1125 {
1126 case 3:
0dfbf9d7 1127 x->array[2] = v;
c6fb90c8 1128 case 2:
0dfbf9d7 1129 x->array[1] = v;
c6fb90c8 1130 case 1:
0dfbf9d7 1131 x->array[0] = v;
c6fb90c8
L		 1132 break;
1133 default:
1134 abort ();
1135 }
1136}
40fb9820 1137
c6fb90c8 1138static INLINE int
0dfbf9d7
L		 1139operand_type_equal (const union i386_operand_type *x,
1140 const union i386_operand_type *y)
c6fb90c8 1141{
0dfbf9d7 1142 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1143 {
1144 case 3:
0dfbf9d7 1145 if (x->array[2] != y->array[2])
c6fb90c8
L		 1146 return 0;
1147 case 2:
0dfbf9d7 1148 if (x->array[1] != y->array[1])
c6fb90c8
L		 1149 return 0;
1150 case 1:
0dfbf9d7 1151 return x->array[0] == y->array[0];
c6fb90c8
L		 1152 break;
1153 default:
1154 abort ();
1155 }
1156}
40fb9820 1157
0dfbf9d7
L		 1158static INLINE int
1159cpu_flags_all_zero (const union i386_cpu_flags *x)
1160{
1161 switch (ARRAY_SIZE(x->array))
1162 {
1163 case 3:
1164 if (x->array[2])
1165 return 0;
1166 case 2:
1167 if (x->array[1])
1168 return 0;
1169 case 1:
1170 return !x->array[0];
1171 default:
1172 abort ();
1173 }
1174}
1175
1176static INLINE void
1177cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1178{
1179 switch (ARRAY_SIZE(x->array))
1180 {
1181 case 3:
1182 x->array[2] = v;
1183 case 2:
1184 x->array[1] = v;
1185 case 1:
1186 x->array[0] = v;
1187 break;
1188 default:
1189 abort ();
1190 }
1191}
1192
1193static INLINE int
1194cpu_flags_equal (const union i386_cpu_flags *x,
1195 const union i386_cpu_flags *y)
1196{
1197 switch (ARRAY_SIZE(x->array))
1198 {
1199 case 3:
1200 if (x->array[2] != y->array[2])
1201 return 0;
1202 case 2:
1203 if (x->array[1] != y->array[1])
1204 return 0;
1205 case 1:
1206 return x->array[0] == y->array[0];
1207 break;
1208 default:
1209 abort ();
1210 }
1211}
c6fb90c8
L		 1212
1213static INLINE int
1214cpu_flags_check_cpu64 (i386_cpu_flags f)
1215{
1216 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1217 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1218}
1219
c6fb90c8
L		 1220static INLINE i386_cpu_flags
1221cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1222{
c6fb90c8
L		 1223 switch (ARRAY_SIZE (x.array))
1224 {
1225 case 3:
1226 x.array [2] &= y.array [2];
1227 case 2:
1228 x.array [1] &= y.array [1];
1229 case 1:
1230 x.array [0] &= y.array [0];
1231 break;
1232 default:
1233 abort ();
1234 }
1235 return x;
1236}
40fb9820 1237
c6fb90c8
L		 1238static INLINE i386_cpu_flags
1239cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1240{
c6fb90c8 1241 switch (ARRAY_SIZE (x.array))
40fb9820 1242 {
c6fb90c8
L		 1243 case 3:
1244 x.array [2] |= y.array [2];
1245 case 2:
1246 x.array [1] |= y.array [1];
1247 case 1:
1248 x.array [0] |= y.array [0];
40fb9820
L		 1249 break;
1250 default:
1251 abort ();
1252 }
40fb9820
L		 1253 return x;
1254}
1255
c0f3af97
L		 1256#define CPU_FLAGS_ARCH_MATCH 0x1
1257#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1258#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1259#define CPU_FLAGS_PCLMUL_MATCH 0x8
1260#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1261
a5ff0eb2 1262#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1263 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1264 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1265#define CPU_FLAGS_PERFECT_MATCH \
1266 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1267
1268/* Return CPU flags match bits. */
3629bb00 1269
40fb9820 1270static int
c0f3af97 1271cpu_flags_match (const template *t)
40fb9820 1272{
c0f3af97
L		 1273 i386_cpu_flags x = t->cpu_flags;
1274 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1275
1276 x.bitfield.cpu64 = 0;
1277 x.bitfield.cpuno64 = 0;
1278
0dfbf9d7 1279 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1280 {
1281 /* This instruction is available on all archs. */
1282 match |= CPU_FLAGS_32BIT_MATCH;
1283 }
3629bb00
L		 1284 else
1285 {
c0f3af97 1286 /* This instruction is available only on some archs. */
3629bb00
L		 1287 i386_cpu_flags cpu = cpu_arch_flags;
1288
1289 cpu.bitfield.cpu64 = 0;
1290 cpu.bitfield.cpuno64 = 0;
1291 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1292 if (!cpu_flags_all_zero (&cpu))
1293 {
a5ff0eb2
L		 1294 if (x.bitfield.cpuavx)
1295 {
ce2f5b3c 1296 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1297 if (cpu.bitfield.cpuavx)
1298 {
1299 /* Check SSE2AVX. */
1300 if (!t->opcode_modifier.sse2avx|| sse2avx)
1301 {
1302 match |= (CPU_FLAGS_ARCH_MATCH
1303 | CPU_FLAGS_AVX_MATCH);
1304 /* Check AES. */
1305 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1306 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1307 /* Check PCLMUL. */
1308 if (!x.bitfield.cpupclmul
1309 || cpu.bitfield.cpupclmul)
1310 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1311 }
1312 }
1313 else
1314 match |= CPU_FLAGS_ARCH_MATCH;
1315 }
1316 else
c0f3af97
L		 1317 match |= CPU_FLAGS_32BIT_MATCH;
1318 }
3629bb00 1319 }
c0f3af97 1320 return match;
40fb9820
L		 1321}
1322
c6fb90c8
L		 1323static INLINE i386_operand_type
1324operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1325{
c6fb90c8
L		 1326 switch (ARRAY_SIZE (x.array))
1327 {
1328 case 3:
1329 x.array [2] &= y.array [2];
1330 case 2:
1331 x.array [1] &= y.array [1];
1332 case 1:
1333 x.array [0] &= y.array [0];
1334 break;
1335 default:
1336 abort ();
1337 }
1338 return x;
40fb9820
L		 1339}
1340
c6fb90c8
L		 1341static INLINE i386_operand_type
1342operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1343{
c6fb90c8 1344 switch (ARRAY_SIZE (x.array))
40fb9820 1345 {
c6fb90c8
L		 1346 case 3:
1347 x.array [2] |= y.array [2];
1348 case 2:
1349 x.array [1] |= y.array [1];
1350 case 1:
1351 x.array [0] |= y.array [0];
40fb9820
L		 1352 break;
1353 default:
1354 abort ();
1355 }
c6fb90c8
L		 1356 return x;
1357}
40fb9820 1358
c6fb90c8
L		 1359static INLINE i386_operand_type
1360operand_type_xor (i386_operand_type x, i386_operand_type y)
1361{
1362 switch (ARRAY_SIZE (x.array))
1363 {
1364 case 3:
1365 x.array [2] ^= y.array [2];
1366 case 2:
1367 x.array [1] ^= y.array [1];
1368 case 1:
1369 x.array [0] ^= y.array [0];
1370 break;
1371 default:
1372 abort ();
1373 }
40fb9820
L		 1374 return x;
1375}
1376
1377static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1378static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1379static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1380static const i386_operand_type inoutportreg
1381 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1382static const i386_operand_type reg16_inoutportreg
1383 = OPERAND_TYPE_REG16_INOUTPORTREG;
1384static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1385static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1386static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1387static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1388static const i386_operand_type anydisp
1389 = OPERAND_TYPE_ANYDISP;
40fb9820 1390static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1391static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1392static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1393static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1394static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1395static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1396static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1397static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1398static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1399static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1400static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1401
1402enum operand_type
1403{
1404 reg,
40fb9820
L		 1405 imm,
1406 disp,
1407 anymem
1408};
1409
c6fb90c8 1410static INLINE int
40fb9820
L		 1411operand_type_check (i386_operand_type t, enum operand_type c)
1412{
1413 switch (c)
1414 {
1415 case reg:
1416 return (t.bitfield.reg8
1417 || t.bitfield.reg16
1418 || t.bitfield.reg32
1419 || t.bitfield.reg64);
1420
40fb9820
L		 1421 case imm:
1422 return (t.bitfield.imm8
1423 || t.bitfield.imm8s
1424 || t.bitfield.imm16
1425 || t.bitfield.imm32
1426 || t.bitfield.imm32s
1427 || t.bitfield.imm64);
1428
1429 case disp:
1430 return (t.bitfield.disp8
1431 || t.bitfield.disp16
1432 || t.bitfield.disp32
1433 || t.bitfield.disp32s
1434 || t.bitfield.disp64);
1435
1436 case anymem:
1437 return (t.bitfield.disp8
1438 || t.bitfield.disp16
1439 || t.bitfield.disp32
1440 || t.bitfield.disp32s
1441 || t.bitfield.disp64
1442 || t.bitfield.baseindex);
1443
1444 default:
1445 abort ();
1446 }
2cfe26b6
AM		 1447
1448 return 0;
40fb9820
L		 1449}
1450
5c07affc
L		 1451/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1452 operand J for instruction template T. */
1453
1454static INLINE int
1455match_reg_size (const template *t, unsigned int j)
1456{
1457 return !((i.types[j].bitfield.byte
1458 && !t->operand_types[j].bitfield.byte)
1459 || (i.types[j].bitfield.word
1460 && !t->operand_types[j].bitfield.word)
1461 || (i.types[j].bitfield.dword
1462 && !t->operand_types[j].bitfield.dword)
1463 || (i.types[j].bitfield.qword
1464 && !t->operand_types[j].bitfield.qword));
1465}
1466
1467/* Return 1 if there is no conflict in any size on operand J for
1468 instruction template T. */
1469
1470static INLINE int
1471match_mem_size (const template *t, unsigned int j)
1472{
1473 return (match_reg_size (t, j)
1474 && !((i.types[j].bitfield.unspecified
1475 && !t->operand_types[j].bitfield.unspecified)
1476 || (i.types[j].bitfield.fword
1477 && !t->operand_types[j].bitfield.fword)
1478 || (i.types[j].bitfield.tbyte
1479 && !t->operand_types[j].bitfield.tbyte)
1480 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1481 && !t->operand_types[j].bitfield.xmmword)
1482 || (i.types[j].bitfield.ymmword
1483 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1484}
1485
1486/* Return 1 if there is no size conflict on any operands for
1487 instruction template T. */
1488
1489static INLINE int
1490operand_size_match (const template *t)
1491{
1492 unsigned int j;
1493 int match = 1;
1494
1495 /* Don't check jump instructions. */
1496 if (t->opcode_modifier.jump
1497 || t->opcode_modifier.jumpbyte
1498 || t->opcode_modifier.jumpdword
1499 || t->opcode_modifier.jumpintersegment)
1500 return match;
1501
1502 /* Check memory and accumulator operand size. */
1503 for (j = 0; j < i.operands; j++)
1504 {
1505 if (t->operand_types[j].bitfield.anysize)
1506 continue;
1507
1508 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1509 {
1510 match = 0;
1511 break;
1512 }
1513
1514 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1515 {
1516 match = 0;
1517 break;
1518 }
1519 }
1520
1521 if (match
1522 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1523 return match;
1524
1525 /* Check reverse. */
1526 assert (i.operands == 2);
1527
1528 match = 1;
1529 for (j = 0; j < 2; j++)
1530 {
1531 if (t->operand_types[j].bitfield.acc
1532 && !match_reg_size (t, j ? 0 : 1))
1533 {
1534 match = 0;
1535 break;
1536 }
1537
1538 if (i.types[j].bitfield.mem
1539 && !match_mem_size (t, j ? 0 : 1))
1540 {
1541 match = 0;
1542 break;
1543 }
1544 }
1545
1546 return match;
1547}
1548
c6fb90c8 1549static INLINE int
40fb9820
L		 1550operand_type_match (i386_operand_type overlap,
1551 i386_operand_type given)
1552{
1553 i386_operand_type temp = overlap;
1554
1555 temp.bitfield.jumpabsolute = 0;
7d5e4556 1556 temp.bitfield.unspecified = 0;
5c07affc
L		 1557 temp.bitfield.byte = 0;
1558 temp.bitfield.word = 0;
1559 temp.bitfield.dword = 0;
1560 temp.bitfield.fword = 0;
1561 temp.bitfield.qword = 0;
1562 temp.bitfield.tbyte = 0;
1563 temp.bitfield.xmmword = 0;
c0f3af97 1564 temp.bitfield.ymmword = 0;
0dfbf9d7 1565 if (operand_type_all_zero (&temp))
40fb9820
L		 1566 return 0;
1567
1568 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1569 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1570}
1571
7d5e4556 1572/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1573 unless the expected operand type register overlap is null.
1574 Note that Acc in a template matches every size of reg. */
1575
c6fb90c8 1576static INLINE int
40fb9820
L		 1577operand_type_register_match (i386_operand_type m0,
1578 i386_operand_type g0,
1579 i386_operand_type t0,
1580 i386_operand_type m1,
1581 i386_operand_type g1,
1582 i386_operand_type t1)
1583{
1584 if (!operand_type_check (g0, reg))
1585 return 1;
1586
1587 if (!operand_type_check (g1, reg))
1588 return 1;
1589
1590 if (g0.bitfield.reg8 == g1.bitfield.reg8
1591 && g0.bitfield.reg16 == g1.bitfield.reg16
1592 && g0.bitfield.reg32 == g1.bitfield.reg32
1593 && g0.bitfield.reg64 == g1.bitfield.reg64)
1594 return 1;
1595
1596 if (m0.bitfield.acc)
1597 {
1598 t0.bitfield.reg8 = 1;
1599 t0.bitfield.reg16 = 1;
1600 t0.bitfield.reg32 = 1;
1601 t0.bitfield.reg64 = 1;
1602 }
1603
1604 if (m1.bitfield.acc)
1605 {
1606 t1.bitfield.reg8 = 1;
1607 t1.bitfield.reg16 = 1;
1608 t1.bitfield.reg32 = 1;
1609 t1.bitfield.reg64 = 1;
1610 }
1611
1612 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1613 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1614 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1615 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1616}
1617
252b5132 1618static INLINE unsigned int
40fb9820 1619mode_from_disp_size (i386_operand_type t)
252b5132 1620{
40fb9820
L		 1621 if (t.bitfield.disp8)
1622 return 1;
1623 else if (t.bitfield.disp16
1624 || t.bitfield.disp32
1625 || t.bitfield.disp32s)
1626 return 2;
1627 else
1628 return 0;
252b5132
RH		 1629}
1630
1631static INLINE int
e3bb37b5 1632fits_in_signed_byte (offsetT num)
252b5132
RH		 1633{
1634 return (num >= -128) && (num <= 127);
47926f60 1635}
252b5132
RH		 1636
1637static INLINE int
e3bb37b5 1638fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1639{
1640 return (num & 0xff) == num;
47926f60 1641}
252b5132
RH		 1642
1643static INLINE int
e3bb37b5 1644fits_in_unsigned_word (offsetT num)
252b5132
RH		 1645{
1646 return (num & 0xffff) == num;
47926f60 1647}
252b5132
RH		 1648
1649static INLINE int
e3bb37b5 1650fits_in_signed_word (offsetT num)
252b5132
RH		 1651{
1652 return (-32768 <= num) && (num <= 32767);
47926f60 1653}
2a962e6d 1654
3e73aa7c 1655static INLINE int
e3bb37b5 1656fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1657{
1658#ifndef BFD64
1659 return 1;
1660#else
1661 return (!(((offsetT) -1 << 31) & num)
1662 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1663#endif
1664} /* fits_in_signed_long() */
2a962e6d 1665
3e73aa7c 1666static INLINE int
e3bb37b5 1667fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1668{
1669#ifndef BFD64
1670 return 1;
1671#else
1672 return (num & (((offsetT) 2 << 31) - 1)) == num;
1673#endif
1674} /* fits_in_unsigned_long() */
252b5132 1675
c0f3af97
L		 1676static INLINE int
1677fits_in_imm4 (offsetT num)
1678{
1679 return (num & 0xf) == num;
1680}
1681
40fb9820 1682static i386_operand_type
e3bb37b5 1683smallest_imm_type (offsetT num)
252b5132 1684{
40fb9820
L		 1685 i386_operand_type t;
1686
0dfbf9d7 1687 operand_type_set (&t, 0);
40fb9820
L		 1688 t.bitfield.imm64 = 1;
1689
1690 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1691 {
1692 /* This code is disabled on the 486 because all the Imm1 forms
1693 in the opcode table are slower on the i486. They're the
1694 versions with the implicitly specified single-position
1695 displacement, which has another syntax if you really want to
1696 use that form. */
40fb9820
L		 1697 t.bitfield.imm1 = 1;
1698 t.bitfield.imm8 = 1;
1699 t.bitfield.imm8s = 1;
1700 t.bitfield.imm16 = 1;
1701 t.bitfield.imm32 = 1;
1702 t.bitfield.imm32s = 1;
1703 }
1704 else if (fits_in_signed_byte (num))
1705 {
1706 t.bitfield.imm8 = 1;
1707 t.bitfield.imm8s = 1;
1708 t.bitfield.imm16 = 1;
1709 t.bitfield.imm32 = 1;
1710 t.bitfield.imm32s = 1;
1711 }
1712 else if (fits_in_unsigned_byte (num))
1713 {
1714 t.bitfield.imm8 = 1;
1715 t.bitfield.imm16 = 1;
1716 t.bitfield.imm32 = 1;
1717 t.bitfield.imm32s = 1;
1718 }
1719 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1720 {
1721 t.bitfield.imm16 = 1;
1722 t.bitfield.imm32 = 1;
1723 t.bitfield.imm32s = 1;
1724 }
1725 else if (fits_in_signed_long (num))
1726 {
1727 t.bitfield.imm32 = 1;
1728 t.bitfield.imm32s = 1;
1729 }
1730 else if (fits_in_unsigned_long (num))
1731 t.bitfield.imm32 = 1;
1732
1733 return t;
47926f60 1734}
252b5132 1735
847f7ad4 1736static offsetT
e3bb37b5 1737offset_in_range (offsetT val, int size)
847f7ad4 1738{
508866be 1739 addressT mask;
ba2adb93 1740
847f7ad4
AM		 1741 switch (size)
1742 {
508866be
L		 1743 case 1: mask = ((addressT) 1 << 8) - 1; break;
1744 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1745 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1746#ifdef BFD64
1747 case 8: mask = ((addressT) 2 << 63) - 1; break;
1748#endif
47926f60 1749 default: abort ();
847f7ad4
AM		 1750 }
1751
ba2adb93 1752 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1753 if (!use_rela_relocations)
1754 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1755 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1756
47926f60 1757 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1758 {
1759 char buf1[40], buf2[40];
1760
1761 sprint_value (buf1, val);
1762 sprint_value (buf2, val & mask);
1763 as_warn (_("%s shortened to %s"), buf1, buf2);
1764 }
1765 return val & mask;
1766}
1767
252b5132
RH		 1768/* Returns 0 if attempting to add a prefix where one from the same
1769 class already exists, 1 if non rep/repne added, 2 if rep/repne
1770 added. */
1771static int
e3bb37b5 1772add_prefix (unsigned int prefix)
252b5132
RH		 1773{
1774 int ret = 1;
b1905489 1775 unsigned int q;
252b5132 1776
29b0f896
AM		 1777 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1778 && flag_code == CODE_64BIT)
b1905489 1779 {
161a04f6
L		 1780 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1781 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1782 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1783 ret = 0;
1784 q = REX_PREFIX;
1785 }
3e73aa7c 1786 else
b1905489
JB		 1787 {
1788 switch (prefix)
1789 {
1790 default:
1791 abort ();
1792
1793 case CS_PREFIX_OPCODE:
1794 case DS_PREFIX_OPCODE:
1795 case ES_PREFIX_OPCODE:
1796 case FS_PREFIX_OPCODE:
1797 case GS_PREFIX_OPCODE:
1798 case SS_PREFIX_OPCODE:
1799 q = SEG_PREFIX;
1800 break;
1801
1802 case REPNE_PREFIX_OPCODE:
1803 case REPE_PREFIX_OPCODE:
1804 ret = 2;
1805 /* fall thru */
1806 case LOCK_PREFIX_OPCODE:
1807 q = LOCKREP_PREFIX;
1808 break;
1809
1810 case FWAIT_OPCODE:
1811 q = WAIT_PREFIX;
1812 break;
1813
1814 case ADDR_PREFIX_OPCODE:
1815 q = ADDR_PREFIX;
1816 break;
1817
1818 case DATA_PREFIX_OPCODE:
1819 q = DATA_PREFIX;
1820 break;
1821 }
1822 if (i.prefix[q] != 0)
1823 ret = 0;
1824 }
252b5132 1825
b1905489 1826 if (ret)
252b5132 1827 {
b1905489
JB		 1828 if (!i.prefix[q])
1829 ++i.prefixes;
1830 i.prefix[q] |= prefix;
252b5132 1831 }
b1905489
JB		 1832 else
1833 as_bad (_("same type of prefix used twice"));
252b5132 1834
252b5132
RH		 1835 return ret;
1836}
1837
1838static void
e3bb37b5 1839set_code_flag (int value)
eecb386c 1840{
3e73aa7c 1841 flag_code = value;
40fb9820
L		 1842 if (flag_code == CODE_64BIT)
1843 {
1844 cpu_arch_flags.bitfield.cpu64 = 1;
1845 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1846 }
1847 else
1848 {
1849 cpu_arch_flags.bitfield.cpu64 = 0;
1850 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1851 }
1852 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1853 {
1854 as_bad (_("64bit mode not supported on this CPU."));
1855 }
40fb9820 1856 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1857 {
1858 as_bad (_("32bit mode not supported on this CPU."));
1859 }
eecb386c
AM		 1860 stackop_size = '\0';
1861}
1862
1863static void
e3bb37b5 1864set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1865{
3e73aa7c 1866 flag_code = new_code_flag;
40fb9820
L		 1867 if (flag_code != CODE_16BIT)
1868 abort ();
1869 cpu_arch_flags.bitfield.cpu64 = 0;
1870 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1871 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1872}
1873
1874static void
e3bb37b5 1875set_intel_syntax (int syntax_flag)
252b5132
RH		 1876{
1877 /* Find out if register prefixing is specified. */
1878 int ask_naked_reg = 0;
1879
1880 SKIP_WHITESPACE ();
29b0f896 1881 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1882 {
1883 char *string = input_line_pointer;
1884 int e = get_symbol_end ();
1885
47926f60 1886 if (strcmp (string, "prefix") == 0)
252b5132 1887 ask_naked_reg = 1;
47926f60 1888 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1889 ask_naked_reg = -1;
1890 else
d0b47220 1891 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1892 *input_line_pointer = e;
1893 }
1894 demand_empty_rest_of_line ();
c3332e24 1895
252b5132
RH		 1896 intel_syntax = syntax_flag;
1897
1898 if (ask_naked_reg == 0)
f86103b7
AM		 1899 allow_naked_reg = (intel_syntax
1900 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1901 else
1902 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1903
e4a3b5a4 1904 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1905 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1906 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1907}
1908
1efbbeb4
L		 1909static void
1910set_intel_mnemonic (int mnemonic_flag)
1911{
e1d4d893 1912 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1913}
1914
db51cc60
L		 1915static void
1916set_allow_index_reg (int flag)
1917{
1918 allow_index_reg = flag;
1919}
1920
cb19c032
L		 1921static void
1922set_sse_check (int dummy ATTRIBUTE_UNUSED)
1923{
1924 SKIP_WHITESPACE ();
1925
1926 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1927 {
1928 char *string = input_line_pointer;
1929 int e = get_symbol_end ();
1930
1931 if (strcmp (string, "none") == 0)
1932 sse_check = sse_check_none;
1933 else if (strcmp (string, "warning") == 0)
1934 sse_check = sse_check_warning;
1935 else if (strcmp (string, "error") == 0)
1936 sse_check = sse_check_error;
1937 else
1938 as_bad (_("bad argument to sse_check directive."));
1939 *input_line_pointer = e;
1940 }
1941 else
1942 as_bad (_("missing argument for sse_check directive"));
1943
1944 demand_empty_rest_of_line ();
1945}
1946
e413e4e9 1947static void
e3bb37b5 1948set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1949{
47926f60 1950 SKIP_WHITESPACE ();
e413e4e9 1951
29b0f896 1952 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1953 {
1954 char *string = input_line_pointer;
1955 int e = get_symbol_end ();
9103f4f4 1956 unsigned int i;
40fb9820 1957 i386_cpu_flags flags;
e413e4e9 1958
9103f4f4 1959 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1960 {
1961 if (strcmp (string, cpu_arch[i].name) == 0)
1962 {
5c6af06e
JB		 1963 if (*string != '.')
1964 {
1965 cpu_arch_name = cpu_arch[i].name;
1966 cpu_sub_arch_name = NULL;
40fb9820
L		 1967 cpu_arch_flags = cpu_arch[i].flags;
1968 if (flag_code == CODE_64BIT)
1969 {
1970 cpu_arch_flags.bitfield.cpu64 = 1;
1971 cpu_arch_flags.bitfield.cpuno64 = 0;
1972 }
1973 else
1974 {
1975 cpu_arch_flags.bitfield.cpu64 = 0;
1976 cpu_arch_flags.bitfield.cpuno64 = 1;
1977 }
ccc9c027 1978 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1979 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1980 if (!cpu_arch_tune_set)
1981 {
1982 cpu_arch_tune = cpu_arch_isa;
1983 cpu_arch_tune_flags = cpu_arch_isa_flags;
1984 }
5c6af06e
JB		 1985 break;
1986 }
40fb9820 1987
c6fb90c8
L		 1988 flags = cpu_flags_or (cpu_arch_flags,
1989 cpu_arch[i].flags);
0dfbf9d7 1990 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1991 {
6305a203
L		 1992 if (cpu_sub_arch_name)
1993 {
1994 char *name = cpu_sub_arch_name;
1995 cpu_sub_arch_name = concat (name,
1996 cpu_arch[i].name,
1bf57e9f 1997 (const char *) NULL);
6305a203
L		 1998 free (name);
1999 }
2000 else
2001 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 2002 cpu_arch_flags = flags;
5c6af06e
JB		 2003 }
2004 *input_line_pointer = e;
2005 demand_empty_rest_of_line ();
2006 return;
e413e4e9
AM		 2007 }
2008 }
9103f4f4 2009 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2010 as_bad (_("no such architecture: `%s'"), string);
2011
2012 *input_line_pointer = e;
2013 }
2014 else
2015 as_bad (_("missing cpu architecture"));
2016
fddf5b5b
AM		 2017 no_cond_jump_promotion = 0;
2018 if (*input_line_pointer == ','
29b0f896 2019 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2020 {
2021 char *string = ++input_line_pointer;
2022 int e = get_symbol_end ();
2023
2024 if (strcmp (string, "nojumps") == 0)
2025 no_cond_jump_promotion = 1;
2026 else if (strcmp (string, "jumps") == 0)
2027 ;
2028 else
2029 as_bad (_("no such architecture modifier: `%s'"), string);
2030
2031 *input_line_pointer = e;
2032 }
2033
e413e4e9
AM		 2034 demand_empty_rest_of_line ();
2035}
2036
b9d79e03
JH		 2037unsigned long
2038i386_mach ()
2039{
2040 if (!strcmp (default_arch, "x86_64"))
2041 return bfd_mach_x86_64;
2042 else if (!strcmp (default_arch, "i386"))
2043 return bfd_mach_i386_i386;
2044 else
2045 as_fatal (_("Unknown architecture"));
2046}
b9d79e03 2047\f
252b5132
RH		 2048void
2049md_begin ()
2050{
2051 const char *hash_err;
2052
47926f60 2053 /* Initialize op_hash hash table. */
252b5132
RH		 2054 op_hash = hash_new ();
2055
2056 {
29b0f896
AM		 2057 const template *optab;
2058 templates *core_optab;
252b5132 2059
47926f60
KH		 2060 /* Setup for loop. */
2061 optab = i386_optab;
252b5132
RH		 2062 core_optab = (templates *) xmalloc (sizeof (templates));
2063 core_optab->start = optab;
2064
2065 while (1)
2066 {
2067 ++optab;
2068 if (optab->name == NULL
2069 || strcmp (optab->name, (optab - 1)->name) != 0)
2070 {
2071 /* different name --> ship out current template list;
47926f60 2072 add to hash table; & begin anew. */
252b5132
RH		 2073 core_optab->end = optab;
2074 hash_err = hash_insert (op_hash,
2075 (optab - 1)->name,
5a49b8ac 2076 (void *) core_optab);
252b5132
RH		 2077 if (hash_err)
2078 {
252b5132
RH		 2079 as_fatal (_("Internal Error: Can't hash %s: %s"),
2080 (optab - 1)->name,
2081 hash_err);
2082 }
2083 if (optab->name == NULL)
2084 break;
2085 core_optab = (templates *) xmalloc (sizeof (templates));
2086 core_optab->start = optab;
2087 }
2088 }
2089 }
2090
47926f60 2091 /* Initialize reg_hash hash table. */
252b5132
RH		 2092 reg_hash = hash_new ();
2093 {
29b0f896 2094 const reg_entry *regtab;
c3fe08fa 2095 unsigned int regtab_size = i386_regtab_size;
252b5132 2096
c3fe08fa 2097 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2098 {
5a49b8ac 2099 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2100 if (hash_err)
3e73aa7c
JH		 2101 as_fatal (_("Internal Error: Can't hash %s: %s"),
2102 regtab->reg_name,
2103 hash_err);
252b5132
RH		 2104 }
2105 }
2106
47926f60 2107 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2108 {
29b0f896
AM		 2109 int c;
2110 char *p;
252b5132
RH		 2111
2112 for (c = 0; c < 256; c++)
2113 {
3882b010 2114 if (ISDIGIT (c))
252b5132
RH		 2115 {
2116 digit_chars[c] = c;
2117 mnemonic_chars[c] = c;
2118 register_chars[c] = c;
2119 operand_chars[c] = c;
2120 }
3882b010 2121 else if (ISLOWER (c))
252b5132
RH		 2122 {
2123 mnemonic_chars[c] = c;
2124 register_chars[c] = c;
2125 operand_chars[c] = c;
2126 }
3882b010 2127 else if (ISUPPER (c))
252b5132 2128 {
3882b010 2129 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2130 register_chars[c] = mnemonic_chars[c];
2131 operand_chars[c] = c;
2132 }
2133
3882b010 2134 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2135 identifier_chars[c] = c;
2136 else if (c >= 128)
2137 {
2138 identifier_chars[c] = c;
2139 operand_chars[c] = c;
2140 }
2141 }
2142
2143#ifdef LEX_AT
2144 identifier_chars['@'] = '@';
32137342
NC		 2145#endif
2146#ifdef LEX_QM
2147 identifier_chars['?'] = '?';
2148 operand_chars['?'] = '?';
252b5132 2149#endif
252b5132 2150 digit_chars['-'] = '-';
c0f3af97 2151 mnemonic_chars['_'] = '_';
791fe849 2152 mnemonic_chars['-'] = '-';
0003779b 2153 mnemonic_chars['.'] = '.';
252b5132
RH		 2154 identifier_chars['_'] = '_';
2155 identifier_chars['.'] = '.';
2156
2157 for (p = operand_special_chars; *p != '\0'; p++)
2158 operand_chars[(unsigned char) *p] = *p;
2159 }
2160
2161#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2162 if (IS_ELF)
252b5132
RH		 2163 {
2164 record_alignment (text_section, 2);
2165 record_alignment (data_section, 2);
2166 record_alignment (bss_section, 2);
2167 }
2168#endif
a4447b93
RH		 2169
2170 if (flag_code == CODE_64BIT)
2171 {
2172 x86_dwarf2_return_column = 16;
2173 x86_cie_data_alignment = -8;
2174 }
2175 else
2176 {
2177 x86_dwarf2_return_column = 8;
2178 x86_cie_data_alignment = -4;
2179 }
252b5132
RH		 2180}
2181
2182void
e3bb37b5 2183i386_print_statistics (FILE *file)
252b5132
RH		 2184{
2185 hash_print_statistics (file, "i386 opcode", op_hash);
2186 hash_print_statistics (file, "i386 register", reg_hash);
2187}
2188\f
252b5132
RH		 2189#ifdef DEBUG386
2190
ce8a8b2f 2191/* Debugging routines for md_assemble. */
e3bb37b5 2192static void pte (template *);
40fb9820 2193static void pt (i386_operand_type);
e3bb37b5
L		 2194static void pe (expressionS *);
2195static void ps (symbolS *);
252b5132
RH		 2196
2197static void
e3bb37b5 2198pi (char *line, i386_insn *x)
252b5132 2199{
09f131f2 2200 unsigned int i;
252b5132
RH		 2201
2202 fprintf (stdout, "%s: template ", line);
2203 pte (&x->tm);
09f131f2
JH		 2204 fprintf (stdout, " address: base %s index %s scale %x\n",
2205 x->base_reg ? x->base_reg->reg_name : "none",
2206 x->index_reg ? x->index_reg->reg_name : "none",
2207 x->log2_scale_factor);
2208 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2209 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2210 fprintf (stdout, " sib: base %x index %x scale %x\n",
2211 x->sib.base, x->sib.index, x->sib.scale);
2212 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2213 (x->rex & REX_W) != 0,
2214 (x->rex & REX_R) != 0,
2215 (x->rex & REX_X) != 0,
2216 (x->rex & REX_B) != 0);
85f10a01
MM		 2217 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2218 x->drex.reg, x->drex.rex);
252b5132
RH		 2219 for (i = 0; i < x->operands; i++)
2220 {
2221 fprintf (stdout, " #%d: ", i + 1);
2222 pt (x->types[i]);
2223 fprintf (stdout, "\n");
40fb9820
L		 2224 if (x->types[i].bitfield.reg8
2225 || x->types[i].bitfield.reg16
2226 || x->types[i].bitfield.reg32
2227 || x->types[i].bitfield.reg64
2228 || x->types[i].bitfield.regmmx
2229 || x->types[i].bitfield.regxmm
c0f3af97 2230 || x->types[i].bitfield.regymm
40fb9820
L		 2231 || x->types[i].bitfield.sreg2
2232 || x->types[i].bitfield.sreg3
2233 || x->types[i].bitfield.control
2234 || x->types[i].bitfield.debug
2235 || x->types[i].bitfield.test)
520dc8e8 2236 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2237 if (operand_type_check (x->types[i], imm))
520dc8e8 2238 pe (x->op[i].imms);
40fb9820 2239 if (operand_type_check (x->types[i], disp))
520dc8e8 2240 pe (x->op[i].disps);
252b5132
RH		 2241 }
2242}
2243
2244static void
e3bb37b5 2245pte (template *t)
252b5132 2246{
09f131f2 2247 unsigned int i;
252b5132 2248 fprintf (stdout, " %d operands ", t->operands);
47926f60 2249 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2250 if (t->extension_opcode != None)
2251 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2252 if (t->opcode_modifier.d)
252b5132 2253 fprintf (stdout, "D");
40fb9820 2254 if (t->opcode_modifier.w)
252b5132
RH		 2255 fprintf (stdout, "W");
2256 fprintf (stdout, "\n");
2257 for (i = 0; i < t->operands; i++)
2258 {
2259 fprintf (stdout, " #%d type ", i + 1);
2260 pt (t->operand_types[i]);
2261 fprintf (stdout, "\n");
2262 }
2263}
2264
2265static void
e3bb37b5 2266pe (expressionS *e)
252b5132 2267{
24eab124 2268 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2269 fprintf (stdout, " add_number %ld (%lx)\n",
2270 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2271 if (e->X_add_symbol)
2272 {
2273 fprintf (stdout, " add_symbol ");
2274 ps (e->X_add_symbol);
2275 fprintf (stdout, "\n");
2276 }
2277 if (e->X_op_symbol)
2278 {
2279 fprintf (stdout, " op_symbol ");
2280 ps (e->X_op_symbol);
2281 fprintf (stdout, "\n");
2282 }
2283}
2284
2285static void
e3bb37b5 2286ps (symbolS *s)
252b5132
RH		 2287{
2288 fprintf (stdout, "%s type %s%s",
2289 S_GET_NAME (s),
2290 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2291 segment_name (S_GET_SEGMENT (s)));
2292}
2293
7b81dfbb 2294static struct type_name
252b5132 2295 {
40fb9820
L		 2296 i386_operand_type mask;
2297 const char *name;
252b5132 2298 }
7b81dfbb 2299const type_names[] =
252b5132 2300{
40fb9820
L		 2301 { OPERAND_TYPE_REG8, "r8" },
2302 { OPERAND_TYPE_REG16, "r16" },
2303 { OPERAND_TYPE_REG32, "r32" },
2304 { OPERAND_TYPE_REG64, "r64" },
2305 { OPERAND_TYPE_IMM8, "i8" },
2306 { OPERAND_TYPE_IMM8, "i8s" },
2307 { OPERAND_TYPE_IMM16, "i16" },
2308 { OPERAND_TYPE_IMM32, "i32" },
2309 { OPERAND_TYPE_IMM32S, "i32s" },
2310 { OPERAND_TYPE_IMM64, "i64" },
2311 { OPERAND_TYPE_IMM1, "i1" },
2312 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2313 { OPERAND_TYPE_DISP8, "d8" },
2314 { OPERAND_TYPE_DISP16, "d16" },
2315 { OPERAND_TYPE_DISP32, "d32" },
2316 { OPERAND_TYPE_DISP32S, "d32s" },
2317 { OPERAND_TYPE_DISP64, "d64" },
2318 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2319 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2320 { OPERAND_TYPE_CONTROL, "control reg" },
2321 { OPERAND_TYPE_TEST, "test reg" },
2322 { OPERAND_TYPE_DEBUG, "debug reg" },
2323 { OPERAND_TYPE_FLOATREG, "FReg" },
2324 { OPERAND_TYPE_FLOATACC, "FAcc" },
2325 { OPERAND_TYPE_SREG2, "SReg2" },
2326 { OPERAND_TYPE_SREG3, "SReg3" },
2327 { OPERAND_TYPE_ACC, "Acc" },
2328 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2329 { OPERAND_TYPE_REGMMX, "rMMX" },
2330 { OPERAND_TYPE_REGXMM, "rXMM" },
2331 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2332};
2333
2334static void
40fb9820 2335pt (i386_operand_type t)
252b5132 2336{
40fb9820 2337 unsigned int j;
c6fb90c8 2338 i386_operand_type a;
252b5132 2339
40fb9820 2340 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2341 {
2342 a = operand_type_and (t, type_names[j].mask);
2343 if (!UINTS_ALL_ZERO (a))
2344 fprintf (stdout, "%s, ", type_names[j].name);
2345 }
252b5132
RH		 2346 fflush (stdout);
2347}
2348
2349#endif /* DEBUG386 */
2350\f
252b5132 2351static bfd_reloc_code_real_type
3956db08 2352reloc (unsigned int size,
64e74474
AM		 2353 int pcrel,
2354 int sign,
2355 bfd_reloc_code_real_type other)
252b5132 2356{
47926f60 2357 if (other != NO_RELOC)
3956db08
JB		 2358 {
2359 reloc_howto_type *reloc;
2360
2361 if (size == 8)
2362 switch (other)
2363 {
64e74474
AM		 2364 case BFD_RELOC_X86_64_GOT32:
2365 return BFD_RELOC_X86_64_GOT64;
2366 break;
2367 case BFD_RELOC_X86_64_PLTOFF64:
2368 return BFD_RELOC_X86_64_PLTOFF64;
2369 break;
2370 case BFD_RELOC_X86_64_GOTPC32:
2371 other = BFD_RELOC_X86_64_GOTPC64;
2372 break;
2373 case BFD_RELOC_X86_64_GOTPCREL:
2374 other = BFD_RELOC_X86_64_GOTPCREL64;
2375 break;
2376 case BFD_RELOC_X86_64_TPOFF32:
2377 other = BFD_RELOC_X86_64_TPOFF64;
2378 break;
2379 case BFD_RELOC_X86_64_DTPOFF32:
2380 other = BFD_RELOC_X86_64_DTPOFF64;
2381 break;
2382 default:
2383 break;
3956db08 2384 }
e05278af
JB		 2385
2386 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2387 if (size == 4 && flag_code != CODE_64BIT)
2388 sign = -1;
2389
3956db08
JB		 2390 reloc = bfd_reloc_type_lookup (stdoutput, other);
2391 if (!reloc)
2392 as_bad (_("unknown relocation (%u)"), other);
2393 else if (size != bfd_get_reloc_size (reloc))
2394 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2395 bfd_get_reloc_size (reloc),
2396 size);
2397 else if (pcrel && !reloc->pc_relative)
2398 as_bad (_("non-pc-relative relocation for pc-relative field"));
2399 else if ((reloc->complain_on_overflow == complain_overflow_signed
2400 && !sign)
2401 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2402 && sign > 0))
3956db08
JB		 2403 as_bad (_("relocated field and relocation type differ in signedness"));
2404 else
2405 return other;
2406 return NO_RELOC;
2407 }
252b5132
RH		 2408
2409 if (pcrel)
2410 {
3e73aa7c 2411 if (!sign)
3956db08 2412 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2413 switch (size)
2414 {
2415 case 1: return BFD_RELOC_8_PCREL;
2416 case 2: return BFD_RELOC_16_PCREL;
2417 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2418 case 8: return BFD_RELOC_64_PCREL;
252b5132 2419 }
3956db08 2420 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2421 }
2422 else
2423 {
3956db08 2424 if (sign > 0)
e5cb08ac 2425 switch (size)
3e73aa7c
JH		 2426 {
2427 case 4: return BFD_RELOC_X86_64_32S;
2428 }
2429 else
2430 switch (size)
2431 {
2432 case 1: return BFD_RELOC_8;
2433 case 2: return BFD_RELOC_16;
2434 case 4: return BFD_RELOC_32;
2435 case 8: return BFD_RELOC_64;
2436 }
3956db08
JB		 2437 as_bad (_("cannot do %s %u byte relocation"),
2438 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2439 }
2440
bfb32b52 2441 abort ();
252b5132
RH		 2442 return BFD_RELOC_NONE;
2443}
2444
47926f60
KH		 2445/* Here we decide which fixups can be adjusted to make them relative to
2446 the beginning of the section instead of the symbol. Basically we need
2447 to make sure that the dynamic relocations are done correctly, so in
2448 some cases we force the original symbol to be used. */
2449
252b5132 2450int
e3bb37b5 2451tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2452{
6d249963 2453#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2454 if (!IS_ELF)
31312f95
AM		 2455 return 1;
2456
a161fe53
AM		 2457 /* Don't adjust pc-relative references to merge sections in 64-bit
2458 mode. */
2459 if (use_rela_relocations
2460 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2461 && fixP->fx_pcrel)
252b5132 2462 return 0;
31312f95 2463
8d01d9a9
AJ		 2464 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2465 and changed later by validate_fix. */
2466 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2467 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2468 return 0;
2469
ce8a8b2f 2470 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2471 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2472 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2473 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2474 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2475 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2476 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2477 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2478 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2479 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2480 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2481 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2482 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2483 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2484 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2485 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2486 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2487 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2488 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2489 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2490 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2491 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2492 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2493 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2494 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2495 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2496 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2497 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2498 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2499 return 0;
31312f95 2500#endif
252b5132
RH		 2501 return 1;
2502}
252b5132 2503
b4cac588 2504static int
e3bb37b5 2505intel_float_operand (const char *mnemonic)
252b5132 2506{
9306ca4a
JB		 2507 /* Note that the value returned is meaningful only for opcodes with (memory)
2508 operands, hence the code here is free to improperly handle opcodes that
2509 have no operands (for better performance and smaller code). */
2510
2511 if (mnemonic[0] != 'f')
2512 return 0; /* non-math */
2513
2514 switch (mnemonic[1])
2515 {
2516 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2517 the fs segment override prefix not currently handled because no
2518 call path can make opcodes without operands get here */
2519 case 'i':
2520 return 2 /* integer op */;
2521 case 'l':
2522 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2523 return 3; /* fldcw/fldenv */
2524 break;
2525 case 'n':
2526 if (mnemonic[2] != 'o' /* fnop */)
2527 return 3; /* non-waiting control op */
2528 break;
2529 case 'r':
2530 if (mnemonic[2] == 's')
2531 return 3; /* frstor/frstpm */
2532 break;
2533 case 's':
2534 if (mnemonic[2] == 'a')
2535 return 3; /* fsave */
2536 if (mnemonic[2] == 't')
2537 {
2538 switch (mnemonic[3])
2539 {
2540 case 'c': /* fstcw */
2541 case 'd': /* fstdw */
2542 case 'e': /* fstenv */
2543 case 's': /* fsts[gw] */
2544 return 3;
2545 }
2546 }
2547 break;
2548 case 'x':
2549 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2550 return 0; /* fxsave/fxrstor are not really math ops */
2551 break;
2552 }
252b5132 2553
9306ca4a 2554 return 1;
252b5132
RH		 2555}
2556
c0f3af97
L		 2557/* Build the VEX prefix. */
2558
2559static void
fa99fab2 2560build_vex_prefix (const template *t)
c0f3af97
L		 2561{
2562 unsigned int register_specifier;
2563 unsigned int implied_prefix;
2564 unsigned int vector_length;
2565
2566 /* Check register specifier. */
2567 if (i.vex.register_specifier)
2568 {
2569 register_specifier = i.vex.register_specifier->reg_num;
2570 if ((i.vex.register_specifier->reg_flags & RegRex))
2571 register_specifier += 8;
2572 register_specifier = ~register_specifier & 0xf;
2573 }
2574 else
2575 register_specifier = 0xf;
2576
fa99fab2
L		 2577 /* Use 2-byte VEX prefix by swappping destination and source
2578 operand. */
2579 if (!i.swap_operand
2580 && i.operands == i.reg_operands
2581 && i.tm.opcode_modifier.vex0f
2582 && i.tm.opcode_modifier.s
2583 && i.rex == REX_B)
2584 {
2585 unsigned int xchg = i.operands - 1;
2586 union i386_op temp_op;
2587 i386_operand_type temp_type;
2588
2589 temp_type = i.types[xchg];
2590 i.types[xchg] = i.types[0];
2591 i.types[0] = temp_type;
2592 temp_op = i.op[xchg];
2593 i.op[xchg] = i.op[0];
2594 i.op[0] = temp_op;
2595
2596 assert (i.rm.mode == 3);
2597
2598 i.rex = REX_R;
2599 xchg = i.rm.regmem;
2600 i.rm.regmem = i.rm.reg;
2601 i.rm.reg = xchg;
2602
2603 /* Use the next insn. */
2604 i.tm = t[1];
2605 }
2606
c0f3af97
L		 2607 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2608
2609 switch ((i.tm.base_opcode >> 8) & 0xff)
2610 {
2611 case 0:
2612 implied_prefix = 0;
2613 break;
2614 case DATA_PREFIX_OPCODE:
2615 implied_prefix = 1;
2616 break;
2617 case REPE_PREFIX_OPCODE:
2618 implied_prefix = 2;
2619 break;
2620 case REPNE_PREFIX_OPCODE:
2621 implied_prefix = 3;
2622 break;
2623 default:
2624 abort ();
2625 }
2626
2627 /* Use 2-byte VEX prefix if possible. */
2628 if (i.tm.opcode_modifier.vex0f
2629 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2630 {
2631 /* 2-byte VEX prefix. */
2632 unsigned int r;
2633
2634 i.vex.length = 2;
2635 i.vex.bytes[0] = 0xc5;
2636
2637 /* Check the REX.R bit. */
2638 r = (i.rex & REX_R) ? 0 : 1;
2639 i.vex.bytes[1] = (r << 7
2640 | register_specifier << 3
2641 | vector_length << 2
2642 | implied_prefix);
2643 }
2644 else
2645 {
2646 /* 3-byte VEX prefix. */
2647 unsigned int m, w;
2648
2649 if (i.tm.opcode_modifier.vex0f)
2650 m = 0x1;
2651 else if (i.tm.opcode_modifier.vex0f38)
2652 m = 0x2;
2653 else if (i.tm.opcode_modifier.vex0f3a)
2654 m = 0x3;
2655 else
2656 abort ();
2657
2658 i.vex.length = 3;
2659 i.vex.bytes[0] = 0xc4;
2660
2661 /* The high 3 bits of the second VEX byte are 1's compliment
2662 of RXB bits from REX. */
2663 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2664
2665 /* Check the REX.W bit. */
2666 w = (i.rex & REX_W) ? 1 : 0;
2667 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2668 {
2669 if (w)
2670 abort ();
2671
2672 if (i.tm.opcode_modifier.vexw1)
2673 w = 1;
2674 }
2675
2676 i.vex.bytes[2] = (w << 7
2677 | register_specifier << 3
2678 | vector_length << 2
2679 | implied_prefix);
2680 }
2681}
2682
65da13b5
L		 2683static void
2684process_immext (void)
2685{
2686 expressionS *exp;
2687
2688 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2689 {
1fed0ba1
L		 2690 /* SSE3 Instructions have the fixed operands with an opcode
2691 suffix which is coded in the same place as an 8-bit immediate
2692 field would be. Here we check those operands and remove them
2693 afterwards. */
65da13b5
L		 2694 unsigned int x;
2695
2696 for (x = 0; x < i.operands; x++)
2697 if (i.op[x].regs->reg_num != x)
2698 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2699 register_prefix, i.op[x].regs->reg_name, x + 1,
2700 i.tm.name);
2701
2702 i.operands = 0;
65da13b5
L		 2703 }
2704
c0f3af97 2705 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2706 which is coded in the same place as an 8-bit immediate field
2707 would be. Here we fake an 8-bit immediate operand from the
2708 opcode suffix stored in tm.extension_opcode.
2709
c0f3af97
L		 2710 SSE5 and AVX instructions also use this encoding, for some of
2711 3 argument instructions. */
65da13b5
L		 2712
2713 assert (i.imm_operands == 0
2714 && (i.operands <= 2
2715 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2716 && i.operands <= 3)
2717 || (i.tm.opcode_modifier.vex
2718 && i.operands <= 4)));
65da13b5
L		 2719
2720 exp = &im_expressions[i.imm_operands++];
2721 i.op[i.operands].imms = exp;
2722 i.types[i.operands] = imm8;
2723 i.operands++;
2724 exp->X_op = O_constant;
2725 exp->X_add_number = i.tm.extension_opcode;
2726 i.tm.extension_opcode = None;
2727}
2728
252b5132
RH		 2729/* This is the guts of the machine-dependent assembler. LINE points to a
2730 machine dependent instruction. This function is supposed to emit
2731 the frags/bytes it assembles to. */
2732
2733void
65da13b5 2734md_assemble (char *line)
252b5132 2735{
40fb9820 2736 unsigned int j;
252b5132 2737 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2738 const template *t;
252b5132 2739
47926f60 2740 /* Initialize globals. */
252b5132
RH		 2741 memset (&i, '\0', sizeof (i));
2742 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2743 i.reloc[j] = NO_RELOC;
252b5132
RH		 2744 memset (disp_expressions, '\0', sizeof (disp_expressions));
2745 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2746 save_stack_p = save_stack;
252b5132
RH		 2747
2748 /* First parse an instruction mnemonic & call i386_operand for the operands.
2749 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2750 start of a (possibly prefixed) mnemonic. */
252b5132 2751
29b0f896
AM		 2752 line = parse_insn (line, mnemonic);
2753 if (line == NULL)
2754 return;
252b5132 2755
29b0f896
AM		 2756 line = parse_operands (line, mnemonic);
2757 if (line == NULL)
2758 return;
252b5132 2759
29b0f896
AM		 2760 /* Now we've parsed the mnemonic into a set of templates, and have the
2761 operands at hand. */
2762
2763 /* All intel opcodes have reversed operands except for "bound" and
2764 "enter". We also don't reverse intersegment "jmp" and "call"
2765 instructions with 2 immediate operands so that the immediate segment
050dfa73 2766 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2767 if (intel_syntax
2768 && i.operands > 1
29b0f896 2769 && (strcmp (mnemonic, "bound") != 0)
30123838 2770 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2771 && !(operand_type_check (i.types[0], imm)
2772 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2773 swap_operands ();
2774
ec56d5c0
JB		 2775 /* The order of the immediates should be reversed
2776 for 2 immediates extrq and insertq instructions */
2777 if (i.imm_operands == 2
2778 && (strcmp (mnemonic, "extrq") == 0
2779 || strcmp (mnemonic, "insertq") == 0))
2780 swap_2_operands (0, 1);
2781
29b0f896
AM		 2782 if (i.imm_operands)
2783 optimize_imm ();
2784
b300c311
L		 2785 /* Don't optimize displacement for movabs since it only takes 64bit
2786 displacement. */
2787 if (i.disp_operands
2788 && (flag_code != CODE_64BIT
2789 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2790 optimize_disp ();
2791
2792 /* Next, we find a template that matches the given insn,
2793 making sure the overlap of the given operands types is consistent
2794 with the template operand types. */
252b5132 2795
fa99fab2 2796 if (!(t = match_template ()))
29b0f896 2797 return;
252b5132 2798
daf50ae7 2799 if (sse_check != sse_check_none
81f8a913 2800 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2801 && (i.tm.cpu_flags.bitfield.cpusse
2802 || i.tm.cpu_flags.bitfield.cpusse2
2803 || i.tm.cpu_flags.bitfield.cpusse3
2804 || i.tm.cpu_flags.bitfield.cpussse3
2805 || i.tm.cpu_flags.bitfield.cpusse4_1
2806 || i.tm.cpu_flags.bitfield.cpusse4_2))
2807 {
2808 (sse_check == sse_check_warning
2809 ? as_warn
2810 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2811 }
2812
321fd21e
L		 2813 /* Zap movzx and movsx suffix. The suffix has been set from
2814 "word ptr" or "byte ptr" on the source operand in Intel syntax
2815 or extracted from mnemonic in AT&T syntax. But we'll use
2816 the destination register to choose the suffix for encoding. */
2817 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2818 {
321fd21e
L		 2819 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2820 there is no suffix, the default will be byte extension. */
2821 if (i.reg_operands != 2
2822 && !i.suffix
2823 && intel_syntax)
2824 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2825
2826 i.suffix = 0;
cd61ebfe 2827 }
24eab124 2828
40fb9820 2829 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2830 if (!add_prefix (FWAIT_OPCODE))
2831 return;
252b5132 2832
29b0f896 2833 /* Check string instruction segment overrides. */
40fb9820 2834 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2835 {
2836 if (!check_string ())
5dd0794d 2837 return;
fc0763e6 2838 i.disp_operands = 0;
29b0f896 2839 }
5dd0794d 2840
29b0f896
AM		 2841 if (!process_suffix ())
2842 return;
e413e4e9 2843
29b0f896
AM		 2844 /* Make still unresolved immediate matches conform to size of immediate
2845 given in i.suffix. */
2846 if (!finalize_imm ())
2847 return;
252b5132 2848
40fb9820 2849 if (i.types[0].bitfield.imm1)
29b0f896 2850 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2851
40fb9820 2852 for (j = 0; j < 3; j++)
c6fb90c8
L		 2853 if (i.types[j].bitfield.inoutportreg
2854 || i.types[j].bitfield.shiftcount
2855 || i.types[j].bitfield.acc
2856 || i.types[j].bitfield.floatacc)
40fb9820
L		 2857 i.reg_operands--;
2858
c0f3af97
L		 2859 /* ImmExt should be processed after SSE2AVX. */
2860 if (!i.tm.opcode_modifier.sse2avx
2861 && i.tm.opcode_modifier.immext)
65da13b5 2862 process_immext ();
252b5132 2863
29b0f896
AM		 2864 /* For insns with operands there are more diddles to do to the opcode. */
2865 if (i.operands)
2866 {
2867 if (!process_operands ())
2868 return;
2869 }
40fb9820 2870 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2871 {
2872 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2873 as_warn (_("translating to `%sp'"), i.tm.name);
2874 }
252b5132 2875
c0f3af97 2876 if (i.tm.opcode_modifier.vex)
fa99fab2 2877 build_vex_prefix (t);
c0f3af97 2878
29b0f896
AM		 2879 /* Handle conversion of 'int $3' --> special int3 insn. */
2880 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2881 {
2882 i.tm.base_opcode = INT3_OPCODE;
2883 i.imm_operands = 0;
2884 }
252b5132 2885
40fb9820
L		 2886 if ((i.tm.opcode_modifier.jump
2887 || i.tm.opcode_modifier.jumpbyte
2888 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2889 && i.op[0].disps->X_op == O_constant)
2890 {
2891 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2892 the absolute address given by the constant. Since ix86 jumps and
2893 calls are pc relative, we need to generate a reloc. */
2894 i.op[0].disps->X_add_symbol = &abs_symbol;
2895 i.op[0].disps->X_op = O_symbol;
2896 }
252b5132 2897
40fb9820 2898 if (i.tm.opcode_modifier.rex64)
161a04f6 2899 i.rex |= REX_W;
252b5132 2900
29b0f896
AM		 2901 /* For 8 bit registers we need an empty rex prefix. Also if the
2902 instruction already has a prefix, we need to convert old
2903 registers to new ones. */
773f551c 2904
40fb9820 2905 if ((i.types[0].bitfield.reg8
29b0f896 2906 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2907 || (i.types[1].bitfield.reg8
29b0f896 2908 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2909 || ((i.types[0].bitfield.reg8
2910 || i.types[1].bitfield.reg8)
29b0f896
AM		 2911 && i.rex != 0))
2912 {
2913 int x;
726c5dcd 2914
29b0f896
AM		 2915 i.rex |= REX_OPCODE;
2916 for (x = 0; x < 2; x++)
2917 {
2918 /* Look for 8 bit operand that uses old registers. */
40fb9820 2919 if (i.types[x].bitfield.reg8
29b0f896 2920 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2921 {
29b0f896
AM		 2922 /* In case it is "hi" register, give up. */
2923 if (i.op[x].regs->reg_num > 3)
a540244d 2924 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2925 "instruction requiring REX prefix."),
a540244d 2926 register_prefix, i.op[x].regs->reg_name);
773f551c 2927
29b0f896
AM		 2928 /* Otherwise it is equivalent to the extended register.
2929 Since the encoding doesn't change this is merely
2930 cosmetic cleanup for debug output. */
2931
2932 i.op[x].regs = i.op[x].regs + 8;
773f551c 2933 }
29b0f896
AM		 2934 }
2935 }
773f551c 2936
85f10a01
MM		 2937 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2938 REX prefix. */
2939 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2940 {
2941 i.drex.rex = i.rex;
2942 i.rex = 0;
2943 }
2944 else if (i.rex != 0)
29b0f896
AM		 2945 add_prefix (REX_OPCODE | i.rex);
2946
2947 /* We are ready to output the insn. */
2948 output_insn ();
2949}
2950
2951static char *
e3bb37b5 2952parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2953{
2954 char *l = line;
2955 char *token_start = l;
2956 char *mnem_p;
5c6af06e
JB		 2957 int supported;
2958 const template *t;
b6169b20 2959 char *dot_p = NULL;
29b0f896
AM		 2960
2961 /* Non-zero if we found a prefix only acceptable with string insns. */
2962 const char *expecting_string_instruction = NULL;
45288df1 2963
29b0f896
AM		 2964 while (1)
2965 {
2966 mnem_p = mnemonic;
2967 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2968 {
b6169b20
L		 2969 if (*mnem_p == '.')
2970 dot_p = mnem_p;
29b0f896
AM		 2971 mnem_p++;
2972 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2973 {
29b0f896
AM		 2974 as_bad (_("no such instruction: `%s'"), token_start);
2975 return NULL;
2976 }
2977 l++;
2978 }
2979 if (!is_space_char (*l)
2980 && *l != END_OF_INSN
e44823cf
JB		 2981 && (intel_syntax
2982 || (*l != PREFIX_SEPARATOR
2983 && *l != ',')))
29b0f896
AM		 2984 {
2985 as_bad (_("invalid character %s in mnemonic"),
2986 output_invalid (*l));
2987 return NULL;
2988 }
2989 if (token_start == l)
2990 {
e44823cf 2991 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2992 as_bad (_("expecting prefix; got nothing"));
2993 else
2994 as_bad (_("expecting mnemonic; got nothing"));
2995 return NULL;
2996 }
45288df1 2997
29b0f896
AM		 2998 /* Look up instruction (or prefix) via hash table. */
2999 current_templates = hash_find (op_hash, mnemonic);
47926f60 3000
29b0f896
AM		 3001 if (*l != END_OF_INSN
3002 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3003 && current_templates
40fb9820 3004 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3005 {
c6fb90c8 3006 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3007 {
3008 as_bad ((flag_code != CODE_64BIT
3009 ? _("`%s' is only supported in 64-bit mode")
3010 : _("`%s' is not supported in 64-bit mode")),
3011 current_templates->start->name);
3012 return NULL;
3013 }
29b0f896
AM		 3014 /* If we are in 16-bit mode, do not allow addr16 or data16.
3015 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3016 if ((current_templates->start->opcode_modifier.size16
3017 || current_templates->start->opcode_modifier.size32)
29b0f896 3018 && flag_code != CODE_64BIT
40fb9820 3019 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3020 ^ (flag_code == CODE_16BIT)))
3021 {
3022 as_bad (_("redundant %s prefix"),
3023 current_templates->start->name);
3024 return NULL;
45288df1 3025 }
29b0f896
AM		 3026 /* Add prefix, checking for repeated prefixes. */
3027 switch (add_prefix (current_templates->start->base_opcode))
3028 {
3029 case 0:
3030 return NULL;
3031 case 2:
3032 expecting_string_instruction = current_templates->start->name;
3033 break;
3034 }
3035 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3036 token_start = ++l;
3037 }
3038 else
3039 break;
3040 }
45288df1 3041
30a55f88 3042 if (!current_templates)
b6169b20 3043 {
30a55f88
L		 3044 /* Check if we should swap operand in encoding. */
3045 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3046 i.swap_operand = 1;
3047 else
3048 goto check_suffix;
3049 mnem_p = dot_p;
3050 *dot_p = '\0';
3051 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3052 }
3053
29b0f896
AM		 3054 if (!current_templates)
3055 {
b6169b20 3056check_suffix:
29b0f896
AM		 3057 /* See if we can get a match by trimming off a suffix. */
3058 switch (mnem_p[-1])
3059 {
3060 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3061 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3062 i.suffix = SHORT_MNEM_SUFFIX;
3063 else
29b0f896
AM		 3064 case BYTE_MNEM_SUFFIX:
3065 case QWORD_MNEM_SUFFIX:
3066 i.suffix = mnem_p[-1];
3067 mnem_p[-1] = '\0';
3068 current_templates = hash_find (op_hash, mnemonic);
3069 break;
3070 case SHORT_MNEM_SUFFIX:
3071 case LONG_MNEM_SUFFIX:
3072 if (!intel_syntax)
3073 {
3074 i.suffix = mnem_p[-1];
3075 mnem_p[-1] = '\0';
3076 current_templates = hash_find (op_hash, mnemonic);
3077 }
3078 break;
252b5132 3079
29b0f896
AM		 3080 /* Intel Syntax. */
3081 case 'd':
3082 if (intel_syntax)
3083 {
9306ca4a 3084 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3085 i.suffix = SHORT_MNEM_SUFFIX;
3086 else
3087 i.suffix = LONG_MNEM_SUFFIX;
3088 mnem_p[-1] = '\0';
3089 current_templates = hash_find (op_hash, mnemonic);
3090 }
3091 break;
3092 }
3093 if (!current_templates)
3094 {
3095 as_bad (_("no such instruction: `%s'"), token_start);
3096 return NULL;
3097 }
3098 }
252b5132 3099
40fb9820
L		 3100 if (current_templates->start->opcode_modifier.jump
3101 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3102 {
3103 /* Check for a branch hint. We allow ",pt" and ",pn" for
3104 predict taken and predict not taken respectively.
3105 I'm not sure that branch hints actually do anything on loop
3106 and jcxz insns (JumpByte) for current Pentium4 chips. They
3107 may work in the future and it doesn't hurt to accept them
3108 now. */
3109 if (l[0] == ',' && l[1] == 'p')
3110 {
3111 if (l[2] == 't')
3112 {
3113 if (!add_prefix (DS_PREFIX_OPCODE))
3114 return NULL;
3115 l += 3;
3116 }
3117 else if (l[2] == 'n')
3118 {
3119 if (!add_prefix (CS_PREFIX_OPCODE))
3120 return NULL;
3121 l += 3;
3122 }
3123 }
3124 }
3125 /* Any other comma loses. */
3126 if (*l == ',')
3127 {
3128 as_bad (_("invalid character %s in mnemonic"),
3129 output_invalid (*l));
3130 return NULL;
3131 }
252b5132 3132
29b0f896 3133 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3134 supported = 0;
3135 for (t = current_templates->start; t < current_templates->end; ++t)
3136 {
c0f3af97
L		 3137 supported |= cpu_flags_match (t);
3138 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3139 goto skip;
5c6af06e 3140 }
3629bb00 3141
c0f3af97 3142 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3143 {
3144 as_bad (flag_code == CODE_64BIT
3145 ? _("`%s' is not supported in 64-bit mode")
3146 : _("`%s' is only supported in 64-bit mode"),
3147 current_templates->start->name);
3148 return NULL;
3149 }
c0f3af97 3150 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3151 {
3629bb00
L		 3152 as_bad (_("`%s' is not supported on `%s%s'"),
3153 current_templates->start->name, cpu_arch_name,
3154 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3155 return NULL;
29b0f896 3156 }
3629bb00
L		 3157
3158skip:
3159 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3160 && (flag_code != CODE_16BIT))
29b0f896
AM		 3161 {
3162 as_warn (_("use .code16 to ensure correct addressing mode"));
3163 }
252b5132 3164
29b0f896 3165 /* Check for rep/repne without a string instruction. */
f41bbced 3166 if (expecting_string_instruction)
29b0f896 3167 {
f41bbced
JB		 3168 static templates override;
3169
3170 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3171 if (t->opcode_modifier.isstring)
f41bbced
JB		 3172 break;
3173 if (t >= current_templates->end)
3174 {
3175 as_bad (_("expecting string instruction after `%s'"),
64e74474 3176 expecting_string_instruction);
f41bbced
JB		 3177 return NULL;
3178 }
3179 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3180 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3181 break;
3182 override.end = t;
3183 current_templates = &override;
29b0f896 3184 }
252b5132 3185
29b0f896
AM		 3186 return l;
3187}
252b5132 3188
29b0f896 3189static char *
e3bb37b5 3190parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3191{
3192 char *token_start;
3138f287 3193
29b0f896
AM		 3194 /* 1 if operand is pending after ','. */
3195 unsigned int expecting_operand = 0;
252b5132 3196
29b0f896
AM		 3197 /* Non-zero if operand parens not balanced. */
3198 unsigned int paren_not_balanced;
3199
3200 while (*l != END_OF_INSN)
3201 {
3202 /* Skip optional white space before operand. */
3203 if (is_space_char (*l))
3204 ++l;
3205 if (!is_operand_char (*l) && *l != END_OF_INSN)
3206 {
3207 as_bad (_("invalid character %s before operand %d"),
3208 output_invalid (*l),
3209 i.operands + 1);
3210 return NULL;
3211 }
3212 token_start = l; /* after white space */
3213 paren_not_balanced = 0;
3214 while (paren_not_balanced || *l != ',')
3215 {
3216 if (*l == END_OF_INSN)
3217 {
3218 if (paren_not_balanced)
3219 {
3220 if (!intel_syntax)
3221 as_bad (_("unbalanced parenthesis in operand %d."),
3222 i.operands + 1);
3223 else
3224 as_bad (_("unbalanced brackets in operand %d."),
3225 i.operands + 1);
3226 return NULL;
3227 }
3228 else
3229 break; /* we are done */
3230 }
3231 else if (!is_operand_char (*l) && !is_space_char (*l))
3232 {
3233 as_bad (_("invalid character %s in operand %d"),
3234 output_invalid (*l),
3235 i.operands + 1);
3236 return NULL;
3237 }
3238 if (!intel_syntax)
3239 {
3240 if (*l == '(')
3241 ++paren_not_balanced;
3242 if (*l == ')')
3243 --paren_not_balanced;
3244 }
3245 else
3246 {
3247 if (*l == '[')
3248 ++paren_not_balanced;
3249 if (*l == ']')
3250 --paren_not_balanced;
3251 }
3252 l++;
3253 }
3254 if (l != token_start)
3255 { /* Yes, we've read in another operand. */
3256 unsigned int operand_ok;
3257 this_operand = i.operands++;
7d5e4556 3258 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3259 if (i.operands > MAX_OPERANDS)
3260 {
3261 as_bad (_("spurious operands; (%d operands/instruction max)"),
3262 MAX_OPERANDS);
3263 return NULL;
3264 }
3265 /* Now parse operand adding info to 'i' as we go along. */
3266 END_STRING_AND_SAVE (l);
3267
3268 if (intel_syntax)
3269 operand_ok =
3270 i386_intel_operand (token_start,
3271 intel_float_operand (mnemonic));
3272 else
a7619375 3273 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3274
3275 RESTORE_END_STRING (l);
3276 if (!operand_ok)
3277 return NULL;
3278 }
3279 else
3280 {
3281 if (expecting_operand)
3282 {
3283 expecting_operand_after_comma:
3284 as_bad (_("expecting operand after ','; got nothing"));
3285 return NULL;
3286 }
3287 if (*l == ',')
3288 {
3289 as_bad (_("expecting operand before ','; got nothing"));
3290 return NULL;
3291 }
3292 }
7f3f1ea2 3293
29b0f896
AM		 3294 /* Now *l must be either ',' or END_OF_INSN. */
3295 if (*l == ',')
3296 {
3297 if (*++l == END_OF_INSN)
3298 {
3299 /* Just skip it, if it's \n complain. */
3300 goto expecting_operand_after_comma;
3301 }
3302 expecting_operand = 1;
3303 }
3304 }
3305 return l;
3306}
7f3f1ea2 3307
050dfa73 3308static void
4d456e3d 3309swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3310{
3311 union i386_op temp_op;
40fb9820 3312 i386_operand_type temp_type;
050dfa73 3313 enum bfd_reloc_code_real temp_reloc;
4eed87de 3314
050dfa73
MM		 3315 temp_type = i.types[xchg2];
3316 i.types[xchg2] = i.types[xchg1];
3317 i.types[xchg1] = temp_type;
3318 temp_op = i.op[xchg2];
3319 i.op[xchg2] = i.op[xchg1];
3320 i.op[xchg1] = temp_op;
3321 temp_reloc = i.reloc[xchg2];
3322 i.reloc[xchg2] = i.reloc[xchg1];
3323 i.reloc[xchg1] = temp_reloc;
3324}
3325
29b0f896 3326static void
e3bb37b5 3327swap_operands (void)
29b0f896 3328{
b7c61d9a 3329 switch (i.operands)
050dfa73 3330 {
c0f3af97 3331 case 5:
b7c61d9a 3332 case 4:
4d456e3d 3333 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3334 case 3:
3335 case 2:
4d456e3d 3336 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3337 break;
3338 default:
3339 abort ();
29b0f896 3340 }
29b0f896
AM		 3341
3342 if (i.mem_operands == 2)
3343 {
3344 const seg_entry *temp_seg;
3345 temp_seg = i.seg[0];
3346 i.seg[0] = i.seg[1];
3347 i.seg[1] = temp_seg;
3348 }
3349}
252b5132 3350
29b0f896
AM		 3351/* Try to ensure constant immediates are represented in the smallest
3352 opcode possible. */
3353static void
e3bb37b5 3354optimize_imm (void)
29b0f896
AM		 3355{
3356 char guess_suffix = 0;
3357 int op;
252b5132 3358
29b0f896
AM		 3359 if (i.suffix)
3360 guess_suffix = i.suffix;
3361 else if (i.reg_operands)
3362 {
3363 /* Figure out a suffix from the last register operand specified.
3364 We can't do this properly yet, ie. excluding InOutPortReg,
3365 but the following works for instructions with immediates.
3366 In any case, we can't set i.suffix yet. */
3367 for (op = i.operands; --op >= 0;)
40fb9820
L		 3368 if (i.types[op].bitfield.reg8)
3369 {
3370 guess_suffix = BYTE_MNEM_SUFFIX;
3371 break;
3372 }
3373 else if (i.types[op].bitfield.reg16)
252b5132 3374 {
40fb9820
L		 3375 guess_suffix = WORD_MNEM_SUFFIX;
3376 break;
3377 }
3378 else if (i.types[op].bitfield.reg32)
3379 {
3380 guess_suffix = LONG_MNEM_SUFFIX;
3381 break;
3382 }
3383 else if (i.types[op].bitfield.reg64)
3384 {
3385 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3386 break;
252b5132 3387 }
29b0f896
AM		 3388 }
3389 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3390 guess_suffix = WORD_MNEM_SUFFIX;
3391
3392 for (op = i.operands; --op >= 0;)
40fb9820 3393 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3394 {
3395 switch (i.op[op].imms->X_op)
252b5132 3396 {
29b0f896
AM		 3397 case O_constant:
3398 /* If a suffix is given, this operand may be shortened. */
3399 switch (guess_suffix)
252b5132 3400 {
29b0f896 3401 case LONG_MNEM_SUFFIX:
40fb9820
L		 3402 i.types[op].bitfield.imm32 = 1;
3403 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3404 break;
3405 case WORD_MNEM_SUFFIX:
40fb9820
L		 3406 i.types[op].bitfield.imm16 = 1;
3407 i.types[op].bitfield.imm32 = 1;
3408 i.types[op].bitfield.imm32s = 1;
3409 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3410 break;
3411 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3412 i.types[op].bitfield.imm8 = 1;
3413 i.types[op].bitfield.imm8s = 1;
3414 i.types[op].bitfield.imm16 = 1;
3415 i.types[op].bitfield.imm32 = 1;
3416 i.types[op].bitfield.imm32s = 1;
3417 i.types[op].bitfield.imm64 = 1;
29b0f896 3418 break;
252b5132 3419 }
252b5132 3420
29b0f896
AM		 3421 /* If this operand is at most 16 bits, convert it
3422 to a signed 16 bit number before trying to see
3423 whether it will fit in an even smaller size.
3424 This allows a 16-bit operand such as $0xffe0 to
3425 be recognised as within Imm8S range. */
40fb9820 3426 if ((i.types[op].bitfield.imm16)
29b0f896 3427 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3428 {
29b0f896
AM		 3429 i.op[op].imms->X_add_number =
3430 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3431 }
40fb9820 3432 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3433 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3434 == 0))
3435 {
3436 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3437 ^ ((offsetT) 1 << 31))
3438 - ((offsetT) 1 << 31));
3439 }
40fb9820 3440 i.types[op]
c6fb90c8
L		 3441 = operand_type_or (i.types[op],
3442 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3443
29b0f896
AM		 3444 /* We must avoid matching of Imm32 templates when 64bit
3445 only immediate is available. */
3446 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3447 i.types[op].bitfield.imm32 = 0;
29b0f896 3448 break;
252b5132 3449
29b0f896
AM		 3450 case O_absent:
3451 case O_register:
3452 abort ();
3453
3454 /* Symbols and expressions. */
3455 default:
9cd96992
JB		 3456 /* Convert symbolic operand to proper sizes for matching, but don't
3457 prevent matching a set of insns that only supports sizes other
3458 than those matching the insn suffix. */
3459 {
40fb9820 3460 i386_operand_type mask, allowed;
9cd96992
JB		 3461 const template *t;
3462
0dfbf9d7
L		 3463 operand_type_set (&mask, 0);
3464 operand_type_set (&allowed, 0);
40fb9820 3465
4eed87de
AM		 3466 for (t = current_templates->start;
3467 t < current_templates->end;
3468 ++t)
c6fb90c8
L		 3469 allowed = operand_type_or (allowed,
3470 t->operand_types[op]);
9cd96992
JB		 3471 switch (guess_suffix)
3472 {
3473 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3474 mask.bitfield.imm64 = 1;
3475 mask.bitfield.imm32s = 1;
9cd96992
JB		 3476 break;
3477 case LONG_MNEM_SUFFIX:
40fb9820 3478 mask.bitfield.imm32 = 1;
9cd96992
JB		 3479 break;
3480 case WORD_MNEM_SUFFIX:
40fb9820 3481 mask.bitfield.imm16 = 1;
9cd96992
JB		 3482 break;
3483 case BYTE_MNEM_SUFFIX:
40fb9820 3484 mask.bitfield.imm8 = 1;
9cd96992
JB		 3485 break;
3486 default:
9cd96992
JB		 3487 break;
3488 }
c6fb90c8 3489 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3490 if (!operand_type_all_zero (&allowed))
c6fb90c8 3491 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3492 }
29b0f896 3493 break;
252b5132 3494 }
29b0f896
AM		 3495 }
3496}
47926f60 3497
29b0f896
AM		 3498/* Try to use the smallest displacement type too. */
3499static void
e3bb37b5 3500optimize_disp (void)
29b0f896
AM		 3501{
3502 int op;
3e73aa7c 3503
29b0f896 3504 for (op = i.operands; --op >= 0;)
40fb9820 3505 if (operand_type_check (i.types[op], disp))
252b5132 3506 {
b300c311 3507 if (i.op[op].disps->X_op == O_constant)
252b5132 3508 {
b300c311 3509 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3510
40fb9820 3511 if (i.types[op].bitfield.disp16
b300c311
L		 3512 && (disp & ~(offsetT) 0xffff) == 0)
3513 {
3514 /* If this operand is at most 16 bits, convert
3515 to a signed 16 bit number and don't use 64bit
3516 displacement. */
3517 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3518 i.types[op].bitfield.disp64 = 0;
b300c311 3519 }
40fb9820 3520 if (i.types[op].bitfield.disp32
b300c311
L		 3521 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3522 {
3523 /* If this operand is at most 32 bits, convert
3524 to a signed 32 bit number and don't use 64bit
3525 displacement. */
3526 disp &= (((offsetT) 2 << 31) - 1);
3527 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3528 i.types[op].bitfield.disp64 = 0;
b300c311 3529 }
40fb9820 3530 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3531 {
40fb9820
L		 3532 i.types[op].bitfield.disp8 = 0;
3533 i.types[op].bitfield.disp16 = 0;
3534 i.types[op].bitfield.disp32 = 0;
3535 i.types[op].bitfield.disp32s = 0;
3536 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3537 i.op[op].disps = 0;
3538 i.disp_operands--;
3539 }
3540 else if (flag_code == CODE_64BIT)
3541 {
3542 if (fits_in_signed_long (disp))
28a9d8f5 3543 {
40fb9820
L		 3544 i.types[op].bitfield.disp64 = 0;
3545 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3546 }
b300c311 3547 if (fits_in_unsigned_long (disp))
40fb9820 3548 i.types[op].bitfield.disp32 = 1;
b300c311 3549 }
40fb9820
L		 3550 if ((i.types[op].bitfield.disp32
3551 || i.types[op].bitfield.disp32s
3552 || i.types[op].bitfield.disp16)
b300c311 3553 && fits_in_signed_byte (disp))
40fb9820 3554 i.types[op].bitfield.disp8 = 1;
252b5132 3555 }
67a4f2b7
AO		 3556 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3557 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3558 {
3559 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3560 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3561 i.types[op].bitfield.disp8 = 0;
3562 i.types[op].bitfield.disp16 = 0;
3563 i.types[op].bitfield.disp32 = 0;
3564 i.types[op].bitfield.disp32s = 0;
3565 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3566 }
3567 else
b300c311 3568 /* We only support 64bit displacement on constants. */
40fb9820 3569 i.types[op].bitfield.disp64 = 0;
252b5132 3570 }
29b0f896
AM		 3571}
3572
fa99fab2 3573static const template *
e3bb37b5 3574match_template (void)
29b0f896
AM		 3575{
3576 /* Points to template once we've found it. */
3577 const template *t;
40fb9820 3578 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3579 i386_operand_type overlap4;
29b0f896 3580 unsigned int found_reverse_match;
40fb9820
L		 3581 i386_opcode_modifier suffix_check;
3582 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3583 int addr_prefix_disp;
a5c311ca 3584 unsigned int j;
3629bb00 3585 unsigned int found_cpu_match;
45664ddb 3586 unsigned int check_register;
29b0f896 3587
c0f3af97
L		 3588#if MAX_OPERANDS != 5
3589# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3590#endif
3591
29b0f896 3592 found_reverse_match = 0;
539e75ad 3593 addr_prefix_disp = -1;
40fb9820
L		 3594
3595 memset (&suffix_check, 0, sizeof (suffix_check));
3596 if (i.suffix == BYTE_MNEM_SUFFIX)
3597 suffix_check.no_bsuf = 1;
3598 else if (i.suffix == WORD_MNEM_SUFFIX)
3599 suffix_check.no_wsuf = 1;
3600 else if (i.suffix == SHORT_MNEM_SUFFIX)
3601 suffix_check.no_ssuf = 1;
3602 else if (i.suffix == LONG_MNEM_SUFFIX)
3603 suffix_check.no_lsuf = 1;
3604 else if (i.suffix == QWORD_MNEM_SUFFIX)
3605 suffix_check.no_qsuf = 1;
3606 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3607 suffix_check.no_ldsuf = 1;
29b0f896 3608
45aa61fe 3609 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3610 {
539e75ad
L		 3611 addr_prefix_disp = -1;
3612
29b0f896
AM		 3613 /* Must have right number of operands. */
3614 if (i.operands != t->operands)
3615 continue;
3616
50aecf8c 3617 /* Check processor support. */
c0f3af97
L		 3618 found_cpu_match = (cpu_flags_match (t)
3619 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3620 if (!found_cpu_match)
3621 continue;
3622
e1d4d893
L		 3623 /* Check old gcc support. */
3624 if (!old_gcc && t->opcode_modifier.oldgcc)
3625 continue;
3626
3627 /* Check AT&T mnemonic. */
3628 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3629 continue;
3630
5c07affc
L		 3631 /* Check AT&T syntax Intel syntax. */
3632 if ((intel_syntax && t->opcode_modifier.attsyntax)
3633 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3634 continue;
3635
20592a94 3636 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3637 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3638 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3639 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3640 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3641 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3642 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3643 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3644 continue;
3645
5c07affc 3646 if (!operand_size_match (t))
7d5e4556 3647 continue;
539e75ad 3648
5c07affc
L		 3649 for (j = 0; j < MAX_OPERANDS; j++)
3650 operand_types[j] = t->operand_types[j];
3651
45aa61fe
AM		 3652 /* In general, don't allow 64-bit operands in 32-bit mode. */
3653 if (i.suffix == QWORD_MNEM_SUFFIX
3654 && flag_code != CODE_64BIT
3655 && (intel_syntax
40fb9820 3656 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3657 && !intel_float_operand (t->name))
3658 : intel_float_operand (t->name) != 2)
40fb9820 3659 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3660 && !operand_types[0].bitfield.regxmm
3661 && !operand_types[0].bitfield.regymm)
40fb9820 3662 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3663 && !!operand_types[t->operands > 1].bitfield.regxmm
3664 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3665 && (t->base_opcode != 0x0fc7
3666 || t->extension_opcode != 1 /* cmpxchg8b */))
3667 continue;
3668
192dc9c6
JB		 3669 /* In general, don't allow 32-bit operands on pre-386. */
3670 else if (i.suffix == LONG_MNEM_SUFFIX
3671 && !cpu_arch_flags.bitfield.cpui386
3672 && (intel_syntax
3673 ? (!t->opcode_modifier.ignoresize
3674 && !intel_float_operand (t->name))
3675 : intel_float_operand (t->name) != 2)
3676 && ((!operand_types[0].bitfield.regmmx
3677 && !operand_types[0].bitfield.regxmm)
3678 || (!operand_types[t->operands > 1].bitfield.regmmx
3679 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3680 continue;
3681
29b0f896 3682 /* Do not verify operands when there are none. */
50aecf8c 3683 else
29b0f896 3684 {
c6fb90c8 3685 if (!t->operands)
2dbab7d5
L		 3686 /* We've found a match; break out of loop. */
3687 break;
29b0f896 3688 }
252b5132 3689
539e75ad
L		 3690 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3691 into Disp32/Disp16/Disp32 operand. */
3692 if (i.prefix[ADDR_PREFIX] != 0)
3693 {
40fb9820 3694 /* There should be only one Disp operand. */
539e75ad
L		 3695 switch (flag_code)
3696 {
3697 case CODE_16BIT:
40fb9820
L		 3698 for (j = 0; j < MAX_OPERANDS; j++)
3699 {
3700 if (operand_types[j].bitfield.disp16)
3701 {
3702 addr_prefix_disp = j;
3703 operand_types[j].bitfield.disp32 = 1;
3704 operand_types[j].bitfield.disp16 = 0;
3705 break;
3706 }
3707 }
539e75ad
L		 3708 break;
3709 case CODE_32BIT:
40fb9820
L		 3710 for (j = 0; j < MAX_OPERANDS; j++)
3711 {
3712 if (operand_types[j].bitfield.disp32)
3713 {
3714 addr_prefix_disp = j;
3715 operand_types[j].bitfield.disp32 = 0;
3716 operand_types[j].bitfield.disp16 = 1;
3717 break;
3718 }
3719 }
539e75ad
L		 3720 break;
3721 case CODE_64BIT:
40fb9820
L		 3722 for (j = 0; j < MAX_OPERANDS; j++)
3723 {
3724 if (operand_types[j].bitfield.disp64)
3725 {
3726 addr_prefix_disp = j;
3727 operand_types[j].bitfield.disp64 = 0;
3728 operand_types[j].bitfield.disp32 = 1;
3729 break;
3730 }
3731 }
539e75ad
L		 3732 break;
3733 }
539e75ad
L		 3734 }
3735
45664ddb
L		 3736 /* We check register size only if size of operands can be
3737 encoded the canonical way. */
3738 check_register = t->opcode_modifier.w;
c6fb90c8 3739 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3740 switch (t->operands)
3741 {
3742 case 1:
40fb9820 3743 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3744 continue;
3745 break;
3746 case 2:
8b38ad71
L		 3747 /* xchg %eax, %eax is a special case. It is an aliase for nop
3748 only in 32bit mode and we can use opcode 0x90. In 64bit
3749 mode, we can't use 0x90 for xchg %eax, %eax since it should
3750 zero-extend %eax to %rax. */
3751 if (flag_code == CODE_64BIT
3752 && t->base_opcode == 0x90
0dfbf9d7
L		 3753 && operand_type_equal (&i.types [0], &acc32)
3754 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3755 continue;
b6169b20
L		 3756 if (i.swap_operand)
3757 {
3758 /* If we swap operand in encoding, we either match
3759 the next one or reverse direction of operands. */
3760 if (t->opcode_modifier.s)
3761 continue;
3762 else if (t->opcode_modifier.d)
3763 goto check_reverse;
3764 }
3765
29b0f896 3766 case 3:
fa99fab2
L		 3767 /* If we swap operand in encoding, we match the next one. */
3768 if (i.swap_operand && t->opcode_modifier.s)
3769 continue;
f48ff2ae 3770 case 4:
c0f3af97 3771 case 5:
c6fb90c8 3772 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3773 if (!operand_type_match (overlap0, i.types[0])
3774 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3775 || (check_register
3776 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3777 operand_types[0],
3778 overlap1, i.types[1],
3779 operand_types[1])))
29b0f896
AM		 3780 {
3781 /* Check if other direction is valid ... */
40fb9820 3782 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3783 continue;
3784
b6169b20 3785check_reverse:
29b0f896 3786 /* Try reversing direction of operands. */
c6fb90c8
L		 3787 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3788 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3789 if (!operand_type_match (overlap0, i.types[0])
3790 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3791 || (check_register
3792 && !operand_type_register_match (overlap0,
3793 i.types[0],
3794 operand_types[1],
3795 overlap1,
3796 i.types[1],
3797 operand_types[0])))
29b0f896
AM		 3798 {
3799 /* Does not match either direction. */
3800 continue;
3801 }
3802 /* found_reverse_match holds which of D or FloatDR
3803 we've found. */
40fb9820 3804 if (t->opcode_modifier.d)
8a2ed489 3805 found_reverse_match = Opcode_D;
40fb9820 3806 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3807 found_reverse_match = Opcode_FloatD;
3808 else
3809 found_reverse_match = 0;
40fb9820 3810 if (t->opcode_modifier.floatr)
8a2ed489 3811 found_reverse_match |= Opcode_FloatR;
29b0f896 3812 }
f48ff2ae 3813 else
29b0f896 3814 {
f48ff2ae 3815 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3816 switch (t->operands)
3817 {
c0f3af97
L		 3818 case 5:
3819 overlap4 = operand_type_and (i.types[4],
3820 operand_types[4]);
d1cbb4db 3821 case 4:
c6fb90c8
L		 3822 overlap3 = operand_type_and (i.types[3],
3823 operand_types[3]);
d1cbb4db 3824 case 3:
c6fb90c8
L		 3825 overlap2 = operand_type_and (i.types[2],
3826 operand_types[2]);
d1cbb4db
L		 3827 break;
3828 }
29b0f896 3829
f48ff2ae
L		 3830 switch (t->operands)
3831 {
c0f3af97
L		 3832 case 5:
3833 if (!operand_type_match (overlap4, i.types[4])
3834 || !operand_type_register_match (overlap3,
3835 i.types[3],
3836 operand_types[3],
3837 overlap4,
3838 i.types[4],
3839 operand_types[4]))
3840 continue;
f48ff2ae 3841 case 4:
40fb9820 3842 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3843 || (check_register
3844 && !operand_type_register_match (overlap2,
3845 i.types[2],
3846 operand_types[2],
3847 overlap3,
3848 i.types[3],
3849 operand_types[3])))
f48ff2ae
L		 3850 continue;
3851 case 3:
3852 /* Here we make use of the fact that there are no
3853 reverse match 3 operand instructions, and all 3
3854 operand instructions only need to be checked for
3855 register consistency between operands 2 and 3. */
40fb9820 3856 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3857 || (check_register
3858 && !operand_type_register_match (overlap1,
3859 i.types[1],
3860 operand_types[1],
3861 overlap2,
3862 i.types[2],
3863 operand_types[2])))
f48ff2ae
L		 3864 continue;
3865 break;
3866 }
29b0f896 3867 }
f48ff2ae 3868 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3869 slip through to break. */
3870 }
3629bb00 3871 if (!found_cpu_match)
29b0f896
AM		 3872 {
3873 found_reverse_match = 0;
3874 continue;
3875 }
c0f3af97 3876
29b0f896
AM		 3877 /* We've found a match; break out of loop. */
3878 break;
3879 }
3880
3881 if (t == current_templates->end)
3882 {
3883 /* We found no match. */
95f283e8
L		 3884 if (intel_syntax)
3885 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3886 current_templates->start->name);
3887 else
3888 as_bad (_("suffix or operands invalid for `%s'"),
3889 current_templates->start->name);
fa99fab2 3890 return NULL;
29b0f896 3891 }
252b5132 3892
29b0f896
AM		 3893 if (!quiet_warnings)
3894 {
3895 if (!intel_syntax
40fb9820
L		 3896 && (i.types[0].bitfield.jumpabsolute
3897 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3898 {
3899 as_warn (_("indirect %s without `*'"), t->name);
3900 }
3901
40fb9820
L		 3902 if (t->opcode_modifier.isprefix
3903 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3904 {
3905 /* Warn them that a data or address size prefix doesn't
3906 affect assembly of the next line of code. */
3907 as_warn (_("stand-alone `%s' prefix"), t->name);
3908 }
3909 }
3910
3911 /* Copy the template we found. */
3912 i.tm = *t;
539e75ad
L		 3913
3914 if (addr_prefix_disp != -1)
3915 i.tm.operand_types[addr_prefix_disp]
3916 = operand_types[addr_prefix_disp];
3917
29b0f896
AM		 3918 if (found_reverse_match)
3919 {
3920 /* If we found a reverse match we must alter the opcode
3921 direction bit. found_reverse_match holds bits to change
3922 (different for int & float insns). */
3923
3924 i.tm.base_opcode ^= found_reverse_match;
3925
539e75ad
L		 3926 i.tm.operand_types[0] = operand_types[1];
3927 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3928 }
3929
fa99fab2 3930 return t;
29b0f896
AM		 3931}
3932
3933static int
e3bb37b5 3934check_string (void)
29b0f896 3935{
40fb9820
L		 3936 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3937 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3938 {
3939 if (i.seg[0] != NULL && i.seg[0] != &es)
3940 {
a87af027 3941 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3942 i.tm.name,
a87af027
JB		 3943 mem_op + 1,
3944 register_prefix);
29b0f896
AM		 3945 return 0;
3946 }
3947 /* There's only ever one segment override allowed per instruction.
3948 This instruction possibly has a legal segment override on the
3949 second operand, so copy the segment to where non-string
3950 instructions store it, allowing common code. */
3951 i.seg[0] = i.seg[1];
3952 }
40fb9820 3953 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3954 {
3955 if (i.seg[1] != NULL && i.seg[1] != &es)
3956 {
a87af027 3957 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3958 i.tm.name,
a87af027
JB		 3959 mem_op + 2,
3960 register_prefix);
29b0f896
AM		 3961 return 0;
3962 }
3963 }
3964 return 1;
3965}
3966
3967static int
543613e9 3968process_suffix (void)
29b0f896
AM		 3969{
3970 /* If matched instruction specifies an explicit instruction mnemonic
3971 suffix, use it. */
40fb9820
L		 3972 if (i.tm.opcode_modifier.size16)
3973 i.suffix = WORD_MNEM_SUFFIX;
3974 else if (i.tm.opcode_modifier.size32)
3975 i.suffix = LONG_MNEM_SUFFIX;
3976 else if (i.tm.opcode_modifier.size64)
3977 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3978 else if (i.reg_operands)
3979 {
3980 /* If there's no instruction mnemonic suffix we try to invent one
3981 based on register operands. */
3982 if (!i.suffix)
3983 {
3984 /* We take i.suffix from the last register operand specified,
3985 Destination register type is more significant than source
381d071f
L		 3986 register type. crc32 in SSE4.2 prefers source register
3987 type. */
3988 if (i.tm.base_opcode == 0xf20f38f1)
3989 {
40fb9820
L		 3990 if (i.types[0].bitfield.reg16)
3991 i.suffix = WORD_MNEM_SUFFIX;
3992 else if (i.types[0].bitfield.reg32)
3993 i.suffix = LONG_MNEM_SUFFIX;
3994 else if (i.types[0].bitfield.reg64)
3995 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3996 }
9344ff29 3997 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3998 {
40fb9820 3999 if (i.types[0].bitfield.reg8)
20592a94
L		 4000 i.suffix = BYTE_MNEM_SUFFIX;
4001 }
381d071f
L		 4002
4003 if (!i.suffix)
4004 {
4005 int op;
4006
20592a94
L		 4007 if (i.tm.base_opcode == 0xf20f38f1
4008 || i.tm.base_opcode == 0xf20f38f0)
4009 {
4010 /* We have to know the operand size for crc32. */
4011 as_bad (_("ambiguous memory operand size for `%s`"),
4012 i.tm.name);
4013 return 0;
4014 }
4015
381d071f 4016 for (op = i.operands; --op >= 0;)
40fb9820 4017 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4018 {
40fb9820
L		 4019 if (i.types[op].bitfield.reg8)
4020 {
4021 i.suffix = BYTE_MNEM_SUFFIX;
4022 break;
4023 }
4024 else if (i.types[op].bitfield.reg16)
4025 {
4026 i.suffix = WORD_MNEM_SUFFIX;
4027 break;
4028 }
4029 else if (i.types[op].bitfield.reg32)
4030 {
4031 i.suffix = LONG_MNEM_SUFFIX;
4032 break;
4033 }
4034 else if (i.types[op].bitfield.reg64)
4035 {
4036 i.suffix = QWORD_MNEM_SUFFIX;
4037 break;
4038 }
381d071f
L		 4039 }
4040 }
29b0f896
AM		 4041 }
4042 else if (i.suffix == BYTE_MNEM_SUFFIX)
4043 {
4044 if (!check_byte_reg ())
4045 return 0;
4046 }
4047 else if (i.suffix == LONG_MNEM_SUFFIX)
4048 {
4049 if (!check_long_reg ())
4050 return 0;
4051 }
4052 else if (i.suffix == QWORD_MNEM_SUFFIX)
4053 {
955e1e6a
L		 4054 if (intel_syntax
4055 && i.tm.opcode_modifier.ignoresize
4056 && i.tm.opcode_modifier.no_qsuf)
4057 i.suffix = 0;
4058 else if (!check_qword_reg ())
29b0f896
AM		 4059 return 0;
4060 }
4061 else if (i.suffix == WORD_MNEM_SUFFIX)
4062 {
4063 if (!check_word_reg ())
4064 return 0;
4065 }
c0f3af97
L		 4066 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4067 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4068 {
c0f3af97 4069 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4070 should check if it is a valid suffix. */
4071 }
40fb9820 4072 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4073 /* Do nothing if the instruction is going to ignore the prefix. */
4074 ;
4075 else
4076 abort ();
4077 }
40fb9820 4078 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4079 && !i.suffix
4080 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4081 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4082 {
4083 i.suffix = stackop_size;
4084 }
9306ca4a
JB		 4085 else if (intel_syntax
4086 && !i.suffix
40fb9820
L		 4087 && (i.tm.operand_types[0].bitfield.jumpabsolute
4088 || i.tm.opcode_modifier.jumpbyte
4089 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4090 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4091 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4092 {
4093 switch (flag_code)
4094 {
4095 case CODE_64BIT:
40fb9820 4096 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4097 {
4098 i.suffix = QWORD_MNEM_SUFFIX;
4099 break;
4100 }
4101 case CODE_32BIT:
40fb9820 4102 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4103 i.suffix = LONG_MNEM_SUFFIX;
4104 break;
4105 case CODE_16BIT:
40fb9820 4106 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4107 i.suffix = WORD_MNEM_SUFFIX;
4108 break;
4109 }
4110 }
252b5132 4111
9306ca4a 4112 if (!i.suffix)
29b0f896 4113 {
9306ca4a
JB		 4114 if (!intel_syntax)
4115 {
40fb9820 4116 if (i.tm.opcode_modifier.w)
9306ca4a 4117 {
4eed87de
AM		 4118 as_bad (_("no instruction mnemonic suffix given and "
4119 "no register operands; can't size instruction"));
9306ca4a
JB		 4120 return 0;
4121 }
4122 }
4123 else
4124 {
40fb9820
L		 4125 unsigned int suffixes;
4126
4127 suffixes = !i.tm.opcode_modifier.no_bsuf;
4128 if (!i.tm.opcode_modifier.no_wsuf)
4129 suffixes |= 1 << 1;
4130 if (!i.tm.opcode_modifier.no_lsuf)
4131 suffixes |= 1 << 2;
fc4adea1 4132 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4133 suffixes |= 1 << 3;
4134 if (!i.tm.opcode_modifier.no_ssuf)
4135 suffixes |= 1 << 4;
4136 if (!i.tm.opcode_modifier.no_qsuf)
4137 suffixes |= 1 << 5;
4138
4139 /* There are more than suffix matches. */
4140 if (i.tm.opcode_modifier.w
9306ca4a 4141 || ((suffixes & (suffixes - 1))
40fb9820
L		 4142 && !i.tm.opcode_modifier.defaultsize
4143 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4144 {
4145 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4146 return 0;
4147 }
4148 }
29b0f896 4149 }
252b5132 4150
9306ca4a
JB		 4151 /* Change the opcode based on the operand size given by i.suffix;
4152 We don't need to change things for byte insns. */
4153
582d5edd
L		 4154 if (i.suffix
4155 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4156 && i.suffix != XMMWORD_MNEM_SUFFIX
4157 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4158 {
4159 /* It's not a byte, select word/dword operation. */
40fb9820 4160 if (i.tm.opcode_modifier.w)
29b0f896 4161 {
40fb9820 4162 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4163 i.tm.base_opcode |= 8;
4164 else
4165 i.tm.base_opcode |= 1;
4166 }
0f3f3d8b 4167
29b0f896
AM		 4168 /* Now select between word & dword operations via the operand
4169 size prefix, except for instructions that will ignore this
4170 prefix anyway. */
ca61edf2 4171 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4172 {
ca61edf2
L		 4173 /* The address size override prefix changes the size of the
4174 first operand. */
40fb9820
L		 4175 if ((flag_code == CODE_32BIT
4176 && i.op->regs[0].reg_type.bitfield.reg16)
4177 || (flag_code != CODE_32BIT
4178 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4179 if (!add_prefix (ADDR_PREFIX_OPCODE))
4180 return 0;
4181 }
4182 else if (i.suffix != QWORD_MNEM_SUFFIX
4183 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4184 && !i.tm.opcode_modifier.ignoresize
4185 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4186 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4187 || (flag_code == CODE_64BIT
40fb9820 4188 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4189 {
4190 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4191
40fb9820 4192 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4193 prefix = ADDR_PREFIX_OPCODE;
252b5132 4194
29b0f896
AM		 4195 if (!add_prefix (prefix))
4196 return 0;
24eab124 4197 }
252b5132 4198
29b0f896
AM		 4199 /* Set mode64 for an operand. */
4200 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4201 && flag_code == CODE_64BIT
40fb9820 4202 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4203 {
4204 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4205 need rex64. cmpxchg8b is also a special case. */
4206 if (! (i.operands == 2
4207 && i.tm.base_opcode == 0x90
4208 && i.tm.extension_opcode == None
0dfbf9d7
L		 4209 && operand_type_equal (&i.types [0], &acc64)
4210 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4211 && ! (i.operands == 1
4212 && i.tm.base_opcode == 0xfc7
4213 && i.tm.extension_opcode == 1
40fb9820
L		 4214 && !operand_type_check (i.types [0], reg)
4215 && operand_type_check (i.types [0], anymem)))
f6bee062 4216 i.rex |= REX_W;
46e883c5 4217 }
3e73aa7c 4218
29b0f896
AM		 4219 /* Size floating point instruction. */
4220 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4221 if (i.tm.opcode_modifier.floatmf)
543613e9 4222 i.tm.base_opcode ^= 4;
29b0f896 4223 }
7ecd2f8b 4224
29b0f896
AM		 4225 return 1;
4226}
3e73aa7c 4227
29b0f896 4228static int
543613e9 4229check_byte_reg (void)
29b0f896
AM		 4230{
4231 int op;
543613e9 4232
29b0f896
AM		 4233 for (op = i.operands; --op >= 0;)
4234 {
4235 /* If this is an eight bit register, it's OK. If it's the 16 or
4236 32 bit version of an eight bit register, we will just use the
4237 low portion, and that's OK too. */
40fb9820 4238 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4239 continue;
4240
ca61edf2
L		 4241 /* Don't generate this warning if not needed. */
4242 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4243 continue;
4244
9344ff29
L		 4245 /* crc32 doesn't generate this warning. */
4246 if (i.tm.base_opcode == 0xf20f38f0)
4247 continue;
4248
40fb9820
L		 4249 if ((i.types[op].bitfield.reg16
4250 || i.types[op].bitfield.reg32
4251 || i.types[op].bitfield.reg64)
4252 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4253 {
4254 /* Prohibit these changes in the 64bit mode, since the
4255 lowering is more complicated. */
4256 if (flag_code == CODE_64BIT
40fb9820 4257 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4258 {
2ca3ace5
L		 4259 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4260 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4261 i.suffix);
4262 return 0;
4263 }
4264#if REGISTER_WARNINGS
4265 if (!quiet_warnings
40fb9820 4266 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4267 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4268 register_prefix,
40fb9820 4269 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4270 ? REGNAM_AL - REGNAM_AX
4271 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4272 register_prefix,
29b0f896
AM		 4273 i.op[op].regs->reg_name,
4274 i.suffix);
4275#endif
4276 continue;
4277 }
4278 /* Any other register is bad. */
40fb9820
L		 4279 if (i.types[op].bitfield.reg16
4280 || i.types[op].bitfield.reg32
4281 || i.types[op].bitfield.reg64
4282 || i.types[op].bitfield.regmmx
4283 || i.types[op].bitfield.regxmm
c0f3af97 4284 || i.types[op].bitfield.regymm
40fb9820
L		 4285 || i.types[op].bitfield.sreg2
4286 || i.types[op].bitfield.sreg3
4287 || i.types[op].bitfield.control
4288 || i.types[op].bitfield.debug
4289 || i.types[op].bitfield.test
4290 || i.types[op].bitfield.floatreg
4291 || i.types[op].bitfield.floatacc)
29b0f896 4292 {
a540244d
L		 4293 as_bad (_("`%s%s' not allowed with `%s%c'"),
4294 register_prefix,
29b0f896
AM		 4295 i.op[op].regs->reg_name,
4296 i.tm.name,
4297 i.suffix);
4298 return 0;
4299 }
4300 }
4301 return 1;
4302}
4303
4304static int
e3bb37b5 4305check_long_reg (void)
29b0f896
AM		 4306{
4307 int op;
4308
4309 for (op = i.operands; --op >= 0;)
4310 /* Reject eight bit registers, except where the template requires
4311 them. (eg. movzb) */
40fb9820
L		 4312 if (i.types[op].bitfield.reg8
4313 && (i.tm.operand_types[op].bitfield.reg16
4314 || i.tm.operand_types[op].bitfield.reg32
4315 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4316 {
a540244d
L		 4317 as_bad (_("`%s%s' not allowed with `%s%c'"),
4318 register_prefix,
29b0f896
AM		 4319 i.op[op].regs->reg_name,
4320 i.tm.name,
4321 i.suffix);
4322 return 0;
4323 }
4324 /* Warn if the e prefix on a general reg is missing. */
4325 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4326 && i.types[op].bitfield.reg16
4327 && (i.tm.operand_types[op].bitfield.reg32
4328 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4329 {
4330 /* Prohibit these changes in the 64bit mode, since the
4331 lowering is more complicated. */
4332 if (flag_code == CODE_64BIT)
252b5132 4333 {
2ca3ace5
L		 4334 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4335 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4336 i.suffix);
4337 return 0;
252b5132 4338 }
29b0f896
AM		 4339#if REGISTER_WARNINGS
4340 else
a540244d
L		 4341 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4342 register_prefix,
29b0f896 4343 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4344 register_prefix,
29b0f896
AM		 4345 i.op[op].regs->reg_name,
4346 i.suffix);
4347#endif
252b5132 4348 }
29b0f896 4349 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4350 else if (i.types[op].bitfield.reg64
4351 && (i.tm.operand_types[op].bitfield.reg32
4352 || i.tm.operand_types[op].bitfield.acc))
252b5132 4353 {
34828aad 4354 if (intel_syntax
ca61edf2 4355 && i.tm.opcode_modifier.toqword
40fb9820 4356 && !i.types[0].bitfield.regxmm)
34828aad 4357 {
ca61edf2 4358 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4359 i.suffix = QWORD_MNEM_SUFFIX;
4360 }
4361 else
4362 {
4363 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4364 register_prefix, i.op[op].regs->reg_name,
4365 i.suffix);
4366 return 0;
4367 }
29b0f896
AM		 4368 }
4369 return 1;
4370}
252b5132 4371
29b0f896 4372static int
e3bb37b5 4373check_qword_reg (void)
29b0f896
AM		 4374{
4375 int op;
252b5132 4376
29b0f896
AM		 4377 for (op = i.operands; --op >= 0; )
4378 /* Reject eight bit registers, except where the template requires
4379 them. (eg. movzb) */
40fb9820
L		 4380 if (i.types[op].bitfield.reg8
4381 && (i.tm.operand_types[op].bitfield.reg16
4382 || i.tm.operand_types[op].bitfield.reg32
4383 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4384 {
a540244d
L		 4385 as_bad (_("`%s%s' not allowed with `%s%c'"),
4386 register_prefix,
29b0f896
AM		 4387 i.op[op].regs->reg_name,
4388 i.tm.name,
4389 i.suffix);
4390 return 0;
4391 }
4392 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4393 else if ((i.types[op].bitfield.reg16
4394 || i.types[op].bitfield.reg32)
4395 && (i.tm.operand_types[op].bitfield.reg32
4396 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4397 {
4398 /* Prohibit these changes in the 64bit mode, since the
4399 lowering is more complicated. */
34828aad 4400 if (intel_syntax
ca61edf2 4401 && i.tm.opcode_modifier.todword
40fb9820 4402 && !i.types[0].bitfield.regxmm)
34828aad 4403 {
ca61edf2 4404 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4405 i.suffix = LONG_MNEM_SUFFIX;
4406 }
4407 else
4408 {
4409 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4410 register_prefix, i.op[op].regs->reg_name,
4411 i.suffix);
4412 return 0;
4413 }
252b5132 4414 }
29b0f896
AM		 4415 return 1;
4416}
252b5132 4417
29b0f896 4418static int
e3bb37b5 4419check_word_reg (void)
29b0f896
AM		 4420{
4421 int op;
4422 for (op = i.operands; --op >= 0;)
4423 /* Reject eight bit registers, except where the template requires
4424 them. (eg. movzb) */
40fb9820
L		 4425 if (i.types[op].bitfield.reg8
4426 && (i.tm.operand_types[op].bitfield.reg16
4427 || i.tm.operand_types[op].bitfield.reg32
4428 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4429 {
a540244d
L		 4430 as_bad (_("`%s%s' not allowed with `%s%c'"),
4431 register_prefix,
29b0f896
AM		 4432 i.op[op].regs->reg_name,
4433 i.tm.name,
4434 i.suffix);
4435 return 0;
4436 }
4437 /* Warn if the e prefix on a general reg is present. */
4438 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4439 && i.types[op].bitfield.reg32
4440 && (i.tm.operand_types[op].bitfield.reg16
4441 || i.tm.operand_types[op].bitfield.acc))
252b5132 4442 {
29b0f896
AM		 4443 /* Prohibit these changes in the 64bit mode, since the
4444 lowering is more complicated. */
4445 if (flag_code == CODE_64BIT)
252b5132 4446 {
2ca3ace5
L		 4447 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4448 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4449 i.suffix);
4450 return 0;
252b5132 4451 }
29b0f896
AM		 4452 else
4453#if REGISTER_WARNINGS
a540244d
L		 4454 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4455 register_prefix,
29b0f896 4456 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4457 register_prefix,
29b0f896
AM		 4458 i.op[op].regs->reg_name,
4459 i.suffix);
4460#endif
4461 }
4462 return 1;
4463}
252b5132 4464
29b0f896 4465static int
40fb9820 4466update_imm (unsigned int j)
29b0f896 4467{
40fb9820
L		 4468 i386_operand_type overlap;
4469
c6fb90c8 4470 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4471 if ((overlap.bitfield.imm8
4472 || overlap.bitfield.imm8s
4473 || overlap.bitfield.imm16
4474 || overlap.bitfield.imm32
4475 || overlap.bitfield.imm32s
4476 || overlap.bitfield.imm64)
0dfbf9d7
L		 4477 && !operand_type_equal (&overlap, &imm8)
4478 && !operand_type_equal (&overlap, &imm8s)
4479 && !operand_type_equal (&overlap, &imm16)
4480 && !operand_type_equal (&overlap, &imm32)
4481 && !operand_type_equal (&overlap, &imm32s)
4482 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4483 {
4484 if (i.suffix)
4485 {
40fb9820
L		 4486 i386_operand_type temp;
4487
0dfbf9d7 4488 operand_type_set (&temp, 0);
40fb9820
L		 4489 if (i.suffix == BYTE_MNEM_SUFFIX)
4490 {
4491 temp.bitfield.imm8 = overlap.bitfield.imm8;
4492 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4493 }
4494 else if (i.suffix == WORD_MNEM_SUFFIX)
4495 temp.bitfield.imm16 = overlap.bitfield.imm16;
4496 else if (i.suffix == QWORD_MNEM_SUFFIX)
4497 {
4498 temp.bitfield.imm64 = overlap.bitfield.imm64;
4499 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4500 }
4501 else
4502 temp.bitfield.imm32 = overlap.bitfield.imm32;
4503 overlap = temp;
29b0f896 4504 }
0dfbf9d7
L		 4505 else if (operand_type_equal (&overlap, &imm16_32_32s)
4506 || operand_type_equal (&overlap, &imm16_32)
4507 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4508 {
40fb9820 4509 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4510 overlap = imm16;
40fb9820 4511 else
65da13b5 4512 overlap = imm32s;
29b0f896 4513 }
0dfbf9d7
L		 4514 if (!operand_type_equal (&overlap, &imm8)
4515 && !operand_type_equal (&overlap, &imm8s)
4516 && !operand_type_equal (&overlap, &imm16)
4517 && !operand_type_equal (&overlap, &imm32)
4518 && !operand_type_equal (&overlap, &imm32s)
4519 && !operand_type_equal (&overlap, &imm64))
29b0f896 4520 {
4eed87de
AM		 4521 as_bad (_("no instruction mnemonic suffix given; "
4522 "can't determine immediate size"));
29b0f896
AM		 4523 return 0;
4524 }
4525 }
40fb9820 4526 i.types[j] = overlap;
29b0f896 4527
40fb9820
L		 4528 return 1;
4529}
4530
4531static int
4532finalize_imm (void)
4533{
4534 unsigned int j;
29b0f896 4535
40fb9820
L		 4536 for (j = 0; j < 2; j++)
4537 if (update_imm (j) == 0)
4538 return 0;
4539
c6fb90c8 4540 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4541 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4542
4543 return 1;
4544}
4545
85f10a01
MM		 4546static void
4547process_drex (void)
4548{
5dd15031
JJ		 4549 i.drex.modrm_reg = 0;
4550 i.drex.modrm_regmem = 0;
85f10a01
MM		 4551
4552 /* SSE5 4 operand instructions must have the destination the same as
4553 one of the inputs. Figure out the destination register and cache
4554 it away in the drex field, and remember which fields to use for
4555 the modrm byte. */
4556 if (i.tm.opcode_modifier.drex
4557 && i.tm.opcode_modifier.drexv
4558 && i.operands == 4)
4559 {
4560 i.tm.extension_opcode = None;
4561
4562 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4563 if (i.types[0].bitfield.regxmm != 0
4564 && i.types[1].bitfield.regxmm != 0
4565 && i.types[2].bitfield.regxmm != 0
4566 && i.types[3].bitfield.regxmm != 0
4567 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4568 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4569 {
4570 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4571 operand_type_set (&i.types[0], 0);
4572 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4573 i.reg_operands -= 2;
4574
4575 /* There are two different ways to encode a 4 operand
4576 instruction with all registers that uses OC1 set to
4577 0 or 1. Favor setting OC1 to 0 since this mimics the
4578 actions of other SSE5 assemblers. Use modrm encoding 2
4579 for register/register. Include the high order bit that
4580 is normally stored in the REX byte in the register
4581 field. */
4582 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4583 i.drex.modrm_reg = 2;
4584 i.drex.modrm_regmem = 1;
4585 i.drex.reg = (i.op[3].regs->reg_num
4586 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4587 }
4588
4589 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4590 else if (i.types[0].bitfield.regxmm != 0
4591 && i.types[1].bitfield.regxmm != 0
4592 && (i.types[2].bitfield.regxmm
4593 || operand_type_check (i.types[2], anymem))
4594 && i.types[3].bitfield.regxmm != 0
4595 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4596 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4597 {
4598 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4599 operand_type_set (&i.types[0], 0);
4600 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4601 i.reg_operands -= 2;
4602
4603 /* Specify the modrm encoding for memory addressing. Include
4604 the high order bit that is normally stored in the REX byte
4605 in the register field. */
4606 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4607 i.drex.modrm_reg = 1;
4608 i.drex.modrm_regmem = 2;
4609 i.drex.reg = (i.op[3].regs->reg_num
4610 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4611 }
4612
4613 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4614 else if (i.types[0].bitfield.regxmm != 0
4615 && operand_type_check (i.types[1], anymem) != 0
4616 && i.types[2].bitfield.regxmm != 0
4617 && i.types[3].bitfield.regxmm != 0
4618 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4619 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4620 {
4621 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4622 operand_type_set (&i.types[0], 0);
4623 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4624 i.reg_operands -= 2;
4625
4626 /* Specify the modrm encoding for memory addressing. Include
4627 the high order bit that is normally stored in the REX byte
4628 in the register field. */
4629 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4630 i.drex.modrm_reg = 2;
4631 i.drex.modrm_regmem = 1;
4632 i.drex.reg = (i.op[3].regs->reg_num
4633 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4634 }
4635
4636 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4637 else if (i.types[0].bitfield.regxmm != 0
4638 && i.types[1].bitfield.regxmm != 0
4639 && i.types[2].bitfield.regxmm != 0
4640 && i.types[3].bitfield.regxmm != 0
4641 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4642 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4643 {
4644 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4645 operand_type_set (&i.types[2], 0);
4646 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4647 i.reg_operands -= 2;
4648
4649 /* There are two different ways to encode a 4 operand
4650 instruction with all registers that uses OC1 set to
4651 0 or 1. Favor setting OC1 to 0 since this mimics the
4652 actions of other SSE5 assemblers. Use modrm encoding
4653 2 for register/register. Include the high order bit that
4654 is normally stored in the REX byte in the register
4655 field. */
4656 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4657 i.drex.modrm_reg = 1;
4658 i.drex.modrm_regmem = 0;
4659
4660 /* Remember the register, including the upper bits */
4661 i.drex.reg = (i.op[3].regs->reg_num
4662 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4663 }
4664
4665 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4666 else if (i.types[0].bitfield.regxmm != 0
4667 && (i.types[1].bitfield.regxmm
4668 || operand_type_check (i.types[1], anymem))
4669 && i.types[2].bitfield.regxmm != 0
4670 && i.types[3].bitfield.regxmm != 0
4671 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4672 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4673 {
4674 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4675 operand_type_set (&i.types[2], 0);
4676 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4677 i.reg_operands -= 2;
4678
4679 /* Specify the modrm encoding and remember the register
4680 including the bits normally stored in the REX byte. */
4681 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4682 i.drex.modrm_reg = 0;
4683 i.drex.modrm_regmem = 1;
4684 i.drex.reg = (i.op[3].regs->reg_num
4685 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4686 }
4687
4688 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4689 else if (operand_type_check (i.types[0], anymem) != 0
4690 && i.types[1].bitfield.regxmm != 0
4691 && i.types[2].bitfield.regxmm != 0
4692 && i.types[3].bitfield.regxmm != 0
4693 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4694 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4695 {
4696 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4697 operand_type_set (&i.types[2], 0);
4698 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4699 i.reg_operands -= 2;
4700
4701 /* Specify the modrm encoding and remember the register
4702 including the bits normally stored in the REX byte. */
4703 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4704 i.drex.modrm_reg = 1;
4705 i.drex.modrm_regmem = 0;
4706 i.drex.reg = (i.op[3].regs->reg_num
4707 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4708 }
4709
4710 else
4711 as_bad (_("Incorrect operands for the '%s' instruction"),
4712 i.tm.name);
4713 }
4714
4715 /* SSE5 instructions with the DREX byte where the only memory operand
4716 is in the 2nd argument, and the first and last xmm register must
4717 match, and is encoded in the DREX byte. */
4718 else if (i.tm.opcode_modifier.drex
4719 && !i.tm.opcode_modifier.drexv
4720 && i.operands == 4)
4721 {
4722 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4723 if (i.types[0].bitfield.regxmm != 0
4724 && (i.types[1].bitfield.regxmm
4725 || operand_type_check(i.types[1], anymem))
4726 && i.types[2].bitfield.regxmm != 0
4727 && i.types[3].bitfield.regxmm != 0
4728 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4729 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4730 {
4731 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4732 operand_type_set (&i.types[0], 0);
4733 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4734 i.reg_operands -= 2;
4735
4736 /* Specify the modrm encoding and remember the register
4737 including the high bit normally stored in the REX
4738 byte. */
4739 i.drex.modrm_reg = 2;
4740 i.drex.modrm_regmem = 1;
4741 i.drex.reg = (i.op[3].regs->reg_num
4742 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4743 }
4744
4745 else
4746 as_bad (_("Incorrect operands for the '%s' instruction"),
4747 i.tm.name);
4748 }
4749
4750 /* SSE5 3 operand instructions that the result is a register, being
4751 either operand can be a memory operand, using OC0 to note which
4752 one is the memory. */
4753 else if (i.tm.opcode_modifier.drex
4754 && i.tm.opcode_modifier.drexv
4755 && i.operands == 3)
4756 {
4757 i.tm.extension_opcode = None;
4758
4759 /* Case 1: 3 operand insn, src1 = register. */
4760 if (i.types[0].bitfield.regxmm != 0
4761 && i.types[1].bitfield.regxmm != 0
4762 && i.types[2].bitfield.regxmm != 0)
4763 {
4764 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4765 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4766 i.reg_operands--;
4767
4768 /* Specify the modrm encoding and remember the register
4769 including the high bit normally stored in the REX byte. */
4770 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4771 i.drex.modrm_reg = 1;
4772 i.drex.modrm_regmem = 0;
4773 i.drex.reg = (i.op[2].regs->reg_num
4774 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4775 }
4776
4777 /* Case 2: 3 operand insn, src1 = memory. */
4778 else if (operand_type_check (i.types[0], anymem) != 0
4779 && i.types[1].bitfield.regxmm != 0
4780 && i.types[2].bitfield.regxmm != 0)
4781 {
4782 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4783 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4784 i.reg_operands--;
4785
4786 /* Specify the modrm encoding and remember the register
4787 including the high bit normally stored in the REX
4788 byte. */
4789 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4790 i.drex.modrm_reg = 1;
4791 i.drex.modrm_regmem = 0;
4792 i.drex.reg = (i.op[2].regs->reg_num
4793 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4794 }
4795
4796 /* Case 3: 3 operand insn, src2 = memory. */
4797 else if (i.types[0].bitfield.regxmm != 0
4798 && operand_type_check (i.types[1], anymem) != 0
4799 && i.types[2].bitfield.regxmm != 0)
4800 {
4801 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4802 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4803 i.reg_operands--;
4804
4805 /* Specify the modrm encoding and remember the register
4806 including the high bit normally stored in the REX byte. */
4807 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4808 i.drex.modrm_reg = 0;
4809 i.drex.modrm_regmem = 1;
4810 i.drex.reg = (i.op[2].regs->reg_num
4811 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4812 }
4813
4814 else
4815 as_bad (_("Incorrect operands for the '%s' instruction"),
4816 i.tm.name);
4817 }
4818
4819 /* SSE5 4 operand instructions that are the comparison instructions
4820 where the first operand is the immediate value of the comparison
4821 to be done. */
4822 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4823 {
4824 /* Case 1: 4 operand insn, src1 = reg/memory. */
4825 if (operand_type_check (i.types[0], imm) != 0
4826 && (i.types[1].bitfield.regxmm
4827 || operand_type_check (i.types[1], anymem))
4828 && i.types[2].bitfield.regxmm != 0
4829 && i.types[3].bitfield.regxmm != 0)
4830 {
4831 /* clear the arguments that are stored in drex */
0dfbf9d7 4832 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4833 i.reg_operands--;
4834
4835 /* Specify the modrm encoding and remember the register
4836 including the high bit normally stored in the REX byte. */
4837 i.drex.modrm_reg = 2;
4838 i.drex.modrm_regmem = 1;
4839 i.drex.reg = (i.op[3].regs->reg_num
4840 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4841 }
4842
4843 /* Case 2: 3 operand insn with ImmExt that places the
4844 opcode_extension as an immediate argument. This is used for
4845 all of the varients of comparison that supplies the appropriate
4846 value as part of the instruction. */
4847 else if ((i.types[0].bitfield.regxmm
4848 || operand_type_check (i.types[0], anymem))
4849 && i.types[1].bitfield.regxmm != 0
4850 && i.types[2].bitfield.regxmm != 0
4851 && operand_type_check (i.types[3], imm) != 0)
4852 {
4853 /* clear the arguments that are stored in drex */
0dfbf9d7 4854 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4855 i.reg_operands--;
4856
4857 /* Specify the modrm encoding and remember the register
4858 including the high bit normally stored in the REX byte. */
4859 i.drex.modrm_reg = 1;
4860 i.drex.modrm_regmem = 0;
4861 i.drex.reg = (i.op[2].regs->reg_num
4862 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4863 }
4864
4865 else
4866 as_bad (_("Incorrect operands for the '%s' instruction"),
4867 i.tm.name);
4868 }
4869
4870 else if (i.tm.opcode_modifier.drex
4871 || i.tm.opcode_modifier.drexv
4872 || i.tm.opcode_modifier.drexc)
4873 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4874}
4875
c0f3af97
L		 4876static int
4877bad_implicit_operand (int xmm)
4878{
4879 const char *reg = xmm ? "xmm0" : "ymm0";
4880 if (intel_syntax)
4881 as_bad (_("the last operand of `%s' must be `%s%s'"),
4882 i.tm.name, register_prefix, reg);
4883 else
4884 as_bad (_("the first operand of `%s' must be `%s%s'"),
4885 i.tm.name, register_prefix, reg);
4886 return 0;
4887}
4888
29b0f896 4889static int
e3bb37b5 4890process_operands (void)
29b0f896
AM		 4891{
4892 /* Default segment register this instruction will use for memory
4893 accesses. 0 means unknown. This is only for optimizing out
4894 unnecessary segment overrides. */
4895 const seg_entry *default_seg = 0;
4896
85f10a01
MM		 4897 /* Handle all of the DREX munging that SSE5 needs. */
4898 if (i.tm.opcode_modifier.drex
4899 || i.tm.opcode_modifier.drexv
4900 || i.tm.opcode_modifier.drexc)
4901 process_drex ();
4902
c0f3af97
L		 4903 if (i.tm.opcode_modifier.sse2avx
4904 && (i.tm.opcode_modifier.vexnds
4905 || i.tm.opcode_modifier.vexndd))
29b0f896 4906 {
c0f3af97
L		 4907 unsigned int dup = i.operands;
4908 unsigned int dest = dup - 1;
9fcfb3d7
L		 4909 unsigned int j;
4910
c0f3af97 4911 /* The destination must be an xmm register. */
0dfbf9d7 4912 assert (i.reg_operands
c0f3af97
L		 4913 && MAX_OPERANDS > dup
4914 && operand_type_equal (&i.types[dest], &regxmm));
4915
4916 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4917 {
c0f3af97
L		 4918 /* The first operand is implicit and must be xmm0. */
4919 assert (operand_type_equal (&i.types[0], &regxmm));
4920 if (i.op[0].regs->reg_num != 0)
4921 return bad_implicit_operand (1);
4922
4923 if (i.tm.opcode_modifier.vex3sources)
4924 {
4925 /* Keep xmm0 for instructions with VEX prefix and 3
4926 sources. */
4927 goto duplicate;
4928 }
e2ec9d29 4929 else
c0f3af97
L		 4930 {
4931 /* We remove the first xmm0 and keep the number of
4932 operands unchanged, which in fact duplicates the
4933 destination. */
4934 for (j = 1; j < i.operands; j++)
4935 {
4936 i.op[j - 1] = i.op[j];
4937 i.types[j - 1] = i.types[j];
4938 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4939 }
4940 }
4941 }
4942 else if (i.tm.opcode_modifier.implicit1stxmm0)
4943 {
4944 assert ((MAX_OPERANDS - 1) > dup
4945 && i.tm.opcode_modifier.vex3sources);
4946
4947 /* Add the implicit xmm0 for instructions with VEX prefix
4948 and 3 sources. */
4949 for (j = i.operands; j > 0; j--)
4950 {
4951 i.op[j] = i.op[j - 1];
4952 i.types[j] = i.types[j - 1];
4953 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4954 }
4955 i.op[0].regs
4956 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4957 i.types[0] = regxmm;
4958 i.tm.operand_types[0] = regxmm;
4959
4960 i.operands += 2;
4961 i.reg_operands += 2;
4962 i.tm.operands += 2;
4963
4964 dup++;
4965 dest++;
4966 i.op[dup] = i.op[dest];
4967 i.types[dup] = i.types[dest];
4968 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4969 }
c0f3af97
L		 4970 else
4971 {
4972duplicate:
4973 i.operands++;
4974 i.reg_operands++;
4975 i.tm.operands++;
4976
4977 i.op[dup] = i.op[dest];
4978 i.types[dup] = i.types[dest];
4979 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4980 }
4981
4982 if (i.tm.opcode_modifier.immext)
4983 process_immext ();
4984 }
4985 else if (i.tm.opcode_modifier.firstxmm0)
4986 {
4987 unsigned int j;
4988
4989 /* The first operand is implicit and must be xmm0/ymm0. */
4990 assert (i.reg_operands
4991 && (operand_type_equal (&i.types[0], &regxmm)
4992 || operand_type_equal (&i.types[0], &regymm)));
4993 if (i.op[0].regs->reg_num != 0)
4994 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4995
4996 for (j = 1; j < i.operands; j++)
4997 {
4998 i.op[j - 1] = i.op[j];
4999 i.types[j - 1] = i.types[j];
5000
5001 /* We need to adjust fields in i.tm since they are used by
5002 build_modrm_byte. */
5003 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5004 }
5005
e2ec9d29
L		 5006 i.operands--;
5007 i.reg_operands--;
e2ec9d29
L		 5008 i.tm.operands--;
5009 }
5010 else if (i.tm.opcode_modifier.regkludge)
5011 {
5012 /* The imul $imm, %reg instruction is converted into
5013 imul $imm, %reg, %reg, and the clr %reg instruction
5014 is converted into xor %reg, %reg. */
5015
5016 unsigned int first_reg_op;
5017
5018 if (operand_type_check (i.types[0], reg))
5019 first_reg_op = 0;
5020 else
5021 first_reg_op = 1;
5022 /* Pretend we saw the extra register operand. */
5023 assert (i.reg_operands == 1
5024 && i.op[first_reg_op + 1].regs == 0);
5025 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5026 i.types[first_reg_op + 1] = i.types[first_reg_op];
5027 i.operands++;
5028 i.reg_operands++;
29b0f896
AM		 5029 }
5030
40fb9820 5031 if (i.tm.opcode_modifier.shortform)
29b0f896 5032 {
40fb9820
L		 5033 if (i.types[0].bitfield.sreg2
5034 || i.types[0].bitfield.sreg3)
29b0f896 5035 {
4eed87de
AM		 5036 if (i.tm.base_opcode == POP_SEG_SHORT
5037 && i.op[0].regs->reg_num == 1)
29b0f896 5038 {
a87af027 5039 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5040 return 0;
29b0f896 5041 }
4eed87de
AM		 5042 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5043 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5044 i.rex |= REX_B;
4eed87de
AM		 5045 }
5046 else
5047 {
85f10a01
MM		 5048 /* The register or float register operand is in operand
5049 0 or 1. */
40fb9820
L		 5050 unsigned int op;
5051
5052 if (i.types[0].bitfield.floatreg
5053 || operand_type_check (i.types[0], reg))
5054 op = 0;
5055 else
5056 op = 1;
4eed87de
AM		 5057 /* Register goes in low 3 bits of opcode. */
5058 i.tm.base_opcode |= i.op[op].regs->reg_num;
5059 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5060 i.rex |= REX_B;
40fb9820 5061 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5062 {
4eed87de
AM		 5063 /* Warn about some common errors, but press on regardless.
5064 The first case can be generated by gcc (<= 2.8.1). */
5065 if (i.operands == 2)
5066 {
5067 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 5068 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5069 register_prefix, i.op[1].regs->reg_name,
5070 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 5071 }
5072 else
5073 {
5074 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5075 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5076 register_prefix, i.op[0].regs->reg_name);
4eed87de 5077 }
29b0f896
AM		 5078 }
5079 }
5080 }
40fb9820 5081 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5082 {
5083 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5084 must be put into the modrm byte). Now, we make the modrm and
5085 index base bytes based on all the info we've collected. */
29b0f896
AM		 5086
5087 default_seg = build_modrm_byte ();
5088 }
8a2ed489 5089 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5090 {
5091 default_seg = &ds;
5092 }
40fb9820 5093 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5094 {
5095 /* For the string instructions that allow a segment override
5096 on one of their operands, the default segment is ds. */
5097 default_seg = &ds;
5098 }
5099
75178d9d
L		 5100 if (i.tm.base_opcode == 0x8d /* lea */
5101 && i.seg[0]
5102 && !quiet_warnings)
30123838 5103 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5104
5105 /* If a segment was explicitly specified, and the specified segment
5106 is not the default, use an opcode prefix to select it. If we
5107 never figured out what the default segment is, then default_seg
5108 will be zero at this point, and the specified segment prefix will
5109 always be used. */
29b0f896
AM		 5110 if ((i.seg[0]) && (i.seg[0] != default_seg))
5111 {
5112 if (!add_prefix (i.seg[0]->seg_prefix))
5113 return 0;
5114 }
5115 return 1;
5116}
5117
5118static const seg_entry *
e3bb37b5 5119build_modrm_byte (void)
29b0f896
AM		 5120{
5121 const seg_entry *default_seg = 0;
c0f3af97
L		 5122 unsigned int source, dest;
5123 int vex_3_sources;
5124
5125 /* The first operand of instructions with VEX prefix and 3 sources
5126 must be VEX_Imm4. */
5127 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5128 if (vex_3_sources)
5129 {
5130 unsigned int nds, reg;
5131
0bfee649 5132 dest = i.operands - 1;
c0f3af97 5133 nds = dest - 1;
0bfee649
L		 5134 source = 1;
5135 reg = 0;
5136
5137 /* This instruction must have 4 operands: 4 register operands
5138 or 3 register operands plus 1 memory operand. It must have
5139 VexNDS and VexImmExt. */
5140 assert (i.operands == 4
5141 && (i.reg_operands == 4
5142 || (i.reg_operands == 3 && i.mem_operands == 1))
5143 && i.tm.opcode_modifier.vexnds
5144 && i.tm.opcode_modifier.veximmext
5145 && (operand_type_equal (&i.tm.operand_types[dest],
5146 &regxmm)
5147 || operand_type_equal (&i.tm.operand_types[dest],
5148 &regymm))
5149 && (operand_type_equal (&i.tm.operand_types[nds],
5150 &regxmm)
5151 || operand_type_equal (&i.tm.operand_types[nds],
5152 &regymm))
5153 && (operand_type_equal (&i.tm.operand_types[reg],
5154 &regxmm)
c0f3af97 5155 || operand_type_equal (&i.tm.operand_types[reg],
0bfee649 5156 &regymm)));
c0f3af97 5157
0bfee649
L		 5158 /* Generate an 8bit immediate operand to encode the register
5159 operand. */
5160 expressionS *exp = &im_expressions[i.imm_operands++];
5161 i.op[i.operands].imms = exp;
5162 i.types[i.operands] = imm8;
5163 i.operands++;
5164 exp->X_op = O_constant;
5165 exp->X_add_number
5166 = ((i.op[0].regs->reg_num
5167 + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 5168
dae39acc 5169 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5170 }
5171 else
5172 source = dest = 0;
29b0f896 5173
85f10a01
MM		 5174 /* SSE5 4 operand instructions are encoded in such a way that one of
5175 the inputs must match the destination register. Process_drex hides
5176 the 3rd argument in the drex field, so that by the time we get
5177 here, it looks to GAS as if this is a 2 operand instruction. */
5178 if ((i.tm.opcode_modifier.drex
5179 || i.tm.opcode_modifier.drexv
b5016f89 5180 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5181 && i.reg_operands == 2)
5182 {
5183 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5184 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5185
5186 i.rm.reg = reg->reg_num;
5187 i.rm.regmem = regmem->reg_num;
5188 i.rm.mode = 3;
5189 if ((reg->reg_flags & RegRex) != 0)
5190 i.rex |= REX_R;
5191 if ((regmem->reg_flags & RegRex) != 0)
5192 i.rex |= REX_B;
5193 }
5194
29b0f896 5195 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5196 implicit registers do not count. If there are 3 register
5197 operands, it must be a instruction with VexNDS. For a
5198 instruction with VexNDD, the destination register is encoded
5199 in VEX prefix. If there are 4 register operands, it must be
5200 a instruction with VEX prefix and 3 sources. */
5201 else if (i.mem_operands == 0
5202 && ((i.reg_operands == 2
5203 && !i.tm.opcode_modifier.vexndd)
5204 || (i.reg_operands == 3
5205 && i.tm.opcode_modifier.vexnds)
5206 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5207 {
cab737b9
L		 5208 switch (i.operands)
5209 {
5210 case 2:
5211 source = 0;
5212 break;
5213 case 3:
c81128dc
L		 5214 /* When there are 3 operands, one of them may be immediate,
5215 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5216 the first operand must be shift count register (cl) or it
5217 is an instruction with VexNDS. */
c81128dc
L		 5218 assert (i.imm_operands == 1
5219 || (i.imm_operands == 0
c0f3af97
L		 5220 && (i.tm.opcode_modifier.vexnds
5221 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5222 if (operand_type_check (i.types[0], imm)
5223 || i.types[0].bitfield.shiftcount)
5224 source = 1;
5225 else
5226 source = 0;
cab737b9
L		 5227 break;
5228 case 4:
368d64cc
L		 5229 /* When there are 4 operands, the first two must be 8bit
5230 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5231 one.
5232
5233 For instructions with VexNDS, if the first operand
5234 an imm8, the source operand is the 2nd one. If the last
5235 operand is imm8, the source operand is the first one. */
5236 assert ((i.imm_operands == 2
5237 && i.types[0].bitfield.imm8
5238 && i.types[1].bitfield.imm8)
5239 || (i.tm.opcode_modifier.vexnds
5240 && i.imm_operands == 1
5241 && (i.types[0].bitfield.imm8
5242 || i.types[i.operands - 1].bitfield.imm8)));
5243 if (i.tm.opcode_modifier.vexnds)
5244 {
5245 if (i.types[0].bitfield.imm8)
5246 source = 1;
5247 else
5248 source = 0;
5249 }
5250 else
5251 source = 2;
5252 break;
5253 case 5:
cab737b9
L		 5254 break;
5255 default:
5256 abort ();
5257 }
5258
c0f3af97
L		 5259 if (!vex_3_sources)
5260 {
5261 dest = source + 1;
5262
5263 if (i.tm.opcode_modifier.vexnds)
5264 {
5265 /* For instructions with VexNDS, the register-only
5266 source operand must be XMM or YMM register. It is
fa99fab2
L		 5267 encoded in VEX prefix. We need to clear RegMem bit
5268 before calling operand_type_equal. */
5269 i386_operand_type op = i.tm.operand_types[dest];
5270 op.bitfield.regmem = 0;
c0f3af97 5271 if ((dest + 1) >= i.operands
fa99fab2
L		 5272 || (!operand_type_equal (&op, &regxmm)
5273 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5274 abort ();
5275 i.vex.register_specifier = i.op[dest].regs;
5276 dest++;
5277 }
5278 }
29b0f896
AM		 5279
5280 i.rm.mode = 3;
5281 /* One of the register operands will be encoded in the i.tm.reg
5282 field, the other in the combined i.tm.mode and i.tm.regmem
5283 fields. If no form of this instruction supports a memory
5284 destination operand, then we assume the source operand may
5285 sometimes be a memory operand and so we need to store the
5286 destination in the i.rm.reg field. */
40fb9820
L		 5287 if (!i.tm.operand_types[dest].bitfield.regmem
5288 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5289 {
5290 i.rm.reg = i.op[dest].regs->reg_num;
5291 i.rm.regmem = i.op[source].regs->reg_num;
5292 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5293 i.rex |= REX_R;
29b0f896 5294 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5295 i.rex |= REX_B;
29b0f896
AM		 5296 }
5297 else
5298 {
5299 i.rm.reg = i.op[source].regs->reg_num;
5300 i.rm.regmem = i.op[dest].regs->reg_num;
5301 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5302 i.rex |= REX_B;
29b0f896 5303 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5304 i.rex |= REX_R;
29b0f896 5305 }
161a04f6 5306 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5307 {
40fb9820
L		 5308 if (!i.types[0].bitfield.control
5309 && !i.types[1].bitfield.control)
c4a530c5 5310 abort ();
161a04f6 5311 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5312 add_prefix (LOCK_PREFIX_OPCODE);
5313 }
29b0f896
AM		 5314 }
5315 else
5316 { /* If it's not 2 reg operands... */
c0f3af97
L		 5317 unsigned int mem;
5318
29b0f896
AM		 5319 if (i.mem_operands)
5320 {
5321 unsigned int fake_zero_displacement = 0;
99018f42 5322 unsigned int op;
4eed87de 5323
85f10a01
MM		 5324 /* This has been precalculated for SSE5 instructions
5325 that have a DREX field earlier in process_drex. */
b5016f89
L		 5326 if (i.tm.opcode_modifier.drex
5327 || i.tm.opcode_modifier.drexv
5328 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5329 op = i.drex.modrm_regmem;
5330 else
5331 {
c0209578
L		 5332 for (op = 0; op < i.operands; op++)
5333 if (operand_type_check (i.types[op], anymem))
5334 break;
5335 assert (op < i.operands);
85f10a01 5336 }
29b0f896
AM		 5337
5338 default_seg = &ds;
5339
5340 if (i.base_reg == 0)
5341 {
5342 i.rm.mode = 0;
5343 if (!i.disp_operands)
5344 fake_zero_displacement = 1;
5345 if (i.index_reg == 0)
5346 {
5347 /* Operand is just <disp> */
20f0a1fc 5348 if (flag_code == CODE_64BIT)
29b0f896
AM		 5349 {
5350 /* 64bit mode overwrites the 32bit absolute
5351 addressing by RIP relative addressing and
5352 absolute addressing is encoded by one of the
5353 redundant SIB forms. */
5354 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5355 i.sib.base = NO_BASE_REGISTER;
5356 i.sib.index = NO_INDEX_REGISTER;
fc225355 5357 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5358 ? disp32s : disp32);
20f0a1fc 5359 }
fc225355
L		 5360 else if ((flag_code == CODE_16BIT)
5361 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5362 {
5363 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5364 i.types[op] = disp16;
20f0a1fc
NC		 5365 }
5366 else
5367 {
5368 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5369 i.types[op] = disp32;
29b0f896
AM		 5370 }
5371 }
5372 else /* !i.base_reg && i.index_reg */
5373 {
db51cc60
L		 5374 if (i.index_reg->reg_num == RegEiz
5375 || i.index_reg->reg_num == RegRiz)
5376 i.sib.index = NO_INDEX_REGISTER;
5377 else
5378 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5379 i.sib.base = NO_BASE_REGISTER;
5380 i.sib.scale = i.log2_scale_factor;
5381 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5382 i.types[op].bitfield.disp8 = 0;
5383 i.types[op].bitfield.disp16 = 0;
5384 i.types[op].bitfield.disp64 = 0;
29b0f896 5385 if (flag_code != CODE_64BIT)
40fb9820
L		 5386 {
5387 /* Must be 32 bit */
5388 i.types[op].bitfield.disp32 = 1;
5389 i.types[op].bitfield.disp32s = 0;
5390 }
29b0f896 5391 else
40fb9820
L		 5392 {
5393 i.types[op].bitfield.disp32 = 0;
5394 i.types[op].bitfield.disp32s = 1;
5395 }
29b0f896 5396 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5397 i.rex |= REX_X;
29b0f896
AM		 5398 }
5399 }
5400 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5401 else if (i.base_reg->reg_num == RegRip ||
5402 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5403 {
5404 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5405 i.types[op].bitfield.disp8 = 0;
5406 i.types[op].bitfield.disp16 = 0;
5407 i.types[op].bitfield.disp32 = 0;
5408 i.types[op].bitfield.disp32s = 1;
5409 i.types[op].bitfield.disp64 = 0;
71903a11 5410 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5411 if (! i.disp_operands)
5412 fake_zero_displacement = 1;
29b0f896 5413 }
40fb9820 5414 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5415 {
5416 switch (i.base_reg->reg_num)
5417 {
5418 case 3: /* (%bx) */
5419 if (i.index_reg == 0)
5420 i.rm.regmem = 7;
5421 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5422 i.rm.regmem = i.index_reg->reg_num - 6;
5423 break;
5424 case 5: /* (%bp) */
5425 default_seg = &ss;
5426 if (i.index_reg == 0)
5427 {
5428 i.rm.regmem = 6;
40fb9820 5429 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5430 {
5431 /* fake (%bp) into 0(%bp) */
40fb9820 5432 i.types[op].bitfield.disp8 = 1;
252b5132 5433 fake_zero_displacement = 1;
29b0f896
AM		 5434 }
5435 }
5436 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5437 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5438 break;
5439 default: /* (%si) -> 4 or (%di) -> 5 */
5440 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5441 }
5442 i.rm.mode = mode_from_disp_size (i.types[op]);
5443 }
5444 else /* i.base_reg and 32/64 bit mode */
5445 {
5446 if (flag_code == CODE_64BIT
40fb9820
L		 5447 && operand_type_check (i.types[op], disp))
5448 {
5449 i386_operand_type temp;
0dfbf9d7 5450 operand_type_set (&temp, 0);
40fb9820
L		 5451 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5452 i.types[op] = temp;
5453 if (i.prefix[ADDR_PREFIX] == 0)
5454 i.types[op].bitfield.disp32s = 1;
5455 else
5456 i.types[op].bitfield.disp32 = 1;
5457 }
20f0a1fc 5458
29b0f896
AM		 5459 i.rm.regmem = i.base_reg->reg_num;
5460 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5461 i.rex |= REX_B;
29b0f896
AM		 5462 i.sib.base = i.base_reg->reg_num;
5463 /* x86-64 ignores REX prefix bit here to avoid decoder
5464 complications. */
5465 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5466 {
5467 default_seg = &ss;
5468 if (i.disp_operands == 0)
5469 {
5470 fake_zero_displacement = 1;
40fb9820 5471 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5472 }
5473 }
5474 else if (i.base_reg->reg_num == ESP_REG_NUM)
5475 {
5476 default_seg = &ss;
5477 }
5478 i.sib.scale = i.log2_scale_factor;
5479 if (i.index_reg == 0)
5480 {
5481 /* <disp>(%esp) becomes two byte modrm with no index
5482 register. We've already stored the code for esp
5483 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5484 Any base register besides %esp will not use the
5485 extra modrm byte. */
5486 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5487 }
5488 else
5489 {
db51cc60
L		 5490 if (i.index_reg->reg_num == RegEiz
5491 || i.index_reg->reg_num == RegRiz)
5492 i.sib.index = NO_INDEX_REGISTER;
5493 else
5494 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5495 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5496 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5497 i.rex |= REX_X;
29b0f896 5498 }
67a4f2b7
AO		 5499
5500 if (i.disp_operands
5501 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5502 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5503 i.rm.mode = 0;
5504 else
5505 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5506 }
252b5132 5507
29b0f896
AM		 5508 if (fake_zero_displacement)
5509 {
5510 /* Fakes a zero displacement assuming that i.types[op]
5511 holds the correct displacement size. */
5512 expressionS *exp;
5513
5514 assert (i.op[op].disps == 0);
5515 exp = &disp_expressions[i.disp_operands++];
5516 i.op[op].disps = exp;
5517 exp->X_op = O_constant;
5518 exp->X_add_number = 0;
5519 exp->X_add_symbol = (symbolS *) 0;
5520 exp->X_op_symbol = (symbolS *) 0;
5521 }
c0f3af97
L		 5522
5523 mem = op;
29b0f896 5524 }
c0f3af97
L		 5525 else
5526 mem = ~0;
252b5132 5527
29b0f896
AM		 5528 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5529 (if any) based on i.tm.extension_opcode. Again, we must be
5530 careful to make sure that segment/control/debug/test/MMX
5531 registers are coded into the i.rm.reg field. */
5532 if (i.reg_operands)
5533 {
99018f42
L		 5534 unsigned int op;
5535
85f10a01
MM		 5536 /* This has been precalculated for SSE5 instructions
5537 that have a DREX field earlier in process_drex. */
b5016f89
L		 5538 if (i.tm.opcode_modifier.drex
5539 || i.tm.opcode_modifier.drexv
5540 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5541 {
5542 op = i.drex.modrm_reg;
5543 i.rm.reg = i.op[op].regs->reg_num;
5544 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5545 i.rex |= REX_R;
5546 }
5547 else
5548 {
c0f3af97
L		 5549 unsigned int vex_reg = ~0;
5550
c0209578
L		 5551 for (op = 0; op < i.operands; op++)
5552 if (i.types[op].bitfield.reg8
5553 || i.types[op].bitfield.reg16
5554 || i.types[op].bitfield.reg32
5555 || i.types[op].bitfield.reg64
5556 || i.types[op].bitfield.regmmx
5557 || i.types[op].bitfield.regxmm
c0f3af97 5558 || i.types[op].bitfield.regymm
c0209578
L		 5559 || i.types[op].bitfield.sreg2
5560 || i.types[op].bitfield.sreg3
5561 || i.types[op].bitfield.control
5562 || i.types[op].bitfield.debug
5563 || i.types[op].bitfield.test)
5564 break;
5565
c0f3af97
L		 5566 if (vex_3_sources)
5567 op = dest;
5568 else if (i.tm.opcode_modifier.vexnds)
5569 {
5570 /* For instructions with VexNDS, the register-only
5571 source operand is encoded in VEX prefix. */
5572 assert (mem != (unsigned int) ~0);
5573
5574 if (op > mem)
5575 {
5576 vex_reg = op++;
5577 assert (op < i.operands);
5578 }
5579 else
5580 {
5581 vex_reg = op + 1;
5582 assert (vex_reg < i.operands);
5583 }
5584 }
5585 else if (i.tm.opcode_modifier.vexndd)
5586 {
5587 /* For instructions with VexNDD, there should be
5588 no memory operand and the register destination
5589 is encoded in VEX prefix. */
5590 assert (i.mem_operands == 0
5591 && (op + 2) == i.operands);
5592 vex_reg = op + 1;
5593 }
5594 else
5595 assert (op < i.operands);
5596
5597 if (vex_reg != (unsigned int) ~0)
5598 {
5599 assert (i.reg_operands == 2);
5600
5601 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5602 & regxmm)
5603 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5604 &regymm))
5605 abort ();
5606 i.vex.register_specifier = i.op[vex_reg].regs;
5607 }
99018f42 5608
85f10a01
MM		 5609 /* If there is an extension opcode to put here, the
5610 register number must be put into the regmem field. */
c0209578
L		 5611 if (i.tm.extension_opcode != None)
5612 {
5613 i.rm.regmem = i.op[op].regs->reg_num;
5614 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5615 i.rex |= REX_B;
5616 }
5617 else
5618 {
5619 i.rm.reg = i.op[op].regs->reg_num;
5620 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5621 i.rex |= REX_R;
5622 }
85f10a01 5623 }
252b5132 5624
29b0f896
AM		 5625 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5626 must set it to 3 to indicate this is a register operand
5627 in the regmem field. */
5628 if (!i.mem_operands)
5629 i.rm.mode = 3;
5630 }
252b5132 5631
29b0f896 5632 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5633 if (i.tm.extension_opcode != None
5634 && !(i.tm.opcode_modifier.drex
5635 || i.tm.opcode_modifier.drexv
5636 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5637 i.rm.reg = i.tm.extension_opcode;
5638 }
5639 return default_seg;
5640}
252b5132 5641
29b0f896 5642static void
e3bb37b5 5643output_branch (void)
29b0f896
AM		 5644{
5645 char *p;
5646 int code16;
5647 int prefix;
5648 relax_substateT subtype;
5649 symbolS *sym;
5650 offsetT off;
5651
5652 code16 = 0;
5653 if (flag_code == CODE_16BIT)
5654 code16 = CODE16;
5655
5656 prefix = 0;
5657 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5658 {
29b0f896
AM		 5659 prefix = 1;
5660 i.prefixes -= 1;
5661 code16 ^= CODE16;
252b5132 5662 }
29b0f896
AM		 5663 /* Pentium4 branch hints. */
5664 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5665 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5666 {
29b0f896
AM		 5667 prefix++;
5668 i.prefixes--;
5669 }
5670 if (i.prefix[REX_PREFIX] != 0)
5671 {
5672 prefix++;
5673 i.prefixes--;
2f66722d
AM		 5674 }
5675
29b0f896
AM		 5676 if (i.prefixes != 0 && !intel_syntax)
5677 as_warn (_("skipping prefixes on this instruction"));
5678
5679 /* It's always a symbol; End frag & setup for relax.
5680 Make sure there is enough room in this frag for the largest
5681 instruction we may generate in md_convert_frag. This is 2
5682 bytes for the opcode and room for the prefix and largest
5683 displacement. */
5684 frag_grow (prefix + 2 + 4);
5685 /* Prefix and 1 opcode byte go in fr_fix. */
5686 p = frag_more (prefix + 1);
5687 if (i.prefix[DATA_PREFIX] != 0)
5688 *p++ = DATA_PREFIX_OPCODE;
5689 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5690 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5691 *p++ = i.prefix[SEG_PREFIX];
5692 if (i.prefix[REX_PREFIX] != 0)
5693 *p++ = i.prefix[REX_PREFIX];
5694 *p = i.tm.base_opcode;
5695
5696 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5697 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5698 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5699 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5700 else
5701 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5702 subtype |= code16;
3e73aa7c 5703
29b0f896
AM		 5704 sym = i.op[0].disps->X_add_symbol;
5705 off = i.op[0].disps->X_add_number;
3e73aa7c 5706
29b0f896
AM		 5707 if (i.op[0].disps->X_op != O_constant
5708 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5709 {
29b0f896
AM		 5710 /* Handle complex expressions. */
5711 sym = make_expr_symbol (i.op[0].disps);
5712 off = 0;
5713 }
3e73aa7c 5714
29b0f896
AM		 5715 /* 1 possible extra opcode + 4 byte displacement go in var part.
5716 Pass reloc in fr_var. */
5717 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5718}
3e73aa7c 5719
29b0f896 5720static void
e3bb37b5 5721output_jump (void)
29b0f896
AM		 5722{
5723 char *p;
5724 int size;
3e02c1cc 5725 fixS *fixP;
29b0f896 5726
40fb9820 5727 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5728 {
5729 /* This is a loop or jecxz type instruction. */
5730 size = 1;
5731 if (i.prefix[ADDR_PREFIX] != 0)
5732 {
5733 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5734 i.prefixes -= 1;
5735 }
5736 /* Pentium4 branch hints. */
5737 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5738 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5739 {
5740 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5741 i.prefixes--;
3e73aa7c
JH		 5742 }
5743 }
29b0f896
AM		 5744 else
5745 {
5746 int code16;
3e73aa7c 5747
29b0f896
AM		 5748 code16 = 0;
5749 if (flag_code == CODE_16BIT)
5750 code16 = CODE16;
3e73aa7c 5751
29b0f896
AM		 5752 if (i.prefix[DATA_PREFIX] != 0)
5753 {
5754 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5755 i.prefixes -= 1;
5756 code16 ^= CODE16;
5757 }
252b5132 5758
29b0f896
AM		 5759 size = 4;
5760 if (code16)
5761 size = 2;
5762 }
9fcc94b6 5763
29b0f896
AM		 5764 if (i.prefix[REX_PREFIX] != 0)
5765 {
5766 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5767 i.prefixes -= 1;
5768 }
252b5132 5769
29b0f896
AM		 5770 if (i.prefixes != 0 && !intel_syntax)
5771 as_warn (_("skipping prefixes on this instruction"));
e0890092 5772
29b0f896
AM		 5773 p = frag_more (1 + size);
5774 *p++ = i.tm.base_opcode;
e0890092 5775
3e02c1cc
AM		 5776 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5777 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5778
5779 /* All jumps handled here are signed, but don't use a signed limit
5780 check for 32 and 16 bit jumps as we want to allow wrap around at
5781 4G and 64k respectively. */
5782 if (size == 1)
5783 fixP->fx_signed = 1;
29b0f896 5784}
e0890092 5785
29b0f896 5786static void
e3bb37b5 5787output_interseg_jump (void)
29b0f896
AM		 5788{
5789 char *p;
5790 int size;
5791 int prefix;
5792 int code16;
252b5132 5793
29b0f896
AM		 5794 code16 = 0;
5795 if (flag_code == CODE_16BIT)
5796 code16 = CODE16;
a217f122 5797
29b0f896
AM		 5798 prefix = 0;
5799 if (i.prefix[DATA_PREFIX] != 0)
5800 {
5801 prefix = 1;
5802 i.prefixes -= 1;
5803 code16 ^= CODE16;
5804 }
5805 if (i.prefix[REX_PREFIX] != 0)
5806 {
5807 prefix++;
5808 i.prefixes -= 1;
5809 }
252b5132 5810
29b0f896
AM		 5811 size = 4;
5812 if (code16)
5813 size = 2;
252b5132 5814
29b0f896
AM		 5815 if (i.prefixes != 0 && !intel_syntax)
5816 as_warn (_("skipping prefixes on this instruction"));
252b5132 5817
29b0f896
AM		 5818 /* 1 opcode; 2 segment; offset */
5819 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5820
29b0f896
AM		 5821 if (i.prefix[DATA_PREFIX] != 0)
5822 *p++ = DATA_PREFIX_OPCODE;
252b5132 5823
29b0f896
AM		 5824 if (i.prefix[REX_PREFIX] != 0)
5825 *p++ = i.prefix[REX_PREFIX];
252b5132 5826
29b0f896
AM		 5827 *p++ = i.tm.base_opcode;
5828 if (i.op[1].imms->X_op == O_constant)
5829 {
5830 offsetT n = i.op[1].imms->X_add_number;
252b5132 5831
29b0f896
AM		 5832 if (size == 2
5833 && !fits_in_unsigned_word (n)
5834 && !fits_in_signed_word (n))
5835 {
5836 as_bad (_("16-bit jump out of range"));
5837 return;
5838 }
5839 md_number_to_chars (p, n, size);
5840 }
5841 else
5842 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5843 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5844 if (i.op[0].imms->X_op != O_constant)
5845 as_bad (_("can't handle non absolute segment in `%s'"),
5846 i.tm.name);
5847 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5848}
a217f122 5849
29b0f896 5850static void
e3bb37b5 5851output_insn (void)
29b0f896 5852{
2bbd9c25
JJ		 5853 fragS *insn_start_frag;
5854 offsetT insn_start_off;
5855
29b0f896
AM		 5856 /* Tie dwarf2 debug info to the address at the start of the insn.
5857 We can't do this after the insn has been output as the current
5858 frag may have been closed off. eg. by frag_var. */
5859 dwarf2_emit_insn (0);
5860
2bbd9c25
JJ		 5861 insn_start_frag = frag_now;
5862 insn_start_off = frag_now_fix ();
5863
29b0f896 5864 /* Output jumps. */
40fb9820 5865 if (i.tm.opcode_modifier.jump)
29b0f896 5866 output_branch ();
40fb9820
L		 5867 else if (i.tm.opcode_modifier.jumpbyte
5868 || i.tm.opcode_modifier.jumpdword)
29b0f896 5869 output_jump ();
40fb9820 5870 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5871 output_interseg_jump ();
5872 else
5873 {
5874 /* Output normal instructions here. */
5875 char *p;
5876 unsigned char *q;
47465058 5877 unsigned int j;
331d2d0d 5878 unsigned int prefix;
4dffcebc 5879
c0f3af97
L		 5880 /* Since the VEX prefix contains the implicit prefix, we don't
5881 need the explicit prefix. */
5882 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5883 {
c0f3af97 5884 switch (i.tm.opcode_length)
bc4bd9ab 5885 {
c0f3af97
L		 5886 case 3:
5887 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5888 {
c0f3af97
L		 5889 prefix = (i.tm.base_opcode >> 24) & 0xff;
5890 goto check_prefix;
5891 }
5892 break;
5893 case 2:
5894 if ((i.tm.base_opcode & 0xff0000) != 0)
5895 {
5896 prefix = (i.tm.base_opcode >> 16) & 0xff;
5897 if (i.tm.cpu_flags.bitfield.cpupadlock)
5898 {
4dffcebc 5899check_prefix:
c0f3af97
L		 5900 if (prefix != REPE_PREFIX_OPCODE
5901 || (i.prefix[LOCKREP_PREFIX]
5902 != REPE_PREFIX_OPCODE))
5903 add_prefix (prefix);
5904 }
5905 else
4dffcebc
L		 5906 add_prefix (prefix);
5907 }
c0f3af97
L		 5908 break;
5909 case 1:
5910 break;
5911 default:
5912 abort ();
bc4bd9ab 5913 }
c0f3af97
L		 5914
5915 /* The prefix bytes. */
5916 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5917 if (*q)
5918 FRAG_APPEND_1_CHAR (*q);
0f10071e 5919 }
252b5132 5920
c0f3af97
L		 5921 if (i.tm.opcode_modifier.vex)
5922 {
5923 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5924 if (*q)
5925 switch (j)
5926 {
5927 case REX_PREFIX:
5928 /* REX byte is encoded in VEX prefix. */
5929 break;
5930 case SEG_PREFIX:
5931 case ADDR_PREFIX:
5932 FRAG_APPEND_1_CHAR (*q);
5933 break;
5934 default:
5935 /* There should be no other prefixes for instructions
5936 with VEX prefix. */
5937 abort ();
5938 }
5939
5940 /* Now the VEX prefix. */
5941 p = frag_more (i.vex.length);
5942 for (j = 0; j < i.vex.length; j++)
5943 p[j] = i.vex.bytes[j];
5944 }
252b5132 5945
29b0f896 5946 /* Now the opcode; be careful about word order here! */
4dffcebc 5947 if (i.tm.opcode_length == 1)
29b0f896
AM		 5948 {
5949 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5950 }
5951 else
5952 {
4dffcebc 5953 switch (i.tm.opcode_length)
331d2d0d 5954 {
4dffcebc 5955 case 3:
331d2d0d
L		 5956 p = frag_more (3);
5957 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5958 break;
5959 case 2:
5960 p = frag_more (2);
5961 break;
5962 default:
5963 abort ();
5964 break;
331d2d0d 5965 }
0f10071e 5966
29b0f896
AM		 5967 /* Put out high byte first: can't use md_number_to_chars! */
5968 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5969 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5970
5971 /* On SSE5, encode the OC1 bit in the DREX field if this
5972 encoding has multiple formats. */
5973 if (i.tm.opcode_modifier.drex
5974 && i.tm.opcode_modifier.drexv
5975 && DREX_OC1 (i.tm.extension_opcode))
5976 *p |= DREX_OC1_MASK;
29b0f896 5977 }
3e73aa7c 5978
29b0f896 5979 /* Now the modrm byte and sib byte (if present). */
40fb9820 5980 if (i.tm.opcode_modifier.modrm)
29b0f896 5981 {
4a3523fa
L		 5982 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5983 | i.rm.reg << 3
5984 | i.rm.mode << 6));
29b0f896
AM		 5985 /* If i.rm.regmem == ESP (4)
5986 && i.rm.mode != (Register mode)
5987 && not 16 bit
5988 ==> need second modrm byte. */
5989 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5990 && i.rm.mode != 3
40fb9820 5991 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5992 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5993 | i.sib.index << 3
5994 | i.sib.scale << 6));
29b0f896 5995 }
3e73aa7c 5996
85f10a01
MM		 5997 /* Write the DREX byte if needed. */
5998 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5999 {
6000 p = frag_more (1);
6001 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
6002
6003 /* Encode the OC0 bit if this encoding has multiple
6004 formats. */
6005 if ((i.tm.opcode_modifier.drex
6006 || i.tm.opcode_modifier.drexv)
6007 && DREX_OC0 (i.tm.extension_opcode))
6008 *p |= DREX_OC0_MASK;
6009 }
6010
29b0f896 6011 if (i.disp_operands)
2bbd9c25 6012 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6013
29b0f896 6014 if (i.imm_operands)
2bbd9c25 6015 output_imm (insn_start_frag, insn_start_off);
29b0f896 6016 }
252b5132 6017
29b0f896
AM		 6018#ifdef DEBUG386
6019 if (flag_debug)
6020 {
7b81dfbb 6021 pi ("" /*line*/, &i);
29b0f896
AM		 6022 }
6023#endif /* DEBUG386 */
6024}
252b5132 6025
e205caa7
L		 6026/* Return the size of the displacement operand N. */
6027
6028static int
6029disp_size (unsigned int n)
6030{
6031 int size = 4;
40fb9820
L		 6032 if (i.types[n].bitfield.disp64)
6033 size = 8;
6034 else if (i.types[n].bitfield.disp8)
6035 size = 1;
6036 else if (i.types[n].bitfield.disp16)
6037 size = 2;
e205caa7
L		 6038 return size;
6039}
6040
6041/* Return the size of the immediate operand N. */
6042
6043static int
6044imm_size (unsigned int n)
6045{
6046 int size = 4;
40fb9820
L		 6047 if (i.types[n].bitfield.imm64)
6048 size = 8;
6049 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6050 size = 1;
6051 else if (i.types[n].bitfield.imm16)
6052 size = 2;
e205caa7
L		 6053 return size;
6054}
6055
29b0f896 6056static void
64e74474 6057output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6058{
6059 char *p;
6060 unsigned int n;
252b5132 6061
29b0f896
AM		 6062 for (n = 0; n < i.operands; n++)
6063 {
40fb9820 6064 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6065 {
6066 if (i.op[n].disps->X_op == O_constant)
6067 {
e205caa7 6068 int size = disp_size (n);
29b0f896 6069 offsetT val;
252b5132 6070
29b0f896
AM		 6071 val = offset_in_range (i.op[n].disps->X_add_number,
6072 size);
6073 p = frag_more (size);
6074 md_number_to_chars (p, val, size);
6075 }
6076 else
6077 {
f86103b7 6078 enum bfd_reloc_code_real reloc_type;
e205caa7 6079 int size = disp_size (n);
40fb9820 6080 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6081 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6082
e205caa7 6083 /* We can't have 8 bit displacement here. */
40fb9820 6084 assert (!i.types[n].bitfield.disp8);
e205caa7 6085
29b0f896
AM		 6086 /* The PC relative address is computed relative
6087 to the instruction boundary, so in case immediate
6088 fields follows, we need to adjust the value. */
6089 if (pcrel && i.imm_operands)
6090 {
29b0f896 6091 unsigned int n1;
e205caa7 6092 int sz = 0;
252b5132 6093
29b0f896 6094 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6095 if (operand_type_check (i.types[n1], imm))
252b5132 6096 {
e205caa7
L		 6097 /* Only one immediate is allowed for PC
6098 relative address. */
6099 assert (sz == 0);
6100 sz = imm_size (n1);
6101 i.op[n].disps->X_add_number -= sz;
252b5132 6102 }
29b0f896 6103 /* We should find the immediate. */
e205caa7 6104 assert (sz != 0);
29b0f896 6105 }
520dc8e8 6106
29b0f896 6107 p = frag_more (size);
2bbd9c25 6108 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6109 if (GOT_symbol
2bbd9c25 6110 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6111 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6112 || reloc_type == BFD_RELOC_X86_64_32S
6113 || (reloc_type == BFD_RELOC_64
6114 && object_64bit))
d6ab8113
JB		 6115 && (i.op[n].disps->X_op == O_symbol
6116 || (i.op[n].disps->X_op == O_add
6117 && ((symbol_get_value_expression
6118 (i.op[n].disps->X_op_symbol)->X_op)
6119 == O_subtract))))
6120 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6121 {
6122 offsetT add;
6123
6124 if (insn_start_frag == frag_now)
6125 add = (p - frag_now->fr_literal) - insn_start_off;
6126 else
6127 {
6128 fragS *fr;
6129
6130 add = insn_start_frag->fr_fix - insn_start_off;
6131 for (fr = insn_start_frag->fr_next;
6132 fr && fr != frag_now; fr = fr->fr_next)
6133 add += fr->fr_fix;
6134 add += p - frag_now->fr_literal;
6135 }
6136
4fa24527 6137 if (!object_64bit)
7b81dfbb
AJ		 6138 {
6139 reloc_type = BFD_RELOC_386_GOTPC;
6140 i.op[n].imms->X_add_number += add;
6141 }
6142 else if (reloc_type == BFD_RELOC_64)
6143 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6144 else
7b81dfbb
AJ		 6145 /* Don't do the adjustment for x86-64, as there
6146 the pcrel addressing is relative to the _next_
6147 insn, and that is taken care of in other code. */
d6ab8113 6148 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6149 }
062cd5e7 6150 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6151 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6152 }
6153 }
6154 }
6155}
252b5132 6156
29b0f896 6157static void
64e74474 6158output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6159{
6160 char *p;
6161 unsigned int n;
252b5132 6162
29b0f896
AM		 6163 for (n = 0; n < i.operands; n++)
6164 {
40fb9820 6165 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6166 {
6167 if (i.op[n].imms->X_op == O_constant)
6168 {
e205caa7 6169 int size = imm_size (n);
29b0f896 6170 offsetT val;
b4cac588 6171
29b0f896
AM		 6172 val = offset_in_range (i.op[n].imms->X_add_number,
6173 size);
6174 p = frag_more (size);
6175 md_number_to_chars (p, val, size);
6176 }
6177 else
6178 {
6179 /* Not absolute_section.
6180 Need a 32-bit fixup (don't support 8bit
6181 non-absolute imms). Try to support other
6182 sizes ... */
f86103b7 6183 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6184 int size = imm_size (n);
6185 int sign;
29b0f896 6186
40fb9820 6187 if (i.types[n].bitfield.imm32s
a7d61044 6188 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6189 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6190 sign = 1;
e205caa7
L		 6191 else
6192 sign = 0;
520dc8e8 6193
29b0f896
AM		 6194 p = frag_more (size);
6195 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6196
2bbd9c25
JJ		 6197 /* This is tough to explain. We end up with this one if we
6198 * have operands that look like
6199 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6200 * obtain the absolute address of the GOT, and it is strongly
6201 * preferable from a performance point of view to avoid using
6202 * a runtime relocation for this. The actual sequence of
6203 * instructions often look something like:
6204 *
6205 * call .L66
6206 * .L66:
6207 * popl %ebx
6208 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6209 *
6210 * The call and pop essentially return the absolute address
6211 * of the label .L66 and store it in %ebx. The linker itself
6212 * will ultimately change the first operand of the addl so
6213 * that %ebx points to the GOT, but to keep things simple, the
6214 * .o file must have this operand set so that it generates not
6215 * the absolute address of .L66, but the absolute address of
6216 * itself. This allows the linker itself simply treat a GOTPC
6217 * relocation as asking for a pcrel offset to the GOT to be
6218 * added in, and the addend of the relocation is stored in the
6219 * operand field for the instruction itself.
6220 *
6221 * Our job here is to fix the operand so that it would add
6222 * the correct offset so that %ebx would point to itself. The
6223 * thing that is tricky is that .-.L66 will point to the
6224 * beginning of the instruction, so we need to further modify
6225 * the operand so that it will point to itself. There are
6226 * other cases where you have something like:
6227 *
6228 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6229 *
6230 * and here no correction would be required. Internally in
6231 * the assembler we treat operands of this form as not being
6232 * pcrel since the '.' is explicitly mentioned, and I wonder
6233 * whether it would simplify matters to do it this way. Who
6234 * knows. In earlier versions of the PIC patches, the
6235 * pcrel_adjust field was used to store the correction, but
6236 * since the expression is not pcrel, I felt it would be
6237 * confusing to do it this way. */
6238
d6ab8113 6239 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6240 || reloc_type == BFD_RELOC_X86_64_32S
6241 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6242 && GOT_symbol
6243 && GOT_symbol == i.op[n].imms->X_add_symbol
6244 && (i.op[n].imms->X_op == O_symbol
6245 || (i.op[n].imms->X_op == O_add
6246 && ((symbol_get_value_expression
6247 (i.op[n].imms->X_op_symbol)->X_op)
6248 == O_subtract))))
6249 {
2bbd9c25
JJ		 6250 offsetT add;
6251
6252 if (insn_start_frag == frag_now)
6253 add = (p - frag_now->fr_literal) - insn_start_off;
6254 else
6255 {
6256 fragS *fr;
6257
6258 add = insn_start_frag->fr_fix - insn_start_off;
6259 for (fr = insn_start_frag->fr_next;
6260 fr && fr != frag_now; fr = fr->fr_next)
6261 add += fr->fr_fix;
6262 add += p - frag_now->fr_literal;
6263 }
6264
4fa24527 6265 if (!object_64bit)
d6ab8113 6266 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6267 else if (size == 4)
d6ab8113 6268 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6269 else if (size == 8)
6270 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6271 i.op[n].imms->X_add_number += add;
29b0f896 6272 }
29b0f896
AM		 6273 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6274 i.op[n].imms, 0, reloc_type);
6275 }
6276 }
6277 }
252b5132
RH		 6278}
6279\f
d182319b
JB		 6280/* x86_cons_fix_new is called via the expression parsing code when a
6281 reloc is needed. We use this hook to get the correct .got reloc. */
6282static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6283static int cons_sign = -1;
6284
6285void
e3bb37b5 6286x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6287 expressionS *exp)
d182319b
JB		 6288{
6289 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6290
6291 got_reloc = NO_RELOC;
6292
6293#ifdef TE_PE
6294 if (exp->X_op == O_secrel)
6295 {
6296 exp->X_op = O_symbol;
6297 r = BFD_RELOC_32_SECREL;
6298 }
6299#endif
6300
6301 fix_new_exp (frag, off, len, exp, 0, r);
6302}
6303
718ddfc0
JB		 6304#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6305# define lex_got(reloc, adjust, types) NULL
6306#else
f3c180ae
AM		 6307/* Parse operands of the form
6308 <symbol>@GOTOFF+<nnn>
6309 and similar .plt or .got references.
6310
6311 If we find one, set up the correct relocation in RELOC and copy the
6312 input string, minus the `@GOTOFF' into a malloc'd buffer for
6313 parsing by the calling routine. Return this buffer, and if ADJUST
6314 is non-null set it to the length of the string we removed from the
6315 input line. Otherwise return NULL. */
6316static char *
3956db08 6317lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6318 int *adjust,
40fb9820 6319 i386_operand_type *types)
f3c180ae 6320{
7b81dfbb
AJ		 6321 /* Some of the relocations depend on the size of what field is to
6322 be relocated. But in our callers i386_immediate and i386_displacement
6323 we don't yet know the operand size (this will be set by insn
6324 matching). Hence we record the word32 relocation here,
6325 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6326 static const struct {
6327 const char *str;
4fa24527 6328 const enum bfd_reloc_code_real rel[2];
40fb9820 6329 const i386_operand_type types64;
f3c180ae 6330 } gotrel[] = {
4eed87de
AM		 6331 { "PLTOFF", { 0,
6332 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6333 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6334 { "PLT", { BFD_RELOC_386_PLT32,
6335 BFD_RELOC_X86_64_PLT32 },
40fb9820 6336 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6337 { "GOTPLT", { 0,
6338 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6339 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6340 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6341 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6342 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6343 { "GOTPCREL", { 0,
6344 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6345 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6346 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6347 BFD_RELOC_X86_64_TLSGD },
40fb9820 6348 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6349 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6350 0 },
40fb9820 6351 OPERAND_TYPE_NONE },
4eed87de
AM		 6352 { "TLSLD", { 0,
6353 BFD_RELOC_X86_64_TLSLD },
40fb9820 6354 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6355 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6356 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6357 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6358 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6359 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6360 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6361 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6362 0 },
40fb9820 6363 OPERAND_TYPE_NONE },
4eed87de
AM		 6364 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6365 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6366
6367 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6368 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6369 0 },
40fb9820 6370 OPERAND_TYPE_NONE },
4eed87de
AM		 6371 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6372 0 },
40fb9820 6373 OPERAND_TYPE_NONE },
4eed87de
AM		 6374 { "GOT", { BFD_RELOC_386_GOT32,
6375 BFD_RELOC_X86_64_GOT32 },
40fb9820 6376 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6377 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6378 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6379 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6380 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6381 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6382 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6383 };
6384 char *cp;
6385 unsigned int j;
6386
718ddfc0
JB		 6387 if (!IS_ELF)
6388 return NULL;
6389
f3c180ae 6390 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6391 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6392 return NULL;
6393
47465058 6394 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6395 {
6396 int len;
6397
6398 len = strlen (gotrel[j].str);
28f81592 6399 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6400 {
4fa24527 6401 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6402 {
28f81592
AM		 6403 int first, second;
6404 char *tmpbuf, *past_reloc;
f3c180ae 6405
4fa24527 6406 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6407 if (adjust)
6408 *adjust = len;
f3c180ae 6409
3956db08
JB		 6410 if (types)
6411 {
6412 if (flag_code != CODE_64BIT)
40fb9820
L		 6413 {
6414 types->bitfield.imm32 = 1;
6415 types->bitfield.disp32 = 1;
6416 }
3956db08
JB		 6417 else
6418 *types = gotrel[j].types64;
6419 }
6420
f3c180ae
AM		 6421 if (GOT_symbol == NULL)
6422 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6423
28f81592 6424 /* The length of the first part of our input line. */
f3c180ae 6425 first = cp - input_line_pointer;
28f81592
AM		 6426
6427 /* The second part goes from after the reloc token until
67c11a9b 6428 (and including) an end_of_line char or comma. */
28f81592 6429 past_reloc = cp + 1 + len;
67c11a9b
AM		 6430 cp = past_reloc;
6431 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6432 ++cp;
6433 second = cp + 1 - past_reloc;
28f81592
AM		 6434
6435 /* Allocate and copy string. The trailing NUL shouldn't
6436 be necessary, but be safe. */
6437 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6438 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6439 if (second != 0 && *past_reloc != ' ')
6440 /* Replace the relocation token with ' ', so that
6441 errors like foo@GOTOFF1 will be detected. */
6442 tmpbuf[first++] = ' ';
6443 memcpy (tmpbuf + first, past_reloc, second);
6444 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6445 return tmpbuf;
6446 }
6447
4fa24527
JB		 6448 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6449 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6450 return NULL;
6451 }
6452 }
6453
6454 /* Might be a symbol version string. Don't as_bad here. */
6455 return NULL;
6456}
6457
f3c180ae 6458void
e3bb37b5 6459x86_cons (expressionS *exp, int size)
f3c180ae 6460{
4fa24527 6461 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6462 {
6463 /* Handle @GOTOFF and the like in an expression. */
6464 char *save;
6465 char *gotfree_input_line;
6466 int adjust;
6467
6468 save = input_line_pointer;
3956db08 6469 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6470 if (gotfree_input_line)
6471 input_line_pointer = gotfree_input_line;
6472
6473 expression (exp);
6474
6475 if (gotfree_input_line)
6476 {
6477 /* expression () has merrily parsed up to the end of line,
6478 or a comma - in the wrong buffer. Transfer how far
6479 input_line_pointer has moved to the right buffer. */
6480 input_line_pointer = (save
6481 + (input_line_pointer - gotfree_input_line)
6482 + adjust);
6483 free (gotfree_input_line);
3992d3b7
AM		 6484 if (exp->X_op == O_constant
6485 || exp->X_op == O_absent
6486 || exp->X_op == O_illegal
6487 || exp->X_op == O_register
6488 || exp->X_op == O_big)
6489 {
6490 char c = *input_line_pointer;
6491 *input_line_pointer = 0;
6492 as_bad (_("missing or invalid expression `%s'"), save);
6493 *input_line_pointer = c;
6494 }
f3c180ae
AM		 6495 }
6496 }
6497 else
6498 expression (exp);
6499}
6500#endif
6501
d182319b 6502static void signed_cons (int size)
6482c264 6503{
d182319b
JB		 6504 if (flag_code == CODE_64BIT)
6505 cons_sign = 1;
6506 cons (size);
6507 cons_sign = -1;
6482c264
NC		 6508}
6509
d182319b 6510#ifdef TE_PE
6482c264
NC		 6511static void
6512pe_directive_secrel (dummy)
6513 int dummy ATTRIBUTE_UNUSED;
6514{
6515 expressionS exp;
6516
6517 do
6518 {
6519 expression (&exp);
6520 if (exp.X_op == O_symbol)
6521 exp.X_op = O_secrel;
6522
6523 emit_expr (&exp, 4);
6524 }
6525 while (*input_line_pointer++ == ',');
6526
6527 input_line_pointer--;
6528 demand_empty_rest_of_line ();
6529}
6482c264
NC		 6530#endif
6531
252b5132 6532static int
70e41ade 6533i386_immediate (char *imm_start)
252b5132
RH		 6534{
6535 char *save_input_line_pointer;
f3c180ae 6536 char *gotfree_input_line;
252b5132 6537 segT exp_seg = 0;
47926f60 6538 expressionS *exp;
40fb9820
L		 6539 i386_operand_type types;
6540
0dfbf9d7 6541 operand_type_set (&types, ~0);
252b5132
RH		 6542
6543 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6544 {
31b2323c
L		 6545 as_bad (_("at most %d immediate operands are allowed"),
6546 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6547 return 0;
6548 }
6549
6550 exp = &im_expressions[i.imm_operands++];
520dc8e8 6551 i.op[this_operand].imms = exp;
252b5132
RH		 6552
6553 if (is_space_char (*imm_start))
6554 ++imm_start;
6555
6556 save_input_line_pointer = input_line_pointer;
6557 input_line_pointer = imm_start;
6558
3956db08 6559 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6560 if (gotfree_input_line)
6561 input_line_pointer = gotfree_input_line;
252b5132
RH		 6562
6563 exp_seg = expression (exp);
6564
83183c0c 6565 SKIP_WHITESPACE ();
252b5132 6566 if (*input_line_pointer)
f3c180ae 6567 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6568
6569 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6570 if (gotfree_input_line)
6571 free (gotfree_input_line);
252b5132 6572
3992d3b7
AM		 6573 if (exp->X_op == O_absent
6574 || exp->X_op == O_illegal
6575 || exp->X_op == O_big
6576 || (gotfree_input_line
6577 && (exp->X_op == O_constant
6578 || exp->X_op == O_register)))
252b5132 6579 {
3992d3b7 6580 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6581 imm_start);
3992d3b7 6582 return 0;
252b5132 6583 }
3e73aa7c 6584 else if (exp->X_op == O_constant)
252b5132 6585 {
47926f60 6586 /* Size it properly later. */
40fb9820 6587 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6588 /* If BFD64, sign extend val. */
4eed87de
AM		 6589 if (!use_rela_relocations
6590 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6591 exp->X_add_number
6592 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6593 }
4c63da97 6594#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6595 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6596 && exp_seg != absolute_section
47926f60 6597 && exp_seg != text_section
24eab124
AM		 6598 && exp_seg != data_section
6599 && exp_seg != bss_section
6600 && exp_seg != undefined_section
f86103b7 6601 && !bfd_is_com_section (exp_seg))
252b5132 6602 {
d0b47220 6603 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6604 return 0;
6605 }
6606#endif
bb8f5920
L		 6607 else if (!intel_syntax && exp->X_op == O_register)
6608 {
6609 as_bad (_("illegal immediate register operand %s"), imm_start);
6610 return 0;
6611 }
252b5132
RH		 6612 else
6613 {
6614 /* This is an address. The size of the address will be
24eab124 6615 determined later, depending on destination register,
3e73aa7c 6616 suffix, or the default for the section. */
40fb9820
L		 6617 i.types[this_operand].bitfield.imm8 = 1;
6618 i.types[this_operand].bitfield.imm16 = 1;
6619 i.types[this_operand].bitfield.imm32 = 1;
6620 i.types[this_operand].bitfield.imm32s = 1;
6621 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6622 i.types[this_operand] = operand_type_and (i.types[this_operand],
6623 types);
252b5132
RH		 6624 }
6625
6626 return 1;
6627}
6628
551c1ca1 6629static char *
e3bb37b5 6630i386_scale (char *scale)
252b5132 6631{
551c1ca1
AM		 6632 offsetT val;
6633 char *save = input_line_pointer;
252b5132 6634
551c1ca1
AM		 6635 input_line_pointer = scale;
6636 val = get_absolute_expression ();
6637
6638 switch (val)
252b5132 6639 {
551c1ca1 6640 case 1:
252b5132
RH		 6641 i.log2_scale_factor = 0;
6642 break;
551c1ca1 6643 case 2:
252b5132
RH		 6644 i.log2_scale_factor = 1;
6645 break;
551c1ca1 6646 case 4:
252b5132
RH		 6647 i.log2_scale_factor = 2;
6648 break;
551c1ca1 6649 case 8:
252b5132
RH		 6650 i.log2_scale_factor = 3;
6651 break;
6652 default:
a724f0f4
JB		 6653 {
6654 char sep = *input_line_pointer;
6655
6656 *input_line_pointer = '\0';
6657 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6658 scale);
6659 *input_line_pointer = sep;
6660 input_line_pointer = save;
6661 return NULL;
6662 }
252b5132 6663 }
29b0f896 6664 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6665 {
6666 as_warn (_("scale factor of %d without an index register"),
24eab124 6667 1 << i.log2_scale_factor);
252b5132 6668 i.log2_scale_factor = 0;
252b5132 6669 }
551c1ca1
AM		 6670 scale = input_line_pointer;
6671 input_line_pointer = save;
6672 return scale;
252b5132
RH		 6673}
6674
252b5132 6675static int
e3bb37b5 6676i386_displacement (char *disp_start, char *disp_end)
252b5132 6677{
29b0f896 6678 expressionS *exp;
252b5132
RH		 6679 segT exp_seg = 0;
6680 char *save_input_line_pointer;
f3c180ae 6681 char *gotfree_input_line;
40fb9820
L		 6682 int override;
6683 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6684 int ret;
252b5132 6685
31b2323c
L		 6686 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6687 {
6688 as_bad (_("at most %d displacement operands are allowed"),
6689 MAX_MEMORY_OPERANDS);
6690 return 0;
6691 }
6692
0dfbf9d7 6693 operand_type_set (&bigdisp, 0);
40fb9820
L		 6694 if ((i.types[this_operand].bitfield.jumpabsolute)
6695 || (!current_templates->start->opcode_modifier.jump
6696 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6697 {
40fb9820 6698 bigdisp.bitfield.disp32 = 1;
e05278af 6699 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6700 if (flag_code == CODE_64BIT)
6701 {
6702 if (!override)
6703 {
6704 bigdisp.bitfield.disp32s = 1;
6705 bigdisp.bitfield.disp64 = 1;
6706 }
6707 }
6708 else if ((flag_code == CODE_16BIT) ^ override)
6709 {
6710 bigdisp.bitfield.disp32 = 0;
6711 bigdisp.bitfield.disp16 = 1;
6712 }
e05278af
JB		 6713 }
6714 else
6715 {
6716 /* For PC-relative branches, the width of the displacement
6717 is dependent upon data size, not address size. */
e05278af 6718 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6719 if (flag_code == CODE_64BIT)
6720 {
6721 if (override || i.suffix == WORD_MNEM_SUFFIX)
6722 bigdisp.bitfield.disp16 = 1;
6723 else
6724 {
6725 bigdisp.bitfield.disp32 = 1;
6726 bigdisp.bitfield.disp32s = 1;
6727 }
6728 }
6729 else
e05278af
JB		 6730 {
6731 if (!override)
6732 override = (i.suffix == (flag_code != CODE_16BIT
6733 ? WORD_MNEM_SUFFIX
6734 : LONG_MNEM_SUFFIX));
40fb9820
L		 6735 bigdisp.bitfield.disp32 = 1;
6736 if ((flag_code == CODE_16BIT) ^ override)
6737 {
6738 bigdisp.bitfield.disp32 = 0;
6739 bigdisp.bitfield.disp16 = 1;
6740 }
e05278af 6741 }
e05278af 6742 }
c6fb90c8
L		 6743 i.types[this_operand] = operand_type_or (i.types[this_operand],
6744 bigdisp);
252b5132
RH		 6745
6746 exp = &disp_expressions[i.disp_operands];
520dc8e8 6747 i.op[this_operand].disps = exp;
252b5132
RH		 6748 i.disp_operands++;
6749 save_input_line_pointer = input_line_pointer;
6750 input_line_pointer = disp_start;
6751 END_STRING_AND_SAVE (disp_end);
6752
6753#ifndef GCC_ASM_O_HACK
6754#define GCC_ASM_O_HACK 0
6755#endif
6756#if GCC_ASM_O_HACK
6757 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6758 if (i.types[this_operand].bitfield.baseIndex
24eab124 6759 && displacement_string_end[-1] == '+')
252b5132
RH		 6760 {
6761 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6762 constraint within gcc asm statements.
6763 For instance:
6764
6765 #define _set_tssldt_desc(n,addr,limit,type) \
6766 __asm__ __volatile__ ( \
6767 "movw %w2,%0\n\t" \
6768 "movw %w1,2+%0\n\t" \
6769 "rorl $16,%1\n\t" \
6770 "movb %b1,4+%0\n\t" \
6771 "movb %4,5+%0\n\t" \
6772 "movb $0,6+%0\n\t" \
6773 "movb %h1,7+%0\n\t" \
6774 "rorl $16,%1" \
6775 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6776
6777 This works great except that the output assembler ends
6778 up looking a bit weird if it turns out that there is
6779 no offset. You end up producing code that looks like:
6780
6781 #APP
6782 movw $235,(%eax)
6783 movw %dx,2+(%eax)
6784 rorl $16,%edx
6785 movb %dl,4+(%eax)
6786 movb $137,5+(%eax)
6787 movb $0,6+(%eax)
6788 movb %dh,7+(%eax)
6789 rorl $16,%edx
6790 #NO_APP
6791
47926f60 6792 So here we provide the missing zero. */
24eab124
AM		 6793
6794 *displacement_string_end = '0';
252b5132
RH		 6795 }
6796#endif
3956db08 6797 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6798 if (gotfree_input_line)
6799 input_line_pointer = gotfree_input_line;
252b5132 6800
24eab124 6801 exp_seg = expression (exp);
252b5132 6802
636c26b0
AM		 6803 SKIP_WHITESPACE ();
6804 if (*input_line_pointer)
6805 as_bad (_("junk `%s' after expression"), input_line_pointer);
6806#if GCC_ASM_O_HACK
6807 RESTORE_END_STRING (disp_end + 1);
6808#endif
636c26b0 6809 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6810 if (gotfree_input_line)
6811 free (gotfree_input_line);
3992d3b7 6812 ret = 1;
636c26b0 6813
24eab124
AM		 6814 /* We do this to make sure that the section symbol is in
6815 the symbol table. We will ultimately change the relocation
47926f60 6816 to be relative to the beginning of the section. */
1ae12ab7 6817 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6818 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6819 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6820 {
636c26b0 6821 if (exp->X_op != O_symbol)
3992d3b7 6822 goto inv_disp;
636c26b0 6823
e5cb08ac 6824 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6825 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6826 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6827 exp->X_op = O_subtract;
6828 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6829 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6830 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6831 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6832 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6833 else
29b0f896 6834 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6835 }
252b5132 6836
3992d3b7
AM		 6837 else if (exp->X_op == O_absent
6838 || exp->X_op == O_illegal
6839 || exp->X_op == O_big
6840 || (gotfree_input_line
6841 && (exp->X_op == O_constant
6842 || exp->X_op == O_register)))
2daf4fd8 6843 {
3992d3b7
AM		 6844 inv_disp:
6845 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6846 disp_start);
3992d3b7 6847 ret = 0;
2daf4fd8
AM		 6848 }
6849
4c63da97 6850#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6851 else if (exp->X_op != O_constant
6852 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6853 && exp_seg != absolute_section
6854 && exp_seg != text_section
6855 && exp_seg != data_section
6856 && exp_seg != bss_section
6857 && exp_seg != undefined_section
6858 && !bfd_is_com_section (exp_seg))
24eab124 6859 {
d0b47220 6860 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6861 ret = 0;
24eab124 6862 }
252b5132 6863#endif
3956db08 6864
3992d3b7
AM		 6865 RESTORE_END_STRING (disp_end);
6866
40fb9820
L		 6867 /* Check if this is a displacement only operand. */
6868 bigdisp = i.types[this_operand];
6869 bigdisp.bitfield.disp8 = 0;
6870 bigdisp.bitfield.disp16 = 0;
6871 bigdisp.bitfield.disp32 = 0;
6872 bigdisp.bitfield.disp32s = 0;
6873 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6874 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6875 i.types[this_operand] = operand_type_and (i.types[this_operand],
6876 types);
3956db08 6877
3992d3b7 6878 return ret;
252b5132
RH		 6879}
6880
eecb386c 6881/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6882 Return 1 on success, 0 on a failure. */
6883
252b5132 6884static int
e3bb37b5 6885i386_index_check (const char *operand_string)
252b5132 6886{
3e73aa7c 6887 int ok;
fc0763e6 6888 const char *kind = "base/index";
24eab124 6889#if INFER_ADDR_PREFIX
eecb386c
AM		 6890 int fudged = 0;
6891
24eab124
AM		 6892 tryprefix:
6893#endif
3e73aa7c 6894 ok = 1;
fc0763e6
JB		 6895 if (current_templates->start->opcode_modifier.isstring
6896 && !current_templates->start->opcode_modifier.immext
6897 && (current_templates->end[-1].opcode_modifier.isstring
6898 || i.mem_operands))
6899 {
6900 /* Memory operands of string insns are special in that they only allow
6901 a single register (rDI, rSI, or rBX) as their memory address. */
6902 unsigned int expected;
6903
6904 kind = "string address";
6905
6906 if (current_templates->start->opcode_modifier.w)
6907 {
6908 i386_operand_type type = current_templates->end[-1].operand_types[0];
6909
6910 if (!type.bitfield.baseindex
6911 || ((!i.mem_operands != !intel_syntax)
6912 && current_templates->end[-1].operand_types[1]
6913 .bitfield.baseindex))
6914 type = current_templates->end[-1].operand_types[1];
6915 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6916 }
6917 else
6918 expected = 3 /* rBX */;
6919
6920 if (!i.base_reg || i.index_reg
6921 || operand_type_check (i.types[this_operand], disp))
6922 ok = -1;
6923 else if (!(flag_code == CODE_64BIT
6924 ? i.prefix[ADDR_PREFIX]
6925 ? i.base_reg->reg_type.bitfield.reg32
6926 : i.base_reg->reg_type.bitfield.reg64
6927 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6928 ? i.base_reg->reg_type.bitfield.reg32
6929 : i.base_reg->reg_type.bitfield.reg16))
6930 ok = 0;
6931 else if (i.base_reg->reg_num != expected)
6932 ok = -1;
6933
6934 if (ok < 0)
6935 {
6936 unsigned int j;
6937
6938 for (j = 0; j < i386_regtab_size; ++j)
6939 if ((flag_code == CODE_64BIT
6940 ? i.prefix[ADDR_PREFIX]
6941 ? i386_regtab[j].reg_type.bitfield.reg32
6942 : i386_regtab[j].reg_type.bitfield.reg64
6943 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6944 ? i386_regtab[j].reg_type.bitfield.reg32
6945 : i386_regtab[j].reg_type.bitfield.reg16)
6946 && i386_regtab[j].reg_num == expected)
6947 break;
6948 assert (j < i386_regtab_size);
6949 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6950 operand_string,
6951 intel_syntax ? '[' : '(',
6952 register_prefix,
6953 i386_regtab[j].reg_name,
6954 intel_syntax ? ']' : ')');
6955 ok = 1;
6956 }
6957 }
6958 else if (flag_code == CODE_64BIT)
64e74474 6959 {
64e74474 6960 if ((i.base_reg
40fb9820
L		 6961 && ((i.prefix[ADDR_PREFIX] == 0
6962 && !i.base_reg->reg_type.bitfield.reg64)
6963 || (i.prefix[ADDR_PREFIX]
6964 && !i.base_reg->reg_type.bitfield.reg32))
6965 && (i.index_reg
9a04903e
JB		 6966 || i.base_reg->reg_num !=
6967 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6968 || (i.index_reg
40fb9820
L		 6969 && (!i.index_reg->reg_type.bitfield.baseindex
6970 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6971 && i.index_reg->reg_num != RegRiz
6972 && !i.index_reg->reg_type.bitfield.reg64
6973 )
40fb9820 6974 || (i.prefix[ADDR_PREFIX]
db51cc60 6975 && i.index_reg->reg_num != RegEiz
40fb9820 6976 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6977 ok = 0;
3e73aa7c
JH		 6978 }
6979 else
6980 {
6981 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6982 {
6983 /* 16bit checks. */
6984 if ((i.base_reg
40fb9820
L		 6985 && (!i.base_reg->reg_type.bitfield.reg16
6986 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6987 || (i.index_reg
40fb9820
L		 6988 && (!i.index_reg->reg_type.bitfield.reg16
6989 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6990 || !(i.base_reg
6991 && i.base_reg->reg_num < 6
6992 && i.index_reg->reg_num >= 6
6993 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6994 ok = 0;
6995 }
6996 else
e5cb08ac 6997 {
3e73aa7c
JH		 6998 /* 32bit checks. */
6999 if ((i.base_reg
40fb9820 7000 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7001 || (i.index_reg
db51cc60
L		 7002 && ((!i.index_reg->reg_type.bitfield.reg32
7003 && i.index_reg->reg_num != RegEiz)
40fb9820 7004 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7005 ok = 0;
3e73aa7c
JH		 7006 }
7007 }
7008 if (!ok)
24eab124
AM		 7009 {
7010#if INFER_ADDR_PREFIX
fc0763e6 7011 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7012 {
7013 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7014 i.prefixes += 1;
b23bac36
AM		 7015 /* Change the size of any displacement too. At most one of
7016 Disp16 or Disp32 is set.
7017 FIXME. There doesn't seem to be any real need for separate
7018 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7019 Removing them would probably clean up the code quite a lot. */
4eed87de 7020 if (flag_code != CODE_64BIT
40fb9820
L		 7021 && (i.types[this_operand].bitfield.disp16
7022 || i.types[this_operand].bitfield.disp32))
7023 i.types[this_operand]
c6fb90c8 7024 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7025 fudged = 1;
24eab124
AM		 7026 goto tryprefix;
7027 }
eecb386c 7028 if (fudged)
fc0763e6
JB		 7029 as_bad (_("`%s' is not a valid %s expression"),
7030 operand_string,
7031 kind);
eecb386c 7032 else
c388dee8 7033#endif
fc0763e6 7034 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7035 operand_string,
fc0763e6
JB		 7036 flag_code_names[i.prefix[ADDR_PREFIX]
7037 ? flag_code == CODE_32BIT
7038 ? CODE_16BIT
7039 : CODE_32BIT
7040 : flag_code],
7041 kind);
24eab124 7042 }
20f0a1fc 7043 return ok;
24eab124 7044}
252b5132 7045
fc0763e6 7046/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7047 on error. */
252b5132 7048
252b5132 7049static int
a7619375 7050i386_att_operand (char *operand_string)
252b5132 7051{
af6bdddf
AM		 7052 const reg_entry *r;
7053 char *end_op;
24eab124 7054 char *op_string = operand_string;
252b5132 7055
24eab124 7056 if (is_space_char (*op_string))
252b5132
RH		 7057 ++op_string;
7058
24eab124 7059 /* We check for an absolute prefix (differentiating,
47926f60 7060 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7061 if (*op_string == ABSOLUTE_PREFIX)
7062 {
7063 ++op_string;
7064 if (is_space_char (*op_string))
7065 ++op_string;
40fb9820 7066 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7067 }
252b5132 7068
47926f60 7069 /* Check if operand is a register. */
4d1bb795 7070 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7071 {
40fb9820
L		 7072 i386_operand_type temp;
7073
24eab124
AM		 7074 /* Check for a segment override by searching for ':' after a
7075 segment register. */
7076 op_string = end_op;
7077 if (is_space_char (*op_string))
7078 ++op_string;
40fb9820
L		 7079 if (*op_string == ':'
7080 && (r->reg_type.bitfield.sreg2
7081 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7082 {
7083 switch (r->reg_num)
7084 {
7085 case 0:
7086 i.seg[i.mem_operands] = &es;
7087 break;
7088 case 1:
7089 i.seg[i.mem_operands] = &cs;
7090 break;
7091 case 2:
7092 i.seg[i.mem_operands] = &ss;
7093 break;
7094 case 3:
7095 i.seg[i.mem_operands] = &ds;
7096 break;
7097 case 4:
7098 i.seg[i.mem_operands] = &fs;
7099 break;
7100 case 5:
7101 i.seg[i.mem_operands] = &gs;
7102 break;
7103 }
252b5132 7104
24eab124 7105 /* Skip the ':' and whitespace. */
252b5132
RH		 7106 ++op_string;
7107 if (is_space_char (*op_string))
24eab124 7108 ++op_string;
252b5132 7109
24eab124
AM		 7110 if (!is_digit_char (*op_string)
7111 && !is_identifier_char (*op_string)
7112 && *op_string != '('
7113 && *op_string != ABSOLUTE_PREFIX)
7114 {
7115 as_bad (_("bad memory operand `%s'"), op_string);
7116 return 0;
7117 }
47926f60 7118 /* Handle case of %es:*foo. */
24eab124
AM		 7119 if (*op_string == ABSOLUTE_PREFIX)
7120 {
7121 ++op_string;
7122 if (is_space_char (*op_string))
7123 ++op_string;
40fb9820 7124 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7125 }
7126 goto do_memory_reference;
7127 }
7128 if (*op_string)
7129 {
d0b47220 7130 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7131 return 0;
7132 }
40fb9820
L		 7133 temp = r->reg_type;
7134 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7135 i.types[this_operand] = operand_type_or (i.types[this_operand],
7136 temp);
7d5e4556 7137 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7138 i.op[this_operand].regs = r;
24eab124
AM		 7139 i.reg_operands++;
7140 }
af6bdddf
AM		 7141 else if (*op_string == REGISTER_PREFIX)
7142 {
7143 as_bad (_("bad register name `%s'"), op_string);
7144 return 0;
7145 }
24eab124 7146 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7147 {
24eab124 7148 ++op_string;
40fb9820 7149 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7150 {
d0b47220 7151 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7152 return 0;
7153 }
7154 if (!i386_immediate (op_string))
7155 return 0;
7156 }
7157 else if (is_digit_char (*op_string)
7158 || is_identifier_char (*op_string)
e5cb08ac 7159 || *op_string == '(')
24eab124 7160 {
47926f60 7161 /* This is a memory reference of some sort. */
af6bdddf 7162 char *base_string;
252b5132 7163
47926f60 7164 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7165 char *displacement_string_start;
7166 char *displacement_string_end;
252b5132 7167
24eab124 7168 do_memory_reference:
24eab124 7169 if ((i.mem_operands == 1
40fb9820 7170 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7171 || i.mem_operands == 2)
7172 {
7173 as_bad (_("too many memory references for `%s'"),
7174 current_templates->start->name);
7175 return 0;
7176 }
252b5132 7177
24eab124
AM		 7178 /* Check for base index form. We detect the base index form by
7179 looking for an ')' at the end of the operand, searching
7180 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7181 after the '('. */
af6bdddf 7182 base_string = op_string + strlen (op_string);
c3332e24 7183
af6bdddf
AM		 7184 --base_string;
7185 if (is_space_char (*base_string))
7186 --base_string;
252b5132 7187
47926f60 7188 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7189 displacement_string_start = op_string;
7190 displacement_string_end = base_string + 1;
252b5132 7191
24eab124
AM		 7192 if (*base_string == ')')
7193 {
af6bdddf 7194 char *temp_string;
24eab124
AM		 7195 unsigned int parens_balanced = 1;
7196 /* We've already checked that the number of left & right ()'s are
47926f60 7197 equal, so this loop will not be infinite. */
24eab124
AM		 7198 do
7199 {
7200 base_string--;
7201 if (*base_string == ')')
7202 parens_balanced++;
7203 if (*base_string == '(')
7204 parens_balanced--;
7205 }
7206 while (parens_balanced);
c3332e24 7207
af6bdddf 7208 temp_string = base_string;
c3332e24 7209
24eab124 7210 /* Skip past '(' and whitespace. */
252b5132
RH		 7211 ++base_string;
7212 if (is_space_char (*base_string))
24eab124 7213 ++base_string;
252b5132 7214
af6bdddf 7215 if (*base_string == ','
4eed87de
AM		 7216 || ((i.base_reg = parse_register (base_string, &end_op))
7217 != NULL))
252b5132 7218 {
af6bdddf 7219 displacement_string_end = temp_string;
252b5132 7220
40fb9820 7221 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7222
af6bdddf 7223 if (i.base_reg)
24eab124 7224 {
24eab124
AM		 7225 base_string = end_op;
7226 if (is_space_char (*base_string))
7227 ++base_string;
af6bdddf
AM		 7228 }
7229
7230 /* There may be an index reg or scale factor here. */
7231 if (*base_string == ',')
7232 {
7233 ++base_string;
7234 if (is_space_char (*base_string))
7235 ++base_string;
7236
4eed87de
AM		 7237 if ((i.index_reg = parse_register (base_string, &end_op))
7238 != NULL)
24eab124 7239 {
af6bdddf 7240 base_string = end_op;
24eab124
AM		 7241 if (is_space_char (*base_string))
7242 ++base_string;
af6bdddf
AM		 7243 if (*base_string == ',')
7244 {
7245 ++base_string;
7246 if (is_space_char (*base_string))
7247 ++base_string;
7248 }
e5cb08ac 7249 else if (*base_string != ')')
af6bdddf 7250 {
4eed87de
AM		 7251 as_bad (_("expecting `,' or `)' "
7252 "after index register in `%s'"),
af6bdddf
AM		 7253 operand_string);
7254 return 0;
7255 }
24eab124 7256 }
af6bdddf 7257 else if (*base_string == REGISTER_PREFIX)
24eab124 7258 {
af6bdddf 7259 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7260 return 0;
7261 }
252b5132 7262
47926f60 7263 /* Check for scale factor. */
551c1ca1 7264 if (*base_string != ')')
af6bdddf 7265 {
551c1ca1
AM		 7266 char *end_scale = i386_scale (base_string);
7267
7268 if (!end_scale)
af6bdddf 7269 return 0;
24eab124 7270
551c1ca1 7271 base_string = end_scale;
af6bdddf
AM		 7272 if (is_space_char (*base_string))
7273 ++base_string;
7274 if (*base_string != ')')
7275 {
4eed87de
AM		 7276 as_bad (_("expecting `)' "
7277 "after scale factor in `%s'"),
af6bdddf
AM		 7278 operand_string);
7279 return 0;
7280 }
7281 }
7282 else if (!i.index_reg)
24eab124 7283 {
4eed87de
AM		 7284 as_bad (_("expecting index register or scale factor "
7285 "after `,'; got '%c'"),
af6bdddf 7286 *base_string);
24eab124
AM		 7287 return 0;
7288 }
7289 }
af6bdddf 7290 else if (*base_string != ')')
24eab124 7291 {
4eed87de
AM		 7292 as_bad (_("expecting `,' or `)' "
7293 "after base register in `%s'"),
af6bdddf 7294 operand_string);
24eab124
AM		 7295 return 0;
7296 }
c3332e24 7297 }
af6bdddf 7298 else if (*base_string == REGISTER_PREFIX)
c3332e24 7299 {
af6bdddf 7300 as_bad (_("bad register name `%s'"), base_string);
24eab124 7301 return 0;
c3332e24 7302 }
24eab124
AM		 7303 }
7304
7305 /* If there's an expression beginning the operand, parse it,
7306 assuming displacement_string_start and
7307 displacement_string_end are meaningful. */
7308 if (displacement_string_start != displacement_string_end)
7309 {
7310 if (!i386_displacement (displacement_string_start,
7311 displacement_string_end))
7312 return 0;
7313 }
7314
7315 /* Special case for (%dx) while doing input/output op. */
7316 if (i.base_reg
0dfbf9d7
L		 7317 && operand_type_equal (&i.base_reg->reg_type,
7318 &reg16_inoutportreg)
24eab124
AM		 7319 && i.index_reg == 0
7320 && i.log2_scale_factor == 0
7321 && i.seg[i.mem_operands] == 0
40fb9820 7322 && !operand_type_check (i.types[this_operand], disp))
24eab124 7323 {
65da13b5 7324 i.types[this_operand] = inoutportreg;
24eab124
AM		 7325 return 1;
7326 }
7327
eecb386c
AM		 7328 if (i386_index_check (operand_string) == 0)
7329 return 0;
5c07affc 7330 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7331 i.mem_operands++;
7332 }
7333 else
ce8a8b2f
AM		 7334 {
7335 /* It's not a memory operand; argh! */
24eab124
AM		 7336 as_bad (_("invalid char %s beginning operand %d `%s'"),
7337 output_invalid (*op_string),
7338 this_operand + 1,
7339 op_string);
7340 return 0;
7341 }
47926f60 7342 return 1; /* Normal return. */
252b5132
RH		 7343}
7344\f
ee7fcc42
AM		 7345/* md_estimate_size_before_relax()
7346
7347 Called just before relax() for rs_machine_dependent frags. The x86
7348 assembler uses these frags to handle variable size jump
7349 instructions.
7350
7351 Any symbol that is now undefined will not become defined.
7352 Return the correct fr_subtype in the frag.
7353 Return the initial "guess for variable size of frag" to caller.
7354 The guess is actually the growth beyond the fixed part. Whatever
7355 we do to grow the fixed or variable part contributes to our
7356 returned value. */
7357
252b5132
RH		 7358int
7359md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7360 fragS *fragP;
7361 segT segment;
252b5132 7362{
252b5132 7363 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7364 check for un-relaxable symbols. On an ELF system, we can't relax
7365 an externally visible symbol, because it may be overridden by a
7366 shared library. */
7367 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7368#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7369 || (IS_ELF
31312f95
AM		 7370 && (S_IS_EXTERNAL (fragP->fr_symbol)
7371 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7372#endif
7373 )
252b5132 7374 {
b98ef147
AM		 7375 /* Symbol is undefined in this segment, or we need to keep a
7376 reloc so that weak symbols can be overridden. */
7377 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7378 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7379 unsigned char *opcode;
7380 int old_fr_fix;
f6af82bd 7381
ee7fcc42
AM		 7382 if (fragP->fr_var != NO_RELOC)
7383 reloc_type = fragP->fr_var;
b98ef147 7384 else if (size == 2)
f6af82bd
AM		 7385 reloc_type = BFD_RELOC_16_PCREL;
7386 else
7387 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7388
ee7fcc42
AM		 7389 old_fr_fix = fragP->fr_fix;
7390 opcode = (unsigned char *) fragP->fr_opcode;
7391
fddf5b5b 7392 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7393 {
fddf5b5b
AM		 7394 case UNCOND_JUMP:
7395 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7396 opcode[0] = 0xe9;
252b5132 7397 fragP->fr_fix += size;
062cd5e7
AS		 7398 fix_new (fragP, old_fr_fix, size,
7399 fragP->fr_symbol,
7400 fragP->fr_offset, 1,
7401 reloc_type);
252b5132
RH		 7402 break;
7403
fddf5b5b 7404 case COND_JUMP86:
412167cb
AM		 7405 if (size == 2
7406 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7407 {
7408 /* Negate the condition, and branch past an
7409 unconditional jump. */
7410 opcode[0] ^= 1;
7411 opcode[1] = 3;
7412 /* Insert an unconditional jump. */
7413 opcode[2] = 0xe9;
7414 /* We added two extra opcode bytes, and have a two byte
7415 offset. */
7416 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7417 fix_new (fragP, old_fr_fix + 2, 2,
7418 fragP->fr_symbol,
7419 fragP->fr_offset, 1,
7420 reloc_type);
fddf5b5b
AM		 7421 break;
7422 }
7423 /* Fall through. */
7424
7425 case COND_JUMP:
412167cb
AM		 7426 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7427 {
3e02c1cc
AM		 7428 fixS *fixP;
7429
412167cb 7430 fragP->fr_fix += 1;
3e02c1cc
AM		 7431 fixP = fix_new (fragP, old_fr_fix, 1,
7432 fragP->fr_symbol,
7433 fragP->fr_offset, 1,
7434 BFD_RELOC_8_PCREL);
7435 fixP->fx_signed = 1;
412167cb
AM		 7436 break;
7437 }
93c2a809 7438
24eab124 7439 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7440 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7441 opcode[1] = opcode[0] + 0x10;
f6af82bd 7442 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7443 /* We've added an opcode byte. */
7444 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7445 fix_new (fragP, old_fr_fix + 1, size,
7446 fragP->fr_symbol,
7447 fragP->fr_offset, 1,
7448 reloc_type);
252b5132 7449 break;
fddf5b5b
AM		 7450
7451 default:
7452 BAD_CASE (fragP->fr_subtype);
7453 break;
252b5132
RH		 7454 }
7455 frag_wane (fragP);
ee7fcc42 7456 return fragP->fr_fix - old_fr_fix;
252b5132 7457 }
93c2a809 7458
93c2a809
AM		 7459 /* Guess size depending on current relax state. Initially the relax
7460 state will correspond to a short jump and we return 1, because
7461 the variable part of the frag (the branch offset) is one byte
7462 long. However, we can relax a section more than once and in that
7463 case we must either set fr_subtype back to the unrelaxed state,
7464 or return the value for the appropriate branch. */
7465 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7466}
7467
47926f60
KH		 7468/* Called after relax() is finished.
7469
7470 In: Address of frag.
7471 fr_type == rs_machine_dependent.
7472 fr_subtype is what the address relaxed to.
7473
7474 Out: Any fixSs and constants are set up.
7475 Caller will turn frag into a ".space 0". */
7476
252b5132
RH		 7477void
7478md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7479 bfd *abfd ATTRIBUTE_UNUSED;
7480 segT sec ATTRIBUTE_UNUSED;
29b0f896 7481 fragS *fragP;
252b5132 7482{
29b0f896 7483 unsigned char *opcode;
252b5132 7484 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7485 offsetT target_address;
7486 offsetT opcode_address;
252b5132 7487 unsigned int extension = 0;
847f7ad4 7488 offsetT displacement_from_opcode_start;
252b5132
RH		 7489
7490 opcode = (unsigned char *) fragP->fr_opcode;
7491
47926f60 7492 /* Address we want to reach in file space. */
252b5132 7493 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7494
47926f60 7495 /* Address opcode resides at in file space. */
252b5132
RH		 7496 opcode_address = fragP->fr_address + fragP->fr_fix;
7497
47926f60 7498 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7499 displacement_from_opcode_start = target_address - opcode_address;
7500
fddf5b5b 7501 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7502 {
47926f60
KH		 7503 /* Don't have to change opcode. */
7504 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7505 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7506 }
7507 else
7508 {
7509 if (no_cond_jump_promotion
7510 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7511 as_warn_where (fragP->fr_file, fragP->fr_line,
7512 _("long jump required"));
252b5132 7513
fddf5b5b
AM		 7514 switch (fragP->fr_subtype)
7515 {
7516 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7517 extension = 4; /* 1 opcode + 4 displacement */
7518 opcode[0] = 0xe9;
7519 where_to_put_displacement = &opcode[1];
7520 break;
252b5132 7521
fddf5b5b
AM		 7522 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7523 extension = 2; /* 1 opcode + 2 displacement */
7524 opcode[0] = 0xe9;
7525 where_to_put_displacement = &opcode[1];
7526 break;
252b5132 7527
fddf5b5b
AM		 7528 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7529 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7530 extension = 5; /* 2 opcode + 4 displacement */
7531 opcode[1] = opcode[0] + 0x10;
7532 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7533 where_to_put_displacement = &opcode[2];
7534 break;
252b5132 7535
fddf5b5b
AM		 7536 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7537 extension = 3; /* 2 opcode + 2 displacement */
7538 opcode[1] = opcode[0] + 0x10;
7539 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7540 where_to_put_displacement = &opcode[2];
7541 break;
252b5132 7542
fddf5b5b
AM		 7543 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7544 extension = 4;
7545 opcode[0] ^= 1;
7546 opcode[1] = 3;
7547 opcode[2] = 0xe9;
7548 where_to_put_displacement = &opcode[3];
7549 break;
7550
7551 default:
7552 BAD_CASE (fragP->fr_subtype);
7553 break;
7554 }
252b5132 7555 }
fddf5b5b 7556
7b81dfbb
AJ		 7557 /* If size if less then four we are sure that the operand fits,
7558 but if it's 4, then it could be that the displacement is larger
7559 then -/+ 2GB. */
7560 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7561 && object_64bit
7562 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7563 + ((addressT) 1 << 31))
7564 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7565 {
7566 as_bad_where (fragP->fr_file, fragP->fr_line,
7567 _("jump target out of range"));
7568 /* Make us emit 0. */
7569 displacement_from_opcode_start = extension;
7570 }
47926f60 7571 /* Now put displacement after opcode. */
252b5132
RH		 7572 md_number_to_chars ((char *) where_to_put_displacement,
7573 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7574 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7575 fragP->fr_fix += extension;
7576}
7577\f
252b5132
RH		 7578/* Apply a fixup (fixS) to segment data, once it has been determined
7579 by our caller that we have all the info we need to fix it up.
7580
7581 On the 386, immediates, displacements, and data pointers are all in
7582 the same (little-endian) format, so we don't need to care about which
7583 we are handling. */
7584
94f592af 7585void
55cf6793 7586md_apply_fix (fixP, valP, seg)
47926f60
KH		 7587 /* The fix we're to put in. */
7588 fixS *fixP;
47926f60 7589 /* Pointer to the value of the bits. */
c6682705 7590 valueT *valP;
47926f60
KH		 7591 /* Segment fix is from. */
7592 segT seg ATTRIBUTE_UNUSED;
252b5132 7593{
94f592af 7594 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7595 valueT value = *valP;
252b5132 7596
f86103b7 7597#if !defined (TE_Mach)
93382f6d
AM		 7598 if (fixP->fx_pcrel)
7599 {
7600 switch (fixP->fx_r_type)
7601 {
5865bb77
ILT		 7602 default:
7603 break;
7604
d6ab8113
JB		 7605 case BFD_RELOC_64:
7606 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7607 break;
93382f6d 7608 case BFD_RELOC_32:
ae8887b5 7609 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7610 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7611 break;
7612 case BFD_RELOC_16:
7613 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7614 break;
7615 case BFD_RELOC_8:
7616 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7617 break;
7618 }
7619 }
252b5132 7620
a161fe53 7621 if (fixP->fx_addsy != NULL
31312f95 7622 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7623 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7624 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7625 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7626 && !use_rela_relocations)
252b5132 7627 {
31312f95
AM		 7628 /* This is a hack. There should be a better way to handle this.
7629 This covers for the fact that bfd_install_relocation will
7630 subtract the current location (for partial_inplace, PC relative
7631 relocations); see more below. */
252b5132 7632#ifndef OBJ_AOUT
718ddfc0 7633 if (IS_ELF
252b5132
RH		 7634#ifdef TE_PE
7635 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7636#endif
7637 )
7638 value += fixP->fx_where + fixP->fx_frag->fr_address;
7639#endif
7640#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7641 if (IS_ELF)
252b5132 7642 {
6539b54b 7643 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7644
6539b54b 7645 if ((sym_seg == seg
2f66722d 7646 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7647 && sym_seg != absolute_section))
ae6063d4 7648 && !generic_force_reloc (fixP))
2f66722d
AM		 7649 {
7650 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7651 bfd_install_relocation subtracts them out again. I think
7652 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7653 it. FIXME. */
7654 value += fixP->fx_where + fixP->fx_frag->fr_address;
7655 }
252b5132
RH		 7656 }
7657#endif
7658#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7659 /* For some reason, the PE format does not store a
7660 section address offset for a PC relative symbol. */
7661 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7662 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7663 value += md_pcrel_from (fixP);
7664#endif
7665 }
7666
7667 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7668 and we must not disappoint it. */
252b5132 7669#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7670 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7671 switch (fixP->fx_r_type)
7672 {
7673 case BFD_RELOC_386_PLT32:
3e73aa7c 7674 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7675 /* Make the jump instruction point to the address of the operand. At
7676 runtime we merely add the offset to the actual PLT entry. */
7677 value = -4;
7678 break;
31312f95 7679
13ae64f3
JJ		 7680 case BFD_RELOC_386_TLS_GD:
7681 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7682 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7683 case BFD_RELOC_386_TLS_IE:
7684 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7685 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7686 case BFD_RELOC_X86_64_TLSGD:
7687 case BFD_RELOC_X86_64_TLSLD:
7688 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7689 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7690 value = 0; /* Fully resolved at runtime. No addend. */
7691 /* Fallthrough */
7692 case BFD_RELOC_386_TLS_LE:
7693 case BFD_RELOC_386_TLS_LDO_32:
7694 case BFD_RELOC_386_TLS_LE_32:
7695 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7696 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7697 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7698 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7699 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7700 break;
7701
67a4f2b7
AO		 7702 case BFD_RELOC_386_TLS_DESC_CALL:
7703 case BFD_RELOC_X86_64_TLSDESC_CALL:
7704 value = 0; /* Fully resolved at runtime. No addend. */
7705 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7706 fixP->fx_done = 0;
7707 return;
7708
00f7efb6
JJ		 7709 case BFD_RELOC_386_GOT32:
7710 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7711 value = 0; /* Fully resolved at runtime. No addend. */
7712 break;
47926f60
KH		 7713
7714 case BFD_RELOC_VTABLE_INHERIT:
7715 case BFD_RELOC_VTABLE_ENTRY:
7716 fixP->fx_done = 0;
94f592af 7717 return;
47926f60
KH		 7718
7719 default:
7720 break;
7721 }
7722#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7723 *valP = value;
f86103b7 7724#endif /* !defined (TE_Mach) */
3e73aa7c 7725
3e73aa7c 7726 /* Are we finished with this relocation now? */
c6682705 7727 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7728 fixP->fx_done = 1;
7729 else if (use_rela_relocations)
7730 {
7731 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7732 /* Remember value for tc_gen_reloc. */
7733 fixP->fx_addnumber = value;
3e73aa7c
JH		 7734 value = 0;
7735 }
f86103b7 7736
94f592af 7737 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7738}
252b5132 7739\f
252b5132 7740char *
499ac353 7741md_atof (int type, char *litP, int *sizeP)
252b5132 7742{
499ac353
NC		 7743 /* This outputs the LITTLENUMs in REVERSE order;
7744 in accord with the bigendian 386. */
7745 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7746}
7747\f
2d545b82 7748static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7749
252b5132 7750static char *
e3bb37b5 7751output_invalid (int c)
252b5132 7752{
3882b010 7753 if (ISPRINT (c))
f9f21a03
L		 7754 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7755 "'%c'", c);
252b5132 7756 else
f9f21a03 7757 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7758 "(0x%x)", (unsigned char) c);
252b5132
RH		 7759 return output_invalid_buf;
7760}
7761
af6bdddf 7762/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7763
7764static const reg_entry *
4d1bb795 7765parse_real_register (char *reg_string, char **end_op)
252b5132 7766{
af6bdddf
AM		 7767 char *s = reg_string;
7768 char *p;
252b5132
RH		 7769 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7770 const reg_entry *r;
7771
7772 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7773 if (*s == REGISTER_PREFIX)
7774 ++s;
7775
7776 if (is_space_char (*s))
7777 ++s;
7778
7779 p = reg_name_given;
af6bdddf 7780 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7781 {
7782 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7783 return (const reg_entry *) NULL;
7784 s++;
252b5132
RH		 7785 }
7786
6588847e
DN		 7787 /* For naked regs, make sure that we are not dealing with an identifier.
7788 This prevents confusing an identifier like `eax_var' with register
7789 `eax'. */
7790 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7791 return (const reg_entry *) NULL;
7792
af6bdddf 7793 *end_op = s;
252b5132
RH		 7794
7795 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7796
5f47d35b 7797 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7798 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7799 {
5f47d35b
AM		 7800 if (is_space_char (*s))
7801 ++s;
7802 if (*s == '(')
7803 {
af6bdddf 7804 ++s;
5f47d35b
AM		 7805 if (is_space_char (*s))
7806 ++s;
7807 if (*s >= '0' && *s <= '7')
7808 {
db557034 7809 int fpr = *s - '0';
af6bdddf 7810 ++s;
5f47d35b
AM		 7811 if (is_space_char (*s))
7812 ++s;
7813 if (*s == ')')
7814 {
7815 *end_op = s + 1;
db557034
AM		 7816 r = hash_find (reg_hash, "st(0)");
7817 know (r);
7818 return r + fpr;
5f47d35b 7819 }
5f47d35b 7820 }
47926f60 7821 /* We have "%st(" then garbage. */
5f47d35b
AM		 7822 return (const reg_entry *) NULL;
7823 }
7824 }
7825
a60de03c
JB		 7826 if (r == NULL || allow_pseudo_reg)
7827 return r;
7828
0dfbf9d7 7829 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7830 return (const reg_entry *) NULL;
7831
192dc9c6
JB		 7832 if ((r->reg_type.bitfield.reg32
7833 || r->reg_type.bitfield.sreg3
7834 || r->reg_type.bitfield.control
7835 || r->reg_type.bitfield.debug
7836 || r->reg_type.bitfield.test)
7837 && !cpu_arch_flags.bitfield.cpui386)
7838 return (const reg_entry *) NULL;
7839
7840 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7841 return (const reg_entry *) NULL;
7842
7843 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7844 return (const reg_entry *) NULL;
7845
40f12533
L		 7846 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7847 return (const reg_entry *) NULL;
7848
db51cc60 7849 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7850 if (!allow_index_reg
db51cc60
L		 7851 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7852 return (const reg_entry *) NULL;
7853
a60de03c
JB		 7854 if (((r->reg_flags & (RegRex64 | RegRex))
7855 || r->reg_type.bitfield.reg64)
40fb9820 7856 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7857 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7858 && flag_code != CODE_64BIT)
20f0a1fc 7859 return (const reg_entry *) NULL;
1ae00879 7860
b7240065
JB		 7861 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7862 return (const reg_entry *) NULL;
7863
252b5132
RH		 7864 return r;
7865}
4d1bb795
JB		 7866
7867/* REG_STRING starts *before* REGISTER_PREFIX. */
7868
7869static const reg_entry *
7870parse_register (char *reg_string, char **end_op)
7871{
7872 const reg_entry *r;
7873
7874 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7875 r = parse_real_register (reg_string, end_op);
7876 else
7877 r = NULL;
7878 if (!r)
7879 {
7880 char *save = input_line_pointer;
7881 char c;
7882 symbolS *symbolP;
7883
7884 input_line_pointer = reg_string;
7885 c = get_symbol_end ();
7886 symbolP = symbol_find (reg_string);
7887 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7888 {
7889 const expressionS *e = symbol_get_value_expression (symbolP);
7890
7891 know (e->X_op == O_register);
4eed87de 7892 know (e->X_add_number >= 0
c3fe08fa 7893 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7894 r = i386_regtab + e->X_add_number;
7895 *end_op = input_line_pointer;
7896 }
7897 *input_line_pointer = c;
7898 input_line_pointer = save;
7899 }
7900 return r;
7901}
7902
7903int
7904i386_parse_name (char *name, expressionS *e, char *nextcharP)
7905{
7906 const reg_entry *r;
7907 char *end = input_line_pointer;
7908
7909 *end = *nextcharP;
7910 r = parse_register (name, &input_line_pointer);
7911 if (r && end <= input_line_pointer)
7912 {
7913 *nextcharP = *input_line_pointer;
7914 *input_line_pointer = 0;
7915 e->X_op = O_register;
7916 e->X_add_number = r - i386_regtab;
7917 return 1;
7918 }
7919 input_line_pointer = end;
7920 *end = 0;
7921 return 0;
7922}
7923
7924void
7925md_operand (expressionS *e)
7926{
7927 if (*input_line_pointer == REGISTER_PREFIX)
7928 {
7929 char *end;
7930 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7931
7932 if (r)
7933 {
7934 e->X_op = O_register;
7935 e->X_add_number = r - i386_regtab;
7936 input_line_pointer = end;
7937 }
7938 }
7939}
7940
252b5132 7941\f
4cc782b5 7942#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7943const char *md_shortopts = "kVQ:sqn";
252b5132 7944#else
12b55ccc 7945const char *md_shortopts = "qn";
252b5132 7946#endif
6e0b89ee 7947
3e73aa7c 7948#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7949#define OPTION_64 (OPTION_MD_BASE + 1)
7950#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7951#define OPTION_MARCH (OPTION_MD_BASE + 3)
7952#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7953#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7954#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7955#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7956#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7957#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7958#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7959#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7960
99ad8390
NC		 7961struct option md_longopts[] =
7962{
3e73aa7c 7963 {"32", no_argument, NULL, OPTION_32},
99ad8390 7964#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7965 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7966#endif
b3b91714 7967 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7968 {"march", required_argument, NULL, OPTION_MARCH},
7969 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7970 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7971 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7972 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7973 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7974 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7975 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7976 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7977 {NULL, no_argument, NULL, 0}
7978};
7979size_t md_longopts_size = sizeof (md_longopts);
7980
7981int
9103f4f4 7982md_parse_option (int c, char *arg)
252b5132 7983{
9103f4f4 7984 unsigned int i;
6305a203 7985 char *arch, *next;
9103f4f4 7986
252b5132
RH		 7987 switch (c)
7988 {
12b55ccc
L		 7989 case 'n':
7990 optimize_align_code = 0;
7991 break;
7992
a38cf1db
AM		 7993 case 'q':
7994 quiet_warnings = 1;
252b5132
RH		 7995 break;
7996
7997#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7998 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7999 should be emitted or not. FIXME: Not implemented. */
8000 case 'Q':
252b5132
RH		 8001 break;
8002
8003 /* -V: SVR4 argument to print version ID. */
8004 case 'V':
8005 print_version_id ();
8006 break;
8007
a38cf1db
AM		 8008 /* -k: Ignore for FreeBSD compatibility. */
8009 case 'k':
252b5132 8010 break;
4cc782b5
ILT		 8011
8012 case 's':
8013 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8014 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8015 break;
99ad8390
NC		 8016#endif
8017#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 8018 case OPTION_64:
8019 {
8020 const char **list, **l;
8021
3e73aa7c
JH		 8022 list = bfd_target_list ();
8023 for (l = list; *l != NULL; l++)
8620418b 8024 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8025 || strcmp (*l, "coff-x86-64") == 0
8026 || strcmp (*l, "pe-x86-64") == 0
8027 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8028 {
8029 default_arch = "x86_64";
8030 break;
8031 }
3e73aa7c 8032 if (*l == NULL)
6e0b89ee 8033 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8034 free (list);
8035 }
8036 break;
8037#endif
252b5132 8038
6e0b89ee
AM		 8039 case OPTION_32:
8040 default_arch = "i386";
8041 break;
8042
b3b91714
AM		 8043 case OPTION_DIVIDE:
8044#ifdef SVR4_COMMENT_CHARS
8045 {
8046 char *n, *t;
8047 const char *s;
8048
8049 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8050 t = n;
8051 for (s = i386_comment_chars; *s != '\0'; s++)
8052 if (*s != '/')
8053 *t++ = *s;
8054 *t = '\0';
8055 i386_comment_chars = n;
8056 }
8057#endif
8058 break;
8059
9103f4f4 8060 case OPTION_MARCH:
6305a203
L		 8061 arch = xstrdup (arg);
8062 do
9103f4f4 8063 {
6305a203
L		 8064 if (*arch == '.')
8065 as_fatal (_("Invalid -march= option: `%s'"), arg);
8066 next = strchr (arch, '+');
8067 if (next)
8068 *next++ = '\0';
8069 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 8070 {
6305a203 8071 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 8072 {
6305a203
L		 8073 /* Processor. */
8074 cpu_arch_name = cpu_arch[i].name;
8075 cpu_sub_arch_name = NULL;
8076 cpu_arch_flags = cpu_arch[i].flags;
8077 cpu_arch_isa = cpu_arch[i].type;
8078 cpu_arch_isa_flags = cpu_arch[i].flags;
8079 if (!cpu_arch_tune_set)
8080 {
8081 cpu_arch_tune = cpu_arch_isa;
8082 cpu_arch_tune_flags = cpu_arch_isa_flags;
8083 }
8084 break;
8085 }
8086 else if (*cpu_arch [i].name == '.'
8087 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8088 {
8089 /* ISA entension. */
8090 i386_cpu_flags flags;
8091 flags = cpu_flags_or (cpu_arch_flags,
8092 cpu_arch[i].flags);
0dfbf9d7 8093 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8094 {
8095 if (cpu_sub_arch_name)
8096 {
8097 char *name = cpu_sub_arch_name;
8098 cpu_sub_arch_name = concat (name,
8099 cpu_arch[i].name,
1bf57e9f 8100 (const char *) NULL);
6305a203
L		 8101 free (name);
8102 }
8103 else
8104 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8105 cpu_arch_flags = flags;
8106 }
8107 break;
ccc9c027 8108 }
9103f4f4 8109 }
6305a203
L		 8110
8111 if (i >= ARRAY_SIZE (cpu_arch))
8112 as_fatal (_("Invalid -march= option: `%s'"), arg);
8113
8114 arch = next;
9103f4f4 8115 }
6305a203 8116 while (next != NULL );
9103f4f4
L		 8117 break;
8118
8119 case OPTION_MTUNE:
8120 if (*arg == '.')
8121 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8122 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8123 {
8124 if (strcmp (arg, cpu_arch [i].name) == 0)
8125 {
ccc9c027 8126 cpu_arch_tune_set = 1;
9103f4f4
L		 8127 cpu_arch_tune = cpu_arch [i].type;
8128 cpu_arch_tune_flags = cpu_arch[i].flags;
8129 break;
8130 }
8131 }
8132 if (i >= ARRAY_SIZE (cpu_arch))
8133 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8134 break;
8135
1efbbeb4
L		 8136 case OPTION_MMNEMONIC:
8137 if (strcasecmp (arg, "att") == 0)
8138 intel_mnemonic = 0;
8139 else if (strcasecmp (arg, "intel") == 0)
8140 intel_mnemonic = 1;
8141 else
8142 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8143 break;
8144
8145 case OPTION_MSYNTAX:
8146 if (strcasecmp (arg, "att") == 0)
8147 intel_syntax = 0;
8148 else if (strcasecmp (arg, "intel") == 0)
8149 intel_syntax = 1;
8150 else
8151 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8152 break;
8153
8154 case OPTION_MINDEX_REG:
8155 allow_index_reg = 1;
8156 break;
8157
8158 case OPTION_MNAKED_REG:
8159 allow_naked_reg = 1;
8160 break;
8161
8162 case OPTION_MOLD_GCC:
8163 old_gcc = 1;
1efbbeb4
L		 8164 break;
8165
c0f3af97
L		 8166 case OPTION_MSSE2AVX:
8167 sse2avx = 1;
8168 break;
8169
daf50ae7
L		 8170 case OPTION_MSSE_CHECK:
8171 if (strcasecmp (arg, "error") == 0)
8172 sse_check = sse_check_error;
8173 else if (strcasecmp (arg, "warning") == 0)
8174 sse_check = sse_check_warning;
8175 else if (strcasecmp (arg, "none") == 0)
8176 sse_check = sse_check_none;
8177 else
8178 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8179 break;
8180
252b5132
RH		 8181 default:
8182 return 0;
8183 }
8184 return 1;
8185}
8186
8187void
8188md_show_usage (stream)
8189 FILE *stream;
8190{
4cc782b5
ILT		 8191#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8192 fprintf (stream, _("\
a38cf1db
AM		 8193 -Q ignored\n\
8194 -V print assembler version number\n\
b3b91714
AM		 8195 -k ignored\n"));
8196#endif
8197 fprintf (stream, _("\
12b55ccc 8198 -n Do not optimize code alignment\n\
b3b91714
AM		 8199 -q quieten some warnings\n"));
8200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8201 fprintf (stream, _("\
a38cf1db 8202 -s ignored\n"));
b3b91714 8203#endif
751d281c
L		 8204#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8205 fprintf (stream, _("\
8206 --32/--64 generate 32bit/64bit code\n"));
8207#endif
b3b91714
AM		 8208#ifdef SVR4_COMMENT_CHARS
8209 fprintf (stream, _("\
8210 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8211#else
8212 fprintf (stream, _("\
b3b91714 8213 --divide ignored\n"));
4cc782b5 8214#endif
9103f4f4 8215 fprintf (stream, _("\
6305a203
L		 8216 -march=CPU[,+EXTENSION...]\n\
8217 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8218 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8219 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8220 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8221 generic32, generic64\n\
599121aa
L		 8222 EXTENSION is combination of:\n\
8223 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695 8224 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2
L		 8225 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8226 sse5, svme, abm, padlock\n"));
6305a203 8227 fprintf (stream, _("\
2cb4f3d5
L		 8228 -mtune=CPU optimize for CPU, CPU is one of:\n\
8229 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8230 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8231 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8232 generic32, generic64\n"));
ba104c83 8233 fprintf (stream, _("\
c0f3af97
L		 8234 -msse2avx encode SSE instructions with VEX prefix\n"));
8235 fprintf (stream, _("\
daf50ae7
L		 8236 -msse-check=[none|error|warning]\n\
8237 check SSE instructions\n"));
8238 fprintf (stream, _("\
ba104c83
L		 8239 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8240 fprintf (stream, _("\
8241 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8242 fprintf (stream, _("\
8243 -mindex-reg support pseudo index registers\n"));
8244 fprintf (stream, _("\
8245 -mnaked-reg don't require `%%' prefix for registers\n"));
8246 fprintf (stream, _("\
8247 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8248}
8249
3e73aa7c 8250#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8251 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8252
8253/* Pick the target format to use. */
8254
47926f60 8255const char *
e3bb37b5 8256i386_target_format (void)
252b5132 8257{
3e73aa7c 8258 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8259 {
8260 set_code_flag (CODE_64BIT);
0dfbf9d7 8261 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8262 {
8263 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8264 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8265 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8266 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8267 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8268 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8269 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8270 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8271 cpu_arch_isa_flags.bitfield.cpusse = 1;
8272 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8273 }
0dfbf9d7 8274 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8275 {
8276 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8277 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8278 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8279 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8280 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8281 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8282 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8283 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8284 cpu_arch_tune_flags.bitfield.cpusse = 1;
8285 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8286 }
9103f4f4 8287 }
3e73aa7c 8288 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8289 {
8290 set_code_flag (CODE_32BIT);
0dfbf9d7 8291 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8292 {
8293 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8294 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8295 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8296 }
0dfbf9d7 8297 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8298 {
8299 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8300 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8301 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8302 }
9103f4f4 8303 }
3e73aa7c
JH		 8304 else
8305 as_fatal (_("Unknown architecture"));
252b5132
RH		 8306 switch (OUTPUT_FLAVOR)
8307 {
872ce6ff
L		 8308#ifdef TE_PEP
8309 case bfd_target_coff_flavour:
b01ee69d 8310 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "pe-i386";
872ce6ff
L		 8311 break;
8312#endif
4c63da97
AM		 8313#ifdef OBJ_MAYBE_AOUT
8314 case bfd_target_aout_flavour:
47926f60 8315 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8316#endif
8317#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8318 case bfd_target_coff_flavour:
8319 return "coff-i386";
4c63da97 8320#endif
3e73aa7c 8321#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8322 case bfd_target_elf_flavour:
3e73aa7c 8323 {
e5cb08ac 8324 if (flag_code == CODE_64BIT)
4fa24527
JB		 8325 {
8326 object_64bit = 1;
8327 use_rela_relocations = 1;
8328 }
9d7cbccd 8329 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8330 }
4c63da97 8331#endif
252b5132
RH		 8332 default:
8333 abort ();
8334 return NULL;
8335 }
8336}
8337
47926f60 8338#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8339
8340#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8341void
8342i386_elf_emit_arch_note (void)
a847613f 8343{
718ddfc0 8344 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8345 {
8346 char *p;
8347 asection *seg = now_seg;
8348 subsegT subseg = now_subseg;
8349 Elf_Internal_Note i_note;
8350 Elf_External_Note e_note;
8351 asection *note_secp;
8352 int len;
8353
8354 /* Create the .note section. */
8355 note_secp = subseg_new (".note", 0);
8356 bfd_set_section_flags (stdoutput,
8357 note_secp,
8358 SEC_HAS_CONTENTS | SEC_READONLY);
8359
8360 /* Process the arch string. */
8361 len = strlen (cpu_arch_name);
8362
8363 i_note.namesz = len + 1;
8364 i_note.descsz = 0;
8365 i_note.type = NT_ARCH;
8366 p = frag_more (sizeof (e_note.namesz));
8367 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8368 p = frag_more (sizeof (e_note.descsz));
8369 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8370 p = frag_more (sizeof (e_note.type));
8371 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8372 p = frag_more (len + 1);
8373 strcpy (p, cpu_arch_name);
8374
8375 frag_align (2, 0, 0);
8376
8377 subseg_set (seg, subseg);
8378 }
8379}
8380#endif
252b5132 8381\f
252b5132
RH		 8382symbolS *
8383md_undefined_symbol (name)
8384 char *name;
8385{
18dc2407
ILT		 8386 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8387 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8388 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8389 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8390 {
8391 if (!GOT_symbol)
8392 {
8393 if (symbol_find (name))
8394 as_bad (_("GOT already in symbol table"));
8395 GOT_symbol = symbol_new (name, undefined_section,
8396 (valueT) 0, &zero_address_frag);
8397 };
8398 return GOT_symbol;
8399 }
252b5132
RH		 8400 return 0;
8401}
8402
8403/* Round up a section size to the appropriate boundary. */
47926f60 8404
252b5132
RH		 8405valueT
8406md_section_align (segment, size)
ab9da554 8407 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8408 valueT size;
8409{
4c63da97
AM		 8410#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8411 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8412 {
8413 /* For a.out, force the section size to be aligned. If we don't do
8414 this, BFD will align it for us, but it will not write out the
8415 final bytes of the section. This may be a bug in BFD, but it is
8416 easier to fix it here since that is how the other a.out targets
8417 work. */
8418 int align;
8419
8420 align = bfd_get_section_alignment (stdoutput, segment);
8421 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8422 }
252b5132
RH		 8423#endif
8424
8425 return size;
8426}
8427
8428/* On the i386, PC-relative offsets are relative to the start of the
8429 next instruction. That is, the address of the offset, plus its
8430 size, since the offset is always the last part of the insn. */
8431
8432long
e3bb37b5 8433md_pcrel_from (fixS *fixP)
252b5132
RH		 8434{
8435 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8436}
8437
8438#ifndef I386COFF
8439
8440static void
e3bb37b5 8441s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8442{
29b0f896 8443 int temp;
252b5132 8444
8a75718c
JB		 8445#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8446 if (IS_ELF)
8447 obj_elf_section_change_hook ();
8448#endif
252b5132
RH		 8449 temp = get_absolute_expression ();
8450 subseg_set (bss_section, (subsegT) temp);
8451 demand_empty_rest_of_line ();
8452}
8453
8454#endif
8455
252b5132 8456void
e3bb37b5 8457i386_validate_fix (fixS *fixp)
252b5132
RH		 8458{
8459 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8460 {
23df1078
JH		 8461 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8462 {
4fa24527 8463 if (!object_64bit)
23df1078
JH		 8464 abort ();
8465 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8466 }
8467 else
8468 {
4fa24527 8469 if (!object_64bit)
d6ab8113
JB		 8470 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8471 else
8472 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8473 }
252b5132
RH		 8474 fixp->fx_subsy = 0;
8475 }
8476}
8477
252b5132
RH		 8478arelent *
8479tc_gen_reloc (section, fixp)
ab9da554 8480 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8481 fixS *fixp;
8482{
8483 arelent *rel;
8484 bfd_reloc_code_real_type code;
8485
8486 switch (fixp->fx_r_type)
8487 {
3e73aa7c
JH		 8488 case BFD_RELOC_X86_64_PLT32:
8489 case BFD_RELOC_X86_64_GOT32:
8490 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8491 case BFD_RELOC_386_PLT32:
8492 case BFD_RELOC_386_GOT32:
8493 case BFD_RELOC_386_GOTOFF:
8494 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8495 case BFD_RELOC_386_TLS_GD:
8496 case BFD_RELOC_386_TLS_LDM:
8497 case BFD_RELOC_386_TLS_LDO_32:
8498 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8499 case BFD_RELOC_386_TLS_IE:
8500 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8501 case BFD_RELOC_386_TLS_LE_32:
8502 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8503 case BFD_RELOC_386_TLS_GOTDESC:
8504 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8505 case BFD_RELOC_X86_64_TLSGD:
8506 case BFD_RELOC_X86_64_TLSLD:
8507 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8508 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8509 case BFD_RELOC_X86_64_GOTTPOFF:
8510 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8511 case BFD_RELOC_X86_64_TPOFF64:
8512 case BFD_RELOC_X86_64_GOTOFF64:
8513 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8514 case BFD_RELOC_X86_64_GOT64:
8515 case BFD_RELOC_X86_64_GOTPCREL64:
8516 case BFD_RELOC_X86_64_GOTPC64:
8517 case BFD_RELOC_X86_64_GOTPLT64:
8518 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8519 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8520 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8521 case BFD_RELOC_RVA:
8522 case BFD_RELOC_VTABLE_ENTRY:
8523 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8524#ifdef TE_PE
8525 case BFD_RELOC_32_SECREL:
8526#endif
252b5132
RH		 8527 code = fixp->fx_r_type;
8528 break;
dbbaec26
L		 8529 case BFD_RELOC_X86_64_32S:
8530 if (!fixp->fx_pcrel)
8531 {
8532 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8533 code = fixp->fx_r_type;
8534 break;
8535 }
252b5132 8536 default:
93382f6d 8537 if (fixp->fx_pcrel)
252b5132 8538 {
93382f6d
AM		 8539 switch (fixp->fx_size)
8540 {
8541 default:
b091f402
AM		 8542 as_bad_where (fixp->fx_file, fixp->fx_line,
8543 _("can not do %d byte pc-relative relocation"),
8544 fixp->fx_size);
93382f6d
AM		 8545 code = BFD_RELOC_32_PCREL;
8546 break;
8547 case 1: code = BFD_RELOC_8_PCREL; break;
8548 case 2: code = BFD_RELOC_16_PCREL; break;
8549 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8550#ifdef BFD64
8551 case 8: code = BFD_RELOC_64_PCREL; break;
8552#endif
93382f6d
AM		 8553 }
8554 }
8555 else
8556 {
8557 switch (fixp->fx_size)
8558 {
8559 default:
b091f402
AM		 8560 as_bad_where (fixp->fx_file, fixp->fx_line,
8561 _("can not do %d byte relocation"),
8562 fixp->fx_size);
93382f6d
AM		 8563 code = BFD_RELOC_32;
8564 break;
8565 case 1: code = BFD_RELOC_8; break;
8566 case 2: code = BFD_RELOC_16; break;
8567 case 4: code = BFD_RELOC_32; break;
937149dd 8568#ifdef BFD64
3e73aa7c 8569 case 8: code = BFD_RELOC_64; break;
937149dd 8570#endif
93382f6d 8571 }
252b5132
RH		 8572 }
8573 break;
8574 }
252b5132 8575
d182319b
JB		 8576 if ((code == BFD_RELOC_32
8577 || code == BFD_RELOC_32_PCREL
8578 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8579 && GOT_symbol
8580 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8581 {
4fa24527 8582 if (!object_64bit)
d6ab8113
JB		 8583 code = BFD_RELOC_386_GOTPC;
8584 else
8585 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8586 }
7b81dfbb
AJ		 8587 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8588 && GOT_symbol
8589 && fixp->fx_addsy == GOT_symbol)
8590 {
8591 code = BFD_RELOC_X86_64_GOTPC64;
8592 }
252b5132
RH		 8593
8594 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8595 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8596 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8597
8598 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8599
3e73aa7c
JH		 8600 if (!use_rela_relocations)
8601 {
8602 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8603 vtable entry to be used in the relocation's section offset. */
8604 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8605 rel->address = fixp->fx_offset;
252b5132 8606
c6682705 8607 rel->addend = 0;
3e73aa7c
JH		 8608 }
8609 /* Use the rela in 64bit mode. */
252b5132 8610 else
3e73aa7c 8611 {
062cd5e7
AS		 8612 if (!fixp->fx_pcrel)
8613 rel->addend = fixp->fx_offset;
8614 else
8615 switch (code)
8616 {
8617 case BFD_RELOC_X86_64_PLT32:
8618 case BFD_RELOC_X86_64_GOT32:
8619 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8620 case BFD_RELOC_X86_64_TLSGD:
8621 case BFD_RELOC_X86_64_TLSLD:
8622 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8623 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8624 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8625 rel->addend = fixp->fx_offset - fixp->fx_size;
8626 break;
8627 default:
8628 rel->addend = (section->vma
8629 - fixp->fx_size
8630 + fixp->fx_addnumber
8631 + md_pcrel_from (fixp));
8632 break;
8633 }
3e73aa7c
JH		 8634 }
8635
252b5132
RH		 8636 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8637 if (rel->howto == NULL)
8638 {
8639 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8640 _("cannot represent relocation type %s"),
252b5132
RH		 8641 bfd_get_reloc_code_name (code));
8642 /* Set howto to a garbage value so that we can keep going. */
8643 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8644 assert (rel->howto != NULL);
8645 }
8646
8647 return rel;
8648}
8649
64a0c779
DN		 8650\f
8651/* Parse operands using Intel syntax. This implements a recursive descent
8652 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8653 Programmer's Guide.
8654
8655 FIXME: We do not recognize the full operand grammar defined in the MASM
8656 documentation. In particular, all the structure/union and
8657 high-level macro operands are missing.
8658
8659 Uppercase words are terminals, lower case words are non-terminals.
8660 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8661 bars '|' denote choices. Most grammar productions are implemented in
8662 functions called 'intel_<production>'.
8663
8664 Initial production is 'expr'.
8665
9306ca4a 8666 addOp + | -
64a0c779
DN		 8667
8668 alpha [a-zA-Z]
8669
9306ca4a
JB		 8670 binOp & | AND | \| | OR | ^ | XOR
8671
64a0c779
DN		 8672 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8673
8674 constant digits [[ radixOverride ]]
8675
c0f3af97 8676 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8677
8678 digits decdigit
b77a7acd
AJ		 8679 | digits decdigit
8680 | digits hexdigit
64a0c779
DN		 8681
8682 decdigit [0-9]
8683
9306ca4a
JB		 8684 e04 e04 addOp e05
8685 | e05
8686
8687 e05 e05 binOp e06
b77a7acd 8688 | e06
64a0c779
DN		 8689
8690 e06 e06 mulOp e09
b77a7acd 8691 | e09
64a0c779
DN		 8692
8693 e09 OFFSET e10
a724f0f4
JB		 8694 | SHORT e10
8695 | + e10
8696 | - e10
9306ca4a
JB		 8697 | ~ e10
8698 | NOT e10
64a0c779
DN		 8699 | e09 PTR e10
8700 | e09 : e10
8701 | e10
8702
8703 e10 e10 [ expr ]
b77a7acd 8704 | e11
64a0c779
DN		 8705
8706 e11 ( expr )
b77a7acd 8707 | [ expr ]
64a0c779
DN		 8708 | constant
8709 | dataType
8710 | id
8711 | $
8712 | register
8713
a724f0f4 8714 => expr expr cmpOp e04
9306ca4a 8715 | e04
64a0c779
DN		 8716
8717 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8718 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8719
8720 hexdigit a | b | c | d | e | f
b77a7acd 8721 | A | B | C | D | E | F
64a0c779
DN		 8722
8723 id alpha
b77a7acd 8724 | id alpha
64a0c779
DN		 8725 | id decdigit
8726
9306ca4a 8727 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8728
8729 quote " | '
8730
8731 register specialRegister
b77a7acd 8732 | gpRegister
64a0c779
DN		 8733 | byteRegister
8734
8735 segmentRegister CS | DS | ES | FS | GS | SS
8736
9306ca4a 8737 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8738 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8739 | TR3 | TR4 | TR5 | TR6 | TR7
8740
64a0c779
DN		 8741 We simplify the grammar in obvious places (e.g., register parsing is
8742 done by calling parse_register) and eliminate immediate left recursion
8743 to implement a recursive-descent parser.
8744
a724f0f4
JB		 8745 expr e04 expr'
8746
8747 expr' cmpOp e04 expr'
8748 | Empty
9306ca4a
JB		 8749
8750 e04 e05 e04'
8751
8752 e04' addOp e05 e04'
8753 | Empty
64a0c779
DN		 8754
8755 e05 e06 e05'
8756
9306ca4a 8757 e05' binOp e06 e05'
b77a7acd 8758 | Empty
64a0c779
DN		 8759
8760 e06 e09 e06'
8761
8762 e06' mulOp e09 e06'
b77a7acd 8763 | Empty
64a0c779
DN		 8764
8765 e09 OFFSET e10 e09'
a724f0f4
JB		 8766 | SHORT e10'
8767 | + e10'
8768 | - e10'
8769 | ~ e10'
8770 | NOT e10'
b77a7acd 8771 | e10 e09'
64a0c779
DN		 8772
8773 e09' PTR e10 e09'
b77a7acd 8774 | : e10 e09'
64a0c779
DN		 8775 | Empty
8776
8777 e10 e11 e10'
8778
8779 e10' [ expr ] e10'
b77a7acd 8780 | Empty
64a0c779
DN		 8781
8782 e11 ( expr )
b77a7acd 8783 | [ expr ]
64a0c779
DN		 8784 | BYTE
8785 | WORD
8786 | DWORD
9306ca4a 8787 | FWORD
64a0c779 8788 | QWORD
9306ca4a
JB		 8789 | TBYTE
8790 | OWORD
8791 | XMMWORD
c0f3af97 8792 | YMMWORD
64a0c779
DN		 8793 | .
8794 | $
8795 | register
8796 | id
8797 | constant */
8798
8799/* Parsing structure for the intel syntax parser. Used to implement the
8800 semantic actions for the operand grammar. */
8801struct intel_parser_s
8802 {
8803 char *op_string; /* The string being parsed. */
8804 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8805 int op_modifier; /* Operand modifier. */
64a0c779 8806 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8807 int in_offset; /* >=1 if parsing operand of offset. */
8808 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8809 const reg_entry *reg; /* Last register reference found. */
8810 char *disp; /* Displacement string being built. */
a724f0f4 8811 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8812 };
8813
8814static struct intel_parser_s intel_parser;
8815
8816/* Token structure for parsing intel syntax. */
8817struct intel_token
8818 {
8819 int code; /* Token code. */
8820 const reg_entry *reg; /* Register entry for register tokens. */
8821 char *str; /* String representation. */
8822 };
8823
8824static struct intel_token cur_token, prev_token;
8825
50705ef4
AM		 8826/* Token codes for the intel parser. Since T_SHORT is already used
8827 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8828#define T_NIL -1
8829#define T_CONST 1
8830#define T_REG 2
8831#define T_BYTE 3
8832#define T_WORD 4
9306ca4a
JB		 8833#define T_DWORD 5
8834#define T_FWORD 6
8835#define T_QWORD 7
8836#define T_TBYTE 8
8837#define T_XMMWORD 9
50705ef4 8838#undef T_SHORT
9306ca4a
JB		 8839#define T_SHORT 10
8840#define T_OFFSET 11
8841#define T_PTR 12
8842#define T_ID 13
8843#define T_SHL 14
8844#define T_SHR 15
c0f3af97 8845#define T_YMMWORD 16
64a0c779
DN		 8846
8847/* Prototypes for intel parser functions. */
e3bb37b5
L		 8848static int intel_match_token (int);
8849static void intel_putback_token (void);
8850static void intel_get_token (void);
8851static int intel_expr (void);
8852static int intel_e04 (void);
8853static int intel_e05 (void);
8854static int intel_e06 (void);
8855static int intel_e09 (void);
8856static int intel_e10 (void);
8857static int intel_e11 (void);
64a0c779 8858
64a0c779 8859static int
e3bb37b5 8860i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8861{
8862 int ret;
8863 char *p;
fc0763e6
JB		 8864 const reg_entry *final_base = i.base_reg;
8865 const reg_entry *final_index = i.index_reg;
64a0c779 8866
a724f0f4
JB		 8867 p = intel_parser.op_string = xstrdup (operand_string);
8868 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8869
8870 for (;;)
64a0c779 8871 {
a724f0f4
JB		 8872 /* Initialize token holders. */
8873 cur_token.code = prev_token.code = T_NIL;
8874 cur_token.reg = prev_token.reg = NULL;
8875 cur_token.str = prev_token.str = NULL;
8876
8877 /* Initialize parser structure. */
8878 intel_parser.got_a_float = got_a_float;
8879 intel_parser.op_modifier = 0;
8880 intel_parser.is_mem = 0;
8881 intel_parser.in_offset = 0;
8882 intel_parser.in_bracket = 0;
8883 intel_parser.reg = NULL;
8884 intel_parser.disp[0] = '\0';
8885 intel_parser.next_operand = NULL;
8886
fc0763e6
JB		 8887 i.base_reg = NULL;
8888 i.index_reg = NULL;
8889
a724f0f4
JB		 8890 /* Read the first token and start the parser. */
8891 intel_get_token ();
8892 ret = intel_expr ();
8893
8894 if (!ret)
8895 break;
8896
9306ca4a
JB		 8897 if (cur_token.code != T_NIL)
8898 {
8899 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8900 current_templates->start->name, cur_token.str);
8901 ret = 0;
8902 }
64a0c779
DN		 8903 /* If we found a memory reference, hand it over to i386_displacement
8904 to fill in the rest of the operand fields. */
9306ca4a 8905 else if (intel_parser.is_mem)
64a0c779
DN		 8906 {
8907 if ((i.mem_operands == 1
40fb9820 8908 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8909 || i.mem_operands == 2)
8910 {
8911 as_bad (_("too many memory references for '%s'"),
8912 current_templates->start->name);
8913 ret = 0;
8914 }
8915 else
8916 {
8917 char *s = intel_parser.disp;
64a0c779 8918
a724f0f4
JB		 8919 if (!quiet_warnings && intel_parser.is_mem < 0)
8920 /* See the comments in intel_bracket_expr. */
8921 as_warn (_("Treating `%s' as memory reference"), operand_string);
8922
64a0c779
DN		 8923 /* Add the displacement expression. */
8924 if (*s != '\0')
a4622f40
AM		 8925 ret = i386_displacement (s, s + strlen (s));
8926 if (ret)
a724f0f4
JB		 8927 {
8928 /* Swap base and index in 16-bit memory operands like
8929 [si+bx]. Since i386_index_check is also used in AT&T
8930 mode we have to do that here. */
8931 if (i.base_reg
8932 && i.index_reg
40fb9820
L		 8933 && i.base_reg->reg_type.bitfield.reg16
8934 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8935 && i.base_reg->reg_num >= 6
8936 && i.index_reg->reg_num < 6)
8937 {
8938 const reg_entry *base = i.index_reg;
8939
8940 i.index_reg = i.base_reg;
8941 i.base_reg = base;
8942 }
8943 ret = i386_index_check (operand_string);
8944 }
fc0763e6
JB		 8945 if (ret)
8946 {
8947 i.types[this_operand].bitfield.mem = 1;
8948 i.mem_operands++;
8949 }
64a0c779
DN		 8950 }
8951 }
8952
8953 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8954 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8955 || intel_parser.reg == NULL)
b7240065
JB		 8956 {
8957 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8958 {
8959 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8960 as_warn (_("Segment override ignored"));
8961 i.seg[i.mem_operands] = NULL;
8962 }
8963 ret = i386_immediate (intel_parser.disp);
8964 }
a724f0f4 8965
fc0763e6
JB		 8966 if (!final_base && !final_index)
8967 {
8968 final_base = i.base_reg;
8969 final_index = i.index_reg;
8970 }
8971
a724f0f4 8972 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8973 ret = 0;
a724f0f4
JB		 8974 if (!ret || !intel_parser.next_operand)
8975 break;
8976 intel_parser.op_string = intel_parser.next_operand;
8977 this_operand = i.operands++;
7d5e4556 8978 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8979 }
8980
8981 free (p);
8982 free (intel_parser.disp);
8983
fc0763e6
JB		 8984 if (final_base || final_index)
8985 {
8986 i.base_reg = final_base;
8987 i.index_reg = final_index;
8988 }
8989
64a0c779
DN		 8990 return ret;
8991}
8992
a724f0f4
JB		 8993#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8994
8995/* expr e04 expr'
8996
8997 expr' cmpOp e04 expr'
8998 | Empty */
64a0c779 8999static int
e3bb37b5 9000intel_expr (void)
64a0c779 9001{
a724f0f4
JB		 9002 /* XXX Implement the comparison operators. */
9003 return intel_e04 ();
9306ca4a
JB		 9004}
9005
a724f0f4 9006/* e04 e05 e04'
9306ca4a 9007
a724f0f4 9008 e04' addOp e05 e04'
9306ca4a
JB		 9009 | Empty */
9010static int
e3bb37b5 9011intel_e04 (void)
9306ca4a 9012{
a724f0f4 9013 int nregs = -1;
9306ca4a 9014
a724f0f4 9015 for (;;)
9306ca4a 9016 {
a724f0f4
JB		 9017 if (!intel_e05())
9018 return 0;
9306ca4a 9019
a724f0f4
JB		 9020 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9021 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 9022
a724f0f4
JB		 9023 if (cur_token.code == '+')
9024 nregs = -1;
9025 else if (cur_token.code == '-')
9026 nregs = NUM_ADDRESS_REGS;
9027 else
9028 return 1;
64a0c779 9029
a724f0f4
JB		 9030 strcat (intel_parser.disp, cur_token.str);
9031 intel_match_token (cur_token.code);
9032 }
64a0c779
DN		 9033}
9034
64a0c779
DN		 9035/* e05 e06 e05'
9036
9306ca4a 9037 e05' binOp e06 e05'
64a0c779
DN		 9038 | Empty */
9039static int
e3bb37b5 9040intel_e05 (void)
64a0c779 9041{
a724f0f4 9042 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9043
a724f0f4 9044 for (;;)
64a0c779 9045 {
a724f0f4
JB		 9046 if (!intel_e06())
9047 return 0;
9048
4eed87de
AM		 9049 if (cur_token.code == '&'
9050 || cur_token.code == '|'
9051 || cur_token.code == '^')
a724f0f4
JB		 9052 {
9053 char str[2];
9054
9055 str[0] = cur_token.code;
9056 str[1] = 0;
9057 strcat (intel_parser.disp, str);
9058 }
9059 else
9060 break;
9306ca4a 9061
64a0c779
DN		 9062 intel_match_token (cur_token.code);
9063
a724f0f4
JB		 9064 if (nregs < 0)
9065 nregs = ~nregs;
64a0c779 9066 }
a724f0f4
JB		 9067 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9068 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
9069 return 1;
4a1805b1 9070}
64a0c779
DN		 9071
9072/* e06 e09 e06'
9073
9074 e06' mulOp e09 e06'
b77a7acd 9075 | Empty */
64a0c779 9076static int
e3bb37b5 9077intel_e06 (void)
64a0c779 9078{
a724f0f4 9079 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9080
a724f0f4 9081 for (;;)
64a0c779 9082 {
a724f0f4
JB		 9083 if (!intel_e09())
9084 return 0;
9306ca4a 9085
4eed87de
AM		 9086 if (cur_token.code == '*'
9087 || cur_token.code == '/'
9088 || cur_token.code == '%')
a724f0f4
JB		 9089 {
9090 char str[2];
9306ca4a 9091
a724f0f4
JB		 9092 str[0] = cur_token.code;
9093 str[1] = 0;
9094 strcat (intel_parser.disp, str);
9095 }
9096 else if (cur_token.code == T_SHL)
9097 strcat (intel_parser.disp, "<<");
9098 else if (cur_token.code == T_SHR)
9099 strcat (intel_parser.disp, ">>");
9100 else
9101 break;
9306ca4a 9102
64e74474 9103 intel_match_token (cur_token.code);
64a0c779 9104
a724f0f4
JB		 9105 if (nregs < 0)
9106 nregs = ~nregs;
64a0c779 9107 }
a724f0f4
JB		 9108 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9109 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9110 return 1;
64a0c779
DN		 9111}
9112
a724f0f4
JB		 9113/* e09 OFFSET e09
9114 | SHORT e09
9115 | + e09
9116 | - e09
9117 | ~ e09
9118 | NOT e09
9306ca4a
JB		 9119 | e10 e09'
9120
64a0c779 9121 e09' PTR e10 e09'
b77a7acd 9122 | : e10 e09'
64a0c779
DN		 9123 | Empty */
9124static int
e3bb37b5 9125intel_e09 (void)
64a0c779 9126{
a724f0f4
JB		 9127 int nregs = ~NUM_ADDRESS_REGS;
9128 int in_offset = 0;
9129
9130 for (;;)
64a0c779 9131 {
a724f0f4
JB		 9132 /* Don't consume constants here. */
9133 if (cur_token.code == '+' || cur_token.code == '-')
9134 {
9135 /* Need to look one token ahead - if the next token
9136 is a constant, the current token is its sign. */
9137 int next_code;
9138
9139 intel_match_token (cur_token.code);
9140 next_code = cur_token.code;
9141 intel_putback_token ();
9142 if (next_code == T_CONST)
9143 break;
9144 }
9145
9146 /* e09 OFFSET e09 */
9147 if (cur_token.code == T_OFFSET)
9148 {
9149 if (!in_offset++)
9150 ++intel_parser.in_offset;
9151 }
9152
9153 /* e09 SHORT e09 */
9154 else if (cur_token.code == T_SHORT)
9155 intel_parser.op_modifier |= 1 << T_SHORT;
9156
9157 /* e09 + e09 */
9158 else if (cur_token.code == '+')
9159 strcat (intel_parser.disp, "+");
9160
9161 /* e09 - e09
9162 | ~ e09
9163 | NOT e09 */
9164 else if (cur_token.code == '-' || cur_token.code == '~')
9165 {
9166 char str[2];
64a0c779 9167
a724f0f4
JB		 9168 if (nregs < 0)
9169 nregs = ~nregs;
9170 str[0] = cur_token.code;
9171 str[1] = 0;
9172 strcat (intel_parser.disp, str);
9173 }
9174
9175 /* e09 e10 e09' */
9176 else
9177 break;
9178
9179 intel_match_token (cur_token.code);
64a0c779
DN		 9180 }
9181
a724f0f4 9182 for (;;)
9306ca4a 9183 {
a724f0f4
JB		 9184 if (!intel_e10 ())
9185 return 0;
9306ca4a 9186
a724f0f4
JB		 9187 /* e09' PTR e10 e09' */
9188 if (cur_token.code == T_PTR)
9189 {
9190 char suffix;
9306ca4a 9191
a724f0f4 9192 if (prev_token.code == T_BYTE)
7d5e4556
L		 9193 {
9194 suffix = BYTE_MNEM_SUFFIX;
9195 i.types[this_operand].bitfield.byte = 1;
9196 }
9306ca4a 9197
a724f0f4
JB		 9198 else if (prev_token.code == T_WORD)
9199 {
34b772a6
JB		 9200 if ((current_templates->start->name[0] == 'l'
9201 && current_templates->start->name[2] == 's'
9202 && current_templates->start->name[3] == 0)
9203 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9204 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9205 else if (intel_parser.got_a_float == 2) /* "fi..." */
9206 suffix = SHORT_MNEM_SUFFIX;
9207 else
9208 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9209 i.types[this_operand].bitfield.word = 1;
a724f0f4 9210 }
64a0c779 9211
a724f0f4
JB		 9212 else if (prev_token.code == T_DWORD)
9213 {
34b772a6
JB		 9214 if ((current_templates->start->name[0] == 'l'
9215 && current_templates->start->name[2] == 's'
9216 && current_templates->start->name[3] == 0)
9217 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9218 suffix = WORD_MNEM_SUFFIX;
9219 else if (flag_code == CODE_16BIT
40fb9820
L		 9220 && (current_templates->start->opcode_modifier.jump
9221 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9222 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9223 else if (intel_parser.got_a_float == 1) /* "f..." */
9224 suffix = SHORT_MNEM_SUFFIX;
9225 else
9226 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9227 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9228 }
9306ca4a 9229
a724f0f4
JB		 9230 else if (prev_token.code == T_FWORD)
9231 {
9232 if (current_templates->start->name[0] == 'l'
9233 && current_templates->start->name[2] == 's'
9234 && current_templates->start->name[3] == 0)
9235 suffix = LONG_MNEM_SUFFIX;
9236 else if (!intel_parser.got_a_float)
9237 {
9238 if (flag_code == CODE_16BIT)
9239 add_prefix (DATA_PREFIX_OPCODE);
9240 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9241 }
9242 else
9243 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9244 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9245 }
64a0c779 9246
a724f0f4
JB		 9247 else if (prev_token.code == T_QWORD)
9248 {
34b772a6
JB		 9249 if (current_templates->start->base_opcode == 0x62 /* bound */
9250 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9251 suffix = LONG_MNEM_SUFFIX;
9252 else
34b772a6 9253 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9254 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9255 }
64a0c779 9256
a724f0f4
JB		 9257 else if (prev_token.code == T_TBYTE)
9258 {
9259 if (intel_parser.got_a_float == 1)
9260 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9261 else
9262 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9263 }
9306ca4a 9264
a724f0f4 9265 else if (prev_token.code == T_XMMWORD)
9306ca4a 9266 {
582d5edd 9267 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9268 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9269 }
64a0c779 9270
c0f3af97
L		 9271 else if (prev_token.code == T_YMMWORD)
9272 {
9273 suffix = YMMWORD_MNEM_SUFFIX;
9274 i.types[this_operand].bitfield.ymmword = 1;
9275 }
9276
f16b83df 9277 else
a724f0f4
JB		 9278 {
9279 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9280 return 0;
9281 }
9282
7d5e4556
L		 9283 i.types[this_operand].bitfield.unspecified = 0;
9284
435acd52
JB		 9285 /* Operands for jump/call using 'ptr' notation denote absolute
9286 addresses. */
40fb9820
L		 9287 if (current_templates->start->opcode_modifier.jump
9288 || current_templates->start->opcode_modifier.jumpdword)
9289 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9290
a724f0f4
JB		 9291 if (current_templates->start->base_opcode == 0x8d /* lea */)
9292 ;
9293 else if (!i.suffix)
9294 i.suffix = suffix;
9295 else if (i.suffix != suffix)
9296 {
9297 as_bad (_("Conflicting operand modifiers"));
9298 return 0;
9299 }
64a0c779 9300
9306ca4a
JB		 9301 }
9302
a724f0f4
JB		 9303 /* e09' : e10 e09' */
9304 else if (cur_token.code == ':')
9306ca4a 9305 {
a724f0f4
JB		 9306 if (prev_token.code != T_REG)
9307 {
9308 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9309 segment/group identifier (which we don't have), using comma
9310 as the operand separator there is even less consistent, since
9311 there all branches only have a single operand. */
9312 if (this_operand != 0
9313 || intel_parser.in_offset
9314 || intel_parser.in_bracket
40fb9820
L		 9315 || (!current_templates->start->opcode_modifier.jump
9316 && !current_templates->start->opcode_modifier.jumpdword
9317 && !current_templates->start->opcode_modifier.jumpintersegment
9318 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9319 return intel_match_token (T_NIL);
9320 /* Remember the start of the 2nd operand and terminate 1st
9321 operand here.
9322 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9323 another expression), but it gets at least the simplest case
9324 (a plain number or symbol on the left side) right. */
9325 intel_parser.next_operand = intel_parser.op_string;
9326 *--intel_parser.op_string = '\0';
9327 return intel_match_token (':');
9328 }
9306ca4a 9329 }
64a0c779 9330
a724f0f4 9331 /* e09' Empty */
64a0c779 9332 else
a724f0f4 9333 break;
64a0c779 9334
a724f0f4
JB		 9335 intel_match_token (cur_token.code);
9336
9337 }
9338
9339 if (in_offset)
9340 {
9341 --intel_parser.in_offset;
9342 if (nregs < 0)
9343 nregs = ~nregs;
9344 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9345 {
a724f0f4 9346 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9347 return 0;
9348 }
a724f0f4
JB		 9349 intel_parser.op_modifier |= 1 << T_OFFSET;
9350 }
9306ca4a 9351
a724f0f4
JB		 9352 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9353 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9354 return 1;
9355}
64a0c779 9356
a724f0f4 9357static int
e3bb37b5 9358intel_bracket_expr (void)
a724f0f4
JB		 9359{
9360 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9361 const char *start = intel_parser.op_string;
9362 int len;
9363
9364 if (i.op[this_operand].regs)
9365 return intel_match_token (T_NIL);
9366
9367 intel_match_token ('[');
9368
9369 /* Mark as a memory operand only if it's not already known to be an
9370 offset expression. If it's an offset expression, we need to keep
9371 the brace in. */
9372 if (!intel_parser.in_offset)
9373 {
9374 ++intel_parser.in_bracket;
435acd52
JB		 9375
9376 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9377 if (current_templates->start->opcode_modifier.jump
9378 || current_templates->start->opcode_modifier.jumpdword)
9379 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9380
a724f0f4
JB		 9381 /* Unfortunately gas always diverged from MASM in a respect that can't
9382 be easily fixed without risking to break code sequences likely to be
9383 encountered (the testsuite even check for this): MASM doesn't consider
9384 an expression inside brackets unconditionally as a memory reference.
9385 When that is e.g. a constant, an offset expression, or the sum of the
9386 two, this is still taken as a constant load. gas, however, always
9387 treated these as memory references. As a compromise, we'll try to make
9388 offset expressions inside brackets work the MASM way (since that's
9389 less likely to be found in real world code), but make constants alone
9390 continue to work the traditional gas way. In either case, issue a
9391 warning. */
9392 intel_parser.op_modifier &= ~was_offset;
64a0c779 9393 }
a724f0f4 9394 else
64e74474 9395 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9396
9397 /* Add a '+' to the displacement string if necessary. */
9398 if (*intel_parser.disp != '\0'
9399 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9400 strcat (intel_parser.disp, "+");
64a0c779 9401
a724f0f4
JB		 9402 if (intel_expr ()
9403 && (len = intel_parser.op_string - start - 1,
9404 intel_match_token (']')))
64a0c779 9405 {
a724f0f4
JB		 9406 /* Preserve brackets when the operand is an offset expression. */
9407 if (intel_parser.in_offset)
9408 strcat (intel_parser.disp, "]");
9409 else
9410 {
9411 --intel_parser.in_bracket;
9412 if (i.base_reg || i.index_reg)
9413 intel_parser.is_mem = 1;
9414 if (!intel_parser.is_mem)
9415 {
9416 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9417 /* Defer the warning until all of the operand was parsed. */
9418 intel_parser.is_mem = -1;
9419 else if (!quiet_warnings)
4eed87de
AM		 9420 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9421 len, start, len, start);
a724f0f4
JB		 9422 }
9423 }
9424 intel_parser.op_modifier |= was_offset;
64a0c779 9425
a724f0f4 9426 return 1;
64a0c779 9427 }
a724f0f4 9428 return 0;
64a0c779
DN		 9429}
9430
9431/* e10 e11 e10'
9432
9433 e10' [ expr ] e10'
b77a7acd 9434 | Empty */
64a0c779 9435static int
e3bb37b5 9436intel_e10 (void)
64a0c779 9437{
a724f0f4
JB		 9438 if (!intel_e11 ())
9439 return 0;
64a0c779 9440
a724f0f4 9441 while (cur_token.code == '[')
64a0c779 9442 {
a724f0f4 9443 if (!intel_bracket_expr ())
21d6c4af 9444 return 0;
64a0c779
DN		 9445 }
9446
a724f0f4 9447 return 1;
64a0c779
DN		 9448}
9449
64a0c779 9450/* e11 ( expr )
b77a7acd 9451 | [ expr ]
64a0c779
DN		 9452 | BYTE
9453 | WORD
9454 | DWORD
9306ca4a 9455 | FWORD
64a0c779 9456 | QWORD
9306ca4a
JB		 9457 | TBYTE
9458 | OWORD
9459 | XMMWORD
c0f3af97 9460 | YMMWORD
4a1805b1 9461 | $
64a0c779
DN		 9462 | .
9463 | register
9464 | id
9465 | constant */
9466static int
e3bb37b5 9467intel_e11 (void)
64a0c779 9468{
a724f0f4 9469 switch (cur_token.code)
64a0c779 9470 {
a724f0f4
JB		 9471 /* e11 ( expr ) */
9472 case '(':
64a0c779
DN		 9473 intel_match_token ('(');
9474 strcat (intel_parser.disp, "(");
9475
9476 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9477 {
9478 strcat (intel_parser.disp, ")");
9479 return 1;
9480 }
a724f0f4 9481 return 0;
4a1805b1 9482
a724f0f4
JB		 9483 /* e11 [ expr ] */
9484 case '[':
a724f0f4 9485 return intel_bracket_expr ();
64a0c779 9486
a724f0f4
JB		 9487 /* e11 $
9488 | . */
9489 case '.':
64a0c779
DN		 9490 strcat (intel_parser.disp, cur_token.str);
9491 intel_match_token (cur_token.code);
21d6c4af
DN		 9492
9493 /* Mark as a memory operand only if it's not already known to be an
9494 offset expression. */
a724f0f4 9495 if (!intel_parser.in_offset)
21d6c4af 9496 intel_parser.is_mem = 1;
64a0c779
DN		 9497
9498 return 1;
64a0c779 9499
a724f0f4
JB		 9500 /* e11 register */
9501 case T_REG:
9502 {
9503 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9504
a724f0f4 9505 intel_match_token (T_REG);
64a0c779 9506
a724f0f4
JB		 9507 /* Check for segment change. */
9508 if (cur_token.code == ':')
9509 {
40fb9820
L		 9510 if (!reg->reg_type.bitfield.sreg2
9511 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9512 {
4eed87de
AM		 9513 as_bad (_("`%s' is not a valid segment register"),
9514 reg->reg_name);
a724f0f4
JB		 9515 return 0;
9516 }
b7240065
JB		 9517 else if (i.mem_operands >= 2)
9518 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9519 else if (i.seg[i.mem_operands])
9520 as_warn (_("Extra segment override ignored"));
9521 else
9522 {
9523 if (!intel_parser.in_offset)
9524 intel_parser.is_mem = 1;
9525 switch (reg->reg_num)
9526 {
9527 case 0:
9528 i.seg[i.mem_operands] = &es;
9529 break;
9530 case 1:
9531 i.seg[i.mem_operands] = &cs;
9532 break;
9533 case 2:
9534 i.seg[i.mem_operands] = &ss;
9535 break;
9536 case 3:
9537 i.seg[i.mem_operands] = &ds;
9538 break;
9539 case 4:
9540 i.seg[i.mem_operands] = &fs;
9541 break;
9542 case 5:
9543 i.seg[i.mem_operands] = &gs;
9544 break;
9545 }
9546 }
9547 }
64a0c779 9548
b7240065
JB		 9549 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9550 {
9551 as_bad (_("cannot use `FLAT' here"));
9552 return 0;
9553 }
9554
a724f0f4
JB		 9555 /* Not a segment register. Check for register scaling. */
9556 else if (cur_token.code == '*')
9557 {
9558 if (!intel_parser.in_bracket)
9559 {
9560 as_bad (_("Register scaling only allowed in memory operands"));
9561 return 0;
9562 }
64a0c779 9563
40fb9820 9564 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9565 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9566 else if (i.index_reg)
9567 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9568
a724f0f4
JB		 9569 /* What follows must be a valid scale. */
9570 intel_match_token ('*');
9571 i.index_reg = reg;
40fb9820 9572 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9573
a724f0f4
JB		 9574 /* Set the scale after setting the register (otherwise,
9575 i386_scale will complain) */
9576 if (cur_token.code == '+' || cur_token.code == '-')
9577 {
9578 char *str, sign = cur_token.code;
9579 intel_match_token (cur_token.code);
9580 if (cur_token.code != T_CONST)
9581 {
9582 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9583 cur_token.str);
9584 return 0;
9585 }
9586 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9587 strcpy (str + 1, cur_token.str);
9588 *str = sign;
9589 if (!i386_scale (str))
9590 return 0;
9591 free (str);
9592 }
9593 else if (!i386_scale (cur_token.str))
64a0c779 9594 return 0;
a724f0f4
JB		 9595 intel_match_token (cur_token.code);
9596 }
64a0c779 9597
a724f0f4
JB		 9598 /* No scaling. If this is a memory operand, the register is either a
9599 base register (first occurrence) or an index register (second
9600 occurrence). */
7b0441f6 9601 else if (intel_parser.in_bracket)
a724f0f4 9602 {
64a0c779 9603
a724f0f4
JB		 9604 if (!i.base_reg)
9605 i.base_reg = reg;
9606 else if (!i.index_reg)
9607 i.index_reg = reg;
9608 else
9609 {
9610 as_bad (_("Too many register references in memory operand"));
9611 return 0;
9612 }
64a0c779 9613
40fb9820 9614 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9615 }
4a1805b1 9616
4d1bb795
JB		 9617 /* It's neither base nor index. */
9618 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9619 {
40fb9820
L		 9620 i386_operand_type temp = reg->reg_type;
9621 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9622 i.types[this_operand] = operand_type_or (i.types[this_operand],
9623 temp);
7d5e4556 9624 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9625 i.op[this_operand].regs = reg;
9626 i.reg_operands++;
9627 }
9628 else
9629 {
9630 as_bad (_("Invalid use of register"));
9631 return 0;
9632 }
64a0c779 9633
a724f0f4
JB		 9634 /* Since registers are not part of the displacement string (except
9635 when we're parsing offset operands), we may need to remove any
9636 preceding '+' from the displacement string. */
9637 if (*intel_parser.disp != '\0'
9638 && !intel_parser.in_offset)
9639 {
9640 char *s = intel_parser.disp;
9641 s += strlen (s) - 1;
9642 if (*s == '+')
9643 *s = '\0';
9644 }
4a1805b1 9645
a724f0f4
JB		 9646 return 1;
9647 }
9648
9649 /* e11 BYTE
9650 | WORD
9651 | DWORD
9652 | FWORD
9653 | QWORD
9654 | TBYTE
9655 | OWORD
c0f3af97
L		 9656 | XMMWORD
9657 | YMMWORD */
a724f0f4
JB		 9658 case T_BYTE:
9659 case T_WORD:
9660 case T_DWORD:
9661 case T_FWORD:
9662 case T_QWORD:
9663 case T_TBYTE:
9664 case T_XMMWORD:
c0f3af97 9665 case T_YMMWORD:
a724f0f4 9666 intel_match_token (cur_token.code);
64a0c779 9667
a724f0f4
JB		 9668 if (cur_token.code == T_PTR)
9669 return 1;
9670
9671 /* It must have been an identifier. */
9672 intel_putback_token ();
9673 cur_token.code = T_ID;
9674 /* FALLTHRU */
9675
9676 /* e11 id
9677 | constant */
9678 case T_ID:
9679 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9680 {
9681 symbolS *symbolP;
9682
a724f0f4
JB		 9683 /* The identifier represents a memory reference only if it's not
9684 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9685 symbolP = symbol_find(cur_token.str);
9686 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9687 intel_parser.is_mem = 1;
9688 }
a724f0f4 9689 /* FALLTHRU */
64a0c779 9690
a724f0f4
JB		 9691 case T_CONST:
9692 case '-':
9693 case '+':
9694 {
9695 char *save_str, sign = 0;
64a0c779 9696
a724f0f4
JB		 9697 /* Allow constants that start with `+' or `-'. */
9698 if (cur_token.code == '-' || cur_token.code == '+')
9699 {
9700 sign = cur_token.code;
9701 intel_match_token (cur_token.code);
9702 if (cur_token.code != T_CONST)
9703 {
9704 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9705 cur_token.str);
9706 return 0;
9707 }
9708 }
64a0c779 9709
a724f0f4
JB		 9710 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9711 strcpy (save_str + !!sign, cur_token.str);
9712 if (sign)
9713 *save_str = sign;
64a0c779 9714
a724f0f4
JB		 9715 /* Get the next token to check for register scaling. */
9716 intel_match_token (cur_token.code);
64a0c779 9717
4eed87de
AM		 9718 /* Check if this constant is a scaling factor for an
9719 index register. */
a724f0f4
JB		 9720 if (cur_token.code == '*')
9721 {
9722 if (intel_match_token ('*') && cur_token.code == T_REG)
9723 {
9724 const reg_entry *reg = cur_token.reg;
9725
9726 if (!intel_parser.in_bracket)
9727 {
4eed87de
AM		 9728 as_bad (_("Register scaling only allowed "
9729 "in memory operands"));
a724f0f4
JB		 9730 return 0;
9731 }
9732
4eed87de
AM		 9733 /* Disallow things like [1*si].
9734 sp and esp are invalid as index. */
40fb9820 9735 if (reg->reg_type.bitfield.reg16)
4eed87de 9736 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9737 else if (i.index_reg)
4eed87de 9738 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9739
9740 /* The constant is followed by `* reg', so it must be
9741 a valid scale. */
9742 i.index_reg = reg;
40fb9820 9743 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9744
9745 /* Set the scale after setting the register (otherwise,
9746 i386_scale will complain) */
9747 if (!i386_scale (save_str))
64a0c779 9748 return 0;
a724f0f4
JB		 9749 intel_match_token (T_REG);
9750
9751 /* Since registers are not part of the displacement
9752 string, we may need to remove any preceding '+' from
9753 the displacement string. */
9754 if (*intel_parser.disp != '\0')
9755 {
9756 char *s = intel_parser.disp;
9757 s += strlen (s) - 1;
9758 if (*s == '+')
9759 *s = '\0';
9760 }
9761
9762 free (save_str);
9763
9764 return 1;
9765 }
64a0c779 9766
a724f0f4
JB		 9767 /* The constant was not used for register scaling. Since we have
9768 already consumed the token following `*' we now need to put it
9769 back in the stream. */
64a0c779 9770 intel_putback_token ();
a724f0f4 9771 }
64a0c779 9772
a724f0f4
JB		 9773 /* Add the constant to the displacement string. */
9774 strcat (intel_parser.disp, save_str);
9775 free (save_str);
64a0c779 9776
a724f0f4
JB		 9777 return 1;
9778 }
64a0c779
DN		 9779 }
9780
64a0c779
DN		 9781 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9782 return 0;
9783}
9784
64a0c779
DN		 9785/* Match the given token against cur_token. If they match, read the next
9786 token from the operand string. */
9787static int
e3bb37b5 9788intel_match_token (int code)
64a0c779
DN		 9789{
9790 if (cur_token.code == code)
9791 {
9792 intel_get_token ();
9793 return 1;
9794 }
9795 else
9796 {
0477af35 9797 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9798 return 0;
9799 }
9800}
9801
64a0c779
DN		 9802/* Read a new token from intel_parser.op_string and store it in cur_token. */
9803static void
e3bb37b5 9804intel_get_token (void)
64a0c779
DN		 9805{
9806 char *end_op;
9807 const reg_entry *reg;
9808 struct intel_token new_token;
9809
9810 new_token.code = T_NIL;
9811 new_token.reg = NULL;
9812 new_token.str = NULL;
9813
4a1805b1 9814 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9815 cur_token to prev_token. */
9816 if (prev_token.str)
9817 free (prev_token.str);
9818
9819 prev_token = cur_token;
9820
9821 /* Skip whitespace. */
9822 while (is_space_char (*intel_parser.op_string))
9823 intel_parser.op_string++;
9824
9825 /* Return an empty token if we find nothing else on the line. */
9826 if (*intel_parser.op_string == '\0')
9827 {
9828 cur_token = new_token;
9829 return;
9830 }
9831
9832 /* The new token cannot be larger than the remainder of the operand
9833 string. */
a724f0f4 9834 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9835 new_token.str[0] = '\0';
9836
9837 if (strchr ("0123456789", *intel_parser.op_string))
9838 {
9839 char *p = new_token.str;
9840 char *q = intel_parser.op_string;
9841 new_token.code = T_CONST;
9842
9843 /* Allow any kind of identifier char to encompass floating point and
9844 hexadecimal numbers. */
9845 while (is_identifier_char (*q))
9846 *p++ = *q++;
9847 *p = '\0';
9848
9849 /* Recognize special symbol names [0-9][bf]. */
9850 if (strlen (intel_parser.op_string) == 2
4a1805b1 9851 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9852 || intel_parser.op_string[1] == 'f'))
9853 new_token.code = T_ID;
9854 }
9855
4d1bb795 9856 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9857 {
4d1bb795
JB		 9858 size_t len = end_op - intel_parser.op_string;
9859
64a0c779
DN		 9860 new_token.code = T_REG;
9861 new_token.reg = reg;
9862
4d1bb795
JB		 9863 memcpy (new_token.str, intel_parser.op_string, len);
9864 new_token.str[len] = '\0';
64a0c779
DN		 9865 }
9866
9867 else if (is_identifier_char (*intel_parser.op_string))
9868 {
9869 char *p = new_token.str;
9870 char *q = intel_parser.op_string;
9871
9872 /* A '.' or '$' followed by an identifier char is an identifier.
9873 Otherwise, it's operator '.' followed by an expression. */
9874 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9875 {
9306ca4a
JB		 9876 new_token.code = '.';
9877 new_token.str[0] = '.';
64a0c779
DN		 9878 new_token.str[1] = '\0';
9879 }
9880 else
9881 {
9882 while (is_identifier_char (*q) || *q == '@')
9883 *p++ = *q++;
9884 *p = '\0';
9885
9306ca4a
JB		 9886 if (strcasecmp (new_token.str, "NOT") == 0)
9887 new_token.code = '~';
9888
9889 else if (strcasecmp (new_token.str, "MOD") == 0)
9890 new_token.code = '%';
9891
9892 else if (strcasecmp (new_token.str, "AND") == 0)
9893 new_token.code = '&';
9894
9895 else if (strcasecmp (new_token.str, "OR") == 0)
9896 new_token.code = '|';
9897
9898 else if (strcasecmp (new_token.str, "XOR") == 0)
9899 new_token.code = '^';
9900
9901 else if (strcasecmp (new_token.str, "SHL") == 0)
9902 new_token.code = T_SHL;
9903
9904 else if (strcasecmp (new_token.str, "SHR") == 0)
9905 new_token.code = T_SHR;
9906
9907 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9908 new_token.code = T_BYTE;
9909
9910 else if (strcasecmp (new_token.str, "WORD") == 0)
9911 new_token.code = T_WORD;
9912
9913 else if (strcasecmp (new_token.str, "DWORD") == 0)
9914 new_token.code = T_DWORD;
9915
9306ca4a
JB		 9916 else if (strcasecmp (new_token.str, "FWORD") == 0)
9917 new_token.code = T_FWORD;
9918
64a0c779
DN		 9919 else if (strcasecmp (new_token.str, "QWORD") == 0)
9920 new_token.code = T_QWORD;
9921
9306ca4a
JB		 9922 else if (strcasecmp (new_token.str, "TBYTE") == 0
9923 /* XXX remove (gcc still uses it) */
9924 || strcasecmp (new_token.str, "XWORD") == 0)
9925 new_token.code = T_TBYTE;
9926
9927 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9928 || strcasecmp (new_token.str, "OWORD") == 0)
9929 new_token.code = T_XMMWORD;
64a0c779 9930
c0f3af97
L		 9931 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9932 new_token.code = T_YMMWORD;
9933
64a0c779
DN		 9934 else if (strcasecmp (new_token.str, "PTR") == 0)
9935 new_token.code = T_PTR;
9936
9937 else if (strcasecmp (new_token.str, "SHORT") == 0)
9938 new_token.code = T_SHORT;
9939
9940 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9941 {
9942 new_token.code = T_OFFSET;
9943
9944 /* ??? This is not mentioned in the MASM grammar but gcc
9945 makes use of it with -mintel-syntax. OFFSET may be
9946 followed by FLAT: */
9947 if (strncasecmp (q, " FLAT:", 6) == 0)
9948 strcat (new_token.str, " FLAT:");
9949 }
9950
64a0c779
DN		 9951 else
9952 new_token.code = T_ID;
9953 }
9954 }
9955
9306ca4a
JB		 9956 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9957 {
9958 new_token.code = *intel_parser.op_string;
9959 new_token.str[0] = *intel_parser.op_string;
9960 new_token.str[1] = '\0';
9961 }
9962
9963 else if (strchr ("<>", *intel_parser.op_string)
9964 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9965 {
9966 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9967 new_token.str[0] = *intel_parser.op_string;
9968 new_token.str[1] = *intel_parser.op_string;
9969 new_token.str[2] = '\0';
9970 }
9971
64a0c779 9972 else
0477af35 9973 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9974
9975 intel_parser.op_string += strlen (new_token.str);
9976 cur_token = new_token;
9977}
9978
64a0c779
DN		 9979/* Put cur_token back into the token stream and make cur_token point to
9980 prev_token. */
9981static void
e3bb37b5 9982intel_putback_token (void)
64a0c779 9983{
a724f0f4
JB		 9984 if (cur_token.code != T_NIL)
9985 {
9986 intel_parser.op_string -= strlen (cur_token.str);
9987 free (cur_token.str);
9988 }
64a0c779 9989 cur_token = prev_token;
4a1805b1 9990
64a0c779
DN		 9991 /* Forget prev_token. */
9992 prev_token.code = T_NIL;
9993 prev_token.reg = NULL;
9994 prev_token.str = NULL;
9995}
54cfded0 9996
a60de03c
JB		 9997void
9998tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9999{
a60de03c
JB		 10000 int saved_naked_reg;
10001 char saved_register_dot;
54cfded0 10002
a60de03c
JB		 10003 saved_naked_reg = allow_naked_reg;
10004 allow_naked_reg = 1;
10005 saved_register_dot = register_chars['.'];
10006 register_chars['.'] = '.';
10007 allow_pseudo_reg = 1;
10008 expression_and_evaluate (exp);
10009 allow_pseudo_reg = 0;
10010 register_chars['.'] = saved_register_dot;
10011 allow_naked_reg = saved_naked_reg;
10012
10013 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10014 {
a60de03c
JB		 10015 if ((addressT) exp->X_add_number < i386_regtab_size)
10016 {
10017 exp->X_op = O_constant;
10018 exp->X_add_number = i386_regtab[exp->X_add_number]
10019 .dw2_regnum[flag_code >> 1];
10020 }
10021 else
10022 exp->X_op = O_illegal;
54cfded0 10023 }
54cfded0
AM		 10024}
10025
10026void
10027tc_x86_frame_initial_instructions (void)
10028{
a60de03c
JB		 10029 static unsigned int sp_regno[2];
10030
10031 if (!sp_regno[flag_code >> 1])
10032 {
10033 char *saved_input = input_line_pointer;
10034 char sp[][4] = {"esp", "rsp"};
10035 expressionS exp;
a4447b93 10036
a60de03c
JB		 10037 input_line_pointer = sp[flag_code >> 1];
10038 tc_x86_parse_to_dw2regnum (&exp);
10039 assert (exp.X_op == O_constant);
10040 sp_regno[flag_code >> 1] = exp.X_add_number;
10041 input_line_pointer = saved_input;
10042 }
a4447b93 10043
a60de03c 10044 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 10045 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10046}
d2b2c203
DJ		 10047
10048int
10049i386_elf_section_type (const char *str, size_t len)
10050{
10051 if (flag_code == CODE_64BIT
10052 && len == sizeof ("unwind") - 1
10053 && strncmp (str, "unwind", 6) == 0)
10054 return SHT_X86_64_UNWIND;
10055
10056 return -1;
10057}
bb41ade5 10058
ad5fec3b
EB		 10059#ifdef TE_SOLARIS
10060void
10061i386_solaris_fix_up_eh_frame (segT sec)
10062{
10063 if (flag_code == CODE_64BIT)
10064 elf_section_type (sec) = SHT_X86_64_UNWIND;
10065}
10066#endif
10067
bb41ade5
AM		 10068#ifdef TE_PE
10069void
10070tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10071{
10072 expressionS expr;
10073
10074 expr.X_op = O_secrel;
10075 expr.X_add_symbol = symbol;
10076 expr.X_add_number = 0;
10077 emit_expr (&expr, size);
10078}
10079#endif
3b22753a
L		 10080
10081#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10082/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10083
01e1a5bc 10084bfd_vma
3b22753a
L		 10085x86_64_section_letter (int letter, char **ptr_msg)
10086{
10087 if (flag_code == CODE_64BIT)
10088 {
10089 if (letter == 'l')
10090 return SHF_X86_64_LARGE;
10091
10092 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10093 }
3b22753a 10094 else
64e74474 10095 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10096 return -1;
10097}
10098
01e1a5bc 10099bfd_vma
3b22753a
L		 10100x86_64_section_word (char *str, size_t len)
10101{
8620418b 10102 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10103 return SHF_X86_64_LARGE;
10104
10105 return -1;
10106}
10107
10108static void
10109handle_large_common (int small ATTRIBUTE_UNUSED)
10110{
10111 if (flag_code != CODE_64BIT)
10112 {
10113 s_comm_internal (0, elf_common_parse);
10114 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10115 }
10116 else
10117 {
10118 static segT lbss_section;
10119 asection *saved_com_section_ptr = elf_com_section_ptr;
10120 asection *saved_bss_section = bss_section;
10121
10122 if (lbss_section == NULL)
10123 {
10124 flagword applicable;
10125 segT seg = now_seg;
10126 subsegT subseg = now_subseg;
10127
10128 /* The .lbss section is for local .largecomm symbols. */
10129 lbss_section = subseg_new (".lbss", 0);
10130 applicable = bfd_applicable_section_flags (stdoutput);
10131 bfd_set_section_flags (stdoutput, lbss_section,
10132 applicable & SEC_ALLOC);
10133 seg_info (lbss_section)->bss = 1;
10134
10135 subseg_set (seg, subseg);
10136 }
10137
10138 elf_com_section_ptr = &_bfd_elf_large_com_section;
10139 bss_section = lbss_section;
10140
10141 s_comm_internal (0, elf_common_parse);
10142
10143 elf_com_section_ptr = saved_com_section_ptr;
10144 bss_section = saved_bss_section;
10145 }
10146}
10147#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.192158 seconds and 4 git commands to generate.