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* gold/testsuite/Makefile.am (justsyms_exec): New testcase.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
314a59d5 185static void handle_quad (int);
17d4e2a2 186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
c0f3af97
L		 190/* VEX prefix. */
191typedef struct
192{
193 /* VEX prefix is either 2 byte or 3 byte. */
194 unsigned char bytes[3];
195 unsigned int length;
196 /* Destination or source register specifier. */
197 const reg_entry *register_specifier;
198} vex_prefix;
199
252b5132 200/* 'md_assemble ()' gathers together information and puts it into a
47926f60 201 i386_insn. */
252b5132 202
520dc8e8
AM		 203union i386_op
204 {
205 expressionS *disps;
206 expressionS *imms;
207 const reg_entry *regs;
208 };
209
a65babc9
L		 210enum i386_error
211 {
86e026a4 212 operand_size_mismatch,
a65babc9
L		 213 operand_type_mismatch,
214 register_type_mismatch,
215 number_of_operands_mismatch,
216 invalid_instruction_suffix,
217 bad_imm4,
218 old_gcc_only,
219 unsupported_with_intel_mnemonic,
220 unsupported_syntax,
6c30d220
L		 221 unsupported,
222 invalid_vsib_address,
223 unsupported_vector_index_register
a65babc9
L		 224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 229 insn_template tm;
252b5132 230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 274 addressing modes of this insn are encoded. */
252b5132 275 modrm_byte rm;
3e73aa7c 276 rex_byte rex;
252b5132 277 sib_byte sib;
c0f3af97 278 vex_prefix vex;
b6169b20
L		 279
280 /* Swap operand in encoding. */
4473e004 281 unsigned int swap_operand;
891edac4 282
f8a5c266
L		 283 /* Force 32bit displacement in encoding. */
284 unsigned int disp32_encoding;
285
891edac4 286 /* Error message. */
a65babc9 287 enum i386_error error;
252b5132
RH		 288 };
289
290typedef struct _i386_insn i386_insn;
291
292/* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
32137342 294const char extra_symbol_chars[] = "*%-(["
252b5132 295#ifdef LEX_AT
32137342
NC		 296 "@"
297#endif
298#ifdef LEX_QM
299 "?"
252b5132 300#endif
32137342 301 ;
252b5132 302
29b0f896
AM		 303#if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 305 && !defined (TE_GNU) \
29b0f896 306 && !defined (TE_LINUX) \
32137342 307 && !defined (TE_NETWARE) \
29b0f896 308 && !defined (TE_FreeBSD) \
5b806d27 309 && !defined (TE_DragonFly) \
29b0f896 310 && !defined (TE_NetBSD)))
252b5132 311/* This array holds the chars that always start a comment. If the
b3b91714
AM		 312 pre-processor is disabled, these aren't very useful. The option
313 --divide will remove '/' from this list. */
314const char *i386_comment_chars = "#/";
315#define SVR4_COMMENT_CHARS 1
252b5132 316#define PREFIX_SEPARATOR '\\'
252b5132 317
b3b91714
AM		 318#else
319const char *i386_comment_chars = "#";
320#define PREFIX_SEPARATOR '/'
321#endif
322
252b5132
RH		 323/* This array holds the chars that only start a comment at the beginning of
324 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 325 .line and .file directives will appear in the pre-processed output.
326 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 327 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 328 #NO_APP at the beginning of its output.
329 Also note that comments started like this one will always work if
252b5132 330 '/' isn't otherwise defined. */
b3b91714 331const char line_comment_chars[] = "#/";
252b5132 332
63a0b638 333const char line_separator_chars[] = ";";
252b5132 334
ce8a8b2f
AM		 335/* Chars that can be used to separate mant from exp in floating point
336 nums. */
252b5132
RH		 337const char EXP_CHARS[] = "eE";
338
ce8a8b2f
AM		 339/* Chars that mean this number is a floating point constant
340 As in 0f12.456
341 or 0d1.2345e12. */
252b5132
RH		 342const char FLT_CHARS[] = "fFdDxX";
343
ce8a8b2f 344/* Tables for lexical analysis. */
252b5132
RH		 345static char mnemonic_chars[256];
346static char register_chars[256];
347static char operand_chars[256];
348static char identifier_chars[256];
349static char digit_chars[256];
350
ce8a8b2f 351/* Lexical macros. */
252b5132
RH		 352#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
353#define is_operand_char(x) (operand_chars[(unsigned char) x])
354#define is_register_char(x) (register_chars[(unsigned char) x])
355#define is_space_char(x) ((x) == ' ')
356#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
357#define is_digit_char(x) (digit_chars[(unsigned char) x])
358
0234cb7c 359/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 360static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361
362/* md_assemble() always leaves the strings it's passed unaltered. To
363 effect this we maintain a stack of saved characters that we've smashed
364 with '\0's (indicating end of strings for various sub-fields of the
47926f60 365 assembler instruction). */
252b5132 366static char save_stack[32];
ce8a8b2f 367static char *save_stack_p;
252b5132
RH		 368#define END_STRING_AND_SAVE(s) \
369 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
370#define RESTORE_END_STRING(s) \
371 do { *(s) = *--save_stack_p; } while (0)
372
47926f60 373/* The instruction we're assembling. */
252b5132
RH		 374static i386_insn i;
375
376/* Possible templates for current insn. */
377static const templates *current_templates;
378
31b2323c
L		 379/* Per instruction expressionS buffers: max displacements & immediates. */
380static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
381static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 382
47926f60 383/* Current operand we are working on. */
ee86248c 384static int this_operand = -1;
252b5132 385
3e73aa7c
JH		 386/* We support four different modes. FLAG_CODE variable is used to distinguish
387 these. */
388
389enum flag_code {
390 CODE_32BIT,
391 CODE_16BIT,
392 CODE_64BIT };
393
394static enum flag_code flag_code;
4fa24527 395static unsigned int object_64bit;
862be3fb 396static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 397static int use_rela_relocations = 0;
398
7af8ed2d
NC		 399#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
400 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
401 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
402
351f65ca
L		 403/* The ELF ABI to use. */
404enum x86_elf_abi
405{
406 I386_ABI,
7f56bc95
L		 407 X86_64_ABI,
408 X86_64_X32_ABI
351f65ca
L		 409};
410
411static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 412#endif
351f65ca 413
3e73aa7c 414/* The names used to print error messages. */
b77a7acd 415static const char *flag_code_names[] =
3e73aa7c
JH		 416 {
417 "32",
418 "16",
419 "64"
420 };
252b5132 421
47926f60
KH		 422/* 1 for intel syntax,
423 0 if att syntax. */
424static int intel_syntax = 0;
252b5132 425
1efbbeb4
L		 426/* 1 for intel mnemonic,
427 0 if att mnemonic. */
428static int intel_mnemonic = !SYSV386_COMPAT;
429
5209009a 430/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 431static int old_gcc = OLDGCC_COMPAT;
432
a60de03c
JB		 433/* 1 if pseudo registers are permitted. */
434static int allow_pseudo_reg = 0;
435
47926f60
KH		 436/* 1 if register prefix % not required. */
437static int allow_naked_reg = 0;
252b5132 438
ba104c83 439/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 440static int allow_index_reg = 0;
441
daf50ae7
L		 442static enum
443 {
444 sse_check_none = 0,
445 sse_check_warning,
446 sse_check_error
447 }
448sse_check;
449
2ca3ace5
L		 450/* Register prefix used for error message. */
451static const char *register_prefix = "%";
452
47926f60
KH		 453/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
454 leave, push, and pop instructions so that gcc has the same stack
455 frame as in 32 bit mode. */
456static char stackop_size = '\0';
eecb386c 457
12b55ccc
L		 458/* Non-zero to optimize code alignment. */
459int optimize_align_code = 1;
460
47926f60
KH		 461/* Non-zero to quieten some warnings. */
462static int quiet_warnings = 0;
a38cf1db 463
47926f60
KH		 464/* CPU name. */
465static const char *cpu_arch_name = NULL;
6305a203 466static char *cpu_sub_arch_name = NULL;
a38cf1db 467
47926f60 468/* CPU feature flags. */
40fb9820
L		 469static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
470
ccc9c027
L		 471/* If we have selected a cpu we are generating instructions for. */
472static int cpu_arch_tune_set = 0;
473
9103f4f4 474/* Cpu we are generating instructions for. */
fbf3f584 475enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 476
477/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 478static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 479
ccc9c027 480/* CPU instruction set architecture used. */
fbf3f584 481enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 482
9103f4f4 483/* CPU feature flags of instruction set architecture used. */
fbf3f584 484i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 485
fddf5b5b
AM		 486/* If set, conditional jumps are not automatically promoted to handle
487 larger than a byte offset. */
488static unsigned int no_cond_jump_promotion = 0;
489
c0f3af97
L		 490/* Encode SSE instructions with VEX prefix. */
491static unsigned int sse2avx;
492
539f890d
L		 493/* Encode scalar AVX instructions with specific vector length. */
494static enum
495 {
496 vex128 = 0,
497 vex256
498 } avxscalar;
499
29b0f896 500/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 501static symbolS *GOT_symbol;
29b0f896 502
a4447b93
RH		 503/* The dwarf2 return column, adjusted for 32 or 64 bit. */
504unsigned int x86_dwarf2_return_column;
505
506/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
507int x86_cie_data_alignment;
508
252b5132 509/* Interface to relax_segment.
fddf5b5b
AM		 510 There are 3 major relax states for 386 jump insns because the
511 different types of jumps add different sizes to frags when we're
512 figuring out what sort of jump to choose to reach a given label. */
252b5132 513
47926f60 514/* Types. */
93c2a809
AM		 515#define UNCOND_JUMP 0
516#define COND_JUMP 1
517#define COND_JUMP86 2
fddf5b5b 518
47926f60 519/* Sizes. */
252b5132
RH		 520#define CODE16 1
521#define SMALL 0
29b0f896 522#define SMALL16 (SMALL | CODE16)
252b5132 523#define BIG 2
29b0f896 524#define BIG16 (BIG | CODE16)
252b5132
RH		 525
526#ifndef INLINE
527#ifdef __GNUC__
528#define INLINE __inline__
529#else
530#define INLINE
531#endif
532#endif
533
fddf5b5b
AM		 534#define ENCODE_RELAX_STATE(type, size) \
535 ((relax_substateT) (((type) << 2) | (size)))
536#define TYPE_FROM_RELAX_STATE(s) \
537 ((s) >> 2)
538#define DISP_SIZE_FROM_RELAX_STATE(s) \
539 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 540
541/* This table is used by relax_frag to promote short jumps to long
542 ones where necessary. SMALL (short) jumps may be promoted to BIG
543 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
544 don't allow a short jump in a 32 bit code segment to be promoted to
545 a 16 bit offset jump because it's slower (requires data size
546 prefix), and doesn't work, unless the destination is in the bottom
547 64k of the code segment (The top 16 bits of eip are zeroed). */
548
549const relax_typeS md_relax_table[] =
550{
24eab124
AM		 551 /* The fields are:
552 1) most positive reach of this state,
553 2) most negative reach of this state,
93c2a809 554 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 555 4) which index into the table to try if we can't fit into this one. */
252b5132 556
fddf5b5b 557 /* UNCOND_JUMP states. */
93c2a809
AM		 558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
560 /* dword jmp adds 4 bytes to frag:
561 0 extra opcode bytes, 4 displacement bytes. */
252b5132 562 {0, 0, 4, 0},
93c2a809
AM		 563 /* word jmp adds 2 byte2 to frag:
564 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 565 {0, 0, 2, 0},
566
93c2a809
AM		 567 /* COND_JUMP states. */
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
570 /* dword conditionals adds 5 bytes to frag:
571 1 extra opcode byte, 4 displacement bytes. */
572 {0, 0, 5, 0},
fddf5b5b 573 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 574 1 extra opcode byte, 2 displacement bytes. */
575 {0, 0, 3, 0},
576
577 /* COND_JUMP86 states. */
578 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
580 /* dword conditionals adds 5 bytes to frag:
581 1 extra opcode byte, 4 displacement bytes. */
582 {0, 0, 5, 0},
583 /* word conditionals add 4 bytes to frag:
584 1 displacement byte and a 3 byte long branch insn. */
585 {0, 0, 4, 0}
252b5132
RH		 586};
587
9103f4f4
L		 588static const arch_entry cpu_arch[] =
589{
89507696
JB		 590 /* Do not replace the first two entries - i386_target_format()
591 relies on them being there in this order. */
8a2c8fef 592 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 593 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 594 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 595 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 596 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 597 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 598 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 599 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 600 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 601 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 602 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 603 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 605 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 607 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 609 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 611 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 613 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 615 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 617 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 619 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 621 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 623 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 625 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 627 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 629 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 631 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 633 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 635 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 636 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
637 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 639 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 640 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 641 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 643 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 644 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 645 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 646 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 647 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 649 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 650 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 651 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 652 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 653 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 654 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 655 CPU_BDVER2_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 657 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 659 CPU_287_FLAGS, 0, 0 },
8a2c8fef 660 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 661 CPU_387_FLAGS, 0, 0 },
8a2c8fef 662 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 663 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 664 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 665 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 666 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 667 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 668 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 669 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 670 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 671 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 673 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 674 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 675 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 677 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 678 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 679 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 680 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 681 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 683 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 684 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 685 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 686 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
687 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 688 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 689 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 690 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 691 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 693 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 694 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 695 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 696 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 697 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 698 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 699 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 700 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 701 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 702 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 703 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 704 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 705 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 706 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 707 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 708 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 709 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 710 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
711 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 713 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 715 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 717 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 718 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 719 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 721 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 723 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 724 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
725 CPU_LZCNT_FLAGS, 0, 0 },
726 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
727 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 729 CPU_CLFLUSH_FLAGS, 0, 0 },
730 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
731 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 733 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 735 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 737 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 739 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 741 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 743 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 744 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 745 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 747 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 749 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 750 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
751 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 752 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
753 CPU_TBM_FLAGS, 0, 0 },
e413e4e9
AM		 754};
755
704209c0 756#ifdef I386COFF
a6c24e68
NC		 757/* Like s_lcomm_internal in gas/read.c but the alignment string
758 is allowed to be optional. */
759
760static symbolS *
761pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
762{
763 addressT align = 0;
764
765 SKIP_WHITESPACE ();
766
7ab9ffdd 767 if (needs_align
a6c24e68
NC		 768 && *input_line_pointer == ',')
769 {
770 align = parse_align (needs_align - 1);
7ab9ffdd 771
a6c24e68
NC		 772 if (align == (addressT) -1)
773 return NULL;
774 }
775 else
776 {
777 if (size >= 8)
778 align = 3;
779 else if (size >= 4)
780 align = 2;
781 else if (size >= 2)
782 align = 1;
783 else
784 align = 0;
785 }
786
787 bss_alloc (symbolP, size, align);
788 return symbolP;
789}
790
704209c0 791static void
a6c24e68
NC		 792pe_lcomm (int needs_align)
793{
794 s_comm_internal (needs_align * 2, pe_lcomm_internal);
795}
704209c0 796#endif
a6c24e68 797
29b0f896
AM		 798const pseudo_typeS md_pseudo_table[] =
799{
800#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
801 {"align", s_align_bytes, 0},
802#else
803 {"align", s_align_ptwo, 0},
804#endif
805 {"arch", set_cpu_arch, 0},
806#ifndef I386COFF
807 {"bss", s_bss, 0},
a6c24e68
NC		 808#else
809 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 810#endif
811 {"ffloat", float_cons, 'f'},
812 {"dfloat", float_cons, 'd'},
813 {"tfloat", float_cons, 'x'},
814 {"value", cons, 2},
d182319b 815 {"slong", signed_cons, 4},
29b0f896
AM		 816 {"noopt", s_ignore, 0},
817 {"optim", s_ignore, 0},
818 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
819 {"code16", set_code_flag, CODE_16BIT},
820 {"code32", set_code_flag, CODE_32BIT},
821 {"code64", set_code_flag, CODE_64BIT},
822 {"intel_syntax", set_intel_syntax, 1},
823 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 824 {"intel_mnemonic", set_intel_mnemonic, 1},
825 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 826 {"allow_index_reg", set_allow_index_reg, 1},
827 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 828 {"sse_check", set_sse_check, 0},
3b22753a
L		 829#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
830 {"largecomm", handle_large_common, 0},
314a59d5 831 {"quad", handle_quad, 8},
07a53e5c 832#else
e3bb37b5 833 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 834 {"loc", dwarf2_directive_loc, 0},
835 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 836#endif
6482c264
NC		 837#ifdef TE_PE
838 {"secrel32", pe_directive_secrel, 0},
839#endif
29b0f896
AM		 840 {0, 0, 0}
841};
842
843/* For interface with expression (). */
844extern char *input_line_pointer;
845
846/* Hash table for instruction mnemonic lookup. */
847static struct hash_control *op_hash;
848
849/* Hash table for register lookup. */
850static struct hash_control *reg_hash;
851\f
252b5132 852void
e3bb37b5 853i386_align_code (fragS *fragP, int count)
252b5132 854{
ce8a8b2f
AM		 855 /* Various efficient no-op patterns for aligning code labels.
856 Note: Don't try to assemble the instructions in the comments.
857 0L and 0w are not legal. */
252b5132
RH		 858 static const char f32_1[] =
859 {0x90}; /* nop */
860 static const char f32_2[] =
ccc9c027 861 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 862 static const char f32_3[] =
863 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
864 static const char f32_4[] =
865 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
866 static const char f32_5[] =
867 {0x90, /* nop */
868 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
869 static const char f32_6[] =
870 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
871 static const char f32_7[] =
872 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
873 static const char f32_8[] =
874 {0x90, /* nop */
875 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
876 static const char f32_9[] =
877 {0x89,0xf6, /* movl %esi,%esi */
878 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
879 static const char f32_10[] =
880 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
881 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
882 static const char f32_11[] =
883 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
884 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
885 static const char f32_12[] =
886 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
887 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
888 static const char f32_13[] =
889 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
890 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
891 static const char f32_14[] =
892 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
893 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 894 static const char f16_3[] =
895 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 896 static const char f16_4[] =
897 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
898 static const char f16_5[] =
899 {0x90, /* nop */
900 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
901 static const char f16_6[] =
902 {0x89,0xf6, /* mov %si,%si */
903 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
904 static const char f16_7[] =
905 {0x8d,0x74,0x00, /* lea 0(%si),%si */
906 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
907 static const char f16_8[] =
908 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
909 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 910 static const char jump_31[] =
911 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
912 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
913 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
914 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 915 static const char *const f32_patt[] = {
916 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 917 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 918 };
919 static const char *const f16_patt[] = {
76bc74dc 920 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 921 };
ccc9c027
L		 922 /* nopl (%[re]ax) */
923 static const char alt_3[] =
924 {0x0f,0x1f,0x00};
925 /* nopl 0(%[re]ax) */
926 static const char alt_4[] =
927 {0x0f,0x1f,0x40,0x00};
928 /* nopl 0(%[re]ax,%[re]ax,1) */
929 static const char alt_5[] =
930 {0x0f,0x1f,0x44,0x00,0x00};
931 /* nopw 0(%[re]ax,%[re]ax,1) */
932 static const char alt_6[] =
933 {0x66,0x0f,0x1f,0x44,0x00,0x00};
934 /* nopl 0L(%[re]ax) */
935 static const char alt_7[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
937 /* nopl 0L(%[re]ax,%[re]ax,1) */
938 static const char alt_8[] =
939 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
940 /* nopw 0L(%[re]ax,%[re]ax,1) */
941 static const char alt_9[] =
942 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
943 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
944 static const char alt_10[] =
945 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
946 /* data16
947 nopw %cs:0L(%[re]ax,%[re]ax,1) */
948 static const char alt_long_11[] =
949 {0x66,
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
951 /* data16
952 data16
953 nopw %cs:0L(%[re]ax,%[re]ax,1) */
954 static const char alt_long_12[] =
955 {0x66,
956 0x66,
957 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
958 /* data16
959 data16
960 data16
961 nopw %cs:0L(%[re]ax,%[re]ax,1) */
962 static const char alt_long_13[] =
963 {0x66,
964 0x66,
965 0x66,
966 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
967 /* data16
968 data16
969 data16
970 data16
971 nopw %cs:0L(%[re]ax,%[re]ax,1) */
972 static const char alt_long_14[] =
973 {0x66,
974 0x66,
975 0x66,
976 0x66,
977 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
978 /* data16
979 data16
980 data16
981 data16
982 data16
983 nopw %cs:0L(%[re]ax,%[re]ax,1) */
984 static const char alt_long_15[] =
985 {0x66,
986 0x66,
987 0x66,
988 0x66,
989 0x66,
990 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
991 /* nopl 0(%[re]ax,%[re]ax,1)
992 nopw 0(%[re]ax,%[re]ax,1) */
993 static const char alt_short_11[] =
994 {0x0f,0x1f,0x44,0x00,0x00,
995 0x66,0x0f,0x1f,0x44,0x00,0x00};
996 /* nopw 0(%[re]ax,%[re]ax,1)
997 nopw 0(%[re]ax,%[re]ax,1) */
998 static const char alt_short_12[] =
999 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1000 0x66,0x0f,0x1f,0x44,0x00,0x00};
1001 /* nopw 0(%[re]ax,%[re]ax,1)
1002 nopl 0L(%[re]ax) */
1003 static const char alt_short_13[] =
1004 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1005 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1006 /* nopl 0L(%[re]ax)
1007 nopl 0L(%[re]ax) */
1008 static const char alt_short_14[] =
1009 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1010 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1011 /* nopl 0L(%[re]ax)
1012 nopl 0L(%[re]ax,%[re]ax,1) */
1013 static const char alt_short_15[] =
1014 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1015 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1016 static const char *const alt_short_patt[] = {
1017 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1018 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1019 alt_short_14, alt_short_15
1020 };
1021 static const char *const alt_long_patt[] = {
1022 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1023 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1024 alt_long_14, alt_long_15
1025 };
252b5132 1026
76bc74dc
L		 1027 /* Only align for at least a positive non-zero boundary. */
1028 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1029 return;
3e73aa7c 1030
ccc9c027
L		 1031 /* We need to decide which NOP sequence to use for 32bit and
1032 64bit. When -mtune= is used:
4eed87de 1033
76bc74dc
L		 1034 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1035 PROCESSOR_GENERIC32, f32_patt will be used.
1036 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1037 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1038 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1039 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
8aedb9fe 1040 PROCESSOR_AMDFAM10, and PROCESSOR_BD, alt_short_patt
69dd9865 1041 will be used.
ccc9c027 1042
76bc74dc 1043 When -mtune= isn't used, alt_long_patt will be used if
22109423 1044 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1045 be used.
ccc9c027
L		 1046
1047 When -march= or .arch is used, we can't use anything beyond
1048 cpu_arch_isa_flags. */
1049
1050 if (flag_code == CODE_16BIT)
1051 {
ccc9c027 1052 if (count > 8)
33fef721 1053 {
76bc74dc
L		 1054 memcpy (fragP->fr_literal + fragP->fr_fix,
1055 jump_31, count);
1056 /* Adjust jump offset. */
1057 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1058 }
76bc74dc
L		 1059 else
1060 memcpy (fragP->fr_literal + fragP->fr_fix,
1061 f16_patt[count - 1], count);
252b5132 1062 }
33fef721 1063 else
ccc9c027
L		 1064 {
1065 const char *const *patt = NULL;
1066
fbf3f584 1067 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1068 {
1069 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1070 switch (cpu_arch_tune)
1071 {
1072 case PROCESSOR_UNKNOWN:
1073 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1074 optimize with nops. */
1075 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1076 patt = alt_long_patt;
ccc9c027
L		 1077 else
1078 patt = f32_patt;
1079 break;
ccc9c027
L		 1080 case PROCESSOR_PENTIUM4:
1081 case PROCESSOR_NOCONA:
ef05d495 1082 case PROCESSOR_CORE:
76bc74dc 1083 case PROCESSOR_CORE2:
bd5295b2 1084 case PROCESSOR_COREI7:
3632d14b 1085 case PROCESSOR_L1OM:
7a9068fe 1086 case PROCESSOR_K1OM:
76bc74dc
L		 1087 case PROCESSOR_GENERIC64:
1088 patt = alt_long_patt;
1089 break;
ccc9c027
L		 1090 case PROCESSOR_K6:
1091 case PROCESSOR_ATHLON:
1092 case PROCESSOR_K8:
4eed87de 1093 case PROCESSOR_AMDFAM10:
8aedb9fe 1094 case PROCESSOR_BD:
ccc9c027
L		 1095 patt = alt_short_patt;
1096 break;
76bc74dc 1097 case PROCESSOR_I386:
ccc9c027
L		 1098 case PROCESSOR_I486:
1099 case PROCESSOR_PENTIUM:
2dde1948 1100 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1101 case PROCESSOR_GENERIC32:
1102 patt = f32_patt;
1103 break;
4eed87de 1104 }
ccc9c027
L		 1105 }
1106 else
1107 {
fbf3f584 1108 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1109 {
1110 case PROCESSOR_UNKNOWN:
e6a14101 1111 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1112 PROCESSOR_UNKNOWN. */
1113 abort ();
1114 break;
1115
76bc74dc 1116 case PROCESSOR_I386:
ccc9c027
L		 1117 case PROCESSOR_I486:
1118 case PROCESSOR_PENTIUM:
ccc9c027
L		 1119 case PROCESSOR_K6:
1120 case PROCESSOR_ATHLON:
1121 case PROCESSOR_K8:
4eed87de 1122 case PROCESSOR_AMDFAM10:
8aedb9fe 1123 case PROCESSOR_BD:
ccc9c027
L		 1124 case PROCESSOR_GENERIC32:
1125 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1126 with nops. */
1127 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1128 patt = alt_short_patt;
1129 else
1130 patt = f32_patt;
1131 break;
76bc74dc
L		 1132 case PROCESSOR_PENTIUMPRO:
1133 case PROCESSOR_PENTIUM4:
1134 case PROCESSOR_NOCONA:
1135 case PROCESSOR_CORE:
ef05d495 1136 case PROCESSOR_CORE2:
bd5295b2 1137 case PROCESSOR_COREI7:
3632d14b 1138 case PROCESSOR_L1OM:
7a9068fe 1139 case PROCESSOR_K1OM:
22109423 1140 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1141 patt = alt_long_patt;
1142 else
1143 patt = f32_patt;
1144 break;
1145 case PROCESSOR_GENERIC64:
76bc74dc 1146 patt = alt_long_patt;
ccc9c027 1147 break;
4eed87de 1148 }
ccc9c027
L		 1149 }
1150
76bc74dc
L		 1151 if (patt == f32_patt)
1152 {
1153 /* If the padding is less than 15 bytes, we use the normal
1154 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1155 its offset. */
1156 int limit;
76ba9986 1157
711eedef
L		 1158 /* For 64bit, the limit is 3 bytes. */
1159 if (flag_code == CODE_64BIT
1160 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1161 limit = 3;
1162 else
1163 limit = 15;
1164 if (count < limit)
76bc74dc
L		 1165 memcpy (fragP->fr_literal + fragP->fr_fix,
1166 patt[count - 1], count);
1167 else
1168 {
1169 memcpy (fragP->fr_literal + fragP->fr_fix,
1170 jump_31, count);
1171 /* Adjust jump offset. */
1172 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1173 }
1174 }
1175 else
1176 {
1177 /* Maximum length of an instruction is 15 byte. If the
1178 padding is greater than 15 bytes and we don't use jump,
1179 we have to break it into smaller pieces. */
1180 int padding = count;
1181 while (padding > 15)
1182 {
1183 padding -= 15;
1184 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1185 patt [14], 15);
1186 }
1187
1188 if (padding)
1189 memcpy (fragP->fr_literal + fragP->fr_fix,
1190 patt [padding - 1], padding);
1191 }
ccc9c027 1192 }
33fef721 1193 fragP->fr_var = count;
252b5132
RH		 1194}
1195
c6fb90c8 1196static INLINE int
0dfbf9d7 1197operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1198{
0dfbf9d7 1199 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1200 {
1201 case 3:
0dfbf9d7 1202 if (x->array[2])
c6fb90c8
L		 1203 return 0;
1204 case 2:
0dfbf9d7 1205 if (x->array[1])
c6fb90c8
L		 1206 return 0;
1207 case 1:
0dfbf9d7 1208 return !x->array[0];
c6fb90c8
L		 1209 default:
1210 abort ();
1211 }
40fb9820
L		 1212}
1213
c6fb90c8 1214static INLINE void
0dfbf9d7 1215operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1216{
0dfbf9d7 1217 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1218 {
1219 case 3:
0dfbf9d7 1220 x->array[2] = v;
c6fb90c8 1221 case 2:
0dfbf9d7 1222 x->array[1] = v;
c6fb90c8 1223 case 1:
0dfbf9d7 1224 x->array[0] = v;
c6fb90c8
L		 1225 break;
1226 default:
1227 abort ();
1228 }
1229}
40fb9820 1230
c6fb90c8 1231static INLINE int
0dfbf9d7
L		 1232operand_type_equal (const union i386_operand_type *x,
1233 const union i386_operand_type *y)
c6fb90c8 1234{
0dfbf9d7 1235 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1236 {
1237 case 3:
0dfbf9d7 1238 if (x->array[2] != y->array[2])
c6fb90c8
L		 1239 return 0;
1240 case 2:
0dfbf9d7 1241 if (x->array[1] != y->array[1])
c6fb90c8
L		 1242 return 0;
1243 case 1:
0dfbf9d7 1244 return x->array[0] == y->array[0];
c6fb90c8
L		 1245 break;
1246 default:
1247 abort ();
1248 }
1249}
40fb9820 1250
0dfbf9d7
L		 1251static INLINE int
1252cpu_flags_all_zero (const union i386_cpu_flags *x)
1253{
1254 switch (ARRAY_SIZE(x->array))
1255 {
1256 case 3:
1257 if (x->array[2])
1258 return 0;
1259 case 2:
1260 if (x->array[1])
1261 return 0;
1262 case 1:
1263 return !x->array[0];
1264 default:
1265 abort ();
1266 }
1267}
1268
1269static INLINE void
1270cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1271{
1272 switch (ARRAY_SIZE(x->array))
1273 {
1274 case 3:
1275 x->array[2] = v;
1276 case 2:
1277 x->array[1] = v;
1278 case 1:
1279 x->array[0] = v;
1280 break;
1281 default:
1282 abort ();
1283 }
1284}
1285
1286static INLINE int
1287cpu_flags_equal (const union i386_cpu_flags *x,
1288 const union i386_cpu_flags *y)
1289{
1290 switch (ARRAY_SIZE(x->array))
1291 {
1292 case 3:
1293 if (x->array[2] != y->array[2])
1294 return 0;
1295 case 2:
1296 if (x->array[1] != y->array[1])
1297 return 0;
1298 case 1:
1299 return x->array[0] == y->array[0];
1300 break;
1301 default:
1302 abort ();
1303 }
1304}
c6fb90c8
L		 1305
1306static INLINE int
1307cpu_flags_check_cpu64 (i386_cpu_flags f)
1308{
1309 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1310 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1311}
1312
c6fb90c8
L		 1313static INLINE i386_cpu_flags
1314cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1315{
c6fb90c8
L		 1316 switch (ARRAY_SIZE (x.array))
1317 {
1318 case 3:
1319 x.array [2] &= y.array [2];
1320 case 2:
1321 x.array [1] &= y.array [1];
1322 case 1:
1323 x.array [0] &= y.array [0];
1324 break;
1325 default:
1326 abort ();
1327 }
1328 return x;
1329}
40fb9820 1330
c6fb90c8
L		 1331static INLINE i386_cpu_flags
1332cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1333{
c6fb90c8 1334 switch (ARRAY_SIZE (x.array))
40fb9820 1335 {
c6fb90c8
L		 1336 case 3:
1337 x.array [2] |= y.array [2];
1338 case 2:
1339 x.array [1] |= y.array [1];
1340 case 1:
1341 x.array [0] |= y.array [0];
40fb9820
L		 1342 break;
1343 default:
1344 abort ();
1345 }
40fb9820
L		 1346 return x;
1347}
1348
309d3373
JB		 1349static INLINE i386_cpu_flags
1350cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1351{
1352 switch (ARRAY_SIZE (x.array))
1353 {
1354 case 3:
1355 x.array [2] &= ~y.array [2];
1356 case 2:
1357 x.array [1] &= ~y.array [1];
1358 case 1:
1359 x.array [0] &= ~y.array [0];
1360 break;
1361 default:
1362 abort ();
1363 }
1364 return x;
1365}
1366
c0f3af97
L		 1367#define CPU_FLAGS_ARCH_MATCH 0x1
1368#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1369#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1370#define CPU_FLAGS_PCLMUL_MATCH 0x8
1371#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1372
a5ff0eb2 1373#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1374 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1375 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1376#define CPU_FLAGS_PERFECT_MATCH \
1377 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1378
1379/* Return CPU flags match bits. */
3629bb00 1380
40fb9820 1381static int
d3ce72d0 1382cpu_flags_match (const insn_template *t)
40fb9820 1383{
c0f3af97
L		 1384 i386_cpu_flags x = t->cpu_flags;
1385 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1386
1387 x.bitfield.cpu64 = 0;
1388 x.bitfield.cpuno64 = 0;
1389
0dfbf9d7 1390 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1391 {
1392 /* This instruction is available on all archs. */
1393 match |= CPU_FLAGS_32BIT_MATCH;
1394 }
3629bb00
L		 1395 else
1396 {
c0f3af97 1397 /* This instruction is available only on some archs. */
3629bb00
L		 1398 i386_cpu_flags cpu = cpu_arch_flags;
1399
1400 cpu.bitfield.cpu64 = 0;
1401 cpu.bitfield.cpuno64 = 0;
1402 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1403 if (!cpu_flags_all_zero (&cpu))
1404 {
a5ff0eb2
L		 1405 if (x.bitfield.cpuavx)
1406 {
ce2f5b3c 1407 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1408 if (cpu.bitfield.cpuavx)
1409 {
1410 /* Check SSE2AVX. */
1411 if (!t->opcode_modifier.sse2avx|| sse2avx)
1412 {
1413 match |= (CPU_FLAGS_ARCH_MATCH
1414 | CPU_FLAGS_AVX_MATCH);
1415 /* Check AES. */
1416 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1417 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1418 /* Check PCLMUL. */
1419 if (!x.bitfield.cpupclmul
1420 || cpu.bitfield.cpupclmul)
1421 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1422 }
1423 }
1424 else
1425 match |= CPU_FLAGS_ARCH_MATCH;
1426 }
1427 else
c0f3af97
L		 1428 match |= CPU_FLAGS_32BIT_MATCH;
1429 }
3629bb00 1430 }
c0f3af97 1431 return match;
40fb9820
L		 1432}
1433
c6fb90c8
L		 1434static INLINE i386_operand_type
1435operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1436{
c6fb90c8
L		 1437 switch (ARRAY_SIZE (x.array))
1438 {
1439 case 3:
1440 x.array [2] &= y.array [2];
1441 case 2:
1442 x.array [1] &= y.array [1];
1443 case 1:
1444 x.array [0] &= y.array [0];
1445 break;
1446 default:
1447 abort ();
1448 }
1449 return x;
40fb9820
L		 1450}
1451
c6fb90c8
L		 1452static INLINE i386_operand_type
1453operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1454{
c6fb90c8 1455 switch (ARRAY_SIZE (x.array))
40fb9820 1456 {
c6fb90c8
L		 1457 case 3:
1458 x.array [2] |= y.array [2];
1459 case 2:
1460 x.array [1] |= y.array [1];
1461 case 1:
1462 x.array [0] |= y.array [0];
40fb9820
L		 1463 break;
1464 default:
1465 abort ();
1466 }
c6fb90c8
L		 1467 return x;
1468}
40fb9820 1469
c6fb90c8
L		 1470static INLINE i386_operand_type
1471operand_type_xor (i386_operand_type x, i386_operand_type y)
1472{
1473 switch (ARRAY_SIZE (x.array))
1474 {
1475 case 3:
1476 x.array [2] ^= y.array [2];
1477 case 2:
1478 x.array [1] ^= y.array [1];
1479 case 1:
1480 x.array [0] ^= y.array [0];
1481 break;
1482 default:
1483 abort ();
1484 }
40fb9820
L		 1485 return x;
1486}
1487
1488static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1489static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1490static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1491static const i386_operand_type inoutportreg
1492 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1493static const i386_operand_type reg16_inoutportreg
1494 = OPERAND_TYPE_REG16_INOUTPORTREG;
1495static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1496static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1497static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1498static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1499static const i386_operand_type anydisp
1500 = OPERAND_TYPE_ANYDISP;
40fb9820 1501static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1502static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1503static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1504static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1505static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1506static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1507static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1508static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1509static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1510static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1511static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1512static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1513
1514enum operand_type
1515{
1516 reg,
40fb9820
L		 1517 imm,
1518 disp,
1519 anymem
1520};
1521
c6fb90c8 1522static INLINE int
40fb9820
L		 1523operand_type_check (i386_operand_type t, enum operand_type c)
1524{
1525 switch (c)
1526 {
1527 case reg:
1528 return (t.bitfield.reg8
1529 || t.bitfield.reg16
1530 || t.bitfield.reg32
1531 || t.bitfield.reg64);
1532
40fb9820
L		 1533 case imm:
1534 return (t.bitfield.imm8
1535 || t.bitfield.imm8s
1536 || t.bitfield.imm16
1537 || t.bitfield.imm32
1538 || t.bitfield.imm32s
1539 || t.bitfield.imm64);
1540
1541 case disp:
1542 return (t.bitfield.disp8
1543 || t.bitfield.disp16
1544 || t.bitfield.disp32
1545 || t.bitfield.disp32s
1546 || t.bitfield.disp64);
1547
1548 case anymem:
1549 return (t.bitfield.disp8
1550 || t.bitfield.disp16
1551 || t.bitfield.disp32
1552 || t.bitfield.disp32s
1553 || t.bitfield.disp64
1554 || t.bitfield.baseindex);
1555
1556 default:
1557 abort ();
1558 }
2cfe26b6
AM		 1559
1560 return 0;
40fb9820
L		 1561}
1562
5c07affc
L		 1563/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1564 operand J for instruction template T. */
1565
1566static INLINE int
d3ce72d0 1567match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1568{
1569 return !((i.types[j].bitfield.byte
1570 && !t->operand_types[j].bitfield.byte)
1571 || (i.types[j].bitfield.word
1572 && !t->operand_types[j].bitfield.word)
1573 || (i.types[j].bitfield.dword
1574 && !t->operand_types[j].bitfield.dword)
1575 || (i.types[j].bitfield.qword
1576 && !t->operand_types[j].bitfield.qword));
1577}
1578
1579/* Return 1 if there is no conflict in any size on operand J for
1580 instruction template T. */
1581
1582static INLINE int
d3ce72d0 1583match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1584{
1585 return (match_reg_size (t, j)
1586 && !((i.types[j].bitfield.unspecified
1587 && !t->operand_types[j].bitfield.unspecified)
1588 || (i.types[j].bitfield.fword
1589 && !t->operand_types[j].bitfield.fword)
1590 || (i.types[j].bitfield.tbyte
1591 && !t->operand_types[j].bitfield.tbyte)
1592 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1593 && !t->operand_types[j].bitfield.xmmword)
1594 || (i.types[j].bitfield.ymmword
1595 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1596}
1597
1598/* Return 1 if there is no size conflict on any operands for
1599 instruction template T. */
1600
1601static INLINE int
d3ce72d0 1602operand_size_match (const insn_template *t)
5c07affc
L		 1603{
1604 unsigned int j;
1605 int match = 1;
1606
1607 /* Don't check jump instructions. */
1608 if (t->opcode_modifier.jump
1609 || t->opcode_modifier.jumpbyte
1610 || t->opcode_modifier.jumpdword
1611 || t->opcode_modifier.jumpintersegment)
1612 return match;
1613
1614 /* Check memory and accumulator operand size. */
1615 for (j = 0; j < i.operands; j++)
1616 {
1617 if (t->operand_types[j].bitfield.anysize)
1618 continue;
1619
1620 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1621 {
1622 match = 0;
1623 break;
1624 }
1625
1626 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1627 {
1628 match = 0;
1629 break;
1630 }
1631 }
1632
891edac4 1633 if (match)
5c07affc 1634 return match;
891edac4
L		 1635 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1636 {
1637mismatch:
86e026a4 1638 i.error = operand_size_mismatch;
891edac4
L		 1639 return 0;
1640 }
5c07affc
L		 1641
1642 /* Check reverse. */
9c2799c2 1643 gas_assert (i.operands == 2);
5c07affc
L		 1644
1645 match = 1;
1646 for (j = 0; j < 2; j++)
1647 {
1648 if (t->operand_types[j].bitfield.acc
1649 && !match_reg_size (t, j ? 0 : 1))
891edac4 1650 goto mismatch;
5c07affc
L		 1651
1652 if (i.types[j].bitfield.mem
1653 && !match_mem_size (t, j ? 0 : 1))
891edac4 1654 goto mismatch;
5c07affc
L		 1655 }
1656
1657 return match;
1658}
1659
c6fb90c8 1660static INLINE int
40fb9820
L		 1661operand_type_match (i386_operand_type overlap,
1662 i386_operand_type given)
1663{
1664 i386_operand_type temp = overlap;
1665
1666 temp.bitfield.jumpabsolute = 0;
7d5e4556 1667 temp.bitfield.unspecified = 0;
5c07affc
L		 1668 temp.bitfield.byte = 0;
1669 temp.bitfield.word = 0;
1670 temp.bitfield.dword = 0;
1671 temp.bitfield.fword = 0;
1672 temp.bitfield.qword = 0;
1673 temp.bitfield.tbyte = 0;
1674 temp.bitfield.xmmword = 0;
c0f3af97 1675 temp.bitfield.ymmword = 0;
0dfbf9d7 1676 if (operand_type_all_zero (&temp))
891edac4 1677 goto mismatch;
40fb9820 1678
891edac4
L		 1679 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1680 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1681 return 1;
1682
1683mismatch:
a65babc9 1684 i.error = operand_type_mismatch;
891edac4 1685 return 0;
40fb9820
L		 1686}
1687
7d5e4556 1688/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1689 unless the expected operand type register overlap is null.
1690 Note that Acc in a template matches every size of reg. */
1691
c6fb90c8 1692static INLINE int
40fb9820
L		 1693operand_type_register_match (i386_operand_type m0,
1694 i386_operand_type g0,
1695 i386_operand_type t0,
1696 i386_operand_type m1,
1697 i386_operand_type g1,
1698 i386_operand_type t1)
1699{
1700 if (!operand_type_check (g0, reg))
1701 return 1;
1702
1703 if (!operand_type_check (g1, reg))
1704 return 1;
1705
1706 if (g0.bitfield.reg8 == g1.bitfield.reg8
1707 && g0.bitfield.reg16 == g1.bitfield.reg16
1708 && g0.bitfield.reg32 == g1.bitfield.reg32
1709 && g0.bitfield.reg64 == g1.bitfield.reg64)
1710 return 1;
1711
1712 if (m0.bitfield.acc)
1713 {
1714 t0.bitfield.reg8 = 1;
1715 t0.bitfield.reg16 = 1;
1716 t0.bitfield.reg32 = 1;
1717 t0.bitfield.reg64 = 1;
1718 }
1719
1720 if (m1.bitfield.acc)
1721 {
1722 t1.bitfield.reg8 = 1;
1723 t1.bitfield.reg16 = 1;
1724 t1.bitfield.reg32 = 1;
1725 t1.bitfield.reg64 = 1;
1726 }
1727
891edac4
L		 1728 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1729 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1730 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1731 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1732 return 1;
1733
a65babc9 1734 i.error = register_type_mismatch;
891edac4
L		 1735
1736 return 0;
40fb9820
L		 1737}
1738
252b5132 1739static INLINE unsigned int
40fb9820 1740mode_from_disp_size (i386_operand_type t)
252b5132 1741{
40fb9820
L		 1742 if (t.bitfield.disp8)
1743 return 1;
1744 else if (t.bitfield.disp16
1745 || t.bitfield.disp32
1746 || t.bitfield.disp32s)
1747 return 2;
1748 else
1749 return 0;
252b5132
RH		 1750}
1751
1752static INLINE int
e3bb37b5 1753fits_in_signed_byte (offsetT num)
252b5132
RH		 1754{
1755 return (num >= -128) && (num <= 127);
47926f60 1756}
252b5132
RH		 1757
1758static INLINE int
e3bb37b5 1759fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1760{
1761 return (num & 0xff) == num;
47926f60 1762}
252b5132
RH		 1763
1764static INLINE int
e3bb37b5 1765fits_in_unsigned_word (offsetT num)
252b5132
RH		 1766{
1767 return (num & 0xffff) == num;
47926f60 1768}
252b5132
RH		 1769
1770static INLINE int
e3bb37b5 1771fits_in_signed_word (offsetT num)
252b5132
RH		 1772{
1773 return (-32768 <= num) && (num <= 32767);
47926f60 1774}
2a962e6d 1775
3e73aa7c 1776static INLINE int
e3bb37b5 1777fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1778{
1779#ifndef BFD64
1780 return 1;
1781#else
1782 return (!(((offsetT) -1 << 31) & num)
1783 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1784#endif
1785} /* fits_in_signed_long() */
2a962e6d 1786
3e73aa7c 1787static INLINE int
e3bb37b5 1788fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1789{
1790#ifndef BFD64
1791 return 1;
1792#else
1793 return (num & (((offsetT) 2 << 31) - 1)) == num;
1794#endif
1795} /* fits_in_unsigned_long() */
252b5132 1796
a683cc34
SP		 1797static INLINE int
1798fits_in_imm4 (offsetT num)
1799{
1800 return (num & 0xf) == num;
1801}
1802
40fb9820 1803static i386_operand_type
e3bb37b5 1804smallest_imm_type (offsetT num)
252b5132 1805{
40fb9820 1806 i386_operand_type t;
7ab9ffdd 1807
0dfbf9d7 1808 operand_type_set (&t, 0);
40fb9820
L		 1809 t.bitfield.imm64 = 1;
1810
1811 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1812 {
1813 /* This code is disabled on the 486 because all the Imm1 forms
1814 in the opcode table are slower on the i486. They're the
1815 versions with the implicitly specified single-position
1816 displacement, which has another syntax if you really want to
1817 use that form. */
40fb9820
L		 1818 t.bitfield.imm1 = 1;
1819 t.bitfield.imm8 = 1;
1820 t.bitfield.imm8s = 1;
1821 t.bitfield.imm16 = 1;
1822 t.bitfield.imm32 = 1;
1823 t.bitfield.imm32s = 1;
1824 }
1825 else if (fits_in_signed_byte (num))
1826 {
1827 t.bitfield.imm8 = 1;
1828 t.bitfield.imm8s = 1;
1829 t.bitfield.imm16 = 1;
1830 t.bitfield.imm32 = 1;
1831 t.bitfield.imm32s = 1;
1832 }
1833 else if (fits_in_unsigned_byte (num))
1834 {
1835 t.bitfield.imm8 = 1;
1836 t.bitfield.imm16 = 1;
1837 t.bitfield.imm32 = 1;
1838 t.bitfield.imm32s = 1;
1839 }
1840 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1841 {
1842 t.bitfield.imm16 = 1;
1843 t.bitfield.imm32 = 1;
1844 t.bitfield.imm32s = 1;
1845 }
1846 else if (fits_in_signed_long (num))
1847 {
1848 t.bitfield.imm32 = 1;
1849 t.bitfield.imm32s = 1;
1850 }
1851 else if (fits_in_unsigned_long (num))
1852 t.bitfield.imm32 = 1;
1853
1854 return t;
47926f60 1855}
252b5132 1856
847f7ad4 1857static offsetT
e3bb37b5 1858offset_in_range (offsetT val, int size)
847f7ad4 1859{
508866be 1860 addressT mask;
ba2adb93 1861
847f7ad4
AM		 1862 switch (size)
1863 {
508866be
L		 1864 case 1: mask = ((addressT) 1 << 8) - 1; break;
1865 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1866 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1867#ifdef BFD64
1868 case 8: mask = ((addressT) 2 << 63) - 1; break;
1869#endif
47926f60 1870 default: abort ();
847f7ad4
AM		 1871 }
1872
9de868bf
L		 1873#ifdef BFD64
1874 /* If BFD64, sign extend val for 32bit address mode. */
1875 if (flag_code != CODE_64BIT
1876 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1877 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1878 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1879#endif
ba2adb93 1880
47926f60 1881 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1882 {
1883 char buf1[40], buf2[40];
1884
1885 sprint_value (buf1, val);
1886 sprint_value (buf2, val & mask);
1887 as_warn (_("%s shortened to %s"), buf1, buf2);
1888 }
1889 return val & mask;
1890}
1891
c32fa91d
L		 1892enum PREFIX_GROUP
1893{
1894 PREFIX_EXIST = 0,
1895 PREFIX_LOCK,
1896 PREFIX_REP,
1897 PREFIX_OTHER
1898};
1899
1900/* Returns
1901 a. PREFIX_EXIST if attempting to add a prefix where one from the
1902 same class already exists.
1903 b. PREFIX_LOCK if lock prefix is added.
1904 c. PREFIX_REP if rep/repne prefix is added.
1905 d. PREFIX_OTHER if other prefix is added.
1906 */
1907
1908static enum PREFIX_GROUP
e3bb37b5 1909add_prefix (unsigned int prefix)
252b5132 1910{
c32fa91d 1911 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1912 unsigned int q;
252b5132 1913
29b0f896
AM		 1914 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1915 && flag_code == CODE_64BIT)
b1905489 1916 {
161a04f6
L		 1917 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1918 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1919 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1920 ret = PREFIX_EXIST;
b1905489
JB		 1921 q = REX_PREFIX;
1922 }
3e73aa7c 1923 else
b1905489
JB		 1924 {
1925 switch (prefix)
1926 {
1927 default:
1928 abort ();
1929
1930 case CS_PREFIX_OPCODE:
1931 case DS_PREFIX_OPCODE:
1932 case ES_PREFIX_OPCODE:
1933 case FS_PREFIX_OPCODE:
1934 case GS_PREFIX_OPCODE:
1935 case SS_PREFIX_OPCODE:
1936 q = SEG_PREFIX;
1937 break;
1938
1939 case REPNE_PREFIX_OPCODE:
1940 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1941 q = REP_PREFIX;
1942 ret = PREFIX_REP;
1943 break;
1944
b1905489 1945 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1946 q = LOCK_PREFIX;
1947 ret = PREFIX_LOCK;
b1905489
JB		 1948 break;
1949
1950 case FWAIT_OPCODE:
1951 q = WAIT_PREFIX;
1952 break;
1953
1954 case ADDR_PREFIX_OPCODE:
1955 q = ADDR_PREFIX;
1956 break;
1957
1958 case DATA_PREFIX_OPCODE:
1959 q = DATA_PREFIX;
1960 break;
1961 }
1962 if (i.prefix[q] != 0)
c32fa91d 1963 ret = PREFIX_EXIST;
b1905489 1964 }
252b5132 1965
b1905489 1966 if (ret)
252b5132 1967 {
b1905489
JB		 1968 if (!i.prefix[q])
1969 ++i.prefixes;
1970 i.prefix[q] |= prefix;
252b5132 1971 }
b1905489
JB		 1972 else
1973 as_bad (_("same type of prefix used twice"));
252b5132 1974
252b5132
RH		 1975 return ret;
1976}
1977
1978static void
78f12dd3 1979update_code_flag (int value, int check)
eecb386c 1980{
78f12dd3
L		 1981 PRINTF_LIKE ((*as_error));
1982
1e9cc1c2 1983 flag_code = (enum flag_code) value;
40fb9820
L		 1984 if (flag_code == CODE_64BIT)
1985 {
1986 cpu_arch_flags.bitfield.cpu64 = 1;
1987 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1988 }
1989 else
1990 {
1991 cpu_arch_flags.bitfield.cpu64 = 0;
1992 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1993 }
1994 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1995 {
78f12dd3
L		 1996 if (check)
1997 as_error = as_fatal;
1998 else
1999 as_error = as_bad;
2000 (*as_error) (_("64bit mode not supported on `%s'."),
2001 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2002 }
40fb9820 2003 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2004 {
78f12dd3
L		 2005 if (check)
2006 as_error = as_fatal;
2007 else
2008 as_error = as_bad;
2009 (*as_error) (_("32bit mode not supported on `%s'."),
2010 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2011 }
eecb386c
AM		 2012 stackop_size = '\0';
2013}
2014
78f12dd3
L		 2015static void
2016set_code_flag (int value)
2017{
2018 update_code_flag (value, 0);
2019}
2020
eecb386c 2021static void
e3bb37b5 2022set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2023{
1e9cc1c2 2024 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2025 if (flag_code != CODE_16BIT)
2026 abort ();
2027 cpu_arch_flags.bitfield.cpu64 = 0;
2028 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2029 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2030}
2031
2032static void
e3bb37b5 2033set_intel_syntax (int syntax_flag)
252b5132
RH		 2034{
2035 /* Find out if register prefixing is specified. */
2036 int ask_naked_reg = 0;
2037
2038 SKIP_WHITESPACE ();
29b0f896 2039 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2040 {
2041 char *string = input_line_pointer;
2042 int e = get_symbol_end ();
2043
47926f60 2044 if (strcmp (string, "prefix") == 0)
252b5132 2045 ask_naked_reg = 1;
47926f60 2046 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2047 ask_naked_reg = -1;
2048 else
d0b47220 2049 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2050 *input_line_pointer = e;
2051 }
2052 demand_empty_rest_of_line ();
c3332e24 2053
252b5132
RH		 2054 intel_syntax = syntax_flag;
2055
2056 if (ask_naked_reg == 0)
f86103b7
AM		 2057 allow_naked_reg = (intel_syntax
2058 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2059 else
2060 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2061
ee86248c 2062 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2063
e4a3b5a4 2064 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2065 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2066 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2067}
2068
1efbbeb4
L		 2069static void
2070set_intel_mnemonic (int mnemonic_flag)
2071{
e1d4d893 2072 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2073}
2074
db51cc60
L		 2075static void
2076set_allow_index_reg (int flag)
2077{
2078 allow_index_reg = flag;
2079}
2080
cb19c032
L		 2081static void
2082set_sse_check (int dummy ATTRIBUTE_UNUSED)
2083{
2084 SKIP_WHITESPACE ();
2085
2086 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2087 {
2088 char *string = input_line_pointer;
2089 int e = get_symbol_end ();
2090
2091 if (strcmp (string, "none") == 0)
2092 sse_check = sse_check_none;
2093 else if (strcmp (string, "warning") == 0)
2094 sse_check = sse_check_warning;
2095 else if (strcmp (string, "error") == 0)
2096 sse_check = sse_check_error;
2097 else
2098 as_bad (_("bad argument to sse_check directive."));
2099 *input_line_pointer = e;
2100 }
2101 else
2102 as_bad (_("missing argument for sse_check directive"));
2103
2104 demand_empty_rest_of_line ();
2105}
2106
8a9036a4
L		 2107static void
2108check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2109 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2110{
2111#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2112 static const char *arch;
2113
2114 /* Intel LIOM is only supported on ELF. */
2115 if (!IS_ELF)
2116 return;
2117
2118 if (!arch)
2119 {
2120 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2121 use default_arch. */
2122 arch = cpu_arch_name;
2123 if (!arch)
2124 arch = default_arch;
2125 }
2126
3632d14b 2127 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2128 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2129 || new_flag.bitfield.cpul1om)
8a9036a4 2130 return;
76ba9986 2131
7a9068fe
L		 2132 /* If we are targeting Intel K1OM, we must enable it. */
2133 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2134 || new_flag.bitfield.cpuk1om)
2135 return;
2136
8a9036a4
L		 2137 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2138#endif
2139}
2140
e413e4e9 2141static void
e3bb37b5 2142set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2143{
47926f60 2144 SKIP_WHITESPACE ();
e413e4e9 2145
29b0f896 2146 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2147 {
2148 char *string = input_line_pointer;
2149 int e = get_symbol_end ();
91d6fa6a 2150 unsigned int j;
40fb9820 2151 i386_cpu_flags flags;
e413e4e9 2152
91d6fa6a 2153 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2154 {
91d6fa6a 2155 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2156 {
91d6fa6a 2157 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2158
5c6af06e
JB		 2159 if (*string != '.')
2160 {
91d6fa6a 2161 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2162 cpu_sub_arch_name = NULL;
91d6fa6a 2163 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2164 if (flag_code == CODE_64BIT)
2165 {
2166 cpu_arch_flags.bitfield.cpu64 = 1;
2167 cpu_arch_flags.bitfield.cpuno64 = 0;
2168 }
2169 else
2170 {
2171 cpu_arch_flags.bitfield.cpu64 = 0;
2172 cpu_arch_flags.bitfield.cpuno64 = 1;
2173 }
91d6fa6a
NC		 2174 cpu_arch_isa = cpu_arch[j].type;
2175 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2176 if (!cpu_arch_tune_set)
2177 {
2178 cpu_arch_tune = cpu_arch_isa;
2179 cpu_arch_tune_flags = cpu_arch_isa_flags;
2180 }
5c6af06e
JB		 2181 break;
2182 }
40fb9820 2183
22109423 2184 if (!cpu_arch[j].negated)
309d3373 2185 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2186 cpu_arch[j].flags);
309d3373
JB		 2187 else
2188 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2189 cpu_arch[j].flags);
0dfbf9d7 2190 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2191 {
6305a203
L		 2192 if (cpu_sub_arch_name)
2193 {
2194 char *name = cpu_sub_arch_name;
2195 cpu_sub_arch_name = concat (name,
91d6fa6a 2196 cpu_arch[j].name,
1bf57e9f 2197 (const char *) NULL);
6305a203
L		 2198 free (name);
2199 }
2200 else
91d6fa6a 2201 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2202 cpu_arch_flags = flags;
a586129e 2203 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2204 }
2205 *input_line_pointer = e;
2206 demand_empty_rest_of_line ();
2207 return;
e413e4e9
AM		 2208 }
2209 }
91d6fa6a 2210 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2211 as_bad (_("no such architecture: `%s'"), string);
2212
2213 *input_line_pointer = e;
2214 }
2215 else
2216 as_bad (_("missing cpu architecture"));
2217
fddf5b5b
AM		 2218 no_cond_jump_promotion = 0;
2219 if (*input_line_pointer == ','
29b0f896 2220 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2221 {
2222 char *string = ++input_line_pointer;
2223 int e = get_symbol_end ();
2224
2225 if (strcmp (string, "nojumps") == 0)
2226 no_cond_jump_promotion = 1;
2227 else if (strcmp (string, "jumps") == 0)
2228 ;
2229 else
2230 as_bad (_("no such architecture modifier: `%s'"), string);
2231
2232 *input_line_pointer = e;
2233 }
2234
e413e4e9
AM		 2235 demand_empty_rest_of_line ();
2236}
2237
8a9036a4
L		 2238enum bfd_architecture
2239i386_arch (void)
2240{
3632d14b 2241 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2242 {
2243 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2244 || flag_code != CODE_64BIT)
2245 as_fatal (_("Intel L1OM is 64bit ELF only"));
2246 return bfd_arch_l1om;
2247 }
7a9068fe
L		 2248 else if (cpu_arch_isa == PROCESSOR_K1OM)
2249 {
2250 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2251 || flag_code != CODE_64BIT)
2252 as_fatal (_("Intel K1OM is 64bit ELF only"));
2253 return bfd_arch_k1om;
2254 }
8a9036a4
L		 2255 else
2256 return bfd_arch_i386;
2257}
2258
b9d79e03 2259unsigned long
7016a5d5 2260i386_mach (void)
b9d79e03 2261{
351f65ca 2262 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2263 {
3632d14b 2264 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2265 {
351f65ca
L		 2266 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2267 || default_arch[6] != '\0')
8a9036a4
L		 2268 as_fatal (_("Intel L1OM is 64bit ELF only"));
2269 return bfd_mach_l1om;
2270 }
7a9068fe
L		 2271 else if (cpu_arch_isa == PROCESSOR_K1OM)
2272 {
2273 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2274 || default_arch[6] != '\0')
2275 as_fatal (_("Intel K1OM is 64bit ELF only"));
2276 return bfd_mach_k1om;
2277 }
351f65ca 2278 else if (default_arch[6] == '\0')
8a9036a4 2279 return bfd_mach_x86_64;
351f65ca
L		 2280 else
2281 return bfd_mach_x64_32;
8a9036a4 2282 }
b9d79e03
JH		 2283 else if (!strcmp (default_arch, "i386"))
2284 return bfd_mach_i386_i386;
2285 else
2b5d6a91 2286 as_fatal (_("unknown architecture"));
b9d79e03 2287}
b9d79e03 2288\f
252b5132 2289void
7016a5d5 2290md_begin (void)
252b5132
RH		 2291{
2292 const char *hash_err;
2293
47926f60 2294 /* Initialize op_hash hash table. */
252b5132
RH		 2295 op_hash = hash_new ();
2296
2297 {
d3ce72d0 2298 const insn_template *optab;
29b0f896 2299 templates *core_optab;
252b5132 2300
47926f60
KH		 2301 /* Setup for loop. */
2302 optab = i386_optab;
252b5132
RH		 2303 core_optab = (templates *) xmalloc (sizeof (templates));
2304 core_optab->start = optab;
2305
2306 while (1)
2307 {
2308 ++optab;
2309 if (optab->name == NULL
2310 || strcmp (optab->name, (optab - 1)->name) != 0)
2311 {
2312 /* different name --> ship out current template list;
47926f60 2313 add to hash table; & begin anew. */
252b5132
RH		 2314 core_optab->end = optab;
2315 hash_err = hash_insert (op_hash,
2316 (optab - 1)->name,
5a49b8ac 2317 (void *) core_optab);
252b5132
RH		 2318 if (hash_err)
2319 {
2b5d6a91 2320 as_fatal (_("internal Error: Can't hash %s: %s"),
252b5132
RH		 2321 (optab - 1)->name,
2322 hash_err);
2323 }
2324 if (optab->name == NULL)
2325 break;
2326 core_optab = (templates *) xmalloc (sizeof (templates));
2327 core_optab->start = optab;
2328 }
2329 }
2330 }
2331
47926f60 2332 /* Initialize reg_hash hash table. */
252b5132
RH		 2333 reg_hash = hash_new ();
2334 {
29b0f896 2335 const reg_entry *regtab;
c3fe08fa 2336 unsigned int regtab_size = i386_regtab_size;
252b5132 2337
c3fe08fa 2338 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2339 {
5a49b8ac 2340 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2341 if (hash_err)
2b5d6a91 2342 as_fatal (_("internal Error: Can't hash %s: %s"),
3e73aa7c
JH		 2343 regtab->reg_name,
2344 hash_err);
252b5132
RH		 2345 }
2346 }
2347
47926f60 2348 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2349 {
29b0f896
AM		 2350 int c;
2351 char *p;
252b5132
RH		 2352
2353 for (c = 0; c < 256; c++)
2354 {
3882b010 2355 if (ISDIGIT (c))
252b5132
RH		 2356 {
2357 digit_chars[c] = c;
2358 mnemonic_chars[c] = c;
2359 register_chars[c] = c;
2360 operand_chars[c] = c;
2361 }
3882b010 2362 else if (ISLOWER (c))
252b5132
RH		 2363 {
2364 mnemonic_chars[c] = c;
2365 register_chars[c] = c;
2366 operand_chars[c] = c;
2367 }
3882b010 2368 else if (ISUPPER (c))
252b5132 2369 {
3882b010 2370 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2371 register_chars[c] = mnemonic_chars[c];
2372 operand_chars[c] = c;
2373 }
2374
3882b010 2375 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2376 identifier_chars[c] = c;
2377 else if (c >= 128)
2378 {
2379 identifier_chars[c] = c;
2380 operand_chars[c] = c;
2381 }
2382 }
2383
2384#ifdef LEX_AT
2385 identifier_chars['@'] = '@';
32137342
NC		 2386#endif
2387#ifdef LEX_QM
2388 identifier_chars['?'] = '?';
2389 operand_chars['?'] = '?';
252b5132 2390#endif
252b5132 2391 digit_chars['-'] = '-';
c0f3af97 2392 mnemonic_chars['_'] = '_';
791fe849 2393 mnemonic_chars['-'] = '-';
0003779b 2394 mnemonic_chars['.'] = '.';
252b5132
RH		 2395 identifier_chars['_'] = '_';
2396 identifier_chars['.'] = '.';
2397
2398 for (p = operand_special_chars; *p != '\0'; p++)
2399 operand_chars[(unsigned char) *p] = *p;
2400 }
2401
2402#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2403 if (IS_ELF)
252b5132
RH		 2404 {
2405 record_alignment (text_section, 2);
2406 record_alignment (data_section, 2);
2407 record_alignment (bss_section, 2);
2408 }
2409#endif
a4447b93
RH		 2410
2411 if (flag_code == CODE_64BIT)
2412 {
ca19b261
KT		 2413#if defined (OBJ_COFF) && defined (TE_PE)
2414 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2415 ? 32 : 16);
2416#else
a4447b93 2417 x86_dwarf2_return_column = 16;
ca19b261 2418#endif
61ff971f 2419 x86_cie_data_alignment = -8;
a4447b93
RH		 2420 }
2421 else
2422 {
2423 x86_dwarf2_return_column = 8;
2424 x86_cie_data_alignment = -4;
2425 }
252b5132
RH		 2426}
2427
2428void
e3bb37b5 2429i386_print_statistics (FILE *file)
252b5132
RH		 2430{
2431 hash_print_statistics (file, "i386 opcode", op_hash);
2432 hash_print_statistics (file, "i386 register", reg_hash);
2433}
2434\f
252b5132
RH		 2435#ifdef DEBUG386
2436
ce8a8b2f 2437/* Debugging routines for md_assemble. */
d3ce72d0 2438static void pte (insn_template *);
40fb9820 2439static void pt (i386_operand_type);
e3bb37b5
L		 2440static void pe (expressionS *);
2441static void ps (symbolS *);
252b5132
RH		 2442
2443static void
e3bb37b5 2444pi (char *line, i386_insn *x)
252b5132 2445{
09137c09 2446 unsigned int j;
252b5132
RH		 2447
2448 fprintf (stdout, "%s: template ", line);
2449 pte (&x->tm);
09f131f2
JH		 2450 fprintf (stdout, " address: base %s index %s scale %x\n",
2451 x->base_reg ? x->base_reg->reg_name : "none",
2452 x->index_reg ? x->index_reg->reg_name : "none",
2453 x->log2_scale_factor);
2454 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2455 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2456 fprintf (stdout, " sib: base %x index %x scale %x\n",
2457 x->sib.base, x->sib.index, x->sib.scale);
2458 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2459 (x->rex & REX_W) != 0,
2460 (x->rex & REX_R) != 0,
2461 (x->rex & REX_X) != 0,
2462 (x->rex & REX_B) != 0);
09137c09 2463 for (j = 0; j < x->operands; j++)
252b5132 2464 {
09137c09
SP		 2465 fprintf (stdout, " #%d: ", j + 1);
2466 pt (x->types[j]);
252b5132 2467 fprintf (stdout, "\n");
09137c09
SP		 2468 if (x->types[j].bitfield.reg8
2469 || x->types[j].bitfield.reg16
2470 || x->types[j].bitfield.reg32
2471 || x->types[j].bitfield.reg64
2472 || x->types[j].bitfield.regmmx
2473 || x->types[j].bitfield.regxmm
2474 || x->types[j].bitfield.regymm
2475 || x->types[j].bitfield.sreg2
2476 || x->types[j].bitfield.sreg3
2477 || x->types[j].bitfield.control
2478 || x->types[j].bitfield.debug
2479 || x->types[j].bitfield.test)
2480 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2481 if (operand_type_check (x->types[j], imm))
2482 pe (x->op[j].imms);
2483 if (operand_type_check (x->types[j], disp))
2484 pe (x->op[j].disps);
252b5132
RH		 2485 }
2486}
2487
2488static void
d3ce72d0 2489pte (insn_template *t)
252b5132 2490{
09137c09 2491 unsigned int j;
252b5132 2492 fprintf (stdout, " %d operands ", t->operands);
47926f60 2493 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2494 if (t->extension_opcode != None)
2495 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2496 if (t->opcode_modifier.d)
252b5132 2497 fprintf (stdout, "D");
40fb9820 2498 if (t->opcode_modifier.w)
252b5132
RH		 2499 fprintf (stdout, "W");
2500 fprintf (stdout, "\n");
09137c09 2501 for (j = 0; j < t->operands; j++)
252b5132 2502 {
09137c09
SP		 2503 fprintf (stdout, " #%d type ", j + 1);
2504 pt (t->operand_types[j]);
252b5132
RH		 2505 fprintf (stdout, "\n");
2506 }
2507}
2508
2509static void
e3bb37b5 2510pe (expressionS *e)
252b5132 2511{
24eab124 2512 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2513 fprintf (stdout, " add_number %ld (%lx)\n",
2514 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2515 if (e->X_add_symbol)
2516 {
2517 fprintf (stdout, " add_symbol ");
2518 ps (e->X_add_symbol);
2519 fprintf (stdout, "\n");
2520 }
2521 if (e->X_op_symbol)
2522 {
2523 fprintf (stdout, " op_symbol ");
2524 ps (e->X_op_symbol);
2525 fprintf (stdout, "\n");
2526 }
2527}
2528
2529static void
e3bb37b5 2530ps (symbolS *s)
252b5132
RH		 2531{
2532 fprintf (stdout, "%s type %s%s",
2533 S_GET_NAME (s),
2534 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2535 segment_name (S_GET_SEGMENT (s)));
2536}
2537
7b81dfbb 2538static struct type_name
252b5132 2539 {
40fb9820
L		 2540 i386_operand_type mask;
2541 const char *name;
252b5132 2542 }
7b81dfbb 2543const type_names[] =
252b5132 2544{
40fb9820
L		 2545 { OPERAND_TYPE_REG8, "r8" },
2546 { OPERAND_TYPE_REG16, "r16" },
2547 { OPERAND_TYPE_REG32, "r32" },
2548 { OPERAND_TYPE_REG64, "r64" },
2549 { OPERAND_TYPE_IMM8, "i8" },
2550 { OPERAND_TYPE_IMM8, "i8s" },
2551 { OPERAND_TYPE_IMM16, "i16" },
2552 { OPERAND_TYPE_IMM32, "i32" },
2553 { OPERAND_TYPE_IMM32S, "i32s" },
2554 { OPERAND_TYPE_IMM64, "i64" },
2555 { OPERAND_TYPE_IMM1, "i1" },
2556 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2557 { OPERAND_TYPE_DISP8, "d8" },
2558 { OPERAND_TYPE_DISP16, "d16" },
2559 { OPERAND_TYPE_DISP32, "d32" },
2560 { OPERAND_TYPE_DISP32S, "d32s" },
2561 { OPERAND_TYPE_DISP64, "d64" },
2562 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2563 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2564 { OPERAND_TYPE_CONTROL, "control reg" },
2565 { OPERAND_TYPE_TEST, "test reg" },
2566 { OPERAND_TYPE_DEBUG, "debug reg" },
2567 { OPERAND_TYPE_FLOATREG, "FReg" },
2568 { OPERAND_TYPE_FLOATACC, "FAcc" },
2569 { OPERAND_TYPE_SREG2, "SReg2" },
2570 { OPERAND_TYPE_SREG3, "SReg3" },
2571 { OPERAND_TYPE_ACC, "Acc" },
2572 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2573 { OPERAND_TYPE_REGMMX, "rMMX" },
2574 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2575 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2576 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2577};
2578
2579static void
40fb9820 2580pt (i386_operand_type t)
252b5132 2581{
40fb9820 2582 unsigned int j;
c6fb90c8 2583 i386_operand_type a;
252b5132 2584
40fb9820 2585 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2586 {
2587 a = operand_type_and (t, type_names[j].mask);
0349dc08 2588 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2589 fprintf (stdout, "%s, ", type_names[j].name);
2590 }
252b5132
RH		 2591 fflush (stdout);
2592}
2593
2594#endif /* DEBUG386 */
2595\f
252b5132 2596static bfd_reloc_code_real_type
3956db08 2597reloc (unsigned int size,
64e74474
AM		 2598 int pcrel,
2599 int sign,
2600 bfd_reloc_code_real_type other)
252b5132 2601{
47926f60 2602 if (other != NO_RELOC)
3956db08 2603 {
91d6fa6a 2604 reloc_howto_type *rel;
3956db08
JB		 2605
2606 if (size == 8)
2607 switch (other)
2608 {
64e74474
AM		 2609 case BFD_RELOC_X86_64_GOT32:
2610 return BFD_RELOC_X86_64_GOT64;
2611 break;
2612 case BFD_RELOC_X86_64_PLTOFF64:
2613 return BFD_RELOC_X86_64_PLTOFF64;
2614 break;
2615 case BFD_RELOC_X86_64_GOTPC32:
2616 other = BFD_RELOC_X86_64_GOTPC64;
2617 break;
2618 case BFD_RELOC_X86_64_GOTPCREL:
2619 other = BFD_RELOC_X86_64_GOTPCREL64;
2620 break;
2621 case BFD_RELOC_X86_64_TPOFF32:
2622 other = BFD_RELOC_X86_64_TPOFF64;
2623 break;
2624 case BFD_RELOC_X86_64_DTPOFF32:
2625 other = BFD_RELOC_X86_64_DTPOFF64;
2626 break;
2627 default:
2628 break;
3956db08 2629 }
e05278af
JB		 2630
2631 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2632 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2633 sign = -1;
2634
91d6fa6a
NC		 2635 rel = bfd_reloc_type_lookup (stdoutput, other);
2636 if (!rel)
3956db08 2637 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2638 else if (size != bfd_get_reloc_size (rel))
3956db08 2639 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2640 bfd_get_reloc_size (rel),
3956db08 2641 size);
91d6fa6a 2642 else if (pcrel && !rel->pc_relative)
3956db08 2643 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2644 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2645 && !sign)
91d6fa6a 2646 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2647 && sign > 0))
3956db08
JB		 2648 as_bad (_("relocated field and relocation type differ in signedness"));
2649 else
2650 return other;
2651 return NO_RELOC;
2652 }
252b5132
RH		 2653
2654 if (pcrel)
2655 {
3e73aa7c 2656 if (!sign)
3956db08 2657 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2658 switch (size)
2659 {
2660 case 1: return BFD_RELOC_8_PCREL;
2661 case 2: return BFD_RELOC_16_PCREL;
2662 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2663 case 8: return BFD_RELOC_64_PCREL;
252b5132 2664 }
3956db08 2665 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2666 }
2667 else
2668 {
3956db08 2669 if (sign > 0)
e5cb08ac 2670 switch (size)
3e73aa7c
JH		 2671 {
2672 case 4: return BFD_RELOC_X86_64_32S;
2673 }
2674 else
2675 switch (size)
2676 {
2677 case 1: return BFD_RELOC_8;
2678 case 2: return BFD_RELOC_16;
2679 case 4: return BFD_RELOC_32;
2680 case 8: return BFD_RELOC_64;
2681 }
3956db08
JB		 2682 as_bad (_("cannot do %s %u byte relocation"),
2683 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2684 }
2685
0cc9e1d3 2686 return NO_RELOC;
252b5132
RH		 2687}
2688
47926f60
KH		 2689/* Here we decide which fixups can be adjusted to make them relative to
2690 the beginning of the section instead of the symbol. Basically we need
2691 to make sure that the dynamic relocations are done correctly, so in
2692 some cases we force the original symbol to be used. */
2693
252b5132 2694int
e3bb37b5 2695tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2696{
6d249963 2697#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2698 if (!IS_ELF)
31312f95
AM		 2699 return 1;
2700
a161fe53
AM		 2701 /* Don't adjust pc-relative references to merge sections in 64-bit
2702 mode. */
2703 if (use_rela_relocations
2704 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2705 && fixP->fx_pcrel)
252b5132 2706 return 0;
31312f95 2707
8d01d9a9
AJ		 2708 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2709 and changed later by validate_fix. */
2710 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2711 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2712 return 0;
2713
ce8a8b2f 2714 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2715 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2716 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2717 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2718 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2719 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2720 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2721 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2722 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2723 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2724 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2725 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2726 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2727 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2728 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2729 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2730 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2731 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2732 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2733 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2734 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2735 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2736 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2737 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2738 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2739 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2740 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2741 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2742 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2743 return 0;
31312f95 2744#endif
252b5132
RH		 2745 return 1;
2746}
252b5132 2747
b4cac588 2748static int
e3bb37b5 2749intel_float_operand (const char *mnemonic)
252b5132 2750{
9306ca4a
JB		 2751 /* Note that the value returned is meaningful only for opcodes with (memory)
2752 operands, hence the code here is free to improperly handle opcodes that
2753 have no operands (for better performance and smaller code). */
2754
2755 if (mnemonic[0] != 'f')
2756 return 0; /* non-math */
2757
2758 switch (mnemonic[1])
2759 {
2760 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2761 the fs segment override prefix not currently handled because no
2762 call path can make opcodes without operands get here */
2763 case 'i':
2764 return 2 /* integer op */;
2765 case 'l':
2766 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2767 return 3; /* fldcw/fldenv */
2768 break;
2769 case 'n':
2770 if (mnemonic[2] != 'o' /* fnop */)
2771 return 3; /* non-waiting control op */
2772 break;
2773 case 'r':
2774 if (mnemonic[2] == 's')
2775 return 3; /* frstor/frstpm */
2776 break;
2777 case 's':
2778 if (mnemonic[2] == 'a')
2779 return 3; /* fsave */
2780 if (mnemonic[2] == 't')
2781 {
2782 switch (mnemonic[3])
2783 {
2784 case 'c': /* fstcw */
2785 case 'd': /* fstdw */
2786 case 'e': /* fstenv */
2787 case 's': /* fsts[gw] */
2788 return 3;
2789 }
2790 }
2791 break;
2792 case 'x':
2793 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2794 return 0; /* fxsave/fxrstor are not really math ops */
2795 break;
2796 }
252b5132 2797
9306ca4a 2798 return 1;
252b5132
RH		 2799}
2800
c0f3af97
L		 2801/* Build the VEX prefix. */
2802
2803static void
d3ce72d0 2804build_vex_prefix (const insn_template *t)
c0f3af97
L		 2805{
2806 unsigned int register_specifier;
2807 unsigned int implied_prefix;
2808 unsigned int vector_length;
2809
2810 /* Check register specifier. */
2811 if (i.vex.register_specifier)
2812 {
2813 register_specifier = i.vex.register_specifier->reg_num;
2814 if ((i.vex.register_specifier->reg_flags & RegRex))
2815 register_specifier += 8;
2816 register_specifier = ~register_specifier & 0xf;
2817 }
2818 else
2819 register_specifier = 0xf;
2820
fa99fab2
L		 2821 /* Use 2-byte VEX prefix by swappping destination and source
2822 operand. */
2823 if (!i.swap_operand
2824 && i.operands == i.reg_operands
7f399153 2825 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2826 && i.tm.opcode_modifier.s
2827 && i.rex == REX_B)
2828 {
2829 unsigned int xchg = i.operands - 1;
2830 union i386_op temp_op;
2831 i386_operand_type temp_type;
2832
2833 temp_type = i.types[xchg];
2834 i.types[xchg] = i.types[0];
2835 i.types[0] = temp_type;
2836 temp_op = i.op[xchg];
2837 i.op[xchg] = i.op[0];
2838 i.op[0] = temp_op;
2839
9c2799c2 2840 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2841
2842 i.rex = REX_R;
2843 xchg = i.rm.regmem;
2844 i.rm.regmem = i.rm.reg;
2845 i.rm.reg = xchg;
2846
2847 /* Use the next insn. */
2848 i.tm = t[1];
2849 }
2850
539f890d
L		 2851 if (i.tm.opcode_modifier.vex == VEXScalar)
2852 vector_length = avxscalar;
2853 else
2854 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2855
2856 switch ((i.tm.base_opcode >> 8) & 0xff)
2857 {
2858 case 0:
2859 implied_prefix = 0;
2860 break;
2861 case DATA_PREFIX_OPCODE:
2862 implied_prefix = 1;
2863 break;
2864 case REPE_PREFIX_OPCODE:
2865 implied_prefix = 2;
2866 break;
2867 case REPNE_PREFIX_OPCODE:
2868 implied_prefix = 3;
2869 break;
2870 default:
2871 abort ();
2872 }
2873
2874 /* Use 2-byte VEX prefix if possible. */
7f399153 2875 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2876 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2877 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2878 {
2879 /* 2-byte VEX prefix. */
2880 unsigned int r;
2881
2882 i.vex.length = 2;
2883 i.vex.bytes[0] = 0xc5;
2884
2885 /* Check the REX.R bit. */
2886 r = (i.rex & REX_R) ? 0 : 1;
2887 i.vex.bytes[1] = (r << 7
2888 | register_specifier << 3
2889 | vector_length << 2
2890 | implied_prefix);
2891 }
2892 else
2893 {
2894 /* 3-byte VEX prefix. */
2895 unsigned int m, w;
2896
f88c9eb0 2897 i.vex.length = 3;
f88c9eb0 2898
7f399153 2899 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2900 {
7f399153
L		 2901 case VEX0F:
2902 m = 0x1;
80de6e00 2903 i.vex.bytes[0] = 0xc4;
7f399153
L		 2904 break;
2905 case VEX0F38:
2906 m = 0x2;
80de6e00 2907 i.vex.bytes[0] = 0xc4;
7f399153
L		 2908 break;
2909 case VEX0F3A:
2910 m = 0x3;
80de6e00 2911 i.vex.bytes[0] = 0xc4;
7f399153
L		 2912 break;
2913 case XOP08:
5dd85c99
SP		 2914 m = 0x8;
2915 i.vex.bytes[0] = 0x8f;
7f399153
L		 2916 break;
2917 case XOP09:
f88c9eb0
SP		 2918 m = 0x9;
2919 i.vex.bytes[0] = 0x8f;
7f399153
L		 2920 break;
2921 case XOP0A:
f88c9eb0
SP		 2922 m = 0xa;
2923 i.vex.bytes[0] = 0x8f;
7f399153
L		 2924 break;
2925 default:
2926 abort ();
f88c9eb0 2927 }
c0f3af97 2928
c0f3af97
L		 2929 /* The high 3 bits of the second VEX byte are 1's compliment
2930 of RXB bits from REX. */
2931 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2932
2933 /* Check the REX.W bit. */
2934 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2935 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2936 {
2937 if (w)
2938 abort ();
2939
1ef99a7b 2940 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2941 w = 1;
2942 }
2943
2944 i.vex.bytes[2] = (w << 7
2945 | register_specifier << 3
2946 | vector_length << 2
2947 | implied_prefix);
2948 }
2949}
2950
65da13b5
L		 2951static void
2952process_immext (void)
2953{
2954 expressionS *exp;
2955
2956 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2957 {
1fed0ba1
L		 2958 /* SSE3 Instructions have the fixed operands with an opcode
2959 suffix which is coded in the same place as an 8-bit immediate
2960 field would be. Here we check those operands and remove them
2961 afterwards. */
65da13b5
L		 2962 unsigned int x;
2963
2964 for (x = 0; x < i.operands; x++)
2965 if (i.op[x].regs->reg_num != x)
2966 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2967 register_prefix, i.op[x].regs->reg_name, x + 1,
2968 i.tm.name);
2969
2970 i.operands = 0;
65da13b5
L		 2971 }
2972
c0f3af97 2973 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2974 which is coded in the same place as an 8-bit immediate field
2975 would be. Here we fake an 8-bit immediate operand from the
2976 opcode suffix stored in tm.extension_opcode.
2977
c1e679ec 2978 AVX instructions also use this encoding, for some of
c0f3af97 2979 3 argument instructions. */
65da13b5 2980
9c2799c2 2981 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2982 && (i.operands <= 2
2983 || (i.tm.opcode_modifier.vex
2984 && i.operands <= 4)));
65da13b5
L		 2985
2986 exp = &im_expressions[i.imm_operands++];
2987 i.op[i.operands].imms = exp;
2988 i.types[i.operands] = imm8;
2989 i.operands++;
2990 exp->X_op = O_constant;
2991 exp->X_add_number = i.tm.extension_opcode;
2992 i.tm.extension_opcode = None;
2993}
2994
252b5132
RH		 2995/* This is the guts of the machine-dependent assembler. LINE points to a
2996 machine dependent instruction. This function is supposed to emit
2997 the frags/bytes it assembles to. */
2998
2999void
65da13b5 3000md_assemble (char *line)
252b5132 3001{
40fb9820 3002 unsigned int j;
252b5132 3003 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3004 const insn_template *t;
252b5132 3005
47926f60 3006 /* Initialize globals. */
252b5132
RH		 3007 memset (&i, '\0', sizeof (i));
3008 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3009 i.reloc[j] = NO_RELOC;
252b5132
RH		 3010 memset (disp_expressions, '\0', sizeof (disp_expressions));
3011 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3012 save_stack_p = save_stack;
252b5132
RH		 3013
3014 /* First parse an instruction mnemonic & call i386_operand for the operands.
3015 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3016 start of a (possibly prefixed) mnemonic. */
252b5132 3017
29b0f896
AM		 3018 line = parse_insn (line, mnemonic);
3019 if (line == NULL)
3020 return;
252b5132 3021
29b0f896 3022 line = parse_operands (line, mnemonic);
ee86248c 3023 this_operand = -1;
29b0f896
AM		 3024 if (line == NULL)
3025 return;
252b5132 3026
29b0f896
AM		 3027 /* Now we've parsed the mnemonic into a set of templates, and have the
3028 operands at hand. */
3029
3030 /* All intel opcodes have reversed operands except for "bound" and
3031 "enter". We also don't reverse intersegment "jmp" and "call"
3032 instructions with 2 immediate operands so that the immediate segment
050dfa73 3033 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3034 if (intel_syntax
3035 && i.operands > 1
29b0f896 3036 && (strcmp (mnemonic, "bound") != 0)
30123838 3037 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3038 && !(operand_type_check (i.types[0], imm)
3039 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3040 swap_operands ();
3041
ec56d5c0
JB		 3042 /* The order of the immediates should be reversed
3043 for 2 immediates extrq and insertq instructions */
3044 if (i.imm_operands == 2
3045 && (strcmp (mnemonic, "extrq") == 0
3046 || strcmp (mnemonic, "insertq") == 0))
3047 swap_2_operands (0, 1);
3048
29b0f896
AM		 3049 if (i.imm_operands)
3050 optimize_imm ();
3051
b300c311
L		 3052 /* Don't optimize displacement for movabs since it only takes 64bit
3053 displacement. */
3054 if (i.disp_operands
862be3fb
L		 3055 && !i.disp32_encoding
3056 && (flag_code != CODE_64BIT
3057 || strcmp (mnemonic, "movabs") != 0))
3058 optimize_disp ();
29b0f896
AM		 3059
3060 /* Next, we find a template that matches the given insn,
3061 making sure the overlap of the given operands types is consistent
3062 with the template operand types. */
252b5132 3063
fa99fab2 3064 if (!(t = match_template ()))
29b0f896 3065 return;
252b5132 3066
daf50ae7 3067 if (sse_check != sse_check_none
81f8a913 3068 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3069 && (i.tm.cpu_flags.bitfield.cpusse
3070 || i.tm.cpu_flags.bitfield.cpusse2
3071 || i.tm.cpu_flags.bitfield.cpusse3
3072 || i.tm.cpu_flags.bitfield.cpussse3
3073 || i.tm.cpu_flags.bitfield.cpusse4_1
3074 || i.tm.cpu_flags.bitfield.cpusse4_2))
3075 {
3076 (sse_check == sse_check_warning
3077 ? as_warn
3078 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3079 }
3080
321fd21e
L		 3081 /* Zap movzx and movsx suffix. The suffix has been set from
3082 "word ptr" or "byte ptr" on the source operand in Intel syntax
3083 or extracted from mnemonic in AT&T syntax. But we'll use
3084 the destination register to choose the suffix for encoding. */
3085 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3086 {
321fd21e
L		 3087 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3088 there is no suffix, the default will be byte extension. */
3089 if (i.reg_operands != 2
3090 && !i.suffix
7ab9ffdd 3091 && intel_syntax)
321fd21e
L		 3092 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3093
3094 i.suffix = 0;
cd61ebfe 3095 }
24eab124 3096
40fb9820 3097 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3098 if (!add_prefix (FWAIT_OPCODE))
3099 return;
252b5132 3100
c1ba0266
L		 3101 /* Check for lock without a lockable instruction. Destination operand
3102 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3103 if (i.prefix[LOCK_PREFIX]
3104 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3105 || i.mem_operands == 0
3106 || (i.tm.base_opcode != 0x86
3107 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3108 {
3109 as_bad (_("expecting lockable instruction after `lock'"));
3110 return;
3111 }
3112
29b0f896 3113 /* Check string instruction segment overrides. */
40fb9820 3114 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3115 {
3116 if (!check_string ())
5dd0794d 3117 return;
fc0763e6 3118 i.disp_operands = 0;
29b0f896 3119 }
5dd0794d 3120
29b0f896
AM		 3121 if (!process_suffix ())
3122 return;
e413e4e9 3123
bc0844ae
L		 3124 /* Update operand types. */
3125 for (j = 0; j < i.operands; j++)
3126 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3127
29b0f896
AM		 3128 /* Make still unresolved immediate matches conform to size of immediate
3129 given in i.suffix. */
3130 if (!finalize_imm ())
3131 return;
252b5132 3132
40fb9820 3133 if (i.types[0].bitfield.imm1)
29b0f896 3134 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3135
9afe6eb8
L		 3136 /* We only need to check those implicit registers for instructions
3137 with 3 operands or less. */
3138 if (i.operands <= 3)
3139 for (j = 0; j < i.operands; j++)
3140 if (i.types[j].bitfield.inoutportreg
3141 || i.types[j].bitfield.shiftcount
3142 || i.types[j].bitfield.acc
3143 || i.types[j].bitfield.floatacc)
3144 i.reg_operands--;
40fb9820 3145
c0f3af97
L		 3146 /* ImmExt should be processed after SSE2AVX. */
3147 if (!i.tm.opcode_modifier.sse2avx
3148 && i.tm.opcode_modifier.immext)
65da13b5 3149 process_immext ();
252b5132 3150
29b0f896
AM		 3151 /* For insns with operands there are more diddles to do to the opcode. */
3152 if (i.operands)
3153 {
3154 if (!process_operands ())
3155 return;
3156 }
40fb9820 3157 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3158 {
3159 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3160 as_warn (_("translating to `%sp'"), i.tm.name);
3161 }
252b5132 3162
c0f3af97 3163 if (i.tm.opcode_modifier.vex)
fa99fab2 3164 build_vex_prefix (t);
c0f3af97 3165
5dd85c99
SP		 3166 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3167 instructions may define INT_OPCODE as well, so avoid this corner
3168 case for those instructions that use MODRM. */
3169 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3170 && !i.tm.opcode_modifier.modrm
3171 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3172 {
3173 i.tm.base_opcode = INT3_OPCODE;
3174 i.imm_operands = 0;
3175 }
252b5132 3176
40fb9820
L		 3177 if ((i.tm.opcode_modifier.jump
3178 || i.tm.opcode_modifier.jumpbyte
3179 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3180 && i.op[0].disps->X_op == O_constant)
3181 {
3182 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3183 the absolute address given by the constant. Since ix86 jumps and
3184 calls are pc relative, we need to generate a reloc. */
3185 i.op[0].disps->X_add_symbol = &abs_symbol;
3186 i.op[0].disps->X_op = O_symbol;
3187 }
252b5132 3188
40fb9820 3189 if (i.tm.opcode_modifier.rex64)
161a04f6 3190 i.rex |= REX_W;
252b5132 3191
29b0f896
AM		 3192 /* For 8 bit registers we need an empty rex prefix. Also if the
3193 instruction already has a prefix, we need to convert old
3194 registers to new ones. */
773f551c 3195
40fb9820 3196 if ((i.types[0].bitfield.reg8
29b0f896 3197 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3198 || (i.types[1].bitfield.reg8
29b0f896 3199 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3200 || ((i.types[0].bitfield.reg8
3201 || i.types[1].bitfield.reg8)
29b0f896
AM		 3202 && i.rex != 0))
3203 {
3204 int x;
726c5dcd 3205
29b0f896
AM		 3206 i.rex |= REX_OPCODE;
3207 for (x = 0; x < 2; x++)
3208 {
3209 /* Look for 8 bit operand that uses old registers. */
40fb9820 3210 if (i.types[x].bitfield.reg8
29b0f896 3211 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3212 {
29b0f896
AM		 3213 /* In case it is "hi" register, give up. */
3214 if (i.op[x].regs->reg_num > 3)
a540244d 3215 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3216 "instruction requiring REX prefix."),
a540244d 3217 register_prefix, i.op[x].regs->reg_name);
773f551c 3218
29b0f896
AM		 3219 /* Otherwise it is equivalent to the extended register.
3220 Since the encoding doesn't change this is merely
3221 cosmetic cleanup for debug output. */
3222
3223 i.op[x].regs = i.op[x].regs + 8;
773f551c 3224 }
29b0f896
AM		 3225 }
3226 }
773f551c 3227
7ab9ffdd 3228 if (i.rex != 0)
29b0f896
AM		 3229 add_prefix (REX_OPCODE | i.rex);
3230
3231 /* We are ready to output the insn. */
3232 output_insn ();
3233}
3234
3235static char *
e3bb37b5 3236parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3237{
3238 char *l = line;
3239 char *token_start = l;
3240 char *mnem_p;
5c6af06e 3241 int supported;
d3ce72d0 3242 const insn_template *t;
b6169b20 3243 char *dot_p = NULL;
29b0f896
AM		 3244
3245 /* Non-zero if we found a prefix only acceptable with string insns. */
3246 const char *expecting_string_instruction = NULL;
45288df1 3247
29b0f896
AM		 3248 while (1)
3249 {
3250 mnem_p = mnemonic;
3251 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3252 {
b6169b20
L		 3253 if (*mnem_p == '.')
3254 dot_p = mnem_p;
29b0f896
AM		 3255 mnem_p++;
3256 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3257 {
29b0f896
AM		 3258 as_bad (_("no such instruction: `%s'"), token_start);
3259 return NULL;
3260 }
3261 l++;
3262 }
3263 if (!is_space_char (*l)
3264 && *l != END_OF_INSN
e44823cf
JB		 3265 && (intel_syntax
3266 || (*l != PREFIX_SEPARATOR
3267 && *l != ',')))
29b0f896
AM		 3268 {
3269 as_bad (_("invalid character %s in mnemonic"),
3270 output_invalid (*l));
3271 return NULL;
3272 }
3273 if (token_start == l)
3274 {
e44823cf 3275 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3276 as_bad (_("expecting prefix; got nothing"));
3277 else
3278 as_bad (_("expecting mnemonic; got nothing"));
3279 return NULL;
3280 }
45288df1 3281
29b0f896 3282 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3283 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3284
29b0f896
AM		 3285 if (*l != END_OF_INSN
3286 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3287 && current_templates
40fb9820 3288 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3289 {
c6fb90c8 3290 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3291 {
3292 as_bad ((flag_code != CODE_64BIT
3293 ? _("`%s' is only supported in 64-bit mode")
3294 : _("`%s' is not supported in 64-bit mode")),
3295 current_templates->start->name);
3296 return NULL;
3297 }
29b0f896
AM		 3298 /* If we are in 16-bit mode, do not allow addr16 or data16.
3299 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3300 if ((current_templates->start->opcode_modifier.size16
3301 || current_templates->start->opcode_modifier.size32)
29b0f896 3302 && flag_code != CODE_64BIT
40fb9820 3303 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3304 ^ (flag_code == CODE_16BIT)))
3305 {
3306 as_bad (_("redundant %s prefix"),
3307 current_templates->start->name);
3308 return NULL;
45288df1 3309 }
29b0f896
AM		 3310 /* Add prefix, checking for repeated prefixes. */
3311 switch (add_prefix (current_templates->start->base_opcode))
3312 {
c32fa91d 3313 case PREFIX_EXIST:
29b0f896 3314 return NULL;
c32fa91d 3315 case PREFIX_REP:
29b0f896
AM		 3316 expecting_string_instruction = current_templates->start->name;
3317 break;
c32fa91d
L		 3318 default:
3319 break;
29b0f896
AM		 3320 }
3321 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3322 token_start = ++l;
3323 }
3324 else
3325 break;
3326 }
45288df1 3327
30a55f88 3328 if (!current_templates)
b6169b20 3329 {
f8a5c266
L		 3330 /* Check if we should swap operand or force 32bit displacement in
3331 encoding. */
30a55f88
L		 3332 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3333 i.swap_operand = 1;
f8a5c266
L		 3334 else if (mnem_p - 4 == dot_p
3335 && dot_p[1] == 'd'
3336 && dot_p[2] == '3'
3337 && dot_p[3] == '2')
3338 i.disp32_encoding = 1;
30a55f88
L		 3339 else
3340 goto check_suffix;
3341 mnem_p = dot_p;
3342 *dot_p = '\0';
d3ce72d0 3343 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3344 }
3345
29b0f896
AM		 3346 if (!current_templates)
3347 {
b6169b20 3348check_suffix:
29b0f896
AM		 3349 /* See if we can get a match by trimming off a suffix. */
3350 switch (mnem_p[-1])
3351 {
3352 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3353 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3354 i.suffix = SHORT_MNEM_SUFFIX;
3355 else
29b0f896
AM		 3356 case BYTE_MNEM_SUFFIX:
3357 case QWORD_MNEM_SUFFIX:
3358 i.suffix = mnem_p[-1];
3359 mnem_p[-1] = '\0';
d3ce72d0
NC		 3360 current_templates = (const templates *) hash_find (op_hash,
3361 mnemonic);
29b0f896
AM		 3362 break;
3363 case SHORT_MNEM_SUFFIX:
3364 case LONG_MNEM_SUFFIX:
3365 if (!intel_syntax)
3366 {
3367 i.suffix = mnem_p[-1];
3368 mnem_p[-1] = '\0';
d3ce72d0
NC		 3369 current_templates = (const templates *) hash_find (op_hash,
3370 mnemonic);
29b0f896
AM		 3371 }
3372 break;
252b5132 3373
29b0f896
AM		 3374 /* Intel Syntax. */
3375 case 'd':
3376 if (intel_syntax)
3377 {
9306ca4a 3378 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3379 i.suffix = SHORT_MNEM_SUFFIX;
3380 else
3381 i.suffix = LONG_MNEM_SUFFIX;
3382 mnem_p[-1] = '\0';
d3ce72d0
NC		 3383 current_templates = (const templates *) hash_find (op_hash,
3384 mnemonic);
29b0f896
AM		 3385 }
3386 break;
3387 }
3388 if (!current_templates)
3389 {
3390 as_bad (_("no such instruction: `%s'"), token_start);
3391 return NULL;
3392 }
3393 }
252b5132 3394
40fb9820
L		 3395 if (current_templates->start->opcode_modifier.jump
3396 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3397 {
3398 /* Check for a branch hint. We allow ",pt" and ",pn" for
3399 predict taken and predict not taken respectively.
3400 I'm not sure that branch hints actually do anything on loop
3401 and jcxz insns (JumpByte) for current Pentium4 chips. They
3402 may work in the future and it doesn't hurt to accept them
3403 now. */
3404 if (l[0] == ',' && l[1] == 'p')
3405 {
3406 if (l[2] == 't')
3407 {
3408 if (!add_prefix (DS_PREFIX_OPCODE))
3409 return NULL;
3410 l += 3;
3411 }
3412 else if (l[2] == 'n')
3413 {
3414 if (!add_prefix (CS_PREFIX_OPCODE))
3415 return NULL;
3416 l += 3;
3417 }
3418 }
3419 }
3420 /* Any other comma loses. */
3421 if (*l == ',')
3422 {
3423 as_bad (_("invalid character %s in mnemonic"),
3424 output_invalid (*l));
3425 return NULL;
3426 }
252b5132 3427
29b0f896 3428 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3429 supported = 0;
3430 for (t = current_templates->start; t < current_templates->end; ++t)
3431 {
c0f3af97
L		 3432 supported |= cpu_flags_match (t);
3433 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3434 goto skip;
5c6af06e 3435 }
3629bb00 3436
c0f3af97 3437 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3438 {
3439 as_bad (flag_code == CODE_64BIT
3440 ? _("`%s' is not supported in 64-bit mode")
3441 : _("`%s' is only supported in 64-bit mode"),
3442 current_templates->start->name);
3443 return NULL;
3444 }
c0f3af97 3445 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3446 {
3629bb00 3447 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3448 current_templates->start->name,
41aacd83 3449 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3450 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3451 return NULL;
29b0f896 3452 }
3629bb00
L		 3453
3454skip:
3455 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3456 && (flag_code != CODE_16BIT))
29b0f896
AM		 3457 {
3458 as_warn (_("use .code16 to ensure correct addressing mode"));
3459 }
252b5132 3460
29b0f896 3461 /* Check for rep/repne without a string instruction. */
f41bbced 3462 if (expecting_string_instruction)
29b0f896 3463 {
f41bbced
JB		 3464 static templates override;
3465
3466 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3467 if (t->opcode_modifier.isstring)
f41bbced
JB		 3468 break;
3469 if (t >= current_templates->end)
3470 {
3471 as_bad (_("expecting string instruction after `%s'"),
64e74474 3472 expecting_string_instruction);
f41bbced
JB		 3473 return NULL;
3474 }
3475 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3476 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3477 break;
3478 override.end = t;
3479 current_templates = &override;
29b0f896 3480 }
252b5132 3481
29b0f896
AM		 3482 return l;
3483}
252b5132 3484
29b0f896 3485static char *
e3bb37b5 3486parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3487{
3488 char *token_start;
3138f287 3489
29b0f896
AM		 3490 /* 1 if operand is pending after ','. */
3491 unsigned int expecting_operand = 0;
252b5132 3492
29b0f896
AM		 3493 /* Non-zero if operand parens not balanced. */
3494 unsigned int paren_not_balanced;
3495
3496 while (*l != END_OF_INSN)
3497 {
3498 /* Skip optional white space before operand. */
3499 if (is_space_char (*l))
3500 ++l;
3501 if (!is_operand_char (*l) && *l != END_OF_INSN)
3502 {
3503 as_bad (_("invalid character %s before operand %d"),
3504 output_invalid (*l),
3505 i.operands + 1);
3506 return NULL;
3507 }
3508 token_start = l; /* after white space */
3509 paren_not_balanced = 0;
3510 while (paren_not_balanced || *l != ',')
3511 {
3512 if (*l == END_OF_INSN)
3513 {
3514 if (paren_not_balanced)
3515 {
3516 if (!intel_syntax)
3517 as_bad (_("unbalanced parenthesis in operand %d."),
3518 i.operands + 1);
3519 else
3520 as_bad (_("unbalanced brackets in operand %d."),
3521 i.operands + 1);
3522 return NULL;
3523 }
3524 else
3525 break; /* we are done */
3526 }
3527 else if (!is_operand_char (*l) && !is_space_char (*l))
3528 {
3529 as_bad (_("invalid character %s in operand %d"),
3530 output_invalid (*l),
3531 i.operands + 1);
3532 return NULL;
3533 }
3534 if (!intel_syntax)
3535 {
3536 if (*l == '(')
3537 ++paren_not_balanced;
3538 if (*l == ')')
3539 --paren_not_balanced;
3540 }
3541 else
3542 {
3543 if (*l == '[')
3544 ++paren_not_balanced;
3545 if (*l == ']')
3546 --paren_not_balanced;
3547 }
3548 l++;
3549 }
3550 if (l != token_start)
3551 { /* Yes, we've read in another operand. */
3552 unsigned int operand_ok;
3553 this_operand = i.operands++;
7d5e4556 3554 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3555 if (i.operands > MAX_OPERANDS)
3556 {
3557 as_bad (_("spurious operands; (%d operands/instruction max)"),
3558 MAX_OPERANDS);
3559 return NULL;
3560 }
3561 /* Now parse operand adding info to 'i' as we go along. */
3562 END_STRING_AND_SAVE (l);
3563
3564 if (intel_syntax)
3565 operand_ok =
3566 i386_intel_operand (token_start,
3567 intel_float_operand (mnemonic));
3568 else
a7619375 3569 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3570
3571 RESTORE_END_STRING (l);
3572 if (!operand_ok)
3573 return NULL;
3574 }
3575 else
3576 {
3577 if (expecting_operand)
3578 {
3579 expecting_operand_after_comma:
3580 as_bad (_("expecting operand after ','; got nothing"));
3581 return NULL;
3582 }
3583 if (*l == ',')
3584 {
3585 as_bad (_("expecting operand before ','; got nothing"));
3586 return NULL;
3587 }
3588 }
7f3f1ea2 3589
29b0f896
AM		 3590 /* Now *l must be either ',' or END_OF_INSN. */
3591 if (*l == ',')
3592 {
3593 if (*++l == END_OF_INSN)
3594 {
3595 /* Just skip it, if it's \n complain. */
3596 goto expecting_operand_after_comma;
3597 }
3598 expecting_operand = 1;
3599 }
3600 }
3601 return l;
3602}
7f3f1ea2 3603
050dfa73 3604static void
4d456e3d 3605swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3606{
3607 union i386_op temp_op;
40fb9820 3608 i386_operand_type temp_type;
050dfa73 3609 enum bfd_reloc_code_real temp_reloc;
4eed87de 3610
050dfa73
MM		 3611 temp_type = i.types[xchg2];
3612 i.types[xchg2] = i.types[xchg1];
3613 i.types[xchg1] = temp_type;
3614 temp_op = i.op[xchg2];
3615 i.op[xchg2] = i.op[xchg1];
3616 i.op[xchg1] = temp_op;
3617 temp_reloc = i.reloc[xchg2];
3618 i.reloc[xchg2] = i.reloc[xchg1];
3619 i.reloc[xchg1] = temp_reloc;
3620}
3621
29b0f896 3622static void
e3bb37b5 3623swap_operands (void)
29b0f896 3624{
b7c61d9a 3625 switch (i.operands)
050dfa73 3626 {
c0f3af97 3627 case 5:
b7c61d9a 3628 case 4:
4d456e3d 3629 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3630 case 3:
3631 case 2:
4d456e3d 3632 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3633 break;
3634 default:
3635 abort ();
29b0f896 3636 }
29b0f896
AM		 3637
3638 if (i.mem_operands == 2)
3639 {
3640 const seg_entry *temp_seg;
3641 temp_seg = i.seg[0];
3642 i.seg[0] = i.seg[1];
3643 i.seg[1] = temp_seg;
3644 }
3645}
252b5132 3646
29b0f896
AM		 3647/* Try to ensure constant immediates are represented in the smallest
3648 opcode possible. */
3649static void
e3bb37b5 3650optimize_imm (void)
29b0f896
AM		 3651{
3652 char guess_suffix = 0;
3653 int op;
252b5132 3654
29b0f896
AM		 3655 if (i.suffix)
3656 guess_suffix = i.suffix;
3657 else if (i.reg_operands)
3658 {
3659 /* Figure out a suffix from the last register operand specified.
3660 We can't do this properly yet, ie. excluding InOutPortReg,
3661 but the following works for instructions with immediates.
3662 In any case, we can't set i.suffix yet. */
3663 for (op = i.operands; --op >= 0;)
40fb9820 3664 if (i.types[op].bitfield.reg8)
7ab9ffdd 3665 {
40fb9820
L		 3666 guess_suffix = BYTE_MNEM_SUFFIX;
3667 break;
3668 }
3669 else if (i.types[op].bitfield.reg16)
252b5132 3670 {
40fb9820
L		 3671 guess_suffix = WORD_MNEM_SUFFIX;
3672 break;
3673 }
3674 else if (i.types[op].bitfield.reg32)
3675 {
3676 guess_suffix = LONG_MNEM_SUFFIX;
3677 break;
3678 }
3679 else if (i.types[op].bitfield.reg64)
3680 {
3681 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3682 break;
252b5132 3683 }
29b0f896
AM		 3684 }
3685 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3686 guess_suffix = WORD_MNEM_SUFFIX;
3687
3688 for (op = i.operands; --op >= 0;)
40fb9820 3689 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3690 {
3691 switch (i.op[op].imms->X_op)
252b5132 3692 {
29b0f896
AM		 3693 case O_constant:
3694 /* If a suffix is given, this operand may be shortened. */
3695 switch (guess_suffix)
252b5132 3696 {
29b0f896 3697 case LONG_MNEM_SUFFIX:
40fb9820
L		 3698 i.types[op].bitfield.imm32 = 1;
3699 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3700 break;
3701 case WORD_MNEM_SUFFIX:
40fb9820
L		 3702 i.types[op].bitfield.imm16 = 1;
3703 i.types[op].bitfield.imm32 = 1;
3704 i.types[op].bitfield.imm32s = 1;
3705 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3706 break;
3707 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3708 i.types[op].bitfield.imm8 = 1;
3709 i.types[op].bitfield.imm8s = 1;
3710 i.types[op].bitfield.imm16 = 1;
3711 i.types[op].bitfield.imm32 = 1;
3712 i.types[op].bitfield.imm32s = 1;
3713 i.types[op].bitfield.imm64 = 1;
29b0f896 3714 break;
252b5132 3715 }
252b5132 3716
29b0f896
AM		 3717 /* If this operand is at most 16 bits, convert it
3718 to a signed 16 bit number before trying to see
3719 whether it will fit in an even smaller size.
3720 This allows a 16-bit operand such as $0xffe0 to
3721 be recognised as within Imm8S range. */
40fb9820 3722 if ((i.types[op].bitfield.imm16)
29b0f896 3723 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3724 {
29b0f896
AM		 3725 i.op[op].imms->X_add_number =
3726 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3727 }
40fb9820 3728 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3729 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3730 == 0))
3731 {
3732 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3733 ^ ((offsetT) 1 << 31))
3734 - ((offsetT) 1 << 31));
3735 }
40fb9820 3736 i.types[op]
c6fb90c8
L		 3737 = operand_type_or (i.types[op],
3738 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3739
29b0f896
AM		 3740 /* We must avoid matching of Imm32 templates when 64bit
3741 only immediate is available. */
3742 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3743 i.types[op].bitfield.imm32 = 0;
29b0f896 3744 break;
252b5132 3745
29b0f896
AM		 3746 case O_absent:
3747 case O_register:
3748 abort ();
3749
3750 /* Symbols and expressions. */
3751 default:
9cd96992
JB		 3752 /* Convert symbolic operand to proper sizes for matching, but don't
3753 prevent matching a set of insns that only supports sizes other
3754 than those matching the insn suffix. */
3755 {
40fb9820 3756 i386_operand_type mask, allowed;
d3ce72d0 3757 const insn_template *t;
9cd96992 3758
0dfbf9d7
L		 3759 operand_type_set (&mask, 0);
3760 operand_type_set (&allowed, 0);
40fb9820 3761
4eed87de
AM		 3762 for (t = current_templates->start;
3763 t < current_templates->end;
3764 ++t)
c6fb90c8
L		 3765 allowed = operand_type_or (allowed,
3766 t->operand_types[op]);
9cd96992
JB		 3767 switch (guess_suffix)
3768 {
3769 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3770 mask.bitfield.imm64 = 1;
3771 mask.bitfield.imm32s = 1;
9cd96992
JB		 3772 break;
3773 case LONG_MNEM_SUFFIX:
40fb9820 3774 mask.bitfield.imm32 = 1;
9cd96992
JB		 3775 break;
3776 case WORD_MNEM_SUFFIX:
40fb9820 3777 mask.bitfield.imm16 = 1;
9cd96992
JB		 3778 break;
3779 case BYTE_MNEM_SUFFIX:
40fb9820 3780 mask.bitfield.imm8 = 1;
9cd96992
JB		 3781 break;
3782 default:
9cd96992
JB		 3783 break;
3784 }
c6fb90c8 3785 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3786 if (!operand_type_all_zero (&allowed))
c6fb90c8 3787 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3788 }
29b0f896 3789 break;
252b5132 3790 }
29b0f896
AM		 3791 }
3792}
47926f60 3793
29b0f896
AM		 3794/* Try to use the smallest displacement type too. */
3795static void
e3bb37b5 3796optimize_disp (void)
29b0f896
AM		 3797{
3798 int op;
3e73aa7c 3799
29b0f896 3800 for (op = i.operands; --op >= 0;)
40fb9820 3801 if (operand_type_check (i.types[op], disp))
252b5132 3802 {
b300c311 3803 if (i.op[op].disps->X_op == O_constant)
252b5132 3804 {
91d6fa6a 3805 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3806
40fb9820 3807 if (i.types[op].bitfield.disp16
91d6fa6a 3808 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3809 {
3810 /* If this operand is at most 16 bits, convert
3811 to a signed 16 bit number and don't use 64bit
3812 displacement. */
91d6fa6a 3813 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3814 i.types[op].bitfield.disp64 = 0;
b300c311 3815 }
40fb9820 3816 if (i.types[op].bitfield.disp32
91d6fa6a 3817 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3818 {
3819 /* If this operand is at most 32 bits, convert
3820 to a signed 32 bit number and don't use 64bit
3821 displacement. */
91d6fa6a
NC		 3822 op_disp &= (((offsetT) 2 << 31) - 1);
3823 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3824 i.types[op].bitfield.disp64 = 0;
b300c311 3825 }
91d6fa6a 3826 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3827 {
40fb9820
L		 3828 i.types[op].bitfield.disp8 = 0;
3829 i.types[op].bitfield.disp16 = 0;
3830 i.types[op].bitfield.disp32 = 0;
3831 i.types[op].bitfield.disp32s = 0;
3832 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3833 i.op[op].disps = 0;
3834 i.disp_operands--;
3835 }
3836 else if (flag_code == CODE_64BIT)
3837 {
91d6fa6a 3838 if (fits_in_signed_long (op_disp))
28a9d8f5 3839 {
40fb9820
L		 3840 i.types[op].bitfield.disp64 = 0;
3841 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3842 }
0e1147d9 3843 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3844 && fits_in_unsigned_long (op_disp))
40fb9820 3845 i.types[op].bitfield.disp32 = 1;
b300c311 3846 }
40fb9820
L		 3847 if ((i.types[op].bitfield.disp32
3848 || i.types[op].bitfield.disp32s
3849 || i.types[op].bitfield.disp16)
91d6fa6a 3850 && fits_in_signed_byte (op_disp))
40fb9820 3851 i.types[op].bitfield.disp8 = 1;
252b5132 3852 }
67a4f2b7
AO		 3853 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3854 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3855 {
3856 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3857 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3858 i.types[op].bitfield.disp8 = 0;
3859 i.types[op].bitfield.disp16 = 0;
3860 i.types[op].bitfield.disp32 = 0;
3861 i.types[op].bitfield.disp32s = 0;
3862 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3863 }
3864 else
b300c311 3865 /* We only support 64bit displacement on constants. */
40fb9820 3866 i.types[op].bitfield.disp64 = 0;
252b5132 3867 }
29b0f896
AM		 3868}
3869
6c30d220
L		 3870/* Check if operands are valid for the instruction. */
3871
3872static int
3873check_VecOperands (const insn_template *t)
3874{
3875 /* Without VSIB byte, we can't have a vector register for index. */
3876 if (!t->opcode_modifier.vecsib
3877 && i.index_reg
3878 && (i.index_reg->reg_type.bitfield.regxmm
3879 || i.index_reg->reg_type.bitfield.regymm))
3880 {
3881 i.error = unsupported_vector_index_register;
3882 return 1;
3883 }
3884
3885 /* For VSIB byte, we need a vector register for index and no PC
3886 relative addressing is allowed. */
3887 if (t->opcode_modifier.vecsib
3888 && (!i.index_reg
3889 || !((t->opcode_modifier.vecsib == VecSIB128
3890 && i.index_reg->reg_type.bitfield.regxmm)
3891 || (t->opcode_modifier.vecsib == VecSIB256
3892 && i.index_reg->reg_type.bitfield.regymm))
3893 || (i.base_reg && i.base_reg->reg_num == RegRip)))
3894 {
3895 i.error = invalid_vsib_address;
3896 return 1;
3897 }
3898
3899 return 0;
3900}
3901
43f3e2ee 3902/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3903 operand types. */
3904
3905static int
3906VEX_check_operands (const insn_template *t)
3907{
3908 if (!t->opcode_modifier.vex)
3909 return 0;
3910
3911 /* Only check VEX_Imm4, which must be the first operand. */
3912 if (t->operand_types[0].bitfield.vec_imm4)
3913 {
3914 if (i.op[0].imms->X_op != O_constant
3915 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3916 {
a65babc9 3917 i.error = bad_imm4;
891edac4
L		 3918 return 1;
3919 }
a683cc34
SP		 3920
3921 /* Turn off Imm8 so that update_imm won't complain. */
3922 i.types[0] = vec_imm4;
3923 }
3924
3925 return 0;
3926}
3927
d3ce72d0 3928static const insn_template *
e3bb37b5 3929match_template (void)
29b0f896
AM		 3930{
3931 /* Points to template once we've found it. */
d3ce72d0 3932 const insn_template *t;
40fb9820 3933 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3934 i386_operand_type overlap4;
29b0f896 3935 unsigned int found_reverse_match;
40fb9820
L		 3936 i386_opcode_modifier suffix_check;
3937 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3938 int addr_prefix_disp;
a5c311ca 3939 unsigned int j;
3629bb00 3940 unsigned int found_cpu_match;
45664ddb 3941 unsigned int check_register;
29b0f896 3942
c0f3af97
L		 3943#if MAX_OPERANDS != 5
3944# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3945#endif
3946
29b0f896 3947 found_reverse_match = 0;
539e75ad 3948 addr_prefix_disp = -1;
40fb9820
L		 3949
3950 memset (&suffix_check, 0, sizeof (suffix_check));
3951 if (i.suffix == BYTE_MNEM_SUFFIX)
3952 suffix_check.no_bsuf = 1;
3953 else if (i.suffix == WORD_MNEM_SUFFIX)
3954 suffix_check.no_wsuf = 1;
3955 else if (i.suffix == SHORT_MNEM_SUFFIX)
3956 suffix_check.no_ssuf = 1;
3957 else if (i.suffix == LONG_MNEM_SUFFIX)
3958 suffix_check.no_lsuf = 1;
3959 else if (i.suffix == QWORD_MNEM_SUFFIX)
3960 suffix_check.no_qsuf = 1;
3961 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3962 suffix_check.no_ldsuf = 1;
29b0f896 3963
01559ecc
L		 3964 /* Must have right number of operands. */
3965 i.error = number_of_operands_mismatch;
3966
45aa61fe 3967 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3968 {
539e75ad
L		 3969 addr_prefix_disp = -1;
3970
29b0f896
AM		 3971 if (i.operands != t->operands)
3972 continue;
3973
50aecf8c 3974 /* Check processor support. */
a65babc9 3975 i.error = unsupported;
c0f3af97
L		 3976 found_cpu_match = (cpu_flags_match (t)
3977 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3978 if (!found_cpu_match)
3979 continue;
3980
e1d4d893 3981 /* Check old gcc support. */
a65babc9 3982 i.error = old_gcc_only;
e1d4d893
L		 3983 if (!old_gcc && t->opcode_modifier.oldgcc)
3984 continue;
3985
3986 /* Check AT&T mnemonic. */
a65babc9 3987 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3988 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3989 continue;
3990
891edac4 3991 /* Check AT&T/Intel syntax. */
a65babc9 3992 i.error = unsupported_syntax;
5c07affc
L		 3993 if ((intel_syntax && t->opcode_modifier.attsyntax)
3994 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3995 continue;
3996
20592a94 3997 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3998 i.error = invalid_instruction_suffix;
567e4e96
L		 3999 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4000 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4001 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4002 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4003 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4004 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4005 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4006 continue;
4007
5c07affc 4008 if (!operand_size_match (t))
7d5e4556 4009 continue;
539e75ad 4010
5c07affc
L		 4011 for (j = 0; j < MAX_OPERANDS; j++)
4012 operand_types[j] = t->operand_types[j];
4013
45aa61fe
AM		 4014 /* In general, don't allow 64-bit operands in 32-bit mode. */
4015 if (i.suffix == QWORD_MNEM_SUFFIX
4016 && flag_code != CODE_64BIT
4017 && (intel_syntax
40fb9820 4018 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4019 && !intel_float_operand (t->name))
4020 : intel_float_operand (t->name) != 2)
40fb9820 4021 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 4022 && !operand_types[0].bitfield.regxmm
4023 && !operand_types[0].bitfield.regymm)
40fb9820 4024 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4025 && !!operand_types[t->operands > 1].bitfield.regxmm
4026 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4027 && (t->base_opcode != 0x0fc7
4028 || t->extension_opcode != 1 /* cmpxchg8b */))
4029 continue;
4030
192dc9c6
JB		 4031 /* In general, don't allow 32-bit operands on pre-386. */
4032 else if (i.suffix == LONG_MNEM_SUFFIX
4033 && !cpu_arch_flags.bitfield.cpui386
4034 && (intel_syntax
4035 ? (!t->opcode_modifier.ignoresize
4036 && !intel_float_operand (t->name))
4037 : intel_float_operand (t->name) != 2)
4038 && ((!operand_types[0].bitfield.regmmx
4039 && !operand_types[0].bitfield.regxmm)
4040 || (!operand_types[t->operands > 1].bitfield.regmmx
4041 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4042 continue;
4043
29b0f896 4044 /* Do not verify operands when there are none. */
50aecf8c 4045 else
29b0f896 4046 {
c6fb90c8 4047 if (!t->operands)
2dbab7d5
L		 4048 /* We've found a match; break out of loop. */
4049 break;
29b0f896 4050 }
252b5132 4051
539e75ad
L		 4052 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4053 into Disp32/Disp16/Disp32 operand. */
4054 if (i.prefix[ADDR_PREFIX] != 0)
4055 {
40fb9820 4056 /* There should be only one Disp operand. */
539e75ad
L		 4057 switch (flag_code)
4058 {
4059 case CODE_16BIT:
40fb9820
L		 4060 for (j = 0; j < MAX_OPERANDS; j++)
4061 {
4062 if (operand_types[j].bitfield.disp16)
4063 {
4064 addr_prefix_disp = j;
4065 operand_types[j].bitfield.disp32 = 1;
4066 operand_types[j].bitfield.disp16 = 0;
4067 break;
4068 }
4069 }
539e75ad
L		 4070 break;
4071 case CODE_32BIT:
40fb9820
L		 4072 for (j = 0; j < MAX_OPERANDS; j++)
4073 {
4074 if (operand_types[j].bitfield.disp32)
4075 {
4076 addr_prefix_disp = j;
4077 operand_types[j].bitfield.disp32 = 0;
4078 operand_types[j].bitfield.disp16 = 1;
4079 break;
4080 }
4081 }
539e75ad
L		 4082 break;
4083 case CODE_64BIT:
40fb9820
L		 4084 for (j = 0; j < MAX_OPERANDS; j++)
4085 {
4086 if (operand_types[j].bitfield.disp64)
4087 {
4088 addr_prefix_disp = j;
4089 operand_types[j].bitfield.disp64 = 0;
4090 operand_types[j].bitfield.disp32 = 1;
4091 break;
4092 }
4093 }
539e75ad
L		 4094 break;
4095 }
539e75ad
L		 4096 }
4097
56ffb741
L		 4098 /* We check register size if needed. */
4099 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4100 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4101 switch (t->operands)
4102 {
4103 case 1:
40fb9820 4104 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4105 continue;
4106 break;
4107 case 2:
8b38ad71
L		 4108 /* xchg %eax, %eax is a special case. It is an aliase for nop
4109 only in 32bit mode and we can use opcode 0x90. In 64bit
4110 mode, we can't use 0x90 for xchg %eax, %eax since it should
4111 zero-extend %eax to %rax. */
4112 if (flag_code == CODE_64BIT
4113 && t->base_opcode == 0x90
0dfbf9d7
L		 4114 && operand_type_equal (&i.types [0], &acc32)
4115 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4116 continue;
b6169b20
L		 4117 if (i.swap_operand)
4118 {
4119 /* If we swap operand in encoding, we either match
4120 the next one or reverse direction of operands. */
4121 if (t->opcode_modifier.s)
4122 continue;
4123 else if (t->opcode_modifier.d)
4124 goto check_reverse;
4125 }
4126
29b0f896 4127 case 3:
fa99fab2
L		 4128 /* If we swap operand in encoding, we match the next one. */
4129 if (i.swap_operand && t->opcode_modifier.s)
4130 continue;
f48ff2ae 4131 case 4:
c0f3af97 4132 case 5:
c6fb90c8 4133 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4134 if (!operand_type_match (overlap0, i.types[0])
4135 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4136 || (check_register
4137 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4138 operand_types[0],
4139 overlap1, i.types[1],
4140 operand_types[1])))
29b0f896
AM		 4141 {
4142 /* Check if other direction is valid ... */
40fb9820 4143 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4144 continue;
4145
b6169b20 4146check_reverse:
29b0f896 4147 /* Try reversing direction of operands. */
c6fb90c8
L		 4148 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4149 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4150 if (!operand_type_match (overlap0, i.types[0])
4151 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4152 || (check_register
4153 && !operand_type_register_match (overlap0,
4154 i.types[0],
4155 operand_types[1],
4156 overlap1,
4157 i.types[1],
4158 operand_types[0])))
29b0f896
AM		 4159 {
4160 /* Does not match either direction. */
4161 continue;
4162 }
4163 /* found_reverse_match holds which of D or FloatDR
4164 we've found. */
40fb9820 4165 if (t->opcode_modifier.d)
8a2ed489 4166 found_reverse_match = Opcode_D;
40fb9820 4167 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4168 found_reverse_match = Opcode_FloatD;
4169 else
4170 found_reverse_match = 0;
40fb9820 4171 if (t->opcode_modifier.floatr)
8a2ed489 4172 found_reverse_match |= Opcode_FloatR;
29b0f896 4173 }
f48ff2ae 4174 else
29b0f896 4175 {
f48ff2ae 4176 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4177 switch (t->operands)
4178 {
c0f3af97
L		 4179 case 5:
4180 overlap4 = operand_type_and (i.types[4],
4181 operand_types[4]);
d1cbb4db 4182 case 4:
c6fb90c8
L		 4183 overlap3 = operand_type_and (i.types[3],
4184 operand_types[3]);
d1cbb4db 4185 case 3:
c6fb90c8
L		 4186 overlap2 = operand_type_and (i.types[2],
4187 operand_types[2]);
d1cbb4db
L		 4188 break;
4189 }
29b0f896 4190
f48ff2ae
L		 4191 switch (t->operands)
4192 {
c0f3af97
L		 4193 case 5:
4194 if (!operand_type_match (overlap4, i.types[4])
4195 || !operand_type_register_match (overlap3,
4196 i.types[3],
4197 operand_types[3],
4198 overlap4,
4199 i.types[4],
4200 operand_types[4]))
4201 continue;
f48ff2ae 4202 case 4:
40fb9820 4203 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4204 || (check_register
4205 && !operand_type_register_match (overlap2,
4206 i.types[2],
4207 operand_types[2],
4208 overlap3,
4209 i.types[3],
4210 operand_types[3])))
f48ff2ae
L		 4211 continue;
4212 case 3:
4213 /* Here we make use of the fact that there are no
4214 reverse match 3 operand instructions, and all 3
4215 operand instructions only need to be checked for
4216 register consistency between operands 2 and 3. */
40fb9820 4217 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4218 || (check_register
4219 && !operand_type_register_match (overlap1,
4220 i.types[1],
4221 operand_types[1],
4222 overlap2,
4223 i.types[2],
4224 operand_types[2])))
f48ff2ae
L		 4225 continue;
4226 break;
4227 }
29b0f896 4228 }
f48ff2ae 4229 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4230 slip through to break. */
4231 }
3629bb00 4232 if (!found_cpu_match)
29b0f896
AM		 4233 {
4234 found_reverse_match = 0;
4235 continue;
4236 }
c0f3af97 4237
6c30d220
L		 4238 /* Check if vector operands are valid. */
4239 if (check_VecOperands (t))
4240 continue;
4241
a683cc34
SP		 4242 /* Check if VEX operands are valid. */
4243 if (VEX_check_operands (t))
4244 continue;
4245
29b0f896
AM		 4246 /* We've found a match; break out of loop. */
4247 break;
4248 }
4249
4250 if (t == current_templates->end)
4251 {
4252 /* We found no match. */
a65babc9
L		 4253 const char *err_msg;
4254 switch (i.error)
4255 {
4256 default:
4257 abort ();
86e026a4 4258 case operand_size_mismatch:
a65babc9
L		 4259 err_msg = _("operand size mismatch");
4260 break;
4261 case operand_type_mismatch:
4262 err_msg = _("operand type mismatch");
4263 break;
4264 case register_type_mismatch:
4265 err_msg = _("register type mismatch");
4266 break;
4267 case number_of_operands_mismatch:
4268 err_msg = _("number of operands mismatch");
4269 break;
4270 case invalid_instruction_suffix:
4271 err_msg = _("invalid instruction suffix");
4272 break;
4273 case bad_imm4:
4274 err_msg = _("Imm4 isn't the first operand");
4275 break;
4276 case old_gcc_only:
4277 err_msg = _("only supported with old gcc");
4278 break;
4279 case unsupported_with_intel_mnemonic:
4280 err_msg = _("unsupported with Intel mnemonic");
4281 break;
4282 case unsupported_syntax:
4283 err_msg = _("unsupported syntax");
4284 break;
4285 case unsupported:
4286 err_msg = _("unsupported");
4287 break;
6c30d220
L		 4288 case invalid_vsib_address:
4289 err_msg = _("invalid VSIB address");
4290 break;
4291 case unsupported_vector_index_register:
4292 err_msg = _("unsupported vector index register");
4293 break;
a65babc9
L		 4294 }
4295 as_bad (_("%s for `%s'"), err_msg,
891edac4 4296 current_templates->start->name);
fa99fab2 4297 return NULL;
29b0f896 4298 }
252b5132 4299
29b0f896
AM		 4300 if (!quiet_warnings)
4301 {
4302 if (!intel_syntax
40fb9820
L		 4303 && (i.types[0].bitfield.jumpabsolute
4304 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4305 {
4306 as_warn (_("indirect %s without `*'"), t->name);
4307 }
4308
40fb9820
L		 4309 if (t->opcode_modifier.isprefix
4310 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4311 {
4312 /* Warn them that a data or address size prefix doesn't
4313 affect assembly of the next line of code. */
4314 as_warn (_("stand-alone `%s' prefix"), t->name);
4315 }
4316 }
4317
4318 /* Copy the template we found. */
4319 i.tm = *t;
539e75ad
L		 4320
4321 if (addr_prefix_disp != -1)
4322 i.tm.operand_types[addr_prefix_disp]
4323 = operand_types[addr_prefix_disp];
4324
29b0f896
AM		 4325 if (found_reverse_match)
4326 {
4327 /* If we found a reverse match we must alter the opcode
4328 direction bit. found_reverse_match holds bits to change
4329 (different for int & float insns). */
4330
4331 i.tm.base_opcode ^= found_reverse_match;
4332
539e75ad
L		 4333 i.tm.operand_types[0] = operand_types[1];
4334 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4335 }
4336
fa99fab2 4337 return t;
29b0f896
AM		 4338}
4339
4340static int
e3bb37b5 4341check_string (void)
29b0f896 4342{
40fb9820
L		 4343 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4344 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4345 {
4346 if (i.seg[0] != NULL && i.seg[0] != &es)
4347 {
a87af027 4348 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4349 i.tm.name,
a87af027
JB		 4350 mem_op + 1,
4351 register_prefix);
29b0f896
AM		 4352 return 0;
4353 }
4354 /* There's only ever one segment override allowed per instruction.
4355 This instruction possibly has a legal segment override on the
4356 second operand, so copy the segment to where non-string
4357 instructions store it, allowing common code. */
4358 i.seg[0] = i.seg[1];
4359 }
40fb9820 4360 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4361 {
4362 if (i.seg[1] != NULL && i.seg[1] != &es)
4363 {
a87af027 4364 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4365 i.tm.name,
a87af027
JB		 4366 mem_op + 2,
4367 register_prefix);
29b0f896
AM		 4368 return 0;
4369 }
4370 }
4371 return 1;
4372}
4373
4374static int
543613e9 4375process_suffix (void)
29b0f896
AM		 4376{
4377 /* If matched instruction specifies an explicit instruction mnemonic
4378 suffix, use it. */
40fb9820
L		 4379 if (i.tm.opcode_modifier.size16)
4380 i.suffix = WORD_MNEM_SUFFIX;
4381 else if (i.tm.opcode_modifier.size32)
4382 i.suffix = LONG_MNEM_SUFFIX;
4383 else if (i.tm.opcode_modifier.size64)
4384 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4385 else if (i.reg_operands)
4386 {
4387 /* If there's no instruction mnemonic suffix we try to invent one
4388 based on register operands. */
4389 if (!i.suffix)
4390 {
4391 /* We take i.suffix from the last register operand specified,
4392 Destination register type is more significant than source
381d071f
L		 4393 register type. crc32 in SSE4.2 prefers source register
4394 type. */
4395 if (i.tm.base_opcode == 0xf20f38f1)
4396 {
40fb9820
L		 4397 if (i.types[0].bitfield.reg16)
4398 i.suffix = WORD_MNEM_SUFFIX;
4399 else if (i.types[0].bitfield.reg32)
4400 i.suffix = LONG_MNEM_SUFFIX;
4401 else if (i.types[0].bitfield.reg64)
4402 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4403 }
9344ff29 4404 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4405 {
40fb9820 4406 if (i.types[0].bitfield.reg8)
20592a94
L		 4407 i.suffix = BYTE_MNEM_SUFFIX;
4408 }
381d071f
L		 4409
4410 if (!i.suffix)
4411 {
4412 int op;
4413
20592a94
L		 4414 if (i.tm.base_opcode == 0xf20f38f1
4415 || i.tm.base_opcode == 0xf20f38f0)
4416 {
4417 /* We have to know the operand size for crc32. */
4418 as_bad (_("ambiguous memory operand size for `%s`"),
4419 i.tm.name);
4420 return 0;
4421 }
4422
381d071f 4423 for (op = i.operands; --op >= 0;)
40fb9820 4424 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4425 {
40fb9820
L		 4426 if (i.types[op].bitfield.reg8)
4427 {
4428 i.suffix = BYTE_MNEM_SUFFIX;
4429 break;
4430 }
4431 else if (i.types[op].bitfield.reg16)
4432 {
4433 i.suffix = WORD_MNEM_SUFFIX;
4434 break;
4435 }
4436 else if (i.types[op].bitfield.reg32)
4437 {
4438 i.suffix = LONG_MNEM_SUFFIX;
4439 break;
4440 }
4441 else if (i.types[op].bitfield.reg64)
4442 {
4443 i.suffix = QWORD_MNEM_SUFFIX;
4444 break;
4445 }
381d071f
L		 4446 }
4447 }
29b0f896
AM		 4448 }
4449 else if (i.suffix == BYTE_MNEM_SUFFIX)
4450 {
2eb952a4
L		 4451 if (intel_syntax
4452 && i.tm.opcode_modifier.ignoresize
4453 && i.tm.opcode_modifier.no_bsuf)
4454 i.suffix = 0;
4455 else if (!check_byte_reg ())
29b0f896
AM		 4456 return 0;
4457 }
4458 else if (i.suffix == LONG_MNEM_SUFFIX)
4459 {
2eb952a4
L		 4460 if (intel_syntax
4461 && i.tm.opcode_modifier.ignoresize
4462 && i.tm.opcode_modifier.no_lsuf)
4463 i.suffix = 0;
4464 else if (!check_long_reg ())
29b0f896
AM		 4465 return 0;
4466 }
4467 else if (i.suffix == QWORD_MNEM_SUFFIX)
4468 {
955e1e6a
L		 4469 if (intel_syntax
4470 && i.tm.opcode_modifier.ignoresize
4471 && i.tm.opcode_modifier.no_qsuf)
4472 i.suffix = 0;
4473 else if (!check_qword_reg ())
29b0f896
AM		 4474 return 0;
4475 }
4476 else if (i.suffix == WORD_MNEM_SUFFIX)
4477 {
2eb952a4
L		 4478 if (intel_syntax
4479 && i.tm.opcode_modifier.ignoresize
4480 && i.tm.opcode_modifier.no_wsuf)
4481 i.suffix = 0;
4482 else if (!check_word_reg ())
29b0f896
AM		 4483 return 0;
4484 }
c0f3af97
L		 4485 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4486 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4487 {
c0f3af97 4488 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4489 should check if it is a valid suffix. */
4490 }
40fb9820 4491 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4492 /* Do nothing if the instruction is going to ignore the prefix. */
4493 ;
4494 else
4495 abort ();
4496 }
40fb9820 4497 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4498 && !i.suffix
4499 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4500 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4501 {
4502 i.suffix = stackop_size;
4503 }
9306ca4a
JB		 4504 else if (intel_syntax
4505 && !i.suffix
40fb9820
L		 4506 && (i.tm.operand_types[0].bitfield.jumpabsolute
4507 || i.tm.opcode_modifier.jumpbyte
4508 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4509 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4510 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4511 {
4512 switch (flag_code)
4513 {
4514 case CODE_64BIT:
40fb9820 4515 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4516 {
4517 i.suffix = QWORD_MNEM_SUFFIX;
4518 break;
4519 }
4520 case CODE_32BIT:
40fb9820 4521 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4522 i.suffix = LONG_MNEM_SUFFIX;
4523 break;
4524 case CODE_16BIT:
40fb9820 4525 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4526 i.suffix = WORD_MNEM_SUFFIX;
4527 break;
4528 }
4529 }
252b5132 4530
9306ca4a 4531 if (!i.suffix)
29b0f896 4532 {
9306ca4a
JB		 4533 if (!intel_syntax)
4534 {
40fb9820 4535 if (i.tm.opcode_modifier.w)
9306ca4a 4536 {
4eed87de
AM		 4537 as_bad (_("no instruction mnemonic suffix given and "
4538 "no register operands; can't size instruction"));
9306ca4a
JB		 4539 return 0;
4540 }
4541 }
4542 else
4543 {
40fb9820 4544 unsigned int suffixes;
7ab9ffdd 4545
40fb9820
L		 4546 suffixes = !i.tm.opcode_modifier.no_bsuf;
4547 if (!i.tm.opcode_modifier.no_wsuf)
4548 suffixes |= 1 << 1;
4549 if (!i.tm.opcode_modifier.no_lsuf)
4550 suffixes |= 1 << 2;
fc4adea1 4551 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4552 suffixes |= 1 << 3;
4553 if (!i.tm.opcode_modifier.no_ssuf)
4554 suffixes |= 1 << 4;
4555 if (!i.tm.opcode_modifier.no_qsuf)
4556 suffixes |= 1 << 5;
4557
4558 /* There are more than suffix matches. */
4559 if (i.tm.opcode_modifier.w
9306ca4a 4560 || ((suffixes & (suffixes - 1))
40fb9820
L		 4561 && !i.tm.opcode_modifier.defaultsize
4562 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4563 {
4564 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4565 return 0;
4566 }
4567 }
29b0f896 4568 }
252b5132 4569
9306ca4a
JB		 4570 /* Change the opcode based on the operand size given by i.suffix;
4571 We don't need to change things for byte insns. */
4572
582d5edd
L		 4573 if (i.suffix
4574 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4575 && i.suffix != XMMWORD_MNEM_SUFFIX
4576 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4577 {
4578 /* It's not a byte, select word/dword operation. */
40fb9820 4579 if (i.tm.opcode_modifier.w)
29b0f896 4580 {
40fb9820 4581 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4582 i.tm.base_opcode |= 8;
4583 else
4584 i.tm.base_opcode |= 1;
4585 }
0f3f3d8b 4586
29b0f896
AM		 4587 /* Now select between word & dword operations via the operand
4588 size prefix, except for instructions that will ignore this
4589 prefix anyway. */
ca61edf2 4590 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4591 {
ca61edf2
L		 4592 /* The address size override prefix changes the size of the
4593 first operand. */
40fb9820
L		 4594 if ((flag_code == CODE_32BIT
4595 && i.op->regs[0].reg_type.bitfield.reg16)
4596 || (flag_code != CODE_32BIT
4597 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4598 if (!add_prefix (ADDR_PREFIX_OPCODE))
4599 return 0;
4600 }
4601 else if (i.suffix != QWORD_MNEM_SUFFIX
4602 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4603 && !i.tm.opcode_modifier.ignoresize
4604 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4605 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4606 || (flag_code == CODE_64BIT
40fb9820 4607 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4608 {
4609 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4610
40fb9820 4611 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4612 prefix = ADDR_PREFIX_OPCODE;
252b5132 4613
29b0f896
AM		 4614 if (!add_prefix (prefix))
4615 return 0;
24eab124 4616 }
252b5132 4617
29b0f896
AM		 4618 /* Set mode64 for an operand. */
4619 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4620 && flag_code == CODE_64BIT
40fb9820 4621 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4622 {
4623 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4624 need rex64. cmpxchg8b is also a special case. */
4625 if (! (i.operands == 2
4626 && i.tm.base_opcode == 0x90
4627 && i.tm.extension_opcode == None
0dfbf9d7
L		 4628 && operand_type_equal (&i.types [0], &acc64)
4629 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4630 && ! (i.operands == 1
4631 && i.tm.base_opcode == 0xfc7
4632 && i.tm.extension_opcode == 1
40fb9820
L		 4633 && !operand_type_check (i.types [0], reg)
4634 && operand_type_check (i.types [0], anymem)))
f6bee062 4635 i.rex |= REX_W;
46e883c5 4636 }
3e73aa7c 4637
29b0f896
AM		 4638 /* Size floating point instruction. */
4639 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4640 if (i.tm.opcode_modifier.floatmf)
543613e9 4641 i.tm.base_opcode ^= 4;
29b0f896 4642 }
7ecd2f8b 4643
29b0f896
AM		 4644 return 1;
4645}
3e73aa7c 4646
29b0f896 4647static int
543613e9 4648check_byte_reg (void)
29b0f896
AM		 4649{
4650 int op;
543613e9 4651
29b0f896
AM		 4652 for (op = i.operands; --op >= 0;)
4653 {
4654 /* If this is an eight bit register, it's OK. If it's the 16 or
4655 32 bit version of an eight bit register, we will just use the
4656 low portion, and that's OK too. */
40fb9820 4657 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4658 continue;
4659
9344ff29
L		 4660 /* crc32 doesn't generate this warning. */
4661 if (i.tm.base_opcode == 0xf20f38f0)
4662 continue;
4663
40fb9820
L		 4664 if ((i.types[op].bitfield.reg16
4665 || i.types[op].bitfield.reg32
4666 || i.types[op].bitfield.reg64)
4667 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4668 {
4669 /* Prohibit these changes in the 64bit mode, since the
4670 lowering is more complicated. */
4671 if (flag_code == CODE_64BIT
40fb9820 4672 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4673 {
2b5d6a91 4674 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4675 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4676 i.suffix);
4677 return 0;
4678 }
4679#if REGISTER_WARNINGS
4680 if (!quiet_warnings
40fb9820 4681 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4682 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4683 register_prefix,
40fb9820 4684 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4685 ? REGNAM_AL - REGNAM_AX
4686 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4687 register_prefix,
29b0f896
AM		 4688 i.op[op].regs->reg_name,
4689 i.suffix);
4690#endif
4691 continue;
4692 }
4693 /* Any other register is bad. */
40fb9820
L		 4694 if (i.types[op].bitfield.reg16
4695 || i.types[op].bitfield.reg32
4696 || i.types[op].bitfield.reg64
4697 || i.types[op].bitfield.regmmx
4698 || i.types[op].bitfield.regxmm
c0f3af97 4699 || i.types[op].bitfield.regymm
40fb9820
L		 4700 || i.types[op].bitfield.sreg2
4701 || i.types[op].bitfield.sreg3
4702 || i.types[op].bitfield.control
4703 || i.types[op].bitfield.debug
4704 || i.types[op].bitfield.test
4705 || i.types[op].bitfield.floatreg
4706 || i.types[op].bitfield.floatacc)
29b0f896 4707 {
a540244d
L		 4708 as_bad (_("`%s%s' not allowed with `%s%c'"),
4709 register_prefix,
29b0f896
AM		 4710 i.op[op].regs->reg_name,
4711 i.tm.name,
4712 i.suffix);
4713 return 0;
4714 }
4715 }
4716 return 1;
4717}
4718
4719static int
e3bb37b5 4720check_long_reg (void)
29b0f896
AM		 4721{
4722 int op;
4723
4724 for (op = i.operands; --op >= 0;)
4725 /* Reject eight bit registers, except where the template requires
4726 them. (eg. movzb) */
40fb9820
L		 4727 if (i.types[op].bitfield.reg8
4728 && (i.tm.operand_types[op].bitfield.reg16
4729 || i.tm.operand_types[op].bitfield.reg32
4730 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4731 {
a540244d
L		 4732 as_bad (_("`%s%s' not allowed with `%s%c'"),
4733 register_prefix,
29b0f896
AM		 4734 i.op[op].regs->reg_name,
4735 i.tm.name,
4736 i.suffix);
4737 return 0;
4738 }
4739 /* Warn if the e prefix on a general reg is missing. */
4740 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4741 && i.types[op].bitfield.reg16
4742 && (i.tm.operand_types[op].bitfield.reg32
4743 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4744 {
4745 /* Prohibit these changes in the 64bit mode, since the
4746 lowering is more complicated. */
4747 if (flag_code == CODE_64BIT)
252b5132 4748 {
2b5d6a91 4749 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4750 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4751 i.suffix);
4752 return 0;
252b5132 4753 }
29b0f896
AM		 4754#if REGISTER_WARNINGS
4755 else
a540244d
L		 4756 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4757 register_prefix,
29b0f896 4758 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4759 register_prefix,
29b0f896
AM		 4760 i.op[op].regs->reg_name,
4761 i.suffix);
4762#endif
252b5132 4763 }
29b0f896 4764 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4765 else if (i.types[op].bitfield.reg64
4766 && (i.tm.operand_types[op].bitfield.reg32
4767 || i.tm.operand_types[op].bitfield.acc))
252b5132 4768 {
34828aad 4769 if (intel_syntax
ca61edf2 4770 && i.tm.opcode_modifier.toqword
40fb9820 4771 && !i.types[0].bitfield.regxmm)
34828aad 4772 {
ca61edf2 4773 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4774 i.suffix = QWORD_MNEM_SUFFIX;
4775 }
4776 else
4777 {
2b5d6a91 4778 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4779 register_prefix, i.op[op].regs->reg_name,
4780 i.suffix);
4781 return 0;
4782 }
29b0f896
AM		 4783 }
4784 return 1;
4785}
252b5132 4786
29b0f896 4787static int
e3bb37b5 4788check_qword_reg (void)
29b0f896
AM		 4789{
4790 int op;
252b5132 4791
29b0f896
AM		 4792 for (op = i.operands; --op >= 0; )
4793 /* Reject eight bit registers, except where the template requires
4794 them. (eg. movzb) */
40fb9820
L		 4795 if (i.types[op].bitfield.reg8
4796 && (i.tm.operand_types[op].bitfield.reg16
4797 || i.tm.operand_types[op].bitfield.reg32
4798 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4799 {
a540244d
L		 4800 as_bad (_("`%s%s' not allowed with `%s%c'"),
4801 register_prefix,
29b0f896
AM		 4802 i.op[op].regs->reg_name,
4803 i.tm.name,
4804 i.suffix);
4805 return 0;
4806 }
4807 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4808 else if ((i.types[op].bitfield.reg16
4809 || i.types[op].bitfield.reg32)
4810 && (i.tm.operand_types[op].bitfield.reg32
4811 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4812 {
4813 /* Prohibit these changes in the 64bit mode, since the
4814 lowering is more complicated. */
34828aad 4815 if (intel_syntax
ca61edf2 4816 && i.tm.opcode_modifier.todword
40fb9820 4817 && !i.types[0].bitfield.regxmm)
34828aad 4818 {
ca61edf2 4819 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4820 i.suffix = LONG_MNEM_SUFFIX;
4821 }
4822 else
4823 {
2b5d6a91 4824 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4825 register_prefix, i.op[op].regs->reg_name,
4826 i.suffix);
4827 return 0;
4828 }
252b5132 4829 }
29b0f896
AM		 4830 return 1;
4831}
252b5132 4832
29b0f896 4833static int
e3bb37b5 4834check_word_reg (void)
29b0f896
AM		 4835{
4836 int op;
4837 for (op = i.operands; --op >= 0;)
4838 /* Reject eight bit registers, except where the template requires
4839 them. (eg. movzb) */
40fb9820
L		 4840 if (i.types[op].bitfield.reg8
4841 && (i.tm.operand_types[op].bitfield.reg16
4842 || i.tm.operand_types[op].bitfield.reg32
4843 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4844 {
a540244d
L		 4845 as_bad (_("`%s%s' not allowed with `%s%c'"),
4846 register_prefix,
29b0f896
AM		 4847 i.op[op].regs->reg_name,
4848 i.tm.name,
4849 i.suffix);
4850 return 0;
4851 }
4852 /* Warn if the e prefix on a general reg is present. */
4853 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4854 && i.types[op].bitfield.reg32
4855 && (i.tm.operand_types[op].bitfield.reg16
4856 || i.tm.operand_types[op].bitfield.acc))
252b5132 4857 {
29b0f896
AM		 4858 /* Prohibit these changes in the 64bit mode, since the
4859 lowering is more complicated. */
4860 if (flag_code == CODE_64BIT)
252b5132 4861 {
2b5d6a91 4862 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4863 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4864 i.suffix);
4865 return 0;
252b5132 4866 }
29b0f896
AM		 4867 else
4868#if REGISTER_WARNINGS
a540244d
L		 4869 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4870 register_prefix,
29b0f896 4871 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4872 register_prefix,
29b0f896
AM		 4873 i.op[op].regs->reg_name,
4874 i.suffix);
4875#endif
4876 }
4877 return 1;
4878}
252b5132 4879
29b0f896 4880static int
40fb9820 4881update_imm (unsigned int j)
29b0f896 4882{
bc0844ae 4883 i386_operand_type overlap = i.types[j];
40fb9820
L		 4884 if ((overlap.bitfield.imm8
4885 || overlap.bitfield.imm8s
4886 || overlap.bitfield.imm16
4887 || overlap.bitfield.imm32
4888 || overlap.bitfield.imm32s
4889 || overlap.bitfield.imm64)
0dfbf9d7
L		 4890 && !operand_type_equal (&overlap, &imm8)
4891 && !operand_type_equal (&overlap, &imm8s)
4892 && !operand_type_equal (&overlap, &imm16)
4893 && !operand_type_equal (&overlap, &imm32)
4894 && !operand_type_equal (&overlap, &imm32s)
4895 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4896 {
4897 if (i.suffix)
4898 {
40fb9820
L		 4899 i386_operand_type temp;
4900
0dfbf9d7 4901 operand_type_set (&temp, 0);
7ab9ffdd 4902 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4903 {
4904 temp.bitfield.imm8 = overlap.bitfield.imm8;
4905 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4906 }
4907 else if (i.suffix == WORD_MNEM_SUFFIX)
4908 temp.bitfield.imm16 = overlap.bitfield.imm16;
4909 else if (i.suffix == QWORD_MNEM_SUFFIX)
4910 {
4911 temp.bitfield.imm64 = overlap.bitfield.imm64;
4912 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4913 }
4914 else
4915 temp.bitfield.imm32 = overlap.bitfield.imm32;
4916 overlap = temp;
29b0f896 4917 }
0dfbf9d7
L		 4918 else if (operand_type_equal (&overlap, &imm16_32_32s)
4919 || operand_type_equal (&overlap, &imm16_32)
4920 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4921 {
40fb9820 4922 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4923 overlap = imm16;
40fb9820 4924 else
65da13b5 4925 overlap = imm32s;
29b0f896 4926 }
0dfbf9d7
L		 4927 if (!operand_type_equal (&overlap, &imm8)
4928 && !operand_type_equal (&overlap, &imm8s)
4929 && !operand_type_equal (&overlap, &imm16)
4930 && !operand_type_equal (&overlap, &imm32)
4931 && !operand_type_equal (&overlap, &imm32s)
4932 && !operand_type_equal (&overlap, &imm64))
29b0f896 4933 {
4eed87de
AM		 4934 as_bad (_("no instruction mnemonic suffix given; "
4935 "can't determine immediate size"));
29b0f896
AM		 4936 return 0;
4937 }
4938 }
40fb9820 4939 i.types[j] = overlap;
29b0f896 4940
40fb9820
L		 4941 return 1;
4942}
4943
4944static int
4945finalize_imm (void)
4946{
bc0844ae 4947 unsigned int j, n;
29b0f896 4948
bc0844ae
L		 4949 /* Update the first 2 immediate operands. */
4950 n = i.operands > 2 ? 2 : i.operands;
4951 if (n)
4952 {
4953 for (j = 0; j < n; j++)
4954 if (update_imm (j) == 0)
4955 return 0;
40fb9820 4956
bc0844ae
L		 4957 /* The 3rd operand can't be immediate operand. */
4958 gas_assert (operand_type_check (i.types[2], imm) == 0);
4959 }
29b0f896
AM		 4960
4961 return 1;
4962}
4963
c0f3af97
L		 4964static int
4965bad_implicit_operand (int xmm)
4966{
91d6fa6a
NC		 4967 const char *ireg = xmm ? "xmm0" : "ymm0";
4968
c0f3af97
L		 4969 if (intel_syntax)
4970 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4971 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4972 else
4973 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4974 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4975 return 0;
4976}
4977
29b0f896 4978static int
e3bb37b5 4979process_operands (void)
29b0f896
AM		 4980{
4981 /* Default segment register this instruction will use for memory
4982 accesses. 0 means unknown. This is only for optimizing out
4983 unnecessary segment overrides. */
4984 const seg_entry *default_seg = 0;
4985
2426c15f 4986 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4987 {
91d6fa6a
NC		 4988 unsigned int dupl = i.operands;
4989 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4990 unsigned int j;
4991
c0f3af97 4992 /* The destination must be an xmm register. */
9c2799c2 4993 gas_assert (i.reg_operands
91d6fa6a 4994 && MAX_OPERANDS > dupl
7ab9ffdd 4995 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4996
4997 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4998 {
c0f3af97 4999 /* The first operand is implicit and must be xmm0. */
9c2799c2 5000 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 5001 if (i.op[0].regs->reg_num != 0)
5002 return bad_implicit_operand (1);
5003
8cd7925b 5004 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5005 {
5006 /* Keep xmm0 for instructions with VEX prefix and 3
5007 sources. */
5008 goto duplicate;
5009 }
e2ec9d29 5010 else
c0f3af97
L		 5011 {
5012 /* We remove the first xmm0 and keep the number of
5013 operands unchanged, which in fact duplicates the
5014 destination. */
5015 for (j = 1; j < i.operands; j++)
5016 {
5017 i.op[j - 1] = i.op[j];
5018 i.types[j - 1] = i.types[j];
5019 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5020 }
5021 }
5022 }
5023 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5024 {
91d6fa6a 5025 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5026 && (i.tm.opcode_modifier.vexsources
5027 == VEX3SOURCES));
c0f3af97
L		 5028
5029 /* Add the implicit xmm0 for instructions with VEX prefix
5030 and 3 sources. */
5031 for (j = i.operands; j > 0; j--)
5032 {
5033 i.op[j] = i.op[j - 1];
5034 i.types[j] = i.types[j - 1];
5035 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5036 }
5037 i.op[0].regs
5038 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5039 i.types[0] = regxmm;
c0f3af97
L		 5040 i.tm.operand_types[0] = regxmm;
5041
5042 i.operands += 2;
5043 i.reg_operands += 2;
5044 i.tm.operands += 2;
5045
91d6fa6a 5046 dupl++;
c0f3af97 5047 dest++;
91d6fa6a
NC		 5048 i.op[dupl] = i.op[dest];
5049 i.types[dupl] = i.types[dest];
5050 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5051 }
c0f3af97
L		 5052 else
5053 {
5054duplicate:
5055 i.operands++;
5056 i.reg_operands++;
5057 i.tm.operands++;
5058
91d6fa6a
NC		 5059 i.op[dupl] = i.op[dest];
5060 i.types[dupl] = i.types[dest];
5061 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5062 }
5063
5064 if (i.tm.opcode_modifier.immext)
5065 process_immext ();
5066 }
5067 else if (i.tm.opcode_modifier.firstxmm0)
5068 {
5069 unsigned int j;
5070
5071 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5072 gas_assert (i.reg_operands
7ab9ffdd
L		 5073 && (operand_type_equal (&i.types[0], &regxmm)
5074 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 5075 if (i.op[0].regs->reg_num != 0)
5076 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5077
5078 for (j = 1; j < i.operands; j++)
5079 {
5080 i.op[j - 1] = i.op[j];
5081 i.types[j - 1] = i.types[j];
5082
5083 /* We need to adjust fields in i.tm since they are used by
5084 build_modrm_byte. */
5085 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5086 }
5087
e2ec9d29
L		 5088 i.operands--;
5089 i.reg_operands--;
e2ec9d29
L		 5090 i.tm.operands--;
5091 }
5092 else if (i.tm.opcode_modifier.regkludge)
5093 {
5094 /* The imul $imm, %reg instruction is converted into
5095 imul $imm, %reg, %reg, and the clr %reg instruction
5096 is converted into xor %reg, %reg. */
5097
5098 unsigned int first_reg_op;
5099
5100 if (operand_type_check (i.types[0], reg))
5101 first_reg_op = 0;
5102 else
5103 first_reg_op = 1;
5104 /* Pretend we saw the extra register operand. */
9c2799c2 5105 gas_assert (i.reg_operands == 1
7ab9ffdd 5106 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5107 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5108 i.types[first_reg_op + 1] = i.types[first_reg_op];
5109 i.operands++;
5110 i.reg_operands++;
29b0f896
AM		 5111 }
5112
40fb9820 5113 if (i.tm.opcode_modifier.shortform)
29b0f896 5114 {
40fb9820
L		 5115 if (i.types[0].bitfield.sreg2
5116 || i.types[0].bitfield.sreg3)
29b0f896 5117 {
4eed87de
AM		 5118 if (i.tm.base_opcode == POP_SEG_SHORT
5119 && i.op[0].regs->reg_num == 1)
29b0f896 5120 {
a87af027 5121 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5122 return 0;
29b0f896 5123 }
4eed87de
AM		 5124 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5125 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5126 i.rex |= REX_B;
4eed87de
AM		 5127 }
5128 else
5129 {
7ab9ffdd 5130 /* The register or float register operand is in operand
85f10a01 5131 0 or 1. */
40fb9820 5132 unsigned int op;
7ab9ffdd
L		 5133
5134 if (i.types[0].bitfield.floatreg
5135 || operand_type_check (i.types[0], reg))
5136 op = 0;
5137 else
5138 op = 1;
4eed87de
AM		 5139 /* Register goes in low 3 bits of opcode. */
5140 i.tm.base_opcode |= i.op[op].regs->reg_num;
5141 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5142 i.rex |= REX_B;
40fb9820 5143 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5144 {
4eed87de
AM		 5145 /* Warn about some common errors, but press on regardless.
5146 The first case can be generated by gcc (<= 2.8.1). */
5147 if (i.operands == 2)
5148 {
5149 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5150 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5151 register_prefix, i.op[!intel_syntax].regs->reg_name,
5152 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5153 }
5154 else
5155 {
5156 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5157 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5158 register_prefix, i.op[0].regs->reg_name);
4eed87de 5159 }
29b0f896
AM		 5160 }
5161 }
5162 }
40fb9820 5163 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5164 {
5165 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5166 must be put into the modrm byte). Now, we make the modrm and
5167 index base bytes based on all the info we've collected. */
29b0f896
AM		 5168
5169 default_seg = build_modrm_byte ();
5170 }
8a2ed489 5171 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5172 {
5173 default_seg = &ds;
5174 }
40fb9820 5175 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5176 {
5177 /* For the string instructions that allow a segment override
5178 on one of their operands, the default segment is ds. */
5179 default_seg = &ds;
5180 }
5181
75178d9d
L		 5182 if (i.tm.base_opcode == 0x8d /* lea */
5183 && i.seg[0]
5184 && !quiet_warnings)
30123838 5185 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5186
5187 /* If a segment was explicitly specified, and the specified segment
5188 is not the default, use an opcode prefix to select it. If we
5189 never figured out what the default segment is, then default_seg
5190 will be zero at this point, and the specified segment prefix will
5191 always be used. */
29b0f896
AM		 5192 if ((i.seg[0]) && (i.seg[0] != default_seg))
5193 {
5194 if (!add_prefix (i.seg[0]->seg_prefix))
5195 return 0;
5196 }
5197 return 1;
5198}
5199
5200static const seg_entry *
e3bb37b5 5201build_modrm_byte (void)
29b0f896
AM		 5202{
5203 const seg_entry *default_seg = 0;
c0f3af97 5204 unsigned int source, dest;
8cd7925b 5205 int vex_3_sources;
c0f3af97
L		 5206
5207 /* The first operand of instructions with VEX prefix and 3 sources
5208 must be VEX_Imm4. */
8cd7925b 5209 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5210 if (vex_3_sources)
5211 {
91d6fa6a 5212 unsigned int nds, reg_slot;
4c2c6516 5213 expressionS *exp;
c0f3af97 5214
922d8de8 5215 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5216 && i.tm.opcode_modifier.immext)
5217 {
5218 dest = i.operands - 2;
5219 gas_assert (dest == 3);
5220 }
922d8de8 5221 else
a683cc34 5222 dest = i.operands - 1;
c0f3af97 5223 nds = dest - 1;
922d8de8 5224
a683cc34
SP		 5225 /* There are 2 kinds of instructions:
5226 1. 5 operands: 4 register operands or 3 register operands
5227 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5228 VexW0 or VexW1. The destination must be either XMM or YMM
5229 register.
5230 2. 4 operands: 4 register operands or 3 register operands
5231 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5232 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5233 || (i.reg_operands == 3 && i.mem_operands == 1))
5234 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5235 && (i.tm.opcode_modifier.veximmext
5236 || (i.imm_operands == 1
5237 && i.types[0].bitfield.vec_imm4
5238 && (i.tm.opcode_modifier.vexw == VEXW0
5239 || i.tm.opcode_modifier.vexw == VEXW1)
5240 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5241 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5242
5243 if (i.imm_operands == 0)
5244 {
5245 /* When there is no immediate operand, generate an 8bit
5246 immediate operand to encode the first operand. */
5247 exp = &im_expressions[i.imm_operands++];
5248 i.op[i.operands].imms = exp;
5249 i.types[i.operands] = imm8;
5250 i.operands++;
5251 /* If VexW1 is set, the first operand is the source and
5252 the second operand is encoded in the immediate operand. */
5253 if (i.tm.opcode_modifier.vexw == VEXW1)
5254 {
5255 source = 0;
5256 reg_slot = 1;
5257 }
5258 else
5259 {
5260 source = 1;
5261 reg_slot = 0;
5262 }
5263
5264 /* FMA swaps REG and NDS. */
5265 if (i.tm.cpu_flags.bitfield.cpufma)
5266 {
5267 unsigned int tmp;
5268 tmp = reg_slot;
5269 reg_slot = nds;
5270 nds = tmp;
5271 }
5272
24981e7b
L		 5273 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5274 &regxmm)
a683cc34
SP		 5275 || operand_type_equal (&i.tm.operand_types[reg_slot],
5276 &regymm));
5277 exp->X_op = O_constant;
5278 exp->X_add_number
5279 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5280 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5281 << 4);
a683cc34 5282 }
922d8de8 5283 else
a683cc34
SP		 5284 {
5285 unsigned int imm_slot;
5286
5287 if (i.tm.opcode_modifier.vexw == VEXW0)
5288 {
5289 /* If VexW0 is set, the third operand is the source and
5290 the second operand is encoded in the immediate
5291 operand. */
5292 source = 2;
5293 reg_slot = 1;
5294 }
5295 else
5296 {
5297 /* VexW1 is set, the second operand is the source and
5298 the third operand is encoded in the immediate
5299 operand. */
5300 source = 1;
5301 reg_slot = 2;
5302 }
5303
5304 if (i.tm.opcode_modifier.immext)
5305 {
5306 /* When ImmExt is set, the immdiate byte is the last
5307 operand. */
5308 imm_slot = i.operands - 1;
5309 source--;
5310 reg_slot--;
5311 }
5312 else
5313 {
5314 imm_slot = 0;
5315
5316 /* Turn on Imm8 so that output_imm will generate it. */
5317 i.types[imm_slot].bitfield.imm8 = 1;
5318 }
5319
24981e7b
L		 5320 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5321 &regxmm)
5322 || operand_type_equal (&i.tm.operand_types[reg_slot],
5323 &regymm));
a683cc34
SP		 5324 i.op[imm_slot].imms->X_add_number
5325 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5326 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5327 << 4);
a683cc34
SP		 5328 }
5329
5330 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5331 || operand_type_equal (&i.tm.operand_types[nds],
5332 &regymm));
dae39acc 5333 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5334 }
5335 else
5336 source = dest = 0;
29b0f896
AM		 5337
5338 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5339 implicit registers do not count. If there are 3 register
5340 operands, it must be a instruction with VexNDS. For a
5341 instruction with VexNDD, the destination register is encoded
5342 in VEX prefix. If there are 4 register operands, it must be
5343 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5344 if (i.mem_operands == 0
5345 && ((i.reg_operands == 2
2426c15f 5346 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5347 || (i.reg_operands == 3
2426c15f 5348 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5349 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5350 {
cab737b9
L		 5351 switch (i.operands)
5352 {
5353 case 2:
5354 source = 0;
5355 break;
5356 case 3:
c81128dc
L		 5357 /* When there are 3 operands, one of them may be immediate,
5358 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5359 the first operand must be shift count register (cl) or it
5360 is an instruction with VexNDS. */
9c2799c2 5361 gas_assert (i.imm_operands == 1
7ab9ffdd 5362 || (i.imm_operands == 0
2426c15f 5363 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5364 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5365 if (operand_type_check (i.types[0], imm)
5366 || i.types[0].bitfield.shiftcount)
5367 source = 1;
5368 else
5369 source = 0;
cab737b9
L		 5370 break;
5371 case 4:
368d64cc
L		 5372 /* When there are 4 operands, the first two must be 8bit
5373 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5374 one.
5375
5376 For instructions with VexNDS, if the first operand
5377 an imm8, the source operand is the 2nd one. If the last
5378 operand is imm8, the source operand is the first one. */
9c2799c2 5379 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5380 && i.types[0].bitfield.imm8
5381 && i.types[1].bitfield.imm8)
2426c15f 5382 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5383 && i.imm_operands == 1
5384 && (i.types[0].bitfield.imm8
5385 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5386 if (i.imm_operands == 2)
5387 source = 2;
5388 else
c0f3af97
L		 5389 {
5390 if (i.types[0].bitfield.imm8)
5391 source = 1;
5392 else
5393 source = 0;
5394 }
c0f3af97
L		 5395 break;
5396 case 5:
cab737b9
L		 5397 break;
5398 default:
5399 abort ();
5400 }
5401
c0f3af97
L		 5402 if (!vex_3_sources)
5403 {
5404 dest = source + 1;
5405
2426c15f 5406 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5407 {
5408 /* For instructions with VexNDS, the register-only
f12dc422
L		 5409 source operand must be 32/64bit integer, XMM or
5410 YMM register. It is encoded in VEX prefix. We
5411 need to clear RegMem bit before calling
5412 operand_type_equal. */
5413
5414 i386_operand_type op;
5415 unsigned int vvvv;
5416
5417 /* Check register-only source operand when two source
5418 operands are swapped. */
5419 if (!i.tm.operand_types[source].bitfield.baseindex
5420 && i.tm.operand_types[dest].bitfield.baseindex)
5421 {
5422 vvvv = source;
5423 source = dest;
5424 }
5425 else
5426 vvvv = dest;
5427
5428 op = i.tm.operand_types[vvvv];
fa99fab2 5429 op.bitfield.regmem = 0;
c0f3af97 5430 if ((dest + 1) >= i.operands
f12dc422
L		 5431 || (op.bitfield.reg32 != 1
5432 && !op.bitfield.reg64 != 1
5433 && !operand_type_equal (&op, &regxmm)
fa99fab2 5434 && !operand_type_equal (&op, &regymm)))
c0f3af97 5435 abort ();
f12dc422 5436 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5437 dest++;
5438 }
5439 }
29b0f896
AM		 5440
5441 i.rm.mode = 3;
5442 /* One of the register operands will be encoded in the i.tm.reg
5443 field, the other in the combined i.tm.mode and i.tm.regmem
5444 fields. If no form of this instruction supports a memory
5445 destination operand, then we assume the source operand may
5446 sometimes be a memory operand and so we need to store the
5447 destination in the i.rm.reg field. */
40fb9820
L		 5448 if (!i.tm.operand_types[dest].bitfield.regmem
5449 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5450 {
5451 i.rm.reg = i.op[dest].regs->reg_num;
5452 i.rm.regmem = i.op[source].regs->reg_num;
5453 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5454 i.rex |= REX_R;
29b0f896 5455 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5456 i.rex |= REX_B;
29b0f896
AM		 5457 }
5458 else
5459 {
5460 i.rm.reg = i.op[source].regs->reg_num;
5461 i.rm.regmem = i.op[dest].regs->reg_num;
5462 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5463 i.rex |= REX_B;
29b0f896 5464 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5465 i.rex |= REX_R;
29b0f896 5466 }
161a04f6 5467 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5468 {
40fb9820
L		 5469 if (!i.types[0].bitfield.control
5470 && !i.types[1].bitfield.control)
c4a530c5 5471 abort ();
161a04f6 5472 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5473 add_prefix (LOCK_PREFIX_OPCODE);
5474 }
29b0f896
AM		 5475 }
5476 else
5477 { /* If it's not 2 reg operands... */
c0f3af97
L		 5478 unsigned int mem;
5479
29b0f896
AM		 5480 if (i.mem_operands)
5481 {
5482 unsigned int fake_zero_displacement = 0;
99018f42 5483 unsigned int op;
4eed87de 5484
7ab9ffdd
L		 5485 for (op = 0; op < i.operands; op++)
5486 if (operand_type_check (i.types[op], anymem))
5487 break;
7ab9ffdd 5488 gas_assert (op < i.operands);
29b0f896 5489
6c30d220
L		 5490 if (i.tm.opcode_modifier.vecsib)
5491 {
5492 if (i.index_reg->reg_num == RegEiz
5493 || i.index_reg->reg_num == RegRiz)
5494 abort ();
5495
5496 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5497 if (!i.base_reg)
5498 {
5499 i.sib.base = NO_BASE_REGISTER;
5500 i.sib.scale = i.log2_scale_factor;
5501 i.types[op].bitfield.disp8 = 0;
5502 i.types[op].bitfield.disp16 = 0;
5503 i.types[op].bitfield.disp64 = 0;
5504 if (flag_code != CODE_64BIT)
5505 {
5506 /* Must be 32 bit */
5507 i.types[op].bitfield.disp32 = 1;
5508 i.types[op].bitfield.disp32s = 0;
5509 }
5510 else
5511 {
5512 i.types[op].bitfield.disp32 = 0;
5513 i.types[op].bitfield.disp32s = 1;
5514 }
5515 }
5516 i.sib.index = i.index_reg->reg_num;
5517 if ((i.index_reg->reg_flags & RegRex) != 0)
5518 i.rex |= REX_X;
5519 }
5520
29b0f896
AM		 5521 default_seg = &ds;
5522
5523 if (i.base_reg == 0)
5524 {
5525 i.rm.mode = 0;
5526 if (!i.disp_operands)
6c30d220
L		 5527 {
5528 fake_zero_displacement = 1;
5529 /* Instructions with VSIB byte need 32bit displacement
5530 if there is no base register. */
5531 if (i.tm.opcode_modifier.vecsib)
5532 i.types[op].bitfield.disp32 = 1;
5533 }
29b0f896
AM		 5534 if (i.index_reg == 0)
5535 {
6c30d220 5536 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5537 /* Operand is just <disp> */
20f0a1fc 5538 if (flag_code == CODE_64BIT)
29b0f896
AM		 5539 {
5540 /* 64bit mode overwrites the 32bit absolute
5541 addressing by RIP relative addressing and
5542 absolute addressing is encoded by one of the
5543 redundant SIB forms. */
5544 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5545 i.sib.base = NO_BASE_REGISTER;
5546 i.sib.index = NO_INDEX_REGISTER;
fc225355 5547 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5548 ? disp32s : disp32);
20f0a1fc 5549 }
fc225355
L		 5550 else if ((flag_code == CODE_16BIT)
5551 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5552 {
5553 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5554 i.types[op] = disp16;
20f0a1fc
NC		 5555 }
5556 else
5557 {
5558 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5559 i.types[op] = disp32;
29b0f896
AM		 5560 }
5561 }
6c30d220 5562 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5563 {
6c30d220 5564 /* !i.base_reg && i.index_reg */
db51cc60
L		 5565 if (i.index_reg->reg_num == RegEiz
5566 || i.index_reg->reg_num == RegRiz)
5567 i.sib.index = NO_INDEX_REGISTER;
5568 else
5569 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5570 i.sib.base = NO_BASE_REGISTER;
5571 i.sib.scale = i.log2_scale_factor;
5572 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5573 i.types[op].bitfield.disp8 = 0;
5574 i.types[op].bitfield.disp16 = 0;
5575 i.types[op].bitfield.disp64 = 0;
29b0f896 5576 if (flag_code != CODE_64BIT)
40fb9820
L		 5577 {
5578 /* Must be 32 bit */
5579 i.types[op].bitfield.disp32 = 1;
5580 i.types[op].bitfield.disp32s = 0;
5581 }
29b0f896 5582 else
40fb9820
L		 5583 {
5584 i.types[op].bitfield.disp32 = 0;
5585 i.types[op].bitfield.disp32s = 1;
5586 }
29b0f896 5587 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5588 i.rex |= REX_X;
29b0f896
AM		 5589 }
5590 }
5591 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5592 else if (i.base_reg->reg_num == RegRip ||
5593 i.base_reg->reg_num == RegEip)
29b0f896 5594 {
6c30d220 5595 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5596 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5597 i.types[op].bitfield.disp8 = 0;
5598 i.types[op].bitfield.disp16 = 0;
5599 i.types[op].bitfield.disp32 = 0;
5600 i.types[op].bitfield.disp32s = 1;
5601 i.types[op].bitfield.disp64 = 0;
71903a11 5602 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5603 if (! i.disp_operands)
5604 fake_zero_displacement = 1;
29b0f896 5605 }
40fb9820 5606 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5607 {
6c30d220 5608 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5609 switch (i.base_reg->reg_num)
5610 {
5611 case 3: /* (%bx) */
5612 if (i.index_reg == 0)
5613 i.rm.regmem = 7;
5614 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5615 i.rm.regmem = i.index_reg->reg_num - 6;
5616 break;
5617 case 5: /* (%bp) */
5618 default_seg = &ss;
5619 if (i.index_reg == 0)
5620 {
5621 i.rm.regmem = 6;
40fb9820 5622 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5623 {
5624 /* fake (%bp) into 0(%bp) */
40fb9820 5625 i.types[op].bitfield.disp8 = 1;
252b5132 5626 fake_zero_displacement = 1;
29b0f896
AM		 5627 }
5628 }
5629 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5630 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5631 break;
5632 default: /* (%si) -> 4 or (%di) -> 5 */
5633 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5634 }
5635 i.rm.mode = mode_from_disp_size (i.types[op]);
5636 }
5637 else /* i.base_reg and 32/64 bit mode */
5638 {
5639 if (flag_code == CODE_64BIT
40fb9820
L		 5640 && operand_type_check (i.types[op], disp))
5641 {
5642 i386_operand_type temp;
0dfbf9d7 5643 operand_type_set (&temp, 0);
40fb9820
L		 5644 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5645 i.types[op] = temp;
5646 if (i.prefix[ADDR_PREFIX] == 0)
5647 i.types[op].bitfield.disp32s = 1;
5648 else
5649 i.types[op].bitfield.disp32 = 1;
5650 }
20f0a1fc 5651
6c30d220
L		 5652 if (!i.tm.opcode_modifier.vecsib)
5653 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5654 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5655 i.rex |= REX_B;
29b0f896
AM		 5656 i.sib.base = i.base_reg->reg_num;
5657 /* x86-64 ignores REX prefix bit here to avoid decoder
5658 complications. */
5659 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5660 {
5661 default_seg = &ss;
5662 if (i.disp_operands == 0)
5663 {
5664 fake_zero_displacement = 1;
40fb9820 5665 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5666 }
5667 }
5668 else if (i.base_reg->reg_num == ESP_REG_NUM)
5669 {
5670 default_seg = &ss;
5671 }
5672 i.sib.scale = i.log2_scale_factor;
5673 if (i.index_reg == 0)
5674 {
6c30d220 5675 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5676 /* <disp>(%esp) becomes two byte modrm with no index
5677 register. We've already stored the code for esp
5678 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5679 Any base register besides %esp will not use the
5680 extra modrm byte. */
5681 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5682 }
6c30d220 5683 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5684 {
db51cc60
L		 5685 if (i.index_reg->reg_num == RegEiz
5686 || i.index_reg->reg_num == RegRiz)
5687 i.sib.index = NO_INDEX_REGISTER;
5688 else
5689 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5690 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5691 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5692 i.rex |= REX_X;
29b0f896 5693 }
67a4f2b7
AO		 5694
5695 if (i.disp_operands
5696 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5697 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5698 i.rm.mode = 0;
5699 else
5700 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5701 }
252b5132 5702
29b0f896
AM		 5703 if (fake_zero_displacement)
5704 {
5705 /* Fakes a zero displacement assuming that i.types[op]
5706 holds the correct displacement size. */
5707 expressionS *exp;
5708
9c2799c2 5709 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5710 exp = &disp_expressions[i.disp_operands++];
5711 i.op[op].disps = exp;
5712 exp->X_op = O_constant;
5713 exp->X_add_number = 0;
5714 exp->X_add_symbol = (symbolS *) 0;
5715 exp->X_op_symbol = (symbolS *) 0;
5716 }
c0f3af97
L		 5717
5718 mem = op;
29b0f896 5719 }
c0f3af97
L		 5720 else
5721 mem = ~0;
252b5132 5722
8c43a48b 5723 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5724 {
5725 if (operand_type_check (i.types[0], imm))
5726 i.vex.register_specifier = NULL;
5727 else
5728 {
5729 /* VEX.vvvv encodes one of the sources when the first
5730 operand is not an immediate. */
1ef99a7b 5731 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5732 i.vex.register_specifier = i.op[0].regs;
5733 else
5734 i.vex.register_specifier = i.op[1].regs;
5735 }
5736
5737 /* Destination is a XMM register encoded in the ModRM.reg
5738 and VEX.R bit. */
5739 i.rm.reg = i.op[2].regs->reg_num;
5740 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5741 i.rex |= REX_R;
5742
5743 /* ModRM.rm and VEX.B encodes the other source. */
5744 if (!i.mem_operands)
5745 {
5746 i.rm.mode = 3;
5747
1ef99a7b 5748 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5749 i.rm.regmem = i.op[1].regs->reg_num;
5750 else
5751 i.rm.regmem = i.op[0].regs->reg_num;
5752
5753 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5754 i.rex |= REX_B;
5755 }
5756 }
2426c15f 5757 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5758 {
5759 i.vex.register_specifier = i.op[2].regs;
5760 if (!i.mem_operands)
5761 {
5762 i.rm.mode = 3;
5763 i.rm.regmem = i.op[1].regs->reg_num;
5764 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5765 i.rex |= REX_B;
5766 }
5767 }
29b0f896
AM		 5768 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5769 (if any) based on i.tm.extension_opcode. Again, we must be
5770 careful to make sure that segment/control/debug/test/MMX
5771 registers are coded into the i.rm.reg field. */
f88c9eb0 5772 else if (i.reg_operands)
29b0f896 5773 {
99018f42 5774 unsigned int op;
7ab9ffdd
L		 5775 unsigned int vex_reg = ~0;
5776
5777 for (op = 0; op < i.operands; op++)
5778 if (i.types[op].bitfield.reg8
5779 || i.types[op].bitfield.reg16
5780 || i.types[op].bitfield.reg32
5781 || i.types[op].bitfield.reg64
5782 || i.types[op].bitfield.regmmx
5783 || i.types[op].bitfield.regxmm
5784 || i.types[op].bitfield.regymm
5785 || i.types[op].bitfield.sreg2
5786 || i.types[op].bitfield.sreg3
5787 || i.types[op].bitfield.control
5788 || i.types[op].bitfield.debug
5789 || i.types[op].bitfield.test)
5790 break;
c0209578 5791
7ab9ffdd
L		 5792 if (vex_3_sources)
5793 op = dest;
2426c15f 5794 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5795 {
5796 /* For instructions with VexNDS, the register-only
5797 source operand is encoded in VEX prefix. */
5798 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5799
7ab9ffdd 5800 if (op > mem)
c0f3af97 5801 {
7ab9ffdd
L		 5802 vex_reg = op++;
5803 gas_assert (op < i.operands);
c0f3af97
L		 5804 }
5805 else
c0f3af97 5806 {
f12dc422
L		 5807 /* Check register-only source operand when two source
5808 operands are swapped. */
5809 if (!i.tm.operand_types[op].bitfield.baseindex
5810 && i.tm.operand_types[op + 1].bitfield.baseindex)
5811 {
5812 vex_reg = op;
5813 op += 2;
5814 gas_assert (mem == (vex_reg + 1)
5815 && op < i.operands);
5816 }
5817 else
5818 {
5819 vex_reg = op + 1;
5820 gas_assert (vex_reg < i.operands);
5821 }
c0f3af97 5822 }
7ab9ffdd 5823 }
2426c15f 5824 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5825 {
f12dc422 5826 /* For instructions with VexNDD, the register destination
7ab9ffdd 5827 is encoded in VEX prefix. */
f12dc422
L		 5828 if (i.mem_operands == 0)
5829 {
5830 /* There is no memory operand. */
5831 gas_assert ((op + 2) == i.operands);
5832 vex_reg = op + 1;
5833 }
5834 else
5835 {
5836 /* There are only 2 operands. */
5837 gas_assert (op < 2 && i.operands == 2);
5838 vex_reg = 1;
5839 }
7ab9ffdd
L		 5840 }
5841 else
5842 gas_assert (op < i.operands);
99018f42 5843
7ab9ffdd
L		 5844 if (vex_reg != (unsigned int) ~0)
5845 {
f12dc422 5846 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5847
f12dc422
L		 5848 if (type->bitfield.reg32 != 1
5849 && type->bitfield.reg64 != 1
5850 && !operand_type_equal (type, &regxmm)
5851 && !operand_type_equal (type, &regymm))
7ab9ffdd 5852 abort ();
f88c9eb0 5853
7ab9ffdd
L		 5854 i.vex.register_specifier = i.op[vex_reg].regs;
5855 }
5856
1b9f0c97
L		 5857 /* Don't set OP operand twice. */
5858 if (vex_reg != op)
7ab9ffdd 5859 {
1b9f0c97
L		 5860 /* If there is an extension opcode to put here, the
5861 register number must be put into the regmem field. */
5862 if (i.tm.extension_opcode != None)
5863 {
5864 i.rm.regmem = i.op[op].regs->reg_num;
5865 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5866 i.rex |= REX_B;
5867 }
5868 else
5869 {
5870 i.rm.reg = i.op[op].regs->reg_num;
5871 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5872 i.rex |= REX_R;
5873 }
7ab9ffdd 5874 }
252b5132 5875
29b0f896
AM		 5876 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5877 must set it to 3 to indicate this is a register operand
5878 in the regmem field. */
5879 if (!i.mem_operands)
5880 i.rm.mode = 3;
5881 }
252b5132 5882
29b0f896 5883 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5884 if (i.tm.extension_opcode != None)
29b0f896
AM		 5885 i.rm.reg = i.tm.extension_opcode;
5886 }
5887 return default_seg;
5888}
252b5132 5889
29b0f896 5890static void
e3bb37b5 5891output_branch (void)
29b0f896
AM		 5892{
5893 char *p;
f8a5c266 5894 int size;
29b0f896
AM		 5895 int code16;
5896 int prefix;
5897 relax_substateT subtype;
5898 symbolS *sym;
5899 offsetT off;
5900
f8a5c266
L		 5901 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5902 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5903
5904 prefix = 0;
5905 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5906 {
29b0f896
AM		 5907 prefix = 1;
5908 i.prefixes -= 1;
5909 code16 ^= CODE16;
252b5132 5910 }
29b0f896
AM		 5911 /* Pentium4 branch hints. */
5912 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5913 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5914 {
29b0f896
AM		 5915 prefix++;
5916 i.prefixes--;
5917 }
5918 if (i.prefix[REX_PREFIX] != 0)
5919 {
5920 prefix++;
5921 i.prefixes--;
2f66722d
AM		 5922 }
5923
29b0f896
AM		 5924 if (i.prefixes != 0 && !intel_syntax)
5925 as_warn (_("skipping prefixes on this instruction"));
5926
5927 /* It's always a symbol; End frag & setup for relax.
5928 Make sure there is enough room in this frag for the largest
5929 instruction we may generate in md_convert_frag. This is 2
5930 bytes for the opcode and room for the prefix and largest
5931 displacement. */
5932 frag_grow (prefix + 2 + 4);
5933 /* Prefix and 1 opcode byte go in fr_fix. */
5934 p = frag_more (prefix + 1);
5935 if (i.prefix[DATA_PREFIX] != 0)
5936 *p++ = DATA_PREFIX_OPCODE;
5937 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5938 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5939 *p++ = i.prefix[SEG_PREFIX];
5940 if (i.prefix[REX_PREFIX] != 0)
5941 *p++ = i.prefix[REX_PREFIX];
5942 *p = i.tm.base_opcode;
5943
5944 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5945 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5946 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5947 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5948 else
f8a5c266 5949 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5950 subtype |= code16;
3e73aa7c 5951
29b0f896
AM		 5952 sym = i.op[0].disps->X_add_symbol;
5953 off = i.op[0].disps->X_add_number;
3e73aa7c 5954
29b0f896
AM		 5955 if (i.op[0].disps->X_op != O_constant
5956 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5957 {
29b0f896
AM		 5958 /* Handle complex expressions. */
5959 sym = make_expr_symbol (i.op[0].disps);
5960 off = 0;
5961 }
3e73aa7c 5962
29b0f896
AM		 5963 /* 1 possible extra opcode + 4 byte displacement go in var part.
5964 Pass reloc in fr_var. */
5965 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5966}
3e73aa7c 5967
29b0f896 5968static void
e3bb37b5 5969output_jump (void)
29b0f896
AM		 5970{
5971 char *p;
5972 int size;
3e02c1cc 5973 fixS *fixP;
29b0f896 5974
40fb9820 5975 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5976 {
5977 /* This is a loop or jecxz type instruction. */
5978 size = 1;
5979 if (i.prefix[ADDR_PREFIX] != 0)
5980 {
5981 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5982 i.prefixes -= 1;
5983 }
5984 /* Pentium4 branch hints. */
5985 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5986 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5987 {
5988 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5989 i.prefixes--;
3e73aa7c
JH		 5990 }
5991 }
29b0f896
AM		 5992 else
5993 {
5994 int code16;
3e73aa7c 5995
29b0f896
AM		 5996 code16 = 0;
5997 if (flag_code == CODE_16BIT)
5998 code16 = CODE16;
3e73aa7c 5999
29b0f896
AM		 6000 if (i.prefix[DATA_PREFIX] != 0)
6001 {
6002 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6003 i.prefixes -= 1;
6004 code16 ^= CODE16;
6005 }
252b5132 6006
29b0f896
AM		 6007 size = 4;
6008 if (code16)
6009 size = 2;
6010 }
9fcc94b6 6011
29b0f896
AM		 6012 if (i.prefix[REX_PREFIX] != 0)
6013 {
6014 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6015 i.prefixes -= 1;
6016 }
252b5132 6017
29b0f896
AM		 6018 if (i.prefixes != 0 && !intel_syntax)
6019 as_warn (_("skipping prefixes on this instruction"));
e0890092 6020
29b0f896
AM		 6021 p = frag_more (1 + size);
6022 *p++ = i.tm.base_opcode;
e0890092 6023
3e02c1cc
AM		 6024 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6025 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6026
6027 /* All jumps handled here are signed, but don't use a signed limit
6028 check for 32 and 16 bit jumps as we want to allow wrap around at
6029 4G and 64k respectively. */
6030 if (size == 1)
6031 fixP->fx_signed = 1;
29b0f896 6032}
e0890092 6033
29b0f896 6034static void
e3bb37b5 6035output_interseg_jump (void)
29b0f896
AM		 6036{
6037 char *p;
6038 int size;
6039 int prefix;
6040 int code16;
252b5132 6041
29b0f896
AM		 6042 code16 = 0;
6043 if (flag_code == CODE_16BIT)
6044 code16 = CODE16;
a217f122 6045
29b0f896
AM		 6046 prefix = 0;
6047 if (i.prefix[DATA_PREFIX] != 0)
6048 {
6049 prefix = 1;
6050 i.prefixes -= 1;
6051 code16 ^= CODE16;
6052 }
6053 if (i.prefix[REX_PREFIX] != 0)
6054 {
6055 prefix++;
6056 i.prefixes -= 1;
6057 }
252b5132 6058
29b0f896
AM		 6059 size = 4;
6060 if (code16)
6061 size = 2;
252b5132 6062
29b0f896
AM		 6063 if (i.prefixes != 0 && !intel_syntax)
6064 as_warn (_("skipping prefixes on this instruction"));
252b5132 6065
29b0f896
AM		 6066 /* 1 opcode; 2 segment; offset */
6067 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6068
29b0f896
AM		 6069 if (i.prefix[DATA_PREFIX] != 0)
6070 *p++ = DATA_PREFIX_OPCODE;
252b5132 6071
29b0f896
AM		 6072 if (i.prefix[REX_PREFIX] != 0)
6073 *p++ = i.prefix[REX_PREFIX];
252b5132 6074
29b0f896
AM		 6075 *p++ = i.tm.base_opcode;
6076 if (i.op[1].imms->X_op == O_constant)
6077 {
6078 offsetT n = i.op[1].imms->X_add_number;
252b5132 6079
29b0f896
AM		 6080 if (size == 2
6081 && !fits_in_unsigned_word (n)
6082 && !fits_in_signed_word (n))
6083 {
6084 as_bad (_("16-bit jump out of range"));
6085 return;
6086 }
6087 md_number_to_chars (p, n, size);
6088 }
6089 else
6090 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6091 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6092 if (i.op[0].imms->X_op != O_constant)
6093 as_bad (_("can't handle non absolute segment in `%s'"),
6094 i.tm.name);
6095 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6096}
a217f122 6097
29b0f896 6098static void
e3bb37b5 6099output_insn (void)
29b0f896 6100{
2bbd9c25
JJ		 6101 fragS *insn_start_frag;
6102 offsetT insn_start_off;
6103
29b0f896
AM		 6104 /* Tie dwarf2 debug info to the address at the start of the insn.
6105 We can't do this after the insn has been output as the current
6106 frag may have been closed off. eg. by frag_var. */
6107 dwarf2_emit_insn (0);
6108
2bbd9c25
JJ		 6109 insn_start_frag = frag_now;
6110 insn_start_off = frag_now_fix ();
6111
29b0f896 6112 /* Output jumps. */
40fb9820 6113 if (i.tm.opcode_modifier.jump)
29b0f896 6114 output_branch ();
40fb9820
L		 6115 else if (i.tm.opcode_modifier.jumpbyte
6116 || i.tm.opcode_modifier.jumpdword)
29b0f896 6117 output_jump ();
40fb9820 6118 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6119 output_interseg_jump ();
6120 else
6121 {
6122 /* Output normal instructions here. */
6123 char *p;
6124 unsigned char *q;
47465058 6125 unsigned int j;
331d2d0d 6126 unsigned int prefix;
4dffcebc 6127
c0f3af97
L		 6128 /* Since the VEX prefix contains the implicit prefix, we don't
6129 need the explicit prefix. */
6130 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6131 {
c0f3af97 6132 switch (i.tm.opcode_length)
bc4bd9ab 6133 {
c0f3af97
L		 6134 case 3:
6135 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6136 {
c0f3af97
L		 6137 prefix = (i.tm.base_opcode >> 24) & 0xff;
6138 goto check_prefix;
6139 }
6140 break;
6141 case 2:
6142 if ((i.tm.base_opcode & 0xff0000) != 0)
6143 {
6144 prefix = (i.tm.base_opcode >> 16) & 0xff;
6145 if (i.tm.cpu_flags.bitfield.cpupadlock)
6146 {
4dffcebc 6147check_prefix:
c0f3af97 6148 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6149 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6150 != REPE_PREFIX_OPCODE))
6151 add_prefix (prefix);
6152 }
6153 else
4dffcebc
L		 6154 add_prefix (prefix);
6155 }
c0f3af97
L		 6156 break;
6157 case 1:
6158 break;
6159 default:
6160 abort ();
bc4bd9ab 6161 }
c0f3af97
L		 6162
6163 /* The prefix bytes. */
6164 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6165 if (*q)
6166 FRAG_APPEND_1_CHAR (*q);
0f10071e 6167 }
252b5132 6168
c0f3af97
L		 6169 if (i.tm.opcode_modifier.vex)
6170 {
6171 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6172 if (*q)
6173 switch (j)
6174 {
6175 case REX_PREFIX:
6176 /* REX byte is encoded in VEX prefix. */
6177 break;
6178 case SEG_PREFIX:
6179 case ADDR_PREFIX:
6180 FRAG_APPEND_1_CHAR (*q);
6181 break;
6182 default:
6183 /* There should be no other prefixes for instructions
6184 with VEX prefix. */
6185 abort ();
6186 }
6187
6188 /* Now the VEX prefix. */
6189 p = frag_more (i.vex.length);
6190 for (j = 0; j < i.vex.length; j++)
6191 p[j] = i.vex.bytes[j];
6192 }
252b5132 6193
29b0f896 6194 /* Now the opcode; be careful about word order here! */
4dffcebc 6195 if (i.tm.opcode_length == 1)
29b0f896
AM		 6196 {
6197 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6198 }
6199 else
6200 {
4dffcebc 6201 switch (i.tm.opcode_length)
331d2d0d 6202 {
4dffcebc 6203 case 3:
331d2d0d
L		 6204 p = frag_more (3);
6205 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6206 break;
6207 case 2:
6208 p = frag_more (2);
6209 break;
6210 default:
6211 abort ();
6212 break;
331d2d0d 6213 }
0f10071e 6214
29b0f896
AM		 6215 /* Put out high byte first: can't use md_number_to_chars! */
6216 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6217 *p = i.tm.base_opcode & 0xff;
6218 }
3e73aa7c 6219
29b0f896 6220 /* Now the modrm byte and sib byte (if present). */
40fb9820 6221 if (i.tm.opcode_modifier.modrm)
29b0f896 6222 {
4a3523fa
L		 6223 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6224 | i.rm.reg << 3
6225 | i.rm.mode << 6));
29b0f896
AM		 6226 /* If i.rm.regmem == ESP (4)
6227 && i.rm.mode != (Register mode)
6228 && not 16 bit
6229 ==> need second modrm byte. */
6230 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6231 && i.rm.mode != 3
40fb9820 6232 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6233 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6234 | i.sib.index << 3
6235 | i.sib.scale << 6));
29b0f896 6236 }
3e73aa7c 6237
29b0f896 6238 if (i.disp_operands)
2bbd9c25 6239 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6240
29b0f896 6241 if (i.imm_operands)
2bbd9c25 6242 output_imm (insn_start_frag, insn_start_off);
29b0f896 6243 }
252b5132 6244
29b0f896
AM		 6245#ifdef DEBUG386
6246 if (flag_debug)
6247 {
7b81dfbb 6248 pi ("" /*line*/, &i);
29b0f896
AM		 6249 }
6250#endif /* DEBUG386 */
6251}
252b5132 6252
e205caa7
L		 6253/* Return the size of the displacement operand N. */
6254
6255static int
6256disp_size (unsigned int n)
6257{
6258 int size = 4;
40fb9820
L		 6259 if (i.types[n].bitfield.disp64)
6260 size = 8;
6261 else if (i.types[n].bitfield.disp8)
6262 size = 1;
6263 else if (i.types[n].bitfield.disp16)
6264 size = 2;
e205caa7
L		 6265 return size;
6266}
6267
6268/* Return the size of the immediate operand N. */
6269
6270static int
6271imm_size (unsigned int n)
6272{
6273 int size = 4;
40fb9820
L		 6274 if (i.types[n].bitfield.imm64)
6275 size = 8;
6276 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6277 size = 1;
6278 else if (i.types[n].bitfield.imm16)
6279 size = 2;
e205caa7
L		 6280 return size;
6281}
6282
29b0f896 6283static void
64e74474 6284output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6285{
6286 char *p;
6287 unsigned int n;
252b5132 6288
29b0f896
AM		 6289 for (n = 0; n < i.operands; n++)
6290 {
40fb9820 6291 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6292 {
6293 if (i.op[n].disps->X_op == O_constant)
6294 {
e205caa7 6295 int size = disp_size (n);
29b0f896 6296 offsetT val;
252b5132 6297
29b0f896
AM		 6298 val = offset_in_range (i.op[n].disps->X_add_number,
6299 size);
6300 p = frag_more (size);
6301 md_number_to_chars (p, val, size);
6302 }
6303 else
6304 {
f86103b7 6305 enum bfd_reloc_code_real reloc_type;
e205caa7 6306 int size = disp_size (n);
40fb9820 6307 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6308 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6309
e205caa7 6310 /* We can't have 8 bit displacement here. */
9c2799c2 6311 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6312
29b0f896
AM		 6313 /* The PC relative address is computed relative
6314 to the instruction boundary, so in case immediate
6315 fields follows, we need to adjust the value. */
6316 if (pcrel && i.imm_operands)
6317 {
29b0f896 6318 unsigned int n1;
e205caa7 6319 int sz = 0;
252b5132 6320
29b0f896 6321 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6322 if (operand_type_check (i.types[n1], imm))
252b5132 6323 {
e205caa7
L		 6324 /* Only one immediate is allowed for PC
6325 relative address. */
9c2799c2 6326 gas_assert (sz == 0);
e205caa7
L		 6327 sz = imm_size (n1);
6328 i.op[n].disps->X_add_number -= sz;
252b5132 6329 }
29b0f896 6330 /* We should find the immediate. */
9c2799c2 6331 gas_assert (sz != 0);
29b0f896 6332 }
520dc8e8 6333
29b0f896 6334 p = frag_more (size);
2bbd9c25 6335 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6336 if (GOT_symbol
2bbd9c25 6337 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6338 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6339 || reloc_type == BFD_RELOC_X86_64_32S
6340 || (reloc_type == BFD_RELOC_64
6341 && object_64bit))
d6ab8113
JB		 6342 && (i.op[n].disps->X_op == O_symbol
6343 || (i.op[n].disps->X_op == O_add
6344 && ((symbol_get_value_expression
6345 (i.op[n].disps->X_op_symbol)->X_op)
6346 == O_subtract))))
6347 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6348 {
6349 offsetT add;
6350
6351 if (insn_start_frag == frag_now)
6352 add = (p - frag_now->fr_literal) - insn_start_off;
6353 else
6354 {
6355 fragS *fr;
6356
6357 add = insn_start_frag->fr_fix - insn_start_off;
6358 for (fr = insn_start_frag->fr_next;
6359 fr && fr != frag_now; fr = fr->fr_next)
6360 add += fr->fr_fix;
6361 add += p - frag_now->fr_literal;
6362 }
6363
4fa24527 6364 if (!object_64bit)
7b81dfbb
AJ		 6365 {
6366 reloc_type = BFD_RELOC_386_GOTPC;
6367 i.op[n].imms->X_add_number += add;
6368 }
6369 else if (reloc_type == BFD_RELOC_64)
6370 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6371 else
7b81dfbb
AJ		 6372 /* Don't do the adjustment for x86-64, as there
6373 the pcrel addressing is relative to the _next_
6374 insn, and that is taken care of in other code. */
d6ab8113 6375 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6376 }
062cd5e7 6377 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6378 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6379 }
6380 }
6381 }
6382}
252b5132 6383
29b0f896 6384static void
64e74474 6385output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6386{
6387 char *p;
6388 unsigned int n;
252b5132 6389
29b0f896
AM		 6390 for (n = 0; n < i.operands; n++)
6391 {
40fb9820 6392 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6393 {
6394 if (i.op[n].imms->X_op == O_constant)
6395 {
e205caa7 6396 int size = imm_size (n);
29b0f896 6397 offsetT val;
b4cac588 6398
29b0f896
AM		 6399 val = offset_in_range (i.op[n].imms->X_add_number,
6400 size);
6401 p = frag_more (size);
6402 md_number_to_chars (p, val, size);
6403 }
6404 else
6405 {
6406 /* Not absolute_section.
6407 Need a 32-bit fixup (don't support 8bit
6408 non-absolute imms). Try to support other
6409 sizes ... */
f86103b7 6410 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6411 int size = imm_size (n);
6412 int sign;
29b0f896 6413
40fb9820 6414 if (i.types[n].bitfield.imm32s
a7d61044 6415 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6416 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6417 sign = 1;
e205caa7
L		 6418 else
6419 sign = 0;
520dc8e8 6420
29b0f896
AM		 6421 p = frag_more (size);
6422 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6423
2bbd9c25
JJ		 6424 /* This is tough to explain. We end up with this one if we
6425 * have operands that look like
6426 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6427 * obtain the absolute address of the GOT, and it is strongly
6428 * preferable from a performance point of view to avoid using
6429 * a runtime relocation for this. The actual sequence of
6430 * instructions often look something like:
6431 *
6432 * call .L66
6433 * .L66:
6434 * popl %ebx
6435 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6436 *
6437 * The call and pop essentially return the absolute address
6438 * of the label .L66 and store it in %ebx. The linker itself
6439 * will ultimately change the first operand of the addl so
6440 * that %ebx points to the GOT, but to keep things simple, the
6441 * .o file must have this operand set so that it generates not
6442 * the absolute address of .L66, but the absolute address of
6443 * itself. This allows the linker itself simply treat a GOTPC
6444 * relocation as asking for a pcrel offset to the GOT to be
6445 * added in, and the addend of the relocation is stored in the
6446 * operand field for the instruction itself.
6447 *
6448 * Our job here is to fix the operand so that it would add
6449 * the correct offset so that %ebx would point to itself. The
6450 * thing that is tricky is that .-.L66 will point to the
6451 * beginning of the instruction, so we need to further modify
6452 * the operand so that it will point to itself. There are
6453 * other cases where you have something like:
6454 *
6455 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6456 *
6457 * and here no correction would be required. Internally in
6458 * the assembler we treat operands of this form as not being
6459 * pcrel since the '.' is explicitly mentioned, and I wonder
6460 * whether it would simplify matters to do it this way. Who
6461 * knows. In earlier versions of the PIC patches, the
6462 * pcrel_adjust field was used to store the correction, but
6463 * since the expression is not pcrel, I felt it would be
6464 * confusing to do it this way. */
6465
d6ab8113 6466 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6467 || reloc_type == BFD_RELOC_X86_64_32S
6468 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6469 && GOT_symbol
6470 && GOT_symbol == i.op[n].imms->X_add_symbol
6471 && (i.op[n].imms->X_op == O_symbol
6472 || (i.op[n].imms->X_op == O_add
6473 && ((symbol_get_value_expression
6474 (i.op[n].imms->X_op_symbol)->X_op)
6475 == O_subtract))))
6476 {
2bbd9c25
JJ		 6477 offsetT add;
6478
6479 if (insn_start_frag == frag_now)
6480 add = (p - frag_now->fr_literal) - insn_start_off;
6481 else
6482 {
6483 fragS *fr;
6484
6485 add = insn_start_frag->fr_fix - insn_start_off;
6486 for (fr = insn_start_frag->fr_next;
6487 fr && fr != frag_now; fr = fr->fr_next)
6488 add += fr->fr_fix;
6489 add += p - frag_now->fr_literal;
6490 }
6491
4fa24527 6492 if (!object_64bit)
d6ab8113 6493 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6494 else if (size == 4)
d6ab8113 6495 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6496 else if (size == 8)
6497 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6498 i.op[n].imms->X_add_number += add;
29b0f896 6499 }
29b0f896
AM		 6500 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6501 i.op[n].imms, 0, reloc_type);
6502 }
6503 }
6504 }
252b5132
RH		 6505}
6506\f
d182319b
JB		 6507/* x86_cons_fix_new is called via the expression parsing code when a
6508 reloc is needed. We use this hook to get the correct .got reloc. */
6509static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6510static int cons_sign = -1;
6511
6512void
e3bb37b5 6513x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6514 expressionS *exp)
d182319b
JB		 6515{
6516 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6517
6518 got_reloc = NO_RELOC;
6519
6520#ifdef TE_PE
6521 if (exp->X_op == O_secrel)
6522 {
6523 exp->X_op = O_symbol;
6524 r = BFD_RELOC_32_SECREL;
6525 }
6526#endif
6527
6528 fix_new_exp (frag, off, len, exp, 0, r);
6529}
6530
718ddfc0
JB		 6531#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6532# define lex_got(reloc, adjust, types) NULL
6533#else
f3c180ae
AM		 6534/* Parse operands of the form
6535 <symbol>@GOTOFF+<nnn>
6536 and similar .plt or .got references.
6537
6538 If we find one, set up the correct relocation in RELOC and copy the
6539 input string, minus the `@GOTOFF' into a malloc'd buffer for
6540 parsing by the calling routine. Return this buffer, and if ADJUST
6541 is non-null set it to the length of the string we removed from the
6542 input line. Otherwise return NULL. */
6543static char *
91d6fa6a 6544lex_got (enum bfd_reloc_code_real *rel,
64e74474 6545 int *adjust,
40fb9820 6546 i386_operand_type *types)
f3c180ae 6547{
7b81dfbb
AJ		 6548 /* Some of the relocations depend on the size of what field is to
6549 be relocated. But in our callers i386_immediate and i386_displacement
6550 we don't yet know the operand size (this will be set by insn
6551 matching). Hence we record the word32 relocation here,
6552 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6553 static const struct {
6554 const char *str;
cff8d58a 6555 int len;
4fa24527 6556 const enum bfd_reloc_code_real rel[2];
40fb9820 6557 const i386_operand_type types64;
f3c180ae 6558 } gotrel[] = {
cff8d58a
L		 6559 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6560 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6561 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6562 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6563 BFD_RELOC_X86_64_PLT32 },
40fb9820 6564 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6565 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6566 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6567 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6568 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6569 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6570 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6571 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6572 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6573 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6574 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6575 BFD_RELOC_X86_64_TLSGD },
40fb9820 6576 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6577 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6578 _dummy_first_bfd_reloc_code_real },
40fb9820 6579 OPERAND_TYPE_NONE },
cff8d58a
L		 6580 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6581 BFD_RELOC_X86_64_TLSLD },
40fb9820 6582 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6583 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6584 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6585 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6586 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6587 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6588 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6589 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6590 _dummy_first_bfd_reloc_code_real },
40fb9820 6591 OPERAND_TYPE_NONE },
cff8d58a
L		 6592 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6593 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6594 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6595 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6596 _dummy_first_bfd_reloc_code_real },
40fb9820 6597 OPERAND_TYPE_NONE },
cff8d58a
L		 6598 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6599 _dummy_first_bfd_reloc_code_real },
40fb9820 6600 OPERAND_TYPE_NONE },
cff8d58a
L		 6601 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6602 BFD_RELOC_X86_64_GOT32 },
40fb9820 6603 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6604 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6605 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6606 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6607 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6608 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6609 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6610 };
6611 char *cp;
6612 unsigned int j;
6613
718ddfc0
JB		 6614 if (!IS_ELF)
6615 return NULL;
6616
f3c180ae 6617 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6618 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6619 return NULL;
6620
47465058 6621 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6622 {
cff8d58a 6623 int len = gotrel[j].len;
28f81592 6624 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6625 {
4fa24527 6626 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6627 {
28f81592
AM		 6628 int first, second;
6629 char *tmpbuf, *past_reloc;
f3c180ae 6630
91d6fa6a 6631 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6632 if (adjust)
6633 *adjust = len;
f3c180ae 6634
3956db08
JB		 6635 if (types)
6636 {
6637 if (flag_code != CODE_64BIT)
40fb9820
L		 6638 {
6639 types->bitfield.imm32 = 1;
6640 types->bitfield.disp32 = 1;
6641 }
3956db08
JB		 6642 else
6643 *types = gotrel[j].types64;
6644 }
6645
f3c180ae
AM		 6646 if (GOT_symbol == NULL)
6647 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6648
28f81592 6649 /* The length of the first part of our input line. */
f3c180ae 6650 first = cp - input_line_pointer;
28f81592
AM		 6651
6652 /* The second part goes from after the reloc token until
67c11a9b 6653 (and including) an end_of_line char or comma. */
28f81592 6654 past_reloc = cp + 1 + len;
67c11a9b
AM		 6655 cp = past_reloc;
6656 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6657 ++cp;
6658 second = cp + 1 - past_reloc;
28f81592
AM		 6659
6660 /* Allocate and copy string. The trailing NUL shouldn't
6661 be necessary, but be safe. */
1e9cc1c2 6662 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6663 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6664 if (second != 0 && *past_reloc != ' ')
6665 /* Replace the relocation token with ' ', so that
6666 errors like foo@GOTOFF1 will be detected. */
6667 tmpbuf[first++] = ' ';
6668 memcpy (tmpbuf + first, past_reloc, second);
6669 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6670 return tmpbuf;
6671 }
6672
4fa24527
JB		 6673 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6674 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6675 return NULL;
6676 }
6677 }
6678
6679 /* Might be a symbol version string. Don't as_bad here. */
6680 return NULL;
6681}
4e4f7c87 6682#endif
f3c180ae 6683
f3c180ae 6684void
e3bb37b5 6685x86_cons (expressionS *exp, int size)
f3c180ae 6686{
ee86248c
JB		 6687 intel_syntax = -intel_syntax;
6688
3c7b9c2c 6689 exp->X_md = 0;
4fa24527 6690 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6691 {
6692 /* Handle @GOTOFF and the like in an expression. */
6693 char *save;
6694 char *gotfree_input_line;
4a57f2cf 6695 int adjust = 0;
f3c180ae
AM		 6696
6697 save = input_line_pointer;
3956db08 6698 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6699 if (gotfree_input_line)
6700 input_line_pointer = gotfree_input_line;
6701
6702 expression (exp);
6703
6704 if (gotfree_input_line)
6705 {
6706 /* expression () has merrily parsed up to the end of line,
6707 or a comma - in the wrong buffer. Transfer how far
6708 input_line_pointer has moved to the right buffer. */
6709 input_line_pointer = (save
6710 + (input_line_pointer - gotfree_input_line)
6711 + adjust);
6712 free (gotfree_input_line);
3992d3b7
AM		 6713 if (exp->X_op == O_constant
6714 || exp->X_op == O_absent
6715 || exp->X_op == O_illegal
0398aac5 6716 || exp->X_op == O_register
3992d3b7
AM		 6717 || exp->X_op == O_big)
6718 {
6719 char c = *input_line_pointer;
6720 *input_line_pointer = 0;
6721 as_bad (_("missing or invalid expression `%s'"), save);
6722 *input_line_pointer = c;
6723 }
f3c180ae
AM		 6724 }
6725 }
6726 else
6727 expression (exp);
ee86248c
JB		 6728
6729 intel_syntax = -intel_syntax;
6730
6731 if (intel_syntax)
6732 i386_intel_simplify (exp);
f3c180ae 6733}
f3c180ae 6734
9f32dd5b
L		 6735static void
6736signed_cons (int size)
6482c264 6737{
d182319b
JB		 6738 if (flag_code == CODE_64BIT)
6739 cons_sign = 1;
6740 cons (size);
6741 cons_sign = -1;
6482c264
NC		 6742}
6743
d182319b 6744#ifdef TE_PE
6482c264 6745static void
7016a5d5 6746pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 6747{
6748 expressionS exp;
6749
6750 do
6751 {
6752 expression (&exp);
6753 if (exp.X_op == O_symbol)
6754 exp.X_op = O_secrel;
6755
6756 emit_expr (&exp, 4);
6757 }
6758 while (*input_line_pointer++ == ',');
6759
6760 input_line_pointer--;
6761 demand_empty_rest_of_line ();
6762}
6482c264
NC		 6763#endif
6764
252b5132 6765static int
70e41ade 6766i386_immediate (char *imm_start)
252b5132
RH		 6767{
6768 char *save_input_line_pointer;
f3c180ae 6769 char *gotfree_input_line;
252b5132 6770 segT exp_seg = 0;
47926f60 6771 expressionS *exp;
40fb9820
L		 6772 i386_operand_type types;
6773
0dfbf9d7 6774 operand_type_set (&types, ~0);
252b5132
RH		 6775
6776 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6777 {
31b2323c
L		 6778 as_bad (_("at most %d immediate operands are allowed"),
6779 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6780 return 0;
6781 }
6782
6783 exp = &im_expressions[i.imm_operands++];
520dc8e8 6784 i.op[this_operand].imms = exp;
252b5132
RH		 6785
6786 if (is_space_char (*imm_start))
6787 ++imm_start;
6788
6789 save_input_line_pointer = input_line_pointer;
6790 input_line_pointer = imm_start;
6791
3956db08 6792 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6793 if (gotfree_input_line)
6794 input_line_pointer = gotfree_input_line;
252b5132
RH		 6795
6796 exp_seg = expression (exp);
6797
83183c0c 6798 SKIP_WHITESPACE ();
252b5132 6799 if (*input_line_pointer)
f3c180ae 6800 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6801
6802 input_line_pointer = save_input_line_pointer;
f3c180ae 6803 if (gotfree_input_line)
ee86248c
JB		 6804 {
6805 free (gotfree_input_line);
6806
6807 if (exp->X_op == O_constant || exp->X_op == O_register)
6808 exp->X_op = O_illegal;
6809 }
6810
6811 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6812}
252b5132 6813
ee86248c
JB		 6814static int
6815i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6816 i386_operand_type types, const char *imm_start)
6817{
6818 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6819 {
313c53d1
L		 6820 if (imm_start)
6821 as_bad (_("missing or invalid immediate expression `%s'"),
6822 imm_start);
3992d3b7 6823 return 0;
252b5132 6824 }
3e73aa7c 6825 else if (exp->X_op == O_constant)
252b5132 6826 {
47926f60 6827 /* Size it properly later. */
40fb9820 6828 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6829 /* If not 64bit, sign extend val. */
6830 if (flag_code != CODE_64BIT
4eed87de
AM		 6831 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6832 exp->X_add_number
6833 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6834 }
4c63da97 6835#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6836 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6837 && exp_seg != absolute_section
47926f60 6838 && exp_seg != text_section
24eab124
AM		 6839 && exp_seg != data_section
6840 && exp_seg != bss_section
6841 && exp_seg != undefined_section
f86103b7 6842 && !bfd_is_com_section (exp_seg))
252b5132 6843 {
d0b47220 6844 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6845 return 0;
6846 }
6847#endif
bb8f5920
L		 6848 else if (!intel_syntax && exp->X_op == O_register)
6849 {
313c53d1
L		 6850 if (imm_start)
6851 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6852 return 0;
6853 }
252b5132
RH		 6854 else
6855 {
6856 /* This is an address. The size of the address will be
24eab124 6857 determined later, depending on destination register,
3e73aa7c 6858 suffix, or the default for the section. */
40fb9820
L		 6859 i.types[this_operand].bitfield.imm8 = 1;
6860 i.types[this_operand].bitfield.imm16 = 1;
6861 i.types[this_operand].bitfield.imm32 = 1;
6862 i.types[this_operand].bitfield.imm32s = 1;
6863 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6864 i.types[this_operand] = operand_type_and (i.types[this_operand],
6865 types);
252b5132
RH		 6866 }
6867
6868 return 1;
6869}
6870
551c1ca1 6871static char *
e3bb37b5 6872i386_scale (char *scale)
252b5132 6873{
551c1ca1
AM		 6874 offsetT val;
6875 char *save = input_line_pointer;
252b5132 6876
551c1ca1
AM		 6877 input_line_pointer = scale;
6878 val = get_absolute_expression ();
6879
6880 switch (val)
252b5132 6881 {
551c1ca1 6882 case 1:
252b5132
RH		 6883 i.log2_scale_factor = 0;
6884 break;
551c1ca1 6885 case 2:
252b5132
RH		 6886 i.log2_scale_factor = 1;
6887 break;
551c1ca1 6888 case 4:
252b5132
RH		 6889 i.log2_scale_factor = 2;
6890 break;
551c1ca1 6891 case 8:
252b5132
RH		 6892 i.log2_scale_factor = 3;
6893 break;
6894 default:
a724f0f4
JB		 6895 {
6896 char sep = *input_line_pointer;
6897
6898 *input_line_pointer = '\0';
6899 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6900 scale);
6901 *input_line_pointer = sep;
6902 input_line_pointer = save;
6903 return NULL;
6904 }
252b5132 6905 }
29b0f896 6906 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6907 {
6908 as_warn (_("scale factor of %d without an index register"),
24eab124 6909 1 << i.log2_scale_factor);
252b5132 6910 i.log2_scale_factor = 0;
252b5132 6911 }
551c1ca1
AM		 6912 scale = input_line_pointer;
6913 input_line_pointer = save;
6914 return scale;
252b5132
RH		 6915}
6916
252b5132 6917static int
e3bb37b5 6918i386_displacement (char *disp_start, char *disp_end)
252b5132 6919{
29b0f896 6920 expressionS *exp;
252b5132
RH		 6921 segT exp_seg = 0;
6922 char *save_input_line_pointer;
f3c180ae 6923 char *gotfree_input_line;
40fb9820
L		 6924 int override;
6925 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6926 int ret;
252b5132 6927
31b2323c
L		 6928 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6929 {
6930 as_bad (_("at most %d displacement operands are allowed"),
6931 MAX_MEMORY_OPERANDS);
6932 return 0;
6933 }
6934
0dfbf9d7 6935 operand_type_set (&bigdisp, 0);
40fb9820
L		 6936 if ((i.types[this_operand].bitfield.jumpabsolute)
6937 || (!current_templates->start->opcode_modifier.jump
6938 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6939 {
40fb9820 6940 bigdisp.bitfield.disp32 = 1;
e05278af 6941 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6942 if (flag_code == CODE_64BIT)
6943 {
6944 if (!override)
6945 {
6946 bigdisp.bitfield.disp32s = 1;
6947 bigdisp.bitfield.disp64 = 1;
6948 }
6949 }
6950 else if ((flag_code == CODE_16BIT) ^ override)
6951 {
6952 bigdisp.bitfield.disp32 = 0;
6953 bigdisp.bitfield.disp16 = 1;
6954 }
e05278af
JB		 6955 }
6956 else
6957 {
6958 /* For PC-relative branches, the width of the displacement
6959 is dependent upon data size, not address size. */
e05278af 6960 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6961 if (flag_code == CODE_64BIT)
6962 {
6963 if (override || i.suffix == WORD_MNEM_SUFFIX)
6964 bigdisp.bitfield.disp16 = 1;
6965 else
6966 {
6967 bigdisp.bitfield.disp32 = 1;
6968 bigdisp.bitfield.disp32s = 1;
6969 }
6970 }
6971 else
e05278af
JB		 6972 {
6973 if (!override)
6974 override = (i.suffix == (flag_code != CODE_16BIT
6975 ? WORD_MNEM_SUFFIX
6976 : LONG_MNEM_SUFFIX));
40fb9820
L		 6977 bigdisp.bitfield.disp32 = 1;
6978 if ((flag_code == CODE_16BIT) ^ override)
6979 {
6980 bigdisp.bitfield.disp32 = 0;
6981 bigdisp.bitfield.disp16 = 1;
6982 }
e05278af 6983 }
e05278af 6984 }
c6fb90c8
L		 6985 i.types[this_operand] = operand_type_or (i.types[this_operand],
6986 bigdisp);
252b5132
RH		 6987
6988 exp = &disp_expressions[i.disp_operands];
520dc8e8 6989 i.op[this_operand].disps = exp;
252b5132
RH		 6990 i.disp_operands++;
6991 save_input_line_pointer = input_line_pointer;
6992 input_line_pointer = disp_start;
6993 END_STRING_AND_SAVE (disp_end);
6994
6995#ifndef GCC_ASM_O_HACK
6996#define GCC_ASM_O_HACK 0
6997#endif
6998#if GCC_ASM_O_HACK
6999 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 7000 if (i.types[this_operand].bitfield.baseIndex
24eab124 7001 && displacement_string_end[-1] == '+')
252b5132
RH		 7002 {
7003 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 7004 constraint within gcc asm statements.
7005 For instance:
7006
7007 #define _set_tssldt_desc(n,addr,limit,type) \
7008 __asm__ __volatile__ ( \
7009 "movw %w2,%0\n\t" \
7010 "movw %w1,2+%0\n\t" \
7011 "rorl $16,%1\n\t" \
7012 "movb %b1,4+%0\n\t" \
7013 "movb %4,5+%0\n\t" \
7014 "movb $0,6+%0\n\t" \
7015 "movb %h1,7+%0\n\t" \
7016 "rorl $16,%1" \
7017 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7018
7019 This works great except that the output assembler ends
7020 up looking a bit weird if it turns out that there is
7021 no offset. You end up producing code that looks like:
7022
7023 #APP
7024 movw $235,(%eax)
7025 movw %dx,2+(%eax)
7026 rorl $16,%edx
7027 movb %dl,4+(%eax)
7028 movb $137,5+(%eax)
7029 movb $0,6+(%eax)
7030 movb %dh,7+(%eax)
7031 rorl $16,%edx
7032 #NO_APP
7033
47926f60 7034 So here we provide the missing zero. */
24eab124
AM		 7035
7036 *displacement_string_end = '0';
252b5132
RH		 7037 }
7038#endif
3956db08 7039 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7040 if (gotfree_input_line)
7041 input_line_pointer = gotfree_input_line;
252b5132 7042
24eab124 7043 exp_seg = expression (exp);
252b5132 7044
636c26b0
AM		 7045 SKIP_WHITESPACE ();
7046 if (*input_line_pointer)
7047 as_bad (_("junk `%s' after expression"), input_line_pointer);
7048#if GCC_ASM_O_HACK
7049 RESTORE_END_STRING (disp_end + 1);
7050#endif
636c26b0 7051 input_line_pointer = save_input_line_pointer;
636c26b0 7052 if (gotfree_input_line)
ee86248c
JB		 7053 {
7054 free (gotfree_input_line);
7055
7056 if (exp->X_op == O_constant || exp->X_op == O_register)
7057 exp->X_op = O_illegal;
7058 }
7059
7060 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7061
7062 RESTORE_END_STRING (disp_end);
7063
7064 return ret;
7065}
7066
7067static int
7068i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7069 i386_operand_type types, const char *disp_start)
7070{
7071 i386_operand_type bigdisp;
7072 int ret = 1;
636c26b0 7073
24eab124
AM		 7074 /* We do this to make sure that the section symbol is in
7075 the symbol table. We will ultimately change the relocation
47926f60 7076 to be relative to the beginning of the section. */
1ae12ab7 7077 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7078 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7079 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7080 {
636c26b0 7081 if (exp->X_op != O_symbol)
3992d3b7 7082 goto inv_disp;
636c26b0 7083
e5cb08ac 7084 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7085 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7086 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7087 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7088 exp->X_op = O_subtract;
7089 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7090 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7091 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7092 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7093 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7094 else
29b0f896 7095 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7096 }
252b5132 7097
3992d3b7
AM		 7098 else if (exp->X_op == O_absent
7099 || exp->X_op == O_illegal
ee86248c 7100 || exp->X_op == O_big)
2daf4fd8 7101 {
3992d3b7
AM		 7102 inv_disp:
7103 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7104 disp_start);
3992d3b7 7105 ret = 0;
2daf4fd8
AM		 7106 }
7107
0e1147d9
L		 7108 else if (flag_code == CODE_64BIT
7109 && !i.prefix[ADDR_PREFIX]
7110 && exp->X_op == O_constant)
7111 {
7112 /* Since displacement is signed extended to 64bit, don't allow
7113 disp32 and turn off disp32s if they are out of range. */
7114 i.types[this_operand].bitfield.disp32 = 0;
7115 if (!fits_in_signed_long (exp->X_add_number))
7116 {
7117 i.types[this_operand].bitfield.disp32s = 0;
7118 if (i.types[this_operand].bitfield.baseindex)
7119 {
7120 as_bad (_("0x%lx out range of signed 32bit displacement"),
7121 (long) exp->X_add_number);
7122 ret = 0;
7123 }
7124 }
7125 }
7126
4c63da97 7127#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7128 else if (exp->X_op != O_constant
7129 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7130 && exp_seg != absolute_section
7131 && exp_seg != text_section
7132 && exp_seg != data_section
7133 && exp_seg != bss_section
7134 && exp_seg != undefined_section
7135 && !bfd_is_com_section (exp_seg))
24eab124 7136 {
d0b47220 7137 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7138 ret = 0;
24eab124 7139 }
252b5132 7140#endif
3956db08 7141
40fb9820
L		 7142 /* Check if this is a displacement only operand. */
7143 bigdisp = i.types[this_operand];
7144 bigdisp.bitfield.disp8 = 0;
7145 bigdisp.bitfield.disp16 = 0;
7146 bigdisp.bitfield.disp32 = 0;
7147 bigdisp.bitfield.disp32s = 0;
7148 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7149 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7150 i.types[this_operand] = operand_type_and (i.types[this_operand],
7151 types);
3956db08 7152
3992d3b7 7153 return ret;
252b5132
RH		 7154}
7155
eecb386c 7156/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7157 Return 1 on success, 0 on a failure. */
7158
252b5132 7159static int
e3bb37b5 7160i386_index_check (const char *operand_string)
252b5132 7161{
3e73aa7c 7162 int ok;
fc0763e6 7163 const char *kind = "base/index";
24eab124 7164#if INFER_ADDR_PREFIX
eecb386c
AM		 7165 int fudged = 0;
7166
24eab124
AM		 7167 tryprefix:
7168#endif
3e73aa7c 7169 ok = 1;
fc0763e6
JB		 7170 if (current_templates->start->opcode_modifier.isstring
7171 && !current_templates->start->opcode_modifier.immext
7172 && (current_templates->end[-1].opcode_modifier.isstring
7173 || i.mem_operands))
7174 {
7175 /* Memory operands of string insns are special in that they only allow
7176 a single register (rDI, rSI, or rBX) as their memory address. */
7177 unsigned int expected;
7178
7179 kind = "string address";
7180
7181 if (current_templates->start->opcode_modifier.w)
7182 {
7183 i386_operand_type type = current_templates->end[-1].operand_types[0];
7184
7185 if (!type.bitfield.baseindex
7186 || ((!i.mem_operands != !intel_syntax)
7187 && current_templates->end[-1].operand_types[1]
7188 .bitfield.baseindex))
7189 type = current_templates->end[-1].operand_types[1];
7190 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7191 }
7192 else
7193 expected = 3 /* rBX */;
7194
7195 if (!i.base_reg || i.index_reg
7196 || operand_type_check (i.types[this_operand], disp))
7197 ok = -1;
7198 else if (!(flag_code == CODE_64BIT
7199 ? i.prefix[ADDR_PREFIX]
7200 ? i.base_reg->reg_type.bitfield.reg32
7201 : i.base_reg->reg_type.bitfield.reg64
7202 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7203 ? i.base_reg->reg_type.bitfield.reg32
7204 : i.base_reg->reg_type.bitfield.reg16))
7205 ok = 0;
7206 else if (i.base_reg->reg_num != expected)
7207 ok = -1;
7208
7209 if (ok < 0)
7210 {
7211 unsigned int j;
7212
7213 for (j = 0; j < i386_regtab_size; ++j)
7214 if ((flag_code == CODE_64BIT
7215 ? i.prefix[ADDR_PREFIX]
7216 ? i386_regtab[j].reg_type.bitfield.reg32
7217 : i386_regtab[j].reg_type.bitfield.reg64
7218 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7219 ? i386_regtab[j].reg_type.bitfield.reg32
7220 : i386_regtab[j].reg_type.bitfield.reg16)
7221 && i386_regtab[j].reg_num == expected)
7222 break;
9c2799c2 7223 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7224 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7225 operand_string,
7226 intel_syntax ? '[' : '(',
7227 register_prefix,
7228 i386_regtab[j].reg_name,
7229 intel_syntax ? ']' : ')');
7230 ok = 1;
7231 }
7232 }
7233 else if (flag_code == CODE_64BIT)
64e74474 7234 {
64e74474 7235 if ((i.base_reg
40fb9820
L		 7236 && ((i.prefix[ADDR_PREFIX] == 0
7237 && !i.base_reg->reg_type.bitfield.reg64)
7238 || (i.prefix[ADDR_PREFIX]
7239 && !i.base_reg->reg_type.bitfield.reg32))
7240 && (i.index_reg
9a04903e
JB		 7241 || i.base_reg->reg_num !=
7242 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7243 || (i.index_reg
6c30d220
L		 7244 && !(i.index_reg->reg_type.bitfield.regxmm
7245 || i.index_reg->reg_type.bitfield.regymm)
40fb9820
L		 7246 && (!i.index_reg->reg_type.bitfield.baseindex
7247 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7248 && i.index_reg->reg_num != RegRiz
7249 && !i.index_reg->reg_type.bitfield.reg64
7250 )
40fb9820 7251 || (i.prefix[ADDR_PREFIX]
db51cc60 7252 && i.index_reg->reg_num != RegEiz
40fb9820 7253 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7254 ok = 0;
3e73aa7c
JH		 7255 }
7256 else
7257 {
7258 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7259 {
7260 /* 16bit checks. */
7261 if ((i.base_reg
40fb9820
L		 7262 && (!i.base_reg->reg_type.bitfield.reg16
7263 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7264 || (i.index_reg
40fb9820
L		 7265 && (!i.index_reg->reg_type.bitfield.reg16
7266 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7267 || !(i.base_reg
7268 && i.base_reg->reg_num < 6
7269 && i.index_reg->reg_num >= 6
7270 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7271 ok = 0;
7272 }
7273 else
e5cb08ac 7274 {
3e73aa7c
JH		 7275 /* 32bit checks. */
7276 if ((i.base_reg
40fb9820 7277 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7278 || (i.index_reg
6c30d220
L		 7279 && !i.index_reg->reg_type.bitfield.regxmm
7280 && !i.index_reg->reg_type.bitfield.regymm
db51cc60
L		 7281 && ((!i.index_reg->reg_type.bitfield.reg32
7282 && i.index_reg->reg_num != RegEiz)
40fb9820 7283 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7284 ok = 0;
3e73aa7c
JH		 7285 }
7286 }
7287 if (!ok)
24eab124
AM		 7288 {
7289#if INFER_ADDR_PREFIX
fc0763e6 7290 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7291 {
7292 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7293 i.prefixes += 1;
b23bac36
AM		 7294 /* Change the size of any displacement too. At most one of
7295 Disp16 or Disp32 is set.
7296 FIXME. There doesn't seem to be any real need for separate
7297 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7298 Removing them would probably clean up the code quite a lot. */
4eed87de 7299 if (flag_code != CODE_64BIT
40fb9820
L		 7300 && (i.types[this_operand].bitfield.disp16
7301 || i.types[this_operand].bitfield.disp32))
7302 i.types[this_operand]
c6fb90c8 7303 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7304 fudged = 1;
24eab124
AM		 7305 goto tryprefix;
7306 }
eecb386c 7307 if (fudged)
fc0763e6
JB		 7308 as_bad (_("`%s' is not a valid %s expression"),
7309 operand_string,
7310 kind);
eecb386c 7311 else
c388dee8 7312#endif
fc0763e6 7313 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7314 operand_string,
fc0763e6
JB		 7315 flag_code_names[i.prefix[ADDR_PREFIX]
7316 ? flag_code == CODE_32BIT
7317 ? CODE_16BIT
7318 : CODE_32BIT
7319 : flag_code],
7320 kind);
24eab124 7321 }
20f0a1fc 7322 return ok;
24eab124 7323}
252b5132 7324
fc0763e6 7325/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7326 on error. */
252b5132 7327
252b5132 7328static int
a7619375 7329i386_att_operand (char *operand_string)
252b5132 7330{
af6bdddf
AM		 7331 const reg_entry *r;
7332 char *end_op;
24eab124 7333 char *op_string = operand_string;
252b5132 7334
24eab124 7335 if (is_space_char (*op_string))
252b5132
RH		 7336 ++op_string;
7337
24eab124 7338 /* We check for an absolute prefix (differentiating,
47926f60 7339 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7340 if (*op_string == ABSOLUTE_PREFIX)
7341 {
7342 ++op_string;
7343 if (is_space_char (*op_string))
7344 ++op_string;
40fb9820 7345 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7346 }
252b5132 7347
47926f60 7348 /* Check if operand is a register. */
4d1bb795 7349 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7350 {
40fb9820
L		 7351 i386_operand_type temp;
7352
24eab124
AM		 7353 /* Check for a segment override by searching for ':' after a
7354 segment register. */
7355 op_string = end_op;
7356 if (is_space_char (*op_string))
7357 ++op_string;
40fb9820
L		 7358 if (*op_string == ':'
7359 && (r->reg_type.bitfield.sreg2
7360 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7361 {
7362 switch (r->reg_num)
7363 {
7364 case 0:
7365 i.seg[i.mem_operands] = &es;
7366 break;
7367 case 1:
7368 i.seg[i.mem_operands] = &cs;
7369 break;
7370 case 2:
7371 i.seg[i.mem_operands] = &ss;
7372 break;
7373 case 3:
7374 i.seg[i.mem_operands] = &ds;
7375 break;
7376 case 4:
7377 i.seg[i.mem_operands] = &fs;
7378 break;
7379 case 5:
7380 i.seg[i.mem_operands] = &gs;
7381 break;
7382 }
252b5132 7383
24eab124 7384 /* Skip the ':' and whitespace. */
252b5132
RH		 7385 ++op_string;
7386 if (is_space_char (*op_string))
24eab124 7387 ++op_string;
252b5132 7388
24eab124
AM		 7389 if (!is_digit_char (*op_string)
7390 && !is_identifier_char (*op_string)
7391 && *op_string != '('
7392 && *op_string != ABSOLUTE_PREFIX)
7393 {
7394 as_bad (_("bad memory operand `%s'"), op_string);
7395 return 0;
7396 }
47926f60 7397 /* Handle case of %es:*foo. */
24eab124
AM		 7398 if (*op_string == ABSOLUTE_PREFIX)
7399 {
7400 ++op_string;
7401 if (is_space_char (*op_string))
7402 ++op_string;
40fb9820 7403 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7404 }
7405 goto do_memory_reference;
7406 }
7407 if (*op_string)
7408 {
d0b47220 7409 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7410 return 0;
7411 }
40fb9820
L		 7412 temp = r->reg_type;
7413 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7414 i.types[this_operand] = operand_type_or (i.types[this_operand],
7415 temp);
7d5e4556 7416 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7417 i.op[this_operand].regs = r;
24eab124
AM		 7418 i.reg_operands++;
7419 }
af6bdddf
AM		 7420 else if (*op_string == REGISTER_PREFIX)
7421 {
7422 as_bad (_("bad register name `%s'"), op_string);
7423 return 0;
7424 }
24eab124 7425 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7426 {
24eab124 7427 ++op_string;
40fb9820 7428 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7429 {
d0b47220 7430 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7431 return 0;
7432 }
7433 if (!i386_immediate (op_string))
7434 return 0;
7435 }
7436 else if (is_digit_char (*op_string)
7437 || is_identifier_char (*op_string)
e5cb08ac 7438 || *op_string == '(')
24eab124 7439 {
47926f60 7440 /* This is a memory reference of some sort. */
af6bdddf 7441 char *base_string;
252b5132 7442
47926f60 7443 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7444 char *displacement_string_start;
7445 char *displacement_string_end;
252b5132 7446
24eab124 7447 do_memory_reference:
24eab124 7448 if ((i.mem_operands == 1
40fb9820 7449 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7450 || i.mem_operands == 2)
7451 {
7452 as_bad (_("too many memory references for `%s'"),
7453 current_templates->start->name);
7454 return 0;
7455 }
252b5132 7456
24eab124
AM		 7457 /* Check for base index form. We detect the base index form by
7458 looking for an ')' at the end of the operand, searching
7459 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7460 after the '('. */
af6bdddf 7461 base_string = op_string + strlen (op_string);
c3332e24 7462
af6bdddf
AM		 7463 --base_string;
7464 if (is_space_char (*base_string))
7465 --base_string;
252b5132 7466
47926f60 7467 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7468 displacement_string_start = op_string;
7469 displacement_string_end = base_string + 1;
252b5132 7470
24eab124
AM		 7471 if (*base_string == ')')
7472 {
af6bdddf 7473 char *temp_string;
24eab124
AM		 7474 unsigned int parens_balanced = 1;
7475 /* We've already checked that the number of left & right ()'s are
47926f60 7476 equal, so this loop will not be infinite. */
24eab124
AM		 7477 do
7478 {
7479 base_string--;
7480 if (*base_string == ')')
7481 parens_balanced++;
7482 if (*base_string == '(')
7483 parens_balanced--;
7484 }
7485 while (parens_balanced);
c3332e24 7486
af6bdddf 7487 temp_string = base_string;
c3332e24 7488
24eab124 7489 /* Skip past '(' and whitespace. */
252b5132
RH		 7490 ++base_string;
7491 if (is_space_char (*base_string))
24eab124 7492 ++base_string;
252b5132 7493
af6bdddf 7494 if (*base_string == ','
4eed87de
AM		 7495 || ((i.base_reg = parse_register (base_string, &end_op))
7496 != NULL))
252b5132 7497 {
af6bdddf 7498 displacement_string_end = temp_string;
252b5132 7499
40fb9820 7500 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7501
af6bdddf 7502 if (i.base_reg)
24eab124 7503 {
24eab124
AM		 7504 base_string = end_op;
7505 if (is_space_char (*base_string))
7506 ++base_string;
af6bdddf
AM		 7507 }
7508
7509 /* There may be an index reg or scale factor here. */
7510 if (*base_string == ',')
7511 {
7512 ++base_string;
7513 if (is_space_char (*base_string))
7514 ++base_string;
7515
4eed87de
AM		 7516 if ((i.index_reg = parse_register (base_string, &end_op))
7517 != NULL)
24eab124 7518 {
af6bdddf 7519 base_string = end_op;
24eab124
AM		 7520 if (is_space_char (*base_string))
7521 ++base_string;
af6bdddf
AM		 7522 if (*base_string == ',')
7523 {
7524 ++base_string;
7525 if (is_space_char (*base_string))
7526 ++base_string;
7527 }
e5cb08ac 7528 else if (*base_string != ')')
af6bdddf 7529 {
4eed87de
AM		 7530 as_bad (_("expecting `,' or `)' "
7531 "after index register in `%s'"),
af6bdddf
AM		 7532 operand_string);
7533 return 0;
7534 }
24eab124 7535 }
af6bdddf 7536 else if (*base_string == REGISTER_PREFIX)
24eab124 7537 {
af6bdddf 7538 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7539 return 0;
7540 }
252b5132 7541
47926f60 7542 /* Check for scale factor. */
551c1ca1 7543 if (*base_string != ')')
af6bdddf 7544 {
551c1ca1
AM		 7545 char *end_scale = i386_scale (base_string);
7546
7547 if (!end_scale)
af6bdddf 7548 return 0;
24eab124 7549
551c1ca1 7550 base_string = end_scale;
af6bdddf
AM		 7551 if (is_space_char (*base_string))
7552 ++base_string;
7553 if (*base_string != ')')
7554 {
4eed87de
AM		 7555 as_bad (_("expecting `)' "
7556 "after scale factor in `%s'"),
af6bdddf
AM		 7557 operand_string);
7558 return 0;
7559 }
7560 }
7561 else if (!i.index_reg)
24eab124 7562 {
4eed87de
AM		 7563 as_bad (_("expecting index register or scale factor "
7564 "after `,'; got '%c'"),
af6bdddf 7565 *base_string);
24eab124
AM		 7566 return 0;
7567 }
7568 }
af6bdddf 7569 else if (*base_string != ')')
24eab124 7570 {
4eed87de
AM		 7571 as_bad (_("expecting `,' or `)' "
7572 "after base register in `%s'"),
af6bdddf 7573 operand_string);
24eab124
AM		 7574 return 0;
7575 }
c3332e24 7576 }
af6bdddf 7577 else if (*base_string == REGISTER_PREFIX)
c3332e24 7578 {
af6bdddf 7579 as_bad (_("bad register name `%s'"), base_string);
24eab124 7580 return 0;
c3332e24 7581 }
24eab124
AM		 7582 }
7583
7584 /* If there's an expression beginning the operand, parse it,
7585 assuming displacement_string_start and
7586 displacement_string_end are meaningful. */
7587 if (displacement_string_start != displacement_string_end)
7588 {
7589 if (!i386_displacement (displacement_string_start,
7590 displacement_string_end))
7591 return 0;
7592 }
7593
7594 /* Special case for (%dx) while doing input/output op. */
7595 if (i.base_reg
0dfbf9d7
L		 7596 && operand_type_equal (&i.base_reg->reg_type,
7597 &reg16_inoutportreg)
24eab124
AM		 7598 && i.index_reg == 0
7599 && i.log2_scale_factor == 0
7600 && i.seg[i.mem_operands] == 0
40fb9820 7601 && !operand_type_check (i.types[this_operand], disp))
24eab124 7602 {
65da13b5 7603 i.types[this_operand] = inoutportreg;
24eab124
AM		 7604 return 1;
7605 }
7606
eecb386c
AM		 7607 if (i386_index_check (operand_string) == 0)
7608 return 0;
5c07affc 7609 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7610 i.mem_operands++;
7611 }
7612 else
ce8a8b2f
AM		 7613 {
7614 /* It's not a memory operand; argh! */
24eab124
AM		 7615 as_bad (_("invalid char %s beginning operand %d `%s'"),
7616 output_invalid (*op_string),
7617 this_operand + 1,
7618 op_string);
7619 return 0;
7620 }
47926f60 7621 return 1; /* Normal return. */
252b5132
RH		 7622}
7623\f
ee7fcc42
AM		 7624/* md_estimate_size_before_relax()
7625
7626 Called just before relax() for rs_machine_dependent frags. The x86
7627 assembler uses these frags to handle variable size jump
7628 instructions.
7629
7630 Any symbol that is now undefined will not become defined.
7631 Return the correct fr_subtype in the frag.
7632 Return the initial "guess for variable size of frag" to caller.
7633 The guess is actually the growth beyond the fixed part. Whatever
7634 we do to grow the fixed or variable part contributes to our
7635 returned value. */
7636
252b5132 7637int
7016a5d5 7638md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7639{
252b5132 7640 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7641 check for un-relaxable symbols. On an ELF system, we can't relax
7642 an externally visible symbol, because it may be overridden by a
7643 shared library. */
7644 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7645#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7646 || (IS_ELF
31312f95 7647 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7648 || S_IS_WEAK (fragP->fr_symbol)
7649 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7650 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7651#endif
7652#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7653 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7654 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7655#endif
7656 )
252b5132 7657 {
b98ef147
AM		 7658 /* Symbol is undefined in this segment, or we need to keep a
7659 reloc so that weak symbols can be overridden. */
7660 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7661 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7662 unsigned char *opcode;
7663 int old_fr_fix;
f6af82bd 7664
ee7fcc42 7665 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7666 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7667 else if (size == 2)
f6af82bd
AM		 7668 reloc_type = BFD_RELOC_16_PCREL;
7669 else
7670 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7671
ee7fcc42
AM		 7672 old_fr_fix = fragP->fr_fix;
7673 opcode = (unsigned char *) fragP->fr_opcode;
7674
fddf5b5b 7675 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7676 {
fddf5b5b
AM		 7677 case UNCOND_JUMP:
7678 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7679 opcode[0] = 0xe9;
252b5132 7680 fragP->fr_fix += size;
062cd5e7
AS		 7681 fix_new (fragP, old_fr_fix, size,
7682 fragP->fr_symbol,
7683 fragP->fr_offset, 1,
7684 reloc_type);
252b5132
RH		 7685 break;
7686
fddf5b5b 7687 case COND_JUMP86:
412167cb
AM		 7688 if (size == 2
7689 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7690 {
7691 /* Negate the condition, and branch past an
7692 unconditional jump. */
7693 opcode[0] ^= 1;
7694 opcode[1] = 3;
7695 /* Insert an unconditional jump. */
7696 opcode[2] = 0xe9;
7697 /* We added two extra opcode bytes, and have a two byte
7698 offset. */
7699 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7700 fix_new (fragP, old_fr_fix + 2, 2,
7701 fragP->fr_symbol,
7702 fragP->fr_offset, 1,
7703 reloc_type);
fddf5b5b
AM		 7704 break;
7705 }
7706 /* Fall through. */
7707
7708 case COND_JUMP:
412167cb
AM		 7709 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7710 {
3e02c1cc
AM		 7711 fixS *fixP;
7712
412167cb 7713 fragP->fr_fix += 1;
3e02c1cc
AM		 7714 fixP = fix_new (fragP, old_fr_fix, 1,
7715 fragP->fr_symbol,
7716 fragP->fr_offset, 1,
7717 BFD_RELOC_8_PCREL);
7718 fixP->fx_signed = 1;
412167cb
AM		 7719 break;
7720 }
93c2a809 7721
24eab124 7722 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7723 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7724 opcode[1] = opcode[0] + 0x10;
f6af82bd 7725 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7726 /* We've added an opcode byte. */
7727 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7728 fix_new (fragP, old_fr_fix + 1, size,
7729 fragP->fr_symbol,
7730 fragP->fr_offset, 1,
7731 reloc_type);
252b5132 7732 break;
fddf5b5b
AM		 7733
7734 default:
7735 BAD_CASE (fragP->fr_subtype);
7736 break;
252b5132
RH		 7737 }
7738 frag_wane (fragP);
ee7fcc42 7739 return fragP->fr_fix - old_fr_fix;
252b5132 7740 }
93c2a809 7741
93c2a809
AM		 7742 /* Guess size depending on current relax state. Initially the relax
7743 state will correspond to a short jump and we return 1, because
7744 the variable part of the frag (the branch offset) is one byte
7745 long. However, we can relax a section more than once and in that
7746 case we must either set fr_subtype back to the unrelaxed state,
7747 or return the value for the appropriate branch. */
7748 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7749}
7750
47926f60
KH		 7751/* Called after relax() is finished.
7752
7753 In: Address of frag.
7754 fr_type == rs_machine_dependent.
7755 fr_subtype is what the address relaxed to.
7756
7757 Out: Any fixSs and constants are set up.
7758 Caller will turn frag into a ".space 0". */
7759
252b5132 7760void
7016a5d5
TG		 7761md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
7762 fragS *fragP)
252b5132 7763{
29b0f896 7764 unsigned char *opcode;
252b5132 7765 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7766 offsetT target_address;
7767 offsetT opcode_address;
252b5132 7768 unsigned int extension = 0;
847f7ad4 7769 offsetT displacement_from_opcode_start;
252b5132
RH		 7770
7771 opcode = (unsigned char *) fragP->fr_opcode;
7772
47926f60 7773 /* Address we want to reach in file space. */
252b5132 7774 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7775
47926f60 7776 /* Address opcode resides at in file space. */
252b5132
RH		 7777 opcode_address = fragP->fr_address + fragP->fr_fix;
7778
47926f60 7779 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7780 displacement_from_opcode_start = target_address - opcode_address;
7781
fddf5b5b 7782 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7783 {
47926f60
KH		 7784 /* Don't have to change opcode. */
7785 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7786 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7787 }
7788 else
7789 {
7790 if (no_cond_jump_promotion
7791 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7792 as_warn_where (fragP->fr_file, fragP->fr_line,
7793 _("long jump required"));
252b5132 7794
fddf5b5b
AM		 7795 switch (fragP->fr_subtype)
7796 {
7797 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7798 extension = 4; /* 1 opcode + 4 displacement */
7799 opcode[0] = 0xe9;
7800 where_to_put_displacement = &opcode[1];
7801 break;
252b5132 7802
fddf5b5b
AM		 7803 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7804 extension = 2; /* 1 opcode + 2 displacement */
7805 opcode[0] = 0xe9;
7806 where_to_put_displacement = &opcode[1];
7807 break;
252b5132 7808
fddf5b5b
AM		 7809 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7810 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7811 extension = 5; /* 2 opcode + 4 displacement */
7812 opcode[1] = opcode[0] + 0x10;
7813 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7814 where_to_put_displacement = &opcode[2];
7815 break;
252b5132 7816
fddf5b5b
AM		 7817 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7818 extension = 3; /* 2 opcode + 2 displacement */
7819 opcode[1] = opcode[0] + 0x10;
7820 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7821 where_to_put_displacement = &opcode[2];
7822 break;
252b5132 7823
fddf5b5b
AM		 7824 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7825 extension = 4;
7826 opcode[0] ^= 1;
7827 opcode[1] = 3;
7828 opcode[2] = 0xe9;
7829 where_to_put_displacement = &opcode[3];
7830 break;
7831
7832 default:
7833 BAD_CASE (fragP->fr_subtype);
7834 break;
7835 }
252b5132 7836 }
fddf5b5b 7837
7b81dfbb
AJ		 7838 /* If size if less then four we are sure that the operand fits,
7839 but if it's 4, then it could be that the displacement is larger
7840 then -/+ 2GB. */
7841 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7842 && object_64bit
7843 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7844 + ((addressT) 1 << 31))
7845 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7846 {
7847 as_bad_where (fragP->fr_file, fragP->fr_line,
7848 _("jump target out of range"));
7849 /* Make us emit 0. */
7850 displacement_from_opcode_start = extension;
7851 }
47926f60 7852 /* Now put displacement after opcode. */
252b5132
RH		 7853 md_number_to_chars ((char *) where_to_put_displacement,
7854 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7855 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7856 fragP->fr_fix += extension;
7857}
7858\f
7016a5d5 7859/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 7860 by our caller that we have all the info we need to fix it up.
7861
7016a5d5
TG		 7862 Parameter valP is the pointer to the value of the bits.
7863
252b5132
RH		 7864 On the 386, immediates, displacements, and data pointers are all in
7865 the same (little-endian) format, so we don't need to care about which
7866 we are handling. */
7867
94f592af 7868void
7016a5d5 7869md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 7870{
94f592af 7871 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7872 valueT value = *valP;
252b5132 7873
f86103b7 7874#if !defined (TE_Mach)
93382f6d
AM		 7875 if (fixP->fx_pcrel)
7876 {
7877 switch (fixP->fx_r_type)
7878 {
5865bb77
ILT		 7879 default:
7880 break;
7881
d6ab8113
JB		 7882 case BFD_RELOC_64:
7883 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7884 break;
93382f6d 7885 case BFD_RELOC_32:
ae8887b5 7886 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7887 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7888 break;
7889 case BFD_RELOC_16:
7890 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7891 break;
7892 case BFD_RELOC_8:
7893 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7894 break;
7895 }
7896 }
252b5132 7897
a161fe53 7898 if (fixP->fx_addsy != NULL
31312f95 7899 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7900 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7901 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7902 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7903 && !use_rela_relocations)
252b5132 7904 {
31312f95
AM		 7905 /* This is a hack. There should be a better way to handle this.
7906 This covers for the fact that bfd_install_relocation will
7907 subtract the current location (for partial_inplace, PC relative
7908 relocations); see more below. */
252b5132 7909#ifndef OBJ_AOUT
718ddfc0 7910 if (IS_ELF
252b5132
RH		 7911#ifdef TE_PE
7912 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7913#endif
7914 )
7915 value += fixP->fx_where + fixP->fx_frag->fr_address;
7916#endif
7917#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7918 if (IS_ELF)
252b5132 7919 {
6539b54b 7920 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7921
6539b54b 7922 if ((sym_seg == seg
2f66722d 7923 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7924 && sym_seg != absolute_section))
af65af87 7925 && !generic_force_reloc (fixP))
2f66722d
AM		 7926 {
7927 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7928 bfd_install_relocation subtracts them out again. I think
7929 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7930 it. FIXME. */
7931 value += fixP->fx_where + fixP->fx_frag->fr_address;
7932 }
252b5132
RH		 7933 }
7934#endif
7935#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7936 /* For some reason, the PE format does not store a
7937 section address offset for a PC relative symbol. */
7938 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7939 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7940 value += md_pcrel_from (fixP);
7941#endif
7942 }
fbeb56a4
DK		 7943#if defined (OBJ_COFF) && defined (TE_PE)
7944 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7945 {
7946 value -= S_GET_VALUE (fixP->fx_addsy);
7947 }
7948#endif
252b5132
RH		 7949
7950 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7951 and we must not disappoint it. */
252b5132 7952#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7953 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7954 switch (fixP->fx_r_type)
7955 {
7956 case BFD_RELOC_386_PLT32:
3e73aa7c 7957 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7958 /* Make the jump instruction point to the address of the operand. At
7959 runtime we merely add the offset to the actual PLT entry. */
7960 value = -4;
7961 break;
31312f95 7962
13ae64f3
JJ		 7963 case BFD_RELOC_386_TLS_GD:
7964 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7965 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7966 case BFD_RELOC_386_TLS_IE:
7967 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7968 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7969 case BFD_RELOC_X86_64_TLSGD:
7970 case BFD_RELOC_X86_64_TLSLD:
7971 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7972 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7973 value = 0; /* Fully resolved at runtime. No addend. */
7974 /* Fallthrough */
7975 case BFD_RELOC_386_TLS_LE:
7976 case BFD_RELOC_386_TLS_LDO_32:
7977 case BFD_RELOC_386_TLS_LE_32:
7978 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7979 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7980 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7981 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7982 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7983 break;
7984
67a4f2b7
AO		 7985 case BFD_RELOC_386_TLS_DESC_CALL:
7986 case BFD_RELOC_X86_64_TLSDESC_CALL:
7987 value = 0; /* Fully resolved at runtime. No addend. */
7988 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7989 fixP->fx_done = 0;
7990 return;
7991
00f7efb6
JJ		 7992 case BFD_RELOC_386_GOT32:
7993 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7994 value = 0; /* Fully resolved at runtime. No addend. */
7995 break;
47926f60
KH		 7996
7997 case BFD_RELOC_VTABLE_INHERIT:
7998 case BFD_RELOC_VTABLE_ENTRY:
7999 fixP->fx_done = 0;
94f592af 8000 return;
47926f60
KH		 8001
8002 default:
8003 break;
8004 }
8005#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 8006 *valP = value;
f86103b7 8007#endif /* !defined (TE_Mach) */
3e73aa7c 8008
3e73aa7c 8009 /* Are we finished with this relocation now? */
c6682705 8010 if (fixP->fx_addsy == NULL)
3e73aa7c 8011 fixP->fx_done = 1;
fbeb56a4
DK		 8012#if defined (OBJ_COFF) && defined (TE_PE)
8013 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8014 {
8015 fixP->fx_done = 0;
8016 /* Remember value for tc_gen_reloc. */
8017 fixP->fx_addnumber = value;
8018 /* Clear out the frag for now. */
8019 value = 0;
8020 }
8021#endif
3e73aa7c
JH		 8022 else if (use_rela_relocations)
8023 {
8024 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8025 /* Remember value for tc_gen_reloc. */
8026 fixP->fx_addnumber = value;
3e73aa7c
JH		 8027 value = 0;
8028 }
f86103b7 8029
94f592af 8030 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8031}
252b5132 8032\f
252b5132 8033char *
499ac353 8034md_atof (int type, char *litP, int *sizeP)
252b5132 8035{
499ac353
NC		 8036 /* This outputs the LITTLENUMs in REVERSE order;
8037 in accord with the bigendian 386. */
8038 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8039}
8040\f
2d545b82 8041static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8042
252b5132 8043static char *
e3bb37b5 8044output_invalid (int c)
252b5132 8045{
3882b010 8046 if (ISPRINT (c))
f9f21a03
L		 8047 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8048 "'%c'", c);
252b5132 8049 else
f9f21a03 8050 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8051 "(0x%x)", (unsigned char) c);
252b5132
RH		 8052 return output_invalid_buf;
8053}
8054
af6bdddf 8055/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8056
8057static const reg_entry *
4d1bb795 8058parse_real_register (char *reg_string, char **end_op)
252b5132 8059{
af6bdddf
AM		 8060 char *s = reg_string;
8061 char *p;
252b5132
RH		 8062 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8063 const reg_entry *r;
8064
8065 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8066 if (*s == REGISTER_PREFIX)
8067 ++s;
8068
8069 if (is_space_char (*s))
8070 ++s;
8071
8072 p = reg_name_given;
af6bdddf 8073 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8074 {
8075 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8076 return (const reg_entry *) NULL;
8077 s++;
252b5132
RH		 8078 }
8079
6588847e
DN		 8080 /* For naked regs, make sure that we are not dealing with an identifier.
8081 This prevents confusing an identifier like `eax_var' with register
8082 `eax'. */
8083 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8084 return (const reg_entry *) NULL;
8085
af6bdddf 8086 *end_op = s;
252b5132
RH		 8087
8088 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8089
5f47d35b 8090 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8091 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8092 {
5f47d35b
AM		 8093 if (is_space_char (*s))
8094 ++s;
8095 if (*s == '(')
8096 {
af6bdddf 8097 ++s;
5f47d35b
AM		 8098 if (is_space_char (*s))
8099 ++s;
8100 if (*s >= '0' && *s <= '7')
8101 {
db557034 8102 int fpr = *s - '0';
af6bdddf 8103 ++s;
5f47d35b
AM		 8104 if (is_space_char (*s))
8105 ++s;
8106 if (*s == ')')
8107 {
8108 *end_op = s + 1;
1e9cc1c2 8109 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8110 know (r);
8111 return r + fpr;
5f47d35b 8112 }
5f47d35b 8113 }
47926f60 8114 /* We have "%st(" then garbage. */
5f47d35b
AM		 8115 return (const reg_entry *) NULL;
8116 }
8117 }
8118
a60de03c
JB		 8119 if (r == NULL || allow_pseudo_reg)
8120 return r;
8121
0dfbf9d7 8122 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8123 return (const reg_entry *) NULL;
8124
192dc9c6
JB		 8125 if ((r->reg_type.bitfield.reg32
8126 || r->reg_type.bitfield.sreg3
8127 || r->reg_type.bitfield.control
8128 || r->reg_type.bitfield.debug
8129 || r->reg_type.bitfield.test)
8130 && !cpu_arch_flags.bitfield.cpui386)
8131 return (const reg_entry *) NULL;
8132
309d3373
JB		 8133 if (r->reg_type.bitfield.floatreg
8134 && !cpu_arch_flags.bitfield.cpu8087
8135 && !cpu_arch_flags.bitfield.cpu287
8136 && !cpu_arch_flags.bitfield.cpu387)
8137 return (const reg_entry *) NULL;
8138
192dc9c6
JB		 8139 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8140 return (const reg_entry *) NULL;
8141
8142 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8143 return (const reg_entry *) NULL;
8144
40f12533
L		 8145 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8146 return (const reg_entry *) NULL;
8147
db51cc60 8148 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8149 if (!allow_index_reg
db51cc60
L		 8150 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8151 return (const reg_entry *) NULL;
8152
a60de03c
JB		 8153 if (((r->reg_flags & (RegRex64 | RegRex))
8154 || r->reg_type.bitfield.reg64)
40fb9820 8155 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8156 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8157 && flag_code != CODE_64BIT)
20f0a1fc 8158 return (const reg_entry *) NULL;
1ae00879 8159
b7240065
JB		 8160 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8161 return (const reg_entry *) NULL;
8162
252b5132
RH		 8163 return r;
8164}
4d1bb795
JB		 8165
8166/* REG_STRING starts *before* REGISTER_PREFIX. */
8167
8168static const reg_entry *
8169parse_register (char *reg_string, char **end_op)
8170{
8171 const reg_entry *r;
8172
8173 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8174 r = parse_real_register (reg_string, end_op);
8175 else
8176 r = NULL;
8177 if (!r)
8178 {
8179 char *save = input_line_pointer;
8180 char c;
8181 symbolS *symbolP;
8182
8183 input_line_pointer = reg_string;
8184 c = get_symbol_end ();
8185 symbolP = symbol_find (reg_string);
8186 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8187 {
8188 const expressionS *e = symbol_get_value_expression (symbolP);
8189
0398aac5 8190 know (e->X_op == O_register);
4eed87de 8191 know (e->X_add_number >= 0
c3fe08fa 8192 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8193 r = i386_regtab + e->X_add_number;
8194 *end_op = input_line_pointer;
8195 }
8196 *input_line_pointer = c;
8197 input_line_pointer = save;
8198 }
8199 return r;
8200}
8201
8202int
8203i386_parse_name (char *name, expressionS *e, char *nextcharP)
8204{
8205 const reg_entry *r;
8206 char *end = input_line_pointer;
8207
8208 *end = *nextcharP;
8209 r = parse_register (name, &input_line_pointer);
8210 if (r && end <= input_line_pointer)
8211 {
8212 *nextcharP = *input_line_pointer;
8213 *input_line_pointer = 0;
8214 e->X_op = O_register;
8215 e->X_add_number = r - i386_regtab;
8216 return 1;
8217 }
8218 input_line_pointer = end;
8219 *end = 0;
ee86248c 8220 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8221}
8222
8223void
8224md_operand (expressionS *e)
8225{
ee86248c
JB		 8226 char *end;
8227 const reg_entry *r;
4d1bb795 8228
ee86248c
JB		 8229 switch (*input_line_pointer)
8230 {
8231 case REGISTER_PREFIX:
8232 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8233 if (r)
8234 {
8235 e->X_op = O_register;
8236 e->X_add_number = r - i386_regtab;
8237 input_line_pointer = end;
8238 }
ee86248c
JB		 8239 break;
8240
8241 case '[':
9c2799c2 8242 gas_assert (intel_syntax);
ee86248c
JB		 8243 end = input_line_pointer++;
8244 expression (e);
8245 if (*input_line_pointer == ']')
8246 {
8247 ++input_line_pointer;
8248 e->X_op_symbol = make_expr_symbol (e);
8249 e->X_add_symbol = NULL;
8250 e->X_add_number = 0;
8251 e->X_op = O_index;
8252 }
8253 else
8254 {
8255 e->X_op = O_absent;
8256 input_line_pointer = end;
8257 }
8258 break;
4d1bb795
JB		 8259 }
8260}
8261
252b5132 8262\f
4cc782b5 8263#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8264const char *md_shortopts = "kVQ:sqn";
252b5132 8265#else
12b55ccc 8266const char *md_shortopts = "qn";
252b5132 8267#endif
6e0b89ee 8268
3e73aa7c 8269#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8270#define OPTION_64 (OPTION_MD_BASE + 1)
8271#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8272#define OPTION_MARCH (OPTION_MD_BASE + 3)
8273#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8274#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8275#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8276#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8277#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8278#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8279#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8280#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8281#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
570561f7 8282#define OPTION_X32 (OPTION_MD_BASE + 13)
b3b91714 8283
99ad8390
NC		 8284struct option md_longopts[] =
8285{
3e73aa7c 8286 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8287#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8288 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8289 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8290#endif
8291#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8292 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8293#endif
b3b91714 8294 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8295 {"march", required_argument, NULL, OPTION_MARCH},
8296 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8297 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8298 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8299 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8300 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8301 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8302 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8303 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8304 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8305 {NULL, no_argument, NULL, 0}
8306};
8307size_t md_longopts_size = sizeof (md_longopts);
8308
8309int
9103f4f4 8310md_parse_option (int c, char *arg)
252b5132 8311{
91d6fa6a 8312 unsigned int j;
6305a203 8313 char *arch, *next;
9103f4f4 8314
252b5132
RH		 8315 switch (c)
8316 {
12b55ccc
L		 8317 case 'n':
8318 optimize_align_code = 0;
8319 break;
8320
a38cf1db
AM		 8321 case 'q':
8322 quiet_warnings = 1;
252b5132
RH		 8323 break;
8324
8325#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8326 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8327 should be emitted or not. FIXME: Not implemented. */
8328 case 'Q':
252b5132
RH		 8329 break;
8330
8331 /* -V: SVR4 argument to print version ID. */
8332 case 'V':
8333 print_version_id ();
8334 break;
8335
a38cf1db
AM		 8336 /* -k: Ignore for FreeBSD compatibility. */
8337 case 'k':
252b5132 8338 break;
4cc782b5
ILT		 8339
8340 case 's':
8341 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8342 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8343 break;
99ad8390 8344#endif
321098a5
L		 8345#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8346 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8347 case OPTION_64:
8348 {
8349 const char **list, **l;
8350
3e73aa7c
JH		 8351 list = bfd_target_list ();
8352 for (l = list; *l != NULL; l++)
8620418b 8353 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8354 || strcmp (*l, "coff-x86-64") == 0
8355 || strcmp (*l, "pe-x86-64") == 0
8356 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8357 {
8358 default_arch = "x86_64";
8359 break;
8360 }
3e73aa7c 8361 if (*l == NULL)
2b5d6a91 8362 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8363 free (list);
8364 }
8365 break;
8366#endif
252b5132 8367
351f65ca 8368#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8369 case OPTION_X32:
351f65ca
L		 8370 if (IS_ELF)
8371 {
8372 const char **list, **l;
8373
8374 list = bfd_target_list ();
8375 for (l = list; *l != NULL; l++)
8376 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8377 {
8378 default_arch = "x86_64:32";
8379 break;
8380 }
8381 if (*l == NULL)
2b5d6a91 8382 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8383 free (list);
8384 }
8385 else
8386 as_fatal (_("32bit x86_64 is only supported for ELF"));
8387 break;
8388#endif
8389
6e0b89ee
AM		 8390 case OPTION_32:
8391 default_arch = "i386";
8392 break;
8393
b3b91714
AM		 8394 case OPTION_DIVIDE:
8395#ifdef SVR4_COMMENT_CHARS
8396 {
8397 char *n, *t;
8398 const char *s;
8399
8400 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8401 t = n;
8402 for (s = i386_comment_chars; *s != '\0'; s++)
8403 if (*s != '/')
8404 *t++ = *s;
8405 *t = '\0';
8406 i386_comment_chars = n;
8407 }
8408#endif
8409 break;
8410
9103f4f4 8411 case OPTION_MARCH:
6305a203
L		 8412 arch = xstrdup (arg);
8413 do
9103f4f4 8414 {
6305a203 8415 if (*arch == '.')
2b5d6a91 8416 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8417 next = strchr (arch, '+');
8418 if (next)
8419 *next++ = '\0';
91d6fa6a 8420 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8421 {
91d6fa6a 8422 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8423 {
6305a203 8424 /* Processor. */
1ded5609
JB		 8425 if (! cpu_arch[j].flags.bitfield.cpui386)
8426 continue;
8427
91d6fa6a 8428 cpu_arch_name = cpu_arch[j].name;
6305a203 8429 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8430 cpu_arch_flags = cpu_arch[j].flags;
8431 cpu_arch_isa = cpu_arch[j].type;
8432 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8433 if (!cpu_arch_tune_set)
8434 {
8435 cpu_arch_tune = cpu_arch_isa;
8436 cpu_arch_tune_flags = cpu_arch_isa_flags;
8437 }
8438 break;
8439 }
91d6fa6a
NC		 8440 else if (*cpu_arch [j].name == '.'
8441 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8442 {
8443 /* ISA entension. */
8444 i386_cpu_flags flags;
309d3373 8445
49021df2 8446 if (!cpu_arch[j].negated)
309d3373 8447 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8448 cpu_arch[j].flags);
309d3373
JB		 8449 else
8450 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8451 cpu_arch[j].flags);
0dfbf9d7 8452 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8453 {
8454 if (cpu_sub_arch_name)
8455 {
8456 char *name = cpu_sub_arch_name;
8457 cpu_sub_arch_name = concat (name,
91d6fa6a 8458 cpu_arch[j].name,
1bf57e9f 8459 (const char *) NULL);
6305a203
L		 8460 free (name);
8461 }
8462 else
91d6fa6a 8463 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8464 cpu_arch_flags = flags;
a586129e 8465 cpu_arch_isa_flags = flags;
6305a203
L		 8466 }
8467 break;
ccc9c027 8468 }
9103f4f4 8469 }
6305a203 8470
91d6fa6a 8471 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8472 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8473
8474 arch = next;
9103f4f4 8475 }
6305a203 8476 while (next != NULL );
9103f4f4
L		 8477 break;
8478
8479 case OPTION_MTUNE:
8480 if (*arg == '.')
2b5d6a91 8481 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8482 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8483 {
91d6fa6a 8484 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8485 {
ccc9c027 8486 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8487 cpu_arch_tune = cpu_arch [j].type;
8488 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8489 break;
8490 }
8491 }
91d6fa6a 8492 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8493 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8494 break;
8495
1efbbeb4
L		 8496 case OPTION_MMNEMONIC:
8497 if (strcasecmp (arg, "att") == 0)
8498 intel_mnemonic = 0;
8499 else if (strcasecmp (arg, "intel") == 0)
8500 intel_mnemonic = 1;
8501 else
2b5d6a91 8502 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8503 break;
8504
8505 case OPTION_MSYNTAX:
8506 if (strcasecmp (arg, "att") == 0)
8507 intel_syntax = 0;
8508 else if (strcasecmp (arg, "intel") == 0)
8509 intel_syntax = 1;
8510 else
2b5d6a91 8511 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8512 break;
8513
8514 case OPTION_MINDEX_REG:
8515 allow_index_reg = 1;
8516 break;
8517
8518 case OPTION_MNAKED_REG:
8519 allow_naked_reg = 1;
8520 break;
8521
8522 case OPTION_MOLD_GCC:
8523 old_gcc = 1;
1efbbeb4
L		 8524 break;
8525
c0f3af97
L		 8526 case OPTION_MSSE2AVX:
8527 sse2avx = 1;
8528 break;
8529
daf50ae7
L		 8530 case OPTION_MSSE_CHECK:
8531 if (strcasecmp (arg, "error") == 0)
8532 sse_check = sse_check_error;
8533 else if (strcasecmp (arg, "warning") == 0)
8534 sse_check = sse_check_warning;
8535 else if (strcasecmp (arg, "none") == 0)
8536 sse_check = sse_check_none;
8537 else
2b5d6a91 8538 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8539 break;
8540
539f890d
L		 8541 case OPTION_MAVXSCALAR:
8542 if (strcasecmp (arg, "128") == 0)
8543 avxscalar = vex128;
8544 else if (strcasecmp (arg, "256") == 0)
8545 avxscalar = vex256;
8546 else
2b5d6a91 8547 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8548 break;
8549
252b5132
RH		 8550 default:
8551 return 0;
8552 }
8553 return 1;
8554}
8555
8a2c8fef
L		 8556#define MESSAGE_TEMPLATE \
8557" "
8558
8559static void
1ded5609 8560show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8561{
8562 static char message[] = MESSAGE_TEMPLATE;
8563 char *start = message + 27;
8564 char *p;
8565 int size = sizeof (MESSAGE_TEMPLATE);
8566 int left;
8567 const char *name;
8568 int len;
8569 unsigned int j;
8570
8571 p = start;
8572 left = size - (start - message);
8573 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8574 {
8575 /* Should it be skipped? */
8576 if (cpu_arch [j].skip)
8577 continue;
8578
8579 name = cpu_arch [j].name;
8580 len = cpu_arch [j].len;
8581 if (*name == '.')
8582 {
8583 /* It is an extension. Skip if we aren't asked to show it. */
8584 if (ext)
8585 {
8586 name++;
8587 len--;
8588 }
8589 else
8590 continue;
8591 }
8592 else if (ext)
8593 {
8594 /* It is an processor. Skip if we show only extension. */
8595 continue;
8596 }
1ded5609
JB		 8597 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8598 {
8599 /* It is an impossible processor - skip. */
8600 continue;
8601 }
8a2c8fef
L		 8602
8603 /* Reserve 2 spaces for ", " or ",\0" */
8604 left -= len + 2;
8605
8606 /* Check if there is any room. */
8607 if (left >= 0)
8608 {
8609 if (p != start)
8610 {
8611 *p++ = ',';
8612 *p++ = ' ';
8613 }
8614 p = mempcpy (p, name, len);
8615 }
8616 else
8617 {
8618 /* Output the current message now and start a new one. */
8619 *p++ = ',';
8620 *p = '\0';
8621 fprintf (stream, "%s\n", message);
8622 p = start;
8623 left = size - (start - message) - len - 2;
8624
8625 gas_assert (left >= 0);
8626
8627 p = mempcpy (p, name, len);
8628 }
8629 }
8630
8631 *p = '\0';
8632 fprintf (stream, "%s\n", message);
8633}
8634
252b5132 8635void
8a2c8fef 8636md_show_usage (FILE *stream)
252b5132 8637{
4cc782b5
ILT		 8638#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8639 fprintf (stream, _("\
a38cf1db
AM		 8640 -Q ignored\n\
8641 -V print assembler version number\n\
b3b91714
AM		 8642 -k ignored\n"));
8643#endif
8644 fprintf (stream, _("\
12b55ccc 8645 -n Do not optimize code alignment\n\
b3b91714
AM		 8646 -q quieten some warnings\n"));
8647#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8648 fprintf (stream, _("\
a38cf1db 8649 -s ignored\n"));
b3b91714 8650#endif
321098a5
L		 8651#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8652 || defined (TE_PE) || defined (TE_PEP))
751d281c 8653 fprintf (stream, _("\
570561f7 8654 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8655#endif
b3b91714
AM		 8656#ifdef SVR4_COMMENT_CHARS
8657 fprintf (stream, _("\
8658 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8659#else
8660 fprintf (stream, _("\
b3b91714 8661 --divide ignored\n"));
4cc782b5 8662#endif
9103f4f4 8663 fprintf (stream, _("\
6305a203 8664 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8665 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8666 show_arch (stream, 0, 1);
8a2c8fef
L		 8667 fprintf (stream, _("\
8668 EXTENSION is combination of:\n"));
1ded5609 8669 show_arch (stream, 1, 0);
6305a203 8670 fprintf (stream, _("\
8a2c8fef 8671 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8672 show_arch (stream, 0, 0);
ba104c83 8673 fprintf (stream, _("\
c0f3af97
L		 8674 -msse2avx encode SSE instructions with VEX prefix\n"));
8675 fprintf (stream, _("\
daf50ae7
L		 8676 -msse-check=[none|error|warning]\n\
8677 check SSE instructions\n"));
8678 fprintf (stream, _("\
539f890d
L		 8679 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8680 length\n"));
8681 fprintf (stream, _("\
ba104c83
L		 8682 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8683 fprintf (stream, _("\
8684 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8685 fprintf (stream, _("\
8686 -mindex-reg support pseudo index registers\n"));
8687 fprintf (stream, _("\
8688 -mnaked-reg don't require `%%' prefix for registers\n"));
8689 fprintf (stream, _("\
8690 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8691}
8692
3e73aa7c 8693#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8694 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8695 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8696
8697/* Pick the target format to use. */
8698
47926f60 8699const char *
e3bb37b5 8700i386_target_format (void)
252b5132 8701{
351f65ca
L		 8702 if (!strncmp (default_arch, "x86_64", 6))
8703 {
8704 update_code_flag (CODE_64BIT, 1);
8705 if (default_arch[6] == '\0')
7f56bc95 8706 x86_elf_abi = X86_64_ABI;
351f65ca 8707 else
7f56bc95 8708 x86_elf_abi = X86_64_X32_ABI;
351f65ca 8709 }
3e73aa7c 8710 else if (!strcmp (default_arch, "i386"))
78f12dd3 8711 update_code_flag (CODE_32BIT, 1);
3e73aa7c 8712 else
2b5d6a91 8713 as_fatal (_("unknown architecture"));
89507696
JB		 8714
8715 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8716 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8717 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8718 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8719
252b5132
RH		 8720 switch (OUTPUT_FLAVOR)
8721 {
9384f2ff 8722#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8723 case bfd_target_aout_flavour:
47926f60 8724 return AOUT_TARGET_FORMAT;
4c63da97 8725#endif
9384f2ff
AM		 8726#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8727# if defined (TE_PE) || defined (TE_PEP)
8728 case bfd_target_coff_flavour:
8729 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8730# elif defined (TE_GO32)
0561d57c
JK		 8731 case bfd_target_coff_flavour:
8732 return "coff-go32";
9384f2ff 8733# else
252b5132
RH		 8734 case bfd_target_coff_flavour:
8735 return "coff-i386";
9384f2ff 8736# endif
4c63da97 8737#endif
3e73aa7c 8738#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8739 case bfd_target_elf_flavour:
3e73aa7c 8740 {
351f65ca
L		 8741 const char *format;
8742
8743 switch (x86_elf_abi)
4fa24527 8744 {
351f65ca
L		 8745 default:
8746 format = ELF_TARGET_FORMAT;
8747 break;
7f56bc95 8748 case X86_64_ABI:
351f65ca 8749 use_rela_relocations = 1;
4fa24527 8750 object_64bit = 1;
351f65ca
L		 8751 format = ELF_TARGET_FORMAT64;
8752 break;
7f56bc95 8753 case X86_64_X32_ABI:
4fa24527 8754 use_rela_relocations = 1;
351f65ca 8755 object_64bit = 1;
862be3fb 8756 disallow_64bit_reloc = 1;
351f65ca
L		 8757 format = ELF_TARGET_FORMAT32;
8758 break;
4fa24527 8759 }
3632d14b 8760 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8761 {
7f56bc95 8762 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 8763 as_fatal (_("Intel L1OM is 64bit only"));
8764 return ELF_TARGET_L1OM_FORMAT;
8765 }
7a9068fe
L		 8766 if (cpu_arch_isa == PROCESSOR_K1OM)
8767 {
8768 if (x86_elf_abi != X86_64_ABI)
8769 as_fatal (_("Intel K1OM is 64bit only"));
8770 return ELF_TARGET_K1OM_FORMAT;
8771 }
8a9036a4 8772 else
351f65ca 8773 return format;
3e73aa7c 8774 }
e57f8c65
TG		 8775#endif
8776#if defined (OBJ_MACH_O)
8777 case bfd_target_mach_o_flavour:
8778 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8779#endif
252b5132
RH		 8780 default:
8781 abort ();
8782 return NULL;
8783 }
8784}
8785
47926f60 8786#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8787
8788#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8789void
8790i386_elf_emit_arch_note (void)
a847613f 8791{
718ddfc0 8792 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8793 {
8794 char *p;
8795 asection *seg = now_seg;
8796 subsegT subseg = now_subseg;
8797 Elf_Internal_Note i_note;
8798 Elf_External_Note e_note;
8799 asection *note_secp;
8800 int len;
8801
8802 /* Create the .note section. */
8803 note_secp = subseg_new (".note", 0);
8804 bfd_set_section_flags (stdoutput,
8805 note_secp,
8806 SEC_HAS_CONTENTS | SEC_READONLY);
8807
8808 /* Process the arch string. */
8809 len = strlen (cpu_arch_name);
8810
8811 i_note.namesz = len + 1;
8812 i_note.descsz = 0;
8813 i_note.type = NT_ARCH;
8814 p = frag_more (sizeof (e_note.namesz));
8815 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8816 p = frag_more (sizeof (e_note.descsz));
8817 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8818 p = frag_more (sizeof (e_note.type));
8819 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8820 p = frag_more (len + 1);
8821 strcpy (p, cpu_arch_name);
8822
8823 frag_align (2, 0, 0);
8824
8825 subseg_set (seg, subseg);
8826 }
8827}
8828#endif
252b5132 8829\f
252b5132 8830symbolS *
7016a5d5 8831md_undefined_symbol (char *name)
252b5132 8832{
18dc2407
ILT		 8833 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8834 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8835 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8836 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8837 {
8838 if (!GOT_symbol)
8839 {
8840 if (symbol_find (name))
8841 as_bad (_("GOT already in symbol table"));
8842 GOT_symbol = symbol_new (name, undefined_section,
8843 (valueT) 0, &zero_address_frag);
8844 };
8845 return GOT_symbol;
8846 }
252b5132
RH		 8847 return 0;
8848}
8849
8850/* Round up a section size to the appropriate boundary. */
47926f60 8851
252b5132 8852valueT
7016a5d5 8853md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 8854{
4c63da97
AM		 8855#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8856 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8857 {
8858 /* For a.out, force the section size to be aligned. If we don't do
8859 this, BFD will align it for us, but it will not write out the
8860 final bytes of the section. This may be a bug in BFD, but it is
8861 easier to fix it here since that is how the other a.out targets
8862 work. */
8863 int align;
8864
8865 align = bfd_get_section_alignment (stdoutput, segment);
8866 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8867 }
252b5132
RH		 8868#endif
8869
8870 return size;
8871}
8872
8873/* On the i386, PC-relative offsets are relative to the start of the
8874 next instruction. That is, the address of the offset, plus its
8875 size, since the offset is always the last part of the insn. */
8876
8877long
e3bb37b5 8878md_pcrel_from (fixS *fixP)
252b5132
RH		 8879{
8880 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8881}
8882
8883#ifndef I386COFF
8884
8885static void
e3bb37b5 8886s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8887{
29b0f896 8888 int temp;
252b5132 8889
8a75718c
JB		 8890#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8891 if (IS_ELF)
8892 obj_elf_section_change_hook ();
8893#endif
252b5132
RH		 8894 temp = get_absolute_expression ();
8895 subseg_set (bss_section, (subsegT) temp);
8896 demand_empty_rest_of_line ();
8897}
8898
8899#endif
8900
252b5132 8901void
e3bb37b5 8902i386_validate_fix (fixS *fixp)
252b5132
RH		 8903{
8904 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8905 {
23df1078
JH		 8906 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8907 {
4fa24527 8908 if (!object_64bit)
23df1078
JH		 8909 abort ();
8910 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8911 }
8912 else
8913 {
4fa24527 8914 if (!object_64bit)
d6ab8113
JB		 8915 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8916 else
8917 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8918 }
252b5132
RH		 8919 fixp->fx_subsy = 0;
8920 }
8921}
8922
252b5132 8923arelent *
7016a5d5 8924tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 8925{
8926 arelent *rel;
8927 bfd_reloc_code_real_type code;
8928
8929 switch (fixp->fx_r_type)
8930 {
3e73aa7c
JH		 8931 case BFD_RELOC_X86_64_PLT32:
8932 case BFD_RELOC_X86_64_GOT32:
8933 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8934 case BFD_RELOC_386_PLT32:
8935 case BFD_RELOC_386_GOT32:
8936 case BFD_RELOC_386_GOTOFF:
8937 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8938 case BFD_RELOC_386_TLS_GD:
8939 case BFD_RELOC_386_TLS_LDM:
8940 case BFD_RELOC_386_TLS_LDO_32:
8941 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8942 case BFD_RELOC_386_TLS_IE:
8943 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8944 case BFD_RELOC_386_TLS_LE_32:
8945 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8946 case BFD_RELOC_386_TLS_GOTDESC:
8947 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8948 case BFD_RELOC_X86_64_TLSGD:
8949 case BFD_RELOC_X86_64_TLSLD:
8950 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8951 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8952 case BFD_RELOC_X86_64_GOTTPOFF:
8953 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8954 case BFD_RELOC_X86_64_TPOFF64:
8955 case BFD_RELOC_X86_64_GOTOFF64:
8956 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8957 case BFD_RELOC_X86_64_GOT64:
8958 case BFD_RELOC_X86_64_GOTPCREL64:
8959 case BFD_RELOC_X86_64_GOTPC64:
8960 case BFD_RELOC_X86_64_GOTPLT64:
8961 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8962 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8963 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8964 case BFD_RELOC_RVA:
8965 case BFD_RELOC_VTABLE_ENTRY:
8966 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8967#ifdef TE_PE
8968 case BFD_RELOC_32_SECREL:
8969#endif
252b5132
RH		 8970 code = fixp->fx_r_type;
8971 break;
dbbaec26
L		 8972 case BFD_RELOC_X86_64_32S:
8973 if (!fixp->fx_pcrel)
8974 {
8975 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8976 code = fixp->fx_r_type;
8977 break;
8978 }
252b5132 8979 default:
93382f6d 8980 if (fixp->fx_pcrel)
252b5132 8981 {
93382f6d
AM		 8982 switch (fixp->fx_size)
8983 {
8984 default:
b091f402
AM		 8985 as_bad_where (fixp->fx_file, fixp->fx_line,
8986 _("can not do %d byte pc-relative relocation"),
8987 fixp->fx_size);
93382f6d
AM		 8988 code = BFD_RELOC_32_PCREL;
8989 break;
8990 case 1: code = BFD_RELOC_8_PCREL; break;
8991 case 2: code = BFD_RELOC_16_PCREL; break;
8992 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8993#ifdef BFD64
8994 case 8: code = BFD_RELOC_64_PCREL; break;
8995#endif
93382f6d
AM		 8996 }
8997 }
8998 else
8999 {
9000 switch (fixp->fx_size)
9001 {
9002 default:
b091f402
AM		 9003 as_bad_where (fixp->fx_file, fixp->fx_line,
9004 _("can not do %d byte relocation"),
9005 fixp->fx_size);
93382f6d
AM		 9006 code = BFD_RELOC_32;
9007 break;
9008 case 1: code = BFD_RELOC_8; break;
9009 case 2: code = BFD_RELOC_16; break;
9010 case 4: code = BFD_RELOC_32; break;
937149dd 9011#ifdef BFD64
3e73aa7c 9012 case 8: code = BFD_RELOC_64; break;
937149dd 9013#endif
93382f6d 9014 }
252b5132
RH		 9015 }
9016 break;
9017 }
252b5132 9018
d182319b
JB		 9019 if ((code == BFD_RELOC_32
9020 || code == BFD_RELOC_32_PCREL
9021 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 9022 && GOT_symbol
9023 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 9024 {
4fa24527 9025 if (!object_64bit)
d6ab8113
JB		 9026 code = BFD_RELOC_386_GOTPC;
9027 else
9028 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9029 }
7b81dfbb
AJ		 9030 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9031 && GOT_symbol
9032 && fixp->fx_addsy == GOT_symbol)
9033 {
9034 code = BFD_RELOC_X86_64_GOTPC64;
9035 }
252b5132
RH		 9036
9037 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9038 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9039 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9040
9041 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9042
3e73aa7c
JH		 9043 if (!use_rela_relocations)
9044 {
9045 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9046 vtable entry to be used in the relocation's section offset. */
9047 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9048 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9049#if defined (OBJ_COFF) && defined (TE_PE)
9050 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9051 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9052 else
9053#endif
c6682705 9054 rel->addend = 0;
3e73aa7c
JH		 9055 }
9056 /* Use the rela in 64bit mode. */
252b5132 9057 else
3e73aa7c 9058 {
862be3fb
L		 9059 if (disallow_64bit_reloc)
9060 switch (code)
9061 {
9062 case BFD_RELOC_64:
9063 case BFD_RELOC_X86_64_DTPOFF64:
9064 case BFD_RELOC_X86_64_TPOFF64:
9065 case BFD_RELOC_64_PCREL:
9066 case BFD_RELOC_X86_64_GOTOFF64:
9067 case BFD_RELOC_X86_64_GOT64:
9068 case BFD_RELOC_X86_64_GOTPCREL64:
9069 case BFD_RELOC_X86_64_GOTPC64:
9070 case BFD_RELOC_X86_64_GOTPLT64:
9071 case BFD_RELOC_X86_64_PLTOFF64:
9072 as_bad_where (fixp->fx_file, fixp->fx_line,
9073 _("cannot represent relocation type %s in x32 mode"),
9074 bfd_get_reloc_code_name (code));
9075 break;
9076 default:
9077 break;
9078 }
9079
062cd5e7
AS		 9080 if (!fixp->fx_pcrel)
9081 rel->addend = fixp->fx_offset;
9082 else
9083 switch (code)
9084 {
9085 case BFD_RELOC_X86_64_PLT32:
9086 case BFD_RELOC_X86_64_GOT32:
9087 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9088 case BFD_RELOC_X86_64_TLSGD:
9089 case BFD_RELOC_X86_64_TLSLD:
9090 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9091 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9092 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9093 rel->addend = fixp->fx_offset - fixp->fx_size;
9094 break;
9095 default:
9096 rel->addend = (section->vma
9097 - fixp->fx_size
9098 + fixp->fx_addnumber
9099 + md_pcrel_from (fixp));
9100 break;
9101 }
3e73aa7c
JH		 9102 }
9103
252b5132
RH		 9104 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9105 if (rel->howto == NULL)
9106 {
9107 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9108 _("cannot represent relocation type %s"),
252b5132
RH		 9109 bfd_get_reloc_code_name (code));
9110 /* Set howto to a garbage value so that we can keep going. */
9111 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9112 gas_assert (rel->howto != NULL);
252b5132
RH		 9113 }
9114
9115 return rel;
9116}
9117
ee86248c 9118#include "tc-i386-intel.c"
54cfded0 9119
a60de03c
JB		 9120void
9121tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9122{
a60de03c
JB		 9123 int saved_naked_reg;
9124 char saved_register_dot;
54cfded0 9125
a60de03c
JB		 9126 saved_naked_reg = allow_naked_reg;
9127 allow_naked_reg = 1;
9128 saved_register_dot = register_chars['.'];
9129 register_chars['.'] = '.';
9130 allow_pseudo_reg = 1;
9131 expression_and_evaluate (exp);
9132 allow_pseudo_reg = 0;
9133 register_chars['.'] = saved_register_dot;
9134 allow_naked_reg = saved_naked_reg;
9135
e96d56a1 9136 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9137 {
a60de03c
JB		 9138 if ((addressT) exp->X_add_number < i386_regtab_size)
9139 {
9140 exp->X_op = O_constant;
9141 exp->X_add_number = i386_regtab[exp->X_add_number]
9142 .dw2_regnum[flag_code >> 1];
9143 }
9144 else
9145 exp->X_op = O_illegal;
54cfded0 9146 }
54cfded0
AM		 9147}
9148
9149void
9150tc_x86_frame_initial_instructions (void)
9151{
a60de03c
JB		 9152 static unsigned int sp_regno[2];
9153
9154 if (!sp_regno[flag_code >> 1])
9155 {
9156 char *saved_input = input_line_pointer;
9157 char sp[][4] = {"esp", "rsp"};
9158 expressionS exp;
a4447b93 9159
a60de03c
JB		 9160 input_line_pointer = sp[flag_code >> 1];
9161 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9162 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9163 sp_regno[flag_code >> 1] = exp.X_add_number;
9164 input_line_pointer = saved_input;
9165 }
a4447b93 9166
61ff971f
L		 9167 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9168 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9169}
d2b2c203
DJ		 9170
9171int
9172i386_elf_section_type (const char *str, size_t len)
9173{
9174 if (flag_code == CODE_64BIT
9175 && len == sizeof ("unwind") - 1
9176 && strncmp (str, "unwind", 6) == 0)
9177 return SHT_X86_64_UNWIND;
9178
9179 return -1;
9180}
bb41ade5 9181
ad5fec3b
EB		 9182#ifdef TE_SOLARIS
9183void
9184i386_solaris_fix_up_eh_frame (segT sec)
9185{
9186 if (flag_code == CODE_64BIT)
9187 elf_section_type (sec) = SHT_X86_64_UNWIND;
9188}
9189#endif
9190
bb41ade5
AM		 9191#ifdef TE_PE
9192void
9193tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9194{
91d6fa6a 9195 expressionS exp;
bb41ade5 9196
91d6fa6a
NC		 9197 exp.X_op = O_secrel;
9198 exp.X_add_symbol = symbol;
9199 exp.X_add_number = 0;
9200 emit_expr (&exp, size);
bb41ade5
AM		 9201}
9202#endif
3b22753a
L		 9203
9204#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9205/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9206
01e1a5bc 9207bfd_vma
3b22753a
L		 9208x86_64_section_letter (int letter, char **ptr_msg)
9209{
9210 if (flag_code == CODE_64BIT)
9211 {
9212 if (letter == 'l')
9213 return SHF_X86_64_LARGE;
9214
8f3bae45 9215 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9216 }
3b22753a 9217 else
8f3bae45 9218 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9219 return -1;
9220}
9221
01e1a5bc 9222bfd_vma
3b22753a
L		 9223x86_64_section_word (char *str, size_t len)
9224{
8620418b 9225 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9226 return SHF_X86_64_LARGE;
9227
9228 return -1;
9229}
9230
9231static void
9232handle_large_common (int small ATTRIBUTE_UNUSED)
9233{
9234 if (flag_code != CODE_64BIT)
9235 {
9236 s_comm_internal (0, elf_common_parse);
9237 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9238 }
9239 else
9240 {
9241 static segT lbss_section;
9242 asection *saved_com_section_ptr = elf_com_section_ptr;
9243 asection *saved_bss_section = bss_section;
9244
9245 if (lbss_section == NULL)
9246 {
9247 flagword applicable;
9248 segT seg = now_seg;
9249 subsegT subseg = now_subseg;
9250
9251 /* The .lbss section is for local .largecomm symbols. */
9252 lbss_section = subseg_new (".lbss", 0);
9253 applicable = bfd_applicable_section_flags (stdoutput);
9254 bfd_set_section_flags (stdoutput, lbss_section,
9255 applicable & SEC_ALLOC);
9256 seg_info (lbss_section)->bss = 1;
9257
9258 subseg_set (seg, subseg);
9259 }
9260
9261 elf_com_section_ptr = &_bfd_elf_large_com_section;
9262 bss_section = lbss_section;
9263
9264 s_comm_internal (0, elf_common_parse);
9265
9266 elf_com_section_ptr = saved_com_section_ptr;
9267 bss_section = saved_bss_section;
9268 }
9269}
314a59d5
L		 9270
9271static void
9272handle_quad (int nbytes)
9273{
9274 expressionS exp;
9275
9276 if (x86_elf_abi != X86_64_X32_ABI)
9277 {
9278 cons (nbytes);
9279 return;
9280 }
9281
9282 if (is_it_end_of_statement ())
9283 {
9284 demand_empty_rest_of_line ();
9285 return;
9286 }
9287
9288 do
9289 {
9290 if (*input_line_pointer == '"')
9291 {
9292 as_bad (_("unexpected `\"' in expression"));
9293 ignore_rest_of_line ();
9294 return;
9295 }
9296 x86_cons (&exp, nbytes);
9297 /* Output 4 bytes if not constant. */
9298 if (exp.X_op != O_constant)
9299 nbytes = 4;
9300 emit_expr (&exp, (unsigned int) nbytes);
75c1c785
L		 9301 /* Zero-extends to 8 bytes if not constant. */
9302 if (nbytes == 4)
9303 {
9304 memset (&exp, '\0', sizeof (exp));
9305 exp.X_op = O_constant;
9306 emit_expr (&exp, nbytes);
9307 }
9308 nbytes = 8;
314a59d5
L		 9309 }
9310 while (*input_line_pointer++ == ',');
9311
9312 input_line_pointer--; /* Put terminator back into stream. */
9313
9314 demand_empty_rest_of_line ();
314a59d5 9315}
3b22753a 9316#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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