Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
b77a7acd | 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 |
47926f60 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
47926f60 KH |
22 | /* Intel 80386 machine specific gas. |
23 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 24 | x86_64 support by Jan Hubicka (jh@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 RH |
27 | |
28 | #include <ctype.h> | |
29 | ||
30 | #include "as.h" | |
31 | #include "subsegs.h" | |
316e2c05 | 32 | #include "dwarf2dbg.h" |
252b5132 RH |
33 | #include "opcode/i386.h" |
34 | ||
252b5132 RH |
35 | #ifndef REGISTER_WARNINGS |
36 | #define REGISTER_WARNINGS 1 | |
37 | #endif | |
38 | ||
c3332e24 | 39 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 40 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
41 | #endif |
42 | ||
252b5132 RH |
43 | #ifndef SCALE1_WHEN_NO_INDEX |
44 | /* Specifying a scale factor besides 1 when there is no index is | |
45 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
46 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
47 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
48 | #define SCALE1_WHEN_NO_INDEX 1 | |
49 | #endif | |
50 | ||
51 | #define true 1 | |
52 | #define false 0 | |
53 | ||
54 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
55 | static int fits_in_signed_byte PARAMS ((offsetT)); |
56 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
57 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
58 | static int fits_in_signed_word PARAMS ((offsetT)); | |
3e73aa7c JH |
59 | static int fits_in_unsigned_long PARAMS ((offsetT)); |
60 | static int fits_in_signed_long PARAMS ((offsetT)); | |
847f7ad4 AM |
61 | static int smallest_imm_type PARAMS ((offsetT)); |
62 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 | 63 | static int add_prefix PARAMS ((unsigned int)); |
3e73aa7c | 64 | static void set_code_flag PARAMS ((int)); |
47926f60 | 65 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 66 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 67 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
68 | |
69 | #ifdef BFD_ASSEMBLER | |
70 | static bfd_reloc_code_real_type reloc | |
3e73aa7c | 71 | PARAMS ((int, int, int, bfd_reloc_code_real_type)); |
252b5132 RH |
72 | #endif |
73 | ||
3e73aa7c JH |
74 | #ifndef DEFAULT_ARCH |
75 | #define DEFAULT_ARCH "i386" | |
76 | #endif | |
77 | static char *default_arch = DEFAULT_ARCH; | |
78 | ||
252b5132 | 79 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 80 | i386_insn. */ |
252b5132 | 81 | |
520dc8e8 AM |
82 | union i386_op |
83 | { | |
84 | expressionS *disps; | |
85 | expressionS *imms; | |
86 | const reg_entry *regs; | |
87 | }; | |
88 | ||
252b5132 RH |
89 | struct _i386_insn |
90 | { | |
47926f60 | 91 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
92 | template tm; |
93 | ||
94 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
95 | (e.g. 'l' for 'movl') */ | |
96 | char suffix; | |
97 | ||
47926f60 | 98 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
99 | unsigned int operands; |
100 | ||
101 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
102 | of given register, displacement, memory operands and immediate | |
47926f60 | 103 | operands. */ |
252b5132 RH |
104 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
105 | ||
106 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 107 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
108 | unsigned int types[MAX_OPERANDS]; |
109 | ||
520dc8e8 AM |
110 | /* Displacement expression, immediate expression, or register for each |
111 | operand. */ | |
112 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 113 | |
3e73aa7c JH |
114 | /* Flags for operands. */ |
115 | unsigned int flags[MAX_OPERANDS]; | |
116 | #define Operand_PCrel 1 | |
117 | ||
252b5132 RH |
118 | /* Relocation type for operand */ |
119 | #ifdef BFD_ASSEMBLER | |
120 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
121 | #else | |
122 | int disp_reloc[MAX_OPERANDS]; | |
123 | #endif | |
124 | ||
252b5132 RH |
125 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
126 | the base index byte below. */ | |
127 | const reg_entry *base_reg; | |
128 | const reg_entry *index_reg; | |
129 | unsigned int log2_scale_factor; | |
130 | ||
131 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 132 | explicit segment overrides are given. */ |
ce8a8b2f | 133 | const seg_entry *seg[2]; |
252b5132 RH |
134 | |
135 | /* PREFIX holds all the given prefix opcodes (usually null). | |
136 | PREFIXES is the number of prefix opcodes. */ | |
137 | unsigned int prefixes; | |
138 | unsigned char prefix[MAX_PREFIXES]; | |
139 | ||
140 | /* RM and SIB are the modrm byte and the sib byte where the | |
141 | addressing modes of this insn are encoded. */ | |
142 | ||
143 | modrm_byte rm; | |
3e73aa7c | 144 | rex_byte rex; |
252b5132 RH |
145 | sib_byte sib; |
146 | }; | |
147 | ||
148 | typedef struct _i386_insn i386_insn; | |
149 | ||
150 | /* List of chars besides those in app.c:symbol_chars that can start an | |
151 | operand. Used to prevent the scrubber eating vital white-space. */ | |
152 | #ifdef LEX_AT | |
153 | const char extra_symbol_chars[] = "*%-(@"; | |
154 | #else | |
155 | const char extra_symbol_chars[] = "*%-("; | |
156 | #endif | |
157 | ||
158 | /* This array holds the chars that always start a comment. If the | |
ce8a8b2f | 159 | pre-processor is disabled, these aren't very useful. */ |
60bcf0fa | 160 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
161 | /* Putting '/' here makes it impossible to use the divide operator. |
162 | However, we need it for compatibility with SVR4 systems. */ | |
163 | const char comment_chars[] = "#/"; | |
164 | #define PREFIX_SEPARATOR '\\' | |
165 | #else | |
166 | const char comment_chars[] = "#"; | |
167 | #define PREFIX_SEPARATOR '/' | |
168 | #endif | |
169 | ||
170 | /* This array holds the chars that only start a comment at the beginning of | |
171 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
172 | .line and .file directives will appear in the pre-processed output. |
173 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 174 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
175 | #NO_APP at the beginning of its output. |
176 | Also note that comments started like this one will always work if | |
252b5132 | 177 | '/' isn't otherwise defined. */ |
60bcf0fa | 178 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
179 | const char line_comment_chars[] = ""; |
180 | #else | |
181 | const char line_comment_chars[] = "/"; | |
182 | #endif | |
183 | ||
63a0b638 | 184 | const char line_separator_chars[] = ";"; |
252b5132 | 185 | |
ce8a8b2f AM |
186 | /* Chars that can be used to separate mant from exp in floating point |
187 | nums. */ | |
252b5132 RH |
188 | const char EXP_CHARS[] = "eE"; |
189 | ||
ce8a8b2f AM |
190 | /* Chars that mean this number is a floating point constant |
191 | As in 0f12.456 | |
192 | or 0d1.2345e12. */ | |
252b5132 RH |
193 | const char FLT_CHARS[] = "fFdDxX"; |
194 | ||
ce8a8b2f | 195 | /* Tables for lexical analysis. */ |
252b5132 RH |
196 | static char mnemonic_chars[256]; |
197 | static char register_chars[256]; | |
198 | static char operand_chars[256]; | |
199 | static char identifier_chars[256]; | |
200 | static char digit_chars[256]; | |
201 | ||
ce8a8b2f | 202 | /* Lexical macros. */ |
252b5132 RH |
203 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
204 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
205 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
206 | #define is_space_char(x) ((x) == ' ') | |
207 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
208 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
209 | ||
ce8a8b2f | 210 | /* All non-digit non-letter charcters that may occur in an operand. */ |
252b5132 RH |
211 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
212 | ||
213 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
214 | effect this we maintain a stack of saved characters that we've smashed | |
215 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 216 | assembler instruction). */ |
252b5132 | 217 | static char save_stack[32]; |
ce8a8b2f | 218 | static char *save_stack_p; |
252b5132 RH |
219 | #define END_STRING_AND_SAVE(s) \ |
220 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
221 | #define RESTORE_END_STRING(s) \ | |
222 | do { *(s) = *--save_stack_p; } while (0) | |
223 | ||
47926f60 | 224 | /* The instruction we're assembling. */ |
252b5132 RH |
225 | static i386_insn i; |
226 | ||
227 | /* Possible templates for current insn. */ | |
228 | static const templates *current_templates; | |
229 | ||
47926f60 | 230 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
231 | static expressionS disp_expressions[2], im_expressions[2]; |
232 | ||
47926f60 KH |
233 | /* Current operand we are working on. */ |
234 | static int this_operand; | |
252b5132 | 235 | |
3e73aa7c JH |
236 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
237 | these. */ | |
238 | ||
239 | enum flag_code { | |
240 | CODE_32BIT, | |
241 | CODE_16BIT, | |
242 | CODE_64BIT }; | |
243 | ||
244 | static enum flag_code flag_code; | |
245 | static int use_rela_relocations = 0; | |
246 | ||
247 | /* The names used to print error messages. */ | |
b77a7acd | 248 | static const char *flag_code_names[] = |
3e73aa7c JH |
249 | { |
250 | "32", | |
251 | "16", | |
252 | "64" | |
253 | }; | |
252b5132 | 254 | |
47926f60 KH |
255 | /* 1 for intel syntax, |
256 | 0 if att syntax. */ | |
257 | static int intel_syntax = 0; | |
252b5132 | 258 | |
47926f60 KH |
259 | /* 1 if register prefix % not required. */ |
260 | static int allow_naked_reg = 0; | |
252b5132 | 261 | |
47926f60 KH |
262 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
263 | leave, push, and pop instructions so that gcc has the same stack | |
264 | frame as in 32 bit mode. */ | |
265 | static char stackop_size = '\0'; | |
eecb386c | 266 | |
47926f60 KH |
267 | /* Non-zero to quieten some warnings. */ |
268 | static int quiet_warnings = 0; | |
a38cf1db | 269 | |
47926f60 KH |
270 | /* CPU name. */ |
271 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 272 | |
47926f60 | 273 | /* CPU feature flags. */ |
3e73aa7c | 274 | static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64; |
a38cf1db | 275 | |
252b5132 RH |
276 | /* Interface to relax_segment. |
277 | There are 2 relax states for 386 jump insns: one for conditional & | |
a217f122 AM |
278 | one for unconditional jumps. This is because these two types of |
279 | jumps add different sizes to frags when we're figuring out what | |
252b5132 RH |
280 | sort of jump to choose to reach a given label. */ |
281 | ||
47926f60 | 282 | /* Types. */ |
ce8a8b2f AM |
283 | #define COND_JUMP 1 |
284 | #define UNCOND_JUMP 2 | |
47926f60 | 285 | /* Sizes. */ |
252b5132 RH |
286 | #define CODE16 1 |
287 | #define SMALL 0 | |
288 | #define SMALL16 (SMALL|CODE16) | |
289 | #define BIG 2 | |
290 | #define BIG16 (BIG|CODE16) | |
291 | ||
292 | #ifndef INLINE | |
293 | #ifdef __GNUC__ | |
294 | #define INLINE __inline__ | |
295 | #else | |
296 | #define INLINE | |
297 | #endif | |
298 | #endif | |
299 | ||
300 | #define ENCODE_RELAX_STATE(type,size) \ | |
bc805888 | 301 | ((relax_substateT) ((type<<2) | (size))) |
252b5132 RH |
302 | #define SIZE_FROM_RELAX_STATE(s) \ |
303 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) | |
304 | ||
305 | /* This table is used by relax_frag to promote short jumps to long | |
306 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
307 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
308 | don't allow a short jump in a 32 bit code segment to be promoted to | |
309 | a 16 bit offset jump because it's slower (requires data size | |
310 | prefix), and doesn't work, unless the destination is in the bottom | |
311 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
312 | ||
313 | const relax_typeS md_relax_table[] = | |
314 | { | |
24eab124 AM |
315 | /* The fields are: |
316 | 1) most positive reach of this state, | |
317 | 2) most negative reach of this state, | |
318 | 3) how many bytes this mode will add to the size of the current frag | |
ce8a8b2f | 319 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 RH |
320 | {1, 1, 0, 0}, |
321 | {1, 1, 0, 0}, | |
322 | {1, 1, 0, 0}, | |
323 | {1, 1, 0, 0}, | |
324 | ||
325 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
326 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
327 | /* dword conditionals adds 4 bytes to frag: | |
328 | 1 extra opcode byte, 3 extra displacement bytes. */ | |
329 | {0, 0, 4, 0}, | |
330 | /* word conditionals add 2 bytes to frag: | |
331 | 1 extra opcode byte, 1 extra displacement byte. */ | |
332 | {0, 0, 2, 0}, | |
333 | ||
334 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, | |
335 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
336 | /* dword jmp adds 3 bytes to frag: | |
337 | 0 extra opcode bytes, 3 extra displacement bytes. */ | |
338 | {0, 0, 3, 0}, | |
339 | /* word jmp adds 1 byte to frag: | |
340 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
341 | {0, 0, 1, 0} | |
342 | ||
343 | }; | |
344 | ||
e413e4e9 AM |
345 | static const arch_entry cpu_arch[] = { |
346 | {"i8086", Cpu086 }, | |
347 | {"i186", Cpu086|Cpu186 }, | |
348 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
349 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
350 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
351 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
352 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
353 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
354 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
a167610d | 355 | {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, |
3e73aa7c JH |
356 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, |
357 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, | |
a167610d | 358 | {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, |
e413e4e9 AM |
359 | {NULL, 0 } |
360 | }; | |
361 | ||
252b5132 RH |
362 | void |
363 | i386_align_code (fragP, count) | |
364 | fragS *fragP; | |
365 | int count; | |
366 | { | |
ce8a8b2f AM |
367 | /* Various efficient no-op patterns for aligning code labels. |
368 | Note: Don't try to assemble the instructions in the comments. | |
369 | 0L and 0w are not legal. */ | |
252b5132 RH |
370 | static const char f32_1[] = |
371 | {0x90}; /* nop */ | |
372 | static const char f32_2[] = | |
373 | {0x89,0xf6}; /* movl %esi,%esi */ | |
374 | static const char f32_3[] = | |
375 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
376 | static const char f32_4[] = | |
377 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
378 | static const char f32_5[] = | |
379 | {0x90, /* nop */ | |
380 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
381 | static const char f32_6[] = | |
382 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
383 | static const char f32_7[] = | |
384 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
385 | static const char f32_8[] = | |
386 | {0x90, /* nop */ | |
387 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
388 | static const char f32_9[] = | |
389 | {0x89,0xf6, /* movl %esi,%esi */ | |
390 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
391 | static const char f32_10[] = | |
392 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
393 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
394 | static const char f32_11[] = | |
395 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
396 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
397 | static const char f32_12[] = | |
398 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
399 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
400 | static const char f32_13[] = | |
401 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
402 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
403 | static const char f32_14[] = | |
404 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
405 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
406 | static const char f32_15[] = | |
407 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
408 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
409 | static const char f16_3[] = |
410 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
411 | static const char f16_4[] = |
412 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
413 | static const char f16_5[] = | |
414 | {0x90, /* nop */ | |
415 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
416 | static const char f16_6[] = | |
417 | {0x89,0xf6, /* mov %si,%si */ | |
418 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
419 | static const char f16_7[] = | |
420 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
421 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
422 | static const char f16_8[] = | |
423 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
424 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
425 | static const char *const f32_patt[] = { | |
426 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
427 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
428 | }; | |
429 | static const char *const f16_patt[] = { | |
c3332e24 | 430 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
431 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
432 | }; | |
433 | ||
3e73aa7c JH |
434 | /* ??? We can't use these fillers for x86_64, since they often kills the |
435 | upper halves. Solve later. */ | |
436 | if (flag_code == CODE_64BIT) | |
437 | count = 1; | |
438 | ||
252b5132 RH |
439 | if (count > 0 && count <= 15) |
440 | { | |
3e73aa7c | 441 | if (flag_code == CODE_16BIT) |
252b5132 | 442 | { |
47926f60 KH |
443 | memcpy (fragP->fr_literal + fragP->fr_fix, |
444 | f16_patt[count - 1], count); | |
445 | if (count > 8) | |
446 | /* Adjust jump offset. */ | |
252b5132 RH |
447 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
448 | } | |
449 | else | |
47926f60 KH |
450 | memcpy (fragP->fr_literal + fragP->fr_fix, |
451 | f32_patt[count - 1], count); | |
252b5132 RH |
452 | fragP->fr_var = count; |
453 | } | |
454 | } | |
455 | ||
456 | static char *output_invalid PARAMS ((int c)); | |
457 | static int i386_operand PARAMS ((char *operand_string)); | |
458 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
459 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
460 | char **end_op)); | |
461 | ||
462 | #ifndef I386COFF | |
463 | static void s_bss PARAMS ((int)); | |
464 | #endif | |
465 | ||
ce8a8b2f | 466 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
252b5132 RH |
467 | |
468 | static INLINE unsigned int | |
469 | mode_from_disp_size (t) | |
470 | unsigned int t; | |
471 | { | |
3e73aa7c | 472 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; |
252b5132 RH |
473 | } |
474 | ||
475 | static INLINE int | |
476 | fits_in_signed_byte (num) | |
847f7ad4 | 477 | offsetT num; |
252b5132 RH |
478 | { |
479 | return (num >= -128) && (num <= 127); | |
47926f60 | 480 | } |
252b5132 RH |
481 | |
482 | static INLINE int | |
483 | fits_in_unsigned_byte (num) | |
847f7ad4 | 484 | offsetT num; |
252b5132 RH |
485 | { |
486 | return (num & 0xff) == num; | |
47926f60 | 487 | } |
252b5132 RH |
488 | |
489 | static INLINE int | |
490 | fits_in_unsigned_word (num) | |
847f7ad4 | 491 | offsetT num; |
252b5132 RH |
492 | { |
493 | return (num & 0xffff) == num; | |
47926f60 | 494 | } |
252b5132 RH |
495 | |
496 | static INLINE int | |
497 | fits_in_signed_word (num) | |
847f7ad4 | 498 | offsetT num; |
252b5132 RH |
499 | { |
500 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 501 | } |
3e73aa7c JH |
502 | static INLINE int |
503 | fits_in_signed_long (num) | |
504 | offsetT num ATTRIBUTE_UNUSED; | |
505 | { | |
506 | #ifndef BFD64 | |
507 | return 1; | |
508 | #else | |
509 | return (!(((offsetT) -1 << 31) & num) | |
510 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
511 | #endif | |
512 | } /* fits_in_signed_long() */ | |
513 | static INLINE int | |
514 | fits_in_unsigned_long (num) | |
515 | offsetT num ATTRIBUTE_UNUSED; | |
516 | { | |
517 | #ifndef BFD64 | |
518 | return 1; | |
519 | #else | |
520 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
521 | #endif | |
522 | } /* fits_in_unsigned_long() */ | |
252b5132 RH |
523 | |
524 | static int | |
525 | smallest_imm_type (num) | |
847f7ad4 | 526 | offsetT num; |
252b5132 | 527 | { |
3e73aa7c JH |
528 | if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64) |
529 | && !(cpu_arch_flags & (CpuUnknown))) | |
e413e4e9 AM |
530 | { |
531 | /* This code is disabled on the 486 because all the Imm1 forms | |
532 | in the opcode table are slower on the i486. They're the | |
533 | versions with the implicitly specified single-position | |
534 | displacement, which has another syntax if you really want to | |
535 | use that form. */ | |
536 | if (num == 1) | |
3e73aa7c | 537 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; |
e413e4e9 | 538 | } |
252b5132 | 539 | return (fits_in_signed_byte (num) |
3e73aa7c | 540 | ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 541 | : fits_in_unsigned_byte (num) |
3e73aa7c | 542 | ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 543 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
3e73aa7c JH |
544 | ? (Imm16 | Imm32 | Imm32S | Imm64) |
545 | : fits_in_signed_long (num) | |
546 | ? (Imm32 | Imm32S | Imm64) | |
547 | : fits_in_unsigned_long (num) | |
548 | ? (Imm32 | Imm64) | |
549 | : Imm64); | |
47926f60 | 550 | } |
252b5132 | 551 | |
847f7ad4 AM |
552 | static offsetT |
553 | offset_in_range (val, size) | |
554 | offsetT val; | |
555 | int size; | |
556 | { | |
508866be | 557 | addressT mask; |
ba2adb93 | 558 | |
847f7ad4 AM |
559 | switch (size) |
560 | { | |
508866be L |
561 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
562 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 563 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
564 | #ifdef BFD64 |
565 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
566 | #endif | |
47926f60 | 567 | default: abort (); |
847f7ad4 AM |
568 | } |
569 | ||
ba2adb93 | 570 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
571 | if (!use_rela_relocations) |
572 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
573 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 574 | |
47926f60 | 575 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
576 | { |
577 | char buf1[40], buf2[40]; | |
578 | ||
579 | sprint_value (buf1, val); | |
580 | sprint_value (buf2, val & mask); | |
581 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
582 | } | |
583 | return val & mask; | |
584 | } | |
585 | ||
252b5132 RH |
586 | /* Returns 0 if attempting to add a prefix where one from the same |
587 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
588 | added. */ | |
589 | static int | |
590 | add_prefix (prefix) | |
591 | unsigned int prefix; | |
592 | { | |
593 | int ret = 1; | |
594 | int q; | |
595 | ||
3e73aa7c JH |
596 | if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT) |
597 | q = REX_PREFIX; | |
598 | else | |
599 | switch (prefix) | |
600 | { | |
601 | default: | |
602 | abort (); | |
603 | ||
604 | case CS_PREFIX_OPCODE: | |
605 | case DS_PREFIX_OPCODE: | |
606 | case ES_PREFIX_OPCODE: | |
607 | case FS_PREFIX_OPCODE: | |
608 | case GS_PREFIX_OPCODE: | |
609 | case SS_PREFIX_OPCODE: | |
610 | q = SEG_PREFIX; | |
611 | break; | |
252b5132 | 612 | |
3e73aa7c JH |
613 | case REPNE_PREFIX_OPCODE: |
614 | case REPE_PREFIX_OPCODE: | |
615 | ret = 2; | |
616 | /* fall thru */ | |
617 | case LOCK_PREFIX_OPCODE: | |
618 | q = LOCKREP_PREFIX; | |
619 | break; | |
252b5132 | 620 | |
3e73aa7c JH |
621 | case FWAIT_OPCODE: |
622 | q = WAIT_PREFIX; | |
623 | break; | |
252b5132 | 624 | |
3e73aa7c JH |
625 | case ADDR_PREFIX_OPCODE: |
626 | q = ADDR_PREFIX; | |
627 | break; | |
252b5132 | 628 | |
3e73aa7c JH |
629 | case DATA_PREFIX_OPCODE: |
630 | q = DATA_PREFIX; | |
631 | break; | |
632 | } | |
252b5132 RH |
633 | |
634 | if (i.prefix[q]) | |
635 | { | |
636 | as_bad (_("same type of prefix used twice")); | |
637 | return 0; | |
638 | } | |
639 | ||
640 | i.prefixes += 1; | |
641 | i.prefix[q] = prefix; | |
642 | return ret; | |
643 | } | |
644 | ||
645 | static void | |
3e73aa7c | 646 | set_code_flag (value) |
e5cb08ac | 647 | int value; |
eecb386c | 648 | { |
3e73aa7c JH |
649 | flag_code = value; |
650 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
651 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
652 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) | |
653 | { | |
654 | as_bad (_("64bit mode not supported on this CPU.")); | |
655 | } | |
656 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) | |
657 | { | |
658 | as_bad (_("32bit mode not supported on this CPU.")); | |
659 | } | |
eecb386c AM |
660 | stackop_size = '\0'; |
661 | } | |
662 | ||
663 | static void | |
3e73aa7c JH |
664 | set_16bit_gcc_code_flag (new_code_flag) |
665 | int new_code_flag; | |
252b5132 | 666 | { |
3e73aa7c JH |
667 | flag_code = new_code_flag; |
668 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
669 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
670 | stackop_size = 'l'; | |
252b5132 RH |
671 | } |
672 | ||
673 | static void | |
674 | set_intel_syntax (syntax_flag) | |
eecb386c | 675 | int syntax_flag; |
252b5132 RH |
676 | { |
677 | /* Find out if register prefixing is specified. */ | |
678 | int ask_naked_reg = 0; | |
679 | ||
680 | SKIP_WHITESPACE (); | |
681 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
682 | { | |
683 | char *string = input_line_pointer; | |
684 | int e = get_symbol_end (); | |
685 | ||
47926f60 | 686 | if (strcmp (string, "prefix") == 0) |
252b5132 | 687 | ask_naked_reg = 1; |
47926f60 | 688 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
689 | ask_naked_reg = -1; |
690 | else | |
d0b47220 | 691 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
692 | *input_line_pointer = e; |
693 | } | |
694 | demand_empty_rest_of_line (); | |
c3332e24 | 695 | |
252b5132 RH |
696 | intel_syntax = syntax_flag; |
697 | ||
698 | if (ask_naked_reg == 0) | |
699 | { | |
700 | #ifdef BFD_ASSEMBLER | |
701 | allow_naked_reg = (intel_syntax | |
24eab124 | 702 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 | 703 | #else |
47926f60 KH |
704 | /* Conservative default. */ |
705 | allow_naked_reg = 0; | |
252b5132 RH |
706 | #endif |
707 | } | |
708 | else | |
709 | allow_naked_reg = (ask_naked_reg < 0); | |
710 | } | |
711 | ||
e413e4e9 AM |
712 | static void |
713 | set_cpu_arch (dummy) | |
47926f60 | 714 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 715 | { |
47926f60 | 716 | SKIP_WHITESPACE (); |
e413e4e9 AM |
717 | |
718 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
719 | { | |
720 | char *string = input_line_pointer; | |
721 | int e = get_symbol_end (); | |
722 | int i; | |
723 | ||
724 | for (i = 0; cpu_arch[i].name; i++) | |
725 | { | |
726 | if (strcmp (string, cpu_arch[i].name) == 0) | |
727 | { | |
728 | cpu_arch_name = cpu_arch[i].name; | |
3e73aa7c | 729 | cpu_arch_flags = cpu_arch[i].flags | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); |
e413e4e9 AM |
730 | break; |
731 | } | |
732 | } | |
733 | if (!cpu_arch[i].name) | |
734 | as_bad (_("no such architecture: `%s'"), string); | |
735 | ||
736 | *input_line_pointer = e; | |
737 | } | |
738 | else | |
739 | as_bad (_("missing cpu architecture")); | |
740 | ||
741 | demand_empty_rest_of_line (); | |
742 | } | |
743 | ||
252b5132 RH |
744 | const pseudo_typeS md_pseudo_table[] = |
745 | { | |
252b5132 RH |
746 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
747 | {"align", s_align_bytes, 0}, | |
748 | #else | |
749 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
750 | #endif |
751 | {"arch", set_cpu_arch, 0}, | |
752 | #ifndef I386COFF | |
753 | {"bss", s_bss, 0}, | |
252b5132 RH |
754 | #endif |
755 | {"ffloat", float_cons, 'f'}, | |
756 | {"dfloat", float_cons, 'd'}, | |
757 | {"tfloat", float_cons, 'x'}, | |
758 | {"value", cons, 2}, | |
759 | {"noopt", s_ignore, 0}, | |
760 | {"optim", s_ignore, 0}, | |
3e73aa7c JH |
761 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, |
762 | {"code16", set_code_flag, CODE_16BIT}, | |
763 | {"code32", set_code_flag, CODE_32BIT}, | |
764 | {"code64", set_code_flag, CODE_64BIT}, | |
252b5132 RH |
765 | {"intel_syntax", set_intel_syntax, 1}, |
766 | {"att_syntax", set_intel_syntax, 0}, | |
316e2c05 RH |
767 | {"file", dwarf2_directive_file, 0}, |
768 | {"loc", dwarf2_directive_loc, 0}, | |
252b5132 RH |
769 | {0, 0, 0} |
770 | }; | |
771 | ||
47926f60 | 772 | /* For interface with expression (). */ |
252b5132 RH |
773 | extern char *input_line_pointer; |
774 | ||
47926f60 | 775 | /* Hash table for instruction mnemonic lookup. */ |
252b5132 | 776 | static struct hash_control *op_hash; |
47926f60 KH |
777 | |
778 | /* Hash table for register lookup. */ | |
252b5132 RH |
779 | static struct hash_control *reg_hash; |
780 | \f | |
b9d79e03 JH |
781 | #ifdef BFD_ASSEMBLER |
782 | unsigned long | |
783 | i386_mach () | |
784 | { | |
785 | if (!strcmp (default_arch, "x86_64")) | |
786 | return bfd_mach_x86_64; | |
787 | else if (!strcmp (default_arch, "i386")) | |
788 | return bfd_mach_i386_i386; | |
789 | else | |
790 | as_fatal (_("Unknown architecture")); | |
791 | } | |
792 | #endif | |
793 | \f | |
252b5132 RH |
794 | void |
795 | md_begin () | |
796 | { | |
797 | const char *hash_err; | |
798 | ||
47926f60 | 799 | /* Initialize op_hash hash table. */ |
252b5132 RH |
800 | op_hash = hash_new (); |
801 | ||
802 | { | |
803 | register const template *optab; | |
804 | register templates *core_optab; | |
805 | ||
47926f60 KH |
806 | /* Setup for loop. */ |
807 | optab = i386_optab; | |
252b5132 RH |
808 | core_optab = (templates *) xmalloc (sizeof (templates)); |
809 | core_optab->start = optab; | |
810 | ||
811 | while (1) | |
812 | { | |
813 | ++optab; | |
814 | if (optab->name == NULL | |
815 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
816 | { | |
817 | /* different name --> ship out current template list; | |
47926f60 | 818 | add to hash table; & begin anew. */ |
252b5132 RH |
819 | core_optab->end = optab; |
820 | hash_err = hash_insert (op_hash, | |
821 | (optab - 1)->name, | |
822 | (PTR) core_optab); | |
823 | if (hash_err) | |
824 | { | |
252b5132 RH |
825 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
826 | (optab - 1)->name, | |
827 | hash_err); | |
828 | } | |
829 | if (optab->name == NULL) | |
830 | break; | |
831 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
832 | core_optab->start = optab; | |
833 | } | |
834 | } | |
835 | } | |
836 | ||
47926f60 | 837 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
838 | reg_hash = hash_new (); |
839 | { | |
840 | register const reg_entry *regtab; | |
841 | ||
842 | for (regtab = i386_regtab; | |
843 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
844 | regtab++) | |
845 | { | |
846 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
847 | if (hash_err) | |
3e73aa7c JH |
848 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
849 | regtab->reg_name, | |
850 | hash_err); | |
252b5132 RH |
851 | } |
852 | } | |
853 | ||
47926f60 | 854 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 RH |
855 | { |
856 | register int c; | |
857 | register char *p; | |
858 | ||
859 | for (c = 0; c < 256; c++) | |
860 | { | |
861 | if (isdigit (c)) | |
862 | { | |
863 | digit_chars[c] = c; | |
864 | mnemonic_chars[c] = c; | |
865 | register_chars[c] = c; | |
866 | operand_chars[c] = c; | |
867 | } | |
868 | else if (islower (c)) | |
869 | { | |
870 | mnemonic_chars[c] = c; | |
871 | register_chars[c] = c; | |
872 | operand_chars[c] = c; | |
873 | } | |
874 | else if (isupper (c)) | |
875 | { | |
876 | mnemonic_chars[c] = tolower (c); | |
877 | register_chars[c] = mnemonic_chars[c]; | |
878 | operand_chars[c] = c; | |
879 | } | |
880 | ||
881 | if (isalpha (c) || isdigit (c)) | |
882 | identifier_chars[c] = c; | |
883 | else if (c >= 128) | |
884 | { | |
885 | identifier_chars[c] = c; | |
886 | operand_chars[c] = c; | |
887 | } | |
888 | } | |
889 | ||
890 | #ifdef LEX_AT | |
891 | identifier_chars['@'] = '@'; | |
892 | #endif | |
252b5132 RH |
893 | digit_chars['-'] = '-'; |
894 | identifier_chars['_'] = '_'; | |
895 | identifier_chars['.'] = '.'; | |
896 | ||
897 | for (p = operand_special_chars; *p != '\0'; p++) | |
898 | operand_chars[(unsigned char) *p] = *p; | |
899 | } | |
900 | ||
901 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
902 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
903 | { | |
904 | record_alignment (text_section, 2); | |
905 | record_alignment (data_section, 2); | |
906 | record_alignment (bss_section, 2); | |
907 | } | |
908 | #endif | |
909 | } | |
910 | ||
911 | void | |
912 | i386_print_statistics (file) | |
913 | FILE *file; | |
914 | { | |
915 | hash_print_statistics (file, "i386 opcode", op_hash); | |
916 | hash_print_statistics (file, "i386 register", reg_hash); | |
917 | } | |
918 | \f | |
252b5132 RH |
919 | #ifdef DEBUG386 |
920 | ||
ce8a8b2f | 921 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
922 | static void pi PARAMS ((char *, i386_insn *)); |
923 | static void pte PARAMS ((template *)); | |
924 | static void pt PARAMS ((unsigned int)); | |
925 | static void pe PARAMS ((expressionS *)); | |
926 | static void ps PARAMS ((symbolS *)); | |
927 | ||
928 | static void | |
929 | pi (line, x) | |
930 | char *line; | |
931 | i386_insn *x; | |
932 | { | |
09f131f2 | 933 | unsigned int i; |
252b5132 RH |
934 | |
935 | fprintf (stdout, "%s: template ", line); | |
936 | pte (&x->tm); | |
09f131f2 JH |
937 | fprintf (stdout, " address: base %s index %s scale %x\n", |
938 | x->base_reg ? x->base_reg->reg_name : "none", | |
939 | x->index_reg ? x->index_reg->reg_name : "none", | |
940 | x->log2_scale_factor); | |
941 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 942 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
943 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
944 | x->sib.base, x->sib.index, x->sib.scale); | |
945 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
946 | x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ); | |
252b5132 RH |
947 | for (i = 0; i < x->operands; i++) |
948 | { | |
949 | fprintf (stdout, " #%d: ", i + 1); | |
950 | pt (x->types[i]); | |
951 | fprintf (stdout, "\n"); | |
952 | if (x->types[i] | |
3f4438ab | 953 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 954 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 955 | if (x->types[i] & Imm) |
520dc8e8 | 956 | pe (x->op[i].imms); |
252b5132 | 957 | if (x->types[i] & Disp) |
520dc8e8 | 958 | pe (x->op[i].disps); |
252b5132 RH |
959 | } |
960 | } | |
961 | ||
962 | static void | |
963 | pte (t) | |
964 | template *t; | |
965 | { | |
09f131f2 | 966 | unsigned int i; |
252b5132 | 967 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 968 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
969 | if (t->extension_opcode != None) |
970 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
971 | if (t->opcode_modifier & D) | |
972 | fprintf (stdout, "D"); | |
973 | if (t->opcode_modifier & W) | |
974 | fprintf (stdout, "W"); | |
975 | fprintf (stdout, "\n"); | |
976 | for (i = 0; i < t->operands; i++) | |
977 | { | |
978 | fprintf (stdout, " #%d type ", i + 1); | |
979 | pt (t->operand_types[i]); | |
980 | fprintf (stdout, "\n"); | |
981 | } | |
982 | } | |
983 | ||
984 | static void | |
985 | pe (e) | |
986 | expressionS *e; | |
987 | { | |
24eab124 | 988 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
989 | fprintf (stdout, " add_number %ld (%lx)\n", |
990 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
991 | if (e->X_add_symbol) |
992 | { | |
993 | fprintf (stdout, " add_symbol "); | |
994 | ps (e->X_add_symbol); | |
995 | fprintf (stdout, "\n"); | |
996 | } | |
997 | if (e->X_op_symbol) | |
998 | { | |
999 | fprintf (stdout, " op_symbol "); | |
1000 | ps (e->X_op_symbol); | |
1001 | fprintf (stdout, "\n"); | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | static void | |
1006 | ps (s) | |
1007 | symbolS *s; | |
1008 | { | |
1009 | fprintf (stdout, "%s type %s%s", | |
1010 | S_GET_NAME (s), | |
1011 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1012 | segment_name (S_GET_SEGMENT (s))); | |
1013 | } | |
1014 | ||
1015 | struct type_name | |
1016 | { | |
1017 | unsigned int mask; | |
1018 | char *tname; | |
1019 | } | |
1020 | ||
1021 | type_names[] = | |
1022 | { | |
1023 | { Reg8, "r8" }, | |
1024 | { Reg16, "r16" }, | |
1025 | { Reg32, "r32" }, | |
09f131f2 | 1026 | { Reg64, "r64" }, |
252b5132 RH |
1027 | { Imm8, "i8" }, |
1028 | { Imm8S, "i8s" }, | |
1029 | { Imm16, "i16" }, | |
1030 | { Imm32, "i32" }, | |
09f131f2 JH |
1031 | { Imm32S, "i32s" }, |
1032 | { Imm64, "i64" }, | |
252b5132 RH |
1033 | { Imm1, "i1" }, |
1034 | { BaseIndex, "BaseIndex" }, | |
1035 | { Disp8, "d8" }, | |
1036 | { Disp16, "d16" }, | |
1037 | { Disp32, "d32" }, | |
09f131f2 JH |
1038 | { Disp32S, "d32s" }, |
1039 | { Disp64, "d64" }, | |
252b5132 RH |
1040 | { InOutPortReg, "InOutPortReg" }, |
1041 | { ShiftCount, "ShiftCount" }, | |
1042 | { Control, "control reg" }, | |
1043 | { Test, "test reg" }, | |
1044 | { Debug, "debug reg" }, | |
1045 | { FloatReg, "FReg" }, | |
1046 | { FloatAcc, "FAcc" }, | |
1047 | { SReg2, "SReg2" }, | |
1048 | { SReg3, "SReg3" }, | |
1049 | { Acc, "Acc" }, | |
1050 | { JumpAbsolute, "Jump Absolute" }, | |
1051 | { RegMMX, "rMMX" }, | |
3f4438ab | 1052 | { RegXMM, "rXMM" }, |
252b5132 RH |
1053 | { EsSeg, "es" }, |
1054 | { 0, "" } | |
1055 | }; | |
1056 | ||
1057 | static void | |
1058 | pt (t) | |
1059 | unsigned int t; | |
1060 | { | |
1061 | register struct type_name *ty; | |
1062 | ||
09f131f2 JH |
1063 | for (ty = type_names; ty->mask; ty++) |
1064 | if (t & ty->mask) | |
1065 | fprintf (stdout, "%s, ", ty->tname); | |
252b5132 RH |
1066 | fflush (stdout); |
1067 | } | |
1068 | ||
1069 | #endif /* DEBUG386 */ | |
1070 | \f | |
1071 | int | |
1072 | tc_i386_force_relocation (fixp) | |
1073 | struct fix *fixp; | |
1074 | { | |
1075 | #ifdef BFD_ASSEMBLER | |
1076 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1077 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1078 | return 1; | |
1079 | return 0; | |
1080 | #else | |
ce8a8b2f | 1081 | /* For COFF. */ |
f6af82bd | 1082 | return fixp->fx_r_type == 7; |
252b5132 RH |
1083 | #endif |
1084 | } | |
1085 | ||
1086 | #ifdef BFD_ASSEMBLER | |
252b5132 RH |
1087 | |
1088 | static bfd_reloc_code_real_type | |
3e73aa7c | 1089 | reloc (size, pcrel, sign, other) |
252b5132 RH |
1090 | int size; |
1091 | int pcrel; | |
3e73aa7c | 1092 | int sign; |
252b5132 RH |
1093 | bfd_reloc_code_real_type other; |
1094 | { | |
47926f60 KH |
1095 | if (other != NO_RELOC) |
1096 | return other; | |
252b5132 RH |
1097 | |
1098 | if (pcrel) | |
1099 | { | |
3e73aa7c | 1100 | if (!sign) |
e5cb08ac | 1101 | as_bad (_("There are no unsigned pc-relative relocations")); |
252b5132 RH |
1102 | switch (size) |
1103 | { | |
1104 | case 1: return BFD_RELOC_8_PCREL; | |
1105 | case 2: return BFD_RELOC_16_PCREL; | |
1106 | case 4: return BFD_RELOC_32_PCREL; | |
1107 | } | |
d0b47220 | 1108 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1109 | } |
1110 | else | |
1111 | { | |
3e73aa7c | 1112 | if (sign) |
e5cb08ac | 1113 | switch (size) |
3e73aa7c JH |
1114 | { |
1115 | case 4: return BFD_RELOC_X86_64_32S; | |
1116 | } | |
1117 | else | |
1118 | switch (size) | |
1119 | { | |
1120 | case 1: return BFD_RELOC_8; | |
1121 | case 2: return BFD_RELOC_16; | |
1122 | case 4: return BFD_RELOC_32; | |
1123 | case 8: return BFD_RELOC_64; | |
1124 | } | |
1125 | as_bad (_("can not do %s %d byte relocation"), | |
1126 | sign ? "signed" : "unsigned", size); | |
252b5132 RH |
1127 | } |
1128 | ||
bfb32b52 | 1129 | abort (); |
252b5132 RH |
1130 | return BFD_RELOC_NONE; |
1131 | } | |
1132 | ||
47926f60 KH |
1133 | /* Here we decide which fixups can be adjusted to make them relative to |
1134 | the beginning of the section instead of the symbol. Basically we need | |
1135 | to make sure that the dynamic relocations are done correctly, so in | |
1136 | some cases we force the original symbol to be used. */ | |
1137 | ||
252b5132 | 1138 | int |
c0c949c7 | 1139 | tc_i386_fix_adjustable (fixP) |
47926f60 | 1140 | fixS *fixP; |
252b5132 | 1141 | { |
6d249963 | 1142 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
79d292aa ILT |
1143 | /* Prevent all adjustments to global symbols, or else dynamic |
1144 | linking will not work correctly. */ | |
b98ef147 AM |
1145 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
1146 | || S_IS_WEAK (fixP->fx_addsy)) | |
252b5132 RH |
1147 | return 0; |
1148 | #endif | |
ce8a8b2f | 1149 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1150 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1151 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1152 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
3e73aa7c JH |
1153 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1154 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
252b5132 RH |
1155 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1156 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1157 | return 0; | |
1158 | return 1; | |
1159 | } | |
1160 | #else | |
ec56dfb4 L |
1161 | #define reloc(SIZE,PCREL,SIGN,OTHER) 0 |
1162 | #define BFD_RELOC_16 0 | |
1163 | #define BFD_RELOC_32 0 | |
1164 | #define BFD_RELOC_16_PCREL 0 | |
1165 | #define BFD_RELOC_32_PCREL 0 | |
1166 | #define BFD_RELOC_386_PLT32 0 | |
1167 | #define BFD_RELOC_386_GOT32 0 | |
1168 | #define BFD_RELOC_386_GOTOFF 0 | |
1169 | #define BFD_RELOC_X86_64_PLT32 0 | |
1170 | #define BFD_RELOC_X86_64_GOT32 0 | |
1171 | #define BFD_RELOC_X86_64_GOTPCREL 0 | |
252b5132 RH |
1172 | #endif |
1173 | ||
47926f60 | 1174 | static int intel_float_operand PARAMS ((char *mnemonic)); |
b4cac588 AM |
1175 | |
1176 | static int | |
252b5132 RH |
1177 | intel_float_operand (mnemonic) |
1178 | char *mnemonic; | |
1179 | { | |
47926f60 | 1180 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1181 | return 2; |
252b5132 RH |
1182 | |
1183 | if (mnemonic[0] == 'f') | |
1184 | return 1; | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1190 | machine dependent instruction. This function is supposed to emit | |
1191 | the frags/bytes it assembles to. */ | |
1192 | ||
1193 | void | |
1194 | md_assemble (line) | |
1195 | char *line; | |
1196 | { | |
47926f60 | 1197 | /* Points to template once we've found it. */ |
252b5132 RH |
1198 | const template *t; |
1199 | ||
1200 | /* Count the size of the instruction generated. */ | |
1201 | int insn_size = 0; | |
1202 | ||
1203 | int j; | |
1204 | ||
1205 | char mnemonic[MAX_MNEM_SIZE]; | |
1206 | ||
47926f60 | 1207 | /* Initialize globals. */ |
252b5132 RH |
1208 | memset (&i, '\0', sizeof (i)); |
1209 | for (j = 0; j < MAX_OPERANDS; j++) | |
1210 | i.disp_reloc[j] = NO_RELOC; | |
1211 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
1212 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1213 | save_stack_p = save_stack; |
252b5132 RH |
1214 | |
1215 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1216 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1217 | start of a (possibly prefixed) mnemonic. */ |
252b5132 RH |
1218 | { |
1219 | char *l = line; | |
1220 | char *token_start = l; | |
1221 | char *mnem_p; | |
1222 | ||
47926f60 | 1223 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
252b5132 RH |
1224 | const char *expecting_string_instruction = NULL; |
1225 | ||
1226 | while (1) | |
1227 | { | |
1228 | mnem_p = mnemonic; | |
1229 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1230 | { | |
1231 | mnem_p++; | |
1232 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1233 | { | |
e413e4e9 | 1234 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1235 | return; |
1236 | } | |
1237 | l++; | |
1238 | } | |
1239 | if (!is_space_char (*l) | |
1240 | && *l != END_OF_INSN | |
1241 | && *l != PREFIX_SEPARATOR) | |
1242 | { | |
1243 | as_bad (_("invalid character %s in mnemonic"), | |
1244 | output_invalid (*l)); | |
1245 | return; | |
1246 | } | |
1247 | if (token_start == l) | |
1248 | { | |
1249 | if (*l == PREFIX_SEPARATOR) | |
1250 | as_bad (_("expecting prefix; got nothing")); | |
1251 | else | |
1252 | as_bad (_("expecting mnemonic; got nothing")); | |
1253 | return; | |
1254 | } | |
1255 | ||
1256 | /* Look up instruction (or prefix) via hash table. */ | |
1257 | current_templates = hash_find (op_hash, mnemonic); | |
1258 | ||
1259 | if (*l != END_OF_INSN | |
1260 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1261 | && current_templates | |
1262 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1263 | { | |
1264 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1265 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1266 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1267 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
3e73aa7c | 1268 | ^ (flag_code == CODE_16BIT))) |
252b5132 RH |
1269 | { |
1270 | as_bad (_("redundant %s prefix"), | |
1271 | current_templates->start->name); | |
1272 | return; | |
1273 | } | |
1274 | /* Add prefix, checking for repeated prefixes. */ | |
1275 | switch (add_prefix (current_templates->start->base_opcode)) | |
1276 | { | |
1277 | case 0: | |
1278 | return; | |
1279 | case 2: | |
47926f60 | 1280 | expecting_string_instruction = current_templates->start->name; |
252b5132 RH |
1281 | break; |
1282 | } | |
1283 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1284 | token_start = ++l; | |
1285 | } | |
1286 | else | |
1287 | break; | |
1288 | } | |
1289 | ||
1290 | if (!current_templates) | |
1291 | { | |
24eab124 | 1292 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1293 | switch (mnem_p[-1]) |
1294 | { | |
252b5132 RH |
1295 | case WORD_MNEM_SUFFIX: |
1296 | case BYTE_MNEM_SUFFIX: | |
3e73aa7c | 1297 | case QWORD_MNEM_SUFFIX: |
252b5132 RH |
1298 | i.suffix = mnem_p[-1]; |
1299 | mnem_p[-1] = '\0'; | |
1300 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1301 | break; |
f16b83df JH |
1302 | case SHORT_MNEM_SUFFIX: |
1303 | case LONG_MNEM_SUFFIX: | |
1304 | if (!intel_syntax) | |
1305 | { | |
1306 | i.suffix = mnem_p[-1]; | |
1307 | mnem_p[-1] = '\0'; | |
1308 | current_templates = hash_find (op_hash, mnemonic); | |
1309 | } | |
1310 | break; | |
24eab124 | 1311 | |
ce8a8b2f | 1312 | /* Intel Syntax. */ |
f16b83df | 1313 | case 'd': |
24eab124 AM |
1314 | if (intel_syntax) |
1315 | { | |
f16b83df JH |
1316 | if (intel_float_operand (mnemonic)) |
1317 | i.suffix = SHORT_MNEM_SUFFIX; | |
1318 | else | |
1319 | i.suffix = LONG_MNEM_SUFFIX; | |
24eab124 AM |
1320 | mnem_p[-1] = '\0'; |
1321 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1322 | } |
f16b83df | 1323 | break; |
252b5132 RH |
1324 | } |
1325 | if (!current_templates) | |
1326 | { | |
e413e4e9 | 1327 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1328 | return; |
1329 | } | |
1330 | } | |
1331 | ||
e413e4e9 AM |
1332 | /* Check if instruction is supported on specified architecture. */ |
1333 | if (cpu_arch_flags != 0) | |
1334 | { | |
3e73aa7c JH |
1335 | if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) |
1336 | & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) | |
e413e4e9 AM |
1337 | { |
1338 | as_warn (_("`%s' is not supported on `%s'"), | |
1339 | current_templates->start->name, cpu_arch_name); | |
1340 | } | |
3e73aa7c | 1341 | else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) |
e413e4e9 AM |
1342 | { |
1343 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1344 | } | |
1345 | } | |
1346 | ||
ce8a8b2f | 1347 | /* Check for rep/repne without a string instruction. */ |
252b5132 RH |
1348 | if (expecting_string_instruction |
1349 | && !(current_templates->start->opcode_modifier & IsString)) | |
1350 | { | |
1351 | as_bad (_("expecting string instruction after `%s'"), | |
1352 | expecting_string_instruction); | |
1353 | return; | |
1354 | } | |
1355 | ||
47926f60 | 1356 | /* There may be operands to parse. */ |
252b5132 RH |
1357 | if (*l != END_OF_INSN) |
1358 | { | |
47926f60 | 1359 | /* 1 if operand is pending after ','. */ |
252b5132 RH |
1360 | unsigned int expecting_operand = 0; |
1361 | ||
47926f60 | 1362 | /* Non-zero if operand parens not balanced. */ |
252b5132 RH |
1363 | unsigned int paren_not_balanced; |
1364 | ||
1365 | do | |
1366 | { | |
ce8a8b2f | 1367 | /* Skip optional white space before operand. */ |
252b5132 RH |
1368 | if (is_space_char (*l)) |
1369 | ++l; | |
1370 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1371 | { | |
1372 | as_bad (_("invalid character %s before operand %d"), | |
1373 | output_invalid (*l), | |
1374 | i.operands + 1); | |
1375 | return; | |
1376 | } | |
1377 | token_start = l; /* after white space */ | |
1378 | paren_not_balanced = 0; | |
1379 | while (paren_not_balanced || *l != ',') | |
1380 | { | |
1381 | if (*l == END_OF_INSN) | |
1382 | { | |
1383 | if (paren_not_balanced) | |
1384 | { | |
24eab124 | 1385 | if (!intel_syntax) |
252b5132 RH |
1386 | as_bad (_("unbalanced parenthesis in operand %d."), |
1387 | i.operands + 1); | |
24eab124 | 1388 | else |
252b5132 RH |
1389 | as_bad (_("unbalanced brackets in operand %d."), |
1390 | i.operands + 1); | |
1391 | return; | |
1392 | } | |
1393 | else | |
1394 | break; /* we are done */ | |
1395 | } | |
1396 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1397 | { | |
1398 | as_bad (_("invalid character %s in operand %d"), | |
1399 | output_invalid (*l), | |
1400 | i.operands + 1); | |
1401 | return; | |
1402 | } | |
24eab124 AM |
1403 | if (!intel_syntax) |
1404 | { | |
252b5132 RH |
1405 | if (*l == '(') |
1406 | ++paren_not_balanced; | |
1407 | if (*l == ')') | |
1408 | --paren_not_balanced; | |
24eab124 AM |
1409 | } |
1410 | else | |
1411 | { | |
252b5132 RH |
1412 | if (*l == '[') |
1413 | ++paren_not_balanced; | |
1414 | if (*l == ']') | |
1415 | --paren_not_balanced; | |
24eab124 | 1416 | } |
252b5132 RH |
1417 | l++; |
1418 | } | |
1419 | if (l != token_start) | |
47926f60 | 1420 | { /* Yes, we've read in another operand. */ |
252b5132 RH |
1421 | unsigned int operand_ok; |
1422 | this_operand = i.operands++; | |
1423 | if (i.operands > MAX_OPERANDS) | |
1424 | { | |
1425 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1426 | MAX_OPERANDS); | |
1427 | return; | |
1428 | } | |
47926f60 | 1429 | /* Now parse operand adding info to 'i' as we go along. */ |
252b5132 RH |
1430 | END_STRING_AND_SAVE (l); |
1431 | ||
24eab124 | 1432 | if (intel_syntax) |
47926f60 KH |
1433 | operand_ok = |
1434 | i386_intel_operand (token_start, | |
1435 | intel_float_operand (mnemonic)); | |
24eab124 AM |
1436 | else |
1437 | operand_ok = i386_operand (token_start); | |
252b5132 | 1438 | |
ce8a8b2f | 1439 | RESTORE_END_STRING (l); |
252b5132 RH |
1440 | if (!operand_ok) |
1441 | return; | |
1442 | } | |
1443 | else | |
1444 | { | |
1445 | if (expecting_operand) | |
1446 | { | |
1447 | expecting_operand_after_comma: | |
1448 | as_bad (_("expecting operand after ','; got nothing")); | |
1449 | return; | |
1450 | } | |
1451 | if (*l == ',') | |
1452 | { | |
1453 | as_bad (_("expecting operand before ','; got nothing")); | |
1454 | return; | |
1455 | } | |
1456 | } | |
1457 | ||
ce8a8b2f | 1458 | /* Now *l must be either ',' or END_OF_INSN. */ |
252b5132 RH |
1459 | if (*l == ',') |
1460 | { | |
1461 | if (*++l == END_OF_INSN) | |
ce8a8b2f AM |
1462 | { |
1463 | /* Just skip it, if it's \n complain. */ | |
252b5132 RH |
1464 | goto expecting_operand_after_comma; |
1465 | } | |
1466 | expecting_operand = 1; | |
1467 | } | |
1468 | } | |
ce8a8b2f | 1469 | while (*l != END_OF_INSN); |
252b5132 RH |
1470 | } |
1471 | } | |
1472 | ||
1473 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1474 | operands at hand. | |
1475 | ||
1476 | Next, we find a template that matches the given insn, | |
1477 | making sure the overlap of the given operands types is consistent | |
47926f60 | 1478 | with the template operand types. */ |
252b5132 RH |
1479 | |
1480 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1481 | ((overlap & ~JumpAbsolute) \ |
1482 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1483 | |
1484 | /* If given types r0 and r1 are registers they must be of the same type | |
1485 | unless the expected operand type register overlap is null. | |
1486 | Note that Acc in a template matches every size of reg. */ | |
1487 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1488 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1489 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1490 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1491 | ||
1492 | { | |
1493 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1494 | unsigned int overlap2; |
1495 | unsigned int found_reverse_match; | |
1496 | int suffix_check; | |
1497 | ||
cc5ca5ce AM |
1498 | /* All intel opcodes have reversed operands except for "bound" and |
1499 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1500 | instructions with 2 immediate operands so that the immediate segment | |
1501 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1502 | intersegment "jmp" and "call" instructions are the only ones that | |
1503 | have two immediate operands. */ | |
520dc8e8 | 1504 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1505 | && (strcmp (mnemonic, "bound") != 0) |
1506 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1507 | { |
520dc8e8 | 1508 | union i386_op temp_op; |
24eab124 | 1509 | unsigned int temp_type; |
76a0ddac | 1510 | #ifdef BFD_ASSEMBLER |
3e73aa7c | 1511 | enum bfd_reloc_code_real temp_reloc; |
76a0ddac | 1512 | #else |
3e73aa7c | 1513 | int temp_reloc; |
76a0ddac | 1514 | #endif |
24eab124 | 1515 | int xchg1 = 0; |
ab9da554 | 1516 | int xchg2 = 0; |
252b5132 | 1517 | |
24eab124 AM |
1518 | if (i.operands == 2) |
1519 | { | |
1520 | xchg1 = 0; | |
1521 | xchg2 = 1; | |
1522 | } | |
1523 | else if (i.operands == 3) | |
1524 | { | |
1525 | xchg1 = 0; | |
1526 | xchg2 = 2; | |
1527 | } | |
520dc8e8 AM |
1528 | temp_type = i.types[xchg2]; |
1529 | i.types[xchg2] = i.types[xchg1]; | |
1530 | i.types[xchg1] = temp_type; | |
1531 | temp_op = i.op[xchg2]; | |
1532 | i.op[xchg2] = i.op[xchg1]; | |
1533 | i.op[xchg1] = temp_op; | |
3e73aa7c | 1534 | temp_reloc = i.disp_reloc[xchg2]; |
76a0ddac | 1535 | i.disp_reloc[xchg2] = i.disp_reloc[xchg1]; |
3e73aa7c | 1536 | i.disp_reloc[xchg1] = temp_reloc; |
36bf8ab9 AM |
1537 | |
1538 | if (i.mem_operands == 2) | |
1539 | { | |
1540 | const seg_entry *temp_seg; | |
1541 | temp_seg = i.seg[0]; | |
1542 | i.seg[0] = i.seg[1]; | |
1543 | i.seg[1] = temp_seg; | |
1544 | } | |
24eab124 | 1545 | } |
773f551c AM |
1546 | |
1547 | if (i.imm_operands) | |
1548 | { | |
1549 | /* Try to ensure constant immediates are represented in the smallest | |
1550 | opcode possible. */ | |
1551 | char guess_suffix = 0; | |
1552 | int op; | |
1553 | ||
1554 | if (i.suffix) | |
1555 | guess_suffix = i.suffix; | |
1556 | else if (i.reg_operands) | |
1557 | { | |
1558 | /* Figure out a suffix from the last register operand specified. | |
1559 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1560 | but the following works for instructions with immediates. | |
1561 | In any case, we can't set i.suffix yet. */ | |
47926f60 | 1562 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1563 | if (i.types[op] & Reg) |
1564 | { | |
1565 | if (i.types[op] & Reg8) | |
1566 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1567 | else if (i.types[op] & Reg16) | |
1568 | guess_suffix = WORD_MNEM_SUFFIX; | |
3e73aa7c JH |
1569 | else if (i.types[op] & Reg32) |
1570 | guess_suffix = LONG_MNEM_SUFFIX; | |
1571 | else if (i.types[op] & Reg64) | |
1572 | guess_suffix = QWORD_MNEM_SUFFIX; | |
773f551c AM |
1573 | break; |
1574 | } | |
1575 | } | |
3e73aa7c | 1576 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
726c5dcd AM |
1577 | guess_suffix = WORD_MNEM_SUFFIX; |
1578 | ||
47926f60 | 1579 | for (op = i.operands; --op >= 0;) |
3e73aa7c | 1580 | if (i.types[op] & Imm) |
773f551c | 1581 | { |
3e73aa7c | 1582 | switch (i.op[op].imms->X_op) |
e5cb08ac | 1583 | { |
3e73aa7c JH |
1584 | case O_constant: |
1585 | /* If a suffix is given, this operand may be shortened. */ | |
1586 | switch (guess_suffix) | |
1587 | { | |
1588 | case LONG_MNEM_SUFFIX: | |
1589 | i.types[op] |= Imm32 | Imm64; | |
1590 | break; | |
1591 | case WORD_MNEM_SUFFIX: | |
1592 | i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; | |
1593 | break; | |
1594 | case BYTE_MNEM_SUFFIX: | |
1595 | i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; | |
1596 | break; | |
1597 | } | |
773f551c | 1598 | |
e5cb08ac KH |
1599 | /* If this operand is at most 16 bits, convert it |
1600 | to a signed 16 bit number before trying to see | |
1601 | whether it will fit in an even smaller size. | |
1602 | This allows a 16-bit operand such as $0xffe0 to | |
1603 | be recognised as within Imm8S range. */ | |
3e73aa7c | 1604 | if ((i.types[op] & Imm16) |
e5cb08ac | 1605 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
3e73aa7c JH |
1606 | { |
1607 | i.op[op].imms->X_add_number = | |
1608 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1609 | } | |
1610 | if ((i.types[op] & Imm32) | |
1611 | && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0) | |
1612 | { | |
1613 | i.op[op].imms->X_add_number = | |
1614 | (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
1615 | } | |
1616 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); | |
1617 | /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */ | |
1618 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
1619 | i.types[op] &= ~Imm32; | |
1620 | break; | |
1621 | case O_absent: | |
1622 | case O_register: | |
bfb32b52 | 1623 | abort (); |
3e73aa7c JH |
1624 | /* Symbols and expressions. */ |
1625 | default: | |
1626 | /* Convert symbolic operand to proper sizes for matching. */ | |
1627 | switch (guess_suffix) | |
1628 | { | |
1629 | case QWORD_MNEM_SUFFIX: | |
1630 | i.types[op] = Imm64 | Imm32S; | |
1631 | break; | |
1632 | case LONG_MNEM_SUFFIX: | |
1633 | i.types[op] = Imm32 | Imm64; | |
1634 | break; | |
1635 | case WORD_MNEM_SUFFIX: | |
1636 | i.types[op] = Imm16 | Imm32 | Imm64; | |
1637 | break; | |
1638 | break; | |
1639 | case BYTE_MNEM_SUFFIX: | |
1640 | i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32; | |
1641 | break; | |
1642 | break; | |
1643 | } | |
1644 | break; | |
773f551c | 1645 | } |
773f551c AM |
1646 | } |
1647 | } | |
1648 | ||
45288df1 AM |
1649 | if (i.disp_operands) |
1650 | { | |
1651 | /* Try to use the smallest displacement type too. */ | |
1652 | int op; | |
1653 | ||
47926f60 | 1654 | for (op = i.operands; --op >= 0;) |
45288df1 AM |
1655 | if ((i.types[op] & Disp) |
1656 | && i.op[op].imms->X_op == O_constant) | |
1657 | { | |
1658 | offsetT disp = i.op[op].disps->X_add_number; | |
1659 | ||
1660 | if (i.types[op] & Disp16) | |
1661 | { | |
1662 | /* We know this operand is at most 16 bits, so | |
1663 | convert to a signed 16 bit number before trying | |
1664 | to see whether it will fit in an even smaller | |
1665 | size. */ | |
47926f60 | 1666 | |
45288df1 AM |
1667 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
1668 | } | |
3e73aa7c JH |
1669 | else if (i.types[op] & Disp32) |
1670 | { | |
1671 | /* We know this operand is at most 32 bits, so convert to a | |
1672 | signed 32 bit number before trying to see whether it will | |
1673 | fit in an even smaller size. */ | |
1674 | disp &= (((offsetT) 2 << 31) - 1); | |
1675 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
1676 | } | |
1677 | if (flag_code == CODE_64BIT) | |
1678 | { | |
1679 | if (fits_in_signed_long (disp)) | |
1680 | i.types[op] |= Disp32S; | |
1681 | if (fits_in_unsigned_long (disp)) | |
1682 | i.types[op] |= Disp32; | |
1683 | } | |
1684 | if ((i.types[op] & (Disp32 | Disp32S | Disp16)) | |
1685 | && fits_in_signed_byte (disp)) | |
45288df1 AM |
1686 | i.types[op] |= Disp8; |
1687 | } | |
1688 | } | |
1689 | ||
252b5132 RH |
1690 | overlap0 = 0; |
1691 | overlap1 = 0; | |
1692 | overlap2 = 0; | |
1693 | found_reverse_match = 0; | |
1694 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1695 | ? No_bSuf | |
1696 | : (i.suffix == WORD_MNEM_SUFFIX | |
1697 | ? No_wSuf | |
1698 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1699 | ? No_sSuf | |
1700 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1701 | ? No_lSuf |
3e73aa7c JH |
1702 | : (i.suffix == QWORD_MNEM_SUFFIX |
1703 | ? No_qSuf | |
1704 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
252b5132 RH |
1705 | |
1706 | for (t = current_templates->start; | |
1707 | t < current_templates->end; | |
1708 | t++) | |
1709 | { | |
47926f60 | 1710 | /* Must have right number of operands. */ |
252b5132 RH |
1711 | if (i.operands != t->operands) |
1712 | continue; | |
1713 | ||
7f3f1ea2 AM |
1714 | /* Check the suffix, except for some instructions in intel mode. */ |
1715 | if ((t->opcode_modifier & suffix_check) | |
fa2255cb DN |
1716 | && !(intel_syntax |
1717 | && (t->opcode_modifier & IgnoreSize)) | |
7f3f1ea2 AM |
1718 | && !(intel_syntax |
1719 | && t->base_opcode == 0xd9 | |
ce8a8b2f AM |
1720 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ |
1721 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1722 | continue; |
252b5132 | 1723 | |
e2914f48 | 1724 | /* Do not verify operands when there are none. */ |
252b5132 | 1725 | else if (!t->operands) |
e2914f48 JH |
1726 | { |
1727 | if (t->cpu_flags & ~cpu_arch_flags) | |
1728 | continue; | |
1729 | /* We've found a match; break out of loop. */ | |
1730 | break; | |
e5cb08ac | 1731 | } |
252b5132 RH |
1732 | |
1733 | overlap0 = i.types[0] & t->operand_types[0]; | |
1734 | switch (t->operands) | |
1735 | { | |
1736 | case 1: | |
1737 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1738 | continue; | |
1739 | break; | |
1740 | case 2: | |
1741 | case 3: | |
1742 | overlap1 = i.types[1] & t->operand_types[1]; | |
1743 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1744 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1745 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1746 | t->operand_types[0], | |
1747 | overlap1, i.types[1], | |
1748 | t->operand_types[1])) | |
1749 | { | |
47926f60 | 1750 | /* Check if other direction is valid ... */ |
252b5132 RH |
1751 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
1752 | continue; | |
1753 | ||
47926f60 | 1754 | /* Try reversing direction of operands. */ |
252b5132 RH |
1755 | overlap0 = i.types[0] & t->operand_types[1]; |
1756 | overlap1 = i.types[1] & t->operand_types[0]; | |
1757 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1758 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1759 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1760 | t->operand_types[1], | |
1761 | overlap1, i.types[1], | |
1762 | t->operand_types[0])) | |
1763 | { | |
47926f60 | 1764 | /* Does not match either direction. */ |
252b5132 RH |
1765 | continue; |
1766 | } | |
1767 | /* found_reverse_match holds which of D or FloatDR | |
1768 | we've found. */ | |
1769 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
252b5132 | 1770 | } |
47926f60 | 1771 | /* Found a forward 2 operand match here. */ |
3e73aa7c | 1772 | else if (t->operands == 3) |
252b5132 RH |
1773 | { |
1774 | /* Here we make use of the fact that there are no | |
1775 | reverse match 3 operand instructions, and all 3 | |
1776 | operand instructions only need to be checked for | |
1777 | register consistency between operands 2 and 3. */ | |
1778 | overlap2 = i.types[2] & t->operand_types[2]; | |
1779 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1780 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1781 | t->operand_types[1], | |
1782 | overlap2, i.types[2], | |
24eab124 | 1783 | t->operand_types[2])) |
252b5132 | 1784 | |
24eab124 | 1785 | continue; |
252b5132 | 1786 | } |
47926f60 | 1787 | /* Found either forward/reverse 2 or 3 operand match here: |
ce8a8b2f | 1788 | slip through to break. */ |
252b5132 | 1789 | } |
3e73aa7c JH |
1790 | if (t->cpu_flags & ~cpu_arch_flags) |
1791 | { | |
1792 | found_reverse_match = 0; | |
1793 | continue; | |
1794 | } | |
47926f60 KH |
1795 | /* We've found a match; break out of loop. */ |
1796 | break; | |
ce8a8b2f | 1797 | } |
252b5132 | 1798 | if (t == current_templates->end) |
47926f60 KH |
1799 | { |
1800 | /* We found no match. */ | |
252b5132 RH |
1801 | as_bad (_("suffix or operands invalid for `%s'"), |
1802 | current_templates->start->name); | |
1803 | return; | |
1804 | } | |
1805 | ||
a38cf1db | 1806 | if (!quiet_warnings) |
3138f287 | 1807 | { |
a38cf1db AM |
1808 | if (!intel_syntax |
1809 | && ((i.types[0] & JumpAbsolute) | |
1810 | != (t->operand_types[0] & JumpAbsolute))) | |
1811 | { | |
1812 | as_warn (_("indirect %s without `*'"), t->name); | |
1813 | } | |
3138f287 | 1814 | |
a38cf1db AM |
1815 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1816 | == (IsPrefix|IgnoreSize)) | |
1817 | { | |
1818 | /* Warn them that a data or address size prefix doesn't | |
1819 | affect assembly of the next line of code. */ | |
1820 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1821 | } | |
252b5132 RH |
1822 | } |
1823 | ||
1824 | /* Copy the template we found. */ | |
1825 | i.tm = *t; | |
1826 | if (found_reverse_match) | |
1827 | { | |
7f3f1ea2 AM |
1828 | /* If we found a reverse match we must alter the opcode |
1829 | direction bit. found_reverse_match holds bits to change | |
1830 | (different for int & float insns). */ | |
1831 | ||
1832 | i.tm.base_opcode ^= found_reverse_match; | |
1833 | ||
252b5132 RH |
1834 | i.tm.operand_types[0] = t->operand_types[1]; |
1835 | i.tm.operand_types[1] = t->operand_types[0]; | |
1836 | } | |
1837 | ||
d0b47220 | 1838 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
e5cb08ac KH |
1839 | if (SYSV386_COMPAT |
1840 | && intel_syntax | |
1841 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1842 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1843 | |
1844 | if (i.tm.opcode_modifier & FWait) | |
1845 | if (! add_prefix (FWAIT_OPCODE)) | |
1846 | return; | |
1847 | ||
ce8a8b2f | 1848 | /* Check string instruction segment overrides. */ |
252b5132 RH |
1849 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) |
1850 | { | |
1851 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1852 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1853 | { | |
1854 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1855 | { | |
1856 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1857 | i.tm.name, | |
1858 | mem_op + 1); | |
1859 | return; | |
1860 | } | |
1861 | /* There's only ever one segment override allowed per instruction. | |
1862 | This instruction possibly has a legal segment override on the | |
1863 | second operand, so copy the segment to where non-string | |
1864 | instructions store it, allowing common code. */ | |
1865 | i.seg[0] = i.seg[1]; | |
1866 | } | |
1867 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1868 | { | |
1869 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1870 | { | |
1871 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1872 | i.tm.name, | |
1873 | mem_op + 2); | |
1874 | return; | |
1875 | } | |
1876 | } | |
1877 | } | |
1878 | ||
3e73aa7c JH |
1879 | if (i.reg_operands && flag_code < CODE_64BIT) |
1880 | { | |
1881 | int op; | |
e5cb08ac | 1882 | for (op = i.operands; --op >= 0;) |
3e73aa7c JH |
1883 | if ((i.types[op] & Reg) |
1884 | && (i.op[op].regs->reg_flags & (RegRex64|RegRex))) | |
b96d3a20 JH |
1885 | { |
1886 | as_bad (_("Extended register `%%%s' available only in 64bit mode."), | |
1887 | i.op[op].regs->reg_name); | |
1888 | return; | |
1889 | } | |
3e73aa7c JH |
1890 | } |
1891 | ||
252b5132 RH |
1892 | /* If matched instruction specifies an explicit instruction mnemonic |
1893 | suffix, use it. */ | |
3e73aa7c | 1894 | if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) |
252b5132 RH |
1895 | { |
1896 | if (i.tm.opcode_modifier & Size16) | |
1897 | i.suffix = WORD_MNEM_SUFFIX; | |
3e73aa7c JH |
1898 | else if (i.tm.opcode_modifier & Size64) |
1899 | i.suffix = QWORD_MNEM_SUFFIX; | |
252b5132 | 1900 | else |
add0c677 | 1901 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1902 | } |
1903 | else if (i.reg_operands) | |
1904 | { | |
1905 | /* If there's no instruction mnemonic suffix we try to invent one | |
47926f60 | 1906 | based on register operands. */ |
252b5132 RH |
1907 | if (!i.suffix) |
1908 | { | |
1909 | /* We take i.suffix from the last register operand specified, | |
1910 | Destination register type is more significant than source | |
1911 | register type. */ | |
1912 | int op; | |
47926f60 | 1913 | for (op = i.operands; --op >= 0;) |
cc5ca5ce AM |
1914 | if ((i.types[op] & Reg) |
1915 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1916 | { |
1917 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1918 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
3e73aa7c | 1919 | (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : |
add0c677 | 1920 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1921 | break; |
1922 | } | |
1923 | } | |
1924 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1925 | { | |
1926 | int op; | |
47926f60 | 1927 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1928 | { |
1929 | /* If this is an eight bit register, it's OK. If it's | |
1930 | the 16 or 32 bit version of an eight bit register, | |
47926f60 | 1931 | we will just use the low portion, and that's OK too. */ |
252b5132 RH |
1932 | if (i.types[op] & Reg8) |
1933 | continue; | |
1934 | ||
47926f60 | 1935 | /* movzx and movsx should not generate this warning. */ |
24eab124 AM |
1936 | if (intel_syntax |
1937 | && (i.tm.base_opcode == 0xfb7 | |
1938 | || i.tm.base_opcode == 0xfb6 | |
3e73aa7c | 1939 | || i.tm.base_opcode == 0x63 |
24eab124 AM |
1940 | || i.tm.base_opcode == 0xfbe |
1941 | || i.tm.base_opcode == 0xfbf)) | |
1942 | continue; | |
252b5132 | 1943 | |
520dc8e8 | 1944 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1945 | #if 0 |
1946 | /* Check that the template allows eight bit regs | |
1947 | This kills insns such as `orb $1,%edx', which | |
1948 | maybe should be allowed. */ | |
1949 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1950 | #endif | |
1951 | ) | |
1952 | { | |
3e73aa7c JH |
1953 | /* Prohibit these changes in the 64bit mode, since |
1954 | the lowering is more complicated. */ | |
1955 | if (flag_code == CODE_64BIT | |
1956 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
1957 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
1958 | i.op[op].regs->reg_name, | |
1959 | i.suffix); | |
252b5132 | 1960 | #if REGISTER_WARNINGS |
a38cf1db AM |
1961 | if (!quiet_warnings |
1962 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 1963 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
520dc8e8 AM |
1964 | (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, |
1965 | i.op[op].regs->reg_name, | |
252b5132 RH |
1966 | i.suffix); |
1967 | #endif | |
1968 | continue; | |
1969 | } | |
ce8a8b2f | 1970 | /* Any other register is bad. */ |
3f4438ab AM |
1971 | if (i.types[op] & (Reg | RegMMX | RegXMM |
1972 | | SReg2 | SReg3 | |
1973 | | Control | Debug | Test | |
1974 | | FloatReg | FloatAcc)) | |
252b5132 RH |
1975 | { |
1976 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1977 | i.op[op].regs->reg_name, |
252b5132 RH |
1978 | i.tm.name, |
1979 | i.suffix); | |
1980 | return; | |
1981 | } | |
1982 | } | |
1983 | } | |
add0c677 | 1984 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
1985 | { |
1986 | int op; | |
47926f60 KH |
1987 | |
1988 | for (op = i.operands; --op >= 0;) | |
252b5132 RH |
1989 | /* Reject eight bit registers, except where the template |
1990 | requires them. (eg. movzb) */ | |
1991 | if ((i.types[op] & Reg8) != 0 | |
47926f60 | 1992 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) |
252b5132 RH |
1993 | { |
1994 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1995 | i.op[op].regs->reg_name, |
252b5132 RH |
1996 | i.tm.name, |
1997 | i.suffix); | |
1998 | return; | |
1999 | } | |
252b5132 | 2000 | /* Warn if the e prefix on a general reg is missing. */ |
3e73aa7c | 2001 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
a38cf1db | 2002 | && (i.types[op] & Reg16) != 0 |
252b5132 RH |
2003 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
2004 | { | |
3e73aa7c JH |
2005 | /* Prohibit these changes in the 64bit mode, since |
2006 | the lowering is more complicated. */ | |
2007 | if (flag_code == CODE_64BIT) | |
2008 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2009 | i.op[op].regs->reg_name, | |
2010 | i.suffix); | |
2011 | #if REGISTER_WARNINGS | |
2012 | else | |
2013 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2014 | (i.op[op].regs + 8)->reg_name, | |
2015 | i.op[op].regs->reg_name, | |
2016 | i.suffix); | |
252b5132 | 2017 | #endif |
3e73aa7c JH |
2018 | } |
2019 | /* Warn if the r prefix on a general reg is missing. */ | |
2020 | else if ((i.types[op] & Reg64) != 0 | |
2021 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
2022 | { | |
2023 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2024 | i.op[op].regs->reg_name, | |
2025 | i.suffix); | |
2026 | } | |
2027 | } | |
2028 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
2029 | { | |
2030 | int op; | |
3e73aa7c JH |
2031 | |
2032 | for (op = i.operands; --op >= 0; ) | |
2033 | /* Reject eight bit registers, except where the template | |
2034 | requires them. (eg. movzb) */ | |
2035 | if ((i.types[op] & Reg8) != 0 | |
2036 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
2037 | { | |
2038 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2039 | i.op[op].regs->reg_name, | |
2040 | i.tm.name, | |
2041 | i.suffix); | |
2042 | return; | |
2043 | } | |
2044 | /* Warn if the e prefix on a general reg is missing. */ | |
2045 | else if (((i.types[op] & Reg16) != 0 | |
2046 | || (i.types[op] & Reg32) != 0) | |
2047 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
2048 | { | |
2049 | /* Prohibit these changes in the 64bit mode, since | |
2050 | the lowering is more complicated. */ | |
2051 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2052 | i.op[op].regs->reg_name, | |
2053 | i.suffix); | |
2054 | } | |
252b5132 RH |
2055 | } |
2056 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
2057 | { | |
2058 | int op; | |
47926f60 | 2059 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
2060 | /* Reject eight bit registers, except where the template |
2061 | requires them. (eg. movzb) */ | |
2062 | if ((i.types[op] & Reg8) != 0 | |
2063 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
2064 | { | |
2065 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2066 | i.op[op].regs->reg_name, |
252b5132 RH |
2067 | i.tm.name, |
2068 | i.suffix); | |
2069 | return; | |
2070 | } | |
252b5132 | 2071 | /* Warn if the e prefix on a general reg is present. */ |
3e73aa7c | 2072 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
a38cf1db | 2073 | && (i.types[op] & Reg32) != 0 |
252b5132 RH |
2074 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
2075 | { | |
3e73aa7c JH |
2076 | /* Prohibit these changes in the 64bit mode, since |
2077 | the lowering is more complicated. */ | |
2078 | if (flag_code == CODE_64BIT) | |
2079 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2080 | i.op[op].regs->reg_name, | |
2081 | i.suffix); | |
2082 | else | |
2083 | #if REGISTER_WARNINGS | |
2084 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2085 | (i.op[op].regs - 8)->reg_name, | |
2086 | i.op[op].regs->reg_name, | |
2087 | i.suffix); | |
252b5132 | 2088 | #endif |
3e73aa7c | 2089 | } |
252b5132 | 2090 | } |
fa2255cb DN |
2091 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) |
2092 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
2093 | ; | |
252b5132 | 2094 | else |
47926f60 | 2095 | abort (); |
252b5132 | 2096 | } |
eecb386c AM |
2097 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
2098 | { | |
2099 | i.suffix = stackop_size; | |
2100 | } | |
252b5132 RH |
2101 | /* Make still unresolved immediate matches conform to size of immediate |
2102 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
3e73aa7c | 2103 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S)) |
252b5132 | 2104 | && overlap0 != Imm8 && overlap0 != Imm8S |
e5cb08ac | 2105 | && overlap0 != Imm16 && overlap0 != Imm32S |
b77a7acd | 2106 | && overlap0 != Imm32 && overlap0 != Imm64) |
252b5132 RH |
2107 | { |
2108 | if (i.suffix) | |
2109 | { | |
24eab124 | 2110 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
b77a7acd | 2111 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : |
3e73aa7c | 2112 | (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32))); |
252b5132 | 2113 | } |
3e73aa7c JH |
2114 | else if (overlap0 == (Imm16 | Imm32S | Imm32) |
2115 | || overlap0 == (Imm16 | Imm32) | |
2116 | || overlap0 == (Imm16 | Imm32S)) | |
252b5132 | 2117 | { |
24eab124 | 2118 | overlap0 = |
3e73aa7c | 2119 | ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S; |
252b5132 | 2120 | } |
3e73aa7c JH |
2121 | if (overlap0 != Imm8 && overlap0 != Imm8S |
2122 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2123 | && overlap0 != Imm32 && overlap0 != Imm64) | |
252b5132 RH |
2124 | { |
2125 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
2126 | return; | |
2127 | } | |
2128 | } | |
3e73aa7c | 2129 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) |
252b5132 | 2130 | && overlap1 != Imm8 && overlap1 != Imm8S |
e5cb08ac | 2131 | && overlap1 != Imm16 && overlap1 != Imm32S |
b77a7acd | 2132 | && overlap1 != Imm32 && overlap1 != Imm64) |
252b5132 RH |
2133 | { |
2134 | if (i.suffix) | |
2135 | { | |
24eab124 | 2136 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
b77a7acd AJ |
2137 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : |
2138 | (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32))); | |
252b5132 | 2139 | } |
3e73aa7c JH |
2140 | else if (overlap1 == (Imm16 | Imm32 | Imm32S) |
2141 | || overlap1 == (Imm16 | Imm32) | |
2142 | || overlap1 == (Imm16 | Imm32S)) | |
252b5132 | 2143 | { |
24eab124 | 2144 | overlap1 = |
3e73aa7c | 2145 | ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S; |
252b5132 | 2146 | } |
3e73aa7c JH |
2147 | if (overlap1 != Imm8 && overlap1 != Imm8S |
2148 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2149 | && overlap1 != Imm32 && overlap1 != Imm64) | |
252b5132 | 2150 | { |
3e73aa7c | 2151 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); |
252b5132 RH |
2152 | return; |
2153 | } | |
2154 | } | |
2155 | assert ((overlap2 & Imm) == 0); | |
2156 | ||
2157 | i.types[0] = overlap0; | |
2158 | if (overlap0 & ImplicitRegister) | |
2159 | i.reg_operands--; | |
2160 | if (overlap0 & Imm1) | |
ce8a8b2f | 2161 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 RH |
2162 | |
2163 | i.types[1] = overlap1; | |
2164 | if (overlap1 & ImplicitRegister) | |
2165 | i.reg_operands--; | |
2166 | ||
2167 | i.types[2] = overlap2; | |
2168 | if (overlap2 & ImplicitRegister) | |
2169 | i.reg_operands--; | |
2170 | ||
2171 | /* Finalize opcode. First, we change the opcode based on the operand | |
2172 | size given by i.suffix: We need not change things for byte insns. */ | |
2173 | ||
2174 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
2175 | { | |
2176 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
2177 | return; | |
2178 | } | |
2179 | ||
ce8a8b2f | 2180 | /* For movzx and movsx, need to check the register type. */ |
252b5132 | 2181 | if (intel_syntax |
24eab124 | 2182 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 2183 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
2184 | { |
2185 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 2186 | |
520dc8e8 | 2187 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
2188 | if (!add_prefix (prefix)) |
2189 | return; | |
2190 | } | |
252b5132 RH |
2191 | |
2192 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
2193 | { | |
2194 | /* It's not a byte, select word/dword operation. */ | |
2195 | if (i.tm.opcode_modifier & W) | |
2196 | { | |
2197 | if (i.tm.opcode_modifier & ShortForm) | |
2198 | i.tm.base_opcode |= 8; | |
2199 | else | |
2200 | i.tm.base_opcode |= 1; | |
2201 | } | |
2202 | /* Now select between word & dword operations via the operand | |
2203 | size prefix, except for instructions that will ignore this | |
2204 | prefix anyway. */ | |
3e73aa7c JH |
2205 | if (i.suffix != QWORD_MNEM_SUFFIX |
2206 | && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
252b5132 RH |
2207 | && !(i.tm.opcode_modifier & IgnoreSize)) |
2208 | { | |
2209 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
2210 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
2211 | prefix = ADDR_PREFIX_OPCODE; | |
2212 | ||
2213 | if (! add_prefix (prefix)) | |
2214 | return; | |
2215 | } | |
3e73aa7c JH |
2216 | |
2217 | /* Set mode64 for an operand. */ | |
2218 | if (i.suffix == QWORD_MNEM_SUFFIX | |
2219 | && !(i.tm.opcode_modifier & NoRex64)) | |
b96d3a20 | 2220 | { |
3e73aa7c | 2221 | i.rex.mode64 = 1; |
b96d3a20 JH |
2222 | if (flag_code < CODE_64BIT) |
2223 | { | |
e5cb08ac KH |
2224 | as_bad (_("64bit operations available only in 64bit modes.")); |
2225 | return; | |
b96d3a20 JH |
2226 | } |
2227 | } | |
3e73aa7c | 2228 | |
252b5132 | 2229 | /* Size floating point instruction. */ |
f16b83df | 2230 | if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
2231 | { |
2232 | if (i.tm.opcode_modifier & FloatMF) | |
2233 | i.tm.base_opcode ^= 4; | |
2234 | } | |
252b5132 RH |
2235 | } |
2236 | ||
3f4438ab | 2237 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 2238 | { |
3f4438ab AM |
2239 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
2240 | opcode suffix which is coded in the same place as an 8-bit | |
2241 | immediate field would be. Here we fake an 8-bit immediate | |
2242 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
2243 | |
2244 | expressionS *exp; | |
2245 | ||
47926f60 | 2246 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
2247 | |
2248 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2249 | i.op[i.operands].imms = exp; |
252b5132 RH |
2250 | i.types[i.operands++] = Imm8; |
2251 | exp->X_op = O_constant; | |
2252 | exp->X_add_number = i.tm.extension_opcode; | |
2253 | i.tm.extension_opcode = None; | |
2254 | } | |
2255 | ||
47926f60 | 2256 | /* For insns with operands there are more diddles to do to the opcode. */ |
252b5132 RH |
2257 | if (i.operands) |
2258 | { | |
24eab124 | 2259 | /* Default segment register this instruction will use |
252b5132 RH |
2260 | for memory accesses. 0 means unknown. |
2261 | This is only for optimizing out unnecessary segment overrides. */ | |
2262 | const seg_entry *default_seg = 0; | |
2263 | ||
252b5132 RH |
2264 | /* The imul $imm, %reg instruction is converted into |
2265 | imul $imm, %reg, %reg, and the clr %reg instruction | |
2266 | is converted into xor %reg, %reg. */ | |
2267 | if (i.tm.opcode_modifier & regKludge) | |
2268 | { | |
2269 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
47926f60 KH |
2270 | /* Pretend we saw the extra register operand. */ |
2271 | assert (i.op[first_reg_op + 1].regs == 0); | |
2272 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
2273 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
252b5132 RH |
2274 | i.reg_operands = 2; |
2275 | } | |
2276 | ||
2277 | if (i.tm.opcode_modifier & ShortForm) | |
2278 | { | |
47926f60 | 2279 | /* The register or float register operand is in operand 0 or 1. */ |
252b5132 | 2280 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
47926f60 | 2281 | /* Register goes in low 3 bits of opcode. */ |
520dc8e8 | 2282 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
3e73aa7c | 2283 | if (i.op[op].regs->reg_flags & RegRex) |
e5cb08ac | 2284 | i.rex.extZ = 1; |
a38cf1db | 2285 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
2286 | { |
2287 | /* Warn about some common errors, but press on regardless. | |
2288 | The first case can be generated by gcc (<= 2.8.1). */ | |
2289 | if (i.operands == 2) | |
2290 | { | |
47926f60 | 2291 | /* Reversed arguments on faddp, fsubp, etc. */ |
252b5132 | 2292 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, |
520dc8e8 AM |
2293 | i.op[1].regs->reg_name, |
2294 | i.op[0].regs->reg_name); | |
252b5132 RH |
2295 | } |
2296 | else | |
2297 | { | |
47926f60 | 2298 | /* Extraneous `l' suffix on fp insn. */ |
252b5132 | 2299 | as_warn (_("translating to `%s %%%s'"), i.tm.name, |
520dc8e8 | 2300 | i.op[0].regs->reg_name); |
252b5132 RH |
2301 | } |
2302 | } | |
2303 | } | |
2304 | else if (i.tm.opcode_modifier & Modrm) | |
2305 | { | |
2306 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
2307 | must be put into the modrm byte). | |
2308 | Now, we make the modrm & index base bytes based on all the | |
47926f60 | 2309 | info we've collected. */ |
252b5132 RH |
2310 | |
2311 | /* i.reg_operands MUST be the number of real register operands; | |
47926f60 | 2312 | implicit registers do not count. */ |
252b5132 RH |
2313 | if (i.reg_operands == 2) |
2314 | { | |
2315 | unsigned int source, dest; | |
2316 | source = ((i.types[0] | |
3f4438ab AM |
2317 | & (Reg | RegMMX | RegXMM |
2318 | | SReg2 | SReg3 | |
2319 | | Control | Debug | Test)) | |
252b5132 RH |
2320 | ? 0 : 1); |
2321 | dest = source + 1; | |
2322 | ||
252b5132 | 2323 | i.rm.mode = 3; |
3f4438ab AM |
2324 | /* One of the register operands will be encoded in the |
2325 | i.tm.reg field, the other in the combined i.tm.mode | |
2326 | and i.tm.regmem fields. If no form of this | |
2327 | instruction supports a memory destination operand, | |
2328 | then we assume the source operand may sometimes be | |
2329 | a memory operand and so we need to store the | |
2330 | destination in the i.rm.reg field. */ | |
2331 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 2332 | { |
520dc8e8 AM |
2333 | i.rm.reg = i.op[dest].regs->reg_num; |
2334 | i.rm.regmem = i.op[source].regs->reg_num; | |
3e73aa7c | 2335 | if (i.op[dest].regs->reg_flags & RegRex) |
e5cb08ac | 2336 | i.rex.extX = 1; |
3e73aa7c | 2337 | if (i.op[source].regs->reg_flags & RegRex) |
e5cb08ac | 2338 | i.rex.extZ = 1; |
252b5132 RH |
2339 | } |
2340 | else | |
2341 | { | |
520dc8e8 AM |
2342 | i.rm.reg = i.op[source].regs->reg_num; |
2343 | i.rm.regmem = i.op[dest].regs->reg_num; | |
3e73aa7c | 2344 | if (i.op[dest].regs->reg_flags & RegRex) |
e5cb08ac | 2345 | i.rex.extZ = 1; |
3e73aa7c | 2346 | if (i.op[source].regs->reg_flags & RegRex) |
e5cb08ac | 2347 | i.rex.extX = 1; |
252b5132 RH |
2348 | } |
2349 | } | |
2350 | else | |
47926f60 | 2351 | { /* If it's not 2 reg operands... */ |
252b5132 RH |
2352 | if (i.mem_operands) |
2353 | { | |
2354 | unsigned int fake_zero_displacement = 0; | |
2355 | unsigned int op = ((i.types[0] & AnyMem) | |
2356 | ? 0 | |
2357 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2358 | ||
2359 | default_seg = &ds; | |
2360 | ||
2361 | if (! i.base_reg) | |
2362 | { | |
2363 | i.rm.mode = 0; | |
2364 | if (! i.disp_operands) | |
2365 | fake_zero_displacement = 1; | |
2366 | if (! i.index_reg) | |
2367 | { | |
47926f60 | 2368 | /* Operand is just <disp> */ |
3e73aa7c | 2369 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) |
252b5132 RH |
2370 | { |
2371 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2372 | i.types[op] &= ~Disp; | |
2373 | i.types[op] |= Disp16; | |
2374 | } | |
3e73aa7c | 2375 | else if (flag_code != CODE_64BIT) |
252b5132 RH |
2376 | { |
2377 | i.rm.regmem = NO_BASE_REGISTER; | |
2378 | i.types[op] &= ~Disp; | |
2379 | i.types[op] |= Disp32; | |
2380 | } | |
3e73aa7c JH |
2381 | else |
2382 | { | |
e5cb08ac KH |
2383 | /* 64bit mode overwrites the 32bit |
2384 | absolute addressing by RIP relative | |
2385 | addressing and absolute addressing | |
2386 | is encoded by one of the redundant | |
2387 | SIB forms. */ | |
3e73aa7c JH |
2388 | |
2389 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2390 | i.sib.base = NO_BASE_REGISTER; | |
2391 | i.sib.index = NO_INDEX_REGISTER; | |
2392 | i.types[op] &= ~Disp; | |
2393 | i.types[op] |= Disp32S; | |
2394 | } | |
252b5132 | 2395 | } |
47926f60 | 2396 | else /* ! i.base_reg && i.index_reg */ |
252b5132 RH |
2397 | { |
2398 | i.sib.index = i.index_reg->reg_num; | |
2399 | i.sib.base = NO_BASE_REGISTER; | |
2400 | i.sib.scale = i.log2_scale_factor; | |
2401 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2402 | i.types[op] &= ~Disp; | |
3e73aa7c JH |
2403 | if (flag_code != CODE_64BIT) |
2404 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2405 | else | |
2406 | i.types[op] |= Disp32S; | |
2407 | if (i.index_reg->reg_flags & RegRex) | |
e5cb08ac | 2408 | i.rex.extY = 1; |
252b5132 RH |
2409 | } |
2410 | } | |
3e73aa7c JH |
2411 | /* RIP addressing for 64bit mode. */ |
2412 | else if (i.base_reg->reg_type == BaseIndex) | |
2413 | { | |
2414 | i.rm.regmem = NO_BASE_REGISTER; | |
2415 | i.types[op] &= ~Disp; | |
2416 | i.types[op] |= Disp32S; | |
2417 | i.flags[op] = Operand_PCrel; | |
2418 | } | |
252b5132 RH |
2419 | else if (i.base_reg->reg_type & Reg16) |
2420 | { | |
2421 | switch (i.base_reg->reg_num) | |
2422 | { | |
47926f60 | 2423 | case 3: /* (%bx) */ |
252b5132 RH |
2424 | if (! i.index_reg) |
2425 | i.rm.regmem = 7; | |
47926f60 | 2426 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
252b5132 RH |
2427 | i.rm.regmem = i.index_reg->reg_num - 6; |
2428 | break; | |
47926f60 | 2429 | case 5: /* (%bp) */ |
252b5132 RH |
2430 | default_seg = &ss; |
2431 | if (! i.index_reg) | |
2432 | { | |
2433 | i.rm.regmem = 6; | |
2434 | if ((i.types[op] & Disp) == 0) | |
2435 | { | |
47926f60 | 2436 | /* fake (%bp) into 0(%bp) */ |
252b5132 RH |
2437 | i.types[op] |= Disp8; |
2438 | fake_zero_displacement = 1; | |
2439 | } | |
2440 | } | |
47926f60 | 2441 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
252b5132 RH |
2442 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
2443 | break; | |
47926f60 | 2444 | default: /* (%si) -> 4 or (%di) -> 5 */ |
252b5132 RH |
2445 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
2446 | } | |
2447 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2448 | } | |
3e73aa7c | 2449 | else /* i.base_reg and 32/64 bit mode */ |
252b5132 | 2450 | { |
3e73aa7c JH |
2451 | if (flag_code == CODE_64BIT |
2452 | && (i.types[op] & Disp)) | |
2453 | { | |
2454 | if (i.types[op] & Disp8) | |
2455 | i.types[op] = Disp8 | Disp32S; | |
2456 | else | |
2457 | i.types[op] = Disp32S; | |
2458 | } | |
252b5132 | 2459 | i.rm.regmem = i.base_reg->reg_num; |
3e73aa7c | 2460 | if (i.base_reg->reg_flags & RegRex) |
e5cb08ac | 2461 | i.rex.extZ = 1; |
252b5132 | 2462 | i.sib.base = i.base_reg->reg_num; |
3e73aa7c JH |
2463 | /* x86-64 ignores REX prefix bit here to avoid |
2464 | decoder complications. */ | |
2465 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
252b5132 RH |
2466 | { |
2467 | default_seg = &ss; | |
2468 | if (i.disp_operands == 0) | |
2469 | { | |
2470 | fake_zero_displacement = 1; | |
2471 | i.types[op] |= Disp8; | |
2472 | } | |
2473 | } | |
2474 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2475 | { | |
2476 | default_seg = &ss; | |
2477 | } | |
2478 | i.sib.scale = i.log2_scale_factor; | |
2479 | if (! i.index_reg) | |
2480 | { | |
2481 | /* <disp>(%esp) becomes two byte modrm | |
2482 | with no index register. We've already | |
2483 | stored the code for esp in i.rm.regmem | |
2484 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2485 | base register besides %esp will not use | |
2486 | the extra modrm byte. */ | |
2487 | i.sib.index = NO_INDEX_REGISTER; | |
2488 | #if ! SCALE1_WHEN_NO_INDEX | |
2489 | /* Another case where we force the second | |
2490 | modrm byte. */ | |
2491 | if (i.log2_scale_factor) | |
2492 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2493 | #endif | |
2494 | } | |
2495 | else | |
2496 | { | |
2497 | i.sib.index = i.index_reg->reg_num; | |
2498 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
3e73aa7c | 2499 | if (i.index_reg->reg_flags & RegRex) |
e5cb08ac | 2500 | i.rex.extY = 1; |
252b5132 RH |
2501 | } |
2502 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2503 | } | |
2504 | ||
2505 | if (fake_zero_displacement) | |
2506 | { | |
2507 | /* Fakes a zero displacement assuming that i.types[op] | |
47926f60 | 2508 | holds the correct displacement size. */ |
b4cac588 AM |
2509 | expressionS *exp; |
2510 | ||
520dc8e8 | 2511 | assert (i.op[op].disps == 0); |
252b5132 | 2512 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2513 | i.op[op].disps = exp; |
252b5132 RH |
2514 | exp->X_op = O_constant; |
2515 | exp->X_add_number = 0; | |
2516 | exp->X_add_symbol = (symbolS *) 0; | |
2517 | exp->X_op_symbol = (symbolS *) 0; | |
2518 | } | |
2519 | } | |
2520 | ||
2521 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2522 | operand (if any) based on i.tm.extension_opcode. | |
2523 | Again, we must be careful to make sure that | |
2524 | segment/control/debug/test/MMX registers are coded | |
47926f60 | 2525 | into the i.rm.reg field. */ |
252b5132 RH |
2526 | if (i.reg_operands) |
2527 | { | |
2528 | unsigned int op = | |
2529 | ((i.types[0] | |
3f4438ab AM |
2530 | & (Reg | RegMMX | RegXMM |
2531 | | SReg2 | SReg3 | |
2532 | | Control | Debug | Test)) | |
252b5132 RH |
2533 | ? 0 |
2534 | : ((i.types[1] | |
3f4438ab AM |
2535 | & (Reg | RegMMX | RegXMM |
2536 | | SReg2 | SReg3 | |
2537 | | Control | Debug | Test)) | |
252b5132 RH |
2538 | ? 1 |
2539 | : 2)); | |
2540 | /* If there is an extension opcode to put here, the | |
47926f60 | 2541 | register number must be put into the regmem field. */ |
252b5132 | 2542 | if (i.tm.extension_opcode != None) |
3e73aa7c JH |
2543 | { |
2544 | i.rm.regmem = i.op[op].regs->reg_num; | |
2545 | if (i.op[op].regs->reg_flags & RegRex) | |
e5cb08ac | 2546 | i.rex.extZ = 1; |
3e73aa7c | 2547 | } |
252b5132 | 2548 | else |
3e73aa7c JH |
2549 | { |
2550 | i.rm.reg = i.op[op].regs->reg_num; | |
2551 | if (i.op[op].regs->reg_flags & RegRex) | |
e5cb08ac | 2552 | i.rex.extX = 1; |
3e73aa7c | 2553 | } |
252b5132 RH |
2554 | |
2555 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2556 | we must set it to 3 to indicate this is a register | |
2557 | operand in the regmem field. */ | |
2558 | if (!i.mem_operands) | |
2559 | i.rm.mode = 3; | |
2560 | } | |
2561 | ||
47926f60 | 2562 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
252b5132 RH |
2563 | if (i.tm.extension_opcode != None) |
2564 | i.rm.reg = i.tm.extension_opcode; | |
2565 | } | |
2566 | } | |
2567 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2568 | { | |
47926f60 KH |
2569 | if (i.tm.base_opcode == POP_SEG_SHORT |
2570 | && i.op[0].regs->reg_num == 1) | |
252b5132 RH |
2571 | { |
2572 | as_bad (_("you can't `pop %%cs'")); | |
2573 | return; | |
2574 | } | |
520dc8e8 | 2575 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
3e73aa7c JH |
2576 | if (i.op[0].regs->reg_flags & RegRex) |
2577 | i.rex.extZ = 1; | |
252b5132 RH |
2578 | } |
2579 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2580 | { | |
2581 | default_seg = &ds; | |
2582 | } | |
2583 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2584 | { | |
2585 | /* For the string instructions that allow a segment override | |
2586 | on one of their operands, the default segment is ds. */ | |
2587 | default_seg = &ds; | |
2588 | } | |
2589 | ||
2590 | /* If a segment was explicitly specified, | |
2591 | and the specified segment is not the default, | |
2592 | use an opcode prefix to select it. | |
2593 | If we never figured out what the default segment is, | |
2594 | then default_seg will be zero at this point, | |
2595 | and the specified segment prefix will always be used. */ | |
2596 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2597 | { | |
2598 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2599 | return; | |
2600 | } | |
2601 | } | |
a38cf1db | 2602 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2603 | { |
24eab124 AM |
2604 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2605 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2606 | } |
2607 | } | |
2608 | ||
47926f60 | 2609 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
520dc8e8 | 2610 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2611 | { |
2612 | i.tm.base_opcode = INT3_OPCODE; | |
2613 | i.imm_operands = 0; | |
2614 | } | |
2615 | ||
2f66722d | 2616 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2617 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2618 | { |
2619 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2620 | the absolute address given by the constant. Since ix86 jumps and | |
2621 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2622 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2623 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2624 | } |
2625 | ||
3e73aa7c JH |
2626 | if (i.tm.opcode_modifier & Rex64) |
2627 | i.rex.mode64 = 1; | |
2628 | ||
2629 | /* For 8bit registers we would need an empty rex prefix. | |
2630 | Also in the case instruction is already having prefix, | |
2631 | we need to convert old registers to new ones. */ | |
2632 | ||
2633 | if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64)) | |
2634 | || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64)) | |
2635 | || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty) | |
2636 | && ((i.types[0] & Reg8) || (i.types[1] & Reg8)))) | |
2637 | { | |
2638 | int x; | |
e5cb08ac | 2639 | i.rex.empty = 1; |
3e73aa7c JH |
2640 | for (x = 0; x < 2; x++) |
2641 | { | |
2642 | /* Look for 8bit operand that does use old registers. */ | |
2643 | if (i.types[x] & Reg8 | |
2644 | && !(i.op[x].regs->reg_flags & RegRex64)) | |
2645 | { | |
2646 | /* In case it is "hi" register, give up. */ | |
2647 | if (i.op[x].regs->reg_num > 3) | |
2648 | as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"), | |
2649 | i.op[x].regs->reg_name); | |
2650 | ||
2651 | /* Otherwise it is equivalent to the extended register. | |
2652 | Since the encoding don't change this is merely cosmetical | |
2653 | cleanup for debug output. */ | |
2654 | ||
2655 | i.op[x].regs = i.op[x].regs + 8; | |
2656 | } | |
2657 | } | |
2658 | } | |
2659 | ||
2660 | if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty) | |
2661 | add_prefix (0x40 | |
2662 | | (i.rex.mode64 ? 8 : 0) | |
2663 | | (i.rex.extX ? 4 : 0) | |
2664 | | (i.rex.extY ? 2 : 0) | |
2665 | | (i.rex.extZ ? 1 : 0)); | |
2666 | ||
47926f60 | 2667 | /* We are ready to output the insn. */ |
252b5132 RH |
2668 | { |
2669 | register char *p; | |
2670 | ||
47926f60 | 2671 | /* Output jumps. */ |
252b5132 RH |
2672 | if (i.tm.opcode_modifier & Jump) |
2673 | { | |
a217f122 AM |
2674 | int size; |
2675 | int code16; | |
2676 | int prefix; | |
252b5132 | 2677 | |
a217f122 | 2678 | code16 = 0; |
3e73aa7c | 2679 | if (flag_code == CODE_16BIT) |
a217f122 AM |
2680 | code16 = CODE16; |
2681 | ||
2682 | prefix = 0; | |
2683 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2684 | { |
a217f122 | 2685 | prefix = 1; |
252b5132 | 2686 | i.prefixes -= 1; |
a217f122 | 2687 | code16 ^= CODE16; |
252b5132 | 2688 | } |
3e73aa7c JH |
2689 | if (i.prefix[REX_PREFIX]) |
2690 | { | |
2691 | prefix++; | |
e5cb08ac | 2692 | i.prefixes--; |
3e73aa7c | 2693 | } |
252b5132 | 2694 | |
a217f122 AM |
2695 | size = 4; |
2696 | if (code16) | |
2697 | size = 2; | |
2698 | ||
2699 | if (i.prefixes != 0 && !intel_syntax) | |
252b5132 RH |
2700 | as_warn (_("skipping prefixes on this instruction")); |
2701 | ||
2f66722d AM |
2702 | /* It's always a symbol; End frag & setup for relax. |
2703 | Make sure there is enough room in this frag for the largest | |
2704 | instruction we may generate in md_convert_frag. This is 2 | |
2705 | bytes for the opcode and room for the prefix and largest | |
2706 | displacement. */ | |
2707 | frag_grow (prefix + 2 + size); | |
2708 | insn_size += prefix + 1; | |
2709 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
2710 | p = frag_more (prefix + 1); | |
3e73aa7c | 2711 | if (i.prefix[DATA_PREFIX]) |
2f66722d | 2712 | *p++ = DATA_PREFIX_OPCODE; |
3e73aa7c JH |
2713 | if (i.prefix[REX_PREFIX]) |
2714 | *p++ = i.prefix[REX_PREFIX]; | |
2f66722d | 2715 | *p = i.tm.base_opcode; |
ee7fcc42 AM |
2716 | /* 1 possible extra opcode + displacement go in var part. |
2717 | Pass reloc in fr_var. */ | |
2f66722d AM |
2718 | frag_var (rs_machine_dependent, |
2719 | 1 + size, | |
ee7fcc42 | 2720 | i.disp_reloc[0], |
2f66722d AM |
2721 | ((unsigned char) *p == JUMP_PC_RELATIVE |
2722 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 | |
2723 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
520dc8e8 AM |
2724 | i.op[0].disps->X_add_symbol, |
2725 | i.op[0].disps->X_add_number, | |
2f66722d | 2726 | p); |
252b5132 RH |
2727 | } |
2728 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2729 | { | |
a217f122 | 2730 | int size; |
252b5132 | 2731 | |
a217f122 | 2732 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2733 | { |
a217f122 AM |
2734 | /* This is a loop or jecxz type instruction. */ |
2735 | size = 1; | |
252b5132 RH |
2736 | if (i.prefix[ADDR_PREFIX]) |
2737 | { | |
2738 | insn_size += 1; | |
2739 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
2740 | i.prefixes -= 1; | |
2741 | } | |
2742 | } | |
2743 | else | |
2744 | { | |
a217f122 AM |
2745 | int code16; |
2746 | ||
2747 | code16 = 0; | |
3e73aa7c | 2748 | if (flag_code == CODE_16BIT) |
a217f122 | 2749 | code16 = CODE16; |
252b5132 RH |
2750 | |
2751 | if (i.prefix[DATA_PREFIX]) | |
2752 | { | |
2753 | insn_size += 1; | |
2754 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
2755 | i.prefixes -= 1; | |
a217f122 | 2756 | code16 ^= CODE16; |
252b5132 | 2757 | } |
252b5132 | 2758 | |
a217f122 | 2759 | size = 4; |
252b5132 RH |
2760 | if (code16) |
2761 | size = 2; | |
2762 | } | |
2763 | ||
3e73aa7c JH |
2764 | if (i.prefix[REX_PREFIX]) |
2765 | { | |
2766 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
2767 | insn_size++; | |
2768 | i.prefixes -= 1; | |
2769 | } | |
2770 | ||
a217f122 | 2771 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2772 | as_warn (_("skipping prefixes on this instruction")); |
2773 | ||
2774 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2775 | { | |
2776 | insn_size += 1 + size; | |
2777 | p = frag_more (1 + size); | |
2778 | } | |
2779 | else | |
2780 | { | |
47926f60 | 2781 | /* Opcode can be at most two bytes. */ |
a217f122 | 2782 | insn_size += 2 + size; |
252b5132 RH |
2783 | p = frag_more (2 + size); |
2784 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2785 | } | |
2786 | *p++ = i.tm.base_opcode & 0xff; | |
2787 | ||
2f66722d | 2788 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3e73aa7c | 2789 | i.op[0].disps, 1, reloc (size, 1, 1, i.disp_reloc[0])); |
252b5132 RH |
2790 | } |
2791 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2792 | { | |
2793 | int size; | |
a217f122 AM |
2794 | int prefix; |
2795 | int code16; | |
252b5132 | 2796 | |
a217f122 | 2797 | code16 = 0; |
3e73aa7c | 2798 | if (flag_code == CODE_16BIT) |
a217f122 AM |
2799 | code16 = CODE16; |
2800 | ||
2801 | prefix = 0; | |
2802 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2803 | { |
a217f122 | 2804 | prefix = 1; |
252b5132 | 2805 | i.prefixes -= 1; |
a217f122 | 2806 | code16 ^= CODE16; |
252b5132 | 2807 | } |
3e73aa7c JH |
2808 | if (i.prefix[REX_PREFIX]) |
2809 | { | |
2810 | prefix++; | |
2811 | i.prefixes -= 1; | |
2812 | } | |
252b5132 RH |
2813 | |
2814 | size = 4; | |
252b5132 | 2815 | if (code16) |
f6af82bd | 2816 | size = 2; |
252b5132 | 2817 | |
a217f122 | 2818 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2819 | as_warn (_("skipping prefixes on this instruction")); |
2820 | ||
47926f60 KH |
2821 | /* 1 opcode; 2 segment; offset */ |
2822 | insn_size += prefix + 1 + 2 + size; | |
252b5132 | 2823 | p = frag_more (prefix + 1 + 2 + size); |
3e73aa7c JH |
2824 | |
2825 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2826 | *p++ = DATA_PREFIX_OPCODE; |
3e73aa7c JH |
2827 | |
2828 | if (i.prefix[REX_PREFIX]) | |
2829 | *p++ = i.prefix[REX_PREFIX]; | |
2830 | ||
252b5132 | 2831 | *p++ = i.tm.base_opcode; |
520dc8e8 | 2832 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2833 | { |
847f7ad4 | 2834 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2835 | |
773f551c AM |
2836 | if (size == 2 |
2837 | && !fits_in_unsigned_word (n) | |
2838 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2839 | { |
2840 | as_bad (_("16-bit jump out of range")); | |
2841 | return; | |
2842 | } | |
847f7ad4 | 2843 | md_number_to_chars (p, n, size); |
252b5132 RH |
2844 | } |
2845 | else | |
2846 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3e73aa7c | 2847 | i.op[1].imms, 0, reloc (size, 0, 0, i.disp_reloc[0])); |
520dc8e8 | 2848 | if (i.op[0].imms->X_op != O_constant) |
252b5132 RH |
2849 | as_bad (_("can't handle non absolute segment in `%s'"), |
2850 | i.tm.name); | |
520dc8e8 | 2851 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2852 | } |
2853 | else | |
2854 | { | |
47926f60 | 2855 | /* Output normal instructions here. */ |
252b5132 RH |
2856 | unsigned char *q; |
2857 | ||
7bc70a8e JH |
2858 | /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third |
2859 | byte for the SSE instructions to specify prefix they require. */ | |
2860 | if (i.tm.base_opcode & 0xff0000) | |
2861 | add_prefix ((i.tm.base_opcode >> 16) & 0xff); | |
2862 | ||
47926f60 | 2863 | /* The prefix bytes. */ |
252b5132 RH |
2864 | for (q = i.prefix; |
2865 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2866 | q++) | |
2867 | { | |
2868 | if (*q) | |
2869 | { | |
2870 | insn_size += 1; | |
2871 | p = frag_more (1); | |
2872 | md_number_to_chars (p, (valueT) *q, 1); | |
2873 | } | |
2874 | } | |
2875 | ||
47926f60 | 2876 | /* Now the opcode; be careful about word order here! */ |
252b5132 RH |
2877 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
2878 | { | |
2879 | insn_size += 1; | |
2880 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
2881 | } | |
7bc70a8e | 2882 | else |
252b5132 RH |
2883 | { |
2884 | insn_size += 2; | |
2885 | p = frag_more (2); | |
47926f60 | 2886 | /* Put out high byte first: can't use md_number_to_chars! */ |
252b5132 RH |
2887 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2888 | *p = i.tm.base_opcode & 0xff; | |
2889 | } | |
252b5132 RH |
2890 | |
2891 | /* Now the modrm byte and sib byte (if present). */ | |
2892 | if (i.tm.opcode_modifier & Modrm) | |
2893 | { | |
2894 | insn_size += 1; | |
2895 | p = frag_more (1); | |
2896 | md_number_to_chars (p, | |
2897 | (valueT) (i.rm.regmem << 0 | |
2898 | | i.rm.reg << 3 | |
2899 | | i.rm.mode << 6), | |
2900 | 1); | |
2901 | /* If i.rm.regmem == ESP (4) | |
2902 | && i.rm.mode != (Register mode) | |
2903 | && not 16 bit | |
2904 | ==> need second modrm byte. */ | |
2905 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2906 | && i.rm.mode != 3 | |
2907 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2908 | { | |
2909 | insn_size += 1; | |
2910 | p = frag_more (1); | |
2911 | md_number_to_chars (p, | |
2912 | (valueT) (i.sib.base << 0 | |
2913 | | i.sib.index << 3 | |
2914 | | i.sib.scale << 6), | |
2915 | 1); | |
2916 | } | |
2917 | } | |
2918 | ||
2919 | if (i.disp_operands) | |
2920 | { | |
2921 | register unsigned int n; | |
2922 | ||
2923 | for (n = 0; n < i.operands; n++) | |
2924 | { | |
520dc8e8 | 2925 | if (i.types[n] & Disp) |
252b5132 | 2926 | { |
520dc8e8 | 2927 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 2928 | { |
847f7ad4 AM |
2929 | int size; |
2930 | offsetT val; | |
b4cac588 | 2931 | |
847f7ad4 | 2932 | size = 4; |
3e73aa7c | 2933 | if (i.types[n] & (Disp8 | Disp16 | Disp64)) |
252b5132 | 2934 | { |
b4cac588 | 2935 | size = 2; |
b4cac588 | 2936 | if (i.types[n] & Disp8) |
847f7ad4 | 2937 | size = 1; |
3e73aa7c JH |
2938 | if (i.types[n] & Disp64) |
2939 | size = 8; | |
252b5132 | 2940 | } |
847f7ad4 AM |
2941 | val = offset_in_range (i.op[n].disps->X_add_number, |
2942 | size); | |
b4cac588 AM |
2943 | insn_size += size; |
2944 | p = frag_more (size); | |
847f7ad4 | 2945 | md_number_to_chars (p, val, size); |
252b5132 | 2946 | } |
252b5132 | 2947 | else |
520dc8e8 AM |
2948 | { |
2949 | int size = 4; | |
3e73aa7c JH |
2950 | int sign = 0; |
2951 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; | |
2952 | ||
2953 | /* The PC relative address is computed relative | |
2954 | to the instruction boundary, so in case immediate | |
2955 | fields follows, we need to adjust the value. */ | |
2956 | if (pcrel && i.imm_operands) | |
2957 | { | |
2958 | int imm_size = 4; | |
2959 | register unsigned int n1; | |
2960 | ||
2961 | for (n1 = 0; n1 < i.operands; n1++) | |
2962 | if (i.types[n1] & Imm) | |
2963 | { | |
2964 | if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
2965 | { | |
2966 | imm_size = 2; | |
2967 | if (i.types[n1] & (Imm8 | Imm8S)) | |
2968 | imm_size = 1; | |
2969 | if (i.types[n1] & Imm64) | |
2970 | imm_size = 8; | |
2971 | } | |
2972 | break; | |
2973 | } | |
2974 | /* We should find the immediate. */ | |
2975 | if (n1 == i.operands) | |
bfb32b52 | 2976 | abort (); |
3e73aa7c JH |
2977 | i.op[n].disps->X_add_number -= imm_size; |
2978 | } | |
520dc8e8 | 2979 | |
3e73aa7c JH |
2980 | if (i.types[n] & Disp32S) |
2981 | sign = 1; | |
2982 | ||
e5cb08ac | 2983 | if (i.types[n] & (Disp16 | Disp64)) |
3e73aa7c JH |
2984 | { |
2985 | size = 2; | |
2986 | if (i.types[n] & Disp64) | |
2987 | size = 8; | |
2988 | } | |
520dc8e8 AM |
2989 | |
2990 | insn_size += size; | |
2991 | p = frag_more (size); | |
2992 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3e73aa7c JH |
2993 | i.op[n].disps, pcrel, |
2994 | reloc (size, pcrel, sign, i.disp_reloc[n])); | |
252b5132 RH |
2995 | } |
2996 | } | |
2997 | } | |
ce8a8b2f | 2998 | } |
252b5132 | 2999 | |
47926f60 | 3000 | /* Output immediate. */ |
252b5132 RH |
3001 | if (i.imm_operands) |
3002 | { | |
3003 | register unsigned int n; | |
3004 | ||
3005 | for (n = 0; n < i.operands; n++) | |
3006 | { | |
520dc8e8 | 3007 | if (i.types[n] & Imm) |
252b5132 | 3008 | { |
520dc8e8 | 3009 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 3010 | { |
847f7ad4 AM |
3011 | int size; |
3012 | offsetT val; | |
b4cac588 | 3013 | |
847f7ad4 | 3014 | size = 4; |
3e73aa7c | 3015 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) |
252b5132 | 3016 | { |
b4cac588 | 3017 | size = 2; |
b4cac588 | 3018 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 3019 | size = 1; |
3e73aa7c JH |
3020 | else if (i.types[n] & Imm64) |
3021 | size = 8; | |
252b5132 | 3022 | } |
847f7ad4 AM |
3023 | val = offset_in_range (i.op[n].imms->X_add_number, |
3024 | size); | |
b4cac588 AM |
3025 | insn_size += size; |
3026 | p = frag_more (size); | |
847f7ad4 | 3027 | md_number_to_chars (p, val, size); |
252b5132 RH |
3028 | } |
3029 | else | |
ce8a8b2f AM |
3030 | { |
3031 | /* Not absolute_section. | |
3032 | Need a 32-bit fixup (don't support 8bit | |
520dc8e8 | 3033 | non-absolute imms). Try to support other |
47926f60 | 3034 | sizes ... */ |
f6af82bd AM |
3035 | #ifdef BFD_ASSEMBLER |
3036 | enum bfd_reloc_code_real reloc_type; | |
3037 | #else | |
3038 | int reloc_type; | |
3039 | #endif | |
520dc8e8 | 3040 | int size = 4; |
3e73aa7c | 3041 | int sign = 0; |
252b5132 | 3042 | |
3e73aa7c JH |
3043 | if ((i.types[n] & (Imm32S)) |
3044 | && i.suffix == QWORD_MNEM_SUFFIX) | |
3045 | sign = 1; | |
3046 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3047 | { | |
3048 | size = 2; | |
3049 | if (i.types[n] & (Imm8 | Imm8S)) | |
3050 | size = 1; | |
3051 | if (i.types[n] & Imm64) | |
3052 | size = 8; | |
3053 | } | |
520dc8e8 | 3054 | |
252b5132 RH |
3055 | insn_size += size; |
3056 | p = frag_more (size); | |
3e73aa7c | 3057 | reloc_type = reloc (size, 0, sign, i.disp_reloc[0]); |
252b5132 | 3058 | #ifdef BFD_ASSEMBLER |
f6af82bd | 3059 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 3060 | && GOT_symbol |
520dc8e8 AM |
3061 | && GOT_symbol == i.op[n].imms->X_add_symbol |
3062 | && (i.op[n].imms->X_op == O_symbol | |
3063 | || (i.op[n].imms->X_op == O_add | |
49309057 | 3064 | && ((symbol_get_value_expression |
520dc8e8 | 3065 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
3066 | == O_subtract)))) |
3067 | { | |
3e73aa7c JH |
3068 | /* We don't support dynamic linking on x86-64 yet. */ |
3069 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 3070 | abort (); |
f6af82bd | 3071 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 3072 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
3073 | } |
3074 | #endif | |
3075 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 3076 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
3077 | } |
3078 | } | |
3079 | } | |
ce8a8b2f | 3080 | } |
252b5132 RH |
3081 | } |
3082 | ||
e346e481 RH |
3083 | dwarf2_emit_insn (insn_size); |
3084 | ||
252b5132 RH |
3085 | #ifdef DEBUG386 |
3086 | if (flag_debug) | |
3087 | { | |
3088 | pi (line, &i); | |
3089 | } | |
47926f60 | 3090 | #endif /* DEBUG386 */ |
252b5132 RH |
3091 | } |
3092 | } | |
3093 | \f | |
252b5132 RH |
3094 | static int i386_immediate PARAMS ((char *)); |
3095 | ||
3096 | static int | |
3097 | i386_immediate (imm_start) | |
3098 | char *imm_start; | |
3099 | { | |
3100 | char *save_input_line_pointer; | |
3101 | segT exp_seg = 0; | |
47926f60 | 3102 | expressionS *exp; |
252b5132 RH |
3103 | |
3104 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
3105 | { | |
d0b47220 | 3106 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
3107 | return 0; |
3108 | } | |
3109 | ||
3110 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 3111 | i.op[this_operand].imms = exp; |
252b5132 RH |
3112 | |
3113 | if (is_space_char (*imm_start)) | |
3114 | ++imm_start; | |
3115 | ||
3116 | save_input_line_pointer = input_line_pointer; | |
3117 | input_line_pointer = imm_start; | |
3118 | ||
3119 | #ifndef LEX_AT | |
24eab124 | 3120 | { |
47926f60 KH |
3121 | /* We can have operands of the form |
3122 | <symbol>@GOTOFF+<nnn> | |
3123 | Take the easy way out here and copy everything | |
3124 | into a temporary buffer... */ | |
24eab124 AM |
3125 | register char *cp; |
3126 | ||
3127 | cp = strchr (input_line_pointer, '@'); | |
3128 | if (cp != NULL) | |
3129 | { | |
3130 | char *tmpbuf; | |
3131 | int len = 0; | |
3132 | int first; | |
3133 | ||
47926f60 | 3134 | /* GOT relocations are not supported in 16 bit mode. */ |
3e73aa7c | 3135 | if (flag_code == CODE_16BIT) |
24eab124 AM |
3136 | as_bad (_("GOT relocations not supported in 16 bit mode")); |
3137 | ||
3138 | if (GOT_symbol == NULL) | |
3139 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3140 | ||
3141 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
3142 | { | |
3e73aa7c JH |
3143 | if (flag_code == CODE_64BIT) |
3144 | i.disp_reloc[this_operand] = BFD_RELOC_X86_64_PLT32; | |
3145 | else | |
3146 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
24eab124 AM |
3147 | len = 3; |
3148 | } | |
3149 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
3150 | { | |
3e73aa7c JH |
3151 | if (flag_code == CODE_64BIT) |
3152 | as_bad ("GOTOFF relocations are unsupported in 64bit mode."); | |
24eab124 AM |
3153 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; |
3154 | len = 6; | |
3155 | } | |
b77a7acd | 3156 | else if (strncmp (cp + 1, "GOTPCREL", 8) == 0) |
24eab124 | 3157 | { |
3e73aa7c | 3158 | if (flag_code == CODE_64BIT) |
b77a7acd | 3159 | i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOTPCREL; |
3e73aa7c | 3160 | else |
b77a7acd AJ |
3161 | as_bad ("GOTPCREL relocations are supported only in 64bit mode."); |
3162 | len = 8; | |
3e73aa7c | 3163 | } |
b77a7acd | 3164 | else if (strncmp (cp + 1, "GOT", 3) == 0) |
3e73aa7c JH |
3165 | { |
3166 | if (flag_code == CODE_64BIT) | |
b77a7acd | 3167 | i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOT32; |
3e73aa7c | 3168 | else |
b77a7acd | 3169 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; |
24eab124 AM |
3170 | len = 3; |
3171 | } | |
3172 | else | |
d0b47220 | 3173 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
3174 | |
3175 | /* Replace the relocation token with ' ', so that errors like | |
3176 | foo@GOTOFF1 will be detected. */ | |
3177 | first = cp - input_line_pointer; | |
47926f60 | 3178 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
24eab124 AM |
3179 | memcpy (tmpbuf, input_line_pointer, first); |
3180 | tmpbuf[first] = ' '; | |
3181 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
3182 | input_line_pointer = tmpbuf; | |
3183 | } | |
3184 | } | |
252b5132 RH |
3185 | #endif |
3186 | ||
3187 | exp_seg = expression (exp); | |
3188 | ||
83183c0c | 3189 | SKIP_WHITESPACE (); |
252b5132 | 3190 | if (*input_line_pointer) |
d0b47220 | 3191 | as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
3192 | |
3193 | input_line_pointer = save_input_line_pointer; | |
3194 | ||
2daf4fd8 | 3195 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 3196 | { |
47926f60 | 3197 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3198 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 3199 | imm_start); |
252b5132 RH |
3200 | exp->X_op = O_constant; |
3201 | exp->X_add_number = 0; | |
3202 | exp->X_add_symbol = (symbolS *) 0; | |
3203 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 3204 | } |
3e73aa7c | 3205 | else if (exp->X_op == O_constant) |
252b5132 | 3206 | { |
47926f60 | 3207 | /* Size it properly later. */ |
3e73aa7c JH |
3208 | i.types[this_operand] |= Imm64; |
3209 | /* If BFD64, sign extend val. */ | |
3210 | if (!use_rela_relocations) | |
3211 | if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
3212 | exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 3213 | } |
4c63da97 | 3214 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
47926f60 | 3215 | else if (1 |
4c63da97 | 3216 | #ifdef BFD_ASSEMBLER |
47926f60 | 3217 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3218 | #endif |
47926f60 | 3219 | && exp_seg != text_section |
24eab124 AM |
3220 | && exp_seg != data_section |
3221 | && exp_seg != bss_section | |
3222 | && exp_seg != undefined_section | |
252b5132 | 3223 | #ifdef BFD_ASSEMBLER |
24eab124 | 3224 | && !bfd_is_com_section (exp_seg) |
252b5132 | 3225 | #endif |
24eab124 | 3226 | ) |
252b5132 | 3227 | { |
4c63da97 | 3228 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3229 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3230 | #else |
d0b47220 | 3231 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3232 | #endif |
252b5132 RH |
3233 | return 0; |
3234 | } | |
3235 | #endif | |
3236 | else | |
3237 | { | |
3238 | /* This is an address. The size of the address will be | |
24eab124 | 3239 | determined later, depending on destination register, |
3e73aa7c JH |
3240 | suffix, or the default for the section. */ |
3241 | i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; | |
252b5132 RH |
3242 | } |
3243 | ||
3244 | return 1; | |
3245 | } | |
3246 | ||
3247 | static int i386_scale PARAMS ((char *)); | |
3248 | ||
3249 | static int | |
3250 | i386_scale (scale) | |
3251 | char *scale; | |
3252 | { | |
3253 | if (!isdigit (*scale)) | |
3254 | goto bad_scale; | |
3255 | ||
3256 | switch (*scale) | |
3257 | { | |
3258 | case '0': | |
3259 | case '1': | |
3260 | i.log2_scale_factor = 0; | |
3261 | break; | |
3262 | case '2': | |
3263 | i.log2_scale_factor = 1; | |
3264 | break; | |
3265 | case '4': | |
3266 | i.log2_scale_factor = 2; | |
3267 | break; | |
3268 | case '8': | |
3269 | i.log2_scale_factor = 3; | |
3270 | break; | |
3271 | default: | |
3272 | bad_scale: | |
3273 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
24eab124 | 3274 | scale); |
252b5132 RH |
3275 | return 0; |
3276 | } | |
3277 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
3278 | { | |
3279 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 3280 | 1 << i.log2_scale_factor); |
252b5132 RH |
3281 | #if SCALE1_WHEN_NO_INDEX |
3282 | i.log2_scale_factor = 0; | |
3283 | #endif | |
3284 | } | |
3285 | return 1; | |
3286 | } | |
3287 | ||
3288 | static int i386_displacement PARAMS ((char *, char *)); | |
3289 | ||
3290 | static int | |
3291 | i386_displacement (disp_start, disp_end) | |
3292 | char *disp_start; | |
3293 | char *disp_end; | |
3294 | { | |
3295 | register expressionS *exp; | |
3296 | segT exp_seg = 0; | |
3297 | char *save_input_line_pointer; | |
3298 | int bigdisp = Disp32; | |
3299 | ||
3e73aa7c | 3300 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) |
252b5132 | 3301 | bigdisp = Disp16; |
3e73aa7c JH |
3302 | if (flag_code == CODE_64BIT) |
3303 | bigdisp = Disp64; | |
252b5132 RH |
3304 | i.types[this_operand] |= bigdisp; |
3305 | ||
3306 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 3307 | i.op[this_operand].disps = exp; |
252b5132 RH |
3308 | i.disp_operands++; |
3309 | save_input_line_pointer = input_line_pointer; | |
3310 | input_line_pointer = disp_start; | |
3311 | END_STRING_AND_SAVE (disp_end); | |
3312 | ||
3313 | #ifndef GCC_ASM_O_HACK | |
3314 | #define GCC_ASM_O_HACK 0 | |
3315 | #endif | |
3316 | #if GCC_ASM_O_HACK | |
3317 | END_STRING_AND_SAVE (disp_end + 1); | |
3318 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 3319 | && displacement_string_end[-1] == '+') |
252b5132 RH |
3320 | { |
3321 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
3322 | constraint within gcc asm statements. |
3323 | For instance: | |
3324 | ||
3325 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
3326 | __asm__ __volatile__ ( \ | |
3327 | "movw %w2,%0\n\t" \ | |
3328 | "movw %w1,2+%0\n\t" \ | |
3329 | "rorl $16,%1\n\t" \ | |
3330 | "movb %b1,4+%0\n\t" \ | |
3331 | "movb %4,5+%0\n\t" \ | |
3332 | "movb $0,6+%0\n\t" \ | |
3333 | "movb %h1,7+%0\n\t" \ | |
3334 | "rorl $16,%1" \ | |
3335 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
3336 | ||
3337 | This works great except that the output assembler ends | |
3338 | up looking a bit weird if it turns out that there is | |
3339 | no offset. You end up producing code that looks like: | |
3340 | ||
3341 | #APP | |
3342 | movw $235,(%eax) | |
3343 | movw %dx,2+(%eax) | |
3344 | rorl $16,%edx | |
3345 | movb %dl,4+(%eax) | |
3346 | movb $137,5+(%eax) | |
3347 | movb $0,6+(%eax) | |
3348 | movb %dh,7+(%eax) | |
3349 | rorl $16,%edx | |
3350 | #NO_APP | |
3351 | ||
47926f60 | 3352 | So here we provide the missing zero. */ |
24eab124 AM |
3353 | |
3354 | *displacement_string_end = '0'; | |
252b5132 RH |
3355 | } |
3356 | #endif | |
3357 | #ifndef LEX_AT | |
24eab124 | 3358 | { |
47926f60 KH |
3359 | /* We can have operands of the form |
3360 | <symbol>@GOTOFF+<nnn> | |
3361 | Take the easy way out here and copy everything | |
3362 | into a temporary buffer... */ | |
24eab124 AM |
3363 | register char *cp; |
3364 | ||
3365 | cp = strchr (input_line_pointer, '@'); | |
3366 | if (cp != NULL) | |
3367 | { | |
3368 | char *tmpbuf; | |
3369 | int len = 0; | |
3370 | int first; | |
3371 | ||
47926f60 | 3372 | /* GOT relocations are not supported in 16 bit mode. */ |
3e73aa7c | 3373 | if (flag_code == CODE_16BIT) |
24eab124 AM |
3374 | as_bad (_("GOT relocations not supported in 16 bit mode")); |
3375 | ||
3376 | if (GOT_symbol == NULL) | |
3377 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3378 | ||
3379 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
3380 | { | |
3e73aa7c JH |
3381 | if (flag_code == CODE_64BIT) |
3382 | i.disp_reloc[this_operand] = BFD_RELOC_X86_64_PLT32; | |
3383 | else | |
3384 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
24eab124 AM |
3385 | len = 3; |
3386 | } | |
3387 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
3388 | { | |
3e73aa7c JH |
3389 | if (flag_code == CODE_64BIT) |
3390 | as_bad ("GOTOFF relocation is not supported in 64bit mode."); | |
24eab124 AM |
3391 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; |
3392 | len = 6; | |
3393 | } | |
b77a7acd AJ |
3394 | else if (strncmp (cp + 1, "GOTPCREL", 8) == 0) |
3395 | { | |
3396 | if (flag_code != CODE_64BIT) | |
3397 | as_bad ("GOTPCREL relocation is supported only in 64bit mode."); | |
3398 | i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOTPCREL; | |
3399 | len = 8; | |
3400 | } | |
24eab124 AM |
3401 | else if (strncmp (cp + 1, "GOT", 3) == 0) |
3402 | { | |
3e73aa7c JH |
3403 | if (flag_code == CODE_64BIT) |
3404 | i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOT32; | |
3405 | else | |
3406 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
3407 | len = 3; | |
3408 | } | |
24eab124 | 3409 | else |
d0b47220 | 3410 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
3411 | |
3412 | /* Replace the relocation token with ' ', so that errors like | |
3413 | foo@GOTOFF1 will be detected. */ | |
3414 | first = cp - input_line_pointer; | |
47926f60 | 3415 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
24eab124 AM |
3416 | memcpy (tmpbuf, input_line_pointer, first); |
3417 | tmpbuf[first] = ' '; | |
3418 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
3419 | input_line_pointer = tmpbuf; | |
3420 | } | |
3421 | } | |
252b5132 RH |
3422 | #endif |
3423 | ||
24eab124 | 3424 | exp_seg = expression (exp); |
252b5132 RH |
3425 | |
3426 | #ifdef BFD_ASSEMBLER | |
24eab124 AM |
3427 | /* We do this to make sure that the section symbol is in |
3428 | the symbol table. We will ultimately change the relocation | |
47926f60 | 3429 | to be relative to the beginning of the section. */ |
3e73aa7c JH |
3430 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF |
3431 | || i.disp_reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) | |
24eab124 | 3432 | { |
e5cb08ac | 3433 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
3434 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
3435 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
3436 | assert (exp->X_op == O_symbol); | |
3437 | exp->X_op = O_subtract; | |
3438 | exp->X_op_symbol = GOT_symbol; | |
23df1078 JH |
3439 | if (i.disp_reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
3440 | i.disp_reloc[this_operand] = BFD_RELOC_32_PCREL; | |
3441 | else | |
3442 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
24eab124 | 3443 | } |
252b5132 RH |
3444 | #endif |
3445 | ||
24eab124 AM |
3446 | SKIP_WHITESPACE (); |
3447 | if (*input_line_pointer) | |
d0b47220 | 3448 | as_bad (_("ignoring junk `%s' after expression"), |
24eab124 | 3449 | input_line_pointer); |
252b5132 | 3450 | #if GCC_ASM_O_HACK |
24eab124 | 3451 | RESTORE_END_STRING (disp_end + 1); |
252b5132 | 3452 | #endif |
24eab124 AM |
3453 | RESTORE_END_STRING (disp_end); |
3454 | input_line_pointer = save_input_line_pointer; | |
3455 | ||
2daf4fd8 AM |
3456 | if (exp->X_op == O_absent || exp->X_op == O_big) |
3457 | { | |
47926f60 | 3458 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3459 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
3460 | disp_start); |
3461 | exp->X_op = O_constant; | |
3462 | exp->X_add_number = 0; | |
3463 | exp->X_add_symbol = (symbolS *) 0; | |
3464 | exp->X_op_symbol = (symbolS *) 0; | |
3465 | } | |
3466 | ||
4c63da97 | 3467 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 3468 | if (exp->X_op != O_constant |
4c63da97 | 3469 | #ifdef BFD_ASSEMBLER |
45288df1 | 3470 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3471 | #endif |
45288df1 AM |
3472 | && exp_seg != text_section |
3473 | && exp_seg != data_section | |
3474 | && exp_seg != bss_section | |
3475 | && exp_seg != undefined_section) | |
24eab124 | 3476 | { |
4c63da97 | 3477 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3478 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3479 | #else |
d0b47220 | 3480 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3481 | #endif |
24eab124 AM |
3482 | return 0; |
3483 | } | |
252b5132 | 3484 | #endif |
3e73aa7c JH |
3485 | else if (flag_code == CODE_64BIT) |
3486 | i.types[this_operand] |= Disp32S | Disp32; | |
252b5132 RH |
3487 | return 1; |
3488 | } | |
3489 | ||
e5cb08ac | 3490 | static int i386_index_check PARAMS ((const char *)); |
252b5132 | 3491 | |
eecb386c | 3492 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3493 | Return 1 on success, 0 on a failure. */ |
3494 | ||
252b5132 | 3495 | static int |
eecb386c AM |
3496 | i386_index_check (operand_string) |
3497 | const char *operand_string; | |
252b5132 | 3498 | { |
3e73aa7c | 3499 | int ok; |
24eab124 | 3500 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3501 | int fudged = 0; |
3502 | ||
24eab124 AM |
3503 | tryprefix: |
3504 | #endif | |
3e73aa7c JH |
3505 | ok = 1; |
3506 | if (flag_code == CODE_64BIT) | |
3507 | { | |
3508 | /* 64bit checks. */ | |
3509 | if ((i.base_reg | |
3510 | && ((i.base_reg->reg_type & Reg64) == 0) | |
3511 | && (i.base_reg->reg_type != BaseIndex | |
3512 | || i.index_reg)) | |
3513 | || (i.index_reg | |
3514 | && ((i.index_reg->reg_type & (Reg64|BaseIndex)) | |
3515 | != (Reg64|BaseIndex)))) | |
3516 | ok = 0; | |
3517 | } | |
3518 | else | |
3519 | { | |
3520 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3521 | { | |
3522 | /* 16bit checks. */ | |
3523 | if ((i.base_reg | |
3524 | && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex)) | |
3525 | != (Reg16|BaseIndex))) | |
3526 | || (i.index_reg | |
3527 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3528 | != (Reg16|BaseIndex)) | |
3529 | || ! (i.base_reg | |
3530 | && i.base_reg->reg_num < 6 | |
3531 | && i.index_reg->reg_num >= 6 | |
3532 | && i.log2_scale_factor == 0)))) | |
3533 | ok = 0; | |
3534 | } | |
3535 | else | |
e5cb08ac | 3536 | { |
3e73aa7c JH |
3537 | /* 32bit checks. */ |
3538 | if ((i.base_reg | |
3539 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
3540 | || (i.index_reg | |
3541 | && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex)) | |
3542 | != (Reg32|BaseIndex)))) | |
e5cb08ac | 3543 | ok = 0; |
3e73aa7c JH |
3544 | } |
3545 | } | |
3546 | if (!ok) | |
24eab124 AM |
3547 | { |
3548 | #if INFER_ADDR_PREFIX | |
3e73aa7c JH |
3549 | if (flag_code != CODE_64BIT |
3550 | && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') | |
24eab124 AM |
3551 | { |
3552 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3553 | i.prefixes += 1; | |
b23bac36 AM |
3554 | /* Change the size of any displacement too. At most one of |
3555 | Disp16 or Disp32 is set. | |
3556 | FIXME. There doesn't seem to be any real need for separate | |
3557 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 3558 | Removing them would probably clean up the code quite a lot. */ |
b23bac36 AM |
3559 | if (i.types[this_operand] & (Disp16|Disp32)) |
3560 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3561 | fudged = 1; |
24eab124 AM |
3562 | goto tryprefix; |
3563 | } | |
eecb386c AM |
3564 | if (fudged) |
3565 | as_bad (_("`%s' is not a valid base/index expression"), | |
3566 | operand_string); | |
3567 | else | |
c388dee8 | 3568 | #endif |
eecb386c AM |
3569 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3570 | operand_string, | |
3e73aa7c | 3571 | flag_code_names[flag_code]); |
eecb386c | 3572 | return 0; |
24eab124 AM |
3573 | } |
3574 | return 1; | |
3575 | } | |
252b5132 | 3576 | |
252b5132 | 3577 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 3578 | on error. */ |
252b5132 | 3579 | |
252b5132 RH |
3580 | static int |
3581 | i386_operand (operand_string) | |
3582 | char *operand_string; | |
3583 | { | |
af6bdddf AM |
3584 | const reg_entry *r; |
3585 | char *end_op; | |
24eab124 | 3586 | char *op_string = operand_string; |
252b5132 | 3587 | |
24eab124 | 3588 | if (is_space_char (*op_string)) |
252b5132 RH |
3589 | ++op_string; |
3590 | ||
24eab124 | 3591 | /* We check for an absolute prefix (differentiating, |
47926f60 | 3592 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
3593 | if (*op_string == ABSOLUTE_PREFIX) |
3594 | { | |
3595 | ++op_string; | |
3596 | if (is_space_char (*op_string)) | |
3597 | ++op_string; | |
3598 | i.types[this_operand] |= JumpAbsolute; | |
3599 | } | |
252b5132 | 3600 | |
47926f60 | 3601 | /* Check if operand is a register. */ |
af6bdddf AM |
3602 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3603 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3604 | { |
24eab124 AM |
3605 | /* Check for a segment override by searching for ':' after a |
3606 | segment register. */ | |
3607 | op_string = end_op; | |
3608 | if (is_space_char (*op_string)) | |
3609 | ++op_string; | |
3610 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3611 | { | |
3612 | switch (r->reg_num) | |
3613 | { | |
3614 | case 0: | |
3615 | i.seg[i.mem_operands] = &es; | |
3616 | break; | |
3617 | case 1: | |
3618 | i.seg[i.mem_operands] = &cs; | |
3619 | break; | |
3620 | case 2: | |
3621 | i.seg[i.mem_operands] = &ss; | |
3622 | break; | |
3623 | case 3: | |
3624 | i.seg[i.mem_operands] = &ds; | |
3625 | break; | |
3626 | case 4: | |
3627 | i.seg[i.mem_operands] = &fs; | |
3628 | break; | |
3629 | case 5: | |
3630 | i.seg[i.mem_operands] = &gs; | |
3631 | break; | |
3632 | } | |
252b5132 | 3633 | |
24eab124 | 3634 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3635 | ++op_string; |
3636 | if (is_space_char (*op_string)) | |
24eab124 | 3637 | ++op_string; |
252b5132 | 3638 | |
24eab124 AM |
3639 | if (!is_digit_char (*op_string) |
3640 | && !is_identifier_char (*op_string) | |
3641 | && *op_string != '(' | |
3642 | && *op_string != ABSOLUTE_PREFIX) | |
3643 | { | |
3644 | as_bad (_("bad memory operand `%s'"), op_string); | |
3645 | return 0; | |
3646 | } | |
47926f60 | 3647 | /* Handle case of %es:*foo. */ |
24eab124 AM |
3648 | if (*op_string == ABSOLUTE_PREFIX) |
3649 | { | |
3650 | ++op_string; | |
3651 | if (is_space_char (*op_string)) | |
3652 | ++op_string; | |
3653 | i.types[this_operand] |= JumpAbsolute; | |
3654 | } | |
3655 | goto do_memory_reference; | |
3656 | } | |
3657 | if (*op_string) | |
3658 | { | |
d0b47220 | 3659 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3660 | return 0; |
3661 | } | |
3662 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3663 | i.op[this_operand].regs = r; |
24eab124 AM |
3664 | i.reg_operands++; |
3665 | } | |
af6bdddf AM |
3666 | else if (*op_string == REGISTER_PREFIX) |
3667 | { | |
3668 | as_bad (_("bad register name `%s'"), op_string); | |
3669 | return 0; | |
3670 | } | |
24eab124 | 3671 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 3672 | { |
24eab124 AM |
3673 | ++op_string; |
3674 | if (i.types[this_operand] & JumpAbsolute) | |
3675 | { | |
d0b47220 | 3676 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3677 | return 0; |
3678 | } | |
3679 | if (!i386_immediate (op_string)) | |
3680 | return 0; | |
3681 | } | |
3682 | else if (is_digit_char (*op_string) | |
3683 | || is_identifier_char (*op_string) | |
e5cb08ac | 3684 | || *op_string == '(') |
24eab124 | 3685 | { |
47926f60 | 3686 | /* This is a memory reference of some sort. */ |
af6bdddf | 3687 | char *base_string; |
252b5132 | 3688 | |
47926f60 | 3689 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3690 | char *displacement_string_start; |
3691 | char *displacement_string_end; | |
252b5132 | 3692 | |
24eab124 | 3693 | do_memory_reference: |
24eab124 AM |
3694 | if ((i.mem_operands == 1 |
3695 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3696 | || i.mem_operands == 2) | |
3697 | { | |
3698 | as_bad (_("too many memory references for `%s'"), | |
3699 | current_templates->start->name); | |
3700 | return 0; | |
3701 | } | |
252b5132 | 3702 | |
24eab124 AM |
3703 | /* Check for base index form. We detect the base index form by |
3704 | looking for an ')' at the end of the operand, searching | |
3705 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3706 | after the '('. */ | |
af6bdddf | 3707 | base_string = op_string + strlen (op_string); |
c3332e24 | 3708 | |
af6bdddf AM |
3709 | --base_string; |
3710 | if (is_space_char (*base_string)) | |
3711 | --base_string; | |
252b5132 | 3712 | |
47926f60 | 3713 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
3714 | displacement_string_start = op_string; |
3715 | displacement_string_end = base_string + 1; | |
252b5132 | 3716 | |
24eab124 AM |
3717 | if (*base_string == ')') |
3718 | { | |
af6bdddf | 3719 | char *temp_string; |
24eab124 AM |
3720 | unsigned int parens_balanced = 1; |
3721 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 3722 | equal, so this loop will not be infinite. */ |
24eab124 AM |
3723 | do |
3724 | { | |
3725 | base_string--; | |
3726 | if (*base_string == ')') | |
3727 | parens_balanced++; | |
3728 | if (*base_string == '(') | |
3729 | parens_balanced--; | |
3730 | } | |
3731 | while (parens_balanced); | |
c3332e24 | 3732 | |
af6bdddf | 3733 | temp_string = base_string; |
c3332e24 | 3734 | |
24eab124 | 3735 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3736 | ++base_string; |
3737 | if (is_space_char (*base_string)) | |
24eab124 | 3738 | ++base_string; |
252b5132 | 3739 | |
af6bdddf AM |
3740 | if (*base_string == ',' |
3741 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3742 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3743 | { |
af6bdddf | 3744 | displacement_string_end = temp_string; |
252b5132 | 3745 | |
af6bdddf | 3746 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3747 | |
af6bdddf | 3748 | if (i.base_reg) |
24eab124 | 3749 | { |
24eab124 AM |
3750 | base_string = end_op; |
3751 | if (is_space_char (*base_string)) | |
3752 | ++base_string; | |
af6bdddf AM |
3753 | } |
3754 | ||
3755 | /* There may be an index reg or scale factor here. */ | |
3756 | if (*base_string == ',') | |
3757 | { | |
3758 | ++base_string; | |
3759 | if (is_space_char (*base_string)) | |
3760 | ++base_string; | |
3761 | ||
3762 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3763 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3764 | { |
af6bdddf | 3765 | base_string = end_op; |
24eab124 AM |
3766 | if (is_space_char (*base_string)) |
3767 | ++base_string; | |
af6bdddf AM |
3768 | if (*base_string == ',') |
3769 | { | |
3770 | ++base_string; | |
3771 | if (is_space_char (*base_string)) | |
3772 | ++base_string; | |
3773 | } | |
e5cb08ac | 3774 | else if (*base_string != ')') |
af6bdddf AM |
3775 | { |
3776 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3777 | operand_string); | |
3778 | return 0; | |
3779 | } | |
24eab124 | 3780 | } |
af6bdddf | 3781 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3782 | { |
af6bdddf | 3783 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3784 | return 0; |
3785 | } | |
252b5132 | 3786 | |
47926f60 | 3787 | /* Check for scale factor. */ |
af6bdddf AM |
3788 | if (isdigit ((unsigned char) *base_string)) |
3789 | { | |
3790 | if (!i386_scale (base_string)) | |
3791 | return 0; | |
24eab124 | 3792 | |
af6bdddf AM |
3793 | ++base_string; |
3794 | if (is_space_char (*base_string)) | |
3795 | ++base_string; | |
3796 | if (*base_string != ')') | |
3797 | { | |
3798 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3799 | operand_string); | |
3800 | return 0; | |
3801 | } | |
3802 | } | |
3803 | else if (!i.index_reg) | |
24eab124 | 3804 | { |
af6bdddf AM |
3805 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3806 | *base_string); | |
24eab124 AM |
3807 | return 0; |
3808 | } | |
3809 | } | |
af6bdddf | 3810 | else if (*base_string != ')') |
24eab124 | 3811 | { |
af6bdddf AM |
3812 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3813 | operand_string); | |
24eab124 AM |
3814 | return 0; |
3815 | } | |
c3332e24 | 3816 | } |
af6bdddf | 3817 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3818 | { |
af6bdddf | 3819 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3820 | return 0; |
c3332e24 | 3821 | } |
24eab124 AM |
3822 | } |
3823 | ||
3824 | /* If there's an expression beginning the operand, parse it, | |
3825 | assuming displacement_string_start and | |
3826 | displacement_string_end are meaningful. */ | |
3827 | if (displacement_string_start != displacement_string_end) | |
3828 | { | |
3829 | if (!i386_displacement (displacement_string_start, | |
3830 | displacement_string_end)) | |
3831 | return 0; | |
3832 | } | |
3833 | ||
3834 | /* Special case for (%dx) while doing input/output op. */ | |
3835 | if (i.base_reg | |
3836 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3837 | && i.index_reg == 0 | |
3838 | && i.log2_scale_factor == 0 | |
3839 | && i.seg[i.mem_operands] == 0 | |
3840 | && (i.types[this_operand] & Disp) == 0) | |
3841 | { | |
3842 | i.types[this_operand] = InOutPortReg; | |
3843 | return 1; | |
3844 | } | |
3845 | ||
eecb386c AM |
3846 | if (i386_index_check (operand_string) == 0) |
3847 | return 0; | |
24eab124 AM |
3848 | i.mem_operands++; |
3849 | } | |
3850 | else | |
ce8a8b2f AM |
3851 | { |
3852 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
3853 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
3854 | output_invalid (*op_string), | |
3855 | this_operand + 1, | |
3856 | op_string); | |
3857 | return 0; | |
3858 | } | |
47926f60 | 3859 | return 1; /* Normal return. */ |
252b5132 RH |
3860 | } |
3861 | \f | |
ee7fcc42 AM |
3862 | /* md_estimate_size_before_relax() |
3863 | ||
3864 | Called just before relax() for rs_machine_dependent frags. The x86 | |
3865 | assembler uses these frags to handle variable size jump | |
3866 | instructions. | |
3867 | ||
3868 | Any symbol that is now undefined will not become defined. | |
3869 | Return the correct fr_subtype in the frag. | |
3870 | Return the initial "guess for variable size of frag" to caller. | |
3871 | The guess is actually the growth beyond the fixed part. Whatever | |
3872 | we do to grow the fixed or variable part contributes to our | |
3873 | returned value. */ | |
3874 | ||
252b5132 RH |
3875 | int |
3876 | md_estimate_size_before_relax (fragP, segment) | |
3877 | register fragS *fragP; | |
3878 | register segT segment; | |
3879 | { | |
252b5132 | 3880 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
3881 | check for un-relaxable symbols. On an ELF system, we can't relax |
3882 | an externally visible symbol, because it may be overridden by a | |
3883 | shared library. */ | |
3884 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 3885 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b98ef147 AM |
3886 | || S_IS_EXTERNAL (fragP->fr_symbol) |
3887 | || S_IS_WEAK (fragP->fr_symbol) | |
3888 | #endif | |
3889 | ) | |
252b5132 | 3890 | { |
b98ef147 AM |
3891 | /* Symbol is undefined in this segment, or we need to keep a |
3892 | reloc so that weak symbols can be overridden. */ | |
3893 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f6af82bd AM |
3894 | #ifdef BFD_ASSEMBLER |
3895 | enum bfd_reloc_code_real reloc_type; | |
3896 | #else | |
3897 | int reloc_type; | |
3898 | #endif | |
ee7fcc42 AM |
3899 | unsigned char *opcode; |
3900 | int old_fr_fix; | |
f6af82bd | 3901 | |
ee7fcc42 AM |
3902 | if (fragP->fr_var != NO_RELOC) |
3903 | reloc_type = fragP->fr_var; | |
b98ef147 | 3904 | else if (size == 2) |
f6af82bd AM |
3905 | reloc_type = BFD_RELOC_16_PCREL; |
3906 | else | |
3907 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 3908 | |
ee7fcc42 AM |
3909 | old_fr_fix = fragP->fr_fix; |
3910 | opcode = (unsigned char *) fragP->fr_opcode; | |
3911 | ||
252b5132 RH |
3912 | switch (opcode[0]) |
3913 | { | |
47926f60 KH |
3914 | case JUMP_PC_RELATIVE: |
3915 | /* Make jmp (0xeb) a dword displacement jump. */ | |
47926f60 | 3916 | opcode[0] = 0xe9; |
252b5132 RH |
3917 | fragP->fr_fix += size; |
3918 | fix_new (fragP, old_fr_fix, size, | |
3919 | fragP->fr_symbol, | |
3920 | fragP->fr_offset, 1, | |
f6af82bd | 3921 | reloc_type); |
252b5132 RH |
3922 | break; |
3923 | ||
3924 | default: | |
24eab124 | 3925 | /* This changes the byte-displacement jump 0x7N |
f6af82bd | 3926 | to the dword-displacement jump 0x0f,0x8N. */ |
252b5132 | 3927 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 3928 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
3929 | /* We've added an opcode byte. */ |
3930 | fragP->fr_fix += 1 + size; | |
252b5132 RH |
3931 | fix_new (fragP, old_fr_fix + 1, size, |
3932 | fragP->fr_symbol, | |
3933 | fragP->fr_offset, 1, | |
f6af82bd | 3934 | reloc_type); |
252b5132 RH |
3935 | break; |
3936 | } | |
3937 | frag_wane (fragP); | |
ee7fcc42 | 3938 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 3939 | } |
47926f60 KH |
3940 | /* Guess a short jump. */ |
3941 | return 1; | |
ee7fcc42 AM |
3942 | } |
3943 | ||
47926f60 KH |
3944 | /* Called after relax() is finished. |
3945 | ||
3946 | In: Address of frag. | |
3947 | fr_type == rs_machine_dependent. | |
3948 | fr_subtype is what the address relaxed to. | |
3949 | ||
3950 | Out: Any fixSs and constants are set up. | |
3951 | Caller will turn frag into a ".space 0". */ | |
3952 | ||
252b5132 RH |
3953 | #ifndef BFD_ASSEMBLER |
3954 | void | |
3955 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
3956 | object_headers *headers ATTRIBUTE_UNUSED; |
3957 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3958 | register fragS *fragP; |
3959 | #else | |
3960 | void | |
3961 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
3962 | bfd *abfd ATTRIBUTE_UNUSED; |
3963 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3964 | register fragS *fragP; |
3965 | #endif | |
3966 | { | |
3967 | register unsigned char *opcode; | |
3968 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
3969 | offsetT target_address; |
3970 | offsetT opcode_address; | |
252b5132 | 3971 | unsigned int extension = 0; |
847f7ad4 | 3972 | offsetT displacement_from_opcode_start; |
252b5132 RH |
3973 | |
3974 | opcode = (unsigned char *) fragP->fr_opcode; | |
3975 | ||
47926f60 | 3976 | /* Address we want to reach in file space. */ |
252b5132 | 3977 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
47926f60 KH |
3978 | #ifdef BFD_ASSEMBLER |
3979 | /* Not needed otherwise? */ | |
49309057 | 3980 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
3981 | #endif |
3982 | ||
47926f60 | 3983 | /* Address opcode resides at in file space. */ |
252b5132 RH |
3984 | opcode_address = fragP->fr_address + fragP->fr_fix; |
3985 | ||
47926f60 | 3986 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
3987 | displacement_from_opcode_start = target_address - opcode_address; |
3988 | ||
3989 | switch (fragP->fr_subtype) | |
3990 | { | |
3991 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): | |
3992 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
3993 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
3994 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
47926f60 KH |
3995 | /* Don't have to change opcode. */ |
3996 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 RH |
3997 | where_to_put_displacement = &opcode[1]; |
3998 | break; | |
3999 | ||
4000 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): | |
47926f60 | 4001 | extension = 5; /* 2 opcode + 4 displacement */ |
252b5132 RH |
4002 | opcode[1] = opcode[0] + 0x10; |
4003 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4004 | where_to_put_displacement = &opcode[2]; | |
4005 | break; | |
4006 | ||
4007 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
47926f60 | 4008 | extension = 4; /* 1 opcode + 4 displacement */ |
252b5132 RH |
4009 | opcode[0] = 0xe9; |
4010 | where_to_put_displacement = &opcode[1]; | |
4011 | break; | |
4012 | ||
4013 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): | |
47926f60 | 4014 | extension = 3; /* 2 opcode + 2 displacement */ |
252b5132 RH |
4015 | opcode[1] = opcode[0] + 0x10; |
4016 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4017 | where_to_put_displacement = &opcode[2]; | |
4018 | break; | |
4019 | ||
4020 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): | |
47926f60 | 4021 | extension = 2; /* 1 opcode + 2 displacement */ |
252b5132 RH |
4022 | opcode[0] = 0xe9; |
4023 | where_to_put_displacement = &opcode[1]; | |
4024 | break; | |
4025 | ||
4026 | default: | |
4027 | BAD_CASE (fragP->fr_subtype); | |
4028 | break; | |
4029 | } | |
47926f60 | 4030 | /* Now put displacement after opcode. */ |
252b5132 RH |
4031 | md_number_to_chars ((char *) where_to_put_displacement, |
4032 | (valueT) (displacement_from_opcode_start - extension), | |
4033 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
4034 | fragP->fr_fix += extension; | |
4035 | } | |
4036 | \f | |
47926f60 KH |
4037 | /* Size of byte displacement jmp. */ |
4038 | int md_short_jump_size = 2; | |
4039 | ||
4040 | /* Size of dword displacement jmp. */ | |
4041 | int md_long_jump_size = 5; | |
252b5132 | 4042 | |
47926f60 KH |
4043 | /* Size of relocation record. */ |
4044 | const int md_reloc_size = 8; | |
252b5132 RH |
4045 | |
4046 | void | |
4047 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4048 | char *ptr; | |
4049 | addressT from_addr, to_addr; | |
ab9da554 ILT |
4050 | fragS *frag ATTRIBUTE_UNUSED; |
4051 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4052 | { |
847f7ad4 | 4053 | offsetT offset; |
252b5132 RH |
4054 | |
4055 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
4056 | /* Opcode for byte-disp jump. */ |
4057 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
4058 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
4059 | } | |
4060 | ||
4061 | void | |
4062 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4063 | char *ptr; | |
4064 | addressT from_addr, to_addr; | |
a38cf1db AM |
4065 | fragS *frag ATTRIBUTE_UNUSED; |
4066 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4067 | { |
847f7ad4 | 4068 | offsetT offset; |
252b5132 | 4069 | |
a38cf1db AM |
4070 | offset = to_addr - (from_addr + 5); |
4071 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
4072 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
4073 | } |
4074 | \f | |
4075 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
4076 | by our caller that we have all the info we need to fix it up. | |
4077 | ||
4078 | On the 386, immediates, displacements, and data pointers are all in | |
4079 | the same (little-endian) format, so we don't need to care about which | |
4080 | we are handling. */ | |
4081 | ||
4082 | int | |
4083 | md_apply_fix3 (fixP, valp, seg) | |
47926f60 KH |
4084 | /* The fix we're to put in. */ |
4085 | fixS *fixP; | |
4086 | ||
4087 | /* Pointer to the value of the bits. */ | |
4088 | valueT *valp; | |
4089 | ||
4090 | /* Segment fix is from. */ | |
4091 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
4092 | { |
4093 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; | |
4094 | valueT value = *valp; | |
4095 | ||
e1b283bb | 4096 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
4097 | if (fixP->fx_pcrel) |
4098 | { | |
4099 | switch (fixP->fx_r_type) | |
4100 | { | |
5865bb77 ILT |
4101 | default: |
4102 | break; | |
4103 | ||
93382f6d AM |
4104 | case BFD_RELOC_32: |
4105 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4106 | break; | |
4107 | case BFD_RELOC_16: | |
4108 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4109 | break; | |
4110 | case BFD_RELOC_8: | |
4111 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4112 | break; | |
4113 | } | |
4114 | } | |
252b5132 | 4115 | |
0723899b ILT |
4116 | /* This is a hack. There should be a better way to handle this. |
4117 | This covers for the fact that bfd_install_relocation will | |
4118 | subtract the current location (for partial_inplace, PC relative | |
4119 | relocations); see more below. */ | |
93382f6d AM |
4120 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
4121 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4122 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
4123 | && fixP->fx_addsy) | |
252b5132 RH |
4124 | { |
4125 | #ifndef OBJ_AOUT | |
4126 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4127 | #ifdef TE_PE | |
4128 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4129 | #endif | |
4130 | ) | |
4131 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4132 | #endif | |
4133 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4134 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4135 | { |
2f66722d AM |
4136 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
4137 | ||
4138 | if ((fseg == seg | |
4139 | || (symbol_section_p (fixP->fx_addsy) | |
4140 | && fseg != absolute_section)) | |
4141 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
4142 | && ! S_IS_WEAK (fixP->fx_addsy) | |
4143 | && S_IS_DEFINED (fixP->fx_addsy) | |
4144 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
4145 | { | |
4146 | /* Yes, we add the values in twice. This is because | |
4147 | bfd_perform_relocation subtracts them out again. I think | |
4148 | bfd_perform_relocation is broken, but I don't dare change | |
4149 | it. FIXME. */ | |
4150 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4151 | } | |
252b5132 RH |
4152 | } |
4153 | #endif | |
4154 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4155 | /* For some reason, the PE format does not store a section | |
24eab124 | 4156 | address offset for a PC relative symbol. */ |
252b5132 RH |
4157 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4158 | value += md_pcrel_from (fixP); | |
4159 | #endif | |
4160 | } | |
4161 | ||
4162 | /* Fix a few things - the dynamic linker expects certain values here, | |
47926f60 | 4163 | and we must not dissappoint it. */ |
252b5132 RH |
4164 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4165 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4166 | && fixP->fx_addsy) | |
47926f60 KH |
4167 | switch (fixP->fx_r_type) |
4168 | { | |
4169 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 4170 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
4171 | /* Make the jump instruction point to the address of the operand. At |
4172 | runtime we merely add the offset to the actual PLT entry. */ | |
4173 | value = -4; | |
4174 | break; | |
4175 | case BFD_RELOC_386_GOTPC: | |
4176 | ||
4177 | /* This is tough to explain. We end up with this one if we have | |
252b5132 RH |
4178 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
4179 | * here is to obtain the absolute address of the GOT, and it is strongly | |
4180 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 4181 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 4182 | * something like: |
c3332e24 | 4183 | * |
24eab124 | 4184 | * call .L66 |
252b5132 | 4185 | * .L66: |
24eab124 AM |
4186 | * popl %ebx |
4187 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 4188 | * |
24eab124 | 4189 | * The call and pop essentially return the absolute address of |
252b5132 RH |
4190 | * the label .L66 and store it in %ebx. The linker itself will |
4191 | * ultimately change the first operand of the addl so that %ebx points to | |
4192 | * the GOT, but to keep things simple, the .o file must have this operand | |
4193 | * set so that it generates not the absolute address of .L66, but the | |
4194 | * absolute address of itself. This allows the linker itself simply | |
4195 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
4196 | * added in, and the addend of the relocation is stored in the operand | |
4197 | * field for the instruction itself. | |
c3332e24 | 4198 | * |
24eab124 | 4199 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
4200 | * offset so that %ebx would point to itself. The thing that is tricky is |
4201 | * that .-.L66 will point to the beginning of the instruction, so we need | |
4202 | * to further modify the operand so that it will point to itself. | |
4203 | * There are other cases where you have something like: | |
c3332e24 | 4204 | * |
24eab124 | 4205 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 4206 | * |
252b5132 | 4207 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 4208 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
4209 | * explicitly mentioned, and I wonder whether it would simplify matters |
4210 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
4211 | * the pcrel_adjust field was used to store the correction, but since the | |
47926f60 KH |
4212 | * expression is not pcrel, I felt it would be confusing to do it this |
4213 | * way. */ | |
4214 | ||
4215 | value -= 1; | |
4216 | break; | |
4217 | case BFD_RELOC_386_GOT32: | |
3e73aa7c | 4218 | case BFD_RELOC_X86_64_GOT32: |
47926f60 KH |
4219 | value = 0; /* Fully resolved at runtime. No addend. */ |
4220 | break; | |
4221 | case BFD_RELOC_386_GOTOFF: | |
3e73aa7c | 4222 | case BFD_RELOC_X86_64_GOTPCREL: |
47926f60 KH |
4223 | break; |
4224 | ||
4225 | case BFD_RELOC_VTABLE_INHERIT: | |
4226 | case BFD_RELOC_VTABLE_ENTRY: | |
4227 | fixP->fx_done = 0; | |
4228 | return 1; | |
4229 | ||
4230 | default: | |
4231 | break; | |
4232 | } | |
4233 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
93382f6d | 4234 | *valp = value; |
47926f60 | 4235 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
3e73aa7c JH |
4236 | |
4237 | #ifndef BFD_ASSEMBLER | |
252b5132 | 4238 | md_number_to_chars (p, value, fixP->fx_size); |
3e73aa7c JH |
4239 | #else |
4240 | /* Are we finished with this relocation now? */ | |
4241 | if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0) | |
4242 | fixP->fx_done = 1; | |
4243 | else if (use_rela_relocations) | |
4244 | { | |
4245 | fixP->fx_no_overflow = 1; | |
4246 | value = 0; | |
4247 | } | |
4248 | md_number_to_chars (p, value, fixP->fx_size); | |
4249 | #endif | |
252b5132 RH |
4250 | |
4251 | return 1; | |
4252 | } | |
252b5132 | 4253 | \f |
252b5132 RH |
4254 | #define MAX_LITTLENUMS 6 |
4255 | ||
47926f60 KH |
4256 | /* Turn the string pointed to by litP into a floating point constant |
4257 | of type TYPE, and emit the appropriate bytes. The number of | |
4258 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4259 | returned, or NULL on OK. */ | |
4260 | ||
252b5132 RH |
4261 | char * |
4262 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4263 | int type; |
252b5132 RH |
4264 | char *litP; |
4265 | int *sizeP; | |
4266 | { | |
4267 | int prec; | |
4268 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4269 | LITTLENUM_TYPE *wordP; | |
4270 | char *t; | |
4271 | ||
4272 | switch (type) | |
4273 | { | |
4274 | case 'f': | |
4275 | case 'F': | |
4276 | prec = 2; | |
4277 | break; | |
4278 | ||
4279 | case 'd': | |
4280 | case 'D': | |
4281 | prec = 4; | |
4282 | break; | |
4283 | ||
4284 | case 'x': | |
4285 | case 'X': | |
4286 | prec = 5; | |
4287 | break; | |
4288 | ||
4289 | default: | |
4290 | *sizeP = 0; | |
4291 | return _("Bad call to md_atof ()"); | |
4292 | } | |
4293 | t = atof_ieee (input_line_pointer, type, words); | |
4294 | if (t) | |
4295 | input_line_pointer = t; | |
4296 | ||
4297 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4298 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4299 | the bigendian 386. */ | |
4300 | for (wordP = words + prec - 1; prec--;) | |
4301 | { | |
4302 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4303 | litP += sizeof (LITTLENUM_TYPE); | |
4304 | } | |
4305 | return 0; | |
4306 | } | |
4307 | \f | |
4308 | char output_invalid_buf[8]; | |
4309 | ||
252b5132 RH |
4310 | static char * |
4311 | output_invalid (c) | |
4312 | int c; | |
4313 | { | |
4314 | if (isprint (c)) | |
4315 | sprintf (output_invalid_buf, "'%c'", c); | |
4316 | else | |
4317 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4318 | return output_invalid_buf; | |
4319 | } | |
4320 | ||
af6bdddf | 4321 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4322 | |
4323 | static const reg_entry * | |
4324 | parse_register (reg_string, end_op) | |
4325 | char *reg_string; | |
4326 | char **end_op; | |
4327 | { | |
af6bdddf AM |
4328 | char *s = reg_string; |
4329 | char *p; | |
252b5132 RH |
4330 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4331 | const reg_entry *r; | |
4332 | ||
4333 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4334 | if (*s == REGISTER_PREFIX) | |
4335 | ++s; | |
4336 | ||
4337 | if (is_space_char (*s)) | |
4338 | ++s; | |
4339 | ||
4340 | p = reg_name_given; | |
af6bdddf | 4341 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4342 | { |
4343 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4344 | return (const reg_entry *) NULL; |
4345 | s++; | |
252b5132 RH |
4346 | } |
4347 | ||
6588847e DN |
4348 | /* For naked regs, make sure that we are not dealing with an identifier. |
4349 | This prevents confusing an identifier like `eax_var' with register | |
4350 | `eax'. */ | |
4351 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
4352 | return (const reg_entry *) NULL; | |
4353 | ||
af6bdddf | 4354 | *end_op = s; |
252b5132 RH |
4355 | |
4356 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4357 | ||
5f47d35b | 4358 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4359 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4360 | { |
5f47d35b AM |
4361 | if (is_space_char (*s)) |
4362 | ++s; | |
4363 | if (*s == '(') | |
4364 | { | |
af6bdddf | 4365 | ++s; |
5f47d35b AM |
4366 | if (is_space_char (*s)) |
4367 | ++s; | |
4368 | if (*s >= '0' && *s <= '7') | |
4369 | { | |
4370 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4371 | ++s; |
5f47d35b AM |
4372 | if (is_space_char (*s)) |
4373 | ++s; | |
4374 | if (*s == ')') | |
4375 | { | |
4376 | *end_op = s + 1; | |
4377 | return r; | |
4378 | } | |
5f47d35b | 4379 | } |
47926f60 | 4380 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
4381 | return (const reg_entry *) NULL; |
4382 | } | |
4383 | } | |
4384 | ||
252b5132 RH |
4385 | return r; |
4386 | } | |
4387 | \f | |
4cc782b5 | 4388 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
65172ab8 | 4389 | const char *md_shortopts = "kVQ:sq"; |
252b5132 | 4390 | #else |
65172ab8 | 4391 | const char *md_shortopts = "q"; |
252b5132 | 4392 | #endif |
6e0b89ee | 4393 | |
252b5132 | 4394 | struct option md_longopts[] = { |
3e73aa7c JH |
4395 | #define OPTION_32 (OPTION_MD_BASE + 0) |
4396 | {"32", no_argument, NULL, OPTION_32}, | |
6e0b89ee | 4397 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3e73aa7c JH |
4398 | #define OPTION_64 (OPTION_MD_BASE + 1) |
4399 | {"64", no_argument, NULL, OPTION_64}, | |
6e0b89ee | 4400 | #endif |
252b5132 RH |
4401 | {NULL, no_argument, NULL, 0} |
4402 | }; | |
4403 | size_t md_longopts_size = sizeof (md_longopts); | |
4404 | ||
4405 | int | |
4406 | md_parse_option (c, arg) | |
4407 | int c; | |
ab9da554 | 4408 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4409 | { |
4410 | switch (c) | |
4411 | { | |
a38cf1db AM |
4412 | case 'q': |
4413 | quiet_warnings = 1; | |
252b5132 RH |
4414 | break; |
4415 | ||
4416 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4417 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4418 | should be emitted or not. FIXME: Not implemented. */ | |
4419 | case 'Q': | |
252b5132 RH |
4420 | break; |
4421 | ||
4422 | /* -V: SVR4 argument to print version ID. */ | |
4423 | case 'V': | |
4424 | print_version_id (); | |
4425 | break; | |
4426 | ||
a38cf1db AM |
4427 | /* -k: Ignore for FreeBSD compatibility. */ |
4428 | case 'k': | |
252b5132 | 4429 | break; |
4cc782b5 ILT |
4430 | |
4431 | case 's': | |
4432 | /* -s: On i386 Solaris, this tells the native assembler to use | |
4433 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
4434 | break; | |
6e0b89ee | 4435 | |
3e73aa7c JH |
4436 | case OPTION_64: |
4437 | { | |
4438 | const char **list, **l; | |
4439 | ||
3e73aa7c JH |
4440 | list = bfd_target_list (); |
4441 | for (l = list; *l != NULL; l++) | |
6e0b89ee AM |
4442 | if (strcmp (*l, "elf64-x86-64") == 0) |
4443 | { | |
4444 | default_arch = "x86_64"; | |
4445 | break; | |
4446 | } | |
3e73aa7c | 4447 | if (*l == NULL) |
6e0b89ee | 4448 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
4449 | free (list); |
4450 | } | |
4451 | break; | |
4452 | #endif | |
252b5132 | 4453 | |
6e0b89ee AM |
4454 | case OPTION_32: |
4455 | default_arch = "i386"; | |
4456 | break; | |
4457 | ||
252b5132 RH |
4458 | default: |
4459 | return 0; | |
4460 | } | |
4461 | return 1; | |
4462 | } | |
4463 | ||
4464 | void | |
4465 | md_show_usage (stream) | |
4466 | FILE *stream; | |
4467 | { | |
4cc782b5 ILT |
4468 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4469 | fprintf (stream, _("\ | |
a38cf1db AM |
4470 | -Q ignored\n\ |
4471 | -V print assembler version number\n\ | |
4472 | -k ignored\n\ | |
4473 | -q quieten some warnings\n\ | |
4474 | -s ignored\n")); | |
4475 | #else | |
4476 | fprintf (stream, _("\ | |
4477 | -q quieten some warnings\n")); | |
4cc782b5 | 4478 | #endif |
252b5132 RH |
4479 | } |
4480 | ||
4481 | #ifdef BFD_ASSEMBLER | |
3e73aa7c JH |
4482 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
4483 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
252b5132 RH |
4484 | |
4485 | /* Pick the target format to use. */ | |
4486 | ||
47926f60 | 4487 | const char * |
252b5132 RH |
4488 | i386_target_format () |
4489 | { | |
3e73aa7c JH |
4490 | if (!strcmp (default_arch, "x86_64")) |
4491 | set_code_flag (CODE_64BIT); | |
4492 | else if (!strcmp (default_arch, "i386")) | |
4493 | set_code_flag (CODE_32BIT); | |
4494 | else | |
4495 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
4496 | switch (OUTPUT_FLAVOR) |
4497 | { | |
4c63da97 AM |
4498 | #ifdef OBJ_MAYBE_AOUT |
4499 | case bfd_target_aout_flavour: | |
47926f60 | 4500 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
4501 | #endif |
4502 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
4503 | case bfd_target_coff_flavour: |
4504 | return "coff-i386"; | |
4c63da97 | 4505 | #endif |
3e73aa7c | 4506 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 4507 | case bfd_target_elf_flavour: |
3e73aa7c | 4508 | { |
e5cb08ac KH |
4509 | if (flag_code == CODE_64BIT) |
4510 | use_rela_relocations = 1; | |
4511 | return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386"; | |
3e73aa7c | 4512 | } |
4c63da97 | 4513 | #endif |
252b5132 RH |
4514 | default: |
4515 | abort (); | |
4516 | return NULL; | |
4517 | } | |
4518 | } | |
4519 | ||
47926f60 KH |
4520 | #endif /* OBJ_MAYBE_ more than one */ |
4521 | #endif /* BFD_ASSEMBLER */ | |
252b5132 | 4522 | \f |
252b5132 RH |
4523 | symbolS * |
4524 | md_undefined_symbol (name) | |
4525 | char *name; | |
4526 | { | |
18dc2407 ILT |
4527 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
4528 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
4529 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
4530 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
4531 | { |
4532 | if (!GOT_symbol) | |
4533 | { | |
4534 | if (symbol_find (name)) | |
4535 | as_bad (_("GOT already in symbol table")); | |
4536 | GOT_symbol = symbol_new (name, undefined_section, | |
4537 | (valueT) 0, &zero_address_frag); | |
4538 | }; | |
4539 | return GOT_symbol; | |
4540 | } | |
252b5132 RH |
4541 | return 0; |
4542 | } | |
4543 | ||
4544 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 4545 | |
252b5132 RH |
4546 | valueT |
4547 | md_section_align (segment, size) | |
ab9da554 | 4548 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
4549 | valueT size; |
4550 | { | |
252b5132 | 4551 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
4552 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4553 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
4554 | { | |
4555 | /* For a.out, force the section size to be aligned. If we don't do | |
4556 | this, BFD will align it for us, but it will not write out the | |
4557 | final bytes of the section. This may be a bug in BFD, but it is | |
4558 | easier to fix it here since that is how the other a.out targets | |
4559 | work. */ | |
4560 | int align; | |
4561 | ||
4562 | align = bfd_get_section_alignment (stdoutput, segment); | |
4563 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4564 | } | |
252b5132 RH |
4565 | #endif |
4566 | #endif | |
4567 | ||
4568 | return size; | |
4569 | } | |
4570 | ||
4571 | /* On the i386, PC-relative offsets are relative to the start of the | |
4572 | next instruction. That is, the address of the offset, plus its | |
4573 | size, since the offset is always the last part of the insn. */ | |
4574 | ||
4575 | long | |
4576 | md_pcrel_from (fixP) | |
4577 | fixS *fixP; | |
4578 | { | |
4579 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4580 | } | |
4581 | ||
4582 | #ifndef I386COFF | |
4583 | ||
4584 | static void | |
4585 | s_bss (ignore) | |
ab9da554 | 4586 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4587 | { |
4588 | register int temp; | |
4589 | ||
4590 | temp = get_absolute_expression (); | |
4591 | subseg_set (bss_section, (subsegT) temp); | |
4592 | demand_empty_rest_of_line (); | |
4593 | } | |
4594 | ||
4595 | #endif | |
4596 | ||
252b5132 RH |
4597 | #ifdef BFD_ASSEMBLER |
4598 | ||
4599 | void | |
4600 | i386_validate_fix (fixp) | |
4601 | fixS *fixp; | |
4602 | { | |
4603 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4604 | { | |
3e73aa7c | 4605 | /* GOTOFF relocation are nonsense in 64bit mode. */ |
23df1078 JH |
4606 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
4607 | { | |
4608 | if (flag_code != CODE_64BIT) | |
4609 | abort (); | |
4610 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
4611 | } | |
4612 | else | |
4613 | { | |
4614 | if (flag_code == CODE_64BIT) | |
4615 | abort (); | |
4616 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4617 | } | |
252b5132 RH |
4618 | fixp->fx_subsy = 0; |
4619 | } | |
4620 | } | |
4621 | ||
252b5132 RH |
4622 | arelent * |
4623 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4624 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4625 | fixS *fixp; |
4626 | { | |
4627 | arelent *rel; | |
4628 | bfd_reloc_code_real_type code; | |
4629 | ||
4630 | switch (fixp->fx_r_type) | |
4631 | { | |
3e73aa7c JH |
4632 | case BFD_RELOC_X86_64_PLT32: |
4633 | case BFD_RELOC_X86_64_GOT32: | |
4634 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
4635 | case BFD_RELOC_386_PLT32: |
4636 | case BFD_RELOC_386_GOT32: | |
4637 | case BFD_RELOC_386_GOTOFF: | |
4638 | case BFD_RELOC_386_GOTPC: | |
3e73aa7c | 4639 | case BFD_RELOC_X86_64_32S: |
252b5132 RH |
4640 | case BFD_RELOC_RVA: |
4641 | case BFD_RELOC_VTABLE_ENTRY: | |
4642 | case BFD_RELOC_VTABLE_INHERIT: | |
4643 | code = fixp->fx_r_type; | |
4644 | break; | |
4645 | default: | |
93382f6d | 4646 | if (fixp->fx_pcrel) |
252b5132 | 4647 | { |
93382f6d AM |
4648 | switch (fixp->fx_size) |
4649 | { | |
4650 | default: | |
d0b47220 | 4651 | as_bad (_("can not do %d byte pc-relative relocation"), |
93382f6d AM |
4652 | fixp->fx_size); |
4653 | code = BFD_RELOC_32_PCREL; | |
4654 | break; | |
4655 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4656 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4657 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4658 | } | |
4659 | } | |
4660 | else | |
4661 | { | |
4662 | switch (fixp->fx_size) | |
4663 | { | |
4664 | default: | |
d0b47220 | 4665 | as_bad (_("can not do %d byte relocation"), fixp->fx_size); |
93382f6d AM |
4666 | code = BFD_RELOC_32; |
4667 | break; | |
4668 | case 1: code = BFD_RELOC_8; break; | |
4669 | case 2: code = BFD_RELOC_16; break; | |
4670 | case 4: code = BFD_RELOC_32; break; | |
3e73aa7c | 4671 | case 8: code = BFD_RELOC_64; break; |
93382f6d | 4672 | } |
252b5132 RH |
4673 | } |
4674 | break; | |
4675 | } | |
252b5132 RH |
4676 | |
4677 | if (code == BFD_RELOC_32 | |
4678 | && GOT_symbol | |
4679 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c JH |
4680 | { |
4681 | /* We don't support GOTPC on 64bit targets. */ | |
4682 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 4683 | abort (); |
3e73aa7c JH |
4684 | code = BFD_RELOC_386_GOTPC; |
4685 | } | |
252b5132 RH |
4686 | |
4687 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4688 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4689 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4690 | |
4691 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
3e73aa7c JH |
4692 | if (!use_rela_relocations) |
4693 | { | |
4694 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4695 | vtable entry to be used in the relocation's section offset. */ | |
4696 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4697 | rel->address = fixp->fx_offset; | |
252b5132 | 4698 | |
3e73aa7c JH |
4699 | if (fixp->fx_pcrel) |
4700 | rel->addend = fixp->fx_addnumber; | |
4701 | else | |
4702 | rel->addend = 0; | |
4703 | } | |
4704 | /* Use the rela in 64bit mode. */ | |
252b5132 | 4705 | else |
3e73aa7c JH |
4706 | { |
4707 | rel->addend = fixp->fx_offset; | |
4708 | #ifdef OBJ_ELF | |
4709 | /* Ohhh, this is ugly. The problem is that if this is a local global | |
4710 | symbol, the relocation will entirely be performed at link time, not | |
4711 | at assembly time. bfd_perform_reloc doesn't know about this sort | |
4712 | of thing, and as a result we need to fake it out here. */ | |
4713 | if ((S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)) | |
e5cb08ac | 4714 | && !S_IS_COMMON (fixp->fx_addsy)) |
3e73aa7c JH |
4715 | rel->addend -= symbol_get_bfdsym (fixp->fx_addsy)->value; |
4716 | #endif | |
4717 | if (fixp->fx_pcrel) | |
4718 | rel->addend -= fixp->fx_size; | |
4719 | } | |
4720 | ||
252b5132 RH |
4721 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
4722 | if (rel->howto == NULL) | |
4723 | { | |
4724 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4725 | _("cannot represent relocation type %s"), |
252b5132 RH |
4726 | bfd_get_reloc_code_name (code)); |
4727 | /* Set howto to a garbage value so that we can keep going. */ | |
4728 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4729 | assert (rel->howto != NULL); | |
4730 | } | |
4731 | ||
4732 | return rel; | |
4733 | } | |
4734 | ||
47926f60 | 4735 | #else /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4736 | |
4737 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4738 | void | |
4739 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4740 | char *where; | |
4741 | fixS *fixP; | |
4742 | relax_addressT segment_address_in_file; | |
4743 | { | |
47926f60 KH |
4744 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
4745 | Out: GNU LD relocation length code: 0, 1, or 2. */ | |
252b5132 | 4746 | |
47926f60 | 4747 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
252b5132 RH |
4748 | long r_symbolnum; |
4749 | ||
4750 | know (fixP->fx_addsy != NULL); | |
4751 | ||
4752 | md_number_to_chars (where, | |
4753 | (valueT) (fixP->fx_frag->fr_address | |
4754 | + fixP->fx_where - segment_address_in_file), | |
4755 | 4); | |
4756 | ||
4757 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4758 | ? S_GET_TYPE (fixP->fx_addsy) | |
4759 | : fixP->fx_addsy->sy_number); | |
4760 | ||
4761 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4762 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4763 | where[4] = r_symbolnum & 0x0ff; | |
4764 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4765 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4766 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4767 | } | |
4768 | ||
47926f60 | 4769 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
252b5132 RH |
4770 | |
4771 | #if defined (I386COFF) | |
4772 | ||
4773 | short | |
4774 | tc_coff_fix2rtype (fixP) | |
4775 | fixS *fixP; | |
4776 | { | |
4777 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4778 | return R_IMAGEBASE; | |
4779 | ||
4780 | return (fixP->fx_pcrel ? | |
4781 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4782 | fixP->fx_size == 2 ? R_PCRWORD : | |
4783 | R_PCRLONG) : | |
4784 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4785 | fixP->fx_size == 2 ? R_RELWORD : | |
4786 | R_DIR32)); | |
4787 | } | |
4788 | ||
4789 | int | |
4790 | tc_coff_sizemachdep (frag) | |
4791 | fragS *frag; | |
4792 | { | |
4793 | if (frag->fr_next) | |
4794 | return (frag->fr_next->fr_address - frag->fr_address); | |
4795 | else | |
4796 | return 0; | |
4797 | } | |
4798 | ||
47926f60 | 4799 | #endif /* I386COFF */ |
252b5132 | 4800 | |
47926f60 | 4801 | #endif /* ! BFD_ASSEMBLER */ |
64a0c779 DN |
4802 | \f |
4803 | /* Parse operands using Intel syntax. This implements a recursive descent | |
4804 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
4805 | Programmer's Guide. | |
4806 | ||
4807 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
4808 | documentation. In particular, all the structure/union and | |
4809 | high-level macro operands are missing. | |
4810 | ||
4811 | Uppercase words are terminals, lower case words are non-terminals. | |
4812 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
4813 | bars '|' denote choices. Most grammar productions are implemented in | |
4814 | functions called 'intel_<production>'. | |
4815 | ||
4816 | Initial production is 'expr'. | |
4817 | ||
64a0c779 DN |
4818 | addOp + | - |
4819 | ||
4820 | alpha [a-zA-Z] | |
4821 | ||
4822 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH | |
4823 | ||
4824 | constant digits [[ radixOverride ]] | |
4825 | ||
4826 | dataType BYTE | WORD | DWORD | QWORD | XWORD | |
4827 | ||
4828 | digits decdigit | |
b77a7acd AJ |
4829 | | digits decdigit |
4830 | | digits hexdigit | |
64a0c779 DN |
4831 | |
4832 | decdigit [0-9] | |
4833 | ||
4834 | e05 e05 addOp e06 | |
b77a7acd | 4835 | | e06 |
64a0c779 DN |
4836 | |
4837 | e06 e06 mulOp e09 | |
b77a7acd | 4838 | | e09 |
64a0c779 DN |
4839 | |
4840 | e09 OFFSET e10 | |
4841 | | e09 PTR e10 | |
4842 | | e09 : e10 | |
4843 | | e10 | |
4844 | ||
4845 | e10 e10 [ expr ] | |
b77a7acd | 4846 | | e11 |
64a0c779 DN |
4847 | |
4848 | e11 ( expr ) | |
b77a7acd | 4849 | | [ expr ] |
64a0c779 DN |
4850 | | constant |
4851 | | dataType | |
4852 | | id | |
4853 | | $ | |
4854 | | register | |
4855 | ||
4856 | => expr SHORT e05 | |
b77a7acd | 4857 | | e05 |
64a0c779 DN |
4858 | |
4859 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 4860 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
4861 | |
4862 | hexdigit a | b | c | d | e | f | |
b77a7acd | 4863 | | A | B | C | D | E | F |
64a0c779 DN |
4864 | |
4865 | id alpha | |
b77a7acd | 4866 | | id alpha |
64a0c779 DN |
4867 | | id decdigit |
4868 | ||
4869 | mulOp * | / | MOD | |
4870 | ||
4871 | quote " | ' | |
4872 | ||
4873 | register specialRegister | |
b77a7acd | 4874 | | gpRegister |
64a0c779 DN |
4875 | | byteRegister |
4876 | ||
4877 | segmentRegister CS | DS | ES | FS | GS | SS | |
4878 | ||
4879 | specialRegister CR0 | CR2 | CR3 | |
b77a7acd | 4880 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
4881 | | TR3 | TR4 | TR5 | TR6 | TR7 |
4882 | ||
64a0c779 DN |
4883 | We simplify the grammar in obvious places (e.g., register parsing is |
4884 | done by calling parse_register) and eliminate immediate left recursion | |
4885 | to implement a recursive-descent parser. | |
4886 | ||
4887 | expr SHORT e05 | |
b77a7acd | 4888 | | e05 |
64a0c779 DN |
4889 | |
4890 | e05 e06 e05' | |
4891 | ||
4892 | e05' addOp e06 e05' | |
b77a7acd | 4893 | | Empty |
64a0c779 DN |
4894 | |
4895 | e06 e09 e06' | |
4896 | ||
4897 | e06' mulOp e09 e06' | |
b77a7acd | 4898 | | Empty |
64a0c779 DN |
4899 | |
4900 | e09 OFFSET e10 e09' | |
b77a7acd | 4901 | | e10 e09' |
64a0c779 DN |
4902 | |
4903 | e09' PTR e10 e09' | |
b77a7acd | 4904 | | : e10 e09' |
64a0c779 DN |
4905 | | Empty |
4906 | ||
4907 | e10 e11 e10' | |
4908 | ||
4909 | e10' [ expr ] e10' | |
b77a7acd | 4910 | | Empty |
64a0c779 DN |
4911 | |
4912 | e11 ( expr ) | |
b77a7acd | 4913 | | [ expr ] |
64a0c779 DN |
4914 | | BYTE |
4915 | | WORD | |
4916 | | DWORD | |
4917 | | QWORD | |
4918 | | XWORD | |
4919 | | . | |
4920 | | $ | |
4921 | | register | |
4922 | | id | |
4923 | | constant */ | |
4924 | ||
4925 | /* Parsing structure for the intel syntax parser. Used to implement the | |
4926 | semantic actions for the operand grammar. */ | |
4927 | struct intel_parser_s | |
4928 | { | |
4929 | char *op_string; /* The string being parsed. */ | |
4930 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 4931 | int op_modifier; /* Operand modifier. */ |
64a0c779 DN |
4932 | int is_mem; /* 1 if operand is memory reference. */ |
4933 | const reg_entry *reg; /* Last register reference found. */ | |
4934 | char *disp; /* Displacement string being built. */ | |
4935 | }; | |
4936 | ||
4937 | static struct intel_parser_s intel_parser; | |
4938 | ||
4939 | /* Token structure for parsing intel syntax. */ | |
4940 | struct intel_token | |
4941 | { | |
4942 | int code; /* Token code. */ | |
4943 | const reg_entry *reg; /* Register entry for register tokens. */ | |
4944 | char *str; /* String representation. */ | |
4945 | }; | |
4946 | ||
4947 | static struct intel_token cur_token, prev_token; | |
4948 | ||
50705ef4 AM |
4949 | /* Token codes for the intel parser. Since T_SHORT is already used |
4950 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
4951 | #define T_NIL -1 |
4952 | #define T_CONST 1 | |
4953 | #define T_REG 2 | |
4954 | #define T_BYTE 3 | |
4955 | #define T_WORD 4 | |
4956 | #define T_DWORD 5 | |
4957 | #define T_QWORD 6 | |
4958 | #define T_XWORD 7 | |
50705ef4 | 4959 | #undef T_SHORT |
64a0c779 DN |
4960 | #define T_SHORT 8 |
4961 | #define T_OFFSET 9 | |
4962 | #define T_PTR 10 | |
4963 | #define T_ID 11 | |
4964 | ||
4965 | /* Prototypes for intel parser functions. */ | |
4966 | static int intel_match_token PARAMS ((int code)); | |
cce0cbdc DN |
4967 | static void intel_get_token PARAMS ((void)); |
4968 | static void intel_putback_token PARAMS ((void)); | |
4969 | static int intel_expr PARAMS ((void)); | |
4970 | static int intel_e05 PARAMS ((void)); | |
4971 | static int intel_e05_1 PARAMS ((void)); | |
4972 | static int intel_e06 PARAMS ((void)); | |
4973 | static int intel_e06_1 PARAMS ((void)); | |
4974 | static int intel_e09 PARAMS ((void)); | |
4975 | static int intel_e09_1 PARAMS ((void)); | |
4976 | static int intel_e10 PARAMS ((void)); | |
4977 | static int intel_e10_1 PARAMS ((void)); | |
4978 | static int intel_e11 PARAMS ((void)); | |
64a0c779 | 4979 | |
64a0c779 DN |
4980 | static int |
4981 | i386_intel_operand (operand_string, got_a_float) | |
4982 | char *operand_string; | |
4983 | int got_a_float; | |
4984 | { | |
4985 | int ret; | |
4986 | char *p; | |
4987 | ||
4988 | /* Initialize token holders. */ | |
4989 | cur_token.code = prev_token.code = T_NIL; | |
4990 | cur_token.reg = prev_token.reg = NULL; | |
4991 | cur_token.str = prev_token.str = NULL; | |
4992 | ||
4993 | /* Initialize parser structure. */ | |
e5cb08ac | 4994 | p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
4995 | if (p == NULL) |
4996 | abort (); | |
4997 | strcpy (intel_parser.op_string, operand_string); | |
4998 | intel_parser.got_a_float = got_a_float; | |
4999 | intel_parser.op_modifier = -1; | |
5000 | intel_parser.is_mem = 0; | |
5001 | intel_parser.reg = NULL; | |
e5cb08ac | 5002 | intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5003 | if (intel_parser.disp == NULL) |
5004 | abort (); | |
5005 | intel_parser.disp[0] = '\0'; | |
5006 | ||
5007 | /* Read the first token and start the parser. */ | |
5008 | intel_get_token (); | |
5009 | ret = intel_expr (); | |
5010 | ||
5011 | if (ret) | |
5012 | { | |
5013 | /* If we found a memory reference, hand it over to i386_displacement | |
5014 | to fill in the rest of the operand fields. */ | |
5015 | if (intel_parser.is_mem) | |
5016 | { | |
5017 | if ((i.mem_operands == 1 | |
5018 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
5019 | || i.mem_operands == 2) | |
5020 | { | |
5021 | as_bad (_("too many memory references for '%s'"), | |
5022 | current_templates->start->name); | |
5023 | ret = 0; | |
5024 | } | |
5025 | else | |
5026 | { | |
5027 | char *s = intel_parser.disp; | |
5028 | i.mem_operands++; | |
5029 | ||
5030 | /* Add the displacement expression. */ | |
5031 | if (*s != '\0') | |
5032 | ret = i386_displacement (s, s + strlen (s)) | |
5033 | && i386_index_check (s); | |
5034 | } | |
5035 | } | |
5036 | ||
5037 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
5038 | else if (intel_parser.op_modifier == OFFSET_FLAT | |
5039 | || intel_parser.reg == NULL) | |
5040 | ret = i386_immediate (intel_parser.disp); | |
5041 | } | |
5042 | ||
5043 | free (p); | |
5044 | free (intel_parser.disp); | |
5045 | ||
5046 | return ret; | |
5047 | } | |
5048 | ||
64a0c779 | 5049 | /* expr SHORT e05 |
b77a7acd | 5050 | | e05 */ |
64a0c779 DN |
5051 | static int |
5052 | intel_expr () | |
5053 | { | |
5054 | /* expr SHORT e05 */ | |
5055 | if (cur_token.code == T_SHORT) | |
5056 | { | |
5057 | intel_parser.op_modifier = SHORT; | |
5058 | intel_match_token (T_SHORT); | |
5059 | ||
5060 | return (intel_e05 ()); | |
5061 | } | |
5062 | ||
5063 | /* expr e05 */ | |
5064 | else | |
5065 | return intel_e05 (); | |
5066 | } | |
5067 | ||
64a0c779 DN |
5068 | /* e05 e06 e05' |
5069 | ||
4a1805b1 | 5070 | e05' addOp e06 e05' |
64a0c779 DN |
5071 | | Empty */ |
5072 | static int | |
5073 | intel_e05 () | |
5074 | { | |
5075 | return (intel_e06 () && intel_e05_1 ()); | |
5076 | } | |
5077 | ||
5078 | static int | |
5079 | intel_e05_1 () | |
5080 | { | |
5081 | /* e05' addOp e06 e05' */ | |
5082 | if (cur_token.code == '+' || cur_token.code == '-') | |
5083 | { | |
5084 | strcat (intel_parser.disp, cur_token.str); | |
5085 | intel_match_token (cur_token.code); | |
5086 | ||
5087 | return (intel_e06 () && intel_e05_1 ()); | |
5088 | } | |
5089 | ||
5090 | /* e05' Empty */ | |
5091 | else | |
5092 | return 1; | |
4a1805b1 | 5093 | } |
64a0c779 DN |
5094 | |
5095 | /* e06 e09 e06' | |
5096 | ||
5097 | e06' mulOp e09 e06' | |
b77a7acd | 5098 | | Empty */ |
64a0c779 DN |
5099 | static int |
5100 | intel_e06 () | |
5101 | { | |
5102 | return (intel_e09 () && intel_e06_1 ()); | |
5103 | } | |
5104 | ||
5105 | static int | |
5106 | intel_e06_1 () | |
5107 | { | |
5108 | /* e06' mulOp e09 e06' */ | |
5109 | if (cur_token.code == '*' || cur_token.code == '/') | |
5110 | { | |
5111 | strcat (intel_parser.disp, cur_token.str); | |
5112 | intel_match_token (cur_token.code); | |
5113 | ||
5114 | return (intel_e09 () && intel_e06_1 ()); | |
5115 | } | |
4a1805b1 | 5116 | |
64a0c779 | 5117 | /* e06' Empty */ |
4a1805b1 | 5118 | else |
64a0c779 DN |
5119 | return 1; |
5120 | } | |
5121 | ||
64a0c779 | 5122 | /* e09 OFFSET e10 e09' |
b77a7acd | 5123 | | e10 e09' |
64a0c779 DN |
5124 | |
5125 | e09' PTR e10 e09' | |
b77a7acd | 5126 | | : e10 e09' |
64a0c779 DN |
5127 | | Empty */ |
5128 | static int | |
5129 | intel_e09 () | |
5130 | { | |
5131 | /* e09 OFFSET e10 e09' */ | |
5132 | if (cur_token.code == T_OFFSET) | |
5133 | { | |
5134 | intel_parser.is_mem = 0; | |
5135 | intel_parser.op_modifier = OFFSET_FLAT; | |
5136 | intel_match_token (T_OFFSET); | |
5137 | ||
5138 | return (intel_e10 () && intel_e09_1 ()); | |
5139 | } | |
5140 | ||
5141 | /* e09 e10 e09' */ | |
5142 | else | |
5143 | return (intel_e10 () && intel_e09_1 ()); | |
5144 | } | |
5145 | ||
5146 | static int | |
5147 | intel_e09_1 () | |
5148 | { | |
5149 | /* e09' PTR e10 e09' */ | |
5150 | if (cur_token.code == T_PTR) | |
5151 | { | |
5152 | if (prev_token.code == T_BYTE) | |
5153 | i.suffix = BYTE_MNEM_SUFFIX; | |
5154 | ||
5155 | else if (prev_token.code == T_WORD) | |
5156 | { | |
5157 | if (intel_parser.got_a_float == 2) /* "fi..." */ | |
5158 | i.suffix = SHORT_MNEM_SUFFIX; | |
5159 | else | |
5160 | i.suffix = WORD_MNEM_SUFFIX; | |
5161 | } | |
5162 | ||
5163 | else if (prev_token.code == T_DWORD) | |
5164 | { | |
5165 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5166 | i.suffix = SHORT_MNEM_SUFFIX; | |
5167 | else | |
5168 | i.suffix = LONG_MNEM_SUFFIX; | |
5169 | } | |
5170 | ||
5171 | else if (prev_token.code == T_QWORD) | |
f16b83df JH |
5172 | { |
5173 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5174 | i.suffix = LONG_MNEM_SUFFIX; | |
5175 | else | |
3e73aa7c | 5176 | i.suffix = QWORD_MNEM_SUFFIX; |
f16b83df | 5177 | } |
64a0c779 DN |
5178 | |
5179 | else if (prev_token.code == T_XWORD) | |
5180 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5181 | ||
5182 | else | |
5183 | { | |
5184 | as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str); | |
5185 | return 0; | |
5186 | } | |
5187 | ||
5188 | intel_match_token (T_PTR); | |
5189 | ||
5190 | return (intel_e10 () && intel_e09_1 ()); | |
5191 | } | |
5192 | ||
5193 | /* e09 : e10 e09' */ | |
5194 | else if (cur_token.code == ':') | |
5195 | { | |
21d6c4af DN |
5196 | /* Mark as a memory operand only if it's not already known to be an |
5197 | offset expression. */ | |
5198 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5199 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5200 | |
5201 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); | |
5202 | } | |
5203 | ||
5204 | /* e09' Empty */ | |
5205 | else | |
5206 | return 1; | |
5207 | } | |
5208 | ||
5209 | /* e10 e11 e10' | |
5210 | ||
5211 | e10' [ expr ] e10' | |
b77a7acd | 5212 | | Empty */ |
64a0c779 DN |
5213 | static int |
5214 | intel_e10 () | |
5215 | { | |
5216 | return (intel_e11 () && intel_e10_1 ()); | |
5217 | } | |
5218 | ||
5219 | static int | |
5220 | intel_e10_1 () | |
5221 | { | |
5222 | /* e10' [ expr ] e10' */ | |
5223 | if (cur_token.code == '[') | |
5224 | { | |
5225 | intel_match_token ('['); | |
21d6c4af DN |
5226 | |
5227 | /* Mark as a memory operand only if it's not already known to be an | |
5228 | offset expression. If it's an offset expression, we need to keep | |
5229 | the brace in. */ | |
5230 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5231 | intel_parser.is_mem = 1; | |
5232 | else | |
5233 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5234 | |
64a0c779 | 5235 | /* Add a '+' to the displacement string if necessary. */ |
21d6c4af DN |
5236 | if (*intel_parser.disp != '\0' |
5237 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5238 | strcat (intel_parser.disp, "+"); |
5239 | ||
21d6c4af DN |
5240 | if (intel_expr () && intel_match_token (']')) |
5241 | { | |
5242 | /* Preserve brackets when the operand is an offset expression. */ | |
5243 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5244 | strcat (intel_parser.disp, "]"); | |
5245 | ||
5246 | return intel_e10_1 (); | |
5247 | } | |
5248 | else | |
5249 | return 0; | |
64a0c779 DN |
5250 | } |
5251 | ||
5252 | /* e10' Empty */ | |
5253 | else | |
5254 | return 1; | |
5255 | } | |
5256 | ||
64a0c779 | 5257 | /* e11 ( expr ) |
b77a7acd | 5258 | | [ expr ] |
64a0c779 DN |
5259 | | BYTE |
5260 | | WORD | |
5261 | | DWORD | |
5262 | | QWORD | |
5263 | | XWORD | |
4a1805b1 | 5264 | | $ |
64a0c779 DN |
5265 | | . |
5266 | | register | |
5267 | | id | |
5268 | | constant */ | |
5269 | static int | |
5270 | intel_e11 () | |
5271 | { | |
5272 | /* e11 ( expr ) */ | |
5273 | if (cur_token.code == '(') | |
5274 | { | |
5275 | intel_match_token ('('); | |
5276 | strcat (intel_parser.disp, "("); | |
5277 | ||
5278 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
5279 | { |
5280 | strcat (intel_parser.disp, ")"); | |
5281 | return 1; | |
5282 | } | |
64a0c779 DN |
5283 | else |
5284 | return 0; | |
5285 | } | |
5286 | ||
5287 | /* e11 [ expr ] */ | |
5288 | else if (cur_token.code == '[') | |
5289 | { | |
5290 | intel_match_token ('['); | |
21d6c4af DN |
5291 | |
5292 | /* Mark as a memory operand only if it's not already known to be an | |
5293 | offset expression. If it's an offset expression, we need to keep | |
5294 | the brace in. */ | |
5295 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5296 | intel_parser.is_mem = 1; | |
5297 | else | |
5298 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5299 | |
64a0c779 DN |
5300 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
5301 | if (current_templates->start->opcode_modifier & Jump | |
5302 | || current_templates->start->opcode_modifier & JumpDword | |
5303 | || current_templates->start->opcode_modifier & JumpByte | |
5304 | || current_templates->start->opcode_modifier & JumpInterSegment) | |
5305 | i.types[this_operand] |= JumpAbsolute; | |
5306 | ||
5307 | /* Add a '+' to the displacement string if necessary. */ | |
21d6c4af DN |
5308 | if (*intel_parser.disp != '\0' |
5309 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5310 | strcat (intel_parser.disp, "+"); |
5311 | ||
21d6c4af DN |
5312 | if (intel_expr () && intel_match_token (']')) |
5313 | { | |
5314 | /* Preserve brackets when the operand is an offset expression. */ | |
5315 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5316 | strcat (intel_parser.disp, "]"); | |
5317 | ||
5318 | return 1; | |
5319 | } | |
5320 | else | |
5321 | return 0; | |
64a0c779 DN |
5322 | } |
5323 | ||
4a1805b1 | 5324 | /* e11 BYTE |
64a0c779 DN |
5325 | | WORD |
5326 | | DWORD | |
5327 | | QWORD | |
5328 | | XWORD */ | |
5329 | else if (cur_token.code == T_BYTE | |
5330 | || cur_token.code == T_WORD | |
5331 | || cur_token.code == T_DWORD | |
5332 | || cur_token.code == T_QWORD | |
5333 | || cur_token.code == T_XWORD) | |
5334 | { | |
5335 | intel_match_token (cur_token.code); | |
5336 | ||
5337 | return 1; | |
5338 | } | |
5339 | ||
5340 | /* e11 $ | |
5341 | | . */ | |
5342 | else if (cur_token.code == '$' || cur_token.code == '.') | |
5343 | { | |
5344 | strcat (intel_parser.disp, cur_token.str); | |
5345 | intel_match_token (cur_token.code); | |
21d6c4af DN |
5346 | |
5347 | /* Mark as a memory operand only if it's not already known to be an | |
5348 | offset expression. */ | |
5349 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5350 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5351 | |
5352 | return 1; | |
5353 | } | |
5354 | ||
5355 | /* e11 register */ | |
5356 | else if (cur_token.code == T_REG) | |
5357 | { | |
5358 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
5359 | ||
5360 | intel_match_token (T_REG); | |
5361 | ||
5362 | /* Check for segment change. */ | |
5363 | if (cur_token.code == ':') | |
5364 | { | |
5365 | if (reg->reg_type & (SReg2 | SReg3)) | |
5366 | { | |
5367 | switch (reg->reg_num) | |
5368 | { | |
5369 | case 0: | |
5370 | i.seg[i.mem_operands] = &es; | |
5371 | break; | |
5372 | case 1: | |
5373 | i.seg[i.mem_operands] = &cs; | |
5374 | break; | |
5375 | case 2: | |
5376 | i.seg[i.mem_operands] = &ss; | |
5377 | break; | |
5378 | case 3: | |
5379 | i.seg[i.mem_operands] = &ds; | |
5380 | break; | |
5381 | case 4: | |
5382 | i.seg[i.mem_operands] = &fs; | |
5383 | break; | |
5384 | case 5: | |
5385 | i.seg[i.mem_operands] = &gs; | |
5386 | break; | |
5387 | } | |
5388 | } | |
5389 | else | |
5390 | { | |
5391 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); | |
5392 | return 0; | |
5393 | } | |
5394 | } | |
5395 | ||
5396 | /* Not a segment register. Check for register scaling. */ | |
5397 | else if (cur_token.code == '*') | |
5398 | { | |
5399 | if (!intel_parser.is_mem) | |
5400 | { | |
5401 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5402 | return 0; | |
5403 | } | |
5404 | ||
4a1805b1 | 5405 | /* What follows must be a valid scale. */ |
64a0c779 DN |
5406 | if (intel_match_token ('*') |
5407 | && strchr ("01248", *cur_token.str)) | |
5408 | { | |
5409 | i.index_reg = reg; | |
5410 | i.types[this_operand] |= BaseIndex; | |
5411 | ||
5412 | /* Set the scale after setting the register (otherwise, | |
5413 | i386_scale will complain) */ | |
5414 | i386_scale (cur_token.str); | |
5415 | intel_match_token (T_CONST); | |
5416 | } | |
5417 | else | |
5418 | { | |
5419 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
5420 | cur_token.str); | |
5421 | return 0; | |
5422 | } | |
5423 | } | |
5424 | ||
5425 | /* No scaling. If this is a memory operand, the register is either a | |
5426 | base register (first occurrence) or an index register (second | |
5427 | occurrence). */ | |
5428 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) | |
5429 | { | |
5430 | if (i.base_reg && i.index_reg) | |
5431 | { | |
5432 | as_bad (_("Too many register references in memory operand.\n")); | |
5433 | return 0; | |
5434 | } | |
5435 | ||
5436 | if (i.base_reg == NULL) | |
5437 | i.base_reg = reg; | |
5438 | else | |
5439 | i.index_reg = reg; | |
5440 | ||
5441 | i.types[this_operand] |= BaseIndex; | |
5442 | } | |
5443 | ||
5444 | /* Offset modifier. Add the register to the displacement string to be | |
5445 | parsed as an immediate expression after we're done. */ | |
5446 | else if (intel_parser.op_modifier == OFFSET_FLAT) | |
5447 | strcat (intel_parser.disp, reg->reg_name); | |
4a1805b1 | 5448 | |
64a0c779 DN |
5449 | /* It's neither base nor index nor offset. */ |
5450 | else | |
5451 | { | |
5452 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
5453 | i.op[this_operand].regs = reg; | |
5454 | i.reg_operands++; | |
5455 | } | |
5456 | ||
5457 | /* Since registers are not part of the displacement string (except | |
5458 | when we're parsing offset operands), we may need to remove any | |
5459 | preceding '+' from the displacement string. */ | |
5460 | if (*intel_parser.disp != '\0' | |
5461 | && intel_parser.op_modifier != OFFSET_FLAT) | |
5462 | { | |
5463 | char *s = intel_parser.disp; | |
5464 | s += strlen (s) - 1; | |
5465 | if (*s == '+') | |
5466 | *s = '\0'; | |
5467 | } | |
5468 | ||
5469 | return 1; | |
5470 | } | |
4a1805b1 | 5471 | |
64a0c779 DN |
5472 | /* e11 id */ |
5473 | else if (cur_token.code == T_ID) | |
5474 | { | |
5475 | /* Add the identifier to the displacement string. */ | |
5476 | strcat (intel_parser.disp, cur_token.str); | |
5477 | intel_match_token (T_ID); | |
5478 | ||
5479 | /* The identifier represents a memory reference only if it's not | |
5480 | preceded by an offset modifier. */ | |
21d6c4af | 5481 | if (intel_parser.op_modifier != OFFSET_FLAT) |
64a0c779 DN |
5482 | intel_parser.is_mem = 1; |
5483 | ||
5484 | return 1; | |
5485 | } | |
5486 | ||
5487 | /* e11 constant */ | |
5488 | else if (cur_token.code == T_CONST | |
e5cb08ac | 5489 | || cur_token.code == '-' |
64a0c779 DN |
5490 | || cur_token.code == '+') |
5491 | { | |
5492 | char *save_str; | |
5493 | ||
5494 | /* Allow constants that start with `+' or `-'. */ | |
5495 | if (cur_token.code == '-' || cur_token.code == '+') | |
5496 | { | |
5497 | strcat (intel_parser.disp, cur_token.str); | |
5498 | intel_match_token (cur_token.code); | |
5499 | if (cur_token.code != T_CONST) | |
5500 | { | |
5501 | as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"), | |
5502 | cur_token.str); | |
5503 | return 0; | |
5504 | } | |
5505 | } | |
5506 | ||
e5cb08ac | 5507 | save_str = (char *) malloc (strlen (cur_token.str) + 1); |
64a0c779 | 5508 | if (save_str == NULL) |
bc805888 | 5509 | abort (); |
64a0c779 DN |
5510 | strcpy (save_str, cur_token.str); |
5511 | ||
5512 | /* Get the next token to check for register scaling. */ | |
5513 | intel_match_token (cur_token.code); | |
5514 | ||
5515 | /* Check if this constant is a scaling factor for an index register. */ | |
5516 | if (cur_token.code == '*') | |
5517 | { | |
5518 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
5519 | { | |
5520 | if (!intel_parser.is_mem) | |
5521 | { | |
5522 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5523 | return 0; | |
5524 | } | |
5525 | ||
4a1805b1 | 5526 | /* The constant is followed by `* reg', so it must be |
64a0c779 DN |
5527 | a valid scale. */ |
5528 | if (strchr ("01248", *save_str)) | |
5529 | { | |
5530 | i.index_reg = cur_token.reg; | |
5531 | i.types[this_operand] |= BaseIndex; | |
5532 | ||
5533 | /* Set the scale after setting the register (otherwise, | |
5534 | i386_scale will complain) */ | |
5535 | i386_scale (save_str); | |
5536 | intel_match_token (T_REG); | |
5537 | ||
5538 | /* Since registers are not part of the displacement | |
5539 | string, we may need to remove any preceding '+' from | |
5540 | the displacement string. */ | |
5541 | if (*intel_parser.disp != '\0') | |
5542 | { | |
5543 | char *s = intel_parser.disp; | |
5544 | s += strlen (s) - 1; | |
5545 | if (*s == '+') | |
5546 | *s = '\0'; | |
5547 | } | |
5548 | ||
5549 | free (save_str); | |
5550 | ||
5551 | return 1; | |
5552 | } | |
5553 | else | |
5554 | return 0; | |
5555 | } | |
5556 | ||
5557 | /* The constant was not used for register scaling. Since we have | |
5558 | already consumed the token following `*' we now need to put it | |
5559 | back in the stream. */ | |
5560 | else | |
5561 | intel_putback_token (); | |
5562 | } | |
5563 | ||
5564 | /* Add the constant to the displacement string. */ | |
5565 | strcat (intel_parser.disp, save_str); | |
5566 | free (save_str); | |
5567 | ||
5568 | return 1; | |
5569 | } | |
5570 | ||
64a0c779 DN |
5571 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
5572 | return 0; | |
5573 | } | |
5574 | ||
64a0c779 DN |
5575 | /* Match the given token against cur_token. If they match, read the next |
5576 | token from the operand string. */ | |
5577 | static int | |
5578 | intel_match_token (code) | |
e5cb08ac | 5579 | int code; |
64a0c779 DN |
5580 | { |
5581 | if (cur_token.code == code) | |
5582 | { | |
5583 | intel_get_token (); | |
5584 | return 1; | |
5585 | } | |
5586 | else | |
5587 | { | |
5588 | as_bad (_("Unexpected token `%s'\n"), cur_token.str); | |
5589 | return 0; | |
5590 | } | |
5591 | } | |
5592 | ||
64a0c779 DN |
5593 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
5594 | static void | |
5595 | intel_get_token () | |
5596 | { | |
5597 | char *end_op; | |
5598 | const reg_entry *reg; | |
5599 | struct intel_token new_token; | |
5600 | ||
5601 | new_token.code = T_NIL; | |
5602 | new_token.reg = NULL; | |
5603 | new_token.str = NULL; | |
5604 | ||
4a1805b1 | 5605 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
5606 | cur_token to prev_token. */ |
5607 | if (prev_token.str) | |
5608 | free (prev_token.str); | |
5609 | ||
5610 | prev_token = cur_token; | |
5611 | ||
5612 | /* Skip whitespace. */ | |
5613 | while (is_space_char (*intel_parser.op_string)) | |
5614 | intel_parser.op_string++; | |
5615 | ||
5616 | /* Return an empty token if we find nothing else on the line. */ | |
5617 | if (*intel_parser.op_string == '\0') | |
5618 | { | |
5619 | cur_token = new_token; | |
5620 | return; | |
5621 | } | |
5622 | ||
5623 | /* The new token cannot be larger than the remainder of the operand | |
5624 | string. */ | |
e5cb08ac | 5625 | new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); |
64a0c779 | 5626 | if (new_token.str == NULL) |
bc805888 | 5627 | abort (); |
64a0c779 DN |
5628 | new_token.str[0] = '\0'; |
5629 | ||
5630 | if (strchr ("0123456789", *intel_parser.op_string)) | |
5631 | { | |
5632 | char *p = new_token.str; | |
5633 | char *q = intel_parser.op_string; | |
5634 | new_token.code = T_CONST; | |
5635 | ||
5636 | /* Allow any kind of identifier char to encompass floating point and | |
5637 | hexadecimal numbers. */ | |
5638 | while (is_identifier_char (*q)) | |
5639 | *p++ = *q++; | |
5640 | *p = '\0'; | |
5641 | ||
5642 | /* Recognize special symbol names [0-9][bf]. */ | |
5643 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 5644 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
5645 | || intel_parser.op_string[1] == 'f')) |
5646 | new_token.code = T_ID; | |
5647 | } | |
5648 | ||
5649 | else if (strchr ("+-/*:[]()", *intel_parser.op_string)) | |
5650 | { | |
5651 | new_token.code = *intel_parser.op_string; | |
5652 | new_token.str[0] = *intel_parser.op_string; | |
5653 | new_token.str[1] = '\0'; | |
5654 | } | |
5655 | ||
5656 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) | |
5657 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) | |
5658 | { | |
5659 | new_token.code = T_REG; | |
5660 | new_token.reg = reg; | |
5661 | ||
5662 | if (*intel_parser.op_string == REGISTER_PREFIX) | |
5663 | { | |
5664 | new_token.str[0] = REGISTER_PREFIX; | |
5665 | new_token.str[1] = '\0'; | |
5666 | } | |
5667 | ||
5668 | strcat (new_token.str, reg->reg_name); | |
5669 | } | |
5670 | ||
5671 | else if (is_identifier_char (*intel_parser.op_string)) | |
5672 | { | |
5673 | char *p = new_token.str; | |
5674 | char *q = intel_parser.op_string; | |
5675 | ||
5676 | /* A '.' or '$' followed by an identifier char is an identifier. | |
5677 | Otherwise, it's operator '.' followed by an expression. */ | |
5678 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
5679 | { | |
5680 | new_token.code = *q; | |
5681 | new_token.str[0] = *q; | |
5682 | new_token.str[1] = '\0'; | |
5683 | } | |
5684 | else | |
5685 | { | |
5686 | while (is_identifier_char (*q) || *q == '@') | |
5687 | *p++ = *q++; | |
5688 | *p = '\0'; | |
5689 | ||
5690 | if (strcasecmp (new_token.str, "BYTE") == 0) | |
5691 | new_token.code = T_BYTE; | |
5692 | ||
5693 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
5694 | new_token.code = T_WORD; | |
5695 | ||
5696 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
5697 | new_token.code = T_DWORD; | |
5698 | ||
5699 | else if (strcasecmp (new_token.str, "QWORD") == 0) | |
5700 | new_token.code = T_QWORD; | |
5701 | ||
5702 | else if (strcasecmp (new_token.str, "XWORD") == 0) | |
5703 | new_token.code = T_XWORD; | |
5704 | ||
5705 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
5706 | new_token.code = T_PTR; | |
5707 | ||
5708 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
5709 | new_token.code = T_SHORT; | |
5710 | ||
5711 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
5712 | { | |
5713 | new_token.code = T_OFFSET; | |
5714 | ||
5715 | /* ??? This is not mentioned in the MASM grammar but gcc | |
5716 | makes use of it with -mintel-syntax. OFFSET may be | |
5717 | followed by FLAT: */ | |
5718 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
5719 | strcat (new_token.str, " FLAT:"); | |
5720 | } | |
5721 | ||
5722 | /* ??? This is not mentioned in the MASM grammar. */ | |
5723 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
5724 | new_token.code = T_OFFSET; | |
5725 | ||
5726 | else | |
5727 | new_token.code = T_ID; | |
5728 | } | |
5729 | } | |
5730 | ||
5731 | else | |
5732 | as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string); | |
5733 | ||
5734 | intel_parser.op_string += strlen (new_token.str); | |
5735 | cur_token = new_token; | |
5736 | } | |
5737 | ||
64a0c779 DN |
5738 | /* Put cur_token back into the token stream and make cur_token point to |
5739 | prev_token. */ | |
5740 | static void | |
5741 | intel_putback_token () | |
5742 | { | |
5743 | intel_parser.op_string -= strlen (cur_token.str); | |
5744 | free (cur_token.str); | |
5745 | cur_token = prev_token; | |
4a1805b1 | 5746 | |
64a0c779 DN |
5747 | /* Forget prev_token. */ |
5748 | prev_token.code = T_NIL; | |
5749 | prev_token.reg = NULL; | |
5750 | prev_token.str = NULL; | |
5751 | } |