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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
e3bb37b5
L		 138static void set_code_flag (int);
139static void set_16bit_gcc_code_flag (int);
140static void set_intel_syntax (int);
1efbbeb4 141static void set_intel_mnemonic (int);
db51cc60 142static void set_allow_index_reg (int);
cb19c032 143static void set_sse_check (int);
e3bb37b5 144static void set_cpu_arch (int);
6482c264 145#ifdef TE_PE
e3bb37b5 146static void pe_directive_secrel (int);
6482c264 147#endif
e3bb37b5
L		 148static void signed_cons (int);
149static char *output_invalid (int c);
ee86248c
JB		 150static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
151 const char *);
152static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
153 const char *);
a7619375 154static int i386_att_operand (char *);
e3bb37b5 155static int i386_intel_operand (char *, int);
ee86248c
JB		 156static int i386_intel_simplify (expressionS *);
157static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 158static const reg_entry *parse_register (char *, char **);
159static char *parse_insn (char *, char *);
160static char *parse_operands (char *, const char *);
161static void swap_operands (void);
4d456e3d 162static void swap_2_operands (int, int);
e3bb37b5
L		 163static void optimize_imm (void);
164static void optimize_disp (void);
d3ce72d0 165static const insn_template *match_template (void);
e3bb37b5
L		 166static int check_string (void);
167static int process_suffix (void);
168static int check_byte_reg (void);
169static int check_long_reg (void);
170static int check_qword_reg (void);
171static int check_word_reg (void);
172static int finalize_imm (void);
173static int process_operands (void);
174static const seg_entry *build_modrm_byte (void);
175static void output_insn (void);
176static void output_imm (fragS *, offsetT);
177static void output_disp (fragS *, offsetT);
29b0f896 178#ifndef I386COFF
e3bb37b5 179static void s_bss (int);
252b5132 180#endif
17d4e2a2
L		 181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182static void handle_large_common (int small ATTRIBUTE_UNUSED);
183#endif
252b5132 184
a847613f 185static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 186
c0f3af97
L		 187/* VEX prefix. */
188typedef struct
189{
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes[3];
192 unsigned int length;
193 /* Destination or source register specifier. */
194 const reg_entry *register_specifier;
195} vex_prefix;
196
252b5132 197/* 'md_assemble ()' gathers together information and puts it into a
47926f60 198 i386_insn. */
252b5132 199
520dc8e8
AM		 200union i386_op
201 {
202 expressionS *disps;
203 expressionS *imms;
204 const reg_entry *regs;
205 };
206
a65babc9
L		 207enum i386_error
208 {
86e026a4 209 operand_size_mismatch,
a65babc9
L		 210 operand_type_mismatch,
211 register_type_mismatch,
212 number_of_operands_mismatch,
213 invalid_instruction_suffix,
214 bad_imm4,
215 old_gcc_only,
216 unsupported_with_intel_mnemonic,
217 unsupported_syntax,
218 unsupported
219 };
220
252b5132
RH		 221struct _i386_insn
222 {
47926f60 223 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 224 insn_template tm;
252b5132 225
7d5e4556
L		 226 /* SUFFIX holds the instruction size suffix for byte, word, dword
227 or qword, if given. */
252b5132
RH		 228 char suffix;
229
47926f60 230 /* OPERANDS gives the number of given operands. */
252b5132
RH		 231 unsigned int operands;
232
233 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
234 of given register, displacement, memory operands and immediate
47926f60 235 operands. */
252b5132
RH		 236 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
237
238 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 239 use OP[i] for the corresponding operand. */
40fb9820 240 i386_operand_type types[MAX_OPERANDS];
252b5132 241
520dc8e8
AM		 242 /* Displacement expression, immediate expression, or register for each
243 operand. */
244 union i386_op op[MAX_OPERANDS];
252b5132 245
3e73aa7c
JH		 246 /* Flags for operands. */
247 unsigned int flags[MAX_OPERANDS];
248#define Operand_PCrel 1
249
252b5132 250 /* Relocation type for operand */
f86103b7 251 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 252
252b5132
RH		 253 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
254 the base index byte below. */
255 const reg_entry *base_reg;
256 const reg_entry *index_reg;
257 unsigned int log2_scale_factor;
258
259 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 260 explicit segment overrides are given. */
ce8a8b2f 261 const seg_entry *seg[2];
252b5132
RH		 262
263 /* PREFIX holds all the given prefix opcodes (usually null).
264 PREFIXES is the number of prefix opcodes. */
265 unsigned int prefixes;
266 unsigned char prefix[MAX_PREFIXES];
267
268 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 269 addressing modes of this insn are encoded. */
252b5132 270 modrm_byte rm;
3e73aa7c 271 rex_byte rex;
252b5132 272 sib_byte sib;
c0f3af97 273 vex_prefix vex;
b6169b20
L		 274
275 /* Swap operand in encoding. */
4473e004 276 unsigned int swap_operand;
891edac4
L		 277
278 /* Error message. */
a65babc9 279 enum i386_error error;
252b5132
RH		 280 };
281
282typedef struct _i386_insn i386_insn;
283
284/* List of chars besides those in app.c:symbol_chars that can start an
285 operand. Used to prevent the scrubber eating vital white-space. */
32137342 286const char extra_symbol_chars[] = "*%-(["
252b5132 287#ifdef LEX_AT
32137342
NC		 288 "@"
289#endif
290#ifdef LEX_QM
291 "?"
252b5132 292#endif
32137342 293 ;
252b5132 294
29b0f896
AM		 295#if (defined (TE_I386AIX) \
296 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 297 && !defined (TE_GNU) \
29b0f896 298 && !defined (TE_LINUX) \
32137342 299 && !defined (TE_NETWARE) \
29b0f896
AM		 300 && !defined (TE_FreeBSD) \
301 && !defined (TE_NetBSD)))
252b5132 302/* This array holds the chars that always start a comment. If the
b3b91714
AM		 303 pre-processor is disabled, these aren't very useful. The option
304 --divide will remove '/' from this list. */
305const char *i386_comment_chars = "#/";
306#define SVR4_COMMENT_CHARS 1
252b5132 307#define PREFIX_SEPARATOR '\\'
252b5132 308
b3b91714
AM		 309#else
310const char *i386_comment_chars = "#";
311#define PREFIX_SEPARATOR '/'
312#endif
313
252b5132
RH		 314/* This array holds the chars that only start a comment at the beginning of
315 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 316 .line and .file directives will appear in the pre-processed output.
317 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 318 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 319 #NO_APP at the beginning of its output.
320 Also note that comments started like this one will always work if
252b5132 321 '/' isn't otherwise defined. */
b3b91714 322const char line_comment_chars[] = "#/";
252b5132 323
63a0b638 324const char line_separator_chars[] = ";";
252b5132 325
ce8a8b2f
AM		 326/* Chars that can be used to separate mant from exp in floating point
327 nums. */
252b5132
RH		 328const char EXP_CHARS[] = "eE";
329
ce8a8b2f
AM		 330/* Chars that mean this number is a floating point constant
331 As in 0f12.456
332 or 0d1.2345e12. */
252b5132
RH		 333const char FLT_CHARS[] = "fFdDxX";
334
ce8a8b2f 335/* Tables for lexical analysis. */
252b5132
RH		 336static char mnemonic_chars[256];
337static char register_chars[256];
338static char operand_chars[256];
339static char identifier_chars[256];
340static char digit_chars[256];
341
ce8a8b2f 342/* Lexical macros. */
252b5132
RH		 343#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
344#define is_operand_char(x) (operand_chars[(unsigned char) x])
345#define is_register_char(x) (register_chars[(unsigned char) x])
346#define is_space_char(x) ((x) == ' ')
347#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
348#define is_digit_char(x) (digit_chars[(unsigned char) x])
349
0234cb7c 350/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 351static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
352
353/* md_assemble() always leaves the strings it's passed unaltered. To
354 effect this we maintain a stack of saved characters that we've smashed
355 with '\0's (indicating end of strings for various sub-fields of the
47926f60 356 assembler instruction). */
252b5132 357static char save_stack[32];
ce8a8b2f 358static char *save_stack_p;
252b5132
RH		 359#define END_STRING_AND_SAVE(s) \
360 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
361#define RESTORE_END_STRING(s) \
362 do { *(s) = *--save_stack_p; } while (0)
363
47926f60 364/* The instruction we're assembling. */
252b5132
RH		 365static i386_insn i;
366
367/* Possible templates for current insn. */
368static const templates *current_templates;
369
31b2323c
L		 370/* Per instruction expressionS buffers: max displacements & immediates. */
371static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
372static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 373
47926f60 374/* Current operand we are working on. */
ee86248c 375static int this_operand = -1;
252b5132 376
3e73aa7c
JH		 377/* We support four different modes. FLAG_CODE variable is used to distinguish
378 these. */
379
380enum flag_code {
381 CODE_32BIT,
382 CODE_16BIT,
383 CODE_64BIT };
384
385static enum flag_code flag_code;
4fa24527 386static unsigned int object_64bit;
3e73aa7c
JH		 387static int use_rela_relocations = 0;
388
389/* The names used to print error messages. */
b77a7acd 390static const char *flag_code_names[] =
3e73aa7c
JH		 391 {
392 "32",
393 "16",
394 "64"
395 };
252b5132 396
47926f60
KH		 397/* 1 for intel syntax,
398 0 if att syntax. */
399static int intel_syntax = 0;
252b5132 400
1efbbeb4
L		 401/* 1 for intel mnemonic,
402 0 if att mnemonic. */
403static int intel_mnemonic = !SYSV386_COMPAT;
404
5209009a 405/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 406static int old_gcc = OLDGCC_COMPAT;
407
a60de03c
JB		 408/* 1 if pseudo registers are permitted. */
409static int allow_pseudo_reg = 0;
410
47926f60
KH		 411/* 1 if register prefix % not required. */
412static int allow_naked_reg = 0;
252b5132 413
ba104c83 414/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 415static int allow_index_reg = 0;
416
daf50ae7
L		 417static enum
418 {
419 sse_check_none = 0,
420 sse_check_warning,
421 sse_check_error
422 }
423sse_check;
424
2ca3ace5
L		 425/* Register prefix used for error message. */
426static const char *register_prefix = "%";
427
47926f60
KH		 428/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431static char stackop_size = '\0';
eecb386c 432
12b55ccc
L		 433/* Non-zero to optimize code alignment. */
434int optimize_align_code = 1;
435
47926f60
KH		 436/* Non-zero to quieten some warnings. */
437static int quiet_warnings = 0;
a38cf1db 438
47926f60
KH		 439/* CPU name. */
440static const char *cpu_arch_name = NULL;
6305a203 441static char *cpu_sub_arch_name = NULL;
a38cf1db 442
47926f60 443/* CPU feature flags. */
40fb9820
L		 444static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
445
ccc9c027
L		 446/* If we have selected a cpu we are generating instructions for. */
447static int cpu_arch_tune_set = 0;
448
9103f4f4 449/* Cpu we are generating instructions for. */
fbf3f584 450enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 451
452/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 453static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 454
ccc9c027 455/* CPU instruction set architecture used. */
fbf3f584 456enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 457
9103f4f4 458/* CPU feature flags of instruction set architecture used. */
fbf3f584 459i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 460
fddf5b5b
AM		 461/* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463static unsigned int no_cond_jump_promotion = 0;
464
c0f3af97
L		 465/* Encode SSE instructions with VEX prefix. */
466static unsigned int sse2avx;
467
539f890d
L		 468/* Encode scalar AVX instructions with specific vector length. */
469static enum
470 {
471 vex128 = 0,
472 vex256
473 } avxscalar;
474
29b0f896 475/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 476static symbolS *GOT_symbol;
29b0f896 477
a4447b93
RH		 478/* The dwarf2 return column, adjusted for 32 or 64 bit. */
479unsigned int x86_dwarf2_return_column;
480
481/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
482int x86_cie_data_alignment;
483
252b5132 484/* Interface to relax_segment.
fddf5b5b
AM		 485 There are 3 major relax states for 386 jump insns because the
486 different types of jumps add different sizes to frags when we're
487 figuring out what sort of jump to choose to reach a given label. */
252b5132 488
47926f60 489/* Types. */
93c2a809
AM		 490#define UNCOND_JUMP 0
491#define COND_JUMP 1
492#define COND_JUMP86 2
fddf5b5b 493
47926f60 494/* Sizes. */
252b5132
RH		 495#define CODE16 1
496#define SMALL 0
29b0f896 497#define SMALL16 (SMALL | CODE16)
252b5132 498#define BIG 2
29b0f896 499#define BIG16 (BIG | CODE16)
252b5132
RH		 500
501#ifndef INLINE
502#ifdef __GNUC__
503#define INLINE __inline__
504#else
505#define INLINE
506#endif
507#endif
508
fddf5b5b
AM		 509#define ENCODE_RELAX_STATE(type, size) \
510 ((relax_substateT) (((type) << 2) | (size)))
511#define TYPE_FROM_RELAX_STATE(s) \
512 ((s) >> 2)
513#define DISP_SIZE_FROM_RELAX_STATE(s) \
514 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 515
516/* This table is used by relax_frag to promote short jumps to long
517 ones where necessary. SMALL (short) jumps may be promoted to BIG
518 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
519 don't allow a short jump in a 32 bit code segment to be promoted to
520 a 16 bit offset jump because it's slower (requires data size
521 prefix), and doesn't work, unless the destination is in the bottom
522 64k of the code segment (The top 16 bits of eip are zeroed). */
523
524const relax_typeS md_relax_table[] =
525{
24eab124
AM		 526 /* The fields are:
527 1) most positive reach of this state,
528 2) most negative reach of this state,
93c2a809 529 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 530 4) which index into the table to try if we can't fit into this one. */
252b5132 531
fddf5b5b 532 /* UNCOND_JUMP states. */
93c2a809
AM		 533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
535 /* dword jmp adds 4 bytes to frag:
536 0 extra opcode bytes, 4 displacement bytes. */
252b5132 537 {0, 0, 4, 0},
93c2a809
AM		 538 /* word jmp adds 2 byte2 to frag:
539 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 540 {0, 0, 2, 0},
541
93c2a809
AM		 542 /* COND_JUMP states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
547 {0, 0, 5, 0},
fddf5b5b 548 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 549 1 extra opcode byte, 2 displacement bytes. */
550 {0, 0, 3, 0},
551
552 /* COND_JUMP86 states. */
553 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
555 /* dword conditionals adds 5 bytes to frag:
556 1 extra opcode byte, 4 displacement bytes. */
557 {0, 0, 5, 0},
558 /* word conditionals add 4 bytes to frag:
559 1 displacement byte and a 3 byte long branch insn. */
560 {0, 0, 4, 0}
252b5132
RH		 561};
562
9103f4f4
L		 563static const arch_entry cpu_arch[] =
564{
8a2c8fef
L		 565 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
566 CPU_GENERIC32_FLAGS, 0 },
567 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
568 CPU_GENERIC64_FLAGS, 0 },
569 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
570 CPU_NONE_FLAGS, 0 },
571 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
572 CPU_I186_FLAGS, 0 },
573 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
574 CPU_I286_FLAGS, 0 },
575 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
576 CPU_I386_FLAGS, 0 },
577 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
578 CPU_I486_FLAGS, 0 },
579 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
580 CPU_I586_FLAGS, 0 },
581 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
582 CPU_I686_FLAGS, 0 },
583 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
584 CPU_I586_FLAGS, 0 },
585 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
586 CPU_I686_FLAGS, 0 },
587 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
588 CPU_P2_FLAGS, 0 },
589 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
590 CPU_P3_FLAGS, 0 },
591 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
592 CPU_P4_FLAGS, 0 },
593 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
594 CPU_CORE_FLAGS, 0 },
595 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
596 CPU_NOCONA_FLAGS, 0 },
597 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
598 CPU_CORE_FLAGS, 1 },
599 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
600 CPU_CORE_FLAGS, 0 },
601 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
602 CPU_CORE2_FLAGS, 1 },
603 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
604 CPU_CORE2_FLAGS, 0 },
605 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
606 CPU_COREI7_FLAGS, 0 },
607 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
608 CPU_L1OM_FLAGS, 0 },
609 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
610 CPU_K6_FLAGS, 0 },
611 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
612 CPU_K6_2_FLAGS, 0 },
613 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
614 CPU_ATHLON_FLAGS, 0 },
615 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
616 CPU_K8_FLAGS, 1 },
617 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
618 CPU_K8_FLAGS, 0 },
619 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
620 CPU_K8_FLAGS, 0 },
621 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
622 CPU_AMDFAM10_FLAGS, 0 },
68339fdf
SP		 623 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
624 CPU_BDVER1_FLAGS, 0 },
8a2c8fef
L		 625 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
626 CPU_8087_FLAGS, 0 },
627 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
628 CPU_287_FLAGS, 0 },
629 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
630 CPU_387_FLAGS, 0 },
631 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
632 CPU_ANY87_FLAGS, 0 },
633 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
634 CPU_MMX_FLAGS, 0 },
635 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
636 CPU_3DNOWA_FLAGS, 0 },
637 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
638 CPU_SSE_FLAGS, 0 },
639 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
640 CPU_SSE2_FLAGS, 0 },
641 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
642 CPU_SSE3_FLAGS, 0 },
643 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
644 CPU_SSSE3_FLAGS, 0 },
645 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
646 CPU_SSE4_1_FLAGS, 0 },
647 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
648 CPU_SSE4_2_FLAGS, 0 },
649 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
650 CPU_SSE4_2_FLAGS, 0 },
651 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
652 CPU_ANY_SSE_FLAGS, 0 },
653 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
654 CPU_AVX_FLAGS, 0 },
655 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
656 CPU_ANY_AVX_FLAGS, 0 },
657 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
658 CPU_VMX_FLAGS, 0 },
659 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
660 CPU_SMX_FLAGS, 0 },
661 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
662 CPU_XSAVE_FLAGS, 0 },
663 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
664 CPU_AES_FLAGS, 0 },
665 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
666 CPU_PCLMUL_FLAGS, 0 },
667 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
668 CPU_PCLMUL_FLAGS, 1 },
669 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
670 CPU_FMA_FLAGS, 0 },
671 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
672 CPU_FMA4_FLAGS, 0 },
673 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
674 CPU_XOP_FLAGS, 0 },
675 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
676 CPU_LWP_FLAGS, 0 },
677 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
678 CPU_MOVBE_FLAGS, 0 },
679 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
680 CPU_EPT_FLAGS, 0 },
681 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
682 CPU_CLFLUSH_FLAGS, 0 },
683 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
684 CPU_SYSCALL_FLAGS, 0 },
685 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
686 CPU_RDTSCP_FLAGS, 0 },
687 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
688 CPU_3DNOW_FLAGS, 0 },
689 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
690 CPU_3DNOWA_FLAGS, 0 },
691 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
692 CPU_PADLOCK_FLAGS, 0 },
693 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
694 CPU_SVME_FLAGS, 1 },
695 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
696 CPU_SVME_FLAGS, 0 },
697 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
698 CPU_SSE4A_FLAGS, 0 },
699 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
700 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 701};
702
704209c0 703#ifdef I386COFF
a6c24e68
NC		 704/* Like s_lcomm_internal in gas/read.c but the alignment string
705 is allowed to be optional. */
706
707static symbolS *
708pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
709{
710 addressT align = 0;
711
712 SKIP_WHITESPACE ();
713
7ab9ffdd 714 if (needs_align
a6c24e68
NC		 715 && *input_line_pointer == ',')
716 {
717 align = parse_align (needs_align - 1);
7ab9ffdd 718
a6c24e68
NC		 719 if (align == (addressT) -1)
720 return NULL;
721 }
722 else
723 {
724 if (size >= 8)
725 align = 3;
726 else if (size >= 4)
727 align = 2;
728 else if (size >= 2)
729 align = 1;
730 else
731 align = 0;
732 }
733
734 bss_alloc (symbolP, size, align);
735 return symbolP;
736}
737
704209c0 738static void
a6c24e68
NC		 739pe_lcomm (int needs_align)
740{
741 s_comm_internal (needs_align * 2, pe_lcomm_internal);
742}
704209c0 743#endif
a6c24e68 744
29b0f896
AM		 745const pseudo_typeS md_pseudo_table[] =
746{
747#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
748 {"align", s_align_bytes, 0},
749#else
750 {"align", s_align_ptwo, 0},
751#endif
752 {"arch", set_cpu_arch, 0},
753#ifndef I386COFF
754 {"bss", s_bss, 0},
a6c24e68
NC		 755#else
756 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 757#endif
758 {"ffloat", float_cons, 'f'},
759 {"dfloat", float_cons, 'd'},
760 {"tfloat", float_cons, 'x'},
761 {"value", cons, 2},
d182319b 762 {"slong", signed_cons, 4},
29b0f896
AM		 763 {"noopt", s_ignore, 0},
764 {"optim", s_ignore, 0},
765 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
766 {"code16", set_code_flag, CODE_16BIT},
767 {"code32", set_code_flag, CODE_32BIT},
768 {"code64", set_code_flag, CODE_64BIT},
769 {"intel_syntax", set_intel_syntax, 1},
770 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 771 {"intel_mnemonic", set_intel_mnemonic, 1},
772 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 773 {"allow_index_reg", set_allow_index_reg, 1},
774 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 775 {"sse_check", set_sse_check, 0},
3b22753a
L		 776#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
777 {"largecomm", handle_large_common, 0},
07a53e5c 778#else
e3bb37b5 779 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 780 {"loc", dwarf2_directive_loc, 0},
781 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 782#endif
6482c264
NC		 783#ifdef TE_PE
784 {"secrel32", pe_directive_secrel, 0},
785#endif
29b0f896
AM		 786 {0, 0, 0}
787};
788
789/* For interface with expression (). */
790extern char *input_line_pointer;
791
792/* Hash table for instruction mnemonic lookup. */
793static struct hash_control *op_hash;
794
795/* Hash table for register lookup. */
796static struct hash_control *reg_hash;
797\f
252b5132 798void
e3bb37b5 799i386_align_code (fragS *fragP, int count)
252b5132 800{
ce8a8b2f
AM		 801 /* Various efficient no-op patterns for aligning code labels.
802 Note: Don't try to assemble the instructions in the comments.
803 0L and 0w are not legal. */
252b5132
RH		 804 static const char f32_1[] =
805 {0x90}; /* nop */
806 static const char f32_2[] =
ccc9c027 807 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 808 static const char f32_3[] =
809 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
810 static const char f32_4[] =
811 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
812 static const char f32_5[] =
813 {0x90, /* nop */
814 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
815 static const char f32_6[] =
816 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
817 static const char f32_7[] =
818 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
819 static const char f32_8[] =
820 {0x90, /* nop */
821 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
822 static const char f32_9[] =
823 {0x89,0xf6, /* movl %esi,%esi */
824 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
825 static const char f32_10[] =
826 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
827 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
828 static const char f32_11[] =
829 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
830 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
831 static const char f32_12[] =
832 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
833 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
834 static const char f32_13[] =
835 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
836 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
837 static const char f32_14[] =
838 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
839 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 840 static const char f16_3[] =
841 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 842 static const char f16_4[] =
843 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
844 static const char f16_5[] =
845 {0x90, /* nop */
846 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
847 static const char f16_6[] =
848 {0x89,0xf6, /* mov %si,%si */
849 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
850 static const char f16_7[] =
851 {0x8d,0x74,0x00, /* lea 0(%si),%si */
852 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
853 static const char f16_8[] =
854 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
855 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 856 static const char jump_31[] =
857 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
858 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
859 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
860 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 861 static const char *const f32_patt[] = {
862 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 863 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 864 };
865 static const char *const f16_patt[] = {
76bc74dc 866 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 867 };
ccc9c027
L		 868 /* nopl (%[re]ax) */
869 static const char alt_3[] =
870 {0x0f,0x1f,0x00};
871 /* nopl 0(%[re]ax) */
872 static const char alt_4[] =
873 {0x0f,0x1f,0x40,0x00};
874 /* nopl 0(%[re]ax,%[re]ax,1) */
875 static const char alt_5[] =
876 {0x0f,0x1f,0x44,0x00,0x00};
877 /* nopw 0(%[re]ax,%[re]ax,1) */
878 static const char alt_6[] =
879 {0x66,0x0f,0x1f,0x44,0x00,0x00};
880 /* nopl 0L(%[re]ax) */
881 static const char alt_7[] =
882 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
883 /* nopl 0L(%[re]ax,%[re]ax,1) */
884 static const char alt_8[] =
885 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
886 /* nopw 0L(%[re]ax,%[re]ax,1) */
887 static const char alt_9[] =
888 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
890 static const char alt_10[] =
891 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
892 /* data16
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_11[] =
895 {0x66,
896 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
897 /* data16
898 data16
899 nopw %cs:0L(%[re]ax,%[re]ax,1) */
900 static const char alt_long_12[] =
901 {0x66,
902 0x66,
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* data16
905 data16
906 data16
907 nopw %cs:0L(%[re]ax,%[re]ax,1) */
908 static const char alt_long_13[] =
909 {0x66,
910 0x66,
911 0x66,
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* data16
914 data16
915 data16
916 data16
917 nopw %cs:0L(%[re]ax,%[re]ax,1) */
918 static const char alt_long_14[] =
919 {0x66,
920 0x66,
921 0x66,
922 0x66,
923 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
924 /* data16
925 data16
926 data16
927 data16
928 data16
929 nopw %cs:0L(%[re]ax,%[re]ax,1) */
930 static const char alt_long_15[] =
931 {0x66,
932 0x66,
933 0x66,
934 0x66,
935 0x66,
936 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
937 /* nopl 0(%[re]ax,%[re]ax,1)
938 nopw 0(%[re]ax,%[re]ax,1) */
939 static const char alt_short_11[] =
940 {0x0f,0x1f,0x44,0x00,0x00,
941 0x66,0x0f,0x1f,0x44,0x00,0x00};
942 /* nopw 0(%[re]ax,%[re]ax,1)
943 nopw 0(%[re]ax,%[re]ax,1) */
944 static const char alt_short_12[] =
945 {0x66,0x0f,0x1f,0x44,0x00,0x00,
946 0x66,0x0f,0x1f,0x44,0x00,0x00};
947 /* nopw 0(%[re]ax,%[re]ax,1)
948 nopl 0L(%[re]ax) */
949 static const char alt_short_13[] =
950 {0x66,0x0f,0x1f,0x44,0x00,0x00,
951 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
952 /* nopl 0L(%[re]ax)
953 nopl 0L(%[re]ax) */
954 static const char alt_short_14[] =
955 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
956 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
957 /* nopl 0L(%[re]ax)
958 nopl 0L(%[re]ax,%[re]ax,1) */
959 static const char alt_short_15[] =
960 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
961 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
962 static const char *const alt_short_patt[] = {
963 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
964 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
965 alt_short_14, alt_short_15
966 };
967 static const char *const alt_long_patt[] = {
968 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
969 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
970 alt_long_14, alt_long_15
971 };
252b5132 972
76bc74dc
L		 973 /* Only align for at least a positive non-zero boundary. */
974 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 975 return;
3e73aa7c 976
ccc9c027
L		 977 /* We need to decide which NOP sequence to use for 32bit and
978 64bit. When -mtune= is used:
4eed87de 979
76bc74dc
L		 980 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
981 PROCESSOR_GENERIC32, f32_patt will be used.
982 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 983 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
984 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 985 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 986 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 987 will be used.
ccc9c027 988
76bc74dc
L		 989 When -mtune= isn't used, alt_long_patt will be used if
990 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
991 be used.
ccc9c027
L		 992
993 When -march= or .arch is used, we can't use anything beyond
994 cpu_arch_isa_flags. */
995
996 if (flag_code == CODE_16BIT)
997 {
ccc9c027 998 if (count > 8)
33fef721 999 {
76bc74dc
L		 1000 memcpy (fragP->fr_literal + fragP->fr_fix,
1001 jump_31, count);
1002 /* Adjust jump offset. */
1003 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1004 }
76bc74dc
L		 1005 else
1006 memcpy (fragP->fr_literal + fragP->fr_fix,
1007 f16_patt[count - 1], count);
252b5132 1008 }
33fef721 1009 else
ccc9c027
L		 1010 {
1011 const char *const *patt = NULL;
1012
fbf3f584 1013 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1014 {
1015 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1016 switch (cpu_arch_tune)
1017 {
1018 case PROCESSOR_UNKNOWN:
1019 /* We use cpu_arch_isa_flags to check if we SHOULD
1020 optimize for Cpu686. */
fbf3f584 1021 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 1022 patt = alt_long_patt;
ccc9c027
L		 1023 else
1024 patt = f32_patt;
1025 break;
ccc9c027
L		 1026 case PROCESSOR_PENTIUMPRO:
1027 case PROCESSOR_PENTIUM4:
1028 case PROCESSOR_NOCONA:
ef05d495 1029 case PROCESSOR_CORE:
76bc74dc 1030 case PROCESSOR_CORE2:
bd5295b2 1031 case PROCESSOR_COREI7:
3632d14b 1032 case PROCESSOR_L1OM:
76bc74dc
L		 1033 case PROCESSOR_GENERIC64:
1034 patt = alt_long_patt;
1035 break;
ccc9c027
L		 1036 case PROCESSOR_K6:
1037 case PROCESSOR_ATHLON:
1038 case PROCESSOR_K8:
4eed87de 1039 case PROCESSOR_AMDFAM10:
68339fdf 1040 case PROCESSOR_BDVER1:
ccc9c027
L		 1041 patt = alt_short_patt;
1042 break;
76bc74dc 1043 case PROCESSOR_I386:
ccc9c027
L		 1044 case PROCESSOR_I486:
1045 case PROCESSOR_PENTIUM:
1046 case PROCESSOR_GENERIC32:
1047 patt = f32_patt;
1048 break;
4eed87de 1049 }
ccc9c027
L		 1050 }
1051 else
1052 {
fbf3f584 1053 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1054 {
1055 case PROCESSOR_UNKNOWN:
e6a14101 1056 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1057 PROCESSOR_UNKNOWN. */
1058 abort ();
1059 break;
1060
76bc74dc 1061 case PROCESSOR_I386:
ccc9c027
L		 1062 case PROCESSOR_I486:
1063 case PROCESSOR_PENTIUM:
ccc9c027
L		 1064 case PROCESSOR_K6:
1065 case PROCESSOR_ATHLON:
1066 case PROCESSOR_K8:
4eed87de 1067 case PROCESSOR_AMDFAM10:
68339fdf 1068 case PROCESSOR_BDVER1:
ccc9c027
L		 1069 case PROCESSOR_GENERIC32:
1070 /* We use cpu_arch_isa_flags to check if we CAN optimize
1071 for Cpu686. */
fbf3f584 1072 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1073 patt = alt_short_patt;
1074 else
1075 patt = f32_patt;
1076 break;
76bc74dc
L		 1077 case PROCESSOR_PENTIUMPRO:
1078 case PROCESSOR_PENTIUM4:
1079 case PROCESSOR_NOCONA:
1080 case PROCESSOR_CORE:
ef05d495 1081 case PROCESSOR_CORE2:
bd5295b2 1082 case PROCESSOR_COREI7:
3632d14b 1083 case PROCESSOR_L1OM:
fbf3f584 1084 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1085 patt = alt_long_patt;
1086 else
1087 patt = f32_patt;
1088 break;
1089 case PROCESSOR_GENERIC64:
76bc74dc 1090 patt = alt_long_patt;
ccc9c027 1091 break;
4eed87de 1092 }
ccc9c027
L		 1093 }
1094
76bc74dc
L		 1095 if (patt == f32_patt)
1096 {
1097 /* If the padding is less than 15 bytes, we use the normal
1098 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1099 its offset. */
1100 int limit;
76ba9986 1101
711eedef
L		 1102 /* For 64bit, the limit is 3 bytes. */
1103 if (flag_code == CODE_64BIT
1104 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1105 limit = 3;
1106 else
1107 limit = 15;
1108 if (count < limit)
76bc74dc
L		 1109 memcpy (fragP->fr_literal + fragP->fr_fix,
1110 patt[count - 1], count);
1111 else
1112 {
1113 memcpy (fragP->fr_literal + fragP->fr_fix,
1114 jump_31, count);
1115 /* Adjust jump offset. */
1116 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1117 }
1118 }
1119 else
1120 {
1121 /* Maximum length of an instruction is 15 byte. If the
1122 padding is greater than 15 bytes and we don't use jump,
1123 we have to break it into smaller pieces. */
1124 int padding = count;
1125 while (padding > 15)
1126 {
1127 padding -= 15;
1128 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1129 patt [14], 15);
1130 }
1131
1132 if (padding)
1133 memcpy (fragP->fr_literal + fragP->fr_fix,
1134 patt [padding - 1], padding);
1135 }
ccc9c027 1136 }
33fef721 1137 fragP->fr_var = count;
252b5132
RH		 1138}
1139
c6fb90c8 1140static INLINE int
0dfbf9d7 1141operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1142{
0dfbf9d7 1143 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1144 {
1145 case 3:
0dfbf9d7 1146 if (x->array[2])
c6fb90c8
L		 1147 return 0;
1148 case 2:
0dfbf9d7 1149 if (x->array[1])
c6fb90c8
L		 1150 return 0;
1151 case 1:
0dfbf9d7 1152 return !x->array[0];
c6fb90c8
L		 1153 default:
1154 abort ();
1155 }
40fb9820
L		 1156}
1157
c6fb90c8 1158static INLINE void
0dfbf9d7 1159operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1160{
0dfbf9d7 1161 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1162 {
1163 case 3:
0dfbf9d7 1164 x->array[2] = v;
c6fb90c8 1165 case 2:
0dfbf9d7 1166 x->array[1] = v;
c6fb90c8 1167 case 1:
0dfbf9d7 1168 x->array[0] = v;
c6fb90c8
L		 1169 break;
1170 default:
1171 abort ();
1172 }
1173}
40fb9820 1174
c6fb90c8 1175static INLINE int
0dfbf9d7
L		 1176operand_type_equal (const union i386_operand_type *x,
1177 const union i386_operand_type *y)
c6fb90c8 1178{
0dfbf9d7 1179 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1180 {
1181 case 3:
0dfbf9d7 1182 if (x->array[2] != y->array[2])
c6fb90c8
L		 1183 return 0;
1184 case 2:
0dfbf9d7 1185 if (x->array[1] != y->array[1])
c6fb90c8
L		 1186 return 0;
1187 case 1:
0dfbf9d7 1188 return x->array[0] == y->array[0];
c6fb90c8
L		 1189 break;
1190 default:
1191 abort ();
1192 }
1193}
40fb9820 1194
0dfbf9d7
L		 1195static INLINE int
1196cpu_flags_all_zero (const union i386_cpu_flags *x)
1197{
1198 switch (ARRAY_SIZE(x->array))
1199 {
1200 case 3:
1201 if (x->array[2])
1202 return 0;
1203 case 2:
1204 if (x->array[1])
1205 return 0;
1206 case 1:
1207 return !x->array[0];
1208 default:
1209 abort ();
1210 }
1211}
1212
1213static INLINE void
1214cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1215{
1216 switch (ARRAY_SIZE(x->array))
1217 {
1218 case 3:
1219 x->array[2] = v;
1220 case 2:
1221 x->array[1] = v;
1222 case 1:
1223 x->array[0] = v;
1224 break;
1225 default:
1226 abort ();
1227 }
1228}
1229
1230static INLINE int
1231cpu_flags_equal (const union i386_cpu_flags *x,
1232 const union i386_cpu_flags *y)
1233{
1234 switch (ARRAY_SIZE(x->array))
1235 {
1236 case 3:
1237 if (x->array[2] != y->array[2])
1238 return 0;
1239 case 2:
1240 if (x->array[1] != y->array[1])
1241 return 0;
1242 case 1:
1243 return x->array[0] == y->array[0];
1244 break;
1245 default:
1246 abort ();
1247 }
1248}
c6fb90c8
L		 1249
1250static INLINE int
1251cpu_flags_check_cpu64 (i386_cpu_flags f)
1252{
1253 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1254 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1255}
1256
c6fb90c8
L		 1257static INLINE i386_cpu_flags
1258cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1259{
c6fb90c8
L		 1260 switch (ARRAY_SIZE (x.array))
1261 {
1262 case 3:
1263 x.array [2] &= y.array [2];
1264 case 2:
1265 x.array [1] &= y.array [1];
1266 case 1:
1267 x.array [0] &= y.array [0];
1268 break;
1269 default:
1270 abort ();
1271 }
1272 return x;
1273}
40fb9820 1274
c6fb90c8
L		 1275static INLINE i386_cpu_flags
1276cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1277{
c6fb90c8 1278 switch (ARRAY_SIZE (x.array))
40fb9820 1279 {
c6fb90c8
L		 1280 case 3:
1281 x.array [2] |= y.array [2];
1282 case 2:
1283 x.array [1] |= y.array [1];
1284 case 1:
1285 x.array [0] |= y.array [0];
40fb9820
L		 1286 break;
1287 default:
1288 abort ();
1289 }
40fb9820
L		 1290 return x;
1291}
1292
309d3373
JB		 1293static INLINE i386_cpu_flags
1294cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1295{
1296 switch (ARRAY_SIZE (x.array))
1297 {
1298 case 3:
1299 x.array [2] &= ~y.array [2];
1300 case 2:
1301 x.array [1] &= ~y.array [1];
1302 case 1:
1303 x.array [0] &= ~y.array [0];
1304 break;
1305 default:
1306 abort ();
1307 }
1308 return x;
1309}
1310
c0f3af97
L		 1311#define CPU_FLAGS_ARCH_MATCH 0x1
1312#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1313#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1314#define CPU_FLAGS_PCLMUL_MATCH 0x8
1315#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1316
a5ff0eb2 1317#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1318 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1319 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1320#define CPU_FLAGS_PERFECT_MATCH \
1321 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1322
1323/* Return CPU flags match bits. */
3629bb00 1324
40fb9820 1325static int
d3ce72d0 1326cpu_flags_match (const insn_template *t)
40fb9820 1327{
c0f3af97
L		 1328 i386_cpu_flags x = t->cpu_flags;
1329 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1330
1331 x.bitfield.cpu64 = 0;
1332 x.bitfield.cpuno64 = 0;
1333
0dfbf9d7 1334 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1335 {
1336 /* This instruction is available on all archs. */
1337 match |= CPU_FLAGS_32BIT_MATCH;
1338 }
3629bb00
L		 1339 else
1340 {
c0f3af97 1341 /* This instruction is available only on some archs. */
3629bb00
L		 1342 i386_cpu_flags cpu = cpu_arch_flags;
1343
1344 cpu.bitfield.cpu64 = 0;
1345 cpu.bitfield.cpuno64 = 0;
1346 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1347 if (!cpu_flags_all_zero (&cpu))
1348 {
a5ff0eb2
L		 1349 if (x.bitfield.cpuavx)
1350 {
ce2f5b3c 1351 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1352 if (cpu.bitfield.cpuavx)
1353 {
1354 /* Check SSE2AVX. */
1355 if (!t->opcode_modifier.sse2avx|| sse2avx)
1356 {
1357 match |= (CPU_FLAGS_ARCH_MATCH
1358 | CPU_FLAGS_AVX_MATCH);
1359 /* Check AES. */
1360 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1361 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1362 /* Check PCLMUL. */
1363 if (!x.bitfield.cpupclmul
1364 || cpu.bitfield.cpupclmul)
1365 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1366 }
1367 }
1368 else
1369 match |= CPU_FLAGS_ARCH_MATCH;
1370 }
1371 else
c0f3af97
L		 1372 match |= CPU_FLAGS_32BIT_MATCH;
1373 }
3629bb00 1374 }
c0f3af97 1375 return match;
40fb9820
L		 1376}
1377
c6fb90c8
L		 1378static INLINE i386_operand_type
1379operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1380{
c6fb90c8
L		 1381 switch (ARRAY_SIZE (x.array))
1382 {
1383 case 3:
1384 x.array [2] &= y.array [2];
1385 case 2:
1386 x.array [1] &= y.array [1];
1387 case 1:
1388 x.array [0] &= y.array [0];
1389 break;
1390 default:
1391 abort ();
1392 }
1393 return x;
40fb9820
L		 1394}
1395
c6fb90c8
L		 1396static INLINE i386_operand_type
1397operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1398{
c6fb90c8 1399 switch (ARRAY_SIZE (x.array))
40fb9820 1400 {
c6fb90c8
L		 1401 case 3:
1402 x.array [2] |= y.array [2];
1403 case 2:
1404 x.array [1] |= y.array [1];
1405 case 1:
1406 x.array [0] |= y.array [0];
40fb9820
L		 1407 break;
1408 default:
1409 abort ();
1410 }
c6fb90c8
L		 1411 return x;
1412}
40fb9820 1413
c6fb90c8
L		 1414static INLINE i386_operand_type
1415operand_type_xor (i386_operand_type x, i386_operand_type y)
1416{
1417 switch (ARRAY_SIZE (x.array))
1418 {
1419 case 3:
1420 x.array [2] ^= y.array [2];
1421 case 2:
1422 x.array [1] ^= y.array [1];
1423 case 1:
1424 x.array [0] ^= y.array [0];
1425 break;
1426 default:
1427 abort ();
1428 }
40fb9820
L		 1429 return x;
1430}
1431
1432static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1433static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1434static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1435static const i386_operand_type inoutportreg
1436 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1437static const i386_operand_type reg16_inoutportreg
1438 = OPERAND_TYPE_REG16_INOUTPORTREG;
1439static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1440static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1441static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1442static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1443static const i386_operand_type anydisp
1444 = OPERAND_TYPE_ANYDISP;
40fb9820 1445static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1446static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1447static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1448static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1449static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1450static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1451static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1452static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1453static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1454static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1455static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1456static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1457
1458enum operand_type
1459{
1460 reg,
40fb9820
L		 1461 imm,
1462 disp,
1463 anymem
1464};
1465
c6fb90c8 1466static INLINE int
40fb9820
L		 1467operand_type_check (i386_operand_type t, enum operand_type c)
1468{
1469 switch (c)
1470 {
1471 case reg:
1472 return (t.bitfield.reg8
1473 || t.bitfield.reg16
1474 || t.bitfield.reg32
1475 || t.bitfield.reg64);
1476
40fb9820
L		 1477 case imm:
1478 return (t.bitfield.imm8
1479 || t.bitfield.imm8s
1480 || t.bitfield.imm16
1481 || t.bitfield.imm32
1482 || t.bitfield.imm32s
1483 || t.bitfield.imm64);
1484
1485 case disp:
1486 return (t.bitfield.disp8
1487 || t.bitfield.disp16
1488 || t.bitfield.disp32
1489 || t.bitfield.disp32s
1490 || t.bitfield.disp64);
1491
1492 case anymem:
1493 return (t.bitfield.disp8
1494 || t.bitfield.disp16
1495 || t.bitfield.disp32
1496 || t.bitfield.disp32s
1497 || t.bitfield.disp64
1498 || t.bitfield.baseindex);
1499
1500 default:
1501 abort ();
1502 }
2cfe26b6
AM		 1503
1504 return 0;
40fb9820
L		 1505}
1506
5c07affc
L		 1507/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1508 operand J for instruction template T. */
1509
1510static INLINE int
d3ce72d0 1511match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1512{
1513 return !((i.types[j].bitfield.byte
1514 && !t->operand_types[j].bitfield.byte)
1515 || (i.types[j].bitfield.word
1516 && !t->operand_types[j].bitfield.word)
1517 || (i.types[j].bitfield.dword
1518 && !t->operand_types[j].bitfield.dword)
1519 || (i.types[j].bitfield.qword
1520 && !t->operand_types[j].bitfield.qword));
1521}
1522
1523/* Return 1 if there is no conflict in any size on operand J for
1524 instruction template T. */
1525
1526static INLINE int
d3ce72d0 1527match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1528{
1529 return (match_reg_size (t, j)
1530 && !((i.types[j].bitfield.unspecified
1531 && !t->operand_types[j].bitfield.unspecified)
1532 || (i.types[j].bitfield.fword
1533 && !t->operand_types[j].bitfield.fword)
1534 || (i.types[j].bitfield.tbyte
1535 && !t->operand_types[j].bitfield.tbyte)
1536 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1537 && !t->operand_types[j].bitfield.xmmword)
1538 || (i.types[j].bitfield.ymmword
1539 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1540}
1541
1542/* Return 1 if there is no size conflict on any operands for
1543 instruction template T. */
1544
1545static INLINE int
d3ce72d0 1546operand_size_match (const insn_template *t)
5c07affc
L		 1547{
1548 unsigned int j;
1549 int match = 1;
1550
1551 /* Don't check jump instructions. */
1552 if (t->opcode_modifier.jump
1553 || t->opcode_modifier.jumpbyte
1554 || t->opcode_modifier.jumpdword
1555 || t->opcode_modifier.jumpintersegment)
1556 return match;
1557
1558 /* Check memory and accumulator operand size. */
1559 for (j = 0; j < i.operands; j++)
1560 {
1561 if (t->operand_types[j].bitfield.anysize)
1562 continue;
1563
1564 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1565 {
1566 match = 0;
1567 break;
1568 }
1569
1570 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1571 {
1572 match = 0;
1573 break;
1574 }
1575 }
1576
891edac4 1577 if (match)
5c07affc 1578 return match;
891edac4
L		 1579 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1580 {
1581mismatch:
86e026a4 1582 i.error = operand_size_mismatch;
891edac4
L		 1583 return 0;
1584 }
5c07affc
L		 1585
1586 /* Check reverse. */
9c2799c2 1587 gas_assert (i.operands == 2);
5c07affc
L		 1588
1589 match = 1;
1590 for (j = 0; j < 2; j++)
1591 {
1592 if (t->operand_types[j].bitfield.acc
1593 && !match_reg_size (t, j ? 0 : 1))
891edac4 1594 goto mismatch;
5c07affc
L		 1595
1596 if (i.types[j].bitfield.mem
1597 && !match_mem_size (t, j ? 0 : 1))
891edac4 1598 goto mismatch;
5c07affc
L		 1599 }
1600
1601 return match;
1602}
1603
c6fb90c8 1604static INLINE int
40fb9820
L		 1605operand_type_match (i386_operand_type overlap,
1606 i386_operand_type given)
1607{
1608 i386_operand_type temp = overlap;
1609
1610 temp.bitfield.jumpabsolute = 0;
7d5e4556 1611 temp.bitfield.unspecified = 0;
5c07affc
L		 1612 temp.bitfield.byte = 0;
1613 temp.bitfield.word = 0;
1614 temp.bitfield.dword = 0;
1615 temp.bitfield.fword = 0;
1616 temp.bitfield.qword = 0;
1617 temp.bitfield.tbyte = 0;
1618 temp.bitfield.xmmword = 0;
c0f3af97 1619 temp.bitfield.ymmword = 0;
0dfbf9d7 1620 if (operand_type_all_zero (&temp))
891edac4 1621 goto mismatch;
40fb9820 1622
891edac4
L		 1623 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1624 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1625 return 1;
1626
1627mismatch:
a65babc9 1628 i.error = operand_type_mismatch;
891edac4 1629 return 0;
40fb9820
L		 1630}
1631
7d5e4556 1632/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1633 unless the expected operand type register overlap is null.
1634 Note that Acc in a template matches every size of reg. */
1635
c6fb90c8 1636static INLINE int
40fb9820
L		 1637operand_type_register_match (i386_operand_type m0,
1638 i386_operand_type g0,
1639 i386_operand_type t0,
1640 i386_operand_type m1,
1641 i386_operand_type g1,
1642 i386_operand_type t1)
1643{
1644 if (!operand_type_check (g0, reg))
1645 return 1;
1646
1647 if (!operand_type_check (g1, reg))
1648 return 1;
1649
1650 if (g0.bitfield.reg8 == g1.bitfield.reg8
1651 && g0.bitfield.reg16 == g1.bitfield.reg16
1652 && g0.bitfield.reg32 == g1.bitfield.reg32
1653 && g0.bitfield.reg64 == g1.bitfield.reg64)
1654 return 1;
1655
1656 if (m0.bitfield.acc)
1657 {
1658 t0.bitfield.reg8 = 1;
1659 t0.bitfield.reg16 = 1;
1660 t0.bitfield.reg32 = 1;
1661 t0.bitfield.reg64 = 1;
1662 }
1663
1664 if (m1.bitfield.acc)
1665 {
1666 t1.bitfield.reg8 = 1;
1667 t1.bitfield.reg16 = 1;
1668 t1.bitfield.reg32 = 1;
1669 t1.bitfield.reg64 = 1;
1670 }
1671
891edac4
L		 1672 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1673 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1674 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1675 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1676 return 1;
1677
a65babc9 1678 i.error = register_type_mismatch;
891edac4
L		 1679
1680 return 0;
40fb9820
L		 1681}
1682
252b5132 1683static INLINE unsigned int
40fb9820 1684mode_from_disp_size (i386_operand_type t)
252b5132 1685{
40fb9820
L		 1686 if (t.bitfield.disp8)
1687 return 1;
1688 else if (t.bitfield.disp16
1689 || t.bitfield.disp32
1690 || t.bitfield.disp32s)
1691 return 2;
1692 else
1693 return 0;
252b5132
RH		 1694}
1695
1696static INLINE int
e3bb37b5 1697fits_in_signed_byte (offsetT num)
252b5132
RH		 1698{
1699 return (num >= -128) && (num <= 127);
47926f60 1700}
252b5132
RH		 1701
1702static INLINE int
e3bb37b5 1703fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1704{
1705 return (num & 0xff) == num;
47926f60 1706}
252b5132
RH		 1707
1708static INLINE int
e3bb37b5 1709fits_in_unsigned_word (offsetT num)
252b5132
RH		 1710{
1711 return (num & 0xffff) == num;
47926f60 1712}
252b5132
RH		 1713
1714static INLINE int
e3bb37b5 1715fits_in_signed_word (offsetT num)
252b5132
RH		 1716{
1717 return (-32768 <= num) && (num <= 32767);
47926f60 1718}
2a962e6d 1719
3e73aa7c 1720static INLINE int
e3bb37b5 1721fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1722{
1723#ifndef BFD64
1724 return 1;
1725#else
1726 return (!(((offsetT) -1 << 31) & num)
1727 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1728#endif
1729} /* fits_in_signed_long() */
2a962e6d 1730
3e73aa7c 1731static INLINE int
e3bb37b5 1732fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1733{
1734#ifndef BFD64
1735 return 1;
1736#else
1737 return (num & (((offsetT) 2 << 31) - 1)) == num;
1738#endif
1739} /* fits_in_unsigned_long() */
252b5132 1740
a683cc34
SP		 1741static INLINE int
1742fits_in_imm4 (offsetT num)
1743{
1744 return (num & 0xf) == num;
1745}
1746
40fb9820 1747static i386_operand_type
e3bb37b5 1748smallest_imm_type (offsetT num)
252b5132 1749{
40fb9820 1750 i386_operand_type t;
7ab9ffdd 1751
0dfbf9d7 1752 operand_type_set (&t, 0);
40fb9820
L		 1753 t.bitfield.imm64 = 1;
1754
1755 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1756 {
1757 /* This code is disabled on the 486 because all the Imm1 forms
1758 in the opcode table are slower on the i486. They're the
1759 versions with the implicitly specified single-position
1760 displacement, which has another syntax if you really want to
1761 use that form. */
40fb9820
L		 1762 t.bitfield.imm1 = 1;
1763 t.bitfield.imm8 = 1;
1764 t.bitfield.imm8s = 1;
1765 t.bitfield.imm16 = 1;
1766 t.bitfield.imm32 = 1;
1767 t.bitfield.imm32s = 1;
1768 }
1769 else if (fits_in_signed_byte (num))
1770 {
1771 t.bitfield.imm8 = 1;
1772 t.bitfield.imm8s = 1;
1773 t.bitfield.imm16 = 1;
1774 t.bitfield.imm32 = 1;
1775 t.bitfield.imm32s = 1;
1776 }
1777 else if (fits_in_unsigned_byte (num))
1778 {
1779 t.bitfield.imm8 = 1;
1780 t.bitfield.imm16 = 1;
1781 t.bitfield.imm32 = 1;
1782 t.bitfield.imm32s = 1;
1783 }
1784 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1785 {
1786 t.bitfield.imm16 = 1;
1787 t.bitfield.imm32 = 1;
1788 t.bitfield.imm32s = 1;
1789 }
1790 else if (fits_in_signed_long (num))
1791 {
1792 t.bitfield.imm32 = 1;
1793 t.bitfield.imm32s = 1;
1794 }
1795 else if (fits_in_unsigned_long (num))
1796 t.bitfield.imm32 = 1;
1797
1798 return t;
47926f60 1799}
252b5132 1800
847f7ad4 1801static offsetT
e3bb37b5 1802offset_in_range (offsetT val, int size)
847f7ad4 1803{
508866be 1804 addressT mask;
ba2adb93 1805
847f7ad4
AM		 1806 switch (size)
1807 {
508866be
L		 1808 case 1: mask = ((addressT) 1 << 8) - 1; break;
1809 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1810 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1811#ifdef BFD64
1812 case 8: mask = ((addressT) 2 << 63) - 1; break;
1813#endif
47926f60 1814 default: abort ();
847f7ad4
AM		 1815 }
1816
9de868bf
L		 1817#ifdef BFD64
1818 /* If BFD64, sign extend val for 32bit address mode. */
1819 if (flag_code != CODE_64BIT
1820 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1821 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1822 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1823#endif
ba2adb93 1824
47926f60 1825 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1826 {
1827 char buf1[40], buf2[40];
1828
1829 sprint_value (buf1, val);
1830 sprint_value (buf2, val & mask);
1831 as_warn (_("%s shortened to %s"), buf1, buf2);
1832 }
1833 return val & mask;
1834}
1835
c32fa91d
L		 1836enum PREFIX_GROUP
1837{
1838 PREFIX_EXIST = 0,
1839 PREFIX_LOCK,
1840 PREFIX_REP,
1841 PREFIX_OTHER
1842};
1843
1844/* Returns
1845 a. PREFIX_EXIST if attempting to add a prefix where one from the
1846 same class already exists.
1847 b. PREFIX_LOCK if lock prefix is added.
1848 c. PREFIX_REP if rep/repne prefix is added.
1849 d. PREFIX_OTHER if other prefix is added.
1850 */
1851
1852static enum PREFIX_GROUP
e3bb37b5 1853add_prefix (unsigned int prefix)
252b5132 1854{
c32fa91d 1855 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1856 unsigned int q;
252b5132 1857
29b0f896
AM		 1858 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1859 && flag_code == CODE_64BIT)
b1905489 1860 {
161a04f6
L		 1861 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1862 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1863 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1864 ret = PREFIX_EXIST;
b1905489
JB		 1865 q = REX_PREFIX;
1866 }
3e73aa7c 1867 else
b1905489
JB		 1868 {
1869 switch (prefix)
1870 {
1871 default:
1872 abort ();
1873
1874 case CS_PREFIX_OPCODE:
1875 case DS_PREFIX_OPCODE:
1876 case ES_PREFIX_OPCODE:
1877 case FS_PREFIX_OPCODE:
1878 case GS_PREFIX_OPCODE:
1879 case SS_PREFIX_OPCODE:
1880 q = SEG_PREFIX;
1881 break;
1882
1883 case REPNE_PREFIX_OPCODE:
1884 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1885 q = REP_PREFIX;
1886 ret = PREFIX_REP;
1887 break;
1888
b1905489 1889 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1890 q = LOCK_PREFIX;
1891 ret = PREFIX_LOCK;
b1905489
JB		 1892 break;
1893
1894 case FWAIT_OPCODE:
1895 q = WAIT_PREFIX;
1896 break;
1897
1898 case ADDR_PREFIX_OPCODE:
1899 q = ADDR_PREFIX;
1900 break;
1901
1902 case DATA_PREFIX_OPCODE:
1903 q = DATA_PREFIX;
1904 break;
1905 }
1906 if (i.prefix[q] != 0)
c32fa91d 1907 ret = PREFIX_EXIST;
b1905489 1908 }
252b5132 1909
b1905489 1910 if (ret)
252b5132 1911 {
b1905489
JB		 1912 if (!i.prefix[q])
1913 ++i.prefixes;
1914 i.prefix[q] |= prefix;
252b5132 1915 }
b1905489
JB		 1916 else
1917 as_bad (_("same type of prefix used twice"));
252b5132 1918
252b5132
RH		 1919 return ret;
1920}
1921
1922static void
e3bb37b5 1923set_code_flag (int value)
eecb386c 1924{
1e9cc1c2 1925 flag_code = (enum flag_code) value;
40fb9820
L		 1926 if (flag_code == CODE_64BIT)
1927 {
1928 cpu_arch_flags.bitfield.cpu64 = 1;
1929 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1930 }
1931 else
1932 {
1933 cpu_arch_flags.bitfield.cpu64 = 0;
1934 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1935 }
1936 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1937 {
1938 as_bad (_("64bit mode not supported on this CPU."));
1939 }
40fb9820 1940 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1941 {
1942 as_bad (_("32bit mode not supported on this CPU."));
1943 }
eecb386c
AM		 1944 stackop_size = '\0';
1945}
1946
1947static void
e3bb37b5 1948set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1949{
1e9cc1c2 1950 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1951 if (flag_code != CODE_16BIT)
1952 abort ();
1953 cpu_arch_flags.bitfield.cpu64 = 0;
1954 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1955 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1956}
1957
1958static void
e3bb37b5 1959set_intel_syntax (int syntax_flag)
252b5132
RH		 1960{
1961 /* Find out if register prefixing is specified. */
1962 int ask_naked_reg = 0;
1963
1964 SKIP_WHITESPACE ();
29b0f896 1965 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1966 {
1967 char *string = input_line_pointer;
1968 int e = get_symbol_end ();
1969
47926f60 1970 if (strcmp (string, "prefix") == 0)
252b5132 1971 ask_naked_reg = 1;
47926f60 1972 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1973 ask_naked_reg = -1;
1974 else
d0b47220 1975 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1976 *input_line_pointer = e;
1977 }
1978 demand_empty_rest_of_line ();
c3332e24 1979
252b5132
RH		 1980 intel_syntax = syntax_flag;
1981
1982 if (ask_naked_reg == 0)
f86103b7
AM		 1983 allow_naked_reg = (intel_syntax
1984 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1985 else
1986 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1987
ee86248c 1988 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1989
e4a3b5a4 1990 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1991 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1992 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1993}
1994
1efbbeb4
L		 1995static void
1996set_intel_mnemonic (int mnemonic_flag)
1997{
e1d4d893 1998 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1999}
2000
db51cc60
L		 2001static void
2002set_allow_index_reg (int flag)
2003{
2004 allow_index_reg = flag;
2005}
2006
cb19c032
L		 2007static void
2008set_sse_check (int dummy ATTRIBUTE_UNUSED)
2009{
2010 SKIP_WHITESPACE ();
2011
2012 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2013 {
2014 char *string = input_line_pointer;
2015 int e = get_symbol_end ();
2016
2017 if (strcmp (string, "none") == 0)
2018 sse_check = sse_check_none;
2019 else if (strcmp (string, "warning") == 0)
2020 sse_check = sse_check_warning;
2021 else if (strcmp (string, "error") == 0)
2022 sse_check = sse_check_error;
2023 else
2024 as_bad (_("bad argument to sse_check directive."));
2025 *input_line_pointer = e;
2026 }
2027 else
2028 as_bad (_("missing argument for sse_check directive"));
2029
2030 demand_empty_rest_of_line ();
2031}
2032
8a9036a4
L		 2033static void
2034check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2035 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2036{
2037#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2038 static const char *arch;
2039
2040 /* Intel LIOM is only supported on ELF. */
2041 if (!IS_ELF)
2042 return;
2043
2044 if (!arch)
2045 {
2046 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2047 use default_arch. */
2048 arch = cpu_arch_name;
2049 if (!arch)
2050 arch = default_arch;
2051 }
2052
3632d14b 2053 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2054 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2055 || new_flag.bitfield.cpul1om)
8a9036a4 2056 return;
76ba9986 2057
8a9036a4
L		 2058 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2059#endif
2060}
2061
e413e4e9 2062static void
e3bb37b5 2063set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2064{
47926f60 2065 SKIP_WHITESPACE ();
e413e4e9 2066
29b0f896 2067 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2068 {
2069 char *string = input_line_pointer;
2070 int e = get_symbol_end ();
91d6fa6a 2071 unsigned int j;
40fb9820 2072 i386_cpu_flags flags;
e413e4e9 2073
91d6fa6a 2074 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2075 {
91d6fa6a 2076 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2077 {
91d6fa6a 2078 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2079
5c6af06e
JB		 2080 if (*string != '.')
2081 {
91d6fa6a 2082 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2083 cpu_sub_arch_name = NULL;
91d6fa6a 2084 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2085 if (flag_code == CODE_64BIT)
2086 {
2087 cpu_arch_flags.bitfield.cpu64 = 1;
2088 cpu_arch_flags.bitfield.cpuno64 = 0;
2089 }
2090 else
2091 {
2092 cpu_arch_flags.bitfield.cpu64 = 0;
2093 cpu_arch_flags.bitfield.cpuno64 = 1;
2094 }
91d6fa6a
NC		 2095 cpu_arch_isa = cpu_arch[j].type;
2096 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2097 if (!cpu_arch_tune_set)
2098 {
2099 cpu_arch_tune = cpu_arch_isa;
2100 cpu_arch_tune_flags = cpu_arch_isa_flags;
2101 }
5c6af06e
JB		 2102 break;
2103 }
40fb9820 2104
309d3373
JB		 2105 if (strncmp (string + 1, "no", 2))
2106 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2107 cpu_arch[j].flags);
309d3373
JB		 2108 else
2109 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 2110 cpu_arch[j].flags);
0dfbf9d7 2111 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2112 {
6305a203
L		 2113 if (cpu_sub_arch_name)
2114 {
2115 char *name = cpu_sub_arch_name;
2116 cpu_sub_arch_name = concat (name,
91d6fa6a 2117 cpu_arch[j].name,
1bf57e9f 2118 (const char *) NULL);
6305a203
L		 2119 free (name);
2120 }
2121 else
91d6fa6a 2122 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2123 cpu_arch_flags = flags;
5c6af06e
JB		 2124 }
2125 *input_line_pointer = e;
2126 demand_empty_rest_of_line ();
2127 return;
e413e4e9
AM		 2128 }
2129 }
91d6fa6a 2130 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2131 as_bad (_("no such architecture: `%s'"), string);
2132
2133 *input_line_pointer = e;
2134 }
2135 else
2136 as_bad (_("missing cpu architecture"));
2137
fddf5b5b
AM		 2138 no_cond_jump_promotion = 0;
2139 if (*input_line_pointer == ','
29b0f896 2140 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2141 {
2142 char *string = ++input_line_pointer;
2143 int e = get_symbol_end ();
2144
2145 if (strcmp (string, "nojumps") == 0)
2146 no_cond_jump_promotion = 1;
2147 else if (strcmp (string, "jumps") == 0)
2148 ;
2149 else
2150 as_bad (_("no such architecture modifier: `%s'"), string);
2151
2152 *input_line_pointer = e;
2153 }
2154
e413e4e9
AM		 2155 demand_empty_rest_of_line ();
2156}
2157
8a9036a4
L		 2158enum bfd_architecture
2159i386_arch (void)
2160{
3632d14b 2161 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2162 {
2163 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2164 || flag_code != CODE_64BIT)
2165 as_fatal (_("Intel L1OM is 64bit ELF only"));
2166 return bfd_arch_l1om;
2167 }
2168 else
2169 return bfd_arch_i386;
2170}
2171
b9d79e03
JH		 2172unsigned long
2173i386_mach ()
2174{
2175 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2176 {
3632d14b 2177 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2178 {
2179 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2180 as_fatal (_("Intel L1OM is 64bit ELF only"));
2181 return bfd_mach_l1om;
2182 }
2183 else
2184 return bfd_mach_x86_64;
2185 }
b9d79e03
JH		 2186 else if (!strcmp (default_arch, "i386"))
2187 return bfd_mach_i386_i386;
2188 else
2189 as_fatal (_("Unknown architecture"));
2190}
b9d79e03 2191\f
252b5132
RH		 2192void
2193md_begin ()
2194{
2195 const char *hash_err;
2196
47926f60 2197 /* Initialize op_hash hash table. */
252b5132
RH		 2198 op_hash = hash_new ();
2199
2200 {
d3ce72d0 2201 const insn_template *optab;
29b0f896 2202 templates *core_optab;
252b5132 2203
47926f60
KH		 2204 /* Setup for loop. */
2205 optab = i386_optab;
252b5132
RH		 2206 core_optab = (templates *) xmalloc (sizeof (templates));
2207 core_optab->start = optab;
2208
2209 while (1)
2210 {
2211 ++optab;
2212 if (optab->name == NULL
2213 || strcmp (optab->name, (optab - 1)->name) != 0)
2214 {
2215 /* different name --> ship out current template list;
47926f60 2216 add to hash table; & begin anew. */
252b5132
RH		 2217 core_optab->end = optab;
2218 hash_err = hash_insert (op_hash,
2219 (optab - 1)->name,
5a49b8ac 2220 (void *) core_optab);
252b5132
RH		 2221 if (hash_err)
2222 {
252b5132
RH		 2223 as_fatal (_("Internal Error: Can't hash %s: %s"),
2224 (optab - 1)->name,
2225 hash_err);
2226 }
2227 if (optab->name == NULL)
2228 break;
2229 core_optab = (templates *) xmalloc (sizeof (templates));
2230 core_optab->start = optab;
2231 }
2232 }
2233 }
2234
47926f60 2235 /* Initialize reg_hash hash table. */
252b5132
RH		 2236 reg_hash = hash_new ();
2237 {
29b0f896 2238 const reg_entry *regtab;
c3fe08fa 2239 unsigned int regtab_size = i386_regtab_size;
252b5132 2240
c3fe08fa 2241 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2242 {
5a49b8ac 2243 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2244 if (hash_err)
3e73aa7c
JH		 2245 as_fatal (_("Internal Error: Can't hash %s: %s"),
2246 regtab->reg_name,
2247 hash_err);
252b5132
RH		 2248 }
2249 }
2250
47926f60 2251 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2252 {
29b0f896
AM		 2253 int c;
2254 char *p;
252b5132
RH		 2255
2256 for (c = 0; c < 256; c++)
2257 {
3882b010 2258 if (ISDIGIT (c))
252b5132
RH		 2259 {
2260 digit_chars[c] = c;
2261 mnemonic_chars[c] = c;
2262 register_chars[c] = c;
2263 operand_chars[c] = c;
2264 }
3882b010 2265 else if (ISLOWER (c))
252b5132
RH		 2266 {
2267 mnemonic_chars[c] = c;
2268 register_chars[c] = c;
2269 operand_chars[c] = c;
2270 }
3882b010 2271 else if (ISUPPER (c))
252b5132 2272 {
3882b010 2273 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2274 register_chars[c] = mnemonic_chars[c];
2275 operand_chars[c] = c;
2276 }
2277
3882b010 2278 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2279 identifier_chars[c] = c;
2280 else if (c >= 128)
2281 {
2282 identifier_chars[c] = c;
2283 operand_chars[c] = c;
2284 }
2285 }
2286
2287#ifdef LEX_AT
2288 identifier_chars['@'] = '@';
32137342
NC		 2289#endif
2290#ifdef LEX_QM
2291 identifier_chars['?'] = '?';
2292 operand_chars['?'] = '?';
252b5132 2293#endif
252b5132 2294 digit_chars['-'] = '-';
c0f3af97 2295 mnemonic_chars['_'] = '_';
791fe849 2296 mnemonic_chars['-'] = '-';
0003779b 2297 mnemonic_chars['.'] = '.';
252b5132
RH		 2298 identifier_chars['_'] = '_';
2299 identifier_chars['.'] = '.';
2300
2301 for (p = operand_special_chars; *p != '\0'; p++)
2302 operand_chars[(unsigned char) *p] = *p;
2303 }
2304
2305#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2306 if (IS_ELF)
252b5132
RH		 2307 {
2308 record_alignment (text_section, 2);
2309 record_alignment (data_section, 2);
2310 record_alignment (bss_section, 2);
2311 }
2312#endif
a4447b93
RH		 2313
2314 if (flag_code == CODE_64BIT)
2315 {
2316 x86_dwarf2_return_column = 16;
2317 x86_cie_data_alignment = -8;
2318 }
2319 else
2320 {
2321 x86_dwarf2_return_column = 8;
2322 x86_cie_data_alignment = -4;
2323 }
252b5132
RH		 2324}
2325
2326void
e3bb37b5 2327i386_print_statistics (FILE *file)
252b5132
RH		 2328{
2329 hash_print_statistics (file, "i386 opcode", op_hash);
2330 hash_print_statistics (file, "i386 register", reg_hash);
2331}
2332\f
252b5132
RH		 2333#ifdef DEBUG386
2334
ce8a8b2f 2335/* Debugging routines for md_assemble. */
d3ce72d0 2336static void pte (insn_template *);
40fb9820 2337static void pt (i386_operand_type);
e3bb37b5
L		 2338static void pe (expressionS *);
2339static void ps (symbolS *);
252b5132
RH		 2340
2341static void
e3bb37b5 2342pi (char *line, i386_insn *x)
252b5132 2343{
09f131f2 2344 unsigned int i;
252b5132
RH		 2345
2346 fprintf (stdout, "%s: template ", line);
2347 pte (&x->tm);
09f131f2
JH		 2348 fprintf (stdout, " address: base %s index %s scale %x\n",
2349 x->base_reg ? x->base_reg->reg_name : "none",
2350 x->index_reg ? x->index_reg->reg_name : "none",
2351 x->log2_scale_factor);
2352 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2353 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2354 fprintf (stdout, " sib: base %x index %x scale %x\n",
2355 x->sib.base, x->sib.index, x->sib.scale);
2356 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2357 (x->rex & REX_W) != 0,
2358 (x->rex & REX_R) != 0,
2359 (x->rex & REX_X) != 0,
2360 (x->rex & REX_B) != 0);
252b5132
RH		 2361 for (i = 0; i < x->operands; i++)
2362 {
2363 fprintf (stdout, " #%d: ", i + 1);
2364 pt (x->types[i]);
2365 fprintf (stdout, "\n");
40fb9820
L		 2366 if (x->types[i].bitfield.reg8
2367 || x->types[i].bitfield.reg16
2368 || x->types[i].bitfield.reg32
2369 || x->types[i].bitfield.reg64
2370 || x->types[i].bitfield.regmmx
2371 || x->types[i].bitfield.regxmm
c0f3af97 2372 || x->types[i].bitfield.regymm
40fb9820
L		 2373 || x->types[i].bitfield.sreg2
2374 || x->types[i].bitfield.sreg3
2375 || x->types[i].bitfield.control
2376 || x->types[i].bitfield.debug
2377 || x->types[i].bitfield.test)
520dc8e8 2378 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2379 if (operand_type_check (x->types[i], imm))
520dc8e8 2380 pe (x->op[i].imms);
40fb9820 2381 if (operand_type_check (x->types[i], disp))
520dc8e8 2382 pe (x->op[i].disps);
252b5132
RH		 2383 }
2384}
2385
2386static void
d3ce72d0 2387pte (insn_template *t)
252b5132 2388{
09f131f2 2389 unsigned int i;
252b5132 2390 fprintf (stdout, " %d operands ", t->operands);
47926f60 2391 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2392 if (t->extension_opcode != None)
2393 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2394 if (t->opcode_modifier.d)
252b5132 2395 fprintf (stdout, "D");
40fb9820 2396 if (t->opcode_modifier.w)
252b5132
RH		 2397 fprintf (stdout, "W");
2398 fprintf (stdout, "\n");
2399 for (i = 0; i < t->operands; i++)
2400 {
2401 fprintf (stdout, " #%d type ", i + 1);
2402 pt (t->operand_types[i]);
2403 fprintf (stdout, "\n");
2404 }
2405}
2406
2407static void
e3bb37b5 2408pe (expressionS *e)
252b5132 2409{
24eab124 2410 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2411 fprintf (stdout, " add_number %ld (%lx)\n",
2412 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2413 if (e->X_add_symbol)
2414 {
2415 fprintf (stdout, " add_symbol ");
2416 ps (e->X_add_symbol);
2417 fprintf (stdout, "\n");
2418 }
2419 if (e->X_op_symbol)
2420 {
2421 fprintf (stdout, " op_symbol ");
2422 ps (e->X_op_symbol);
2423 fprintf (stdout, "\n");
2424 }
2425}
2426
2427static void
e3bb37b5 2428ps (symbolS *s)
252b5132
RH		 2429{
2430 fprintf (stdout, "%s type %s%s",
2431 S_GET_NAME (s),
2432 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2433 segment_name (S_GET_SEGMENT (s)));
2434}
2435
7b81dfbb 2436static struct type_name
252b5132 2437 {
40fb9820
L		 2438 i386_operand_type mask;
2439 const char *name;
252b5132 2440 }
7b81dfbb 2441const type_names[] =
252b5132 2442{
40fb9820
L		 2443 { OPERAND_TYPE_REG8, "r8" },
2444 { OPERAND_TYPE_REG16, "r16" },
2445 { OPERAND_TYPE_REG32, "r32" },
2446 { OPERAND_TYPE_REG64, "r64" },
2447 { OPERAND_TYPE_IMM8, "i8" },
2448 { OPERAND_TYPE_IMM8, "i8s" },
2449 { OPERAND_TYPE_IMM16, "i16" },
2450 { OPERAND_TYPE_IMM32, "i32" },
2451 { OPERAND_TYPE_IMM32S, "i32s" },
2452 { OPERAND_TYPE_IMM64, "i64" },
2453 { OPERAND_TYPE_IMM1, "i1" },
2454 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2455 { OPERAND_TYPE_DISP8, "d8" },
2456 { OPERAND_TYPE_DISP16, "d16" },
2457 { OPERAND_TYPE_DISP32, "d32" },
2458 { OPERAND_TYPE_DISP32S, "d32s" },
2459 { OPERAND_TYPE_DISP64, "d64" },
2460 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2461 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2462 { OPERAND_TYPE_CONTROL, "control reg" },
2463 { OPERAND_TYPE_TEST, "test reg" },
2464 { OPERAND_TYPE_DEBUG, "debug reg" },
2465 { OPERAND_TYPE_FLOATREG, "FReg" },
2466 { OPERAND_TYPE_FLOATACC, "FAcc" },
2467 { OPERAND_TYPE_SREG2, "SReg2" },
2468 { OPERAND_TYPE_SREG3, "SReg3" },
2469 { OPERAND_TYPE_ACC, "Acc" },
2470 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2471 { OPERAND_TYPE_REGMMX, "rMMX" },
2472 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2473 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2474 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2475};
2476
2477static void
40fb9820 2478pt (i386_operand_type t)
252b5132 2479{
40fb9820 2480 unsigned int j;
c6fb90c8 2481 i386_operand_type a;
252b5132 2482
40fb9820 2483 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2484 {
2485 a = operand_type_and (t, type_names[j].mask);
0349dc08 2486 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2487 fprintf (stdout, "%s, ", type_names[j].name);
2488 }
252b5132
RH		 2489 fflush (stdout);
2490}
2491
2492#endif /* DEBUG386 */
2493\f
252b5132 2494static bfd_reloc_code_real_type
3956db08 2495reloc (unsigned int size,
64e74474
AM		 2496 int pcrel,
2497 int sign,
2498 bfd_reloc_code_real_type other)
252b5132 2499{
47926f60 2500 if (other != NO_RELOC)
3956db08 2501 {
91d6fa6a 2502 reloc_howto_type *rel;
3956db08
JB		 2503
2504 if (size == 8)
2505 switch (other)
2506 {
64e74474
AM		 2507 case BFD_RELOC_X86_64_GOT32:
2508 return BFD_RELOC_X86_64_GOT64;
2509 break;
2510 case BFD_RELOC_X86_64_PLTOFF64:
2511 return BFD_RELOC_X86_64_PLTOFF64;
2512 break;
2513 case BFD_RELOC_X86_64_GOTPC32:
2514 other = BFD_RELOC_X86_64_GOTPC64;
2515 break;
2516 case BFD_RELOC_X86_64_GOTPCREL:
2517 other = BFD_RELOC_X86_64_GOTPCREL64;
2518 break;
2519 case BFD_RELOC_X86_64_TPOFF32:
2520 other = BFD_RELOC_X86_64_TPOFF64;
2521 break;
2522 case BFD_RELOC_X86_64_DTPOFF32:
2523 other = BFD_RELOC_X86_64_DTPOFF64;
2524 break;
2525 default:
2526 break;
3956db08 2527 }
e05278af
JB		 2528
2529 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2530 if (size == 4 && flag_code != CODE_64BIT)
2531 sign = -1;
2532
91d6fa6a
NC		 2533 rel = bfd_reloc_type_lookup (stdoutput, other);
2534 if (!rel)
3956db08 2535 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2536 else if (size != bfd_get_reloc_size (rel))
3956db08 2537 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2538 bfd_get_reloc_size (rel),
3956db08 2539 size);
91d6fa6a 2540 else if (pcrel && !rel->pc_relative)
3956db08 2541 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2542 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2543 && !sign)
91d6fa6a 2544 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2545 && sign > 0))
3956db08
JB		 2546 as_bad (_("relocated field and relocation type differ in signedness"));
2547 else
2548 return other;
2549 return NO_RELOC;
2550 }
252b5132
RH		 2551
2552 if (pcrel)
2553 {
3e73aa7c 2554 if (!sign)
3956db08 2555 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2556 switch (size)
2557 {
2558 case 1: return BFD_RELOC_8_PCREL;
2559 case 2: return BFD_RELOC_16_PCREL;
2560 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2561 case 8: return BFD_RELOC_64_PCREL;
252b5132 2562 }
3956db08 2563 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2564 }
2565 else
2566 {
3956db08 2567 if (sign > 0)
e5cb08ac 2568 switch (size)
3e73aa7c
JH		 2569 {
2570 case 4: return BFD_RELOC_X86_64_32S;
2571 }
2572 else
2573 switch (size)
2574 {
2575 case 1: return BFD_RELOC_8;
2576 case 2: return BFD_RELOC_16;
2577 case 4: return BFD_RELOC_32;
2578 case 8: return BFD_RELOC_64;
2579 }
3956db08
JB		 2580 as_bad (_("cannot do %s %u byte relocation"),
2581 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2582 }
2583
0cc9e1d3 2584 return NO_RELOC;
252b5132
RH		 2585}
2586
47926f60
KH		 2587/* Here we decide which fixups can be adjusted to make them relative to
2588 the beginning of the section instead of the symbol. Basically we need
2589 to make sure that the dynamic relocations are done correctly, so in
2590 some cases we force the original symbol to be used. */
2591
252b5132 2592int
e3bb37b5 2593tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2594{
6d249963 2595#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2596 if (!IS_ELF)
31312f95
AM		 2597 return 1;
2598
a161fe53
AM		 2599 /* Don't adjust pc-relative references to merge sections in 64-bit
2600 mode. */
2601 if (use_rela_relocations
2602 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2603 && fixP->fx_pcrel)
252b5132 2604 return 0;
31312f95 2605
8d01d9a9
AJ		 2606 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2607 and changed later by validate_fix. */
2608 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2609 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2610 return 0;
2611
ce8a8b2f 2612 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2613 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2614 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2615 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2616 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2617 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2618 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2619 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2620 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2621 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2622 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2623 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2624 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2625 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2626 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2627 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2628 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2629 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2630 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2631 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2632 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2633 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2634 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2635 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2636 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2637 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2638 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2639 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2640 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2641 return 0;
31312f95 2642#endif
252b5132
RH		 2643 return 1;
2644}
252b5132 2645
b4cac588 2646static int
e3bb37b5 2647intel_float_operand (const char *mnemonic)
252b5132 2648{
9306ca4a
JB		 2649 /* Note that the value returned is meaningful only for opcodes with (memory)
2650 operands, hence the code here is free to improperly handle opcodes that
2651 have no operands (for better performance and smaller code). */
2652
2653 if (mnemonic[0] != 'f')
2654 return 0; /* non-math */
2655
2656 switch (mnemonic[1])
2657 {
2658 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2659 the fs segment override prefix not currently handled because no
2660 call path can make opcodes without operands get here */
2661 case 'i':
2662 return 2 /* integer op */;
2663 case 'l':
2664 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2665 return 3; /* fldcw/fldenv */
2666 break;
2667 case 'n':
2668 if (mnemonic[2] != 'o' /* fnop */)
2669 return 3; /* non-waiting control op */
2670 break;
2671 case 'r':
2672 if (mnemonic[2] == 's')
2673 return 3; /* frstor/frstpm */
2674 break;
2675 case 's':
2676 if (mnemonic[2] == 'a')
2677 return 3; /* fsave */
2678 if (mnemonic[2] == 't')
2679 {
2680 switch (mnemonic[3])
2681 {
2682 case 'c': /* fstcw */
2683 case 'd': /* fstdw */
2684 case 'e': /* fstenv */
2685 case 's': /* fsts[gw] */
2686 return 3;
2687 }
2688 }
2689 break;
2690 case 'x':
2691 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2692 return 0; /* fxsave/fxrstor are not really math ops */
2693 break;
2694 }
252b5132 2695
9306ca4a 2696 return 1;
252b5132
RH		 2697}
2698
c0f3af97
L		 2699/* Build the VEX prefix. */
2700
2701static void
d3ce72d0 2702build_vex_prefix (const insn_template *t)
c0f3af97
L		 2703{
2704 unsigned int register_specifier;
2705 unsigned int implied_prefix;
2706 unsigned int vector_length;
2707
2708 /* Check register specifier. */
2709 if (i.vex.register_specifier)
2710 {
2711 register_specifier = i.vex.register_specifier->reg_num;
2712 if ((i.vex.register_specifier->reg_flags & RegRex))
2713 register_specifier += 8;
2714 register_specifier = ~register_specifier & 0xf;
2715 }
2716 else
2717 register_specifier = 0xf;
2718
fa99fab2
L		 2719 /* Use 2-byte VEX prefix by swappping destination and source
2720 operand. */
2721 if (!i.swap_operand
2722 && i.operands == i.reg_operands
7f399153 2723 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2724 && i.tm.opcode_modifier.s
2725 && i.rex == REX_B)
2726 {
2727 unsigned int xchg = i.operands - 1;
2728 union i386_op temp_op;
2729 i386_operand_type temp_type;
2730
2731 temp_type = i.types[xchg];
2732 i.types[xchg] = i.types[0];
2733 i.types[0] = temp_type;
2734 temp_op = i.op[xchg];
2735 i.op[xchg] = i.op[0];
2736 i.op[0] = temp_op;
2737
9c2799c2 2738 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2739
2740 i.rex = REX_R;
2741 xchg = i.rm.regmem;
2742 i.rm.regmem = i.rm.reg;
2743 i.rm.reg = xchg;
2744
2745 /* Use the next insn. */
2746 i.tm = t[1];
2747 }
2748
539f890d
L		 2749 if (i.tm.opcode_modifier.vex == VEXScalar)
2750 vector_length = avxscalar;
2751 else
2752 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2753
2754 switch ((i.tm.base_opcode >> 8) & 0xff)
2755 {
2756 case 0:
2757 implied_prefix = 0;
2758 break;
2759 case DATA_PREFIX_OPCODE:
2760 implied_prefix = 1;
2761 break;
2762 case REPE_PREFIX_OPCODE:
2763 implied_prefix = 2;
2764 break;
2765 case REPNE_PREFIX_OPCODE:
2766 implied_prefix = 3;
2767 break;
2768 default:
2769 abort ();
2770 }
2771
2772 /* Use 2-byte VEX prefix if possible. */
7f399153 2773 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2774 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2775 {
2776 /* 2-byte VEX prefix. */
2777 unsigned int r;
2778
2779 i.vex.length = 2;
2780 i.vex.bytes[0] = 0xc5;
2781
2782 /* Check the REX.R bit. */
2783 r = (i.rex & REX_R) ? 0 : 1;
2784 i.vex.bytes[1] = (r << 7
2785 | register_specifier << 3
2786 | vector_length << 2
2787 | implied_prefix);
2788 }
2789 else
2790 {
2791 /* 3-byte VEX prefix. */
2792 unsigned int m, w;
2793
f88c9eb0 2794 i.vex.length = 3;
f88c9eb0 2795
7f399153 2796 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2797 {
7f399153
L		 2798 case VEX0F:
2799 m = 0x1;
80de6e00 2800 i.vex.bytes[0] = 0xc4;
7f399153
L		 2801 break;
2802 case VEX0F38:
2803 m = 0x2;
80de6e00 2804 i.vex.bytes[0] = 0xc4;
7f399153
L		 2805 break;
2806 case VEX0F3A:
2807 m = 0x3;
80de6e00 2808 i.vex.bytes[0] = 0xc4;
7f399153
L		 2809 break;
2810 case XOP08:
5dd85c99
SP		 2811 m = 0x8;
2812 i.vex.bytes[0] = 0x8f;
7f399153
L		 2813 break;
2814 case XOP09:
f88c9eb0
SP		 2815 m = 0x9;
2816 i.vex.bytes[0] = 0x8f;
7f399153
L		 2817 break;
2818 case XOP0A:
f88c9eb0
SP		 2819 m = 0xa;
2820 i.vex.bytes[0] = 0x8f;
7f399153
L		 2821 break;
2822 default:
2823 abort ();
f88c9eb0 2824 }
c0f3af97 2825
c0f3af97
L		 2826 /* The high 3 bits of the second VEX byte are 1's compliment
2827 of RXB bits from REX. */
2828 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2829
2830 /* Check the REX.W bit. */
2831 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2832 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2833 {
2834 if (w)
2835 abort ();
2836
1ef99a7b 2837 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2838 w = 1;
2839 }
2840
2841 i.vex.bytes[2] = (w << 7
2842 | register_specifier << 3
2843 | vector_length << 2
2844 | implied_prefix);
2845 }
2846}
2847
65da13b5
L		 2848static void
2849process_immext (void)
2850{
2851 expressionS *exp;
2852
2853 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2854 {
1fed0ba1
L		 2855 /* SSE3 Instructions have the fixed operands with an opcode
2856 suffix which is coded in the same place as an 8-bit immediate
2857 field would be. Here we check those operands and remove them
2858 afterwards. */
65da13b5
L		 2859 unsigned int x;
2860
2861 for (x = 0; x < i.operands; x++)
2862 if (i.op[x].regs->reg_num != x)
2863 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2864 register_prefix, i.op[x].regs->reg_name, x + 1,
2865 i.tm.name);
2866
2867 i.operands = 0;
65da13b5
L		 2868 }
2869
c0f3af97 2870 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2871 which is coded in the same place as an 8-bit immediate field
2872 would be. Here we fake an 8-bit immediate operand from the
2873 opcode suffix stored in tm.extension_opcode.
2874
c1e679ec 2875 AVX instructions also use this encoding, for some of
c0f3af97 2876 3 argument instructions. */
65da13b5 2877
9c2799c2 2878 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2879 && (i.operands <= 2
2880 || (i.tm.opcode_modifier.vex
2881 && i.operands <= 4)));
65da13b5
L		 2882
2883 exp = &im_expressions[i.imm_operands++];
2884 i.op[i.operands].imms = exp;
2885 i.types[i.operands] = imm8;
2886 i.operands++;
2887 exp->X_op = O_constant;
2888 exp->X_add_number = i.tm.extension_opcode;
2889 i.tm.extension_opcode = None;
2890}
2891
252b5132
RH		 2892/* This is the guts of the machine-dependent assembler. LINE points to a
2893 machine dependent instruction. This function is supposed to emit
2894 the frags/bytes it assembles to. */
2895
2896void
65da13b5 2897md_assemble (char *line)
252b5132 2898{
40fb9820 2899 unsigned int j;
252b5132 2900 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2901 const insn_template *t;
252b5132 2902
47926f60 2903 /* Initialize globals. */
252b5132
RH		 2904 memset (&i, '\0', sizeof (i));
2905 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2906 i.reloc[j] = NO_RELOC;
252b5132
RH		 2907 memset (disp_expressions, '\0', sizeof (disp_expressions));
2908 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2909 save_stack_p = save_stack;
252b5132
RH		 2910
2911 /* First parse an instruction mnemonic & call i386_operand for the operands.
2912 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2913 start of a (possibly prefixed) mnemonic. */
252b5132 2914
29b0f896
AM		 2915 line = parse_insn (line, mnemonic);
2916 if (line == NULL)
2917 return;
252b5132 2918
29b0f896 2919 line = parse_operands (line, mnemonic);
ee86248c 2920 this_operand = -1;
29b0f896
AM		 2921 if (line == NULL)
2922 return;
252b5132 2923
29b0f896
AM		 2924 /* Now we've parsed the mnemonic into a set of templates, and have the
2925 operands at hand. */
2926
2927 /* All intel opcodes have reversed operands except for "bound" and
2928 "enter". We also don't reverse intersegment "jmp" and "call"
2929 instructions with 2 immediate operands so that the immediate segment
050dfa73 2930 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2931 if (intel_syntax
2932 && i.operands > 1
29b0f896 2933 && (strcmp (mnemonic, "bound") != 0)
30123838 2934 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2935 && !(operand_type_check (i.types[0], imm)
2936 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2937 swap_operands ();
2938
ec56d5c0
JB		 2939 /* The order of the immediates should be reversed
2940 for 2 immediates extrq and insertq instructions */
2941 if (i.imm_operands == 2
2942 && (strcmp (mnemonic, "extrq") == 0
2943 || strcmp (mnemonic, "insertq") == 0))
2944 swap_2_operands (0, 1);
2945
29b0f896
AM		 2946 if (i.imm_operands)
2947 optimize_imm ();
2948
b300c311
L		 2949 /* Don't optimize displacement for movabs since it only takes 64bit
2950 displacement. */
2951 if (i.disp_operands
2952 && (flag_code != CODE_64BIT
2953 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2954 optimize_disp ();
2955
2956 /* Next, we find a template that matches the given insn,
2957 making sure the overlap of the given operands types is consistent
2958 with the template operand types. */
252b5132 2959
fa99fab2 2960 if (!(t = match_template ()))
29b0f896 2961 return;
252b5132 2962
daf50ae7 2963 if (sse_check != sse_check_none
81f8a913 2964 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2965 && (i.tm.cpu_flags.bitfield.cpusse
2966 || i.tm.cpu_flags.bitfield.cpusse2
2967 || i.tm.cpu_flags.bitfield.cpusse3
2968 || i.tm.cpu_flags.bitfield.cpussse3
2969 || i.tm.cpu_flags.bitfield.cpusse4_1
2970 || i.tm.cpu_flags.bitfield.cpusse4_2))
2971 {
2972 (sse_check == sse_check_warning
2973 ? as_warn
2974 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2975 }
2976
321fd21e
L		 2977 /* Zap movzx and movsx suffix. The suffix has been set from
2978 "word ptr" or "byte ptr" on the source operand in Intel syntax
2979 or extracted from mnemonic in AT&T syntax. But we'll use
2980 the destination register to choose the suffix for encoding. */
2981 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2982 {
321fd21e
L		 2983 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2984 there is no suffix, the default will be byte extension. */
2985 if (i.reg_operands != 2
2986 && !i.suffix
7ab9ffdd 2987 && intel_syntax)
321fd21e
L		 2988 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2989
2990 i.suffix = 0;
cd61ebfe 2991 }
24eab124 2992
40fb9820 2993 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2994 if (!add_prefix (FWAIT_OPCODE))
2995 return;
252b5132 2996
c1ba0266
L		 2997 /* Check for lock without a lockable instruction. Destination operand
2998 must be memory unless it is xchg (0x86). */
c32fa91d
L		 2999 if (i.prefix[LOCK_PREFIX]
3000 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3001 || i.mem_operands == 0
3002 || (i.tm.base_opcode != 0x86
3003 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3004 {
3005 as_bad (_("expecting lockable instruction after `lock'"));
3006 return;
3007 }
3008
29b0f896 3009 /* Check string instruction segment overrides. */
40fb9820 3010 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3011 {
3012 if (!check_string ())
5dd0794d 3013 return;
fc0763e6 3014 i.disp_operands = 0;
29b0f896 3015 }
5dd0794d 3016
29b0f896
AM		 3017 if (!process_suffix ())
3018 return;
e413e4e9 3019
bc0844ae
L		 3020 /* Update operand types. */
3021 for (j = 0; j < i.operands; j++)
3022 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3023
29b0f896
AM		 3024 /* Make still unresolved immediate matches conform to size of immediate
3025 given in i.suffix. */
3026 if (!finalize_imm ())
3027 return;
252b5132 3028
40fb9820 3029 if (i.types[0].bitfield.imm1)
29b0f896 3030 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3031
9afe6eb8
L		 3032 /* We only need to check those implicit registers for instructions
3033 with 3 operands or less. */
3034 if (i.operands <= 3)
3035 for (j = 0; j < i.operands; j++)
3036 if (i.types[j].bitfield.inoutportreg
3037 || i.types[j].bitfield.shiftcount
3038 || i.types[j].bitfield.acc
3039 || i.types[j].bitfield.floatacc)
3040 i.reg_operands--;
40fb9820 3041
c0f3af97
L		 3042 /* ImmExt should be processed after SSE2AVX. */
3043 if (!i.tm.opcode_modifier.sse2avx
3044 && i.tm.opcode_modifier.immext)
65da13b5 3045 process_immext ();
252b5132 3046
29b0f896
AM		 3047 /* For insns with operands there are more diddles to do to the opcode. */
3048 if (i.operands)
3049 {
3050 if (!process_operands ())
3051 return;
3052 }
40fb9820 3053 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3054 {
3055 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3056 as_warn (_("translating to `%sp'"), i.tm.name);
3057 }
252b5132 3058
c0f3af97 3059 if (i.tm.opcode_modifier.vex)
fa99fab2 3060 build_vex_prefix (t);
c0f3af97 3061
5dd85c99
SP		 3062 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3063 instructions may define INT_OPCODE as well, so avoid this corner
3064 case for those instructions that use MODRM. */
3065 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3066 && !i.tm.opcode_modifier.modrm
3067 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3068 {
3069 i.tm.base_opcode = INT3_OPCODE;
3070 i.imm_operands = 0;
3071 }
252b5132 3072
40fb9820
L		 3073 if ((i.tm.opcode_modifier.jump
3074 || i.tm.opcode_modifier.jumpbyte
3075 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3076 && i.op[0].disps->X_op == O_constant)
3077 {
3078 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3079 the absolute address given by the constant. Since ix86 jumps and
3080 calls are pc relative, we need to generate a reloc. */
3081 i.op[0].disps->X_add_symbol = &abs_symbol;
3082 i.op[0].disps->X_op = O_symbol;
3083 }
252b5132 3084
40fb9820 3085 if (i.tm.opcode_modifier.rex64)
161a04f6 3086 i.rex |= REX_W;
252b5132 3087
29b0f896
AM		 3088 /* For 8 bit registers we need an empty rex prefix. Also if the
3089 instruction already has a prefix, we need to convert old
3090 registers to new ones. */
773f551c 3091
40fb9820 3092 if ((i.types[0].bitfield.reg8
29b0f896 3093 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3094 || (i.types[1].bitfield.reg8
29b0f896 3095 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3096 || ((i.types[0].bitfield.reg8
3097 || i.types[1].bitfield.reg8)
29b0f896
AM		 3098 && i.rex != 0))
3099 {
3100 int x;
726c5dcd 3101
29b0f896
AM		 3102 i.rex |= REX_OPCODE;
3103 for (x = 0; x < 2; x++)
3104 {
3105 /* Look for 8 bit operand that uses old registers. */
40fb9820 3106 if (i.types[x].bitfield.reg8
29b0f896 3107 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3108 {
29b0f896
AM		 3109 /* In case it is "hi" register, give up. */
3110 if (i.op[x].regs->reg_num > 3)
a540244d 3111 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3112 "instruction requiring REX prefix."),
a540244d 3113 register_prefix, i.op[x].regs->reg_name);
773f551c 3114
29b0f896
AM		 3115 /* Otherwise it is equivalent to the extended register.
3116 Since the encoding doesn't change this is merely
3117 cosmetic cleanup for debug output. */
3118
3119 i.op[x].regs = i.op[x].regs + 8;
773f551c 3120 }
29b0f896
AM		 3121 }
3122 }
773f551c 3123
7ab9ffdd 3124 if (i.rex != 0)
29b0f896
AM		 3125 add_prefix (REX_OPCODE | i.rex);
3126
3127 /* We are ready to output the insn. */
3128 output_insn ();
3129}
3130
3131static char *
e3bb37b5 3132parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3133{
3134 char *l = line;
3135 char *token_start = l;
3136 char *mnem_p;
5c6af06e 3137 int supported;
d3ce72d0 3138 const insn_template *t;
b6169b20 3139 char *dot_p = NULL;
29b0f896
AM		 3140
3141 /* Non-zero if we found a prefix only acceptable with string insns. */
3142 const char *expecting_string_instruction = NULL;
45288df1 3143
29b0f896
AM		 3144 while (1)
3145 {
3146 mnem_p = mnemonic;
3147 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3148 {
b6169b20
L		 3149 if (*mnem_p == '.')
3150 dot_p = mnem_p;
29b0f896
AM		 3151 mnem_p++;
3152 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3153 {
29b0f896
AM		 3154 as_bad (_("no such instruction: `%s'"), token_start);
3155 return NULL;
3156 }
3157 l++;
3158 }
3159 if (!is_space_char (*l)
3160 && *l != END_OF_INSN
e44823cf
JB		 3161 && (intel_syntax
3162 || (*l != PREFIX_SEPARATOR
3163 && *l != ',')))
29b0f896
AM		 3164 {
3165 as_bad (_("invalid character %s in mnemonic"),
3166 output_invalid (*l));
3167 return NULL;
3168 }
3169 if (token_start == l)
3170 {
e44823cf 3171 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3172 as_bad (_("expecting prefix; got nothing"));
3173 else
3174 as_bad (_("expecting mnemonic; got nothing"));
3175 return NULL;
3176 }
45288df1 3177
29b0f896 3178 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3179 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3180
29b0f896
AM		 3181 if (*l != END_OF_INSN
3182 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3183 && current_templates
40fb9820 3184 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3185 {
c6fb90c8 3186 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3187 {
3188 as_bad ((flag_code != CODE_64BIT
3189 ? _("`%s' is only supported in 64-bit mode")
3190 : _("`%s' is not supported in 64-bit mode")),
3191 current_templates->start->name);
3192 return NULL;
3193 }
29b0f896
AM		 3194 /* If we are in 16-bit mode, do not allow addr16 or data16.
3195 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3196 if ((current_templates->start->opcode_modifier.size16
3197 || current_templates->start->opcode_modifier.size32)
29b0f896 3198 && flag_code != CODE_64BIT
40fb9820 3199 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3200 ^ (flag_code == CODE_16BIT)))
3201 {
3202 as_bad (_("redundant %s prefix"),
3203 current_templates->start->name);
3204 return NULL;
45288df1 3205 }
29b0f896
AM		 3206 /* Add prefix, checking for repeated prefixes. */
3207 switch (add_prefix (current_templates->start->base_opcode))
3208 {
c32fa91d 3209 case PREFIX_EXIST:
29b0f896 3210 return NULL;
c32fa91d 3211 case PREFIX_REP:
29b0f896
AM		 3212 expecting_string_instruction = current_templates->start->name;
3213 break;
c32fa91d
L		 3214 default:
3215 break;
29b0f896
AM		 3216 }
3217 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3218 token_start = ++l;
3219 }
3220 else
3221 break;
3222 }
45288df1 3223
30a55f88 3224 if (!current_templates)
b6169b20 3225 {
30a55f88
L		 3226 /* Check if we should swap operand in encoding. */
3227 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3228 i.swap_operand = 1;
3229 else
3230 goto check_suffix;
3231 mnem_p = dot_p;
3232 *dot_p = '\0';
d3ce72d0 3233 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3234 }
3235
29b0f896
AM		 3236 if (!current_templates)
3237 {
b6169b20 3238check_suffix:
29b0f896
AM		 3239 /* See if we can get a match by trimming off a suffix. */
3240 switch (mnem_p[-1])
3241 {
3242 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3243 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3244 i.suffix = SHORT_MNEM_SUFFIX;
3245 else
29b0f896
AM		 3246 case BYTE_MNEM_SUFFIX:
3247 case QWORD_MNEM_SUFFIX:
3248 i.suffix = mnem_p[-1];
3249 mnem_p[-1] = '\0';
d3ce72d0
NC		 3250 current_templates = (const templates *) hash_find (op_hash,
3251 mnemonic);
29b0f896
AM		 3252 break;
3253 case SHORT_MNEM_SUFFIX:
3254 case LONG_MNEM_SUFFIX:
3255 if (!intel_syntax)
3256 {
3257 i.suffix = mnem_p[-1];
3258 mnem_p[-1] = '\0';
d3ce72d0
NC		 3259 current_templates = (const templates *) hash_find (op_hash,
3260 mnemonic);
29b0f896
AM		 3261 }
3262 break;
252b5132 3263
29b0f896
AM		 3264 /* Intel Syntax. */
3265 case 'd':
3266 if (intel_syntax)
3267 {
9306ca4a 3268 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3269 i.suffix = SHORT_MNEM_SUFFIX;
3270 else
3271 i.suffix = LONG_MNEM_SUFFIX;
3272 mnem_p[-1] = '\0';
d3ce72d0
NC		 3273 current_templates = (const templates *) hash_find (op_hash,
3274 mnemonic);
29b0f896
AM		 3275 }
3276 break;
3277 }
3278 if (!current_templates)
3279 {
3280 as_bad (_("no such instruction: `%s'"), token_start);
3281 return NULL;
3282 }
3283 }
252b5132 3284
40fb9820
L		 3285 if (current_templates->start->opcode_modifier.jump
3286 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3287 {
3288 /* Check for a branch hint. We allow ",pt" and ",pn" for
3289 predict taken and predict not taken respectively.
3290 I'm not sure that branch hints actually do anything on loop
3291 and jcxz insns (JumpByte) for current Pentium4 chips. They
3292 may work in the future and it doesn't hurt to accept them
3293 now. */
3294 if (l[0] == ',' && l[1] == 'p')
3295 {
3296 if (l[2] == 't')
3297 {
3298 if (!add_prefix (DS_PREFIX_OPCODE))
3299 return NULL;
3300 l += 3;
3301 }
3302 else if (l[2] == 'n')
3303 {
3304 if (!add_prefix (CS_PREFIX_OPCODE))
3305 return NULL;
3306 l += 3;
3307 }
3308 }
3309 }
3310 /* Any other comma loses. */
3311 if (*l == ',')
3312 {
3313 as_bad (_("invalid character %s in mnemonic"),
3314 output_invalid (*l));
3315 return NULL;
3316 }
252b5132 3317
29b0f896 3318 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3319 supported = 0;
3320 for (t = current_templates->start; t < current_templates->end; ++t)
3321 {
c0f3af97
L		 3322 supported |= cpu_flags_match (t);
3323 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3324 goto skip;
5c6af06e 3325 }
3629bb00 3326
c0f3af97 3327 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3328 {
3329 as_bad (flag_code == CODE_64BIT
3330 ? _("`%s' is not supported in 64-bit mode")
3331 : _("`%s' is only supported in 64-bit mode"),
3332 current_templates->start->name);
3333 return NULL;
3334 }
c0f3af97 3335 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3336 {
3629bb00 3337 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3338 current_templates->start->name,
41aacd83 3339 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3340 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3341 return NULL;
29b0f896 3342 }
3629bb00
L		 3343
3344skip:
3345 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3346 && (flag_code != CODE_16BIT))
29b0f896
AM		 3347 {
3348 as_warn (_("use .code16 to ensure correct addressing mode"));
3349 }
252b5132 3350
29b0f896 3351 /* Check for rep/repne without a string instruction. */
f41bbced 3352 if (expecting_string_instruction)
29b0f896 3353 {
f41bbced
JB		 3354 static templates override;
3355
3356 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3357 if (t->opcode_modifier.isstring)
f41bbced
JB		 3358 break;
3359 if (t >= current_templates->end)
3360 {
3361 as_bad (_("expecting string instruction after `%s'"),
64e74474 3362 expecting_string_instruction);
f41bbced
JB		 3363 return NULL;
3364 }
3365 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3366 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3367 break;
3368 override.end = t;
3369 current_templates = &override;
29b0f896 3370 }
252b5132 3371
29b0f896
AM		 3372 return l;
3373}
252b5132 3374
29b0f896 3375static char *
e3bb37b5 3376parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3377{
3378 char *token_start;
3138f287 3379
29b0f896
AM		 3380 /* 1 if operand is pending after ','. */
3381 unsigned int expecting_operand = 0;
252b5132 3382
29b0f896
AM		 3383 /* Non-zero if operand parens not balanced. */
3384 unsigned int paren_not_balanced;
3385
3386 while (*l != END_OF_INSN)
3387 {
3388 /* Skip optional white space before operand. */
3389 if (is_space_char (*l))
3390 ++l;
3391 if (!is_operand_char (*l) && *l != END_OF_INSN)
3392 {
3393 as_bad (_("invalid character %s before operand %d"),
3394 output_invalid (*l),
3395 i.operands + 1);
3396 return NULL;
3397 }
3398 token_start = l; /* after white space */
3399 paren_not_balanced = 0;
3400 while (paren_not_balanced || *l != ',')
3401 {
3402 if (*l == END_OF_INSN)
3403 {
3404 if (paren_not_balanced)
3405 {
3406 if (!intel_syntax)
3407 as_bad (_("unbalanced parenthesis in operand %d."),
3408 i.operands + 1);
3409 else
3410 as_bad (_("unbalanced brackets in operand %d."),
3411 i.operands + 1);
3412 return NULL;
3413 }
3414 else
3415 break; /* we are done */
3416 }
3417 else if (!is_operand_char (*l) && !is_space_char (*l))
3418 {
3419 as_bad (_("invalid character %s in operand %d"),
3420 output_invalid (*l),
3421 i.operands + 1);
3422 return NULL;
3423 }
3424 if (!intel_syntax)
3425 {
3426 if (*l == '(')
3427 ++paren_not_balanced;
3428 if (*l == ')')
3429 --paren_not_balanced;
3430 }
3431 else
3432 {
3433 if (*l == '[')
3434 ++paren_not_balanced;
3435 if (*l == ']')
3436 --paren_not_balanced;
3437 }
3438 l++;
3439 }
3440 if (l != token_start)
3441 { /* Yes, we've read in another operand. */
3442 unsigned int operand_ok;
3443 this_operand = i.operands++;
7d5e4556 3444 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3445 if (i.operands > MAX_OPERANDS)
3446 {
3447 as_bad (_("spurious operands; (%d operands/instruction max)"),
3448 MAX_OPERANDS);
3449 return NULL;
3450 }
3451 /* Now parse operand adding info to 'i' as we go along. */
3452 END_STRING_AND_SAVE (l);
3453
3454 if (intel_syntax)
3455 operand_ok =
3456 i386_intel_operand (token_start,
3457 intel_float_operand (mnemonic));
3458 else
a7619375 3459 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3460
3461 RESTORE_END_STRING (l);
3462 if (!operand_ok)
3463 return NULL;
3464 }
3465 else
3466 {
3467 if (expecting_operand)
3468 {
3469 expecting_operand_after_comma:
3470 as_bad (_("expecting operand after ','; got nothing"));
3471 return NULL;
3472 }
3473 if (*l == ',')
3474 {
3475 as_bad (_("expecting operand before ','; got nothing"));
3476 return NULL;
3477 }
3478 }
7f3f1ea2 3479
29b0f896
AM		 3480 /* Now *l must be either ',' or END_OF_INSN. */
3481 if (*l == ',')
3482 {
3483 if (*++l == END_OF_INSN)
3484 {
3485 /* Just skip it, if it's \n complain. */
3486 goto expecting_operand_after_comma;
3487 }
3488 expecting_operand = 1;
3489 }
3490 }
3491 return l;
3492}
7f3f1ea2 3493
050dfa73 3494static void
4d456e3d 3495swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3496{
3497 union i386_op temp_op;
40fb9820 3498 i386_operand_type temp_type;
050dfa73 3499 enum bfd_reloc_code_real temp_reloc;
4eed87de 3500
050dfa73
MM		 3501 temp_type = i.types[xchg2];
3502 i.types[xchg2] = i.types[xchg1];
3503 i.types[xchg1] = temp_type;
3504 temp_op = i.op[xchg2];
3505 i.op[xchg2] = i.op[xchg1];
3506 i.op[xchg1] = temp_op;
3507 temp_reloc = i.reloc[xchg2];
3508 i.reloc[xchg2] = i.reloc[xchg1];
3509 i.reloc[xchg1] = temp_reloc;
3510}
3511
29b0f896 3512static void
e3bb37b5 3513swap_operands (void)
29b0f896 3514{
b7c61d9a 3515 switch (i.operands)
050dfa73 3516 {
c0f3af97 3517 case 5:
b7c61d9a 3518 case 4:
4d456e3d 3519 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3520 case 3:
3521 case 2:
4d456e3d 3522 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3523 break;
3524 default:
3525 abort ();
29b0f896 3526 }
29b0f896
AM		 3527
3528 if (i.mem_operands == 2)
3529 {
3530 const seg_entry *temp_seg;
3531 temp_seg = i.seg[0];
3532 i.seg[0] = i.seg[1];
3533 i.seg[1] = temp_seg;
3534 }
3535}
252b5132 3536
29b0f896
AM		 3537/* Try to ensure constant immediates are represented in the smallest
3538 opcode possible. */
3539static void
e3bb37b5 3540optimize_imm (void)
29b0f896
AM		 3541{
3542 char guess_suffix = 0;
3543 int op;
252b5132 3544
29b0f896
AM		 3545 if (i.suffix)
3546 guess_suffix = i.suffix;
3547 else if (i.reg_operands)
3548 {
3549 /* Figure out a suffix from the last register operand specified.
3550 We can't do this properly yet, ie. excluding InOutPortReg,
3551 but the following works for instructions with immediates.
3552 In any case, we can't set i.suffix yet. */
3553 for (op = i.operands; --op >= 0;)
40fb9820 3554 if (i.types[op].bitfield.reg8)
7ab9ffdd 3555 {
40fb9820
L		 3556 guess_suffix = BYTE_MNEM_SUFFIX;
3557 break;
3558 }
3559 else if (i.types[op].bitfield.reg16)
252b5132 3560 {
40fb9820
L		 3561 guess_suffix = WORD_MNEM_SUFFIX;
3562 break;
3563 }
3564 else if (i.types[op].bitfield.reg32)
3565 {
3566 guess_suffix = LONG_MNEM_SUFFIX;
3567 break;
3568 }
3569 else if (i.types[op].bitfield.reg64)
3570 {
3571 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3572 break;
252b5132 3573 }
29b0f896
AM		 3574 }
3575 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3576 guess_suffix = WORD_MNEM_SUFFIX;
3577
3578 for (op = i.operands; --op >= 0;)
40fb9820 3579 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3580 {
3581 switch (i.op[op].imms->X_op)
252b5132 3582 {
29b0f896
AM		 3583 case O_constant:
3584 /* If a suffix is given, this operand may be shortened. */
3585 switch (guess_suffix)
252b5132 3586 {
29b0f896 3587 case LONG_MNEM_SUFFIX:
40fb9820
L		 3588 i.types[op].bitfield.imm32 = 1;
3589 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3590 break;
3591 case WORD_MNEM_SUFFIX:
40fb9820
L		 3592 i.types[op].bitfield.imm16 = 1;
3593 i.types[op].bitfield.imm32 = 1;
3594 i.types[op].bitfield.imm32s = 1;
3595 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3596 break;
3597 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3598 i.types[op].bitfield.imm8 = 1;
3599 i.types[op].bitfield.imm8s = 1;
3600 i.types[op].bitfield.imm16 = 1;
3601 i.types[op].bitfield.imm32 = 1;
3602 i.types[op].bitfield.imm32s = 1;
3603 i.types[op].bitfield.imm64 = 1;
29b0f896 3604 break;
252b5132 3605 }
252b5132 3606
29b0f896
AM		 3607 /* If this operand is at most 16 bits, convert it
3608 to a signed 16 bit number before trying to see
3609 whether it will fit in an even smaller size.
3610 This allows a 16-bit operand such as $0xffe0 to
3611 be recognised as within Imm8S range. */
40fb9820 3612 if ((i.types[op].bitfield.imm16)
29b0f896 3613 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3614 {
29b0f896
AM		 3615 i.op[op].imms->X_add_number =
3616 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3617 }
40fb9820 3618 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3619 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3620 == 0))
3621 {
3622 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3623 ^ ((offsetT) 1 << 31))
3624 - ((offsetT) 1 << 31));
3625 }
40fb9820 3626 i.types[op]
c6fb90c8
L		 3627 = operand_type_or (i.types[op],
3628 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3629
29b0f896
AM		 3630 /* We must avoid matching of Imm32 templates when 64bit
3631 only immediate is available. */
3632 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3633 i.types[op].bitfield.imm32 = 0;
29b0f896 3634 break;
252b5132 3635
29b0f896
AM		 3636 case O_absent:
3637 case O_register:
3638 abort ();
3639
3640 /* Symbols and expressions. */
3641 default:
9cd96992
JB		 3642 /* Convert symbolic operand to proper sizes for matching, but don't
3643 prevent matching a set of insns that only supports sizes other
3644 than those matching the insn suffix. */
3645 {
40fb9820 3646 i386_operand_type mask, allowed;
d3ce72d0 3647 const insn_template *t;
9cd96992 3648
0dfbf9d7
L		 3649 operand_type_set (&mask, 0);
3650 operand_type_set (&allowed, 0);
40fb9820 3651
4eed87de
AM		 3652 for (t = current_templates->start;
3653 t < current_templates->end;
3654 ++t)
c6fb90c8
L		 3655 allowed = operand_type_or (allowed,
3656 t->operand_types[op]);
9cd96992
JB		 3657 switch (guess_suffix)
3658 {
3659 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3660 mask.bitfield.imm64 = 1;
3661 mask.bitfield.imm32s = 1;
9cd96992
JB		 3662 break;
3663 case LONG_MNEM_SUFFIX:
40fb9820 3664 mask.bitfield.imm32 = 1;
9cd96992
JB		 3665 break;
3666 case WORD_MNEM_SUFFIX:
40fb9820 3667 mask.bitfield.imm16 = 1;
9cd96992
JB		 3668 break;
3669 case BYTE_MNEM_SUFFIX:
40fb9820 3670 mask.bitfield.imm8 = 1;
9cd96992
JB		 3671 break;
3672 default:
9cd96992
JB		 3673 break;
3674 }
c6fb90c8 3675 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3676 if (!operand_type_all_zero (&allowed))
c6fb90c8 3677 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3678 }
29b0f896 3679 break;
252b5132 3680 }
29b0f896
AM		 3681 }
3682}
47926f60 3683
29b0f896
AM		 3684/* Try to use the smallest displacement type too. */
3685static void
e3bb37b5 3686optimize_disp (void)
29b0f896
AM		 3687{
3688 int op;
3e73aa7c 3689
29b0f896 3690 for (op = i.operands; --op >= 0;)
40fb9820 3691 if (operand_type_check (i.types[op], disp))
252b5132 3692 {
b300c311 3693 if (i.op[op].disps->X_op == O_constant)
252b5132 3694 {
91d6fa6a 3695 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3696
40fb9820 3697 if (i.types[op].bitfield.disp16
91d6fa6a 3698 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3699 {
3700 /* If this operand is at most 16 bits, convert
3701 to a signed 16 bit number and don't use 64bit
3702 displacement. */
91d6fa6a 3703 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3704 i.types[op].bitfield.disp64 = 0;
b300c311 3705 }
40fb9820 3706 if (i.types[op].bitfield.disp32
91d6fa6a 3707 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3708 {
3709 /* If this operand is at most 32 bits, convert
3710 to a signed 32 bit number and don't use 64bit
3711 displacement. */
91d6fa6a
NC		 3712 op_disp &= (((offsetT) 2 << 31) - 1);
3713 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3714 i.types[op].bitfield.disp64 = 0;
b300c311 3715 }
91d6fa6a 3716 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3717 {
40fb9820
L		 3718 i.types[op].bitfield.disp8 = 0;
3719 i.types[op].bitfield.disp16 = 0;
3720 i.types[op].bitfield.disp32 = 0;
3721 i.types[op].bitfield.disp32s = 0;
3722 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3723 i.op[op].disps = 0;
3724 i.disp_operands--;
3725 }
3726 else if (flag_code == CODE_64BIT)
3727 {
91d6fa6a 3728 if (fits_in_signed_long (op_disp))
28a9d8f5 3729 {
40fb9820
L		 3730 i.types[op].bitfield.disp64 = 0;
3731 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3732 }
0e1147d9 3733 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3734 && fits_in_unsigned_long (op_disp))
40fb9820 3735 i.types[op].bitfield.disp32 = 1;
b300c311 3736 }
40fb9820
L		 3737 if ((i.types[op].bitfield.disp32
3738 || i.types[op].bitfield.disp32s
3739 || i.types[op].bitfield.disp16)
91d6fa6a 3740 && fits_in_signed_byte (op_disp))
40fb9820 3741 i.types[op].bitfield.disp8 = 1;
252b5132 3742 }
67a4f2b7
AO		 3743 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3744 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3745 {
3746 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3747 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3748 i.types[op].bitfield.disp8 = 0;
3749 i.types[op].bitfield.disp16 = 0;
3750 i.types[op].bitfield.disp32 = 0;
3751 i.types[op].bitfield.disp32s = 0;
3752 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3753 }
3754 else
b300c311 3755 /* We only support 64bit displacement on constants. */
40fb9820 3756 i.types[op].bitfield.disp64 = 0;
252b5132 3757 }
29b0f896
AM		 3758}
3759
a683cc34
SP		 3760/* Check if operands are valid for the instrucrtion. Update VEX
3761 operand types. */
3762
3763static int
3764VEX_check_operands (const insn_template *t)
3765{
3766 if (!t->opcode_modifier.vex)
3767 return 0;
3768
3769 /* Only check VEX_Imm4, which must be the first operand. */
3770 if (t->operand_types[0].bitfield.vec_imm4)
3771 {
3772 if (i.op[0].imms->X_op != O_constant
3773 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3774 {
a65babc9 3775 i.error = bad_imm4;
891edac4
L		 3776 return 1;
3777 }
a683cc34
SP		 3778
3779 /* Turn off Imm8 so that update_imm won't complain. */
3780 i.types[0] = vec_imm4;
3781 }
3782
3783 return 0;
3784}
3785
d3ce72d0 3786static const insn_template *
e3bb37b5 3787match_template (void)
29b0f896
AM		 3788{
3789 /* Points to template once we've found it. */
d3ce72d0 3790 const insn_template *t;
40fb9820 3791 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3792 i386_operand_type overlap4;
29b0f896 3793 unsigned int found_reverse_match;
40fb9820
L		 3794 i386_opcode_modifier suffix_check;
3795 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3796 int addr_prefix_disp;
a5c311ca 3797 unsigned int j;
3629bb00 3798 unsigned int found_cpu_match;
45664ddb 3799 unsigned int check_register;
29b0f896 3800
c0f3af97
L		 3801#if MAX_OPERANDS != 5
3802# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3803#endif
3804
29b0f896 3805 found_reverse_match = 0;
539e75ad 3806 addr_prefix_disp = -1;
40fb9820
L		 3807
3808 memset (&suffix_check, 0, sizeof (suffix_check));
3809 if (i.suffix == BYTE_MNEM_SUFFIX)
3810 suffix_check.no_bsuf = 1;
3811 else if (i.suffix == WORD_MNEM_SUFFIX)
3812 suffix_check.no_wsuf = 1;
3813 else if (i.suffix == SHORT_MNEM_SUFFIX)
3814 suffix_check.no_ssuf = 1;
3815 else if (i.suffix == LONG_MNEM_SUFFIX)
3816 suffix_check.no_lsuf = 1;
3817 else if (i.suffix == QWORD_MNEM_SUFFIX)
3818 suffix_check.no_qsuf = 1;
3819 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3820 suffix_check.no_ldsuf = 1;
29b0f896 3821
45aa61fe 3822 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3823 {
539e75ad
L		 3824 addr_prefix_disp = -1;
3825
29b0f896 3826 /* Must have right number of operands. */
a65babc9 3827 i.error = number_of_operands_mismatch;
29b0f896
AM		 3828 if (i.operands != t->operands)
3829 continue;
3830
50aecf8c 3831 /* Check processor support. */
a65babc9 3832 i.error = unsupported;
c0f3af97
L		 3833 found_cpu_match = (cpu_flags_match (t)
3834 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3835 if (!found_cpu_match)
3836 continue;
3837
e1d4d893 3838 /* Check old gcc support. */
a65babc9 3839 i.error = old_gcc_only;
e1d4d893
L		 3840 if (!old_gcc && t->opcode_modifier.oldgcc)
3841 continue;
3842
3843 /* Check AT&T mnemonic. */
a65babc9 3844 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3845 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3846 continue;
3847
891edac4 3848 /* Check AT&T/Intel syntax. */
a65babc9 3849 i.error = unsupported_syntax;
5c07affc
L		 3850 if ((intel_syntax && t->opcode_modifier.attsyntax)
3851 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3852 continue;
3853
20592a94 3854 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3855 i.error = invalid_instruction_suffix;
567e4e96
L		 3856 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3857 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3858 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3859 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3860 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3861 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3862 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3863 continue;
3864
5c07affc 3865 if (!operand_size_match (t))
7d5e4556 3866 continue;
539e75ad 3867
5c07affc
L		 3868 for (j = 0; j < MAX_OPERANDS; j++)
3869 operand_types[j] = t->operand_types[j];
3870
45aa61fe
AM		 3871 /* In general, don't allow 64-bit operands in 32-bit mode. */
3872 if (i.suffix == QWORD_MNEM_SUFFIX
3873 && flag_code != CODE_64BIT
3874 && (intel_syntax
40fb9820 3875 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3876 && !intel_float_operand (t->name))
3877 : intel_float_operand (t->name) != 2)
40fb9820 3878 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3879 && !operand_types[0].bitfield.regxmm
3880 && !operand_types[0].bitfield.regymm)
40fb9820 3881 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3882 && !!operand_types[t->operands > 1].bitfield.regxmm
3883 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3884 && (t->base_opcode != 0x0fc7
3885 || t->extension_opcode != 1 /* cmpxchg8b */))
3886 continue;
3887
192dc9c6
JB		 3888 /* In general, don't allow 32-bit operands on pre-386. */
3889 else if (i.suffix == LONG_MNEM_SUFFIX
3890 && !cpu_arch_flags.bitfield.cpui386
3891 && (intel_syntax
3892 ? (!t->opcode_modifier.ignoresize
3893 && !intel_float_operand (t->name))
3894 : intel_float_operand (t->name) != 2)
3895 && ((!operand_types[0].bitfield.regmmx
3896 && !operand_types[0].bitfield.regxmm)
3897 || (!operand_types[t->operands > 1].bitfield.regmmx
3898 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3899 continue;
3900
29b0f896 3901 /* Do not verify operands when there are none. */
50aecf8c 3902 else
29b0f896 3903 {
c6fb90c8 3904 if (!t->operands)
2dbab7d5
L		 3905 /* We've found a match; break out of loop. */
3906 break;
29b0f896 3907 }
252b5132 3908
539e75ad
L		 3909 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3910 into Disp32/Disp16/Disp32 operand. */
3911 if (i.prefix[ADDR_PREFIX] != 0)
3912 {
40fb9820 3913 /* There should be only one Disp operand. */
539e75ad
L		 3914 switch (flag_code)
3915 {
3916 case CODE_16BIT:
40fb9820
L		 3917 for (j = 0; j < MAX_OPERANDS; j++)
3918 {
3919 if (operand_types[j].bitfield.disp16)
3920 {
3921 addr_prefix_disp = j;
3922 operand_types[j].bitfield.disp32 = 1;
3923 operand_types[j].bitfield.disp16 = 0;
3924 break;
3925 }
3926 }
539e75ad
L		 3927 break;
3928 case CODE_32BIT:
40fb9820
L		 3929 for (j = 0; j < MAX_OPERANDS; j++)
3930 {
3931 if (operand_types[j].bitfield.disp32)
3932 {
3933 addr_prefix_disp = j;
3934 operand_types[j].bitfield.disp32 = 0;
3935 operand_types[j].bitfield.disp16 = 1;
3936 break;
3937 }
3938 }
539e75ad
L		 3939 break;
3940 case CODE_64BIT:
40fb9820
L		 3941 for (j = 0; j < MAX_OPERANDS; j++)
3942 {
3943 if (operand_types[j].bitfield.disp64)
3944 {
3945 addr_prefix_disp = j;
3946 operand_types[j].bitfield.disp64 = 0;
3947 operand_types[j].bitfield.disp32 = 1;
3948 break;
3949 }
3950 }
539e75ad
L		 3951 break;
3952 }
539e75ad
L		 3953 }
3954
45664ddb
L		 3955 /* We check register size only if size of operands can be
3956 encoded the canonical way. */
3957 check_register = t->opcode_modifier.w;
c6fb90c8 3958 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3959 switch (t->operands)
3960 {
3961 case 1:
40fb9820 3962 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3963 continue;
3964 break;
3965 case 2:
8b38ad71
L		 3966 /* xchg %eax, %eax is a special case. It is an aliase for nop
3967 only in 32bit mode and we can use opcode 0x90. In 64bit
3968 mode, we can't use 0x90 for xchg %eax, %eax since it should
3969 zero-extend %eax to %rax. */
3970 if (flag_code == CODE_64BIT
3971 && t->base_opcode == 0x90
0dfbf9d7
L		 3972 && operand_type_equal (&i.types [0], &acc32)
3973 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3974 continue;
b6169b20
L		 3975 if (i.swap_operand)
3976 {
3977 /* If we swap operand in encoding, we either match
3978 the next one or reverse direction of operands. */
3979 if (t->opcode_modifier.s)
3980 continue;
3981 else if (t->opcode_modifier.d)
3982 goto check_reverse;
3983 }
3984
29b0f896 3985 case 3:
fa99fab2
L		 3986 /* If we swap operand in encoding, we match the next one. */
3987 if (i.swap_operand && t->opcode_modifier.s)
3988 continue;
f48ff2ae 3989 case 4:
c0f3af97 3990 case 5:
c6fb90c8 3991 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3992 if (!operand_type_match (overlap0, i.types[0])
3993 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3994 || (check_register
3995 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3996 operand_types[0],
3997 overlap1, i.types[1],
3998 operand_types[1])))
29b0f896
AM		 3999 {
4000 /* Check if other direction is valid ... */
40fb9820 4001 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4002 continue;
4003
b6169b20 4004check_reverse:
29b0f896 4005 /* Try reversing direction of operands. */
c6fb90c8
L		 4006 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4007 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4008 if (!operand_type_match (overlap0, i.types[0])
4009 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4010 || (check_register
4011 && !operand_type_register_match (overlap0,
4012 i.types[0],
4013 operand_types[1],
4014 overlap1,
4015 i.types[1],
4016 operand_types[0])))
29b0f896
AM		 4017 {
4018 /* Does not match either direction. */
4019 continue;
4020 }
4021 /* found_reverse_match holds which of D or FloatDR
4022 we've found. */
40fb9820 4023 if (t->opcode_modifier.d)
8a2ed489 4024 found_reverse_match = Opcode_D;
40fb9820 4025 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4026 found_reverse_match = Opcode_FloatD;
4027 else
4028 found_reverse_match = 0;
40fb9820 4029 if (t->opcode_modifier.floatr)
8a2ed489 4030 found_reverse_match |= Opcode_FloatR;
29b0f896 4031 }
f48ff2ae 4032 else
29b0f896 4033 {
f48ff2ae 4034 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4035 switch (t->operands)
4036 {
c0f3af97
L		 4037 case 5:
4038 overlap4 = operand_type_and (i.types[4],
4039 operand_types[4]);
d1cbb4db 4040 case 4:
c6fb90c8
L		 4041 overlap3 = operand_type_and (i.types[3],
4042 operand_types[3]);
d1cbb4db 4043 case 3:
c6fb90c8
L		 4044 overlap2 = operand_type_and (i.types[2],
4045 operand_types[2]);
d1cbb4db
L		 4046 break;
4047 }
29b0f896 4048
f48ff2ae
L		 4049 switch (t->operands)
4050 {
c0f3af97
L		 4051 case 5:
4052 if (!operand_type_match (overlap4, i.types[4])
4053 || !operand_type_register_match (overlap3,
4054 i.types[3],
4055 operand_types[3],
4056 overlap4,
4057 i.types[4],
4058 operand_types[4]))
4059 continue;
f48ff2ae 4060 case 4:
40fb9820 4061 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4062 || (check_register
4063 && !operand_type_register_match (overlap2,
4064 i.types[2],
4065 operand_types[2],
4066 overlap3,
4067 i.types[3],
4068 operand_types[3])))
f48ff2ae
L		 4069 continue;
4070 case 3:
4071 /* Here we make use of the fact that there are no
4072 reverse match 3 operand instructions, and all 3
4073 operand instructions only need to be checked for
4074 register consistency between operands 2 and 3. */
40fb9820 4075 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4076 || (check_register
4077 && !operand_type_register_match (overlap1,
4078 i.types[1],
4079 operand_types[1],
4080 overlap2,
4081 i.types[2],
4082 operand_types[2])))
f48ff2ae
L		 4083 continue;
4084 break;
4085 }
29b0f896 4086 }
f48ff2ae 4087 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4088 slip through to break. */
4089 }
3629bb00 4090 if (!found_cpu_match)
29b0f896
AM		 4091 {
4092 found_reverse_match = 0;
4093 continue;
4094 }
c0f3af97 4095
a683cc34
SP		 4096 /* Check if VEX operands are valid. */
4097 if (VEX_check_operands (t))
4098 continue;
4099
29b0f896
AM		 4100 /* We've found a match; break out of loop. */
4101 break;
4102 }
4103
4104 if (t == current_templates->end)
4105 {
4106 /* We found no match. */
a65babc9
L		 4107 const char *err_msg;
4108 switch (i.error)
4109 {
4110 default:
4111 abort ();
86e026a4 4112 case operand_size_mismatch:
a65babc9
L		 4113 err_msg = _("operand size mismatch");
4114 break;
4115 case operand_type_mismatch:
4116 err_msg = _("operand type mismatch");
4117 break;
4118 case register_type_mismatch:
4119 err_msg = _("register type mismatch");
4120 break;
4121 case number_of_operands_mismatch:
4122 err_msg = _("number of operands mismatch");
4123 break;
4124 case invalid_instruction_suffix:
4125 err_msg = _("invalid instruction suffix");
4126 break;
4127 case bad_imm4:
4128 err_msg = _("Imm4 isn't the first operand");
4129 break;
4130 case old_gcc_only:
4131 err_msg = _("only supported with old gcc");
4132 break;
4133 case unsupported_with_intel_mnemonic:
4134 err_msg = _("unsupported with Intel mnemonic");
4135 break;
4136 case unsupported_syntax:
4137 err_msg = _("unsupported syntax");
4138 break;
4139 case unsupported:
4140 err_msg = _("unsupported");
4141 break;
4142 }
4143 as_bad (_("%s for `%s'"), err_msg,
891edac4 4144 current_templates->start->name);
fa99fab2 4145 return NULL;
29b0f896 4146 }
252b5132 4147
29b0f896
AM		 4148 if (!quiet_warnings)
4149 {
4150 if (!intel_syntax
40fb9820
L		 4151 && (i.types[0].bitfield.jumpabsolute
4152 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4153 {
4154 as_warn (_("indirect %s without `*'"), t->name);
4155 }
4156
40fb9820
L		 4157 if (t->opcode_modifier.isprefix
4158 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4159 {
4160 /* Warn them that a data or address size prefix doesn't
4161 affect assembly of the next line of code. */
4162 as_warn (_("stand-alone `%s' prefix"), t->name);
4163 }
4164 }
4165
4166 /* Copy the template we found. */
4167 i.tm = *t;
539e75ad
L		 4168
4169 if (addr_prefix_disp != -1)
4170 i.tm.operand_types[addr_prefix_disp]
4171 = operand_types[addr_prefix_disp];
4172
29b0f896
AM		 4173 if (found_reverse_match)
4174 {
4175 /* If we found a reverse match we must alter the opcode
4176 direction bit. found_reverse_match holds bits to change
4177 (different for int & float insns). */
4178
4179 i.tm.base_opcode ^= found_reverse_match;
4180
539e75ad
L		 4181 i.tm.operand_types[0] = operand_types[1];
4182 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4183 }
4184
fa99fab2 4185 return t;
29b0f896
AM		 4186}
4187
4188static int
e3bb37b5 4189check_string (void)
29b0f896 4190{
40fb9820
L		 4191 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4192 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4193 {
4194 if (i.seg[0] != NULL && i.seg[0] != &es)
4195 {
a87af027 4196 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4197 i.tm.name,
a87af027
JB		 4198 mem_op + 1,
4199 register_prefix);
29b0f896
AM		 4200 return 0;
4201 }
4202 /* There's only ever one segment override allowed per instruction.
4203 This instruction possibly has a legal segment override on the
4204 second operand, so copy the segment to where non-string
4205 instructions store it, allowing common code. */
4206 i.seg[0] = i.seg[1];
4207 }
40fb9820 4208 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4209 {
4210 if (i.seg[1] != NULL && i.seg[1] != &es)
4211 {
a87af027 4212 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4213 i.tm.name,
a87af027
JB		 4214 mem_op + 2,
4215 register_prefix);
29b0f896
AM		 4216 return 0;
4217 }
4218 }
4219 return 1;
4220}
4221
4222static int
543613e9 4223process_suffix (void)
29b0f896
AM		 4224{
4225 /* If matched instruction specifies an explicit instruction mnemonic
4226 suffix, use it. */
40fb9820
L		 4227 if (i.tm.opcode_modifier.size16)
4228 i.suffix = WORD_MNEM_SUFFIX;
4229 else if (i.tm.opcode_modifier.size32)
4230 i.suffix = LONG_MNEM_SUFFIX;
4231 else if (i.tm.opcode_modifier.size64)
4232 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4233 else if (i.reg_operands)
4234 {
4235 /* If there's no instruction mnemonic suffix we try to invent one
4236 based on register operands. */
4237 if (!i.suffix)
4238 {
4239 /* We take i.suffix from the last register operand specified,
4240 Destination register type is more significant than source
381d071f
L		 4241 register type. crc32 in SSE4.2 prefers source register
4242 type. */
4243 if (i.tm.base_opcode == 0xf20f38f1)
4244 {
40fb9820
L		 4245 if (i.types[0].bitfield.reg16)
4246 i.suffix = WORD_MNEM_SUFFIX;
4247 else if (i.types[0].bitfield.reg32)
4248 i.suffix = LONG_MNEM_SUFFIX;
4249 else if (i.types[0].bitfield.reg64)
4250 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4251 }
9344ff29 4252 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4253 {
40fb9820 4254 if (i.types[0].bitfield.reg8)
20592a94
L		 4255 i.suffix = BYTE_MNEM_SUFFIX;
4256 }
381d071f
L		 4257
4258 if (!i.suffix)
4259 {
4260 int op;
4261
20592a94
L		 4262 if (i.tm.base_opcode == 0xf20f38f1
4263 || i.tm.base_opcode == 0xf20f38f0)
4264 {
4265 /* We have to know the operand size for crc32. */
4266 as_bad (_("ambiguous memory operand size for `%s`"),
4267 i.tm.name);
4268 return 0;
4269 }
4270
381d071f 4271 for (op = i.operands; --op >= 0;)
40fb9820 4272 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4273 {
40fb9820
L		 4274 if (i.types[op].bitfield.reg8)
4275 {
4276 i.suffix = BYTE_MNEM_SUFFIX;
4277 break;
4278 }
4279 else if (i.types[op].bitfield.reg16)
4280 {
4281 i.suffix = WORD_MNEM_SUFFIX;
4282 break;
4283 }
4284 else if (i.types[op].bitfield.reg32)
4285 {
4286 i.suffix = LONG_MNEM_SUFFIX;
4287 break;
4288 }
4289 else if (i.types[op].bitfield.reg64)
4290 {
4291 i.suffix = QWORD_MNEM_SUFFIX;
4292 break;
4293 }
381d071f
L		 4294 }
4295 }
29b0f896
AM		 4296 }
4297 else if (i.suffix == BYTE_MNEM_SUFFIX)
4298 {
2eb952a4
L		 4299 if (intel_syntax
4300 && i.tm.opcode_modifier.ignoresize
4301 && i.tm.opcode_modifier.no_bsuf)
4302 i.suffix = 0;
4303 else if (!check_byte_reg ())
29b0f896
AM		 4304 return 0;
4305 }
4306 else if (i.suffix == LONG_MNEM_SUFFIX)
4307 {
2eb952a4
L		 4308 if (intel_syntax
4309 && i.tm.opcode_modifier.ignoresize
4310 && i.tm.opcode_modifier.no_lsuf)
4311 i.suffix = 0;
4312 else if (!check_long_reg ())
29b0f896
AM		 4313 return 0;
4314 }
4315 else if (i.suffix == QWORD_MNEM_SUFFIX)
4316 {
955e1e6a
L		 4317 if (intel_syntax
4318 && i.tm.opcode_modifier.ignoresize
4319 && i.tm.opcode_modifier.no_qsuf)
4320 i.suffix = 0;
4321 else if (!check_qword_reg ())
29b0f896
AM		 4322 return 0;
4323 }
4324 else if (i.suffix == WORD_MNEM_SUFFIX)
4325 {
2eb952a4
L		 4326 if (intel_syntax
4327 && i.tm.opcode_modifier.ignoresize
4328 && i.tm.opcode_modifier.no_wsuf)
4329 i.suffix = 0;
4330 else if (!check_word_reg ())
29b0f896
AM		 4331 return 0;
4332 }
c0f3af97
L		 4333 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4334 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4335 {
c0f3af97 4336 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4337 should check if it is a valid suffix. */
4338 }
40fb9820 4339 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4340 /* Do nothing if the instruction is going to ignore the prefix. */
4341 ;
4342 else
4343 abort ();
4344 }
40fb9820 4345 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4346 && !i.suffix
4347 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4348 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4349 {
4350 i.suffix = stackop_size;
4351 }
9306ca4a
JB		 4352 else if (intel_syntax
4353 && !i.suffix
40fb9820
L		 4354 && (i.tm.operand_types[0].bitfield.jumpabsolute
4355 || i.tm.opcode_modifier.jumpbyte
4356 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4357 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4358 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4359 {
4360 switch (flag_code)
4361 {
4362 case CODE_64BIT:
40fb9820 4363 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4364 {
4365 i.suffix = QWORD_MNEM_SUFFIX;
4366 break;
4367 }
4368 case CODE_32BIT:
40fb9820 4369 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4370 i.suffix = LONG_MNEM_SUFFIX;
4371 break;
4372 case CODE_16BIT:
40fb9820 4373 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4374 i.suffix = WORD_MNEM_SUFFIX;
4375 break;
4376 }
4377 }
252b5132 4378
9306ca4a 4379 if (!i.suffix)
29b0f896 4380 {
9306ca4a
JB		 4381 if (!intel_syntax)
4382 {
40fb9820 4383 if (i.tm.opcode_modifier.w)
9306ca4a 4384 {
4eed87de
AM		 4385 as_bad (_("no instruction mnemonic suffix given and "
4386 "no register operands; can't size instruction"));
9306ca4a
JB		 4387 return 0;
4388 }
4389 }
4390 else
4391 {
40fb9820 4392 unsigned int suffixes;
7ab9ffdd 4393
40fb9820
L		 4394 suffixes = !i.tm.opcode_modifier.no_bsuf;
4395 if (!i.tm.opcode_modifier.no_wsuf)
4396 suffixes |= 1 << 1;
4397 if (!i.tm.opcode_modifier.no_lsuf)
4398 suffixes |= 1 << 2;
fc4adea1 4399 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4400 suffixes |= 1 << 3;
4401 if (!i.tm.opcode_modifier.no_ssuf)
4402 suffixes |= 1 << 4;
4403 if (!i.tm.opcode_modifier.no_qsuf)
4404 suffixes |= 1 << 5;
4405
4406 /* There are more than suffix matches. */
4407 if (i.tm.opcode_modifier.w
9306ca4a 4408 || ((suffixes & (suffixes - 1))
40fb9820
L		 4409 && !i.tm.opcode_modifier.defaultsize
4410 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4411 {
4412 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4413 return 0;
4414 }
4415 }
29b0f896 4416 }
252b5132 4417
9306ca4a
JB		 4418 /* Change the opcode based on the operand size given by i.suffix;
4419 We don't need to change things for byte insns. */
4420
582d5edd
L		 4421 if (i.suffix
4422 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4423 && i.suffix != XMMWORD_MNEM_SUFFIX
4424 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4425 {
4426 /* It's not a byte, select word/dword operation. */
40fb9820 4427 if (i.tm.opcode_modifier.w)
29b0f896 4428 {
40fb9820 4429 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4430 i.tm.base_opcode |= 8;
4431 else
4432 i.tm.base_opcode |= 1;
4433 }
0f3f3d8b 4434
29b0f896
AM		 4435 /* Now select between word & dword operations via the operand
4436 size prefix, except for instructions that will ignore this
4437 prefix anyway. */
ca61edf2 4438 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4439 {
ca61edf2
L		 4440 /* The address size override prefix changes the size of the
4441 first operand. */
40fb9820
L		 4442 if ((flag_code == CODE_32BIT
4443 && i.op->regs[0].reg_type.bitfield.reg16)
4444 || (flag_code != CODE_32BIT
4445 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4446 if (!add_prefix (ADDR_PREFIX_OPCODE))
4447 return 0;
4448 }
4449 else if (i.suffix != QWORD_MNEM_SUFFIX
4450 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4451 && !i.tm.opcode_modifier.ignoresize
4452 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4453 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4454 || (flag_code == CODE_64BIT
40fb9820 4455 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4456 {
4457 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4458
40fb9820 4459 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4460 prefix = ADDR_PREFIX_OPCODE;
252b5132 4461
29b0f896
AM		 4462 if (!add_prefix (prefix))
4463 return 0;
24eab124 4464 }
252b5132 4465
29b0f896
AM		 4466 /* Set mode64 for an operand. */
4467 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4468 && flag_code == CODE_64BIT
40fb9820 4469 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4470 {
4471 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4472 need rex64. cmpxchg8b is also a special case. */
4473 if (! (i.operands == 2
4474 && i.tm.base_opcode == 0x90
4475 && i.tm.extension_opcode == None
0dfbf9d7
L		 4476 && operand_type_equal (&i.types [0], &acc64)
4477 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4478 && ! (i.operands == 1
4479 && i.tm.base_opcode == 0xfc7
4480 && i.tm.extension_opcode == 1
40fb9820
L		 4481 && !operand_type_check (i.types [0], reg)
4482 && operand_type_check (i.types [0], anymem)))
f6bee062 4483 i.rex |= REX_W;
46e883c5 4484 }
3e73aa7c 4485
29b0f896
AM		 4486 /* Size floating point instruction. */
4487 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4488 if (i.tm.opcode_modifier.floatmf)
543613e9 4489 i.tm.base_opcode ^= 4;
29b0f896 4490 }
7ecd2f8b 4491
29b0f896
AM		 4492 return 1;
4493}
3e73aa7c 4494
29b0f896 4495static int
543613e9 4496check_byte_reg (void)
29b0f896
AM		 4497{
4498 int op;
543613e9 4499
29b0f896
AM		 4500 for (op = i.operands; --op >= 0;)
4501 {
4502 /* If this is an eight bit register, it's OK. If it's the 16 or
4503 32 bit version of an eight bit register, we will just use the
4504 low portion, and that's OK too. */
40fb9820 4505 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4506 continue;
4507
9344ff29
L		 4508 /* crc32 doesn't generate this warning. */
4509 if (i.tm.base_opcode == 0xf20f38f0)
4510 continue;
4511
40fb9820
L		 4512 if ((i.types[op].bitfield.reg16
4513 || i.types[op].bitfield.reg32
4514 || i.types[op].bitfield.reg64)
4515 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4516 {
4517 /* Prohibit these changes in the 64bit mode, since the
4518 lowering is more complicated. */
4519 if (flag_code == CODE_64BIT
40fb9820 4520 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4521 {
2ca3ace5
L		 4522 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4523 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4524 i.suffix);
4525 return 0;
4526 }
4527#if REGISTER_WARNINGS
4528 if (!quiet_warnings
40fb9820 4529 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4530 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4531 register_prefix,
40fb9820 4532 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4533 ? REGNAM_AL - REGNAM_AX
4534 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4535 register_prefix,
29b0f896
AM		 4536 i.op[op].regs->reg_name,
4537 i.suffix);
4538#endif
4539 continue;
4540 }
4541 /* Any other register is bad. */
40fb9820
L		 4542 if (i.types[op].bitfield.reg16
4543 || i.types[op].bitfield.reg32
4544 || i.types[op].bitfield.reg64
4545 || i.types[op].bitfield.regmmx
4546 || i.types[op].bitfield.regxmm
c0f3af97 4547 || i.types[op].bitfield.regymm
40fb9820
L		 4548 || i.types[op].bitfield.sreg2
4549 || i.types[op].bitfield.sreg3
4550 || i.types[op].bitfield.control
4551 || i.types[op].bitfield.debug
4552 || i.types[op].bitfield.test
4553 || i.types[op].bitfield.floatreg
4554 || i.types[op].bitfield.floatacc)
29b0f896 4555 {
a540244d
L		 4556 as_bad (_("`%s%s' not allowed with `%s%c'"),
4557 register_prefix,
29b0f896
AM		 4558 i.op[op].regs->reg_name,
4559 i.tm.name,
4560 i.suffix);
4561 return 0;
4562 }
4563 }
4564 return 1;
4565}
4566
4567static int
e3bb37b5 4568check_long_reg (void)
29b0f896
AM		 4569{
4570 int op;
4571
4572 for (op = i.operands; --op >= 0;)
4573 /* Reject eight bit registers, except where the template requires
4574 them. (eg. movzb) */
40fb9820
L		 4575 if (i.types[op].bitfield.reg8
4576 && (i.tm.operand_types[op].bitfield.reg16
4577 || i.tm.operand_types[op].bitfield.reg32
4578 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4579 {
a540244d
L		 4580 as_bad (_("`%s%s' not allowed with `%s%c'"),
4581 register_prefix,
29b0f896
AM		 4582 i.op[op].regs->reg_name,
4583 i.tm.name,
4584 i.suffix);
4585 return 0;
4586 }
4587 /* Warn if the e prefix on a general reg is missing. */
4588 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4589 && i.types[op].bitfield.reg16
4590 && (i.tm.operand_types[op].bitfield.reg32
4591 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4592 {
4593 /* Prohibit these changes in the 64bit mode, since the
4594 lowering is more complicated. */
4595 if (flag_code == CODE_64BIT)
252b5132 4596 {
2ca3ace5
L		 4597 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4598 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4599 i.suffix);
4600 return 0;
252b5132 4601 }
29b0f896
AM		 4602#if REGISTER_WARNINGS
4603 else
a540244d
L		 4604 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4605 register_prefix,
29b0f896 4606 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4607 register_prefix,
29b0f896
AM		 4608 i.op[op].regs->reg_name,
4609 i.suffix);
4610#endif
252b5132 4611 }
29b0f896 4612 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4613 else if (i.types[op].bitfield.reg64
4614 && (i.tm.operand_types[op].bitfield.reg32
4615 || i.tm.operand_types[op].bitfield.acc))
252b5132 4616 {
34828aad 4617 if (intel_syntax
ca61edf2 4618 && i.tm.opcode_modifier.toqword
40fb9820 4619 && !i.types[0].bitfield.regxmm)
34828aad 4620 {
ca61edf2 4621 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4622 i.suffix = QWORD_MNEM_SUFFIX;
4623 }
4624 else
4625 {
4626 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4627 register_prefix, i.op[op].regs->reg_name,
4628 i.suffix);
4629 return 0;
4630 }
29b0f896
AM		 4631 }
4632 return 1;
4633}
252b5132 4634
29b0f896 4635static int
e3bb37b5 4636check_qword_reg (void)
29b0f896
AM		 4637{
4638 int op;
252b5132 4639
29b0f896
AM		 4640 for (op = i.operands; --op >= 0; )
4641 /* Reject eight bit registers, except where the template requires
4642 them. (eg. movzb) */
40fb9820
L		 4643 if (i.types[op].bitfield.reg8
4644 && (i.tm.operand_types[op].bitfield.reg16
4645 || i.tm.operand_types[op].bitfield.reg32
4646 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4647 {
a540244d
L		 4648 as_bad (_("`%s%s' not allowed with `%s%c'"),
4649 register_prefix,
29b0f896
AM		 4650 i.op[op].regs->reg_name,
4651 i.tm.name,
4652 i.suffix);
4653 return 0;
4654 }
4655 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4656 else if ((i.types[op].bitfield.reg16
4657 || i.types[op].bitfield.reg32)
4658 && (i.tm.operand_types[op].bitfield.reg32
4659 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4660 {
4661 /* Prohibit these changes in the 64bit mode, since the
4662 lowering is more complicated. */
34828aad 4663 if (intel_syntax
ca61edf2 4664 && i.tm.opcode_modifier.todword
40fb9820 4665 && !i.types[0].bitfield.regxmm)
34828aad 4666 {
ca61edf2 4667 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4668 i.suffix = LONG_MNEM_SUFFIX;
4669 }
4670 else
4671 {
4672 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4673 register_prefix, i.op[op].regs->reg_name,
4674 i.suffix);
4675 return 0;
4676 }
252b5132 4677 }
29b0f896
AM		 4678 return 1;
4679}
252b5132 4680
29b0f896 4681static int
e3bb37b5 4682check_word_reg (void)
29b0f896
AM		 4683{
4684 int op;
4685 for (op = i.operands; --op >= 0;)
4686 /* Reject eight bit registers, except where the template requires
4687 them. (eg. movzb) */
40fb9820
L		 4688 if (i.types[op].bitfield.reg8
4689 && (i.tm.operand_types[op].bitfield.reg16
4690 || i.tm.operand_types[op].bitfield.reg32
4691 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4692 {
a540244d
L		 4693 as_bad (_("`%s%s' not allowed with `%s%c'"),
4694 register_prefix,
29b0f896
AM		 4695 i.op[op].regs->reg_name,
4696 i.tm.name,
4697 i.suffix);
4698 return 0;
4699 }
4700 /* Warn if the e prefix on a general reg is present. */
4701 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4702 && i.types[op].bitfield.reg32
4703 && (i.tm.operand_types[op].bitfield.reg16
4704 || i.tm.operand_types[op].bitfield.acc))
252b5132 4705 {
29b0f896
AM		 4706 /* Prohibit these changes in the 64bit mode, since the
4707 lowering is more complicated. */
4708 if (flag_code == CODE_64BIT)
252b5132 4709 {
2ca3ace5
L		 4710 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4711 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4712 i.suffix);
4713 return 0;
252b5132 4714 }
29b0f896
AM		 4715 else
4716#if REGISTER_WARNINGS
a540244d
L		 4717 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4718 register_prefix,
29b0f896 4719 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4720 register_prefix,
29b0f896
AM		 4721 i.op[op].regs->reg_name,
4722 i.suffix);
4723#endif
4724 }
4725 return 1;
4726}
252b5132 4727
29b0f896 4728static int
40fb9820 4729update_imm (unsigned int j)
29b0f896 4730{
bc0844ae 4731 i386_operand_type overlap = i.types[j];
40fb9820
L		 4732 if ((overlap.bitfield.imm8
4733 || overlap.bitfield.imm8s
4734 || overlap.bitfield.imm16
4735 || overlap.bitfield.imm32
4736 || overlap.bitfield.imm32s
4737 || overlap.bitfield.imm64)
0dfbf9d7
L		 4738 && !operand_type_equal (&overlap, &imm8)
4739 && !operand_type_equal (&overlap, &imm8s)
4740 && !operand_type_equal (&overlap, &imm16)
4741 && !operand_type_equal (&overlap, &imm32)
4742 && !operand_type_equal (&overlap, &imm32s)
4743 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4744 {
4745 if (i.suffix)
4746 {
40fb9820
L		 4747 i386_operand_type temp;
4748
0dfbf9d7 4749 operand_type_set (&temp, 0);
7ab9ffdd 4750 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4751 {
4752 temp.bitfield.imm8 = overlap.bitfield.imm8;
4753 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4754 }
4755 else if (i.suffix == WORD_MNEM_SUFFIX)
4756 temp.bitfield.imm16 = overlap.bitfield.imm16;
4757 else if (i.suffix == QWORD_MNEM_SUFFIX)
4758 {
4759 temp.bitfield.imm64 = overlap.bitfield.imm64;
4760 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4761 }
4762 else
4763 temp.bitfield.imm32 = overlap.bitfield.imm32;
4764 overlap = temp;
29b0f896 4765 }
0dfbf9d7
L		 4766 else if (operand_type_equal (&overlap, &imm16_32_32s)
4767 || operand_type_equal (&overlap, &imm16_32)
4768 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4769 {
40fb9820 4770 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4771 overlap = imm16;
40fb9820 4772 else
65da13b5 4773 overlap = imm32s;
29b0f896 4774 }
0dfbf9d7
L		 4775 if (!operand_type_equal (&overlap, &imm8)
4776 && !operand_type_equal (&overlap, &imm8s)
4777 && !operand_type_equal (&overlap, &imm16)
4778 && !operand_type_equal (&overlap, &imm32)
4779 && !operand_type_equal (&overlap, &imm32s)
4780 && !operand_type_equal (&overlap, &imm64))
29b0f896 4781 {
4eed87de
AM		 4782 as_bad (_("no instruction mnemonic suffix given; "
4783 "can't determine immediate size"));
29b0f896
AM		 4784 return 0;
4785 }
4786 }
40fb9820 4787 i.types[j] = overlap;
29b0f896 4788
40fb9820
L		 4789 return 1;
4790}
4791
4792static int
4793finalize_imm (void)
4794{
bc0844ae 4795 unsigned int j, n;
29b0f896 4796
bc0844ae
L		 4797 /* Update the first 2 immediate operands. */
4798 n = i.operands > 2 ? 2 : i.operands;
4799 if (n)
4800 {
4801 for (j = 0; j < n; j++)
4802 if (update_imm (j) == 0)
4803 return 0;
40fb9820 4804
bc0844ae
L		 4805 /* The 3rd operand can't be immediate operand. */
4806 gas_assert (operand_type_check (i.types[2], imm) == 0);
4807 }
29b0f896
AM		 4808
4809 return 1;
4810}
4811
c0f3af97
L		 4812static int
4813bad_implicit_operand (int xmm)
4814{
91d6fa6a
NC		 4815 const char *ireg = xmm ? "xmm0" : "ymm0";
4816
c0f3af97
L		 4817 if (intel_syntax)
4818 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4819 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4820 else
4821 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4822 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4823 return 0;
4824}
4825
29b0f896 4826static int
e3bb37b5 4827process_operands (void)
29b0f896
AM		 4828{
4829 /* Default segment register this instruction will use for memory
4830 accesses. 0 means unknown. This is only for optimizing out
4831 unnecessary segment overrides. */
4832 const seg_entry *default_seg = 0;
4833
2426c15f 4834 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4835 {
91d6fa6a
NC		 4836 unsigned int dupl = i.operands;
4837 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4838 unsigned int j;
4839
c0f3af97 4840 /* The destination must be an xmm register. */
9c2799c2 4841 gas_assert (i.reg_operands
91d6fa6a 4842 && MAX_OPERANDS > dupl
7ab9ffdd 4843 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4844
4845 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4846 {
c0f3af97 4847 /* The first operand is implicit and must be xmm0. */
9c2799c2 4848 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4849 if (i.op[0].regs->reg_num != 0)
4850 return bad_implicit_operand (1);
4851
8cd7925b 4852 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4853 {
4854 /* Keep xmm0 for instructions with VEX prefix and 3
4855 sources. */
4856 goto duplicate;
4857 }
e2ec9d29 4858 else
c0f3af97
L		 4859 {
4860 /* We remove the first xmm0 and keep the number of
4861 operands unchanged, which in fact duplicates the
4862 destination. */
4863 for (j = 1; j < i.operands; j++)
4864 {
4865 i.op[j - 1] = i.op[j];
4866 i.types[j - 1] = i.types[j];
4867 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4868 }
4869 }
4870 }
4871 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4872 {
91d6fa6a 4873 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4874 && (i.tm.opcode_modifier.vexsources
4875 == VEX3SOURCES));
c0f3af97
L		 4876
4877 /* Add the implicit xmm0 for instructions with VEX prefix
4878 and 3 sources. */
4879 for (j = i.operands; j > 0; j--)
4880 {
4881 i.op[j] = i.op[j - 1];
4882 i.types[j] = i.types[j - 1];
4883 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4884 }
4885 i.op[0].regs
4886 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4887 i.types[0] = regxmm;
c0f3af97
L		 4888 i.tm.operand_types[0] = regxmm;
4889
4890 i.operands += 2;
4891 i.reg_operands += 2;
4892 i.tm.operands += 2;
4893
91d6fa6a 4894 dupl++;
c0f3af97 4895 dest++;
91d6fa6a
NC		 4896 i.op[dupl] = i.op[dest];
4897 i.types[dupl] = i.types[dest];
4898 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4899 }
c0f3af97
L		 4900 else
4901 {
4902duplicate:
4903 i.operands++;
4904 i.reg_operands++;
4905 i.tm.operands++;
4906
91d6fa6a
NC		 4907 i.op[dupl] = i.op[dest];
4908 i.types[dupl] = i.types[dest];
4909 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4910 }
4911
4912 if (i.tm.opcode_modifier.immext)
4913 process_immext ();
4914 }
4915 else if (i.tm.opcode_modifier.firstxmm0)
4916 {
4917 unsigned int j;
4918
4919 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4920 gas_assert (i.reg_operands
7ab9ffdd
L		 4921 && (operand_type_equal (&i.types[0], &regxmm)
4922 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4923 if (i.op[0].regs->reg_num != 0)
4924 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4925
4926 for (j = 1; j < i.operands; j++)
4927 {
4928 i.op[j - 1] = i.op[j];
4929 i.types[j - 1] = i.types[j];
4930
4931 /* We need to adjust fields in i.tm since they are used by
4932 build_modrm_byte. */
4933 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4934 }
4935
e2ec9d29
L		 4936 i.operands--;
4937 i.reg_operands--;
e2ec9d29
L		 4938 i.tm.operands--;
4939 }
4940 else if (i.tm.opcode_modifier.regkludge)
4941 {
4942 /* The imul $imm, %reg instruction is converted into
4943 imul $imm, %reg, %reg, and the clr %reg instruction
4944 is converted into xor %reg, %reg. */
4945
4946 unsigned int first_reg_op;
4947
4948 if (operand_type_check (i.types[0], reg))
4949 first_reg_op = 0;
4950 else
4951 first_reg_op = 1;
4952 /* Pretend we saw the extra register operand. */
9c2799c2 4953 gas_assert (i.reg_operands == 1
7ab9ffdd 4954 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4955 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4956 i.types[first_reg_op + 1] = i.types[first_reg_op];
4957 i.operands++;
4958 i.reg_operands++;
29b0f896
AM		 4959 }
4960
40fb9820 4961 if (i.tm.opcode_modifier.shortform)
29b0f896 4962 {
40fb9820
L		 4963 if (i.types[0].bitfield.sreg2
4964 || i.types[0].bitfield.sreg3)
29b0f896 4965 {
4eed87de
AM		 4966 if (i.tm.base_opcode == POP_SEG_SHORT
4967 && i.op[0].regs->reg_num == 1)
29b0f896 4968 {
a87af027 4969 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4970 return 0;
29b0f896 4971 }
4eed87de
AM		 4972 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4973 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4974 i.rex |= REX_B;
4eed87de
AM		 4975 }
4976 else
4977 {
7ab9ffdd 4978 /* The register or float register operand is in operand
85f10a01 4979 0 or 1. */
40fb9820 4980 unsigned int op;
7ab9ffdd
L		 4981
4982 if (i.types[0].bitfield.floatreg
4983 || operand_type_check (i.types[0], reg))
4984 op = 0;
4985 else
4986 op = 1;
4eed87de
AM		 4987 /* Register goes in low 3 bits of opcode. */
4988 i.tm.base_opcode |= i.op[op].regs->reg_num;
4989 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4990 i.rex |= REX_B;
40fb9820 4991 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4992 {
4eed87de
AM		 4993 /* Warn about some common errors, but press on regardless.
4994 The first case can be generated by gcc (<= 2.8.1). */
4995 if (i.operands == 2)
4996 {
4997 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4998 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4999 register_prefix, i.op[!intel_syntax].regs->reg_name,
5000 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5001 }
5002 else
5003 {
5004 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5005 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5006 register_prefix, i.op[0].regs->reg_name);
4eed87de 5007 }
29b0f896
AM		 5008 }
5009 }
5010 }
40fb9820 5011 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5012 {
5013 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5014 must be put into the modrm byte). Now, we make the modrm and
5015 index base bytes based on all the info we've collected. */
29b0f896
AM		 5016
5017 default_seg = build_modrm_byte ();
5018 }
8a2ed489 5019 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5020 {
5021 default_seg = &ds;
5022 }
40fb9820 5023 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5024 {
5025 /* For the string instructions that allow a segment override
5026 on one of their operands, the default segment is ds. */
5027 default_seg = &ds;
5028 }
5029
75178d9d
L		 5030 if (i.tm.base_opcode == 0x8d /* lea */
5031 && i.seg[0]
5032 && !quiet_warnings)
30123838 5033 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5034
5035 /* If a segment was explicitly specified, and the specified segment
5036 is not the default, use an opcode prefix to select it. If we
5037 never figured out what the default segment is, then default_seg
5038 will be zero at this point, and the specified segment prefix will
5039 always be used. */
29b0f896
AM		 5040 if ((i.seg[0]) && (i.seg[0] != default_seg))
5041 {
5042 if (!add_prefix (i.seg[0]->seg_prefix))
5043 return 0;
5044 }
5045 return 1;
5046}
5047
5048static const seg_entry *
e3bb37b5 5049build_modrm_byte (void)
29b0f896
AM		 5050{
5051 const seg_entry *default_seg = 0;
c0f3af97 5052 unsigned int source, dest;
8cd7925b 5053 int vex_3_sources;
c0f3af97
L		 5054
5055 /* The first operand of instructions with VEX prefix and 3 sources
5056 must be VEX_Imm4. */
8cd7925b 5057 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5058 if (vex_3_sources)
5059 {
91d6fa6a 5060 unsigned int nds, reg_slot;
4c2c6516 5061 expressionS *exp;
c0f3af97 5062
922d8de8 5063 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5064 && i.tm.opcode_modifier.immext)
5065 {
5066 dest = i.operands - 2;
5067 gas_assert (dest == 3);
5068 }
922d8de8 5069 else
a683cc34 5070 dest = i.operands - 1;
c0f3af97 5071 nds = dest - 1;
922d8de8 5072
a683cc34
SP		 5073 /* There are 2 kinds of instructions:
5074 1. 5 operands: 4 register operands or 3 register operands
5075 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5076 VexW0 or VexW1. The destination must be either XMM or YMM
5077 register.
5078 2. 4 operands: 4 register operands or 3 register operands
5079 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5080 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5081 || (i.reg_operands == 3 && i.mem_operands == 1))
5082 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5083 && (i.tm.opcode_modifier.veximmext
5084 || (i.imm_operands == 1
5085 && i.types[0].bitfield.vec_imm4
5086 && (i.tm.opcode_modifier.vexw == VEXW0
5087 || i.tm.opcode_modifier.vexw == VEXW1)
5088 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5089 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5090
5091 if (i.imm_operands == 0)
5092 {
5093 /* When there is no immediate operand, generate an 8bit
5094 immediate operand to encode the first operand. */
5095 exp = &im_expressions[i.imm_operands++];
5096 i.op[i.operands].imms = exp;
5097 i.types[i.operands] = imm8;
5098 i.operands++;
5099 /* If VexW1 is set, the first operand is the source and
5100 the second operand is encoded in the immediate operand. */
5101 if (i.tm.opcode_modifier.vexw == VEXW1)
5102 {
5103 source = 0;
5104 reg_slot = 1;
5105 }
5106 else
5107 {
5108 source = 1;
5109 reg_slot = 0;
5110 }
5111
5112 /* FMA swaps REG and NDS. */
5113 if (i.tm.cpu_flags.bitfield.cpufma)
5114 {
5115 unsigned int tmp;
5116 tmp = reg_slot;
5117 reg_slot = nds;
5118 nds = tmp;
5119 }
5120
24981e7b
L		 5121 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5122 &regxmm)
a683cc34
SP		 5123 || operand_type_equal (&i.tm.operand_types[reg_slot],
5124 &regymm));
5125 exp->X_op = O_constant;
5126 exp->X_add_number
5127 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5128 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5129 << 4);
a683cc34 5130 }
922d8de8 5131 else
a683cc34
SP		 5132 {
5133 unsigned int imm_slot;
5134
5135 if (i.tm.opcode_modifier.vexw == VEXW0)
5136 {
5137 /* If VexW0 is set, the third operand is the source and
5138 the second operand is encoded in the immediate
5139 operand. */
5140 source = 2;
5141 reg_slot = 1;
5142 }
5143 else
5144 {
5145 /* VexW1 is set, the second operand is the source and
5146 the third operand is encoded in the immediate
5147 operand. */
5148 source = 1;
5149 reg_slot = 2;
5150 }
5151
5152 if (i.tm.opcode_modifier.immext)
5153 {
5154 /* When ImmExt is set, the immdiate byte is the last
5155 operand. */
5156 imm_slot = i.operands - 1;
5157 source--;
5158 reg_slot--;
5159 }
5160 else
5161 {
5162 imm_slot = 0;
5163
5164 /* Turn on Imm8 so that output_imm will generate it. */
5165 i.types[imm_slot].bitfield.imm8 = 1;
5166 }
5167
24981e7b
L		 5168 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5169 &regxmm)
5170 || operand_type_equal (&i.tm.operand_types[reg_slot],
5171 &regymm));
a683cc34
SP		 5172 i.op[imm_slot].imms->X_add_number
5173 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5174 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5175 << 4);
a683cc34
SP		 5176 }
5177
5178 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5179 || operand_type_equal (&i.tm.operand_types[nds],
5180 &regymm));
dae39acc 5181 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5182 }
5183 else
5184 source = dest = 0;
29b0f896
AM		 5185
5186 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5187 implicit registers do not count. If there are 3 register
5188 operands, it must be a instruction with VexNDS. For a
5189 instruction with VexNDD, the destination register is encoded
5190 in VEX prefix. If there are 4 register operands, it must be
5191 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5192 if (i.mem_operands == 0
5193 && ((i.reg_operands == 2
2426c15f 5194 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5195 || (i.reg_operands == 3
2426c15f 5196 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5197 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5198 {
cab737b9
L		 5199 switch (i.operands)
5200 {
5201 case 2:
5202 source = 0;
5203 break;
5204 case 3:
c81128dc
L		 5205 /* When there are 3 operands, one of them may be immediate,
5206 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5207 the first operand must be shift count register (cl) or it
5208 is an instruction with VexNDS. */
9c2799c2 5209 gas_assert (i.imm_operands == 1
7ab9ffdd 5210 || (i.imm_operands == 0
2426c15f 5211 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5212 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5213 if (operand_type_check (i.types[0], imm)
5214 || i.types[0].bitfield.shiftcount)
5215 source = 1;
5216 else
5217 source = 0;
cab737b9
L		 5218 break;
5219 case 4:
368d64cc
L		 5220 /* When there are 4 operands, the first two must be 8bit
5221 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5222 one.
5223
5224 For instructions with VexNDS, if the first operand
5225 an imm8, the source operand is the 2nd one. If the last
5226 operand is imm8, the source operand is the first one. */
9c2799c2 5227 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5228 && i.types[0].bitfield.imm8
5229 && i.types[1].bitfield.imm8)
2426c15f 5230 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5231 && i.imm_operands == 1
5232 && (i.types[0].bitfield.imm8
5233 || i.types[i.operands - 1].bitfield.imm8)));
2426c15f 5234 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5235 {
5236 if (i.types[0].bitfield.imm8)
5237 source = 1;
5238 else
5239 source = 0;
5240 }
5241 else
5242 source = 2;
5243 break;
5244 case 5:
cab737b9
L		 5245 break;
5246 default:
5247 abort ();
5248 }
5249
c0f3af97
L		 5250 if (!vex_3_sources)
5251 {
5252 dest = source + 1;
5253
2426c15f 5254 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5255 {
5256 /* For instructions with VexNDS, the register-only
5257 source operand must be XMM or YMM register. It is
fa99fab2
L		 5258 encoded in VEX prefix. We need to clear RegMem bit
5259 before calling operand_type_equal. */
5260 i386_operand_type op = i.tm.operand_types[dest];
5261 op.bitfield.regmem = 0;
c0f3af97 5262 if ((dest + 1) >= i.operands
fa99fab2
L		 5263 || (!operand_type_equal (&op, &regxmm)
5264 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5265 abort ();
5266 i.vex.register_specifier = i.op[dest].regs;
5267 dest++;
5268 }
5269 }
29b0f896
AM		 5270
5271 i.rm.mode = 3;
5272 /* One of the register operands will be encoded in the i.tm.reg
5273 field, the other in the combined i.tm.mode and i.tm.regmem
5274 fields. If no form of this instruction supports a memory
5275 destination operand, then we assume the source operand may
5276 sometimes be a memory operand and so we need to store the
5277 destination in the i.rm.reg field. */
40fb9820
L		 5278 if (!i.tm.operand_types[dest].bitfield.regmem
5279 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5280 {
5281 i.rm.reg = i.op[dest].regs->reg_num;
5282 i.rm.regmem = i.op[source].regs->reg_num;
5283 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5284 i.rex |= REX_R;
29b0f896 5285 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5286 i.rex |= REX_B;
29b0f896
AM		 5287 }
5288 else
5289 {
5290 i.rm.reg = i.op[source].regs->reg_num;
5291 i.rm.regmem = i.op[dest].regs->reg_num;
5292 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5293 i.rex |= REX_B;
29b0f896 5294 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5295 i.rex |= REX_R;
29b0f896 5296 }
161a04f6 5297 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5298 {
40fb9820
L		 5299 if (!i.types[0].bitfield.control
5300 && !i.types[1].bitfield.control)
c4a530c5 5301 abort ();
161a04f6 5302 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5303 add_prefix (LOCK_PREFIX_OPCODE);
5304 }
29b0f896
AM		 5305 }
5306 else
5307 { /* If it's not 2 reg operands... */
c0f3af97
L		 5308 unsigned int mem;
5309
29b0f896
AM		 5310 if (i.mem_operands)
5311 {
5312 unsigned int fake_zero_displacement = 0;
99018f42 5313 unsigned int op;
4eed87de 5314
7ab9ffdd
L		 5315 for (op = 0; op < i.operands; op++)
5316 if (operand_type_check (i.types[op], anymem))
5317 break;
7ab9ffdd 5318 gas_assert (op < i.operands);
29b0f896
AM		 5319
5320 default_seg = &ds;
5321
5322 if (i.base_reg == 0)
5323 {
5324 i.rm.mode = 0;
5325 if (!i.disp_operands)
5326 fake_zero_displacement = 1;
5327 if (i.index_reg == 0)
5328 {
5329 /* Operand is just <disp> */
20f0a1fc 5330 if (flag_code == CODE_64BIT)
29b0f896
AM		 5331 {
5332 /* 64bit mode overwrites the 32bit absolute
5333 addressing by RIP relative addressing and
5334 absolute addressing is encoded by one of the
5335 redundant SIB forms. */
5336 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5337 i.sib.base = NO_BASE_REGISTER;
5338 i.sib.index = NO_INDEX_REGISTER;
fc225355 5339 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5340 ? disp32s : disp32);
20f0a1fc 5341 }
fc225355
L		 5342 else if ((flag_code == CODE_16BIT)
5343 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5344 {
5345 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5346 i.types[op] = disp16;
20f0a1fc
NC		 5347 }
5348 else
5349 {
5350 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5351 i.types[op] = disp32;
29b0f896
AM		 5352 }
5353 }
5354 else /* !i.base_reg && i.index_reg */
5355 {
db51cc60
L		 5356 if (i.index_reg->reg_num == RegEiz
5357 || i.index_reg->reg_num == RegRiz)
5358 i.sib.index = NO_INDEX_REGISTER;
5359 else
5360 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5361 i.sib.base = NO_BASE_REGISTER;
5362 i.sib.scale = i.log2_scale_factor;
5363 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5364 i.types[op].bitfield.disp8 = 0;
5365 i.types[op].bitfield.disp16 = 0;
5366 i.types[op].bitfield.disp64 = 0;
29b0f896 5367 if (flag_code != CODE_64BIT)
40fb9820
L		 5368 {
5369 /* Must be 32 bit */
5370 i.types[op].bitfield.disp32 = 1;
5371 i.types[op].bitfield.disp32s = 0;
5372 }
29b0f896 5373 else
40fb9820
L		 5374 {
5375 i.types[op].bitfield.disp32 = 0;
5376 i.types[op].bitfield.disp32s = 1;
5377 }
29b0f896 5378 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5379 i.rex |= REX_X;
29b0f896
AM		 5380 }
5381 }
5382 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5383 else if (i.base_reg->reg_num == RegRip ||
5384 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5385 {
5386 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5387 i.types[op].bitfield.disp8 = 0;
5388 i.types[op].bitfield.disp16 = 0;
5389 i.types[op].bitfield.disp32 = 0;
5390 i.types[op].bitfield.disp32s = 1;
5391 i.types[op].bitfield.disp64 = 0;
71903a11 5392 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5393 if (! i.disp_operands)
5394 fake_zero_displacement = 1;
29b0f896 5395 }
40fb9820 5396 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5397 {
5398 switch (i.base_reg->reg_num)
5399 {
5400 case 3: /* (%bx) */
5401 if (i.index_reg == 0)
5402 i.rm.regmem = 7;
5403 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5404 i.rm.regmem = i.index_reg->reg_num - 6;
5405 break;
5406 case 5: /* (%bp) */
5407 default_seg = &ss;
5408 if (i.index_reg == 0)
5409 {
5410 i.rm.regmem = 6;
40fb9820 5411 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5412 {
5413 /* fake (%bp) into 0(%bp) */
40fb9820 5414 i.types[op].bitfield.disp8 = 1;
252b5132 5415 fake_zero_displacement = 1;
29b0f896
AM		 5416 }
5417 }
5418 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5419 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5420 break;
5421 default: /* (%si) -> 4 or (%di) -> 5 */
5422 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5423 }
5424 i.rm.mode = mode_from_disp_size (i.types[op]);
5425 }
5426 else /* i.base_reg and 32/64 bit mode */
5427 {
5428 if (flag_code == CODE_64BIT
40fb9820
L		 5429 && operand_type_check (i.types[op], disp))
5430 {
5431 i386_operand_type temp;
0dfbf9d7 5432 operand_type_set (&temp, 0);
40fb9820
L		 5433 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5434 i.types[op] = temp;
5435 if (i.prefix[ADDR_PREFIX] == 0)
5436 i.types[op].bitfield.disp32s = 1;
5437 else
5438 i.types[op].bitfield.disp32 = 1;
5439 }
20f0a1fc 5440
29b0f896
AM		 5441 i.rm.regmem = i.base_reg->reg_num;
5442 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5443 i.rex |= REX_B;
29b0f896
AM		 5444 i.sib.base = i.base_reg->reg_num;
5445 /* x86-64 ignores REX prefix bit here to avoid decoder
5446 complications. */
5447 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5448 {
5449 default_seg = &ss;
5450 if (i.disp_operands == 0)
5451 {
5452 fake_zero_displacement = 1;
40fb9820 5453 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5454 }
5455 }
5456 else if (i.base_reg->reg_num == ESP_REG_NUM)
5457 {
5458 default_seg = &ss;
5459 }
5460 i.sib.scale = i.log2_scale_factor;
5461 if (i.index_reg == 0)
5462 {
5463 /* <disp>(%esp) becomes two byte modrm with no index
5464 register. We've already stored the code for esp
5465 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5466 Any base register besides %esp will not use the
5467 extra modrm byte. */
5468 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5469 }
5470 else
5471 {
db51cc60
L		 5472 if (i.index_reg->reg_num == RegEiz
5473 || i.index_reg->reg_num == RegRiz)
5474 i.sib.index = NO_INDEX_REGISTER;
5475 else
5476 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5477 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5478 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5479 i.rex |= REX_X;
29b0f896 5480 }
67a4f2b7
AO		 5481
5482 if (i.disp_operands
5483 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5484 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5485 i.rm.mode = 0;
5486 else
5487 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5488 }
252b5132 5489
29b0f896
AM		 5490 if (fake_zero_displacement)
5491 {
5492 /* Fakes a zero displacement assuming that i.types[op]
5493 holds the correct displacement size. */
5494 expressionS *exp;
5495
9c2799c2 5496 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5497 exp = &disp_expressions[i.disp_operands++];
5498 i.op[op].disps = exp;
5499 exp->X_op = O_constant;
5500 exp->X_add_number = 0;
5501 exp->X_add_symbol = (symbolS *) 0;
5502 exp->X_op_symbol = (symbolS *) 0;
5503 }
c0f3af97
L		 5504
5505 mem = op;
29b0f896 5506 }
c0f3af97
L		 5507 else
5508 mem = ~0;
252b5132 5509
8c43a48b 5510 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5511 {
5512 if (operand_type_check (i.types[0], imm))
5513 i.vex.register_specifier = NULL;
5514 else
5515 {
5516 /* VEX.vvvv encodes one of the sources when the first
5517 operand is not an immediate. */
1ef99a7b 5518 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5519 i.vex.register_specifier = i.op[0].regs;
5520 else
5521 i.vex.register_specifier = i.op[1].regs;
5522 }
5523
5524 /* Destination is a XMM register encoded in the ModRM.reg
5525 and VEX.R bit. */
5526 i.rm.reg = i.op[2].regs->reg_num;
5527 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5528 i.rex |= REX_R;
5529
5530 /* ModRM.rm and VEX.B encodes the other source. */
5531 if (!i.mem_operands)
5532 {
5533 i.rm.mode = 3;
5534
1ef99a7b 5535 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5536 i.rm.regmem = i.op[1].regs->reg_num;
5537 else
5538 i.rm.regmem = i.op[0].regs->reg_num;
5539
5540 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5541 i.rex |= REX_B;
5542 }
5543 }
2426c15f 5544 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5545 {
5546 i.vex.register_specifier = i.op[2].regs;
5547 if (!i.mem_operands)
5548 {
5549 i.rm.mode = 3;
5550 i.rm.regmem = i.op[1].regs->reg_num;
5551 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5552 i.rex |= REX_B;
5553 }
5554 }
29b0f896
AM		 5555 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5556 (if any) based on i.tm.extension_opcode. Again, we must be
5557 careful to make sure that segment/control/debug/test/MMX
5558 registers are coded into the i.rm.reg field. */
f88c9eb0 5559 else if (i.reg_operands)
29b0f896 5560 {
99018f42 5561 unsigned int op;
7ab9ffdd
L		 5562 unsigned int vex_reg = ~0;
5563
5564 for (op = 0; op < i.operands; op++)
5565 if (i.types[op].bitfield.reg8
5566 || i.types[op].bitfield.reg16
5567 || i.types[op].bitfield.reg32
5568 || i.types[op].bitfield.reg64
5569 || i.types[op].bitfield.regmmx
5570 || i.types[op].bitfield.regxmm
5571 || i.types[op].bitfield.regymm
5572 || i.types[op].bitfield.sreg2
5573 || i.types[op].bitfield.sreg3
5574 || i.types[op].bitfield.control
5575 || i.types[op].bitfield.debug
5576 || i.types[op].bitfield.test)
5577 break;
c0209578 5578
7ab9ffdd
L		 5579 if (vex_3_sources)
5580 op = dest;
2426c15f 5581 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5582 {
5583 /* For instructions with VexNDS, the register-only
5584 source operand is encoded in VEX prefix. */
5585 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5586
7ab9ffdd 5587 if (op > mem)
c0f3af97 5588 {
7ab9ffdd
L		 5589 vex_reg = op++;
5590 gas_assert (op < i.operands);
c0f3af97
L		 5591 }
5592 else
c0f3af97 5593 {
7ab9ffdd
L		 5594 vex_reg = op + 1;
5595 gas_assert (vex_reg < i.operands);
c0f3af97 5596 }
7ab9ffdd 5597 }
2426c15f 5598 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5599 {
5600 /* For instructions with VexNDD, there should be
5601 no memory operand and the register destination
5602 is encoded in VEX prefix. */
5603 gas_assert (i.mem_operands == 0
5604 && (op + 2) == i.operands);
5605 vex_reg = op + 1;
5606 }
5607 else
5608 gas_assert (op < i.operands);
99018f42 5609
7ab9ffdd
L		 5610 if (vex_reg != (unsigned int) ~0)
5611 {
5612 gas_assert (i.reg_operands == 2);
5613
5614 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5615 &regxmm)
7ab9ffdd
L		 5616 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5617 &regymm))
5618 abort ();
f88c9eb0 5619
7ab9ffdd
L		 5620 i.vex.register_specifier = i.op[vex_reg].regs;
5621 }
5622
1b9f0c97
L		 5623 /* Don't set OP operand twice. */
5624 if (vex_reg != op)
7ab9ffdd 5625 {
1b9f0c97
L		 5626 /* If there is an extension opcode to put here, the
5627 register number must be put into the regmem field. */
5628 if (i.tm.extension_opcode != None)
5629 {
5630 i.rm.regmem = i.op[op].regs->reg_num;
5631 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5632 i.rex |= REX_B;
5633 }
5634 else
5635 {
5636 i.rm.reg = i.op[op].regs->reg_num;
5637 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5638 i.rex |= REX_R;
5639 }
7ab9ffdd 5640 }
252b5132 5641
29b0f896
AM		 5642 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5643 must set it to 3 to indicate this is a register operand
5644 in the regmem field. */
5645 if (!i.mem_operands)
5646 i.rm.mode = 3;
5647 }
252b5132 5648
29b0f896 5649 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5650 if (i.tm.extension_opcode != None)
29b0f896
AM		 5651 i.rm.reg = i.tm.extension_opcode;
5652 }
5653 return default_seg;
5654}
252b5132 5655
29b0f896 5656static void
e3bb37b5 5657output_branch (void)
29b0f896
AM		 5658{
5659 char *p;
5660 int code16;
5661 int prefix;
5662 relax_substateT subtype;
5663 symbolS *sym;
5664 offsetT off;
5665
5666 code16 = 0;
5667 if (flag_code == CODE_16BIT)
5668 code16 = CODE16;
5669
5670 prefix = 0;
5671 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5672 {
29b0f896
AM		 5673 prefix = 1;
5674 i.prefixes -= 1;
5675 code16 ^= CODE16;
252b5132 5676 }
29b0f896
AM		 5677 /* Pentium4 branch hints. */
5678 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5679 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5680 {
29b0f896
AM		 5681 prefix++;
5682 i.prefixes--;
5683 }
5684 if (i.prefix[REX_PREFIX] != 0)
5685 {
5686 prefix++;
5687 i.prefixes--;
2f66722d
AM		 5688 }
5689
29b0f896
AM		 5690 if (i.prefixes != 0 && !intel_syntax)
5691 as_warn (_("skipping prefixes on this instruction"));
5692
5693 /* It's always a symbol; End frag & setup for relax.
5694 Make sure there is enough room in this frag for the largest
5695 instruction we may generate in md_convert_frag. This is 2
5696 bytes for the opcode and room for the prefix and largest
5697 displacement. */
5698 frag_grow (prefix + 2 + 4);
5699 /* Prefix and 1 opcode byte go in fr_fix. */
5700 p = frag_more (prefix + 1);
5701 if (i.prefix[DATA_PREFIX] != 0)
5702 *p++ = DATA_PREFIX_OPCODE;
5703 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5704 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5705 *p++ = i.prefix[SEG_PREFIX];
5706 if (i.prefix[REX_PREFIX] != 0)
5707 *p++ = i.prefix[REX_PREFIX];
5708 *p = i.tm.base_opcode;
5709
5710 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5711 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5712 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5713 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5714 else
5715 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5716 subtype |= code16;
3e73aa7c 5717
29b0f896
AM		 5718 sym = i.op[0].disps->X_add_symbol;
5719 off = i.op[0].disps->X_add_number;
3e73aa7c 5720
29b0f896
AM		 5721 if (i.op[0].disps->X_op != O_constant
5722 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5723 {
29b0f896
AM		 5724 /* Handle complex expressions. */
5725 sym = make_expr_symbol (i.op[0].disps);
5726 off = 0;
5727 }
3e73aa7c 5728
29b0f896
AM		 5729 /* 1 possible extra opcode + 4 byte displacement go in var part.
5730 Pass reloc in fr_var. */
5731 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5732}
3e73aa7c 5733
29b0f896 5734static void
e3bb37b5 5735output_jump (void)
29b0f896
AM		 5736{
5737 char *p;
5738 int size;
3e02c1cc 5739 fixS *fixP;
29b0f896 5740
40fb9820 5741 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5742 {
5743 /* This is a loop or jecxz type instruction. */
5744 size = 1;
5745 if (i.prefix[ADDR_PREFIX] != 0)
5746 {
5747 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5748 i.prefixes -= 1;
5749 }
5750 /* Pentium4 branch hints. */
5751 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5752 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5753 {
5754 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5755 i.prefixes--;
3e73aa7c
JH		 5756 }
5757 }
29b0f896
AM		 5758 else
5759 {
5760 int code16;
3e73aa7c 5761
29b0f896
AM		 5762 code16 = 0;
5763 if (flag_code == CODE_16BIT)
5764 code16 = CODE16;
3e73aa7c 5765
29b0f896
AM		 5766 if (i.prefix[DATA_PREFIX] != 0)
5767 {
5768 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5769 i.prefixes -= 1;
5770 code16 ^= CODE16;
5771 }
252b5132 5772
29b0f896
AM		 5773 size = 4;
5774 if (code16)
5775 size = 2;
5776 }
9fcc94b6 5777
29b0f896
AM		 5778 if (i.prefix[REX_PREFIX] != 0)
5779 {
5780 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5781 i.prefixes -= 1;
5782 }
252b5132 5783
29b0f896
AM		 5784 if (i.prefixes != 0 && !intel_syntax)
5785 as_warn (_("skipping prefixes on this instruction"));
e0890092 5786
29b0f896
AM		 5787 p = frag_more (1 + size);
5788 *p++ = i.tm.base_opcode;
e0890092 5789
3e02c1cc
AM		 5790 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5791 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5792
5793 /* All jumps handled here are signed, but don't use a signed limit
5794 check for 32 and 16 bit jumps as we want to allow wrap around at
5795 4G and 64k respectively. */
5796 if (size == 1)
5797 fixP->fx_signed = 1;
29b0f896 5798}
e0890092 5799
29b0f896 5800static void
e3bb37b5 5801output_interseg_jump (void)
29b0f896
AM		 5802{
5803 char *p;
5804 int size;
5805 int prefix;
5806 int code16;
252b5132 5807
29b0f896
AM		 5808 code16 = 0;
5809 if (flag_code == CODE_16BIT)
5810 code16 = CODE16;
a217f122 5811
29b0f896
AM		 5812 prefix = 0;
5813 if (i.prefix[DATA_PREFIX] != 0)
5814 {
5815 prefix = 1;
5816 i.prefixes -= 1;
5817 code16 ^= CODE16;
5818 }
5819 if (i.prefix[REX_PREFIX] != 0)
5820 {
5821 prefix++;
5822 i.prefixes -= 1;
5823 }
252b5132 5824
29b0f896
AM		 5825 size = 4;
5826 if (code16)
5827 size = 2;
252b5132 5828
29b0f896
AM		 5829 if (i.prefixes != 0 && !intel_syntax)
5830 as_warn (_("skipping prefixes on this instruction"));
252b5132 5831
29b0f896
AM		 5832 /* 1 opcode; 2 segment; offset */
5833 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5834
29b0f896
AM		 5835 if (i.prefix[DATA_PREFIX] != 0)
5836 *p++ = DATA_PREFIX_OPCODE;
252b5132 5837
29b0f896
AM		 5838 if (i.prefix[REX_PREFIX] != 0)
5839 *p++ = i.prefix[REX_PREFIX];
252b5132 5840
29b0f896
AM		 5841 *p++ = i.tm.base_opcode;
5842 if (i.op[1].imms->X_op == O_constant)
5843 {
5844 offsetT n = i.op[1].imms->X_add_number;
252b5132 5845
29b0f896
AM		 5846 if (size == 2
5847 && !fits_in_unsigned_word (n)
5848 && !fits_in_signed_word (n))
5849 {
5850 as_bad (_("16-bit jump out of range"));
5851 return;
5852 }
5853 md_number_to_chars (p, n, size);
5854 }
5855 else
5856 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5857 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5858 if (i.op[0].imms->X_op != O_constant)
5859 as_bad (_("can't handle non absolute segment in `%s'"),
5860 i.tm.name);
5861 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5862}
a217f122 5863
29b0f896 5864static void
e3bb37b5 5865output_insn (void)
29b0f896 5866{
2bbd9c25
JJ		 5867 fragS *insn_start_frag;
5868 offsetT insn_start_off;
5869
29b0f896
AM		 5870 /* Tie dwarf2 debug info to the address at the start of the insn.
5871 We can't do this after the insn has been output as the current
5872 frag may have been closed off. eg. by frag_var. */
5873 dwarf2_emit_insn (0);
5874
2bbd9c25
JJ		 5875 insn_start_frag = frag_now;
5876 insn_start_off = frag_now_fix ();
5877
29b0f896 5878 /* Output jumps. */
40fb9820 5879 if (i.tm.opcode_modifier.jump)
29b0f896 5880 output_branch ();
40fb9820
L		 5881 else if (i.tm.opcode_modifier.jumpbyte
5882 || i.tm.opcode_modifier.jumpdword)
29b0f896 5883 output_jump ();
40fb9820 5884 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5885 output_interseg_jump ();
5886 else
5887 {
5888 /* Output normal instructions here. */
5889 char *p;
5890 unsigned char *q;
47465058 5891 unsigned int j;
331d2d0d 5892 unsigned int prefix;
4dffcebc 5893
c0f3af97
L		 5894 /* Since the VEX prefix contains the implicit prefix, we don't
5895 need the explicit prefix. */
5896 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5897 {
c0f3af97 5898 switch (i.tm.opcode_length)
bc4bd9ab 5899 {
c0f3af97
L		 5900 case 3:
5901 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5902 {
c0f3af97
L		 5903 prefix = (i.tm.base_opcode >> 24) & 0xff;
5904 goto check_prefix;
5905 }
5906 break;
5907 case 2:
5908 if ((i.tm.base_opcode & 0xff0000) != 0)
5909 {
5910 prefix = (i.tm.base_opcode >> 16) & 0xff;
5911 if (i.tm.cpu_flags.bitfield.cpupadlock)
5912 {
4dffcebc 5913check_prefix:
c0f3af97 5914 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5915 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5916 != REPE_PREFIX_OPCODE))
5917 add_prefix (prefix);
5918 }
5919 else
4dffcebc
L		 5920 add_prefix (prefix);
5921 }
c0f3af97
L		 5922 break;
5923 case 1:
5924 break;
5925 default:
5926 abort ();
bc4bd9ab 5927 }
c0f3af97
L		 5928
5929 /* The prefix bytes. */
5930 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5931 if (*q)
5932 FRAG_APPEND_1_CHAR (*q);
0f10071e 5933 }
252b5132 5934
c0f3af97
L		 5935 if (i.tm.opcode_modifier.vex)
5936 {
5937 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5938 if (*q)
5939 switch (j)
5940 {
5941 case REX_PREFIX:
5942 /* REX byte is encoded in VEX prefix. */
5943 break;
5944 case SEG_PREFIX:
5945 case ADDR_PREFIX:
5946 FRAG_APPEND_1_CHAR (*q);
5947 break;
5948 default:
5949 /* There should be no other prefixes for instructions
5950 with VEX prefix. */
5951 abort ();
5952 }
5953
5954 /* Now the VEX prefix. */
5955 p = frag_more (i.vex.length);
5956 for (j = 0; j < i.vex.length; j++)
5957 p[j] = i.vex.bytes[j];
5958 }
252b5132 5959
29b0f896 5960 /* Now the opcode; be careful about word order here! */
4dffcebc 5961 if (i.tm.opcode_length == 1)
29b0f896
AM		 5962 {
5963 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5964 }
5965 else
5966 {
4dffcebc 5967 switch (i.tm.opcode_length)
331d2d0d 5968 {
4dffcebc 5969 case 3:
331d2d0d
L		 5970 p = frag_more (3);
5971 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5972 break;
5973 case 2:
5974 p = frag_more (2);
5975 break;
5976 default:
5977 abort ();
5978 break;
331d2d0d 5979 }
0f10071e 5980
29b0f896
AM		 5981 /* Put out high byte first: can't use md_number_to_chars! */
5982 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5983 *p = i.tm.base_opcode & 0xff;
5984 }
3e73aa7c 5985
29b0f896 5986 /* Now the modrm byte and sib byte (if present). */
40fb9820 5987 if (i.tm.opcode_modifier.modrm)
29b0f896 5988 {
4a3523fa
L		 5989 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5990 | i.rm.reg << 3
5991 | i.rm.mode << 6));
29b0f896
AM		 5992 /* If i.rm.regmem == ESP (4)
5993 && i.rm.mode != (Register mode)
5994 && not 16 bit
5995 ==> need second modrm byte. */
5996 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5997 && i.rm.mode != 3
40fb9820 5998 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5999 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6000 | i.sib.index << 3
6001 | i.sib.scale << 6));
29b0f896 6002 }
3e73aa7c 6003
29b0f896 6004 if (i.disp_operands)
2bbd9c25 6005 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6006
29b0f896 6007 if (i.imm_operands)
2bbd9c25 6008 output_imm (insn_start_frag, insn_start_off);
29b0f896 6009 }
252b5132 6010
29b0f896
AM		 6011#ifdef DEBUG386
6012 if (flag_debug)
6013 {
7b81dfbb 6014 pi ("" /*line*/, &i);
29b0f896
AM		 6015 }
6016#endif /* DEBUG386 */
6017}
252b5132 6018
e205caa7
L		 6019/* Return the size of the displacement operand N. */
6020
6021static int
6022disp_size (unsigned int n)
6023{
6024 int size = 4;
40fb9820
L		 6025 if (i.types[n].bitfield.disp64)
6026 size = 8;
6027 else if (i.types[n].bitfield.disp8)
6028 size = 1;
6029 else if (i.types[n].bitfield.disp16)
6030 size = 2;
e205caa7
L		 6031 return size;
6032}
6033
6034/* Return the size of the immediate operand N. */
6035
6036static int
6037imm_size (unsigned int n)
6038{
6039 int size = 4;
40fb9820
L		 6040 if (i.types[n].bitfield.imm64)
6041 size = 8;
6042 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6043 size = 1;
6044 else if (i.types[n].bitfield.imm16)
6045 size = 2;
e205caa7
L		 6046 return size;
6047}
6048
29b0f896 6049static void
64e74474 6050output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6051{
6052 char *p;
6053 unsigned int n;
252b5132 6054
29b0f896
AM		 6055 for (n = 0; n < i.operands; n++)
6056 {
40fb9820 6057 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6058 {
6059 if (i.op[n].disps->X_op == O_constant)
6060 {
e205caa7 6061 int size = disp_size (n);
29b0f896 6062 offsetT val;
252b5132 6063
29b0f896
AM		 6064 val = offset_in_range (i.op[n].disps->X_add_number,
6065 size);
6066 p = frag_more (size);
6067 md_number_to_chars (p, val, size);
6068 }
6069 else
6070 {
f86103b7 6071 enum bfd_reloc_code_real reloc_type;
e205caa7 6072 int size = disp_size (n);
40fb9820 6073 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6074 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6075
e205caa7 6076 /* We can't have 8 bit displacement here. */
9c2799c2 6077 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6078
29b0f896
AM		 6079 /* The PC relative address is computed relative
6080 to the instruction boundary, so in case immediate
6081 fields follows, we need to adjust the value. */
6082 if (pcrel && i.imm_operands)
6083 {
29b0f896 6084 unsigned int n1;
e205caa7 6085 int sz = 0;
252b5132 6086
29b0f896 6087 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6088 if (operand_type_check (i.types[n1], imm))
252b5132 6089 {
e205caa7
L		 6090 /* Only one immediate is allowed for PC
6091 relative address. */
9c2799c2 6092 gas_assert (sz == 0);
e205caa7
L		 6093 sz = imm_size (n1);
6094 i.op[n].disps->X_add_number -= sz;
252b5132 6095 }
29b0f896 6096 /* We should find the immediate. */
9c2799c2 6097 gas_assert (sz != 0);
29b0f896 6098 }
520dc8e8 6099
29b0f896 6100 p = frag_more (size);
2bbd9c25 6101 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6102 if (GOT_symbol
2bbd9c25 6103 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6104 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6105 || reloc_type == BFD_RELOC_X86_64_32S
6106 || (reloc_type == BFD_RELOC_64
6107 && object_64bit))
d6ab8113
JB		 6108 && (i.op[n].disps->X_op == O_symbol
6109 || (i.op[n].disps->X_op == O_add
6110 && ((symbol_get_value_expression
6111 (i.op[n].disps->X_op_symbol)->X_op)
6112 == O_subtract))))
6113 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6114 {
6115 offsetT add;
6116
6117 if (insn_start_frag == frag_now)
6118 add = (p - frag_now->fr_literal) - insn_start_off;
6119 else
6120 {
6121 fragS *fr;
6122
6123 add = insn_start_frag->fr_fix - insn_start_off;
6124 for (fr = insn_start_frag->fr_next;
6125 fr && fr != frag_now; fr = fr->fr_next)
6126 add += fr->fr_fix;
6127 add += p - frag_now->fr_literal;
6128 }
6129
4fa24527 6130 if (!object_64bit)
7b81dfbb
AJ		 6131 {
6132 reloc_type = BFD_RELOC_386_GOTPC;
6133 i.op[n].imms->X_add_number += add;
6134 }
6135 else if (reloc_type == BFD_RELOC_64)
6136 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6137 else
7b81dfbb
AJ		 6138 /* Don't do the adjustment for x86-64, as there
6139 the pcrel addressing is relative to the _next_
6140 insn, and that is taken care of in other code. */
d6ab8113 6141 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6142 }
062cd5e7 6143 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6144 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6145 }
6146 }
6147 }
6148}
252b5132 6149
29b0f896 6150static void
64e74474 6151output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6152{
6153 char *p;
6154 unsigned int n;
252b5132 6155
29b0f896
AM		 6156 for (n = 0; n < i.operands; n++)
6157 {
40fb9820 6158 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6159 {
6160 if (i.op[n].imms->X_op == O_constant)
6161 {
e205caa7 6162 int size = imm_size (n);
29b0f896 6163 offsetT val;
b4cac588 6164
29b0f896
AM		 6165 val = offset_in_range (i.op[n].imms->X_add_number,
6166 size);
6167 p = frag_more (size);
6168 md_number_to_chars (p, val, size);
6169 }
6170 else
6171 {
6172 /* Not absolute_section.
6173 Need a 32-bit fixup (don't support 8bit
6174 non-absolute imms). Try to support other
6175 sizes ... */
f86103b7 6176 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6177 int size = imm_size (n);
6178 int sign;
29b0f896 6179
40fb9820 6180 if (i.types[n].bitfield.imm32s
a7d61044 6181 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6182 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6183 sign = 1;
e205caa7
L		 6184 else
6185 sign = 0;
520dc8e8 6186
29b0f896
AM		 6187 p = frag_more (size);
6188 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6189
2bbd9c25
JJ		 6190 /* This is tough to explain. We end up with this one if we
6191 * have operands that look like
6192 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6193 * obtain the absolute address of the GOT, and it is strongly
6194 * preferable from a performance point of view to avoid using
6195 * a runtime relocation for this. The actual sequence of
6196 * instructions often look something like:
6197 *
6198 * call .L66
6199 * .L66:
6200 * popl %ebx
6201 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6202 *
6203 * The call and pop essentially return the absolute address
6204 * of the label .L66 and store it in %ebx. The linker itself
6205 * will ultimately change the first operand of the addl so
6206 * that %ebx points to the GOT, but to keep things simple, the
6207 * .o file must have this operand set so that it generates not
6208 * the absolute address of .L66, but the absolute address of
6209 * itself. This allows the linker itself simply treat a GOTPC
6210 * relocation as asking for a pcrel offset to the GOT to be
6211 * added in, and the addend of the relocation is stored in the
6212 * operand field for the instruction itself.
6213 *
6214 * Our job here is to fix the operand so that it would add
6215 * the correct offset so that %ebx would point to itself. The
6216 * thing that is tricky is that .-.L66 will point to the
6217 * beginning of the instruction, so we need to further modify
6218 * the operand so that it will point to itself. There are
6219 * other cases where you have something like:
6220 *
6221 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6222 *
6223 * and here no correction would be required. Internally in
6224 * the assembler we treat operands of this form as not being
6225 * pcrel since the '.' is explicitly mentioned, and I wonder
6226 * whether it would simplify matters to do it this way. Who
6227 * knows. In earlier versions of the PIC patches, the
6228 * pcrel_adjust field was used to store the correction, but
6229 * since the expression is not pcrel, I felt it would be
6230 * confusing to do it this way. */
6231
d6ab8113 6232 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6233 || reloc_type == BFD_RELOC_X86_64_32S
6234 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6235 && GOT_symbol
6236 && GOT_symbol == i.op[n].imms->X_add_symbol
6237 && (i.op[n].imms->X_op == O_symbol
6238 || (i.op[n].imms->X_op == O_add
6239 && ((symbol_get_value_expression
6240 (i.op[n].imms->X_op_symbol)->X_op)
6241 == O_subtract))))
6242 {
2bbd9c25
JJ		 6243 offsetT add;
6244
6245 if (insn_start_frag == frag_now)
6246 add = (p - frag_now->fr_literal) - insn_start_off;
6247 else
6248 {
6249 fragS *fr;
6250
6251 add = insn_start_frag->fr_fix - insn_start_off;
6252 for (fr = insn_start_frag->fr_next;
6253 fr && fr != frag_now; fr = fr->fr_next)
6254 add += fr->fr_fix;
6255 add += p - frag_now->fr_literal;
6256 }
6257
4fa24527 6258 if (!object_64bit)
d6ab8113 6259 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6260 else if (size == 4)
d6ab8113 6261 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6262 else if (size == 8)
6263 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6264 i.op[n].imms->X_add_number += add;
29b0f896 6265 }
29b0f896
AM		 6266 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6267 i.op[n].imms, 0, reloc_type);
6268 }
6269 }
6270 }
252b5132
RH		 6271}
6272\f
d182319b
JB		 6273/* x86_cons_fix_new is called via the expression parsing code when a
6274 reloc is needed. We use this hook to get the correct .got reloc. */
6275static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6276static int cons_sign = -1;
6277
6278void
e3bb37b5 6279x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6280 expressionS *exp)
d182319b
JB		 6281{
6282 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6283
6284 got_reloc = NO_RELOC;
6285
6286#ifdef TE_PE
6287 if (exp->X_op == O_secrel)
6288 {
6289 exp->X_op = O_symbol;
6290 r = BFD_RELOC_32_SECREL;
6291 }
6292#endif
6293
6294 fix_new_exp (frag, off, len, exp, 0, r);
6295}
6296
718ddfc0
JB		 6297#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6298# define lex_got(reloc, adjust, types) NULL
6299#else
f3c180ae
AM		 6300/* Parse operands of the form
6301 <symbol>@GOTOFF+<nnn>
6302 and similar .plt or .got references.
6303
6304 If we find one, set up the correct relocation in RELOC and copy the
6305 input string, minus the `@GOTOFF' into a malloc'd buffer for
6306 parsing by the calling routine. Return this buffer, and if ADJUST
6307 is non-null set it to the length of the string we removed from the
6308 input line. Otherwise return NULL. */
6309static char *
91d6fa6a 6310lex_got (enum bfd_reloc_code_real *rel,
64e74474 6311 int *adjust,
40fb9820 6312 i386_operand_type *types)
f3c180ae 6313{
7b81dfbb
AJ		 6314 /* Some of the relocations depend on the size of what field is to
6315 be relocated. But in our callers i386_immediate and i386_displacement
6316 we don't yet know the operand size (this will be set by insn
6317 matching). Hence we record the word32 relocation here,
6318 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6319 static const struct {
6320 const char *str;
cff8d58a 6321 int len;
4fa24527 6322 const enum bfd_reloc_code_real rel[2];
40fb9820 6323 const i386_operand_type types64;
f3c180ae 6324 } gotrel[] = {
cff8d58a
L		 6325 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6326 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6327 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6328 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6329 BFD_RELOC_X86_64_PLT32 },
40fb9820 6330 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6331 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6332 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6333 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6334 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6335 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6336 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6337 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6338 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6339 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6340 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6341 BFD_RELOC_X86_64_TLSGD },
40fb9820 6342 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6343 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6344 _dummy_first_bfd_reloc_code_real },
40fb9820 6345 OPERAND_TYPE_NONE },
cff8d58a
L		 6346 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6347 BFD_RELOC_X86_64_TLSLD },
40fb9820 6348 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6349 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6350 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6351 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6352 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6353 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6354 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6355 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6356 _dummy_first_bfd_reloc_code_real },
40fb9820 6357 OPERAND_TYPE_NONE },
cff8d58a
L		 6358 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6359 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6360 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6361 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6362 _dummy_first_bfd_reloc_code_real },
40fb9820 6363 OPERAND_TYPE_NONE },
cff8d58a
L		 6364 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6365 _dummy_first_bfd_reloc_code_real },
40fb9820 6366 OPERAND_TYPE_NONE },
cff8d58a
L		 6367 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6368 BFD_RELOC_X86_64_GOT32 },
40fb9820 6369 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6370 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6371 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6372 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6373 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6374 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6375 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6376 };
6377 char *cp;
6378 unsigned int j;
6379
718ddfc0
JB		 6380 if (!IS_ELF)
6381 return NULL;
6382
f3c180ae 6383 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6384 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6385 return NULL;
6386
47465058 6387 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6388 {
cff8d58a 6389 int len = gotrel[j].len;
28f81592 6390 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6391 {
4fa24527 6392 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6393 {
28f81592
AM		 6394 int first, second;
6395 char *tmpbuf, *past_reloc;
f3c180ae 6396
91d6fa6a 6397 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6398 if (adjust)
6399 *adjust = len;
f3c180ae 6400
3956db08
JB		 6401 if (types)
6402 {
6403 if (flag_code != CODE_64BIT)
40fb9820
L		 6404 {
6405 types->bitfield.imm32 = 1;
6406 types->bitfield.disp32 = 1;
6407 }
3956db08
JB		 6408 else
6409 *types = gotrel[j].types64;
6410 }
6411
f3c180ae
AM		 6412 if (GOT_symbol == NULL)
6413 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6414
28f81592 6415 /* The length of the first part of our input line. */
f3c180ae 6416 first = cp - input_line_pointer;
28f81592
AM		 6417
6418 /* The second part goes from after the reloc token until
67c11a9b 6419 (and including) an end_of_line char or comma. */
28f81592 6420 past_reloc = cp + 1 + len;
67c11a9b
AM		 6421 cp = past_reloc;
6422 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6423 ++cp;
6424 second = cp + 1 - past_reloc;
28f81592
AM		 6425
6426 /* Allocate and copy string. The trailing NUL shouldn't
6427 be necessary, but be safe. */
1e9cc1c2 6428 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6429 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6430 if (second != 0 && *past_reloc != ' ')
6431 /* Replace the relocation token with ' ', so that
6432 errors like foo@GOTOFF1 will be detected. */
6433 tmpbuf[first++] = ' ';
6434 memcpy (tmpbuf + first, past_reloc, second);
6435 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6436 return tmpbuf;
6437 }
6438
4fa24527
JB		 6439 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6440 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6441 return NULL;
6442 }
6443 }
6444
6445 /* Might be a symbol version string. Don't as_bad here. */
6446 return NULL;
6447}
6448
f3c180ae 6449void
e3bb37b5 6450x86_cons (expressionS *exp, int size)
f3c180ae 6451{
ee86248c
JB		 6452 intel_syntax = -intel_syntax;
6453
4fa24527 6454 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6455 {
6456 /* Handle @GOTOFF and the like in an expression. */
6457 char *save;
6458 char *gotfree_input_line;
6459 int adjust;
6460
6461 save = input_line_pointer;
3956db08 6462 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6463 if (gotfree_input_line)
6464 input_line_pointer = gotfree_input_line;
6465
6466 expression (exp);
6467
6468 if (gotfree_input_line)
6469 {
6470 /* expression () has merrily parsed up to the end of line,
6471 or a comma - in the wrong buffer. Transfer how far
6472 input_line_pointer has moved to the right buffer. */
6473 input_line_pointer = (save
6474 + (input_line_pointer - gotfree_input_line)
6475 + adjust);
6476 free (gotfree_input_line);
3992d3b7
AM		 6477 if (exp->X_op == O_constant
6478 || exp->X_op == O_absent
6479 || exp->X_op == O_illegal
6480 || exp->X_op == O_register
6481 || exp->X_op == O_big)
6482 {
6483 char c = *input_line_pointer;
6484 *input_line_pointer = 0;
6485 as_bad (_("missing or invalid expression `%s'"), save);
6486 *input_line_pointer = c;
6487 }
f3c180ae
AM		 6488 }
6489 }
6490 else
6491 expression (exp);
ee86248c
JB		 6492
6493 intel_syntax = -intel_syntax;
6494
6495 if (intel_syntax)
6496 i386_intel_simplify (exp);
f3c180ae
AM		 6497}
6498#endif
6499
9f32dd5b
L		 6500static void
6501signed_cons (int size)
6482c264 6502{
d182319b
JB		 6503 if (flag_code == CODE_64BIT)
6504 cons_sign = 1;
6505 cons (size);
6506 cons_sign = -1;
6482c264
NC		 6507}
6508
d182319b 6509#ifdef TE_PE
6482c264
NC		 6510static void
6511pe_directive_secrel (dummy)
6512 int dummy ATTRIBUTE_UNUSED;
6513{
6514 expressionS exp;
6515
6516 do
6517 {
6518 expression (&exp);
6519 if (exp.X_op == O_symbol)
6520 exp.X_op = O_secrel;
6521
6522 emit_expr (&exp, 4);
6523 }
6524 while (*input_line_pointer++ == ',');
6525
6526 input_line_pointer--;
6527 demand_empty_rest_of_line ();
6528}
6482c264
NC		 6529#endif
6530
252b5132 6531static int
70e41ade 6532i386_immediate (char *imm_start)
252b5132
RH		 6533{
6534 char *save_input_line_pointer;
f3c180ae 6535 char *gotfree_input_line;
252b5132 6536 segT exp_seg = 0;
47926f60 6537 expressionS *exp;
40fb9820
L		 6538 i386_operand_type types;
6539
0dfbf9d7 6540 operand_type_set (&types, ~0);
252b5132
RH		 6541
6542 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6543 {
31b2323c
L		 6544 as_bad (_("at most %d immediate operands are allowed"),
6545 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6546 return 0;
6547 }
6548
6549 exp = &im_expressions[i.imm_operands++];
520dc8e8 6550 i.op[this_operand].imms = exp;
252b5132
RH		 6551
6552 if (is_space_char (*imm_start))
6553 ++imm_start;
6554
6555 save_input_line_pointer = input_line_pointer;
6556 input_line_pointer = imm_start;
6557
3956db08 6558 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6559 if (gotfree_input_line)
6560 input_line_pointer = gotfree_input_line;
252b5132
RH		 6561
6562 exp_seg = expression (exp);
6563
83183c0c 6564 SKIP_WHITESPACE ();
252b5132 6565 if (*input_line_pointer)
f3c180ae 6566 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6567
6568 input_line_pointer = save_input_line_pointer;
f3c180ae 6569 if (gotfree_input_line)
ee86248c
JB		 6570 {
6571 free (gotfree_input_line);
6572
6573 if (exp->X_op == O_constant || exp->X_op == O_register)
6574 exp->X_op = O_illegal;
6575 }
6576
6577 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6578}
252b5132 6579
ee86248c
JB		 6580static int
6581i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6582 i386_operand_type types, const char *imm_start)
6583{
6584 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6585 {
313c53d1
L		 6586 if (imm_start)
6587 as_bad (_("missing or invalid immediate expression `%s'"),
6588 imm_start);
3992d3b7 6589 return 0;
252b5132 6590 }
3e73aa7c 6591 else if (exp->X_op == O_constant)
252b5132 6592 {
47926f60 6593 /* Size it properly later. */
40fb9820 6594 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6595 /* If BFD64, sign extend val. */
4eed87de
AM		 6596 if (!use_rela_relocations
6597 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6598 exp->X_add_number
6599 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6600 }
4c63da97 6601#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6602 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6603 && exp_seg != absolute_section
47926f60 6604 && exp_seg != text_section
24eab124
AM		 6605 && exp_seg != data_section
6606 && exp_seg != bss_section
6607 && exp_seg != undefined_section
f86103b7 6608 && !bfd_is_com_section (exp_seg))
252b5132 6609 {
d0b47220 6610 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6611 return 0;
6612 }
6613#endif
bb8f5920
L		 6614 else if (!intel_syntax && exp->X_op == O_register)
6615 {
313c53d1
L		 6616 if (imm_start)
6617 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6618 return 0;
6619 }
252b5132
RH		 6620 else
6621 {
6622 /* This is an address. The size of the address will be
24eab124 6623 determined later, depending on destination register,
3e73aa7c 6624 suffix, or the default for the section. */
40fb9820
L		 6625 i.types[this_operand].bitfield.imm8 = 1;
6626 i.types[this_operand].bitfield.imm16 = 1;
6627 i.types[this_operand].bitfield.imm32 = 1;
6628 i.types[this_operand].bitfield.imm32s = 1;
6629 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6630 i.types[this_operand] = operand_type_and (i.types[this_operand],
6631 types);
252b5132
RH		 6632 }
6633
6634 return 1;
6635}
6636
551c1ca1 6637static char *
e3bb37b5 6638i386_scale (char *scale)
252b5132 6639{
551c1ca1
AM		 6640 offsetT val;
6641 char *save = input_line_pointer;
252b5132 6642
551c1ca1
AM		 6643 input_line_pointer = scale;
6644 val = get_absolute_expression ();
6645
6646 switch (val)
252b5132 6647 {
551c1ca1 6648 case 1:
252b5132
RH		 6649 i.log2_scale_factor = 0;
6650 break;
551c1ca1 6651 case 2:
252b5132
RH		 6652 i.log2_scale_factor = 1;
6653 break;
551c1ca1 6654 case 4:
252b5132
RH		 6655 i.log2_scale_factor = 2;
6656 break;
551c1ca1 6657 case 8:
252b5132
RH		 6658 i.log2_scale_factor = 3;
6659 break;
6660 default:
a724f0f4
JB		 6661 {
6662 char sep = *input_line_pointer;
6663
6664 *input_line_pointer = '\0';
6665 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6666 scale);
6667 *input_line_pointer = sep;
6668 input_line_pointer = save;
6669 return NULL;
6670 }
252b5132 6671 }
29b0f896 6672 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6673 {
6674 as_warn (_("scale factor of %d without an index register"),
24eab124 6675 1 << i.log2_scale_factor);
252b5132 6676 i.log2_scale_factor = 0;
252b5132 6677 }
551c1ca1
AM		 6678 scale = input_line_pointer;
6679 input_line_pointer = save;
6680 return scale;
252b5132
RH		 6681}
6682
252b5132 6683static int
e3bb37b5 6684i386_displacement (char *disp_start, char *disp_end)
252b5132 6685{
29b0f896 6686 expressionS *exp;
252b5132
RH		 6687 segT exp_seg = 0;
6688 char *save_input_line_pointer;
f3c180ae 6689 char *gotfree_input_line;
40fb9820
L		 6690 int override;
6691 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6692 int ret;
252b5132 6693
31b2323c
L		 6694 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6695 {
6696 as_bad (_("at most %d displacement operands are allowed"),
6697 MAX_MEMORY_OPERANDS);
6698 return 0;
6699 }
6700
0dfbf9d7 6701 operand_type_set (&bigdisp, 0);
40fb9820
L		 6702 if ((i.types[this_operand].bitfield.jumpabsolute)
6703 || (!current_templates->start->opcode_modifier.jump
6704 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6705 {
40fb9820 6706 bigdisp.bitfield.disp32 = 1;
e05278af 6707 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6708 if (flag_code == CODE_64BIT)
6709 {
6710 if (!override)
6711 {
6712 bigdisp.bitfield.disp32s = 1;
6713 bigdisp.bitfield.disp64 = 1;
6714 }
6715 }
6716 else if ((flag_code == CODE_16BIT) ^ override)
6717 {
6718 bigdisp.bitfield.disp32 = 0;
6719 bigdisp.bitfield.disp16 = 1;
6720 }
e05278af
JB		 6721 }
6722 else
6723 {
6724 /* For PC-relative branches, the width of the displacement
6725 is dependent upon data size, not address size. */
e05278af 6726 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6727 if (flag_code == CODE_64BIT)
6728 {
6729 if (override || i.suffix == WORD_MNEM_SUFFIX)
6730 bigdisp.bitfield.disp16 = 1;
6731 else
6732 {
6733 bigdisp.bitfield.disp32 = 1;
6734 bigdisp.bitfield.disp32s = 1;
6735 }
6736 }
6737 else
e05278af
JB		 6738 {
6739 if (!override)
6740 override = (i.suffix == (flag_code != CODE_16BIT
6741 ? WORD_MNEM_SUFFIX
6742 : LONG_MNEM_SUFFIX));
40fb9820
L		 6743 bigdisp.bitfield.disp32 = 1;
6744 if ((flag_code == CODE_16BIT) ^ override)
6745 {
6746 bigdisp.bitfield.disp32 = 0;
6747 bigdisp.bitfield.disp16 = 1;
6748 }
e05278af 6749 }
e05278af 6750 }
c6fb90c8
L		 6751 i.types[this_operand] = operand_type_or (i.types[this_operand],
6752 bigdisp);
252b5132
RH		 6753
6754 exp = &disp_expressions[i.disp_operands];
520dc8e8 6755 i.op[this_operand].disps = exp;
252b5132
RH		 6756 i.disp_operands++;
6757 save_input_line_pointer = input_line_pointer;
6758 input_line_pointer = disp_start;
6759 END_STRING_AND_SAVE (disp_end);
6760
6761#ifndef GCC_ASM_O_HACK
6762#define GCC_ASM_O_HACK 0
6763#endif
6764#if GCC_ASM_O_HACK
6765 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6766 if (i.types[this_operand].bitfield.baseIndex
24eab124 6767 && displacement_string_end[-1] == '+')
252b5132
RH		 6768 {
6769 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6770 constraint within gcc asm statements.
6771 For instance:
6772
6773 #define _set_tssldt_desc(n,addr,limit,type) \
6774 __asm__ __volatile__ ( \
6775 "movw %w2,%0\n\t" \
6776 "movw %w1,2+%0\n\t" \
6777 "rorl $16,%1\n\t" \
6778 "movb %b1,4+%0\n\t" \
6779 "movb %4,5+%0\n\t" \
6780 "movb $0,6+%0\n\t" \
6781 "movb %h1,7+%0\n\t" \
6782 "rorl $16,%1" \
6783 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6784
6785 This works great except that the output assembler ends
6786 up looking a bit weird if it turns out that there is
6787 no offset. You end up producing code that looks like:
6788
6789 #APP
6790 movw $235,(%eax)
6791 movw %dx,2+(%eax)
6792 rorl $16,%edx
6793 movb %dl,4+(%eax)
6794 movb $137,5+(%eax)
6795 movb $0,6+(%eax)
6796 movb %dh,7+(%eax)
6797 rorl $16,%edx
6798 #NO_APP
6799
47926f60 6800 So here we provide the missing zero. */
24eab124
AM		 6801
6802 *displacement_string_end = '0';
252b5132
RH		 6803 }
6804#endif
3956db08 6805 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6806 if (gotfree_input_line)
6807 input_line_pointer = gotfree_input_line;
252b5132 6808
24eab124 6809 exp_seg = expression (exp);
252b5132 6810
636c26b0
AM		 6811 SKIP_WHITESPACE ();
6812 if (*input_line_pointer)
6813 as_bad (_("junk `%s' after expression"), input_line_pointer);
6814#if GCC_ASM_O_HACK
6815 RESTORE_END_STRING (disp_end + 1);
6816#endif
636c26b0 6817 input_line_pointer = save_input_line_pointer;
636c26b0 6818 if (gotfree_input_line)
ee86248c
JB		 6819 {
6820 free (gotfree_input_line);
6821
6822 if (exp->X_op == O_constant || exp->X_op == O_register)
6823 exp->X_op = O_illegal;
6824 }
6825
6826 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6827
6828 RESTORE_END_STRING (disp_end);
6829
6830 return ret;
6831}
6832
6833static int
6834i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6835 i386_operand_type types, const char *disp_start)
6836{
6837 i386_operand_type bigdisp;
6838 int ret = 1;
636c26b0 6839
24eab124
AM		 6840 /* We do this to make sure that the section symbol is in
6841 the symbol table. We will ultimately change the relocation
47926f60 6842 to be relative to the beginning of the section. */
1ae12ab7 6843 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6844 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6845 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6846 {
636c26b0 6847 if (exp->X_op != O_symbol)
3992d3b7 6848 goto inv_disp;
636c26b0 6849
e5cb08ac 6850 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6851 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6852 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6853 exp->X_op = O_subtract;
6854 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6855 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6856 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6857 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6858 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6859 else
29b0f896 6860 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6861 }
252b5132 6862
3992d3b7
AM		 6863 else if (exp->X_op == O_absent
6864 || exp->X_op == O_illegal
ee86248c 6865 || exp->X_op == O_big)
2daf4fd8 6866 {
3992d3b7
AM		 6867 inv_disp:
6868 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6869 disp_start);
3992d3b7 6870 ret = 0;
2daf4fd8
AM		 6871 }
6872
0e1147d9
L		 6873 else if (flag_code == CODE_64BIT
6874 && !i.prefix[ADDR_PREFIX]
6875 && exp->X_op == O_constant)
6876 {
6877 /* Since displacement is signed extended to 64bit, don't allow
6878 disp32 and turn off disp32s if they are out of range. */
6879 i.types[this_operand].bitfield.disp32 = 0;
6880 if (!fits_in_signed_long (exp->X_add_number))
6881 {
6882 i.types[this_operand].bitfield.disp32s = 0;
6883 if (i.types[this_operand].bitfield.baseindex)
6884 {
6885 as_bad (_("0x%lx out range of signed 32bit displacement"),
6886 (long) exp->X_add_number);
6887 ret = 0;
6888 }
6889 }
6890 }
6891
4c63da97 6892#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6893 else if (exp->X_op != O_constant
6894 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6895 && exp_seg != absolute_section
6896 && exp_seg != text_section
6897 && exp_seg != data_section
6898 && exp_seg != bss_section
6899 && exp_seg != undefined_section
6900 && !bfd_is_com_section (exp_seg))
24eab124 6901 {
d0b47220 6902 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6903 ret = 0;
24eab124 6904 }
252b5132 6905#endif
3956db08 6906
40fb9820
L		 6907 /* Check if this is a displacement only operand. */
6908 bigdisp = i.types[this_operand];
6909 bigdisp.bitfield.disp8 = 0;
6910 bigdisp.bitfield.disp16 = 0;
6911 bigdisp.bitfield.disp32 = 0;
6912 bigdisp.bitfield.disp32s = 0;
6913 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6914 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6915 i.types[this_operand] = operand_type_and (i.types[this_operand],
6916 types);
3956db08 6917
3992d3b7 6918 return ret;
252b5132
RH		 6919}
6920
eecb386c 6921/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6922 Return 1 on success, 0 on a failure. */
6923
252b5132 6924static int
e3bb37b5 6925i386_index_check (const char *operand_string)
252b5132 6926{
3e73aa7c 6927 int ok;
fc0763e6 6928 const char *kind = "base/index";
24eab124 6929#if INFER_ADDR_PREFIX
eecb386c
AM		 6930 int fudged = 0;
6931
24eab124
AM		 6932 tryprefix:
6933#endif
3e73aa7c 6934 ok = 1;
fc0763e6
JB		 6935 if (current_templates->start->opcode_modifier.isstring
6936 && !current_templates->start->opcode_modifier.immext
6937 && (current_templates->end[-1].opcode_modifier.isstring
6938 || i.mem_operands))
6939 {
6940 /* Memory operands of string insns are special in that they only allow
6941 a single register (rDI, rSI, or rBX) as their memory address. */
6942 unsigned int expected;
6943
6944 kind = "string address";
6945
6946 if (current_templates->start->opcode_modifier.w)
6947 {
6948 i386_operand_type type = current_templates->end[-1].operand_types[0];
6949
6950 if (!type.bitfield.baseindex
6951 || ((!i.mem_operands != !intel_syntax)
6952 && current_templates->end[-1].operand_types[1]
6953 .bitfield.baseindex))
6954 type = current_templates->end[-1].operand_types[1];
6955 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6956 }
6957 else
6958 expected = 3 /* rBX */;
6959
6960 if (!i.base_reg || i.index_reg
6961 || operand_type_check (i.types[this_operand], disp))
6962 ok = -1;
6963 else if (!(flag_code == CODE_64BIT
6964 ? i.prefix[ADDR_PREFIX]
6965 ? i.base_reg->reg_type.bitfield.reg32
6966 : i.base_reg->reg_type.bitfield.reg64
6967 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6968 ? i.base_reg->reg_type.bitfield.reg32
6969 : i.base_reg->reg_type.bitfield.reg16))
6970 ok = 0;
6971 else if (i.base_reg->reg_num != expected)
6972 ok = -1;
6973
6974 if (ok < 0)
6975 {
6976 unsigned int j;
6977
6978 for (j = 0; j < i386_regtab_size; ++j)
6979 if ((flag_code == CODE_64BIT
6980 ? i.prefix[ADDR_PREFIX]
6981 ? i386_regtab[j].reg_type.bitfield.reg32
6982 : i386_regtab[j].reg_type.bitfield.reg64
6983 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6984 ? i386_regtab[j].reg_type.bitfield.reg32
6985 : i386_regtab[j].reg_type.bitfield.reg16)
6986 && i386_regtab[j].reg_num == expected)
6987 break;
9c2799c2 6988 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6989 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6990 operand_string,
6991 intel_syntax ? '[' : '(',
6992 register_prefix,
6993 i386_regtab[j].reg_name,
6994 intel_syntax ? ']' : ')');
6995 ok = 1;
6996 }
6997 }
6998 else if (flag_code == CODE_64BIT)
64e74474 6999 {
64e74474 7000 if ((i.base_reg
40fb9820
L		 7001 && ((i.prefix[ADDR_PREFIX] == 0
7002 && !i.base_reg->reg_type.bitfield.reg64)
7003 || (i.prefix[ADDR_PREFIX]
7004 && !i.base_reg->reg_type.bitfield.reg32))
7005 && (i.index_reg
9a04903e
JB		 7006 || i.base_reg->reg_num !=
7007 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7008 || (i.index_reg
40fb9820
L		 7009 && (!i.index_reg->reg_type.bitfield.baseindex
7010 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7011 && i.index_reg->reg_num != RegRiz
7012 && !i.index_reg->reg_type.bitfield.reg64
7013 )
40fb9820 7014 || (i.prefix[ADDR_PREFIX]
db51cc60 7015 && i.index_reg->reg_num != RegEiz
40fb9820 7016 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7017 ok = 0;
3e73aa7c
JH		 7018 }
7019 else
7020 {
7021 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7022 {
7023 /* 16bit checks. */
7024 if ((i.base_reg
40fb9820
L		 7025 && (!i.base_reg->reg_type.bitfield.reg16
7026 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7027 || (i.index_reg
40fb9820
L		 7028 && (!i.index_reg->reg_type.bitfield.reg16
7029 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7030 || !(i.base_reg
7031 && i.base_reg->reg_num < 6
7032 && i.index_reg->reg_num >= 6
7033 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7034 ok = 0;
7035 }
7036 else
e5cb08ac 7037 {
3e73aa7c
JH		 7038 /* 32bit checks. */
7039 if ((i.base_reg
40fb9820 7040 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7041 || (i.index_reg
db51cc60
L		 7042 && ((!i.index_reg->reg_type.bitfield.reg32
7043 && i.index_reg->reg_num != RegEiz)
40fb9820 7044 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7045 ok = 0;
3e73aa7c
JH		 7046 }
7047 }
7048 if (!ok)
24eab124
AM		 7049 {
7050#if INFER_ADDR_PREFIX
fc0763e6 7051 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7052 {
7053 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7054 i.prefixes += 1;
b23bac36
AM		 7055 /* Change the size of any displacement too. At most one of
7056 Disp16 or Disp32 is set.
7057 FIXME. There doesn't seem to be any real need for separate
7058 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7059 Removing them would probably clean up the code quite a lot. */
4eed87de 7060 if (flag_code != CODE_64BIT
40fb9820
L		 7061 && (i.types[this_operand].bitfield.disp16
7062 || i.types[this_operand].bitfield.disp32))
7063 i.types[this_operand]
c6fb90c8 7064 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7065 fudged = 1;
24eab124
AM		 7066 goto tryprefix;
7067 }
eecb386c 7068 if (fudged)
fc0763e6
JB		 7069 as_bad (_("`%s' is not a valid %s expression"),
7070 operand_string,
7071 kind);
eecb386c 7072 else
c388dee8 7073#endif
fc0763e6 7074 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7075 operand_string,
fc0763e6
JB		 7076 flag_code_names[i.prefix[ADDR_PREFIX]
7077 ? flag_code == CODE_32BIT
7078 ? CODE_16BIT
7079 : CODE_32BIT
7080 : flag_code],
7081 kind);
24eab124 7082 }
20f0a1fc 7083 return ok;
24eab124 7084}
252b5132 7085
fc0763e6 7086/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7087 on error. */
252b5132 7088
252b5132 7089static int
a7619375 7090i386_att_operand (char *operand_string)
252b5132 7091{
af6bdddf
AM		 7092 const reg_entry *r;
7093 char *end_op;
24eab124 7094 char *op_string = operand_string;
252b5132 7095
24eab124 7096 if (is_space_char (*op_string))
252b5132
RH		 7097 ++op_string;
7098
24eab124 7099 /* We check for an absolute prefix (differentiating,
47926f60 7100 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7101 if (*op_string == ABSOLUTE_PREFIX)
7102 {
7103 ++op_string;
7104 if (is_space_char (*op_string))
7105 ++op_string;
40fb9820 7106 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7107 }
252b5132 7108
47926f60 7109 /* Check if operand is a register. */
4d1bb795 7110 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7111 {
40fb9820
L		 7112 i386_operand_type temp;
7113
24eab124
AM		 7114 /* Check for a segment override by searching for ':' after a
7115 segment register. */
7116 op_string = end_op;
7117 if (is_space_char (*op_string))
7118 ++op_string;
40fb9820
L		 7119 if (*op_string == ':'
7120 && (r->reg_type.bitfield.sreg2
7121 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7122 {
7123 switch (r->reg_num)
7124 {
7125 case 0:
7126 i.seg[i.mem_operands] = &es;
7127 break;
7128 case 1:
7129 i.seg[i.mem_operands] = &cs;
7130 break;
7131 case 2:
7132 i.seg[i.mem_operands] = &ss;
7133 break;
7134 case 3:
7135 i.seg[i.mem_operands] = &ds;
7136 break;
7137 case 4:
7138 i.seg[i.mem_operands] = &fs;
7139 break;
7140 case 5:
7141 i.seg[i.mem_operands] = &gs;
7142 break;
7143 }
252b5132 7144
24eab124 7145 /* Skip the ':' and whitespace. */
252b5132
RH		 7146 ++op_string;
7147 if (is_space_char (*op_string))
24eab124 7148 ++op_string;
252b5132 7149
24eab124
AM		 7150 if (!is_digit_char (*op_string)
7151 && !is_identifier_char (*op_string)
7152 && *op_string != '('
7153 && *op_string != ABSOLUTE_PREFIX)
7154 {
7155 as_bad (_("bad memory operand `%s'"), op_string);
7156 return 0;
7157 }
47926f60 7158 /* Handle case of %es:*foo. */
24eab124
AM		 7159 if (*op_string == ABSOLUTE_PREFIX)
7160 {
7161 ++op_string;
7162 if (is_space_char (*op_string))
7163 ++op_string;
40fb9820 7164 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7165 }
7166 goto do_memory_reference;
7167 }
7168 if (*op_string)
7169 {
d0b47220 7170 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7171 return 0;
7172 }
40fb9820
L		 7173 temp = r->reg_type;
7174 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7175 i.types[this_operand] = operand_type_or (i.types[this_operand],
7176 temp);
7d5e4556 7177 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7178 i.op[this_operand].regs = r;
24eab124
AM		 7179 i.reg_operands++;
7180 }
af6bdddf
AM		 7181 else if (*op_string == REGISTER_PREFIX)
7182 {
7183 as_bad (_("bad register name `%s'"), op_string);
7184 return 0;
7185 }
24eab124 7186 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7187 {
24eab124 7188 ++op_string;
40fb9820 7189 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7190 {
d0b47220 7191 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7192 return 0;
7193 }
7194 if (!i386_immediate (op_string))
7195 return 0;
7196 }
7197 else if (is_digit_char (*op_string)
7198 || is_identifier_char (*op_string)
e5cb08ac 7199 || *op_string == '(')
24eab124 7200 {
47926f60 7201 /* This is a memory reference of some sort. */
af6bdddf 7202 char *base_string;
252b5132 7203
47926f60 7204 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7205 char *displacement_string_start;
7206 char *displacement_string_end;
252b5132 7207
24eab124 7208 do_memory_reference:
24eab124 7209 if ((i.mem_operands == 1
40fb9820 7210 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7211 || i.mem_operands == 2)
7212 {
7213 as_bad (_("too many memory references for `%s'"),
7214 current_templates->start->name);
7215 return 0;
7216 }
252b5132 7217
24eab124
AM		 7218 /* Check for base index form. We detect the base index form by
7219 looking for an ')' at the end of the operand, searching
7220 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7221 after the '('. */
af6bdddf 7222 base_string = op_string + strlen (op_string);
c3332e24 7223
af6bdddf
AM		 7224 --base_string;
7225 if (is_space_char (*base_string))
7226 --base_string;
252b5132 7227
47926f60 7228 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7229 displacement_string_start = op_string;
7230 displacement_string_end = base_string + 1;
252b5132 7231
24eab124
AM		 7232 if (*base_string == ')')
7233 {
af6bdddf 7234 char *temp_string;
24eab124
AM		 7235 unsigned int parens_balanced = 1;
7236 /* We've already checked that the number of left & right ()'s are
47926f60 7237 equal, so this loop will not be infinite. */
24eab124
AM		 7238 do
7239 {
7240 base_string--;
7241 if (*base_string == ')')
7242 parens_balanced++;
7243 if (*base_string == '(')
7244 parens_balanced--;
7245 }
7246 while (parens_balanced);
c3332e24 7247
af6bdddf 7248 temp_string = base_string;
c3332e24 7249
24eab124 7250 /* Skip past '(' and whitespace. */
252b5132
RH		 7251 ++base_string;
7252 if (is_space_char (*base_string))
24eab124 7253 ++base_string;
252b5132 7254
af6bdddf 7255 if (*base_string == ','
4eed87de
AM		 7256 || ((i.base_reg = parse_register (base_string, &end_op))
7257 != NULL))
252b5132 7258 {
af6bdddf 7259 displacement_string_end = temp_string;
252b5132 7260
40fb9820 7261 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7262
af6bdddf 7263 if (i.base_reg)
24eab124 7264 {
24eab124
AM		 7265 base_string = end_op;
7266 if (is_space_char (*base_string))
7267 ++base_string;
af6bdddf
AM		 7268 }
7269
7270 /* There may be an index reg or scale factor here. */
7271 if (*base_string == ',')
7272 {
7273 ++base_string;
7274 if (is_space_char (*base_string))
7275 ++base_string;
7276
4eed87de
AM		 7277 if ((i.index_reg = parse_register (base_string, &end_op))
7278 != NULL)
24eab124 7279 {
af6bdddf 7280 base_string = end_op;
24eab124
AM		 7281 if (is_space_char (*base_string))
7282 ++base_string;
af6bdddf
AM		 7283 if (*base_string == ',')
7284 {
7285 ++base_string;
7286 if (is_space_char (*base_string))
7287 ++base_string;
7288 }
e5cb08ac 7289 else if (*base_string != ')')
af6bdddf 7290 {
4eed87de
AM		 7291 as_bad (_("expecting `,' or `)' "
7292 "after index register in `%s'"),
af6bdddf
AM		 7293 operand_string);
7294 return 0;
7295 }
24eab124 7296 }
af6bdddf 7297 else if (*base_string == REGISTER_PREFIX)
24eab124 7298 {
af6bdddf 7299 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7300 return 0;
7301 }
252b5132 7302
47926f60 7303 /* Check for scale factor. */
551c1ca1 7304 if (*base_string != ')')
af6bdddf 7305 {
551c1ca1
AM		 7306 char *end_scale = i386_scale (base_string);
7307
7308 if (!end_scale)
af6bdddf 7309 return 0;
24eab124 7310
551c1ca1 7311 base_string = end_scale;
af6bdddf
AM		 7312 if (is_space_char (*base_string))
7313 ++base_string;
7314 if (*base_string != ')')
7315 {
4eed87de
AM		 7316 as_bad (_("expecting `)' "
7317 "after scale factor in `%s'"),
af6bdddf
AM		 7318 operand_string);
7319 return 0;
7320 }
7321 }
7322 else if (!i.index_reg)
24eab124 7323 {
4eed87de
AM		 7324 as_bad (_("expecting index register or scale factor "
7325 "after `,'; got '%c'"),
af6bdddf 7326 *base_string);
24eab124
AM		 7327 return 0;
7328 }
7329 }
af6bdddf 7330 else if (*base_string != ')')
24eab124 7331 {
4eed87de
AM		 7332 as_bad (_("expecting `,' or `)' "
7333 "after base register in `%s'"),
af6bdddf 7334 operand_string);
24eab124
AM		 7335 return 0;
7336 }
c3332e24 7337 }
af6bdddf 7338 else if (*base_string == REGISTER_PREFIX)
c3332e24 7339 {
af6bdddf 7340 as_bad (_("bad register name `%s'"), base_string);
24eab124 7341 return 0;
c3332e24 7342 }
24eab124
AM		 7343 }
7344
7345 /* If there's an expression beginning the operand, parse it,
7346 assuming displacement_string_start and
7347 displacement_string_end are meaningful. */
7348 if (displacement_string_start != displacement_string_end)
7349 {
7350 if (!i386_displacement (displacement_string_start,
7351 displacement_string_end))
7352 return 0;
7353 }
7354
7355 /* Special case for (%dx) while doing input/output op. */
7356 if (i.base_reg
0dfbf9d7
L		 7357 && operand_type_equal (&i.base_reg->reg_type,
7358 &reg16_inoutportreg)
24eab124
AM		 7359 && i.index_reg == 0
7360 && i.log2_scale_factor == 0
7361 && i.seg[i.mem_operands] == 0
40fb9820 7362 && !operand_type_check (i.types[this_operand], disp))
24eab124 7363 {
65da13b5 7364 i.types[this_operand] = inoutportreg;
24eab124
AM		 7365 return 1;
7366 }
7367
eecb386c
AM		 7368 if (i386_index_check (operand_string) == 0)
7369 return 0;
5c07affc 7370 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7371 i.mem_operands++;
7372 }
7373 else
ce8a8b2f
AM		 7374 {
7375 /* It's not a memory operand; argh! */
24eab124
AM		 7376 as_bad (_("invalid char %s beginning operand %d `%s'"),
7377 output_invalid (*op_string),
7378 this_operand + 1,
7379 op_string);
7380 return 0;
7381 }
47926f60 7382 return 1; /* Normal return. */
252b5132
RH		 7383}
7384\f
ee7fcc42
AM		 7385/* md_estimate_size_before_relax()
7386
7387 Called just before relax() for rs_machine_dependent frags. The x86
7388 assembler uses these frags to handle variable size jump
7389 instructions.
7390
7391 Any symbol that is now undefined will not become defined.
7392 Return the correct fr_subtype in the frag.
7393 Return the initial "guess for variable size of frag" to caller.
7394 The guess is actually the growth beyond the fixed part. Whatever
7395 we do to grow the fixed or variable part contributes to our
7396 returned value. */
7397
252b5132
RH		 7398int
7399md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7400 fragS *fragP;
7401 segT segment;
252b5132 7402{
252b5132 7403 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7404 check for un-relaxable symbols. On an ELF system, we can't relax
7405 an externally visible symbol, because it may be overridden by a
7406 shared library. */
7407 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7408#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7409 || (IS_ELF
31312f95 7410 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7411 || S_IS_WEAK (fragP->fr_symbol)
7412 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7413 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7414#endif
7415#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7416 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7417 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7418#endif
7419 )
252b5132 7420 {
b98ef147
AM		 7421 /* Symbol is undefined in this segment, or we need to keep a
7422 reloc so that weak symbols can be overridden. */
7423 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7424 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7425 unsigned char *opcode;
7426 int old_fr_fix;
f6af82bd 7427
ee7fcc42 7428 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7429 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7430 else if (size == 2)
f6af82bd
AM		 7431 reloc_type = BFD_RELOC_16_PCREL;
7432 else
7433 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7434
ee7fcc42
AM		 7435 old_fr_fix = fragP->fr_fix;
7436 opcode = (unsigned char *) fragP->fr_opcode;
7437
fddf5b5b 7438 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7439 {
fddf5b5b
AM		 7440 case UNCOND_JUMP:
7441 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7442 opcode[0] = 0xe9;
252b5132 7443 fragP->fr_fix += size;
062cd5e7
AS		 7444 fix_new (fragP, old_fr_fix, size,
7445 fragP->fr_symbol,
7446 fragP->fr_offset, 1,
7447 reloc_type);
252b5132
RH		 7448 break;
7449
fddf5b5b 7450 case COND_JUMP86:
412167cb
AM		 7451 if (size == 2
7452 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7453 {
7454 /* Negate the condition, and branch past an
7455 unconditional jump. */
7456 opcode[0] ^= 1;
7457 opcode[1] = 3;
7458 /* Insert an unconditional jump. */
7459 opcode[2] = 0xe9;
7460 /* We added two extra opcode bytes, and have a two byte
7461 offset. */
7462 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7463 fix_new (fragP, old_fr_fix + 2, 2,
7464 fragP->fr_symbol,
7465 fragP->fr_offset, 1,
7466 reloc_type);
fddf5b5b
AM		 7467 break;
7468 }
7469 /* Fall through. */
7470
7471 case COND_JUMP:
412167cb
AM		 7472 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7473 {
3e02c1cc
AM		 7474 fixS *fixP;
7475
412167cb 7476 fragP->fr_fix += 1;
3e02c1cc
AM		 7477 fixP = fix_new (fragP, old_fr_fix, 1,
7478 fragP->fr_symbol,
7479 fragP->fr_offset, 1,
7480 BFD_RELOC_8_PCREL);
7481 fixP->fx_signed = 1;
412167cb
AM		 7482 break;
7483 }
93c2a809 7484
24eab124 7485 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7486 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7487 opcode[1] = opcode[0] + 0x10;
f6af82bd 7488 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7489 /* We've added an opcode byte. */
7490 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7491 fix_new (fragP, old_fr_fix + 1, size,
7492 fragP->fr_symbol,
7493 fragP->fr_offset, 1,
7494 reloc_type);
252b5132 7495 break;
fddf5b5b
AM		 7496
7497 default:
7498 BAD_CASE (fragP->fr_subtype);
7499 break;
252b5132
RH		 7500 }
7501 frag_wane (fragP);
ee7fcc42 7502 return fragP->fr_fix - old_fr_fix;
252b5132 7503 }
93c2a809 7504
93c2a809
AM		 7505 /* Guess size depending on current relax state. Initially the relax
7506 state will correspond to a short jump and we return 1, because
7507 the variable part of the frag (the branch offset) is one byte
7508 long. However, we can relax a section more than once and in that
7509 case we must either set fr_subtype back to the unrelaxed state,
7510 or return the value for the appropriate branch. */
7511 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7512}
7513
47926f60
KH		 7514/* Called after relax() is finished.
7515
7516 In: Address of frag.
7517 fr_type == rs_machine_dependent.
7518 fr_subtype is what the address relaxed to.
7519
7520 Out: Any fixSs and constants are set up.
7521 Caller will turn frag into a ".space 0". */
7522
252b5132
RH		 7523void
7524md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7525 bfd *abfd ATTRIBUTE_UNUSED;
7526 segT sec ATTRIBUTE_UNUSED;
29b0f896 7527 fragS *fragP;
252b5132 7528{
29b0f896 7529 unsigned char *opcode;
252b5132 7530 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7531 offsetT target_address;
7532 offsetT opcode_address;
252b5132 7533 unsigned int extension = 0;
847f7ad4 7534 offsetT displacement_from_opcode_start;
252b5132
RH		 7535
7536 opcode = (unsigned char *) fragP->fr_opcode;
7537
47926f60 7538 /* Address we want to reach in file space. */
252b5132 7539 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7540
47926f60 7541 /* Address opcode resides at in file space. */
252b5132
RH		 7542 opcode_address = fragP->fr_address + fragP->fr_fix;
7543
47926f60 7544 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7545 displacement_from_opcode_start = target_address - opcode_address;
7546
fddf5b5b 7547 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7548 {
47926f60
KH		 7549 /* Don't have to change opcode. */
7550 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7551 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7552 }
7553 else
7554 {
7555 if (no_cond_jump_promotion
7556 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7557 as_warn_where (fragP->fr_file, fragP->fr_line,
7558 _("long jump required"));
252b5132 7559
fddf5b5b
AM		 7560 switch (fragP->fr_subtype)
7561 {
7562 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7563 extension = 4; /* 1 opcode + 4 displacement */
7564 opcode[0] = 0xe9;
7565 where_to_put_displacement = &opcode[1];
7566 break;
252b5132 7567
fddf5b5b
AM		 7568 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7569 extension = 2; /* 1 opcode + 2 displacement */
7570 opcode[0] = 0xe9;
7571 where_to_put_displacement = &opcode[1];
7572 break;
252b5132 7573
fddf5b5b
AM		 7574 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7575 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7576 extension = 5; /* 2 opcode + 4 displacement */
7577 opcode[1] = opcode[0] + 0x10;
7578 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7579 where_to_put_displacement = &opcode[2];
7580 break;
252b5132 7581
fddf5b5b
AM		 7582 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7583 extension = 3; /* 2 opcode + 2 displacement */
7584 opcode[1] = opcode[0] + 0x10;
7585 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7586 where_to_put_displacement = &opcode[2];
7587 break;
252b5132 7588
fddf5b5b
AM		 7589 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7590 extension = 4;
7591 opcode[0] ^= 1;
7592 opcode[1] = 3;
7593 opcode[2] = 0xe9;
7594 where_to_put_displacement = &opcode[3];
7595 break;
7596
7597 default:
7598 BAD_CASE (fragP->fr_subtype);
7599 break;
7600 }
252b5132 7601 }
fddf5b5b 7602
7b81dfbb
AJ		 7603 /* If size if less then four we are sure that the operand fits,
7604 but if it's 4, then it could be that the displacement is larger
7605 then -/+ 2GB. */
7606 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7607 && object_64bit
7608 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7609 + ((addressT) 1 << 31))
7610 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7611 {
7612 as_bad_where (fragP->fr_file, fragP->fr_line,
7613 _("jump target out of range"));
7614 /* Make us emit 0. */
7615 displacement_from_opcode_start = extension;
7616 }
47926f60 7617 /* Now put displacement after opcode. */
252b5132
RH		 7618 md_number_to_chars ((char *) where_to_put_displacement,
7619 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7620 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7621 fragP->fr_fix += extension;
7622}
7623\f
252b5132
RH		 7624/* Apply a fixup (fixS) to segment data, once it has been determined
7625 by our caller that we have all the info we need to fix it up.
7626
7627 On the 386, immediates, displacements, and data pointers are all in
7628 the same (little-endian) format, so we don't need to care about which
7629 we are handling. */
7630
94f592af 7631void
55cf6793 7632md_apply_fix (fixP, valP, seg)
47926f60
KH		 7633 /* The fix we're to put in. */
7634 fixS *fixP;
47926f60 7635 /* Pointer to the value of the bits. */
c6682705 7636 valueT *valP;
47926f60
KH		 7637 /* Segment fix is from. */
7638 segT seg ATTRIBUTE_UNUSED;
252b5132 7639{
94f592af 7640 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7641 valueT value = *valP;
252b5132 7642
f86103b7 7643#if !defined (TE_Mach)
93382f6d
AM		 7644 if (fixP->fx_pcrel)
7645 {
7646 switch (fixP->fx_r_type)
7647 {
5865bb77
ILT		 7648 default:
7649 break;
7650
d6ab8113
JB		 7651 case BFD_RELOC_64:
7652 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7653 break;
93382f6d 7654 case BFD_RELOC_32:
ae8887b5 7655 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7656 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7657 break;
7658 case BFD_RELOC_16:
7659 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7660 break;
7661 case BFD_RELOC_8:
7662 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7663 break;
7664 }
7665 }
252b5132 7666
a161fe53 7667 if (fixP->fx_addsy != NULL
31312f95 7668 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7669 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7670 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7671 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7672 && !use_rela_relocations)
252b5132 7673 {
31312f95
AM		 7674 /* This is a hack. There should be a better way to handle this.
7675 This covers for the fact that bfd_install_relocation will
7676 subtract the current location (for partial_inplace, PC relative
7677 relocations); see more below. */
252b5132 7678#ifndef OBJ_AOUT
718ddfc0 7679 if (IS_ELF
252b5132
RH		 7680#ifdef TE_PE
7681 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7682#endif
7683 )
7684 value += fixP->fx_where + fixP->fx_frag->fr_address;
7685#endif
7686#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7687 if (IS_ELF)
252b5132 7688 {
6539b54b 7689 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7690
6539b54b 7691 if ((sym_seg == seg
2f66722d 7692 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7693 && sym_seg != absolute_section))
af65af87 7694 && !generic_force_reloc (fixP))
2f66722d
AM		 7695 {
7696 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7697 bfd_install_relocation subtracts them out again. I think
7698 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7699 it. FIXME. */
7700 value += fixP->fx_where + fixP->fx_frag->fr_address;
7701 }
252b5132
RH		 7702 }
7703#endif
7704#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7705 /* For some reason, the PE format does not store a
7706 section address offset for a PC relative symbol. */
7707 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7708 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7709 value += md_pcrel_from (fixP);
7710#endif
7711 }
fbeb56a4
DK		 7712#if defined (OBJ_COFF) && defined (TE_PE)
7713 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7714 {
7715 value -= S_GET_VALUE (fixP->fx_addsy);
7716 }
7717#endif
252b5132
RH		 7718
7719 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7720 and we must not disappoint it. */
252b5132 7721#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7722 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7723 switch (fixP->fx_r_type)
7724 {
7725 case BFD_RELOC_386_PLT32:
3e73aa7c 7726 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7727 /* Make the jump instruction point to the address of the operand. At
7728 runtime we merely add the offset to the actual PLT entry. */
7729 value = -4;
7730 break;
31312f95 7731
13ae64f3
JJ		 7732 case BFD_RELOC_386_TLS_GD:
7733 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7734 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7735 case BFD_RELOC_386_TLS_IE:
7736 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7737 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7738 case BFD_RELOC_X86_64_TLSGD:
7739 case BFD_RELOC_X86_64_TLSLD:
7740 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7741 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7742 value = 0; /* Fully resolved at runtime. No addend. */
7743 /* Fallthrough */
7744 case BFD_RELOC_386_TLS_LE:
7745 case BFD_RELOC_386_TLS_LDO_32:
7746 case BFD_RELOC_386_TLS_LE_32:
7747 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7748 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7749 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7750 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7751 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7752 break;
7753
67a4f2b7
AO		 7754 case BFD_RELOC_386_TLS_DESC_CALL:
7755 case BFD_RELOC_X86_64_TLSDESC_CALL:
7756 value = 0; /* Fully resolved at runtime. No addend. */
7757 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7758 fixP->fx_done = 0;
7759 return;
7760
00f7efb6
JJ		 7761 case BFD_RELOC_386_GOT32:
7762 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7763 value = 0; /* Fully resolved at runtime. No addend. */
7764 break;
47926f60
KH		 7765
7766 case BFD_RELOC_VTABLE_INHERIT:
7767 case BFD_RELOC_VTABLE_ENTRY:
7768 fixP->fx_done = 0;
94f592af 7769 return;
47926f60
KH		 7770
7771 default:
7772 break;
7773 }
7774#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7775 *valP = value;
f86103b7 7776#endif /* !defined (TE_Mach) */
3e73aa7c 7777
3e73aa7c 7778 /* Are we finished with this relocation now? */
c6682705 7779 if (fixP->fx_addsy == NULL)
3e73aa7c 7780 fixP->fx_done = 1;
fbeb56a4
DK		 7781#if defined (OBJ_COFF) && defined (TE_PE)
7782 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7783 {
7784 fixP->fx_done = 0;
7785 /* Remember value for tc_gen_reloc. */
7786 fixP->fx_addnumber = value;
7787 /* Clear out the frag for now. */
7788 value = 0;
7789 }
7790#endif
3e73aa7c
JH		 7791 else if (use_rela_relocations)
7792 {
7793 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7794 /* Remember value for tc_gen_reloc. */
7795 fixP->fx_addnumber = value;
3e73aa7c
JH		 7796 value = 0;
7797 }
f86103b7 7798
94f592af 7799 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7800}
252b5132 7801\f
252b5132 7802char *
499ac353 7803md_atof (int type, char *litP, int *sizeP)
252b5132 7804{
499ac353
NC		 7805 /* This outputs the LITTLENUMs in REVERSE order;
7806 in accord with the bigendian 386. */
7807 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7808}
7809\f
2d545b82 7810static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7811
252b5132 7812static char *
e3bb37b5 7813output_invalid (int c)
252b5132 7814{
3882b010 7815 if (ISPRINT (c))
f9f21a03
L		 7816 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7817 "'%c'", c);
252b5132 7818 else
f9f21a03 7819 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7820 "(0x%x)", (unsigned char) c);
252b5132
RH		 7821 return output_invalid_buf;
7822}
7823
af6bdddf 7824/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7825
7826static const reg_entry *
4d1bb795 7827parse_real_register (char *reg_string, char **end_op)
252b5132 7828{
af6bdddf
AM		 7829 char *s = reg_string;
7830 char *p;
252b5132
RH		 7831 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7832 const reg_entry *r;
7833
7834 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7835 if (*s == REGISTER_PREFIX)
7836 ++s;
7837
7838 if (is_space_char (*s))
7839 ++s;
7840
7841 p = reg_name_given;
af6bdddf 7842 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7843 {
7844 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7845 return (const reg_entry *) NULL;
7846 s++;
252b5132
RH		 7847 }
7848
6588847e
DN		 7849 /* For naked regs, make sure that we are not dealing with an identifier.
7850 This prevents confusing an identifier like `eax_var' with register
7851 `eax'. */
7852 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7853 return (const reg_entry *) NULL;
7854
af6bdddf 7855 *end_op = s;
252b5132
RH		 7856
7857 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7858
5f47d35b 7859 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7860 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7861 {
5f47d35b
AM		 7862 if (is_space_char (*s))
7863 ++s;
7864 if (*s == '(')
7865 {
af6bdddf 7866 ++s;
5f47d35b
AM		 7867 if (is_space_char (*s))
7868 ++s;
7869 if (*s >= '0' && *s <= '7')
7870 {
db557034 7871 int fpr = *s - '0';
af6bdddf 7872 ++s;
5f47d35b
AM		 7873 if (is_space_char (*s))
7874 ++s;
7875 if (*s == ')')
7876 {
7877 *end_op = s + 1;
1e9cc1c2 7878 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7879 know (r);
7880 return r + fpr;
5f47d35b 7881 }
5f47d35b 7882 }
47926f60 7883 /* We have "%st(" then garbage. */
5f47d35b
AM		 7884 return (const reg_entry *) NULL;
7885 }
7886 }
7887
a60de03c
JB		 7888 if (r == NULL || allow_pseudo_reg)
7889 return r;
7890
0dfbf9d7 7891 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7892 return (const reg_entry *) NULL;
7893
192dc9c6
JB		 7894 if ((r->reg_type.bitfield.reg32
7895 || r->reg_type.bitfield.sreg3
7896 || r->reg_type.bitfield.control
7897 || r->reg_type.bitfield.debug
7898 || r->reg_type.bitfield.test)
7899 && !cpu_arch_flags.bitfield.cpui386)
7900 return (const reg_entry *) NULL;
7901
309d3373
JB		 7902 if (r->reg_type.bitfield.floatreg
7903 && !cpu_arch_flags.bitfield.cpu8087
7904 && !cpu_arch_flags.bitfield.cpu287
7905 && !cpu_arch_flags.bitfield.cpu387)
7906 return (const reg_entry *) NULL;
7907
192dc9c6
JB		 7908 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7909 return (const reg_entry *) NULL;
7910
7911 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7912 return (const reg_entry *) NULL;
7913
40f12533
L		 7914 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7915 return (const reg_entry *) NULL;
7916
db51cc60 7917 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7918 if (!allow_index_reg
db51cc60
L		 7919 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7920 return (const reg_entry *) NULL;
7921
a60de03c
JB		 7922 if (((r->reg_flags & (RegRex64 | RegRex))
7923 || r->reg_type.bitfield.reg64)
40fb9820 7924 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7925 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7926 && flag_code != CODE_64BIT)
20f0a1fc 7927 return (const reg_entry *) NULL;
1ae00879 7928
b7240065
JB		 7929 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7930 return (const reg_entry *) NULL;
7931
252b5132
RH		 7932 return r;
7933}
4d1bb795
JB		 7934
7935/* REG_STRING starts *before* REGISTER_PREFIX. */
7936
7937static const reg_entry *
7938parse_register (char *reg_string, char **end_op)
7939{
7940 const reg_entry *r;
7941
7942 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7943 r = parse_real_register (reg_string, end_op);
7944 else
7945 r = NULL;
7946 if (!r)
7947 {
7948 char *save = input_line_pointer;
7949 char c;
7950 symbolS *symbolP;
7951
7952 input_line_pointer = reg_string;
7953 c = get_symbol_end ();
7954 symbolP = symbol_find (reg_string);
7955 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7956 {
7957 const expressionS *e = symbol_get_value_expression (symbolP);
7958
7959 know (e->X_op == O_register);
4eed87de 7960 know (e->X_add_number >= 0
c3fe08fa 7961 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7962 r = i386_regtab + e->X_add_number;
7963 *end_op = input_line_pointer;
7964 }
7965 *input_line_pointer = c;
7966 input_line_pointer = save;
7967 }
7968 return r;
7969}
7970
7971int
7972i386_parse_name (char *name, expressionS *e, char *nextcharP)
7973{
7974 const reg_entry *r;
7975 char *end = input_line_pointer;
7976
7977 *end = *nextcharP;
7978 r = parse_register (name, &input_line_pointer);
7979 if (r && end <= input_line_pointer)
7980 {
7981 *nextcharP = *input_line_pointer;
7982 *input_line_pointer = 0;
7983 e->X_op = O_register;
7984 e->X_add_number = r - i386_regtab;
7985 return 1;
7986 }
7987 input_line_pointer = end;
7988 *end = 0;
ee86248c 7989 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7990}
7991
7992void
7993md_operand (expressionS *e)
7994{
ee86248c
JB		 7995 char *end;
7996 const reg_entry *r;
4d1bb795 7997
ee86248c
JB		 7998 switch (*input_line_pointer)
7999 {
8000 case REGISTER_PREFIX:
8001 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8002 if (r)
8003 {
8004 e->X_op = O_register;
8005 e->X_add_number = r - i386_regtab;
8006 input_line_pointer = end;
8007 }
ee86248c
JB		 8008 break;
8009
8010 case '[':
9c2799c2 8011 gas_assert (intel_syntax);
ee86248c
JB		 8012 end = input_line_pointer++;
8013 expression (e);
8014 if (*input_line_pointer == ']')
8015 {
8016 ++input_line_pointer;
8017 e->X_op_symbol = make_expr_symbol (e);
8018 e->X_add_symbol = NULL;
8019 e->X_add_number = 0;
8020 e->X_op = O_index;
8021 }
8022 else
8023 {
8024 e->X_op = O_absent;
8025 input_line_pointer = end;
8026 }
8027 break;
4d1bb795
JB		 8028 }
8029}
8030
252b5132 8031\f
4cc782b5 8032#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8033const char *md_shortopts = "kVQ:sqn";
252b5132 8034#else
12b55ccc 8035const char *md_shortopts = "qn";
252b5132 8036#endif
6e0b89ee 8037
3e73aa7c 8038#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8039#define OPTION_64 (OPTION_MD_BASE + 1)
8040#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8041#define OPTION_MARCH (OPTION_MD_BASE + 3)
8042#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8043#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8044#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8045#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8046#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8047#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8048#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8049#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
539f890d 8050#define OPTION_MAVXSCALAR (OPTION_MSSE_CHECK + 11)
b3b91714 8051
99ad8390
NC		 8052struct option md_longopts[] =
8053{
3e73aa7c 8054 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8055#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8056 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8057 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 8058#endif
b3b91714 8059 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8060 {"march", required_argument, NULL, OPTION_MARCH},
8061 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8062 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8063 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8064 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8065 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8066 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8067 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8068 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8069 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8070 {NULL, no_argument, NULL, 0}
8071};
8072size_t md_longopts_size = sizeof (md_longopts);
8073
8074int
9103f4f4 8075md_parse_option (int c, char *arg)
252b5132 8076{
91d6fa6a 8077 unsigned int j;
6305a203 8078 char *arch, *next;
9103f4f4 8079
252b5132
RH		 8080 switch (c)
8081 {
12b55ccc
L		 8082 case 'n':
8083 optimize_align_code = 0;
8084 break;
8085
a38cf1db
AM		 8086 case 'q':
8087 quiet_warnings = 1;
252b5132
RH		 8088 break;
8089
8090#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8091 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8092 should be emitted or not. FIXME: Not implemented. */
8093 case 'Q':
252b5132
RH		 8094 break;
8095
8096 /* -V: SVR4 argument to print version ID. */
8097 case 'V':
8098 print_version_id ();
8099 break;
8100
a38cf1db
AM		 8101 /* -k: Ignore for FreeBSD compatibility. */
8102 case 'k':
252b5132 8103 break;
4cc782b5
ILT		 8104
8105 case 's':
8106 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8107 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8108 break;
99ad8390 8109#endif
321098a5
L		 8110#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8111 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8112 case OPTION_64:
8113 {
8114 const char **list, **l;
8115
3e73aa7c
JH		 8116 list = bfd_target_list ();
8117 for (l = list; *l != NULL; l++)
8620418b 8118 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8119 || strcmp (*l, "coff-x86-64") == 0
8120 || strcmp (*l, "pe-x86-64") == 0
8121 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8122 {
8123 default_arch = "x86_64";
8124 break;
8125 }
3e73aa7c 8126 if (*l == NULL)
6e0b89ee 8127 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8128 free (list);
8129 }
8130 break;
8131#endif
252b5132 8132
6e0b89ee
AM		 8133 case OPTION_32:
8134 default_arch = "i386";
8135 break;
8136
b3b91714
AM		 8137 case OPTION_DIVIDE:
8138#ifdef SVR4_COMMENT_CHARS
8139 {
8140 char *n, *t;
8141 const char *s;
8142
8143 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8144 t = n;
8145 for (s = i386_comment_chars; *s != '\0'; s++)
8146 if (*s != '/')
8147 *t++ = *s;
8148 *t = '\0';
8149 i386_comment_chars = n;
8150 }
8151#endif
8152 break;
8153
9103f4f4 8154 case OPTION_MARCH:
6305a203
L		 8155 arch = xstrdup (arg);
8156 do
9103f4f4 8157 {
6305a203
L		 8158 if (*arch == '.')
8159 as_fatal (_("Invalid -march= option: `%s'"), arg);
8160 next = strchr (arch, '+');
8161 if (next)
8162 *next++ = '\0';
91d6fa6a 8163 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8164 {
91d6fa6a 8165 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8166 {
6305a203 8167 /* Processor. */
91d6fa6a 8168 cpu_arch_name = cpu_arch[j].name;
6305a203 8169 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8170 cpu_arch_flags = cpu_arch[j].flags;
8171 cpu_arch_isa = cpu_arch[j].type;
8172 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8173 if (!cpu_arch_tune_set)
8174 {
8175 cpu_arch_tune = cpu_arch_isa;
8176 cpu_arch_tune_flags = cpu_arch_isa_flags;
8177 }
8178 break;
8179 }
91d6fa6a
NC		 8180 else if (*cpu_arch [j].name == '.'
8181 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8182 {
8183 /* ISA entension. */
8184 i386_cpu_flags flags;
309d3373
JB		 8185
8186 if (strncmp (arch, "no", 2))
8187 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8188 cpu_arch[j].flags);
309d3373
JB		 8189 else
8190 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 8191 cpu_arch[j].flags);
0dfbf9d7 8192 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8193 {
8194 if (cpu_sub_arch_name)
8195 {
8196 char *name = cpu_sub_arch_name;
8197 cpu_sub_arch_name = concat (name,
91d6fa6a 8198 cpu_arch[j].name,
1bf57e9f 8199 (const char *) NULL);
6305a203
L		 8200 free (name);
8201 }
8202 else
91d6fa6a 8203 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8204 cpu_arch_flags = flags;
8205 }
8206 break;
ccc9c027 8207 }
9103f4f4 8208 }
6305a203 8209
91d6fa6a 8210 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8211 as_fatal (_("Invalid -march= option: `%s'"), arg);
8212
8213 arch = next;
9103f4f4 8214 }
6305a203 8215 while (next != NULL );
9103f4f4
L		 8216 break;
8217
8218 case OPTION_MTUNE:
8219 if (*arg == '.')
8220 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8221 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8222 {
91d6fa6a 8223 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8224 {
ccc9c027 8225 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8226 cpu_arch_tune = cpu_arch [j].type;
8227 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8228 break;
8229 }
8230 }
91d6fa6a 8231 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8232 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8233 break;
8234
1efbbeb4
L		 8235 case OPTION_MMNEMONIC:
8236 if (strcasecmp (arg, "att") == 0)
8237 intel_mnemonic = 0;
8238 else if (strcasecmp (arg, "intel") == 0)
8239 intel_mnemonic = 1;
8240 else
8241 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8242 break;
8243
8244 case OPTION_MSYNTAX:
8245 if (strcasecmp (arg, "att") == 0)
8246 intel_syntax = 0;
8247 else if (strcasecmp (arg, "intel") == 0)
8248 intel_syntax = 1;
8249 else
8250 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8251 break;
8252
8253 case OPTION_MINDEX_REG:
8254 allow_index_reg = 1;
8255 break;
8256
8257 case OPTION_MNAKED_REG:
8258 allow_naked_reg = 1;
8259 break;
8260
8261 case OPTION_MOLD_GCC:
8262 old_gcc = 1;
1efbbeb4
L		 8263 break;
8264
c0f3af97
L		 8265 case OPTION_MSSE2AVX:
8266 sse2avx = 1;
8267 break;
8268
daf50ae7
L		 8269 case OPTION_MSSE_CHECK:
8270 if (strcasecmp (arg, "error") == 0)
8271 sse_check = sse_check_error;
8272 else if (strcasecmp (arg, "warning") == 0)
8273 sse_check = sse_check_warning;
8274 else if (strcasecmp (arg, "none") == 0)
8275 sse_check = sse_check_none;
8276 else
8277 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8278 break;
8279
539f890d
L		 8280 case OPTION_MAVXSCALAR:
8281 if (strcasecmp (arg, "128") == 0)
8282 avxscalar = vex128;
8283 else if (strcasecmp (arg, "256") == 0)
8284 avxscalar = vex256;
8285 else
8286 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8287 break;
8288
252b5132
RH		 8289 default:
8290 return 0;
8291 }
8292 return 1;
8293}
8294
8a2c8fef
L		 8295#define MESSAGE_TEMPLATE \
8296" "
8297
8298static void
8299show_arch (FILE *stream, int ext)
8300{
8301 static char message[] = MESSAGE_TEMPLATE;
8302 char *start = message + 27;
8303 char *p;
8304 int size = sizeof (MESSAGE_TEMPLATE);
8305 int left;
8306 const char *name;
8307 int len;
8308 unsigned int j;
8309
8310 p = start;
8311 left = size - (start - message);
8312 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8313 {
8314 /* Should it be skipped? */
8315 if (cpu_arch [j].skip)
8316 continue;
8317
8318 name = cpu_arch [j].name;
8319 len = cpu_arch [j].len;
8320 if (*name == '.')
8321 {
8322 /* It is an extension. Skip if we aren't asked to show it. */
8323 if (ext)
8324 {
8325 name++;
8326 len--;
8327 }
8328 else
8329 continue;
8330 }
8331 else if (ext)
8332 {
8333 /* It is an processor. Skip if we show only extension. */
8334 continue;
8335 }
8336
8337 /* Reserve 2 spaces for ", " or ",\0" */
8338 left -= len + 2;
8339
8340 /* Check if there is any room. */
8341 if (left >= 0)
8342 {
8343 if (p != start)
8344 {
8345 *p++ = ',';
8346 *p++ = ' ';
8347 }
8348 p = mempcpy (p, name, len);
8349 }
8350 else
8351 {
8352 /* Output the current message now and start a new one. */
8353 *p++ = ',';
8354 *p = '\0';
8355 fprintf (stream, "%s\n", message);
8356 p = start;
8357 left = size - (start - message) - len - 2;
8358
8359 gas_assert (left >= 0);
8360
8361 p = mempcpy (p, name, len);
8362 }
8363 }
8364
8365 *p = '\0';
8366 fprintf (stream, "%s\n", message);
8367}
8368
252b5132 8369void
8a2c8fef 8370md_show_usage (FILE *stream)
252b5132 8371{
4cc782b5
ILT		 8372#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8373 fprintf (stream, _("\
a38cf1db
AM		 8374 -Q ignored\n\
8375 -V print assembler version number\n\
b3b91714
AM		 8376 -k ignored\n"));
8377#endif
8378 fprintf (stream, _("\
12b55ccc 8379 -n Do not optimize code alignment\n\
b3b91714
AM		 8380 -q quieten some warnings\n"));
8381#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8382 fprintf (stream, _("\
a38cf1db 8383 -s ignored\n"));
b3b91714 8384#endif
321098a5
L		 8385#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8386 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8387 fprintf (stream, _("\
8388 --32/--64 generate 32bit/64bit code\n"));
8389#endif
b3b91714
AM		 8390#ifdef SVR4_COMMENT_CHARS
8391 fprintf (stream, _("\
8392 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8393#else
8394 fprintf (stream, _("\
b3b91714 8395 --divide ignored\n"));
4cc782b5 8396#endif
9103f4f4 8397 fprintf (stream, _("\
6305a203 8398 -march=CPU[,+EXTENSION...]\n\
8a2c8fef
L		 8399 generate code for CPU and EXTENSION, CPU is one of:\n"));
8400 show_arch (stream, 0);
8401 fprintf (stream, _("\
8402 EXTENSION is combination of:\n"));
8403 show_arch (stream, 1);
6305a203 8404 fprintf (stream, _("\
8a2c8fef
L		 8405 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8406 show_arch (stream, 0);
ba104c83 8407 fprintf (stream, _("\
c0f3af97
L		 8408 -msse2avx encode SSE instructions with VEX prefix\n"));
8409 fprintf (stream, _("\
daf50ae7
L		 8410 -msse-check=[none|error|warning]\n\
8411 check SSE instructions\n"));
8412 fprintf (stream, _("\
539f890d
L		 8413 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8414 length\n"));
8415 fprintf (stream, _("\
ba104c83
L		 8416 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8417 fprintf (stream, _("\
8418 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8419 fprintf (stream, _("\
8420 -mindex-reg support pseudo index registers\n"));
8421 fprintf (stream, _("\
8422 -mnaked-reg don't require `%%' prefix for registers\n"));
8423 fprintf (stream, _("\
8424 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8425}
8426
3e73aa7c 8427#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8428 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8429 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8430
8431/* Pick the target format to use. */
8432
47926f60 8433const char *
e3bb37b5 8434i386_target_format (void)
252b5132 8435{
3e73aa7c 8436 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8437 {
8438 set_code_flag (CODE_64BIT);
0dfbf9d7 8439 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8440 {
8441 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8442 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8443 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8444 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8445 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8446 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8447 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8448 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8449 cpu_arch_isa_flags.bitfield.cpusse = 1;
8450 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8451 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8452 }
0dfbf9d7 8453 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8454 {
8455 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8456 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8457 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8458 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8459 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8460 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8461 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8462 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8463 cpu_arch_tune_flags.bitfield.cpusse = 1;
8464 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8465 }
9103f4f4 8466 }
3e73aa7c 8467 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8468 {
8469 set_code_flag (CODE_32BIT);
0dfbf9d7 8470 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8471 {
8472 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8473 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8474 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8475 }
0dfbf9d7 8476 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8477 {
8478 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8479 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8480 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8481 }
9103f4f4 8482 }
3e73aa7c
JH		 8483 else
8484 as_fatal (_("Unknown architecture"));
252b5132
RH		 8485 switch (OUTPUT_FLAVOR)
8486 {
9384f2ff 8487#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8488 case bfd_target_aout_flavour:
47926f60 8489 return AOUT_TARGET_FORMAT;
4c63da97 8490#endif
9384f2ff
AM		 8491#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8492# if defined (TE_PE) || defined (TE_PEP)
8493 case bfd_target_coff_flavour:
8494 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8495# elif defined (TE_GO32)
0561d57c
JK		 8496 case bfd_target_coff_flavour:
8497 return "coff-go32";
9384f2ff 8498# else
252b5132
RH		 8499 case bfd_target_coff_flavour:
8500 return "coff-i386";
9384f2ff 8501# endif
4c63da97 8502#endif
3e73aa7c 8503#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8504 case bfd_target_elf_flavour:
3e73aa7c 8505 {
e5cb08ac 8506 if (flag_code == CODE_64BIT)
4fa24527
JB		 8507 {
8508 object_64bit = 1;
8509 use_rela_relocations = 1;
8510 }
3632d14b 8511 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8512 {
8513 if (flag_code != CODE_64BIT)
8514 as_fatal (_("Intel L1OM is 64bit only"));
8515 return ELF_TARGET_L1OM_FORMAT;
8516 }
8517 else
8518 return (flag_code == CODE_64BIT
8519 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8520 }
e57f8c65
TG		 8521#endif
8522#if defined (OBJ_MACH_O)
8523 case bfd_target_mach_o_flavour:
8524 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8525#endif
252b5132
RH		 8526 default:
8527 abort ();
8528 return NULL;
8529 }
8530}
8531
47926f60 8532#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8533
8534#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8535void
8536i386_elf_emit_arch_note (void)
a847613f 8537{
718ddfc0 8538 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8539 {
8540 char *p;
8541 asection *seg = now_seg;
8542 subsegT subseg = now_subseg;
8543 Elf_Internal_Note i_note;
8544 Elf_External_Note e_note;
8545 asection *note_secp;
8546 int len;
8547
8548 /* Create the .note section. */
8549 note_secp = subseg_new (".note", 0);
8550 bfd_set_section_flags (stdoutput,
8551 note_secp,
8552 SEC_HAS_CONTENTS | SEC_READONLY);
8553
8554 /* Process the arch string. */
8555 len = strlen (cpu_arch_name);
8556
8557 i_note.namesz = len + 1;
8558 i_note.descsz = 0;
8559 i_note.type = NT_ARCH;
8560 p = frag_more (sizeof (e_note.namesz));
8561 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8562 p = frag_more (sizeof (e_note.descsz));
8563 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8564 p = frag_more (sizeof (e_note.type));
8565 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8566 p = frag_more (len + 1);
8567 strcpy (p, cpu_arch_name);
8568
8569 frag_align (2, 0, 0);
8570
8571 subseg_set (seg, subseg);
8572 }
8573}
8574#endif
252b5132 8575\f
252b5132
RH		 8576symbolS *
8577md_undefined_symbol (name)
8578 char *name;
8579{
18dc2407
ILT		 8580 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8581 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8582 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8583 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8584 {
8585 if (!GOT_symbol)
8586 {
8587 if (symbol_find (name))
8588 as_bad (_("GOT already in symbol table"));
8589 GOT_symbol = symbol_new (name, undefined_section,
8590 (valueT) 0, &zero_address_frag);
8591 };
8592 return GOT_symbol;
8593 }
252b5132
RH		 8594 return 0;
8595}
8596
8597/* Round up a section size to the appropriate boundary. */
47926f60 8598
252b5132
RH		 8599valueT
8600md_section_align (segment, size)
ab9da554 8601 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8602 valueT size;
8603{
4c63da97
AM		 8604#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8605 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8606 {
8607 /* For a.out, force the section size to be aligned. If we don't do
8608 this, BFD will align it for us, but it will not write out the
8609 final bytes of the section. This may be a bug in BFD, but it is
8610 easier to fix it here since that is how the other a.out targets
8611 work. */
8612 int align;
8613
8614 align = bfd_get_section_alignment (stdoutput, segment);
8615 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8616 }
252b5132
RH		 8617#endif
8618
8619 return size;
8620}
8621
8622/* On the i386, PC-relative offsets are relative to the start of the
8623 next instruction. That is, the address of the offset, plus its
8624 size, since the offset is always the last part of the insn. */
8625
8626long
e3bb37b5 8627md_pcrel_from (fixS *fixP)
252b5132
RH		 8628{
8629 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8630}
8631
8632#ifndef I386COFF
8633
8634static void
e3bb37b5 8635s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8636{
29b0f896 8637 int temp;
252b5132 8638
8a75718c
JB		 8639#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8640 if (IS_ELF)
8641 obj_elf_section_change_hook ();
8642#endif
252b5132
RH		 8643 temp = get_absolute_expression ();
8644 subseg_set (bss_section, (subsegT) temp);
8645 demand_empty_rest_of_line ();
8646}
8647
8648#endif
8649
252b5132 8650void
e3bb37b5 8651i386_validate_fix (fixS *fixp)
252b5132
RH		 8652{
8653 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8654 {
23df1078
JH		 8655 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8656 {
4fa24527 8657 if (!object_64bit)
23df1078
JH		 8658 abort ();
8659 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8660 }
8661 else
8662 {
4fa24527 8663 if (!object_64bit)
d6ab8113
JB		 8664 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8665 else
8666 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8667 }
252b5132
RH		 8668 fixp->fx_subsy = 0;
8669 }
8670}
8671
252b5132
RH		 8672arelent *
8673tc_gen_reloc (section, fixp)
ab9da554 8674 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8675 fixS *fixp;
8676{
8677 arelent *rel;
8678 bfd_reloc_code_real_type code;
8679
8680 switch (fixp->fx_r_type)
8681 {
3e73aa7c
JH		 8682 case BFD_RELOC_X86_64_PLT32:
8683 case BFD_RELOC_X86_64_GOT32:
8684 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8685 case BFD_RELOC_386_PLT32:
8686 case BFD_RELOC_386_GOT32:
8687 case BFD_RELOC_386_GOTOFF:
8688 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8689 case BFD_RELOC_386_TLS_GD:
8690 case BFD_RELOC_386_TLS_LDM:
8691 case BFD_RELOC_386_TLS_LDO_32:
8692 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8693 case BFD_RELOC_386_TLS_IE:
8694 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8695 case BFD_RELOC_386_TLS_LE_32:
8696 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8697 case BFD_RELOC_386_TLS_GOTDESC:
8698 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8699 case BFD_RELOC_X86_64_TLSGD:
8700 case BFD_RELOC_X86_64_TLSLD:
8701 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8702 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8703 case BFD_RELOC_X86_64_GOTTPOFF:
8704 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8705 case BFD_RELOC_X86_64_TPOFF64:
8706 case BFD_RELOC_X86_64_GOTOFF64:
8707 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8708 case BFD_RELOC_X86_64_GOT64:
8709 case BFD_RELOC_X86_64_GOTPCREL64:
8710 case BFD_RELOC_X86_64_GOTPC64:
8711 case BFD_RELOC_X86_64_GOTPLT64:
8712 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8713 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8714 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8715 case BFD_RELOC_RVA:
8716 case BFD_RELOC_VTABLE_ENTRY:
8717 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8718#ifdef TE_PE
8719 case BFD_RELOC_32_SECREL:
8720#endif
252b5132
RH		 8721 code = fixp->fx_r_type;
8722 break;
dbbaec26
L		 8723 case BFD_RELOC_X86_64_32S:
8724 if (!fixp->fx_pcrel)
8725 {
8726 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8727 code = fixp->fx_r_type;
8728 break;
8729 }
252b5132 8730 default:
93382f6d 8731 if (fixp->fx_pcrel)
252b5132 8732 {
93382f6d
AM		 8733 switch (fixp->fx_size)
8734 {
8735 default:
b091f402
AM		 8736 as_bad_where (fixp->fx_file, fixp->fx_line,
8737 _("can not do %d byte pc-relative relocation"),
8738 fixp->fx_size);
93382f6d
AM		 8739 code = BFD_RELOC_32_PCREL;
8740 break;
8741 case 1: code = BFD_RELOC_8_PCREL; break;
8742 case 2: code = BFD_RELOC_16_PCREL; break;
8743 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8744#ifdef BFD64
8745 case 8: code = BFD_RELOC_64_PCREL; break;
8746#endif
93382f6d
AM		 8747 }
8748 }
8749 else
8750 {
8751 switch (fixp->fx_size)
8752 {
8753 default:
b091f402
AM		 8754 as_bad_where (fixp->fx_file, fixp->fx_line,
8755 _("can not do %d byte relocation"),
8756 fixp->fx_size);
93382f6d
AM		 8757 code = BFD_RELOC_32;
8758 break;
8759 case 1: code = BFD_RELOC_8; break;
8760 case 2: code = BFD_RELOC_16; break;
8761 case 4: code = BFD_RELOC_32; break;
937149dd 8762#ifdef BFD64
3e73aa7c 8763 case 8: code = BFD_RELOC_64; break;
937149dd 8764#endif
93382f6d 8765 }
252b5132
RH		 8766 }
8767 break;
8768 }
252b5132 8769
d182319b
JB		 8770 if ((code == BFD_RELOC_32
8771 || code == BFD_RELOC_32_PCREL
8772 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8773 && GOT_symbol
8774 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8775 {
4fa24527 8776 if (!object_64bit)
d6ab8113
JB		 8777 code = BFD_RELOC_386_GOTPC;
8778 else
8779 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8780 }
7b81dfbb
AJ		 8781 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8782 && GOT_symbol
8783 && fixp->fx_addsy == GOT_symbol)
8784 {
8785 code = BFD_RELOC_X86_64_GOTPC64;
8786 }
252b5132
RH		 8787
8788 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8789 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8790 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8791
8792 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8793
3e73aa7c
JH		 8794 if (!use_rela_relocations)
8795 {
8796 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8797 vtable entry to be used in the relocation's section offset. */
8798 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8799 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8800#if defined (OBJ_COFF) && defined (TE_PE)
8801 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8802 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8803 else
8804#endif
c6682705 8805 rel->addend = 0;
3e73aa7c
JH		 8806 }
8807 /* Use the rela in 64bit mode. */
252b5132 8808 else
3e73aa7c 8809 {
062cd5e7
AS		 8810 if (!fixp->fx_pcrel)
8811 rel->addend = fixp->fx_offset;
8812 else
8813 switch (code)
8814 {
8815 case BFD_RELOC_X86_64_PLT32:
8816 case BFD_RELOC_X86_64_GOT32:
8817 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8818 case BFD_RELOC_X86_64_TLSGD:
8819 case BFD_RELOC_X86_64_TLSLD:
8820 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8821 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8822 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8823 rel->addend = fixp->fx_offset - fixp->fx_size;
8824 break;
8825 default:
8826 rel->addend = (section->vma
8827 - fixp->fx_size
8828 + fixp->fx_addnumber
8829 + md_pcrel_from (fixp));
8830 break;
8831 }
3e73aa7c
JH		 8832 }
8833
252b5132
RH		 8834 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8835 if (rel->howto == NULL)
8836 {
8837 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8838 _("cannot represent relocation type %s"),
252b5132
RH		 8839 bfd_get_reloc_code_name (code));
8840 /* Set howto to a garbage value so that we can keep going. */
8841 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8842 gas_assert (rel->howto != NULL);
252b5132
RH		 8843 }
8844
8845 return rel;
8846}
8847
ee86248c 8848#include "tc-i386-intel.c"
54cfded0 8849
a60de03c
JB		 8850void
8851tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8852{
a60de03c
JB		 8853 int saved_naked_reg;
8854 char saved_register_dot;
54cfded0 8855
a60de03c
JB		 8856 saved_naked_reg = allow_naked_reg;
8857 allow_naked_reg = 1;
8858 saved_register_dot = register_chars['.'];
8859 register_chars['.'] = '.';
8860 allow_pseudo_reg = 1;
8861 expression_and_evaluate (exp);
8862 allow_pseudo_reg = 0;
8863 register_chars['.'] = saved_register_dot;
8864 allow_naked_reg = saved_naked_reg;
8865
8866 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8867 {
a60de03c
JB		 8868 if ((addressT) exp->X_add_number < i386_regtab_size)
8869 {
8870 exp->X_op = O_constant;
8871 exp->X_add_number = i386_regtab[exp->X_add_number]
8872 .dw2_regnum[flag_code >> 1];
8873 }
8874 else
8875 exp->X_op = O_illegal;
54cfded0 8876 }
54cfded0
AM		 8877}
8878
8879void
8880tc_x86_frame_initial_instructions (void)
8881{
a60de03c
JB		 8882 static unsigned int sp_regno[2];
8883
8884 if (!sp_regno[flag_code >> 1])
8885 {
8886 char *saved_input = input_line_pointer;
8887 char sp[][4] = {"esp", "rsp"};
8888 expressionS exp;
a4447b93 8889
a60de03c
JB		 8890 input_line_pointer = sp[flag_code >> 1];
8891 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8892 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8893 sp_regno[flag_code >> 1] = exp.X_add_number;
8894 input_line_pointer = saved_input;
8895 }
a4447b93 8896
a60de03c 8897 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8898 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8899}
d2b2c203
DJ		 8900
8901int
8902i386_elf_section_type (const char *str, size_t len)
8903{
8904 if (flag_code == CODE_64BIT
8905 && len == sizeof ("unwind") - 1
8906 && strncmp (str, "unwind", 6) == 0)
8907 return SHT_X86_64_UNWIND;
8908
8909 return -1;
8910}
bb41ade5 8911
ad5fec3b
EB		 8912#ifdef TE_SOLARIS
8913void
8914i386_solaris_fix_up_eh_frame (segT sec)
8915{
8916 if (flag_code == CODE_64BIT)
8917 elf_section_type (sec) = SHT_X86_64_UNWIND;
8918}
8919#endif
8920
bb41ade5
AM		 8921#ifdef TE_PE
8922void
8923tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8924{
91d6fa6a 8925 expressionS exp;
bb41ade5 8926
91d6fa6a
NC		 8927 exp.X_op = O_secrel;
8928 exp.X_add_symbol = symbol;
8929 exp.X_add_number = 0;
8930 emit_expr (&exp, size);
bb41ade5
AM		 8931}
8932#endif
3b22753a
L		 8933
8934#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8935/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8936
01e1a5bc 8937bfd_vma
3b22753a
L		 8938x86_64_section_letter (int letter, char **ptr_msg)
8939{
8940 if (flag_code == CODE_64BIT)
8941 {
8942 if (letter == 'l')
8943 return SHF_X86_64_LARGE;
8944
8945 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8946 }
3b22753a 8947 else
64e74474 8948 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8949 return -1;
8950}
8951
01e1a5bc 8952bfd_vma
3b22753a
L		 8953x86_64_section_word (char *str, size_t len)
8954{
8620418b 8955 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8956 return SHF_X86_64_LARGE;
8957
8958 return -1;
8959}
8960
8961static void
8962handle_large_common (int small ATTRIBUTE_UNUSED)
8963{
8964 if (flag_code != CODE_64BIT)
8965 {
8966 s_comm_internal (0, elf_common_parse);
8967 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8968 }
8969 else
8970 {
8971 static segT lbss_section;
8972 asection *saved_com_section_ptr = elf_com_section_ptr;
8973 asection *saved_bss_section = bss_section;
8974
8975 if (lbss_section == NULL)
8976 {
8977 flagword applicable;
8978 segT seg = now_seg;
8979 subsegT subseg = now_subseg;
8980
8981 /* The .lbss section is for local .largecomm symbols. */
8982 lbss_section = subseg_new (".lbss", 0);
8983 applicable = bfd_applicable_section_flags (stdoutput);
8984 bfd_set_section_flags (stdoutput, lbss_section,
8985 applicable & SEC_ALLOC);
8986 seg_info (lbss_section)->bss = 1;
8987
8988 subseg_set (seg, subseg);
8989 }
8990
8991 elf_com_section_ptr = &_bfd_elf_large_com_section;
8992 bss_section = lbss_section;
8993
8994 s_comm_internal (0, elf_common_parse);
8995
8996 elf_com_section_ptr = saved_com_section_ptr;
8997 bss_section = saved_bss_section;
8998 }
8999}
9000#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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