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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
92static void optimize_imm PARAMS ((void));
93static void optimize_disp PARAMS ((void));
94static int match_template PARAMS ((void));
95static int check_string PARAMS ((void));
96static int process_suffix PARAMS ((void));
97static int check_byte_reg PARAMS ((void));
98static int check_long_reg PARAMS ((void));
99static int check_qword_reg PARAMS ((void));
100static int check_word_reg PARAMS ((void));
101static int finalize_imm PARAMS ((void));
102static int process_operands PARAMS ((void));
103static const seg_entry *build_modrm_byte PARAMS ((void));
104static void output_insn PARAMS ((void));
105static void output_branch PARAMS ((void));
106static void output_jump PARAMS ((void));
107static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 108static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
29b0f896
AM		 112#ifndef I386COFF
113static void s_bss PARAMS ((int));
252b5132 114#endif
17d4e2a2
L		 115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116static void handle_large_common (int small ATTRIBUTE_UNUSED);
117#endif
252b5132 118
a847613f 119static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 120
252b5132 121/* 'md_assemble ()' gathers together information and puts it into a
47926f60 122 i386_insn. */
252b5132 123
520dc8e8
AM		 124union i386_op
125 {
126 expressionS *disps;
127 expressionS *imms;
128 const reg_entry *regs;
129 };
130
252b5132
RH		 131struct _i386_insn
132 {
47926f60 133 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 134 template tm;
135
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
138 char suffix;
139
47926f60 140 /* OPERANDS gives the number of given operands. */
252b5132
RH		 141 unsigned int operands;
142
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
47926f60 145 operands. */
252b5132
RH		 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147
148 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 149 use OP[i] for the corresponding operand. */
252b5132
RH		 150 unsigned int types[MAX_OPERANDS];
151
520dc8e8
AM		 152 /* Displacement expression, immediate expression, or register for each
153 operand. */
154 union i386_op op[MAX_OPERANDS];
252b5132 155
3e73aa7c
JH		 156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158#define Operand_PCrel 1
159
252b5132 160 /* Relocation type for operand */
f86103b7 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 162
252b5132
RH		 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
168
169 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 170 explicit segment overrides are given. */
ce8a8b2f 171 const seg_entry *seg[2];
252b5132
RH		 172
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
177
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
180
181 modrm_byte rm;
3e73aa7c 182 rex_byte rex;
252b5132
RH		 183 sib_byte sib;
184 };
185
186typedef struct _i386_insn i386_insn;
187
188/* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
32137342 190const char extra_symbol_chars[] = "*%-(["
252b5132 191#ifdef LEX_AT
32137342
NC		 192 "@"
193#endif
194#ifdef LEX_QM
195 "?"
252b5132 196#endif
32137342 197 ;
252b5132 198
29b0f896
AM		 199#if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_LINUX) \
32137342 202 && !defined (TE_NETWARE) \
29b0f896
AM		 203 && !defined (TE_FreeBSD) \
204 && !defined (TE_NetBSD)))
252b5132 205/* This array holds the chars that always start a comment. If the
ce8a8b2f 206 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 207const char comment_chars[] = "#/";
208#define PREFIX_SEPARATOR '\\'
252b5132
RH		 209
210/* This array holds the chars that only start a comment at the beginning of
211 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 212 .line and .file directives will appear in the pre-processed output.
213 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 214 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 215 #NO_APP at the beginning of its output.
216 Also note that comments started like this one will always work if
252b5132 217 '/' isn't otherwise defined. */
0d9f6d04 218const char line_comment_chars[] = "#";
29b0f896 219
252b5132 220#else
29b0f896
AM		 221/* Putting '/' here makes it impossible to use the divide operator.
222 However, we need it for compatibility with SVR4 systems. */
223const char comment_chars[] = "#";
224#define PREFIX_SEPARATOR '/'
225
0d9f6d04 226const char line_comment_chars[] = "/#";
252b5132
RH		 227#endif
228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
fddf5b5b
AM		 327/* If set, conditional jumps are not automatically promoted to handle
328 larger than a byte offset. */
329static unsigned int no_cond_jump_promotion = 0;
330
29b0f896 331/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 332static symbolS *GOT_symbol;
29b0f896 333
a4447b93
RH		 334/* The dwarf2 return column, adjusted for 32 or 64 bit. */
335unsigned int x86_dwarf2_return_column;
336
337/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
338int x86_cie_data_alignment;
339
252b5132 340/* Interface to relax_segment.
fddf5b5b
AM		 341 There are 3 major relax states for 386 jump insns because the
342 different types of jumps add different sizes to frags when we're
343 figuring out what sort of jump to choose to reach a given label. */
252b5132 344
47926f60 345/* Types. */
93c2a809
AM		 346#define UNCOND_JUMP 0
347#define COND_JUMP 1
348#define COND_JUMP86 2
fddf5b5b 349
47926f60 350/* Sizes. */
252b5132
RH		 351#define CODE16 1
352#define SMALL 0
29b0f896 353#define SMALL16 (SMALL | CODE16)
252b5132 354#define BIG 2
29b0f896 355#define BIG16 (BIG | CODE16)
252b5132
RH		 356
357#ifndef INLINE
358#ifdef __GNUC__
359#define INLINE __inline__
360#else
361#define INLINE
362#endif
363#endif
364
fddf5b5b
AM		 365#define ENCODE_RELAX_STATE(type, size) \
366 ((relax_substateT) (((type) << 2) | (size)))
367#define TYPE_FROM_RELAX_STATE(s) \
368 ((s) >> 2)
369#define DISP_SIZE_FROM_RELAX_STATE(s) \
370 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 371
372/* This table is used by relax_frag to promote short jumps to long
373 ones where necessary. SMALL (short) jumps may be promoted to BIG
374 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
375 don't allow a short jump in a 32 bit code segment to be promoted to
376 a 16 bit offset jump because it's slower (requires data size
377 prefix), and doesn't work, unless the destination is in the bottom
378 64k of the code segment (The top 16 bits of eip are zeroed). */
379
380const relax_typeS md_relax_table[] =
381{
24eab124
AM		 382 /* The fields are:
383 1) most positive reach of this state,
384 2) most negative reach of this state,
93c2a809 385 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 386 4) which index into the table to try if we can't fit into this one. */
252b5132 387
fddf5b5b 388 /* UNCOND_JUMP states. */
93c2a809
AM		 389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
391 /* dword jmp adds 4 bytes to frag:
392 0 extra opcode bytes, 4 displacement bytes. */
252b5132 393 {0, 0, 4, 0},
93c2a809
AM		 394 /* word jmp adds 2 byte2 to frag:
395 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 396 {0, 0, 2, 0},
397
93c2a809
AM		 398 /* COND_JUMP states. */
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
400 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
401 /* dword conditionals adds 5 bytes to frag:
402 1 extra opcode byte, 4 displacement bytes. */
403 {0, 0, 5, 0},
fddf5b5b 404 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 405 1 extra opcode byte, 2 displacement bytes. */
406 {0, 0, 3, 0},
407
408 /* COND_JUMP86 states. */
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
410 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
411 /* dword conditionals adds 5 bytes to frag:
412 1 extra opcode byte, 4 displacement bytes. */
413 {0, 0, 5, 0},
414 /* word conditionals add 4 bytes to frag:
415 1 displacement byte and a 3 byte long branch insn. */
416 {0, 0, 4, 0}
252b5132
RH		 417};
418
e413e4e9
AM		 419static const arch_entry cpu_arch[] = {
420 {"i8086", Cpu086 },
421 {"i186", Cpu086|Cpu186 },
422 {"i286", Cpu086|Cpu186|Cpu286 },
423 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
424 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 425 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
426 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
427 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
428 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
429 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
430 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
431 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
432 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
433 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
434 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
435 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
436 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 437 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 438 {".mmx", CpuMMX },
439 {".sse", CpuMMX|CpuMMX2|CpuSSE },
440 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 441 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 442 {".3dnow", CpuMMX|Cpu3dnow },
443 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
444 {".padlock", CpuPadLock },
30123838
JB		 445 {".pacifica", CpuSVME },
446 {".svme", CpuSVME },
e413e4e9
AM		 447 {NULL, 0 }
448};
449
29b0f896
AM		 450const pseudo_typeS md_pseudo_table[] =
451{
452#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
453 {"align", s_align_bytes, 0},
454#else
455 {"align", s_align_ptwo, 0},
456#endif
457 {"arch", set_cpu_arch, 0},
458#ifndef I386COFF
459 {"bss", s_bss, 0},
460#endif
461 {"ffloat", float_cons, 'f'},
462 {"dfloat", float_cons, 'd'},
463 {"tfloat", float_cons, 'x'},
464 {"value", cons, 2},
d182319b 465 {"slong", signed_cons, 4},
29b0f896
AM		 466 {"noopt", s_ignore, 0},
467 {"optim", s_ignore, 0},
468 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
469 {"code16", set_code_flag, CODE_16BIT},
470 {"code32", set_code_flag, CODE_32BIT},
471 {"code64", set_code_flag, CODE_64BIT},
472 {"intel_syntax", set_intel_syntax, 1},
473 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 474#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
475 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 476#else
477 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
478 {"loc", dwarf2_directive_loc, 0},
479 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 480#endif
6482c264
NC		 481#ifdef TE_PE
482 {"secrel32", pe_directive_secrel, 0},
483#endif
29b0f896
AM		 484 {0, 0, 0}
485};
486
487/* For interface with expression (). */
488extern char *input_line_pointer;
489
490/* Hash table for instruction mnemonic lookup. */
491static struct hash_control *op_hash;
492
493/* Hash table for register lookup. */
494static struct hash_control *reg_hash;
495\f
252b5132
RH		 496void
497i386_align_code (fragP, count)
498 fragS *fragP;
499 int count;
500{
ce8a8b2f
AM		 501 /* Various efficient no-op patterns for aligning code labels.
502 Note: Don't try to assemble the instructions in the comments.
503 0L and 0w are not legal. */
252b5132
RH		 504 static const char f32_1[] =
505 {0x90}; /* nop */
506 static const char f32_2[] =
507 {0x89,0xf6}; /* movl %esi,%esi */
508 static const char f32_3[] =
509 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
510 static const char f32_4[] =
511 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
512 static const char f32_5[] =
513 {0x90, /* nop */
514 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
515 static const char f32_6[] =
516 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
517 static const char f32_7[] =
518 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
519 static const char f32_8[] =
520 {0x90, /* nop */
521 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
522 static const char f32_9[] =
523 {0x89,0xf6, /* movl %esi,%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_10[] =
526 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
527 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
528 static const char f32_11[] =
529 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
530 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
531 static const char f32_12[] =
532 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
533 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
534 static const char f32_13[] =
535 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
536 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
537 static const char f32_14[] =
538 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
539 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
540 static const char f32_15[] =
541 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
542 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 543 static const char f16_3[] =
544 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 545 static const char f16_4[] =
546 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
547 static const char f16_5[] =
548 {0x90, /* nop */
549 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
550 static const char f16_6[] =
551 {0x89,0xf6, /* mov %si,%si */
552 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
553 static const char f16_7[] =
554 {0x8d,0x74,0x00, /* lea 0(%si),%si */
555 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
556 static const char f16_8[] =
557 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
558 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
559 static const char *const f32_patt[] = {
560 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
561 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
562 };
563 static const char *const f16_patt[] = {
c3332e24 564 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 565 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
566 };
567
33fef721
JH		 568 if (count <= 0 || count > 15)
569 return;
3e73aa7c 570
33fef721
JH		 571 /* The recommended way to pad 64bit code is to use NOPs preceded by
572 maximally four 0x66 prefixes. Balance the size of nops. */
573 if (flag_code == CODE_64BIT)
252b5132 574 {
33fef721
JH		 575 int i;
576 int nnops = (count + 3) / 4;
577 int len = count / nnops;
578 int remains = count - nnops * len;
579 int pos = 0;
580
581 for (i = 0; i < remains; i++)
252b5132 582 {
33fef721
JH		 583 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
584 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
585 pos += len + 1;
586 }
587 for (; i < nnops; i++)
588 {
589 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
590 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
591 pos += len;
252b5132 592 }
252b5132 593 }
33fef721
JH		 594 else
595 if (flag_code == CODE_16BIT)
596 {
597 memcpy (fragP->fr_literal + fragP->fr_fix,
598 f16_patt[count - 1], count);
599 if (count > 8)
600 /* Adjust jump offset. */
601 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
602 }
603 else
604 memcpy (fragP->fr_literal + fragP->fr_fix,
605 f32_patt[count - 1], count);
606 fragP->fr_var = count;
252b5132
RH		 607}
608
252b5132
RH		 609static INLINE unsigned int
610mode_from_disp_size (t)
611 unsigned int t;
612{
3e73aa7c 613 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 614}
615
616static INLINE int
617fits_in_signed_byte (num)
847f7ad4 618 offsetT num;
252b5132
RH		 619{
620 return (num >= -128) && (num <= 127);
47926f60 621}
252b5132
RH		 622
623static INLINE int
624fits_in_unsigned_byte (num)
847f7ad4 625 offsetT num;
252b5132
RH		 626{
627 return (num & 0xff) == num;
47926f60 628}
252b5132
RH		 629
630static INLINE int
631fits_in_unsigned_word (num)
847f7ad4 632 offsetT num;
252b5132
RH		 633{
634 return (num & 0xffff) == num;
47926f60 635}
252b5132
RH		 636
637static INLINE int
638fits_in_signed_word (num)
847f7ad4 639 offsetT num;
252b5132
RH		 640{
641 return (-32768 <= num) && (num <= 32767);
47926f60 642}
3e73aa7c
JH		 643static INLINE int
644fits_in_signed_long (num)
645 offsetT num ATTRIBUTE_UNUSED;
646{
647#ifndef BFD64
648 return 1;
649#else
650 return (!(((offsetT) -1 << 31) & num)
651 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
652#endif
653} /* fits_in_signed_long() */
654static INLINE int
655fits_in_unsigned_long (num)
656 offsetT num ATTRIBUTE_UNUSED;
657{
658#ifndef BFD64
659 return 1;
660#else
661 return (num & (((offsetT) 2 << 31) - 1)) == num;
662#endif
663} /* fits_in_unsigned_long() */
252b5132
RH		 664
665static int
666smallest_imm_type (num)
847f7ad4 667 offsetT num;
252b5132 668{
a847613f 669 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 670 {
671 /* This code is disabled on the 486 because all the Imm1 forms
672 in the opcode table are slower on the i486. They're the
673 versions with the implicitly specified single-position
674 displacement, which has another syntax if you really want to
675 use that form. */
676 if (num == 1)
3e73aa7c 677 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 678 }
252b5132 679 return (fits_in_signed_byte (num)
3e73aa7c 680 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 681 : fits_in_unsigned_byte (num)
3e73aa7c 682 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 683 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 684 ? (Imm16 | Imm32 | Imm32S | Imm64)
685 : fits_in_signed_long (num)
686 ? (Imm32 | Imm32S | Imm64)
687 : fits_in_unsigned_long (num)
688 ? (Imm32 | Imm64)
689 : Imm64);
47926f60 690}
252b5132 691
847f7ad4
AM		 692static offsetT
693offset_in_range (val, size)
694 offsetT val;
695 int size;
696{
508866be 697 addressT mask;
ba2adb93 698
847f7ad4
AM		 699 switch (size)
700 {
508866be
L		 701 case 1: mask = ((addressT) 1 << 8) - 1; break;
702 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 703 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 704#ifdef BFD64
705 case 8: mask = ((addressT) 2 << 63) - 1; break;
706#endif
47926f60 707 default: abort ();
847f7ad4
AM		 708 }
709
ba2adb93 710 /* If BFD64, sign extend val. */
3e73aa7c
JH		 711 if (!use_rela_relocations)
712 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
713 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 714
47926f60 715 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 716 {
717 char buf1[40], buf2[40];
718
719 sprint_value (buf1, val);
720 sprint_value (buf2, val & mask);
721 as_warn (_("%s shortened to %s"), buf1, buf2);
722 }
723 return val & mask;
724}
725
252b5132
RH		 726/* Returns 0 if attempting to add a prefix where one from the same
727 class already exists, 1 if non rep/repne added, 2 if rep/repne
728 added. */
729static int
730add_prefix (prefix)
731 unsigned int prefix;
732{
733 int ret = 1;
734 int q;
735
29b0f896
AM		 736 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
737 && flag_code == CODE_64BIT)
3e73aa7c
JH		 738 q = REX_PREFIX;
739 else
740 switch (prefix)
741 {
742 default:
743 abort ();
744
745 case CS_PREFIX_OPCODE:
746 case DS_PREFIX_OPCODE:
747 case ES_PREFIX_OPCODE:
748 case FS_PREFIX_OPCODE:
749 case GS_PREFIX_OPCODE:
750 case SS_PREFIX_OPCODE:
751 q = SEG_PREFIX;
752 break;
252b5132 753
3e73aa7c
JH		 754 case REPNE_PREFIX_OPCODE:
755 case REPE_PREFIX_OPCODE:
756 ret = 2;
757 /* fall thru */
758 case LOCK_PREFIX_OPCODE:
759 q = LOCKREP_PREFIX;
760 break;
252b5132 761
3e73aa7c
JH		 762 case FWAIT_OPCODE:
763 q = WAIT_PREFIX;
764 break;
252b5132 765
3e73aa7c
JH		 766 case ADDR_PREFIX_OPCODE:
767 q = ADDR_PREFIX;
768 break;
252b5132 769
3e73aa7c
JH		 770 case DATA_PREFIX_OPCODE:
771 q = DATA_PREFIX;
772 break;
773 }
252b5132 774
29b0f896 775 if (i.prefix[q] != 0)
252b5132
RH		 776 {
777 as_bad (_("same type of prefix used twice"));
778 return 0;
779 }
780
781 i.prefixes += 1;
782 i.prefix[q] = prefix;
783 return ret;
784}
785
786static void
3e73aa7c 787set_code_flag (value)
e5cb08ac 788 int value;
eecb386c 789{
3e73aa7c
JH		 790 flag_code = value;
791 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
792 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
793 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
794 {
795 as_bad (_("64bit mode not supported on this CPU."));
796 }
797 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
798 {
799 as_bad (_("32bit mode not supported on this CPU."));
800 }
eecb386c
AM		 801 stackop_size = '\0';
802}
803
804static void
3e73aa7c
JH		 805set_16bit_gcc_code_flag (new_code_flag)
806 int new_code_flag;
252b5132 807{
3e73aa7c
JH		 808 flag_code = new_code_flag;
809 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
810 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 811 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 812}
813
814static void
815set_intel_syntax (syntax_flag)
eecb386c 816 int syntax_flag;
252b5132
RH		 817{
818 /* Find out if register prefixing is specified. */
819 int ask_naked_reg = 0;
820
821 SKIP_WHITESPACE ();
29b0f896 822 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 823 {
824 char *string = input_line_pointer;
825 int e = get_symbol_end ();
826
47926f60 827 if (strcmp (string, "prefix") == 0)
252b5132 828 ask_naked_reg = 1;
47926f60 829 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 830 ask_naked_reg = -1;
831 else
d0b47220 832 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 833 *input_line_pointer = e;
834 }
835 demand_empty_rest_of_line ();
c3332e24 836
252b5132
RH		 837 intel_syntax = syntax_flag;
838
839 if (ask_naked_reg == 0)
f86103b7
AM		 840 allow_naked_reg = (intel_syntax
841 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 842 else
843 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 844
845 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
846 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 847}
848
e413e4e9
AM		 849static void
850set_cpu_arch (dummy)
47926f60 851 int dummy ATTRIBUTE_UNUSED;
e413e4e9 852{
47926f60 853 SKIP_WHITESPACE ();
e413e4e9 854
29b0f896 855 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 856 {
857 char *string = input_line_pointer;
858 int e = get_symbol_end ();
859 int i;
860
861 for (i = 0; cpu_arch[i].name; i++)
862 {
863 if (strcmp (string, cpu_arch[i].name) == 0)
864 {
5c6af06e
JB		 865 if (*string != '.')
866 {
867 cpu_arch_name = cpu_arch[i].name;
868 cpu_sub_arch_name = NULL;
869 cpu_arch_flags = (cpu_arch[i].flags
870 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
871 break;
872 }
873 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
874 {
875 cpu_sub_arch_name = cpu_arch[i].name;
876 cpu_arch_flags |= cpu_arch[i].flags;
877 }
878 *input_line_pointer = e;
879 demand_empty_rest_of_line ();
880 return;
e413e4e9
AM		 881 }
882 }
883 if (!cpu_arch[i].name)
884 as_bad (_("no such architecture: `%s'"), string);
885
886 *input_line_pointer = e;
887 }
888 else
889 as_bad (_("missing cpu architecture"));
890
fddf5b5b
AM		 891 no_cond_jump_promotion = 0;
892 if (*input_line_pointer == ','
29b0f896 893 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 894 {
895 char *string = ++input_line_pointer;
896 int e = get_symbol_end ();
897
898 if (strcmp (string, "nojumps") == 0)
899 no_cond_jump_promotion = 1;
900 else if (strcmp (string, "jumps") == 0)
901 ;
902 else
903 as_bad (_("no such architecture modifier: `%s'"), string);
904
905 *input_line_pointer = e;
906 }
907
e413e4e9
AM		 908 demand_empty_rest_of_line ();
909}
910
b9d79e03
JH		 911unsigned long
912i386_mach ()
913{
914 if (!strcmp (default_arch, "x86_64"))
915 return bfd_mach_x86_64;
916 else if (!strcmp (default_arch, "i386"))
917 return bfd_mach_i386_i386;
918 else
919 as_fatal (_("Unknown architecture"));
920}
b9d79e03 921\f
252b5132
RH		 922void
923md_begin ()
924{
925 const char *hash_err;
926
47926f60 927 /* Initialize op_hash hash table. */
252b5132
RH		 928 op_hash = hash_new ();
929
930 {
29b0f896
AM		 931 const template *optab;
932 templates *core_optab;
252b5132 933
47926f60
KH		 934 /* Setup for loop. */
935 optab = i386_optab;
252b5132
RH		 936 core_optab = (templates *) xmalloc (sizeof (templates));
937 core_optab->start = optab;
938
939 while (1)
940 {
941 ++optab;
942 if (optab->name == NULL
943 || strcmp (optab->name, (optab - 1)->name) != 0)
944 {
945 /* different name --> ship out current template list;
47926f60 946 add to hash table; & begin anew. */
252b5132
RH		 947 core_optab->end = optab;
948 hash_err = hash_insert (op_hash,
949 (optab - 1)->name,
950 (PTR) core_optab);
951 if (hash_err)
952 {
252b5132
RH		 953 as_fatal (_("Internal Error: Can't hash %s: %s"),
954 (optab - 1)->name,
955 hash_err);
956 }
957 if (optab->name == NULL)
958 break;
959 core_optab = (templates *) xmalloc (sizeof (templates));
960 core_optab->start = optab;
961 }
962 }
963 }
964
47926f60 965 /* Initialize reg_hash hash table. */
252b5132
RH		 966 reg_hash = hash_new ();
967 {
29b0f896 968 const reg_entry *regtab;
252b5132
RH		 969
970 for (regtab = i386_regtab;
971 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
972 regtab++)
973 {
974 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
975 if (hash_err)
3e73aa7c
JH		 976 as_fatal (_("Internal Error: Can't hash %s: %s"),
977 regtab->reg_name,
978 hash_err);
252b5132
RH		 979 }
980 }
981
47926f60 982 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 983 {
29b0f896
AM		 984 int c;
985 char *p;
252b5132
RH		 986
987 for (c = 0; c < 256; c++)
988 {
3882b010 989 if (ISDIGIT (c))
252b5132
RH		 990 {
991 digit_chars[c] = c;
992 mnemonic_chars[c] = c;
993 register_chars[c] = c;
994 operand_chars[c] = c;
995 }
3882b010 996 else if (ISLOWER (c))
252b5132
RH		 997 {
998 mnemonic_chars[c] = c;
999 register_chars[c] = c;
1000 operand_chars[c] = c;
1001 }
3882b010 1002 else if (ISUPPER (c))
252b5132 1003 {
3882b010 1004 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1005 register_chars[c] = mnemonic_chars[c];
1006 operand_chars[c] = c;
1007 }
1008
3882b010 1009 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1010 identifier_chars[c] = c;
1011 else if (c >= 128)
1012 {
1013 identifier_chars[c] = c;
1014 operand_chars[c] = c;
1015 }
1016 }
1017
1018#ifdef LEX_AT
1019 identifier_chars['@'] = '@';
32137342
NC		 1020#endif
1021#ifdef LEX_QM
1022 identifier_chars['?'] = '?';
1023 operand_chars['?'] = '?';
252b5132 1024#endif
252b5132 1025 digit_chars['-'] = '-';
791fe849 1026 mnemonic_chars['-'] = '-';
252b5132
RH		 1027 identifier_chars['_'] = '_';
1028 identifier_chars['.'] = '.';
1029
1030 for (p = operand_special_chars; *p != '\0'; p++)
1031 operand_chars[(unsigned char) *p] = *p;
1032 }
1033
1034#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1035 if (IS_ELF)
252b5132
RH		 1036 {
1037 record_alignment (text_section, 2);
1038 record_alignment (data_section, 2);
1039 record_alignment (bss_section, 2);
1040 }
1041#endif
a4447b93
RH		 1042
1043 if (flag_code == CODE_64BIT)
1044 {
1045 x86_dwarf2_return_column = 16;
1046 x86_cie_data_alignment = -8;
1047 }
1048 else
1049 {
1050 x86_dwarf2_return_column = 8;
1051 x86_cie_data_alignment = -4;
1052 }
252b5132
RH		 1053}
1054
1055void
1056i386_print_statistics (file)
1057 FILE *file;
1058{
1059 hash_print_statistics (file, "i386 opcode", op_hash);
1060 hash_print_statistics (file, "i386 register", reg_hash);
1061}
1062\f
252b5132
RH		 1063#ifdef DEBUG386
1064
ce8a8b2f 1065/* Debugging routines for md_assemble. */
252b5132
RH		 1066static void pi PARAMS ((char *, i386_insn *));
1067static void pte PARAMS ((template *));
1068static void pt PARAMS ((unsigned int));
1069static void pe PARAMS ((expressionS *));
1070static void ps PARAMS ((symbolS *));
1071
1072static void
1073pi (line, x)
1074 char *line;
1075 i386_insn *x;
1076{
09f131f2 1077 unsigned int i;
252b5132
RH		 1078
1079 fprintf (stdout, "%s: template ", line);
1080 pte (&x->tm);
09f131f2
JH		 1081 fprintf (stdout, " address: base %s index %s scale %x\n",
1082 x->base_reg ? x->base_reg->reg_name : "none",
1083 x->index_reg ? x->index_reg->reg_name : "none",
1084 x->log2_scale_factor);
1085 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1086 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1087 fprintf (stdout, " sib: base %x index %x scale %x\n",
1088 x->sib.base, x->sib.index, x->sib.scale);
1089 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1090 (x->rex & REX_MODE64) != 0,
1091 (x->rex & REX_EXTX) != 0,
1092 (x->rex & REX_EXTY) != 0,
1093 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1094 for (i = 0; i < x->operands; i++)
1095 {
1096 fprintf (stdout, " #%d: ", i + 1);
1097 pt (x->types[i]);
1098 fprintf (stdout, "\n");
1099 if (x->types[i]
3f4438ab 1100 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1101 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1102 if (x->types[i] & Imm)
520dc8e8 1103 pe (x->op[i].imms);
252b5132 1104 if (x->types[i] & Disp)
520dc8e8 1105 pe (x->op[i].disps);
252b5132
RH		 1106 }
1107}
1108
1109static void
1110pte (t)
1111 template *t;
1112{
09f131f2 1113 unsigned int i;
252b5132 1114 fprintf (stdout, " %d operands ", t->operands);
47926f60 1115 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1116 if (t->extension_opcode != None)
1117 fprintf (stdout, "ext %x ", t->extension_opcode);
1118 if (t->opcode_modifier & D)
1119 fprintf (stdout, "D");
1120 if (t->opcode_modifier & W)
1121 fprintf (stdout, "W");
1122 fprintf (stdout, "\n");
1123 for (i = 0; i < t->operands; i++)
1124 {
1125 fprintf (stdout, " #%d type ", i + 1);
1126 pt (t->operand_types[i]);
1127 fprintf (stdout, "\n");
1128 }
1129}
1130
1131static void
1132pe (e)
1133 expressionS *e;
1134{
24eab124 1135 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1136 fprintf (stdout, " add_number %ld (%lx)\n",
1137 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1138 if (e->X_add_symbol)
1139 {
1140 fprintf (stdout, " add_symbol ");
1141 ps (e->X_add_symbol);
1142 fprintf (stdout, "\n");
1143 }
1144 if (e->X_op_symbol)
1145 {
1146 fprintf (stdout, " op_symbol ");
1147 ps (e->X_op_symbol);
1148 fprintf (stdout, "\n");
1149 }
1150}
1151
1152static void
1153ps (s)
1154 symbolS *s;
1155{
1156 fprintf (stdout, "%s type %s%s",
1157 S_GET_NAME (s),
1158 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1159 segment_name (S_GET_SEGMENT (s)));
1160}
1161
1162struct type_name
1163 {
1164 unsigned int mask;
1165 char *tname;
1166 }
1167
29b0f896 1168static const type_names[] =
252b5132
RH		 1169{
1170 { Reg8, "r8" },
1171 { Reg16, "r16" },
1172 { Reg32, "r32" },
09f131f2 1173 { Reg64, "r64" },
252b5132
RH		 1174 { Imm8, "i8" },
1175 { Imm8S, "i8s" },
1176 { Imm16, "i16" },
1177 { Imm32, "i32" },
09f131f2
JH		 1178 { Imm32S, "i32s" },
1179 { Imm64, "i64" },
252b5132
RH		 1180 { Imm1, "i1" },
1181 { BaseIndex, "BaseIndex" },
1182 { Disp8, "d8" },
1183 { Disp16, "d16" },
1184 { Disp32, "d32" },
09f131f2
JH		 1185 { Disp32S, "d32s" },
1186 { Disp64, "d64" },
252b5132
RH		 1187 { InOutPortReg, "InOutPortReg" },
1188 { ShiftCount, "ShiftCount" },
1189 { Control, "control reg" },
1190 { Test, "test reg" },
1191 { Debug, "debug reg" },
1192 { FloatReg, "FReg" },
1193 { FloatAcc, "FAcc" },
1194 { SReg2, "SReg2" },
1195 { SReg3, "SReg3" },
1196 { Acc, "Acc" },
1197 { JumpAbsolute, "Jump Absolute" },
1198 { RegMMX, "rMMX" },
3f4438ab 1199 { RegXMM, "rXMM" },
252b5132
RH		 1200 { EsSeg, "es" },
1201 { 0, "" }
1202};
1203
1204static void
1205pt (t)
1206 unsigned int t;
1207{
29b0f896 1208 const struct type_name *ty;
252b5132 1209
09f131f2
JH		 1210 for (ty = type_names; ty->mask; ty++)
1211 if (t & ty->mask)
1212 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1213 fflush (stdout);
1214}
1215
1216#endif /* DEBUG386 */
1217\f
252b5132 1218static bfd_reloc_code_real_type
3956db08
JB		 1219reloc (unsigned int size,
1220 int pcrel,
1221 int sign,
1222 bfd_reloc_code_real_type other)
252b5132 1223{
47926f60 1224 if (other != NO_RELOC)
3956db08
JB		 1225 {
1226 reloc_howto_type *reloc;
1227
1228 if (size == 8)
1229 switch (other)
1230 {
1231 case BFD_RELOC_X86_64_TPOFF32:
1232 other = BFD_RELOC_X86_64_TPOFF64;
1233 break;
1234 case BFD_RELOC_X86_64_DTPOFF32:
1235 other = BFD_RELOC_X86_64_DTPOFF64;
1236 break;
1237 default:
1238 break;
1239 }
1240 reloc = bfd_reloc_type_lookup (stdoutput, other);
1241 if (!reloc)
1242 as_bad (_("unknown relocation (%u)"), other);
1243 else if (size != bfd_get_reloc_size (reloc))
1244 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1245 bfd_get_reloc_size (reloc),
1246 size);
1247 else if (pcrel && !reloc->pc_relative)
1248 as_bad (_("non-pc-relative relocation for pc-relative field"));
1249 else if ((reloc->complain_on_overflow == complain_overflow_signed
1250 && !sign)
1251 || (reloc->complain_on_overflow == complain_overflow_unsigned
1252 && sign > 0))
1253 as_bad (_("relocated field and relocation type differ in signedness"));
1254 else
1255 return other;
1256 return NO_RELOC;
1257 }
252b5132
RH		 1258
1259 if (pcrel)
1260 {
3e73aa7c 1261 if (!sign)
3956db08 1262 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1263 switch (size)
1264 {
1265 case 1: return BFD_RELOC_8_PCREL;
1266 case 2: return BFD_RELOC_16_PCREL;
1267 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1268 case 8: return BFD_RELOC_64_PCREL;
252b5132 1269 }
3956db08 1270 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1271 }
1272 else
1273 {
3956db08 1274 if (sign > 0)
e5cb08ac 1275 switch (size)
3e73aa7c
JH		 1276 {
1277 case 4: return BFD_RELOC_X86_64_32S;
1278 }
1279 else
1280 switch (size)
1281 {
1282 case 1: return BFD_RELOC_8;
1283 case 2: return BFD_RELOC_16;
1284 case 4: return BFD_RELOC_32;
1285 case 8: return BFD_RELOC_64;
1286 }
3956db08
JB		 1287 as_bad (_("cannot do %s %u byte relocation"),
1288 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1289 }
1290
bfb32b52 1291 abort ();
252b5132
RH		 1292 return BFD_RELOC_NONE;
1293}
1294
47926f60
KH		 1295/* Here we decide which fixups can be adjusted to make them relative to
1296 the beginning of the section instead of the symbol. Basically we need
1297 to make sure that the dynamic relocations are done correctly, so in
1298 some cases we force the original symbol to be used. */
1299
252b5132 1300int
c0c949c7 1301tc_i386_fix_adjustable (fixP)
31312f95 1302 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1303{
6d249963 1304#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1305 if (!IS_ELF)
31312f95
AM		 1306 return 1;
1307
a161fe53
AM		 1308 /* Don't adjust pc-relative references to merge sections in 64-bit
1309 mode. */
1310 if (use_rela_relocations
1311 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1312 && fixP->fx_pcrel)
252b5132 1313 return 0;
31312f95 1314
8d01d9a9
AJ		 1315 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1316 and changed later by validate_fix. */
1317 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1318 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1319 return 0;
1320
ce8a8b2f 1321 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1322 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1323 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1324 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1325 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1326 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1327 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1328 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1329 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1330 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1331 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1332 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1333 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1334 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1335 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1336 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1337 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1338 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1339 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1340 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1341 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1342 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1343 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1344 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1345 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1346 return 0;
31312f95 1347#endif
252b5132
RH		 1348 return 1;
1349}
252b5132 1350
29b0f896 1351static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1352
1353static int
252b5132 1354intel_float_operand (mnemonic)
29b0f896 1355 const char *mnemonic;
252b5132 1356{
9306ca4a
JB		 1357 /* Note that the value returned is meaningful only for opcodes with (memory)
1358 operands, hence the code here is free to improperly handle opcodes that
1359 have no operands (for better performance and smaller code). */
1360
1361 if (mnemonic[0] != 'f')
1362 return 0; /* non-math */
1363
1364 switch (mnemonic[1])
1365 {
1366 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1367 the fs segment override prefix not currently handled because no
1368 call path can make opcodes without operands get here */
1369 case 'i':
1370 return 2 /* integer op */;
1371 case 'l':
1372 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1373 return 3; /* fldcw/fldenv */
1374 break;
1375 case 'n':
1376 if (mnemonic[2] != 'o' /* fnop */)
1377 return 3; /* non-waiting control op */
1378 break;
1379 case 'r':
1380 if (mnemonic[2] == 's')
1381 return 3; /* frstor/frstpm */
1382 break;
1383 case 's':
1384 if (mnemonic[2] == 'a')
1385 return 3; /* fsave */
1386 if (mnemonic[2] == 't')
1387 {
1388 switch (mnemonic[3])
1389 {
1390 case 'c': /* fstcw */
1391 case 'd': /* fstdw */
1392 case 'e': /* fstenv */
1393 case 's': /* fsts[gw] */
1394 return 3;
1395 }
1396 }
1397 break;
1398 case 'x':
1399 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1400 return 0; /* fxsave/fxrstor are not really math ops */
1401 break;
1402 }
252b5132 1403
9306ca4a 1404 return 1;
252b5132
RH		 1405}
1406
1407/* This is the guts of the machine-dependent assembler. LINE points to a
1408 machine dependent instruction. This function is supposed to emit
1409 the frags/bytes it assembles to. */
1410
1411void
1412md_assemble (line)
1413 char *line;
1414{
252b5132 1415 int j;
252b5132
RH		 1416 char mnemonic[MAX_MNEM_SIZE];
1417
47926f60 1418 /* Initialize globals. */
252b5132
RH		 1419 memset (&i, '\0', sizeof (i));
1420 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1421 i.reloc[j] = NO_RELOC;
252b5132
RH		 1422 memset (disp_expressions, '\0', sizeof (disp_expressions));
1423 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1424 save_stack_p = save_stack;
252b5132
RH		 1425
1426 /* First parse an instruction mnemonic & call i386_operand for the operands.
1427 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1428 start of a (possibly prefixed) mnemonic. */
252b5132 1429
29b0f896
AM		 1430 line = parse_insn (line, mnemonic);
1431 if (line == NULL)
1432 return;
252b5132 1433
29b0f896
AM		 1434 line = parse_operands (line, mnemonic);
1435 if (line == NULL)
1436 return;
252b5132 1437
29b0f896
AM		 1438 /* Now we've parsed the mnemonic into a set of templates, and have the
1439 operands at hand. */
1440
1441 /* All intel opcodes have reversed operands except for "bound" and
1442 "enter". We also don't reverse intersegment "jmp" and "call"
1443 instructions with 2 immediate operands so that the immediate segment
1444 precedes the offset, as it does when in AT&T mode. "enter" and the
1445 intersegment "jmp" and "call" instructions are the only ones that
1446 have two immediate operands. */
1447 if (intel_syntax && i.operands > 1
1448 && (strcmp (mnemonic, "bound") != 0)
30123838 1449 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1450 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1451 swap_operands ();
1452
1453 if (i.imm_operands)
1454 optimize_imm ();
1455
b300c311
L		 1456 /* Don't optimize displacement for movabs since it only takes 64bit
1457 displacement. */
1458 if (i.disp_operands
1459 && (flag_code != CODE_64BIT
1460 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1461 optimize_disp ();
1462
1463 /* Next, we find a template that matches the given insn,
1464 making sure the overlap of the given operands types is consistent
1465 with the template operand types. */
252b5132 1466
29b0f896
AM		 1467 if (!match_template ())
1468 return;
252b5132 1469
cd61ebfe
AM		 1470 if (intel_syntax)
1471 {
1472 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1473 if (SYSV386_COMPAT
1474 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1475 i.tm.base_opcode ^= FloatR;
1476
1477 /* Zap movzx and movsx suffix. The suffix may have been set from
1478 "word ptr" or "byte ptr" on the source operand, but we'll use
1479 the suffix later to choose the destination register. */
1480 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1481 {
1482 if (i.reg_operands < 2
1483 && !i.suffix
1484 && (~i.tm.opcode_modifier
1485 & (No_bSuf
1486 | No_wSuf
1487 | No_lSuf
1488 | No_sSuf
1489 | No_xSuf
1490 | No_qSuf)))
1491 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1492
1493 i.suffix = 0;
1494 }
cd61ebfe 1495 }
24eab124 1496
29b0f896
AM		 1497 if (i.tm.opcode_modifier & FWait)
1498 if (!add_prefix (FWAIT_OPCODE))
1499 return;
252b5132 1500
29b0f896
AM		 1501 /* Check string instruction segment overrides. */
1502 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1503 {
1504 if (!check_string ())
5dd0794d 1505 return;
29b0f896 1506 }
5dd0794d 1507
29b0f896
AM		 1508 if (!process_suffix ())
1509 return;
e413e4e9 1510
29b0f896
AM		 1511 /* Make still unresolved immediate matches conform to size of immediate
1512 given in i.suffix. */
1513 if (!finalize_imm ())
1514 return;
252b5132 1515
29b0f896
AM		 1516 if (i.types[0] & Imm1)
1517 i.imm_operands = 0; /* kludge for shift insns. */
1518 if (i.types[0] & ImplicitRegister)
1519 i.reg_operands--;
1520 if (i.types[1] & ImplicitRegister)
1521 i.reg_operands--;
1522 if (i.types[2] & ImplicitRegister)
1523 i.reg_operands--;
252b5132 1524
29b0f896
AM		 1525 if (i.tm.opcode_modifier & ImmExt)
1526 {
02fc3089
L		 1527 expressionS *exp;
1528
ca164297
L		 1529 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1530 {
67c1ffbe 1531 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1532 operands with an opcode suffix which is coded in the same
1533 place as an 8-bit immediate field would be. Here we check
1534 those operands and remove them afterwards. */
1535 unsigned int x;
1536
a4622f40 1537 for (x = 0; x < i.operands; x++)
ca164297
L		 1538 if (i.op[x].regs->reg_num != x)
1539 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1540 i.op[x].regs->reg_name, x + 1, i.tm.name);
1541 i.operands = 0;
1542 }
1543
29b0f896
AM		 1544 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1545 opcode suffix which is coded in the same place as an 8-bit
1546 immediate field would be. Here we fake an 8-bit immediate
1547 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1548
29b0f896 1549 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1550
29b0f896
AM		 1551 exp = &im_expressions[i.imm_operands++];
1552 i.op[i.operands].imms = exp;
1553 i.types[i.operands++] = Imm8;
1554 exp->X_op = O_constant;
1555 exp->X_add_number = i.tm.extension_opcode;
1556 i.tm.extension_opcode = None;
1557 }
252b5132 1558
29b0f896
AM		 1559 /* For insns with operands there are more diddles to do to the opcode. */
1560 if (i.operands)
1561 {
1562 if (!process_operands ())
1563 return;
1564 }
1565 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1566 {
1567 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1568 as_warn (_("translating to `%sp'"), i.tm.name);
1569 }
252b5132 1570
29b0f896
AM		 1571 /* Handle conversion of 'int $3' --> special int3 insn. */
1572 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1573 {
1574 i.tm.base_opcode = INT3_OPCODE;
1575 i.imm_operands = 0;
1576 }
252b5132 1577
29b0f896
AM		 1578 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1579 && i.op[0].disps->X_op == O_constant)
1580 {
1581 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1582 the absolute address given by the constant. Since ix86 jumps and
1583 calls are pc relative, we need to generate a reloc. */
1584 i.op[0].disps->X_add_symbol = &abs_symbol;
1585 i.op[0].disps->X_op = O_symbol;
1586 }
252b5132 1587
29b0f896
AM		 1588 if ((i.tm.opcode_modifier & Rex64) != 0)
1589 i.rex |= REX_MODE64;
252b5132 1590
29b0f896
AM		 1591 /* For 8 bit registers we need an empty rex prefix. Also if the
1592 instruction already has a prefix, we need to convert old
1593 registers to new ones. */
773f551c 1594
29b0f896
AM		 1595 if (((i.types[0] & Reg8) != 0
1596 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1597 || ((i.types[1] & Reg8) != 0
1598 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1599 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1600 && i.rex != 0))
1601 {
1602 int x;
726c5dcd 1603
29b0f896
AM		 1604 i.rex |= REX_OPCODE;
1605 for (x = 0; x < 2; x++)
1606 {
1607 /* Look for 8 bit operand that uses old registers. */
1608 if ((i.types[x] & Reg8) != 0
1609 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1610 {
29b0f896
AM		 1611 /* In case it is "hi" register, give up. */
1612 if (i.op[x].regs->reg_num > 3)
0477af35 1613 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1614 i.op[x].regs->reg_name);
773f551c 1615
29b0f896
AM		 1616 /* Otherwise it is equivalent to the extended register.
1617 Since the encoding doesn't change this is merely
1618 cosmetic cleanup for debug output. */
1619
1620 i.op[x].regs = i.op[x].regs + 8;
773f551c 1621 }
29b0f896
AM		 1622 }
1623 }
773f551c 1624
29b0f896
AM		 1625 if (i.rex != 0)
1626 add_prefix (REX_OPCODE | i.rex);
1627
1628 /* We are ready to output the insn. */
1629 output_insn ();
1630}
1631
1632static char *
1633parse_insn (line, mnemonic)
1634 char *line;
1635 char *mnemonic;
1636{
1637 char *l = line;
1638 char *token_start = l;
1639 char *mnem_p;
5c6af06e
JB		 1640 int supported;
1641 const template *t;
29b0f896
AM		 1642
1643 /* Non-zero if we found a prefix only acceptable with string insns. */
1644 const char *expecting_string_instruction = NULL;
45288df1 1645
29b0f896
AM		 1646 while (1)
1647 {
1648 mnem_p = mnemonic;
1649 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1650 {
1651 mnem_p++;
1652 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1653 {
29b0f896
AM		 1654 as_bad (_("no such instruction: `%s'"), token_start);
1655 return NULL;
1656 }
1657 l++;
1658 }
1659 if (!is_space_char (*l)
1660 && *l != END_OF_INSN
e44823cf
JB		 1661 && (intel_syntax
1662 || (*l != PREFIX_SEPARATOR
1663 && *l != ',')))
29b0f896
AM		 1664 {
1665 as_bad (_("invalid character %s in mnemonic"),
1666 output_invalid (*l));
1667 return NULL;
1668 }
1669 if (token_start == l)
1670 {
e44823cf 1671 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1672 as_bad (_("expecting prefix; got nothing"));
1673 else
1674 as_bad (_("expecting mnemonic; got nothing"));
1675 return NULL;
1676 }
45288df1 1677
29b0f896
AM		 1678 /* Look up instruction (or prefix) via hash table. */
1679 current_templates = hash_find (op_hash, mnemonic);
47926f60 1680
29b0f896
AM		 1681 if (*l != END_OF_INSN
1682 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1683 && current_templates
1684 && (current_templates->start->opcode_modifier & IsPrefix))
1685 {
2dd88dca
JB		 1686 if (current_templates->start->cpu_flags
1687 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1688 {
1689 as_bad ((flag_code != CODE_64BIT
1690 ? _("`%s' is only supported in 64-bit mode")
1691 : _("`%s' is not supported in 64-bit mode")),
1692 current_templates->start->name);
1693 return NULL;
1694 }
29b0f896
AM		 1695 /* If we are in 16-bit mode, do not allow addr16 or data16.
1696 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1697 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1698 && flag_code != CODE_64BIT
1699 && (((current_templates->start->opcode_modifier & Size32) != 0)
1700 ^ (flag_code == CODE_16BIT)))
1701 {
1702 as_bad (_("redundant %s prefix"),
1703 current_templates->start->name);
1704 return NULL;
45288df1 1705 }
29b0f896
AM		 1706 /* Add prefix, checking for repeated prefixes. */
1707 switch (add_prefix (current_templates->start->base_opcode))
1708 {
1709 case 0:
1710 return NULL;
1711 case 2:
1712 expecting_string_instruction = current_templates->start->name;
1713 break;
1714 }
1715 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1716 token_start = ++l;
1717 }
1718 else
1719 break;
1720 }
45288df1 1721
29b0f896
AM		 1722 if (!current_templates)
1723 {
1724 /* See if we can get a match by trimming off a suffix. */
1725 switch (mnem_p[-1])
1726 {
1727 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1728 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1729 i.suffix = SHORT_MNEM_SUFFIX;
1730 else
29b0f896
AM		 1731 case BYTE_MNEM_SUFFIX:
1732 case QWORD_MNEM_SUFFIX:
1733 i.suffix = mnem_p[-1];
1734 mnem_p[-1] = '\0';
1735 current_templates = hash_find (op_hash, mnemonic);
1736 break;
1737 case SHORT_MNEM_SUFFIX:
1738 case LONG_MNEM_SUFFIX:
1739 if (!intel_syntax)
1740 {
1741 i.suffix = mnem_p[-1];
1742 mnem_p[-1] = '\0';
1743 current_templates = hash_find (op_hash, mnemonic);
1744 }
1745 break;
252b5132 1746
29b0f896
AM		 1747 /* Intel Syntax. */
1748 case 'd':
1749 if (intel_syntax)
1750 {
9306ca4a 1751 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1752 i.suffix = SHORT_MNEM_SUFFIX;
1753 else
1754 i.suffix = LONG_MNEM_SUFFIX;
1755 mnem_p[-1] = '\0';
1756 current_templates = hash_find (op_hash, mnemonic);
1757 }
1758 break;
1759 }
1760 if (!current_templates)
1761 {
1762 as_bad (_("no such instruction: `%s'"), token_start);
1763 return NULL;
1764 }
1765 }
252b5132 1766
29b0f896
AM		 1767 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1768 {
1769 /* Check for a branch hint. We allow ",pt" and ",pn" for
1770 predict taken and predict not taken respectively.
1771 I'm not sure that branch hints actually do anything on loop
1772 and jcxz insns (JumpByte) for current Pentium4 chips. They
1773 may work in the future and it doesn't hurt to accept them
1774 now. */
1775 if (l[0] == ',' && l[1] == 'p')
1776 {
1777 if (l[2] == 't')
1778 {
1779 if (!add_prefix (DS_PREFIX_OPCODE))
1780 return NULL;
1781 l += 3;
1782 }
1783 else if (l[2] == 'n')
1784 {
1785 if (!add_prefix (CS_PREFIX_OPCODE))
1786 return NULL;
1787 l += 3;
1788 }
1789 }
1790 }
1791 /* Any other comma loses. */
1792 if (*l == ',')
1793 {
1794 as_bad (_("invalid character %s in mnemonic"),
1795 output_invalid (*l));
1796 return NULL;
1797 }
252b5132 1798
29b0f896 1799 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1800 supported = 0;
1801 for (t = current_templates->start; t < current_templates->end; ++t)
1802 {
1803 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1804 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1805 supported |= 1;
1806 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1807 supported |= 2;
1808 }
1809 if (!(supported & 2))
1810 {
1811 as_bad (flag_code == CODE_64BIT
1812 ? _("`%s' is not supported in 64-bit mode")
1813 : _("`%s' is only supported in 64-bit mode"),
1814 current_templates->start->name);
1815 return NULL;
1816 }
1817 if (!(supported & 1))
29b0f896 1818 {
5c6af06e
JB		 1819 as_warn (_("`%s' is not supported on `%s%s'"),
1820 current_templates->start->name,
1821 cpu_arch_name,
1822 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1823 }
1824 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1825 {
1826 as_warn (_("use .code16 to ensure correct addressing mode"));
1827 }
252b5132 1828
29b0f896 1829 /* Check for rep/repne without a string instruction. */
f41bbced 1830 if (expecting_string_instruction)
29b0f896 1831 {
f41bbced
JB		 1832 static templates override;
1833
1834 for (t = current_templates->start; t < current_templates->end; ++t)
1835 if (t->opcode_modifier & IsString)
1836 break;
1837 if (t >= current_templates->end)
1838 {
1839 as_bad (_("expecting string instruction after `%s'"),
1840 expecting_string_instruction);
1841 return NULL;
1842 }
1843 for (override.start = t; t < current_templates->end; ++t)
1844 if (!(t->opcode_modifier & IsString))
1845 break;
1846 override.end = t;
1847 current_templates = &override;
29b0f896 1848 }
252b5132 1849
29b0f896
AM		 1850 return l;
1851}
252b5132 1852
29b0f896
AM		 1853static char *
1854parse_operands (l, mnemonic)
1855 char *l;
1856 const char *mnemonic;
1857{
1858 char *token_start;
3138f287 1859
29b0f896
AM		 1860 /* 1 if operand is pending after ','. */
1861 unsigned int expecting_operand = 0;
252b5132 1862
29b0f896
AM		 1863 /* Non-zero if operand parens not balanced. */
1864 unsigned int paren_not_balanced;
1865
1866 while (*l != END_OF_INSN)
1867 {
1868 /* Skip optional white space before operand. */
1869 if (is_space_char (*l))
1870 ++l;
1871 if (!is_operand_char (*l) && *l != END_OF_INSN)
1872 {
1873 as_bad (_("invalid character %s before operand %d"),
1874 output_invalid (*l),
1875 i.operands + 1);
1876 return NULL;
1877 }
1878 token_start = l; /* after white space */
1879 paren_not_balanced = 0;
1880 while (paren_not_balanced || *l != ',')
1881 {
1882 if (*l == END_OF_INSN)
1883 {
1884 if (paren_not_balanced)
1885 {
1886 if (!intel_syntax)
1887 as_bad (_("unbalanced parenthesis in operand %d."),
1888 i.operands + 1);
1889 else
1890 as_bad (_("unbalanced brackets in operand %d."),
1891 i.operands + 1);
1892 return NULL;
1893 }
1894 else
1895 break; /* we are done */
1896 }
1897 else if (!is_operand_char (*l) && !is_space_char (*l))
1898 {
1899 as_bad (_("invalid character %s in operand %d"),
1900 output_invalid (*l),
1901 i.operands + 1);
1902 return NULL;
1903 }
1904 if (!intel_syntax)
1905 {
1906 if (*l == '(')
1907 ++paren_not_balanced;
1908 if (*l == ')')
1909 --paren_not_balanced;
1910 }
1911 else
1912 {
1913 if (*l == '[')
1914 ++paren_not_balanced;
1915 if (*l == ']')
1916 --paren_not_balanced;
1917 }
1918 l++;
1919 }
1920 if (l != token_start)
1921 { /* Yes, we've read in another operand. */
1922 unsigned int operand_ok;
1923 this_operand = i.operands++;
1924 if (i.operands > MAX_OPERANDS)
1925 {
1926 as_bad (_("spurious operands; (%d operands/instruction max)"),
1927 MAX_OPERANDS);
1928 return NULL;
1929 }
1930 /* Now parse operand adding info to 'i' as we go along. */
1931 END_STRING_AND_SAVE (l);
1932
1933 if (intel_syntax)
1934 operand_ok =
1935 i386_intel_operand (token_start,
1936 intel_float_operand (mnemonic));
1937 else
1938 operand_ok = i386_operand (token_start);
1939
1940 RESTORE_END_STRING (l);
1941 if (!operand_ok)
1942 return NULL;
1943 }
1944 else
1945 {
1946 if (expecting_operand)
1947 {
1948 expecting_operand_after_comma:
1949 as_bad (_("expecting operand after ','; got nothing"));
1950 return NULL;
1951 }
1952 if (*l == ',')
1953 {
1954 as_bad (_("expecting operand before ','; got nothing"));
1955 return NULL;
1956 }
1957 }
7f3f1ea2 1958
29b0f896
AM		 1959 /* Now *l must be either ',' or END_OF_INSN. */
1960 if (*l == ',')
1961 {
1962 if (*++l == END_OF_INSN)
1963 {
1964 /* Just skip it, if it's \n complain. */
1965 goto expecting_operand_after_comma;
1966 }
1967 expecting_operand = 1;
1968 }
1969 }
1970 return l;
1971}
7f3f1ea2 1972
29b0f896
AM		 1973static void
1974swap_operands ()
1975{
1976 union i386_op temp_op;
1977 unsigned int temp_type;
f86103b7 1978 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1979 int xchg1 = 0;
1980 int xchg2 = 0;
252b5132 1981
29b0f896
AM		 1982 if (i.operands == 2)
1983 {
1984 xchg1 = 0;
1985 xchg2 = 1;
1986 }
1987 else if (i.operands == 3)
1988 {
1989 xchg1 = 0;
1990 xchg2 = 2;
1991 }
1992 temp_type = i.types[xchg2];
1993 i.types[xchg2] = i.types[xchg1];
1994 i.types[xchg1] = temp_type;
1995 temp_op = i.op[xchg2];
1996 i.op[xchg2] = i.op[xchg1];
1997 i.op[xchg1] = temp_op;
1998 temp_reloc = i.reloc[xchg2];
1999 i.reloc[xchg2] = i.reloc[xchg1];
2000 i.reloc[xchg1] = temp_reloc;
2001
2002 if (i.mem_operands == 2)
2003 {
2004 const seg_entry *temp_seg;
2005 temp_seg = i.seg[0];
2006 i.seg[0] = i.seg[1];
2007 i.seg[1] = temp_seg;
2008 }
2009}
252b5132 2010
29b0f896
AM		 2011/* Try to ensure constant immediates are represented in the smallest
2012 opcode possible. */
2013static void
2014optimize_imm ()
2015{
2016 char guess_suffix = 0;
2017 int op;
252b5132 2018
29b0f896
AM		 2019 if (i.suffix)
2020 guess_suffix = i.suffix;
2021 else if (i.reg_operands)
2022 {
2023 /* Figure out a suffix from the last register operand specified.
2024 We can't do this properly yet, ie. excluding InOutPortReg,
2025 but the following works for instructions with immediates.
2026 In any case, we can't set i.suffix yet. */
2027 for (op = i.operands; --op >= 0;)
2028 if (i.types[op] & Reg)
252b5132 2029 {
29b0f896
AM		 2030 if (i.types[op] & Reg8)
2031 guess_suffix = BYTE_MNEM_SUFFIX;
2032 else if (i.types[op] & Reg16)
2033 guess_suffix = WORD_MNEM_SUFFIX;
2034 else if (i.types[op] & Reg32)
2035 guess_suffix = LONG_MNEM_SUFFIX;
2036 else if (i.types[op] & Reg64)
2037 guess_suffix = QWORD_MNEM_SUFFIX;
2038 break;
252b5132 2039 }
29b0f896
AM		 2040 }
2041 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2042 guess_suffix = WORD_MNEM_SUFFIX;
2043
2044 for (op = i.operands; --op >= 0;)
2045 if (i.types[op] & Imm)
2046 {
2047 switch (i.op[op].imms->X_op)
252b5132 2048 {
29b0f896
AM		 2049 case O_constant:
2050 /* If a suffix is given, this operand may be shortened. */
2051 switch (guess_suffix)
252b5132 2052 {
29b0f896
AM		 2053 case LONG_MNEM_SUFFIX:
2054 i.types[op] |= Imm32 | Imm64;
2055 break;
2056 case WORD_MNEM_SUFFIX:
2057 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2058 break;
2059 case BYTE_MNEM_SUFFIX:
2060 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2061 break;
252b5132 2062 }
252b5132 2063
29b0f896
AM		 2064 /* If this operand is at most 16 bits, convert it
2065 to a signed 16 bit number before trying to see
2066 whether it will fit in an even smaller size.
2067 This allows a 16-bit operand such as $0xffe0 to
2068 be recognised as within Imm8S range. */
2069 if ((i.types[op] & Imm16)
2070 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2071 {
29b0f896
AM		 2072 i.op[op].imms->X_add_number =
2073 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2074 }
2075 if ((i.types[op] & Imm32)
2076 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2077 == 0))
2078 {
2079 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2080 ^ ((offsetT) 1 << 31))
2081 - ((offsetT) 1 << 31));
2082 }
2083 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2084
29b0f896
AM		 2085 /* We must avoid matching of Imm32 templates when 64bit
2086 only immediate is available. */
2087 if (guess_suffix == QWORD_MNEM_SUFFIX)
2088 i.types[op] &= ~Imm32;
2089 break;
252b5132 2090
29b0f896
AM		 2091 case O_absent:
2092 case O_register:
2093 abort ();
2094
2095 /* Symbols and expressions. */
2096 default:
9cd96992
JB		 2097 /* Convert symbolic operand to proper sizes for matching, but don't
2098 prevent matching a set of insns that only supports sizes other
2099 than those matching the insn suffix. */
2100 {
2101 unsigned int mask, allowed = 0;
2102 const template *t;
2103
2104 for (t = current_templates->start; t < current_templates->end; ++t)
2105 allowed |= t->operand_types[op];
2106 switch (guess_suffix)
2107 {
2108 case QWORD_MNEM_SUFFIX:
2109 mask = Imm64 | Imm32S;
2110 break;
2111 case LONG_MNEM_SUFFIX:
2112 mask = Imm32;
2113 break;
2114 case WORD_MNEM_SUFFIX:
2115 mask = Imm16;
2116 break;
2117 case BYTE_MNEM_SUFFIX:
2118 mask = Imm8;
2119 break;
2120 default:
2121 mask = 0;
2122 break;
2123 }
2124 if (mask & allowed)
2125 i.types[op] &= mask;
2126 }
29b0f896 2127 break;
252b5132 2128 }
29b0f896
AM		 2129 }
2130}
47926f60 2131
29b0f896
AM		 2132/* Try to use the smallest displacement type too. */
2133static void
2134optimize_disp ()
2135{
2136 int op;
3e73aa7c 2137
29b0f896 2138 for (op = i.operands; --op >= 0;)
b300c311 2139 if (i.types[op] & Disp)
252b5132 2140 {
b300c311 2141 if (i.op[op].disps->X_op == O_constant)
252b5132 2142 {
b300c311 2143 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2144
b300c311
L		 2145 if ((i.types[op] & Disp16)
2146 && (disp & ~(offsetT) 0xffff) == 0)
2147 {
2148 /* If this operand is at most 16 bits, convert
2149 to a signed 16 bit number and don't use 64bit
2150 displacement. */
2151 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2152 i.types[op] &= ~Disp64;
2153 }
2154 if ((i.types[op] & Disp32)
2155 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2156 {
2157 /* If this operand is at most 32 bits, convert
2158 to a signed 32 bit number and don't use 64bit
2159 displacement. */
2160 disp &= (((offsetT) 2 << 31) - 1);
2161 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2162 i.types[op] &= ~Disp64;
2163 }
2164 if (!disp && (i.types[op] & BaseIndex))
2165 {
2166 i.types[op] &= ~Disp;
2167 i.op[op].disps = 0;
2168 i.disp_operands--;
2169 }
2170 else if (flag_code == CODE_64BIT)
2171 {
2172 if (fits_in_signed_long (disp))
28a9d8f5
L		 2173 {
2174 i.types[op] &= ~Disp64;
2175 i.types[op] |= Disp32S;
2176 }
b300c311
L		 2177 if (fits_in_unsigned_long (disp))
2178 i.types[op] |= Disp32;
2179 }
2180 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2181 && fits_in_signed_byte (disp))
2182 i.types[op] |= Disp8;
252b5132 2183 }
b300c311
L		 2184 else
2185 /* We only support 64bit displacement on constants. */
2186 i.types[op] &= ~Disp64;
252b5132 2187 }
29b0f896
AM		 2188}
2189
2190static int
2191match_template ()
2192{
2193 /* Points to template once we've found it. */
2194 const template *t;
2195 unsigned int overlap0, overlap1, overlap2;
2196 unsigned int found_reverse_match;
2197 int suffix_check;
2198
2199#define MATCH(overlap, given, template) \
2200 ((overlap & ~JumpAbsolute) \
2201 && (((given) & (BaseIndex | JumpAbsolute)) \
2202 == ((overlap) & (BaseIndex | JumpAbsolute))))
2203
2204 /* If given types r0 and r1 are registers they must be of the same type
2205 unless the expected operand type register overlap is null.
2206 Note that Acc in a template matches every size of reg. */
2207#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2208 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2209 || ((g0) & Reg) == ((g1) & Reg) \
2210 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2211
2212 overlap0 = 0;
2213 overlap1 = 0;
2214 overlap2 = 0;
2215 found_reverse_match = 0;
2216 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2217 ? No_bSuf
2218 : (i.suffix == WORD_MNEM_SUFFIX
2219 ? No_wSuf
2220 : (i.suffix == SHORT_MNEM_SUFFIX
2221 ? No_sSuf
2222 : (i.suffix == LONG_MNEM_SUFFIX
2223 ? No_lSuf
2224 : (i.suffix == QWORD_MNEM_SUFFIX
2225 ? No_qSuf
2226 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2227 ? No_xSuf : 0))))));
2228
20f0a1fc
NC		 2229 t = current_templates->start;
2230 if (i.suffix == QWORD_MNEM_SUFFIX
2231 && flag_code != CODE_64BIT
9306ca4a
JB		 2232 && (intel_syntax
2233 ? !(t->opcode_modifier & IgnoreSize)
2234 && !intel_float_operand (t->name)
2235 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2236 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2237 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2238 && (t->base_opcode != 0x0fc7
2239 || t->extension_opcode != 1 /* cmpxchg8b */))
2240 t = current_templates->end;
2241 for (; t < current_templates->end; t++)
29b0f896
AM		 2242 {
2243 /* Must have right number of operands. */
2244 if (i.operands != t->operands)
2245 continue;
2246
2247 /* Check the suffix, except for some instructions in intel mode. */
2248 if ((t->opcode_modifier & suffix_check)
2249 && !(intel_syntax
9306ca4a 2250 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2251 continue;
2252
2253 /* Do not verify operands when there are none. */
2254 else if (!t->operands)
2255 {
2256 if (t->cpu_flags & ~cpu_arch_flags)
2257 continue;
2258 /* We've found a match; break out of loop. */
2259 break;
2260 }
252b5132 2261
29b0f896
AM		 2262 overlap0 = i.types[0] & t->operand_types[0];
2263 switch (t->operands)
2264 {
2265 case 1:
2266 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2267 continue;
2268 break;
2269 case 2:
2270 case 3:
2271 overlap1 = i.types[1] & t->operand_types[1];
2272 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2273 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2274 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2275 t->operand_types[0],
2276 overlap1, i.types[1],
2277 t->operand_types[1]))
2278 {
2279 /* Check if other direction is valid ... */
2280 if ((t->opcode_modifier & (D | FloatD)) == 0)
2281 continue;
2282
2283 /* Try reversing direction of operands. */
2284 overlap0 = i.types[0] & t->operand_types[1];
2285 overlap1 = i.types[1] & t->operand_types[0];
2286 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2287 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2288 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2289 t->operand_types[1],
2290 overlap1, i.types[1],
2291 t->operand_types[0]))
2292 {
2293 /* Does not match either direction. */
2294 continue;
2295 }
2296 /* found_reverse_match holds which of D or FloatDR
2297 we've found. */
2298 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2299 }
2300 /* Found a forward 2 operand match here. */
2301 else if (t->operands == 3)
2302 {
2303 /* Here we make use of the fact that there are no
2304 reverse match 3 operand instructions, and all 3
2305 operand instructions only need to be checked for
2306 register consistency between operands 2 and 3. */
2307 overlap2 = i.types[2] & t->operand_types[2];
2308 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2309 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2310 t->operand_types[1],
2311 overlap2, i.types[2],
2312 t->operand_types[2]))
2313
2314 continue;
2315 }
2316 /* Found either forward/reverse 2 or 3 operand match here:
2317 slip through to break. */
2318 }
2319 if (t->cpu_flags & ~cpu_arch_flags)
2320 {
2321 found_reverse_match = 0;
2322 continue;
2323 }
2324 /* We've found a match; break out of loop. */
2325 break;
2326 }
2327
2328 if (t == current_templates->end)
2329 {
2330 /* We found no match. */
2331 as_bad (_("suffix or operands invalid for `%s'"),
2332 current_templates->start->name);
2333 return 0;
2334 }
252b5132 2335
29b0f896
AM		 2336 if (!quiet_warnings)
2337 {
2338 if (!intel_syntax
2339 && ((i.types[0] & JumpAbsolute)
2340 != (t->operand_types[0] & JumpAbsolute)))
2341 {
2342 as_warn (_("indirect %s without `*'"), t->name);
2343 }
2344
2345 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2346 == (IsPrefix | IgnoreSize))
2347 {
2348 /* Warn them that a data or address size prefix doesn't
2349 affect assembly of the next line of code. */
2350 as_warn (_("stand-alone `%s' prefix"), t->name);
2351 }
2352 }
2353
2354 /* Copy the template we found. */
2355 i.tm = *t;
2356 if (found_reverse_match)
2357 {
2358 /* If we found a reverse match we must alter the opcode
2359 direction bit. found_reverse_match holds bits to change
2360 (different for int & float insns). */
2361
2362 i.tm.base_opcode ^= found_reverse_match;
2363
2364 i.tm.operand_types[0] = t->operand_types[1];
2365 i.tm.operand_types[1] = t->operand_types[0];
2366 }
2367
2368 return 1;
2369}
2370
2371static int
2372check_string ()
2373{
2374 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2375 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2376 {
2377 if (i.seg[0] != NULL && i.seg[0] != &es)
2378 {
2379 as_bad (_("`%s' operand %d must use `%%es' segment"),
2380 i.tm.name,
2381 mem_op + 1);
2382 return 0;
2383 }
2384 /* There's only ever one segment override allowed per instruction.
2385 This instruction possibly has a legal segment override on the
2386 second operand, so copy the segment to where non-string
2387 instructions store it, allowing common code. */
2388 i.seg[0] = i.seg[1];
2389 }
2390 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2391 {
2392 if (i.seg[1] != NULL && i.seg[1] != &es)
2393 {
2394 as_bad (_("`%s' operand %d must use `%%es' segment"),
2395 i.tm.name,
2396 mem_op + 2);
2397 return 0;
2398 }
2399 }
2400 return 1;
2401}
2402
2403static int
543613e9 2404process_suffix (void)
29b0f896
AM		 2405{
2406 /* If matched instruction specifies an explicit instruction mnemonic
2407 suffix, use it. */
2408 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2409 {
2410 if (i.tm.opcode_modifier & Size16)
2411 i.suffix = WORD_MNEM_SUFFIX;
2412 else if (i.tm.opcode_modifier & Size64)
2413 i.suffix = QWORD_MNEM_SUFFIX;
2414 else
2415 i.suffix = LONG_MNEM_SUFFIX;
2416 }
2417 else if (i.reg_operands)
2418 {
2419 /* If there's no instruction mnemonic suffix we try to invent one
2420 based on register operands. */
2421 if (!i.suffix)
2422 {
2423 /* We take i.suffix from the last register operand specified,
2424 Destination register type is more significant than source
2425 register type. */
2426 int op;
543613e9 2427
29b0f896
AM		 2428 for (op = i.operands; --op >= 0;)
2429 if ((i.types[op] & Reg)
2430 && !(i.tm.operand_types[op] & InOutPortReg))
2431 {
2432 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2433 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2434 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2435 LONG_MNEM_SUFFIX);
2436 break;
2437 }
2438 }
2439 else if (i.suffix == BYTE_MNEM_SUFFIX)
2440 {
2441 if (!check_byte_reg ())
2442 return 0;
2443 }
2444 else if (i.suffix == LONG_MNEM_SUFFIX)
2445 {
2446 if (!check_long_reg ())
2447 return 0;
2448 }
2449 else if (i.suffix == QWORD_MNEM_SUFFIX)
2450 {
2451 if (!check_qword_reg ())
2452 return 0;
2453 }
2454 else if (i.suffix == WORD_MNEM_SUFFIX)
2455 {
2456 if (!check_word_reg ())
2457 return 0;
2458 }
2459 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2460 /* Do nothing if the instruction is going to ignore the prefix. */
2461 ;
2462 else
2463 abort ();
2464 }
9306ca4a
JB		 2465 else if ((i.tm.opcode_modifier & DefaultSize)
2466 && !i.suffix
2467 /* exclude fldenv/frstor/fsave/fstenv */
2468 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2469 {
2470 i.suffix = stackop_size;
2471 }
9306ca4a
JB		 2472 else if (intel_syntax
2473 && !i.suffix
2474 && ((i.tm.operand_types[0] & JumpAbsolute)
2475 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2476 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2477 && i.tm.extension_opcode <= 3)))
2478 {
2479 switch (flag_code)
2480 {
2481 case CODE_64BIT:
2482 if (!(i.tm.opcode_modifier & No_qSuf))
2483 {
2484 i.suffix = QWORD_MNEM_SUFFIX;
2485 break;
2486 }
2487 case CODE_32BIT:
2488 if (!(i.tm.opcode_modifier & No_lSuf))
2489 i.suffix = LONG_MNEM_SUFFIX;
2490 break;
2491 case CODE_16BIT:
2492 if (!(i.tm.opcode_modifier & No_wSuf))
2493 i.suffix = WORD_MNEM_SUFFIX;
2494 break;
2495 }
2496 }
252b5132 2497
9306ca4a 2498 if (!i.suffix)
29b0f896 2499 {
9306ca4a
JB		 2500 if (!intel_syntax)
2501 {
2502 if (i.tm.opcode_modifier & W)
2503 {
2504 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2505 return 0;
2506 }
2507 }
2508 else
2509 {
2510 unsigned int suffixes = ~i.tm.opcode_modifier
2511 & (No_bSuf
2512 | No_wSuf
2513 | No_lSuf
2514 | No_sSuf
2515 | No_xSuf
2516 | No_qSuf);
2517
2518 if ((i.tm.opcode_modifier & W)
2519 || ((suffixes & (suffixes - 1))
2520 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2521 {
2522 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2523 return 0;
2524 }
2525 }
29b0f896 2526 }
252b5132 2527
9306ca4a
JB		 2528 /* Change the opcode based on the operand size given by i.suffix;
2529 We don't need to change things for byte insns. */
2530
29b0f896
AM		 2531 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2532 {
2533 /* It's not a byte, select word/dword operation. */
2534 if (i.tm.opcode_modifier & W)
2535 {
2536 if (i.tm.opcode_modifier & ShortForm)
2537 i.tm.base_opcode |= 8;
2538 else
2539 i.tm.base_opcode |= 1;
2540 }
0f3f3d8b 2541
29b0f896
AM		 2542 /* Now select between word & dword operations via the operand
2543 size prefix, except for instructions that will ignore this
2544 prefix anyway. */
2545 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2546 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2547 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2548 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2549 || (flag_code == CODE_64BIT
2550 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2551 {
2552 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2553
29b0f896
AM		 2554 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2555 prefix = ADDR_PREFIX_OPCODE;
252b5132 2556
29b0f896
AM		 2557 if (!add_prefix (prefix))
2558 return 0;
24eab124 2559 }
252b5132 2560
29b0f896
AM		 2561 /* Set mode64 for an operand. */
2562 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2563 && flag_code == CODE_64BIT
29b0f896 2564 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2565 i.rex |= REX_MODE64;
3e73aa7c 2566
29b0f896
AM		 2567 /* Size floating point instruction. */
2568 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2569 if (i.tm.opcode_modifier & FloatMF)
2570 i.tm.base_opcode ^= 4;
29b0f896 2571 }
7ecd2f8b 2572
29b0f896
AM		 2573 return 1;
2574}
3e73aa7c 2575
29b0f896 2576static int
543613e9 2577check_byte_reg (void)
29b0f896
AM		 2578{
2579 int op;
543613e9 2580
29b0f896
AM		 2581 for (op = i.operands; --op >= 0;)
2582 {
2583 /* If this is an eight bit register, it's OK. If it's the 16 or
2584 32 bit version of an eight bit register, we will just use the
2585 low portion, and that's OK too. */
2586 if (i.types[op] & Reg8)
2587 continue;
2588
2589 /* movzx and movsx should not generate this warning. */
2590 if (intel_syntax
2591 && (i.tm.base_opcode == 0xfb7
2592 || i.tm.base_opcode == 0xfb6
2593 || i.tm.base_opcode == 0x63
2594 || i.tm.base_opcode == 0xfbe
2595 || i.tm.base_opcode == 0xfbf))
2596 continue;
2597
65ec77d2 2598 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2599 {
2600 /* Prohibit these changes in the 64bit mode, since the
2601 lowering is more complicated. */
2602 if (flag_code == CODE_64BIT
2603 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2604 {
0f3f3d8b 2605 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2606 i.op[op].regs->reg_name,
2607 i.suffix);
2608 return 0;
2609 }
2610#if REGISTER_WARNINGS
2611 if (!quiet_warnings
2612 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2613 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2614 (i.op[op].regs + (i.types[op] & Reg16
2615 ? REGNAM_AL - REGNAM_AX
2616 : REGNAM_AL - REGNAM_EAX))->reg_name,
2617 i.op[op].regs->reg_name,
2618 i.suffix);
2619#endif
2620 continue;
2621 }
2622 /* Any other register is bad. */
2623 if (i.types[op] & (Reg | RegMMX | RegXMM
2624 | SReg2 | SReg3
2625 | Control | Debug | Test
2626 | FloatReg | FloatAcc))
2627 {
2628 as_bad (_("`%%%s' not allowed with `%s%c'"),
2629 i.op[op].regs->reg_name,
2630 i.tm.name,
2631 i.suffix);
2632 return 0;
2633 }
2634 }
2635 return 1;
2636}
2637
2638static int
2639check_long_reg ()
2640{
2641 int op;
2642
2643 for (op = i.operands; --op >= 0;)
2644 /* Reject eight bit registers, except where the template requires
2645 them. (eg. movzb) */
2646 if ((i.types[op] & Reg8) != 0
2647 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2648 {
2649 as_bad (_("`%%%s' not allowed with `%s%c'"),
2650 i.op[op].regs->reg_name,
2651 i.tm.name,
2652 i.suffix);
2653 return 0;
2654 }
2655 /* Warn if the e prefix on a general reg is missing. */
2656 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2657 && (i.types[op] & Reg16) != 0
2658 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2659 {
2660 /* Prohibit these changes in the 64bit mode, since the
2661 lowering is more complicated. */
2662 if (flag_code == CODE_64BIT)
252b5132 2663 {
0f3f3d8b 2664 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2665 i.op[op].regs->reg_name,
2666 i.suffix);
2667 return 0;
252b5132 2668 }
29b0f896
AM		 2669#if REGISTER_WARNINGS
2670 else
2671 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2672 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2673 i.op[op].regs->reg_name,
2674 i.suffix);
2675#endif
252b5132 2676 }
29b0f896
AM		 2677 /* Warn if the r prefix on a general reg is missing. */
2678 else if ((i.types[op] & Reg64) != 0
2679 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2680 {
0f3f3d8b 2681 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2682 i.op[op].regs->reg_name,
2683 i.suffix);
2684 return 0;
2685 }
2686 return 1;
2687}
252b5132 2688
29b0f896
AM		 2689static int
2690check_qword_reg ()
2691{
2692 int op;
252b5132 2693
29b0f896
AM		 2694 for (op = i.operands; --op >= 0; )
2695 /* Reject eight bit registers, except where the template requires
2696 them. (eg. movzb) */
2697 if ((i.types[op] & Reg8) != 0
2698 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2699 {
2700 as_bad (_("`%%%s' not allowed with `%s%c'"),
2701 i.op[op].regs->reg_name,
2702 i.tm.name,
2703 i.suffix);
2704 return 0;
2705 }
2706 /* Warn if the e prefix on a general reg is missing. */
2707 else if (((i.types[op] & Reg16) != 0
2708 || (i.types[op] & Reg32) != 0)
2709 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2710 {
2711 /* Prohibit these changes in the 64bit mode, since the
2712 lowering is more complicated. */
0f3f3d8b 2713 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2714 i.op[op].regs->reg_name,
2715 i.suffix);
2716 return 0;
252b5132 2717 }
29b0f896
AM		 2718 return 1;
2719}
252b5132 2720
29b0f896
AM		 2721static int
2722check_word_reg ()
2723{
2724 int op;
2725 for (op = i.operands; --op >= 0;)
2726 /* Reject eight bit registers, except where the template requires
2727 them. (eg. movzb) */
2728 if ((i.types[op] & Reg8) != 0
2729 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2730 {
2731 as_bad (_("`%%%s' not allowed with `%s%c'"),
2732 i.op[op].regs->reg_name,
2733 i.tm.name,
2734 i.suffix);
2735 return 0;
2736 }
2737 /* Warn if the e prefix on a general reg is present. */
2738 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2739 && (i.types[op] & Reg32) != 0
2740 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2741 {
29b0f896
AM		 2742 /* Prohibit these changes in the 64bit mode, since the
2743 lowering is more complicated. */
2744 if (flag_code == CODE_64BIT)
252b5132 2745 {
0f3f3d8b 2746 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2747 i.op[op].regs->reg_name,
2748 i.suffix);
2749 return 0;
252b5132 2750 }
29b0f896
AM		 2751 else
2752#if REGISTER_WARNINGS
2753 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2754 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2755 i.op[op].regs->reg_name,
2756 i.suffix);
2757#endif
2758 }
2759 return 1;
2760}
252b5132 2761
29b0f896
AM		 2762static int
2763finalize_imm ()
2764{
2765 unsigned int overlap0, overlap1, overlap2;
2766
2767 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2768 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2769 && overlap0 != Imm8 && overlap0 != Imm8S
2770 && overlap0 != Imm16 && overlap0 != Imm32S
2771 && overlap0 != Imm32 && overlap0 != Imm64)
2772 {
2773 if (i.suffix)
2774 {
2775 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2776 ? Imm8 | Imm8S
2777 : (i.suffix == WORD_MNEM_SUFFIX
2778 ? Imm16
2779 : (i.suffix == QWORD_MNEM_SUFFIX
2780 ? Imm64 | Imm32S
2781 : Imm32)));
2782 }
2783 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2784 || overlap0 == (Imm16 | Imm32)
2785 || overlap0 == (Imm16 | Imm32S))
2786 {
2787 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2788 ? Imm16 : Imm32S);
2789 }
2790 if (overlap0 != Imm8 && overlap0 != Imm8S
2791 && overlap0 != Imm16 && overlap0 != Imm32S
2792 && overlap0 != Imm32 && overlap0 != Imm64)
2793 {
2794 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2795 return 0;
2796 }
2797 }
2798 i.types[0] = overlap0;
2799
2800 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2801 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2802 && overlap1 != Imm8 && overlap1 != Imm8S
2803 && overlap1 != Imm16 && overlap1 != Imm32S
2804 && overlap1 != Imm32 && overlap1 != Imm64)
2805 {
2806 if (i.suffix)
2807 {
2808 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2809 ? Imm8 | Imm8S
2810 : (i.suffix == WORD_MNEM_SUFFIX
2811 ? Imm16
2812 : (i.suffix == QWORD_MNEM_SUFFIX
2813 ? Imm64 | Imm32S
2814 : Imm32)));
2815 }
2816 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2817 || overlap1 == (Imm16 | Imm32)
2818 || overlap1 == (Imm16 | Imm32S))
2819 {
2820 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2821 ? Imm16 : Imm32S);
2822 }
2823 if (overlap1 != Imm8 && overlap1 != Imm8S
2824 && overlap1 != Imm16 && overlap1 != Imm32S
2825 && overlap1 != Imm32 && overlap1 != Imm64)
2826 {
2827 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2828 return 0;
2829 }
2830 }
2831 i.types[1] = overlap1;
2832
2833 overlap2 = i.types[2] & i.tm.operand_types[2];
2834 assert ((overlap2 & Imm) == 0);
2835 i.types[2] = overlap2;
2836
2837 return 1;
2838}
2839
2840static int
2841process_operands ()
2842{
2843 /* Default segment register this instruction will use for memory
2844 accesses. 0 means unknown. This is only for optimizing out
2845 unnecessary segment overrides. */
2846 const seg_entry *default_seg = 0;
2847
2848 /* The imul $imm, %reg instruction is converted into
2849 imul $imm, %reg, %reg, and the clr %reg instruction
2850 is converted into xor %reg, %reg. */
2851 if (i.tm.opcode_modifier & regKludge)
2852 {
2853 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2854 /* Pretend we saw the extra register operand. */
2855 assert (i.op[first_reg_op + 1].regs == 0);
2856 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2857 i.types[first_reg_op + 1] = i.types[first_reg_op];
2858 i.reg_operands = 2;
2859 }
2860
2861 if (i.tm.opcode_modifier & ShortForm)
2862 {
2863 /* The register or float register operand is in operand 0 or 1. */
2864 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2865 /* Register goes in low 3 bits of opcode. */
2866 i.tm.base_opcode |= i.op[op].regs->reg_num;
2867 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2868 i.rex |= REX_EXTZ;
2869 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2870 {
2871 /* Warn about some common errors, but press on regardless.
2872 The first case can be generated by gcc (<= 2.8.1). */
2873 if (i.operands == 2)
2874 {
2875 /* Reversed arguments on faddp, fsubp, etc. */
2876 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2877 i.op[1].regs->reg_name,
2878 i.op[0].regs->reg_name);
2879 }
2880 else
2881 {
2882 /* Extraneous `l' suffix on fp insn. */
2883 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2884 i.op[0].regs->reg_name);
2885 }
2886 }
2887 }
2888 else if (i.tm.opcode_modifier & Modrm)
2889 {
2890 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2891 must be put into the modrm byte). Now, we make the modrm and
2892 index base bytes based on all the info we've collected. */
29b0f896
AM		 2893
2894 default_seg = build_modrm_byte ();
2895 }
2896 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2897 {
2898 if (i.tm.base_opcode == POP_SEG_SHORT
2899 && i.op[0].regs->reg_num == 1)
2900 {
2901 as_bad (_("you can't `pop %%cs'"));
2902 return 0;
2903 }
2904 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2905 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2906 i.rex |= REX_EXTZ;
2907 }
2908 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2909 {
2910 default_seg = &ds;
2911 }
2912 else if ((i.tm.opcode_modifier & IsString) != 0)
2913 {
2914 /* For the string instructions that allow a segment override
2915 on one of their operands, the default segment is ds. */
2916 default_seg = &ds;
2917 }
2918
30123838
JB		 2919 if ((i.tm.base_opcode == 0x8d /* lea */
2920 || (i.tm.cpu_flags & CpuSVME))
2921 && i.seg[0] && !quiet_warnings)
2922 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2923
2924 /* If a segment was explicitly specified, and the specified segment
2925 is not the default, use an opcode prefix to select it. If we
2926 never figured out what the default segment is, then default_seg
2927 will be zero at this point, and the specified segment prefix will
2928 always be used. */
29b0f896
AM		 2929 if ((i.seg[0]) && (i.seg[0] != default_seg))
2930 {
2931 if (!add_prefix (i.seg[0]->seg_prefix))
2932 return 0;
2933 }
2934 return 1;
2935}
2936
2937static const seg_entry *
2938build_modrm_byte ()
2939{
2940 const seg_entry *default_seg = 0;
2941
2942 /* i.reg_operands MUST be the number of real register operands;
2943 implicit registers do not count. */
2944 if (i.reg_operands == 2)
2945 {
2946 unsigned int source, dest;
2947 source = ((i.types[0]
2948 & (Reg | RegMMX | RegXMM
2949 | SReg2 | SReg3
2950 | Control | Debug | Test))
2951 ? 0 : 1);
2952 dest = source + 1;
2953
2954 i.rm.mode = 3;
2955 /* One of the register operands will be encoded in the i.tm.reg
2956 field, the other in the combined i.tm.mode and i.tm.regmem
2957 fields. If no form of this instruction supports a memory
2958 destination operand, then we assume the source operand may
2959 sometimes be a memory operand and so we need to store the
2960 destination in the i.rm.reg field. */
2961 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2962 {
2963 i.rm.reg = i.op[dest].regs->reg_num;
2964 i.rm.regmem = i.op[source].regs->reg_num;
2965 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2966 i.rex |= REX_EXTX;
2967 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2968 i.rex |= REX_EXTZ;
2969 }
2970 else
2971 {
2972 i.rm.reg = i.op[source].regs->reg_num;
2973 i.rm.regmem = i.op[dest].regs->reg_num;
2974 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2975 i.rex |= REX_EXTZ;
2976 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2977 i.rex |= REX_EXTX;
2978 }
c4a530c5
JB		 2979 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2980 {
2981 if (!((i.types[0] | i.types[1]) & Control))
2982 abort ();
2983 i.rex &= ~(REX_EXTX | REX_EXTZ);
2984 add_prefix (LOCK_PREFIX_OPCODE);
2985 }
29b0f896
AM		 2986 }
2987 else
2988 { /* If it's not 2 reg operands... */
2989 if (i.mem_operands)
2990 {
2991 unsigned int fake_zero_displacement = 0;
2992 unsigned int op = ((i.types[0] & AnyMem)
2993 ? 0
2994 : (i.types[1] & AnyMem) ? 1 : 2);
2995
2996 default_seg = &ds;
2997
2998 if (i.base_reg == 0)
2999 {
3000 i.rm.mode = 0;
3001 if (!i.disp_operands)
3002 fake_zero_displacement = 1;
3003 if (i.index_reg == 0)
3004 {
3005 /* Operand is just <disp> */
20f0a1fc 3006 if (flag_code == CODE_64BIT)
29b0f896
AM		 3007 {
3008 /* 64bit mode overwrites the 32bit absolute
3009 addressing by RIP relative addressing and
3010 absolute addressing is encoded by one of the
3011 redundant SIB forms. */
3012 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3013 i.sib.base = NO_BASE_REGISTER;
3014 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3015 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3016 }
3017 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3018 {
3019 i.rm.regmem = NO_BASE_REGISTER_16;
3020 i.types[op] = Disp16;
3021 }
3022 else
3023 {
3024 i.rm.regmem = NO_BASE_REGISTER;
3025 i.types[op] = Disp32;
29b0f896
AM		 3026 }
3027 }
3028 else /* !i.base_reg && i.index_reg */
3029 {
3030 i.sib.index = i.index_reg->reg_num;
3031 i.sib.base = NO_BASE_REGISTER;
3032 i.sib.scale = i.log2_scale_factor;
3033 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3034 i.types[op] &= ~Disp;
3035 if (flag_code != CODE_64BIT)
3036 i.types[op] |= Disp32; /* Must be 32 bit */
3037 else
3038 i.types[op] |= Disp32S;
3039 if ((i.index_reg->reg_flags & RegRex) != 0)
3040 i.rex |= REX_EXTY;
3041 }
3042 }
3043 /* RIP addressing for 64bit mode. */
3044 else if (i.base_reg->reg_type == BaseIndex)
3045 {
3046 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3047 i.types[op] &= ~ Disp;
29b0f896
AM		 3048 i.types[op] |= Disp32S;
3049 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3050 if (! i.disp_operands)
3051 fake_zero_displacement = 1;
29b0f896
AM		 3052 }
3053 else if (i.base_reg->reg_type & Reg16)
3054 {
3055 switch (i.base_reg->reg_num)
3056 {
3057 case 3: /* (%bx) */
3058 if (i.index_reg == 0)
3059 i.rm.regmem = 7;
3060 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3061 i.rm.regmem = i.index_reg->reg_num - 6;
3062 break;
3063 case 5: /* (%bp) */
3064 default_seg = &ss;
3065 if (i.index_reg == 0)
3066 {
3067 i.rm.regmem = 6;
3068 if ((i.types[op] & Disp) == 0)
3069 {
3070 /* fake (%bp) into 0(%bp) */
3071 i.types[op] |= Disp8;
252b5132 3072 fake_zero_displacement = 1;
29b0f896
AM		 3073 }
3074 }
3075 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3076 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3077 break;
3078 default: /* (%si) -> 4 or (%di) -> 5 */
3079 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3080 }
3081 i.rm.mode = mode_from_disp_size (i.types[op]);
3082 }
3083 else /* i.base_reg and 32/64 bit mode */
3084 {
3085 if (flag_code == CODE_64BIT
3086 && (i.types[op] & Disp))
20f0a1fc
NC		 3087 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3088
29b0f896
AM		 3089 i.rm.regmem = i.base_reg->reg_num;
3090 if ((i.base_reg->reg_flags & RegRex) != 0)
3091 i.rex |= REX_EXTZ;
3092 i.sib.base = i.base_reg->reg_num;
3093 /* x86-64 ignores REX prefix bit here to avoid decoder
3094 complications. */
3095 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3096 {
3097 default_seg = &ss;
3098 if (i.disp_operands == 0)
3099 {
3100 fake_zero_displacement = 1;
3101 i.types[op] |= Disp8;
3102 }
3103 }
3104 else if (i.base_reg->reg_num == ESP_REG_NUM)
3105 {
3106 default_seg = &ss;
3107 }
3108 i.sib.scale = i.log2_scale_factor;
3109 if (i.index_reg == 0)
3110 {
3111 /* <disp>(%esp) becomes two byte modrm with no index
3112 register. We've already stored the code for esp
3113 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3114 Any base register besides %esp will not use the
3115 extra modrm byte. */
3116 i.sib.index = NO_INDEX_REGISTER;
3117#if !SCALE1_WHEN_NO_INDEX
3118 /* Another case where we force the second modrm byte. */
3119 if (i.log2_scale_factor)
3120 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3121#endif
29b0f896
AM		 3122 }
3123 else
3124 {
3125 i.sib.index = i.index_reg->reg_num;
3126 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3127 if ((i.index_reg->reg_flags & RegRex) != 0)
3128 i.rex |= REX_EXTY;
3129 }
3130 i.rm.mode = mode_from_disp_size (i.types[op]);
3131 }
252b5132 3132
29b0f896
AM		 3133 if (fake_zero_displacement)
3134 {
3135 /* Fakes a zero displacement assuming that i.types[op]
3136 holds the correct displacement size. */
3137 expressionS *exp;
3138
3139 assert (i.op[op].disps == 0);
3140 exp = &disp_expressions[i.disp_operands++];
3141 i.op[op].disps = exp;
3142 exp->X_op = O_constant;
3143 exp->X_add_number = 0;
3144 exp->X_add_symbol = (symbolS *) 0;
3145 exp->X_op_symbol = (symbolS *) 0;
3146 }
3147 }
252b5132 3148
29b0f896
AM		 3149 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3150 (if any) based on i.tm.extension_opcode. Again, we must be
3151 careful to make sure that segment/control/debug/test/MMX
3152 registers are coded into the i.rm.reg field. */
3153 if (i.reg_operands)
3154 {
3155 unsigned int op =
3156 ((i.types[0]
3157 & (Reg | RegMMX | RegXMM
3158 | SReg2 | SReg3
3159 | Control | Debug | Test))
3160 ? 0
3161 : ((i.types[1]
3162 & (Reg | RegMMX | RegXMM
3163 | SReg2 | SReg3
3164 | Control | Debug | Test))
3165 ? 1
3166 : 2));
3167 /* If there is an extension opcode to put here, the register
3168 number must be put into the regmem field. */
3169 if (i.tm.extension_opcode != None)
3170 {
3171 i.rm.regmem = i.op[op].regs->reg_num;
3172 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3173 i.rex |= REX_EXTZ;
3174 }
3175 else
3176 {
3177 i.rm.reg = i.op[op].regs->reg_num;
3178 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3179 i.rex |= REX_EXTX;
3180 }
252b5132 3181
29b0f896
AM		 3182 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3183 must set it to 3 to indicate this is a register operand
3184 in the regmem field. */
3185 if (!i.mem_operands)
3186 i.rm.mode = 3;
3187 }
252b5132 3188
29b0f896
AM		 3189 /* Fill in i.rm.reg field with extension opcode (if any). */
3190 if (i.tm.extension_opcode != None)
3191 i.rm.reg = i.tm.extension_opcode;
3192 }
3193 return default_seg;
3194}
252b5132 3195
29b0f896
AM		 3196static void
3197output_branch ()
3198{
3199 char *p;
3200 int code16;
3201 int prefix;
3202 relax_substateT subtype;
3203 symbolS *sym;
3204 offsetT off;
3205
3206 code16 = 0;
3207 if (flag_code == CODE_16BIT)
3208 code16 = CODE16;
3209
3210 prefix = 0;
3211 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3212 {
29b0f896
AM		 3213 prefix = 1;
3214 i.prefixes -= 1;
3215 code16 ^= CODE16;
252b5132 3216 }
29b0f896
AM		 3217 /* Pentium4 branch hints. */
3218 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3219 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3220 {
29b0f896
AM		 3221 prefix++;
3222 i.prefixes--;
3223 }
3224 if (i.prefix[REX_PREFIX] != 0)
3225 {
3226 prefix++;
3227 i.prefixes--;
2f66722d
AM		 3228 }
3229
29b0f896
AM		 3230 if (i.prefixes != 0 && !intel_syntax)
3231 as_warn (_("skipping prefixes on this instruction"));
3232
3233 /* It's always a symbol; End frag & setup for relax.
3234 Make sure there is enough room in this frag for the largest
3235 instruction we may generate in md_convert_frag. This is 2
3236 bytes for the opcode and room for the prefix and largest
3237 displacement. */
3238 frag_grow (prefix + 2 + 4);
3239 /* Prefix and 1 opcode byte go in fr_fix. */
3240 p = frag_more (prefix + 1);
3241 if (i.prefix[DATA_PREFIX] != 0)
3242 *p++ = DATA_PREFIX_OPCODE;
3243 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3244 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3245 *p++ = i.prefix[SEG_PREFIX];
3246 if (i.prefix[REX_PREFIX] != 0)
3247 *p++ = i.prefix[REX_PREFIX];
3248 *p = i.tm.base_opcode;
3249
3250 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3251 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3252 else if ((cpu_arch_flags & Cpu386) != 0)
3253 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3254 else
3255 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3256 subtype |= code16;
3e73aa7c 3257
29b0f896
AM		 3258 sym = i.op[0].disps->X_add_symbol;
3259 off = i.op[0].disps->X_add_number;
3e73aa7c 3260
29b0f896
AM		 3261 if (i.op[0].disps->X_op != O_constant
3262 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3263 {
29b0f896
AM		 3264 /* Handle complex expressions. */
3265 sym = make_expr_symbol (i.op[0].disps);
3266 off = 0;
3267 }
3e73aa7c 3268
29b0f896
AM		 3269 /* 1 possible extra opcode + 4 byte displacement go in var part.
3270 Pass reloc in fr_var. */
3271 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3272}
3e73aa7c 3273
29b0f896
AM		 3274static void
3275output_jump ()
3276{
3277 char *p;
3278 int size;
3e02c1cc 3279 fixS *fixP;
29b0f896
AM		 3280
3281 if (i.tm.opcode_modifier & JumpByte)
3282 {
3283 /* This is a loop or jecxz type instruction. */
3284 size = 1;
3285 if (i.prefix[ADDR_PREFIX] != 0)
3286 {
3287 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3288 i.prefixes -= 1;
3289 }
3290 /* Pentium4 branch hints. */
3291 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3292 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3293 {
3294 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3295 i.prefixes--;
3e73aa7c
JH		 3296 }
3297 }
29b0f896
AM		 3298 else
3299 {
3300 int code16;
3e73aa7c 3301
29b0f896
AM		 3302 code16 = 0;
3303 if (flag_code == CODE_16BIT)
3304 code16 = CODE16;
3e73aa7c 3305
29b0f896
AM		 3306 if (i.prefix[DATA_PREFIX] != 0)
3307 {
3308 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3309 i.prefixes -= 1;
3310 code16 ^= CODE16;
3311 }
252b5132 3312
29b0f896
AM		 3313 size = 4;
3314 if (code16)
3315 size = 2;
3316 }
9fcc94b6 3317
29b0f896
AM		 3318 if (i.prefix[REX_PREFIX] != 0)
3319 {
3320 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3321 i.prefixes -= 1;
3322 }
252b5132 3323
29b0f896
AM		 3324 if (i.prefixes != 0 && !intel_syntax)
3325 as_warn (_("skipping prefixes on this instruction"));
e0890092 3326
29b0f896
AM		 3327 p = frag_more (1 + size);
3328 *p++ = i.tm.base_opcode;
e0890092 3329
3e02c1cc
AM		 3330 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3331 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3332
3333 /* All jumps handled here are signed, but don't use a signed limit
3334 check for 32 and 16 bit jumps as we want to allow wrap around at
3335 4G and 64k respectively. */
3336 if (size == 1)
3337 fixP->fx_signed = 1;
29b0f896 3338}
e0890092 3339
29b0f896
AM		 3340static void
3341output_interseg_jump ()
3342{
3343 char *p;
3344 int size;
3345 int prefix;
3346 int code16;
252b5132 3347
29b0f896
AM		 3348 code16 = 0;
3349 if (flag_code == CODE_16BIT)
3350 code16 = CODE16;
a217f122 3351
29b0f896
AM		 3352 prefix = 0;
3353 if (i.prefix[DATA_PREFIX] != 0)
3354 {
3355 prefix = 1;
3356 i.prefixes -= 1;
3357 code16 ^= CODE16;
3358 }
3359 if (i.prefix[REX_PREFIX] != 0)
3360 {
3361 prefix++;
3362 i.prefixes -= 1;
3363 }
252b5132 3364
29b0f896
AM		 3365 size = 4;
3366 if (code16)
3367 size = 2;
252b5132 3368
29b0f896
AM		 3369 if (i.prefixes != 0 && !intel_syntax)
3370 as_warn (_("skipping prefixes on this instruction"));
252b5132 3371
29b0f896
AM		 3372 /* 1 opcode; 2 segment; offset */
3373 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3374
29b0f896
AM		 3375 if (i.prefix[DATA_PREFIX] != 0)
3376 *p++ = DATA_PREFIX_OPCODE;
252b5132 3377
29b0f896
AM		 3378 if (i.prefix[REX_PREFIX] != 0)
3379 *p++ = i.prefix[REX_PREFIX];
252b5132 3380
29b0f896
AM		 3381 *p++ = i.tm.base_opcode;
3382 if (i.op[1].imms->X_op == O_constant)
3383 {
3384 offsetT n = i.op[1].imms->X_add_number;
252b5132 3385
29b0f896
AM		 3386 if (size == 2
3387 && !fits_in_unsigned_word (n)
3388 && !fits_in_signed_word (n))
3389 {
3390 as_bad (_("16-bit jump out of range"));
3391 return;
3392 }
3393 md_number_to_chars (p, n, size);
3394 }
3395 else
3396 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3397 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3398 if (i.op[0].imms->X_op != O_constant)
3399 as_bad (_("can't handle non absolute segment in `%s'"),
3400 i.tm.name);
3401 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3402}
a217f122 3403
29b0f896
AM		 3404static void
3405output_insn ()
3406{
2bbd9c25
JJ		 3407 fragS *insn_start_frag;
3408 offsetT insn_start_off;
3409
29b0f896
AM		 3410 /* Tie dwarf2 debug info to the address at the start of the insn.
3411 We can't do this after the insn has been output as the current
3412 frag may have been closed off. eg. by frag_var. */
3413 dwarf2_emit_insn (0);
3414
2bbd9c25
JJ		 3415 insn_start_frag = frag_now;
3416 insn_start_off = frag_now_fix ();
3417
29b0f896
AM		 3418 /* Output jumps. */
3419 if (i.tm.opcode_modifier & Jump)
3420 output_branch ();
3421 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3422 output_jump ();
3423 else if (i.tm.opcode_modifier & JumpInterSegment)
3424 output_interseg_jump ();
3425 else
3426 {
3427 /* Output normal instructions here. */
3428 char *p;
3429 unsigned char *q;
252b5132 3430
bc4bd9ab
MK		 3431 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3432 more higher byte to specify a prefix the instruction
3433 requires. */
3434 if ((i.tm.base_opcode & 0xff0000) != 0)
3435 {
3436 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3437 {
3438 unsigned int prefix;
3439 prefix = (i.tm.base_opcode >> 16) & 0xff;
3440
3441 if (prefix != REPE_PREFIX_OPCODE
3442 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3443 add_prefix (prefix);
3444 }
3445 else
3446 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3447 }
252b5132 3448
29b0f896
AM		 3449 /* The prefix bytes. */
3450 for (q = i.prefix;
3451 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3452 q++)
3453 {
3454 if (*q)
3455 {
3456 p = frag_more (1);
3457 md_number_to_chars (p, (valueT) *q, 1);
3458 }
3459 }
252b5132 3460
29b0f896
AM		 3461 /* Now the opcode; be careful about word order here! */
3462 if (fits_in_unsigned_byte (i.tm.base_opcode))
3463 {
3464 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3465 }
3466 else
3467 {
bc4bd9ab 3468 p = frag_more (2);
0f10071e 3469
29b0f896
AM		 3470 /* Put out high byte first: can't use md_number_to_chars! */
3471 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3472 *p = i.tm.base_opcode & 0xff;
3473 }
3e73aa7c 3474
29b0f896
AM		 3475 /* Now the modrm byte and sib byte (if present). */
3476 if (i.tm.opcode_modifier & Modrm)
3477 {
3478 p = frag_more (1);
3479 md_number_to_chars (p,
3480 (valueT) (i.rm.regmem << 0
3481 | i.rm.reg << 3
3482 | i.rm.mode << 6),
3483 1);
3484 /* If i.rm.regmem == ESP (4)
3485 && i.rm.mode != (Register mode)
3486 && not 16 bit
3487 ==> need second modrm byte. */
3488 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3489 && i.rm.mode != 3
3490 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3491 {
3492 p = frag_more (1);
3493 md_number_to_chars (p,
3494 (valueT) (i.sib.base << 0
3495 | i.sib.index << 3
3496 | i.sib.scale << 6),
3497 1);
3498 }
3499 }
3e73aa7c 3500
29b0f896 3501 if (i.disp_operands)
2bbd9c25 3502 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3503
29b0f896 3504 if (i.imm_operands)
2bbd9c25 3505 output_imm (insn_start_frag, insn_start_off);
29b0f896 3506 }
252b5132 3507
29b0f896
AM		 3508#ifdef DEBUG386
3509 if (flag_debug)
3510 {
3511 pi (line, &i);
3512 }
3513#endif /* DEBUG386 */
3514}
252b5132 3515
29b0f896 3516static void
2bbd9c25
JJ		 3517output_disp (insn_start_frag, insn_start_off)
3518 fragS *insn_start_frag;
3519 offsetT insn_start_off;
29b0f896
AM		 3520{
3521 char *p;
3522 unsigned int n;
252b5132 3523
29b0f896
AM		 3524 for (n = 0; n < i.operands; n++)
3525 {
3526 if (i.types[n] & Disp)
3527 {
3528 if (i.op[n].disps->X_op == O_constant)
3529 {
3530 int size;
3531 offsetT val;
252b5132 3532
29b0f896
AM		 3533 size = 4;
3534 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3535 {
3536 size = 2;
3537 if (i.types[n] & Disp8)
3538 size = 1;
3539 if (i.types[n] & Disp64)
3540 size = 8;
3541 }
3542 val = offset_in_range (i.op[n].disps->X_add_number,
3543 size);
3544 p = frag_more (size);
3545 md_number_to_chars (p, val, size);
3546 }
3547 else
3548 {
f86103b7 3549 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3550 int size = 4;
3551 int sign = 0;
3552 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3553
3554 /* The PC relative address is computed relative
3555 to the instruction boundary, so in case immediate
3556 fields follows, we need to adjust the value. */
3557 if (pcrel && i.imm_operands)
3558 {
3559 int imm_size = 4;
3560 unsigned int n1;
252b5132 3561
29b0f896
AM		 3562 for (n1 = 0; n1 < i.operands; n1++)
3563 if (i.types[n1] & Imm)
252b5132 3564 {
29b0f896 3565 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3566 {
29b0f896
AM		 3567 imm_size = 2;
3568 if (i.types[n1] & (Imm8 | Imm8S))
3569 imm_size = 1;
3570 if (i.types[n1] & Imm64)
3571 imm_size = 8;
252b5132 3572 }
29b0f896 3573 break;
252b5132 3574 }
29b0f896
AM		 3575 /* We should find the immediate. */
3576 if (n1 == i.operands)
3577 abort ();
3578 i.op[n].disps->X_add_number -= imm_size;
3579 }
520dc8e8 3580
29b0f896
AM		 3581 if (i.types[n] & Disp32S)
3582 sign = 1;
3e73aa7c 3583
29b0f896
AM		 3584 if (i.types[n] & (Disp16 | Disp64))
3585 {
3586 size = 2;
3587 if (i.types[n] & Disp64)
3588 size = 8;
3589 }
520dc8e8 3590
29b0f896 3591 p = frag_more (size);
2bbd9c25 3592 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3593 if (GOT_symbol
2bbd9c25 3594 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3595 && (((reloc_type == BFD_RELOC_32
3596 || reloc_type == BFD_RELOC_X86_64_32S)
3597 && (i.op[n].disps->X_op == O_symbol
3598 || (i.op[n].disps->X_op == O_add
3599 && ((symbol_get_value_expression
3600 (i.op[n].disps->X_op_symbol)->X_op)
3601 == O_subtract))))
3602 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3603 {
3604 offsetT add;
3605
3606 if (insn_start_frag == frag_now)
3607 add = (p - frag_now->fr_literal) - insn_start_off;
3608 else
3609 {
3610 fragS *fr;
3611
3612 add = insn_start_frag->fr_fix - insn_start_off;
3613 for (fr = insn_start_frag->fr_next;
3614 fr && fr != frag_now; fr = fr->fr_next)
3615 add += fr->fr_fix;
3616 add += p - frag_now->fr_literal;
3617 }
3618
4fa24527 3619 if (!object_64bit)
d6ab8113
JB		 3620 reloc_type = BFD_RELOC_386_GOTPC;
3621 else
3622 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3623 i.op[n].disps->X_add_number += add;
3624 }
062cd5e7 3625 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3626 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3627 }
3628 }
3629 }
3630}
252b5132 3631
29b0f896 3632static void
2bbd9c25
JJ		 3633output_imm (insn_start_frag, insn_start_off)
3634 fragS *insn_start_frag;
3635 offsetT insn_start_off;
29b0f896
AM		 3636{
3637 char *p;
3638 unsigned int n;
252b5132 3639
29b0f896
AM		 3640 for (n = 0; n < i.operands; n++)
3641 {
3642 if (i.types[n] & Imm)
3643 {
3644 if (i.op[n].imms->X_op == O_constant)
3645 {
3646 int size;
3647 offsetT val;
b4cac588 3648
29b0f896
AM		 3649 size = 4;
3650 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3651 {
3652 size = 2;
3653 if (i.types[n] & (Imm8 | Imm8S))
3654 size = 1;
3655 else if (i.types[n] & Imm64)
3656 size = 8;
3657 }
3658 val = offset_in_range (i.op[n].imms->X_add_number,
3659 size);
3660 p = frag_more (size);
3661 md_number_to_chars (p, val, size);
3662 }
3663 else
3664 {
3665 /* Not absolute_section.
3666 Need a 32-bit fixup (don't support 8bit
3667 non-absolute imms). Try to support other
3668 sizes ... */
f86103b7 3669 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3670 int size = 4;
3671 int sign = 0;
3672
3673 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3674 && (i.suffix == QWORD_MNEM_SUFFIX
3675 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3676 sign = 1;
3677 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3678 {
3679 size = 2;
3680 if (i.types[n] & (Imm8 | Imm8S))
3681 size = 1;
3682 if (i.types[n] & Imm64)
3683 size = 8;
3684 }
520dc8e8 3685
29b0f896
AM		 3686 p = frag_more (size);
3687 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3688
2bbd9c25
JJ		 3689 /* This is tough to explain. We end up with this one if we
3690 * have operands that look like
3691 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3692 * obtain the absolute address of the GOT, and it is strongly
3693 * preferable from a performance point of view to avoid using
3694 * a runtime relocation for this. The actual sequence of
3695 * instructions often look something like:
3696 *
3697 * call .L66
3698 * .L66:
3699 * popl %ebx
3700 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3701 *
3702 * The call and pop essentially return the absolute address
3703 * of the label .L66 and store it in %ebx. The linker itself
3704 * will ultimately change the first operand of the addl so
3705 * that %ebx points to the GOT, but to keep things simple, the
3706 * .o file must have this operand set so that it generates not
3707 * the absolute address of .L66, but the absolute address of
3708 * itself. This allows the linker itself simply treat a GOTPC
3709 * relocation as asking for a pcrel offset to the GOT to be
3710 * added in, and the addend of the relocation is stored in the
3711 * operand field for the instruction itself.
3712 *
3713 * Our job here is to fix the operand so that it would add
3714 * the correct offset so that %ebx would point to itself. The
3715 * thing that is tricky is that .-.L66 will point to the
3716 * beginning of the instruction, so we need to further modify
3717 * the operand so that it will point to itself. There are
3718 * other cases where you have something like:
3719 *
3720 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3721 *
3722 * and here no correction would be required. Internally in
3723 * the assembler we treat operands of this form as not being
3724 * pcrel since the '.' is explicitly mentioned, and I wonder
3725 * whether it would simplify matters to do it this way. Who
3726 * knows. In earlier versions of the PIC patches, the
3727 * pcrel_adjust field was used to store the correction, but
3728 * since the expression is not pcrel, I felt it would be
3729 * confusing to do it this way. */
3730
d6ab8113
JB		 3731 if ((reloc_type == BFD_RELOC_32
3732 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3733 && GOT_symbol
3734 && GOT_symbol == i.op[n].imms->X_add_symbol
3735 && (i.op[n].imms->X_op == O_symbol
3736 || (i.op[n].imms->X_op == O_add
3737 && ((symbol_get_value_expression
3738 (i.op[n].imms->X_op_symbol)->X_op)
3739 == O_subtract))))
3740 {
2bbd9c25
JJ		 3741 offsetT add;
3742
3743 if (insn_start_frag == frag_now)
3744 add = (p - frag_now->fr_literal) - insn_start_off;
3745 else
3746 {
3747 fragS *fr;
3748
3749 add = insn_start_frag->fr_fix - insn_start_off;
3750 for (fr = insn_start_frag->fr_next;
3751 fr && fr != frag_now; fr = fr->fr_next)
3752 add += fr->fr_fix;
3753 add += p - frag_now->fr_literal;
3754 }
3755
4fa24527 3756 if (!object_64bit)
d6ab8113
JB		 3757 reloc_type = BFD_RELOC_386_GOTPC;
3758 else
3759 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3760 i.op[n].imms->X_add_number += add;
29b0f896 3761 }
29b0f896
AM		 3762 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3763 i.op[n].imms, 0, reloc_type);
3764 }
3765 }
3766 }
252b5132
RH		 3767}
3768\f
d182319b
JB		 3769/* x86_cons_fix_new is called via the expression parsing code when a
3770 reloc is needed. We use this hook to get the correct .got reloc. */
3771static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3772static int cons_sign = -1;
3773
3774void
3775x86_cons_fix_new (fragS *frag,
3776 unsigned int off,
3777 unsigned int len,
3778 expressionS *exp)
3779{
3780 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3781
3782 got_reloc = NO_RELOC;
3783
3784#ifdef TE_PE
3785 if (exp->X_op == O_secrel)
3786 {
3787 exp->X_op = O_symbol;
3788 r = BFD_RELOC_32_SECREL;
3789 }
3790#endif
3791
3792 fix_new_exp (frag, off, len, exp, 0, r);
3793}
3794
718ddfc0
JB		 3795#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3796# define lex_got(reloc, adjust, types) NULL
3797#else
f3c180ae
AM		 3798/* Parse operands of the form
3799 <symbol>@GOTOFF+<nnn>
3800 and similar .plt or .got references.
3801
3802 If we find one, set up the correct relocation in RELOC and copy the
3803 input string, minus the `@GOTOFF' into a malloc'd buffer for
3804 parsing by the calling routine. Return this buffer, and if ADJUST
3805 is non-null set it to the length of the string we removed from the
3806 input line. Otherwise return NULL. */
3807static char *
3956db08
JB		 3808lex_got (enum bfd_reloc_code_real *reloc,
3809 int *adjust,
3810 unsigned int *types)
f3c180ae 3811{
f3c180ae
AM		 3812 static const struct {
3813 const char *str;
4fa24527 3814 const enum bfd_reloc_code_real rel[2];
3956db08 3815 const unsigned int types64;
f3c180ae 3816 } gotrel[] = {
4fa24527
JB		 3817 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3818 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3819 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3820 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3821 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3822 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3823 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3824 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3825 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3826 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3827 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3828 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3829 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3830 };
3831 char *cp;
3832 unsigned int j;
3833
718ddfc0
JB		 3834 if (!IS_ELF)
3835 return NULL;
3836
f3c180ae
AM		 3837 for (cp = input_line_pointer; *cp != '@'; cp++)
3838 if (is_end_of_line[(unsigned char) *cp])
3839 return NULL;
3840
3841 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3842 {
3843 int len;
3844
3845 len = strlen (gotrel[j].str);
28f81592 3846 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 3847 {
4fa24527 3848 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 3849 {
28f81592
AM		 3850 int first, second;
3851 char *tmpbuf, *past_reloc;
f3c180ae 3852
4fa24527 3853 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 3854 if (adjust)
3855 *adjust = len;
f3c180ae 3856
3956db08
JB		 3857 if (types)
3858 {
3859 if (flag_code != CODE_64BIT)
3860 *types = Imm32|Disp32;
3861 else
3862 *types = gotrel[j].types64;
3863 }
3864
f3c180ae
AM		 3865 if (GOT_symbol == NULL)
3866 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3867
3868 /* Replace the relocation token with ' ', so that
3869 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3870
3871 /* The length of the first part of our input line. */
f3c180ae 3872 first = cp - input_line_pointer;
28f81592
AM		 3873
3874 /* The second part goes from after the reloc token until
3875 (and including) an end_of_line char. Don't use strlen
3876 here as the end_of_line char may not be a NUL. */
3877 past_reloc = cp + 1 + len;
3878 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3879 ;
3880 second = cp - past_reloc;
3881
3882 /* Allocate and copy string. The trailing NUL shouldn't
3883 be necessary, but be safe. */
3884 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3885 memcpy (tmpbuf, input_line_pointer, first);
3886 tmpbuf[first] = ' ';
28f81592
AM		 3887 memcpy (tmpbuf + first + 1, past_reloc, second);
3888 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3889 return tmpbuf;
3890 }
3891
4fa24527
JB		 3892 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3893 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 3894 return NULL;
3895 }
3896 }
3897
3898 /* Might be a symbol version string. Don't as_bad here. */
3899 return NULL;
3900}
3901
f3c180ae
AM		 3902void
3903x86_cons (exp, size)
3904 expressionS *exp;
3905 int size;
3906{
4fa24527 3907 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 3908 {
3909 /* Handle @GOTOFF and the like in an expression. */
3910 char *save;
3911 char *gotfree_input_line;
3912 int adjust;
3913
3914 save = input_line_pointer;
3956db08 3915 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3916 if (gotfree_input_line)
3917 input_line_pointer = gotfree_input_line;
3918
3919 expression (exp);
3920
3921 if (gotfree_input_line)
3922 {
3923 /* expression () has merrily parsed up to the end of line,
3924 or a comma - in the wrong buffer. Transfer how far
3925 input_line_pointer has moved to the right buffer. */
3926 input_line_pointer = (save
3927 + (input_line_pointer - gotfree_input_line)
3928 + adjust);
3929 free (gotfree_input_line);
3930 }
3931 }
3932 else
3933 expression (exp);
3934}
3935#endif
3936
d182319b 3937static void signed_cons (int size)
6482c264 3938{
d182319b
JB		 3939 if (flag_code == CODE_64BIT)
3940 cons_sign = 1;
3941 cons (size);
3942 cons_sign = -1;
6482c264
NC		 3943}
3944
d182319b 3945#ifdef TE_PE
6482c264
NC		 3946static void
3947pe_directive_secrel (dummy)
3948 int dummy ATTRIBUTE_UNUSED;
3949{
3950 expressionS exp;
3951
3952 do
3953 {
3954 expression (&exp);
3955 if (exp.X_op == O_symbol)
3956 exp.X_op = O_secrel;
3957
3958 emit_expr (&exp, 4);
3959 }
3960 while (*input_line_pointer++ == ',');
3961
3962 input_line_pointer--;
3963 demand_empty_rest_of_line ();
3964}
6482c264
NC		 3965#endif
3966
252b5132
RH		 3967static int i386_immediate PARAMS ((char *));
3968
3969static int
3970i386_immediate (imm_start)
3971 char *imm_start;
3972{
3973 char *save_input_line_pointer;
f3c180ae 3974 char *gotfree_input_line;
252b5132 3975 segT exp_seg = 0;
47926f60 3976 expressionS *exp;
3956db08 3977 unsigned int types = ~0U;
252b5132
RH		 3978
3979 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3980 {
d0b47220 3981 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3982 return 0;
3983 }
3984
3985 exp = &im_expressions[i.imm_operands++];
520dc8e8 3986 i.op[this_operand].imms = exp;
252b5132
RH		 3987
3988 if (is_space_char (*imm_start))
3989 ++imm_start;
3990
3991 save_input_line_pointer = input_line_pointer;
3992 input_line_pointer = imm_start;
3993
3956db08 3994 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 3995 if (gotfree_input_line)
3996 input_line_pointer = gotfree_input_line;
252b5132
RH		 3997
3998 exp_seg = expression (exp);
3999
83183c0c 4000 SKIP_WHITESPACE ();
252b5132 4001 if (*input_line_pointer)
f3c180ae 4002 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4003
4004 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4005 if (gotfree_input_line)
4006 free (gotfree_input_line);
252b5132 4007
2daf4fd8 4008 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4009 {
47926f60 4010 /* Missing or bad expr becomes absolute 0. */
d0b47220 4011 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4012 imm_start);
252b5132
RH		 4013 exp->X_op = O_constant;
4014 exp->X_add_number = 0;
4015 exp->X_add_symbol = (symbolS *) 0;
4016 exp->X_op_symbol = (symbolS *) 0;
252b5132 4017 }
3e73aa7c 4018 else if (exp->X_op == O_constant)
252b5132 4019 {
47926f60 4020 /* Size it properly later. */
3e73aa7c
JH		 4021 i.types[this_operand] |= Imm64;
4022 /* If BFD64, sign extend val. */
4023 if (!use_rela_relocations)
4024 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4025 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4026 }
4c63da97 4027#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4028 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4029 && exp_seg != absolute_section
47926f60 4030 && exp_seg != text_section
24eab124
AM		 4031 && exp_seg != data_section
4032 && exp_seg != bss_section
4033 && exp_seg != undefined_section
f86103b7 4034 && !bfd_is_com_section (exp_seg))
252b5132 4035 {
d0b47220 4036 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4037 return 0;
4038 }
4039#endif
4040 else
4041 {
4042 /* This is an address. The size of the address will be
24eab124 4043 determined later, depending on destination register,
3e73aa7c
JH		 4044 suffix, or the default for the section. */
4045 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4046 i.types[this_operand] &= types;
252b5132
RH		 4047 }
4048
4049 return 1;
4050}
4051
551c1ca1 4052static char *i386_scale PARAMS ((char *));
252b5132 4053
551c1ca1 4054static char *
252b5132
RH		 4055i386_scale (scale)
4056 char *scale;
4057{
551c1ca1
AM		 4058 offsetT val;
4059 char *save = input_line_pointer;
252b5132 4060
551c1ca1
AM		 4061 input_line_pointer = scale;
4062 val = get_absolute_expression ();
4063
4064 switch (val)
252b5132 4065 {
551c1ca1 4066 case 1:
252b5132
RH		 4067 i.log2_scale_factor = 0;
4068 break;
551c1ca1 4069 case 2:
252b5132
RH		 4070 i.log2_scale_factor = 1;
4071 break;
551c1ca1 4072 case 4:
252b5132
RH		 4073 i.log2_scale_factor = 2;
4074 break;
551c1ca1 4075 case 8:
252b5132
RH		 4076 i.log2_scale_factor = 3;
4077 break;
4078 default:
a724f0f4
JB		 4079 {
4080 char sep = *input_line_pointer;
4081
4082 *input_line_pointer = '\0';
4083 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4084 scale);
4085 *input_line_pointer = sep;
4086 input_line_pointer = save;
4087 return NULL;
4088 }
252b5132 4089 }
29b0f896 4090 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4091 {
4092 as_warn (_("scale factor of %d without an index register"),
24eab124 4093 1 << i.log2_scale_factor);
252b5132
RH		 4094#if SCALE1_WHEN_NO_INDEX
4095 i.log2_scale_factor = 0;
4096#endif
4097 }
551c1ca1
AM		 4098 scale = input_line_pointer;
4099 input_line_pointer = save;
4100 return scale;
252b5132
RH		 4101}
4102
4103static int i386_displacement PARAMS ((char *, char *));
4104
4105static int
4106i386_displacement (disp_start, disp_end)
4107 char *disp_start;
4108 char *disp_end;
4109{
29b0f896 4110 expressionS *exp;
252b5132
RH		 4111 segT exp_seg = 0;
4112 char *save_input_line_pointer;
f3c180ae 4113 char *gotfree_input_line;
252b5132 4114 int bigdisp = Disp32;
3956db08 4115 unsigned int types = Disp;
252b5132 4116
3e73aa7c 4117 if (flag_code == CODE_64BIT)
7ecd2f8b 4118 {
29b0f896 4119 if (i.prefix[ADDR_PREFIX] == 0)
3956db08 4120 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b
JH		 4121 }
4122 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4123 bigdisp = Disp16;
252b5132
RH		 4124 i.types[this_operand] |= bigdisp;
4125
4126 exp = &disp_expressions[i.disp_operands];
520dc8e8 4127 i.op[this_operand].disps = exp;
252b5132
RH		 4128 i.disp_operands++;
4129 save_input_line_pointer = input_line_pointer;
4130 input_line_pointer = disp_start;
4131 END_STRING_AND_SAVE (disp_end);
4132
4133#ifndef GCC_ASM_O_HACK
4134#define GCC_ASM_O_HACK 0
4135#endif
4136#if GCC_ASM_O_HACK
4137 END_STRING_AND_SAVE (disp_end + 1);
4138 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4139 && displacement_string_end[-1] == '+')
252b5132
RH		 4140 {
4141 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4142 constraint within gcc asm statements.
4143 For instance:
4144
4145 #define _set_tssldt_desc(n,addr,limit,type) \
4146 __asm__ __volatile__ ( \
4147 "movw %w2,%0\n\t" \
4148 "movw %w1,2+%0\n\t" \
4149 "rorl $16,%1\n\t" \
4150 "movb %b1,4+%0\n\t" \
4151 "movb %4,5+%0\n\t" \
4152 "movb $0,6+%0\n\t" \
4153 "movb %h1,7+%0\n\t" \
4154 "rorl $16,%1" \
4155 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4156
4157 This works great except that the output assembler ends
4158 up looking a bit weird if it turns out that there is
4159 no offset. You end up producing code that looks like:
4160
4161 #APP
4162 movw $235,(%eax)
4163 movw %dx,2+(%eax)
4164 rorl $16,%edx
4165 movb %dl,4+(%eax)
4166 movb $137,5+(%eax)
4167 movb $0,6+(%eax)
4168 movb %dh,7+(%eax)
4169 rorl $16,%edx
4170 #NO_APP
4171
47926f60 4172 So here we provide the missing zero. */
24eab124
AM		 4173
4174 *displacement_string_end = '0';
252b5132
RH		 4175 }
4176#endif
3956db08 4177 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4178 if (gotfree_input_line)
4179 input_line_pointer = gotfree_input_line;
252b5132 4180
24eab124 4181 exp_seg = expression (exp);
252b5132 4182
636c26b0
AM		 4183 SKIP_WHITESPACE ();
4184 if (*input_line_pointer)
4185 as_bad (_("junk `%s' after expression"), input_line_pointer);
4186#if GCC_ASM_O_HACK
4187 RESTORE_END_STRING (disp_end + 1);
4188#endif
4189 RESTORE_END_STRING (disp_end);
4190 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4191 if (gotfree_input_line)
4192 free (gotfree_input_line);
636c26b0 4193
24eab124
AM		 4194 /* We do this to make sure that the section symbol is in
4195 the symbol table. We will ultimately change the relocation
47926f60 4196 to be relative to the beginning of the section. */
1ae12ab7 4197 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4198 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4199 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4200 {
636c26b0
AM		 4201 if (exp->X_op != O_symbol)
4202 {
4203 as_bad (_("bad expression used with @%s"),
4204 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4205 ? "GOTPCREL"
4206 : "GOTOFF"));
4207 return 0;
4208 }
4209
e5cb08ac 4210 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4211 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4212 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4213 exp->X_op = O_subtract;
4214 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4215 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4216 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4217 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4218 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4219 else
29b0f896 4220 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4221 }
252b5132 4222
2daf4fd8
AM		 4223 if (exp->X_op == O_absent || exp->X_op == O_big)
4224 {
47926f60 4225 /* Missing or bad expr becomes absolute 0. */
d0b47220 4226 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4227 disp_start);
4228 exp->X_op = O_constant;
4229 exp->X_add_number = 0;
4230 exp->X_add_symbol = (symbolS *) 0;
4231 exp->X_op_symbol = (symbolS *) 0;
4232 }
4233
4c63da97 4234#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4235 if (exp->X_op != O_constant
45288df1 4236 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4237 && exp_seg != absolute_section
45288df1
AM		 4238 && exp_seg != text_section
4239 && exp_seg != data_section
4240 && exp_seg != bss_section
31312f95 4241 && exp_seg != undefined_section
f86103b7 4242 && !bfd_is_com_section (exp_seg))
24eab124 4243 {
d0b47220 4244 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4245 return 0;
4246 }
252b5132 4247#endif
3956db08
JB		 4248
4249 if (!(i.types[this_operand] & ~Disp))
4250 i.types[this_operand] &= types;
4251
252b5132
RH		 4252 return 1;
4253}
4254
e5cb08ac 4255static int i386_index_check PARAMS ((const char *));
252b5132 4256
eecb386c 4257/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4258 Return 1 on success, 0 on a failure. */
4259
252b5132 4260static int
eecb386c
AM		 4261i386_index_check (operand_string)
4262 const char *operand_string;
252b5132 4263{
3e73aa7c 4264 int ok;
24eab124 4265#if INFER_ADDR_PREFIX
eecb386c
AM		 4266 int fudged = 0;
4267
24eab124
AM		 4268 tryprefix:
4269#endif
3e73aa7c 4270 ok = 1;
30123838
JB		 4271 if ((current_templates->start->cpu_flags & CpuSVME)
4272 && current_templates->end[-1].operand_types[0] == AnyMem)
4273 {
4274 /* Memory operands of SVME insns are special in that they only allow
4275 rAX as their memory address and ignore any segment override. */
4276 unsigned RegXX;
4277
4278 /* SKINIT is even more restrictive: it always requires EAX. */
4279 if (strcmp (current_templates->start->name, "skinit") == 0)
4280 RegXX = Reg32;
4281 else if (flag_code == CODE_64BIT)
4282 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4283 else
4284 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4285 ? Reg16
4286 : Reg32;
4287 if (!i.base_reg
4288 || !(i.base_reg->reg_type & Acc)
4289 || !(i.base_reg->reg_type & RegXX)
4290 || i.index_reg
4291 || (i.types[0] & Disp))
4292 ok = 0;
4293 }
4294 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4295 {
4296 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4297
4298 if ((i.base_reg
4299 && ((i.base_reg->reg_type & RegXX) == 0)
4300 && (i.base_reg->reg_type != BaseIndex
4301 || i.index_reg))
4302 || (i.index_reg
4303 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4304 != (RegXX | BaseIndex))))
4305 ok = 0;
3e73aa7c
JH		 4306 }
4307 else
4308 {
4309 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4310 {
4311 /* 16bit checks. */
4312 if ((i.base_reg
29b0f896
AM		 4313 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4314 != (Reg16 | BaseIndex)))
3e73aa7c 4315 || (i.index_reg
29b0f896
AM		 4316 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4317 != (Reg16 | BaseIndex))
4318 || !(i.base_reg
4319 && i.base_reg->reg_num < 6
4320 && i.index_reg->reg_num >= 6
4321 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4322 ok = 0;
4323 }
4324 else
e5cb08ac 4325 {
3e73aa7c
JH		 4326 /* 32bit checks. */
4327 if ((i.base_reg
4328 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4329 || (i.index_reg
29b0f896
AM		 4330 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4331 != (Reg32 | BaseIndex))))
e5cb08ac 4332 ok = 0;
3e73aa7c
JH		 4333 }
4334 }
4335 if (!ok)
24eab124
AM		 4336 {
4337#if INFER_ADDR_PREFIX
20f0a1fc 4338 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4339 {
4340 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4341 i.prefixes += 1;
b23bac36
AM		 4342 /* Change the size of any displacement too. At most one of
4343 Disp16 or Disp32 is set.
4344 FIXME. There doesn't seem to be any real need for separate
4345 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4346 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4347 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4348 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4349 fudged = 1;
24eab124
AM		 4350 goto tryprefix;
4351 }
eecb386c
AM		 4352 if (fudged)
4353 as_bad (_("`%s' is not a valid base/index expression"),
4354 operand_string);
4355 else
c388dee8 4356#endif
eecb386c
AM		 4357 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4358 operand_string,
3e73aa7c 4359 flag_code_names[flag_code]);
24eab124 4360 }
20f0a1fc 4361 return ok;
24eab124 4362}
252b5132 4363
252b5132 4364/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4365 on error. */
252b5132 4366
252b5132
RH		 4367static int
4368i386_operand (operand_string)
4369 char *operand_string;
4370{
af6bdddf
AM		 4371 const reg_entry *r;
4372 char *end_op;
24eab124 4373 char *op_string = operand_string;
252b5132 4374
24eab124 4375 if (is_space_char (*op_string))
252b5132
RH		 4376 ++op_string;
4377
24eab124 4378 /* We check for an absolute prefix (differentiating,
47926f60 4379 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4380 if (*op_string == ABSOLUTE_PREFIX)
4381 {
4382 ++op_string;
4383 if (is_space_char (*op_string))
4384 ++op_string;
4385 i.types[this_operand] |= JumpAbsolute;
4386 }
252b5132 4387
47926f60 4388 /* Check if operand is a register. */
af6bdddf
AM		 4389 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4390 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4391 {
24eab124
AM		 4392 /* Check for a segment override by searching for ':' after a
4393 segment register. */
4394 op_string = end_op;
4395 if (is_space_char (*op_string))
4396 ++op_string;
4397 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4398 {
4399 switch (r->reg_num)
4400 {
4401 case 0:
4402 i.seg[i.mem_operands] = &es;
4403 break;
4404 case 1:
4405 i.seg[i.mem_operands] = &cs;
4406 break;
4407 case 2:
4408 i.seg[i.mem_operands] = &ss;
4409 break;
4410 case 3:
4411 i.seg[i.mem_operands] = &ds;
4412 break;
4413 case 4:
4414 i.seg[i.mem_operands] = &fs;
4415 break;
4416 case 5:
4417 i.seg[i.mem_operands] = &gs;
4418 break;
4419 }
252b5132 4420
24eab124 4421 /* Skip the ':' and whitespace. */
252b5132
RH		 4422 ++op_string;
4423 if (is_space_char (*op_string))
24eab124 4424 ++op_string;
252b5132 4425
24eab124
AM		 4426 if (!is_digit_char (*op_string)
4427 && !is_identifier_char (*op_string)
4428 && *op_string != '('
4429 && *op_string != ABSOLUTE_PREFIX)
4430 {
4431 as_bad (_("bad memory operand `%s'"), op_string);
4432 return 0;
4433 }
47926f60 4434 /* Handle case of %es:*foo. */
24eab124
AM		 4435 if (*op_string == ABSOLUTE_PREFIX)
4436 {
4437 ++op_string;
4438 if (is_space_char (*op_string))
4439 ++op_string;
4440 i.types[this_operand] |= JumpAbsolute;
4441 }
4442 goto do_memory_reference;
4443 }
4444 if (*op_string)
4445 {
d0b47220 4446 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4447 return 0;
4448 }
4449 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4450 i.op[this_operand].regs = r;
24eab124
AM		 4451 i.reg_operands++;
4452 }
af6bdddf
AM		 4453 else if (*op_string == REGISTER_PREFIX)
4454 {
4455 as_bad (_("bad register name `%s'"), op_string);
4456 return 0;
4457 }
24eab124 4458 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4459 {
24eab124
AM		 4460 ++op_string;
4461 if (i.types[this_operand] & JumpAbsolute)
4462 {
d0b47220 4463 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4464 return 0;
4465 }
4466 if (!i386_immediate (op_string))
4467 return 0;
4468 }
4469 else if (is_digit_char (*op_string)
4470 || is_identifier_char (*op_string)
e5cb08ac 4471 || *op_string == '(')
24eab124 4472 {
47926f60 4473 /* This is a memory reference of some sort. */
af6bdddf 4474 char *base_string;
252b5132 4475
47926f60 4476 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4477 char *displacement_string_start;
4478 char *displacement_string_end;
252b5132 4479
24eab124 4480 do_memory_reference:
24eab124
AM		 4481 if ((i.mem_operands == 1
4482 && (current_templates->start->opcode_modifier & IsString) == 0)
4483 || i.mem_operands == 2)
4484 {
4485 as_bad (_("too many memory references for `%s'"),
4486 current_templates->start->name);
4487 return 0;
4488 }
252b5132 4489
24eab124
AM		 4490 /* Check for base index form. We detect the base index form by
4491 looking for an ')' at the end of the operand, searching
4492 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4493 after the '('. */
af6bdddf 4494 base_string = op_string + strlen (op_string);
c3332e24 4495
af6bdddf
AM		 4496 --base_string;
4497 if (is_space_char (*base_string))
4498 --base_string;
252b5132 4499
47926f60 4500 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4501 displacement_string_start = op_string;
4502 displacement_string_end = base_string + 1;
252b5132 4503
24eab124
AM		 4504 if (*base_string == ')')
4505 {
af6bdddf 4506 char *temp_string;
24eab124
AM		 4507 unsigned int parens_balanced = 1;
4508 /* We've already checked that the number of left & right ()'s are
47926f60 4509 equal, so this loop will not be infinite. */
24eab124
AM		 4510 do
4511 {
4512 base_string--;
4513 if (*base_string == ')')
4514 parens_balanced++;
4515 if (*base_string == '(')
4516 parens_balanced--;
4517 }
4518 while (parens_balanced);
c3332e24 4519
af6bdddf 4520 temp_string = base_string;
c3332e24 4521
24eab124 4522 /* Skip past '(' and whitespace. */
252b5132
RH		 4523 ++base_string;
4524 if (is_space_char (*base_string))
24eab124 4525 ++base_string;
252b5132 4526
af6bdddf
AM		 4527 if (*base_string == ','
4528 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4529 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4530 {
af6bdddf 4531 displacement_string_end = temp_string;
252b5132 4532
af6bdddf 4533 i.types[this_operand] |= BaseIndex;
252b5132 4534
af6bdddf 4535 if (i.base_reg)
24eab124 4536 {
24eab124
AM		 4537 base_string = end_op;
4538 if (is_space_char (*base_string))
4539 ++base_string;
af6bdddf
AM		 4540 }
4541
4542 /* There may be an index reg or scale factor here. */
4543 if (*base_string == ',')
4544 {
4545 ++base_string;
4546 if (is_space_char (*base_string))
4547 ++base_string;
4548
4549 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4550 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4551 {
af6bdddf 4552 base_string = end_op;
24eab124
AM		 4553 if (is_space_char (*base_string))
4554 ++base_string;
af6bdddf
AM		 4555 if (*base_string == ',')
4556 {
4557 ++base_string;
4558 if (is_space_char (*base_string))
4559 ++base_string;
4560 }
e5cb08ac 4561 else if (*base_string != ')')
af6bdddf
AM		 4562 {
4563 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4564 operand_string);
4565 return 0;
4566 }
24eab124 4567 }
af6bdddf 4568 else if (*base_string == REGISTER_PREFIX)
24eab124 4569 {
af6bdddf 4570 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4571 return 0;
4572 }
252b5132 4573
47926f60 4574 /* Check for scale factor. */
551c1ca1 4575 if (*base_string != ')')
af6bdddf 4576 {
551c1ca1
AM		 4577 char *end_scale = i386_scale (base_string);
4578
4579 if (!end_scale)
af6bdddf 4580 return 0;
24eab124 4581
551c1ca1 4582 base_string = end_scale;
af6bdddf
AM		 4583 if (is_space_char (*base_string))
4584 ++base_string;
4585 if (*base_string != ')')
4586 {
4587 as_bad (_("expecting `)' after scale factor in `%s'"),
4588 operand_string);
4589 return 0;
4590 }
4591 }
4592 else if (!i.index_reg)
24eab124 4593 {
af6bdddf
AM		 4594 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4595 *base_string);
24eab124
AM		 4596 return 0;
4597 }
4598 }
af6bdddf 4599 else if (*base_string != ')')
24eab124 4600 {
af6bdddf
AM		 4601 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4602 operand_string);
24eab124
AM		 4603 return 0;
4604 }
c3332e24 4605 }
af6bdddf 4606 else if (*base_string == REGISTER_PREFIX)
c3332e24 4607 {
af6bdddf 4608 as_bad (_("bad register name `%s'"), base_string);
24eab124 4609 return 0;
c3332e24 4610 }
24eab124
AM		 4611 }
4612
4613 /* If there's an expression beginning the operand, parse it,
4614 assuming displacement_string_start and
4615 displacement_string_end are meaningful. */
4616 if (displacement_string_start != displacement_string_end)
4617 {
4618 if (!i386_displacement (displacement_string_start,
4619 displacement_string_end))
4620 return 0;
4621 }
4622
4623 /* Special case for (%dx) while doing input/output op. */
4624 if (i.base_reg
4625 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4626 && i.index_reg == 0
4627 && i.log2_scale_factor == 0
4628 && i.seg[i.mem_operands] == 0
4629 && (i.types[this_operand] & Disp) == 0)
4630 {
4631 i.types[this_operand] = InOutPortReg;
4632 return 1;
4633 }
4634
eecb386c
AM		 4635 if (i386_index_check (operand_string) == 0)
4636 return 0;
24eab124
AM		 4637 i.mem_operands++;
4638 }
4639 else
ce8a8b2f
AM		 4640 {
4641 /* It's not a memory operand; argh! */
24eab124
AM		 4642 as_bad (_("invalid char %s beginning operand %d `%s'"),
4643 output_invalid (*op_string),
4644 this_operand + 1,
4645 op_string);
4646 return 0;
4647 }
47926f60 4648 return 1; /* Normal return. */
252b5132
RH		 4649}
4650\f
ee7fcc42
AM		 4651/* md_estimate_size_before_relax()
4652
4653 Called just before relax() for rs_machine_dependent frags. The x86
4654 assembler uses these frags to handle variable size jump
4655 instructions.
4656
4657 Any symbol that is now undefined will not become defined.
4658 Return the correct fr_subtype in the frag.
4659 Return the initial "guess for variable size of frag" to caller.
4660 The guess is actually the growth beyond the fixed part. Whatever
4661 we do to grow the fixed or variable part contributes to our
4662 returned value. */
4663
252b5132
RH		 4664int
4665md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4666 fragS *fragP;
4667 segT segment;
252b5132 4668{
252b5132 4669 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4670 check for un-relaxable symbols. On an ELF system, we can't relax
4671 an externally visible symbol, because it may be overridden by a
4672 shared library. */
4673 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4674#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4675 || (IS_ELF
31312f95
AM		 4676 && (S_IS_EXTERNAL (fragP->fr_symbol)
4677 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4678#endif
4679 )
252b5132 4680 {
b98ef147
AM		 4681 /* Symbol is undefined in this segment, or we need to keep a
4682 reloc so that weak symbols can be overridden. */
4683 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4684 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4685 unsigned char *opcode;
4686 int old_fr_fix;
f6af82bd 4687
ee7fcc42
AM		 4688 if (fragP->fr_var != NO_RELOC)
4689 reloc_type = fragP->fr_var;
b98ef147 4690 else if (size == 2)
f6af82bd
AM		 4691 reloc_type = BFD_RELOC_16_PCREL;
4692 else
4693 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4694
ee7fcc42
AM		 4695 old_fr_fix = fragP->fr_fix;
4696 opcode = (unsigned char *) fragP->fr_opcode;
4697
fddf5b5b 4698 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4699 {
fddf5b5b
AM		 4700 case UNCOND_JUMP:
4701 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4702 opcode[0] = 0xe9;
252b5132 4703 fragP->fr_fix += size;
062cd5e7
AS		 4704 fix_new (fragP, old_fr_fix, size,
4705 fragP->fr_symbol,
4706 fragP->fr_offset, 1,
4707 reloc_type);
252b5132
RH		 4708 break;
4709
fddf5b5b 4710 case COND_JUMP86:
412167cb
AM		 4711 if (size == 2
4712 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4713 {
4714 /* Negate the condition, and branch past an
4715 unconditional jump. */
4716 opcode[0] ^= 1;
4717 opcode[1] = 3;
4718 /* Insert an unconditional jump. */
4719 opcode[2] = 0xe9;
4720 /* We added two extra opcode bytes, and have a two byte
4721 offset. */
4722 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4723 fix_new (fragP, old_fr_fix + 2, 2,
4724 fragP->fr_symbol,
4725 fragP->fr_offset, 1,
4726 reloc_type);
fddf5b5b
AM		 4727 break;
4728 }
4729 /* Fall through. */
4730
4731 case COND_JUMP:
412167cb
AM		 4732 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4733 {
3e02c1cc
AM		 4734 fixS *fixP;
4735
412167cb 4736 fragP->fr_fix += 1;
3e02c1cc
AM		 4737 fixP = fix_new (fragP, old_fr_fix, 1,
4738 fragP->fr_symbol,
4739 fragP->fr_offset, 1,
4740 BFD_RELOC_8_PCREL);
4741 fixP->fx_signed = 1;
412167cb
AM		 4742 break;
4743 }
93c2a809 4744
24eab124 4745 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4746 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4747 opcode[1] = opcode[0] + 0x10;
f6af82bd 4748 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4749 /* We've added an opcode byte. */
4750 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4751 fix_new (fragP, old_fr_fix + 1, size,
4752 fragP->fr_symbol,
4753 fragP->fr_offset, 1,
4754 reloc_type);
252b5132 4755 break;
fddf5b5b
AM		 4756
4757 default:
4758 BAD_CASE (fragP->fr_subtype);
4759 break;
252b5132
RH		 4760 }
4761 frag_wane (fragP);
ee7fcc42 4762 return fragP->fr_fix - old_fr_fix;
252b5132 4763 }
93c2a809 4764
93c2a809
AM		 4765 /* Guess size depending on current relax state. Initially the relax
4766 state will correspond to a short jump and we return 1, because
4767 the variable part of the frag (the branch offset) is one byte
4768 long. However, we can relax a section more than once and in that
4769 case we must either set fr_subtype back to the unrelaxed state,
4770 or return the value for the appropriate branch. */
4771 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4772}
4773
47926f60
KH		 4774/* Called after relax() is finished.
4775
4776 In: Address of frag.
4777 fr_type == rs_machine_dependent.
4778 fr_subtype is what the address relaxed to.
4779
4780 Out: Any fixSs and constants are set up.
4781 Caller will turn frag into a ".space 0". */
4782
252b5132
RH		 4783void
4784md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4785 bfd *abfd ATTRIBUTE_UNUSED;
4786 segT sec ATTRIBUTE_UNUSED;
29b0f896 4787 fragS *fragP;
252b5132 4788{
29b0f896 4789 unsigned char *opcode;
252b5132 4790 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4791 offsetT target_address;
4792 offsetT opcode_address;
252b5132 4793 unsigned int extension = 0;
847f7ad4 4794 offsetT displacement_from_opcode_start;
252b5132
RH		 4795
4796 opcode = (unsigned char *) fragP->fr_opcode;
4797
47926f60 4798 /* Address we want to reach in file space. */
252b5132 4799 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4800
47926f60 4801 /* Address opcode resides at in file space. */
252b5132
RH		 4802 opcode_address = fragP->fr_address + fragP->fr_fix;
4803
47926f60 4804 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4805 displacement_from_opcode_start = target_address - opcode_address;
4806
fddf5b5b 4807 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4808 {
47926f60
KH		 4809 /* Don't have to change opcode. */
4810 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4811 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4812 }
4813 else
4814 {
4815 if (no_cond_jump_promotion
4816 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4817 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4818
fddf5b5b
AM		 4819 switch (fragP->fr_subtype)
4820 {
4821 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4822 extension = 4; /* 1 opcode + 4 displacement */
4823 opcode[0] = 0xe9;
4824 where_to_put_displacement = &opcode[1];
4825 break;
252b5132 4826
fddf5b5b
AM		 4827 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4828 extension = 2; /* 1 opcode + 2 displacement */
4829 opcode[0] = 0xe9;
4830 where_to_put_displacement = &opcode[1];
4831 break;
252b5132 4832
fddf5b5b
AM		 4833 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4834 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4835 extension = 5; /* 2 opcode + 4 displacement */
4836 opcode[1] = opcode[0] + 0x10;
4837 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4838 where_to_put_displacement = &opcode[2];
4839 break;
252b5132 4840
fddf5b5b
AM		 4841 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4842 extension = 3; /* 2 opcode + 2 displacement */
4843 opcode[1] = opcode[0] + 0x10;
4844 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4845 where_to_put_displacement = &opcode[2];
4846 break;
252b5132 4847
fddf5b5b
AM		 4848 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4849 extension = 4;
4850 opcode[0] ^= 1;
4851 opcode[1] = 3;
4852 opcode[2] = 0xe9;
4853 where_to_put_displacement = &opcode[3];
4854 break;
4855
4856 default:
4857 BAD_CASE (fragP->fr_subtype);
4858 break;
4859 }
252b5132 4860 }
fddf5b5b 4861
47926f60 4862 /* Now put displacement after opcode. */
252b5132
RH		 4863 md_number_to_chars ((char *) where_to_put_displacement,
4864 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4865 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4866 fragP->fr_fix += extension;
4867}
4868\f
47926f60
KH		 4869/* Size of byte displacement jmp. */
4870int md_short_jump_size = 2;
4871
4872/* Size of dword displacement jmp. */
4873int md_long_jump_size = 5;
252b5132 4874
252b5132
RH		 4875void
4876md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4877 char *ptr;
4878 addressT from_addr, to_addr;
ab9da554
ILT		 4879 fragS *frag ATTRIBUTE_UNUSED;
4880 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4881{
847f7ad4 4882 offsetT offset;
252b5132
RH		 4883
4884 offset = to_addr - (from_addr + 2);
47926f60
KH		 4885 /* Opcode for byte-disp jump. */
4886 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4887 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4888}
4889
4890void
4891md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4892 char *ptr;
4893 addressT from_addr, to_addr;
a38cf1db
AM		 4894 fragS *frag ATTRIBUTE_UNUSED;
4895 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4896{
847f7ad4 4897 offsetT offset;
252b5132 4898
a38cf1db
AM		 4899 offset = to_addr - (from_addr + 5);
4900 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4901 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4902}
4903\f
4904/* Apply a fixup (fixS) to segment data, once it has been determined
4905 by our caller that we have all the info we need to fix it up.
4906
4907 On the 386, immediates, displacements, and data pointers are all in
4908 the same (little-endian) format, so we don't need to care about which
4909 we are handling. */
4910
94f592af 4911void
55cf6793 4912md_apply_fix (fixP, valP, seg)
47926f60
KH		 4913 /* The fix we're to put in. */
4914 fixS *fixP;
47926f60 4915 /* Pointer to the value of the bits. */
c6682705 4916 valueT *valP;
47926f60
KH		 4917 /* Segment fix is from. */
4918 segT seg ATTRIBUTE_UNUSED;
252b5132 4919{
94f592af 4920 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4921 valueT value = *valP;
252b5132 4922
f86103b7 4923#if !defined (TE_Mach)
93382f6d
AM		 4924 if (fixP->fx_pcrel)
4925 {
4926 switch (fixP->fx_r_type)
4927 {
5865bb77
ILT		 4928 default:
4929 break;
4930
d6ab8113
JB		 4931 case BFD_RELOC_64:
4932 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4933 break;
93382f6d 4934 case BFD_RELOC_32:
ae8887b5 4935 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4936 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4937 break;
4938 case BFD_RELOC_16:
4939 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4940 break;
4941 case BFD_RELOC_8:
4942 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4943 break;
4944 }
4945 }
252b5132 4946
a161fe53 4947 if (fixP->fx_addsy != NULL
31312f95 4948 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4949 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4950 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4951 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4952 && !use_rela_relocations)
252b5132 4953 {
31312f95
AM		 4954 /* This is a hack. There should be a better way to handle this.
4955 This covers for the fact that bfd_install_relocation will
4956 subtract the current location (for partial_inplace, PC relative
4957 relocations); see more below. */
252b5132 4958#ifndef OBJ_AOUT
718ddfc0 4959 if (IS_ELF
252b5132
RH		 4960#ifdef TE_PE
4961 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4962#endif
4963 )
4964 value += fixP->fx_where + fixP->fx_frag->fr_address;
4965#endif
4966#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4967 if (IS_ELF)
252b5132 4968 {
6539b54b 4969 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4970
6539b54b 4971 if ((sym_seg == seg
2f66722d 4972 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4973 && sym_seg != absolute_section))
ae6063d4 4974 && !generic_force_reloc (fixP))
2f66722d
AM		 4975 {
4976 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4977 bfd_install_relocation subtracts them out again. I think
4978 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4979 it. FIXME. */
4980 value += fixP->fx_where + fixP->fx_frag->fr_address;
4981 }
252b5132
RH		 4982 }
4983#endif
4984#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4985 /* For some reason, the PE format does not store a
4986 section address offset for a PC relative symbol. */
4987 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 4988 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 4989 value += md_pcrel_from (fixP);
4990#endif
4991 }
4992
4993 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4994 and we must not disappoint it. */
252b5132 4995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4996 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 4997 switch (fixP->fx_r_type)
4998 {
4999 case BFD_RELOC_386_PLT32:
3e73aa7c 5000 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5001 /* Make the jump instruction point to the address of the operand. At
5002 runtime we merely add the offset to the actual PLT entry. */
5003 value = -4;
5004 break;
31312f95 5005
13ae64f3
JJ		 5006 case BFD_RELOC_386_TLS_GD:
5007 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5008 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5009 case BFD_RELOC_386_TLS_IE:
5010 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5011 case BFD_RELOC_X86_64_TLSGD:
5012 case BFD_RELOC_X86_64_TLSLD:
5013 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5014 value = 0; /* Fully resolved at runtime. No addend. */
5015 /* Fallthrough */
5016 case BFD_RELOC_386_TLS_LE:
5017 case BFD_RELOC_386_TLS_LDO_32:
5018 case BFD_RELOC_386_TLS_LE_32:
5019 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5020 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5021 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5022 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5023 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5024 break;
5025
5026 case BFD_RELOC_386_GOT32:
5027 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5028 value = 0; /* Fully resolved at runtime. No addend. */
5029 break;
47926f60
KH		 5030
5031 case BFD_RELOC_VTABLE_INHERIT:
5032 case BFD_RELOC_VTABLE_ENTRY:
5033 fixP->fx_done = 0;
94f592af 5034 return;
47926f60
KH		 5035
5036 default:
5037 break;
5038 }
5039#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5040 *valP = value;
f86103b7 5041#endif /* !defined (TE_Mach) */
3e73aa7c 5042
3e73aa7c 5043 /* Are we finished with this relocation now? */
c6682705 5044 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5045 fixP->fx_done = 1;
5046 else if (use_rela_relocations)
5047 {
5048 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5049 /* Remember value for tc_gen_reloc. */
5050 fixP->fx_addnumber = value;
3e73aa7c
JH		 5051 value = 0;
5052 }
f86103b7 5053
94f592af 5054 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5055}
252b5132 5056\f
252b5132
RH		 5057#define MAX_LITTLENUMS 6
5058
47926f60
KH		 5059/* Turn the string pointed to by litP into a floating point constant
5060 of type TYPE, and emit the appropriate bytes. The number of
5061 LITTLENUMS emitted is stored in *SIZEP. An error message is
5062 returned, or NULL on OK. */
5063
252b5132
RH		 5064char *
5065md_atof (type, litP, sizeP)
2ab9b79e 5066 int type;
252b5132
RH		 5067 char *litP;
5068 int *sizeP;
5069{
5070 int prec;
5071 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5072 LITTLENUM_TYPE *wordP;
5073 char *t;
5074
5075 switch (type)
5076 {
5077 case 'f':
5078 case 'F':
5079 prec = 2;
5080 break;
5081
5082 case 'd':
5083 case 'D':
5084 prec = 4;
5085 break;
5086
5087 case 'x':
5088 case 'X':
5089 prec = 5;
5090 break;
5091
5092 default:
5093 *sizeP = 0;
5094 return _("Bad call to md_atof ()");
5095 }
5096 t = atof_ieee (input_line_pointer, type, words);
5097 if (t)
5098 input_line_pointer = t;
5099
5100 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5101 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5102 the bigendian 386. */
5103 for (wordP = words + prec - 1; prec--;)
5104 {
5105 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5106 litP += sizeof (LITTLENUM_TYPE);
5107 }
5108 return 0;
5109}
5110\f
87c245cc 5111static char output_invalid_buf[8];
252b5132 5112
252b5132
RH		 5113static char *
5114output_invalid (c)
5115 int c;
5116{
3882b010 5117 if (ISPRINT (c))
252b5132
RH		 5118 sprintf (output_invalid_buf, "'%c'", c);
5119 else
5120 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5121 return output_invalid_buf;
5122}
5123
af6bdddf 5124/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5125
5126static const reg_entry *
5127parse_register (reg_string, end_op)
5128 char *reg_string;
5129 char **end_op;
5130{
af6bdddf
AM		 5131 char *s = reg_string;
5132 char *p;
252b5132
RH		 5133 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5134 const reg_entry *r;
5135
5136 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5137 if (*s == REGISTER_PREFIX)
5138 ++s;
5139
5140 if (is_space_char (*s))
5141 ++s;
5142
5143 p = reg_name_given;
af6bdddf 5144 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5145 {
5146 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5147 return (const reg_entry *) NULL;
5148 s++;
252b5132
RH		 5149 }
5150
6588847e
DN		 5151 /* For naked regs, make sure that we are not dealing with an identifier.
5152 This prevents confusing an identifier like `eax_var' with register
5153 `eax'. */
5154 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5155 return (const reg_entry *) NULL;
5156
af6bdddf 5157 *end_op = s;
252b5132
RH		 5158
5159 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5160
5f47d35b 5161 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5162 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5163 {
5f47d35b
AM		 5164 if (is_space_char (*s))
5165 ++s;
5166 if (*s == '(')
5167 {
af6bdddf 5168 ++s;
5f47d35b
AM		 5169 if (is_space_char (*s))
5170 ++s;
5171 if (*s >= '0' && *s <= '7')
5172 {
5173 r = &i386_float_regtab[*s - '0'];
af6bdddf 5174 ++s;
5f47d35b
AM		 5175 if (is_space_char (*s))
5176 ++s;
5177 if (*s == ')')
5178 {
5179 *end_op = s + 1;
5180 return r;
5181 }
5f47d35b 5182 }
47926f60 5183 /* We have "%st(" then garbage. */
5f47d35b
AM		 5184 return (const reg_entry *) NULL;
5185 }
5186 }
5187
1ae00879 5188 if (r != NULL
20f0a1fc 5189 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5190 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5191 && flag_code != CODE_64BIT)
20f0a1fc 5192 return (const reg_entry *) NULL;
1ae00879 5193
252b5132
RH		 5194 return r;
5195}
5196\f
4cc782b5 5197#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5198const char *md_shortopts = "kVQ:sqn";
252b5132 5199#else
12b55ccc 5200const char *md_shortopts = "qn";
252b5132 5201#endif
6e0b89ee 5202
252b5132 5203struct option md_longopts[] = {
3e73aa7c
JH		 5204#define OPTION_32 (OPTION_MD_BASE + 0)
5205 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5207#define OPTION_64 (OPTION_MD_BASE + 1)
5208 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5209#endif
252b5132
RH		 5210 {NULL, no_argument, NULL, 0}
5211};
5212size_t md_longopts_size = sizeof (md_longopts);
5213
5214int
5215md_parse_option (c, arg)
5216 int c;
ab9da554 5217 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5218{
5219 switch (c)
5220 {
12b55ccc
L		 5221 case 'n':
5222 optimize_align_code = 0;
5223 break;
5224
a38cf1db
AM		 5225 case 'q':
5226 quiet_warnings = 1;
252b5132
RH		 5227 break;
5228
5229#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5230 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5231 should be emitted or not. FIXME: Not implemented. */
5232 case 'Q':
252b5132
RH		 5233 break;
5234
5235 /* -V: SVR4 argument to print version ID. */
5236 case 'V':
5237 print_version_id ();
5238 break;
5239
a38cf1db
AM		 5240 /* -k: Ignore for FreeBSD compatibility. */
5241 case 'k':
252b5132 5242 break;
4cc782b5
ILT		 5243
5244 case 's':
5245 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5246 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5247 break;
6e0b89ee 5248
3e73aa7c
JH		 5249 case OPTION_64:
5250 {
5251 const char **list, **l;
5252
3e73aa7c
JH		 5253 list = bfd_target_list ();
5254 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5255 if (strcmp (*l, "elf64-x86-64") == 0)
5256 {
5257 default_arch = "x86_64";
5258 break;
5259 }
3e73aa7c 5260 if (*l == NULL)
6e0b89ee 5261 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5262 free (list);
5263 }
5264 break;
5265#endif
252b5132 5266
6e0b89ee
AM		 5267 case OPTION_32:
5268 default_arch = "i386";
5269 break;
5270
252b5132
RH		 5271 default:
5272 return 0;
5273 }
5274 return 1;
5275}
5276
5277void
5278md_show_usage (stream)
5279 FILE *stream;
5280{
4cc782b5
ILT		 5281#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5282 fprintf (stream, _("\
a38cf1db
AM		 5283 -Q ignored\n\
5284 -V print assembler version number\n\
5285 -k ignored\n\
12b55ccc 5286 -n Do not optimize code alignment\n\
a38cf1db
AM		 5287 -q quieten some warnings\n\
5288 -s ignored\n"));
5289#else
5290 fprintf (stream, _("\
12b55ccc 5291 -n Do not optimize code alignment\n\
a38cf1db 5292 -q quieten some warnings\n"));
4cc782b5 5293#endif
252b5132
RH		 5294}
5295
3e73aa7c
JH		 5296#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5297 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5298
5299/* Pick the target format to use. */
5300
47926f60 5301const char *
252b5132
RH		 5302i386_target_format ()
5303{
3e73aa7c
JH		 5304 if (!strcmp (default_arch, "x86_64"))
5305 set_code_flag (CODE_64BIT);
5306 else if (!strcmp (default_arch, "i386"))
5307 set_code_flag (CODE_32BIT);
5308 else
5309 as_fatal (_("Unknown architecture"));
252b5132
RH		 5310 switch (OUTPUT_FLAVOR)
5311 {
4c63da97
AM		 5312#ifdef OBJ_MAYBE_AOUT
5313 case bfd_target_aout_flavour:
47926f60 5314 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5315#endif
5316#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5317 case bfd_target_coff_flavour:
5318 return "coff-i386";
4c63da97 5319#endif
3e73aa7c 5320#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5321 case bfd_target_elf_flavour:
3e73aa7c 5322 {
e5cb08ac 5323 if (flag_code == CODE_64BIT)
4fa24527
JB		 5324 {
5325 object_64bit = 1;
5326 use_rela_relocations = 1;
5327 }
4ada7262 5328 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5329 }
4c63da97 5330#endif
252b5132
RH		 5331 default:
5332 abort ();
5333 return NULL;
5334 }
5335}
5336
47926f60 5337#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5338
5339#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5340void i386_elf_emit_arch_note ()
5341{
718ddfc0 5342 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5343 {
5344 char *p;
5345 asection *seg = now_seg;
5346 subsegT subseg = now_subseg;
5347 Elf_Internal_Note i_note;
5348 Elf_External_Note e_note;
5349 asection *note_secp;
5350 int len;
5351
5352 /* Create the .note section. */
5353 note_secp = subseg_new (".note", 0);
5354 bfd_set_section_flags (stdoutput,
5355 note_secp,
5356 SEC_HAS_CONTENTS | SEC_READONLY);
5357
5358 /* Process the arch string. */
5359 len = strlen (cpu_arch_name);
5360
5361 i_note.namesz = len + 1;
5362 i_note.descsz = 0;
5363 i_note.type = NT_ARCH;
5364 p = frag_more (sizeof (e_note.namesz));
5365 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5366 p = frag_more (sizeof (e_note.descsz));
5367 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5368 p = frag_more (sizeof (e_note.type));
5369 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5370 p = frag_more (len + 1);
5371 strcpy (p, cpu_arch_name);
5372
5373 frag_align (2, 0, 0);
5374
5375 subseg_set (seg, subseg);
5376 }
5377}
5378#endif
252b5132 5379\f
252b5132
RH		 5380symbolS *
5381md_undefined_symbol (name)
5382 char *name;
5383{
18dc2407
ILT		 5384 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5385 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5386 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5387 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5388 {
5389 if (!GOT_symbol)
5390 {
5391 if (symbol_find (name))
5392 as_bad (_("GOT already in symbol table"));
5393 GOT_symbol = symbol_new (name, undefined_section,
5394 (valueT) 0, &zero_address_frag);
5395 };
5396 return GOT_symbol;
5397 }
252b5132
RH		 5398 return 0;
5399}
5400
5401/* Round up a section size to the appropriate boundary. */
47926f60 5402
252b5132
RH		 5403valueT
5404md_section_align (segment, size)
ab9da554 5405 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5406 valueT size;
5407{
4c63da97
AM		 5408#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5409 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5410 {
5411 /* For a.out, force the section size to be aligned. If we don't do
5412 this, BFD will align it for us, but it will not write out the
5413 final bytes of the section. This may be a bug in BFD, but it is
5414 easier to fix it here since that is how the other a.out targets
5415 work. */
5416 int align;
5417
5418 align = bfd_get_section_alignment (stdoutput, segment);
5419 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5420 }
252b5132
RH		 5421#endif
5422
5423 return size;
5424}
5425
5426/* On the i386, PC-relative offsets are relative to the start of the
5427 next instruction. That is, the address of the offset, plus its
5428 size, since the offset is always the last part of the insn. */
5429
5430long
5431md_pcrel_from (fixP)
5432 fixS *fixP;
5433{
5434 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5435}
5436
5437#ifndef I386COFF
5438
5439static void
5440s_bss (ignore)
ab9da554 5441 int ignore ATTRIBUTE_UNUSED;
252b5132 5442{
29b0f896 5443 int temp;
252b5132 5444
8a75718c
JB		 5445#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5446 if (IS_ELF)
5447 obj_elf_section_change_hook ();
5448#endif
252b5132
RH		 5449 temp = get_absolute_expression ();
5450 subseg_set (bss_section, (subsegT) temp);
5451 demand_empty_rest_of_line ();
5452}
5453
5454#endif
5455
252b5132
RH		 5456void
5457i386_validate_fix (fixp)
5458 fixS *fixp;
5459{
5460 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5461 {
23df1078
JH		 5462 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5463 {
4fa24527 5464 if (!object_64bit)
23df1078
JH		 5465 abort ();
5466 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5467 }
5468 else
5469 {
4fa24527 5470 if (!object_64bit)
d6ab8113
JB		 5471 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5472 else
5473 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5474 }
252b5132
RH		 5475 fixp->fx_subsy = 0;
5476 }
5477}
5478
252b5132
RH		 5479arelent *
5480tc_gen_reloc (section, fixp)
ab9da554 5481 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5482 fixS *fixp;
5483{
5484 arelent *rel;
5485 bfd_reloc_code_real_type code;
5486
5487 switch (fixp->fx_r_type)
5488 {
3e73aa7c
JH		 5489 case BFD_RELOC_X86_64_PLT32:
5490 case BFD_RELOC_X86_64_GOT32:
5491 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5492 case BFD_RELOC_386_PLT32:
5493 case BFD_RELOC_386_GOT32:
5494 case BFD_RELOC_386_GOTOFF:
5495 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5496 case BFD_RELOC_386_TLS_GD:
5497 case BFD_RELOC_386_TLS_LDM:
5498 case BFD_RELOC_386_TLS_LDO_32:
5499 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5500 case BFD_RELOC_386_TLS_IE:
5501 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5502 case BFD_RELOC_386_TLS_LE_32:
5503 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5504 case BFD_RELOC_X86_64_TLSGD:
5505 case BFD_RELOC_X86_64_TLSLD:
5506 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5507 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5508 case BFD_RELOC_X86_64_GOTTPOFF:
5509 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5510 case BFD_RELOC_X86_64_TPOFF64:
5511 case BFD_RELOC_X86_64_GOTOFF64:
5512 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5513 case BFD_RELOC_RVA:
5514 case BFD_RELOC_VTABLE_ENTRY:
5515 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5516#ifdef TE_PE
5517 case BFD_RELOC_32_SECREL:
5518#endif
252b5132
RH		 5519 code = fixp->fx_r_type;
5520 break;
dbbaec26
L		 5521 case BFD_RELOC_X86_64_32S:
5522 if (!fixp->fx_pcrel)
5523 {
5524 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5525 code = fixp->fx_r_type;
5526 break;
5527 }
252b5132 5528 default:
93382f6d 5529 if (fixp->fx_pcrel)
252b5132 5530 {
93382f6d
AM		 5531 switch (fixp->fx_size)
5532 {
5533 default:
b091f402
AM		 5534 as_bad_where (fixp->fx_file, fixp->fx_line,
5535 _("can not do %d byte pc-relative relocation"),
5536 fixp->fx_size);
93382f6d
AM		 5537 code = BFD_RELOC_32_PCREL;
5538 break;
5539 case 1: code = BFD_RELOC_8_PCREL; break;
5540 case 2: code = BFD_RELOC_16_PCREL; break;
5541 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5542#ifdef BFD64
5543 case 8: code = BFD_RELOC_64_PCREL; break;
5544#endif
93382f6d
AM		 5545 }
5546 }
5547 else
5548 {
5549 switch (fixp->fx_size)
5550 {
5551 default:
b091f402
AM		 5552 as_bad_where (fixp->fx_file, fixp->fx_line,
5553 _("can not do %d byte relocation"),
5554 fixp->fx_size);
93382f6d
AM		 5555 code = BFD_RELOC_32;
5556 break;
5557 case 1: code = BFD_RELOC_8; break;
5558 case 2: code = BFD_RELOC_16; break;
5559 case 4: code = BFD_RELOC_32; break;
937149dd 5560#ifdef BFD64
3e73aa7c 5561 case 8: code = BFD_RELOC_64; break;
937149dd 5562#endif
93382f6d 5563 }
252b5132
RH		 5564 }
5565 break;
5566 }
252b5132 5567
d182319b
JB		 5568 if ((code == BFD_RELOC_32
5569 || code == BFD_RELOC_32_PCREL
5570 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 5571 && GOT_symbol
5572 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5573 {
4fa24527 5574 if (!object_64bit)
d6ab8113
JB		 5575 code = BFD_RELOC_386_GOTPC;
5576 else
5577 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5578 }
252b5132
RH		 5579
5580 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5581 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5582 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5583
5584 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5585
3e73aa7c
JH		 5586 if (!use_rela_relocations)
5587 {
5588 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5589 vtable entry to be used in the relocation's section offset. */
5590 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5591 rel->address = fixp->fx_offset;
252b5132 5592
c6682705 5593 rel->addend = 0;
3e73aa7c
JH		 5594 }
5595 /* Use the rela in 64bit mode. */
252b5132 5596 else
3e73aa7c 5597 {
062cd5e7
AS		 5598 if (!fixp->fx_pcrel)
5599 rel->addend = fixp->fx_offset;
5600 else
5601 switch (code)
5602 {
5603 case BFD_RELOC_X86_64_PLT32:
5604 case BFD_RELOC_X86_64_GOT32:
5605 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5606 case BFD_RELOC_X86_64_TLSGD:
5607 case BFD_RELOC_X86_64_TLSLD:
5608 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5609 rel->addend = fixp->fx_offset - fixp->fx_size;
5610 break;
5611 default:
5612 rel->addend = (section->vma
5613 - fixp->fx_size
5614 + fixp->fx_addnumber
5615 + md_pcrel_from (fixp));
5616 break;
5617 }
3e73aa7c
JH		 5618 }
5619
252b5132
RH		 5620 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5621 if (rel->howto == NULL)
5622 {
5623 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5624 _("cannot represent relocation type %s"),
252b5132
RH		 5625 bfd_get_reloc_code_name (code));
5626 /* Set howto to a garbage value so that we can keep going. */
5627 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5628 assert (rel->howto != NULL);
5629 }
5630
5631 return rel;
5632}
5633
64a0c779
DN		 5634\f
5635/* Parse operands using Intel syntax. This implements a recursive descent
5636 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5637 Programmer's Guide.
5638
5639 FIXME: We do not recognize the full operand grammar defined in the MASM
5640 documentation. In particular, all the structure/union and
5641 high-level macro operands are missing.
5642
5643 Uppercase words are terminals, lower case words are non-terminals.
5644 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5645 bars '|' denote choices. Most grammar productions are implemented in
5646 functions called 'intel_<production>'.
5647
5648 Initial production is 'expr'.
5649
9306ca4a 5650 addOp + | -
64a0c779
DN		 5651
5652 alpha [a-zA-Z]
5653
9306ca4a
JB		 5654 binOp & | AND | \| | OR | ^ | XOR
5655
64a0c779
DN		 5656 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5657
5658 constant digits [[ radixOverride ]]
5659
9306ca4a 5660 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5661
5662 digits decdigit
b77a7acd
AJ		 5663 | digits decdigit
5664 | digits hexdigit
64a0c779
DN		 5665
5666 decdigit [0-9]
5667
9306ca4a
JB		 5668 e04 e04 addOp e05
5669 | e05
5670
5671 e05 e05 binOp e06
b77a7acd 5672 | e06
64a0c779
DN		 5673
5674 e06 e06 mulOp e09
b77a7acd 5675 | e09
64a0c779
DN		 5676
5677 e09 OFFSET e10
a724f0f4
JB		 5678 | SHORT e10
5679 | + e10
5680 | - e10
9306ca4a
JB		 5681 | ~ e10
5682 | NOT e10
64a0c779
DN		 5683 | e09 PTR e10
5684 | e09 : e10
5685 | e10
5686
5687 e10 e10 [ expr ]
b77a7acd 5688 | e11
64a0c779
DN		 5689
5690 e11 ( expr )
b77a7acd 5691 | [ expr ]
64a0c779
DN		 5692 | constant
5693 | dataType
5694 | id
5695 | $
5696 | register
5697
a724f0f4 5698 => expr expr cmpOp e04
9306ca4a 5699 | e04
64a0c779
DN		 5700
5701 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5702 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5703
5704 hexdigit a | b | c | d | e | f
b77a7acd 5705 | A | B | C | D | E | F
64a0c779
DN		 5706
5707 id alpha
b77a7acd 5708 | id alpha
64a0c779
DN		 5709 | id decdigit
5710
9306ca4a 5711 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5712
5713 quote " | '
5714
5715 register specialRegister
b77a7acd 5716 | gpRegister
64a0c779
DN		 5717 | byteRegister
5718
5719 segmentRegister CS | DS | ES | FS | GS | SS
5720
9306ca4a 5721 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5722 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5723 | TR3 | TR4 | TR5 | TR6 | TR7
5724
64a0c779
DN		 5725 We simplify the grammar in obvious places (e.g., register parsing is
5726 done by calling parse_register) and eliminate immediate left recursion
5727 to implement a recursive-descent parser.
5728
a724f0f4
JB		 5729 expr e04 expr'
5730
5731 expr' cmpOp e04 expr'
5732 | Empty
9306ca4a
JB		 5733
5734 e04 e05 e04'
5735
5736 e04' addOp e05 e04'
5737 | Empty
64a0c779
DN		 5738
5739 e05 e06 e05'
5740
9306ca4a 5741 e05' binOp e06 e05'
b77a7acd 5742 | Empty
64a0c779
DN		 5743
5744 e06 e09 e06'
5745
5746 e06' mulOp e09 e06'
b77a7acd 5747 | Empty
64a0c779
DN		 5748
5749 e09 OFFSET e10 e09'
a724f0f4
JB		 5750 | SHORT e10'
5751 | + e10'
5752 | - e10'
5753 | ~ e10'
5754 | NOT e10'
b77a7acd 5755 | e10 e09'
64a0c779
DN		 5756
5757 e09' PTR e10 e09'
b77a7acd 5758 | : e10 e09'
64a0c779
DN		 5759 | Empty
5760
5761 e10 e11 e10'
5762
5763 e10' [ expr ] e10'
b77a7acd 5764 | Empty
64a0c779
DN		 5765
5766 e11 ( expr )
b77a7acd 5767 | [ expr ]
64a0c779
DN		 5768 | BYTE
5769 | WORD
5770 | DWORD
9306ca4a 5771 | FWORD
64a0c779 5772 | QWORD
9306ca4a
JB		 5773 | TBYTE
5774 | OWORD
5775 | XMMWORD
64a0c779
DN		 5776 | .
5777 | $
5778 | register
5779 | id
5780 | constant */
5781
5782/* Parsing structure for the intel syntax parser. Used to implement the
5783 semantic actions for the operand grammar. */
5784struct intel_parser_s
5785 {
5786 char *op_string; /* The string being parsed. */
5787 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5788 int op_modifier; /* Operand modifier. */
64a0c779 5789 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5790 int in_offset; /* >=1 if parsing operand of offset. */
5791 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5792 const reg_entry *reg; /* Last register reference found. */
5793 char *disp; /* Displacement string being built. */
a724f0f4 5794 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5795 };
5796
5797static struct intel_parser_s intel_parser;
5798
5799/* Token structure for parsing intel syntax. */
5800struct intel_token
5801 {
5802 int code; /* Token code. */
5803 const reg_entry *reg; /* Register entry for register tokens. */
5804 char *str; /* String representation. */
5805 };
5806
5807static struct intel_token cur_token, prev_token;
5808
50705ef4
AM		 5809/* Token codes for the intel parser. Since T_SHORT is already used
5810 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5811#define T_NIL -1
5812#define T_CONST 1
5813#define T_REG 2
5814#define T_BYTE 3
5815#define T_WORD 4
9306ca4a
JB		 5816#define T_DWORD 5
5817#define T_FWORD 6
5818#define T_QWORD 7
5819#define T_TBYTE 8
5820#define T_XMMWORD 9
50705ef4 5821#undef T_SHORT
9306ca4a
JB		 5822#define T_SHORT 10
5823#define T_OFFSET 11
5824#define T_PTR 12
5825#define T_ID 13
5826#define T_SHL 14
5827#define T_SHR 15
64a0c779
DN		 5828
5829/* Prototypes for intel parser functions. */
5830static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5831static void intel_get_token PARAMS ((void));
5832static void intel_putback_token PARAMS ((void));
5833static int intel_expr PARAMS ((void));
9306ca4a 5834static int intel_e04 PARAMS ((void));
cce0cbdc 5835static int intel_e05 PARAMS ((void));
cce0cbdc 5836static int intel_e06 PARAMS ((void));
cce0cbdc 5837static int intel_e09 PARAMS ((void));
a724f0f4 5838static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5839static int intel_e10 PARAMS ((void));
cce0cbdc 5840static int intel_e11 PARAMS ((void));
64a0c779 5841
64a0c779
DN		 5842static int
5843i386_intel_operand (operand_string, got_a_float)
5844 char *operand_string;
5845 int got_a_float;
5846{
5847 int ret;
5848 char *p;
5849
a724f0f4
JB		 5850 p = intel_parser.op_string = xstrdup (operand_string);
5851 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5852
5853 for (;;)
64a0c779 5854 {
a724f0f4
JB		 5855 /* Initialize token holders. */
5856 cur_token.code = prev_token.code = T_NIL;
5857 cur_token.reg = prev_token.reg = NULL;
5858 cur_token.str = prev_token.str = NULL;
5859
5860 /* Initialize parser structure. */
5861 intel_parser.got_a_float = got_a_float;
5862 intel_parser.op_modifier = 0;
5863 intel_parser.is_mem = 0;
5864 intel_parser.in_offset = 0;
5865 intel_parser.in_bracket = 0;
5866 intel_parser.reg = NULL;
5867 intel_parser.disp[0] = '\0';
5868 intel_parser.next_operand = NULL;
5869
5870 /* Read the first token and start the parser. */
5871 intel_get_token ();
5872 ret = intel_expr ();
5873
5874 if (!ret)
5875 break;
5876
9306ca4a
JB		 5877 if (cur_token.code != T_NIL)
5878 {
5879 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5880 current_templates->start->name, cur_token.str);
5881 ret = 0;
5882 }
64a0c779
DN		 5883 /* If we found a memory reference, hand it over to i386_displacement
5884 to fill in the rest of the operand fields. */
9306ca4a 5885 else if (intel_parser.is_mem)
64a0c779
DN		 5886 {
5887 if ((i.mem_operands == 1
5888 && (current_templates->start->opcode_modifier & IsString) == 0)
5889 || i.mem_operands == 2)
5890 {
5891 as_bad (_("too many memory references for '%s'"),
5892 current_templates->start->name);
5893 ret = 0;
5894 }
5895 else
5896 {
5897 char *s = intel_parser.disp;
5898 i.mem_operands++;
5899
a724f0f4
JB		 5900 if (!quiet_warnings && intel_parser.is_mem < 0)
5901 /* See the comments in intel_bracket_expr. */
5902 as_warn (_("Treating `%s' as memory reference"), operand_string);
5903
64a0c779
DN		 5904 /* Add the displacement expression. */
5905 if (*s != '\0')
a4622f40
AM		 5906 ret = i386_displacement (s, s + strlen (s));
5907 if (ret)
a724f0f4
JB		 5908 {
5909 /* Swap base and index in 16-bit memory operands like
5910 [si+bx]. Since i386_index_check is also used in AT&T
5911 mode we have to do that here. */
5912 if (i.base_reg
5913 && i.index_reg
5914 && (i.base_reg->reg_type & Reg16)
5915 && (i.index_reg->reg_type & Reg16)
5916 && i.base_reg->reg_num >= 6
5917 && i.index_reg->reg_num < 6)
5918 {
5919 const reg_entry *base = i.index_reg;
5920
5921 i.index_reg = i.base_reg;
5922 i.base_reg = base;
5923 }
5924 ret = i386_index_check (operand_string);
5925 }
64a0c779
DN		 5926 }
5927 }
5928
5929 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5930 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5931 || intel_parser.reg == NULL)
5932 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5933
5934 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5935 ret = 0;
5936 if (!ret || !intel_parser.next_operand)
5937 break;
5938 intel_parser.op_string = intel_parser.next_operand;
5939 this_operand = i.operands++;
64a0c779
DN		 5940 }
5941
5942 free (p);
5943 free (intel_parser.disp);
5944
5945 return ret;
5946}
5947
a724f0f4
JB		 5948#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5949
5950/* expr e04 expr'
5951
5952 expr' cmpOp e04 expr'
5953 | Empty */
64a0c779
DN		 5954static int
5955intel_expr ()
5956{
a724f0f4
JB		 5957 /* XXX Implement the comparison operators. */
5958 return intel_e04 ();
9306ca4a
JB		 5959}
5960
a724f0f4 5961/* e04 e05 e04'
9306ca4a 5962
a724f0f4 5963 e04' addOp e05 e04'
9306ca4a
JB		 5964 | Empty */
5965static int
5966intel_e04 ()
5967{
a724f0f4 5968 int nregs = -1;
9306ca4a 5969
a724f0f4 5970 for (;;)
9306ca4a 5971 {
a724f0f4
JB		 5972 if (!intel_e05())
5973 return 0;
9306ca4a 5974
a724f0f4
JB		 5975 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5976 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5977
a724f0f4
JB		 5978 if (cur_token.code == '+')
5979 nregs = -1;
5980 else if (cur_token.code == '-')
5981 nregs = NUM_ADDRESS_REGS;
5982 else
5983 return 1;
64a0c779 5984
a724f0f4
JB		 5985 strcat (intel_parser.disp, cur_token.str);
5986 intel_match_token (cur_token.code);
5987 }
64a0c779
DN		 5988}
5989
64a0c779
DN		 5990/* e05 e06 e05'
5991
9306ca4a 5992 e05' binOp e06 e05'
64a0c779
DN		 5993 | Empty */
5994static int
5995intel_e05 ()
5996{
a724f0f4 5997 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5998
a724f0f4 5999 for (;;)
64a0c779 6000 {
a724f0f4
JB		 6001 if (!intel_e06())
6002 return 0;
6003
6004 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6005 {
6006 char str[2];
6007
6008 str[0] = cur_token.code;
6009 str[1] = 0;
6010 strcat (intel_parser.disp, str);
6011 }
6012 else
6013 break;
9306ca4a 6014
64a0c779
DN		 6015 intel_match_token (cur_token.code);
6016
a724f0f4
JB		 6017 if (nregs < 0)
6018 nregs = ~nregs;
64a0c779 6019 }
a724f0f4
JB		 6020 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6021 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6022 return 1;
4a1805b1 6023}
64a0c779
DN		 6024
6025/* e06 e09 e06'
6026
6027 e06' mulOp e09 e06'
b77a7acd 6028 | Empty */
64a0c779
DN		 6029static int
6030intel_e06 ()
6031{
a724f0f4 6032 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6033
a724f0f4 6034 for (;;)
64a0c779 6035 {
a724f0f4
JB		 6036 if (!intel_e09())
6037 return 0;
9306ca4a 6038
a724f0f4
JB		 6039 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6040 {
6041 char str[2];
9306ca4a 6042
a724f0f4
JB		 6043 str[0] = cur_token.code;
6044 str[1] = 0;
6045 strcat (intel_parser.disp, str);
6046 }
6047 else if (cur_token.code == T_SHL)
6048 strcat (intel_parser.disp, "<<");
6049 else if (cur_token.code == T_SHR)
6050 strcat (intel_parser.disp, ">>");
6051 else
6052 break;
9306ca4a 6053
a724f0f4 6054 intel_match_token (cur_token.code);
64a0c779 6055
a724f0f4
JB		 6056 if (nregs < 0)
6057 nregs = ~nregs;
64a0c779 6058 }
a724f0f4
JB		 6059 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6060 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6061 return 1;
64a0c779
DN		 6062}
6063
a724f0f4
JB		 6064/* e09 OFFSET e09
6065 | SHORT e09
6066 | + e09
6067 | - e09
6068 | ~ e09
6069 | NOT e09
9306ca4a
JB		 6070 | e10 e09'
6071
64a0c779 6072 e09' PTR e10 e09'
b77a7acd 6073 | : e10 e09'
64a0c779
DN		 6074 | Empty */
6075static int
6076intel_e09 ()
6077{
a724f0f4
JB		 6078 int nregs = ~NUM_ADDRESS_REGS;
6079 int in_offset = 0;
6080
6081 for (;;)
64a0c779 6082 {
a724f0f4
JB		 6083 /* Don't consume constants here. */
6084 if (cur_token.code == '+' || cur_token.code == '-')
6085 {
6086 /* Need to look one token ahead - if the next token
6087 is a constant, the current token is its sign. */
6088 int next_code;
6089
6090 intel_match_token (cur_token.code);
6091 next_code = cur_token.code;
6092 intel_putback_token ();
6093 if (next_code == T_CONST)
6094 break;
6095 }
6096
6097 /* e09 OFFSET e09 */
6098 if (cur_token.code == T_OFFSET)
6099 {
6100 if (!in_offset++)
6101 ++intel_parser.in_offset;
6102 }
6103
6104 /* e09 SHORT e09 */
6105 else if (cur_token.code == T_SHORT)
6106 intel_parser.op_modifier |= 1 << T_SHORT;
6107
6108 /* e09 + e09 */
6109 else if (cur_token.code == '+')
6110 strcat (intel_parser.disp, "+");
6111
6112 /* e09 - e09
6113 | ~ e09
6114 | NOT e09 */
6115 else if (cur_token.code == '-' || cur_token.code == '~')
6116 {
6117 char str[2];
64a0c779 6118
a724f0f4
JB		 6119 if (nregs < 0)
6120 nregs = ~nregs;
6121 str[0] = cur_token.code;
6122 str[1] = 0;
6123 strcat (intel_parser.disp, str);
6124 }
6125
6126 /* e09 e10 e09' */
6127 else
6128 break;
6129
6130 intel_match_token (cur_token.code);
64a0c779
DN		 6131 }
6132
a724f0f4 6133 for (;;)
9306ca4a 6134 {
a724f0f4
JB		 6135 if (!intel_e10 ())
6136 return 0;
9306ca4a 6137
a724f0f4
JB		 6138 /* e09' PTR e10 e09' */
6139 if (cur_token.code == T_PTR)
6140 {
6141 char suffix;
9306ca4a 6142
a724f0f4
JB		 6143 if (prev_token.code == T_BYTE)
6144 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6145
a724f0f4
JB		 6146 else if (prev_token.code == T_WORD)
6147 {
6148 if (current_templates->start->name[0] == 'l'
6149 && current_templates->start->name[2] == 's'
6150 && current_templates->start->name[3] == 0)
6151 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6152 else if (intel_parser.got_a_float == 2) /* "fi..." */
6153 suffix = SHORT_MNEM_SUFFIX;
6154 else
6155 suffix = WORD_MNEM_SUFFIX;
6156 }
64a0c779 6157
a724f0f4
JB		 6158 else if (prev_token.code == T_DWORD)
6159 {
6160 if (current_templates->start->name[0] == 'l'
6161 && current_templates->start->name[2] == 's'
6162 && current_templates->start->name[3] == 0)
6163 suffix = WORD_MNEM_SUFFIX;
6164 else if (flag_code == CODE_16BIT
6165 && (current_templates->start->opcode_modifier
435acd52 6166 & (Jump | JumpDword)))
a724f0f4
JB		 6167 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6168 else if (intel_parser.got_a_float == 1) /* "f..." */
6169 suffix = SHORT_MNEM_SUFFIX;
6170 else
6171 suffix = LONG_MNEM_SUFFIX;
6172 }
9306ca4a 6173
a724f0f4
JB		 6174 else if (prev_token.code == T_FWORD)
6175 {
6176 if (current_templates->start->name[0] == 'l'
6177 && current_templates->start->name[2] == 's'
6178 && current_templates->start->name[3] == 0)
6179 suffix = LONG_MNEM_SUFFIX;
6180 else if (!intel_parser.got_a_float)
6181 {
6182 if (flag_code == CODE_16BIT)
6183 add_prefix (DATA_PREFIX_OPCODE);
6184 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6185 }
6186 else
6187 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6188 }
64a0c779 6189
a724f0f4
JB		 6190 else if (prev_token.code == T_QWORD)
6191 {
6192 if (intel_parser.got_a_float == 1) /* "f..." */
6193 suffix = LONG_MNEM_SUFFIX;
6194 else
6195 suffix = QWORD_MNEM_SUFFIX;
6196 }
64a0c779 6197
a724f0f4
JB		 6198 else if (prev_token.code == T_TBYTE)
6199 {
6200 if (intel_parser.got_a_float == 1)
6201 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6202 else
6203 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6204 }
9306ca4a 6205
a724f0f4 6206 else if (prev_token.code == T_XMMWORD)
9306ca4a 6207 {
a724f0f4
JB		 6208 /* XXX ignored for now, but accepted since gcc uses it */
6209 suffix = 0;
9306ca4a 6210 }
64a0c779 6211
f16b83df 6212 else
a724f0f4
JB		 6213 {
6214 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6215 return 0;
6216 }
6217
435acd52
JB		 6218 /* Operands for jump/call using 'ptr' notation denote absolute
6219 addresses. */
6220 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6221 i.types[this_operand] |= JumpAbsolute;
6222
a724f0f4
JB		 6223 if (current_templates->start->base_opcode == 0x8d /* lea */)
6224 ;
6225 else if (!i.suffix)
6226 i.suffix = suffix;
6227 else if (i.suffix != suffix)
6228 {
6229 as_bad (_("Conflicting operand modifiers"));
6230 return 0;
6231 }
64a0c779 6232
9306ca4a
JB		 6233 }
6234
a724f0f4
JB		 6235 /* e09' : e10 e09' */
6236 else if (cur_token.code == ':')
9306ca4a 6237 {
a724f0f4
JB		 6238 if (prev_token.code != T_REG)
6239 {
6240 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6241 segment/group identifier (which we don't have), using comma
6242 as the operand separator there is even less consistent, since
6243 there all branches only have a single operand. */
6244 if (this_operand != 0
6245 || intel_parser.in_offset
6246 || intel_parser.in_bracket
6247 || (!(current_templates->start->opcode_modifier
6248 & (Jump|JumpDword|JumpInterSegment))
6249 && !(current_templates->start->operand_types[0]
6250 & JumpAbsolute)))
6251 return intel_match_token (T_NIL);
6252 /* Remember the start of the 2nd operand and terminate 1st
6253 operand here.
6254 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6255 another expression), but it gets at least the simplest case
6256 (a plain number or symbol on the left side) right. */
6257 intel_parser.next_operand = intel_parser.op_string;
6258 *--intel_parser.op_string = '\0';
6259 return intel_match_token (':');
6260 }
9306ca4a 6261 }
64a0c779 6262
a724f0f4 6263 /* e09' Empty */
64a0c779 6264 else
a724f0f4 6265 break;
64a0c779 6266
a724f0f4
JB		 6267 intel_match_token (cur_token.code);
6268
6269 }
6270
6271 if (in_offset)
6272 {
6273 --intel_parser.in_offset;
6274 if (nregs < 0)
6275 nregs = ~nregs;
6276 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6277 {
a724f0f4 6278 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6279 return 0;
6280 }
a724f0f4
JB		 6281 intel_parser.op_modifier |= 1 << T_OFFSET;
6282 }
9306ca4a 6283
a724f0f4
JB		 6284 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6285 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6286 return 1;
6287}
64a0c779 6288
a724f0f4
JB		 6289static int
6290intel_bracket_expr ()
6291{
6292 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6293 const char *start = intel_parser.op_string;
6294 int len;
6295
6296 if (i.op[this_operand].regs)
6297 return intel_match_token (T_NIL);
6298
6299 intel_match_token ('[');
6300
6301 /* Mark as a memory operand only if it's not already known to be an
6302 offset expression. If it's an offset expression, we need to keep
6303 the brace in. */
6304 if (!intel_parser.in_offset)
6305 {
6306 ++intel_parser.in_bracket;
435acd52
JB		 6307
6308 /* Operands for jump/call inside brackets denote absolute addresses. */
6309 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6310 i.types[this_operand] |= JumpAbsolute;
6311
a724f0f4
JB		 6312 /* Unfortunately gas always diverged from MASM in a respect that can't
6313 be easily fixed without risking to break code sequences likely to be
6314 encountered (the testsuite even check for this): MASM doesn't consider
6315 an expression inside brackets unconditionally as a memory reference.
6316 When that is e.g. a constant, an offset expression, or the sum of the
6317 two, this is still taken as a constant load. gas, however, always
6318 treated these as memory references. As a compromise, we'll try to make
6319 offset expressions inside brackets work the MASM way (since that's
6320 less likely to be found in real world code), but make constants alone
6321 continue to work the traditional gas way. In either case, issue a
6322 warning. */
6323 intel_parser.op_modifier &= ~was_offset;
64a0c779 6324 }
a724f0f4
JB		 6325 else
6326 strcat (intel_parser.disp, "[");
6327
6328 /* Add a '+' to the displacement string if necessary. */
6329 if (*intel_parser.disp != '\0'
6330 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6331 strcat (intel_parser.disp, "+");
64a0c779 6332
a724f0f4
JB		 6333 if (intel_expr ()
6334 && (len = intel_parser.op_string - start - 1,
6335 intel_match_token (']')))
64a0c779 6336 {
a724f0f4
JB		 6337 /* Preserve brackets when the operand is an offset expression. */
6338 if (intel_parser.in_offset)
6339 strcat (intel_parser.disp, "]");
6340 else
6341 {
6342 --intel_parser.in_bracket;
6343 if (i.base_reg || i.index_reg)
6344 intel_parser.is_mem = 1;
6345 if (!intel_parser.is_mem)
6346 {
6347 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6348 /* Defer the warning until all of the operand was parsed. */
6349 intel_parser.is_mem = -1;
6350 else if (!quiet_warnings)
6351 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6352 }
6353 }
6354 intel_parser.op_modifier |= was_offset;
64a0c779 6355
a724f0f4 6356 return 1;
64a0c779 6357 }
a724f0f4 6358 return 0;
64a0c779
DN		 6359}
6360
6361/* e10 e11 e10'
6362
6363 e10' [ expr ] e10'
b77a7acd 6364 | Empty */
64a0c779
DN		 6365static int
6366intel_e10 ()
6367{
a724f0f4
JB		 6368 if (!intel_e11 ())
6369 return 0;
64a0c779 6370
a724f0f4 6371 while (cur_token.code == '[')
64a0c779 6372 {
a724f0f4 6373 if (!intel_bracket_expr ())
21d6c4af 6374 return 0;
64a0c779
DN		 6375 }
6376
a724f0f4 6377 return 1;
64a0c779
DN		 6378}
6379
64a0c779 6380/* e11 ( expr )
b77a7acd 6381 | [ expr ]
64a0c779
DN		 6382 | BYTE
6383 | WORD
6384 | DWORD
9306ca4a 6385 | FWORD
64a0c779 6386 | QWORD
9306ca4a
JB		 6387 | TBYTE
6388 | OWORD
6389 | XMMWORD
4a1805b1 6390 | $
64a0c779
DN		 6391 | .
6392 | register
6393 | id
6394 | constant */
6395static int
6396intel_e11 ()
6397{
a724f0f4 6398 switch (cur_token.code)
64a0c779 6399 {
a724f0f4
JB		 6400 /* e11 ( expr ) */
6401 case '(':
64a0c779
DN		 6402 intel_match_token ('(');
6403 strcat (intel_parser.disp, "(");
6404
6405 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6406 {
6407 strcat (intel_parser.disp, ")");
6408 return 1;
6409 }
a724f0f4 6410 return 0;
4a1805b1 6411
a724f0f4
JB		 6412 /* e11 [ expr ] */
6413 case '[':
a724f0f4 6414 return intel_bracket_expr ();
64a0c779 6415
a724f0f4
JB		 6416 /* e11 $
6417 | . */
6418 case '.':
64a0c779
DN		 6419 strcat (intel_parser.disp, cur_token.str);
6420 intel_match_token (cur_token.code);
21d6c4af
DN		 6421
6422 /* Mark as a memory operand only if it's not already known to be an
6423 offset expression. */
a724f0f4 6424 if (!intel_parser.in_offset)
21d6c4af 6425 intel_parser.is_mem = 1;
64a0c779
DN		 6426
6427 return 1;
64a0c779 6428
a724f0f4
JB		 6429 /* e11 register */
6430 case T_REG:
6431 {
6432 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6433
a724f0f4 6434 intel_match_token (T_REG);
64a0c779 6435
a724f0f4
JB		 6436 /* Check for segment change. */
6437 if (cur_token.code == ':')
6438 {
6439 if (!(reg->reg_type & (SReg2 | SReg3)))
6440 {
6441 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6442 return 0;
6443 }
6444 else if (i.seg[i.mem_operands])
6445 as_warn (_("Extra segment override ignored"));
6446 else
6447 {
6448 if (!intel_parser.in_offset)
6449 intel_parser.is_mem = 1;
6450 switch (reg->reg_num)
6451 {
6452 case 0:
6453 i.seg[i.mem_operands] = &es;
6454 break;
6455 case 1:
6456 i.seg[i.mem_operands] = &cs;
6457 break;
6458 case 2:
6459 i.seg[i.mem_operands] = &ss;
6460 break;
6461 case 3:
6462 i.seg[i.mem_operands] = &ds;
6463 break;
6464 case 4:
6465 i.seg[i.mem_operands] = &fs;
6466 break;
6467 case 5:
6468 i.seg[i.mem_operands] = &gs;
6469 break;
6470 }
6471 }
6472 }
64a0c779 6473
a724f0f4
JB		 6474 /* Not a segment register. Check for register scaling. */
6475 else if (cur_token.code == '*')
6476 {
6477 if (!intel_parser.in_bracket)
6478 {
6479 as_bad (_("Register scaling only allowed in memory operands"));
6480 return 0;
6481 }
64a0c779 6482
a724f0f4
JB		 6483 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6484 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6485 else if (i.index_reg)
6486 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6487
a724f0f4
JB		 6488 /* What follows must be a valid scale. */
6489 intel_match_token ('*');
6490 i.index_reg = reg;
6491 i.types[this_operand] |= BaseIndex;
64a0c779 6492
a724f0f4
JB		 6493 /* Set the scale after setting the register (otherwise,
6494 i386_scale will complain) */
6495 if (cur_token.code == '+' || cur_token.code == '-')
6496 {
6497 char *str, sign = cur_token.code;
6498 intel_match_token (cur_token.code);
6499 if (cur_token.code != T_CONST)
6500 {
6501 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6502 cur_token.str);
6503 return 0;
6504 }
6505 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6506 strcpy (str + 1, cur_token.str);
6507 *str = sign;
6508 if (!i386_scale (str))
6509 return 0;
6510 free (str);
6511 }
6512 else if (!i386_scale (cur_token.str))
64a0c779 6513 return 0;
a724f0f4
JB		 6514 intel_match_token (cur_token.code);
6515 }
64a0c779 6516
a724f0f4
JB		 6517 /* No scaling. If this is a memory operand, the register is either a
6518 base register (first occurrence) or an index register (second
6519 occurrence). */
6520 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6521 {
64a0c779 6522
a724f0f4
JB		 6523 if (!i.base_reg)
6524 i.base_reg = reg;
6525 else if (!i.index_reg)
6526 i.index_reg = reg;
6527 else
6528 {
6529 as_bad (_("Too many register references in memory operand"));
6530 return 0;
6531 }
64a0c779 6532
a724f0f4
JB		 6533 i.types[this_operand] |= BaseIndex;
6534 }
4a1805b1 6535
a724f0f4
JB		 6536 /* Offset modifier. Add the register to the displacement string to be
6537 parsed as an immediate expression after we're done. */
6538 else if (intel_parser.in_offset)
6539 {
6540 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6541 strcat (intel_parser.disp, reg->reg_name);
6542 }
64a0c779 6543
a724f0f4
JB		 6544 /* It's neither base nor index nor offset. */
6545 else if (!intel_parser.is_mem)
6546 {
6547 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6548 i.op[this_operand].regs = reg;
6549 i.reg_operands++;
6550 }
6551 else
6552 {
6553 as_bad (_("Invalid use of register"));
6554 return 0;
6555 }
64a0c779 6556
a724f0f4
JB		 6557 /* Since registers are not part of the displacement string (except
6558 when we're parsing offset operands), we may need to remove any
6559 preceding '+' from the displacement string. */
6560 if (*intel_parser.disp != '\0'
6561 && !intel_parser.in_offset)
6562 {
6563 char *s = intel_parser.disp;
6564 s += strlen (s) - 1;
6565 if (*s == '+')
6566 *s = '\0';
6567 }
4a1805b1 6568
a724f0f4
JB		 6569 return 1;
6570 }
6571
6572 /* e11 BYTE
6573 | WORD
6574 | DWORD
6575 | FWORD
6576 | QWORD
6577 | TBYTE
6578 | OWORD
6579 | XMMWORD */
6580 case T_BYTE:
6581 case T_WORD:
6582 case T_DWORD:
6583 case T_FWORD:
6584 case T_QWORD:
6585 case T_TBYTE:
6586 case T_XMMWORD:
6587 intel_match_token (cur_token.code);
64a0c779 6588
a724f0f4
JB		 6589 if (cur_token.code == T_PTR)
6590 return 1;
6591
6592 /* It must have been an identifier. */
6593 intel_putback_token ();
6594 cur_token.code = T_ID;
6595 /* FALLTHRU */
6596
6597 /* e11 id
6598 | constant */
6599 case T_ID:
6600 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6601 {
6602 symbolS *symbolP;
6603
a724f0f4
JB		 6604 /* The identifier represents a memory reference only if it's not
6605 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6606 symbolP = symbol_find(cur_token.str);
6607 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6608 intel_parser.is_mem = 1;
6609 }
a724f0f4 6610 /* FALLTHRU */
64a0c779 6611
a724f0f4
JB		 6612 case T_CONST:
6613 case '-':
6614 case '+':
6615 {
6616 char *save_str, sign = 0;
64a0c779 6617
a724f0f4
JB		 6618 /* Allow constants that start with `+' or `-'. */
6619 if (cur_token.code == '-' || cur_token.code == '+')
6620 {
6621 sign = cur_token.code;
6622 intel_match_token (cur_token.code);
6623 if (cur_token.code != T_CONST)
6624 {
6625 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6626 cur_token.str);
6627 return 0;
6628 }
6629 }
64a0c779 6630
a724f0f4
JB		 6631 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6632 strcpy (save_str + !!sign, cur_token.str);
6633 if (sign)
6634 *save_str = sign;
64a0c779 6635
a724f0f4
JB		 6636 /* Get the next token to check for register scaling. */
6637 intel_match_token (cur_token.code);
64a0c779 6638
a724f0f4
JB		 6639 /* Check if this constant is a scaling factor for an index register. */
6640 if (cur_token.code == '*')
6641 {
6642 if (intel_match_token ('*') && cur_token.code == T_REG)
6643 {
6644 const reg_entry *reg = cur_token.reg;
6645
6646 if (!intel_parser.in_bracket)
6647 {
6648 as_bad (_("Register scaling only allowed in memory operands"));
6649 return 0;
6650 }
6651
6652 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6653 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6654 else if (i.index_reg)
6655 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6656
6657 /* The constant is followed by `* reg', so it must be
6658 a valid scale. */
6659 i.index_reg = reg;
6660 i.types[this_operand] |= BaseIndex;
6661
6662 /* Set the scale after setting the register (otherwise,
6663 i386_scale will complain) */
6664 if (!i386_scale (save_str))
64a0c779 6665 return 0;
a724f0f4
JB		 6666 intel_match_token (T_REG);
6667
6668 /* Since registers are not part of the displacement
6669 string, we may need to remove any preceding '+' from
6670 the displacement string. */
6671 if (*intel_parser.disp != '\0')
6672 {
6673 char *s = intel_parser.disp;
6674 s += strlen (s) - 1;
6675 if (*s == '+')
6676 *s = '\0';
6677 }
6678
6679 free (save_str);
6680
6681 return 1;
6682 }
64a0c779 6683
a724f0f4
JB		 6684 /* The constant was not used for register scaling. Since we have
6685 already consumed the token following `*' we now need to put it
6686 back in the stream. */
64a0c779 6687 intel_putback_token ();
a724f0f4 6688 }
64a0c779 6689
a724f0f4
JB		 6690 /* Add the constant to the displacement string. */
6691 strcat (intel_parser.disp, save_str);
6692 free (save_str);
64a0c779 6693
a724f0f4
JB		 6694 return 1;
6695 }
64a0c779
DN		 6696 }
6697
64a0c779
DN		 6698 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6699 return 0;
6700}
6701
64a0c779
DN		 6702/* Match the given token against cur_token. If they match, read the next
6703 token from the operand string. */
6704static int
6705intel_match_token (code)
e5cb08ac 6706 int code;
64a0c779
DN		 6707{
6708 if (cur_token.code == code)
6709 {
6710 intel_get_token ();
6711 return 1;
6712 }
6713 else
6714 {
0477af35 6715 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6716 return 0;
6717 }
6718}
6719
64a0c779
DN		 6720/* Read a new token from intel_parser.op_string and store it in cur_token. */
6721static void
6722intel_get_token ()
6723{
6724 char *end_op;
6725 const reg_entry *reg;
6726 struct intel_token new_token;
6727
6728 new_token.code = T_NIL;
6729 new_token.reg = NULL;
6730 new_token.str = NULL;
6731
4a1805b1 6732 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6733 cur_token to prev_token. */
6734 if (prev_token.str)
6735 free (prev_token.str);
6736
6737 prev_token = cur_token;
6738
6739 /* Skip whitespace. */
6740 while (is_space_char (*intel_parser.op_string))
6741 intel_parser.op_string++;
6742
6743 /* Return an empty token if we find nothing else on the line. */
6744 if (*intel_parser.op_string == '\0')
6745 {
6746 cur_token = new_token;
6747 return;
6748 }
6749
6750 /* The new token cannot be larger than the remainder of the operand
6751 string. */
a724f0f4 6752 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6753 new_token.str[0] = '\0';
6754
6755 if (strchr ("0123456789", *intel_parser.op_string))
6756 {
6757 char *p = new_token.str;
6758 char *q = intel_parser.op_string;
6759 new_token.code = T_CONST;
6760
6761 /* Allow any kind of identifier char to encompass floating point and
6762 hexadecimal numbers. */
6763 while (is_identifier_char (*q))
6764 *p++ = *q++;
6765 *p = '\0';
6766
6767 /* Recognize special symbol names [0-9][bf]. */
6768 if (strlen (intel_parser.op_string) == 2
4a1805b1 6769 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6770 || intel_parser.op_string[1] == 'f'))
6771 new_token.code = T_ID;
6772 }
6773
64a0c779
DN		 6774 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6775 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6776 {
6777 new_token.code = T_REG;
6778 new_token.reg = reg;
6779
6780 if (*intel_parser.op_string == REGISTER_PREFIX)
6781 {
6782 new_token.str[0] = REGISTER_PREFIX;
6783 new_token.str[1] = '\0';
6784 }
6785
6786 strcat (new_token.str, reg->reg_name);
6787 }
6788
6789 else if (is_identifier_char (*intel_parser.op_string))
6790 {
6791 char *p = new_token.str;
6792 char *q = intel_parser.op_string;
6793
6794 /* A '.' or '$' followed by an identifier char is an identifier.
6795 Otherwise, it's operator '.' followed by an expression. */
6796 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6797 {
9306ca4a
JB		 6798 new_token.code = '.';
6799 new_token.str[0] = '.';
64a0c779
DN		 6800 new_token.str[1] = '\0';
6801 }
6802 else
6803 {
6804 while (is_identifier_char (*q) || *q == '@')
6805 *p++ = *q++;
6806 *p = '\0';
6807
9306ca4a
JB		 6808 if (strcasecmp (new_token.str, "NOT") == 0)
6809 new_token.code = '~';
6810
6811 else if (strcasecmp (new_token.str, "MOD") == 0)
6812 new_token.code = '%';
6813
6814 else if (strcasecmp (new_token.str, "AND") == 0)
6815 new_token.code = '&';
6816
6817 else if (strcasecmp (new_token.str, "OR") == 0)
6818 new_token.code = '|';
6819
6820 else if (strcasecmp (new_token.str, "XOR") == 0)
6821 new_token.code = '^';
6822
6823 else if (strcasecmp (new_token.str, "SHL") == 0)
6824 new_token.code = T_SHL;
6825
6826 else if (strcasecmp (new_token.str, "SHR") == 0)
6827 new_token.code = T_SHR;
6828
6829 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6830 new_token.code = T_BYTE;
6831
6832 else if (strcasecmp (new_token.str, "WORD") == 0)
6833 new_token.code = T_WORD;
6834
6835 else if (strcasecmp (new_token.str, "DWORD") == 0)
6836 new_token.code = T_DWORD;
6837
9306ca4a
JB		 6838 else if (strcasecmp (new_token.str, "FWORD") == 0)
6839 new_token.code = T_FWORD;
6840
64a0c779
DN		 6841 else if (strcasecmp (new_token.str, "QWORD") == 0)
6842 new_token.code = T_QWORD;
6843
9306ca4a
JB		 6844 else if (strcasecmp (new_token.str, "TBYTE") == 0
6845 /* XXX remove (gcc still uses it) */
6846 || strcasecmp (new_token.str, "XWORD") == 0)
6847 new_token.code = T_TBYTE;
6848
6849 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6850 || strcasecmp (new_token.str, "OWORD") == 0)
6851 new_token.code = T_XMMWORD;
64a0c779
DN		 6852
6853 else if (strcasecmp (new_token.str, "PTR") == 0)
6854 new_token.code = T_PTR;
6855
6856 else if (strcasecmp (new_token.str, "SHORT") == 0)
6857 new_token.code = T_SHORT;
6858
6859 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6860 {
6861 new_token.code = T_OFFSET;
6862
6863 /* ??? This is not mentioned in the MASM grammar but gcc
6864 makes use of it with -mintel-syntax. OFFSET may be
6865 followed by FLAT: */
6866 if (strncasecmp (q, " FLAT:", 6) == 0)
6867 strcat (new_token.str, " FLAT:");
6868 }
6869
6870 /* ??? This is not mentioned in the MASM grammar. */
6871 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6872 {
6873 new_token.code = T_OFFSET;
6874 if (*q == ':')
6875 strcat (new_token.str, ":");
6876 else
6877 as_bad (_("`:' expected"));
6878 }
64a0c779
DN		 6879
6880 else
6881 new_token.code = T_ID;
6882 }
6883 }
6884
9306ca4a
JB		 6885 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6886 {
6887 new_token.code = *intel_parser.op_string;
6888 new_token.str[0] = *intel_parser.op_string;
6889 new_token.str[1] = '\0';
6890 }
6891
6892 else if (strchr ("<>", *intel_parser.op_string)
6893 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6894 {
6895 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6896 new_token.str[0] = *intel_parser.op_string;
6897 new_token.str[1] = *intel_parser.op_string;
6898 new_token.str[2] = '\0';
6899 }
6900
64a0c779 6901 else
0477af35 6902 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6903
6904 intel_parser.op_string += strlen (new_token.str);
6905 cur_token = new_token;
6906}
6907
64a0c779
DN		 6908/* Put cur_token back into the token stream and make cur_token point to
6909 prev_token. */
6910static void
6911intel_putback_token ()
6912{
a724f0f4
JB		 6913 if (cur_token.code != T_NIL)
6914 {
6915 intel_parser.op_string -= strlen (cur_token.str);
6916 free (cur_token.str);
6917 }
64a0c779 6918 cur_token = prev_token;
4a1805b1 6919
64a0c779
DN		 6920 /* Forget prev_token. */
6921 prev_token.code = T_NIL;
6922 prev_token.reg = NULL;
6923 prev_token.str = NULL;
6924}
54cfded0 6925
a4447b93 6926int
54cfded0
AM		 6927tc_x86_regname_to_dw2regnum (const char *regname)
6928{
6929 unsigned int regnum;
6930 unsigned int regnames_count;
089dfecd 6931 static const char *const regnames_32[] =
54cfded0 6932 {
a4447b93
RH		 6933 "eax", "ecx", "edx", "ebx",
6934 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6935 "eip", "eflags", NULL,
6936 "st0", "st1", "st2", "st3",
6937 "st4", "st5", "st6", "st7",
6938 NULL, NULL,
6939 "xmm0", "xmm1", "xmm2", "xmm3",
6940 "xmm4", "xmm5", "xmm6", "xmm7",
6941 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 6942 "mm4", "mm5", "mm6", "mm7",
6943 "fcw", "fsw", "mxcsr",
6944 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
6945 "tr", "ldtr"
54cfded0 6946 };
089dfecd 6947 static const char *const regnames_64[] =
54cfded0 6948 {
089dfecd
JB		 6949 "rax", "rdx", "rcx", "rbx",
6950 "rsi", "rdi", "rbp", "rsp",
6951 "r8", "r9", "r10", "r11",
54cfded0 6952 "r12", "r13", "r14", "r15",
089dfecd
JB		 6953 "rip",
6954 "xmm0", "xmm1", "xmm2", "xmm3",
6955 "xmm4", "xmm5", "xmm6", "xmm7",
6956 "xmm8", "xmm9", "xmm10", "xmm11",
6957 "xmm12", "xmm13", "xmm14", "xmm15",
6958 "st0", "st1", "st2", "st3",
6959 "st4", "st5", "st6", "st7",
6960 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 6961 "mm4", "mm5", "mm6", "mm7",
6962 "rflags",
6963 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
6964 "fs.base", "gs.base", NULL, NULL,
6965 "tr", "ldtr",
6966 "mxcsr", "fcw", "fsw"
54cfded0 6967 };
089dfecd 6968 const char *const *regnames;
54cfded0
AM		 6969
6970 if (flag_code == CODE_64BIT)
6971 {
6972 regnames = regnames_64;
0cea6190 6973 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6974 }
6975 else
6976 {
6977 regnames = regnames_32;
0cea6190 6978 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6979 }
6980
6981 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 6982 if (regnames[regnum] != NULL
6983 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 6984 return regnum;
6985
54cfded0
AM		 6986 return -1;
6987}
6988
6989void
6990tc_x86_frame_initial_instructions (void)
6991{
a4447b93
RH		 6992 static unsigned int sp_regno;
6993
6994 if (!sp_regno)
6995 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6996 ? "rsp" : "esp");
6997
6998 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6999 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7000}
d2b2c203
DJ		 7001
7002int
7003i386_elf_section_type (const char *str, size_t len)
7004{
7005 if (flag_code == CODE_64BIT
7006 && len == sizeof ("unwind") - 1
7007 && strncmp (str, "unwind", 6) == 0)
7008 return SHT_X86_64_UNWIND;
7009
7010 return -1;
7011}
bb41ade5
AM		 7012
7013#ifdef TE_PE
7014void
7015tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7016{
7017 expressionS expr;
7018
7019 expr.X_op = O_secrel;
7020 expr.X_add_symbol = symbol;
7021 expr.X_add_number = 0;
7022 emit_expr (&expr, size);
7023}
7024#endif
3b22753a
L		 7025
7026#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7027/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7028
7029int
7030x86_64_section_letter (int letter, char **ptr_msg)
7031{
7032 if (flag_code == CODE_64BIT)
7033 {
7034 if (letter == 'l')
7035 return SHF_X86_64_LARGE;
7036
7037 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7038 }
7039 else
7040 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7041 return -1;
7042}
7043
7044int
7045x86_64_section_word (char *str, size_t len)
7046{
7047 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7048 return SHF_X86_64_LARGE;
7049
7050 return -1;
7051}
7052
7053static void
7054handle_large_common (int small ATTRIBUTE_UNUSED)
7055{
7056 if (flag_code != CODE_64BIT)
7057 {
7058 s_comm_internal (0, elf_common_parse);
7059 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7060 }
7061 else
7062 {
7063 static segT lbss_section;
7064 asection *saved_com_section_ptr = elf_com_section_ptr;
7065 asection *saved_bss_section = bss_section;
7066
7067 if (lbss_section == NULL)
7068 {
7069 flagword applicable;
7070 segT seg = now_seg;
7071 subsegT subseg = now_subseg;
7072
7073 /* The .lbss section is for local .largecomm symbols. */
7074 lbss_section = subseg_new (".lbss", 0);
7075 applicable = bfd_applicable_section_flags (stdoutput);
7076 bfd_set_section_flags (stdoutput, lbss_section,
7077 applicable & SEC_ALLOC);
7078 seg_info (lbss_section)->bss = 1;
7079
7080 subseg_set (seg, subseg);
7081 }
7082
7083 elf_com_section_ptr = &_bfd_elf_large_com_section;
7084 bss_section = lbss_section;
7085
7086 s_comm_internal (0, elf_common_parse);
7087
7088 elf_com_section_ptr = saved_com_section_ptr;
7089 bss_section = saved_bss_section;
7090 }
7091}
7092#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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