Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
5dd15031 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
29b0f896 AM |
46 | #ifndef DEFAULT_ARCH |
47 | #define DEFAULT_ARCH "i386" | |
246fcdee | 48 | #endif |
252b5132 | 49 | |
edde18a5 AM |
50 | #ifndef INLINE |
51 | #if __GNUC__ >= 2 | |
52 | #define INLINE __inline__ | |
53 | #else | |
54 | #define INLINE | |
55 | #endif | |
56 | #endif | |
57 | ||
6305a203 L |
58 | /* Prefixes will be emitted in the order defined below. |
59 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
60 | instruction, and so must come before any prefixes. | |
61 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
62 | LOCKREP_PREFIX. */ | |
63 | #define WAIT_PREFIX 0 | |
64 | #define SEG_PREFIX 1 | |
65 | #define ADDR_PREFIX 2 | |
66 | #define DATA_PREFIX 3 | |
67 | #define LOCKREP_PREFIX 4 | |
68 | #define REX_PREFIX 5 /* must come last. */ | |
69 | #define MAX_PREFIXES 6 /* max prefixes per opcode */ | |
70 | ||
71 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
72 | #define REGISTER_PREFIX '%' | |
73 | #define IMMEDIATE_PREFIX '$' | |
74 | #define ABSOLUTE_PREFIX '*' | |
75 | ||
76 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
77 | memory operand size in Intel syntax. */ | |
78 | #define WORD_MNEM_SUFFIX 'w' | |
79 | #define BYTE_MNEM_SUFFIX 'b' | |
80 | #define SHORT_MNEM_SUFFIX 's' | |
81 | #define LONG_MNEM_SUFFIX 'l' | |
82 | #define QWORD_MNEM_SUFFIX 'q' | |
83 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 84 | #define YMMWORD_MNEM_SUFFIX 'y' |
6305a203 L |
85 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
86 | in instructions. */ | |
87 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
88 | ||
89 | #define END_OF_INSN '\0' | |
90 | ||
91 | /* | |
92 | 'templates' is for grouping together 'template' structures for opcodes | |
93 | of the same name. This is only used for storing the insns in the grand | |
94 | ole hash table of insns. | |
95 | The templates themselves start at START and range up to (but not including) | |
96 | END. | |
97 | */ | |
98 | typedef struct | |
99 | { | |
100 | const template *start; | |
101 | const template *end; | |
102 | } | |
103 | templates; | |
104 | ||
105 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
106 | typedef struct | |
107 | { | |
108 | unsigned int regmem; /* codes register or memory operand */ | |
109 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
110 | unsigned int mode; /* how to interpret regmem & reg */ | |
111 | } | |
112 | modrm_byte; | |
113 | ||
114 | /* x86-64 extension prefix. */ | |
115 | typedef int rex_byte; | |
116 | ||
117 | /* The SSE5 instructions have a two bit instruction modifier (OC) that | |
118 | is stored in two separate bytes in the instruction. Pick apart OC | |
119 | into the 2 separate bits for instruction. */ | |
120 | #define DREX_OC0(x) (((x) & 1) != 0) | |
121 | #define DREX_OC1(x) (((x) & 2) != 0) | |
122 | ||
123 | #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */ | |
124 | #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */ | |
125 | ||
126 | /* OC mappings */ | |
127 | #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */ | |
128 | #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */ | |
129 | #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */ | |
130 | #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */ | |
131 | ||
132 | #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */ | |
133 | #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */ | |
134 | ||
135 | /* Information needed to create the DREX byte in SSE5 instructions. */ | |
136 | typedef struct | |
137 | { | |
138 | unsigned int reg; /* register */ | |
139 | unsigned int rex; /* REX flags */ | |
140 | unsigned int modrm_reg; /* which arg goes in the modrm.reg field */ | |
141 | unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */ | |
142 | } drex_byte; | |
143 | ||
144 | /* 386 opcode byte to code indirect addressing. */ | |
145 | typedef struct | |
146 | { | |
147 | unsigned base; | |
148 | unsigned index; | |
149 | unsigned scale; | |
150 | } | |
151 | sib_byte; | |
152 | ||
153 | enum processor_type | |
154 | { | |
155 | PROCESSOR_UNKNOWN, | |
156 | PROCESSOR_I386, | |
157 | PROCESSOR_I486, | |
158 | PROCESSOR_PENTIUM, | |
159 | PROCESSOR_PENTIUMPRO, | |
160 | PROCESSOR_PENTIUM4, | |
161 | PROCESSOR_NOCONA, | |
162 | PROCESSOR_CORE, | |
163 | PROCESSOR_CORE2, | |
164 | PROCESSOR_K6, | |
165 | PROCESSOR_ATHLON, | |
166 | PROCESSOR_K8, | |
167 | PROCESSOR_GENERIC32, | |
168 | PROCESSOR_GENERIC64, | |
169 | PROCESSOR_AMDFAM10 | |
170 | }; | |
171 | ||
172 | /* x86 arch names, types and features */ | |
173 | typedef struct | |
174 | { | |
175 | const char *name; /* arch name */ | |
176 | enum processor_type type; /* arch type */ | |
177 | i386_cpu_flags flags; /* cpu feature flags */ | |
178 | } | |
179 | arch_entry; | |
180 | ||
e3bb37b5 L |
181 | static void set_code_flag (int); |
182 | static void set_16bit_gcc_code_flag (int); | |
183 | static void set_intel_syntax (int); | |
1efbbeb4 | 184 | static void set_intel_mnemonic (int); |
db51cc60 | 185 | static void set_allow_index_reg (int); |
cb19c032 | 186 | static void set_sse_check (int); |
e3bb37b5 | 187 | static void set_cpu_arch (int); |
6482c264 | 188 | #ifdef TE_PE |
e3bb37b5 | 189 | static void pe_directive_secrel (int); |
6482c264 | 190 | #endif |
e3bb37b5 L |
191 | static void signed_cons (int); |
192 | static char *output_invalid (int c); | |
a7619375 | 193 | static int i386_att_operand (char *); |
e3bb37b5 L |
194 | static int i386_intel_operand (char *, int); |
195 | static const reg_entry *parse_register (char *, char **); | |
196 | static char *parse_insn (char *, char *); | |
197 | static char *parse_operands (char *, const char *); | |
198 | static void swap_operands (void); | |
4d456e3d | 199 | static void swap_2_operands (int, int); |
e3bb37b5 L |
200 | static void optimize_imm (void); |
201 | static void optimize_disp (void); | |
202 | static int match_template (void); | |
203 | static int check_string (void); | |
204 | static int process_suffix (void); | |
205 | static int check_byte_reg (void); | |
206 | static int check_long_reg (void); | |
207 | static int check_qword_reg (void); | |
208 | static int check_word_reg (void); | |
209 | static int finalize_imm (void); | |
85f10a01 | 210 | static void process_drex (void); |
e3bb37b5 L |
211 | static int process_operands (void); |
212 | static const seg_entry *build_modrm_byte (void); | |
213 | static void output_insn (void); | |
214 | static void output_imm (fragS *, offsetT); | |
215 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 216 | #ifndef I386COFF |
e3bb37b5 | 217 | static void s_bss (int); |
252b5132 | 218 | #endif |
17d4e2a2 L |
219 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
220 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
221 | #endif | |
252b5132 | 222 | |
a847613f | 223 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 224 | |
c0f3af97 L |
225 | /* VEX prefix. */ |
226 | typedef struct | |
227 | { | |
228 | /* VEX prefix is either 2 byte or 3 byte. */ | |
229 | unsigned char bytes[3]; | |
230 | unsigned int length; | |
231 | /* Destination or source register specifier. */ | |
232 | const reg_entry *register_specifier; | |
233 | } vex_prefix; | |
234 | ||
252b5132 | 235 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 236 | i386_insn. */ |
252b5132 | 237 | |
520dc8e8 AM |
238 | union i386_op |
239 | { | |
240 | expressionS *disps; | |
241 | expressionS *imms; | |
242 | const reg_entry *regs; | |
243 | }; | |
244 | ||
252b5132 RH |
245 | struct _i386_insn |
246 | { | |
47926f60 | 247 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
248 | template tm; |
249 | ||
7d5e4556 L |
250 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
251 | or qword, if given. */ | |
252b5132 RH |
252 | char suffix; |
253 | ||
47926f60 | 254 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
255 | unsigned int operands; |
256 | ||
257 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
258 | of given register, displacement, memory operands and immediate | |
47926f60 | 259 | operands. */ |
252b5132 RH |
260 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
261 | ||
262 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 263 | use OP[i] for the corresponding operand. */ |
40fb9820 | 264 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 265 | |
520dc8e8 AM |
266 | /* Displacement expression, immediate expression, or register for each |
267 | operand. */ | |
268 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 269 | |
3e73aa7c JH |
270 | /* Flags for operands. */ |
271 | unsigned int flags[MAX_OPERANDS]; | |
272 | #define Operand_PCrel 1 | |
273 | ||
252b5132 | 274 | /* Relocation type for operand */ |
f86103b7 | 275 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 276 | |
252b5132 RH |
277 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
278 | the base index byte below. */ | |
279 | const reg_entry *base_reg; | |
280 | const reg_entry *index_reg; | |
281 | unsigned int log2_scale_factor; | |
282 | ||
283 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 284 | explicit segment overrides are given. */ |
ce8a8b2f | 285 | const seg_entry *seg[2]; |
252b5132 RH |
286 | |
287 | /* PREFIX holds all the given prefix opcodes (usually null). | |
288 | PREFIXES is the number of prefix opcodes. */ | |
289 | unsigned int prefixes; | |
290 | unsigned char prefix[MAX_PREFIXES]; | |
291 | ||
292 | /* RM and SIB are the modrm byte and the sib byte where the | |
85f10a01 MM |
293 | addressing modes of this insn are encoded. DREX is the byte |
294 | added by the SSE5 instructions. */ | |
252b5132 RH |
295 | |
296 | modrm_byte rm; | |
3e73aa7c | 297 | rex_byte rex; |
252b5132 | 298 | sib_byte sib; |
85f10a01 | 299 | drex_byte drex; |
c0f3af97 | 300 | vex_prefix vex; |
252b5132 RH |
301 | }; |
302 | ||
303 | typedef struct _i386_insn i386_insn; | |
304 | ||
305 | /* List of chars besides those in app.c:symbol_chars that can start an | |
306 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 307 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 308 | #ifdef LEX_AT |
32137342 NC |
309 | "@" |
310 | #endif | |
311 | #ifdef LEX_QM | |
312 | "?" | |
252b5132 | 313 | #endif |
32137342 | 314 | ; |
252b5132 | 315 | |
29b0f896 AM |
316 | #if (defined (TE_I386AIX) \ |
317 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 318 | && !defined (TE_GNU) \ |
29b0f896 | 319 | && !defined (TE_LINUX) \ |
32137342 | 320 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
321 | && !defined (TE_FreeBSD) \ |
322 | && !defined (TE_NetBSD))) | |
252b5132 | 323 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
324 | pre-processor is disabled, these aren't very useful. The option |
325 | --divide will remove '/' from this list. */ | |
326 | const char *i386_comment_chars = "#/"; | |
327 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 328 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 329 | |
b3b91714 AM |
330 | #else |
331 | const char *i386_comment_chars = "#"; | |
332 | #define PREFIX_SEPARATOR '/' | |
333 | #endif | |
334 | ||
252b5132 RH |
335 | /* This array holds the chars that only start a comment at the beginning of |
336 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
337 | .line and .file directives will appear in the pre-processed output. |
338 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 339 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
340 | #NO_APP at the beginning of its output. |
341 | Also note that comments started like this one will always work if | |
252b5132 | 342 | '/' isn't otherwise defined. */ |
b3b91714 | 343 | const char line_comment_chars[] = "#/"; |
252b5132 | 344 | |
63a0b638 | 345 | const char line_separator_chars[] = ";"; |
252b5132 | 346 | |
ce8a8b2f AM |
347 | /* Chars that can be used to separate mant from exp in floating point |
348 | nums. */ | |
252b5132 RH |
349 | const char EXP_CHARS[] = "eE"; |
350 | ||
ce8a8b2f AM |
351 | /* Chars that mean this number is a floating point constant |
352 | As in 0f12.456 | |
353 | or 0d1.2345e12. */ | |
252b5132 RH |
354 | const char FLT_CHARS[] = "fFdDxX"; |
355 | ||
ce8a8b2f | 356 | /* Tables for lexical analysis. */ |
252b5132 RH |
357 | static char mnemonic_chars[256]; |
358 | static char register_chars[256]; | |
359 | static char operand_chars[256]; | |
360 | static char identifier_chars[256]; | |
361 | static char digit_chars[256]; | |
362 | ||
ce8a8b2f | 363 | /* Lexical macros. */ |
252b5132 RH |
364 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
365 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
366 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
367 | #define is_space_char(x) ((x) == ' ') | |
368 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
369 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
370 | ||
0234cb7c | 371 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
372 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
373 | ||
374 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
375 | effect this we maintain a stack of saved characters that we've smashed | |
376 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 377 | assembler instruction). */ |
252b5132 | 378 | static char save_stack[32]; |
ce8a8b2f | 379 | static char *save_stack_p; |
252b5132 RH |
380 | #define END_STRING_AND_SAVE(s) \ |
381 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
382 | #define RESTORE_END_STRING(s) \ | |
383 | do { *(s) = *--save_stack_p; } while (0) | |
384 | ||
47926f60 | 385 | /* The instruction we're assembling. */ |
252b5132 RH |
386 | static i386_insn i; |
387 | ||
388 | /* Possible templates for current insn. */ | |
389 | static const templates *current_templates; | |
390 | ||
31b2323c L |
391 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
392 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
393 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 394 | |
47926f60 KH |
395 | /* Current operand we are working on. */ |
396 | static int this_operand; | |
252b5132 | 397 | |
3e73aa7c JH |
398 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
399 | these. */ | |
400 | ||
401 | enum flag_code { | |
402 | CODE_32BIT, | |
403 | CODE_16BIT, | |
404 | CODE_64BIT }; | |
405 | ||
406 | static enum flag_code flag_code; | |
4fa24527 | 407 | static unsigned int object_64bit; |
3e73aa7c JH |
408 | static int use_rela_relocations = 0; |
409 | ||
410 | /* The names used to print error messages. */ | |
b77a7acd | 411 | static const char *flag_code_names[] = |
3e73aa7c JH |
412 | { |
413 | "32", | |
414 | "16", | |
415 | "64" | |
416 | }; | |
252b5132 | 417 | |
47926f60 KH |
418 | /* 1 for intel syntax, |
419 | 0 if att syntax. */ | |
420 | static int intel_syntax = 0; | |
252b5132 | 421 | |
1efbbeb4 L |
422 | /* 1 for intel mnemonic, |
423 | 0 if att mnemonic. */ | |
424 | static int intel_mnemonic = !SYSV386_COMPAT; | |
425 | ||
5209009a | 426 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
427 | static int old_gcc = OLDGCC_COMPAT; |
428 | ||
a60de03c JB |
429 | /* 1 if pseudo registers are permitted. */ |
430 | static int allow_pseudo_reg = 0; | |
431 | ||
47926f60 KH |
432 | /* 1 if register prefix % not required. */ |
433 | static int allow_naked_reg = 0; | |
252b5132 | 434 | |
ba104c83 | 435 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
436 | static int allow_index_reg = 0; |
437 | ||
daf50ae7 L |
438 | static enum |
439 | { | |
440 | sse_check_none = 0, | |
441 | sse_check_warning, | |
442 | sse_check_error | |
443 | } | |
444 | sse_check; | |
445 | ||
2ca3ace5 L |
446 | /* Register prefix used for error message. */ |
447 | static const char *register_prefix = "%"; | |
448 | ||
47926f60 KH |
449 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
450 | leave, push, and pop instructions so that gcc has the same stack | |
451 | frame as in 32 bit mode. */ | |
452 | static char stackop_size = '\0'; | |
eecb386c | 453 | |
12b55ccc L |
454 | /* Non-zero to optimize code alignment. */ |
455 | int optimize_align_code = 1; | |
456 | ||
47926f60 KH |
457 | /* Non-zero to quieten some warnings. */ |
458 | static int quiet_warnings = 0; | |
a38cf1db | 459 | |
47926f60 KH |
460 | /* CPU name. */ |
461 | static const char *cpu_arch_name = NULL; | |
6305a203 | 462 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 463 | |
47926f60 | 464 | /* CPU feature flags. */ |
40fb9820 L |
465 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
466 | ||
ccc9c027 L |
467 | /* If we have selected a cpu we are generating instructions for. */ |
468 | static int cpu_arch_tune_set = 0; | |
469 | ||
9103f4f4 L |
470 | /* Cpu we are generating instructions for. */ |
471 | static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; | |
472 | ||
473 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 474 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 475 | |
ccc9c027 L |
476 | /* CPU instruction set architecture used. */ |
477 | static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; | |
478 | ||
9103f4f4 | 479 | /* CPU feature flags of instruction set architecture used. */ |
40fb9820 | 480 | static i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 481 | |
fddf5b5b AM |
482 | /* If set, conditional jumps are not automatically promoted to handle |
483 | larger than a byte offset. */ | |
484 | static unsigned int no_cond_jump_promotion = 0; | |
485 | ||
c0f3af97 L |
486 | /* Encode SSE instructions with VEX prefix. */ |
487 | static unsigned int sse2avx; | |
488 | ||
29b0f896 | 489 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 490 | static symbolS *GOT_symbol; |
29b0f896 | 491 | |
a4447b93 RH |
492 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
493 | unsigned int x86_dwarf2_return_column; | |
494 | ||
495 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
496 | int x86_cie_data_alignment; | |
497 | ||
252b5132 | 498 | /* Interface to relax_segment. |
fddf5b5b AM |
499 | There are 3 major relax states for 386 jump insns because the |
500 | different types of jumps add different sizes to frags when we're | |
501 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 502 | |
47926f60 | 503 | /* Types. */ |
93c2a809 AM |
504 | #define UNCOND_JUMP 0 |
505 | #define COND_JUMP 1 | |
506 | #define COND_JUMP86 2 | |
fddf5b5b | 507 | |
47926f60 | 508 | /* Sizes. */ |
252b5132 RH |
509 | #define CODE16 1 |
510 | #define SMALL 0 | |
29b0f896 | 511 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 512 | #define BIG 2 |
29b0f896 | 513 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
514 | |
515 | #ifndef INLINE | |
516 | #ifdef __GNUC__ | |
517 | #define INLINE __inline__ | |
518 | #else | |
519 | #define INLINE | |
520 | #endif | |
521 | #endif | |
522 | ||
fddf5b5b AM |
523 | #define ENCODE_RELAX_STATE(type, size) \ |
524 | ((relax_substateT) (((type) << 2) | (size))) | |
525 | #define TYPE_FROM_RELAX_STATE(s) \ | |
526 | ((s) >> 2) | |
527 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
528 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
529 | |
530 | /* This table is used by relax_frag to promote short jumps to long | |
531 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
532 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
533 | don't allow a short jump in a 32 bit code segment to be promoted to | |
534 | a 16 bit offset jump because it's slower (requires data size | |
535 | prefix), and doesn't work, unless the destination is in the bottom | |
536 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
537 | ||
538 | const relax_typeS md_relax_table[] = | |
539 | { | |
24eab124 AM |
540 | /* The fields are: |
541 | 1) most positive reach of this state, | |
542 | 2) most negative reach of this state, | |
93c2a809 | 543 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 544 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 545 | |
fddf5b5b | 546 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
547 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
548 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
549 | /* dword jmp adds 4 bytes to frag: | |
550 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 551 | {0, 0, 4, 0}, |
93c2a809 AM |
552 | /* word jmp adds 2 byte2 to frag: |
553 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
554 | {0, 0, 2, 0}, |
555 | ||
93c2a809 AM |
556 | /* COND_JUMP states. */ |
557 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
558 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
559 | /* dword conditionals adds 5 bytes to frag: | |
560 | 1 extra opcode byte, 4 displacement bytes. */ | |
561 | {0, 0, 5, 0}, | |
fddf5b5b | 562 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
563 | 1 extra opcode byte, 2 displacement bytes. */ |
564 | {0, 0, 3, 0}, | |
565 | ||
566 | /* COND_JUMP86 states. */ | |
567 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
568 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
569 | /* dword conditionals adds 5 bytes to frag: | |
570 | 1 extra opcode byte, 4 displacement bytes. */ | |
571 | {0, 0, 5, 0}, | |
572 | /* word conditionals add 4 bytes to frag: | |
573 | 1 displacement byte and a 3 byte long branch insn. */ | |
574 | {0, 0, 4, 0} | |
252b5132 RH |
575 | }; |
576 | ||
9103f4f4 L |
577 | static const arch_entry cpu_arch[] = |
578 | { | |
6305a203 L |
579 | { "generic32", PROCESSOR_GENERIC32, |
580 | CPU_GENERIC32_FLAGS }, | |
581 | { "generic64", PROCESSOR_GENERIC64, | |
582 | CPU_GENERIC64_FLAGS }, | |
583 | { "i8086", PROCESSOR_UNKNOWN, | |
584 | CPU_NONE_FLAGS }, | |
585 | { "i186", PROCESSOR_UNKNOWN, | |
586 | CPU_I186_FLAGS }, | |
587 | { "i286", PROCESSOR_UNKNOWN, | |
588 | CPU_I286_FLAGS }, | |
589 | { "i386", PROCESSOR_I386, | |
590 | CPU_I386_FLAGS }, | |
591 | { "i486", PROCESSOR_I486, | |
592 | CPU_I486_FLAGS }, | |
593 | { "i586", PROCESSOR_PENTIUM, | |
594 | CPU_I586_FLAGS }, | |
595 | { "i686", PROCESSOR_PENTIUMPRO, | |
596 | CPU_I686_FLAGS }, | |
597 | { "pentium", PROCESSOR_PENTIUM, | |
598 | CPU_I586_FLAGS }, | |
599 | { "pentiumpro", PROCESSOR_PENTIUMPRO, | |
600 | CPU_I686_FLAGS }, | |
601 | { "pentiumii", PROCESSOR_PENTIUMPRO, | |
602 | CPU_P2_FLAGS }, | |
603 | { "pentiumiii",PROCESSOR_PENTIUMPRO, | |
604 | CPU_P3_FLAGS }, | |
605 | { "pentium4", PROCESSOR_PENTIUM4, | |
606 | CPU_P4_FLAGS }, | |
607 | { "prescott", PROCESSOR_NOCONA, | |
608 | CPU_CORE_FLAGS }, | |
609 | { "nocona", PROCESSOR_NOCONA, | |
610 | CPU_NOCONA_FLAGS }, | |
611 | { "yonah", PROCESSOR_CORE, | |
612 | CPU_CORE_FLAGS }, | |
613 | { "core", PROCESSOR_CORE, | |
614 | CPU_CORE_FLAGS }, | |
615 | { "merom", PROCESSOR_CORE2, | |
616 | CPU_CORE2_FLAGS }, | |
617 | { "core2", PROCESSOR_CORE2, | |
618 | CPU_CORE2_FLAGS }, | |
619 | { "k6", PROCESSOR_K6, | |
620 | CPU_K6_FLAGS }, | |
621 | { "k6_2", PROCESSOR_K6, | |
622 | CPU_K6_2_FLAGS }, | |
623 | { "athlon", PROCESSOR_ATHLON, | |
624 | CPU_ATHLON_FLAGS }, | |
625 | { "sledgehammer", PROCESSOR_K8, | |
626 | CPU_K8_FLAGS }, | |
627 | { "opteron", PROCESSOR_K8, | |
628 | CPU_K8_FLAGS }, | |
629 | { "k8", PROCESSOR_K8, | |
630 | CPU_K8_FLAGS }, | |
631 | { "amdfam10", PROCESSOR_AMDFAM10, | |
632 | CPU_AMDFAM10_FLAGS }, | |
633 | { ".mmx", PROCESSOR_UNKNOWN, | |
634 | CPU_MMX_FLAGS }, | |
635 | { ".sse", PROCESSOR_UNKNOWN, | |
636 | CPU_SSE_FLAGS }, | |
637 | { ".sse2", PROCESSOR_UNKNOWN, | |
638 | CPU_SSE2_FLAGS }, | |
639 | { ".sse3", PROCESSOR_UNKNOWN, | |
640 | CPU_SSE3_FLAGS }, | |
641 | { ".ssse3", PROCESSOR_UNKNOWN, | |
642 | CPU_SSSE3_FLAGS }, | |
643 | { ".sse4.1", PROCESSOR_UNKNOWN, | |
644 | CPU_SSE4_1_FLAGS }, | |
645 | { ".sse4.2", PROCESSOR_UNKNOWN, | |
646 | CPU_SSE4_2_FLAGS }, | |
647 | { ".sse4", PROCESSOR_UNKNOWN, | |
648 | CPU_SSE4_2_FLAGS }, | |
c0f3af97 L |
649 | { ".avx", PROCESSOR_UNKNOWN, |
650 | CPU_AVX_FLAGS }, | |
6305a203 L |
651 | { ".vmx", PROCESSOR_UNKNOWN, |
652 | CPU_VMX_FLAGS }, | |
653 | { ".smx", PROCESSOR_UNKNOWN, | |
654 | CPU_SMX_FLAGS }, | |
f03fe4c1 L |
655 | { ".xsave", PROCESSOR_UNKNOWN, |
656 | CPU_XSAVE_FLAGS }, | |
c0f3af97 L |
657 | { ".aes", PROCESSOR_UNKNOWN, |
658 | CPU_AES_FLAGS }, | |
594ab6a3 L |
659 | { ".pclmul", PROCESSOR_UNKNOWN, |
660 | CPU_PCLMUL_FLAGS }, | |
c0f3af97 | 661 | { ".clmul", PROCESSOR_UNKNOWN, |
594ab6a3 | 662 | CPU_PCLMUL_FLAGS }, |
c0f3af97 L |
663 | { ".fma", PROCESSOR_UNKNOWN, |
664 | CPU_FMA_FLAGS }, | |
f1f8f695 L |
665 | { ".movbe", PROCESSOR_UNKNOWN, |
666 | CPU_MOVBE_FLAGS }, | |
667 | { ".ept", PROCESSOR_UNKNOWN, | |
668 | CPU_EPT_FLAGS }, | |
6305a203 L |
669 | { ".3dnow", PROCESSOR_UNKNOWN, |
670 | CPU_3DNOW_FLAGS }, | |
671 | { ".3dnowa", PROCESSOR_UNKNOWN, | |
672 | CPU_3DNOWA_FLAGS }, | |
673 | { ".padlock", PROCESSOR_UNKNOWN, | |
674 | CPU_PADLOCK_FLAGS }, | |
675 | { ".pacifica", PROCESSOR_UNKNOWN, | |
676 | CPU_SVME_FLAGS }, | |
677 | { ".svme", PROCESSOR_UNKNOWN, | |
678 | CPU_SVME_FLAGS }, | |
679 | { ".sse4a", PROCESSOR_UNKNOWN, | |
680 | CPU_SSE4A_FLAGS }, | |
681 | { ".abm", PROCESSOR_UNKNOWN, | |
682 | CPU_ABM_FLAGS }, | |
683 | { ".sse5", PROCESSOR_UNKNOWN, | |
684 | CPU_SSE5_FLAGS }, | |
e413e4e9 AM |
685 | }; |
686 | ||
704209c0 | 687 | #ifdef I386COFF |
a6c24e68 NC |
688 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
689 | is allowed to be optional. */ | |
690 | ||
691 | static symbolS * | |
692 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
693 | { | |
694 | addressT align = 0; | |
695 | ||
696 | SKIP_WHITESPACE (); | |
697 | ||
698 | if (needs_align | |
699 | && *input_line_pointer == ',') | |
700 | { | |
701 | align = parse_align (needs_align - 1); | |
702 | ||
703 | if (align == (addressT) -1) | |
704 | return NULL; | |
705 | } | |
706 | else | |
707 | { | |
708 | if (size >= 8) | |
709 | align = 3; | |
710 | else if (size >= 4) | |
711 | align = 2; | |
712 | else if (size >= 2) | |
713 | align = 1; | |
714 | else | |
715 | align = 0; | |
716 | } | |
717 | ||
718 | bss_alloc (symbolP, size, align); | |
719 | return symbolP; | |
720 | } | |
721 | ||
704209c0 | 722 | static void |
a6c24e68 NC |
723 | pe_lcomm (int needs_align) |
724 | { | |
725 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
726 | } | |
704209c0 | 727 | #endif |
a6c24e68 | 728 | |
29b0f896 AM |
729 | const pseudo_typeS md_pseudo_table[] = |
730 | { | |
731 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
732 | {"align", s_align_bytes, 0}, | |
733 | #else | |
734 | {"align", s_align_ptwo, 0}, | |
735 | #endif | |
736 | {"arch", set_cpu_arch, 0}, | |
737 | #ifndef I386COFF | |
738 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
739 | #else |
740 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
741 | #endif |
742 | {"ffloat", float_cons, 'f'}, | |
743 | {"dfloat", float_cons, 'd'}, | |
744 | {"tfloat", float_cons, 'x'}, | |
745 | {"value", cons, 2}, | |
d182319b | 746 | {"slong", signed_cons, 4}, |
29b0f896 AM |
747 | {"noopt", s_ignore, 0}, |
748 | {"optim", s_ignore, 0}, | |
749 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
750 | {"code16", set_code_flag, CODE_16BIT}, | |
751 | {"code32", set_code_flag, CODE_32BIT}, | |
752 | {"code64", set_code_flag, CODE_64BIT}, | |
753 | {"intel_syntax", set_intel_syntax, 1}, | |
754 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
755 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
756 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
757 | {"allow_index_reg", set_allow_index_reg, 1}, |
758 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
cb19c032 | 759 | {"sse_check", set_sse_check, 0}, |
3b22753a L |
760 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
761 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 762 | #else |
e3bb37b5 | 763 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
764 | {"loc", dwarf2_directive_loc, 0}, |
765 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 766 | #endif |
6482c264 NC |
767 | #ifdef TE_PE |
768 | {"secrel32", pe_directive_secrel, 0}, | |
769 | #endif | |
29b0f896 AM |
770 | {0, 0, 0} |
771 | }; | |
772 | ||
773 | /* For interface with expression (). */ | |
774 | extern char *input_line_pointer; | |
775 | ||
776 | /* Hash table for instruction mnemonic lookup. */ | |
777 | static struct hash_control *op_hash; | |
778 | ||
779 | /* Hash table for register lookup. */ | |
780 | static struct hash_control *reg_hash; | |
781 | \f | |
252b5132 | 782 | void |
e3bb37b5 | 783 | i386_align_code (fragS *fragP, int count) |
252b5132 | 784 | { |
ce8a8b2f AM |
785 | /* Various efficient no-op patterns for aligning code labels. |
786 | Note: Don't try to assemble the instructions in the comments. | |
787 | 0L and 0w are not legal. */ | |
252b5132 RH |
788 | static const char f32_1[] = |
789 | {0x90}; /* nop */ | |
790 | static const char f32_2[] = | |
ccc9c027 | 791 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
792 | static const char f32_3[] = |
793 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
794 | static const char f32_4[] = | |
795 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
796 | static const char f32_5[] = | |
797 | {0x90, /* nop */ | |
798 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
799 | static const char f32_6[] = | |
800 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
801 | static const char f32_7[] = | |
802 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
803 | static const char f32_8[] = | |
804 | {0x90, /* nop */ | |
805 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
806 | static const char f32_9[] = | |
807 | {0x89,0xf6, /* movl %esi,%esi */ | |
808 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
809 | static const char f32_10[] = | |
810 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
811 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
812 | static const char f32_11[] = | |
813 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
814 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
815 | static const char f32_12[] = | |
816 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
817 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
818 | static const char f32_13[] = | |
819 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
820 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
821 | static const char f32_14[] = | |
822 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
823 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
824 | static const char f16_3[] = |
825 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
826 | static const char f16_4[] = |
827 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
828 | static const char f16_5[] = | |
829 | {0x90, /* nop */ | |
830 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
831 | static const char f16_6[] = | |
832 | {0x89,0xf6, /* mov %si,%si */ | |
833 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
834 | static const char f16_7[] = | |
835 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
836 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
837 | static const char f16_8[] = | |
838 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
839 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
840 | static const char jump_31[] = |
841 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
842 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
843 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
844 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
845 | static const char *const f32_patt[] = { |
846 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 847 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
848 | }; |
849 | static const char *const f16_patt[] = { | |
76bc74dc | 850 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 851 | }; |
ccc9c027 L |
852 | /* nopl (%[re]ax) */ |
853 | static const char alt_3[] = | |
854 | {0x0f,0x1f,0x00}; | |
855 | /* nopl 0(%[re]ax) */ | |
856 | static const char alt_4[] = | |
857 | {0x0f,0x1f,0x40,0x00}; | |
858 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
859 | static const char alt_5[] = | |
860 | {0x0f,0x1f,0x44,0x00,0x00}; | |
861 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
862 | static const char alt_6[] = | |
863 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
864 | /* nopl 0L(%[re]ax) */ | |
865 | static const char alt_7[] = | |
866 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
867 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
868 | static const char alt_8[] = | |
869 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
870 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
871 | static const char alt_9[] = | |
872 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
873 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
874 | static const char alt_10[] = | |
875 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
876 | /* data16 | |
877 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
878 | static const char alt_long_11[] = | |
879 | {0x66, | |
880 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
881 | /* data16 | |
882 | data16 | |
883 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
884 | static const char alt_long_12[] = | |
885 | {0x66, | |
886 | 0x66, | |
887 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
888 | /* data16 | |
889 | data16 | |
890 | data16 | |
891 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
892 | static const char alt_long_13[] = | |
893 | {0x66, | |
894 | 0x66, | |
895 | 0x66, | |
896 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
897 | /* data16 | |
898 | data16 | |
899 | data16 | |
900 | data16 | |
901 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
902 | static const char alt_long_14[] = | |
903 | {0x66, | |
904 | 0x66, | |
905 | 0x66, | |
906 | 0x66, | |
907 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
908 | /* data16 | |
909 | data16 | |
910 | data16 | |
911 | data16 | |
912 | data16 | |
913 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
914 | static const char alt_long_15[] = | |
915 | {0x66, | |
916 | 0x66, | |
917 | 0x66, | |
918 | 0x66, | |
919 | 0x66, | |
920 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
921 | /* nopl 0(%[re]ax,%[re]ax,1) | |
922 | nopw 0(%[re]ax,%[re]ax,1) */ | |
923 | static const char alt_short_11[] = | |
924 | {0x0f,0x1f,0x44,0x00,0x00, | |
925 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
926 | /* nopw 0(%[re]ax,%[re]ax,1) | |
927 | nopw 0(%[re]ax,%[re]ax,1) */ | |
928 | static const char alt_short_12[] = | |
929 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
930 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
931 | /* nopw 0(%[re]ax,%[re]ax,1) | |
932 | nopl 0L(%[re]ax) */ | |
933 | static const char alt_short_13[] = | |
934 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
935 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
936 | /* nopl 0L(%[re]ax) | |
937 | nopl 0L(%[re]ax) */ | |
938 | static const char alt_short_14[] = | |
939 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
940 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
941 | /* nopl 0L(%[re]ax) | |
942 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
943 | static const char alt_short_15[] = | |
944 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
945 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
946 | static const char *const alt_short_patt[] = { | |
947 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
948 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
949 | alt_short_14, alt_short_15 | |
950 | }; | |
951 | static const char *const alt_long_patt[] = { | |
952 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
953 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
954 | alt_long_14, alt_long_15 | |
955 | }; | |
252b5132 | 956 | |
76bc74dc L |
957 | /* Only align for at least a positive non-zero boundary. */ |
958 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 959 | return; |
3e73aa7c | 960 | |
ccc9c027 L |
961 | /* We need to decide which NOP sequence to use for 32bit and |
962 | 64bit. When -mtune= is used: | |
4eed87de | 963 | |
76bc74dc L |
964 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
965 | PROCESSOR_GENERIC32, f32_patt will be used. | |
966 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
967 | PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64, | |
968 | alt_long_patt will be used. | |
969 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and | |
970 | PROCESSOR_AMDFAM10, alt_short_patt will be used. | |
ccc9c027 | 971 | |
76bc74dc L |
972 | When -mtune= isn't used, alt_long_patt will be used if |
973 | cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will | |
974 | be used. | |
ccc9c027 L |
975 | |
976 | When -march= or .arch is used, we can't use anything beyond | |
977 | cpu_arch_isa_flags. */ | |
978 | ||
979 | if (flag_code == CODE_16BIT) | |
980 | { | |
ccc9c027 | 981 | if (count > 8) |
33fef721 | 982 | { |
76bc74dc L |
983 | memcpy (fragP->fr_literal + fragP->fr_fix, |
984 | jump_31, count); | |
985 | /* Adjust jump offset. */ | |
986 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 987 | } |
76bc74dc L |
988 | else |
989 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
990 | f16_patt[count - 1], count); | |
252b5132 | 991 | } |
33fef721 | 992 | else |
ccc9c027 L |
993 | { |
994 | const char *const *patt = NULL; | |
995 | ||
996 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
997 | { | |
998 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
999 | switch (cpu_arch_tune) | |
1000 | { | |
1001 | case PROCESSOR_UNKNOWN: | |
1002 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
1003 | optimize for Cpu686. */ | |
40fb9820 | 1004 | if (cpu_arch_isa_flags.bitfield.cpui686) |
76bc74dc | 1005 | patt = alt_long_patt; |
ccc9c027 L |
1006 | else |
1007 | patt = f32_patt; | |
1008 | break; | |
ccc9c027 L |
1009 | case PROCESSOR_PENTIUMPRO: |
1010 | case PROCESSOR_PENTIUM4: | |
1011 | case PROCESSOR_NOCONA: | |
ef05d495 | 1012 | case PROCESSOR_CORE: |
76bc74dc L |
1013 | case PROCESSOR_CORE2: |
1014 | case PROCESSOR_GENERIC64: | |
1015 | patt = alt_long_patt; | |
1016 | break; | |
ccc9c027 L |
1017 | case PROCESSOR_K6: |
1018 | case PROCESSOR_ATHLON: | |
1019 | case PROCESSOR_K8: | |
4eed87de | 1020 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
1021 | patt = alt_short_patt; |
1022 | break; | |
76bc74dc | 1023 | case PROCESSOR_I386: |
ccc9c027 L |
1024 | case PROCESSOR_I486: |
1025 | case PROCESSOR_PENTIUM: | |
1026 | case PROCESSOR_GENERIC32: | |
1027 | patt = f32_patt; | |
1028 | break; | |
4eed87de | 1029 | } |
ccc9c027 L |
1030 | } |
1031 | else | |
1032 | { | |
1033 | switch (cpu_arch_tune) | |
1034 | { | |
1035 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1036 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1037 | PROCESSOR_UNKNOWN. */ |
1038 | abort (); | |
1039 | break; | |
1040 | ||
76bc74dc | 1041 | case PROCESSOR_I386: |
ccc9c027 L |
1042 | case PROCESSOR_I486: |
1043 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
1044 | case PROCESSOR_K6: |
1045 | case PROCESSOR_ATHLON: | |
1046 | case PROCESSOR_K8: | |
4eed87de | 1047 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
1048 | case PROCESSOR_GENERIC32: |
1049 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
1050 | for Cpu686. */ | |
40fb9820 | 1051 | if (cpu_arch_isa_flags.bitfield.cpui686) |
ccc9c027 L |
1052 | patt = alt_short_patt; |
1053 | else | |
1054 | patt = f32_patt; | |
1055 | break; | |
76bc74dc L |
1056 | case PROCESSOR_PENTIUMPRO: |
1057 | case PROCESSOR_PENTIUM4: | |
1058 | case PROCESSOR_NOCONA: | |
1059 | case PROCESSOR_CORE: | |
ef05d495 | 1060 | case PROCESSOR_CORE2: |
40fb9820 | 1061 | if (cpu_arch_isa_flags.bitfield.cpui686) |
ccc9c027 L |
1062 | patt = alt_long_patt; |
1063 | else | |
1064 | patt = f32_patt; | |
1065 | break; | |
1066 | case PROCESSOR_GENERIC64: | |
76bc74dc | 1067 | patt = alt_long_patt; |
ccc9c027 | 1068 | break; |
4eed87de | 1069 | } |
ccc9c027 L |
1070 | } |
1071 | ||
76bc74dc L |
1072 | if (patt == f32_patt) |
1073 | { | |
1074 | /* If the padding is less than 15 bytes, we use the normal | |
1075 | ones. Otherwise, we use a jump instruction and adjust | |
1076 | its offset. */ | |
1077 | if (count < 15) | |
1078 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1079 | patt[count - 1], count); | |
1080 | else | |
1081 | { | |
1082 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1083 | jump_31, count); | |
1084 | /* Adjust jump offset. */ | |
1085 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1086 | } | |
1087 | } | |
1088 | else | |
1089 | { | |
1090 | /* Maximum length of an instruction is 15 byte. If the | |
1091 | padding is greater than 15 bytes and we don't use jump, | |
1092 | we have to break it into smaller pieces. */ | |
1093 | int padding = count; | |
1094 | while (padding > 15) | |
1095 | { | |
1096 | padding -= 15; | |
1097 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
1098 | patt [14], 15); | |
1099 | } | |
1100 | ||
1101 | if (padding) | |
1102 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1103 | patt [padding - 1], padding); | |
1104 | } | |
ccc9c027 | 1105 | } |
33fef721 | 1106 | fragP->fr_var = count; |
252b5132 RH |
1107 | } |
1108 | ||
c6fb90c8 | 1109 | static INLINE int |
0dfbf9d7 | 1110 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1111 | { |
0dfbf9d7 | 1112 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1113 | { |
1114 | case 3: | |
0dfbf9d7 | 1115 | if (x->array[2]) |
c6fb90c8 L |
1116 | return 0; |
1117 | case 2: | |
0dfbf9d7 | 1118 | if (x->array[1]) |
c6fb90c8 L |
1119 | return 0; |
1120 | case 1: | |
0dfbf9d7 | 1121 | return !x->array[0]; |
c6fb90c8 L |
1122 | default: |
1123 | abort (); | |
1124 | } | |
40fb9820 L |
1125 | } |
1126 | ||
c6fb90c8 | 1127 | static INLINE void |
0dfbf9d7 | 1128 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1129 | { |
0dfbf9d7 | 1130 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1131 | { |
1132 | case 3: | |
0dfbf9d7 | 1133 | x->array[2] = v; |
c6fb90c8 | 1134 | case 2: |
0dfbf9d7 | 1135 | x->array[1] = v; |
c6fb90c8 | 1136 | case 1: |
0dfbf9d7 | 1137 | x->array[0] = v; |
c6fb90c8 L |
1138 | break; |
1139 | default: | |
1140 | abort (); | |
1141 | } | |
1142 | } | |
40fb9820 | 1143 | |
c6fb90c8 | 1144 | static INLINE int |
0dfbf9d7 L |
1145 | operand_type_equal (const union i386_operand_type *x, |
1146 | const union i386_operand_type *y) | |
c6fb90c8 | 1147 | { |
0dfbf9d7 | 1148 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1149 | { |
1150 | case 3: | |
0dfbf9d7 | 1151 | if (x->array[2] != y->array[2]) |
c6fb90c8 L |
1152 | return 0; |
1153 | case 2: | |
0dfbf9d7 | 1154 | if (x->array[1] != y->array[1]) |
c6fb90c8 L |
1155 | return 0; |
1156 | case 1: | |
0dfbf9d7 | 1157 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1158 | break; |
1159 | default: | |
1160 | abort (); | |
1161 | } | |
1162 | } | |
40fb9820 | 1163 | |
0dfbf9d7 L |
1164 | static INLINE int |
1165 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1166 | { | |
1167 | switch (ARRAY_SIZE(x->array)) | |
1168 | { | |
1169 | case 3: | |
1170 | if (x->array[2]) | |
1171 | return 0; | |
1172 | case 2: | |
1173 | if (x->array[1]) | |
1174 | return 0; | |
1175 | case 1: | |
1176 | return !x->array[0]; | |
1177 | default: | |
1178 | abort (); | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | static INLINE void | |
1183 | cpu_flags_set (union i386_cpu_flags *x, unsigned int v) | |
1184 | { | |
1185 | switch (ARRAY_SIZE(x->array)) | |
1186 | { | |
1187 | case 3: | |
1188 | x->array[2] = v; | |
1189 | case 2: | |
1190 | x->array[1] = v; | |
1191 | case 1: | |
1192 | x->array[0] = v; | |
1193 | break; | |
1194 | default: | |
1195 | abort (); | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | static INLINE int | |
1200 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1201 | const union i386_cpu_flags *y) | |
1202 | { | |
1203 | switch (ARRAY_SIZE(x->array)) | |
1204 | { | |
1205 | case 3: | |
1206 | if (x->array[2] != y->array[2]) | |
1207 | return 0; | |
1208 | case 2: | |
1209 | if (x->array[1] != y->array[1]) | |
1210 | return 0; | |
1211 | case 1: | |
1212 | return x->array[0] == y->array[0]; | |
1213 | break; | |
1214 | default: | |
1215 | abort (); | |
1216 | } | |
1217 | } | |
c6fb90c8 L |
1218 | |
1219 | static INLINE int | |
1220 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1221 | { | |
1222 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1223 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1224 | } |
1225 | ||
c6fb90c8 L |
1226 | static INLINE i386_cpu_flags |
1227 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1228 | { |
c6fb90c8 L |
1229 | switch (ARRAY_SIZE (x.array)) |
1230 | { | |
1231 | case 3: | |
1232 | x.array [2] &= y.array [2]; | |
1233 | case 2: | |
1234 | x.array [1] &= y.array [1]; | |
1235 | case 1: | |
1236 | x.array [0] &= y.array [0]; | |
1237 | break; | |
1238 | default: | |
1239 | abort (); | |
1240 | } | |
1241 | return x; | |
1242 | } | |
40fb9820 | 1243 | |
c6fb90c8 L |
1244 | static INLINE i386_cpu_flags |
1245 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1246 | { |
c6fb90c8 | 1247 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1248 | { |
c6fb90c8 L |
1249 | case 3: |
1250 | x.array [2] |= y.array [2]; | |
1251 | case 2: | |
1252 | x.array [1] |= y.array [1]; | |
1253 | case 1: | |
1254 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1255 | break; |
1256 | default: | |
1257 | abort (); | |
1258 | } | |
40fb9820 L |
1259 | return x; |
1260 | } | |
1261 | ||
c0f3af97 L |
1262 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1263 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 L |
1264 | #define CPU_FLAGS_AES_MATCH 0x4 |
1265 | #define CPU_FLAGS_AVX_MATCH 0x8 | |
c0f3af97 | 1266 | |
a5ff0eb2 L |
1267 | #define CPU_FLAGS_32BIT_MATCH \ |
1268 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1269 | #define CPU_FLAGS_PERFECT_MATCH \ |
1270 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1271 | ||
1272 | /* Return CPU flags match bits. */ | |
3629bb00 | 1273 | |
40fb9820 | 1274 | static int |
c0f3af97 | 1275 | cpu_flags_match (const template *t) |
40fb9820 | 1276 | { |
c0f3af97 L |
1277 | i386_cpu_flags x = t->cpu_flags; |
1278 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1279 | |
1280 | x.bitfield.cpu64 = 0; | |
1281 | x.bitfield.cpuno64 = 0; | |
1282 | ||
0dfbf9d7 | 1283 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1284 | { |
1285 | /* This instruction is available on all archs. */ | |
1286 | match |= CPU_FLAGS_32BIT_MATCH; | |
1287 | } | |
3629bb00 L |
1288 | else |
1289 | { | |
c0f3af97 | 1290 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1291 | i386_cpu_flags cpu = cpu_arch_flags; |
1292 | ||
1293 | cpu.bitfield.cpu64 = 0; | |
1294 | cpu.bitfield.cpuno64 = 0; | |
1295 | cpu = cpu_flags_and (x, cpu); | |
c0f3af97 L |
1296 | if (!cpu_flags_all_zero (&cpu)) |
1297 | { | |
a5ff0eb2 L |
1298 | if (x.bitfield.cpuavx) |
1299 | { | |
1300 | /* We only need to check AES/SSE2AVX with AVX. */ | |
1301 | if (cpu.bitfield.cpuavx) | |
1302 | { | |
1303 | /* Check SSE2AVX. */ | |
1304 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1305 | { | |
1306 | match |= (CPU_FLAGS_ARCH_MATCH | |
1307 | | CPU_FLAGS_AVX_MATCH); | |
1308 | /* Check AES. */ | |
1309 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1310 | match |= CPU_FLAGS_AES_MATCH; | |
1311 | } | |
1312 | } | |
1313 | else | |
1314 | match |= CPU_FLAGS_ARCH_MATCH; | |
1315 | } | |
1316 | else | |
c0f3af97 L |
1317 | match |= CPU_FLAGS_32BIT_MATCH; |
1318 | } | |
3629bb00 | 1319 | } |
c0f3af97 | 1320 | return match; |
40fb9820 L |
1321 | } |
1322 | ||
c6fb90c8 L |
1323 | static INLINE i386_operand_type |
1324 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1325 | { |
c6fb90c8 L |
1326 | switch (ARRAY_SIZE (x.array)) |
1327 | { | |
1328 | case 3: | |
1329 | x.array [2] &= y.array [2]; | |
1330 | case 2: | |
1331 | x.array [1] &= y.array [1]; | |
1332 | case 1: | |
1333 | x.array [0] &= y.array [0]; | |
1334 | break; | |
1335 | default: | |
1336 | abort (); | |
1337 | } | |
1338 | return x; | |
40fb9820 L |
1339 | } |
1340 | ||
c6fb90c8 L |
1341 | static INLINE i386_operand_type |
1342 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1343 | { |
c6fb90c8 | 1344 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1345 | { |
c6fb90c8 L |
1346 | case 3: |
1347 | x.array [2] |= y.array [2]; | |
1348 | case 2: | |
1349 | x.array [1] |= y.array [1]; | |
1350 | case 1: | |
1351 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1352 | break; |
1353 | default: | |
1354 | abort (); | |
1355 | } | |
c6fb90c8 L |
1356 | return x; |
1357 | } | |
40fb9820 | 1358 | |
c6fb90c8 L |
1359 | static INLINE i386_operand_type |
1360 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1361 | { | |
1362 | switch (ARRAY_SIZE (x.array)) | |
1363 | { | |
1364 | case 3: | |
1365 | x.array [2] ^= y.array [2]; | |
1366 | case 2: | |
1367 | x.array [1] ^= y.array [1]; | |
1368 | case 1: | |
1369 | x.array [0] ^= y.array [0]; | |
1370 | break; | |
1371 | default: | |
1372 | abort (); | |
1373 | } | |
40fb9820 L |
1374 | return x; |
1375 | } | |
1376 | ||
1377 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1378 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1379 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1380 | static const i386_operand_type inoutportreg |
1381 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1382 | static const i386_operand_type reg16_inoutportreg |
1383 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1384 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1385 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1386 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1387 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1388 | static const i386_operand_type anydisp | |
1389 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1390 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1391 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
40fb9820 L |
1392 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1393 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1394 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1395 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1396 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1397 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1398 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1399 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1400 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
c0f3af97 | 1401 | static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4; |
40fb9820 L |
1402 | |
1403 | enum operand_type | |
1404 | { | |
1405 | reg, | |
40fb9820 L |
1406 | imm, |
1407 | disp, | |
1408 | anymem | |
1409 | }; | |
1410 | ||
c6fb90c8 | 1411 | static INLINE int |
40fb9820 L |
1412 | operand_type_check (i386_operand_type t, enum operand_type c) |
1413 | { | |
1414 | switch (c) | |
1415 | { | |
1416 | case reg: | |
1417 | return (t.bitfield.reg8 | |
1418 | || t.bitfield.reg16 | |
1419 | || t.bitfield.reg32 | |
1420 | || t.bitfield.reg64); | |
1421 | ||
40fb9820 L |
1422 | case imm: |
1423 | return (t.bitfield.imm8 | |
1424 | || t.bitfield.imm8s | |
1425 | || t.bitfield.imm16 | |
1426 | || t.bitfield.imm32 | |
1427 | || t.bitfield.imm32s | |
1428 | || t.bitfield.imm64); | |
1429 | ||
1430 | case disp: | |
1431 | return (t.bitfield.disp8 | |
1432 | || t.bitfield.disp16 | |
1433 | || t.bitfield.disp32 | |
1434 | || t.bitfield.disp32s | |
1435 | || t.bitfield.disp64); | |
1436 | ||
1437 | case anymem: | |
1438 | return (t.bitfield.disp8 | |
1439 | || t.bitfield.disp16 | |
1440 | || t.bitfield.disp32 | |
1441 | || t.bitfield.disp32s | |
1442 | || t.bitfield.disp64 | |
1443 | || t.bitfield.baseindex); | |
1444 | ||
1445 | default: | |
1446 | abort (); | |
1447 | } | |
2cfe26b6 AM |
1448 | |
1449 | return 0; | |
40fb9820 L |
1450 | } |
1451 | ||
5c07affc L |
1452 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1453 | operand J for instruction template T. */ | |
1454 | ||
1455 | static INLINE int | |
1456 | match_reg_size (const template *t, unsigned int j) | |
1457 | { | |
1458 | return !((i.types[j].bitfield.byte | |
1459 | && !t->operand_types[j].bitfield.byte) | |
1460 | || (i.types[j].bitfield.word | |
1461 | && !t->operand_types[j].bitfield.word) | |
1462 | || (i.types[j].bitfield.dword | |
1463 | && !t->operand_types[j].bitfield.dword) | |
1464 | || (i.types[j].bitfield.qword | |
1465 | && !t->operand_types[j].bitfield.qword)); | |
1466 | } | |
1467 | ||
1468 | /* Return 1 if there is no conflict in any size on operand J for | |
1469 | instruction template T. */ | |
1470 | ||
1471 | static INLINE int | |
1472 | match_mem_size (const template *t, unsigned int j) | |
1473 | { | |
1474 | return (match_reg_size (t, j) | |
1475 | && !((i.types[j].bitfield.unspecified | |
1476 | && !t->operand_types[j].bitfield.unspecified) | |
1477 | || (i.types[j].bitfield.fword | |
1478 | && !t->operand_types[j].bitfield.fword) | |
1479 | || (i.types[j].bitfield.tbyte | |
1480 | && !t->operand_types[j].bitfield.tbyte) | |
1481 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1482 | && !t->operand_types[j].bitfield.xmmword) |
1483 | || (i.types[j].bitfield.ymmword | |
1484 | && !t->operand_types[j].bitfield.ymmword))); | |
5c07affc L |
1485 | } |
1486 | ||
1487 | /* Return 1 if there is no size conflict on any operands for | |
1488 | instruction template T. */ | |
1489 | ||
1490 | static INLINE int | |
1491 | operand_size_match (const template *t) | |
1492 | { | |
1493 | unsigned int j; | |
1494 | int match = 1; | |
1495 | ||
1496 | /* Don't check jump instructions. */ | |
1497 | if (t->opcode_modifier.jump | |
1498 | || t->opcode_modifier.jumpbyte | |
1499 | || t->opcode_modifier.jumpdword | |
1500 | || t->opcode_modifier.jumpintersegment) | |
1501 | return match; | |
1502 | ||
1503 | /* Check memory and accumulator operand size. */ | |
1504 | for (j = 0; j < i.operands; j++) | |
1505 | { | |
1506 | if (t->operand_types[j].bitfield.anysize) | |
1507 | continue; | |
1508 | ||
1509 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1510 | { | |
1511 | match = 0; | |
1512 | break; | |
1513 | } | |
1514 | ||
1515 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1516 | { | |
1517 | match = 0; | |
1518 | break; | |
1519 | } | |
1520 | } | |
1521 | ||
1522 | if (match | |
1523 | || (!t->opcode_modifier.d && !t->opcode_modifier.floatd)) | |
1524 | return match; | |
1525 | ||
1526 | /* Check reverse. */ | |
1527 | assert (i.operands == 2); | |
1528 | ||
1529 | match = 1; | |
1530 | for (j = 0; j < 2; j++) | |
1531 | { | |
1532 | if (t->operand_types[j].bitfield.acc | |
1533 | && !match_reg_size (t, j ? 0 : 1)) | |
1534 | { | |
1535 | match = 0; | |
1536 | break; | |
1537 | } | |
1538 | ||
1539 | if (i.types[j].bitfield.mem | |
1540 | && !match_mem_size (t, j ? 0 : 1)) | |
1541 | { | |
1542 | match = 0; | |
1543 | break; | |
1544 | } | |
1545 | } | |
1546 | ||
1547 | return match; | |
1548 | } | |
1549 | ||
c6fb90c8 | 1550 | static INLINE int |
40fb9820 L |
1551 | operand_type_match (i386_operand_type overlap, |
1552 | i386_operand_type given) | |
1553 | { | |
1554 | i386_operand_type temp = overlap; | |
1555 | ||
1556 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1557 | temp.bitfield.unspecified = 0; |
5c07affc L |
1558 | temp.bitfield.byte = 0; |
1559 | temp.bitfield.word = 0; | |
1560 | temp.bitfield.dword = 0; | |
1561 | temp.bitfield.fword = 0; | |
1562 | temp.bitfield.qword = 0; | |
1563 | temp.bitfield.tbyte = 0; | |
1564 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1565 | temp.bitfield.ymmword = 0; |
0dfbf9d7 | 1566 | if (operand_type_all_zero (&temp)) |
40fb9820 L |
1567 | return 0; |
1568 | ||
1569 | return (given.bitfield.baseindex == overlap.bitfield.baseindex | |
1570 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute); | |
1571 | } | |
1572 | ||
7d5e4556 | 1573 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1574 | unless the expected operand type register overlap is null. |
1575 | Note that Acc in a template matches every size of reg. */ | |
1576 | ||
c6fb90c8 | 1577 | static INLINE int |
40fb9820 L |
1578 | operand_type_register_match (i386_operand_type m0, |
1579 | i386_operand_type g0, | |
1580 | i386_operand_type t0, | |
1581 | i386_operand_type m1, | |
1582 | i386_operand_type g1, | |
1583 | i386_operand_type t1) | |
1584 | { | |
1585 | if (!operand_type_check (g0, reg)) | |
1586 | return 1; | |
1587 | ||
1588 | if (!operand_type_check (g1, reg)) | |
1589 | return 1; | |
1590 | ||
1591 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1592 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1593 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1594 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1595 | return 1; | |
1596 | ||
1597 | if (m0.bitfield.acc) | |
1598 | { | |
1599 | t0.bitfield.reg8 = 1; | |
1600 | t0.bitfield.reg16 = 1; | |
1601 | t0.bitfield.reg32 = 1; | |
1602 | t0.bitfield.reg64 = 1; | |
1603 | } | |
1604 | ||
1605 | if (m1.bitfield.acc) | |
1606 | { | |
1607 | t1.bitfield.reg8 = 1; | |
1608 | t1.bitfield.reg16 = 1; | |
1609 | t1.bitfield.reg32 = 1; | |
1610 | t1.bitfield.reg64 = 1; | |
1611 | } | |
1612 | ||
1613 | return (!(t0.bitfield.reg8 & t1.bitfield.reg8) | |
1614 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1615 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1616 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)); | |
1617 | } | |
1618 | ||
252b5132 | 1619 | static INLINE unsigned int |
40fb9820 | 1620 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1621 | { |
40fb9820 L |
1622 | if (t.bitfield.disp8) |
1623 | return 1; | |
1624 | else if (t.bitfield.disp16 | |
1625 | || t.bitfield.disp32 | |
1626 | || t.bitfield.disp32s) | |
1627 | return 2; | |
1628 | else | |
1629 | return 0; | |
252b5132 RH |
1630 | } |
1631 | ||
1632 | static INLINE int | |
e3bb37b5 | 1633 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1634 | { |
1635 | return (num >= -128) && (num <= 127); | |
47926f60 | 1636 | } |
252b5132 RH |
1637 | |
1638 | static INLINE int | |
e3bb37b5 | 1639 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1640 | { |
1641 | return (num & 0xff) == num; | |
47926f60 | 1642 | } |
252b5132 RH |
1643 | |
1644 | static INLINE int | |
e3bb37b5 | 1645 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1646 | { |
1647 | return (num & 0xffff) == num; | |
47926f60 | 1648 | } |
252b5132 RH |
1649 | |
1650 | static INLINE int | |
e3bb37b5 | 1651 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1652 | { |
1653 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1654 | } |
2a962e6d | 1655 | |
3e73aa7c | 1656 | static INLINE int |
e3bb37b5 | 1657 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1658 | { |
1659 | #ifndef BFD64 | |
1660 | return 1; | |
1661 | #else | |
1662 | return (!(((offsetT) -1 << 31) & num) | |
1663 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1664 | #endif | |
1665 | } /* fits_in_signed_long() */ | |
2a962e6d | 1666 | |
3e73aa7c | 1667 | static INLINE int |
e3bb37b5 | 1668 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1669 | { |
1670 | #ifndef BFD64 | |
1671 | return 1; | |
1672 | #else | |
1673 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1674 | #endif | |
1675 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1676 | |
c0f3af97 L |
1677 | static INLINE int |
1678 | fits_in_imm4 (offsetT num) | |
1679 | { | |
1680 | return (num & 0xf) == num; | |
1681 | } | |
1682 | ||
40fb9820 | 1683 | static i386_operand_type |
e3bb37b5 | 1684 | smallest_imm_type (offsetT num) |
252b5132 | 1685 | { |
40fb9820 L |
1686 | i386_operand_type t; |
1687 | ||
0dfbf9d7 | 1688 | operand_type_set (&t, 0); |
40fb9820 L |
1689 | t.bitfield.imm64 = 1; |
1690 | ||
1691 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1692 | { |
1693 | /* This code is disabled on the 486 because all the Imm1 forms | |
1694 | in the opcode table are slower on the i486. They're the | |
1695 | versions with the implicitly specified single-position | |
1696 | displacement, which has another syntax if you really want to | |
1697 | use that form. */ | |
40fb9820 L |
1698 | t.bitfield.imm1 = 1; |
1699 | t.bitfield.imm8 = 1; | |
1700 | t.bitfield.imm8s = 1; | |
1701 | t.bitfield.imm16 = 1; | |
1702 | t.bitfield.imm32 = 1; | |
1703 | t.bitfield.imm32s = 1; | |
1704 | } | |
1705 | else if (fits_in_signed_byte (num)) | |
1706 | { | |
1707 | t.bitfield.imm8 = 1; | |
1708 | t.bitfield.imm8s = 1; | |
1709 | t.bitfield.imm16 = 1; | |
1710 | t.bitfield.imm32 = 1; | |
1711 | t.bitfield.imm32s = 1; | |
1712 | } | |
1713 | else if (fits_in_unsigned_byte (num)) | |
1714 | { | |
1715 | t.bitfield.imm8 = 1; | |
1716 | t.bitfield.imm16 = 1; | |
1717 | t.bitfield.imm32 = 1; | |
1718 | t.bitfield.imm32s = 1; | |
1719 | } | |
1720 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1721 | { | |
1722 | t.bitfield.imm16 = 1; | |
1723 | t.bitfield.imm32 = 1; | |
1724 | t.bitfield.imm32s = 1; | |
1725 | } | |
1726 | else if (fits_in_signed_long (num)) | |
1727 | { | |
1728 | t.bitfield.imm32 = 1; | |
1729 | t.bitfield.imm32s = 1; | |
1730 | } | |
1731 | else if (fits_in_unsigned_long (num)) | |
1732 | t.bitfield.imm32 = 1; | |
1733 | ||
1734 | return t; | |
47926f60 | 1735 | } |
252b5132 | 1736 | |
847f7ad4 | 1737 | static offsetT |
e3bb37b5 | 1738 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1739 | { |
508866be | 1740 | addressT mask; |
ba2adb93 | 1741 | |
847f7ad4 AM |
1742 | switch (size) |
1743 | { | |
508866be L |
1744 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1745 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1746 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1747 | #ifdef BFD64 |
1748 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1749 | #endif | |
47926f60 | 1750 | default: abort (); |
847f7ad4 AM |
1751 | } |
1752 | ||
ba2adb93 | 1753 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
1754 | if (!use_rela_relocations) |
1755 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
1756 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 1757 | |
47926f60 | 1758 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1759 | { |
1760 | char buf1[40], buf2[40]; | |
1761 | ||
1762 | sprint_value (buf1, val); | |
1763 | sprint_value (buf2, val & mask); | |
1764 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1765 | } | |
1766 | return val & mask; | |
1767 | } | |
1768 | ||
252b5132 RH |
1769 | /* Returns 0 if attempting to add a prefix where one from the same |
1770 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
1771 | added. */ | |
1772 | static int | |
e3bb37b5 | 1773 | add_prefix (unsigned int prefix) |
252b5132 RH |
1774 | { |
1775 | int ret = 1; | |
b1905489 | 1776 | unsigned int q; |
252b5132 | 1777 | |
29b0f896 AM |
1778 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1779 | && flag_code == CODE_64BIT) | |
b1905489 | 1780 | { |
161a04f6 L |
1781 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1782 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1783 | && (prefix & (REX_R | REX_X | REX_B)))) | |
b1905489 JB |
1784 | ret = 0; |
1785 | q = REX_PREFIX; | |
1786 | } | |
3e73aa7c | 1787 | else |
b1905489 JB |
1788 | { |
1789 | switch (prefix) | |
1790 | { | |
1791 | default: | |
1792 | abort (); | |
1793 | ||
1794 | case CS_PREFIX_OPCODE: | |
1795 | case DS_PREFIX_OPCODE: | |
1796 | case ES_PREFIX_OPCODE: | |
1797 | case FS_PREFIX_OPCODE: | |
1798 | case GS_PREFIX_OPCODE: | |
1799 | case SS_PREFIX_OPCODE: | |
1800 | q = SEG_PREFIX; | |
1801 | break; | |
1802 | ||
1803 | case REPNE_PREFIX_OPCODE: | |
1804 | case REPE_PREFIX_OPCODE: | |
1805 | ret = 2; | |
1806 | /* fall thru */ | |
1807 | case LOCK_PREFIX_OPCODE: | |
1808 | q = LOCKREP_PREFIX; | |
1809 | break; | |
1810 | ||
1811 | case FWAIT_OPCODE: | |
1812 | q = WAIT_PREFIX; | |
1813 | break; | |
1814 | ||
1815 | case ADDR_PREFIX_OPCODE: | |
1816 | q = ADDR_PREFIX; | |
1817 | break; | |
1818 | ||
1819 | case DATA_PREFIX_OPCODE: | |
1820 | q = DATA_PREFIX; | |
1821 | break; | |
1822 | } | |
1823 | if (i.prefix[q] != 0) | |
1824 | ret = 0; | |
1825 | } | |
252b5132 | 1826 | |
b1905489 | 1827 | if (ret) |
252b5132 | 1828 | { |
b1905489 JB |
1829 | if (!i.prefix[q]) |
1830 | ++i.prefixes; | |
1831 | i.prefix[q] |= prefix; | |
252b5132 | 1832 | } |
b1905489 JB |
1833 | else |
1834 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 1835 | |
252b5132 RH |
1836 | return ret; |
1837 | } | |
1838 | ||
1839 | static void | |
e3bb37b5 | 1840 | set_code_flag (int value) |
eecb386c | 1841 | { |
3e73aa7c | 1842 | flag_code = value; |
40fb9820 L |
1843 | if (flag_code == CODE_64BIT) |
1844 | { | |
1845 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1846 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
1847 | } |
1848 | else | |
1849 | { | |
1850 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1851 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
1852 | } |
1853 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c JH |
1854 | { |
1855 | as_bad (_("64bit mode not supported on this CPU.")); | |
1856 | } | |
40fb9820 | 1857 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c JH |
1858 | { |
1859 | as_bad (_("32bit mode not supported on this CPU.")); | |
1860 | } | |
eecb386c AM |
1861 | stackop_size = '\0'; |
1862 | } | |
1863 | ||
1864 | static void | |
e3bb37b5 | 1865 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 1866 | { |
3e73aa7c | 1867 | flag_code = new_code_flag; |
40fb9820 L |
1868 | if (flag_code != CODE_16BIT) |
1869 | abort (); | |
1870 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1871 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 1872 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
1873 | } |
1874 | ||
1875 | static void | |
e3bb37b5 | 1876 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
1877 | { |
1878 | /* Find out if register prefixing is specified. */ | |
1879 | int ask_naked_reg = 0; | |
1880 | ||
1881 | SKIP_WHITESPACE (); | |
29b0f896 | 1882 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
1883 | { |
1884 | char *string = input_line_pointer; | |
1885 | int e = get_symbol_end (); | |
1886 | ||
47926f60 | 1887 | if (strcmp (string, "prefix") == 0) |
252b5132 | 1888 | ask_naked_reg = 1; |
47926f60 | 1889 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
1890 | ask_naked_reg = -1; |
1891 | else | |
d0b47220 | 1892 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
1893 | *input_line_pointer = e; |
1894 | } | |
1895 | demand_empty_rest_of_line (); | |
c3332e24 | 1896 | |
252b5132 RH |
1897 | intel_syntax = syntax_flag; |
1898 | ||
1899 | if (ask_naked_reg == 0) | |
f86103b7 AM |
1900 | allow_naked_reg = (intel_syntax |
1901 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
1902 | else |
1903 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 1904 | |
e4a3b5a4 | 1905 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 1906 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 1907 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
1908 | } |
1909 | ||
1efbbeb4 L |
1910 | static void |
1911 | set_intel_mnemonic (int mnemonic_flag) | |
1912 | { | |
e1d4d893 | 1913 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
1914 | } |
1915 | ||
db51cc60 L |
1916 | static void |
1917 | set_allow_index_reg (int flag) | |
1918 | { | |
1919 | allow_index_reg = flag; | |
1920 | } | |
1921 | ||
cb19c032 L |
1922 | static void |
1923 | set_sse_check (int dummy ATTRIBUTE_UNUSED) | |
1924 | { | |
1925 | SKIP_WHITESPACE (); | |
1926 | ||
1927 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
1928 | { | |
1929 | char *string = input_line_pointer; | |
1930 | int e = get_symbol_end (); | |
1931 | ||
1932 | if (strcmp (string, "none") == 0) | |
1933 | sse_check = sse_check_none; | |
1934 | else if (strcmp (string, "warning") == 0) | |
1935 | sse_check = sse_check_warning; | |
1936 | else if (strcmp (string, "error") == 0) | |
1937 | sse_check = sse_check_error; | |
1938 | else | |
1939 | as_bad (_("bad argument to sse_check directive.")); | |
1940 | *input_line_pointer = e; | |
1941 | } | |
1942 | else | |
1943 | as_bad (_("missing argument for sse_check directive")); | |
1944 | ||
1945 | demand_empty_rest_of_line (); | |
1946 | } | |
1947 | ||
e413e4e9 | 1948 | static void |
e3bb37b5 | 1949 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 1950 | { |
47926f60 | 1951 | SKIP_WHITESPACE (); |
e413e4e9 | 1952 | |
29b0f896 | 1953 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
1954 | { |
1955 | char *string = input_line_pointer; | |
1956 | int e = get_symbol_end (); | |
9103f4f4 | 1957 | unsigned int i; |
40fb9820 | 1958 | i386_cpu_flags flags; |
e413e4e9 | 1959 | |
9103f4f4 | 1960 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) |
e413e4e9 AM |
1961 | { |
1962 | if (strcmp (string, cpu_arch[i].name) == 0) | |
1963 | { | |
5c6af06e JB |
1964 | if (*string != '.') |
1965 | { | |
1966 | cpu_arch_name = cpu_arch[i].name; | |
1967 | cpu_sub_arch_name = NULL; | |
40fb9820 L |
1968 | cpu_arch_flags = cpu_arch[i].flags; |
1969 | if (flag_code == CODE_64BIT) | |
1970 | { | |
1971 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1972 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
1973 | } | |
1974 | else | |
1975 | { | |
1976 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1977 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
1978 | } | |
ccc9c027 | 1979 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 1980 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
1981 | if (!cpu_arch_tune_set) |
1982 | { | |
1983 | cpu_arch_tune = cpu_arch_isa; | |
1984 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
1985 | } | |
5c6af06e JB |
1986 | break; |
1987 | } | |
40fb9820 | 1988 | |
c6fb90c8 L |
1989 | flags = cpu_flags_or (cpu_arch_flags, |
1990 | cpu_arch[i].flags); | |
0dfbf9d7 | 1991 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 1992 | { |
6305a203 L |
1993 | if (cpu_sub_arch_name) |
1994 | { | |
1995 | char *name = cpu_sub_arch_name; | |
1996 | cpu_sub_arch_name = concat (name, | |
1997 | cpu_arch[i].name, | |
1bf57e9f | 1998 | (const char *) NULL); |
6305a203 L |
1999 | free (name); |
2000 | } | |
2001 | else | |
2002 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
40fb9820 | 2003 | cpu_arch_flags = flags; |
5c6af06e JB |
2004 | } |
2005 | *input_line_pointer = e; | |
2006 | demand_empty_rest_of_line (); | |
2007 | return; | |
e413e4e9 AM |
2008 | } |
2009 | } | |
9103f4f4 | 2010 | if (i >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2011 | as_bad (_("no such architecture: `%s'"), string); |
2012 | ||
2013 | *input_line_pointer = e; | |
2014 | } | |
2015 | else | |
2016 | as_bad (_("missing cpu architecture")); | |
2017 | ||
fddf5b5b AM |
2018 | no_cond_jump_promotion = 0; |
2019 | if (*input_line_pointer == ',' | |
29b0f896 | 2020 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
2021 | { |
2022 | char *string = ++input_line_pointer; | |
2023 | int e = get_symbol_end (); | |
2024 | ||
2025 | if (strcmp (string, "nojumps") == 0) | |
2026 | no_cond_jump_promotion = 1; | |
2027 | else if (strcmp (string, "jumps") == 0) | |
2028 | ; | |
2029 | else | |
2030 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2031 | ||
2032 | *input_line_pointer = e; | |
2033 | } | |
2034 | ||
e413e4e9 AM |
2035 | demand_empty_rest_of_line (); |
2036 | } | |
2037 | ||
b9d79e03 JH |
2038 | unsigned long |
2039 | i386_mach () | |
2040 | { | |
2041 | if (!strcmp (default_arch, "x86_64")) | |
2042 | return bfd_mach_x86_64; | |
2043 | else if (!strcmp (default_arch, "i386")) | |
2044 | return bfd_mach_i386_i386; | |
2045 | else | |
2046 | as_fatal (_("Unknown architecture")); | |
2047 | } | |
b9d79e03 | 2048 | \f |
252b5132 RH |
2049 | void |
2050 | md_begin () | |
2051 | { | |
2052 | const char *hash_err; | |
2053 | ||
47926f60 | 2054 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2055 | op_hash = hash_new (); |
2056 | ||
2057 | { | |
29b0f896 AM |
2058 | const template *optab; |
2059 | templates *core_optab; | |
252b5132 | 2060 | |
47926f60 KH |
2061 | /* Setup for loop. */ |
2062 | optab = i386_optab; | |
252b5132 RH |
2063 | core_optab = (templates *) xmalloc (sizeof (templates)); |
2064 | core_optab->start = optab; | |
2065 | ||
2066 | while (1) | |
2067 | { | |
2068 | ++optab; | |
2069 | if (optab->name == NULL | |
2070 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2071 | { | |
2072 | /* different name --> ship out current template list; | |
47926f60 | 2073 | add to hash table; & begin anew. */ |
252b5132 RH |
2074 | core_optab->end = optab; |
2075 | hash_err = hash_insert (op_hash, | |
2076 | (optab - 1)->name, | |
5a49b8ac | 2077 | (void *) core_optab); |
252b5132 RH |
2078 | if (hash_err) |
2079 | { | |
252b5132 RH |
2080 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2081 | (optab - 1)->name, | |
2082 | hash_err); | |
2083 | } | |
2084 | if (optab->name == NULL) | |
2085 | break; | |
2086 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
2087 | core_optab->start = optab; | |
2088 | } | |
2089 | } | |
2090 | } | |
2091 | ||
47926f60 | 2092 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2093 | reg_hash = hash_new (); |
2094 | { | |
29b0f896 | 2095 | const reg_entry *regtab; |
c3fe08fa | 2096 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2097 | |
c3fe08fa | 2098 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2099 | { |
5a49b8ac | 2100 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2101 | if (hash_err) |
3e73aa7c JH |
2102 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2103 | regtab->reg_name, | |
2104 | hash_err); | |
252b5132 RH |
2105 | } |
2106 | } | |
2107 | ||
47926f60 | 2108 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2109 | { |
29b0f896 AM |
2110 | int c; |
2111 | char *p; | |
252b5132 RH |
2112 | |
2113 | for (c = 0; c < 256; c++) | |
2114 | { | |
3882b010 | 2115 | if (ISDIGIT (c)) |
252b5132 RH |
2116 | { |
2117 | digit_chars[c] = c; | |
2118 | mnemonic_chars[c] = c; | |
2119 | register_chars[c] = c; | |
2120 | operand_chars[c] = c; | |
2121 | } | |
3882b010 | 2122 | else if (ISLOWER (c)) |
252b5132 RH |
2123 | { |
2124 | mnemonic_chars[c] = c; | |
2125 | register_chars[c] = c; | |
2126 | operand_chars[c] = c; | |
2127 | } | |
3882b010 | 2128 | else if (ISUPPER (c)) |
252b5132 | 2129 | { |
3882b010 | 2130 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2131 | register_chars[c] = mnemonic_chars[c]; |
2132 | operand_chars[c] = c; | |
2133 | } | |
2134 | ||
3882b010 | 2135 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2136 | identifier_chars[c] = c; |
2137 | else if (c >= 128) | |
2138 | { | |
2139 | identifier_chars[c] = c; | |
2140 | operand_chars[c] = c; | |
2141 | } | |
2142 | } | |
2143 | ||
2144 | #ifdef LEX_AT | |
2145 | identifier_chars['@'] = '@'; | |
32137342 NC |
2146 | #endif |
2147 | #ifdef LEX_QM | |
2148 | identifier_chars['?'] = '?'; | |
2149 | operand_chars['?'] = '?'; | |
252b5132 | 2150 | #endif |
252b5132 | 2151 | digit_chars['-'] = '-'; |
c0f3af97 | 2152 | mnemonic_chars['_'] = '_'; |
791fe849 | 2153 | mnemonic_chars['-'] = '-'; |
0003779b | 2154 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2155 | identifier_chars['_'] = '_'; |
2156 | identifier_chars['.'] = '.'; | |
2157 | ||
2158 | for (p = operand_special_chars; *p != '\0'; p++) | |
2159 | operand_chars[(unsigned char) *p] = *p; | |
2160 | } | |
2161 | ||
2162 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 2163 | if (IS_ELF) |
252b5132 RH |
2164 | { |
2165 | record_alignment (text_section, 2); | |
2166 | record_alignment (data_section, 2); | |
2167 | record_alignment (bss_section, 2); | |
2168 | } | |
2169 | #endif | |
a4447b93 RH |
2170 | |
2171 | if (flag_code == CODE_64BIT) | |
2172 | { | |
2173 | x86_dwarf2_return_column = 16; | |
2174 | x86_cie_data_alignment = -8; | |
2175 | } | |
2176 | else | |
2177 | { | |
2178 | x86_dwarf2_return_column = 8; | |
2179 | x86_cie_data_alignment = -4; | |
2180 | } | |
252b5132 RH |
2181 | } |
2182 | ||
2183 | void | |
e3bb37b5 | 2184 | i386_print_statistics (FILE *file) |
252b5132 RH |
2185 | { |
2186 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2187 | hash_print_statistics (file, "i386 register", reg_hash); | |
2188 | } | |
2189 | \f | |
252b5132 RH |
2190 | #ifdef DEBUG386 |
2191 | ||
ce8a8b2f | 2192 | /* Debugging routines for md_assemble. */ |
e3bb37b5 | 2193 | static void pte (template *); |
40fb9820 | 2194 | static void pt (i386_operand_type); |
e3bb37b5 L |
2195 | static void pe (expressionS *); |
2196 | static void ps (symbolS *); | |
252b5132 RH |
2197 | |
2198 | static void | |
e3bb37b5 | 2199 | pi (char *line, i386_insn *x) |
252b5132 | 2200 | { |
09f131f2 | 2201 | unsigned int i; |
252b5132 RH |
2202 | |
2203 | fprintf (stdout, "%s: template ", line); | |
2204 | pte (&x->tm); | |
09f131f2 JH |
2205 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2206 | x->base_reg ? x->base_reg->reg_name : "none", | |
2207 | x->index_reg ? x->index_reg->reg_name : "none", | |
2208 | x->log2_scale_factor); | |
2209 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2210 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2211 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2212 | x->sib.base, x->sib.index, x->sib.scale); | |
2213 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2214 | (x->rex & REX_W) != 0, |
2215 | (x->rex & REX_R) != 0, | |
2216 | (x->rex & REX_X) != 0, | |
2217 | (x->rex & REX_B) != 0); | |
85f10a01 MM |
2218 | fprintf (stdout, " drex: reg %d rex 0x%x\n", |
2219 | x->drex.reg, x->drex.rex); | |
252b5132 RH |
2220 | for (i = 0; i < x->operands; i++) |
2221 | { | |
2222 | fprintf (stdout, " #%d: ", i + 1); | |
2223 | pt (x->types[i]); | |
2224 | fprintf (stdout, "\n"); | |
40fb9820 L |
2225 | if (x->types[i].bitfield.reg8 |
2226 | || x->types[i].bitfield.reg16 | |
2227 | || x->types[i].bitfield.reg32 | |
2228 | || x->types[i].bitfield.reg64 | |
2229 | || x->types[i].bitfield.regmmx | |
2230 | || x->types[i].bitfield.regxmm | |
c0f3af97 | 2231 | || x->types[i].bitfield.regymm |
40fb9820 L |
2232 | || x->types[i].bitfield.sreg2 |
2233 | || x->types[i].bitfield.sreg3 | |
2234 | || x->types[i].bitfield.control | |
2235 | || x->types[i].bitfield.debug | |
2236 | || x->types[i].bitfield.test) | |
520dc8e8 | 2237 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
40fb9820 | 2238 | if (operand_type_check (x->types[i], imm)) |
520dc8e8 | 2239 | pe (x->op[i].imms); |
40fb9820 | 2240 | if (operand_type_check (x->types[i], disp)) |
520dc8e8 | 2241 | pe (x->op[i].disps); |
252b5132 RH |
2242 | } |
2243 | } | |
2244 | ||
2245 | static void | |
e3bb37b5 | 2246 | pte (template *t) |
252b5132 | 2247 | { |
09f131f2 | 2248 | unsigned int i; |
252b5132 | 2249 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2250 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2251 | if (t->extension_opcode != None) |
2252 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2253 | if (t->opcode_modifier.d) |
252b5132 | 2254 | fprintf (stdout, "D"); |
40fb9820 | 2255 | if (t->opcode_modifier.w) |
252b5132 RH |
2256 | fprintf (stdout, "W"); |
2257 | fprintf (stdout, "\n"); | |
2258 | for (i = 0; i < t->operands; i++) | |
2259 | { | |
2260 | fprintf (stdout, " #%d type ", i + 1); | |
2261 | pt (t->operand_types[i]); | |
2262 | fprintf (stdout, "\n"); | |
2263 | } | |
2264 | } | |
2265 | ||
2266 | static void | |
e3bb37b5 | 2267 | pe (expressionS *e) |
252b5132 | 2268 | { |
24eab124 | 2269 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2270 | fprintf (stdout, " add_number %ld (%lx)\n", |
2271 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2272 | if (e->X_add_symbol) |
2273 | { | |
2274 | fprintf (stdout, " add_symbol "); | |
2275 | ps (e->X_add_symbol); | |
2276 | fprintf (stdout, "\n"); | |
2277 | } | |
2278 | if (e->X_op_symbol) | |
2279 | { | |
2280 | fprintf (stdout, " op_symbol "); | |
2281 | ps (e->X_op_symbol); | |
2282 | fprintf (stdout, "\n"); | |
2283 | } | |
2284 | } | |
2285 | ||
2286 | static void | |
e3bb37b5 | 2287 | ps (symbolS *s) |
252b5132 RH |
2288 | { |
2289 | fprintf (stdout, "%s type %s%s", | |
2290 | S_GET_NAME (s), | |
2291 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2292 | segment_name (S_GET_SEGMENT (s))); | |
2293 | } | |
2294 | ||
7b81dfbb | 2295 | static struct type_name |
252b5132 | 2296 | { |
40fb9820 L |
2297 | i386_operand_type mask; |
2298 | const char *name; | |
252b5132 | 2299 | } |
7b81dfbb | 2300 | const type_names[] = |
252b5132 | 2301 | { |
40fb9820 L |
2302 | { OPERAND_TYPE_REG8, "r8" }, |
2303 | { OPERAND_TYPE_REG16, "r16" }, | |
2304 | { OPERAND_TYPE_REG32, "r32" }, | |
2305 | { OPERAND_TYPE_REG64, "r64" }, | |
2306 | { OPERAND_TYPE_IMM8, "i8" }, | |
2307 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2308 | { OPERAND_TYPE_IMM16, "i16" }, | |
2309 | { OPERAND_TYPE_IMM32, "i32" }, | |
2310 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2311 | { OPERAND_TYPE_IMM64, "i64" }, | |
2312 | { OPERAND_TYPE_IMM1, "i1" }, | |
2313 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2314 | { OPERAND_TYPE_DISP8, "d8" }, | |
2315 | { OPERAND_TYPE_DISP16, "d16" }, | |
2316 | { OPERAND_TYPE_DISP32, "d32" }, | |
2317 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2318 | { OPERAND_TYPE_DISP64, "d64" }, | |
2319 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2320 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2321 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2322 | { OPERAND_TYPE_TEST, "test reg" }, | |
2323 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2324 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2325 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2326 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2327 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2328 | { OPERAND_TYPE_ACC, "Acc" }, | |
2329 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2330 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2331 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
2332 | { OPERAND_TYPE_ESSEG, "es" }, | |
c0f3af97 | 2333 | { OPERAND_TYPE_VEX_IMM4, "VEX i4" }, |
252b5132 RH |
2334 | }; |
2335 | ||
2336 | static void | |
40fb9820 | 2337 | pt (i386_operand_type t) |
252b5132 | 2338 | { |
40fb9820 | 2339 | unsigned int j; |
c6fb90c8 | 2340 | i386_operand_type a; |
252b5132 | 2341 | |
40fb9820 | 2342 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2343 | { |
2344 | a = operand_type_and (t, type_names[j].mask); | |
2345 | if (!UINTS_ALL_ZERO (a)) | |
2346 | fprintf (stdout, "%s, ", type_names[j].name); | |
2347 | } | |
252b5132 RH |
2348 | fflush (stdout); |
2349 | } | |
2350 | ||
2351 | #endif /* DEBUG386 */ | |
2352 | \f | |
252b5132 | 2353 | static bfd_reloc_code_real_type |
3956db08 | 2354 | reloc (unsigned int size, |
64e74474 AM |
2355 | int pcrel, |
2356 | int sign, | |
2357 | bfd_reloc_code_real_type other) | |
252b5132 | 2358 | { |
47926f60 | 2359 | if (other != NO_RELOC) |
3956db08 JB |
2360 | { |
2361 | reloc_howto_type *reloc; | |
2362 | ||
2363 | if (size == 8) | |
2364 | switch (other) | |
2365 | { | |
64e74474 AM |
2366 | case BFD_RELOC_X86_64_GOT32: |
2367 | return BFD_RELOC_X86_64_GOT64; | |
2368 | break; | |
2369 | case BFD_RELOC_X86_64_PLTOFF64: | |
2370 | return BFD_RELOC_X86_64_PLTOFF64; | |
2371 | break; | |
2372 | case BFD_RELOC_X86_64_GOTPC32: | |
2373 | other = BFD_RELOC_X86_64_GOTPC64; | |
2374 | break; | |
2375 | case BFD_RELOC_X86_64_GOTPCREL: | |
2376 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2377 | break; | |
2378 | case BFD_RELOC_X86_64_TPOFF32: | |
2379 | other = BFD_RELOC_X86_64_TPOFF64; | |
2380 | break; | |
2381 | case BFD_RELOC_X86_64_DTPOFF32: | |
2382 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2383 | break; | |
2384 | default: | |
2385 | break; | |
3956db08 | 2386 | } |
e05278af JB |
2387 | |
2388 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
2389 | if (size == 4 && flag_code != CODE_64BIT) | |
2390 | sign = -1; | |
2391 | ||
3956db08 JB |
2392 | reloc = bfd_reloc_type_lookup (stdoutput, other); |
2393 | if (!reloc) | |
2394 | as_bad (_("unknown relocation (%u)"), other); | |
2395 | else if (size != bfd_get_reloc_size (reloc)) | |
2396 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), | |
2397 | bfd_get_reloc_size (reloc), | |
2398 | size); | |
2399 | else if (pcrel && !reloc->pc_relative) | |
2400 | as_bad (_("non-pc-relative relocation for pc-relative field")); | |
2401 | else if ((reloc->complain_on_overflow == complain_overflow_signed | |
2402 | && !sign) | |
2403 | || (reloc->complain_on_overflow == complain_overflow_unsigned | |
64e74474 | 2404 | && sign > 0)) |
3956db08 JB |
2405 | as_bad (_("relocated field and relocation type differ in signedness")); |
2406 | else | |
2407 | return other; | |
2408 | return NO_RELOC; | |
2409 | } | |
252b5132 RH |
2410 | |
2411 | if (pcrel) | |
2412 | { | |
3e73aa7c | 2413 | if (!sign) |
3956db08 | 2414 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2415 | switch (size) |
2416 | { | |
2417 | case 1: return BFD_RELOC_8_PCREL; | |
2418 | case 2: return BFD_RELOC_16_PCREL; | |
2419 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2420 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2421 | } |
3956db08 | 2422 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2423 | } |
2424 | else | |
2425 | { | |
3956db08 | 2426 | if (sign > 0) |
e5cb08ac | 2427 | switch (size) |
3e73aa7c JH |
2428 | { |
2429 | case 4: return BFD_RELOC_X86_64_32S; | |
2430 | } | |
2431 | else | |
2432 | switch (size) | |
2433 | { | |
2434 | case 1: return BFD_RELOC_8; | |
2435 | case 2: return BFD_RELOC_16; | |
2436 | case 4: return BFD_RELOC_32; | |
2437 | case 8: return BFD_RELOC_64; | |
2438 | } | |
3956db08 JB |
2439 | as_bad (_("cannot do %s %u byte relocation"), |
2440 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2441 | } |
2442 | ||
bfb32b52 | 2443 | abort (); |
252b5132 RH |
2444 | return BFD_RELOC_NONE; |
2445 | } | |
2446 | ||
47926f60 KH |
2447 | /* Here we decide which fixups can be adjusted to make them relative to |
2448 | the beginning of the section instead of the symbol. Basically we need | |
2449 | to make sure that the dynamic relocations are done correctly, so in | |
2450 | some cases we force the original symbol to be used. */ | |
2451 | ||
252b5132 | 2452 | int |
e3bb37b5 | 2453 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2454 | { |
6d249963 | 2455 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2456 | if (!IS_ELF) |
31312f95 AM |
2457 | return 1; |
2458 | ||
a161fe53 AM |
2459 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2460 | mode. */ | |
2461 | if (use_rela_relocations | |
2462 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2463 | && fixP->fx_pcrel) | |
252b5132 | 2464 | return 0; |
31312f95 | 2465 | |
8d01d9a9 AJ |
2466 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2467 | and changed later by validate_fix. */ | |
2468 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2469 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2470 | return 0; | |
2471 | ||
ce8a8b2f | 2472 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2473 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2474 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2475 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2476 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2477 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2478 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2479 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2480 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2481 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2482 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2483 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2484 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2485 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2486 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2487 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2488 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2489 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2490 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2491 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2492 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2493 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2494 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2495 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2496 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2497 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2498 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2499 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2500 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2501 | return 0; | |
31312f95 | 2502 | #endif |
252b5132 RH |
2503 | return 1; |
2504 | } | |
252b5132 | 2505 | |
b4cac588 | 2506 | static int |
e3bb37b5 | 2507 | intel_float_operand (const char *mnemonic) |
252b5132 | 2508 | { |
9306ca4a JB |
2509 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2510 | operands, hence the code here is free to improperly handle opcodes that | |
2511 | have no operands (for better performance and smaller code). */ | |
2512 | ||
2513 | if (mnemonic[0] != 'f') | |
2514 | return 0; /* non-math */ | |
2515 | ||
2516 | switch (mnemonic[1]) | |
2517 | { | |
2518 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2519 | the fs segment override prefix not currently handled because no | |
2520 | call path can make opcodes without operands get here */ | |
2521 | case 'i': | |
2522 | return 2 /* integer op */; | |
2523 | case 'l': | |
2524 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2525 | return 3; /* fldcw/fldenv */ | |
2526 | break; | |
2527 | case 'n': | |
2528 | if (mnemonic[2] != 'o' /* fnop */) | |
2529 | return 3; /* non-waiting control op */ | |
2530 | break; | |
2531 | case 'r': | |
2532 | if (mnemonic[2] == 's') | |
2533 | return 3; /* frstor/frstpm */ | |
2534 | break; | |
2535 | case 's': | |
2536 | if (mnemonic[2] == 'a') | |
2537 | return 3; /* fsave */ | |
2538 | if (mnemonic[2] == 't') | |
2539 | { | |
2540 | switch (mnemonic[3]) | |
2541 | { | |
2542 | case 'c': /* fstcw */ | |
2543 | case 'd': /* fstdw */ | |
2544 | case 'e': /* fstenv */ | |
2545 | case 's': /* fsts[gw] */ | |
2546 | return 3; | |
2547 | } | |
2548 | } | |
2549 | break; | |
2550 | case 'x': | |
2551 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2552 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2553 | break; | |
2554 | } | |
252b5132 | 2555 | |
9306ca4a | 2556 | return 1; |
252b5132 RH |
2557 | } |
2558 | ||
c0f3af97 L |
2559 | /* Build the VEX prefix. */ |
2560 | ||
2561 | static void | |
2562 | build_vex_prefix (void) | |
2563 | { | |
2564 | unsigned int register_specifier; | |
2565 | unsigned int implied_prefix; | |
2566 | unsigned int vector_length; | |
2567 | ||
2568 | /* Check register specifier. */ | |
2569 | if (i.vex.register_specifier) | |
2570 | { | |
2571 | register_specifier = i.vex.register_specifier->reg_num; | |
2572 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
2573 | register_specifier += 8; | |
2574 | register_specifier = ~register_specifier & 0xf; | |
2575 | } | |
2576 | else | |
2577 | register_specifier = 0xf; | |
2578 | ||
2579 | vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0; | |
2580 | ||
2581 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
2582 | { | |
2583 | case 0: | |
2584 | implied_prefix = 0; | |
2585 | break; | |
2586 | case DATA_PREFIX_OPCODE: | |
2587 | implied_prefix = 1; | |
2588 | break; | |
2589 | case REPE_PREFIX_OPCODE: | |
2590 | implied_prefix = 2; | |
2591 | break; | |
2592 | case REPNE_PREFIX_OPCODE: | |
2593 | implied_prefix = 3; | |
2594 | break; | |
2595 | default: | |
2596 | abort (); | |
2597 | } | |
2598 | ||
2599 | /* Use 2-byte VEX prefix if possible. */ | |
2600 | if (i.tm.opcode_modifier.vex0f | |
2601 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) | |
2602 | { | |
2603 | /* 2-byte VEX prefix. */ | |
2604 | unsigned int r; | |
2605 | ||
2606 | i.vex.length = 2; | |
2607 | i.vex.bytes[0] = 0xc5; | |
2608 | ||
2609 | /* Check the REX.R bit. */ | |
2610 | r = (i.rex & REX_R) ? 0 : 1; | |
2611 | i.vex.bytes[1] = (r << 7 | |
2612 | | register_specifier << 3 | |
2613 | | vector_length << 2 | |
2614 | | implied_prefix); | |
2615 | } | |
2616 | else | |
2617 | { | |
2618 | /* 3-byte VEX prefix. */ | |
2619 | unsigned int m, w; | |
2620 | ||
2621 | if (i.tm.opcode_modifier.vex0f) | |
2622 | m = 0x1; | |
2623 | else if (i.tm.opcode_modifier.vex0f38) | |
2624 | m = 0x2; | |
2625 | else if (i.tm.opcode_modifier.vex0f3a) | |
2626 | m = 0x3; | |
2627 | else | |
2628 | abort (); | |
2629 | ||
2630 | i.vex.length = 3; | |
2631 | i.vex.bytes[0] = 0xc4; | |
2632 | ||
2633 | /* The high 3 bits of the second VEX byte are 1's compliment | |
2634 | of RXB bits from REX. */ | |
2635 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
2636 | ||
2637 | /* Check the REX.W bit. */ | |
2638 | w = (i.rex & REX_W) ? 1 : 0; | |
2639 | if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1) | |
2640 | { | |
2641 | if (w) | |
2642 | abort (); | |
2643 | ||
2644 | if (i.tm.opcode_modifier.vexw1) | |
2645 | w = 1; | |
2646 | } | |
2647 | ||
2648 | i.vex.bytes[2] = (w << 7 | |
2649 | | register_specifier << 3 | |
2650 | | vector_length << 2 | |
2651 | | implied_prefix); | |
2652 | } | |
2653 | } | |
2654 | ||
65da13b5 L |
2655 | static void |
2656 | process_immext (void) | |
2657 | { | |
2658 | expressionS *exp; | |
2659 | ||
2660 | if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) | |
2661 | { | |
1fed0ba1 L |
2662 | /* SSE3 Instructions have the fixed operands with an opcode |
2663 | suffix which is coded in the same place as an 8-bit immediate | |
2664 | field would be. Here we check those operands and remove them | |
2665 | afterwards. */ | |
65da13b5 L |
2666 | unsigned int x; |
2667 | ||
2668 | for (x = 0; x < i.operands; x++) | |
2669 | if (i.op[x].regs->reg_num != x) | |
2670 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
1fed0ba1 L |
2671 | register_prefix, i.op[x].regs->reg_name, x + 1, |
2672 | i.tm.name); | |
2673 | ||
2674 | i.operands = 0; | |
65da13b5 L |
2675 | } |
2676 | ||
c0f3af97 | 2677 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
2678 | which is coded in the same place as an 8-bit immediate field |
2679 | would be. Here we fake an 8-bit immediate operand from the | |
2680 | opcode suffix stored in tm.extension_opcode. | |
2681 | ||
c0f3af97 L |
2682 | SSE5 and AVX instructions also use this encoding, for some of |
2683 | 3 argument instructions. */ | |
65da13b5 L |
2684 | |
2685 | assert (i.imm_operands == 0 | |
2686 | && (i.operands <= 2 | |
2687 | || (i.tm.cpu_flags.bitfield.cpusse5 | |
c0f3af97 L |
2688 | && i.operands <= 3) |
2689 | || (i.tm.opcode_modifier.vex | |
2690 | && i.operands <= 4))); | |
65da13b5 L |
2691 | |
2692 | exp = &im_expressions[i.imm_operands++]; | |
2693 | i.op[i.operands].imms = exp; | |
2694 | i.types[i.operands] = imm8; | |
2695 | i.operands++; | |
2696 | exp->X_op = O_constant; | |
2697 | exp->X_add_number = i.tm.extension_opcode; | |
2698 | i.tm.extension_opcode = None; | |
2699 | } | |
2700 | ||
252b5132 RH |
2701 | /* This is the guts of the machine-dependent assembler. LINE points to a |
2702 | machine dependent instruction. This function is supposed to emit | |
2703 | the frags/bytes it assembles to. */ | |
2704 | ||
2705 | void | |
65da13b5 | 2706 | md_assemble (char *line) |
252b5132 | 2707 | { |
40fb9820 | 2708 | unsigned int j; |
252b5132 RH |
2709 | char mnemonic[MAX_MNEM_SIZE]; |
2710 | ||
47926f60 | 2711 | /* Initialize globals. */ |
252b5132 RH |
2712 | memset (&i, '\0', sizeof (i)); |
2713 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 2714 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
2715 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
2716 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 2717 | save_stack_p = save_stack; |
252b5132 RH |
2718 | |
2719 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
2720 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 2721 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 2722 | |
29b0f896 AM |
2723 | line = parse_insn (line, mnemonic); |
2724 | if (line == NULL) | |
2725 | return; | |
252b5132 | 2726 | |
29b0f896 AM |
2727 | line = parse_operands (line, mnemonic); |
2728 | if (line == NULL) | |
2729 | return; | |
252b5132 | 2730 | |
29b0f896 AM |
2731 | /* Now we've parsed the mnemonic into a set of templates, and have the |
2732 | operands at hand. */ | |
2733 | ||
2734 | /* All intel opcodes have reversed operands except for "bound" and | |
2735 | "enter". We also don't reverse intersegment "jmp" and "call" | |
2736 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 2737 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
2738 | if (intel_syntax |
2739 | && i.operands > 1 | |
29b0f896 | 2740 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 2741 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
2742 | && !(operand_type_check (i.types[0], imm) |
2743 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
2744 | swap_operands (); |
2745 | ||
ec56d5c0 JB |
2746 | /* The order of the immediates should be reversed |
2747 | for 2 immediates extrq and insertq instructions */ | |
2748 | if (i.imm_operands == 2 | |
2749 | && (strcmp (mnemonic, "extrq") == 0 | |
2750 | || strcmp (mnemonic, "insertq") == 0)) | |
2751 | swap_2_operands (0, 1); | |
2752 | ||
29b0f896 AM |
2753 | if (i.imm_operands) |
2754 | optimize_imm (); | |
2755 | ||
b300c311 L |
2756 | /* Don't optimize displacement for movabs since it only takes 64bit |
2757 | displacement. */ | |
2758 | if (i.disp_operands | |
2759 | && (flag_code != CODE_64BIT | |
2760 | || strcmp (mnemonic, "movabs") != 0)) | |
29b0f896 AM |
2761 | optimize_disp (); |
2762 | ||
2763 | /* Next, we find a template that matches the given insn, | |
2764 | making sure the overlap of the given operands types is consistent | |
2765 | with the template operand types. */ | |
252b5132 | 2766 | |
29b0f896 AM |
2767 | if (!match_template ()) |
2768 | return; | |
252b5132 | 2769 | |
daf50ae7 | 2770 | if (sse_check != sse_check_none |
81f8a913 | 2771 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
2772 | && (i.tm.cpu_flags.bitfield.cpusse |
2773 | || i.tm.cpu_flags.bitfield.cpusse2 | |
2774 | || i.tm.cpu_flags.bitfield.cpusse3 | |
2775 | || i.tm.cpu_flags.bitfield.cpussse3 | |
2776 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
2777 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
2778 | { | |
2779 | (sse_check == sse_check_warning | |
2780 | ? as_warn | |
2781 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
2782 | } | |
2783 | ||
321fd21e L |
2784 | /* Zap movzx and movsx suffix. The suffix has been set from |
2785 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
2786 | or extracted from mnemonic in AT&T syntax. But we'll use | |
2787 | the destination register to choose the suffix for encoding. */ | |
2788 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 2789 | { |
321fd21e L |
2790 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
2791 | there is no suffix, the default will be byte extension. */ | |
2792 | if (i.reg_operands != 2 | |
2793 | && !i.suffix | |
2794 | && intel_syntax) | |
2795 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
2796 | ||
2797 | i.suffix = 0; | |
cd61ebfe | 2798 | } |
24eab124 | 2799 | |
40fb9820 | 2800 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
2801 | if (!add_prefix (FWAIT_OPCODE)) |
2802 | return; | |
252b5132 | 2803 | |
29b0f896 | 2804 | /* Check string instruction segment overrides. */ |
40fb9820 | 2805 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
2806 | { |
2807 | if (!check_string ()) | |
5dd0794d | 2808 | return; |
fc0763e6 | 2809 | i.disp_operands = 0; |
29b0f896 | 2810 | } |
5dd0794d | 2811 | |
29b0f896 AM |
2812 | if (!process_suffix ()) |
2813 | return; | |
e413e4e9 | 2814 | |
29b0f896 AM |
2815 | /* Make still unresolved immediate matches conform to size of immediate |
2816 | given in i.suffix. */ | |
2817 | if (!finalize_imm ()) | |
2818 | return; | |
252b5132 | 2819 | |
40fb9820 | 2820 | if (i.types[0].bitfield.imm1) |
29b0f896 | 2821 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 2822 | |
40fb9820 | 2823 | for (j = 0; j < 3; j++) |
c6fb90c8 L |
2824 | if (i.types[j].bitfield.inoutportreg |
2825 | || i.types[j].bitfield.shiftcount | |
2826 | || i.types[j].bitfield.acc | |
2827 | || i.types[j].bitfield.floatacc) | |
40fb9820 L |
2828 | i.reg_operands--; |
2829 | ||
c0f3af97 L |
2830 | /* ImmExt should be processed after SSE2AVX. */ |
2831 | if (!i.tm.opcode_modifier.sse2avx | |
2832 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 2833 | process_immext (); |
252b5132 | 2834 | |
29b0f896 AM |
2835 | /* For insns with operands there are more diddles to do to the opcode. */ |
2836 | if (i.operands) | |
2837 | { | |
2838 | if (!process_operands ()) | |
2839 | return; | |
2840 | } | |
40fb9820 | 2841 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
2842 | { |
2843 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
2844 | as_warn (_("translating to `%sp'"), i.tm.name); | |
2845 | } | |
252b5132 | 2846 | |
c0f3af97 L |
2847 | if (i.tm.opcode_modifier.vex) |
2848 | build_vex_prefix (); | |
2849 | ||
29b0f896 AM |
2850 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
2851 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
2852 | { | |
2853 | i.tm.base_opcode = INT3_OPCODE; | |
2854 | i.imm_operands = 0; | |
2855 | } | |
252b5132 | 2856 | |
40fb9820 L |
2857 | if ((i.tm.opcode_modifier.jump |
2858 | || i.tm.opcode_modifier.jumpbyte | |
2859 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
2860 | && i.op[0].disps->X_op == O_constant) |
2861 | { | |
2862 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2863 | the absolute address given by the constant. Since ix86 jumps and | |
2864 | calls are pc relative, we need to generate a reloc. */ | |
2865 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
2866 | i.op[0].disps->X_op = O_symbol; | |
2867 | } | |
252b5132 | 2868 | |
40fb9820 | 2869 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 2870 | i.rex |= REX_W; |
252b5132 | 2871 | |
29b0f896 AM |
2872 | /* For 8 bit registers we need an empty rex prefix. Also if the |
2873 | instruction already has a prefix, we need to convert old | |
2874 | registers to new ones. */ | |
773f551c | 2875 | |
40fb9820 | 2876 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 2877 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 2878 | || (i.types[1].bitfield.reg8 |
29b0f896 | 2879 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
2880 | || ((i.types[0].bitfield.reg8 |
2881 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
2882 | && i.rex != 0)) |
2883 | { | |
2884 | int x; | |
726c5dcd | 2885 | |
29b0f896 AM |
2886 | i.rex |= REX_OPCODE; |
2887 | for (x = 0; x < 2; x++) | |
2888 | { | |
2889 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 2890 | if (i.types[x].bitfield.reg8 |
29b0f896 | 2891 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 2892 | { |
29b0f896 AM |
2893 | /* In case it is "hi" register, give up. */ |
2894 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 2895 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 2896 | "instruction requiring REX prefix."), |
a540244d | 2897 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 2898 | |
29b0f896 AM |
2899 | /* Otherwise it is equivalent to the extended register. |
2900 | Since the encoding doesn't change this is merely | |
2901 | cosmetic cleanup for debug output. */ | |
2902 | ||
2903 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 2904 | } |
29b0f896 AM |
2905 | } |
2906 | } | |
773f551c | 2907 | |
85f10a01 MM |
2908 | /* If the instruction has the DREX attribute (aka SSE5), don't emit a |
2909 | REX prefix. */ | |
2910 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
2911 | { | |
2912 | i.drex.rex = i.rex; | |
2913 | i.rex = 0; | |
2914 | } | |
2915 | else if (i.rex != 0) | |
29b0f896 AM |
2916 | add_prefix (REX_OPCODE | i.rex); |
2917 | ||
2918 | /* We are ready to output the insn. */ | |
2919 | output_insn (); | |
2920 | } | |
2921 | ||
2922 | static char * | |
e3bb37b5 | 2923 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
2924 | { |
2925 | char *l = line; | |
2926 | char *token_start = l; | |
2927 | char *mnem_p; | |
5c6af06e JB |
2928 | int supported; |
2929 | const template *t; | |
29b0f896 AM |
2930 | |
2931 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
2932 | const char *expecting_string_instruction = NULL; | |
45288df1 | 2933 | |
29b0f896 AM |
2934 | while (1) |
2935 | { | |
2936 | mnem_p = mnemonic; | |
2937 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
2938 | { | |
2939 | mnem_p++; | |
2940 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 2941 | { |
29b0f896 AM |
2942 | as_bad (_("no such instruction: `%s'"), token_start); |
2943 | return NULL; | |
2944 | } | |
2945 | l++; | |
2946 | } | |
2947 | if (!is_space_char (*l) | |
2948 | && *l != END_OF_INSN | |
e44823cf JB |
2949 | && (intel_syntax |
2950 | || (*l != PREFIX_SEPARATOR | |
2951 | && *l != ','))) | |
29b0f896 AM |
2952 | { |
2953 | as_bad (_("invalid character %s in mnemonic"), | |
2954 | output_invalid (*l)); | |
2955 | return NULL; | |
2956 | } | |
2957 | if (token_start == l) | |
2958 | { | |
e44823cf | 2959 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
2960 | as_bad (_("expecting prefix; got nothing")); |
2961 | else | |
2962 | as_bad (_("expecting mnemonic; got nothing")); | |
2963 | return NULL; | |
2964 | } | |
45288df1 | 2965 | |
29b0f896 AM |
2966 | /* Look up instruction (or prefix) via hash table. */ |
2967 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 2968 | |
29b0f896 AM |
2969 | if (*l != END_OF_INSN |
2970 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
2971 | && current_templates | |
40fb9820 | 2972 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 2973 | { |
c6fb90c8 | 2974 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
2975 | { |
2976 | as_bad ((flag_code != CODE_64BIT | |
2977 | ? _("`%s' is only supported in 64-bit mode") | |
2978 | : _("`%s' is not supported in 64-bit mode")), | |
2979 | current_templates->start->name); | |
2980 | return NULL; | |
2981 | } | |
29b0f896 AM |
2982 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
2983 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
2984 | if ((current_templates->start->opcode_modifier.size16 |
2985 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 2986 | && flag_code != CODE_64BIT |
40fb9820 | 2987 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
2988 | ^ (flag_code == CODE_16BIT))) |
2989 | { | |
2990 | as_bad (_("redundant %s prefix"), | |
2991 | current_templates->start->name); | |
2992 | return NULL; | |
45288df1 | 2993 | } |
29b0f896 AM |
2994 | /* Add prefix, checking for repeated prefixes. */ |
2995 | switch (add_prefix (current_templates->start->base_opcode)) | |
2996 | { | |
2997 | case 0: | |
2998 | return NULL; | |
2999 | case 2: | |
3000 | expecting_string_instruction = current_templates->start->name; | |
3001 | break; | |
3002 | } | |
3003 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
3004 | token_start = ++l; | |
3005 | } | |
3006 | else | |
3007 | break; | |
3008 | } | |
45288df1 | 3009 | |
29b0f896 AM |
3010 | if (!current_templates) |
3011 | { | |
3012 | /* See if we can get a match by trimming off a suffix. */ | |
3013 | switch (mnem_p[-1]) | |
3014 | { | |
3015 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
3016 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
3017 | i.suffix = SHORT_MNEM_SUFFIX; | |
3018 | else | |
29b0f896 AM |
3019 | case BYTE_MNEM_SUFFIX: |
3020 | case QWORD_MNEM_SUFFIX: | |
3021 | i.suffix = mnem_p[-1]; | |
3022 | mnem_p[-1] = '\0'; | |
3023 | current_templates = hash_find (op_hash, mnemonic); | |
3024 | break; | |
3025 | case SHORT_MNEM_SUFFIX: | |
3026 | case LONG_MNEM_SUFFIX: | |
3027 | if (!intel_syntax) | |
3028 | { | |
3029 | i.suffix = mnem_p[-1]; | |
3030 | mnem_p[-1] = '\0'; | |
3031 | current_templates = hash_find (op_hash, mnemonic); | |
3032 | } | |
3033 | break; | |
252b5132 | 3034 | |
29b0f896 AM |
3035 | /* Intel Syntax. */ |
3036 | case 'd': | |
3037 | if (intel_syntax) | |
3038 | { | |
9306ca4a | 3039 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
3040 | i.suffix = SHORT_MNEM_SUFFIX; |
3041 | else | |
3042 | i.suffix = LONG_MNEM_SUFFIX; | |
3043 | mnem_p[-1] = '\0'; | |
3044 | current_templates = hash_find (op_hash, mnemonic); | |
3045 | } | |
3046 | break; | |
3047 | } | |
3048 | if (!current_templates) | |
3049 | { | |
3050 | as_bad (_("no such instruction: `%s'"), token_start); | |
3051 | return NULL; | |
3052 | } | |
3053 | } | |
252b5132 | 3054 | |
40fb9820 L |
3055 | if (current_templates->start->opcode_modifier.jump |
3056 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
3057 | { |
3058 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
3059 | predict taken and predict not taken respectively. | |
3060 | I'm not sure that branch hints actually do anything on loop | |
3061 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
3062 | may work in the future and it doesn't hurt to accept them | |
3063 | now. */ | |
3064 | if (l[0] == ',' && l[1] == 'p') | |
3065 | { | |
3066 | if (l[2] == 't') | |
3067 | { | |
3068 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
3069 | return NULL; | |
3070 | l += 3; | |
3071 | } | |
3072 | else if (l[2] == 'n') | |
3073 | { | |
3074 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
3075 | return NULL; | |
3076 | l += 3; | |
3077 | } | |
3078 | } | |
3079 | } | |
3080 | /* Any other comma loses. */ | |
3081 | if (*l == ',') | |
3082 | { | |
3083 | as_bad (_("invalid character %s in mnemonic"), | |
3084 | output_invalid (*l)); | |
3085 | return NULL; | |
3086 | } | |
252b5132 | 3087 | |
29b0f896 | 3088 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
3089 | supported = 0; |
3090 | for (t = current_templates->start; t < current_templates->end; ++t) | |
3091 | { | |
c0f3af97 L |
3092 | supported |= cpu_flags_match (t); |
3093 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 3094 | goto skip; |
5c6af06e | 3095 | } |
3629bb00 | 3096 | |
c0f3af97 | 3097 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
3098 | { |
3099 | as_bad (flag_code == CODE_64BIT | |
3100 | ? _("`%s' is not supported in 64-bit mode") | |
3101 | : _("`%s' is only supported in 64-bit mode"), | |
3102 | current_templates->start->name); | |
3103 | return NULL; | |
3104 | } | |
c0f3af97 | 3105 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 3106 | { |
3629bb00 L |
3107 | as_bad (_("`%s' is not supported on `%s%s'"), |
3108 | current_templates->start->name, cpu_arch_name, | |
3109 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
3110 | return NULL; | |
29b0f896 | 3111 | } |
3629bb00 L |
3112 | |
3113 | skip: | |
3114 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 3115 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
3116 | { |
3117 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3118 | } | |
252b5132 | 3119 | |
29b0f896 | 3120 | /* Check for rep/repne without a string instruction. */ |
f41bbced | 3121 | if (expecting_string_instruction) |
29b0f896 | 3122 | { |
f41bbced JB |
3123 | static templates override; |
3124 | ||
3125 | for (t = current_templates->start; t < current_templates->end; ++t) | |
40fb9820 | 3126 | if (t->opcode_modifier.isstring) |
f41bbced JB |
3127 | break; |
3128 | if (t >= current_templates->end) | |
3129 | { | |
3130 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 3131 | expecting_string_instruction); |
f41bbced JB |
3132 | return NULL; |
3133 | } | |
3134 | for (override.start = t; t < current_templates->end; ++t) | |
40fb9820 | 3135 | if (!t->opcode_modifier.isstring) |
f41bbced JB |
3136 | break; |
3137 | override.end = t; | |
3138 | current_templates = &override; | |
29b0f896 | 3139 | } |
252b5132 | 3140 | |
29b0f896 AM |
3141 | return l; |
3142 | } | |
252b5132 | 3143 | |
29b0f896 | 3144 | static char * |
e3bb37b5 | 3145 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
3146 | { |
3147 | char *token_start; | |
3138f287 | 3148 | |
29b0f896 AM |
3149 | /* 1 if operand is pending after ','. */ |
3150 | unsigned int expecting_operand = 0; | |
252b5132 | 3151 | |
29b0f896 AM |
3152 | /* Non-zero if operand parens not balanced. */ |
3153 | unsigned int paren_not_balanced; | |
3154 | ||
3155 | while (*l != END_OF_INSN) | |
3156 | { | |
3157 | /* Skip optional white space before operand. */ | |
3158 | if (is_space_char (*l)) | |
3159 | ++l; | |
3160 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
3161 | { | |
3162 | as_bad (_("invalid character %s before operand %d"), | |
3163 | output_invalid (*l), | |
3164 | i.operands + 1); | |
3165 | return NULL; | |
3166 | } | |
3167 | token_start = l; /* after white space */ | |
3168 | paren_not_balanced = 0; | |
3169 | while (paren_not_balanced || *l != ',') | |
3170 | { | |
3171 | if (*l == END_OF_INSN) | |
3172 | { | |
3173 | if (paren_not_balanced) | |
3174 | { | |
3175 | if (!intel_syntax) | |
3176 | as_bad (_("unbalanced parenthesis in operand %d."), | |
3177 | i.operands + 1); | |
3178 | else | |
3179 | as_bad (_("unbalanced brackets in operand %d."), | |
3180 | i.operands + 1); | |
3181 | return NULL; | |
3182 | } | |
3183 | else | |
3184 | break; /* we are done */ | |
3185 | } | |
3186 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
3187 | { | |
3188 | as_bad (_("invalid character %s in operand %d"), | |
3189 | output_invalid (*l), | |
3190 | i.operands + 1); | |
3191 | return NULL; | |
3192 | } | |
3193 | if (!intel_syntax) | |
3194 | { | |
3195 | if (*l == '(') | |
3196 | ++paren_not_balanced; | |
3197 | if (*l == ')') | |
3198 | --paren_not_balanced; | |
3199 | } | |
3200 | else | |
3201 | { | |
3202 | if (*l == '[') | |
3203 | ++paren_not_balanced; | |
3204 | if (*l == ']') | |
3205 | --paren_not_balanced; | |
3206 | } | |
3207 | l++; | |
3208 | } | |
3209 | if (l != token_start) | |
3210 | { /* Yes, we've read in another operand. */ | |
3211 | unsigned int operand_ok; | |
3212 | this_operand = i.operands++; | |
7d5e4556 | 3213 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
3214 | if (i.operands > MAX_OPERANDS) |
3215 | { | |
3216 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
3217 | MAX_OPERANDS); | |
3218 | return NULL; | |
3219 | } | |
3220 | /* Now parse operand adding info to 'i' as we go along. */ | |
3221 | END_STRING_AND_SAVE (l); | |
3222 | ||
3223 | if (intel_syntax) | |
3224 | operand_ok = | |
3225 | i386_intel_operand (token_start, | |
3226 | intel_float_operand (mnemonic)); | |
3227 | else | |
a7619375 | 3228 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
3229 | |
3230 | RESTORE_END_STRING (l); | |
3231 | if (!operand_ok) | |
3232 | return NULL; | |
3233 | } | |
3234 | else | |
3235 | { | |
3236 | if (expecting_operand) | |
3237 | { | |
3238 | expecting_operand_after_comma: | |
3239 | as_bad (_("expecting operand after ','; got nothing")); | |
3240 | return NULL; | |
3241 | } | |
3242 | if (*l == ',') | |
3243 | { | |
3244 | as_bad (_("expecting operand before ','; got nothing")); | |
3245 | return NULL; | |
3246 | } | |
3247 | } | |
7f3f1ea2 | 3248 | |
29b0f896 AM |
3249 | /* Now *l must be either ',' or END_OF_INSN. */ |
3250 | if (*l == ',') | |
3251 | { | |
3252 | if (*++l == END_OF_INSN) | |
3253 | { | |
3254 | /* Just skip it, if it's \n complain. */ | |
3255 | goto expecting_operand_after_comma; | |
3256 | } | |
3257 | expecting_operand = 1; | |
3258 | } | |
3259 | } | |
3260 | return l; | |
3261 | } | |
7f3f1ea2 | 3262 | |
050dfa73 | 3263 | static void |
4d456e3d | 3264 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
3265 | { |
3266 | union i386_op temp_op; | |
40fb9820 | 3267 | i386_operand_type temp_type; |
050dfa73 | 3268 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 3269 | |
050dfa73 MM |
3270 | temp_type = i.types[xchg2]; |
3271 | i.types[xchg2] = i.types[xchg1]; | |
3272 | i.types[xchg1] = temp_type; | |
3273 | temp_op = i.op[xchg2]; | |
3274 | i.op[xchg2] = i.op[xchg1]; | |
3275 | i.op[xchg1] = temp_op; | |
3276 | temp_reloc = i.reloc[xchg2]; | |
3277 | i.reloc[xchg2] = i.reloc[xchg1]; | |
3278 | i.reloc[xchg1] = temp_reloc; | |
3279 | } | |
3280 | ||
29b0f896 | 3281 | static void |
e3bb37b5 | 3282 | swap_operands (void) |
29b0f896 | 3283 | { |
b7c61d9a | 3284 | switch (i.operands) |
050dfa73 | 3285 | { |
c0f3af97 | 3286 | case 5: |
b7c61d9a | 3287 | case 4: |
4d456e3d | 3288 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
3289 | case 3: |
3290 | case 2: | |
4d456e3d | 3291 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
3292 | break; |
3293 | default: | |
3294 | abort (); | |
29b0f896 | 3295 | } |
29b0f896 AM |
3296 | |
3297 | if (i.mem_operands == 2) | |
3298 | { | |
3299 | const seg_entry *temp_seg; | |
3300 | temp_seg = i.seg[0]; | |
3301 | i.seg[0] = i.seg[1]; | |
3302 | i.seg[1] = temp_seg; | |
3303 | } | |
3304 | } | |
252b5132 | 3305 | |
29b0f896 AM |
3306 | /* Try to ensure constant immediates are represented in the smallest |
3307 | opcode possible. */ | |
3308 | static void | |
e3bb37b5 | 3309 | optimize_imm (void) |
29b0f896 AM |
3310 | { |
3311 | char guess_suffix = 0; | |
3312 | int op; | |
252b5132 | 3313 | |
29b0f896 AM |
3314 | if (i.suffix) |
3315 | guess_suffix = i.suffix; | |
3316 | else if (i.reg_operands) | |
3317 | { | |
3318 | /* Figure out a suffix from the last register operand specified. | |
3319 | We can't do this properly yet, ie. excluding InOutPortReg, | |
3320 | but the following works for instructions with immediates. | |
3321 | In any case, we can't set i.suffix yet. */ | |
3322 | for (op = i.operands; --op >= 0;) | |
40fb9820 L |
3323 | if (i.types[op].bitfield.reg8) |
3324 | { | |
3325 | guess_suffix = BYTE_MNEM_SUFFIX; | |
3326 | break; | |
3327 | } | |
3328 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 3329 | { |
40fb9820 L |
3330 | guess_suffix = WORD_MNEM_SUFFIX; |
3331 | break; | |
3332 | } | |
3333 | else if (i.types[op].bitfield.reg32) | |
3334 | { | |
3335 | guess_suffix = LONG_MNEM_SUFFIX; | |
3336 | break; | |
3337 | } | |
3338 | else if (i.types[op].bitfield.reg64) | |
3339 | { | |
3340 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 3341 | break; |
252b5132 | 3342 | } |
29b0f896 AM |
3343 | } |
3344 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
3345 | guess_suffix = WORD_MNEM_SUFFIX; | |
3346 | ||
3347 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3348 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
3349 | { |
3350 | switch (i.op[op].imms->X_op) | |
252b5132 | 3351 | { |
29b0f896 AM |
3352 | case O_constant: |
3353 | /* If a suffix is given, this operand may be shortened. */ | |
3354 | switch (guess_suffix) | |
252b5132 | 3355 | { |
29b0f896 | 3356 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
3357 | i.types[op].bitfield.imm32 = 1; |
3358 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3359 | break; |
3360 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
3361 | i.types[op].bitfield.imm16 = 1; |
3362 | i.types[op].bitfield.imm32 = 1; | |
3363 | i.types[op].bitfield.imm32s = 1; | |
3364 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3365 | break; |
3366 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
3367 | i.types[op].bitfield.imm8 = 1; |
3368 | i.types[op].bitfield.imm8s = 1; | |
3369 | i.types[op].bitfield.imm16 = 1; | |
3370 | i.types[op].bitfield.imm32 = 1; | |
3371 | i.types[op].bitfield.imm32s = 1; | |
3372 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 3373 | break; |
252b5132 | 3374 | } |
252b5132 | 3375 | |
29b0f896 AM |
3376 | /* If this operand is at most 16 bits, convert it |
3377 | to a signed 16 bit number before trying to see | |
3378 | whether it will fit in an even smaller size. | |
3379 | This allows a 16-bit operand such as $0xffe0 to | |
3380 | be recognised as within Imm8S range. */ | |
40fb9820 | 3381 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 3382 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 3383 | { |
29b0f896 AM |
3384 | i.op[op].imms->X_add_number = |
3385 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
3386 | } | |
40fb9820 | 3387 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
3388 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
3389 | == 0)) | |
3390 | { | |
3391 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
3392 | ^ ((offsetT) 1 << 31)) | |
3393 | - ((offsetT) 1 << 31)); | |
3394 | } | |
40fb9820 | 3395 | i.types[op] |
c6fb90c8 L |
3396 | = operand_type_or (i.types[op], |
3397 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 3398 | |
29b0f896 AM |
3399 | /* We must avoid matching of Imm32 templates when 64bit |
3400 | only immediate is available. */ | |
3401 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 3402 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 3403 | break; |
252b5132 | 3404 | |
29b0f896 AM |
3405 | case O_absent: |
3406 | case O_register: | |
3407 | abort (); | |
3408 | ||
3409 | /* Symbols and expressions. */ | |
3410 | default: | |
9cd96992 JB |
3411 | /* Convert symbolic operand to proper sizes for matching, but don't |
3412 | prevent matching a set of insns that only supports sizes other | |
3413 | than those matching the insn suffix. */ | |
3414 | { | |
40fb9820 | 3415 | i386_operand_type mask, allowed; |
9cd96992 JB |
3416 | const template *t; |
3417 | ||
0dfbf9d7 L |
3418 | operand_type_set (&mask, 0); |
3419 | operand_type_set (&allowed, 0); | |
40fb9820 | 3420 | |
4eed87de AM |
3421 | for (t = current_templates->start; |
3422 | t < current_templates->end; | |
3423 | ++t) | |
c6fb90c8 L |
3424 | allowed = operand_type_or (allowed, |
3425 | t->operand_types[op]); | |
9cd96992 JB |
3426 | switch (guess_suffix) |
3427 | { | |
3428 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
3429 | mask.bitfield.imm64 = 1; |
3430 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
3431 | break; |
3432 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 3433 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
3434 | break; |
3435 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 3436 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
3437 | break; |
3438 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 3439 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
3440 | break; |
3441 | default: | |
9cd96992 JB |
3442 | break; |
3443 | } | |
c6fb90c8 | 3444 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 3445 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 3446 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 3447 | } |
29b0f896 | 3448 | break; |
252b5132 | 3449 | } |
29b0f896 AM |
3450 | } |
3451 | } | |
47926f60 | 3452 | |
29b0f896 AM |
3453 | /* Try to use the smallest displacement type too. */ |
3454 | static void | |
e3bb37b5 | 3455 | optimize_disp (void) |
29b0f896 AM |
3456 | { |
3457 | int op; | |
3e73aa7c | 3458 | |
29b0f896 | 3459 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3460 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 3461 | { |
b300c311 | 3462 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 3463 | { |
b300c311 | 3464 | offsetT disp = i.op[op].disps->X_add_number; |
29b0f896 | 3465 | |
40fb9820 | 3466 | if (i.types[op].bitfield.disp16 |
b300c311 L |
3467 | && (disp & ~(offsetT) 0xffff) == 0) |
3468 | { | |
3469 | /* If this operand is at most 16 bits, convert | |
3470 | to a signed 16 bit number and don't use 64bit | |
3471 | displacement. */ | |
3472 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
40fb9820 | 3473 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3474 | } |
40fb9820 | 3475 | if (i.types[op].bitfield.disp32 |
b300c311 L |
3476 | && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
3477 | { | |
3478 | /* If this operand is at most 32 bits, convert | |
3479 | to a signed 32 bit number and don't use 64bit | |
3480 | displacement. */ | |
3481 | disp &= (((offsetT) 2 << 31) - 1); | |
3482 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 3483 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3484 | } |
40fb9820 | 3485 | if (!disp && i.types[op].bitfield.baseindex) |
b300c311 | 3486 | { |
40fb9820 L |
3487 | i.types[op].bitfield.disp8 = 0; |
3488 | i.types[op].bitfield.disp16 = 0; | |
3489 | i.types[op].bitfield.disp32 = 0; | |
3490 | i.types[op].bitfield.disp32s = 0; | |
3491 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
3492 | i.op[op].disps = 0; |
3493 | i.disp_operands--; | |
3494 | } | |
3495 | else if (flag_code == CODE_64BIT) | |
3496 | { | |
3497 | if (fits_in_signed_long (disp)) | |
28a9d8f5 | 3498 | { |
40fb9820 L |
3499 | i.types[op].bitfield.disp64 = 0; |
3500 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 3501 | } |
b300c311 | 3502 | if (fits_in_unsigned_long (disp)) |
40fb9820 | 3503 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 3504 | } |
40fb9820 L |
3505 | if ((i.types[op].bitfield.disp32 |
3506 | || i.types[op].bitfield.disp32s | |
3507 | || i.types[op].bitfield.disp16) | |
b300c311 | 3508 | && fits_in_signed_byte (disp)) |
40fb9820 | 3509 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 3510 | } |
67a4f2b7 AO |
3511 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3512 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3513 | { | |
3514 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3515 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3516 | i.types[op].bitfield.disp8 = 0; |
3517 | i.types[op].bitfield.disp16 = 0; | |
3518 | i.types[op].bitfield.disp32 = 0; | |
3519 | i.types[op].bitfield.disp32s = 0; | |
3520 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3521 | } |
3522 | else | |
b300c311 | 3523 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3524 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3525 | } |
29b0f896 AM |
3526 | } |
3527 | ||
c0f3af97 L |
3528 | /* Check if operands are valid for the instrucrtion. Update VEX |
3529 | operand types. */ | |
3530 | ||
3531 | static int | |
3532 | VEX_check_operands (const template *t) | |
3533 | { | |
3534 | if (!t->opcode_modifier.vex) | |
3535 | return 0; | |
3536 | ||
3537 | /* Only check VEX_Imm4, which must be the first operand. */ | |
3538 | if (t->operand_types[0].bitfield.vex_imm4) | |
3539 | { | |
3540 | if (i.op[0].imms->X_op != O_constant | |
3541 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
3542 | return 1; | |
3543 | ||
3544 | /* Turn off Imm8 so that update_imm won't complain. */ | |
3545 | i.types[0] = vex_imm4; | |
3546 | } | |
3547 | ||
3548 | return 0; | |
3549 | } | |
3550 | ||
29b0f896 | 3551 | static int |
e3bb37b5 | 3552 | match_template (void) |
29b0f896 AM |
3553 | { |
3554 | /* Points to template once we've found it. */ | |
3555 | const template *t; | |
40fb9820 | 3556 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 3557 | i386_operand_type overlap4; |
29b0f896 | 3558 | unsigned int found_reverse_match; |
40fb9820 L |
3559 | i386_opcode_modifier suffix_check; |
3560 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 3561 | int addr_prefix_disp; |
a5c311ca | 3562 | unsigned int j; |
3629bb00 | 3563 | unsigned int found_cpu_match; |
45664ddb | 3564 | unsigned int check_register; |
29b0f896 | 3565 | |
c0f3af97 L |
3566 | #if MAX_OPERANDS != 5 |
3567 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
3568 | #endif |
3569 | ||
29b0f896 | 3570 | found_reverse_match = 0; |
539e75ad | 3571 | addr_prefix_disp = -1; |
40fb9820 L |
3572 | |
3573 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
3574 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
3575 | suffix_check.no_bsuf = 1; | |
3576 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3577 | suffix_check.no_wsuf = 1; | |
3578 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
3579 | suffix_check.no_ssuf = 1; | |
3580 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3581 | suffix_check.no_lsuf = 1; | |
3582 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3583 | suffix_check.no_qsuf = 1; | |
3584 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 3585 | suffix_check.no_ldsuf = 1; |
29b0f896 | 3586 | |
45aa61fe | 3587 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 3588 | { |
539e75ad L |
3589 | addr_prefix_disp = -1; |
3590 | ||
29b0f896 AM |
3591 | /* Must have right number of operands. */ |
3592 | if (i.operands != t->operands) | |
3593 | continue; | |
3594 | ||
50aecf8c | 3595 | /* Check processor support. */ |
c0f3af97 L |
3596 | found_cpu_match = (cpu_flags_match (t) |
3597 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
3598 | if (!found_cpu_match) |
3599 | continue; | |
3600 | ||
e1d4d893 L |
3601 | /* Check old gcc support. */ |
3602 | if (!old_gcc && t->opcode_modifier.oldgcc) | |
3603 | continue; | |
3604 | ||
3605 | /* Check AT&T mnemonic. */ | |
3606 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) | |
1efbbeb4 L |
3607 | continue; |
3608 | ||
5c07affc L |
3609 | /* Check AT&T syntax Intel syntax. */ |
3610 | if ((intel_syntax && t->opcode_modifier.attsyntax) | |
3611 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) | |
1efbbeb4 L |
3612 | continue; |
3613 | ||
20592a94 | 3614 | /* Check the suffix, except for some instructions in intel mode. */ |
567e4e96 L |
3615 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
3616 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
3617 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
3618 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
3619 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
3620 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
3621 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
3622 | continue; |
3623 | ||
5c07affc | 3624 | if (!operand_size_match (t)) |
7d5e4556 | 3625 | continue; |
539e75ad | 3626 | |
5c07affc L |
3627 | for (j = 0; j < MAX_OPERANDS; j++) |
3628 | operand_types[j] = t->operand_types[j]; | |
3629 | ||
45aa61fe AM |
3630 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
3631 | if (i.suffix == QWORD_MNEM_SUFFIX | |
3632 | && flag_code != CODE_64BIT | |
3633 | && (intel_syntax | |
40fb9820 | 3634 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
3635 | && !intel_float_operand (t->name)) |
3636 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 3637 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 L |
3638 | && !operand_types[0].bitfield.regxmm |
3639 | && !operand_types[0].bitfield.regymm) | |
40fb9820 | 3640 | || (!operand_types[t->operands > 1].bitfield.regmmx |
c0f3af97 L |
3641 | && !!operand_types[t->operands > 1].bitfield.regxmm |
3642 | && !!operand_types[t->operands > 1].bitfield.regymm)) | |
45aa61fe AM |
3643 | && (t->base_opcode != 0x0fc7 |
3644 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
3645 | continue; | |
3646 | ||
192dc9c6 JB |
3647 | /* In general, don't allow 32-bit operands on pre-386. */ |
3648 | else if (i.suffix == LONG_MNEM_SUFFIX | |
3649 | && !cpu_arch_flags.bitfield.cpui386 | |
3650 | && (intel_syntax | |
3651 | ? (!t->opcode_modifier.ignoresize | |
3652 | && !intel_float_operand (t->name)) | |
3653 | : intel_float_operand (t->name) != 2) | |
3654 | && ((!operand_types[0].bitfield.regmmx | |
3655 | && !operand_types[0].bitfield.regxmm) | |
3656 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
3657 | && !!operand_types[t->operands > 1].bitfield.regxmm))) | |
3658 | continue; | |
3659 | ||
29b0f896 | 3660 | /* Do not verify operands when there are none. */ |
50aecf8c | 3661 | else |
29b0f896 | 3662 | { |
c6fb90c8 | 3663 | if (!t->operands) |
2dbab7d5 L |
3664 | /* We've found a match; break out of loop. */ |
3665 | break; | |
29b0f896 | 3666 | } |
252b5132 | 3667 | |
539e75ad L |
3668 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
3669 | into Disp32/Disp16/Disp32 operand. */ | |
3670 | if (i.prefix[ADDR_PREFIX] != 0) | |
3671 | { | |
40fb9820 | 3672 | /* There should be only one Disp operand. */ |
539e75ad L |
3673 | switch (flag_code) |
3674 | { | |
3675 | case CODE_16BIT: | |
40fb9820 L |
3676 | for (j = 0; j < MAX_OPERANDS; j++) |
3677 | { | |
3678 | if (operand_types[j].bitfield.disp16) | |
3679 | { | |
3680 | addr_prefix_disp = j; | |
3681 | operand_types[j].bitfield.disp32 = 1; | |
3682 | operand_types[j].bitfield.disp16 = 0; | |
3683 | break; | |
3684 | } | |
3685 | } | |
539e75ad L |
3686 | break; |
3687 | case CODE_32BIT: | |
40fb9820 L |
3688 | for (j = 0; j < MAX_OPERANDS; j++) |
3689 | { | |
3690 | if (operand_types[j].bitfield.disp32) | |
3691 | { | |
3692 | addr_prefix_disp = j; | |
3693 | operand_types[j].bitfield.disp32 = 0; | |
3694 | operand_types[j].bitfield.disp16 = 1; | |
3695 | break; | |
3696 | } | |
3697 | } | |
539e75ad L |
3698 | break; |
3699 | case CODE_64BIT: | |
40fb9820 L |
3700 | for (j = 0; j < MAX_OPERANDS; j++) |
3701 | { | |
3702 | if (operand_types[j].bitfield.disp64) | |
3703 | { | |
3704 | addr_prefix_disp = j; | |
3705 | operand_types[j].bitfield.disp64 = 0; | |
3706 | operand_types[j].bitfield.disp32 = 1; | |
3707 | break; | |
3708 | } | |
3709 | } | |
539e75ad L |
3710 | break; |
3711 | } | |
539e75ad L |
3712 | } |
3713 | ||
45664ddb L |
3714 | /* We check register size only if size of operands can be |
3715 | encoded the canonical way. */ | |
3716 | check_register = t->opcode_modifier.w; | |
c6fb90c8 | 3717 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
3718 | switch (t->operands) |
3719 | { | |
3720 | case 1: | |
40fb9820 | 3721 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
3722 | continue; |
3723 | break; | |
3724 | case 2: | |
8b38ad71 L |
3725 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
3726 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
3727 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
3728 | zero-extend %eax to %rax. */ | |
3729 | if (flag_code == CODE_64BIT | |
3730 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
3731 | && operand_type_equal (&i.types [0], &acc32) |
3732 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 3733 | continue; |
29b0f896 | 3734 | case 3: |
f48ff2ae | 3735 | case 4: |
c0f3af97 | 3736 | case 5: |
c6fb90c8 | 3737 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
3738 | if (!operand_type_match (overlap0, i.types[0]) |
3739 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3740 | || (check_register |
3741 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
3742 | operand_types[0], |
3743 | overlap1, i.types[1], | |
3744 | operand_types[1]))) | |
29b0f896 AM |
3745 | { |
3746 | /* Check if other direction is valid ... */ | |
40fb9820 | 3747 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
3748 | continue; |
3749 | ||
3750 | /* Try reversing direction of operands. */ | |
c6fb90c8 L |
3751 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
3752 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
3753 | if (!operand_type_match (overlap0, i.types[0]) |
3754 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3755 | || (check_register |
3756 | && !operand_type_register_match (overlap0, | |
3757 | i.types[0], | |
3758 | operand_types[1], | |
3759 | overlap1, | |
3760 | i.types[1], | |
3761 | operand_types[0]))) | |
29b0f896 AM |
3762 | { |
3763 | /* Does not match either direction. */ | |
3764 | continue; | |
3765 | } | |
3766 | /* found_reverse_match holds which of D or FloatDR | |
3767 | we've found. */ | |
40fb9820 | 3768 | if (t->opcode_modifier.d) |
8a2ed489 | 3769 | found_reverse_match = Opcode_D; |
40fb9820 | 3770 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
3771 | found_reverse_match = Opcode_FloatD; |
3772 | else | |
3773 | found_reverse_match = 0; | |
40fb9820 | 3774 | if (t->opcode_modifier.floatr) |
8a2ed489 | 3775 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 3776 | } |
f48ff2ae | 3777 | else |
29b0f896 | 3778 | { |
f48ff2ae | 3779 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
3780 | switch (t->operands) |
3781 | { | |
c0f3af97 L |
3782 | case 5: |
3783 | overlap4 = operand_type_and (i.types[4], | |
3784 | operand_types[4]); | |
d1cbb4db | 3785 | case 4: |
c6fb90c8 L |
3786 | overlap3 = operand_type_and (i.types[3], |
3787 | operand_types[3]); | |
d1cbb4db | 3788 | case 3: |
c6fb90c8 L |
3789 | overlap2 = operand_type_and (i.types[2], |
3790 | operand_types[2]); | |
d1cbb4db L |
3791 | break; |
3792 | } | |
29b0f896 | 3793 | |
f48ff2ae L |
3794 | switch (t->operands) |
3795 | { | |
c0f3af97 L |
3796 | case 5: |
3797 | if (!operand_type_match (overlap4, i.types[4]) | |
3798 | || !operand_type_register_match (overlap3, | |
3799 | i.types[3], | |
3800 | operand_types[3], | |
3801 | overlap4, | |
3802 | i.types[4], | |
3803 | operand_types[4])) | |
3804 | continue; | |
f48ff2ae | 3805 | case 4: |
40fb9820 | 3806 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
3807 | || (check_register |
3808 | && !operand_type_register_match (overlap2, | |
3809 | i.types[2], | |
3810 | operand_types[2], | |
3811 | overlap3, | |
3812 | i.types[3], | |
3813 | operand_types[3]))) | |
f48ff2ae L |
3814 | continue; |
3815 | case 3: | |
3816 | /* Here we make use of the fact that there are no | |
3817 | reverse match 3 operand instructions, and all 3 | |
3818 | operand instructions only need to be checked for | |
3819 | register consistency between operands 2 and 3. */ | |
40fb9820 | 3820 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
3821 | || (check_register |
3822 | && !operand_type_register_match (overlap1, | |
3823 | i.types[1], | |
3824 | operand_types[1], | |
3825 | overlap2, | |
3826 | i.types[2], | |
3827 | operand_types[2]))) | |
f48ff2ae L |
3828 | continue; |
3829 | break; | |
3830 | } | |
29b0f896 | 3831 | } |
f48ff2ae | 3832 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
3833 | slip through to break. */ |
3834 | } | |
3629bb00 | 3835 | if (!found_cpu_match) |
29b0f896 AM |
3836 | { |
3837 | found_reverse_match = 0; | |
3838 | continue; | |
3839 | } | |
c0f3af97 L |
3840 | |
3841 | /* Check if VEX operands are valid. */ | |
3842 | if (VEX_check_operands (t)) | |
3843 | continue; | |
3844 | ||
29b0f896 AM |
3845 | /* We've found a match; break out of loop. */ |
3846 | break; | |
3847 | } | |
3848 | ||
3849 | if (t == current_templates->end) | |
3850 | { | |
3851 | /* We found no match. */ | |
95f283e8 L |
3852 | if (intel_syntax) |
3853 | as_bad (_("ambiguous operand size or operands invalid for `%s'"), | |
3854 | current_templates->start->name); | |
3855 | else | |
3856 | as_bad (_("suffix or operands invalid for `%s'"), | |
3857 | current_templates->start->name); | |
29b0f896 AM |
3858 | return 0; |
3859 | } | |
252b5132 | 3860 | |
29b0f896 AM |
3861 | if (!quiet_warnings) |
3862 | { | |
3863 | if (!intel_syntax | |
40fb9820 L |
3864 | && (i.types[0].bitfield.jumpabsolute |
3865 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
3866 | { |
3867 | as_warn (_("indirect %s without `*'"), t->name); | |
3868 | } | |
3869 | ||
40fb9820 L |
3870 | if (t->opcode_modifier.isprefix |
3871 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
3872 | { |
3873 | /* Warn them that a data or address size prefix doesn't | |
3874 | affect assembly of the next line of code. */ | |
3875 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
3876 | } | |
3877 | } | |
3878 | ||
3879 | /* Copy the template we found. */ | |
3880 | i.tm = *t; | |
539e75ad L |
3881 | |
3882 | if (addr_prefix_disp != -1) | |
3883 | i.tm.operand_types[addr_prefix_disp] | |
3884 | = operand_types[addr_prefix_disp]; | |
3885 | ||
29b0f896 AM |
3886 | if (found_reverse_match) |
3887 | { | |
3888 | /* If we found a reverse match we must alter the opcode | |
3889 | direction bit. found_reverse_match holds bits to change | |
3890 | (different for int & float insns). */ | |
3891 | ||
3892 | i.tm.base_opcode ^= found_reverse_match; | |
3893 | ||
539e75ad L |
3894 | i.tm.operand_types[0] = operand_types[1]; |
3895 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
3896 | } |
3897 | ||
3898 | return 1; | |
3899 | } | |
3900 | ||
3901 | static int | |
e3bb37b5 | 3902 | check_string (void) |
29b0f896 | 3903 | { |
40fb9820 L |
3904 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
3905 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
3906 | { |
3907 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
3908 | { | |
a87af027 | 3909 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 3910 | i.tm.name, |
a87af027 JB |
3911 | mem_op + 1, |
3912 | register_prefix); | |
29b0f896 AM |
3913 | return 0; |
3914 | } | |
3915 | /* There's only ever one segment override allowed per instruction. | |
3916 | This instruction possibly has a legal segment override on the | |
3917 | second operand, so copy the segment to where non-string | |
3918 | instructions store it, allowing common code. */ | |
3919 | i.seg[0] = i.seg[1]; | |
3920 | } | |
40fb9820 | 3921 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
3922 | { |
3923 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
3924 | { | |
a87af027 | 3925 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 3926 | i.tm.name, |
a87af027 JB |
3927 | mem_op + 2, |
3928 | register_prefix); | |
29b0f896 AM |
3929 | return 0; |
3930 | } | |
3931 | } | |
3932 | return 1; | |
3933 | } | |
3934 | ||
3935 | static int | |
543613e9 | 3936 | process_suffix (void) |
29b0f896 AM |
3937 | { |
3938 | /* If matched instruction specifies an explicit instruction mnemonic | |
3939 | suffix, use it. */ | |
40fb9820 L |
3940 | if (i.tm.opcode_modifier.size16) |
3941 | i.suffix = WORD_MNEM_SUFFIX; | |
3942 | else if (i.tm.opcode_modifier.size32) | |
3943 | i.suffix = LONG_MNEM_SUFFIX; | |
3944 | else if (i.tm.opcode_modifier.size64) | |
3945 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
3946 | else if (i.reg_operands) |
3947 | { | |
3948 | /* If there's no instruction mnemonic suffix we try to invent one | |
3949 | based on register operands. */ | |
3950 | if (!i.suffix) | |
3951 | { | |
3952 | /* We take i.suffix from the last register operand specified, | |
3953 | Destination register type is more significant than source | |
381d071f L |
3954 | register type. crc32 in SSE4.2 prefers source register |
3955 | type. */ | |
3956 | if (i.tm.base_opcode == 0xf20f38f1) | |
3957 | { | |
40fb9820 L |
3958 | if (i.types[0].bitfield.reg16) |
3959 | i.suffix = WORD_MNEM_SUFFIX; | |
3960 | else if (i.types[0].bitfield.reg32) | |
3961 | i.suffix = LONG_MNEM_SUFFIX; | |
3962 | else if (i.types[0].bitfield.reg64) | |
3963 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 3964 | } |
9344ff29 | 3965 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 3966 | { |
40fb9820 | 3967 | if (i.types[0].bitfield.reg8) |
20592a94 L |
3968 | i.suffix = BYTE_MNEM_SUFFIX; |
3969 | } | |
381d071f L |
3970 | |
3971 | if (!i.suffix) | |
3972 | { | |
3973 | int op; | |
3974 | ||
20592a94 L |
3975 | if (i.tm.base_opcode == 0xf20f38f1 |
3976 | || i.tm.base_opcode == 0xf20f38f0) | |
3977 | { | |
3978 | /* We have to know the operand size for crc32. */ | |
3979 | as_bad (_("ambiguous memory operand size for `%s`"), | |
3980 | i.tm.name); | |
3981 | return 0; | |
3982 | } | |
3983 | ||
381d071f | 3984 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3985 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 3986 | { |
40fb9820 L |
3987 | if (i.types[op].bitfield.reg8) |
3988 | { | |
3989 | i.suffix = BYTE_MNEM_SUFFIX; | |
3990 | break; | |
3991 | } | |
3992 | else if (i.types[op].bitfield.reg16) | |
3993 | { | |
3994 | i.suffix = WORD_MNEM_SUFFIX; | |
3995 | break; | |
3996 | } | |
3997 | else if (i.types[op].bitfield.reg32) | |
3998 | { | |
3999 | i.suffix = LONG_MNEM_SUFFIX; | |
4000 | break; | |
4001 | } | |
4002 | else if (i.types[op].bitfield.reg64) | |
4003 | { | |
4004 | i.suffix = QWORD_MNEM_SUFFIX; | |
4005 | break; | |
4006 | } | |
381d071f L |
4007 | } |
4008 | } | |
29b0f896 AM |
4009 | } |
4010 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
4011 | { | |
4012 | if (!check_byte_reg ()) | |
4013 | return 0; | |
4014 | } | |
4015 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4016 | { | |
4017 | if (!check_long_reg ()) | |
4018 | return 0; | |
4019 | } | |
4020 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4021 | { | |
955e1e6a L |
4022 | if (intel_syntax |
4023 | && i.tm.opcode_modifier.ignoresize | |
4024 | && i.tm.opcode_modifier.no_qsuf) | |
4025 | i.suffix = 0; | |
4026 | else if (!check_qword_reg ()) | |
29b0f896 AM |
4027 | return 0; |
4028 | } | |
4029 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4030 | { | |
4031 | if (!check_word_reg ()) | |
4032 | return 0; | |
4033 | } | |
c0f3af97 L |
4034 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
4035 | || i.suffix == YMMWORD_MNEM_SUFFIX) | |
582d5edd | 4036 | { |
c0f3af97 | 4037 | /* Skip if the instruction has x/y suffix. match_template |
582d5edd L |
4038 | should check if it is a valid suffix. */ |
4039 | } | |
40fb9820 | 4040 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
4041 | /* Do nothing if the instruction is going to ignore the prefix. */ |
4042 | ; | |
4043 | else | |
4044 | abort (); | |
4045 | } | |
40fb9820 | 4046 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
4047 | && !i.suffix |
4048 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 4049 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
4050 | { |
4051 | i.suffix = stackop_size; | |
4052 | } | |
9306ca4a JB |
4053 | else if (intel_syntax |
4054 | && !i.suffix | |
40fb9820 L |
4055 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
4056 | || i.tm.opcode_modifier.jumpbyte | |
4057 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
4058 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
4059 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
4060 | { |
4061 | switch (flag_code) | |
4062 | { | |
4063 | case CODE_64BIT: | |
40fb9820 | 4064 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
4065 | { |
4066 | i.suffix = QWORD_MNEM_SUFFIX; | |
4067 | break; | |
4068 | } | |
4069 | case CODE_32BIT: | |
40fb9820 | 4070 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
4071 | i.suffix = LONG_MNEM_SUFFIX; |
4072 | break; | |
4073 | case CODE_16BIT: | |
40fb9820 | 4074 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
4075 | i.suffix = WORD_MNEM_SUFFIX; |
4076 | break; | |
4077 | } | |
4078 | } | |
252b5132 | 4079 | |
9306ca4a | 4080 | if (!i.suffix) |
29b0f896 | 4081 | { |
9306ca4a JB |
4082 | if (!intel_syntax) |
4083 | { | |
40fb9820 | 4084 | if (i.tm.opcode_modifier.w) |
9306ca4a | 4085 | { |
4eed87de AM |
4086 | as_bad (_("no instruction mnemonic suffix given and " |
4087 | "no register operands; can't size instruction")); | |
9306ca4a JB |
4088 | return 0; |
4089 | } | |
4090 | } | |
4091 | else | |
4092 | { | |
40fb9820 L |
4093 | unsigned int suffixes; |
4094 | ||
4095 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
4096 | if (!i.tm.opcode_modifier.no_wsuf) | |
4097 | suffixes |= 1 << 1; | |
4098 | if (!i.tm.opcode_modifier.no_lsuf) | |
4099 | suffixes |= 1 << 2; | |
fc4adea1 | 4100 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
4101 | suffixes |= 1 << 3; |
4102 | if (!i.tm.opcode_modifier.no_ssuf) | |
4103 | suffixes |= 1 << 4; | |
4104 | if (!i.tm.opcode_modifier.no_qsuf) | |
4105 | suffixes |= 1 << 5; | |
4106 | ||
4107 | /* There are more than suffix matches. */ | |
4108 | if (i.tm.opcode_modifier.w | |
9306ca4a | 4109 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
4110 | && !i.tm.opcode_modifier.defaultsize |
4111 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
4112 | { |
4113 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
4114 | return 0; | |
4115 | } | |
4116 | } | |
29b0f896 | 4117 | } |
252b5132 | 4118 | |
9306ca4a JB |
4119 | /* Change the opcode based on the operand size given by i.suffix; |
4120 | We don't need to change things for byte insns. */ | |
4121 | ||
582d5edd L |
4122 | if (i.suffix |
4123 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 L |
4124 | && i.suffix != XMMWORD_MNEM_SUFFIX |
4125 | && i.suffix != YMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
4126 | { |
4127 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 4128 | if (i.tm.opcode_modifier.w) |
29b0f896 | 4129 | { |
40fb9820 | 4130 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
4131 | i.tm.base_opcode |= 8; |
4132 | else | |
4133 | i.tm.base_opcode |= 1; | |
4134 | } | |
0f3f3d8b | 4135 | |
29b0f896 AM |
4136 | /* Now select between word & dword operations via the operand |
4137 | size prefix, except for instructions that will ignore this | |
4138 | prefix anyway. */ | |
ca61edf2 | 4139 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 4140 | { |
ca61edf2 L |
4141 | /* The address size override prefix changes the size of the |
4142 | first operand. */ | |
40fb9820 L |
4143 | if ((flag_code == CODE_32BIT |
4144 | && i.op->regs[0].reg_type.bitfield.reg16) | |
4145 | || (flag_code != CODE_32BIT | |
4146 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
4147 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
4148 | return 0; | |
4149 | } | |
4150 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
4151 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
4152 | && !i.tm.opcode_modifier.ignoresize |
4153 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
4154 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
4155 | || (flag_code == CODE_64BIT | |
40fb9820 | 4156 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
4157 | { |
4158 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 4159 | |
40fb9820 | 4160 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 4161 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 4162 | |
29b0f896 AM |
4163 | if (!add_prefix (prefix)) |
4164 | return 0; | |
24eab124 | 4165 | } |
252b5132 | 4166 | |
29b0f896 AM |
4167 | /* Set mode64 for an operand. */ |
4168 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 4169 | && flag_code == CODE_64BIT |
40fb9820 | 4170 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
4171 | { |
4172 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
4173 | need rex64. cmpxchg8b is also a special case. */ |
4174 | if (! (i.operands == 2 | |
4175 | && i.tm.base_opcode == 0x90 | |
4176 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
4177 | && operand_type_equal (&i.types [0], &acc64) |
4178 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
4179 | && ! (i.operands == 1 |
4180 | && i.tm.base_opcode == 0xfc7 | |
4181 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
4182 | && !operand_type_check (i.types [0], reg) |
4183 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 4184 | i.rex |= REX_W; |
46e883c5 | 4185 | } |
3e73aa7c | 4186 | |
29b0f896 AM |
4187 | /* Size floating point instruction. */ |
4188 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 4189 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 4190 | i.tm.base_opcode ^= 4; |
29b0f896 | 4191 | } |
7ecd2f8b | 4192 | |
29b0f896 AM |
4193 | return 1; |
4194 | } | |
3e73aa7c | 4195 | |
29b0f896 | 4196 | static int |
543613e9 | 4197 | check_byte_reg (void) |
29b0f896 AM |
4198 | { |
4199 | int op; | |
543613e9 | 4200 | |
29b0f896 AM |
4201 | for (op = i.operands; --op >= 0;) |
4202 | { | |
4203 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
4204 | 32 bit version of an eight bit register, we will just use the | |
4205 | low portion, and that's OK too. */ | |
40fb9820 | 4206 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
4207 | continue; |
4208 | ||
ca61edf2 L |
4209 | /* Don't generate this warning if not needed. */ |
4210 | if (intel_syntax && i.tm.opcode_modifier.byteokintel) | |
29b0f896 AM |
4211 | continue; |
4212 | ||
9344ff29 L |
4213 | /* crc32 doesn't generate this warning. */ |
4214 | if (i.tm.base_opcode == 0xf20f38f0) | |
4215 | continue; | |
4216 | ||
40fb9820 L |
4217 | if ((i.types[op].bitfield.reg16 |
4218 | || i.types[op].bitfield.reg32 | |
4219 | || i.types[op].bitfield.reg64) | |
4220 | && i.op[op].regs->reg_num < 4) | |
29b0f896 AM |
4221 | { |
4222 | /* Prohibit these changes in the 64bit mode, since the | |
4223 | lowering is more complicated. */ | |
4224 | if (flag_code == CODE_64BIT | |
40fb9820 | 4225 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
29b0f896 | 4226 | { |
2ca3ace5 L |
4227 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4228 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4229 | i.suffix); |
4230 | return 0; | |
4231 | } | |
4232 | #if REGISTER_WARNINGS | |
4233 | if (!quiet_warnings | |
40fb9820 | 4234 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
a540244d L |
4235 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4236 | register_prefix, | |
40fb9820 | 4237 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
4238 | ? REGNAM_AL - REGNAM_AX |
4239 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 4240 | register_prefix, |
29b0f896 AM |
4241 | i.op[op].regs->reg_name, |
4242 | i.suffix); | |
4243 | #endif | |
4244 | continue; | |
4245 | } | |
4246 | /* Any other register is bad. */ | |
40fb9820 L |
4247 | if (i.types[op].bitfield.reg16 |
4248 | || i.types[op].bitfield.reg32 | |
4249 | || i.types[op].bitfield.reg64 | |
4250 | || i.types[op].bitfield.regmmx | |
4251 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 4252 | || i.types[op].bitfield.regymm |
40fb9820 L |
4253 | || i.types[op].bitfield.sreg2 |
4254 | || i.types[op].bitfield.sreg3 | |
4255 | || i.types[op].bitfield.control | |
4256 | || i.types[op].bitfield.debug | |
4257 | || i.types[op].bitfield.test | |
4258 | || i.types[op].bitfield.floatreg | |
4259 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 4260 | { |
a540244d L |
4261 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4262 | register_prefix, | |
29b0f896 AM |
4263 | i.op[op].regs->reg_name, |
4264 | i.tm.name, | |
4265 | i.suffix); | |
4266 | return 0; | |
4267 | } | |
4268 | } | |
4269 | return 1; | |
4270 | } | |
4271 | ||
4272 | static int | |
e3bb37b5 | 4273 | check_long_reg (void) |
29b0f896 AM |
4274 | { |
4275 | int op; | |
4276 | ||
4277 | for (op = i.operands; --op >= 0;) | |
4278 | /* Reject eight bit registers, except where the template requires | |
4279 | them. (eg. movzb) */ | |
40fb9820 L |
4280 | if (i.types[op].bitfield.reg8 |
4281 | && (i.tm.operand_types[op].bitfield.reg16 | |
4282 | || i.tm.operand_types[op].bitfield.reg32 | |
4283 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4284 | { |
a540244d L |
4285 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4286 | register_prefix, | |
29b0f896 AM |
4287 | i.op[op].regs->reg_name, |
4288 | i.tm.name, | |
4289 | i.suffix); | |
4290 | return 0; | |
4291 | } | |
4292 | /* Warn if the e prefix on a general reg is missing. */ | |
4293 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4294 | && i.types[op].bitfield.reg16 |
4295 | && (i.tm.operand_types[op].bitfield.reg32 | |
4296 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4297 | { |
4298 | /* Prohibit these changes in the 64bit mode, since the | |
4299 | lowering is more complicated. */ | |
4300 | if (flag_code == CODE_64BIT) | |
252b5132 | 4301 | { |
2ca3ace5 L |
4302 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4303 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4304 | i.suffix); |
4305 | return 0; | |
252b5132 | 4306 | } |
29b0f896 AM |
4307 | #if REGISTER_WARNINGS |
4308 | else | |
a540244d L |
4309 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4310 | register_prefix, | |
29b0f896 | 4311 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 4312 | register_prefix, |
29b0f896 AM |
4313 | i.op[op].regs->reg_name, |
4314 | i.suffix); | |
4315 | #endif | |
252b5132 | 4316 | } |
29b0f896 | 4317 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
4318 | else if (i.types[op].bitfield.reg64 |
4319 | && (i.tm.operand_types[op].bitfield.reg32 | |
4320 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4321 | { |
34828aad | 4322 | if (intel_syntax |
ca61edf2 | 4323 | && i.tm.opcode_modifier.toqword |
40fb9820 | 4324 | && !i.types[0].bitfield.regxmm) |
34828aad | 4325 | { |
ca61edf2 | 4326 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
4327 | i.suffix = QWORD_MNEM_SUFFIX; |
4328 | } | |
4329 | else | |
4330 | { | |
4331 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4332 | register_prefix, i.op[op].regs->reg_name, | |
4333 | i.suffix); | |
4334 | return 0; | |
4335 | } | |
29b0f896 AM |
4336 | } |
4337 | return 1; | |
4338 | } | |
252b5132 | 4339 | |
29b0f896 | 4340 | static int |
e3bb37b5 | 4341 | check_qword_reg (void) |
29b0f896 AM |
4342 | { |
4343 | int op; | |
252b5132 | 4344 | |
29b0f896 AM |
4345 | for (op = i.operands; --op >= 0; ) |
4346 | /* Reject eight bit registers, except where the template requires | |
4347 | them. (eg. movzb) */ | |
40fb9820 L |
4348 | if (i.types[op].bitfield.reg8 |
4349 | && (i.tm.operand_types[op].bitfield.reg16 | |
4350 | || i.tm.operand_types[op].bitfield.reg32 | |
4351 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4352 | { |
a540244d L |
4353 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4354 | register_prefix, | |
29b0f896 AM |
4355 | i.op[op].regs->reg_name, |
4356 | i.tm.name, | |
4357 | i.suffix); | |
4358 | return 0; | |
4359 | } | |
4360 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
4361 | else if ((i.types[op].bitfield.reg16 |
4362 | || i.types[op].bitfield.reg32) | |
4363 | && (i.tm.operand_types[op].bitfield.reg32 | |
4364 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4365 | { |
4366 | /* Prohibit these changes in the 64bit mode, since the | |
4367 | lowering is more complicated. */ | |
34828aad | 4368 | if (intel_syntax |
ca61edf2 | 4369 | && i.tm.opcode_modifier.todword |
40fb9820 | 4370 | && !i.types[0].bitfield.regxmm) |
34828aad | 4371 | { |
ca61edf2 | 4372 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
4373 | i.suffix = LONG_MNEM_SUFFIX; |
4374 | } | |
4375 | else | |
4376 | { | |
4377 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4378 | register_prefix, i.op[op].regs->reg_name, | |
4379 | i.suffix); | |
4380 | return 0; | |
4381 | } | |
252b5132 | 4382 | } |
29b0f896 AM |
4383 | return 1; |
4384 | } | |
252b5132 | 4385 | |
29b0f896 | 4386 | static int |
e3bb37b5 | 4387 | check_word_reg (void) |
29b0f896 AM |
4388 | { |
4389 | int op; | |
4390 | for (op = i.operands; --op >= 0;) | |
4391 | /* Reject eight bit registers, except where the template requires | |
4392 | them. (eg. movzb) */ | |
40fb9820 L |
4393 | if (i.types[op].bitfield.reg8 |
4394 | && (i.tm.operand_types[op].bitfield.reg16 | |
4395 | || i.tm.operand_types[op].bitfield.reg32 | |
4396 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4397 | { |
a540244d L |
4398 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4399 | register_prefix, | |
29b0f896 AM |
4400 | i.op[op].regs->reg_name, |
4401 | i.tm.name, | |
4402 | i.suffix); | |
4403 | return 0; | |
4404 | } | |
4405 | /* Warn if the e prefix on a general reg is present. */ | |
4406 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4407 | && i.types[op].bitfield.reg32 |
4408 | && (i.tm.operand_types[op].bitfield.reg16 | |
4409 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4410 | { |
29b0f896 AM |
4411 | /* Prohibit these changes in the 64bit mode, since the |
4412 | lowering is more complicated. */ | |
4413 | if (flag_code == CODE_64BIT) | |
252b5132 | 4414 | { |
2ca3ace5 L |
4415 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4416 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4417 | i.suffix); |
4418 | return 0; | |
252b5132 | 4419 | } |
29b0f896 AM |
4420 | else |
4421 | #if REGISTER_WARNINGS | |
a540244d L |
4422 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4423 | register_prefix, | |
29b0f896 | 4424 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 4425 | register_prefix, |
29b0f896 AM |
4426 | i.op[op].regs->reg_name, |
4427 | i.suffix); | |
4428 | #endif | |
4429 | } | |
4430 | return 1; | |
4431 | } | |
252b5132 | 4432 | |
29b0f896 | 4433 | static int |
40fb9820 | 4434 | update_imm (unsigned int j) |
29b0f896 | 4435 | { |
40fb9820 L |
4436 | i386_operand_type overlap; |
4437 | ||
c6fb90c8 | 4438 | overlap = operand_type_and (i.types[j], i.tm.operand_types[j]); |
40fb9820 L |
4439 | if ((overlap.bitfield.imm8 |
4440 | || overlap.bitfield.imm8s | |
4441 | || overlap.bitfield.imm16 | |
4442 | || overlap.bitfield.imm32 | |
4443 | || overlap.bitfield.imm32s | |
4444 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
4445 | && !operand_type_equal (&overlap, &imm8) |
4446 | && !operand_type_equal (&overlap, &imm8s) | |
4447 | && !operand_type_equal (&overlap, &imm16) | |
4448 | && !operand_type_equal (&overlap, &imm32) | |
4449 | && !operand_type_equal (&overlap, &imm32s) | |
4450 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
4451 | { |
4452 | if (i.suffix) | |
4453 | { | |
40fb9820 L |
4454 | i386_operand_type temp; |
4455 | ||
0dfbf9d7 | 4456 | operand_type_set (&temp, 0); |
40fb9820 L |
4457 | if (i.suffix == BYTE_MNEM_SUFFIX) |
4458 | { | |
4459 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
4460 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
4461 | } | |
4462 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4463 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
4464 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4465 | { | |
4466 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
4467 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
4468 | } | |
4469 | else | |
4470 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
4471 | overlap = temp; | |
29b0f896 | 4472 | } |
0dfbf9d7 L |
4473 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
4474 | || operand_type_equal (&overlap, &imm16_32) | |
4475 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 4476 | { |
40fb9820 | 4477 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 4478 | overlap = imm16; |
40fb9820 | 4479 | else |
65da13b5 | 4480 | overlap = imm32s; |
29b0f896 | 4481 | } |
0dfbf9d7 L |
4482 | if (!operand_type_equal (&overlap, &imm8) |
4483 | && !operand_type_equal (&overlap, &imm8s) | |
4484 | && !operand_type_equal (&overlap, &imm16) | |
4485 | && !operand_type_equal (&overlap, &imm32) | |
4486 | && !operand_type_equal (&overlap, &imm32s) | |
4487 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 4488 | { |
4eed87de AM |
4489 | as_bad (_("no instruction mnemonic suffix given; " |
4490 | "can't determine immediate size")); | |
29b0f896 AM |
4491 | return 0; |
4492 | } | |
4493 | } | |
40fb9820 | 4494 | i.types[j] = overlap; |
29b0f896 | 4495 | |
40fb9820 L |
4496 | return 1; |
4497 | } | |
4498 | ||
4499 | static int | |
4500 | finalize_imm (void) | |
4501 | { | |
4502 | unsigned int j; | |
29b0f896 | 4503 | |
40fb9820 L |
4504 | for (j = 0; j < 2; j++) |
4505 | if (update_imm (j) == 0) | |
4506 | return 0; | |
4507 | ||
c6fb90c8 | 4508 | i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]); |
40fb9820 | 4509 | assert (operand_type_check (i.types[2], imm) == 0); |
29b0f896 AM |
4510 | |
4511 | return 1; | |
4512 | } | |
4513 | ||
85f10a01 MM |
4514 | static void |
4515 | process_drex (void) | |
4516 | { | |
5dd15031 JJ |
4517 | i.drex.modrm_reg = 0; |
4518 | i.drex.modrm_regmem = 0; | |
85f10a01 MM |
4519 | |
4520 | /* SSE5 4 operand instructions must have the destination the same as | |
4521 | one of the inputs. Figure out the destination register and cache | |
4522 | it away in the drex field, and remember which fields to use for | |
4523 | the modrm byte. */ | |
4524 | if (i.tm.opcode_modifier.drex | |
4525 | && i.tm.opcode_modifier.drexv | |
4526 | && i.operands == 4) | |
4527 | { | |
4528 | i.tm.extension_opcode = None; | |
4529 | ||
4530 | /* Case 1: 4 operand insn, dest = src1, src3 = register. */ | |
4531 | if (i.types[0].bitfield.regxmm != 0 | |
4532 | && i.types[1].bitfield.regxmm != 0 | |
4533 | && i.types[2].bitfield.regxmm != 0 | |
4534 | && i.types[3].bitfield.regxmm != 0 | |
4535 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4536 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4537 | { | |
4538 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4539 | operand_type_set (&i.types[0], 0); |
4540 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4541 | i.reg_operands -= 2; |
4542 | ||
4543 | /* There are two different ways to encode a 4 operand | |
4544 | instruction with all registers that uses OC1 set to | |
4545 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4546 | actions of other SSE5 assemblers. Use modrm encoding 2 | |
4547 | for register/register. Include the high order bit that | |
4548 | is normally stored in the REX byte in the register | |
4549 | field. */ | |
4550 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4551 | i.drex.modrm_reg = 2; | |
4552 | i.drex.modrm_regmem = 1; | |
4553 | i.drex.reg = (i.op[3].regs->reg_num | |
4554 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4555 | } | |
4556 | ||
4557 | /* Case 2: 4 operand insn, dest = src1, src3 = memory. */ | |
4558 | else if (i.types[0].bitfield.regxmm != 0 | |
4559 | && i.types[1].bitfield.regxmm != 0 | |
4560 | && (i.types[2].bitfield.regxmm | |
4561 | || operand_type_check (i.types[2], anymem)) | |
4562 | && i.types[3].bitfield.regxmm != 0 | |
4563 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4564 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4565 | { | |
4566 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4567 | operand_type_set (&i.types[0], 0); |
4568 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4569 | i.reg_operands -= 2; |
4570 | ||
4571 | /* Specify the modrm encoding for memory addressing. Include | |
4572 | the high order bit that is normally stored in the REX byte | |
4573 | in the register field. */ | |
4574 | i.tm.extension_opcode = DREX_X1_X2_XMEM_X1; | |
4575 | i.drex.modrm_reg = 1; | |
4576 | i.drex.modrm_regmem = 2; | |
4577 | i.drex.reg = (i.op[3].regs->reg_num | |
4578 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4579 | } | |
4580 | ||
4581 | /* Case 3: 4 operand insn, dest = src1, src2 = memory. */ | |
4582 | else if (i.types[0].bitfield.regxmm != 0 | |
4583 | && operand_type_check (i.types[1], anymem) != 0 | |
4584 | && i.types[2].bitfield.regxmm != 0 | |
4585 | && i.types[3].bitfield.regxmm != 0 | |
4586 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4587 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4588 | { | |
4589 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4590 | operand_type_set (&i.types[0], 0); |
4591 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4592 | i.reg_operands -= 2; |
4593 | ||
4594 | /* Specify the modrm encoding for memory addressing. Include | |
4595 | the high order bit that is normally stored in the REX byte | |
4596 | in the register field. */ | |
4597 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4598 | i.drex.modrm_reg = 2; | |
4599 | i.drex.modrm_regmem = 1; | |
4600 | i.drex.reg = (i.op[3].regs->reg_num | |
4601 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4602 | } | |
4603 | ||
4604 | /* Case 4: 4 operand insn, dest = src3, src2 = register. */ | |
4605 | else if (i.types[0].bitfield.regxmm != 0 | |
4606 | && i.types[1].bitfield.regxmm != 0 | |
4607 | && i.types[2].bitfield.regxmm != 0 | |
4608 | && i.types[3].bitfield.regxmm != 0 | |
4609 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4610 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4611 | { | |
4612 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4613 | operand_type_set (&i.types[2], 0); |
4614 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4615 | i.reg_operands -= 2; |
4616 | ||
4617 | /* There are two different ways to encode a 4 operand | |
4618 | instruction with all registers that uses OC1 set to | |
4619 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4620 | actions of other SSE5 assemblers. Use modrm encoding | |
4621 | 2 for register/register. Include the high order bit that | |
4622 | is normally stored in the REX byte in the register | |
4623 | field. */ | |
4624 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4625 | i.drex.modrm_reg = 1; | |
4626 | i.drex.modrm_regmem = 0; | |
4627 | ||
4628 | /* Remember the register, including the upper bits */ | |
4629 | i.drex.reg = (i.op[3].regs->reg_num | |
4630 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4631 | } | |
4632 | ||
4633 | /* Case 5: 4 operand insn, dest = src3, src2 = memory. */ | |
4634 | else if (i.types[0].bitfield.regxmm != 0 | |
4635 | && (i.types[1].bitfield.regxmm | |
4636 | || operand_type_check (i.types[1], anymem)) | |
4637 | && i.types[2].bitfield.regxmm != 0 | |
4638 | && i.types[3].bitfield.regxmm != 0 | |
4639 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4640 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4641 | { | |
4642 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4643 | operand_type_set (&i.types[2], 0); |
4644 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4645 | i.reg_operands -= 2; |
4646 | ||
4647 | /* Specify the modrm encoding and remember the register | |
4648 | including the bits normally stored in the REX byte. */ | |
4649 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X2; | |
4650 | i.drex.modrm_reg = 0; | |
4651 | i.drex.modrm_regmem = 1; | |
4652 | i.drex.reg = (i.op[3].regs->reg_num | |
4653 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4654 | } | |
4655 | ||
4656 | /* Case 6: 4 operand insn, dest = src3, src1 = memory. */ | |
4657 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4658 | && i.types[1].bitfield.regxmm != 0 | |
4659 | && i.types[2].bitfield.regxmm != 0 | |
4660 | && i.types[3].bitfield.regxmm != 0 | |
4661 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4662 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4663 | { | |
4664 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4665 | operand_type_set (&i.types[2], 0); |
4666 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4667 | i.reg_operands -= 2; |
4668 | ||
4669 | /* Specify the modrm encoding and remember the register | |
4670 | including the bits normally stored in the REX byte. */ | |
4671 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4672 | i.drex.modrm_reg = 1; | |
4673 | i.drex.modrm_regmem = 0; | |
4674 | i.drex.reg = (i.op[3].regs->reg_num | |
4675 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4676 | } | |
4677 | ||
4678 | else | |
4679 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4680 | i.tm.name); | |
4681 | } | |
4682 | ||
4683 | /* SSE5 instructions with the DREX byte where the only memory operand | |
4684 | is in the 2nd argument, and the first and last xmm register must | |
4685 | match, and is encoded in the DREX byte. */ | |
4686 | else if (i.tm.opcode_modifier.drex | |
4687 | && !i.tm.opcode_modifier.drexv | |
4688 | && i.operands == 4) | |
4689 | { | |
4690 | /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */ | |
4691 | if (i.types[0].bitfield.regxmm != 0 | |
4692 | && (i.types[1].bitfield.regxmm | |
4693 | || operand_type_check(i.types[1], anymem)) | |
4694 | && i.types[2].bitfield.regxmm != 0 | |
4695 | && i.types[3].bitfield.regxmm != 0 | |
4696 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4697 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4698 | { | |
4699 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4700 | operand_type_set (&i.types[0], 0); |
4701 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4702 | i.reg_operands -= 2; |
4703 | ||
4704 | /* Specify the modrm encoding and remember the register | |
4705 | including the high bit normally stored in the REX | |
4706 | byte. */ | |
4707 | i.drex.modrm_reg = 2; | |
4708 | i.drex.modrm_regmem = 1; | |
4709 | i.drex.reg = (i.op[3].regs->reg_num | |
4710 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4711 | } | |
4712 | ||
4713 | else | |
4714 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4715 | i.tm.name); | |
4716 | } | |
4717 | ||
4718 | /* SSE5 3 operand instructions that the result is a register, being | |
4719 | either operand can be a memory operand, using OC0 to note which | |
4720 | one is the memory. */ | |
4721 | else if (i.tm.opcode_modifier.drex | |
4722 | && i.tm.opcode_modifier.drexv | |
4723 | && i.operands == 3) | |
4724 | { | |
4725 | i.tm.extension_opcode = None; | |
4726 | ||
4727 | /* Case 1: 3 operand insn, src1 = register. */ | |
4728 | if (i.types[0].bitfield.regxmm != 0 | |
4729 | && i.types[1].bitfield.regxmm != 0 | |
4730 | && i.types[2].bitfield.regxmm != 0) | |
4731 | { | |
4732 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4733 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4734 | i.reg_operands--; |
4735 | ||
4736 | /* Specify the modrm encoding and remember the register | |
4737 | including the high bit normally stored in the REX byte. */ | |
4738 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4739 | i.drex.modrm_reg = 1; | |
4740 | i.drex.modrm_regmem = 0; | |
4741 | i.drex.reg = (i.op[2].regs->reg_num | |
4742 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4743 | } | |
4744 | ||
4745 | /* Case 2: 3 operand insn, src1 = memory. */ | |
4746 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4747 | && i.types[1].bitfield.regxmm != 0 | |
4748 | && i.types[2].bitfield.regxmm != 0) | |
4749 | { | |
4750 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4751 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4752 | i.reg_operands--; |
4753 | ||
4754 | /* Specify the modrm encoding and remember the register | |
4755 | including the high bit normally stored in the REX | |
4756 | byte. */ | |
4757 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4758 | i.drex.modrm_reg = 1; | |
4759 | i.drex.modrm_regmem = 0; | |
4760 | i.drex.reg = (i.op[2].regs->reg_num | |
4761 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4762 | } | |
4763 | ||
4764 | /* Case 3: 3 operand insn, src2 = memory. */ | |
4765 | else if (i.types[0].bitfield.regxmm != 0 | |
4766 | && operand_type_check (i.types[1], anymem) != 0 | |
4767 | && i.types[2].bitfield.regxmm != 0) | |
4768 | { | |
4769 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4770 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4771 | i.reg_operands--; |
4772 | ||
4773 | /* Specify the modrm encoding and remember the register | |
4774 | including the high bit normally stored in the REX byte. */ | |
4775 | i.tm.extension_opcode = DREX_X1_XMEM_X2; | |
4776 | i.drex.modrm_reg = 0; | |
4777 | i.drex.modrm_regmem = 1; | |
4778 | i.drex.reg = (i.op[2].regs->reg_num | |
4779 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4780 | } | |
4781 | ||
4782 | else | |
4783 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4784 | i.tm.name); | |
4785 | } | |
4786 | ||
4787 | /* SSE5 4 operand instructions that are the comparison instructions | |
4788 | where the first operand is the immediate value of the comparison | |
4789 | to be done. */ | |
4790 | else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4) | |
4791 | { | |
4792 | /* Case 1: 4 operand insn, src1 = reg/memory. */ | |
4793 | if (operand_type_check (i.types[0], imm) != 0 | |
4794 | && (i.types[1].bitfield.regxmm | |
4795 | || operand_type_check (i.types[1], anymem)) | |
4796 | && i.types[2].bitfield.regxmm != 0 | |
4797 | && i.types[3].bitfield.regxmm != 0) | |
4798 | { | |
4799 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 | 4800 | operand_type_set (&i.types[3], 0); |
85f10a01 MM |
4801 | i.reg_operands--; |
4802 | ||
4803 | /* Specify the modrm encoding and remember the register | |
4804 | including the high bit normally stored in the REX byte. */ | |
4805 | i.drex.modrm_reg = 2; | |
4806 | i.drex.modrm_regmem = 1; | |
4807 | i.drex.reg = (i.op[3].regs->reg_num | |
4808 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4809 | } | |
4810 | ||
4811 | /* Case 2: 3 operand insn with ImmExt that places the | |
4812 | opcode_extension as an immediate argument. This is used for | |
4813 | all of the varients of comparison that supplies the appropriate | |
4814 | value as part of the instruction. */ | |
4815 | else if ((i.types[0].bitfield.regxmm | |
4816 | || operand_type_check (i.types[0], anymem)) | |
4817 | && i.types[1].bitfield.regxmm != 0 | |
4818 | && i.types[2].bitfield.regxmm != 0 | |
4819 | && operand_type_check (i.types[3], imm) != 0) | |
4820 | { | |
4821 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 | 4822 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4823 | i.reg_operands--; |
4824 | ||
4825 | /* Specify the modrm encoding and remember the register | |
4826 | including the high bit normally stored in the REX byte. */ | |
4827 | i.drex.modrm_reg = 1; | |
4828 | i.drex.modrm_regmem = 0; | |
4829 | i.drex.reg = (i.op[2].regs->reg_num | |
4830 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4831 | } | |
4832 | ||
4833 | else | |
4834 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4835 | i.tm.name); | |
4836 | } | |
4837 | ||
4838 | else if (i.tm.opcode_modifier.drex | |
4839 | || i.tm.opcode_modifier.drexv | |
4840 | || i.tm.opcode_modifier.drexc) | |
4841 | as_bad (_("Internal error for the '%s' instruction"), i.tm.name); | |
4842 | } | |
4843 | ||
c0f3af97 L |
4844 | static int |
4845 | bad_implicit_operand (int xmm) | |
4846 | { | |
4847 | const char *reg = xmm ? "xmm0" : "ymm0"; | |
4848 | if (intel_syntax) | |
4849 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
4850 | i.tm.name, register_prefix, reg); | |
4851 | else | |
4852 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
4853 | i.tm.name, register_prefix, reg); | |
4854 | return 0; | |
4855 | } | |
4856 | ||
29b0f896 | 4857 | static int |
e3bb37b5 | 4858 | process_operands (void) |
29b0f896 AM |
4859 | { |
4860 | /* Default segment register this instruction will use for memory | |
4861 | accesses. 0 means unknown. This is only for optimizing out | |
4862 | unnecessary segment overrides. */ | |
4863 | const seg_entry *default_seg = 0; | |
4864 | ||
85f10a01 MM |
4865 | /* Handle all of the DREX munging that SSE5 needs. */ |
4866 | if (i.tm.opcode_modifier.drex | |
4867 | || i.tm.opcode_modifier.drexv | |
4868 | || i.tm.opcode_modifier.drexc) | |
4869 | process_drex (); | |
4870 | ||
c0f3af97 L |
4871 | if (i.tm.opcode_modifier.sse2avx |
4872 | && (i.tm.opcode_modifier.vexnds | |
4873 | || i.tm.opcode_modifier.vexndd)) | |
29b0f896 | 4874 | { |
c0f3af97 L |
4875 | unsigned int dup = i.operands; |
4876 | unsigned int dest = dup - 1; | |
9fcfb3d7 L |
4877 | unsigned int j; |
4878 | ||
c0f3af97 | 4879 | /* The destination must be an xmm register. */ |
0dfbf9d7 | 4880 | assert (i.reg_operands |
c0f3af97 L |
4881 | && MAX_OPERANDS > dup |
4882 | && operand_type_equal (&i.types[dest], ®xmm)); | |
4883 | ||
4884 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 4885 | { |
c0f3af97 L |
4886 | /* The first operand is implicit and must be xmm0. */ |
4887 | assert (operand_type_equal (&i.types[0], ®xmm)); | |
4888 | if (i.op[0].regs->reg_num != 0) | |
4889 | return bad_implicit_operand (1); | |
4890 | ||
4891 | if (i.tm.opcode_modifier.vex3sources) | |
4892 | { | |
4893 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
4894 | sources. */ | |
4895 | goto duplicate; | |
4896 | } | |
e2ec9d29 | 4897 | else |
c0f3af97 L |
4898 | { |
4899 | /* We remove the first xmm0 and keep the number of | |
4900 | operands unchanged, which in fact duplicates the | |
4901 | destination. */ | |
4902 | for (j = 1; j < i.operands; j++) | |
4903 | { | |
4904 | i.op[j - 1] = i.op[j]; | |
4905 | i.types[j - 1] = i.types[j]; | |
4906 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
4907 | } | |
4908 | } | |
4909 | } | |
4910 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
4911 | { | |
4912 | assert ((MAX_OPERANDS - 1) > dup | |
4913 | && i.tm.opcode_modifier.vex3sources); | |
4914 | ||
4915 | /* Add the implicit xmm0 for instructions with VEX prefix | |
4916 | and 3 sources. */ | |
4917 | for (j = i.operands; j > 0; j--) | |
4918 | { | |
4919 | i.op[j] = i.op[j - 1]; | |
4920 | i.types[j] = i.types[j - 1]; | |
4921 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
4922 | } | |
4923 | i.op[0].regs | |
4924 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
4925 | i.types[0] = regxmm; | |
4926 | i.tm.operand_types[0] = regxmm; | |
4927 | ||
4928 | i.operands += 2; | |
4929 | i.reg_operands += 2; | |
4930 | i.tm.operands += 2; | |
4931 | ||
4932 | dup++; | |
4933 | dest++; | |
4934 | i.op[dup] = i.op[dest]; | |
4935 | i.types[dup] = i.types[dest]; | |
4936 | i.tm.operand_types[dup] = i.tm.operand_types[dest]; | |
e2ec9d29 | 4937 | } |
c0f3af97 L |
4938 | else |
4939 | { | |
4940 | duplicate: | |
4941 | i.operands++; | |
4942 | i.reg_operands++; | |
4943 | i.tm.operands++; | |
4944 | ||
4945 | i.op[dup] = i.op[dest]; | |
4946 | i.types[dup] = i.types[dest]; | |
4947 | i.tm.operand_types[dup] = i.tm.operand_types[dest]; | |
4948 | } | |
4949 | ||
4950 | if (i.tm.opcode_modifier.immext) | |
4951 | process_immext (); | |
4952 | } | |
4953 | else if (i.tm.opcode_modifier.firstxmm0) | |
4954 | { | |
4955 | unsigned int j; | |
4956 | ||
4957 | /* The first operand is implicit and must be xmm0/ymm0. */ | |
4958 | assert (i.reg_operands | |
4959 | && (operand_type_equal (&i.types[0], ®xmm) | |
4960 | || operand_type_equal (&i.types[0], ®ymm))); | |
4961 | if (i.op[0].regs->reg_num != 0) | |
4962 | return bad_implicit_operand (i.types[0].bitfield.regxmm); | |
9fcfb3d7 L |
4963 | |
4964 | for (j = 1; j < i.operands; j++) | |
4965 | { | |
4966 | i.op[j - 1] = i.op[j]; | |
4967 | i.types[j - 1] = i.types[j]; | |
4968 | ||
4969 | /* We need to adjust fields in i.tm since they are used by | |
4970 | build_modrm_byte. */ | |
4971 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
4972 | } | |
4973 | ||
e2ec9d29 L |
4974 | i.operands--; |
4975 | i.reg_operands--; | |
e2ec9d29 L |
4976 | i.tm.operands--; |
4977 | } | |
4978 | else if (i.tm.opcode_modifier.regkludge) | |
4979 | { | |
4980 | /* The imul $imm, %reg instruction is converted into | |
4981 | imul $imm, %reg, %reg, and the clr %reg instruction | |
4982 | is converted into xor %reg, %reg. */ | |
4983 | ||
4984 | unsigned int first_reg_op; | |
4985 | ||
4986 | if (operand_type_check (i.types[0], reg)) | |
4987 | first_reg_op = 0; | |
4988 | else | |
4989 | first_reg_op = 1; | |
4990 | /* Pretend we saw the extra register operand. */ | |
4991 | assert (i.reg_operands == 1 | |
4992 | && i.op[first_reg_op + 1].regs == 0); | |
4993 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
4994 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
4995 | i.operands++; | |
4996 | i.reg_operands++; | |
29b0f896 AM |
4997 | } |
4998 | ||
40fb9820 | 4999 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 5000 | { |
40fb9820 L |
5001 | if (i.types[0].bitfield.sreg2 |
5002 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 5003 | { |
4eed87de AM |
5004 | if (i.tm.base_opcode == POP_SEG_SHORT |
5005 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 5006 | { |
a87af027 | 5007 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 5008 | return 0; |
29b0f896 | 5009 | } |
4eed87de AM |
5010 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
5011 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5012 | i.rex |= REX_B; |
4eed87de AM |
5013 | } |
5014 | else | |
5015 | { | |
85f10a01 MM |
5016 | /* The register or float register operand is in operand |
5017 | 0 or 1. */ | |
40fb9820 L |
5018 | unsigned int op; |
5019 | ||
5020 | if (i.types[0].bitfield.floatreg | |
5021 | || operand_type_check (i.types[0], reg)) | |
5022 | op = 0; | |
5023 | else | |
5024 | op = 1; | |
4eed87de AM |
5025 | /* Register goes in low 3 bits of opcode. */ |
5026 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
5027 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5028 | i.rex |= REX_B; |
40fb9820 | 5029 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 5030 | { |
4eed87de AM |
5031 | /* Warn about some common errors, but press on regardless. |
5032 | The first case can be generated by gcc (<= 2.8.1). */ | |
5033 | if (i.operands == 2) | |
5034 | { | |
5035 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d L |
5036 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
5037 | register_prefix, i.op[1].regs->reg_name, | |
5038 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de AM |
5039 | } |
5040 | else | |
5041 | { | |
5042 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
5043 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
5044 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 5045 | } |
29b0f896 AM |
5046 | } |
5047 | } | |
5048 | } | |
40fb9820 | 5049 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
5050 | { |
5051 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
5052 | must be put into the modrm byte). Now, we make the modrm and |
5053 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
5054 | |
5055 | default_seg = build_modrm_byte (); | |
5056 | } | |
8a2ed489 | 5057 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
5058 | { |
5059 | default_seg = &ds; | |
5060 | } | |
40fb9820 | 5061 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
5062 | { |
5063 | /* For the string instructions that allow a segment override | |
5064 | on one of their operands, the default segment is ds. */ | |
5065 | default_seg = &ds; | |
5066 | } | |
5067 | ||
75178d9d L |
5068 | if (i.tm.base_opcode == 0x8d /* lea */ |
5069 | && i.seg[0] | |
5070 | && !quiet_warnings) | |
30123838 | 5071 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
5072 | |
5073 | /* If a segment was explicitly specified, and the specified segment | |
5074 | is not the default, use an opcode prefix to select it. If we | |
5075 | never figured out what the default segment is, then default_seg | |
5076 | will be zero at this point, and the specified segment prefix will | |
5077 | always be used. */ | |
29b0f896 AM |
5078 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
5079 | { | |
5080 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
5081 | return 0; | |
5082 | } | |
5083 | return 1; | |
5084 | } | |
5085 | ||
5086 | static const seg_entry * | |
e3bb37b5 | 5087 | build_modrm_byte (void) |
29b0f896 AM |
5088 | { |
5089 | const seg_entry *default_seg = 0; | |
c0f3af97 L |
5090 | unsigned int source, dest; |
5091 | int vex_3_sources; | |
5092 | ||
5093 | /* The first operand of instructions with VEX prefix and 3 sources | |
5094 | must be VEX_Imm4. */ | |
5095 | vex_3_sources = i.tm.opcode_modifier.vex3sources; | |
5096 | if (vex_3_sources) | |
5097 | { | |
5098 | unsigned int nds, reg; | |
5099 | ||
5100 | if (i.tm.opcode_modifier.veximmext | |
5101 | && i.tm.opcode_modifier.immext) | |
5102 | { | |
5103 | dest = i.operands - 2; | |
5104 | assert (dest == 3); | |
5105 | } | |
5106 | else | |
5107 | dest = i.operands - 1; | |
5108 | nds = dest - 1; | |
5109 | ||
5110 | /* There are 2 kinds of instructions: | |
dae39acc | 5111 | 1. 5 operands: one immediate operand and 4 register |
c0f3af97 L |
5112 | operands or 3 register operands plus 1 memory operand. |
5113 | It must have VexNDS and VexW0 or VexW1. The destination | |
5114 | must be either XMM or YMM register. | |
5115 | 2. 4 operands: 4 register operands or 3 register operands | |
5116 | plus 1 memory operand. It must have VexNDS and VexImmExt. */ | |
5117 | if (!((i.reg_operands == 4 | |
5118 | || (i.reg_operands == 3 && i.mem_operands == 1)) | |
5119 | && i.tm.opcode_modifier.vexnds | |
5120 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) | |
5121 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm)) | |
c0f3af97 L |
5122 | && ((dest == 4 |
5123 | && i.imm_operands == 1 | |
5124 | && i.types[0].bitfield.vex_imm4 | |
5125 | && (i.tm.opcode_modifier.vexw0 | |
5126 | || i.tm.opcode_modifier.vexw1)) | |
5127 | || (dest == 3 | |
5128 | && (i.imm_operands == 0 | |
5129 | || (i.imm_operands == 1 | |
5130 | && i.tm.opcode_modifier.immext)) | |
5131 | && i.tm.opcode_modifier.veximmext)))) | |
5132 | abort (); | |
5133 | ||
c0f3af97 L |
5134 | if (i.imm_operands == 0) |
5135 | { | |
5136 | /* When there is no immediate operand, generate an 8bit | |
5137 | immediate operand to encode the first operand. */ | |
5138 | expressionS *exp = &im_expressions[i.imm_operands++]; | |
5139 | i.op[i.operands].imms = exp; | |
5140 | i.types[i.operands] = imm8; | |
5141 | i.operands++; | |
5142 | /* If VexW1 is set, the first operand is the source and | |
5143 | the second operand is encoded in the immediate operand. */ | |
5144 | if (i.tm.opcode_modifier.vexw1) | |
5145 | { | |
5146 | source = 0; | |
5147 | reg = 1; | |
5148 | } | |
5149 | else | |
5150 | { | |
5151 | source = 1; | |
5152 | reg = 0; | |
5153 | } | |
dae39acc L |
5154 | |
5155 | /* FMA swaps REG and NDS. */ | |
5156 | if (i.tm.cpu_flags.bitfield.cpufma) | |
5157 | { | |
5158 | unsigned int tmp; | |
5159 | tmp = reg; | |
5160 | reg = nds; | |
5161 | nds = tmp; | |
5162 | } | |
5163 | ||
c0f3af97 L |
5164 | assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm) |
5165 | || operand_type_equal (&i.tm.operand_types[reg], | |
5166 | ®ymm)); | |
5167 | exp->X_op = O_constant; | |
5168 | exp->X_add_number | |
5169 | = ((i.op[reg].regs->reg_num | |
5170 | + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4); | |
5171 | } | |
5172 | else | |
5173 | { | |
5174 | unsigned int imm; | |
5175 | ||
5176 | if (i.tm.opcode_modifier.vexw0) | |
5177 | { | |
5178 | /* If VexW0 is set, the third operand is the source and | |
5179 | the second operand is encoded in the immediate | |
5180 | operand. */ | |
5181 | source = 2; | |
5182 | reg = 1; | |
5183 | } | |
5184 | else | |
5185 | { | |
5186 | /* VexW1 is set, the second operand is the source and | |
5187 | the third operand is encoded in the immediate | |
5188 | operand. */ | |
5189 | source = 1; | |
5190 | reg = 2; | |
5191 | } | |
5192 | ||
5193 | if (i.tm.opcode_modifier.immext) | |
5194 | { | |
5195 | /* When ImmExt is set, the immdiate byte is the last | |
5196 | operand. */ | |
5197 | imm = i.operands - 1; | |
5198 | source--; | |
5199 | reg--; | |
5200 | } | |
5201 | else | |
5202 | { | |
5203 | imm = 0; | |
5204 | ||
5205 | /* Turn on Imm8 so that output_imm will generate it. */ | |
5206 | i.types[imm].bitfield.imm8 = 1; | |
5207 | } | |
5208 | ||
5209 | assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm) | |
5210 | || operand_type_equal (&i.tm.operand_types[reg], | |
5211 | ®ymm)); | |
5212 | i.op[imm].imms->X_add_number | |
5213 | |= ((i.op[reg].regs->reg_num | |
5214 | + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4); | |
5215 | } | |
dae39acc L |
5216 | |
5217 | assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
5218 | || operand_type_equal (&i.tm.operand_types[nds], ®ymm)); | |
5219 | i.vex.register_specifier = i.op[nds].regs; | |
5220 | ||
c0f3af97 L |
5221 | } |
5222 | else | |
5223 | source = dest = 0; | |
29b0f896 | 5224 | |
85f10a01 MM |
5225 | /* SSE5 4 operand instructions are encoded in such a way that one of |
5226 | the inputs must match the destination register. Process_drex hides | |
5227 | the 3rd argument in the drex field, so that by the time we get | |
5228 | here, it looks to GAS as if this is a 2 operand instruction. */ | |
5229 | if ((i.tm.opcode_modifier.drex | |
5230 | || i.tm.opcode_modifier.drexv | |
b5016f89 | 5231 | || i.tm.opcode_modifier.drexc) |
85f10a01 MM |
5232 | && i.reg_operands == 2) |
5233 | { | |
5234 | const reg_entry *reg = i.op[i.drex.modrm_reg].regs; | |
5235 | const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs; | |
5236 | ||
5237 | i.rm.reg = reg->reg_num; | |
5238 | i.rm.regmem = regmem->reg_num; | |
5239 | i.rm.mode = 3; | |
5240 | if ((reg->reg_flags & RegRex) != 0) | |
5241 | i.rex |= REX_R; | |
5242 | if ((regmem->reg_flags & RegRex) != 0) | |
5243 | i.rex |= REX_B; | |
5244 | } | |
5245 | ||
29b0f896 | 5246 | /* i.reg_operands MUST be the number of real register operands; |
c0f3af97 L |
5247 | implicit registers do not count. If there are 3 register |
5248 | operands, it must be a instruction with VexNDS. For a | |
5249 | instruction with VexNDD, the destination register is encoded | |
5250 | in VEX prefix. If there are 4 register operands, it must be | |
5251 | a instruction with VEX prefix and 3 sources. */ | |
5252 | else if (i.mem_operands == 0 | |
5253 | && ((i.reg_operands == 2 | |
5254 | && !i.tm.opcode_modifier.vexndd) | |
5255 | || (i.reg_operands == 3 | |
5256 | && i.tm.opcode_modifier.vexnds) | |
5257 | || (i.reg_operands == 4 && vex_3_sources))) | |
29b0f896 | 5258 | { |
cab737b9 L |
5259 | switch (i.operands) |
5260 | { | |
5261 | case 2: | |
5262 | source = 0; | |
5263 | break; | |
5264 | case 3: | |
c81128dc L |
5265 | /* When there are 3 operands, one of them may be immediate, |
5266 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
5267 | the first operand must be shift count register (cl) or it |
5268 | is an instruction with VexNDS. */ | |
c81128dc L |
5269 | assert (i.imm_operands == 1 |
5270 | || (i.imm_operands == 0 | |
c0f3af97 L |
5271 | && (i.tm.opcode_modifier.vexnds |
5272 | || i.types[0].bitfield.shiftcount))); | |
40fb9820 L |
5273 | if (operand_type_check (i.types[0], imm) |
5274 | || i.types[0].bitfield.shiftcount) | |
5275 | source = 1; | |
5276 | else | |
5277 | source = 0; | |
cab737b9 L |
5278 | break; |
5279 | case 4: | |
368d64cc L |
5280 | /* When there are 4 operands, the first two must be 8bit |
5281 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
5282 | one. |
5283 | ||
5284 | For instructions with VexNDS, if the first operand | |
5285 | an imm8, the source operand is the 2nd one. If the last | |
5286 | operand is imm8, the source operand is the first one. */ | |
5287 | assert ((i.imm_operands == 2 | |
5288 | && i.types[0].bitfield.imm8 | |
5289 | && i.types[1].bitfield.imm8) | |
5290 | || (i.tm.opcode_modifier.vexnds | |
5291 | && i.imm_operands == 1 | |
5292 | && (i.types[0].bitfield.imm8 | |
5293 | || i.types[i.operands - 1].bitfield.imm8))); | |
5294 | if (i.tm.opcode_modifier.vexnds) | |
5295 | { | |
5296 | if (i.types[0].bitfield.imm8) | |
5297 | source = 1; | |
5298 | else | |
5299 | source = 0; | |
5300 | } | |
5301 | else | |
5302 | source = 2; | |
5303 | break; | |
5304 | case 5: | |
cab737b9 L |
5305 | break; |
5306 | default: | |
5307 | abort (); | |
5308 | } | |
5309 | ||
c0f3af97 L |
5310 | if (!vex_3_sources) |
5311 | { | |
5312 | dest = source + 1; | |
5313 | ||
5314 | if (i.tm.opcode_modifier.vexnds) | |
5315 | { | |
5316 | /* For instructions with VexNDS, the register-only | |
5317 | source operand must be XMM or YMM register. It is | |
5318 | encoded in VEX prefix. */ | |
5319 | if ((dest + 1) >= i.operands | |
5320 | || (!operand_type_equal (&i.tm.operand_types[dest], | |
5321 | ®xmm) | |
5322 | && !operand_type_equal (&i.tm.operand_types[dest], | |
5323 | ®ymm))) | |
5324 | abort (); | |
5325 | i.vex.register_specifier = i.op[dest].regs; | |
5326 | dest++; | |
5327 | } | |
5328 | } | |
29b0f896 AM |
5329 | |
5330 | i.rm.mode = 3; | |
5331 | /* One of the register operands will be encoded in the i.tm.reg | |
5332 | field, the other in the combined i.tm.mode and i.tm.regmem | |
5333 | fields. If no form of this instruction supports a memory | |
5334 | destination operand, then we assume the source operand may | |
5335 | sometimes be a memory operand and so we need to store the | |
5336 | destination in the i.rm.reg field. */ | |
40fb9820 L |
5337 | if (!i.tm.operand_types[dest].bitfield.regmem |
5338 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
5339 | { |
5340 | i.rm.reg = i.op[dest].regs->reg_num; | |
5341 | i.rm.regmem = i.op[source].regs->reg_num; | |
5342 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5343 | i.rex |= REX_R; |
29b0f896 | 5344 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5345 | i.rex |= REX_B; |
29b0f896 AM |
5346 | } |
5347 | else | |
5348 | { | |
5349 | i.rm.reg = i.op[source].regs->reg_num; | |
5350 | i.rm.regmem = i.op[dest].regs->reg_num; | |
5351 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5352 | i.rex |= REX_B; |
29b0f896 | 5353 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5354 | i.rex |= REX_R; |
29b0f896 | 5355 | } |
161a04f6 | 5356 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 5357 | { |
40fb9820 L |
5358 | if (!i.types[0].bitfield.control |
5359 | && !i.types[1].bitfield.control) | |
c4a530c5 | 5360 | abort (); |
161a04f6 | 5361 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
5362 | add_prefix (LOCK_PREFIX_OPCODE); |
5363 | } | |
29b0f896 AM |
5364 | } |
5365 | else | |
5366 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
5367 | unsigned int mem; |
5368 | ||
29b0f896 AM |
5369 | if (i.mem_operands) |
5370 | { | |
5371 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 5372 | unsigned int op; |
4eed87de | 5373 | |
85f10a01 MM |
5374 | /* This has been precalculated for SSE5 instructions |
5375 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
5376 | if (i.tm.opcode_modifier.drex |
5377 | || i.tm.opcode_modifier.drexv | |
5378 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
5379 | op = i.drex.modrm_regmem; |
5380 | else | |
5381 | { | |
c0209578 L |
5382 | for (op = 0; op < i.operands; op++) |
5383 | if (operand_type_check (i.types[op], anymem)) | |
5384 | break; | |
5385 | assert (op < i.operands); | |
85f10a01 | 5386 | } |
29b0f896 AM |
5387 | |
5388 | default_seg = &ds; | |
5389 | ||
5390 | if (i.base_reg == 0) | |
5391 | { | |
5392 | i.rm.mode = 0; | |
5393 | if (!i.disp_operands) | |
5394 | fake_zero_displacement = 1; | |
5395 | if (i.index_reg == 0) | |
5396 | { | |
5397 | /* Operand is just <disp> */ | |
20f0a1fc | 5398 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
5399 | { |
5400 | /* 64bit mode overwrites the 32bit absolute | |
5401 | addressing by RIP relative addressing and | |
5402 | absolute addressing is encoded by one of the | |
5403 | redundant SIB forms. */ | |
5404 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5405 | i.sib.base = NO_BASE_REGISTER; | |
5406 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 5407 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 5408 | ? disp32s : disp32); |
20f0a1fc | 5409 | } |
fc225355 L |
5410 | else if ((flag_code == CODE_16BIT) |
5411 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
5412 | { |
5413 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 5414 | i.types[op] = disp16; |
20f0a1fc NC |
5415 | } |
5416 | else | |
5417 | { | |
5418 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 5419 | i.types[op] = disp32; |
29b0f896 AM |
5420 | } |
5421 | } | |
5422 | else /* !i.base_reg && i.index_reg */ | |
5423 | { | |
db51cc60 L |
5424 | if (i.index_reg->reg_num == RegEiz |
5425 | || i.index_reg->reg_num == RegRiz) | |
5426 | i.sib.index = NO_INDEX_REGISTER; | |
5427 | else | |
5428 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5429 | i.sib.base = NO_BASE_REGISTER; |
5430 | i.sib.scale = i.log2_scale_factor; | |
5431 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
5432 | i.types[op].bitfield.disp8 = 0; |
5433 | i.types[op].bitfield.disp16 = 0; | |
5434 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 5435 | if (flag_code != CODE_64BIT) |
40fb9820 L |
5436 | { |
5437 | /* Must be 32 bit */ | |
5438 | i.types[op].bitfield.disp32 = 1; | |
5439 | i.types[op].bitfield.disp32s = 0; | |
5440 | } | |
29b0f896 | 5441 | else |
40fb9820 L |
5442 | { |
5443 | i.types[op].bitfield.disp32 = 0; | |
5444 | i.types[op].bitfield.disp32s = 1; | |
5445 | } | |
29b0f896 | 5446 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5447 | i.rex |= REX_X; |
29b0f896 AM |
5448 | } |
5449 | } | |
5450 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
5451 | else if (i.base_reg->reg_num == RegRip || |
5452 | i.base_reg->reg_num == RegEip) | |
29b0f896 AM |
5453 | { |
5454 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 L |
5455 | i.types[op].bitfield.disp8 = 0; |
5456 | i.types[op].bitfield.disp16 = 0; | |
5457 | i.types[op].bitfield.disp32 = 0; | |
5458 | i.types[op].bitfield.disp32s = 1; | |
5459 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 5460 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
5461 | if (! i.disp_operands) |
5462 | fake_zero_displacement = 1; | |
29b0f896 | 5463 | } |
40fb9820 | 5464 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 AM |
5465 | { |
5466 | switch (i.base_reg->reg_num) | |
5467 | { | |
5468 | case 3: /* (%bx) */ | |
5469 | if (i.index_reg == 0) | |
5470 | i.rm.regmem = 7; | |
5471 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
5472 | i.rm.regmem = i.index_reg->reg_num - 6; | |
5473 | break; | |
5474 | case 5: /* (%bp) */ | |
5475 | default_seg = &ss; | |
5476 | if (i.index_reg == 0) | |
5477 | { | |
5478 | i.rm.regmem = 6; | |
40fb9820 | 5479 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
5480 | { |
5481 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 5482 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5483 | fake_zero_displacement = 1; |
29b0f896 AM |
5484 | } |
5485 | } | |
5486 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
5487 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
5488 | break; | |
5489 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
5490 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
5491 | } | |
5492 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5493 | } | |
5494 | else /* i.base_reg and 32/64 bit mode */ | |
5495 | { | |
5496 | if (flag_code == CODE_64BIT | |
40fb9820 L |
5497 | && operand_type_check (i.types[op], disp)) |
5498 | { | |
5499 | i386_operand_type temp; | |
0dfbf9d7 | 5500 | operand_type_set (&temp, 0); |
40fb9820 L |
5501 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
5502 | i.types[op] = temp; | |
5503 | if (i.prefix[ADDR_PREFIX] == 0) | |
5504 | i.types[op].bitfield.disp32s = 1; | |
5505 | else | |
5506 | i.types[op].bitfield.disp32 = 1; | |
5507 | } | |
20f0a1fc | 5508 | |
29b0f896 AM |
5509 | i.rm.regmem = i.base_reg->reg_num; |
5510 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5511 | i.rex |= REX_B; |
29b0f896 AM |
5512 | i.sib.base = i.base_reg->reg_num; |
5513 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
5514 | complications. */ | |
5515 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
5516 | { | |
5517 | default_seg = &ss; | |
5518 | if (i.disp_operands == 0) | |
5519 | { | |
5520 | fake_zero_displacement = 1; | |
40fb9820 | 5521 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
5522 | } |
5523 | } | |
5524 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
5525 | { | |
5526 | default_seg = &ss; | |
5527 | } | |
5528 | i.sib.scale = i.log2_scale_factor; | |
5529 | if (i.index_reg == 0) | |
5530 | { | |
5531 | /* <disp>(%esp) becomes two byte modrm with no index | |
5532 | register. We've already stored the code for esp | |
5533 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
5534 | Any base register besides %esp will not use the | |
5535 | extra modrm byte. */ | |
5536 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 AM |
5537 | } |
5538 | else | |
5539 | { | |
db51cc60 L |
5540 | if (i.index_reg->reg_num == RegEiz |
5541 | || i.index_reg->reg_num == RegRiz) | |
5542 | i.sib.index = NO_INDEX_REGISTER; | |
5543 | else | |
5544 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5545 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
5546 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5547 | i.rex |= REX_X; |
29b0f896 | 5548 | } |
67a4f2b7 AO |
5549 | |
5550 | if (i.disp_operands | |
5551 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
5552 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
5553 | i.rm.mode = 0; | |
5554 | else | |
5555 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
29b0f896 | 5556 | } |
252b5132 | 5557 | |
29b0f896 AM |
5558 | if (fake_zero_displacement) |
5559 | { | |
5560 | /* Fakes a zero displacement assuming that i.types[op] | |
5561 | holds the correct displacement size. */ | |
5562 | expressionS *exp; | |
5563 | ||
5564 | assert (i.op[op].disps == 0); | |
5565 | exp = &disp_expressions[i.disp_operands++]; | |
5566 | i.op[op].disps = exp; | |
5567 | exp->X_op = O_constant; | |
5568 | exp->X_add_number = 0; | |
5569 | exp->X_add_symbol = (symbolS *) 0; | |
5570 | exp->X_op_symbol = (symbolS *) 0; | |
5571 | } | |
c0f3af97 L |
5572 | |
5573 | mem = op; | |
29b0f896 | 5574 | } |
c0f3af97 L |
5575 | else |
5576 | mem = ~0; | |
252b5132 | 5577 | |
29b0f896 AM |
5578 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
5579 | (if any) based on i.tm.extension_opcode. Again, we must be | |
5580 | careful to make sure that segment/control/debug/test/MMX | |
5581 | registers are coded into the i.rm.reg field. */ | |
5582 | if (i.reg_operands) | |
5583 | { | |
99018f42 L |
5584 | unsigned int op; |
5585 | ||
85f10a01 MM |
5586 | /* This has been precalculated for SSE5 instructions |
5587 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
5588 | if (i.tm.opcode_modifier.drex |
5589 | || i.tm.opcode_modifier.drexv | |
5590 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
5591 | { |
5592 | op = i.drex.modrm_reg; | |
5593 | i.rm.reg = i.op[op].regs->reg_num; | |
5594 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5595 | i.rex |= REX_R; | |
5596 | } | |
5597 | else | |
5598 | { | |
c0f3af97 L |
5599 | unsigned int vex_reg = ~0; |
5600 | ||
c0209578 L |
5601 | for (op = 0; op < i.operands; op++) |
5602 | if (i.types[op].bitfield.reg8 | |
5603 | || i.types[op].bitfield.reg16 | |
5604 | || i.types[op].bitfield.reg32 | |
5605 | || i.types[op].bitfield.reg64 | |
5606 | || i.types[op].bitfield.regmmx | |
5607 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 5608 | || i.types[op].bitfield.regymm |
c0209578 L |
5609 | || i.types[op].bitfield.sreg2 |
5610 | || i.types[op].bitfield.sreg3 | |
5611 | || i.types[op].bitfield.control | |
5612 | || i.types[op].bitfield.debug | |
5613 | || i.types[op].bitfield.test) | |
5614 | break; | |
5615 | ||
c0f3af97 L |
5616 | if (vex_3_sources) |
5617 | op = dest; | |
5618 | else if (i.tm.opcode_modifier.vexnds) | |
5619 | { | |
5620 | /* For instructions with VexNDS, the register-only | |
5621 | source operand is encoded in VEX prefix. */ | |
5622 | assert (mem != (unsigned int) ~0); | |
5623 | ||
5624 | if (op > mem) | |
5625 | { | |
5626 | vex_reg = op++; | |
5627 | assert (op < i.operands); | |
5628 | } | |
5629 | else | |
5630 | { | |
5631 | vex_reg = op + 1; | |
5632 | assert (vex_reg < i.operands); | |
5633 | } | |
5634 | } | |
5635 | else if (i.tm.opcode_modifier.vexndd) | |
5636 | { | |
5637 | /* For instructions with VexNDD, there should be | |
5638 | no memory operand and the register destination | |
5639 | is encoded in VEX prefix. */ | |
5640 | assert (i.mem_operands == 0 | |
5641 | && (op + 2) == i.operands); | |
5642 | vex_reg = op + 1; | |
5643 | } | |
5644 | else | |
5645 | assert (op < i.operands); | |
5646 | ||
5647 | if (vex_reg != (unsigned int) ~0) | |
5648 | { | |
5649 | assert (i.reg_operands == 2); | |
5650 | ||
5651 | if (!operand_type_equal (&i.tm.operand_types[vex_reg], | |
5652 | & regxmm) | |
5653 | && !operand_type_equal (&i.tm.operand_types[vex_reg], | |
5654 | ®ymm)) | |
5655 | abort (); | |
5656 | i.vex.register_specifier = i.op[vex_reg].regs; | |
5657 | } | |
99018f42 | 5658 | |
85f10a01 MM |
5659 | /* If there is an extension opcode to put here, the |
5660 | register number must be put into the regmem field. */ | |
c0209578 L |
5661 | if (i.tm.extension_opcode != None) |
5662 | { | |
5663 | i.rm.regmem = i.op[op].regs->reg_num; | |
5664 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5665 | i.rex |= REX_B; | |
5666 | } | |
5667 | else | |
5668 | { | |
5669 | i.rm.reg = i.op[op].regs->reg_num; | |
5670 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5671 | i.rex |= REX_R; | |
5672 | } | |
85f10a01 | 5673 | } |
252b5132 | 5674 | |
29b0f896 AM |
5675 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
5676 | must set it to 3 to indicate this is a register operand | |
5677 | in the regmem field. */ | |
5678 | if (!i.mem_operands) | |
5679 | i.rm.mode = 3; | |
5680 | } | |
252b5132 | 5681 | |
29b0f896 | 5682 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
85f10a01 MM |
5683 | if (i.tm.extension_opcode != None |
5684 | && !(i.tm.opcode_modifier.drex | |
5685 | || i.tm.opcode_modifier.drexv | |
5686 | || i.tm.opcode_modifier.drexc)) | |
29b0f896 AM |
5687 | i.rm.reg = i.tm.extension_opcode; |
5688 | } | |
5689 | return default_seg; | |
5690 | } | |
252b5132 | 5691 | |
29b0f896 | 5692 | static void |
e3bb37b5 | 5693 | output_branch (void) |
29b0f896 AM |
5694 | { |
5695 | char *p; | |
5696 | int code16; | |
5697 | int prefix; | |
5698 | relax_substateT subtype; | |
5699 | symbolS *sym; | |
5700 | offsetT off; | |
5701 | ||
5702 | code16 = 0; | |
5703 | if (flag_code == CODE_16BIT) | |
5704 | code16 = CODE16; | |
5705 | ||
5706 | prefix = 0; | |
5707 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 5708 | { |
29b0f896 AM |
5709 | prefix = 1; |
5710 | i.prefixes -= 1; | |
5711 | code16 ^= CODE16; | |
252b5132 | 5712 | } |
29b0f896 AM |
5713 | /* Pentium4 branch hints. */ |
5714 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5715 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 5716 | { |
29b0f896 AM |
5717 | prefix++; |
5718 | i.prefixes--; | |
5719 | } | |
5720 | if (i.prefix[REX_PREFIX] != 0) | |
5721 | { | |
5722 | prefix++; | |
5723 | i.prefixes--; | |
2f66722d AM |
5724 | } |
5725 | ||
29b0f896 AM |
5726 | if (i.prefixes != 0 && !intel_syntax) |
5727 | as_warn (_("skipping prefixes on this instruction")); | |
5728 | ||
5729 | /* It's always a symbol; End frag & setup for relax. | |
5730 | Make sure there is enough room in this frag for the largest | |
5731 | instruction we may generate in md_convert_frag. This is 2 | |
5732 | bytes for the opcode and room for the prefix and largest | |
5733 | displacement. */ | |
5734 | frag_grow (prefix + 2 + 4); | |
5735 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
5736 | p = frag_more (prefix + 1); | |
5737 | if (i.prefix[DATA_PREFIX] != 0) | |
5738 | *p++ = DATA_PREFIX_OPCODE; | |
5739 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
5740 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
5741 | *p++ = i.prefix[SEG_PREFIX]; | |
5742 | if (i.prefix[REX_PREFIX] != 0) | |
5743 | *p++ = i.prefix[REX_PREFIX]; | |
5744 | *p = i.tm.base_opcode; | |
5745 | ||
5746 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
5747 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
40fb9820 | 5748 | else if (cpu_arch_flags.bitfield.cpui386) |
29b0f896 AM |
5749 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); |
5750 | else | |
5751 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
5752 | subtype |= code16; | |
3e73aa7c | 5753 | |
29b0f896 AM |
5754 | sym = i.op[0].disps->X_add_symbol; |
5755 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 5756 | |
29b0f896 AM |
5757 | if (i.op[0].disps->X_op != O_constant |
5758 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 5759 | { |
29b0f896 AM |
5760 | /* Handle complex expressions. */ |
5761 | sym = make_expr_symbol (i.op[0].disps); | |
5762 | off = 0; | |
5763 | } | |
3e73aa7c | 5764 | |
29b0f896 AM |
5765 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
5766 | Pass reloc in fr_var. */ | |
5767 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
5768 | } | |
3e73aa7c | 5769 | |
29b0f896 | 5770 | static void |
e3bb37b5 | 5771 | output_jump (void) |
29b0f896 AM |
5772 | { |
5773 | char *p; | |
5774 | int size; | |
3e02c1cc | 5775 | fixS *fixP; |
29b0f896 | 5776 | |
40fb9820 | 5777 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
5778 | { |
5779 | /* This is a loop or jecxz type instruction. */ | |
5780 | size = 1; | |
5781 | if (i.prefix[ADDR_PREFIX] != 0) | |
5782 | { | |
5783 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
5784 | i.prefixes -= 1; | |
5785 | } | |
5786 | /* Pentium4 branch hints. */ | |
5787 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5788 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
5789 | { | |
5790 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
5791 | i.prefixes--; | |
3e73aa7c JH |
5792 | } |
5793 | } | |
29b0f896 AM |
5794 | else |
5795 | { | |
5796 | int code16; | |
3e73aa7c | 5797 | |
29b0f896 AM |
5798 | code16 = 0; |
5799 | if (flag_code == CODE_16BIT) | |
5800 | code16 = CODE16; | |
3e73aa7c | 5801 | |
29b0f896 AM |
5802 | if (i.prefix[DATA_PREFIX] != 0) |
5803 | { | |
5804 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
5805 | i.prefixes -= 1; | |
5806 | code16 ^= CODE16; | |
5807 | } | |
252b5132 | 5808 | |
29b0f896 AM |
5809 | size = 4; |
5810 | if (code16) | |
5811 | size = 2; | |
5812 | } | |
9fcc94b6 | 5813 | |
29b0f896 AM |
5814 | if (i.prefix[REX_PREFIX] != 0) |
5815 | { | |
5816 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
5817 | i.prefixes -= 1; | |
5818 | } | |
252b5132 | 5819 | |
29b0f896 AM |
5820 | if (i.prefixes != 0 && !intel_syntax) |
5821 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 5822 | |
29b0f896 AM |
5823 | p = frag_more (1 + size); |
5824 | *p++ = i.tm.base_opcode; | |
e0890092 | 5825 | |
3e02c1cc AM |
5826 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5827 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
5828 | ||
5829 | /* All jumps handled here are signed, but don't use a signed limit | |
5830 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
5831 | 4G and 64k respectively. */ | |
5832 | if (size == 1) | |
5833 | fixP->fx_signed = 1; | |
29b0f896 | 5834 | } |
e0890092 | 5835 | |
29b0f896 | 5836 | static void |
e3bb37b5 | 5837 | output_interseg_jump (void) |
29b0f896 AM |
5838 | { |
5839 | char *p; | |
5840 | int size; | |
5841 | int prefix; | |
5842 | int code16; | |
252b5132 | 5843 | |
29b0f896 AM |
5844 | code16 = 0; |
5845 | if (flag_code == CODE_16BIT) | |
5846 | code16 = CODE16; | |
a217f122 | 5847 | |
29b0f896 AM |
5848 | prefix = 0; |
5849 | if (i.prefix[DATA_PREFIX] != 0) | |
5850 | { | |
5851 | prefix = 1; | |
5852 | i.prefixes -= 1; | |
5853 | code16 ^= CODE16; | |
5854 | } | |
5855 | if (i.prefix[REX_PREFIX] != 0) | |
5856 | { | |
5857 | prefix++; | |
5858 | i.prefixes -= 1; | |
5859 | } | |
252b5132 | 5860 | |
29b0f896 AM |
5861 | size = 4; |
5862 | if (code16) | |
5863 | size = 2; | |
252b5132 | 5864 | |
29b0f896 AM |
5865 | if (i.prefixes != 0 && !intel_syntax) |
5866 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 5867 | |
29b0f896 AM |
5868 | /* 1 opcode; 2 segment; offset */ |
5869 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 5870 | |
29b0f896 AM |
5871 | if (i.prefix[DATA_PREFIX] != 0) |
5872 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 5873 | |
29b0f896 AM |
5874 | if (i.prefix[REX_PREFIX] != 0) |
5875 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 5876 | |
29b0f896 AM |
5877 | *p++ = i.tm.base_opcode; |
5878 | if (i.op[1].imms->X_op == O_constant) | |
5879 | { | |
5880 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 5881 | |
29b0f896 AM |
5882 | if (size == 2 |
5883 | && !fits_in_unsigned_word (n) | |
5884 | && !fits_in_signed_word (n)) | |
5885 | { | |
5886 | as_bad (_("16-bit jump out of range")); | |
5887 | return; | |
5888 | } | |
5889 | md_number_to_chars (p, n, size); | |
5890 | } | |
5891 | else | |
5892 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
5893 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
5894 | if (i.op[0].imms->X_op != O_constant) | |
5895 | as_bad (_("can't handle non absolute segment in `%s'"), | |
5896 | i.tm.name); | |
5897 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
5898 | } | |
a217f122 | 5899 | |
29b0f896 | 5900 | static void |
e3bb37b5 | 5901 | output_insn (void) |
29b0f896 | 5902 | { |
2bbd9c25 JJ |
5903 | fragS *insn_start_frag; |
5904 | offsetT insn_start_off; | |
5905 | ||
29b0f896 AM |
5906 | /* Tie dwarf2 debug info to the address at the start of the insn. |
5907 | We can't do this after the insn has been output as the current | |
5908 | frag may have been closed off. eg. by frag_var. */ | |
5909 | dwarf2_emit_insn (0); | |
5910 | ||
2bbd9c25 JJ |
5911 | insn_start_frag = frag_now; |
5912 | insn_start_off = frag_now_fix (); | |
5913 | ||
29b0f896 | 5914 | /* Output jumps. */ |
40fb9820 | 5915 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 5916 | output_branch (); |
40fb9820 L |
5917 | else if (i.tm.opcode_modifier.jumpbyte |
5918 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 5919 | output_jump (); |
40fb9820 | 5920 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
5921 | output_interseg_jump (); |
5922 | else | |
5923 | { | |
5924 | /* Output normal instructions here. */ | |
5925 | char *p; | |
5926 | unsigned char *q; | |
47465058 | 5927 | unsigned int j; |
331d2d0d | 5928 | unsigned int prefix; |
4dffcebc | 5929 | |
c0f3af97 L |
5930 | /* Since the VEX prefix contains the implicit prefix, we don't |
5931 | need the explicit prefix. */ | |
5932 | if (!i.tm.opcode_modifier.vex) | |
bc4bd9ab | 5933 | { |
c0f3af97 | 5934 | switch (i.tm.opcode_length) |
bc4bd9ab | 5935 | { |
c0f3af97 L |
5936 | case 3: |
5937 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 5938 | { |
c0f3af97 L |
5939 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
5940 | goto check_prefix; | |
5941 | } | |
5942 | break; | |
5943 | case 2: | |
5944 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
5945 | { | |
5946 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
5947 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
5948 | { | |
4dffcebc | 5949 | check_prefix: |
c0f3af97 L |
5950 | if (prefix != REPE_PREFIX_OPCODE |
5951 | || (i.prefix[LOCKREP_PREFIX] | |
5952 | != REPE_PREFIX_OPCODE)) | |
5953 | add_prefix (prefix); | |
5954 | } | |
5955 | else | |
4dffcebc L |
5956 | add_prefix (prefix); |
5957 | } | |
c0f3af97 L |
5958 | break; |
5959 | case 1: | |
5960 | break; | |
5961 | default: | |
5962 | abort (); | |
bc4bd9ab | 5963 | } |
c0f3af97 L |
5964 | |
5965 | /* The prefix bytes. */ | |
5966 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
5967 | if (*q) | |
5968 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 5969 | } |
252b5132 | 5970 | |
c0f3af97 L |
5971 | if (i.tm.opcode_modifier.vex) |
5972 | { | |
5973 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
5974 | if (*q) | |
5975 | switch (j) | |
5976 | { | |
5977 | case REX_PREFIX: | |
5978 | /* REX byte is encoded in VEX prefix. */ | |
5979 | break; | |
5980 | case SEG_PREFIX: | |
5981 | case ADDR_PREFIX: | |
5982 | FRAG_APPEND_1_CHAR (*q); | |
5983 | break; | |
5984 | default: | |
5985 | /* There should be no other prefixes for instructions | |
5986 | with VEX prefix. */ | |
5987 | abort (); | |
5988 | } | |
5989 | ||
5990 | /* Now the VEX prefix. */ | |
5991 | p = frag_more (i.vex.length); | |
5992 | for (j = 0; j < i.vex.length; j++) | |
5993 | p[j] = i.vex.bytes[j]; | |
5994 | } | |
252b5132 | 5995 | |
29b0f896 | 5996 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 5997 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
5998 | { |
5999 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
6000 | } | |
6001 | else | |
6002 | { | |
4dffcebc | 6003 | switch (i.tm.opcode_length) |
331d2d0d | 6004 | { |
4dffcebc | 6005 | case 3: |
331d2d0d L |
6006 | p = frag_more (3); |
6007 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
6008 | break; |
6009 | case 2: | |
6010 | p = frag_more (2); | |
6011 | break; | |
6012 | default: | |
6013 | abort (); | |
6014 | break; | |
331d2d0d | 6015 | } |
0f10071e | 6016 | |
29b0f896 AM |
6017 | /* Put out high byte first: can't use md_number_to_chars! */ |
6018 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
6019 | *p = i.tm.base_opcode & 0xff; | |
85f10a01 MM |
6020 | |
6021 | /* On SSE5, encode the OC1 bit in the DREX field if this | |
6022 | encoding has multiple formats. */ | |
6023 | if (i.tm.opcode_modifier.drex | |
6024 | && i.tm.opcode_modifier.drexv | |
6025 | && DREX_OC1 (i.tm.extension_opcode)) | |
6026 | *p |= DREX_OC1_MASK; | |
29b0f896 | 6027 | } |
3e73aa7c | 6028 | |
29b0f896 | 6029 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 6030 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 6031 | { |
4a3523fa L |
6032 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
6033 | | i.rm.reg << 3 | |
6034 | | i.rm.mode << 6)); | |
29b0f896 AM |
6035 | /* If i.rm.regmem == ESP (4) |
6036 | && i.rm.mode != (Register mode) | |
6037 | && not 16 bit | |
6038 | ==> need second modrm byte. */ | |
6039 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
6040 | && i.rm.mode != 3 | |
40fb9820 | 6041 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
6042 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
6043 | | i.sib.index << 3 | |
6044 | | i.sib.scale << 6)); | |
29b0f896 | 6045 | } |
3e73aa7c | 6046 | |
85f10a01 MM |
6047 | /* Write the DREX byte if needed. */ |
6048 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
6049 | { | |
6050 | p = frag_more (1); | |
6051 | *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7)); | |
6052 | ||
6053 | /* Encode the OC0 bit if this encoding has multiple | |
6054 | formats. */ | |
6055 | if ((i.tm.opcode_modifier.drex | |
6056 | || i.tm.opcode_modifier.drexv) | |
6057 | && DREX_OC0 (i.tm.extension_opcode)) | |
6058 | *p |= DREX_OC0_MASK; | |
6059 | } | |
6060 | ||
29b0f896 | 6061 | if (i.disp_operands) |
2bbd9c25 | 6062 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 6063 | |
29b0f896 | 6064 | if (i.imm_operands) |
2bbd9c25 | 6065 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 6066 | } |
252b5132 | 6067 | |
29b0f896 AM |
6068 | #ifdef DEBUG386 |
6069 | if (flag_debug) | |
6070 | { | |
7b81dfbb | 6071 | pi ("" /*line*/, &i); |
29b0f896 AM |
6072 | } |
6073 | #endif /* DEBUG386 */ | |
6074 | } | |
252b5132 | 6075 | |
e205caa7 L |
6076 | /* Return the size of the displacement operand N. */ |
6077 | ||
6078 | static int | |
6079 | disp_size (unsigned int n) | |
6080 | { | |
6081 | int size = 4; | |
40fb9820 L |
6082 | if (i.types[n].bitfield.disp64) |
6083 | size = 8; | |
6084 | else if (i.types[n].bitfield.disp8) | |
6085 | size = 1; | |
6086 | else if (i.types[n].bitfield.disp16) | |
6087 | size = 2; | |
e205caa7 L |
6088 | return size; |
6089 | } | |
6090 | ||
6091 | /* Return the size of the immediate operand N. */ | |
6092 | ||
6093 | static int | |
6094 | imm_size (unsigned int n) | |
6095 | { | |
6096 | int size = 4; | |
40fb9820 L |
6097 | if (i.types[n].bitfield.imm64) |
6098 | size = 8; | |
6099 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
6100 | size = 1; | |
6101 | else if (i.types[n].bitfield.imm16) | |
6102 | size = 2; | |
e205caa7 L |
6103 | return size; |
6104 | } | |
6105 | ||
29b0f896 | 6106 | static void |
64e74474 | 6107 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6108 | { |
6109 | char *p; | |
6110 | unsigned int n; | |
252b5132 | 6111 | |
29b0f896 AM |
6112 | for (n = 0; n < i.operands; n++) |
6113 | { | |
40fb9820 | 6114 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
6115 | { |
6116 | if (i.op[n].disps->X_op == O_constant) | |
6117 | { | |
e205caa7 | 6118 | int size = disp_size (n); |
29b0f896 | 6119 | offsetT val; |
252b5132 | 6120 | |
29b0f896 AM |
6121 | val = offset_in_range (i.op[n].disps->X_add_number, |
6122 | size); | |
6123 | p = frag_more (size); | |
6124 | md_number_to_chars (p, val, size); | |
6125 | } | |
6126 | else | |
6127 | { | |
f86103b7 | 6128 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 6129 | int size = disp_size (n); |
40fb9820 | 6130 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
6131 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
6132 | ||
e205caa7 | 6133 | /* We can't have 8 bit displacement here. */ |
40fb9820 | 6134 | assert (!i.types[n].bitfield.disp8); |
e205caa7 | 6135 | |
29b0f896 AM |
6136 | /* The PC relative address is computed relative |
6137 | to the instruction boundary, so in case immediate | |
6138 | fields follows, we need to adjust the value. */ | |
6139 | if (pcrel && i.imm_operands) | |
6140 | { | |
29b0f896 | 6141 | unsigned int n1; |
e205caa7 | 6142 | int sz = 0; |
252b5132 | 6143 | |
29b0f896 | 6144 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 6145 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 6146 | { |
e205caa7 L |
6147 | /* Only one immediate is allowed for PC |
6148 | relative address. */ | |
6149 | assert (sz == 0); | |
6150 | sz = imm_size (n1); | |
6151 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 6152 | } |
29b0f896 | 6153 | /* We should find the immediate. */ |
e205caa7 | 6154 | assert (sz != 0); |
29b0f896 | 6155 | } |
520dc8e8 | 6156 | |
29b0f896 | 6157 | p = frag_more (size); |
2bbd9c25 | 6158 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 6159 | if (GOT_symbol |
2bbd9c25 | 6160 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 6161 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6162 | || reloc_type == BFD_RELOC_X86_64_32S |
6163 | || (reloc_type == BFD_RELOC_64 | |
6164 | && object_64bit)) | |
d6ab8113 JB |
6165 | && (i.op[n].disps->X_op == O_symbol |
6166 | || (i.op[n].disps->X_op == O_add | |
6167 | && ((symbol_get_value_expression | |
6168 | (i.op[n].disps->X_op_symbol)->X_op) | |
6169 | == O_subtract)))) | |
6170 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
6171 | { |
6172 | offsetT add; | |
6173 | ||
6174 | if (insn_start_frag == frag_now) | |
6175 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6176 | else | |
6177 | { | |
6178 | fragS *fr; | |
6179 | ||
6180 | add = insn_start_frag->fr_fix - insn_start_off; | |
6181 | for (fr = insn_start_frag->fr_next; | |
6182 | fr && fr != frag_now; fr = fr->fr_next) | |
6183 | add += fr->fr_fix; | |
6184 | add += p - frag_now->fr_literal; | |
6185 | } | |
6186 | ||
4fa24527 | 6187 | if (!object_64bit) |
7b81dfbb AJ |
6188 | { |
6189 | reloc_type = BFD_RELOC_386_GOTPC; | |
6190 | i.op[n].imms->X_add_number += add; | |
6191 | } | |
6192 | else if (reloc_type == BFD_RELOC_64) | |
6193 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 6194 | else |
7b81dfbb AJ |
6195 | /* Don't do the adjustment for x86-64, as there |
6196 | the pcrel addressing is relative to the _next_ | |
6197 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 6198 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 6199 | } |
062cd5e7 | 6200 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 6201 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
6202 | } |
6203 | } | |
6204 | } | |
6205 | } | |
252b5132 | 6206 | |
29b0f896 | 6207 | static void |
64e74474 | 6208 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6209 | { |
6210 | char *p; | |
6211 | unsigned int n; | |
252b5132 | 6212 | |
29b0f896 AM |
6213 | for (n = 0; n < i.operands; n++) |
6214 | { | |
40fb9820 | 6215 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
6216 | { |
6217 | if (i.op[n].imms->X_op == O_constant) | |
6218 | { | |
e205caa7 | 6219 | int size = imm_size (n); |
29b0f896 | 6220 | offsetT val; |
b4cac588 | 6221 | |
29b0f896 AM |
6222 | val = offset_in_range (i.op[n].imms->X_add_number, |
6223 | size); | |
6224 | p = frag_more (size); | |
6225 | md_number_to_chars (p, val, size); | |
6226 | } | |
6227 | else | |
6228 | { | |
6229 | /* Not absolute_section. | |
6230 | Need a 32-bit fixup (don't support 8bit | |
6231 | non-absolute imms). Try to support other | |
6232 | sizes ... */ | |
f86103b7 | 6233 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
6234 | int size = imm_size (n); |
6235 | int sign; | |
29b0f896 | 6236 | |
40fb9820 | 6237 | if (i.types[n].bitfield.imm32s |
a7d61044 | 6238 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 6239 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 6240 | sign = 1; |
e205caa7 L |
6241 | else |
6242 | sign = 0; | |
520dc8e8 | 6243 | |
29b0f896 AM |
6244 | p = frag_more (size); |
6245 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 6246 | |
2bbd9c25 JJ |
6247 | /* This is tough to explain. We end up with this one if we |
6248 | * have operands that look like | |
6249 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
6250 | * obtain the absolute address of the GOT, and it is strongly | |
6251 | * preferable from a performance point of view to avoid using | |
6252 | * a runtime relocation for this. The actual sequence of | |
6253 | * instructions often look something like: | |
6254 | * | |
6255 | * call .L66 | |
6256 | * .L66: | |
6257 | * popl %ebx | |
6258 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
6259 | * | |
6260 | * The call and pop essentially return the absolute address | |
6261 | * of the label .L66 and store it in %ebx. The linker itself | |
6262 | * will ultimately change the first operand of the addl so | |
6263 | * that %ebx points to the GOT, but to keep things simple, the | |
6264 | * .o file must have this operand set so that it generates not | |
6265 | * the absolute address of .L66, but the absolute address of | |
6266 | * itself. This allows the linker itself simply treat a GOTPC | |
6267 | * relocation as asking for a pcrel offset to the GOT to be | |
6268 | * added in, and the addend of the relocation is stored in the | |
6269 | * operand field for the instruction itself. | |
6270 | * | |
6271 | * Our job here is to fix the operand so that it would add | |
6272 | * the correct offset so that %ebx would point to itself. The | |
6273 | * thing that is tricky is that .-.L66 will point to the | |
6274 | * beginning of the instruction, so we need to further modify | |
6275 | * the operand so that it will point to itself. There are | |
6276 | * other cases where you have something like: | |
6277 | * | |
6278 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
6279 | * | |
6280 | * and here no correction would be required. Internally in | |
6281 | * the assembler we treat operands of this form as not being | |
6282 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
6283 | * whether it would simplify matters to do it this way. Who | |
6284 | * knows. In earlier versions of the PIC patches, the | |
6285 | * pcrel_adjust field was used to store the correction, but | |
6286 | * since the expression is not pcrel, I felt it would be | |
6287 | * confusing to do it this way. */ | |
6288 | ||
d6ab8113 | 6289 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6290 | || reloc_type == BFD_RELOC_X86_64_32S |
6291 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
6292 | && GOT_symbol |
6293 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
6294 | && (i.op[n].imms->X_op == O_symbol | |
6295 | || (i.op[n].imms->X_op == O_add | |
6296 | && ((symbol_get_value_expression | |
6297 | (i.op[n].imms->X_op_symbol)->X_op) | |
6298 | == O_subtract)))) | |
6299 | { | |
2bbd9c25 JJ |
6300 | offsetT add; |
6301 | ||
6302 | if (insn_start_frag == frag_now) | |
6303 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6304 | else | |
6305 | { | |
6306 | fragS *fr; | |
6307 | ||
6308 | add = insn_start_frag->fr_fix - insn_start_off; | |
6309 | for (fr = insn_start_frag->fr_next; | |
6310 | fr && fr != frag_now; fr = fr->fr_next) | |
6311 | add += fr->fr_fix; | |
6312 | add += p - frag_now->fr_literal; | |
6313 | } | |
6314 | ||
4fa24527 | 6315 | if (!object_64bit) |
d6ab8113 | 6316 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 6317 | else if (size == 4) |
d6ab8113 | 6318 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
6319 | else if (size == 8) |
6320 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 6321 | i.op[n].imms->X_add_number += add; |
29b0f896 | 6322 | } |
29b0f896 AM |
6323 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
6324 | i.op[n].imms, 0, reloc_type); | |
6325 | } | |
6326 | } | |
6327 | } | |
252b5132 RH |
6328 | } |
6329 | \f | |
d182319b JB |
6330 | /* x86_cons_fix_new is called via the expression parsing code when a |
6331 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
6332 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
6333 | static int cons_sign = -1; | |
6334 | ||
6335 | void | |
e3bb37b5 | 6336 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 6337 | expressionS *exp) |
d182319b JB |
6338 | { |
6339 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
6340 | ||
6341 | got_reloc = NO_RELOC; | |
6342 | ||
6343 | #ifdef TE_PE | |
6344 | if (exp->X_op == O_secrel) | |
6345 | { | |
6346 | exp->X_op = O_symbol; | |
6347 | r = BFD_RELOC_32_SECREL; | |
6348 | } | |
6349 | #endif | |
6350 | ||
6351 | fix_new_exp (frag, off, len, exp, 0, r); | |
6352 | } | |
6353 | ||
718ddfc0 JB |
6354 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
6355 | # define lex_got(reloc, adjust, types) NULL | |
6356 | #else | |
f3c180ae AM |
6357 | /* Parse operands of the form |
6358 | <symbol>@GOTOFF+<nnn> | |
6359 | and similar .plt or .got references. | |
6360 | ||
6361 | If we find one, set up the correct relocation in RELOC and copy the | |
6362 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
6363 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6364 | is non-null set it to the length of the string we removed from the | |
6365 | input line. Otherwise return NULL. */ | |
6366 | static char * | |
3956db08 | 6367 | lex_got (enum bfd_reloc_code_real *reloc, |
64e74474 | 6368 | int *adjust, |
40fb9820 | 6369 | i386_operand_type *types) |
f3c180ae | 6370 | { |
7b81dfbb AJ |
6371 | /* Some of the relocations depend on the size of what field is to |
6372 | be relocated. But in our callers i386_immediate and i386_displacement | |
6373 | we don't yet know the operand size (this will be set by insn | |
6374 | matching). Hence we record the word32 relocation here, | |
6375 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
6376 | static const struct { |
6377 | const char *str; | |
4fa24527 | 6378 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 6379 | const i386_operand_type types64; |
f3c180ae | 6380 | } gotrel[] = { |
4eed87de AM |
6381 | { "PLTOFF", { 0, |
6382 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 6383 | OPERAND_TYPE_IMM64 }, |
4eed87de AM |
6384 | { "PLT", { BFD_RELOC_386_PLT32, |
6385 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 6386 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6387 | { "GOTPLT", { 0, |
6388 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 6389 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
6390 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, |
6391 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 6392 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
6393 | { "GOTPCREL", { 0, |
6394 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 6395 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6396 | { "TLSGD", { BFD_RELOC_386_TLS_GD, |
6397 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 6398 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6399 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, |
6400 | 0 }, | |
40fb9820 | 6401 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6402 | { "TLSLD", { 0, |
6403 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 6404 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6405 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, |
6406 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 6407 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6408 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, |
6409 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 6410 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
4eed87de AM |
6411 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, |
6412 | 0 }, | |
40fb9820 | 6413 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6414 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, |
6415 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 L |
6416 | |
6417 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
4eed87de AM |
6418 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, |
6419 | 0 }, | |
40fb9820 | 6420 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6421 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, |
6422 | 0 }, | |
40fb9820 | 6423 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6424 | { "GOT", { BFD_RELOC_386_GOT32, |
6425 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 6426 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
4eed87de AM |
6427 | { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, |
6428 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 6429 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6430 | { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, |
6431 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 6432 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
6433 | }; |
6434 | char *cp; | |
6435 | unsigned int j; | |
6436 | ||
718ddfc0 JB |
6437 | if (!IS_ELF) |
6438 | return NULL; | |
6439 | ||
f3c180ae | 6440 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 6441 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
6442 | return NULL; |
6443 | ||
47465058 | 6444 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae AM |
6445 | { |
6446 | int len; | |
6447 | ||
6448 | len = strlen (gotrel[j].str); | |
28f81592 | 6449 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 6450 | { |
4fa24527 | 6451 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 6452 | { |
28f81592 AM |
6453 | int first, second; |
6454 | char *tmpbuf, *past_reloc; | |
f3c180ae | 6455 | |
4fa24527 | 6456 | *reloc = gotrel[j].rel[object_64bit]; |
28f81592 AM |
6457 | if (adjust) |
6458 | *adjust = len; | |
f3c180ae | 6459 | |
3956db08 JB |
6460 | if (types) |
6461 | { | |
6462 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
6463 | { |
6464 | types->bitfield.imm32 = 1; | |
6465 | types->bitfield.disp32 = 1; | |
6466 | } | |
3956db08 JB |
6467 | else |
6468 | *types = gotrel[j].types64; | |
6469 | } | |
6470 | ||
f3c180ae AM |
6471 | if (GOT_symbol == NULL) |
6472 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
6473 | ||
28f81592 | 6474 | /* The length of the first part of our input line. */ |
f3c180ae | 6475 | first = cp - input_line_pointer; |
28f81592 AM |
6476 | |
6477 | /* The second part goes from after the reloc token until | |
67c11a9b | 6478 | (and including) an end_of_line char or comma. */ |
28f81592 | 6479 | past_reloc = cp + 1 + len; |
67c11a9b AM |
6480 | cp = past_reloc; |
6481 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6482 | ++cp; | |
6483 | second = cp + 1 - past_reloc; | |
28f81592 AM |
6484 | |
6485 | /* Allocate and copy string. The trailing NUL shouldn't | |
6486 | be necessary, but be safe. */ | |
6487 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae | 6488 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
6489 | if (second != 0 && *past_reloc != ' ') |
6490 | /* Replace the relocation token with ' ', so that | |
6491 | errors like foo@GOTOFF1 will be detected. */ | |
6492 | tmpbuf[first++] = ' '; | |
6493 | memcpy (tmpbuf + first, past_reloc, second); | |
6494 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
6495 | return tmpbuf; |
6496 | } | |
6497 | ||
4fa24527 JB |
6498 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
6499 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
6500 | return NULL; |
6501 | } | |
6502 | } | |
6503 | ||
6504 | /* Might be a symbol version string. Don't as_bad here. */ | |
6505 | return NULL; | |
6506 | } | |
6507 | ||
f3c180ae | 6508 | void |
e3bb37b5 | 6509 | x86_cons (expressionS *exp, int size) |
f3c180ae | 6510 | { |
4fa24527 | 6511 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
6512 | { |
6513 | /* Handle @GOTOFF and the like in an expression. */ | |
6514 | char *save; | |
6515 | char *gotfree_input_line; | |
6516 | int adjust; | |
6517 | ||
6518 | save = input_line_pointer; | |
3956db08 | 6519 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
6520 | if (gotfree_input_line) |
6521 | input_line_pointer = gotfree_input_line; | |
6522 | ||
6523 | expression (exp); | |
6524 | ||
6525 | if (gotfree_input_line) | |
6526 | { | |
6527 | /* expression () has merrily parsed up to the end of line, | |
6528 | or a comma - in the wrong buffer. Transfer how far | |
6529 | input_line_pointer has moved to the right buffer. */ | |
6530 | input_line_pointer = (save | |
6531 | + (input_line_pointer - gotfree_input_line) | |
6532 | + adjust); | |
6533 | free (gotfree_input_line); | |
3992d3b7 AM |
6534 | if (exp->X_op == O_constant |
6535 | || exp->X_op == O_absent | |
6536 | || exp->X_op == O_illegal | |
6537 | || exp->X_op == O_register | |
6538 | || exp->X_op == O_big) | |
6539 | { | |
6540 | char c = *input_line_pointer; | |
6541 | *input_line_pointer = 0; | |
6542 | as_bad (_("missing or invalid expression `%s'"), save); | |
6543 | *input_line_pointer = c; | |
6544 | } | |
f3c180ae AM |
6545 | } |
6546 | } | |
6547 | else | |
6548 | expression (exp); | |
6549 | } | |
6550 | #endif | |
6551 | ||
d182319b | 6552 | static void signed_cons (int size) |
6482c264 | 6553 | { |
d182319b JB |
6554 | if (flag_code == CODE_64BIT) |
6555 | cons_sign = 1; | |
6556 | cons (size); | |
6557 | cons_sign = -1; | |
6482c264 NC |
6558 | } |
6559 | ||
d182319b | 6560 | #ifdef TE_PE |
6482c264 NC |
6561 | static void |
6562 | pe_directive_secrel (dummy) | |
6563 | int dummy ATTRIBUTE_UNUSED; | |
6564 | { | |
6565 | expressionS exp; | |
6566 | ||
6567 | do | |
6568 | { | |
6569 | expression (&exp); | |
6570 | if (exp.X_op == O_symbol) | |
6571 | exp.X_op = O_secrel; | |
6572 | ||
6573 | emit_expr (&exp, 4); | |
6574 | } | |
6575 | while (*input_line_pointer++ == ','); | |
6576 | ||
6577 | input_line_pointer--; | |
6578 | demand_empty_rest_of_line (); | |
6579 | } | |
6482c264 NC |
6580 | #endif |
6581 | ||
252b5132 | 6582 | static int |
70e41ade | 6583 | i386_immediate (char *imm_start) |
252b5132 RH |
6584 | { |
6585 | char *save_input_line_pointer; | |
f3c180ae | 6586 | char *gotfree_input_line; |
252b5132 | 6587 | segT exp_seg = 0; |
47926f60 | 6588 | expressionS *exp; |
40fb9820 L |
6589 | i386_operand_type types; |
6590 | ||
0dfbf9d7 | 6591 | operand_type_set (&types, ~0); |
252b5132 RH |
6592 | |
6593 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
6594 | { | |
31b2323c L |
6595 | as_bad (_("at most %d immediate operands are allowed"), |
6596 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
6597 | return 0; |
6598 | } | |
6599 | ||
6600 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 6601 | i.op[this_operand].imms = exp; |
252b5132 RH |
6602 | |
6603 | if (is_space_char (*imm_start)) | |
6604 | ++imm_start; | |
6605 | ||
6606 | save_input_line_pointer = input_line_pointer; | |
6607 | input_line_pointer = imm_start; | |
6608 | ||
3956db08 | 6609 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6610 | if (gotfree_input_line) |
6611 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
6612 | |
6613 | exp_seg = expression (exp); | |
6614 | ||
83183c0c | 6615 | SKIP_WHITESPACE (); |
252b5132 | 6616 | if (*input_line_pointer) |
f3c180ae | 6617 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
6618 | |
6619 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
6620 | if (gotfree_input_line) |
6621 | free (gotfree_input_line); | |
252b5132 | 6622 | |
3992d3b7 AM |
6623 | if (exp->X_op == O_absent |
6624 | || exp->X_op == O_illegal | |
6625 | || exp->X_op == O_big | |
6626 | || (gotfree_input_line | |
6627 | && (exp->X_op == O_constant | |
6628 | || exp->X_op == O_register))) | |
252b5132 | 6629 | { |
3992d3b7 | 6630 | as_bad (_("missing or invalid immediate expression `%s'"), |
24eab124 | 6631 | imm_start); |
3992d3b7 | 6632 | return 0; |
252b5132 | 6633 | } |
3e73aa7c | 6634 | else if (exp->X_op == O_constant) |
252b5132 | 6635 | { |
47926f60 | 6636 | /* Size it properly later. */ |
40fb9820 | 6637 | i.types[this_operand].bitfield.imm64 = 1; |
3e73aa7c | 6638 | /* If BFD64, sign extend val. */ |
4eed87de AM |
6639 | if (!use_rela_relocations |
6640 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
6641 | exp->X_add_number | |
6642 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 6643 | } |
4c63da97 | 6644 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 6645 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 6646 | && exp_seg != absolute_section |
47926f60 | 6647 | && exp_seg != text_section |
24eab124 AM |
6648 | && exp_seg != data_section |
6649 | && exp_seg != bss_section | |
6650 | && exp_seg != undefined_section | |
f86103b7 | 6651 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 6652 | { |
d0b47220 | 6653 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
6654 | return 0; |
6655 | } | |
6656 | #endif | |
bb8f5920 L |
6657 | else if (!intel_syntax && exp->X_op == O_register) |
6658 | { | |
6659 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
6660 | return 0; | |
6661 | } | |
252b5132 RH |
6662 | else |
6663 | { | |
6664 | /* This is an address. The size of the address will be | |
24eab124 | 6665 | determined later, depending on destination register, |
3e73aa7c | 6666 | suffix, or the default for the section. */ |
40fb9820 L |
6667 | i.types[this_operand].bitfield.imm8 = 1; |
6668 | i.types[this_operand].bitfield.imm16 = 1; | |
6669 | i.types[this_operand].bitfield.imm32 = 1; | |
6670 | i.types[this_operand].bitfield.imm32s = 1; | |
6671 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
6672 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6673 | types); | |
252b5132 RH |
6674 | } |
6675 | ||
6676 | return 1; | |
6677 | } | |
6678 | ||
551c1ca1 | 6679 | static char * |
e3bb37b5 | 6680 | i386_scale (char *scale) |
252b5132 | 6681 | { |
551c1ca1 AM |
6682 | offsetT val; |
6683 | char *save = input_line_pointer; | |
252b5132 | 6684 | |
551c1ca1 AM |
6685 | input_line_pointer = scale; |
6686 | val = get_absolute_expression (); | |
6687 | ||
6688 | switch (val) | |
252b5132 | 6689 | { |
551c1ca1 | 6690 | case 1: |
252b5132 RH |
6691 | i.log2_scale_factor = 0; |
6692 | break; | |
551c1ca1 | 6693 | case 2: |
252b5132 RH |
6694 | i.log2_scale_factor = 1; |
6695 | break; | |
551c1ca1 | 6696 | case 4: |
252b5132 RH |
6697 | i.log2_scale_factor = 2; |
6698 | break; | |
551c1ca1 | 6699 | case 8: |
252b5132 RH |
6700 | i.log2_scale_factor = 3; |
6701 | break; | |
6702 | default: | |
a724f0f4 JB |
6703 | { |
6704 | char sep = *input_line_pointer; | |
6705 | ||
6706 | *input_line_pointer = '\0'; | |
6707 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
6708 | scale); | |
6709 | *input_line_pointer = sep; | |
6710 | input_line_pointer = save; | |
6711 | return NULL; | |
6712 | } | |
252b5132 | 6713 | } |
29b0f896 | 6714 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
6715 | { |
6716 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 6717 | 1 << i.log2_scale_factor); |
252b5132 | 6718 | i.log2_scale_factor = 0; |
252b5132 | 6719 | } |
551c1ca1 AM |
6720 | scale = input_line_pointer; |
6721 | input_line_pointer = save; | |
6722 | return scale; | |
252b5132 RH |
6723 | } |
6724 | ||
252b5132 | 6725 | static int |
e3bb37b5 | 6726 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 6727 | { |
29b0f896 | 6728 | expressionS *exp; |
252b5132 RH |
6729 | segT exp_seg = 0; |
6730 | char *save_input_line_pointer; | |
f3c180ae | 6731 | char *gotfree_input_line; |
40fb9820 L |
6732 | int override; |
6733 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 6734 | int ret; |
252b5132 | 6735 | |
31b2323c L |
6736 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
6737 | { | |
6738 | as_bad (_("at most %d displacement operands are allowed"), | |
6739 | MAX_MEMORY_OPERANDS); | |
6740 | return 0; | |
6741 | } | |
6742 | ||
0dfbf9d7 | 6743 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
6744 | if ((i.types[this_operand].bitfield.jumpabsolute) |
6745 | || (!current_templates->start->opcode_modifier.jump | |
6746 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 6747 | { |
40fb9820 | 6748 | bigdisp.bitfield.disp32 = 1; |
e05278af | 6749 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
6750 | if (flag_code == CODE_64BIT) |
6751 | { | |
6752 | if (!override) | |
6753 | { | |
6754 | bigdisp.bitfield.disp32s = 1; | |
6755 | bigdisp.bitfield.disp64 = 1; | |
6756 | } | |
6757 | } | |
6758 | else if ((flag_code == CODE_16BIT) ^ override) | |
6759 | { | |
6760 | bigdisp.bitfield.disp32 = 0; | |
6761 | bigdisp.bitfield.disp16 = 1; | |
6762 | } | |
e05278af JB |
6763 | } |
6764 | else | |
6765 | { | |
6766 | /* For PC-relative branches, the width of the displacement | |
6767 | is dependent upon data size, not address size. */ | |
e05278af | 6768 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
6769 | if (flag_code == CODE_64BIT) |
6770 | { | |
6771 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
6772 | bigdisp.bitfield.disp16 = 1; | |
6773 | else | |
6774 | { | |
6775 | bigdisp.bitfield.disp32 = 1; | |
6776 | bigdisp.bitfield.disp32s = 1; | |
6777 | } | |
6778 | } | |
6779 | else | |
e05278af JB |
6780 | { |
6781 | if (!override) | |
6782 | override = (i.suffix == (flag_code != CODE_16BIT | |
6783 | ? WORD_MNEM_SUFFIX | |
6784 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
6785 | bigdisp.bitfield.disp32 = 1; |
6786 | if ((flag_code == CODE_16BIT) ^ override) | |
6787 | { | |
6788 | bigdisp.bitfield.disp32 = 0; | |
6789 | bigdisp.bitfield.disp16 = 1; | |
6790 | } | |
e05278af | 6791 | } |
e05278af | 6792 | } |
c6fb90c8 L |
6793 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6794 | bigdisp); | |
252b5132 RH |
6795 | |
6796 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 6797 | i.op[this_operand].disps = exp; |
252b5132 RH |
6798 | i.disp_operands++; |
6799 | save_input_line_pointer = input_line_pointer; | |
6800 | input_line_pointer = disp_start; | |
6801 | END_STRING_AND_SAVE (disp_end); | |
6802 | ||
6803 | #ifndef GCC_ASM_O_HACK | |
6804 | #define GCC_ASM_O_HACK 0 | |
6805 | #endif | |
6806 | #if GCC_ASM_O_HACK | |
6807 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 6808 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 6809 | && displacement_string_end[-1] == '+') |
252b5132 RH |
6810 | { |
6811 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
6812 | constraint within gcc asm statements. |
6813 | For instance: | |
6814 | ||
6815 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
6816 | __asm__ __volatile__ ( \ | |
6817 | "movw %w2,%0\n\t" \ | |
6818 | "movw %w1,2+%0\n\t" \ | |
6819 | "rorl $16,%1\n\t" \ | |
6820 | "movb %b1,4+%0\n\t" \ | |
6821 | "movb %4,5+%0\n\t" \ | |
6822 | "movb $0,6+%0\n\t" \ | |
6823 | "movb %h1,7+%0\n\t" \ | |
6824 | "rorl $16,%1" \ | |
6825 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
6826 | ||
6827 | This works great except that the output assembler ends | |
6828 | up looking a bit weird if it turns out that there is | |
6829 | no offset. You end up producing code that looks like: | |
6830 | ||
6831 | #APP | |
6832 | movw $235,(%eax) | |
6833 | movw %dx,2+(%eax) | |
6834 | rorl $16,%edx | |
6835 | movb %dl,4+(%eax) | |
6836 | movb $137,5+(%eax) | |
6837 | movb $0,6+(%eax) | |
6838 | movb %dh,7+(%eax) | |
6839 | rorl $16,%edx | |
6840 | #NO_APP | |
6841 | ||
47926f60 | 6842 | So here we provide the missing zero. */ |
24eab124 AM |
6843 | |
6844 | *displacement_string_end = '0'; | |
252b5132 RH |
6845 | } |
6846 | #endif | |
3956db08 | 6847 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6848 | if (gotfree_input_line) |
6849 | input_line_pointer = gotfree_input_line; | |
252b5132 | 6850 | |
24eab124 | 6851 | exp_seg = expression (exp); |
252b5132 | 6852 | |
636c26b0 AM |
6853 | SKIP_WHITESPACE (); |
6854 | if (*input_line_pointer) | |
6855 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
6856 | #if GCC_ASM_O_HACK | |
6857 | RESTORE_END_STRING (disp_end + 1); | |
6858 | #endif | |
636c26b0 | 6859 | input_line_pointer = save_input_line_pointer; |
636c26b0 AM |
6860 | if (gotfree_input_line) |
6861 | free (gotfree_input_line); | |
3992d3b7 | 6862 | ret = 1; |
636c26b0 | 6863 | |
24eab124 AM |
6864 | /* We do this to make sure that the section symbol is in |
6865 | the symbol table. We will ultimately change the relocation | |
47926f60 | 6866 | to be relative to the beginning of the section. */ |
1ae12ab7 | 6867 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
6868 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
6869 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 6870 | { |
636c26b0 | 6871 | if (exp->X_op != O_symbol) |
3992d3b7 | 6872 | goto inv_disp; |
636c26b0 | 6873 | |
e5cb08ac | 6874 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
6875 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
6876 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
6877 | exp->X_op = O_subtract; |
6878 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 6879 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 6880 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
6881 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
6882 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 6883 | else |
29b0f896 | 6884 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 6885 | } |
252b5132 | 6886 | |
3992d3b7 AM |
6887 | else if (exp->X_op == O_absent |
6888 | || exp->X_op == O_illegal | |
6889 | || exp->X_op == O_big | |
6890 | || (gotfree_input_line | |
6891 | && (exp->X_op == O_constant | |
6892 | || exp->X_op == O_register))) | |
2daf4fd8 | 6893 | { |
3992d3b7 AM |
6894 | inv_disp: |
6895 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 6896 | disp_start); |
3992d3b7 | 6897 | ret = 0; |
2daf4fd8 AM |
6898 | } |
6899 | ||
4c63da97 | 6900 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
6901 | else if (exp->X_op != O_constant |
6902 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
6903 | && exp_seg != absolute_section | |
6904 | && exp_seg != text_section | |
6905 | && exp_seg != data_section | |
6906 | && exp_seg != bss_section | |
6907 | && exp_seg != undefined_section | |
6908 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 6909 | { |
d0b47220 | 6910 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 6911 | ret = 0; |
24eab124 | 6912 | } |
252b5132 | 6913 | #endif |
3956db08 | 6914 | |
3992d3b7 AM |
6915 | RESTORE_END_STRING (disp_end); |
6916 | ||
40fb9820 L |
6917 | /* Check if this is a displacement only operand. */ |
6918 | bigdisp = i.types[this_operand]; | |
6919 | bigdisp.bitfield.disp8 = 0; | |
6920 | bigdisp.bitfield.disp16 = 0; | |
6921 | bigdisp.bitfield.disp32 = 0; | |
6922 | bigdisp.bitfield.disp32s = 0; | |
6923 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 6924 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
6925 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6926 | types); | |
3956db08 | 6927 | |
3992d3b7 | 6928 | return ret; |
252b5132 RH |
6929 | } |
6930 | ||
eecb386c | 6931 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
6932 | Return 1 on success, 0 on a failure. */ |
6933 | ||
252b5132 | 6934 | static int |
e3bb37b5 | 6935 | i386_index_check (const char *operand_string) |
252b5132 | 6936 | { |
3e73aa7c | 6937 | int ok; |
fc0763e6 | 6938 | const char *kind = "base/index"; |
24eab124 | 6939 | #if INFER_ADDR_PREFIX |
eecb386c AM |
6940 | int fudged = 0; |
6941 | ||
24eab124 AM |
6942 | tryprefix: |
6943 | #endif | |
3e73aa7c | 6944 | ok = 1; |
fc0763e6 JB |
6945 | if (current_templates->start->opcode_modifier.isstring |
6946 | && !current_templates->start->opcode_modifier.immext | |
6947 | && (current_templates->end[-1].opcode_modifier.isstring | |
6948 | || i.mem_operands)) | |
6949 | { | |
6950 | /* Memory operands of string insns are special in that they only allow | |
6951 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
6952 | unsigned int expected; | |
6953 | ||
6954 | kind = "string address"; | |
6955 | ||
6956 | if (current_templates->start->opcode_modifier.w) | |
6957 | { | |
6958 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
6959 | ||
6960 | if (!type.bitfield.baseindex | |
6961 | || ((!i.mem_operands != !intel_syntax) | |
6962 | && current_templates->end[-1].operand_types[1] | |
6963 | .bitfield.baseindex)) | |
6964 | type = current_templates->end[-1].operand_types[1]; | |
6965 | expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */; | |
6966 | } | |
6967 | else | |
6968 | expected = 3 /* rBX */; | |
6969 | ||
6970 | if (!i.base_reg || i.index_reg | |
6971 | || operand_type_check (i.types[this_operand], disp)) | |
6972 | ok = -1; | |
6973 | else if (!(flag_code == CODE_64BIT | |
6974 | ? i.prefix[ADDR_PREFIX] | |
6975 | ? i.base_reg->reg_type.bitfield.reg32 | |
6976 | : i.base_reg->reg_type.bitfield.reg64 | |
6977 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
6978 | ? i.base_reg->reg_type.bitfield.reg32 | |
6979 | : i.base_reg->reg_type.bitfield.reg16)) | |
6980 | ok = 0; | |
6981 | else if (i.base_reg->reg_num != expected) | |
6982 | ok = -1; | |
6983 | ||
6984 | if (ok < 0) | |
6985 | { | |
6986 | unsigned int j; | |
6987 | ||
6988 | for (j = 0; j < i386_regtab_size; ++j) | |
6989 | if ((flag_code == CODE_64BIT | |
6990 | ? i.prefix[ADDR_PREFIX] | |
6991 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
6992 | : i386_regtab[j].reg_type.bitfield.reg64 | |
6993 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
6994 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
6995 | : i386_regtab[j].reg_type.bitfield.reg16) | |
6996 | && i386_regtab[j].reg_num == expected) | |
6997 | break; | |
6998 | assert (j < i386_regtab_size); | |
6999 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), | |
7000 | operand_string, | |
7001 | intel_syntax ? '[' : '(', | |
7002 | register_prefix, | |
7003 | i386_regtab[j].reg_name, | |
7004 | intel_syntax ? ']' : ')'); | |
7005 | ok = 1; | |
7006 | } | |
7007 | } | |
7008 | else if (flag_code == CODE_64BIT) | |
64e74474 | 7009 | { |
64e74474 | 7010 | if ((i.base_reg |
40fb9820 L |
7011 | && ((i.prefix[ADDR_PREFIX] == 0 |
7012 | && !i.base_reg->reg_type.bitfield.reg64) | |
7013 | || (i.prefix[ADDR_PREFIX] | |
7014 | && !i.base_reg->reg_type.bitfield.reg32)) | |
7015 | && (i.index_reg | |
9a04903e JB |
7016 | || i.base_reg->reg_num != |
7017 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 7018 | || (i.index_reg |
40fb9820 L |
7019 | && (!i.index_reg->reg_type.bitfield.baseindex |
7020 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
7021 | && i.index_reg->reg_num != RegRiz |
7022 | && !i.index_reg->reg_type.bitfield.reg64 | |
7023 | ) | |
40fb9820 | 7024 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 7025 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 7026 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 7027 | ok = 0; |
3e73aa7c JH |
7028 | } |
7029 | else | |
7030 | { | |
7031 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
7032 | { | |
7033 | /* 16bit checks. */ | |
7034 | if ((i.base_reg | |
40fb9820 L |
7035 | && (!i.base_reg->reg_type.bitfield.reg16 |
7036 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 7037 | || (i.index_reg |
40fb9820 L |
7038 | && (!i.index_reg->reg_type.bitfield.reg16 |
7039 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
7040 | || !(i.base_reg |
7041 | && i.base_reg->reg_num < 6 | |
7042 | && i.index_reg->reg_num >= 6 | |
7043 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
7044 | ok = 0; |
7045 | } | |
7046 | else | |
e5cb08ac | 7047 | { |
3e73aa7c JH |
7048 | /* 32bit checks. */ |
7049 | if ((i.base_reg | |
40fb9820 | 7050 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 7051 | || (i.index_reg |
db51cc60 L |
7052 | && ((!i.index_reg->reg_type.bitfield.reg32 |
7053 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 7054 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 7055 | ok = 0; |
3e73aa7c JH |
7056 | } |
7057 | } | |
7058 | if (!ok) | |
24eab124 AM |
7059 | { |
7060 | #if INFER_ADDR_PREFIX | |
fc0763e6 | 7061 | if (!i.mem_operands && !i.prefix[ADDR_PREFIX]) |
24eab124 AM |
7062 | { |
7063 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
7064 | i.prefixes += 1; | |
b23bac36 AM |
7065 | /* Change the size of any displacement too. At most one of |
7066 | Disp16 or Disp32 is set. | |
7067 | FIXME. There doesn't seem to be any real need for separate | |
7068 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 7069 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 7070 | if (flag_code != CODE_64BIT |
40fb9820 L |
7071 | && (i.types[this_operand].bitfield.disp16 |
7072 | || i.types[this_operand].bitfield.disp32)) | |
7073 | i.types[this_operand] | |
c6fb90c8 | 7074 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 7075 | fudged = 1; |
24eab124 AM |
7076 | goto tryprefix; |
7077 | } | |
eecb386c | 7078 | if (fudged) |
fc0763e6 JB |
7079 | as_bad (_("`%s' is not a valid %s expression"), |
7080 | operand_string, | |
7081 | kind); | |
eecb386c | 7082 | else |
c388dee8 | 7083 | #endif |
fc0763e6 | 7084 | as_bad (_("`%s' is not a valid %s-bit %s expression"), |
eecb386c | 7085 | operand_string, |
fc0763e6 JB |
7086 | flag_code_names[i.prefix[ADDR_PREFIX] |
7087 | ? flag_code == CODE_32BIT | |
7088 | ? CODE_16BIT | |
7089 | : CODE_32BIT | |
7090 | : flag_code], | |
7091 | kind); | |
24eab124 | 7092 | } |
20f0a1fc | 7093 | return ok; |
24eab124 | 7094 | } |
252b5132 | 7095 | |
fc0763e6 | 7096 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 7097 | on error. */ |
252b5132 | 7098 | |
252b5132 | 7099 | static int |
a7619375 | 7100 | i386_att_operand (char *operand_string) |
252b5132 | 7101 | { |
af6bdddf AM |
7102 | const reg_entry *r; |
7103 | char *end_op; | |
24eab124 | 7104 | char *op_string = operand_string; |
252b5132 | 7105 | |
24eab124 | 7106 | if (is_space_char (*op_string)) |
252b5132 RH |
7107 | ++op_string; |
7108 | ||
24eab124 | 7109 | /* We check for an absolute prefix (differentiating, |
47926f60 | 7110 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
7111 | if (*op_string == ABSOLUTE_PREFIX) |
7112 | { | |
7113 | ++op_string; | |
7114 | if (is_space_char (*op_string)) | |
7115 | ++op_string; | |
40fb9820 | 7116 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 7117 | } |
252b5132 | 7118 | |
47926f60 | 7119 | /* Check if operand is a register. */ |
4d1bb795 | 7120 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 7121 | { |
40fb9820 L |
7122 | i386_operand_type temp; |
7123 | ||
24eab124 AM |
7124 | /* Check for a segment override by searching for ':' after a |
7125 | segment register. */ | |
7126 | op_string = end_op; | |
7127 | if (is_space_char (*op_string)) | |
7128 | ++op_string; | |
40fb9820 L |
7129 | if (*op_string == ':' |
7130 | && (r->reg_type.bitfield.sreg2 | |
7131 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
7132 | { |
7133 | switch (r->reg_num) | |
7134 | { | |
7135 | case 0: | |
7136 | i.seg[i.mem_operands] = &es; | |
7137 | break; | |
7138 | case 1: | |
7139 | i.seg[i.mem_operands] = &cs; | |
7140 | break; | |
7141 | case 2: | |
7142 | i.seg[i.mem_operands] = &ss; | |
7143 | break; | |
7144 | case 3: | |
7145 | i.seg[i.mem_operands] = &ds; | |
7146 | break; | |
7147 | case 4: | |
7148 | i.seg[i.mem_operands] = &fs; | |
7149 | break; | |
7150 | case 5: | |
7151 | i.seg[i.mem_operands] = &gs; | |
7152 | break; | |
7153 | } | |
252b5132 | 7154 | |
24eab124 | 7155 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
7156 | ++op_string; |
7157 | if (is_space_char (*op_string)) | |
24eab124 | 7158 | ++op_string; |
252b5132 | 7159 | |
24eab124 AM |
7160 | if (!is_digit_char (*op_string) |
7161 | && !is_identifier_char (*op_string) | |
7162 | && *op_string != '(' | |
7163 | && *op_string != ABSOLUTE_PREFIX) | |
7164 | { | |
7165 | as_bad (_("bad memory operand `%s'"), op_string); | |
7166 | return 0; | |
7167 | } | |
47926f60 | 7168 | /* Handle case of %es:*foo. */ |
24eab124 AM |
7169 | if (*op_string == ABSOLUTE_PREFIX) |
7170 | { | |
7171 | ++op_string; | |
7172 | if (is_space_char (*op_string)) | |
7173 | ++op_string; | |
40fb9820 | 7174 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
7175 | } |
7176 | goto do_memory_reference; | |
7177 | } | |
7178 | if (*op_string) | |
7179 | { | |
d0b47220 | 7180 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
7181 | return 0; |
7182 | } | |
40fb9820 L |
7183 | temp = r->reg_type; |
7184 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
7185 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
7186 | temp); | |
7d5e4556 | 7187 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 7188 | i.op[this_operand].regs = r; |
24eab124 AM |
7189 | i.reg_operands++; |
7190 | } | |
af6bdddf AM |
7191 | else if (*op_string == REGISTER_PREFIX) |
7192 | { | |
7193 | as_bad (_("bad register name `%s'"), op_string); | |
7194 | return 0; | |
7195 | } | |
24eab124 | 7196 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 7197 | { |
24eab124 | 7198 | ++op_string; |
40fb9820 | 7199 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 7200 | { |
d0b47220 | 7201 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
7202 | return 0; |
7203 | } | |
7204 | if (!i386_immediate (op_string)) | |
7205 | return 0; | |
7206 | } | |
7207 | else if (is_digit_char (*op_string) | |
7208 | || is_identifier_char (*op_string) | |
e5cb08ac | 7209 | || *op_string == '(') |
24eab124 | 7210 | { |
47926f60 | 7211 | /* This is a memory reference of some sort. */ |
af6bdddf | 7212 | char *base_string; |
252b5132 | 7213 | |
47926f60 | 7214 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
7215 | char *displacement_string_start; |
7216 | char *displacement_string_end; | |
252b5132 | 7217 | |
24eab124 | 7218 | do_memory_reference: |
24eab124 | 7219 | if ((i.mem_operands == 1 |
40fb9820 | 7220 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
7221 | || i.mem_operands == 2) |
7222 | { | |
7223 | as_bad (_("too many memory references for `%s'"), | |
7224 | current_templates->start->name); | |
7225 | return 0; | |
7226 | } | |
252b5132 | 7227 | |
24eab124 AM |
7228 | /* Check for base index form. We detect the base index form by |
7229 | looking for an ')' at the end of the operand, searching | |
7230 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
7231 | after the '('. */ | |
af6bdddf | 7232 | base_string = op_string + strlen (op_string); |
c3332e24 | 7233 | |
af6bdddf AM |
7234 | --base_string; |
7235 | if (is_space_char (*base_string)) | |
7236 | --base_string; | |
252b5132 | 7237 | |
47926f60 | 7238 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
7239 | displacement_string_start = op_string; |
7240 | displacement_string_end = base_string + 1; | |
252b5132 | 7241 | |
24eab124 AM |
7242 | if (*base_string == ')') |
7243 | { | |
af6bdddf | 7244 | char *temp_string; |
24eab124 AM |
7245 | unsigned int parens_balanced = 1; |
7246 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 7247 | equal, so this loop will not be infinite. */ |
24eab124 AM |
7248 | do |
7249 | { | |
7250 | base_string--; | |
7251 | if (*base_string == ')') | |
7252 | parens_balanced++; | |
7253 | if (*base_string == '(') | |
7254 | parens_balanced--; | |
7255 | } | |
7256 | while (parens_balanced); | |
c3332e24 | 7257 | |
af6bdddf | 7258 | temp_string = base_string; |
c3332e24 | 7259 | |
24eab124 | 7260 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
7261 | ++base_string; |
7262 | if (is_space_char (*base_string)) | |
24eab124 | 7263 | ++base_string; |
252b5132 | 7264 | |
af6bdddf | 7265 | if (*base_string == ',' |
4eed87de AM |
7266 | || ((i.base_reg = parse_register (base_string, &end_op)) |
7267 | != NULL)) | |
252b5132 | 7268 | { |
af6bdddf | 7269 | displacement_string_end = temp_string; |
252b5132 | 7270 | |
40fb9820 | 7271 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 7272 | |
af6bdddf | 7273 | if (i.base_reg) |
24eab124 | 7274 | { |
24eab124 AM |
7275 | base_string = end_op; |
7276 | if (is_space_char (*base_string)) | |
7277 | ++base_string; | |
af6bdddf AM |
7278 | } |
7279 | ||
7280 | /* There may be an index reg or scale factor here. */ | |
7281 | if (*base_string == ',') | |
7282 | { | |
7283 | ++base_string; | |
7284 | if (is_space_char (*base_string)) | |
7285 | ++base_string; | |
7286 | ||
4eed87de AM |
7287 | if ((i.index_reg = parse_register (base_string, &end_op)) |
7288 | != NULL) | |
24eab124 | 7289 | { |
af6bdddf | 7290 | base_string = end_op; |
24eab124 AM |
7291 | if (is_space_char (*base_string)) |
7292 | ++base_string; | |
af6bdddf AM |
7293 | if (*base_string == ',') |
7294 | { | |
7295 | ++base_string; | |
7296 | if (is_space_char (*base_string)) | |
7297 | ++base_string; | |
7298 | } | |
e5cb08ac | 7299 | else if (*base_string != ')') |
af6bdddf | 7300 | { |
4eed87de AM |
7301 | as_bad (_("expecting `,' or `)' " |
7302 | "after index register in `%s'"), | |
af6bdddf AM |
7303 | operand_string); |
7304 | return 0; | |
7305 | } | |
24eab124 | 7306 | } |
af6bdddf | 7307 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 7308 | { |
af6bdddf | 7309 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
7310 | return 0; |
7311 | } | |
252b5132 | 7312 | |
47926f60 | 7313 | /* Check for scale factor. */ |
551c1ca1 | 7314 | if (*base_string != ')') |
af6bdddf | 7315 | { |
551c1ca1 AM |
7316 | char *end_scale = i386_scale (base_string); |
7317 | ||
7318 | if (!end_scale) | |
af6bdddf | 7319 | return 0; |
24eab124 | 7320 | |
551c1ca1 | 7321 | base_string = end_scale; |
af6bdddf AM |
7322 | if (is_space_char (*base_string)) |
7323 | ++base_string; | |
7324 | if (*base_string != ')') | |
7325 | { | |
4eed87de AM |
7326 | as_bad (_("expecting `)' " |
7327 | "after scale factor in `%s'"), | |
af6bdddf AM |
7328 | operand_string); |
7329 | return 0; | |
7330 | } | |
7331 | } | |
7332 | else if (!i.index_reg) | |
24eab124 | 7333 | { |
4eed87de AM |
7334 | as_bad (_("expecting index register or scale factor " |
7335 | "after `,'; got '%c'"), | |
af6bdddf | 7336 | *base_string); |
24eab124 AM |
7337 | return 0; |
7338 | } | |
7339 | } | |
af6bdddf | 7340 | else if (*base_string != ')') |
24eab124 | 7341 | { |
4eed87de AM |
7342 | as_bad (_("expecting `,' or `)' " |
7343 | "after base register in `%s'"), | |
af6bdddf | 7344 | operand_string); |
24eab124 AM |
7345 | return 0; |
7346 | } | |
c3332e24 | 7347 | } |
af6bdddf | 7348 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 7349 | { |
af6bdddf | 7350 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 7351 | return 0; |
c3332e24 | 7352 | } |
24eab124 AM |
7353 | } |
7354 | ||
7355 | /* If there's an expression beginning the operand, parse it, | |
7356 | assuming displacement_string_start and | |
7357 | displacement_string_end are meaningful. */ | |
7358 | if (displacement_string_start != displacement_string_end) | |
7359 | { | |
7360 | if (!i386_displacement (displacement_string_start, | |
7361 | displacement_string_end)) | |
7362 | return 0; | |
7363 | } | |
7364 | ||
7365 | /* Special case for (%dx) while doing input/output op. */ | |
7366 | if (i.base_reg | |
0dfbf9d7 L |
7367 | && operand_type_equal (&i.base_reg->reg_type, |
7368 | ®16_inoutportreg) | |
24eab124 AM |
7369 | && i.index_reg == 0 |
7370 | && i.log2_scale_factor == 0 | |
7371 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 7372 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 7373 | { |
65da13b5 | 7374 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
7375 | return 1; |
7376 | } | |
7377 | ||
eecb386c AM |
7378 | if (i386_index_check (operand_string) == 0) |
7379 | return 0; | |
5c07affc | 7380 | i.types[this_operand].bitfield.mem = 1; |
24eab124 AM |
7381 | i.mem_operands++; |
7382 | } | |
7383 | else | |
ce8a8b2f AM |
7384 | { |
7385 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
7386 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
7387 | output_invalid (*op_string), | |
7388 | this_operand + 1, | |
7389 | op_string); | |
7390 | return 0; | |
7391 | } | |
47926f60 | 7392 | return 1; /* Normal return. */ |
252b5132 RH |
7393 | } |
7394 | \f | |
ee7fcc42 AM |
7395 | /* md_estimate_size_before_relax() |
7396 | ||
7397 | Called just before relax() for rs_machine_dependent frags. The x86 | |
7398 | assembler uses these frags to handle variable size jump | |
7399 | instructions. | |
7400 | ||
7401 | Any symbol that is now undefined will not become defined. | |
7402 | Return the correct fr_subtype in the frag. | |
7403 | Return the initial "guess for variable size of frag" to caller. | |
7404 | The guess is actually the growth beyond the fixed part. Whatever | |
7405 | we do to grow the fixed or variable part contributes to our | |
7406 | returned value. */ | |
7407 | ||
252b5132 RH |
7408 | int |
7409 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
7410 | fragS *fragP; |
7411 | segT segment; | |
252b5132 | 7412 | { |
252b5132 | 7413 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
7414 | check for un-relaxable symbols. On an ELF system, we can't relax |
7415 | an externally visible symbol, because it may be overridden by a | |
7416 | shared library. */ | |
7417 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 7418 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7419 | || (IS_ELF |
31312f95 AM |
7420 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
7421 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
7422 | #endif |
7423 | ) | |
252b5132 | 7424 | { |
b98ef147 AM |
7425 | /* Symbol is undefined in this segment, or we need to keep a |
7426 | reloc so that weak symbols can be overridden. */ | |
7427 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 7428 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
7429 | unsigned char *opcode; |
7430 | int old_fr_fix; | |
f6af82bd | 7431 | |
ee7fcc42 AM |
7432 | if (fragP->fr_var != NO_RELOC) |
7433 | reloc_type = fragP->fr_var; | |
b98ef147 | 7434 | else if (size == 2) |
f6af82bd AM |
7435 | reloc_type = BFD_RELOC_16_PCREL; |
7436 | else | |
7437 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 7438 | |
ee7fcc42 AM |
7439 | old_fr_fix = fragP->fr_fix; |
7440 | opcode = (unsigned char *) fragP->fr_opcode; | |
7441 | ||
fddf5b5b | 7442 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 7443 | { |
fddf5b5b AM |
7444 | case UNCOND_JUMP: |
7445 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 7446 | opcode[0] = 0xe9; |
252b5132 | 7447 | fragP->fr_fix += size; |
062cd5e7 AS |
7448 | fix_new (fragP, old_fr_fix, size, |
7449 | fragP->fr_symbol, | |
7450 | fragP->fr_offset, 1, | |
7451 | reloc_type); | |
252b5132 RH |
7452 | break; |
7453 | ||
fddf5b5b | 7454 | case COND_JUMP86: |
412167cb AM |
7455 | if (size == 2 |
7456 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
7457 | { |
7458 | /* Negate the condition, and branch past an | |
7459 | unconditional jump. */ | |
7460 | opcode[0] ^= 1; | |
7461 | opcode[1] = 3; | |
7462 | /* Insert an unconditional jump. */ | |
7463 | opcode[2] = 0xe9; | |
7464 | /* We added two extra opcode bytes, and have a two byte | |
7465 | offset. */ | |
7466 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
7467 | fix_new (fragP, old_fr_fix + 2, 2, |
7468 | fragP->fr_symbol, | |
7469 | fragP->fr_offset, 1, | |
7470 | reloc_type); | |
fddf5b5b AM |
7471 | break; |
7472 | } | |
7473 | /* Fall through. */ | |
7474 | ||
7475 | case COND_JUMP: | |
412167cb AM |
7476 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
7477 | { | |
3e02c1cc AM |
7478 | fixS *fixP; |
7479 | ||
412167cb | 7480 | fragP->fr_fix += 1; |
3e02c1cc AM |
7481 | fixP = fix_new (fragP, old_fr_fix, 1, |
7482 | fragP->fr_symbol, | |
7483 | fragP->fr_offset, 1, | |
7484 | BFD_RELOC_8_PCREL); | |
7485 | fixP->fx_signed = 1; | |
412167cb AM |
7486 | break; |
7487 | } | |
93c2a809 | 7488 | |
24eab124 | 7489 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 7490 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 7491 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 7492 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
7493 | /* We've added an opcode byte. */ |
7494 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
7495 | fix_new (fragP, old_fr_fix + 1, size, |
7496 | fragP->fr_symbol, | |
7497 | fragP->fr_offset, 1, | |
7498 | reloc_type); | |
252b5132 | 7499 | break; |
fddf5b5b AM |
7500 | |
7501 | default: | |
7502 | BAD_CASE (fragP->fr_subtype); | |
7503 | break; | |
252b5132 RH |
7504 | } |
7505 | frag_wane (fragP); | |
ee7fcc42 | 7506 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 7507 | } |
93c2a809 | 7508 | |
93c2a809 AM |
7509 | /* Guess size depending on current relax state. Initially the relax |
7510 | state will correspond to a short jump and we return 1, because | |
7511 | the variable part of the frag (the branch offset) is one byte | |
7512 | long. However, we can relax a section more than once and in that | |
7513 | case we must either set fr_subtype back to the unrelaxed state, | |
7514 | or return the value for the appropriate branch. */ | |
7515 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
7516 | } |
7517 | ||
47926f60 KH |
7518 | /* Called after relax() is finished. |
7519 | ||
7520 | In: Address of frag. | |
7521 | fr_type == rs_machine_dependent. | |
7522 | fr_subtype is what the address relaxed to. | |
7523 | ||
7524 | Out: Any fixSs and constants are set up. | |
7525 | Caller will turn frag into a ".space 0". */ | |
7526 | ||
252b5132 RH |
7527 | void |
7528 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
7529 | bfd *abfd ATTRIBUTE_UNUSED; |
7530 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 7531 | fragS *fragP; |
252b5132 | 7532 | { |
29b0f896 | 7533 | unsigned char *opcode; |
252b5132 | 7534 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
7535 | offsetT target_address; |
7536 | offsetT opcode_address; | |
252b5132 | 7537 | unsigned int extension = 0; |
847f7ad4 | 7538 | offsetT displacement_from_opcode_start; |
252b5132 RH |
7539 | |
7540 | opcode = (unsigned char *) fragP->fr_opcode; | |
7541 | ||
47926f60 | 7542 | /* Address we want to reach in file space. */ |
252b5132 | 7543 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 7544 | |
47926f60 | 7545 | /* Address opcode resides at in file space. */ |
252b5132 RH |
7546 | opcode_address = fragP->fr_address + fragP->fr_fix; |
7547 | ||
47926f60 | 7548 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
7549 | displacement_from_opcode_start = target_address - opcode_address; |
7550 | ||
fddf5b5b | 7551 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 7552 | { |
47926f60 KH |
7553 | /* Don't have to change opcode. */ |
7554 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 7555 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
7556 | } |
7557 | else | |
7558 | { | |
7559 | if (no_cond_jump_promotion | |
7560 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
7561 | as_warn_where (fragP->fr_file, fragP->fr_line, |
7562 | _("long jump required")); | |
252b5132 | 7563 | |
fddf5b5b AM |
7564 | switch (fragP->fr_subtype) |
7565 | { | |
7566 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
7567 | extension = 4; /* 1 opcode + 4 displacement */ | |
7568 | opcode[0] = 0xe9; | |
7569 | where_to_put_displacement = &opcode[1]; | |
7570 | break; | |
252b5132 | 7571 | |
fddf5b5b AM |
7572 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
7573 | extension = 2; /* 1 opcode + 2 displacement */ | |
7574 | opcode[0] = 0xe9; | |
7575 | where_to_put_displacement = &opcode[1]; | |
7576 | break; | |
252b5132 | 7577 | |
fddf5b5b AM |
7578 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
7579 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
7580 | extension = 5; /* 2 opcode + 4 displacement */ | |
7581 | opcode[1] = opcode[0] + 0x10; | |
7582 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7583 | where_to_put_displacement = &opcode[2]; | |
7584 | break; | |
252b5132 | 7585 | |
fddf5b5b AM |
7586 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
7587 | extension = 3; /* 2 opcode + 2 displacement */ | |
7588 | opcode[1] = opcode[0] + 0x10; | |
7589 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7590 | where_to_put_displacement = &opcode[2]; | |
7591 | break; | |
252b5132 | 7592 | |
fddf5b5b AM |
7593 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
7594 | extension = 4; | |
7595 | opcode[0] ^= 1; | |
7596 | opcode[1] = 3; | |
7597 | opcode[2] = 0xe9; | |
7598 | where_to_put_displacement = &opcode[3]; | |
7599 | break; | |
7600 | ||
7601 | default: | |
7602 | BAD_CASE (fragP->fr_subtype); | |
7603 | break; | |
7604 | } | |
252b5132 | 7605 | } |
fddf5b5b | 7606 | |
7b81dfbb AJ |
7607 | /* If size if less then four we are sure that the operand fits, |
7608 | but if it's 4, then it could be that the displacement is larger | |
7609 | then -/+ 2GB. */ | |
7610 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
7611 | && object_64bit | |
7612 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
7613 | + ((addressT) 1 << 31)) |
7614 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
7615 | { |
7616 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
7617 | _("jump target out of range")); | |
7618 | /* Make us emit 0. */ | |
7619 | displacement_from_opcode_start = extension; | |
7620 | } | |
47926f60 | 7621 | /* Now put displacement after opcode. */ |
252b5132 RH |
7622 | md_number_to_chars ((char *) where_to_put_displacement, |
7623 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 7624 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
7625 | fragP->fr_fix += extension; |
7626 | } | |
7627 | \f | |
252b5132 RH |
7628 | /* Apply a fixup (fixS) to segment data, once it has been determined |
7629 | by our caller that we have all the info we need to fix it up. | |
7630 | ||
7631 | On the 386, immediates, displacements, and data pointers are all in | |
7632 | the same (little-endian) format, so we don't need to care about which | |
7633 | we are handling. */ | |
7634 | ||
94f592af | 7635 | void |
55cf6793 | 7636 | md_apply_fix (fixP, valP, seg) |
47926f60 KH |
7637 | /* The fix we're to put in. */ |
7638 | fixS *fixP; | |
47926f60 | 7639 | /* Pointer to the value of the bits. */ |
c6682705 | 7640 | valueT *valP; |
47926f60 KH |
7641 | /* Segment fix is from. */ |
7642 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 7643 | { |
94f592af | 7644 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 7645 | valueT value = *valP; |
252b5132 | 7646 | |
f86103b7 | 7647 | #if !defined (TE_Mach) |
93382f6d AM |
7648 | if (fixP->fx_pcrel) |
7649 | { | |
7650 | switch (fixP->fx_r_type) | |
7651 | { | |
5865bb77 ILT |
7652 | default: |
7653 | break; | |
7654 | ||
d6ab8113 JB |
7655 | case BFD_RELOC_64: |
7656 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
7657 | break; | |
93382f6d | 7658 | case BFD_RELOC_32: |
ae8887b5 | 7659 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
7660 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
7661 | break; | |
7662 | case BFD_RELOC_16: | |
7663 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
7664 | break; | |
7665 | case BFD_RELOC_8: | |
7666 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
7667 | break; | |
7668 | } | |
7669 | } | |
252b5132 | 7670 | |
a161fe53 | 7671 | if (fixP->fx_addsy != NULL |
31312f95 | 7672 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 7673 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
7674 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
7675 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
7676 | && !use_rela_relocations) | |
252b5132 | 7677 | { |
31312f95 AM |
7678 | /* This is a hack. There should be a better way to handle this. |
7679 | This covers for the fact that bfd_install_relocation will | |
7680 | subtract the current location (for partial_inplace, PC relative | |
7681 | relocations); see more below. */ | |
252b5132 | 7682 | #ifndef OBJ_AOUT |
718ddfc0 | 7683 | if (IS_ELF |
252b5132 RH |
7684 | #ifdef TE_PE |
7685 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
7686 | #endif | |
7687 | ) | |
7688 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7689 | #endif | |
7690 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 7691 | if (IS_ELF) |
252b5132 | 7692 | { |
6539b54b | 7693 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 7694 | |
6539b54b | 7695 | if ((sym_seg == seg |
2f66722d | 7696 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 7697 | && sym_seg != absolute_section)) |
ae6063d4 | 7698 | && !generic_force_reloc (fixP)) |
2f66722d AM |
7699 | { |
7700 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
7701 | bfd_install_relocation subtracts them out again. I think |
7702 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
7703 | it. FIXME. */ |
7704 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7705 | } | |
252b5132 RH |
7706 | } |
7707 | #endif | |
7708 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
7709 | /* For some reason, the PE format does not store a |
7710 | section address offset for a PC relative symbol. */ | |
7711 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 7712 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
7713 | value += md_pcrel_from (fixP); |
7714 | #endif | |
7715 | } | |
7716 | ||
7717 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 7718 | and we must not disappoint it. */ |
252b5132 | 7719 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7720 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
7721 | switch (fixP->fx_r_type) |
7722 | { | |
7723 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 7724 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
7725 | /* Make the jump instruction point to the address of the operand. At |
7726 | runtime we merely add the offset to the actual PLT entry. */ | |
7727 | value = -4; | |
7728 | break; | |
31312f95 | 7729 | |
13ae64f3 JJ |
7730 | case BFD_RELOC_386_TLS_GD: |
7731 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 7732 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
7733 | case BFD_RELOC_386_TLS_IE: |
7734 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 7735 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
7736 | case BFD_RELOC_X86_64_TLSGD: |
7737 | case BFD_RELOC_X86_64_TLSLD: | |
7738 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 7739 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
7740 | value = 0; /* Fully resolved at runtime. No addend. */ |
7741 | /* Fallthrough */ | |
7742 | case BFD_RELOC_386_TLS_LE: | |
7743 | case BFD_RELOC_386_TLS_LDO_32: | |
7744 | case BFD_RELOC_386_TLS_LE_32: | |
7745 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 7746 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 7747 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 7748 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
7749 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
7750 | break; | |
7751 | ||
67a4f2b7 AO |
7752 | case BFD_RELOC_386_TLS_DESC_CALL: |
7753 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
7754 | value = 0; /* Fully resolved at runtime. No addend. */ | |
7755 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7756 | fixP->fx_done = 0; | |
7757 | return; | |
7758 | ||
00f7efb6 JJ |
7759 | case BFD_RELOC_386_GOT32: |
7760 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
7761 | value = 0; /* Fully resolved at runtime. No addend. */ |
7762 | break; | |
47926f60 KH |
7763 | |
7764 | case BFD_RELOC_VTABLE_INHERIT: | |
7765 | case BFD_RELOC_VTABLE_ENTRY: | |
7766 | fixP->fx_done = 0; | |
94f592af | 7767 | return; |
47926f60 KH |
7768 | |
7769 | default: | |
7770 | break; | |
7771 | } | |
7772 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 7773 | *valP = value; |
f86103b7 | 7774 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 7775 | |
3e73aa7c | 7776 | /* Are we finished with this relocation now? */ |
c6682705 | 7777 | if (fixP->fx_addsy == NULL) |
3e73aa7c JH |
7778 | fixP->fx_done = 1; |
7779 | else if (use_rela_relocations) | |
7780 | { | |
7781 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
7782 | /* Remember value for tc_gen_reloc. */ |
7783 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
7784 | value = 0; |
7785 | } | |
f86103b7 | 7786 | |
94f592af | 7787 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 7788 | } |
252b5132 | 7789 | \f |
252b5132 | 7790 | char * |
499ac353 | 7791 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 7792 | { |
499ac353 NC |
7793 | /* This outputs the LITTLENUMs in REVERSE order; |
7794 | in accord with the bigendian 386. */ | |
7795 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
7796 | } |
7797 | \f | |
2d545b82 | 7798 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 7799 | |
252b5132 | 7800 | static char * |
e3bb37b5 | 7801 | output_invalid (int c) |
252b5132 | 7802 | { |
3882b010 | 7803 | if (ISPRINT (c)) |
f9f21a03 L |
7804 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
7805 | "'%c'", c); | |
252b5132 | 7806 | else |
f9f21a03 | 7807 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 7808 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
7809 | return output_invalid_buf; |
7810 | } | |
7811 | ||
af6bdddf | 7812 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
7813 | |
7814 | static const reg_entry * | |
4d1bb795 | 7815 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 7816 | { |
af6bdddf AM |
7817 | char *s = reg_string; |
7818 | char *p; | |
252b5132 RH |
7819 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
7820 | const reg_entry *r; | |
7821 | ||
7822 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
7823 | if (*s == REGISTER_PREFIX) | |
7824 | ++s; | |
7825 | ||
7826 | if (is_space_char (*s)) | |
7827 | ++s; | |
7828 | ||
7829 | p = reg_name_given; | |
af6bdddf | 7830 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
7831 | { |
7832 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
7833 | return (const reg_entry *) NULL; |
7834 | s++; | |
252b5132 RH |
7835 | } |
7836 | ||
6588847e DN |
7837 | /* For naked regs, make sure that we are not dealing with an identifier. |
7838 | This prevents confusing an identifier like `eax_var' with register | |
7839 | `eax'. */ | |
7840 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
7841 | return (const reg_entry *) NULL; | |
7842 | ||
af6bdddf | 7843 | *end_op = s; |
252b5132 RH |
7844 | |
7845 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
7846 | ||
5f47d35b | 7847 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 7848 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 7849 | { |
5f47d35b AM |
7850 | if (is_space_char (*s)) |
7851 | ++s; | |
7852 | if (*s == '(') | |
7853 | { | |
af6bdddf | 7854 | ++s; |
5f47d35b AM |
7855 | if (is_space_char (*s)) |
7856 | ++s; | |
7857 | if (*s >= '0' && *s <= '7') | |
7858 | { | |
db557034 | 7859 | int fpr = *s - '0'; |
af6bdddf | 7860 | ++s; |
5f47d35b AM |
7861 | if (is_space_char (*s)) |
7862 | ++s; | |
7863 | if (*s == ')') | |
7864 | { | |
7865 | *end_op = s + 1; | |
db557034 AM |
7866 | r = hash_find (reg_hash, "st(0)"); |
7867 | know (r); | |
7868 | return r + fpr; | |
5f47d35b | 7869 | } |
5f47d35b | 7870 | } |
47926f60 | 7871 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
7872 | return (const reg_entry *) NULL; |
7873 | } | |
7874 | } | |
7875 | ||
a60de03c JB |
7876 | if (r == NULL || allow_pseudo_reg) |
7877 | return r; | |
7878 | ||
0dfbf9d7 | 7879 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
7880 | return (const reg_entry *) NULL; |
7881 | ||
192dc9c6 JB |
7882 | if ((r->reg_type.bitfield.reg32 |
7883 | || r->reg_type.bitfield.sreg3 | |
7884 | || r->reg_type.bitfield.control | |
7885 | || r->reg_type.bitfield.debug | |
7886 | || r->reg_type.bitfield.test) | |
7887 | && !cpu_arch_flags.bitfield.cpui386) | |
7888 | return (const reg_entry *) NULL; | |
7889 | ||
7890 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) | |
7891 | return (const reg_entry *) NULL; | |
7892 | ||
7893 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) | |
7894 | return (const reg_entry *) NULL; | |
7895 | ||
40f12533 L |
7896 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) |
7897 | return (const reg_entry *) NULL; | |
7898 | ||
db51cc60 | 7899 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 7900 | if (!allow_index_reg |
db51cc60 L |
7901 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
7902 | return (const reg_entry *) NULL; | |
7903 | ||
a60de03c JB |
7904 | if (((r->reg_flags & (RegRex64 | RegRex)) |
7905 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 7906 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 7907 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 7908 | && flag_code != CODE_64BIT) |
20f0a1fc | 7909 | return (const reg_entry *) NULL; |
1ae00879 | 7910 | |
b7240065 JB |
7911 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
7912 | return (const reg_entry *) NULL; | |
7913 | ||
252b5132 RH |
7914 | return r; |
7915 | } | |
4d1bb795 JB |
7916 | |
7917 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
7918 | ||
7919 | static const reg_entry * | |
7920 | parse_register (char *reg_string, char **end_op) | |
7921 | { | |
7922 | const reg_entry *r; | |
7923 | ||
7924 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
7925 | r = parse_real_register (reg_string, end_op); | |
7926 | else | |
7927 | r = NULL; | |
7928 | if (!r) | |
7929 | { | |
7930 | char *save = input_line_pointer; | |
7931 | char c; | |
7932 | symbolS *symbolP; | |
7933 | ||
7934 | input_line_pointer = reg_string; | |
7935 | c = get_symbol_end (); | |
7936 | symbolP = symbol_find (reg_string); | |
7937 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
7938 | { | |
7939 | const expressionS *e = symbol_get_value_expression (symbolP); | |
7940 | ||
7941 | know (e->X_op == O_register); | |
4eed87de | 7942 | know (e->X_add_number >= 0 |
c3fe08fa | 7943 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
7944 | r = i386_regtab + e->X_add_number; |
7945 | *end_op = input_line_pointer; | |
7946 | } | |
7947 | *input_line_pointer = c; | |
7948 | input_line_pointer = save; | |
7949 | } | |
7950 | return r; | |
7951 | } | |
7952 | ||
7953 | int | |
7954 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
7955 | { | |
7956 | const reg_entry *r; | |
7957 | char *end = input_line_pointer; | |
7958 | ||
7959 | *end = *nextcharP; | |
7960 | r = parse_register (name, &input_line_pointer); | |
7961 | if (r && end <= input_line_pointer) | |
7962 | { | |
7963 | *nextcharP = *input_line_pointer; | |
7964 | *input_line_pointer = 0; | |
7965 | e->X_op = O_register; | |
7966 | e->X_add_number = r - i386_regtab; | |
7967 | return 1; | |
7968 | } | |
7969 | input_line_pointer = end; | |
7970 | *end = 0; | |
7971 | return 0; | |
7972 | } | |
7973 | ||
7974 | void | |
7975 | md_operand (expressionS *e) | |
7976 | { | |
7977 | if (*input_line_pointer == REGISTER_PREFIX) | |
7978 | { | |
7979 | char *end; | |
7980 | const reg_entry *r = parse_real_register (input_line_pointer, &end); | |
7981 | ||
7982 | if (r) | |
7983 | { | |
7984 | e->X_op = O_register; | |
7985 | e->X_add_number = r - i386_regtab; | |
7986 | input_line_pointer = end; | |
7987 | } | |
7988 | } | |
7989 | } | |
7990 | ||
252b5132 | 7991 | \f |
4cc782b5 | 7992 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 7993 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 7994 | #else |
12b55ccc | 7995 | const char *md_shortopts = "qn"; |
252b5132 | 7996 | #endif |
6e0b89ee | 7997 | |
3e73aa7c | 7998 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
7999 | #define OPTION_64 (OPTION_MD_BASE + 1) |
8000 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
8001 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
8002 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
8003 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
8004 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
8005 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
8006 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
8007 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 8008 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 8009 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
b3b91714 | 8010 | |
99ad8390 NC |
8011 | struct option md_longopts[] = |
8012 | { | |
3e73aa7c | 8013 | {"32", no_argument, NULL, OPTION_32}, |
99ad8390 | 8014 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
3e73aa7c | 8015 | {"64", no_argument, NULL, OPTION_64}, |
6e0b89ee | 8016 | #endif |
b3b91714 | 8017 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
8018 | {"march", required_argument, NULL, OPTION_MARCH}, |
8019 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
8020 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
8021 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
8022 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
8023 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
8024 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 8025 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 8026 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
252b5132 RH |
8027 | {NULL, no_argument, NULL, 0} |
8028 | }; | |
8029 | size_t md_longopts_size = sizeof (md_longopts); | |
8030 | ||
8031 | int | |
9103f4f4 | 8032 | md_parse_option (int c, char *arg) |
252b5132 | 8033 | { |
9103f4f4 | 8034 | unsigned int i; |
6305a203 | 8035 | char *arch, *next; |
9103f4f4 | 8036 | |
252b5132 RH |
8037 | switch (c) |
8038 | { | |
12b55ccc L |
8039 | case 'n': |
8040 | optimize_align_code = 0; | |
8041 | break; | |
8042 | ||
a38cf1db AM |
8043 | case 'q': |
8044 | quiet_warnings = 1; | |
252b5132 RH |
8045 | break; |
8046 | ||
8047 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
8048 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
8049 | should be emitted or not. FIXME: Not implemented. */ | |
8050 | case 'Q': | |
252b5132 RH |
8051 | break; |
8052 | ||
8053 | /* -V: SVR4 argument to print version ID. */ | |
8054 | case 'V': | |
8055 | print_version_id (); | |
8056 | break; | |
8057 | ||
a38cf1db AM |
8058 | /* -k: Ignore for FreeBSD compatibility. */ |
8059 | case 'k': | |
252b5132 | 8060 | break; |
4cc782b5 ILT |
8061 | |
8062 | case 's': | |
8063 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 8064 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 8065 | break; |
99ad8390 NC |
8066 | #endif |
8067 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) | |
3e73aa7c JH |
8068 | case OPTION_64: |
8069 | { | |
8070 | const char **list, **l; | |
8071 | ||
3e73aa7c JH |
8072 | list = bfd_target_list (); |
8073 | for (l = list; *l != NULL; l++) | |
8620418b | 8074 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
8075 | || strcmp (*l, "coff-x86-64") == 0 |
8076 | || strcmp (*l, "pe-x86-64") == 0 | |
8077 | || strcmp (*l, "pei-x86-64") == 0) | |
6e0b89ee AM |
8078 | { |
8079 | default_arch = "x86_64"; | |
8080 | break; | |
8081 | } | |
3e73aa7c | 8082 | if (*l == NULL) |
6e0b89ee | 8083 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
8084 | free (list); |
8085 | } | |
8086 | break; | |
8087 | #endif | |
252b5132 | 8088 | |
6e0b89ee AM |
8089 | case OPTION_32: |
8090 | default_arch = "i386"; | |
8091 | break; | |
8092 | ||
b3b91714 AM |
8093 | case OPTION_DIVIDE: |
8094 | #ifdef SVR4_COMMENT_CHARS | |
8095 | { | |
8096 | char *n, *t; | |
8097 | const char *s; | |
8098 | ||
8099 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
8100 | t = n; | |
8101 | for (s = i386_comment_chars; *s != '\0'; s++) | |
8102 | if (*s != '/') | |
8103 | *t++ = *s; | |
8104 | *t = '\0'; | |
8105 | i386_comment_chars = n; | |
8106 | } | |
8107 | #endif | |
8108 | break; | |
8109 | ||
9103f4f4 | 8110 | case OPTION_MARCH: |
6305a203 L |
8111 | arch = xstrdup (arg); |
8112 | do | |
9103f4f4 | 8113 | { |
6305a203 L |
8114 | if (*arch == '.') |
8115 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
8116 | next = strchr (arch, '+'); | |
8117 | if (next) | |
8118 | *next++ = '\0'; | |
8119 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
9103f4f4 | 8120 | { |
6305a203 | 8121 | if (strcmp (arch, cpu_arch [i].name) == 0) |
ccc9c027 | 8122 | { |
6305a203 L |
8123 | /* Processor. */ |
8124 | cpu_arch_name = cpu_arch[i].name; | |
8125 | cpu_sub_arch_name = NULL; | |
8126 | cpu_arch_flags = cpu_arch[i].flags; | |
8127 | cpu_arch_isa = cpu_arch[i].type; | |
8128 | cpu_arch_isa_flags = cpu_arch[i].flags; | |
8129 | if (!cpu_arch_tune_set) | |
8130 | { | |
8131 | cpu_arch_tune = cpu_arch_isa; | |
8132 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
8133 | } | |
8134 | break; | |
8135 | } | |
8136 | else if (*cpu_arch [i].name == '.' | |
8137 | && strcmp (arch, cpu_arch [i].name + 1) == 0) | |
8138 | { | |
8139 | /* ISA entension. */ | |
8140 | i386_cpu_flags flags; | |
8141 | flags = cpu_flags_or (cpu_arch_flags, | |
8142 | cpu_arch[i].flags); | |
0dfbf9d7 | 8143 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
8144 | { |
8145 | if (cpu_sub_arch_name) | |
8146 | { | |
8147 | char *name = cpu_sub_arch_name; | |
8148 | cpu_sub_arch_name = concat (name, | |
8149 | cpu_arch[i].name, | |
1bf57e9f | 8150 | (const char *) NULL); |
6305a203 L |
8151 | free (name); |
8152 | } | |
8153 | else | |
8154 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
8155 | cpu_arch_flags = flags; | |
8156 | } | |
8157 | break; | |
ccc9c027 | 8158 | } |
9103f4f4 | 8159 | } |
6305a203 L |
8160 | |
8161 | if (i >= ARRAY_SIZE (cpu_arch)) | |
8162 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
8163 | ||
8164 | arch = next; | |
9103f4f4 | 8165 | } |
6305a203 | 8166 | while (next != NULL ); |
9103f4f4 L |
8167 | break; |
8168 | ||
8169 | case OPTION_MTUNE: | |
8170 | if (*arg == '.') | |
8171 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
8172 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
8173 | { | |
8174 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
8175 | { | |
ccc9c027 | 8176 | cpu_arch_tune_set = 1; |
9103f4f4 L |
8177 | cpu_arch_tune = cpu_arch [i].type; |
8178 | cpu_arch_tune_flags = cpu_arch[i].flags; | |
8179 | break; | |
8180 | } | |
8181 | } | |
8182 | if (i >= ARRAY_SIZE (cpu_arch)) | |
8183 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
8184 | break; | |
8185 | ||
1efbbeb4 L |
8186 | case OPTION_MMNEMONIC: |
8187 | if (strcasecmp (arg, "att") == 0) | |
8188 | intel_mnemonic = 0; | |
8189 | else if (strcasecmp (arg, "intel") == 0) | |
8190 | intel_mnemonic = 1; | |
8191 | else | |
8192 | as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg); | |
8193 | break; | |
8194 | ||
8195 | case OPTION_MSYNTAX: | |
8196 | if (strcasecmp (arg, "att") == 0) | |
8197 | intel_syntax = 0; | |
8198 | else if (strcasecmp (arg, "intel") == 0) | |
8199 | intel_syntax = 1; | |
8200 | else | |
8201 | as_fatal (_("Invalid -msyntax= option: `%s'"), arg); | |
8202 | break; | |
8203 | ||
8204 | case OPTION_MINDEX_REG: | |
8205 | allow_index_reg = 1; | |
8206 | break; | |
8207 | ||
8208 | case OPTION_MNAKED_REG: | |
8209 | allow_naked_reg = 1; | |
8210 | break; | |
8211 | ||
8212 | case OPTION_MOLD_GCC: | |
8213 | old_gcc = 1; | |
1efbbeb4 L |
8214 | break; |
8215 | ||
c0f3af97 L |
8216 | case OPTION_MSSE2AVX: |
8217 | sse2avx = 1; | |
8218 | break; | |
8219 | ||
daf50ae7 L |
8220 | case OPTION_MSSE_CHECK: |
8221 | if (strcasecmp (arg, "error") == 0) | |
8222 | sse_check = sse_check_error; | |
8223 | else if (strcasecmp (arg, "warning") == 0) | |
8224 | sse_check = sse_check_warning; | |
8225 | else if (strcasecmp (arg, "none") == 0) | |
8226 | sse_check = sse_check_none; | |
8227 | else | |
8228 | as_fatal (_("Invalid -msse-check= option: `%s'"), arg); | |
8229 | break; | |
8230 | ||
252b5132 RH |
8231 | default: |
8232 | return 0; | |
8233 | } | |
8234 | return 1; | |
8235 | } | |
8236 | ||
8237 | void | |
8238 | md_show_usage (stream) | |
8239 | FILE *stream; | |
8240 | { | |
4cc782b5 ILT |
8241 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8242 | fprintf (stream, _("\ | |
a38cf1db AM |
8243 | -Q ignored\n\ |
8244 | -V print assembler version number\n\ | |
b3b91714 AM |
8245 | -k ignored\n")); |
8246 | #endif | |
8247 | fprintf (stream, _("\ | |
12b55ccc | 8248 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
8249 | -q quieten some warnings\n")); |
8250 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
8251 | fprintf (stream, _("\ | |
a38cf1db | 8252 | -s ignored\n")); |
b3b91714 | 8253 | #endif |
751d281c L |
8254 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
8255 | fprintf (stream, _("\ | |
8256 | --32/--64 generate 32bit/64bit code\n")); | |
8257 | #endif | |
b3b91714 AM |
8258 | #ifdef SVR4_COMMENT_CHARS |
8259 | fprintf (stream, _("\ | |
8260 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
8261 | #else |
8262 | fprintf (stream, _("\ | |
b3b91714 | 8263 | --divide ignored\n")); |
4cc782b5 | 8264 | #endif |
9103f4f4 | 8265 | fprintf (stream, _("\ |
6305a203 L |
8266 | -march=CPU[,+EXTENSION...]\n\ |
8267 | generate code for CPU and EXTENSION, CPU is one of:\n\ | |
2cb4f3d5 L |
8268 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ |
8269 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
8270 | core, core2, k6, k6_2, athlon, k8, amdfam10,\n\ | |
8271 | generic32, generic64\n\ | |
599121aa L |
8272 | EXTENSION is combination of:\n\ |
8273 | mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\ | |
f1f8f695 L |
8274 | avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\ |
8275 | 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n")); | |
6305a203 | 8276 | fprintf (stream, _("\ |
2cb4f3d5 L |
8277 | -mtune=CPU optimize for CPU, CPU is one of:\n\ |
8278 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ | |
8279 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
8280 | core, core2, k6, k6_2, athlon, k8, amdfam10,\n\ | |
8281 | generic32, generic64\n")); | |
ba104c83 | 8282 | fprintf (stream, _("\ |
c0f3af97 L |
8283 | -msse2avx encode SSE instructions with VEX prefix\n")); |
8284 | fprintf (stream, _("\ | |
daf50ae7 L |
8285 | -msse-check=[none|error|warning]\n\ |
8286 | check SSE instructions\n")); | |
8287 | fprintf (stream, _("\ | |
ba104c83 L |
8288 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
8289 | fprintf (stream, _("\ | |
8290 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
8291 | fprintf (stream, _("\ | |
8292 | -mindex-reg support pseudo index registers\n")); | |
8293 | fprintf (stream, _("\ | |
8294 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
8295 | fprintf (stream, _("\ | |
8296 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
8297 | } |
8298 | ||
3e73aa7c | 8299 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
872ce6ff | 8300 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP)) |
252b5132 RH |
8301 | |
8302 | /* Pick the target format to use. */ | |
8303 | ||
47926f60 | 8304 | const char * |
e3bb37b5 | 8305 | i386_target_format (void) |
252b5132 | 8306 | { |
3e73aa7c | 8307 | if (!strcmp (default_arch, "x86_64")) |
9103f4f4 L |
8308 | { |
8309 | set_code_flag (CODE_64BIT); | |
0dfbf9d7 | 8310 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
40fb9820 L |
8311 | { |
8312 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
8313 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
8314 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
8315 | cpu_arch_isa_flags.bitfield.cpui486 = 1; | |
8316 | cpu_arch_isa_flags.bitfield.cpui586 = 1; | |
8317 | cpu_arch_isa_flags.bitfield.cpui686 = 1; | |
8318 | cpu_arch_isa_flags.bitfield.cpup4 = 1; | |
8319 | cpu_arch_isa_flags.bitfield.cpummx= 1; | |
40fb9820 L |
8320 | cpu_arch_isa_flags.bitfield.cpusse = 1; |
8321 | cpu_arch_isa_flags.bitfield.cpusse2 = 1; | |
8322 | } | |
0dfbf9d7 | 8323 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
40fb9820 L |
8324 | { |
8325 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
8326 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
8327 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
8328 | cpu_arch_tune_flags.bitfield.cpui486 = 1; | |
8329 | cpu_arch_tune_flags.bitfield.cpui586 = 1; | |
8330 | cpu_arch_tune_flags.bitfield.cpui686 = 1; | |
8331 | cpu_arch_tune_flags.bitfield.cpup4 = 1; | |
8332 | cpu_arch_tune_flags.bitfield.cpummx= 1; | |
40fb9820 L |
8333 | cpu_arch_tune_flags.bitfield.cpusse = 1; |
8334 | cpu_arch_tune_flags.bitfield.cpusse2 = 1; | |
8335 | } | |
9103f4f4 | 8336 | } |
3e73aa7c | 8337 | else if (!strcmp (default_arch, "i386")) |
9103f4f4 L |
8338 | { |
8339 | set_code_flag (CODE_32BIT); | |
0dfbf9d7 | 8340 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
40fb9820 L |
8341 | { |
8342 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
8343 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
8344 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
8345 | } | |
0dfbf9d7 | 8346 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
40fb9820 L |
8347 | { |
8348 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
8349 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
8350 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
8351 | } | |
9103f4f4 | 8352 | } |
3e73aa7c JH |
8353 | else |
8354 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
8355 | switch (OUTPUT_FLAVOR) |
8356 | { | |
872ce6ff L |
8357 | #ifdef TE_PEP |
8358 | case bfd_target_coff_flavour: | |
8359 | return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386"; | |
8360 | break; | |
8361 | #endif | |
4c63da97 AM |
8362 | #ifdef OBJ_MAYBE_AOUT |
8363 | case bfd_target_aout_flavour: | |
47926f60 | 8364 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
8365 | #endif |
8366 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
8367 | case bfd_target_coff_flavour: |
8368 | return "coff-i386"; | |
4c63da97 | 8369 | #endif |
3e73aa7c | 8370 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 8371 | case bfd_target_elf_flavour: |
3e73aa7c | 8372 | { |
e5cb08ac | 8373 | if (flag_code == CODE_64BIT) |
4fa24527 JB |
8374 | { |
8375 | object_64bit = 1; | |
8376 | use_rela_relocations = 1; | |
8377 | } | |
9d7cbccd | 8378 | return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT; |
3e73aa7c | 8379 | } |
4c63da97 | 8380 | #endif |
252b5132 RH |
8381 | default: |
8382 | abort (); | |
8383 | return NULL; | |
8384 | } | |
8385 | } | |
8386 | ||
47926f60 | 8387 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
8388 | |
8389 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
8390 | void |
8391 | i386_elf_emit_arch_note (void) | |
a847613f | 8392 | { |
718ddfc0 | 8393 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
8394 | { |
8395 | char *p; | |
8396 | asection *seg = now_seg; | |
8397 | subsegT subseg = now_subseg; | |
8398 | Elf_Internal_Note i_note; | |
8399 | Elf_External_Note e_note; | |
8400 | asection *note_secp; | |
8401 | int len; | |
8402 | ||
8403 | /* Create the .note section. */ | |
8404 | note_secp = subseg_new (".note", 0); | |
8405 | bfd_set_section_flags (stdoutput, | |
8406 | note_secp, | |
8407 | SEC_HAS_CONTENTS | SEC_READONLY); | |
8408 | ||
8409 | /* Process the arch string. */ | |
8410 | len = strlen (cpu_arch_name); | |
8411 | ||
8412 | i_note.namesz = len + 1; | |
8413 | i_note.descsz = 0; | |
8414 | i_note.type = NT_ARCH; | |
8415 | p = frag_more (sizeof (e_note.namesz)); | |
8416 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
8417 | p = frag_more (sizeof (e_note.descsz)); | |
8418 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
8419 | p = frag_more (sizeof (e_note.type)); | |
8420 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
8421 | p = frag_more (len + 1); | |
8422 | strcpy (p, cpu_arch_name); | |
8423 | ||
8424 | frag_align (2, 0, 0); | |
8425 | ||
8426 | subseg_set (seg, subseg); | |
8427 | } | |
8428 | } | |
8429 | #endif | |
252b5132 | 8430 | \f |
252b5132 RH |
8431 | symbolS * |
8432 | md_undefined_symbol (name) | |
8433 | char *name; | |
8434 | { | |
18dc2407 ILT |
8435 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
8436 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
8437 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
8438 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
8439 | { |
8440 | if (!GOT_symbol) | |
8441 | { | |
8442 | if (symbol_find (name)) | |
8443 | as_bad (_("GOT already in symbol table")); | |
8444 | GOT_symbol = symbol_new (name, undefined_section, | |
8445 | (valueT) 0, &zero_address_frag); | |
8446 | }; | |
8447 | return GOT_symbol; | |
8448 | } | |
252b5132 RH |
8449 | return 0; |
8450 | } | |
8451 | ||
8452 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 8453 | |
252b5132 RH |
8454 | valueT |
8455 | md_section_align (segment, size) | |
ab9da554 | 8456 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
8457 | valueT size; |
8458 | { | |
4c63da97 AM |
8459 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
8460 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
8461 | { | |
8462 | /* For a.out, force the section size to be aligned. If we don't do | |
8463 | this, BFD will align it for us, but it will not write out the | |
8464 | final bytes of the section. This may be a bug in BFD, but it is | |
8465 | easier to fix it here since that is how the other a.out targets | |
8466 | work. */ | |
8467 | int align; | |
8468 | ||
8469 | align = bfd_get_section_alignment (stdoutput, segment); | |
8470 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
8471 | } | |
252b5132 RH |
8472 | #endif |
8473 | ||
8474 | return size; | |
8475 | } | |
8476 | ||
8477 | /* On the i386, PC-relative offsets are relative to the start of the | |
8478 | next instruction. That is, the address of the offset, plus its | |
8479 | size, since the offset is always the last part of the insn. */ | |
8480 | ||
8481 | long | |
e3bb37b5 | 8482 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
8483 | { |
8484 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
8485 | } | |
8486 | ||
8487 | #ifndef I386COFF | |
8488 | ||
8489 | static void | |
e3bb37b5 | 8490 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 8491 | { |
29b0f896 | 8492 | int temp; |
252b5132 | 8493 | |
8a75718c JB |
8494 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8495 | if (IS_ELF) | |
8496 | obj_elf_section_change_hook (); | |
8497 | #endif | |
252b5132 RH |
8498 | temp = get_absolute_expression (); |
8499 | subseg_set (bss_section, (subsegT) temp); | |
8500 | demand_empty_rest_of_line (); | |
8501 | } | |
8502 | ||
8503 | #endif | |
8504 | ||
252b5132 | 8505 | void |
e3bb37b5 | 8506 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
8507 | { |
8508 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
8509 | { | |
23df1078 JH |
8510 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
8511 | { | |
4fa24527 | 8512 | if (!object_64bit) |
23df1078 JH |
8513 | abort (); |
8514 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
8515 | } | |
8516 | else | |
8517 | { | |
4fa24527 | 8518 | if (!object_64bit) |
d6ab8113 JB |
8519 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
8520 | else | |
8521 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 8522 | } |
252b5132 RH |
8523 | fixp->fx_subsy = 0; |
8524 | } | |
8525 | } | |
8526 | ||
252b5132 RH |
8527 | arelent * |
8528 | tc_gen_reloc (section, fixp) | |
ab9da554 | 8529 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
8530 | fixS *fixp; |
8531 | { | |
8532 | arelent *rel; | |
8533 | bfd_reloc_code_real_type code; | |
8534 | ||
8535 | switch (fixp->fx_r_type) | |
8536 | { | |
3e73aa7c JH |
8537 | case BFD_RELOC_X86_64_PLT32: |
8538 | case BFD_RELOC_X86_64_GOT32: | |
8539 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
8540 | case BFD_RELOC_386_PLT32: |
8541 | case BFD_RELOC_386_GOT32: | |
8542 | case BFD_RELOC_386_GOTOFF: | |
8543 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
8544 | case BFD_RELOC_386_TLS_GD: |
8545 | case BFD_RELOC_386_TLS_LDM: | |
8546 | case BFD_RELOC_386_TLS_LDO_32: | |
8547 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
8548 | case BFD_RELOC_386_TLS_IE: |
8549 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
8550 | case BFD_RELOC_386_TLS_LE_32: |
8551 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
8552 | case BFD_RELOC_386_TLS_GOTDESC: |
8553 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
8554 | case BFD_RELOC_X86_64_TLSGD: |
8555 | case BFD_RELOC_X86_64_TLSLD: | |
8556 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 8557 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
8558 | case BFD_RELOC_X86_64_GOTTPOFF: |
8559 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
8560 | case BFD_RELOC_X86_64_TPOFF64: |
8561 | case BFD_RELOC_X86_64_GOTOFF64: | |
8562 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
8563 | case BFD_RELOC_X86_64_GOT64: |
8564 | case BFD_RELOC_X86_64_GOTPCREL64: | |
8565 | case BFD_RELOC_X86_64_GOTPC64: | |
8566 | case BFD_RELOC_X86_64_GOTPLT64: | |
8567 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
8568 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8569 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
8570 | case BFD_RELOC_RVA: |
8571 | case BFD_RELOC_VTABLE_ENTRY: | |
8572 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
8573 | #ifdef TE_PE |
8574 | case BFD_RELOC_32_SECREL: | |
8575 | #endif | |
252b5132 RH |
8576 | code = fixp->fx_r_type; |
8577 | break; | |
dbbaec26 L |
8578 | case BFD_RELOC_X86_64_32S: |
8579 | if (!fixp->fx_pcrel) | |
8580 | { | |
8581 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
8582 | code = fixp->fx_r_type; | |
8583 | break; | |
8584 | } | |
252b5132 | 8585 | default: |
93382f6d | 8586 | if (fixp->fx_pcrel) |
252b5132 | 8587 | { |
93382f6d AM |
8588 | switch (fixp->fx_size) |
8589 | { | |
8590 | default: | |
b091f402 AM |
8591 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8592 | _("can not do %d byte pc-relative relocation"), | |
8593 | fixp->fx_size); | |
93382f6d AM |
8594 | code = BFD_RELOC_32_PCREL; |
8595 | break; | |
8596 | case 1: code = BFD_RELOC_8_PCREL; break; | |
8597 | case 2: code = BFD_RELOC_16_PCREL; break; | |
8598 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
8599 | #ifdef BFD64 |
8600 | case 8: code = BFD_RELOC_64_PCREL; break; | |
8601 | #endif | |
93382f6d AM |
8602 | } |
8603 | } | |
8604 | else | |
8605 | { | |
8606 | switch (fixp->fx_size) | |
8607 | { | |
8608 | default: | |
b091f402 AM |
8609 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8610 | _("can not do %d byte relocation"), | |
8611 | fixp->fx_size); | |
93382f6d AM |
8612 | code = BFD_RELOC_32; |
8613 | break; | |
8614 | case 1: code = BFD_RELOC_8; break; | |
8615 | case 2: code = BFD_RELOC_16; break; | |
8616 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 8617 | #ifdef BFD64 |
3e73aa7c | 8618 | case 8: code = BFD_RELOC_64; break; |
937149dd | 8619 | #endif |
93382f6d | 8620 | } |
252b5132 RH |
8621 | } |
8622 | break; | |
8623 | } | |
252b5132 | 8624 | |
d182319b JB |
8625 | if ((code == BFD_RELOC_32 |
8626 | || code == BFD_RELOC_32_PCREL | |
8627 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
8628 | && GOT_symbol |
8629 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 8630 | { |
4fa24527 | 8631 | if (!object_64bit) |
d6ab8113 JB |
8632 | code = BFD_RELOC_386_GOTPC; |
8633 | else | |
8634 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 8635 | } |
7b81dfbb AJ |
8636 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
8637 | && GOT_symbol | |
8638 | && fixp->fx_addsy == GOT_symbol) | |
8639 | { | |
8640 | code = BFD_RELOC_X86_64_GOTPC64; | |
8641 | } | |
252b5132 RH |
8642 | |
8643 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
8644 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
8645 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
8646 | |
8647 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 8648 | |
3e73aa7c JH |
8649 | if (!use_rela_relocations) |
8650 | { | |
8651 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
8652 | vtable entry to be used in the relocation's section offset. */ | |
8653 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
8654 | rel->address = fixp->fx_offset; | |
252b5132 | 8655 | |
c6682705 | 8656 | rel->addend = 0; |
3e73aa7c JH |
8657 | } |
8658 | /* Use the rela in 64bit mode. */ | |
252b5132 | 8659 | else |
3e73aa7c | 8660 | { |
062cd5e7 AS |
8661 | if (!fixp->fx_pcrel) |
8662 | rel->addend = fixp->fx_offset; | |
8663 | else | |
8664 | switch (code) | |
8665 | { | |
8666 | case BFD_RELOC_X86_64_PLT32: | |
8667 | case BFD_RELOC_X86_64_GOT32: | |
8668 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
8669 | case BFD_RELOC_X86_64_TLSGD: |
8670 | case BFD_RELOC_X86_64_TLSLD: | |
8671 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
8672 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8673 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
8674 | rel->addend = fixp->fx_offset - fixp->fx_size; |
8675 | break; | |
8676 | default: | |
8677 | rel->addend = (section->vma | |
8678 | - fixp->fx_size | |
8679 | + fixp->fx_addnumber | |
8680 | + md_pcrel_from (fixp)); | |
8681 | break; | |
8682 | } | |
3e73aa7c JH |
8683 | } |
8684 | ||
252b5132 RH |
8685 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
8686 | if (rel->howto == NULL) | |
8687 | { | |
8688 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 8689 | _("cannot represent relocation type %s"), |
252b5132 RH |
8690 | bfd_get_reloc_code_name (code)); |
8691 | /* Set howto to a garbage value so that we can keep going. */ | |
8692 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
8693 | assert (rel->howto != NULL); | |
8694 | } | |
8695 | ||
8696 | return rel; | |
8697 | } | |
8698 | ||
64a0c779 DN |
8699 | \f |
8700 | /* Parse operands using Intel syntax. This implements a recursive descent | |
8701 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
8702 | Programmer's Guide. | |
8703 | ||
8704 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
8705 | documentation. In particular, all the structure/union and | |
8706 | high-level macro operands are missing. | |
8707 | ||
8708 | Uppercase words are terminals, lower case words are non-terminals. | |
8709 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
8710 | bars '|' denote choices. Most grammar productions are implemented in | |
8711 | functions called 'intel_<production>'. | |
8712 | ||
8713 | Initial production is 'expr'. | |
8714 | ||
9306ca4a | 8715 | addOp + | - |
64a0c779 DN |
8716 | |
8717 | alpha [a-zA-Z] | |
8718 | ||
9306ca4a JB |
8719 | binOp & | AND | \| | OR | ^ | XOR |
8720 | ||
64a0c779 DN |
8721 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH |
8722 | ||
8723 | constant digits [[ radixOverride ]] | |
8724 | ||
c0f3af97 | 8725 | dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD |
64a0c779 DN |
8726 | |
8727 | digits decdigit | |
b77a7acd AJ |
8728 | | digits decdigit |
8729 | | digits hexdigit | |
64a0c779 DN |
8730 | |
8731 | decdigit [0-9] | |
8732 | ||
9306ca4a JB |
8733 | e04 e04 addOp e05 |
8734 | | e05 | |
8735 | ||
8736 | e05 e05 binOp e06 | |
b77a7acd | 8737 | | e06 |
64a0c779 DN |
8738 | |
8739 | e06 e06 mulOp e09 | |
b77a7acd | 8740 | | e09 |
64a0c779 DN |
8741 | |
8742 | e09 OFFSET e10 | |
a724f0f4 JB |
8743 | | SHORT e10 |
8744 | | + e10 | |
8745 | | - e10 | |
9306ca4a JB |
8746 | | ~ e10 |
8747 | | NOT e10 | |
64a0c779 DN |
8748 | | e09 PTR e10 |
8749 | | e09 : e10 | |
8750 | | e10 | |
8751 | ||
8752 | e10 e10 [ expr ] | |
b77a7acd | 8753 | | e11 |
64a0c779 DN |
8754 | |
8755 | e11 ( expr ) | |
b77a7acd | 8756 | | [ expr ] |
64a0c779 DN |
8757 | | constant |
8758 | | dataType | |
8759 | | id | |
8760 | | $ | |
8761 | | register | |
8762 | ||
a724f0f4 | 8763 | => expr expr cmpOp e04 |
9306ca4a | 8764 | | e04 |
64a0c779 DN |
8765 | |
8766 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 8767 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
8768 | |
8769 | hexdigit a | b | c | d | e | f | |
b77a7acd | 8770 | | A | B | C | D | E | F |
64a0c779 DN |
8771 | |
8772 | id alpha | |
b77a7acd | 8773 | | id alpha |
64a0c779 DN |
8774 | | id decdigit |
8775 | ||
9306ca4a | 8776 | mulOp * | / | % | MOD | << | SHL | >> | SHR |
64a0c779 DN |
8777 | |
8778 | quote " | ' | |
8779 | ||
8780 | register specialRegister | |
b77a7acd | 8781 | | gpRegister |
64a0c779 DN |
8782 | | byteRegister |
8783 | ||
8784 | segmentRegister CS | DS | ES | FS | GS | SS | |
8785 | ||
9306ca4a | 8786 | specialRegister CR0 | CR2 | CR3 | CR4 |
b77a7acd | 8787 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
8788 | | TR3 | TR4 | TR5 | TR6 | TR7 |
8789 | ||
64a0c779 DN |
8790 | We simplify the grammar in obvious places (e.g., register parsing is |
8791 | done by calling parse_register) and eliminate immediate left recursion | |
8792 | to implement a recursive-descent parser. | |
8793 | ||
a724f0f4 JB |
8794 | expr e04 expr' |
8795 | ||
8796 | expr' cmpOp e04 expr' | |
8797 | | Empty | |
9306ca4a JB |
8798 | |
8799 | e04 e05 e04' | |
8800 | ||
8801 | e04' addOp e05 e04' | |
8802 | | Empty | |
64a0c779 DN |
8803 | |
8804 | e05 e06 e05' | |
8805 | ||
9306ca4a | 8806 | e05' binOp e06 e05' |
b77a7acd | 8807 | | Empty |
64a0c779 DN |
8808 | |
8809 | e06 e09 e06' | |
8810 | ||
8811 | e06' mulOp e09 e06' | |
b77a7acd | 8812 | | Empty |
64a0c779 DN |
8813 | |
8814 | e09 OFFSET e10 e09' | |
a724f0f4 JB |
8815 | | SHORT e10' |
8816 | | + e10' | |
8817 | | - e10' | |
8818 | | ~ e10' | |
8819 | | NOT e10' | |
b77a7acd | 8820 | | e10 e09' |
64a0c779 DN |
8821 | |
8822 | e09' PTR e10 e09' | |
b77a7acd | 8823 | | : e10 e09' |
64a0c779 DN |
8824 | | Empty |
8825 | ||
8826 | e10 e11 e10' | |
8827 | ||
8828 | e10' [ expr ] e10' | |
b77a7acd | 8829 | | Empty |
64a0c779 DN |
8830 | |
8831 | e11 ( expr ) | |
b77a7acd | 8832 | | [ expr ] |
64a0c779 DN |
8833 | | BYTE |
8834 | | WORD | |
8835 | | DWORD | |
9306ca4a | 8836 | | FWORD |
64a0c779 | 8837 | | QWORD |
9306ca4a JB |
8838 | | TBYTE |
8839 | | OWORD | |
8840 | | XMMWORD | |
c0f3af97 | 8841 | | YMMWORD |
64a0c779 DN |
8842 | | . |
8843 | | $ | |
8844 | | register | |
8845 | | id | |
8846 | | constant */ | |
8847 | ||
8848 | /* Parsing structure for the intel syntax parser. Used to implement the | |
8849 | semantic actions for the operand grammar. */ | |
8850 | struct intel_parser_s | |
8851 | { | |
8852 | char *op_string; /* The string being parsed. */ | |
8853 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 8854 | int op_modifier; /* Operand modifier. */ |
64a0c779 | 8855 | int is_mem; /* 1 if operand is memory reference. */ |
4eed87de AM |
8856 | int in_offset; /* >=1 if parsing operand of offset. */ |
8857 | int in_bracket; /* >=1 if parsing operand in brackets. */ | |
64a0c779 DN |
8858 | const reg_entry *reg; /* Last register reference found. */ |
8859 | char *disp; /* Displacement string being built. */ | |
a724f0f4 | 8860 | char *next_operand; /* Resume point when splitting operands. */ |
64a0c779 DN |
8861 | }; |
8862 | ||
8863 | static struct intel_parser_s intel_parser; | |
8864 | ||
8865 | /* Token structure for parsing intel syntax. */ | |
8866 | struct intel_token | |
8867 | { | |
8868 | int code; /* Token code. */ | |
8869 | const reg_entry *reg; /* Register entry for register tokens. */ | |
8870 | char *str; /* String representation. */ | |
8871 | }; | |
8872 | ||
8873 | static struct intel_token cur_token, prev_token; | |
8874 | ||
50705ef4 AM |
8875 | /* Token codes for the intel parser. Since T_SHORT is already used |
8876 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
8877 | #define T_NIL -1 |
8878 | #define T_CONST 1 | |
8879 | #define T_REG 2 | |
8880 | #define T_BYTE 3 | |
8881 | #define T_WORD 4 | |
9306ca4a JB |
8882 | #define T_DWORD 5 |
8883 | #define T_FWORD 6 | |
8884 | #define T_QWORD 7 | |
8885 | #define T_TBYTE 8 | |
8886 | #define T_XMMWORD 9 | |
50705ef4 | 8887 | #undef T_SHORT |
9306ca4a JB |
8888 | #define T_SHORT 10 |
8889 | #define T_OFFSET 11 | |
8890 | #define T_PTR 12 | |
8891 | #define T_ID 13 | |
8892 | #define T_SHL 14 | |
8893 | #define T_SHR 15 | |
c0f3af97 | 8894 | #define T_YMMWORD 16 |
64a0c779 DN |
8895 | |
8896 | /* Prototypes for intel parser functions. */ | |
e3bb37b5 L |
8897 | static int intel_match_token (int); |
8898 | static void intel_putback_token (void); | |
8899 | static void intel_get_token (void); | |
8900 | static int intel_expr (void); | |
8901 | static int intel_e04 (void); | |
8902 | static int intel_e05 (void); | |
8903 | static int intel_e06 (void); | |
8904 | static int intel_e09 (void); | |
8905 | static int intel_e10 (void); | |
8906 | static int intel_e11 (void); | |
64a0c779 | 8907 | |
64a0c779 | 8908 | static int |
e3bb37b5 | 8909 | i386_intel_operand (char *operand_string, int got_a_float) |
64a0c779 DN |
8910 | { |
8911 | int ret; | |
8912 | char *p; | |
fc0763e6 JB |
8913 | const reg_entry *final_base = i.base_reg; |
8914 | const reg_entry *final_index = i.index_reg; | |
64a0c779 | 8915 | |
a724f0f4 JB |
8916 | p = intel_parser.op_string = xstrdup (operand_string); |
8917 | intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); | |
8918 | ||
8919 | for (;;) | |
64a0c779 | 8920 | { |
a724f0f4 JB |
8921 | /* Initialize token holders. */ |
8922 | cur_token.code = prev_token.code = T_NIL; | |
8923 | cur_token.reg = prev_token.reg = NULL; | |
8924 | cur_token.str = prev_token.str = NULL; | |
8925 | ||
8926 | /* Initialize parser structure. */ | |
8927 | intel_parser.got_a_float = got_a_float; | |
8928 | intel_parser.op_modifier = 0; | |
8929 | intel_parser.is_mem = 0; | |
8930 | intel_parser.in_offset = 0; | |
8931 | intel_parser.in_bracket = 0; | |
8932 | intel_parser.reg = NULL; | |
8933 | intel_parser.disp[0] = '\0'; | |
8934 | intel_parser.next_operand = NULL; | |
8935 | ||
fc0763e6 JB |
8936 | i.base_reg = NULL; |
8937 | i.index_reg = NULL; | |
8938 | ||
a724f0f4 JB |
8939 | /* Read the first token and start the parser. */ |
8940 | intel_get_token (); | |
8941 | ret = intel_expr (); | |
8942 | ||
8943 | if (!ret) | |
8944 | break; | |
8945 | ||
9306ca4a JB |
8946 | if (cur_token.code != T_NIL) |
8947 | { | |
8948 | as_bad (_("invalid operand for '%s' ('%s' unexpected)"), | |
8949 | current_templates->start->name, cur_token.str); | |
8950 | ret = 0; | |
8951 | } | |
64a0c779 DN |
8952 | /* If we found a memory reference, hand it over to i386_displacement |
8953 | to fill in the rest of the operand fields. */ | |
9306ca4a | 8954 | else if (intel_parser.is_mem) |
64a0c779 DN |
8955 | { |
8956 | if ((i.mem_operands == 1 | |
40fb9820 | 8957 | && !current_templates->start->opcode_modifier.isstring) |
64a0c779 DN |
8958 | || i.mem_operands == 2) |
8959 | { | |
8960 | as_bad (_("too many memory references for '%s'"), | |
8961 | current_templates->start->name); | |
8962 | ret = 0; | |
8963 | } | |
8964 | else | |
8965 | { | |
8966 | char *s = intel_parser.disp; | |
64a0c779 | 8967 | |
a724f0f4 JB |
8968 | if (!quiet_warnings && intel_parser.is_mem < 0) |
8969 | /* See the comments in intel_bracket_expr. */ | |
8970 | as_warn (_("Treating `%s' as memory reference"), operand_string); | |
8971 | ||
64a0c779 DN |
8972 | /* Add the displacement expression. */ |
8973 | if (*s != '\0') | |
a4622f40 AM |
8974 | ret = i386_displacement (s, s + strlen (s)); |
8975 | if (ret) | |
a724f0f4 JB |
8976 | { |
8977 | /* Swap base and index in 16-bit memory operands like | |
8978 | [si+bx]. Since i386_index_check is also used in AT&T | |
8979 | mode we have to do that here. */ | |
8980 | if (i.base_reg | |
8981 | && i.index_reg | |
40fb9820 L |
8982 | && i.base_reg->reg_type.bitfield.reg16 |
8983 | && i.index_reg->reg_type.bitfield.reg16 | |
a724f0f4 JB |
8984 | && i.base_reg->reg_num >= 6 |
8985 | && i.index_reg->reg_num < 6) | |
8986 | { | |
8987 | const reg_entry *base = i.index_reg; | |
8988 | ||
8989 | i.index_reg = i.base_reg; | |
8990 | i.base_reg = base; | |
8991 | } | |
8992 | ret = i386_index_check (operand_string); | |
8993 | } | |
fc0763e6 JB |
8994 | if (ret) |
8995 | { | |
8996 | i.types[this_operand].bitfield.mem = 1; | |
8997 | i.mem_operands++; | |
8998 | } | |
64a0c779 DN |
8999 | } |
9000 | } | |
9001 | ||
9002 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
a724f0f4 | 9003 | else if ((intel_parser.op_modifier & (1 << T_OFFSET)) |
64a0c779 | 9004 | || intel_parser.reg == NULL) |
b7240065 JB |
9005 | { |
9006 | if (i.mem_operands < 2 && i.seg[i.mem_operands]) | |
9007 | { | |
9008 | if (!(intel_parser.op_modifier & (1 << T_OFFSET))) | |
9009 | as_warn (_("Segment override ignored")); | |
9010 | i.seg[i.mem_operands] = NULL; | |
9011 | } | |
9012 | ret = i386_immediate (intel_parser.disp); | |
9013 | } | |
a724f0f4 | 9014 | |
fc0763e6 JB |
9015 | if (!final_base && !final_index) |
9016 | { | |
9017 | final_base = i.base_reg; | |
9018 | final_index = i.index_reg; | |
9019 | } | |
9020 | ||
a724f0f4 | 9021 | if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) |
4eed87de | 9022 | ret = 0; |
a724f0f4 JB |
9023 | if (!ret || !intel_parser.next_operand) |
9024 | break; | |
9025 | intel_parser.op_string = intel_parser.next_operand; | |
9026 | this_operand = i.operands++; | |
7d5e4556 | 9027 | i.types[this_operand].bitfield.unspecified = 1; |
64a0c779 DN |
9028 | } |
9029 | ||
9030 | free (p); | |
9031 | free (intel_parser.disp); | |
9032 | ||
fc0763e6 JB |
9033 | if (final_base || final_index) |
9034 | { | |
9035 | i.base_reg = final_base; | |
9036 | i.index_reg = final_index; | |
9037 | } | |
9038 | ||
64a0c779 DN |
9039 | return ret; |
9040 | } | |
9041 | ||
a724f0f4 JB |
9042 | #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg) |
9043 | ||
9044 | /* expr e04 expr' | |
9045 | ||
9046 | expr' cmpOp e04 expr' | |
9047 | | Empty */ | |
64a0c779 | 9048 | static int |
e3bb37b5 | 9049 | intel_expr (void) |
64a0c779 | 9050 | { |
a724f0f4 JB |
9051 | /* XXX Implement the comparison operators. */ |
9052 | return intel_e04 (); | |
9306ca4a JB |
9053 | } |
9054 | ||
a724f0f4 | 9055 | /* e04 e05 e04' |
9306ca4a | 9056 | |
a724f0f4 | 9057 | e04' addOp e05 e04' |
9306ca4a JB |
9058 | | Empty */ |
9059 | static int | |
e3bb37b5 | 9060 | intel_e04 (void) |
9306ca4a | 9061 | { |
a724f0f4 | 9062 | int nregs = -1; |
9306ca4a | 9063 | |
a724f0f4 | 9064 | for (;;) |
9306ca4a | 9065 | { |
a724f0f4 JB |
9066 | if (!intel_e05()) |
9067 | return 0; | |
9306ca4a | 9068 | |
a724f0f4 JB |
9069 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
9070 | i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */ | |
9306ca4a | 9071 | |
a724f0f4 JB |
9072 | if (cur_token.code == '+') |
9073 | nregs = -1; | |
9074 | else if (cur_token.code == '-') | |
9075 | nregs = NUM_ADDRESS_REGS; | |
9076 | else | |
9077 | return 1; | |
64a0c779 | 9078 | |
a724f0f4 JB |
9079 | strcat (intel_parser.disp, cur_token.str); |
9080 | intel_match_token (cur_token.code); | |
9081 | } | |
64a0c779 DN |
9082 | } |
9083 | ||
64a0c779 DN |
9084 | /* e05 e06 e05' |
9085 | ||
9306ca4a | 9086 | e05' binOp e06 e05' |
64a0c779 DN |
9087 | | Empty */ |
9088 | static int | |
e3bb37b5 | 9089 | intel_e05 (void) |
64a0c779 | 9090 | { |
a724f0f4 | 9091 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 9092 | |
a724f0f4 | 9093 | for (;;) |
64a0c779 | 9094 | { |
a724f0f4 JB |
9095 | if (!intel_e06()) |
9096 | return 0; | |
9097 | ||
4eed87de AM |
9098 | if (cur_token.code == '&' |
9099 | || cur_token.code == '|' | |
9100 | || cur_token.code == '^') | |
a724f0f4 JB |
9101 | { |
9102 | char str[2]; | |
9103 | ||
9104 | str[0] = cur_token.code; | |
9105 | str[1] = 0; | |
9106 | strcat (intel_parser.disp, str); | |
9107 | } | |
9108 | else | |
9109 | break; | |
9306ca4a | 9110 | |
64a0c779 DN |
9111 | intel_match_token (cur_token.code); |
9112 | ||
a724f0f4 JB |
9113 | if (nregs < 0) |
9114 | nregs = ~nregs; | |
64a0c779 | 9115 | } |
a724f0f4 JB |
9116 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
9117 | i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */ | |
9118 | return 1; | |
4a1805b1 | 9119 | } |
64a0c779 DN |
9120 | |
9121 | /* e06 e09 e06' | |
9122 | ||
9123 | e06' mulOp e09 e06' | |
b77a7acd | 9124 | | Empty */ |
64a0c779 | 9125 | static int |
e3bb37b5 | 9126 | intel_e06 (void) |
64a0c779 | 9127 | { |
a724f0f4 | 9128 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 9129 | |
a724f0f4 | 9130 | for (;;) |
64a0c779 | 9131 | { |
a724f0f4 JB |
9132 | if (!intel_e09()) |
9133 | return 0; | |
9306ca4a | 9134 | |
4eed87de AM |
9135 | if (cur_token.code == '*' |
9136 | || cur_token.code == '/' | |
9137 | || cur_token.code == '%') | |
a724f0f4 JB |
9138 | { |
9139 | char str[2]; | |
9306ca4a | 9140 | |
a724f0f4 JB |
9141 | str[0] = cur_token.code; |
9142 | str[1] = 0; | |
9143 | strcat (intel_parser.disp, str); | |
9144 | } | |
9145 | else if (cur_token.code == T_SHL) | |
9146 | strcat (intel_parser.disp, "<<"); | |
9147 | else if (cur_token.code == T_SHR) | |
9148 | strcat (intel_parser.disp, ">>"); | |
9149 | else | |
9150 | break; | |
9306ca4a | 9151 | |
64e74474 | 9152 | intel_match_token (cur_token.code); |
64a0c779 | 9153 | |
a724f0f4 JB |
9154 | if (nregs < 0) |
9155 | nregs = ~nregs; | |
64a0c779 | 9156 | } |
a724f0f4 JB |
9157 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
9158 | i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */ | |
9159 | return 1; | |
64a0c779 DN |
9160 | } |
9161 | ||
a724f0f4 JB |
9162 | /* e09 OFFSET e09 |
9163 | | SHORT e09 | |
9164 | | + e09 | |
9165 | | - e09 | |
9166 | | ~ e09 | |
9167 | | NOT e09 | |
9306ca4a JB |
9168 | | e10 e09' |
9169 | ||
64a0c779 | 9170 | e09' PTR e10 e09' |
b77a7acd | 9171 | | : e10 e09' |
64a0c779 DN |
9172 | | Empty */ |
9173 | static int | |
e3bb37b5 | 9174 | intel_e09 (void) |
64a0c779 | 9175 | { |
a724f0f4 JB |
9176 | int nregs = ~NUM_ADDRESS_REGS; |
9177 | int in_offset = 0; | |
9178 | ||
9179 | for (;;) | |
64a0c779 | 9180 | { |
a724f0f4 JB |
9181 | /* Don't consume constants here. */ |
9182 | if (cur_token.code == '+' || cur_token.code == '-') | |
9183 | { | |
9184 | /* Need to look one token ahead - if the next token | |
9185 | is a constant, the current token is its sign. */ | |
9186 | int next_code; | |
9187 | ||
9188 | intel_match_token (cur_token.code); | |
9189 | next_code = cur_token.code; | |
9190 | intel_putback_token (); | |
9191 | if (next_code == T_CONST) | |
9192 | break; | |
9193 | } | |
9194 | ||
9195 | /* e09 OFFSET e09 */ | |
9196 | if (cur_token.code == T_OFFSET) | |
9197 | { | |
9198 | if (!in_offset++) | |
9199 | ++intel_parser.in_offset; | |
9200 | } | |
9201 | ||
9202 | /* e09 SHORT e09 */ | |
9203 | else if (cur_token.code == T_SHORT) | |
9204 | intel_parser.op_modifier |= 1 << T_SHORT; | |
9205 | ||
9206 | /* e09 + e09 */ | |
9207 | else if (cur_token.code == '+') | |
9208 | strcat (intel_parser.disp, "+"); | |
9209 | ||
9210 | /* e09 - e09 | |
9211 | | ~ e09 | |
9212 | | NOT e09 */ | |
9213 | else if (cur_token.code == '-' || cur_token.code == '~') | |
9214 | { | |
9215 | char str[2]; | |
64a0c779 | 9216 | |
a724f0f4 JB |
9217 | if (nregs < 0) |
9218 | nregs = ~nregs; | |
9219 | str[0] = cur_token.code; | |
9220 | str[1] = 0; | |
9221 | strcat (intel_parser.disp, str); | |
9222 | } | |
9223 | ||
9224 | /* e09 e10 e09' */ | |
9225 | else | |
9226 | break; | |
9227 | ||
9228 | intel_match_token (cur_token.code); | |
64a0c779 DN |
9229 | } |
9230 | ||
a724f0f4 | 9231 | for (;;) |
9306ca4a | 9232 | { |
a724f0f4 JB |
9233 | if (!intel_e10 ()) |
9234 | return 0; | |
9306ca4a | 9235 | |
a724f0f4 JB |
9236 | /* e09' PTR e10 e09' */ |
9237 | if (cur_token.code == T_PTR) | |
9238 | { | |
9239 | char suffix; | |
9306ca4a | 9240 | |
a724f0f4 | 9241 | if (prev_token.code == T_BYTE) |
7d5e4556 L |
9242 | { |
9243 | suffix = BYTE_MNEM_SUFFIX; | |
9244 | i.types[this_operand].bitfield.byte = 1; | |
9245 | } | |
9306ca4a | 9246 | |
a724f0f4 JB |
9247 | else if (prev_token.code == T_WORD) |
9248 | { | |
34b772a6 JB |
9249 | if ((current_templates->start->name[0] == 'l' |
9250 | && current_templates->start->name[2] == 's' | |
9251 | && current_templates->start->name[3] == 0) | |
9252 | || current_templates->start->base_opcode == 0x62 /* bound */) | |
a724f0f4 JB |
9253 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ |
9254 | else if (intel_parser.got_a_float == 2) /* "fi..." */ | |
9255 | suffix = SHORT_MNEM_SUFFIX; | |
9256 | else | |
9257 | suffix = WORD_MNEM_SUFFIX; | |
7d5e4556 | 9258 | i.types[this_operand].bitfield.word = 1; |
a724f0f4 | 9259 | } |
64a0c779 | 9260 | |
a724f0f4 JB |
9261 | else if (prev_token.code == T_DWORD) |
9262 | { | |
34b772a6 JB |
9263 | if ((current_templates->start->name[0] == 'l' |
9264 | && current_templates->start->name[2] == 's' | |
9265 | && current_templates->start->name[3] == 0) | |
9266 | || current_templates->start->base_opcode == 0x62 /* bound */) | |
a724f0f4 JB |
9267 | suffix = WORD_MNEM_SUFFIX; |
9268 | else if (flag_code == CODE_16BIT | |
40fb9820 L |
9269 | && (current_templates->start->opcode_modifier.jump |
9270 | || current_templates->start->opcode_modifier.jumpdword)) | |
a724f0f4 JB |
9271 | suffix = LONG_DOUBLE_MNEM_SUFFIX; |
9272 | else if (intel_parser.got_a_float == 1) /* "f..." */ | |
9273 | suffix = SHORT_MNEM_SUFFIX; | |
9274 | else | |
9275 | suffix = LONG_MNEM_SUFFIX; | |
7d5e4556 | 9276 | i.types[this_operand].bitfield.dword = 1; |
a724f0f4 | 9277 | } |
9306ca4a | 9278 | |
a724f0f4 JB |
9279 | else if (prev_token.code == T_FWORD) |
9280 | { | |
9281 | if (current_templates->start->name[0] == 'l' | |
9282 | && current_templates->start->name[2] == 's' | |
9283 | && current_templates->start->name[3] == 0) | |
9284 | suffix = LONG_MNEM_SUFFIX; | |
9285 | else if (!intel_parser.got_a_float) | |
9286 | { | |
9287 | if (flag_code == CODE_16BIT) | |
9288 | add_prefix (DATA_PREFIX_OPCODE); | |
9289 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
9290 | } | |
9291 | else | |
9292 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
7d5e4556 | 9293 | i.types[this_operand].bitfield.fword = 1; |
a724f0f4 | 9294 | } |
64a0c779 | 9295 | |
a724f0f4 JB |
9296 | else if (prev_token.code == T_QWORD) |
9297 | { | |
34b772a6 JB |
9298 | if (current_templates->start->base_opcode == 0x62 /* bound */ |
9299 | || intel_parser.got_a_float == 1) /* "f..." */ | |
a724f0f4 JB |
9300 | suffix = LONG_MNEM_SUFFIX; |
9301 | else | |
34b772a6 | 9302 | suffix = QWORD_MNEM_SUFFIX; |
7d5e4556 | 9303 | i.types[this_operand].bitfield.qword = 1; |
a724f0f4 | 9304 | } |
64a0c779 | 9305 | |
a724f0f4 JB |
9306 | else if (prev_token.code == T_TBYTE) |
9307 | { | |
9308 | if (intel_parser.got_a_float == 1) | |
9309 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
9310 | else | |
9311 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
9312 | } | |
9306ca4a | 9313 | |
a724f0f4 | 9314 | else if (prev_token.code == T_XMMWORD) |
9306ca4a | 9315 | { |
582d5edd | 9316 | suffix = XMMWORD_MNEM_SUFFIX; |
7d5e4556 | 9317 | i.types[this_operand].bitfield.xmmword = 1; |
9306ca4a | 9318 | } |
64a0c779 | 9319 | |
c0f3af97 L |
9320 | else if (prev_token.code == T_YMMWORD) |
9321 | { | |
9322 | suffix = YMMWORD_MNEM_SUFFIX; | |
9323 | i.types[this_operand].bitfield.ymmword = 1; | |
9324 | } | |
9325 | ||
f16b83df | 9326 | else |
a724f0f4 JB |
9327 | { |
9328 | as_bad (_("Unknown operand modifier `%s'"), prev_token.str); | |
9329 | return 0; | |
9330 | } | |
9331 | ||
7d5e4556 L |
9332 | i.types[this_operand].bitfield.unspecified = 0; |
9333 | ||
435acd52 JB |
9334 | /* Operands for jump/call using 'ptr' notation denote absolute |
9335 | addresses. */ | |
40fb9820 L |
9336 | if (current_templates->start->opcode_modifier.jump |
9337 | || current_templates->start->opcode_modifier.jumpdword) | |
9338 | i.types[this_operand].bitfield.jumpabsolute = 1; | |
435acd52 | 9339 | |
a724f0f4 JB |
9340 | if (current_templates->start->base_opcode == 0x8d /* lea */) |
9341 | ; | |
9342 | else if (!i.suffix) | |
9343 | i.suffix = suffix; | |
9344 | else if (i.suffix != suffix) | |
9345 | { | |
9346 | as_bad (_("Conflicting operand modifiers")); | |
9347 | return 0; | |
9348 | } | |
64a0c779 | 9349 | |
9306ca4a JB |
9350 | } |
9351 | ||
a724f0f4 JB |
9352 | /* e09' : e10 e09' */ |
9353 | else if (cur_token.code == ':') | |
9306ca4a | 9354 | { |
a724f0f4 JB |
9355 | if (prev_token.code != T_REG) |
9356 | { | |
9357 | /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a | |
9358 | segment/group identifier (which we don't have), using comma | |
9359 | as the operand separator there is even less consistent, since | |
9360 | there all branches only have a single operand. */ | |
9361 | if (this_operand != 0 | |
9362 | || intel_parser.in_offset | |
9363 | || intel_parser.in_bracket | |
40fb9820 L |
9364 | || (!current_templates->start->opcode_modifier.jump |
9365 | && !current_templates->start->opcode_modifier.jumpdword | |
9366 | && !current_templates->start->opcode_modifier.jumpintersegment | |
9367 | && !current_templates->start->operand_types[0].bitfield.jumpabsolute)) | |
a724f0f4 JB |
9368 | return intel_match_token (T_NIL); |
9369 | /* Remember the start of the 2nd operand and terminate 1st | |
9370 | operand here. | |
9371 | XXX This isn't right, yet (when SSSS:OOOO is right operand of | |
9372 | another expression), but it gets at least the simplest case | |
9373 | (a plain number or symbol on the left side) right. */ | |
9374 | intel_parser.next_operand = intel_parser.op_string; | |
9375 | *--intel_parser.op_string = '\0'; | |
9376 | return intel_match_token (':'); | |
9377 | } | |
9306ca4a | 9378 | } |
64a0c779 | 9379 | |
a724f0f4 | 9380 | /* e09' Empty */ |
64a0c779 | 9381 | else |
a724f0f4 | 9382 | break; |
64a0c779 | 9383 | |
a724f0f4 JB |
9384 | intel_match_token (cur_token.code); |
9385 | ||
9386 | } | |
9387 | ||
9388 | if (in_offset) | |
9389 | { | |
9390 | --intel_parser.in_offset; | |
9391 | if (nregs < 0) | |
9392 | nregs = ~nregs; | |
9393 | if (NUM_ADDRESS_REGS > nregs) | |
9306ca4a | 9394 | { |
a724f0f4 | 9395 | as_bad (_("Invalid operand to `OFFSET'")); |
9306ca4a JB |
9396 | return 0; |
9397 | } | |
a724f0f4 JB |
9398 | intel_parser.op_modifier |= 1 << T_OFFSET; |
9399 | } | |
9306ca4a | 9400 | |
a724f0f4 JB |
9401 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
9402 | i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */ | |
9403 | return 1; | |
9404 | } | |
64a0c779 | 9405 | |
a724f0f4 | 9406 | static int |
e3bb37b5 | 9407 | intel_bracket_expr (void) |
a724f0f4 JB |
9408 | { |
9409 | int was_offset = intel_parser.op_modifier & (1 << T_OFFSET); | |
9410 | const char *start = intel_parser.op_string; | |
9411 | int len; | |
9412 | ||
9413 | if (i.op[this_operand].regs) | |
9414 | return intel_match_token (T_NIL); | |
9415 | ||
9416 | intel_match_token ('['); | |
9417 | ||
9418 | /* Mark as a memory operand only if it's not already known to be an | |
9419 | offset expression. If it's an offset expression, we need to keep | |
9420 | the brace in. */ | |
9421 | if (!intel_parser.in_offset) | |
9422 | { | |
9423 | ++intel_parser.in_bracket; | |
435acd52 JB |
9424 | |
9425 | /* Operands for jump/call inside brackets denote absolute addresses. */ | |
40fb9820 L |
9426 | if (current_templates->start->opcode_modifier.jump |
9427 | || current_templates->start->opcode_modifier.jumpdword) | |
9428 | i.types[this_operand].bitfield.jumpabsolute = 1; | |
435acd52 | 9429 | |
a724f0f4 JB |
9430 | /* Unfortunately gas always diverged from MASM in a respect that can't |
9431 | be easily fixed without risking to break code sequences likely to be | |
9432 | encountered (the testsuite even check for this): MASM doesn't consider | |
9433 | an expression inside brackets unconditionally as a memory reference. | |
9434 | When that is e.g. a constant, an offset expression, or the sum of the | |
9435 | two, this is still taken as a constant load. gas, however, always | |
9436 | treated these as memory references. As a compromise, we'll try to make | |
9437 | offset expressions inside brackets work the MASM way (since that's | |
9438 | less likely to be found in real world code), but make constants alone | |
9439 | continue to work the traditional gas way. In either case, issue a | |
9440 | warning. */ | |
9441 | intel_parser.op_modifier &= ~was_offset; | |
64a0c779 | 9442 | } |
a724f0f4 | 9443 | else |
64e74474 | 9444 | strcat (intel_parser.disp, "["); |
a724f0f4 JB |
9445 | |
9446 | /* Add a '+' to the displacement string if necessary. */ | |
9447 | if (*intel_parser.disp != '\0' | |
9448 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
9449 | strcat (intel_parser.disp, "+"); | |
64a0c779 | 9450 | |
a724f0f4 JB |
9451 | if (intel_expr () |
9452 | && (len = intel_parser.op_string - start - 1, | |
9453 | intel_match_token (']'))) | |
64a0c779 | 9454 | { |
a724f0f4 JB |
9455 | /* Preserve brackets when the operand is an offset expression. */ |
9456 | if (intel_parser.in_offset) | |
9457 | strcat (intel_parser.disp, "]"); | |
9458 | else | |
9459 | { | |
9460 | --intel_parser.in_bracket; | |
9461 | if (i.base_reg || i.index_reg) | |
9462 | intel_parser.is_mem = 1; | |
9463 | if (!intel_parser.is_mem) | |
9464 | { | |
9465 | if (!(intel_parser.op_modifier & (1 << T_OFFSET))) | |
9466 | /* Defer the warning until all of the operand was parsed. */ | |
9467 | intel_parser.is_mem = -1; | |
9468 | else if (!quiet_warnings) | |
4eed87de AM |
9469 | as_warn (_("`[%.*s]' taken to mean just `%.*s'"), |
9470 | len, start, len, start); | |
a724f0f4 JB |
9471 | } |
9472 | } | |
9473 | intel_parser.op_modifier |= was_offset; | |
64a0c779 | 9474 | |
a724f0f4 | 9475 | return 1; |
64a0c779 | 9476 | } |
a724f0f4 | 9477 | return 0; |
64a0c779 DN |
9478 | } |
9479 | ||
9480 | /* e10 e11 e10' | |
9481 | ||
9482 | e10' [ expr ] e10' | |
b77a7acd | 9483 | | Empty */ |
64a0c779 | 9484 | static int |
e3bb37b5 | 9485 | intel_e10 (void) |
64a0c779 | 9486 | { |
a724f0f4 JB |
9487 | if (!intel_e11 ()) |
9488 | return 0; | |
64a0c779 | 9489 | |
a724f0f4 | 9490 | while (cur_token.code == '[') |
64a0c779 | 9491 | { |
a724f0f4 | 9492 | if (!intel_bracket_expr ()) |
21d6c4af | 9493 | return 0; |
64a0c779 DN |
9494 | } |
9495 | ||
a724f0f4 | 9496 | return 1; |
64a0c779 DN |
9497 | } |
9498 | ||
64a0c779 | 9499 | /* e11 ( expr ) |
b77a7acd | 9500 | | [ expr ] |
64a0c779 DN |
9501 | | BYTE |
9502 | | WORD | |
9503 | | DWORD | |
9306ca4a | 9504 | | FWORD |
64a0c779 | 9505 | | QWORD |
9306ca4a JB |
9506 | | TBYTE |
9507 | | OWORD | |
9508 | | XMMWORD | |
c0f3af97 | 9509 | | YMMWORD |
4a1805b1 | 9510 | | $ |
64a0c779 DN |
9511 | | . |
9512 | | register | |
9513 | | id | |
9514 | | constant */ | |
9515 | static int | |
e3bb37b5 | 9516 | intel_e11 (void) |
64a0c779 | 9517 | { |
a724f0f4 | 9518 | switch (cur_token.code) |
64a0c779 | 9519 | { |
a724f0f4 JB |
9520 | /* e11 ( expr ) */ |
9521 | case '(': | |
64a0c779 DN |
9522 | intel_match_token ('('); |
9523 | strcat (intel_parser.disp, "("); | |
9524 | ||
9525 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
9526 | { |
9527 | strcat (intel_parser.disp, ")"); | |
9528 | return 1; | |
9529 | } | |
a724f0f4 | 9530 | return 0; |
4a1805b1 | 9531 | |
a724f0f4 JB |
9532 | /* e11 [ expr ] */ |
9533 | case '[': | |
a724f0f4 | 9534 | return intel_bracket_expr (); |
64a0c779 | 9535 | |
a724f0f4 JB |
9536 | /* e11 $ |
9537 | | . */ | |
9538 | case '.': | |
64a0c779 DN |
9539 | strcat (intel_parser.disp, cur_token.str); |
9540 | intel_match_token (cur_token.code); | |
21d6c4af DN |
9541 | |
9542 | /* Mark as a memory operand only if it's not already known to be an | |
9543 | offset expression. */ | |
a724f0f4 | 9544 | if (!intel_parser.in_offset) |
21d6c4af | 9545 | intel_parser.is_mem = 1; |
64a0c779 DN |
9546 | |
9547 | return 1; | |
64a0c779 | 9548 | |
a724f0f4 JB |
9549 | /* e11 register */ |
9550 | case T_REG: | |
9551 | { | |
9552 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
64a0c779 | 9553 | |
a724f0f4 | 9554 | intel_match_token (T_REG); |
64a0c779 | 9555 | |
a724f0f4 JB |
9556 | /* Check for segment change. */ |
9557 | if (cur_token.code == ':') | |
9558 | { | |
40fb9820 L |
9559 | if (!reg->reg_type.bitfield.sreg2 |
9560 | && !reg->reg_type.bitfield.sreg3) | |
a724f0f4 | 9561 | { |
4eed87de AM |
9562 | as_bad (_("`%s' is not a valid segment register"), |
9563 | reg->reg_name); | |
a724f0f4 JB |
9564 | return 0; |
9565 | } | |
b7240065 JB |
9566 | else if (i.mem_operands >= 2) |
9567 | as_warn (_("Segment override ignored")); | |
a724f0f4 JB |
9568 | else if (i.seg[i.mem_operands]) |
9569 | as_warn (_("Extra segment override ignored")); | |
9570 | else | |
9571 | { | |
9572 | if (!intel_parser.in_offset) | |
9573 | intel_parser.is_mem = 1; | |
9574 | switch (reg->reg_num) | |
9575 | { | |
9576 | case 0: | |
9577 | i.seg[i.mem_operands] = &es; | |
9578 | break; | |
9579 | case 1: | |
9580 | i.seg[i.mem_operands] = &cs; | |
9581 | break; | |
9582 | case 2: | |
9583 | i.seg[i.mem_operands] = &ss; | |
9584 | break; | |
9585 | case 3: | |
9586 | i.seg[i.mem_operands] = &ds; | |
9587 | break; | |
9588 | case 4: | |
9589 | i.seg[i.mem_operands] = &fs; | |
9590 | break; | |
9591 | case 5: | |
9592 | i.seg[i.mem_operands] = &gs; | |
9593 | break; | |
9594 | } | |
9595 | } | |
9596 | } | |
64a0c779 | 9597 | |
b7240065 JB |
9598 | else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat) |
9599 | { | |
9600 | as_bad (_("cannot use `FLAT' here")); | |
9601 | return 0; | |
9602 | } | |
9603 | ||
a724f0f4 JB |
9604 | /* Not a segment register. Check for register scaling. */ |
9605 | else if (cur_token.code == '*') | |
9606 | { | |
9607 | if (!intel_parser.in_bracket) | |
9608 | { | |
9609 | as_bad (_("Register scaling only allowed in memory operands")); | |
9610 | return 0; | |
9611 | } | |
64a0c779 | 9612 | |
40fb9820 | 9613 | if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */ |
a724f0f4 JB |
9614 | reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ |
9615 | else if (i.index_reg) | |
9616 | reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ | |
64a0c779 | 9617 | |
a724f0f4 JB |
9618 | /* What follows must be a valid scale. */ |
9619 | intel_match_token ('*'); | |
9620 | i.index_reg = reg; | |
40fb9820 | 9621 | i.types[this_operand].bitfield.baseindex = 1; |
64a0c779 | 9622 | |
a724f0f4 JB |
9623 | /* Set the scale after setting the register (otherwise, |
9624 | i386_scale will complain) */ | |
9625 | if (cur_token.code == '+' || cur_token.code == '-') | |
9626 | { | |
9627 | char *str, sign = cur_token.code; | |
9628 | intel_match_token (cur_token.code); | |
9629 | if (cur_token.code != T_CONST) | |
9630 | { | |
9631 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
9632 | cur_token.str); | |
9633 | return 0; | |
9634 | } | |
9635 | str = (char *) xmalloc (strlen (cur_token.str) + 2); | |
9636 | strcpy (str + 1, cur_token.str); | |
9637 | *str = sign; | |
9638 | if (!i386_scale (str)) | |
9639 | return 0; | |
9640 | free (str); | |
9641 | } | |
9642 | else if (!i386_scale (cur_token.str)) | |
64a0c779 | 9643 | return 0; |
a724f0f4 JB |
9644 | intel_match_token (cur_token.code); |
9645 | } | |
64a0c779 | 9646 | |
a724f0f4 JB |
9647 | /* No scaling. If this is a memory operand, the register is either a |
9648 | base register (first occurrence) or an index register (second | |
9649 | occurrence). */ | |
7b0441f6 | 9650 | else if (intel_parser.in_bracket) |
a724f0f4 | 9651 | { |
64a0c779 | 9652 | |
a724f0f4 JB |
9653 | if (!i.base_reg) |
9654 | i.base_reg = reg; | |
9655 | else if (!i.index_reg) | |
9656 | i.index_reg = reg; | |
9657 | else | |
9658 | { | |
9659 | as_bad (_("Too many register references in memory operand")); | |
9660 | return 0; | |
9661 | } | |
64a0c779 | 9662 | |
40fb9820 | 9663 | i.types[this_operand].bitfield.baseindex = 1; |
a724f0f4 | 9664 | } |
4a1805b1 | 9665 | |
4d1bb795 JB |
9666 | /* It's neither base nor index. */ |
9667 | else if (!intel_parser.in_offset && !intel_parser.is_mem) | |
a724f0f4 | 9668 | { |
40fb9820 L |
9669 | i386_operand_type temp = reg->reg_type; |
9670 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9671 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9672 | temp); | |
7d5e4556 | 9673 | i.types[this_operand].bitfield.unspecified = 0; |
a724f0f4 JB |
9674 | i.op[this_operand].regs = reg; |
9675 | i.reg_operands++; | |
9676 | } | |
9677 | else | |
9678 | { | |
9679 | as_bad (_("Invalid use of register")); | |
9680 | return 0; | |
9681 | } | |
64a0c779 | 9682 | |
a724f0f4 JB |
9683 | /* Since registers are not part of the displacement string (except |
9684 | when we're parsing offset operands), we may need to remove any | |
9685 | preceding '+' from the displacement string. */ | |
9686 | if (*intel_parser.disp != '\0' | |
9687 | && !intel_parser.in_offset) | |
9688 | { | |
9689 | char *s = intel_parser.disp; | |
9690 | s += strlen (s) - 1; | |
9691 | if (*s == '+') | |
9692 | *s = '\0'; | |
9693 | } | |
4a1805b1 | 9694 | |
a724f0f4 JB |
9695 | return 1; |
9696 | } | |
9697 | ||
9698 | /* e11 BYTE | |
9699 | | WORD | |
9700 | | DWORD | |
9701 | | FWORD | |
9702 | | QWORD | |
9703 | | TBYTE | |
9704 | | OWORD | |
c0f3af97 L |
9705 | | XMMWORD |
9706 | | YMMWORD */ | |
a724f0f4 JB |
9707 | case T_BYTE: |
9708 | case T_WORD: | |
9709 | case T_DWORD: | |
9710 | case T_FWORD: | |
9711 | case T_QWORD: | |
9712 | case T_TBYTE: | |
9713 | case T_XMMWORD: | |
c0f3af97 | 9714 | case T_YMMWORD: |
a724f0f4 | 9715 | intel_match_token (cur_token.code); |
64a0c779 | 9716 | |
a724f0f4 JB |
9717 | if (cur_token.code == T_PTR) |
9718 | return 1; | |
9719 | ||
9720 | /* It must have been an identifier. */ | |
9721 | intel_putback_token (); | |
9722 | cur_token.code = T_ID; | |
9723 | /* FALLTHRU */ | |
9724 | ||
9725 | /* e11 id | |
9726 | | constant */ | |
9727 | case T_ID: | |
9728 | if (!intel_parser.in_offset && intel_parser.is_mem <= 0) | |
9306ca4a JB |
9729 | { |
9730 | symbolS *symbolP; | |
9731 | ||
a724f0f4 JB |
9732 | /* The identifier represents a memory reference only if it's not |
9733 | preceded by an offset modifier and if it's not an equate. */ | |
9306ca4a JB |
9734 | symbolP = symbol_find(cur_token.str); |
9735 | if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) | |
9736 | intel_parser.is_mem = 1; | |
9737 | } | |
a724f0f4 | 9738 | /* FALLTHRU */ |
64a0c779 | 9739 | |
a724f0f4 JB |
9740 | case T_CONST: |
9741 | case '-': | |
9742 | case '+': | |
9743 | { | |
9744 | char *save_str, sign = 0; | |
64a0c779 | 9745 | |
a724f0f4 JB |
9746 | /* Allow constants that start with `+' or `-'. */ |
9747 | if (cur_token.code == '-' || cur_token.code == '+') | |
9748 | { | |
9749 | sign = cur_token.code; | |
9750 | intel_match_token (cur_token.code); | |
9751 | if (cur_token.code != T_CONST) | |
9752 | { | |
9753 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
9754 | cur_token.str); | |
9755 | return 0; | |
9756 | } | |
9757 | } | |
64a0c779 | 9758 | |
a724f0f4 JB |
9759 | save_str = (char *) xmalloc (strlen (cur_token.str) + 2); |
9760 | strcpy (save_str + !!sign, cur_token.str); | |
9761 | if (sign) | |
9762 | *save_str = sign; | |
64a0c779 | 9763 | |
a724f0f4 JB |
9764 | /* Get the next token to check for register scaling. */ |
9765 | intel_match_token (cur_token.code); | |
64a0c779 | 9766 | |
4eed87de AM |
9767 | /* Check if this constant is a scaling factor for an |
9768 | index register. */ | |
a724f0f4 JB |
9769 | if (cur_token.code == '*') |
9770 | { | |
9771 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
9772 | { | |
9773 | const reg_entry *reg = cur_token.reg; | |
9774 | ||
9775 | if (!intel_parser.in_bracket) | |
9776 | { | |
4eed87de AM |
9777 | as_bad (_("Register scaling only allowed " |
9778 | "in memory operands")); | |
a724f0f4 JB |
9779 | return 0; |
9780 | } | |
9781 | ||
4eed87de AM |
9782 | /* Disallow things like [1*si]. |
9783 | sp and esp are invalid as index. */ | |
40fb9820 | 9784 | if (reg->reg_type.bitfield.reg16) |
4eed87de | 9785 | reg = i386_regtab + REGNAM_AX + 4; |
a724f0f4 | 9786 | else if (i.index_reg) |
4eed87de | 9787 | reg = i386_regtab + REGNAM_EAX + 4; |
a724f0f4 JB |
9788 | |
9789 | /* The constant is followed by `* reg', so it must be | |
9790 | a valid scale. */ | |
9791 | i.index_reg = reg; | |
40fb9820 | 9792 | i.types[this_operand].bitfield.baseindex = 1; |
a724f0f4 JB |
9793 | |
9794 | /* Set the scale after setting the register (otherwise, | |
9795 | i386_scale will complain) */ | |
9796 | if (!i386_scale (save_str)) | |
64a0c779 | 9797 | return 0; |
a724f0f4 JB |
9798 | intel_match_token (T_REG); |
9799 | ||
9800 | /* Since registers are not part of the displacement | |
9801 | string, we may need to remove any preceding '+' from | |
9802 | the displacement string. */ | |
9803 | if (*intel_parser.disp != '\0') | |
9804 | { | |
9805 | char *s = intel_parser.disp; | |
9806 | s += strlen (s) - 1; | |
9807 | if (*s == '+') | |
9808 | *s = '\0'; | |
9809 | } | |
9810 | ||
9811 | free (save_str); | |
9812 | ||
9813 | return 1; | |
9814 | } | |
64a0c779 | 9815 | |
a724f0f4 JB |
9816 | /* The constant was not used for register scaling. Since we have |
9817 | already consumed the token following `*' we now need to put it | |
9818 | back in the stream. */ | |
64a0c779 | 9819 | intel_putback_token (); |
a724f0f4 | 9820 | } |
64a0c779 | 9821 | |
a724f0f4 JB |
9822 | /* Add the constant to the displacement string. */ |
9823 | strcat (intel_parser.disp, save_str); | |
9824 | free (save_str); | |
64a0c779 | 9825 | |
a724f0f4 JB |
9826 | return 1; |
9827 | } | |
64a0c779 DN |
9828 | } |
9829 | ||
64a0c779 DN |
9830 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
9831 | return 0; | |
9832 | } | |
9833 | ||
64a0c779 DN |
9834 | /* Match the given token against cur_token. If they match, read the next |
9835 | token from the operand string. */ | |
9836 | static int | |
e3bb37b5 | 9837 | intel_match_token (int code) |
64a0c779 DN |
9838 | { |
9839 | if (cur_token.code == code) | |
9840 | { | |
9841 | intel_get_token (); | |
9842 | return 1; | |
9843 | } | |
9844 | else | |
9845 | { | |
0477af35 | 9846 | as_bad (_("Unexpected token `%s'"), cur_token.str); |
64a0c779 DN |
9847 | return 0; |
9848 | } | |
9849 | } | |
9850 | ||
64a0c779 DN |
9851 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
9852 | static void | |
e3bb37b5 | 9853 | intel_get_token (void) |
64a0c779 DN |
9854 | { |
9855 | char *end_op; | |
9856 | const reg_entry *reg; | |
9857 | struct intel_token new_token; | |
9858 | ||
9859 | new_token.code = T_NIL; | |
9860 | new_token.reg = NULL; | |
9861 | new_token.str = NULL; | |
9862 | ||
4a1805b1 | 9863 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
9864 | cur_token to prev_token. */ |
9865 | if (prev_token.str) | |
9866 | free (prev_token.str); | |
9867 | ||
9868 | prev_token = cur_token; | |
9869 | ||
9870 | /* Skip whitespace. */ | |
9871 | while (is_space_char (*intel_parser.op_string)) | |
9872 | intel_parser.op_string++; | |
9873 | ||
9874 | /* Return an empty token if we find nothing else on the line. */ | |
9875 | if (*intel_parser.op_string == '\0') | |
9876 | { | |
9877 | cur_token = new_token; | |
9878 | return; | |
9879 | } | |
9880 | ||
9881 | /* The new token cannot be larger than the remainder of the operand | |
9882 | string. */ | |
a724f0f4 | 9883 | new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); |
64a0c779 DN |
9884 | new_token.str[0] = '\0'; |
9885 | ||
9886 | if (strchr ("0123456789", *intel_parser.op_string)) | |
9887 | { | |
9888 | char *p = new_token.str; | |
9889 | char *q = intel_parser.op_string; | |
9890 | new_token.code = T_CONST; | |
9891 | ||
9892 | /* Allow any kind of identifier char to encompass floating point and | |
9893 | hexadecimal numbers. */ | |
9894 | while (is_identifier_char (*q)) | |
9895 | *p++ = *q++; | |
9896 | *p = '\0'; | |
9897 | ||
9898 | /* Recognize special symbol names [0-9][bf]. */ | |
9899 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 9900 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
9901 | || intel_parser.op_string[1] == 'f')) |
9902 | new_token.code = T_ID; | |
9903 | } | |
9904 | ||
4d1bb795 | 9905 | else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL) |
64a0c779 | 9906 | { |
4d1bb795 JB |
9907 | size_t len = end_op - intel_parser.op_string; |
9908 | ||
64a0c779 DN |
9909 | new_token.code = T_REG; |
9910 | new_token.reg = reg; | |
9911 | ||
4d1bb795 JB |
9912 | memcpy (new_token.str, intel_parser.op_string, len); |
9913 | new_token.str[len] = '\0'; | |
64a0c779 DN |
9914 | } |
9915 | ||
9916 | else if (is_identifier_char (*intel_parser.op_string)) | |
9917 | { | |
9918 | char *p = new_token.str; | |
9919 | char *q = intel_parser.op_string; | |
9920 | ||
9921 | /* A '.' or '$' followed by an identifier char is an identifier. | |
9922 | Otherwise, it's operator '.' followed by an expression. */ | |
9923 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
9924 | { | |
9306ca4a JB |
9925 | new_token.code = '.'; |
9926 | new_token.str[0] = '.'; | |
64a0c779 DN |
9927 | new_token.str[1] = '\0'; |
9928 | } | |
9929 | else | |
9930 | { | |
9931 | while (is_identifier_char (*q) || *q == '@') | |
9932 | *p++ = *q++; | |
9933 | *p = '\0'; | |
9934 | ||
9306ca4a JB |
9935 | if (strcasecmp (new_token.str, "NOT") == 0) |
9936 | new_token.code = '~'; | |
9937 | ||
9938 | else if (strcasecmp (new_token.str, "MOD") == 0) | |
9939 | new_token.code = '%'; | |
9940 | ||
9941 | else if (strcasecmp (new_token.str, "AND") == 0) | |
9942 | new_token.code = '&'; | |
9943 | ||
9944 | else if (strcasecmp (new_token.str, "OR") == 0) | |
9945 | new_token.code = '|'; | |
9946 | ||
9947 | else if (strcasecmp (new_token.str, "XOR") == 0) | |
9948 | new_token.code = '^'; | |
9949 | ||
9950 | else if (strcasecmp (new_token.str, "SHL") == 0) | |
9951 | new_token.code = T_SHL; | |
9952 | ||
9953 | else if (strcasecmp (new_token.str, "SHR") == 0) | |
9954 | new_token.code = T_SHR; | |
9955 | ||
9956 | else if (strcasecmp (new_token.str, "BYTE") == 0) | |
64a0c779 DN |
9957 | new_token.code = T_BYTE; |
9958 | ||
9959 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
9960 | new_token.code = T_WORD; | |
9961 | ||
9962 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
9963 | new_token.code = T_DWORD; | |
9964 | ||
9306ca4a JB |
9965 | else if (strcasecmp (new_token.str, "FWORD") == 0) |
9966 | new_token.code = T_FWORD; | |
9967 | ||
64a0c779 DN |
9968 | else if (strcasecmp (new_token.str, "QWORD") == 0) |
9969 | new_token.code = T_QWORD; | |
9970 | ||
9306ca4a JB |
9971 | else if (strcasecmp (new_token.str, "TBYTE") == 0 |
9972 | /* XXX remove (gcc still uses it) */ | |
9973 | || strcasecmp (new_token.str, "XWORD") == 0) | |
9974 | new_token.code = T_TBYTE; | |
9975 | ||
9976 | else if (strcasecmp (new_token.str, "XMMWORD") == 0 | |
9977 | || strcasecmp (new_token.str, "OWORD") == 0) | |
9978 | new_token.code = T_XMMWORD; | |
64a0c779 | 9979 | |
c0f3af97 L |
9980 | else if (strcasecmp (new_token.str, "YMMWORD") == 0) |
9981 | new_token.code = T_YMMWORD; | |
9982 | ||
64a0c779 DN |
9983 | else if (strcasecmp (new_token.str, "PTR") == 0) |
9984 | new_token.code = T_PTR; | |
9985 | ||
9986 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
9987 | new_token.code = T_SHORT; | |
9988 | ||
9989 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
9990 | { | |
9991 | new_token.code = T_OFFSET; | |
9992 | ||
9993 | /* ??? This is not mentioned in the MASM grammar but gcc | |
9994 | makes use of it with -mintel-syntax. OFFSET may be | |
9995 | followed by FLAT: */ | |
9996 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
9997 | strcat (new_token.str, " FLAT:"); | |
9998 | } | |
9999 | ||
64a0c779 DN |
10000 | else |
10001 | new_token.code = T_ID; | |
10002 | } | |
10003 | } | |
10004 | ||
9306ca4a JB |
10005 | else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) |
10006 | { | |
10007 | new_token.code = *intel_parser.op_string; | |
10008 | new_token.str[0] = *intel_parser.op_string; | |
10009 | new_token.str[1] = '\0'; | |
10010 | } | |
10011 | ||
10012 | else if (strchr ("<>", *intel_parser.op_string) | |
10013 | && *intel_parser.op_string == *(intel_parser.op_string + 1)) | |
10014 | { | |
10015 | new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; | |
10016 | new_token.str[0] = *intel_parser.op_string; | |
10017 | new_token.str[1] = *intel_parser.op_string; | |
10018 | new_token.str[2] = '\0'; | |
10019 | } | |
10020 | ||
64a0c779 | 10021 | else |
0477af35 | 10022 | as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); |
64a0c779 DN |
10023 | |
10024 | intel_parser.op_string += strlen (new_token.str); | |
10025 | cur_token = new_token; | |
10026 | } | |
10027 | ||
64a0c779 DN |
10028 | /* Put cur_token back into the token stream and make cur_token point to |
10029 | prev_token. */ | |
10030 | static void | |
e3bb37b5 | 10031 | intel_putback_token (void) |
64a0c779 | 10032 | { |
a724f0f4 JB |
10033 | if (cur_token.code != T_NIL) |
10034 | { | |
10035 | intel_parser.op_string -= strlen (cur_token.str); | |
10036 | free (cur_token.str); | |
10037 | } | |
64a0c779 | 10038 | cur_token = prev_token; |
4a1805b1 | 10039 | |
64a0c779 DN |
10040 | /* Forget prev_token. */ |
10041 | prev_token.code = T_NIL; | |
10042 | prev_token.reg = NULL; | |
10043 | prev_token.str = NULL; | |
10044 | } | |
54cfded0 | 10045 | |
a60de03c JB |
10046 | void |
10047 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 10048 | { |
a60de03c JB |
10049 | int saved_naked_reg; |
10050 | char saved_register_dot; | |
54cfded0 | 10051 | |
a60de03c JB |
10052 | saved_naked_reg = allow_naked_reg; |
10053 | allow_naked_reg = 1; | |
10054 | saved_register_dot = register_chars['.']; | |
10055 | register_chars['.'] = '.'; | |
10056 | allow_pseudo_reg = 1; | |
10057 | expression_and_evaluate (exp); | |
10058 | allow_pseudo_reg = 0; | |
10059 | register_chars['.'] = saved_register_dot; | |
10060 | allow_naked_reg = saved_naked_reg; | |
10061 | ||
10062 | if (exp->X_op == O_register && exp->X_add_number >= 0) | |
54cfded0 | 10063 | { |
a60de03c JB |
10064 | if ((addressT) exp->X_add_number < i386_regtab_size) |
10065 | { | |
10066 | exp->X_op = O_constant; | |
10067 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
10068 | .dw2_regnum[flag_code >> 1]; | |
10069 | } | |
10070 | else | |
10071 | exp->X_op = O_illegal; | |
54cfded0 | 10072 | } |
54cfded0 AM |
10073 | } |
10074 | ||
10075 | void | |
10076 | tc_x86_frame_initial_instructions (void) | |
10077 | { | |
a60de03c JB |
10078 | static unsigned int sp_regno[2]; |
10079 | ||
10080 | if (!sp_regno[flag_code >> 1]) | |
10081 | { | |
10082 | char *saved_input = input_line_pointer; | |
10083 | char sp[][4] = {"esp", "rsp"}; | |
10084 | expressionS exp; | |
a4447b93 | 10085 | |
a60de03c JB |
10086 | input_line_pointer = sp[flag_code >> 1]; |
10087 | tc_x86_parse_to_dw2regnum (&exp); | |
10088 | assert (exp.X_op == O_constant); | |
10089 | sp_regno[flag_code >> 1] = exp.X_add_number; | |
10090 | input_line_pointer = saved_input; | |
10091 | } | |
a4447b93 | 10092 | |
a60de03c | 10093 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
a4447b93 | 10094 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
54cfded0 | 10095 | } |
d2b2c203 DJ |
10096 | |
10097 | int | |
10098 | i386_elf_section_type (const char *str, size_t len) | |
10099 | { | |
10100 | if (flag_code == CODE_64BIT | |
10101 | && len == sizeof ("unwind") - 1 | |
10102 | && strncmp (str, "unwind", 6) == 0) | |
10103 | return SHT_X86_64_UNWIND; | |
10104 | ||
10105 | return -1; | |
10106 | } | |
bb41ade5 AM |
10107 | |
10108 | #ifdef TE_PE | |
10109 | void | |
10110 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
10111 | { | |
10112 | expressionS expr; | |
10113 | ||
10114 | expr.X_op = O_secrel; | |
10115 | expr.X_add_symbol = symbol; | |
10116 | expr.X_add_number = 0; | |
10117 | emit_expr (&expr, size); | |
10118 | } | |
10119 | #endif | |
3b22753a L |
10120 | |
10121 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10122 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
10123 | ||
10124 | int | |
10125 | x86_64_section_letter (int letter, char **ptr_msg) | |
10126 | { | |
10127 | if (flag_code == CODE_64BIT) | |
10128 | { | |
10129 | if (letter == 'l') | |
10130 | return SHF_X86_64_LARGE; | |
10131 | ||
10132 | *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); | |
64e74474 | 10133 | } |
3b22753a | 10134 | else |
64e74474 | 10135 | *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
10136 | return -1; |
10137 | } | |
10138 | ||
10139 | int | |
10140 | x86_64_section_word (char *str, size_t len) | |
10141 | { | |
8620418b | 10142 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
10143 | return SHF_X86_64_LARGE; |
10144 | ||
10145 | return -1; | |
10146 | } | |
10147 | ||
10148 | static void | |
10149 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
10150 | { | |
10151 | if (flag_code != CODE_64BIT) | |
10152 | { | |
10153 | s_comm_internal (0, elf_common_parse); | |
10154 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
10155 | } | |
10156 | else | |
10157 | { | |
10158 | static segT lbss_section; | |
10159 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
10160 | asection *saved_bss_section = bss_section; | |
10161 | ||
10162 | if (lbss_section == NULL) | |
10163 | { | |
10164 | flagword applicable; | |
10165 | segT seg = now_seg; | |
10166 | subsegT subseg = now_subseg; | |
10167 | ||
10168 | /* The .lbss section is for local .largecomm symbols. */ | |
10169 | lbss_section = subseg_new (".lbss", 0); | |
10170 | applicable = bfd_applicable_section_flags (stdoutput); | |
10171 | bfd_set_section_flags (stdoutput, lbss_section, | |
10172 | applicable & SEC_ALLOC); | |
10173 | seg_info (lbss_section)->bss = 1; | |
10174 | ||
10175 | subseg_set (seg, subseg); | |
10176 | } | |
10177 | ||
10178 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
10179 | bss_section = lbss_section; | |
10180 | ||
10181 | s_comm_internal (0, elf_common_parse); | |
10182 | ||
10183 | elf_com_section_ptr = saved_com_section_ptr; | |
10184 | bss_section = saved_bss_section; | |
10185 | } | |
10186 | } | |
10187 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |