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* cr16-dis.c (getcinvstring): Add const qualifier to char * parameter.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
9103f4f4 434 {"i386", PROCESSOR_GENERIC32,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
42903f7f
L		 501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
381d071f
L		 503 {".sse4.2", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
505 {".sse4", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
9103f4f4
L		 507 {".3dnow", PROCESSOR_UNKNOWN,
508 CpuMMX|Cpu3dnow},
509 {".3dnowa", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
511 {".padlock", PROCESSOR_UNKNOWN,
512 CpuPadLock},
513 {".pacifica", PROCESSOR_UNKNOWN,
514 CpuSVME},
515 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 516 CpuSVME},
517 {".sse4a", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
519 {".abm", PROCESSOR_UNKNOWN,
520 CpuABM}
e413e4e9
AM		 521};
522
29b0f896
AM		 523const pseudo_typeS md_pseudo_table[] =
524{
525#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes, 0},
527#else
528 {"align", s_align_ptwo, 0},
529#endif
530 {"arch", set_cpu_arch, 0},
531#ifndef I386COFF
532 {"bss", s_bss, 0},
533#endif
534 {"ffloat", float_cons, 'f'},
535 {"dfloat", float_cons, 'd'},
536 {"tfloat", float_cons, 'x'},
537 {"value", cons, 2},
d182319b 538 {"slong", signed_cons, 4},
29b0f896
AM		 539 {"noopt", s_ignore, 0},
540 {"optim", s_ignore, 0},
541 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
542 {"code16", set_code_flag, CODE_16BIT},
543 {"code32", set_code_flag, CODE_32BIT},
544 {"code64", set_code_flag, CODE_64BIT},
545 {"intel_syntax", set_intel_syntax, 1},
546 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common, 0},
07a53e5c 549#else
e3bb37b5 550 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 551 {"loc", dwarf2_directive_loc, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 553#endif
6482c264
NC		 554#ifdef TE_PE
555 {"secrel32", pe_directive_secrel, 0},
556#endif
29b0f896
AM		 557 {0, 0, 0}
558};
559
560/* For interface with expression (). */
561extern char *input_line_pointer;
562
563/* Hash table for instruction mnemonic lookup. */
564static struct hash_control *op_hash;
565
566/* Hash table for register lookup. */
567static struct hash_control *reg_hash;
568\f
252b5132 569void
e3bb37b5 570i386_align_code (fragS *fragP, int count)
252b5132 571{
ce8a8b2f
AM		 572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
252b5132
RH		 575 static const char f32_1[] =
576 {0x90}; /* nop */
577 static const char f32_2[] =
ccc9c027 578 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 579 static const char f32_3[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5[] =
584 {0x90, /* nop */
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8[] =
591 {0x90, /* nop */
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_15[] =
612 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
613 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 614 static const char f16_3[] =
615 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 616 static const char f16_4[] =
617 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_5[] =
619 {0x90, /* nop */
620 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
621 static const char f16_6[] =
622 {0x89,0xf6, /* mov %si,%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_7[] =
625 {0x8d,0x74,0x00, /* lea 0(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
627 static const char f16_8[] =
628 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
629 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
630 static const char *const f32_patt[] = {
631 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
632 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
633 };
634 static const char *const f16_patt[] = {
c3332e24 635 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 636 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
637 };
ccc9c027
L		 638 /* nopl (%[re]ax) */
639 static const char alt_3[] =
640 {0x0f,0x1f,0x00};
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
665 {0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
671 {0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
679 {0x66,
680 0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 /* data16
695 data16
696 data16
697 data16
698 data16
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
701 {0x66,
702 0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax) */
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 /* nopl 0L(%[re]ax)
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
736 };
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
741 };
252b5132 742
33fef721
JH		 743 if (count <= 0 || count > 15)
744 return;
3e73aa7c 745
ccc9c027
L		 746 /* We need to decide which NOP sequence to use for 32bit and
747 64bit. When -mtune= is used:
4eed87de 748
ccc9c027
L		 749 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
750 f32_patt will be used.
4eed87de
AM		 751 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
752 0x66 prefix will be used.
ef05d495 753 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 755 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
757
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
760
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
763
764 if (flag_code == CODE_16BIT)
765 {
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
768 if (count > 8)
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 }
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 773 {
33fef721
JH		 774 int i;
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
778 int pos = 0;
779
ccc9c027 780 /* The recommended way to pad 64bit code is to use NOPs preceded
4eed87de 781 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 782 for (i = 0; i < remains; i++)
252b5132 783 {
33fef721
JH		 784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
786 pos += len + 1;
787 }
788 for (; i < nnops; i++)
789 {
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
792 pos += len;
252b5132 793 }
252b5132 794 }
33fef721 795 else
ccc9c027
L		 796 {
797 const char *const *patt = NULL;
798
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
800 {
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
803 {
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
809 else
810 patt = f32_patt;
811 break;
ef05d495 812 case PROCESSOR_CORE2:
ccc9c027
L		 813 patt = alt_long_patt;
814 break;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
ef05d495 818 case PROCESSOR_CORE:
ccc9c027
L		 819 case PROCESSOR_K6:
820 case PROCESSOR_ATHLON:
821 case PROCESSOR_K8:
822 case PROCESSOR_GENERIC64:
4eed87de 823 case PROCESSOR_AMDFAM10:
ccc9c027
L		 824 patt = alt_short_patt;
825 break;
826 case PROCESSOR_I486:
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
829 patt = f32_patt;
830 break;
4eed87de 831 }
ccc9c027
L		 832 }
833 else
834 {
835 switch (cpu_arch_tune)
836 {
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
840 abort ();
841 break;
842
843 case PROCESSOR_I486:
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
ef05d495 848 case PROCESSOR_CORE:
ccc9c027
L		 849 case PROCESSOR_K6:
850 case PROCESSOR_ATHLON:
851 case PROCESSOR_K8:
4eed87de 852 case PROCESSOR_AMDFAM10:
ccc9c027
L		 853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
855 for Cpu686. */
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
858 else
859 patt = f32_patt;
860 break;
ef05d495 861 case PROCESSOR_CORE2:
ccc9c027
L		 862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
864 else
865 patt = f32_patt;
866 break;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
869 break;
4eed87de 870 }
ccc9c027
L		 871 }
872
33fef721 873 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 874 patt[count - 1], count);
875 }
33fef721 876 fragP->fr_var = count;
252b5132
RH		 877}
878
252b5132 879static INLINE unsigned int
e3bb37b5 880mode_from_disp_size (unsigned int t)
252b5132 881{
3e73aa7c 882 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 883}
884
885static INLINE int
e3bb37b5 886fits_in_signed_byte (offsetT num)
252b5132
RH		 887{
888 return (num >= -128) && (num <= 127);
47926f60 889}
252b5132
RH		 890
891static INLINE int
e3bb37b5 892fits_in_unsigned_byte (offsetT num)
252b5132
RH		 893{
894 return (num & 0xff) == num;
47926f60 895}
252b5132
RH		 896
897static INLINE int
e3bb37b5 898fits_in_unsigned_word (offsetT num)
252b5132
RH		 899{
900 return (num & 0xffff) == num;
47926f60 901}
252b5132
RH		 902
903static INLINE int
e3bb37b5 904fits_in_signed_word (offsetT num)
252b5132
RH		 905{
906 return (-32768 <= num) && (num <= 32767);
47926f60 907}
2a962e6d 908
3e73aa7c 909static INLINE int
e3bb37b5 910fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 911{
912#ifndef BFD64
913 return 1;
914#else
915 return (!(((offsetT) -1 << 31) & num)
916 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
917#endif
918} /* fits_in_signed_long() */
2a962e6d 919
3e73aa7c 920static INLINE int
e3bb37b5 921fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 922{
923#ifndef BFD64
924 return 1;
925#else
926 return (num & (((offsetT) 2 << 31) - 1)) == num;
927#endif
928} /* fits_in_unsigned_long() */
252b5132 929
1509aa9a 930static unsigned int
e3bb37b5 931smallest_imm_type (offsetT num)
252b5132 932{
d32cad65 933 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 934 {
935 /* This code is disabled on the 486 because all the Imm1 forms
936 in the opcode table are slower on the i486. They're the
937 versions with the implicitly specified single-position
938 displacement, which has another syntax if you really want to
939 use that form. */
940 if (num == 1)
3e73aa7c 941 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 942 }
252b5132 943 return (fits_in_signed_byte (num)
3e73aa7c 944 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 945 : fits_in_unsigned_byte (num)
3e73aa7c 946 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 947 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 948 ? (Imm16 | Imm32 | Imm32S | Imm64)
949 : fits_in_signed_long (num)
950 ? (Imm32 | Imm32S | Imm64)
951 : fits_in_unsigned_long (num)
952 ? (Imm32 | Imm64)
953 : Imm64);
47926f60 954}
252b5132 955
847f7ad4 956static offsetT
e3bb37b5 957offset_in_range (offsetT val, int size)
847f7ad4 958{
508866be 959 addressT mask;
ba2adb93 960
847f7ad4
AM		 961 switch (size)
962 {
508866be
L		 963 case 1: mask = ((addressT) 1 << 8) - 1; break;
964 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 965 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 966#ifdef BFD64
967 case 8: mask = ((addressT) 2 << 63) - 1; break;
968#endif
47926f60 969 default: abort ();
847f7ad4
AM		 970 }
971
ba2adb93 972 /* If BFD64, sign extend val. */
3e73aa7c
JH		 973 if (!use_rela_relocations)
974 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
975 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 976
47926f60 977 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 978 {
979 char buf1[40], buf2[40];
980
981 sprint_value (buf1, val);
982 sprint_value (buf2, val & mask);
983 as_warn (_("%s shortened to %s"), buf1, buf2);
984 }
985 return val & mask;
986}
987
252b5132
RH		 988/* Returns 0 if attempting to add a prefix where one from the same
989 class already exists, 1 if non rep/repne added, 2 if rep/repne
990 added. */
991static int
e3bb37b5 992add_prefix (unsigned int prefix)
252b5132
RH		 993{
994 int ret = 1;
b1905489 995 unsigned int q;
252b5132 996
29b0f896
AM		 997 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
998 && flag_code == CODE_64BIT)
b1905489 999 {
161a04f6
L		 1000 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1001 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1002 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1003 ret = 0;
1004 q = REX_PREFIX;
1005 }
3e73aa7c 1006 else
b1905489
JB		 1007 {
1008 switch (prefix)
1009 {
1010 default:
1011 abort ();
1012
1013 case CS_PREFIX_OPCODE:
1014 case DS_PREFIX_OPCODE:
1015 case ES_PREFIX_OPCODE:
1016 case FS_PREFIX_OPCODE:
1017 case GS_PREFIX_OPCODE:
1018 case SS_PREFIX_OPCODE:
1019 q = SEG_PREFIX;
1020 break;
1021
1022 case REPNE_PREFIX_OPCODE:
1023 case REPE_PREFIX_OPCODE:
1024 ret = 2;
1025 /* fall thru */
1026 case LOCK_PREFIX_OPCODE:
1027 q = LOCKREP_PREFIX;
1028 break;
1029
1030 case FWAIT_OPCODE:
1031 q = WAIT_PREFIX;
1032 break;
1033
1034 case ADDR_PREFIX_OPCODE:
1035 q = ADDR_PREFIX;
1036 break;
1037
1038 case DATA_PREFIX_OPCODE:
1039 q = DATA_PREFIX;
1040 break;
1041 }
1042 if (i.prefix[q] != 0)
1043 ret = 0;
1044 }
252b5132 1045
b1905489 1046 if (ret)
252b5132 1047 {
b1905489
JB		 1048 if (!i.prefix[q])
1049 ++i.prefixes;
1050 i.prefix[q] |= prefix;
252b5132 1051 }
b1905489
JB		 1052 else
1053 as_bad (_("same type of prefix used twice"));
252b5132 1054
252b5132
RH		 1055 return ret;
1056}
1057
1058static void
e3bb37b5 1059set_code_flag (int value)
eecb386c 1060{
3e73aa7c
JH		 1061 flag_code = value;
1062 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1063 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1064 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1065 {
1066 as_bad (_("64bit mode not supported on this CPU."));
1067 }
1068 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1069 {
1070 as_bad (_("32bit mode not supported on this CPU."));
1071 }
eecb386c
AM		 1072 stackop_size = '\0';
1073}
1074
1075static void
e3bb37b5 1076set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1077{
3e73aa7c
JH		 1078 flag_code = new_code_flag;
1079 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1080 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1081 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1082}
1083
1084static void
e3bb37b5 1085set_intel_syntax (int syntax_flag)
252b5132
RH		 1086{
1087 /* Find out if register prefixing is specified. */
1088 int ask_naked_reg = 0;
1089
1090 SKIP_WHITESPACE ();
29b0f896 1091 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1092 {
1093 char *string = input_line_pointer;
1094 int e = get_symbol_end ();
1095
47926f60 1096 if (strcmp (string, "prefix") == 0)
252b5132 1097 ask_naked_reg = 1;
47926f60 1098 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1099 ask_naked_reg = -1;
1100 else
d0b47220 1101 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1102 *input_line_pointer = e;
1103 }
1104 demand_empty_rest_of_line ();
c3332e24 1105
252b5132
RH		 1106 intel_syntax = syntax_flag;
1107
1108 if (ask_naked_reg == 0)
f86103b7
AM		 1109 allow_naked_reg = (intel_syntax
1110 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1111 else
1112 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1113
e4a3b5a4 1114 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1115 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1116 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1117}
1118
e413e4e9 1119static void
e3bb37b5 1120set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1121{
47926f60 1122 SKIP_WHITESPACE ();
e413e4e9 1123
29b0f896 1124 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1125 {
1126 char *string = input_line_pointer;
1127 int e = get_symbol_end ();
9103f4f4 1128 unsigned int i;
e413e4e9 1129
9103f4f4 1130 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1131 {
1132 if (strcmp (string, cpu_arch[i].name) == 0)
1133 {
5c6af06e
JB		 1134 if (*string != '.')
1135 {
1136 cpu_arch_name = cpu_arch[i].name;
1137 cpu_sub_arch_name = NULL;
1138 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1139 | (flag_code == CODE_64BIT
1140 ? Cpu64 : CpuNo64));
ccc9c027 1141 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1142 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1143 if (!cpu_arch_tune_set)
1144 {
1145 cpu_arch_tune = cpu_arch_isa;
1146 cpu_arch_tune_flags = cpu_arch_isa_flags;
1147 }
5c6af06e
JB		 1148 break;
1149 }
1150 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1151 {
1152 cpu_sub_arch_name = cpu_arch[i].name;
1153 cpu_arch_flags |= cpu_arch[i].flags;
1154 }
1155 *input_line_pointer = e;
1156 demand_empty_rest_of_line ();
1157 return;
e413e4e9
AM		 1158 }
1159 }
9103f4f4 1160 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1161 as_bad (_("no such architecture: `%s'"), string);
1162
1163 *input_line_pointer = e;
1164 }
1165 else
1166 as_bad (_("missing cpu architecture"));
1167
fddf5b5b
AM		 1168 no_cond_jump_promotion = 0;
1169 if (*input_line_pointer == ','
29b0f896 1170 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1171 {
1172 char *string = ++input_line_pointer;
1173 int e = get_symbol_end ();
1174
1175 if (strcmp (string, "nojumps") == 0)
1176 no_cond_jump_promotion = 1;
1177 else if (strcmp (string, "jumps") == 0)
1178 ;
1179 else
1180 as_bad (_("no such architecture modifier: `%s'"), string);
1181
1182 *input_line_pointer = e;
1183 }
1184
e413e4e9
AM		 1185 demand_empty_rest_of_line ();
1186}
1187
b9d79e03
JH		 1188unsigned long
1189i386_mach ()
1190{
1191 if (!strcmp (default_arch, "x86_64"))
1192 return bfd_mach_x86_64;
1193 else if (!strcmp (default_arch, "i386"))
1194 return bfd_mach_i386_i386;
1195 else
1196 as_fatal (_("Unknown architecture"));
1197}
b9d79e03 1198\f
252b5132
RH		 1199void
1200md_begin ()
1201{
1202 const char *hash_err;
1203
47926f60 1204 /* Initialize op_hash hash table. */
252b5132
RH		 1205 op_hash = hash_new ();
1206
1207 {
29b0f896
AM		 1208 const template *optab;
1209 templates *core_optab;
252b5132 1210
47926f60
KH		 1211 /* Setup for loop. */
1212 optab = i386_optab;
252b5132
RH		 1213 core_optab = (templates *) xmalloc (sizeof (templates));
1214 core_optab->start = optab;
1215
1216 while (1)
1217 {
1218 ++optab;
1219 if (optab->name == NULL
1220 || strcmp (optab->name, (optab - 1)->name) != 0)
1221 {
1222 /* different name --> ship out current template list;
47926f60 1223 add to hash table; & begin anew. */
252b5132
RH		 1224 core_optab->end = optab;
1225 hash_err = hash_insert (op_hash,
1226 (optab - 1)->name,
1227 (PTR) core_optab);
1228 if (hash_err)
1229 {
252b5132
RH		 1230 as_fatal (_("Internal Error: Can't hash %s: %s"),
1231 (optab - 1)->name,
1232 hash_err);
1233 }
1234 if (optab->name == NULL)
1235 break;
1236 core_optab = (templates *) xmalloc (sizeof (templates));
1237 core_optab->start = optab;
1238 }
1239 }
1240 }
1241
47926f60 1242 /* Initialize reg_hash hash table. */
252b5132
RH		 1243 reg_hash = hash_new ();
1244 {
29b0f896 1245 const reg_entry *regtab;
c3fe08fa 1246 unsigned int regtab_size = i386_regtab_size;
252b5132 1247
c3fe08fa 1248 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1249 {
1250 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1251 if (hash_err)
3e73aa7c
JH		 1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 regtab->reg_name,
1254 hash_err);
252b5132
RH		 1255 }
1256 }
1257
47926f60 1258 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1259 {
29b0f896
AM		 1260 int c;
1261 char *p;
252b5132
RH		 1262
1263 for (c = 0; c < 256; c++)
1264 {
3882b010 1265 if (ISDIGIT (c))
252b5132
RH		 1266 {
1267 digit_chars[c] = c;
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1271 }
3882b010 1272 else if (ISLOWER (c))
252b5132
RH		 1273 {
1274 mnemonic_chars[c] = c;
1275 register_chars[c] = c;
1276 operand_chars[c] = c;
1277 }
3882b010 1278 else if (ISUPPER (c))
252b5132 1279 {
3882b010 1280 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1281 register_chars[c] = mnemonic_chars[c];
1282 operand_chars[c] = c;
1283 }
1284
3882b010 1285 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1286 identifier_chars[c] = c;
1287 else if (c >= 128)
1288 {
1289 identifier_chars[c] = c;
1290 operand_chars[c] = c;
1291 }
1292 }
1293
1294#ifdef LEX_AT
1295 identifier_chars['@'] = '@';
32137342
NC		 1296#endif
1297#ifdef LEX_QM
1298 identifier_chars['?'] = '?';
1299 operand_chars['?'] = '?';
252b5132 1300#endif
252b5132 1301 digit_chars['-'] = '-';
791fe849 1302 mnemonic_chars['-'] = '-';
0003779b 1303 mnemonic_chars['.'] = '.';
252b5132
RH		 1304 identifier_chars['_'] = '_';
1305 identifier_chars['.'] = '.';
1306
1307 for (p = operand_special_chars; *p != '\0'; p++)
1308 operand_chars[(unsigned char) *p] = *p;
1309 }
1310
1311#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1312 if (IS_ELF)
252b5132
RH		 1313 {
1314 record_alignment (text_section, 2);
1315 record_alignment (data_section, 2);
1316 record_alignment (bss_section, 2);
1317 }
1318#endif
a4447b93
RH		 1319
1320 if (flag_code == CODE_64BIT)
1321 {
1322 x86_dwarf2_return_column = 16;
1323 x86_cie_data_alignment = -8;
1324 }
1325 else
1326 {
1327 x86_dwarf2_return_column = 8;
1328 x86_cie_data_alignment = -4;
1329 }
252b5132
RH		 1330}
1331
1332void
e3bb37b5 1333i386_print_statistics (FILE *file)
252b5132
RH		 1334{
1335 hash_print_statistics (file, "i386 opcode", op_hash);
1336 hash_print_statistics (file, "i386 register", reg_hash);
1337}
1338\f
252b5132
RH		 1339#ifdef DEBUG386
1340
ce8a8b2f 1341/* Debugging routines for md_assemble. */
e3bb37b5
L		 1342static void pte (template *);
1343static void pt (unsigned int);
1344static void pe (expressionS *);
1345static void ps (symbolS *);
252b5132
RH		 1346
1347static void
e3bb37b5 1348pi (char *line, i386_insn *x)
252b5132 1349{
09f131f2 1350 unsigned int i;
252b5132
RH		 1351
1352 fprintf (stdout, "%s: template ", line);
1353 pte (&x->tm);
09f131f2
JH		 1354 fprintf (stdout, " address: base %s index %s scale %x\n",
1355 x->base_reg ? x->base_reg->reg_name : "none",
1356 x->index_reg ? x->index_reg->reg_name : "none",
1357 x->log2_scale_factor);
1358 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1359 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1360 fprintf (stdout, " sib: base %x index %x scale %x\n",
1361 x->sib.base, x->sib.index, x->sib.scale);
1362 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1363 (x->rex & REX_W) != 0,
1364 (x->rex & REX_R) != 0,
1365 (x->rex & REX_X) != 0,
1366 (x->rex & REX_B) != 0);
252b5132
RH		 1367 for (i = 0; i < x->operands; i++)
1368 {
1369 fprintf (stdout, " #%d: ", i + 1);
1370 pt (x->types[i]);
1371 fprintf (stdout, "\n");
1372 if (x->types[i]
3f4438ab 1373 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1374 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1375 if (x->types[i] & Imm)
520dc8e8 1376 pe (x->op[i].imms);
252b5132 1377 if (x->types[i] & Disp)
520dc8e8 1378 pe (x->op[i].disps);
252b5132
RH		 1379 }
1380}
1381
1382static void
e3bb37b5 1383pte (template *t)
252b5132 1384{
09f131f2 1385 unsigned int i;
252b5132 1386 fprintf (stdout, " %d operands ", t->operands);
47926f60 1387 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1388 if (t->extension_opcode != None)
1389 fprintf (stdout, "ext %x ", t->extension_opcode);
1390 if (t->opcode_modifier & D)
1391 fprintf (stdout, "D");
1392 if (t->opcode_modifier & W)
1393 fprintf (stdout, "W");
1394 fprintf (stdout, "\n");
1395 for (i = 0; i < t->operands; i++)
1396 {
1397 fprintf (stdout, " #%d type ", i + 1);
1398 pt (t->operand_types[i]);
1399 fprintf (stdout, "\n");
1400 }
1401}
1402
1403static void
e3bb37b5 1404pe (expressionS *e)
252b5132 1405{
24eab124 1406 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1407 fprintf (stdout, " add_number %ld (%lx)\n",
1408 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1409 if (e->X_add_symbol)
1410 {
1411 fprintf (stdout, " add_symbol ");
1412 ps (e->X_add_symbol);
1413 fprintf (stdout, "\n");
1414 }
1415 if (e->X_op_symbol)
1416 {
1417 fprintf (stdout, " op_symbol ");
1418 ps (e->X_op_symbol);
1419 fprintf (stdout, "\n");
1420 }
1421}
1422
1423static void
e3bb37b5 1424ps (symbolS *s)
252b5132
RH		 1425{
1426 fprintf (stdout, "%s type %s%s",
1427 S_GET_NAME (s),
1428 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1429 segment_name (S_GET_SEGMENT (s)));
1430}
1431
7b81dfbb 1432static struct type_name
252b5132
RH		 1433 {
1434 unsigned int mask;
1435 char *tname;
1436 }
7b81dfbb 1437const type_names[] =
252b5132
RH		 1438{
1439 { Reg8, "r8" },
1440 { Reg16, "r16" },
1441 { Reg32, "r32" },
09f131f2 1442 { Reg64, "r64" },
252b5132
RH		 1443 { Imm8, "i8" },
1444 { Imm8S, "i8s" },
1445 { Imm16, "i16" },
1446 { Imm32, "i32" },
09f131f2
JH		 1447 { Imm32S, "i32s" },
1448 { Imm64, "i64" },
252b5132
RH		 1449 { Imm1, "i1" },
1450 { BaseIndex, "BaseIndex" },
1451 { Disp8, "d8" },
1452 { Disp16, "d16" },
1453 { Disp32, "d32" },
09f131f2
JH		 1454 { Disp32S, "d32s" },
1455 { Disp64, "d64" },
252b5132
RH		 1456 { InOutPortReg, "InOutPortReg" },
1457 { ShiftCount, "ShiftCount" },
1458 { Control, "control reg" },
1459 { Test, "test reg" },
1460 { Debug, "debug reg" },
1461 { FloatReg, "FReg" },
1462 { FloatAcc, "FAcc" },
1463 { SReg2, "SReg2" },
1464 { SReg3, "SReg3" },
1465 { Acc, "Acc" },
1466 { JumpAbsolute, "Jump Absolute" },
1467 { RegMMX, "rMMX" },
3f4438ab 1468 { RegXMM, "rXMM" },
252b5132
RH		 1469 { EsSeg, "es" },
1470 { 0, "" }
1471};
1472
1473static void
1474pt (t)
1475 unsigned int t;
1476{
29b0f896 1477 const struct type_name *ty;
252b5132 1478
09f131f2
JH		 1479 for (ty = type_names; ty->mask; ty++)
1480 if (t & ty->mask)
1481 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1482 fflush (stdout);
1483}
1484
1485#endif /* DEBUG386 */
1486\f
252b5132 1487static bfd_reloc_code_real_type
3956db08 1488reloc (unsigned int size,
64e74474
AM		 1489 int pcrel,
1490 int sign,
1491 bfd_reloc_code_real_type other)
252b5132 1492{
47926f60 1493 if (other != NO_RELOC)
3956db08
JB		 1494 {
1495 reloc_howto_type *reloc;
1496
1497 if (size == 8)
1498 switch (other)
1499 {
64e74474
AM		 1500 case BFD_RELOC_X86_64_GOT32:
1501 return BFD_RELOC_X86_64_GOT64;
1502 break;
1503 case BFD_RELOC_X86_64_PLTOFF64:
1504 return BFD_RELOC_X86_64_PLTOFF64;
1505 break;
1506 case BFD_RELOC_X86_64_GOTPC32:
1507 other = BFD_RELOC_X86_64_GOTPC64;
1508 break;
1509 case BFD_RELOC_X86_64_GOTPCREL:
1510 other = BFD_RELOC_X86_64_GOTPCREL64;
1511 break;
1512 case BFD_RELOC_X86_64_TPOFF32:
1513 other = BFD_RELOC_X86_64_TPOFF64;
1514 break;
1515 case BFD_RELOC_X86_64_DTPOFF32:
1516 other = BFD_RELOC_X86_64_DTPOFF64;
1517 break;
1518 default:
1519 break;
3956db08 1520 }
e05278af
JB		 1521
1522 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1523 if (size == 4 && flag_code != CODE_64BIT)
1524 sign = -1;
1525
3956db08
JB		 1526 reloc = bfd_reloc_type_lookup (stdoutput, other);
1527 if (!reloc)
1528 as_bad (_("unknown relocation (%u)"), other);
1529 else if (size != bfd_get_reloc_size (reloc))
1530 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1531 bfd_get_reloc_size (reloc),
1532 size);
1533 else if (pcrel && !reloc->pc_relative)
1534 as_bad (_("non-pc-relative relocation for pc-relative field"));
1535 else if ((reloc->complain_on_overflow == complain_overflow_signed
1536 && !sign)
1537 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1538 && sign > 0))
3956db08
JB		 1539 as_bad (_("relocated field and relocation type differ in signedness"));
1540 else
1541 return other;
1542 return NO_RELOC;
1543 }
252b5132
RH		 1544
1545 if (pcrel)
1546 {
3e73aa7c 1547 if (!sign)
3956db08 1548 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1549 switch (size)
1550 {
1551 case 1: return BFD_RELOC_8_PCREL;
1552 case 2: return BFD_RELOC_16_PCREL;
1553 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1554 case 8: return BFD_RELOC_64_PCREL;
252b5132 1555 }
3956db08 1556 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1557 }
1558 else
1559 {
3956db08 1560 if (sign > 0)
e5cb08ac 1561 switch (size)
3e73aa7c
JH		 1562 {
1563 case 4: return BFD_RELOC_X86_64_32S;
1564 }
1565 else
1566 switch (size)
1567 {
1568 case 1: return BFD_RELOC_8;
1569 case 2: return BFD_RELOC_16;
1570 case 4: return BFD_RELOC_32;
1571 case 8: return BFD_RELOC_64;
1572 }
3956db08
JB		 1573 as_bad (_("cannot do %s %u byte relocation"),
1574 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1575 }
1576
bfb32b52 1577 abort ();
252b5132
RH		 1578 return BFD_RELOC_NONE;
1579}
1580
47926f60
KH		 1581/* Here we decide which fixups can be adjusted to make them relative to
1582 the beginning of the section instead of the symbol. Basically we need
1583 to make sure that the dynamic relocations are done correctly, so in
1584 some cases we force the original symbol to be used. */
1585
252b5132 1586int
e3bb37b5 1587tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1588{
6d249963 1589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1590 if (!IS_ELF)
31312f95
AM		 1591 return 1;
1592
a161fe53
AM		 1593 /* Don't adjust pc-relative references to merge sections in 64-bit
1594 mode. */
1595 if (use_rela_relocations
1596 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1597 && fixP->fx_pcrel)
252b5132 1598 return 0;
31312f95 1599
8d01d9a9
AJ		 1600 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1601 and changed later by validate_fix. */
1602 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1603 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1604 return 0;
1605
ce8a8b2f 1606 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1607 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1608 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1609 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1614 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1615 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1616 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1617 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1618 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1619 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1623 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1626 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1627 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1628 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1629 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1630 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1631 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1632 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1633 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1634 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1635 return 0;
31312f95 1636#endif
252b5132
RH		 1637 return 1;
1638}
252b5132 1639
b4cac588 1640static int
e3bb37b5 1641intel_float_operand (const char *mnemonic)
252b5132 1642{
9306ca4a
JB		 1643 /* Note that the value returned is meaningful only for opcodes with (memory)
1644 operands, hence the code here is free to improperly handle opcodes that
1645 have no operands (for better performance and smaller code). */
1646
1647 if (mnemonic[0] != 'f')
1648 return 0; /* non-math */
1649
1650 switch (mnemonic[1])
1651 {
1652 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1653 the fs segment override prefix not currently handled because no
1654 call path can make opcodes without operands get here */
1655 case 'i':
1656 return 2 /* integer op */;
1657 case 'l':
1658 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1659 return 3; /* fldcw/fldenv */
1660 break;
1661 case 'n':
1662 if (mnemonic[2] != 'o' /* fnop */)
1663 return 3; /* non-waiting control op */
1664 break;
1665 case 'r':
1666 if (mnemonic[2] == 's')
1667 return 3; /* frstor/frstpm */
1668 break;
1669 case 's':
1670 if (mnemonic[2] == 'a')
1671 return 3; /* fsave */
1672 if (mnemonic[2] == 't')
1673 {
1674 switch (mnemonic[3])
1675 {
1676 case 'c': /* fstcw */
1677 case 'd': /* fstdw */
1678 case 'e': /* fstenv */
1679 case 's': /* fsts[gw] */
1680 return 3;
1681 }
1682 }
1683 break;
1684 case 'x':
1685 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1686 return 0; /* fxsave/fxrstor are not really math ops */
1687 break;
1688 }
252b5132 1689
9306ca4a 1690 return 1;
252b5132
RH		 1691}
1692
1693/* This is the guts of the machine-dependent assembler. LINE points to a
1694 machine dependent instruction. This function is supposed to emit
1695 the frags/bytes it assembles to. */
1696
1697void
1698md_assemble (line)
1699 char *line;
1700{
252b5132 1701 int j;
252b5132
RH		 1702 char mnemonic[MAX_MNEM_SIZE];
1703
47926f60 1704 /* Initialize globals. */
252b5132
RH		 1705 memset (&i, '\0', sizeof (i));
1706 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1707 i.reloc[j] = NO_RELOC;
252b5132
RH		 1708 memset (disp_expressions, '\0', sizeof (disp_expressions));
1709 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1710 save_stack_p = save_stack;
252b5132
RH		 1711
1712 /* First parse an instruction mnemonic & call i386_operand for the operands.
1713 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1714 start of a (possibly prefixed) mnemonic. */
252b5132 1715
29b0f896
AM		 1716 line = parse_insn (line, mnemonic);
1717 if (line == NULL)
1718 return;
252b5132 1719
29b0f896
AM		 1720 line = parse_operands (line, mnemonic);
1721 if (line == NULL)
1722 return;
252b5132 1723
4eed87de 1724 /* The order of the immediates should be reversed
050dfa73 1725 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1726 if ((i.imm_operands == 2)
1727 && ((strcmp (mnemonic, "extrq") == 0)
1728 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1729 {
4eed87de
AM		 1730 swap_2_operands (0, 1);
1731 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1732 have to be reversed even though they have two immediate operands.
1733 */
1734 if (intel_syntax)
1735 swap_operands ();
1736 }
1737
29b0f896
AM		 1738 /* Now we've parsed the mnemonic into a set of templates, and have the
1739 operands at hand. */
1740
1741 /* All intel opcodes have reversed operands except for "bound" and
1742 "enter". We also don't reverse intersegment "jmp" and "call"
1743 instructions with 2 immediate operands so that the immediate segment
050dfa73 1744 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1745 if (intel_syntax
1746 && i.operands > 1
29b0f896 1747 && (strcmp (mnemonic, "bound") != 0)
30123838 1748 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1749 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1750 swap_operands ();
1751
1752 if (i.imm_operands)
1753 optimize_imm ();
1754
b300c311
L		 1755 /* Don't optimize displacement for movabs since it only takes 64bit
1756 displacement. */
1757 if (i.disp_operands
1758 && (flag_code != CODE_64BIT
1759 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1760 optimize_disp ();
1761
1762 /* Next, we find a template that matches the given insn,
1763 making sure the overlap of the given operands types is consistent
1764 with the template operand types. */
252b5132 1765
29b0f896
AM		 1766 if (!match_template ())
1767 return;
252b5132 1768
cd61ebfe
AM		 1769 if (intel_syntax)
1770 {
1771 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1772 if (SYSV386_COMPAT
1773 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1774 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1775
1776 /* Zap movzx and movsx suffix. The suffix may have been set from
1777 "word ptr" or "byte ptr" on the source operand, but we'll use
1778 the suffix later to choose the destination register. */
1779 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1780 {
1781 if (i.reg_operands < 2
1782 && !i.suffix
1783 && (~i.tm.opcode_modifier
1784 & (No_bSuf
1785 | No_wSuf
1786 | No_lSuf
1787 | No_sSuf
1788 | No_xSuf
1789 | No_qSuf)))
1790 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1791
1792 i.suffix = 0;
1793 }
cd61ebfe 1794 }
24eab124 1795
29b0f896
AM		 1796 if (i.tm.opcode_modifier & FWait)
1797 if (!add_prefix (FWAIT_OPCODE))
1798 return;
252b5132 1799
29b0f896
AM		 1800 /* Check string instruction segment overrides. */
1801 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1802 {
1803 if (!check_string ())
5dd0794d 1804 return;
29b0f896 1805 }
5dd0794d 1806
29b0f896
AM		 1807 if (!process_suffix ())
1808 return;
e413e4e9 1809
29b0f896
AM		 1810 /* Make still unresolved immediate matches conform to size of immediate
1811 given in i.suffix. */
1812 if (!finalize_imm ())
1813 return;
252b5132 1814
29b0f896
AM		 1815 if (i.types[0] & Imm1)
1816 i.imm_operands = 0; /* kludge for shift insns. */
1817 if (i.types[0] & ImplicitRegister)
1818 i.reg_operands--;
1819 if (i.types[1] & ImplicitRegister)
1820 i.reg_operands--;
1821 if (i.types[2] & ImplicitRegister)
1822 i.reg_operands--;
252b5132 1823
29b0f896
AM		 1824 if (i.tm.opcode_modifier & ImmExt)
1825 {
02fc3089
L		 1826 expressionS *exp;
1827
b7d9ef37 1828 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1829 {
b7d9ef37 1830 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1831 operands with an opcode suffix which is coded in the same
1832 place as an 8-bit immediate field would be. Here we check
1833 those operands and remove them afterwards. */
1834 unsigned int x;
1835
a4622f40 1836 for (x = 0; x < i.operands; x++)
ca164297 1837 if (i.op[x].regs->reg_num != x)
a540244d
L		 1838 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1839 register_prefix,
1840 i.op[x].regs->reg_name,
1841 x + 1,
1842 i.tm.name);
ca164297
L		 1843 i.operands = 0;
1844 }
1845
29b0f896
AM		 1846 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1847 opcode suffix which is coded in the same place as an 8-bit
1848 immediate field would be. Here we fake an 8-bit immediate
1849 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1850
29b0f896 1851 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1852
29b0f896
AM		 1853 exp = &im_expressions[i.imm_operands++];
1854 i.op[i.operands].imms = exp;
1855 i.types[i.operands++] = Imm8;
1856 exp->X_op = O_constant;
1857 exp->X_add_number = i.tm.extension_opcode;
1858 i.tm.extension_opcode = None;
1859 }
252b5132 1860
29b0f896
AM		 1861 /* For insns with operands there are more diddles to do to the opcode. */
1862 if (i.operands)
1863 {
1864 if (!process_operands ())
1865 return;
1866 }
1867 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1868 {
1869 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1870 as_warn (_("translating to `%sp'"), i.tm.name);
1871 }
252b5132 1872
29b0f896
AM		 1873 /* Handle conversion of 'int $3' --> special int3 insn. */
1874 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1875 {
1876 i.tm.base_opcode = INT3_OPCODE;
1877 i.imm_operands = 0;
1878 }
252b5132 1879
29b0f896
AM		 1880 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1881 && i.op[0].disps->X_op == O_constant)
1882 {
1883 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1884 the absolute address given by the constant. Since ix86 jumps and
1885 calls are pc relative, we need to generate a reloc. */
1886 i.op[0].disps->X_add_symbol = &abs_symbol;
1887 i.op[0].disps->X_op = O_symbol;
1888 }
252b5132 1889
29b0f896 1890 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1891 i.rex |= REX_W;
252b5132 1892
29b0f896
AM		 1893 /* For 8 bit registers we need an empty rex prefix. Also if the
1894 instruction already has a prefix, we need to convert old
1895 registers to new ones. */
773f551c 1896
29b0f896
AM		 1897 if (((i.types[0] & Reg8) != 0
1898 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1899 || ((i.types[1] & Reg8) != 0
1900 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1901 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1902 && i.rex != 0))
1903 {
1904 int x;
726c5dcd 1905
29b0f896
AM		 1906 i.rex |= REX_OPCODE;
1907 for (x = 0; x < 2; x++)
1908 {
1909 /* Look for 8 bit operand that uses old registers. */
1910 if ((i.types[x] & Reg8) != 0
1911 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1912 {
29b0f896
AM		 1913 /* In case it is "hi" register, give up. */
1914 if (i.op[x].regs->reg_num > 3)
a540244d 1915 as_bad (_("can't encode register '%s%s' in an "
4eed87de 1916 "instruction requiring REX prefix."),
a540244d 1917 register_prefix, i.op[x].regs->reg_name);
773f551c 1918
29b0f896
AM		 1919 /* Otherwise it is equivalent to the extended register.
1920 Since the encoding doesn't change this is merely
1921 cosmetic cleanup for debug output. */
1922
1923 i.op[x].regs = i.op[x].regs + 8;
773f551c 1924 }
29b0f896
AM		 1925 }
1926 }
773f551c 1927
29b0f896
AM		 1928 if (i.rex != 0)
1929 add_prefix (REX_OPCODE | i.rex);
1930
1931 /* We are ready to output the insn. */
1932 output_insn ();
1933}
1934
1935static char *
e3bb37b5 1936parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1937{
1938 char *l = line;
1939 char *token_start = l;
1940 char *mnem_p;
5c6af06e
JB		 1941 int supported;
1942 const template *t;
29b0f896
AM		 1943
1944 /* Non-zero if we found a prefix only acceptable with string insns. */
1945 const char *expecting_string_instruction = NULL;
45288df1 1946
29b0f896
AM		 1947 while (1)
1948 {
1949 mnem_p = mnemonic;
1950 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1951 {
1952 mnem_p++;
1953 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1954 {
29b0f896
AM		 1955 as_bad (_("no such instruction: `%s'"), token_start);
1956 return NULL;
1957 }
1958 l++;
1959 }
1960 if (!is_space_char (*l)
1961 && *l != END_OF_INSN
e44823cf
JB		 1962 && (intel_syntax
1963 || (*l != PREFIX_SEPARATOR
1964 && *l != ',')))
29b0f896
AM		 1965 {
1966 as_bad (_("invalid character %s in mnemonic"),
1967 output_invalid (*l));
1968 return NULL;
1969 }
1970 if (token_start == l)
1971 {
e44823cf 1972 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1973 as_bad (_("expecting prefix; got nothing"));
1974 else
1975 as_bad (_("expecting mnemonic; got nothing"));
1976 return NULL;
1977 }
45288df1 1978
29b0f896
AM		 1979 /* Look up instruction (or prefix) via hash table. */
1980 current_templates = hash_find (op_hash, mnemonic);
47926f60 1981
29b0f896
AM		 1982 if (*l != END_OF_INSN
1983 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1984 && current_templates
1985 && (current_templates->start->opcode_modifier & IsPrefix))
1986 {
2dd88dca
JB		 1987 if (current_templates->start->cpu_flags
1988 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1989 {
1990 as_bad ((flag_code != CODE_64BIT
1991 ? _("`%s' is only supported in 64-bit mode")
1992 : _("`%s' is not supported in 64-bit mode")),
1993 current_templates->start->name);
1994 return NULL;
1995 }
29b0f896
AM		 1996 /* If we are in 16-bit mode, do not allow addr16 or data16.
1997 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1998 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1999 && flag_code != CODE_64BIT
2000 && (((current_templates->start->opcode_modifier & Size32) != 0)
2001 ^ (flag_code == CODE_16BIT)))
2002 {
2003 as_bad (_("redundant %s prefix"),
2004 current_templates->start->name);
2005 return NULL;
45288df1 2006 }
29b0f896
AM		 2007 /* Add prefix, checking for repeated prefixes. */
2008 switch (add_prefix (current_templates->start->base_opcode))
2009 {
2010 case 0:
2011 return NULL;
2012 case 2:
2013 expecting_string_instruction = current_templates->start->name;
2014 break;
2015 }
2016 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2017 token_start = ++l;
2018 }
2019 else
2020 break;
2021 }
45288df1 2022
29b0f896
AM		 2023 if (!current_templates)
2024 {
2025 /* See if we can get a match by trimming off a suffix. */
2026 switch (mnem_p[-1])
2027 {
2028 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2029 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2030 i.suffix = SHORT_MNEM_SUFFIX;
2031 else
29b0f896
AM		 2032 case BYTE_MNEM_SUFFIX:
2033 case QWORD_MNEM_SUFFIX:
2034 i.suffix = mnem_p[-1];
2035 mnem_p[-1] = '\0';
2036 current_templates = hash_find (op_hash, mnemonic);
2037 break;
2038 case SHORT_MNEM_SUFFIX:
2039 case LONG_MNEM_SUFFIX:
2040 if (!intel_syntax)
2041 {
2042 i.suffix = mnem_p[-1];
2043 mnem_p[-1] = '\0';
2044 current_templates = hash_find (op_hash, mnemonic);
2045 }
2046 break;
252b5132 2047
29b0f896
AM		 2048 /* Intel Syntax. */
2049 case 'd':
2050 if (intel_syntax)
2051 {
9306ca4a 2052 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2053 i.suffix = SHORT_MNEM_SUFFIX;
2054 else
2055 i.suffix = LONG_MNEM_SUFFIX;
2056 mnem_p[-1] = '\0';
2057 current_templates = hash_find (op_hash, mnemonic);
2058 }
2059 break;
2060 }
2061 if (!current_templates)
2062 {
2063 as_bad (_("no such instruction: `%s'"), token_start);
2064 return NULL;
2065 }
2066 }
252b5132 2067
29b0f896
AM		 2068 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2069 {
2070 /* Check for a branch hint. We allow ",pt" and ",pn" for
2071 predict taken and predict not taken respectively.
2072 I'm not sure that branch hints actually do anything on loop
2073 and jcxz insns (JumpByte) for current Pentium4 chips. They
2074 may work in the future and it doesn't hurt to accept them
2075 now. */
2076 if (l[0] == ',' && l[1] == 'p')
2077 {
2078 if (l[2] == 't')
2079 {
2080 if (!add_prefix (DS_PREFIX_OPCODE))
2081 return NULL;
2082 l += 3;
2083 }
2084 else if (l[2] == 'n')
2085 {
2086 if (!add_prefix (CS_PREFIX_OPCODE))
2087 return NULL;
2088 l += 3;
2089 }
2090 }
2091 }
2092 /* Any other comma loses. */
2093 if (*l == ',')
2094 {
2095 as_bad (_("invalid character %s in mnemonic"),
2096 output_invalid (*l));
2097 return NULL;
2098 }
252b5132 2099
29b0f896 2100 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2101 supported = 0;
2102 for (t = current_templates->start; t < current_templates->end; ++t)
2103 {
2104 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2105 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2106 supported |= 1;
5c6af06e 2107 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2108 supported |= 2;
5c6af06e
JB		 2109 }
2110 if (!(supported & 2))
2111 {
2112 as_bad (flag_code == CODE_64BIT
2113 ? _("`%s' is not supported in 64-bit mode")
2114 : _("`%s' is only supported in 64-bit mode"),
2115 current_templates->start->name);
2116 return NULL;
2117 }
2118 if (!(supported & 1))
29b0f896 2119 {
5c6af06e
JB		 2120 as_warn (_("`%s' is not supported on `%s%s'"),
2121 current_templates->start->name,
2122 cpu_arch_name,
2123 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2124 }
2125 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2126 {
2127 as_warn (_("use .code16 to ensure correct addressing mode"));
2128 }
252b5132 2129
29b0f896 2130 /* Check for rep/repne without a string instruction. */
f41bbced 2131 if (expecting_string_instruction)
29b0f896 2132 {
f41bbced
JB		 2133 static templates override;
2134
2135 for (t = current_templates->start; t < current_templates->end; ++t)
2136 if (t->opcode_modifier & IsString)
2137 break;
2138 if (t >= current_templates->end)
2139 {
2140 as_bad (_("expecting string instruction after `%s'"),
64e74474 2141 expecting_string_instruction);
f41bbced
JB		 2142 return NULL;
2143 }
2144 for (override.start = t; t < current_templates->end; ++t)
2145 if (!(t->opcode_modifier & IsString))
2146 break;
2147 override.end = t;
2148 current_templates = &override;
29b0f896 2149 }
252b5132 2150
29b0f896
AM		 2151 return l;
2152}
252b5132 2153
29b0f896 2154static char *
e3bb37b5 2155parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2156{
2157 char *token_start;
3138f287 2158
29b0f896
AM		 2159 /* 1 if operand is pending after ','. */
2160 unsigned int expecting_operand = 0;
252b5132 2161
29b0f896
AM		 2162 /* Non-zero if operand parens not balanced. */
2163 unsigned int paren_not_balanced;
2164
2165 while (*l != END_OF_INSN)
2166 {
2167 /* Skip optional white space before operand. */
2168 if (is_space_char (*l))
2169 ++l;
2170 if (!is_operand_char (*l) && *l != END_OF_INSN)
2171 {
2172 as_bad (_("invalid character %s before operand %d"),
2173 output_invalid (*l),
2174 i.operands + 1);
2175 return NULL;
2176 }
2177 token_start = l; /* after white space */
2178 paren_not_balanced = 0;
2179 while (paren_not_balanced || *l != ',')
2180 {
2181 if (*l == END_OF_INSN)
2182 {
2183 if (paren_not_balanced)
2184 {
2185 if (!intel_syntax)
2186 as_bad (_("unbalanced parenthesis in operand %d."),
2187 i.operands + 1);
2188 else
2189 as_bad (_("unbalanced brackets in operand %d."),
2190 i.operands + 1);
2191 return NULL;
2192 }
2193 else
2194 break; /* we are done */
2195 }
2196 else if (!is_operand_char (*l) && !is_space_char (*l))
2197 {
2198 as_bad (_("invalid character %s in operand %d"),
2199 output_invalid (*l),
2200 i.operands + 1);
2201 return NULL;
2202 }
2203 if (!intel_syntax)
2204 {
2205 if (*l == '(')
2206 ++paren_not_balanced;
2207 if (*l == ')')
2208 --paren_not_balanced;
2209 }
2210 else
2211 {
2212 if (*l == '[')
2213 ++paren_not_balanced;
2214 if (*l == ']')
2215 --paren_not_balanced;
2216 }
2217 l++;
2218 }
2219 if (l != token_start)
2220 { /* Yes, we've read in another operand. */
2221 unsigned int operand_ok;
2222 this_operand = i.operands++;
2223 if (i.operands > MAX_OPERANDS)
2224 {
2225 as_bad (_("spurious operands; (%d operands/instruction max)"),
2226 MAX_OPERANDS);
2227 return NULL;
2228 }
2229 /* Now parse operand adding info to 'i' as we go along. */
2230 END_STRING_AND_SAVE (l);
2231
2232 if (intel_syntax)
2233 operand_ok =
2234 i386_intel_operand (token_start,
2235 intel_float_operand (mnemonic));
2236 else
2237 operand_ok = i386_operand (token_start);
2238
2239 RESTORE_END_STRING (l);
2240 if (!operand_ok)
2241 return NULL;
2242 }
2243 else
2244 {
2245 if (expecting_operand)
2246 {
2247 expecting_operand_after_comma:
2248 as_bad (_("expecting operand after ','; got nothing"));
2249 return NULL;
2250 }
2251 if (*l == ',')
2252 {
2253 as_bad (_("expecting operand before ','; got nothing"));
2254 return NULL;
2255 }
2256 }
7f3f1ea2 2257
29b0f896
AM		 2258 /* Now *l must be either ',' or END_OF_INSN. */
2259 if (*l == ',')
2260 {
2261 if (*++l == END_OF_INSN)
2262 {
2263 /* Just skip it, if it's \n complain. */
2264 goto expecting_operand_after_comma;
2265 }
2266 expecting_operand = 1;
2267 }
2268 }
2269 return l;
2270}
7f3f1ea2 2271
050dfa73 2272static void
4d456e3d 2273swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2274{
2275 union i386_op temp_op;
2276 unsigned int temp_type;
2277 enum bfd_reloc_code_real temp_reloc;
4eed87de 2278
050dfa73
MM		 2279 temp_type = i.types[xchg2];
2280 i.types[xchg2] = i.types[xchg1];
2281 i.types[xchg1] = temp_type;
2282 temp_op = i.op[xchg2];
2283 i.op[xchg2] = i.op[xchg1];
2284 i.op[xchg1] = temp_op;
2285 temp_reloc = i.reloc[xchg2];
2286 i.reloc[xchg2] = i.reloc[xchg1];
2287 i.reloc[xchg1] = temp_reloc;
2288}
2289
29b0f896 2290static void
e3bb37b5 2291swap_operands (void)
29b0f896 2292{
b7c61d9a 2293 switch (i.operands)
050dfa73 2294 {
b7c61d9a 2295 case 4:
4d456e3d 2296 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2297 case 3:
2298 case 2:
4d456e3d 2299 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2300 break;
2301 default:
2302 abort ();
29b0f896 2303 }
29b0f896
AM		 2304
2305 if (i.mem_operands == 2)
2306 {
2307 const seg_entry *temp_seg;
2308 temp_seg = i.seg[0];
2309 i.seg[0] = i.seg[1];
2310 i.seg[1] = temp_seg;
2311 }
2312}
252b5132 2313
29b0f896
AM		 2314/* Try to ensure constant immediates are represented in the smallest
2315 opcode possible. */
2316static void
e3bb37b5 2317optimize_imm (void)
29b0f896
AM		 2318{
2319 char guess_suffix = 0;
2320 int op;
252b5132 2321
29b0f896
AM		 2322 if (i.suffix)
2323 guess_suffix = i.suffix;
2324 else if (i.reg_operands)
2325 {
2326 /* Figure out a suffix from the last register operand specified.
2327 We can't do this properly yet, ie. excluding InOutPortReg,
2328 but the following works for instructions with immediates.
2329 In any case, we can't set i.suffix yet. */
2330 for (op = i.operands; --op >= 0;)
2331 if (i.types[op] & Reg)
252b5132 2332 {
29b0f896
AM		 2333 if (i.types[op] & Reg8)
2334 guess_suffix = BYTE_MNEM_SUFFIX;
2335 else if (i.types[op] & Reg16)
2336 guess_suffix = WORD_MNEM_SUFFIX;
2337 else if (i.types[op] & Reg32)
2338 guess_suffix = LONG_MNEM_SUFFIX;
2339 else if (i.types[op] & Reg64)
2340 guess_suffix = QWORD_MNEM_SUFFIX;
2341 break;
252b5132 2342 }
29b0f896
AM		 2343 }
2344 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2345 guess_suffix = WORD_MNEM_SUFFIX;
2346
2347 for (op = i.operands; --op >= 0;)
2348 if (i.types[op] & Imm)
2349 {
2350 switch (i.op[op].imms->X_op)
252b5132 2351 {
29b0f896
AM		 2352 case O_constant:
2353 /* If a suffix is given, this operand may be shortened. */
2354 switch (guess_suffix)
252b5132 2355 {
29b0f896
AM		 2356 case LONG_MNEM_SUFFIX:
2357 i.types[op] |= Imm32 | Imm64;
2358 break;
2359 case WORD_MNEM_SUFFIX:
2360 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2361 break;
2362 case BYTE_MNEM_SUFFIX:
2363 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2364 break;
252b5132 2365 }
252b5132 2366
29b0f896
AM		 2367 /* If this operand is at most 16 bits, convert it
2368 to a signed 16 bit number before trying to see
2369 whether it will fit in an even smaller size.
2370 This allows a 16-bit operand such as $0xffe0 to
2371 be recognised as within Imm8S range. */
2372 if ((i.types[op] & Imm16)
2373 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2374 {
29b0f896
AM		 2375 i.op[op].imms->X_add_number =
2376 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2377 }
2378 if ((i.types[op] & Imm32)
2379 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2380 == 0))
2381 {
2382 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2383 ^ ((offsetT) 1 << 31))
2384 - ((offsetT) 1 << 31));
2385 }
2386 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2387
29b0f896
AM		 2388 /* We must avoid matching of Imm32 templates when 64bit
2389 only immediate is available. */
2390 if (guess_suffix == QWORD_MNEM_SUFFIX)
2391 i.types[op] &= ~Imm32;
2392 break;
252b5132 2393
29b0f896
AM		 2394 case O_absent:
2395 case O_register:
2396 abort ();
2397
2398 /* Symbols and expressions. */
2399 default:
9cd96992
JB		 2400 /* Convert symbolic operand to proper sizes for matching, but don't
2401 prevent matching a set of insns that only supports sizes other
2402 than those matching the insn suffix. */
2403 {
2404 unsigned int mask, allowed = 0;
2405 const template *t;
2406
4eed87de
AM		 2407 for (t = current_templates->start;
2408 t < current_templates->end;
2409 ++t)
2410 allowed |= t->operand_types[op];
9cd96992
JB		 2411 switch (guess_suffix)
2412 {
2413 case QWORD_MNEM_SUFFIX:
2414 mask = Imm64 | Imm32S;
2415 break;
2416 case LONG_MNEM_SUFFIX:
2417 mask = Imm32;
2418 break;
2419 case WORD_MNEM_SUFFIX:
2420 mask = Imm16;
2421 break;
2422 case BYTE_MNEM_SUFFIX:
2423 mask = Imm8;
2424 break;
2425 default:
2426 mask = 0;
2427 break;
2428 }
64e74474
AM		 2429 if (mask & allowed)
2430 i.types[op] &= mask;
9cd96992 2431 }
29b0f896 2432 break;
252b5132 2433 }
29b0f896
AM		 2434 }
2435}
47926f60 2436
29b0f896
AM		 2437/* Try to use the smallest displacement type too. */
2438static void
e3bb37b5 2439optimize_disp (void)
29b0f896
AM		 2440{
2441 int op;
3e73aa7c 2442
29b0f896 2443 for (op = i.operands; --op >= 0;)
b300c311 2444 if (i.types[op] & Disp)
252b5132 2445 {
b300c311 2446 if (i.op[op].disps->X_op == O_constant)
252b5132 2447 {
b300c311 2448 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2449
b300c311
L		 2450 if ((i.types[op] & Disp16)
2451 && (disp & ~(offsetT) 0xffff) == 0)
2452 {
2453 /* If this operand is at most 16 bits, convert
2454 to a signed 16 bit number and don't use 64bit
2455 displacement. */
2456 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2457 i.types[op] &= ~Disp64;
2458 }
2459 if ((i.types[op] & Disp32)
2460 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2461 {
2462 /* If this operand is at most 32 bits, convert
2463 to a signed 32 bit number and don't use 64bit
2464 displacement. */
2465 disp &= (((offsetT) 2 << 31) - 1);
2466 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2467 i.types[op] &= ~Disp64;
2468 }
2469 if (!disp && (i.types[op] & BaseIndex))
2470 {
2471 i.types[op] &= ~Disp;
2472 i.op[op].disps = 0;
2473 i.disp_operands--;
2474 }
2475 else if (flag_code == CODE_64BIT)
2476 {
2477 if (fits_in_signed_long (disp))
28a9d8f5
L		 2478 {
2479 i.types[op] &= ~Disp64;
2480 i.types[op] |= Disp32S;
2481 }
b300c311
L		 2482 if (fits_in_unsigned_long (disp))
2483 i.types[op] |= Disp32;
2484 }
2485 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2486 && fits_in_signed_byte (disp))
2487 i.types[op] |= Disp8;
252b5132 2488 }
67a4f2b7
AO		 2489 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2490 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2491 {
2492 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2493 i.op[op].disps, 0, i.reloc[op]);
2494 i.types[op] &= ~Disp;
2495 }
2496 else
b300c311
L		 2497 /* We only support 64bit displacement on constants. */
2498 i.types[op] &= ~Disp64;
252b5132 2499 }
29b0f896
AM		 2500}
2501
2502static int
e3bb37b5 2503match_template (void)
29b0f896
AM		 2504{
2505 /* Points to template once we've found it. */
2506 const template *t;
f48ff2ae 2507 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2508 unsigned int found_reverse_match;
2509 int suffix_check;
f48ff2ae 2510 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2511 int addr_prefix_disp;
a5c311ca 2512 unsigned int j;
29b0f896 2513
f48ff2ae
L		 2514#if MAX_OPERANDS != 4
2515# error "MAX_OPERANDS must be 4."
2516#endif
2517
29b0f896
AM		 2518#define MATCH(overlap, given, template) \
2519 ((overlap & ~JumpAbsolute) \
2520 && (((given) & (BaseIndex | JumpAbsolute)) \
2521 == ((overlap) & (BaseIndex | JumpAbsolute))))
2522
2523 /* If given types r0 and r1 are registers they must be of the same type
2524 unless the expected operand type register overlap is null.
2525 Note that Acc in a template matches every size of reg. */
2526#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2527 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2528 || ((g0) & Reg) == ((g1) & Reg) \
2529 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2530
2531 overlap0 = 0;
2532 overlap1 = 0;
2533 overlap2 = 0;
f48ff2ae 2534 overlap3 = 0;
29b0f896 2535 found_reverse_match = 0;
a5c311ca
L		 2536 for (j = 0; j < MAX_OPERANDS; j++)
2537 operand_types [j] = 0;
539e75ad 2538 addr_prefix_disp = -1;
29b0f896
AM		 2539 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2540 ? No_bSuf
2541 : (i.suffix == WORD_MNEM_SUFFIX
2542 ? No_wSuf
2543 : (i.suffix == SHORT_MNEM_SUFFIX
2544 ? No_sSuf
2545 : (i.suffix == LONG_MNEM_SUFFIX
2546 ? No_lSuf
2547 : (i.suffix == QWORD_MNEM_SUFFIX
2548 ? No_qSuf
2549 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2550 ? No_xSuf : 0))))));
2551
45aa61fe 2552 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2553 {
539e75ad
L		 2554 addr_prefix_disp = -1;
2555
29b0f896
AM		 2556 /* Must have right number of operands. */
2557 if (i.operands != t->operands)
2558 continue;
2559
20592a94 2560 /* Check the suffix, except for some instructions in intel mode. */
29b0f896
AM		 2561 if ((t->opcode_modifier & suffix_check)
2562 && !(intel_syntax
9306ca4a 2563 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2564 continue;
2565
a5c311ca
L		 2566 for (j = 0; j < MAX_OPERANDS; j++)
2567 operand_types [j] = t->operand_types [j];
539e75ad 2568
45aa61fe
AM		 2569 /* In general, don't allow 64-bit operands in 32-bit mode. */
2570 if (i.suffix == QWORD_MNEM_SUFFIX
2571 && flag_code != CODE_64BIT
2572 && (intel_syntax
2573 ? (!(t->opcode_modifier & IgnoreSize)
2574 && !intel_float_operand (t->name))
2575 : intel_float_operand (t->name) != 2)
539e75ad
L		 2576 && (!(operand_types[0] & (RegMMX | RegXMM))
2577 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2578 && (t->base_opcode != 0x0fc7
2579 || t->extension_opcode != 1 /* cmpxchg8b */))
2580 continue;
2581
29b0f896
AM		 2582 /* Do not verify operands when there are none. */
2583 else if (!t->operands)
2584 {
2585 if (t->cpu_flags & ~cpu_arch_flags)
2586 continue;
2587 /* We've found a match; break out of loop. */
2588 break;
2589 }
252b5132 2590
539e75ad
L		 2591 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2592 into Disp32/Disp16/Disp32 operand. */
2593 if (i.prefix[ADDR_PREFIX] != 0)
2594 {
a5c311ca 2595 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2596
2597 switch (flag_code)
2598 {
2599 case CODE_16BIT:
2600 DispOn = Disp32;
2601 DispOff = Disp16;
2602 break;
2603 case CODE_32BIT:
2604 DispOn = Disp16;
2605 DispOff = Disp32;
2606 break;
2607 case CODE_64BIT:
2608 DispOn = Disp32;
2609 DispOff = Disp64;
2610 break;
2611 }
2612
f48ff2ae 2613 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2614 {
2615 /* There should be only one Disp operand. */
2616 if ((operand_types[j] & DispOff))
2617 {
2618 addr_prefix_disp = j;
2619 operand_types[j] |= DispOn;
2620 operand_types[j] &= ~DispOff;
2621 break;
2622 }
2623 }
2624 }
2625
2626 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2627 switch (t->operands)
2628 {
2629 case 1:
539e75ad 2630 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2631 continue;
2632 break;
2633 case 2:
8b38ad71
L		 2634 /* xchg %eax, %eax is a special case. It is an aliase for nop
2635 only in 32bit mode and we can use opcode 0x90. In 64bit
2636 mode, we can't use 0x90 for xchg %eax, %eax since it should
2637 zero-extend %eax to %rax. */
2638 if (flag_code == CODE_64BIT
2639 && t->base_opcode == 0x90
2640 && i.types [0] == (Acc | Reg32)
2641 && i.types [1] == (Acc | Reg32))
2642 continue;
29b0f896 2643 case 3:
f48ff2ae 2644 case 4:
539e75ad
L		 2645 overlap1 = i.types[1] & operand_types[1];
2646 if (!MATCH (overlap0, i.types[0], operand_types[0])
2647 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2648 /* monitor in SSE3 is a very special case. The first
708587a4 2649 register and the second register may have different
381d071f 2650 sizes. The same applies to crc32 in SSE4.2. */
cb712a9e
L		 2651 || !((t->base_opcode == 0x0f01
2652 && t->extension_opcode == 0xc8)
381d071f 2653 || t->base_opcode == 0xf20f38f1
cb712a9e 2654 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2655 operand_types[0],
cb712a9e 2656 overlap1, i.types[1],
539e75ad 2657 operand_types[1])))
29b0f896
AM		 2658 {
2659 /* Check if other direction is valid ... */
2660 if ((t->opcode_modifier & (D | FloatD)) == 0)
2661 continue;
2662
2663 /* Try reversing direction of operands. */
539e75ad
L		 2664 overlap0 = i.types[0] & operand_types[1];
2665 overlap1 = i.types[1] & operand_types[0];
2666 if (!MATCH (overlap0, i.types[0], operand_types[1])
2667 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2668 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2669 operand_types[1],
29b0f896 2670 overlap1, i.types[1],
539e75ad 2671 operand_types[0]))
29b0f896
AM		 2672 {
2673 /* Does not match either direction. */
2674 continue;
2675 }
2676 /* found_reverse_match holds which of D or FloatDR
2677 we've found. */
8a2ed489
L		 2678 if ((t->opcode_modifier & D))
2679 found_reverse_match = Opcode_D;
2680 else if ((t->opcode_modifier & FloatD))
2681 found_reverse_match = Opcode_FloatD;
2682 else
2683 found_reverse_match = 0;
2684 if ((t->opcode_modifier & FloatR))
2685 found_reverse_match |= Opcode_FloatR;
29b0f896 2686 }
f48ff2ae 2687 else
29b0f896 2688 {
f48ff2ae 2689 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2690 switch (t->operands)
2691 {
2692 case 4:
2693 overlap3 = i.types[3] & operand_types[3];
2694 case 3:
2695 overlap2 = i.types[2] & operand_types[2];
2696 break;
2697 }
29b0f896 2698
f48ff2ae
L		 2699 switch (t->operands)
2700 {
2701 case 4:
2702 if (!MATCH (overlap3, i.types[3], operand_types[3])
2703 || !CONSISTENT_REGISTER_MATCH (overlap2,
2704 i.types[2],
2705 operand_types[2],
2706 overlap3,
2707 i.types[3],
2708 operand_types[3]))
2709 continue;
2710 case 3:
2711 /* Here we make use of the fact that there are no
2712 reverse match 3 operand instructions, and all 3
2713 operand instructions only need to be checked for
2714 register consistency between operands 2 and 3. */
2715 if (!MATCH (overlap2, i.types[2], operand_types[2])
2716 || !CONSISTENT_REGISTER_MATCH (overlap1,
2717 i.types[1],
2718 operand_types[1],
2719 overlap2,
2720 i.types[2],
2721 operand_types[2]))
2722 continue;
2723 break;
2724 }
29b0f896 2725 }
f48ff2ae 2726 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2727 slip through to break. */
2728 }
2729 if (t->cpu_flags & ~cpu_arch_flags)
2730 {
2731 found_reverse_match = 0;
2732 continue;
2733 }
2734 /* We've found a match; break out of loop. */
2735 break;
2736 }
2737
2738 if (t == current_templates->end)
2739 {
2740 /* We found no match. */
2741 as_bad (_("suffix or operands invalid for `%s'"),
2742 current_templates->start->name);
2743 return 0;
2744 }
252b5132 2745
29b0f896
AM		 2746 if (!quiet_warnings)
2747 {
2748 if (!intel_syntax
2749 && ((i.types[0] & JumpAbsolute)
539e75ad 2750 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2751 {
2752 as_warn (_("indirect %s without `*'"), t->name);
2753 }
2754
2755 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2756 == (IsPrefix | IgnoreSize))
2757 {
2758 /* Warn them that a data or address size prefix doesn't
2759 affect assembly of the next line of code. */
2760 as_warn (_("stand-alone `%s' prefix"), t->name);
2761 }
2762 }
2763
2764 /* Copy the template we found. */
2765 i.tm = *t;
539e75ad
L		 2766
2767 if (addr_prefix_disp != -1)
2768 i.tm.operand_types[addr_prefix_disp]
2769 = operand_types[addr_prefix_disp];
2770
29b0f896
AM		 2771 if (found_reverse_match)
2772 {
2773 /* If we found a reverse match we must alter the opcode
2774 direction bit. found_reverse_match holds bits to change
2775 (different for int & float insns). */
2776
2777 i.tm.base_opcode ^= found_reverse_match;
2778
539e75ad
L		 2779 i.tm.operand_types[0] = operand_types[1];
2780 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2781 }
2782
2783 return 1;
2784}
2785
2786static int
e3bb37b5 2787check_string (void)
29b0f896
AM		 2788{
2789 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2790 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2791 {
2792 if (i.seg[0] != NULL && i.seg[0] != &es)
2793 {
2794 as_bad (_("`%s' operand %d must use `%%es' segment"),
2795 i.tm.name,
2796 mem_op + 1);
2797 return 0;
2798 }
2799 /* There's only ever one segment override allowed per instruction.
2800 This instruction possibly has a legal segment override on the
2801 second operand, so copy the segment to where non-string
2802 instructions store it, allowing common code. */
2803 i.seg[0] = i.seg[1];
2804 }
2805 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2806 {
2807 if (i.seg[1] != NULL && i.seg[1] != &es)
2808 {
2809 as_bad (_("`%s' operand %d must use `%%es' segment"),
2810 i.tm.name,
2811 mem_op + 2);
2812 return 0;
2813 }
2814 }
2815 return 1;
2816}
2817
2818static int
543613e9 2819process_suffix (void)
29b0f896
AM		 2820{
2821 /* If matched instruction specifies an explicit instruction mnemonic
2822 suffix, use it. */
2823 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2824 {
2825 if (i.tm.opcode_modifier & Size16)
2826 i.suffix = WORD_MNEM_SUFFIX;
2827 else if (i.tm.opcode_modifier & Size64)
2828 i.suffix = QWORD_MNEM_SUFFIX;
2829 else
2830 i.suffix = LONG_MNEM_SUFFIX;
2831 }
2832 else if (i.reg_operands)
2833 {
2834 /* If there's no instruction mnemonic suffix we try to invent one
2835 based on register operands. */
2836 if (!i.suffix)
2837 {
2838 /* We take i.suffix from the last register operand specified,
2839 Destination register type is more significant than source
381d071f
L		 2840 register type. crc32 in SSE4.2 prefers source register
2841 type. */
2842 if (i.tm.base_opcode == 0xf20f38f1)
2843 {
2844 if ((i.types[0] & Reg))
2845 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
29b0f896 2846 LONG_MNEM_SUFFIX);
381d071f 2847 }
9344ff29 2848 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94
L		 2849 {
2850 if ((i.types[0] & Reg8))
2851 i.suffix = BYTE_MNEM_SUFFIX;
2852 }
381d071f
L		 2853
2854 if (!i.suffix)
2855 {
2856 int op;
2857
20592a94
L		 2858 if (i.tm.base_opcode == 0xf20f38f1
2859 || i.tm.base_opcode == 0xf20f38f0)
2860 {
2861 /* We have to know the operand size for crc32. */
2862 as_bad (_("ambiguous memory operand size for `%s`"),
2863 i.tm.name);
2864 return 0;
2865 }
2866
381d071f
L		 2867 for (op = i.operands; --op >= 0;)
2868 if ((i.types[op] & Reg)
2869 && !(i.tm.operand_types[op] & InOutPortReg))
2870 {
2871 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2872 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2873 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2874 LONG_MNEM_SUFFIX);
2875 break;
2876 }
2877 }
29b0f896
AM		 2878 }
2879 else if (i.suffix == BYTE_MNEM_SUFFIX)
2880 {
2881 if (!check_byte_reg ())
2882 return 0;
2883 }
2884 else if (i.suffix == LONG_MNEM_SUFFIX)
2885 {
2886 if (!check_long_reg ())
2887 return 0;
2888 }
2889 else if (i.suffix == QWORD_MNEM_SUFFIX)
2890 {
2891 if (!check_qword_reg ())
2892 return 0;
2893 }
2894 else if (i.suffix == WORD_MNEM_SUFFIX)
2895 {
2896 if (!check_word_reg ())
2897 return 0;
2898 }
2899 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2900 /* Do nothing if the instruction is going to ignore the prefix. */
2901 ;
2902 else
2903 abort ();
2904 }
9306ca4a
JB		 2905 else if ((i.tm.opcode_modifier & DefaultSize)
2906 && !i.suffix
2907 /* exclude fldenv/frstor/fsave/fstenv */
2908 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2909 {
2910 i.suffix = stackop_size;
2911 }
9306ca4a
JB		 2912 else if (intel_syntax
2913 && !i.suffix
2914 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2915 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2916 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2917 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2918 {
2919 switch (flag_code)
2920 {
2921 case CODE_64BIT:
2922 if (!(i.tm.opcode_modifier & No_qSuf))
2923 {
2924 i.suffix = QWORD_MNEM_SUFFIX;
2925 break;
2926 }
2927 case CODE_32BIT:
2928 if (!(i.tm.opcode_modifier & No_lSuf))
2929 i.suffix = LONG_MNEM_SUFFIX;
2930 break;
2931 case CODE_16BIT:
2932 if (!(i.tm.opcode_modifier & No_wSuf))
2933 i.suffix = WORD_MNEM_SUFFIX;
2934 break;
2935 }
2936 }
252b5132 2937
9306ca4a 2938 if (!i.suffix)
29b0f896 2939 {
9306ca4a
JB		 2940 if (!intel_syntax)
2941 {
2942 if (i.tm.opcode_modifier & W)
2943 {
4eed87de
AM		 2944 as_bad (_("no instruction mnemonic suffix given and "
2945 "no register operands; can't size instruction"));
9306ca4a
JB		 2946 return 0;
2947 }
2948 }
2949 else
2950 {
64e74474
AM		 2951 unsigned int suffixes = (~i.tm.opcode_modifier
2952 & (No_bSuf
2953 | No_wSuf
2954 | No_lSuf
2955 | No_sSuf
2956 | No_xSuf
2957 | No_qSuf));
9306ca4a
JB		 2958
2959 if ((i.tm.opcode_modifier & W)
2960 || ((suffixes & (suffixes - 1))
2961 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2962 {
2963 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2964 return 0;
2965 }
2966 }
29b0f896 2967 }
252b5132 2968
9306ca4a
JB		 2969 /* Change the opcode based on the operand size given by i.suffix;
2970 We don't need to change things for byte insns. */
2971
29b0f896
AM		 2972 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2973 {
2974 /* It's not a byte, select word/dword operation. */
2975 if (i.tm.opcode_modifier & W)
2976 {
2977 if (i.tm.opcode_modifier & ShortForm)
2978 i.tm.base_opcode |= 8;
2979 else
2980 i.tm.base_opcode |= 1;
2981 }
0f3f3d8b 2982
29b0f896
AM		 2983 /* Now select between word & dword operations via the operand
2984 size prefix, except for instructions that will ignore this
2985 prefix anyway. */
cb712a9e
L		 2986 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2987 {
2988 /* monitor in SSE3 is a very special case. The default size
2989 of AX is the size of mode. The address size override
2990 prefix will change the size of AX. */
2991 if (i.op->regs[0].reg_type &
2992 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2993 if (!add_prefix (ADDR_PREFIX_OPCODE))
2994 return 0;
2995 }
2996 else if (i.suffix != QWORD_MNEM_SUFFIX
2997 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2998 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2999 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3000 || (flag_code == CODE_64BIT
3001 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3002 {
3003 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3004
29b0f896
AM		 3005 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3006 prefix = ADDR_PREFIX_OPCODE;
252b5132 3007
29b0f896
AM		 3008 if (!add_prefix (prefix))
3009 return 0;
24eab124 3010 }
252b5132 3011
29b0f896
AM		 3012 /* Set mode64 for an operand. */
3013 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3014 && flag_code == CODE_64BIT
29b0f896 3015 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3016 {
3017 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3018 need rex64. */
3019 if (i.operands != 2
3020 || i.types [0] != (Acc | Reg64)
3021 || i.types [1] != (Acc | Reg64)
13a1e313 3022 || i.tm.base_opcode != 0x90)
f6bee062 3023 i.rex |= REX_W;
46e883c5 3024 }
3e73aa7c 3025
29b0f896
AM		 3026 /* Size floating point instruction. */
3027 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3028 if (i.tm.opcode_modifier & FloatMF)
3029 i.tm.base_opcode ^= 4;
29b0f896 3030 }
7ecd2f8b 3031
29b0f896
AM		 3032 return 1;
3033}
3e73aa7c 3034
29b0f896 3035static int
543613e9 3036check_byte_reg (void)
29b0f896
AM		 3037{
3038 int op;
543613e9 3039
29b0f896
AM		 3040 for (op = i.operands; --op >= 0;)
3041 {
3042 /* If this is an eight bit register, it's OK. If it's the 16 or
3043 32 bit version of an eight bit register, we will just use the
3044 low portion, and that's OK too. */
3045 if (i.types[op] & Reg8)
3046 continue;
3047
3048 /* movzx and movsx should not generate this warning. */
3049 if (intel_syntax
3050 && (i.tm.base_opcode == 0xfb7
3051 || i.tm.base_opcode == 0xfb6
3052 || i.tm.base_opcode == 0x63
3053 || i.tm.base_opcode == 0xfbe
3054 || i.tm.base_opcode == 0xfbf))
3055 continue;
3056
9344ff29
L		 3057 /* crc32 doesn't generate this warning. */
3058 if (i.tm.base_opcode == 0xf20f38f0)
3059 continue;
3060
65ec77d2 3061 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3062 {
3063 /* Prohibit these changes in the 64bit mode, since the
3064 lowering is more complicated. */
3065 if (flag_code == CODE_64BIT
3066 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3067 {
2ca3ace5
L		 3068 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3069 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3070 i.suffix);
3071 return 0;
3072 }
3073#if REGISTER_WARNINGS
3074 if (!quiet_warnings
3075 && (i.tm.operand_types[op] & InOutPortReg) == 0)
a540244d
L		 3076 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3077 register_prefix,
29b0f896
AM		 3078 (i.op[op].regs + (i.types[op] & Reg16
3079 ? REGNAM_AL - REGNAM_AX
3080 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3081 register_prefix,
29b0f896
AM		 3082 i.op[op].regs->reg_name,
3083 i.suffix);
3084#endif
3085 continue;
3086 }
3087 /* Any other register is bad. */
3088 if (i.types[op] & (Reg | RegMMX | RegXMM
3089 | SReg2 | SReg3
3090 | Control | Debug | Test
3091 | FloatReg | FloatAcc))
3092 {
a540244d
L		 3093 as_bad (_("`%s%s' not allowed with `%s%c'"),
3094 register_prefix,
29b0f896
AM		 3095 i.op[op].regs->reg_name,
3096 i.tm.name,
3097 i.suffix);
3098 return 0;
3099 }
3100 }
3101 return 1;
3102}
3103
3104static int
e3bb37b5 3105check_long_reg (void)
29b0f896
AM		 3106{
3107 int op;
3108
3109 for (op = i.operands; --op >= 0;)
3110 /* Reject eight bit registers, except where the template requires
3111 them. (eg. movzb) */
3112 if ((i.types[op] & Reg8) != 0
3113 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3114 {
a540244d
L		 3115 as_bad (_("`%s%s' not allowed with `%s%c'"),
3116 register_prefix,
29b0f896
AM		 3117 i.op[op].regs->reg_name,
3118 i.tm.name,
3119 i.suffix);
3120 return 0;
3121 }
3122 /* Warn if the e prefix on a general reg is missing. */
3123 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3124 && (i.types[op] & Reg16) != 0
3125 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3126 {
3127 /* Prohibit these changes in the 64bit mode, since the
3128 lowering is more complicated. */
3129 if (flag_code == CODE_64BIT)
252b5132 3130 {
2ca3ace5
L		 3131 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3132 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3133 i.suffix);
3134 return 0;
252b5132 3135 }
29b0f896
AM		 3136#if REGISTER_WARNINGS
3137 else
a540244d
L		 3138 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3139 register_prefix,
29b0f896 3140 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3141 register_prefix,
29b0f896
AM		 3142 i.op[op].regs->reg_name,
3143 i.suffix);
3144#endif
252b5132 3145 }
29b0f896
AM		 3146 /* Warn if the r prefix on a general reg is missing. */
3147 else if ((i.types[op] & Reg64) != 0
3148 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3149 {
2ca3ace5
L		 3150 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3151 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3152 i.suffix);
3153 return 0;
3154 }
3155 return 1;
3156}
252b5132 3157
29b0f896 3158static int
e3bb37b5 3159check_qword_reg (void)
29b0f896
AM		 3160{
3161 int op;
252b5132 3162
29b0f896
AM		 3163 for (op = i.operands; --op >= 0; )
3164 /* Reject eight bit registers, except where the template requires
3165 them. (eg. movzb) */
3166 if ((i.types[op] & Reg8) != 0
3167 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3168 {
a540244d
L		 3169 as_bad (_("`%s%s' not allowed with `%s%c'"),
3170 register_prefix,
29b0f896
AM		 3171 i.op[op].regs->reg_name,
3172 i.tm.name,
3173 i.suffix);
3174 return 0;
3175 }
3176 /* Warn if the e prefix on a general reg is missing. */
3177 else if (((i.types[op] & Reg16) != 0
3178 || (i.types[op] & Reg32) != 0)
3179 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3180 {
3181 /* Prohibit these changes in the 64bit mode, since the
3182 lowering is more complicated. */
2ca3ace5
L		 3183 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3184 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3185 i.suffix);
3186 return 0;
252b5132 3187 }
29b0f896
AM		 3188 return 1;
3189}
252b5132 3190
29b0f896 3191static int
e3bb37b5 3192check_word_reg (void)
29b0f896
AM		 3193{
3194 int op;
3195 for (op = i.operands; --op >= 0;)
3196 /* Reject eight bit registers, except where the template requires
3197 them. (eg. movzb) */
3198 if ((i.types[op] & Reg8) != 0
3199 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3200 {
a540244d
L		 3201 as_bad (_("`%s%s' not allowed with `%s%c'"),
3202 register_prefix,
29b0f896
AM		 3203 i.op[op].regs->reg_name,
3204 i.tm.name,
3205 i.suffix);
3206 return 0;
3207 }
3208 /* Warn if the e prefix on a general reg is present. */
3209 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3210 && (i.types[op] & Reg32) != 0
3211 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3212 {
29b0f896
AM		 3213 /* Prohibit these changes in the 64bit mode, since the
3214 lowering is more complicated. */
3215 if (flag_code == CODE_64BIT)
252b5132 3216 {
2ca3ace5
L		 3217 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3218 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3219 i.suffix);
3220 return 0;
252b5132 3221 }
29b0f896
AM		 3222 else
3223#if REGISTER_WARNINGS
a540244d
L		 3224 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3225 register_prefix,
29b0f896 3226 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3227 register_prefix,
29b0f896
AM		 3228 i.op[op].regs->reg_name,
3229 i.suffix);
3230#endif
3231 }
3232 return 1;
3233}
252b5132 3234
29b0f896 3235static int
e3bb37b5 3236finalize_imm (void)
29b0f896
AM		 3237{
3238 unsigned int overlap0, overlap1, overlap2;
3239
3240 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3241 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3242 && overlap0 != Imm8 && overlap0 != Imm8S
3243 && overlap0 != Imm16 && overlap0 != Imm32S
3244 && overlap0 != Imm32 && overlap0 != Imm64)
3245 {
3246 if (i.suffix)
3247 {
3248 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3249 ? Imm8 | Imm8S
3250 : (i.suffix == WORD_MNEM_SUFFIX
3251 ? Imm16
3252 : (i.suffix == QWORD_MNEM_SUFFIX
3253 ? Imm64 | Imm32S
3254 : Imm32)));
3255 }
3256 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3257 || overlap0 == (Imm16 | Imm32)
3258 || overlap0 == (Imm16 | Imm32S))
3259 {
3260 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3261 ? Imm16 : Imm32S);
3262 }
3263 if (overlap0 != Imm8 && overlap0 != Imm8S
3264 && overlap0 != Imm16 && overlap0 != Imm32S
3265 && overlap0 != Imm32 && overlap0 != Imm64)
3266 {
4eed87de
AM		 3267 as_bad (_("no instruction mnemonic suffix given; "
3268 "can't determine immediate size"));
29b0f896
AM		 3269 return 0;
3270 }
3271 }
3272 i.types[0] = overlap0;
3273
3274 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3275 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3276 && overlap1 != Imm8 && overlap1 != Imm8S
3277 && overlap1 != Imm16 && overlap1 != Imm32S
3278 && overlap1 != Imm32 && overlap1 != Imm64)
3279 {
3280 if (i.suffix)
3281 {
3282 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3283 ? Imm8 | Imm8S
3284 : (i.suffix == WORD_MNEM_SUFFIX
3285 ? Imm16
3286 : (i.suffix == QWORD_MNEM_SUFFIX
3287 ? Imm64 | Imm32S
3288 : Imm32)));
3289 }
3290 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3291 || overlap1 == (Imm16 | Imm32)
3292 || overlap1 == (Imm16 | Imm32S))
3293 {
3294 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3295 ? Imm16 : Imm32S);
3296 }
3297 if (overlap1 != Imm8 && overlap1 != Imm8S
3298 && overlap1 != Imm16 && overlap1 != Imm32S
3299 && overlap1 != Imm32 && overlap1 != Imm64)
3300 {
4eed87de
AM		 3301 as_bad (_("no instruction mnemonic suffix given; "
3302 "can't determine immediate size %x %c"),
3303 overlap1, i.suffix);
29b0f896
AM		 3304 return 0;
3305 }
3306 }
3307 i.types[1] = overlap1;
3308
3309 overlap2 = i.types[2] & i.tm.operand_types[2];
3310 assert ((overlap2 & Imm) == 0);
3311 i.types[2] = overlap2;
3312
3313 return 1;
3314}
3315
3316static int
e3bb37b5 3317process_operands (void)
29b0f896
AM		 3318{
3319 /* Default segment register this instruction will use for memory
3320 accesses. 0 means unknown. This is only for optimizing out
3321 unnecessary segment overrides. */
3322 const seg_entry *default_seg = 0;
3323
3324 /* The imul $imm, %reg instruction is converted into
3325 imul $imm, %reg, %reg, and the clr %reg instruction
3326 is converted into xor %reg, %reg. */
5f15756d 3327 if (i.tm.opcode_modifier & RegKludge)
29b0f896 3328 {
42903f7f
L		 3329 if ((i.tm.cpu_flags & CpuSSE4_1))
3330 {
3331 /* The first operand in instruction blendvpd, blendvps and
3332 pblendvb in SSE4.1 is implicit and must be xmm0. */
3333 assert (i.operands == 3
3334 && i.reg_operands >= 2
3335 && i.types[0] == RegXMM);
3336 if (i.op[0].regs->reg_num != 0)
3337 {
3338 if (intel_syntax)
3339 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3340 i.tm.name, register_prefix);
3341 else
3342 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3343 i.tm.name, register_prefix);
3344 return 0;
3345 }
3346 i.op[0] = i.op[1];
3347 i.op[1] = i.op[2];
3348 i.types[0] = i.types[1];
3349 i.types[1] = i.types[2];
3350 i.operands--;
3351 i.reg_operands--;
3352
3353 /* We need to adjust fields in i.tm since they are used by
3354 build_modrm_byte. */
3355 i.tm.operand_types [0] = i.tm.operand_types [1];
3356 i.tm.operand_types [1] = i.tm.operand_types [2];
3357 i.tm.operands--;
3358 }
3359 else
3360 {
3361 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3362 /* Pretend we saw the extra register operand. */
3363 assert (i.reg_operands == 1
3364 && i.op[first_reg_op + 1].regs == 0);
3365 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3366 i.types[first_reg_op + 1] = i.types[first_reg_op];
3367 i.operands++;
3368 i.reg_operands++;
3369 }
29b0f896
AM		 3370 }
3371
3372 if (i.tm.opcode_modifier & ShortForm)
3373 {
4eed87de 3374 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3375 {
4eed87de
AM		 3376 if (i.tm.base_opcode == POP_SEG_SHORT
3377 && i.op[0].regs->reg_num == 1)
29b0f896 3378 {
4eed87de
AM		 3379 as_bad (_("you can't `pop %%cs'"));
3380 return 0;
29b0f896 3381 }
4eed87de
AM		 3382 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3383 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3384 i.rex |= REX_B;
4eed87de
AM		 3385 }
3386 else
3387 {
3388 /* The register or float register operand is in operand 0 or 1. */
3389 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3390 /* Register goes in low 3 bits of opcode. */
3391 i.tm.base_opcode |= i.op[op].regs->reg_num;
3392 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3393 i.rex |= REX_B;
4eed87de 3394 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3395 {
4eed87de
AM		 3396 /* Warn about some common errors, but press on regardless.
3397 The first case can be generated by gcc (<= 2.8.1). */
3398 if (i.operands == 2)
3399 {
3400 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3401 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3402 register_prefix, i.op[1].regs->reg_name,
3403 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3404 }
3405 else
3406 {
3407 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3408 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3409 register_prefix, i.op[0].regs->reg_name);
4eed87de 3410 }
29b0f896
AM		 3411 }
3412 }
3413 }
3414 else if (i.tm.opcode_modifier & Modrm)
3415 {
3416 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3417 must be put into the modrm byte). Now, we make the modrm and
3418 index base bytes based on all the info we've collected. */
29b0f896
AM		 3419
3420 default_seg = build_modrm_byte ();
3421 }
8a2ed489 3422 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3423 {
3424 default_seg = &ds;
3425 }
3426 else if ((i.tm.opcode_modifier & IsString) != 0)
3427 {
3428 /* For the string instructions that allow a segment override
3429 on one of their operands, the default segment is ds. */
3430 default_seg = &ds;
3431 }
3432
30123838
JB		 3433 if ((i.tm.base_opcode == 0x8d /* lea */
3434 || (i.tm.cpu_flags & CpuSVME))
3435 && i.seg[0] && !quiet_warnings)
3436 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3437
3438 /* If a segment was explicitly specified, and the specified segment
3439 is not the default, use an opcode prefix to select it. If we
3440 never figured out what the default segment is, then default_seg
3441 will be zero at this point, and the specified segment prefix will
3442 always be used. */
29b0f896
AM		 3443 if ((i.seg[0]) && (i.seg[0] != default_seg))
3444 {
3445 if (!add_prefix (i.seg[0]->seg_prefix))
3446 return 0;
3447 }
3448 return 1;
3449}
3450
3451static const seg_entry *
e3bb37b5 3452build_modrm_byte (void)
29b0f896
AM		 3453{
3454 const seg_entry *default_seg = 0;
3455
3456 /* i.reg_operands MUST be the number of real register operands;
3457 implicit registers do not count. */
3458 if (i.reg_operands == 2)
3459 {
3460 unsigned int source, dest;
cab737b9
L		 3461
3462 switch (i.operands)
3463 {
3464 case 2:
3465 source = 0;
3466 break;
3467 case 3:
c81128dc
L		 3468 /* When there are 3 operands, one of them may be immediate,
3469 which may be the first or the last operand. Otherwise,
3470 the first operand must be shift count register (cl). */
3471 assert (i.imm_operands == 1
3472 || (i.imm_operands == 0
3473 && (i.types[0] & ShiftCount)));
3474 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3475 break;
3476 case 4:
3477 /* When there are 4 operands, the first two must be immediate
3478 operands. The source operand will be the 3rd one. */
3479 assert (i.imm_operands == 2
3480 && (i.types[0] & Imm)
3481 && (i.types[1] & Imm));
3482 source = 2;
3483 break;
3484 default:
3485 abort ();
3486 }
3487
29b0f896
AM		 3488 dest = source + 1;
3489
3490 i.rm.mode = 3;
3491 /* One of the register operands will be encoded in the i.tm.reg
3492 field, the other in the combined i.tm.mode and i.tm.regmem
3493 fields. If no form of this instruction supports a memory
3494 destination operand, then we assume the source operand may
3495 sometimes be a memory operand and so we need to store the
3496 destination in the i.rm.reg field. */
e72cf3ec 3497 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM		 3498 {
3499 i.rm.reg = i.op[dest].regs->reg_num;
3500 i.rm.regmem = i.op[source].regs->reg_num;
3501 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3502 i.rex |= REX_R;
29b0f896 3503 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3504 i.rex |= REX_B;
29b0f896
AM		 3505 }
3506 else
3507 {
3508 i.rm.reg = i.op[source].regs->reg_num;
3509 i.rm.regmem = i.op[dest].regs->reg_num;
3510 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3511 i.rex |= REX_B;
29b0f896 3512 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3513 i.rex |= REX_R;
29b0f896 3514 }
161a04f6 3515 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB		 3516 {
3517 if (!((i.types[0] | i.types[1]) & Control))
3518 abort ();
161a04f6 3519 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 3520 add_prefix (LOCK_PREFIX_OPCODE);
3521 }
29b0f896
AM		 3522 }
3523 else
3524 { /* If it's not 2 reg operands... */
3525 if (i.mem_operands)
3526 {
3527 unsigned int fake_zero_displacement = 0;
99018f42 3528 unsigned int op;
4eed87de 3529
99018f42
L		 3530 for (op = 0; op < i.operands; op++)
3531 if ((i.types[op] & AnyMem))
3532 break;
3533 assert (op < i.operands);
29b0f896
AM		 3534
3535 default_seg = &ds;
3536
3537 if (i.base_reg == 0)
3538 {
3539 i.rm.mode = 0;
3540 if (!i.disp_operands)
3541 fake_zero_displacement = 1;
3542 if (i.index_reg == 0)
3543 {
3544 /* Operand is just <disp> */
20f0a1fc 3545 if (flag_code == CODE_64BIT)
29b0f896
AM		 3546 {
3547 /* 64bit mode overwrites the 32bit absolute
3548 addressing by RIP relative addressing and
3549 absolute addressing is encoded by one of the
3550 redundant SIB forms. */
3551 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3552 i.sib.base = NO_BASE_REGISTER;
3553 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3554 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3555 ? Disp32S : Disp32);
20f0a1fc 3556 }
fc225355
L		 3557 else if ((flag_code == CODE_16BIT)
3558 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3559 {
3560 i.rm.regmem = NO_BASE_REGISTER_16;
3561 i.types[op] = Disp16;
3562 }
3563 else
3564 {
3565 i.rm.regmem = NO_BASE_REGISTER;
3566 i.types[op] = Disp32;
29b0f896
AM		 3567 }
3568 }
3569 else /* !i.base_reg && i.index_reg */
3570 {
3571 i.sib.index = i.index_reg->reg_num;
3572 i.sib.base = NO_BASE_REGISTER;
3573 i.sib.scale = i.log2_scale_factor;
3574 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3575 i.types[op] &= ~Disp;
3576 if (flag_code != CODE_64BIT)
3577 i.types[op] |= Disp32; /* Must be 32 bit */
3578 else
3579 i.types[op] |= Disp32S;
3580 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3581 i.rex |= REX_X;
29b0f896
AM		 3582 }
3583 }
3584 /* RIP addressing for 64bit mode. */
3585 else if (i.base_reg->reg_type == BaseIndex)
3586 {
3587 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3588 i.types[op] &= ~ Disp;
29b0f896 3589 i.types[op] |= Disp32S;
71903a11 3590 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3591 if (! i.disp_operands)
3592 fake_zero_displacement = 1;
29b0f896
AM		 3593 }
3594 else if (i.base_reg->reg_type & Reg16)
3595 {
3596 switch (i.base_reg->reg_num)
3597 {
3598 case 3: /* (%bx) */
3599 if (i.index_reg == 0)
3600 i.rm.regmem = 7;
3601 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3602 i.rm.regmem = i.index_reg->reg_num - 6;
3603 break;
3604 case 5: /* (%bp) */
3605 default_seg = &ss;
3606 if (i.index_reg == 0)
3607 {
3608 i.rm.regmem = 6;
3609 if ((i.types[op] & Disp) == 0)
3610 {
3611 /* fake (%bp) into 0(%bp) */
3612 i.types[op] |= Disp8;
252b5132 3613 fake_zero_displacement = 1;
29b0f896
AM		 3614 }
3615 }
3616 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3617 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3618 break;
3619 default: /* (%si) -> 4 or (%di) -> 5 */
3620 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3621 }
3622 i.rm.mode = mode_from_disp_size (i.types[op]);
3623 }
3624 else /* i.base_reg and 32/64 bit mode */
3625 {
3626 if (flag_code == CODE_64BIT
3627 && (i.types[op] & Disp))
fc225355
L		 3628 i.types[op] = ((i.types[op] & Disp8)
3629 | (i.prefix[ADDR_PREFIX] == 0
3630 ? Disp32S : Disp32));
20f0a1fc 3631
29b0f896
AM		 3632 i.rm.regmem = i.base_reg->reg_num;
3633 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3634 i.rex |= REX_B;
29b0f896
AM		 3635 i.sib.base = i.base_reg->reg_num;
3636 /* x86-64 ignores REX prefix bit here to avoid decoder
3637 complications. */
3638 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3639 {
3640 default_seg = &ss;
3641 if (i.disp_operands == 0)
3642 {
3643 fake_zero_displacement = 1;
3644 i.types[op] |= Disp8;
3645 }
3646 }
3647 else if (i.base_reg->reg_num == ESP_REG_NUM)
3648 {
3649 default_seg = &ss;
3650 }
3651 i.sib.scale = i.log2_scale_factor;
3652 if (i.index_reg == 0)
3653 {
3654 /* <disp>(%esp) becomes two byte modrm with no index
3655 register. We've already stored the code for esp
3656 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3657 Any base register besides %esp will not use the
3658 extra modrm byte. */
3659 i.sib.index = NO_INDEX_REGISTER;
3660#if !SCALE1_WHEN_NO_INDEX
3661 /* Another case where we force the second modrm byte. */
3662 if (i.log2_scale_factor)
3663 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3664#endif
29b0f896
AM		 3665 }
3666 else
3667 {
3668 i.sib.index = i.index_reg->reg_num;
3669 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3670 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3671 i.rex |= REX_X;
29b0f896 3672 }
67a4f2b7
AO		 3673
3674 if (i.disp_operands
3675 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3676 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3677 i.rm.mode = 0;
3678 else
3679 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3680 }
252b5132 3681
29b0f896
AM		 3682 if (fake_zero_displacement)
3683 {
3684 /* Fakes a zero displacement assuming that i.types[op]
3685 holds the correct displacement size. */
3686 expressionS *exp;
3687
3688 assert (i.op[op].disps == 0);
3689 exp = &disp_expressions[i.disp_operands++];
3690 i.op[op].disps = exp;
3691 exp->X_op = O_constant;
3692 exp->X_add_number = 0;
3693 exp->X_add_symbol = (symbolS *) 0;
3694 exp->X_op_symbol = (symbolS *) 0;
3695 }
3696 }
252b5132 3697
29b0f896
AM		 3698 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3699 (if any) based on i.tm.extension_opcode. Again, we must be
3700 careful to make sure that segment/control/debug/test/MMX
3701 registers are coded into the i.rm.reg field. */
3702 if (i.reg_operands)
3703 {
99018f42
L		 3704 unsigned int op;
3705
3706 for (op = 0; op < i.operands; op++)
3707 if ((i.types[op] & (Reg | RegMMX | RegXMM
3708 | SReg2 | SReg3
3709 | Control | Debug | Test)))
3710 break;
3711 assert (op < i.operands);
3712
29b0f896
AM		 3713 /* If there is an extension opcode to put here, the register
3714 number must be put into the regmem field. */
3715 if (i.tm.extension_opcode != None)
3716 {
3717 i.rm.regmem = i.op[op].regs->reg_num;
3718 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3719 i.rex |= REX_B;
29b0f896
AM		 3720 }
3721 else
3722 {
3723 i.rm.reg = i.op[op].regs->reg_num;
3724 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3725 i.rex |= REX_R;
29b0f896 3726 }
252b5132 3727
29b0f896
AM		 3728 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3729 must set it to 3 to indicate this is a register operand
3730 in the regmem field. */
3731 if (!i.mem_operands)
3732 i.rm.mode = 3;
3733 }
252b5132 3734
29b0f896
AM		 3735 /* Fill in i.rm.reg field with extension opcode (if any). */
3736 if (i.tm.extension_opcode != None)
3737 i.rm.reg = i.tm.extension_opcode;
3738 }
3739 return default_seg;
3740}
252b5132 3741
29b0f896 3742static void
e3bb37b5 3743output_branch (void)
29b0f896
AM		 3744{
3745 char *p;
3746 int code16;
3747 int prefix;
3748 relax_substateT subtype;
3749 symbolS *sym;
3750 offsetT off;
3751
3752 code16 = 0;
3753 if (flag_code == CODE_16BIT)
3754 code16 = CODE16;
3755
3756 prefix = 0;
3757 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3758 {
29b0f896
AM		 3759 prefix = 1;
3760 i.prefixes -= 1;
3761 code16 ^= CODE16;
252b5132 3762 }
29b0f896
AM		 3763 /* Pentium4 branch hints. */
3764 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3765 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3766 {
29b0f896
AM		 3767 prefix++;
3768 i.prefixes--;
3769 }
3770 if (i.prefix[REX_PREFIX] != 0)
3771 {
3772 prefix++;
3773 i.prefixes--;
2f66722d
AM		 3774 }
3775
29b0f896
AM		 3776 if (i.prefixes != 0 && !intel_syntax)
3777 as_warn (_("skipping prefixes on this instruction"));
3778
3779 /* It's always a symbol; End frag & setup for relax.
3780 Make sure there is enough room in this frag for the largest
3781 instruction we may generate in md_convert_frag. This is 2
3782 bytes for the opcode and room for the prefix and largest
3783 displacement. */
3784 frag_grow (prefix + 2 + 4);
3785 /* Prefix and 1 opcode byte go in fr_fix. */
3786 p = frag_more (prefix + 1);
3787 if (i.prefix[DATA_PREFIX] != 0)
3788 *p++ = DATA_PREFIX_OPCODE;
3789 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3790 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3791 *p++ = i.prefix[SEG_PREFIX];
3792 if (i.prefix[REX_PREFIX] != 0)
3793 *p++ = i.prefix[REX_PREFIX];
3794 *p = i.tm.base_opcode;
3795
3796 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3797 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3798 else if ((cpu_arch_flags & Cpu386) != 0)
3799 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3800 else
3801 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3802 subtype |= code16;
3e73aa7c 3803
29b0f896
AM		 3804 sym = i.op[0].disps->X_add_symbol;
3805 off = i.op[0].disps->X_add_number;
3e73aa7c 3806
29b0f896
AM		 3807 if (i.op[0].disps->X_op != O_constant
3808 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3809 {
29b0f896
AM		 3810 /* Handle complex expressions. */
3811 sym = make_expr_symbol (i.op[0].disps);
3812 off = 0;
3813 }
3e73aa7c 3814
29b0f896
AM		 3815 /* 1 possible extra opcode + 4 byte displacement go in var part.
3816 Pass reloc in fr_var. */
3817 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3818}
3e73aa7c 3819
29b0f896 3820static void
e3bb37b5 3821output_jump (void)
29b0f896
AM		 3822{
3823 char *p;
3824 int size;
3e02c1cc 3825 fixS *fixP;
29b0f896
AM		 3826
3827 if (i.tm.opcode_modifier & JumpByte)
3828 {
3829 /* This is a loop or jecxz type instruction. */
3830 size = 1;
3831 if (i.prefix[ADDR_PREFIX] != 0)
3832 {
3833 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3834 i.prefixes -= 1;
3835 }
3836 /* Pentium4 branch hints. */
3837 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3838 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3839 {
3840 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3841 i.prefixes--;
3e73aa7c
JH		 3842 }
3843 }
29b0f896
AM		 3844 else
3845 {
3846 int code16;
3e73aa7c 3847
29b0f896
AM		 3848 code16 = 0;
3849 if (flag_code == CODE_16BIT)
3850 code16 = CODE16;
3e73aa7c 3851
29b0f896
AM		 3852 if (i.prefix[DATA_PREFIX] != 0)
3853 {
3854 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3855 i.prefixes -= 1;
3856 code16 ^= CODE16;
3857 }
252b5132 3858
29b0f896
AM		 3859 size = 4;
3860 if (code16)
3861 size = 2;
3862 }
9fcc94b6 3863
29b0f896
AM		 3864 if (i.prefix[REX_PREFIX] != 0)
3865 {
3866 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3867 i.prefixes -= 1;
3868 }
252b5132 3869
29b0f896
AM		 3870 if (i.prefixes != 0 && !intel_syntax)
3871 as_warn (_("skipping prefixes on this instruction"));
e0890092 3872
29b0f896
AM		 3873 p = frag_more (1 + size);
3874 *p++ = i.tm.base_opcode;
e0890092 3875
3e02c1cc
AM		 3876 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3877 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3878
3879 /* All jumps handled here are signed, but don't use a signed limit
3880 check for 32 and 16 bit jumps as we want to allow wrap around at
3881 4G and 64k respectively. */
3882 if (size == 1)
3883 fixP->fx_signed = 1;
29b0f896 3884}
e0890092 3885
29b0f896 3886static void
e3bb37b5 3887output_interseg_jump (void)
29b0f896
AM		 3888{
3889 char *p;
3890 int size;
3891 int prefix;
3892 int code16;
252b5132 3893
29b0f896
AM		 3894 code16 = 0;
3895 if (flag_code == CODE_16BIT)
3896 code16 = CODE16;
a217f122 3897
29b0f896
AM		 3898 prefix = 0;
3899 if (i.prefix[DATA_PREFIX] != 0)
3900 {
3901 prefix = 1;
3902 i.prefixes -= 1;
3903 code16 ^= CODE16;
3904 }
3905 if (i.prefix[REX_PREFIX] != 0)
3906 {
3907 prefix++;
3908 i.prefixes -= 1;
3909 }
252b5132 3910
29b0f896
AM		 3911 size = 4;
3912 if (code16)
3913 size = 2;
252b5132 3914
29b0f896
AM		 3915 if (i.prefixes != 0 && !intel_syntax)
3916 as_warn (_("skipping prefixes on this instruction"));
252b5132 3917
29b0f896
AM		 3918 /* 1 opcode; 2 segment; offset */
3919 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3920
29b0f896
AM		 3921 if (i.prefix[DATA_PREFIX] != 0)
3922 *p++ = DATA_PREFIX_OPCODE;
252b5132 3923
29b0f896
AM		 3924 if (i.prefix[REX_PREFIX] != 0)
3925 *p++ = i.prefix[REX_PREFIX];
252b5132 3926
29b0f896
AM		 3927 *p++ = i.tm.base_opcode;
3928 if (i.op[1].imms->X_op == O_constant)
3929 {
3930 offsetT n = i.op[1].imms->X_add_number;
252b5132 3931
29b0f896
AM		 3932 if (size == 2
3933 && !fits_in_unsigned_word (n)
3934 && !fits_in_signed_word (n))
3935 {
3936 as_bad (_("16-bit jump out of range"));
3937 return;
3938 }
3939 md_number_to_chars (p, n, size);
3940 }
3941 else
3942 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3943 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3944 if (i.op[0].imms->X_op != O_constant)
3945 as_bad (_("can't handle non absolute segment in `%s'"),
3946 i.tm.name);
3947 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3948}
a217f122 3949
29b0f896 3950static void
e3bb37b5 3951output_insn (void)
29b0f896 3952{
2bbd9c25
JJ		 3953 fragS *insn_start_frag;
3954 offsetT insn_start_off;
3955
29b0f896
AM		 3956 /* Tie dwarf2 debug info to the address at the start of the insn.
3957 We can't do this after the insn has been output as the current
3958 frag may have been closed off. eg. by frag_var. */
3959 dwarf2_emit_insn (0);
3960
2bbd9c25
JJ		 3961 insn_start_frag = frag_now;
3962 insn_start_off = frag_now_fix ();
3963
29b0f896
AM		 3964 /* Output jumps. */
3965 if (i.tm.opcode_modifier & Jump)
3966 output_branch ();
3967 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3968 output_jump ();
3969 else if (i.tm.opcode_modifier & JumpInterSegment)
3970 output_interseg_jump ();
3971 else
3972 {
3973 /* Output normal instructions here. */
3974 char *p;
3975 unsigned char *q;
331d2d0d 3976 unsigned int prefix;
252b5132 3977
42903f7f 3978 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 3979 SSE4 instructions have 3 bytes. We may use one more higher
3980 byte to specify a prefix the instruction requires. Exclude
3981 instructions which are in both SSE4 and ABM. */
3982 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
3983 && (i.tm.cpu_flags & CpuABM) == 0)
bc4bd9ab 3984 {
331d2d0d
L		 3985 if (i.tm.base_opcode & 0xff000000)
3986 {
3987 prefix = (i.tm.base_opcode >> 24) & 0xff;
3988 goto check_prefix;
3989 }
3990 }
3991 else if ((i.tm.base_opcode & 0xff0000) != 0)
3992 {
3993 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3994 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3995 {
64e74474 3996 check_prefix:
bc4bd9ab
MK		 3997 if (prefix != REPE_PREFIX_OPCODE
3998 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3999 add_prefix (prefix);
4000 }
4001 else
331d2d0d 4002 add_prefix (prefix);
0f10071e 4003 }
252b5132 4004
29b0f896
AM		 4005 /* The prefix bytes. */
4006 for (q = i.prefix;
4007 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
4008 q++)
4009 {
4010 if (*q)
4011 {
4012 p = frag_more (1);
4013 md_number_to_chars (p, (valueT) *q, 1);
4014 }
4015 }
252b5132 4016
29b0f896
AM		 4017 /* Now the opcode; be careful about word order here! */
4018 if (fits_in_unsigned_byte (i.tm.base_opcode))
4019 {
4020 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4021 }
4022 else
4023 {
381d071f
L		 4024 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4025 && (i.tm.cpu_flags & CpuABM) == 0)
331d2d0d
L		 4026 {
4027 p = frag_more (3);
4028 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4029 }
4030 else
4031 p = frag_more (2);
0f10071e 4032
29b0f896
AM		 4033 /* Put out high byte first: can't use md_number_to_chars! */
4034 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4035 *p = i.tm.base_opcode & 0xff;
4036 }
3e73aa7c 4037
29b0f896
AM		 4038 /* Now the modrm byte and sib byte (if present). */
4039 if (i.tm.opcode_modifier & Modrm)
4040 {
4041 p = frag_more (1);
4042 md_number_to_chars (p,
4043 (valueT) (i.rm.regmem << 0
4044 | i.rm.reg << 3
4045 | i.rm.mode << 6),
4046 1);
4047 /* If i.rm.regmem == ESP (4)
4048 && i.rm.mode != (Register mode)
4049 && not 16 bit
4050 ==> need second modrm byte. */
4051 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4052 && i.rm.mode != 3
4053 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4054 {
4055 p = frag_more (1);
4056 md_number_to_chars (p,
4057 (valueT) (i.sib.base << 0
4058 | i.sib.index << 3
4059 | i.sib.scale << 6),
4060 1);
4061 }
4062 }
3e73aa7c 4063
29b0f896 4064 if (i.disp_operands)
2bbd9c25 4065 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4066
29b0f896 4067 if (i.imm_operands)
2bbd9c25 4068 output_imm (insn_start_frag, insn_start_off);
29b0f896 4069 }
252b5132 4070
29b0f896
AM		 4071#ifdef DEBUG386
4072 if (flag_debug)
4073 {
7b81dfbb 4074 pi ("" /*line*/, &i);
29b0f896
AM		 4075 }
4076#endif /* DEBUG386 */
4077}
252b5132 4078
e205caa7
L		 4079/* Return the size of the displacement operand N. */
4080
4081static int
4082disp_size (unsigned int n)
4083{
4084 int size = 4;
4085 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4086 {
4087 size = 2;
4088 if (i.types[n] & Disp8)
4089 size = 1;
4090 if (i.types[n] & Disp64)
4091 size = 8;
4092 }
4093 return size;
4094}
4095
4096/* Return the size of the immediate operand N. */
4097
4098static int
4099imm_size (unsigned int n)
4100{
4101 int size = 4;
4102 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4103 {
4104 size = 2;
4105 if (i.types[n] & (Imm8 | Imm8S))
4106 size = 1;
4107 if (i.types[n] & Imm64)
4108 size = 8;
4109 }
4110 return size;
4111}
4112
29b0f896 4113static void
64e74474 4114output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4115{
4116 char *p;
4117 unsigned int n;
252b5132 4118
29b0f896
AM		 4119 for (n = 0; n < i.operands; n++)
4120 {
4121 if (i.types[n] & Disp)
4122 {
4123 if (i.op[n].disps->X_op == O_constant)
4124 {
e205caa7 4125 int size = disp_size (n);
29b0f896 4126 offsetT val;
252b5132 4127
29b0f896
AM		 4128 val = offset_in_range (i.op[n].disps->X_add_number,
4129 size);
4130 p = frag_more (size);
4131 md_number_to_chars (p, val, size);
4132 }
4133 else
4134 {
f86103b7 4135 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4136 int size = disp_size (n);
4137 int sign = (i.types[n] & Disp32S) != 0;
29b0f896
AM		 4138 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4139
e205caa7
L		 4140 /* We can't have 8 bit displacement here. */
4141 assert ((i.types[n] & Disp8) == 0);
4142
29b0f896
AM		 4143 /* The PC relative address is computed relative
4144 to the instruction boundary, so in case immediate
4145 fields follows, we need to adjust the value. */
4146 if (pcrel && i.imm_operands)
4147 {
29b0f896 4148 unsigned int n1;
e205caa7 4149 int sz = 0;
252b5132 4150
29b0f896
AM		 4151 for (n1 = 0; n1 < i.operands; n1++)
4152 if (i.types[n1] & Imm)
252b5132 4153 {
e205caa7
L		 4154 /* Only one immediate is allowed for PC
4155 relative address. */
4156 assert (sz == 0);
4157 sz = imm_size (n1);
4158 i.op[n].disps->X_add_number -= sz;
252b5132 4159 }
29b0f896 4160 /* We should find the immediate. */
e205caa7 4161 assert (sz != 0);
29b0f896 4162 }
520dc8e8 4163
29b0f896 4164 p = frag_more (size);
2bbd9c25 4165 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4166 if (GOT_symbol
2bbd9c25 4167 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4168 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4169 || reloc_type == BFD_RELOC_X86_64_32S
4170 || (reloc_type == BFD_RELOC_64
4171 && object_64bit))
d6ab8113
JB		 4172 && (i.op[n].disps->X_op == O_symbol
4173 || (i.op[n].disps->X_op == O_add
4174 && ((symbol_get_value_expression
4175 (i.op[n].disps->X_op_symbol)->X_op)
4176 == O_subtract))))
4177 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4178 {
4179 offsetT add;
4180
4181 if (insn_start_frag == frag_now)
4182 add = (p - frag_now->fr_literal) - insn_start_off;
4183 else
4184 {
4185 fragS *fr;
4186
4187 add = insn_start_frag->fr_fix - insn_start_off;
4188 for (fr = insn_start_frag->fr_next;
4189 fr && fr != frag_now; fr = fr->fr_next)
4190 add += fr->fr_fix;
4191 add += p - frag_now->fr_literal;
4192 }
4193
4fa24527 4194 if (!object_64bit)
7b81dfbb
AJ		 4195 {
4196 reloc_type = BFD_RELOC_386_GOTPC;
4197 i.op[n].imms->X_add_number += add;
4198 }
4199 else if (reloc_type == BFD_RELOC_64)
4200 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4201 else
7b81dfbb
AJ		 4202 /* Don't do the adjustment for x86-64, as there
4203 the pcrel addressing is relative to the _next_
4204 insn, and that is taken care of in other code. */
d6ab8113 4205 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4206 }
062cd5e7 4207 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4208 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4209 }
4210 }
4211 }
4212}
252b5132 4213
29b0f896 4214static void
64e74474 4215output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4216{
4217 char *p;
4218 unsigned int n;
252b5132 4219
29b0f896
AM		 4220 for (n = 0; n < i.operands; n++)
4221 {
4222 if (i.types[n] & Imm)
4223 {
4224 if (i.op[n].imms->X_op == O_constant)
4225 {
e205caa7 4226 int size = imm_size (n);
29b0f896 4227 offsetT val;
b4cac588 4228
29b0f896
AM		 4229 val = offset_in_range (i.op[n].imms->X_add_number,
4230 size);
4231 p = frag_more (size);
4232 md_number_to_chars (p, val, size);
4233 }
4234 else
4235 {
4236 /* Not absolute_section.
4237 Need a 32-bit fixup (don't support 8bit
4238 non-absolute imms). Try to support other
4239 sizes ... */
f86103b7 4240 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 4241 int size = imm_size (n);
4242 int sign;
29b0f896
AM		 4243
4244 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4245 && (i.suffix == QWORD_MNEM_SUFFIX
4246 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896 4247 sign = 1;
e205caa7
L		 4248 else
4249 sign = 0;
520dc8e8 4250
29b0f896
AM		 4251 p = frag_more (size);
4252 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4253
2bbd9c25
JJ		 4254 /* This is tough to explain. We end up with this one if we
4255 * have operands that look like
4256 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4257 * obtain the absolute address of the GOT, and it is strongly
4258 * preferable from a performance point of view to avoid using
4259 * a runtime relocation for this. The actual sequence of
4260 * instructions often look something like:
4261 *
4262 * call .L66
4263 * .L66:
4264 * popl %ebx
4265 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4266 *
4267 * The call and pop essentially return the absolute address
4268 * of the label .L66 and store it in %ebx. The linker itself
4269 * will ultimately change the first operand of the addl so
4270 * that %ebx points to the GOT, but to keep things simple, the
4271 * .o file must have this operand set so that it generates not
4272 * the absolute address of .L66, but the absolute address of
4273 * itself. This allows the linker itself simply treat a GOTPC
4274 * relocation as asking for a pcrel offset to the GOT to be
4275 * added in, and the addend of the relocation is stored in the
4276 * operand field for the instruction itself.
4277 *
4278 * Our job here is to fix the operand so that it would add
4279 * the correct offset so that %ebx would point to itself. The
4280 * thing that is tricky is that .-.L66 will point to the
4281 * beginning of the instruction, so we need to further modify
4282 * the operand so that it will point to itself. There are
4283 * other cases where you have something like:
4284 *
4285 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4286 *
4287 * and here no correction would be required. Internally in
4288 * the assembler we treat operands of this form as not being
4289 * pcrel since the '.' is explicitly mentioned, and I wonder
4290 * whether it would simplify matters to do it this way. Who
4291 * knows. In earlier versions of the PIC patches, the
4292 * pcrel_adjust field was used to store the correction, but
4293 * since the expression is not pcrel, I felt it would be
4294 * confusing to do it this way. */
4295
d6ab8113 4296 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4297 || reloc_type == BFD_RELOC_X86_64_32S
4298 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4299 && GOT_symbol
4300 && GOT_symbol == i.op[n].imms->X_add_symbol
4301 && (i.op[n].imms->X_op == O_symbol
4302 || (i.op[n].imms->X_op == O_add
4303 && ((symbol_get_value_expression
4304 (i.op[n].imms->X_op_symbol)->X_op)
4305 == O_subtract))))
4306 {
2bbd9c25
JJ		 4307 offsetT add;
4308
4309 if (insn_start_frag == frag_now)
4310 add = (p - frag_now->fr_literal) - insn_start_off;
4311 else
4312 {
4313 fragS *fr;
4314
4315 add = insn_start_frag->fr_fix - insn_start_off;
4316 for (fr = insn_start_frag->fr_next;
4317 fr && fr != frag_now; fr = fr->fr_next)
4318 add += fr->fr_fix;
4319 add += p - frag_now->fr_literal;
4320 }
4321
4fa24527 4322 if (!object_64bit)
d6ab8113 4323 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4324 else if (size == 4)
d6ab8113 4325 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4326 else if (size == 8)
4327 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4328 i.op[n].imms->X_add_number += add;
29b0f896 4329 }
29b0f896
AM		 4330 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4331 i.op[n].imms, 0, reloc_type);
4332 }
4333 }
4334 }
252b5132
RH		 4335}
4336\f
d182319b
JB		 4337/* x86_cons_fix_new is called via the expression parsing code when a
4338 reloc is needed. We use this hook to get the correct .got reloc. */
4339static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4340static int cons_sign = -1;
4341
4342void
e3bb37b5 4343x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4344 expressionS *exp)
d182319b
JB		 4345{
4346 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4347
4348 got_reloc = NO_RELOC;
4349
4350#ifdef TE_PE
4351 if (exp->X_op == O_secrel)
4352 {
4353 exp->X_op = O_symbol;
4354 r = BFD_RELOC_32_SECREL;
4355 }
4356#endif
4357
4358 fix_new_exp (frag, off, len, exp, 0, r);
4359}
4360
718ddfc0
JB		 4361#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4362# define lex_got(reloc, adjust, types) NULL
4363#else
f3c180ae
AM		 4364/* Parse operands of the form
4365 <symbol>@GOTOFF+<nnn>
4366 and similar .plt or .got references.
4367
4368 If we find one, set up the correct relocation in RELOC and copy the
4369 input string, minus the `@GOTOFF' into a malloc'd buffer for
4370 parsing by the calling routine. Return this buffer, and if ADJUST
4371 is non-null set it to the length of the string we removed from the
4372 input line. Otherwise return NULL. */
4373static char *
3956db08 4374lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4375 int *adjust,
4376 unsigned int *types)
f3c180ae 4377{
7b81dfbb
AJ		 4378 /* Some of the relocations depend on the size of what field is to
4379 be relocated. But in our callers i386_immediate and i386_displacement
4380 we don't yet know the operand size (this will be set by insn
4381 matching). Hence we record the word32 relocation here,
4382 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4383 static const struct {
4384 const char *str;
4fa24527 4385 const enum bfd_reloc_code_real rel[2];
3956db08 4386 const unsigned int types64;
f3c180ae 4387 } gotrel[] = {
4eed87de
AM		 4388 { "PLTOFF", { 0,
4389 BFD_RELOC_X86_64_PLTOFF64 },
4390 Imm64 },
4391 { "PLT", { BFD_RELOC_386_PLT32,
4392 BFD_RELOC_X86_64_PLT32 },
4393 Imm32 | Imm32S | Disp32 },
4394 { "GOTPLT", { 0,
4395 BFD_RELOC_X86_64_GOTPLT64 },
4396 Imm64 | Disp64 },
4397 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4398 BFD_RELOC_X86_64_GOTOFF64 },
4399 Imm64 | Disp64 },
4400 { "GOTPCREL", { 0,
4401 BFD_RELOC_X86_64_GOTPCREL },
4402 Imm32 | Imm32S | Disp32 },
4403 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4404 BFD_RELOC_X86_64_TLSGD },
4405 Imm32 | Imm32S | Disp32 },
4406 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4407 0 },
4408 0 },
4409 { "TLSLD", { 0,
4410 BFD_RELOC_X86_64_TLSLD },
4411 Imm32 | Imm32S | Disp32 },
4412 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4413 BFD_RELOC_X86_64_GOTTPOFF },
4414 Imm32 | Imm32S | Disp32 },
4415 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4416 BFD_RELOC_X86_64_TPOFF32 },
4417 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4418 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4419 0 },
4420 0 },
4421 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4422 BFD_RELOC_X86_64_DTPOFF32 },
4423 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4424 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4425 0 },
4426 0 },
4427 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4428 0 },
4429 0 },
4430 { "GOT", { BFD_RELOC_386_GOT32,
4431 BFD_RELOC_X86_64_GOT32 },
4432 Imm32 | Imm32S | Disp32 | Imm64 },
4433 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4434 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4435 Imm32 | Imm32S | Disp32 },
4436 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4437 BFD_RELOC_X86_64_TLSDESC_CALL },
4438 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4439 };
4440 char *cp;
4441 unsigned int j;
4442
718ddfc0
JB		 4443 if (!IS_ELF)
4444 return NULL;
4445
f3c180ae
AM		 4446 for (cp = input_line_pointer; *cp != '@'; cp++)
4447 if (is_end_of_line[(unsigned char) *cp])
4448 return NULL;
4449
4450 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4451 {
4452 int len;
4453
4454 len = strlen (gotrel[j].str);
28f81592 4455 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4456 {
4fa24527 4457 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4458 {
28f81592
AM		 4459 int first, second;
4460 char *tmpbuf, *past_reloc;
f3c180ae 4461
4fa24527 4462 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4463 if (adjust)
4464 *adjust = len;
f3c180ae 4465
3956db08
JB		 4466 if (types)
4467 {
4468 if (flag_code != CODE_64BIT)
4eed87de 4469 *types = Imm32 | Disp32;
3956db08
JB		 4470 else
4471 *types = gotrel[j].types64;
4472 }
4473
f3c180ae
AM		 4474 if (GOT_symbol == NULL)
4475 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4476
28f81592 4477 /* The length of the first part of our input line. */
f3c180ae 4478 first = cp - input_line_pointer;
28f81592
AM		 4479
4480 /* The second part goes from after the reloc token until
4481 (and including) an end_of_line char. Don't use strlen
4482 here as the end_of_line char may not be a NUL. */
4483 past_reloc = cp + 1 + len;
4484 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4485 ;
4486 second = cp - past_reloc;
4487
4488 /* Allocate and copy string. The trailing NUL shouldn't
4489 be necessary, but be safe. */
4490 tmpbuf = xmalloc (first + second + 2);
f3c180ae 4491 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 4492 if (second != 0 && *past_reloc != ' ')
4493 /* Replace the relocation token with ' ', so that
4494 errors like foo@GOTOFF1 will be detected. */
4495 tmpbuf[first++] = ' ';
4496 memcpy (tmpbuf + first, past_reloc, second);
4497 tmpbuf[first + second] = '\0';
f3c180ae
AM		 4498 return tmpbuf;
4499 }
4500
4fa24527
JB		 4501 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4502 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4503 return NULL;
4504 }
4505 }
4506
4507 /* Might be a symbol version string. Don't as_bad here. */
4508 return NULL;
4509}
4510
f3c180ae 4511void
e3bb37b5 4512x86_cons (expressionS *exp, int size)
f3c180ae 4513{
4fa24527 4514 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4515 {
4516 /* Handle @GOTOFF and the like in an expression. */
4517 char *save;
4518 char *gotfree_input_line;
4519 int adjust;
4520
4521 save = input_line_pointer;
3956db08 4522 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4523 if (gotfree_input_line)
4524 input_line_pointer = gotfree_input_line;
4525
4526 expression (exp);
4527
4528 if (gotfree_input_line)
4529 {
4530 /* expression () has merrily parsed up to the end of line,
4531 or a comma - in the wrong buffer. Transfer how far
4532 input_line_pointer has moved to the right buffer. */
4533 input_line_pointer = (save
4534 + (input_line_pointer - gotfree_input_line)
4535 + adjust);
4536 free (gotfree_input_line);
4537 }
4538 }
4539 else
4540 expression (exp);
4541}
4542#endif
4543
d182319b 4544static void signed_cons (int size)
6482c264 4545{
d182319b
JB		 4546 if (flag_code == CODE_64BIT)
4547 cons_sign = 1;
4548 cons (size);
4549 cons_sign = -1;
6482c264
NC		 4550}
4551
d182319b 4552#ifdef TE_PE
6482c264
NC		 4553static void
4554pe_directive_secrel (dummy)
4555 int dummy ATTRIBUTE_UNUSED;
4556{
4557 expressionS exp;
4558
4559 do
4560 {
4561 expression (&exp);
4562 if (exp.X_op == O_symbol)
4563 exp.X_op = O_secrel;
4564
4565 emit_expr (&exp, 4);
4566 }
4567 while (*input_line_pointer++ == ',');
4568
4569 input_line_pointer--;
4570 demand_empty_rest_of_line ();
4571}
6482c264
NC		 4572#endif
4573
252b5132 4574static int
70e41ade 4575i386_immediate (char *imm_start)
252b5132
RH		 4576{
4577 char *save_input_line_pointer;
f3c180ae 4578 char *gotfree_input_line;
252b5132 4579 segT exp_seg = 0;
47926f60 4580 expressionS *exp;
3956db08 4581 unsigned int types = ~0U;
252b5132
RH		 4582
4583 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4584 {
31b2323c
L		 4585 as_bad (_("at most %d immediate operands are allowed"),
4586 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4587 return 0;
4588 }
4589
4590 exp = &im_expressions[i.imm_operands++];
520dc8e8 4591 i.op[this_operand].imms = exp;
252b5132
RH		 4592
4593 if (is_space_char (*imm_start))
4594 ++imm_start;
4595
4596 save_input_line_pointer = input_line_pointer;
4597 input_line_pointer = imm_start;
4598
3956db08 4599 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4600 if (gotfree_input_line)
4601 input_line_pointer = gotfree_input_line;
252b5132
RH		 4602
4603 exp_seg = expression (exp);
4604
83183c0c 4605 SKIP_WHITESPACE ();
252b5132 4606 if (*input_line_pointer)
f3c180ae 4607 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4608
4609 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4610 if (gotfree_input_line)
4611 free (gotfree_input_line);
252b5132 4612
2daf4fd8 4613 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4614 {
47926f60 4615 /* Missing or bad expr becomes absolute 0. */
d0b47220 4616 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4617 imm_start);
252b5132
RH		 4618 exp->X_op = O_constant;
4619 exp->X_add_number = 0;
4620 exp->X_add_symbol = (symbolS *) 0;
4621 exp->X_op_symbol = (symbolS *) 0;
252b5132 4622 }
3e73aa7c 4623 else if (exp->X_op == O_constant)
252b5132 4624 {
47926f60 4625 /* Size it properly later. */
3e73aa7c
JH		 4626 i.types[this_operand] |= Imm64;
4627 /* If BFD64, sign extend val. */
4eed87de
AM		 4628 if (!use_rela_relocations
4629 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4630 exp->X_add_number
4631 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4632 }
4c63da97 4633#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4634 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4635 && exp_seg != absolute_section
47926f60 4636 && exp_seg != text_section
24eab124
AM		 4637 && exp_seg != data_section
4638 && exp_seg != bss_section
4639 && exp_seg != undefined_section
f86103b7 4640 && !bfd_is_com_section (exp_seg))
252b5132 4641 {
d0b47220 4642 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4643 return 0;
4644 }
4645#endif
bb8f5920
L		 4646 else if (!intel_syntax && exp->X_op == O_register)
4647 {
4648 as_bad (_("illegal immediate register operand %s"), imm_start);
4649 return 0;
4650 }
252b5132
RH		 4651 else
4652 {
4653 /* This is an address. The size of the address will be
24eab124 4654 determined later, depending on destination register,
3e73aa7c
JH		 4655 suffix, or the default for the section. */
4656 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4657 i.types[this_operand] &= types;
252b5132
RH		 4658 }
4659
4660 return 1;
4661}
4662
551c1ca1 4663static char *
e3bb37b5 4664i386_scale (char *scale)
252b5132 4665{
551c1ca1
AM		 4666 offsetT val;
4667 char *save = input_line_pointer;
252b5132 4668
551c1ca1
AM		 4669 input_line_pointer = scale;
4670 val = get_absolute_expression ();
4671
4672 switch (val)
252b5132 4673 {
551c1ca1 4674 case 1:
252b5132
RH		 4675 i.log2_scale_factor = 0;
4676 break;
551c1ca1 4677 case 2:
252b5132
RH		 4678 i.log2_scale_factor = 1;
4679 break;
551c1ca1 4680 case 4:
252b5132
RH		 4681 i.log2_scale_factor = 2;
4682 break;
551c1ca1 4683 case 8:
252b5132
RH		 4684 i.log2_scale_factor = 3;
4685 break;
4686 default:
a724f0f4
JB		 4687 {
4688 char sep = *input_line_pointer;
4689
4690 *input_line_pointer = '\0';
4691 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4692 scale);
4693 *input_line_pointer = sep;
4694 input_line_pointer = save;
4695 return NULL;
4696 }
252b5132 4697 }
29b0f896 4698 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4699 {
4700 as_warn (_("scale factor of %d without an index register"),
24eab124 4701 1 << i.log2_scale_factor);
252b5132
RH		 4702#if SCALE1_WHEN_NO_INDEX
4703 i.log2_scale_factor = 0;
4704#endif
4705 }
551c1ca1
AM		 4706 scale = input_line_pointer;
4707 input_line_pointer = save;
4708 return scale;
252b5132
RH		 4709}
4710
252b5132 4711static int
e3bb37b5 4712i386_displacement (char *disp_start, char *disp_end)
252b5132 4713{
29b0f896 4714 expressionS *exp;
252b5132
RH		 4715 segT exp_seg = 0;
4716 char *save_input_line_pointer;
f3c180ae 4717 char *gotfree_input_line;
e05278af 4718 int bigdisp, override;
3956db08 4719 unsigned int types = Disp;
252b5132 4720
31b2323c
L		 4721 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4722 {
4723 as_bad (_("at most %d displacement operands are allowed"),
4724 MAX_MEMORY_OPERANDS);
4725 return 0;
4726 }
4727
e05278af
JB		 4728 if ((i.types[this_operand] & JumpAbsolute)
4729 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4730 {
4731 bigdisp = Disp32;
4732 override = (i.prefix[ADDR_PREFIX] != 0);
4733 }
4734 else
4735 {
4736 /* For PC-relative branches, the width of the displacement
4737 is dependent upon data size, not address size. */
4738 bigdisp = 0;
4739 override = (i.prefix[DATA_PREFIX] != 0);
4740 }
3e73aa7c 4741 if (flag_code == CODE_64BIT)
7ecd2f8b 4742 {
e05278af 4743 if (!bigdisp)
64e74474
AM		 4744 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4745 ? Disp16
4746 : Disp32S | Disp32);
e05278af 4747 else if (!override)
3956db08 4748 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4749 }
e05278af
JB		 4750 else
4751 {
4752 if (!bigdisp)
4753 {
4754 if (!override)
4755 override = (i.suffix == (flag_code != CODE_16BIT
4756 ? WORD_MNEM_SUFFIX
4757 : LONG_MNEM_SUFFIX));
4758 bigdisp = Disp32;
4759 }
4760 if ((flag_code == CODE_16BIT) ^ override)
4761 bigdisp = Disp16;
4762 }
252b5132
RH		 4763 i.types[this_operand] |= bigdisp;
4764
4765 exp = &disp_expressions[i.disp_operands];
520dc8e8 4766 i.op[this_operand].disps = exp;
252b5132
RH		 4767 i.disp_operands++;
4768 save_input_line_pointer = input_line_pointer;
4769 input_line_pointer = disp_start;
4770 END_STRING_AND_SAVE (disp_end);
4771
4772#ifndef GCC_ASM_O_HACK
4773#define GCC_ASM_O_HACK 0
4774#endif
4775#if GCC_ASM_O_HACK
4776 END_STRING_AND_SAVE (disp_end + 1);
4777 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4778 && displacement_string_end[-1] == '+')
252b5132
RH		 4779 {
4780 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4781 constraint within gcc asm statements.
4782 For instance:
4783
4784 #define _set_tssldt_desc(n,addr,limit,type) \
4785 __asm__ __volatile__ ( \
4786 "movw %w2,%0\n\t" \
4787 "movw %w1,2+%0\n\t" \
4788 "rorl $16,%1\n\t" \
4789 "movb %b1,4+%0\n\t" \
4790 "movb %4,5+%0\n\t" \
4791 "movb $0,6+%0\n\t" \
4792 "movb %h1,7+%0\n\t" \
4793 "rorl $16,%1" \
4794 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4795
4796 This works great except that the output assembler ends
4797 up looking a bit weird if it turns out that there is
4798 no offset. You end up producing code that looks like:
4799
4800 #APP
4801 movw $235,(%eax)
4802 movw %dx,2+(%eax)
4803 rorl $16,%edx
4804 movb %dl,4+(%eax)
4805 movb $137,5+(%eax)
4806 movb $0,6+(%eax)
4807 movb %dh,7+(%eax)
4808 rorl $16,%edx
4809 #NO_APP
4810
47926f60 4811 So here we provide the missing zero. */
24eab124
AM		 4812
4813 *displacement_string_end = '0';
252b5132
RH		 4814 }
4815#endif
3956db08 4816 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4817 if (gotfree_input_line)
4818 input_line_pointer = gotfree_input_line;
252b5132 4819
24eab124 4820 exp_seg = expression (exp);
252b5132 4821
636c26b0
AM		 4822 SKIP_WHITESPACE ();
4823 if (*input_line_pointer)
4824 as_bad (_("junk `%s' after expression"), input_line_pointer);
4825#if GCC_ASM_O_HACK
4826 RESTORE_END_STRING (disp_end + 1);
4827#endif
4828 RESTORE_END_STRING (disp_end);
4829 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4830 if (gotfree_input_line)
4831 free (gotfree_input_line);
636c26b0 4832
24eab124
AM		 4833 /* We do this to make sure that the section symbol is in
4834 the symbol table. We will ultimately change the relocation
47926f60 4835 to be relative to the beginning of the section. */
1ae12ab7 4836 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4837 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4838 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4839 {
636c26b0
AM		 4840 if (exp->X_op != O_symbol)
4841 {
4842 as_bad (_("bad expression used with @%s"),
4843 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4844 ? "GOTPCREL"
4845 : "GOTOFF"));
4846 return 0;
4847 }
4848
e5cb08ac 4849 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4850 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4851 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4852 exp->X_op = O_subtract;
4853 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4854 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4855 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4856 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4857 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4858 else
29b0f896 4859 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4860 }
252b5132 4861
2daf4fd8
AM		 4862 if (exp->X_op == O_absent || exp->X_op == O_big)
4863 {
47926f60 4864 /* Missing or bad expr becomes absolute 0. */
d0b47220 4865 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4866 disp_start);
4867 exp->X_op = O_constant;
4868 exp->X_add_number = 0;
4869 exp->X_add_symbol = (symbolS *) 0;
4870 exp->X_op_symbol = (symbolS *) 0;
4871 }
4872
4c63da97 4873#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4874 if (exp->X_op != O_constant
45288df1 4875 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4876 && exp_seg != absolute_section
45288df1
AM		 4877 && exp_seg != text_section
4878 && exp_seg != data_section
4879 && exp_seg != bss_section
31312f95 4880 && exp_seg != undefined_section
f86103b7 4881 && !bfd_is_com_section (exp_seg))
24eab124 4882 {
d0b47220 4883 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4884 return 0;
4885 }
252b5132 4886#endif
3956db08
JB		 4887
4888 if (!(i.types[this_operand] & ~Disp))
4889 i.types[this_operand] &= types;
4890
252b5132
RH		 4891 return 1;
4892}
4893
eecb386c 4894/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4895 Return 1 on success, 0 on a failure. */
4896
252b5132 4897static int
e3bb37b5 4898i386_index_check (const char *operand_string)
252b5132 4899{
3e73aa7c 4900 int ok;
24eab124 4901#if INFER_ADDR_PREFIX
eecb386c
AM		 4902 int fudged = 0;
4903
24eab124
AM		 4904 tryprefix:
4905#endif
3e73aa7c 4906 ok = 1;
30123838
JB		 4907 if ((current_templates->start->cpu_flags & CpuSVME)
4908 && current_templates->end[-1].operand_types[0] == AnyMem)
4909 {
4910 /* Memory operands of SVME insns are special in that they only allow
4911 rAX as their memory address and ignore any segment override. */
4912 unsigned RegXX;
4913
4914 /* SKINIT is even more restrictive: it always requires EAX. */
4915 if (strcmp (current_templates->start->name, "skinit") == 0)
4916 RegXX = Reg32;
4917 else if (flag_code == CODE_64BIT)
4918 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4919 else
64e74474
AM		 4920 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4921 ? Reg16
4922 : Reg32);
30123838
JB		 4923 if (!i.base_reg
4924 || !(i.base_reg->reg_type & Acc)
4925 || !(i.base_reg->reg_type & RegXX)
4926 || i.index_reg
4927 || (i.types[0] & Disp))
4928 ok = 0;
4929 }
4930 else if (flag_code == CODE_64BIT)
64e74474
AM		 4931 {
4932 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4933
4934 if ((i.base_reg
4935 && ((i.base_reg->reg_type & RegXX) == 0)
4936 && (i.base_reg->reg_type != BaseIndex
4937 || i.index_reg))
4938 || (i.index_reg
4939 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4940 != (RegXX | BaseIndex))))
4941 ok = 0;
3e73aa7c
JH		 4942 }
4943 else
4944 {
4945 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4946 {
4947 /* 16bit checks. */
4948 if ((i.base_reg
29b0f896
AM		 4949 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4950 != (Reg16 | BaseIndex)))
3e73aa7c 4951 || (i.index_reg
29b0f896
AM		 4952 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4953 != (Reg16 | BaseIndex))
4954 || !(i.base_reg
4955 && i.base_reg->reg_num < 6
4956 && i.index_reg->reg_num >= 6
4957 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4958 ok = 0;
4959 }
4960 else
e5cb08ac 4961 {
3e73aa7c
JH		 4962 /* 32bit checks. */
4963 if ((i.base_reg
4964 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4965 || (i.index_reg
29b0f896
AM		 4966 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4967 != (Reg32 | BaseIndex))))
e5cb08ac 4968 ok = 0;
3e73aa7c
JH		 4969 }
4970 }
4971 if (!ok)
24eab124
AM		 4972 {
4973#if INFER_ADDR_PREFIX
20f0a1fc 4974 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4975 {
4976 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4977 i.prefixes += 1;
b23bac36
AM		 4978 /* Change the size of any displacement too. At most one of
4979 Disp16 or Disp32 is set.
4980 FIXME. There doesn't seem to be any real need for separate
4981 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4982 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 4983 if (flag_code != CODE_64BIT
4984 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4985 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4986 fudged = 1;
24eab124
AM		 4987 goto tryprefix;
4988 }
eecb386c
AM		 4989 if (fudged)
4990 as_bad (_("`%s' is not a valid base/index expression"),
4991 operand_string);
4992 else
c388dee8 4993#endif
eecb386c
AM		 4994 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4995 operand_string,
3e73aa7c 4996 flag_code_names[flag_code]);
24eab124 4997 }
20f0a1fc 4998 return ok;
24eab124 4999}
252b5132 5000
252b5132 5001/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 5002 on error. */
252b5132 5003
252b5132 5004static int
e3bb37b5 5005i386_operand (char *operand_string)
252b5132 5006{
af6bdddf
AM		 5007 const reg_entry *r;
5008 char *end_op;
24eab124 5009 char *op_string = operand_string;
252b5132 5010
24eab124 5011 if (is_space_char (*op_string))
252b5132
RH		 5012 ++op_string;
5013
24eab124 5014 /* We check for an absolute prefix (differentiating,
47926f60 5015 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5016 if (*op_string == ABSOLUTE_PREFIX)
5017 {
5018 ++op_string;
5019 if (is_space_char (*op_string))
5020 ++op_string;
5021 i.types[this_operand] |= JumpAbsolute;
5022 }
252b5132 5023
47926f60 5024 /* Check if operand is a register. */
4d1bb795 5025 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5026 {
24eab124
AM		 5027 /* Check for a segment override by searching for ':' after a
5028 segment register. */
5029 op_string = end_op;
5030 if (is_space_char (*op_string))
5031 ++op_string;
5032 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
5033 {
5034 switch (r->reg_num)
5035 {
5036 case 0:
5037 i.seg[i.mem_operands] = &es;
5038 break;
5039 case 1:
5040 i.seg[i.mem_operands] = &cs;
5041 break;
5042 case 2:
5043 i.seg[i.mem_operands] = &ss;
5044 break;
5045 case 3:
5046 i.seg[i.mem_operands] = &ds;
5047 break;
5048 case 4:
5049 i.seg[i.mem_operands] = &fs;
5050 break;
5051 case 5:
5052 i.seg[i.mem_operands] = &gs;
5053 break;
5054 }
252b5132 5055
24eab124 5056 /* Skip the ':' and whitespace. */
252b5132
RH		 5057 ++op_string;
5058 if (is_space_char (*op_string))
24eab124 5059 ++op_string;
252b5132 5060
24eab124
AM		 5061 if (!is_digit_char (*op_string)
5062 && !is_identifier_char (*op_string)
5063 && *op_string != '('
5064 && *op_string != ABSOLUTE_PREFIX)
5065 {
5066 as_bad (_("bad memory operand `%s'"), op_string);
5067 return 0;
5068 }
47926f60 5069 /* Handle case of %es:*foo. */
24eab124
AM		 5070 if (*op_string == ABSOLUTE_PREFIX)
5071 {
5072 ++op_string;
5073 if (is_space_char (*op_string))
5074 ++op_string;
5075 i.types[this_operand] |= JumpAbsolute;
5076 }
5077 goto do_memory_reference;
5078 }
5079 if (*op_string)
5080 {
d0b47220 5081 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5082 return 0;
5083 }
5084 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5085 i.op[this_operand].regs = r;
24eab124
AM		 5086 i.reg_operands++;
5087 }
af6bdddf
AM		 5088 else if (*op_string == REGISTER_PREFIX)
5089 {
5090 as_bad (_("bad register name `%s'"), op_string);
5091 return 0;
5092 }
24eab124 5093 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5094 {
24eab124
AM		 5095 ++op_string;
5096 if (i.types[this_operand] & JumpAbsolute)
5097 {
d0b47220 5098 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5099 return 0;
5100 }
5101 if (!i386_immediate (op_string))
5102 return 0;
5103 }
5104 else if (is_digit_char (*op_string)
5105 || is_identifier_char (*op_string)
e5cb08ac 5106 || *op_string == '(')
24eab124 5107 {
47926f60 5108 /* This is a memory reference of some sort. */
af6bdddf 5109 char *base_string;
252b5132 5110
47926f60 5111 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5112 char *displacement_string_start;
5113 char *displacement_string_end;
252b5132 5114
24eab124 5115 do_memory_reference:
24eab124
AM		 5116 if ((i.mem_operands == 1
5117 && (current_templates->start->opcode_modifier & IsString) == 0)
5118 || i.mem_operands == 2)
5119 {
5120 as_bad (_("too many memory references for `%s'"),
5121 current_templates->start->name);
5122 return 0;
5123 }
252b5132 5124
24eab124
AM		 5125 /* Check for base index form. We detect the base index form by
5126 looking for an ')' at the end of the operand, searching
5127 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5128 after the '('. */
af6bdddf 5129 base_string = op_string + strlen (op_string);
c3332e24 5130
af6bdddf
AM		 5131 --base_string;
5132 if (is_space_char (*base_string))
5133 --base_string;
252b5132 5134
47926f60 5135 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5136 displacement_string_start = op_string;
5137 displacement_string_end = base_string + 1;
252b5132 5138
24eab124
AM		 5139 if (*base_string == ')')
5140 {
af6bdddf 5141 char *temp_string;
24eab124
AM		 5142 unsigned int parens_balanced = 1;
5143 /* We've already checked that the number of left & right ()'s are
47926f60 5144 equal, so this loop will not be infinite. */
24eab124
AM		 5145 do
5146 {
5147 base_string--;
5148 if (*base_string == ')')
5149 parens_balanced++;
5150 if (*base_string == '(')
5151 parens_balanced--;
5152 }
5153 while (parens_balanced);
c3332e24 5154
af6bdddf 5155 temp_string = base_string;
c3332e24 5156
24eab124 5157 /* Skip past '(' and whitespace. */
252b5132
RH		 5158 ++base_string;
5159 if (is_space_char (*base_string))
24eab124 5160 ++base_string;
252b5132 5161
af6bdddf 5162 if (*base_string == ','
4eed87de
AM		 5163 || ((i.base_reg = parse_register (base_string, &end_op))
5164 != NULL))
252b5132 5165 {
af6bdddf 5166 displacement_string_end = temp_string;
252b5132 5167
af6bdddf 5168 i.types[this_operand] |= BaseIndex;
252b5132 5169
af6bdddf 5170 if (i.base_reg)
24eab124 5171 {
24eab124
AM		 5172 base_string = end_op;
5173 if (is_space_char (*base_string))
5174 ++base_string;
af6bdddf
AM		 5175 }
5176
5177 /* There may be an index reg or scale factor here. */
5178 if (*base_string == ',')
5179 {
5180 ++base_string;
5181 if (is_space_char (*base_string))
5182 ++base_string;
5183
4eed87de
AM		 5184 if ((i.index_reg = parse_register (base_string, &end_op))
5185 != NULL)
24eab124 5186 {
af6bdddf 5187 base_string = end_op;
24eab124
AM		 5188 if (is_space_char (*base_string))
5189 ++base_string;
af6bdddf
AM		 5190 if (*base_string == ',')
5191 {
5192 ++base_string;
5193 if (is_space_char (*base_string))
5194 ++base_string;
5195 }
e5cb08ac 5196 else if (*base_string != ')')
af6bdddf 5197 {
4eed87de
AM		 5198 as_bad (_("expecting `,' or `)' "
5199 "after index register in `%s'"),
af6bdddf
AM		 5200 operand_string);
5201 return 0;
5202 }
24eab124 5203 }
af6bdddf 5204 else if (*base_string == REGISTER_PREFIX)
24eab124 5205 {
af6bdddf 5206 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5207 return 0;
5208 }
252b5132 5209
47926f60 5210 /* Check for scale factor. */
551c1ca1 5211 if (*base_string != ')')
af6bdddf 5212 {
551c1ca1
AM		 5213 char *end_scale = i386_scale (base_string);
5214
5215 if (!end_scale)
af6bdddf 5216 return 0;
24eab124 5217
551c1ca1 5218 base_string = end_scale;
af6bdddf
AM		 5219 if (is_space_char (*base_string))
5220 ++base_string;
5221 if (*base_string != ')')
5222 {
4eed87de
AM		 5223 as_bad (_("expecting `)' "
5224 "after scale factor in `%s'"),
af6bdddf
AM		 5225 operand_string);
5226 return 0;
5227 }
5228 }
5229 else if (!i.index_reg)
24eab124 5230 {
4eed87de
AM		 5231 as_bad (_("expecting index register or scale factor "
5232 "after `,'; got '%c'"),
af6bdddf 5233 *base_string);
24eab124
AM		 5234 return 0;
5235 }
5236 }
af6bdddf 5237 else if (*base_string != ')')
24eab124 5238 {
4eed87de
AM		 5239 as_bad (_("expecting `,' or `)' "
5240 "after base register in `%s'"),
af6bdddf 5241 operand_string);
24eab124
AM		 5242 return 0;
5243 }
c3332e24 5244 }
af6bdddf 5245 else if (*base_string == REGISTER_PREFIX)
c3332e24 5246 {
af6bdddf 5247 as_bad (_("bad register name `%s'"), base_string);
24eab124 5248 return 0;
c3332e24 5249 }
24eab124
AM		 5250 }
5251
5252 /* If there's an expression beginning the operand, parse it,
5253 assuming displacement_string_start and
5254 displacement_string_end are meaningful. */
5255 if (displacement_string_start != displacement_string_end)
5256 {
5257 if (!i386_displacement (displacement_string_start,
5258 displacement_string_end))
5259 return 0;
5260 }
5261
5262 /* Special case for (%dx) while doing input/output op. */
5263 if (i.base_reg
5264 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5265 && i.index_reg == 0
5266 && i.log2_scale_factor == 0
5267 && i.seg[i.mem_operands] == 0
5268 && (i.types[this_operand] & Disp) == 0)
5269 {
5270 i.types[this_operand] = InOutPortReg;
5271 return 1;
5272 }
5273
eecb386c
AM		 5274 if (i386_index_check (operand_string) == 0)
5275 return 0;
24eab124
AM		 5276 i.mem_operands++;
5277 }
5278 else
ce8a8b2f
AM		 5279 {
5280 /* It's not a memory operand; argh! */
24eab124
AM		 5281 as_bad (_("invalid char %s beginning operand %d `%s'"),
5282 output_invalid (*op_string),
5283 this_operand + 1,
5284 op_string);
5285 return 0;
5286 }
47926f60 5287 return 1; /* Normal return. */
252b5132
RH		 5288}
5289\f
ee7fcc42
AM		 5290/* md_estimate_size_before_relax()
5291
5292 Called just before relax() for rs_machine_dependent frags. The x86
5293 assembler uses these frags to handle variable size jump
5294 instructions.
5295
5296 Any symbol that is now undefined will not become defined.
5297 Return the correct fr_subtype in the frag.
5298 Return the initial "guess for variable size of frag" to caller.
5299 The guess is actually the growth beyond the fixed part. Whatever
5300 we do to grow the fixed or variable part contributes to our
5301 returned value. */
5302
252b5132
RH		 5303int
5304md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5305 fragS *fragP;
5306 segT segment;
252b5132 5307{
252b5132 5308 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5309 check for un-relaxable symbols. On an ELF system, we can't relax
5310 an externally visible symbol, because it may be overridden by a
5311 shared library. */
5312 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5313#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5314 || (IS_ELF
31312f95
AM		 5315 && (S_IS_EXTERNAL (fragP->fr_symbol)
5316 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5317#endif
5318 )
252b5132 5319 {
b98ef147
AM		 5320 /* Symbol is undefined in this segment, or we need to keep a
5321 reloc so that weak symbols can be overridden. */
5322 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5323 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5324 unsigned char *opcode;
5325 int old_fr_fix;
f6af82bd 5326
ee7fcc42
AM		 5327 if (fragP->fr_var != NO_RELOC)
5328 reloc_type = fragP->fr_var;
b98ef147 5329 else if (size == 2)
f6af82bd
AM		 5330 reloc_type = BFD_RELOC_16_PCREL;
5331 else
5332 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5333
ee7fcc42
AM		 5334 old_fr_fix = fragP->fr_fix;
5335 opcode = (unsigned char *) fragP->fr_opcode;
5336
fddf5b5b 5337 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5338 {
fddf5b5b
AM		 5339 case UNCOND_JUMP:
5340 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5341 opcode[0] = 0xe9;
252b5132 5342 fragP->fr_fix += size;
062cd5e7
AS		 5343 fix_new (fragP, old_fr_fix, size,
5344 fragP->fr_symbol,
5345 fragP->fr_offset, 1,
5346 reloc_type);
252b5132
RH		 5347 break;
5348
fddf5b5b 5349 case COND_JUMP86:
412167cb
AM		 5350 if (size == 2
5351 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5352 {
5353 /* Negate the condition, and branch past an
5354 unconditional jump. */
5355 opcode[0] ^= 1;
5356 opcode[1] = 3;
5357 /* Insert an unconditional jump. */
5358 opcode[2] = 0xe9;
5359 /* We added two extra opcode bytes, and have a two byte
5360 offset. */
5361 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5362 fix_new (fragP, old_fr_fix + 2, 2,
5363 fragP->fr_symbol,
5364 fragP->fr_offset, 1,
5365 reloc_type);
fddf5b5b
AM		 5366 break;
5367 }
5368 /* Fall through. */
5369
5370 case COND_JUMP:
412167cb
AM		 5371 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5372 {
3e02c1cc
AM		 5373 fixS *fixP;
5374
412167cb 5375 fragP->fr_fix += 1;
3e02c1cc
AM		 5376 fixP = fix_new (fragP, old_fr_fix, 1,
5377 fragP->fr_symbol,
5378 fragP->fr_offset, 1,
5379 BFD_RELOC_8_PCREL);
5380 fixP->fx_signed = 1;
412167cb
AM		 5381 break;
5382 }
93c2a809 5383
24eab124 5384 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5385 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5386 opcode[1] = opcode[0] + 0x10;
f6af82bd 5387 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5388 /* We've added an opcode byte. */
5389 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5390 fix_new (fragP, old_fr_fix + 1, size,
5391 fragP->fr_symbol,
5392 fragP->fr_offset, 1,
5393 reloc_type);
252b5132 5394 break;
fddf5b5b
AM		 5395
5396 default:
5397 BAD_CASE (fragP->fr_subtype);
5398 break;
252b5132
RH		 5399 }
5400 frag_wane (fragP);
ee7fcc42 5401 return fragP->fr_fix - old_fr_fix;
252b5132 5402 }
93c2a809 5403
93c2a809
AM		 5404 /* Guess size depending on current relax state. Initially the relax
5405 state will correspond to a short jump and we return 1, because
5406 the variable part of the frag (the branch offset) is one byte
5407 long. However, we can relax a section more than once and in that
5408 case we must either set fr_subtype back to the unrelaxed state,
5409 or return the value for the appropriate branch. */
5410 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5411}
5412
47926f60
KH		 5413/* Called after relax() is finished.
5414
5415 In: Address of frag.
5416 fr_type == rs_machine_dependent.
5417 fr_subtype is what the address relaxed to.
5418
5419 Out: Any fixSs and constants are set up.
5420 Caller will turn frag into a ".space 0". */
5421
252b5132
RH		 5422void
5423md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5424 bfd *abfd ATTRIBUTE_UNUSED;
5425 segT sec ATTRIBUTE_UNUSED;
29b0f896 5426 fragS *fragP;
252b5132 5427{
29b0f896 5428 unsigned char *opcode;
252b5132 5429 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5430 offsetT target_address;
5431 offsetT opcode_address;
252b5132 5432 unsigned int extension = 0;
847f7ad4 5433 offsetT displacement_from_opcode_start;
252b5132
RH		 5434
5435 opcode = (unsigned char *) fragP->fr_opcode;
5436
47926f60 5437 /* Address we want to reach in file space. */
252b5132 5438 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5439
47926f60 5440 /* Address opcode resides at in file space. */
252b5132
RH		 5441 opcode_address = fragP->fr_address + fragP->fr_fix;
5442
47926f60 5443 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5444 displacement_from_opcode_start = target_address - opcode_address;
5445
fddf5b5b 5446 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5447 {
47926f60
KH		 5448 /* Don't have to change opcode. */
5449 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5450 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5451 }
5452 else
5453 {
5454 if (no_cond_jump_promotion
5455 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5456 as_warn_where (fragP->fr_file, fragP->fr_line,
5457 _("long jump required"));
252b5132 5458
fddf5b5b
AM		 5459 switch (fragP->fr_subtype)
5460 {
5461 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5462 extension = 4; /* 1 opcode + 4 displacement */
5463 opcode[0] = 0xe9;
5464 where_to_put_displacement = &opcode[1];
5465 break;
252b5132 5466
fddf5b5b
AM		 5467 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5468 extension = 2; /* 1 opcode + 2 displacement */
5469 opcode[0] = 0xe9;
5470 where_to_put_displacement = &opcode[1];
5471 break;
252b5132 5472
fddf5b5b
AM		 5473 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5474 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5475 extension = 5; /* 2 opcode + 4 displacement */
5476 opcode[1] = opcode[0] + 0x10;
5477 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5478 where_to_put_displacement = &opcode[2];
5479 break;
252b5132 5480
fddf5b5b
AM		 5481 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5482 extension = 3; /* 2 opcode + 2 displacement */
5483 opcode[1] = opcode[0] + 0x10;
5484 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5485 where_to_put_displacement = &opcode[2];
5486 break;
252b5132 5487
fddf5b5b
AM		 5488 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5489 extension = 4;
5490 opcode[0] ^= 1;
5491 opcode[1] = 3;
5492 opcode[2] = 0xe9;
5493 where_to_put_displacement = &opcode[3];
5494 break;
5495
5496 default:
5497 BAD_CASE (fragP->fr_subtype);
5498 break;
5499 }
252b5132 5500 }
fddf5b5b 5501
7b81dfbb
AJ		 5502 /* If size if less then four we are sure that the operand fits,
5503 but if it's 4, then it could be that the displacement is larger
5504 then -/+ 2GB. */
5505 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5506 && object_64bit
5507 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5508 + ((addressT) 1 << 31))
5509 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5510 {
5511 as_bad_where (fragP->fr_file, fragP->fr_line,
5512 _("jump target out of range"));
5513 /* Make us emit 0. */
5514 displacement_from_opcode_start = extension;
5515 }
47926f60 5516 /* Now put displacement after opcode. */
252b5132
RH		 5517 md_number_to_chars ((char *) where_to_put_displacement,
5518 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5519 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5520 fragP->fr_fix += extension;
5521}
5522\f
47926f60
KH		 5523/* Size of byte displacement jmp. */
5524int md_short_jump_size = 2;
5525
5526/* Size of dword displacement jmp. */
5527int md_long_jump_size = 5;
252b5132 5528
252b5132
RH		 5529void
5530md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5531 char *ptr;
5532 addressT from_addr, to_addr;
ab9da554
ILT		 5533 fragS *frag ATTRIBUTE_UNUSED;
5534 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5535{
847f7ad4 5536 offsetT offset;
252b5132
RH		 5537
5538 offset = to_addr - (from_addr + 2);
47926f60
KH		 5539 /* Opcode for byte-disp jump. */
5540 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5541 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5542}
5543
5544void
5545md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5546 char *ptr;
5547 addressT from_addr, to_addr;
a38cf1db
AM		 5548 fragS *frag ATTRIBUTE_UNUSED;
5549 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5550{
847f7ad4 5551 offsetT offset;
252b5132 5552
a38cf1db
AM		 5553 offset = to_addr - (from_addr + 5);
5554 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5555 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5556}
5557\f
5558/* Apply a fixup (fixS) to segment data, once it has been determined
5559 by our caller that we have all the info we need to fix it up.
5560
5561 On the 386, immediates, displacements, and data pointers are all in
5562 the same (little-endian) format, so we don't need to care about which
5563 we are handling. */
5564
94f592af 5565void
55cf6793 5566md_apply_fix (fixP, valP, seg)
47926f60
KH		 5567 /* The fix we're to put in. */
5568 fixS *fixP;
47926f60 5569 /* Pointer to the value of the bits. */
c6682705 5570 valueT *valP;
47926f60
KH		 5571 /* Segment fix is from. */
5572 segT seg ATTRIBUTE_UNUSED;
252b5132 5573{
94f592af 5574 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5575 valueT value = *valP;
252b5132 5576
f86103b7 5577#if !defined (TE_Mach)
93382f6d
AM		 5578 if (fixP->fx_pcrel)
5579 {
5580 switch (fixP->fx_r_type)
5581 {
5865bb77
ILT		 5582 default:
5583 break;
5584
d6ab8113
JB		 5585 case BFD_RELOC_64:
5586 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5587 break;
93382f6d 5588 case BFD_RELOC_32:
ae8887b5 5589 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5590 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5591 break;
5592 case BFD_RELOC_16:
5593 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5594 break;
5595 case BFD_RELOC_8:
5596 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5597 break;
5598 }
5599 }
252b5132 5600
a161fe53 5601 if (fixP->fx_addsy != NULL
31312f95 5602 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5603 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5604 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5605 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5606 && !use_rela_relocations)
252b5132 5607 {
31312f95
AM		 5608 /* This is a hack. There should be a better way to handle this.
5609 This covers for the fact that bfd_install_relocation will
5610 subtract the current location (for partial_inplace, PC relative
5611 relocations); see more below. */
252b5132 5612#ifndef OBJ_AOUT
718ddfc0 5613 if (IS_ELF
252b5132
RH		 5614#ifdef TE_PE
5615 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5616#endif
5617 )
5618 value += fixP->fx_where + fixP->fx_frag->fr_address;
5619#endif
5620#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5621 if (IS_ELF)
252b5132 5622 {
6539b54b 5623 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5624
6539b54b 5625 if ((sym_seg == seg
2f66722d 5626 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5627 && sym_seg != absolute_section))
ae6063d4 5628 && !generic_force_reloc (fixP))
2f66722d
AM		 5629 {
5630 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5631 bfd_install_relocation subtracts them out again. I think
5632 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5633 it. FIXME. */
5634 value += fixP->fx_where + fixP->fx_frag->fr_address;
5635 }
252b5132
RH		 5636 }
5637#endif
5638#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5639 /* For some reason, the PE format does not store a
5640 section address offset for a PC relative symbol. */
5641 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5642 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5643 value += md_pcrel_from (fixP);
5644#endif
5645 }
5646
5647 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5648 and we must not disappoint it. */
252b5132 5649#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5650 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5651 switch (fixP->fx_r_type)
5652 {
5653 case BFD_RELOC_386_PLT32:
3e73aa7c 5654 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5655 /* Make the jump instruction point to the address of the operand. At
5656 runtime we merely add the offset to the actual PLT entry. */
5657 value = -4;
5658 break;
31312f95 5659
13ae64f3
JJ		 5660 case BFD_RELOC_386_TLS_GD:
5661 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5662 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5663 case BFD_RELOC_386_TLS_IE:
5664 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5665 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5666 case BFD_RELOC_X86_64_TLSGD:
5667 case BFD_RELOC_X86_64_TLSLD:
5668 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5669 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5670 value = 0; /* Fully resolved at runtime. No addend. */
5671 /* Fallthrough */
5672 case BFD_RELOC_386_TLS_LE:
5673 case BFD_RELOC_386_TLS_LDO_32:
5674 case BFD_RELOC_386_TLS_LE_32:
5675 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5676 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5677 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5678 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5679 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5680 break;
5681
67a4f2b7
AO		 5682 case BFD_RELOC_386_TLS_DESC_CALL:
5683 case BFD_RELOC_X86_64_TLSDESC_CALL:
5684 value = 0; /* Fully resolved at runtime. No addend. */
5685 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5686 fixP->fx_done = 0;
5687 return;
5688
00f7efb6
JJ		 5689 case BFD_RELOC_386_GOT32:
5690 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5691 value = 0; /* Fully resolved at runtime. No addend. */
5692 break;
47926f60
KH		 5693
5694 case BFD_RELOC_VTABLE_INHERIT:
5695 case BFD_RELOC_VTABLE_ENTRY:
5696 fixP->fx_done = 0;
94f592af 5697 return;
47926f60
KH		 5698
5699 default:
5700 break;
5701 }
5702#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5703 *valP = value;
f86103b7 5704#endif /* !defined (TE_Mach) */
3e73aa7c 5705
3e73aa7c 5706 /* Are we finished with this relocation now? */
c6682705 5707 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5708 fixP->fx_done = 1;
5709 else if (use_rela_relocations)
5710 {
5711 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5712 /* Remember value for tc_gen_reloc. */
5713 fixP->fx_addnumber = value;
3e73aa7c
JH		 5714 value = 0;
5715 }
f86103b7 5716
94f592af 5717 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5718}
252b5132 5719\f
252b5132
RH		 5720#define MAX_LITTLENUMS 6
5721
47926f60
KH		 5722/* Turn the string pointed to by litP into a floating point constant
5723 of type TYPE, and emit the appropriate bytes. The number of
5724 LITTLENUMS emitted is stored in *SIZEP. An error message is
5725 returned, or NULL on OK. */
5726
252b5132
RH		 5727char *
5728md_atof (type, litP, sizeP)
2ab9b79e 5729 int type;
252b5132
RH		 5730 char *litP;
5731 int *sizeP;
5732{
5733 int prec;
5734 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5735 LITTLENUM_TYPE *wordP;
5736 char *t;
5737
5738 switch (type)
5739 {
5740 case 'f':
5741 case 'F':
5742 prec = 2;
5743 break;
5744
5745 case 'd':
5746 case 'D':
5747 prec = 4;
5748 break;
5749
5750 case 'x':
5751 case 'X':
5752 prec = 5;
5753 break;
5754
5755 default:
5756 *sizeP = 0;
5757 return _("Bad call to md_atof ()");
5758 }
5759 t = atof_ieee (input_line_pointer, type, words);
5760 if (t)
5761 input_line_pointer = t;
5762
5763 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5764 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5765 the bigendian 386. */
5766 for (wordP = words + prec - 1; prec--;)
5767 {
5768 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5769 litP += sizeof (LITTLENUM_TYPE);
5770 }
5771 return 0;
5772}
5773\f
2d545b82 5774static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5775
252b5132 5776static char *
e3bb37b5 5777output_invalid (int c)
252b5132 5778{
3882b010 5779 if (ISPRINT (c))
f9f21a03
L		 5780 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5781 "'%c'", c);
252b5132 5782 else
f9f21a03 5783 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5784 "(0x%x)", (unsigned char) c);
252b5132
RH		 5785 return output_invalid_buf;
5786}
5787
af6bdddf 5788/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5789
5790static const reg_entry *
4d1bb795 5791parse_real_register (char *reg_string, char **end_op)
252b5132 5792{
af6bdddf
AM		 5793 char *s = reg_string;
5794 char *p;
252b5132
RH		 5795 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5796 const reg_entry *r;
5797
5798 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5799 if (*s == REGISTER_PREFIX)
5800 ++s;
5801
5802 if (is_space_char (*s))
5803 ++s;
5804
5805 p = reg_name_given;
af6bdddf 5806 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5807 {
5808 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5809 return (const reg_entry *) NULL;
5810 s++;
252b5132
RH		 5811 }
5812
6588847e
DN		 5813 /* For naked regs, make sure that we are not dealing with an identifier.
5814 This prevents confusing an identifier like `eax_var' with register
5815 `eax'. */
5816 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5817 return (const reg_entry *) NULL;
5818
af6bdddf 5819 *end_op = s;
252b5132
RH		 5820
5821 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5822
5f47d35b 5823 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5824 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5825 {
5f47d35b
AM		 5826 if (is_space_char (*s))
5827 ++s;
5828 if (*s == '(')
5829 {
af6bdddf 5830 ++s;
5f47d35b
AM		 5831 if (is_space_char (*s))
5832 ++s;
5833 if (*s >= '0' && *s <= '7')
5834 {
db557034 5835 int fpr = *s - '0';
af6bdddf 5836 ++s;
5f47d35b
AM		 5837 if (is_space_char (*s))
5838 ++s;
5839 if (*s == ')')
5840 {
5841 *end_op = s + 1;
db557034
AM		 5842 r = hash_find (reg_hash, "st(0)");
5843 know (r);
5844 return r + fpr;
5f47d35b 5845 }
5f47d35b 5846 }
47926f60 5847 /* We have "%st(" then garbage. */
5f47d35b
AM		 5848 return (const reg_entry *) NULL;
5849 }
5850 }
5851
1ae00879 5852 if (r != NULL
20f0a1fc 5853 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5854 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5855 && flag_code != CODE_64BIT)
20f0a1fc 5856 return (const reg_entry *) NULL;
1ae00879 5857
252b5132
RH		 5858 return r;
5859}
4d1bb795
JB		 5860
5861/* REG_STRING starts *before* REGISTER_PREFIX. */
5862
5863static const reg_entry *
5864parse_register (char *reg_string, char **end_op)
5865{
5866 const reg_entry *r;
5867
5868 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5869 r = parse_real_register (reg_string, end_op);
5870 else
5871 r = NULL;
5872 if (!r)
5873 {
5874 char *save = input_line_pointer;
5875 char c;
5876 symbolS *symbolP;
5877
5878 input_line_pointer = reg_string;
5879 c = get_symbol_end ();
5880 symbolP = symbol_find (reg_string);
5881 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5882 {
5883 const expressionS *e = symbol_get_value_expression (symbolP);
5884
5885 know (e->X_op == O_register);
4eed87de 5886 know (e->X_add_number >= 0
c3fe08fa 5887 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5888 r = i386_regtab + e->X_add_number;
5889 *end_op = input_line_pointer;
5890 }
5891 *input_line_pointer = c;
5892 input_line_pointer = save;
5893 }
5894 return r;
5895}
5896
5897int
5898i386_parse_name (char *name, expressionS *e, char *nextcharP)
5899{
5900 const reg_entry *r;
5901 char *end = input_line_pointer;
5902
5903 *end = *nextcharP;
5904 r = parse_register (name, &input_line_pointer);
5905 if (r && end <= input_line_pointer)
5906 {
5907 *nextcharP = *input_line_pointer;
5908 *input_line_pointer = 0;
5909 e->X_op = O_register;
5910 e->X_add_number = r - i386_regtab;
5911 return 1;
5912 }
5913 input_line_pointer = end;
5914 *end = 0;
5915 return 0;
5916}
5917
5918void
5919md_operand (expressionS *e)
5920{
5921 if (*input_line_pointer == REGISTER_PREFIX)
5922 {
5923 char *end;
5924 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5925
5926 if (r)
5927 {
5928 e->X_op = O_register;
5929 e->X_add_number = r - i386_regtab;
5930 input_line_pointer = end;
5931 }
5932 }
5933}
5934
252b5132 5935\f
4cc782b5 5936#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5937const char *md_shortopts = "kVQ:sqn";
252b5132 5938#else
12b55ccc 5939const char *md_shortopts = "qn";
252b5132 5940#endif
6e0b89ee 5941
3e73aa7c 5942#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5943#define OPTION_64 (OPTION_MD_BASE + 1)
5944#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5945#define OPTION_MARCH (OPTION_MD_BASE + 3)
5946#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5947
99ad8390
NC		 5948struct option md_longopts[] =
5949{
3e73aa7c 5950 {"32", no_argument, NULL, OPTION_32},
99ad8390 5951#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5952 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5953#endif
b3b91714 5954 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5955 {"march", required_argument, NULL, OPTION_MARCH},
5956 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5957 {NULL, no_argument, NULL, 0}
5958};
5959size_t md_longopts_size = sizeof (md_longopts);
5960
5961int
9103f4f4 5962md_parse_option (int c, char *arg)
252b5132 5963{
9103f4f4
L		 5964 unsigned int i;
5965
252b5132
RH		 5966 switch (c)
5967 {
12b55ccc
L		 5968 case 'n':
5969 optimize_align_code = 0;
5970 break;
5971
a38cf1db
AM		 5972 case 'q':
5973 quiet_warnings = 1;
252b5132
RH		 5974 break;
5975
5976#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5977 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5978 should be emitted or not. FIXME: Not implemented. */
5979 case 'Q':
252b5132
RH		 5980 break;
5981
5982 /* -V: SVR4 argument to print version ID. */
5983 case 'V':
5984 print_version_id ();
5985 break;
5986
a38cf1db
AM		 5987 /* -k: Ignore for FreeBSD compatibility. */
5988 case 'k':
252b5132 5989 break;
4cc782b5
ILT		 5990
5991 case 's':
5992 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5993 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5994 break;
99ad8390
NC		 5995#endif
5996#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5997 case OPTION_64:
5998 {
5999 const char **list, **l;
6000
3e73aa7c
JH		 6001 list = bfd_target_list ();
6002 for (l = list; *l != NULL; l++)
8620418b 6003 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 6004 || strcmp (*l, "coff-x86-64") == 0
6005 || strcmp (*l, "pe-x86-64") == 0
6006 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 6007 {
6008 default_arch = "x86_64";
6009 break;
6010 }
3e73aa7c 6011 if (*l == NULL)
6e0b89ee 6012 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 6013 free (list);
6014 }
6015 break;
6016#endif
252b5132 6017
6e0b89ee
AM		 6018 case OPTION_32:
6019 default_arch = "i386";
6020 break;
6021
b3b91714
AM		 6022 case OPTION_DIVIDE:
6023#ifdef SVR4_COMMENT_CHARS
6024 {
6025 char *n, *t;
6026 const char *s;
6027
6028 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6029 t = n;
6030 for (s = i386_comment_chars; *s != '\0'; s++)
6031 if (*s != '/')
6032 *t++ = *s;
6033 *t = '\0';
6034 i386_comment_chars = n;
6035 }
6036#endif
6037 break;
6038
9103f4f4
L		 6039 case OPTION_MARCH:
6040 if (*arg == '.')
6041 as_fatal (_("Invalid -march= option: `%s'"), arg);
6042 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6043 {
6044 if (strcmp (arg, cpu_arch [i].name) == 0)
6045 {
ccc9c027 6046 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6047 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6048 if (!cpu_arch_tune_set)
6049 {
6050 cpu_arch_tune = cpu_arch_isa;
6051 cpu_arch_tune_flags = cpu_arch_isa_flags;
6052 }
9103f4f4
L		 6053 break;
6054 }
6055 }
6056 if (i >= ARRAY_SIZE (cpu_arch))
6057 as_fatal (_("Invalid -march= option: `%s'"), arg);
6058 break;
6059
6060 case OPTION_MTUNE:
6061 if (*arg == '.')
6062 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6063 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6064 {
6065 if (strcmp (arg, cpu_arch [i].name) == 0)
6066 {
ccc9c027 6067 cpu_arch_tune_set = 1;
9103f4f4
L		 6068 cpu_arch_tune = cpu_arch [i].type;
6069 cpu_arch_tune_flags = cpu_arch[i].flags;
6070 break;
6071 }
6072 }
6073 if (i >= ARRAY_SIZE (cpu_arch))
6074 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6075 break;
6076
252b5132
RH		 6077 default:
6078 return 0;
6079 }
6080 return 1;
6081}
6082
6083void
6084md_show_usage (stream)
6085 FILE *stream;
6086{
4cc782b5
ILT		 6087#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6088 fprintf (stream, _("\
a38cf1db
AM		 6089 -Q ignored\n\
6090 -V print assembler version number\n\
b3b91714
AM		 6091 -k ignored\n"));
6092#endif
6093 fprintf (stream, _("\
12b55ccc 6094 -n Do not optimize code alignment\n\
b3b91714
AM		 6095 -q quieten some warnings\n"));
6096#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6097 fprintf (stream, _("\
a38cf1db 6098 -s ignored\n"));
b3b91714 6099#endif
751d281c
L		 6100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6101 fprintf (stream, _("\
6102 --32/--64 generate 32bit/64bit code\n"));
6103#endif
b3b91714
AM		 6104#ifdef SVR4_COMMENT_CHARS
6105 fprintf (stream, _("\
6106 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6107#else
6108 fprintf (stream, _("\
b3b91714 6109 --divide ignored\n"));
4cc782b5 6110#endif
9103f4f4
L		 6111 fprintf (stream, _("\
6112 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6113 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6114 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6115
252b5132
RH		 6116}
6117
99ad8390
NC		 6118#if defined(TE_PEP)
6119const char *
6120x86_64_target_format (void)
6121{
6122 if (strcmp (default_arch, "x86_64") == 0)
6123 {
6124 set_code_flag (CODE_64BIT);
6125 return COFF_TARGET_FORMAT;
6126 }
6127 else if (strcmp (default_arch, "i386") == 0)
6128 {
6129 set_code_flag (CODE_32BIT);
6130 return "coff-i386";
6131 }
6132
6133 as_fatal (_("Unknown architecture"));
6134 return NULL;
6135}
6136#endif
6137
3e73aa7c
JH		 6138#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6139 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6140
6141/* Pick the target format to use. */
6142
47926f60 6143const char *
e3bb37b5 6144i386_target_format (void)
252b5132 6145{
3e73aa7c 6146 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6147 {
6148 set_code_flag (CODE_64BIT);
6149 if (cpu_arch_isa_flags == 0)
d32cad65 6150 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6151 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6152 |CpuSSE|CpuSSE2;
ccc9c027 6153 if (cpu_arch_tune_flags == 0)
d32cad65 6154 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6155 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6156 |CpuSSE|CpuSSE2;
9103f4f4 6157 }
3e73aa7c 6158 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6159 {
6160 set_code_flag (CODE_32BIT);
6161 if (cpu_arch_isa_flags == 0)
d32cad65 6162 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6163 if (cpu_arch_tune_flags == 0)
d32cad65 6164 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6165 }
3e73aa7c
JH		 6166 else
6167 as_fatal (_("Unknown architecture"));
252b5132
RH		 6168 switch (OUTPUT_FLAVOR)
6169 {
4c63da97
AM		 6170#ifdef OBJ_MAYBE_AOUT
6171 case bfd_target_aout_flavour:
47926f60 6172 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6173#endif
6174#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6175 case bfd_target_coff_flavour:
6176 return "coff-i386";
4c63da97 6177#endif
3e73aa7c 6178#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6179 case bfd_target_elf_flavour:
3e73aa7c 6180 {
e5cb08ac 6181 if (flag_code == CODE_64BIT)
4fa24527
JB		 6182 {
6183 object_64bit = 1;
6184 use_rela_relocations = 1;
6185 }
9d7cbccd 6186 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6187 }
4c63da97 6188#endif
252b5132
RH		 6189 default:
6190 abort ();
6191 return NULL;
6192 }
6193}
6194
47926f60 6195#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6196
6197#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6198void
6199i386_elf_emit_arch_note (void)
a847613f 6200{
718ddfc0 6201 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6202 {
6203 char *p;
6204 asection *seg = now_seg;
6205 subsegT subseg = now_subseg;
6206 Elf_Internal_Note i_note;
6207 Elf_External_Note e_note;
6208 asection *note_secp;
6209 int len;
6210
6211 /* Create the .note section. */
6212 note_secp = subseg_new (".note", 0);
6213 bfd_set_section_flags (stdoutput,
6214 note_secp,
6215 SEC_HAS_CONTENTS | SEC_READONLY);
6216
6217 /* Process the arch string. */
6218 len = strlen (cpu_arch_name);
6219
6220 i_note.namesz = len + 1;
6221 i_note.descsz = 0;
6222 i_note.type = NT_ARCH;
6223 p = frag_more (sizeof (e_note.namesz));
6224 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6225 p = frag_more (sizeof (e_note.descsz));
6226 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6227 p = frag_more (sizeof (e_note.type));
6228 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6229 p = frag_more (len + 1);
6230 strcpy (p, cpu_arch_name);
6231
6232 frag_align (2, 0, 0);
6233
6234 subseg_set (seg, subseg);
6235 }
6236}
6237#endif
252b5132 6238\f
252b5132
RH		 6239symbolS *
6240md_undefined_symbol (name)
6241 char *name;
6242{
18dc2407
ILT		 6243 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6244 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6245 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6246 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6247 {
6248 if (!GOT_symbol)
6249 {
6250 if (symbol_find (name))
6251 as_bad (_("GOT already in symbol table"));
6252 GOT_symbol = symbol_new (name, undefined_section,
6253 (valueT) 0, &zero_address_frag);
6254 };
6255 return GOT_symbol;
6256 }
252b5132
RH		 6257 return 0;
6258}
6259
6260/* Round up a section size to the appropriate boundary. */
47926f60 6261
252b5132
RH		 6262valueT
6263md_section_align (segment, size)
ab9da554 6264 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6265 valueT size;
6266{
4c63da97
AM		 6267#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6268 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6269 {
6270 /* For a.out, force the section size to be aligned. If we don't do
6271 this, BFD will align it for us, but it will not write out the
6272 final bytes of the section. This may be a bug in BFD, but it is
6273 easier to fix it here since that is how the other a.out targets
6274 work. */
6275 int align;
6276
6277 align = bfd_get_section_alignment (stdoutput, segment);
6278 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6279 }
252b5132
RH		 6280#endif
6281
6282 return size;
6283}
6284
6285/* On the i386, PC-relative offsets are relative to the start of the
6286 next instruction. That is, the address of the offset, plus its
6287 size, since the offset is always the last part of the insn. */
6288
6289long
e3bb37b5 6290md_pcrel_from (fixS *fixP)
252b5132
RH		 6291{
6292 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6293}
6294
6295#ifndef I386COFF
6296
6297static void
e3bb37b5 6298s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6299{
29b0f896 6300 int temp;
252b5132 6301
8a75718c
JB		 6302#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6303 if (IS_ELF)
6304 obj_elf_section_change_hook ();
6305#endif
252b5132
RH		 6306 temp = get_absolute_expression ();
6307 subseg_set (bss_section, (subsegT) temp);
6308 demand_empty_rest_of_line ();
6309}
6310
6311#endif
6312
252b5132 6313void
e3bb37b5 6314i386_validate_fix (fixS *fixp)
252b5132
RH		 6315{
6316 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6317 {
23df1078
JH		 6318 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6319 {
4fa24527 6320 if (!object_64bit)
23df1078
JH		 6321 abort ();
6322 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6323 }
6324 else
6325 {
4fa24527 6326 if (!object_64bit)
d6ab8113
JB		 6327 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6328 else
6329 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6330 }
252b5132
RH		 6331 fixp->fx_subsy = 0;
6332 }
6333}
6334
252b5132
RH		 6335arelent *
6336tc_gen_reloc (section, fixp)
ab9da554 6337 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6338 fixS *fixp;
6339{
6340 arelent *rel;
6341 bfd_reloc_code_real_type code;
6342
6343 switch (fixp->fx_r_type)
6344 {
3e73aa7c
JH		 6345 case BFD_RELOC_X86_64_PLT32:
6346 case BFD_RELOC_X86_64_GOT32:
6347 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6348 case BFD_RELOC_386_PLT32:
6349 case BFD_RELOC_386_GOT32:
6350 case BFD_RELOC_386_GOTOFF:
6351 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6352 case BFD_RELOC_386_TLS_GD:
6353 case BFD_RELOC_386_TLS_LDM:
6354 case BFD_RELOC_386_TLS_LDO_32:
6355 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6356 case BFD_RELOC_386_TLS_IE:
6357 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6358 case BFD_RELOC_386_TLS_LE_32:
6359 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6360 case BFD_RELOC_386_TLS_GOTDESC:
6361 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6362 case BFD_RELOC_X86_64_TLSGD:
6363 case BFD_RELOC_X86_64_TLSLD:
6364 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6365 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6366 case BFD_RELOC_X86_64_GOTTPOFF:
6367 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6368 case BFD_RELOC_X86_64_TPOFF64:
6369 case BFD_RELOC_X86_64_GOTOFF64:
6370 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6371 case BFD_RELOC_X86_64_GOT64:
6372 case BFD_RELOC_X86_64_GOTPCREL64:
6373 case BFD_RELOC_X86_64_GOTPC64:
6374 case BFD_RELOC_X86_64_GOTPLT64:
6375 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6376 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6377 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6378 case BFD_RELOC_RVA:
6379 case BFD_RELOC_VTABLE_ENTRY:
6380 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6381#ifdef TE_PE
6382 case BFD_RELOC_32_SECREL:
6383#endif
252b5132
RH		 6384 code = fixp->fx_r_type;
6385 break;
dbbaec26
L		 6386 case BFD_RELOC_X86_64_32S:
6387 if (!fixp->fx_pcrel)
6388 {
6389 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6390 code = fixp->fx_r_type;
6391 break;
6392 }
252b5132 6393 default:
93382f6d 6394 if (fixp->fx_pcrel)
252b5132 6395 {
93382f6d
AM		 6396 switch (fixp->fx_size)
6397 {
6398 default:
b091f402
AM		 6399 as_bad_where (fixp->fx_file, fixp->fx_line,
6400 _("can not do %d byte pc-relative relocation"),
6401 fixp->fx_size);
93382f6d
AM		 6402 code = BFD_RELOC_32_PCREL;
6403 break;
6404 case 1: code = BFD_RELOC_8_PCREL; break;
6405 case 2: code = BFD_RELOC_16_PCREL; break;
6406 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6407#ifdef BFD64
6408 case 8: code = BFD_RELOC_64_PCREL; break;
6409#endif
93382f6d
AM		 6410 }
6411 }
6412 else
6413 {
6414 switch (fixp->fx_size)
6415 {
6416 default:
b091f402
AM		 6417 as_bad_where (fixp->fx_file, fixp->fx_line,
6418 _("can not do %d byte relocation"),
6419 fixp->fx_size);
93382f6d
AM		 6420 code = BFD_RELOC_32;
6421 break;
6422 case 1: code = BFD_RELOC_8; break;
6423 case 2: code = BFD_RELOC_16; break;
6424 case 4: code = BFD_RELOC_32; break;
937149dd 6425#ifdef BFD64
3e73aa7c 6426 case 8: code = BFD_RELOC_64; break;
937149dd 6427#endif
93382f6d 6428 }
252b5132
RH		 6429 }
6430 break;
6431 }
252b5132 6432
d182319b
JB		 6433 if ((code == BFD_RELOC_32
6434 || code == BFD_RELOC_32_PCREL
6435 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6436 && GOT_symbol
6437 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6438 {
4fa24527 6439 if (!object_64bit)
d6ab8113
JB		 6440 code = BFD_RELOC_386_GOTPC;
6441 else
6442 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6443 }
7b81dfbb
AJ		 6444 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6445 && GOT_symbol
6446 && fixp->fx_addsy == GOT_symbol)
6447 {
6448 code = BFD_RELOC_X86_64_GOTPC64;
6449 }
252b5132
RH		 6450
6451 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6452 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6453 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6454
6455 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6456
3e73aa7c
JH		 6457 if (!use_rela_relocations)
6458 {
6459 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6460 vtable entry to be used in the relocation's section offset. */
6461 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6462 rel->address = fixp->fx_offset;
252b5132 6463
c6682705 6464 rel->addend = 0;
3e73aa7c
JH		 6465 }
6466 /* Use the rela in 64bit mode. */
252b5132 6467 else
3e73aa7c 6468 {
062cd5e7
AS		 6469 if (!fixp->fx_pcrel)
6470 rel->addend = fixp->fx_offset;
6471 else
6472 switch (code)
6473 {
6474 case BFD_RELOC_X86_64_PLT32:
6475 case BFD_RELOC_X86_64_GOT32:
6476 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6477 case BFD_RELOC_X86_64_TLSGD:
6478 case BFD_RELOC_X86_64_TLSLD:
6479 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6480 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6481 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6482 rel->addend = fixp->fx_offset - fixp->fx_size;
6483 break;
6484 default:
6485 rel->addend = (section->vma
6486 - fixp->fx_size
6487 + fixp->fx_addnumber
6488 + md_pcrel_from (fixp));
6489 break;
6490 }
3e73aa7c
JH		 6491 }
6492
252b5132
RH		 6493 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6494 if (rel->howto == NULL)
6495 {
6496 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6497 _("cannot represent relocation type %s"),
252b5132
RH		 6498 bfd_get_reloc_code_name (code));
6499 /* Set howto to a garbage value so that we can keep going. */
6500 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6501 assert (rel->howto != NULL);
6502 }
6503
6504 return rel;
6505}
6506
64a0c779
DN		 6507\f
6508/* Parse operands using Intel syntax. This implements a recursive descent
6509 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6510 Programmer's Guide.
6511
6512 FIXME: We do not recognize the full operand grammar defined in the MASM
6513 documentation. In particular, all the structure/union and
6514 high-level macro operands are missing.
6515
6516 Uppercase words are terminals, lower case words are non-terminals.
6517 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6518 bars '|' denote choices. Most grammar productions are implemented in
6519 functions called 'intel_<production>'.
6520
6521 Initial production is 'expr'.
6522
9306ca4a 6523 addOp + | -
64a0c779
DN		 6524
6525 alpha [a-zA-Z]
6526
9306ca4a
JB		 6527 binOp & | AND | \| | OR | ^ | XOR
6528
64a0c779
DN		 6529 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6530
6531 constant digits [[ radixOverride ]]
6532
9306ca4a 6533 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6534
6535 digits decdigit
b77a7acd
AJ		 6536 | digits decdigit
6537 | digits hexdigit
64a0c779
DN		 6538
6539 decdigit [0-9]
6540
9306ca4a
JB		 6541 e04 e04 addOp e05
6542 | e05
6543
6544 e05 e05 binOp e06
b77a7acd 6545 | e06
64a0c779
DN		 6546
6547 e06 e06 mulOp e09
b77a7acd 6548 | e09
64a0c779
DN		 6549
6550 e09 OFFSET e10
a724f0f4
JB		 6551 | SHORT e10
6552 | + e10
6553 | - e10
9306ca4a
JB		 6554 | ~ e10
6555 | NOT e10
64a0c779
DN		 6556 | e09 PTR e10
6557 | e09 : e10
6558 | e10
6559
6560 e10 e10 [ expr ]
b77a7acd 6561 | e11
64a0c779
DN		 6562
6563 e11 ( expr )
b77a7acd 6564 | [ expr ]
64a0c779
DN		 6565 | constant
6566 | dataType
6567 | id
6568 | $
6569 | register
6570
a724f0f4 6571 => expr expr cmpOp e04
9306ca4a 6572 | e04
64a0c779
DN		 6573
6574 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6575 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6576
6577 hexdigit a | b | c | d | e | f
b77a7acd 6578 | A | B | C | D | E | F
64a0c779
DN		 6579
6580 id alpha
b77a7acd 6581 | id alpha
64a0c779
DN		 6582 | id decdigit
6583
9306ca4a 6584 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6585
6586 quote " | '
6587
6588 register specialRegister
b77a7acd 6589 | gpRegister
64a0c779
DN		 6590 | byteRegister
6591
6592 segmentRegister CS | DS | ES | FS | GS | SS
6593
9306ca4a 6594 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6595 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6596 | TR3 | TR4 | TR5 | TR6 | TR7
6597
64a0c779
DN		 6598 We simplify the grammar in obvious places (e.g., register parsing is
6599 done by calling parse_register) and eliminate immediate left recursion
6600 to implement a recursive-descent parser.
6601
a724f0f4
JB		 6602 expr e04 expr'
6603
6604 expr' cmpOp e04 expr'
6605 | Empty
9306ca4a
JB		 6606
6607 e04 e05 e04'
6608
6609 e04' addOp e05 e04'
6610 | Empty
64a0c779
DN		 6611
6612 e05 e06 e05'
6613
9306ca4a 6614 e05' binOp e06 e05'
b77a7acd 6615 | Empty
64a0c779
DN		 6616
6617 e06 e09 e06'
6618
6619 e06' mulOp e09 e06'
b77a7acd 6620 | Empty
64a0c779
DN		 6621
6622 e09 OFFSET e10 e09'
a724f0f4
JB		 6623 | SHORT e10'
6624 | + e10'
6625 | - e10'
6626 | ~ e10'
6627 | NOT e10'
b77a7acd 6628 | e10 e09'
64a0c779
DN		 6629
6630 e09' PTR e10 e09'
b77a7acd 6631 | : e10 e09'
64a0c779
DN		 6632 | Empty
6633
6634 e10 e11 e10'
6635
6636 e10' [ expr ] e10'
b77a7acd 6637 | Empty
64a0c779
DN		 6638
6639 e11 ( expr )
b77a7acd 6640 | [ expr ]
64a0c779
DN		 6641 | BYTE
6642 | WORD
6643 | DWORD
9306ca4a 6644 | FWORD
64a0c779 6645 | QWORD
9306ca4a
JB		 6646 | TBYTE
6647 | OWORD
6648 | XMMWORD
64a0c779
DN		 6649 | .
6650 | $
6651 | register
6652 | id
6653 | constant */
6654
6655/* Parsing structure for the intel syntax parser. Used to implement the
6656 semantic actions for the operand grammar. */
6657struct intel_parser_s
6658 {
6659 char *op_string; /* The string being parsed. */
6660 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6661 int op_modifier; /* Operand modifier. */
64a0c779 6662 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6663 int in_offset; /* >=1 if parsing operand of offset. */
6664 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6665 const reg_entry *reg; /* Last register reference found. */
6666 char *disp; /* Displacement string being built. */
a724f0f4 6667 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6668 };
6669
6670static struct intel_parser_s intel_parser;
6671
6672/* Token structure for parsing intel syntax. */
6673struct intel_token
6674 {
6675 int code; /* Token code. */
6676 const reg_entry *reg; /* Register entry for register tokens. */
6677 char *str; /* String representation. */
6678 };
6679
6680static struct intel_token cur_token, prev_token;
6681
50705ef4
AM		 6682/* Token codes for the intel parser. Since T_SHORT is already used
6683 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6684#define T_NIL -1
6685#define T_CONST 1
6686#define T_REG 2
6687#define T_BYTE 3
6688#define T_WORD 4
9306ca4a
JB		 6689#define T_DWORD 5
6690#define T_FWORD 6
6691#define T_QWORD 7
6692#define T_TBYTE 8
6693#define T_XMMWORD 9
50705ef4 6694#undef T_SHORT
9306ca4a
JB		 6695#define T_SHORT 10
6696#define T_OFFSET 11
6697#define T_PTR 12
6698#define T_ID 13
6699#define T_SHL 14
6700#define T_SHR 15
64a0c779
DN		 6701
6702/* Prototypes for intel parser functions. */
e3bb37b5
L		 6703static int intel_match_token (int);
6704static void intel_putback_token (void);
6705static void intel_get_token (void);
6706static int intel_expr (void);
6707static int intel_e04 (void);
6708static int intel_e05 (void);
6709static int intel_e06 (void);
6710static int intel_e09 (void);
6711static int intel_e10 (void);
6712static int intel_e11 (void);
64a0c779 6713
64a0c779 6714static int
e3bb37b5 6715i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6716{
6717 int ret;
6718 char *p;
6719
a724f0f4
JB		 6720 p = intel_parser.op_string = xstrdup (operand_string);
6721 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6722
6723 for (;;)
64a0c779 6724 {
a724f0f4
JB		 6725 /* Initialize token holders. */
6726 cur_token.code = prev_token.code = T_NIL;
6727 cur_token.reg = prev_token.reg = NULL;
6728 cur_token.str = prev_token.str = NULL;
6729
6730 /* Initialize parser structure. */
6731 intel_parser.got_a_float = got_a_float;
6732 intel_parser.op_modifier = 0;
6733 intel_parser.is_mem = 0;
6734 intel_parser.in_offset = 0;
6735 intel_parser.in_bracket = 0;
6736 intel_parser.reg = NULL;
6737 intel_parser.disp[0] = '\0';
6738 intel_parser.next_operand = NULL;
6739
6740 /* Read the first token and start the parser. */
6741 intel_get_token ();
6742 ret = intel_expr ();
6743
6744 if (!ret)
6745 break;
6746
9306ca4a
JB		 6747 if (cur_token.code != T_NIL)
6748 {
6749 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6750 current_templates->start->name, cur_token.str);
6751 ret = 0;
6752 }
64a0c779
DN		 6753 /* If we found a memory reference, hand it over to i386_displacement
6754 to fill in the rest of the operand fields. */
9306ca4a 6755 else if (intel_parser.is_mem)
64a0c779
DN		 6756 {
6757 if ((i.mem_operands == 1
6758 && (current_templates->start->opcode_modifier & IsString) == 0)
6759 || i.mem_operands == 2)
6760 {
6761 as_bad (_("too many memory references for '%s'"),
6762 current_templates->start->name);
6763 ret = 0;
6764 }
6765 else
6766 {
6767 char *s = intel_parser.disp;
6768 i.mem_operands++;
6769
a724f0f4
JB		 6770 if (!quiet_warnings && intel_parser.is_mem < 0)
6771 /* See the comments in intel_bracket_expr. */
6772 as_warn (_("Treating `%s' as memory reference"), operand_string);
6773
64a0c779
DN		 6774 /* Add the displacement expression. */
6775 if (*s != '\0')
a4622f40
AM		 6776 ret = i386_displacement (s, s + strlen (s));
6777 if (ret)
a724f0f4
JB		 6778 {
6779 /* Swap base and index in 16-bit memory operands like
6780 [si+bx]. Since i386_index_check is also used in AT&T
6781 mode we have to do that here. */
6782 if (i.base_reg
6783 && i.index_reg
6784 && (i.base_reg->reg_type & Reg16)
6785 && (i.index_reg->reg_type & Reg16)
6786 && i.base_reg->reg_num >= 6
6787 && i.index_reg->reg_num < 6)
6788 {
6789 const reg_entry *base = i.index_reg;
6790
6791 i.index_reg = i.base_reg;
6792 i.base_reg = base;
6793 }
6794 ret = i386_index_check (operand_string);
6795 }
64a0c779
DN		 6796 }
6797 }
6798
6799 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6800 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6801 || intel_parser.reg == NULL)
6802 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6803
6804 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6805 ret = 0;
a724f0f4
JB		 6806 if (!ret || !intel_parser.next_operand)
6807 break;
6808 intel_parser.op_string = intel_parser.next_operand;
6809 this_operand = i.operands++;
64a0c779
DN		 6810 }
6811
6812 free (p);
6813 free (intel_parser.disp);
6814
6815 return ret;
6816}
6817
a724f0f4
JB		 6818#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6819
6820/* expr e04 expr'
6821
6822 expr' cmpOp e04 expr'
6823 | Empty */
64a0c779 6824static int
e3bb37b5 6825intel_expr (void)
64a0c779 6826{
a724f0f4
JB		 6827 /* XXX Implement the comparison operators. */
6828 return intel_e04 ();
9306ca4a
JB		 6829}
6830
a724f0f4 6831/* e04 e05 e04'
9306ca4a 6832
a724f0f4 6833 e04' addOp e05 e04'
9306ca4a
JB		 6834 | Empty */
6835static int
e3bb37b5 6836intel_e04 (void)
9306ca4a 6837{
a724f0f4 6838 int nregs = -1;
9306ca4a 6839
a724f0f4 6840 for (;;)
9306ca4a 6841 {
a724f0f4
JB		 6842 if (!intel_e05())
6843 return 0;
9306ca4a 6844
a724f0f4
JB		 6845 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6846 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6847
a724f0f4
JB		 6848 if (cur_token.code == '+')
6849 nregs = -1;
6850 else if (cur_token.code == '-')
6851 nregs = NUM_ADDRESS_REGS;
6852 else
6853 return 1;
64a0c779 6854
a724f0f4
JB		 6855 strcat (intel_parser.disp, cur_token.str);
6856 intel_match_token (cur_token.code);
6857 }
64a0c779
DN		 6858}
6859
64a0c779
DN		 6860/* e05 e06 e05'
6861
9306ca4a 6862 e05' binOp e06 e05'
64a0c779
DN		 6863 | Empty */
6864static int
e3bb37b5 6865intel_e05 (void)
64a0c779 6866{
a724f0f4 6867 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6868
a724f0f4 6869 for (;;)
64a0c779 6870 {
a724f0f4
JB		 6871 if (!intel_e06())
6872 return 0;
6873
4eed87de
AM		 6874 if (cur_token.code == '&'
6875 || cur_token.code == '|'
6876 || cur_token.code == '^')
a724f0f4
JB		 6877 {
6878 char str[2];
6879
6880 str[0] = cur_token.code;
6881 str[1] = 0;
6882 strcat (intel_parser.disp, str);
6883 }
6884 else
6885 break;
9306ca4a 6886
64a0c779
DN		 6887 intel_match_token (cur_token.code);
6888
a724f0f4
JB		 6889 if (nregs < 0)
6890 nregs = ~nregs;
64a0c779 6891 }
a724f0f4
JB		 6892 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6893 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6894 return 1;
4a1805b1 6895}
64a0c779
DN		 6896
6897/* e06 e09 e06'
6898
6899 e06' mulOp e09 e06'
b77a7acd 6900 | Empty */
64a0c779 6901static int
e3bb37b5 6902intel_e06 (void)
64a0c779 6903{
a724f0f4 6904 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6905
a724f0f4 6906 for (;;)
64a0c779 6907 {
a724f0f4
JB		 6908 if (!intel_e09())
6909 return 0;
9306ca4a 6910
4eed87de
AM		 6911 if (cur_token.code == '*'
6912 || cur_token.code == '/'
6913 || cur_token.code == '%')
a724f0f4
JB		 6914 {
6915 char str[2];
9306ca4a 6916
a724f0f4
JB		 6917 str[0] = cur_token.code;
6918 str[1] = 0;
6919 strcat (intel_parser.disp, str);
6920 }
6921 else if (cur_token.code == T_SHL)
6922 strcat (intel_parser.disp, "<<");
6923 else if (cur_token.code == T_SHR)
6924 strcat (intel_parser.disp, ">>");
6925 else
6926 break;
9306ca4a 6927
64e74474 6928 intel_match_token (cur_token.code);
64a0c779 6929
a724f0f4
JB		 6930 if (nregs < 0)
6931 nregs = ~nregs;
64a0c779 6932 }
a724f0f4
JB		 6933 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6934 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6935 return 1;
64a0c779
DN		 6936}
6937
a724f0f4
JB		 6938/* e09 OFFSET e09
6939 | SHORT e09
6940 | + e09
6941 | - e09
6942 | ~ e09
6943 | NOT e09
9306ca4a
JB		 6944 | e10 e09'
6945
64a0c779 6946 e09' PTR e10 e09'
b77a7acd 6947 | : e10 e09'
64a0c779
DN		 6948 | Empty */
6949static int
e3bb37b5 6950intel_e09 (void)
64a0c779 6951{
a724f0f4
JB		 6952 int nregs = ~NUM_ADDRESS_REGS;
6953 int in_offset = 0;
6954
6955 for (;;)
64a0c779 6956 {
a724f0f4
JB		 6957 /* Don't consume constants here. */
6958 if (cur_token.code == '+' || cur_token.code == '-')
6959 {
6960 /* Need to look one token ahead - if the next token
6961 is a constant, the current token is its sign. */
6962 int next_code;
6963
6964 intel_match_token (cur_token.code);
6965 next_code = cur_token.code;
6966 intel_putback_token ();
6967 if (next_code == T_CONST)
6968 break;
6969 }
6970
6971 /* e09 OFFSET e09 */
6972 if (cur_token.code == T_OFFSET)
6973 {
6974 if (!in_offset++)
6975 ++intel_parser.in_offset;
6976 }
6977
6978 /* e09 SHORT e09 */
6979 else if (cur_token.code == T_SHORT)
6980 intel_parser.op_modifier |= 1 << T_SHORT;
6981
6982 /* e09 + e09 */
6983 else if (cur_token.code == '+')
6984 strcat (intel_parser.disp, "+");
6985
6986 /* e09 - e09
6987 | ~ e09
6988 | NOT e09 */
6989 else if (cur_token.code == '-' || cur_token.code == '~')
6990 {
6991 char str[2];
64a0c779 6992
a724f0f4
JB		 6993 if (nregs < 0)
6994 nregs = ~nregs;
6995 str[0] = cur_token.code;
6996 str[1] = 0;
6997 strcat (intel_parser.disp, str);
6998 }
6999
7000 /* e09 e10 e09' */
7001 else
7002 break;
7003
7004 intel_match_token (cur_token.code);
64a0c779
DN		 7005 }
7006
a724f0f4 7007 for (;;)
9306ca4a 7008 {
a724f0f4
JB		 7009 if (!intel_e10 ())
7010 return 0;
9306ca4a 7011
a724f0f4
JB		 7012 /* e09' PTR e10 e09' */
7013 if (cur_token.code == T_PTR)
7014 {
7015 char suffix;
9306ca4a 7016
a724f0f4
JB		 7017 if (prev_token.code == T_BYTE)
7018 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7019
a724f0f4
JB		 7020 else if (prev_token.code == T_WORD)
7021 {
7022 if (current_templates->start->name[0] == 'l'
7023 && current_templates->start->name[2] == 's'
7024 && current_templates->start->name[3] == 0)
7025 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7026 else if (intel_parser.got_a_float == 2) /* "fi..." */
7027 suffix = SHORT_MNEM_SUFFIX;
7028 else
7029 suffix = WORD_MNEM_SUFFIX;
7030 }
64a0c779 7031
a724f0f4
JB		 7032 else if (prev_token.code == T_DWORD)
7033 {
7034 if (current_templates->start->name[0] == 'l'
7035 && current_templates->start->name[2] == 's'
7036 && current_templates->start->name[3] == 0)
7037 suffix = WORD_MNEM_SUFFIX;
7038 else if (flag_code == CODE_16BIT
7039 && (current_templates->start->opcode_modifier
435acd52 7040 & (Jump | JumpDword)))
a724f0f4
JB		 7041 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7042 else if (intel_parser.got_a_float == 1) /* "f..." */
7043 suffix = SHORT_MNEM_SUFFIX;
7044 else
7045 suffix = LONG_MNEM_SUFFIX;
7046 }
9306ca4a 7047
a724f0f4
JB		 7048 else if (prev_token.code == T_FWORD)
7049 {
7050 if (current_templates->start->name[0] == 'l'
7051 && current_templates->start->name[2] == 's'
7052 && current_templates->start->name[3] == 0)
7053 suffix = LONG_MNEM_SUFFIX;
7054 else if (!intel_parser.got_a_float)
7055 {
7056 if (flag_code == CODE_16BIT)
7057 add_prefix (DATA_PREFIX_OPCODE);
7058 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7059 }
7060 else
7061 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7062 }
64a0c779 7063
a724f0f4
JB		 7064 else if (prev_token.code == T_QWORD)
7065 {
7066 if (intel_parser.got_a_float == 1) /* "f..." */
7067 suffix = LONG_MNEM_SUFFIX;
7068 else
7069 suffix = QWORD_MNEM_SUFFIX;
7070 }
64a0c779 7071
a724f0f4
JB		 7072 else if (prev_token.code == T_TBYTE)
7073 {
7074 if (intel_parser.got_a_float == 1)
7075 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7076 else
7077 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7078 }
9306ca4a 7079
a724f0f4 7080 else if (prev_token.code == T_XMMWORD)
9306ca4a 7081 {
a724f0f4
JB		 7082 /* XXX ignored for now, but accepted since gcc uses it */
7083 suffix = 0;
9306ca4a 7084 }
64a0c779 7085
f16b83df 7086 else
a724f0f4
JB		 7087 {
7088 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7089 return 0;
7090 }
7091
435acd52
JB		 7092 /* Operands for jump/call using 'ptr' notation denote absolute
7093 addresses. */
7094 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7095 i.types[this_operand] |= JumpAbsolute;
7096
a724f0f4
JB		 7097 if (current_templates->start->base_opcode == 0x8d /* lea */)
7098 ;
7099 else if (!i.suffix)
7100 i.suffix = suffix;
7101 else if (i.suffix != suffix)
7102 {
7103 as_bad (_("Conflicting operand modifiers"));
7104 return 0;
7105 }
64a0c779 7106
9306ca4a
JB		 7107 }
7108
a724f0f4
JB		 7109 /* e09' : e10 e09' */
7110 else if (cur_token.code == ':')
9306ca4a 7111 {
a724f0f4
JB		 7112 if (prev_token.code != T_REG)
7113 {
7114 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7115 segment/group identifier (which we don't have), using comma
7116 as the operand separator there is even less consistent, since
7117 there all branches only have a single operand. */
7118 if (this_operand != 0
7119 || intel_parser.in_offset
7120 || intel_parser.in_bracket
7121 || (!(current_templates->start->opcode_modifier
7122 & (Jump|JumpDword|JumpInterSegment))
7123 && !(current_templates->start->operand_types[0]
7124 & JumpAbsolute)))
7125 return intel_match_token (T_NIL);
7126 /* Remember the start of the 2nd operand and terminate 1st
7127 operand here.
7128 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7129 another expression), but it gets at least the simplest case
7130 (a plain number or symbol on the left side) right. */
7131 intel_parser.next_operand = intel_parser.op_string;
7132 *--intel_parser.op_string = '\0';
7133 return intel_match_token (':');
7134 }
9306ca4a 7135 }
64a0c779 7136
a724f0f4 7137 /* e09' Empty */
64a0c779 7138 else
a724f0f4 7139 break;
64a0c779 7140
a724f0f4
JB		 7141 intel_match_token (cur_token.code);
7142
7143 }
7144
7145 if (in_offset)
7146 {
7147 --intel_parser.in_offset;
7148 if (nregs < 0)
7149 nregs = ~nregs;
7150 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7151 {
a724f0f4 7152 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7153 return 0;
7154 }
a724f0f4
JB		 7155 intel_parser.op_modifier |= 1 << T_OFFSET;
7156 }
9306ca4a 7157
a724f0f4
JB		 7158 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7159 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7160 return 1;
7161}
64a0c779 7162
a724f0f4 7163static int
e3bb37b5 7164intel_bracket_expr (void)
a724f0f4
JB		 7165{
7166 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7167 const char *start = intel_parser.op_string;
7168 int len;
7169
7170 if (i.op[this_operand].regs)
7171 return intel_match_token (T_NIL);
7172
7173 intel_match_token ('[');
7174
7175 /* Mark as a memory operand only if it's not already known to be an
7176 offset expression. If it's an offset expression, we need to keep
7177 the brace in. */
7178 if (!intel_parser.in_offset)
7179 {
7180 ++intel_parser.in_bracket;
435acd52
JB		 7181
7182 /* Operands for jump/call inside brackets denote absolute addresses. */
7183 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7184 i.types[this_operand] |= JumpAbsolute;
7185
a724f0f4
JB		 7186 /* Unfortunately gas always diverged from MASM in a respect that can't
7187 be easily fixed without risking to break code sequences likely to be
7188 encountered (the testsuite even check for this): MASM doesn't consider
7189 an expression inside brackets unconditionally as a memory reference.
7190 When that is e.g. a constant, an offset expression, or the sum of the
7191 two, this is still taken as a constant load. gas, however, always
7192 treated these as memory references. As a compromise, we'll try to make
7193 offset expressions inside brackets work the MASM way (since that's
7194 less likely to be found in real world code), but make constants alone
7195 continue to work the traditional gas way. In either case, issue a
7196 warning. */
7197 intel_parser.op_modifier &= ~was_offset;
64a0c779 7198 }
a724f0f4 7199 else
64e74474 7200 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7201
7202 /* Add a '+' to the displacement string if necessary. */
7203 if (*intel_parser.disp != '\0'
7204 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7205 strcat (intel_parser.disp, "+");
64a0c779 7206
a724f0f4
JB		 7207 if (intel_expr ()
7208 && (len = intel_parser.op_string - start - 1,
7209 intel_match_token (']')))
64a0c779 7210 {
a724f0f4
JB		 7211 /* Preserve brackets when the operand is an offset expression. */
7212 if (intel_parser.in_offset)
7213 strcat (intel_parser.disp, "]");
7214 else
7215 {
7216 --intel_parser.in_bracket;
7217 if (i.base_reg || i.index_reg)
7218 intel_parser.is_mem = 1;
7219 if (!intel_parser.is_mem)
7220 {
7221 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7222 /* Defer the warning until all of the operand was parsed. */
7223 intel_parser.is_mem = -1;
7224 else if (!quiet_warnings)
4eed87de
AM		 7225 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7226 len, start, len, start);
a724f0f4
JB		 7227 }
7228 }
7229 intel_parser.op_modifier |= was_offset;
64a0c779 7230
a724f0f4 7231 return 1;
64a0c779 7232 }
a724f0f4 7233 return 0;
64a0c779
DN		 7234}
7235
7236/* e10 e11 e10'
7237
7238 e10' [ expr ] e10'
b77a7acd 7239 | Empty */
64a0c779 7240static int
e3bb37b5 7241intel_e10 (void)
64a0c779 7242{
a724f0f4
JB		 7243 if (!intel_e11 ())
7244 return 0;
64a0c779 7245
a724f0f4 7246 while (cur_token.code == '[')
64a0c779 7247 {
a724f0f4 7248 if (!intel_bracket_expr ())
21d6c4af 7249 return 0;
64a0c779
DN		 7250 }
7251
a724f0f4 7252 return 1;
64a0c779
DN		 7253}
7254
64a0c779 7255/* e11 ( expr )
b77a7acd 7256 | [ expr ]
64a0c779
DN		 7257 | BYTE
7258 | WORD
7259 | DWORD
9306ca4a 7260 | FWORD
64a0c779 7261 | QWORD
9306ca4a
JB		 7262 | TBYTE
7263 | OWORD
7264 | XMMWORD
4a1805b1 7265 | $
64a0c779
DN		 7266 | .
7267 | register
7268 | id
7269 | constant */
7270static int
e3bb37b5 7271intel_e11 (void)
64a0c779 7272{
a724f0f4 7273 switch (cur_token.code)
64a0c779 7274 {
a724f0f4
JB		 7275 /* e11 ( expr ) */
7276 case '(':
64a0c779
DN		 7277 intel_match_token ('(');
7278 strcat (intel_parser.disp, "(");
7279
7280 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7281 {
7282 strcat (intel_parser.disp, ")");
7283 return 1;
7284 }
a724f0f4 7285 return 0;
4a1805b1 7286
a724f0f4
JB		 7287 /* e11 [ expr ] */
7288 case '[':
a724f0f4 7289 return intel_bracket_expr ();
64a0c779 7290
a724f0f4
JB		 7291 /* e11 $
7292 | . */
7293 case '.':
64a0c779
DN		 7294 strcat (intel_parser.disp, cur_token.str);
7295 intel_match_token (cur_token.code);
21d6c4af
DN		 7296
7297 /* Mark as a memory operand only if it's not already known to be an
7298 offset expression. */
a724f0f4 7299 if (!intel_parser.in_offset)
21d6c4af 7300 intel_parser.is_mem = 1;
64a0c779
DN		 7301
7302 return 1;
64a0c779 7303
a724f0f4
JB		 7304 /* e11 register */
7305 case T_REG:
7306 {
7307 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7308
a724f0f4 7309 intel_match_token (T_REG);
64a0c779 7310
a724f0f4
JB		 7311 /* Check for segment change. */
7312 if (cur_token.code == ':')
7313 {
7314 if (!(reg->reg_type & (SReg2 | SReg3)))
7315 {
4eed87de
AM		 7316 as_bad (_("`%s' is not a valid segment register"),
7317 reg->reg_name);
a724f0f4
JB		 7318 return 0;
7319 }
7320 else if (i.seg[i.mem_operands])
7321 as_warn (_("Extra segment override ignored"));
7322 else
7323 {
7324 if (!intel_parser.in_offset)
7325 intel_parser.is_mem = 1;
7326 switch (reg->reg_num)
7327 {
7328 case 0:
7329 i.seg[i.mem_operands] = &es;
7330 break;
7331 case 1:
7332 i.seg[i.mem_operands] = &cs;
7333 break;
7334 case 2:
7335 i.seg[i.mem_operands] = &ss;
7336 break;
7337 case 3:
7338 i.seg[i.mem_operands] = &ds;
7339 break;
7340 case 4:
7341 i.seg[i.mem_operands] = &fs;
7342 break;
7343 case 5:
7344 i.seg[i.mem_operands] = &gs;
7345 break;
7346 }
7347 }
7348 }
64a0c779 7349
a724f0f4
JB		 7350 /* Not a segment register. Check for register scaling. */
7351 else if (cur_token.code == '*')
7352 {
7353 if (!intel_parser.in_bracket)
7354 {
7355 as_bad (_("Register scaling only allowed in memory operands"));
7356 return 0;
7357 }
64a0c779 7358
a724f0f4
JB		 7359 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7360 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7361 else if (i.index_reg)
7362 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7363
a724f0f4
JB		 7364 /* What follows must be a valid scale. */
7365 intel_match_token ('*');
7366 i.index_reg = reg;
7367 i.types[this_operand] |= BaseIndex;
64a0c779 7368
a724f0f4
JB		 7369 /* Set the scale after setting the register (otherwise,
7370 i386_scale will complain) */
7371 if (cur_token.code == '+' || cur_token.code == '-')
7372 {
7373 char *str, sign = cur_token.code;
7374 intel_match_token (cur_token.code);
7375 if (cur_token.code != T_CONST)
7376 {
7377 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7378 cur_token.str);
7379 return 0;
7380 }
7381 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7382 strcpy (str + 1, cur_token.str);
7383 *str = sign;
7384 if (!i386_scale (str))
7385 return 0;
7386 free (str);
7387 }
7388 else if (!i386_scale (cur_token.str))
64a0c779 7389 return 0;
a724f0f4
JB		 7390 intel_match_token (cur_token.code);
7391 }
64a0c779 7392
a724f0f4
JB		 7393 /* No scaling. If this is a memory operand, the register is either a
7394 base register (first occurrence) or an index register (second
7395 occurrence). */
7b0441f6 7396 else if (intel_parser.in_bracket)
a724f0f4 7397 {
64a0c779 7398
a724f0f4
JB		 7399 if (!i.base_reg)
7400 i.base_reg = reg;
7401 else if (!i.index_reg)
7402 i.index_reg = reg;
7403 else
7404 {
7405 as_bad (_("Too many register references in memory operand"));
7406 return 0;
7407 }
64a0c779 7408
a724f0f4
JB		 7409 i.types[this_operand] |= BaseIndex;
7410 }
4a1805b1 7411
4d1bb795
JB		 7412 /* It's neither base nor index. */
7413 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7414 {
7415 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7416 i.op[this_operand].regs = reg;
7417 i.reg_operands++;
7418 }
7419 else
7420 {
7421 as_bad (_("Invalid use of register"));
7422 return 0;
7423 }
64a0c779 7424
a724f0f4
JB		 7425 /* Since registers are not part of the displacement string (except
7426 when we're parsing offset operands), we may need to remove any
7427 preceding '+' from the displacement string. */
7428 if (*intel_parser.disp != '\0'
7429 && !intel_parser.in_offset)
7430 {
7431 char *s = intel_parser.disp;
7432 s += strlen (s) - 1;
7433 if (*s == '+')
7434 *s = '\0';
7435 }
4a1805b1 7436
a724f0f4
JB		 7437 return 1;
7438 }
7439
7440 /* e11 BYTE
7441 | WORD
7442 | DWORD
7443 | FWORD
7444 | QWORD
7445 | TBYTE
7446 | OWORD
7447 | XMMWORD */
7448 case T_BYTE:
7449 case T_WORD:
7450 case T_DWORD:
7451 case T_FWORD:
7452 case T_QWORD:
7453 case T_TBYTE:
7454 case T_XMMWORD:
7455 intel_match_token (cur_token.code);
64a0c779 7456
a724f0f4
JB		 7457 if (cur_token.code == T_PTR)
7458 return 1;
7459
7460 /* It must have been an identifier. */
7461 intel_putback_token ();
7462 cur_token.code = T_ID;
7463 /* FALLTHRU */
7464
7465 /* e11 id
7466 | constant */
7467 case T_ID:
7468 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7469 {
7470 symbolS *symbolP;
7471
a724f0f4
JB		 7472 /* The identifier represents a memory reference only if it's not
7473 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7474 symbolP = symbol_find(cur_token.str);
7475 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7476 intel_parser.is_mem = 1;
7477 }
a724f0f4 7478 /* FALLTHRU */
64a0c779 7479
a724f0f4
JB		 7480 case T_CONST:
7481 case '-':
7482 case '+':
7483 {
7484 char *save_str, sign = 0;
64a0c779 7485
a724f0f4
JB		 7486 /* Allow constants that start with `+' or `-'. */
7487 if (cur_token.code == '-' || cur_token.code == '+')
7488 {
7489 sign = cur_token.code;
7490 intel_match_token (cur_token.code);
7491 if (cur_token.code != T_CONST)
7492 {
7493 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7494 cur_token.str);
7495 return 0;
7496 }
7497 }
64a0c779 7498
a724f0f4
JB		 7499 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7500 strcpy (save_str + !!sign, cur_token.str);
7501 if (sign)
7502 *save_str = sign;
64a0c779 7503
a724f0f4
JB		 7504 /* Get the next token to check for register scaling. */
7505 intel_match_token (cur_token.code);
64a0c779 7506
4eed87de
AM		 7507 /* Check if this constant is a scaling factor for an
7508 index register. */
a724f0f4
JB		 7509 if (cur_token.code == '*')
7510 {
7511 if (intel_match_token ('*') && cur_token.code == T_REG)
7512 {
7513 const reg_entry *reg = cur_token.reg;
7514
7515 if (!intel_parser.in_bracket)
7516 {
4eed87de
AM		 7517 as_bad (_("Register scaling only allowed "
7518 "in memory operands"));
a724f0f4
JB		 7519 return 0;
7520 }
7521
4eed87de
AM		 7522 /* Disallow things like [1*si].
7523 sp and esp are invalid as index. */
7524 if (reg->reg_type & Reg16)
7525 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7526 else if (i.index_reg)
4eed87de 7527 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7528
7529 /* The constant is followed by `* reg', so it must be
7530 a valid scale. */
7531 i.index_reg = reg;
7532 i.types[this_operand] |= BaseIndex;
7533
7534 /* Set the scale after setting the register (otherwise,
7535 i386_scale will complain) */
7536 if (!i386_scale (save_str))
64a0c779 7537 return 0;
a724f0f4
JB		 7538 intel_match_token (T_REG);
7539
7540 /* Since registers are not part of the displacement
7541 string, we may need to remove any preceding '+' from
7542 the displacement string. */
7543 if (*intel_parser.disp != '\0')
7544 {
7545 char *s = intel_parser.disp;
7546 s += strlen (s) - 1;
7547 if (*s == '+')
7548 *s = '\0';
7549 }
7550
7551 free (save_str);
7552
7553 return 1;
7554 }
64a0c779 7555
a724f0f4
JB		 7556 /* The constant was not used for register scaling. Since we have
7557 already consumed the token following `*' we now need to put it
7558 back in the stream. */
64a0c779 7559 intel_putback_token ();
a724f0f4 7560 }
64a0c779 7561
a724f0f4
JB		 7562 /* Add the constant to the displacement string. */
7563 strcat (intel_parser.disp, save_str);
7564 free (save_str);
64a0c779 7565
a724f0f4
JB		 7566 return 1;
7567 }
64a0c779
DN		 7568 }
7569
64a0c779
DN		 7570 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7571 return 0;
7572}
7573
64a0c779
DN		 7574/* Match the given token against cur_token. If they match, read the next
7575 token from the operand string. */
7576static int
e3bb37b5 7577intel_match_token (int code)
64a0c779
DN		 7578{
7579 if (cur_token.code == code)
7580 {
7581 intel_get_token ();
7582 return 1;
7583 }
7584 else
7585 {
0477af35 7586 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7587 return 0;
7588 }
7589}
7590
64a0c779
DN		 7591/* Read a new token from intel_parser.op_string and store it in cur_token. */
7592static void
e3bb37b5 7593intel_get_token (void)
64a0c779
DN		 7594{
7595 char *end_op;
7596 const reg_entry *reg;
7597 struct intel_token new_token;
7598
7599 new_token.code = T_NIL;
7600 new_token.reg = NULL;
7601 new_token.str = NULL;
7602
4a1805b1 7603 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7604 cur_token to prev_token. */
7605 if (prev_token.str)
7606 free (prev_token.str);
7607
7608 prev_token = cur_token;
7609
7610 /* Skip whitespace. */
7611 while (is_space_char (*intel_parser.op_string))
7612 intel_parser.op_string++;
7613
7614 /* Return an empty token if we find nothing else on the line. */
7615 if (*intel_parser.op_string == '\0')
7616 {
7617 cur_token = new_token;
7618 return;
7619 }
7620
7621 /* The new token cannot be larger than the remainder of the operand
7622 string. */
a724f0f4 7623 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7624 new_token.str[0] = '\0';
7625
7626 if (strchr ("0123456789", *intel_parser.op_string))
7627 {
7628 char *p = new_token.str;
7629 char *q = intel_parser.op_string;
7630 new_token.code = T_CONST;
7631
7632 /* Allow any kind of identifier char to encompass floating point and
7633 hexadecimal numbers. */
7634 while (is_identifier_char (*q))
7635 *p++ = *q++;
7636 *p = '\0';
7637
7638 /* Recognize special symbol names [0-9][bf]. */
7639 if (strlen (intel_parser.op_string) == 2
4a1805b1 7640 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7641 || intel_parser.op_string[1] == 'f'))
7642 new_token.code = T_ID;
7643 }
7644
4d1bb795 7645 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7646 {
4d1bb795
JB		 7647 size_t len = end_op - intel_parser.op_string;
7648
64a0c779
DN		 7649 new_token.code = T_REG;
7650 new_token.reg = reg;
7651
4d1bb795
JB		 7652 memcpy (new_token.str, intel_parser.op_string, len);
7653 new_token.str[len] = '\0';
64a0c779
DN		 7654 }
7655
7656 else if (is_identifier_char (*intel_parser.op_string))
7657 {
7658 char *p = new_token.str;
7659 char *q = intel_parser.op_string;
7660
7661 /* A '.' or '$' followed by an identifier char is an identifier.
7662 Otherwise, it's operator '.' followed by an expression. */
7663 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7664 {
9306ca4a
JB		 7665 new_token.code = '.';
7666 new_token.str[0] = '.';
64a0c779
DN		 7667 new_token.str[1] = '\0';
7668 }
7669 else
7670 {
7671 while (is_identifier_char (*q) || *q == '@')
7672 *p++ = *q++;
7673 *p = '\0';
7674
9306ca4a
JB		 7675 if (strcasecmp (new_token.str, "NOT") == 0)
7676 new_token.code = '~';
7677
7678 else if (strcasecmp (new_token.str, "MOD") == 0)
7679 new_token.code = '%';
7680
7681 else if (strcasecmp (new_token.str, "AND") == 0)
7682 new_token.code = '&';
7683
7684 else if (strcasecmp (new_token.str, "OR") == 0)
7685 new_token.code = '|';
7686
7687 else if (strcasecmp (new_token.str, "XOR") == 0)
7688 new_token.code = '^';
7689
7690 else if (strcasecmp (new_token.str, "SHL") == 0)
7691 new_token.code = T_SHL;
7692
7693 else if (strcasecmp (new_token.str, "SHR") == 0)
7694 new_token.code = T_SHR;
7695
7696 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7697 new_token.code = T_BYTE;
7698
7699 else if (strcasecmp (new_token.str, "WORD") == 0)
7700 new_token.code = T_WORD;
7701
7702 else if (strcasecmp (new_token.str, "DWORD") == 0)
7703 new_token.code = T_DWORD;
7704
9306ca4a
JB		 7705 else if (strcasecmp (new_token.str, "FWORD") == 0)
7706 new_token.code = T_FWORD;
7707
64a0c779
DN		 7708 else if (strcasecmp (new_token.str, "QWORD") == 0)
7709 new_token.code = T_QWORD;
7710
9306ca4a
JB		 7711 else if (strcasecmp (new_token.str, "TBYTE") == 0
7712 /* XXX remove (gcc still uses it) */
7713 || strcasecmp (new_token.str, "XWORD") == 0)
7714 new_token.code = T_TBYTE;
7715
7716 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7717 || strcasecmp (new_token.str, "OWORD") == 0)
7718 new_token.code = T_XMMWORD;
64a0c779
DN		 7719
7720 else if (strcasecmp (new_token.str, "PTR") == 0)
7721 new_token.code = T_PTR;
7722
7723 else if (strcasecmp (new_token.str, "SHORT") == 0)
7724 new_token.code = T_SHORT;
7725
7726 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7727 {
7728 new_token.code = T_OFFSET;
7729
7730 /* ??? This is not mentioned in the MASM grammar but gcc
7731 makes use of it with -mintel-syntax. OFFSET may be
7732 followed by FLAT: */
7733 if (strncasecmp (q, " FLAT:", 6) == 0)
7734 strcat (new_token.str, " FLAT:");
7735 }
7736
7737 /* ??? This is not mentioned in the MASM grammar. */
7738 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7739 {
7740 new_token.code = T_OFFSET;
7741 if (*q == ':')
7742 strcat (new_token.str, ":");
7743 else
7744 as_bad (_("`:' expected"));
7745 }
64a0c779
DN		 7746
7747 else
7748 new_token.code = T_ID;
7749 }
7750 }
7751
9306ca4a
JB		 7752 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7753 {
7754 new_token.code = *intel_parser.op_string;
7755 new_token.str[0] = *intel_parser.op_string;
7756 new_token.str[1] = '\0';
7757 }
7758
7759 else if (strchr ("<>", *intel_parser.op_string)
7760 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7761 {
7762 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7763 new_token.str[0] = *intel_parser.op_string;
7764 new_token.str[1] = *intel_parser.op_string;
7765 new_token.str[2] = '\0';
7766 }
7767
64a0c779 7768 else
0477af35 7769 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7770
7771 intel_parser.op_string += strlen (new_token.str);
7772 cur_token = new_token;
7773}
7774
64a0c779
DN		 7775/* Put cur_token back into the token stream and make cur_token point to
7776 prev_token. */
7777static void
e3bb37b5 7778intel_putback_token (void)
64a0c779 7779{
a724f0f4
JB		 7780 if (cur_token.code != T_NIL)
7781 {
7782 intel_parser.op_string -= strlen (cur_token.str);
7783 free (cur_token.str);
7784 }
64a0c779 7785 cur_token = prev_token;
4a1805b1 7786
64a0c779
DN		 7787 /* Forget prev_token. */
7788 prev_token.code = T_NIL;
7789 prev_token.reg = NULL;
7790 prev_token.str = NULL;
7791}
54cfded0 7792
a4447b93 7793int
1df69f4f 7794tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7795{
7796 unsigned int regnum;
7797 unsigned int regnames_count;
089dfecd 7798 static const char *const regnames_32[] =
54cfded0 7799 {
a4447b93
RH		 7800 "eax", "ecx", "edx", "ebx",
7801 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7802 "eip", "eflags", NULL,
7803 "st0", "st1", "st2", "st3",
7804 "st4", "st5", "st6", "st7",
7805 NULL, NULL,
7806 "xmm0", "xmm1", "xmm2", "xmm3",
7807 "xmm4", "xmm5", "xmm6", "xmm7",
7808 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7809 "mm4", "mm5", "mm6", "mm7",
7810 "fcw", "fsw", "mxcsr",
7811 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7812 "tr", "ldtr"
54cfded0 7813 };
089dfecd 7814 static const char *const regnames_64[] =
54cfded0 7815 {
089dfecd
JB		 7816 "rax", "rdx", "rcx", "rbx",
7817 "rsi", "rdi", "rbp", "rsp",
7818 "r8", "r9", "r10", "r11",
54cfded0 7819 "r12", "r13", "r14", "r15",
089dfecd
JB		 7820 "rip",
7821 "xmm0", "xmm1", "xmm2", "xmm3",
7822 "xmm4", "xmm5", "xmm6", "xmm7",
7823 "xmm8", "xmm9", "xmm10", "xmm11",
7824 "xmm12", "xmm13", "xmm14", "xmm15",
7825 "st0", "st1", "st2", "st3",
7826 "st4", "st5", "st6", "st7",
7827 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7828 "mm4", "mm5", "mm6", "mm7",
7829 "rflags",
7830 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7831 "fs.base", "gs.base", NULL, NULL,
7832 "tr", "ldtr",
7833 "mxcsr", "fcw", "fsw"
54cfded0 7834 };
089dfecd 7835 const char *const *regnames;
54cfded0
AM		 7836
7837 if (flag_code == CODE_64BIT)
7838 {
7839 regnames = regnames_64;
0cea6190 7840 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7841 }
7842 else
7843 {
7844 regnames = regnames_32;
0cea6190 7845 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7846 }
7847
7848 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7849 if (regnames[regnum] != NULL
7850 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7851 return regnum;
7852
54cfded0
AM		 7853 return -1;
7854}
7855
7856void
7857tc_x86_frame_initial_instructions (void)
7858{
a4447b93
RH		 7859 static unsigned int sp_regno;
7860
7861 if (!sp_regno)
7862 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7863 ? "rsp" : "esp");
7864
7865 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7866 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7867}
d2b2c203
DJ		 7868
7869int
7870i386_elf_section_type (const char *str, size_t len)
7871{
7872 if (flag_code == CODE_64BIT
7873 && len == sizeof ("unwind") - 1
7874 && strncmp (str, "unwind", 6) == 0)
7875 return SHT_X86_64_UNWIND;
7876
7877 return -1;
7878}
bb41ade5
AM		 7879
7880#ifdef TE_PE
7881void
7882tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7883{
7884 expressionS expr;
7885
7886 expr.X_op = O_secrel;
7887 expr.X_add_symbol = symbol;
7888 expr.X_add_number = 0;
7889 emit_expr (&expr, size);
7890}
7891#endif
3b22753a
L		 7892
7893#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7894/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7895
7896int
7897x86_64_section_letter (int letter, char **ptr_msg)
7898{
7899 if (flag_code == CODE_64BIT)
7900 {
7901 if (letter == 'l')
7902 return SHF_X86_64_LARGE;
7903
7904 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7905 }
3b22753a 7906 else
64e74474 7907 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7908 return -1;
7909}
7910
7911int
7912x86_64_section_word (char *str, size_t len)
7913{
8620418b 7914 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7915 return SHF_X86_64_LARGE;
7916
7917 return -1;
7918}
7919
7920static void
7921handle_large_common (int small ATTRIBUTE_UNUSED)
7922{
7923 if (flag_code != CODE_64BIT)
7924 {
7925 s_comm_internal (0, elf_common_parse);
7926 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7927 }
7928 else
7929 {
7930 static segT lbss_section;
7931 asection *saved_com_section_ptr = elf_com_section_ptr;
7932 asection *saved_bss_section = bss_section;
7933
7934 if (lbss_section == NULL)
7935 {
7936 flagword applicable;
7937 segT seg = now_seg;
7938 subsegT subseg = now_subseg;
7939
7940 /* The .lbss section is for local .largecomm symbols. */
7941 lbss_section = subseg_new (".lbss", 0);
7942 applicable = bfd_applicable_section_flags (stdoutput);
7943 bfd_set_section_flags (stdoutput, lbss_section,
7944 applicable & SEC_ALLOC);
7945 seg_info (lbss_section)->bss = 1;
7946
7947 subseg_set (seg, subseg);
7948 }
7949
7950 elf_com_section_ptr = &_bfd_elf_large_com_section;
7951 bss_section = lbss_section;
7952
7953 s_comm_internal (0, elf_common_parse);
7954
7955 elf_com_section_ptr = saved_com_section_ptr;
7956 bss_section = saved_bss_section;
7957 }
7958}
7959#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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