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x86: tighten condition for emitting LOCK on control register accesses
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e 434 && !defined (TE_NACL) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
a60de03c
JB		 563/* 1 if pseudo registers are permitted. */
564static int allow_pseudo_reg = 0;
565
47926f60
KH		 566/* 1 if register prefix % not required. */
567static int allow_naked_reg = 0;
252b5132 568
33eaf5de 569/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 570 instructions supporting it, even if this prefix wasn't specified
571 explicitly. */
572static int add_bnd_prefix = 0;
573
ba104c83 574/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 575static int allow_index_reg = 0;
576
d022bddd
IT		 577/* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579static int omit_lock_prefix = 0;
580
e4e00185
AS		 581/* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583static int avoid_fence = 0;
584
0cb4071e
L		 585/* 1 if the assembler should generate relax relocations. */
586
587static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589
7bab8ab5 590static enum check_kind
daf50ae7 591 {
7bab8ab5
JB		 592 check_none = 0,
593 check_warning,
594 check_error
daf50ae7 595 }
7bab8ab5 596sse_check, operand_check = check_warning;
daf50ae7 597
b6f8c7c4
L		 598/* Optimization:
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
601 register.
602 */
603static int optimize = 0;
604
605/* Optimization:
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
608 register.
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
610 "testb $imm7,%r8".
611 */
612static int optimize_for_space = 0;
613
2ca3ace5
L		 614/* Register prefix used for error message. */
615static const char *register_prefix = "%";
616
47926f60
KH		 617/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620static char stackop_size = '\0';
eecb386c 621
12b55ccc
L		 622/* Non-zero to optimize code alignment. */
623int optimize_align_code = 1;
624
47926f60
KH		 625/* Non-zero to quieten some warnings. */
626static int quiet_warnings = 0;
a38cf1db 627
47926f60
KH		 628/* CPU name. */
629static const char *cpu_arch_name = NULL;
6305a203 630static char *cpu_sub_arch_name = NULL;
a38cf1db 631
47926f60 632/* CPU feature flags. */
40fb9820
L		 633static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
634
ccc9c027
L		 635/* If we have selected a cpu we are generating instructions for. */
636static int cpu_arch_tune_set = 0;
637
9103f4f4 638/* Cpu we are generating instructions for. */
fbf3f584 639enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 640
641/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 642static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 643
ccc9c027 644/* CPU instruction set architecture used. */
fbf3f584 645enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 646
9103f4f4 647/* CPU feature flags of instruction set architecture used. */
fbf3f584 648i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 649
fddf5b5b
AM		 650/* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652static unsigned int no_cond_jump_promotion = 0;
653
c0f3af97
L		 654/* Encode SSE instructions with VEX prefix. */
655static unsigned int sse2avx;
656
539f890d
L		 657/* Encode scalar AVX instructions with specific vector length. */
658static enum
659 {
660 vex128 = 0,
661 vex256
662 } avxscalar;
663
43234a1e
L		 664/* Encode scalar EVEX LIG instructions with specific vector length. */
665static enum
666 {
667 evexl128 = 0,
668 evexl256,
669 evexl512
670 } evexlig;
671
672/* Encode EVEX WIG instructions with specific evex.w. */
673static enum
674 {
675 evexw0 = 0,
676 evexw1
677 } evexwig;
678
d3d3c6db
IT		 679/* Value to encode in EVEX RC bits, for SAE-only instructions. */
680static enum rc_type evexrcig = rne;
681
29b0f896 682/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 683static symbolS *GOT_symbol;
29b0f896 684
a4447b93
RH		 685/* The dwarf2 return column, adjusted for 32 or 64 bit. */
686unsigned int x86_dwarf2_return_column;
687
688/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689int x86_cie_data_alignment;
690
252b5132 691/* Interface to relax_segment.
fddf5b5b
AM		 692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
252b5132 695
47926f60 696/* Types. */
93c2a809
AM		 697#define UNCOND_JUMP 0
698#define COND_JUMP 1
699#define COND_JUMP86 2
fddf5b5b 700
47926f60 701/* Sizes. */
252b5132
RH		 702#define CODE16 1
703#define SMALL 0
29b0f896 704#define SMALL16 (SMALL | CODE16)
252b5132 705#define BIG 2
29b0f896 706#define BIG16 (BIG | CODE16)
252b5132
RH		 707
708#ifndef INLINE
709#ifdef __GNUC__
710#define INLINE __inline__
711#else
712#define INLINE
713#endif
714#endif
715
fddf5b5b
AM		 716#define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718#define TYPE_FROM_RELAX_STATE(s) \
719 ((s) >> 2)
720#define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 722
723/* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
730
731const relax_typeS md_relax_table[] =
732{
24eab124
AM		 733 /* The fields are:
734 1) most positive reach of this state,
735 2) most negative reach of this state,
93c2a809 736 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 737 4) which index into the table to try if we can't fit into this one. */
252b5132 738
fddf5b5b 739 /* UNCOND_JUMP states. */
93c2a809
AM		 740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
252b5132 744 {0, 0, 4, 0},
93c2a809
AM		 745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 747 {0, 0, 2, 0},
748
93c2a809
AM		 749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
754 {0, 0, 5, 0},
fddf5b5b 755 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 756 1 extra opcode byte, 2 displacement bytes. */
757 {0, 0, 3, 0},
758
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
764 {0, 0, 5, 0},
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
767 {0, 0, 4, 0}
252b5132
RH		 768};
769
9103f4f4
L		 770static const arch_entry cpu_arch[] =
771{
89507696
JB		 772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
8a2c8fef 774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 775 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 777 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 779 CPU_NONE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 781 CPU_I186_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 783 CPU_I286_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 785 CPU_I386_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 787 CPU_I486_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 789 CPU_I586_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 791 CPU_I686_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 793 CPU_I586_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 795 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 797 CPU_P2_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 799 CPU_P3_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 801 CPU_P4_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 803 CPU_CORE_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 805 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 807 CPU_CORE_FLAGS, 1 },
8a2c8fef 808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 809 CPU_CORE_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 811 CPU_CORE2_FLAGS, 1 },
8a2c8fef 812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 813 CPU_CORE2_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 815 CPU_COREI7_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 817 CPU_L1OM_FLAGS, 0 },
7a9068fe 818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 819 CPU_K1OM_FLAGS, 0 },
81486035 820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 821 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 823 CPU_K6_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 825 CPU_K6_2_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 827 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 829 CPU_K8_FLAGS, 1 },
8a2c8fef 830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 831 CPU_K8_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 833 CPU_K8_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 835 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 837 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 839 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 841 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 843 CPU_BDVER4_FLAGS, 0 },
029f3522 844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 845 CPU_ZNVER1_FLAGS, 0 },
a9660a6f
AP		 846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
847 CPU_ZNVER2_FLAGS, 0 },
7b458c12 848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 849 CPU_BTVER1_FLAGS, 0 },
7b458c12 850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 851 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_8087_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_287_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_387_FLAGS, 0 },
1848e567
L		 858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 CPU_687_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_MMX_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_SSE_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_SSE2_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_SSE3_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX_FLAGS, 0 },
6c30d220 878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_AVX2_FLAGS, 0 },
43234a1e 880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_AVX512F_FLAGS, 0 },
43234a1e 882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_AVX512CD_FLAGS, 0 },
43234a1e 884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_AVX512ER_FLAGS, 0 },
43234a1e 886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_VMX_FLAGS, 0 },
8729a6f6 896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_SMX_FLAGS, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_AES_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_F16C_FLAGS, 0 },
6c30d220 920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_BMI2_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_FMA_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_FMA4_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_XOP_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_LWP_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_MOVBE_FLAGS, 0 },
60aa667e 932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_CX16_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_EPT_FLAGS, 0 },
6c30d220 936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_LZCNT_FLAGS, 0 },
42164a71 938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_HLE_FLAGS, 0 },
42164a71 940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_RTM_FLAGS, 0 },
6c30d220 942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_CLFLUSH_FLAGS, 0 },
22109423 946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_NOP_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_SVME_FLAGS, 1 },
8a2c8fef 960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SVME_FLAGS, 0 },
8a2c8fef 962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_ABM_FLAGS, 0 },
87973e9f 966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_BMI_FLAGS, 0 },
2a2a0f38 968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_TBM_FLAGS, 0 },
e2e1fcde 970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_ADX_FLAGS, 0 },
e2e1fcde 972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_PRFCHW_FLAGS, 0 },
5c111e37 976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_SMAP_FLAGS, 0 },
7e8b059b 978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 979 CPU_MPX_FLAGS, 0 },
a0046408 980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 981 CPU_SHA_FLAGS, 0 },
963f3586 982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_SE1_FLAGS, 0 },
c5e7287a 988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1007 CPU_CLZERO_FLAGS, 0 },
9916071f 1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1009 CPU_MWAITX_FLAGS, 0 },
8eab4136 1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1011 CPU_OSPKE_FLAGS, 0 },
8bc52696 1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1013 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1015 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 CPU_IBT_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1019 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1021 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1023 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1025 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1027 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1029 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1031 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1033 CPU_CLDEMOTE_FLAGS, 0 },
c0a30a9f
L		 1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIRI_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIR64B_FLAGS, 0 },
293f5f65
L		 1038};
1039
1040static const noarch_entry cpu_noarch[] =
1041{
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
c0a30a9f
L		 1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
e413e4e9
AM		 1075};
1076
704209c0 1077#ifdef I386COFF
a6c24e68
NC		 1078/* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1080
1081static symbolS *
1082pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1083{
1084 addressT align = 0;
1085
1086 SKIP_WHITESPACE ();
1087
7ab9ffdd 1088 if (needs_align
a6c24e68
NC		 1089 && *input_line_pointer == ',')
1090 {
1091 align = parse_align (needs_align - 1);
7ab9ffdd 1092
a6c24e68
NC		 1093 if (align == (addressT) -1)
1094 return NULL;
1095 }
1096 else
1097 {
1098 if (size >= 8)
1099 align = 3;
1100 else if (size >= 4)
1101 align = 2;
1102 else if (size >= 2)
1103 align = 1;
1104 else
1105 align = 0;
1106 }
1107
1108 bss_alloc (symbolP, size, align);
1109 return symbolP;
1110}
1111
704209c0 1112static void
a6c24e68
NC		 1113pe_lcomm (int needs_align)
1114{
1115 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1116}
704209c0 1117#endif
a6c24e68 1118
29b0f896
AM		 1119const pseudo_typeS md_pseudo_table[] =
1120{
1121#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes, 0},
1123#else
1124 {"align", s_align_ptwo, 0},
1125#endif
1126 {"arch", set_cpu_arch, 0},
1127#ifndef I386COFF
1128 {"bss", s_bss, 0},
a6c24e68
NC		 1129#else
1130 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1131#endif
1132 {"ffloat", float_cons, 'f'},
1133 {"dfloat", float_cons, 'd'},
1134 {"tfloat", float_cons, 'x'},
1135 {"value", cons, 2},
d182319b 1136 {"slong", signed_cons, 4},
29b0f896
AM		 1137 {"noopt", s_ignore, 0},
1138 {"optim", s_ignore, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1140 {"code16", set_code_flag, CODE_16BIT},
1141 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1142#ifdef BFD64
29b0f896 1143 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1144#endif
29b0f896
AM		 1145 {"intel_syntax", set_intel_syntax, 1},
1146 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1147 {"intel_mnemonic", set_intel_mnemonic, 1},
1148 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1149 {"allow_index_reg", set_allow_index_reg, 1},
1150 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1151 {"sse_check", set_check, 0},
1152 {"operand_check", set_check, 1},
3b22753a
L		 1153#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common, 0},
07a53e5c 1155#else
68d20676 1156 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1157 {"loc", dwarf2_directive_loc, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1159#endif
6482c264
NC		 1160#ifdef TE_PE
1161 {"secrel32", pe_directive_secrel, 0},
1162#endif
29b0f896
AM		 1163 {0, 0, 0}
1164};
1165
1166/* For interface with expression (). */
1167extern char *input_line_pointer;
1168
1169/* Hash table for instruction mnemonic lookup. */
1170static struct hash_control *op_hash;
1171
1172/* Hash table for register lookup. */
1173static struct hash_control *reg_hash;
1174\f
ce8a8b2f
AM		 1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
62a02d25
L		 1178static const unsigned char f32_1[] =
1179 {0x90}; /* nop */
1180static const unsigned char f32_2[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182static const unsigned char f32_3[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184static const unsigned char f32_4[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1186static const unsigned char f32_6[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188static const unsigned char f32_7[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1190static const unsigned char f16_3[] =
3ae729d5 1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1192static const unsigned char f16_4[] =
3ae729d5
L		 1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194static const unsigned char jump_disp8[] =
1195 {0xeb}; /* jmp disp8 */
1196static const unsigned char jump32_disp32[] =
1197 {0xe9}; /* jmp disp32 */
1198static const unsigned char jump16_disp32[] =
1199 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1200/* 32-bit NOPs patterns. */
1201static const unsigned char *const f32_patt[] = {
3ae729d5 1202 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1203};
1204/* 16-bit NOPs patterns. */
1205static const unsigned char *const f16_patt[] = {
3ae729d5 1206 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1207};
1208/* nopl (%[re]ax) */
1209static const unsigned char alt_3[] =
1210 {0x0f,0x1f,0x00};
1211/* nopl 0(%[re]ax) */
1212static const unsigned char alt_4[] =
1213 {0x0f,0x1f,0x40,0x00};
1214/* nopl 0(%[re]ax,%[re]ax,1) */
1215static const unsigned char alt_5[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217/* nopw 0(%[re]ax,%[re]ax,1) */
1218static const unsigned char alt_6[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220/* nopl 0L(%[re]ax) */
1221static const unsigned char alt_7[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223/* nopl 0L(%[re]ax,%[re]ax,1) */
1224static const unsigned char alt_8[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226/* nopw 0L(%[re]ax,%[re]ax,1) */
1227static const unsigned char alt_9[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230static const unsigned char alt_10[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1232/* data16 nopw %cs:0L(%eax,%eax,1) */
1233static const unsigned char alt_11[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1235/* 32-bit and 64-bit NOPs patterns. */
1236static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1238 alt_9, alt_10, alt_11
62a02d25
L		 1239};
1240
1241/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1243
1244static void
1245i386_output_nops (char *where, const unsigned char *const *patt,
1246 int count, int max_single_nop_size)
1247
1248{
3ae729d5
L		 1249 /* Place the longer NOP first. */
1250 int last;
1251 int offset;
1252 const unsigned char *nops = patt[max_single_nop_size - 1];
1253
1254 /* Use the smaller one if the requsted one isn't available. */
1255 if (nops == NULL)
62a02d25 1256 {
3ae729d5
L		 1257 max_single_nop_size--;
1258 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1259 }
1260
3ae729d5
L		 1261 last = count % max_single_nop_size;
1262
1263 count -= last;
1264 for (offset = 0; offset < count; offset += max_single_nop_size)
1265 memcpy (where + offset, nops, max_single_nop_size);
1266
1267 if (last)
1268 {
1269 nops = patt[last - 1];
1270 if (nops == NULL)
1271 {
1272 /* Use the smaller one plus one-byte NOP if the needed one
1273 isn't available. */
1274 last--;
1275 nops = patt[last - 1];
1276 memcpy (where + offset, nops, last);
1277 where[offset + last] = *patt[0];
1278 }
1279 else
1280 memcpy (where + offset, nops, last);
1281 }
62a02d25
L		 1282}
1283
3ae729d5
L		 1284static INLINE int
1285fits_in_imm7 (offsetT num)
1286{
1287 return (num & 0x7f) == num;
1288}
1289
1290static INLINE int
1291fits_in_imm31 (offsetT num)
1292{
1293 return (num & 0x7fffffff) == num;
1294}
62a02d25
L		 1295
1296/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1298
1299void
3ae729d5 1300i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1301{
3ae729d5 1302 const unsigned char *const *patt = NULL;
62a02d25 1303 int max_single_nop_size;
3ae729d5
L		 1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops;
62a02d25 1306
3ae729d5 1307 switch (fragP->fr_type)
62a02d25 1308 {
3ae729d5
L		 1309 case rs_fill_nop:
1310 case rs_align_code:
1311 break;
1312 default:
62a02d25
L		 1313 return;
1314 }
1315
ccc9c027
L		 1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
4eed87de 1318
76bc74dc
L		 1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1321 2. For the rest, alt_patt will be used.
1322
1323 When -mtune= isn't used, alt_patt will be used if
22109423 1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1325 be used.
ccc9c027
L		 1326
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1329
1330 if (flag_code == CODE_16BIT)
1331 {
3ae729d5
L		 1332 patt = f16_patt;
1333 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops = 2;
252b5132 1336 }
33fef721 1337 else
ccc9c027 1338 {
fbf3f584 1339 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1340 {
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune)
1343 {
1344 case PROCESSOR_UNKNOWN:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1346 optimize with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1348 patt = alt_patt;
ccc9c027
L		 1349 else
1350 patt = f32_patt;
1351 break;
ccc9c027
L		 1352 case PROCESSOR_PENTIUM4:
1353 case PROCESSOR_NOCONA:
ef05d495 1354 case PROCESSOR_CORE:
76bc74dc 1355 case PROCESSOR_CORE2:
bd5295b2 1356 case PROCESSOR_COREI7:
3632d14b 1357 case PROCESSOR_L1OM:
7a9068fe 1358 case PROCESSOR_K1OM:
76bc74dc 1359 case PROCESSOR_GENERIC64:
ccc9c027
L		 1360 case PROCESSOR_K6:
1361 case PROCESSOR_ATHLON:
1362 case PROCESSOR_K8:
4eed87de 1363 case PROCESSOR_AMDFAM10:
8aedb9fe 1364 case PROCESSOR_BD:
029f3522 1365 case PROCESSOR_ZNVER:
7b458c12 1366 case PROCESSOR_BT:
80b8656c 1367 patt = alt_patt;
ccc9c027 1368 break;
76bc74dc 1369 case PROCESSOR_I386:
ccc9c027
L		 1370 case PROCESSOR_I486:
1371 case PROCESSOR_PENTIUM:
2dde1948 1372 case PROCESSOR_PENTIUMPRO:
81486035 1373 case PROCESSOR_IAMCU:
ccc9c027
L		 1374 case PROCESSOR_GENERIC32:
1375 patt = f32_patt;
1376 break;
4eed87de 1377 }
ccc9c027
L		 1378 }
1379 else
1380 {
fbf3f584 1381 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1382 {
1383 case PROCESSOR_UNKNOWN:
e6a14101 1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1385 PROCESSOR_UNKNOWN. */
1386 abort ();
1387 break;
1388
76bc74dc 1389 case PROCESSOR_I386:
ccc9c027
L		 1390 case PROCESSOR_I486:
1391 case PROCESSOR_PENTIUM:
81486035 1392 case PROCESSOR_IAMCU:
ccc9c027
L		 1393 case PROCESSOR_K6:
1394 case PROCESSOR_ATHLON:
1395 case PROCESSOR_K8:
4eed87de 1396 case PROCESSOR_AMDFAM10:
8aedb9fe 1397 case PROCESSOR_BD:
029f3522 1398 case PROCESSOR_ZNVER:
7b458c12 1399 case PROCESSOR_BT:
ccc9c027
L		 1400 case PROCESSOR_GENERIC32:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1402 with nops. */
1403 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1404 patt = alt_patt;
ccc9c027
L		 1405 else
1406 patt = f32_patt;
1407 break;
76bc74dc
L		 1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_PENTIUM4:
1410 case PROCESSOR_NOCONA:
1411 case PROCESSOR_CORE:
ef05d495 1412 case PROCESSOR_CORE2:
bd5295b2 1413 case PROCESSOR_COREI7:
3632d14b 1414 case PROCESSOR_L1OM:
7a9068fe 1415 case PROCESSOR_K1OM:
22109423 1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1417 patt = alt_patt;
ccc9c027
L		 1418 else
1419 patt = f32_patt;
1420 break;
1421 case PROCESSOR_GENERIC64:
80b8656c 1422 patt = alt_patt;
ccc9c027 1423 break;
4eed87de 1424 }
ccc9c027
L		 1425 }
1426
76bc74dc
L		 1427 if (patt == f32_patt)
1428 {
3ae729d5
L		 1429 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops = 2;
76bc74dc
L		 1432 }
1433 else
1434 {
3ae729d5
L		 1435 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops = 7;
1438 }
1439 }
1440
1441 if (limit == 0)
1442 limit = max_single_nop_size;
1443
1444 if (fragP->fr_type == rs_fill_nop)
1445 {
1446 /* Output NOPs for .nop directive. */
1447 if (limit > max_single_nop_size)
1448 {
1449 as_bad_where (fragP->fr_file, fragP->fr_line,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit, max_single_nop_size);
1453 return;
1454 }
1455 }
1456 else
1457 fragP->fr_var = count;
1458
1459 if ((count / max_single_nop_size) > max_number_of_nops)
1460 {
1461 /* Generate jump over NOPs. */
1462 offsetT disp = count - 2;
1463 if (fits_in_imm7 (disp))
1464 {
1465 /* Use "jmp disp8" if possible. */
1466 count = disp;
1467 where[0] = jump_disp8[0];
1468 where[1] = count;
1469 where += 2;
1470 }
1471 else
1472 {
1473 unsigned int size_of_jump;
1474
1475 if (flag_code == CODE_16BIT)
1476 {
1477 where[0] = jump16_disp32[0];
1478 where[1] = jump16_disp32[1];
1479 size_of_jump = 2;
1480 }
1481 else
1482 {
1483 where[0] = jump32_disp32[0];
1484 size_of_jump = 1;
1485 }
1486
1487 count -= size_of_jump + 4;
1488 if (!fits_in_imm31 (count))
1489 {
1490 as_bad_where (fragP->fr_file, fragP->fr_line,
1491 _("jump over nop padding out of range"));
1492 return;
1493 }
1494
1495 md_number_to_chars (where + size_of_jump, count, 4);
1496 where += size_of_jump + 4;
76bc74dc 1497 }
ccc9c027 1498 }
3ae729d5
L		 1499
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1502}
1503
c6fb90c8 1504static INLINE int
0dfbf9d7 1505operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1506{
0dfbf9d7 1507 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1508 {
1509 case 3:
0dfbf9d7 1510 if (x->array[2])
c6fb90c8 1511 return 0;
1a0670f3 1512 /* Fall through. */
c6fb90c8 1513 case 2:
0dfbf9d7 1514 if (x->array[1])
c6fb90c8 1515 return 0;
1a0670f3 1516 /* Fall through. */
c6fb90c8 1517 case 1:
0dfbf9d7 1518 return !x->array[0];
c6fb90c8
L		 1519 default:
1520 abort ();
1521 }
40fb9820
L		 1522}
1523
c6fb90c8 1524static INLINE void
0dfbf9d7 1525operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1526{
0dfbf9d7 1527 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1528 {
1529 case 3:
0dfbf9d7 1530 x->array[2] = v;
1a0670f3 1531 /* Fall through. */
c6fb90c8 1532 case 2:
0dfbf9d7 1533 x->array[1] = v;
1a0670f3 1534 /* Fall through. */
c6fb90c8 1535 case 1:
0dfbf9d7 1536 x->array[0] = v;
1a0670f3 1537 /* Fall through. */
c6fb90c8
L		 1538 break;
1539 default:
1540 abort ();
1541 }
1542}
40fb9820 1543
c6fb90c8 1544static INLINE int
0dfbf9d7
L		 1545operand_type_equal (const union i386_operand_type *x,
1546 const union i386_operand_type *y)
c6fb90c8 1547{
0dfbf9d7 1548 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1549 {
1550 case 3:
0dfbf9d7 1551 if (x->array[2] != y->array[2])
c6fb90c8 1552 return 0;
1a0670f3 1553 /* Fall through. */
c6fb90c8 1554 case 2:
0dfbf9d7 1555 if (x->array[1] != y->array[1])
c6fb90c8 1556 return 0;
1a0670f3 1557 /* Fall through. */
c6fb90c8 1558 case 1:
0dfbf9d7 1559 return x->array[0] == y->array[0];
c6fb90c8
L		 1560 break;
1561 default:
1562 abort ();
1563 }
1564}
40fb9820 1565
0dfbf9d7
L		 1566static INLINE int
1567cpu_flags_all_zero (const union i386_cpu_flags *x)
1568{
1569 switch (ARRAY_SIZE(x->array))
1570 {
53467f57
IT		 1571 case 4:
1572 if (x->array[3])
1573 return 0;
1574 /* Fall through. */
0dfbf9d7
L		 1575 case 3:
1576 if (x->array[2])
1577 return 0;
1a0670f3 1578 /* Fall through. */
0dfbf9d7
L		 1579 case 2:
1580 if (x->array[1])
1581 return 0;
1a0670f3 1582 /* Fall through. */
0dfbf9d7
L		 1583 case 1:
1584 return !x->array[0];
1585 default:
1586 abort ();
1587 }
1588}
1589
0dfbf9d7
L		 1590static INLINE int
1591cpu_flags_equal (const union i386_cpu_flags *x,
1592 const union i386_cpu_flags *y)
1593{
1594 switch (ARRAY_SIZE(x->array))
1595 {
53467f57
IT		 1596 case 4:
1597 if (x->array[3] != y->array[3])
1598 return 0;
1599 /* Fall through. */
0dfbf9d7
L		 1600 case 3:
1601 if (x->array[2] != y->array[2])
1602 return 0;
1a0670f3 1603 /* Fall through. */
0dfbf9d7
L		 1604 case 2:
1605 if (x->array[1] != y->array[1])
1606 return 0;
1a0670f3 1607 /* Fall through. */
0dfbf9d7
L		 1608 case 1:
1609 return x->array[0] == y->array[0];
1610 break;
1611 default:
1612 abort ();
1613 }
1614}
c6fb90c8
L		 1615
1616static INLINE int
1617cpu_flags_check_cpu64 (i386_cpu_flags f)
1618{
1619 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1620 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1621}
1622
c6fb90c8
L		 1623static INLINE i386_cpu_flags
1624cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1625{
c6fb90c8
L		 1626 switch (ARRAY_SIZE (x.array))
1627 {
53467f57
IT		 1628 case 4:
1629 x.array [3] &= y.array [3];
1630 /* Fall through. */
c6fb90c8
L		 1631 case 3:
1632 x.array [2] &= y.array [2];
1a0670f3 1633 /* Fall through. */
c6fb90c8
L		 1634 case 2:
1635 x.array [1] &= y.array [1];
1a0670f3 1636 /* Fall through. */
c6fb90c8
L		 1637 case 1:
1638 x.array [0] &= y.array [0];
1639 break;
1640 default:
1641 abort ();
1642 }
1643 return x;
1644}
40fb9820 1645
c6fb90c8
L		 1646static INLINE i386_cpu_flags
1647cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1648{
c6fb90c8 1649 switch (ARRAY_SIZE (x.array))
40fb9820 1650 {
53467f57
IT		 1651 case 4:
1652 x.array [3] |= y.array [3];
1653 /* Fall through. */
c6fb90c8
L		 1654 case 3:
1655 x.array [2] |= y.array [2];
1a0670f3 1656 /* Fall through. */
c6fb90c8
L		 1657 case 2:
1658 x.array [1] |= y.array [1];
1a0670f3 1659 /* Fall through. */
c6fb90c8
L		 1660 case 1:
1661 x.array [0] |= y.array [0];
40fb9820
L		 1662 break;
1663 default:
1664 abort ();
1665 }
40fb9820
L		 1666 return x;
1667}
1668
309d3373
JB		 1669static INLINE i386_cpu_flags
1670cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1671{
1672 switch (ARRAY_SIZE (x.array))
1673 {
53467f57
IT		 1674 case 4:
1675 x.array [3] &= ~y.array [3];
1676 /* Fall through. */
309d3373
JB		 1677 case 3:
1678 x.array [2] &= ~y.array [2];
1a0670f3 1679 /* Fall through. */
309d3373
JB		 1680 case 2:
1681 x.array [1] &= ~y.array [1];
1a0670f3 1682 /* Fall through. */
309d3373
JB		 1683 case 1:
1684 x.array [0] &= ~y.array [0];
1685 break;
1686 default:
1687 abort ();
1688 }
1689 return x;
1690}
1691
c0f3af97
L		 1692#define CPU_FLAGS_ARCH_MATCH 0x1
1693#define CPU_FLAGS_64BIT_MATCH 0x2
1694
c0f3af97 1695#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1697
1698/* Return CPU flags match bits. */
3629bb00 1699
40fb9820 1700static int
d3ce72d0 1701cpu_flags_match (const insn_template *t)
40fb9820 1702{
c0f3af97
L		 1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1705
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1708
0dfbf9d7 1709 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1710 {
1711 /* This instruction is available on all archs. */
db12e14e 1712 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1713 }
3629bb00
L		 1714 else
1715 {
c0f3af97 1716 /* This instruction is available only on some archs. */
3629bb00
L		 1717 i386_cpu_flags cpu = cpu_arch_flags;
1718
ab592e75
JB		 1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1721 return match;
1722 x.bitfield.cpuavx512vl = 0;
1723
3629bb00 1724 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1725 if (!cpu_flags_all_zero (&cpu))
1726 {
a5ff0eb2
L		 1727 if (x.bitfield.cpuavx)
1728 {
929f69fa 1729 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1730 if (cpu.bitfield.cpuavx
1731 && (!t->opcode_modifier.sse2avx || sse2avx)
1732 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1734 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1735 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1736 }
929f69fa
JB		 1737 else if (x.bitfield.cpuavx512f)
1738 {
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu.bitfield.cpuavx512f
1741 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1742 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1743 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1744 match |= CPU_FLAGS_ARCH_MATCH;
1745 }
a5ff0eb2 1746 else
db12e14e 1747 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1748 }
3629bb00 1749 }
c0f3af97 1750 return match;
40fb9820
L		 1751}
1752
c6fb90c8
L		 1753static INLINE i386_operand_type
1754operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1755{
c6fb90c8
L		 1756 switch (ARRAY_SIZE (x.array))
1757 {
1758 case 3:
1759 x.array [2] &= y.array [2];
1a0670f3 1760 /* Fall through. */
c6fb90c8
L		 1761 case 2:
1762 x.array [1] &= y.array [1];
1a0670f3 1763 /* Fall through. */
c6fb90c8
L		 1764 case 1:
1765 x.array [0] &= y.array [0];
1766 break;
1767 default:
1768 abort ();
1769 }
1770 return x;
40fb9820
L		 1771}
1772
73053c1f
JB		 1773static INLINE i386_operand_type
1774operand_type_and_not (i386_operand_type x, i386_operand_type y)
1775{
1776 switch (ARRAY_SIZE (x.array))
1777 {
1778 case 3:
1779 x.array [2] &= ~y.array [2];
1780 /* Fall through. */
1781 case 2:
1782 x.array [1] &= ~y.array [1];
1783 /* Fall through. */
1784 case 1:
1785 x.array [0] &= ~y.array [0];
1786 break;
1787 default:
1788 abort ();
1789 }
1790 return x;
1791}
1792
c6fb90c8
L		 1793static INLINE i386_operand_type
1794operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1795{
c6fb90c8 1796 switch (ARRAY_SIZE (x.array))
40fb9820 1797 {
c6fb90c8
L		 1798 case 3:
1799 x.array [2] |= y.array [2];
1a0670f3 1800 /* Fall through. */
c6fb90c8
L		 1801 case 2:
1802 x.array [1] |= y.array [1];
1a0670f3 1803 /* Fall through. */
c6fb90c8
L		 1804 case 1:
1805 x.array [0] |= y.array [0];
40fb9820
L		 1806 break;
1807 default:
1808 abort ();
1809 }
c6fb90c8
L		 1810 return x;
1811}
40fb9820 1812
c6fb90c8
L		 1813static INLINE i386_operand_type
1814operand_type_xor (i386_operand_type x, i386_operand_type y)
1815{
1816 switch (ARRAY_SIZE (x.array))
1817 {
1818 case 3:
1819 x.array [2] ^= y.array [2];
1a0670f3 1820 /* Fall through. */
c6fb90c8
L		 1821 case 2:
1822 x.array [1] ^= y.array [1];
1a0670f3 1823 /* Fall through. */
c6fb90c8
L		 1824 case 1:
1825 x.array [0] ^= y.array [0];
1826 break;
1827 default:
1828 abort ();
1829 }
40fb9820
L		 1830 return x;
1831}
1832
1833static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1834static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1835static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1836static const i386_operand_type inoutportreg
1837 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1838static const i386_operand_type reg16_inoutportreg
1839 = OPERAND_TYPE_REG16_INOUTPORTREG;
1840static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1841static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1842static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1843static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1844static const i386_operand_type anydisp
1845 = OPERAND_TYPE_ANYDISP;
40fb9820 1846static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1847static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1848static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1849static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1850static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1851static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1852static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1853static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1854static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1855static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1856static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1857static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1858
1859enum operand_type
1860{
1861 reg,
40fb9820
L		 1862 imm,
1863 disp,
1864 anymem
1865};
1866
c6fb90c8 1867static INLINE int
40fb9820
L		 1868operand_type_check (i386_operand_type t, enum operand_type c)
1869{
1870 switch (c)
1871 {
1872 case reg:
dc821c5f 1873 return t.bitfield.reg;
40fb9820 1874
40fb9820
L		 1875 case imm:
1876 return (t.bitfield.imm8
1877 || t.bitfield.imm8s
1878 || t.bitfield.imm16
1879 || t.bitfield.imm32
1880 || t.bitfield.imm32s
1881 || t.bitfield.imm64);
1882
1883 case disp:
1884 return (t.bitfield.disp8
1885 || t.bitfield.disp16
1886 || t.bitfield.disp32
1887 || t.bitfield.disp32s
1888 || t.bitfield.disp64);
1889
1890 case anymem:
1891 return (t.bitfield.disp8
1892 || t.bitfield.disp16
1893 || t.bitfield.disp32
1894 || t.bitfield.disp32s
1895 || t.bitfield.disp64
1896 || t.bitfield.baseindex);
1897
1898 default:
1899 abort ();
1900 }
2cfe26b6
AM		 1901
1902 return 0;
40fb9820
L		 1903}
1904
ca0d63fe 1905/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1906 operand J for instruction template T. */
1907
1908static INLINE int
d3ce72d0 1909match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1910{
1911 return !((i.types[j].bitfield.byte
1912 && !t->operand_types[j].bitfield.byte)
1913 || (i.types[j].bitfield.word
1914 && !t->operand_types[j].bitfield.word)
1915 || (i.types[j].bitfield.dword
1916 && !t->operand_types[j].bitfield.dword)
1917 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1918 && !t->operand_types[j].bitfield.qword)
1919 || (i.types[j].bitfield.tbyte
1920 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1921}
1922
1b54b8d7
JB		 1923/* Return 1 if there is no conflict in SIMD register on
1924 operand J for instruction template T. */
1925
1926static INLINE int
1927match_simd_size (const insn_template *t, unsigned int j)
1928{
1929 return !((i.types[j].bitfield.xmmword
1930 && !t->operand_types[j].bitfield.xmmword)
1931 || (i.types[j].bitfield.ymmword
1932 && !t->operand_types[j].bitfield.ymmword)
1933 || (i.types[j].bitfield.zmmword
1934 && !t->operand_types[j].bitfield.zmmword));
1935}
1936
5c07affc
L		 1937/* Return 1 if there is no conflict in any size on operand J for
1938 instruction template T. */
1939
1940static INLINE int
d3ce72d0 1941match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1942{
1943 return (match_reg_size (t, j)
1944 && !((i.types[j].bitfield.unspecified
af508cb9 1945 && !i.broadcast
5c07affc
L		 1946 && !t->operand_types[j].bitfield.unspecified)
1947 || (i.types[j].bitfield.fword
1948 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1949 /* For scalar opcode templates to allow register and memory
1950 operands at the same time, some special casing is needed
d6793fa1
JB		 1951 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1952 down-conversion vpmov*. */
1b54b8d7
JB		 1953 || ((t->operand_types[j].bitfield.regsimd
1954 && !t->opcode_modifier.broadcast
d6793fa1
JB		 1955 && (t->operand_types[j].bitfield.byte
1956 || t->operand_types[j].bitfield.word
1957 || t->operand_types[j].bitfield.dword
1b54b8d7
JB		 1958 || t->operand_types[j].bitfield.qword))
1959 ? (i.types[j].bitfield.xmmword
1960 || i.types[j].bitfield.ymmword
1961 || i.types[j].bitfield.zmmword)
1962 : !match_simd_size(t, j))));
5c07affc
L		 1963}
1964
1965/* Return 1 if there is no size conflict on any operands for
1966 instruction template T. */
1967
1968static INLINE int
d3ce72d0 1969operand_size_match (const insn_template *t)
5c07affc
L		 1970{
1971 unsigned int j;
1972 int match = 1;
1973
1974 /* Don't check jump instructions. */
1975 if (t->opcode_modifier.jump
1976 || t->opcode_modifier.jumpbyte
1977 || t->opcode_modifier.jumpdword
1978 || t->opcode_modifier.jumpintersegment)
1979 return match;
1980
1981 /* Check memory and accumulator operand size. */
1982 for (j = 0; j < i.operands; j++)
1983 {
1b54b8d7
JB		 1984 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1985 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1986 continue;
1987
1b54b8d7 1988 if (t->operand_types[j].bitfield.reg
dc821c5f 1989 && !match_reg_size (t, j))
5c07affc
L		 1990 {
1991 match = 0;
1992 break;
1993 }
1994
1b54b8d7
JB		 1995 if (t->operand_types[j].bitfield.regsimd
1996 && !match_simd_size (t, j))
1997 {
1998 match = 0;
1999 break;
2000 }
2001
2002 if (t->operand_types[j].bitfield.acc
2003 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
2004 {
2005 match = 0;
2006 break;
2007 }
2008
5c07affc
L		 2009 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2010 {
2011 match = 0;
2012 break;
2013 }
2014 }
2015
891edac4 2016 if (match)
5c07affc 2017 return match;
38e314eb 2018 else if (!t->opcode_modifier.d)
891edac4
L		 2019 {
2020mismatch:
86e026a4 2021 i.error = operand_size_mismatch;
891edac4
L		 2022 return 0;
2023 }
5c07affc
L		 2024
2025 /* Check reverse. */
9c2799c2 2026 gas_assert (i.operands == 2);
5c07affc
L		 2027
2028 match = 1;
2029 for (j = 0; j < 2; j++)
2030 {
dc821c5f
JB		 2031 if ((t->operand_types[j].bitfield.reg
2032 || t->operand_types[j].bitfield.acc)
5c07affc 2033 && !match_reg_size (t, j ? 0 : 1))
891edac4 2034 goto mismatch;
5c07affc
L		 2035
2036 if (i.types[j].bitfield.mem
2037 && !match_mem_size (t, j ? 0 : 1))
891edac4 2038 goto mismatch;
5c07affc
L		 2039 }
2040
2041 return match;
2042}
2043
c6fb90c8 2044static INLINE int
40fb9820
L		 2045operand_type_match (i386_operand_type overlap,
2046 i386_operand_type given)
2047{
2048 i386_operand_type temp = overlap;
2049
2050 temp.bitfield.jumpabsolute = 0;
7d5e4556 2051 temp.bitfield.unspecified = 0;
5c07affc
L		 2052 temp.bitfield.byte = 0;
2053 temp.bitfield.word = 0;
2054 temp.bitfield.dword = 0;
2055 temp.bitfield.fword = 0;
2056 temp.bitfield.qword = 0;
2057 temp.bitfield.tbyte = 0;
2058 temp.bitfield.xmmword = 0;
c0f3af97 2059 temp.bitfield.ymmword = 0;
43234a1e 2060 temp.bitfield.zmmword = 0;
0dfbf9d7 2061 if (operand_type_all_zero (&temp))
891edac4 2062 goto mismatch;
40fb9820 2063
891edac4
L		 2064 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2065 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2066 return 1;
2067
2068mismatch:
a65babc9 2069 i.error = operand_type_mismatch;
891edac4 2070 return 0;
40fb9820
L		 2071}
2072
7d5e4556 2073/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2074 unless the expected operand type register overlap is null.
2075 Memory operand size of certain SIMD instructions is also being checked
2076 here. */
40fb9820 2077
c6fb90c8 2078static INLINE int
dc821c5f 2079operand_type_register_match (i386_operand_type g0,
40fb9820 2080 i386_operand_type t0,
40fb9820
L		 2081 i386_operand_type g1,
2082 i386_operand_type t1)
2083{
10c17abd
JB		 2084 if (!g0.bitfield.reg
2085 && !g0.bitfield.regsimd
2086 && (!operand_type_check (g0, anymem)
2087 || g0.bitfield.unspecified
2088 || !t0.bitfield.regsimd))
40fb9820
L		 2089 return 1;
2090
10c17abd
JB		 2091 if (!g1.bitfield.reg
2092 && !g1.bitfield.regsimd
2093 && (!operand_type_check (g1, anymem)
2094 || g1.bitfield.unspecified
2095 || !t1.bitfield.regsimd))
40fb9820
L		 2096 return 1;
2097
dc821c5f
JB		 2098 if (g0.bitfield.byte == g1.bitfield.byte
2099 && g0.bitfield.word == g1.bitfield.word
2100 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2101 && g0.bitfield.qword == g1.bitfield.qword
2102 && g0.bitfield.xmmword == g1.bitfield.xmmword
2103 && g0.bitfield.ymmword == g1.bitfield.ymmword
2104 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2105 return 1;
2106
dc821c5f
JB		 2107 if (!(t0.bitfield.byte & t1.bitfield.byte)
2108 && !(t0.bitfield.word & t1.bitfield.word)
2109 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2110 && !(t0.bitfield.qword & t1.bitfield.qword)
2111 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2112 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2113 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2114 return 1;
2115
a65babc9 2116 i.error = register_type_mismatch;
891edac4
L		 2117
2118 return 0;
40fb9820
L		 2119}
2120
4c692bc7
JB		 2121static INLINE unsigned int
2122register_number (const reg_entry *r)
2123{
2124 unsigned int nr = r->reg_num;
2125
2126 if (r->reg_flags & RegRex)
2127 nr += 8;
2128
200cbe0f
L		 2129 if (r->reg_flags & RegVRex)
2130 nr += 16;
2131
4c692bc7
JB		 2132 return nr;
2133}
2134
252b5132 2135static INLINE unsigned int
40fb9820 2136mode_from_disp_size (i386_operand_type t)
252b5132 2137{
b5014f7a 2138 if (t.bitfield.disp8)
40fb9820
L		 2139 return 1;
2140 else if (t.bitfield.disp16
2141 || t.bitfield.disp32
2142 || t.bitfield.disp32s)
2143 return 2;
2144 else
2145 return 0;
252b5132
RH		 2146}
2147
2148static INLINE int
65879393 2149fits_in_signed_byte (addressT num)
252b5132 2150{
65879393 2151 return num + 0x80 <= 0xff;
47926f60 2152}
252b5132
RH		 2153
2154static INLINE int
65879393 2155fits_in_unsigned_byte (addressT num)
252b5132 2156{
65879393 2157 return num <= 0xff;
47926f60 2158}
252b5132
RH		 2159
2160static INLINE int
65879393 2161fits_in_unsigned_word (addressT num)
252b5132 2162{
65879393 2163 return num <= 0xffff;
47926f60 2164}
252b5132
RH		 2165
2166static INLINE int
65879393 2167fits_in_signed_word (addressT num)
252b5132 2168{
65879393 2169 return num + 0x8000 <= 0xffff;
47926f60 2170}
2a962e6d 2171
3e73aa7c 2172static INLINE int
65879393 2173fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2174{
2175#ifndef BFD64
2176 return 1;
2177#else
65879393 2178 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2179#endif
2180} /* fits_in_signed_long() */
2a962e6d 2181
3e73aa7c 2182static INLINE int
65879393 2183fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2184{
2185#ifndef BFD64
2186 return 1;
2187#else
65879393 2188 return num <= 0xffffffff;
3e73aa7c
JH		 2189#endif
2190} /* fits_in_unsigned_long() */
252b5132 2191
43234a1e 2192static INLINE int
b5014f7a 2193fits_in_disp8 (offsetT num)
43234a1e
L		 2194{
2195 int shift = i.memshift;
2196 unsigned int mask;
2197
2198 if (shift == -1)
2199 abort ();
2200
2201 mask = (1 << shift) - 1;
2202
2203 /* Return 0 if NUM isn't properly aligned. */
2204 if ((num & mask))
2205 return 0;
2206
2207 /* Check if NUM will fit in 8bit after shift. */
2208 return fits_in_signed_byte (num >> shift);
2209}
2210
a683cc34
SP		 2211static INLINE int
2212fits_in_imm4 (offsetT num)
2213{
2214 return (num & 0xf) == num;
2215}
2216
40fb9820 2217static i386_operand_type
e3bb37b5 2218smallest_imm_type (offsetT num)
252b5132 2219{
40fb9820 2220 i386_operand_type t;
7ab9ffdd 2221
0dfbf9d7 2222 operand_type_set (&t, 0);
40fb9820
L		 2223 t.bitfield.imm64 = 1;
2224
2225 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2226 {
2227 /* This code is disabled on the 486 because all the Imm1 forms
2228 in the opcode table are slower on the i486. They're the
2229 versions with the implicitly specified single-position
2230 displacement, which has another syntax if you really want to
2231 use that form. */
40fb9820
L		 2232 t.bitfield.imm1 = 1;
2233 t.bitfield.imm8 = 1;
2234 t.bitfield.imm8s = 1;
2235 t.bitfield.imm16 = 1;
2236 t.bitfield.imm32 = 1;
2237 t.bitfield.imm32s = 1;
2238 }
2239 else if (fits_in_signed_byte (num))
2240 {
2241 t.bitfield.imm8 = 1;
2242 t.bitfield.imm8s = 1;
2243 t.bitfield.imm16 = 1;
2244 t.bitfield.imm32 = 1;
2245 t.bitfield.imm32s = 1;
2246 }
2247 else if (fits_in_unsigned_byte (num))
2248 {
2249 t.bitfield.imm8 = 1;
2250 t.bitfield.imm16 = 1;
2251 t.bitfield.imm32 = 1;
2252 t.bitfield.imm32s = 1;
2253 }
2254 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2255 {
2256 t.bitfield.imm16 = 1;
2257 t.bitfield.imm32 = 1;
2258 t.bitfield.imm32s = 1;
2259 }
2260 else if (fits_in_signed_long (num))
2261 {
2262 t.bitfield.imm32 = 1;
2263 t.bitfield.imm32s = 1;
2264 }
2265 else if (fits_in_unsigned_long (num))
2266 t.bitfield.imm32 = 1;
2267
2268 return t;
47926f60 2269}
252b5132 2270
847f7ad4 2271static offsetT
e3bb37b5 2272offset_in_range (offsetT val, int size)
847f7ad4 2273{
508866be 2274 addressT mask;
ba2adb93 2275
847f7ad4
AM		 2276 switch (size)
2277 {
508866be
L		 2278 case 1: mask = ((addressT) 1 << 8) - 1; break;
2279 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2280 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2281#ifdef BFD64
2282 case 8: mask = ((addressT) 2 << 63) - 1; break;
2283#endif
47926f60 2284 default: abort ();
847f7ad4
AM		 2285 }
2286
9de868bf
L		 2287#ifdef BFD64
2288 /* If BFD64, sign extend val for 32bit address mode. */
2289 if (flag_code != CODE_64BIT
2290 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2291 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2292 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2293#endif
ba2adb93 2294
47926f60 2295 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2296 {
2297 char buf1[40], buf2[40];
2298
2299 sprint_value (buf1, val);
2300 sprint_value (buf2, val & mask);
2301 as_warn (_("%s shortened to %s"), buf1, buf2);
2302 }
2303 return val & mask;
2304}
2305
c32fa91d
L		 2306enum PREFIX_GROUP
2307{
2308 PREFIX_EXIST = 0,
2309 PREFIX_LOCK,
2310 PREFIX_REP,
04ef582a 2311 PREFIX_DS,
c32fa91d
L		 2312 PREFIX_OTHER
2313};
2314
2315/* Returns
2316 a. PREFIX_EXIST if attempting to add a prefix where one from the
2317 same class already exists.
2318 b. PREFIX_LOCK if lock prefix is added.
2319 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2320 d. PREFIX_DS if ds prefix is added.
2321 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2322 */
2323
2324static enum PREFIX_GROUP
e3bb37b5 2325add_prefix (unsigned int prefix)
252b5132 2326{
c32fa91d 2327 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2328 unsigned int q;
252b5132 2329
29b0f896
AM		 2330 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2331 && flag_code == CODE_64BIT)
b1905489 2332 {
161a04f6
L		 2333 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2334 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2335 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2336 ret = PREFIX_EXIST;
b1905489
JB		 2337 q = REX_PREFIX;
2338 }
3e73aa7c 2339 else
b1905489
JB		 2340 {
2341 switch (prefix)
2342 {
2343 default:
2344 abort ();
2345
b1905489 2346 case DS_PREFIX_OPCODE:
04ef582a
L		 2347 ret = PREFIX_DS;
2348 /* Fall through. */
2349 case CS_PREFIX_OPCODE:
b1905489
JB		 2350 case ES_PREFIX_OPCODE:
2351 case FS_PREFIX_OPCODE:
2352 case GS_PREFIX_OPCODE:
2353 case SS_PREFIX_OPCODE:
2354 q = SEG_PREFIX;
2355 break;
2356
2357 case REPNE_PREFIX_OPCODE:
2358 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2359 q = REP_PREFIX;
2360 ret = PREFIX_REP;
2361 break;
2362
b1905489 2363 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2364 q = LOCK_PREFIX;
2365 ret = PREFIX_LOCK;
b1905489
JB		 2366 break;
2367
2368 case FWAIT_OPCODE:
2369 q = WAIT_PREFIX;
2370 break;
2371
2372 case ADDR_PREFIX_OPCODE:
2373 q = ADDR_PREFIX;
2374 break;
2375
2376 case DATA_PREFIX_OPCODE:
2377 q = DATA_PREFIX;
2378 break;
2379 }
2380 if (i.prefix[q] != 0)
c32fa91d 2381 ret = PREFIX_EXIST;
b1905489 2382 }
252b5132 2383
b1905489 2384 if (ret)
252b5132 2385 {
b1905489
JB		 2386 if (!i.prefix[q])
2387 ++i.prefixes;
2388 i.prefix[q] |= prefix;
252b5132 2389 }
b1905489
JB		 2390 else
2391 as_bad (_("same type of prefix used twice"));
252b5132 2392
252b5132
RH		 2393 return ret;
2394}
2395
2396static void
78f12dd3 2397update_code_flag (int value, int check)
eecb386c 2398{
78f12dd3
L		 2399 PRINTF_LIKE ((*as_error));
2400
1e9cc1c2 2401 flag_code = (enum flag_code) value;
40fb9820
L		 2402 if (flag_code == CODE_64BIT)
2403 {
2404 cpu_arch_flags.bitfield.cpu64 = 1;
2405 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2406 }
2407 else
2408 {
2409 cpu_arch_flags.bitfield.cpu64 = 0;
2410 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2411 }
2412 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2413 {
78f12dd3
L		 2414 if (check)
2415 as_error = as_fatal;
2416 else
2417 as_error = as_bad;
2418 (*as_error) (_("64bit mode not supported on `%s'."),
2419 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2420 }
40fb9820 2421 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2422 {
78f12dd3
L		 2423 if (check)
2424 as_error = as_fatal;
2425 else
2426 as_error = as_bad;
2427 (*as_error) (_("32bit mode not supported on `%s'."),
2428 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2429 }
eecb386c
AM		 2430 stackop_size = '\0';
2431}
2432
78f12dd3
L		 2433static void
2434set_code_flag (int value)
2435{
2436 update_code_flag (value, 0);
2437}
2438
eecb386c 2439static void
e3bb37b5 2440set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2441{
1e9cc1c2 2442 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2443 if (flag_code != CODE_16BIT)
2444 abort ();
2445 cpu_arch_flags.bitfield.cpu64 = 0;
2446 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2447 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2448}
2449
2450static void
e3bb37b5 2451set_intel_syntax (int syntax_flag)
252b5132
RH		 2452{
2453 /* Find out if register prefixing is specified. */
2454 int ask_naked_reg = 0;
2455
2456 SKIP_WHITESPACE ();
29b0f896 2457 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2458 {
d02603dc
NC		 2459 char *string;
2460 int e = get_symbol_name (&string);
252b5132 2461
47926f60 2462 if (strcmp (string, "prefix") == 0)
252b5132 2463 ask_naked_reg = 1;
47926f60 2464 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2465 ask_naked_reg = -1;
2466 else
d0b47220 2467 as_bad (_("bad argument to syntax directive."));
d02603dc 2468 (void) restore_line_pointer (e);
252b5132
RH		 2469 }
2470 demand_empty_rest_of_line ();
c3332e24 2471
252b5132
RH		 2472 intel_syntax = syntax_flag;
2473
2474 if (ask_naked_reg == 0)
f86103b7
AM		 2475 allow_naked_reg = (intel_syntax
2476 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2477 else
2478 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2479
ee86248c 2480 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2481
e4a3b5a4 2482 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2483 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2484 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2485}
2486
1efbbeb4
L		 2487static void
2488set_intel_mnemonic (int mnemonic_flag)
2489{
e1d4d893 2490 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2491}
2492
db51cc60
L		 2493static void
2494set_allow_index_reg (int flag)
2495{
2496 allow_index_reg = flag;
2497}
2498
cb19c032 2499static void
7bab8ab5 2500set_check (int what)
cb19c032 2501{
7bab8ab5
JB		 2502 enum check_kind *kind;
2503 const char *str;
2504
2505 if (what)
2506 {
2507 kind = &operand_check;
2508 str = "operand";
2509 }
2510 else
2511 {
2512 kind = &sse_check;
2513 str = "sse";
2514 }
2515
cb19c032
L		 2516 SKIP_WHITESPACE ();
2517
2518 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2519 {
d02603dc
NC		 2520 char *string;
2521 int e = get_symbol_name (&string);
cb19c032
L		 2522
2523 if (strcmp (string, "none") == 0)
7bab8ab5 2524 *kind = check_none;
cb19c032 2525 else if (strcmp (string, "warning") == 0)
7bab8ab5 2526 *kind = check_warning;
cb19c032 2527 else if (strcmp (string, "error") == 0)
7bab8ab5 2528 *kind = check_error;
cb19c032 2529 else
7bab8ab5 2530 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2531 (void) restore_line_pointer (e);
cb19c032
L		 2532 }
2533 else
7bab8ab5 2534 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2535
2536 demand_empty_rest_of_line ();
2537}
2538
8a9036a4
L		 2539static void
2540check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2541 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2542{
2543#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2544 static const char *arch;
2545
2546 /* Intel LIOM is only supported on ELF. */
2547 if (!IS_ELF)
2548 return;
2549
2550 if (!arch)
2551 {
2552 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2553 use default_arch. */
2554 arch = cpu_arch_name;
2555 if (!arch)
2556 arch = default_arch;
2557 }
2558
81486035
L		 2559 /* If we are targeting Intel MCU, we must enable it. */
2560 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2561 || new_flag.bitfield.cpuiamcu)
2562 return;
2563
3632d14b 2564 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2565 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2566 || new_flag.bitfield.cpul1om)
8a9036a4 2567 return;
76ba9986 2568
7a9068fe
L		 2569 /* If we are targeting Intel K1OM, we must enable it. */
2570 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2571 || new_flag.bitfield.cpuk1om)
2572 return;
2573
8a9036a4
L		 2574 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2575#endif
2576}
2577
e413e4e9 2578static void
e3bb37b5 2579set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2580{
47926f60 2581 SKIP_WHITESPACE ();
e413e4e9 2582
29b0f896 2583 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2584 {
d02603dc
NC		 2585 char *string;
2586 int e = get_symbol_name (&string);
91d6fa6a 2587 unsigned int j;
40fb9820 2588 i386_cpu_flags flags;
e413e4e9 2589
91d6fa6a 2590 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2591 {
91d6fa6a 2592 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2593 {
91d6fa6a 2594 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2595
5c6af06e
JB		 2596 if (*string != '.')
2597 {
91d6fa6a 2598 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2599 cpu_sub_arch_name = NULL;
91d6fa6a 2600 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2601 if (flag_code == CODE_64BIT)
2602 {
2603 cpu_arch_flags.bitfield.cpu64 = 1;
2604 cpu_arch_flags.bitfield.cpuno64 = 0;
2605 }
2606 else
2607 {
2608 cpu_arch_flags.bitfield.cpu64 = 0;
2609 cpu_arch_flags.bitfield.cpuno64 = 1;
2610 }
91d6fa6a
NC		 2611 cpu_arch_isa = cpu_arch[j].type;
2612 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2613 if (!cpu_arch_tune_set)
2614 {
2615 cpu_arch_tune = cpu_arch_isa;
2616 cpu_arch_tune_flags = cpu_arch_isa_flags;
2617 }
5c6af06e
JB		 2618 break;
2619 }
40fb9820 2620
293f5f65
L		 2621 flags = cpu_flags_or (cpu_arch_flags,
2622 cpu_arch[j].flags);
81486035 2623
5b64d091 2624 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2625 {
6305a203
L		 2626 if (cpu_sub_arch_name)
2627 {
2628 char *name = cpu_sub_arch_name;
2629 cpu_sub_arch_name = concat (name,
91d6fa6a 2630 cpu_arch[j].name,
1bf57e9f 2631 (const char *) NULL);
6305a203
L		 2632 free (name);
2633 }
2634 else
91d6fa6a 2635 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2636 cpu_arch_flags = flags;
a586129e 2637 cpu_arch_isa_flags = flags;
5c6af06e 2638 }
0089dace
L		 2639 else
2640 cpu_arch_isa_flags
2641 = cpu_flags_or (cpu_arch_isa_flags,
2642 cpu_arch[j].flags);
d02603dc 2643 (void) restore_line_pointer (e);
5c6af06e
JB		 2644 demand_empty_rest_of_line ();
2645 return;
e413e4e9
AM		 2646 }
2647 }
293f5f65
L		 2648
2649 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2650 {
33eaf5de 2651 /* Disable an ISA extension. */
293f5f65
L		 2652 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2653 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2654 {
2655 flags = cpu_flags_and_not (cpu_arch_flags,
2656 cpu_noarch[j].flags);
2657 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2658 {
2659 if (cpu_sub_arch_name)
2660 {
2661 char *name = cpu_sub_arch_name;
2662 cpu_sub_arch_name = concat (name, string,
2663 (const char *) NULL);
2664 free (name);
2665 }
2666 else
2667 cpu_sub_arch_name = xstrdup (string);
2668 cpu_arch_flags = flags;
2669 cpu_arch_isa_flags = flags;
2670 }
2671 (void) restore_line_pointer (e);
2672 demand_empty_rest_of_line ();
2673 return;
2674 }
2675
2676 j = ARRAY_SIZE (cpu_arch);
2677 }
2678
91d6fa6a 2679 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2680 as_bad (_("no such architecture: `%s'"), string);
2681
2682 *input_line_pointer = e;
2683 }
2684 else
2685 as_bad (_("missing cpu architecture"));
2686
fddf5b5b
AM		 2687 no_cond_jump_promotion = 0;
2688 if (*input_line_pointer == ','
29b0f896 2689 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2690 {
d02603dc
NC		 2691 char *string;
2692 char e;
2693
2694 ++input_line_pointer;
2695 e = get_symbol_name (&string);
fddf5b5b
AM		 2696
2697 if (strcmp (string, "nojumps") == 0)
2698 no_cond_jump_promotion = 1;
2699 else if (strcmp (string, "jumps") == 0)
2700 ;
2701 else
2702 as_bad (_("no such architecture modifier: `%s'"), string);
2703
d02603dc 2704 (void) restore_line_pointer (e);
fddf5b5b
AM		 2705 }
2706
e413e4e9
AM		 2707 demand_empty_rest_of_line ();
2708}
2709
8a9036a4
L		 2710enum bfd_architecture
2711i386_arch (void)
2712{
3632d14b 2713 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2714 {
2715 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2716 || flag_code != CODE_64BIT)
2717 as_fatal (_("Intel L1OM is 64bit ELF only"));
2718 return bfd_arch_l1om;
2719 }
7a9068fe
L		 2720 else if (cpu_arch_isa == PROCESSOR_K1OM)
2721 {
2722 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2723 || flag_code != CODE_64BIT)
2724 as_fatal (_("Intel K1OM is 64bit ELF only"));
2725 return bfd_arch_k1om;
2726 }
81486035
L		 2727 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2728 {
2729 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2730 || flag_code == CODE_64BIT)
2731 as_fatal (_("Intel MCU is 32bit ELF only"));
2732 return bfd_arch_iamcu;
2733 }
8a9036a4
L		 2734 else
2735 return bfd_arch_i386;
2736}
2737
b9d79e03 2738unsigned long
7016a5d5 2739i386_mach (void)
b9d79e03 2740{
351f65ca 2741 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2742 {
3632d14b 2743 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2744 {
351f65ca
L		 2745 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2746 || default_arch[6] != '\0')
8a9036a4
L		 2747 as_fatal (_("Intel L1OM is 64bit ELF only"));
2748 return bfd_mach_l1om;
2749 }
7a9068fe
L		 2750 else if (cpu_arch_isa == PROCESSOR_K1OM)
2751 {
2752 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2753 || default_arch[6] != '\0')
2754 as_fatal (_("Intel K1OM is 64bit ELF only"));
2755 return bfd_mach_k1om;
2756 }
351f65ca 2757 else if (default_arch[6] == '\0')
8a9036a4 2758 return bfd_mach_x86_64;
351f65ca
L		 2759 else
2760 return bfd_mach_x64_32;
8a9036a4 2761 }
5197d474
L		 2762 else if (!strcmp (default_arch, "i386")
2763 || !strcmp (default_arch, "iamcu"))
81486035
L		 2764 {
2765 if (cpu_arch_isa == PROCESSOR_IAMCU)
2766 {
2767 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2768 as_fatal (_("Intel MCU is 32bit ELF only"));
2769 return bfd_mach_i386_iamcu;
2770 }
2771 else
2772 return bfd_mach_i386_i386;
2773 }
b9d79e03 2774 else
2b5d6a91 2775 as_fatal (_("unknown architecture"));
b9d79e03 2776}
b9d79e03 2777\f
252b5132 2778void
7016a5d5 2779md_begin (void)
252b5132
RH		 2780{
2781 const char *hash_err;
2782
86fa6981
L		 2783 /* Support pseudo prefixes like {disp32}. */
2784 lex_type ['{'] = LEX_BEGIN_NAME;
2785
47926f60 2786 /* Initialize op_hash hash table. */
252b5132
RH		 2787 op_hash = hash_new ();
2788
2789 {
d3ce72d0 2790 const insn_template *optab;
29b0f896 2791 templates *core_optab;
252b5132 2792
47926f60
KH		 2793 /* Setup for loop. */
2794 optab = i386_optab;
add39d23 2795 core_optab = XNEW (templates);
252b5132
RH		 2796 core_optab->start = optab;
2797
2798 while (1)
2799 {
2800 ++optab;
2801 if (optab->name == NULL
2802 || strcmp (optab->name, (optab - 1)->name) != 0)
2803 {
2804 /* different name --> ship out current template list;
47926f60 2805 add to hash table; & begin anew. */
252b5132
RH		 2806 core_optab->end = optab;
2807 hash_err = hash_insert (op_hash,
2808 (optab - 1)->name,
5a49b8ac 2809 (void *) core_optab);
252b5132
RH		 2810 if (hash_err)
2811 {
b37df7c4 2812 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2813 (optab - 1)->name,
2814 hash_err);
2815 }
2816 if (optab->name == NULL)
2817 break;
add39d23 2818 core_optab = XNEW (templates);
252b5132
RH		 2819 core_optab->start = optab;
2820 }
2821 }
2822 }
2823
47926f60 2824 /* Initialize reg_hash hash table. */
252b5132
RH		 2825 reg_hash = hash_new ();
2826 {
29b0f896 2827 const reg_entry *regtab;
c3fe08fa 2828 unsigned int regtab_size = i386_regtab_size;
252b5132 2829
c3fe08fa 2830 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2831 {
5a49b8ac 2832 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2833 if (hash_err)
b37df7c4 2834 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2835 regtab->reg_name,
2836 hash_err);
252b5132
RH		 2837 }
2838 }
2839
47926f60 2840 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2841 {
29b0f896
AM		 2842 int c;
2843 char *p;
252b5132
RH		 2844
2845 for (c = 0; c < 256; c++)
2846 {
3882b010 2847 if (ISDIGIT (c))
252b5132
RH		 2848 {
2849 digit_chars[c] = c;
2850 mnemonic_chars[c] = c;
2851 register_chars[c] = c;
2852 operand_chars[c] = c;
2853 }
3882b010 2854 else if (ISLOWER (c))
252b5132
RH		 2855 {
2856 mnemonic_chars[c] = c;
2857 register_chars[c] = c;
2858 operand_chars[c] = c;
2859 }
3882b010 2860 else if (ISUPPER (c))
252b5132 2861 {
3882b010 2862 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2863 register_chars[c] = mnemonic_chars[c];
2864 operand_chars[c] = c;
2865 }
43234a1e 2866 else if (c == '{' || c == '}')
86fa6981
L		 2867 {
2868 mnemonic_chars[c] = c;
2869 operand_chars[c] = c;
2870 }
252b5132 2871
3882b010 2872 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2873 identifier_chars[c] = c;
2874 else if (c >= 128)
2875 {
2876 identifier_chars[c] = c;
2877 operand_chars[c] = c;
2878 }
2879 }
2880
2881#ifdef LEX_AT
2882 identifier_chars['@'] = '@';
32137342
NC		 2883#endif
2884#ifdef LEX_QM
2885 identifier_chars['?'] = '?';
2886 operand_chars['?'] = '?';
252b5132 2887#endif
252b5132 2888 digit_chars['-'] = '-';
c0f3af97 2889 mnemonic_chars['_'] = '_';
791fe849 2890 mnemonic_chars['-'] = '-';
0003779b 2891 mnemonic_chars['.'] = '.';
252b5132
RH		 2892 identifier_chars['_'] = '_';
2893 identifier_chars['.'] = '.';
2894
2895 for (p = operand_special_chars; *p != '\0'; p++)
2896 operand_chars[(unsigned char) *p] = *p;
2897 }
2898
a4447b93
RH		 2899 if (flag_code == CODE_64BIT)
2900 {
ca19b261
KT		 2901#if defined (OBJ_COFF) && defined (TE_PE)
2902 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2903 ? 32 : 16);
2904#else
a4447b93 2905 x86_dwarf2_return_column = 16;
ca19b261 2906#endif
61ff971f 2907 x86_cie_data_alignment = -8;
a4447b93
RH		 2908 }
2909 else
2910 {
2911 x86_dwarf2_return_column = 8;
2912 x86_cie_data_alignment = -4;
2913 }
252b5132
RH		 2914}
2915
2916void
e3bb37b5 2917i386_print_statistics (FILE *file)
252b5132
RH		 2918{
2919 hash_print_statistics (file, "i386 opcode", op_hash);
2920 hash_print_statistics (file, "i386 register", reg_hash);
2921}
2922\f
252b5132
RH		 2923#ifdef DEBUG386
2924
ce8a8b2f 2925/* Debugging routines for md_assemble. */
d3ce72d0 2926static void pte (insn_template *);
40fb9820 2927static void pt (i386_operand_type);
e3bb37b5
L		 2928static void pe (expressionS *);
2929static void ps (symbolS *);
252b5132
RH		 2930
2931static void
e3bb37b5 2932pi (char *line, i386_insn *x)
252b5132 2933{
09137c09 2934 unsigned int j;
252b5132
RH		 2935
2936 fprintf (stdout, "%s: template ", line);
2937 pte (&x->tm);
09f131f2
JH		 2938 fprintf (stdout, " address: base %s index %s scale %x\n",
2939 x->base_reg ? x->base_reg->reg_name : "none",
2940 x->index_reg ? x->index_reg->reg_name : "none",
2941 x->log2_scale_factor);
2942 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2943 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2944 fprintf (stdout, " sib: base %x index %x scale %x\n",
2945 x->sib.base, x->sib.index, x->sib.scale);
2946 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2947 (x->rex & REX_W) != 0,
2948 (x->rex & REX_R) != 0,
2949 (x->rex & REX_X) != 0,
2950 (x->rex & REX_B) != 0);
09137c09 2951 for (j = 0; j < x->operands; j++)
252b5132 2952 {
09137c09
SP		 2953 fprintf (stdout, " #%d: ", j + 1);
2954 pt (x->types[j]);
252b5132 2955 fprintf (stdout, "\n");
dc821c5f 2956 if (x->types[j].bitfield.reg
09137c09 2957 || x->types[j].bitfield.regmmx
1b54b8d7 2958 || x->types[j].bitfield.regsimd
09137c09
SP		 2959 || x->types[j].bitfield.sreg2
2960 || x->types[j].bitfield.sreg3
2961 || x->types[j].bitfield.control
2962 || x->types[j].bitfield.debug
2963 || x->types[j].bitfield.test)
2964 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2965 if (operand_type_check (x->types[j], imm))
2966 pe (x->op[j].imms);
2967 if (operand_type_check (x->types[j], disp))
2968 pe (x->op[j].disps);
252b5132
RH		 2969 }
2970}
2971
2972static void
d3ce72d0 2973pte (insn_template *t)
252b5132 2974{
09137c09 2975 unsigned int j;
252b5132 2976 fprintf (stdout, " %d operands ", t->operands);
47926f60 2977 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2978 if (t->extension_opcode != None)
2979 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2980 if (t->opcode_modifier.d)
252b5132 2981 fprintf (stdout, "D");
40fb9820 2982 if (t->opcode_modifier.w)
252b5132
RH		 2983 fprintf (stdout, "W");
2984 fprintf (stdout, "\n");
09137c09 2985 for (j = 0; j < t->operands; j++)
252b5132 2986 {
09137c09
SP		 2987 fprintf (stdout, " #%d type ", j + 1);
2988 pt (t->operand_types[j]);
252b5132
RH		 2989 fprintf (stdout, "\n");
2990 }
2991}
2992
2993static void
e3bb37b5 2994pe (expressionS *e)
252b5132 2995{
24eab124 2996 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2997 fprintf (stdout, " add_number %ld (%lx)\n",
2998 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2999 if (e->X_add_symbol)
3000 {
3001 fprintf (stdout, " add_symbol ");
3002 ps (e->X_add_symbol);
3003 fprintf (stdout, "\n");
3004 }
3005 if (e->X_op_symbol)
3006 {
3007 fprintf (stdout, " op_symbol ");
3008 ps (e->X_op_symbol);
3009 fprintf (stdout, "\n");
3010 }
3011}
3012
3013static void
e3bb37b5 3014ps (symbolS *s)
252b5132
RH		 3015{
3016 fprintf (stdout, "%s type %s%s",
3017 S_GET_NAME (s),
3018 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3019 segment_name (S_GET_SEGMENT (s)));
3020}
3021
7b81dfbb 3022static struct type_name
252b5132 3023 {
40fb9820
L		 3024 i386_operand_type mask;
3025 const char *name;
252b5132 3026 }
7b81dfbb 3027const type_names[] =
252b5132 3028{
40fb9820
L		 3029 { OPERAND_TYPE_REG8, "r8" },
3030 { OPERAND_TYPE_REG16, "r16" },
3031 { OPERAND_TYPE_REG32, "r32" },
3032 { OPERAND_TYPE_REG64, "r64" },
3033 { OPERAND_TYPE_IMM8, "i8" },
3034 { OPERAND_TYPE_IMM8, "i8s" },
3035 { OPERAND_TYPE_IMM16, "i16" },
3036 { OPERAND_TYPE_IMM32, "i32" },
3037 { OPERAND_TYPE_IMM32S, "i32s" },
3038 { OPERAND_TYPE_IMM64, "i64" },
3039 { OPERAND_TYPE_IMM1, "i1" },
3040 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3041 { OPERAND_TYPE_DISP8, "d8" },
3042 { OPERAND_TYPE_DISP16, "d16" },
3043 { OPERAND_TYPE_DISP32, "d32" },
3044 { OPERAND_TYPE_DISP32S, "d32s" },
3045 { OPERAND_TYPE_DISP64, "d64" },
3046 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3047 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3048 { OPERAND_TYPE_CONTROL, "control reg" },
3049 { OPERAND_TYPE_TEST, "test reg" },
3050 { OPERAND_TYPE_DEBUG, "debug reg" },
3051 { OPERAND_TYPE_FLOATREG, "FReg" },
3052 { OPERAND_TYPE_FLOATACC, "FAcc" },
3053 { OPERAND_TYPE_SREG2, "SReg2" },
3054 { OPERAND_TYPE_SREG3, "SReg3" },
3055 { OPERAND_TYPE_ACC, "Acc" },
3056 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3057 { OPERAND_TYPE_REGMMX, "rMMX" },
3058 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3059 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3060 { OPERAND_TYPE_REGZMM, "rZMM" },
3061 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3062 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3063};
3064
3065static void
40fb9820 3066pt (i386_operand_type t)
252b5132 3067{
40fb9820 3068 unsigned int j;
c6fb90c8 3069 i386_operand_type a;
252b5132 3070
40fb9820 3071 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3072 {
3073 a = operand_type_and (t, type_names[j].mask);
0349dc08 3074 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3075 fprintf (stdout, "%s, ", type_names[j].name);
3076 }
252b5132
RH		 3077 fflush (stdout);
3078}
3079
3080#endif /* DEBUG386 */
3081\f
252b5132 3082static bfd_reloc_code_real_type
3956db08 3083reloc (unsigned int size,
64e74474
AM		 3084 int pcrel,
3085 int sign,
3086 bfd_reloc_code_real_type other)
252b5132 3087{
47926f60 3088 if (other != NO_RELOC)
3956db08 3089 {
91d6fa6a 3090 reloc_howto_type *rel;
3956db08
JB		 3091
3092 if (size == 8)
3093 switch (other)
3094 {
64e74474
AM		 3095 case BFD_RELOC_X86_64_GOT32:
3096 return BFD_RELOC_X86_64_GOT64;
3097 break;
553d1284
L		 3098 case BFD_RELOC_X86_64_GOTPLT64:
3099 return BFD_RELOC_X86_64_GOTPLT64;
3100 break;
64e74474
AM		 3101 case BFD_RELOC_X86_64_PLTOFF64:
3102 return BFD_RELOC_X86_64_PLTOFF64;
3103 break;
3104 case BFD_RELOC_X86_64_GOTPC32:
3105 other = BFD_RELOC_X86_64_GOTPC64;
3106 break;
3107 case BFD_RELOC_X86_64_GOTPCREL:
3108 other = BFD_RELOC_X86_64_GOTPCREL64;
3109 break;
3110 case BFD_RELOC_X86_64_TPOFF32:
3111 other = BFD_RELOC_X86_64_TPOFF64;
3112 break;
3113 case BFD_RELOC_X86_64_DTPOFF32:
3114 other = BFD_RELOC_X86_64_DTPOFF64;
3115 break;
3116 default:
3117 break;
3956db08 3118 }
e05278af 3119
8ce3d284 3120#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3121 if (other == BFD_RELOC_SIZE32)
3122 {
3123 if (size == 8)
1ab668bf 3124 other = BFD_RELOC_SIZE64;
8fd4256d 3125 if (pcrel)
1ab668bf
AM		 3126 {
3127 as_bad (_("there are no pc-relative size relocations"));
3128 return NO_RELOC;
3129 }
8fd4256d 3130 }
8ce3d284 3131#endif
8fd4256d 3132
e05278af 3133 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3134 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3135 sign = -1;
3136
91d6fa6a
NC		 3137 rel = bfd_reloc_type_lookup (stdoutput, other);
3138 if (!rel)
3956db08 3139 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3140 else if (size != bfd_get_reloc_size (rel))
3956db08 3141 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3142 bfd_get_reloc_size (rel),
3956db08 3143 size);
91d6fa6a 3144 else if (pcrel && !rel->pc_relative)
3956db08 3145 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3146 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3147 && !sign)
91d6fa6a 3148 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3149 && sign > 0))
3956db08
JB		 3150 as_bad (_("relocated field and relocation type differ in signedness"));
3151 else
3152 return other;
3153 return NO_RELOC;
3154 }
252b5132
RH		 3155
3156 if (pcrel)
3157 {
3e73aa7c 3158 if (!sign)
3956db08 3159 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3160 switch (size)
3161 {
3162 case 1: return BFD_RELOC_8_PCREL;
3163 case 2: return BFD_RELOC_16_PCREL;
d258b828 3164 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3165 case 8: return BFD_RELOC_64_PCREL;
252b5132 3166 }
3956db08 3167 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3168 }
3169 else
3170 {
3956db08 3171 if (sign > 0)
e5cb08ac 3172 switch (size)
3e73aa7c
JH		 3173 {
3174 case 4: return BFD_RELOC_X86_64_32S;
3175 }
3176 else
3177 switch (size)
3178 {
3179 case 1: return BFD_RELOC_8;
3180 case 2: return BFD_RELOC_16;
3181 case 4: return BFD_RELOC_32;
3182 case 8: return BFD_RELOC_64;
3183 }
3956db08
JB		 3184 as_bad (_("cannot do %s %u byte relocation"),
3185 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3186 }
3187
0cc9e1d3 3188 return NO_RELOC;
252b5132
RH		 3189}
3190
47926f60
KH		 3191/* Here we decide which fixups can be adjusted to make them relative to
3192 the beginning of the section instead of the symbol. Basically we need
3193 to make sure that the dynamic relocations are done correctly, so in
3194 some cases we force the original symbol to be used. */
3195
252b5132 3196int
e3bb37b5 3197tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3198{
6d249963 3199#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3200 if (!IS_ELF)
31312f95
AM		 3201 return 1;
3202
a161fe53
AM		 3203 /* Don't adjust pc-relative references to merge sections in 64-bit
3204 mode. */
3205 if (use_rela_relocations
3206 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3207 && fixP->fx_pcrel)
252b5132 3208 return 0;
31312f95 3209
8d01d9a9
AJ		 3210 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3211 and changed later by validate_fix. */
3212 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3213 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3214 return 0;
3215
8fd4256d
L		 3216 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3217 for size relocations. */
3218 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3219 || fixP->fx_r_type == BFD_RELOC_SIZE64
3220 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3221 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3222 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3223 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3233 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3239 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3242 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3243 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3245 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3247 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3248 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3249 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3250 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3251 return 0;
31312f95 3252#endif
252b5132
RH		 3253 return 1;
3254}
252b5132 3255
b4cac588 3256static int
e3bb37b5 3257intel_float_operand (const char *mnemonic)
252b5132 3258{
9306ca4a
JB		 3259 /* Note that the value returned is meaningful only for opcodes with (memory)
3260 operands, hence the code here is free to improperly handle opcodes that
3261 have no operands (for better performance and smaller code). */
3262
3263 if (mnemonic[0] != 'f')
3264 return 0; /* non-math */
3265
3266 switch (mnemonic[1])
3267 {
3268 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3269 the fs segment override prefix not currently handled because no
3270 call path can make opcodes without operands get here */
3271 case 'i':
3272 return 2 /* integer op */;
3273 case 'l':
3274 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3275 return 3; /* fldcw/fldenv */
3276 break;
3277 case 'n':
3278 if (mnemonic[2] != 'o' /* fnop */)
3279 return 3; /* non-waiting control op */
3280 break;
3281 case 'r':
3282 if (mnemonic[2] == 's')
3283 return 3; /* frstor/frstpm */
3284 break;
3285 case 's':
3286 if (mnemonic[2] == 'a')
3287 return 3; /* fsave */
3288 if (mnemonic[2] == 't')
3289 {
3290 switch (mnemonic[3])
3291 {
3292 case 'c': /* fstcw */
3293 case 'd': /* fstdw */
3294 case 'e': /* fstenv */
3295 case 's': /* fsts[gw] */
3296 return 3;
3297 }
3298 }
3299 break;
3300 case 'x':
3301 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3302 return 0; /* fxsave/fxrstor are not really math ops */
3303 break;
3304 }
252b5132 3305
9306ca4a 3306 return 1;
252b5132
RH		 3307}
3308
c0f3af97
L		 3309/* Build the VEX prefix. */
3310
3311static void
d3ce72d0 3312build_vex_prefix (const insn_template *t)
c0f3af97
L		 3313{
3314 unsigned int register_specifier;
3315 unsigned int implied_prefix;
3316 unsigned int vector_length;
3317
3318 /* Check register specifier. */
3319 if (i.vex.register_specifier)
43234a1e
L		 3320 {
3321 register_specifier =
3322 ~register_number (i.vex.register_specifier) & 0xf;
3323 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3324 }
c0f3af97
L		 3325 else
3326 register_specifier = 0xf;
3327
33eaf5de 3328 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3329 operand. */
86fa6981
L		 3330 if (i.vec_encoding != vex_encoding_vex3
3331 && i.dir_encoding == dir_encoding_default
fa99fab2 3332 && i.operands == i.reg_operands
7f399153 3333 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3334 && i.tm.opcode_modifier.load
fa99fab2
L		 3335 && i.rex == REX_B)
3336 {
3337 unsigned int xchg = i.operands - 1;
3338 union i386_op temp_op;
3339 i386_operand_type temp_type;
3340
3341 temp_type = i.types[xchg];
3342 i.types[xchg] = i.types[0];
3343 i.types[0] = temp_type;
3344 temp_op = i.op[xchg];
3345 i.op[xchg] = i.op[0];
3346 i.op[0] = temp_op;
3347
9c2799c2 3348 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3349
3350 i.rex = REX_R;
3351 xchg = i.rm.regmem;
3352 i.rm.regmem = i.rm.reg;
3353 i.rm.reg = xchg;
3354
3355 /* Use the next insn. */
3356 i.tm = t[1];
3357 }
3358
539f890d
L		 3359 if (i.tm.opcode_modifier.vex == VEXScalar)
3360 vector_length = avxscalar;
10c17abd
JB		 3361 else if (i.tm.opcode_modifier.vex == VEX256)
3362 vector_length = 1;
539f890d 3363 else
10c17abd
JB		 3364 {
3365 unsigned int op;
3366
3367 vector_length = 0;
3368 for (op = 0; op < t->operands; ++op)
3369 if (t->operand_types[op].bitfield.xmmword
3370 && t->operand_types[op].bitfield.ymmword
3371 && i.types[op].bitfield.ymmword)
3372 {
3373 vector_length = 1;
3374 break;
3375 }
3376 }
c0f3af97
L		 3377
3378 switch ((i.tm.base_opcode >> 8) & 0xff)
3379 {
3380 case 0:
3381 implied_prefix = 0;
3382 break;
3383 case DATA_PREFIX_OPCODE:
3384 implied_prefix = 1;
3385 break;
3386 case REPE_PREFIX_OPCODE:
3387 implied_prefix = 2;
3388 break;
3389 case REPNE_PREFIX_OPCODE:
3390 implied_prefix = 3;
3391 break;
3392 default:
3393 abort ();
3394 }
3395
3396 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3397 if (i.vec_encoding != vex_encoding_vex3
3398 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3399 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3400 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3401 {
3402 /* 2-byte VEX prefix. */
3403 unsigned int r;
3404
3405 i.vex.length = 2;
3406 i.vex.bytes[0] = 0xc5;
3407
3408 /* Check the REX.R bit. */
3409 r = (i.rex & REX_R) ? 0 : 1;
3410 i.vex.bytes[1] = (r << 7
3411 | register_specifier << 3
3412 | vector_length << 2
3413 | implied_prefix);
3414 }
3415 else
3416 {
3417 /* 3-byte VEX prefix. */
3418 unsigned int m, w;
3419
f88c9eb0 3420 i.vex.length = 3;
f88c9eb0 3421
7f399153 3422 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3423 {
7f399153
L		 3424 case VEX0F:
3425 m = 0x1;
80de6e00 3426 i.vex.bytes[0] = 0xc4;
7f399153
L		 3427 break;
3428 case VEX0F38:
3429 m = 0x2;
80de6e00 3430 i.vex.bytes[0] = 0xc4;
7f399153
L		 3431 break;
3432 case VEX0F3A:
3433 m = 0x3;
80de6e00 3434 i.vex.bytes[0] = 0xc4;
7f399153
L		 3435 break;
3436 case XOP08:
5dd85c99
SP		 3437 m = 0x8;
3438 i.vex.bytes[0] = 0x8f;
7f399153
L		 3439 break;
3440 case XOP09:
f88c9eb0
SP		 3441 m = 0x9;
3442 i.vex.bytes[0] = 0x8f;
7f399153
L		 3443 break;
3444 case XOP0A:
f88c9eb0
SP		 3445 m = 0xa;
3446 i.vex.bytes[0] = 0x8f;
7f399153
L		 3447 break;
3448 default:
3449 abort ();
f88c9eb0 3450 }
c0f3af97 3451
c0f3af97
L		 3452 /* The high 3 bits of the second VEX byte are 1's compliment
3453 of RXB bits from REX. */
3454 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3455
3456 /* Check the REX.W bit. */
3457 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3458 if (i.tm.opcode_modifier.vexw == VEXW1)
3459 w = 1;
c0f3af97
L		 3460
3461 i.vex.bytes[2] = (w << 7
3462 | register_specifier << 3
3463 | vector_length << 2
3464 | implied_prefix);
3465 }
3466}
3467
e771e7c9
JB		 3468static INLINE bfd_boolean
3469is_evex_encoding (const insn_template *t)
3470{
3471 return t->opcode_modifier.evex
3472 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3473 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3474}
3475
43234a1e
L		 3476/* Build the EVEX prefix. */
3477
3478static void
3479build_evex_prefix (void)
3480{
3481 unsigned int register_specifier;
3482 unsigned int implied_prefix;
3483 unsigned int m, w;
3484 rex_byte vrex_used = 0;
3485
3486 /* Check register specifier. */
3487 if (i.vex.register_specifier)
3488 {
3489 gas_assert ((i.vrex & REX_X) == 0);
3490
3491 register_specifier = i.vex.register_specifier->reg_num;
3492 if ((i.vex.register_specifier->reg_flags & RegRex))
3493 register_specifier += 8;
3494 /* The upper 16 registers are encoded in the fourth byte of the
3495 EVEX prefix. */
3496 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3497 i.vex.bytes[3] = 0x8;
3498 register_specifier = ~register_specifier & 0xf;
3499 }
3500 else
3501 {
3502 register_specifier = 0xf;
3503
3504 /* Encode upper 16 vector index register in the fourth byte of
3505 the EVEX prefix. */
3506 if (!(i.vrex & REX_X))
3507 i.vex.bytes[3] = 0x8;
3508 else
3509 vrex_used |= REX_X;
3510 }
3511
3512 switch ((i.tm.base_opcode >> 8) & 0xff)
3513 {
3514 case 0:
3515 implied_prefix = 0;
3516 break;
3517 case DATA_PREFIX_OPCODE:
3518 implied_prefix = 1;
3519 break;
3520 case REPE_PREFIX_OPCODE:
3521 implied_prefix = 2;
3522 break;
3523 case REPNE_PREFIX_OPCODE:
3524 implied_prefix = 3;
3525 break;
3526 default:
3527 abort ();
3528 }
3529
3530 /* 4 byte EVEX prefix. */
3531 i.vex.length = 4;
3532 i.vex.bytes[0] = 0x62;
3533
3534 /* mmmm bits. */
3535 switch (i.tm.opcode_modifier.vexopcode)
3536 {
3537 case VEX0F:
3538 m = 1;
3539 break;
3540 case VEX0F38:
3541 m = 2;
3542 break;
3543 case VEX0F3A:
3544 m = 3;
3545 break;
3546 default:
3547 abort ();
3548 break;
3549 }
3550
3551 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3552 bits from REX. */
3553 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3554
3555 /* The fifth bit of the second EVEX byte is 1's compliment of the
3556 REX_R bit in VREX. */
3557 if (!(i.vrex & REX_R))
3558 i.vex.bytes[1] |= 0x10;
3559 else
3560 vrex_used |= REX_R;
3561
3562 if ((i.reg_operands + i.imm_operands) == i.operands)
3563 {
3564 /* When all operands are registers, the REX_X bit in REX is not
3565 used. We reuse it to encode the upper 16 registers, which is
3566 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3567 as 1's compliment. */
3568 if ((i.vrex & REX_B))
3569 {
3570 vrex_used |= REX_B;
3571 i.vex.bytes[1] &= ~0x40;
3572 }
3573 }
3574
3575 /* EVEX instructions shouldn't need the REX prefix. */
3576 i.vrex &= ~vrex_used;
3577 gas_assert (i.vrex == 0);
3578
3579 /* Check the REX.W bit. */
3580 w = (i.rex & REX_W) ? 1 : 0;
3581 if (i.tm.opcode_modifier.vexw)
3582 {
3583 if (i.tm.opcode_modifier.vexw == VEXW1)
3584 w = 1;
3585 }
3586 /* If w is not set it means we are dealing with WIG instruction. */
3587 else if (!w)
3588 {
3589 if (evexwig == evexw1)
3590 w = 1;
3591 }
3592
3593 /* Encode the U bit. */
3594 implied_prefix |= 0x4;
3595
3596 /* The third byte of the EVEX prefix. */
3597 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3598
3599 /* The fourth byte of the EVEX prefix. */
3600 /* The zeroing-masking bit. */
3601 if (i.mask && i.mask->zeroing)
3602 i.vex.bytes[3] |= 0x80;
3603
3604 /* Don't always set the broadcast bit if there is no RC. */
3605 if (!i.rounding)
3606 {
3607 /* Encode the vector length. */
3608 unsigned int vec_length;
3609
e771e7c9
JB		 3610 if (!i.tm.opcode_modifier.evex
3611 || i.tm.opcode_modifier.evex == EVEXDYN)
3612 {
3613 unsigned int op;
3614
3615 vec_length = 0;
3616 for (op = 0; op < i.tm.operands; ++op)
3617 if (i.tm.operand_types[op].bitfield.xmmword
3618 + i.tm.operand_types[op].bitfield.ymmword
3619 + i.tm.operand_types[op].bitfield.zmmword > 1)
3620 {
3621 if (i.types[op].bitfield.zmmword)
3622 i.tm.opcode_modifier.evex = EVEX512;
3623 else if (i.types[op].bitfield.ymmword)
3624 i.tm.opcode_modifier.evex = EVEX256;
3625 else if (i.types[op].bitfield.xmmword)
3626 i.tm.opcode_modifier.evex = EVEX128;
3627 else
3628 continue;
3629 break;
3630 }
3631 }
3632
43234a1e
L		 3633 switch (i.tm.opcode_modifier.evex)
3634 {
3635 case EVEXLIG: /* LL' is ignored */
3636 vec_length = evexlig << 5;
3637 break;
3638 case EVEX128:
3639 vec_length = 0 << 5;
3640 break;
3641 case EVEX256:
3642 vec_length = 1 << 5;
3643 break;
3644 case EVEX512:
3645 vec_length = 2 << 5;
3646 break;
3647 default:
3648 abort ();
3649 break;
3650 }
3651 i.vex.bytes[3] |= vec_length;
3652 /* Encode the broadcast bit. */
3653 if (i.broadcast)
3654 i.vex.bytes[3] |= 0x10;
3655 }
3656 else
3657 {
3658 if (i.rounding->type != saeonly)
3659 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3660 else
d3d3c6db 3661 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3662 }
3663
3664 if (i.mask && i.mask->mask)
3665 i.vex.bytes[3] |= i.mask->mask->reg_num;
3666}
3667
65da13b5
L		 3668static void
3669process_immext (void)
3670{
3671 expressionS *exp;
3672
4c692bc7
JB		 3673 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3674 && i.operands > 0)
65da13b5 3675 {
4c692bc7
JB		 3676 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3677 with an opcode suffix which is coded in the same place as an
3678 8-bit immediate field would be.
3679 Here we check those operands and remove them afterwards. */
65da13b5
L		 3680 unsigned int x;
3681
3682 for (x = 0; x < i.operands; x++)
4c692bc7 3683 if (register_number (i.op[x].regs) != x)
65da13b5 3684 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3685 register_prefix, i.op[x].regs->reg_name, x + 1,
3686 i.tm.name);
3687
3688 i.operands = 0;
65da13b5
L		 3689 }
3690
9916071f
AP		 3691 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3692 {
3693 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3694 suffix which is coded in the same place as an 8-bit immediate
3695 field would be.
3696 Here we check those operands and remove them afterwards. */
3697 unsigned int x;
3698
3699 if (i.operands != 3)
3700 abort();
3701
3702 for (x = 0; x < 2; x++)
3703 if (register_number (i.op[x].regs) != x)
3704 goto bad_register_operand;
3705
3706 /* Check for third operand for mwaitx/monitorx insn. */
3707 if (register_number (i.op[x].regs)
3708 != (x + (i.tm.extension_opcode == 0xfb)))
3709 {
3710bad_register_operand:
3711 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3712 register_prefix, i.op[x].regs->reg_name, x+1,
3713 i.tm.name);
3714 }
3715
3716 i.operands = 0;
3717 }
3718
c0f3af97 3719 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3720 which is coded in the same place as an 8-bit immediate field
3721 would be. Here we fake an 8-bit immediate operand from the
3722 opcode suffix stored in tm.extension_opcode.
3723
c1e679ec 3724 AVX instructions also use this encoding, for some of
c0f3af97 3725 3 argument instructions. */
65da13b5 3726
43234a1e 3727 gas_assert (i.imm_operands <= 1
7ab9ffdd 3728 && (i.operands <= 2
43234a1e 3729 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3730 || i.tm.opcode_modifier.vexopcode
3731 || is_evex_encoding (&i.tm))
7ab9ffdd 3732 && i.operands <= 4)));
65da13b5
L		 3733
3734 exp = &im_expressions[i.imm_operands++];
3735 i.op[i.operands].imms = exp;
3736 i.types[i.operands] = imm8;
3737 i.operands++;
3738 exp->X_op = O_constant;
3739 exp->X_add_number = i.tm.extension_opcode;
3740 i.tm.extension_opcode = None;
3741}
3742
42164a71
L		 3743
3744static int
3745check_hle (void)
3746{
3747 switch (i.tm.opcode_modifier.hleprefixok)
3748 {
3749 default:
3750 abort ();
82c2def5 3751 case HLEPrefixNone:
165de32a
L		 3752 as_bad (_("invalid instruction `%s' after `%s'"),
3753 i.tm.name, i.hle_prefix);
42164a71 3754 return 0;
82c2def5 3755 case HLEPrefixLock:
42164a71
L		 3756 if (i.prefix[LOCK_PREFIX])
3757 return 1;
165de32a 3758 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3759 return 0;
82c2def5 3760 case HLEPrefixAny:
42164a71 3761 return 1;
82c2def5 3762 case HLEPrefixRelease:
42164a71
L		 3763 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3764 {
3765 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3766 i.tm.name);
3767 return 0;
3768 }
3769 if (i.mem_operands == 0
3770 || !operand_type_check (i.types[i.operands - 1], anymem))
3771 {
3772 as_bad (_("memory destination needed for instruction `%s'"
3773 " after `xrelease'"), i.tm.name);
3774 return 0;
3775 }
3776 return 1;
3777 }
3778}
3779
b6f8c7c4
L		 3780/* Try the shortest encoding by shortening operand size. */
3781
3782static void
3783optimize_encoding (void)
3784{
3785 int j;
3786
3787 if (optimize_for_space
3788 && i.reg_operands == 1
3789 && i.imm_operands == 1
3790 && !i.types[1].bitfield.byte
3791 && i.op[0].imms->X_op == O_constant
3792 && fits_in_imm7 (i.op[0].imms->X_add_number)
3793 && ((i.tm.base_opcode == 0xa8
3794 && i.tm.extension_opcode == None)
3795 || (i.tm.base_opcode == 0xf6
3796 && i.tm.extension_opcode == 0x0)))
3797 {
3798 /* Optimize: -Os:
3799 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3800 */
3801 unsigned int base_regnum = i.op[1].regs->reg_num;
3802 if (flag_code == CODE_64BIT || base_regnum < 4)
3803 {
3804 i.types[1].bitfield.byte = 1;
3805 /* Ignore the suffix. */
3806 i.suffix = 0;
3807 if (base_regnum >= 4
3808 && !(i.op[1].regs->reg_flags & RegRex))
3809 {
3810 /* Handle SP, BP, SI and DI registers. */
3811 if (i.types[1].bitfield.word)
3812 j = 16;
3813 else if (i.types[1].bitfield.dword)
3814 j = 32;
3815 else
3816 j = 48;
3817 i.op[1].regs -= j;
3818 }
3819 }
3820 }
3821 else if (flag_code == CODE_64BIT
d3d50934
L		 3822 && ((i.types[1].bitfield.qword
3823 && i.reg_operands == 1
b6f8c7c4
L		 3824 && i.imm_operands == 1
3825 && i.op[0].imms->X_op == O_constant
3826 && ((i.tm.base_opcode == 0xb0
3827 && i.tm.extension_opcode == None
3828 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3829 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3830 && (((i.tm.base_opcode == 0x24
3831 || i.tm.base_opcode == 0xa8)
3832 && i.tm.extension_opcode == None)
3833 || (i.tm.base_opcode == 0x80
3834 && i.tm.extension_opcode == 0x4)
3835 || ((i.tm.base_opcode == 0xf6
3836 || i.tm.base_opcode == 0xc6)
3837 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3838 || (i.types[0].bitfield.qword
3839 && ((i.reg_operands == 2
3840 && i.op[0].regs == i.op[1].regs
3841 && ((i.tm.base_opcode == 0x30
3842 || i.tm.base_opcode == 0x28)
3843 && i.tm.extension_opcode == None))
3844 || (i.reg_operands == 1
3845 && i.operands == 1
3846 && i.tm.base_opcode == 0x30
3847 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3848 {
3849 /* Optimize: -O:
3850 andq $imm31, %r64 -> andl $imm31, %r32
3851 testq $imm31, %r64 -> testl $imm31, %r32
3852 xorq %r64, %r64 -> xorl %r32, %r32
3853 subq %r64, %r64 -> subl %r32, %r32
3854 movq $imm31, %r64 -> movl $imm31, %r32
3855 movq $imm32, %r64 -> movl $imm32, %r32
3856 */
3857 i.tm.opcode_modifier.norex64 = 1;
3858 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3859 {
3860 /* Handle
3861 movq $imm31, %r64 -> movl $imm31, %r32
3862 movq $imm32, %r64 -> movl $imm32, %r32
3863 */
3864 i.tm.operand_types[0].bitfield.imm32 = 1;
3865 i.tm.operand_types[0].bitfield.imm32s = 0;
3866 i.tm.operand_types[0].bitfield.imm64 = 0;
3867 i.types[0].bitfield.imm32 = 1;
3868 i.types[0].bitfield.imm32s = 0;
3869 i.types[0].bitfield.imm64 = 0;
3870 i.types[1].bitfield.dword = 1;
3871 i.types[1].bitfield.qword = 0;
3872 if (i.tm.base_opcode == 0xc6)
3873 {
3874 /* Handle
3875 movq $imm31, %r64 -> movl $imm31, %r32
3876 */
3877 i.tm.base_opcode = 0xb0;
3878 i.tm.extension_opcode = None;
3879 i.tm.opcode_modifier.shortform = 1;
3880 i.tm.opcode_modifier.modrm = 0;
3881 }
3882 }
3883 }
3884 else if (optimize > 1
3885 && i.reg_operands == 3
3886 && i.op[0].regs == i.op[1].regs
3887 && !i.types[2].bitfield.xmmword
3888 && (i.tm.opcode_modifier.vex
7a69eac3 3889 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 3890 && !i.rounding
e771e7c9 3891 && is_evex_encoding (&i.tm)
80c34c38
L		 3892 && (i.vec_encoding != vex_encoding_evex
3893 || i.tm.cpu_flags.bitfield.cpuavx512vl
0089dace 3894 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3895 && ((i.tm.base_opcode == 0x55
3896 || i.tm.base_opcode == 0x6655
3897 || i.tm.base_opcode == 0x66df
3898 || i.tm.base_opcode == 0x57
3899 || i.tm.base_opcode == 0x6657
8305403a
L		 3900 || i.tm.base_opcode == 0x66ef
3901 || i.tm.base_opcode == 0x66f8
3902 || i.tm.base_opcode == 0x66f9
3903 || i.tm.base_opcode == 0x66fa
3904 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3905 && i.tm.extension_opcode == None))
3906 {
3907 /* Optimize: -O2:
8305403a
L		 3908 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3909 vpsubq and vpsubw:
b6f8c7c4
L		 3910 EVEX VOP %zmmM, %zmmM, %zmmN
3911 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3912 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3913 EVEX VOP %ymmM, %ymmM, %ymmN
3914 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3915 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3916 VEX VOP %ymmM, %ymmM, %ymmN
3917 -> VEX VOP %xmmM, %xmmM, %xmmN
3918 VOP, one of vpandn and vpxor:
3919 VEX VOP %ymmM, %ymmM, %ymmN
3920 -> VEX VOP %xmmM, %xmmM, %xmmN
3921 VOP, one of vpandnd and vpandnq:
3922 EVEX VOP %zmmM, %zmmM, %zmmN
3923 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3924 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3925 EVEX VOP %ymmM, %ymmM, %ymmN
3926 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3927 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3928 VOP, one of vpxord and vpxorq:
3929 EVEX VOP %zmmM, %zmmM, %zmmN
3930 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3931 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3932 EVEX VOP %ymmM, %ymmM, %ymmN
3933 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3934 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3935 */
e771e7c9 3936 if (is_evex_encoding (&i.tm))
b6f8c7c4 3937 {
0089dace 3938 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3939 i.tm.opcode_modifier.evex = EVEX128;
3940 else
3941 {
3942 i.tm.opcode_modifier.vex = VEX128;
3943 i.tm.opcode_modifier.vexw = VEXW0;
3944 i.tm.opcode_modifier.evex = 0;
3945 }
3946 }
3947 else
3948 i.tm.opcode_modifier.vex = VEX128;
3949
3950 if (i.tm.opcode_modifier.vex)
3951 for (j = 0; j < 3; j++)
3952 {
3953 i.types[j].bitfield.xmmword = 1;
3954 i.types[j].bitfield.ymmword = 0;
3955 }
3956 }
3957}
3958
252b5132
RH		 3959/* This is the guts of the machine-dependent assembler. LINE points to a
3960 machine dependent instruction. This function is supposed to emit
3961 the frags/bytes it assembles to. */
3962
3963void
65da13b5 3964md_assemble (char *line)
252b5132 3965{
40fb9820 3966 unsigned int j;
83b16ac6 3967 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3968 const insn_template *t;
252b5132 3969
47926f60 3970 /* Initialize globals. */
252b5132
RH		 3971 memset (&i, '\0', sizeof (i));
3972 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3973 i.reloc[j] = NO_RELOC;
252b5132
RH		 3974 memset (disp_expressions, '\0', sizeof (disp_expressions));
3975 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3976 save_stack_p = save_stack;
252b5132
RH		 3977
3978 /* First parse an instruction mnemonic & call i386_operand for the operands.
3979 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3980 start of a (possibly prefixed) mnemonic. */
252b5132 3981
29b0f896
AM		 3982 line = parse_insn (line, mnemonic);
3983 if (line == NULL)
3984 return;
83b16ac6 3985 mnem_suffix = i.suffix;
252b5132 3986
29b0f896 3987 line = parse_operands (line, mnemonic);
ee86248c 3988 this_operand = -1;
8325cc63
JB		 3989 xfree (i.memop1_string);
3990 i.memop1_string = NULL;
29b0f896
AM		 3991 if (line == NULL)
3992 return;
252b5132 3993
29b0f896
AM		 3994 /* Now we've parsed the mnemonic into a set of templates, and have the
3995 operands at hand. */
3996
3997 /* All intel opcodes have reversed operands except for "bound" and
3998 "enter". We also don't reverse intersegment "jmp" and "call"
3999 instructions with 2 immediate operands so that the immediate segment
050dfa73 4000 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 4001 if (intel_syntax
4002 && i.operands > 1
29b0f896 4003 && (strcmp (mnemonic, "bound") != 0)
30123838 4004 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 4005 && !(operand_type_check (i.types[0], imm)
4006 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 4007 swap_operands ();
4008
ec56d5c0
JB		 4009 /* The order of the immediates should be reversed
4010 for 2 immediates extrq and insertq instructions */
4011 if (i.imm_operands == 2
4012 && (strcmp (mnemonic, "extrq") == 0
4013 || strcmp (mnemonic, "insertq") == 0))
4014 swap_2_operands (0, 1);
4015
29b0f896
AM		 4016 if (i.imm_operands)
4017 optimize_imm ();
4018
b300c311
L		 4019 /* Don't optimize displacement for movabs since it only takes 64bit
4020 displacement. */
4021 if (i.disp_operands
a501d77e 4022 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4023 && (flag_code != CODE_64BIT
4024 || strcmp (mnemonic, "movabs") != 0))
4025 optimize_disp ();
29b0f896
AM		 4026
4027 /* Next, we find a template that matches the given insn,
4028 making sure the overlap of the given operands types is consistent
4029 with the template operand types. */
252b5132 4030
83b16ac6 4031 if (!(t = match_template (mnem_suffix)))
29b0f896 4032 return;
252b5132 4033
7bab8ab5 4034 if (sse_check != check_none
81f8a913 4035 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4036 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4037 && (i.tm.cpu_flags.bitfield.cpusse
4038 || i.tm.cpu_flags.bitfield.cpusse2
4039 || i.tm.cpu_flags.bitfield.cpusse3
4040 || i.tm.cpu_flags.bitfield.cpussse3
4041 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4042 || i.tm.cpu_flags.bitfield.cpusse4_2
4043 || i.tm.cpu_flags.bitfield.cpupclmul
4044 || i.tm.cpu_flags.bitfield.cpuaes
4045 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4046 {
7bab8ab5 4047 (sse_check == check_warning
daf50ae7
L		 4048 ? as_warn
4049 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4050 }
4051
321fd21e
L		 4052 /* Zap movzx and movsx suffix. The suffix has been set from
4053 "word ptr" or "byte ptr" on the source operand in Intel syntax
4054 or extracted from mnemonic in AT&T syntax. But we'll use
4055 the destination register to choose the suffix for encoding. */
4056 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4057 {
321fd21e
L		 4058 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4059 there is no suffix, the default will be byte extension. */
4060 if (i.reg_operands != 2
4061 && !i.suffix
7ab9ffdd 4062 && intel_syntax)
321fd21e
L		 4063 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4064
4065 i.suffix = 0;
cd61ebfe 4066 }
24eab124 4067
40fb9820 4068 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4069 if (!add_prefix (FWAIT_OPCODE))
4070 return;
252b5132 4071
d5de92cf
L		 4072 /* Check if REP prefix is OK. */
4073 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4074 {
4075 as_bad (_("invalid instruction `%s' after `%s'"),
4076 i.tm.name, i.rep_prefix);
4077 return;
4078 }
4079
c1ba0266
L		 4080 /* Check for lock without a lockable instruction. Destination operand
4081 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4082 if (i.prefix[LOCK_PREFIX]
4083 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4084 || i.mem_operands == 0
4085 || (i.tm.base_opcode != 0x86
4086 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4087 {
4088 as_bad (_("expecting lockable instruction after `lock'"));
4089 return;
4090 }
4091
42164a71 4092 /* Check if HLE prefix is OK. */
165de32a 4093 if (i.hle_prefix && !check_hle ())
42164a71
L		 4094 return;
4095
7e8b059b
L		 4096 /* Check BND prefix. */
4097 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4098 as_bad (_("expecting valid branch instruction after `bnd'"));
4099
04ef582a 4100 /* Check NOTRACK prefix. */
9fef80d6
L		 4101 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4102 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4103
327e8c42
JB		 4104 if (i.tm.cpu_flags.bitfield.cpumpx)
4105 {
4106 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4107 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4108 else if (flag_code != CODE_16BIT
4109 ? i.prefix[ADDR_PREFIX]
4110 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4111 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4112 }
7e8b059b
L		 4113
4114 /* Insert BND prefix. */
4115 if (add_bnd_prefix
4116 && i.tm.opcode_modifier.bndprefixok
4117 && !i.prefix[BND_PREFIX])
4118 add_prefix (BND_PREFIX_OPCODE);
4119
29b0f896 4120 /* Check string instruction segment overrides. */
40fb9820 4121 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4122 {
4123 if (!check_string ())
5dd0794d 4124 return;
fc0763e6 4125 i.disp_operands = 0;
29b0f896 4126 }
5dd0794d 4127
b6f8c7c4
L		 4128 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4129 optimize_encoding ();
4130
29b0f896
AM		 4131 if (!process_suffix ())
4132 return;
e413e4e9 4133
bc0844ae
L		 4134 /* Update operand types. */
4135 for (j = 0; j < i.operands; j++)
4136 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4137
29b0f896
AM		 4138 /* Make still unresolved immediate matches conform to size of immediate
4139 given in i.suffix. */
4140 if (!finalize_imm ())
4141 return;
252b5132 4142
40fb9820 4143 if (i.types[0].bitfield.imm1)
29b0f896 4144 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4145
9afe6eb8
L		 4146 /* We only need to check those implicit registers for instructions
4147 with 3 operands or less. */
4148 if (i.operands <= 3)
4149 for (j = 0; j < i.operands; j++)
4150 if (i.types[j].bitfield.inoutportreg
4151 || i.types[j].bitfield.shiftcount
1b54b8d7 4152 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4153 i.reg_operands--;
40fb9820 4154
c0f3af97
L		 4155 /* ImmExt should be processed after SSE2AVX. */
4156 if (!i.tm.opcode_modifier.sse2avx
4157 && i.tm.opcode_modifier.immext)
65da13b5 4158 process_immext ();
252b5132 4159
29b0f896
AM		 4160 /* For insns with operands there are more diddles to do to the opcode. */
4161 if (i.operands)
4162 {
4163 if (!process_operands ())
4164 return;
4165 }
40fb9820 4166 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4167 {
4168 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4169 as_warn (_("translating to `%sp'"), i.tm.name);
4170 }
252b5132 4171
e771e7c9
JB		 4172 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4173 || is_evex_encoding (&i.tm))
9e5e5283
L		 4174 {
4175 if (flag_code == CODE_16BIT)
4176 {
4177 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4178 i.tm.name);
4179 return;
4180 }
c0f3af97 4181
9e5e5283
L		 4182 if (i.tm.opcode_modifier.vex)
4183 build_vex_prefix (t);
4184 else
4185 build_evex_prefix ();
4186 }
43234a1e 4187
5dd85c99
SP		 4188 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4189 instructions may define INT_OPCODE as well, so avoid this corner
4190 case for those instructions that use MODRM. */
4191 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4192 && !i.tm.opcode_modifier.modrm
4193 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4194 {
4195 i.tm.base_opcode = INT3_OPCODE;
4196 i.imm_operands = 0;
4197 }
252b5132 4198
40fb9820
L		 4199 if ((i.tm.opcode_modifier.jump
4200 || i.tm.opcode_modifier.jumpbyte
4201 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4202 && i.op[0].disps->X_op == O_constant)
4203 {
4204 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4205 the absolute address given by the constant. Since ix86 jumps and
4206 calls are pc relative, we need to generate a reloc. */
4207 i.op[0].disps->X_add_symbol = &abs_symbol;
4208 i.op[0].disps->X_op = O_symbol;
4209 }
252b5132 4210
40fb9820 4211 if (i.tm.opcode_modifier.rex64)
161a04f6 4212 i.rex |= REX_W;
252b5132 4213
29b0f896
AM		 4214 /* For 8 bit registers we need an empty rex prefix. Also if the
4215 instruction already has a prefix, we need to convert old
4216 registers to new ones. */
773f551c 4217
dc821c5f 4218 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4219 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4220 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4221 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4222 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4223 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4224 && i.rex != 0))
4225 {
4226 int x;
726c5dcd 4227
29b0f896
AM		 4228 i.rex |= REX_OPCODE;
4229 for (x = 0; x < 2; x++)
4230 {
4231 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4232 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4233 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4234 {
29b0f896
AM		 4235 /* In case it is "hi" register, give up. */
4236 if (i.op[x].regs->reg_num > 3)
a540244d 4237 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4238 "instruction requiring REX prefix."),
a540244d 4239 register_prefix, i.op[x].regs->reg_name);
773f551c 4240
29b0f896
AM		 4241 /* Otherwise it is equivalent to the extended register.
4242 Since the encoding doesn't change this is merely
4243 cosmetic cleanup for debug output. */
4244
4245 i.op[x].regs = i.op[x].regs + 8;
773f551c 4246 }
29b0f896
AM		 4247 }
4248 }
773f551c 4249
6b6b6807
L		 4250 if (i.rex == 0 && i.rex_encoding)
4251 {
4252 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4253 that uses legacy register. If it is "hi" register, don't add
4254 the REX_OPCODE byte. */
4255 int x;
4256 for (x = 0; x < 2; x++)
4257 if (i.types[x].bitfield.reg
4258 && i.types[x].bitfield.byte
4259 && (i.op[x].regs->reg_flags & RegRex64) == 0
4260 && i.op[x].regs->reg_num > 3)
4261 {
4262 i.rex_encoding = FALSE;
4263 break;
4264 }
4265
4266 if (i.rex_encoding)
4267 i.rex = REX_OPCODE;
4268 }
4269
7ab9ffdd 4270 if (i.rex != 0)
29b0f896
AM		 4271 add_prefix (REX_OPCODE | i.rex);
4272
4273 /* We are ready to output the insn. */
4274 output_insn ();
4275}
4276
4277static char *
e3bb37b5 4278parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4279{
4280 char *l = line;
4281 char *token_start = l;
4282 char *mnem_p;
5c6af06e 4283 int supported;
d3ce72d0 4284 const insn_template *t;
b6169b20 4285 char *dot_p = NULL;
29b0f896 4286
29b0f896
AM		 4287 while (1)
4288 {
4289 mnem_p = mnemonic;
4290 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4291 {
b6169b20
L		 4292 if (*mnem_p == '.')
4293 dot_p = mnem_p;
29b0f896
AM		 4294 mnem_p++;
4295 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4296 {
29b0f896
AM		 4297 as_bad (_("no such instruction: `%s'"), token_start);
4298 return NULL;
4299 }
4300 l++;
4301 }
4302 if (!is_space_char (*l)
4303 && *l != END_OF_INSN
e44823cf
JB		 4304 && (intel_syntax
4305 || (*l != PREFIX_SEPARATOR
4306 && *l != ',')))
29b0f896
AM		 4307 {
4308 as_bad (_("invalid character %s in mnemonic"),
4309 output_invalid (*l));
4310 return NULL;
4311 }
4312 if (token_start == l)
4313 {
e44823cf 4314 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4315 as_bad (_("expecting prefix; got nothing"));
4316 else
4317 as_bad (_("expecting mnemonic; got nothing"));
4318 return NULL;
4319 }
45288df1 4320
29b0f896 4321 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4322 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4323
29b0f896
AM		 4324 if (*l != END_OF_INSN
4325 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4326 && current_templates
40fb9820 4327 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4328 {
c6fb90c8 4329 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4330 {
4331 as_bad ((flag_code != CODE_64BIT
4332 ? _("`%s' is only supported in 64-bit mode")
4333 : _("`%s' is not supported in 64-bit mode")),
4334 current_templates->start->name);
4335 return NULL;
4336 }
29b0f896
AM		 4337 /* If we are in 16-bit mode, do not allow addr16 or data16.
4338 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4339 if ((current_templates->start->opcode_modifier.size16
4340 || current_templates->start->opcode_modifier.size32)
29b0f896 4341 && flag_code != CODE_64BIT
40fb9820 4342 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4343 ^ (flag_code == CODE_16BIT)))
4344 {
4345 as_bad (_("redundant %s prefix"),
4346 current_templates->start->name);
4347 return NULL;
45288df1 4348 }
86fa6981 4349 if (current_templates->start->opcode_length == 0)
29b0f896 4350 {
86fa6981
L		 4351 /* Handle pseudo prefixes. */
4352 switch (current_templates->start->base_opcode)
4353 {
4354 case 0x0:
4355 /* {disp8} */
4356 i.disp_encoding = disp_encoding_8bit;
4357 break;
4358 case 0x1:
4359 /* {disp32} */
4360 i.disp_encoding = disp_encoding_32bit;
4361 break;
4362 case 0x2:
4363 /* {load} */
4364 i.dir_encoding = dir_encoding_load;
4365 break;
4366 case 0x3:
4367 /* {store} */
4368 i.dir_encoding = dir_encoding_store;
4369 break;
4370 case 0x4:
4371 /* {vex2} */
4372 i.vec_encoding = vex_encoding_vex2;
4373 break;
4374 case 0x5:
4375 /* {vex3} */
4376 i.vec_encoding = vex_encoding_vex3;
4377 break;
4378 case 0x6:
4379 /* {evex} */
4380 i.vec_encoding = vex_encoding_evex;
4381 break;
6b6b6807
L		 4382 case 0x7:
4383 /* {rex} */
4384 i.rex_encoding = TRUE;
4385 break;
b6f8c7c4
L		 4386 case 0x8:
4387 /* {nooptimize} */
4388 i.no_optimize = TRUE;
4389 break;
86fa6981
L		 4390 default:
4391 abort ();
4392 }
4393 }
4394 else
4395 {
4396 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4397 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4398 {
4e9ac44a
L		 4399 case PREFIX_EXIST:
4400 return NULL;
4401 case PREFIX_DS:
d777820b 4402 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4403 i.notrack_prefix = current_templates->start->name;
4404 break;
4405 case PREFIX_REP:
4406 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4407 i.hle_prefix = current_templates->start->name;
4408 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4409 i.bnd_prefix = current_templates->start->name;
4410 else
4411 i.rep_prefix = current_templates->start->name;
4412 break;
4413 default:
4414 break;
86fa6981 4415 }
29b0f896
AM		 4416 }
4417 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4418 token_start = ++l;
4419 }
4420 else
4421 break;
4422 }
45288df1 4423
30a55f88 4424 if (!current_templates)
b6169b20 4425 {
f8a5c266
L		 4426 /* Check if we should swap operand or force 32bit displacement in
4427 encoding. */
30a55f88 4428 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4429 i.dir_encoding = dir_encoding_store;
8d63c93e 4430 else if (mnem_p - 3 == dot_p
a501d77e
L		 4431 && dot_p[1] == 'd'
4432 && dot_p[2] == '8')
4433 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4434 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4435 && dot_p[1] == 'd'
4436 && dot_p[2] == '3'
4437 && dot_p[3] == '2')
a501d77e 4438 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4439 else
4440 goto check_suffix;
4441 mnem_p = dot_p;
4442 *dot_p = '\0';
d3ce72d0 4443 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4444 }
4445
29b0f896
AM		 4446 if (!current_templates)
4447 {
b6169b20 4448check_suffix:
29b0f896
AM		 4449 /* See if we can get a match by trimming off a suffix. */
4450 switch (mnem_p[-1])
4451 {
4452 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4453 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4454 i.suffix = SHORT_MNEM_SUFFIX;
4455 else
1a0670f3 4456 /* Fall through. */
29b0f896
AM		 4457 case BYTE_MNEM_SUFFIX:
4458 case QWORD_MNEM_SUFFIX:
4459 i.suffix = mnem_p[-1];
4460 mnem_p[-1] = '\0';
d3ce72d0
NC		 4461 current_templates = (const templates *) hash_find (op_hash,
4462 mnemonic);
29b0f896
AM		 4463 break;
4464 case SHORT_MNEM_SUFFIX:
4465 case LONG_MNEM_SUFFIX:
4466 if (!intel_syntax)
4467 {
4468 i.suffix = mnem_p[-1];
4469 mnem_p[-1] = '\0';
d3ce72d0
NC		 4470 current_templates = (const templates *) hash_find (op_hash,
4471 mnemonic);
29b0f896
AM		 4472 }
4473 break;
252b5132 4474
29b0f896
AM		 4475 /* Intel Syntax. */
4476 case 'd':
4477 if (intel_syntax)
4478 {
9306ca4a 4479 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4480 i.suffix = SHORT_MNEM_SUFFIX;
4481 else
4482 i.suffix = LONG_MNEM_SUFFIX;
4483 mnem_p[-1] = '\0';
d3ce72d0
NC		 4484 current_templates = (const templates *) hash_find (op_hash,
4485 mnemonic);
29b0f896
AM		 4486 }
4487 break;
4488 }
4489 if (!current_templates)
4490 {
4491 as_bad (_("no such instruction: `%s'"), token_start);
4492 return NULL;
4493 }
4494 }
252b5132 4495
40fb9820
L		 4496 if (current_templates->start->opcode_modifier.jump
4497 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4498 {
4499 /* Check for a branch hint. We allow ",pt" and ",pn" for
4500 predict taken and predict not taken respectively.
4501 I'm not sure that branch hints actually do anything on loop
4502 and jcxz insns (JumpByte) for current Pentium4 chips. They
4503 may work in the future and it doesn't hurt to accept them
4504 now. */
4505 if (l[0] == ',' && l[1] == 'p')
4506 {
4507 if (l[2] == 't')
4508 {
4509 if (!add_prefix (DS_PREFIX_OPCODE))
4510 return NULL;
4511 l += 3;
4512 }
4513 else if (l[2] == 'n')
4514 {
4515 if (!add_prefix (CS_PREFIX_OPCODE))
4516 return NULL;
4517 l += 3;
4518 }
4519 }
4520 }
4521 /* Any other comma loses. */
4522 if (*l == ',')
4523 {
4524 as_bad (_("invalid character %s in mnemonic"),
4525 output_invalid (*l));
4526 return NULL;
4527 }
252b5132 4528
29b0f896 4529 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4530 supported = 0;
4531 for (t = current_templates->start; t < current_templates->end; ++t)
4532 {
c0f3af97
L		 4533 supported |= cpu_flags_match (t);
4534 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4535 {
4536 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4537 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4538
548d0ee6
JB		 4539 return l;
4540 }
29b0f896 4541 }
3629bb00 4542
548d0ee6
JB		 4543 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4544 as_bad (flag_code == CODE_64BIT
4545 ? _("`%s' is not supported in 64-bit mode")
4546 : _("`%s' is only supported in 64-bit mode"),
4547 current_templates->start->name);
4548 else
4549 as_bad (_("`%s' is not supported on `%s%s'"),
4550 current_templates->start->name,
4551 cpu_arch_name ? cpu_arch_name : default_arch,
4552 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4553
548d0ee6 4554 return NULL;
29b0f896 4555}
252b5132 4556
29b0f896 4557static char *
e3bb37b5 4558parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4559{
4560 char *token_start;
3138f287 4561
29b0f896
AM		 4562 /* 1 if operand is pending after ','. */
4563 unsigned int expecting_operand = 0;
252b5132 4564
29b0f896
AM		 4565 /* Non-zero if operand parens not balanced. */
4566 unsigned int paren_not_balanced;
4567
4568 while (*l != END_OF_INSN)
4569 {
4570 /* Skip optional white space before operand. */
4571 if (is_space_char (*l))
4572 ++l;
d02603dc 4573 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4574 {
4575 as_bad (_("invalid character %s before operand %d"),
4576 output_invalid (*l),
4577 i.operands + 1);
4578 return NULL;
4579 }
d02603dc 4580 token_start = l; /* After white space. */
29b0f896
AM		 4581 paren_not_balanced = 0;
4582 while (paren_not_balanced || *l != ',')
4583 {
4584 if (*l == END_OF_INSN)
4585 {
4586 if (paren_not_balanced)
4587 {
4588 if (!intel_syntax)
4589 as_bad (_("unbalanced parenthesis in operand %d."),
4590 i.operands + 1);
4591 else
4592 as_bad (_("unbalanced brackets in operand %d."),
4593 i.operands + 1);
4594 return NULL;
4595 }
4596 else
4597 break; /* we are done */
4598 }
d02603dc 4599 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4600 {
4601 as_bad (_("invalid character %s in operand %d"),
4602 output_invalid (*l),
4603 i.operands + 1);
4604 return NULL;
4605 }
4606 if (!intel_syntax)
4607 {
4608 if (*l == '(')
4609 ++paren_not_balanced;
4610 if (*l == ')')
4611 --paren_not_balanced;
4612 }
4613 else
4614 {
4615 if (*l == '[')
4616 ++paren_not_balanced;
4617 if (*l == ']')
4618 --paren_not_balanced;
4619 }
4620 l++;
4621 }
4622 if (l != token_start)
4623 { /* Yes, we've read in another operand. */
4624 unsigned int operand_ok;
4625 this_operand = i.operands++;
4626 if (i.operands > MAX_OPERANDS)
4627 {
4628 as_bad (_("spurious operands; (%d operands/instruction max)"),
4629 MAX_OPERANDS);
4630 return NULL;
4631 }
9d46ce34 4632 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4633 /* Now parse operand adding info to 'i' as we go along. */
4634 END_STRING_AND_SAVE (l);
4635
4636 if (intel_syntax)
4637 operand_ok =
4638 i386_intel_operand (token_start,
4639 intel_float_operand (mnemonic));
4640 else
a7619375 4641 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4642
4643 RESTORE_END_STRING (l);
4644 if (!operand_ok)
4645 return NULL;
4646 }
4647 else
4648 {
4649 if (expecting_operand)
4650 {
4651 expecting_operand_after_comma:
4652 as_bad (_("expecting operand after ','; got nothing"));
4653 return NULL;
4654 }
4655 if (*l == ',')
4656 {
4657 as_bad (_("expecting operand before ','; got nothing"));
4658 return NULL;
4659 }
4660 }
7f3f1ea2 4661
29b0f896
AM		 4662 /* Now *l must be either ',' or END_OF_INSN. */
4663 if (*l == ',')
4664 {
4665 if (*++l == END_OF_INSN)
4666 {
4667 /* Just skip it, if it's \n complain. */
4668 goto expecting_operand_after_comma;
4669 }
4670 expecting_operand = 1;
4671 }
4672 }
4673 return l;
4674}
7f3f1ea2 4675
050dfa73 4676static void
4d456e3d 4677swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4678{
4679 union i386_op temp_op;
40fb9820 4680 i386_operand_type temp_type;
050dfa73 4681 enum bfd_reloc_code_real temp_reloc;
4eed87de 4682
050dfa73
MM		 4683 temp_type = i.types[xchg2];
4684 i.types[xchg2] = i.types[xchg1];
4685 i.types[xchg1] = temp_type;
4686 temp_op = i.op[xchg2];
4687 i.op[xchg2] = i.op[xchg1];
4688 i.op[xchg1] = temp_op;
4689 temp_reloc = i.reloc[xchg2];
4690 i.reloc[xchg2] = i.reloc[xchg1];
4691 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4692
4693 if (i.mask)
4694 {
4695 if (i.mask->operand == xchg1)
4696 i.mask->operand = xchg2;
4697 else if (i.mask->operand == xchg2)
4698 i.mask->operand = xchg1;
4699 }
4700 if (i.broadcast)
4701 {
4702 if (i.broadcast->operand == xchg1)
4703 i.broadcast->operand = xchg2;
4704 else if (i.broadcast->operand == xchg2)
4705 i.broadcast->operand = xchg1;
4706 }
4707 if (i.rounding)
4708 {
4709 if (i.rounding->operand == xchg1)
4710 i.rounding->operand = xchg2;
4711 else if (i.rounding->operand == xchg2)
4712 i.rounding->operand = xchg1;
4713 }
050dfa73
MM		 4714}
4715
29b0f896 4716static void
e3bb37b5 4717swap_operands (void)
29b0f896 4718{
b7c61d9a 4719 switch (i.operands)
050dfa73 4720 {
c0f3af97 4721 case 5:
b7c61d9a 4722 case 4:
4d456e3d 4723 swap_2_operands (1, i.operands - 2);
1a0670f3 4724 /* Fall through. */
b7c61d9a
L		 4725 case 3:
4726 case 2:
4d456e3d 4727 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4728 break;
4729 default:
4730 abort ();
29b0f896 4731 }
29b0f896
AM		 4732
4733 if (i.mem_operands == 2)
4734 {
4735 const seg_entry *temp_seg;
4736 temp_seg = i.seg[0];
4737 i.seg[0] = i.seg[1];
4738 i.seg[1] = temp_seg;
4739 }
4740}
252b5132 4741
29b0f896
AM		 4742/* Try to ensure constant immediates are represented in the smallest
4743 opcode possible. */
4744static void
e3bb37b5 4745optimize_imm (void)
29b0f896
AM		 4746{
4747 char guess_suffix = 0;
4748 int op;
252b5132 4749
29b0f896
AM		 4750 if (i.suffix)
4751 guess_suffix = i.suffix;
4752 else if (i.reg_operands)
4753 {
4754 /* Figure out a suffix from the last register operand specified.
4755 We can't do this properly yet, ie. excluding InOutPortReg,
4756 but the following works for instructions with immediates.
4757 In any case, we can't set i.suffix yet. */
4758 for (op = i.operands; --op >= 0;)
dc821c5f 4759 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4760 {
40fb9820
L		 4761 guess_suffix = BYTE_MNEM_SUFFIX;
4762 break;
4763 }
dc821c5f 4764 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4765 {
40fb9820
L		 4766 guess_suffix = WORD_MNEM_SUFFIX;
4767 break;
4768 }
dc821c5f 4769 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4770 {
4771 guess_suffix = LONG_MNEM_SUFFIX;
4772 break;
4773 }
dc821c5f 4774 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4775 {
4776 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4777 break;
252b5132 4778 }
29b0f896
AM		 4779 }
4780 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4781 guess_suffix = WORD_MNEM_SUFFIX;
4782
4783 for (op = i.operands; --op >= 0;)
40fb9820 4784 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4785 {
4786 switch (i.op[op].imms->X_op)
252b5132 4787 {
29b0f896
AM		 4788 case O_constant:
4789 /* If a suffix is given, this operand may be shortened. */
4790 switch (guess_suffix)
252b5132 4791 {
29b0f896 4792 case LONG_MNEM_SUFFIX:
40fb9820
L		 4793 i.types[op].bitfield.imm32 = 1;
4794 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4795 break;
4796 case WORD_MNEM_SUFFIX:
40fb9820
L		 4797 i.types[op].bitfield.imm16 = 1;
4798 i.types[op].bitfield.imm32 = 1;
4799 i.types[op].bitfield.imm32s = 1;
4800 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4801 break;
4802 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4803 i.types[op].bitfield.imm8 = 1;
4804 i.types[op].bitfield.imm8s = 1;
4805 i.types[op].bitfield.imm16 = 1;
4806 i.types[op].bitfield.imm32 = 1;
4807 i.types[op].bitfield.imm32s = 1;
4808 i.types[op].bitfield.imm64 = 1;
29b0f896 4809 break;
252b5132 4810 }
252b5132 4811
29b0f896
AM		 4812 /* If this operand is at most 16 bits, convert it
4813 to a signed 16 bit number before trying to see
4814 whether it will fit in an even smaller size.
4815 This allows a 16-bit operand such as $0xffe0 to
4816 be recognised as within Imm8S range. */
40fb9820 4817 if ((i.types[op].bitfield.imm16)
29b0f896 4818 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4819 {
29b0f896
AM		 4820 i.op[op].imms->X_add_number =
4821 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4822 }
a28def75
L		 4823#ifdef BFD64
4824 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4825 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4826 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4827 == 0))
4828 {
4829 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4830 ^ ((offsetT) 1 << 31))
4831 - ((offsetT) 1 << 31));
4832 }
a28def75 4833#endif
40fb9820 4834 i.types[op]
c6fb90c8
L		 4835 = operand_type_or (i.types[op],
4836 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4837
29b0f896
AM		 4838 /* We must avoid matching of Imm32 templates when 64bit
4839 only immediate is available. */
4840 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4841 i.types[op].bitfield.imm32 = 0;
29b0f896 4842 break;
252b5132 4843
29b0f896
AM		 4844 case O_absent:
4845 case O_register:
4846 abort ();
4847
4848 /* Symbols and expressions. */
4849 default:
9cd96992
JB		 4850 /* Convert symbolic operand to proper sizes for matching, but don't
4851 prevent matching a set of insns that only supports sizes other
4852 than those matching the insn suffix. */
4853 {
40fb9820 4854 i386_operand_type mask, allowed;
d3ce72d0 4855 const insn_template *t;
9cd96992 4856
0dfbf9d7
L		 4857 operand_type_set (&mask, 0);
4858 operand_type_set (&allowed, 0);
40fb9820 4859
4eed87de
AM		 4860 for (t = current_templates->start;
4861 t < current_templates->end;
4862 ++t)
c6fb90c8
L		 4863 allowed = operand_type_or (allowed,
4864 t->operand_types[op]);
9cd96992
JB		 4865 switch (guess_suffix)
4866 {
4867 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4868 mask.bitfield.imm64 = 1;
4869 mask.bitfield.imm32s = 1;
9cd96992
JB		 4870 break;
4871 case LONG_MNEM_SUFFIX:
40fb9820 4872 mask.bitfield.imm32 = 1;
9cd96992
JB		 4873 break;
4874 case WORD_MNEM_SUFFIX:
40fb9820 4875 mask.bitfield.imm16 = 1;
9cd96992
JB		 4876 break;
4877 case BYTE_MNEM_SUFFIX:
40fb9820 4878 mask.bitfield.imm8 = 1;
9cd96992
JB		 4879 break;
4880 default:
9cd96992
JB		 4881 break;
4882 }
c6fb90c8 4883 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4884 if (!operand_type_all_zero (&allowed))
c6fb90c8 4885 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4886 }
29b0f896 4887 break;
252b5132 4888 }
29b0f896
AM		 4889 }
4890}
47926f60 4891
29b0f896
AM		 4892/* Try to use the smallest displacement type too. */
4893static void
e3bb37b5 4894optimize_disp (void)
29b0f896
AM		 4895{
4896 int op;
3e73aa7c 4897
29b0f896 4898 for (op = i.operands; --op >= 0;)
40fb9820 4899 if (operand_type_check (i.types[op], disp))
252b5132 4900 {
b300c311 4901 if (i.op[op].disps->X_op == O_constant)
252b5132 4902 {
91d6fa6a 4903 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4904
40fb9820 4905 if (i.types[op].bitfield.disp16
91d6fa6a 4906 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4907 {
4908 /* If this operand is at most 16 bits, convert
4909 to a signed 16 bit number and don't use 64bit
4910 displacement. */
91d6fa6a 4911 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4912 i.types[op].bitfield.disp64 = 0;
b300c311 4913 }
a28def75
L		 4914#ifdef BFD64
4915 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4916 if (i.types[op].bitfield.disp32
91d6fa6a 4917 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4918 {
4919 /* If this operand is at most 32 bits, convert
4920 to a signed 32 bit number and don't use 64bit
4921 displacement. */
91d6fa6a
NC		 4922 op_disp &= (((offsetT) 2 << 31) - 1);
4923 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4924 i.types[op].bitfield.disp64 = 0;
b300c311 4925 }
a28def75 4926#endif
91d6fa6a 4927 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4928 {
40fb9820
L		 4929 i.types[op].bitfield.disp8 = 0;
4930 i.types[op].bitfield.disp16 = 0;
4931 i.types[op].bitfield.disp32 = 0;
4932 i.types[op].bitfield.disp32s = 0;
4933 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4934 i.op[op].disps = 0;
4935 i.disp_operands--;
4936 }
4937 else if (flag_code == CODE_64BIT)
4938 {
91d6fa6a 4939 if (fits_in_signed_long (op_disp))
28a9d8f5 4940 {
40fb9820
L		 4941 i.types[op].bitfield.disp64 = 0;
4942 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4943 }
0e1147d9 4944 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4945 && fits_in_unsigned_long (op_disp))
40fb9820 4946 i.types[op].bitfield.disp32 = 1;
b300c311 4947 }
40fb9820
L		 4948 if ((i.types[op].bitfield.disp32
4949 || i.types[op].bitfield.disp32s
4950 || i.types[op].bitfield.disp16)
b5014f7a 4951 && fits_in_disp8 (op_disp))
40fb9820 4952 i.types[op].bitfield.disp8 = 1;
252b5132 4953 }
67a4f2b7
AO		 4954 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4955 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4956 {
4957 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4958 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4959 i.types[op].bitfield.disp8 = 0;
4960 i.types[op].bitfield.disp16 = 0;
4961 i.types[op].bitfield.disp32 = 0;
4962 i.types[op].bitfield.disp32s = 0;
4963 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4964 }
4965 else
b300c311 4966 /* We only support 64bit displacement on constants. */
40fb9820 4967 i.types[op].bitfield.disp64 = 0;
252b5132 4968 }
29b0f896
AM		 4969}
4970
6c30d220
L		 4971/* Check if operands are valid for the instruction. */
4972
4973static int
4974check_VecOperands (const insn_template *t)
4975{
43234a1e 4976 unsigned int op;
e2195274
JB		 4977 i386_cpu_flags cpu;
4978 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
4979
4980 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4981 any one operand are implicity requiring AVX512VL support if the actual
4982 operand size is YMMword or XMMword. Since this function runs after
4983 template matching, there's no need to check for YMMword/XMMword in
4984 the template. */
4985 cpu = cpu_flags_and (t->cpu_flags, avx512);
4986 if (!cpu_flags_all_zero (&cpu)
4987 && !t->cpu_flags.bitfield.cpuavx512vl
4988 && !cpu_arch_flags.bitfield.cpuavx512vl)
4989 {
4990 for (op = 0; op < t->operands; ++op)
4991 {
4992 if (t->operand_types[op].bitfield.zmmword
4993 && (i.types[op].bitfield.ymmword
4994 || i.types[op].bitfield.xmmword))
4995 {
4996 i.error = unsupported;
4997 return 1;
4998 }
4999 }
5000 }
43234a1e 5001
6c30d220
L		 5002 /* Without VSIB byte, we can't have a vector register for index. */
5003 if (!t->opcode_modifier.vecsib
5004 && i.index_reg
1b54b8d7
JB		 5005 && (i.index_reg->reg_type.bitfield.xmmword
5006 || i.index_reg->reg_type.bitfield.ymmword
5007 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5008 {
5009 i.error = unsupported_vector_index_register;
5010 return 1;
5011 }
5012
ad8ecc81
MZ		 5013 /* Check if default mask is allowed. */
5014 if (t->opcode_modifier.nodefmask
5015 && (!i.mask || i.mask->mask->reg_num == 0))
5016 {
5017 i.error = no_default_mask;
5018 return 1;
5019 }
5020
7bab8ab5
JB		 5021 /* For VSIB byte, we need a vector register for index, and all vector
5022 registers must be distinct. */
5023 if (t->opcode_modifier.vecsib)
5024 {
5025 if (!i.index_reg
6c30d220 5026 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5027 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5028 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5029 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5030 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5031 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5032 {
5033 i.error = invalid_vsib_address;
5034 return 1;
5035 }
5036
43234a1e
L		 5037 gas_assert (i.reg_operands == 2 || i.mask);
5038 if (i.reg_operands == 2 && !i.mask)
5039 {
1b54b8d7
JB		 5040 gas_assert (i.types[0].bitfield.regsimd);
5041 gas_assert (i.types[0].bitfield.xmmword
5042 || i.types[0].bitfield.ymmword);
5043 gas_assert (i.types[2].bitfield.regsimd);
5044 gas_assert (i.types[2].bitfield.xmmword
5045 || i.types[2].bitfield.ymmword);
43234a1e
L		 5046 if (operand_check == check_none)
5047 return 0;
5048 if (register_number (i.op[0].regs)
5049 != register_number (i.index_reg)
5050 && register_number (i.op[2].regs)
5051 != register_number (i.index_reg)
5052 && register_number (i.op[0].regs)
5053 != register_number (i.op[2].regs))
5054 return 0;
5055 if (operand_check == check_error)
5056 {
5057 i.error = invalid_vector_register_set;
5058 return 1;
5059 }
5060 as_warn (_("mask, index, and destination registers should be distinct"));
5061 }
8444f82a
MZ		 5062 else if (i.reg_operands == 1 && i.mask)
5063 {
1b54b8d7
JB		 5064 if (i.types[1].bitfield.regsimd
5065 && (i.types[1].bitfield.xmmword
5066 || i.types[1].bitfield.ymmword
5067 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5068 && (register_number (i.op[1].regs)
5069 == register_number (i.index_reg)))
5070 {
5071 if (operand_check == check_error)
5072 {
5073 i.error = invalid_vector_register_set;
5074 return 1;
5075 }
5076 if (operand_check != check_none)
5077 as_warn (_("index and destination registers should be distinct"));
5078 }
5079 }
43234a1e 5080 }
7bab8ab5 5081
43234a1e
L		 5082 /* Check if broadcast is supported by the instruction and is applied
5083 to the memory operand. */
5084 if (i.broadcast)
5085 {
8e6e0792 5086 i386_operand_type type, overlap;
43234a1e
L		 5087
5088 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5089 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5090 op = i.broadcast->operand;
8e6e0792 5091 if (!t->opcode_modifier.broadcast
32546502 5092 || !i.types[op].bitfield.mem
c39e5b26
JB		 5093 || (!i.types[op].bitfield.unspecified
5094 && (t->operand_types[op].bitfield.dword
5095 ? !i.types[op].bitfield.dword
5096 : !i.types[op].bitfield.qword)))
43234a1e
L		 5097 {
5098 bad_broadcast:
5099 i.error = unsupported_broadcast;
5100 return 1;
5101 }
8e6e0792
JB		 5102
5103 operand_type_set (&type, 0);
c39e5b26 5104 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5105 {
5106 case 8:
5107 type.bitfield.qword = 1;
5108 break;
5109 case 16:
5110 type.bitfield.xmmword = 1;
5111 break;
5112 case 32:
5113 type.bitfield.ymmword = 1;
5114 break;
5115 case 64:
5116 type.bitfield.zmmword = 1;
5117 break;
5118 default:
5119 goto bad_broadcast;
5120 }
5121
5122 overlap = operand_type_and (type, t->operand_types[op]);
5123 if (operand_type_all_zero (&overlap))
5124 goto bad_broadcast;
5125
5126 if (t->opcode_modifier.checkregsize)
5127 {
5128 unsigned int j;
5129
e2195274 5130 type.bitfield.baseindex = 1;
8e6e0792
JB		 5131 for (j = 0; j < i.operands; ++j)
5132 {
5133 if (j != op
5134 && !operand_type_register_match(i.types[j],
5135 t->operand_types[j],
5136 type,
5137 t->operand_types[op]))
5138 goto bad_broadcast;
5139 }
5140 }
43234a1e
L		 5141 }
5142 /* If broadcast is supported in this instruction, we need to check if
5143 operand of one-element size isn't specified without broadcast. */
5144 else if (t->opcode_modifier.broadcast && i.mem_operands)
5145 {
5146 /* Find memory operand. */
5147 for (op = 0; op < i.operands; op++)
5148 if (operand_type_check (i.types[op], anymem))
5149 break;
5150 gas_assert (op < i.operands);
5151 /* Check size of the memory operand. */
c39e5b26
JB		 5152 if (t->operand_types[op].bitfield.dword
5153 ? i.types[op].bitfield.dword
5154 : i.types[op].bitfield.qword)
43234a1e
L		 5155 {
5156 i.error = broadcast_needed;
5157 return 1;
5158 }
5159 }
c39e5b26
JB		 5160 else
5161 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5162
5163 /* Check if requested masking is supported. */
5164 if (i.mask
5165 && (!t->opcode_modifier.masking
5166 || (i.mask->zeroing
5167 && t->opcode_modifier.masking == MERGING_MASKING)))
5168 {
5169 i.error = unsupported_masking;
5170 return 1;
5171 }
5172
5173 /* Check if masking is applied to dest operand. */
5174 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5175 {
5176 i.error = mask_not_on_destination;
5177 return 1;
5178 }
5179
43234a1e
L		 5180 /* Check RC/SAE. */
5181 if (i.rounding)
5182 {
5183 if ((i.rounding->type != saeonly
5184 && !t->opcode_modifier.staticrounding)
5185 || (i.rounding->type == saeonly
5186 && (t->opcode_modifier.staticrounding
5187 || !t->opcode_modifier.sae)))
5188 {
5189 i.error = unsupported_rc_sae;
5190 return 1;
5191 }
5192 /* If the instruction has several immediate operands and one of
5193 them is rounding, the rounding operand should be the last
5194 immediate operand. */
5195 if (i.imm_operands > 1
5196 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5197 {
43234a1e 5198 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5199 return 1;
5200 }
6c30d220
L		 5201 }
5202
43234a1e 5203 /* Check vector Disp8 operand. */
b5014f7a
JB		 5204 if (t->opcode_modifier.disp8memshift
5205 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5206 {
5207 if (i.broadcast)
c39e5b26 5208 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
43234a1e
L		 5209 else
5210 i.memshift = t->opcode_modifier.disp8memshift;
5211
5212 for (op = 0; op < i.operands; op++)
5213 if (operand_type_check (i.types[op], disp)
5214 && i.op[op].disps->X_op == O_constant)
5215 {
b5014f7a 5216 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5217 {
b5014f7a
JB		 5218 i.types[op].bitfield.disp8 = 1;
5219 return 0;
43234a1e 5220 }
b5014f7a 5221 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5222 }
5223 }
b5014f7a
JB		 5224
5225 i.memshift = 0;
43234a1e 5226
6c30d220
L		 5227 return 0;
5228}
5229
43f3e2ee 5230/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5231 operand types. */
5232
5233static int
5234VEX_check_operands (const insn_template *t)
5235{
86fa6981 5236 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5237 {
86fa6981 5238 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5239 if (!is_evex_encoding (t))
86fa6981
L		 5240 {
5241 i.error = unsupported;
5242 return 1;
5243 }
5244 return 0;
43234a1e
L		 5245 }
5246
a683cc34 5247 if (!t->opcode_modifier.vex)
86fa6981
L		 5248 {
5249 /* This instruction template doesn't have VEX prefix. */
5250 if (i.vec_encoding != vex_encoding_default)
5251 {
5252 i.error = unsupported;
5253 return 1;
5254 }
5255 return 0;
5256 }
a683cc34
SP		 5257
5258 /* Only check VEX_Imm4, which must be the first operand. */
5259 if (t->operand_types[0].bitfield.vec_imm4)
5260 {
5261 if (i.op[0].imms->X_op != O_constant
5262 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5263 {
a65babc9 5264 i.error = bad_imm4;
891edac4
L		 5265 return 1;
5266 }
a683cc34
SP		 5267
5268 /* Turn off Imm8 so that update_imm won't complain. */
5269 i.types[0] = vec_imm4;
5270 }
5271
5272 return 0;
5273}
5274
d3ce72d0 5275static const insn_template *
83b16ac6 5276match_template (char mnem_suffix)
29b0f896
AM		 5277{
5278 /* Points to template once we've found it. */
d3ce72d0 5279 const insn_template *t;
40fb9820 5280 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5281 i386_operand_type overlap4;
29b0f896 5282 unsigned int found_reverse_match;
83b16ac6 5283 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5284 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5285 int addr_prefix_disp;
a5c311ca 5286 unsigned int j;
3629bb00 5287 unsigned int found_cpu_match;
45664ddb 5288 unsigned int check_register;
5614d22c 5289 enum i386_error specific_error = 0;
29b0f896 5290
c0f3af97
L		 5291#if MAX_OPERANDS != 5
5292# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5293#endif
5294
29b0f896 5295 found_reverse_match = 0;
539e75ad 5296 addr_prefix_disp = -1;
40fb9820
L		 5297
5298 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5299 if (intel_syntax && i.broadcast)
5300 /* nothing */;
5301 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5302 suffix_check.no_bsuf = 1;
5303 else if (i.suffix == WORD_MNEM_SUFFIX)
5304 suffix_check.no_wsuf = 1;
5305 else if (i.suffix == SHORT_MNEM_SUFFIX)
5306 suffix_check.no_ssuf = 1;
5307 else if (i.suffix == LONG_MNEM_SUFFIX)
5308 suffix_check.no_lsuf = 1;
5309 else if (i.suffix == QWORD_MNEM_SUFFIX)
5310 suffix_check.no_qsuf = 1;
5311 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5312 suffix_check.no_ldsuf = 1;
29b0f896 5313
83b16ac6
JB		 5314 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5315 if (intel_syntax)
5316 {
5317 switch (mnem_suffix)
5318 {
5319 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5320 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5321 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5322 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5323 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5324 }
5325 }
5326
01559ecc
L		 5327 /* Must have right number of operands. */
5328 i.error = number_of_operands_mismatch;
5329
45aa61fe 5330 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5331 {
539e75ad
L		 5332 addr_prefix_disp = -1;
5333
29b0f896
AM		 5334 if (i.operands != t->operands)
5335 continue;
5336
50aecf8c 5337 /* Check processor support. */
a65babc9 5338 i.error = unsupported;
c0f3af97
L		 5339 found_cpu_match = (cpu_flags_match (t)
5340 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5341 if (!found_cpu_match)
5342 continue;
5343
e1d4d893 5344 /* Check AT&T mnemonic. */
a65babc9 5345 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5346 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5347 continue;
5348
e92bae62 5349 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5350 i.error = unsupported_syntax;
5c07affc 5351 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5352 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5353 || (intel64 && t->opcode_modifier.amd64)
5354 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5355 continue;
5356
20592a94 5357 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5358 i.error = invalid_instruction_suffix;
567e4e96
L		 5359 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5360 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5361 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5362 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5363 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5364 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5365 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5366 continue;
83b16ac6
JB		 5367 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5368 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5369 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5370 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5371 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5372 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5373 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5374 continue;
29b0f896 5375
5c07affc 5376 if (!operand_size_match (t))
7d5e4556 5377 continue;
539e75ad 5378
5c07affc
L		 5379 for (j = 0; j < MAX_OPERANDS; j++)
5380 operand_types[j] = t->operand_types[j];
5381
45aa61fe
AM		 5382 /* In general, don't allow 64-bit operands in 32-bit mode. */
5383 if (i.suffix == QWORD_MNEM_SUFFIX
5384 && flag_code != CODE_64BIT
5385 && (intel_syntax
40fb9820 5386 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5387 && !intel_float_operand (t->name))
5388 : intel_float_operand (t->name) != 2)
40fb9820 5389 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5390 && !operand_types[0].bitfield.regsimd)
40fb9820 5391 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5392 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5393 && (t->base_opcode != 0x0fc7
5394 || t->extension_opcode != 1 /* cmpxchg8b */))
5395 continue;
5396
192dc9c6
JB		 5397 /* In general, don't allow 32-bit operands on pre-386. */
5398 else if (i.suffix == LONG_MNEM_SUFFIX
5399 && !cpu_arch_flags.bitfield.cpui386
5400 && (intel_syntax
5401 ? (!t->opcode_modifier.ignoresize
5402 && !intel_float_operand (t->name))
5403 : intel_float_operand (t->name) != 2)
5404 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5405 && !operand_types[0].bitfield.regsimd)
192dc9c6 5406 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5407 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5408 continue;
5409
29b0f896 5410 /* Do not verify operands when there are none. */
50aecf8c 5411 else
29b0f896 5412 {
c6fb90c8 5413 if (!t->operands)
2dbab7d5
L		 5414 /* We've found a match; break out of loop. */
5415 break;
29b0f896 5416 }
252b5132 5417
539e75ad
L		 5418 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5419 into Disp32/Disp16/Disp32 operand. */
5420 if (i.prefix[ADDR_PREFIX] != 0)
5421 {
40fb9820 5422 /* There should be only one Disp operand. */
539e75ad
L		 5423 switch (flag_code)
5424 {
5425 case CODE_16BIT:
40fb9820
L		 5426 for (j = 0; j < MAX_OPERANDS; j++)
5427 {
5428 if (operand_types[j].bitfield.disp16)
5429 {
5430 addr_prefix_disp = j;
5431 operand_types[j].bitfield.disp32 = 1;
5432 operand_types[j].bitfield.disp16 = 0;
5433 break;
5434 }
5435 }
539e75ad
L		 5436 break;
5437 case CODE_32BIT:
40fb9820
L		 5438 for (j = 0; j < MAX_OPERANDS; j++)
5439 {
5440 if (operand_types[j].bitfield.disp32)
5441 {
5442 addr_prefix_disp = j;
5443 operand_types[j].bitfield.disp32 = 0;
5444 operand_types[j].bitfield.disp16 = 1;
5445 break;
5446 }
5447 }
539e75ad
L		 5448 break;
5449 case CODE_64BIT:
40fb9820
L		 5450 for (j = 0; j < MAX_OPERANDS; j++)
5451 {
5452 if (operand_types[j].bitfield.disp64)
5453 {
5454 addr_prefix_disp = j;
5455 operand_types[j].bitfield.disp64 = 0;
5456 operand_types[j].bitfield.disp32 = 1;
5457 break;
5458 }
5459 }
539e75ad
L		 5460 break;
5461 }
539e75ad
L		 5462 }
5463
02a86693
L		 5464 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5465 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5466 continue;
5467
56ffb741 5468 /* We check register size if needed. */
e2195274
JB		 5469 if (t->opcode_modifier.checkregsize)
5470 {
5471 check_register = (1 << t->operands) - 1;
5472 if (i.broadcast)
5473 check_register &= ~(1 << i.broadcast->operand);
5474 }
5475 else
5476 check_register = 0;
5477
c6fb90c8 5478 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5479 switch (t->operands)
5480 {
5481 case 1:
40fb9820 5482 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5483 continue;
5484 break;
5485 case 2:
33eaf5de 5486 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5487 only in 32bit mode and we can use opcode 0x90. In 64bit
5488 mode, we can't use 0x90 for xchg %eax, %eax since it should
5489 zero-extend %eax to %rax. */
5490 if (flag_code == CODE_64BIT
5491 && t->base_opcode == 0x90
0dfbf9d7
L		 5492 && operand_type_equal (&i.types [0], &acc32)
5493 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5494 continue;
1212781b
JB		 5495 /* xrelease mov %eax, <disp> is another special case. It must not
5496 match the accumulator-only encoding of mov. */
5497 if (flag_code != CODE_64BIT
5498 && i.hle_prefix
5499 && t->base_opcode == 0xa0
5500 && i.types[0].bitfield.acc
5501 && operand_type_check (i.types[1], anymem))
5502 continue;
86fa6981
L		 5503 /* If we want store form, we reverse direction of operands. */
5504 if (i.dir_encoding == dir_encoding_store
5505 && t->opcode_modifier.d)
5506 goto check_reverse;
1a0670f3 5507 /* Fall through. */
b6169b20 5508
29b0f896 5509 case 3:
86fa6981
L		 5510 /* If we want store form, we skip the current load. */
5511 if (i.dir_encoding == dir_encoding_store
5512 && i.mem_operands == 0
5513 && t->opcode_modifier.load)
fa99fab2 5514 continue;
1a0670f3 5515 /* Fall through. */
f48ff2ae 5516 case 4:
c0f3af97 5517 case 5:
c6fb90c8 5518 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5519 if (!operand_type_match (overlap0, i.types[0])
5520 || !operand_type_match (overlap1, i.types[1])
e2195274 5521 || ((check_register & 3) == 3
dc821c5f 5522 && !operand_type_register_match (i.types[0],
40fb9820 5523 operand_types[0],
dc821c5f 5524 i.types[1],
40fb9820 5525 operand_types[1])))
29b0f896
AM		 5526 {
5527 /* Check if other direction is valid ... */
38e314eb 5528 if (!t->opcode_modifier.d)
29b0f896
AM		 5529 continue;
5530
b6169b20 5531check_reverse:
29b0f896 5532 /* Try reversing direction of operands. */
c6fb90c8
L		 5533 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5534 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5535 if (!operand_type_match (overlap0, i.types[0])
5536 || !operand_type_match (overlap1, i.types[1])
45664ddb 5537 || (check_register
dc821c5f 5538 && !operand_type_register_match (i.types[0],
45664ddb 5539 operand_types[1],
45664ddb
L		 5540 i.types[1],
5541 operand_types[0])))
29b0f896
AM		 5542 {
5543 /* Does not match either direction. */
5544 continue;
5545 }
38e314eb 5546 /* found_reverse_match holds which of D or FloatR
29b0f896 5547 we've found. */
38e314eb
JB		 5548 if (!t->opcode_modifier.d)
5549 found_reverse_match = 0;
5550 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5551 found_reverse_match = Opcode_FloatD;
5552 else
38e314eb 5553 found_reverse_match = Opcode_D;
40fb9820 5554 if (t->opcode_modifier.floatr)
8a2ed489 5555 found_reverse_match |= Opcode_FloatR;
29b0f896 5556 }
f48ff2ae 5557 else
29b0f896 5558 {
f48ff2ae 5559 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5560 switch (t->operands)
5561 {
c0f3af97
L		 5562 case 5:
5563 overlap4 = operand_type_and (i.types[4],
5564 operand_types[4]);
1a0670f3 5565 /* Fall through. */
d1cbb4db 5566 case 4:
c6fb90c8
L		 5567 overlap3 = operand_type_and (i.types[3],
5568 operand_types[3]);
1a0670f3 5569 /* Fall through. */
d1cbb4db 5570 case 3:
c6fb90c8
L		 5571 overlap2 = operand_type_and (i.types[2],
5572 operand_types[2]);
d1cbb4db
L		 5573 break;
5574 }
29b0f896 5575
f48ff2ae
L		 5576 switch (t->operands)
5577 {
c0f3af97
L		 5578 case 5:
5579 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5580 || !operand_type_register_match (i.types[3],
c0f3af97 5581 operand_types[3],
c0f3af97
L		 5582 i.types[4],
5583 operand_types[4]))
5584 continue;
1a0670f3 5585 /* Fall through. */
f48ff2ae 5586 case 4:
40fb9820 5587 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5588 || ((check_register & 0xa) == 0xa
5589 && !operand_type_register_match (i.types[1],
f7768225
JB		 5590 operand_types[1],
5591 i.types[3],
e2195274
JB		 5592 operand_types[3]))
5593 || ((check_register & 0xc) == 0xc
5594 && !operand_type_register_match (i.types[2],
5595 operand_types[2],
5596 i.types[3],
5597 operand_types[3])))
f48ff2ae 5598 continue;
1a0670f3 5599 /* Fall through. */
f48ff2ae
L		 5600 case 3:
5601 /* Here we make use of the fact that there are no
23e42951 5602 reverse match 3 operand instructions. */
40fb9820 5603 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5604 || ((check_register & 5) == 5
5605 && !operand_type_register_match (i.types[0],
23e42951
JB		 5606 operand_types[0],
5607 i.types[2],
e2195274
JB		 5608 operand_types[2]))
5609 || ((check_register & 6) == 6
5610 && !operand_type_register_match (i.types[1],
5611 operand_types[1],
5612 i.types[2],
5613 operand_types[2])))
f48ff2ae
L		 5614 continue;
5615 break;
5616 }
29b0f896 5617 }
f48ff2ae 5618 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5619 slip through to break. */
5620 }
3629bb00 5621 if (!found_cpu_match)
29b0f896
AM		 5622 {
5623 found_reverse_match = 0;
5624 continue;
5625 }
c0f3af97 5626
5614d22c
JB		 5627 /* Check if vector and VEX operands are valid. */
5628 if (check_VecOperands (t) || VEX_check_operands (t))
5629 {
5630 specific_error = i.error;
5631 continue;
5632 }
a683cc34 5633
29b0f896
AM		 5634 /* We've found a match; break out of loop. */
5635 break;
5636 }
5637
5638 if (t == current_templates->end)
5639 {
5640 /* We found no match. */
a65babc9 5641 const char *err_msg;
5614d22c 5642 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5643 {
5644 default:
5645 abort ();
86e026a4 5646 case operand_size_mismatch:
a65babc9
L		 5647 err_msg = _("operand size mismatch");
5648 break;
5649 case operand_type_mismatch:
5650 err_msg = _("operand type mismatch");
5651 break;
5652 case register_type_mismatch:
5653 err_msg = _("register type mismatch");
5654 break;
5655 case number_of_operands_mismatch:
5656 err_msg = _("number of operands mismatch");
5657 break;
5658 case invalid_instruction_suffix:
5659 err_msg = _("invalid instruction suffix");
5660 break;
5661 case bad_imm4:
4a2608e3 5662 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5663 break;
a65babc9
L		 5664 case unsupported_with_intel_mnemonic:
5665 err_msg = _("unsupported with Intel mnemonic");
5666 break;
5667 case unsupported_syntax:
5668 err_msg = _("unsupported syntax");
5669 break;
5670 case unsupported:
35262a23 5671 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5672 current_templates->start->name);
5673 return NULL;
6c30d220
L		 5674 case invalid_vsib_address:
5675 err_msg = _("invalid VSIB address");
5676 break;
7bab8ab5
JB		 5677 case invalid_vector_register_set:
5678 err_msg = _("mask, index, and destination registers must be distinct");
5679 break;
6c30d220
L		 5680 case unsupported_vector_index_register:
5681 err_msg = _("unsupported vector index register");
5682 break;
43234a1e
L		 5683 case unsupported_broadcast:
5684 err_msg = _("unsupported broadcast");
5685 break;
5686 case broadcast_not_on_src_operand:
5687 err_msg = _("broadcast not on source memory operand");
5688 break;
5689 case broadcast_needed:
5690 err_msg = _("broadcast is needed for operand of such type");
5691 break;
5692 case unsupported_masking:
5693 err_msg = _("unsupported masking");
5694 break;
5695 case mask_not_on_destination:
5696 err_msg = _("mask not on destination operand");
5697 break;
5698 case no_default_mask:
5699 err_msg = _("default mask isn't allowed");
5700 break;
5701 case unsupported_rc_sae:
5702 err_msg = _("unsupported static rounding/sae");
5703 break;
5704 case rc_sae_operand_not_last_imm:
5705 if (intel_syntax)
5706 err_msg = _("RC/SAE operand must precede immediate operands");
5707 else
5708 err_msg = _("RC/SAE operand must follow immediate operands");
5709 break;
5710 case invalid_register_operand:
5711 err_msg = _("invalid register operand");
5712 break;
a65babc9
L		 5713 }
5714 as_bad (_("%s for `%s'"), err_msg,
891edac4 5715 current_templates->start->name);
fa99fab2 5716 return NULL;
29b0f896 5717 }
252b5132 5718
29b0f896
AM		 5719 if (!quiet_warnings)
5720 {
5721 if (!intel_syntax
40fb9820
L		 5722 && (i.types[0].bitfield.jumpabsolute
5723 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5724 {
5725 as_warn (_("indirect %s without `*'"), t->name);
5726 }
5727
40fb9820
L		 5728 if (t->opcode_modifier.isprefix
5729 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5730 {
5731 /* Warn them that a data or address size prefix doesn't
5732 affect assembly of the next line of code. */
5733 as_warn (_("stand-alone `%s' prefix"), t->name);
5734 }
5735 }
5736
5737 /* Copy the template we found. */
5738 i.tm = *t;
539e75ad
L		 5739
5740 if (addr_prefix_disp != -1)
5741 i.tm.operand_types[addr_prefix_disp]
5742 = operand_types[addr_prefix_disp];
5743
29b0f896
AM		 5744 if (found_reverse_match)
5745 {
5746 /* If we found a reverse match we must alter the opcode
5747 direction bit. found_reverse_match holds bits to change
5748 (different for int & float insns). */
5749
5750 i.tm.base_opcode ^= found_reverse_match;
5751
539e75ad
L		 5752 i.tm.operand_types[0] = operand_types[1];
5753 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5754 }
5755
fa99fab2 5756 return t;
29b0f896
AM		 5757}
5758
5759static int
e3bb37b5 5760check_string (void)
29b0f896 5761{
40fb9820
L		 5762 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5763 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5764 {
5765 if (i.seg[0] != NULL && i.seg[0] != &es)
5766 {
a87af027 5767 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5768 i.tm.name,
a87af027
JB		 5769 mem_op + 1,
5770 register_prefix);
29b0f896
AM		 5771 return 0;
5772 }
5773 /* There's only ever one segment override allowed per instruction.
5774 This instruction possibly has a legal segment override on the
5775 second operand, so copy the segment to where non-string
5776 instructions store it, allowing common code. */
5777 i.seg[0] = i.seg[1];
5778 }
40fb9820 5779 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5780 {
5781 if (i.seg[1] != NULL && i.seg[1] != &es)
5782 {
a87af027 5783 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5784 i.tm.name,
a87af027
JB		 5785 mem_op + 2,
5786 register_prefix);
29b0f896
AM		 5787 return 0;
5788 }
5789 }
5790 return 1;
5791}
5792
5793static int
543613e9 5794process_suffix (void)
29b0f896
AM		 5795{
5796 /* If matched instruction specifies an explicit instruction mnemonic
5797 suffix, use it. */
40fb9820
L		 5798 if (i.tm.opcode_modifier.size16)
5799 i.suffix = WORD_MNEM_SUFFIX;
5800 else if (i.tm.opcode_modifier.size32)
5801 i.suffix = LONG_MNEM_SUFFIX;
5802 else if (i.tm.opcode_modifier.size64)
5803 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5804 else if (i.reg_operands)
5805 {
5806 /* If there's no instruction mnemonic suffix we try to invent one
5807 based on register operands. */
5808 if (!i.suffix)
5809 {
5810 /* We take i.suffix from the last register operand specified,
5811 Destination register type is more significant than source
381d071f
L		 5812 register type. crc32 in SSE4.2 prefers source register
5813 type. */
5814 if (i.tm.base_opcode == 0xf20f38f1)
5815 {
dc821c5f 5816 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5817 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5818 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5819 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5820 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5821 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5822 }
9344ff29 5823 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5824 {
dc821c5f 5825 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5826 i.suffix = BYTE_MNEM_SUFFIX;
5827 }
381d071f
L		 5828
5829 if (!i.suffix)
5830 {
5831 int op;
5832
20592a94
L		 5833 if (i.tm.base_opcode == 0xf20f38f1
5834 || i.tm.base_opcode == 0xf20f38f0)
5835 {
5836 /* We have to know the operand size for crc32. */
5837 as_bad (_("ambiguous memory operand size for `%s`"),
5838 i.tm.name);
5839 return 0;
5840 }
5841
381d071f 5842 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5843 if (!i.tm.operand_types[op].bitfield.inoutportreg
5844 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5845 {
8819ada6
JB		 5846 if (!i.types[op].bitfield.reg)
5847 continue;
5848 if (i.types[op].bitfield.byte)
5849 i.suffix = BYTE_MNEM_SUFFIX;
5850 else if (i.types[op].bitfield.word)
5851 i.suffix = WORD_MNEM_SUFFIX;
5852 else if (i.types[op].bitfield.dword)
5853 i.suffix = LONG_MNEM_SUFFIX;
5854 else if (i.types[op].bitfield.qword)
5855 i.suffix = QWORD_MNEM_SUFFIX;
5856 else
5857 continue;
5858 break;
381d071f
L		 5859 }
5860 }
29b0f896
AM		 5861 }
5862 else if (i.suffix == BYTE_MNEM_SUFFIX)
5863 {
2eb952a4
L		 5864 if (intel_syntax
5865 && i.tm.opcode_modifier.ignoresize
5866 && i.tm.opcode_modifier.no_bsuf)
5867 i.suffix = 0;
5868 else if (!check_byte_reg ())
29b0f896
AM		 5869 return 0;
5870 }
5871 else if (i.suffix == LONG_MNEM_SUFFIX)
5872 {
2eb952a4
L		 5873 if (intel_syntax
5874 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5875 && i.tm.opcode_modifier.no_lsuf
5876 && !i.tm.opcode_modifier.todword
5877 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5878 i.suffix = 0;
5879 else if (!check_long_reg ())
29b0f896
AM		 5880 return 0;
5881 }
5882 else if (i.suffix == QWORD_MNEM_SUFFIX)
5883 {
955e1e6a
L		 5884 if (intel_syntax
5885 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5886 && i.tm.opcode_modifier.no_qsuf
5887 && !i.tm.opcode_modifier.todword
5888 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5889 i.suffix = 0;
5890 else if (!check_qword_reg ())
29b0f896
AM		 5891 return 0;
5892 }
5893 else if (i.suffix == WORD_MNEM_SUFFIX)
5894 {
2eb952a4
L		 5895 if (intel_syntax
5896 && i.tm.opcode_modifier.ignoresize
5897 && i.tm.opcode_modifier.no_wsuf)
5898 i.suffix = 0;
5899 else if (!check_word_reg ())
29b0f896
AM		 5900 return 0;
5901 }
40fb9820 5902 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5903 /* Do nothing if the instruction is going to ignore the prefix. */
5904 ;
5905 else
5906 abort ();
5907 }
40fb9820 5908 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5909 && !i.suffix
5910 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5911 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5912 {
5913 i.suffix = stackop_size;
5914 }
9306ca4a
JB		 5915 else if (intel_syntax
5916 && !i.suffix
40fb9820
L		 5917 && (i.tm.operand_types[0].bitfield.jumpabsolute
5918 || i.tm.opcode_modifier.jumpbyte
5919 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5920 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5921 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5922 {
5923 switch (flag_code)
5924 {
5925 case CODE_64BIT:
40fb9820 5926 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5927 {
5928 i.suffix = QWORD_MNEM_SUFFIX;
5929 break;
5930 }
1a0670f3 5931 /* Fall through. */
9306ca4a 5932 case CODE_32BIT:
40fb9820 5933 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5934 i.suffix = LONG_MNEM_SUFFIX;
5935 break;
5936 case CODE_16BIT:
40fb9820 5937 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5938 i.suffix = WORD_MNEM_SUFFIX;
5939 break;
5940 }
5941 }
252b5132 5942
9306ca4a 5943 if (!i.suffix)
29b0f896 5944 {
9306ca4a
JB		 5945 if (!intel_syntax)
5946 {
40fb9820 5947 if (i.tm.opcode_modifier.w)
9306ca4a 5948 {
4eed87de
AM		 5949 as_bad (_("no instruction mnemonic suffix given and "
5950 "no register operands; can't size instruction"));
9306ca4a
JB		 5951 return 0;
5952 }
5953 }
5954 else
5955 {
40fb9820 5956 unsigned int suffixes;
7ab9ffdd 5957
40fb9820
L		 5958 suffixes = !i.tm.opcode_modifier.no_bsuf;
5959 if (!i.tm.opcode_modifier.no_wsuf)
5960 suffixes |= 1 << 1;
5961 if (!i.tm.opcode_modifier.no_lsuf)
5962 suffixes |= 1 << 2;
fc4adea1 5963 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5964 suffixes |= 1 << 3;
5965 if (!i.tm.opcode_modifier.no_ssuf)
5966 suffixes |= 1 << 4;
c2b9da16 5967 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5968 suffixes |= 1 << 5;
5969
5970 /* There are more than suffix matches. */
5971 if (i.tm.opcode_modifier.w
9306ca4a 5972 || ((suffixes & (suffixes - 1))
40fb9820
L		 5973 && !i.tm.opcode_modifier.defaultsize
5974 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5975 {
5976 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5977 return 0;
5978 }
5979 }
29b0f896 5980 }
252b5132 5981
d2224064
JB		 5982 /* Change the opcode based on the operand size given by i.suffix. */
5983 switch (i.suffix)
29b0f896 5984 {
d2224064
JB		 5985 /* Size floating point instruction. */
5986 case LONG_MNEM_SUFFIX:
5987 if (i.tm.opcode_modifier.floatmf)
5988 {
5989 i.tm.base_opcode ^= 4;
5990 break;
5991 }
5992 /* fall through */
5993 case WORD_MNEM_SUFFIX:
5994 case QWORD_MNEM_SUFFIX:
29b0f896 5995 /* It's not a byte, select word/dword operation. */
40fb9820 5996 if (i.tm.opcode_modifier.w)
29b0f896 5997 {
40fb9820 5998 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5999 i.tm.base_opcode |= 8;
6000 else
6001 i.tm.base_opcode |= 1;
6002 }
d2224064
JB		 6003 /* fall through */
6004 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 6005 /* Now select between word & dword operations via the operand
6006 size prefix, except for instructions that will ignore this
6007 prefix anyway. */
75c0a438
L		 6008 if (i.reg_operands > 0
6009 && i.types[0].bitfield.reg
6010 && i.tm.opcode_modifier.addrprefixopreg
6011 && (i.tm.opcode_modifier.immext
6012 || i.operands == 1))
cb712a9e 6013 {
ca61edf2
L		 6014 /* The address size override prefix changes the size of the
6015 first operand. */
40fb9820 6016 if ((flag_code == CODE_32BIT
75c0a438 6017 && i.op[0].regs->reg_type.bitfield.word)
40fb9820 6018 || (flag_code != CODE_32BIT
75c0a438 6019 && i.op[0].regs->reg_type.bitfield.dword))
cb712a9e
L		 6020 if (!add_prefix (ADDR_PREFIX_OPCODE))
6021 return 0;
6022 }
6023 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6024 && !i.tm.opcode_modifier.ignoresize
6025 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 6026 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6027 || (flag_code == CODE_64BIT
40fb9820 6028 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6029 {
6030 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6031
40fb9820 6032 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6033 prefix = ADDR_PREFIX_OPCODE;
252b5132 6034
29b0f896
AM		 6035 if (!add_prefix (prefix))
6036 return 0;
24eab124 6037 }
252b5132 6038
29b0f896
AM		 6039 /* Set mode64 for an operand. */
6040 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6041 && flag_code == CODE_64BIT
d2224064 6042 && !i.tm.opcode_modifier.norex64
46e883c5 6043 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6044 need rex64. */
6045 && ! (i.operands == 2
6046 && i.tm.base_opcode == 0x90
6047 && i.tm.extension_opcode == None
6048 && operand_type_equal (&i.types [0], &acc64)
6049 && operand_type_equal (&i.types [1], &acc64)))
6050 i.rex |= REX_W;
3e73aa7c 6051
d2224064 6052 break;
29b0f896 6053 }
7ecd2f8b 6054
c0a30a9f
L		 6055 if (i.reg_operands != 0
6056 && i.operands > 1
6057 && i.tm.opcode_modifier.addrprefixopreg
6058 && !i.tm.opcode_modifier.immext)
6059 {
6060 /* Check invalid register operand when the address size override
6061 prefix changes the size of register operands. */
6062 unsigned int op;
6063 enum { need_word, need_dword, need_qword } need;
6064
6065 if (flag_code == CODE_32BIT)
6066 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6067 else
6068 {
6069 if (i.prefix[ADDR_PREFIX])
6070 need = need_dword;
6071 else
6072 need = flag_code == CODE_64BIT ? need_qword : need_word;
6073 }
6074
6075 for (op = 0; op < i.operands; op++)
6076 if (i.types[op].bitfield.reg
6077 && ((need == need_word
6078 && !i.op[op].regs->reg_type.bitfield.word)
6079 || (need == need_dword
6080 && !i.op[op].regs->reg_type.bitfield.dword)
6081 || (need == need_qword
6082 && !i.op[op].regs->reg_type.bitfield.qword)))
6083 {
6084 as_bad (_("invalid register operand size for `%s'"),
6085 i.tm.name);
6086 return 0;
6087 }
6088 }
6089
29b0f896
AM		 6090 return 1;
6091}
3e73aa7c 6092
29b0f896 6093static int
543613e9 6094check_byte_reg (void)
29b0f896
AM		 6095{
6096 int op;
543613e9 6097
29b0f896
AM		 6098 for (op = i.operands; --op >= 0;)
6099 {
dc821c5f
JB		 6100 /* Skip non-register operands. */
6101 if (!i.types[op].bitfield.reg)
6102 continue;
6103
29b0f896
AM		 6104 /* If this is an eight bit register, it's OK. If it's the 16 or
6105 32 bit version of an eight bit register, we will just use the
6106 low portion, and that's OK too. */
dc821c5f 6107 if (i.types[op].bitfield.byte)
29b0f896
AM		 6108 continue;
6109
5a819eb9
JB		 6110 /* I/O port address operands are OK too. */
6111 if (i.tm.operand_types[op].bitfield.inoutportreg)
6112 continue;
6113
9344ff29
L		 6114 /* crc32 doesn't generate this warning. */
6115 if (i.tm.base_opcode == 0xf20f38f0)
6116 continue;
6117
dc821c5f
JB		 6118 if ((i.types[op].bitfield.word
6119 || i.types[op].bitfield.dword
6120 || i.types[op].bitfield.qword)
5a819eb9
JB		 6121 && i.op[op].regs->reg_num < 4
6122 /* Prohibit these changes in 64bit mode, since the lowering
6123 would be more complicated. */
6124 && flag_code != CODE_64BIT)
29b0f896 6125 {
29b0f896 6126#if REGISTER_WARNINGS
5a819eb9 6127 if (!quiet_warnings)
a540244d
L		 6128 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6129 register_prefix,
dc821c5f 6130 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6131 ? REGNAM_AL - REGNAM_AX
6132 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6133 register_prefix,
29b0f896
AM		 6134 i.op[op].regs->reg_name,
6135 i.suffix);
6136#endif
6137 continue;
6138 }
6139 /* Any other register is bad. */
dc821c5f 6140 if (i.types[op].bitfield.reg
40fb9820 6141 || i.types[op].bitfield.regmmx
1b54b8d7 6142 || i.types[op].bitfield.regsimd
40fb9820
L		 6143 || i.types[op].bitfield.sreg2
6144 || i.types[op].bitfield.sreg3
6145 || i.types[op].bitfield.control
6146 || i.types[op].bitfield.debug
ca0d63fe 6147 || i.types[op].bitfield.test)
29b0f896 6148 {
a540244d
L		 6149 as_bad (_("`%s%s' not allowed with `%s%c'"),
6150 register_prefix,
29b0f896
AM		 6151 i.op[op].regs->reg_name,
6152 i.tm.name,
6153 i.suffix);
6154 return 0;
6155 }
6156 }
6157 return 1;
6158}
6159
6160static int
e3bb37b5 6161check_long_reg (void)
29b0f896
AM		 6162{
6163 int op;
6164
6165 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6166 /* Skip non-register operands. */
6167 if (!i.types[op].bitfield.reg)
6168 continue;
29b0f896
AM		 6169 /* Reject eight bit registers, except where the template requires
6170 them. (eg. movzb) */
dc821c5f
JB		 6171 else if (i.types[op].bitfield.byte
6172 && (i.tm.operand_types[op].bitfield.reg
6173 || i.tm.operand_types[op].bitfield.acc)
6174 && (i.tm.operand_types[op].bitfield.word
6175 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6176 {
a540244d
L		 6177 as_bad (_("`%s%s' not allowed with `%s%c'"),
6178 register_prefix,
29b0f896
AM		 6179 i.op[op].regs->reg_name,
6180 i.tm.name,
6181 i.suffix);
6182 return 0;
6183 }
e4630f71 6184 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6185 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6186 && i.types[op].bitfield.word
6187 && (i.tm.operand_types[op].bitfield.reg
6188 || i.tm.operand_types[op].bitfield.acc)
6189 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6190 {
6191 /* Prohibit these changes in the 64bit mode, since the
6192 lowering is more complicated. */
6193 if (flag_code == CODE_64BIT)
252b5132 6194 {
2b5d6a91 6195 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6196 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6197 i.suffix);
6198 return 0;
252b5132 6199 }
29b0f896 6200#if REGISTER_WARNINGS
cecf1424
JB		 6201 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6202 register_prefix,
6203 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6204 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6205#endif
252b5132 6206 }
e4630f71 6207 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6208 else if (i.types[op].bitfield.qword
6209 && (i.tm.operand_types[op].bitfield.reg
6210 || i.tm.operand_types[op].bitfield.acc)
6211 && i.tm.operand_types[op].bitfield.dword)
252b5132 6212 {
34828aad 6213 if (intel_syntax
ca61edf2 6214 && i.tm.opcode_modifier.toqword
1b54b8d7 6215 && !i.types[0].bitfield.regsimd)
34828aad 6216 {
ca61edf2 6217 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6218 i.suffix = QWORD_MNEM_SUFFIX;
6219 }
6220 else
6221 {
2b5d6a91 6222 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6223 register_prefix, i.op[op].regs->reg_name,
6224 i.suffix);
6225 return 0;
6226 }
29b0f896
AM		 6227 }
6228 return 1;
6229}
252b5132 6230
29b0f896 6231static int
e3bb37b5 6232check_qword_reg (void)
29b0f896
AM		 6233{
6234 int op;
252b5132 6235
29b0f896 6236 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6237 /* Skip non-register operands. */
6238 if (!i.types[op].bitfield.reg)
6239 continue;
29b0f896
AM		 6240 /* Reject eight bit registers, except where the template requires
6241 them. (eg. movzb) */
dc821c5f
JB		 6242 else if (i.types[op].bitfield.byte
6243 && (i.tm.operand_types[op].bitfield.reg
6244 || i.tm.operand_types[op].bitfield.acc)
6245 && (i.tm.operand_types[op].bitfield.word
6246 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6247 {
a540244d
L		 6248 as_bad (_("`%s%s' not allowed with `%s%c'"),
6249 register_prefix,
29b0f896
AM		 6250 i.op[op].regs->reg_name,
6251 i.tm.name,
6252 i.suffix);
6253 return 0;
6254 }
e4630f71 6255 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6256 else if ((i.types[op].bitfield.word
6257 || i.types[op].bitfield.dword)
6258 && (i.tm.operand_types[op].bitfield.reg
6259 || i.tm.operand_types[op].bitfield.acc)
6260 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6261 {
6262 /* Prohibit these changes in the 64bit mode, since the
6263 lowering is more complicated. */
34828aad 6264 if (intel_syntax
ca61edf2 6265 && i.tm.opcode_modifier.todword
1b54b8d7 6266 && !i.types[0].bitfield.regsimd)
34828aad 6267 {
ca61edf2 6268 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6269 i.suffix = LONG_MNEM_SUFFIX;
6270 }
6271 else
6272 {
2b5d6a91 6273 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6274 register_prefix, i.op[op].regs->reg_name,
6275 i.suffix);
6276 return 0;
6277 }
252b5132 6278 }
29b0f896
AM		 6279 return 1;
6280}
252b5132 6281
29b0f896 6282static int
e3bb37b5 6283check_word_reg (void)
29b0f896
AM		 6284{
6285 int op;
6286 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6287 /* Skip non-register operands. */
6288 if (!i.types[op].bitfield.reg)
6289 continue;
29b0f896
AM		 6290 /* Reject eight bit registers, except where the template requires
6291 them. (eg. movzb) */
dc821c5f
JB		 6292 else if (i.types[op].bitfield.byte
6293 && (i.tm.operand_types[op].bitfield.reg
6294 || i.tm.operand_types[op].bitfield.acc)
6295 && (i.tm.operand_types[op].bitfield.word
6296 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6297 {
a540244d
L		 6298 as_bad (_("`%s%s' not allowed with `%s%c'"),
6299 register_prefix,
29b0f896
AM		 6300 i.op[op].regs->reg_name,
6301 i.tm.name,
6302 i.suffix);
6303 return 0;
6304 }
e4630f71 6305 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6306 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6307 && (i.types[op].bitfield.dword
6308 || i.types[op].bitfield.qword)
6309 && (i.tm.operand_types[op].bitfield.reg
6310 || i.tm.operand_types[op].bitfield.acc)
6311 && i.tm.operand_types[op].bitfield.word)
252b5132 6312 {
29b0f896
AM		 6313 /* Prohibit these changes in the 64bit mode, since the
6314 lowering is more complicated. */
6315 if (flag_code == CODE_64BIT)
252b5132 6316 {
2b5d6a91 6317 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6318 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6319 i.suffix);
6320 return 0;
252b5132 6321 }
29b0f896 6322#if REGISTER_WARNINGS
cecf1424
JB		 6323 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6324 register_prefix,
6325 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6326 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6327#endif
6328 }
6329 return 1;
6330}
252b5132 6331
29b0f896 6332static int
40fb9820 6333update_imm (unsigned int j)
29b0f896 6334{
bc0844ae 6335 i386_operand_type overlap = i.types[j];
40fb9820
L		 6336 if ((overlap.bitfield.imm8
6337 || overlap.bitfield.imm8s
6338 || overlap.bitfield.imm16
6339 || overlap.bitfield.imm32
6340 || overlap.bitfield.imm32s
6341 || overlap.bitfield.imm64)
0dfbf9d7
L		 6342 && !operand_type_equal (&overlap, &imm8)
6343 && !operand_type_equal (&overlap, &imm8s)
6344 && !operand_type_equal (&overlap, &imm16)
6345 && !operand_type_equal (&overlap, &imm32)
6346 && !operand_type_equal (&overlap, &imm32s)
6347 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6348 {
6349 if (i.suffix)
6350 {
40fb9820
L		 6351 i386_operand_type temp;
6352
0dfbf9d7 6353 operand_type_set (&temp, 0);
7ab9ffdd 6354 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6355 {
6356 temp.bitfield.imm8 = overlap.bitfield.imm8;
6357 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6358 }
6359 else if (i.suffix == WORD_MNEM_SUFFIX)
6360 temp.bitfield.imm16 = overlap.bitfield.imm16;
6361 else if (i.suffix == QWORD_MNEM_SUFFIX)
6362 {
6363 temp.bitfield.imm64 = overlap.bitfield.imm64;
6364 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6365 }
6366 else
6367 temp.bitfield.imm32 = overlap.bitfield.imm32;
6368 overlap = temp;
29b0f896 6369 }
0dfbf9d7
L		 6370 else if (operand_type_equal (&overlap, &imm16_32_32s)
6371 || operand_type_equal (&overlap, &imm16_32)
6372 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6373 {
40fb9820 6374 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6375 overlap = imm16;
40fb9820 6376 else
65da13b5 6377 overlap = imm32s;
29b0f896 6378 }
0dfbf9d7
L		 6379 if (!operand_type_equal (&overlap, &imm8)
6380 && !operand_type_equal (&overlap, &imm8s)
6381 && !operand_type_equal (&overlap, &imm16)
6382 && !operand_type_equal (&overlap, &imm32)
6383 && !operand_type_equal (&overlap, &imm32s)
6384 && !operand_type_equal (&overlap, &imm64))
29b0f896 6385 {
4eed87de
AM		 6386 as_bad (_("no instruction mnemonic suffix given; "
6387 "can't determine immediate size"));
29b0f896
AM		 6388 return 0;
6389 }
6390 }
40fb9820 6391 i.types[j] = overlap;
29b0f896 6392
40fb9820
L		 6393 return 1;
6394}
6395
6396static int
6397finalize_imm (void)
6398{
bc0844ae 6399 unsigned int j, n;
29b0f896 6400
bc0844ae
L		 6401 /* Update the first 2 immediate operands. */
6402 n = i.operands > 2 ? 2 : i.operands;
6403 if (n)
6404 {
6405 for (j = 0; j < n; j++)
6406 if (update_imm (j) == 0)
6407 return 0;
40fb9820 6408
bc0844ae
L		 6409 /* The 3rd operand can't be immediate operand. */
6410 gas_assert (operand_type_check (i.types[2], imm) == 0);
6411 }
29b0f896
AM		 6412
6413 return 1;
6414}
6415
6416static int
e3bb37b5 6417process_operands (void)
29b0f896
AM		 6418{
6419 /* Default segment register this instruction will use for memory
6420 accesses. 0 means unknown. This is only for optimizing out
6421 unnecessary segment overrides. */
6422 const seg_entry *default_seg = 0;
6423
2426c15f 6424 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6425 {
91d6fa6a
NC		 6426 unsigned int dupl = i.operands;
6427 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6428 unsigned int j;
6429
c0f3af97 6430 /* The destination must be an xmm register. */
9c2799c2 6431 gas_assert (i.reg_operands
91d6fa6a 6432 && MAX_OPERANDS > dupl
7ab9ffdd 6433 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6434
1b54b8d7
JB		 6435 if (i.tm.operand_types[0].bitfield.acc
6436 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6437 {
8cd7925b 6438 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6439 {
6440 /* Keep xmm0 for instructions with VEX prefix and 3
6441 sources. */
1b54b8d7
JB		 6442 i.tm.operand_types[0].bitfield.acc = 0;
6443 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6444 goto duplicate;
6445 }
e2ec9d29 6446 else
c0f3af97
L		 6447 {
6448 /* We remove the first xmm0 and keep the number of
6449 operands unchanged, which in fact duplicates the
6450 destination. */
6451 for (j = 1; j < i.operands; j++)
6452 {
6453 i.op[j - 1] = i.op[j];
6454 i.types[j - 1] = i.types[j];
6455 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6456 }
6457 }
6458 }
6459 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6460 {
91d6fa6a 6461 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6462 && (i.tm.opcode_modifier.vexsources
6463 == VEX3SOURCES));
c0f3af97
L		 6464
6465 /* Add the implicit xmm0 for instructions with VEX prefix
6466 and 3 sources. */
6467 for (j = i.operands; j > 0; j--)
6468 {
6469 i.op[j] = i.op[j - 1];
6470 i.types[j] = i.types[j - 1];
6471 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6472 }
6473 i.op[0].regs
6474 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6475 i.types[0] = regxmm;
c0f3af97
L		 6476 i.tm.operand_types[0] = regxmm;
6477
6478 i.operands += 2;
6479 i.reg_operands += 2;
6480 i.tm.operands += 2;
6481
91d6fa6a 6482 dupl++;
c0f3af97 6483 dest++;
91d6fa6a
NC		 6484 i.op[dupl] = i.op[dest];
6485 i.types[dupl] = i.types[dest];
6486 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6487 }
c0f3af97
L		 6488 else
6489 {
6490duplicate:
6491 i.operands++;
6492 i.reg_operands++;
6493 i.tm.operands++;
6494
91d6fa6a
NC		 6495 i.op[dupl] = i.op[dest];
6496 i.types[dupl] = i.types[dest];
6497 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6498 }
6499
6500 if (i.tm.opcode_modifier.immext)
6501 process_immext ();
6502 }
1b54b8d7
JB		 6503 else if (i.tm.operand_types[0].bitfield.acc
6504 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6505 {
6506 unsigned int j;
6507
9fcfb3d7
L		 6508 for (j = 1; j < i.operands; j++)
6509 {
6510 i.op[j - 1] = i.op[j];
6511 i.types[j - 1] = i.types[j];
6512
6513 /* We need to adjust fields in i.tm since they are used by
6514 build_modrm_byte. */
6515 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6516 }
6517
e2ec9d29
L		 6518 i.operands--;
6519 i.reg_operands--;
e2ec9d29
L		 6520 i.tm.operands--;
6521 }
920d2ddc
IT		 6522 else if (i.tm.opcode_modifier.implicitquadgroup)
6523 {
a477a8c4
JB		 6524 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6525
920d2ddc 6526 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6527 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6528 regnum = register_number (i.op[1].regs);
6529 first_reg_in_group = regnum & ~3;
6530 last_reg_in_group = first_reg_in_group + 3;
6531 if (regnum != first_reg_in_group)
6532 as_warn (_("source register `%s%s' implicitly denotes"
6533 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6534 register_prefix, i.op[1].regs->reg_name,
6535 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6536 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6537 i.tm.name);
6538 }
e2ec9d29
L		 6539 else if (i.tm.opcode_modifier.regkludge)
6540 {
6541 /* The imul $imm, %reg instruction is converted into
6542 imul $imm, %reg, %reg, and the clr %reg instruction
6543 is converted into xor %reg, %reg. */
6544
6545 unsigned int first_reg_op;
6546
6547 if (operand_type_check (i.types[0], reg))
6548 first_reg_op = 0;
6549 else
6550 first_reg_op = 1;
6551 /* Pretend we saw the extra register operand. */
9c2799c2 6552 gas_assert (i.reg_operands == 1
7ab9ffdd 6553 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6554 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6555 i.types[first_reg_op + 1] = i.types[first_reg_op];
6556 i.operands++;
6557 i.reg_operands++;
29b0f896
AM		 6558 }
6559
40fb9820 6560 if (i.tm.opcode_modifier.shortform)
29b0f896 6561 {
40fb9820
L		 6562 if (i.types[0].bitfield.sreg2
6563 || i.types[0].bitfield.sreg3)
29b0f896 6564 {
4eed87de
AM		 6565 if (i.tm.base_opcode == POP_SEG_SHORT
6566 && i.op[0].regs->reg_num == 1)
29b0f896 6567 {
a87af027 6568 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6569 return 0;
29b0f896 6570 }
4eed87de
AM		 6571 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6572 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6573 i.rex |= REX_B;
4eed87de
AM		 6574 }
6575 else
6576 {
7ab9ffdd 6577 /* The register or float register operand is in operand
85f10a01 6578 0 or 1. */
40fb9820 6579 unsigned int op;
7ab9ffdd 6580
ca0d63fe 6581 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6582 || operand_type_check (i.types[0], reg))
6583 op = 0;
6584 else
6585 op = 1;
4eed87de
AM		 6586 /* Register goes in low 3 bits of opcode. */
6587 i.tm.base_opcode |= i.op[op].regs->reg_num;
6588 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6589 i.rex |= REX_B;
40fb9820 6590 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6591 {
4eed87de
AM		 6592 /* Warn about some common errors, but press on regardless.
6593 The first case can be generated by gcc (<= 2.8.1). */
6594 if (i.operands == 2)
6595 {
6596 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6597 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6598 register_prefix, i.op[!intel_syntax].regs->reg_name,
6599 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6600 }
6601 else
6602 {
6603 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6604 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6605 register_prefix, i.op[0].regs->reg_name);
4eed87de 6606 }
29b0f896
AM		 6607 }
6608 }
6609 }
40fb9820 6610 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6611 {
6612 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6613 must be put into the modrm byte). Now, we make the modrm and
6614 index base bytes based on all the info we've collected. */
29b0f896
AM		 6615
6616 default_seg = build_modrm_byte ();
6617 }
8a2ed489 6618 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6619 {
6620 default_seg = &ds;
6621 }
40fb9820 6622 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6623 {
6624 /* For the string instructions that allow a segment override
6625 on one of their operands, the default segment is ds. */
6626 default_seg = &ds;
6627 }
6628
75178d9d
L		 6629 if (i.tm.base_opcode == 0x8d /* lea */
6630 && i.seg[0]
6631 && !quiet_warnings)
30123838 6632 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6633
6634 /* If a segment was explicitly specified, and the specified segment
6635 is not the default, use an opcode prefix to select it. If we
6636 never figured out what the default segment is, then default_seg
6637 will be zero at this point, and the specified segment prefix will
6638 always be used. */
29b0f896
AM		 6639 if ((i.seg[0]) && (i.seg[0] != default_seg))
6640 {
6641 if (!add_prefix (i.seg[0]->seg_prefix))
6642 return 0;
6643 }
6644 return 1;
6645}
6646
6647static const seg_entry *
e3bb37b5 6648build_modrm_byte (void)
29b0f896
AM		 6649{
6650 const seg_entry *default_seg = 0;
c0f3af97 6651 unsigned int source, dest;
8cd7925b 6652 int vex_3_sources;
c0f3af97 6653
8cd7925b 6654 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6655 if (vex_3_sources)
6656 {
91d6fa6a 6657 unsigned int nds, reg_slot;
4c2c6516 6658 expressionS *exp;
c0f3af97 6659
6b8d3588 6660 dest = i.operands - 1;
c0f3af97 6661 nds = dest - 1;
922d8de8 6662
a683cc34 6663 /* There are 2 kinds of instructions:
bed3d976
JB		 6664 1. 5 operands: 4 register operands or 3 register operands
6665 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6666 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 6667 ZMM register.
bed3d976 6668 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 6669 plus 1 memory operand, with VexXDS. */
922d8de8 6670 gas_assert ((i.reg_operands == 4
bed3d976
JB		 6671 || (i.reg_operands == 3 && i.mem_operands == 1))
6672 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 6673 && i.tm.opcode_modifier.vexw
6674 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 6675
48db9223
JB		 6676 /* If VexW1 is set, the first non-immediate operand is the source and
6677 the second non-immediate one is encoded in the immediate operand. */
6678 if (i.tm.opcode_modifier.vexw == VEXW1)
6679 {
6680 source = i.imm_operands;
6681 reg_slot = i.imm_operands + 1;
6682 }
6683 else
6684 {
6685 source = i.imm_operands + 1;
6686 reg_slot = i.imm_operands;
6687 }
6688
a683cc34 6689 if (i.imm_operands == 0)
bed3d976
JB		 6690 {
6691 /* When there is no immediate operand, generate an 8bit
6692 immediate operand to encode the first operand. */
6693 exp = &im_expressions[i.imm_operands++];
6694 i.op[i.operands].imms = exp;
6695 i.types[i.operands] = imm8;
6696 i.operands++;
6697
6698 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6699 exp->X_op = O_constant;
6700 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6701 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6702 }
922d8de8 6703 else
bed3d976
JB		 6704 {
6705 unsigned int imm_slot;
a683cc34 6706
2f1bada2
JB		 6707 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6708
bed3d976
JB		 6709 if (i.tm.opcode_modifier.immext)
6710 {
6711 /* When ImmExt is set, the immediate byte is the last
6712 operand. */
6713 imm_slot = i.operands - 1;
6714 source--;
6715 reg_slot--;
6716 }
6717 else
6718 {
6719 imm_slot = 0;
6720
6721 /* Turn on Imm8 so that output_imm will generate it. */
6722 i.types[imm_slot].bitfield.imm8 = 1;
6723 }
6724
6725 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6726 i.op[imm_slot].imms->X_add_number
6727 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6728 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 6729 }
a683cc34 6730
10c17abd 6731 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6732 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6733 }
6734 else
6735 source = dest = 0;
29b0f896
AM		 6736
6737 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6738 implicit registers do not count. If there are 3 register
6739 operands, it must be a instruction with VexNDS. For a
6740 instruction with VexNDD, the destination register is encoded
6741 in VEX prefix. If there are 4 register operands, it must be
6742 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6743 if (i.mem_operands == 0
6744 && ((i.reg_operands == 2
2426c15f 6745 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6746 || (i.reg_operands == 3
2426c15f 6747 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6748 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6749 {
cab737b9
L		 6750 switch (i.operands)
6751 {
6752 case 2:
6753 source = 0;
6754 break;
6755 case 3:
c81128dc
L		 6756 /* When there are 3 operands, one of them may be immediate,
6757 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6758 the first operand must be shift count register (cl) or it
6759 is an instruction with VexNDS. */
9c2799c2 6760 gas_assert (i.imm_operands == 1
7ab9ffdd 6761 || (i.imm_operands == 0
2426c15f 6762 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6763 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6764 if (operand_type_check (i.types[0], imm)
6765 || i.types[0].bitfield.shiftcount)
6766 source = 1;
6767 else
6768 source = 0;
cab737b9
L		 6769 break;
6770 case 4:
368d64cc
L		 6771 /* When there are 4 operands, the first two must be 8bit
6772 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6773 one.
6774
6775 For instructions with VexNDS, if the first operand
6776 an imm8, the source operand is the 2nd one. If the last
6777 operand is imm8, the source operand is the first one. */
9c2799c2 6778 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6779 && i.types[0].bitfield.imm8
6780 && i.types[1].bitfield.imm8)
2426c15f 6781 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6782 && i.imm_operands == 1
6783 && (i.types[0].bitfield.imm8
43234a1e
L		 6784 || i.types[i.operands - 1].bitfield.imm8
6785 || i.rounding)));
9f2670f2
L		 6786 if (i.imm_operands == 2)
6787 source = 2;
6788 else
c0f3af97
L		 6789 {
6790 if (i.types[0].bitfield.imm8)
6791 source = 1;
6792 else
6793 source = 0;
6794 }
c0f3af97
L		 6795 break;
6796 case 5:
e771e7c9 6797 if (is_evex_encoding (&i.tm))
43234a1e
L		 6798 {
6799 /* For EVEX instructions, when there are 5 operands, the
6800 first one must be immediate operand. If the second one
6801 is immediate operand, the source operand is the 3th
6802 one. If the last one is immediate operand, the source
6803 operand is the 2nd one. */
6804 gas_assert (i.imm_operands == 2
6805 && i.tm.opcode_modifier.sae
6806 && operand_type_check (i.types[0], imm));
6807 if (operand_type_check (i.types[1], imm))
6808 source = 2;
6809 else if (operand_type_check (i.types[4], imm))
6810 source = 1;
6811 else
6812 abort ();
6813 }
cab737b9
L		 6814 break;
6815 default:
6816 abort ();
6817 }
6818
c0f3af97
L		 6819 if (!vex_3_sources)
6820 {
6821 dest = source + 1;
6822
43234a1e
L		 6823 /* RC/SAE operand could be between DEST and SRC. That happens
6824 when one operand is GPR and the other one is XMM/YMM/ZMM
6825 register. */
6826 if (i.rounding && i.rounding->operand == (int) dest)
6827 dest++;
6828
2426c15f 6829 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6830 {
43234a1e 6831 /* For instructions with VexNDS, the register-only source
c5d0745b 6832 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6833 register. It is encoded in VEX prefix. We need to
6834 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6835
6836 i386_operand_type op;
6837 unsigned int vvvv;
6838
6839 /* Check register-only source operand when two source
6840 operands are swapped. */
6841 if (!i.tm.operand_types[source].bitfield.baseindex
6842 && i.tm.operand_types[dest].bitfield.baseindex)
6843 {
6844 vvvv = source;
6845 source = dest;
6846 }
6847 else
6848 vvvv = dest;
6849
6850 op = i.tm.operand_types[vvvv];
fa99fab2 6851 op.bitfield.regmem = 0;
c0f3af97 6852 if ((dest + 1) >= i.operands
dc821c5f
JB		 6853 || ((!op.bitfield.reg
6854 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6855 && !op.bitfield.regsimd
43234a1e 6856 && !operand_type_equal (&op, &regmask)))
c0f3af97 6857 abort ();
f12dc422 6858 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6859 dest++;
6860 }
6861 }
29b0f896
AM		 6862
6863 i.rm.mode = 3;
6864 /* One of the register operands will be encoded in the i.tm.reg
6865 field, the other in the combined i.tm.mode and i.tm.regmem
6866 fields. If no form of this instruction supports a memory
6867 destination operand, then we assume the source operand may
6868 sometimes be a memory operand and so we need to store the
6869 destination in the i.rm.reg field. */
40fb9820
L		 6870 if (!i.tm.operand_types[dest].bitfield.regmem
6871 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6872 {
6873 i.rm.reg = i.op[dest].regs->reg_num;
6874 i.rm.regmem = i.op[source].regs->reg_num;
6875 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6876 i.rex |= REX_R;
43234a1e
L		 6877 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6878 i.vrex |= REX_R;
29b0f896 6879 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6880 i.rex |= REX_B;
43234a1e
L		 6881 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6882 i.vrex |= REX_B;
29b0f896
AM		 6883 }
6884 else
6885 {
6886 i.rm.reg = i.op[source].regs->reg_num;
6887 i.rm.regmem = i.op[dest].regs->reg_num;
6888 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6889 i.rex |= REX_B;
43234a1e
L		 6890 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6891 i.vrex |= REX_B;
29b0f896 6892 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6893 i.rex |= REX_R;
43234a1e
L		 6894 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6895 i.vrex |= REX_R;
29b0f896 6896 }
e0c7f900 6897 if (flag_code != CODE_64BIT && (i.rex & REX_R))
c4a530c5 6898 {
e0c7f900 6899 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
c4a530c5 6900 abort ();
e0c7f900 6901 i.rex &= ~REX_R;
c4a530c5
JB		 6902 add_prefix (LOCK_PREFIX_OPCODE);
6903 }
29b0f896
AM		 6904 }
6905 else
6906 { /* If it's not 2 reg operands... */
c0f3af97
L		 6907 unsigned int mem;
6908
29b0f896
AM		 6909 if (i.mem_operands)
6910 {
6911 unsigned int fake_zero_displacement = 0;
99018f42 6912 unsigned int op;
4eed87de 6913
7ab9ffdd
L		 6914 for (op = 0; op < i.operands; op++)
6915 if (operand_type_check (i.types[op], anymem))
6916 break;
7ab9ffdd 6917 gas_assert (op < i.operands);
29b0f896 6918
6c30d220
L		 6919 if (i.tm.opcode_modifier.vecsib)
6920 {
6921 if (i.index_reg->reg_num == RegEiz
6922 || i.index_reg->reg_num == RegRiz)
6923 abort ();
6924
6925 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6926 if (!i.base_reg)
6927 {
6928 i.sib.base = NO_BASE_REGISTER;
6929 i.sib.scale = i.log2_scale_factor;
6930 i.types[op].bitfield.disp8 = 0;
6931 i.types[op].bitfield.disp16 = 0;
6932 i.types[op].bitfield.disp64 = 0;
43083a50 6933 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6934 {
6935 /* Must be 32 bit */
6936 i.types[op].bitfield.disp32 = 1;
6937 i.types[op].bitfield.disp32s = 0;
6938 }
6939 else
6940 {
6941 i.types[op].bitfield.disp32 = 0;
6942 i.types[op].bitfield.disp32s = 1;
6943 }
6944 }
6945 i.sib.index = i.index_reg->reg_num;
6946 if ((i.index_reg->reg_flags & RegRex) != 0)
6947 i.rex |= REX_X;
43234a1e
L		 6948 if ((i.index_reg->reg_flags & RegVRex) != 0)
6949 i.vrex |= REX_X;
6c30d220
L		 6950 }
6951
29b0f896
AM		 6952 default_seg = &ds;
6953
6954 if (i.base_reg == 0)
6955 {
6956 i.rm.mode = 0;
6957 if (!i.disp_operands)
9bb129e8 6958 fake_zero_displacement = 1;
29b0f896
AM		 6959 if (i.index_reg == 0)
6960 {
73053c1f
JB		 6961 i386_operand_type newdisp;
6962
6c30d220 6963 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6964 /* Operand is just <disp> */
20f0a1fc 6965 if (flag_code == CODE_64BIT)
29b0f896
AM		 6966 {
6967 /* 64bit mode overwrites the 32bit absolute
6968 addressing by RIP relative addressing and
6969 absolute addressing is encoded by one of the
6970 redundant SIB forms. */
6971 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6972 i.sib.base = NO_BASE_REGISTER;
6973 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6974 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6975 }
fc225355
L		 6976 else if ((flag_code == CODE_16BIT)
6977 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6978 {
6979 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6980 newdisp = disp16;
20f0a1fc
NC		 6981 }
6982 else
6983 {
6984 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6985 newdisp = disp32;
29b0f896 6986 }
73053c1f
JB		 6987 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6988 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6989 }
6c30d220 6990 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6991 {
6c30d220 6992 /* !i.base_reg && i.index_reg */
db51cc60
L		 6993 if (i.index_reg->reg_num == RegEiz
6994 || i.index_reg->reg_num == RegRiz)
6995 i.sib.index = NO_INDEX_REGISTER;
6996 else
6997 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6998 i.sib.base = NO_BASE_REGISTER;
6999 i.sib.scale = i.log2_scale_factor;
7000 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 7001 i.types[op].bitfield.disp8 = 0;
7002 i.types[op].bitfield.disp16 = 0;
7003 i.types[op].bitfield.disp64 = 0;
43083a50 7004 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 7005 {
7006 /* Must be 32 bit */
7007 i.types[op].bitfield.disp32 = 1;
7008 i.types[op].bitfield.disp32s = 0;
7009 }
29b0f896 7010 else
40fb9820
L		 7011 {
7012 i.types[op].bitfield.disp32 = 0;
7013 i.types[op].bitfield.disp32s = 1;
7014 }
29b0f896 7015 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7016 i.rex |= REX_X;
29b0f896
AM		 7017 }
7018 }
7019 /* RIP addressing for 64bit mode. */
9a04903e
JB		 7020 else if (i.base_reg->reg_num == RegRip ||
7021 i.base_reg->reg_num == RegEip)
29b0f896 7022 {
6c30d220 7023 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7024 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 7025 i.types[op].bitfield.disp8 = 0;
7026 i.types[op].bitfield.disp16 = 0;
7027 i.types[op].bitfield.disp32 = 0;
7028 i.types[op].bitfield.disp32s = 1;
7029 i.types[op].bitfield.disp64 = 0;
71903a11 7030 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 7031 if (! i.disp_operands)
7032 fake_zero_displacement = 1;
29b0f896 7033 }
dc821c5f 7034 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 7035 {
6c30d220 7036 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7037 switch (i.base_reg->reg_num)
7038 {
7039 case 3: /* (%bx) */
7040 if (i.index_reg == 0)
7041 i.rm.regmem = 7;
7042 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7043 i.rm.regmem = i.index_reg->reg_num - 6;
7044 break;
7045 case 5: /* (%bp) */
7046 default_seg = &ss;
7047 if (i.index_reg == 0)
7048 {
7049 i.rm.regmem = 6;
40fb9820 7050 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7051 {
7052 /* fake (%bp) into 0(%bp) */
b5014f7a 7053 i.types[op].bitfield.disp8 = 1;
252b5132 7054 fake_zero_displacement = 1;
29b0f896
AM		 7055 }
7056 }
7057 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7058 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7059 break;
7060 default: /* (%si) -> 4 or (%di) -> 5 */
7061 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7062 }
7063 i.rm.mode = mode_from_disp_size (i.types[op]);
7064 }
7065 else /* i.base_reg and 32/64 bit mode */
7066 {
7067 if (flag_code == CODE_64BIT
40fb9820
L		 7068 && operand_type_check (i.types[op], disp))
7069 {
73053c1f
JB		 7070 i.types[op].bitfield.disp16 = 0;
7071 i.types[op].bitfield.disp64 = 0;
40fb9820 7072 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7073 {
7074 i.types[op].bitfield.disp32 = 0;
7075 i.types[op].bitfield.disp32s = 1;
7076 }
40fb9820 7077 else
73053c1f
JB		 7078 {
7079 i.types[op].bitfield.disp32 = 1;
7080 i.types[op].bitfield.disp32s = 0;
7081 }
40fb9820 7082 }
20f0a1fc 7083
6c30d220
L		 7084 if (!i.tm.opcode_modifier.vecsib)
7085 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7086 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7087 i.rex |= REX_B;
29b0f896
AM		 7088 i.sib.base = i.base_reg->reg_num;
7089 /* x86-64 ignores REX prefix bit here to avoid decoder
7090 complications. */
848930b2
JB		 7091 if (!(i.base_reg->reg_flags & RegRex)
7092 && (i.base_reg->reg_num == EBP_REG_NUM
7093 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7094 default_seg = &ss;
848930b2 7095 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7096 {
848930b2 7097 fake_zero_displacement = 1;
b5014f7a 7098 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7099 }
7100 i.sib.scale = i.log2_scale_factor;
7101 if (i.index_reg == 0)
7102 {
6c30d220 7103 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7104 /* <disp>(%esp) becomes two byte modrm with no index
7105 register. We've already stored the code for esp
7106 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7107 Any base register besides %esp will not use the
7108 extra modrm byte. */
7109 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7110 }
6c30d220 7111 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7112 {
db51cc60
L		 7113 if (i.index_reg->reg_num == RegEiz
7114 || i.index_reg->reg_num == RegRiz)
7115 i.sib.index = NO_INDEX_REGISTER;
7116 else
7117 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7118 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7119 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7120 i.rex |= REX_X;
29b0f896 7121 }
67a4f2b7
AO		 7122
7123 if (i.disp_operands
7124 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7125 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7126 i.rm.mode = 0;
7127 else
a501d77e
L		 7128 {
7129 if (!fake_zero_displacement
7130 && !i.disp_operands
7131 && i.disp_encoding)
7132 {
7133 fake_zero_displacement = 1;
7134 if (i.disp_encoding == disp_encoding_8bit)
7135 i.types[op].bitfield.disp8 = 1;
7136 else
7137 i.types[op].bitfield.disp32 = 1;
7138 }
7139 i.rm.mode = mode_from_disp_size (i.types[op]);
7140 }
29b0f896 7141 }
252b5132 7142
29b0f896
AM		 7143 if (fake_zero_displacement)
7144 {
7145 /* Fakes a zero displacement assuming that i.types[op]
7146 holds the correct displacement size. */
7147 expressionS *exp;
7148
9c2799c2 7149 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7150 exp = &disp_expressions[i.disp_operands++];
7151 i.op[op].disps = exp;
7152 exp->X_op = O_constant;
7153 exp->X_add_number = 0;
7154 exp->X_add_symbol = (symbolS *) 0;
7155 exp->X_op_symbol = (symbolS *) 0;
7156 }
c0f3af97
L		 7157
7158 mem = op;
29b0f896 7159 }
c0f3af97
L		 7160 else
7161 mem = ~0;
252b5132 7162
8c43a48b 7163 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7164 {
7165 if (operand_type_check (i.types[0], imm))
7166 i.vex.register_specifier = NULL;
7167 else
7168 {
7169 /* VEX.vvvv encodes one of the sources when the first
7170 operand is not an immediate. */
1ef99a7b 7171 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7172 i.vex.register_specifier = i.op[0].regs;
7173 else
7174 i.vex.register_specifier = i.op[1].regs;
7175 }
7176
7177 /* Destination is a XMM register encoded in the ModRM.reg
7178 and VEX.R bit. */
7179 i.rm.reg = i.op[2].regs->reg_num;
7180 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7181 i.rex |= REX_R;
7182
7183 /* ModRM.rm and VEX.B encodes the other source. */
7184 if (!i.mem_operands)
7185 {
7186 i.rm.mode = 3;
7187
1ef99a7b 7188 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7189 i.rm.regmem = i.op[1].regs->reg_num;
7190 else
7191 i.rm.regmem = i.op[0].regs->reg_num;
7192
7193 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7194 i.rex |= REX_B;
7195 }
7196 }
2426c15f 7197 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7198 {
7199 i.vex.register_specifier = i.op[2].regs;
7200 if (!i.mem_operands)
7201 {
7202 i.rm.mode = 3;
7203 i.rm.regmem = i.op[1].regs->reg_num;
7204 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7205 i.rex |= REX_B;
7206 }
7207 }
29b0f896
AM		 7208 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7209 (if any) based on i.tm.extension_opcode. Again, we must be
7210 careful to make sure that segment/control/debug/test/MMX
7211 registers are coded into the i.rm.reg field. */
f88c9eb0 7212 else if (i.reg_operands)
29b0f896 7213 {
99018f42 7214 unsigned int op;
7ab9ffdd
L		 7215 unsigned int vex_reg = ~0;
7216
7217 for (op = 0; op < i.operands; op++)
dc821c5f 7218 if (i.types[op].bitfield.reg
7ab9ffdd 7219 || i.types[op].bitfield.regmmx
1b54b8d7 7220 || i.types[op].bitfield.regsimd
7e8b059b 7221 || i.types[op].bitfield.regbnd
43234a1e 7222 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7223 || i.types[op].bitfield.sreg2
7224 || i.types[op].bitfield.sreg3
7225 || i.types[op].bitfield.control
7226 || i.types[op].bitfield.debug
7227 || i.types[op].bitfield.test)
7228 break;
c0209578 7229
7ab9ffdd
L		 7230 if (vex_3_sources)
7231 op = dest;
2426c15f 7232 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7233 {
7234 /* For instructions with VexNDS, the register-only
7235 source operand is encoded in VEX prefix. */
7236 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7237
7ab9ffdd 7238 if (op > mem)
c0f3af97 7239 {
7ab9ffdd
L		 7240 vex_reg = op++;
7241 gas_assert (op < i.operands);
c0f3af97
L		 7242 }
7243 else
c0f3af97 7244 {
f12dc422
L		 7245 /* Check register-only source operand when two source
7246 operands are swapped. */
7247 if (!i.tm.operand_types[op].bitfield.baseindex
7248 && i.tm.operand_types[op + 1].bitfield.baseindex)
7249 {
7250 vex_reg = op;
7251 op += 2;
7252 gas_assert (mem == (vex_reg + 1)
7253 && op < i.operands);
7254 }
7255 else
7256 {
7257 vex_reg = op + 1;
7258 gas_assert (vex_reg < i.operands);
7259 }
c0f3af97 7260 }
7ab9ffdd 7261 }
2426c15f 7262 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7263 {
f12dc422 7264 /* For instructions with VexNDD, the register destination
7ab9ffdd 7265 is encoded in VEX prefix. */
f12dc422
L		 7266 if (i.mem_operands == 0)
7267 {
7268 /* There is no memory operand. */
7269 gas_assert ((op + 2) == i.operands);
7270 vex_reg = op + 1;
7271 }
7272 else
8d63c93e 7273 {
ed438a93
JB		 7274 /* There are only 2 non-immediate operands. */
7275 gas_assert (op < i.imm_operands + 2
7276 && i.operands == i.imm_operands + 2);
7277 vex_reg = i.imm_operands + 1;
f12dc422 7278 }
7ab9ffdd
L		 7279 }
7280 else
7281 gas_assert (op < i.operands);
99018f42 7282
7ab9ffdd
L		 7283 if (vex_reg != (unsigned int) ~0)
7284 {
f12dc422 7285 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7286
dc821c5f
JB		 7287 if ((!type->bitfield.reg
7288 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7289 && !type->bitfield.regsimd
43234a1e 7290 && !operand_type_equal (type, &regmask))
7ab9ffdd 7291 abort ();
f88c9eb0 7292
7ab9ffdd
L		 7293 i.vex.register_specifier = i.op[vex_reg].regs;
7294 }
7295
1b9f0c97
L		 7296 /* Don't set OP operand twice. */
7297 if (vex_reg != op)
7ab9ffdd 7298 {
1b9f0c97
L		 7299 /* If there is an extension opcode to put here, the
7300 register number must be put into the regmem field. */
7301 if (i.tm.extension_opcode != None)
7302 {
7303 i.rm.regmem = i.op[op].regs->reg_num;
7304 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7305 i.rex |= REX_B;
43234a1e
L		 7306 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7307 i.vrex |= REX_B;
1b9f0c97
L		 7308 }
7309 else
7310 {
7311 i.rm.reg = i.op[op].regs->reg_num;
7312 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7313 i.rex |= REX_R;
43234a1e
L		 7314 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7315 i.vrex |= REX_R;
1b9f0c97 7316 }
7ab9ffdd 7317 }
252b5132 7318
29b0f896
AM		 7319 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7320 must set it to 3 to indicate this is a register operand
7321 in the regmem field. */
7322 if (!i.mem_operands)
7323 i.rm.mode = 3;
7324 }
252b5132 7325
29b0f896 7326 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7327 if (i.tm.extension_opcode != None)
29b0f896
AM		 7328 i.rm.reg = i.tm.extension_opcode;
7329 }
7330 return default_seg;
7331}
252b5132 7332
29b0f896 7333static void
e3bb37b5 7334output_branch (void)
29b0f896
AM		 7335{
7336 char *p;
f8a5c266 7337 int size;
29b0f896
AM		 7338 int code16;
7339 int prefix;
7340 relax_substateT subtype;
7341 symbolS *sym;
7342 offsetT off;
7343
f8a5c266 7344 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7345 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7346
7347 prefix = 0;
7348 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7349 {
29b0f896
AM		 7350 prefix = 1;
7351 i.prefixes -= 1;
7352 code16 ^= CODE16;
252b5132 7353 }
29b0f896
AM		 7354 /* Pentium4 branch hints. */
7355 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7356 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7357 {
29b0f896
AM		 7358 prefix++;
7359 i.prefixes--;
7360 }
7361 if (i.prefix[REX_PREFIX] != 0)
7362 {
7363 prefix++;
7364 i.prefixes--;
2f66722d
AM		 7365 }
7366
7e8b059b
L		 7367 /* BND prefixed jump. */
7368 if (i.prefix[BND_PREFIX] != 0)
7369 {
7370 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7371 i.prefixes -= 1;
7372 }
7373
29b0f896
AM		 7374 if (i.prefixes != 0 && !intel_syntax)
7375 as_warn (_("skipping prefixes on this instruction"));
7376
7377 /* It's always a symbol; End frag & setup for relax.
7378 Make sure there is enough room in this frag for the largest
7379 instruction we may generate in md_convert_frag. This is 2
7380 bytes for the opcode and room for the prefix and largest
7381 displacement. */
7382 frag_grow (prefix + 2 + 4);
7383 /* Prefix and 1 opcode byte go in fr_fix. */
7384 p = frag_more (prefix + 1);
7385 if (i.prefix[DATA_PREFIX] != 0)
7386 *p++ = DATA_PREFIX_OPCODE;
7387 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7388 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7389 *p++ = i.prefix[SEG_PREFIX];
7390 if (i.prefix[REX_PREFIX] != 0)
7391 *p++ = i.prefix[REX_PREFIX];
7392 *p = i.tm.base_opcode;
7393
7394 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7395 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7396 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7397 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7398 else
f8a5c266 7399 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7400 subtype |= code16;
3e73aa7c 7401
29b0f896
AM		 7402 sym = i.op[0].disps->X_add_symbol;
7403 off = i.op[0].disps->X_add_number;
3e73aa7c 7404
29b0f896
AM		 7405 if (i.op[0].disps->X_op != O_constant
7406 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7407 {
29b0f896
AM		 7408 /* Handle complex expressions. */
7409 sym = make_expr_symbol (i.op[0].disps);
7410 off = 0;
7411 }
3e73aa7c 7412
29b0f896
AM		 7413 /* 1 possible extra opcode + 4 byte displacement go in var part.
7414 Pass reloc in fr_var. */
d258b828 7415 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7416}
3e73aa7c 7417
bd7ab16b
L		 7418#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7419/* Return TRUE iff PLT32 relocation should be used for branching to
7420 symbol S. */
7421
7422static bfd_boolean
7423need_plt32_p (symbolS *s)
7424{
7425 /* PLT32 relocation is ELF only. */
7426 if (!IS_ELF)
7427 return FALSE;
7428
7429 /* Since there is no need to prepare for PLT branch on x86-64, we
7430 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7431 be used as a marker for 32-bit PC-relative branches. */
7432 if (!object_64bit)
7433 return FALSE;
7434
7435 /* Weak or undefined symbol need PLT32 relocation. */
7436 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7437 return TRUE;
7438
7439 /* Non-global symbol doesn't need PLT32 relocation. */
7440 if (! S_IS_EXTERNAL (s))
7441 return FALSE;
7442
7443 /* Other global symbols need PLT32 relocation. NB: Symbol with
7444 non-default visibilities are treated as normal global symbol
7445 so that PLT32 relocation can be used as a marker for 32-bit
7446 PC-relative branches. It is useful for linker relaxation. */
7447 return TRUE;
7448}
7449#endif
7450
29b0f896 7451static void
e3bb37b5 7452output_jump (void)
29b0f896
AM		 7453{
7454 char *p;
7455 int size;
3e02c1cc 7456 fixS *fixP;
bd7ab16b 7457 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7458
40fb9820 7459 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7460 {
7461 /* This is a loop or jecxz type instruction. */
7462 size = 1;
7463 if (i.prefix[ADDR_PREFIX] != 0)
7464 {
7465 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7466 i.prefixes -= 1;
7467 }
7468 /* Pentium4 branch hints. */
7469 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7470 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7471 {
7472 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7473 i.prefixes--;
3e73aa7c
JH		 7474 }
7475 }
29b0f896
AM		 7476 else
7477 {
7478 int code16;
3e73aa7c 7479
29b0f896
AM		 7480 code16 = 0;
7481 if (flag_code == CODE_16BIT)
7482 code16 = CODE16;
3e73aa7c 7483
29b0f896
AM		 7484 if (i.prefix[DATA_PREFIX] != 0)
7485 {
7486 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7487 i.prefixes -= 1;
7488 code16 ^= CODE16;
7489 }
252b5132 7490
29b0f896
AM		 7491 size = 4;
7492 if (code16)
7493 size = 2;
7494 }
9fcc94b6 7495
29b0f896
AM		 7496 if (i.prefix[REX_PREFIX] != 0)
7497 {
7498 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7499 i.prefixes -= 1;
7500 }
252b5132 7501
7e8b059b
L		 7502 /* BND prefixed jump. */
7503 if (i.prefix[BND_PREFIX] != 0)
7504 {
7505 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7506 i.prefixes -= 1;
7507 }
7508
29b0f896
AM		 7509 if (i.prefixes != 0 && !intel_syntax)
7510 as_warn (_("skipping prefixes on this instruction"));
e0890092 7511
42164a71
L		 7512 p = frag_more (i.tm.opcode_length + size);
7513 switch (i.tm.opcode_length)
7514 {
7515 case 2:
7516 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7517 /* Fall through. */
42164a71
L		 7518 case 1:
7519 *p++ = i.tm.base_opcode;
7520 break;
7521 default:
7522 abort ();
7523 }
e0890092 7524
bd7ab16b
L		 7525#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7526 if (size == 4
7527 && jump_reloc == NO_RELOC
7528 && need_plt32_p (i.op[0].disps->X_add_symbol))
7529 jump_reloc = BFD_RELOC_X86_64_PLT32;
7530#endif
7531
7532 jump_reloc = reloc (size, 1, 1, jump_reloc);
7533
3e02c1cc 7534 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7535 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7536
7537 /* All jumps handled here are signed, but don't use a signed limit
7538 check for 32 and 16 bit jumps as we want to allow wrap around at
7539 4G and 64k respectively. */
7540 if (size == 1)
7541 fixP->fx_signed = 1;
29b0f896 7542}
e0890092 7543
29b0f896 7544static void
e3bb37b5 7545output_interseg_jump (void)
29b0f896
AM		 7546{
7547 char *p;
7548 int size;
7549 int prefix;
7550 int code16;
252b5132 7551
29b0f896
AM		 7552 code16 = 0;
7553 if (flag_code == CODE_16BIT)
7554 code16 = CODE16;
a217f122 7555
29b0f896
AM		 7556 prefix = 0;
7557 if (i.prefix[DATA_PREFIX] != 0)
7558 {
7559 prefix = 1;
7560 i.prefixes -= 1;
7561 code16 ^= CODE16;
7562 }
7563 if (i.prefix[REX_PREFIX] != 0)
7564 {
7565 prefix++;
7566 i.prefixes -= 1;
7567 }
252b5132 7568
29b0f896
AM		 7569 size = 4;
7570 if (code16)
7571 size = 2;
252b5132 7572
29b0f896
AM		 7573 if (i.prefixes != 0 && !intel_syntax)
7574 as_warn (_("skipping prefixes on this instruction"));
252b5132 7575
29b0f896
AM		 7576 /* 1 opcode; 2 segment; offset */
7577 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7578
29b0f896
AM		 7579 if (i.prefix[DATA_PREFIX] != 0)
7580 *p++ = DATA_PREFIX_OPCODE;
252b5132 7581
29b0f896
AM		 7582 if (i.prefix[REX_PREFIX] != 0)
7583 *p++ = i.prefix[REX_PREFIX];
252b5132 7584
29b0f896
AM		 7585 *p++ = i.tm.base_opcode;
7586 if (i.op[1].imms->X_op == O_constant)
7587 {
7588 offsetT n = i.op[1].imms->X_add_number;
252b5132 7589
29b0f896
AM		 7590 if (size == 2
7591 && !fits_in_unsigned_word (n)
7592 && !fits_in_signed_word (n))
7593 {
7594 as_bad (_("16-bit jump out of range"));
7595 return;
7596 }
7597 md_number_to_chars (p, n, size);
7598 }
7599 else
7600 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7601 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7602 if (i.op[0].imms->X_op != O_constant)
7603 as_bad (_("can't handle non absolute segment in `%s'"),
7604 i.tm.name);
7605 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7606}
a217f122 7607
29b0f896 7608static void
e3bb37b5 7609output_insn (void)
29b0f896 7610{
2bbd9c25
JJ		 7611 fragS *insn_start_frag;
7612 offsetT insn_start_off;
7613
29b0f896
AM		 7614 /* Tie dwarf2 debug info to the address at the start of the insn.
7615 We can't do this after the insn has been output as the current
7616 frag may have been closed off. eg. by frag_var. */
7617 dwarf2_emit_insn (0);
7618
2bbd9c25
JJ		 7619 insn_start_frag = frag_now;
7620 insn_start_off = frag_now_fix ();
7621
29b0f896 7622 /* Output jumps. */
40fb9820 7623 if (i.tm.opcode_modifier.jump)
29b0f896 7624 output_branch ();
40fb9820
L		 7625 else if (i.tm.opcode_modifier.jumpbyte
7626 || i.tm.opcode_modifier.jumpdword)
29b0f896 7627 output_jump ();
40fb9820 7628 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7629 output_interseg_jump ();
7630 else
7631 {
7632 /* Output normal instructions here. */
7633 char *p;
7634 unsigned char *q;
47465058 7635 unsigned int j;
331d2d0d 7636 unsigned int prefix;
4dffcebc 7637
e4e00185
AS		 7638 if (avoid_fence
7639 && i.tm.base_opcode == 0xfae
7640 && i.operands == 1
7641 && i.imm_operands == 1
7642 && (i.op[0].imms->X_add_number == 0xe8
7643 || i.op[0].imms->X_add_number == 0xf0
7644 || i.op[0].imms->X_add_number == 0xf8))
7645 {
7646 /* Encode lfence, mfence, and sfence as
7647 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7648 offsetT val = 0x240483f0ULL;
7649 p = frag_more (5);
7650 md_number_to_chars (p, val, 5);
7651 return;
7652 }
7653
d022bddd
IT		 7654 /* Some processors fail on LOCK prefix. This options makes
7655 assembler ignore LOCK prefix and serves as a workaround. */
7656 if (omit_lock_prefix)
7657 {
7658 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7659 return;
7660 i.prefix[LOCK_PREFIX] = 0;
7661 }
7662
43234a1e
L		 7663 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7664 don't need the explicit prefix. */
7665 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7666 {
c0f3af97 7667 switch (i.tm.opcode_length)
bc4bd9ab 7668 {
c0f3af97
L		 7669 case 3:
7670 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7671 {
c0f3af97
L		 7672 prefix = (i.tm.base_opcode >> 24) & 0xff;
7673 goto check_prefix;
7674 }
7675 break;
7676 case 2:
7677 if ((i.tm.base_opcode & 0xff0000) != 0)
7678 {
7679 prefix = (i.tm.base_opcode >> 16) & 0xff;
7680 if (i.tm.cpu_flags.bitfield.cpupadlock)
7681 {
4dffcebc 7682check_prefix:
c0f3af97 7683 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7684 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7685 != REPE_PREFIX_OPCODE))
7686 add_prefix (prefix);
7687 }
7688 else
4dffcebc
L		 7689 add_prefix (prefix);
7690 }
c0f3af97
L		 7691 break;
7692 case 1:
7693 break;
390c91cf
L		 7694 case 0:
7695 /* Check for pseudo prefixes. */
7696 as_bad_where (insn_start_frag->fr_file,
7697 insn_start_frag->fr_line,
7698 _("pseudo prefix without instruction"));
7699 return;
c0f3af97
L		 7700 default:
7701 abort ();
bc4bd9ab 7702 }
c0f3af97 7703
6d19a37a 7704#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7705 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7706 R_X86_64_GOTTPOFF relocation so that linker can safely
7707 perform IE->LE optimization. */
7708 if (x86_elf_abi == X86_64_X32_ABI
7709 && i.operands == 2
7710 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7711 && i.prefix[REX_PREFIX] == 0)
7712 add_prefix (REX_OPCODE);
6d19a37a 7713#endif
cf61b747 7714
c0f3af97
L		 7715 /* The prefix bytes. */
7716 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7717 if (*q)
7718 FRAG_APPEND_1_CHAR (*q);
0f10071e 7719 }
ae5c1c7b 7720 else
c0f3af97
L		 7721 {
7722 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7723 if (*q)
7724 switch (j)
7725 {
7726 case REX_PREFIX:
7727 /* REX byte is encoded in VEX prefix. */
7728 break;
7729 case SEG_PREFIX:
7730 case ADDR_PREFIX:
7731 FRAG_APPEND_1_CHAR (*q);
7732 break;
7733 default:
7734 /* There should be no other prefixes for instructions
7735 with VEX prefix. */
7736 abort ();
7737 }
7738
43234a1e
L		 7739 /* For EVEX instructions i.vrex should become 0 after
7740 build_evex_prefix. For VEX instructions upper 16 registers
7741 aren't available, so VREX should be 0. */
7742 if (i.vrex)
7743 abort ();
c0f3af97
L		 7744 /* Now the VEX prefix. */
7745 p = frag_more (i.vex.length);
7746 for (j = 0; j < i.vex.length; j++)
7747 p[j] = i.vex.bytes[j];
7748 }
252b5132 7749
29b0f896 7750 /* Now the opcode; be careful about word order here! */
4dffcebc 7751 if (i.tm.opcode_length == 1)
29b0f896
AM		 7752 {
7753 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7754 }
7755 else
7756 {
4dffcebc 7757 switch (i.tm.opcode_length)
331d2d0d 7758 {
43234a1e
L		 7759 case 4:
7760 p = frag_more (4);
7761 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7762 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7763 break;
4dffcebc 7764 case 3:
331d2d0d
L		 7765 p = frag_more (3);
7766 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7767 break;
7768 case 2:
7769 p = frag_more (2);
7770 break;
7771 default:
7772 abort ();
7773 break;
331d2d0d 7774 }
0f10071e 7775
29b0f896
AM		 7776 /* Put out high byte first: can't use md_number_to_chars! */
7777 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7778 *p = i.tm.base_opcode & 0xff;
7779 }
3e73aa7c 7780
29b0f896 7781 /* Now the modrm byte and sib byte (if present). */
40fb9820 7782 if (i.tm.opcode_modifier.modrm)
29b0f896 7783 {
4a3523fa
L		 7784 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7785 | i.rm.reg << 3
7786 | i.rm.mode << 6));
29b0f896
AM		 7787 /* If i.rm.regmem == ESP (4)
7788 && i.rm.mode != (Register mode)
7789 && not 16 bit
7790 ==> need second modrm byte. */
7791 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7792 && i.rm.mode != 3
dc821c5f 7793 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7794 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7795 | i.sib.index << 3
7796 | i.sib.scale << 6));
29b0f896 7797 }
3e73aa7c 7798
29b0f896 7799 if (i.disp_operands)
2bbd9c25 7800 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7801
29b0f896 7802 if (i.imm_operands)
2bbd9c25 7803 output_imm (insn_start_frag, insn_start_off);
29b0f896 7804 }
252b5132 7805
29b0f896
AM		 7806#ifdef DEBUG386
7807 if (flag_debug)
7808 {
7b81dfbb 7809 pi ("" /*line*/, &i);
29b0f896
AM		 7810 }
7811#endif /* DEBUG386 */
7812}
252b5132 7813
e205caa7
L		 7814/* Return the size of the displacement operand N. */
7815
7816static int
7817disp_size (unsigned int n)
7818{
7819 int size = 4;
43234a1e 7820
b5014f7a 7821 if (i.types[n].bitfield.disp64)
40fb9820
L		 7822 size = 8;
7823 else if (i.types[n].bitfield.disp8)
7824 size = 1;
7825 else if (i.types[n].bitfield.disp16)
7826 size = 2;
e205caa7
L		 7827 return size;
7828}
7829
7830/* Return the size of the immediate operand N. */
7831
7832static int
7833imm_size (unsigned int n)
7834{
7835 int size = 4;
40fb9820
L		 7836 if (i.types[n].bitfield.imm64)
7837 size = 8;
7838 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7839 size = 1;
7840 else if (i.types[n].bitfield.imm16)
7841 size = 2;
e205caa7
L		 7842 return size;
7843}
7844
29b0f896 7845static void
64e74474 7846output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7847{
7848 char *p;
7849 unsigned int n;
252b5132 7850
29b0f896
AM		 7851 for (n = 0; n < i.operands; n++)
7852 {
b5014f7a 7853 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7854 {
7855 if (i.op[n].disps->X_op == O_constant)
7856 {
e205caa7 7857 int size = disp_size (n);
43234a1e 7858 offsetT val = i.op[n].disps->X_add_number;
252b5132 7859
b5014f7a 7860 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7861 p = frag_more (size);
7862 md_number_to_chars (p, val, size);
7863 }
7864 else
7865 {
f86103b7 7866 enum bfd_reloc_code_real reloc_type;
e205caa7 7867 int size = disp_size (n);
40fb9820 7868 int sign = i.types[n].bitfield.disp32s;
29b0f896 7869 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7870 fixS *fixP;
29b0f896 7871
e205caa7 7872 /* We can't have 8 bit displacement here. */
9c2799c2 7873 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7874
29b0f896
AM		 7875 /* The PC relative address is computed relative
7876 to the instruction boundary, so in case immediate
7877 fields follows, we need to adjust the value. */
7878 if (pcrel && i.imm_operands)
7879 {
29b0f896 7880 unsigned int n1;
e205caa7 7881 int sz = 0;
252b5132 7882
29b0f896 7883 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7884 if (operand_type_check (i.types[n1], imm))
252b5132 7885 {
e205caa7
L		 7886 /* Only one immediate is allowed for PC
7887 relative address. */
9c2799c2 7888 gas_assert (sz == 0);
e205caa7
L		 7889 sz = imm_size (n1);
7890 i.op[n].disps->X_add_number -= sz;
252b5132 7891 }
29b0f896 7892 /* We should find the immediate. */
9c2799c2 7893 gas_assert (sz != 0);
29b0f896 7894 }
520dc8e8 7895
29b0f896 7896 p = frag_more (size);
d258b828 7897 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7898 if (GOT_symbol
2bbd9c25 7899 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7900 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7901 || reloc_type == BFD_RELOC_X86_64_32S
7902 || (reloc_type == BFD_RELOC_64
7903 && object_64bit))
d6ab8113
JB		 7904 && (i.op[n].disps->X_op == O_symbol
7905 || (i.op[n].disps->X_op == O_add
7906 && ((symbol_get_value_expression
7907 (i.op[n].disps->X_op_symbol)->X_op)
7908 == O_subtract))))
7909 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7910 {
7911 offsetT add;
7912
7913 if (insn_start_frag == frag_now)
7914 add = (p - frag_now->fr_literal) - insn_start_off;
7915 else
7916 {
7917 fragS *fr;
7918
7919 add = insn_start_frag->fr_fix - insn_start_off;
7920 for (fr = insn_start_frag->fr_next;
7921 fr && fr != frag_now; fr = fr->fr_next)
7922 add += fr->fr_fix;
7923 add += p - frag_now->fr_literal;
7924 }
7925
4fa24527 7926 if (!object_64bit)
7b81dfbb
AJ		 7927 {
7928 reloc_type = BFD_RELOC_386_GOTPC;
7929 i.op[n].imms->X_add_number += add;
7930 }
7931 else if (reloc_type == BFD_RELOC_64)
7932 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7933 else
7b81dfbb
AJ		 7934 /* Don't do the adjustment for x86-64, as there
7935 the pcrel addressing is relative to the _next_
7936 insn, and that is taken care of in other code. */
d6ab8113 7937 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7938 }
02a86693
L		 7939 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7940 size, i.op[n].disps, pcrel,
7941 reloc_type);
7942 /* Check for "call/jmp *mem", "mov mem, %reg",
7943 "test %reg, mem" and "binop mem, %reg" where binop
7944 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7945 instructions. Always generate R_386_GOT32X for
7946 "sym*GOT" operand in 32-bit mode. */
7947 if ((generate_relax_relocations
7948 || (!object_64bit
7949 && i.rm.mode == 0
7950 && i.rm.regmem == 5))
7951 && (i.rm.mode == 2
7952 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7953 && ((i.operands == 1
7954 && i.tm.base_opcode == 0xff
7955 && (i.rm.reg == 2 || i.rm.reg == 4))
7956 || (i.operands == 2
7957 && (i.tm.base_opcode == 0x8b
7958 || i.tm.base_opcode == 0x85
7959 || (i.tm.base_opcode & 0xc7) == 0x03))))
7960 {
7961 if (object_64bit)
7962 {
7963 fixP->fx_tcbit = i.rex != 0;
7964 if (i.base_reg
7965 && (i.base_reg->reg_num == RegRip
7966 || i.base_reg->reg_num == RegEip))
7967 fixP->fx_tcbit2 = 1;
7968 }
7969 else
7970 fixP->fx_tcbit2 = 1;
7971 }
29b0f896
AM		 7972 }
7973 }
7974 }
7975}
252b5132 7976
29b0f896 7977static void
64e74474 7978output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7979{
7980 char *p;
7981 unsigned int n;
252b5132 7982
29b0f896
AM		 7983 for (n = 0; n < i.operands; n++)
7984 {
43234a1e
L		 7985 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7986 if (i.rounding && (int) n == i.rounding->operand)
7987 continue;
7988
40fb9820 7989 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7990 {
7991 if (i.op[n].imms->X_op == O_constant)
7992 {
e205caa7 7993 int size = imm_size (n);
29b0f896 7994 offsetT val;
b4cac588 7995
29b0f896
AM		 7996 val = offset_in_range (i.op[n].imms->X_add_number,
7997 size);
7998 p = frag_more (size);
7999 md_number_to_chars (p, val, size);
8000 }
8001 else
8002 {
8003 /* Not absolute_section.
8004 Need a 32-bit fixup (don't support 8bit
8005 non-absolute imms). Try to support other
8006 sizes ... */
f86103b7 8007 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 8008 int size = imm_size (n);
8009 int sign;
29b0f896 8010
40fb9820 8011 if (i.types[n].bitfield.imm32s
a7d61044 8012 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 8013 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 8014 sign = 1;
e205caa7
L		 8015 else
8016 sign = 0;
520dc8e8 8017
29b0f896 8018 p = frag_more (size);
d258b828 8019 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 8020
2bbd9c25
JJ		 8021 /* This is tough to explain. We end up with this one if we
8022 * have operands that look like
8023 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8024 * obtain the absolute address of the GOT, and it is strongly
8025 * preferable from a performance point of view to avoid using
8026 * a runtime relocation for this. The actual sequence of
8027 * instructions often look something like:
8028 *
8029 * call .L66
8030 * .L66:
8031 * popl %ebx
8032 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8033 *
8034 * The call and pop essentially return the absolute address
8035 * of the label .L66 and store it in %ebx. The linker itself
8036 * will ultimately change the first operand of the addl so
8037 * that %ebx points to the GOT, but to keep things simple, the
8038 * .o file must have this operand set so that it generates not
8039 * the absolute address of .L66, but the absolute address of
8040 * itself. This allows the linker itself simply treat a GOTPC
8041 * relocation as asking for a pcrel offset to the GOT to be
8042 * added in, and the addend of the relocation is stored in the
8043 * operand field for the instruction itself.
8044 *
8045 * Our job here is to fix the operand so that it would add
8046 * the correct offset so that %ebx would point to itself. The
8047 * thing that is tricky is that .-.L66 will point to the
8048 * beginning of the instruction, so we need to further modify
8049 * the operand so that it will point to itself. There are
8050 * other cases where you have something like:
8051 *
8052 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8053 *
8054 * and here no correction would be required. Internally in
8055 * the assembler we treat operands of this form as not being
8056 * pcrel since the '.' is explicitly mentioned, and I wonder
8057 * whether it would simplify matters to do it this way. Who
8058 * knows. In earlier versions of the PIC patches, the
8059 * pcrel_adjust field was used to store the correction, but
8060 * since the expression is not pcrel, I felt it would be
8061 * confusing to do it this way. */
8062
d6ab8113 8063 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8064 || reloc_type == BFD_RELOC_X86_64_32S
8065 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8066 && GOT_symbol
8067 && GOT_symbol == i.op[n].imms->X_add_symbol
8068 && (i.op[n].imms->X_op == O_symbol
8069 || (i.op[n].imms->X_op == O_add
8070 && ((symbol_get_value_expression
8071 (i.op[n].imms->X_op_symbol)->X_op)
8072 == O_subtract))))
8073 {
2bbd9c25
JJ		 8074 offsetT add;
8075
8076 if (insn_start_frag == frag_now)
8077 add = (p - frag_now->fr_literal) - insn_start_off;
8078 else
8079 {
8080 fragS *fr;
8081
8082 add = insn_start_frag->fr_fix - insn_start_off;
8083 for (fr = insn_start_frag->fr_next;
8084 fr && fr != frag_now; fr = fr->fr_next)
8085 add += fr->fr_fix;
8086 add += p - frag_now->fr_literal;
8087 }
8088
4fa24527 8089 if (!object_64bit)
d6ab8113 8090 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8091 else if (size == 4)
d6ab8113 8092 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8093 else if (size == 8)
8094 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8095 i.op[n].imms->X_add_number += add;
29b0f896 8096 }
29b0f896
AM		 8097 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8098 i.op[n].imms, 0, reloc_type);
8099 }
8100 }
8101 }
252b5132
RH		 8102}
8103\f
d182319b
JB		 8104/* x86_cons_fix_new is called via the expression parsing code when a
8105 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8106static int cons_sign = -1;
8107
8108void
e3bb37b5 8109x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8110 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8111{
d258b828 8112 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8113
8114#ifdef TE_PE
8115 if (exp->X_op == O_secrel)
8116 {
8117 exp->X_op = O_symbol;
8118 r = BFD_RELOC_32_SECREL;
8119 }
8120#endif
8121
8122 fix_new_exp (frag, off, len, exp, 0, r);
8123}
8124
357d1bd8
L		 8125/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8126 purpose of the `.dc.a' internal pseudo-op. */
8127
8128int
8129x86_address_bytes (void)
8130{
8131 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8132 return 4;
8133 return stdoutput->arch_info->bits_per_address / 8;
8134}
8135
d382c579
TG		 8136#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8137 || defined (LEX_AT)
d258b828 8138# define lex_got(reloc, adjust, types) NULL
718ddfc0 8139#else
f3c180ae
AM		 8140/* Parse operands of the form
8141 <symbol>@GOTOFF+<nnn>
8142 and similar .plt or .got references.
8143
8144 If we find one, set up the correct relocation in RELOC and copy the
8145 input string, minus the `@GOTOFF' into a malloc'd buffer for
8146 parsing by the calling routine. Return this buffer, and if ADJUST
8147 is non-null set it to the length of the string we removed from the
8148 input line. Otherwise return NULL. */
8149static char *
91d6fa6a 8150lex_got (enum bfd_reloc_code_real *rel,
64e74474 8151 int *adjust,
d258b828 8152 i386_operand_type *types)
f3c180ae 8153{
7b81dfbb
AJ		 8154 /* Some of the relocations depend on the size of what field is to
8155 be relocated. But in our callers i386_immediate and i386_displacement
8156 we don't yet know the operand size (this will be set by insn
8157 matching). Hence we record the word32 relocation here,
8158 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8159 static const struct {
8160 const char *str;
cff8d58a 8161 int len;
4fa24527 8162 const enum bfd_reloc_code_real rel[2];
40fb9820 8163 const i386_operand_type types64;
f3c180ae 8164 } gotrel[] = {
8ce3d284 8165#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8166 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8167 BFD_RELOC_SIZE32 },
8168 OPERAND_TYPE_IMM32_64 },
8ce3d284 8169#endif
cff8d58a
L		 8170 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8171 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8172 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8173 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8174 BFD_RELOC_X86_64_PLT32 },
40fb9820 8175 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8176 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8177 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8178 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8179 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8180 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8181 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8182 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8183 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8184 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8185 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8186 BFD_RELOC_X86_64_TLSGD },
40fb9820 8187 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8188 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8189 _dummy_first_bfd_reloc_code_real },
40fb9820 8190 OPERAND_TYPE_NONE },
cff8d58a
L		 8191 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8192 BFD_RELOC_X86_64_TLSLD },
40fb9820 8193 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8194 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8195 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8196 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8197 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8198 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8199 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8200 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8201 _dummy_first_bfd_reloc_code_real },
40fb9820 8202 OPERAND_TYPE_NONE },
cff8d58a
L		 8203 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8204 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8205 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8206 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8207 _dummy_first_bfd_reloc_code_real },
40fb9820 8208 OPERAND_TYPE_NONE },
cff8d58a
L		 8209 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8210 _dummy_first_bfd_reloc_code_real },
40fb9820 8211 OPERAND_TYPE_NONE },
cff8d58a
L		 8212 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8213 BFD_RELOC_X86_64_GOT32 },
40fb9820 8214 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8215 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8216 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8217 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8218 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8219 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8220 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8221 };
8222 char *cp;
8223 unsigned int j;
8224
d382c579 8225#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8226 if (!IS_ELF)
8227 return NULL;
d382c579 8228#endif
718ddfc0 8229
f3c180ae 8230 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8231 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8232 return NULL;
8233
47465058 8234 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8235 {
cff8d58a 8236 int len = gotrel[j].len;
28f81592 8237 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8238 {
4fa24527 8239 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8240 {
28f81592
AM		 8241 int first, second;
8242 char *tmpbuf, *past_reloc;
f3c180ae 8243
91d6fa6a 8244 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8245
3956db08
JB		 8246 if (types)
8247 {
8248 if (flag_code != CODE_64BIT)
40fb9820
L		 8249 {
8250 types->bitfield.imm32 = 1;
8251 types->bitfield.disp32 = 1;
8252 }
3956db08
JB		 8253 else
8254 *types = gotrel[j].types64;
8255 }
8256
8fd4256d 8257 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8258 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8259
28f81592 8260 /* The length of the first part of our input line. */
f3c180ae 8261 first = cp - input_line_pointer;
28f81592
AM		 8262
8263 /* The second part goes from after the reloc token until
67c11a9b 8264 (and including) an end_of_line char or comma. */
28f81592 8265 past_reloc = cp + 1 + len;
67c11a9b
AM		 8266 cp = past_reloc;
8267 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8268 ++cp;
8269 second = cp + 1 - past_reloc;
28f81592
AM		 8270
8271 /* Allocate and copy string. The trailing NUL shouldn't
8272 be necessary, but be safe. */
add39d23 8273 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8274 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8275 if (second != 0 && *past_reloc != ' ')
8276 /* Replace the relocation token with ' ', so that
8277 errors like foo@GOTOFF1 will be detected. */
8278 tmpbuf[first++] = ' ';
af89796a
L		 8279 else
8280 /* Increment length by 1 if the relocation token is
8281 removed. */
8282 len++;
8283 if (adjust)
8284 *adjust = len;
0787a12d
AM		 8285 memcpy (tmpbuf + first, past_reloc, second);
8286 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8287 return tmpbuf;
8288 }
8289
4fa24527
JB		 8290 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8291 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8292 return NULL;
8293 }
8294 }
8295
8296 /* Might be a symbol version string. Don't as_bad here. */
8297 return NULL;
8298}
4e4f7c87 8299#endif
f3c180ae 8300
a988325c
NC		 8301#ifdef TE_PE
8302#ifdef lex_got
8303#undef lex_got
8304#endif
8305/* Parse operands of the form
8306 <symbol>@SECREL32+<nnn>
8307
8308 If we find one, set up the correct relocation in RELOC and copy the
8309 input string, minus the `@SECREL32' into a malloc'd buffer for
8310 parsing by the calling routine. Return this buffer, and if ADJUST
8311 is non-null set it to the length of the string we removed from the
34bca508
L		 8312 input line. Otherwise return NULL.
8313
a988325c
NC		 8314 This function is copied from the ELF version above adjusted for PE targets. */
8315
8316static char *
8317lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8318 int *adjust ATTRIBUTE_UNUSED,
d258b828 8319 i386_operand_type *types)
a988325c
NC		 8320{
8321 static const struct
8322 {
8323 const char *str;
8324 int len;
8325 const enum bfd_reloc_code_real rel[2];
8326 const i386_operand_type types64;
8327 }
8328 gotrel[] =
8329 {
8330 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8331 BFD_RELOC_32_SECREL },
8332 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8333 };
8334
8335 char *cp;
8336 unsigned j;
8337
8338 for (cp = input_line_pointer; *cp != '@'; cp++)
8339 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8340 return NULL;
8341
8342 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8343 {
8344 int len = gotrel[j].len;
8345
8346 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8347 {
8348 if (gotrel[j].rel[object_64bit] != 0)
8349 {
8350 int first, second;
8351 char *tmpbuf, *past_reloc;
8352
8353 *rel = gotrel[j].rel[object_64bit];
8354 if (adjust)
8355 *adjust = len;
8356
8357 if (types)
8358 {
8359 if (flag_code != CODE_64BIT)
8360 {
8361 types->bitfield.imm32 = 1;
8362 types->bitfield.disp32 = 1;
8363 }
8364 else
8365 *types = gotrel[j].types64;
8366 }
8367
8368 /* The length of the first part of our input line. */
8369 first = cp - input_line_pointer;
8370
8371 /* The second part goes from after the reloc token until
8372 (and including) an end_of_line char or comma. */
8373 past_reloc = cp + 1 + len;
8374 cp = past_reloc;
8375 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8376 ++cp;
8377 second = cp + 1 - past_reloc;
8378
8379 /* Allocate and copy string. The trailing NUL shouldn't
8380 be necessary, but be safe. */
add39d23 8381 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8382 memcpy (tmpbuf, input_line_pointer, first);
8383 if (second != 0 && *past_reloc != ' ')
8384 /* Replace the relocation token with ' ', so that
8385 errors like foo@SECLREL321 will be detected. */
8386 tmpbuf[first++] = ' ';
8387 memcpy (tmpbuf + first, past_reloc, second);
8388 tmpbuf[first + second] = '\0';
8389 return tmpbuf;
8390 }
8391
8392 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8393 gotrel[j].str, 1 << (5 + object_64bit));
8394 return NULL;
8395 }
8396 }
8397
8398 /* Might be a symbol version string. Don't as_bad here. */
8399 return NULL;
8400}
8401
8402#endif /* TE_PE */
8403
62ebcb5c 8404bfd_reloc_code_real_type
e3bb37b5 8405x86_cons (expressionS *exp, int size)
f3c180ae 8406{
62ebcb5c
AM		 8407 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8408
ee86248c
JB		 8409 intel_syntax = -intel_syntax;
8410
3c7b9c2c 8411 exp->X_md = 0;
4fa24527 8412 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8413 {
8414 /* Handle @GOTOFF and the like in an expression. */
8415 char *save;
8416 char *gotfree_input_line;
4a57f2cf 8417 int adjust = 0;
f3c180ae
AM		 8418
8419 save = input_line_pointer;
d258b828 8420 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8421 if (gotfree_input_line)
8422 input_line_pointer = gotfree_input_line;
8423
8424 expression (exp);
8425
8426 if (gotfree_input_line)
8427 {
8428 /* expression () has merrily parsed up to the end of line,
8429 or a comma - in the wrong buffer. Transfer how far
8430 input_line_pointer has moved to the right buffer. */
8431 input_line_pointer = (save
8432 + (input_line_pointer - gotfree_input_line)
8433 + adjust);
8434 free (gotfree_input_line);
3992d3b7
AM		 8435 if (exp->X_op == O_constant
8436 || exp->X_op == O_absent
8437 || exp->X_op == O_illegal
0398aac5 8438 || exp->X_op == O_register
3992d3b7
AM		 8439 || exp->X_op == O_big)
8440 {
8441 char c = *input_line_pointer;
8442 *input_line_pointer = 0;
8443 as_bad (_("missing or invalid expression `%s'"), save);
8444 *input_line_pointer = c;
8445 }
f3c180ae
AM		 8446 }
8447 }
8448 else
8449 expression (exp);
ee86248c
JB		 8450
8451 intel_syntax = -intel_syntax;
8452
8453 if (intel_syntax)
8454 i386_intel_simplify (exp);
62ebcb5c
AM		 8455
8456 return got_reloc;
f3c180ae 8457}
f3c180ae 8458
9f32dd5b
L		 8459static void
8460signed_cons (int size)
6482c264 8461{
d182319b
JB		 8462 if (flag_code == CODE_64BIT)
8463 cons_sign = 1;
8464 cons (size);
8465 cons_sign = -1;
6482c264
NC		 8466}
8467
d182319b 8468#ifdef TE_PE
6482c264 8469static void
7016a5d5 8470pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8471{
8472 expressionS exp;
8473
8474 do
8475 {
8476 expression (&exp);
8477 if (exp.X_op == O_symbol)
8478 exp.X_op = O_secrel;
8479
8480 emit_expr (&exp, 4);
8481 }
8482 while (*input_line_pointer++ == ',');
8483
8484 input_line_pointer--;
8485 demand_empty_rest_of_line ();
8486}
6482c264
NC		 8487#endif
8488
43234a1e
L		 8489/* Handle Vector operations. */
8490
8491static char *
8492check_VecOperations (char *op_string, char *op_end)
8493{
8494 const reg_entry *mask;
8495 const char *saved;
8496 char *end_op;
8497
8498 while (*op_string
8499 && (op_end == NULL || op_string < op_end))
8500 {
8501 saved = op_string;
8502 if (*op_string == '{')
8503 {
8504 op_string++;
8505
8506 /* Check broadcasts. */
8507 if (strncmp (op_string, "1to", 3) == 0)
8508 {
8509 int bcst_type;
8510
8511 if (i.broadcast)
8512 goto duplicated_vec_op;
8513
8514 op_string += 3;
8515 if (*op_string == '8')
8e6e0792 8516 bcst_type = 8;
b28d1bda 8517 else if (*op_string == '4')
8e6e0792 8518 bcst_type = 4;
b28d1bda 8519 else if (*op_string == '2')
8e6e0792 8520 bcst_type = 2;
43234a1e
L		 8521 else if (*op_string == '1'
8522 && *(op_string+1) == '6')
8523 {
8e6e0792 8524 bcst_type = 16;
43234a1e
L		 8525 op_string++;
8526 }
8527 else
8528 {
8529 as_bad (_("Unsupported broadcast: `%s'"), saved);
8530 return NULL;
8531 }
8532 op_string++;
8533
8534 broadcast_op.type = bcst_type;
8535 broadcast_op.operand = this_operand;
8536 i.broadcast = &broadcast_op;
8537 }
8538 /* Check masking operation. */
8539 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8540 {
8541 /* k0 can't be used for write mask. */
6d2cd6b2 8542 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8543 {
6d2cd6b2
JB		 8544 as_bad (_("`%s%s' can't be used for write mask"),
8545 register_prefix, mask->reg_name);
43234a1e
L		 8546 return NULL;
8547 }
8548
8549 if (!i.mask)
8550 {
8551 mask_op.mask = mask;
8552 mask_op.zeroing = 0;
8553 mask_op.operand = this_operand;
8554 i.mask = &mask_op;
8555 }
8556 else
8557 {
8558 if (i.mask->mask)
8559 goto duplicated_vec_op;
8560
8561 i.mask->mask = mask;
8562
8563 /* Only "{z}" is allowed here. No need to check
8564 zeroing mask explicitly. */
8565 if (i.mask->operand != this_operand)
8566 {
8567 as_bad (_("invalid write mask `%s'"), saved);
8568 return NULL;
8569 }
8570 }
8571
8572 op_string = end_op;
8573 }
8574 /* Check zeroing-flag for masking operation. */
8575 else if (*op_string == 'z')
8576 {
8577 if (!i.mask)
8578 {
8579 mask_op.mask = NULL;
8580 mask_op.zeroing = 1;
8581 mask_op.operand = this_operand;
8582 i.mask = &mask_op;
8583 }
8584 else
8585 {
8586 if (i.mask->zeroing)
8587 {
8588 duplicated_vec_op:
8589 as_bad (_("duplicated `%s'"), saved);
8590 return NULL;
8591 }
8592
8593 i.mask->zeroing = 1;
8594
8595 /* Only "{%k}" is allowed here. No need to check mask
8596 register explicitly. */
8597 if (i.mask->operand != this_operand)
8598 {
8599 as_bad (_("invalid zeroing-masking `%s'"),
8600 saved);
8601 return NULL;
8602 }
8603 }
8604
8605 op_string++;
8606 }
8607 else
8608 goto unknown_vec_op;
8609
8610 if (*op_string != '}')
8611 {
8612 as_bad (_("missing `}' in `%s'"), saved);
8613 return NULL;
8614 }
8615 op_string++;
0ba3a731
L		 8616
8617 /* Strip whitespace since the addition of pseudo prefixes
8618 changed how the scrubber treats '{'. */
8619 if (is_space_char (*op_string))
8620 ++op_string;
8621
43234a1e
L		 8622 continue;
8623 }
8624 unknown_vec_op:
8625 /* We don't know this one. */
8626 as_bad (_("unknown vector operation: `%s'"), saved);
8627 return NULL;
8628 }
8629
6d2cd6b2
JB		 8630 if (i.mask && i.mask->zeroing && !i.mask->mask)
8631 {
8632 as_bad (_("zeroing-masking only allowed with write mask"));
8633 return NULL;
8634 }
8635
43234a1e
L		 8636 return op_string;
8637}
8638
252b5132 8639static int
70e41ade 8640i386_immediate (char *imm_start)
252b5132
RH		 8641{
8642 char *save_input_line_pointer;
f3c180ae 8643 char *gotfree_input_line;
252b5132 8644 segT exp_seg = 0;
47926f60 8645 expressionS *exp;
40fb9820
L		 8646 i386_operand_type types;
8647
0dfbf9d7 8648 operand_type_set (&types, ~0);
252b5132
RH		 8649
8650 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8651 {
31b2323c
L		 8652 as_bad (_("at most %d immediate operands are allowed"),
8653 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8654 return 0;
8655 }
8656
8657 exp = &im_expressions[i.imm_operands++];
520dc8e8 8658 i.op[this_operand].imms = exp;
252b5132
RH		 8659
8660 if (is_space_char (*imm_start))
8661 ++imm_start;
8662
8663 save_input_line_pointer = input_line_pointer;
8664 input_line_pointer = imm_start;
8665
d258b828 8666 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8667 if (gotfree_input_line)
8668 input_line_pointer = gotfree_input_line;
252b5132
RH		 8669
8670 exp_seg = expression (exp);
8671
83183c0c 8672 SKIP_WHITESPACE ();
43234a1e
L		 8673
8674 /* Handle vector operations. */
8675 if (*input_line_pointer == '{')
8676 {
8677 input_line_pointer = check_VecOperations (input_line_pointer,
8678 NULL);
8679 if (input_line_pointer == NULL)
8680 return 0;
8681 }
8682
252b5132 8683 if (*input_line_pointer)
f3c180ae 8684 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8685
8686 input_line_pointer = save_input_line_pointer;
f3c180ae 8687 if (gotfree_input_line)
ee86248c
JB		 8688 {
8689 free (gotfree_input_line);
8690
8691 if (exp->X_op == O_constant || exp->X_op == O_register)
8692 exp->X_op = O_illegal;
8693 }
8694
8695 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8696}
252b5132 8697
ee86248c
JB		 8698static int
8699i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8700 i386_operand_type types, const char *imm_start)
8701{
8702 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8703 {
313c53d1
L		 8704 if (imm_start)
8705 as_bad (_("missing or invalid immediate expression `%s'"),
8706 imm_start);
3992d3b7 8707 return 0;
252b5132 8708 }
3e73aa7c 8709 else if (exp->X_op == O_constant)
252b5132 8710 {
47926f60 8711 /* Size it properly later. */
40fb9820 8712 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8713 /* If not 64bit, sign extend val. */
8714 if (flag_code != CODE_64BIT
4eed87de
AM		 8715 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8716 exp->X_add_number
8717 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8718 }
4c63da97 8719#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8720 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8721 && exp_seg != absolute_section
47926f60 8722 && exp_seg != text_section
24eab124
AM		 8723 && exp_seg != data_section
8724 && exp_seg != bss_section
8725 && exp_seg != undefined_section
f86103b7 8726 && !bfd_is_com_section (exp_seg))
252b5132 8727 {
d0b47220 8728 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8729 return 0;
8730 }
8731#endif
a841bdf5 8732 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8733 {
313c53d1
L		 8734 if (imm_start)
8735 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8736 return 0;
8737 }
252b5132
RH		 8738 else
8739 {
8740 /* This is an address. The size of the address will be
24eab124 8741 determined later, depending on destination register,
3e73aa7c 8742 suffix, or the default for the section. */
40fb9820
L		 8743 i.types[this_operand].bitfield.imm8 = 1;
8744 i.types[this_operand].bitfield.imm16 = 1;
8745 i.types[this_operand].bitfield.imm32 = 1;
8746 i.types[this_operand].bitfield.imm32s = 1;
8747 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8748 i.types[this_operand] = operand_type_and (i.types[this_operand],
8749 types);
252b5132
RH		 8750 }
8751
8752 return 1;
8753}
8754
551c1ca1 8755static char *
e3bb37b5 8756i386_scale (char *scale)
252b5132 8757{
551c1ca1
AM		 8758 offsetT val;
8759 char *save = input_line_pointer;
252b5132 8760
551c1ca1
AM		 8761 input_line_pointer = scale;
8762 val = get_absolute_expression ();
8763
8764 switch (val)
252b5132 8765 {
551c1ca1 8766 case 1:
252b5132
RH		 8767 i.log2_scale_factor = 0;
8768 break;
551c1ca1 8769 case 2:
252b5132
RH		 8770 i.log2_scale_factor = 1;
8771 break;
551c1ca1 8772 case 4:
252b5132
RH		 8773 i.log2_scale_factor = 2;
8774 break;
551c1ca1 8775 case 8:
252b5132
RH		 8776 i.log2_scale_factor = 3;
8777 break;
8778 default:
a724f0f4
JB		 8779 {
8780 char sep = *input_line_pointer;
8781
8782 *input_line_pointer = '\0';
8783 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8784 scale);
8785 *input_line_pointer = sep;
8786 input_line_pointer = save;
8787 return NULL;
8788 }
252b5132 8789 }
29b0f896 8790 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8791 {
8792 as_warn (_("scale factor of %d without an index register"),
24eab124 8793 1 << i.log2_scale_factor);
252b5132 8794 i.log2_scale_factor = 0;
252b5132 8795 }
551c1ca1
AM		 8796 scale = input_line_pointer;
8797 input_line_pointer = save;
8798 return scale;
252b5132
RH		 8799}
8800
252b5132 8801static int
e3bb37b5 8802i386_displacement (char *disp_start, char *disp_end)
252b5132 8803{
29b0f896 8804 expressionS *exp;
252b5132
RH		 8805 segT exp_seg = 0;
8806 char *save_input_line_pointer;
f3c180ae 8807 char *gotfree_input_line;
40fb9820
L		 8808 int override;
8809 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8810 int ret;
252b5132 8811
31b2323c
L		 8812 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8813 {
8814 as_bad (_("at most %d displacement operands are allowed"),
8815 MAX_MEMORY_OPERANDS);
8816 return 0;
8817 }
8818
0dfbf9d7 8819 operand_type_set (&bigdisp, 0);
40fb9820
L		 8820 if ((i.types[this_operand].bitfield.jumpabsolute)
8821 || (!current_templates->start->opcode_modifier.jump
8822 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8823 {
40fb9820 8824 bigdisp.bitfield.disp32 = 1;
e05278af 8825 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8826 if (flag_code == CODE_64BIT)
8827 {
8828 if (!override)
8829 {
8830 bigdisp.bitfield.disp32s = 1;
8831 bigdisp.bitfield.disp64 = 1;
8832 }
8833 }
8834 else if ((flag_code == CODE_16BIT) ^ override)
8835 {
8836 bigdisp.bitfield.disp32 = 0;
8837 bigdisp.bitfield.disp16 = 1;
8838 }
e05278af
JB		 8839 }
8840 else
8841 {
8842 /* For PC-relative branches, the width of the displacement
8843 is dependent upon data size, not address size. */
e05278af 8844 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8845 if (flag_code == CODE_64BIT)
8846 {
8847 if (override || i.suffix == WORD_MNEM_SUFFIX)
8848 bigdisp.bitfield.disp16 = 1;
8849 else
8850 {
8851 bigdisp.bitfield.disp32 = 1;
8852 bigdisp.bitfield.disp32s = 1;
8853 }
8854 }
8855 else
e05278af
JB		 8856 {
8857 if (!override)
8858 override = (i.suffix == (flag_code != CODE_16BIT
8859 ? WORD_MNEM_SUFFIX
8860 : LONG_MNEM_SUFFIX));
40fb9820
L		 8861 bigdisp.bitfield.disp32 = 1;
8862 if ((flag_code == CODE_16BIT) ^ override)
8863 {
8864 bigdisp.bitfield.disp32 = 0;
8865 bigdisp.bitfield.disp16 = 1;
8866 }
e05278af 8867 }
e05278af 8868 }
c6fb90c8
L		 8869 i.types[this_operand] = operand_type_or (i.types[this_operand],
8870 bigdisp);
252b5132
RH		 8871
8872 exp = &disp_expressions[i.disp_operands];
520dc8e8 8873 i.op[this_operand].disps = exp;
252b5132
RH		 8874 i.disp_operands++;
8875 save_input_line_pointer = input_line_pointer;
8876 input_line_pointer = disp_start;
8877 END_STRING_AND_SAVE (disp_end);
8878
8879#ifndef GCC_ASM_O_HACK
8880#define GCC_ASM_O_HACK 0
8881#endif
8882#if GCC_ASM_O_HACK
8883 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8884 if (i.types[this_operand].bitfield.baseIndex
24eab124 8885 && displacement_string_end[-1] == '+')
252b5132
RH		 8886 {
8887 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8888 constraint within gcc asm statements.
8889 For instance:
8890
8891 #define _set_tssldt_desc(n,addr,limit,type) \
8892 __asm__ __volatile__ ( \
8893 "movw %w2,%0\n\t" \
8894 "movw %w1,2+%0\n\t" \
8895 "rorl $16,%1\n\t" \
8896 "movb %b1,4+%0\n\t" \
8897 "movb %4,5+%0\n\t" \
8898 "movb $0,6+%0\n\t" \
8899 "movb %h1,7+%0\n\t" \
8900 "rorl $16,%1" \
8901 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8902
8903 This works great except that the output assembler ends
8904 up looking a bit weird if it turns out that there is
8905 no offset. You end up producing code that looks like:
8906
8907 #APP
8908 movw $235,(%eax)
8909 movw %dx,2+(%eax)
8910 rorl $16,%edx
8911 movb %dl,4+(%eax)
8912 movb $137,5+(%eax)
8913 movb $0,6+(%eax)
8914 movb %dh,7+(%eax)
8915 rorl $16,%edx
8916 #NO_APP
8917
47926f60 8918 So here we provide the missing zero. */
24eab124
AM		 8919
8920 *displacement_string_end = '0';
252b5132
RH		 8921 }
8922#endif
d258b828 8923 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8924 if (gotfree_input_line)
8925 input_line_pointer = gotfree_input_line;
252b5132 8926
24eab124 8927 exp_seg = expression (exp);
252b5132 8928
636c26b0
AM		 8929 SKIP_WHITESPACE ();
8930 if (*input_line_pointer)
8931 as_bad (_("junk `%s' after expression"), input_line_pointer);
8932#if GCC_ASM_O_HACK
8933 RESTORE_END_STRING (disp_end + 1);
8934#endif
636c26b0 8935 input_line_pointer = save_input_line_pointer;
636c26b0 8936 if (gotfree_input_line)
ee86248c
JB		 8937 {
8938 free (gotfree_input_line);
8939
8940 if (exp->X_op == O_constant || exp->X_op == O_register)
8941 exp->X_op = O_illegal;
8942 }
8943
8944 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8945
8946 RESTORE_END_STRING (disp_end);
8947
8948 return ret;
8949}
8950
8951static int
8952i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8953 i386_operand_type types, const char *disp_start)
8954{
8955 i386_operand_type bigdisp;
8956 int ret = 1;
636c26b0 8957
24eab124
AM		 8958 /* We do this to make sure that the section symbol is in
8959 the symbol table. We will ultimately change the relocation
47926f60 8960 to be relative to the beginning of the section. */
1ae12ab7 8961 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8962 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8963 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8964 {
636c26b0 8965 if (exp->X_op != O_symbol)
3992d3b7 8966 goto inv_disp;
636c26b0 8967
e5cb08ac 8968 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8969 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8970 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8971 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8972 exp->X_op = O_subtract;
8973 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8974 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8975 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8976 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8977 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8978 else
29b0f896 8979 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8980 }
252b5132 8981
3992d3b7
AM		 8982 else if (exp->X_op == O_absent
8983 || exp->X_op == O_illegal
ee86248c 8984 || exp->X_op == O_big)
2daf4fd8 8985 {
3992d3b7
AM		 8986 inv_disp:
8987 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8988 disp_start);
3992d3b7 8989 ret = 0;
2daf4fd8
AM		 8990 }
8991
0e1147d9
L		 8992 else if (flag_code == CODE_64BIT
8993 && !i.prefix[ADDR_PREFIX]
8994 && exp->X_op == O_constant)
8995 {
8996 /* Since displacement is signed extended to 64bit, don't allow
8997 disp32 and turn off disp32s if they are out of range. */
8998 i.types[this_operand].bitfield.disp32 = 0;
8999 if (!fits_in_signed_long (exp->X_add_number))
9000 {
9001 i.types[this_operand].bitfield.disp32s = 0;
9002 if (i.types[this_operand].bitfield.baseindex)
9003 {
9004 as_bad (_("0x%lx out range of signed 32bit displacement"),
9005 (long) exp->X_add_number);
9006 ret = 0;
9007 }
9008 }
9009 }
9010
4c63da97 9011#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 9012 else if (exp->X_op != O_constant
9013 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9014 && exp_seg != absolute_section
9015 && exp_seg != text_section
9016 && exp_seg != data_section
9017 && exp_seg != bss_section
9018 && exp_seg != undefined_section
9019 && !bfd_is_com_section (exp_seg))
24eab124 9020 {
d0b47220 9021 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 9022 ret = 0;
24eab124 9023 }
252b5132 9024#endif
3956db08 9025
40fb9820
L		 9026 /* Check if this is a displacement only operand. */
9027 bigdisp = i.types[this_operand];
9028 bigdisp.bitfield.disp8 = 0;
9029 bigdisp.bitfield.disp16 = 0;
9030 bigdisp.bitfield.disp32 = 0;
9031 bigdisp.bitfield.disp32s = 0;
9032 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 9033 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 9034 i.types[this_operand] = operand_type_and (i.types[this_operand],
9035 types);
3956db08 9036
3992d3b7 9037 return ret;
252b5132
RH		 9038}
9039
2abc2bec
JB		 9040/* Return the active addressing mode, taking address override and
9041 registers forming the address into consideration. Update the
9042 address override prefix if necessary. */
47926f60 9043
2abc2bec
JB		 9044static enum flag_code
9045i386_addressing_mode (void)
252b5132 9046{
be05d201
L		 9047 enum flag_code addr_mode;
9048
9049 if (i.prefix[ADDR_PREFIX])
9050 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9051 else
9052 {
9053 addr_mode = flag_code;
9054
24eab124 9055#if INFER_ADDR_PREFIX
be05d201
L		 9056 if (i.mem_operands == 0)
9057 {
9058 /* Infer address prefix from the first memory operand. */
9059 const reg_entry *addr_reg = i.base_reg;
9060
9061 if (addr_reg == NULL)
9062 addr_reg = i.index_reg;
eecb386c 9063
be05d201
L		 9064 if (addr_reg)
9065 {
9066 if (addr_reg->reg_num == RegEip
9067 || addr_reg->reg_num == RegEiz
dc821c5f 9068 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9069 addr_mode = CODE_32BIT;
9070 else if (flag_code != CODE_64BIT
dc821c5f 9071 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9072 addr_mode = CODE_16BIT;
9073
9074 if (addr_mode != flag_code)
9075 {
9076 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9077 i.prefixes += 1;
9078 /* Change the size of any displacement too. At most one
9079 of Disp16 or Disp32 is set.
9080 FIXME. There doesn't seem to be any real need for
9081 separate Disp16 and Disp32 flags. The same goes for
9082 Imm16 and Imm32. Removing them would probably clean
9083 up the code quite a lot. */
9084 if (flag_code != CODE_64BIT
9085 && (i.types[this_operand].bitfield.disp16
9086 || i.types[this_operand].bitfield.disp32))
9087 i.types[this_operand]
9088 = operand_type_xor (i.types[this_operand], disp16_32);
9089 }
9090 }
9091 }
24eab124 9092#endif
be05d201
L		 9093 }
9094
2abc2bec
JB		 9095 return addr_mode;
9096}
9097
9098/* Make sure the memory operand we've been dealt is valid.
9099 Return 1 on success, 0 on a failure. */
9100
9101static int
9102i386_index_check (const char *operand_string)
9103{
9104 const char *kind = "base/index";
9105 enum flag_code addr_mode = i386_addressing_mode ();
9106
fc0763e6
JB		 9107 if (current_templates->start->opcode_modifier.isstring
9108 && !current_templates->start->opcode_modifier.immext
9109 && (current_templates->end[-1].opcode_modifier.isstring
9110 || i.mem_operands))
9111 {
9112 /* Memory operands of string insns are special in that they only allow
9113 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9114 const reg_entry *expected_reg;
9115 static const char *di_si[][2] =
9116 {
9117 { "esi", "edi" },
9118 { "si", "di" },
9119 { "rsi", "rdi" }
9120 };
9121 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9122
9123 kind = "string address";
9124
8325cc63 9125 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9126 {
9127 i386_operand_type type = current_templates->end[-1].operand_types[0];
9128
9129 if (!type.bitfield.baseindex
9130 || ((!i.mem_operands != !intel_syntax)
9131 && current_templates->end[-1].operand_types[1]
9132 .bitfield.baseindex))
9133 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9134 expected_reg = hash_find (reg_hash,
9135 di_si[addr_mode][type.bitfield.esseg]);
9136
fc0763e6
JB		 9137 }
9138 else
be05d201 9139 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9140
be05d201
L		 9141 if (i.base_reg != expected_reg
9142 || i.index_reg
fc0763e6 9143 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9144 {
be05d201
L		 9145 /* The second memory operand must have the same size as
9146 the first one. */
9147 if (i.mem_operands
9148 && i.base_reg
9149 && !((addr_mode == CODE_64BIT
dc821c5f 9150 && i.base_reg->reg_type.bitfield.qword)
be05d201 9151 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9152 ? i.base_reg->reg_type.bitfield.dword
9153 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9154 goto bad_address;
9155
fc0763e6
JB		 9156 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9157 operand_string,
9158 intel_syntax ? '[' : '(',
9159 register_prefix,
be05d201 9160 expected_reg->reg_name,
fc0763e6 9161 intel_syntax ? ']' : ')');
be05d201 9162 return 1;
fc0763e6 9163 }
be05d201
L		 9164 else
9165 return 1;
9166
9167bad_address:
9168 as_bad (_("`%s' is not a valid %s expression"),
9169 operand_string, kind);
9170 return 0;
3e73aa7c
JH		 9171 }
9172 else
9173 {
be05d201
L		 9174 if (addr_mode != CODE_16BIT)
9175 {
9176 /* 32-bit/64-bit checks. */
9177 if ((i.base_reg
9178 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9179 ? !i.base_reg->reg_type.bitfield.qword
9180 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9181 && (i.index_reg
9182 || (i.base_reg->reg_num
9183 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9184 || (i.index_reg
1b54b8d7
JB		 9185 && !i.index_reg->reg_type.bitfield.xmmword
9186 && !i.index_reg->reg_type.bitfield.ymmword
9187 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9188 && ((addr_mode == CODE_64BIT
dc821c5f 9189 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9190 || i.index_reg->reg_num == RegRiz)
dc821c5f 9191 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9192 || i.index_reg->reg_num == RegEiz))
9193 || !i.index_reg->reg_type.bitfield.baseindex)))
9194 goto bad_address;
8178be5b
JB		 9195
9196 /* bndmk, bndldx, and bndstx have special restrictions. */
9197 if (current_templates->start->base_opcode == 0xf30f1b
9198 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9199 {
9200 /* They cannot use RIP-relative addressing. */
9201 if (i.base_reg && i.base_reg->reg_num == RegRip)
9202 {
9203 as_bad (_("`%s' cannot be used here"), operand_string);
9204 return 0;
9205 }
9206
9207 /* bndldx and bndstx ignore their scale factor. */
9208 if (current_templates->start->base_opcode != 0xf30f1b
9209 && i.log2_scale_factor)
9210 as_warn (_("register scaling is being ignored here"));
9211 }
be05d201
L		 9212 }
9213 else
3e73aa7c 9214 {
be05d201 9215 /* 16-bit checks. */
3e73aa7c 9216 if ((i.base_reg
dc821c5f 9217 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9218 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9219 || (i.index_reg
dc821c5f 9220 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9221 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9222 || !(i.base_reg
9223 && i.base_reg->reg_num < 6
9224 && i.index_reg->reg_num >= 6
9225 && i.log2_scale_factor == 0))))
be05d201 9226 goto bad_address;
3e73aa7c
JH		 9227 }
9228 }
be05d201 9229 return 1;
24eab124 9230}
252b5132 9231
43234a1e
L		 9232/* Handle vector immediates. */
9233
9234static int
9235RC_SAE_immediate (const char *imm_start)
9236{
9237 unsigned int match_found, j;
9238 const char *pstr = imm_start;
9239 expressionS *exp;
9240
9241 if (*pstr != '{')
9242 return 0;
9243
9244 pstr++;
9245 match_found = 0;
9246 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9247 {
9248 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9249 {
9250 if (!i.rounding)
9251 {
9252 rc_op.type = RC_NamesTable[j].type;
9253 rc_op.operand = this_operand;
9254 i.rounding = &rc_op;
9255 }
9256 else
9257 {
9258 as_bad (_("duplicated `%s'"), imm_start);
9259 return 0;
9260 }
9261 pstr += RC_NamesTable[j].len;
9262 match_found = 1;
9263 break;
9264 }
9265 }
9266 if (!match_found)
9267 return 0;
9268
9269 if (*pstr++ != '}')
9270 {
9271 as_bad (_("Missing '}': '%s'"), imm_start);
9272 return 0;
9273 }
9274 /* RC/SAE immediate string should contain nothing more. */;
9275 if (*pstr != 0)
9276 {
9277 as_bad (_("Junk after '}': '%s'"), imm_start);
9278 return 0;
9279 }
9280
9281 exp = &im_expressions[i.imm_operands++];
9282 i.op[this_operand].imms = exp;
9283
9284 exp->X_op = O_constant;
9285 exp->X_add_number = 0;
9286 exp->X_add_symbol = (symbolS *) 0;
9287 exp->X_op_symbol = (symbolS *) 0;
9288
9289 i.types[this_operand].bitfield.imm8 = 1;
9290 return 1;
9291}
9292
8325cc63
JB		 9293/* Only string instructions can have a second memory operand, so
9294 reduce current_templates to just those if it contains any. */
9295static int
9296maybe_adjust_templates (void)
9297{
9298 const insn_template *t;
9299
9300 gas_assert (i.mem_operands == 1);
9301
9302 for (t = current_templates->start; t < current_templates->end; ++t)
9303 if (t->opcode_modifier.isstring)
9304 break;
9305
9306 if (t < current_templates->end)
9307 {
9308 static templates aux_templates;
9309 bfd_boolean recheck;
9310
9311 aux_templates.start = t;
9312 for (; t < current_templates->end; ++t)
9313 if (!t->opcode_modifier.isstring)
9314 break;
9315 aux_templates.end = t;
9316
9317 /* Determine whether to re-check the first memory operand. */
9318 recheck = (aux_templates.start != current_templates->start
9319 || t != current_templates->end);
9320
9321 current_templates = &aux_templates;
9322
9323 if (recheck)
9324 {
9325 i.mem_operands = 0;
9326 if (i.memop1_string != NULL
9327 && i386_index_check (i.memop1_string) == 0)
9328 return 0;
9329 i.mem_operands = 1;
9330 }
9331 }
9332
9333 return 1;
9334}
9335
fc0763e6 9336/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9337 on error. */
252b5132 9338
252b5132 9339static int
a7619375 9340i386_att_operand (char *operand_string)
252b5132 9341{
af6bdddf
AM		 9342 const reg_entry *r;
9343 char *end_op;
24eab124 9344 char *op_string = operand_string;
252b5132 9345
24eab124 9346 if (is_space_char (*op_string))
252b5132
RH		 9347 ++op_string;
9348
24eab124 9349 /* We check for an absolute prefix (differentiating,
47926f60 9350 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9351 if (*op_string == ABSOLUTE_PREFIX)
9352 {
9353 ++op_string;
9354 if (is_space_char (*op_string))
9355 ++op_string;
40fb9820 9356 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9357 }
252b5132 9358
47926f60 9359 /* Check if operand is a register. */
4d1bb795 9360 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9361 {
40fb9820
L		 9362 i386_operand_type temp;
9363
24eab124
AM		 9364 /* Check for a segment override by searching for ':' after a
9365 segment register. */
9366 op_string = end_op;
9367 if (is_space_char (*op_string))
9368 ++op_string;
40fb9820
L		 9369 if (*op_string == ':'
9370 && (r->reg_type.bitfield.sreg2
9371 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9372 {
9373 switch (r->reg_num)
9374 {
9375 case 0:
9376 i.seg[i.mem_operands] = &es;
9377 break;
9378 case 1:
9379 i.seg[i.mem_operands] = &cs;
9380 break;
9381 case 2:
9382 i.seg[i.mem_operands] = &ss;
9383 break;
9384 case 3:
9385 i.seg[i.mem_operands] = &ds;
9386 break;
9387 case 4:
9388 i.seg[i.mem_operands] = &fs;
9389 break;
9390 case 5:
9391 i.seg[i.mem_operands] = &gs;
9392 break;
9393 }
252b5132 9394
24eab124 9395 /* Skip the ':' and whitespace. */
252b5132
RH		 9396 ++op_string;
9397 if (is_space_char (*op_string))
24eab124 9398 ++op_string;
252b5132 9399
24eab124
AM		 9400 if (!is_digit_char (*op_string)
9401 && !is_identifier_char (*op_string)
9402 && *op_string != '('
9403 && *op_string != ABSOLUTE_PREFIX)
9404 {
9405 as_bad (_("bad memory operand `%s'"), op_string);
9406 return 0;
9407 }
47926f60 9408 /* Handle case of %es:*foo. */
24eab124
AM		 9409 if (*op_string == ABSOLUTE_PREFIX)
9410 {
9411 ++op_string;
9412 if (is_space_char (*op_string))
9413 ++op_string;
40fb9820 9414 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9415 }
9416 goto do_memory_reference;
9417 }
43234a1e
L		 9418
9419 /* Handle vector operations. */
9420 if (*op_string == '{')
9421 {
9422 op_string = check_VecOperations (op_string, NULL);
9423 if (op_string == NULL)
9424 return 0;
9425 }
9426
24eab124
AM		 9427 if (*op_string)
9428 {
d0b47220 9429 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9430 return 0;
9431 }
40fb9820
L		 9432 temp = r->reg_type;
9433 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9434 i.types[this_operand] = operand_type_or (i.types[this_operand],
9435 temp);
7d5e4556 9436 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9437 i.op[this_operand].regs = r;
24eab124
AM		 9438 i.reg_operands++;
9439 }
af6bdddf
AM		 9440 else if (*op_string == REGISTER_PREFIX)
9441 {
9442 as_bad (_("bad register name `%s'"), op_string);
9443 return 0;
9444 }
24eab124 9445 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9446 {
24eab124 9447 ++op_string;
40fb9820 9448 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9449 {
d0b47220 9450 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9451 return 0;
9452 }
9453 if (!i386_immediate (op_string))
9454 return 0;
9455 }
43234a1e
L		 9456 else if (RC_SAE_immediate (operand_string))
9457 {
9458 /* If it is a RC or SAE immediate, do nothing. */
9459 ;
9460 }
24eab124
AM		 9461 else if (is_digit_char (*op_string)
9462 || is_identifier_char (*op_string)
d02603dc 9463 || *op_string == '"'
e5cb08ac 9464 || *op_string == '(')
24eab124 9465 {
47926f60 9466 /* This is a memory reference of some sort. */
af6bdddf 9467 char *base_string;
252b5132 9468
47926f60 9469 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9470 char *displacement_string_start;
9471 char *displacement_string_end;
43234a1e 9472 char *vop_start;
252b5132 9473
24eab124 9474 do_memory_reference:
8325cc63
JB		 9475 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9476 return 0;
24eab124 9477 if ((i.mem_operands == 1
40fb9820 9478 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9479 || i.mem_operands == 2)
9480 {
9481 as_bad (_("too many memory references for `%s'"),
9482 current_templates->start->name);
9483 return 0;
9484 }
252b5132 9485
24eab124
AM		 9486 /* Check for base index form. We detect the base index form by
9487 looking for an ')' at the end of the operand, searching
9488 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9489 after the '('. */
af6bdddf 9490 base_string = op_string + strlen (op_string);
c3332e24 9491
43234a1e
L		 9492 /* Handle vector operations. */
9493 vop_start = strchr (op_string, '{');
9494 if (vop_start && vop_start < base_string)
9495 {
9496 if (check_VecOperations (vop_start, base_string) == NULL)
9497 return 0;
9498 base_string = vop_start;
9499 }
9500
af6bdddf
AM		 9501 --base_string;
9502 if (is_space_char (*base_string))
9503 --base_string;
252b5132 9504
47926f60 9505 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9506 displacement_string_start = op_string;
9507 displacement_string_end = base_string + 1;
252b5132 9508
24eab124
AM		 9509 if (*base_string == ')')
9510 {
af6bdddf 9511 char *temp_string;
24eab124
AM		 9512 unsigned int parens_balanced = 1;
9513 /* We've already checked that the number of left & right ()'s are
47926f60 9514 equal, so this loop will not be infinite. */
24eab124
AM		 9515 do
9516 {
9517 base_string--;
9518 if (*base_string == ')')
9519 parens_balanced++;
9520 if (*base_string == '(')
9521 parens_balanced--;
9522 }
9523 while (parens_balanced);
c3332e24 9524
af6bdddf 9525 temp_string = base_string;
c3332e24 9526
24eab124 9527 /* Skip past '(' and whitespace. */
252b5132
RH		 9528 ++base_string;
9529 if (is_space_char (*base_string))
24eab124 9530 ++base_string;
252b5132 9531
af6bdddf 9532 if (*base_string == ','
4eed87de
AM		 9533 || ((i.base_reg = parse_register (base_string, &end_op))
9534 != NULL))
252b5132 9535 {
af6bdddf 9536 displacement_string_end = temp_string;
252b5132 9537
40fb9820 9538 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9539
af6bdddf 9540 if (i.base_reg)
24eab124 9541 {
24eab124
AM		 9542 base_string = end_op;
9543 if (is_space_char (*base_string))
9544 ++base_string;
af6bdddf
AM		 9545 }
9546
9547 /* There may be an index reg or scale factor here. */
9548 if (*base_string == ',')
9549 {
9550 ++base_string;
9551 if (is_space_char (*base_string))
9552 ++base_string;
9553
4eed87de
AM		 9554 if ((i.index_reg = parse_register (base_string, &end_op))
9555 != NULL)
24eab124 9556 {
af6bdddf 9557 base_string = end_op;
24eab124
AM		 9558 if (is_space_char (*base_string))
9559 ++base_string;
af6bdddf
AM		 9560 if (*base_string == ',')
9561 {
9562 ++base_string;
9563 if (is_space_char (*base_string))
9564 ++base_string;
9565 }
e5cb08ac 9566 else if (*base_string != ')')
af6bdddf 9567 {
4eed87de
AM		 9568 as_bad (_("expecting `,' or `)' "
9569 "after index register in `%s'"),
af6bdddf
AM		 9570 operand_string);
9571 return 0;
9572 }
24eab124 9573 }
af6bdddf 9574 else if (*base_string == REGISTER_PREFIX)
24eab124 9575 {
f76bf5e0
L		 9576 end_op = strchr (base_string, ',');
9577 if (end_op)
9578 *end_op = '\0';
af6bdddf 9579 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9580 return 0;
9581 }
252b5132 9582
47926f60 9583 /* Check for scale factor. */
551c1ca1 9584 if (*base_string != ')')
af6bdddf 9585 {
551c1ca1
AM		 9586 char *end_scale = i386_scale (base_string);
9587
9588 if (!end_scale)
af6bdddf 9589 return 0;
24eab124 9590
551c1ca1 9591 base_string = end_scale;
af6bdddf
AM		 9592 if (is_space_char (*base_string))
9593 ++base_string;
9594 if (*base_string != ')')
9595 {
4eed87de
AM		 9596 as_bad (_("expecting `)' "
9597 "after scale factor in `%s'"),
af6bdddf
AM		 9598 operand_string);
9599 return 0;
9600 }
9601 }
9602 else if (!i.index_reg)
24eab124 9603 {
4eed87de
AM		 9604 as_bad (_("expecting index register or scale factor "
9605 "after `,'; got '%c'"),
af6bdddf 9606 *base_string);
24eab124
AM		 9607 return 0;
9608 }
9609 }
af6bdddf 9610 else if (*base_string != ')')
24eab124 9611 {
4eed87de
AM		 9612 as_bad (_("expecting `,' or `)' "
9613 "after base register in `%s'"),
af6bdddf 9614 operand_string);
24eab124
AM		 9615 return 0;
9616 }
c3332e24 9617 }
af6bdddf 9618 else if (*base_string == REGISTER_PREFIX)
c3332e24 9619 {
f76bf5e0
L		 9620 end_op = strchr (base_string, ',');
9621 if (end_op)
9622 *end_op = '\0';
af6bdddf 9623 as_bad (_("bad register name `%s'"), base_string);
24eab124 9624 return 0;
c3332e24 9625 }
24eab124
AM		 9626 }
9627
9628 /* If there's an expression beginning the operand, parse it,
9629 assuming displacement_string_start and
9630 displacement_string_end are meaningful. */
9631 if (displacement_string_start != displacement_string_end)
9632 {
9633 if (!i386_displacement (displacement_string_start,
9634 displacement_string_end))
9635 return 0;
9636 }
9637
9638 /* Special case for (%dx) while doing input/output op. */
9639 if (i.base_reg
0dfbf9d7
L		 9640 && operand_type_equal (&i.base_reg->reg_type,
9641 &reg16_inoutportreg)
24eab124
AM		 9642 && i.index_reg == 0
9643 && i.log2_scale_factor == 0
9644 && i.seg[i.mem_operands] == 0
40fb9820 9645 && !operand_type_check (i.types[this_operand], disp))
24eab124 9646 {
65da13b5 9647 i.types[this_operand] = inoutportreg;
24eab124
AM		 9648 return 1;
9649 }
9650
eecb386c
AM		 9651 if (i386_index_check (operand_string) == 0)
9652 return 0;
5c07affc 9653 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9654 if (i.mem_operands == 0)
9655 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9656 i.mem_operands++;
9657 }
9658 else
ce8a8b2f
AM		 9659 {
9660 /* It's not a memory operand; argh! */
24eab124
AM		 9661 as_bad (_("invalid char %s beginning operand %d `%s'"),
9662 output_invalid (*op_string),
9663 this_operand + 1,
9664 op_string);
9665 return 0;
9666 }
47926f60 9667 return 1; /* Normal return. */
252b5132
RH		 9668}
9669\f
fa94de6b
RM		 9670/* Calculate the maximum variable size (i.e., excluding fr_fix)
9671 that an rs_machine_dependent frag may reach. */
9672
9673unsigned int
9674i386_frag_max_var (fragS *frag)
9675{
9676 /* The only relaxable frags are for jumps.
9677 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9678 gas_assert (frag->fr_type == rs_machine_dependent);
9679 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9680}
9681
b084df0b
L		 9682#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9683static int
8dcea932 9684elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9685{
9686 /* STT_GNU_IFUNC symbol must go through PLT. */
9687 if ((symbol_get_bfdsym (fr_symbol)->flags
9688 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9689 return 0;
9690
9691 if (!S_IS_EXTERNAL (fr_symbol))
9692 /* Symbol may be weak or local. */
9693 return !S_IS_WEAK (fr_symbol);
9694
8dcea932
L		 9695 /* Global symbols with non-default visibility can't be preempted. */
9696 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9697 return 1;
9698
9699 if (fr_var != NO_RELOC)
9700 switch ((enum bfd_reloc_code_real) fr_var)
9701 {
9702 case BFD_RELOC_386_PLT32:
9703 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9704 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9705 return 0;
9706 default:
9707 abort ();
9708 }
9709
b084df0b
L		 9710 /* Global symbols with default visibility in a shared library may be
9711 preempted by another definition. */
8dcea932 9712 return !shared;
b084df0b
L		 9713}
9714#endif
9715
ee7fcc42
AM		 9716/* md_estimate_size_before_relax()
9717
9718 Called just before relax() for rs_machine_dependent frags. The x86
9719 assembler uses these frags to handle variable size jump
9720 instructions.
9721
9722 Any symbol that is now undefined will not become defined.
9723 Return the correct fr_subtype in the frag.
9724 Return the initial "guess for variable size of frag" to caller.
9725 The guess is actually the growth beyond the fixed part. Whatever
9726 we do to grow the fixed or variable part contributes to our
9727 returned value. */
9728
252b5132 9729int
7016a5d5 9730md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9731{
252b5132 9732 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9733 check for un-relaxable symbols. On an ELF system, we can't relax
9734 an externally visible symbol, because it may be overridden by a
9735 shared library. */
9736 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9737#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9738 || (IS_ELF
8dcea932
L		 9739 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9740 fragP->fr_var))
fbeb56a4
DK		 9741#endif
9742#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9743 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9744 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9745#endif
9746 )
252b5132 9747 {
b98ef147
AM		 9748 /* Symbol is undefined in this segment, or we need to keep a
9749 reloc so that weak symbols can be overridden. */
9750 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9751 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9752 unsigned char *opcode;
9753 int old_fr_fix;
f6af82bd 9754
ee7fcc42 9755 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9756 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9757 else if (size == 2)
f6af82bd 9758 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9759#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9760 else if (need_plt32_p (fragP->fr_symbol))
9761 reloc_type = BFD_RELOC_X86_64_PLT32;
9762#endif
f6af82bd
AM		 9763 else
9764 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9765
ee7fcc42
AM		 9766 old_fr_fix = fragP->fr_fix;
9767 opcode = (unsigned char *) fragP->fr_opcode;
9768
fddf5b5b 9769 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9770 {
fddf5b5b
AM		 9771 case UNCOND_JUMP:
9772 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9773 opcode[0] = 0xe9;
252b5132 9774 fragP->fr_fix += size;
062cd5e7
AS		 9775 fix_new (fragP, old_fr_fix, size,
9776 fragP->fr_symbol,
9777 fragP->fr_offset, 1,
9778 reloc_type);
252b5132
RH		 9779 break;
9780
fddf5b5b 9781 case COND_JUMP86:
412167cb
AM		 9782 if (size == 2
9783 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9784 {
9785 /* Negate the condition, and branch past an
9786 unconditional jump. */
9787 opcode[0] ^= 1;
9788 opcode[1] = 3;
9789 /* Insert an unconditional jump. */
9790 opcode[2] = 0xe9;
9791 /* We added two extra opcode bytes, and have a two byte
9792 offset. */
9793 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9794 fix_new (fragP, old_fr_fix + 2, 2,
9795 fragP->fr_symbol,
9796 fragP->fr_offset, 1,
9797 reloc_type);
fddf5b5b
AM		 9798 break;
9799 }
9800 /* Fall through. */
9801
9802 case COND_JUMP:
412167cb
AM		 9803 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9804 {
3e02c1cc
AM		 9805 fixS *fixP;
9806
412167cb 9807 fragP->fr_fix += 1;
3e02c1cc
AM		 9808 fixP = fix_new (fragP, old_fr_fix, 1,
9809 fragP->fr_symbol,
9810 fragP->fr_offset, 1,
9811 BFD_RELOC_8_PCREL);
9812 fixP->fx_signed = 1;
412167cb
AM		 9813 break;
9814 }
93c2a809 9815
24eab124 9816 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9817 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9818 opcode[1] = opcode[0] + 0x10;
f6af82bd 9819 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9820 /* We've added an opcode byte. */
9821 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9822 fix_new (fragP, old_fr_fix + 1, size,
9823 fragP->fr_symbol,
9824 fragP->fr_offset, 1,
9825 reloc_type);
252b5132 9826 break;
fddf5b5b
AM		 9827
9828 default:
9829 BAD_CASE (fragP->fr_subtype);
9830 break;
252b5132
RH		 9831 }
9832 frag_wane (fragP);
ee7fcc42 9833 return fragP->fr_fix - old_fr_fix;
252b5132 9834 }
93c2a809 9835
93c2a809
AM		 9836 /* Guess size depending on current relax state. Initially the relax
9837 state will correspond to a short jump and we return 1, because
9838 the variable part of the frag (the branch offset) is one byte
9839 long. However, we can relax a section more than once and in that
9840 case we must either set fr_subtype back to the unrelaxed state,
9841 or return the value for the appropriate branch. */
9842 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9843}
9844
47926f60
KH		 9845/* Called after relax() is finished.
9846
9847 In: Address of frag.
9848 fr_type == rs_machine_dependent.
9849 fr_subtype is what the address relaxed to.
9850
9851 Out: Any fixSs and constants are set up.
9852 Caller will turn frag into a ".space 0". */
9853
252b5132 9854void
7016a5d5
TG		 9855md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9856 fragS *fragP)
252b5132 9857{
29b0f896 9858 unsigned char *opcode;
252b5132 9859 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9860 offsetT target_address;
9861 offsetT opcode_address;
252b5132 9862 unsigned int extension = 0;
847f7ad4 9863 offsetT displacement_from_opcode_start;
252b5132
RH		 9864
9865 opcode = (unsigned char *) fragP->fr_opcode;
9866
47926f60 9867 /* Address we want to reach in file space. */
252b5132 9868 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9869
47926f60 9870 /* Address opcode resides at in file space. */
252b5132
RH		 9871 opcode_address = fragP->fr_address + fragP->fr_fix;
9872
47926f60 9873 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9874 displacement_from_opcode_start = target_address - opcode_address;
9875
fddf5b5b 9876 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9877 {
47926f60
KH		 9878 /* Don't have to change opcode. */
9879 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9880 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9881 }
9882 else
9883 {
9884 if (no_cond_jump_promotion
9885 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9886 as_warn_where (fragP->fr_file, fragP->fr_line,
9887 _("long jump required"));
252b5132 9888
fddf5b5b
AM		 9889 switch (fragP->fr_subtype)
9890 {
9891 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9892 extension = 4; /* 1 opcode + 4 displacement */
9893 opcode[0] = 0xe9;
9894 where_to_put_displacement = &opcode[1];
9895 break;
252b5132 9896
fddf5b5b
AM		 9897 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9898 extension = 2; /* 1 opcode + 2 displacement */
9899 opcode[0] = 0xe9;
9900 where_to_put_displacement = &opcode[1];
9901 break;
252b5132 9902
fddf5b5b
AM		 9903 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9904 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9905 extension = 5; /* 2 opcode + 4 displacement */
9906 opcode[1] = opcode[0] + 0x10;
9907 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9908 where_to_put_displacement = &opcode[2];
9909 break;
252b5132 9910
fddf5b5b
AM		 9911 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9912 extension = 3; /* 2 opcode + 2 displacement */
9913 opcode[1] = opcode[0] + 0x10;
9914 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9915 where_to_put_displacement = &opcode[2];
9916 break;
252b5132 9917
fddf5b5b
AM		 9918 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9919 extension = 4;
9920 opcode[0] ^= 1;
9921 opcode[1] = 3;
9922 opcode[2] = 0xe9;
9923 where_to_put_displacement = &opcode[3];
9924 break;
9925
9926 default:
9927 BAD_CASE (fragP->fr_subtype);
9928 break;
9929 }
252b5132 9930 }
fddf5b5b 9931
7b81dfbb
AJ		 9932 /* If size if less then four we are sure that the operand fits,
9933 but if it's 4, then it could be that the displacement is larger
9934 then -/+ 2GB. */
9935 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9936 && object_64bit
9937 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9938 + ((addressT) 1 << 31))
9939 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9940 {
9941 as_bad_where (fragP->fr_file, fragP->fr_line,
9942 _("jump target out of range"));
9943 /* Make us emit 0. */
9944 displacement_from_opcode_start = extension;
9945 }
47926f60 9946 /* Now put displacement after opcode. */
252b5132
RH		 9947 md_number_to_chars ((char *) where_to_put_displacement,
9948 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9949 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9950 fragP->fr_fix += extension;
9951}
9952\f
7016a5d5 9953/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9954 by our caller that we have all the info we need to fix it up.
9955
7016a5d5
TG		 9956 Parameter valP is the pointer to the value of the bits.
9957
252b5132
RH		 9958 On the 386, immediates, displacements, and data pointers are all in
9959 the same (little-endian) format, so we don't need to care about which
9960 we are handling. */
9961
94f592af 9962void
7016a5d5 9963md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9964{
94f592af 9965 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9966 valueT value = *valP;
252b5132 9967
f86103b7 9968#if !defined (TE_Mach)
93382f6d
AM		 9969 if (fixP->fx_pcrel)
9970 {
9971 switch (fixP->fx_r_type)
9972 {
5865bb77
ILT		 9973 default:
9974 break;
9975
d6ab8113
JB		 9976 case BFD_RELOC_64:
9977 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9978 break;
93382f6d 9979 case BFD_RELOC_32:
ae8887b5 9980 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9981 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9982 break;
9983 case BFD_RELOC_16:
9984 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9985 break;
9986 case BFD_RELOC_8:
9987 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9988 break;
9989 }
9990 }
252b5132 9991
a161fe53 9992 if (fixP->fx_addsy != NULL
31312f95 9993 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9994 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9995 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9996 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9997 && !use_rela_relocations)
252b5132 9998 {
31312f95
AM		 9999 /* This is a hack. There should be a better way to handle this.
10000 This covers for the fact that bfd_install_relocation will
10001 subtract the current location (for partial_inplace, PC relative
10002 relocations); see more below. */
252b5132 10003#ifndef OBJ_AOUT
718ddfc0 10004 if (IS_ELF
252b5132
RH		 10005#ifdef TE_PE
10006 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10007#endif
10008 )
10009 value += fixP->fx_where + fixP->fx_frag->fr_address;
10010#endif
10011#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10012 if (IS_ELF)
252b5132 10013 {
6539b54b 10014 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 10015
6539b54b 10016 if ((sym_seg == seg
2f66722d 10017 || (symbol_section_p (fixP->fx_addsy)
6539b54b 10018 && sym_seg != absolute_section))
af65af87 10019 && !generic_force_reloc (fixP))
2f66722d
AM		 10020 {
10021 /* Yes, we add the values in twice. This is because
6539b54b
AM		 10022 bfd_install_relocation subtracts them out again. I think
10023 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 10024 it. FIXME. */
10025 value += fixP->fx_where + fixP->fx_frag->fr_address;
10026 }
252b5132
RH		 10027 }
10028#endif
10029#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 10030 /* For some reason, the PE format does not store a
10031 section address offset for a PC relative symbol. */
10032 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 10033 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 10034 value += md_pcrel_from (fixP);
10035#endif
10036 }
fbeb56a4 10037#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 10038 if (fixP->fx_addsy != NULL
10039 && S_IS_WEAK (fixP->fx_addsy)
10040 /* PR 16858: Do not modify weak function references. */
10041 && ! fixP->fx_pcrel)
fbeb56a4 10042 {
296a8689
NC		 10043#if !defined (TE_PEP)
10044 /* For x86 PE weak function symbols are neither PC-relative
10045 nor do they set S_IS_FUNCTION. So the only reliable way
10046 to detect them is to check the flags of their containing
10047 section. */
10048 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10049 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10050 ;
10051 else
10052#endif
fbeb56a4
DK		 10053 value -= S_GET_VALUE (fixP->fx_addsy);
10054 }
10055#endif
252b5132
RH		 10056
10057 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10058 and we must not disappoint it. */
252b5132 10059#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10060 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10061 switch (fixP->fx_r_type)
10062 {
10063 case BFD_RELOC_386_PLT32:
3e73aa7c 10064 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10065 /* Make the jump instruction point to the address of the operand. At
10066 runtime we merely add the offset to the actual PLT entry. */
10067 value = -4;
10068 break;
31312f95 10069
13ae64f3
JJ		 10070 case BFD_RELOC_386_TLS_GD:
10071 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10072 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10073 case BFD_RELOC_386_TLS_IE:
10074 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10075 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10076 case BFD_RELOC_X86_64_TLSGD:
10077 case BFD_RELOC_X86_64_TLSLD:
10078 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10079 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10080 value = 0; /* Fully resolved at runtime. No addend. */
10081 /* Fallthrough */
10082 case BFD_RELOC_386_TLS_LE:
10083 case BFD_RELOC_386_TLS_LDO_32:
10084 case BFD_RELOC_386_TLS_LE_32:
10085 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10086 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10087 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10088 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10089 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10090 break;
10091
67a4f2b7
AO		 10092 case BFD_RELOC_386_TLS_DESC_CALL:
10093 case BFD_RELOC_X86_64_TLSDESC_CALL:
10094 value = 0; /* Fully resolved at runtime. No addend. */
10095 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10096 fixP->fx_done = 0;
10097 return;
10098
47926f60
KH		 10099 case BFD_RELOC_VTABLE_INHERIT:
10100 case BFD_RELOC_VTABLE_ENTRY:
10101 fixP->fx_done = 0;
94f592af 10102 return;
47926f60
KH		 10103
10104 default:
10105 break;
10106 }
10107#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10108 *valP = value;
f86103b7 10109#endif /* !defined (TE_Mach) */
3e73aa7c 10110
3e73aa7c 10111 /* Are we finished with this relocation now? */
c6682705 10112 if (fixP->fx_addsy == NULL)
3e73aa7c 10113 fixP->fx_done = 1;
fbeb56a4
DK		 10114#if defined (OBJ_COFF) && defined (TE_PE)
10115 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10116 {
10117 fixP->fx_done = 0;
10118 /* Remember value for tc_gen_reloc. */
10119 fixP->fx_addnumber = value;
10120 /* Clear out the frag for now. */
10121 value = 0;
10122 }
10123#endif
3e73aa7c
JH		 10124 else if (use_rela_relocations)
10125 {
10126 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10127 /* Remember value for tc_gen_reloc. */
10128 fixP->fx_addnumber = value;
3e73aa7c
JH		 10129 value = 0;
10130 }
f86103b7 10131
94f592af 10132 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10133}
252b5132 10134\f
6d4af3c2 10135const char *
499ac353 10136md_atof (int type, char *litP, int *sizeP)
252b5132 10137{
499ac353
NC		 10138 /* This outputs the LITTLENUMs in REVERSE order;
10139 in accord with the bigendian 386. */
10140 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10141}
10142\f
2d545b82 10143static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10144
252b5132 10145static char *
e3bb37b5 10146output_invalid (int c)
252b5132 10147{
3882b010 10148 if (ISPRINT (c))
f9f21a03
L		 10149 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10150 "'%c'", c);
252b5132 10151 else
f9f21a03 10152 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10153 "(0x%x)", (unsigned char) c);
252b5132
RH		 10154 return output_invalid_buf;
10155}
10156
af6bdddf 10157/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10158
10159static const reg_entry *
4d1bb795 10160parse_real_register (char *reg_string, char **end_op)
252b5132 10161{
af6bdddf
AM		 10162 char *s = reg_string;
10163 char *p;
252b5132
RH		 10164 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10165 const reg_entry *r;
10166
10167 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10168 if (*s == REGISTER_PREFIX)
10169 ++s;
10170
10171 if (is_space_char (*s))
10172 ++s;
10173
10174 p = reg_name_given;
af6bdddf 10175 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10176 {
10177 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10178 return (const reg_entry *) NULL;
10179 s++;
252b5132
RH		 10180 }
10181
6588847e
DN		 10182 /* For naked regs, make sure that we are not dealing with an identifier.
10183 This prevents confusing an identifier like `eax_var' with register
10184 `eax'. */
10185 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10186 return (const reg_entry *) NULL;
10187
af6bdddf 10188 *end_op = s;
252b5132
RH		 10189
10190 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10191
5f47d35b 10192 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10193 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10194 {
0e0eea78
JB		 10195 if (!cpu_arch_flags.bitfield.cpu8087
10196 && !cpu_arch_flags.bitfield.cpu287
10197 && !cpu_arch_flags.bitfield.cpu387)
10198 return (const reg_entry *) NULL;
10199
5f47d35b
AM		 10200 if (is_space_char (*s))
10201 ++s;
10202 if (*s == '(')
10203 {
af6bdddf 10204 ++s;
5f47d35b
AM		 10205 if (is_space_char (*s))
10206 ++s;
10207 if (*s >= '0' && *s <= '7')
10208 {
db557034 10209 int fpr = *s - '0';
af6bdddf 10210 ++s;
5f47d35b
AM		 10211 if (is_space_char (*s))
10212 ++s;
10213 if (*s == ')')
10214 {
10215 *end_op = s + 1;
1e9cc1c2 10216 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10217 know (r);
10218 return r + fpr;
5f47d35b 10219 }
5f47d35b 10220 }
47926f60 10221 /* We have "%st(" then garbage. */
5f47d35b
AM		 10222 return (const reg_entry *) NULL;
10223 }
10224 }
10225
a60de03c
JB		 10226 if (r == NULL || allow_pseudo_reg)
10227 return r;
10228
0dfbf9d7 10229 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10230 return (const reg_entry *) NULL;
10231
dc821c5f 10232 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10233 || r->reg_type.bitfield.sreg3
10234 || r->reg_type.bitfield.control
10235 || r->reg_type.bitfield.debug
10236 || r->reg_type.bitfield.test)
10237 && !cpu_arch_flags.bitfield.cpui386)
10238 return (const reg_entry *) NULL;
10239
6e041cf4 10240 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10241 return (const reg_entry *) NULL;
10242
6e041cf4
JB		 10243 if (!cpu_arch_flags.bitfield.cpuavx512f)
10244 {
10245 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10246 return (const reg_entry *) NULL;
40f12533 10247
6e041cf4
JB		 10248 if (!cpu_arch_flags.bitfield.cpuavx)
10249 {
10250 if (r->reg_type.bitfield.ymmword)
10251 return (const reg_entry *) NULL;
1848e567 10252
6e041cf4
JB		 10253 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10254 return (const reg_entry *) NULL;
10255 }
10256 }
43234a1e 10257
1adf7f56
JB		 10258 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10259 return (const reg_entry *) NULL;
10260
db51cc60 10261 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10262 if (!allow_index_reg
db51cc60
L		 10263 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10264 return (const reg_entry *) NULL;
10265
1d3f8286
JB		 10266 /* Upper 16 vector registers are only available with VREX in 64bit
10267 mode, and require EVEX encoding. */
10268 if (r->reg_flags & RegVRex)
43234a1e
L		 10269 {
10270 if (!cpu_arch_flags.bitfield.cpuvrex
10271 || flag_code != CODE_64BIT)
10272 return (const reg_entry *) NULL;
1d3f8286
JB		 10273
10274 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10275 }
10276
a60de03c 10277 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10278 || r->reg_type.bitfield.qword)
40fb9820 10279 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10280 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10281 && flag_code != CODE_64BIT)
20f0a1fc 10282 return (const reg_entry *) NULL;
1ae00879 10283
b7240065
JB		 10284 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10285 return (const reg_entry *) NULL;
10286
252b5132
RH		 10287 return r;
10288}
4d1bb795
JB		 10289
10290/* REG_STRING starts *before* REGISTER_PREFIX. */
10291
10292static const reg_entry *
10293parse_register (char *reg_string, char **end_op)
10294{
10295 const reg_entry *r;
10296
10297 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10298 r = parse_real_register (reg_string, end_op);
10299 else
10300 r = NULL;
10301 if (!r)
10302 {
10303 char *save = input_line_pointer;
10304 char c;
10305 symbolS *symbolP;
10306
10307 input_line_pointer = reg_string;
d02603dc 10308 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10309 symbolP = symbol_find (reg_string);
10310 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10311 {
10312 const expressionS *e = symbol_get_value_expression (symbolP);
10313
0398aac5 10314 know (e->X_op == O_register);
4eed87de 10315 know (e->X_add_number >= 0
c3fe08fa 10316 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10317 r = i386_regtab + e->X_add_number;
d3bb6b49 10318 if ((r->reg_flags & RegVRex))
86fa6981 10319 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10320 *end_op = input_line_pointer;
10321 }
10322 *input_line_pointer = c;
10323 input_line_pointer = save;
10324 }
10325 return r;
10326}
10327
10328int
10329i386_parse_name (char *name, expressionS *e, char *nextcharP)
10330{
10331 const reg_entry *r;
10332 char *end = input_line_pointer;
10333
10334 *end = *nextcharP;
10335 r = parse_register (name, &input_line_pointer);
10336 if (r && end <= input_line_pointer)
10337 {
10338 *nextcharP = *input_line_pointer;
10339 *input_line_pointer = 0;
10340 e->X_op = O_register;
10341 e->X_add_number = r - i386_regtab;
10342 return 1;
10343 }
10344 input_line_pointer = end;
10345 *end = 0;
ee86248c 10346 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10347}
10348
10349void
10350md_operand (expressionS *e)
10351{
ee86248c
JB		 10352 char *end;
10353 const reg_entry *r;
4d1bb795 10354
ee86248c
JB		 10355 switch (*input_line_pointer)
10356 {
10357 case REGISTER_PREFIX:
10358 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10359 if (r)
10360 {
10361 e->X_op = O_register;
10362 e->X_add_number = r - i386_regtab;
10363 input_line_pointer = end;
10364 }
ee86248c
JB		 10365 break;
10366
10367 case '[':
9c2799c2 10368 gas_assert (intel_syntax);
ee86248c
JB		 10369 end = input_line_pointer++;
10370 expression (e);
10371 if (*input_line_pointer == ']')
10372 {
10373 ++input_line_pointer;
10374 e->X_op_symbol = make_expr_symbol (e);
10375 e->X_add_symbol = NULL;
10376 e->X_add_number = 0;
10377 e->X_op = O_index;
10378 }
10379 else
10380 {
10381 e->X_op = O_absent;
10382 input_line_pointer = end;
10383 }
10384 break;
4d1bb795
JB		 10385 }
10386}
10387
252b5132 10388\f
4cc782b5 10389#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10390const char *md_shortopts = "kVQ:sqnO::";
252b5132 10391#else
b6f8c7c4 10392const char *md_shortopts = "qnO::";
252b5132 10393#endif
6e0b89ee 10394
3e73aa7c 10395#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10396#define OPTION_64 (OPTION_MD_BASE + 1)
10397#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10398#define OPTION_MARCH (OPTION_MD_BASE + 3)
10399#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10400#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10401#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10402#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10403#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10404#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10405#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10406#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10407#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10408#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10409#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10410#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10411#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10412#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10413#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10414#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10415#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10416#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10417#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10418#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10419#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10420
99ad8390
NC		 10421struct option md_longopts[] =
10422{
3e73aa7c 10423 {"32", no_argument, NULL, OPTION_32},
321098a5 10424#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10425 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10426 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10427#endif
10428#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10429 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10430 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10431#endif
b3b91714 10432 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10433 {"march", required_argument, NULL, OPTION_MARCH},
10434 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10435 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10436 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10437 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10438 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10439 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10440 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10441 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10442 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10443 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10444 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10445 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10446# if defined (TE_PE) || defined (TE_PEP)
10447 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10448#endif
d1982f93 10449 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10450 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10451 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10452 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10453 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10454 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10455 {NULL, no_argument, NULL, 0}
10456};
10457size_t md_longopts_size = sizeof (md_longopts);
10458
10459int
17b9d67d 10460md_parse_option (int c, const char *arg)
252b5132 10461{
91d6fa6a 10462 unsigned int j;
293f5f65 10463 char *arch, *next, *saved;
9103f4f4 10464
252b5132
RH		 10465 switch (c)
10466 {
12b55ccc
L		 10467 case 'n':
10468 optimize_align_code = 0;
10469 break;
10470
a38cf1db
AM		 10471 case 'q':
10472 quiet_warnings = 1;
252b5132
RH		 10473 break;
10474
10475#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10476 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10477 should be emitted or not. FIXME: Not implemented. */
10478 case 'Q':
252b5132
RH		 10479 break;
10480
10481 /* -V: SVR4 argument to print version ID. */
10482 case 'V':
10483 print_version_id ();
10484 break;
10485
a38cf1db
AM		 10486 /* -k: Ignore for FreeBSD compatibility. */
10487 case 'k':
252b5132 10488 break;
4cc782b5
ILT		 10489
10490 case 's':
10491 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10492 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10493 break;
8dcea932
L		 10494
10495 case OPTION_MSHARED:
10496 shared = 1;
10497 break;
99ad8390 10498#endif
321098a5 10499#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10500 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10501 case OPTION_64:
10502 {
10503 const char **list, **l;
10504
3e73aa7c
JH		 10505 list = bfd_target_list ();
10506 for (l = list; *l != NULL; l++)
8620418b 10507 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10508 || strcmp (*l, "coff-x86-64") == 0
10509 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10510 || strcmp (*l, "pei-x86-64") == 0
10511 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10512 {
10513 default_arch = "x86_64";
10514 break;
10515 }
3e73aa7c 10516 if (*l == NULL)
2b5d6a91 10517 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10518 free (list);
10519 }
10520 break;
10521#endif
252b5132 10522
351f65ca 10523#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10524 case OPTION_X32:
351f65ca
L		 10525 if (IS_ELF)
10526 {
10527 const char **list, **l;
10528
10529 list = bfd_target_list ();
10530 for (l = list; *l != NULL; l++)
10531 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10532 {
10533 default_arch = "x86_64:32";
10534 break;
10535 }
10536 if (*l == NULL)
2b5d6a91 10537 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10538 free (list);
10539 }
10540 else
10541 as_fatal (_("32bit x86_64 is only supported for ELF"));
10542 break;
10543#endif
10544
6e0b89ee
AM		 10545 case OPTION_32:
10546 default_arch = "i386";
10547 break;
10548
b3b91714
AM		 10549 case OPTION_DIVIDE:
10550#ifdef SVR4_COMMENT_CHARS
10551 {
10552 char *n, *t;
10553 const char *s;
10554
add39d23 10555 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10556 t = n;
10557 for (s = i386_comment_chars; *s != '\0'; s++)
10558 if (*s != '/')
10559 *t++ = *s;
10560 *t = '\0';
10561 i386_comment_chars = n;
10562 }
10563#endif
10564 break;
10565
9103f4f4 10566 case OPTION_MARCH:
293f5f65
L		 10567 saved = xstrdup (arg);
10568 arch = saved;
10569 /* Allow -march=+nosse. */
10570 if (*arch == '+')
10571 arch++;
6305a203 10572 do
9103f4f4 10573 {
6305a203 10574 if (*arch == '.')
2b5d6a91 10575 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10576 next = strchr (arch, '+');
10577 if (next)
10578 *next++ = '\0';
91d6fa6a 10579 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10580 {
91d6fa6a 10581 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10582 {
6305a203 10583 /* Processor. */
1ded5609
JB		 10584 if (! cpu_arch[j].flags.bitfield.cpui386)
10585 continue;
10586
91d6fa6a 10587 cpu_arch_name = cpu_arch[j].name;
6305a203 10588 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10589 cpu_arch_flags = cpu_arch[j].flags;
10590 cpu_arch_isa = cpu_arch[j].type;
10591 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10592 if (!cpu_arch_tune_set)
10593 {
10594 cpu_arch_tune = cpu_arch_isa;
10595 cpu_arch_tune_flags = cpu_arch_isa_flags;
10596 }
10597 break;
10598 }
91d6fa6a
NC		 10599 else if (*cpu_arch [j].name == '.'
10600 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10601 {
33eaf5de 10602 /* ISA extension. */
6305a203 10603 i386_cpu_flags flags;
309d3373 10604
293f5f65
L		 10605 flags = cpu_flags_or (cpu_arch_flags,
10606 cpu_arch[j].flags);
81486035 10607
5b64d091 10608 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10609 {
10610 if (cpu_sub_arch_name)
10611 {
10612 char *name = cpu_sub_arch_name;
10613 cpu_sub_arch_name = concat (name,
91d6fa6a 10614 cpu_arch[j].name,
1bf57e9f 10615 (const char *) NULL);
6305a203
L		 10616 free (name);
10617 }
10618 else
91d6fa6a 10619 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10620 cpu_arch_flags = flags;
a586129e 10621 cpu_arch_isa_flags = flags;
6305a203 10622 }
0089dace
L		 10623 else
10624 cpu_arch_isa_flags
10625 = cpu_flags_or (cpu_arch_isa_flags,
10626 cpu_arch[j].flags);
6305a203 10627 break;
ccc9c027 10628 }
9103f4f4 10629 }
6305a203 10630
293f5f65
L		 10631 if (j >= ARRAY_SIZE (cpu_arch))
10632 {
33eaf5de 10633 /* Disable an ISA extension. */
293f5f65
L		 10634 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10635 if (strcmp (arch, cpu_noarch [j].name) == 0)
10636 {
10637 i386_cpu_flags flags;
10638
10639 flags = cpu_flags_and_not (cpu_arch_flags,
10640 cpu_noarch[j].flags);
10641 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10642 {
10643 if (cpu_sub_arch_name)
10644 {
10645 char *name = cpu_sub_arch_name;
10646 cpu_sub_arch_name = concat (arch,
10647 (const char *) NULL);
10648 free (name);
10649 }
10650 else
10651 cpu_sub_arch_name = xstrdup (arch);
10652 cpu_arch_flags = flags;
10653 cpu_arch_isa_flags = flags;
10654 }
10655 break;
10656 }
10657
10658 if (j >= ARRAY_SIZE (cpu_noarch))
10659 j = ARRAY_SIZE (cpu_arch);
10660 }
10661
91d6fa6a 10662 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10663 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10664
10665 arch = next;
9103f4f4 10666 }
293f5f65
L		 10667 while (next != NULL);
10668 free (saved);
9103f4f4
L		 10669 break;
10670
10671 case OPTION_MTUNE:
10672 if (*arg == '.')
2b5d6a91 10673 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10674 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10675 {
91d6fa6a 10676 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10677 {
ccc9c027 10678 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10679 cpu_arch_tune = cpu_arch [j].type;
10680 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10681 break;
10682 }
10683 }
91d6fa6a 10684 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10685 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10686 break;
10687
1efbbeb4
L		 10688 case OPTION_MMNEMONIC:
10689 if (strcasecmp (arg, "att") == 0)
10690 intel_mnemonic = 0;
10691 else if (strcasecmp (arg, "intel") == 0)
10692 intel_mnemonic = 1;
10693 else
2b5d6a91 10694 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10695 break;
10696
10697 case OPTION_MSYNTAX:
10698 if (strcasecmp (arg, "att") == 0)
10699 intel_syntax = 0;
10700 else if (strcasecmp (arg, "intel") == 0)
10701 intel_syntax = 1;
10702 else
2b5d6a91 10703 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10704 break;
10705
10706 case OPTION_MINDEX_REG:
10707 allow_index_reg = 1;
10708 break;
10709
10710 case OPTION_MNAKED_REG:
10711 allow_naked_reg = 1;
10712 break;
10713
c0f3af97
L		 10714 case OPTION_MSSE2AVX:
10715 sse2avx = 1;
10716 break;
10717
daf50ae7
L		 10718 case OPTION_MSSE_CHECK:
10719 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10720 sse_check = check_error;
daf50ae7 10721 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10722 sse_check = check_warning;
daf50ae7 10723 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10724 sse_check = check_none;
daf50ae7 10725 else
2b5d6a91 10726 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10727 break;
10728
7bab8ab5
JB		 10729 case OPTION_MOPERAND_CHECK:
10730 if (strcasecmp (arg, "error") == 0)
10731 operand_check = check_error;
10732 else if (strcasecmp (arg, "warning") == 0)
10733 operand_check = check_warning;
10734 else if (strcasecmp (arg, "none") == 0)
10735 operand_check = check_none;
10736 else
10737 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10738 break;
10739
539f890d
L		 10740 case OPTION_MAVXSCALAR:
10741 if (strcasecmp (arg, "128") == 0)
10742 avxscalar = vex128;
10743 else if (strcasecmp (arg, "256") == 0)
10744 avxscalar = vex256;
10745 else
2b5d6a91 10746 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10747 break;
10748
7e8b059b
L		 10749 case OPTION_MADD_BND_PREFIX:
10750 add_bnd_prefix = 1;
10751 break;
10752
43234a1e
L		 10753 case OPTION_MEVEXLIG:
10754 if (strcmp (arg, "128") == 0)
10755 evexlig = evexl128;
10756 else if (strcmp (arg, "256") == 0)
10757 evexlig = evexl256;
10758 else if (strcmp (arg, "512") == 0)
10759 evexlig = evexl512;
10760 else
10761 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10762 break;
10763
d3d3c6db
IT		 10764 case OPTION_MEVEXRCIG:
10765 if (strcmp (arg, "rne") == 0)
10766 evexrcig = rne;
10767 else if (strcmp (arg, "rd") == 0)
10768 evexrcig = rd;
10769 else if (strcmp (arg, "ru") == 0)
10770 evexrcig = ru;
10771 else if (strcmp (arg, "rz") == 0)
10772 evexrcig = rz;
10773 else
10774 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10775 break;
10776
43234a1e
L		 10777 case OPTION_MEVEXWIG:
10778 if (strcmp (arg, "0") == 0)
10779 evexwig = evexw0;
10780 else if (strcmp (arg, "1") == 0)
10781 evexwig = evexw1;
10782 else
10783 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10784 break;
10785
167ad85b
TG		 10786# if defined (TE_PE) || defined (TE_PEP)
10787 case OPTION_MBIG_OBJ:
10788 use_big_obj = 1;
10789 break;
10790#endif
10791
d1982f93 10792 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10793 if (strcasecmp (arg, "yes") == 0)
10794 omit_lock_prefix = 1;
10795 else if (strcasecmp (arg, "no") == 0)
10796 omit_lock_prefix = 0;
10797 else
10798 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10799 break;
10800
e4e00185
AS		 10801 case OPTION_MFENCE_AS_LOCK_ADD:
10802 if (strcasecmp (arg, "yes") == 0)
10803 avoid_fence = 1;
10804 else if (strcasecmp (arg, "no") == 0)
10805 avoid_fence = 0;
10806 else
10807 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10808 break;
10809
0cb4071e
L		 10810 case OPTION_MRELAX_RELOCATIONS:
10811 if (strcasecmp (arg, "yes") == 0)
10812 generate_relax_relocations = 1;
10813 else if (strcasecmp (arg, "no") == 0)
10814 generate_relax_relocations = 0;
10815 else
10816 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10817 break;
10818
5db04b09 10819 case OPTION_MAMD64:
e89c5eaa 10820 intel64 = 0;
5db04b09
L		 10821 break;
10822
10823 case OPTION_MINTEL64:
e89c5eaa 10824 intel64 = 1;
5db04b09
L		 10825 break;
10826
b6f8c7c4
L		 10827 case 'O':
10828 if (arg == NULL)
10829 {
10830 optimize = 1;
10831 /* Turn off -Os. */
10832 optimize_for_space = 0;
10833 }
10834 else if (*arg == 's')
10835 {
10836 optimize_for_space = 1;
10837 /* Turn on all encoding optimizations. */
10838 optimize = -1;
10839 }
10840 else
10841 {
10842 optimize = atoi (arg);
10843 /* Turn off -Os. */
10844 optimize_for_space = 0;
10845 }
10846 break;
10847
252b5132
RH		 10848 default:
10849 return 0;
10850 }
10851 return 1;
10852}
10853
8a2c8fef
L		 10854#define MESSAGE_TEMPLATE \
10855" "
10856
293f5f65
L		 10857static char *
10858output_message (FILE *stream, char *p, char *message, char *start,
10859 int *left_p, const char *name, int len)
10860{
10861 int size = sizeof (MESSAGE_TEMPLATE);
10862 int left = *left_p;
10863
10864 /* Reserve 2 spaces for ", " or ",\0" */
10865 left -= len + 2;
10866
10867 /* Check if there is any room. */
10868 if (left >= 0)
10869 {
10870 if (p != start)
10871 {
10872 *p++ = ',';
10873 *p++ = ' ';
10874 }
10875 p = mempcpy (p, name, len);
10876 }
10877 else
10878 {
10879 /* Output the current message now and start a new one. */
10880 *p++ = ',';
10881 *p = '\0';
10882 fprintf (stream, "%s\n", message);
10883 p = start;
10884 left = size - (start - message) - len - 2;
10885
10886 gas_assert (left >= 0);
10887
10888 p = mempcpy (p, name, len);
10889 }
10890
10891 *left_p = left;
10892 return p;
10893}
10894
8a2c8fef 10895static void
1ded5609 10896show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10897{
10898 static char message[] = MESSAGE_TEMPLATE;
10899 char *start = message + 27;
10900 char *p;
10901 int size = sizeof (MESSAGE_TEMPLATE);
10902 int left;
10903 const char *name;
10904 int len;
10905 unsigned int j;
10906
10907 p = start;
10908 left = size - (start - message);
10909 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10910 {
10911 /* Should it be skipped? */
10912 if (cpu_arch [j].skip)
10913 continue;
10914
10915 name = cpu_arch [j].name;
10916 len = cpu_arch [j].len;
10917 if (*name == '.')
10918 {
10919 /* It is an extension. Skip if we aren't asked to show it. */
10920 if (ext)
10921 {
10922 name++;
10923 len--;
10924 }
10925 else
10926 continue;
10927 }
10928 else if (ext)
10929 {
10930 /* It is an processor. Skip if we show only extension. */
10931 continue;
10932 }
1ded5609
JB		 10933 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10934 {
10935 /* It is an impossible processor - skip. */
10936 continue;
10937 }
8a2c8fef 10938
293f5f65 10939 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10940 }
10941
293f5f65
L		 10942 /* Display disabled extensions. */
10943 if (ext)
10944 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10945 {
10946 name = cpu_noarch [j].name;
10947 len = cpu_noarch [j].len;
10948 p = output_message (stream, p, message, start, &left, name,
10949 len);
10950 }
10951
8a2c8fef
L		 10952 *p = '\0';
10953 fprintf (stream, "%s\n", message);
10954}
10955
252b5132 10956void
8a2c8fef 10957md_show_usage (FILE *stream)
252b5132 10958{
4cc782b5
ILT		 10959#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10960 fprintf (stream, _("\
a38cf1db
AM		 10961 -Q ignored\n\
10962 -V print assembler version number\n\
b3b91714
AM		 10963 -k ignored\n"));
10964#endif
10965 fprintf (stream, _("\
12b55ccc 10966 -n Do not optimize code alignment\n\
b3b91714
AM		 10967 -q quieten some warnings\n"));
10968#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10969 fprintf (stream, _("\
a38cf1db 10970 -s ignored\n"));
b3b91714 10971#endif
321098a5
L		 10972#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10973 || defined (TE_PE) || defined (TE_PEP))
751d281c 10974 fprintf (stream, _("\
570561f7 10975 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10976#endif
b3b91714
AM		 10977#ifdef SVR4_COMMENT_CHARS
10978 fprintf (stream, _("\
10979 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10980#else
10981 fprintf (stream, _("\
b3b91714 10982 --divide ignored\n"));
4cc782b5 10983#endif
9103f4f4 10984 fprintf (stream, _("\
6305a203 10985 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10986 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10987 show_arch (stream, 0, 1);
8a2c8fef
L		 10988 fprintf (stream, _("\
10989 EXTENSION is combination of:\n"));
1ded5609 10990 show_arch (stream, 1, 0);
6305a203 10991 fprintf (stream, _("\
8a2c8fef 10992 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10993 show_arch (stream, 0, 0);
ba104c83 10994 fprintf (stream, _("\
c0f3af97
L		 10995 -msse2avx encode SSE instructions with VEX prefix\n"));
10996 fprintf (stream, _("\
daf50ae7
L		 10997 -msse-check=[none|error|warning]\n\
10998 check SSE instructions\n"));
10999 fprintf (stream, _("\
7bab8ab5
JB		 11000 -moperand-check=[none|error|warning]\n\
11001 check operand combinations for validity\n"));
11002 fprintf (stream, _("\
539f890d
L		 11003 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11004 length\n"));
11005 fprintf (stream, _("\
43234a1e
L		 11006 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11007 length\n"));
11008 fprintf (stream, _("\
11009 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11010 for EVEX.W bit ignored instructions\n"));
11011 fprintf (stream, _("\
d3d3c6db
IT		 11012 -mevexrcig=[rne|rd|ru|rz]\n\
11013 encode EVEX instructions with specific EVEX.RC value\n\
11014 for SAE-only ignored instructions\n"));
11015 fprintf (stream, _("\
ba104c83
L		 11016 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11017 fprintf (stream, _("\
11018 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11019 fprintf (stream, _("\
11020 -mindex-reg support pseudo index registers\n"));
11021 fprintf (stream, _("\
11022 -mnaked-reg don't require `%%' prefix for registers\n"));
11023 fprintf (stream, _("\
7e8b059b 11024 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 11025 fprintf (stream, _("\
11026 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 11027# if defined (TE_PE) || defined (TE_PEP)
11028 fprintf (stream, _("\
11029 -mbig-obj generate big object files\n"));
11030#endif
d022bddd
IT		 11031 fprintf (stream, _("\
11032 -momit-lock-prefix=[no|yes]\n\
11033 strip all lock prefixes\n"));
5db04b09 11034 fprintf (stream, _("\
e4e00185
AS		 11035 -mfence-as-lock-add=[no|yes]\n\
11036 encode lfence, mfence and sfence as\n\
11037 lock addl $0x0, (%%{re}sp)\n"));
11038 fprintf (stream, _("\
0cb4071e
L		 11039 -mrelax-relocations=[no|yes]\n\
11040 generate relax relocations\n"));
11041 fprintf (stream, _("\
5db04b09
L		 11042 -mamd64 accept only AMD64 ISA\n"));
11043 fprintf (stream, _("\
11044 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 11045}
11046
3e73aa7c 11047#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11048 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11049 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11050
11051/* Pick the target format to use. */
11052
47926f60 11053const char *
e3bb37b5 11054i386_target_format (void)
252b5132 11055{
351f65ca
L		 11056 if (!strncmp (default_arch, "x86_64", 6))
11057 {
11058 update_code_flag (CODE_64BIT, 1);
11059 if (default_arch[6] == '\0')
7f56bc95 11060 x86_elf_abi = X86_64_ABI;
351f65ca 11061 else
7f56bc95 11062 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11063 }
3e73aa7c 11064 else if (!strcmp (default_arch, "i386"))
78f12dd3 11065 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11066 else if (!strcmp (default_arch, "iamcu"))
11067 {
11068 update_code_flag (CODE_32BIT, 1);
11069 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11070 {
11071 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11072 cpu_arch_name = "iamcu";
11073 cpu_sub_arch_name = NULL;
11074 cpu_arch_flags = iamcu_flags;
11075 cpu_arch_isa = PROCESSOR_IAMCU;
11076 cpu_arch_isa_flags = iamcu_flags;
11077 if (!cpu_arch_tune_set)
11078 {
11079 cpu_arch_tune = cpu_arch_isa;
11080 cpu_arch_tune_flags = cpu_arch_isa_flags;
11081 }
11082 }
8d471ec1 11083 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11084 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11085 cpu_arch_name);
11086 }
3e73aa7c 11087 else
2b5d6a91 11088 as_fatal (_("unknown architecture"));
89507696
JB		 11089
11090 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11091 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11092 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11093 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11094
252b5132
RH		 11095 switch (OUTPUT_FLAVOR)
11096 {
9384f2ff 11097#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11098 case bfd_target_aout_flavour:
47926f60 11099 return AOUT_TARGET_FORMAT;
4c63da97 11100#endif
9384f2ff
AM		 11101#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11102# if defined (TE_PE) || defined (TE_PEP)
11103 case bfd_target_coff_flavour:
167ad85b
TG		 11104 if (flag_code == CODE_64BIT)
11105 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11106 else
11107 return "pe-i386";
9384f2ff 11108# elif defined (TE_GO32)
0561d57c
JK		 11109 case bfd_target_coff_flavour:
11110 return "coff-go32";
9384f2ff 11111# else
252b5132
RH		 11112 case bfd_target_coff_flavour:
11113 return "coff-i386";
9384f2ff 11114# endif
4c63da97 11115#endif
3e73aa7c 11116#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11117 case bfd_target_elf_flavour:
3e73aa7c 11118 {
351f65ca
L		 11119 const char *format;
11120
11121 switch (x86_elf_abi)
4fa24527 11122 {
351f65ca
L		 11123 default:
11124 format = ELF_TARGET_FORMAT;
11125 break;
7f56bc95 11126 case X86_64_ABI:
351f65ca 11127 use_rela_relocations = 1;
4fa24527 11128 object_64bit = 1;
351f65ca
L		 11129 format = ELF_TARGET_FORMAT64;
11130 break;
7f56bc95 11131 case X86_64_X32_ABI:
4fa24527 11132 use_rela_relocations = 1;
351f65ca 11133 object_64bit = 1;
862be3fb 11134 disallow_64bit_reloc = 1;
351f65ca
L		 11135 format = ELF_TARGET_FORMAT32;
11136 break;
4fa24527 11137 }
3632d14b 11138 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11139 {
7f56bc95 11140 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11141 as_fatal (_("Intel L1OM is 64bit only"));
11142 return ELF_TARGET_L1OM_FORMAT;
11143 }
b49f93f6 11144 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11145 {
11146 if (x86_elf_abi != X86_64_ABI)
11147 as_fatal (_("Intel K1OM is 64bit only"));
11148 return ELF_TARGET_K1OM_FORMAT;
11149 }
81486035
L		 11150 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11151 {
11152 if (x86_elf_abi != I386_ABI)
11153 as_fatal (_("Intel MCU is 32bit only"));
11154 return ELF_TARGET_IAMCU_FORMAT;
11155 }
8a9036a4 11156 else
351f65ca 11157 return format;
3e73aa7c 11158 }
e57f8c65
TG		 11159#endif
11160#if defined (OBJ_MACH_O)
11161 case bfd_target_mach_o_flavour:
d382c579
TG		 11162 if (flag_code == CODE_64BIT)
11163 {
11164 use_rela_relocations = 1;
11165 object_64bit = 1;
11166 return "mach-o-x86-64";
11167 }
11168 else
11169 return "mach-o-i386";
4c63da97 11170#endif
252b5132
RH		 11171 default:
11172 abort ();
11173 return NULL;
11174 }
11175}
11176
47926f60 11177#endif /* OBJ_MAYBE_ more than one */
252b5132 11178\f
252b5132 11179symbolS *
7016a5d5 11180md_undefined_symbol (char *name)
252b5132 11181{
18dc2407
ILT		 11182 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11183 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11184 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11185 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11186 {
11187 if (!GOT_symbol)
11188 {
11189 if (symbol_find (name))
11190 as_bad (_("GOT already in symbol table"));
11191 GOT_symbol = symbol_new (name, undefined_section,
11192 (valueT) 0, &zero_address_frag);
11193 };
11194 return GOT_symbol;
11195 }
252b5132
RH		 11196 return 0;
11197}
11198
11199/* Round up a section size to the appropriate boundary. */
47926f60 11200
252b5132 11201valueT
7016a5d5 11202md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11203{
4c63da97
AM		 11204#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11205 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11206 {
11207 /* For a.out, force the section size to be aligned. If we don't do
11208 this, BFD will align it for us, but it will not write out the
11209 final bytes of the section. This may be a bug in BFD, but it is
11210 easier to fix it here since that is how the other a.out targets
11211 work. */
11212 int align;
11213
11214 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11215 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11216 }
252b5132
RH		 11217#endif
11218
11219 return size;
11220}
11221
11222/* On the i386, PC-relative offsets are relative to the start of the
11223 next instruction. That is, the address of the offset, plus its
11224 size, since the offset is always the last part of the insn. */
11225
11226long
e3bb37b5 11227md_pcrel_from (fixS *fixP)
252b5132
RH		 11228{
11229 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11230}
11231
11232#ifndef I386COFF
11233
11234static void
e3bb37b5 11235s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11236{
29b0f896 11237 int temp;
252b5132 11238
8a75718c
JB		 11239#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11240 if (IS_ELF)
11241 obj_elf_section_change_hook ();
11242#endif
252b5132
RH		 11243 temp = get_absolute_expression ();
11244 subseg_set (bss_section, (subsegT) temp);
11245 demand_empty_rest_of_line ();
11246}
11247
11248#endif
11249
252b5132 11250void
e3bb37b5 11251i386_validate_fix (fixS *fixp)
252b5132 11252{
02a86693 11253 if (fixp->fx_subsy)
252b5132 11254 {
02a86693 11255 if (fixp->fx_subsy == GOT_symbol)
23df1078 11256 {
02a86693
L		 11257 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11258 {
11259 if (!object_64bit)
11260 abort ();
11261#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11262 if (fixp->fx_tcbit2)
56ceb5b5
L		 11263 fixp->fx_r_type = (fixp->fx_tcbit
11264 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11265 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11266 else
11267#endif
11268 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11269 }
d6ab8113 11270 else
02a86693
L		 11271 {
11272 if (!object_64bit)
11273 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11274 else
11275 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11276 }
11277 fixp->fx_subsy = 0;
23df1078 11278 }
252b5132 11279 }
02a86693
L		 11280#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11281 else if (!object_64bit)
11282 {
11283 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11284 && fixp->fx_tcbit2)
11285 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11286 }
11287#endif
252b5132
RH		 11288}
11289
252b5132 11290arelent *
7016a5d5 11291tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11292{
11293 arelent *rel;
11294 bfd_reloc_code_real_type code;
11295
11296 switch (fixp->fx_r_type)
11297 {
8ce3d284 11298#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11299 case BFD_RELOC_SIZE32:
11300 case BFD_RELOC_SIZE64:
11301 if (S_IS_DEFINED (fixp->fx_addsy)
11302 && !S_IS_EXTERNAL (fixp->fx_addsy))
11303 {
11304 /* Resolve size relocation against local symbol to size of
11305 the symbol plus addend. */
11306 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11307 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11308 && !fits_in_unsigned_long (value))
11309 as_bad_where (fixp->fx_file, fixp->fx_line,
11310 _("symbol size computation overflow"));
11311 fixp->fx_addsy = NULL;
11312 fixp->fx_subsy = NULL;
11313 md_apply_fix (fixp, (valueT *) &value, NULL);
11314 return NULL;
11315 }
8ce3d284 11316#endif
1a0670f3 11317 /* Fall through. */
8fd4256d 11318
3e73aa7c
JH		 11319 case BFD_RELOC_X86_64_PLT32:
11320 case BFD_RELOC_X86_64_GOT32:
11321 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11322 case BFD_RELOC_X86_64_GOTPCRELX:
11323 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11324 case BFD_RELOC_386_PLT32:
11325 case BFD_RELOC_386_GOT32:
02a86693 11326 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11327 case BFD_RELOC_386_GOTOFF:
11328 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11329 case BFD_RELOC_386_TLS_GD:
11330 case BFD_RELOC_386_TLS_LDM:
11331 case BFD_RELOC_386_TLS_LDO_32:
11332 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11333 case BFD_RELOC_386_TLS_IE:
11334 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11335 case BFD_RELOC_386_TLS_LE_32:
11336 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11337 case BFD_RELOC_386_TLS_GOTDESC:
11338 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11339 case BFD_RELOC_X86_64_TLSGD:
11340 case BFD_RELOC_X86_64_TLSLD:
11341 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11342 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11343 case BFD_RELOC_X86_64_GOTTPOFF:
11344 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11345 case BFD_RELOC_X86_64_TPOFF64:
11346 case BFD_RELOC_X86_64_GOTOFF64:
11347 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11348 case BFD_RELOC_X86_64_GOT64:
11349 case BFD_RELOC_X86_64_GOTPCREL64:
11350 case BFD_RELOC_X86_64_GOTPC64:
11351 case BFD_RELOC_X86_64_GOTPLT64:
11352 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11353 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11354 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11355 case BFD_RELOC_RVA:
11356 case BFD_RELOC_VTABLE_ENTRY:
11357 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11358#ifdef TE_PE
11359 case BFD_RELOC_32_SECREL:
11360#endif
252b5132
RH		 11361 code = fixp->fx_r_type;
11362 break;
dbbaec26
L		 11363 case BFD_RELOC_X86_64_32S:
11364 if (!fixp->fx_pcrel)
11365 {
11366 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11367 code = fixp->fx_r_type;
11368 break;
11369 }
1a0670f3 11370 /* Fall through. */
252b5132 11371 default:
93382f6d 11372 if (fixp->fx_pcrel)
252b5132 11373 {
93382f6d
AM		 11374 switch (fixp->fx_size)
11375 {
11376 default:
b091f402
AM		 11377 as_bad_where (fixp->fx_file, fixp->fx_line,
11378 _("can not do %d byte pc-relative relocation"),
11379 fixp->fx_size);
93382f6d
AM		 11380 code = BFD_RELOC_32_PCREL;
11381 break;
11382 case 1: code = BFD_RELOC_8_PCREL; break;
11383 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11384 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11385#ifdef BFD64
11386 case 8: code = BFD_RELOC_64_PCREL; break;
11387#endif
93382f6d
AM		 11388 }
11389 }
11390 else
11391 {
11392 switch (fixp->fx_size)
11393 {
11394 default:
b091f402
AM		 11395 as_bad_where (fixp->fx_file, fixp->fx_line,
11396 _("can not do %d byte relocation"),
11397 fixp->fx_size);
93382f6d
AM		 11398 code = BFD_RELOC_32;
11399 break;
11400 case 1: code = BFD_RELOC_8; break;
11401 case 2: code = BFD_RELOC_16; break;
11402 case 4: code = BFD_RELOC_32; break;
937149dd 11403#ifdef BFD64
3e73aa7c 11404 case 8: code = BFD_RELOC_64; break;
937149dd 11405#endif
93382f6d 11406 }
252b5132
RH		 11407 }
11408 break;
11409 }
252b5132 11410
d182319b
JB		 11411 if ((code == BFD_RELOC_32
11412 || code == BFD_RELOC_32_PCREL
11413 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11414 && GOT_symbol
11415 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11416 {
4fa24527 11417 if (!object_64bit)
d6ab8113
JB		 11418 code = BFD_RELOC_386_GOTPC;
11419 else
11420 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11421 }
7b81dfbb
AJ		 11422 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11423 && GOT_symbol
11424 && fixp->fx_addsy == GOT_symbol)
11425 {
11426 code = BFD_RELOC_X86_64_GOTPC64;
11427 }
252b5132 11428
add39d23
TS		 11429 rel = XNEW (arelent);
11430 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11431 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11432
11433 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11434
3e73aa7c
JH		 11435 if (!use_rela_relocations)
11436 {
11437 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11438 vtable entry to be used in the relocation's section offset. */
11439 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11440 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11441#if defined (OBJ_COFF) && defined (TE_PE)
11442 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11443 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11444 else
11445#endif
c6682705 11446 rel->addend = 0;
3e73aa7c
JH		 11447 }
11448 /* Use the rela in 64bit mode. */
252b5132 11449 else
3e73aa7c 11450 {
862be3fb
L		 11451 if (disallow_64bit_reloc)
11452 switch (code)
11453 {
862be3fb
L		 11454 case BFD_RELOC_X86_64_DTPOFF64:
11455 case BFD_RELOC_X86_64_TPOFF64:
11456 case BFD_RELOC_64_PCREL:
11457 case BFD_RELOC_X86_64_GOTOFF64:
11458 case BFD_RELOC_X86_64_GOT64:
11459 case BFD_RELOC_X86_64_GOTPCREL64:
11460 case BFD_RELOC_X86_64_GOTPC64:
11461 case BFD_RELOC_X86_64_GOTPLT64:
11462 case BFD_RELOC_X86_64_PLTOFF64:
11463 as_bad_where (fixp->fx_file, fixp->fx_line,
11464 _("cannot represent relocation type %s in x32 mode"),
11465 bfd_get_reloc_code_name (code));
11466 break;
11467 default:
11468 break;
11469 }
11470
062cd5e7
AS		 11471 if (!fixp->fx_pcrel)
11472 rel->addend = fixp->fx_offset;
11473 else
11474 switch (code)
11475 {
11476 case BFD_RELOC_X86_64_PLT32:
11477 case BFD_RELOC_X86_64_GOT32:
11478 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11479 case BFD_RELOC_X86_64_GOTPCRELX:
11480 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11481 case BFD_RELOC_X86_64_TLSGD:
11482 case BFD_RELOC_X86_64_TLSLD:
11483 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11484 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11485 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11486 rel->addend = fixp->fx_offset - fixp->fx_size;
11487 break;
11488 default:
11489 rel->addend = (section->vma
11490 - fixp->fx_size
11491 + fixp->fx_addnumber
11492 + md_pcrel_from (fixp));
11493 break;
11494 }
3e73aa7c
JH		 11495 }
11496
252b5132
RH		 11497 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11498 if (rel->howto == NULL)
11499 {
11500 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11501 _("cannot represent relocation type %s"),
252b5132
RH		 11502 bfd_get_reloc_code_name (code));
11503 /* Set howto to a garbage value so that we can keep going. */
11504 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11505 gas_assert (rel->howto != NULL);
252b5132
RH		 11506 }
11507
11508 return rel;
11509}
11510
ee86248c 11511#include "tc-i386-intel.c"
54cfded0 11512
a60de03c
JB		 11513void
11514tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11515{
a60de03c
JB		 11516 int saved_naked_reg;
11517 char saved_register_dot;
54cfded0 11518
a60de03c
JB		 11519 saved_naked_reg = allow_naked_reg;
11520 allow_naked_reg = 1;
11521 saved_register_dot = register_chars['.'];
11522 register_chars['.'] = '.';
11523 allow_pseudo_reg = 1;
11524 expression_and_evaluate (exp);
11525 allow_pseudo_reg = 0;
11526 register_chars['.'] = saved_register_dot;
11527 allow_naked_reg = saved_naked_reg;
11528
e96d56a1 11529 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11530 {
a60de03c
JB		 11531 if ((addressT) exp->X_add_number < i386_regtab_size)
11532 {
11533 exp->X_op = O_constant;
11534 exp->X_add_number = i386_regtab[exp->X_add_number]
11535 .dw2_regnum[flag_code >> 1];
11536 }
11537 else
11538 exp->X_op = O_illegal;
54cfded0 11539 }
54cfded0
AM		 11540}
11541
11542void
11543tc_x86_frame_initial_instructions (void)
11544{
a60de03c
JB		 11545 static unsigned int sp_regno[2];
11546
11547 if (!sp_regno[flag_code >> 1])
11548 {
11549 char *saved_input = input_line_pointer;
11550 char sp[][4] = {"esp", "rsp"};
11551 expressionS exp;
a4447b93 11552
a60de03c
JB		 11553 input_line_pointer = sp[flag_code >> 1];
11554 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11555 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11556 sp_regno[flag_code >> 1] = exp.X_add_number;
11557 input_line_pointer = saved_input;
11558 }
a4447b93 11559
61ff971f
L		 11560 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11561 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11562}
d2b2c203 11563
d7921315
L		 11564int
11565x86_dwarf2_addr_size (void)
11566{
11567#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11568 if (x86_elf_abi == X86_64_X32_ABI)
11569 return 4;
11570#endif
11571 return bfd_arch_bits_per_address (stdoutput) / 8;
11572}
11573
d2b2c203
DJ		 11574int
11575i386_elf_section_type (const char *str, size_t len)
11576{
11577 if (flag_code == CODE_64BIT
11578 && len == sizeof ("unwind") - 1
11579 && strncmp (str, "unwind", 6) == 0)
11580 return SHT_X86_64_UNWIND;
11581
11582 return -1;
11583}
bb41ade5 11584
ad5fec3b
EB		 11585#ifdef TE_SOLARIS
11586void
11587i386_solaris_fix_up_eh_frame (segT sec)
11588{
11589 if (flag_code == CODE_64BIT)
11590 elf_section_type (sec) = SHT_X86_64_UNWIND;
11591}
11592#endif
11593
bb41ade5
AM		 11594#ifdef TE_PE
11595void
11596tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11597{
91d6fa6a 11598 expressionS exp;
bb41ade5 11599
91d6fa6a
NC		 11600 exp.X_op = O_secrel;
11601 exp.X_add_symbol = symbol;
11602 exp.X_add_number = 0;
11603 emit_expr (&exp, size);
bb41ade5
AM		 11604}
11605#endif
3b22753a
L		 11606
11607#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11608/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11609
01e1a5bc 11610bfd_vma
6d4af3c2 11611x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11612{
11613 if (flag_code == CODE_64BIT)
11614 {
11615 if (letter == 'l')
11616 return SHF_X86_64_LARGE;
11617
8f3bae45 11618 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11619 }
3b22753a 11620 else
8f3bae45 11621 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11622 return -1;
11623}
11624
01e1a5bc 11625bfd_vma
3b22753a
L		 11626x86_64_section_word (char *str, size_t len)
11627{
8620418b 11628 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11629 return SHF_X86_64_LARGE;
11630
11631 return -1;
11632}
11633
11634static void
11635handle_large_common (int small ATTRIBUTE_UNUSED)
11636{
11637 if (flag_code != CODE_64BIT)
11638 {
11639 s_comm_internal (0, elf_common_parse);
11640 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11641 }
11642 else
11643 {
11644 static segT lbss_section;
11645 asection *saved_com_section_ptr = elf_com_section_ptr;
11646 asection *saved_bss_section = bss_section;
11647
11648 if (lbss_section == NULL)
11649 {
11650 flagword applicable;
11651 segT seg = now_seg;
11652 subsegT subseg = now_subseg;
11653
11654 /* The .lbss section is for local .largecomm symbols. */
11655 lbss_section = subseg_new (".lbss", 0);
11656 applicable = bfd_applicable_section_flags (stdoutput);
11657 bfd_set_section_flags (stdoutput, lbss_section,
11658 applicable & SEC_ALLOC);
11659 seg_info (lbss_section)->bss = 1;
11660
11661 subseg_set (seg, subseg);
11662 }
11663
11664 elf_com_section_ptr = &_bfd_elf_large_com_section;
11665 bss_section = lbss_section;
11666
11667 s_comm_internal (0, elf_common_parse);
11668
11669 elf_com_section_ptr = saved_com_section_ptr;
11670 bss_section = saved_bss_section;
11671 }
11672}
11673#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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