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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
185#endif
252b5132 186
a847613f 187static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 188
c0f3af97
L		 189/* VEX prefix. */
190typedef struct
191{
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes[3];
194 unsigned int length;
195 /* Destination or source register specifier. */
196 const reg_entry *register_specifier;
197} vex_prefix;
198
252b5132 199/* 'md_assemble ()' gathers together information and puts it into a
47926f60 200 i386_insn. */
252b5132 201
520dc8e8
AM		 202union i386_op
203 {
204 expressionS *disps;
205 expressionS *imms;
206 const reg_entry *regs;
207 };
208
a65babc9
L		 209enum i386_error
210 {
86e026a4 211 operand_size_mismatch,
a65babc9
L		 212 operand_type_mismatch,
213 register_type_mismatch,
214 number_of_operands_mismatch,
215 invalid_instruction_suffix,
216 bad_imm4,
217 old_gcc_only,
218 unsupported_with_intel_mnemonic,
219 unsupported_syntax,
220 unsupported
221 };
222
252b5132
RH		 223struct _i386_insn
224 {
47926f60 225 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 226 insn_template tm;
252b5132 227
7d5e4556
L		 228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
252b5132
RH		 230 char suffix;
231
47926f60 232 /* OPERANDS gives the number of given operands. */
252b5132
RH		 233 unsigned int operands;
234
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
47926f60 237 operands. */
252b5132
RH		 238 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
239
240 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 241 use OP[i] for the corresponding operand. */
40fb9820 242 i386_operand_type types[MAX_OPERANDS];
252b5132 243
520dc8e8
AM		 244 /* Displacement expression, immediate expression, or register for each
245 operand. */
246 union i386_op op[MAX_OPERANDS];
252b5132 247
3e73aa7c
JH		 248 /* Flags for operands. */
249 unsigned int flags[MAX_OPERANDS];
250#define Operand_PCrel 1
251
252b5132 252 /* Relocation type for operand */
f86103b7 253 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 254
252b5132
RH		 255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry *base_reg;
258 const reg_entry *index_reg;
259 unsigned int log2_scale_factor;
260
261 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 262 explicit segment overrides are given. */
ce8a8b2f 263 const seg_entry *seg[2];
252b5132
RH		 264
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes;
268 unsigned char prefix[MAX_PREFIXES];
269
270 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 271 addressing modes of this insn are encoded. */
252b5132 272 modrm_byte rm;
3e73aa7c 273 rex_byte rex;
252b5132 274 sib_byte sib;
c0f3af97 275 vex_prefix vex;
b6169b20
L		 276
277 /* Swap operand in encoding. */
4473e004 278 unsigned int swap_operand;
891edac4 279
f8a5c266
L		 280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding;
282
891edac4 283 /* Error message. */
a65babc9 284 enum i386_error error;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896 305 && !defined (TE_FreeBSD) \
5b806d27 306 && !defined (TE_DragonFly) \
29b0f896 307 && !defined (TE_NetBSD)))
252b5132 308/* This array holds the chars that always start a comment. If the
b3b91714
AM		 309 pre-processor is disabled, these aren't very useful. The option
310 --divide will remove '/' from this list. */
311const char *i386_comment_chars = "#/";
312#define SVR4_COMMENT_CHARS 1
252b5132 313#define PREFIX_SEPARATOR '\\'
252b5132 314
b3b91714
AM		 315#else
316const char *i386_comment_chars = "#";
317#define PREFIX_SEPARATOR '/'
318#endif
319
252b5132
RH		 320/* This array holds the chars that only start a comment at the beginning of
321 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 322 .line and .file directives will appear in the pre-processed output.
323 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 324 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 325 #NO_APP at the beginning of its output.
326 Also note that comments started like this one will always work if
252b5132 327 '/' isn't otherwise defined. */
b3b91714 328const char line_comment_chars[] = "#/";
252b5132 329
63a0b638 330const char line_separator_chars[] = ";";
252b5132 331
ce8a8b2f
AM		 332/* Chars that can be used to separate mant from exp in floating point
333 nums. */
252b5132
RH		 334const char EXP_CHARS[] = "eE";
335
ce8a8b2f
AM		 336/* Chars that mean this number is a floating point constant
337 As in 0f12.456
338 or 0d1.2345e12. */
252b5132
RH		 339const char FLT_CHARS[] = "fFdDxX";
340
ce8a8b2f 341/* Tables for lexical analysis. */
252b5132
RH		 342static char mnemonic_chars[256];
343static char register_chars[256];
344static char operand_chars[256];
345static char identifier_chars[256];
346static char digit_chars[256];
347
ce8a8b2f 348/* Lexical macros. */
252b5132
RH		 349#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
350#define is_operand_char(x) (operand_chars[(unsigned char) x])
351#define is_register_char(x) (register_chars[(unsigned char) x])
352#define is_space_char(x) ((x) == ' ')
353#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
354#define is_digit_char(x) (digit_chars[(unsigned char) x])
355
0234cb7c 356/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 357static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
358
359/* md_assemble() always leaves the strings it's passed unaltered. To
360 effect this we maintain a stack of saved characters that we've smashed
361 with '\0's (indicating end of strings for various sub-fields of the
47926f60 362 assembler instruction). */
252b5132 363static char save_stack[32];
ce8a8b2f 364static char *save_stack_p;
252b5132
RH		 365#define END_STRING_AND_SAVE(s) \
366 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
367#define RESTORE_END_STRING(s) \
368 do { *(s) = *--save_stack_p; } while (0)
369
47926f60 370/* The instruction we're assembling. */
252b5132
RH		 371static i386_insn i;
372
373/* Possible templates for current insn. */
374static const templates *current_templates;
375
31b2323c
L		 376/* Per instruction expressionS buffers: max displacements & immediates. */
377static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
378static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 379
47926f60 380/* Current operand we are working on. */
ee86248c 381static int this_operand = -1;
252b5132 382
3e73aa7c
JH		 383/* We support four different modes. FLAG_CODE variable is used to distinguish
384 these. */
385
386enum flag_code {
387 CODE_32BIT,
388 CODE_16BIT,
389 CODE_64BIT };
390
391static enum flag_code flag_code;
4fa24527 392static unsigned int object_64bit;
862be3fb 393static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 394static int use_rela_relocations = 0;
395
7af8ed2d
NC		 396#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
397 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
398 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
399
351f65ca
L		 400/* The ELF ABI to use. */
401enum x86_elf_abi
402{
403 I386_ABI,
7f56bc95
L		 404 X86_64_ABI,
405 X86_64_X32_ABI
351f65ca
L		 406};
407
408static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 409#endif
351f65ca 410
3e73aa7c 411/* The names used to print error messages. */
b77a7acd 412static const char *flag_code_names[] =
3e73aa7c
JH		 413 {
414 "32",
415 "16",
416 "64"
417 };
252b5132 418
47926f60
KH		 419/* 1 for intel syntax,
420 0 if att syntax. */
421static int intel_syntax = 0;
252b5132 422
1efbbeb4
L		 423/* 1 for intel mnemonic,
424 0 if att mnemonic. */
425static int intel_mnemonic = !SYSV386_COMPAT;
426
5209009a 427/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 428static int old_gcc = OLDGCC_COMPAT;
429
a60de03c
JB		 430/* 1 if pseudo registers are permitted. */
431static int allow_pseudo_reg = 0;
432
47926f60
KH		 433/* 1 if register prefix % not required. */
434static int allow_naked_reg = 0;
252b5132 435
ba104c83 436/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 437static int allow_index_reg = 0;
438
daf50ae7
L		 439static enum
440 {
441 sse_check_none = 0,
442 sse_check_warning,
443 sse_check_error
444 }
445sse_check;
446
2ca3ace5
L		 447/* Register prefix used for error message. */
448static const char *register_prefix = "%";
449
47926f60
KH		 450/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
451 leave, push, and pop instructions so that gcc has the same stack
452 frame as in 32 bit mode. */
453static char stackop_size = '\0';
eecb386c 454
12b55ccc
L		 455/* Non-zero to optimize code alignment. */
456int optimize_align_code = 1;
457
47926f60
KH		 458/* Non-zero to quieten some warnings. */
459static int quiet_warnings = 0;
a38cf1db 460
47926f60
KH		 461/* CPU name. */
462static const char *cpu_arch_name = NULL;
6305a203 463static char *cpu_sub_arch_name = NULL;
a38cf1db 464
47926f60 465/* CPU feature flags. */
40fb9820
L		 466static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
467
ccc9c027
L		 468/* If we have selected a cpu we are generating instructions for. */
469static int cpu_arch_tune_set = 0;
470
9103f4f4 471/* Cpu we are generating instructions for. */
fbf3f584 472enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 473
474/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 475static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 476
ccc9c027 477/* CPU instruction set architecture used. */
fbf3f584 478enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 479
9103f4f4 480/* CPU feature flags of instruction set architecture used. */
fbf3f584 481i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 482
fddf5b5b
AM		 483/* If set, conditional jumps are not automatically promoted to handle
484 larger than a byte offset. */
485static unsigned int no_cond_jump_promotion = 0;
486
c0f3af97
L		 487/* Encode SSE instructions with VEX prefix. */
488static unsigned int sse2avx;
489
539f890d
L		 490/* Encode scalar AVX instructions with specific vector length. */
491static enum
492 {
493 vex128 = 0,
494 vex256
495 } avxscalar;
496
29b0f896 497/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 498static symbolS *GOT_symbol;
29b0f896 499
a4447b93
RH		 500/* The dwarf2 return column, adjusted for 32 or 64 bit. */
501unsigned int x86_dwarf2_return_column;
502
503/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
504int x86_cie_data_alignment;
505
252b5132 506/* Interface to relax_segment.
fddf5b5b
AM		 507 There are 3 major relax states for 386 jump insns because the
508 different types of jumps add different sizes to frags when we're
509 figuring out what sort of jump to choose to reach a given label. */
252b5132 510
47926f60 511/* Types. */
93c2a809
AM		 512#define UNCOND_JUMP 0
513#define COND_JUMP 1
514#define COND_JUMP86 2
fddf5b5b 515
47926f60 516/* Sizes. */
252b5132
RH		 517#define CODE16 1
518#define SMALL 0
29b0f896 519#define SMALL16 (SMALL | CODE16)
252b5132 520#define BIG 2
29b0f896 521#define BIG16 (BIG | CODE16)
252b5132
RH		 522
523#ifndef INLINE
524#ifdef __GNUC__
525#define INLINE __inline__
526#else
527#define INLINE
528#endif
529#endif
530
fddf5b5b
AM		 531#define ENCODE_RELAX_STATE(type, size) \
532 ((relax_substateT) (((type) << 2) | (size)))
533#define TYPE_FROM_RELAX_STATE(s) \
534 ((s) >> 2)
535#define DISP_SIZE_FROM_RELAX_STATE(s) \
536 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 537
538/* This table is used by relax_frag to promote short jumps to long
539 ones where necessary. SMALL (short) jumps may be promoted to BIG
540 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
541 don't allow a short jump in a 32 bit code segment to be promoted to
542 a 16 bit offset jump because it's slower (requires data size
543 prefix), and doesn't work, unless the destination is in the bottom
544 64k of the code segment (The top 16 bits of eip are zeroed). */
545
546const relax_typeS md_relax_table[] =
547{
24eab124
AM		 548 /* The fields are:
549 1) most positive reach of this state,
550 2) most negative reach of this state,
93c2a809 551 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 552 4) which index into the table to try if we can't fit into this one. */
252b5132 553
fddf5b5b 554 /* UNCOND_JUMP states. */
93c2a809
AM		 555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
557 /* dword jmp adds 4 bytes to frag:
558 0 extra opcode bytes, 4 displacement bytes. */
252b5132 559 {0, 0, 4, 0},
93c2a809
AM		 560 /* word jmp adds 2 byte2 to frag:
561 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 562 {0, 0, 2, 0},
563
93c2a809
AM		 564 /* COND_JUMP states. */
565 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
566 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
567 /* dword conditionals adds 5 bytes to frag:
568 1 extra opcode byte, 4 displacement bytes. */
569 {0, 0, 5, 0},
fddf5b5b 570 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 571 1 extra opcode byte, 2 displacement bytes. */
572 {0, 0, 3, 0},
573
574 /* COND_JUMP86 states. */
575 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
576 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
577 /* dword conditionals adds 5 bytes to frag:
578 1 extra opcode byte, 4 displacement bytes. */
579 {0, 0, 5, 0},
580 /* word conditionals add 4 bytes to frag:
581 1 displacement byte and a 3 byte long branch insn. */
582 {0, 0, 4, 0}
252b5132
RH		 583};
584
9103f4f4
L		 585static const arch_entry cpu_arch[] =
586{
89507696
JB		 587 /* Do not replace the first two entries - i386_target_format()
588 relies on them being there in this order. */
8a2c8fef 589 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 590 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 591 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 592 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 593 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 594 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 595 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 596 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 597 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 598 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 599 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 600 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 601 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 602 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 603 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 604 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 605 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 606 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 607 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 608 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 609 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 610 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 611 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 612 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 613 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 614 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 615 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 616 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 617 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 618 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 619 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 620 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 621 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 622 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 623 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 624 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 625 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 626 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 627 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 628 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 629 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 630 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 631 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 632 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 633 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 634 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 635 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 636 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 637 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 638 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 639 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 640 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 641 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 642 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 643 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 644 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 645 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 646 CPU_AMDFAM10_FLAGS, 0, 0 },
68339fdf 647 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
22109423 648 CPU_BDVER1_FLAGS, 0, 0 },
8a2c8fef 649 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 650 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 651 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 652 CPU_287_FLAGS, 0, 0 },
8a2c8fef 653 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 654 CPU_387_FLAGS, 0, 0 },
8a2c8fef 655 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 656 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 657 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 658 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 659 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 660 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 661 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 662 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 663 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 664 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 665 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 666 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 667 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 668 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 669 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 670 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 671 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 672 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 673 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 674 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 675 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 676 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 677 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 678 CPU_AVX_FLAGS, 0, 0 },
8a2c8fef 679 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 680 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 681 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 682 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 683 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 684 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 685 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 686 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 687 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 688 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 689 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 690 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 691 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 692 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 693 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 694 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 695 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 696 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 697 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 698 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 699 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 700 CPU_F16C_FLAGS, 0, 0 },
8a2c8fef 701 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 702 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 703 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 704 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 705 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 706 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 707 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 708 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 709 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 710 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 712 CPU_EPT_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 714 CPU_CLFLUSH_FLAGS, 0, 0 },
715 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
716 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 718 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 720 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 722 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 724 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 726 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 728 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 729 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 730 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 732 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 734 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 735 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
736 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 737 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
738 CPU_TBM_FLAGS, 0, 0 },
e413e4e9
AM		 739};
740
704209c0 741#ifdef I386COFF
a6c24e68
NC		 742/* Like s_lcomm_internal in gas/read.c but the alignment string
743 is allowed to be optional. */
744
745static symbolS *
746pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
747{
748 addressT align = 0;
749
750 SKIP_WHITESPACE ();
751
7ab9ffdd 752 if (needs_align
a6c24e68
NC		 753 && *input_line_pointer == ',')
754 {
755 align = parse_align (needs_align - 1);
7ab9ffdd 756
a6c24e68
NC		 757 if (align == (addressT) -1)
758 return NULL;
759 }
760 else
761 {
762 if (size >= 8)
763 align = 3;
764 else if (size >= 4)
765 align = 2;
766 else if (size >= 2)
767 align = 1;
768 else
769 align = 0;
770 }
771
772 bss_alloc (symbolP, size, align);
773 return symbolP;
774}
775
704209c0 776static void
a6c24e68
NC		 777pe_lcomm (int needs_align)
778{
779 s_comm_internal (needs_align * 2, pe_lcomm_internal);
780}
704209c0 781#endif
a6c24e68 782
29b0f896
AM		 783const pseudo_typeS md_pseudo_table[] =
784{
785#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
786 {"align", s_align_bytes, 0},
787#else
788 {"align", s_align_ptwo, 0},
789#endif
790 {"arch", set_cpu_arch, 0},
791#ifndef I386COFF
792 {"bss", s_bss, 0},
a6c24e68
NC		 793#else
794 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 795#endif
796 {"ffloat", float_cons, 'f'},
797 {"dfloat", float_cons, 'd'},
798 {"tfloat", float_cons, 'x'},
799 {"value", cons, 2},
d182319b 800 {"slong", signed_cons, 4},
29b0f896
AM		 801 {"noopt", s_ignore, 0},
802 {"optim", s_ignore, 0},
803 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
804 {"code16", set_code_flag, CODE_16BIT},
805 {"code32", set_code_flag, CODE_32BIT},
806 {"code64", set_code_flag, CODE_64BIT},
807 {"intel_syntax", set_intel_syntax, 1},
808 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 809 {"intel_mnemonic", set_intel_mnemonic, 1},
810 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 811 {"allow_index_reg", set_allow_index_reg, 1},
812 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 813 {"sse_check", set_sse_check, 0},
3b22753a
L		 814#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
815 {"largecomm", handle_large_common, 0},
07a53e5c 816#else
e3bb37b5 817 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 818 {"loc", dwarf2_directive_loc, 0},
819 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 820#endif
6482c264
NC		 821#ifdef TE_PE
822 {"secrel32", pe_directive_secrel, 0},
823#endif
29b0f896
AM		 824 {0, 0, 0}
825};
826
827/* For interface with expression (). */
828extern char *input_line_pointer;
829
830/* Hash table for instruction mnemonic lookup. */
831static struct hash_control *op_hash;
832
833/* Hash table for register lookup. */
834static struct hash_control *reg_hash;
835\f
252b5132 836void
e3bb37b5 837i386_align_code (fragS *fragP, int count)
252b5132 838{
ce8a8b2f
AM		 839 /* Various efficient no-op patterns for aligning code labels.
840 Note: Don't try to assemble the instructions in the comments.
841 0L and 0w are not legal. */
252b5132
RH		 842 static const char f32_1[] =
843 {0x90}; /* nop */
844 static const char f32_2[] =
ccc9c027 845 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 846 static const char f32_3[] =
847 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
848 static const char f32_4[] =
849 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
850 static const char f32_5[] =
851 {0x90, /* nop */
852 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
853 static const char f32_6[] =
854 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
855 static const char f32_7[] =
856 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
857 static const char f32_8[] =
858 {0x90, /* nop */
859 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
860 static const char f32_9[] =
861 {0x89,0xf6, /* movl %esi,%esi */
862 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
863 static const char f32_10[] =
864 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
865 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
866 static const char f32_11[] =
867 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
868 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
869 static const char f32_12[] =
870 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
871 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
872 static const char f32_13[] =
873 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
874 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
875 static const char f32_14[] =
876 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
877 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 878 static const char f16_3[] =
879 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 880 static const char f16_4[] =
881 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
882 static const char f16_5[] =
883 {0x90, /* nop */
884 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
885 static const char f16_6[] =
886 {0x89,0xf6, /* mov %si,%si */
887 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
888 static const char f16_7[] =
889 {0x8d,0x74,0x00, /* lea 0(%si),%si */
890 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
891 static const char f16_8[] =
892 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
893 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 894 static const char jump_31[] =
895 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
896 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
897 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
898 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 899 static const char *const f32_patt[] = {
900 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 901 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 902 };
903 static const char *const f16_patt[] = {
76bc74dc 904 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 905 };
ccc9c027
L		 906 /* nopl (%[re]ax) */
907 static const char alt_3[] =
908 {0x0f,0x1f,0x00};
909 /* nopl 0(%[re]ax) */
910 static const char alt_4[] =
911 {0x0f,0x1f,0x40,0x00};
912 /* nopl 0(%[re]ax,%[re]ax,1) */
913 static const char alt_5[] =
914 {0x0f,0x1f,0x44,0x00,0x00};
915 /* nopw 0(%[re]ax,%[re]ax,1) */
916 static const char alt_6[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopl 0L(%[re]ax) */
919 static const char alt_7[] =
920 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 /* nopl 0L(%[re]ax,%[re]ax,1) */
922 static const char alt_8[] =
923 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
924 /* nopw 0L(%[re]ax,%[re]ax,1) */
925 static const char alt_9[] =
926 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
928 static const char alt_10[] =
929 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
930 /* data16
931 nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_long_11[] =
933 {0x66,
934 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
935 /* data16
936 data16
937 nopw %cs:0L(%[re]ax,%[re]ax,1) */
938 static const char alt_long_12[] =
939 {0x66,
940 0x66,
941 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
942 /* data16
943 data16
944 data16
945 nopw %cs:0L(%[re]ax,%[re]ax,1) */
946 static const char alt_long_13[] =
947 {0x66,
948 0x66,
949 0x66,
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
951 /* data16
952 data16
953 data16
954 data16
955 nopw %cs:0L(%[re]ax,%[re]ax,1) */
956 static const char alt_long_14[] =
957 {0x66,
958 0x66,
959 0x66,
960 0x66,
961 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
962 /* data16
963 data16
964 data16
965 data16
966 data16
967 nopw %cs:0L(%[re]ax,%[re]ax,1) */
968 static const char alt_long_15[] =
969 {0x66,
970 0x66,
971 0x66,
972 0x66,
973 0x66,
974 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
975 /* nopl 0(%[re]ax,%[re]ax,1)
976 nopw 0(%[re]ax,%[re]ax,1) */
977 static const char alt_short_11[] =
978 {0x0f,0x1f,0x44,0x00,0x00,
979 0x66,0x0f,0x1f,0x44,0x00,0x00};
980 /* nopw 0(%[re]ax,%[re]ax,1)
981 nopw 0(%[re]ax,%[re]ax,1) */
982 static const char alt_short_12[] =
983 {0x66,0x0f,0x1f,0x44,0x00,0x00,
984 0x66,0x0f,0x1f,0x44,0x00,0x00};
985 /* nopw 0(%[re]ax,%[re]ax,1)
986 nopl 0L(%[re]ax) */
987 static const char alt_short_13[] =
988 {0x66,0x0f,0x1f,0x44,0x00,0x00,
989 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
990 /* nopl 0L(%[re]ax)
991 nopl 0L(%[re]ax) */
992 static const char alt_short_14[] =
993 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
994 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
995 /* nopl 0L(%[re]ax)
996 nopl 0L(%[re]ax,%[re]ax,1) */
997 static const char alt_short_15[] =
998 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
999 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1000 static const char *const alt_short_patt[] = {
1001 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1002 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1003 alt_short_14, alt_short_15
1004 };
1005 static const char *const alt_long_patt[] = {
1006 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1007 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1008 alt_long_14, alt_long_15
1009 };
252b5132 1010
76bc74dc
L		 1011 /* Only align for at least a positive non-zero boundary. */
1012 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1013 return;
3e73aa7c 1014
ccc9c027
L		 1015 /* We need to decide which NOP sequence to use for 32bit and
1016 64bit. When -mtune= is used:
4eed87de 1017
76bc74dc
L		 1018 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1019 PROCESSOR_GENERIC32, f32_patt will be used.
1020 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1021 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1022 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1023 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 1024 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 1025 will be used.
ccc9c027 1026
76bc74dc 1027 When -mtune= isn't used, alt_long_patt will be used if
22109423 1028 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1029 be used.
ccc9c027
L		 1030
1031 When -march= or .arch is used, we can't use anything beyond
1032 cpu_arch_isa_flags. */
1033
1034 if (flag_code == CODE_16BIT)
1035 {
ccc9c027 1036 if (count > 8)
33fef721 1037 {
76bc74dc
L		 1038 memcpy (fragP->fr_literal + fragP->fr_fix,
1039 jump_31, count);
1040 /* Adjust jump offset. */
1041 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1042 }
76bc74dc
L		 1043 else
1044 memcpy (fragP->fr_literal + fragP->fr_fix,
1045 f16_patt[count - 1], count);
252b5132 1046 }
33fef721 1047 else
ccc9c027
L		 1048 {
1049 const char *const *patt = NULL;
1050
fbf3f584 1051 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1052 {
1053 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1054 switch (cpu_arch_tune)
1055 {
1056 case PROCESSOR_UNKNOWN:
1057 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1058 optimize with nops. */
1059 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1060 patt = alt_long_patt;
ccc9c027
L		 1061 else
1062 patt = f32_patt;
1063 break;
ccc9c027
L		 1064 case PROCESSOR_PENTIUM4:
1065 case PROCESSOR_NOCONA:
ef05d495 1066 case PROCESSOR_CORE:
76bc74dc 1067 case PROCESSOR_CORE2:
bd5295b2 1068 case PROCESSOR_COREI7:
3632d14b 1069 case PROCESSOR_L1OM:
76bc74dc
L		 1070 case PROCESSOR_GENERIC64:
1071 patt = alt_long_patt;
1072 break;
ccc9c027
L		 1073 case PROCESSOR_K6:
1074 case PROCESSOR_ATHLON:
1075 case PROCESSOR_K8:
4eed87de 1076 case PROCESSOR_AMDFAM10:
68339fdf 1077 case PROCESSOR_BDVER1:
ccc9c027
L		 1078 patt = alt_short_patt;
1079 break;
76bc74dc 1080 case PROCESSOR_I386:
ccc9c027
L		 1081 case PROCESSOR_I486:
1082 case PROCESSOR_PENTIUM:
2dde1948 1083 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1084 case PROCESSOR_GENERIC32:
1085 patt = f32_patt;
1086 break;
4eed87de 1087 }
ccc9c027
L		 1088 }
1089 else
1090 {
fbf3f584 1091 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1092 {
1093 case PROCESSOR_UNKNOWN:
e6a14101 1094 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1095 PROCESSOR_UNKNOWN. */
1096 abort ();
1097 break;
1098
76bc74dc 1099 case PROCESSOR_I386:
ccc9c027
L		 1100 case PROCESSOR_I486:
1101 case PROCESSOR_PENTIUM:
ccc9c027
L		 1102 case PROCESSOR_K6:
1103 case PROCESSOR_ATHLON:
1104 case PROCESSOR_K8:
4eed87de 1105 case PROCESSOR_AMDFAM10:
68339fdf 1106 case PROCESSOR_BDVER1:
ccc9c027
L		 1107 case PROCESSOR_GENERIC32:
1108 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1109 with nops. */
1110 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1111 patt = alt_short_patt;
1112 else
1113 patt = f32_patt;
1114 break;
76bc74dc
L		 1115 case PROCESSOR_PENTIUMPRO:
1116 case PROCESSOR_PENTIUM4:
1117 case PROCESSOR_NOCONA:
1118 case PROCESSOR_CORE:
ef05d495 1119 case PROCESSOR_CORE2:
bd5295b2 1120 case PROCESSOR_COREI7:
3632d14b 1121 case PROCESSOR_L1OM:
22109423 1122 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1123 patt = alt_long_patt;
1124 else
1125 patt = f32_patt;
1126 break;
1127 case PROCESSOR_GENERIC64:
76bc74dc 1128 patt = alt_long_patt;
ccc9c027 1129 break;
4eed87de 1130 }
ccc9c027
L		 1131 }
1132
76bc74dc
L		 1133 if (patt == f32_patt)
1134 {
1135 /* If the padding is less than 15 bytes, we use the normal
1136 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1137 its offset. */
1138 int limit;
76ba9986 1139
711eedef
L		 1140 /* For 64bit, the limit is 3 bytes. */
1141 if (flag_code == CODE_64BIT
1142 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1143 limit = 3;
1144 else
1145 limit = 15;
1146 if (count < limit)
76bc74dc
L		 1147 memcpy (fragP->fr_literal + fragP->fr_fix,
1148 patt[count - 1], count);
1149 else
1150 {
1151 memcpy (fragP->fr_literal + fragP->fr_fix,
1152 jump_31, count);
1153 /* Adjust jump offset. */
1154 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1155 }
1156 }
1157 else
1158 {
1159 /* Maximum length of an instruction is 15 byte. If the
1160 padding is greater than 15 bytes and we don't use jump,
1161 we have to break it into smaller pieces. */
1162 int padding = count;
1163 while (padding > 15)
1164 {
1165 padding -= 15;
1166 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1167 patt [14], 15);
1168 }
1169
1170 if (padding)
1171 memcpy (fragP->fr_literal + fragP->fr_fix,
1172 patt [padding - 1], padding);
1173 }
ccc9c027 1174 }
33fef721 1175 fragP->fr_var = count;
252b5132
RH		 1176}
1177
c6fb90c8 1178static INLINE int
0dfbf9d7 1179operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1180{
0dfbf9d7 1181 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1182 {
1183 case 3:
0dfbf9d7 1184 if (x->array[2])
c6fb90c8
L		 1185 return 0;
1186 case 2:
0dfbf9d7 1187 if (x->array[1])
c6fb90c8
L		 1188 return 0;
1189 case 1:
0dfbf9d7 1190 return !x->array[0];
c6fb90c8
L		 1191 default:
1192 abort ();
1193 }
40fb9820
L		 1194}
1195
c6fb90c8 1196static INLINE void
0dfbf9d7 1197operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1198{
0dfbf9d7 1199 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1200 {
1201 case 3:
0dfbf9d7 1202 x->array[2] = v;
c6fb90c8 1203 case 2:
0dfbf9d7 1204 x->array[1] = v;
c6fb90c8 1205 case 1:
0dfbf9d7 1206 x->array[0] = v;
c6fb90c8
L		 1207 break;
1208 default:
1209 abort ();
1210 }
1211}
40fb9820 1212
c6fb90c8 1213static INLINE int
0dfbf9d7
L		 1214operand_type_equal (const union i386_operand_type *x,
1215 const union i386_operand_type *y)
c6fb90c8 1216{
0dfbf9d7 1217 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1218 {
1219 case 3:
0dfbf9d7 1220 if (x->array[2] != y->array[2])
c6fb90c8
L		 1221 return 0;
1222 case 2:
0dfbf9d7 1223 if (x->array[1] != y->array[1])
c6fb90c8
L		 1224 return 0;
1225 case 1:
0dfbf9d7 1226 return x->array[0] == y->array[0];
c6fb90c8
L		 1227 break;
1228 default:
1229 abort ();
1230 }
1231}
40fb9820 1232
0dfbf9d7
L		 1233static INLINE int
1234cpu_flags_all_zero (const union i386_cpu_flags *x)
1235{
1236 switch (ARRAY_SIZE(x->array))
1237 {
1238 case 3:
1239 if (x->array[2])
1240 return 0;
1241 case 2:
1242 if (x->array[1])
1243 return 0;
1244 case 1:
1245 return !x->array[0];
1246 default:
1247 abort ();
1248 }
1249}
1250
1251static INLINE void
1252cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1253{
1254 switch (ARRAY_SIZE(x->array))
1255 {
1256 case 3:
1257 x->array[2] = v;
1258 case 2:
1259 x->array[1] = v;
1260 case 1:
1261 x->array[0] = v;
1262 break;
1263 default:
1264 abort ();
1265 }
1266}
1267
1268static INLINE int
1269cpu_flags_equal (const union i386_cpu_flags *x,
1270 const union i386_cpu_flags *y)
1271{
1272 switch (ARRAY_SIZE(x->array))
1273 {
1274 case 3:
1275 if (x->array[2] != y->array[2])
1276 return 0;
1277 case 2:
1278 if (x->array[1] != y->array[1])
1279 return 0;
1280 case 1:
1281 return x->array[0] == y->array[0];
1282 break;
1283 default:
1284 abort ();
1285 }
1286}
c6fb90c8
L		 1287
1288static INLINE int
1289cpu_flags_check_cpu64 (i386_cpu_flags f)
1290{
1291 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1292 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1293}
1294
c6fb90c8
L		 1295static INLINE i386_cpu_flags
1296cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1297{
c6fb90c8
L		 1298 switch (ARRAY_SIZE (x.array))
1299 {
1300 case 3:
1301 x.array [2] &= y.array [2];
1302 case 2:
1303 x.array [1] &= y.array [1];
1304 case 1:
1305 x.array [0] &= y.array [0];
1306 break;
1307 default:
1308 abort ();
1309 }
1310 return x;
1311}
40fb9820 1312
c6fb90c8
L		 1313static INLINE i386_cpu_flags
1314cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1315{
c6fb90c8 1316 switch (ARRAY_SIZE (x.array))
40fb9820 1317 {
c6fb90c8
L		 1318 case 3:
1319 x.array [2] |= y.array [2];
1320 case 2:
1321 x.array [1] |= y.array [1];
1322 case 1:
1323 x.array [0] |= y.array [0];
40fb9820
L		 1324 break;
1325 default:
1326 abort ();
1327 }
40fb9820
L		 1328 return x;
1329}
1330
309d3373
JB		 1331static INLINE i386_cpu_flags
1332cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1333{
1334 switch (ARRAY_SIZE (x.array))
1335 {
1336 case 3:
1337 x.array [2] &= ~y.array [2];
1338 case 2:
1339 x.array [1] &= ~y.array [1];
1340 case 1:
1341 x.array [0] &= ~y.array [0];
1342 break;
1343 default:
1344 abort ();
1345 }
1346 return x;
1347}
1348
c0f3af97
L		 1349#define CPU_FLAGS_ARCH_MATCH 0x1
1350#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1351#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1352#define CPU_FLAGS_PCLMUL_MATCH 0x8
1353#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1354
a5ff0eb2 1355#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1356 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1357 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1358#define CPU_FLAGS_PERFECT_MATCH \
1359 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1360
1361/* Return CPU flags match bits. */
3629bb00 1362
40fb9820 1363static int
d3ce72d0 1364cpu_flags_match (const insn_template *t)
40fb9820 1365{
c0f3af97
L		 1366 i386_cpu_flags x = t->cpu_flags;
1367 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1368
1369 x.bitfield.cpu64 = 0;
1370 x.bitfield.cpuno64 = 0;
1371
0dfbf9d7 1372 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1373 {
1374 /* This instruction is available on all archs. */
1375 match |= CPU_FLAGS_32BIT_MATCH;
1376 }
3629bb00
L		 1377 else
1378 {
c0f3af97 1379 /* This instruction is available only on some archs. */
3629bb00
L		 1380 i386_cpu_flags cpu = cpu_arch_flags;
1381
1382 cpu.bitfield.cpu64 = 0;
1383 cpu.bitfield.cpuno64 = 0;
1384 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1385 if (!cpu_flags_all_zero (&cpu))
1386 {
a5ff0eb2
L		 1387 if (x.bitfield.cpuavx)
1388 {
ce2f5b3c 1389 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1390 if (cpu.bitfield.cpuavx)
1391 {
1392 /* Check SSE2AVX. */
1393 if (!t->opcode_modifier.sse2avx|| sse2avx)
1394 {
1395 match |= (CPU_FLAGS_ARCH_MATCH
1396 | CPU_FLAGS_AVX_MATCH);
1397 /* Check AES. */
1398 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1399 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1400 /* Check PCLMUL. */
1401 if (!x.bitfield.cpupclmul
1402 || cpu.bitfield.cpupclmul)
1403 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1404 }
1405 }
1406 else
1407 match |= CPU_FLAGS_ARCH_MATCH;
1408 }
1409 else
c0f3af97
L		 1410 match |= CPU_FLAGS_32BIT_MATCH;
1411 }
3629bb00 1412 }
c0f3af97 1413 return match;
40fb9820
L		 1414}
1415
c6fb90c8
L		 1416static INLINE i386_operand_type
1417operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1418{
c6fb90c8
L		 1419 switch (ARRAY_SIZE (x.array))
1420 {
1421 case 3:
1422 x.array [2] &= y.array [2];
1423 case 2:
1424 x.array [1] &= y.array [1];
1425 case 1:
1426 x.array [0] &= y.array [0];
1427 break;
1428 default:
1429 abort ();
1430 }
1431 return x;
40fb9820
L		 1432}
1433
c6fb90c8
L		 1434static INLINE i386_operand_type
1435operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1436{
c6fb90c8 1437 switch (ARRAY_SIZE (x.array))
40fb9820 1438 {
c6fb90c8
L		 1439 case 3:
1440 x.array [2] |= y.array [2];
1441 case 2:
1442 x.array [1] |= y.array [1];
1443 case 1:
1444 x.array [0] |= y.array [0];
40fb9820
L		 1445 break;
1446 default:
1447 abort ();
1448 }
c6fb90c8
L		 1449 return x;
1450}
40fb9820 1451
c6fb90c8
L		 1452static INLINE i386_operand_type
1453operand_type_xor (i386_operand_type x, i386_operand_type y)
1454{
1455 switch (ARRAY_SIZE (x.array))
1456 {
1457 case 3:
1458 x.array [2] ^= y.array [2];
1459 case 2:
1460 x.array [1] ^= y.array [1];
1461 case 1:
1462 x.array [0] ^= y.array [0];
1463 break;
1464 default:
1465 abort ();
1466 }
40fb9820
L		 1467 return x;
1468}
1469
1470static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1471static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1472static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1473static const i386_operand_type inoutportreg
1474 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1475static const i386_operand_type reg16_inoutportreg
1476 = OPERAND_TYPE_REG16_INOUTPORTREG;
1477static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1478static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1479static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1480static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1481static const i386_operand_type anydisp
1482 = OPERAND_TYPE_ANYDISP;
40fb9820 1483static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1484static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1485static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1486static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1487static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1488static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1489static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1490static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1491static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1492static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1493static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1494static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1495
1496enum operand_type
1497{
1498 reg,
40fb9820
L		 1499 imm,
1500 disp,
1501 anymem
1502};
1503
c6fb90c8 1504static INLINE int
40fb9820
L		 1505operand_type_check (i386_operand_type t, enum operand_type c)
1506{
1507 switch (c)
1508 {
1509 case reg:
1510 return (t.bitfield.reg8
1511 || t.bitfield.reg16
1512 || t.bitfield.reg32
1513 || t.bitfield.reg64);
1514
40fb9820
L		 1515 case imm:
1516 return (t.bitfield.imm8
1517 || t.bitfield.imm8s
1518 || t.bitfield.imm16
1519 || t.bitfield.imm32
1520 || t.bitfield.imm32s
1521 || t.bitfield.imm64);
1522
1523 case disp:
1524 return (t.bitfield.disp8
1525 || t.bitfield.disp16
1526 || t.bitfield.disp32
1527 || t.bitfield.disp32s
1528 || t.bitfield.disp64);
1529
1530 case anymem:
1531 return (t.bitfield.disp8
1532 || t.bitfield.disp16
1533 || t.bitfield.disp32
1534 || t.bitfield.disp32s
1535 || t.bitfield.disp64
1536 || t.bitfield.baseindex);
1537
1538 default:
1539 abort ();
1540 }
2cfe26b6
AM		 1541
1542 return 0;
40fb9820
L		 1543}
1544
5c07affc
L		 1545/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1546 operand J for instruction template T. */
1547
1548static INLINE int
d3ce72d0 1549match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1550{
1551 return !((i.types[j].bitfield.byte
1552 && !t->operand_types[j].bitfield.byte)
1553 || (i.types[j].bitfield.word
1554 && !t->operand_types[j].bitfield.word)
1555 || (i.types[j].bitfield.dword
1556 && !t->operand_types[j].bitfield.dword)
1557 || (i.types[j].bitfield.qword
1558 && !t->operand_types[j].bitfield.qword));
1559}
1560
1561/* Return 1 if there is no conflict in any size on operand J for
1562 instruction template T. */
1563
1564static INLINE int
d3ce72d0 1565match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1566{
1567 return (match_reg_size (t, j)
1568 && !((i.types[j].bitfield.unspecified
1569 && !t->operand_types[j].bitfield.unspecified)
1570 || (i.types[j].bitfield.fword
1571 && !t->operand_types[j].bitfield.fword)
1572 || (i.types[j].bitfield.tbyte
1573 && !t->operand_types[j].bitfield.tbyte)
1574 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1575 && !t->operand_types[j].bitfield.xmmword)
1576 || (i.types[j].bitfield.ymmword
1577 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1578}
1579
1580/* Return 1 if there is no size conflict on any operands for
1581 instruction template T. */
1582
1583static INLINE int
d3ce72d0 1584operand_size_match (const insn_template *t)
5c07affc
L		 1585{
1586 unsigned int j;
1587 int match = 1;
1588
1589 /* Don't check jump instructions. */
1590 if (t->opcode_modifier.jump
1591 || t->opcode_modifier.jumpbyte
1592 || t->opcode_modifier.jumpdword
1593 || t->opcode_modifier.jumpintersegment)
1594 return match;
1595
1596 /* Check memory and accumulator operand size. */
1597 for (j = 0; j < i.operands; j++)
1598 {
1599 if (t->operand_types[j].bitfield.anysize)
1600 continue;
1601
1602 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1603 {
1604 match = 0;
1605 break;
1606 }
1607
1608 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1609 {
1610 match = 0;
1611 break;
1612 }
1613 }
1614
891edac4 1615 if (match)
5c07affc 1616 return match;
891edac4
L		 1617 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1618 {
1619mismatch:
86e026a4 1620 i.error = operand_size_mismatch;
891edac4
L		 1621 return 0;
1622 }
5c07affc
L		 1623
1624 /* Check reverse. */
9c2799c2 1625 gas_assert (i.operands == 2);
5c07affc
L		 1626
1627 match = 1;
1628 for (j = 0; j < 2; j++)
1629 {
1630 if (t->operand_types[j].bitfield.acc
1631 && !match_reg_size (t, j ? 0 : 1))
891edac4 1632 goto mismatch;
5c07affc
L		 1633
1634 if (i.types[j].bitfield.mem
1635 && !match_mem_size (t, j ? 0 : 1))
891edac4 1636 goto mismatch;
5c07affc
L		 1637 }
1638
1639 return match;
1640}
1641
c6fb90c8 1642static INLINE int
40fb9820
L		 1643operand_type_match (i386_operand_type overlap,
1644 i386_operand_type given)
1645{
1646 i386_operand_type temp = overlap;
1647
1648 temp.bitfield.jumpabsolute = 0;
7d5e4556 1649 temp.bitfield.unspecified = 0;
5c07affc
L		 1650 temp.bitfield.byte = 0;
1651 temp.bitfield.word = 0;
1652 temp.bitfield.dword = 0;
1653 temp.bitfield.fword = 0;
1654 temp.bitfield.qword = 0;
1655 temp.bitfield.tbyte = 0;
1656 temp.bitfield.xmmword = 0;
c0f3af97 1657 temp.bitfield.ymmword = 0;
0dfbf9d7 1658 if (operand_type_all_zero (&temp))
891edac4 1659 goto mismatch;
40fb9820 1660
891edac4
L		 1661 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1662 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1663 return 1;
1664
1665mismatch:
a65babc9 1666 i.error = operand_type_mismatch;
891edac4 1667 return 0;
40fb9820
L		 1668}
1669
7d5e4556 1670/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1671 unless the expected operand type register overlap is null.
1672 Note that Acc in a template matches every size of reg. */
1673
c6fb90c8 1674static INLINE int
40fb9820
L		 1675operand_type_register_match (i386_operand_type m0,
1676 i386_operand_type g0,
1677 i386_operand_type t0,
1678 i386_operand_type m1,
1679 i386_operand_type g1,
1680 i386_operand_type t1)
1681{
1682 if (!operand_type_check (g0, reg))
1683 return 1;
1684
1685 if (!operand_type_check (g1, reg))
1686 return 1;
1687
1688 if (g0.bitfield.reg8 == g1.bitfield.reg8
1689 && g0.bitfield.reg16 == g1.bitfield.reg16
1690 && g0.bitfield.reg32 == g1.bitfield.reg32
1691 && g0.bitfield.reg64 == g1.bitfield.reg64)
1692 return 1;
1693
1694 if (m0.bitfield.acc)
1695 {
1696 t0.bitfield.reg8 = 1;
1697 t0.bitfield.reg16 = 1;
1698 t0.bitfield.reg32 = 1;
1699 t0.bitfield.reg64 = 1;
1700 }
1701
1702 if (m1.bitfield.acc)
1703 {
1704 t1.bitfield.reg8 = 1;
1705 t1.bitfield.reg16 = 1;
1706 t1.bitfield.reg32 = 1;
1707 t1.bitfield.reg64 = 1;
1708 }
1709
891edac4
L		 1710 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1711 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1712 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1713 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1714 return 1;
1715
a65babc9 1716 i.error = register_type_mismatch;
891edac4
L		 1717
1718 return 0;
40fb9820
L		 1719}
1720
252b5132 1721static INLINE unsigned int
40fb9820 1722mode_from_disp_size (i386_operand_type t)
252b5132 1723{
40fb9820
L		 1724 if (t.bitfield.disp8)
1725 return 1;
1726 else if (t.bitfield.disp16
1727 || t.bitfield.disp32
1728 || t.bitfield.disp32s)
1729 return 2;
1730 else
1731 return 0;
252b5132
RH		 1732}
1733
1734static INLINE int
e3bb37b5 1735fits_in_signed_byte (offsetT num)
252b5132
RH		 1736{
1737 return (num >= -128) && (num <= 127);
47926f60 1738}
252b5132
RH		 1739
1740static INLINE int
e3bb37b5 1741fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1742{
1743 return (num & 0xff) == num;
47926f60 1744}
252b5132
RH		 1745
1746static INLINE int
e3bb37b5 1747fits_in_unsigned_word (offsetT num)
252b5132
RH		 1748{
1749 return (num & 0xffff) == num;
47926f60 1750}
252b5132
RH		 1751
1752static INLINE int
e3bb37b5 1753fits_in_signed_word (offsetT num)
252b5132
RH		 1754{
1755 return (-32768 <= num) && (num <= 32767);
47926f60 1756}
2a962e6d 1757
3e73aa7c 1758static INLINE int
e3bb37b5 1759fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1760{
1761#ifndef BFD64
1762 return 1;
1763#else
1764 return (!(((offsetT) -1 << 31) & num)
1765 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1766#endif
1767} /* fits_in_signed_long() */
2a962e6d 1768
3e73aa7c 1769static INLINE int
e3bb37b5 1770fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1771{
1772#ifndef BFD64
1773 return 1;
1774#else
1775 return (num & (((offsetT) 2 << 31) - 1)) == num;
1776#endif
1777} /* fits_in_unsigned_long() */
252b5132 1778
a683cc34
SP		 1779static INLINE int
1780fits_in_imm4 (offsetT num)
1781{
1782 return (num & 0xf) == num;
1783}
1784
40fb9820 1785static i386_operand_type
e3bb37b5 1786smallest_imm_type (offsetT num)
252b5132 1787{
40fb9820 1788 i386_operand_type t;
7ab9ffdd 1789
0dfbf9d7 1790 operand_type_set (&t, 0);
40fb9820
L		 1791 t.bitfield.imm64 = 1;
1792
1793 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1794 {
1795 /* This code is disabled on the 486 because all the Imm1 forms
1796 in the opcode table are slower on the i486. They're the
1797 versions with the implicitly specified single-position
1798 displacement, which has another syntax if you really want to
1799 use that form. */
40fb9820
L		 1800 t.bitfield.imm1 = 1;
1801 t.bitfield.imm8 = 1;
1802 t.bitfield.imm8s = 1;
1803 t.bitfield.imm16 = 1;
1804 t.bitfield.imm32 = 1;
1805 t.bitfield.imm32s = 1;
1806 }
1807 else if (fits_in_signed_byte (num))
1808 {
1809 t.bitfield.imm8 = 1;
1810 t.bitfield.imm8s = 1;
1811 t.bitfield.imm16 = 1;
1812 t.bitfield.imm32 = 1;
1813 t.bitfield.imm32s = 1;
1814 }
1815 else if (fits_in_unsigned_byte (num))
1816 {
1817 t.bitfield.imm8 = 1;
1818 t.bitfield.imm16 = 1;
1819 t.bitfield.imm32 = 1;
1820 t.bitfield.imm32s = 1;
1821 }
1822 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1823 {
1824 t.bitfield.imm16 = 1;
1825 t.bitfield.imm32 = 1;
1826 t.bitfield.imm32s = 1;
1827 }
1828 else if (fits_in_signed_long (num))
1829 {
1830 t.bitfield.imm32 = 1;
1831 t.bitfield.imm32s = 1;
1832 }
1833 else if (fits_in_unsigned_long (num))
1834 t.bitfield.imm32 = 1;
1835
1836 return t;
47926f60 1837}
252b5132 1838
847f7ad4 1839static offsetT
e3bb37b5 1840offset_in_range (offsetT val, int size)
847f7ad4 1841{
508866be 1842 addressT mask;
ba2adb93 1843
847f7ad4
AM		 1844 switch (size)
1845 {
508866be
L		 1846 case 1: mask = ((addressT) 1 << 8) - 1; break;
1847 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1848 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1849#ifdef BFD64
1850 case 8: mask = ((addressT) 2 << 63) - 1; break;
1851#endif
47926f60 1852 default: abort ();
847f7ad4
AM		 1853 }
1854
9de868bf
L		 1855#ifdef BFD64
1856 /* If BFD64, sign extend val for 32bit address mode. */
1857 if (flag_code != CODE_64BIT
1858 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1859 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1860 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1861#endif
ba2adb93 1862
47926f60 1863 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1864 {
1865 char buf1[40], buf2[40];
1866
1867 sprint_value (buf1, val);
1868 sprint_value (buf2, val & mask);
1869 as_warn (_("%s shortened to %s"), buf1, buf2);
1870 }
1871 return val & mask;
1872}
1873
c32fa91d
L		 1874enum PREFIX_GROUP
1875{
1876 PREFIX_EXIST = 0,
1877 PREFIX_LOCK,
1878 PREFIX_REP,
1879 PREFIX_OTHER
1880};
1881
1882/* Returns
1883 a. PREFIX_EXIST if attempting to add a prefix where one from the
1884 same class already exists.
1885 b. PREFIX_LOCK if lock prefix is added.
1886 c. PREFIX_REP if rep/repne prefix is added.
1887 d. PREFIX_OTHER if other prefix is added.
1888 */
1889
1890static enum PREFIX_GROUP
e3bb37b5 1891add_prefix (unsigned int prefix)
252b5132 1892{
c32fa91d 1893 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1894 unsigned int q;
252b5132 1895
29b0f896
AM		 1896 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1897 && flag_code == CODE_64BIT)
b1905489 1898 {
161a04f6
L		 1899 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1900 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1901 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1902 ret = PREFIX_EXIST;
b1905489
JB		 1903 q = REX_PREFIX;
1904 }
3e73aa7c 1905 else
b1905489
JB		 1906 {
1907 switch (prefix)
1908 {
1909 default:
1910 abort ();
1911
1912 case CS_PREFIX_OPCODE:
1913 case DS_PREFIX_OPCODE:
1914 case ES_PREFIX_OPCODE:
1915 case FS_PREFIX_OPCODE:
1916 case GS_PREFIX_OPCODE:
1917 case SS_PREFIX_OPCODE:
1918 q = SEG_PREFIX;
1919 break;
1920
1921 case REPNE_PREFIX_OPCODE:
1922 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1923 q = REP_PREFIX;
1924 ret = PREFIX_REP;
1925 break;
1926
b1905489 1927 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1928 q = LOCK_PREFIX;
1929 ret = PREFIX_LOCK;
b1905489
JB		 1930 break;
1931
1932 case FWAIT_OPCODE:
1933 q = WAIT_PREFIX;
1934 break;
1935
1936 case ADDR_PREFIX_OPCODE:
1937 q = ADDR_PREFIX;
1938 break;
1939
1940 case DATA_PREFIX_OPCODE:
1941 q = DATA_PREFIX;
1942 break;
1943 }
1944 if (i.prefix[q] != 0)
c32fa91d 1945 ret = PREFIX_EXIST;
b1905489 1946 }
252b5132 1947
b1905489 1948 if (ret)
252b5132 1949 {
b1905489
JB		 1950 if (!i.prefix[q])
1951 ++i.prefixes;
1952 i.prefix[q] |= prefix;
252b5132 1953 }
b1905489
JB		 1954 else
1955 as_bad (_("same type of prefix used twice"));
252b5132 1956
252b5132
RH		 1957 return ret;
1958}
1959
1960static void
78f12dd3 1961update_code_flag (int value, int check)
eecb386c 1962{
78f12dd3
L		 1963 PRINTF_LIKE ((*as_error));
1964
1e9cc1c2 1965 flag_code = (enum flag_code) value;
40fb9820
L		 1966 if (flag_code == CODE_64BIT)
1967 {
1968 cpu_arch_flags.bitfield.cpu64 = 1;
1969 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1970 }
1971 else
1972 {
1973 cpu_arch_flags.bitfield.cpu64 = 0;
1974 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1975 }
1976 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1977 {
78f12dd3
L		 1978 if (check)
1979 as_error = as_fatal;
1980 else
1981 as_error = as_bad;
1982 (*as_error) (_("64bit mode not supported on `%s'."),
1983 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1984 }
40fb9820 1985 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1986 {
78f12dd3
L		 1987 if (check)
1988 as_error = as_fatal;
1989 else
1990 as_error = as_bad;
1991 (*as_error) (_("32bit mode not supported on `%s'."),
1992 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1993 }
eecb386c
AM		 1994 stackop_size = '\0';
1995}
1996
78f12dd3
L		 1997static void
1998set_code_flag (int value)
1999{
2000 update_code_flag (value, 0);
2001}
2002
eecb386c 2003static void
e3bb37b5 2004set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2005{
1e9cc1c2 2006 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2007 if (flag_code != CODE_16BIT)
2008 abort ();
2009 cpu_arch_flags.bitfield.cpu64 = 0;
2010 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2011 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2012}
2013
2014static void
e3bb37b5 2015set_intel_syntax (int syntax_flag)
252b5132
RH		 2016{
2017 /* Find out if register prefixing is specified. */
2018 int ask_naked_reg = 0;
2019
2020 SKIP_WHITESPACE ();
29b0f896 2021 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2022 {
2023 char *string = input_line_pointer;
2024 int e = get_symbol_end ();
2025
47926f60 2026 if (strcmp (string, "prefix") == 0)
252b5132 2027 ask_naked_reg = 1;
47926f60 2028 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2029 ask_naked_reg = -1;
2030 else
d0b47220 2031 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2032 *input_line_pointer = e;
2033 }
2034 demand_empty_rest_of_line ();
c3332e24 2035
252b5132
RH		 2036 intel_syntax = syntax_flag;
2037
2038 if (ask_naked_reg == 0)
f86103b7
AM		 2039 allow_naked_reg = (intel_syntax
2040 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2041 else
2042 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2043
ee86248c 2044 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2045
e4a3b5a4 2046 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2047 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2048 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2049}
2050
1efbbeb4
L		 2051static void
2052set_intel_mnemonic (int mnemonic_flag)
2053{
e1d4d893 2054 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2055}
2056
db51cc60
L		 2057static void
2058set_allow_index_reg (int flag)
2059{
2060 allow_index_reg = flag;
2061}
2062
cb19c032
L		 2063static void
2064set_sse_check (int dummy ATTRIBUTE_UNUSED)
2065{
2066 SKIP_WHITESPACE ();
2067
2068 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2069 {
2070 char *string = input_line_pointer;
2071 int e = get_symbol_end ();
2072
2073 if (strcmp (string, "none") == 0)
2074 sse_check = sse_check_none;
2075 else if (strcmp (string, "warning") == 0)
2076 sse_check = sse_check_warning;
2077 else if (strcmp (string, "error") == 0)
2078 sse_check = sse_check_error;
2079 else
2080 as_bad (_("bad argument to sse_check directive."));
2081 *input_line_pointer = e;
2082 }
2083 else
2084 as_bad (_("missing argument for sse_check directive"));
2085
2086 demand_empty_rest_of_line ();
2087}
2088
8a9036a4
L		 2089static void
2090check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2091 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2092{
2093#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2094 static const char *arch;
2095
2096 /* Intel LIOM is only supported on ELF. */
2097 if (!IS_ELF)
2098 return;
2099
2100 if (!arch)
2101 {
2102 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2103 use default_arch. */
2104 arch = cpu_arch_name;
2105 if (!arch)
2106 arch = default_arch;
2107 }
2108
3632d14b 2109 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2110 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2111 || new_flag.bitfield.cpul1om)
8a9036a4 2112 return;
76ba9986 2113
8a9036a4
L		 2114 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2115#endif
2116}
2117
e413e4e9 2118static void
e3bb37b5 2119set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2120{
47926f60 2121 SKIP_WHITESPACE ();
e413e4e9 2122
29b0f896 2123 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2124 {
2125 char *string = input_line_pointer;
2126 int e = get_symbol_end ();
91d6fa6a 2127 unsigned int j;
40fb9820 2128 i386_cpu_flags flags;
e413e4e9 2129
91d6fa6a 2130 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2131 {
91d6fa6a 2132 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2133 {
91d6fa6a 2134 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2135
5c6af06e
JB		 2136 if (*string != '.')
2137 {
91d6fa6a 2138 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2139 cpu_sub_arch_name = NULL;
91d6fa6a 2140 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2141 if (flag_code == CODE_64BIT)
2142 {
2143 cpu_arch_flags.bitfield.cpu64 = 1;
2144 cpu_arch_flags.bitfield.cpuno64 = 0;
2145 }
2146 else
2147 {
2148 cpu_arch_flags.bitfield.cpu64 = 0;
2149 cpu_arch_flags.bitfield.cpuno64 = 1;
2150 }
91d6fa6a
NC		 2151 cpu_arch_isa = cpu_arch[j].type;
2152 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2153 if (!cpu_arch_tune_set)
2154 {
2155 cpu_arch_tune = cpu_arch_isa;
2156 cpu_arch_tune_flags = cpu_arch_isa_flags;
2157 }
5c6af06e
JB		 2158 break;
2159 }
40fb9820 2160
22109423 2161 if (!cpu_arch[j].negated)
309d3373 2162 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2163 cpu_arch[j].flags);
309d3373
JB		 2164 else
2165 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2166 cpu_arch[j].flags);
0dfbf9d7 2167 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2168 {
6305a203
L		 2169 if (cpu_sub_arch_name)
2170 {
2171 char *name = cpu_sub_arch_name;
2172 cpu_sub_arch_name = concat (name,
91d6fa6a 2173 cpu_arch[j].name,
1bf57e9f 2174 (const char *) NULL);
6305a203
L		 2175 free (name);
2176 }
2177 else
91d6fa6a 2178 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2179 cpu_arch_flags = flags;
a586129e 2180 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2181 }
2182 *input_line_pointer = e;
2183 demand_empty_rest_of_line ();
2184 return;
e413e4e9
AM		 2185 }
2186 }
91d6fa6a 2187 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2188 as_bad (_("no such architecture: `%s'"), string);
2189
2190 *input_line_pointer = e;
2191 }
2192 else
2193 as_bad (_("missing cpu architecture"));
2194
fddf5b5b
AM		 2195 no_cond_jump_promotion = 0;
2196 if (*input_line_pointer == ','
29b0f896 2197 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2198 {
2199 char *string = ++input_line_pointer;
2200 int e = get_symbol_end ();
2201
2202 if (strcmp (string, "nojumps") == 0)
2203 no_cond_jump_promotion = 1;
2204 else if (strcmp (string, "jumps") == 0)
2205 ;
2206 else
2207 as_bad (_("no such architecture modifier: `%s'"), string);
2208
2209 *input_line_pointer = e;
2210 }
2211
e413e4e9
AM		 2212 demand_empty_rest_of_line ();
2213}
2214
8a9036a4
L		 2215enum bfd_architecture
2216i386_arch (void)
2217{
3632d14b 2218 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2219 {
2220 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2221 || flag_code != CODE_64BIT)
2222 as_fatal (_("Intel L1OM is 64bit ELF only"));
2223 return bfd_arch_l1om;
2224 }
2225 else
2226 return bfd_arch_i386;
2227}
2228
b9d79e03
JH		 2229unsigned long
2230i386_mach ()
2231{
351f65ca 2232 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2233 {
3632d14b 2234 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2235 {
351f65ca
L		 2236 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2237 || default_arch[6] != '\0')
8a9036a4
L		 2238 as_fatal (_("Intel L1OM is 64bit ELF only"));
2239 return bfd_mach_l1om;
2240 }
351f65ca 2241 else if (default_arch[6] == '\0')
8a9036a4 2242 return bfd_mach_x86_64;
351f65ca
L		 2243 else
2244 return bfd_mach_x64_32;
8a9036a4 2245 }
b9d79e03
JH		 2246 else if (!strcmp (default_arch, "i386"))
2247 return bfd_mach_i386_i386;
2248 else
2249 as_fatal (_("Unknown architecture"));
2250}
b9d79e03 2251\f
252b5132
RH		 2252void
2253md_begin ()
2254{
2255 const char *hash_err;
2256
47926f60 2257 /* Initialize op_hash hash table. */
252b5132
RH		 2258 op_hash = hash_new ();
2259
2260 {
d3ce72d0 2261 const insn_template *optab;
29b0f896 2262 templates *core_optab;
252b5132 2263
47926f60
KH		 2264 /* Setup for loop. */
2265 optab = i386_optab;
252b5132
RH		 2266 core_optab = (templates *) xmalloc (sizeof (templates));
2267 core_optab->start = optab;
2268
2269 while (1)
2270 {
2271 ++optab;
2272 if (optab->name == NULL
2273 || strcmp (optab->name, (optab - 1)->name) != 0)
2274 {
2275 /* different name --> ship out current template list;
47926f60 2276 add to hash table; & begin anew. */
252b5132
RH		 2277 core_optab->end = optab;
2278 hash_err = hash_insert (op_hash,
2279 (optab - 1)->name,
5a49b8ac 2280 (void *) core_optab);
252b5132
RH		 2281 if (hash_err)
2282 {
252b5132
RH		 2283 as_fatal (_("Internal Error: Can't hash %s: %s"),
2284 (optab - 1)->name,
2285 hash_err);
2286 }
2287 if (optab->name == NULL)
2288 break;
2289 core_optab = (templates *) xmalloc (sizeof (templates));
2290 core_optab->start = optab;
2291 }
2292 }
2293 }
2294
47926f60 2295 /* Initialize reg_hash hash table. */
252b5132
RH		 2296 reg_hash = hash_new ();
2297 {
29b0f896 2298 const reg_entry *regtab;
c3fe08fa 2299 unsigned int regtab_size = i386_regtab_size;
252b5132 2300
c3fe08fa 2301 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2302 {
5a49b8ac 2303 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2304 if (hash_err)
3e73aa7c
JH		 2305 as_fatal (_("Internal Error: Can't hash %s: %s"),
2306 regtab->reg_name,
2307 hash_err);
252b5132
RH		 2308 }
2309 }
2310
47926f60 2311 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2312 {
29b0f896
AM		 2313 int c;
2314 char *p;
252b5132
RH		 2315
2316 for (c = 0; c < 256; c++)
2317 {
3882b010 2318 if (ISDIGIT (c))
252b5132
RH		 2319 {
2320 digit_chars[c] = c;
2321 mnemonic_chars[c] = c;
2322 register_chars[c] = c;
2323 operand_chars[c] = c;
2324 }
3882b010 2325 else if (ISLOWER (c))
252b5132
RH		 2326 {
2327 mnemonic_chars[c] = c;
2328 register_chars[c] = c;
2329 operand_chars[c] = c;
2330 }
3882b010 2331 else if (ISUPPER (c))
252b5132 2332 {
3882b010 2333 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2334 register_chars[c] = mnemonic_chars[c];
2335 operand_chars[c] = c;
2336 }
2337
3882b010 2338 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2339 identifier_chars[c] = c;
2340 else if (c >= 128)
2341 {
2342 identifier_chars[c] = c;
2343 operand_chars[c] = c;
2344 }
2345 }
2346
2347#ifdef LEX_AT
2348 identifier_chars['@'] = '@';
32137342
NC		 2349#endif
2350#ifdef LEX_QM
2351 identifier_chars['?'] = '?';
2352 operand_chars['?'] = '?';
252b5132 2353#endif
252b5132 2354 digit_chars['-'] = '-';
c0f3af97 2355 mnemonic_chars['_'] = '_';
791fe849 2356 mnemonic_chars['-'] = '-';
0003779b 2357 mnemonic_chars['.'] = '.';
252b5132
RH		 2358 identifier_chars['_'] = '_';
2359 identifier_chars['.'] = '.';
2360
2361 for (p = operand_special_chars; *p != '\0'; p++)
2362 operand_chars[(unsigned char) *p] = *p;
2363 }
2364
2365#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2366 if (IS_ELF)
252b5132
RH		 2367 {
2368 record_alignment (text_section, 2);
2369 record_alignment (data_section, 2);
2370 record_alignment (bss_section, 2);
2371 }
2372#endif
a4447b93
RH		 2373
2374 if (flag_code == CODE_64BIT)
2375 {
ca19b261
KT		 2376#if defined (OBJ_COFF) && defined (TE_PE)
2377 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2378 ? 32 : 16);
2379#else
a4447b93 2380 x86_dwarf2_return_column = 16;
ca19b261 2381#endif
61ff971f 2382 x86_cie_data_alignment = -8;
a4447b93
RH		 2383 }
2384 else
2385 {
2386 x86_dwarf2_return_column = 8;
2387 x86_cie_data_alignment = -4;
2388 }
252b5132
RH		 2389}
2390
2391void
e3bb37b5 2392i386_print_statistics (FILE *file)
252b5132
RH		 2393{
2394 hash_print_statistics (file, "i386 opcode", op_hash);
2395 hash_print_statistics (file, "i386 register", reg_hash);
2396}
2397\f
252b5132
RH		 2398#ifdef DEBUG386
2399
ce8a8b2f 2400/* Debugging routines for md_assemble. */
d3ce72d0 2401static void pte (insn_template *);
40fb9820 2402static void pt (i386_operand_type);
e3bb37b5
L		 2403static void pe (expressionS *);
2404static void ps (symbolS *);
252b5132
RH		 2405
2406static void
e3bb37b5 2407pi (char *line, i386_insn *x)
252b5132 2408{
09137c09 2409 unsigned int j;
252b5132
RH		 2410
2411 fprintf (stdout, "%s: template ", line);
2412 pte (&x->tm);
09f131f2
JH		 2413 fprintf (stdout, " address: base %s index %s scale %x\n",
2414 x->base_reg ? x->base_reg->reg_name : "none",
2415 x->index_reg ? x->index_reg->reg_name : "none",
2416 x->log2_scale_factor);
2417 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2418 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2419 fprintf (stdout, " sib: base %x index %x scale %x\n",
2420 x->sib.base, x->sib.index, x->sib.scale);
2421 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2422 (x->rex & REX_W) != 0,
2423 (x->rex & REX_R) != 0,
2424 (x->rex & REX_X) != 0,
2425 (x->rex & REX_B) != 0);
09137c09 2426 for (j = 0; j < x->operands; j++)
252b5132 2427 {
09137c09
SP		 2428 fprintf (stdout, " #%d: ", j + 1);
2429 pt (x->types[j]);
252b5132 2430 fprintf (stdout, "\n");
09137c09
SP		 2431 if (x->types[j].bitfield.reg8
2432 || x->types[j].bitfield.reg16
2433 || x->types[j].bitfield.reg32
2434 || x->types[j].bitfield.reg64
2435 || x->types[j].bitfield.regmmx
2436 || x->types[j].bitfield.regxmm
2437 || x->types[j].bitfield.regymm
2438 || x->types[j].bitfield.sreg2
2439 || x->types[j].bitfield.sreg3
2440 || x->types[j].bitfield.control
2441 || x->types[j].bitfield.debug
2442 || x->types[j].bitfield.test)
2443 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2444 if (operand_type_check (x->types[j], imm))
2445 pe (x->op[j].imms);
2446 if (operand_type_check (x->types[j], disp))
2447 pe (x->op[j].disps);
252b5132
RH		 2448 }
2449}
2450
2451static void
d3ce72d0 2452pte (insn_template *t)
252b5132 2453{
09137c09 2454 unsigned int j;
252b5132 2455 fprintf (stdout, " %d operands ", t->operands);
47926f60 2456 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2457 if (t->extension_opcode != None)
2458 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2459 if (t->opcode_modifier.d)
252b5132 2460 fprintf (stdout, "D");
40fb9820 2461 if (t->opcode_modifier.w)
252b5132
RH		 2462 fprintf (stdout, "W");
2463 fprintf (stdout, "\n");
09137c09 2464 for (j = 0; j < t->operands; j++)
252b5132 2465 {
09137c09
SP		 2466 fprintf (stdout, " #%d type ", j + 1);
2467 pt (t->operand_types[j]);
252b5132
RH		 2468 fprintf (stdout, "\n");
2469 }
2470}
2471
2472static void
e3bb37b5 2473pe (expressionS *e)
252b5132 2474{
24eab124 2475 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2476 fprintf (stdout, " add_number %ld (%lx)\n",
2477 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2478 if (e->X_add_symbol)
2479 {
2480 fprintf (stdout, " add_symbol ");
2481 ps (e->X_add_symbol);
2482 fprintf (stdout, "\n");
2483 }
2484 if (e->X_op_symbol)
2485 {
2486 fprintf (stdout, " op_symbol ");
2487 ps (e->X_op_symbol);
2488 fprintf (stdout, "\n");
2489 }
2490}
2491
2492static void
e3bb37b5 2493ps (symbolS *s)
252b5132
RH		 2494{
2495 fprintf (stdout, "%s type %s%s",
2496 S_GET_NAME (s),
2497 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2498 segment_name (S_GET_SEGMENT (s)));
2499}
2500
7b81dfbb 2501static struct type_name
252b5132 2502 {
40fb9820
L		 2503 i386_operand_type mask;
2504 const char *name;
252b5132 2505 }
7b81dfbb 2506const type_names[] =
252b5132 2507{
40fb9820
L		 2508 { OPERAND_TYPE_REG8, "r8" },
2509 { OPERAND_TYPE_REG16, "r16" },
2510 { OPERAND_TYPE_REG32, "r32" },
2511 { OPERAND_TYPE_REG64, "r64" },
2512 { OPERAND_TYPE_IMM8, "i8" },
2513 { OPERAND_TYPE_IMM8, "i8s" },
2514 { OPERAND_TYPE_IMM16, "i16" },
2515 { OPERAND_TYPE_IMM32, "i32" },
2516 { OPERAND_TYPE_IMM32S, "i32s" },
2517 { OPERAND_TYPE_IMM64, "i64" },
2518 { OPERAND_TYPE_IMM1, "i1" },
2519 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2520 { OPERAND_TYPE_DISP8, "d8" },
2521 { OPERAND_TYPE_DISP16, "d16" },
2522 { OPERAND_TYPE_DISP32, "d32" },
2523 { OPERAND_TYPE_DISP32S, "d32s" },
2524 { OPERAND_TYPE_DISP64, "d64" },
2525 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2526 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2527 { OPERAND_TYPE_CONTROL, "control reg" },
2528 { OPERAND_TYPE_TEST, "test reg" },
2529 { OPERAND_TYPE_DEBUG, "debug reg" },
2530 { OPERAND_TYPE_FLOATREG, "FReg" },
2531 { OPERAND_TYPE_FLOATACC, "FAcc" },
2532 { OPERAND_TYPE_SREG2, "SReg2" },
2533 { OPERAND_TYPE_SREG3, "SReg3" },
2534 { OPERAND_TYPE_ACC, "Acc" },
2535 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2536 { OPERAND_TYPE_REGMMX, "rMMX" },
2537 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2538 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2539 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2540};
2541
2542static void
40fb9820 2543pt (i386_operand_type t)
252b5132 2544{
40fb9820 2545 unsigned int j;
c6fb90c8 2546 i386_operand_type a;
252b5132 2547
40fb9820 2548 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2549 {
2550 a = operand_type_and (t, type_names[j].mask);
0349dc08 2551 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2552 fprintf (stdout, "%s, ", type_names[j].name);
2553 }
252b5132
RH		 2554 fflush (stdout);
2555}
2556
2557#endif /* DEBUG386 */
2558\f
252b5132 2559static bfd_reloc_code_real_type
3956db08 2560reloc (unsigned int size,
64e74474
AM		 2561 int pcrel,
2562 int sign,
2563 bfd_reloc_code_real_type other)
252b5132 2564{
47926f60 2565 if (other != NO_RELOC)
3956db08 2566 {
91d6fa6a 2567 reloc_howto_type *rel;
3956db08
JB		 2568
2569 if (size == 8)
2570 switch (other)
2571 {
64e74474
AM		 2572 case BFD_RELOC_X86_64_GOT32:
2573 return BFD_RELOC_X86_64_GOT64;
2574 break;
2575 case BFD_RELOC_X86_64_PLTOFF64:
2576 return BFD_RELOC_X86_64_PLTOFF64;
2577 break;
2578 case BFD_RELOC_X86_64_GOTPC32:
2579 other = BFD_RELOC_X86_64_GOTPC64;
2580 break;
2581 case BFD_RELOC_X86_64_GOTPCREL:
2582 other = BFD_RELOC_X86_64_GOTPCREL64;
2583 break;
2584 case BFD_RELOC_X86_64_TPOFF32:
2585 other = BFD_RELOC_X86_64_TPOFF64;
2586 break;
2587 case BFD_RELOC_X86_64_DTPOFF32:
2588 other = BFD_RELOC_X86_64_DTPOFF64;
2589 break;
2590 default:
2591 break;
3956db08 2592 }
e05278af
JB		 2593
2594 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2595 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2596 sign = -1;
2597
91d6fa6a
NC		 2598 rel = bfd_reloc_type_lookup (stdoutput, other);
2599 if (!rel)
3956db08 2600 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2601 else if (size != bfd_get_reloc_size (rel))
3956db08 2602 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2603 bfd_get_reloc_size (rel),
3956db08 2604 size);
91d6fa6a 2605 else if (pcrel && !rel->pc_relative)
3956db08 2606 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2607 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2608 && !sign)
91d6fa6a 2609 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2610 && sign > 0))
3956db08
JB		 2611 as_bad (_("relocated field and relocation type differ in signedness"));
2612 else
2613 return other;
2614 return NO_RELOC;
2615 }
252b5132
RH		 2616
2617 if (pcrel)
2618 {
3e73aa7c 2619 if (!sign)
3956db08 2620 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2621 switch (size)
2622 {
2623 case 1: return BFD_RELOC_8_PCREL;
2624 case 2: return BFD_RELOC_16_PCREL;
2625 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2626 case 8: return BFD_RELOC_64_PCREL;
252b5132 2627 }
3956db08 2628 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2629 }
2630 else
2631 {
3956db08 2632 if (sign > 0)
e5cb08ac 2633 switch (size)
3e73aa7c
JH		 2634 {
2635 case 4: return BFD_RELOC_X86_64_32S;
2636 }
2637 else
2638 switch (size)
2639 {
2640 case 1: return BFD_RELOC_8;
2641 case 2: return BFD_RELOC_16;
2642 case 4: return BFD_RELOC_32;
2643 case 8: return BFD_RELOC_64;
2644 }
3956db08
JB		 2645 as_bad (_("cannot do %s %u byte relocation"),
2646 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2647 }
2648
0cc9e1d3 2649 return NO_RELOC;
252b5132
RH		 2650}
2651
47926f60
KH		 2652/* Here we decide which fixups can be adjusted to make them relative to
2653 the beginning of the section instead of the symbol. Basically we need
2654 to make sure that the dynamic relocations are done correctly, so in
2655 some cases we force the original symbol to be used. */
2656
252b5132 2657int
e3bb37b5 2658tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2659{
6d249963 2660#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2661 if (!IS_ELF)
31312f95
AM		 2662 return 1;
2663
a161fe53
AM		 2664 /* Don't adjust pc-relative references to merge sections in 64-bit
2665 mode. */
2666 if (use_rela_relocations
2667 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2668 && fixP->fx_pcrel)
252b5132 2669 return 0;
31312f95 2670
8d01d9a9
AJ		 2671 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2672 and changed later by validate_fix. */
2673 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2674 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2675 return 0;
2676
ce8a8b2f 2677 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2678 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2679 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2680 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2681 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2682 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2683 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2684 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2685 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2686 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2687 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2688 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2689 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2690 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2691 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2692 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2693 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2694 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2695 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2696 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2697 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2698 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2699 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2700 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2701 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2702 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2703 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2704 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2705 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2706 return 0;
31312f95 2707#endif
252b5132
RH		 2708 return 1;
2709}
252b5132 2710
b4cac588 2711static int
e3bb37b5 2712intel_float_operand (const char *mnemonic)
252b5132 2713{
9306ca4a
JB		 2714 /* Note that the value returned is meaningful only for opcodes with (memory)
2715 operands, hence the code here is free to improperly handle opcodes that
2716 have no operands (for better performance and smaller code). */
2717
2718 if (mnemonic[0] != 'f')
2719 return 0; /* non-math */
2720
2721 switch (mnemonic[1])
2722 {
2723 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2724 the fs segment override prefix not currently handled because no
2725 call path can make opcodes without operands get here */
2726 case 'i':
2727 return 2 /* integer op */;
2728 case 'l':
2729 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2730 return 3; /* fldcw/fldenv */
2731 break;
2732 case 'n':
2733 if (mnemonic[2] != 'o' /* fnop */)
2734 return 3; /* non-waiting control op */
2735 break;
2736 case 'r':
2737 if (mnemonic[2] == 's')
2738 return 3; /* frstor/frstpm */
2739 break;
2740 case 's':
2741 if (mnemonic[2] == 'a')
2742 return 3; /* fsave */
2743 if (mnemonic[2] == 't')
2744 {
2745 switch (mnemonic[3])
2746 {
2747 case 'c': /* fstcw */
2748 case 'd': /* fstdw */
2749 case 'e': /* fstenv */
2750 case 's': /* fsts[gw] */
2751 return 3;
2752 }
2753 }
2754 break;
2755 case 'x':
2756 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2757 return 0; /* fxsave/fxrstor are not really math ops */
2758 break;
2759 }
252b5132 2760
9306ca4a 2761 return 1;
252b5132
RH		 2762}
2763
c0f3af97
L		 2764/* Build the VEX prefix. */
2765
2766static void
d3ce72d0 2767build_vex_prefix (const insn_template *t)
c0f3af97
L		 2768{
2769 unsigned int register_specifier;
2770 unsigned int implied_prefix;
2771 unsigned int vector_length;
2772
2773 /* Check register specifier. */
2774 if (i.vex.register_specifier)
2775 {
2776 register_specifier = i.vex.register_specifier->reg_num;
2777 if ((i.vex.register_specifier->reg_flags & RegRex))
2778 register_specifier += 8;
2779 register_specifier = ~register_specifier & 0xf;
2780 }
2781 else
2782 register_specifier = 0xf;
2783
fa99fab2
L		 2784 /* Use 2-byte VEX prefix by swappping destination and source
2785 operand. */
2786 if (!i.swap_operand
2787 && i.operands == i.reg_operands
7f399153 2788 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2789 && i.tm.opcode_modifier.s
2790 && i.rex == REX_B)
2791 {
2792 unsigned int xchg = i.operands - 1;
2793 union i386_op temp_op;
2794 i386_operand_type temp_type;
2795
2796 temp_type = i.types[xchg];
2797 i.types[xchg] = i.types[0];
2798 i.types[0] = temp_type;
2799 temp_op = i.op[xchg];
2800 i.op[xchg] = i.op[0];
2801 i.op[0] = temp_op;
2802
9c2799c2 2803 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2804
2805 i.rex = REX_R;
2806 xchg = i.rm.regmem;
2807 i.rm.regmem = i.rm.reg;
2808 i.rm.reg = xchg;
2809
2810 /* Use the next insn. */
2811 i.tm = t[1];
2812 }
2813
539f890d
L		 2814 if (i.tm.opcode_modifier.vex == VEXScalar)
2815 vector_length = avxscalar;
2816 else
2817 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2818
2819 switch ((i.tm.base_opcode >> 8) & 0xff)
2820 {
2821 case 0:
2822 implied_prefix = 0;
2823 break;
2824 case DATA_PREFIX_OPCODE:
2825 implied_prefix = 1;
2826 break;
2827 case REPE_PREFIX_OPCODE:
2828 implied_prefix = 2;
2829 break;
2830 case REPNE_PREFIX_OPCODE:
2831 implied_prefix = 3;
2832 break;
2833 default:
2834 abort ();
2835 }
2836
2837 /* Use 2-byte VEX prefix if possible. */
7f399153 2838 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2839 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2840 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2841 {
2842 /* 2-byte VEX prefix. */
2843 unsigned int r;
2844
2845 i.vex.length = 2;
2846 i.vex.bytes[0] = 0xc5;
2847
2848 /* Check the REX.R bit. */
2849 r = (i.rex & REX_R) ? 0 : 1;
2850 i.vex.bytes[1] = (r << 7
2851 | register_specifier << 3
2852 | vector_length << 2
2853 | implied_prefix);
2854 }
2855 else
2856 {
2857 /* 3-byte VEX prefix. */
2858 unsigned int m, w;
2859
f88c9eb0 2860 i.vex.length = 3;
f88c9eb0 2861
7f399153 2862 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2863 {
7f399153
L		 2864 case VEX0F:
2865 m = 0x1;
80de6e00 2866 i.vex.bytes[0] = 0xc4;
7f399153
L		 2867 break;
2868 case VEX0F38:
2869 m = 0x2;
80de6e00 2870 i.vex.bytes[0] = 0xc4;
7f399153
L		 2871 break;
2872 case VEX0F3A:
2873 m = 0x3;
80de6e00 2874 i.vex.bytes[0] = 0xc4;
7f399153
L		 2875 break;
2876 case XOP08:
5dd85c99
SP		 2877 m = 0x8;
2878 i.vex.bytes[0] = 0x8f;
7f399153
L		 2879 break;
2880 case XOP09:
f88c9eb0
SP		 2881 m = 0x9;
2882 i.vex.bytes[0] = 0x8f;
7f399153
L		 2883 break;
2884 case XOP0A:
f88c9eb0
SP		 2885 m = 0xa;
2886 i.vex.bytes[0] = 0x8f;
7f399153
L		 2887 break;
2888 default:
2889 abort ();
f88c9eb0 2890 }
c0f3af97 2891
c0f3af97
L		 2892 /* The high 3 bits of the second VEX byte are 1's compliment
2893 of RXB bits from REX. */
2894 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2895
2896 /* Check the REX.W bit. */
2897 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2898 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2899 {
2900 if (w)
2901 abort ();
2902
1ef99a7b 2903 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2904 w = 1;
2905 }
2906
2907 i.vex.bytes[2] = (w << 7
2908 | register_specifier << 3
2909 | vector_length << 2
2910 | implied_prefix);
2911 }
2912}
2913
65da13b5
L		 2914static void
2915process_immext (void)
2916{
2917 expressionS *exp;
2918
2919 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2920 {
1fed0ba1
L		 2921 /* SSE3 Instructions have the fixed operands with an opcode
2922 suffix which is coded in the same place as an 8-bit immediate
2923 field would be. Here we check those operands and remove them
2924 afterwards. */
65da13b5
L		 2925 unsigned int x;
2926
2927 for (x = 0; x < i.operands; x++)
2928 if (i.op[x].regs->reg_num != x)
2929 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2930 register_prefix, i.op[x].regs->reg_name, x + 1,
2931 i.tm.name);
2932
2933 i.operands = 0;
65da13b5
L		 2934 }
2935
c0f3af97 2936 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2937 which is coded in the same place as an 8-bit immediate field
2938 would be. Here we fake an 8-bit immediate operand from the
2939 opcode suffix stored in tm.extension_opcode.
2940
c1e679ec 2941 AVX instructions also use this encoding, for some of
c0f3af97 2942 3 argument instructions. */
65da13b5 2943
9c2799c2 2944 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2945 && (i.operands <= 2
2946 || (i.tm.opcode_modifier.vex
2947 && i.operands <= 4)));
65da13b5
L		 2948
2949 exp = &im_expressions[i.imm_operands++];
2950 i.op[i.operands].imms = exp;
2951 i.types[i.operands] = imm8;
2952 i.operands++;
2953 exp->X_op = O_constant;
2954 exp->X_add_number = i.tm.extension_opcode;
2955 i.tm.extension_opcode = None;
2956}
2957
252b5132
RH		 2958/* This is the guts of the machine-dependent assembler. LINE points to a
2959 machine dependent instruction. This function is supposed to emit
2960 the frags/bytes it assembles to. */
2961
2962void
65da13b5 2963md_assemble (char *line)
252b5132 2964{
40fb9820 2965 unsigned int j;
252b5132 2966 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2967 const insn_template *t;
252b5132 2968
47926f60 2969 /* Initialize globals. */
252b5132
RH		 2970 memset (&i, '\0', sizeof (i));
2971 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2972 i.reloc[j] = NO_RELOC;
252b5132
RH		 2973 memset (disp_expressions, '\0', sizeof (disp_expressions));
2974 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2975 save_stack_p = save_stack;
252b5132
RH		 2976
2977 /* First parse an instruction mnemonic & call i386_operand for the operands.
2978 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2979 start of a (possibly prefixed) mnemonic. */
252b5132 2980
29b0f896
AM		 2981 line = parse_insn (line, mnemonic);
2982 if (line == NULL)
2983 return;
252b5132 2984
29b0f896 2985 line = parse_operands (line, mnemonic);
ee86248c 2986 this_operand = -1;
29b0f896
AM		 2987 if (line == NULL)
2988 return;
252b5132 2989
29b0f896
AM		 2990 /* Now we've parsed the mnemonic into a set of templates, and have the
2991 operands at hand. */
2992
2993 /* All intel opcodes have reversed operands except for "bound" and
2994 "enter". We also don't reverse intersegment "jmp" and "call"
2995 instructions with 2 immediate operands so that the immediate segment
050dfa73 2996 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2997 if (intel_syntax
2998 && i.operands > 1
29b0f896 2999 && (strcmp (mnemonic, "bound") != 0)
30123838 3000 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3001 && !(operand_type_check (i.types[0], imm)
3002 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3003 swap_operands ();
3004
ec56d5c0
JB		 3005 /* The order of the immediates should be reversed
3006 for 2 immediates extrq and insertq instructions */
3007 if (i.imm_operands == 2
3008 && (strcmp (mnemonic, "extrq") == 0
3009 || strcmp (mnemonic, "insertq") == 0))
3010 swap_2_operands (0, 1);
3011
29b0f896
AM		 3012 if (i.imm_operands)
3013 optimize_imm ();
3014
b300c311
L		 3015 /* Don't optimize displacement for movabs since it only takes 64bit
3016 displacement. */
3017 if (i.disp_operands
862be3fb
L		 3018 && !i.disp32_encoding
3019 && (flag_code != CODE_64BIT
3020 || strcmp (mnemonic, "movabs") != 0))
3021 optimize_disp ();
29b0f896
AM		 3022
3023 /* Next, we find a template that matches the given insn,
3024 making sure the overlap of the given operands types is consistent
3025 with the template operand types. */
252b5132 3026
fa99fab2 3027 if (!(t = match_template ()))
29b0f896 3028 return;
252b5132 3029
daf50ae7 3030 if (sse_check != sse_check_none
81f8a913 3031 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3032 && (i.tm.cpu_flags.bitfield.cpusse
3033 || i.tm.cpu_flags.bitfield.cpusse2
3034 || i.tm.cpu_flags.bitfield.cpusse3
3035 || i.tm.cpu_flags.bitfield.cpussse3
3036 || i.tm.cpu_flags.bitfield.cpusse4_1
3037 || i.tm.cpu_flags.bitfield.cpusse4_2))
3038 {
3039 (sse_check == sse_check_warning
3040 ? as_warn
3041 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3042 }
3043
321fd21e
L		 3044 /* Zap movzx and movsx suffix. The suffix has been set from
3045 "word ptr" or "byte ptr" on the source operand in Intel syntax
3046 or extracted from mnemonic in AT&T syntax. But we'll use
3047 the destination register to choose the suffix for encoding. */
3048 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3049 {
321fd21e
L		 3050 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3051 there is no suffix, the default will be byte extension. */
3052 if (i.reg_operands != 2
3053 && !i.suffix
7ab9ffdd 3054 && intel_syntax)
321fd21e
L		 3055 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3056
3057 i.suffix = 0;
cd61ebfe 3058 }
24eab124 3059
40fb9820 3060 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3061 if (!add_prefix (FWAIT_OPCODE))
3062 return;
252b5132 3063
c1ba0266
L		 3064 /* Check for lock without a lockable instruction. Destination operand
3065 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3066 if (i.prefix[LOCK_PREFIX]
3067 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3068 || i.mem_operands == 0
3069 || (i.tm.base_opcode != 0x86
3070 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3071 {
3072 as_bad (_("expecting lockable instruction after `lock'"));
3073 return;
3074 }
3075
29b0f896 3076 /* Check string instruction segment overrides. */
40fb9820 3077 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3078 {
3079 if (!check_string ())
5dd0794d 3080 return;
fc0763e6 3081 i.disp_operands = 0;
29b0f896 3082 }
5dd0794d 3083
29b0f896
AM		 3084 if (!process_suffix ())
3085 return;
e413e4e9 3086
bc0844ae
L		 3087 /* Update operand types. */
3088 for (j = 0; j < i.operands; j++)
3089 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3090
29b0f896
AM		 3091 /* Make still unresolved immediate matches conform to size of immediate
3092 given in i.suffix. */
3093 if (!finalize_imm ())
3094 return;
252b5132 3095
40fb9820 3096 if (i.types[0].bitfield.imm1)
29b0f896 3097 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3098
9afe6eb8
L		 3099 /* We only need to check those implicit registers for instructions
3100 with 3 operands or less. */
3101 if (i.operands <= 3)
3102 for (j = 0; j < i.operands; j++)
3103 if (i.types[j].bitfield.inoutportreg
3104 || i.types[j].bitfield.shiftcount
3105 || i.types[j].bitfield.acc
3106 || i.types[j].bitfield.floatacc)
3107 i.reg_operands--;
40fb9820 3108
c0f3af97
L		 3109 /* ImmExt should be processed after SSE2AVX. */
3110 if (!i.tm.opcode_modifier.sse2avx
3111 && i.tm.opcode_modifier.immext)
65da13b5 3112 process_immext ();
252b5132 3113
29b0f896
AM		 3114 /* For insns with operands there are more diddles to do to the opcode. */
3115 if (i.operands)
3116 {
3117 if (!process_operands ())
3118 return;
3119 }
40fb9820 3120 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3121 {
3122 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3123 as_warn (_("translating to `%sp'"), i.tm.name);
3124 }
252b5132 3125
c0f3af97 3126 if (i.tm.opcode_modifier.vex)
fa99fab2 3127 build_vex_prefix (t);
c0f3af97 3128
5dd85c99
SP		 3129 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3130 instructions may define INT_OPCODE as well, so avoid this corner
3131 case for those instructions that use MODRM. */
3132 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3133 && !i.tm.opcode_modifier.modrm
3134 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3135 {
3136 i.tm.base_opcode = INT3_OPCODE;
3137 i.imm_operands = 0;
3138 }
252b5132 3139
40fb9820
L		 3140 if ((i.tm.opcode_modifier.jump
3141 || i.tm.opcode_modifier.jumpbyte
3142 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3143 && i.op[0].disps->X_op == O_constant)
3144 {
3145 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3146 the absolute address given by the constant. Since ix86 jumps and
3147 calls are pc relative, we need to generate a reloc. */
3148 i.op[0].disps->X_add_symbol = &abs_symbol;
3149 i.op[0].disps->X_op = O_symbol;
3150 }
252b5132 3151
40fb9820 3152 if (i.tm.opcode_modifier.rex64)
161a04f6 3153 i.rex |= REX_W;
252b5132 3154
29b0f896
AM		 3155 /* For 8 bit registers we need an empty rex prefix. Also if the
3156 instruction already has a prefix, we need to convert old
3157 registers to new ones. */
773f551c 3158
40fb9820 3159 if ((i.types[0].bitfield.reg8
29b0f896 3160 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3161 || (i.types[1].bitfield.reg8
29b0f896 3162 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3163 || ((i.types[0].bitfield.reg8
3164 || i.types[1].bitfield.reg8)
29b0f896
AM		 3165 && i.rex != 0))
3166 {
3167 int x;
726c5dcd 3168
29b0f896
AM		 3169 i.rex |= REX_OPCODE;
3170 for (x = 0; x < 2; x++)
3171 {
3172 /* Look for 8 bit operand that uses old registers. */
40fb9820 3173 if (i.types[x].bitfield.reg8
29b0f896 3174 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3175 {
29b0f896
AM		 3176 /* In case it is "hi" register, give up. */
3177 if (i.op[x].regs->reg_num > 3)
a540244d 3178 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3179 "instruction requiring REX prefix."),
a540244d 3180 register_prefix, i.op[x].regs->reg_name);
773f551c 3181
29b0f896
AM		 3182 /* Otherwise it is equivalent to the extended register.
3183 Since the encoding doesn't change this is merely
3184 cosmetic cleanup for debug output. */
3185
3186 i.op[x].regs = i.op[x].regs + 8;
773f551c 3187 }
29b0f896
AM		 3188 }
3189 }
773f551c 3190
7ab9ffdd 3191 if (i.rex != 0)
29b0f896
AM		 3192 add_prefix (REX_OPCODE | i.rex);
3193
3194 /* We are ready to output the insn. */
3195 output_insn ();
3196}
3197
3198static char *
e3bb37b5 3199parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3200{
3201 char *l = line;
3202 char *token_start = l;
3203 char *mnem_p;
5c6af06e 3204 int supported;
d3ce72d0 3205 const insn_template *t;
b6169b20 3206 char *dot_p = NULL;
29b0f896
AM		 3207
3208 /* Non-zero if we found a prefix only acceptable with string insns. */
3209 const char *expecting_string_instruction = NULL;
45288df1 3210
29b0f896
AM		 3211 while (1)
3212 {
3213 mnem_p = mnemonic;
3214 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3215 {
b6169b20
L		 3216 if (*mnem_p == '.')
3217 dot_p = mnem_p;
29b0f896
AM		 3218 mnem_p++;
3219 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3220 {
29b0f896
AM		 3221 as_bad (_("no such instruction: `%s'"), token_start);
3222 return NULL;
3223 }
3224 l++;
3225 }
3226 if (!is_space_char (*l)
3227 && *l != END_OF_INSN
e44823cf
JB		 3228 && (intel_syntax
3229 || (*l != PREFIX_SEPARATOR
3230 && *l != ',')))
29b0f896
AM		 3231 {
3232 as_bad (_("invalid character %s in mnemonic"),
3233 output_invalid (*l));
3234 return NULL;
3235 }
3236 if (token_start == l)
3237 {
e44823cf 3238 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3239 as_bad (_("expecting prefix; got nothing"));
3240 else
3241 as_bad (_("expecting mnemonic; got nothing"));
3242 return NULL;
3243 }
45288df1 3244
29b0f896 3245 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3246 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3247
29b0f896
AM		 3248 if (*l != END_OF_INSN
3249 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3250 && current_templates
40fb9820 3251 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3252 {
c6fb90c8 3253 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3254 {
3255 as_bad ((flag_code != CODE_64BIT
3256 ? _("`%s' is only supported in 64-bit mode")
3257 : _("`%s' is not supported in 64-bit mode")),
3258 current_templates->start->name);
3259 return NULL;
3260 }
29b0f896
AM		 3261 /* If we are in 16-bit mode, do not allow addr16 or data16.
3262 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3263 if ((current_templates->start->opcode_modifier.size16
3264 || current_templates->start->opcode_modifier.size32)
29b0f896 3265 && flag_code != CODE_64BIT
40fb9820 3266 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3267 ^ (flag_code == CODE_16BIT)))
3268 {
3269 as_bad (_("redundant %s prefix"),
3270 current_templates->start->name);
3271 return NULL;
45288df1 3272 }
29b0f896
AM		 3273 /* Add prefix, checking for repeated prefixes. */
3274 switch (add_prefix (current_templates->start->base_opcode))
3275 {
c32fa91d 3276 case PREFIX_EXIST:
29b0f896 3277 return NULL;
c32fa91d 3278 case PREFIX_REP:
29b0f896
AM		 3279 expecting_string_instruction = current_templates->start->name;
3280 break;
c32fa91d
L		 3281 default:
3282 break;
29b0f896
AM		 3283 }
3284 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3285 token_start = ++l;
3286 }
3287 else
3288 break;
3289 }
45288df1 3290
30a55f88 3291 if (!current_templates)
b6169b20 3292 {
f8a5c266
L		 3293 /* Check if we should swap operand or force 32bit displacement in
3294 encoding. */
30a55f88
L		 3295 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3296 i.swap_operand = 1;
f8a5c266
L		 3297 else if (mnem_p - 4 == dot_p
3298 && dot_p[1] == 'd'
3299 && dot_p[2] == '3'
3300 && dot_p[3] == '2')
3301 i.disp32_encoding = 1;
30a55f88
L		 3302 else
3303 goto check_suffix;
3304 mnem_p = dot_p;
3305 *dot_p = '\0';
d3ce72d0 3306 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3307 }
3308
29b0f896
AM		 3309 if (!current_templates)
3310 {
b6169b20 3311check_suffix:
29b0f896
AM		 3312 /* See if we can get a match by trimming off a suffix. */
3313 switch (mnem_p[-1])
3314 {
3315 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3316 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3317 i.suffix = SHORT_MNEM_SUFFIX;
3318 else
29b0f896
AM		 3319 case BYTE_MNEM_SUFFIX:
3320 case QWORD_MNEM_SUFFIX:
3321 i.suffix = mnem_p[-1];
3322 mnem_p[-1] = '\0';
d3ce72d0
NC		 3323 current_templates = (const templates *) hash_find (op_hash,
3324 mnemonic);
29b0f896
AM		 3325 break;
3326 case SHORT_MNEM_SUFFIX:
3327 case LONG_MNEM_SUFFIX:
3328 if (!intel_syntax)
3329 {
3330 i.suffix = mnem_p[-1];
3331 mnem_p[-1] = '\0';
d3ce72d0
NC		 3332 current_templates = (const templates *) hash_find (op_hash,
3333 mnemonic);
29b0f896
AM		 3334 }
3335 break;
252b5132 3336
29b0f896
AM		 3337 /* Intel Syntax. */
3338 case 'd':
3339 if (intel_syntax)
3340 {
9306ca4a 3341 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3342 i.suffix = SHORT_MNEM_SUFFIX;
3343 else
3344 i.suffix = LONG_MNEM_SUFFIX;
3345 mnem_p[-1] = '\0';
d3ce72d0
NC		 3346 current_templates = (const templates *) hash_find (op_hash,
3347 mnemonic);
29b0f896
AM		 3348 }
3349 break;
3350 }
3351 if (!current_templates)
3352 {
3353 as_bad (_("no such instruction: `%s'"), token_start);
3354 return NULL;
3355 }
3356 }
252b5132 3357
40fb9820
L		 3358 if (current_templates->start->opcode_modifier.jump
3359 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3360 {
3361 /* Check for a branch hint. We allow ",pt" and ",pn" for
3362 predict taken and predict not taken respectively.
3363 I'm not sure that branch hints actually do anything on loop
3364 and jcxz insns (JumpByte) for current Pentium4 chips. They
3365 may work in the future and it doesn't hurt to accept them
3366 now. */
3367 if (l[0] == ',' && l[1] == 'p')
3368 {
3369 if (l[2] == 't')
3370 {
3371 if (!add_prefix (DS_PREFIX_OPCODE))
3372 return NULL;
3373 l += 3;
3374 }
3375 else if (l[2] == 'n')
3376 {
3377 if (!add_prefix (CS_PREFIX_OPCODE))
3378 return NULL;
3379 l += 3;
3380 }
3381 }
3382 }
3383 /* Any other comma loses. */
3384 if (*l == ',')
3385 {
3386 as_bad (_("invalid character %s in mnemonic"),
3387 output_invalid (*l));
3388 return NULL;
3389 }
252b5132 3390
29b0f896 3391 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3392 supported = 0;
3393 for (t = current_templates->start; t < current_templates->end; ++t)
3394 {
c0f3af97
L		 3395 supported |= cpu_flags_match (t);
3396 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3397 goto skip;
5c6af06e 3398 }
3629bb00 3399
c0f3af97 3400 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3401 {
3402 as_bad (flag_code == CODE_64BIT
3403 ? _("`%s' is not supported in 64-bit mode")
3404 : _("`%s' is only supported in 64-bit mode"),
3405 current_templates->start->name);
3406 return NULL;
3407 }
c0f3af97 3408 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3409 {
3629bb00 3410 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3411 current_templates->start->name,
41aacd83 3412 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3413 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3414 return NULL;
29b0f896 3415 }
3629bb00
L		 3416
3417skip:
3418 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3419 && (flag_code != CODE_16BIT))
29b0f896
AM		 3420 {
3421 as_warn (_("use .code16 to ensure correct addressing mode"));
3422 }
252b5132 3423
29b0f896 3424 /* Check for rep/repne without a string instruction. */
f41bbced 3425 if (expecting_string_instruction)
29b0f896 3426 {
f41bbced
JB		 3427 static templates override;
3428
3429 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3430 if (t->opcode_modifier.isstring)
f41bbced
JB		 3431 break;
3432 if (t >= current_templates->end)
3433 {
3434 as_bad (_("expecting string instruction after `%s'"),
64e74474 3435 expecting_string_instruction);
f41bbced
JB		 3436 return NULL;
3437 }
3438 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3439 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3440 break;
3441 override.end = t;
3442 current_templates = &override;
29b0f896 3443 }
252b5132 3444
29b0f896
AM		 3445 return l;
3446}
252b5132 3447
29b0f896 3448static char *
e3bb37b5 3449parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3450{
3451 char *token_start;
3138f287 3452
29b0f896
AM		 3453 /* 1 if operand is pending after ','. */
3454 unsigned int expecting_operand = 0;
252b5132 3455
29b0f896
AM		 3456 /* Non-zero if operand parens not balanced. */
3457 unsigned int paren_not_balanced;
3458
3459 while (*l != END_OF_INSN)
3460 {
3461 /* Skip optional white space before operand. */
3462 if (is_space_char (*l))
3463 ++l;
3464 if (!is_operand_char (*l) && *l != END_OF_INSN)
3465 {
3466 as_bad (_("invalid character %s before operand %d"),
3467 output_invalid (*l),
3468 i.operands + 1);
3469 return NULL;
3470 }
3471 token_start = l; /* after white space */
3472 paren_not_balanced = 0;
3473 while (paren_not_balanced || *l != ',')
3474 {
3475 if (*l == END_OF_INSN)
3476 {
3477 if (paren_not_balanced)
3478 {
3479 if (!intel_syntax)
3480 as_bad (_("unbalanced parenthesis in operand %d."),
3481 i.operands + 1);
3482 else
3483 as_bad (_("unbalanced brackets in operand %d."),
3484 i.operands + 1);
3485 return NULL;
3486 }
3487 else
3488 break; /* we are done */
3489 }
3490 else if (!is_operand_char (*l) && !is_space_char (*l))
3491 {
3492 as_bad (_("invalid character %s in operand %d"),
3493 output_invalid (*l),
3494 i.operands + 1);
3495 return NULL;
3496 }
3497 if (!intel_syntax)
3498 {
3499 if (*l == '(')
3500 ++paren_not_balanced;
3501 if (*l == ')')
3502 --paren_not_balanced;
3503 }
3504 else
3505 {
3506 if (*l == '[')
3507 ++paren_not_balanced;
3508 if (*l == ']')
3509 --paren_not_balanced;
3510 }
3511 l++;
3512 }
3513 if (l != token_start)
3514 { /* Yes, we've read in another operand. */
3515 unsigned int operand_ok;
3516 this_operand = i.operands++;
7d5e4556 3517 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3518 if (i.operands > MAX_OPERANDS)
3519 {
3520 as_bad (_("spurious operands; (%d operands/instruction max)"),
3521 MAX_OPERANDS);
3522 return NULL;
3523 }
3524 /* Now parse operand adding info to 'i' as we go along. */
3525 END_STRING_AND_SAVE (l);
3526
3527 if (intel_syntax)
3528 operand_ok =
3529 i386_intel_operand (token_start,
3530 intel_float_operand (mnemonic));
3531 else
a7619375 3532 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3533
3534 RESTORE_END_STRING (l);
3535 if (!operand_ok)
3536 return NULL;
3537 }
3538 else
3539 {
3540 if (expecting_operand)
3541 {
3542 expecting_operand_after_comma:
3543 as_bad (_("expecting operand after ','; got nothing"));
3544 return NULL;
3545 }
3546 if (*l == ',')
3547 {
3548 as_bad (_("expecting operand before ','; got nothing"));
3549 return NULL;
3550 }
3551 }
7f3f1ea2 3552
29b0f896
AM		 3553 /* Now *l must be either ',' or END_OF_INSN. */
3554 if (*l == ',')
3555 {
3556 if (*++l == END_OF_INSN)
3557 {
3558 /* Just skip it, if it's \n complain. */
3559 goto expecting_operand_after_comma;
3560 }
3561 expecting_operand = 1;
3562 }
3563 }
3564 return l;
3565}
7f3f1ea2 3566
050dfa73 3567static void
4d456e3d 3568swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3569{
3570 union i386_op temp_op;
40fb9820 3571 i386_operand_type temp_type;
050dfa73 3572 enum bfd_reloc_code_real temp_reloc;
4eed87de 3573
050dfa73
MM		 3574 temp_type = i.types[xchg2];
3575 i.types[xchg2] = i.types[xchg1];
3576 i.types[xchg1] = temp_type;
3577 temp_op = i.op[xchg2];
3578 i.op[xchg2] = i.op[xchg1];
3579 i.op[xchg1] = temp_op;
3580 temp_reloc = i.reloc[xchg2];
3581 i.reloc[xchg2] = i.reloc[xchg1];
3582 i.reloc[xchg1] = temp_reloc;
3583}
3584
29b0f896 3585static void
e3bb37b5 3586swap_operands (void)
29b0f896 3587{
b7c61d9a 3588 switch (i.operands)
050dfa73 3589 {
c0f3af97 3590 case 5:
b7c61d9a 3591 case 4:
4d456e3d 3592 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3593 case 3:
3594 case 2:
4d456e3d 3595 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3596 break;
3597 default:
3598 abort ();
29b0f896 3599 }
29b0f896
AM		 3600
3601 if (i.mem_operands == 2)
3602 {
3603 const seg_entry *temp_seg;
3604 temp_seg = i.seg[0];
3605 i.seg[0] = i.seg[1];
3606 i.seg[1] = temp_seg;
3607 }
3608}
252b5132 3609
29b0f896
AM		 3610/* Try to ensure constant immediates are represented in the smallest
3611 opcode possible. */
3612static void
e3bb37b5 3613optimize_imm (void)
29b0f896
AM		 3614{
3615 char guess_suffix = 0;
3616 int op;
252b5132 3617
29b0f896
AM		 3618 if (i.suffix)
3619 guess_suffix = i.suffix;
3620 else if (i.reg_operands)
3621 {
3622 /* Figure out a suffix from the last register operand specified.
3623 We can't do this properly yet, ie. excluding InOutPortReg,
3624 but the following works for instructions with immediates.
3625 In any case, we can't set i.suffix yet. */
3626 for (op = i.operands; --op >= 0;)
40fb9820 3627 if (i.types[op].bitfield.reg8)
7ab9ffdd 3628 {
40fb9820
L		 3629 guess_suffix = BYTE_MNEM_SUFFIX;
3630 break;
3631 }
3632 else if (i.types[op].bitfield.reg16)
252b5132 3633 {
40fb9820
L		 3634 guess_suffix = WORD_MNEM_SUFFIX;
3635 break;
3636 }
3637 else if (i.types[op].bitfield.reg32)
3638 {
3639 guess_suffix = LONG_MNEM_SUFFIX;
3640 break;
3641 }
3642 else if (i.types[op].bitfield.reg64)
3643 {
3644 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3645 break;
252b5132 3646 }
29b0f896
AM		 3647 }
3648 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3649 guess_suffix = WORD_MNEM_SUFFIX;
3650
3651 for (op = i.operands; --op >= 0;)
40fb9820 3652 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3653 {
3654 switch (i.op[op].imms->X_op)
252b5132 3655 {
29b0f896
AM		 3656 case O_constant:
3657 /* If a suffix is given, this operand may be shortened. */
3658 switch (guess_suffix)
252b5132 3659 {
29b0f896 3660 case LONG_MNEM_SUFFIX:
40fb9820
L		 3661 i.types[op].bitfield.imm32 = 1;
3662 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3663 break;
3664 case WORD_MNEM_SUFFIX:
40fb9820
L		 3665 i.types[op].bitfield.imm16 = 1;
3666 i.types[op].bitfield.imm32 = 1;
3667 i.types[op].bitfield.imm32s = 1;
3668 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3669 break;
3670 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3671 i.types[op].bitfield.imm8 = 1;
3672 i.types[op].bitfield.imm8s = 1;
3673 i.types[op].bitfield.imm16 = 1;
3674 i.types[op].bitfield.imm32 = 1;
3675 i.types[op].bitfield.imm32s = 1;
3676 i.types[op].bitfield.imm64 = 1;
29b0f896 3677 break;
252b5132 3678 }
252b5132 3679
29b0f896
AM		 3680 /* If this operand is at most 16 bits, convert it
3681 to a signed 16 bit number before trying to see
3682 whether it will fit in an even smaller size.
3683 This allows a 16-bit operand such as $0xffe0 to
3684 be recognised as within Imm8S range. */
40fb9820 3685 if ((i.types[op].bitfield.imm16)
29b0f896 3686 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3687 {
29b0f896
AM		 3688 i.op[op].imms->X_add_number =
3689 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3690 }
40fb9820 3691 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3692 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3693 == 0))
3694 {
3695 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3696 ^ ((offsetT) 1 << 31))
3697 - ((offsetT) 1 << 31));
3698 }
40fb9820 3699 i.types[op]
c6fb90c8
L		 3700 = operand_type_or (i.types[op],
3701 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3702
29b0f896
AM		 3703 /* We must avoid matching of Imm32 templates when 64bit
3704 only immediate is available. */
3705 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3706 i.types[op].bitfield.imm32 = 0;
29b0f896 3707 break;
252b5132 3708
29b0f896
AM		 3709 case O_absent:
3710 case O_register:
3711 abort ();
3712
3713 /* Symbols and expressions. */
3714 default:
9cd96992
JB		 3715 /* Convert symbolic operand to proper sizes for matching, but don't
3716 prevent matching a set of insns that only supports sizes other
3717 than those matching the insn suffix. */
3718 {
40fb9820 3719 i386_operand_type mask, allowed;
d3ce72d0 3720 const insn_template *t;
9cd96992 3721
0dfbf9d7
L		 3722 operand_type_set (&mask, 0);
3723 operand_type_set (&allowed, 0);
40fb9820 3724
4eed87de
AM		 3725 for (t = current_templates->start;
3726 t < current_templates->end;
3727 ++t)
c6fb90c8
L		 3728 allowed = operand_type_or (allowed,
3729 t->operand_types[op]);
9cd96992
JB		 3730 switch (guess_suffix)
3731 {
3732 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3733 mask.bitfield.imm64 = 1;
3734 mask.bitfield.imm32s = 1;
9cd96992
JB		 3735 break;
3736 case LONG_MNEM_SUFFIX:
40fb9820 3737 mask.bitfield.imm32 = 1;
9cd96992
JB		 3738 break;
3739 case WORD_MNEM_SUFFIX:
40fb9820 3740 mask.bitfield.imm16 = 1;
9cd96992
JB		 3741 break;
3742 case BYTE_MNEM_SUFFIX:
40fb9820 3743 mask.bitfield.imm8 = 1;
9cd96992
JB		 3744 break;
3745 default:
9cd96992
JB		 3746 break;
3747 }
c6fb90c8 3748 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3749 if (!operand_type_all_zero (&allowed))
c6fb90c8 3750 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3751 }
29b0f896 3752 break;
252b5132 3753 }
29b0f896
AM		 3754 }
3755}
47926f60 3756
29b0f896
AM		 3757/* Try to use the smallest displacement type too. */
3758static void
e3bb37b5 3759optimize_disp (void)
29b0f896
AM		 3760{
3761 int op;
3e73aa7c 3762
29b0f896 3763 for (op = i.operands; --op >= 0;)
40fb9820 3764 if (operand_type_check (i.types[op], disp))
252b5132 3765 {
b300c311 3766 if (i.op[op].disps->X_op == O_constant)
252b5132 3767 {
91d6fa6a 3768 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3769
40fb9820 3770 if (i.types[op].bitfield.disp16
91d6fa6a 3771 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3772 {
3773 /* If this operand is at most 16 bits, convert
3774 to a signed 16 bit number and don't use 64bit
3775 displacement. */
91d6fa6a 3776 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3777 i.types[op].bitfield.disp64 = 0;
b300c311 3778 }
40fb9820 3779 if (i.types[op].bitfield.disp32
91d6fa6a 3780 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3781 {
3782 /* If this operand is at most 32 bits, convert
3783 to a signed 32 bit number and don't use 64bit
3784 displacement. */
91d6fa6a
NC		 3785 op_disp &= (((offsetT) 2 << 31) - 1);
3786 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3787 i.types[op].bitfield.disp64 = 0;
b300c311 3788 }
91d6fa6a 3789 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3790 {
40fb9820
L		 3791 i.types[op].bitfield.disp8 = 0;
3792 i.types[op].bitfield.disp16 = 0;
3793 i.types[op].bitfield.disp32 = 0;
3794 i.types[op].bitfield.disp32s = 0;
3795 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3796 i.op[op].disps = 0;
3797 i.disp_operands--;
3798 }
3799 else if (flag_code == CODE_64BIT)
3800 {
91d6fa6a 3801 if (fits_in_signed_long (op_disp))
28a9d8f5 3802 {
40fb9820
L		 3803 i.types[op].bitfield.disp64 = 0;
3804 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3805 }
0e1147d9 3806 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3807 && fits_in_unsigned_long (op_disp))
40fb9820 3808 i.types[op].bitfield.disp32 = 1;
b300c311 3809 }
40fb9820
L		 3810 if ((i.types[op].bitfield.disp32
3811 || i.types[op].bitfield.disp32s
3812 || i.types[op].bitfield.disp16)
91d6fa6a 3813 && fits_in_signed_byte (op_disp))
40fb9820 3814 i.types[op].bitfield.disp8 = 1;
252b5132 3815 }
67a4f2b7
AO		 3816 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3817 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3818 {
3819 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3820 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3821 i.types[op].bitfield.disp8 = 0;
3822 i.types[op].bitfield.disp16 = 0;
3823 i.types[op].bitfield.disp32 = 0;
3824 i.types[op].bitfield.disp32s = 0;
3825 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3826 }
3827 else
b300c311 3828 /* We only support 64bit displacement on constants. */
40fb9820 3829 i.types[op].bitfield.disp64 = 0;
252b5132 3830 }
29b0f896
AM		 3831}
3832
43f3e2ee 3833/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3834 operand types. */
3835
3836static int
3837VEX_check_operands (const insn_template *t)
3838{
3839 if (!t->opcode_modifier.vex)
3840 return 0;
3841
3842 /* Only check VEX_Imm4, which must be the first operand. */
3843 if (t->operand_types[0].bitfield.vec_imm4)
3844 {
3845 if (i.op[0].imms->X_op != O_constant
3846 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3847 {
a65babc9 3848 i.error = bad_imm4;
891edac4
L		 3849 return 1;
3850 }
a683cc34
SP		 3851
3852 /* Turn off Imm8 so that update_imm won't complain. */
3853 i.types[0] = vec_imm4;
3854 }
3855
3856 return 0;
3857}
3858
d3ce72d0 3859static const insn_template *
e3bb37b5 3860match_template (void)
29b0f896
AM		 3861{
3862 /* Points to template once we've found it. */
d3ce72d0 3863 const insn_template *t;
40fb9820 3864 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3865 i386_operand_type overlap4;
29b0f896 3866 unsigned int found_reverse_match;
40fb9820
L		 3867 i386_opcode_modifier suffix_check;
3868 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3869 int addr_prefix_disp;
a5c311ca 3870 unsigned int j;
3629bb00 3871 unsigned int found_cpu_match;
45664ddb 3872 unsigned int check_register;
29b0f896 3873
c0f3af97
L		 3874#if MAX_OPERANDS != 5
3875# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3876#endif
3877
29b0f896 3878 found_reverse_match = 0;
539e75ad 3879 addr_prefix_disp = -1;
40fb9820
L		 3880
3881 memset (&suffix_check, 0, sizeof (suffix_check));
3882 if (i.suffix == BYTE_MNEM_SUFFIX)
3883 suffix_check.no_bsuf = 1;
3884 else if (i.suffix == WORD_MNEM_SUFFIX)
3885 suffix_check.no_wsuf = 1;
3886 else if (i.suffix == SHORT_MNEM_SUFFIX)
3887 suffix_check.no_ssuf = 1;
3888 else if (i.suffix == LONG_MNEM_SUFFIX)
3889 suffix_check.no_lsuf = 1;
3890 else if (i.suffix == QWORD_MNEM_SUFFIX)
3891 suffix_check.no_qsuf = 1;
3892 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3893 suffix_check.no_ldsuf = 1;
29b0f896 3894
01559ecc
L		 3895 /* Must have right number of operands. */
3896 i.error = number_of_operands_mismatch;
3897
45aa61fe 3898 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3899 {
539e75ad
L		 3900 addr_prefix_disp = -1;
3901
29b0f896
AM		 3902 if (i.operands != t->operands)
3903 continue;
3904
50aecf8c 3905 /* Check processor support. */
a65babc9 3906 i.error = unsupported;
c0f3af97
L		 3907 found_cpu_match = (cpu_flags_match (t)
3908 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3909 if (!found_cpu_match)
3910 continue;
3911
e1d4d893 3912 /* Check old gcc support. */
a65babc9 3913 i.error = old_gcc_only;
e1d4d893
L		 3914 if (!old_gcc && t->opcode_modifier.oldgcc)
3915 continue;
3916
3917 /* Check AT&T mnemonic. */
a65babc9 3918 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3919 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3920 continue;
3921
891edac4 3922 /* Check AT&T/Intel syntax. */
a65babc9 3923 i.error = unsupported_syntax;
5c07affc
L		 3924 if ((intel_syntax && t->opcode_modifier.attsyntax)
3925 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3926 continue;
3927
20592a94 3928 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3929 i.error = invalid_instruction_suffix;
567e4e96
L		 3930 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3931 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3932 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3933 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3934 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3935 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3936 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3937 continue;
3938
5c07affc 3939 if (!operand_size_match (t))
7d5e4556 3940 continue;
539e75ad 3941
5c07affc
L		 3942 for (j = 0; j < MAX_OPERANDS; j++)
3943 operand_types[j] = t->operand_types[j];
3944
45aa61fe
AM		 3945 /* In general, don't allow 64-bit operands in 32-bit mode. */
3946 if (i.suffix == QWORD_MNEM_SUFFIX
3947 && flag_code != CODE_64BIT
3948 && (intel_syntax
40fb9820 3949 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3950 && !intel_float_operand (t->name))
3951 : intel_float_operand (t->name) != 2)
40fb9820 3952 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3953 && !operand_types[0].bitfield.regxmm
3954 && !operand_types[0].bitfield.regymm)
40fb9820 3955 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3956 && !!operand_types[t->operands > 1].bitfield.regxmm
3957 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3958 && (t->base_opcode != 0x0fc7
3959 || t->extension_opcode != 1 /* cmpxchg8b */))
3960 continue;
3961
192dc9c6
JB		 3962 /* In general, don't allow 32-bit operands on pre-386. */
3963 else if (i.suffix == LONG_MNEM_SUFFIX
3964 && !cpu_arch_flags.bitfield.cpui386
3965 && (intel_syntax
3966 ? (!t->opcode_modifier.ignoresize
3967 && !intel_float_operand (t->name))
3968 : intel_float_operand (t->name) != 2)
3969 && ((!operand_types[0].bitfield.regmmx
3970 && !operand_types[0].bitfield.regxmm)
3971 || (!operand_types[t->operands > 1].bitfield.regmmx
3972 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3973 continue;
3974
29b0f896 3975 /* Do not verify operands when there are none. */
50aecf8c 3976 else
29b0f896 3977 {
c6fb90c8 3978 if (!t->operands)
2dbab7d5
L		 3979 /* We've found a match; break out of loop. */
3980 break;
29b0f896 3981 }
252b5132 3982
539e75ad
L		 3983 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3984 into Disp32/Disp16/Disp32 operand. */
3985 if (i.prefix[ADDR_PREFIX] != 0)
3986 {
40fb9820 3987 /* There should be only one Disp operand. */
539e75ad
L		 3988 switch (flag_code)
3989 {
3990 case CODE_16BIT:
40fb9820
L		 3991 for (j = 0; j < MAX_OPERANDS; j++)
3992 {
3993 if (operand_types[j].bitfield.disp16)
3994 {
3995 addr_prefix_disp = j;
3996 operand_types[j].bitfield.disp32 = 1;
3997 operand_types[j].bitfield.disp16 = 0;
3998 break;
3999 }
4000 }
539e75ad
L		 4001 break;
4002 case CODE_32BIT:
40fb9820
L		 4003 for (j = 0; j < MAX_OPERANDS; j++)
4004 {
4005 if (operand_types[j].bitfield.disp32)
4006 {
4007 addr_prefix_disp = j;
4008 operand_types[j].bitfield.disp32 = 0;
4009 operand_types[j].bitfield.disp16 = 1;
4010 break;
4011 }
4012 }
539e75ad
L		 4013 break;
4014 case CODE_64BIT:
40fb9820
L		 4015 for (j = 0; j < MAX_OPERANDS; j++)
4016 {
4017 if (operand_types[j].bitfield.disp64)
4018 {
4019 addr_prefix_disp = j;
4020 operand_types[j].bitfield.disp64 = 0;
4021 operand_types[j].bitfield.disp32 = 1;
4022 break;
4023 }
4024 }
539e75ad
L		 4025 break;
4026 }
539e75ad
L		 4027 }
4028
56ffb741
L		 4029 /* We check register size if needed. */
4030 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4031 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4032 switch (t->operands)
4033 {
4034 case 1:
40fb9820 4035 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4036 continue;
4037 break;
4038 case 2:
8b38ad71
L		 4039 /* xchg %eax, %eax is a special case. It is an aliase for nop
4040 only in 32bit mode and we can use opcode 0x90. In 64bit
4041 mode, we can't use 0x90 for xchg %eax, %eax since it should
4042 zero-extend %eax to %rax. */
4043 if (flag_code == CODE_64BIT
4044 && t->base_opcode == 0x90
0dfbf9d7
L		 4045 && operand_type_equal (&i.types [0], &acc32)
4046 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4047 continue;
b6169b20
L		 4048 if (i.swap_operand)
4049 {
4050 /* If we swap operand in encoding, we either match
4051 the next one or reverse direction of operands. */
4052 if (t->opcode_modifier.s)
4053 continue;
4054 else if (t->opcode_modifier.d)
4055 goto check_reverse;
4056 }
4057
29b0f896 4058 case 3:
fa99fab2
L		 4059 /* If we swap operand in encoding, we match the next one. */
4060 if (i.swap_operand && t->opcode_modifier.s)
4061 continue;
f48ff2ae 4062 case 4:
c0f3af97 4063 case 5:
c6fb90c8 4064 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4065 if (!operand_type_match (overlap0, i.types[0])
4066 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4067 || (check_register
4068 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4069 operand_types[0],
4070 overlap1, i.types[1],
4071 operand_types[1])))
29b0f896
AM		 4072 {
4073 /* Check if other direction is valid ... */
40fb9820 4074 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4075 continue;
4076
b6169b20 4077check_reverse:
29b0f896 4078 /* Try reversing direction of operands. */
c6fb90c8
L		 4079 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4080 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4081 if (!operand_type_match (overlap0, i.types[0])
4082 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4083 || (check_register
4084 && !operand_type_register_match (overlap0,
4085 i.types[0],
4086 operand_types[1],
4087 overlap1,
4088 i.types[1],
4089 operand_types[0])))
29b0f896
AM		 4090 {
4091 /* Does not match either direction. */
4092 continue;
4093 }
4094 /* found_reverse_match holds which of D or FloatDR
4095 we've found. */
40fb9820 4096 if (t->opcode_modifier.d)
8a2ed489 4097 found_reverse_match = Opcode_D;
40fb9820 4098 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4099 found_reverse_match = Opcode_FloatD;
4100 else
4101 found_reverse_match = 0;
40fb9820 4102 if (t->opcode_modifier.floatr)
8a2ed489 4103 found_reverse_match |= Opcode_FloatR;
29b0f896 4104 }
f48ff2ae 4105 else
29b0f896 4106 {
f48ff2ae 4107 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4108 switch (t->operands)
4109 {
c0f3af97
L		 4110 case 5:
4111 overlap4 = operand_type_and (i.types[4],
4112 operand_types[4]);
d1cbb4db 4113 case 4:
c6fb90c8
L		 4114 overlap3 = operand_type_and (i.types[3],
4115 operand_types[3]);
d1cbb4db 4116 case 3:
c6fb90c8
L		 4117 overlap2 = operand_type_and (i.types[2],
4118 operand_types[2]);
d1cbb4db
L		 4119 break;
4120 }
29b0f896 4121
f48ff2ae
L		 4122 switch (t->operands)
4123 {
c0f3af97
L		 4124 case 5:
4125 if (!operand_type_match (overlap4, i.types[4])
4126 || !operand_type_register_match (overlap3,
4127 i.types[3],
4128 operand_types[3],
4129 overlap4,
4130 i.types[4],
4131 operand_types[4]))
4132 continue;
f48ff2ae 4133 case 4:
40fb9820 4134 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4135 || (check_register
4136 && !operand_type_register_match (overlap2,
4137 i.types[2],
4138 operand_types[2],
4139 overlap3,
4140 i.types[3],
4141 operand_types[3])))
f48ff2ae
L		 4142 continue;
4143 case 3:
4144 /* Here we make use of the fact that there are no
4145 reverse match 3 operand instructions, and all 3
4146 operand instructions only need to be checked for
4147 register consistency between operands 2 and 3. */
40fb9820 4148 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4149 || (check_register
4150 && !operand_type_register_match (overlap1,
4151 i.types[1],
4152 operand_types[1],
4153 overlap2,
4154 i.types[2],
4155 operand_types[2])))
f48ff2ae
L		 4156 continue;
4157 break;
4158 }
29b0f896 4159 }
f48ff2ae 4160 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4161 slip through to break. */
4162 }
3629bb00 4163 if (!found_cpu_match)
29b0f896
AM		 4164 {
4165 found_reverse_match = 0;
4166 continue;
4167 }
c0f3af97 4168
a683cc34
SP		 4169 /* Check if VEX operands are valid. */
4170 if (VEX_check_operands (t))
4171 continue;
4172
29b0f896
AM		 4173 /* We've found a match; break out of loop. */
4174 break;
4175 }
4176
4177 if (t == current_templates->end)
4178 {
4179 /* We found no match. */
a65babc9
L		 4180 const char *err_msg;
4181 switch (i.error)
4182 {
4183 default:
4184 abort ();
86e026a4 4185 case operand_size_mismatch:
a65babc9
L		 4186 err_msg = _("operand size mismatch");
4187 break;
4188 case operand_type_mismatch:
4189 err_msg = _("operand type mismatch");
4190 break;
4191 case register_type_mismatch:
4192 err_msg = _("register type mismatch");
4193 break;
4194 case number_of_operands_mismatch:
4195 err_msg = _("number of operands mismatch");
4196 break;
4197 case invalid_instruction_suffix:
4198 err_msg = _("invalid instruction suffix");
4199 break;
4200 case bad_imm4:
4201 err_msg = _("Imm4 isn't the first operand");
4202 break;
4203 case old_gcc_only:
4204 err_msg = _("only supported with old gcc");
4205 break;
4206 case unsupported_with_intel_mnemonic:
4207 err_msg = _("unsupported with Intel mnemonic");
4208 break;
4209 case unsupported_syntax:
4210 err_msg = _("unsupported syntax");
4211 break;
4212 case unsupported:
4213 err_msg = _("unsupported");
4214 break;
4215 }
4216 as_bad (_("%s for `%s'"), err_msg,
891edac4 4217 current_templates->start->name);
fa99fab2 4218 return NULL;
29b0f896 4219 }
252b5132 4220
29b0f896
AM		 4221 if (!quiet_warnings)
4222 {
4223 if (!intel_syntax
40fb9820
L		 4224 && (i.types[0].bitfield.jumpabsolute
4225 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4226 {
4227 as_warn (_("indirect %s without `*'"), t->name);
4228 }
4229
40fb9820
L		 4230 if (t->opcode_modifier.isprefix
4231 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4232 {
4233 /* Warn them that a data or address size prefix doesn't
4234 affect assembly of the next line of code. */
4235 as_warn (_("stand-alone `%s' prefix"), t->name);
4236 }
4237 }
4238
4239 /* Copy the template we found. */
4240 i.tm = *t;
539e75ad
L		 4241
4242 if (addr_prefix_disp != -1)
4243 i.tm.operand_types[addr_prefix_disp]
4244 = operand_types[addr_prefix_disp];
4245
29b0f896
AM		 4246 if (found_reverse_match)
4247 {
4248 /* If we found a reverse match we must alter the opcode
4249 direction bit. found_reverse_match holds bits to change
4250 (different for int & float insns). */
4251
4252 i.tm.base_opcode ^= found_reverse_match;
4253
539e75ad
L		 4254 i.tm.operand_types[0] = operand_types[1];
4255 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4256 }
4257
fa99fab2 4258 return t;
29b0f896
AM		 4259}
4260
4261static int
e3bb37b5 4262check_string (void)
29b0f896 4263{
40fb9820
L		 4264 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4265 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4266 {
4267 if (i.seg[0] != NULL && i.seg[0] != &es)
4268 {
a87af027 4269 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4270 i.tm.name,
a87af027
JB		 4271 mem_op + 1,
4272 register_prefix);
29b0f896
AM		 4273 return 0;
4274 }
4275 /* There's only ever one segment override allowed per instruction.
4276 This instruction possibly has a legal segment override on the
4277 second operand, so copy the segment to where non-string
4278 instructions store it, allowing common code. */
4279 i.seg[0] = i.seg[1];
4280 }
40fb9820 4281 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4282 {
4283 if (i.seg[1] != NULL && i.seg[1] != &es)
4284 {
a87af027 4285 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4286 i.tm.name,
a87af027
JB		 4287 mem_op + 2,
4288 register_prefix);
29b0f896
AM		 4289 return 0;
4290 }
4291 }
4292 return 1;
4293}
4294
4295static int
543613e9 4296process_suffix (void)
29b0f896
AM		 4297{
4298 /* If matched instruction specifies an explicit instruction mnemonic
4299 suffix, use it. */
40fb9820
L		 4300 if (i.tm.opcode_modifier.size16)
4301 i.suffix = WORD_MNEM_SUFFIX;
4302 else if (i.tm.opcode_modifier.size32)
4303 i.suffix = LONG_MNEM_SUFFIX;
4304 else if (i.tm.opcode_modifier.size64)
4305 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4306 else if (i.reg_operands)
4307 {
4308 /* If there's no instruction mnemonic suffix we try to invent one
4309 based on register operands. */
4310 if (!i.suffix)
4311 {
4312 /* We take i.suffix from the last register operand specified,
4313 Destination register type is more significant than source
381d071f
L		 4314 register type. crc32 in SSE4.2 prefers source register
4315 type. */
4316 if (i.tm.base_opcode == 0xf20f38f1)
4317 {
40fb9820
L		 4318 if (i.types[0].bitfield.reg16)
4319 i.suffix = WORD_MNEM_SUFFIX;
4320 else if (i.types[0].bitfield.reg32)
4321 i.suffix = LONG_MNEM_SUFFIX;
4322 else if (i.types[0].bitfield.reg64)
4323 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4324 }
9344ff29 4325 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4326 {
40fb9820 4327 if (i.types[0].bitfield.reg8)
20592a94
L		 4328 i.suffix = BYTE_MNEM_SUFFIX;
4329 }
381d071f
L		 4330
4331 if (!i.suffix)
4332 {
4333 int op;
4334
20592a94
L		 4335 if (i.tm.base_opcode == 0xf20f38f1
4336 || i.tm.base_opcode == 0xf20f38f0)
4337 {
4338 /* We have to know the operand size for crc32. */
4339 as_bad (_("ambiguous memory operand size for `%s`"),
4340 i.tm.name);
4341 return 0;
4342 }
4343
381d071f 4344 for (op = i.operands; --op >= 0;)
40fb9820 4345 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4346 {
40fb9820
L		 4347 if (i.types[op].bitfield.reg8)
4348 {
4349 i.suffix = BYTE_MNEM_SUFFIX;
4350 break;
4351 }
4352 else if (i.types[op].bitfield.reg16)
4353 {
4354 i.suffix = WORD_MNEM_SUFFIX;
4355 break;
4356 }
4357 else if (i.types[op].bitfield.reg32)
4358 {
4359 i.suffix = LONG_MNEM_SUFFIX;
4360 break;
4361 }
4362 else if (i.types[op].bitfield.reg64)
4363 {
4364 i.suffix = QWORD_MNEM_SUFFIX;
4365 break;
4366 }
381d071f
L		 4367 }
4368 }
29b0f896
AM		 4369 }
4370 else if (i.suffix == BYTE_MNEM_SUFFIX)
4371 {
2eb952a4
L		 4372 if (intel_syntax
4373 && i.tm.opcode_modifier.ignoresize
4374 && i.tm.opcode_modifier.no_bsuf)
4375 i.suffix = 0;
4376 else if (!check_byte_reg ())
29b0f896
AM		 4377 return 0;
4378 }
4379 else if (i.suffix == LONG_MNEM_SUFFIX)
4380 {
2eb952a4
L		 4381 if (intel_syntax
4382 && i.tm.opcode_modifier.ignoresize
4383 && i.tm.opcode_modifier.no_lsuf)
4384 i.suffix = 0;
4385 else if (!check_long_reg ())
29b0f896
AM		 4386 return 0;
4387 }
4388 else if (i.suffix == QWORD_MNEM_SUFFIX)
4389 {
955e1e6a
L		 4390 if (intel_syntax
4391 && i.tm.opcode_modifier.ignoresize
4392 && i.tm.opcode_modifier.no_qsuf)
4393 i.suffix = 0;
4394 else if (!check_qword_reg ())
29b0f896
AM		 4395 return 0;
4396 }
4397 else if (i.suffix == WORD_MNEM_SUFFIX)
4398 {
2eb952a4
L		 4399 if (intel_syntax
4400 && i.tm.opcode_modifier.ignoresize
4401 && i.tm.opcode_modifier.no_wsuf)
4402 i.suffix = 0;
4403 else if (!check_word_reg ())
29b0f896
AM		 4404 return 0;
4405 }
c0f3af97
L		 4406 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4407 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4408 {
c0f3af97 4409 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4410 should check if it is a valid suffix. */
4411 }
40fb9820 4412 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4413 /* Do nothing if the instruction is going to ignore the prefix. */
4414 ;
4415 else
4416 abort ();
4417 }
40fb9820 4418 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4419 && !i.suffix
4420 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4421 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4422 {
4423 i.suffix = stackop_size;
4424 }
9306ca4a
JB		 4425 else if (intel_syntax
4426 && !i.suffix
40fb9820
L		 4427 && (i.tm.operand_types[0].bitfield.jumpabsolute
4428 || i.tm.opcode_modifier.jumpbyte
4429 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4430 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4431 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4432 {
4433 switch (flag_code)
4434 {
4435 case CODE_64BIT:
40fb9820 4436 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4437 {
4438 i.suffix = QWORD_MNEM_SUFFIX;
4439 break;
4440 }
4441 case CODE_32BIT:
40fb9820 4442 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4443 i.suffix = LONG_MNEM_SUFFIX;
4444 break;
4445 case CODE_16BIT:
40fb9820 4446 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4447 i.suffix = WORD_MNEM_SUFFIX;
4448 break;
4449 }
4450 }
252b5132 4451
9306ca4a 4452 if (!i.suffix)
29b0f896 4453 {
9306ca4a
JB		 4454 if (!intel_syntax)
4455 {
40fb9820 4456 if (i.tm.opcode_modifier.w)
9306ca4a 4457 {
4eed87de
AM		 4458 as_bad (_("no instruction mnemonic suffix given and "
4459 "no register operands; can't size instruction"));
9306ca4a
JB		 4460 return 0;
4461 }
4462 }
4463 else
4464 {
40fb9820 4465 unsigned int suffixes;
7ab9ffdd 4466
40fb9820
L		 4467 suffixes = !i.tm.opcode_modifier.no_bsuf;
4468 if (!i.tm.opcode_modifier.no_wsuf)
4469 suffixes |= 1 << 1;
4470 if (!i.tm.opcode_modifier.no_lsuf)
4471 suffixes |= 1 << 2;
fc4adea1 4472 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4473 suffixes |= 1 << 3;
4474 if (!i.tm.opcode_modifier.no_ssuf)
4475 suffixes |= 1 << 4;
4476 if (!i.tm.opcode_modifier.no_qsuf)
4477 suffixes |= 1 << 5;
4478
4479 /* There are more than suffix matches. */
4480 if (i.tm.opcode_modifier.w
9306ca4a 4481 || ((suffixes & (suffixes - 1))
40fb9820
L		 4482 && !i.tm.opcode_modifier.defaultsize
4483 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4484 {
4485 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4486 return 0;
4487 }
4488 }
29b0f896 4489 }
252b5132 4490
9306ca4a
JB		 4491 /* Change the opcode based on the operand size given by i.suffix;
4492 We don't need to change things for byte insns. */
4493
582d5edd
L		 4494 if (i.suffix
4495 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4496 && i.suffix != XMMWORD_MNEM_SUFFIX
4497 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4498 {
4499 /* It's not a byte, select word/dword operation. */
40fb9820 4500 if (i.tm.opcode_modifier.w)
29b0f896 4501 {
40fb9820 4502 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4503 i.tm.base_opcode |= 8;
4504 else
4505 i.tm.base_opcode |= 1;
4506 }
0f3f3d8b 4507
29b0f896
AM		 4508 /* Now select between word & dword operations via the operand
4509 size prefix, except for instructions that will ignore this
4510 prefix anyway. */
ca61edf2 4511 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4512 {
ca61edf2
L		 4513 /* The address size override prefix changes the size of the
4514 first operand. */
40fb9820
L		 4515 if ((flag_code == CODE_32BIT
4516 && i.op->regs[0].reg_type.bitfield.reg16)
4517 || (flag_code != CODE_32BIT
4518 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4519 if (!add_prefix (ADDR_PREFIX_OPCODE))
4520 return 0;
4521 }
4522 else if (i.suffix != QWORD_MNEM_SUFFIX
4523 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4524 && !i.tm.opcode_modifier.ignoresize
4525 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4526 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4527 || (flag_code == CODE_64BIT
40fb9820 4528 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4529 {
4530 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4531
40fb9820 4532 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4533 prefix = ADDR_PREFIX_OPCODE;
252b5132 4534
29b0f896
AM		 4535 if (!add_prefix (prefix))
4536 return 0;
24eab124 4537 }
252b5132 4538
29b0f896
AM		 4539 /* Set mode64 for an operand. */
4540 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4541 && flag_code == CODE_64BIT
40fb9820 4542 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4543 {
4544 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4545 need rex64. cmpxchg8b is also a special case. */
4546 if (! (i.operands == 2
4547 && i.tm.base_opcode == 0x90
4548 && i.tm.extension_opcode == None
0dfbf9d7
L		 4549 && operand_type_equal (&i.types [0], &acc64)
4550 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4551 && ! (i.operands == 1
4552 && i.tm.base_opcode == 0xfc7
4553 && i.tm.extension_opcode == 1
40fb9820
L		 4554 && !operand_type_check (i.types [0], reg)
4555 && operand_type_check (i.types [0], anymem)))
f6bee062 4556 i.rex |= REX_W;
46e883c5 4557 }
3e73aa7c 4558
29b0f896
AM		 4559 /* Size floating point instruction. */
4560 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4561 if (i.tm.opcode_modifier.floatmf)
543613e9 4562 i.tm.base_opcode ^= 4;
29b0f896 4563 }
7ecd2f8b 4564
29b0f896
AM		 4565 return 1;
4566}
3e73aa7c 4567
29b0f896 4568static int
543613e9 4569check_byte_reg (void)
29b0f896
AM		 4570{
4571 int op;
543613e9 4572
29b0f896
AM		 4573 for (op = i.operands; --op >= 0;)
4574 {
4575 /* If this is an eight bit register, it's OK. If it's the 16 or
4576 32 bit version of an eight bit register, we will just use the
4577 low portion, and that's OK too. */
40fb9820 4578 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4579 continue;
4580
9344ff29
L		 4581 /* crc32 doesn't generate this warning. */
4582 if (i.tm.base_opcode == 0xf20f38f0)
4583 continue;
4584
40fb9820
L		 4585 if ((i.types[op].bitfield.reg16
4586 || i.types[op].bitfield.reg32
4587 || i.types[op].bitfield.reg64)
4588 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4589 {
4590 /* Prohibit these changes in the 64bit mode, since the
4591 lowering is more complicated. */
4592 if (flag_code == CODE_64BIT
40fb9820 4593 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4594 {
2ca3ace5
L		 4595 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4596 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4597 i.suffix);
4598 return 0;
4599 }
4600#if REGISTER_WARNINGS
4601 if (!quiet_warnings
40fb9820 4602 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4603 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4604 register_prefix,
40fb9820 4605 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4606 ? REGNAM_AL - REGNAM_AX
4607 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4608 register_prefix,
29b0f896
AM		 4609 i.op[op].regs->reg_name,
4610 i.suffix);
4611#endif
4612 continue;
4613 }
4614 /* Any other register is bad. */
40fb9820
L		 4615 if (i.types[op].bitfield.reg16
4616 || i.types[op].bitfield.reg32
4617 || i.types[op].bitfield.reg64
4618 || i.types[op].bitfield.regmmx
4619 || i.types[op].bitfield.regxmm
c0f3af97 4620 || i.types[op].bitfield.regymm
40fb9820
L		 4621 || i.types[op].bitfield.sreg2
4622 || i.types[op].bitfield.sreg3
4623 || i.types[op].bitfield.control
4624 || i.types[op].bitfield.debug
4625 || i.types[op].bitfield.test
4626 || i.types[op].bitfield.floatreg
4627 || i.types[op].bitfield.floatacc)
29b0f896 4628 {
a540244d
L		 4629 as_bad (_("`%s%s' not allowed with `%s%c'"),
4630 register_prefix,
29b0f896
AM		 4631 i.op[op].regs->reg_name,
4632 i.tm.name,
4633 i.suffix);
4634 return 0;
4635 }
4636 }
4637 return 1;
4638}
4639
4640static int
e3bb37b5 4641check_long_reg (void)
29b0f896
AM		 4642{
4643 int op;
4644
4645 for (op = i.operands; --op >= 0;)
4646 /* Reject eight bit registers, except where the template requires
4647 them. (eg. movzb) */
40fb9820
L		 4648 if (i.types[op].bitfield.reg8
4649 && (i.tm.operand_types[op].bitfield.reg16
4650 || i.tm.operand_types[op].bitfield.reg32
4651 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4652 {
a540244d
L		 4653 as_bad (_("`%s%s' not allowed with `%s%c'"),
4654 register_prefix,
29b0f896
AM		 4655 i.op[op].regs->reg_name,
4656 i.tm.name,
4657 i.suffix);
4658 return 0;
4659 }
4660 /* Warn if the e prefix on a general reg is missing. */
4661 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4662 && i.types[op].bitfield.reg16
4663 && (i.tm.operand_types[op].bitfield.reg32
4664 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4665 {
4666 /* Prohibit these changes in the 64bit mode, since the
4667 lowering is more complicated. */
4668 if (flag_code == CODE_64BIT)
252b5132 4669 {
2ca3ace5
L		 4670 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4671 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4672 i.suffix);
4673 return 0;
252b5132 4674 }
29b0f896
AM		 4675#if REGISTER_WARNINGS
4676 else
a540244d
L		 4677 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4678 register_prefix,
29b0f896 4679 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4680 register_prefix,
29b0f896
AM		 4681 i.op[op].regs->reg_name,
4682 i.suffix);
4683#endif
252b5132 4684 }
29b0f896 4685 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4686 else if (i.types[op].bitfield.reg64
4687 && (i.tm.operand_types[op].bitfield.reg32
4688 || i.tm.operand_types[op].bitfield.acc))
252b5132 4689 {
34828aad 4690 if (intel_syntax
ca61edf2 4691 && i.tm.opcode_modifier.toqword
40fb9820 4692 && !i.types[0].bitfield.regxmm)
34828aad 4693 {
ca61edf2 4694 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4695 i.suffix = QWORD_MNEM_SUFFIX;
4696 }
4697 else
4698 {
4699 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4700 register_prefix, i.op[op].regs->reg_name,
4701 i.suffix);
4702 return 0;
4703 }
29b0f896
AM		 4704 }
4705 return 1;
4706}
252b5132 4707
29b0f896 4708static int
e3bb37b5 4709check_qword_reg (void)
29b0f896
AM		 4710{
4711 int op;
252b5132 4712
29b0f896
AM		 4713 for (op = i.operands; --op >= 0; )
4714 /* Reject eight bit registers, except where the template requires
4715 them. (eg. movzb) */
40fb9820
L		 4716 if (i.types[op].bitfield.reg8
4717 && (i.tm.operand_types[op].bitfield.reg16
4718 || i.tm.operand_types[op].bitfield.reg32
4719 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4720 {
a540244d
L		 4721 as_bad (_("`%s%s' not allowed with `%s%c'"),
4722 register_prefix,
29b0f896
AM		 4723 i.op[op].regs->reg_name,
4724 i.tm.name,
4725 i.suffix);
4726 return 0;
4727 }
4728 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4729 else if ((i.types[op].bitfield.reg16
4730 || i.types[op].bitfield.reg32)
4731 && (i.tm.operand_types[op].bitfield.reg32
4732 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4733 {
4734 /* Prohibit these changes in the 64bit mode, since the
4735 lowering is more complicated. */
34828aad 4736 if (intel_syntax
ca61edf2 4737 && i.tm.opcode_modifier.todword
40fb9820 4738 && !i.types[0].bitfield.regxmm)
34828aad 4739 {
ca61edf2 4740 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4741 i.suffix = LONG_MNEM_SUFFIX;
4742 }
4743 else
4744 {
4745 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4746 register_prefix, i.op[op].regs->reg_name,
4747 i.suffix);
4748 return 0;
4749 }
252b5132 4750 }
29b0f896
AM		 4751 return 1;
4752}
252b5132 4753
29b0f896 4754static int
e3bb37b5 4755check_word_reg (void)
29b0f896
AM		 4756{
4757 int op;
4758 for (op = i.operands; --op >= 0;)
4759 /* Reject eight bit registers, except where the template requires
4760 them. (eg. movzb) */
40fb9820
L		 4761 if (i.types[op].bitfield.reg8
4762 && (i.tm.operand_types[op].bitfield.reg16
4763 || i.tm.operand_types[op].bitfield.reg32
4764 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4765 {
a540244d
L		 4766 as_bad (_("`%s%s' not allowed with `%s%c'"),
4767 register_prefix,
29b0f896
AM		 4768 i.op[op].regs->reg_name,
4769 i.tm.name,
4770 i.suffix);
4771 return 0;
4772 }
4773 /* Warn if the e prefix on a general reg is present. */
4774 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4775 && i.types[op].bitfield.reg32
4776 && (i.tm.operand_types[op].bitfield.reg16
4777 || i.tm.operand_types[op].bitfield.acc))
252b5132 4778 {
29b0f896
AM		 4779 /* Prohibit these changes in the 64bit mode, since the
4780 lowering is more complicated. */
4781 if (flag_code == CODE_64BIT)
252b5132 4782 {
2ca3ace5
L		 4783 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4784 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4785 i.suffix);
4786 return 0;
252b5132 4787 }
29b0f896
AM		 4788 else
4789#if REGISTER_WARNINGS
a540244d
L		 4790 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4791 register_prefix,
29b0f896 4792 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4793 register_prefix,
29b0f896
AM		 4794 i.op[op].regs->reg_name,
4795 i.suffix);
4796#endif
4797 }
4798 return 1;
4799}
252b5132 4800
29b0f896 4801static int
40fb9820 4802update_imm (unsigned int j)
29b0f896 4803{
bc0844ae 4804 i386_operand_type overlap = i.types[j];
40fb9820
L		 4805 if ((overlap.bitfield.imm8
4806 || overlap.bitfield.imm8s
4807 || overlap.bitfield.imm16
4808 || overlap.bitfield.imm32
4809 || overlap.bitfield.imm32s
4810 || overlap.bitfield.imm64)
0dfbf9d7
L		 4811 && !operand_type_equal (&overlap, &imm8)
4812 && !operand_type_equal (&overlap, &imm8s)
4813 && !operand_type_equal (&overlap, &imm16)
4814 && !operand_type_equal (&overlap, &imm32)
4815 && !operand_type_equal (&overlap, &imm32s)
4816 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4817 {
4818 if (i.suffix)
4819 {
40fb9820
L		 4820 i386_operand_type temp;
4821
0dfbf9d7 4822 operand_type_set (&temp, 0);
7ab9ffdd 4823 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4824 {
4825 temp.bitfield.imm8 = overlap.bitfield.imm8;
4826 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4827 }
4828 else if (i.suffix == WORD_MNEM_SUFFIX)
4829 temp.bitfield.imm16 = overlap.bitfield.imm16;
4830 else if (i.suffix == QWORD_MNEM_SUFFIX)
4831 {
4832 temp.bitfield.imm64 = overlap.bitfield.imm64;
4833 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4834 }
4835 else
4836 temp.bitfield.imm32 = overlap.bitfield.imm32;
4837 overlap = temp;
29b0f896 4838 }
0dfbf9d7
L		 4839 else if (operand_type_equal (&overlap, &imm16_32_32s)
4840 || operand_type_equal (&overlap, &imm16_32)
4841 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4842 {
40fb9820 4843 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4844 overlap = imm16;
40fb9820 4845 else
65da13b5 4846 overlap = imm32s;
29b0f896 4847 }
0dfbf9d7
L		 4848 if (!operand_type_equal (&overlap, &imm8)
4849 && !operand_type_equal (&overlap, &imm8s)
4850 && !operand_type_equal (&overlap, &imm16)
4851 && !operand_type_equal (&overlap, &imm32)
4852 && !operand_type_equal (&overlap, &imm32s)
4853 && !operand_type_equal (&overlap, &imm64))
29b0f896 4854 {
4eed87de
AM		 4855 as_bad (_("no instruction mnemonic suffix given; "
4856 "can't determine immediate size"));
29b0f896
AM		 4857 return 0;
4858 }
4859 }
40fb9820 4860 i.types[j] = overlap;
29b0f896 4861
40fb9820
L		 4862 return 1;
4863}
4864
4865static int
4866finalize_imm (void)
4867{
bc0844ae 4868 unsigned int j, n;
29b0f896 4869
bc0844ae
L		 4870 /* Update the first 2 immediate operands. */
4871 n = i.operands > 2 ? 2 : i.operands;
4872 if (n)
4873 {
4874 for (j = 0; j < n; j++)
4875 if (update_imm (j) == 0)
4876 return 0;
40fb9820 4877
bc0844ae
L		 4878 /* The 3rd operand can't be immediate operand. */
4879 gas_assert (operand_type_check (i.types[2], imm) == 0);
4880 }
29b0f896
AM		 4881
4882 return 1;
4883}
4884
c0f3af97
L		 4885static int
4886bad_implicit_operand (int xmm)
4887{
91d6fa6a
NC		 4888 const char *ireg = xmm ? "xmm0" : "ymm0";
4889
c0f3af97
L		 4890 if (intel_syntax)
4891 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4892 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4893 else
4894 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4895 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4896 return 0;
4897}
4898
29b0f896 4899static int
e3bb37b5 4900process_operands (void)
29b0f896
AM		 4901{
4902 /* Default segment register this instruction will use for memory
4903 accesses. 0 means unknown. This is only for optimizing out
4904 unnecessary segment overrides. */
4905 const seg_entry *default_seg = 0;
4906
2426c15f 4907 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4908 {
91d6fa6a
NC		 4909 unsigned int dupl = i.operands;
4910 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4911 unsigned int j;
4912
c0f3af97 4913 /* The destination must be an xmm register. */
9c2799c2 4914 gas_assert (i.reg_operands
91d6fa6a 4915 && MAX_OPERANDS > dupl
7ab9ffdd 4916 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4917
4918 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4919 {
c0f3af97 4920 /* The first operand is implicit and must be xmm0. */
9c2799c2 4921 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4922 if (i.op[0].regs->reg_num != 0)
4923 return bad_implicit_operand (1);
4924
8cd7925b 4925 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4926 {
4927 /* Keep xmm0 for instructions with VEX prefix and 3
4928 sources. */
4929 goto duplicate;
4930 }
e2ec9d29 4931 else
c0f3af97
L		 4932 {
4933 /* We remove the first xmm0 and keep the number of
4934 operands unchanged, which in fact duplicates the
4935 destination. */
4936 for (j = 1; j < i.operands; j++)
4937 {
4938 i.op[j - 1] = i.op[j];
4939 i.types[j - 1] = i.types[j];
4940 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4941 }
4942 }
4943 }
4944 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4945 {
91d6fa6a 4946 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4947 && (i.tm.opcode_modifier.vexsources
4948 == VEX3SOURCES));
c0f3af97
L		 4949
4950 /* Add the implicit xmm0 for instructions with VEX prefix
4951 and 3 sources. */
4952 for (j = i.operands; j > 0; j--)
4953 {
4954 i.op[j] = i.op[j - 1];
4955 i.types[j] = i.types[j - 1];
4956 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4957 }
4958 i.op[0].regs
4959 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4960 i.types[0] = regxmm;
c0f3af97
L		 4961 i.tm.operand_types[0] = regxmm;
4962
4963 i.operands += 2;
4964 i.reg_operands += 2;
4965 i.tm.operands += 2;
4966
91d6fa6a 4967 dupl++;
c0f3af97 4968 dest++;
91d6fa6a
NC		 4969 i.op[dupl] = i.op[dest];
4970 i.types[dupl] = i.types[dest];
4971 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4972 }
c0f3af97
L		 4973 else
4974 {
4975duplicate:
4976 i.operands++;
4977 i.reg_operands++;
4978 i.tm.operands++;
4979
91d6fa6a
NC		 4980 i.op[dupl] = i.op[dest];
4981 i.types[dupl] = i.types[dest];
4982 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4983 }
4984
4985 if (i.tm.opcode_modifier.immext)
4986 process_immext ();
4987 }
4988 else if (i.tm.opcode_modifier.firstxmm0)
4989 {
4990 unsigned int j;
4991
4992 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4993 gas_assert (i.reg_operands
7ab9ffdd
L		 4994 && (operand_type_equal (&i.types[0], &regxmm)
4995 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4996 if (i.op[0].regs->reg_num != 0)
4997 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4998
4999 for (j = 1; j < i.operands; j++)
5000 {
5001 i.op[j - 1] = i.op[j];
5002 i.types[j - 1] = i.types[j];
5003
5004 /* We need to adjust fields in i.tm since they are used by
5005 build_modrm_byte. */
5006 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5007 }
5008
e2ec9d29
L		 5009 i.operands--;
5010 i.reg_operands--;
e2ec9d29
L		 5011 i.tm.operands--;
5012 }
5013 else if (i.tm.opcode_modifier.regkludge)
5014 {
5015 /* The imul $imm, %reg instruction is converted into
5016 imul $imm, %reg, %reg, and the clr %reg instruction
5017 is converted into xor %reg, %reg. */
5018
5019 unsigned int first_reg_op;
5020
5021 if (operand_type_check (i.types[0], reg))
5022 first_reg_op = 0;
5023 else
5024 first_reg_op = 1;
5025 /* Pretend we saw the extra register operand. */
9c2799c2 5026 gas_assert (i.reg_operands == 1
7ab9ffdd 5027 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5028 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5029 i.types[first_reg_op + 1] = i.types[first_reg_op];
5030 i.operands++;
5031 i.reg_operands++;
29b0f896
AM		 5032 }
5033
40fb9820 5034 if (i.tm.opcode_modifier.shortform)
29b0f896 5035 {
40fb9820
L		 5036 if (i.types[0].bitfield.sreg2
5037 || i.types[0].bitfield.sreg3)
29b0f896 5038 {
4eed87de
AM		 5039 if (i.tm.base_opcode == POP_SEG_SHORT
5040 && i.op[0].regs->reg_num == 1)
29b0f896 5041 {
a87af027 5042 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5043 return 0;
29b0f896 5044 }
4eed87de
AM		 5045 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5046 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5047 i.rex |= REX_B;
4eed87de
AM		 5048 }
5049 else
5050 {
7ab9ffdd 5051 /* The register or float register operand is in operand
85f10a01 5052 0 or 1. */
40fb9820 5053 unsigned int op;
7ab9ffdd
L		 5054
5055 if (i.types[0].bitfield.floatreg
5056 || operand_type_check (i.types[0], reg))
5057 op = 0;
5058 else
5059 op = 1;
4eed87de
AM		 5060 /* Register goes in low 3 bits of opcode. */
5061 i.tm.base_opcode |= i.op[op].regs->reg_num;
5062 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5063 i.rex |= REX_B;
40fb9820 5064 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5065 {
4eed87de
AM		 5066 /* Warn about some common errors, but press on regardless.
5067 The first case can be generated by gcc (<= 2.8.1). */
5068 if (i.operands == 2)
5069 {
5070 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5071 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5072 register_prefix, i.op[!intel_syntax].regs->reg_name,
5073 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5074 }
5075 else
5076 {
5077 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5078 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5079 register_prefix, i.op[0].regs->reg_name);
4eed87de 5080 }
29b0f896
AM		 5081 }
5082 }
5083 }
40fb9820 5084 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5085 {
5086 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5087 must be put into the modrm byte). Now, we make the modrm and
5088 index base bytes based on all the info we've collected. */
29b0f896
AM		 5089
5090 default_seg = build_modrm_byte ();
5091 }
8a2ed489 5092 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5093 {
5094 default_seg = &ds;
5095 }
40fb9820 5096 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5097 {
5098 /* For the string instructions that allow a segment override
5099 on one of their operands, the default segment is ds. */
5100 default_seg = &ds;
5101 }
5102
75178d9d
L		 5103 if (i.tm.base_opcode == 0x8d /* lea */
5104 && i.seg[0]
5105 && !quiet_warnings)
30123838 5106 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5107
5108 /* If a segment was explicitly specified, and the specified segment
5109 is not the default, use an opcode prefix to select it. If we
5110 never figured out what the default segment is, then default_seg
5111 will be zero at this point, and the specified segment prefix will
5112 always be used. */
29b0f896
AM		 5113 if ((i.seg[0]) && (i.seg[0] != default_seg))
5114 {
5115 if (!add_prefix (i.seg[0]->seg_prefix))
5116 return 0;
5117 }
5118 return 1;
5119}
5120
5121static const seg_entry *
e3bb37b5 5122build_modrm_byte (void)
29b0f896
AM		 5123{
5124 const seg_entry *default_seg = 0;
c0f3af97 5125 unsigned int source, dest;
8cd7925b 5126 int vex_3_sources;
c0f3af97
L		 5127
5128 /* The first operand of instructions with VEX prefix and 3 sources
5129 must be VEX_Imm4. */
8cd7925b 5130 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5131 if (vex_3_sources)
5132 {
91d6fa6a 5133 unsigned int nds, reg_slot;
4c2c6516 5134 expressionS *exp;
c0f3af97 5135
922d8de8 5136 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5137 && i.tm.opcode_modifier.immext)
5138 {
5139 dest = i.operands - 2;
5140 gas_assert (dest == 3);
5141 }
922d8de8 5142 else
a683cc34 5143 dest = i.operands - 1;
c0f3af97 5144 nds = dest - 1;
922d8de8 5145
a683cc34
SP		 5146 /* There are 2 kinds of instructions:
5147 1. 5 operands: 4 register operands or 3 register operands
5148 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5149 VexW0 or VexW1. The destination must be either XMM or YMM
5150 register.
5151 2. 4 operands: 4 register operands or 3 register operands
5152 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5153 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5154 || (i.reg_operands == 3 && i.mem_operands == 1))
5155 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5156 && (i.tm.opcode_modifier.veximmext
5157 || (i.imm_operands == 1
5158 && i.types[0].bitfield.vec_imm4
5159 && (i.tm.opcode_modifier.vexw == VEXW0
5160 || i.tm.opcode_modifier.vexw == VEXW1)
5161 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5162 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5163
5164 if (i.imm_operands == 0)
5165 {
5166 /* When there is no immediate operand, generate an 8bit
5167 immediate operand to encode the first operand. */
5168 exp = &im_expressions[i.imm_operands++];
5169 i.op[i.operands].imms = exp;
5170 i.types[i.operands] = imm8;
5171 i.operands++;
5172 /* If VexW1 is set, the first operand is the source and
5173 the second operand is encoded in the immediate operand. */
5174 if (i.tm.opcode_modifier.vexw == VEXW1)
5175 {
5176 source = 0;
5177 reg_slot = 1;
5178 }
5179 else
5180 {
5181 source = 1;
5182 reg_slot = 0;
5183 }
5184
5185 /* FMA swaps REG and NDS. */
5186 if (i.tm.cpu_flags.bitfield.cpufma)
5187 {
5188 unsigned int tmp;
5189 tmp = reg_slot;
5190 reg_slot = nds;
5191 nds = tmp;
5192 }
5193
24981e7b
L		 5194 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5195 &regxmm)
a683cc34
SP		 5196 || operand_type_equal (&i.tm.operand_types[reg_slot],
5197 &regymm));
5198 exp->X_op = O_constant;
5199 exp->X_add_number
5200 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5201 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5202 << 4);
a683cc34 5203 }
922d8de8 5204 else
a683cc34
SP		 5205 {
5206 unsigned int imm_slot;
5207
5208 if (i.tm.opcode_modifier.vexw == VEXW0)
5209 {
5210 /* If VexW0 is set, the third operand is the source and
5211 the second operand is encoded in the immediate
5212 operand. */
5213 source = 2;
5214 reg_slot = 1;
5215 }
5216 else
5217 {
5218 /* VexW1 is set, the second operand is the source and
5219 the third operand is encoded in the immediate
5220 operand. */
5221 source = 1;
5222 reg_slot = 2;
5223 }
5224
5225 if (i.tm.opcode_modifier.immext)
5226 {
5227 /* When ImmExt is set, the immdiate byte is the last
5228 operand. */
5229 imm_slot = i.operands - 1;
5230 source--;
5231 reg_slot--;
5232 }
5233 else
5234 {
5235 imm_slot = 0;
5236
5237 /* Turn on Imm8 so that output_imm will generate it. */
5238 i.types[imm_slot].bitfield.imm8 = 1;
5239 }
5240
24981e7b
L		 5241 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5242 &regxmm)
5243 || operand_type_equal (&i.tm.operand_types[reg_slot],
5244 &regymm));
a683cc34
SP		 5245 i.op[imm_slot].imms->X_add_number
5246 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5247 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5248 << 4);
a683cc34
SP		 5249 }
5250
5251 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5252 || operand_type_equal (&i.tm.operand_types[nds],
5253 &regymm));
dae39acc 5254 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5255 }
5256 else
5257 source = dest = 0;
29b0f896
AM		 5258
5259 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5260 implicit registers do not count. If there are 3 register
5261 operands, it must be a instruction with VexNDS. For a
5262 instruction with VexNDD, the destination register is encoded
5263 in VEX prefix. If there are 4 register operands, it must be
5264 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5265 if (i.mem_operands == 0
5266 && ((i.reg_operands == 2
2426c15f 5267 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5268 || (i.reg_operands == 3
2426c15f 5269 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5270 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5271 {
cab737b9
L		 5272 switch (i.operands)
5273 {
5274 case 2:
5275 source = 0;
5276 break;
5277 case 3:
c81128dc
L		 5278 /* When there are 3 operands, one of them may be immediate,
5279 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5280 the first operand must be shift count register (cl) or it
5281 is an instruction with VexNDS. */
9c2799c2 5282 gas_assert (i.imm_operands == 1
7ab9ffdd 5283 || (i.imm_operands == 0
2426c15f 5284 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5285 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5286 if (operand_type_check (i.types[0], imm)
5287 || i.types[0].bitfield.shiftcount)
5288 source = 1;
5289 else
5290 source = 0;
cab737b9
L		 5291 break;
5292 case 4:
368d64cc
L		 5293 /* When there are 4 operands, the first two must be 8bit
5294 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5295 one.
5296
5297 For instructions with VexNDS, if the first operand
5298 an imm8, the source operand is the 2nd one. If the last
5299 operand is imm8, the source operand is the first one. */
9c2799c2 5300 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5301 && i.types[0].bitfield.imm8
5302 && i.types[1].bitfield.imm8)
2426c15f 5303 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5304 && i.imm_operands == 1
5305 && (i.types[0].bitfield.imm8
5306 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5307 if (i.imm_operands == 2)
5308 source = 2;
5309 else
c0f3af97
L		 5310 {
5311 if (i.types[0].bitfield.imm8)
5312 source = 1;
5313 else
5314 source = 0;
5315 }
c0f3af97
L		 5316 break;
5317 case 5:
cab737b9
L		 5318 break;
5319 default:
5320 abort ();
5321 }
5322
c0f3af97
L		 5323 if (!vex_3_sources)
5324 {
5325 dest = source + 1;
5326
2426c15f 5327 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5328 {
5329 /* For instructions with VexNDS, the register-only
f12dc422
L		 5330 source operand must be 32/64bit integer, XMM or
5331 YMM register. It is encoded in VEX prefix. We
5332 need to clear RegMem bit before calling
5333 operand_type_equal. */
5334
5335 i386_operand_type op;
5336 unsigned int vvvv;
5337
5338 /* Check register-only source operand when two source
5339 operands are swapped. */
5340 if (!i.tm.operand_types[source].bitfield.baseindex
5341 && i.tm.operand_types[dest].bitfield.baseindex)
5342 {
5343 vvvv = source;
5344 source = dest;
5345 }
5346 else
5347 vvvv = dest;
5348
5349 op = i.tm.operand_types[vvvv];
fa99fab2 5350 op.bitfield.regmem = 0;
c0f3af97 5351 if ((dest + 1) >= i.operands
f12dc422
L		 5352 || (op.bitfield.reg32 != 1
5353 && !op.bitfield.reg64 != 1
5354 && !operand_type_equal (&op, &regxmm)
fa99fab2 5355 && !operand_type_equal (&op, &regymm)))
c0f3af97 5356 abort ();
f12dc422 5357 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5358 dest++;
5359 }
5360 }
29b0f896
AM		 5361
5362 i.rm.mode = 3;
5363 /* One of the register operands will be encoded in the i.tm.reg
5364 field, the other in the combined i.tm.mode and i.tm.regmem
5365 fields. If no form of this instruction supports a memory
5366 destination operand, then we assume the source operand may
5367 sometimes be a memory operand and so we need to store the
5368 destination in the i.rm.reg field. */
40fb9820
L		 5369 if (!i.tm.operand_types[dest].bitfield.regmem
5370 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5371 {
5372 i.rm.reg = i.op[dest].regs->reg_num;
5373 i.rm.regmem = i.op[source].regs->reg_num;
5374 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5375 i.rex |= REX_R;
29b0f896 5376 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5377 i.rex |= REX_B;
29b0f896
AM		 5378 }
5379 else
5380 {
5381 i.rm.reg = i.op[source].regs->reg_num;
5382 i.rm.regmem = i.op[dest].regs->reg_num;
5383 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5384 i.rex |= REX_B;
29b0f896 5385 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5386 i.rex |= REX_R;
29b0f896 5387 }
161a04f6 5388 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5389 {
40fb9820
L		 5390 if (!i.types[0].bitfield.control
5391 && !i.types[1].bitfield.control)
c4a530c5 5392 abort ();
161a04f6 5393 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5394 add_prefix (LOCK_PREFIX_OPCODE);
5395 }
29b0f896
AM		 5396 }
5397 else
5398 { /* If it's not 2 reg operands... */
c0f3af97
L		 5399 unsigned int mem;
5400
29b0f896
AM		 5401 if (i.mem_operands)
5402 {
5403 unsigned int fake_zero_displacement = 0;
99018f42 5404 unsigned int op;
4eed87de 5405
7ab9ffdd
L		 5406 for (op = 0; op < i.operands; op++)
5407 if (operand_type_check (i.types[op], anymem))
5408 break;
7ab9ffdd 5409 gas_assert (op < i.operands);
29b0f896
AM		 5410
5411 default_seg = &ds;
5412
5413 if (i.base_reg == 0)
5414 {
5415 i.rm.mode = 0;
5416 if (!i.disp_operands)
5417 fake_zero_displacement = 1;
5418 if (i.index_reg == 0)
5419 {
5420 /* Operand is just <disp> */
20f0a1fc 5421 if (flag_code == CODE_64BIT)
29b0f896
AM		 5422 {
5423 /* 64bit mode overwrites the 32bit absolute
5424 addressing by RIP relative addressing and
5425 absolute addressing is encoded by one of the
5426 redundant SIB forms. */
5427 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5428 i.sib.base = NO_BASE_REGISTER;
5429 i.sib.index = NO_INDEX_REGISTER;
fc225355 5430 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5431 ? disp32s : disp32);
20f0a1fc 5432 }
fc225355
L		 5433 else if ((flag_code == CODE_16BIT)
5434 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5435 {
5436 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5437 i.types[op] = disp16;
20f0a1fc
NC		 5438 }
5439 else
5440 {
5441 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5442 i.types[op] = disp32;
29b0f896
AM		 5443 }
5444 }
5445 else /* !i.base_reg && i.index_reg */
5446 {
db51cc60
L		 5447 if (i.index_reg->reg_num == RegEiz
5448 || i.index_reg->reg_num == RegRiz)
5449 i.sib.index = NO_INDEX_REGISTER;
5450 else
5451 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5452 i.sib.base = NO_BASE_REGISTER;
5453 i.sib.scale = i.log2_scale_factor;
5454 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5455 i.types[op].bitfield.disp8 = 0;
5456 i.types[op].bitfield.disp16 = 0;
5457 i.types[op].bitfield.disp64 = 0;
29b0f896 5458 if (flag_code != CODE_64BIT)
40fb9820
L		 5459 {
5460 /* Must be 32 bit */
5461 i.types[op].bitfield.disp32 = 1;
5462 i.types[op].bitfield.disp32s = 0;
5463 }
29b0f896 5464 else
40fb9820
L		 5465 {
5466 i.types[op].bitfield.disp32 = 0;
5467 i.types[op].bitfield.disp32s = 1;
5468 }
29b0f896 5469 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5470 i.rex |= REX_X;
29b0f896
AM		 5471 }
5472 }
5473 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5474 else if (i.base_reg->reg_num == RegRip ||
5475 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5476 {
5477 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5478 i.types[op].bitfield.disp8 = 0;
5479 i.types[op].bitfield.disp16 = 0;
5480 i.types[op].bitfield.disp32 = 0;
5481 i.types[op].bitfield.disp32s = 1;
5482 i.types[op].bitfield.disp64 = 0;
71903a11 5483 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5484 if (! i.disp_operands)
5485 fake_zero_displacement = 1;
29b0f896 5486 }
40fb9820 5487 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5488 {
5489 switch (i.base_reg->reg_num)
5490 {
5491 case 3: /* (%bx) */
5492 if (i.index_reg == 0)
5493 i.rm.regmem = 7;
5494 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5495 i.rm.regmem = i.index_reg->reg_num - 6;
5496 break;
5497 case 5: /* (%bp) */
5498 default_seg = &ss;
5499 if (i.index_reg == 0)
5500 {
5501 i.rm.regmem = 6;
40fb9820 5502 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5503 {
5504 /* fake (%bp) into 0(%bp) */
40fb9820 5505 i.types[op].bitfield.disp8 = 1;
252b5132 5506 fake_zero_displacement = 1;
29b0f896
AM		 5507 }
5508 }
5509 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5510 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5511 break;
5512 default: /* (%si) -> 4 or (%di) -> 5 */
5513 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5514 }
5515 i.rm.mode = mode_from_disp_size (i.types[op]);
5516 }
5517 else /* i.base_reg and 32/64 bit mode */
5518 {
5519 if (flag_code == CODE_64BIT
40fb9820
L		 5520 && operand_type_check (i.types[op], disp))
5521 {
5522 i386_operand_type temp;
0dfbf9d7 5523 operand_type_set (&temp, 0);
40fb9820
L		 5524 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5525 i.types[op] = temp;
5526 if (i.prefix[ADDR_PREFIX] == 0)
5527 i.types[op].bitfield.disp32s = 1;
5528 else
5529 i.types[op].bitfield.disp32 = 1;
5530 }
20f0a1fc 5531
29b0f896
AM		 5532 i.rm.regmem = i.base_reg->reg_num;
5533 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5534 i.rex |= REX_B;
29b0f896
AM		 5535 i.sib.base = i.base_reg->reg_num;
5536 /* x86-64 ignores REX prefix bit here to avoid decoder
5537 complications. */
5538 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5539 {
5540 default_seg = &ss;
5541 if (i.disp_operands == 0)
5542 {
5543 fake_zero_displacement = 1;
40fb9820 5544 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5545 }
5546 }
5547 else if (i.base_reg->reg_num == ESP_REG_NUM)
5548 {
5549 default_seg = &ss;
5550 }
5551 i.sib.scale = i.log2_scale_factor;
5552 if (i.index_reg == 0)
5553 {
5554 /* <disp>(%esp) becomes two byte modrm with no index
5555 register. We've already stored the code for esp
5556 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5557 Any base register besides %esp will not use the
5558 extra modrm byte. */
5559 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5560 }
5561 else
5562 {
db51cc60
L		 5563 if (i.index_reg->reg_num == RegEiz
5564 || i.index_reg->reg_num == RegRiz)
5565 i.sib.index = NO_INDEX_REGISTER;
5566 else
5567 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5568 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5569 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5570 i.rex |= REX_X;
29b0f896 5571 }
67a4f2b7
AO		 5572
5573 if (i.disp_operands
5574 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5575 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5576 i.rm.mode = 0;
5577 else
5578 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5579 }
252b5132 5580
29b0f896
AM		 5581 if (fake_zero_displacement)
5582 {
5583 /* Fakes a zero displacement assuming that i.types[op]
5584 holds the correct displacement size. */
5585 expressionS *exp;
5586
9c2799c2 5587 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5588 exp = &disp_expressions[i.disp_operands++];
5589 i.op[op].disps = exp;
5590 exp->X_op = O_constant;
5591 exp->X_add_number = 0;
5592 exp->X_add_symbol = (symbolS *) 0;
5593 exp->X_op_symbol = (symbolS *) 0;
5594 }
c0f3af97
L		 5595
5596 mem = op;
29b0f896 5597 }
c0f3af97
L		 5598 else
5599 mem = ~0;
252b5132 5600
8c43a48b 5601 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5602 {
5603 if (operand_type_check (i.types[0], imm))
5604 i.vex.register_specifier = NULL;
5605 else
5606 {
5607 /* VEX.vvvv encodes one of the sources when the first
5608 operand is not an immediate. */
1ef99a7b 5609 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5610 i.vex.register_specifier = i.op[0].regs;
5611 else
5612 i.vex.register_specifier = i.op[1].regs;
5613 }
5614
5615 /* Destination is a XMM register encoded in the ModRM.reg
5616 and VEX.R bit. */
5617 i.rm.reg = i.op[2].regs->reg_num;
5618 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5619 i.rex |= REX_R;
5620
5621 /* ModRM.rm and VEX.B encodes the other source. */
5622 if (!i.mem_operands)
5623 {
5624 i.rm.mode = 3;
5625
1ef99a7b 5626 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5627 i.rm.regmem = i.op[1].regs->reg_num;
5628 else
5629 i.rm.regmem = i.op[0].regs->reg_num;
5630
5631 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5632 i.rex |= REX_B;
5633 }
5634 }
2426c15f 5635 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5636 {
5637 i.vex.register_specifier = i.op[2].regs;
5638 if (!i.mem_operands)
5639 {
5640 i.rm.mode = 3;
5641 i.rm.regmem = i.op[1].regs->reg_num;
5642 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5643 i.rex |= REX_B;
5644 }
5645 }
29b0f896
AM		 5646 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5647 (if any) based on i.tm.extension_opcode. Again, we must be
5648 careful to make sure that segment/control/debug/test/MMX
5649 registers are coded into the i.rm.reg field. */
f88c9eb0 5650 else if (i.reg_operands)
29b0f896 5651 {
99018f42 5652 unsigned int op;
7ab9ffdd
L		 5653 unsigned int vex_reg = ~0;
5654
5655 for (op = 0; op < i.operands; op++)
5656 if (i.types[op].bitfield.reg8
5657 || i.types[op].bitfield.reg16
5658 || i.types[op].bitfield.reg32
5659 || i.types[op].bitfield.reg64
5660 || i.types[op].bitfield.regmmx
5661 || i.types[op].bitfield.regxmm
5662 || i.types[op].bitfield.regymm
5663 || i.types[op].bitfield.sreg2
5664 || i.types[op].bitfield.sreg3
5665 || i.types[op].bitfield.control
5666 || i.types[op].bitfield.debug
5667 || i.types[op].bitfield.test)
5668 break;
c0209578 5669
7ab9ffdd
L		 5670 if (vex_3_sources)
5671 op = dest;
2426c15f 5672 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5673 {
5674 /* For instructions with VexNDS, the register-only
5675 source operand is encoded in VEX prefix. */
5676 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5677
7ab9ffdd 5678 if (op > mem)
c0f3af97 5679 {
7ab9ffdd
L		 5680 vex_reg = op++;
5681 gas_assert (op < i.operands);
c0f3af97
L		 5682 }
5683 else
c0f3af97 5684 {
f12dc422
L		 5685 /* Check register-only source operand when two source
5686 operands are swapped. */
5687 if (!i.tm.operand_types[op].bitfield.baseindex
5688 && i.tm.operand_types[op + 1].bitfield.baseindex)
5689 {
5690 vex_reg = op;
5691 op += 2;
5692 gas_assert (mem == (vex_reg + 1)
5693 && op < i.operands);
5694 }
5695 else
5696 {
5697 vex_reg = op + 1;
5698 gas_assert (vex_reg < i.operands);
5699 }
c0f3af97 5700 }
7ab9ffdd 5701 }
2426c15f 5702 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5703 {
f12dc422 5704 /* For instructions with VexNDD, the register destination
7ab9ffdd 5705 is encoded in VEX prefix. */
f12dc422
L		 5706 if (i.mem_operands == 0)
5707 {
5708 /* There is no memory operand. */
5709 gas_assert ((op + 2) == i.operands);
5710 vex_reg = op + 1;
5711 }
5712 else
5713 {
5714 /* There are only 2 operands. */
5715 gas_assert (op < 2 && i.operands == 2);
5716 vex_reg = 1;
5717 }
7ab9ffdd
L		 5718 }
5719 else
5720 gas_assert (op < i.operands);
99018f42 5721
7ab9ffdd
L		 5722 if (vex_reg != (unsigned int) ~0)
5723 {
f12dc422 5724 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5725
f12dc422
L		 5726 if (type->bitfield.reg32 != 1
5727 && type->bitfield.reg64 != 1
5728 && !operand_type_equal (type, &regxmm)
5729 && !operand_type_equal (type, &regymm))
7ab9ffdd 5730 abort ();
f88c9eb0 5731
7ab9ffdd
L		 5732 i.vex.register_specifier = i.op[vex_reg].regs;
5733 }
5734
1b9f0c97
L		 5735 /* Don't set OP operand twice. */
5736 if (vex_reg != op)
7ab9ffdd 5737 {
1b9f0c97
L		 5738 /* If there is an extension opcode to put here, the
5739 register number must be put into the regmem field. */
5740 if (i.tm.extension_opcode != None)
5741 {
5742 i.rm.regmem = i.op[op].regs->reg_num;
5743 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5744 i.rex |= REX_B;
5745 }
5746 else
5747 {
5748 i.rm.reg = i.op[op].regs->reg_num;
5749 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5750 i.rex |= REX_R;
5751 }
7ab9ffdd 5752 }
252b5132 5753
29b0f896
AM		 5754 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5755 must set it to 3 to indicate this is a register operand
5756 in the regmem field. */
5757 if (!i.mem_operands)
5758 i.rm.mode = 3;
5759 }
252b5132 5760
29b0f896 5761 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5762 if (i.tm.extension_opcode != None)
29b0f896
AM		 5763 i.rm.reg = i.tm.extension_opcode;
5764 }
5765 return default_seg;
5766}
252b5132 5767
29b0f896 5768static void
e3bb37b5 5769output_branch (void)
29b0f896
AM		 5770{
5771 char *p;
f8a5c266 5772 int size;
29b0f896
AM		 5773 int code16;
5774 int prefix;
5775 relax_substateT subtype;
5776 symbolS *sym;
5777 offsetT off;
5778
f8a5c266
L		 5779 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5780 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5781
5782 prefix = 0;
5783 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5784 {
29b0f896
AM		 5785 prefix = 1;
5786 i.prefixes -= 1;
5787 code16 ^= CODE16;
252b5132 5788 }
29b0f896
AM		 5789 /* Pentium4 branch hints. */
5790 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5791 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5792 {
29b0f896
AM		 5793 prefix++;
5794 i.prefixes--;
5795 }
5796 if (i.prefix[REX_PREFIX] != 0)
5797 {
5798 prefix++;
5799 i.prefixes--;
2f66722d
AM		 5800 }
5801
29b0f896
AM		 5802 if (i.prefixes != 0 && !intel_syntax)
5803 as_warn (_("skipping prefixes on this instruction"));
5804
5805 /* It's always a symbol; End frag & setup for relax.
5806 Make sure there is enough room in this frag for the largest
5807 instruction we may generate in md_convert_frag. This is 2
5808 bytes for the opcode and room for the prefix and largest
5809 displacement. */
5810 frag_grow (prefix + 2 + 4);
5811 /* Prefix and 1 opcode byte go in fr_fix. */
5812 p = frag_more (prefix + 1);
5813 if (i.prefix[DATA_PREFIX] != 0)
5814 *p++ = DATA_PREFIX_OPCODE;
5815 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5816 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5817 *p++ = i.prefix[SEG_PREFIX];
5818 if (i.prefix[REX_PREFIX] != 0)
5819 *p++ = i.prefix[REX_PREFIX];
5820 *p = i.tm.base_opcode;
5821
5822 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5823 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5824 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5825 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5826 else
f8a5c266 5827 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5828 subtype |= code16;
3e73aa7c 5829
29b0f896
AM		 5830 sym = i.op[0].disps->X_add_symbol;
5831 off = i.op[0].disps->X_add_number;
3e73aa7c 5832
29b0f896
AM		 5833 if (i.op[0].disps->X_op != O_constant
5834 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5835 {
29b0f896
AM		 5836 /* Handle complex expressions. */
5837 sym = make_expr_symbol (i.op[0].disps);
5838 off = 0;
5839 }
3e73aa7c 5840
29b0f896
AM		 5841 /* 1 possible extra opcode + 4 byte displacement go in var part.
5842 Pass reloc in fr_var. */
5843 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5844}
3e73aa7c 5845
29b0f896 5846static void
e3bb37b5 5847output_jump (void)
29b0f896
AM		 5848{
5849 char *p;
5850 int size;
3e02c1cc 5851 fixS *fixP;
29b0f896 5852
40fb9820 5853 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5854 {
5855 /* This is a loop or jecxz type instruction. */
5856 size = 1;
5857 if (i.prefix[ADDR_PREFIX] != 0)
5858 {
5859 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5860 i.prefixes -= 1;
5861 }
5862 /* Pentium4 branch hints. */
5863 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5864 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5865 {
5866 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5867 i.prefixes--;
3e73aa7c
JH		 5868 }
5869 }
29b0f896
AM		 5870 else
5871 {
5872 int code16;
3e73aa7c 5873
29b0f896
AM		 5874 code16 = 0;
5875 if (flag_code == CODE_16BIT)
5876 code16 = CODE16;
3e73aa7c 5877
29b0f896
AM		 5878 if (i.prefix[DATA_PREFIX] != 0)
5879 {
5880 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5881 i.prefixes -= 1;
5882 code16 ^= CODE16;
5883 }
252b5132 5884
29b0f896
AM		 5885 size = 4;
5886 if (code16)
5887 size = 2;
5888 }
9fcc94b6 5889
29b0f896
AM		 5890 if (i.prefix[REX_PREFIX] != 0)
5891 {
5892 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5893 i.prefixes -= 1;
5894 }
252b5132 5895
29b0f896
AM		 5896 if (i.prefixes != 0 && !intel_syntax)
5897 as_warn (_("skipping prefixes on this instruction"));
e0890092 5898
29b0f896
AM		 5899 p = frag_more (1 + size);
5900 *p++ = i.tm.base_opcode;
e0890092 5901
3e02c1cc
AM		 5902 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5903 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5904
5905 /* All jumps handled here are signed, but don't use a signed limit
5906 check for 32 and 16 bit jumps as we want to allow wrap around at
5907 4G and 64k respectively. */
5908 if (size == 1)
5909 fixP->fx_signed = 1;
29b0f896 5910}
e0890092 5911
29b0f896 5912static void
e3bb37b5 5913output_interseg_jump (void)
29b0f896
AM		 5914{
5915 char *p;
5916 int size;
5917 int prefix;
5918 int code16;
252b5132 5919
29b0f896
AM		 5920 code16 = 0;
5921 if (flag_code == CODE_16BIT)
5922 code16 = CODE16;
a217f122 5923
29b0f896
AM		 5924 prefix = 0;
5925 if (i.prefix[DATA_PREFIX] != 0)
5926 {
5927 prefix = 1;
5928 i.prefixes -= 1;
5929 code16 ^= CODE16;
5930 }
5931 if (i.prefix[REX_PREFIX] != 0)
5932 {
5933 prefix++;
5934 i.prefixes -= 1;
5935 }
252b5132 5936
29b0f896
AM		 5937 size = 4;
5938 if (code16)
5939 size = 2;
252b5132 5940
29b0f896
AM		 5941 if (i.prefixes != 0 && !intel_syntax)
5942 as_warn (_("skipping prefixes on this instruction"));
252b5132 5943
29b0f896
AM		 5944 /* 1 opcode; 2 segment; offset */
5945 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5946
29b0f896
AM		 5947 if (i.prefix[DATA_PREFIX] != 0)
5948 *p++ = DATA_PREFIX_OPCODE;
252b5132 5949
29b0f896
AM		 5950 if (i.prefix[REX_PREFIX] != 0)
5951 *p++ = i.prefix[REX_PREFIX];
252b5132 5952
29b0f896
AM		 5953 *p++ = i.tm.base_opcode;
5954 if (i.op[1].imms->X_op == O_constant)
5955 {
5956 offsetT n = i.op[1].imms->X_add_number;
252b5132 5957
29b0f896
AM		 5958 if (size == 2
5959 && !fits_in_unsigned_word (n)
5960 && !fits_in_signed_word (n))
5961 {
5962 as_bad (_("16-bit jump out of range"));
5963 return;
5964 }
5965 md_number_to_chars (p, n, size);
5966 }
5967 else
5968 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5969 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5970 if (i.op[0].imms->X_op != O_constant)
5971 as_bad (_("can't handle non absolute segment in `%s'"),
5972 i.tm.name);
5973 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5974}
a217f122 5975
29b0f896 5976static void
e3bb37b5 5977output_insn (void)
29b0f896 5978{
2bbd9c25
JJ		 5979 fragS *insn_start_frag;
5980 offsetT insn_start_off;
5981
29b0f896
AM		 5982 /* Tie dwarf2 debug info to the address at the start of the insn.
5983 We can't do this after the insn has been output as the current
5984 frag may have been closed off. eg. by frag_var. */
5985 dwarf2_emit_insn (0);
5986
2bbd9c25
JJ		 5987 insn_start_frag = frag_now;
5988 insn_start_off = frag_now_fix ();
5989
29b0f896 5990 /* Output jumps. */
40fb9820 5991 if (i.tm.opcode_modifier.jump)
29b0f896 5992 output_branch ();
40fb9820
L		 5993 else if (i.tm.opcode_modifier.jumpbyte
5994 || i.tm.opcode_modifier.jumpdword)
29b0f896 5995 output_jump ();
40fb9820 5996 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5997 output_interseg_jump ();
5998 else
5999 {
6000 /* Output normal instructions here. */
6001 char *p;
6002 unsigned char *q;
47465058 6003 unsigned int j;
331d2d0d 6004 unsigned int prefix;
4dffcebc 6005
c0f3af97
L		 6006 /* Since the VEX prefix contains the implicit prefix, we don't
6007 need the explicit prefix. */
6008 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6009 {
c0f3af97 6010 switch (i.tm.opcode_length)
bc4bd9ab 6011 {
c0f3af97
L		 6012 case 3:
6013 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6014 {
c0f3af97
L		 6015 prefix = (i.tm.base_opcode >> 24) & 0xff;
6016 goto check_prefix;
6017 }
6018 break;
6019 case 2:
6020 if ((i.tm.base_opcode & 0xff0000) != 0)
6021 {
6022 prefix = (i.tm.base_opcode >> 16) & 0xff;
6023 if (i.tm.cpu_flags.bitfield.cpupadlock)
6024 {
4dffcebc 6025check_prefix:
c0f3af97 6026 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6027 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6028 != REPE_PREFIX_OPCODE))
6029 add_prefix (prefix);
6030 }
6031 else
4dffcebc
L		 6032 add_prefix (prefix);
6033 }
c0f3af97
L		 6034 break;
6035 case 1:
6036 break;
6037 default:
6038 abort ();
bc4bd9ab 6039 }
c0f3af97
L		 6040
6041 /* The prefix bytes. */
6042 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6043 if (*q)
6044 FRAG_APPEND_1_CHAR (*q);
0f10071e 6045 }
252b5132 6046
c0f3af97
L		 6047 if (i.tm.opcode_modifier.vex)
6048 {
6049 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6050 if (*q)
6051 switch (j)
6052 {
6053 case REX_PREFIX:
6054 /* REX byte is encoded in VEX prefix. */
6055 break;
6056 case SEG_PREFIX:
6057 case ADDR_PREFIX:
6058 FRAG_APPEND_1_CHAR (*q);
6059 break;
6060 default:
6061 /* There should be no other prefixes for instructions
6062 with VEX prefix. */
6063 abort ();
6064 }
6065
6066 /* Now the VEX prefix. */
6067 p = frag_more (i.vex.length);
6068 for (j = 0; j < i.vex.length; j++)
6069 p[j] = i.vex.bytes[j];
6070 }
252b5132 6071
29b0f896 6072 /* Now the opcode; be careful about word order here! */
4dffcebc 6073 if (i.tm.opcode_length == 1)
29b0f896
AM		 6074 {
6075 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6076 }
6077 else
6078 {
4dffcebc 6079 switch (i.tm.opcode_length)
331d2d0d 6080 {
4dffcebc 6081 case 3:
331d2d0d
L		 6082 p = frag_more (3);
6083 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6084 break;
6085 case 2:
6086 p = frag_more (2);
6087 break;
6088 default:
6089 abort ();
6090 break;
331d2d0d 6091 }
0f10071e 6092
29b0f896
AM		 6093 /* Put out high byte first: can't use md_number_to_chars! */
6094 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6095 *p = i.tm.base_opcode & 0xff;
6096 }
3e73aa7c 6097
29b0f896 6098 /* Now the modrm byte and sib byte (if present). */
40fb9820 6099 if (i.tm.opcode_modifier.modrm)
29b0f896 6100 {
4a3523fa
L		 6101 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6102 | i.rm.reg << 3
6103 | i.rm.mode << 6));
29b0f896
AM		 6104 /* If i.rm.regmem == ESP (4)
6105 && i.rm.mode != (Register mode)
6106 && not 16 bit
6107 ==> need second modrm byte. */
6108 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6109 && i.rm.mode != 3
40fb9820 6110 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6111 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6112 | i.sib.index << 3
6113 | i.sib.scale << 6));
29b0f896 6114 }
3e73aa7c 6115
29b0f896 6116 if (i.disp_operands)
2bbd9c25 6117 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6118
29b0f896 6119 if (i.imm_operands)
2bbd9c25 6120 output_imm (insn_start_frag, insn_start_off);
29b0f896 6121 }
252b5132 6122
29b0f896
AM		 6123#ifdef DEBUG386
6124 if (flag_debug)
6125 {
7b81dfbb 6126 pi ("" /*line*/, &i);
29b0f896
AM		 6127 }
6128#endif /* DEBUG386 */
6129}
252b5132 6130
e205caa7
L		 6131/* Return the size of the displacement operand N. */
6132
6133static int
6134disp_size (unsigned int n)
6135{
6136 int size = 4;
40fb9820
L		 6137 if (i.types[n].bitfield.disp64)
6138 size = 8;
6139 else if (i.types[n].bitfield.disp8)
6140 size = 1;
6141 else if (i.types[n].bitfield.disp16)
6142 size = 2;
e205caa7
L		 6143 return size;
6144}
6145
6146/* Return the size of the immediate operand N. */
6147
6148static int
6149imm_size (unsigned int n)
6150{
6151 int size = 4;
40fb9820
L		 6152 if (i.types[n].bitfield.imm64)
6153 size = 8;
6154 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6155 size = 1;
6156 else if (i.types[n].bitfield.imm16)
6157 size = 2;
e205caa7
L		 6158 return size;
6159}
6160
29b0f896 6161static void
64e74474 6162output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6163{
6164 char *p;
6165 unsigned int n;
252b5132 6166
29b0f896
AM		 6167 for (n = 0; n < i.operands; n++)
6168 {
40fb9820 6169 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6170 {
6171 if (i.op[n].disps->X_op == O_constant)
6172 {
e205caa7 6173 int size = disp_size (n);
29b0f896 6174 offsetT val;
252b5132 6175
29b0f896
AM		 6176 val = offset_in_range (i.op[n].disps->X_add_number,
6177 size);
6178 p = frag_more (size);
6179 md_number_to_chars (p, val, size);
6180 }
6181 else
6182 {
f86103b7 6183 enum bfd_reloc_code_real reloc_type;
e205caa7 6184 int size = disp_size (n);
40fb9820 6185 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6186 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6187
e205caa7 6188 /* We can't have 8 bit displacement here. */
9c2799c2 6189 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6190
29b0f896
AM		 6191 /* The PC relative address is computed relative
6192 to the instruction boundary, so in case immediate
6193 fields follows, we need to adjust the value. */
6194 if (pcrel && i.imm_operands)
6195 {
29b0f896 6196 unsigned int n1;
e205caa7 6197 int sz = 0;
252b5132 6198
29b0f896 6199 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6200 if (operand_type_check (i.types[n1], imm))
252b5132 6201 {
e205caa7
L		 6202 /* Only one immediate is allowed for PC
6203 relative address. */
9c2799c2 6204 gas_assert (sz == 0);
e205caa7
L		 6205 sz = imm_size (n1);
6206 i.op[n].disps->X_add_number -= sz;
252b5132 6207 }
29b0f896 6208 /* We should find the immediate. */
9c2799c2 6209 gas_assert (sz != 0);
29b0f896 6210 }
520dc8e8 6211
29b0f896 6212 p = frag_more (size);
2bbd9c25 6213 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6214 if (GOT_symbol
2bbd9c25 6215 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6216 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6217 || reloc_type == BFD_RELOC_X86_64_32S
6218 || (reloc_type == BFD_RELOC_64
6219 && object_64bit))
d6ab8113
JB		 6220 && (i.op[n].disps->X_op == O_symbol
6221 || (i.op[n].disps->X_op == O_add
6222 && ((symbol_get_value_expression
6223 (i.op[n].disps->X_op_symbol)->X_op)
6224 == O_subtract))))
6225 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6226 {
6227 offsetT add;
6228
6229 if (insn_start_frag == frag_now)
6230 add = (p - frag_now->fr_literal) - insn_start_off;
6231 else
6232 {
6233 fragS *fr;
6234
6235 add = insn_start_frag->fr_fix - insn_start_off;
6236 for (fr = insn_start_frag->fr_next;
6237 fr && fr != frag_now; fr = fr->fr_next)
6238 add += fr->fr_fix;
6239 add += p - frag_now->fr_literal;
6240 }
6241
4fa24527 6242 if (!object_64bit)
7b81dfbb
AJ		 6243 {
6244 reloc_type = BFD_RELOC_386_GOTPC;
6245 i.op[n].imms->X_add_number += add;
6246 }
6247 else if (reloc_type == BFD_RELOC_64)
6248 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6249 else
7b81dfbb
AJ		 6250 /* Don't do the adjustment for x86-64, as there
6251 the pcrel addressing is relative to the _next_
6252 insn, and that is taken care of in other code. */
d6ab8113 6253 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6254 }
062cd5e7 6255 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6256 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6257 }
6258 }
6259 }
6260}
252b5132 6261
29b0f896 6262static void
64e74474 6263output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6264{
6265 char *p;
6266 unsigned int n;
252b5132 6267
29b0f896
AM		 6268 for (n = 0; n < i.operands; n++)
6269 {
40fb9820 6270 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6271 {
6272 if (i.op[n].imms->X_op == O_constant)
6273 {
e205caa7 6274 int size = imm_size (n);
29b0f896 6275 offsetT val;
b4cac588 6276
29b0f896
AM		 6277 val = offset_in_range (i.op[n].imms->X_add_number,
6278 size);
6279 p = frag_more (size);
6280 md_number_to_chars (p, val, size);
6281 }
6282 else
6283 {
6284 /* Not absolute_section.
6285 Need a 32-bit fixup (don't support 8bit
6286 non-absolute imms). Try to support other
6287 sizes ... */
f86103b7 6288 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6289 int size = imm_size (n);
6290 int sign;
29b0f896 6291
40fb9820 6292 if (i.types[n].bitfield.imm32s
a7d61044 6293 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6294 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6295 sign = 1;
e205caa7
L		 6296 else
6297 sign = 0;
520dc8e8 6298
29b0f896
AM		 6299 p = frag_more (size);
6300 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6301
2bbd9c25
JJ		 6302 /* This is tough to explain. We end up with this one if we
6303 * have operands that look like
6304 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6305 * obtain the absolute address of the GOT, and it is strongly
6306 * preferable from a performance point of view to avoid using
6307 * a runtime relocation for this. The actual sequence of
6308 * instructions often look something like:
6309 *
6310 * call .L66
6311 * .L66:
6312 * popl %ebx
6313 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6314 *
6315 * The call and pop essentially return the absolute address
6316 * of the label .L66 and store it in %ebx. The linker itself
6317 * will ultimately change the first operand of the addl so
6318 * that %ebx points to the GOT, but to keep things simple, the
6319 * .o file must have this operand set so that it generates not
6320 * the absolute address of .L66, but the absolute address of
6321 * itself. This allows the linker itself simply treat a GOTPC
6322 * relocation as asking for a pcrel offset to the GOT to be
6323 * added in, and the addend of the relocation is stored in the
6324 * operand field for the instruction itself.
6325 *
6326 * Our job here is to fix the operand so that it would add
6327 * the correct offset so that %ebx would point to itself. The
6328 * thing that is tricky is that .-.L66 will point to the
6329 * beginning of the instruction, so we need to further modify
6330 * the operand so that it will point to itself. There are
6331 * other cases where you have something like:
6332 *
6333 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6334 *
6335 * and here no correction would be required. Internally in
6336 * the assembler we treat operands of this form as not being
6337 * pcrel since the '.' is explicitly mentioned, and I wonder
6338 * whether it would simplify matters to do it this way. Who
6339 * knows. In earlier versions of the PIC patches, the
6340 * pcrel_adjust field was used to store the correction, but
6341 * since the expression is not pcrel, I felt it would be
6342 * confusing to do it this way. */
6343
d6ab8113 6344 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6345 || reloc_type == BFD_RELOC_X86_64_32S
6346 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6347 && GOT_symbol
6348 && GOT_symbol == i.op[n].imms->X_add_symbol
6349 && (i.op[n].imms->X_op == O_symbol
6350 || (i.op[n].imms->X_op == O_add
6351 && ((symbol_get_value_expression
6352 (i.op[n].imms->X_op_symbol)->X_op)
6353 == O_subtract))))
6354 {
2bbd9c25
JJ		 6355 offsetT add;
6356
6357 if (insn_start_frag == frag_now)
6358 add = (p - frag_now->fr_literal) - insn_start_off;
6359 else
6360 {
6361 fragS *fr;
6362
6363 add = insn_start_frag->fr_fix - insn_start_off;
6364 for (fr = insn_start_frag->fr_next;
6365 fr && fr != frag_now; fr = fr->fr_next)
6366 add += fr->fr_fix;
6367 add += p - frag_now->fr_literal;
6368 }
6369
4fa24527 6370 if (!object_64bit)
d6ab8113 6371 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6372 else if (size == 4)
d6ab8113 6373 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6374 else if (size == 8)
6375 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6376 i.op[n].imms->X_add_number += add;
29b0f896 6377 }
29b0f896
AM		 6378 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6379 i.op[n].imms, 0, reloc_type);
6380 }
6381 }
6382 }
252b5132
RH		 6383}
6384\f
d182319b
JB		 6385/* x86_cons_fix_new is called via the expression parsing code when a
6386 reloc is needed. We use this hook to get the correct .got reloc. */
6387static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6388static int cons_sign = -1;
6389
6390void
e3bb37b5 6391x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6392 expressionS *exp)
d182319b
JB		 6393{
6394 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6395
6396 got_reloc = NO_RELOC;
6397
6398#ifdef TE_PE
6399 if (exp->X_op == O_secrel)
6400 {
6401 exp->X_op = O_symbol;
6402 r = BFD_RELOC_32_SECREL;
6403 }
6404#endif
6405
6406 fix_new_exp (frag, off, len, exp, 0, r);
6407}
6408
718ddfc0
JB		 6409#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6410# define lex_got(reloc, adjust, types) NULL
6411#else
f3c180ae
AM		 6412/* Parse operands of the form
6413 <symbol>@GOTOFF+<nnn>
6414 and similar .plt or .got references.
6415
6416 If we find one, set up the correct relocation in RELOC and copy the
6417 input string, minus the `@GOTOFF' into a malloc'd buffer for
6418 parsing by the calling routine. Return this buffer, and if ADJUST
6419 is non-null set it to the length of the string we removed from the
6420 input line. Otherwise return NULL. */
6421static char *
91d6fa6a 6422lex_got (enum bfd_reloc_code_real *rel,
64e74474 6423 int *adjust,
40fb9820 6424 i386_operand_type *types)
f3c180ae 6425{
7b81dfbb
AJ		 6426 /* Some of the relocations depend on the size of what field is to
6427 be relocated. But in our callers i386_immediate and i386_displacement
6428 we don't yet know the operand size (this will be set by insn
6429 matching). Hence we record the word32 relocation here,
6430 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6431 static const struct {
6432 const char *str;
cff8d58a 6433 int len;
4fa24527 6434 const enum bfd_reloc_code_real rel[2];
40fb9820 6435 const i386_operand_type types64;
f3c180ae 6436 } gotrel[] = {
cff8d58a
L		 6437 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6438 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6439 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6440 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6441 BFD_RELOC_X86_64_PLT32 },
40fb9820 6442 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6443 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6444 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6445 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6446 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6447 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6448 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6449 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6450 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6451 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6452 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6453 BFD_RELOC_X86_64_TLSGD },
40fb9820 6454 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6455 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6456 _dummy_first_bfd_reloc_code_real },
40fb9820 6457 OPERAND_TYPE_NONE },
cff8d58a
L		 6458 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6459 BFD_RELOC_X86_64_TLSLD },
40fb9820 6460 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6461 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6462 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6463 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6464 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6465 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6466 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6467 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6468 _dummy_first_bfd_reloc_code_real },
40fb9820 6469 OPERAND_TYPE_NONE },
cff8d58a
L		 6470 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6471 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6472 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6473 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6474 _dummy_first_bfd_reloc_code_real },
40fb9820 6475 OPERAND_TYPE_NONE },
cff8d58a
L		 6476 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6477 _dummy_first_bfd_reloc_code_real },
40fb9820 6478 OPERAND_TYPE_NONE },
cff8d58a
L		 6479 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6480 BFD_RELOC_X86_64_GOT32 },
40fb9820 6481 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6482 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6483 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6484 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6485 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6486 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6487 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6488 };
6489 char *cp;
6490 unsigned int j;
6491
718ddfc0
JB		 6492 if (!IS_ELF)
6493 return NULL;
6494
f3c180ae 6495 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6496 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6497 return NULL;
6498
47465058 6499 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6500 {
cff8d58a 6501 int len = gotrel[j].len;
28f81592 6502 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6503 {
4fa24527 6504 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6505 {
28f81592
AM		 6506 int first, second;
6507 char *tmpbuf, *past_reloc;
f3c180ae 6508
91d6fa6a 6509 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6510 if (adjust)
6511 *adjust = len;
f3c180ae 6512
3956db08
JB		 6513 if (types)
6514 {
6515 if (flag_code != CODE_64BIT)
40fb9820
L		 6516 {
6517 types->bitfield.imm32 = 1;
6518 types->bitfield.disp32 = 1;
6519 }
3956db08
JB		 6520 else
6521 *types = gotrel[j].types64;
6522 }
6523
f3c180ae
AM		 6524 if (GOT_symbol == NULL)
6525 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6526
28f81592 6527 /* The length of the first part of our input line. */
f3c180ae 6528 first = cp - input_line_pointer;
28f81592
AM		 6529
6530 /* The second part goes from after the reloc token until
67c11a9b 6531 (and including) an end_of_line char or comma. */
28f81592 6532 past_reloc = cp + 1 + len;
67c11a9b
AM		 6533 cp = past_reloc;
6534 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6535 ++cp;
6536 second = cp + 1 - past_reloc;
28f81592
AM		 6537
6538 /* Allocate and copy string. The trailing NUL shouldn't
6539 be necessary, but be safe. */
1e9cc1c2 6540 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6541 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6542 if (second != 0 && *past_reloc != ' ')
6543 /* Replace the relocation token with ' ', so that
6544 errors like foo@GOTOFF1 will be detected. */
6545 tmpbuf[first++] = ' ';
6546 memcpy (tmpbuf + first, past_reloc, second);
6547 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6548 return tmpbuf;
6549 }
6550
4fa24527
JB		 6551 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6552 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6553 return NULL;
6554 }
6555 }
6556
6557 /* Might be a symbol version string. Don't as_bad here. */
6558 return NULL;
6559}
6560
f3c180ae 6561void
e3bb37b5 6562x86_cons (expressionS *exp, int size)
f3c180ae 6563{
ee86248c
JB		 6564 intel_syntax = -intel_syntax;
6565
3c7b9c2c 6566 exp->X_md = 0;
4fa24527 6567 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6568 {
6569 /* Handle @GOTOFF and the like in an expression. */
6570 char *save;
6571 char *gotfree_input_line;
6572 int adjust;
6573
6574 save = input_line_pointer;
3956db08 6575 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6576 if (gotfree_input_line)
6577 input_line_pointer = gotfree_input_line;
6578
6579 expression (exp);
6580
6581 if (gotfree_input_line)
6582 {
6583 /* expression () has merrily parsed up to the end of line,
6584 or a comma - in the wrong buffer. Transfer how far
6585 input_line_pointer has moved to the right buffer. */
6586 input_line_pointer = (save
6587 + (input_line_pointer - gotfree_input_line)
6588 + adjust);
6589 free (gotfree_input_line);
3992d3b7
AM		 6590 if (exp->X_op == O_constant
6591 || exp->X_op == O_absent
6592 || exp->X_op == O_illegal
0398aac5 6593 || exp->X_op == O_register
3992d3b7
AM		 6594 || exp->X_op == O_big)
6595 {
6596 char c = *input_line_pointer;
6597 *input_line_pointer = 0;
6598 as_bad (_("missing or invalid expression `%s'"), save);
6599 *input_line_pointer = c;
6600 }
f3c180ae
AM		 6601 }
6602 }
6603 else
6604 expression (exp);
ee86248c
JB		 6605
6606 intel_syntax = -intel_syntax;
6607
6608 if (intel_syntax)
6609 i386_intel_simplify (exp);
f3c180ae
AM		 6610}
6611#endif
6612
9f32dd5b
L		 6613static void
6614signed_cons (int size)
6482c264 6615{
d182319b
JB		 6616 if (flag_code == CODE_64BIT)
6617 cons_sign = 1;
6618 cons (size);
6619 cons_sign = -1;
6482c264
NC		 6620}
6621
d182319b 6622#ifdef TE_PE
6482c264
NC		 6623static void
6624pe_directive_secrel (dummy)
6625 int dummy ATTRIBUTE_UNUSED;
6626{
6627 expressionS exp;
6628
6629 do
6630 {
6631 expression (&exp);
6632 if (exp.X_op == O_symbol)
6633 exp.X_op = O_secrel;
6634
6635 emit_expr (&exp, 4);
6636 }
6637 while (*input_line_pointer++ == ',');
6638
6639 input_line_pointer--;
6640 demand_empty_rest_of_line ();
6641}
6482c264
NC		 6642#endif
6643
252b5132 6644static int
70e41ade 6645i386_immediate (char *imm_start)
252b5132
RH		 6646{
6647 char *save_input_line_pointer;
f3c180ae 6648 char *gotfree_input_line;
252b5132 6649 segT exp_seg = 0;
47926f60 6650 expressionS *exp;
40fb9820
L		 6651 i386_operand_type types;
6652
0dfbf9d7 6653 operand_type_set (&types, ~0);
252b5132
RH		 6654
6655 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6656 {
31b2323c
L		 6657 as_bad (_("at most %d immediate operands are allowed"),
6658 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6659 return 0;
6660 }
6661
6662 exp = &im_expressions[i.imm_operands++];
520dc8e8 6663 i.op[this_operand].imms = exp;
252b5132
RH		 6664
6665 if (is_space_char (*imm_start))
6666 ++imm_start;
6667
6668 save_input_line_pointer = input_line_pointer;
6669 input_line_pointer = imm_start;
6670
3956db08 6671 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6672 if (gotfree_input_line)
6673 input_line_pointer = gotfree_input_line;
252b5132
RH		 6674
6675 exp_seg = expression (exp);
6676
83183c0c 6677 SKIP_WHITESPACE ();
252b5132 6678 if (*input_line_pointer)
f3c180ae 6679 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6680
6681 input_line_pointer = save_input_line_pointer;
f3c180ae 6682 if (gotfree_input_line)
ee86248c
JB		 6683 {
6684 free (gotfree_input_line);
6685
6686 if (exp->X_op == O_constant || exp->X_op == O_register)
6687 exp->X_op = O_illegal;
6688 }
6689
6690 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6691}
252b5132 6692
ee86248c
JB		 6693static int
6694i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6695 i386_operand_type types, const char *imm_start)
6696{
6697 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6698 {
313c53d1
L		 6699 if (imm_start)
6700 as_bad (_("missing or invalid immediate expression `%s'"),
6701 imm_start);
3992d3b7 6702 return 0;
252b5132 6703 }
3e73aa7c 6704 else if (exp->X_op == O_constant)
252b5132 6705 {
47926f60 6706 /* Size it properly later. */
40fb9820 6707 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6708 /* If not 64bit, sign extend val. */
6709 if (flag_code != CODE_64BIT
4eed87de
AM		 6710 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6711 exp->X_add_number
6712 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6713 }
4c63da97 6714#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6715 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6716 && exp_seg != absolute_section
47926f60 6717 && exp_seg != text_section
24eab124
AM		 6718 && exp_seg != data_section
6719 && exp_seg != bss_section
6720 && exp_seg != undefined_section
f86103b7 6721 && !bfd_is_com_section (exp_seg))
252b5132 6722 {
d0b47220 6723 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6724 return 0;
6725 }
6726#endif
bb8f5920
L		 6727 else if (!intel_syntax && exp->X_op == O_register)
6728 {
313c53d1
L		 6729 if (imm_start)
6730 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6731 return 0;
6732 }
252b5132
RH		 6733 else
6734 {
6735 /* This is an address. The size of the address will be
24eab124 6736 determined later, depending on destination register,
3e73aa7c 6737 suffix, or the default for the section. */
40fb9820
L		 6738 i.types[this_operand].bitfield.imm8 = 1;
6739 i.types[this_operand].bitfield.imm16 = 1;
6740 i.types[this_operand].bitfield.imm32 = 1;
6741 i.types[this_operand].bitfield.imm32s = 1;
6742 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6743 i.types[this_operand] = operand_type_and (i.types[this_operand],
6744 types);
252b5132
RH		 6745 }
6746
6747 return 1;
6748}
6749
551c1ca1 6750static char *
e3bb37b5 6751i386_scale (char *scale)
252b5132 6752{
551c1ca1
AM		 6753 offsetT val;
6754 char *save = input_line_pointer;
252b5132 6755
551c1ca1
AM		 6756 input_line_pointer = scale;
6757 val = get_absolute_expression ();
6758
6759 switch (val)
252b5132 6760 {
551c1ca1 6761 case 1:
252b5132
RH		 6762 i.log2_scale_factor = 0;
6763 break;
551c1ca1 6764 case 2:
252b5132
RH		 6765 i.log2_scale_factor = 1;
6766 break;
551c1ca1 6767 case 4:
252b5132
RH		 6768 i.log2_scale_factor = 2;
6769 break;
551c1ca1 6770 case 8:
252b5132
RH		 6771 i.log2_scale_factor = 3;
6772 break;
6773 default:
a724f0f4
JB		 6774 {
6775 char sep = *input_line_pointer;
6776
6777 *input_line_pointer = '\0';
6778 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6779 scale);
6780 *input_line_pointer = sep;
6781 input_line_pointer = save;
6782 return NULL;
6783 }
252b5132 6784 }
29b0f896 6785 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6786 {
6787 as_warn (_("scale factor of %d without an index register"),
24eab124 6788 1 << i.log2_scale_factor);
252b5132 6789 i.log2_scale_factor = 0;
252b5132 6790 }
551c1ca1
AM		 6791 scale = input_line_pointer;
6792 input_line_pointer = save;
6793 return scale;
252b5132
RH		 6794}
6795
252b5132 6796static int
e3bb37b5 6797i386_displacement (char *disp_start, char *disp_end)
252b5132 6798{
29b0f896 6799 expressionS *exp;
252b5132
RH		 6800 segT exp_seg = 0;
6801 char *save_input_line_pointer;
f3c180ae 6802 char *gotfree_input_line;
40fb9820
L		 6803 int override;
6804 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6805 int ret;
252b5132 6806
31b2323c
L		 6807 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6808 {
6809 as_bad (_("at most %d displacement operands are allowed"),
6810 MAX_MEMORY_OPERANDS);
6811 return 0;
6812 }
6813
0dfbf9d7 6814 operand_type_set (&bigdisp, 0);
40fb9820
L		 6815 if ((i.types[this_operand].bitfield.jumpabsolute)
6816 || (!current_templates->start->opcode_modifier.jump
6817 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6818 {
40fb9820 6819 bigdisp.bitfield.disp32 = 1;
e05278af 6820 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6821 if (flag_code == CODE_64BIT)
6822 {
6823 if (!override)
6824 {
6825 bigdisp.bitfield.disp32s = 1;
6826 bigdisp.bitfield.disp64 = 1;
6827 }
6828 }
6829 else if ((flag_code == CODE_16BIT) ^ override)
6830 {
6831 bigdisp.bitfield.disp32 = 0;
6832 bigdisp.bitfield.disp16 = 1;
6833 }
e05278af
JB		 6834 }
6835 else
6836 {
6837 /* For PC-relative branches, the width of the displacement
6838 is dependent upon data size, not address size. */
e05278af 6839 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6840 if (flag_code == CODE_64BIT)
6841 {
6842 if (override || i.suffix == WORD_MNEM_SUFFIX)
6843 bigdisp.bitfield.disp16 = 1;
6844 else
6845 {
6846 bigdisp.bitfield.disp32 = 1;
6847 bigdisp.bitfield.disp32s = 1;
6848 }
6849 }
6850 else
e05278af
JB		 6851 {
6852 if (!override)
6853 override = (i.suffix == (flag_code != CODE_16BIT
6854 ? WORD_MNEM_SUFFIX
6855 : LONG_MNEM_SUFFIX));
40fb9820
L		 6856 bigdisp.bitfield.disp32 = 1;
6857 if ((flag_code == CODE_16BIT) ^ override)
6858 {
6859 bigdisp.bitfield.disp32 = 0;
6860 bigdisp.bitfield.disp16 = 1;
6861 }
e05278af 6862 }
e05278af 6863 }
c6fb90c8
L		 6864 i.types[this_operand] = operand_type_or (i.types[this_operand],
6865 bigdisp);
252b5132
RH		 6866
6867 exp = &disp_expressions[i.disp_operands];
520dc8e8 6868 i.op[this_operand].disps = exp;
252b5132
RH		 6869 i.disp_operands++;
6870 save_input_line_pointer = input_line_pointer;
6871 input_line_pointer = disp_start;
6872 END_STRING_AND_SAVE (disp_end);
6873
6874#ifndef GCC_ASM_O_HACK
6875#define GCC_ASM_O_HACK 0
6876#endif
6877#if GCC_ASM_O_HACK
6878 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6879 if (i.types[this_operand].bitfield.baseIndex
24eab124 6880 && displacement_string_end[-1] == '+')
252b5132
RH		 6881 {
6882 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6883 constraint within gcc asm statements.
6884 For instance:
6885
6886 #define _set_tssldt_desc(n,addr,limit,type) \
6887 __asm__ __volatile__ ( \
6888 "movw %w2,%0\n\t" \
6889 "movw %w1,2+%0\n\t" \
6890 "rorl $16,%1\n\t" \
6891 "movb %b1,4+%0\n\t" \
6892 "movb %4,5+%0\n\t" \
6893 "movb $0,6+%0\n\t" \
6894 "movb %h1,7+%0\n\t" \
6895 "rorl $16,%1" \
6896 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6897
6898 This works great except that the output assembler ends
6899 up looking a bit weird if it turns out that there is
6900 no offset. You end up producing code that looks like:
6901
6902 #APP
6903 movw $235,(%eax)
6904 movw %dx,2+(%eax)
6905 rorl $16,%edx
6906 movb %dl,4+(%eax)
6907 movb $137,5+(%eax)
6908 movb $0,6+(%eax)
6909 movb %dh,7+(%eax)
6910 rorl $16,%edx
6911 #NO_APP
6912
47926f60 6913 So here we provide the missing zero. */
24eab124
AM		 6914
6915 *displacement_string_end = '0';
252b5132
RH		 6916 }
6917#endif
3956db08 6918 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6919 if (gotfree_input_line)
6920 input_line_pointer = gotfree_input_line;
252b5132 6921
24eab124 6922 exp_seg = expression (exp);
252b5132 6923
636c26b0
AM		 6924 SKIP_WHITESPACE ();
6925 if (*input_line_pointer)
6926 as_bad (_("junk `%s' after expression"), input_line_pointer);
6927#if GCC_ASM_O_HACK
6928 RESTORE_END_STRING (disp_end + 1);
6929#endif
636c26b0 6930 input_line_pointer = save_input_line_pointer;
636c26b0 6931 if (gotfree_input_line)
ee86248c
JB		 6932 {
6933 free (gotfree_input_line);
6934
6935 if (exp->X_op == O_constant || exp->X_op == O_register)
6936 exp->X_op = O_illegal;
6937 }
6938
6939 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6940
6941 RESTORE_END_STRING (disp_end);
6942
6943 return ret;
6944}
6945
6946static int
6947i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6948 i386_operand_type types, const char *disp_start)
6949{
6950 i386_operand_type bigdisp;
6951 int ret = 1;
636c26b0 6952
24eab124
AM		 6953 /* We do this to make sure that the section symbol is in
6954 the symbol table. We will ultimately change the relocation
47926f60 6955 to be relative to the beginning of the section. */
1ae12ab7 6956 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6957 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6958 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6959 {
636c26b0 6960 if (exp->X_op != O_symbol)
3992d3b7 6961 goto inv_disp;
636c26b0 6962
e5cb08ac 6963 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 6964 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
6965 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 6966 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6967 exp->X_op = O_subtract;
6968 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6969 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6970 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6971 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6972 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6973 else
29b0f896 6974 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6975 }
252b5132 6976
3992d3b7
AM		 6977 else if (exp->X_op == O_absent
6978 || exp->X_op == O_illegal
ee86248c 6979 || exp->X_op == O_big)
2daf4fd8 6980 {
3992d3b7
AM		 6981 inv_disp:
6982 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6983 disp_start);
3992d3b7 6984 ret = 0;
2daf4fd8
AM		 6985 }
6986
0e1147d9
L		 6987 else if (flag_code == CODE_64BIT
6988 && !i.prefix[ADDR_PREFIX]
6989 && exp->X_op == O_constant)
6990 {
6991 /* Since displacement is signed extended to 64bit, don't allow
6992 disp32 and turn off disp32s if they are out of range. */
6993 i.types[this_operand].bitfield.disp32 = 0;
6994 if (!fits_in_signed_long (exp->X_add_number))
6995 {
6996 i.types[this_operand].bitfield.disp32s = 0;
6997 if (i.types[this_operand].bitfield.baseindex)
6998 {
6999 as_bad (_("0x%lx out range of signed 32bit displacement"),
7000 (long) exp->X_add_number);
7001 ret = 0;
7002 }
7003 }
7004 }
7005
4c63da97 7006#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7007 else if (exp->X_op != O_constant
7008 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7009 && exp_seg != absolute_section
7010 && exp_seg != text_section
7011 && exp_seg != data_section
7012 && exp_seg != bss_section
7013 && exp_seg != undefined_section
7014 && !bfd_is_com_section (exp_seg))
24eab124 7015 {
d0b47220 7016 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7017 ret = 0;
24eab124 7018 }
252b5132 7019#endif
3956db08 7020
40fb9820
L		 7021 /* Check if this is a displacement only operand. */
7022 bigdisp = i.types[this_operand];
7023 bigdisp.bitfield.disp8 = 0;
7024 bigdisp.bitfield.disp16 = 0;
7025 bigdisp.bitfield.disp32 = 0;
7026 bigdisp.bitfield.disp32s = 0;
7027 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7028 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7029 i.types[this_operand] = operand_type_and (i.types[this_operand],
7030 types);
3956db08 7031
3992d3b7 7032 return ret;
252b5132
RH		 7033}
7034
eecb386c 7035/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7036 Return 1 on success, 0 on a failure. */
7037
252b5132 7038static int
e3bb37b5 7039i386_index_check (const char *operand_string)
252b5132 7040{
3e73aa7c 7041 int ok;
fc0763e6 7042 const char *kind = "base/index";
24eab124 7043#if INFER_ADDR_PREFIX
eecb386c
AM		 7044 int fudged = 0;
7045
24eab124
AM		 7046 tryprefix:
7047#endif
3e73aa7c 7048 ok = 1;
fc0763e6
JB		 7049 if (current_templates->start->opcode_modifier.isstring
7050 && !current_templates->start->opcode_modifier.immext
7051 && (current_templates->end[-1].opcode_modifier.isstring
7052 || i.mem_operands))
7053 {
7054 /* Memory operands of string insns are special in that they only allow
7055 a single register (rDI, rSI, or rBX) as their memory address. */
7056 unsigned int expected;
7057
7058 kind = "string address";
7059
7060 if (current_templates->start->opcode_modifier.w)
7061 {
7062 i386_operand_type type = current_templates->end[-1].operand_types[0];
7063
7064 if (!type.bitfield.baseindex
7065 || ((!i.mem_operands != !intel_syntax)
7066 && current_templates->end[-1].operand_types[1]
7067 .bitfield.baseindex))
7068 type = current_templates->end[-1].operand_types[1];
7069 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7070 }
7071 else
7072 expected = 3 /* rBX */;
7073
7074 if (!i.base_reg || i.index_reg
7075 || operand_type_check (i.types[this_operand], disp))
7076 ok = -1;
7077 else if (!(flag_code == CODE_64BIT
7078 ? i.prefix[ADDR_PREFIX]
7079 ? i.base_reg->reg_type.bitfield.reg32
7080 : i.base_reg->reg_type.bitfield.reg64
7081 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7082 ? i.base_reg->reg_type.bitfield.reg32
7083 : i.base_reg->reg_type.bitfield.reg16))
7084 ok = 0;
7085 else if (i.base_reg->reg_num != expected)
7086 ok = -1;
7087
7088 if (ok < 0)
7089 {
7090 unsigned int j;
7091
7092 for (j = 0; j < i386_regtab_size; ++j)
7093 if ((flag_code == CODE_64BIT
7094 ? i.prefix[ADDR_PREFIX]
7095 ? i386_regtab[j].reg_type.bitfield.reg32
7096 : i386_regtab[j].reg_type.bitfield.reg64
7097 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7098 ? i386_regtab[j].reg_type.bitfield.reg32
7099 : i386_regtab[j].reg_type.bitfield.reg16)
7100 && i386_regtab[j].reg_num == expected)
7101 break;
9c2799c2 7102 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7103 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7104 operand_string,
7105 intel_syntax ? '[' : '(',
7106 register_prefix,
7107 i386_regtab[j].reg_name,
7108 intel_syntax ? ']' : ')');
7109 ok = 1;
7110 }
7111 }
7112 else if (flag_code == CODE_64BIT)
64e74474 7113 {
64e74474 7114 if ((i.base_reg
40fb9820
L		 7115 && ((i.prefix[ADDR_PREFIX] == 0
7116 && !i.base_reg->reg_type.bitfield.reg64)
7117 || (i.prefix[ADDR_PREFIX]
7118 && !i.base_reg->reg_type.bitfield.reg32))
7119 && (i.index_reg
9a04903e
JB		 7120 || i.base_reg->reg_num !=
7121 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7122 || (i.index_reg
40fb9820
L		 7123 && (!i.index_reg->reg_type.bitfield.baseindex
7124 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7125 && i.index_reg->reg_num != RegRiz
7126 && !i.index_reg->reg_type.bitfield.reg64
7127 )
40fb9820 7128 || (i.prefix[ADDR_PREFIX]
db51cc60 7129 && i.index_reg->reg_num != RegEiz
40fb9820 7130 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7131 ok = 0;
3e73aa7c
JH		 7132 }
7133 else
7134 {
7135 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7136 {
7137 /* 16bit checks. */
7138 if ((i.base_reg
40fb9820
L		 7139 && (!i.base_reg->reg_type.bitfield.reg16
7140 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7141 || (i.index_reg
40fb9820
L		 7142 && (!i.index_reg->reg_type.bitfield.reg16
7143 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7144 || !(i.base_reg
7145 && i.base_reg->reg_num < 6
7146 && i.index_reg->reg_num >= 6
7147 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7148 ok = 0;
7149 }
7150 else
e5cb08ac 7151 {
3e73aa7c
JH		 7152 /* 32bit checks. */
7153 if ((i.base_reg
40fb9820 7154 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7155 || (i.index_reg
db51cc60
L		 7156 && ((!i.index_reg->reg_type.bitfield.reg32
7157 && i.index_reg->reg_num != RegEiz)
40fb9820 7158 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7159 ok = 0;
3e73aa7c
JH		 7160 }
7161 }
7162 if (!ok)
24eab124
AM		 7163 {
7164#if INFER_ADDR_PREFIX
fc0763e6 7165 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7166 {
7167 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7168 i.prefixes += 1;
b23bac36
AM		 7169 /* Change the size of any displacement too. At most one of
7170 Disp16 or Disp32 is set.
7171 FIXME. There doesn't seem to be any real need for separate
7172 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7173 Removing them would probably clean up the code quite a lot. */
4eed87de 7174 if (flag_code != CODE_64BIT
40fb9820
L		 7175 && (i.types[this_operand].bitfield.disp16
7176 || i.types[this_operand].bitfield.disp32))
7177 i.types[this_operand]
c6fb90c8 7178 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7179 fudged = 1;
24eab124
AM		 7180 goto tryprefix;
7181 }
eecb386c 7182 if (fudged)
fc0763e6
JB		 7183 as_bad (_("`%s' is not a valid %s expression"),
7184 operand_string,
7185 kind);
eecb386c 7186 else
c388dee8 7187#endif
fc0763e6 7188 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7189 operand_string,
fc0763e6
JB		 7190 flag_code_names[i.prefix[ADDR_PREFIX]
7191 ? flag_code == CODE_32BIT
7192 ? CODE_16BIT
7193 : CODE_32BIT
7194 : flag_code],
7195 kind);
24eab124 7196 }
20f0a1fc 7197 return ok;
24eab124 7198}
252b5132 7199
fc0763e6 7200/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7201 on error. */
252b5132 7202
252b5132 7203static int
a7619375 7204i386_att_operand (char *operand_string)
252b5132 7205{
af6bdddf
AM		 7206 const reg_entry *r;
7207 char *end_op;
24eab124 7208 char *op_string = operand_string;
252b5132 7209
24eab124 7210 if (is_space_char (*op_string))
252b5132
RH		 7211 ++op_string;
7212
24eab124 7213 /* We check for an absolute prefix (differentiating,
47926f60 7214 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7215 if (*op_string == ABSOLUTE_PREFIX)
7216 {
7217 ++op_string;
7218 if (is_space_char (*op_string))
7219 ++op_string;
40fb9820 7220 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7221 }
252b5132 7222
47926f60 7223 /* Check if operand is a register. */
4d1bb795 7224 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7225 {
40fb9820
L		 7226 i386_operand_type temp;
7227
24eab124
AM		 7228 /* Check for a segment override by searching for ':' after a
7229 segment register. */
7230 op_string = end_op;
7231 if (is_space_char (*op_string))
7232 ++op_string;
40fb9820
L		 7233 if (*op_string == ':'
7234 && (r->reg_type.bitfield.sreg2
7235 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7236 {
7237 switch (r->reg_num)
7238 {
7239 case 0:
7240 i.seg[i.mem_operands] = &es;
7241 break;
7242 case 1:
7243 i.seg[i.mem_operands] = &cs;
7244 break;
7245 case 2:
7246 i.seg[i.mem_operands] = &ss;
7247 break;
7248 case 3:
7249 i.seg[i.mem_operands] = &ds;
7250 break;
7251 case 4:
7252 i.seg[i.mem_operands] = &fs;
7253 break;
7254 case 5:
7255 i.seg[i.mem_operands] = &gs;
7256 break;
7257 }
252b5132 7258
24eab124 7259 /* Skip the ':' and whitespace. */
252b5132
RH		 7260 ++op_string;
7261 if (is_space_char (*op_string))
24eab124 7262 ++op_string;
252b5132 7263
24eab124
AM		 7264 if (!is_digit_char (*op_string)
7265 && !is_identifier_char (*op_string)
7266 && *op_string != '('
7267 && *op_string != ABSOLUTE_PREFIX)
7268 {
7269 as_bad (_("bad memory operand `%s'"), op_string);
7270 return 0;
7271 }
47926f60 7272 /* Handle case of %es:*foo. */
24eab124
AM		 7273 if (*op_string == ABSOLUTE_PREFIX)
7274 {
7275 ++op_string;
7276 if (is_space_char (*op_string))
7277 ++op_string;
40fb9820 7278 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7279 }
7280 goto do_memory_reference;
7281 }
7282 if (*op_string)
7283 {
d0b47220 7284 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7285 return 0;
7286 }
40fb9820
L		 7287 temp = r->reg_type;
7288 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7289 i.types[this_operand] = operand_type_or (i.types[this_operand],
7290 temp);
7d5e4556 7291 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7292 i.op[this_operand].regs = r;
24eab124
AM		 7293 i.reg_operands++;
7294 }
af6bdddf
AM		 7295 else if (*op_string == REGISTER_PREFIX)
7296 {
7297 as_bad (_("bad register name `%s'"), op_string);
7298 return 0;
7299 }
24eab124 7300 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7301 {
24eab124 7302 ++op_string;
40fb9820 7303 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7304 {
d0b47220 7305 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7306 return 0;
7307 }
7308 if (!i386_immediate (op_string))
7309 return 0;
7310 }
7311 else if (is_digit_char (*op_string)
7312 || is_identifier_char (*op_string)
e5cb08ac 7313 || *op_string == '(')
24eab124 7314 {
47926f60 7315 /* This is a memory reference of some sort. */
af6bdddf 7316 char *base_string;
252b5132 7317
47926f60 7318 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7319 char *displacement_string_start;
7320 char *displacement_string_end;
252b5132 7321
24eab124 7322 do_memory_reference:
24eab124 7323 if ((i.mem_operands == 1
40fb9820 7324 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7325 || i.mem_operands == 2)
7326 {
7327 as_bad (_("too many memory references for `%s'"),
7328 current_templates->start->name);
7329 return 0;
7330 }
252b5132 7331
24eab124
AM		 7332 /* Check for base index form. We detect the base index form by
7333 looking for an ')' at the end of the operand, searching
7334 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7335 after the '('. */
af6bdddf 7336 base_string = op_string + strlen (op_string);
c3332e24 7337
af6bdddf
AM		 7338 --base_string;
7339 if (is_space_char (*base_string))
7340 --base_string;
252b5132 7341
47926f60 7342 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7343 displacement_string_start = op_string;
7344 displacement_string_end = base_string + 1;
252b5132 7345
24eab124
AM		 7346 if (*base_string == ')')
7347 {
af6bdddf 7348 char *temp_string;
24eab124
AM		 7349 unsigned int parens_balanced = 1;
7350 /* We've already checked that the number of left & right ()'s are
47926f60 7351 equal, so this loop will not be infinite. */
24eab124
AM		 7352 do
7353 {
7354 base_string--;
7355 if (*base_string == ')')
7356 parens_balanced++;
7357 if (*base_string == '(')
7358 parens_balanced--;
7359 }
7360 while (parens_balanced);
c3332e24 7361
af6bdddf 7362 temp_string = base_string;
c3332e24 7363
24eab124 7364 /* Skip past '(' and whitespace. */
252b5132
RH		 7365 ++base_string;
7366 if (is_space_char (*base_string))
24eab124 7367 ++base_string;
252b5132 7368
af6bdddf 7369 if (*base_string == ','
4eed87de
AM		 7370 || ((i.base_reg = parse_register (base_string, &end_op))
7371 != NULL))
252b5132 7372 {
af6bdddf 7373 displacement_string_end = temp_string;
252b5132 7374
40fb9820 7375 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7376
af6bdddf 7377 if (i.base_reg)
24eab124 7378 {
24eab124
AM		 7379 base_string = end_op;
7380 if (is_space_char (*base_string))
7381 ++base_string;
af6bdddf
AM		 7382 }
7383
7384 /* There may be an index reg or scale factor here. */
7385 if (*base_string == ',')
7386 {
7387 ++base_string;
7388 if (is_space_char (*base_string))
7389 ++base_string;
7390
4eed87de
AM		 7391 if ((i.index_reg = parse_register (base_string, &end_op))
7392 != NULL)
24eab124 7393 {
af6bdddf 7394 base_string = end_op;
24eab124
AM		 7395 if (is_space_char (*base_string))
7396 ++base_string;
af6bdddf
AM		 7397 if (*base_string == ',')
7398 {
7399 ++base_string;
7400 if (is_space_char (*base_string))
7401 ++base_string;
7402 }
e5cb08ac 7403 else if (*base_string != ')')
af6bdddf 7404 {
4eed87de
AM		 7405 as_bad (_("expecting `,' or `)' "
7406 "after index register in `%s'"),
af6bdddf
AM		 7407 operand_string);
7408 return 0;
7409 }
24eab124 7410 }
af6bdddf 7411 else if (*base_string == REGISTER_PREFIX)
24eab124 7412 {
af6bdddf 7413 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7414 return 0;
7415 }
252b5132 7416
47926f60 7417 /* Check for scale factor. */
551c1ca1 7418 if (*base_string != ')')
af6bdddf 7419 {
551c1ca1
AM		 7420 char *end_scale = i386_scale (base_string);
7421
7422 if (!end_scale)
af6bdddf 7423 return 0;
24eab124 7424
551c1ca1 7425 base_string = end_scale;
af6bdddf
AM		 7426 if (is_space_char (*base_string))
7427 ++base_string;
7428 if (*base_string != ')')
7429 {
4eed87de
AM		 7430 as_bad (_("expecting `)' "
7431 "after scale factor in `%s'"),
af6bdddf
AM		 7432 operand_string);
7433 return 0;
7434 }
7435 }
7436 else if (!i.index_reg)
24eab124 7437 {
4eed87de
AM		 7438 as_bad (_("expecting index register or scale factor "
7439 "after `,'; got '%c'"),
af6bdddf 7440 *base_string);
24eab124
AM		 7441 return 0;
7442 }
7443 }
af6bdddf 7444 else if (*base_string != ')')
24eab124 7445 {
4eed87de
AM		 7446 as_bad (_("expecting `,' or `)' "
7447 "after base register in `%s'"),
af6bdddf 7448 operand_string);
24eab124
AM		 7449 return 0;
7450 }
c3332e24 7451 }
af6bdddf 7452 else if (*base_string == REGISTER_PREFIX)
c3332e24 7453 {
af6bdddf 7454 as_bad (_("bad register name `%s'"), base_string);
24eab124 7455 return 0;
c3332e24 7456 }
24eab124
AM		 7457 }
7458
7459 /* If there's an expression beginning the operand, parse it,
7460 assuming displacement_string_start and
7461 displacement_string_end are meaningful. */
7462 if (displacement_string_start != displacement_string_end)
7463 {
7464 if (!i386_displacement (displacement_string_start,
7465 displacement_string_end))
7466 return 0;
7467 }
7468
7469 /* Special case for (%dx) while doing input/output op. */
7470 if (i.base_reg
0dfbf9d7
L		 7471 && operand_type_equal (&i.base_reg->reg_type,
7472 &reg16_inoutportreg)
24eab124
AM		 7473 && i.index_reg == 0
7474 && i.log2_scale_factor == 0
7475 && i.seg[i.mem_operands] == 0
40fb9820 7476 && !operand_type_check (i.types[this_operand], disp))
24eab124 7477 {
65da13b5 7478 i.types[this_operand] = inoutportreg;
24eab124
AM		 7479 return 1;
7480 }
7481
eecb386c
AM		 7482 if (i386_index_check (operand_string) == 0)
7483 return 0;
5c07affc 7484 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7485 i.mem_operands++;
7486 }
7487 else
ce8a8b2f
AM		 7488 {
7489 /* It's not a memory operand; argh! */
24eab124
AM		 7490 as_bad (_("invalid char %s beginning operand %d `%s'"),
7491 output_invalid (*op_string),
7492 this_operand + 1,
7493 op_string);
7494 return 0;
7495 }
47926f60 7496 return 1; /* Normal return. */
252b5132
RH		 7497}
7498\f
ee7fcc42
AM		 7499/* md_estimate_size_before_relax()
7500
7501 Called just before relax() for rs_machine_dependent frags. The x86
7502 assembler uses these frags to handle variable size jump
7503 instructions.
7504
7505 Any symbol that is now undefined will not become defined.
7506 Return the correct fr_subtype in the frag.
7507 Return the initial "guess for variable size of frag" to caller.
7508 The guess is actually the growth beyond the fixed part. Whatever
7509 we do to grow the fixed or variable part contributes to our
7510 returned value. */
7511
252b5132
RH		 7512int
7513md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7514 fragS *fragP;
7515 segT segment;
252b5132 7516{
252b5132 7517 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7518 check for un-relaxable symbols. On an ELF system, we can't relax
7519 an externally visible symbol, because it may be overridden by a
7520 shared library. */
7521 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7522#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7523 || (IS_ELF
31312f95 7524 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7525 || S_IS_WEAK (fragP->fr_symbol)
7526 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7527 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7528#endif
7529#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7530 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7531 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7532#endif
7533 )
252b5132 7534 {
b98ef147
AM		 7535 /* Symbol is undefined in this segment, or we need to keep a
7536 reloc so that weak symbols can be overridden. */
7537 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7538 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7539 unsigned char *opcode;
7540 int old_fr_fix;
f6af82bd 7541
ee7fcc42 7542 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7543 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7544 else if (size == 2)
f6af82bd
AM		 7545 reloc_type = BFD_RELOC_16_PCREL;
7546 else
7547 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7548
ee7fcc42
AM		 7549 old_fr_fix = fragP->fr_fix;
7550 opcode = (unsigned char *) fragP->fr_opcode;
7551
fddf5b5b 7552 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7553 {
fddf5b5b
AM		 7554 case UNCOND_JUMP:
7555 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7556 opcode[0] = 0xe9;
252b5132 7557 fragP->fr_fix += size;
062cd5e7
AS		 7558 fix_new (fragP, old_fr_fix, size,
7559 fragP->fr_symbol,
7560 fragP->fr_offset, 1,
7561 reloc_type);
252b5132
RH		 7562 break;
7563
fddf5b5b 7564 case COND_JUMP86:
412167cb
AM		 7565 if (size == 2
7566 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7567 {
7568 /* Negate the condition, and branch past an
7569 unconditional jump. */
7570 opcode[0] ^= 1;
7571 opcode[1] = 3;
7572 /* Insert an unconditional jump. */
7573 opcode[2] = 0xe9;
7574 /* We added two extra opcode bytes, and have a two byte
7575 offset. */
7576 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7577 fix_new (fragP, old_fr_fix + 2, 2,
7578 fragP->fr_symbol,
7579 fragP->fr_offset, 1,
7580 reloc_type);
fddf5b5b
AM		 7581 break;
7582 }
7583 /* Fall through. */
7584
7585 case COND_JUMP:
412167cb
AM		 7586 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7587 {
3e02c1cc
AM		 7588 fixS *fixP;
7589
412167cb 7590 fragP->fr_fix += 1;
3e02c1cc
AM		 7591 fixP = fix_new (fragP, old_fr_fix, 1,
7592 fragP->fr_symbol,
7593 fragP->fr_offset, 1,
7594 BFD_RELOC_8_PCREL);
7595 fixP->fx_signed = 1;
412167cb
AM		 7596 break;
7597 }
93c2a809 7598
24eab124 7599 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7600 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7601 opcode[1] = opcode[0] + 0x10;
f6af82bd 7602 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7603 /* We've added an opcode byte. */
7604 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7605 fix_new (fragP, old_fr_fix + 1, size,
7606 fragP->fr_symbol,
7607 fragP->fr_offset, 1,
7608 reloc_type);
252b5132 7609 break;
fddf5b5b
AM		 7610
7611 default:
7612 BAD_CASE (fragP->fr_subtype);
7613 break;
252b5132
RH		 7614 }
7615 frag_wane (fragP);
ee7fcc42 7616 return fragP->fr_fix - old_fr_fix;
252b5132 7617 }
93c2a809 7618
93c2a809
AM		 7619 /* Guess size depending on current relax state. Initially the relax
7620 state will correspond to a short jump and we return 1, because
7621 the variable part of the frag (the branch offset) is one byte
7622 long. However, we can relax a section more than once and in that
7623 case we must either set fr_subtype back to the unrelaxed state,
7624 or return the value for the appropriate branch. */
7625 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7626}
7627
47926f60
KH		 7628/* Called after relax() is finished.
7629
7630 In: Address of frag.
7631 fr_type == rs_machine_dependent.
7632 fr_subtype is what the address relaxed to.
7633
7634 Out: Any fixSs and constants are set up.
7635 Caller will turn frag into a ".space 0". */
7636
252b5132
RH		 7637void
7638md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7639 bfd *abfd ATTRIBUTE_UNUSED;
7640 segT sec ATTRIBUTE_UNUSED;
29b0f896 7641 fragS *fragP;
252b5132 7642{
29b0f896 7643 unsigned char *opcode;
252b5132 7644 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7645 offsetT target_address;
7646 offsetT opcode_address;
252b5132 7647 unsigned int extension = 0;
847f7ad4 7648 offsetT displacement_from_opcode_start;
252b5132
RH		 7649
7650 opcode = (unsigned char *) fragP->fr_opcode;
7651
47926f60 7652 /* Address we want to reach in file space. */
252b5132 7653 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7654
47926f60 7655 /* Address opcode resides at in file space. */
252b5132
RH		 7656 opcode_address = fragP->fr_address + fragP->fr_fix;
7657
47926f60 7658 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7659 displacement_from_opcode_start = target_address - opcode_address;
7660
fddf5b5b 7661 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7662 {
47926f60
KH		 7663 /* Don't have to change opcode. */
7664 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7665 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7666 }
7667 else
7668 {
7669 if (no_cond_jump_promotion
7670 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7671 as_warn_where (fragP->fr_file, fragP->fr_line,
7672 _("long jump required"));
252b5132 7673
fddf5b5b
AM		 7674 switch (fragP->fr_subtype)
7675 {
7676 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7677 extension = 4; /* 1 opcode + 4 displacement */
7678 opcode[0] = 0xe9;
7679 where_to_put_displacement = &opcode[1];
7680 break;
252b5132 7681
fddf5b5b
AM		 7682 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7683 extension = 2; /* 1 opcode + 2 displacement */
7684 opcode[0] = 0xe9;
7685 where_to_put_displacement = &opcode[1];
7686 break;
252b5132 7687
fddf5b5b
AM		 7688 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7689 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7690 extension = 5; /* 2 opcode + 4 displacement */
7691 opcode[1] = opcode[0] + 0x10;
7692 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7693 where_to_put_displacement = &opcode[2];
7694 break;
252b5132 7695
fddf5b5b
AM		 7696 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7697 extension = 3; /* 2 opcode + 2 displacement */
7698 opcode[1] = opcode[0] + 0x10;
7699 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7700 where_to_put_displacement = &opcode[2];
7701 break;
252b5132 7702
fddf5b5b
AM		 7703 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7704 extension = 4;
7705 opcode[0] ^= 1;
7706 opcode[1] = 3;
7707 opcode[2] = 0xe9;
7708 where_to_put_displacement = &opcode[3];
7709 break;
7710
7711 default:
7712 BAD_CASE (fragP->fr_subtype);
7713 break;
7714 }
252b5132 7715 }
fddf5b5b 7716
7b81dfbb
AJ		 7717 /* If size if less then four we are sure that the operand fits,
7718 but if it's 4, then it could be that the displacement is larger
7719 then -/+ 2GB. */
7720 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7721 && object_64bit
7722 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7723 + ((addressT) 1 << 31))
7724 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7725 {
7726 as_bad_where (fragP->fr_file, fragP->fr_line,
7727 _("jump target out of range"));
7728 /* Make us emit 0. */
7729 displacement_from_opcode_start = extension;
7730 }
47926f60 7731 /* Now put displacement after opcode. */
252b5132
RH		 7732 md_number_to_chars ((char *) where_to_put_displacement,
7733 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7734 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7735 fragP->fr_fix += extension;
7736}
7737\f
252b5132
RH		 7738/* Apply a fixup (fixS) to segment data, once it has been determined
7739 by our caller that we have all the info we need to fix it up.
7740
7741 On the 386, immediates, displacements, and data pointers are all in
7742 the same (little-endian) format, so we don't need to care about which
7743 we are handling. */
7744
94f592af 7745void
55cf6793 7746md_apply_fix (fixP, valP, seg)
47926f60
KH		 7747 /* The fix we're to put in. */
7748 fixS *fixP;
47926f60 7749 /* Pointer to the value of the bits. */
c6682705 7750 valueT *valP;
47926f60
KH		 7751 /* Segment fix is from. */
7752 segT seg ATTRIBUTE_UNUSED;
252b5132 7753{
94f592af 7754 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7755 valueT value = *valP;
252b5132 7756
f86103b7 7757#if !defined (TE_Mach)
93382f6d
AM		 7758 if (fixP->fx_pcrel)
7759 {
7760 switch (fixP->fx_r_type)
7761 {
5865bb77
ILT		 7762 default:
7763 break;
7764
d6ab8113
JB		 7765 case BFD_RELOC_64:
7766 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7767 break;
93382f6d 7768 case BFD_RELOC_32:
ae8887b5 7769 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7770 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7771 break;
7772 case BFD_RELOC_16:
7773 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7774 break;
7775 case BFD_RELOC_8:
7776 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7777 break;
7778 }
7779 }
252b5132 7780
a161fe53 7781 if (fixP->fx_addsy != NULL
31312f95 7782 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7783 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7784 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7785 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7786 && !use_rela_relocations)
252b5132 7787 {
31312f95
AM		 7788 /* This is a hack. There should be a better way to handle this.
7789 This covers for the fact that bfd_install_relocation will
7790 subtract the current location (for partial_inplace, PC relative
7791 relocations); see more below. */
252b5132 7792#ifndef OBJ_AOUT
718ddfc0 7793 if (IS_ELF
252b5132
RH		 7794#ifdef TE_PE
7795 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7796#endif
7797 )
7798 value += fixP->fx_where + fixP->fx_frag->fr_address;
7799#endif
7800#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7801 if (IS_ELF)
252b5132 7802 {
6539b54b 7803 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7804
6539b54b 7805 if ((sym_seg == seg
2f66722d 7806 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7807 && sym_seg != absolute_section))
af65af87 7808 && !generic_force_reloc (fixP))
2f66722d
AM		 7809 {
7810 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7811 bfd_install_relocation subtracts them out again. I think
7812 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7813 it. FIXME. */
7814 value += fixP->fx_where + fixP->fx_frag->fr_address;
7815 }
252b5132
RH		 7816 }
7817#endif
7818#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7819 /* For some reason, the PE format does not store a
7820 section address offset for a PC relative symbol. */
7821 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7822 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7823 value += md_pcrel_from (fixP);
7824#endif
7825 }
fbeb56a4
DK		 7826#if defined (OBJ_COFF) && defined (TE_PE)
7827 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7828 {
7829 value -= S_GET_VALUE (fixP->fx_addsy);
7830 }
7831#endif
252b5132
RH		 7832
7833 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7834 and we must not disappoint it. */
252b5132 7835#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7836 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7837 switch (fixP->fx_r_type)
7838 {
7839 case BFD_RELOC_386_PLT32:
3e73aa7c 7840 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7841 /* Make the jump instruction point to the address of the operand. At
7842 runtime we merely add the offset to the actual PLT entry. */
7843 value = -4;
7844 break;
31312f95 7845
13ae64f3
JJ		 7846 case BFD_RELOC_386_TLS_GD:
7847 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7848 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7849 case BFD_RELOC_386_TLS_IE:
7850 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7851 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7852 case BFD_RELOC_X86_64_TLSGD:
7853 case BFD_RELOC_X86_64_TLSLD:
7854 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7855 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7856 value = 0; /* Fully resolved at runtime. No addend. */
7857 /* Fallthrough */
7858 case BFD_RELOC_386_TLS_LE:
7859 case BFD_RELOC_386_TLS_LDO_32:
7860 case BFD_RELOC_386_TLS_LE_32:
7861 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7862 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7863 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7864 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7865 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7866 break;
7867
67a4f2b7
AO		 7868 case BFD_RELOC_386_TLS_DESC_CALL:
7869 case BFD_RELOC_X86_64_TLSDESC_CALL:
7870 value = 0; /* Fully resolved at runtime. No addend. */
7871 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7872 fixP->fx_done = 0;
7873 return;
7874
00f7efb6
JJ		 7875 case BFD_RELOC_386_GOT32:
7876 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7877 value = 0; /* Fully resolved at runtime. No addend. */
7878 break;
47926f60
KH		 7879
7880 case BFD_RELOC_VTABLE_INHERIT:
7881 case BFD_RELOC_VTABLE_ENTRY:
7882 fixP->fx_done = 0;
94f592af 7883 return;
47926f60
KH		 7884
7885 default:
7886 break;
7887 }
7888#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7889 *valP = value;
f86103b7 7890#endif /* !defined (TE_Mach) */
3e73aa7c 7891
3e73aa7c 7892 /* Are we finished with this relocation now? */
c6682705 7893 if (fixP->fx_addsy == NULL)
3e73aa7c 7894 fixP->fx_done = 1;
fbeb56a4
DK		 7895#if defined (OBJ_COFF) && defined (TE_PE)
7896 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7897 {
7898 fixP->fx_done = 0;
7899 /* Remember value for tc_gen_reloc. */
7900 fixP->fx_addnumber = value;
7901 /* Clear out the frag for now. */
7902 value = 0;
7903 }
7904#endif
3e73aa7c
JH		 7905 else if (use_rela_relocations)
7906 {
7907 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7908 /* Remember value for tc_gen_reloc. */
7909 fixP->fx_addnumber = value;
3e73aa7c
JH		 7910 value = 0;
7911 }
f86103b7 7912
94f592af 7913 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7914}
252b5132 7915\f
252b5132 7916char *
499ac353 7917md_atof (int type, char *litP, int *sizeP)
252b5132 7918{
499ac353
NC		 7919 /* This outputs the LITTLENUMs in REVERSE order;
7920 in accord with the bigendian 386. */
7921 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7922}
7923\f
2d545b82 7924static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7925
252b5132 7926static char *
e3bb37b5 7927output_invalid (int c)
252b5132 7928{
3882b010 7929 if (ISPRINT (c))
f9f21a03
L		 7930 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7931 "'%c'", c);
252b5132 7932 else
f9f21a03 7933 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7934 "(0x%x)", (unsigned char) c);
252b5132
RH		 7935 return output_invalid_buf;
7936}
7937
af6bdddf 7938/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7939
7940static const reg_entry *
4d1bb795 7941parse_real_register (char *reg_string, char **end_op)
252b5132 7942{
af6bdddf
AM		 7943 char *s = reg_string;
7944 char *p;
252b5132
RH		 7945 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7946 const reg_entry *r;
7947
7948 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7949 if (*s == REGISTER_PREFIX)
7950 ++s;
7951
7952 if (is_space_char (*s))
7953 ++s;
7954
7955 p = reg_name_given;
af6bdddf 7956 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7957 {
7958 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7959 return (const reg_entry *) NULL;
7960 s++;
252b5132
RH		 7961 }
7962
6588847e
DN		 7963 /* For naked regs, make sure that we are not dealing with an identifier.
7964 This prevents confusing an identifier like `eax_var' with register
7965 `eax'. */
7966 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7967 return (const reg_entry *) NULL;
7968
af6bdddf 7969 *end_op = s;
252b5132
RH		 7970
7971 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7972
5f47d35b 7973 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7974 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7975 {
5f47d35b
AM		 7976 if (is_space_char (*s))
7977 ++s;
7978 if (*s == '(')
7979 {
af6bdddf 7980 ++s;
5f47d35b
AM		 7981 if (is_space_char (*s))
7982 ++s;
7983 if (*s >= '0' && *s <= '7')
7984 {
db557034 7985 int fpr = *s - '0';
af6bdddf 7986 ++s;
5f47d35b
AM		 7987 if (is_space_char (*s))
7988 ++s;
7989 if (*s == ')')
7990 {
7991 *end_op = s + 1;
1e9cc1c2 7992 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7993 know (r);
7994 return r + fpr;
5f47d35b 7995 }
5f47d35b 7996 }
47926f60 7997 /* We have "%st(" then garbage. */
5f47d35b
AM		 7998 return (const reg_entry *) NULL;
7999 }
8000 }
8001
a60de03c
JB		 8002 if (r == NULL || allow_pseudo_reg)
8003 return r;
8004
0dfbf9d7 8005 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8006 return (const reg_entry *) NULL;
8007
192dc9c6
JB		 8008 if ((r->reg_type.bitfield.reg32
8009 || r->reg_type.bitfield.sreg3
8010 || r->reg_type.bitfield.control
8011 || r->reg_type.bitfield.debug
8012 || r->reg_type.bitfield.test)
8013 && !cpu_arch_flags.bitfield.cpui386)
8014 return (const reg_entry *) NULL;
8015
309d3373
JB		 8016 if (r->reg_type.bitfield.floatreg
8017 && !cpu_arch_flags.bitfield.cpu8087
8018 && !cpu_arch_flags.bitfield.cpu287
8019 && !cpu_arch_flags.bitfield.cpu387)
8020 return (const reg_entry *) NULL;
8021
192dc9c6
JB		 8022 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8023 return (const reg_entry *) NULL;
8024
8025 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8026 return (const reg_entry *) NULL;
8027
40f12533
L		 8028 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8029 return (const reg_entry *) NULL;
8030
db51cc60 8031 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8032 if (!allow_index_reg
db51cc60
L		 8033 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8034 return (const reg_entry *) NULL;
8035
a60de03c
JB		 8036 if (((r->reg_flags & (RegRex64 | RegRex))
8037 || r->reg_type.bitfield.reg64)
40fb9820 8038 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8039 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8040 && flag_code != CODE_64BIT)
20f0a1fc 8041 return (const reg_entry *) NULL;
1ae00879 8042
b7240065
JB		 8043 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8044 return (const reg_entry *) NULL;
8045
252b5132
RH		 8046 return r;
8047}
4d1bb795
JB		 8048
8049/* REG_STRING starts *before* REGISTER_PREFIX. */
8050
8051static const reg_entry *
8052parse_register (char *reg_string, char **end_op)
8053{
8054 const reg_entry *r;
8055
8056 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8057 r = parse_real_register (reg_string, end_op);
8058 else
8059 r = NULL;
8060 if (!r)
8061 {
8062 char *save = input_line_pointer;
8063 char c;
8064 symbolS *symbolP;
8065
8066 input_line_pointer = reg_string;
8067 c = get_symbol_end ();
8068 symbolP = symbol_find (reg_string);
8069 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8070 {
8071 const expressionS *e = symbol_get_value_expression (symbolP);
8072
0398aac5 8073 know (e->X_op == O_register);
4eed87de 8074 know (e->X_add_number >= 0
c3fe08fa 8075 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8076 r = i386_regtab + e->X_add_number;
8077 *end_op = input_line_pointer;
8078 }
8079 *input_line_pointer = c;
8080 input_line_pointer = save;
8081 }
8082 return r;
8083}
8084
8085int
8086i386_parse_name (char *name, expressionS *e, char *nextcharP)
8087{
8088 const reg_entry *r;
8089 char *end = input_line_pointer;
8090
8091 *end = *nextcharP;
8092 r = parse_register (name, &input_line_pointer);
8093 if (r && end <= input_line_pointer)
8094 {
8095 *nextcharP = *input_line_pointer;
8096 *input_line_pointer = 0;
8097 e->X_op = O_register;
8098 e->X_add_number = r - i386_regtab;
8099 return 1;
8100 }
8101 input_line_pointer = end;
8102 *end = 0;
ee86248c 8103 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8104}
8105
8106void
8107md_operand (expressionS *e)
8108{
ee86248c
JB		 8109 char *end;
8110 const reg_entry *r;
4d1bb795 8111
ee86248c
JB		 8112 switch (*input_line_pointer)
8113 {
8114 case REGISTER_PREFIX:
8115 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8116 if (r)
8117 {
8118 e->X_op = O_register;
8119 e->X_add_number = r - i386_regtab;
8120 input_line_pointer = end;
8121 }
ee86248c
JB		 8122 break;
8123
8124 case '[':
9c2799c2 8125 gas_assert (intel_syntax);
ee86248c
JB		 8126 end = input_line_pointer++;
8127 expression (e);
8128 if (*input_line_pointer == ']')
8129 {
8130 ++input_line_pointer;
8131 e->X_op_symbol = make_expr_symbol (e);
8132 e->X_add_symbol = NULL;
8133 e->X_add_number = 0;
8134 e->X_op = O_index;
8135 }
8136 else
8137 {
8138 e->X_op = O_absent;
8139 input_line_pointer = end;
8140 }
8141 break;
4d1bb795
JB		 8142 }
8143}
8144
252b5132 8145\f
4cc782b5 8146#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8147const char *md_shortopts = "kVQ:sqn";
252b5132 8148#else
12b55ccc 8149const char *md_shortopts = "qn";
252b5132 8150#endif
6e0b89ee 8151
3e73aa7c 8152#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8153#define OPTION_64 (OPTION_MD_BASE + 1)
8154#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8155#define OPTION_MARCH (OPTION_MD_BASE + 3)
8156#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8157#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8158#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8159#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8160#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8161#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8162#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8163#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8164#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
570561f7 8165#define OPTION_X32 (OPTION_MD_BASE + 13)
b3b91714 8166
99ad8390
NC		 8167struct option md_longopts[] =
8168{
3e73aa7c 8169 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8170#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8171 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8172 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8173#endif
8174#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8175 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8176#endif
b3b91714 8177 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8178 {"march", required_argument, NULL, OPTION_MARCH},
8179 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8180 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8181 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8182 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8183 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8184 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8185 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8186 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8187 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8188 {NULL, no_argument, NULL, 0}
8189};
8190size_t md_longopts_size = sizeof (md_longopts);
8191
8192int
9103f4f4 8193md_parse_option (int c, char *arg)
252b5132 8194{
91d6fa6a 8195 unsigned int j;
6305a203 8196 char *arch, *next;
9103f4f4 8197
252b5132
RH		 8198 switch (c)
8199 {
12b55ccc
L		 8200 case 'n':
8201 optimize_align_code = 0;
8202 break;
8203
a38cf1db
AM		 8204 case 'q':
8205 quiet_warnings = 1;
252b5132
RH		 8206 break;
8207
8208#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8209 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8210 should be emitted or not. FIXME: Not implemented. */
8211 case 'Q':
252b5132
RH		 8212 break;
8213
8214 /* -V: SVR4 argument to print version ID. */
8215 case 'V':
8216 print_version_id ();
8217 break;
8218
a38cf1db
AM		 8219 /* -k: Ignore for FreeBSD compatibility. */
8220 case 'k':
252b5132 8221 break;
4cc782b5
ILT		 8222
8223 case 's':
8224 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8225 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8226 break;
99ad8390 8227#endif
321098a5
L		 8228#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8229 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8230 case OPTION_64:
8231 {
8232 const char **list, **l;
8233
3e73aa7c
JH		 8234 list = bfd_target_list ();
8235 for (l = list; *l != NULL; l++)
8620418b 8236 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8237 || strcmp (*l, "coff-x86-64") == 0
8238 || strcmp (*l, "pe-x86-64") == 0
8239 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8240 {
8241 default_arch = "x86_64";
8242 break;
8243 }
3e73aa7c 8244 if (*l == NULL)
6e0b89ee 8245 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8246 free (list);
8247 }
8248 break;
8249#endif
252b5132 8250
351f65ca 8251#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8252 case OPTION_X32:
351f65ca
L		 8253 if (IS_ELF)
8254 {
8255 const char **list, **l;
8256
8257 list = bfd_target_list ();
8258 for (l = list; *l != NULL; l++)
8259 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8260 {
8261 default_arch = "x86_64:32";
8262 break;
8263 }
8264 if (*l == NULL)
8265 as_fatal (_("No compiled in support for 32bit x86_64"));
8266 free (list);
8267 }
8268 else
8269 as_fatal (_("32bit x86_64 is only supported for ELF"));
8270 break;
8271#endif
8272
6e0b89ee
AM		 8273 case OPTION_32:
8274 default_arch = "i386";
8275 break;
8276
b3b91714
AM		 8277 case OPTION_DIVIDE:
8278#ifdef SVR4_COMMENT_CHARS
8279 {
8280 char *n, *t;
8281 const char *s;
8282
8283 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8284 t = n;
8285 for (s = i386_comment_chars; *s != '\0'; s++)
8286 if (*s != '/')
8287 *t++ = *s;
8288 *t = '\0';
8289 i386_comment_chars = n;
8290 }
8291#endif
8292 break;
8293
9103f4f4 8294 case OPTION_MARCH:
6305a203
L		 8295 arch = xstrdup (arg);
8296 do
9103f4f4 8297 {
6305a203
L		 8298 if (*arch == '.')
8299 as_fatal (_("Invalid -march= option: `%s'"), arg);
8300 next = strchr (arch, '+');
8301 if (next)
8302 *next++ = '\0';
91d6fa6a 8303 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8304 {
91d6fa6a 8305 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8306 {
6305a203 8307 /* Processor. */
1ded5609
JB		 8308 if (! cpu_arch[j].flags.bitfield.cpui386)
8309 continue;
8310
91d6fa6a 8311 cpu_arch_name = cpu_arch[j].name;
6305a203 8312 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8313 cpu_arch_flags = cpu_arch[j].flags;
8314 cpu_arch_isa = cpu_arch[j].type;
8315 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8316 if (!cpu_arch_tune_set)
8317 {
8318 cpu_arch_tune = cpu_arch_isa;
8319 cpu_arch_tune_flags = cpu_arch_isa_flags;
8320 }
8321 break;
8322 }
91d6fa6a
NC		 8323 else if (*cpu_arch [j].name == '.'
8324 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8325 {
8326 /* ISA entension. */
8327 i386_cpu_flags flags;
309d3373 8328
49021df2 8329 if (!cpu_arch[j].negated)
309d3373 8330 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8331 cpu_arch[j].flags);
309d3373
JB		 8332 else
8333 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8334 cpu_arch[j].flags);
0dfbf9d7 8335 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8336 {
8337 if (cpu_sub_arch_name)
8338 {
8339 char *name = cpu_sub_arch_name;
8340 cpu_sub_arch_name = concat (name,
91d6fa6a 8341 cpu_arch[j].name,
1bf57e9f 8342 (const char *) NULL);
6305a203
L		 8343 free (name);
8344 }
8345 else
91d6fa6a 8346 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8347 cpu_arch_flags = flags;
a586129e 8348 cpu_arch_isa_flags = flags;
6305a203
L		 8349 }
8350 break;
ccc9c027 8351 }
9103f4f4 8352 }
6305a203 8353
91d6fa6a 8354 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8355 as_fatal (_("Invalid -march= option: `%s'"), arg);
8356
8357 arch = next;
9103f4f4 8358 }
6305a203 8359 while (next != NULL );
9103f4f4
L		 8360 break;
8361
8362 case OPTION_MTUNE:
8363 if (*arg == '.')
8364 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8365 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8366 {
91d6fa6a 8367 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8368 {
ccc9c027 8369 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8370 cpu_arch_tune = cpu_arch [j].type;
8371 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8372 break;
8373 }
8374 }
91d6fa6a 8375 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8376 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8377 break;
8378
1efbbeb4
L		 8379 case OPTION_MMNEMONIC:
8380 if (strcasecmp (arg, "att") == 0)
8381 intel_mnemonic = 0;
8382 else if (strcasecmp (arg, "intel") == 0)
8383 intel_mnemonic = 1;
8384 else
8385 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8386 break;
8387
8388 case OPTION_MSYNTAX:
8389 if (strcasecmp (arg, "att") == 0)
8390 intel_syntax = 0;
8391 else if (strcasecmp (arg, "intel") == 0)
8392 intel_syntax = 1;
8393 else
8394 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8395 break;
8396
8397 case OPTION_MINDEX_REG:
8398 allow_index_reg = 1;
8399 break;
8400
8401 case OPTION_MNAKED_REG:
8402 allow_naked_reg = 1;
8403 break;
8404
8405 case OPTION_MOLD_GCC:
8406 old_gcc = 1;
1efbbeb4
L		 8407 break;
8408
c0f3af97
L		 8409 case OPTION_MSSE2AVX:
8410 sse2avx = 1;
8411 break;
8412
daf50ae7
L		 8413 case OPTION_MSSE_CHECK:
8414 if (strcasecmp (arg, "error") == 0)
8415 sse_check = sse_check_error;
8416 else if (strcasecmp (arg, "warning") == 0)
8417 sse_check = sse_check_warning;
8418 else if (strcasecmp (arg, "none") == 0)
8419 sse_check = sse_check_none;
8420 else
8421 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8422 break;
8423
539f890d
L		 8424 case OPTION_MAVXSCALAR:
8425 if (strcasecmp (arg, "128") == 0)
8426 avxscalar = vex128;
8427 else if (strcasecmp (arg, "256") == 0)
8428 avxscalar = vex256;
8429 else
8430 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8431 break;
8432
252b5132
RH		 8433 default:
8434 return 0;
8435 }
8436 return 1;
8437}
8438
8a2c8fef
L		 8439#define MESSAGE_TEMPLATE \
8440" "
8441
8442static void
1ded5609 8443show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8444{
8445 static char message[] = MESSAGE_TEMPLATE;
8446 char *start = message + 27;
8447 char *p;
8448 int size = sizeof (MESSAGE_TEMPLATE);
8449 int left;
8450 const char *name;
8451 int len;
8452 unsigned int j;
8453
8454 p = start;
8455 left = size - (start - message);
8456 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8457 {
8458 /* Should it be skipped? */
8459 if (cpu_arch [j].skip)
8460 continue;
8461
8462 name = cpu_arch [j].name;
8463 len = cpu_arch [j].len;
8464 if (*name == '.')
8465 {
8466 /* It is an extension. Skip if we aren't asked to show it. */
8467 if (ext)
8468 {
8469 name++;
8470 len--;
8471 }
8472 else
8473 continue;
8474 }
8475 else if (ext)
8476 {
8477 /* It is an processor. Skip if we show only extension. */
8478 continue;
8479 }
1ded5609
JB		 8480 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8481 {
8482 /* It is an impossible processor - skip. */
8483 continue;
8484 }
8a2c8fef
L		 8485
8486 /* Reserve 2 spaces for ", " or ",\0" */
8487 left -= len + 2;
8488
8489 /* Check if there is any room. */
8490 if (left >= 0)
8491 {
8492 if (p != start)
8493 {
8494 *p++ = ',';
8495 *p++ = ' ';
8496 }
8497 p = mempcpy (p, name, len);
8498 }
8499 else
8500 {
8501 /* Output the current message now and start a new one. */
8502 *p++ = ',';
8503 *p = '\0';
8504 fprintf (stream, "%s\n", message);
8505 p = start;
8506 left = size - (start - message) - len - 2;
8507
8508 gas_assert (left >= 0);
8509
8510 p = mempcpy (p, name, len);
8511 }
8512 }
8513
8514 *p = '\0';
8515 fprintf (stream, "%s\n", message);
8516}
8517
252b5132 8518void
8a2c8fef 8519md_show_usage (FILE *stream)
252b5132 8520{
4cc782b5
ILT		 8521#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8522 fprintf (stream, _("\
a38cf1db
AM		 8523 -Q ignored\n\
8524 -V print assembler version number\n\
b3b91714
AM		 8525 -k ignored\n"));
8526#endif
8527 fprintf (stream, _("\
12b55ccc 8528 -n Do not optimize code alignment\n\
b3b91714
AM		 8529 -q quieten some warnings\n"));
8530#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8531 fprintf (stream, _("\
a38cf1db 8532 -s ignored\n"));
b3b91714 8533#endif
321098a5
L		 8534#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8535 || defined (TE_PE) || defined (TE_PEP))
751d281c 8536 fprintf (stream, _("\
570561f7 8537 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8538#endif
b3b91714
AM		 8539#ifdef SVR4_COMMENT_CHARS
8540 fprintf (stream, _("\
8541 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8542#else
8543 fprintf (stream, _("\
b3b91714 8544 --divide ignored\n"));
4cc782b5 8545#endif
9103f4f4 8546 fprintf (stream, _("\
6305a203 8547 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8548 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8549 show_arch (stream, 0, 1);
8a2c8fef
L		 8550 fprintf (stream, _("\
8551 EXTENSION is combination of:\n"));
1ded5609 8552 show_arch (stream, 1, 0);
6305a203 8553 fprintf (stream, _("\
8a2c8fef 8554 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8555 show_arch (stream, 0, 0);
ba104c83 8556 fprintf (stream, _("\
c0f3af97
L		 8557 -msse2avx encode SSE instructions with VEX prefix\n"));
8558 fprintf (stream, _("\
daf50ae7
L		 8559 -msse-check=[none|error|warning]\n\
8560 check SSE instructions\n"));
8561 fprintf (stream, _("\
539f890d
L		 8562 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8563 length\n"));
8564 fprintf (stream, _("\
ba104c83
L		 8565 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8566 fprintf (stream, _("\
8567 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8568 fprintf (stream, _("\
8569 -mindex-reg support pseudo index registers\n"));
8570 fprintf (stream, _("\
8571 -mnaked-reg don't require `%%' prefix for registers\n"));
8572 fprintf (stream, _("\
8573 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8574}
8575
3e73aa7c 8576#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8577 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8578 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8579
8580/* Pick the target format to use. */
8581
47926f60 8582const char *
e3bb37b5 8583i386_target_format (void)
252b5132 8584{
351f65ca
L		 8585 if (!strncmp (default_arch, "x86_64", 6))
8586 {
8587 update_code_flag (CODE_64BIT, 1);
8588 if (default_arch[6] == '\0')
7f56bc95 8589 x86_elf_abi = X86_64_ABI;
351f65ca 8590 else
7f56bc95 8591 x86_elf_abi = X86_64_X32_ABI;
351f65ca 8592 }
3e73aa7c 8593 else if (!strcmp (default_arch, "i386"))
78f12dd3 8594 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8595 else
8596 as_fatal (_("Unknown architecture"));
89507696
JB		 8597
8598 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8599 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8600 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8601 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8602
252b5132
RH		 8603 switch (OUTPUT_FLAVOR)
8604 {
9384f2ff 8605#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8606 case bfd_target_aout_flavour:
47926f60 8607 return AOUT_TARGET_FORMAT;
4c63da97 8608#endif
9384f2ff
AM		 8609#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8610# if defined (TE_PE) || defined (TE_PEP)
8611 case bfd_target_coff_flavour:
8612 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8613# elif defined (TE_GO32)
0561d57c
JK		 8614 case bfd_target_coff_flavour:
8615 return "coff-go32";
9384f2ff 8616# else
252b5132
RH		 8617 case bfd_target_coff_flavour:
8618 return "coff-i386";
9384f2ff 8619# endif
4c63da97 8620#endif
3e73aa7c 8621#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8622 case bfd_target_elf_flavour:
3e73aa7c 8623 {
351f65ca
L		 8624 const char *format;
8625
8626 switch (x86_elf_abi)
4fa24527 8627 {
351f65ca
L		 8628 default:
8629 format = ELF_TARGET_FORMAT;
8630 break;
7f56bc95 8631 case X86_64_ABI:
351f65ca 8632 use_rela_relocations = 1;
4fa24527 8633 object_64bit = 1;
351f65ca
L		 8634 format = ELF_TARGET_FORMAT64;
8635 break;
7f56bc95 8636 case X86_64_X32_ABI:
4fa24527 8637 use_rela_relocations = 1;
351f65ca 8638 object_64bit = 1;
862be3fb 8639 disallow_64bit_reloc = 1;
351f65ca
L		 8640 format = ELF_TARGET_FORMAT32;
8641 break;
4fa24527 8642 }
3632d14b 8643 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8644 {
7f56bc95 8645 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 8646 as_fatal (_("Intel L1OM is 64bit only"));
8647 return ELF_TARGET_L1OM_FORMAT;
8648 }
8649 else
351f65ca 8650 return format;
3e73aa7c 8651 }
e57f8c65
TG		 8652#endif
8653#if defined (OBJ_MACH_O)
8654 case bfd_target_mach_o_flavour:
8655 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8656#endif
252b5132
RH		 8657 default:
8658 abort ();
8659 return NULL;
8660 }
8661}
8662
47926f60 8663#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8664
8665#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8666void
8667i386_elf_emit_arch_note (void)
a847613f 8668{
718ddfc0 8669 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8670 {
8671 char *p;
8672 asection *seg = now_seg;
8673 subsegT subseg = now_subseg;
8674 Elf_Internal_Note i_note;
8675 Elf_External_Note e_note;
8676 asection *note_secp;
8677 int len;
8678
8679 /* Create the .note section. */
8680 note_secp = subseg_new (".note", 0);
8681 bfd_set_section_flags (stdoutput,
8682 note_secp,
8683 SEC_HAS_CONTENTS | SEC_READONLY);
8684
8685 /* Process the arch string. */
8686 len = strlen (cpu_arch_name);
8687
8688 i_note.namesz = len + 1;
8689 i_note.descsz = 0;
8690 i_note.type = NT_ARCH;
8691 p = frag_more (sizeof (e_note.namesz));
8692 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8693 p = frag_more (sizeof (e_note.descsz));
8694 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8695 p = frag_more (sizeof (e_note.type));
8696 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8697 p = frag_more (len + 1);
8698 strcpy (p, cpu_arch_name);
8699
8700 frag_align (2, 0, 0);
8701
8702 subseg_set (seg, subseg);
8703 }
8704}
8705#endif
252b5132 8706\f
252b5132
RH		 8707symbolS *
8708md_undefined_symbol (name)
8709 char *name;
8710{
18dc2407
ILT		 8711 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8712 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8713 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8714 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8715 {
8716 if (!GOT_symbol)
8717 {
8718 if (symbol_find (name))
8719 as_bad (_("GOT already in symbol table"));
8720 GOT_symbol = symbol_new (name, undefined_section,
8721 (valueT) 0, &zero_address_frag);
8722 };
8723 return GOT_symbol;
8724 }
252b5132
RH		 8725 return 0;
8726}
8727
8728/* Round up a section size to the appropriate boundary. */
47926f60 8729
252b5132
RH		 8730valueT
8731md_section_align (segment, size)
ab9da554 8732 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8733 valueT size;
8734{
4c63da97
AM		 8735#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8736 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8737 {
8738 /* For a.out, force the section size to be aligned. If we don't do
8739 this, BFD will align it for us, but it will not write out the
8740 final bytes of the section. This may be a bug in BFD, but it is
8741 easier to fix it here since that is how the other a.out targets
8742 work. */
8743 int align;
8744
8745 align = bfd_get_section_alignment (stdoutput, segment);
8746 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8747 }
252b5132
RH		 8748#endif
8749
8750 return size;
8751}
8752
8753/* On the i386, PC-relative offsets are relative to the start of the
8754 next instruction. That is, the address of the offset, plus its
8755 size, since the offset is always the last part of the insn. */
8756
8757long
e3bb37b5 8758md_pcrel_from (fixS *fixP)
252b5132
RH		 8759{
8760 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8761}
8762
8763#ifndef I386COFF
8764
8765static void
e3bb37b5 8766s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8767{
29b0f896 8768 int temp;
252b5132 8769
8a75718c
JB		 8770#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8771 if (IS_ELF)
8772 obj_elf_section_change_hook ();
8773#endif
252b5132
RH		 8774 temp = get_absolute_expression ();
8775 subseg_set (bss_section, (subsegT) temp);
8776 demand_empty_rest_of_line ();
8777}
8778
8779#endif
8780
252b5132 8781void
e3bb37b5 8782i386_validate_fix (fixS *fixp)
252b5132
RH		 8783{
8784 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8785 {
23df1078
JH		 8786 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8787 {
4fa24527 8788 if (!object_64bit)
23df1078
JH		 8789 abort ();
8790 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8791 }
8792 else
8793 {
4fa24527 8794 if (!object_64bit)
d6ab8113
JB		 8795 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8796 else
8797 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8798 }
252b5132
RH		 8799 fixp->fx_subsy = 0;
8800 }
8801}
8802
252b5132
RH		 8803arelent *
8804tc_gen_reloc (section, fixp)
ab9da554 8805 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8806 fixS *fixp;
8807{
8808 arelent *rel;
8809 bfd_reloc_code_real_type code;
8810
8811 switch (fixp->fx_r_type)
8812 {
3e73aa7c
JH		 8813 case BFD_RELOC_X86_64_PLT32:
8814 case BFD_RELOC_X86_64_GOT32:
8815 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8816 case BFD_RELOC_386_PLT32:
8817 case BFD_RELOC_386_GOT32:
8818 case BFD_RELOC_386_GOTOFF:
8819 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8820 case BFD_RELOC_386_TLS_GD:
8821 case BFD_RELOC_386_TLS_LDM:
8822 case BFD_RELOC_386_TLS_LDO_32:
8823 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8824 case BFD_RELOC_386_TLS_IE:
8825 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8826 case BFD_RELOC_386_TLS_LE_32:
8827 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8828 case BFD_RELOC_386_TLS_GOTDESC:
8829 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8830 case BFD_RELOC_X86_64_TLSGD:
8831 case BFD_RELOC_X86_64_TLSLD:
8832 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8833 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8834 case BFD_RELOC_X86_64_GOTTPOFF:
8835 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8836 case BFD_RELOC_X86_64_TPOFF64:
8837 case BFD_RELOC_X86_64_GOTOFF64:
8838 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8839 case BFD_RELOC_X86_64_GOT64:
8840 case BFD_RELOC_X86_64_GOTPCREL64:
8841 case BFD_RELOC_X86_64_GOTPC64:
8842 case BFD_RELOC_X86_64_GOTPLT64:
8843 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8844 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8845 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8846 case BFD_RELOC_RVA:
8847 case BFD_RELOC_VTABLE_ENTRY:
8848 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8849#ifdef TE_PE
8850 case BFD_RELOC_32_SECREL:
8851#endif
252b5132
RH		 8852 code = fixp->fx_r_type;
8853 break;
dbbaec26
L		 8854 case BFD_RELOC_X86_64_32S:
8855 if (!fixp->fx_pcrel)
8856 {
8857 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8858 code = fixp->fx_r_type;
8859 break;
8860 }
252b5132 8861 default:
93382f6d 8862 if (fixp->fx_pcrel)
252b5132 8863 {
93382f6d
AM		 8864 switch (fixp->fx_size)
8865 {
8866 default:
b091f402
AM		 8867 as_bad_where (fixp->fx_file, fixp->fx_line,
8868 _("can not do %d byte pc-relative relocation"),
8869 fixp->fx_size);
93382f6d
AM		 8870 code = BFD_RELOC_32_PCREL;
8871 break;
8872 case 1: code = BFD_RELOC_8_PCREL; break;
8873 case 2: code = BFD_RELOC_16_PCREL; break;
8874 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8875#ifdef BFD64
8876 case 8: code = BFD_RELOC_64_PCREL; break;
8877#endif
93382f6d
AM		 8878 }
8879 }
8880 else
8881 {
8882 switch (fixp->fx_size)
8883 {
8884 default:
b091f402
AM		 8885 as_bad_where (fixp->fx_file, fixp->fx_line,
8886 _("can not do %d byte relocation"),
8887 fixp->fx_size);
93382f6d
AM		 8888 code = BFD_RELOC_32;
8889 break;
8890 case 1: code = BFD_RELOC_8; break;
8891 case 2: code = BFD_RELOC_16; break;
8892 case 4: code = BFD_RELOC_32; break;
937149dd 8893#ifdef BFD64
3e73aa7c 8894 case 8: code = BFD_RELOC_64; break;
937149dd 8895#endif
93382f6d 8896 }
252b5132
RH		 8897 }
8898 break;
8899 }
252b5132 8900
d182319b
JB		 8901 if ((code == BFD_RELOC_32
8902 || code == BFD_RELOC_32_PCREL
8903 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8904 && GOT_symbol
8905 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8906 {
4fa24527 8907 if (!object_64bit)
d6ab8113
JB		 8908 code = BFD_RELOC_386_GOTPC;
8909 else
8910 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8911 }
7b81dfbb
AJ		 8912 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8913 && GOT_symbol
8914 && fixp->fx_addsy == GOT_symbol)
8915 {
8916 code = BFD_RELOC_X86_64_GOTPC64;
8917 }
252b5132
RH		 8918
8919 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8920 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8921 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8922
8923 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8924
3e73aa7c
JH		 8925 if (!use_rela_relocations)
8926 {
8927 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8928 vtable entry to be used in the relocation's section offset. */
8929 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8930 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8931#if defined (OBJ_COFF) && defined (TE_PE)
8932 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8933 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8934 else
8935#endif
c6682705 8936 rel->addend = 0;
3e73aa7c
JH		 8937 }
8938 /* Use the rela in 64bit mode. */
252b5132 8939 else
3e73aa7c 8940 {
862be3fb
L		 8941 if (disallow_64bit_reloc)
8942 switch (code)
8943 {
8944 case BFD_RELOC_64:
8945 case BFD_RELOC_X86_64_DTPOFF64:
8946 case BFD_RELOC_X86_64_TPOFF64:
8947 case BFD_RELOC_64_PCREL:
8948 case BFD_RELOC_X86_64_GOTOFF64:
8949 case BFD_RELOC_X86_64_GOT64:
8950 case BFD_RELOC_X86_64_GOTPCREL64:
8951 case BFD_RELOC_X86_64_GOTPC64:
8952 case BFD_RELOC_X86_64_GOTPLT64:
8953 case BFD_RELOC_X86_64_PLTOFF64:
8954 as_bad_where (fixp->fx_file, fixp->fx_line,
8955 _("cannot represent relocation type %s in x32 mode"),
8956 bfd_get_reloc_code_name (code));
8957 break;
8958 default:
8959 break;
8960 }
8961
062cd5e7
AS		 8962 if (!fixp->fx_pcrel)
8963 rel->addend = fixp->fx_offset;
8964 else
8965 switch (code)
8966 {
8967 case BFD_RELOC_X86_64_PLT32:
8968 case BFD_RELOC_X86_64_GOT32:
8969 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8970 case BFD_RELOC_X86_64_TLSGD:
8971 case BFD_RELOC_X86_64_TLSLD:
8972 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8973 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8974 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8975 rel->addend = fixp->fx_offset - fixp->fx_size;
8976 break;
8977 default:
8978 rel->addend = (section->vma
8979 - fixp->fx_size
8980 + fixp->fx_addnumber
8981 + md_pcrel_from (fixp));
8982 break;
8983 }
3e73aa7c
JH		 8984 }
8985
252b5132
RH		 8986 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8987 if (rel->howto == NULL)
8988 {
8989 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8990 _("cannot represent relocation type %s"),
252b5132
RH		 8991 bfd_get_reloc_code_name (code));
8992 /* Set howto to a garbage value so that we can keep going. */
8993 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8994 gas_assert (rel->howto != NULL);
252b5132
RH		 8995 }
8996
8997 return rel;
8998}
8999
ee86248c 9000#include "tc-i386-intel.c"
54cfded0 9001
a60de03c
JB		 9002void
9003tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9004{
a60de03c
JB		 9005 int saved_naked_reg;
9006 char saved_register_dot;
54cfded0 9007
a60de03c
JB		 9008 saved_naked_reg = allow_naked_reg;
9009 allow_naked_reg = 1;
9010 saved_register_dot = register_chars['.'];
9011 register_chars['.'] = '.';
9012 allow_pseudo_reg = 1;
9013 expression_and_evaluate (exp);
9014 allow_pseudo_reg = 0;
9015 register_chars['.'] = saved_register_dot;
9016 allow_naked_reg = saved_naked_reg;
9017
e96d56a1 9018 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9019 {
a60de03c
JB		 9020 if ((addressT) exp->X_add_number < i386_regtab_size)
9021 {
9022 exp->X_op = O_constant;
9023 exp->X_add_number = i386_regtab[exp->X_add_number]
9024 .dw2_regnum[flag_code >> 1];
9025 }
9026 else
9027 exp->X_op = O_illegal;
54cfded0 9028 }
54cfded0
AM		 9029}
9030
9031void
9032tc_x86_frame_initial_instructions (void)
9033{
a60de03c
JB		 9034 static unsigned int sp_regno[2];
9035
9036 if (!sp_regno[flag_code >> 1])
9037 {
9038 char *saved_input = input_line_pointer;
9039 char sp[][4] = {"esp", "rsp"};
9040 expressionS exp;
a4447b93 9041
a60de03c
JB		 9042 input_line_pointer = sp[flag_code >> 1];
9043 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9044 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9045 sp_regno[flag_code >> 1] = exp.X_add_number;
9046 input_line_pointer = saved_input;
9047 }
a4447b93 9048
61ff971f
L		 9049 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9050 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9051}
d2b2c203
DJ		 9052
9053int
9054i386_elf_section_type (const char *str, size_t len)
9055{
9056 if (flag_code == CODE_64BIT
9057 && len == sizeof ("unwind") - 1
9058 && strncmp (str, "unwind", 6) == 0)
9059 return SHT_X86_64_UNWIND;
9060
9061 return -1;
9062}
bb41ade5 9063
ad5fec3b
EB		 9064#ifdef TE_SOLARIS
9065void
9066i386_solaris_fix_up_eh_frame (segT sec)
9067{
9068 if (flag_code == CODE_64BIT)
9069 elf_section_type (sec) = SHT_X86_64_UNWIND;
9070}
9071#endif
9072
bb41ade5
AM		 9073#ifdef TE_PE
9074void
9075tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9076{
91d6fa6a 9077 expressionS exp;
bb41ade5 9078
91d6fa6a
NC		 9079 exp.X_op = O_secrel;
9080 exp.X_add_symbol = symbol;
9081 exp.X_add_number = 0;
9082 emit_expr (&exp, size);
bb41ade5
AM		 9083}
9084#endif
3b22753a
L		 9085
9086#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9087/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9088
01e1a5bc 9089bfd_vma
3b22753a
L		 9090x86_64_section_letter (int letter, char **ptr_msg)
9091{
9092 if (flag_code == CODE_64BIT)
9093 {
9094 if (letter == 'l')
9095 return SHF_X86_64_LARGE;
9096
8f3bae45 9097 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9098 }
3b22753a 9099 else
8f3bae45 9100 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9101 return -1;
9102}
9103
01e1a5bc 9104bfd_vma
3b22753a
L		 9105x86_64_section_word (char *str, size_t len)
9106{
8620418b 9107 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9108 return SHF_X86_64_LARGE;
9109
9110 return -1;
9111}
9112
9113static void
9114handle_large_common (int small ATTRIBUTE_UNUSED)
9115{
9116 if (flag_code != CODE_64BIT)
9117 {
9118 s_comm_internal (0, elf_common_parse);
9119 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9120 }
9121 else
9122 {
9123 static segT lbss_section;
9124 asection *saved_com_section_ptr = elf_com_section_ptr;
9125 asection *saved_bss_section = bss_section;
9126
9127 if (lbss_section == NULL)
9128 {
9129 flagword applicable;
9130 segT seg = now_seg;
9131 subsegT subseg = now_subseg;
9132
9133 /* The .lbss section is for local .largecomm symbols. */
9134 lbss_section = subseg_new (".lbss", 0);
9135 applicable = bfd_applicable_section_flags (stdoutput);
9136 bfd_set_section_flags (stdoutput, lbss_section,
9137 applicable & SEC_ALLOC);
9138 seg_info (lbss_section)->bss = 1;
9139
9140 subseg_set (seg, subseg);
9141 }
9142
9143 elf_com_section_ptr = &_bfd_elf_large_com_section;
9144 bss_section = lbss_section;
9145
9146 s_comm_internal (0, elf_common_parse);
9147
9148 elf_com_section_ptr = saved_com_section_ptr;
9149 bss_section = saved_bss_section;
9150 }
9151}
9152#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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