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x86: fold several AVX512VL templates
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
265 old_gcc_only,
266 unsupported_with_intel_mnemonic,
267 unsupported_syntax,
6c30d220
L		 268 unsupported,
269 invalid_vsib_address,
7bab8ab5 270 invalid_vector_register_set,
43234a1e
L		 271 unsupported_vector_index_register,
272 unsupported_broadcast,
273 broadcast_not_on_src_operand,
274 broadcast_needed,
275 unsupported_masking,
276 mask_not_on_destination,
277 no_default_mask,
278 unsupported_rc_sae,
279 rc_sae_operand_not_last_imm,
280 invalid_register_operand,
a65babc9
L		 281 };
282
252b5132
RH		 283struct _i386_insn
284 {
47926f60 285 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 286 insn_template tm;
252b5132 287
7d5e4556
L		 288 /* SUFFIX holds the instruction size suffix for byte, word, dword
289 or qword, if given. */
252b5132
RH		 290 char suffix;
291
47926f60 292 /* OPERANDS gives the number of given operands. */
252b5132
RH		 293 unsigned int operands;
294
295 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
296 of given register, displacement, memory operands and immediate
47926f60 297 operands. */
252b5132
RH		 298 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299
300 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 301 use OP[i] for the corresponding operand. */
40fb9820 302 i386_operand_type types[MAX_OPERANDS];
252b5132 303
520dc8e8
AM		 304 /* Displacement expression, immediate expression, or register for each
305 operand. */
306 union i386_op op[MAX_OPERANDS];
252b5132 307
3e73aa7c
JH		 308 /* Flags for operands. */
309 unsigned int flags[MAX_OPERANDS];
310#define Operand_PCrel 1
311
252b5132 312 /* Relocation type for operand */
f86103b7 313 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 314
252b5132
RH		 315 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
316 the base index byte below. */
317 const reg_entry *base_reg;
318 const reg_entry *index_reg;
319 unsigned int log2_scale_factor;
320
321 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 322 explicit segment overrides are given. */
ce8a8b2f 323 const seg_entry *seg[2];
252b5132 324
8325cc63
JB		 325 /* Copied first memory operand string, for re-checking. */
326 char *memop1_string;
327
252b5132
RH		 328 /* PREFIX holds all the given prefix opcodes (usually null).
329 PREFIXES is the number of prefix opcodes. */
330 unsigned int prefixes;
331 unsigned char prefix[MAX_PREFIXES];
332
333 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 334 addressing modes of this insn are encoded. */
252b5132 335 modrm_byte rm;
3e73aa7c 336 rex_byte rex;
43234a1e 337 rex_byte vrex;
252b5132 338 sib_byte sib;
c0f3af97 339 vex_prefix vex;
b6169b20 340
43234a1e
L		 341 /* Masking attributes. */
342 struct Mask_Operation *mask;
343
344 /* Rounding control and SAE attributes. */
345 struct RC_Operation *rounding;
346
347 /* Broadcasting attributes. */
348 struct Broadcast_Operation *broadcast;
349
350 /* Compressed disp8*N attribute. */
351 unsigned int memshift;
352
86fa6981
L		 353 /* Prefer load or store in encoding. */
354 enum
355 {
356 dir_encoding_default = 0,
357 dir_encoding_load,
358 dir_encoding_store
359 } dir_encoding;
891edac4 360
a501d77e
L		 361 /* Prefer 8bit or 32bit displacement in encoding. */
362 enum
363 {
364 disp_encoding_default = 0,
365 disp_encoding_8bit,
366 disp_encoding_32bit
367 } disp_encoding;
f8a5c266 368
6b6b6807
L		 369 /* Prefer the REX byte in encoding. */
370 bfd_boolean rex_encoding;
371
b6f8c7c4
L		 372 /* Disable instruction size optimization. */
373 bfd_boolean no_optimize;
374
86fa6981
L		 375 /* How to encode vector instructions. */
376 enum
377 {
378 vex_encoding_default = 0,
379 vex_encoding_vex2,
380 vex_encoding_vex3,
381 vex_encoding_evex
382 } vec_encoding;
383
d5de92cf
L		 384 /* REP prefix. */
385 const char *rep_prefix;
386
165de32a
L		 387 /* HLE prefix. */
388 const char *hle_prefix;
42164a71 389
7e8b059b
L		 390 /* Have BND prefix. */
391 const char *bnd_prefix;
392
04ef582a
L		 393 /* Have NOTRACK prefix. */
394 const char *notrack_prefix;
395
891edac4 396 /* Error message. */
a65babc9 397 enum i386_error error;
252b5132
RH		 398 };
399
400typedef struct _i386_insn i386_insn;
401
43234a1e
L		 402/* Link RC type with corresponding string, that'll be looked for in
403 asm. */
404struct RC_name
405{
406 enum rc_type type;
407 const char *name;
408 unsigned int len;
409};
410
411static const struct RC_name RC_NamesTable[] =
412{
413 { rne, STRING_COMMA_LEN ("rn-sae") },
414 { rd, STRING_COMMA_LEN ("rd-sae") },
415 { ru, STRING_COMMA_LEN ("ru-sae") },
416 { rz, STRING_COMMA_LEN ("rz-sae") },
417 { saeonly, STRING_COMMA_LEN ("sae") },
418};
419
252b5132
RH		 420/* List of chars besides those in app.c:symbol_chars that can start an
421 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 422const char extra_symbol_chars[] = "*%-([{}"
252b5132 423#ifdef LEX_AT
32137342
NC		 424 "@"
425#endif
426#ifdef LEX_QM
427 "?"
252b5132 428#endif
32137342 429 ;
252b5132 430
29b0f896
AM		 431#if (defined (TE_I386AIX) \
432 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 433 && !defined (TE_GNU) \
29b0f896 434 && !defined (TE_LINUX) \
8d63c93e
RM		 435 && !defined (TE_NACL) \
436 && !defined (TE_NETWARE) \
29b0f896 437 && !defined (TE_FreeBSD) \
5b806d27 438 && !defined (TE_DragonFly) \
29b0f896 439 && !defined (TE_NetBSD)))
252b5132 440/* This array holds the chars that always start a comment. If the
b3b91714
AM		 441 pre-processor is disabled, these aren't very useful. The option
442 --divide will remove '/' from this list. */
443const char *i386_comment_chars = "#/";
444#define SVR4_COMMENT_CHARS 1
252b5132 445#define PREFIX_SEPARATOR '\\'
252b5132 446
b3b91714
AM		 447#else
448const char *i386_comment_chars = "#";
449#define PREFIX_SEPARATOR '/'
450#endif
451
252b5132
RH		 452/* This array holds the chars that only start a comment at the beginning of
453 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 454 .line and .file directives will appear in the pre-processed output.
455 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 456 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 457 #NO_APP at the beginning of its output.
458 Also note that comments started like this one will always work if
252b5132 459 '/' isn't otherwise defined. */
b3b91714 460const char line_comment_chars[] = "#/";
252b5132 461
63a0b638 462const char line_separator_chars[] = ";";
252b5132 463
ce8a8b2f
AM		 464/* Chars that can be used to separate mant from exp in floating point
465 nums. */
252b5132
RH		 466const char EXP_CHARS[] = "eE";
467
ce8a8b2f
AM		 468/* Chars that mean this number is a floating point constant
469 As in 0f12.456
470 or 0d1.2345e12. */
252b5132
RH		 471const char FLT_CHARS[] = "fFdDxX";
472
ce8a8b2f 473/* Tables for lexical analysis. */
252b5132
RH		 474static char mnemonic_chars[256];
475static char register_chars[256];
476static char operand_chars[256];
477static char identifier_chars[256];
478static char digit_chars[256];
479
ce8a8b2f 480/* Lexical macros. */
252b5132
RH		 481#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
482#define is_operand_char(x) (operand_chars[(unsigned char) x])
483#define is_register_char(x) (register_chars[(unsigned char) x])
484#define is_space_char(x) ((x) == ' ')
485#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
486#define is_digit_char(x) (digit_chars[(unsigned char) x])
487
0234cb7c 488/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 489static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
490
491/* md_assemble() always leaves the strings it's passed unaltered. To
492 effect this we maintain a stack of saved characters that we've smashed
493 with '\0's (indicating end of strings for various sub-fields of the
47926f60 494 assembler instruction). */
252b5132 495static char save_stack[32];
ce8a8b2f 496static char *save_stack_p;
252b5132
RH		 497#define END_STRING_AND_SAVE(s) \
498 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
499#define RESTORE_END_STRING(s) \
500 do { *(s) = *--save_stack_p; } while (0)
501
47926f60 502/* The instruction we're assembling. */
252b5132
RH		 503static i386_insn i;
504
505/* Possible templates for current insn. */
506static const templates *current_templates;
507
31b2323c
L		 508/* Per instruction expressionS buffers: max displacements & immediates. */
509static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
510static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 511
47926f60 512/* Current operand we are working on. */
ee86248c 513static int this_operand = -1;
252b5132 514
3e73aa7c
JH		 515/* We support four different modes. FLAG_CODE variable is used to distinguish
516 these. */
517
518enum flag_code {
519 CODE_32BIT,
520 CODE_16BIT,
521 CODE_64BIT };
522
523static enum flag_code flag_code;
4fa24527 524static unsigned int object_64bit;
862be3fb 525static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 526static int use_rela_relocations = 0;
527
7af8ed2d
NC		 528#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
529 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
531
351f65ca
L		 532/* The ELF ABI to use. */
533enum x86_elf_abi
534{
535 I386_ABI,
7f56bc95
L		 536 X86_64_ABI,
537 X86_64_X32_ABI
351f65ca
L		 538};
539
540static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 541#endif
351f65ca 542
167ad85b
TG		 543#if defined (TE_PE) || defined (TE_PEP)
544/* Use big object file format. */
545static int use_big_obj = 0;
546#endif
547
8dcea932
L		 548#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
549/* 1 if generating code for a shared library. */
550static int shared = 0;
551#endif
552
47926f60
KH		 553/* 1 for intel syntax,
554 0 if att syntax. */
555static int intel_syntax = 0;
252b5132 556
e89c5eaa
L		 557/* 1 for Intel64 ISA,
558 0 if AMD64 ISA. */
559static int intel64;
560
1efbbeb4
L		 561/* 1 for intel mnemonic,
562 0 if att mnemonic. */
563static int intel_mnemonic = !SYSV386_COMPAT;
564
5209009a 565/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 566static int old_gcc = OLDGCC_COMPAT;
567
a60de03c
JB		 568/* 1 if pseudo registers are permitted. */
569static int allow_pseudo_reg = 0;
570
47926f60
KH		 571/* 1 if register prefix % not required. */
572static int allow_naked_reg = 0;
252b5132 573
33eaf5de 574/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 575 instructions supporting it, even if this prefix wasn't specified
576 explicitly. */
577static int add_bnd_prefix = 0;
578
ba104c83 579/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 580static int allow_index_reg = 0;
581
d022bddd
IT		 582/* 1 if the assembler should ignore LOCK prefix, even if it was
583 specified explicitly. */
584static int omit_lock_prefix = 0;
585
e4e00185
AS		 586/* 1 if the assembler should encode lfence, mfence, and sfence as
587 "lock addl $0, (%{re}sp)". */
588static int avoid_fence = 0;
589
0cb4071e
L		 590/* 1 if the assembler should generate relax relocations. */
591
592static int generate_relax_relocations
593 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
594
7bab8ab5 595static enum check_kind
daf50ae7 596 {
7bab8ab5
JB		 597 check_none = 0,
598 check_warning,
599 check_error
daf50ae7 600 }
7bab8ab5 601sse_check, operand_check = check_warning;
daf50ae7 602
b6f8c7c4
L		 603/* Optimization:
604 1. Clear the REX_W bit with register operand if possible.
605 2. Above plus use 128bit vector instruction to clear the full vector
606 register.
607 */
608static int optimize = 0;
609
610/* Optimization:
611 1. Clear the REX_W bit with register operand if possible.
612 2. Above plus use 128bit vector instruction to clear the full vector
613 register.
614 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
615 "testb $imm7,%r8".
616 */
617static int optimize_for_space = 0;
618
2ca3ace5
L		 619/* Register prefix used for error message. */
620static const char *register_prefix = "%";
621
47926f60
KH		 622/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
623 leave, push, and pop instructions so that gcc has the same stack
624 frame as in 32 bit mode. */
625static char stackop_size = '\0';
eecb386c 626
12b55ccc
L		 627/* Non-zero to optimize code alignment. */
628int optimize_align_code = 1;
629
47926f60
KH		 630/* Non-zero to quieten some warnings. */
631static int quiet_warnings = 0;
a38cf1db 632
47926f60
KH		 633/* CPU name. */
634static const char *cpu_arch_name = NULL;
6305a203 635static char *cpu_sub_arch_name = NULL;
a38cf1db 636
47926f60 637/* CPU feature flags. */
40fb9820
L		 638static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
639
ccc9c027
L		 640/* If we have selected a cpu we are generating instructions for. */
641static int cpu_arch_tune_set = 0;
642
9103f4f4 643/* Cpu we are generating instructions for. */
fbf3f584 644enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 645
646/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 647static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 648
ccc9c027 649/* CPU instruction set architecture used. */
fbf3f584 650enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 651
9103f4f4 652/* CPU feature flags of instruction set architecture used. */
fbf3f584 653i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 654
fddf5b5b
AM		 655/* If set, conditional jumps are not automatically promoted to handle
656 larger than a byte offset. */
657static unsigned int no_cond_jump_promotion = 0;
658
c0f3af97
L		 659/* Encode SSE instructions with VEX prefix. */
660static unsigned int sse2avx;
661
539f890d
L		 662/* Encode scalar AVX instructions with specific vector length. */
663static enum
664 {
665 vex128 = 0,
666 vex256
667 } avxscalar;
668
43234a1e
L		 669/* Encode scalar EVEX LIG instructions with specific vector length. */
670static enum
671 {
672 evexl128 = 0,
673 evexl256,
674 evexl512
675 } evexlig;
676
677/* Encode EVEX WIG instructions with specific evex.w. */
678static enum
679 {
680 evexw0 = 0,
681 evexw1
682 } evexwig;
683
d3d3c6db
IT		 684/* Value to encode in EVEX RC bits, for SAE-only instructions. */
685static enum rc_type evexrcig = rne;
686
29b0f896 687/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 688static symbolS *GOT_symbol;
29b0f896 689
a4447b93
RH		 690/* The dwarf2 return column, adjusted for 32 or 64 bit. */
691unsigned int x86_dwarf2_return_column;
692
693/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
694int x86_cie_data_alignment;
695
252b5132 696/* Interface to relax_segment.
fddf5b5b
AM		 697 There are 3 major relax states for 386 jump insns because the
698 different types of jumps add different sizes to frags when we're
699 figuring out what sort of jump to choose to reach a given label. */
252b5132 700
47926f60 701/* Types. */
93c2a809
AM		 702#define UNCOND_JUMP 0
703#define COND_JUMP 1
704#define COND_JUMP86 2
fddf5b5b 705
47926f60 706/* Sizes. */
252b5132
RH		 707#define CODE16 1
708#define SMALL 0
29b0f896 709#define SMALL16 (SMALL | CODE16)
252b5132 710#define BIG 2
29b0f896 711#define BIG16 (BIG | CODE16)
252b5132
RH		 712
713#ifndef INLINE
714#ifdef __GNUC__
715#define INLINE __inline__
716#else
717#define INLINE
718#endif
719#endif
720
fddf5b5b
AM		 721#define ENCODE_RELAX_STATE(type, size) \
722 ((relax_substateT) (((type) << 2) | (size)))
723#define TYPE_FROM_RELAX_STATE(s) \
724 ((s) >> 2)
725#define DISP_SIZE_FROM_RELAX_STATE(s) \
726 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 727
728/* This table is used by relax_frag to promote short jumps to long
729 ones where necessary. SMALL (short) jumps may be promoted to BIG
730 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
731 don't allow a short jump in a 32 bit code segment to be promoted to
732 a 16 bit offset jump because it's slower (requires data size
733 prefix), and doesn't work, unless the destination is in the bottom
734 64k of the code segment (The top 16 bits of eip are zeroed). */
735
736const relax_typeS md_relax_table[] =
737{
24eab124
AM		 738 /* The fields are:
739 1) most positive reach of this state,
740 2) most negative reach of this state,
93c2a809 741 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 742 4) which index into the table to try if we can't fit into this one. */
252b5132 743
fddf5b5b 744 /* UNCOND_JUMP states. */
93c2a809
AM		 745 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
747 /* dword jmp adds 4 bytes to frag:
748 0 extra opcode bytes, 4 displacement bytes. */
252b5132 749 {0, 0, 4, 0},
93c2a809
AM		 750 /* word jmp adds 2 byte2 to frag:
751 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 752 {0, 0, 2, 0},
753
93c2a809
AM		 754 /* COND_JUMP states. */
755 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
756 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
757 /* dword conditionals adds 5 bytes to frag:
758 1 extra opcode byte, 4 displacement bytes. */
759 {0, 0, 5, 0},
fddf5b5b 760 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 761 1 extra opcode byte, 2 displacement bytes. */
762 {0, 0, 3, 0},
763
764 /* COND_JUMP86 states. */
765 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
766 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
767 /* dword conditionals adds 5 bytes to frag:
768 1 extra opcode byte, 4 displacement bytes. */
769 {0, 0, 5, 0},
770 /* word conditionals add 4 bytes to frag:
771 1 displacement byte and a 3 byte long branch insn. */
772 {0, 0, 4, 0}
252b5132
RH		 773};
774
9103f4f4
L		 775static const arch_entry cpu_arch[] =
776{
89507696
JB		 777 /* Do not replace the first two entries - i386_target_format()
778 relies on them being there in this order. */
8a2c8fef 779 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 780 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 782 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 784 CPU_NONE_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 786 CPU_I186_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 788 CPU_I286_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 790 CPU_I386_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 792 CPU_I486_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 794 CPU_I586_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 796 CPU_I686_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 798 CPU_I586_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 800 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 802 CPU_P2_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 804 CPU_P3_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 806 CPU_P4_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 808 CPU_CORE_FLAGS, 0 },
8a2c8fef 809 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 810 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 812 CPU_CORE_FLAGS, 1 },
8a2c8fef 813 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 814 CPU_CORE_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 816 CPU_CORE2_FLAGS, 1 },
8a2c8fef 817 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 818 CPU_CORE2_FLAGS, 0 },
8a2c8fef 819 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 820 CPU_COREI7_FLAGS, 0 },
8a2c8fef 821 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 822 CPU_L1OM_FLAGS, 0 },
7a9068fe 823 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 824 CPU_K1OM_FLAGS, 0 },
81486035 825 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 826 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 828 CPU_K6_FLAGS, 0 },
8a2c8fef 829 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 830 CPU_K6_2_FLAGS, 0 },
8a2c8fef 831 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 832 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 834 CPU_K8_FLAGS, 1 },
8a2c8fef 835 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 836 CPU_K8_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 838 CPU_K8_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 840 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 841 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 842 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 843 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 844 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 845 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 846 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 847 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 848 CPU_BDVER4_FLAGS, 0 },
029f3522 849 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 850 CPU_ZNVER1_FLAGS, 0 },
7b458c12 851 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 852 CPU_BTVER1_FLAGS, 0 },
7b458c12 853 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 854 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_8087_FLAGS, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_287_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_387_FLAGS, 0 },
1848e567
L		 861 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
862 CPU_687_FLAGS, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_MMX_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_SSE_FLAGS, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_SSE2_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SSE3_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AVX_FLAGS, 0 },
6c30d220 881 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_AVX2_FLAGS, 0 },
43234a1e 883 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_AVX512F_FLAGS, 0 },
43234a1e 885 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_AVX512CD_FLAGS, 0 },
43234a1e 887 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_AVX512ER_FLAGS, 0 },
43234a1e 889 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 893 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 895 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_VMX_FLAGS, 0 },
8729a6f6 899 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_SMX_FLAGS, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 905 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 907 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 909 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_AES_FLAGS, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 917 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 919 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 921 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_F16C_FLAGS, 0 },
6c30d220 923 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_BMI2_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_FMA_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_FMA4_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_XOP_FLAGS, 0 },
8a2c8fef 931 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_LWP_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_MOVBE_FLAGS, 0 },
60aa667e 935 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_CX16_FLAGS, 0 },
8a2c8fef 937 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_EPT_FLAGS, 0 },
6c30d220 939 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_LZCNT_FLAGS, 0 },
42164a71 941 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_HLE_FLAGS, 0 },
42164a71 943 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_RTM_FLAGS, 0 },
6c30d220 945 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_CLFLUSH_FLAGS, 0 },
22109423 949 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_NOP_FLAGS, 0 },
8a2c8fef 951 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 953 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 955 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 957 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 959 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 961 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SVME_FLAGS, 1 },
8a2c8fef 963 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_SVME_FLAGS, 0 },
8a2c8fef 965 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 967 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_ABM_FLAGS, 0 },
87973e9f 969 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_BMI_FLAGS, 0 },
2a2a0f38 971 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_TBM_FLAGS, 0 },
e2e1fcde 973 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_ADX_FLAGS, 0 },
e2e1fcde 975 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 977 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_PRFCHW_FLAGS, 0 },
5c111e37 979 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 980 CPU_SMAP_FLAGS, 0 },
7e8b059b 981 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 982 CPU_MPX_FLAGS, 0 },
a0046408 983 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 984 CPU_SHA_FLAGS, 0 },
963f3586 985 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 986 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 987 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 989 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_SE1_FLAGS, 0 },
c5e7287a 991 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 993 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 994 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 995 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 996 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 997 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 999 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 1001 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 1003 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1005 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1006 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1007 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1008 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1009 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1010 CPU_CLZERO_FLAGS, 0 },
9916071f 1011 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1012 CPU_MWAITX_FLAGS, 0 },
8eab4136 1013 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1014 CPU_OSPKE_FLAGS, 0 },
8bc52696 1015 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1016 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1017 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1018 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1019 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1020 CPU_IBT_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1022 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1023 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1024 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1025 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1026 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1027 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1028 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1029 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1030 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1031 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1032 CPU_PCONFIG_FLAGS, 0 },
293f5f65
L		 1033};
1034
1035static const noarch_entry cpu_noarch[] =
1036{
1037 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1038 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1039 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1040 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1041 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1042 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1043 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1045 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1046 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1047 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1048 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1049 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1050 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1051 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1060 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1061 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1062 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1063 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1064 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1065 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1066 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1067 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
e413e4e9
AM		 1068};
1069
704209c0 1070#ifdef I386COFF
a6c24e68
NC		 1071/* Like s_lcomm_internal in gas/read.c but the alignment string
1072 is allowed to be optional. */
1073
1074static symbolS *
1075pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1076{
1077 addressT align = 0;
1078
1079 SKIP_WHITESPACE ();
1080
7ab9ffdd 1081 if (needs_align
a6c24e68
NC		 1082 && *input_line_pointer == ',')
1083 {
1084 align = parse_align (needs_align - 1);
7ab9ffdd 1085
a6c24e68
NC		 1086 if (align == (addressT) -1)
1087 return NULL;
1088 }
1089 else
1090 {
1091 if (size >= 8)
1092 align = 3;
1093 else if (size >= 4)
1094 align = 2;
1095 else if (size >= 2)
1096 align = 1;
1097 else
1098 align = 0;
1099 }
1100
1101 bss_alloc (symbolP, size, align);
1102 return symbolP;
1103}
1104
704209c0 1105static void
a6c24e68
NC		 1106pe_lcomm (int needs_align)
1107{
1108 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1109}
704209c0 1110#endif
a6c24e68 1111
29b0f896
AM		 1112const pseudo_typeS md_pseudo_table[] =
1113{
1114#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1115 {"align", s_align_bytes, 0},
1116#else
1117 {"align", s_align_ptwo, 0},
1118#endif
1119 {"arch", set_cpu_arch, 0},
1120#ifndef I386COFF
1121 {"bss", s_bss, 0},
a6c24e68
NC		 1122#else
1123 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1124#endif
1125 {"ffloat", float_cons, 'f'},
1126 {"dfloat", float_cons, 'd'},
1127 {"tfloat", float_cons, 'x'},
1128 {"value", cons, 2},
d182319b 1129 {"slong", signed_cons, 4},
29b0f896
AM		 1130 {"noopt", s_ignore, 0},
1131 {"optim", s_ignore, 0},
1132 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1133 {"code16", set_code_flag, CODE_16BIT},
1134 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1135#ifdef BFD64
29b0f896 1136 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1137#endif
29b0f896
AM		 1138 {"intel_syntax", set_intel_syntax, 1},
1139 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1140 {"intel_mnemonic", set_intel_mnemonic, 1},
1141 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1142 {"allow_index_reg", set_allow_index_reg, 1},
1143 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1144 {"sse_check", set_check, 0},
1145 {"operand_check", set_check, 1},
3b22753a
L		 1146#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1147 {"largecomm", handle_large_common, 0},
07a53e5c 1148#else
68d20676 1149 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1150 {"loc", dwarf2_directive_loc, 0},
1151 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1152#endif
6482c264
NC		 1153#ifdef TE_PE
1154 {"secrel32", pe_directive_secrel, 0},
1155#endif
29b0f896
AM		 1156 {0, 0, 0}
1157};
1158
1159/* For interface with expression (). */
1160extern char *input_line_pointer;
1161
1162/* Hash table for instruction mnemonic lookup. */
1163static struct hash_control *op_hash;
1164
1165/* Hash table for register lookup. */
1166static struct hash_control *reg_hash;
1167\f
ce8a8b2f
AM		 1168 /* Various efficient no-op patterns for aligning code labels.
1169 Note: Don't try to assemble the instructions in the comments.
1170 0L and 0w are not legal. */
62a02d25
L		 1171static const unsigned char f32_1[] =
1172 {0x90}; /* nop */
1173static const unsigned char f32_2[] =
1174 {0x66,0x90}; /* xchg %ax,%ax */
1175static const unsigned char f32_3[] =
1176 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1177static const unsigned char f32_4[] =
1178 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1179static const unsigned char f32_6[] =
1180 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1181static const unsigned char f32_7[] =
1182 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1183static const unsigned char f16_3[] =
3ae729d5 1184 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1185static const unsigned char f16_4[] =
3ae729d5
L		 1186 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1187static const unsigned char jump_disp8[] =
1188 {0xeb}; /* jmp disp8 */
1189static const unsigned char jump32_disp32[] =
1190 {0xe9}; /* jmp disp32 */
1191static const unsigned char jump16_disp32[] =
1192 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1193/* 32-bit NOPs patterns. */
1194static const unsigned char *const f32_patt[] = {
3ae729d5 1195 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1196};
1197/* 16-bit NOPs patterns. */
1198static const unsigned char *const f16_patt[] = {
3ae729d5 1199 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1200};
1201/* nopl (%[re]ax) */
1202static const unsigned char alt_3[] =
1203 {0x0f,0x1f,0x00};
1204/* nopl 0(%[re]ax) */
1205static const unsigned char alt_4[] =
1206 {0x0f,0x1f,0x40,0x00};
1207/* nopl 0(%[re]ax,%[re]ax,1) */
1208static const unsigned char alt_5[] =
1209 {0x0f,0x1f,0x44,0x00,0x00};
1210/* nopw 0(%[re]ax,%[re]ax,1) */
1211static const unsigned char alt_6[] =
1212 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1213/* nopl 0L(%[re]ax) */
1214static const unsigned char alt_7[] =
1215 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1216/* nopl 0L(%[re]ax,%[re]ax,1) */
1217static const unsigned char alt_8[] =
1218 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219/* nopw 0L(%[re]ax,%[re]ax,1) */
1220static const unsigned char alt_9[] =
1221 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1223static const unsigned char alt_10[] =
1224 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1225/* data16 nopw %cs:0L(%eax,%eax,1) */
1226static const unsigned char alt_11[] =
1227 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1228/* 32-bit and 64-bit NOPs patterns. */
1229static const unsigned char *const alt_patt[] = {
1230 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1231 alt_9, alt_10, alt_11
62a02d25
L		 1232};
1233
1234/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1235 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1236
1237static void
1238i386_output_nops (char *where, const unsigned char *const *patt,
1239 int count, int max_single_nop_size)
1240
1241{
3ae729d5
L		 1242 /* Place the longer NOP first. */
1243 int last;
1244 int offset;
1245 const unsigned char *nops = patt[max_single_nop_size - 1];
1246
1247 /* Use the smaller one if the requsted one isn't available. */
1248 if (nops == NULL)
62a02d25 1249 {
3ae729d5
L		 1250 max_single_nop_size--;
1251 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1252 }
1253
3ae729d5
L		 1254 last = count % max_single_nop_size;
1255
1256 count -= last;
1257 for (offset = 0; offset < count; offset += max_single_nop_size)
1258 memcpy (where + offset, nops, max_single_nop_size);
1259
1260 if (last)
1261 {
1262 nops = patt[last - 1];
1263 if (nops == NULL)
1264 {
1265 /* Use the smaller one plus one-byte NOP if the needed one
1266 isn't available. */
1267 last--;
1268 nops = patt[last - 1];
1269 memcpy (where + offset, nops, last);
1270 where[offset + last] = *patt[0];
1271 }
1272 else
1273 memcpy (where + offset, nops, last);
1274 }
62a02d25
L		 1275}
1276
3ae729d5
L		 1277static INLINE int
1278fits_in_imm7 (offsetT num)
1279{
1280 return (num & 0x7f) == num;
1281}
1282
1283static INLINE int
1284fits_in_imm31 (offsetT num)
1285{
1286 return (num & 0x7fffffff) == num;
1287}
62a02d25
L		 1288
1289/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1290 single NOP instruction LIMIT. */
1291
1292void
3ae729d5 1293i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1294{
3ae729d5 1295 const unsigned char *const *patt = NULL;
62a02d25 1296 int max_single_nop_size;
3ae729d5
L		 1297 /* Maximum number of NOPs before switching to jump over NOPs. */
1298 int max_number_of_nops;
62a02d25 1299
3ae729d5 1300 switch (fragP->fr_type)
62a02d25 1301 {
3ae729d5
L		 1302 case rs_fill_nop:
1303 case rs_align_code:
1304 break;
1305 default:
62a02d25
L		 1306 return;
1307 }
1308
ccc9c027
L		 1309 /* We need to decide which NOP sequence to use for 32bit and
1310 64bit. When -mtune= is used:
4eed87de 1311
76bc74dc
L		 1312 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1313 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1314 2. For the rest, alt_patt will be used.
1315
1316 When -mtune= isn't used, alt_patt will be used if
22109423 1317 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1318 be used.
ccc9c027
L		 1319
1320 When -march= or .arch is used, we can't use anything beyond
1321 cpu_arch_isa_flags. */
1322
1323 if (flag_code == CODE_16BIT)
1324 {
3ae729d5
L		 1325 patt = f16_patt;
1326 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1327 /* Limit number of NOPs to 2 in 16-bit mode. */
1328 max_number_of_nops = 2;
252b5132 1329 }
33fef721 1330 else
ccc9c027 1331 {
fbf3f584 1332 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1333 {
1334 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1335 switch (cpu_arch_tune)
1336 {
1337 case PROCESSOR_UNKNOWN:
1338 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1339 optimize with nops. */
1340 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1341 patt = alt_patt;
ccc9c027
L		 1342 else
1343 patt = f32_patt;
1344 break;
ccc9c027
L		 1345 case PROCESSOR_PENTIUM4:
1346 case PROCESSOR_NOCONA:
ef05d495 1347 case PROCESSOR_CORE:
76bc74dc 1348 case PROCESSOR_CORE2:
bd5295b2 1349 case PROCESSOR_COREI7:
3632d14b 1350 case PROCESSOR_L1OM:
7a9068fe 1351 case PROCESSOR_K1OM:
76bc74dc 1352 case PROCESSOR_GENERIC64:
ccc9c027
L		 1353 case PROCESSOR_K6:
1354 case PROCESSOR_ATHLON:
1355 case PROCESSOR_K8:
4eed87de 1356 case PROCESSOR_AMDFAM10:
8aedb9fe 1357 case PROCESSOR_BD:
029f3522 1358 case PROCESSOR_ZNVER:
7b458c12 1359 case PROCESSOR_BT:
80b8656c 1360 patt = alt_patt;
ccc9c027 1361 break;
76bc74dc 1362 case PROCESSOR_I386:
ccc9c027
L		 1363 case PROCESSOR_I486:
1364 case PROCESSOR_PENTIUM:
2dde1948 1365 case PROCESSOR_PENTIUMPRO:
81486035 1366 case PROCESSOR_IAMCU:
ccc9c027
L		 1367 case PROCESSOR_GENERIC32:
1368 patt = f32_patt;
1369 break;
4eed87de 1370 }
ccc9c027
L		 1371 }
1372 else
1373 {
fbf3f584 1374 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1375 {
1376 case PROCESSOR_UNKNOWN:
e6a14101 1377 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1378 PROCESSOR_UNKNOWN. */
1379 abort ();
1380 break;
1381
76bc74dc 1382 case PROCESSOR_I386:
ccc9c027
L		 1383 case PROCESSOR_I486:
1384 case PROCESSOR_PENTIUM:
81486035 1385 case PROCESSOR_IAMCU:
ccc9c027
L		 1386 case PROCESSOR_K6:
1387 case PROCESSOR_ATHLON:
1388 case PROCESSOR_K8:
4eed87de 1389 case PROCESSOR_AMDFAM10:
8aedb9fe 1390 case PROCESSOR_BD:
029f3522 1391 case PROCESSOR_ZNVER:
7b458c12 1392 case PROCESSOR_BT:
ccc9c027
L		 1393 case PROCESSOR_GENERIC32:
1394 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1395 with nops. */
1396 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1397 patt = alt_patt;
ccc9c027
L		 1398 else
1399 patt = f32_patt;
1400 break;
76bc74dc
L		 1401 case PROCESSOR_PENTIUMPRO:
1402 case PROCESSOR_PENTIUM4:
1403 case PROCESSOR_NOCONA:
1404 case PROCESSOR_CORE:
ef05d495 1405 case PROCESSOR_CORE2:
bd5295b2 1406 case PROCESSOR_COREI7:
3632d14b 1407 case PROCESSOR_L1OM:
7a9068fe 1408 case PROCESSOR_K1OM:
22109423 1409 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1410 patt = alt_patt;
ccc9c027
L		 1411 else
1412 patt = f32_patt;
1413 break;
1414 case PROCESSOR_GENERIC64:
80b8656c 1415 patt = alt_patt;
ccc9c027 1416 break;
4eed87de 1417 }
ccc9c027
L		 1418 }
1419
76bc74dc
L		 1420 if (patt == f32_patt)
1421 {
3ae729d5
L		 1422 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1423 /* Limit number of NOPs to 2 for older processors. */
1424 max_number_of_nops = 2;
76bc74dc
L		 1425 }
1426 else
1427 {
3ae729d5
L		 1428 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1429 /* Limit number of NOPs to 7 for newer processors. */
1430 max_number_of_nops = 7;
1431 }
1432 }
1433
1434 if (limit == 0)
1435 limit = max_single_nop_size;
1436
1437 if (fragP->fr_type == rs_fill_nop)
1438 {
1439 /* Output NOPs for .nop directive. */
1440 if (limit > max_single_nop_size)
1441 {
1442 as_bad_where (fragP->fr_file, fragP->fr_line,
1443 _("invalid single nop size: %d "
1444 "(expect within [0, %d])"),
1445 limit, max_single_nop_size);
1446 return;
1447 }
1448 }
1449 else
1450 fragP->fr_var = count;
1451
1452 if ((count / max_single_nop_size) > max_number_of_nops)
1453 {
1454 /* Generate jump over NOPs. */
1455 offsetT disp = count - 2;
1456 if (fits_in_imm7 (disp))
1457 {
1458 /* Use "jmp disp8" if possible. */
1459 count = disp;
1460 where[0] = jump_disp8[0];
1461 where[1] = count;
1462 where += 2;
1463 }
1464 else
1465 {
1466 unsigned int size_of_jump;
1467
1468 if (flag_code == CODE_16BIT)
1469 {
1470 where[0] = jump16_disp32[0];
1471 where[1] = jump16_disp32[1];
1472 size_of_jump = 2;
1473 }
1474 else
1475 {
1476 where[0] = jump32_disp32[0];
1477 size_of_jump = 1;
1478 }
1479
1480 count -= size_of_jump + 4;
1481 if (!fits_in_imm31 (count))
1482 {
1483 as_bad_where (fragP->fr_file, fragP->fr_line,
1484 _("jump over nop padding out of range"));
1485 return;
1486 }
1487
1488 md_number_to_chars (where + size_of_jump, count, 4);
1489 where += size_of_jump + 4;
76bc74dc 1490 }
ccc9c027 1491 }
3ae729d5
L		 1492
1493 /* Generate multiple NOPs. */
1494 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1495}
1496
c6fb90c8 1497static INLINE int
0dfbf9d7 1498operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1499{
0dfbf9d7 1500 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1501 {
1502 case 3:
0dfbf9d7 1503 if (x->array[2])
c6fb90c8 1504 return 0;
1a0670f3 1505 /* Fall through. */
c6fb90c8 1506 case 2:
0dfbf9d7 1507 if (x->array[1])
c6fb90c8 1508 return 0;
1a0670f3 1509 /* Fall through. */
c6fb90c8 1510 case 1:
0dfbf9d7 1511 return !x->array[0];
c6fb90c8
L		 1512 default:
1513 abort ();
1514 }
40fb9820
L		 1515}
1516
c6fb90c8 1517static INLINE void
0dfbf9d7 1518operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1519{
0dfbf9d7 1520 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1521 {
1522 case 3:
0dfbf9d7 1523 x->array[2] = v;
1a0670f3 1524 /* Fall through. */
c6fb90c8 1525 case 2:
0dfbf9d7 1526 x->array[1] = v;
1a0670f3 1527 /* Fall through. */
c6fb90c8 1528 case 1:
0dfbf9d7 1529 x->array[0] = v;
1a0670f3 1530 /* Fall through. */
c6fb90c8
L		 1531 break;
1532 default:
1533 abort ();
1534 }
1535}
40fb9820 1536
c6fb90c8 1537static INLINE int
0dfbf9d7
L		 1538operand_type_equal (const union i386_operand_type *x,
1539 const union i386_operand_type *y)
c6fb90c8 1540{
0dfbf9d7 1541 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1542 {
1543 case 3:
0dfbf9d7 1544 if (x->array[2] != y->array[2])
c6fb90c8 1545 return 0;
1a0670f3 1546 /* Fall through. */
c6fb90c8 1547 case 2:
0dfbf9d7 1548 if (x->array[1] != y->array[1])
c6fb90c8 1549 return 0;
1a0670f3 1550 /* Fall through. */
c6fb90c8 1551 case 1:
0dfbf9d7 1552 return x->array[0] == y->array[0];
c6fb90c8
L		 1553 break;
1554 default:
1555 abort ();
1556 }
1557}
40fb9820 1558
0dfbf9d7
L		 1559static INLINE int
1560cpu_flags_all_zero (const union i386_cpu_flags *x)
1561{
1562 switch (ARRAY_SIZE(x->array))
1563 {
53467f57
IT		 1564 case 4:
1565 if (x->array[3])
1566 return 0;
1567 /* Fall through. */
0dfbf9d7
L		 1568 case 3:
1569 if (x->array[2])
1570 return 0;
1a0670f3 1571 /* Fall through. */
0dfbf9d7
L		 1572 case 2:
1573 if (x->array[1])
1574 return 0;
1a0670f3 1575 /* Fall through. */
0dfbf9d7
L		 1576 case 1:
1577 return !x->array[0];
1578 default:
1579 abort ();
1580 }
1581}
1582
0dfbf9d7
L		 1583static INLINE int
1584cpu_flags_equal (const union i386_cpu_flags *x,
1585 const union i386_cpu_flags *y)
1586{
1587 switch (ARRAY_SIZE(x->array))
1588 {
53467f57
IT		 1589 case 4:
1590 if (x->array[3] != y->array[3])
1591 return 0;
1592 /* Fall through. */
0dfbf9d7
L		 1593 case 3:
1594 if (x->array[2] != y->array[2])
1595 return 0;
1a0670f3 1596 /* Fall through. */
0dfbf9d7
L		 1597 case 2:
1598 if (x->array[1] != y->array[1])
1599 return 0;
1a0670f3 1600 /* Fall through. */
0dfbf9d7
L		 1601 case 1:
1602 return x->array[0] == y->array[0];
1603 break;
1604 default:
1605 abort ();
1606 }
1607}
c6fb90c8
L		 1608
1609static INLINE int
1610cpu_flags_check_cpu64 (i386_cpu_flags f)
1611{
1612 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1613 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1614}
1615
c6fb90c8
L		 1616static INLINE i386_cpu_flags
1617cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1618{
c6fb90c8
L		 1619 switch (ARRAY_SIZE (x.array))
1620 {
53467f57
IT		 1621 case 4:
1622 x.array [3] &= y.array [3];
1623 /* Fall through. */
c6fb90c8
L		 1624 case 3:
1625 x.array [2] &= y.array [2];
1a0670f3 1626 /* Fall through. */
c6fb90c8
L		 1627 case 2:
1628 x.array [1] &= y.array [1];
1a0670f3 1629 /* Fall through. */
c6fb90c8
L		 1630 case 1:
1631 x.array [0] &= y.array [0];
1632 break;
1633 default:
1634 abort ();
1635 }
1636 return x;
1637}
40fb9820 1638
c6fb90c8
L		 1639static INLINE i386_cpu_flags
1640cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1641{
c6fb90c8 1642 switch (ARRAY_SIZE (x.array))
40fb9820 1643 {
53467f57
IT		 1644 case 4:
1645 x.array [3] |= y.array [3];
1646 /* Fall through. */
c6fb90c8
L		 1647 case 3:
1648 x.array [2] |= y.array [2];
1a0670f3 1649 /* Fall through. */
c6fb90c8
L		 1650 case 2:
1651 x.array [1] |= y.array [1];
1a0670f3 1652 /* Fall through. */
c6fb90c8
L		 1653 case 1:
1654 x.array [0] |= y.array [0];
40fb9820
L		 1655 break;
1656 default:
1657 abort ();
1658 }
40fb9820
L		 1659 return x;
1660}
1661
309d3373
JB		 1662static INLINE i386_cpu_flags
1663cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1664{
1665 switch (ARRAY_SIZE (x.array))
1666 {
53467f57
IT		 1667 case 4:
1668 x.array [3] &= ~y.array [3];
1669 /* Fall through. */
309d3373
JB		 1670 case 3:
1671 x.array [2] &= ~y.array [2];
1a0670f3 1672 /* Fall through. */
309d3373
JB		 1673 case 2:
1674 x.array [1] &= ~y.array [1];
1a0670f3 1675 /* Fall through. */
309d3373
JB		 1676 case 1:
1677 x.array [0] &= ~y.array [0];
1678 break;
1679 default:
1680 abort ();
1681 }
1682 return x;
1683}
1684
c0f3af97
L		 1685#define CPU_FLAGS_ARCH_MATCH 0x1
1686#define CPU_FLAGS_64BIT_MATCH 0x2
1687
c0f3af97 1688#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1689 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1690
1691/* Return CPU flags match bits. */
3629bb00 1692
40fb9820 1693static int
d3ce72d0 1694cpu_flags_match (const insn_template *t)
40fb9820 1695{
c0f3af97
L		 1696 i386_cpu_flags x = t->cpu_flags;
1697 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1698
1699 x.bitfield.cpu64 = 0;
1700 x.bitfield.cpuno64 = 0;
1701
0dfbf9d7 1702 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1703 {
1704 /* This instruction is available on all archs. */
db12e14e 1705 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1706 }
3629bb00
L		 1707 else
1708 {
c0f3af97 1709 /* This instruction is available only on some archs. */
3629bb00
L		 1710 i386_cpu_flags cpu = cpu_arch_flags;
1711
ab592e75
JB		 1712 /* AVX512VL is no standalone feature - match it and then strip it. */
1713 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1714 return match;
1715 x.bitfield.cpuavx512vl = 0;
1716
3629bb00 1717 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1718 if (!cpu_flags_all_zero (&cpu))
1719 {
a5ff0eb2
L		 1720 if (x.bitfield.cpuavx)
1721 {
929f69fa 1722 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1723 if (cpu.bitfield.cpuavx
1724 && (!t->opcode_modifier.sse2avx || sse2avx)
1725 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1726 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1727 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1728 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1729 }
929f69fa
JB		 1730 else if (x.bitfield.cpuavx512f)
1731 {
1732 /* We need to check a few extra flags with AVX512F. */
1733 if (cpu.bitfield.cpuavx512f
1734 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1735 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1736 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1737 match |= CPU_FLAGS_ARCH_MATCH;
1738 }
a5ff0eb2 1739 else
db12e14e 1740 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1741 }
3629bb00 1742 }
c0f3af97 1743 return match;
40fb9820
L		 1744}
1745
c6fb90c8
L		 1746static INLINE i386_operand_type
1747operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1748{
c6fb90c8
L		 1749 switch (ARRAY_SIZE (x.array))
1750 {
1751 case 3:
1752 x.array [2] &= y.array [2];
1a0670f3 1753 /* Fall through. */
c6fb90c8
L		 1754 case 2:
1755 x.array [1] &= y.array [1];
1a0670f3 1756 /* Fall through. */
c6fb90c8
L		 1757 case 1:
1758 x.array [0] &= y.array [0];
1759 break;
1760 default:
1761 abort ();
1762 }
1763 return x;
40fb9820
L		 1764}
1765
73053c1f
JB		 1766static INLINE i386_operand_type
1767operand_type_and_not (i386_operand_type x, i386_operand_type y)
1768{
1769 switch (ARRAY_SIZE (x.array))
1770 {
1771 case 3:
1772 x.array [2] &= ~y.array [2];
1773 /* Fall through. */
1774 case 2:
1775 x.array [1] &= ~y.array [1];
1776 /* Fall through. */
1777 case 1:
1778 x.array [0] &= ~y.array [0];
1779 break;
1780 default:
1781 abort ();
1782 }
1783 return x;
1784}
1785
c6fb90c8
L		 1786static INLINE i386_operand_type
1787operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1788{
c6fb90c8 1789 switch (ARRAY_SIZE (x.array))
40fb9820 1790 {
c6fb90c8
L		 1791 case 3:
1792 x.array [2] |= y.array [2];
1a0670f3 1793 /* Fall through. */
c6fb90c8
L		 1794 case 2:
1795 x.array [1] |= y.array [1];
1a0670f3 1796 /* Fall through. */
c6fb90c8
L		 1797 case 1:
1798 x.array [0] |= y.array [0];
40fb9820
L		 1799 break;
1800 default:
1801 abort ();
1802 }
c6fb90c8
L		 1803 return x;
1804}
40fb9820 1805
c6fb90c8
L		 1806static INLINE i386_operand_type
1807operand_type_xor (i386_operand_type x, i386_operand_type y)
1808{
1809 switch (ARRAY_SIZE (x.array))
1810 {
1811 case 3:
1812 x.array [2] ^= y.array [2];
1a0670f3 1813 /* Fall through. */
c6fb90c8
L		 1814 case 2:
1815 x.array [1] ^= y.array [1];
1a0670f3 1816 /* Fall through. */
c6fb90c8
L		 1817 case 1:
1818 x.array [0] ^= y.array [0];
1819 break;
1820 default:
1821 abort ();
1822 }
40fb9820
L		 1823 return x;
1824}
1825
1826static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1827static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1828static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1829static const i386_operand_type inoutportreg
1830 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1831static const i386_operand_type reg16_inoutportreg
1832 = OPERAND_TYPE_REG16_INOUTPORTREG;
1833static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1834static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1835static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1836static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1837static const i386_operand_type anydisp
1838 = OPERAND_TYPE_ANYDISP;
40fb9820 1839static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1840static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1841static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1842static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1843static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1844static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1845static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1846static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1847static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1848static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1849static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1850static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1851
1852enum operand_type
1853{
1854 reg,
40fb9820
L		 1855 imm,
1856 disp,
1857 anymem
1858};
1859
c6fb90c8 1860static INLINE int
40fb9820
L		 1861operand_type_check (i386_operand_type t, enum operand_type c)
1862{
1863 switch (c)
1864 {
1865 case reg:
dc821c5f 1866 return t.bitfield.reg;
40fb9820 1867
40fb9820
L		 1868 case imm:
1869 return (t.bitfield.imm8
1870 || t.bitfield.imm8s
1871 || t.bitfield.imm16
1872 || t.bitfield.imm32
1873 || t.bitfield.imm32s
1874 || t.bitfield.imm64);
1875
1876 case disp:
1877 return (t.bitfield.disp8
1878 || t.bitfield.disp16
1879 || t.bitfield.disp32
1880 || t.bitfield.disp32s
1881 || t.bitfield.disp64);
1882
1883 case anymem:
1884 return (t.bitfield.disp8
1885 || t.bitfield.disp16
1886 || t.bitfield.disp32
1887 || t.bitfield.disp32s
1888 || t.bitfield.disp64
1889 || t.bitfield.baseindex);
1890
1891 default:
1892 abort ();
1893 }
2cfe26b6
AM		 1894
1895 return 0;
40fb9820
L		 1896}
1897
ca0d63fe 1898/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1899 operand J for instruction template T. */
1900
1901static INLINE int
d3ce72d0 1902match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1903{
1904 return !((i.types[j].bitfield.byte
1905 && !t->operand_types[j].bitfield.byte)
1906 || (i.types[j].bitfield.word
1907 && !t->operand_types[j].bitfield.word)
1908 || (i.types[j].bitfield.dword
1909 && !t->operand_types[j].bitfield.dword)
1910 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1911 && !t->operand_types[j].bitfield.qword)
1912 || (i.types[j].bitfield.tbyte
1913 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1914}
1915
1b54b8d7
JB		 1916/* Return 1 if there is no conflict in SIMD register on
1917 operand J for instruction template T. */
1918
1919static INLINE int
1920match_simd_size (const insn_template *t, unsigned int j)
1921{
1922 return !((i.types[j].bitfield.xmmword
1923 && !t->operand_types[j].bitfield.xmmword)
1924 || (i.types[j].bitfield.ymmword
1925 && !t->operand_types[j].bitfield.ymmword)
1926 || (i.types[j].bitfield.zmmword
1927 && !t->operand_types[j].bitfield.zmmword));
1928}
1929
5c07affc
L		 1930/* Return 1 if there is no conflict in any size on operand J for
1931 instruction template T. */
1932
1933static INLINE int
d3ce72d0 1934match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1935{
1936 return (match_reg_size (t, j)
1937 && !((i.types[j].bitfield.unspecified
af508cb9 1938 && !i.broadcast
5c07affc
L		 1939 && !t->operand_types[j].bitfield.unspecified)
1940 || (i.types[j].bitfield.fword
1941 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1942 /* For scalar opcode templates to allow register and memory
1943 operands at the same time, some special casing is needed
1944 here. */
1945 || ((t->operand_types[j].bitfield.regsimd
1946 && !t->opcode_modifier.broadcast
1947 && (t->operand_types[j].bitfield.dword
1948 || t->operand_types[j].bitfield.qword))
1949 ? (i.types[j].bitfield.xmmword
1950 || i.types[j].bitfield.ymmword
1951 || i.types[j].bitfield.zmmword)
1952 : !match_simd_size(t, j))));
5c07affc
L		 1953}
1954
1955/* Return 1 if there is no size conflict on any operands for
1956 instruction template T. */
1957
1958static INLINE int
d3ce72d0 1959operand_size_match (const insn_template *t)
5c07affc
L		 1960{
1961 unsigned int j;
1962 int match = 1;
1963
1964 /* Don't check jump instructions. */
1965 if (t->opcode_modifier.jump
1966 || t->opcode_modifier.jumpbyte
1967 || t->opcode_modifier.jumpdword
1968 || t->opcode_modifier.jumpintersegment)
1969 return match;
1970
1971 /* Check memory and accumulator operand size. */
1972 for (j = 0; j < i.operands; j++)
1973 {
1b54b8d7
JB		 1974 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1975 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1976 continue;
1977
1b54b8d7 1978 if (t->operand_types[j].bitfield.reg
dc821c5f 1979 && !match_reg_size (t, j))
5c07affc
L		 1980 {
1981 match = 0;
1982 break;
1983 }
1984
1b54b8d7
JB		 1985 if (t->operand_types[j].bitfield.regsimd
1986 && !match_simd_size (t, j))
1987 {
1988 match = 0;
1989 break;
1990 }
1991
1992 if (t->operand_types[j].bitfield.acc
1993 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1994 {
1995 match = 0;
1996 break;
1997 }
1998
5c07affc
L		 1999 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2000 {
2001 match = 0;
2002 break;
2003 }
2004 }
2005
891edac4 2006 if (match)
5c07affc 2007 return match;
38e314eb 2008 else if (!t->opcode_modifier.d)
891edac4
L		 2009 {
2010mismatch:
86e026a4 2011 i.error = operand_size_mismatch;
891edac4
L		 2012 return 0;
2013 }
5c07affc
L		 2014
2015 /* Check reverse. */
9c2799c2 2016 gas_assert (i.operands == 2);
5c07affc
L		 2017
2018 match = 1;
2019 for (j = 0; j < 2; j++)
2020 {
dc821c5f
JB		 2021 if ((t->operand_types[j].bitfield.reg
2022 || t->operand_types[j].bitfield.acc)
5c07affc 2023 && !match_reg_size (t, j ? 0 : 1))
891edac4 2024 goto mismatch;
5c07affc
L		 2025
2026 if (i.types[j].bitfield.mem
2027 && !match_mem_size (t, j ? 0 : 1))
891edac4 2028 goto mismatch;
5c07affc
L		 2029 }
2030
2031 return match;
2032}
2033
c6fb90c8 2034static INLINE int
40fb9820
L		 2035operand_type_match (i386_operand_type overlap,
2036 i386_operand_type given)
2037{
2038 i386_operand_type temp = overlap;
2039
2040 temp.bitfield.jumpabsolute = 0;
7d5e4556 2041 temp.bitfield.unspecified = 0;
5c07affc
L		 2042 temp.bitfield.byte = 0;
2043 temp.bitfield.word = 0;
2044 temp.bitfield.dword = 0;
2045 temp.bitfield.fword = 0;
2046 temp.bitfield.qword = 0;
2047 temp.bitfield.tbyte = 0;
2048 temp.bitfield.xmmword = 0;
c0f3af97 2049 temp.bitfield.ymmword = 0;
43234a1e 2050 temp.bitfield.zmmword = 0;
0dfbf9d7 2051 if (operand_type_all_zero (&temp))
891edac4 2052 goto mismatch;
40fb9820 2053
891edac4
L		 2054 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2055 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2056 return 1;
2057
2058mismatch:
a65babc9 2059 i.error = operand_type_mismatch;
891edac4 2060 return 0;
40fb9820
L		 2061}
2062
7d5e4556 2063/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2064 unless the expected operand type register overlap is null.
2065 Memory operand size of certain SIMD instructions is also being checked
2066 here. */
40fb9820 2067
c6fb90c8 2068static INLINE int
dc821c5f 2069operand_type_register_match (i386_operand_type g0,
40fb9820 2070 i386_operand_type t0,
40fb9820
L		 2071 i386_operand_type g1,
2072 i386_operand_type t1)
2073{
10c17abd
JB		 2074 if (!g0.bitfield.reg
2075 && !g0.bitfield.regsimd
2076 && (!operand_type_check (g0, anymem)
2077 || g0.bitfield.unspecified
2078 || !t0.bitfield.regsimd))
40fb9820
L		 2079 return 1;
2080
10c17abd
JB		 2081 if (!g1.bitfield.reg
2082 && !g1.bitfield.regsimd
2083 && (!operand_type_check (g1, anymem)
2084 || g1.bitfield.unspecified
2085 || !t1.bitfield.regsimd))
40fb9820
L		 2086 return 1;
2087
dc821c5f
JB		 2088 if (g0.bitfield.byte == g1.bitfield.byte
2089 && g0.bitfield.word == g1.bitfield.word
2090 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2091 && g0.bitfield.qword == g1.bitfield.qword
2092 && g0.bitfield.xmmword == g1.bitfield.xmmword
2093 && g0.bitfield.ymmword == g1.bitfield.ymmword
2094 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2095 return 1;
2096
dc821c5f
JB		 2097 if (!(t0.bitfield.byte & t1.bitfield.byte)
2098 && !(t0.bitfield.word & t1.bitfield.word)
2099 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2100 && !(t0.bitfield.qword & t1.bitfield.qword)
2101 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2102 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2103 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2104 return 1;
2105
a65babc9 2106 i.error = register_type_mismatch;
891edac4
L		 2107
2108 return 0;
40fb9820
L		 2109}
2110
4c692bc7
JB		 2111static INLINE unsigned int
2112register_number (const reg_entry *r)
2113{
2114 unsigned int nr = r->reg_num;
2115
2116 if (r->reg_flags & RegRex)
2117 nr += 8;
2118
200cbe0f
L		 2119 if (r->reg_flags & RegVRex)
2120 nr += 16;
2121
4c692bc7
JB		 2122 return nr;
2123}
2124
252b5132 2125static INLINE unsigned int
40fb9820 2126mode_from_disp_size (i386_operand_type t)
252b5132 2127{
b5014f7a 2128 if (t.bitfield.disp8)
40fb9820
L		 2129 return 1;
2130 else if (t.bitfield.disp16
2131 || t.bitfield.disp32
2132 || t.bitfield.disp32s)
2133 return 2;
2134 else
2135 return 0;
252b5132
RH		 2136}
2137
2138static INLINE int
65879393 2139fits_in_signed_byte (addressT num)
252b5132 2140{
65879393 2141 return num + 0x80 <= 0xff;
47926f60 2142}
252b5132
RH		 2143
2144static INLINE int
65879393 2145fits_in_unsigned_byte (addressT num)
252b5132 2146{
65879393 2147 return num <= 0xff;
47926f60 2148}
252b5132
RH		 2149
2150static INLINE int
65879393 2151fits_in_unsigned_word (addressT num)
252b5132 2152{
65879393 2153 return num <= 0xffff;
47926f60 2154}
252b5132
RH		 2155
2156static INLINE int
65879393 2157fits_in_signed_word (addressT num)
252b5132 2158{
65879393 2159 return num + 0x8000 <= 0xffff;
47926f60 2160}
2a962e6d 2161
3e73aa7c 2162static INLINE int
65879393 2163fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2164{
2165#ifndef BFD64
2166 return 1;
2167#else
65879393 2168 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2169#endif
2170} /* fits_in_signed_long() */
2a962e6d 2171
3e73aa7c 2172static INLINE int
65879393 2173fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2174{
2175#ifndef BFD64
2176 return 1;
2177#else
65879393 2178 return num <= 0xffffffff;
3e73aa7c
JH		 2179#endif
2180} /* fits_in_unsigned_long() */
252b5132 2181
43234a1e 2182static INLINE int
b5014f7a 2183fits_in_disp8 (offsetT num)
43234a1e
L		 2184{
2185 int shift = i.memshift;
2186 unsigned int mask;
2187
2188 if (shift == -1)
2189 abort ();
2190
2191 mask = (1 << shift) - 1;
2192
2193 /* Return 0 if NUM isn't properly aligned. */
2194 if ((num & mask))
2195 return 0;
2196
2197 /* Check if NUM will fit in 8bit after shift. */
2198 return fits_in_signed_byte (num >> shift);
2199}
2200
a683cc34
SP		 2201static INLINE int
2202fits_in_imm4 (offsetT num)
2203{
2204 return (num & 0xf) == num;
2205}
2206
40fb9820 2207static i386_operand_type
e3bb37b5 2208smallest_imm_type (offsetT num)
252b5132 2209{
40fb9820 2210 i386_operand_type t;
7ab9ffdd 2211
0dfbf9d7 2212 operand_type_set (&t, 0);
40fb9820
L		 2213 t.bitfield.imm64 = 1;
2214
2215 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2216 {
2217 /* This code is disabled on the 486 because all the Imm1 forms
2218 in the opcode table are slower on the i486. They're the
2219 versions with the implicitly specified single-position
2220 displacement, which has another syntax if you really want to
2221 use that form. */
40fb9820
L		 2222 t.bitfield.imm1 = 1;
2223 t.bitfield.imm8 = 1;
2224 t.bitfield.imm8s = 1;
2225 t.bitfield.imm16 = 1;
2226 t.bitfield.imm32 = 1;
2227 t.bitfield.imm32s = 1;
2228 }
2229 else if (fits_in_signed_byte (num))
2230 {
2231 t.bitfield.imm8 = 1;
2232 t.bitfield.imm8s = 1;
2233 t.bitfield.imm16 = 1;
2234 t.bitfield.imm32 = 1;
2235 t.bitfield.imm32s = 1;
2236 }
2237 else if (fits_in_unsigned_byte (num))
2238 {
2239 t.bitfield.imm8 = 1;
2240 t.bitfield.imm16 = 1;
2241 t.bitfield.imm32 = 1;
2242 t.bitfield.imm32s = 1;
2243 }
2244 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2245 {
2246 t.bitfield.imm16 = 1;
2247 t.bitfield.imm32 = 1;
2248 t.bitfield.imm32s = 1;
2249 }
2250 else if (fits_in_signed_long (num))
2251 {
2252 t.bitfield.imm32 = 1;
2253 t.bitfield.imm32s = 1;
2254 }
2255 else if (fits_in_unsigned_long (num))
2256 t.bitfield.imm32 = 1;
2257
2258 return t;
47926f60 2259}
252b5132 2260
847f7ad4 2261static offsetT
e3bb37b5 2262offset_in_range (offsetT val, int size)
847f7ad4 2263{
508866be 2264 addressT mask;
ba2adb93 2265
847f7ad4
AM		 2266 switch (size)
2267 {
508866be
L		 2268 case 1: mask = ((addressT) 1 << 8) - 1; break;
2269 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2270 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2271#ifdef BFD64
2272 case 8: mask = ((addressT) 2 << 63) - 1; break;
2273#endif
47926f60 2274 default: abort ();
847f7ad4
AM		 2275 }
2276
9de868bf
L		 2277#ifdef BFD64
2278 /* If BFD64, sign extend val for 32bit address mode. */
2279 if (flag_code != CODE_64BIT
2280 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2281 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2282 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2283#endif
ba2adb93 2284
47926f60 2285 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2286 {
2287 char buf1[40], buf2[40];
2288
2289 sprint_value (buf1, val);
2290 sprint_value (buf2, val & mask);
2291 as_warn (_("%s shortened to %s"), buf1, buf2);
2292 }
2293 return val & mask;
2294}
2295
c32fa91d
L		 2296enum PREFIX_GROUP
2297{
2298 PREFIX_EXIST = 0,
2299 PREFIX_LOCK,
2300 PREFIX_REP,
04ef582a 2301 PREFIX_DS,
c32fa91d
L		 2302 PREFIX_OTHER
2303};
2304
2305/* Returns
2306 a. PREFIX_EXIST if attempting to add a prefix where one from the
2307 same class already exists.
2308 b. PREFIX_LOCK if lock prefix is added.
2309 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2310 d. PREFIX_DS if ds prefix is added.
2311 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2312 */
2313
2314static enum PREFIX_GROUP
e3bb37b5 2315add_prefix (unsigned int prefix)
252b5132 2316{
c32fa91d 2317 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2318 unsigned int q;
252b5132 2319
29b0f896
AM		 2320 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2321 && flag_code == CODE_64BIT)
b1905489 2322 {
161a04f6
L		 2323 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2324 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2325 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2326 ret = PREFIX_EXIST;
b1905489
JB		 2327 q = REX_PREFIX;
2328 }
3e73aa7c 2329 else
b1905489
JB		 2330 {
2331 switch (prefix)
2332 {
2333 default:
2334 abort ();
2335
b1905489 2336 case DS_PREFIX_OPCODE:
04ef582a
L		 2337 ret = PREFIX_DS;
2338 /* Fall through. */
2339 case CS_PREFIX_OPCODE:
b1905489
JB		 2340 case ES_PREFIX_OPCODE:
2341 case FS_PREFIX_OPCODE:
2342 case GS_PREFIX_OPCODE:
2343 case SS_PREFIX_OPCODE:
2344 q = SEG_PREFIX;
2345 break;
2346
2347 case REPNE_PREFIX_OPCODE:
2348 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2349 q = REP_PREFIX;
2350 ret = PREFIX_REP;
2351 break;
2352
b1905489 2353 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2354 q = LOCK_PREFIX;
2355 ret = PREFIX_LOCK;
b1905489
JB		 2356 break;
2357
2358 case FWAIT_OPCODE:
2359 q = WAIT_PREFIX;
2360 break;
2361
2362 case ADDR_PREFIX_OPCODE:
2363 q = ADDR_PREFIX;
2364 break;
2365
2366 case DATA_PREFIX_OPCODE:
2367 q = DATA_PREFIX;
2368 break;
2369 }
2370 if (i.prefix[q] != 0)
c32fa91d 2371 ret = PREFIX_EXIST;
b1905489 2372 }
252b5132 2373
b1905489 2374 if (ret)
252b5132 2375 {
b1905489
JB		 2376 if (!i.prefix[q])
2377 ++i.prefixes;
2378 i.prefix[q] |= prefix;
252b5132 2379 }
b1905489
JB		 2380 else
2381 as_bad (_("same type of prefix used twice"));
252b5132 2382
252b5132
RH		 2383 return ret;
2384}
2385
2386static void
78f12dd3 2387update_code_flag (int value, int check)
eecb386c 2388{
78f12dd3
L		 2389 PRINTF_LIKE ((*as_error));
2390
1e9cc1c2 2391 flag_code = (enum flag_code) value;
40fb9820
L		 2392 if (flag_code == CODE_64BIT)
2393 {
2394 cpu_arch_flags.bitfield.cpu64 = 1;
2395 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2396 }
2397 else
2398 {
2399 cpu_arch_flags.bitfield.cpu64 = 0;
2400 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2401 }
2402 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2403 {
78f12dd3
L		 2404 if (check)
2405 as_error = as_fatal;
2406 else
2407 as_error = as_bad;
2408 (*as_error) (_("64bit mode not supported on `%s'."),
2409 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2410 }
40fb9820 2411 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2412 {
78f12dd3
L		 2413 if (check)
2414 as_error = as_fatal;
2415 else
2416 as_error = as_bad;
2417 (*as_error) (_("32bit mode not supported on `%s'."),
2418 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2419 }
eecb386c
AM		 2420 stackop_size = '\0';
2421}
2422
78f12dd3
L		 2423static void
2424set_code_flag (int value)
2425{
2426 update_code_flag (value, 0);
2427}
2428
eecb386c 2429static void
e3bb37b5 2430set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2431{
1e9cc1c2 2432 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2433 if (flag_code != CODE_16BIT)
2434 abort ();
2435 cpu_arch_flags.bitfield.cpu64 = 0;
2436 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2437 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2438}
2439
2440static void
e3bb37b5 2441set_intel_syntax (int syntax_flag)
252b5132
RH		 2442{
2443 /* Find out if register prefixing is specified. */
2444 int ask_naked_reg = 0;
2445
2446 SKIP_WHITESPACE ();
29b0f896 2447 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2448 {
d02603dc
NC		 2449 char *string;
2450 int e = get_symbol_name (&string);
252b5132 2451
47926f60 2452 if (strcmp (string, "prefix") == 0)
252b5132 2453 ask_naked_reg = 1;
47926f60 2454 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2455 ask_naked_reg = -1;
2456 else
d0b47220 2457 as_bad (_("bad argument to syntax directive."));
d02603dc 2458 (void) restore_line_pointer (e);
252b5132
RH		 2459 }
2460 demand_empty_rest_of_line ();
c3332e24 2461
252b5132
RH		 2462 intel_syntax = syntax_flag;
2463
2464 if (ask_naked_reg == 0)
f86103b7
AM		 2465 allow_naked_reg = (intel_syntax
2466 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2467 else
2468 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2469
ee86248c 2470 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2471
e4a3b5a4 2472 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2473 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2474 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2475}
2476
1efbbeb4
L		 2477static void
2478set_intel_mnemonic (int mnemonic_flag)
2479{
e1d4d893 2480 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2481}
2482
db51cc60
L		 2483static void
2484set_allow_index_reg (int flag)
2485{
2486 allow_index_reg = flag;
2487}
2488
cb19c032 2489static void
7bab8ab5 2490set_check (int what)
cb19c032 2491{
7bab8ab5
JB		 2492 enum check_kind *kind;
2493 const char *str;
2494
2495 if (what)
2496 {
2497 kind = &operand_check;
2498 str = "operand";
2499 }
2500 else
2501 {
2502 kind = &sse_check;
2503 str = "sse";
2504 }
2505
cb19c032
L		 2506 SKIP_WHITESPACE ();
2507
2508 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2509 {
d02603dc
NC		 2510 char *string;
2511 int e = get_symbol_name (&string);
cb19c032
L		 2512
2513 if (strcmp (string, "none") == 0)
7bab8ab5 2514 *kind = check_none;
cb19c032 2515 else if (strcmp (string, "warning") == 0)
7bab8ab5 2516 *kind = check_warning;
cb19c032 2517 else if (strcmp (string, "error") == 0)
7bab8ab5 2518 *kind = check_error;
cb19c032 2519 else
7bab8ab5 2520 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2521 (void) restore_line_pointer (e);
cb19c032
L		 2522 }
2523 else
7bab8ab5 2524 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2525
2526 demand_empty_rest_of_line ();
2527}
2528
8a9036a4
L		 2529static void
2530check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2531 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2532{
2533#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2534 static const char *arch;
2535
2536 /* Intel LIOM is only supported on ELF. */
2537 if (!IS_ELF)
2538 return;
2539
2540 if (!arch)
2541 {
2542 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2543 use default_arch. */
2544 arch = cpu_arch_name;
2545 if (!arch)
2546 arch = default_arch;
2547 }
2548
81486035
L		 2549 /* If we are targeting Intel MCU, we must enable it. */
2550 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2551 || new_flag.bitfield.cpuiamcu)
2552 return;
2553
3632d14b 2554 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2555 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2556 || new_flag.bitfield.cpul1om)
8a9036a4 2557 return;
76ba9986 2558
7a9068fe
L		 2559 /* If we are targeting Intel K1OM, we must enable it. */
2560 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2561 || new_flag.bitfield.cpuk1om)
2562 return;
2563
8a9036a4
L		 2564 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2565#endif
2566}
2567
e413e4e9 2568static void
e3bb37b5 2569set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2570{
47926f60 2571 SKIP_WHITESPACE ();
e413e4e9 2572
29b0f896 2573 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2574 {
d02603dc
NC		 2575 char *string;
2576 int e = get_symbol_name (&string);
91d6fa6a 2577 unsigned int j;
40fb9820 2578 i386_cpu_flags flags;
e413e4e9 2579
91d6fa6a 2580 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2581 {
91d6fa6a 2582 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2583 {
91d6fa6a 2584 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2585
5c6af06e
JB		 2586 if (*string != '.')
2587 {
91d6fa6a 2588 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2589 cpu_sub_arch_name = NULL;
91d6fa6a 2590 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2591 if (flag_code == CODE_64BIT)
2592 {
2593 cpu_arch_flags.bitfield.cpu64 = 1;
2594 cpu_arch_flags.bitfield.cpuno64 = 0;
2595 }
2596 else
2597 {
2598 cpu_arch_flags.bitfield.cpu64 = 0;
2599 cpu_arch_flags.bitfield.cpuno64 = 1;
2600 }
91d6fa6a
NC		 2601 cpu_arch_isa = cpu_arch[j].type;
2602 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2603 if (!cpu_arch_tune_set)
2604 {
2605 cpu_arch_tune = cpu_arch_isa;
2606 cpu_arch_tune_flags = cpu_arch_isa_flags;
2607 }
5c6af06e
JB		 2608 break;
2609 }
40fb9820 2610
293f5f65
L		 2611 flags = cpu_flags_or (cpu_arch_flags,
2612 cpu_arch[j].flags);
81486035 2613
5b64d091 2614 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2615 {
6305a203
L		 2616 if (cpu_sub_arch_name)
2617 {
2618 char *name = cpu_sub_arch_name;
2619 cpu_sub_arch_name = concat (name,
91d6fa6a 2620 cpu_arch[j].name,
1bf57e9f 2621 (const char *) NULL);
6305a203
L		 2622 free (name);
2623 }
2624 else
91d6fa6a 2625 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2626 cpu_arch_flags = flags;
a586129e 2627 cpu_arch_isa_flags = flags;
5c6af06e 2628 }
d02603dc 2629 (void) restore_line_pointer (e);
5c6af06e
JB		 2630 demand_empty_rest_of_line ();
2631 return;
e413e4e9
AM		 2632 }
2633 }
293f5f65
L		 2634
2635 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2636 {
33eaf5de 2637 /* Disable an ISA extension. */
293f5f65
L		 2638 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2639 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2640 {
2641 flags = cpu_flags_and_not (cpu_arch_flags,
2642 cpu_noarch[j].flags);
2643 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2644 {
2645 if (cpu_sub_arch_name)
2646 {
2647 char *name = cpu_sub_arch_name;
2648 cpu_sub_arch_name = concat (name, string,
2649 (const char *) NULL);
2650 free (name);
2651 }
2652 else
2653 cpu_sub_arch_name = xstrdup (string);
2654 cpu_arch_flags = flags;
2655 cpu_arch_isa_flags = flags;
2656 }
2657 (void) restore_line_pointer (e);
2658 demand_empty_rest_of_line ();
2659 return;
2660 }
2661
2662 j = ARRAY_SIZE (cpu_arch);
2663 }
2664
91d6fa6a 2665 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2666 as_bad (_("no such architecture: `%s'"), string);
2667
2668 *input_line_pointer = e;
2669 }
2670 else
2671 as_bad (_("missing cpu architecture"));
2672
fddf5b5b
AM		 2673 no_cond_jump_promotion = 0;
2674 if (*input_line_pointer == ','
29b0f896 2675 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2676 {
d02603dc
NC		 2677 char *string;
2678 char e;
2679
2680 ++input_line_pointer;
2681 e = get_symbol_name (&string);
fddf5b5b
AM		 2682
2683 if (strcmp (string, "nojumps") == 0)
2684 no_cond_jump_promotion = 1;
2685 else if (strcmp (string, "jumps") == 0)
2686 ;
2687 else
2688 as_bad (_("no such architecture modifier: `%s'"), string);
2689
d02603dc 2690 (void) restore_line_pointer (e);
fddf5b5b
AM		 2691 }
2692
e413e4e9
AM		 2693 demand_empty_rest_of_line ();
2694}
2695
8a9036a4
L		 2696enum bfd_architecture
2697i386_arch (void)
2698{
3632d14b 2699 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2700 {
2701 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2702 || flag_code != CODE_64BIT)
2703 as_fatal (_("Intel L1OM is 64bit ELF only"));
2704 return bfd_arch_l1om;
2705 }
7a9068fe
L		 2706 else if (cpu_arch_isa == PROCESSOR_K1OM)
2707 {
2708 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2709 || flag_code != CODE_64BIT)
2710 as_fatal (_("Intel K1OM is 64bit ELF only"));
2711 return bfd_arch_k1om;
2712 }
81486035
L		 2713 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2714 {
2715 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2716 || flag_code == CODE_64BIT)
2717 as_fatal (_("Intel MCU is 32bit ELF only"));
2718 return bfd_arch_iamcu;
2719 }
8a9036a4
L		 2720 else
2721 return bfd_arch_i386;
2722}
2723
b9d79e03 2724unsigned long
7016a5d5 2725i386_mach (void)
b9d79e03 2726{
351f65ca 2727 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2728 {
3632d14b 2729 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2730 {
351f65ca
L		 2731 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2732 || default_arch[6] != '\0')
8a9036a4
L		 2733 as_fatal (_("Intel L1OM is 64bit ELF only"));
2734 return bfd_mach_l1om;
2735 }
7a9068fe
L		 2736 else if (cpu_arch_isa == PROCESSOR_K1OM)
2737 {
2738 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2739 || default_arch[6] != '\0')
2740 as_fatal (_("Intel K1OM is 64bit ELF only"));
2741 return bfd_mach_k1om;
2742 }
351f65ca 2743 else if (default_arch[6] == '\0')
8a9036a4 2744 return bfd_mach_x86_64;
351f65ca
L		 2745 else
2746 return bfd_mach_x64_32;
8a9036a4 2747 }
5197d474
L		 2748 else if (!strcmp (default_arch, "i386")
2749 || !strcmp (default_arch, "iamcu"))
81486035
L		 2750 {
2751 if (cpu_arch_isa == PROCESSOR_IAMCU)
2752 {
2753 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2754 as_fatal (_("Intel MCU is 32bit ELF only"));
2755 return bfd_mach_i386_iamcu;
2756 }
2757 else
2758 return bfd_mach_i386_i386;
2759 }
b9d79e03 2760 else
2b5d6a91 2761 as_fatal (_("unknown architecture"));
b9d79e03 2762}
b9d79e03 2763\f
252b5132 2764void
7016a5d5 2765md_begin (void)
252b5132
RH		 2766{
2767 const char *hash_err;
2768
86fa6981
L		 2769 /* Support pseudo prefixes like {disp32}. */
2770 lex_type ['{'] = LEX_BEGIN_NAME;
2771
47926f60 2772 /* Initialize op_hash hash table. */
252b5132
RH		 2773 op_hash = hash_new ();
2774
2775 {
d3ce72d0 2776 const insn_template *optab;
29b0f896 2777 templates *core_optab;
252b5132 2778
47926f60
KH		 2779 /* Setup for loop. */
2780 optab = i386_optab;
add39d23 2781 core_optab = XNEW (templates);
252b5132
RH		 2782 core_optab->start = optab;
2783
2784 while (1)
2785 {
2786 ++optab;
2787 if (optab->name == NULL
2788 || strcmp (optab->name, (optab - 1)->name) != 0)
2789 {
2790 /* different name --> ship out current template list;
47926f60 2791 add to hash table; & begin anew. */
252b5132
RH		 2792 core_optab->end = optab;
2793 hash_err = hash_insert (op_hash,
2794 (optab - 1)->name,
5a49b8ac 2795 (void *) core_optab);
252b5132
RH		 2796 if (hash_err)
2797 {
b37df7c4 2798 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2799 (optab - 1)->name,
2800 hash_err);
2801 }
2802 if (optab->name == NULL)
2803 break;
add39d23 2804 core_optab = XNEW (templates);
252b5132
RH		 2805 core_optab->start = optab;
2806 }
2807 }
2808 }
2809
47926f60 2810 /* Initialize reg_hash hash table. */
252b5132
RH		 2811 reg_hash = hash_new ();
2812 {
29b0f896 2813 const reg_entry *regtab;
c3fe08fa 2814 unsigned int regtab_size = i386_regtab_size;
252b5132 2815
c3fe08fa 2816 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2817 {
5a49b8ac 2818 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2819 if (hash_err)
b37df7c4 2820 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2821 regtab->reg_name,
2822 hash_err);
252b5132
RH		 2823 }
2824 }
2825
47926f60 2826 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2827 {
29b0f896
AM		 2828 int c;
2829 char *p;
252b5132
RH		 2830
2831 for (c = 0; c < 256; c++)
2832 {
3882b010 2833 if (ISDIGIT (c))
252b5132
RH		 2834 {
2835 digit_chars[c] = c;
2836 mnemonic_chars[c] = c;
2837 register_chars[c] = c;
2838 operand_chars[c] = c;
2839 }
3882b010 2840 else if (ISLOWER (c))
252b5132
RH		 2841 {
2842 mnemonic_chars[c] = c;
2843 register_chars[c] = c;
2844 operand_chars[c] = c;
2845 }
3882b010 2846 else if (ISUPPER (c))
252b5132 2847 {
3882b010 2848 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2849 register_chars[c] = mnemonic_chars[c];
2850 operand_chars[c] = c;
2851 }
43234a1e 2852 else if (c == '{' || c == '}')
86fa6981
L		 2853 {
2854 mnemonic_chars[c] = c;
2855 operand_chars[c] = c;
2856 }
252b5132 2857
3882b010 2858 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2859 identifier_chars[c] = c;
2860 else if (c >= 128)
2861 {
2862 identifier_chars[c] = c;
2863 operand_chars[c] = c;
2864 }
2865 }
2866
2867#ifdef LEX_AT
2868 identifier_chars['@'] = '@';
32137342
NC		 2869#endif
2870#ifdef LEX_QM
2871 identifier_chars['?'] = '?';
2872 operand_chars['?'] = '?';
252b5132 2873#endif
252b5132 2874 digit_chars['-'] = '-';
c0f3af97 2875 mnemonic_chars['_'] = '_';
791fe849 2876 mnemonic_chars['-'] = '-';
0003779b 2877 mnemonic_chars['.'] = '.';
252b5132
RH		 2878 identifier_chars['_'] = '_';
2879 identifier_chars['.'] = '.';
2880
2881 for (p = operand_special_chars; *p != '\0'; p++)
2882 operand_chars[(unsigned char) *p] = *p;
2883 }
2884
a4447b93
RH		 2885 if (flag_code == CODE_64BIT)
2886 {
ca19b261
KT		 2887#if defined (OBJ_COFF) && defined (TE_PE)
2888 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2889 ? 32 : 16);
2890#else
a4447b93 2891 x86_dwarf2_return_column = 16;
ca19b261 2892#endif
61ff971f 2893 x86_cie_data_alignment = -8;
a4447b93
RH		 2894 }
2895 else
2896 {
2897 x86_dwarf2_return_column = 8;
2898 x86_cie_data_alignment = -4;
2899 }
252b5132
RH		 2900}
2901
2902void
e3bb37b5 2903i386_print_statistics (FILE *file)
252b5132
RH		 2904{
2905 hash_print_statistics (file, "i386 opcode", op_hash);
2906 hash_print_statistics (file, "i386 register", reg_hash);
2907}
2908\f
252b5132
RH		 2909#ifdef DEBUG386
2910
ce8a8b2f 2911/* Debugging routines for md_assemble. */
d3ce72d0 2912static void pte (insn_template *);
40fb9820 2913static void pt (i386_operand_type);
e3bb37b5
L		 2914static void pe (expressionS *);
2915static void ps (symbolS *);
252b5132
RH		 2916
2917static void
e3bb37b5 2918pi (char *line, i386_insn *x)
252b5132 2919{
09137c09 2920 unsigned int j;
252b5132
RH		 2921
2922 fprintf (stdout, "%s: template ", line);
2923 pte (&x->tm);
09f131f2
JH		 2924 fprintf (stdout, " address: base %s index %s scale %x\n",
2925 x->base_reg ? x->base_reg->reg_name : "none",
2926 x->index_reg ? x->index_reg->reg_name : "none",
2927 x->log2_scale_factor);
2928 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2929 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2930 fprintf (stdout, " sib: base %x index %x scale %x\n",
2931 x->sib.base, x->sib.index, x->sib.scale);
2932 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2933 (x->rex & REX_W) != 0,
2934 (x->rex & REX_R) != 0,
2935 (x->rex & REX_X) != 0,
2936 (x->rex & REX_B) != 0);
09137c09 2937 for (j = 0; j < x->operands; j++)
252b5132 2938 {
09137c09
SP		 2939 fprintf (stdout, " #%d: ", j + 1);
2940 pt (x->types[j]);
252b5132 2941 fprintf (stdout, "\n");
dc821c5f 2942 if (x->types[j].bitfield.reg
09137c09 2943 || x->types[j].bitfield.regmmx
1b54b8d7 2944 || x->types[j].bitfield.regsimd
09137c09
SP		 2945 || x->types[j].bitfield.sreg2
2946 || x->types[j].bitfield.sreg3
2947 || x->types[j].bitfield.control
2948 || x->types[j].bitfield.debug
2949 || x->types[j].bitfield.test)
2950 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2951 if (operand_type_check (x->types[j], imm))
2952 pe (x->op[j].imms);
2953 if (operand_type_check (x->types[j], disp))
2954 pe (x->op[j].disps);
252b5132
RH		 2955 }
2956}
2957
2958static void
d3ce72d0 2959pte (insn_template *t)
252b5132 2960{
09137c09 2961 unsigned int j;
252b5132 2962 fprintf (stdout, " %d operands ", t->operands);
47926f60 2963 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2964 if (t->extension_opcode != None)
2965 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2966 if (t->opcode_modifier.d)
252b5132 2967 fprintf (stdout, "D");
40fb9820 2968 if (t->opcode_modifier.w)
252b5132
RH		 2969 fprintf (stdout, "W");
2970 fprintf (stdout, "\n");
09137c09 2971 for (j = 0; j < t->operands; j++)
252b5132 2972 {
09137c09
SP		 2973 fprintf (stdout, " #%d type ", j + 1);
2974 pt (t->operand_types[j]);
252b5132
RH		 2975 fprintf (stdout, "\n");
2976 }
2977}
2978
2979static void
e3bb37b5 2980pe (expressionS *e)
252b5132 2981{
24eab124 2982 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2983 fprintf (stdout, " add_number %ld (%lx)\n",
2984 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2985 if (e->X_add_symbol)
2986 {
2987 fprintf (stdout, " add_symbol ");
2988 ps (e->X_add_symbol);
2989 fprintf (stdout, "\n");
2990 }
2991 if (e->X_op_symbol)
2992 {
2993 fprintf (stdout, " op_symbol ");
2994 ps (e->X_op_symbol);
2995 fprintf (stdout, "\n");
2996 }
2997}
2998
2999static void
e3bb37b5 3000ps (symbolS *s)
252b5132
RH		 3001{
3002 fprintf (stdout, "%s type %s%s",
3003 S_GET_NAME (s),
3004 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3005 segment_name (S_GET_SEGMENT (s)));
3006}
3007
7b81dfbb 3008static struct type_name
252b5132 3009 {
40fb9820
L		 3010 i386_operand_type mask;
3011 const char *name;
252b5132 3012 }
7b81dfbb 3013const type_names[] =
252b5132 3014{
40fb9820
L		 3015 { OPERAND_TYPE_REG8, "r8" },
3016 { OPERAND_TYPE_REG16, "r16" },
3017 { OPERAND_TYPE_REG32, "r32" },
3018 { OPERAND_TYPE_REG64, "r64" },
3019 { OPERAND_TYPE_IMM8, "i8" },
3020 { OPERAND_TYPE_IMM8, "i8s" },
3021 { OPERAND_TYPE_IMM16, "i16" },
3022 { OPERAND_TYPE_IMM32, "i32" },
3023 { OPERAND_TYPE_IMM32S, "i32s" },
3024 { OPERAND_TYPE_IMM64, "i64" },
3025 { OPERAND_TYPE_IMM1, "i1" },
3026 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3027 { OPERAND_TYPE_DISP8, "d8" },
3028 { OPERAND_TYPE_DISP16, "d16" },
3029 { OPERAND_TYPE_DISP32, "d32" },
3030 { OPERAND_TYPE_DISP32S, "d32s" },
3031 { OPERAND_TYPE_DISP64, "d64" },
3032 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3033 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3034 { OPERAND_TYPE_CONTROL, "control reg" },
3035 { OPERAND_TYPE_TEST, "test reg" },
3036 { OPERAND_TYPE_DEBUG, "debug reg" },
3037 { OPERAND_TYPE_FLOATREG, "FReg" },
3038 { OPERAND_TYPE_FLOATACC, "FAcc" },
3039 { OPERAND_TYPE_SREG2, "SReg2" },
3040 { OPERAND_TYPE_SREG3, "SReg3" },
3041 { OPERAND_TYPE_ACC, "Acc" },
3042 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3043 { OPERAND_TYPE_REGMMX, "rMMX" },
3044 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3045 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3046 { OPERAND_TYPE_REGZMM, "rZMM" },
3047 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3048 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3049};
3050
3051static void
40fb9820 3052pt (i386_operand_type t)
252b5132 3053{
40fb9820 3054 unsigned int j;
c6fb90c8 3055 i386_operand_type a;
252b5132 3056
40fb9820 3057 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3058 {
3059 a = operand_type_and (t, type_names[j].mask);
0349dc08 3060 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3061 fprintf (stdout, "%s, ", type_names[j].name);
3062 }
252b5132
RH		 3063 fflush (stdout);
3064}
3065
3066#endif /* DEBUG386 */
3067\f
252b5132 3068static bfd_reloc_code_real_type
3956db08 3069reloc (unsigned int size,
64e74474
AM		 3070 int pcrel,
3071 int sign,
3072 bfd_reloc_code_real_type other)
252b5132 3073{
47926f60 3074 if (other != NO_RELOC)
3956db08 3075 {
91d6fa6a 3076 reloc_howto_type *rel;
3956db08
JB		 3077
3078 if (size == 8)
3079 switch (other)
3080 {
64e74474
AM		 3081 case BFD_RELOC_X86_64_GOT32:
3082 return BFD_RELOC_X86_64_GOT64;
3083 break;
553d1284
L		 3084 case BFD_RELOC_X86_64_GOTPLT64:
3085 return BFD_RELOC_X86_64_GOTPLT64;
3086 break;
64e74474
AM		 3087 case BFD_RELOC_X86_64_PLTOFF64:
3088 return BFD_RELOC_X86_64_PLTOFF64;
3089 break;
3090 case BFD_RELOC_X86_64_GOTPC32:
3091 other = BFD_RELOC_X86_64_GOTPC64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPCREL:
3094 other = BFD_RELOC_X86_64_GOTPCREL64;
3095 break;
3096 case BFD_RELOC_X86_64_TPOFF32:
3097 other = BFD_RELOC_X86_64_TPOFF64;
3098 break;
3099 case BFD_RELOC_X86_64_DTPOFF32:
3100 other = BFD_RELOC_X86_64_DTPOFF64;
3101 break;
3102 default:
3103 break;
3956db08 3104 }
e05278af 3105
8ce3d284 3106#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3107 if (other == BFD_RELOC_SIZE32)
3108 {
3109 if (size == 8)
1ab668bf 3110 other = BFD_RELOC_SIZE64;
8fd4256d 3111 if (pcrel)
1ab668bf
AM		 3112 {
3113 as_bad (_("there are no pc-relative size relocations"));
3114 return NO_RELOC;
3115 }
8fd4256d 3116 }
8ce3d284 3117#endif
8fd4256d 3118
e05278af 3119 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3120 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3121 sign = -1;
3122
91d6fa6a
NC		 3123 rel = bfd_reloc_type_lookup (stdoutput, other);
3124 if (!rel)
3956db08 3125 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3126 else if (size != bfd_get_reloc_size (rel))
3956db08 3127 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3128 bfd_get_reloc_size (rel),
3956db08 3129 size);
91d6fa6a 3130 else if (pcrel && !rel->pc_relative)
3956db08 3131 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3132 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3133 && !sign)
91d6fa6a 3134 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3135 && sign > 0))
3956db08
JB		 3136 as_bad (_("relocated field and relocation type differ in signedness"));
3137 else
3138 return other;
3139 return NO_RELOC;
3140 }
252b5132
RH		 3141
3142 if (pcrel)
3143 {
3e73aa7c 3144 if (!sign)
3956db08 3145 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3146 switch (size)
3147 {
3148 case 1: return BFD_RELOC_8_PCREL;
3149 case 2: return BFD_RELOC_16_PCREL;
d258b828 3150 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3151 case 8: return BFD_RELOC_64_PCREL;
252b5132 3152 }
3956db08 3153 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3154 }
3155 else
3156 {
3956db08 3157 if (sign > 0)
e5cb08ac 3158 switch (size)
3e73aa7c
JH		 3159 {
3160 case 4: return BFD_RELOC_X86_64_32S;
3161 }
3162 else
3163 switch (size)
3164 {
3165 case 1: return BFD_RELOC_8;
3166 case 2: return BFD_RELOC_16;
3167 case 4: return BFD_RELOC_32;
3168 case 8: return BFD_RELOC_64;
3169 }
3956db08
JB		 3170 as_bad (_("cannot do %s %u byte relocation"),
3171 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3172 }
3173
0cc9e1d3 3174 return NO_RELOC;
252b5132
RH		 3175}
3176
47926f60
KH		 3177/* Here we decide which fixups can be adjusted to make them relative to
3178 the beginning of the section instead of the symbol. Basically we need
3179 to make sure that the dynamic relocations are done correctly, so in
3180 some cases we force the original symbol to be used. */
3181
252b5132 3182int
e3bb37b5 3183tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3184{
6d249963 3185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3186 if (!IS_ELF)
31312f95
AM		 3187 return 1;
3188
a161fe53
AM		 3189 /* Don't adjust pc-relative references to merge sections in 64-bit
3190 mode. */
3191 if (use_rela_relocations
3192 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3193 && fixP->fx_pcrel)
252b5132 3194 return 0;
31312f95 3195
8d01d9a9
AJ		 3196 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3197 and changed later by validate_fix. */
3198 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3199 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3200 return 0;
3201
8fd4256d
L		 3202 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3203 for size relocations. */
3204 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3205 || fixP->fx_r_type == BFD_RELOC_SIZE64
3206 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3207 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3208 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3209 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3210 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3211 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3212 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3220 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3221 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3222 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3223 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3225 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3228 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3235 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3236 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3237 return 0;
31312f95 3238#endif
252b5132
RH		 3239 return 1;
3240}
252b5132 3241
b4cac588 3242static int
e3bb37b5 3243intel_float_operand (const char *mnemonic)
252b5132 3244{
9306ca4a
JB		 3245 /* Note that the value returned is meaningful only for opcodes with (memory)
3246 operands, hence the code here is free to improperly handle opcodes that
3247 have no operands (for better performance and smaller code). */
3248
3249 if (mnemonic[0] != 'f')
3250 return 0; /* non-math */
3251
3252 switch (mnemonic[1])
3253 {
3254 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3255 the fs segment override prefix not currently handled because no
3256 call path can make opcodes without operands get here */
3257 case 'i':
3258 return 2 /* integer op */;
3259 case 'l':
3260 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3261 return 3; /* fldcw/fldenv */
3262 break;
3263 case 'n':
3264 if (mnemonic[2] != 'o' /* fnop */)
3265 return 3; /* non-waiting control op */
3266 break;
3267 case 'r':
3268 if (mnemonic[2] == 's')
3269 return 3; /* frstor/frstpm */
3270 break;
3271 case 's':
3272 if (mnemonic[2] == 'a')
3273 return 3; /* fsave */
3274 if (mnemonic[2] == 't')
3275 {
3276 switch (mnemonic[3])
3277 {
3278 case 'c': /* fstcw */
3279 case 'd': /* fstdw */
3280 case 'e': /* fstenv */
3281 case 's': /* fsts[gw] */
3282 return 3;
3283 }
3284 }
3285 break;
3286 case 'x':
3287 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3288 return 0; /* fxsave/fxrstor are not really math ops */
3289 break;
3290 }
252b5132 3291
9306ca4a 3292 return 1;
252b5132
RH		 3293}
3294
c0f3af97
L		 3295/* Build the VEX prefix. */
3296
3297static void
d3ce72d0 3298build_vex_prefix (const insn_template *t)
c0f3af97
L		 3299{
3300 unsigned int register_specifier;
3301 unsigned int implied_prefix;
3302 unsigned int vector_length;
3303
3304 /* Check register specifier. */
3305 if (i.vex.register_specifier)
43234a1e
L		 3306 {
3307 register_specifier =
3308 ~register_number (i.vex.register_specifier) & 0xf;
3309 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3310 }
c0f3af97
L		 3311 else
3312 register_specifier = 0xf;
3313
33eaf5de 3314 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3315 operand. */
86fa6981
L		 3316 if (i.vec_encoding != vex_encoding_vex3
3317 && i.dir_encoding == dir_encoding_default
fa99fab2 3318 && i.operands == i.reg_operands
7f399153 3319 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3320 && i.tm.opcode_modifier.load
fa99fab2
L		 3321 && i.rex == REX_B)
3322 {
3323 unsigned int xchg = i.operands - 1;
3324 union i386_op temp_op;
3325 i386_operand_type temp_type;
3326
3327 temp_type = i.types[xchg];
3328 i.types[xchg] = i.types[0];
3329 i.types[0] = temp_type;
3330 temp_op = i.op[xchg];
3331 i.op[xchg] = i.op[0];
3332 i.op[0] = temp_op;
3333
9c2799c2 3334 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3335
3336 i.rex = REX_R;
3337 xchg = i.rm.regmem;
3338 i.rm.regmem = i.rm.reg;
3339 i.rm.reg = xchg;
3340
3341 /* Use the next insn. */
3342 i.tm = t[1];
3343 }
3344
539f890d
L		 3345 if (i.tm.opcode_modifier.vex == VEXScalar)
3346 vector_length = avxscalar;
10c17abd
JB		 3347 else if (i.tm.opcode_modifier.vex == VEX256)
3348 vector_length = 1;
539f890d 3349 else
10c17abd
JB		 3350 {
3351 unsigned int op;
3352
3353 vector_length = 0;
3354 for (op = 0; op < t->operands; ++op)
3355 if (t->operand_types[op].bitfield.xmmword
3356 && t->operand_types[op].bitfield.ymmword
3357 && i.types[op].bitfield.ymmword)
3358 {
3359 vector_length = 1;
3360 break;
3361 }
3362 }
c0f3af97
L		 3363
3364 switch ((i.tm.base_opcode >> 8) & 0xff)
3365 {
3366 case 0:
3367 implied_prefix = 0;
3368 break;
3369 case DATA_PREFIX_OPCODE:
3370 implied_prefix = 1;
3371 break;
3372 case REPE_PREFIX_OPCODE:
3373 implied_prefix = 2;
3374 break;
3375 case REPNE_PREFIX_OPCODE:
3376 implied_prefix = 3;
3377 break;
3378 default:
3379 abort ();
3380 }
3381
3382 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3383 if (i.vec_encoding != vex_encoding_vex3
3384 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3385 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3386 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3387 {
3388 /* 2-byte VEX prefix. */
3389 unsigned int r;
3390
3391 i.vex.length = 2;
3392 i.vex.bytes[0] = 0xc5;
3393
3394 /* Check the REX.R bit. */
3395 r = (i.rex & REX_R) ? 0 : 1;
3396 i.vex.bytes[1] = (r << 7
3397 | register_specifier << 3
3398 | vector_length << 2
3399 | implied_prefix);
3400 }
3401 else
3402 {
3403 /* 3-byte VEX prefix. */
3404 unsigned int m, w;
3405
f88c9eb0 3406 i.vex.length = 3;
f88c9eb0 3407
7f399153 3408 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3409 {
7f399153
L		 3410 case VEX0F:
3411 m = 0x1;
80de6e00 3412 i.vex.bytes[0] = 0xc4;
7f399153
L		 3413 break;
3414 case VEX0F38:
3415 m = 0x2;
80de6e00 3416 i.vex.bytes[0] = 0xc4;
7f399153
L		 3417 break;
3418 case VEX0F3A:
3419 m = 0x3;
80de6e00 3420 i.vex.bytes[0] = 0xc4;
7f399153
L		 3421 break;
3422 case XOP08:
5dd85c99
SP		 3423 m = 0x8;
3424 i.vex.bytes[0] = 0x8f;
7f399153
L		 3425 break;
3426 case XOP09:
f88c9eb0
SP		 3427 m = 0x9;
3428 i.vex.bytes[0] = 0x8f;
7f399153
L		 3429 break;
3430 case XOP0A:
f88c9eb0
SP		 3431 m = 0xa;
3432 i.vex.bytes[0] = 0x8f;
7f399153
L		 3433 break;
3434 default:
3435 abort ();
f88c9eb0 3436 }
c0f3af97 3437
c0f3af97
L		 3438 /* The high 3 bits of the second VEX byte are 1's compliment
3439 of RXB bits from REX. */
3440 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3441
3442 /* Check the REX.W bit. */
3443 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3444 if (i.tm.opcode_modifier.vexw == VEXW1)
3445 w = 1;
c0f3af97
L		 3446
3447 i.vex.bytes[2] = (w << 7
3448 | register_specifier << 3
3449 | vector_length << 2
3450 | implied_prefix);
3451 }
3452}
3453
e771e7c9
JB		 3454static INLINE bfd_boolean
3455is_evex_encoding (const insn_template *t)
3456{
3457 return t->opcode_modifier.evex
3458 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3459 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3460}
3461
43234a1e
L		 3462/* Build the EVEX prefix. */
3463
3464static void
3465build_evex_prefix (void)
3466{
3467 unsigned int register_specifier;
3468 unsigned int implied_prefix;
3469 unsigned int m, w;
3470 rex_byte vrex_used = 0;
3471
3472 /* Check register specifier. */
3473 if (i.vex.register_specifier)
3474 {
3475 gas_assert ((i.vrex & REX_X) == 0);
3476
3477 register_specifier = i.vex.register_specifier->reg_num;
3478 if ((i.vex.register_specifier->reg_flags & RegRex))
3479 register_specifier += 8;
3480 /* The upper 16 registers are encoded in the fourth byte of the
3481 EVEX prefix. */
3482 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3483 i.vex.bytes[3] = 0x8;
3484 register_specifier = ~register_specifier & 0xf;
3485 }
3486 else
3487 {
3488 register_specifier = 0xf;
3489
3490 /* Encode upper 16 vector index register in the fourth byte of
3491 the EVEX prefix. */
3492 if (!(i.vrex & REX_X))
3493 i.vex.bytes[3] = 0x8;
3494 else
3495 vrex_used |= REX_X;
3496 }
3497
3498 switch ((i.tm.base_opcode >> 8) & 0xff)
3499 {
3500 case 0:
3501 implied_prefix = 0;
3502 break;
3503 case DATA_PREFIX_OPCODE:
3504 implied_prefix = 1;
3505 break;
3506 case REPE_PREFIX_OPCODE:
3507 implied_prefix = 2;
3508 break;
3509 case REPNE_PREFIX_OPCODE:
3510 implied_prefix = 3;
3511 break;
3512 default:
3513 abort ();
3514 }
3515
3516 /* 4 byte EVEX prefix. */
3517 i.vex.length = 4;
3518 i.vex.bytes[0] = 0x62;
3519
3520 /* mmmm bits. */
3521 switch (i.tm.opcode_modifier.vexopcode)
3522 {
3523 case VEX0F:
3524 m = 1;
3525 break;
3526 case VEX0F38:
3527 m = 2;
3528 break;
3529 case VEX0F3A:
3530 m = 3;
3531 break;
3532 default:
3533 abort ();
3534 break;
3535 }
3536
3537 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3538 bits from REX. */
3539 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3540
3541 /* The fifth bit of the second EVEX byte is 1's compliment of the
3542 REX_R bit in VREX. */
3543 if (!(i.vrex & REX_R))
3544 i.vex.bytes[1] |= 0x10;
3545 else
3546 vrex_used |= REX_R;
3547
3548 if ((i.reg_operands + i.imm_operands) == i.operands)
3549 {
3550 /* When all operands are registers, the REX_X bit in REX is not
3551 used. We reuse it to encode the upper 16 registers, which is
3552 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3553 as 1's compliment. */
3554 if ((i.vrex & REX_B))
3555 {
3556 vrex_used |= REX_B;
3557 i.vex.bytes[1] &= ~0x40;
3558 }
3559 }
3560
3561 /* EVEX instructions shouldn't need the REX prefix. */
3562 i.vrex &= ~vrex_used;
3563 gas_assert (i.vrex == 0);
3564
3565 /* Check the REX.W bit. */
3566 w = (i.rex & REX_W) ? 1 : 0;
3567 if (i.tm.opcode_modifier.vexw)
3568 {
3569 if (i.tm.opcode_modifier.vexw == VEXW1)
3570 w = 1;
3571 }
3572 /* If w is not set it means we are dealing with WIG instruction. */
3573 else if (!w)
3574 {
3575 if (evexwig == evexw1)
3576 w = 1;
3577 }
3578
3579 /* Encode the U bit. */
3580 implied_prefix |= 0x4;
3581
3582 /* The third byte of the EVEX prefix. */
3583 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3584
3585 /* The fourth byte of the EVEX prefix. */
3586 /* The zeroing-masking bit. */
3587 if (i.mask && i.mask->zeroing)
3588 i.vex.bytes[3] |= 0x80;
3589
3590 /* Don't always set the broadcast bit if there is no RC. */
3591 if (!i.rounding)
3592 {
3593 /* Encode the vector length. */
3594 unsigned int vec_length;
3595
e771e7c9
JB		 3596 if (!i.tm.opcode_modifier.evex
3597 || i.tm.opcode_modifier.evex == EVEXDYN)
3598 {
3599 unsigned int op;
3600
3601 vec_length = 0;
3602 for (op = 0; op < i.tm.operands; ++op)
3603 if (i.tm.operand_types[op].bitfield.xmmword
3604 + i.tm.operand_types[op].bitfield.ymmword
3605 + i.tm.operand_types[op].bitfield.zmmword > 1)
3606 {
3607 if (i.types[op].bitfield.zmmword)
3608 i.tm.opcode_modifier.evex = EVEX512;
3609 else if (i.types[op].bitfield.ymmword)
3610 i.tm.opcode_modifier.evex = EVEX256;
3611 else if (i.types[op].bitfield.xmmword)
3612 i.tm.opcode_modifier.evex = EVEX128;
3613 else
3614 continue;
3615 break;
3616 }
3617 }
3618
43234a1e
L		 3619 switch (i.tm.opcode_modifier.evex)
3620 {
3621 case EVEXLIG: /* LL' is ignored */
3622 vec_length = evexlig << 5;
3623 break;
3624 case EVEX128:
3625 vec_length = 0 << 5;
3626 break;
3627 case EVEX256:
3628 vec_length = 1 << 5;
3629 break;
3630 case EVEX512:
3631 vec_length = 2 << 5;
3632 break;
3633 default:
3634 abort ();
3635 break;
3636 }
3637 i.vex.bytes[3] |= vec_length;
3638 /* Encode the broadcast bit. */
3639 if (i.broadcast)
3640 i.vex.bytes[3] |= 0x10;
3641 }
3642 else
3643 {
3644 if (i.rounding->type != saeonly)
3645 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3646 else
d3d3c6db 3647 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3648 }
3649
3650 if (i.mask && i.mask->mask)
3651 i.vex.bytes[3] |= i.mask->mask->reg_num;
3652}
3653
65da13b5
L		 3654static void
3655process_immext (void)
3656{
3657 expressionS *exp;
3658
4c692bc7
JB		 3659 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3660 && i.operands > 0)
65da13b5 3661 {
4c692bc7
JB		 3662 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3663 with an opcode suffix which is coded in the same place as an
3664 8-bit immediate field would be.
3665 Here we check those operands and remove them afterwards. */
65da13b5
L		 3666 unsigned int x;
3667
3668 for (x = 0; x < i.operands; x++)
4c692bc7 3669 if (register_number (i.op[x].regs) != x)
65da13b5 3670 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3671 register_prefix, i.op[x].regs->reg_name, x + 1,
3672 i.tm.name);
3673
3674 i.operands = 0;
65da13b5
L		 3675 }
3676
9916071f
AP		 3677 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3678 {
3679 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3680 suffix which is coded in the same place as an 8-bit immediate
3681 field would be.
3682 Here we check those operands and remove them afterwards. */
3683 unsigned int x;
3684
3685 if (i.operands != 3)
3686 abort();
3687
3688 for (x = 0; x < 2; x++)
3689 if (register_number (i.op[x].regs) != x)
3690 goto bad_register_operand;
3691
3692 /* Check for third operand for mwaitx/monitorx insn. */
3693 if (register_number (i.op[x].regs)
3694 != (x + (i.tm.extension_opcode == 0xfb)))
3695 {
3696bad_register_operand:
3697 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3698 register_prefix, i.op[x].regs->reg_name, x+1,
3699 i.tm.name);
3700 }
3701
3702 i.operands = 0;
3703 }
3704
c0f3af97 3705 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3706 which is coded in the same place as an 8-bit immediate field
3707 would be. Here we fake an 8-bit immediate operand from the
3708 opcode suffix stored in tm.extension_opcode.
3709
c1e679ec 3710 AVX instructions also use this encoding, for some of
c0f3af97 3711 3 argument instructions. */
65da13b5 3712
43234a1e 3713 gas_assert (i.imm_operands <= 1
7ab9ffdd 3714 && (i.operands <= 2
43234a1e 3715 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3716 || i.tm.opcode_modifier.vexopcode
3717 || is_evex_encoding (&i.tm))
7ab9ffdd 3718 && i.operands <= 4)));
65da13b5
L		 3719
3720 exp = &im_expressions[i.imm_operands++];
3721 i.op[i.operands].imms = exp;
3722 i.types[i.operands] = imm8;
3723 i.operands++;
3724 exp->X_op = O_constant;
3725 exp->X_add_number = i.tm.extension_opcode;
3726 i.tm.extension_opcode = None;
3727}
3728
42164a71
L		 3729
3730static int
3731check_hle (void)
3732{
3733 switch (i.tm.opcode_modifier.hleprefixok)
3734 {
3735 default:
3736 abort ();
82c2def5 3737 case HLEPrefixNone:
165de32a
L		 3738 as_bad (_("invalid instruction `%s' after `%s'"),
3739 i.tm.name, i.hle_prefix);
42164a71 3740 return 0;
82c2def5 3741 case HLEPrefixLock:
42164a71
L		 3742 if (i.prefix[LOCK_PREFIX])
3743 return 1;
165de32a 3744 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3745 return 0;
82c2def5 3746 case HLEPrefixAny:
42164a71 3747 return 1;
82c2def5 3748 case HLEPrefixRelease:
42164a71
L		 3749 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3750 {
3751 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3752 i.tm.name);
3753 return 0;
3754 }
3755 if (i.mem_operands == 0
3756 || !operand_type_check (i.types[i.operands - 1], anymem))
3757 {
3758 as_bad (_("memory destination needed for instruction `%s'"
3759 " after `xrelease'"), i.tm.name);
3760 return 0;
3761 }
3762 return 1;
3763 }
3764}
3765
b6f8c7c4
L		 3766/* Try the shortest encoding by shortening operand size. */
3767
3768static void
3769optimize_encoding (void)
3770{
3771 int j;
3772
3773 if (optimize_for_space
3774 && i.reg_operands == 1
3775 && i.imm_operands == 1
3776 && !i.types[1].bitfield.byte
3777 && i.op[0].imms->X_op == O_constant
3778 && fits_in_imm7 (i.op[0].imms->X_add_number)
3779 && ((i.tm.base_opcode == 0xa8
3780 && i.tm.extension_opcode == None)
3781 || (i.tm.base_opcode == 0xf6
3782 && i.tm.extension_opcode == 0x0)))
3783 {
3784 /* Optimize: -Os:
3785 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3786 */
3787 unsigned int base_regnum = i.op[1].regs->reg_num;
3788 if (flag_code == CODE_64BIT || base_regnum < 4)
3789 {
3790 i.types[1].bitfield.byte = 1;
3791 /* Ignore the suffix. */
3792 i.suffix = 0;
3793 if (base_regnum >= 4
3794 && !(i.op[1].regs->reg_flags & RegRex))
3795 {
3796 /* Handle SP, BP, SI and DI registers. */
3797 if (i.types[1].bitfield.word)
3798 j = 16;
3799 else if (i.types[1].bitfield.dword)
3800 j = 32;
3801 else
3802 j = 48;
3803 i.op[1].regs -= j;
3804 }
3805 }
3806 }
3807 else if (flag_code == CODE_64BIT
3808 && ((i.reg_operands == 1
3809 && i.imm_operands == 1
3810 && i.op[0].imms->X_op == O_constant
3811 && ((i.tm.base_opcode == 0xb0
3812 && i.tm.extension_opcode == None
3813 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3814 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3815 && (((i.tm.base_opcode == 0x24
3816 || i.tm.base_opcode == 0xa8)
3817 && i.tm.extension_opcode == None)
3818 || (i.tm.base_opcode == 0x80
3819 && i.tm.extension_opcode == 0x4)
3820 || ((i.tm.base_opcode == 0xf6
3821 || i.tm.base_opcode == 0xc6)
3822 && i.tm.extension_opcode == 0x0)))))
3823 || (i.reg_operands == 2
3824 && i.op[0].regs == i.op[1].regs
3825 && ((i.tm.base_opcode == 0x30
3826 || i.tm.base_opcode == 0x28)
3827 && i.tm.extension_opcode == None)))
3828 && i.types[1].bitfield.qword)
3829 {
3830 /* Optimize: -O:
3831 andq $imm31, %r64 -> andl $imm31, %r32
3832 testq $imm31, %r64 -> testl $imm31, %r32
3833 xorq %r64, %r64 -> xorl %r32, %r32
3834 subq %r64, %r64 -> subl %r32, %r32
3835 movq $imm31, %r64 -> movl $imm31, %r32
3836 movq $imm32, %r64 -> movl $imm32, %r32
3837 */
3838 i.tm.opcode_modifier.norex64 = 1;
3839 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3840 {
3841 /* Handle
3842 movq $imm31, %r64 -> movl $imm31, %r32
3843 movq $imm32, %r64 -> movl $imm32, %r32
3844 */
3845 i.tm.operand_types[0].bitfield.imm32 = 1;
3846 i.tm.operand_types[0].bitfield.imm32s = 0;
3847 i.tm.operand_types[0].bitfield.imm64 = 0;
3848 i.types[0].bitfield.imm32 = 1;
3849 i.types[0].bitfield.imm32s = 0;
3850 i.types[0].bitfield.imm64 = 0;
3851 i.types[1].bitfield.dword = 1;
3852 i.types[1].bitfield.qword = 0;
3853 if (i.tm.base_opcode == 0xc6)
3854 {
3855 /* Handle
3856 movq $imm31, %r64 -> movl $imm31, %r32
3857 */
3858 i.tm.base_opcode = 0xb0;
3859 i.tm.extension_opcode = None;
3860 i.tm.opcode_modifier.shortform = 1;
3861 i.tm.opcode_modifier.modrm = 0;
3862 }
3863 }
3864 }
3865 else if (optimize > 1
3866 && i.reg_operands == 3
3867 && i.op[0].regs == i.op[1].regs
3868 && !i.types[2].bitfield.xmmword
3869 && (i.tm.opcode_modifier.vex
3870 || (!i.mask
3871 && !i.rounding
e771e7c9 3872 && is_evex_encoding (&i.tm)
b6f8c7c4
L		 3873 && cpu_arch_flags.bitfield.cpuavx512vl))
3874 && ((i.tm.base_opcode == 0x55
3875 || i.tm.base_opcode == 0x6655
3876 || i.tm.base_opcode == 0x66df
3877 || i.tm.base_opcode == 0x57
3878 || i.tm.base_opcode == 0x6657
8305403a
L		 3879 || i.tm.base_opcode == 0x66ef
3880 || i.tm.base_opcode == 0x66f8
3881 || i.tm.base_opcode == 0x66f9
3882 || i.tm.base_opcode == 0x66fa
3883 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3884 && i.tm.extension_opcode == None))
3885 {
3886 /* Optimize: -O2:
8305403a
L		 3887 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3888 vpsubq and vpsubw:
b6f8c7c4
L		 3889 EVEX VOP %zmmM, %zmmM, %zmmN
3890 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3891 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3892 EVEX VOP %ymmM, %ymmM, %ymmN
3893 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3894 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3895 VEX VOP %ymmM, %ymmM, %ymmN
3896 -> VEX VOP %xmmM, %xmmM, %xmmN
3897 VOP, one of vpandn and vpxor:
3898 VEX VOP %ymmM, %ymmM, %ymmN
3899 -> VEX VOP %xmmM, %xmmM, %xmmN
3900 VOP, one of vpandnd and vpandnq:
3901 EVEX VOP %zmmM, %zmmM, %zmmN
3902 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3903 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3904 EVEX VOP %ymmM, %ymmM, %ymmN
3905 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3906 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3907 VOP, one of vpxord and vpxorq:
3908 EVEX VOP %zmmM, %zmmM, %zmmN
3909 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3910 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3911 EVEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 */
e771e7c9 3915 if (is_evex_encoding (&i.tm))
b6f8c7c4
L		 3916 {
3917 /* If only lower 16 vector registers are used, we can use
3918 VEX encoding. */
3919 for (j = 0; j < 3; j++)
3920 if (register_number (i.op[j].regs) > 15)
3921 break;
3922
3923 if (j < 3)
3924 i.tm.opcode_modifier.evex = EVEX128;
3925 else
3926 {
3927 i.tm.opcode_modifier.vex = VEX128;
3928 i.tm.opcode_modifier.vexw = VEXW0;
3929 i.tm.opcode_modifier.evex = 0;
3930 }
3931 }
3932 else
3933 i.tm.opcode_modifier.vex = VEX128;
3934
3935 if (i.tm.opcode_modifier.vex)
3936 for (j = 0; j < 3; j++)
3937 {
3938 i.types[j].bitfield.xmmword = 1;
3939 i.types[j].bitfield.ymmword = 0;
3940 }
3941 }
3942}
3943
252b5132
RH		 3944/* This is the guts of the machine-dependent assembler. LINE points to a
3945 machine dependent instruction. This function is supposed to emit
3946 the frags/bytes it assembles to. */
3947
3948void
65da13b5 3949md_assemble (char *line)
252b5132 3950{
40fb9820 3951 unsigned int j;
83b16ac6 3952 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3953 const insn_template *t;
252b5132 3954
47926f60 3955 /* Initialize globals. */
252b5132
RH		 3956 memset (&i, '\0', sizeof (i));
3957 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3958 i.reloc[j] = NO_RELOC;
252b5132
RH		 3959 memset (disp_expressions, '\0', sizeof (disp_expressions));
3960 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3961 save_stack_p = save_stack;
252b5132
RH		 3962
3963 /* First parse an instruction mnemonic & call i386_operand for the operands.
3964 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3965 start of a (possibly prefixed) mnemonic. */
252b5132 3966
29b0f896
AM		 3967 line = parse_insn (line, mnemonic);
3968 if (line == NULL)
3969 return;
83b16ac6 3970 mnem_suffix = i.suffix;
252b5132 3971
29b0f896 3972 line = parse_operands (line, mnemonic);
ee86248c 3973 this_operand = -1;
8325cc63
JB		 3974 xfree (i.memop1_string);
3975 i.memop1_string = NULL;
29b0f896
AM		 3976 if (line == NULL)
3977 return;
252b5132 3978
29b0f896
AM		 3979 /* Now we've parsed the mnemonic into a set of templates, and have the
3980 operands at hand. */
3981
3982 /* All intel opcodes have reversed operands except for "bound" and
3983 "enter". We also don't reverse intersegment "jmp" and "call"
3984 instructions with 2 immediate operands so that the immediate segment
050dfa73 3985 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3986 if (intel_syntax
3987 && i.operands > 1
29b0f896 3988 && (strcmp (mnemonic, "bound") != 0)
30123838 3989 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3990 && !(operand_type_check (i.types[0], imm)
3991 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3992 swap_operands ();
3993
ec56d5c0
JB		 3994 /* The order of the immediates should be reversed
3995 for 2 immediates extrq and insertq instructions */
3996 if (i.imm_operands == 2
3997 && (strcmp (mnemonic, "extrq") == 0
3998 || strcmp (mnemonic, "insertq") == 0))
3999 swap_2_operands (0, 1);
4000
29b0f896
AM		 4001 if (i.imm_operands)
4002 optimize_imm ();
4003
b300c311
L		 4004 /* Don't optimize displacement for movabs since it only takes 64bit
4005 displacement. */
4006 if (i.disp_operands
a501d77e 4007 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4008 && (flag_code != CODE_64BIT
4009 || strcmp (mnemonic, "movabs") != 0))
4010 optimize_disp ();
29b0f896
AM		 4011
4012 /* Next, we find a template that matches the given insn,
4013 making sure the overlap of the given operands types is consistent
4014 with the template operand types. */
252b5132 4015
83b16ac6 4016 if (!(t = match_template (mnem_suffix)))
29b0f896 4017 return;
252b5132 4018
7bab8ab5 4019 if (sse_check != check_none
81f8a913 4020 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4021 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4022 && (i.tm.cpu_flags.bitfield.cpusse
4023 || i.tm.cpu_flags.bitfield.cpusse2
4024 || i.tm.cpu_flags.bitfield.cpusse3
4025 || i.tm.cpu_flags.bitfield.cpussse3
4026 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4027 || i.tm.cpu_flags.bitfield.cpusse4_2
4028 || i.tm.cpu_flags.bitfield.cpupclmul
4029 || i.tm.cpu_flags.bitfield.cpuaes
4030 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4031 {
7bab8ab5 4032 (sse_check == check_warning
daf50ae7
L		 4033 ? as_warn
4034 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4035 }
4036
321fd21e
L		 4037 /* Zap movzx and movsx suffix. The suffix has been set from
4038 "word ptr" or "byte ptr" on the source operand in Intel syntax
4039 or extracted from mnemonic in AT&T syntax. But we'll use
4040 the destination register to choose the suffix for encoding. */
4041 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4042 {
321fd21e
L		 4043 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4044 there is no suffix, the default will be byte extension. */
4045 if (i.reg_operands != 2
4046 && !i.suffix
7ab9ffdd 4047 && intel_syntax)
321fd21e
L		 4048 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4049
4050 i.suffix = 0;
cd61ebfe 4051 }
24eab124 4052
40fb9820 4053 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4054 if (!add_prefix (FWAIT_OPCODE))
4055 return;
252b5132 4056
d5de92cf
L		 4057 /* Check if REP prefix is OK. */
4058 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4059 {
4060 as_bad (_("invalid instruction `%s' after `%s'"),
4061 i.tm.name, i.rep_prefix);
4062 return;
4063 }
4064
c1ba0266
L		 4065 /* Check for lock without a lockable instruction. Destination operand
4066 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4067 if (i.prefix[LOCK_PREFIX]
4068 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4069 || i.mem_operands == 0
4070 || (i.tm.base_opcode != 0x86
4071 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4072 {
4073 as_bad (_("expecting lockable instruction after `lock'"));
4074 return;
4075 }
4076
42164a71 4077 /* Check if HLE prefix is OK. */
165de32a 4078 if (i.hle_prefix && !check_hle ())
42164a71
L		 4079 return;
4080
7e8b059b
L		 4081 /* Check BND prefix. */
4082 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4083 as_bad (_("expecting valid branch instruction after `bnd'"));
4084
04ef582a 4085 /* Check NOTRACK prefix. */
9fef80d6
L		 4086 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4087 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4088
327e8c42
JB		 4089 if (i.tm.cpu_flags.bitfield.cpumpx)
4090 {
4091 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4092 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4093 else if (flag_code != CODE_16BIT
4094 ? i.prefix[ADDR_PREFIX]
4095 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4096 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4097 }
7e8b059b
L		 4098
4099 /* Insert BND prefix. */
4100 if (add_bnd_prefix
4101 && i.tm.opcode_modifier.bndprefixok
4102 && !i.prefix[BND_PREFIX])
4103 add_prefix (BND_PREFIX_OPCODE);
4104
29b0f896 4105 /* Check string instruction segment overrides. */
40fb9820 4106 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4107 {
4108 if (!check_string ())
5dd0794d 4109 return;
fc0763e6 4110 i.disp_operands = 0;
29b0f896 4111 }
5dd0794d 4112
b6f8c7c4
L		 4113 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4114 optimize_encoding ();
4115
29b0f896
AM		 4116 if (!process_suffix ())
4117 return;
e413e4e9 4118
bc0844ae
L		 4119 /* Update operand types. */
4120 for (j = 0; j < i.operands; j++)
4121 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4122
29b0f896
AM		 4123 /* Make still unresolved immediate matches conform to size of immediate
4124 given in i.suffix. */
4125 if (!finalize_imm ())
4126 return;
252b5132 4127
40fb9820 4128 if (i.types[0].bitfield.imm1)
29b0f896 4129 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4130
9afe6eb8
L		 4131 /* We only need to check those implicit registers for instructions
4132 with 3 operands or less. */
4133 if (i.operands <= 3)
4134 for (j = 0; j < i.operands; j++)
4135 if (i.types[j].bitfield.inoutportreg
4136 || i.types[j].bitfield.shiftcount
1b54b8d7 4137 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4138 i.reg_operands--;
40fb9820 4139
c0f3af97
L		 4140 /* ImmExt should be processed after SSE2AVX. */
4141 if (!i.tm.opcode_modifier.sse2avx
4142 && i.tm.opcode_modifier.immext)
65da13b5 4143 process_immext ();
252b5132 4144
29b0f896
AM		 4145 /* For insns with operands there are more diddles to do to the opcode. */
4146 if (i.operands)
4147 {
4148 if (!process_operands ())
4149 return;
4150 }
40fb9820 4151 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4152 {
4153 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4154 as_warn (_("translating to `%sp'"), i.tm.name);
4155 }
252b5132 4156
e771e7c9
JB		 4157 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4158 || is_evex_encoding (&i.tm))
9e5e5283
L		 4159 {
4160 if (flag_code == CODE_16BIT)
4161 {
4162 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4163 i.tm.name);
4164 return;
4165 }
c0f3af97 4166
9e5e5283
L		 4167 if (i.tm.opcode_modifier.vex)
4168 build_vex_prefix (t);
4169 else
4170 build_evex_prefix ();
4171 }
43234a1e 4172
5dd85c99
SP		 4173 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4174 instructions may define INT_OPCODE as well, so avoid this corner
4175 case for those instructions that use MODRM. */
4176 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4177 && !i.tm.opcode_modifier.modrm
4178 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4179 {
4180 i.tm.base_opcode = INT3_OPCODE;
4181 i.imm_operands = 0;
4182 }
252b5132 4183
40fb9820
L		 4184 if ((i.tm.opcode_modifier.jump
4185 || i.tm.opcode_modifier.jumpbyte
4186 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4187 && i.op[0].disps->X_op == O_constant)
4188 {
4189 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4190 the absolute address given by the constant. Since ix86 jumps and
4191 calls are pc relative, we need to generate a reloc. */
4192 i.op[0].disps->X_add_symbol = &abs_symbol;
4193 i.op[0].disps->X_op = O_symbol;
4194 }
252b5132 4195
40fb9820 4196 if (i.tm.opcode_modifier.rex64)
161a04f6 4197 i.rex |= REX_W;
252b5132 4198
29b0f896
AM		 4199 /* For 8 bit registers we need an empty rex prefix. Also if the
4200 instruction already has a prefix, we need to convert old
4201 registers to new ones. */
773f551c 4202
dc821c5f 4203 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4204 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4205 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4206 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4207 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4208 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4209 && i.rex != 0))
4210 {
4211 int x;
726c5dcd 4212
29b0f896
AM		 4213 i.rex |= REX_OPCODE;
4214 for (x = 0; x < 2; x++)
4215 {
4216 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4217 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4218 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4219 {
29b0f896
AM		 4220 /* In case it is "hi" register, give up. */
4221 if (i.op[x].regs->reg_num > 3)
a540244d 4222 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4223 "instruction requiring REX prefix."),
a540244d 4224 register_prefix, i.op[x].regs->reg_name);
773f551c 4225
29b0f896
AM		 4226 /* Otherwise it is equivalent to the extended register.
4227 Since the encoding doesn't change this is merely
4228 cosmetic cleanup for debug output. */
4229
4230 i.op[x].regs = i.op[x].regs + 8;
773f551c 4231 }
29b0f896
AM		 4232 }
4233 }
773f551c 4234
6b6b6807
L		 4235 if (i.rex == 0 && i.rex_encoding)
4236 {
4237 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4238 that uses legacy register. If it is "hi" register, don't add
4239 the REX_OPCODE byte. */
4240 int x;
4241 for (x = 0; x < 2; x++)
4242 if (i.types[x].bitfield.reg
4243 && i.types[x].bitfield.byte
4244 && (i.op[x].regs->reg_flags & RegRex64) == 0
4245 && i.op[x].regs->reg_num > 3)
4246 {
4247 i.rex_encoding = FALSE;
4248 break;
4249 }
4250
4251 if (i.rex_encoding)
4252 i.rex = REX_OPCODE;
4253 }
4254
7ab9ffdd 4255 if (i.rex != 0)
29b0f896
AM		 4256 add_prefix (REX_OPCODE | i.rex);
4257
4258 /* We are ready to output the insn. */
4259 output_insn ();
4260}
4261
4262static char *
e3bb37b5 4263parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4264{
4265 char *l = line;
4266 char *token_start = l;
4267 char *mnem_p;
5c6af06e 4268 int supported;
d3ce72d0 4269 const insn_template *t;
b6169b20 4270 char *dot_p = NULL;
29b0f896 4271
29b0f896
AM		 4272 while (1)
4273 {
4274 mnem_p = mnemonic;
4275 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4276 {
b6169b20
L		 4277 if (*mnem_p == '.')
4278 dot_p = mnem_p;
29b0f896
AM		 4279 mnem_p++;
4280 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4281 {
29b0f896
AM		 4282 as_bad (_("no such instruction: `%s'"), token_start);
4283 return NULL;
4284 }
4285 l++;
4286 }
4287 if (!is_space_char (*l)
4288 && *l != END_OF_INSN
e44823cf
JB		 4289 && (intel_syntax
4290 || (*l != PREFIX_SEPARATOR
4291 && *l != ',')))
29b0f896
AM		 4292 {
4293 as_bad (_("invalid character %s in mnemonic"),
4294 output_invalid (*l));
4295 return NULL;
4296 }
4297 if (token_start == l)
4298 {
e44823cf 4299 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4300 as_bad (_("expecting prefix; got nothing"));
4301 else
4302 as_bad (_("expecting mnemonic; got nothing"));
4303 return NULL;
4304 }
45288df1 4305
29b0f896 4306 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4307 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4308
29b0f896
AM		 4309 if (*l != END_OF_INSN
4310 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4311 && current_templates
40fb9820 4312 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4313 {
c6fb90c8 4314 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4315 {
4316 as_bad ((flag_code != CODE_64BIT
4317 ? _("`%s' is only supported in 64-bit mode")
4318 : _("`%s' is not supported in 64-bit mode")),
4319 current_templates->start->name);
4320 return NULL;
4321 }
29b0f896
AM		 4322 /* If we are in 16-bit mode, do not allow addr16 or data16.
4323 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4324 if ((current_templates->start->opcode_modifier.size16
4325 || current_templates->start->opcode_modifier.size32)
29b0f896 4326 && flag_code != CODE_64BIT
40fb9820 4327 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4328 ^ (flag_code == CODE_16BIT)))
4329 {
4330 as_bad (_("redundant %s prefix"),
4331 current_templates->start->name);
4332 return NULL;
45288df1 4333 }
86fa6981 4334 if (current_templates->start->opcode_length == 0)
29b0f896 4335 {
86fa6981
L		 4336 /* Handle pseudo prefixes. */
4337 switch (current_templates->start->base_opcode)
4338 {
4339 case 0x0:
4340 /* {disp8} */
4341 i.disp_encoding = disp_encoding_8bit;
4342 break;
4343 case 0x1:
4344 /* {disp32} */
4345 i.disp_encoding = disp_encoding_32bit;
4346 break;
4347 case 0x2:
4348 /* {load} */
4349 i.dir_encoding = dir_encoding_load;
4350 break;
4351 case 0x3:
4352 /* {store} */
4353 i.dir_encoding = dir_encoding_store;
4354 break;
4355 case 0x4:
4356 /* {vex2} */
4357 i.vec_encoding = vex_encoding_vex2;
4358 break;
4359 case 0x5:
4360 /* {vex3} */
4361 i.vec_encoding = vex_encoding_vex3;
4362 break;
4363 case 0x6:
4364 /* {evex} */
4365 i.vec_encoding = vex_encoding_evex;
4366 break;
6b6b6807
L		 4367 case 0x7:
4368 /* {rex} */
4369 i.rex_encoding = TRUE;
4370 break;
b6f8c7c4
L		 4371 case 0x8:
4372 /* {nooptimize} */
4373 i.no_optimize = TRUE;
4374 break;
86fa6981
L		 4375 default:
4376 abort ();
4377 }
4378 }
4379 else
4380 {
4381 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4382 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4383 {
4e9ac44a
L		 4384 case PREFIX_EXIST:
4385 return NULL;
4386 case PREFIX_DS:
d777820b 4387 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4388 i.notrack_prefix = current_templates->start->name;
4389 break;
4390 case PREFIX_REP:
4391 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4392 i.hle_prefix = current_templates->start->name;
4393 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4394 i.bnd_prefix = current_templates->start->name;
4395 else
4396 i.rep_prefix = current_templates->start->name;
4397 break;
4398 default:
4399 break;
86fa6981 4400 }
29b0f896
AM		 4401 }
4402 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4403 token_start = ++l;
4404 }
4405 else
4406 break;
4407 }
45288df1 4408
30a55f88 4409 if (!current_templates)
b6169b20 4410 {
f8a5c266
L		 4411 /* Check if we should swap operand or force 32bit displacement in
4412 encoding. */
30a55f88 4413 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4414 i.dir_encoding = dir_encoding_store;
8d63c93e 4415 else if (mnem_p - 3 == dot_p
a501d77e
L		 4416 && dot_p[1] == 'd'
4417 && dot_p[2] == '8')
4418 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4419 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4420 && dot_p[1] == 'd'
4421 && dot_p[2] == '3'
4422 && dot_p[3] == '2')
a501d77e 4423 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4424 else
4425 goto check_suffix;
4426 mnem_p = dot_p;
4427 *dot_p = '\0';
d3ce72d0 4428 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4429 }
4430
29b0f896
AM		 4431 if (!current_templates)
4432 {
b6169b20 4433check_suffix:
29b0f896
AM		 4434 /* See if we can get a match by trimming off a suffix. */
4435 switch (mnem_p[-1])
4436 {
4437 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4438 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4439 i.suffix = SHORT_MNEM_SUFFIX;
4440 else
1a0670f3 4441 /* Fall through. */
29b0f896
AM		 4442 case BYTE_MNEM_SUFFIX:
4443 case QWORD_MNEM_SUFFIX:
4444 i.suffix = mnem_p[-1];
4445 mnem_p[-1] = '\0';
d3ce72d0
NC		 4446 current_templates = (const templates *) hash_find (op_hash,
4447 mnemonic);
29b0f896
AM		 4448 break;
4449 case SHORT_MNEM_SUFFIX:
4450 case LONG_MNEM_SUFFIX:
4451 if (!intel_syntax)
4452 {
4453 i.suffix = mnem_p[-1];
4454 mnem_p[-1] = '\0';
d3ce72d0
NC		 4455 current_templates = (const templates *) hash_find (op_hash,
4456 mnemonic);
29b0f896
AM		 4457 }
4458 break;
252b5132 4459
29b0f896
AM		 4460 /* Intel Syntax. */
4461 case 'd':
4462 if (intel_syntax)
4463 {
9306ca4a 4464 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4465 i.suffix = SHORT_MNEM_SUFFIX;
4466 else
4467 i.suffix = LONG_MNEM_SUFFIX;
4468 mnem_p[-1] = '\0';
d3ce72d0
NC		 4469 current_templates = (const templates *) hash_find (op_hash,
4470 mnemonic);
29b0f896
AM		 4471 }
4472 break;
4473 }
4474 if (!current_templates)
4475 {
4476 as_bad (_("no such instruction: `%s'"), token_start);
4477 return NULL;
4478 }
4479 }
252b5132 4480
40fb9820
L		 4481 if (current_templates->start->opcode_modifier.jump
4482 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4483 {
4484 /* Check for a branch hint. We allow ",pt" and ",pn" for
4485 predict taken and predict not taken respectively.
4486 I'm not sure that branch hints actually do anything on loop
4487 and jcxz insns (JumpByte) for current Pentium4 chips. They
4488 may work in the future and it doesn't hurt to accept them
4489 now. */
4490 if (l[0] == ',' && l[1] == 'p')
4491 {
4492 if (l[2] == 't')
4493 {
4494 if (!add_prefix (DS_PREFIX_OPCODE))
4495 return NULL;
4496 l += 3;
4497 }
4498 else if (l[2] == 'n')
4499 {
4500 if (!add_prefix (CS_PREFIX_OPCODE))
4501 return NULL;
4502 l += 3;
4503 }
4504 }
4505 }
4506 /* Any other comma loses. */
4507 if (*l == ',')
4508 {
4509 as_bad (_("invalid character %s in mnemonic"),
4510 output_invalid (*l));
4511 return NULL;
4512 }
252b5132 4513
29b0f896 4514 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4515 supported = 0;
4516 for (t = current_templates->start; t < current_templates->end; ++t)
4517 {
c0f3af97
L		 4518 supported |= cpu_flags_match (t);
4519 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4520 {
4521 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4522 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4523
548d0ee6
JB		 4524 return l;
4525 }
29b0f896 4526 }
3629bb00 4527
548d0ee6
JB		 4528 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4529 as_bad (flag_code == CODE_64BIT
4530 ? _("`%s' is not supported in 64-bit mode")
4531 : _("`%s' is only supported in 64-bit mode"),
4532 current_templates->start->name);
4533 else
4534 as_bad (_("`%s' is not supported on `%s%s'"),
4535 current_templates->start->name,
4536 cpu_arch_name ? cpu_arch_name : default_arch,
4537 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4538
548d0ee6 4539 return NULL;
29b0f896 4540}
252b5132 4541
29b0f896 4542static char *
e3bb37b5 4543parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4544{
4545 char *token_start;
3138f287 4546
29b0f896
AM		 4547 /* 1 if operand is pending after ','. */
4548 unsigned int expecting_operand = 0;
252b5132 4549
29b0f896
AM		 4550 /* Non-zero if operand parens not balanced. */
4551 unsigned int paren_not_balanced;
4552
4553 while (*l != END_OF_INSN)
4554 {
4555 /* Skip optional white space before operand. */
4556 if (is_space_char (*l))
4557 ++l;
d02603dc 4558 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4559 {
4560 as_bad (_("invalid character %s before operand %d"),
4561 output_invalid (*l),
4562 i.operands + 1);
4563 return NULL;
4564 }
d02603dc 4565 token_start = l; /* After white space. */
29b0f896
AM		 4566 paren_not_balanced = 0;
4567 while (paren_not_balanced || *l != ',')
4568 {
4569 if (*l == END_OF_INSN)
4570 {
4571 if (paren_not_balanced)
4572 {
4573 if (!intel_syntax)
4574 as_bad (_("unbalanced parenthesis in operand %d."),
4575 i.operands + 1);
4576 else
4577 as_bad (_("unbalanced brackets in operand %d."),
4578 i.operands + 1);
4579 return NULL;
4580 }
4581 else
4582 break; /* we are done */
4583 }
d02603dc 4584 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4585 {
4586 as_bad (_("invalid character %s in operand %d"),
4587 output_invalid (*l),
4588 i.operands + 1);
4589 return NULL;
4590 }
4591 if (!intel_syntax)
4592 {
4593 if (*l == '(')
4594 ++paren_not_balanced;
4595 if (*l == ')')
4596 --paren_not_balanced;
4597 }
4598 else
4599 {
4600 if (*l == '[')
4601 ++paren_not_balanced;
4602 if (*l == ']')
4603 --paren_not_balanced;
4604 }
4605 l++;
4606 }
4607 if (l != token_start)
4608 { /* Yes, we've read in another operand. */
4609 unsigned int operand_ok;
4610 this_operand = i.operands++;
4611 if (i.operands > MAX_OPERANDS)
4612 {
4613 as_bad (_("spurious operands; (%d operands/instruction max)"),
4614 MAX_OPERANDS);
4615 return NULL;
4616 }
9d46ce34 4617 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4618 /* Now parse operand adding info to 'i' as we go along. */
4619 END_STRING_AND_SAVE (l);
4620
4621 if (intel_syntax)
4622 operand_ok =
4623 i386_intel_operand (token_start,
4624 intel_float_operand (mnemonic));
4625 else
a7619375 4626 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4627
4628 RESTORE_END_STRING (l);
4629 if (!operand_ok)
4630 return NULL;
4631 }
4632 else
4633 {
4634 if (expecting_operand)
4635 {
4636 expecting_operand_after_comma:
4637 as_bad (_("expecting operand after ','; got nothing"));
4638 return NULL;
4639 }
4640 if (*l == ',')
4641 {
4642 as_bad (_("expecting operand before ','; got nothing"));
4643 return NULL;
4644 }
4645 }
7f3f1ea2 4646
29b0f896
AM		 4647 /* Now *l must be either ',' or END_OF_INSN. */
4648 if (*l == ',')
4649 {
4650 if (*++l == END_OF_INSN)
4651 {
4652 /* Just skip it, if it's \n complain. */
4653 goto expecting_operand_after_comma;
4654 }
4655 expecting_operand = 1;
4656 }
4657 }
4658 return l;
4659}
7f3f1ea2 4660
050dfa73 4661static void
4d456e3d 4662swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4663{
4664 union i386_op temp_op;
40fb9820 4665 i386_operand_type temp_type;
050dfa73 4666 enum bfd_reloc_code_real temp_reloc;
4eed87de 4667
050dfa73
MM		 4668 temp_type = i.types[xchg2];
4669 i.types[xchg2] = i.types[xchg1];
4670 i.types[xchg1] = temp_type;
4671 temp_op = i.op[xchg2];
4672 i.op[xchg2] = i.op[xchg1];
4673 i.op[xchg1] = temp_op;
4674 temp_reloc = i.reloc[xchg2];
4675 i.reloc[xchg2] = i.reloc[xchg1];
4676 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4677
4678 if (i.mask)
4679 {
4680 if (i.mask->operand == xchg1)
4681 i.mask->operand = xchg2;
4682 else if (i.mask->operand == xchg2)
4683 i.mask->operand = xchg1;
4684 }
4685 if (i.broadcast)
4686 {
4687 if (i.broadcast->operand == xchg1)
4688 i.broadcast->operand = xchg2;
4689 else if (i.broadcast->operand == xchg2)
4690 i.broadcast->operand = xchg1;
4691 }
4692 if (i.rounding)
4693 {
4694 if (i.rounding->operand == xchg1)
4695 i.rounding->operand = xchg2;
4696 else if (i.rounding->operand == xchg2)
4697 i.rounding->operand = xchg1;
4698 }
050dfa73
MM		 4699}
4700
29b0f896 4701static void
e3bb37b5 4702swap_operands (void)
29b0f896 4703{
b7c61d9a 4704 switch (i.operands)
050dfa73 4705 {
c0f3af97 4706 case 5:
b7c61d9a 4707 case 4:
4d456e3d 4708 swap_2_operands (1, i.operands - 2);
1a0670f3 4709 /* Fall through. */
b7c61d9a
L		 4710 case 3:
4711 case 2:
4d456e3d 4712 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4713 break;
4714 default:
4715 abort ();
29b0f896 4716 }
29b0f896
AM		 4717
4718 if (i.mem_operands == 2)
4719 {
4720 const seg_entry *temp_seg;
4721 temp_seg = i.seg[0];
4722 i.seg[0] = i.seg[1];
4723 i.seg[1] = temp_seg;
4724 }
4725}
252b5132 4726
29b0f896
AM		 4727/* Try to ensure constant immediates are represented in the smallest
4728 opcode possible. */
4729static void
e3bb37b5 4730optimize_imm (void)
29b0f896
AM		 4731{
4732 char guess_suffix = 0;
4733 int op;
252b5132 4734
29b0f896
AM		 4735 if (i.suffix)
4736 guess_suffix = i.suffix;
4737 else if (i.reg_operands)
4738 {
4739 /* Figure out a suffix from the last register operand specified.
4740 We can't do this properly yet, ie. excluding InOutPortReg,
4741 but the following works for instructions with immediates.
4742 In any case, we can't set i.suffix yet. */
4743 for (op = i.operands; --op >= 0;)
dc821c5f 4744 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4745 {
40fb9820
L		 4746 guess_suffix = BYTE_MNEM_SUFFIX;
4747 break;
4748 }
dc821c5f 4749 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4750 {
40fb9820
L		 4751 guess_suffix = WORD_MNEM_SUFFIX;
4752 break;
4753 }
dc821c5f 4754 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4755 {
4756 guess_suffix = LONG_MNEM_SUFFIX;
4757 break;
4758 }
dc821c5f 4759 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4760 {
4761 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4762 break;
252b5132 4763 }
29b0f896
AM		 4764 }
4765 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4766 guess_suffix = WORD_MNEM_SUFFIX;
4767
4768 for (op = i.operands; --op >= 0;)
40fb9820 4769 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4770 {
4771 switch (i.op[op].imms->X_op)
252b5132 4772 {
29b0f896
AM		 4773 case O_constant:
4774 /* If a suffix is given, this operand may be shortened. */
4775 switch (guess_suffix)
252b5132 4776 {
29b0f896 4777 case LONG_MNEM_SUFFIX:
40fb9820
L		 4778 i.types[op].bitfield.imm32 = 1;
4779 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4780 break;
4781 case WORD_MNEM_SUFFIX:
40fb9820
L		 4782 i.types[op].bitfield.imm16 = 1;
4783 i.types[op].bitfield.imm32 = 1;
4784 i.types[op].bitfield.imm32s = 1;
4785 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4786 break;
4787 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4788 i.types[op].bitfield.imm8 = 1;
4789 i.types[op].bitfield.imm8s = 1;
4790 i.types[op].bitfield.imm16 = 1;
4791 i.types[op].bitfield.imm32 = 1;
4792 i.types[op].bitfield.imm32s = 1;
4793 i.types[op].bitfield.imm64 = 1;
29b0f896 4794 break;
252b5132 4795 }
252b5132 4796
29b0f896
AM		 4797 /* If this operand is at most 16 bits, convert it
4798 to a signed 16 bit number before trying to see
4799 whether it will fit in an even smaller size.
4800 This allows a 16-bit operand such as $0xffe0 to
4801 be recognised as within Imm8S range. */
40fb9820 4802 if ((i.types[op].bitfield.imm16)
29b0f896 4803 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4804 {
29b0f896
AM		 4805 i.op[op].imms->X_add_number =
4806 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4807 }
a28def75
L		 4808#ifdef BFD64
4809 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4810 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4811 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4812 == 0))
4813 {
4814 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4815 ^ ((offsetT) 1 << 31))
4816 - ((offsetT) 1 << 31));
4817 }
a28def75 4818#endif
40fb9820 4819 i.types[op]
c6fb90c8
L		 4820 = operand_type_or (i.types[op],
4821 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4822
29b0f896
AM		 4823 /* We must avoid matching of Imm32 templates when 64bit
4824 only immediate is available. */
4825 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4826 i.types[op].bitfield.imm32 = 0;
29b0f896 4827 break;
252b5132 4828
29b0f896
AM		 4829 case O_absent:
4830 case O_register:
4831 abort ();
4832
4833 /* Symbols and expressions. */
4834 default:
9cd96992
JB		 4835 /* Convert symbolic operand to proper sizes for matching, but don't
4836 prevent matching a set of insns that only supports sizes other
4837 than those matching the insn suffix. */
4838 {
40fb9820 4839 i386_operand_type mask, allowed;
d3ce72d0 4840 const insn_template *t;
9cd96992 4841
0dfbf9d7
L		 4842 operand_type_set (&mask, 0);
4843 operand_type_set (&allowed, 0);
40fb9820 4844
4eed87de
AM		 4845 for (t = current_templates->start;
4846 t < current_templates->end;
4847 ++t)
c6fb90c8
L		 4848 allowed = operand_type_or (allowed,
4849 t->operand_types[op]);
9cd96992
JB		 4850 switch (guess_suffix)
4851 {
4852 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4853 mask.bitfield.imm64 = 1;
4854 mask.bitfield.imm32s = 1;
9cd96992
JB		 4855 break;
4856 case LONG_MNEM_SUFFIX:
40fb9820 4857 mask.bitfield.imm32 = 1;
9cd96992
JB		 4858 break;
4859 case WORD_MNEM_SUFFIX:
40fb9820 4860 mask.bitfield.imm16 = 1;
9cd96992
JB		 4861 break;
4862 case BYTE_MNEM_SUFFIX:
40fb9820 4863 mask.bitfield.imm8 = 1;
9cd96992
JB		 4864 break;
4865 default:
9cd96992
JB		 4866 break;
4867 }
c6fb90c8 4868 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4869 if (!operand_type_all_zero (&allowed))
c6fb90c8 4870 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4871 }
29b0f896 4872 break;
252b5132 4873 }
29b0f896
AM		 4874 }
4875}
47926f60 4876
29b0f896
AM		 4877/* Try to use the smallest displacement type too. */
4878static void
e3bb37b5 4879optimize_disp (void)
29b0f896
AM		 4880{
4881 int op;
3e73aa7c 4882
29b0f896 4883 for (op = i.operands; --op >= 0;)
40fb9820 4884 if (operand_type_check (i.types[op], disp))
252b5132 4885 {
b300c311 4886 if (i.op[op].disps->X_op == O_constant)
252b5132 4887 {
91d6fa6a 4888 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4889
40fb9820 4890 if (i.types[op].bitfield.disp16
91d6fa6a 4891 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4892 {
4893 /* If this operand is at most 16 bits, convert
4894 to a signed 16 bit number and don't use 64bit
4895 displacement. */
91d6fa6a 4896 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4897 i.types[op].bitfield.disp64 = 0;
b300c311 4898 }
a28def75
L		 4899#ifdef BFD64
4900 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4901 if (i.types[op].bitfield.disp32
91d6fa6a 4902 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4903 {
4904 /* If this operand is at most 32 bits, convert
4905 to a signed 32 bit number and don't use 64bit
4906 displacement. */
91d6fa6a
NC		 4907 op_disp &= (((offsetT) 2 << 31) - 1);
4908 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4909 i.types[op].bitfield.disp64 = 0;
b300c311 4910 }
a28def75 4911#endif
91d6fa6a 4912 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4913 {
40fb9820
L		 4914 i.types[op].bitfield.disp8 = 0;
4915 i.types[op].bitfield.disp16 = 0;
4916 i.types[op].bitfield.disp32 = 0;
4917 i.types[op].bitfield.disp32s = 0;
4918 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4919 i.op[op].disps = 0;
4920 i.disp_operands--;
4921 }
4922 else if (flag_code == CODE_64BIT)
4923 {
91d6fa6a 4924 if (fits_in_signed_long (op_disp))
28a9d8f5 4925 {
40fb9820
L		 4926 i.types[op].bitfield.disp64 = 0;
4927 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4928 }
0e1147d9 4929 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4930 && fits_in_unsigned_long (op_disp))
40fb9820 4931 i.types[op].bitfield.disp32 = 1;
b300c311 4932 }
40fb9820
L		 4933 if ((i.types[op].bitfield.disp32
4934 || i.types[op].bitfield.disp32s
4935 || i.types[op].bitfield.disp16)
b5014f7a 4936 && fits_in_disp8 (op_disp))
40fb9820 4937 i.types[op].bitfield.disp8 = 1;
252b5132 4938 }
67a4f2b7
AO		 4939 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4940 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4941 {
4942 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4943 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4944 i.types[op].bitfield.disp8 = 0;
4945 i.types[op].bitfield.disp16 = 0;
4946 i.types[op].bitfield.disp32 = 0;
4947 i.types[op].bitfield.disp32s = 0;
4948 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4949 }
4950 else
b300c311 4951 /* We only support 64bit displacement on constants. */
40fb9820 4952 i.types[op].bitfield.disp64 = 0;
252b5132 4953 }
29b0f896
AM		 4954}
4955
6c30d220
L		 4956/* Check if operands are valid for the instruction. */
4957
4958static int
4959check_VecOperands (const insn_template *t)
4960{
43234a1e
L		 4961 unsigned int op;
4962
6c30d220
L		 4963 /* Without VSIB byte, we can't have a vector register for index. */
4964 if (!t->opcode_modifier.vecsib
4965 && i.index_reg
1b54b8d7
JB		 4966 && (i.index_reg->reg_type.bitfield.xmmword
4967 || i.index_reg->reg_type.bitfield.ymmword
4968 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4969 {
4970 i.error = unsupported_vector_index_register;
4971 return 1;
4972 }
4973
ad8ecc81
MZ		 4974 /* Check if default mask is allowed. */
4975 if (t->opcode_modifier.nodefmask
4976 && (!i.mask || i.mask->mask->reg_num == 0))
4977 {
4978 i.error = no_default_mask;
4979 return 1;
4980 }
4981
7bab8ab5
JB		 4982 /* For VSIB byte, we need a vector register for index, and all vector
4983 registers must be distinct. */
4984 if (t->opcode_modifier.vecsib)
4985 {
4986 if (!i.index_reg
6c30d220 4987 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4988 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4989 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4990 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4991 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4992 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4993 {
4994 i.error = invalid_vsib_address;
4995 return 1;
4996 }
4997
43234a1e
L		 4998 gas_assert (i.reg_operands == 2 || i.mask);
4999 if (i.reg_operands == 2 && !i.mask)
5000 {
1b54b8d7
JB		 5001 gas_assert (i.types[0].bitfield.regsimd);
5002 gas_assert (i.types[0].bitfield.xmmword
5003 || i.types[0].bitfield.ymmword);
5004 gas_assert (i.types[2].bitfield.regsimd);
5005 gas_assert (i.types[2].bitfield.xmmword
5006 || i.types[2].bitfield.ymmword);
43234a1e
L		 5007 if (operand_check == check_none)
5008 return 0;
5009 if (register_number (i.op[0].regs)
5010 != register_number (i.index_reg)
5011 && register_number (i.op[2].regs)
5012 != register_number (i.index_reg)
5013 && register_number (i.op[0].regs)
5014 != register_number (i.op[2].regs))
5015 return 0;
5016 if (operand_check == check_error)
5017 {
5018 i.error = invalid_vector_register_set;
5019 return 1;
5020 }
5021 as_warn (_("mask, index, and destination registers should be distinct"));
5022 }
8444f82a
MZ		 5023 else if (i.reg_operands == 1 && i.mask)
5024 {
1b54b8d7
JB		 5025 if (i.types[1].bitfield.regsimd
5026 && (i.types[1].bitfield.xmmword
5027 || i.types[1].bitfield.ymmword
5028 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5029 && (register_number (i.op[1].regs)
5030 == register_number (i.index_reg)))
5031 {
5032 if (operand_check == check_error)
5033 {
5034 i.error = invalid_vector_register_set;
5035 return 1;
5036 }
5037 if (operand_check != check_none)
5038 as_warn (_("index and destination registers should be distinct"));
5039 }
5040 }
43234a1e 5041 }
7bab8ab5 5042
43234a1e
L		 5043 /* Check if broadcast is supported by the instruction and is applied
5044 to the memory operand. */
5045 if (i.broadcast)
5046 {
5047 int broadcasted_opnd_size;
5048
5049 /* Check if specified broadcast is supported in this instruction,
5050 and it's applied to memory operand of DWORD or QWORD type,
5051 depending on VecESize. */
5052 if (i.broadcast->type != t->opcode_modifier.broadcast
5053 || !i.types[i.broadcast->operand].bitfield.mem
5054 || (t->opcode_modifier.vecesize == 0
5055 && !i.types[i.broadcast->operand].bitfield.dword
5056 && !i.types[i.broadcast->operand].bitfield.unspecified)
5057 || (t->opcode_modifier.vecesize == 1
5058 && !i.types[i.broadcast->operand].bitfield.qword
5059 && !i.types[i.broadcast->operand].bitfield.unspecified))
5060 goto bad_broadcast;
5061
5062 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5063 if (i.broadcast->type == BROADCAST_1TO16)
5064 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5065 else if (i.broadcast->type == BROADCAST_1TO8)
5066 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 5067 else if (i.broadcast->type == BROADCAST_1TO4)
5068 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5069 else if (i.broadcast->type == BROADCAST_1TO2)
5070 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 5071 else
5072 goto bad_broadcast;
5073
5074 if ((broadcasted_opnd_size == 256
5075 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5076 || (broadcasted_opnd_size == 512
5077 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5078 {
5079 bad_broadcast:
5080 i.error = unsupported_broadcast;
5081 return 1;
5082 }
5083 }
5084 /* If broadcast is supported in this instruction, we need to check if
5085 operand of one-element size isn't specified without broadcast. */
5086 else if (t->opcode_modifier.broadcast && i.mem_operands)
5087 {
5088 /* Find memory operand. */
5089 for (op = 0; op < i.operands; op++)
5090 if (operand_type_check (i.types[op], anymem))
5091 break;
5092 gas_assert (op < i.operands);
5093 /* Check size of the memory operand. */
5094 if ((t->opcode_modifier.vecesize == 0
5095 && i.types[op].bitfield.dword)
5096 || (t->opcode_modifier.vecesize == 1
5097 && i.types[op].bitfield.qword))
5098 {
5099 i.error = broadcast_needed;
5100 return 1;
5101 }
5102 }
5103
5104 /* Check if requested masking is supported. */
5105 if (i.mask
5106 && (!t->opcode_modifier.masking
5107 || (i.mask->zeroing
5108 && t->opcode_modifier.masking == MERGING_MASKING)))
5109 {
5110 i.error = unsupported_masking;
5111 return 1;
5112 }
5113
5114 /* Check if masking is applied to dest operand. */
5115 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5116 {
5117 i.error = mask_not_on_destination;
5118 return 1;
5119 }
5120
43234a1e
L		 5121 /* Check RC/SAE. */
5122 if (i.rounding)
5123 {
5124 if ((i.rounding->type != saeonly
5125 && !t->opcode_modifier.staticrounding)
5126 || (i.rounding->type == saeonly
5127 && (t->opcode_modifier.staticrounding
5128 || !t->opcode_modifier.sae)))
5129 {
5130 i.error = unsupported_rc_sae;
5131 return 1;
5132 }
5133 /* If the instruction has several immediate operands and one of
5134 them is rounding, the rounding operand should be the last
5135 immediate operand. */
5136 if (i.imm_operands > 1
5137 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5138 {
43234a1e 5139 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5140 return 1;
5141 }
6c30d220
L		 5142 }
5143
43234a1e 5144 /* Check vector Disp8 operand. */
b5014f7a
JB		 5145 if (t->opcode_modifier.disp8memshift
5146 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5147 {
5148 if (i.broadcast)
5149 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5150 else
5151 i.memshift = t->opcode_modifier.disp8memshift;
5152
5153 for (op = 0; op < i.operands; op++)
5154 if (operand_type_check (i.types[op], disp)
5155 && i.op[op].disps->X_op == O_constant)
5156 {
b5014f7a 5157 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5158 {
b5014f7a
JB		 5159 i.types[op].bitfield.disp8 = 1;
5160 return 0;
43234a1e 5161 }
b5014f7a 5162 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5163 }
5164 }
b5014f7a
JB		 5165
5166 i.memshift = 0;
43234a1e 5167
6c30d220
L		 5168 return 0;
5169}
5170
43f3e2ee 5171/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5172 operand types. */
5173
5174static int
5175VEX_check_operands (const insn_template *t)
5176{
86fa6981 5177 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5178 {
86fa6981 5179 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5180 if (!is_evex_encoding (t))
86fa6981
L		 5181 {
5182 i.error = unsupported;
5183 return 1;
5184 }
5185 return 0;
43234a1e
L		 5186 }
5187
a683cc34 5188 if (!t->opcode_modifier.vex)
86fa6981
L		 5189 {
5190 /* This instruction template doesn't have VEX prefix. */
5191 if (i.vec_encoding != vex_encoding_default)
5192 {
5193 i.error = unsupported;
5194 return 1;
5195 }
5196 return 0;
5197 }
a683cc34
SP		 5198
5199 /* Only check VEX_Imm4, which must be the first operand. */
5200 if (t->operand_types[0].bitfield.vec_imm4)
5201 {
5202 if (i.op[0].imms->X_op != O_constant
5203 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5204 {
a65babc9 5205 i.error = bad_imm4;
891edac4
L		 5206 return 1;
5207 }
a683cc34
SP		 5208
5209 /* Turn off Imm8 so that update_imm won't complain. */
5210 i.types[0] = vec_imm4;
5211 }
5212
5213 return 0;
5214}
5215
d3ce72d0 5216static const insn_template *
83b16ac6 5217match_template (char mnem_suffix)
29b0f896
AM		 5218{
5219 /* Points to template once we've found it. */
d3ce72d0 5220 const insn_template *t;
40fb9820 5221 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5222 i386_operand_type overlap4;
29b0f896 5223 unsigned int found_reverse_match;
83b16ac6 5224 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5225 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5226 int addr_prefix_disp;
a5c311ca 5227 unsigned int j;
3629bb00 5228 unsigned int found_cpu_match;
45664ddb 5229 unsigned int check_register;
5614d22c 5230 enum i386_error specific_error = 0;
29b0f896 5231
c0f3af97
L		 5232#if MAX_OPERANDS != 5
5233# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5234#endif
5235
29b0f896 5236 found_reverse_match = 0;
539e75ad 5237 addr_prefix_disp = -1;
40fb9820
L		 5238
5239 memset (&suffix_check, 0, sizeof (suffix_check));
5240 if (i.suffix == BYTE_MNEM_SUFFIX)
5241 suffix_check.no_bsuf = 1;
5242 else if (i.suffix == WORD_MNEM_SUFFIX)
5243 suffix_check.no_wsuf = 1;
5244 else if (i.suffix == SHORT_MNEM_SUFFIX)
5245 suffix_check.no_ssuf = 1;
5246 else if (i.suffix == LONG_MNEM_SUFFIX)
5247 suffix_check.no_lsuf = 1;
5248 else if (i.suffix == QWORD_MNEM_SUFFIX)
5249 suffix_check.no_qsuf = 1;
5250 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5251 suffix_check.no_ldsuf = 1;
29b0f896 5252
83b16ac6
JB		 5253 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5254 if (intel_syntax)
5255 {
5256 switch (mnem_suffix)
5257 {
5258 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5259 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5260 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5261 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5262 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5263 }
5264 }
5265
01559ecc
L		 5266 /* Must have right number of operands. */
5267 i.error = number_of_operands_mismatch;
5268
45aa61fe 5269 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5270 {
539e75ad
L		 5271 addr_prefix_disp = -1;
5272
29b0f896
AM		 5273 if (i.operands != t->operands)
5274 continue;
5275
50aecf8c 5276 /* Check processor support. */
a65babc9 5277 i.error = unsupported;
c0f3af97
L		 5278 found_cpu_match = (cpu_flags_match (t)
5279 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5280 if (!found_cpu_match)
5281 continue;
5282
e1d4d893 5283 /* Check old gcc support. */
a65babc9 5284 i.error = old_gcc_only;
e1d4d893
L		 5285 if (!old_gcc && t->opcode_modifier.oldgcc)
5286 continue;
5287
5288 /* Check AT&T mnemonic. */
a65babc9 5289 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5290 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5291 continue;
5292
e92bae62 5293 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5294 i.error = unsupported_syntax;
5c07affc 5295 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5296 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5297 || (intel64 && t->opcode_modifier.amd64)
5298 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5299 continue;
5300
20592a94 5301 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5302 i.error = invalid_instruction_suffix;
567e4e96
L		 5303 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5304 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5305 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5306 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5307 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5308 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5309 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5310 continue;
83b16ac6
JB		 5311 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5312 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5313 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5314 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5315 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5316 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5317 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5318 continue;
29b0f896 5319
5c07affc 5320 if (!operand_size_match (t))
7d5e4556 5321 continue;
539e75ad 5322
5c07affc
L		 5323 for (j = 0; j < MAX_OPERANDS; j++)
5324 operand_types[j] = t->operand_types[j];
5325
45aa61fe
AM		 5326 /* In general, don't allow 64-bit operands in 32-bit mode. */
5327 if (i.suffix == QWORD_MNEM_SUFFIX
5328 && flag_code != CODE_64BIT
5329 && (intel_syntax
40fb9820 5330 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5331 && !intel_float_operand (t->name))
5332 : intel_float_operand (t->name) != 2)
40fb9820 5333 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5334 && !operand_types[0].bitfield.regsimd)
40fb9820 5335 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5336 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5337 && (t->base_opcode != 0x0fc7
5338 || t->extension_opcode != 1 /* cmpxchg8b */))
5339 continue;
5340
192dc9c6
JB		 5341 /* In general, don't allow 32-bit operands on pre-386. */
5342 else if (i.suffix == LONG_MNEM_SUFFIX
5343 && !cpu_arch_flags.bitfield.cpui386
5344 && (intel_syntax
5345 ? (!t->opcode_modifier.ignoresize
5346 && !intel_float_operand (t->name))
5347 : intel_float_operand (t->name) != 2)
5348 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5349 && !operand_types[0].bitfield.regsimd)
192dc9c6 5350 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5351 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5352 continue;
5353
29b0f896 5354 /* Do not verify operands when there are none. */
50aecf8c 5355 else
29b0f896 5356 {
c6fb90c8 5357 if (!t->operands)
2dbab7d5
L		 5358 /* We've found a match; break out of loop. */
5359 break;
29b0f896 5360 }
252b5132 5361
539e75ad
L		 5362 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5363 into Disp32/Disp16/Disp32 operand. */
5364 if (i.prefix[ADDR_PREFIX] != 0)
5365 {
40fb9820 5366 /* There should be only one Disp operand. */
539e75ad
L		 5367 switch (flag_code)
5368 {
5369 case CODE_16BIT:
40fb9820
L		 5370 for (j = 0; j < MAX_OPERANDS; j++)
5371 {
5372 if (operand_types[j].bitfield.disp16)
5373 {
5374 addr_prefix_disp = j;
5375 operand_types[j].bitfield.disp32 = 1;
5376 operand_types[j].bitfield.disp16 = 0;
5377 break;
5378 }
5379 }
539e75ad
L		 5380 break;
5381 case CODE_32BIT:
40fb9820
L		 5382 for (j = 0; j < MAX_OPERANDS; j++)
5383 {
5384 if (operand_types[j].bitfield.disp32)
5385 {
5386 addr_prefix_disp = j;
5387 operand_types[j].bitfield.disp32 = 0;
5388 operand_types[j].bitfield.disp16 = 1;
5389 break;
5390 }
5391 }
539e75ad
L		 5392 break;
5393 case CODE_64BIT:
40fb9820
L		 5394 for (j = 0; j < MAX_OPERANDS; j++)
5395 {
5396 if (operand_types[j].bitfield.disp64)
5397 {
5398 addr_prefix_disp = j;
5399 operand_types[j].bitfield.disp64 = 0;
5400 operand_types[j].bitfield.disp32 = 1;
5401 break;
5402 }
5403 }
539e75ad
L		 5404 break;
5405 }
539e75ad
L		 5406 }
5407
02a86693
L		 5408 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5409 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5410 continue;
5411
56ffb741
L		 5412 /* We check register size if needed. */
5413 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5414 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5415 switch (t->operands)
5416 {
5417 case 1:
40fb9820 5418 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5419 continue;
5420 break;
5421 case 2:
33eaf5de 5422 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5423 only in 32bit mode and we can use opcode 0x90. In 64bit
5424 mode, we can't use 0x90 for xchg %eax, %eax since it should
5425 zero-extend %eax to %rax. */
5426 if (flag_code == CODE_64BIT
5427 && t->base_opcode == 0x90
0dfbf9d7
L		 5428 && operand_type_equal (&i.types [0], &acc32)
5429 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5430 continue;
86fa6981
L		 5431 /* If we want store form, we reverse direction of operands. */
5432 if (i.dir_encoding == dir_encoding_store
5433 && t->opcode_modifier.d)
5434 goto check_reverse;
1a0670f3 5435 /* Fall through. */
b6169b20 5436
29b0f896 5437 case 3:
86fa6981
L		 5438 /* If we want store form, we skip the current load. */
5439 if (i.dir_encoding == dir_encoding_store
5440 && i.mem_operands == 0
5441 && t->opcode_modifier.load)
fa99fab2 5442 continue;
1a0670f3 5443 /* Fall through. */
f48ff2ae 5444 case 4:
c0f3af97 5445 case 5:
c6fb90c8 5446 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5447 if (!operand_type_match (overlap0, i.types[0])
5448 || !operand_type_match (overlap1, i.types[1])
45664ddb 5449 || (check_register
dc821c5f 5450 && !operand_type_register_match (i.types[0],
40fb9820 5451 operand_types[0],
dc821c5f 5452 i.types[1],
40fb9820 5453 operand_types[1])))
29b0f896
AM		 5454 {
5455 /* Check if other direction is valid ... */
38e314eb 5456 if (!t->opcode_modifier.d)
29b0f896
AM		 5457 continue;
5458
b6169b20 5459check_reverse:
29b0f896 5460 /* Try reversing direction of operands. */
c6fb90c8
L		 5461 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5462 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5463 if (!operand_type_match (overlap0, i.types[0])
5464 || !operand_type_match (overlap1, i.types[1])
45664ddb 5465 || (check_register
dc821c5f 5466 && !operand_type_register_match (i.types[0],
45664ddb 5467 operand_types[1],
45664ddb
L		 5468 i.types[1],
5469 operand_types[0])))
29b0f896
AM		 5470 {
5471 /* Does not match either direction. */
5472 continue;
5473 }
38e314eb 5474 /* found_reverse_match holds which of D or FloatR
29b0f896 5475 we've found. */
38e314eb
JB		 5476 if (!t->opcode_modifier.d)
5477 found_reverse_match = 0;
5478 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5479 found_reverse_match = Opcode_FloatD;
5480 else
38e314eb 5481 found_reverse_match = Opcode_D;
40fb9820 5482 if (t->opcode_modifier.floatr)
8a2ed489 5483 found_reverse_match |= Opcode_FloatR;
29b0f896 5484 }
f48ff2ae 5485 else
29b0f896 5486 {
f48ff2ae 5487 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5488 switch (t->operands)
5489 {
c0f3af97
L		 5490 case 5:
5491 overlap4 = operand_type_and (i.types[4],
5492 operand_types[4]);
1a0670f3 5493 /* Fall through. */
d1cbb4db 5494 case 4:
c6fb90c8
L		 5495 overlap3 = operand_type_and (i.types[3],
5496 operand_types[3]);
1a0670f3 5497 /* Fall through. */
d1cbb4db 5498 case 3:
c6fb90c8
L		 5499 overlap2 = operand_type_and (i.types[2],
5500 operand_types[2]);
d1cbb4db
L		 5501 break;
5502 }
29b0f896 5503
f48ff2ae
L		 5504 switch (t->operands)
5505 {
c0f3af97
L		 5506 case 5:
5507 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5508 || !operand_type_register_match (i.types[3],
c0f3af97 5509 operand_types[3],
c0f3af97
L		 5510 i.types[4],
5511 operand_types[4]))
5512 continue;
1a0670f3 5513 /* Fall through. */
f48ff2ae 5514 case 4:
40fb9820 5515 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5516 || (check_register
dc821c5f 5517 && !operand_type_register_match (i.types[2],
45664ddb 5518 operand_types[2],
45664ddb
L		 5519 i.types[3],
5520 operand_types[3])))
f48ff2ae 5521 continue;
1a0670f3 5522 /* Fall through. */
f48ff2ae
L		 5523 case 3:
5524 /* Here we make use of the fact that there are no
23e42951 5525 reverse match 3 operand instructions. */
40fb9820 5526 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5527 || (check_register
23e42951
JB		 5528 && (!operand_type_register_match (i.types[0],
5529 operand_types[0],
5530 i.types[2],
5531 operand_types[2])
5532 || !operand_type_register_match (i.types[1],
5533 operand_types[1],
5534 i.types[2],
5535 operand_types[2]))))
f48ff2ae
L		 5536 continue;
5537 break;
5538 }
29b0f896 5539 }
f48ff2ae 5540 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5541 slip through to break. */
5542 }
3629bb00 5543 if (!found_cpu_match)
29b0f896
AM		 5544 {
5545 found_reverse_match = 0;
5546 continue;
5547 }
c0f3af97 5548
5614d22c
JB		 5549 /* Check if vector and VEX operands are valid. */
5550 if (check_VecOperands (t) || VEX_check_operands (t))
5551 {
5552 specific_error = i.error;
5553 continue;
5554 }
a683cc34 5555
29b0f896
AM		 5556 /* We've found a match; break out of loop. */
5557 break;
5558 }
5559
5560 if (t == current_templates->end)
5561 {
5562 /* We found no match. */
a65babc9 5563 const char *err_msg;
5614d22c 5564 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5565 {
5566 default:
5567 abort ();
86e026a4 5568 case operand_size_mismatch:
a65babc9
L		 5569 err_msg = _("operand size mismatch");
5570 break;
5571 case operand_type_mismatch:
5572 err_msg = _("operand type mismatch");
5573 break;
5574 case register_type_mismatch:
5575 err_msg = _("register type mismatch");
5576 break;
5577 case number_of_operands_mismatch:
5578 err_msg = _("number of operands mismatch");
5579 break;
5580 case invalid_instruction_suffix:
5581 err_msg = _("invalid instruction suffix");
5582 break;
5583 case bad_imm4:
4a2608e3 5584 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5585 break;
5586 case old_gcc_only:
5587 err_msg = _("only supported with old gcc");
5588 break;
5589 case unsupported_with_intel_mnemonic:
5590 err_msg = _("unsupported with Intel mnemonic");
5591 break;
5592 case unsupported_syntax:
5593 err_msg = _("unsupported syntax");
5594 break;
5595 case unsupported:
35262a23 5596 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5597 current_templates->start->name);
5598 return NULL;
6c30d220
L		 5599 case invalid_vsib_address:
5600 err_msg = _("invalid VSIB address");
5601 break;
7bab8ab5
JB		 5602 case invalid_vector_register_set:
5603 err_msg = _("mask, index, and destination registers must be distinct");
5604 break;
6c30d220
L		 5605 case unsupported_vector_index_register:
5606 err_msg = _("unsupported vector index register");
5607 break;
43234a1e
L		 5608 case unsupported_broadcast:
5609 err_msg = _("unsupported broadcast");
5610 break;
5611 case broadcast_not_on_src_operand:
5612 err_msg = _("broadcast not on source memory operand");
5613 break;
5614 case broadcast_needed:
5615 err_msg = _("broadcast is needed for operand of such type");
5616 break;
5617 case unsupported_masking:
5618 err_msg = _("unsupported masking");
5619 break;
5620 case mask_not_on_destination:
5621 err_msg = _("mask not on destination operand");
5622 break;
5623 case no_default_mask:
5624 err_msg = _("default mask isn't allowed");
5625 break;
5626 case unsupported_rc_sae:
5627 err_msg = _("unsupported static rounding/sae");
5628 break;
5629 case rc_sae_operand_not_last_imm:
5630 if (intel_syntax)
5631 err_msg = _("RC/SAE operand must precede immediate operands");
5632 else
5633 err_msg = _("RC/SAE operand must follow immediate operands");
5634 break;
5635 case invalid_register_operand:
5636 err_msg = _("invalid register operand");
5637 break;
a65babc9
L		 5638 }
5639 as_bad (_("%s for `%s'"), err_msg,
891edac4 5640 current_templates->start->name);
fa99fab2 5641 return NULL;
29b0f896 5642 }
252b5132 5643
29b0f896
AM		 5644 if (!quiet_warnings)
5645 {
5646 if (!intel_syntax
40fb9820
L		 5647 && (i.types[0].bitfield.jumpabsolute
5648 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5649 {
5650 as_warn (_("indirect %s without `*'"), t->name);
5651 }
5652
40fb9820
L		 5653 if (t->opcode_modifier.isprefix
5654 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5655 {
5656 /* Warn them that a data or address size prefix doesn't
5657 affect assembly of the next line of code. */
5658 as_warn (_("stand-alone `%s' prefix"), t->name);
5659 }
5660 }
5661
5662 /* Copy the template we found. */
5663 i.tm = *t;
539e75ad
L		 5664
5665 if (addr_prefix_disp != -1)
5666 i.tm.operand_types[addr_prefix_disp]
5667 = operand_types[addr_prefix_disp];
5668
29b0f896
AM		 5669 if (found_reverse_match)
5670 {
5671 /* If we found a reverse match we must alter the opcode
5672 direction bit. found_reverse_match holds bits to change
5673 (different for int & float insns). */
5674
5675 i.tm.base_opcode ^= found_reverse_match;
5676
539e75ad
L		 5677 i.tm.operand_types[0] = operand_types[1];
5678 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5679 }
5680
fa99fab2 5681 return t;
29b0f896
AM		 5682}
5683
5684static int
e3bb37b5 5685check_string (void)
29b0f896 5686{
40fb9820
L		 5687 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5688 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5689 {
5690 if (i.seg[0] != NULL && i.seg[0] != &es)
5691 {
a87af027 5692 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5693 i.tm.name,
a87af027
JB		 5694 mem_op + 1,
5695 register_prefix);
29b0f896
AM		 5696 return 0;
5697 }
5698 /* There's only ever one segment override allowed per instruction.
5699 This instruction possibly has a legal segment override on the
5700 second operand, so copy the segment to where non-string
5701 instructions store it, allowing common code. */
5702 i.seg[0] = i.seg[1];
5703 }
40fb9820 5704 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5705 {
5706 if (i.seg[1] != NULL && i.seg[1] != &es)
5707 {
a87af027 5708 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5709 i.tm.name,
a87af027
JB		 5710 mem_op + 2,
5711 register_prefix);
29b0f896
AM		 5712 return 0;
5713 }
5714 }
5715 return 1;
5716}
5717
5718static int
543613e9 5719process_suffix (void)
29b0f896
AM		 5720{
5721 /* If matched instruction specifies an explicit instruction mnemonic
5722 suffix, use it. */
40fb9820
L		 5723 if (i.tm.opcode_modifier.size16)
5724 i.suffix = WORD_MNEM_SUFFIX;
5725 else if (i.tm.opcode_modifier.size32)
5726 i.suffix = LONG_MNEM_SUFFIX;
5727 else if (i.tm.opcode_modifier.size64)
5728 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5729 else if (i.reg_operands)
5730 {
5731 /* If there's no instruction mnemonic suffix we try to invent one
5732 based on register operands. */
5733 if (!i.suffix)
5734 {
5735 /* We take i.suffix from the last register operand specified,
5736 Destination register type is more significant than source
381d071f
L		 5737 register type. crc32 in SSE4.2 prefers source register
5738 type. */
5739 if (i.tm.base_opcode == 0xf20f38f1)
5740 {
dc821c5f 5741 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5742 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5743 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5744 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5745 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5746 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5747 }
9344ff29 5748 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5749 {
dc821c5f 5750 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5751 i.suffix = BYTE_MNEM_SUFFIX;
5752 }
381d071f
L		 5753
5754 if (!i.suffix)
5755 {
5756 int op;
5757
20592a94
L		 5758 if (i.tm.base_opcode == 0xf20f38f1
5759 || i.tm.base_opcode == 0xf20f38f0)
5760 {
5761 /* We have to know the operand size for crc32. */
5762 as_bad (_("ambiguous memory operand size for `%s`"),
5763 i.tm.name);
5764 return 0;
5765 }
5766
381d071f 5767 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5768 if (!i.tm.operand_types[op].bitfield.inoutportreg
5769 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5770 {
8819ada6
JB		 5771 if (!i.types[op].bitfield.reg)
5772 continue;
5773 if (i.types[op].bitfield.byte)
5774 i.suffix = BYTE_MNEM_SUFFIX;
5775 else if (i.types[op].bitfield.word)
5776 i.suffix = WORD_MNEM_SUFFIX;
5777 else if (i.types[op].bitfield.dword)
5778 i.suffix = LONG_MNEM_SUFFIX;
5779 else if (i.types[op].bitfield.qword)
5780 i.suffix = QWORD_MNEM_SUFFIX;
5781 else
5782 continue;
5783 break;
381d071f
L		 5784 }
5785 }
29b0f896
AM		 5786 }
5787 else if (i.suffix == BYTE_MNEM_SUFFIX)
5788 {
2eb952a4
L		 5789 if (intel_syntax
5790 && i.tm.opcode_modifier.ignoresize
5791 && i.tm.opcode_modifier.no_bsuf)
5792 i.suffix = 0;
5793 else if (!check_byte_reg ())
29b0f896
AM		 5794 return 0;
5795 }
5796 else if (i.suffix == LONG_MNEM_SUFFIX)
5797 {
2eb952a4
L		 5798 if (intel_syntax
5799 && i.tm.opcode_modifier.ignoresize
5800 && i.tm.opcode_modifier.no_lsuf)
5801 i.suffix = 0;
5802 else if (!check_long_reg ())
29b0f896
AM		 5803 return 0;
5804 }
5805 else if (i.suffix == QWORD_MNEM_SUFFIX)
5806 {
955e1e6a
L		 5807 if (intel_syntax
5808 && i.tm.opcode_modifier.ignoresize
5809 && i.tm.opcode_modifier.no_qsuf)
5810 i.suffix = 0;
5811 else if (!check_qword_reg ())
29b0f896
AM		 5812 return 0;
5813 }
5814 else if (i.suffix == WORD_MNEM_SUFFIX)
5815 {
2eb952a4
L		 5816 if (intel_syntax
5817 && i.tm.opcode_modifier.ignoresize
5818 && i.tm.opcode_modifier.no_wsuf)
5819 i.suffix = 0;
5820 else if (!check_word_reg ())
29b0f896
AM		 5821 return 0;
5822 }
40fb9820 5823 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5824 /* Do nothing if the instruction is going to ignore the prefix. */
5825 ;
5826 else
5827 abort ();
5828 }
40fb9820 5829 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5830 && !i.suffix
5831 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5832 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5833 {
5834 i.suffix = stackop_size;
5835 }
9306ca4a
JB		 5836 else if (intel_syntax
5837 && !i.suffix
40fb9820
L		 5838 && (i.tm.operand_types[0].bitfield.jumpabsolute
5839 || i.tm.opcode_modifier.jumpbyte
5840 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5841 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5842 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5843 {
5844 switch (flag_code)
5845 {
5846 case CODE_64BIT:
40fb9820 5847 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5848 {
5849 i.suffix = QWORD_MNEM_SUFFIX;
5850 break;
5851 }
1a0670f3 5852 /* Fall through. */
9306ca4a 5853 case CODE_32BIT:
40fb9820 5854 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5855 i.suffix = LONG_MNEM_SUFFIX;
5856 break;
5857 case CODE_16BIT:
40fb9820 5858 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5859 i.suffix = WORD_MNEM_SUFFIX;
5860 break;
5861 }
5862 }
252b5132 5863
9306ca4a 5864 if (!i.suffix)
29b0f896 5865 {
9306ca4a
JB		 5866 if (!intel_syntax)
5867 {
40fb9820 5868 if (i.tm.opcode_modifier.w)
9306ca4a 5869 {
4eed87de
AM		 5870 as_bad (_("no instruction mnemonic suffix given and "
5871 "no register operands; can't size instruction"));
9306ca4a
JB		 5872 return 0;
5873 }
5874 }
5875 else
5876 {
40fb9820 5877 unsigned int suffixes;
7ab9ffdd 5878
40fb9820
L		 5879 suffixes = !i.tm.opcode_modifier.no_bsuf;
5880 if (!i.tm.opcode_modifier.no_wsuf)
5881 suffixes |= 1 << 1;
5882 if (!i.tm.opcode_modifier.no_lsuf)
5883 suffixes |= 1 << 2;
fc4adea1 5884 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5885 suffixes |= 1 << 3;
5886 if (!i.tm.opcode_modifier.no_ssuf)
5887 suffixes |= 1 << 4;
c2b9da16 5888 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5889 suffixes |= 1 << 5;
5890
5891 /* There are more than suffix matches. */
5892 if (i.tm.opcode_modifier.w
9306ca4a 5893 || ((suffixes & (suffixes - 1))
40fb9820
L		 5894 && !i.tm.opcode_modifier.defaultsize
5895 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5896 {
5897 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5898 return 0;
5899 }
5900 }
29b0f896 5901 }
252b5132 5902
d2224064
JB		 5903 /* Change the opcode based on the operand size given by i.suffix. */
5904 switch (i.suffix)
29b0f896 5905 {
d2224064
JB		 5906 /* Size floating point instruction. */
5907 case LONG_MNEM_SUFFIX:
5908 if (i.tm.opcode_modifier.floatmf)
5909 {
5910 i.tm.base_opcode ^= 4;
5911 break;
5912 }
5913 /* fall through */
5914 case WORD_MNEM_SUFFIX:
5915 case QWORD_MNEM_SUFFIX:
29b0f896 5916 /* It's not a byte, select word/dword operation. */
40fb9820 5917 if (i.tm.opcode_modifier.w)
29b0f896 5918 {
40fb9820 5919 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5920 i.tm.base_opcode |= 8;
5921 else
5922 i.tm.base_opcode |= 1;
5923 }
d2224064
JB		 5924 /* fall through */
5925 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 5926 /* Now select between word & dword operations via the operand
5927 size prefix, except for instructions that will ignore this
5928 prefix anyway. */
ca61edf2 5929 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5930 {
ca61edf2
L		 5931 /* The address size override prefix changes the size of the
5932 first operand. */
40fb9820 5933 if ((flag_code == CODE_32BIT
dc821c5f 5934 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5935 || (flag_code != CODE_32BIT
dc821c5f 5936 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5937 if (!add_prefix (ADDR_PREFIX_OPCODE))
5938 return 0;
5939 }
5940 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 5941 && !i.tm.opcode_modifier.ignoresize
5942 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5943 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5944 || (flag_code == CODE_64BIT
40fb9820 5945 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5946 {
5947 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5948
40fb9820 5949 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5950 prefix = ADDR_PREFIX_OPCODE;
252b5132 5951
29b0f896
AM		 5952 if (!add_prefix (prefix))
5953 return 0;
24eab124 5954 }
252b5132 5955
29b0f896
AM		 5956 /* Set mode64 for an operand. */
5957 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5958 && flag_code == CODE_64BIT
d2224064 5959 && !i.tm.opcode_modifier.norex64
46e883c5 5960 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 5961 need rex64. */
5962 && ! (i.operands == 2
5963 && i.tm.base_opcode == 0x90
5964 && i.tm.extension_opcode == None
5965 && operand_type_equal (&i.types [0], &acc64)
5966 && operand_type_equal (&i.types [1], &acc64)))
5967 i.rex |= REX_W;
3e73aa7c 5968
d2224064 5969 break;
29b0f896 5970 }
7ecd2f8b 5971
29b0f896
AM		 5972 return 1;
5973}
3e73aa7c 5974
29b0f896 5975static int
543613e9 5976check_byte_reg (void)
29b0f896
AM		 5977{
5978 int op;
543613e9 5979
29b0f896
AM		 5980 for (op = i.operands; --op >= 0;)
5981 {
dc821c5f
JB		 5982 /* Skip non-register operands. */
5983 if (!i.types[op].bitfield.reg)
5984 continue;
5985
29b0f896
AM		 5986 /* If this is an eight bit register, it's OK. If it's the 16 or
5987 32 bit version of an eight bit register, we will just use the
5988 low portion, and that's OK too. */
dc821c5f 5989 if (i.types[op].bitfield.byte)
29b0f896
AM		 5990 continue;
5991
5a819eb9
JB		 5992 /* I/O port address operands are OK too. */
5993 if (i.tm.operand_types[op].bitfield.inoutportreg)
5994 continue;
5995
9344ff29
L		 5996 /* crc32 doesn't generate this warning. */
5997 if (i.tm.base_opcode == 0xf20f38f0)
5998 continue;
5999
dc821c5f
JB		 6000 if ((i.types[op].bitfield.word
6001 || i.types[op].bitfield.dword
6002 || i.types[op].bitfield.qword)
5a819eb9
JB		 6003 && i.op[op].regs->reg_num < 4
6004 /* Prohibit these changes in 64bit mode, since the lowering
6005 would be more complicated. */
6006 && flag_code != CODE_64BIT)
29b0f896 6007 {
29b0f896 6008#if REGISTER_WARNINGS
5a819eb9 6009 if (!quiet_warnings)
a540244d
L		 6010 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6011 register_prefix,
dc821c5f 6012 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6013 ? REGNAM_AL - REGNAM_AX
6014 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6015 register_prefix,
29b0f896
AM		 6016 i.op[op].regs->reg_name,
6017 i.suffix);
6018#endif
6019 continue;
6020 }
6021 /* Any other register is bad. */
dc821c5f 6022 if (i.types[op].bitfield.reg
40fb9820 6023 || i.types[op].bitfield.regmmx
1b54b8d7 6024 || i.types[op].bitfield.regsimd
40fb9820
L		 6025 || i.types[op].bitfield.sreg2
6026 || i.types[op].bitfield.sreg3
6027 || i.types[op].bitfield.control
6028 || i.types[op].bitfield.debug
ca0d63fe 6029 || i.types[op].bitfield.test)
29b0f896 6030 {
a540244d
L		 6031 as_bad (_("`%s%s' not allowed with `%s%c'"),
6032 register_prefix,
29b0f896
AM		 6033 i.op[op].regs->reg_name,
6034 i.tm.name,
6035 i.suffix);
6036 return 0;
6037 }
6038 }
6039 return 1;
6040}
6041
6042static int
e3bb37b5 6043check_long_reg (void)
29b0f896
AM		 6044{
6045 int op;
6046
6047 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6048 /* Skip non-register operands. */
6049 if (!i.types[op].bitfield.reg)
6050 continue;
29b0f896
AM		 6051 /* Reject eight bit registers, except where the template requires
6052 them. (eg. movzb) */
dc821c5f
JB		 6053 else if (i.types[op].bitfield.byte
6054 && (i.tm.operand_types[op].bitfield.reg
6055 || i.tm.operand_types[op].bitfield.acc)
6056 && (i.tm.operand_types[op].bitfield.word
6057 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6058 {
a540244d
L		 6059 as_bad (_("`%s%s' not allowed with `%s%c'"),
6060 register_prefix,
29b0f896
AM		 6061 i.op[op].regs->reg_name,
6062 i.tm.name,
6063 i.suffix);
6064 return 0;
6065 }
e4630f71 6066 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6067 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6068 && i.types[op].bitfield.word
6069 && (i.tm.operand_types[op].bitfield.reg
6070 || i.tm.operand_types[op].bitfield.acc)
6071 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6072 {
6073 /* Prohibit these changes in the 64bit mode, since the
6074 lowering is more complicated. */
6075 if (flag_code == CODE_64BIT)
252b5132 6076 {
2b5d6a91 6077 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6078 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6079 i.suffix);
6080 return 0;
252b5132 6081 }
29b0f896 6082#if REGISTER_WARNINGS
cecf1424
JB		 6083 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6084 register_prefix,
6085 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6086 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6087#endif
252b5132 6088 }
e4630f71 6089 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6090 else if (i.types[op].bitfield.qword
6091 && (i.tm.operand_types[op].bitfield.reg
6092 || i.tm.operand_types[op].bitfield.acc)
6093 && i.tm.operand_types[op].bitfield.dword)
252b5132 6094 {
34828aad 6095 if (intel_syntax
ca61edf2 6096 && i.tm.opcode_modifier.toqword
1b54b8d7 6097 && !i.types[0].bitfield.regsimd)
34828aad 6098 {
ca61edf2 6099 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6100 i.suffix = QWORD_MNEM_SUFFIX;
6101 }
6102 else
6103 {
2b5d6a91 6104 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6105 register_prefix, i.op[op].regs->reg_name,
6106 i.suffix);
6107 return 0;
6108 }
29b0f896
AM		 6109 }
6110 return 1;
6111}
252b5132 6112
29b0f896 6113static int
e3bb37b5 6114check_qword_reg (void)
29b0f896
AM		 6115{
6116 int op;
252b5132 6117
29b0f896 6118 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6119 /* Skip non-register operands. */
6120 if (!i.types[op].bitfield.reg)
6121 continue;
29b0f896
AM		 6122 /* Reject eight bit registers, except where the template requires
6123 them. (eg. movzb) */
dc821c5f
JB		 6124 else if (i.types[op].bitfield.byte
6125 && (i.tm.operand_types[op].bitfield.reg
6126 || i.tm.operand_types[op].bitfield.acc)
6127 && (i.tm.operand_types[op].bitfield.word
6128 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6129 {
a540244d
L		 6130 as_bad (_("`%s%s' not allowed with `%s%c'"),
6131 register_prefix,
29b0f896
AM		 6132 i.op[op].regs->reg_name,
6133 i.tm.name,
6134 i.suffix);
6135 return 0;
6136 }
e4630f71 6137 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6138 else if ((i.types[op].bitfield.word
6139 || i.types[op].bitfield.dword)
6140 && (i.tm.operand_types[op].bitfield.reg
6141 || i.tm.operand_types[op].bitfield.acc)
6142 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6143 {
6144 /* Prohibit these changes in the 64bit mode, since the
6145 lowering is more complicated. */
34828aad 6146 if (intel_syntax
ca61edf2 6147 && i.tm.opcode_modifier.todword
1b54b8d7 6148 && !i.types[0].bitfield.regsimd)
34828aad 6149 {
ca61edf2 6150 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6151 i.suffix = LONG_MNEM_SUFFIX;
6152 }
6153 else
6154 {
2b5d6a91 6155 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6156 register_prefix, i.op[op].regs->reg_name,
6157 i.suffix);
6158 return 0;
6159 }
252b5132 6160 }
29b0f896
AM		 6161 return 1;
6162}
252b5132 6163
29b0f896 6164static int
e3bb37b5 6165check_word_reg (void)
29b0f896
AM		 6166{
6167 int op;
6168 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6169 /* Skip non-register operands. */
6170 if (!i.types[op].bitfield.reg)
6171 continue;
29b0f896
AM		 6172 /* Reject eight bit registers, except where the template requires
6173 them. (eg. movzb) */
dc821c5f
JB		 6174 else if (i.types[op].bitfield.byte
6175 && (i.tm.operand_types[op].bitfield.reg
6176 || i.tm.operand_types[op].bitfield.acc)
6177 && (i.tm.operand_types[op].bitfield.word
6178 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6179 {
a540244d
L		 6180 as_bad (_("`%s%s' not allowed with `%s%c'"),
6181 register_prefix,
29b0f896
AM		 6182 i.op[op].regs->reg_name,
6183 i.tm.name,
6184 i.suffix);
6185 return 0;
6186 }
e4630f71 6187 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6188 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6189 && (i.types[op].bitfield.dword
6190 || i.types[op].bitfield.qword)
6191 && (i.tm.operand_types[op].bitfield.reg
6192 || i.tm.operand_types[op].bitfield.acc)
6193 && i.tm.operand_types[op].bitfield.word)
252b5132 6194 {
29b0f896
AM		 6195 /* Prohibit these changes in the 64bit mode, since the
6196 lowering is more complicated. */
6197 if (flag_code == CODE_64BIT)
252b5132 6198 {
2b5d6a91 6199 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6200 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6201 i.suffix);
6202 return 0;
252b5132 6203 }
29b0f896 6204#if REGISTER_WARNINGS
cecf1424
JB		 6205 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6206 register_prefix,
6207 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6208 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6209#endif
6210 }
6211 return 1;
6212}
252b5132 6213
29b0f896 6214static int
40fb9820 6215update_imm (unsigned int j)
29b0f896 6216{
bc0844ae 6217 i386_operand_type overlap = i.types[j];
40fb9820
L		 6218 if ((overlap.bitfield.imm8
6219 || overlap.bitfield.imm8s
6220 || overlap.bitfield.imm16
6221 || overlap.bitfield.imm32
6222 || overlap.bitfield.imm32s
6223 || overlap.bitfield.imm64)
0dfbf9d7
L		 6224 && !operand_type_equal (&overlap, &imm8)
6225 && !operand_type_equal (&overlap, &imm8s)
6226 && !operand_type_equal (&overlap, &imm16)
6227 && !operand_type_equal (&overlap, &imm32)
6228 && !operand_type_equal (&overlap, &imm32s)
6229 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6230 {
6231 if (i.suffix)
6232 {
40fb9820
L		 6233 i386_operand_type temp;
6234
0dfbf9d7 6235 operand_type_set (&temp, 0);
7ab9ffdd 6236 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6237 {
6238 temp.bitfield.imm8 = overlap.bitfield.imm8;
6239 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6240 }
6241 else if (i.suffix == WORD_MNEM_SUFFIX)
6242 temp.bitfield.imm16 = overlap.bitfield.imm16;
6243 else if (i.suffix == QWORD_MNEM_SUFFIX)
6244 {
6245 temp.bitfield.imm64 = overlap.bitfield.imm64;
6246 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6247 }
6248 else
6249 temp.bitfield.imm32 = overlap.bitfield.imm32;
6250 overlap = temp;
29b0f896 6251 }
0dfbf9d7
L		 6252 else if (operand_type_equal (&overlap, &imm16_32_32s)
6253 || operand_type_equal (&overlap, &imm16_32)
6254 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6255 {
40fb9820 6256 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6257 overlap = imm16;
40fb9820 6258 else
65da13b5 6259 overlap = imm32s;
29b0f896 6260 }
0dfbf9d7
L		 6261 if (!operand_type_equal (&overlap, &imm8)
6262 && !operand_type_equal (&overlap, &imm8s)
6263 && !operand_type_equal (&overlap, &imm16)
6264 && !operand_type_equal (&overlap, &imm32)
6265 && !operand_type_equal (&overlap, &imm32s)
6266 && !operand_type_equal (&overlap, &imm64))
29b0f896 6267 {
4eed87de
AM		 6268 as_bad (_("no instruction mnemonic suffix given; "
6269 "can't determine immediate size"));
29b0f896
AM		 6270 return 0;
6271 }
6272 }
40fb9820 6273 i.types[j] = overlap;
29b0f896 6274
40fb9820
L		 6275 return 1;
6276}
6277
6278static int
6279finalize_imm (void)
6280{
bc0844ae 6281 unsigned int j, n;
29b0f896 6282
bc0844ae
L		 6283 /* Update the first 2 immediate operands. */
6284 n = i.operands > 2 ? 2 : i.operands;
6285 if (n)
6286 {
6287 for (j = 0; j < n; j++)
6288 if (update_imm (j) == 0)
6289 return 0;
40fb9820 6290
bc0844ae
L		 6291 /* The 3rd operand can't be immediate operand. */
6292 gas_assert (operand_type_check (i.types[2], imm) == 0);
6293 }
29b0f896
AM		 6294
6295 return 1;
6296}
6297
6298static int
e3bb37b5 6299process_operands (void)
29b0f896
AM		 6300{
6301 /* Default segment register this instruction will use for memory
6302 accesses. 0 means unknown. This is only for optimizing out
6303 unnecessary segment overrides. */
6304 const seg_entry *default_seg = 0;
6305
2426c15f 6306 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6307 {
91d6fa6a
NC		 6308 unsigned int dupl = i.operands;
6309 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6310 unsigned int j;
6311
c0f3af97 6312 /* The destination must be an xmm register. */
9c2799c2 6313 gas_assert (i.reg_operands
91d6fa6a 6314 && MAX_OPERANDS > dupl
7ab9ffdd 6315 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6316
1b54b8d7
JB		 6317 if (i.tm.operand_types[0].bitfield.acc
6318 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6319 {
8cd7925b 6320 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6321 {
6322 /* Keep xmm0 for instructions with VEX prefix and 3
6323 sources. */
1b54b8d7
JB		 6324 i.tm.operand_types[0].bitfield.acc = 0;
6325 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6326 goto duplicate;
6327 }
e2ec9d29 6328 else
c0f3af97
L		 6329 {
6330 /* We remove the first xmm0 and keep the number of
6331 operands unchanged, which in fact duplicates the
6332 destination. */
6333 for (j = 1; j < i.operands; j++)
6334 {
6335 i.op[j - 1] = i.op[j];
6336 i.types[j - 1] = i.types[j];
6337 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6338 }
6339 }
6340 }
6341 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6342 {
91d6fa6a 6343 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6344 && (i.tm.opcode_modifier.vexsources
6345 == VEX3SOURCES));
c0f3af97
L		 6346
6347 /* Add the implicit xmm0 for instructions with VEX prefix
6348 and 3 sources. */
6349 for (j = i.operands; j > 0; j--)
6350 {
6351 i.op[j] = i.op[j - 1];
6352 i.types[j] = i.types[j - 1];
6353 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6354 }
6355 i.op[0].regs
6356 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6357 i.types[0] = regxmm;
c0f3af97
L		 6358 i.tm.operand_types[0] = regxmm;
6359
6360 i.operands += 2;
6361 i.reg_operands += 2;
6362 i.tm.operands += 2;
6363
91d6fa6a 6364 dupl++;
c0f3af97 6365 dest++;
91d6fa6a
NC		 6366 i.op[dupl] = i.op[dest];
6367 i.types[dupl] = i.types[dest];
6368 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6369 }
c0f3af97
L		 6370 else
6371 {
6372duplicate:
6373 i.operands++;
6374 i.reg_operands++;
6375 i.tm.operands++;
6376
91d6fa6a
NC		 6377 i.op[dupl] = i.op[dest];
6378 i.types[dupl] = i.types[dest];
6379 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6380 }
6381
6382 if (i.tm.opcode_modifier.immext)
6383 process_immext ();
6384 }
1b54b8d7
JB		 6385 else if (i.tm.operand_types[0].bitfield.acc
6386 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6387 {
6388 unsigned int j;
6389
9fcfb3d7
L		 6390 for (j = 1; j < i.operands; j++)
6391 {
6392 i.op[j - 1] = i.op[j];
6393 i.types[j - 1] = i.types[j];
6394
6395 /* We need to adjust fields in i.tm since they are used by
6396 build_modrm_byte. */
6397 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6398 }
6399
e2ec9d29
L		 6400 i.operands--;
6401 i.reg_operands--;
e2ec9d29
L		 6402 i.tm.operands--;
6403 }
920d2ddc
IT		 6404 else if (i.tm.opcode_modifier.implicitquadgroup)
6405 {
a477a8c4
JB		 6406 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6407
920d2ddc 6408 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6409 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6410 regnum = register_number (i.op[1].regs);
6411 first_reg_in_group = regnum & ~3;
6412 last_reg_in_group = first_reg_in_group + 3;
6413 if (regnum != first_reg_in_group)
6414 as_warn (_("source register `%s%s' implicitly denotes"
6415 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6416 register_prefix, i.op[1].regs->reg_name,
6417 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6418 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6419 i.tm.name);
6420 }
e2ec9d29
L		 6421 else if (i.tm.opcode_modifier.regkludge)
6422 {
6423 /* The imul $imm, %reg instruction is converted into
6424 imul $imm, %reg, %reg, and the clr %reg instruction
6425 is converted into xor %reg, %reg. */
6426
6427 unsigned int first_reg_op;
6428
6429 if (operand_type_check (i.types[0], reg))
6430 first_reg_op = 0;
6431 else
6432 first_reg_op = 1;
6433 /* Pretend we saw the extra register operand. */
9c2799c2 6434 gas_assert (i.reg_operands == 1
7ab9ffdd 6435 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6436 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6437 i.types[first_reg_op + 1] = i.types[first_reg_op];
6438 i.operands++;
6439 i.reg_operands++;
29b0f896
AM		 6440 }
6441
40fb9820 6442 if (i.tm.opcode_modifier.shortform)
29b0f896 6443 {
40fb9820
L		 6444 if (i.types[0].bitfield.sreg2
6445 || i.types[0].bitfield.sreg3)
29b0f896 6446 {
4eed87de
AM		 6447 if (i.tm.base_opcode == POP_SEG_SHORT
6448 && i.op[0].regs->reg_num == 1)
29b0f896 6449 {
a87af027 6450 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6451 return 0;
29b0f896 6452 }
4eed87de
AM		 6453 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6454 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6455 i.rex |= REX_B;
4eed87de
AM		 6456 }
6457 else
6458 {
7ab9ffdd 6459 /* The register or float register operand is in operand
85f10a01 6460 0 or 1. */
40fb9820 6461 unsigned int op;
7ab9ffdd 6462
ca0d63fe 6463 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6464 || operand_type_check (i.types[0], reg))
6465 op = 0;
6466 else
6467 op = 1;
4eed87de
AM		 6468 /* Register goes in low 3 bits of opcode. */
6469 i.tm.base_opcode |= i.op[op].regs->reg_num;
6470 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6471 i.rex |= REX_B;
40fb9820 6472 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6473 {
4eed87de
AM		 6474 /* Warn about some common errors, but press on regardless.
6475 The first case can be generated by gcc (<= 2.8.1). */
6476 if (i.operands == 2)
6477 {
6478 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6479 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6480 register_prefix, i.op[!intel_syntax].regs->reg_name,
6481 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6482 }
6483 else
6484 {
6485 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6486 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6487 register_prefix, i.op[0].regs->reg_name);
4eed87de 6488 }
29b0f896
AM		 6489 }
6490 }
6491 }
40fb9820 6492 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6493 {
6494 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6495 must be put into the modrm byte). Now, we make the modrm and
6496 index base bytes based on all the info we've collected. */
29b0f896
AM		 6497
6498 default_seg = build_modrm_byte ();
6499 }
8a2ed489 6500 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6501 {
6502 default_seg = &ds;
6503 }
40fb9820 6504 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6505 {
6506 /* For the string instructions that allow a segment override
6507 on one of their operands, the default segment is ds. */
6508 default_seg = &ds;
6509 }
6510
75178d9d
L		 6511 if (i.tm.base_opcode == 0x8d /* lea */
6512 && i.seg[0]
6513 && !quiet_warnings)
30123838 6514 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6515
6516 /* If a segment was explicitly specified, and the specified segment
6517 is not the default, use an opcode prefix to select it. If we
6518 never figured out what the default segment is, then default_seg
6519 will be zero at this point, and the specified segment prefix will
6520 always be used. */
29b0f896
AM		 6521 if ((i.seg[0]) && (i.seg[0] != default_seg))
6522 {
6523 if (!add_prefix (i.seg[0]->seg_prefix))
6524 return 0;
6525 }
6526 return 1;
6527}
6528
6529static const seg_entry *
e3bb37b5 6530build_modrm_byte (void)
29b0f896
AM		 6531{
6532 const seg_entry *default_seg = 0;
c0f3af97 6533 unsigned int source, dest;
8cd7925b 6534 int vex_3_sources;
c0f3af97
L		 6535
6536 /* The first operand of instructions with VEX prefix and 3 sources
6537 must be VEX_Imm4. */
8cd7925b 6538 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6539 if (vex_3_sources)
6540 {
91d6fa6a 6541 unsigned int nds, reg_slot;
4c2c6516 6542 expressionS *exp;
c0f3af97 6543
922d8de8 6544 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6545 && i.tm.opcode_modifier.immext)
6546 {
6547 dest = i.operands - 2;
6548 gas_assert (dest == 3);
6549 }
922d8de8 6550 else
a683cc34 6551 dest = i.operands - 1;
c0f3af97 6552 nds = dest - 1;
922d8de8 6553
a683cc34
SP		 6554 /* There are 2 kinds of instructions:
6555 1. 5 operands: 4 register operands or 3 register operands
6556 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6557 VexW0 or VexW1. The destination must be either XMM, YMM or
6558 ZMM register.
a683cc34
SP		 6559 2. 4 operands: 4 register operands or 3 register operands
6560 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6561 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6562 || (i.reg_operands == 3 && i.mem_operands == 1))
6563 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6564 && (i.tm.opcode_modifier.veximmext
6565 || (i.imm_operands == 1
6566 && i.types[0].bitfield.vec_imm4
6567 && (i.tm.opcode_modifier.vexw == VEXW0
6568 || i.tm.opcode_modifier.vexw == VEXW1)
10c17abd 6569 && i.tm.operand_types[dest].bitfield.regsimd)));
a683cc34
SP		 6570
6571 if (i.imm_operands == 0)
6572 {
6573 /* When there is no immediate operand, generate an 8bit
6574 immediate operand to encode the first operand. */
6575 exp = &im_expressions[i.imm_operands++];
6576 i.op[i.operands].imms = exp;
6577 i.types[i.operands] = imm8;
6578 i.operands++;
6579 /* If VexW1 is set, the first operand is the source and
6580 the second operand is encoded in the immediate operand. */
6581 if (i.tm.opcode_modifier.vexw == VEXW1)
6582 {
6583 source = 0;
6584 reg_slot = 1;
6585 }
6586 else
6587 {
6588 source = 1;
6589 reg_slot = 0;
6590 }
6591
6592 /* FMA swaps REG and NDS. */
6593 if (i.tm.cpu_flags.bitfield.cpufma)
6594 {
6595 unsigned int tmp;
6596 tmp = reg_slot;
6597 reg_slot = nds;
6598 nds = tmp;
6599 }
6600
10c17abd 6601 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6602 exp->X_op = O_constant;
4c692bc7 6603 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6604 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6605 }
922d8de8 6606 else
a683cc34
SP		 6607 {
6608 unsigned int imm_slot;
6609
6610 if (i.tm.opcode_modifier.vexw == VEXW0)
6611 {
6612 /* If VexW0 is set, the third operand is the source and
6613 the second operand is encoded in the immediate
6614 operand. */
6615 source = 2;
6616 reg_slot = 1;
6617 }
6618 else
6619 {
6620 /* VexW1 is set, the second operand is the source and
6621 the third operand is encoded in the immediate
6622 operand. */
6623 source = 1;
6624 reg_slot = 2;
6625 }
6626
6627 if (i.tm.opcode_modifier.immext)
6628 {
33eaf5de 6629 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6630 operand. */
6631 imm_slot = i.operands - 1;
6632 source--;
6633 reg_slot--;
6634 }
6635 else
6636 {
6637 imm_slot = 0;
6638
6639 /* Turn on Imm8 so that output_imm will generate it. */
6640 i.types[imm_slot].bitfield.imm8 = 1;
6641 }
6642
10c17abd 6643 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6644 i.op[imm_slot].imms->X_add_number
4c692bc7 6645 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6646 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6647 }
6648
10c17abd 6649 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6650 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6651 }
6652 else
6653 source = dest = 0;
29b0f896
AM		 6654
6655 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6656 implicit registers do not count. If there are 3 register
6657 operands, it must be a instruction with VexNDS. For a
6658 instruction with VexNDD, the destination register is encoded
6659 in VEX prefix. If there are 4 register operands, it must be
6660 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6661 if (i.mem_operands == 0
6662 && ((i.reg_operands == 2
2426c15f 6663 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6664 || (i.reg_operands == 3
2426c15f 6665 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6666 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6667 {
cab737b9
L		 6668 switch (i.operands)
6669 {
6670 case 2:
6671 source = 0;
6672 break;
6673 case 3:
c81128dc
L		 6674 /* When there are 3 operands, one of them may be immediate,
6675 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6676 the first operand must be shift count register (cl) or it
6677 is an instruction with VexNDS. */
9c2799c2 6678 gas_assert (i.imm_operands == 1
7ab9ffdd 6679 || (i.imm_operands == 0
2426c15f 6680 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6681 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6682 if (operand_type_check (i.types[0], imm)
6683 || i.types[0].bitfield.shiftcount)
6684 source = 1;
6685 else
6686 source = 0;
cab737b9
L		 6687 break;
6688 case 4:
368d64cc
L		 6689 /* When there are 4 operands, the first two must be 8bit
6690 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6691 one.
6692
6693 For instructions with VexNDS, if the first operand
6694 an imm8, the source operand is the 2nd one. If the last
6695 operand is imm8, the source operand is the first one. */
9c2799c2 6696 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6697 && i.types[0].bitfield.imm8
6698 && i.types[1].bitfield.imm8)
2426c15f 6699 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6700 && i.imm_operands == 1
6701 && (i.types[0].bitfield.imm8
43234a1e
L		 6702 || i.types[i.operands - 1].bitfield.imm8
6703 || i.rounding)));
9f2670f2
L		 6704 if (i.imm_operands == 2)
6705 source = 2;
6706 else
c0f3af97
L		 6707 {
6708 if (i.types[0].bitfield.imm8)
6709 source = 1;
6710 else
6711 source = 0;
6712 }
c0f3af97
L		 6713 break;
6714 case 5:
e771e7c9 6715 if (is_evex_encoding (&i.tm))
43234a1e
L		 6716 {
6717 /* For EVEX instructions, when there are 5 operands, the
6718 first one must be immediate operand. If the second one
6719 is immediate operand, the source operand is the 3th
6720 one. If the last one is immediate operand, the source
6721 operand is the 2nd one. */
6722 gas_assert (i.imm_operands == 2
6723 && i.tm.opcode_modifier.sae
6724 && operand_type_check (i.types[0], imm));
6725 if (operand_type_check (i.types[1], imm))
6726 source = 2;
6727 else if (operand_type_check (i.types[4], imm))
6728 source = 1;
6729 else
6730 abort ();
6731 }
cab737b9
L		 6732 break;
6733 default:
6734 abort ();
6735 }
6736
c0f3af97
L		 6737 if (!vex_3_sources)
6738 {
6739 dest = source + 1;
6740
43234a1e
L		 6741 /* RC/SAE operand could be between DEST and SRC. That happens
6742 when one operand is GPR and the other one is XMM/YMM/ZMM
6743 register. */
6744 if (i.rounding && i.rounding->operand == (int) dest)
6745 dest++;
6746
2426c15f 6747 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6748 {
43234a1e 6749 /* For instructions with VexNDS, the register-only source
c5d0745b 6750 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6751 register. It is encoded in VEX prefix. We need to
6752 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6753
6754 i386_operand_type op;
6755 unsigned int vvvv;
6756
6757 /* Check register-only source operand when two source
6758 operands are swapped. */
6759 if (!i.tm.operand_types[source].bitfield.baseindex
6760 && i.tm.operand_types[dest].bitfield.baseindex)
6761 {
6762 vvvv = source;
6763 source = dest;
6764 }
6765 else
6766 vvvv = dest;
6767
6768 op = i.tm.operand_types[vvvv];
fa99fab2 6769 op.bitfield.regmem = 0;
c0f3af97 6770 if ((dest + 1) >= i.operands
dc821c5f
JB		 6771 || ((!op.bitfield.reg
6772 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6773 && !op.bitfield.regsimd
43234a1e 6774 && !operand_type_equal (&op, &regmask)))
c0f3af97 6775 abort ();
f12dc422 6776 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6777 dest++;
6778 }
6779 }
29b0f896
AM		 6780
6781 i.rm.mode = 3;
6782 /* One of the register operands will be encoded in the i.tm.reg
6783 field, the other in the combined i.tm.mode and i.tm.regmem
6784 fields. If no form of this instruction supports a memory
6785 destination operand, then we assume the source operand may
6786 sometimes be a memory operand and so we need to store the
6787 destination in the i.rm.reg field. */
40fb9820
L		 6788 if (!i.tm.operand_types[dest].bitfield.regmem
6789 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6790 {
6791 i.rm.reg = i.op[dest].regs->reg_num;
6792 i.rm.regmem = i.op[source].regs->reg_num;
6793 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6794 i.rex |= REX_R;
43234a1e
L		 6795 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6796 i.vrex |= REX_R;
29b0f896 6797 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6798 i.rex |= REX_B;
43234a1e
L		 6799 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6800 i.vrex |= REX_B;
29b0f896
AM		 6801 }
6802 else
6803 {
6804 i.rm.reg = i.op[source].regs->reg_num;
6805 i.rm.regmem = i.op[dest].regs->reg_num;
6806 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6807 i.rex |= REX_B;
43234a1e
L		 6808 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6809 i.vrex |= REX_B;
29b0f896 6810 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6811 i.rex |= REX_R;
43234a1e
L		 6812 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6813 i.vrex |= REX_R;
29b0f896 6814 }
161a04f6 6815 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6816 {
40fb9820
L		 6817 if (!i.types[0].bitfield.control
6818 && !i.types[1].bitfield.control)
c4a530c5 6819 abort ();
161a04f6 6820 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6821 add_prefix (LOCK_PREFIX_OPCODE);
6822 }
29b0f896
AM		 6823 }
6824 else
6825 { /* If it's not 2 reg operands... */
c0f3af97
L		 6826 unsigned int mem;
6827
29b0f896
AM		 6828 if (i.mem_operands)
6829 {
6830 unsigned int fake_zero_displacement = 0;
99018f42 6831 unsigned int op;
4eed87de 6832
7ab9ffdd
L		 6833 for (op = 0; op < i.operands; op++)
6834 if (operand_type_check (i.types[op], anymem))
6835 break;
7ab9ffdd 6836 gas_assert (op < i.operands);
29b0f896 6837
6c30d220
L		 6838 if (i.tm.opcode_modifier.vecsib)
6839 {
6840 if (i.index_reg->reg_num == RegEiz
6841 || i.index_reg->reg_num == RegRiz)
6842 abort ();
6843
6844 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6845 if (!i.base_reg)
6846 {
6847 i.sib.base = NO_BASE_REGISTER;
6848 i.sib.scale = i.log2_scale_factor;
6849 i.types[op].bitfield.disp8 = 0;
6850 i.types[op].bitfield.disp16 = 0;
6851 i.types[op].bitfield.disp64 = 0;
43083a50 6852 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6853 {
6854 /* Must be 32 bit */
6855 i.types[op].bitfield.disp32 = 1;
6856 i.types[op].bitfield.disp32s = 0;
6857 }
6858 else
6859 {
6860 i.types[op].bitfield.disp32 = 0;
6861 i.types[op].bitfield.disp32s = 1;
6862 }
6863 }
6864 i.sib.index = i.index_reg->reg_num;
6865 if ((i.index_reg->reg_flags & RegRex) != 0)
6866 i.rex |= REX_X;
43234a1e
L		 6867 if ((i.index_reg->reg_flags & RegVRex) != 0)
6868 i.vrex |= REX_X;
6c30d220
L		 6869 }
6870
29b0f896
AM		 6871 default_seg = &ds;
6872
6873 if (i.base_reg == 0)
6874 {
6875 i.rm.mode = 0;
6876 if (!i.disp_operands)
9bb129e8 6877 fake_zero_displacement = 1;
29b0f896
AM		 6878 if (i.index_reg == 0)
6879 {
73053c1f
JB		 6880 i386_operand_type newdisp;
6881
6c30d220 6882 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6883 /* Operand is just <disp> */
20f0a1fc 6884 if (flag_code == CODE_64BIT)
29b0f896
AM		 6885 {
6886 /* 64bit mode overwrites the 32bit absolute
6887 addressing by RIP relative addressing and
6888 absolute addressing is encoded by one of the
6889 redundant SIB forms. */
6890 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6891 i.sib.base = NO_BASE_REGISTER;
6892 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6893 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6894 }
fc225355
L		 6895 else if ((flag_code == CODE_16BIT)
6896 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6897 {
6898 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6899 newdisp = disp16;
20f0a1fc
NC		 6900 }
6901 else
6902 {
6903 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6904 newdisp = disp32;
29b0f896 6905 }
73053c1f
JB		 6906 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6907 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6908 }
6c30d220 6909 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6910 {
6c30d220 6911 /* !i.base_reg && i.index_reg */
db51cc60
L		 6912 if (i.index_reg->reg_num == RegEiz
6913 || i.index_reg->reg_num == RegRiz)
6914 i.sib.index = NO_INDEX_REGISTER;
6915 else
6916 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6917 i.sib.base = NO_BASE_REGISTER;
6918 i.sib.scale = i.log2_scale_factor;
6919 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6920 i.types[op].bitfield.disp8 = 0;
6921 i.types[op].bitfield.disp16 = 0;
6922 i.types[op].bitfield.disp64 = 0;
43083a50 6923 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6924 {
6925 /* Must be 32 bit */
6926 i.types[op].bitfield.disp32 = 1;
6927 i.types[op].bitfield.disp32s = 0;
6928 }
29b0f896 6929 else
40fb9820
L		 6930 {
6931 i.types[op].bitfield.disp32 = 0;
6932 i.types[op].bitfield.disp32s = 1;
6933 }
29b0f896 6934 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6935 i.rex |= REX_X;
29b0f896
AM		 6936 }
6937 }
6938 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6939 else if (i.base_reg->reg_num == RegRip ||
6940 i.base_reg->reg_num == RegEip)
29b0f896 6941 {
6c30d220 6942 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6943 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6944 i.types[op].bitfield.disp8 = 0;
6945 i.types[op].bitfield.disp16 = 0;
6946 i.types[op].bitfield.disp32 = 0;
6947 i.types[op].bitfield.disp32s = 1;
6948 i.types[op].bitfield.disp64 = 0;
71903a11 6949 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6950 if (! i.disp_operands)
6951 fake_zero_displacement = 1;
29b0f896 6952 }
dc821c5f 6953 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6954 {
6c30d220 6955 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6956 switch (i.base_reg->reg_num)
6957 {
6958 case 3: /* (%bx) */
6959 if (i.index_reg == 0)
6960 i.rm.regmem = 7;
6961 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6962 i.rm.regmem = i.index_reg->reg_num - 6;
6963 break;
6964 case 5: /* (%bp) */
6965 default_seg = &ss;
6966 if (i.index_reg == 0)
6967 {
6968 i.rm.regmem = 6;
40fb9820 6969 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6970 {
6971 /* fake (%bp) into 0(%bp) */
b5014f7a 6972 i.types[op].bitfield.disp8 = 1;
252b5132 6973 fake_zero_displacement = 1;
29b0f896
AM		 6974 }
6975 }
6976 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6977 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6978 break;
6979 default: /* (%si) -> 4 or (%di) -> 5 */
6980 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6981 }
6982 i.rm.mode = mode_from_disp_size (i.types[op]);
6983 }
6984 else /* i.base_reg and 32/64 bit mode */
6985 {
6986 if (flag_code == CODE_64BIT
40fb9820
L		 6987 && operand_type_check (i.types[op], disp))
6988 {
73053c1f
JB		 6989 i.types[op].bitfield.disp16 = 0;
6990 i.types[op].bitfield.disp64 = 0;
40fb9820 6991 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 6992 {
6993 i.types[op].bitfield.disp32 = 0;
6994 i.types[op].bitfield.disp32s = 1;
6995 }
40fb9820 6996 else
73053c1f
JB		 6997 {
6998 i.types[op].bitfield.disp32 = 1;
6999 i.types[op].bitfield.disp32s = 0;
7000 }
40fb9820 7001 }
20f0a1fc 7002
6c30d220
L		 7003 if (!i.tm.opcode_modifier.vecsib)
7004 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7005 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7006 i.rex |= REX_B;
29b0f896
AM		 7007 i.sib.base = i.base_reg->reg_num;
7008 /* x86-64 ignores REX prefix bit here to avoid decoder
7009 complications. */
848930b2
JB		 7010 if (!(i.base_reg->reg_flags & RegRex)
7011 && (i.base_reg->reg_num == EBP_REG_NUM
7012 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7013 default_seg = &ss;
848930b2 7014 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7015 {
848930b2 7016 fake_zero_displacement = 1;
b5014f7a 7017 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7018 }
7019 i.sib.scale = i.log2_scale_factor;
7020 if (i.index_reg == 0)
7021 {
6c30d220 7022 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7023 /* <disp>(%esp) becomes two byte modrm with no index
7024 register. We've already stored the code for esp
7025 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7026 Any base register besides %esp will not use the
7027 extra modrm byte. */
7028 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7029 }
6c30d220 7030 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7031 {
db51cc60
L		 7032 if (i.index_reg->reg_num == RegEiz
7033 || i.index_reg->reg_num == RegRiz)
7034 i.sib.index = NO_INDEX_REGISTER;
7035 else
7036 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7037 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7038 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7039 i.rex |= REX_X;
29b0f896 7040 }
67a4f2b7
AO		 7041
7042 if (i.disp_operands
7043 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7044 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7045 i.rm.mode = 0;
7046 else
a501d77e
L		 7047 {
7048 if (!fake_zero_displacement
7049 && !i.disp_operands
7050 && i.disp_encoding)
7051 {
7052 fake_zero_displacement = 1;
7053 if (i.disp_encoding == disp_encoding_8bit)
7054 i.types[op].bitfield.disp8 = 1;
7055 else
7056 i.types[op].bitfield.disp32 = 1;
7057 }
7058 i.rm.mode = mode_from_disp_size (i.types[op]);
7059 }
29b0f896 7060 }
252b5132 7061
29b0f896
AM		 7062 if (fake_zero_displacement)
7063 {
7064 /* Fakes a zero displacement assuming that i.types[op]
7065 holds the correct displacement size. */
7066 expressionS *exp;
7067
9c2799c2 7068 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7069 exp = &disp_expressions[i.disp_operands++];
7070 i.op[op].disps = exp;
7071 exp->X_op = O_constant;
7072 exp->X_add_number = 0;
7073 exp->X_add_symbol = (symbolS *) 0;
7074 exp->X_op_symbol = (symbolS *) 0;
7075 }
c0f3af97
L		 7076
7077 mem = op;
29b0f896 7078 }
c0f3af97
L		 7079 else
7080 mem = ~0;
252b5132 7081
8c43a48b 7082 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7083 {
7084 if (operand_type_check (i.types[0], imm))
7085 i.vex.register_specifier = NULL;
7086 else
7087 {
7088 /* VEX.vvvv encodes one of the sources when the first
7089 operand is not an immediate. */
1ef99a7b 7090 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7091 i.vex.register_specifier = i.op[0].regs;
7092 else
7093 i.vex.register_specifier = i.op[1].regs;
7094 }
7095
7096 /* Destination is a XMM register encoded in the ModRM.reg
7097 and VEX.R bit. */
7098 i.rm.reg = i.op[2].regs->reg_num;
7099 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7100 i.rex |= REX_R;
7101
7102 /* ModRM.rm and VEX.B encodes the other source. */
7103 if (!i.mem_operands)
7104 {
7105 i.rm.mode = 3;
7106
1ef99a7b 7107 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7108 i.rm.regmem = i.op[1].regs->reg_num;
7109 else
7110 i.rm.regmem = i.op[0].regs->reg_num;
7111
7112 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7113 i.rex |= REX_B;
7114 }
7115 }
2426c15f 7116 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7117 {
7118 i.vex.register_specifier = i.op[2].regs;
7119 if (!i.mem_operands)
7120 {
7121 i.rm.mode = 3;
7122 i.rm.regmem = i.op[1].regs->reg_num;
7123 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7124 i.rex |= REX_B;
7125 }
7126 }
29b0f896
AM		 7127 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7128 (if any) based on i.tm.extension_opcode. Again, we must be
7129 careful to make sure that segment/control/debug/test/MMX
7130 registers are coded into the i.rm.reg field. */
f88c9eb0 7131 else if (i.reg_operands)
29b0f896 7132 {
99018f42 7133 unsigned int op;
7ab9ffdd
L		 7134 unsigned int vex_reg = ~0;
7135
7136 for (op = 0; op < i.operands; op++)
dc821c5f 7137 if (i.types[op].bitfield.reg
7ab9ffdd 7138 || i.types[op].bitfield.regmmx
1b54b8d7 7139 || i.types[op].bitfield.regsimd
7e8b059b 7140 || i.types[op].bitfield.regbnd
43234a1e 7141 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7142 || i.types[op].bitfield.sreg2
7143 || i.types[op].bitfield.sreg3
7144 || i.types[op].bitfield.control
7145 || i.types[op].bitfield.debug
7146 || i.types[op].bitfield.test)
7147 break;
c0209578 7148
7ab9ffdd
L		 7149 if (vex_3_sources)
7150 op = dest;
2426c15f 7151 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7152 {
7153 /* For instructions with VexNDS, the register-only
7154 source operand is encoded in VEX prefix. */
7155 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7156
7ab9ffdd 7157 if (op > mem)
c0f3af97 7158 {
7ab9ffdd
L		 7159 vex_reg = op++;
7160 gas_assert (op < i.operands);
c0f3af97
L		 7161 }
7162 else
c0f3af97 7163 {
f12dc422
L		 7164 /* Check register-only source operand when two source
7165 operands are swapped. */
7166 if (!i.tm.operand_types[op].bitfield.baseindex
7167 && i.tm.operand_types[op + 1].bitfield.baseindex)
7168 {
7169 vex_reg = op;
7170 op += 2;
7171 gas_assert (mem == (vex_reg + 1)
7172 && op < i.operands);
7173 }
7174 else
7175 {
7176 vex_reg = op + 1;
7177 gas_assert (vex_reg < i.operands);
7178 }
c0f3af97 7179 }
7ab9ffdd 7180 }
2426c15f 7181 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7182 {
f12dc422 7183 /* For instructions with VexNDD, the register destination
7ab9ffdd 7184 is encoded in VEX prefix. */
f12dc422
L		 7185 if (i.mem_operands == 0)
7186 {
7187 /* There is no memory operand. */
7188 gas_assert ((op + 2) == i.operands);
7189 vex_reg = op + 1;
7190 }
7191 else
8d63c93e 7192 {
ed438a93
JB		 7193 /* There are only 2 non-immediate operands. */
7194 gas_assert (op < i.imm_operands + 2
7195 && i.operands == i.imm_operands + 2);
7196 vex_reg = i.imm_operands + 1;
f12dc422 7197 }
7ab9ffdd
L		 7198 }
7199 else
7200 gas_assert (op < i.operands);
99018f42 7201
7ab9ffdd
L		 7202 if (vex_reg != (unsigned int) ~0)
7203 {
f12dc422 7204 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7205
dc821c5f
JB		 7206 if ((!type->bitfield.reg
7207 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7208 && !type->bitfield.regsimd
43234a1e 7209 && !operand_type_equal (type, &regmask))
7ab9ffdd 7210 abort ();
f88c9eb0 7211
7ab9ffdd
L		 7212 i.vex.register_specifier = i.op[vex_reg].regs;
7213 }
7214
1b9f0c97
L		 7215 /* Don't set OP operand twice. */
7216 if (vex_reg != op)
7ab9ffdd 7217 {
1b9f0c97
L		 7218 /* If there is an extension opcode to put here, the
7219 register number must be put into the regmem field. */
7220 if (i.tm.extension_opcode != None)
7221 {
7222 i.rm.regmem = i.op[op].regs->reg_num;
7223 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7224 i.rex |= REX_B;
43234a1e
L		 7225 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7226 i.vrex |= REX_B;
1b9f0c97
L		 7227 }
7228 else
7229 {
7230 i.rm.reg = i.op[op].regs->reg_num;
7231 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7232 i.rex |= REX_R;
43234a1e
L		 7233 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7234 i.vrex |= REX_R;
1b9f0c97 7235 }
7ab9ffdd 7236 }
252b5132 7237
29b0f896
AM		 7238 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7239 must set it to 3 to indicate this is a register operand
7240 in the regmem field. */
7241 if (!i.mem_operands)
7242 i.rm.mode = 3;
7243 }
252b5132 7244
29b0f896 7245 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7246 if (i.tm.extension_opcode != None)
29b0f896
AM		 7247 i.rm.reg = i.tm.extension_opcode;
7248 }
7249 return default_seg;
7250}
252b5132 7251
29b0f896 7252static void
e3bb37b5 7253output_branch (void)
29b0f896
AM		 7254{
7255 char *p;
f8a5c266 7256 int size;
29b0f896
AM		 7257 int code16;
7258 int prefix;
7259 relax_substateT subtype;
7260 symbolS *sym;
7261 offsetT off;
7262
f8a5c266 7263 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7264 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7265
7266 prefix = 0;
7267 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7268 {
29b0f896
AM		 7269 prefix = 1;
7270 i.prefixes -= 1;
7271 code16 ^= CODE16;
252b5132 7272 }
29b0f896
AM		 7273 /* Pentium4 branch hints. */
7274 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7275 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7276 {
29b0f896
AM		 7277 prefix++;
7278 i.prefixes--;
7279 }
7280 if (i.prefix[REX_PREFIX] != 0)
7281 {
7282 prefix++;
7283 i.prefixes--;
2f66722d
AM		 7284 }
7285
7e8b059b
L		 7286 /* BND prefixed jump. */
7287 if (i.prefix[BND_PREFIX] != 0)
7288 {
7289 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7290 i.prefixes -= 1;
7291 }
7292
29b0f896
AM		 7293 if (i.prefixes != 0 && !intel_syntax)
7294 as_warn (_("skipping prefixes on this instruction"));
7295
7296 /* It's always a symbol; End frag & setup for relax.
7297 Make sure there is enough room in this frag for the largest
7298 instruction we may generate in md_convert_frag. This is 2
7299 bytes for the opcode and room for the prefix and largest
7300 displacement. */
7301 frag_grow (prefix + 2 + 4);
7302 /* Prefix and 1 opcode byte go in fr_fix. */
7303 p = frag_more (prefix + 1);
7304 if (i.prefix[DATA_PREFIX] != 0)
7305 *p++ = DATA_PREFIX_OPCODE;
7306 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7307 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7308 *p++ = i.prefix[SEG_PREFIX];
7309 if (i.prefix[REX_PREFIX] != 0)
7310 *p++ = i.prefix[REX_PREFIX];
7311 *p = i.tm.base_opcode;
7312
7313 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7314 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7315 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7316 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7317 else
f8a5c266 7318 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7319 subtype |= code16;
3e73aa7c 7320
29b0f896
AM		 7321 sym = i.op[0].disps->X_add_symbol;
7322 off = i.op[0].disps->X_add_number;
3e73aa7c 7323
29b0f896
AM		 7324 if (i.op[0].disps->X_op != O_constant
7325 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7326 {
29b0f896
AM		 7327 /* Handle complex expressions. */
7328 sym = make_expr_symbol (i.op[0].disps);
7329 off = 0;
7330 }
3e73aa7c 7331
29b0f896
AM		 7332 /* 1 possible extra opcode + 4 byte displacement go in var part.
7333 Pass reloc in fr_var. */
d258b828 7334 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7335}
3e73aa7c 7336
bd7ab16b
L		 7337#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7338/* Return TRUE iff PLT32 relocation should be used for branching to
7339 symbol S. */
7340
7341static bfd_boolean
7342need_plt32_p (symbolS *s)
7343{
7344 /* PLT32 relocation is ELF only. */
7345 if (!IS_ELF)
7346 return FALSE;
7347
7348 /* Since there is no need to prepare for PLT branch on x86-64, we
7349 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7350 be used as a marker for 32-bit PC-relative branches. */
7351 if (!object_64bit)
7352 return FALSE;
7353
7354 /* Weak or undefined symbol need PLT32 relocation. */
7355 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7356 return TRUE;
7357
7358 /* Non-global symbol doesn't need PLT32 relocation. */
7359 if (! S_IS_EXTERNAL (s))
7360 return FALSE;
7361
7362 /* Other global symbols need PLT32 relocation. NB: Symbol with
7363 non-default visibilities are treated as normal global symbol
7364 so that PLT32 relocation can be used as a marker for 32-bit
7365 PC-relative branches. It is useful for linker relaxation. */
7366 return TRUE;
7367}
7368#endif
7369
29b0f896 7370static void
e3bb37b5 7371output_jump (void)
29b0f896
AM		 7372{
7373 char *p;
7374 int size;
3e02c1cc 7375 fixS *fixP;
bd7ab16b 7376 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7377
40fb9820 7378 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7379 {
7380 /* This is a loop or jecxz type instruction. */
7381 size = 1;
7382 if (i.prefix[ADDR_PREFIX] != 0)
7383 {
7384 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7385 i.prefixes -= 1;
7386 }
7387 /* Pentium4 branch hints. */
7388 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7389 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7390 {
7391 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7392 i.prefixes--;
3e73aa7c
JH		 7393 }
7394 }
29b0f896
AM		 7395 else
7396 {
7397 int code16;
3e73aa7c 7398
29b0f896
AM		 7399 code16 = 0;
7400 if (flag_code == CODE_16BIT)
7401 code16 = CODE16;
3e73aa7c 7402
29b0f896
AM		 7403 if (i.prefix[DATA_PREFIX] != 0)
7404 {
7405 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7406 i.prefixes -= 1;
7407 code16 ^= CODE16;
7408 }
252b5132 7409
29b0f896
AM		 7410 size = 4;
7411 if (code16)
7412 size = 2;
7413 }
9fcc94b6 7414
29b0f896
AM		 7415 if (i.prefix[REX_PREFIX] != 0)
7416 {
7417 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7418 i.prefixes -= 1;
7419 }
252b5132 7420
7e8b059b
L		 7421 /* BND prefixed jump. */
7422 if (i.prefix[BND_PREFIX] != 0)
7423 {
7424 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7425 i.prefixes -= 1;
7426 }
7427
29b0f896
AM		 7428 if (i.prefixes != 0 && !intel_syntax)
7429 as_warn (_("skipping prefixes on this instruction"));
e0890092 7430
42164a71
L		 7431 p = frag_more (i.tm.opcode_length + size);
7432 switch (i.tm.opcode_length)
7433 {
7434 case 2:
7435 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7436 /* Fall through. */
42164a71
L		 7437 case 1:
7438 *p++ = i.tm.base_opcode;
7439 break;
7440 default:
7441 abort ();
7442 }
e0890092 7443
bd7ab16b
L		 7444#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7445 if (size == 4
7446 && jump_reloc == NO_RELOC
7447 && need_plt32_p (i.op[0].disps->X_add_symbol))
7448 jump_reloc = BFD_RELOC_X86_64_PLT32;
7449#endif
7450
7451 jump_reloc = reloc (size, 1, 1, jump_reloc);
7452
3e02c1cc 7453 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7454 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7455
7456 /* All jumps handled here are signed, but don't use a signed limit
7457 check for 32 and 16 bit jumps as we want to allow wrap around at
7458 4G and 64k respectively. */
7459 if (size == 1)
7460 fixP->fx_signed = 1;
29b0f896 7461}
e0890092 7462
29b0f896 7463static void
e3bb37b5 7464output_interseg_jump (void)
29b0f896
AM		 7465{
7466 char *p;
7467 int size;
7468 int prefix;
7469 int code16;
252b5132 7470
29b0f896
AM		 7471 code16 = 0;
7472 if (flag_code == CODE_16BIT)
7473 code16 = CODE16;
a217f122 7474
29b0f896
AM		 7475 prefix = 0;
7476 if (i.prefix[DATA_PREFIX] != 0)
7477 {
7478 prefix = 1;
7479 i.prefixes -= 1;
7480 code16 ^= CODE16;
7481 }
7482 if (i.prefix[REX_PREFIX] != 0)
7483 {
7484 prefix++;
7485 i.prefixes -= 1;
7486 }
252b5132 7487
29b0f896
AM		 7488 size = 4;
7489 if (code16)
7490 size = 2;
252b5132 7491
29b0f896
AM		 7492 if (i.prefixes != 0 && !intel_syntax)
7493 as_warn (_("skipping prefixes on this instruction"));
252b5132 7494
29b0f896
AM		 7495 /* 1 opcode; 2 segment; offset */
7496 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7497
29b0f896
AM		 7498 if (i.prefix[DATA_PREFIX] != 0)
7499 *p++ = DATA_PREFIX_OPCODE;
252b5132 7500
29b0f896
AM		 7501 if (i.prefix[REX_PREFIX] != 0)
7502 *p++ = i.prefix[REX_PREFIX];
252b5132 7503
29b0f896
AM		 7504 *p++ = i.tm.base_opcode;
7505 if (i.op[1].imms->X_op == O_constant)
7506 {
7507 offsetT n = i.op[1].imms->X_add_number;
252b5132 7508
29b0f896
AM		 7509 if (size == 2
7510 && !fits_in_unsigned_word (n)
7511 && !fits_in_signed_word (n))
7512 {
7513 as_bad (_("16-bit jump out of range"));
7514 return;
7515 }
7516 md_number_to_chars (p, n, size);
7517 }
7518 else
7519 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7520 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7521 if (i.op[0].imms->X_op != O_constant)
7522 as_bad (_("can't handle non absolute segment in `%s'"),
7523 i.tm.name);
7524 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7525}
a217f122 7526
29b0f896 7527static void
e3bb37b5 7528output_insn (void)
29b0f896 7529{
2bbd9c25
JJ		 7530 fragS *insn_start_frag;
7531 offsetT insn_start_off;
7532
29b0f896
AM		 7533 /* Tie dwarf2 debug info to the address at the start of the insn.
7534 We can't do this after the insn has been output as the current
7535 frag may have been closed off. eg. by frag_var. */
7536 dwarf2_emit_insn (0);
7537
2bbd9c25
JJ		 7538 insn_start_frag = frag_now;
7539 insn_start_off = frag_now_fix ();
7540
29b0f896 7541 /* Output jumps. */
40fb9820 7542 if (i.tm.opcode_modifier.jump)
29b0f896 7543 output_branch ();
40fb9820
L		 7544 else if (i.tm.opcode_modifier.jumpbyte
7545 || i.tm.opcode_modifier.jumpdword)
29b0f896 7546 output_jump ();
40fb9820 7547 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7548 output_interseg_jump ();
7549 else
7550 {
7551 /* Output normal instructions here. */
7552 char *p;
7553 unsigned char *q;
47465058 7554 unsigned int j;
331d2d0d 7555 unsigned int prefix;
4dffcebc 7556
e4e00185
AS		 7557 if (avoid_fence
7558 && i.tm.base_opcode == 0xfae
7559 && i.operands == 1
7560 && i.imm_operands == 1
7561 && (i.op[0].imms->X_add_number == 0xe8
7562 || i.op[0].imms->X_add_number == 0xf0
7563 || i.op[0].imms->X_add_number == 0xf8))
7564 {
7565 /* Encode lfence, mfence, and sfence as
7566 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7567 offsetT val = 0x240483f0ULL;
7568 p = frag_more (5);
7569 md_number_to_chars (p, val, 5);
7570 return;
7571 }
7572
d022bddd
IT		 7573 /* Some processors fail on LOCK prefix. This options makes
7574 assembler ignore LOCK prefix and serves as a workaround. */
7575 if (omit_lock_prefix)
7576 {
7577 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7578 return;
7579 i.prefix[LOCK_PREFIX] = 0;
7580 }
7581
43234a1e
L		 7582 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7583 don't need the explicit prefix. */
7584 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7585 {
c0f3af97 7586 switch (i.tm.opcode_length)
bc4bd9ab 7587 {
c0f3af97
L		 7588 case 3:
7589 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7590 {
c0f3af97
L		 7591 prefix = (i.tm.base_opcode >> 24) & 0xff;
7592 goto check_prefix;
7593 }
7594 break;
7595 case 2:
7596 if ((i.tm.base_opcode & 0xff0000) != 0)
7597 {
7598 prefix = (i.tm.base_opcode >> 16) & 0xff;
7599 if (i.tm.cpu_flags.bitfield.cpupadlock)
7600 {
4dffcebc 7601check_prefix:
c0f3af97 7602 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7603 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7604 != REPE_PREFIX_OPCODE))
7605 add_prefix (prefix);
7606 }
7607 else
4dffcebc
L		 7608 add_prefix (prefix);
7609 }
c0f3af97
L		 7610 break;
7611 case 1:
7612 break;
390c91cf
L		 7613 case 0:
7614 /* Check for pseudo prefixes. */
7615 as_bad_where (insn_start_frag->fr_file,
7616 insn_start_frag->fr_line,
7617 _("pseudo prefix without instruction"));
7618 return;
c0f3af97
L		 7619 default:
7620 abort ();
bc4bd9ab 7621 }
c0f3af97 7622
6d19a37a 7623#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7624 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7625 R_X86_64_GOTTPOFF relocation so that linker can safely
7626 perform IE->LE optimization. */
7627 if (x86_elf_abi == X86_64_X32_ABI
7628 && i.operands == 2
7629 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7630 && i.prefix[REX_PREFIX] == 0)
7631 add_prefix (REX_OPCODE);
6d19a37a 7632#endif
cf61b747 7633
c0f3af97
L		 7634 /* The prefix bytes. */
7635 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7636 if (*q)
7637 FRAG_APPEND_1_CHAR (*q);
0f10071e 7638 }
ae5c1c7b 7639 else
c0f3af97
L		 7640 {
7641 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7642 if (*q)
7643 switch (j)
7644 {
7645 case REX_PREFIX:
7646 /* REX byte is encoded in VEX prefix. */
7647 break;
7648 case SEG_PREFIX:
7649 case ADDR_PREFIX:
7650 FRAG_APPEND_1_CHAR (*q);
7651 break;
7652 default:
7653 /* There should be no other prefixes for instructions
7654 with VEX prefix. */
7655 abort ();
7656 }
7657
43234a1e
L		 7658 /* For EVEX instructions i.vrex should become 0 after
7659 build_evex_prefix. For VEX instructions upper 16 registers
7660 aren't available, so VREX should be 0. */
7661 if (i.vrex)
7662 abort ();
c0f3af97
L		 7663 /* Now the VEX prefix. */
7664 p = frag_more (i.vex.length);
7665 for (j = 0; j < i.vex.length; j++)
7666 p[j] = i.vex.bytes[j];
7667 }
252b5132 7668
29b0f896 7669 /* Now the opcode; be careful about word order here! */
4dffcebc 7670 if (i.tm.opcode_length == 1)
29b0f896
AM		 7671 {
7672 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7673 }
7674 else
7675 {
4dffcebc 7676 switch (i.tm.opcode_length)
331d2d0d 7677 {
43234a1e
L		 7678 case 4:
7679 p = frag_more (4);
7680 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7681 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7682 break;
4dffcebc 7683 case 3:
331d2d0d
L		 7684 p = frag_more (3);
7685 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7686 break;
7687 case 2:
7688 p = frag_more (2);
7689 break;
7690 default:
7691 abort ();
7692 break;
331d2d0d 7693 }
0f10071e 7694
29b0f896
AM		 7695 /* Put out high byte first: can't use md_number_to_chars! */
7696 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7697 *p = i.tm.base_opcode & 0xff;
7698 }
3e73aa7c 7699
29b0f896 7700 /* Now the modrm byte and sib byte (if present). */
40fb9820 7701 if (i.tm.opcode_modifier.modrm)
29b0f896 7702 {
4a3523fa
L		 7703 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7704 | i.rm.reg << 3
7705 | i.rm.mode << 6));
29b0f896
AM		 7706 /* If i.rm.regmem == ESP (4)
7707 && i.rm.mode != (Register mode)
7708 && not 16 bit
7709 ==> need second modrm byte. */
7710 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7711 && i.rm.mode != 3
dc821c5f 7712 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7713 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7714 | i.sib.index << 3
7715 | i.sib.scale << 6));
29b0f896 7716 }
3e73aa7c 7717
29b0f896 7718 if (i.disp_operands)
2bbd9c25 7719 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7720
29b0f896 7721 if (i.imm_operands)
2bbd9c25 7722 output_imm (insn_start_frag, insn_start_off);
29b0f896 7723 }
252b5132 7724
29b0f896
AM		 7725#ifdef DEBUG386
7726 if (flag_debug)
7727 {
7b81dfbb 7728 pi ("" /*line*/, &i);
29b0f896
AM		 7729 }
7730#endif /* DEBUG386 */
7731}
252b5132 7732
e205caa7
L		 7733/* Return the size of the displacement operand N. */
7734
7735static int
7736disp_size (unsigned int n)
7737{
7738 int size = 4;
43234a1e 7739
b5014f7a 7740 if (i.types[n].bitfield.disp64)
40fb9820
L		 7741 size = 8;
7742 else if (i.types[n].bitfield.disp8)
7743 size = 1;
7744 else if (i.types[n].bitfield.disp16)
7745 size = 2;
e205caa7
L		 7746 return size;
7747}
7748
7749/* Return the size of the immediate operand N. */
7750
7751static int
7752imm_size (unsigned int n)
7753{
7754 int size = 4;
40fb9820
L		 7755 if (i.types[n].bitfield.imm64)
7756 size = 8;
7757 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7758 size = 1;
7759 else if (i.types[n].bitfield.imm16)
7760 size = 2;
e205caa7
L		 7761 return size;
7762}
7763
29b0f896 7764static void
64e74474 7765output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7766{
7767 char *p;
7768 unsigned int n;
252b5132 7769
29b0f896
AM		 7770 for (n = 0; n < i.operands; n++)
7771 {
b5014f7a 7772 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7773 {
7774 if (i.op[n].disps->X_op == O_constant)
7775 {
e205caa7 7776 int size = disp_size (n);
43234a1e 7777 offsetT val = i.op[n].disps->X_add_number;
252b5132 7778
b5014f7a 7779 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7780 p = frag_more (size);
7781 md_number_to_chars (p, val, size);
7782 }
7783 else
7784 {
f86103b7 7785 enum bfd_reloc_code_real reloc_type;
e205caa7 7786 int size = disp_size (n);
40fb9820 7787 int sign = i.types[n].bitfield.disp32s;
29b0f896 7788 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7789 fixS *fixP;
29b0f896 7790
e205caa7 7791 /* We can't have 8 bit displacement here. */
9c2799c2 7792 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7793
29b0f896
AM		 7794 /* The PC relative address is computed relative
7795 to the instruction boundary, so in case immediate
7796 fields follows, we need to adjust the value. */
7797 if (pcrel && i.imm_operands)
7798 {
29b0f896 7799 unsigned int n1;
e205caa7 7800 int sz = 0;
252b5132 7801
29b0f896 7802 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7803 if (operand_type_check (i.types[n1], imm))
252b5132 7804 {
e205caa7
L		 7805 /* Only one immediate is allowed for PC
7806 relative address. */
9c2799c2 7807 gas_assert (sz == 0);
e205caa7
L		 7808 sz = imm_size (n1);
7809 i.op[n].disps->X_add_number -= sz;
252b5132 7810 }
29b0f896 7811 /* We should find the immediate. */
9c2799c2 7812 gas_assert (sz != 0);
29b0f896 7813 }
520dc8e8 7814
29b0f896 7815 p = frag_more (size);
d258b828 7816 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7817 if (GOT_symbol
2bbd9c25 7818 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7819 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7820 || reloc_type == BFD_RELOC_X86_64_32S
7821 || (reloc_type == BFD_RELOC_64
7822 && object_64bit))
d6ab8113
JB		 7823 && (i.op[n].disps->X_op == O_symbol
7824 || (i.op[n].disps->X_op == O_add
7825 && ((symbol_get_value_expression
7826 (i.op[n].disps->X_op_symbol)->X_op)
7827 == O_subtract))))
7828 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7829 {
7830 offsetT add;
7831
7832 if (insn_start_frag == frag_now)
7833 add = (p - frag_now->fr_literal) - insn_start_off;
7834 else
7835 {
7836 fragS *fr;
7837
7838 add = insn_start_frag->fr_fix - insn_start_off;
7839 for (fr = insn_start_frag->fr_next;
7840 fr && fr != frag_now; fr = fr->fr_next)
7841 add += fr->fr_fix;
7842 add += p - frag_now->fr_literal;
7843 }
7844
4fa24527 7845 if (!object_64bit)
7b81dfbb
AJ		 7846 {
7847 reloc_type = BFD_RELOC_386_GOTPC;
7848 i.op[n].imms->X_add_number += add;
7849 }
7850 else if (reloc_type == BFD_RELOC_64)
7851 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7852 else
7b81dfbb
AJ		 7853 /* Don't do the adjustment for x86-64, as there
7854 the pcrel addressing is relative to the _next_
7855 insn, and that is taken care of in other code. */
d6ab8113 7856 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7857 }
02a86693
L		 7858 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7859 size, i.op[n].disps, pcrel,
7860 reloc_type);
7861 /* Check for "call/jmp *mem", "mov mem, %reg",
7862 "test %reg, mem" and "binop mem, %reg" where binop
7863 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7864 instructions. Always generate R_386_GOT32X for
7865 "sym*GOT" operand in 32-bit mode. */
7866 if ((generate_relax_relocations
7867 || (!object_64bit
7868 && i.rm.mode == 0
7869 && i.rm.regmem == 5))
7870 && (i.rm.mode == 2
7871 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7872 && ((i.operands == 1
7873 && i.tm.base_opcode == 0xff
7874 && (i.rm.reg == 2 || i.rm.reg == 4))
7875 || (i.operands == 2
7876 && (i.tm.base_opcode == 0x8b
7877 || i.tm.base_opcode == 0x85
7878 || (i.tm.base_opcode & 0xc7) == 0x03))))
7879 {
7880 if (object_64bit)
7881 {
7882 fixP->fx_tcbit = i.rex != 0;
7883 if (i.base_reg
7884 && (i.base_reg->reg_num == RegRip
7885 || i.base_reg->reg_num == RegEip))
7886 fixP->fx_tcbit2 = 1;
7887 }
7888 else
7889 fixP->fx_tcbit2 = 1;
7890 }
29b0f896
AM		 7891 }
7892 }
7893 }
7894}
252b5132 7895
29b0f896 7896static void
64e74474 7897output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7898{
7899 char *p;
7900 unsigned int n;
252b5132 7901
29b0f896
AM		 7902 for (n = 0; n < i.operands; n++)
7903 {
43234a1e
L		 7904 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7905 if (i.rounding && (int) n == i.rounding->operand)
7906 continue;
7907
40fb9820 7908 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7909 {
7910 if (i.op[n].imms->X_op == O_constant)
7911 {
e205caa7 7912 int size = imm_size (n);
29b0f896 7913 offsetT val;
b4cac588 7914
29b0f896
AM		 7915 val = offset_in_range (i.op[n].imms->X_add_number,
7916 size);
7917 p = frag_more (size);
7918 md_number_to_chars (p, val, size);
7919 }
7920 else
7921 {
7922 /* Not absolute_section.
7923 Need a 32-bit fixup (don't support 8bit
7924 non-absolute imms). Try to support other
7925 sizes ... */
f86103b7 7926 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7927 int size = imm_size (n);
7928 int sign;
29b0f896 7929
40fb9820 7930 if (i.types[n].bitfield.imm32s
a7d61044 7931 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7932 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7933 sign = 1;
e205caa7
L		 7934 else
7935 sign = 0;
520dc8e8 7936
29b0f896 7937 p = frag_more (size);
d258b828 7938 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7939
2bbd9c25
JJ		 7940 /* This is tough to explain. We end up with this one if we
7941 * have operands that look like
7942 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7943 * obtain the absolute address of the GOT, and it is strongly
7944 * preferable from a performance point of view to avoid using
7945 * a runtime relocation for this. The actual sequence of
7946 * instructions often look something like:
7947 *
7948 * call .L66
7949 * .L66:
7950 * popl %ebx
7951 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7952 *
7953 * The call and pop essentially return the absolute address
7954 * of the label .L66 and store it in %ebx. The linker itself
7955 * will ultimately change the first operand of the addl so
7956 * that %ebx points to the GOT, but to keep things simple, the
7957 * .o file must have this operand set so that it generates not
7958 * the absolute address of .L66, but the absolute address of
7959 * itself. This allows the linker itself simply treat a GOTPC
7960 * relocation as asking for a pcrel offset to the GOT to be
7961 * added in, and the addend of the relocation is stored in the
7962 * operand field for the instruction itself.
7963 *
7964 * Our job here is to fix the operand so that it would add
7965 * the correct offset so that %ebx would point to itself. The
7966 * thing that is tricky is that .-.L66 will point to the
7967 * beginning of the instruction, so we need to further modify
7968 * the operand so that it will point to itself. There are
7969 * other cases where you have something like:
7970 *
7971 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7972 *
7973 * and here no correction would be required. Internally in
7974 * the assembler we treat operands of this form as not being
7975 * pcrel since the '.' is explicitly mentioned, and I wonder
7976 * whether it would simplify matters to do it this way. Who
7977 * knows. In earlier versions of the PIC patches, the
7978 * pcrel_adjust field was used to store the correction, but
7979 * since the expression is not pcrel, I felt it would be
7980 * confusing to do it this way. */
7981
d6ab8113 7982 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7983 || reloc_type == BFD_RELOC_X86_64_32S
7984 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7985 && GOT_symbol
7986 && GOT_symbol == i.op[n].imms->X_add_symbol
7987 && (i.op[n].imms->X_op == O_symbol
7988 || (i.op[n].imms->X_op == O_add
7989 && ((symbol_get_value_expression
7990 (i.op[n].imms->X_op_symbol)->X_op)
7991 == O_subtract))))
7992 {
2bbd9c25
JJ		 7993 offsetT add;
7994
7995 if (insn_start_frag == frag_now)
7996 add = (p - frag_now->fr_literal) - insn_start_off;
7997 else
7998 {
7999 fragS *fr;
8000
8001 add = insn_start_frag->fr_fix - insn_start_off;
8002 for (fr = insn_start_frag->fr_next;
8003 fr && fr != frag_now; fr = fr->fr_next)
8004 add += fr->fr_fix;
8005 add += p - frag_now->fr_literal;
8006 }
8007
4fa24527 8008 if (!object_64bit)
d6ab8113 8009 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8010 else if (size == 4)
d6ab8113 8011 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8012 else if (size == 8)
8013 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8014 i.op[n].imms->X_add_number += add;
29b0f896 8015 }
29b0f896
AM		 8016 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8017 i.op[n].imms, 0, reloc_type);
8018 }
8019 }
8020 }
252b5132
RH		 8021}
8022\f
d182319b
JB		 8023/* x86_cons_fix_new is called via the expression parsing code when a
8024 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8025static int cons_sign = -1;
8026
8027void
e3bb37b5 8028x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8029 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8030{
d258b828 8031 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8032
8033#ifdef TE_PE
8034 if (exp->X_op == O_secrel)
8035 {
8036 exp->X_op = O_symbol;
8037 r = BFD_RELOC_32_SECREL;
8038 }
8039#endif
8040
8041 fix_new_exp (frag, off, len, exp, 0, r);
8042}
8043
357d1bd8
L		 8044/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8045 purpose of the `.dc.a' internal pseudo-op. */
8046
8047int
8048x86_address_bytes (void)
8049{
8050 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8051 return 4;
8052 return stdoutput->arch_info->bits_per_address / 8;
8053}
8054
d382c579
TG		 8055#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8056 || defined (LEX_AT)
d258b828 8057# define lex_got(reloc, adjust, types) NULL
718ddfc0 8058#else
f3c180ae
AM		 8059/* Parse operands of the form
8060 <symbol>@GOTOFF+<nnn>
8061 and similar .plt or .got references.
8062
8063 If we find one, set up the correct relocation in RELOC and copy the
8064 input string, minus the `@GOTOFF' into a malloc'd buffer for
8065 parsing by the calling routine. Return this buffer, and if ADJUST
8066 is non-null set it to the length of the string we removed from the
8067 input line. Otherwise return NULL. */
8068static char *
91d6fa6a 8069lex_got (enum bfd_reloc_code_real *rel,
64e74474 8070 int *adjust,
d258b828 8071 i386_operand_type *types)
f3c180ae 8072{
7b81dfbb
AJ		 8073 /* Some of the relocations depend on the size of what field is to
8074 be relocated. But in our callers i386_immediate and i386_displacement
8075 we don't yet know the operand size (this will be set by insn
8076 matching). Hence we record the word32 relocation here,
8077 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8078 static const struct {
8079 const char *str;
cff8d58a 8080 int len;
4fa24527 8081 const enum bfd_reloc_code_real rel[2];
40fb9820 8082 const i386_operand_type types64;
f3c180ae 8083 } gotrel[] = {
8ce3d284 8084#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8085 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8086 BFD_RELOC_SIZE32 },
8087 OPERAND_TYPE_IMM32_64 },
8ce3d284 8088#endif
cff8d58a
L		 8089 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8090 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8091 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8092 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8093 BFD_RELOC_X86_64_PLT32 },
40fb9820 8094 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8095 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8096 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8097 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8098 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8099 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8100 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8101 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8102 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8103 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8104 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8105 BFD_RELOC_X86_64_TLSGD },
40fb9820 8106 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8107 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8108 _dummy_first_bfd_reloc_code_real },
40fb9820 8109 OPERAND_TYPE_NONE },
cff8d58a
L		 8110 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8111 BFD_RELOC_X86_64_TLSLD },
40fb9820 8112 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8113 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8114 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8115 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8116 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8117 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8118 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8119 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8120 _dummy_first_bfd_reloc_code_real },
40fb9820 8121 OPERAND_TYPE_NONE },
cff8d58a
L		 8122 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8123 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8124 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8125 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8126 _dummy_first_bfd_reloc_code_real },
40fb9820 8127 OPERAND_TYPE_NONE },
cff8d58a
L		 8128 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8129 _dummy_first_bfd_reloc_code_real },
40fb9820 8130 OPERAND_TYPE_NONE },
cff8d58a
L		 8131 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8132 BFD_RELOC_X86_64_GOT32 },
40fb9820 8133 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8134 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8135 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8136 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8137 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8138 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8139 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8140 };
8141 char *cp;
8142 unsigned int j;
8143
d382c579 8144#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8145 if (!IS_ELF)
8146 return NULL;
d382c579 8147#endif
718ddfc0 8148
f3c180ae 8149 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8150 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8151 return NULL;
8152
47465058 8153 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8154 {
cff8d58a 8155 int len = gotrel[j].len;
28f81592 8156 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8157 {
4fa24527 8158 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8159 {
28f81592
AM		 8160 int first, second;
8161 char *tmpbuf, *past_reloc;
f3c180ae 8162
91d6fa6a 8163 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8164
3956db08
JB		 8165 if (types)
8166 {
8167 if (flag_code != CODE_64BIT)
40fb9820
L		 8168 {
8169 types->bitfield.imm32 = 1;
8170 types->bitfield.disp32 = 1;
8171 }
3956db08
JB		 8172 else
8173 *types = gotrel[j].types64;
8174 }
8175
8fd4256d 8176 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8177 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8178
28f81592 8179 /* The length of the first part of our input line. */
f3c180ae 8180 first = cp - input_line_pointer;
28f81592
AM		 8181
8182 /* The second part goes from after the reloc token until
67c11a9b 8183 (and including) an end_of_line char or comma. */
28f81592 8184 past_reloc = cp + 1 + len;
67c11a9b
AM		 8185 cp = past_reloc;
8186 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8187 ++cp;
8188 second = cp + 1 - past_reloc;
28f81592
AM		 8189
8190 /* Allocate and copy string. The trailing NUL shouldn't
8191 be necessary, but be safe. */
add39d23 8192 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8193 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8194 if (second != 0 && *past_reloc != ' ')
8195 /* Replace the relocation token with ' ', so that
8196 errors like foo@GOTOFF1 will be detected. */
8197 tmpbuf[first++] = ' ';
af89796a
L		 8198 else
8199 /* Increment length by 1 if the relocation token is
8200 removed. */
8201 len++;
8202 if (adjust)
8203 *adjust = len;
0787a12d
AM		 8204 memcpy (tmpbuf + first, past_reloc, second);
8205 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8206 return tmpbuf;
8207 }
8208
4fa24527
JB		 8209 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8210 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8211 return NULL;
8212 }
8213 }
8214
8215 /* Might be a symbol version string. Don't as_bad here. */
8216 return NULL;
8217}
4e4f7c87 8218#endif
f3c180ae 8219
a988325c
NC		 8220#ifdef TE_PE
8221#ifdef lex_got
8222#undef lex_got
8223#endif
8224/* Parse operands of the form
8225 <symbol>@SECREL32+<nnn>
8226
8227 If we find one, set up the correct relocation in RELOC and copy the
8228 input string, minus the `@SECREL32' into a malloc'd buffer for
8229 parsing by the calling routine. Return this buffer, and if ADJUST
8230 is non-null set it to the length of the string we removed from the
34bca508
L		 8231 input line. Otherwise return NULL.
8232
a988325c
NC		 8233 This function is copied from the ELF version above adjusted for PE targets. */
8234
8235static char *
8236lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8237 int *adjust ATTRIBUTE_UNUSED,
d258b828 8238 i386_operand_type *types)
a988325c
NC		 8239{
8240 static const struct
8241 {
8242 const char *str;
8243 int len;
8244 const enum bfd_reloc_code_real rel[2];
8245 const i386_operand_type types64;
8246 }
8247 gotrel[] =
8248 {
8249 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8250 BFD_RELOC_32_SECREL },
8251 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8252 };
8253
8254 char *cp;
8255 unsigned j;
8256
8257 for (cp = input_line_pointer; *cp != '@'; cp++)
8258 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8259 return NULL;
8260
8261 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8262 {
8263 int len = gotrel[j].len;
8264
8265 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8266 {
8267 if (gotrel[j].rel[object_64bit] != 0)
8268 {
8269 int first, second;
8270 char *tmpbuf, *past_reloc;
8271
8272 *rel = gotrel[j].rel[object_64bit];
8273 if (adjust)
8274 *adjust = len;
8275
8276 if (types)
8277 {
8278 if (flag_code != CODE_64BIT)
8279 {
8280 types->bitfield.imm32 = 1;
8281 types->bitfield.disp32 = 1;
8282 }
8283 else
8284 *types = gotrel[j].types64;
8285 }
8286
8287 /* The length of the first part of our input line. */
8288 first = cp - input_line_pointer;
8289
8290 /* The second part goes from after the reloc token until
8291 (and including) an end_of_line char or comma. */
8292 past_reloc = cp + 1 + len;
8293 cp = past_reloc;
8294 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8295 ++cp;
8296 second = cp + 1 - past_reloc;
8297
8298 /* Allocate and copy string. The trailing NUL shouldn't
8299 be necessary, but be safe. */
add39d23 8300 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8301 memcpy (tmpbuf, input_line_pointer, first);
8302 if (second != 0 && *past_reloc != ' ')
8303 /* Replace the relocation token with ' ', so that
8304 errors like foo@SECLREL321 will be detected. */
8305 tmpbuf[first++] = ' ';
8306 memcpy (tmpbuf + first, past_reloc, second);
8307 tmpbuf[first + second] = '\0';
8308 return tmpbuf;
8309 }
8310
8311 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8312 gotrel[j].str, 1 << (5 + object_64bit));
8313 return NULL;
8314 }
8315 }
8316
8317 /* Might be a symbol version string. Don't as_bad here. */
8318 return NULL;
8319}
8320
8321#endif /* TE_PE */
8322
62ebcb5c 8323bfd_reloc_code_real_type
e3bb37b5 8324x86_cons (expressionS *exp, int size)
f3c180ae 8325{
62ebcb5c
AM		 8326 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8327
ee86248c
JB		 8328 intel_syntax = -intel_syntax;
8329
3c7b9c2c 8330 exp->X_md = 0;
4fa24527 8331 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8332 {
8333 /* Handle @GOTOFF and the like in an expression. */
8334 char *save;
8335 char *gotfree_input_line;
4a57f2cf 8336 int adjust = 0;
f3c180ae
AM		 8337
8338 save = input_line_pointer;
d258b828 8339 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8340 if (gotfree_input_line)
8341 input_line_pointer = gotfree_input_line;
8342
8343 expression (exp);
8344
8345 if (gotfree_input_line)
8346 {
8347 /* expression () has merrily parsed up to the end of line,
8348 or a comma - in the wrong buffer. Transfer how far
8349 input_line_pointer has moved to the right buffer. */
8350 input_line_pointer = (save
8351 + (input_line_pointer - gotfree_input_line)
8352 + adjust);
8353 free (gotfree_input_line);
3992d3b7
AM		 8354 if (exp->X_op == O_constant
8355 || exp->X_op == O_absent
8356 || exp->X_op == O_illegal
0398aac5 8357 || exp->X_op == O_register
3992d3b7
AM		 8358 || exp->X_op == O_big)
8359 {
8360 char c = *input_line_pointer;
8361 *input_line_pointer = 0;
8362 as_bad (_("missing or invalid expression `%s'"), save);
8363 *input_line_pointer = c;
8364 }
f3c180ae
AM		 8365 }
8366 }
8367 else
8368 expression (exp);
ee86248c
JB		 8369
8370 intel_syntax = -intel_syntax;
8371
8372 if (intel_syntax)
8373 i386_intel_simplify (exp);
62ebcb5c
AM		 8374
8375 return got_reloc;
f3c180ae 8376}
f3c180ae 8377
9f32dd5b
L		 8378static void
8379signed_cons (int size)
6482c264 8380{
d182319b
JB		 8381 if (flag_code == CODE_64BIT)
8382 cons_sign = 1;
8383 cons (size);
8384 cons_sign = -1;
6482c264
NC		 8385}
8386
d182319b 8387#ifdef TE_PE
6482c264 8388static void
7016a5d5 8389pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8390{
8391 expressionS exp;
8392
8393 do
8394 {
8395 expression (&exp);
8396 if (exp.X_op == O_symbol)
8397 exp.X_op = O_secrel;
8398
8399 emit_expr (&exp, 4);
8400 }
8401 while (*input_line_pointer++ == ',');
8402
8403 input_line_pointer--;
8404 demand_empty_rest_of_line ();
8405}
6482c264
NC		 8406#endif
8407
43234a1e
L		 8408/* Handle Vector operations. */
8409
8410static char *
8411check_VecOperations (char *op_string, char *op_end)
8412{
8413 const reg_entry *mask;
8414 const char *saved;
8415 char *end_op;
8416
8417 while (*op_string
8418 && (op_end == NULL || op_string < op_end))
8419 {
8420 saved = op_string;
8421 if (*op_string == '{')
8422 {
8423 op_string++;
8424
8425 /* Check broadcasts. */
8426 if (strncmp (op_string, "1to", 3) == 0)
8427 {
8428 int bcst_type;
8429
8430 if (i.broadcast)
8431 goto duplicated_vec_op;
8432
8433 op_string += 3;
8434 if (*op_string == '8')
8435 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8436 else if (*op_string == '4')
8437 bcst_type = BROADCAST_1TO4;
8438 else if (*op_string == '2')
8439 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8440 else if (*op_string == '1'
8441 && *(op_string+1) == '6')
8442 {
8443 bcst_type = BROADCAST_1TO16;
8444 op_string++;
8445 }
8446 else
8447 {
8448 as_bad (_("Unsupported broadcast: `%s'"), saved);
8449 return NULL;
8450 }
8451 op_string++;
8452
8453 broadcast_op.type = bcst_type;
8454 broadcast_op.operand = this_operand;
8455 i.broadcast = &broadcast_op;
8456 }
8457 /* Check masking operation. */
8458 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8459 {
8460 /* k0 can't be used for write mask. */
6d2cd6b2 8461 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8462 {
6d2cd6b2
JB		 8463 as_bad (_("`%s%s' can't be used for write mask"),
8464 register_prefix, mask->reg_name);
43234a1e
L		 8465 return NULL;
8466 }
8467
8468 if (!i.mask)
8469 {
8470 mask_op.mask = mask;
8471 mask_op.zeroing = 0;
8472 mask_op.operand = this_operand;
8473 i.mask = &mask_op;
8474 }
8475 else
8476 {
8477 if (i.mask->mask)
8478 goto duplicated_vec_op;
8479
8480 i.mask->mask = mask;
8481
8482 /* Only "{z}" is allowed here. No need to check
8483 zeroing mask explicitly. */
8484 if (i.mask->operand != this_operand)
8485 {
8486 as_bad (_("invalid write mask `%s'"), saved);
8487 return NULL;
8488 }
8489 }
8490
8491 op_string = end_op;
8492 }
8493 /* Check zeroing-flag for masking operation. */
8494 else if (*op_string == 'z')
8495 {
8496 if (!i.mask)
8497 {
8498 mask_op.mask = NULL;
8499 mask_op.zeroing = 1;
8500 mask_op.operand = this_operand;
8501 i.mask = &mask_op;
8502 }
8503 else
8504 {
8505 if (i.mask->zeroing)
8506 {
8507 duplicated_vec_op:
8508 as_bad (_("duplicated `%s'"), saved);
8509 return NULL;
8510 }
8511
8512 i.mask->zeroing = 1;
8513
8514 /* Only "{%k}" is allowed here. No need to check mask
8515 register explicitly. */
8516 if (i.mask->operand != this_operand)
8517 {
8518 as_bad (_("invalid zeroing-masking `%s'"),
8519 saved);
8520 return NULL;
8521 }
8522 }
8523
8524 op_string++;
8525 }
8526 else
8527 goto unknown_vec_op;
8528
8529 if (*op_string != '}')
8530 {
8531 as_bad (_("missing `}' in `%s'"), saved);
8532 return NULL;
8533 }
8534 op_string++;
8535 continue;
8536 }
8537 unknown_vec_op:
8538 /* We don't know this one. */
8539 as_bad (_("unknown vector operation: `%s'"), saved);
8540 return NULL;
8541 }
8542
6d2cd6b2
JB		 8543 if (i.mask && i.mask->zeroing && !i.mask->mask)
8544 {
8545 as_bad (_("zeroing-masking only allowed with write mask"));
8546 return NULL;
8547 }
8548
43234a1e
L		 8549 return op_string;
8550}
8551
252b5132 8552static int
70e41ade 8553i386_immediate (char *imm_start)
252b5132
RH		 8554{
8555 char *save_input_line_pointer;
f3c180ae 8556 char *gotfree_input_line;
252b5132 8557 segT exp_seg = 0;
47926f60 8558 expressionS *exp;
40fb9820
L		 8559 i386_operand_type types;
8560
0dfbf9d7 8561 operand_type_set (&types, ~0);
252b5132
RH		 8562
8563 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8564 {
31b2323c
L		 8565 as_bad (_("at most %d immediate operands are allowed"),
8566 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8567 return 0;
8568 }
8569
8570 exp = &im_expressions[i.imm_operands++];
520dc8e8 8571 i.op[this_operand].imms = exp;
252b5132
RH		 8572
8573 if (is_space_char (*imm_start))
8574 ++imm_start;
8575
8576 save_input_line_pointer = input_line_pointer;
8577 input_line_pointer = imm_start;
8578
d258b828 8579 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8580 if (gotfree_input_line)
8581 input_line_pointer = gotfree_input_line;
252b5132
RH		 8582
8583 exp_seg = expression (exp);
8584
83183c0c 8585 SKIP_WHITESPACE ();
43234a1e
L		 8586
8587 /* Handle vector operations. */
8588 if (*input_line_pointer == '{')
8589 {
8590 input_line_pointer = check_VecOperations (input_line_pointer,
8591 NULL);
8592 if (input_line_pointer == NULL)
8593 return 0;
8594 }
8595
252b5132 8596 if (*input_line_pointer)
f3c180ae 8597 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8598
8599 input_line_pointer = save_input_line_pointer;
f3c180ae 8600 if (gotfree_input_line)
ee86248c
JB		 8601 {
8602 free (gotfree_input_line);
8603
8604 if (exp->X_op == O_constant || exp->X_op == O_register)
8605 exp->X_op = O_illegal;
8606 }
8607
8608 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8609}
252b5132 8610
ee86248c
JB		 8611static int
8612i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8613 i386_operand_type types, const char *imm_start)
8614{
8615 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8616 {
313c53d1
L		 8617 if (imm_start)
8618 as_bad (_("missing or invalid immediate expression `%s'"),
8619 imm_start);
3992d3b7 8620 return 0;
252b5132 8621 }
3e73aa7c 8622 else if (exp->X_op == O_constant)
252b5132 8623 {
47926f60 8624 /* Size it properly later. */
40fb9820 8625 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8626 /* If not 64bit, sign extend val. */
8627 if (flag_code != CODE_64BIT
4eed87de
AM		 8628 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8629 exp->X_add_number
8630 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8631 }
4c63da97 8632#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8633 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8634 && exp_seg != absolute_section
47926f60 8635 && exp_seg != text_section
24eab124
AM		 8636 && exp_seg != data_section
8637 && exp_seg != bss_section
8638 && exp_seg != undefined_section
f86103b7 8639 && !bfd_is_com_section (exp_seg))
252b5132 8640 {
d0b47220 8641 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8642 return 0;
8643 }
8644#endif
a841bdf5 8645 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8646 {
313c53d1
L		 8647 if (imm_start)
8648 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8649 return 0;
8650 }
252b5132
RH		 8651 else
8652 {
8653 /* This is an address. The size of the address will be
24eab124 8654 determined later, depending on destination register,
3e73aa7c 8655 suffix, or the default for the section. */
40fb9820
L		 8656 i.types[this_operand].bitfield.imm8 = 1;
8657 i.types[this_operand].bitfield.imm16 = 1;
8658 i.types[this_operand].bitfield.imm32 = 1;
8659 i.types[this_operand].bitfield.imm32s = 1;
8660 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8661 i.types[this_operand] = operand_type_and (i.types[this_operand],
8662 types);
252b5132
RH		 8663 }
8664
8665 return 1;
8666}
8667
551c1ca1 8668static char *
e3bb37b5 8669i386_scale (char *scale)
252b5132 8670{
551c1ca1
AM		 8671 offsetT val;
8672 char *save = input_line_pointer;
252b5132 8673
551c1ca1
AM		 8674 input_line_pointer = scale;
8675 val = get_absolute_expression ();
8676
8677 switch (val)
252b5132 8678 {
551c1ca1 8679 case 1:
252b5132
RH		 8680 i.log2_scale_factor = 0;
8681 break;
551c1ca1 8682 case 2:
252b5132
RH		 8683 i.log2_scale_factor = 1;
8684 break;
551c1ca1 8685 case 4:
252b5132
RH		 8686 i.log2_scale_factor = 2;
8687 break;
551c1ca1 8688 case 8:
252b5132
RH		 8689 i.log2_scale_factor = 3;
8690 break;
8691 default:
a724f0f4
JB		 8692 {
8693 char sep = *input_line_pointer;
8694
8695 *input_line_pointer = '\0';
8696 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8697 scale);
8698 *input_line_pointer = sep;
8699 input_line_pointer = save;
8700 return NULL;
8701 }
252b5132 8702 }
29b0f896 8703 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8704 {
8705 as_warn (_("scale factor of %d without an index register"),
24eab124 8706 1 << i.log2_scale_factor);
252b5132 8707 i.log2_scale_factor = 0;
252b5132 8708 }
551c1ca1
AM		 8709 scale = input_line_pointer;
8710 input_line_pointer = save;
8711 return scale;
252b5132
RH		 8712}
8713
252b5132 8714static int
e3bb37b5 8715i386_displacement (char *disp_start, char *disp_end)
252b5132 8716{
29b0f896 8717 expressionS *exp;
252b5132
RH		 8718 segT exp_seg = 0;
8719 char *save_input_line_pointer;
f3c180ae 8720 char *gotfree_input_line;
40fb9820
L		 8721 int override;
8722 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8723 int ret;
252b5132 8724
31b2323c
L		 8725 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8726 {
8727 as_bad (_("at most %d displacement operands are allowed"),
8728 MAX_MEMORY_OPERANDS);
8729 return 0;
8730 }
8731
0dfbf9d7 8732 operand_type_set (&bigdisp, 0);
40fb9820
L		 8733 if ((i.types[this_operand].bitfield.jumpabsolute)
8734 || (!current_templates->start->opcode_modifier.jump
8735 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8736 {
40fb9820 8737 bigdisp.bitfield.disp32 = 1;
e05278af 8738 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8739 if (flag_code == CODE_64BIT)
8740 {
8741 if (!override)
8742 {
8743 bigdisp.bitfield.disp32s = 1;
8744 bigdisp.bitfield.disp64 = 1;
8745 }
8746 }
8747 else if ((flag_code == CODE_16BIT) ^ override)
8748 {
8749 bigdisp.bitfield.disp32 = 0;
8750 bigdisp.bitfield.disp16 = 1;
8751 }
e05278af
JB		 8752 }
8753 else
8754 {
8755 /* For PC-relative branches, the width of the displacement
8756 is dependent upon data size, not address size. */
e05278af 8757 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8758 if (flag_code == CODE_64BIT)
8759 {
8760 if (override || i.suffix == WORD_MNEM_SUFFIX)
8761 bigdisp.bitfield.disp16 = 1;
8762 else
8763 {
8764 bigdisp.bitfield.disp32 = 1;
8765 bigdisp.bitfield.disp32s = 1;
8766 }
8767 }
8768 else
e05278af
JB		 8769 {
8770 if (!override)
8771 override = (i.suffix == (flag_code != CODE_16BIT
8772 ? WORD_MNEM_SUFFIX
8773 : LONG_MNEM_SUFFIX));
40fb9820
L		 8774 bigdisp.bitfield.disp32 = 1;
8775 if ((flag_code == CODE_16BIT) ^ override)
8776 {
8777 bigdisp.bitfield.disp32 = 0;
8778 bigdisp.bitfield.disp16 = 1;
8779 }
e05278af 8780 }
e05278af 8781 }
c6fb90c8
L		 8782 i.types[this_operand] = operand_type_or (i.types[this_operand],
8783 bigdisp);
252b5132
RH		 8784
8785 exp = &disp_expressions[i.disp_operands];
520dc8e8 8786 i.op[this_operand].disps = exp;
252b5132
RH		 8787 i.disp_operands++;
8788 save_input_line_pointer = input_line_pointer;
8789 input_line_pointer = disp_start;
8790 END_STRING_AND_SAVE (disp_end);
8791
8792#ifndef GCC_ASM_O_HACK
8793#define GCC_ASM_O_HACK 0
8794#endif
8795#if GCC_ASM_O_HACK
8796 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8797 if (i.types[this_operand].bitfield.baseIndex
24eab124 8798 && displacement_string_end[-1] == '+')
252b5132
RH		 8799 {
8800 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8801 constraint within gcc asm statements.
8802 For instance:
8803
8804 #define _set_tssldt_desc(n,addr,limit,type) \
8805 __asm__ __volatile__ ( \
8806 "movw %w2,%0\n\t" \
8807 "movw %w1,2+%0\n\t" \
8808 "rorl $16,%1\n\t" \
8809 "movb %b1,4+%0\n\t" \
8810 "movb %4,5+%0\n\t" \
8811 "movb $0,6+%0\n\t" \
8812 "movb %h1,7+%0\n\t" \
8813 "rorl $16,%1" \
8814 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8815
8816 This works great except that the output assembler ends
8817 up looking a bit weird if it turns out that there is
8818 no offset. You end up producing code that looks like:
8819
8820 #APP
8821 movw $235,(%eax)
8822 movw %dx,2+(%eax)
8823 rorl $16,%edx
8824 movb %dl,4+(%eax)
8825 movb $137,5+(%eax)
8826 movb $0,6+(%eax)
8827 movb %dh,7+(%eax)
8828 rorl $16,%edx
8829 #NO_APP
8830
47926f60 8831 So here we provide the missing zero. */
24eab124
AM		 8832
8833 *displacement_string_end = '0';
252b5132
RH		 8834 }
8835#endif
d258b828 8836 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8837 if (gotfree_input_line)
8838 input_line_pointer = gotfree_input_line;
252b5132 8839
24eab124 8840 exp_seg = expression (exp);
252b5132 8841
636c26b0
AM		 8842 SKIP_WHITESPACE ();
8843 if (*input_line_pointer)
8844 as_bad (_("junk `%s' after expression"), input_line_pointer);
8845#if GCC_ASM_O_HACK
8846 RESTORE_END_STRING (disp_end + 1);
8847#endif
636c26b0 8848 input_line_pointer = save_input_line_pointer;
636c26b0 8849 if (gotfree_input_line)
ee86248c
JB		 8850 {
8851 free (gotfree_input_line);
8852
8853 if (exp->X_op == O_constant || exp->X_op == O_register)
8854 exp->X_op = O_illegal;
8855 }
8856
8857 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8858
8859 RESTORE_END_STRING (disp_end);
8860
8861 return ret;
8862}
8863
8864static int
8865i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8866 i386_operand_type types, const char *disp_start)
8867{
8868 i386_operand_type bigdisp;
8869 int ret = 1;
636c26b0 8870
24eab124
AM		 8871 /* We do this to make sure that the section symbol is in
8872 the symbol table. We will ultimately change the relocation
47926f60 8873 to be relative to the beginning of the section. */
1ae12ab7 8874 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8875 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8876 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8877 {
636c26b0 8878 if (exp->X_op != O_symbol)
3992d3b7 8879 goto inv_disp;
636c26b0 8880
e5cb08ac 8881 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8882 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8883 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8884 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8885 exp->X_op = O_subtract;
8886 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8887 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8888 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8889 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8890 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8891 else
29b0f896 8892 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8893 }
252b5132 8894
3992d3b7
AM		 8895 else if (exp->X_op == O_absent
8896 || exp->X_op == O_illegal
ee86248c 8897 || exp->X_op == O_big)
2daf4fd8 8898 {
3992d3b7
AM		 8899 inv_disp:
8900 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8901 disp_start);
3992d3b7 8902 ret = 0;
2daf4fd8
AM		 8903 }
8904
0e1147d9
L		 8905 else if (flag_code == CODE_64BIT
8906 && !i.prefix[ADDR_PREFIX]
8907 && exp->X_op == O_constant)
8908 {
8909 /* Since displacement is signed extended to 64bit, don't allow
8910 disp32 and turn off disp32s if they are out of range. */
8911 i.types[this_operand].bitfield.disp32 = 0;
8912 if (!fits_in_signed_long (exp->X_add_number))
8913 {
8914 i.types[this_operand].bitfield.disp32s = 0;
8915 if (i.types[this_operand].bitfield.baseindex)
8916 {
8917 as_bad (_("0x%lx out range of signed 32bit displacement"),
8918 (long) exp->X_add_number);
8919 ret = 0;
8920 }
8921 }
8922 }
8923
4c63da97 8924#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8925 else if (exp->X_op != O_constant
8926 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8927 && exp_seg != absolute_section
8928 && exp_seg != text_section
8929 && exp_seg != data_section
8930 && exp_seg != bss_section
8931 && exp_seg != undefined_section
8932 && !bfd_is_com_section (exp_seg))
24eab124 8933 {
d0b47220 8934 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8935 ret = 0;
24eab124 8936 }
252b5132 8937#endif
3956db08 8938
40fb9820
L		 8939 /* Check if this is a displacement only operand. */
8940 bigdisp = i.types[this_operand];
8941 bigdisp.bitfield.disp8 = 0;
8942 bigdisp.bitfield.disp16 = 0;
8943 bigdisp.bitfield.disp32 = 0;
8944 bigdisp.bitfield.disp32s = 0;
8945 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8946 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8947 i.types[this_operand] = operand_type_and (i.types[this_operand],
8948 types);
3956db08 8949
3992d3b7 8950 return ret;
252b5132
RH		 8951}
8952
2abc2bec
JB		 8953/* Return the active addressing mode, taking address override and
8954 registers forming the address into consideration. Update the
8955 address override prefix if necessary. */
47926f60 8956
2abc2bec
JB		 8957static enum flag_code
8958i386_addressing_mode (void)
252b5132 8959{
be05d201
L		 8960 enum flag_code addr_mode;
8961
8962 if (i.prefix[ADDR_PREFIX])
8963 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8964 else
8965 {
8966 addr_mode = flag_code;
8967
24eab124 8968#if INFER_ADDR_PREFIX
be05d201
L		 8969 if (i.mem_operands == 0)
8970 {
8971 /* Infer address prefix from the first memory operand. */
8972 const reg_entry *addr_reg = i.base_reg;
8973
8974 if (addr_reg == NULL)
8975 addr_reg = i.index_reg;
eecb386c 8976
be05d201
L		 8977 if (addr_reg)
8978 {
8979 if (addr_reg->reg_num == RegEip
8980 || addr_reg->reg_num == RegEiz
dc821c5f 8981 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 8982 addr_mode = CODE_32BIT;
8983 else if (flag_code != CODE_64BIT
dc821c5f 8984 && addr_reg->reg_type.bitfield.word)
be05d201
L		 8985 addr_mode = CODE_16BIT;
8986
8987 if (addr_mode != flag_code)
8988 {
8989 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8990 i.prefixes += 1;
8991 /* Change the size of any displacement too. At most one
8992 of Disp16 or Disp32 is set.
8993 FIXME. There doesn't seem to be any real need for
8994 separate Disp16 and Disp32 flags. The same goes for
8995 Imm16 and Imm32. Removing them would probably clean
8996 up the code quite a lot. */
8997 if (flag_code != CODE_64BIT
8998 && (i.types[this_operand].bitfield.disp16
8999 || i.types[this_operand].bitfield.disp32))
9000 i.types[this_operand]
9001 = operand_type_xor (i.types[this_operand], disp16_32);
9002 }
9003 }
9004 }
24eab124 9005#endif
be05d201
L		 9006 }
9007
2abc2bec
JB		 9008 return addr_mode;
9009}
9010
9011/* Make sure the memory operand we've been dealt is valid.
9012 Return 1 on success, 0 on a failure. */
9013
9014static int
9015i386_index_check (const char *operand_string)
9016{
9017 const char *kind = "base/index";
9018 enum flag_code addr_mode = i386_addressing_mode ();
9019
fc0763e6
JB		 9020 if (current_templates->start->opcode_modifier.isstring
9021 && !current_templates->start->opcode_modifier.immext
9022 && (current_templates->end[-1].opcode_modifier.isstring
9023 || i.mem_operands))
9024 {
9025 /* Memory operands of string insns are special in that they only allow
9026 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9027 const reg_entry *expected_reg;
9028 static const char *di_si[][2] =
9029 {
9030 { "esi", "edi" },
9031 { "si", "di" },
9032 { "rsi", "rdi" }
9033 };
9034 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9035
9036 kind = "string address";
9037
8325cc63 9038 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9039 {
9040 i386_operand_type type = current_templates->end[-1].operand_types[0];
9041
9042 if (!type.bitfield.baseindex
9043 || ((!i.mem_operands != !intel_syntax)
9044 && current_templates->end[-1].operand_types[1]
9045 .bitfield.baseindex))
9046 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9047 expected_reg = hash_find (reg_hash,
9048 di_si[addr_mode][type.bitfield.esseg]);
9049
fc0763e6
JB		 9050 }
9051 else
be05d201 9052 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9053
be05d201
L		 9054 if (i.base_reg != expected_reg
9055 || i.index_reg
fc0763e6 9056 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9057 {
be05d201
L		 9058 /* The second memory operand must have the same size as
9059 the first one. */
9060 if (i.mem_operands
9061 && i.base_reg
9062 && !((addr_mode == CODE_64BIT
dc821c5f 9063 && i.base_reg->reg_type.bitfield.qword)
be05d201 9064 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9065 ? i.base_reg->reg_type.bitfield.dword
9066 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9067 goto bad_address;
9068
fc0763e6
JB		 9069 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9070 operand_string,
9071 intel_syntax ? '[' : '(',
9072 register_prefix,
be05d201 9073 expected_reg->reg_name,
fc0763e6 9074 intel_syntax ? ']' : ')');
be05d201 9075 return 1;
fc0763e6 9076 }
be05d201
L		 9077 else
9078 return 1;
9079
9080bad_address:
9081 as_bad (_("`%s' is not a valid %s expression"),
9082 operand_string, kind);
9083 return 0;
3e73aa7c
JH		 9084 }
9085 else
9086 {
be05d201
L		 9087 if (addr_mode != CODE_16BIT)
9088 {
9089 /* 32-bit/64-bit checks. */
9090 if ((i.base_reg
9091 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9092 ? !i.base_reg->reg_type.bitfield.qword
9093 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9094 && (i.index_reg
9095 || (i.base_reg->reg_num
9096 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9097 || (i.index_reg
1b54b8d7
JB		 9098 && !i.index_reg->reg_type.bitfield.xmmword
9099 && !i.index_reg->reg_type.bitfield.ymmword
9100 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9101 && ((addr_mode == CODE_64BIT
dc821c5f 9102 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9103 || i.index_reg->reg_num == RegRiz)
dc821c5f 9104 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9105 || i.index_reg->reg_num == RegEiz))
9106 || !i.index_reg->reg_type.bitfield.baseindex)))
9107 goto bad_address;
8178be5b
JB		 9108
9109 /* bndmk, bndldx, and bndstx have special restrictions. */
9110 if (current_templates->start->base_opcode == 0xf30f1b
9111 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9112 {
9113 /* They cannot use RIP-relative addressing. */
9114 if (i.base_reg && i.base_reg->reg_num == RegRip)
9115 {
9116 as_bad (_("`%s' cannot be used here"), operand_string);
9117 return 0;
9118 }
9119
9120 /* bndldx and bndstx ignore their scale factor. */
9121 if (current_templates->start->base_opcode != 0xf30f1b
9122 && i.log2_scale_factor)
9123 as_warn (_("register scaling is being ignored here"));
9124 }
be05d201
L		 9125 }
9126 else
3e73aa7c 9127 {
be05d201 9128 /* 16-bit checks. */
3e73aa7c 9129 if ((i.base_reg
dc821c5f 9130 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9131 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9132 || (i.index_reg
dc821c5f 9133 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9134 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9135 || !(i.base_reg
9136 && i.base_reg->reg_num < 6
9137 && i.index_reg->reg_num >= 6
9138 && i.log2_scale_factor == 0))))
be05d201 9139 goto bad_address;
3e73aa7c
JH		 9140 }
9141 }
be05d201 9142 return 1;
24eab124 9143}
252b5132 9144
43234a1e
L		 9145/* Handle vector immediates. */
9146
9147static int
9148RC_SAE_immediate (const char *imm_start)
9149{
9150 unsigned int match_found, j;
9151 const char *pstr = imm_start;
9152 expressionS *exp;
9153
9154 if (*pstr != '{')
9155 return 0;
9156
9157 pstr++;
9158 match_found = 0;
9159 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9160 {
9161 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9162 {
9163 if (!i.rounding)
9164 {
9165 rc_op.type = RC_NamesTable[j].type;
9166 rc_op.operand = this_operand;
9167 i.rounding = &rc_op;
9168 }
9169 else
9170 {
9171 as_bad (_("duplicated `%s'"), imm_start);
9172 return 0;
9173 }
9174 pstr += RC_NamesTable[j].len;
9175 match_found = 1;
9176 break;
9177 }
9178 }
9179 if (!match_found)
9180 return 0;
9181
9182 if (*pstr++ != '}')
9183 {
9184 as_bad (_("Missing '}': '%s'"), imm_start);
9185 return 0;
9186 }
9187 /* RC/SAE immediate string should contain nothing more. */;
9188 if (*pstr != 0)
9189 {
9190 as_bad (_("Junk after '}': '%s'"), imm_start);
9191 return 0;
9192 }
9193
9194 exp = &im_expressions[i.imm_operands++];
9195 i.op[this_operand].imms = exp;
9196
9197 exp->X_op = O_constant;
9198 exp->X_add_number = 0;
9199 exp->X_add_symbol = (symbolS *) 0;
9200 exp->X_op_symbol = (symbolS *) 0;
9201
9202 i.types[this_operand].bitfield.imm8 = 1;
9203 return 1;
9204}
9205
8325cc63
JB		 9206/* Only string instructions can have a second memory operand, so
9207 reduce current_templates to just those if it contains any. */
9208static int
9209maybe_adjust_templates (void)
9210{
9211 const insn_template *t;
9212
9213 gas_assert (i.mem_operands == 1);
9214
9215 for (t = current_templates->start; t < current_templates->end; ++t)
9216 if (t->opcode_modifier.isstring)
9217 break;
9218
9219 if (t < current_templates->end)
9220 {
9221 static templates aux_templates;
9222 bfd_boolean recheck;
9223
9224 aux_templates.start = t;
9225 for (; t < current_templates->end; ++t)
9226 if (!t->opcode_modifier.isstring)
9227 break;
9228 aux_templates.end = t;
9229
9230 /* Determine whether to re-check the first memory operand. */
9231 recheck = (aux_templates.start != current_templates->start
9232 || t != current_templates->end);
9233
9234 current_templates = &aux_templates;
9235
9236 if (recheck)
9237 {
9238 i.mem_operands = 0;
9239 if (i.memop1_string != NULL
9240 && i386_index_check (i.memop1_string) == 0)
9241 return 0;
9242 i.mem_operands = 1;
9243 }
9244 }
9245
9246 return 1;
9247}
9248
fc0763e6 9249/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9250 on error. */
252b5132 9251
252b5132 9252static int
a7619375 9253i386_att_operand (char *operand_string)
252b5132 9254{
af6bdddf
AM		 9255 const reg_entry *r;
9256 char *end_op;
24eab124 9257 char *op_string = operand_string;
252b5132 9258
24eab124 9259 if (is_space_char (*op_string))
252b5132
RH		 9260 ++op_string;
9261
24eab124 9262 /* We check for an absolute prefix (differentiating,
47926f60 9263 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9264 if (*op_string == ABSOLUTE_PREFIX)
9265 {
9266 ++op_string;
9267 if (is_space_char (*op_string))
9268 ++op_string;
40fb9820 9269 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9270 }
252b5132 9271
47926f60 9272 /* Check if operand is a register. */
4d1bb795 9273 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9274 {
40fb9820
L		 9275 i386_operand_type temp;
9276
24eab124
AM		 9277 /* Check for a segment override by searching for ':' after a
9278 segment register. */
9279 op_string = end_op;
9280 if (is_space_char (*op_string))
9281 ++op_string;
40fb9820
L		 9282 if (*op_string == ':'
9283 && (r->reg_type.bitfield.sreg2
9284 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9285 {
9286 switch (r->reg_num)
9287 {
9288 case 0:
9289 i.seg[i.mem_operands] = &es;
9290 break;
9291 case 1:
9292 i.seg[i.mem_operands] = &cs;
9293 break;
9294 case 2:
9295 i.seg[i.mem_operands] = &ss;
9296 break;
9297 case 3:
9298 i.seg[i.mem_operands] = &ds;
9299 break;
9300 case 4:
9301 i.seg[i.mem_operands] = &fs;
9302 break;
9303 case 5:
9304 i.seg[i.mem_operands] = &gs;
9305 break;
9306 }
252b5132 9307
24eab124 9308 /* Skip the ':' and whitespace. */
252b5132
RH		 9309 ++op_string;
9310 if (is_space_char (*op_string))
24eab124 9311 ++op_string;
252b5132 9312
24eab124
AM		 9313 if (!is_digit_char (*op_string)
9314 && !is_identifier_char (*op_string)
9315 && *op_string != '('
9316 && *op_string != ABSOLUTE_PREFIX)
9317 {
9318 as_bad (_("bad memory operand `%s'"), op_string);
9319 return 0;
9320 }
47926f60 9321 /* Handle case of %es:*foo. */
24eab124
AM		 9322 if (*op_string == ABSOLUTE_PREFIX)
9323 {
9324 ++op_string;
9325 if (is_space_char (*op_string))
9326 ++op_string;
40fb9820 9327 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9328 }
9329 goto do_memory_reference;
9330 }
43234a1e
L		 9331
9332 /* Handle vector operations. */
9333 if (*op_string == '{')
9334 {
9335 op_string = check_VecOperations (op_string, NULL);
9336 if (op_string == NULL)
9337 return 0;
9338 }
9339
24eab124
AM		 9340 if (*op_string)
9341 {
d0b47220 9342 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9343 return 0;
9344 }
40fb9820
L		 9345 temp = r->reg_type;
9346 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9347 i.types[this_operand] = operand_type_or (i.types[this_operand],
9348 temp);
7d5e4556 9349 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9350 i.op[this_operand].regs = r;
24eab124
AM		 9351 i.reg_operands++;
9352 }
af6bdddf
AM		 9353 else if (*op_string == REGISTER_PREFIX)
9354 {
9355 as_bad (_("bad register name `%s'"), op_string);
9356 return 0;
9357 }
24eab124 9358 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9359 {
24eab124 9360 ++op_string;
40fb9820 9361 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9362 {
d0b47220 9363 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9364 return 0;
9365 }
9366 if (!i386_immediate (op_string))
9367 return 0;
9368 }
43234a1e
L		 9369 else if (RC_SAE_immediate (operand_string))
9370 {
9371 /* If it is a RC or SAE immediate, do nothing. */
9372 ;
9373 }
24eab124
AM		 9374 else if (is_digit_char (*op_string)
9375 || is_identifier_char (*op_string)
d02603dc 9376 || *op_string == '"'
e5cb08ac 9377 || *op_string == '(')
24eab124 9378 {
47926f60 9379 /* This is a memory reference of some sort. */
af6bdddf 9380 char *base_string;
252b5132 9381
47926f60 9382 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9383 char *displacement_string_start;
9384 char *displacement_string_end;
43234a1e 9385 char *vop_start;
252b5132 9386
24eab124 9387 do_memory_reference:
8325cc63
JB		 9388 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9389 return 0;
24eab124 9390 if ((i.mem_operands == 1
40fb9820 9391 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9392 || i.mem_operands == 2)
9393 {
9394 as_bad (_("too many memory references for `%s'"),
9395 current_templates->start->name);
9396 return 0;
9397 }
252b5132 9398
24eab124
AM		 9399 /* Check for base index form. We detect the base index form by
9400 looking for an ')' at the end of the operand, searching
9401 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9402 after the '('. */
af6bdddf 9403 base_string = op_string + strlen (op_string);
c3332e24 9404
43234a1e
L		 9405 /* Handle vector operations. */
9406 vop_start = strchr (op_string, '{');
9407 if (vop_start && vop_start < base_string)
9408 {
9409 if (check_VecOperations (vop_start, base_string) == NULL)
9410 return 0;
9411 base_string = vop_start;
9412 }
9413
af6bdddf
AM		 9414 --base_string;
9415 if (is_space_char (*base_string))
9416 --base_string;
252b5132 9417
47926f60 9418 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9419 displacement_string_start = op_string;
9420 displacement_string_end = base_string + 1;
252b5132 9421
24eab124
AM		 9422 if (*base_string == ')')
9423 {
af6bdddf 9424 char *temp_string;
24eab124
AM		 9425 unsigned int parens_balanced = 1;
9426 /* We've already checked that the number of left & right ()'s are
47926f60 9427 equal, so this loop will not be infinite. */
24eab124
AM		 9428 do
9429 {
9430 base_string--;
9431 if (*base_string == ')')
9432 parens_balanced++;
9433 if (*base_string == '(')
9434 parens_balanced--;
9435 }
9436 while (parens_balanced);
c3332e24 9437
af6bdddf 9438 temp_string = base_string;
c3332e24 9439
24eab124 9440 /* Skip past '(' and whitespace. */
252b5132
RH		 9441 ++base_string;
9442 if (is_space_char (*base_string))
24eab124 9443 ++base_string;
252b5132 9444
af6bdddf 9445 if (*base_string == ','
4eed87de
AM		 9446 || ((i.base_reg = parse_register (base_string, &end_op))
9447 != NULL))
252b5132 9448 {
af6bdddf 9449 displacement_string_end = temp_string;
252b5132 9450
40fb9820 9451 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9452
af6bdddf 9453 if (i.base_reg)
24eab124 9454 {
24eab124
AM		 9455 base_string = end_op;
9456 if (is_space_char (*base_string))
9457 ++base_string;
af6bdddf
AM		 9458 }
9459
9460 /* There may be an index reg or scale factor here. */
9461 if (*base_string == ',')
9462 {
9463 ++base_string;
9464 if (is_space_char (*base_string))
9465 ++base_string;
9466
4eed87de
AM		 9467 if ((i.index_reg = parse_register (base_string, &end_op))
9468 != NULL)
24eab124 9469 {
af6bdddf 9470 base_string = end_op;
24eab124
AM		 9471 if (is_space_char (*base_string))
9472 ++base_string;
af6bdddf
AM		 9473 if (*base_string == ',')
9474 {
9475 ++base_string;
9476 if (is_space_char (*base_string))
9477 ++base_string;
9478 }
e5cb08ac 9479 else if (*base_string != ')')
af6bdddf 9480 {
4eed87de
AM		 9481 as_bad (_("expecting `,' or `)' "
9482 "after index register in `%s'"),
af6bdddf
AM		 9483 operand_string);
9484 return 0;
9485 }
24eab124 9486 }
af6bdddf 9487 else if (*base_string == REGISTER_PREFIX)
24eab124 9488 {
f76bf5e0
L		 9489 end_op = strchr (base_string, ',');
9490 if (end_op)
9491 *end_op = '\0';
af6bdddf 9492 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9493 return 0;
9494 }
252b5132 9495
47926f60 9496 /* Check for scale factor. */
551c1ca1 9497 if (*base_string != ')')
af6bdddf 9498 {
551c1ca1
AM		 9499 char *end_scale = i386_scale (base_string);
9500
9501 if (!end_scale)
af6bdddf 9502 return 0;
24eab124 9503
551c1ca1 9504 base_string = end_scale;
af6bdddf
AM		 9505 if (is_space_char (*base_string))
9506 ++base_string;
9507 if (*base_string != ')')
9508 {
4eed87de
AM		 9509 as_bad (_("expecting `)' "
9510 "after scale factor in `%s'"),
af6bdddf
AM		 9511 operand_string);
9512 return 0;
9513 }
9514 }
9515 else if (!i.index_reg)
24eab124 9516 {
4eed87de
AM		 9517 as_bad (_("expecting index register or scale factor "
9518 "after `,'; got '%c'"),
af6bdddf 9519 *base_string);
24eab124
AM		 9520 return 0;
9521 }
9522 }
af6bdddf 9523 else if (*base_string != ')')
24eab124 9524 {
4eed87de
AM		 9525 as_bad (_("expecting `,' or `)' "
9526 "after base register in `%s'"),
af6bdddf 9527 operand_string);
24eab124
AM		 9528 return 0;
9529 }
c3332e24 9530 }
af6bdddf 9531 else if (*base_string == REGISTER_PREFIX)
c3332e24 9532 {
f76bf5e0
L		 9533 end_op = strchr (base_string, ',');
9534 if (end_op)
9535 *end_op = '\0';
af6bdddf 9536 as_bad (_("bad register name `%s'"), base_string);
24eab124 9537 return 0;
c3332e24 9538 }
24eab124
AM		 9539 }
9540
9541 /* If there's an expression beginning the operand, parse it,
9542 assuming displacement_string_start and
9543 displacement_string_end are meaningful. */
9544 if (displacement_string_start != displacement_string_end)
9545 {
9546 if (!i386_displacement (displacement_string_start,
9547 displacement_string_end))
9548 return 0;
9549 }
9550
9551 /* Special case for (%dx) while doing input/output op. */
9552 if (i.base_reg
0dfbf9d7
L		 9553 && operand_type_equal (&i.base_reg->reg_type,
9554 &reg16_inoutportreg)
24eab124
AM		 9555 && i.index_reg == 0
9556 && i.log2_scale_factor == 0
9557 && i.seg[i.mem_operands] == 0
40fb9820 9558 && !operand_type_check (i.types[this_operand], disp))
24eab124 9559 {
65da13b5 9560 i.types[this_operand] = inoutportreg;
24eab124
AM		 9561 return 1;
9562 }
9563
eecb386c
AM		 9564 if (i386_index_check (operand_string) == 0)
9565 return 0;
5c07affc 9566 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9567 if (i.mem_operands == 0)
9568 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9569 i.mem_operands++;
9570 }
9571 else
ce8a8b2f
AM		 9572 {
9573 /* It's not a memory operand; argh! */
24eab124
AM		 9574 as_bad (_("invalid char %s beginning operand %d `%s'"),
9575 output_invalid (*op_string),
9576 this_operand + 1,
9577 op_string);
9578 return 0;
9579 }
47926f60 9580 return 1; /* Normal return. */
252b5132
RH		 9581}
9582\f
fa94de6b
RM		 9583/* Calculate the maximum variable size (i.e., excluding fr_fix)
9584 that an rs_machine_dependent frag may reach. */
9585
9586unsigned int
9587i386_frag_max_var (fragS *frag)
9588{
9589 /* The only relaxable frags are for jumps.
9590 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9591 gas_assert (frag->fr_type == rs_machine_dependent);
9592 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9593}
9594
b084df0b
L		 9595#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9596static int
8dcea932 9597elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9598{
9599 /* STT_GNU_IFUNC symbol must go through PLT. */
9600 if ((symbol_get_bfdsym (fr_symbol)->flags
9601 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9602 return 0;
9603
9604 if (!S_IS_EXTERNAL (fr_symbol))
9605 /* Symbol may be weak or local. */
9606 return !S_IS_WEAK (fr_symbol);
9607
8dcea932
L		 9608 /* Global symbols with non-default visibility can't be preempted. */
9609 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9610 return 1;
9611
9612 if (fr_var != NO_RELOC)
9613 switch ((enum bfd_reloc_code_real) fr_var)
9614 {
9615 case BFD_RELOC_386_PLT32:
9616 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9617 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9618 return 0;
9619 default:
9620 abort ();
9621 }
9622
b084df0b
L		 9623 /* Global symbols with default visibility in a shared library may be
9624 preempted by another definition. */
8dcea932 9625 return !shared;
b084df0b
L		 9626}
9627#endif
9628
ee7fcc42
AM		 9629/* md_estimate_size_before_relax()
9630
9631 Called just before relax() for rs_machine_dependent frags. The x86
9632 assembler uses these frags to handle variable size jump
9633 instructions.
9634
9635 Any symbol that is now undefined will not become defined.
9636 Return the correct fr_subtype in the frag.
9637 Return the initial "guess for variable size of frag" to caller.
9638 The guess is actually the growth beyond the fixed part. Whatever
9639 we do to grow the fixed or variable part contributes to our
9640 returned value. */
9641
252b5132 9642int
7016a5d5 9643md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9644{
252b5132 9645 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9646 check for un-relaxable symbols. On an ELF system, we can't relax
9647 an externally visible symbol, because it may be overridden by a
9648 shared library. */
9649 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9650#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9651 || (IS_ELF
8dcea932
L		 9652 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9653 fragP->fr_var))
fbeb56a4
DK		 9654#endif
9655#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9656 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9657 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9658#endif
9659 )
252b5132 9660 {
b98ef147
AM		 9661 /* Symbol is undefined in this segment, or we need to keep a
9662 reloc so that weak symbols can be overridden. */
9663 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9664 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9665 unsigned char *opcode;
9666 int old_fr_fix;
f6af82bd 9667
ee7fcc42 9668 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9669 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9670 else if (size == 2)
f6af82bd 9671 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9672#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9673 else if (need_plt32_p (fragP->fr_symbol))
9674 reloc_type = BFD_RELOC_X86_64_PLT32;
9675#endif
f6af82bd
AM		 9676 else
9677 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9678
ee7fcc42
AM		 9679 old_fr_fix = fragP->fr_fix;
9680 opcode = (unsigned char *) fragP->fr_opcode;
9681
fddf5b5b 9682 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9683 {
fddf5b5b
AM		 9684 case UNCOND_JUMP:
9685 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9686 opcode[0] = 0xe9;
252b5132 9687 fragP->fr_fix += size;
062cd5e7
AS		 9688 fix_new (fragP, old_fr_fix, size,
9689 fragP->fr_symbol,
9690 fragP->fr_offset, 1,
9691 reloc_type);
252b5132
RH		 9692 break;
9693
fddf5b5b 9694 case COND_JUMP86:
412167cb
AM		 9695 if (size == 2
9696 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9697 {
9698 /* Negate the condition, and branch past an
9699 unconditional jump. */
9700 opcode[0] ^= 1;
9701 opcode[1] = 3;
9702 /* Insert an unconditional jump. */
9703 opcode[2] = 0xe9;
9704 /* We added two extra opcode bytes, and have a two byte
9705 offset. */
9706 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9707 fix_new (fragP, old_fr_fix + 2, 2,
9708 fragP->fr_symbol,
9709 fragP->fr_offset, 1,
9710 reloc_type);
fddf5b5b
AM		 9711 break;
9712 }
9713 /* Fall through. */
9714
9715 case COND_JUMP:
412167cb
AM		 9716 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9717 {
3e02c1cc
AM		 9718 fixS *fixP;
9719
412167cb 9720 fragP->fr_fix += 1;
3e02c1cc
AM		 9721 fixP = fix_new (fragP, old_fr_fix, 1,
9722 fragP->fr_symbol,
9723 fragP->fr_offset, 1,
9724 BFD_RELOC_8_PCREL);
9725 fixP->fx_signed = 1;
412167cb
AM		 9726 break;
9727 }
93c2a809 9728
24eab124 9729 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9730 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9731 opcode[1] = opcode[0] + 0x10;
f6af82bd 9732 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9733 /* We've added an opcode byte. */
9734 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9735 fix_new (fragP, old_fr_fix + 1, size,
9736 fragP->fr_symbol,
9737 fragP->fr_offset, 1,
9738 reloc_type);
252b5132 9739 break;
fddf5b5b
AM		 9740
9741 default:
9742 BAD_CASE (fragP->fr_subtype);
9743 break;
252b5132
RH		 9744 }
9745 frag_wane (fragP);
ee7fcc42 9746 return fragP->fr_fix - old_fr_fix;
252b5132 9747 }
93c2a809 9748
93c2a809
AM		 9749 /* Guess size depending on current relax state. Initially the relax
9750 state will correspond to a short jump and we return 1, because
9751 the variable part of the frag (the branch offset) is one byte
9752 long. However, we can relax a section more than once and in that
9753 case we must either set fr_subtype back to the unrelaxed state,
9754 or return the value for the appropriate branch. */
9755 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9756}
9757
47926f60
KH		 9758/* Called after relax() is finished.
9759
9760 In: Address of frag.
9761 fr_type == rs_machine_dependent.
9762 fr_subtype is what the address relaxed to.
9763
9764 Out: Any fixSs and constants are set up.
9765 Caller will turn frag into a ".space 0". */
9766
252b5132 9767void
7016a5d5
TG		 9768md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9769 fragS *fragP)
252b5132 9770{
29b0f896 9771 unsigned char *opcode;
252b5132 9772 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9773 offsetT target_address;
9774 offsetT opcode_address;
252b5132 9775 unsigned int extension = 0;
847f7ad4 9776 offsetT displacement_from_opcode_start;
252b5132
RH		 9777
9778 opcode = (unsigned char *) fragP->fr_opcode;
9779
47926f60 9780 /* Address we want to reach in file space. */
252b5132 9781 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9782
47926f60 9783 /* Address opcode resides at in file space. */
252b5132
RH		 9784 opcode_address = fragP->fr_address + fragP->fr_fix;
9785
47926f60 9786 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9787 displacement_from_opcode_start = target_address - opcode_address;
9788
fddf5b5b 9789 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9790 {
47926f60
KH		 9791 /* Don't have to change opcode. */
9792 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9793 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9794 }
9795 else
9796 {
9797 if (no_cond_jump_promotion
9798 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9799 as_warn_where (fragP->fr_file, fragP->fr_line,
9800 _("long jump required"));
252b5132 9801
fddf5b5b
AM		 9802 switch (fragP->fr_subtype)
9803 {
9804 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9805 extension = 4; /* 1 opcode + 4 displacement */
9806 opcode[0] = 0xe9;
9807 where_to_put_displacement = &opcode[1];
9808 break;
252b5132 9809
fddf5b5b
AM		 9810 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9811 extension = 2; /* 1 opcode + 2 displacement */
9812 opcode[0] = 0xe9;
9813 where_to_put_displacement = &opcode[1];
9814 break;
252b5132 9815
fddf5b5b
AM		 9816 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9817 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9818 extension = 5; /* 2 opcode + 4 displacement */
9819 opcode[1] = opcode[0] + 0x10;
9820 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9821 where_to_put_displacement = &opcode[2];
9822 break;
252b5132 9823
fddf5b5b
AM		 9824 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9825 extension = 3; /* 2 opcode + 2 displacement */
9826 opcode[1] = opcode[0] + 0x10;
9827 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9828 where_to_put_displacement = &opcode[2];
9829 break;
252b5132 9830
fddf5b5b
AM		 9831 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9832 extension = 4;
9833 opcode[0] ^= 1;
9834 opcode[1] = 3;
9835 opcode[2] = 0xe9;
9836 where_to_put_displacement = &opcode[3];
9837 break;
9838
9839 default:
9840 BAD_CASE (fragP->fr_subtype);
9841 break;
9842 }
252b5132 9843 }
fddf5b5b 9844
7b81dfbb
AJ		 9845 /* If size if less then four we are sure that the operand fits,
9846 but if it's 4, then it could be that the displacement is larger
9847 then -/+ 2GB. */
9848 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9849 && object_64bit
9850 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9851 + ((addressT) 1 << 31))
9852 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9853 {
9854 as_bad_where (fragP->fr_file, fragP->fr_line,
9855 _("jump target out of range"));
9856 /* Make us emit 0. */
9857 displacement_from_opcode_start = extension;
9858 }
47926f60 9859 /* Now put displacement after opcode. */
252b5132
RH		 9860 md_number_to_chars ((char *) where_to_put_displacement,
9861 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9862 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9863 fragP->fr_fix += extension;
9864}
9865\f
7016a5d5 9866/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9867 by our caller that we have all the info we need to fix it up.
9868
7016a5d5
TG		 9869 Parameter valP is the pointer to the value of the bits.
9870
252b5132
RH		 9871 On the 386, immediates, displacements, and data pointers are all in
9872 the same (little-endian) format, so we don't need to care about which
9873 we are handling. */
9874
94f592af 9875void
7016a5d5 9876md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9877{
94f592af 9878 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9879 valueT value = *valP;
252b5132 9880
f86103b7 9881#if !defined (TE_Mach)
93382f6d
AM		 9882 if (fixP->fx_pcrel)
9883 {
9884 switch (fixP->fx_r_type)
9885 {
5865bb77
ILT		 9886 default:
9887 break;
9888
d6ab8113
JB		 9889 case BFD_RELOC_64:
9890 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9891 break;
93382f6d 9892 case BFD_RELOC_32:
ae8887b5 9893 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9894 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9895 break;
9896 case BFD_RELOC_16:
9897 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9898 break;
9899 case BFD_RELOC_8:
9900 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9901 break;
9902 }
9903 }
252b5132 9904
a161fe53 9905 if (fixP->fx_addsy != NULL
31312f95 9906 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9907 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9908 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9909 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9910 && !use_rela_relocations)
252b5132 9911 {
31312f95
AM		 9912 /* This is a hack. There should be a better way to handle this.
9913 This covers for the fact that bfd_install_relocation will
9914 subtract the current location (for partial_inplace, PC relative
9915 relocations); see more below. */
252b5132 9916#ifndef OBJ_AOUT
718ddfc0 9917 if (IS_ELF
252b5132
RH		 9918#ifdef TE_PE
9919 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9920#endif
9921 )
9922 value += fixP->fx_where + fixP->fx_frag->fr_address;
9923#endif
9924#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9925 if (IS_ELF)
252b5132 9926 {
6539b54b 9927 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9928
6539b54b 9929 if ((sym_seg == seg
2f66722d 9930 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9931 && sym_seg != absolute_section))
af65af87 9932 && !generic_force_reloc (fixP))
2f66722d
AM		 9933 {
9934 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9935 bfd_install_relocation subtracts them out again. I think
9936 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9937 it. FIXME. */
9938 value += fixP->fx_where + fixP->fx_frag->fr_address;
9939 }
252b5132
RH		 9940 }
9941#endif
9942#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9943 /* For some reason, the PE format does not store a
9944 section address offset for a PC relative symbol. */
9945 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9946 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9947 value += md_pcrel_from (fixP);
9948#endif
9949 }
fbeb56a4 9950#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9951 if (fixP->fx_addsy != NULL
9952 && S_IS_WEAK (fixP->fx_addsy)
9953 /* PR 16858: Do not modify weak function references. */
9954 && ! fixP->fx_pcrel)
fbeb56a4 9955 {
296a8689
NC		 9956#if !defined (TE_PEP)
9957 /* For x86 PE weak function symbols are neither PC-relative
9958 nor do they set S_IS_FUNCTION. So the only reliable way
9959 to detect them is to check the flags of their containing
9960 section. */
9961 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9962 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9963 ;
9964 else
9965#endif
fbeb56a4
DK		 9966 value -= S_GET_VALUE (fixP->fx_addsy);
9967 }
9968#endif
252b5132
RH		 9969
9970 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9971 and we must not disappoint it. */
252b5132 9972#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9973 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9974 switch (fixP->fx_r_type)
9975 {
9976 case BFD_RELOC_386_PLT32:
3e73aa7c 9977 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9978 /* Make the jump instruction point to the address of the operand. At
9979 runtime we merely add the offset to the actual PLT entry. */
9980 value = -4;
9981 break;
31312f95 9982
13ae64f3
JJ		 9983 case BFD_RELOC_386_TLS_GD:
9984 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9985 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9986 case BFD_RELOC_386_TLS_IE:
9987 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9988 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9989 case BFD_RELOC_X86_64_TLSGD:
9990 case BFD_RELOC_X86_64_TLSLD:
9991 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9992 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9993 value = 0; /* Fully resolved at runtime. No addend. */
9994 /* Fallthrough */
9995 case BFD_RELOC_386_TLS_LE:
9996 case BFD_RELOC_386_TLS_LDO_32:
9997 case BFD_RELOC_386_TLS_LE_32:
9998 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9999 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10000 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10001 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10002 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10003 break;
10004
67a4f2b7
AO		 10005 case BFD_RELOC_386_TLS_DESC_CALL:
10006 case BFD_RELOC_X86_64_TLSDESC_CALL:
10007 value = 0; /* Fully resolved at runtime. No addend. */
10008 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10009 fixP->fx_done = 0;
10010 return;
10011
47926f60
KH		 10012 case BFD_RELOC_VTABLE_INHERIT:
10013 case BFD_RELOC_VTABLE_ENTRY:
10014 fixP->fx_done = 0;
94f592af 10015 return;
47926f60
KH		 10016
10017 default:
10018 break;
10019 }
10020#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10021 *valP = value;
f86103b7 10022#endif /* !defined (TE_Mach) */
3e73aa7c 10023
3e73aa7c 10024 /* Are we finished with this relocation now? */
c6682705 10025 if (fixP->fx_addsy == NULL)
3e73aa7c 10026 fixP->fx_done = 1;
fbeb56a4
DK		 10027#if defined (OBJ_COFF) && defined (TE_PE)
10028 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10029 {
10030 fixP->fx_done = 0;
10031 /* Remember value for tc_gen_reloc. */
10032 fixP->fx_addnumber = value;
10033 /* Clear out the frag for now. */
10034 value = 0;
10035 }
10036#endif
3e73aa7c
JH		 10037 else if (use_rela_relocations)
10038 {
10039 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10040 /* Remember value for tc_gen_reloc. */
10041 fixP->fx_addnumber = value;
3e73aa7c
JH		 10042 value = 0;
10043 }
f86103b7 10044
94f592af 10045 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10046}
252b5132 10047\f
6d4af3c2 10048const char *
499ac353 10049md_atof (int type, char *litP, int *sizeP)
252b5132 10050{
499ac353
NC		 10051 /* This outputs the LITTLENUMs in REVERSE order;
10052 in accord with the bigendian 386. */
10053 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10054}
10055\f
2d545b82 10056static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10057
252b5132 10058static char *
e3bb37b5 10059output_invalid (int c)
252b5132 10060{
3882b010 10061 if (ISPRINT (c))
f9f21a03
L		 10062 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10063 "'%c'", c);
252b5132 10064 else
f9f21a03 10065 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10066 "(0x%x)", (unsigned char) c);
252b5132
RH		 10067 return output_invalid_buf;
10068}
10069
af6bdddf 10070/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10071
10072static const reg_entry *
4d1bb795 10073parse_real_register (char *reg_string, char **end_op)
252b5132 10074{
af6bdddf
AM		 10075 char *s = reg_string;
10076 char *p;
252b5132
RH		 10077 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10078 const reg_entry *r;
10079
10080 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10081 if (*s == REGISTER_PREFIX)
10082 ++s;
10083
10084 if (is_space_char (*s))
10085 ++s;
10086
10087 p = reg_name_given;
af6bdddf 10088 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10089 {
10090 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10091 return (const reg_entry *) NULL;
10092 s++;
252b5132
RH		 10093 }
10094
6588847e
DN		 10095 /* For naked regs, make sure that we are not dealing with an identifier.
10096 This prevents confusing an identifier like `eax_var' with register
10097 `eax'. */
10098 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10099 return (const reg_entry *) NULL;
10100
af6bdddf 10101 *end_op = s;
252b5132
RH		 10102
10103 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10104
5f47d35b 10105 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10106 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10107 {
5f47d35b
AM		 10108 if (is_space_char (*s))
10109 ++s;
10110 if (*s == '(')
10111 {
af6bdddf 10112 ++s;
5f47d35b
AM		 10113 if (is_space_char (*s))
10114 ++s;
10115 if (*s >= '0' && *s <= '7')
10116 {
db557034 10117 int fpr = *s - '0';
af6bdddf 10118 ++s;
5f47d35b
AM		 10119 if (is_space_char (*s))
10120 ++s;
10121 if (*s == ')')
10122 {
10123 *end_op = s + 1;
1e9cc1c2 10124 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10125 know (r);
10126 return r + fpr;
5f47d35b 10127 }
5f47d35b 10128 }
47926f60 10129 /* We have "%st(" then garbage. */
5f47d35b
AM		 10130 return (const reg_entry *) NULL;
10131 }
10132 }
10133
a60de03c
JB		 10134 if (r == NULL || allow_pseudo_reg)
10135 return r;
10136
0dfbf9d7 10137 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10138 return (const reg_entry *) NULL;
10139
dc821c5f 10140 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10141 || r->reg_type.bitfield.sreg3
10142 || r->reg_type.bitfield.control
10143 || r->reg_type.bitfield.debug
10144 || r->reg_type.bitfield.test)
10145 && !cpu_arch_flags.bitfield.cpui386)
10146 return (const reg_entry *) NULL;
10147
ca0d63fe 10148 if (r->reg_type.bitfield.tbyte
309d3373
JB		 10149 && !cpu_arch_flags.bitfield.cpu8087
10150 && !cpu_arch_flags.bitfield.cpu287
10151 && !cpu_arch_flags.bitfield.cpu387)
10152 return (const reg_entry *) NULL;
10153
1848e567 10154 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 10155 return (const reg_entry *) NULL;
10156
1b54b8d7 10157 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 10158 return (const reg_entry *) NULL;
10159
1b54b8d7 10160 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 10161 return (const reg_entry *) NULL;
10162
1b54b8d7 10163 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 10164 return (const reg_entry *) NULL;
10165
10166 if (r->reg_type.bitfield.regmask
10167 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 10168 return (const reg_entry *) NULL;
10169
db51cc60 10170 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10171 if (!allow_index_reg
db51cc60
L		 10172 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10173 return (const reg_entry *) NULL;
10174
43234a1e
L		 10175 /* Upper 16 vector register is only available with VREX in 64bit
10176 mode. */
10177 if ((r->reg_flags & RegVRex))
10178 {
86fa6981
L		 10179 if (i.vec_encoding == vex_encoding_default)
10180 i.vec_encoding = vex_encoding_evex;
10181
43234a1e 10182 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 10183 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 10184 || flag_code != CODE_64BIT)
10185 return (const reg_entry *) NULL;
43234a1e
L		 10186 }
10187
a60de03c 10188 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10189 || r->reg_type.bitfield.qword)
40fb9820 10190 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10191 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10192 && flag_code != CODE_64BIT)
20f0a1fc 10193 return (const reg_entry *) NULL;
1ae00879 10194
b7240065
JB		 10195 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10196 return (const reg_entry *) NULL;
10197
252b5132
RH		 10198 return r;
10199}
4d1bb795
JB		 10200
10201/* REG_STRING starts *before* REGISTER_PREFIX. */
10202
10203static const reg_entry *
10204parse_register (char *reg_string, char **end_op)
10205{
10206 const reg_entry *r;
10207
10208 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10209 r = parse_real_register (reg_string, end_op);
10210 else
10211 r = NULL;
10212 if (!r)
10213 {
10214 char *save = input_line_pointer;
10215 char c;
10216 symbolS *symbolP;
10217
10218 input_line_pointer = reg_string;
d02603dc 10219 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10220 symbolP = symbol_find (reg_string);
10221 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10222 {
10223 const expressionS *e = symbol_get_value_expression (symbolP);
10224
0398aac5 10225 know (e->X_op == O_register);
4eed87de 10226 know (e->X_add_number >= 0
c3fe08fa 10227 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10228 r = i386_regtab + e->X_add_number;
d3bb6b49 10229 if ((r->reg_flags & RegVRex))
86fa6981 10230 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10231 *end_op = input_line_pointer;
10232 }
10233 *input_line_pointer = c;
10234 input_line_pointer = save;
10235 }
10236 return r;
10237}
10238
10239int
10240i386_parse_name (char *name, expressionS *e, char *nextcharP)
10241{
10242 const reg_entry *r;
10243 char *end = input_line_pointer;
10244
10245 *end = *nextcharP;
10246 r = parse_register (name, &input_line_pointer);
10247 if (r && end <= input_line_pointer)
10248 {
10249 *nextcharP = *input_line_pointer;
10250 *input_line_pointer = 0;
10251 e->X_op = O_register;
10252 e->X_add_number = r - i386_regtab;
10253 return 1;
10254 }
10255 input_line_pointer = end;
10256 *end = 0;
ee86248c 10257 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10258}
10259
10260void
10261md_operand (expressionS *e)
10262{
ee86248c
JB		 10263 char *end;
10264 const reg_entry *r;
4d1bb795 10265
ee86248c
JB		 10266 switch (*input_line_pointer)
10267 {
10268 case REGISTER_PREFIX:
10269 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10270 if (r)
10271 {
10272 e->X_op = O_register;
10273 e->X_add_number = r - i386_regtab;
10274 input_line_pointer = end;
10275 }
ee86248c
JB		 10276 break;
10277
10278 case '[':
9c2799c2 10279 gas_assert (intel_syntax);
ee86248c
JB		 10280 end = input_line_pointer++;
10281 expression (e);
10282 if (*input_line_pointer == ']')
10283 {
10284 ++input_line_pointer;
10285 e->X_op_symbol = make_expr_symbol (e);
10286 e->X_add_symbol = NULL;
10287 e->X_add_number = 0;
10288 e->X_op = O_index;
10289 }
10290 else
10291 {
10292 e->X_op = O_absent;
10293 input_line_pointer = end;
10294 }
10295 break;
4d1bb795
JB		 10296 }
10297}
10298
252b5132 10299\f
4cc782b5 10300#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10301const char *md_shortopts = "kVQ:sqnO::";
252b5132 10302#else
b6f8c7c4 10303const char *md_shortopts = "qnO::";
252b5132 10304#endif
6e0b89ee 10305
3e73aa7c 10306#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10307#define OPTION_64 (OPTION_MD_BASE + 1)
10308#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10309#define OPTION_MARCH (OPTION_MD_BASE + 3)
10310#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10311#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10312#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10313#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10314#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10315#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 10316#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10317#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10318#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10319#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10320#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10321#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10322#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10323#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10324#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10325#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10326#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10327#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10328#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10329#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10330#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 10331#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 10332
99ad8390
NC		 10333struct option md_longopts[] =
10334{
3e73aa7c 10335 {"32", no_argument, NULL, OPTION_32},
321098a5 10336#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10337 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10338 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10339#endif
10340#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10341 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10342 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10343#endif
b3b91714 10344 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10345 {"march", required_argument, NULL, OPTION_MARCH},
10346 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10347 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10348 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10349 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10350 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10351 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 10352 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10353 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10354 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10355 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10356 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10357 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10358 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10359# if defined (TE_PE) || defined (TE_PEP)
10360 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10361#endif
d1982f93 10362 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10363 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10364 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10365 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10366 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10367 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10368 {NULL, no_argument, NULL, 0}
10369};
10370size_t md_longopts_size = sizeof (md_longopts);
10371
10372int
17b9d67d 10373md_parse_option (int c, const char *arg)
252b5132 10374{
91d6fa6a 10375 unsigned int j;
293f5f65 10376 char *arch, *next, *saved;
9103f4f4 10377
252b5132
RH		 10378 switch (c)
10379 {
12b55ccc
L		 10380 case 'n':
10381 optimize_align_code = 0;
10382 break;
10383
a38cf1db
AM		 10384 case 'q':
10385 quiet_warnings = 1;
252b5132
RH		 10386 break;
10387
10388#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10389 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10390 should be emitted or not. FIXME: Not implemented. */
10391 case 'Q':
252b5132
RH		 10392 break;
10393
10394 /* -V: SVR4 argument to print version ID. */
10395 case 'V':
10396 print_version_id ();
10397 break;
10398
a38cf1db
AM		 10399 /* -k: Ignore for FreeBSD compatibility. */
10400 case 'k':
252b5132 10401 break;
4cc782b5
ILT		 10402
10403 case 's':
10404 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10405 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10406 break;
8dcea932
L		 10407
10408 case OPTION_MSHARED:
10409 shared = 1;
10410 break;
99ad8390 10411#endif
321098a5 10412#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10413 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10414 case OPTION_64:
10415 {
10416 const char **list, **l;
10417
3e73aa7c
JH		 10418 list = bfd_target_list ();
10419 for (l = list; *l != NULL; l++)
8620418b 10420 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10421 || strcmp (*l, "coff-x86-64") == 0
10422 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10423 || strcmp (*l, "pei-x86-64") == 0
10424 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10425 {
10426 default_arch = "x86_64";
10427 break;
10428 }
3e73aa7c 10429 if (*l == NULL)
2b5d6a91 10430 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10431 free (list);
10432 }
10433 break;
10434#endif
252b5132 10435
351f65ca 10436#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10437 case OPTION_X32:
351f65ca
L		 10438 if (IS_ELF)
10439 {
10440 const char **list, **l;
10441
10442 list = bfd_target_list ();
10443 for (l = list; *l != NULL; l++)
10444 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10445 {
10446 default_arch = "x86_64:32";
10447 break;
10448 }
10449 if (*l == NULL)
2b5d6a91 10450 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10451 free (list);
10452 }
10453 else
10454 as_fatal (_("32bit x86_64 is only supported for ELF"));
10455 break;
10456#endif
10457
6e0b89ee
AM		 10458 case OPTION_32:
10459 default_arch = "i386";
10460 break;
10461
b3b91714
AM		 10462 case OPTION_DIVIDE:
10463#ifdef SVR4_COMMENT_CHARS
10464 {
10465 char *n, *t;
10466 const char *s;
10467
add39d23 10468 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10469 t = n;
10470 for (s = i386_comment_chars; *s != '\0'; s++)
10471 if (*s != '/')
10472 *t++ = *s;
10473 *t = '\0';
10474 i386_comment_chars = n;
10475 }
10476#endif
10477 break;
10478
9103f4f4 10479 case OPTION_MARCH:
293f5f65
L		 10480 saved = xstrdup (arg);
10481 arch = saved;
10482 /* Allow -march=+nosse. */
10483 if (*arch == '+')
10484 arch++;
6305a203 10485 do
9103f4f4 10486 {
6305a203 10487 if (*arch == '.')
2b5d6a91 10488 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10489 next = strchr (arch, '+');
10490 if (next)
10491 *next++ = '\0';
91d6fa6a 10492 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10493 {
91d6fa6a 10494 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10495 {
6305a203 10496 /* Processor. */
1ded5609
JB		 10497 if (! cpu_arch[j].flags.bitfield.cpui386)
10498 continue;
10499
91d6fa6a 10500 cpu_arch_name = cpu_arch[j].name;
6305a203 10501 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10502 cpu_arch_flags = cpu_arch[j].flags;
10503 cpu_arch_isa = cpu_arch[j].type;
10504 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10505 if (!cpu_arch_tune_set)
10506 {
10507 cpu_arch_tune = cpu_arch_isa;
10508 cpu_arch_tune_flags = cpu_arch_isa_flags;
10509 }
10510 break;
10511 }
91d6fa6a
NC		 10512 else if (*cpu_arch [j].name == '.'
10513 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10514 {
33eaf5de 10515 /* ISA extension. */
6305a203 10516 i386_cpu_flags flags;
309d3373 10517
293f5f65
L		 10518 flags = cpu_flags_or (cpu_arch_flags,
10519 cpu_arch[j].flags);
81486035 10520
5b64d091 10521 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10522 {
10523 if (cpu_sub_arch_name)
10524 {
10525 char *name = cpu_sub_arch_name;
10526 cpu_sub_arch_name = concat (name,
91d6fa6a 10527 cpu_arch[j].name,
1bf57e9f 10528 (const char *) NULL);
6305a203
L		 10529 free (name);
10530 }
10531 else
91d6fa6a 10532 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10533 cpu_arch_flags = flags;
a586129e 10534 cpu_arch_isa_flags = flags;
6305a203
L		 10535 }
10536 break;
ccc9c027 10537 }
9103f4f4 10538 }
6305a203 10539
293f5f65
L		 10540 if (j >= ARRAY_SIZE (cpu_arch))
10541 {
33eaf5de 10542 /* Disable an ISA extension. */
293f5f65
L		 10543 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10544 if (strcmp (arch, cpu_noarch [j].name) == 0)
10545 {
10546 i386_cpu_flags flags;
10547
10548 flags = cpu_flags_and_not (cpu_arch_flags,
10549 cpu_noarch[j].flags);
10550 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10551 {
10552 if (cpu_sub_arch_name)
10553 {
10554 char *name = cpu_sub_arch_name;
10555 cpu_sub_arch_name = concat (arch,
10556 (const char *) NULL);
10557 free (name);
10558 }
10559 else
10560 cpu_sub_arch_name = xstrdup (arch);
10561 cpu_arch_flags = flags;
10562 cpu_arch_isa_flags = flags;
10563 }
10564 break;
10565 }
10566
10567 if (j >= ARRAY_SIZE (cpu_noarch))
10568 j = ARRAY_SIZE (cpu_arch);
10569 }
10570
91d6fa6a 10571 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10572 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10573
10574 arch = next;
9103f4f4 10575 }
293f5f65
L		 10576 while (next != NULL);
10577 free (saved);
9103f4f4
L		 10578 break;
10579
10580 case OPTION_MTUNE:
10581 if (*arg == '.')
2b5d6a91 10582 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10583 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10584 {
91d6fa6a 10585 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10586 {
ccc9c027 10587 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10588 cpu_arch_tune = cpu_arch [j].type;
10589 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10590 break;
10591 }
10592 }
91d6fa6a 10593 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10594 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10595 break;
10596
1efbbeb4
L		 10597 case OPTION_MMNEMONIC:
10598 if (strcasecmp (arg, "att") == 0)
10599 intel_mnemonic = 0;
10600 else if (strcasecmp (arg, "intel") == 0)
10601 intel_mnemonic = 1;
10602 else
2b5d6a91 10603 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10604 break;
10605
10606 case OPTION_MSYNTAX:
10607 if (strcasecmp (arg, "att") == 0)
10608 intel_syntax = 0;
10609 else if (strcasecmp (arg, "intel") == 0)
10610 intel_syntax = 1;
10611 else
2b5d6a91 10612 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10613 break;
10614
10615 case OPTION_MINDEX_REG:
10616 allow_index_reg = 1;
10617 break;
10618
10619 case OPTION_MNAKED_REG:
10620 allow_naked_reg = 1;
10621 break;
10622
10623 case OPTION_MOLD_GCC:
10624 old_gcc = 1;
1efbbeb4
L		 10625 break;
10626
c0f3af97
L		 10627 case OPTION_MSSE2AVX:
10628 sse2avx = 1;
10629 break;
10630
daf50ae7
L		 10631 case OPTION_MSSE_CHECK:
10632 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10633 sse_check = check_error;
daf50ae7 10634 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10635 sse_check = check_warning;
daf50ae7 10636 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10637 sse_check = check_none;
daf50ae7 10638 else
2b5d6a91 10639 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10640 break;
10641
7bab8ab5
JB		 10642 case OPTION_MOPERAND_CHECK:
10643 if (strcasecmp (arg, "error") == 0)
10644 operand_check = check_error;
10645 else if (strcasecmp (arg, "warning") == 0)
10646 operand_check = check_warning;
10647 else if (strcasecmp (arg, "none") == 0)
10648 operand_check = check_none;
10649 else
10650 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10651 break;
10652
539f890d
L		 10653 case OPTION_MAVXSCALAR:
10654 if (strcasecmp (arg, "128") == 0)
10655 avxscalar = vex128;
10656 else if (strcasecmp (arg, "256") == 0)
10657 avxscalar = vex256;
10658 else
2b5d6a91 10659 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10660 break;
10661
7e8b059b
L		 10662 case OPTION_MADD_BND_PREFIX:
10663 add_bnd_prefix = 1;
10664 break;
10665
43234a1e
L		 10666 case OPTION_MEVEXLIG:
10667 if (strcmp (arg, "128") == 0)
10668 evexlig = evexl128;
10669 else if (strcmp (arg, "256") == 0)
10670 evexlig = evexl256;
10671 else if (strcmp (arg, "512") == 0)
10672 evexlig = evexl512;
10673 else
10674 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10675 break;
10676
d3d3c6db
IT		 10677 case OPTION_MEVEXRCIG:
10678 if (strcmp (arg, "rne") == 0)
10679 evexrcig = rne;
10680 else if (strcmp (arg, "rd") == 0)
10681 evexrcig = rd;
10682 else if (strcmp (arg, "ru") == 0)
10683 evexrcig = ru;
10684 else if (strcmp (arg, "rz") == 0)
10685 evexrcig = rz;
10686 else
10687 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10688 break;
10689
43234a1e
L		 10690 case OPTION_MEVEXWIG:
10691 if (strcmp (arg, "0") == 0)
10692 evexwig = evexw0;
10693 else if (strcmp (arg, "1") == 0)
10694 evexwig = evexw1;
10695 else
10696 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10697 break;
10698
167ad85b
TG		 10699# if defined (TE_PE) || defined (TE_PEP)
10700 case OPTION_MBIG_OBJ:
10701 use_big_obj = 1;
10702 break;
10703#endif
10704
d1982f93 10705 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10706 if (strcasecmp (arg, "yes") == 0)
10707 omit_lock_prefix = 1;
10708 else if (strcasecmp (arg, "no") == 0)
10709 omit_lock_prefix = 0;
10710 else
10711 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10712 break;
10713
e4e00185
AS		 10714 case OPTION_MFENCE_AS_LOCK_ADD:
10715 if (strcasecmp (arg, "yes") == 0)
10716 avoid_fence = 1;
10717 else if (strcasecmp (arg, "no") == 0)
10718 avoid_fence = 0;
10719 else
10720 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10721 break;
10722
0cb4071e
L		 10723 case OPTION_MRELAX_RELOCATIONS:
10724 if (strcasecmp (arg, "yes") == 0)
10725 generate_relax_relocations = 1;
10726 else if (strcasecmp (arg, "no") == 0)
10727 generate_relax_relocations = 0;
10728 else
10729 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10730 break;
10731
5db04b09 10732 case OPTION_MAMD64:
e89c5eaa 10733 intel64 = 0;
5db04b09
L		 10734 break;
10735
10736 case OPTION_MINTEL64:
e89c5eaa 10737 intel64 = 1;
5db04b09
L		 10738 break;
10739
b6f8c7c4
L		 10740 case 'O':
10741 if (arg == NULL)
10742 {
10743 optimize = 1;
10744 /* Turn off -Os. */
10745 optimize_for_space = 0;
10746 }
10747 else if (*arg == 's')
10748 {
10749 optimize_for_space = 1;
10750 /* Turn on all encoding optimizations. */
10751 optimize = -1;
10752 }
10753 else
10754 {
10755 optimize = atoi (arg);
10756 /* Turn off -Os. */
10757 optimize_for_space = 0;
10758 }
10759 break;
10760
252b5132
RH		 10761 default:
10762 return 0;
10763 }
10764 return 1;
10765}
10766
8a2c8fef
L		 10767#define MESSAGE_TEMPLATE \
10768" "
10769
293f5f65
L		 10770static char *
10771output_message (FILE *stream, char *p, char *message, char *start,
10772 int *left_p, const char *name, int len)
10773{
10774 int size = sizeof (MESSAGE_TEMPLATE);
10775 int left = *left_p;
10776
10777 /* Reserve 2 spaces for ", " or ",\0" */
10778 left -= len + 2;
10779
10780 /* Check if there is any room. */
10781 if (left >= 0)
10782 {
10783 if (p != start)
10784 {
10785 *p++ = ',';
10786 *p++ = ' ';
10787 }
10788 p = mempcpy (p, name, len);
10789 }
10790 else
10791 {
10792 /* Output the current message now and start a new one. */
10793 *p++ = ',';
10794 *p = '\0';
10795 fprintf (stream, "%s\n", message);
10796 p = start;
10797 left = size - (start - message) - len - 2;
10798
10799 gas_assert (left >= 0);
10800
10801 p = mempcpy (p, name, len);
10802 }
10803
10804 *left_p = left;
10805 return p;
10806}
10807
8a2c8fef 10808static void
1ded5609 10809show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10810{
10811 static char message[] = MESSAGE_TEMPLATE;
10812 char *start = message + 27;
10813 char *p;
10814 int size = sizeof (MESSAGE_TEMPLATE);
10815 int left;
10816 const char *name;
10817 int len;
10818 unsigned int j;
10819
10820 p = start;
10821 left = size - (start - message);
10822 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10823 {
10824 /* Should it be skipped? */
10825 if (cpu_arch [j].skip)
10826 continue;
10827
10828 name = cpu_arch [j].name;
10829 len = cpu_arch [j].len;
10830 if (*name == '.')
10831 {
10832 /* It is an extension. Skip if we aren't asked to show it. */
10833 if (ext)
10834 {
10835 name++;
10836 len--;
10837 }
10838 else
10839 continue;
10840 }
10841 else if (ext)
10842 {
10843 /* It is an processor. Skip if we show only extension. */
10844 continue;
10845 }
1ded5609
JB		 10846 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10847 {
10848 /* It is an impossible processor - skip. */
10849 continue;
10850 }
8a2c8fef 10851
293f5f65 10852 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10853 }
10854
293f5f65
L		 10855 /* Display disabled extensions. */
10856 if (ext)
10857 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10858 {
10859 name = cpu_noarch [j].name;
10860 len = cpu_noarch [j].len;
10861 p = output_message (stream, p, message, start, &left, name,
10862 len);
10863 }
10864
8a2c8fef
L		 10865 *p = '\0';
10866 fprintf (stream, "%s\n", message);
10867}
10868
252b5132 10869void
8a2c8fef 10870md_show_usage (FILE *stream)
252b5132 10871{
4cc782b5
ILT		 10872#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10873 fprintf (stream, _("\
a38cf1db
AM		 10874 -Q ignored\n\
10875 -V print assembler version number\n\
b3b91714
AM		 10876 -k ignored\n"));
10877#endif
10878 fprintf (stream, _("\
12b55ccc 10879 -n Do not optimize code alignment\n\
b3b91714
AM		 10880 -q quieten some warnings\n"));
10881#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10882 fprintf (stream, _("\
a38cf1db 10883 -s ignored\n"));
b3b91714 10884#endif
321098a5
L		 10885#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10886 || defined (TE_PE) || defined (TE_PEP))
751d281c 10887 fprintf (stream, _("\
570561f7 10888 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10889#endif
b3b91714
AM		 10890#ifdef SVR4_COMMENT_CHARS
10891 fprintf (stream, _("\
10892 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10893#else
10894 fprintf (stream, _("\
b3b91714 10895 --divide ignored\n"));
4cc782b5 10896#endif
9103f4f4 10897 fprintf (stream, _("\
6305a203 10898 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10899 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10900 show_arch (stream, 0, 1);
8a2c8fef
L		 10901 fprintf (stream, _("\
10902 EXTENSION is combination of:\n"));
1ded5609 10903 show_arch (stream, 1, 0);
6305a203 10904 fprintf (stream, _("\
8a2c8fef 10905 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10906 show_arch (stream, 0, 0);
ba104c83 10907 fprintf (stream, _("\
c0f3af97
L		 10908 -msse2avx encode SSE instructions with VEX prefix\n"));
10909 fprintf (stream, _("\
daf50ae7
L		 10910 -msse-check=[none|error|warning]\n\
10911 check SSE instructions\n"));
10912 fprintf (stream, _("\
7bab8ab5
JB		 10913 -moperand-check=[none|error|warning]\n\
10914 check operand combinations for validity\n"));
10915 fprintf (stream, _("\
539f890d
L		 10916 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10917 length\n"));
10918 fprintf (stream, _("\
43234a1e
L		 10919 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10920 length\n"));
10921 fprintf (stream, _("\
10922 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10923 for EVEX.W bit ignored instructions\n"));
10924 fprintf (stream, _("\
d3d3c6db
IT		 10925 -mevexrcig=[rne|rd|ru|rz]\n\
10926 encode EVEX instructions with specific EVEX.RC value\n\
10927 for SAE-only ignored instructions\n"));
10928 fprintf (stream, _("\
ba104c83
L		 10929 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10930 fprintf (stream, _("\
10931 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10932 fprintf (stream, _("\
10933 -mindex-reg support pseudo index registers\n"));
10934 fprintf (stream, _("\
10935 -mnaked-reg don't require `%%' prefix for registers\n"));
10936 fprintf (stream, _("\
10937 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10938 fprintf (stream, _("\
10939 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10940 fprintf (stream, _("\
10941 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10942# if defined (TE_PE) || defined (TE_PEP)
10943 fprintf (stream, _("\
10944 -mbig-obj generate big object files\n"));
10945#endif
d022bddd
IT		 10946 fprintf (stream, _("\
10947 -momit-lock-prefix=[no|yes]\n\
10948 strip all lock prefixes\n"));
5db04b09 10949 fprintf (stream, _("\
e4e00185
AS		 10950 -mfence-as-lock-add=[no|yes]\n\
10951 encode lfence, mfence and sfence as\n\
10952 lock addl $0x0, (%%{re}sp)\n"));
10953 fprintf (stream, _("\
0cb4071e
L		 10954 -mrelax-relocations=[no|yes]\n\
10955 generate relax relocations\n"));
10956 fprintf (stream, _("\
5db04b09
L		 10957 -mamd64 accept only AMD64 ISA\n"));
10958 fprintf (stream, _("\
10959 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10960}
10961
3e73aa7c 10962#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10963 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10964 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10965
10966/* Pick the target format to use. */
10967
47926f60 10968const char *
e3bb37b5 10969i386_target_format (void)
252b5132 10970{
351f65ca
L		 10971 if (!strncmp (default_arch, "x86_64", 6))
10972 {
10973 update_code_flag (CODE_64BIT, 1);
10974 if (default_arch[6] == '\0')
7f56bc95 10975 x86_elf_abi = X86_64_ABI;
351f65ca 10976 else
7f56bc95 10977 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10978 }
3e73aa7c 10979 else if (!strcmp (default_arch, "i386"))
78f12dd3 10980 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10981 else if (!strcmp (default_arch, "iamcu"))
10982 {
10983 update_code_flag (CODE_32BIT, 1);
10984 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10985 {
10986 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10987 cpu_arch_name = "iamcu";
10988 cpu_sub_arch_name = NULL;
10989 cpu_arch_flags = iamcu_flags;
10990 cpu_arch_isa = PROCESSOR_IAMCU;
10991 cpu_arch_isa_flags = iamcu_flags;
10992 if (!cpu_arch_tune_set)
10993 {
10994 cpu_arch_tune = cpu_arch_isa;
10995 cpu_arch_tune_flags = cpu_arch_isa_flags;
10996 }
10997 }
8d471ec1 10998 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10999 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11000 cpu_arch_name);
11001 }
3e73aa7c 11002 else
2b5d6a91 11003 as_fatal (_("unknown architecture"));
89507696
JB		 11004
11005 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11006 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11007 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11008 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11009
252b5132
RH		 11010 switch (OUTPUT_FLAVOR)
11011 {
9384f2ff 11012#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11013 case bfd_target_aout_flavour:
47926f60 11014 return AOUT_TARGET_FORMAT;
4c63da97 11015#endif
9384f2ff
AM		 11016#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11017# if defined (TE_PE) || defined (TE_PEP)
11018 case bfd_target_coff_flavour:
167ad85b
TG		 11019 if (flag_code == CODE_64BIT)
11020 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11021 else
11022 return "pe-i386";
9384f2ff 11023# elif defined (TE_GO32)
0561d57c
JK		 11024 case bfd_target_coff_flavour:
11025 return "coff-go32";
9384f2ff 11026# else
252b5132
RH		 11027 case bfd_target_coff_flavour:
11028 return "coff-i386";
9384f2ff 11029# endif
4c63da97 11030#endif
3e73aa7c 11031#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11032 case bfd_target_elf_flavour:
3e73aa7c 11033 {
351f65ca
L		 11034 const char *format;
11035
11036 switch (x86_elf_abi)
4fa24527 11037 {
351f65ca
L		 11038 default:
11039 format = ELF_TARGET_FORMAT;
11040 break;
7f56bc95 11041 case X86_64_ABI:
351f65ca 11042 use_rela_relocations = 1;
4fa24527 11043 object_64bit = 1;
351f65ca
L		 11044 format = ELF_TARGET_FORMAT64;
11045 break;
7f56bc95 11046 case X86_64_X32_ABI:
4fa24527 11047 use_rela_relocations = 1;
351f65ca 11048 object_64bit = 1;
862be3fb 11049 disallow_64bit_reloc = 1;
351f65ca
L		 11050 format = ELF_TARGET_FORMAT32;
11051 break;
4fa24527 11052 }
3632d14b 11053 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11054 {
7f56bc95 11055 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11056 as_fatal (_("Intel L1OM is 64bit only"));
11057 return ELF_TARGET_L1OM_FORMAT;
11058 }
b49f93f6 11059 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11060 {
11061 if (x86_elf_abi != X86_64_ABI)
11062 as_fatal (_("Intel K1OM is 64bit only"));
11063 return ELF_TARGET_K1OM_FORMAT;
11064 }
81486035
L		 11065 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11066 {
11067 if (x86_elf_abi != I386_ABI)
11068 as_fatal (_("Intel MCU is 32bit only"));
11069 return ELF_TARGET_IAMCU_FORMAT;
11070 }
8a9036a4 11071 else
351f65ca 11072 return format;
3e73aa7c 11073 }
e57f8c65
TG		 11074#endif
11075#if defined (OBJ_MACH_O)
11076 case bfd_target_mach_o_flavour:
d382c579
TG		 11077 if (flag_code == CODE_64BIT)
11078 {
11079 use_rela_relocations = 1;
11080 object_64bit = 1;
11081 return "mach-o-x86-64";
11082 }
11083 else
11084 return "mach-o-i386";
4c63da97 11085#endif
252b5132
RH		 11086 default:
11087 abort ();
11088 return NULL;
11089 }
11090}
11091
47926f60 11092#endif /* OBJ_MAYBE_ more than one */
252b5132 11093\f
252b5132 11094symbolS *
7016a5d5 11095md_undefined_symbol (char *name)
252b5132 11096{
18dc2407
ILT		 11097 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11098 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11099 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11100 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11101 {
11102 if (!GOT_symbol)
11103 {
11104 if (symbol_find (name))
11105 as_bad (_("GOT already in symbol table"));
11106 GOT_symbol = symbol_new (name, undefined_section,
11107 (valueT) 0, &zero_address_frag);
11108 };
11109 return GOT_symbol;
11110 }
252b5132
RH		 11111 return 0;
11112}
11113
11114/* Round up a section size to the appropriate boundary. */
47926f60 11115
252b5132 11116valueT
7016a5d5 11117md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11118{
4c63da97
AM		 11119#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11120 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11121 {
11122 /* For a.out, force the section size to be aligned. If we don't do
11123 this, BFD will align it for us, but it will not write out the
11124 final bytes of the section. This may be a bug in BFD, but it is
11125 easier to fix it here since that is how the other a.out targets
11126 work. */
11127 int align;
11128
11129 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11130 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11131 }
252b5132
RH		 11132#endif
11133
11134 return size;
11135}
11136
11137/* On the i386, PC-relative offsets are relative to the start of the
11138 next instruction. That is, the address of the offset, plus its
11139 size, since the offset is always the last part of the insn. */
11140
11141long
e3bb37b5 11142md_pcrel_from (fixS *fixP)
252b5132
RH		 11143{
11144 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11145}
11146
11147#ifndef I386COFF
11148
11149static void
e3bb37b5 11150s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11151{
29b0f896 11152 int temp;
252b5132 11153
8a75718c
JB		 11154#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11155 if (IS_ELF)
11156 obj_elf_section_change_hook ();
11157#endif
252b5132
RH		 11158 temp = get_absolute_expression ();
11159 subseg_set (bss_section, (subsegT) temp);
11160 demand_empty_rest_of_line ();
11161}
11162
11163#endif
11164
252b5132 11165void
e3bb37b5 11166i386_validate_fix (fixS *fixp)
252b5132 11167{
02a86693 11168 if (fixp->fx_subsy)
252b5132 11169 {
02a86693 11170 if (fixp->fx_subsy == GOT_symbol)
23df1078 11171 {
02a86693
L		 11172 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11173 {
11174 if (!object_64bit)
11175 abort ();
11176#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11177 if (fixp->fx_tcbit2)
56ceb5b5
L		 11178 fixp->fx_r_type = (fixp->fx_tcbit
11179 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11180 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11181 else
11182#endif
11183 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11184 }
d6ab8113 11185 else
02a86693
L		 11186 {
11187 if (!object_64bit)
11188 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11189 else
11190 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11191 }
11192 fixp->fx_subsy = 0;
23df1078 11193 }
252b5132 11194 }
02a86693
L		 11195#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11196 else if (!object_64bit)
11197 {
11198 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11199 && fixp->fx_tcbit2)
11200 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11201 }
11202#endif
252b5132
RH		 11203}
11204
252b5132 11205arelent *
7016a5d5 11206tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11207{
11208 arelent *rel;
11209 bfd_reloc_code_real_type code;
11210
11211 switch (fixp->fx_r_type)
11212 {
8ce3d284 11213#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11214 case BFD_RELOC_SIZE32:
11215 case BFD_RELOC_SIZE64:
11216 if (S_IS_DEFINED (fixp->fx_addsy)
11217 && !S_IS_EXTERNAL (fixp->fx_addsy))
11218 {
11219 /* Resolve size relocation against local symbol to size of
11220 the symbol plus addend. */
11221 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11222 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11223 && !fits_in_unsigned_long (value))
11224 as_bad_where (fixp->fx_file, fixp->fx_line,
11225 _("symbol size computation overflow"));
11226 fixp->fx_addsy = NULL;
11227 fixp->fx_subsy = NULL;
11228 md_apply_fix (fixp, (valueT *) &value, NULL);
11229 return NULL;
11230 }
8ce3d284 11231#endif
1a0670f3 11232 /* Fall through. */
8fd4256d 11233
3e73aa7c
JH		 11234 case BFD_RELOC_X86_64_PLT32:
11235 case BFD_RELOC_X86_64_GOT32:
11236 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11237 case BFD_RELOC_X86_64_GOTPCRELX:
11238 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11239 case BFD_RELOC_386_PLT32:
11240 case BFD_RELOC_386_GOT32:
02a86693 11241 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11242 case BFD_RELOC_386_GOTOFF:
11243 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11244 case BFD_RELOC_386_TLS_GD:
11245 case BFD_RELOC_386_TLS_LDM:
11246 case BFD_RELOC_386_TLS_LDO_32:
11247 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11248 case BFD_RELOC_386_TLS_IE:
11249 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11250 case BFD_RELOC_386_TLS_LE_32:
11251 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11252 case BFD_RELOC_386_TLS_GOTDESC:
11253 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11254 case BFD_RELOC_X86_64_TLSGD:
11255 case BFD_RELOC_X86_64_TLSLD:
11256 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11257 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11258 case BFD_RELOC_X86_64_GOTTPOFF:
11259 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11260 case BFD_RELOC_X86_64_TPOFF64:
11261 case BFD_RELOC_X86_64_GOTOFF64:
11262 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11263 case BFD_RELOC_X86_64_GOT64:
11264 case BFD_RELOC_X86_64_GOTPCREL64:
11265 case BFD_RELOC_X86_64_GOTPC64:
11266 case BFD_RELOC_X86_64_GOTPLT64:
11267 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11268 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11269 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11270 case BFD_RELOC_RVA:
11271 case BFD_RELOC_VTABLE_ENTRY:
11272 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11273#ifdef TE_PE
11274 case BFD_RELOC_32_SECREL:
11275#endif
252b5132
RH		 11276 code = fixp->fx_r_type;
11277 break;
dbbaec26
L		 11278 case BFD_RELOC_X86_64_32S:
11279 if (!fixp->fx_pcrel)
11280 {
11281 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11282 code = fixp->fx_r_type;
11283 break;
11284 }
1a0670f3 11285 /* Fall through. */
252b5132 11286 default:
93382f6d 11287 if (fixp->fx_pcrel)
252b5132 11288 {
93382f6d
AM		 11289 switch (fixp->fx_size)
11290 {
11291 default:
b091f402
AM		 11292 as_bad_where (fixp->fx_file, fixp->fx_line,
11293 _("can not do %d byte pc-relative relocation"),
11294 fixp->fx_size);
93382f6d
AM		 11295 code = BFD_RELOC_32_PCREL;
11296 break;
11297 case 1: code = BFD_RELOC_8_PCREL; break;
11298 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11299 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11300#ifdef BFD64
11301 case 8: code = BFD_RELOC_64_PCREL; break;
11302#endif
93382f6d
AM		 11303 }
11304 }
11305 else
11306 {
11307 switch (fixp->fx_size)
11308 {
11309 default:
b091f402
AM		 11310 as_bad_where (fixp->fx_file, fixp->fx_line,
11311 _("can not do %d byte relocation"),
11312 fixp->fx_size);
93382f6d
AM		 11313 code = BFD_RELOC_32;
11314 break;
11315 case 1: code = BFD_RELOC_8; break;
11316 case 2: code = BFD_RELOC_16; break;
11317 case 4: code = BFD_RELOC_32; break;
937149dd 11318#ifdef BFD64
3e73aa7c 11319 case 8: code = BFD_RELOC_64; break;
937149dd 11320#endif
93382f6d 11321 }
252b5132
RH		 11322 }
11323 break;
11324 }
252b5132 11325
d182319b
JB		 11326 if ((code == BFD_RELOC_32
11327 || code == BFD_RELOC_32_PCREL
11328 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11329 && GOT_symbol
11330 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11331 {
4fa24527 11332 if (!object_64bit)
d6ab8113
JB		 11333 code = BFD_RELOC_386_GOTPC;
11334 else
11335 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11336 }
7b81dfbb
AJ		 11337 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11338 && GOT_symbol
11339 && fixp->fx_addsy == GOT_symbol)
11340 {
11341 code = BFD_RELOC_X86_64_GOTPC64;
11342 }
252b5132 11343
add39d23
TS		 11344 rel = XNEW (arelent);
11345 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11346 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11347
11348 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11349
3e73aa7c
JH		 11350 if (!use_rela_relocations)
11351 {
11352 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11353 vtable entry to be used in the relocation's section offset. */
11354 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11355 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11356#if defined (OBJ_COFF) && defined (TE_PE)
11357 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11358 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11359 else
11360#endif
c6682705 11361 rel->addend = 0;
3e73aa7c
JH		 11362 }
11363 /* Use the rela in 64bit mode. */
252b5132 11364 else
3e73aa7c 11365 {
862be3fb
L		 11366 if (disallow_64bit_reloc)
11367 switch (code)
11368 {
862be3fb
L		 11369 case BFD_RELOC_X86_64_DTPOFF64:
11370 case BFD_RELOC_X86_64_TPOFF64:
11371 case BFD_RELOC_64_PCREL:
11372 case BFD_RELOC_X86_64_GOTOFF64:
11373 case BFD_RELOC_X86_64_GOT64:
11374 case BFD_RELOC_X86_64_GOTPCREL64:
11375 case BFD_RELOC_X86_64_GOTPC64:
11376 case BFD_RELOC_X86_64_GOTPLT64:
11377 case BFD_RELOC_X86_64_PLTOFF64:
11378 as_bad_where (fixp->fx_file, fixp->fx_line,
11379 _("cannot represent relocation type %s in x32 mode"),
11380 bfd_get_reloc_code_name (code));
11381 break;
11382 default:
11383 break;
11384 }
11385
062cd5e7
AS		 11386 if (!fixp->fx_pcrel)
11387 rel->addend = fixp->fx_offset;
11388 else
11389 switch (code)
11390 {
11391 case BFD_RELOC_X86_64_PLT32:
11392 case BFD_RELOC_X86_64_GOT32:
11393 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11394 case BFD_RELOC_X86_64_GOTPCRELX:
11395 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11396 case BFD_RELOC_X86_64_TLSGD:
11397 case BFD_RELOC_X86_64_TLSLD:
11398 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11399 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11400 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11401 rel->addend = fixp->fx_offset - fixp->fx_size;
11402 break;
11403 default:
11404 rel->addend = (section->vma
11405 - fixp->fx_size
11406 + fixp->fx_addnumber
11407 + md_pcrel_from (fixp));
11408 break;
11409 }
3e73aa7c
JH		 11410 }
11411
252b5132
RH		 11412 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11413 if (rel->howto == NULL)
11414 {
11415 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11416 _("cannot represent relocation type %s"),
252b5132
RH		 11417 bfd_get_reloc_code_name (code));
11418 /* Set howto to a garbage value so that we can keep going. */
11419 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11420 gas_assert (rel->howto != NULL);
252b5132
RH		 11421 }
11422
11423 return rel;
11424}
11425
ee86248c 11426#include "tc-i386-intel.c"
54cfded0 11427
a60de03c
JB		 11428void
11429tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11430{
a60de03c
JB		 11431 int saved_naked_reg;
11432 char saved_register_dot;
54cfded0 11433
a60de03c
JB		 11434 saved_naked_reg = allow_naked_reg;
11435 allow_naked_reg = 1;
11436 saved_register_dot = register_chars['.'];
11437 register_chars['.'] = '.';
11438 allow_pseudo_reg = 1;
11439 expression_and_evaluate (exp);
11440 allow_pseudo_reg = 0;
11441 register_chars['.'] = saved_register_dot;
11442 allow_naked_reg = saved_naked_reg;
11443
e96d56a1 11444 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11445 {
a60de03c
JB		 11446 if ((addressT) exp->X_add_number < i386_regtab_size)
11447 {
11448 exp->X_op = O_constant;
11449 exp->X_add_number = i386_regtab[exp->X_add_number]
11450 .dw2_regnum[flag_code >> 1];
11451 }
11452 else
11453 exp->X_op = O_illegal;
54cfded0 11454 }
54cfded0
AM		 11455}
11456
11457void
11458tc_x86_frame_initial_instructions (void)
11459{
a60de03c
JB		 11460 static unsigned int sp_regno[2];
11461
11462 if (!sp_regno[flag_code >> 1])
11463 {
11464 char *saved_input = input_line_pointer;
11465 char sp[][4] = {"esp", "rsp"};
11466 expressionS exp;
a4447b93 11467
a60de03c
JB		 11468 input_line_pointer = sp[flag_code >> 1];
11469 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11470 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11471 sp_regno[flag_code >> 1] = exp.X_add_number;
11472 input_line_pointer = saved_input;
11473 }
a4447b93 11474
61ff971f
L		 11475 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11476 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11477}
d2b2c203 11478
d7921315
L		 11479int
11480x86_dwarf2_addr_size (void)
11481{
11482#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11483 if (x86_elf_abi == X86_64_X32_ABI)
11484 return 4;
11485#endif
11486 return bfd_arch_bits_per_address (stdoutput) / 8;
11487}
11488
d2b2c203
DJ		 11489int
11490i386_elf_section_type (const char *str, size_t len)
11491{
11492 if (flag_code == CODE_64BIT
11493 && len == sizeof ("unwind") - 1
11494 && strncmp (str, "unwind", 6) == 0)
11495 return SHT_X86_64_UNWIND;
11496
11497 return -1;
11498}
bb41ade5 11499
ad5fec3b
EB		 11500#ifdef TE_SOLARIS
11501void
11502i386_solaris_fix_up_eh_frame (segT sec)
11503{
11504 if (flag_code == CODE_64BIT)
11505 elf_section_type (sec) = SHT_X86_64_UNWIND;
11506}
11507#endif
11508
bb41ade5
AM		 11509#ifdef TE_PE
11510void
11511tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11512{
91d6fa6a 11513 expressionS exp;
bb41ade5 11514
91d6fa6a
NC		 11515 exp.X_op = O_secrel;
11516 exp.X_add_symbol = symbol;
11517 exp.X_add_number = 0;
11518 emit_expr (&exp, size);
bb41ade5
AM		 11519}
11520#endif
3b22753a
L		 11521
11522#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11523/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11524
01e1a5bc 11525bfd_vma
6d4af3c2 11526x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11527{
11528 if (flag_code == CODE_64BIT)
11529 {
11530 if (letter == 'l')
11531 return SHF_X86_64_LARGE;
11532
8f3bae45 11533 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11534 }
3b22753a 11535 else
8f3bae45 11536 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11537 return -1;
11538}
11539
01e1a5bc 11540bfd_vma
3b22753a
L		 11541x86_64_section_word (char *str, size_t len)
11542{
8620418b 11543 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11544 return SHF_X86_64_LARGE;
11545
11546 return -1;
11547}
11548
11549static void
11550handle_large_common (int small ATTRIBUTE_UNUSED)
11551{
11552 if (flag_code != CODE_64BIT)
11553 {
11554 s_comm_internal (0, elf_common_parse);
11555 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11556 }
11557 else
11558 {
11559 static segT lbss_section;
11560 asection *saved_com_section_ptr = elf_com_section_ptr;
11561 asection *saved_bss_section = bss_section;
11562
11563 if (lbss_section == NULL)
11564 {
11565 flagword applicable;
11566 segT seg = now_seg;
11567 subsegT subseg = now_subseg;
11568
11569 /* The .lbss section is for local .largecomm symbols. */
11570 lbss_section = subseg_new (".lbss", 0);
11571 applicable = bfd_applicable_section_flags (stdoutput);
11572 bfd_set_section_flags (stdoutput, lbss_section,
11573 applicable & SEC_ALLOC);
11574 seg_info (lbss_section)->bss = 1;
11575
11576 subseg_set (seg, subseg);
11577 }
11578
11579 elf_com_section_ptr = &_bfd_elf_large_com_section;
11580 bss_section = lbss_section;
11581
11582 s_comm_internal (0, elf_common_parse);
11583
11584 elf_com_section_ptr = saved_com_section_ptr;
11585 bss_section = saved_bss_section;
11586 }
11587}
11588#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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