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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
185#endif
252b5132 186
a847613f 187static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 188
c0f3af97
L		 189/* VEX prefix. */
190typedef struct
191{
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes[3];
194 unsigned int length;
195 /* Destination or source register specifier. */
196 const reg_entry *register_specifier;
197} vex_prefix;
198
252b5132 199/* 'md_assemble ()' gathers together information and puts it into a
47926f60 200 i386_insn. */
252b5132 201
520dc8e8
AM		 202union i386_op
203 {
204 expressionS *disps;
205 expressionS *imms;
206 const reg_entry *regs;
207 };
208
a65babc9
L		 209enum i386_error
210 {
86e026a4 211 operand_size_mismatch,
a65babc9
L		 212 operand_type_mismatch,
213 register_type_mismatch,
214 number_of_operands_mismatch,
215 invalid_instruction_suffix,
216 bad_imm4,
217 old_gcc_only,
218 unsupported_with_intel_mnemonic,
219 unsupported_syntax,
220 unsupported
221 };
222
252b5132
RH		 223struct _i386_insn
224 {
47926f60 225 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 226 insn_template tm;
252b5132 227
7d5e4556
L		 228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
252b5132
RH		 230 char suffix;
231
47926f60 232 /* OPERANDS gives the number of given operands. */
252b5132
RH		 233 unsigned int operands;
234
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
47926f60 237 operands. */
252b5132
RH		 238 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
239
240 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 241 use OP[i] for the corresponding operand. */
40fb9820 242 i386_operand_type types[MAX_OPERANDS];
252b5132 243
520dc8e8
AM		 244 /* Displacement expression, immediate expression, or register for each
245 operand. */
246 union i386_op op[MAX_OPERANDS];
252b5132 247
3e73aa7c
JH		 248 /* Flags for operands. */
249 unsigned int flags[MAX_OPERANDS];
250#define Operand_PCrel 1
251
252b5132 252 /* Relocation type for operand */
f86103b7 253 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 254
252b5132
RH		 255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry *base_reg;
258 const reg_entry *index_reg;
259 unsigned int log2_scale_factor;
260
261 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 262 explicit segment overrides are given. */
ce8a8b2f 263 const seg_entry *seg[2];
252b5132
RH		 264
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes;
268 unsigned char prefix[MAX_PREFIXES];
269
270 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 271 addressing modes of this insn are encoded. */
252b5132 272 modrm_byte rm;
3e73aa7c 273 rex_byte rex;
252b5132 274 sib_byte sib;
c0f3af97 275 vex_prefix vex;
b6169b20
L		 276
277 /* Swap operand in encoding. */
4473e004 278 unsigned int swap_operand;
891edac4 279
f8a5c266
L		 280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding;
282
891edac4 283 /* Error message. */
a65babc9 284 enum i386_error error;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60 379/* Current operand we are working on. */
ee86248c 380static int this_operand = -1;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
351f65ca
L		 394/* The ELF ABI to use. */
395enum x86_elf_abi
396{
397 I386_ABI,
398 X86_64_LP64_ABI,
399 X86_64_ILP32_ABI
400};
401
402static enum x86_elf_abi x86_elf_abi = I386_ABI;
403
3e73aa7c 404/* The names used to print error messages. */
b77a7acd 405static const char *flag_code_names[] =
3e73aa7c
JH		 406 {
407 "32",
408 "16",
409 "64"
410 };
252b5132 411
47926f60
KH		 412/* 1 for intel syntax,
413 0 if att syntax. */
414static int intel_syntax = 0;
252b5132 415
1efbbeb4
L		 416/* 1 for intel mnemonic,
417 0 if att mnemonic. */
418static int intel_mnemonic = !SYSV386_COMPAT;
419
5209009a 420/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 421static int old_gcc = OLDGCC_COMPAT;
422
a60de03c
JB		 423/* 1 if pseudo registers are permitted. */
424static int allow_pseudo_reg = 0;
425
47926f60
KH		 426/* 1 if register prefix % not required. */
427static int allow_naked_reg = 0;
252b5132 428
ba104c83 429/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 430static int allow_index_reg = 0;
431
daf50ae7
L		 432static enum
433 {
434 sse_check_none = 0,
435 sse_check_warning,
436 sse_check_error
437 }
438sse_check;
439
2ca3ace5
L		 440/* Register prefix used for error message. */
441static const char *register_prefix = "%";
442
47926f60
KH		 443/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
444 leave, push, and pop instructions so that gcc has the same stack
445 frame as in 32 bit mode. */
446static char stackop_size = '\0';
eecb386c 447
12b55ccc
L		 448/* Non-zero to optimize code alignment. */
449int optimize_align_code = 1;
450
47926f60
KH		 451/* Non-zero to quieten some warnings. */
452static int quiet_warnings = 0;
a38cf1db 453
47926f60
KH		 454/* CPU name. */
455static const char *cpu_arch_name = NULL;
6305a203 456static char *cpu_sub_arch_name = NULL;
a38cf1db 457
47926f60 458/* CPU feature flags. */
40fb9820
L		 459static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
460
ccc9c027
L		 461/* If we have selected a cpu we are generating instructions for. */
462static int cpu_arch_tune_set = 0;
463
9103f4f4 464/* Cpu we are generating instructions for. */
fbf3f584 465enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 466
467/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 468static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 469
ccc9c027 470/* CPU instruction set architecture used. */
fbf3f584 471enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 472
9103f4f4 473/* CPU feature flags of instruction set architecture used. */
fbf3f584 474i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 475
fddf5b5b
AM		 476/* If set, conditional jumps are not automatically promoted to handle
477 larger than a byte offset. */
478static unsigned int no_cond_jump_promotion = 0;
479
c0f3af97
L		 480/* Encode SSE instructions with VEX prefix. */
481static unsigned int sse2avx;
482
539f890d
L		 483/* Encode scalar AVX instructions with specific vector length. */
484static enum
485 {
486 vex128 = 0,
487 vex256
488 } avxscalar;
489
29b0f896 490/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 491static symbolS *GOT_symbol;
29b0f896 492
a4447b93
RH		 493/* The dwarf2 return column, adjusted for 32 or 64 bit. */
494unsigned int x86_dwarf2_return_column;
495
496/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
497int x86_cie_data_alignment;
498
252b5132 499/* Interface to relax_segment.
fddf5b5b
AM		 500 There are 3 major relax states for 386 jump insns because the
501 different types of jumps add different sizes to frags when we're
502 figuring out what sort of jump to choose to reach a given label. */
252b5132 503
47926f60 504/* Types. */
93c2a809
AM		 505#define UNCOND_JUMP 0
506#define COND_JUMP 1
507#define COND_JUMP86 2
fddf5b5b 508
47926f60 509/* Sizes. */
252b5132
RH		 510#define CODE16 1
511#define SMALL 0
29b0f896 512#define SMALL16 (SMALL | CODE16)
252b5132 513#define BIG 2
29b0f896 514#define BIG16 (BIG | CODE16)
252b5132
RH		 515
516#ifndef INLINE
517#ifdef __GNUC__
518#define INLINE __inline__
519#else
520#define INLINE
521#endif
522#endif
523
fddf5b5b
AM		 524#define ENCODE_RELAX_STATE(type, size) \
525 ((relax_substateT) (((type) << 2) | (size)))
526#define TYPE_FROM_RELAX_STATE(s) \
527 ((s) >> 2)
528#define DISP_SIZE_FROM_RELAX_STATE(s) \
529 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 530
531/* This table is used by relax_frag to promote short jumps to long
532 ones where necessary. SMALL (short) jumps may be promoted to BIG
533 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
534 don't allow a short jump in a 32 bit code segment to be promoted to
535 a 16 bit offset jump because it's slower (requires data size
536 prefix), and doesn't work, unless the destination is in the bottom
537 64k of the code segment (The top 16 bits of eip are zeroed). */
538
539const relax_typeS md_relax_table[] =
540{
24eab124
AM		 541 /* The fields are:
542 1) most positive reach of this state,
543 2) most negative reach of this state,
93c2a809 544 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 545 4) which index into the table to try if we can't fit into this one. */
252b5132 546
fddf5b5b 547 /* UNCOND_JUMP states. */
93c2a809
AM		 548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
549 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
550 /* dword jmp adds 4 bytes to frag:
551 0 extra opcode bytes, 4 displacement bytes. */
252b5132 552 {0, 0, 4, 0},
93c2a809
AM		 553 /* word jmp adds 2 byte2 to frag:
554 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 555 {0, 0, 2, 0},
556
93c2a809
AM		 557 /* COND_JUMP states. */
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
560 /* dword conditionals adds 5 bytes to frag:
561 1 extra opcode byte, 4 displacement bytes. */
562 {0, 0, 5, 0},
fddf5b5b 563 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 564 1 extra opcode byte, 2 displacement bytes. */
565 {0, 0, 3, 0},
566
567 /* COND_JUMP86 states. */
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
570 /* dword conditionals adds 5 bytes to frag:
571 1 extra opcode byte, 4 displacement bytes. */
572 {0, 0, 5, 0},
573 /* word conditionals add 4 bytes to frag:
574 1 displacement byte and a 3 byte long branch insn. */
575 {0, 0, 4, 0}
252b5132
RH		 576};
577
9103f4f4
L		 578static const arch_entry cpu_arch[] =
579{
89507696
JB		 580 /* Do not replace the first two entries - i386_target_format()
581 relies on them being there in this order. */
8a2c8fef 582 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 583 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 584 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 585 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 586 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 587 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 588 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 589 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 590 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 591 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 592 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 593 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 594 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 595 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 596 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 597 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 598 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 599 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 600 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 601 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 602 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 603 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 605 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 607 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 609 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 611 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 613 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 615 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 617 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 619 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 621 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 623 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 625 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 627 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 629 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 631 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 633 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 635 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 636 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 637 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 639 CPU_AMDFAM10_FLAGS, 0, 0 },
68339fdf 640 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
22109423 641 CPU_BDVER1_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 643 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 644 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 645 CPU_287_FLAGS, 0, 0 },
8a2c8fef 646 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 647 CPU_387_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 649 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 650 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 651 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 652 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 653 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 654 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 655 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 657 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 659 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 660 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 661 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 662 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 663 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 664 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 665 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 666 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 667 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 668 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 669 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 670 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 671 CPU_AVX_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 673 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 674 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 675 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 677 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 678 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 679 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 680 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 681 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 683 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 684 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 685 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 687 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 688 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 689 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 690 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 691 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 692 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 693 CPU_F16C_FLAGS, 0, 0 },
8a2c8fef 694 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 695 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 696 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 697 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 698 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 699 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 700 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 701 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 702 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 703 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 704 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 705 CPU_EPT_FLAGS, 0, 0 },
8a2c8fef 706 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 707 CPU_CLFLUSH_FLAGS, 0, 0 },
708 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
709 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 710 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 711 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 713 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 715 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 717 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 718 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 719 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 721 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 722 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 723 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 725 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 727 CPU_ABM_FLAGS, 0, 0 },
e413e4e9
AM		 728};
729
704209c0 730#ifdef I386COFF
a6c24e68
NC		 731/* Like s_lcomm_internal in gas/read.c but the alignment string
732 is allowed to be optional. */
733
734static symbolS *
735pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
736{
737 addressT align = 0;
738
739 SKIP_WHITESPACE ();
740
7ab9ffdd 741 if (needs_align
a6c24e68
NC		 742 && *input_line_pointer == ',')
743 {
744 align = parse_align (needs_align - 1);
7ab9ffdd 745
a6c24e68
NC		 746 if (align == (addressT) -1)
747 return NULL;
748 }
749 else
750 {
751 if (size >= 8)
752 align = 3;
753 else if (size >= 4)
754 align = 2;
755 else if (size >= 2)
756 align = 1;
757 else
758 align = 0;
759 }
760
761 bss_alloc (symbolP, size, align);
762 return symbolP;
763}
764
704209c0 765static void
a6c24e68
NC		 766pe_lcomm (int needs_align)
767{
768 s_comm_internal (needs_align * 2, pe_lcomm_internal);
769}
704209c0 770#endif
a6c24e68 771
29b0f896
AM		 772const pseudo_typeS md_pseudo_table[] =
773{
774#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
775 {"align", s_align_bytes, 0},
776#else
777 {"align", s_align_ptwo, 0},
778#endif
779 {"arch", set_cpu_arch, 0},
780#ifndef I386COFF
781 {"bss", s_bss, 0},
a6c24e68
NC		 782#else
783 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 784#endif
785 {"ffloat", float_cons, 'f'},
786 {"dfloat", float_cons, 'd'},
787 {"tfloat", float_cons, 'x'},
788 {"value", cons, 2},
d182319b 789 {"slong", signed_cons, 4},
29b0f896
AM		 790 {"noopt", s_ignore, 0},
791 {"optim", s_ignore, 0},
792 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
793 {"code16", set_code_flag, CODE_16BIT},
794 {"code32", set_code_flag, CODE_32BIT},
795 {"code64", set_code_flag, CODE_64BIT},
796 {"intel_syntax", set_intel_syntax, 1},
797 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 798 {"intel_mnemonic", set_intel_mnemonic, 1},
799 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 800 {"allow_index_reg", set_allow_index_reg, 1},
801 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 802 {"sse_check", set_sse_check, 0},
3b22753a
L		 803#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
804 {"largecomm", handle_large_common, 0},
07a53e5c 805#else
e3bb37b5 806 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 807 {"loc", dwarf2_directive_loc, 0},
808 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 809#endif
6482c264
NC		 810#ifdef TE_PE
811 {"secrel32", pe_directive_secrel, 0},
812#endif
29b0f896
AM		 813 {0, 0, 0}
814};
815
816/* For interface with expression (). */
817extern char *input_line_pointer;
818
819/* Hash table for instruction mnemonic lookup. */
820static struct hash_control *op_hash;
821
822/* Hash table for register lookup. */
823static struct hash_control *reg_hash;
824\f
252b5132 825void
e3bb37b5 826i386_align_code (fragS *fragP, int count)
252b5132 827{
ce8a8b2f
AM		 828 /* Various efficient no-op patterns for aligning code labels.
829 Note: Don't try to assemble the instructions in the comments.
830 0L and 0w are not legal. */
252b5132
RH		 831 static const char f32_1[] =
832 {0x90}; /* nop */
833 static const char f32_2[] =
ccc9c027 834 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 835 static const char f32_3[] =
836 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
837 static const char f32_4[] =
838 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
839 static const char f32_5[] =
840 {0x90, /* nop */
841 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
842 static const char f32_6[] =
843 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
844 static const char f32_7[] =
845 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
846 static const char f32_8[] =
847 {0x90, /* nop */
848 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
849 static const char f32_9[] =
850 {0x89,0xf6, /* movl %esi,%esi */
851 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
852 static const char f32_10[] =
853 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
854 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
855 static const char f32_11[] =
856 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
857 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
858 static const char f32_12[] =
859 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
860 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
861 static const char f32_13[] =
862 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
863 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
864 static const char f32_14[] =
865 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
866 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 867 static const char f16_3[] =
868 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 869 static const char f16_4[] =
870 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
871 static const char f16_5[] =
872 {0x90, /* nop */
873 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
874 static const char f16_6[] =
875 {0x89,0xf6, /* mov %si,%si */
876 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
877 static const char f16_7[] =
878 {0x8d,0x74,0x00, /* lea 0(%si),%si */
879 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
880 static const char f16_8[] =
881 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
882 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 883 static const char jump_31[] =
884 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
885 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
886 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
887 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 888 static const char *const f32_patt[] = {
889 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 890 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 891 };
892 static const char *const f16_patt[] = {
76bc74dc 893 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 894 };
ccc9c027
L		 895 /* nopl (%[re]ax) */
896 static const char alt_3[] =
897 {0x0f,0x1f,0x00};
898 /* nopl 0(%[re]ax) */
899 static const char alt_4[] =
900 {0x0f,0x1f,0x40,0x00};
901 /* nopl 0(%[re]ax,%[re]ax,1) */
902 static const char alt_5[] =
903 {0x0f,0x1f,0x44,0x00,0x00};
904 /* nopw 0(%[re]ax,%[re]ax,1) */
905 static const char alt_6[] =
906 {0x66,0x0f,0x1f,0x44,0x00,0x00};
907 /* nopl 0L(%[re]ax) */
908 static const char alt_7[] =
909 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
910 /* nopl 0L(%[re]ax,%[re]ax,1) */
911 static const char alt_8[] =
912 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopw 0L(%[re]ax,%[re]ax,1) */
914 static const char alt_9[] =
915 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
916 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
917 static const char alt_10[] =
918 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
919 /* data16
920 nopw %cs:0L(%[re]ax,%[re]ax,1) */
921 static const char alt_long_11[] =
922 {0x66,
923 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
924 /* data16
925 data16
926 nopw %cs:0L(%[re]ax,%[re]ax,1) */
927 static const char alt_long_12[] =
928 {0x66,
929 0x66,
930 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 /* data16
932 data16
933 data16
934 nopw %cs:0L(%[re]ax,%[re]ax,1) */
935 static const char alt_long_13[] =
936 {0x66,
937 0x66,
938 0x66,
939 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
940 /* data16
941 data16
942 data16
943 data16
944 nopw %cs:0L(%[re]ax,%[re]ax,1) */
945 static const char alt_long_14[] =
946 {0x66,
947 0x66,
948 0x66,
949 0x66,
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
951 /* data16
952 data16
953 data16
954 data16
955 data16
956 nopw %cs:0L(%[re]ax,%[re]ax,1) */
957 static const char alt_long_15[] =
958 {0x66,
959 0x66,
960 0x66,
961 0x66,
962 0x66,
963 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
964 /* nopl 0(%[re]ax,%[re]ax,1)
965 nopw 0(%[re]ax,%[re]ax,1) */
966 static const char alt_short_11[] =
967 {0x0f,0x1f,0x44,0x00,0x00,
968 0x66,0x0f,0x1f,0x44,0x00,0x00};
969 /* nopw 0(%[re]ax,%[re]ax,1)
970 nopw 0(%[re]ax,%[re]ax,1) */
971 static const char alt_short_12[] =
972 {0x66,0x0f,0x1f,0x44,0x00,0x00,
973 0x66,0x0f,0x1f,0x44,0x00,0x00};
974 /* nopw 0(%[re]ax,%[re]ax,1)
975 nopl 0L(%[re]ax) */
976 static const char alt_short_13[] =
977 {0x66,0x0f,0x1f,0x44,0x00,0x00,
978 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
979 /* nopl 0L(%[re]ax)
980 nopl 0L(%[re]ax) */
981 static const char alt_short_14[] =
982 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
983 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
984 /* nopl 0L(%[re]ax)
985 nopl 0L(%[re]ax,%[re]ax,1) */
986 static const char alt_short_15[] =
987 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
988 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
989 static const char *const alt_short_patt[] = {
990 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
991 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
992 alt_short_14, alt_short_15
993 };
994 static const char *const alt_long_patt[] = {
995 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
996 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
997 alt_long_14, alt_long_15
998 };
252b5132 999
76bc74dc
L		 1000 /* Only align for at least a positive non-zero boundary. */
1001 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1002 return;
3e73aa7c 1003
ccc9c027
L		 1004 /* We need to decide which NOP sequence to use for 32bit and
1005 64bit. When -mtune= is used:
4eed87de 1006
76bc74dc
L		 1007 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1008 PROCESSOR_GENERIC32, f32_patt will be used.
1009 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1010 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1011 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1012 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 1013 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 1014 will be used.
ccc9c027 1015
76bc74dc 1016 When -mtune= isn't used, alt_long_patt will be used if
22109423 1017 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1018 be used.
ccc9c027
L		 1019
1020 When -march= or .arch is used, we can't use anything beyond
1021 cpu_arch_isa_flags. */
1022
1023 if (flag_code == CODE_16BIT)
1024 {
ccc9c027 1025 if (count > 8)
33fef721 1026 {
76bc74dc
L		 1027 memcpy (fragP->fr_literal + fragP->fr_fix,
1028 jump_31, count);
1029 /* Adjust jump offset. */
1030 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1031 }
76bc74dc
L		 1032 else
1033 memcpy (fragP->fr_literal + fragP->fr_fix,
1034 f16_patt[count - 1], count);
252b5132 1035 }
33fef721 1036 else
ccc9c027
L		 1037 {
1038 const char *const *patt = NULL;
1039
fbf3f584 1040 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1041 {
1042 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1043 switch (cpu_arch_tune)
1044 {
1045 case PROCESSOR_UNKNOWN:
1046 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1047 optimize with nops. */
1048 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1049 patt = alt_long_patt;
ccc9c027
L		 1050 else
1051 patt = f32_patt;
1052 break;
ccc9c027
L		 1053 case PROCESSOR_PENTIUMPRO:
1054 case PROCESSOR_PENTIUM4:
1055 case PROCESSOR_NOCONA:
ef05d495 1056 case PROCESSOR_CORE:
76bc74dc 1057 case PROCESSOR_CORE2:
bd5295b2 1058 case PROCESSOR_COREI7:
3632d14b 1059 case PROCESSOR_L1OM:
76bc74dc
L		 1060 case PROCESSOR_GENERIC64:
1061 patt = alt_long_patt;
1062 break;
ccc9c027
L		 1063 case PROCESSOR_K6:
1064 case PROCESSOR_ATHLON:
1065 case PROCESSOR_K8:
4eed87de 1066 case PROCESSOR_AMDFAM10:
68339fdf 1067 case PROCESSOR_BDVER1:
ccc9c027
L		 1068 patt = alt_short_patt;
1069 break;
76bc74dc 1070 case PROCESSOR_I386:
ccc9c027
L		 1071 case PROCESSOR_I486:
1072 case PROCESSOR_PENTIUM:
1073 case PROCESSOR_GENERIC32:
1074 patt = f32_patt;
1075 break;
4eed87de 1076 }
ccc9c027
L		 1077 }
1078 else
1079 {
fbf3f584 1080 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1081 {
1082 case PROCESSOR_UNKNOWN:
e6a14101 1083 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1084 PROCESSOR_UNKNOWN. */
1085 abort ();
1086 break;
1087
76bc74dc 1088 case PROCESSOR_I386:
ccc9c027
L		 1089 case PROCESSOR_I486:
1090 case PROCESSOR_PENTIUM:
ccc9c027
L		 1091 case PROCESSOR_K6:
1092 case PROCESSOR_ATHLON:
1093 case PROCESSOR_K8:
4eed87de 1094 case PROCESSOR_AMDFAM10:
68339fdf 1095 case PROCESSOR_BDVER1:
ccc9c027
L		 1096 case PROCESSOR_GENERIC32:
1097 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1098 with nops. */
1099 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1100 patt = alt_short_patt;
1101 else
1102 patt = f32_patt;
1103 break;
76bc74dc
L		 1104 case PROCESSOR_PENTIUMPRO:
1105 case PROCESSOR_PENTIUM4:
1106 case PROCESSOR_NOCONA:
1107 case PROCESSOR_CORE:
ef05d495 1108 case PROCESSOR_CORE2:
bd5295b2 1109 case PROCESSOR_COREI7:
3632d14b 1110 case PROCESSOR_L1OM:
22109423 1111 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1112 patt = alt_long_patt;
1113 else
1114 patt = f32_patt;
1115 break;
1116 case PROCESSOR_GENERIC64:
76bc74dc 1117 patt = alt_long_patt;
ccc9c027 1118 break;
4eed87de 1119 }
ccc9c027
L		 1120 }
1121
76bc74dc
L		 1122 if (patt == f32_patt)
1123 {
1124 /* If the padding is less than 15 bytes, we use the normal
1125 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1126 its offset. */
1127 int limit;
76ba9986 1128
711eedef
L		 1129 /* For 64bit, the limit is 3 bytes. */
1130 if (flag_code == CODE_64BIT
1131 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1132 limit = 3;
1133 else
1134 limit = 15;
1135 if (count < limit)
76bc74dc
L		 1136 memcpy (fragP->fr_literal + fragP->fr_fix,
1137 patt[count - 1], count);
1138 else
1139 {
1140 memcpy (fragP->fr_literal + fragP->fr_fix,
1141 jump_31, count);
1142 /* Adjust jump offset. */
1143 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1144 }
1145 }
1146 else
1147 {
1148 /* Maximum length of an instruction is 15 byte. If the
1149 padding is greater than 15 bytes and we don't use jump,
1150 we have to break it into smaller pieces. */
1151 int padding = count;
1152 while (padding > 15)
1153 {
1154 padding -= 15;
1155 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1156 patt [14], 15);
1157 }
1158
1159 if (padding)
1160 memcpy (fragP->fr_literal + fragP->fr_fix,
1161 patt [padding - 1], padding);
1162 }
ccc9c027 1163 }
33fef721 1164 fragP->fr_var = count;
252b5132
RH		 1165}
1166
c6fb90c8 1167static INLINE int
0dfbf9d7 1168operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1169{
0dfbf9d7 1170 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1171 {
1172 case 3:
0dfbf9d7 1173 if (x->array[2])
c6fb90c8
L		 1174 return 0;
1175 case 2:
0dfbf9d7 1176 if (x->array[1])
c6fb90c8
L		 1177 return 0;
1178 case 1:
0dfbf9d7 1179 return !x->array[0];
c6fb90c8
L		 1180 default:
1181 abort ();
1182 }
40fb9820
L		 1183}
1184
c6fb90c8 1185static INLINE void
0dfbf9d7 1186operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1187{
0dfbf9d7 1188 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1189 {
1190 case 3:
0dfbf9d7 1191 x->array[2] = v;
c6fb90c8 1192 case 2:
0dfbf9d7 1193 x->array[1] = v;
c6fb90c8 1194 case 1:
0dfbf9d7 1195 x->array[0] = v;
c6fb90c8
L		 1196 break;
1197 default:
1198 abort ();
1199 }
1200}
40fb9820 1201
c6fb90c8 1202static INLINE int
0dfbf9d7
L		 1203operand_type_equal (const union i386_operand_type *x,
1204 const union i386_operand_type *y)
c6fb90c8 1205{
0dfbf9d7 1206 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1207 {
1208 case 3:
0dfbf9d7 1209 if (x->array[2] != y->array[2])
c6fb90c8
L		 1210 return 0;
1211 case 2:
0dfbf9d7 1212 if (x->array[1] != y->array[1])
c6fb90c8
L		 1213 return 0;
1214 case 1:
0dfbf9d7 1215 return x->array[0] == y->array[0];
c6fb90c8
L		 1216 break;
1217 default:
1218 abort ();
1219 }
1220}
40fb9820 1221
0dfbf9d7
L		 1222static INLINE int
1223cpu_flags_all_zero (const union i386_cpu_flags *x)
1224{
1225 switch (ARRAY_SIZE(x->array))
1226 {
1227 case 3:
1228 if (x->array[2])
1229 return 0;
1230 case 2:
1231 if (x->array[1])
1232 return 0;
1233 case 1:
1234 return !x->array[0];
1235 default:
1236 abort ();
1237 }
1238}
1239
1240static INLINE void
1241cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1242{
1243 switch (ARRAY_SIZE(x->array))
1244 {
1245 case 3:
1246 x->array[2] = v;
1247 case 2:
1248 x->array[1] = v;
1249 case 1:
1250 x->array[0] = v;
1251 break;
1252 default:
1253 abort ();
1254 }
1255}
1256
1257static INLINE int
1258cpu_flags_equal (const union i386_cpu_flags *x,
1259 const union i386_cpu_flags *y)
1260{
1261 switch (ARRAY_SIZE(x->array))
1262 {
1263 case 3:
1264 if (x->array[2] != y->array[2])
1265 return 0;
1266 case 2:
1267 if (x->array[1] != y->array[1])
1268 return 0;
1269 case 1:
1270 return x->array[0] == y->array[0];
1271 break;
1272 default:
1273 abort ();
1274 }
1275}
c6fb90c8
L		 1276
1277static INLINE int
1278cpu_flags_check_cpu64 (i386_cpu_flags f)
1279{
1280 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1281 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1282}
1283
c6fb90c8
L		 1284static INLINE i386_cpu_flags
1285cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1286{
c6fb90c8
L		 1287 switch (ARRAY_SIZE (x.array))
1288 {
1289 case 3:
1290 x.array [2] &= y.array [2];
1291 case 2:
1292 x.array [1] &= y.array [1];
1293 case 1:
1294 x.array [0] &= y.array [0];
1295 break;
1296 default:
1297 abort ();
1298 }
1299 return x;
1300}
40fb9820 1301
c6fb90c8
L		 1302static INLINE i386_cpu_flags
1303cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1304{
c6fb90c8 1305 switch (ARRAY_SIZE (x.array))
40fb9820 1306 {
c6fb90c8
L		 1307 case 3:
1308 x.array [2] |= y.array [2];
1309 case 2:
1310 x.array [1] |= y.array [1];
1311 case 1:
1312 x.array [0] |= y.array [0];
40fb9820
L		 1313 break;
1314 default:
1315 abort ();
1316 }
40fb9820
L		 1317 return x;
1318}
1319
309d3373
JB		 1320static INLINE i386_cpu_flags
1321cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1322{
1323 switch (ARRAY_SIZE (x.array))
1324 {
1325 case 3:
1326 x.array [2] &= ~y.array [2];
1327 case 2:
1328 x.array [1] &= ~y.array [1];
1329 case 1:
1330 x.array [0] &= ~y.array [0];
1331 break;
1332 default:
1333 abort ();
1334 }
1335 return x;
1336}
1337
c0f3af97
L		 1338#define CPU_FLAGS_ARCH_MATCH 0x1
1339#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1340#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1341#define CPU_FLAGS_PCLMUL_MATCH 0x8
1342#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1343
a5ff0eb2 1344#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1345 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1346 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1347#define CPU_FLAGS_PERFECT_MATCH \
1348 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1349
1350/* Return CPU flags match bits. */
3629bb00 1351
40fb9820 1352static int
d3ce72d0 1353cpu_flags_match (const insn_template *t)
40fb9820 1354{
c0f3af97
L		 1355 i386_cpu_flags x = t->cpu_flags;
1356 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1357
1358 x.bitfield.cpu64 = 0;
1359 x.bitfield.cpuno64 = 0;
1360
0dfbf9d7 1361 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1362 {
1363 /* This instruction is available on all archs. */
1364 match |= CPU_FLAGS_32BIT_MATCH;
1365 }
3629bb00
L		 1366 else
1367 {
c0f3af97 1368 /* This instruction is available only on some archs. */
3629bb00
L		 1369 i386_cpu_flags cpu = cpu_arch_flags;
1370
1371 cpu.bitfield.cpu64 = 0;
1372 cpu.bitfield.cpuno64 = 0;
1373 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1374 if (!cpu_flags_all_zero (&cpu))
1375 {
a5ff0eb2
L		 1376 if (x.bitfield.cpuavx)
1377 {
ce2f5b3c 1378 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1379 if (cpu.bitfield.cpuavx)
1380 {
1381 /* Check SSE2AVX. */
1382 if (!t->opcode_modifier.sse2avx|| sse2avx)
1383 {
1384 match |= (CPU_FLAGS_ARCH_MATCH
1385 | CPU_FLAGS_AVX_MATCH);
1386 /* Check AES. */
1387 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1388 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1389 /* Check PCLMUL. */
1390 if (!x.bitfield.cpupclmul
1391 || cpu.bitfield.cpupclmul)
1392 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1393 }
1394 }
1395 else
1396 match |= CPU_FLAGS_ARCH_MATCH;
1397 }
1398 else
c0f3af97
L		 1399 match |= CPU_FLAGS_32BIT_MATCH;
1400 }
3629bb00 1401 }
c0f3af97 1402 return match;
40fb9820
L		 1403}
1404
c6fb90c8
L		 1405static INLINE i386_operand_type
1406operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1407{
c6fb90c8
L		 1408 switch (ARRAY_SIZE (x.array))
1409 {
1410 case 3:
1411 x.array [2] &= y.array [2];
1412 case 2:
1413 x.array [1] &= y.array [1];
1414 case 1:
1415 x.array [0] &= y.array [0];
1416 break;
1417 default:
1418 abort ();
1419 }
1420 return x;
40fb9820
L		 1421}
1422
c6fb90c8
L		 1423static INLINE i386_operand_type
1424operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1425{
c6fb90c8 1426 switch (ARRAY_SIZE (x.array))
40fb9820 1427 {
c6fb90c8
L		 1428 case 3:
1429 x.array [2] |= y.array [2];
1430 case 2:
1431 x.array [1] |= y.array [1];
1432 case 1:
1433 x.array [0] |= y.array [0];
40fb9820
L		 1434 break;
1435 default:
1436 abort ();
1437 }
c6fb90c8
L		 1438 return x;
1439}
40fb9820 1440
c6fb90c8
L		 1441static INLINE i386_operand_type
1442operand_type_xor (i386_operand_type x, i386_operand_type y)
1443{
1444 switch (ARRAY_SIZE (x.array))
1445 {
1446 case 3:
1447 x.array [2] ^= y.array [2];
1448 case 2:
1449 x.array [1] ^= y.array [1];
1450 case 1:
1451 x.array [0] ^= y.array [0];
1452 break;
1453 default:
1454 abort ();
1455 }
40fb9820
L		 1456 return x;
1457}
1458
1459static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1460static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1461static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1462static const i386_operand_type inoutportreg
1463 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1464static const i386_operand_type reg16_inoutportreg
1465 = OPERAND_TYPE_REG16_INOUTPORTREG;
1466static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1467static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1468static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1469static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1470static const i386_operand_type anydisp
1471 = OPERAND_TYPE_ANYDISP;
40fb9820 1472static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1473static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1474static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1475static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1476static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1477static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1478static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1479static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1480static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1481static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1482static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1483static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1484
1485enum operand_type
1486{
1487 reg,
40fb9820
L		 1488 imm,
1489 disp,
1490 anymem
1491};
1492
c6fb90c8 1493static INLINE int
40fb9820
L		 1494operand_type_check (i386_operand_type t, enum operand_type c)
1495{
1496 switch (c)
1497 {
1498 case reg:
1499 return (t.bitfield.reg8
1500 || t.bitfield.reg16
1501 || t.bitfield.reg32
1502 || t.bitfield.reg64);
1503
40fb9820
L		 1504 case imm:
1505 return (t.bitfield.imm8
1506 || t.bitfield.imm8s
1507 || t.bitfield.imm16
1508 || t.bitfield.imm32
1509 || t.bitfield.imm32s
1510 || t.bitfield.imm64);
1511
1512 case disp:
1513 return (t.bitfield.disp8
1514 || t.bitfield.disp16
1515 || t.bitfield.disp32
1516 || t.bitfield.disp32s
1517 || t.bitfield.disp64);
1518
1519 case anymem:
1520 return (t.bitfield.disp8
1521 || t.bitfield.disp16
1522 || t.bitfield.disp32
1523 || t.bitfield.disp32s
1524 || t.bitfield.disp64
1525 || t.bitfield.baseindex);
1526
1527 default:
1528 abort ();
1529 }
2cfe26b6
AM		 1530
1531 return 0;
40fb9820
L		 1532}
1533
5c07affc
L		 1534/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1535 operand J for instruction template T. */
1536
1537static INLINE int
d3ce72d0 1538match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1539{
1540 return !((i.types[j].bitfield.byte
1541 && !t->operand_types[j].bitfield.byte)
1542 || (i.types[j].bitfield.word
1543 && !t->operand_types[j].bitfield.word)
1544 || (i.types[j].bitfield.dword
1545 && !t->operand_types[j].bitfield.dword)
1546 || (i.types[j].bitfield.qword
1547 && !t->operand_types[j].bitfield.qword));
1548}
1549
1550/* Return 1 if there is no conflict in any size on operand J for
1551 instruction template T. */
1552
1553static INLINE int
d3ce72d0 1554match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1555{
1556 return (match_reg_size (t, j)
1557 && !((i.types[j].bitfield.unspecified
1558 && !t->operand_types[j].bitfield.unspecified)
1559 || (i.types[j].bitfield.fword
1560 && !t->operand_types[j].bitfield.fword)
1561 || (i.types[j].bitfield.tbyte
1562 && !t->operand_types[j].bitfield.tbyte)
1563 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1564 && !t->operand_types[j].bitfield.xmmword)
1565 || (i.types[j].bitfield.ymmword
1566 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1567}
1568
1569/* Return 1 if there is no size conflict on any operands for
1570 instruction template T. */
1571
1572static INLINE int
d3ce72d0 1573operand_size_match (const insn_template *t)
5c07affc
L		 1574{
1575 unsigned int j;
1576 int match = 1;
1577
1578 /* Don't check jump instructions. */
1579 if (t->opcode_modifier.jump
1580 || t->opcode_modifier.jumpbyte
1581 || t->opcode_modifier.jumpdword
1582 || t->opcode_modifier.jumpintersegment)
1583 return match;
1584
1585 /* Check memory and accumulator operand size. */
1586 for (j = 0; j < i.operands; j++)
1587 {
1588 if (t->operand_types[j].bitfield.anysize)
1589 continue;
1590
1591 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1592 {
1593 match = 0;
1594 break;
1595 }
1596
1597 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1598 {
1599 match = 0;
1600 break;
1601 }
1602 }
1603
891edac4 1604 if (match)
5c07affc 1605 return match;
891edac4
L		 1606 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1607 {
1608mismatch:
86e026a4 1609 i.error = operand_size_mismatch;
891edac4
L		 1610 return 0;
1611 }
5c07affc
L		 1612
1613 /* Check reverse. */
9c2799c2 1614 gas_assert (i.operands == 2);
5c07affc
L		 1615
1616 match = 1;
1617 for (j = 0; j < 2; j++)
1618 {
1619 if (t->operand_types[j].bitfield.acc
1620 && !match_reg_size (t, j ? 0 : 1))
891edac4 1621 goto mismatch;
5c07affc
L		 1622
1623 if (i.types[j].bitfield.mem
1624 && !match_mem_size (t, j ? 0 : 1))
891edac4 1625 goto mismatch;
5c07affc
L		 1626 }
1627
1628 return match;
1629}
1630
c6fb90c8 1631static INLINE int
40fb9820
L		 1632operand_type_match (i386_operand_type overlap,
1633 i386_operand_type given)
1634{
1635 i386_operand_type temp = overlap;
1636
1637 temp.bitfield.jumpabsolute = 0;
7d5e4556 1638 temp.bitfield.unspecified = 0;
5c07affc
L		 1639 temp.bitfield.byte = 0;
1640 temp.bitfield.word = 0;
1641 temp.bitfield.dword = 0;
1642 temp.bitfield.fword = 0;
1643 temp.bitfield.qword = 0;
1644 temp.bitfield.tbyte = 0;
1645 temp.bitfield.xmmword = 0;
c0f3af97 1646 temp.bitfield.ymmword = 0;
0dfbf9d7 1647 if (operand_type_all_zero (&temp))
891edac4 1648 goto mismatch;
40fb9820 1649
891edac4
L		 1650 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1651 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1652 return 1;
1653
1654mismatch:
a65babc9 1655 i.error = operand_type_mismatch;
891edac4 1656 return 0;
40fb9820
L		 1657}
1658
7d5e4556 1659/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1660 unless the expected operand type register overlap is null.
1661 Note that Acc in a template matches every size of reg. */
1662
c6fb90c8 1663static INLINE int
40fb9820
L		 1664operand_type_register_match (i386_operand_type m0,
1665 i386_operand_type g0,
1666 i386_operand_type t0,
1667 i386_operand_type m1,
1668 i386_operand_type g1,
1669 i386_operand_type t1)
1670{
1671 if (!operand_type_check (g0, reg))
1672 return 1;
1673
1674 if (!operand_type_check (g1, reg))
1675 return 1;
1676
1677 if (g0.bitfield.reg8 == g1.bitfield.reg8
1678 && g0.bitfield.reg16 == g1.bitfield.reg16
1679 && g0.bitfield.reg32 == g1.bitfield.reg32
1680 && g0.bitfield.reg64 == g1.bitfield.reg64)
1681 return 1;
1682
1683 if (m0.bitfield.acc)
1684 {
1685 t0.bitfield.reg8 = 1;
1686 t0.bitfield.reg16 = 1;
1687 t0.bitfield.reg32 = 1;
1688 t0.bitfield.reg64 = 1;
1689 }
1690
1691 if (m1.bitfield.acc)
1692 {
1693 t1.bitfield.reg8 = 1;
1694 t1.bitfield.reg16 = 1;
1695 t1.bitfield.reg32 = 1;
1696 t1.bitfield.reg64 = 1;
1697 }
1698
891edac4
L		 1699 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1700 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1701 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1702 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1703 return 1;
1704
a65babc9 1705 i.error = register_type_mismatch;
891edac4
L		 1706
1707 return 0;
40fb9820
L		 1708}
1709
252b5132 1710static INLINE unsigned int
40fb9820 1711mode_from_disp_size (i386_operand_type t)
252b5132 1712{
40fb9820
L		 1713 if (t.bitfield.disp8)
1714 return 1;
1715 else if (t.bitfield.disp16
1716 || t.bitfield.disp32
1717 || t.bitfield.disp32s)
1718 return 2;
1719 else
1720 return 0;
252b5132
RH		 1721}
1722
1723static INLINE int
e3bb37b5 1724fits_in_signed_byte (offsetT num)
252b5132
RH		 1725{
1726 return (num >= -128) && (num <= 127);
47926f60 1727}
252b5132
RH		 1728
1729static INLINE int
e3bb37b5 1730fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1731{
1732 return (num & 0xff) == num;
47926f60 1733}
252b5132
RH		 1734
1735static INLINE int
e3bb37b5 1736fits_in_unsigned_word (offsetT num)
252b5132
RH		 1737{
1738 return (num & 0xffff) == num;
47926f60 1739}
252b5132
RH		 1740
1741static INLINE int
e3bb37b5 1742fits_in_signed_word (offsetT num)
252b5132
RH		 1743{
1744 return (-32768 <= num) && (num <= 32767);
47926f60 1745}
2a962e6d 1746
3e73aa7c 1747static INLINE int
e3bb37b5 1748fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1749{
1750#ifndef BFD64
1751 return 1;
1752#else
1753 return (!(((offsetT) -1 << 31) & num)
1754 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1755#endif
1756} /* fits_in_signed_long() */
2a962e6d 1757
3e73aa7c 1758static INLINE int
e3bb37b5 1759fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1760{
1761#ifndef BFD64
1762 return 1;
1763#else
1764 return (num & (((offsetT) 2 << 31) - 1)) == num;
1765#endif
1766} /* fits_in_unsigned_long() */
252b5132 1767
a683cc34
SP		 1768static INLINE int
1769fits_in_imm4 (offsetT num)
1770{
1771 return (num & 0xf) == num;
1772}
1773
40fb9820 1774static i386_operand_type
e3bb37b5 1775smallest_imm_type (offsetT num)
252b5132 1776{
40fb9820 1777 i386_operand_type t;
7ab9ffdd 1778
0dfbf9d7 1779 operand_type_set (&t, 0);
40fb9820
L		 1780 t.bitfield.imm64 = 1;
1781
1782 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1783 {
1784 /* This code is disabled on the 486 because all the Imm1 forms
1785 in the opcode table are slower on the i486. They're the
1786 versions with the implicitly specified single-position
1787 displacement, which has another syntax if you really want to
1788 use that form. */
40fb9820
L		 1789 t.bitfield.imm1 = 1;
1790 t.bitfield.imm8 = 1;
1791 t.bitfield.imm8s = 1;
1792 t.bitfield.imm16 = 1;
1793 t.bitfield.imm32 = 1;
1794 t.bitfield.imm32s = 1;
1795 }
1796 else if (fits_in_signed_byte (num))
1797 {
1798 t.bitfield.imm8 = 1;
1799 t.bitfield.imm8s = 1;
1800 t.bitfield.imm16 = 1;
1801 t.bitfield.imm32 = 1;
1802 t.bitfield.imm32s = 1;
1803 }
1804 else if (fits_in_unsigned_byte (num))
1805 {
1806 t.bitfield.imm8 = 1;
1807 t.bitfield.imm16 = 1;
1808 t.bitfield.imm32 = 1;
1809 t.bitfield.imm32s = 1;
1810 }
1811 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1812 {
1813 t.bitfield.imm16 = 1;
1814 t.bitfield.imm32 = 1;
1815 t.bitfield.imm32s = 1;
1816 }
1817 else if (fits_in_signed_long (num))
1818 {
1819 t.bitfield.imm32 = 1;
1820 t.bitfield.imm32s = 1;
1821 }
1822 else if (fits_in_unsigned_long (num))
1823 t.bitfield.imm32 = 1;
1824
1825 return t;
47926f60 1826}
252b5132 1827
847f7ad4 1828static offsetT
e3bb37b5 1829offset_in_range (offsetT val, int size)
847f7ad4 1830{
508866be 1831 addressT mask;
ba2adb93 1832
847f7ad4
AM		 1833 switch (size)
1834 {
508866be
L		 1835 case 1: mask = ((addressT) 1 << 8) - 1; break;
1836 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1837 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1838#ifdef BFD64
1839 case 8: mask = ((addressT) 2 << 63) - 1; break;
1840#endif
47926f60 1841 default: abort ();
847f7ad4
AM		 1842 }
1843
9de868bf
L		 1844#ifdef BFD64
1845 /* If BFD64, sign extend val for 32bit address mode. */
1846 if (flag_code != CODE_64BIT
1847 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1848 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1849 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1850#endif
ba2adb93 1851
47926f60 1852 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1853 {
1854 char buf1[40], buf2[40];
1855
1856 sprint_value (buf1, val);
1857 sprint_value (buf2, val & mask);
1858 as_warn (_("%s shortened to %s"), buf1, buf2);
1859 }
1860 return val & mask;
1861}
1862
c32fa91d
L		 1863enum PREFIX_GROUP
1864{
1865 PREFIX_EXIST = 0,
1866 PREFIX_LOCK,
1867 PREFIX_REP,
1868 PREFIX_OTHER
1869};
1870
1871/* Returns
1872 a. PREFIX_EXIST if attempting to add a prefix where one from the
1873 same class already exists.
1874 b. PREFIX_LOCK if lock prefix is added.
1875 c. PREFIX_REP if rep/repne prefix is added.
1876 d. PREFIX_OTHER if other prefix is added.
1877 */
1878
1879static enum PREFIX_GROUP
e3bb37b5 1880add_prefix (unsigned int prefix)
252b5132 1881{
c32fa91d 1882 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1883 unsigned int q;
252b5132 1884
29b0f896
AM		 1885 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1886 && flag_code == CODE_64BIT)
b1905489 1887 {
161a04f6
L		 1888 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1889 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1890 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1891 ret = PREFIX_EXIST;
b1905489
JB		 1892 q = REX_PREFIX;
1893 }
3e73aa7c 1894 else
b1905489
JB		 1895 {
1896 switch (prefix)
1897 {
1898 default:
1899 abort ();
1900
1901 case CS_PREFIX_OPCODE:
1902 case DS_PREFIX_OPCODE:
1903 case ES_PREFIX_OPCODE:
1904 case FS_PREFIX_OPCODE:
1905 case GS_PREFIX_OPCODE:
1906 case SS_PREFIX_OPCODE:
1907 q = SEG_PREFIX;
1908 break;
1909
1910 case REPNE_PREFIX_OPCODE:
1911 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1912 q = REP_PREFIX;
1913 ret = PREFIX_REP;
1914 break;
1915
b1905489 1916 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1917 q = LOCK_PREFIX;
1918 ret = PREFIX_LOCK;
b1905489
JB		 1919 break;
1920
1921 case FWAIT_OPCODE:
1922 q = WAIT_PREFIX;
1923 break;
1924
1925 case ADDR_PREFIX_OPCODE:
1926 q = ADDR_PREFIX;
1927 break;
1928
1929 case DATA_PREFIX_OPCODE:
1930 q = DATA_PREFIX;
1931 break;
1932 }
1933 if (i.prefix[q] != 0)
c32fa91d 1934 ret = PREFIX_EXIST;
b1905489 1935 }
252b5132 1936
b1905489 1937 if (ret)
252b5132 1938 {
b1905489
JB		 1939 if (!i.prefix[q])
1940 ++i.prefixes;
1941 i.prefix[q] |= prefix;
252b5132 1942 }
b1905489
JB		 1943 else
1944 as_bad (_("same type of prefix used twice"));
252b5132 1945
252b5132
RH		 1946 return ret;
1947}
1948
1949static void
78f12dd3 1950update_code_flag (int value, int check)
eecb386c 1951{
78f12dd3
L		 1952 PRINTF_LIKE ((*as_error));
1953
1e9cc1c2 1954 flag_code = (enum flag_code) value;
40fb9820
L		 1955 if (flag_code == CODE_64BIT)
1956 {
1957 cpu_arch_flags.bitfield.cpu64 = 1;
1958 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1959 }
1960 else
1961 {
1962 cpu_arch_flags.bitfield.cpu64 = 0;
1963 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1964 }
1965 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1966 {
78f12dd3
L		 1967 if (check)
1968 as_error = as_fatal;
1969 else
1970 as_error = as_bad;
1971 (*as_error) (_("64bit mode not supported on `%s'."),
1972 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1973 }
40fb9820 1974 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1975 {
78f12dd3
L		 1976 if (check)
1977 as_error = as_fatal;
1978 else
1979 as_error = as_bad;
1980 (*as_error) (_("32bit mode not supported on `%s'."),
1981 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1982 }
eecb386c
AM		 1983 stackop_size = '\0';
1984}
1985
78f12dd3
L		 1986static void
1987set_code_flag (int value)
1988{
1989 update_code_flag (value, 0);
1990}
1991
eecb386c 1992static void
e3bb37b5 1993set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1994{
1e9cc1c2 1995 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1996 if (flag_code != CODE_16BIT)
1997 abort ();
1998 cpu_arch_flags.bitfield.cpu64 = 0;
1999 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2000 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2001}
2002
2003static void
e3bb37b5 2004set_intel_syntax (int syntax_flag)
252b5132
RH		 2005{
2006 /* Find out if register prefixing is specified. */
2007 int ask_naked_reg = 0;
2008
2009 SKIP_WHITESPACE ();
29b0f896 2010 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2011 {
2012 char *string = input_line_pointer;
2013 int e = get_symbol_end ();
2014
47926f60 2015 if (strcmp (string, "prefix") == 0)
252b5132 2016 ask_naked_reg = 1;
47926f60 2017 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2018 ask_naked_reg = -1;
2019 else
d0b47220 2020 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2021 *input_line_pointer = e;
2022 }
2023 demand_empty_rest_of_line ();
c3332e24 2024
252b5132
RH		 2025 intel_syntax = syntax_flag;
2026
2027 if (ask_naked_reg == 0)
f86103b7
AM		 2028 allow_naked_reg = (intel_syntax
2029 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2030 else
2031 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2032
ee86248c 2033 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2034
e4a3b5a4 2035 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2036 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2037 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2038}
2039
1efbbeb4
L		 2040static void
2041set_intel_mnemonic (int mnemonic_flag)
2042{
e1d4d893 2043 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2044}
2045
db51cc60
L		 2046static void
2047set_allow_index_reg (int flag)
2048{
2049 allow_index_reg = flag;
2050}
2051
cb19c032
L		 2052static void
2053set_sse_check (int dummy ATTRIBUTE_UNUSED)
2054{
2055 SKIP_WHITESPACE ();
2056
2057 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2058 {
2059 char *string = input_line_pointer;
2060 int e = get_symbol_end ();
2061
2062 if (strcmp (string, "none") == 0)
2063 sse_check = sse_check_none;
2064 else if (strcmp (string, "warning") == 0)
2065 sse_check = sse_check_warning;
2066 else if (strcmp (string, "error") == 0)
2067 sse_check = sse_check_error;
2068 else
2069 as_bad (_("bad argument to sse_check directive."));
2070 *input_line_pointer = e;
2071 }
2072 else
2073 as_bad (_("missing argument for sse_check directive"));
2074
2075 demand_empty_rest_of_line ();
2076}
2077
8a9036a4
L		 2078static void
2079check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2080 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2081{
2082#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2083 static const char *arch;
2084
2085 /* Intel LIOM is only supported on ELF. */
2086 if (!IS_ELF)
2087 return;
2088
2089 if (!arch)
2090 {
2091 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2092 use default_arch. */
2093 arch = cpu_arch_name;
2094 if (!arch)
2095 arch = default_arch;
2096 }
2097
3632d14b 2098 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2099 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2100 || new_flag.bitfield.cpul1om)
8a9036a4 2101 return;
76ba9986 2102
8a9036a4
L		 2103 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2104#endif
2105}
2106
e413e4e9 2107static void
e3bb37b5 2108set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2109{
47926f60 2110 SKIP_WHITESPACE ();
e413e4e9 2111
29b0f896 2112 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2113 {
2114 char *string = input_line_pointer;
2115 int e = get_symbol_end ();
91d6fa6a 2116 unsigned int j;
40fb9820 2117 i386_cpu_flags flags;
e413e4e9 2118
91d6fa6a 2119 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2120 {
91d6fa6a 2121 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2122 {
91d6fa6a 2123 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2124
5c6af06e
JB		 2125 if (*string != '.')
2126 {
91d6fa6a 2127 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2128 cpu_sub_arch_name = NULL;
91d6fa6a 2129 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2130 if (flag_code == CODE_64BIT)
2131 {
2132 cpu_arch_flags.bitfield.cpu64 = 1;
2133 cpu_arch_flags.bitfield.cpuno64 = 0;
2134 }
2135 else
2136 {
2137 cpu_arch_flags.bitfield.cpu64 = 0;
2138 cpu_arch_flags.bitfield.cpuno64 = 1;
2139 }
91d6fa6a
NC		 2140 cpu_arch_isa = cpu_arch[j].type;
2141 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2142 if (!cpu_arch_tune_set)
2143 {
2144 cpu_arch_tune = cpu_arch_isa;
2145 cpu_arch_tune_flags = cpu_arch_isa_flags;
2146 }
5c6af06e
JB		 2147 break;
2148 }
40fb9820 2149
22109423 2150 if (!cpu_arch[j].negated)
309d3373 2151 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2152 cpu_arch[j].flags);
309d3373
JB		 2153 else
2154 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2155 cpu_arch[j].flags);
0dfbf9d7 2156 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2157 {
6305a203
L		 2158 if (cpu_sub_arch_name)
2159 {
2160 char *name = cpu_sub_arch_name;
2161 cpu_sub_arch_name = concat (name,
91d6fa6a 2162 cpu_arch[j].name,
1bf57e9f 2163 (const char *) NULL);
6305a203
L		 2164 free (name);
2165 }
2166 else
91d6fa6a 2167 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2168 cpu_arch_flags = flags;
5c6af06e
JB		 2169 }
2170 *input_line_pointer = e;
2171 demand_empty_rest_of_line ();
2172 return;
e413e4e9
AM		 2173 }
2174 }
91d6fa6a 2175 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2176 as_bad (_("no such architecture: `%s'"), string);
2177
2178 *input_line_pointer = e;
2179 }
2180 else
2181 as_bad (_("missing cpu architecture"));
2182
fddf5b5b
AM		 2183 no_cond_jump_promotion = 0;
2184 if (*input_line_pointer == ','
29b0f896 2185 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2186 {
2187 char *string = ++input_line_pointer;
2188 int e = get_symbol_end ();
2189
2190 if (strcmp (string, "nojumps") == 0)
2191 no_cond_jump_promotion = 1;
2192 else if (strcmp (string, "jumps") == 0)
2193 ;
2194 else
2195 as_bad (_("no such architecture modifier: `%s'"), string);
2196
2197 *input_line_pointer = e;
2198 }
2199
e413e4e9
AM		 2200 demand_empty_rest_of_line ();
2201}
2202
8a9036a4
L		 2203enum bfd_architecture
2204i386_arch (void)
2205{
3632d14b 2206 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2207 {
2208 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2209 || flag_code != CODE_64BIT)
2210 as_fatal (_("Intel L1OM is 64bit ELF only"));
2211 return bfd_arch_l1om;
2212 }
2213 else
2214 return bfd_arch_i386;
2215}
2216
b9d79e03
JH		 2217unsigned long
2218i386_mach ()
2219{
351f65ca 2220 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2221 {
3632d14b 2222 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2223 {
351f65ca
L		 2224 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2225 || default_arch[6] != '\0')
8a9036a4
L		 2226 as_fatal (_("Intel L1OM is 64bit ELF only"));
2227 return bfd_mach_l1om;
2228 }
351f65ca 2229 else if (default_arch[6] == '\0')
8a9036a4 2230 return bfd_mach_x86_64;
351f65ca
L		 2231 else
2232 return bfd_mach_x64_32;
8a9036a4 2233 }
b9d79e03
JH		 2234 else if (!strcmp (default_arch, "i386"))
2235 return bfd_mach_i386_i386;
2236 else
2237 as_fatal (_("Unknown architecture"));
2238}
b9d79e03 2239\f
252b5132
RH		 2240void
2241md_begin ()
2242{
2243 const char *hash_err;
2244
47926f60 2245 /* Initialize op_hash hash table. */
252b5132
RH		 2246 op_hash = hash_new ();
2247
2248 {
d3ce72d0 2249 const insn_template *optab;
29b0f896 2250 templates *core_optab;
252b5132 2251
47926f60
KH		 2252 /* Setup for loop. */
2253 optab = i386_optab;
252b5132
RH		 2254 core_optab = (templates *) xmalloc (sizeof (templates));
2255 core_optab->start = optab;
2256
2257 while (1)
2258 {
2259 ++optab;
2260 if (optab->name == NULL
2261 || strcmp (optab->name, (optab - 1)->name) != 0)
2262 {
2263 /* different name --> ship out current template list;
47926f60 2264 add to hash table; & begin anew. */
252b5132
RH		 2265 core_optab->end = optab;
2266 hash_err = hash_insert (op_hash,
2267 (optab - 1)->name,
5a49b8ac 2268 (void *) core_optab);
252b5132
RH		 2269 if (hash_err)
2270 {
252b5132
RH		 2271 as_fatal (_("Internal Error: Can't hash %s: %s"),
2272 (optab - 1)->name,
2273 hash_err);
2274 }
2275 if (optab->name == NULL)
2276 break;
2277 core_optab = (templates *) xmalloc (sizeof (templates));
2278 core_optab->start = optab;
2279 }
2280 }
2281 }
2282
47926f60 2283 /* Initialize reg_hash hash table. */
252b5132
RH		 2284 reg_hash = hash_new ();
2285 {
29b0f896 2286 const reg_entry *regtab;
c3fe08fa 2287 unsigned int regtab_size = i386_regtab_size;
252b5132 2288
c3fe08fa 2289 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2290 {
5a49b8ac 2291 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2292 if (hash_err)
3e73aa7c
JH		 2293 as_fatal (_("Internal Error: Can't hash %s: %s"),
2294 regtab->reg_name,
2295 hash_err);
252b5132
RH		 2296 }
2297 }
2298
47926f60 2299 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2300 {
29b0f896
AM		 2301 int c;
2302 char *p;
252b5132
RH		 2303
2304 for (c = 0; c < 256; c++)
2305 {
3882b010 2306 if (ISDIGIT (c))
252b5132
RH		 2307 {
2308 digit_chars[c] = c;
2309 mnemonic_chars[c] = c;
2310 register_chars[c] = c;
2311 operand_chars[c] = c;
2312 }
3882b010 2313 else if (ISLOWER (c))
252b5132
RH		 2314 {
2315 mnemonic_chars[c] = c;
2316 register_chars[c] = c;
2317 operand_chars[c] = c;
2318 }
3882b010 2319 else if (ISUPPER (c))
252b5132 2320 {
3882b010 2321 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2322 register_chars[c] = mnemonic_chars[c];
2323 operand_chars[c] = c;
2324 }
2325
3882b010 2326 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2327 identifier_chars[c] = c;
2328 else if (c >= 128)
2329 {
2330 identifier_chars[c] = c;
2331 operand_chars[c] = c;
2332 }
2333 }
2334
2335#ifdef LEX_AT
2336 identifier_chars['@'] = '@';
32137342
NC		 2337#endif
2338#ifdef LEX_QM
2339 identifier_chars['?'] = '?';
2340 operand_chars['?'] = '?';
252b5132 2341#endif
252b5132 2342 digit_chars['-'] = '-';
c0f3af97 2343 mnemonic_chars['_'] = '_';
791fe849 2344 mnemonic_chars['-'] = '-';
0003779b 2345 mnemonic_chars['.'] = '.';
252b5132
RH		 2346 identifier_chars['_'] = '_';
2347 identifier_chars['.'] = '.';
2348
2349 for (p = operand_special_chars; *p != '\0'; p++)
2350 operand_chars[(unsigned char) *p] = *p;
2351 }
2352
2353#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2354 if (IS_ELF)
252b5132
RH		 2355 {
2356 record_alignment (text_section, 2);
2357 record_alignment (data_section, 2);
2358 record_alignment (bss_section, 2);
2359 }
2360#endif
a4447b93
RH		 2361
2362 if (flag_code == CODE_64BIT)
2363 {
2364 x86_dwarf2_return_column = 16;
2365 x86_cie_data_alignment = -8;
2366 }
2367 else
2368 {
2369 x86_dwarf2_return_column = 8;
2370 x86_cie_data_alignment = -4;
2371 }
252b5132
RH		 2372}
2373
2374void
e3bb37b5 2375i386_print_statistics (FILE *file)
252b5132
RH		 2376{
2377 hash_print_statistics (file, "i386 opcode", op_hash);
2378 hash_print_statistics (file, "i386 register", reg_hash);
2379}
2380\f
252b5132
RH		 2381#ifdef DEBUG386
2382
ce8a8b2f 2383/* Debugging routines for md_assemble. */
d3ce72d0 2384static void pte (insn_template *);
40fb9820 2385static void pt (i386_operand_type);
e3bb37b5
L		 2386static void pe (expressionS *);
2387static void ps (symbolS *);
252b5132
RH		 2388
2389static void
e3bb37b5 2390pi (char *line, i386_insn *x)
252b5132 2391{
09137c09 2392 unsigned int j;
252b5132
RH		 2393
2394 fprintf (stdout, "%s: template ", line);
2395 pte (&x->tm);
09f131f2
JH		 2396 fprintf (stdout, " address: base %s index %s scale %x\n",
2397 x->base_reg ? x->base_reg->reg_name : "none",
2398 x->index_reg ? x->index_reg->reg_name : "none",
2399 x->log2_scale_factor);
2400 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2401 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2402 fprintf (stdout, " sib: base %x index %x scale %x\n",
2403 x->sib.base, x->sib.index, x->sib.scale);
2404 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2405 (x->rex & REX_W) != 0,
2406 (x->rex & REX_R) != 0,
2407 (x->rex & REX_X) != 0,
2408 (x->rex & REX_B) != 0);
09137c09 2409 for (j = 0; j < x->operands; j++)
252b5132 2410 {
09137c09
SP		 2411 fprintf (stdout, " #%d: ", j + 1);
2412 pt (x->types[j]);
252b5132 2413 fprintf (stdout, "\n");
09137c09
SP		 2414 if (x->types[j].bitfield.reg8
2415 || x->types[j].bitfield.reg16
2416 || x->types[j].bitfield.reg32
2417 || x->types[j].bitfield.reg64
2418 || x->types[j].bitfield.regmmx
2419 || x->types[j].bitfield.regxmm
2420 || x->types[j].bitfield.regymm
2421 || x->types[j].bitfield.sreg2
2422 || x->types[j].bitfield.sreg3
2423 || x->types[j].bitfield.control
2424 || x->types[j].bitfield.debug
2425 || x->types[j].bitfield.test)
2426 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2427 if (operand_type_check (x->types[j], imm))
2428 pe (x->op[j].imms);
2429 if (operand_type_check (x->types[j], disp))
2430 pe (x->op[j].disps);
252b5132
RH		 2431 }
2432}
2433
2434static void
d3ce72d0 2435pte (insn_template *t)
252b5132 2436{
09137c09 2437 unsigned int j;
252b5132 2438 fprintf (stdout, " %d operands ", t->operands);
47926f60 2439 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2440 if (t->extension_opcode != None)
2441 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2442 if (t->opcode_modifier.d)
252b5132 2443 fprintf (stdout, "D");
40fb9820 2444 if (t->opcode_modifier.w)
252b5132
RH		 2445 fprintf (stdout, "W");
2446 fprintf (stdout, "\n");
09137c09 2447 for (j = 0; j < t->operands; j++)
252b5132 2448 {
09137c09
SP		 2449 fprintf (stdout, " #%d type ", j + 1);
2450 pt (t->operand_types[j]);
252b5132
RH		 2451 fprintf (stdout, "\n");
2452 }
2453}
2454
2455static void
e3bb37b5 2456pe (expressionS *e)
252b5132 2457{
24eab124 2458 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2459 fprintf (stdout, " add_number %ld (%lx)\n",
2460 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2461 if (e->X_add_symbol)
2462 {
2463 fprintf (stdout, " add_symbol ");
2464 ps (e->X_add_symbol);
2465 fprintf (stdout, "\n");
2466 }
2467 if (e->X_op_symbol)
2468 {
2469 fprintf (stdout, " op_symbol ");
2470 ps (e->X_op_symbol);
2471 fprintf (stdout, "\n");
2472 }
2473}
2474
2475static void
e3bb37b5 2476ps (symbolS *s)
252b5132
RH		 2477{
2478 fprintf (stdout, "%s type %s%s",
2479 S_GET_NAME (s),
2480 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2481 segment_name (S_GET_SEGMENT (s)));
2482}
2483
7b81dfbb 2484static struct type_name
252b5132 2485 {
40fb9820
L		 2486 i386_operand_type mask;
2487 const char *name;
252b5132 2488 }
7b81dfbb 2489const type_names[] =
252b5132 2490{
40fb9820
L		 2491 { OPERAND_TYPE_REG8, "r8" },
2492 { OPERAND_TYPE_REG16, "r16" },
2493 { OPERAND_TYPE_REG32, "r32" },
2494 { OPERAND_TYPE_REG64, "r64" },
2495 { OPERAND_TYPE_IMM8, "i8" },
2496 { OPERAND_TYPE_IMM8, "i8s" },
2497 { OPERAND_TYPE_IMM16, "i16" },
2498 { OPERAND_TYPE_IMM32, "i32" },
2499 { OPERAND_TYPE_IMM32S, "i32s" },
2500 { OPERAND_TYPE_IMM64, "i64" },
2501 { OPERAND_TYPE_IMM1, "i1" },
2502 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2503 { OPERAND_TYPE_DISP8, "d8" },
2504 { OPERAND_TYPE_DISP16, "d16" },
2505 { OPERAND_TYPE_DISP32, "d32" },
2506 { OPERAND_TYPE_DISP32S, "d32s" },
2507 { OPERAND_TYPE_DISP64, "d64" },
2508 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2509 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2510 { OPERAND_TYPE_CONTROL, "control reg" },
2511 { OPERAND_TYPE_TEST, "test reg" },
2512 { OPERAND_TYPE_DEBUG, "debug reg" },
2513 { OPERAND_TYPE_FLOATREG, "FReg" },
2514 { OPERAND_TYPE_FLOATACC, "FAcc" },
2515 { OPERAND_TYPE_SREG2, "SReg2" },
2516 { OPERAND_TYPE_SREG3, "SReg3" },
2517 { OPERAND_TYPE_ACC, "Acc" },
2518 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2519 { OPERAND_TYPE_REGMMX, "rMMX" },
2520 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2521 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2522 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2523};
2524
2525static void
40fb9820 2526pt (i386_operand_type t)
252b5132 2527{
40fb9820 2528 unsigned int j;
c6fb90c8 2529 i386_operand_type a;
252b5132 2530
40fb9820 2531 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2532 {
2533 a = operand_type_and (t, type_names[j].mask);
0349dc08 2534 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2535 fprintf (stdout, "%s, ", type_names[j].name);
2536 }
252b5132
RH		 2537 fflush (stdout);
2538}
2539
2540#endif /* DEBUG386 */
2541\f
252b5132 2542static bfd_reloc_code_real_type
3956db08 2543reloc (unsigned int size,
64e74474
AM		 2544 int pcrel,
2545 int sign,
2546 bfd_reloc_code_real_type other)
252b5132 2547{
47926f60 2548 if (other != NO_RELOC)
3956db08 2549 {
91d6fa6a 2550 reloc_howto_type *rel;
3956db08
JB		 2551
2552 if (size == 8)
2553 switch (other)
2554 {
64e74474
AM		 2555 case BFD_RELOC_X86_64_GOT32:
2556 return BFD_RELOC_X86_64_GOT64;
2557 break;
2558 case BFD_RELOC_X86_64_PLTOFF64:
2559 return BFD_RELOC_X86_64_PLTOFF64;
2560 break;
2561 case BFD_RELOC_X86_64_GOTPC32:
2562 other = BFD_RELOC_X86_64_GOTPC64;
2563 break;
2564 case BFD_RELOC_X86_64_GOTPCREL:
2565 other = BFD_RELOC_X86_64_GOTPCREL64;
2566 break;
2567 case BFD_RELOC_X86_64_TPOFF32:
2568 other = BFD_RELOC_X86_64_TPOFF64;
2569 break;
2570 case BFD_RELOC_X86_64_DTPOFF32:
2571 other = BFD_RELOC_X86_64_DTPOFF64;
2572 break;
2573 default:
2574 break;
3956db08 2575 }
e05278af
JB		 2576
2577 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2578 if (size == 4 && flag_code != CODE_64BIT)
2579 sign = -1;
2580
91d6fa6a
NC		 2581 rel = bfd_reloc_type_lookup (stdoutput, other);
2582 if (!rel)
3956db08 2583 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2584 else if (size != bfd_get_reloc_size (rel))
3956db08 2585 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2586 bfd_get_reloc_size (rel),
3956db08 2587 size);
91d6fa6a 2588 else if (pcrel && !rel->pc_relative)
3956db08 2589 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2590 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2591 && !sign)
91d6fa6a 2592 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2593 && sign > 0))
3956db08
JB		 2594 as_bad (_("relocated field and relocation type differ in signedness"));
2595 else
2596 return other;
2597 return NO_RELOC;
2598 }
252b5132
RH		 2599
2600 if (pcrel)
2601 {
3e73aa7c 2602 if (!sign)
3956db08 2603 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2604 switch (size)
2605 {
2606 case 1: return BFD_RELOC_8_PCREL;
2607 case 2: return BFD_RELOC_16_PCREL;
2608 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2609 case 8: return BFD_RELOC_64_PCREL;
252b5132 2610 }
3956db08 2611 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2612 }
2613 else
2614 {
3956db08 2615 if (sign > 0)
e5cb08ac 2616 switch (size)
3e73aa7c
JH		 2617 {
2618 case 4: return BFD_RELOC_X86_64_32S;
2619 }
2620 else
2621 switch (size)
2622 {
2623 case 1: return BFD_RELOC_8;
2624 case 2: return BFD_RELOC_16;
2625 case 4: return BFD_RELOC_32;
2626 case 8: return BFD_RELOC_64;
2627 }
3956db08
JB		 2628 as_bad (_("cannot do %s %u byte relocation"),
2629 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2630 }
2631
0cc9e1d3 2632 return NO_RELOC;
252b5132
RH		 2633}
2634
47926f60
KH		 2635/* Here we decide which fixups can be adjusted to make them relative to
2636 the beginning of the section instead of the symbol. Basically we need
2637 to make sure that the dynamic relocations are done correctly, so in
2638 some cases we force the original symbol to be used. */
2639
252b5132 2640int
e3bb37b5 2641tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2642{
6d249963 2643#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2644 if (!IS_ELF)
31312f95
AM		 2645 return 1;
2646
a161fe53
AM		 2647 /* Don't adjust pc-relative references to merge sections in 64-bit
2648 mode. */
2649 if (use_rela_relocations
2650 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2651 && fixP->fx_pcrel)
252b5132 2652 return 0;
31312f95 2653
8d01d9a9
AJ		 2654 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2655 and changed later by validate_fix. */
2656 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2657 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2658 return 0;
2659
ce8a8b2f 2660 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2661 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2662 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2663 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2664 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2665 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2666 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2667 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2668 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2669 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2670 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2671 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2672 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2673 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2674 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2675 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2676 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2677 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2678 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2679 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2680 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2681 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2682 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2683 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2684 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2685 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2686 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2687 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2688 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2689 return 0;
31312f95 2690#endif
252b5132
RH		 2691 return 1;
2692}
252b5132 2693
b4cac588 2694static int
e3bb37b5 2695intel_float_operand (const char *mnemonic)
252b5132 2696{
9306ca4a
JB		 2697 /* Note that the value returned is meaningful only for opcodes with (memory)
2698 operands, hence the code here is free to improperly handle opcodes that
2699 have no operands (for better performance and smaller code). */
2700
2701 if (mnemonic[0] != 'f')
2702 return 0; /* non-math */
2703
2704 switch (mnemonic[1])
2705 {
2706 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2707 the fs segment override prefix not currently handled because no
2708 call path can make opcodes without operands get here */
2709 case 'i':
2710 return 2 /* integer op */;
2711 case 'l':
2712 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2713 return 3; /* fldcw/fldenv */
2714 break;
2715 case 'n':
2716 if (mnemonic[2] != 'o' /* fnop */)
2717 return 3; /* non-waiting control op */
2718 break;
2719 case 'r':
2720 if (mnemonic[2] == 's')
2721 return 3; /* frstor/frstpm */
2722 break;
2723 case 's':
2724 if (mnemonic[2] == 'a')
2725 return 3; /* fsave */
2726 if (mnemonic[2] == 't')
2727 {
2728 switch (mnemonic[3])
2729 {
2730 case 'c': /* fstcw */
2731 case 'd': /* fstdw */
2732 case 'e': /* fstenv */
2733 case 's': /* fsts[gw] */
2734 return 3;
2735 }
2736 }
2737 break;
2738 case 'x':
2739 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2740 return 0; /* fxsave/fxrstor are not really math ops */
2741 break;
2742 }
252b5132 2743
9306ca4a 2744 return 1;
252b5132
RH		 2745}
2746
c0f3af97
L		 2747/* Build the VEX prefix. */
2748
2749static void
d3ce72d0 2750build_vex_prefix (const insn_template *t)
c0f3af97
L		 2751{
2752 unsigned int register_specifier;
2753 unsigned int implied_prefix;
2754 unsigned int vector_length;
2755
2756 /* Check register specifier. */
2757 if (i.vex.register_specifier)
2758 {
2759 register_specifier = i.vex.register_specifier->reg_num;
2760 if ((i.vex.register_specifier->reg_flags & RegRex))
2761 register_specifier += 8;
2762 register_specifier = ~register_specifier & 0xf;
2763 }
2764 else
2765 register_specifier = 0xf;
2766
fa99fab2
L		 2767 /* Use 2-byte VEX prefix by swappping destination and source
2768 operand. */
2769 if (!i.swap_operand
2770 && i.operands == i.reg_operands
7f399153 2771 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2772 && i.tm.opcode_modifier.s
2773 && i.rex == REX_B)
2774 {
2775 unsigned int xchg = i.operands - 1;
2776 union i386_op temp_op;
2777 i386_operand_type temp_type;
2778
2779 temp_type = i.types[xchg];
2780 i.types[xchg] = i.types[0];
2781 i.types[0] = temp_type;
2782 temp_op = i.op[xchg];
2783 i.op[xchg] = i.op[0];
2784 i.op[0] = temp_op;
2785
9c2799c2 2786 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2787
2788 i.rex = REX_R;
2789 xchg = i.rm.regmem;
2790 i.rm.regmem = i.rm.reg;
2791 i.rm.reg = xchg;
2792
2793 /* Use the next insn. */
2794 i.tm = t[1];
2795 }
2796
539f890d
L		 2797 if (i.tm.opcode_modifier.vex == VEXScalar)
2798 vector_length = avxscalar;
2799 else
2800 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2801
2802 switch ((i.tm.base_opcode >> 8) & 0xff)
2803 {
2804 case 0:
2805 implied_prefix = 0;
2806 break;
2807 case DATA_PREFIX_OPCODE:
2808 implied_prefix = 1;
2809 break;
2810 case REPE_PREFIX_OPCODE:
2811 implied_prefix = 2;
2812 break;
2813 case REPNE_PREFIX_OPCODE:
2814 implied_prefix = 3;
2815 break;
2816 default:
2817 abort ();
2818 }
2819
2820 /* Use 2-byte VEX prefix if possible. */
7f399153 2821 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2822 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2823 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2824 {
2825 /* 2-byte VEX prefix. */
2826 unsigned int r;
2827
2828 i.vex.length = 2;
2829 i.vex.bytes[0] = 0xc5;
2830
2831 /* Check the REX.R bit. */
2832 r = (i.rex & REX_R) ? 0 : 1;
2833 i.vex.bytes[1] = (r << 7
2834 | register_specifier << 3
2835 | vector_length << 2
2836 | implied_prefix);
2837 }
2838 else
2839 {
2840 /* 3-byte VEX prefix. */
2841 unsigned int m, w;
2842
f88c9eb0 2843 i.vex.length = 3;
f88c9eb0 2844
7f399153 2845 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2846 {
7f399153
L		 2847 case VEX0F:
2848 m = 0x1;
80de6e00 2849 i.vex.bytes[0] = 0xc4;
7f399153
L		 2850 break;
2851 case VEX0F38:
2852 m = 0x2;
80de6e00 2853 i.vex.bytes[0] = 0xc4;
7f399153
L		 2854 break;
2855 case VEX0F3A:
2856 m = 0x3;
80de6e00 2857 i.vex.bytes[0] = 0xc4;
7f399153
L		 2858 break;
2859 case XOP08:
5dd85c99
SP		 2860 m = 0x8;
2861 i.vex.bytes[0] = 0x8f;
7f399153
L		 2862 break;
2863 case XOP09:
f88c9eb0
SP		 2864 m = 0x9;
2865 i.vex.bytes[0] = 0x8f;
7f399153
L		 2866 break;
2867 case XOP0A:
f88c9eb0
SP		 2868 m = 0xa;
2869 i.vex.bytes[0] = 0x8f;
7f399153
L		 2870 break;
2871 default:
2872 abort ();
f88c9eb0 2873 }
c0f3af97 2874
c0f3af97
L		 2875 /* The high 3 bits of the second VEX byte are 1's compliment
2876 of RXB bits from REX. */
2877 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2878
2879 /* Check the REX.W bit. */
2880 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2881 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2882 {
2883 if (w)
2884 abort ();
2885
1ef99a7b 2886 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2887 w = 1;
2888 }
2889
2890 i.vex.bytes[2] = (w << 7
2891 | register_specifier << 3
2892 | vector_length << 2
2893 | implied_prefix);
2894 }
2895}
2896
65da13b5
L		 2897static void
2898process_immext (void)
2899{
2900 expressionS *exp;
2901
2902 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2903 {
1fed0ba1
L		 2904 /* SSE3 Instructions have the fixed operands with an opcode
2905 suffix which is coded in the same place as an 8-bit immediate
2906 field would be. Here we check those operands and remove them
2907 afterwards. */
65da13b5
L		 2908 unsigned int x;
2909
2910 for (x = 0; x < i.operands; x++)
2911 if (i.op[x].regs->reg_num != x)
2912 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2913 register_prefix, i.op[x].regs->reg_name, x + 1,
2914 i.tm.name);
2915
2916 i.operands = 0;
65da13b5
L		 2917 }
2918
c0f3af97 2919 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2920 which is coded in the same place as an 8-bit immediate field
2921 would be. Here we fake an 8-bit immediate operand from the
2922 opcode suffix stored in tm.extension_opcode.
2923
c1e679ec 2924 AVX instructions also use this encoding, for some of
c0f3af97 2925 3 argument instructions. */
65da13b5 2926
9c2799c2 2927 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2928 && (i.operands <= 2
2929 || (i.tm.opcode_modifier.vex
2930 && i.operands <= 4)));
65da13b5
L		 2931
2932 exp = &im_expressions[i.imm_operands++];
2933 i.op[i.operands].imms = exp;
2934 i.types[i.operands] = imm8;
2935 i.operands++;
2936 exp->X_op = O_constant;
2937 exp->X_add_number = i.tm.extension_opcode;
2938 i.tm.extension_opcode = None;
2939}
2940
252b5132
RH		 2941/* This is the guts of the machine-dependent assembler. LINE points to a
2942 machine dependent instruction. This function is supposed to emit
2943 the frags/bytes it assembles to. */
2944
2945void
65da13b5 2946md_assemble (char *line)
252b5132 2947{
40fb9820 2948 unsigned int j;
252b5132 2949 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2950 const insn_template *t;
252b5132 2951
47926f60 2952 /* Initialize globals. */
252b5132
RH		 2953 memset (&i, '\0', sizeof (i));
2954 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2955 i.reloc[j] = NO_RELOC;
252b5132
RH		 2956 memset (disp_expressions, '\0', sizeof (disp_expressions));
2957 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2958 save_stack_p = save_stack;
252b5132
RH		 2959
2960 /* First parse an instruction mnemonic & call i386_operand for the operands.
2961 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2962 start of a (possibly prefixed) mnemonic. */
252b5132 2963
29b0f896
AM		 2964 line = parse_insn (line, mnemonic);
2965 if (line == NULL)
2966 return;
252b5132 2967
29b0f896 2968 line = parse_operands (line, mnemonic);
ee86248c 2969 this_operand = -1;
29b0f896
AM		 2970 if (line == NULL)
2971 return;
252b5132 2972
29b0f896
AM		 2973 /* Now we've parsed the mnemonic into a set of templates, and have the
2974 operands at hand. */
2975
2976 /* All intel opcodes have reversed operands except for "bound" and
2977 "enter". We also don't reverse intersegment "jmp" and "call"
2978 instructions with 2 immediate operands so that the immediate segment
050dfa73 2979 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2980 if (intel_syntax
2981 && i.operands > 1
29b0f896 2982 && (strcmp (mnemonic, "bound") != 0)
30123838 2983 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2984 && !(operand_type_check (i.types[0], imm)
2985 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2986 swap_operands ();
2987
ec56d5c0
JB		 2988 /* The order of the immediates should be reversed
2989 for 2 immediates extrq and insertq instructions */
2990 if (i.imm_operands == 2
2991 && (strcmp (mnemonic, "extrq") == 0
2992 || strcmp (mnemonic, "insertq") == 0))
2993 swap_2_operands (0, 1);
2994
29b0f896
AM		 2995 if (i.imm_operands)
2996 optimize_imm ();
2997
b300c311
L		 2998 /* Don't optimize displacement for movabs since it only takes 64bit
2999 displacement. */
3000 if (i.disp_operands
f8a5c266 3001 && !i.disp32_encoding
b300c311
L		 3002 && (flag_code != CODE_64BIT
3003 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 3004 optimize_disp ();
3005
3006 /* Next, we find a template that matches the given insn,
3007 making sure the overlap of the given operands types is consistent
3008 with the template operand types. */
252b5132 3009
fa99fab2 3010 if (!(t = match_template ()))
29b0f896 3011 return;
252b5132 3012
daf50ae7 3013 if (sse_check != sse_check_none
81f8a913 3014 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3015 && (i.tm.cpu_flags.bitfield.cpusse
3016 || i.tm.cpu_flags.bitfield.cpusse2
3017 || i.tm.cpu_flags.bitfield.cpusse3
3018 || i.tm.cpu_flags.bitfield.cpussse3
3019 || i.tm.cpu_flags.bitfield.cpusse4_1
3020 || i.tm.cpu_flags.bitfield.cpusse4_2))
3021 {
3022 (sse_check == sse_check_warning
3023 ? as_warn
3024 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3025 }
3026
321fd21e
L		 3027 /* Zap movzx and movsx suffix. The suffix has been set from
3028 "word ptr" or "byte ptr" on the source operand in Intel syntax
3029 or extracted from mnemonic in AT&T syntax. But we'll use
3030 the destination register to choose the suffix for encoding. */
3031 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3032 {
321fd21e
L		 3033 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3034 there is no suffix, the default will be byte extension. */
3035 if (i.reg_operands != 2
3036 && !i.suffix
7ab9ffdd 3037 && intel_syntax)
321fd21e
L		 3038 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3039
3040 i.suffix = 0;
cd61ebfe 3041 }
24eab124 3042
40fb9820 3043 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3044 if (!add_prefix (FWAIT_OPCODE))
3045 return;
252b5132 3046
c1ba0266
L		 3047 /* Check for lock without a lockable instruction. Destination operand
3048 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3049 if (i.prefix[LOCK_PREFIX]
3050 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3051 || i.mem_operands == 0
3052 || (i.tm.base_opcode != 0x86
3053 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3054 {
3055 as_bad (_("expecting lockable instruction after `lock'"));
3056 return;
3057 }
3058
29b0f896 3059 /* Check string instruction segment overrides. */
40fb9820 3060 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3061 {
3062 if (!check_string ())
5dd0794d 3063 return;
fc0763e6 3064 i.disp_operands = 0;
29b0f896 3065 }
5dd0794d 3066
29b0f896
AM		 3067 if (!process_suffix ())
3068 return;
e413e4e9 3069
bc0844ae
L		 3070 /* Update operand types. */
3071 for (j = 0; j < i.operands; j++)
3072 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3073
29b0f896
AM		 3074 /* Make still unresolved immediate matches conform to size of immediate
3075 given in i.suffix. */
3076 if (!finalize_imm ())
3077 return;
252b5132 3078
40fb9820 3079 if (i.types[0].bitfield.imm1)
29b0f896 3080 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3081
9afe6eb8
L		 3082 /* We only need to check those implicit registers for instructions
3083 with 3 operands or less. */
3084 if (i.operands <= 3)
3085 for (j = 0; j < i.operands; j++)
3086 if (i.types[j].bitfield.inoutportreg
3087 || i.types[j].bitfield.shiftcount
3088 || i.types[j].bitfield.acc
3089 || i.types[j].bitfield.floatacc)
3090 i.reg_operands--;
40fb9820 3091
c0f3af97
L		 3092 /* ImmExt should be processed after SSE2AVX. */
3093 if (!i.tm.opcode_modifier.sse2avx
3094 && i.tm.opcode_modifier.immext)
65da13b5 3095 process_immext ();
252b5132 3096
29b0f896
AM		 3097 /* For insns with operands there are more diddles to do to the opcode. */
3098 if (i.operands)
3099 {
3100 if (!process_operands ())
3101 return;
3102 }
40fb9820 3103 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3104 {
3105 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3106 as_warn (_("translating to `%sp'"), i.tm.name);
3107 }
252b5132 3108
c0f3af97 3109 if (i.tm.opcode_modifier.vex)
fa99fab2 3110 build_vex_prefix (t);
c0f3af97 3111
5dd85c99
SP		 3112 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3113 instructions may define INT_OPCODE as well, so avoid this corner
3114 case for those instructions that use MODRM. */
3115 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3116 && !i.tm.opcode_modifier.modrm
3117 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3118 {
3119 i.tm.base_opcode = INT3_OPCODE;
3120 i.imm_operands = 0;
3121 }
252b5132 3122
40fb9820
L		 3123 if ((i.tm.opcode_modifier.jump
3124 || i.tm.opcode_modifier.jumpbyte
3125 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3126 && i.op[0].disps->X_op == O_constant)
3127 {
3128 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3129 the absolute address given by the constant. Since ix86 jumps and
3130 calls are pc relative, we need to generate a reloc. */
3131 i.op[0].disps->X_add_symbol = &abs_symbol;
3132 i.op[0].disps->X_op = O_symbol;
3133 }
252b5132 3134
40fb9820 3135 if (i.tm.opcode_modifier.rex64)
161a04f6 3136 i.rex |= REX_W;
252b5132 3137
29b0f896
AM		 3138 /* For 8 bit registers we need an empty rex prefix. Also if the
3139 instruction already has a prefix, we need to convert old
3140 registers to new ones. */
773f551c 3141
40fb9820 3142 if ((i.types[0].bitfield.reg8
29b0f896 3143 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3144 || (i.types[1].bitfield.reg8
29b0f896 3145 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3146 || ((i.types[0].bitfield.reg8
3147 || i.types[1].bitfield.reg8)
29b0f896
AM		 3148 && i.rex != 0))
3149 {
3150 int x;
726c5dcd 3151
29b0f896
AM		 3152 i.rex |= REX_OPCODE;
3153 for (x = 0; x < 2; x++)
3154 {
3155 /* Look for 8 bit operand that uses old registers. */
40fb9820 3156 if (i.types[x].bitfield.reg8
29b0f896 3157 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3158 {
29b0f896
AM		 3159 /* In case it is "hi" register, give up. */
3160 if (i.op[x].regs->reg_num > 3)
a540244d 3161 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3162 "instruction requiring REX prefix."),
a540244d 3163 register_prefix, i.op[x].regs->reg_name);
773f551c 3164
29b0f896
AM		 3165 /* Otherwise it is equivalent to the extended register.
3166 Since the encoding doesn't change this is merely
3167 cosmetic cleanup for debug output. */
3168
3169 i.op[x].regs = i.op[x].regs + 8;
773f551c 3170 }
29b0f896
AM		 3171 }
3172 }
773f551c 3173
7ab9ffdd 3174 if (i.rex != 0)
29b0f896
AM		 3175 add_prefix (REX_OPCODE | i.rex);
3176
3177 /* We are ready to output the insn. */
3178 output_insn ();
3179}
3180
3181static char *
e3bb37b5 3182parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3183{
3184 char *l = line;
3185 char *token_start = l;
3186 char *mnem_p;
5c6af06e 3187 int supported;
d3ce72d0 3188 const insn_template *t;
b6169b20 3189 char *dot_p = NULL;
29b0f896
AM		 3190
3191 /* Non-zero if we found a prefix only acceptable with string insns. */
3192 const char *expecting_string_instruction = NULL;
45288df1 3193
29b0f896
AM		 3194 while (1)
3195 {
3196 mnem_p = mnemonic;
3197 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3198 {
b6169b20
L		 3199 if (*mnem_p == '.')
3200 dot_p = mnem_p;
29b0f896
AM		 3201 mnem_p++;
3202 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3203 {
29b0f896
AM		 3204 as_bad (_("no such instruction: `%s'"), token_start);
3205 return NULL;
3206 }
3207 l++;
3208 }
3209 if (!is_space_char (*l)
3210 && *l != END_OF_INSN
e44823cf
JB		 3211 && (intel_syntax
3212 || (*l != PREFIX_SEPARATOR
3213 && *l != ',')))
29b0f896
AM		 3214 {
3215 as_bad (_("invalid character %s in mnemonic"),
3216 output_invalid (*l));
3217 return NULL;
3218 }
3219 if (token_start == l)
3220 {
e44823cf 3221 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3222 as_bad (_("expecting prefix; got nothing"));
3223 else
3224 as_bad (_("expecting mnemonic; got nothing"));
3225 return NULL;
3226 }
45288df1 3227
29b0f896 3228 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3229 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3230
29b0f896
AM		 3231 if (*l != END_OF_INSN
3232 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3233 && current_templates
40fb9820 3234 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3235 {
c6fb90c8 3236 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3237 {
3238 as_bad ((flag_code != CODE_64BIT
3239 ? _("`%s' is only supported in 64-bit mode")
3240 : _("`%s' is not supported in 64-bit mode")),
3241 current_templates->start->name);
3242 return NULL;
3243 }
29b0f896
AM		 3244 /* If we are in 16-bit mode, do not allow addr16 or data16.
3245 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3246 if ((current_templates->start->opcode_modifier.size16
3247 || current_templates->start->opcode_modifier.size32)
29b0f896 3248 && flag_code != CODE_64BIT
40fb9820 3249 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3250 ^ (flag_code == CODE_16BIT)))
3251 {
3252 as_bad (_("redundant %s prefix"),
3253 current_templates->start->name);
3254 return NULL;
45288df1 3255 }
29b0f896
AM		 3256 /* Add prefix, checking for repeated prefixes. */
3257 switch (add_prefix (current_templates->start->base_opcode))
3258 {
c32fa91d 3259 case PREFIX_EXIST:
29b0f896 3260 return NULL;
c32fa91d 3261 case PREFIX_REP:
29b0f896
AM		 3262 expecting_string_instruction = current_templates->start->name;
3263 break;
c32fa91d
L		 3264 default:
3265 break;
29b0f896
AM		 3266 }
3267 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3268 token_start = ++l;
3269 }
3270 else
3271 break;
3272 }
45288df1 3273
30a55f88 3274 if (!current_templates)
b6169b20 3275 {
f8a5c266
L		 3276 /* Check if we should swap operand or force 32bit displacement in
3277 encoding. */
30a55f88
L		 3278 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3279 i.swap_operand = 1;
f8a5c266
L		 3280 else if (mnem_p - 4 == dot_p
3281 && dot_p[1] == 'd'
3282 && dot_p[2] == '3'
3283 && dot_p[3] == '2')
3284 i.disp32_encoding = 1;
30a55f88
L		 3285 else
3286 goto check_suffix;
3287 mnem_p = dot_p;
3288 *dot_p = '\0';
d3ce72d0 3289 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3290 }
3291
29b0f896
AM		 3292 if (!current_templates)
3293 {
b6169b20 3294check_suffix:
29b0f896
AM		 3295 /* See if we can get a match by trimming off a suffix. */
3296 switch (mnem_p[-1])
3297 {
3298 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3299 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3300 i.suffix = SHORT_MNEM_SUFFIX;
3301 else
29b0f896
AM		 3302 case BYTE_MNEM_SUFFIX:
3303 case QWORD_MNEM_SUFFIX:
3304 i.suffix = mnem_p[-1];
3305 mnem_p[-1] = '\0';
d3ce72d0
NC		 3306 current_templates = (const templates *) hash_find (op_hash,
3307 mnemonic);
29b0f896
AM		 3308 break;
3309 case SHORT_MNEM_SUFFIX:
3310 case LONG_MNEM_SUFFIX:
3311 if (!intel_syntax)
3312 {
3313 i.suffix = mnem_p[-1];
3314 mnem_p[-1] = '\0';
d3ce72d0
NC		 3315 current_templates = (const templates *) hash_find (op_hash,
3316 mnemonic);
29b0f896
AM		 3317 }
3318 break;
252b5132 3319
29b0f896
AM		 3320 /* Intel Syntax. */
3321 case 'd':
3322 if (intel_syntax)
3323 {
9306ca4a 3324 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3325 i.suffix = SHORT_MNEM_SUFFIX;
3326 else
3327 i.suffix = LONG_MNEM_SUFFIX;
3328 mnem_p[-1] = '\0';
d3ce72d0
NC		 3329 current_templates = (const templates *) hash_find (op_hash,
3330 mnemonic);
29b0f896
AM		 3331 }
3332 break;
3333 }
3334 if (!current_templates)
3335 {
3336 as_bad (_("no such instruction: `%s'"), token_start);
3337 return NULL;
3338 }
3339 }
252b5132 3340
40fb9820
L		 3341 if (current_templates->start->opcode_modifier.jump
3342 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3343 {
3344 /* Check for a branch hint. We allow ",pt" and ",pn" for
3345 predict taken and predict not taken respectively.
3346 I'm not sure that branch hints actually do anything on loop
3347 and jcxz insns (JumpByte) for current Pentium4 chips. They
3348 may work in the future and it doesn't hurt to accept them
3349 now. */
3350 if (l[0] == ',' && l[1] == 'p')
3351 {
3352 if (l[2] == 't')
3353 {
3354 if (!add_prefix (DS_PREFIX_OPCODE))
3355 return NULL;
3356 l += 3;
3357 }
3358 else if (l[2] == 'n')
3359 {
3360 if (!add_prefix (CS_PREFIX_OPCODE))
3361 return NULL;
3362 l += 3;
3363 }
3364 }
3365 }
3366 /* Any other comma loses. */
3367 if (*l == ',')
3368 {
3369 as_bad (_("invalid character %s in mnemonic"),
3370 output_invalid (*l));
3371 return NULL;
3372 }
252b5132 3373
29b0f896 3374 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3375 supported = 0;
3376 for (t = current_templates->start; t < current_templates->end; ++t)
3377 {
c0f3af97
L		 3378 supported |= cpu_flags_match (t);
3379 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3380 goto skip;
5c6af06e 3381 }
3629bb00 3382
c0f3af97 3383 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3384 {
3385 as_bad (flag_code == CODE_64BIT
3386 ? _("`%s' is not supported in 64-bit mode")
3387 : _("`%s' is only supported in 64-bit mode"),
3388 current_templates->start->name);
3389 return NULL;
3390 }
c0f3af97 3391 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3392 {
3629bb00 3393 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3394 current_templates->start->name,
41aacd83 3395 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3396 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3397 return NULL;
29b0f896 3398 }
3629bb00
L		 3399
3400skip:
3401 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3402 && (flag_code != CODE_16BIT))
29b0f896
AM		 3403 {
3404 as_warn (_("use .code16 to ensure correct addressing mode"));
3405 }
252b5132 3406
29b0f896 3407 /* Check for rep/repne without a string instruction. */
f41bbced 3408 if (expecting_string_instruction)
29b0f896 3409 {
f41bbced
JB		 3410 static templates override;
3411
3412 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3413 if (t->opcode_modifier.isstring)
f41bbced
JB		 3414 break;
3415 if (t >= current_templates->end)
3416 {
3417 as_bad (_("expecting string instruction after `%s'"),
64e74474 3418 expecting_string_instruction);
f41bbced
JB		 3419 return NULL;
3420 }
3421 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3422 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3423 break;
3424 override.end = t;
3425 current_templates = &override;
29b0f896 3426 }
252b5132 3427
29b0f896
AM		 3428 return l;
3429}
252b5132 3430
29b0f896 3431static char *
e3bb37b5 3432parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3433{
3434 char *token_start;
3138f287 3435
29b0f896
AM		 3436 /* 1 if operand is pending after ','. */
3437 unsigned int expecting_operand = 0;
252b5132 3438
29b0f896
AM		 3439 /* Non-zero if operand parens not balanced. */
3440 unsigned int paren_not_balanced;
3441
3442 while (*l != END_OF_INSN)
3443 {
3444 /* Skip optional white space before operand. */
3445 if (is_space_char (*l))
3446 ++l;
3447 if (!is_operand_char (*l) && *l != END_OF_INSN)
3448 {
3449 as_bad (_("invalid character %s before operand %d"),
3450 output_invalid (*l),
3451 i.operands + 1);
3452 return NULL;
3453 }
3454 token_start = l; /* after white space */
3455 paren_not_balanced = 0;
3456 while (paren_not_balanced || *l != ',')
3457 {
3458 if (*l == END_OF_INSN)
3459 {
3460 if (paren_not_balanced)
3461 {
3462 if (!intel_syntax)
3463 as_bad (_("unbalanced parenthesis in operand %d."),
3464 i.operands + 1);
3465 else
3466 as_bad (_("unbalanced brackets in operand %d."),
3467 i.operands + 1);
3468 return NULL;
3469 }
3470 else
3471 break; /* we are done */
3472 }
3473 else if (!is_operand_char (*l) && !is_space_char (*l))
3474 {
3475 as_bad (_("invalid character %s in operand %d"),
3476 output_invalid (*l),
3477 i.operands + 1);
3478 return NULL;
3479 }
3480 if (!intel_syntax)
3481 {
3482 if (*l == '(')
3483 ++paren_not_balanced;
3484 if (*l == ')')
3485 --paren_not_balanced;
3486 }
3487 else
3488 {
3489 if (*l == '[')
3490 ++paren_not_balanced;
3491 if (*l == ']')
3492 --paren_not_balanced;
3493 }
3494 l++;
3495 }
3496 if (l != token_start)
3497 { /* Yes, we've read in another operand. */
3498 unsigned int operand_ok;
3499 this_operand = i.operands++;
7d5e4556 3500 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3501 if (i.operands > MAX_OPERANDS)
3502 {
3503 as_bad (_("spurious operands; (%d operands/instruction max)"),
3504 MAX_OPERANDS);
3505 return NULL;
3506 }
3507 /* Now parse operand adding info to 'i' as we go along. */
3508 END_STRING_AND_SAVE (l);
3509
3510 if (intel_syntax)
3511 operand_ok =
3512 i386_intel_operand (token_start,
3513 intel_float_operand (mnemonic));
3514 else
a7619375 3515 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3516
3517 RESTORE_END_STRING (l);
3518 if (!operand_ok)
3519 return NULL;
3520 }
3521 else
3522 {
3523 if (expecting_operand)
3524 {
3525 expecting_operand_after_comma:
3526 as_bad (_("expecting operand after ','; got nothing"));
3527 return NULL;
3528 }
3529 if (*l == ',')
3530 {
3531 as_bad (_("expecting operand before ','; got nothing"));
3532 return NULL;
3533 }
3534 }
7f3f1ea2 3535
29b0f896
AM		 3536 /* Now *l must be either ',' or END_OF_INSN. */
3537 if (*l == ',')
3538 {
3539 if (*++l == END_OF_INSN)
3540 {
3541 /* Just skip it, if it's \n complain. */
3542 goto expecting_operand_after_comma;
3543 }
3544 expecting_operand = 1;
3545 }
3546 }
3547 return l;
3548}
7f3f1ea2 3549
050dfa73 3550static void
4d456e3d 3551swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3552{
3553 union i386_op temp_op;
40fb9820 3554 i386_operand_type temp_type;
050dfa73 3555 enum bfd_reloc_code_real temp_reloc;
4eed87de 3556
050dfa73
MM		 3557 temp_type = i.types[xchg2];
3558 i.types[xchg2] = i.types[xchg1];
3559 i.types[xchg1] = temp_type;
3560 temp_op = i.op[xchg2];
3561 i.op[xchg2] = i.op[xchg1];
3562 i.op[xchg1] = temp_op;
3563 temp_reloc = i.reloc[xchg2];
3564 i.reloc[xchg2] = i.reloc[xchg1];
3565 i.reloc[xchg1] = temp_reloc;
3566}
3567
29b0f896 3568static void
e3bb37b5 3569swap_operands (void)
29b0f896 3570{
b7c61d9a 3571 switch (i.operands)
050dfa73 3572 {
c0f3af97 3573 case 5:
b7c61d9a 3574 case 4:
4d456e3d 3575 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3576 case 3:
3577 case 2:
4d456e3d 3578 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3579 break;
3580 default:
3581 abort ();
29b0f896 3582 }
29b0f896
AM		 3583
3584 if (i.mem_operands == 2)
3585 {
3586 const seg_entry *temp_seg;
3587 temp_seg = i.seg[0];
3588 i.seg[0] = i.seg[1];
3589 i.seg[1] = temp_seg;
3590 }
3591}
252b5132 3592
29b0f896
AM		 3593/* Try to ensure constant immediates are represented in the smallest
3594 opcode possible. */
3595static void
e3bb37b5 3596optimize_imm (void)
29b0f896
AM		 3597{
3598 char guess_suffix = 0;
3599 int op;
252b5132 3600
29b0f896
AM		 3601 if (i.suffix)
3602 guess_suffix = i.suffix;
3603 else if (i.reg_operands)
3604 {
3605 /* Figure out a suffix from the last register operand specified.
3606 We can't do this properly yet, ie. excluding InOutPortReg,
3607 but the following works for instructions with immediates.
3608 In any case, we can't set i.suffix yet. */
3609 for (op = i.operands; --op >= 0;)
40fb9820 3610 if (i.types[op].bitfield.reg8)
7ab9ffdd 3611 {
40fb9820
L		 3612 guess_suffix = BYTE_MNEM_SUFFIX;
3613 break;
3614 }
3615 else if (i.types[op].bitfield.reg16)
252b5132 3616 {
40fb9820
L		 3617 guess_suffix = WORD_MNEM_SUFFIX;
3618 break;
3619 }
3620 else if (i.types[op].bitfield.reg32)
3621 {
3622 guess_suffix = LONG_MNEM_SUFFIX;
3623 break;
3624 }
3625 else if (i.types[op].bitfield.reg64)
3626 {
3627 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3628 break;
252b5132 3629 }
29b0f896
AM		 3630 }
3631 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3632 guess_suffix = WORD_MNEM_SUFFIX;
3633
3634 for (op = i.operands; --op >= 0;)
40fb9820 3635 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3636 {
3637 switch (i.op[op].imms->X_op)
252b5132 3638 {
29b0f896
AM		 3639 case O_constant:
3640 /* If a suffix is given, this operand may be shortened. */
3641 switch (guess_suffix)
252b5132 3642 {
29b0f896 3643 case LONG_MNEM_SUFFIX:
40fb9820
L		 3644 i.types[op].bitfield.imm32 = 1;
3645 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3646 break;
3647 case WORD_MNEM_SUFFIX:
40fb9820
L		 3648 i.types[op].bitfield.imm16 = 1;
3649 i.types[op].bitfield.imm32 = 1;
3650 i.types[op].bitfield.imm32s = 1;
3651 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3652 break;
3653 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3654 i.types[op].bitfield.imm8 = 1;
3655 i.types[op].bitfield.imm8s = 1;
3656 i.types[op].bitfield.imm16 = 1;
3657 i.types[op].bitfield.imm32 = 1;
3658 i.types[op].bitfield.imm32s = 1;
3659 i.types[op].bitfield.imm64 = 1;
29b0f896 3660 break;
252b5132 3661 }
252b5132 3662
29b0f896
AM		 3663 /* If this operand is at most 16 bits, convert it
3664 to a signed 16 bit number before trying to see
3665 whether it will fit in an even smaller size.
3666 This allows a 16-bit operand such as $0xffe0 to
3667 be recognised as within Imm8S range. */
40fb9820 3668 if ((i.types[op].bitfield.imm16)
29b0f896 3669 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3670 {
29b0f896
AM		 3671 i.op[op].imms->X_add_number =
3672 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3673 }
40fb9820 3674 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3675 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3676 == 0))
3677 {
3678 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3679 ^ ((offsetT) 1 << 31))
3680 - ((offsetT) 1 << 31));
3681 }
40fb9820 3682 i.types[op]
c6fb90c8
L		 3683 = operand_type_or (i.types[op],
3684 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3685
29b0f896
AM		 3686 /* We must avoid matching of Imm32 templates when 64bit
3687 only immediate is available. */
3688 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3689 i.types[op].bitfield.imm32 = 0;
29b0f896 3690 break;
252b5132 3691
29b0f896
AM		 3692 case O_absent:
3693 case O_register:
3694 abort ();
3695
3696 /* Symbols and expressions. */
3697 default:
9cd96992
JB		 3698 /* Convert symbolic operand to proper sizes for matching, but don't
3699 prevent matching a set of insns that only supports sizes other
3700 than those matching the insn suffix. */
3701 {
40fb9820 3702 i386_operand_type mask, allowed;
d3ce72d0 3703 const insn_template *t;
9cd96992 3704
0dfbf9d7
L		 3705 operand_type_set (&mask, 0);
3706 operand_type_set (&allowed, 0);
40fb9820 3707
4eed87de
AM		 3708 for (t = current_templates->start;
3709 t < current_templates->end;
3710 ++t)
c6fb90c8
L		 3711 allowed = operand_type_or (allowed,
3712 t->operand_types[op]);
9cd96992
JB		 3713 switch (guess_suffix)
3714 {
3715 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3716 mask.bitfield.imm64 = 1;
3717 mask.bitfield.imm32s = 1;
9cd96992
JB		 3718 break;
3719 case LONG_MNEM_SUFFIX:
40fb9820 3720 mask.bitfield.imm32 = 1;
9cd96992
JB		 3721 break;
3722 case WORD_MNEM_SUFFIX:
40fb9820 3723 mask.bitfield.imm16 = 1;
9cd96992
JB		 3724 break;
3725 case BYTE_MNEM_SUFFIX:
40fb9820 3726 mask.bitfield.imm8 = 1;
9cd96992
JB		 3727 break;
3728 default:
9cd96992
JB		 3729 break;
3730 }
c6fb90c8 3731 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3732 if (!operand_type_all_zero (&allowed))
c6fb90c8 3733 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3734 }
29b0f896 3735 break;
252b5132 3736 }
29b0f896
AM		 3737 }
3738}
47926f60 3739
29b0f896
AM		 3740/* Try to use the smallest displacement type too. */
3741static void
e3bb37b5 3742optimize_disp (void)
29b0f896
AM		 3743{
3744 int op;
3e73aa7c 3745
29b0f896 3746 for (op = i.operands; --op >= 0;)
40fb9820 3747 if (operand_type_check (i.types[op], disp))
252b5132 3748 {
b300c311 3749 if (i.op[op].disps->X_op == O_constant)
252b5132 3750 {
91d6fa6a 3751 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3752
40fb9820 3753 if (i.types[op].bitfield.disp16
91d6fa6a 3754 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3755 {
3756 /* If this operand is at most 16 bits, convert
3757 to a signed 16 bit number and don't use 64bit
3758 displacement. */
91d6fa6a 3759 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3760 i.types[op].bitfield.disp64 = 0;
b300c311 3761 }
40fb9820 3762 if (i.types[op].bitfield.disp32
91d6fa6a 3763 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3764 {
3765 /* If this operand is at most 32 bits, convert
3766 to a signed 32 bit number and don't use 64bit
3767 displacement. */
91d6fa6a
NC		 3768 op_disp &= (((offsetT) 2 << 31) - 1);
3769 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3770 i.types[op].bitfield.disp64 = 0;
b300c311 3771 }
91d6fa6a 3772 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3773 {
40fb9820
L		 3774 i.types[op].bitfield.disp8 = 0;
3775 i.types[op].bitfield.disp16 = 0;
3776 i.types[op].bitfield.disp32 = 0;
3777 i.types[op].bitfield.disp32s = 0;
3778 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3779 i.op[op].disps = 0;
3780 i.disp_operands--;
3781 }
3782 else if (flag_code == CODE_64BIT)
3783 {
91d6fa6a 3784 if (fits_in_signed_long (op_disp))
28a9d8f5 3785 {
40fb9820
L		 3786 i.types[op].bitfield.disp64 = 0;
3787 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3788 }
0e1147d9 3789 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3790 && fits_in_unsigned_long (op_disp))
40fb9820 3791 i.types[op].bitfield.disp32 = 1;
b300c311 3792 }
40fb9820
L		 3793 if ((i.types[op].bitfield.disp32
3794 || i.types[op].bitfield.disp32s
3795 || i.types[op].bitfield.disp16)
91d6fa6a 3796 && fits_in_signed_byte (op_disp))
40fb9820 3797 i.types[op].bitfield.disp8 = 1;
252b5132 3798 }
67a4f2b7
AO		 3799 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3800 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3801 {
3802 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3803 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3804 i.types[op].bitfield.disp8 = 0;
3805 i.types[op].bitfield.disp16 = 0;
3806 i.types[op].bitfield.disp32 = 0;
3807 i.types[op].bitfield.disp32s = 0;
3808 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3809 }
3810 else
b300c311 3811 /* We only support 64bit displacement on constants. */
40fb9820 3812 i.types[op].bitfield.disp64 = 0;
252b5132 3813 }
29b0f896
AM		 3814}
3815
43f3e2ee 3816/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3817 operand types. */
3818
3819static int
3820VEX_check_operands (const insn_template *t)
3821{
3822 if (!t->opcode_modifier.vex)
3823 return 0;
3824
3825 /* Only check VEX_Imm4, which must be the first operand. */
3826 if (t->operand_types[0].bitfield.vec_imm4)
3827 {
3828 if (i.op[0].imms->X_op != O_constant
3829 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3830 {
a65babc9 3831 i.error = bad_imm4;
891edac4
L		 3832 return 1;
3833 }
a683cc34
SP		 3834
3835 /* Turn off Imm8 so that update_imm won't complain. */
3836 i.types[0] = vec_imm4;
3837 }
3838
3839 return 0;
3840}
3841
d3ce72d0 3842static const insn_template *
e3bb37b5 3843match_template (void)
29b0f896
AM		 3844{
3845 /* Points to template once we've found it. */
d3ce72d0 3846 const insn_template *t;
40fb9820 3847 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3848 i386_operand_type overlap4;
29b0f896 3849 unsigned int found_reverse_match;
40fb9820
L		 3850 i386_opcode_modifier suffix_check;
3851 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3852 int addr_prefix_disp;
a5c311ca 3853 unsigned int j;
3629bb00 3854 unsigned int found_cpu_match;
45664ddb 3855 unsigned int check_register;
29b0f896 3856
c0f3af97
L		 3857#if MAX_OPERANDS != 5
3858# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3859#endif
3860
29b0f896 3861 found_reverse_match = 0;
539e75ad 3862 addr_prefix_disp = -1;
40fb9820
L		 3863
3864 memset (&suffix_check, 0, sizeof (suffix_check));
3865 if (i.suffix == BYTE_MNEM_SUFFIX)
3866 suffix_check.no_bsuf = 1;
3867 else if (i.suffix == WORD_MNEM_SUFFIX)
3868 suffix_check.no_wsuf = 1;
3869 else if (i.suffix == SHORT_MNEM_SUFFIX)
3870 suffix_check.no_ssuf = 1;
3871 else if (i.suffix == LONG_MNEM_SUFFIX)
3872 suffix_check.no_lsuf = 1;
3873 else if (i.suffix == QWORD_MNEM_SUFFIX)
3874 suffix_check.no_qsuf = 1;
3875 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3876 suffix_check.no_ldsuf = 1;
29b0f896 3877
01559ecc
L		 3878 /* Must have right number of operands. */
3879 i.error = number_of_operands_mismatch;
3880
45aa61fe 3881 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3882 {
539e75ad
L		 3883 addr_prefix_disp = -1;
3884
29b0f896
AM		 3885 if (i.operands != t->operands)
3886 continue;
3887
50aecf8c 3888 /* Check processor support. */
a65babc9 3889 i.error = unsupported;
c0f3af97
L		 3890 found_cpu_match = (cpu_flags_match (t)
3891 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3892 if (!found_cpu_match)
3893 continue;
3894
e1d4d893 3895 /* Check old gcc support. */
a65babc9 3896 i.error = old_gcc_only;
e1d4d893
L		 3897 if (!old_gcc && t->opcode_modifier.oldgcc)
3898 continue;
3899
3900 /* Check AT&T mnemonic. */
a65babc9 3901 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3902 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3903 continue;
3904
891edac4 3905 /* Check AT&T/Intel syntax. */
a65babc9 3906 i.error = unsupported_syntax;
5c07affc
L		 3907 if ((intel_syntax && t->opcode_modifier.attsyntax)
3908 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3909 continue;
3910
20592a94 3911 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3912 i.error = invalid_instruction_suffix;
567e4e96
L		 3913 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3914 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3915 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3916 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3917 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3918 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3919 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3920 continue;
3921
5c07affc 3922 if (!operand_size_match (t))
7d5e4556 3923 continue;
539e75ad 3924
5c07affc
L		 3925 for (j = 0; j < MAX_OPERANDS; j++)
3926 operand_types[j] = t->operand_types[j];
3927
45aa61fe
AM		 3928 /* In general, don't allow 64-bit operands in 32-bit mode. */
3929 if (i.suffix == QWORD_MNEM_SUFFIX
3930 && flag_code != CODE_64BIT
3931 && (intel_syntax
40fb9820 3932 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3933 && !intel_float_operand (t->name))
3934 : intel_float_operand (t->name) != 2)
40fb9820 3935 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3936 && !operand_types[0].bitfield.regxmm
3937 && !operand_types[0].bitfield.regymm)
40fb9820 3938 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3939 && !!operand_types[t->operands > 1].bitfield.regxmm
3940 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3941 && (t->base_opcode != 0x0fc7
3942 || t->extension_opcode != 1 /* cmpxchg8b */))
3943 continue;
3944
192dc9c6
JB		 3945 /* In general, don't allow 32-bit operands on pre-386. */
3946 else if (i.suffix == LONG_MNEM_SUFFIX
3947 && !cpu_arch_flags.bitfield.cpui386
3948 && (intel_syntax
3949 ? (!t->opcode_modifier.ignoresize
3950 && !intel_float_operand (t->name))
3951 : intel_float_operand (t->name) != 2)
3952 && ((!operand_types[0].bitfield.regmmx
3953 && !operand_types[0].bitfield.regxmm)
3954 || (!operand_types[t->operands > 1].bitfield.regmmx
3955 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3956 continue;
3957
29b0f896 3958 /* Do not verify operands when there are none. */
50aecf8c 3959 else
29b0f896 3960 {
c6fb90c8 3961 if (!t->operands)
2dbab7d5
L		 3962 /* We've found a match; break out of loop. */
3963 break;
29b0f896 3964 }
252b5132 3965
539e75ad
L		 3966 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3967 into Disp32/Disp16/Disp32 operand. */
3968 if (i.prefix[ADDR_PREFIX] != 0)
3969 {
40fb9820 3970 /* There should be only one Disp operand. */
539e75ad
L		 3971 switch (flag_code)
3972 {
3973 case CODE_16BIT:
40fb9820
L		 3974 for (j = 0; j < MAX_OPERANDS; j++)
3975 {
3976 if (operand_types[j].bitfield.disp16)
3977 {
3978 addr_prefix_disp = j;
3979 operand_types[j].bitfield.disp32 = 1;
3980 operand_types[j].bitfield.disp16 = 0;
3981 break;
3982 }
3983 }
539e75ad
L		 3984 break;
3985 case CODE_32BIT:
40fb9820
L		 3986 for (j = 0; j < MAX_OPERANDS; j++)
3987 {
3988 if (operand_types[j].bitfield.disp32)
3989 {
3990 addr_prefix_disp = j;
3991 operand_types[j].bitfield.disp32 = 0;
3992 operand_types[j].bitfield.disp16 = 1;
3993 break;
3994 }
3995 }
539e75ad
L		 3996 break;
3997 case CODE_64BIT:
40fb9820
L		 3998 for (j = 0; j < MAX_OPERANDS; j++)
3999 {
4000 if (operand_types[j].bitfield.disp64)
4001 {
4002 addr_prefix_disp = j;
4003 operand_types[j].bitfield.disp64 = 0;
4004 operand_types[j].bitfield.disp32 = 1;
4005 break;
4006 }
4007 }
539e75ad
L		 4008 break;
4009 }
539e75ad
L		 4010 }
4011
56ffb741
L		 4012 /* We check register size if needed. */
4013 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4014 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4015 switch (t->operands)
4016 {
4017 case 1:
40fb9820 4018 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4019 continue;
4020 break;
4021 case 2:
8b38ad71
L		 4022 /* xchg %eax, %eax is a special case. It is an aliase for nop
4023 only in 32bit mode and we can use opcode 0x90. In 64bit
4024 mode, we can't use 0x90 for xchg %eax, %eax since it should
4025 zero-extend %eax to %rax. */
4026 if (flag_code == CODE_64BIT
4027 && t->base_opcode == 0x90
0dfbf9d7
L		 4028 && operand_type_equal (&i.types [0], &acc32)
4029 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4030 continue;
b6169b20
L		 4031 if (i.swap_operand)
4032 {
4033 /* If we swap operand in encoding, we either match
4034 the next one or reverse direction of operands. */
4035 if (t->opcode_modifier.s)
4036 continue;
4037 else if (t->opcode_modifier.d)
4038 goto check_reverse;
4039 }
4040
29b0f896 4041 case 3:
fa99fab2
L		 4042 /* If we swap operand in encoding, we match the next one. */
4043 if (i.swap_operand && t->opcode_modifier.s)
4044 continue;
f48ff2ae 4045 case 4:
c0f3af97 4046 case 5:
c6fb90c8 4047 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4048 if (!operand_type_match (overlap0, i.types[0])
4049 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4050 || (check_register
4051 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4052 operand_types[0],
4053 overlap1, i.types[1],
4054 operand_types[1])))
29b0f896
AM		 4055 {
4056 /* Check if other direction is valid ... */
40fb9820 4057 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4058 continue;
4059
b6169b20 4060check_reverse:
29b0f896 4061 /* Try reversing direction of operands. */
c6fb90c8
L		 4062 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4063 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4064 if (!operand_type_match (overlap0, i.types[0])
4065 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4066 || (check_register
4067 && !operand_type_register_match (overlap0,
4068 i.types[0],
4069 operand_types[1],
4070 overlap1,
4071 i.types[1],
4072 operand_types[0])))
29b0f896
AM		 4073 {
4074 /* Does not match either direction. */
4075 continue;
4076 }
4077 /* found_reverse_match holds which of D or FloatDR
4078 we've found. */
40fb9820 4079 if (t->opcode_modifier.d)
8a2ed489 4080 found_reverse_match = Opcode_D;
40fb9820 4081 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4082 found_reverse_match = Opcode_FloatD;
4083 else
4084 found_reverse_match = 0;
40fb9820 4085 if (t->opcode_modifier.floatr)
8a2ed489 4086 found_reverse_match |= Opcode_FloatR;
29b0f896 4087 }
f48ff2ae 4088 else
29b0f896 4089 {
f48ff2ae 4090 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4091 switch (t->operands)
4092 {
c0f3af97
L		 4093 case 5:
4094 overlap4 = operand_type_and (i.types[4],
4095 operand_types[4]);
d1cbb4db 4096 case 4:
c6fb90c8
L		 4097 overlap3 = operand_type_and (i.types[3],
4098 operand_types[3]);
d1cbb4db 4099 case 3:
c6fb90c8
L		 4100 overlap2 = operand_type_and (i.types[2],
4101 operand_types[2]);
d1cbb4db
L		 4102 break;
4103 }
29b0f896 4104
f48ff2ae
L		 4105 switch (t->operands)
4106 {
c0f3af97
L		 4107 case 5:
4108 if (!operand_type_match (overlap4, i.types[4])
4109 || !operand_type_register_match (overlap3,
4110 i.types[3],
4111 operand_types[3],
4112 overlap4,
4113 i.types[4],
4114 operand_types[4]))
4115 continue;
f48ff2ae 4116 case 4:
40fb9820 4117 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4118 || (check_register
4119 && !operand_type_register_match (overlap2,
4120 i.types[2],
4121 operand_types[2],
4122 overlap3,
4123 i.types[3],
4124 operand_types[3])))
f48ff2ae
L		 4125 continue;
4126 case 3:
4127 /* Here we make use of the fact that there are no
4128 reverse match 3 operand instructions, and all 3
4129 operand instructions only need to be checked for
4130 register consistency between operands 2 and 3. */
40fb9820 4131 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4132 || (check_register
4133 && !operand_type_register_match (overlap1,
4134 i.types[1],
4135 operand_types[1],
4136 overlap2,
4137 i.types[2],
4138 operand_types[2])))
f48ff2ae
L		 4139 continue;
4140 break;
4141 }
29b0f896 4142 }
f48ff2ae 4143 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4144 slip through to break. */
4145 }
3629bb00 4146 if (!found_cpu_match)
29b0f896
AM		 4147 {
4148 found_reverse_match = 0;
4149 continue;
4150 }
c0f3af97 4151
a683cc34
SP		 4152 /* Check if VEX operands are valid. */
4153 if (VEX_check_operands (t))
4154 continue;
4155
29b0f896
AM		 4156 /* We've found a match; break out of loop. */
4157 break;
4158 }
4159
4160 if (t == current_templates->end)
4161 {
4162 /* We found no match. */
a65babc9
L		 4163 const char *err_msg;
4164 switch (i.error)
4165 {
4166 default:
4167 abort ();
86e026a4 4168 case operand_size_mismatch:
a65babc9
L		 4169 err_msg = _("operand size mismatch");
4170 break;
4171 case operand_type_mismatch:
4172 err_msg = _("operand type mismatch");
4173 break;
4174 case register_type_mismatch:
4175 err_msg = _("register type mismatch");
4176 break;
4177 case number_of_operands_mismatch:
4178 err_msg = _("number of operands mismatch");
4179 break;
4180 case invalid_instruction_suffix:
4181 err_msg = _("invalid instruction suffix");
4182 break;
4183 case bad_imm4:
4184 err_msg = _("Imm4 isn't the first operand");
4185 break;
4186 case old_gcc_only:
4187 err_msg = _("only supported with old gcc");
4188 break;
4189 case unsupported_with_intel_mnemonic:
4190 err_msg = _("unsupported with Intel mnemonic");
4191 break;
4192 case unsupported_syntax:
4193 err_msg = _("unsupported syntax");
4194 break;
4195 case unsupported:
4196 err_msg = _("unsupported");
4197 break;
4198 }
4199 as_bad (_("%s for `%s'"), err_msg,
891edac4 4200 current_templates->start->name);
fa99fab2 4201 return NULL;
29b0f896 4202 }
252b5132 4203
29b0f896
AM		 4204 if (!quiet_warnings)
4205 {
4206 if (!intel_syntax
40fb9820
L		 4207 && (i.types[0].bitfield.jumpabsolute
4208 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4209 {
4210 as_warn (_("indirect %s without `*'"), t->name);
4211 }
4212
40fb9820
L		 4213 if (t->opcode_modifier.isprefix
4214 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4215 {
4216 /* Warn them that a data or address size prefix doesn't
4217 affect assembly of the next line of code. */
4218 as_warn (_("stand-alone `%s' prefix"), t->name);
4219 }
4220 }
4221
4222 /* Copy the template we found. */
4223 i.tm = *t;
539e75ad
L		 4224
4225 if (addr_prefix_disp != -1)
4226 i.tm.operand_types[addr_prefix_disp]
4227 = operand_types[addr_prefix_disp];
4228
29b0f896
AM		 4229 if (found_reverse_match)
4230 {
4231 /* If we found a reverse match we must alter the opcode
4232 direction bit. found_reverse_match holds bits to change
4233 (different for int & float insns). */
4234
4235 i.tm.base_opcode ^= found_reverse_match;
4236
539e75ad
L		 4237 i.tm.operand_types[0] = operand_types[1];
4238 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4239 }
4240
fa99fab2 4241 return t;
29b0f896
AM		 4242}
4243
4244static int
e3bb37b5 4245check_string (void)
29b0f896 4246{
40fb9820
L		 4247 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4248 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4249 {
4250 if (i.seg[0] != NULL && i.seg[0] != &es)
4251 {
a87af027 4252 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4253 i.tm.name,
a87af027
JB		 4254 mem_op + 1,
4255 register_prefix);
29b0f896
AM		 4256 return 0;
4257 }
4258 /* There's only ever one segment override allowed per instruction.
4259 This instruction possibly has a legal segment override on the
4260 second operand, so copy the segment to where non-string
4261 instructions store it, allowing common code. */
4262 i.seg[0] = i.seg[1];
4263 }
40fb9820 4264 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4265 {
4266 if (i.seg[1] != NULL && i.seg[1] != &es)
4267 {
a87af027 4268 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4269 i.tm.name,
a87af027
JB		 4270 mem_op + 2,
4271 register_prefix);
29b0f896
AM		 4272 return 0;
4273 }
4274 }
4275 return 1;
4276}
4277
4278static int
543613e9 4279process_suffix (void)
29b0f896
AM		 4280{
4281 /* If matched instruction specifies an explicit instruction mnemonic
4282 suffix, use it. */
40fb9820
L		 4283 if (i.tm.opcode_modifier.size16)
4284 i.suffix = WORD_MNEM_SUFFIX;
4285 else if (i.tm.opcode_modifier.size32)
4286 i.suffix = LONG_MNEM_SUFFIX;
4287 else if (i.tm.opcode_modifier.size64)
4288 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4289 else if (i.reg_operands)
4290 {
4291 /* If there's no instruction mnemonic suffix we try to invent one
4292 based on register operands. */
4293 if (!i.suffix)
4294 {
4295 /* We take i.suffix from the last register operand specified,
4296 Destination register type is more significant than source
381d071f
L		 4297 register type. crc32 in SSE4.2 prefers source register
4298 type. */
4299 if (i.tm.base_opcode == 0xf20f38f1)
4300 {
40fb9820
L		 4301 if (i.types[0].bitfield.reg16)
4302 i.suffix = WORD_MNEM_SUFFIX;
4303 else if (i.types[0].bitfield.reg32)
4304 i.suffix = LONG_MNEM_SUFFIX;
4305 else if (i.types[0].bitfield.reg64)
4306 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4307 }
9344ff29 4308 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4309 {
40fb9820 4310 if (i.types[0].bitfield.reg8)
20592a94
L		 4311 i.suffix = BYTE_MNEM_SUFFIX;
4312 }
381d071f
L		 4313
4314 if (!i.suffix)
4315 {
4316 int op;
4317
20592a94
L		 4318 if (i.tm.base_opcode == 0xf20f38f1
4319 || i.tm.base_opcode == 0xf20f38f0)
4320 {
4321 /* We have to know the operand size for crc32. */
4322 as_bad (_("ambiguous memory operand size for `%s`"),
4323 i.tm.name);
4324 return 0;
4325 }
4326
381d071f 4327 for (op = i.operands; --op >= 0;)
40fb9820 4328 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4329 {
40fb9820
L		 4330 if (i.types[op].bitfield.reg8)
4331 {
4332 i.suffix = BYTE_MNEM_SUFFIX;
4333 break;
4334 }
4335 else if (i.types[op].bitfield.reg16)
4336 {
4337 i.suffix = WORD_MNEM_SUFFIX;
4338 break;
4339 }
4340 else if (i.types[op].bitfield.reg32)
4341 {
4342 i.suffix = LONG_MNEM_SUFFIX;
4343 break;
4344 }
4345 else if (i.types[op].bitfield.reg64)
4346 {
4347 i.suffix = QWORD_MNEM_SUFFIX;
4348 break;
4349 }
381d071f
L		 4350 }
4351 }
29b0f896
AM		 4352 }
4353 else if (i.suffix == BYTE_MNEM_SUFFIX)
4354 {
2eb952a4
L		 4355 if (intel_syntax
4356 && i.tm.opcode_modifier.ignoresize
4357 && i.tm.opcode_modifier.no_bsuf)
4358 i.suffix = 0;
4359 else if (!check_byte_reg ())
29b0f896
AM		 4360 return 0;
4361 }
4362 else if (i.suffix == LONG_MNEM_SUFFIX)
4363 {
2eb952a4
L		 4364 if (intel_syntax
4365 && i.tm.opcode_modifier.ignoresize
4366 && i.tm.opcode_modifier.no_lsuf)
4367 i.suffix = 0;
4368 else if (!check_long_reg ())
29b0f896
AM		 4369 return 0;
4370 }
4371 else if (i.suffix == QWORD_MNEM_SUFFIX)
4372 {
955e1e6a
L		 4373 if (intel_syntax
4374 && i.tm.opcode_modifier.ignoresize
4375 && i.tm.opcode_modifier.no_qsuf)
4376 i.suffix = 0;
4377 else if (!check_qword_reg ())
29b0f896
AM		 4378 return 0;
4379 }
4380 else if (i.suffix == WORD_MNEM_SUFFIX)
4381 {
2eb952a4
L		 4382 if (intel_syntax
4383 && i.tm.opcode_modifier.ignoresize
4384 && i.tm.opcode_modifier.no_wsuf)
4385 i.suffix = 0;
4386 else if (!check_word_reg ())
29b0f896
AM		 4387 return 0;
4388 }
c0f3af97
L		 4389 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4390 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4391 {
c0f3af97 4392 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4393 should check if it is a valid suffix. */
4394 }
40fb9820 4395 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4396 /* Do nothing if the instruction is going to ignore the prefix. */
4397 ;
4398 else
4399 abort ();
4400 }
40fb9820 4401 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4402 && !i.suffix
4403 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4404 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4405 {
4406 i.suffix = stackop_size;
4407 }
9306ca4a
JB		 4408 else if (intel_syntax
4409 && !i.suffix
40fb9820
L		 4410 && (i.tm.operand_types[0].bitfield.jumpabsolute
4411 || i.tm.opcode_modifier.jumpbyte
4412 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4413 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4414 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4415 {
4416 switch (flag_code)
4417 {
4418 case CODE_64BIT:
40fb9820 4419 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4420 {
4421 i.suffix = QWORD_MNEM_SUFFIX;
4422 break;
4423 }
4424 case CODE_32BIT:
40fb9820 4425 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4426 i.suffix = LONG_MNEM_SUFFIX;
4427 break;
4428 case CODE_16BIT:
40fb9820 4429 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4430 i.suffix = WORD_MNEM_SUFFIX;
4431 break;
4432 }
4433 }
252b5132 4434
9306ca4a 4435 if (!i.suffix)
29b0f896 4436 {
9306ca4a
JB		 4437 if (!intel_syntax)
4438 {
40fb9820 4439 if (i.tm.opcode_modifier.w)
9306ca4a 4440 {
4eed87de
AM		 4441 as_bad (_("no instruction mnemonic suffix given and "
4442 "no register operands; can't size instruction"));
9306ca4a
JB		 4443 return 0;
4444 }
4445 }
4446 else
4447 {
40fb9820 4448 unsigned int suffixes;
7ab9ffdd 4449
40fb9820
L		 4450 suffixes = !i.tm.opcode_modifier.no_bsuf;
4451 if (!i.tm.opcode_modifier.no_wsuf)
4452 suffixes |= 1 << 1;
4453 if (!i.tm.opcode_modifier.no_lsuf)
4454 suffixes |= 1 << 2;
fc4adea1 4455 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4456 suffixes |= 1 << 3;
4457 if (!i.tm.opcode_modifier.no_ssuf)
4458 suffixes |= 1 << 4;
4459 if (!i.tm.opcode_modifier.no_qsuf)
4460 suffixes |= 1 << 5;
4461
4462 /* There are more than suffix matches. */
4463 if (i.tm.opcode_modifier.w
9306ca4a 4464 || ((suffixes & (suffixes - 1))
40fb9820
L		 4465 && !i.tm.opcode_modifier.defaultsize
4466 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4467 {
4468 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4469 return 0;
4470 }
4471 }
29b0f896 4472 }
252b5132 4473
9306ca4a
JB		 4474 /* Change the opcode based on the operand size given by i.suffix;
4475 We don't need to change things for byte insns. */
4476
582d5edd
L		 4477 if (i.suffix
4478 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4479 && i.suffix != XMMWORD_MNEM_SUFFIX
4480 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4481 {
4482 /* It's not a byte, select word/dword operation. */
40fb9820 4483 if (i.tm.opcode_modifier.w)
29b0f896 4484 {
40fb9820 4485 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4486 i.tm.base_opcode |= 8;
4487 else
4488 i.tm.base_opcode |= 1;
4489 }
0f3f3d8b 4490
29b0f896
AM		 4491 /* Now select between word & dword operations via the operand
4492 size prefix, except for instructions that will ignore this
4493 prefix anyway. */
ca61edf2 4494 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4495 {
ca61edf2
L		 4496 /* The address size override prefix changes the size of the
4497 first operand. */
40fb9820
L		 4498 if ((flag_code == CODE_32BIT
4499 && i.op->regs[0].reg_type.bitfield.reg16)
4500 || (flag_code != CODE_32BIT
4501 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4502 if (!add_prefix (ADDR_PREFIX_OPCODE))
4503 return 0;
4504 }
4505 else if (i.suffix != QWORD_MNEM_SUFFIX
4506 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4507 && !i.tm.opcode_modifier.ignoresize
4508 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4509 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4510 || (flag_code == CODE_64BIT
40fb9820 4511 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4512 {
4513 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4514
40fb9820 4515 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4516 prefix = ADDR_PREFIX_OPCODE;
252b5132 4517
29b0f896
AM		 4518 if (!add_prefix (prefix))
4519 return 0;
24eab124 4520 }
252b5132 4521
29b0f896
AM		 4522 /* Set mode64 for an operand. */
4523 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4524 && flag_code == CODE_64BIT
40fb9820 4525 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4526 {
4527 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4528 need rex64. cmpxchg8b is also a special case. */
4529 if (! (i.operands == 2
4530 && i.tm.base_opcode == 0x90
4531 && i.tm.extension_opcode == None
0dfbf9d7
L		 4532 && operand_type_equal (&i.types [0], &acc64)
4533 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4534 && ! (i.operands == 1
4535 && i.tm.base_opcode == 0xfc7
4536 && i.tm.extension_opcode == 1
40fb9820
L		 4537 && !operand_type_check (i.types [0], reg)
4538 && operand_type_check (i.types [0], anymem)))
f6bee062 4539 i.rex |= REX_W;
46e883c5 4540 }
3e73aa7c 4541
29b0f896
AM		 4542 /* Size floating point instruction. */
4543 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4544 if (i.tm.opcode_modifier.floatmf)
543613e9 4545 i.tm.base_opcode ^= 4;
29b0f896 4546 }
7ecd2f8b 4547
29b0f896
AM		 4548 return 1;
4549}
3e73aa7c 4550
29b0f896 4551static int
543613e9 4552check_byte_reg (void)
29b0f896
AM		 4553{
4554 int op;
543613e9 4555
29b0f896
AM		 4556 for (op = i.operands; --op >= 0;)
4557 {
4558 /* If this is an eight bit register, it's OK. If it's the 16 or
4559 32 bit version of an eight bit register, we will just use the
4560 low portion, and that's OK too. */
40fb9820 4561 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4562 continue;
4563
9344ff29
L		 4564 /* crc32 doesn't generate this warning. */
4565 if (i.tm.base_opcode == 0xf20f38f0)
4566 continue;
4567
40fb9820
L		 4568 if ((i.types[op].bitfield.reg16
4569 || i.types[op].bitfield.reg32
4570 || i.types[op].bitfield.reg64)
4571 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4572 {
4573 /* Prohibit these changes in the 64bit mode, since the
4574 lowering is more complicated. */
4575 if (flag_code == CODE_64BIT
40fb9820 4576 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4577 {
2ca3ace5
L		 4578 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4579 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4580 i.suffix);
4581 return 0;
4582 }
4583#if REGISTER_WARNINGS
4584 if (!quiet_warnings
40fb9820 4585 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4586 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4587 register_prefix,
40fb9820 4588 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4589 ? REGNAM_AL - REGNAM_AX
4590 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4591 register_prefix,
29b0f896
AM		 4592 i.op[op].regs->reg_name,
4593 i.suffix);
4594#endif
4595 continue;
4596 }
4597 /* Any other register is bad. */
40fb9820
L		 4598 if (i.types[op].bitfield.reg16
4599 || i.types[op].bitfield.reg32
4600 || i.types[op].bitfield.reg64
4601 || i.types[op].bitfield.regmmx
4602 || i.types[op].bitfield.regxmm
c0f3af97 4603 || i.types[op].bitfield.regymm
40fb9820
L		 4604 || i.types[op].bitfield.sreg2
4605 || i.types[op].bitfield.sreg3
4606 || i.types[op].bitfield.control
4607 || i.types[op].bitfield.debug
4608 || i.types[op].bitfield.test
4609 || i.types[op].bitfield.floatreg
4610 || i.types[op].bitfield.floatacc)
29b0f896 4611 {
a540244d
L		 4612 as_bad (_("`%s%s' not allowed with `%s%c'"),
4613 register_prefix,
29b0f896
AM		 4614 i.op[op].regs->reg_name,
4615 i.tm.name,
4616 i.suffix);
4617 return 0;
4618 }
4619 }
4620 return 1;
4621}
4622
4623static int
e3bb37b5 4624check_long_reg (void)
29b0f896
AM		 4625{
4626 int op;
4627
4628 for (op = i.operands; --op >= 0;)
4629 /* Reject eight bit registers, except where the template requires
4630 them. (eg. movzb) */
40fb9820
L		 4631 if (i.types[op].bitfield.reg8
4632 && (i.tm.operand_types[op].bitfield.reg16
4633 || i.tm.operand_types[op].bitfield.reg32
4634 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4635 {
a540244d
L		 4636 as_bad (_("`%s%s' not allowed with `%s%c'"),
4637 register_prefix,
29b0f896
AM		 4638 i.op[op].regs->reg_name,
4639 i.tm.name,
4640 i.suffix);
4641 return 0;
4642 }
4643 /* Warn if the e prefix on a general reg is missing. */
4644 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4645 && i.types[op].bitfield.reg16
4646 && (i.tm.operand_types[op].bitfield.reg32
4647 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4648 {
4649 /* Prohibit these changes in the 64bit mode, since the
4650 lowering is more complicated. */
4651 if (flag_code == CODE_64BIT)
252b5132 4652 {
2ca3ace5
L		 4653 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4654 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4655 i.suffix);
4656 return 0;
252b5132 4657 }
29b0f896
AM		 4658#if REGISTER_WARNINGS
4659 else
a540244d
L		 4660 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4661 register_prefix,
29b0f896 4662 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4663 register_prefix,
29b0f896
AM		 4664 i.op[op].regs->reg_name,
4665 i.suffix);
4666#endif
252b5132 4667 }
29b0f896 4668 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4669 else if (i.types[op].bitfield.reg64
4670 && (i.tm.operand_types[op].bitfield.reg32
4671 || i.tm.operand_types[op].bitfield.acc))
252b5132 4672 {
34828aad 4673 if (intel_syntax
ca61edf2 4674 && i.tm.opcode_modifier.toqword
40fb9820 4675 && !i.types[0].bitfield.regxmm)
34828aad 4676 {
ca61edf2 4677 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4678 i.suffix = QWORD_MNEM_SUFFIX;
4679 }
4680 else
4681 {
4682 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4683 register_prefix, i.op[op].regs->reg_name,
4684 i.suffix);
4685 return 0;
4686 }
29b0f896
AM		 4687 }
4688 return 1;
4689}
252b5132 4690
29b0f896 4691static int
e3bb37b5 4692check_qword_reg (void)
29b0f896
AM		 4693{
4694 int op;
252b5132 4695
29b0f896
AM		 4696 for (op = i.operands; --op >= 0; )
4697 /* Reject eight bit registers, except where the template requires
4698 them. (eg. movzb) */
40fb9820
L		 4699 if (i.types[op].bitfield.reg8
4700 && (i.tm.operand_types[op].bitfield.reg16
4701 || i.tm.operand_types[op].bitfield.reg32
4702 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4703 {
a540244d
L		 4704 as_bad (_("`%s%s' not allowed with `%s%c'"),
4705 register_prefix,
29b0f896
AM		 4706 i.op[op].regs->reg_name,
4707 i.tm.name,
4708 i.suffix);
4709 return 0;
4710 }
4711 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4712 else if ((i.types[op].bitfield.reg16
4713 || i.types[op].bitfield.reg32)
4714 && (i.tm.operand_types[op].bitfield.reg32
4715 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4716 {
4717 /* Prohibit these changes in the 64bit mode, since the
4718 lowering is more complicated. */
34828aad 4719 if (intel_syntax
ca61edf2 4720 && i.tm.opcode_modifier.todword
40fb9820 4721 && !i.types[0].bitfield.regxmm)
34828aad 4722 {
ca61edf2 4723 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4724 i.suffix = LONG_MNEM_SUFFIX;
4725 }
4726 else
4727 {
4728 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4729 register_prefix, i.op[op].regs->reg_name,
4730 i.suffix);
4731 return 0;
4732 }
252b5132 4733 }
29b0f896
AM		 4734 return 1;
4735}
252b5132 4736
29b0f896 4737static int
e3bb37b5 4738check_word_reg (void)
29b0f896
AM		 4739{
4740 int op;
4741 for (op = i.operands; --op >= 0;)
4742 /* Reject eight bit registers, except where the template requires
4743 them. (eg. movzb) */
40fb9820
L		 4744 if (i.types[op].bitfield.reg8
4745 && (i.tm.operand_types[op].bitfield.reg16
4746 || i.tm.operand_types[op].bitfield.reg32
4747 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4748 {
a540244d
L		 4749 as_bad (_("`%s%s' not allowed with `%s%c'"),
4750 register_prefix,
29b0f896
AM		 4751 i.op[op].regs->reg_name,
4752 i.tm.name,
4753 i.suffix);
4754 return 0;
4755 }
4756 /* Warn if the e prefix on a general reg is present. */
4757 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4758 && i.types[op].bitfield.reg32
4759 && (i.tm.operand_types[op].bitfield.reg16
4760 || i.tm.operand_types[op].bitfield.acc))
252b5132 4761 {
29b0f896
AM		 4762 /* Prohibit these changes in the 64bit mode, since the
4763 lowering is more complicated. */
4764 if (flag_code == CODE_64BIT)
252b5132 4765 {
2ca3ace5
L		 4766 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4767 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4768 i.suffix);
4769 return 0;
252b5132 4770 }
29b0f896
AM		 4771 else
4772#if REGISTER_WARNINGS
a540244d
L		 4773 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4774 register_prefix,
29b0f896 4775 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4776 register_prefix,
29b0f896
AM		 4777 i.op[op].regs->reg_name,
4778 i.suffix);
4779#endif
4780 }
4781 return 1;
4782}
252b5132 4783
29b0f896 4784static int
40fb9820 4785update_imm (unsigned int j)
29b0f896 4786{
bc0844ae 4787 i386_operand_type overlap = i.types[j];
40fb9820
L		 4788 if ((overlap.bitfield.imm8
4789 || overlap.bitfield.imm8s
4790 || overlap.bitfield.imm16
4791 || overlap.bitfield.imm32
4792 || overlap.bitfield.imm32s
4793 || overlap.bitfield.imm64)
0dfbf9d7
L		 4794 && !operand_type_equal (&overlap, &imm8)
4795 && !operand_type_equal (&overlap, &imm8s)
4796 && !operand_type_equal (&overlap, &imm16)
4797 && !operand_type_equal (&overlap, &imm32)
4798 && !operand_type_equal (&overlap, &imm32s)
4799 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4800 {
4801 if (i.suffix)
4802 {
40fb9820
L		 4803 i386_operand_type temp;
4804
0dfbf9d7 4805 operand_type_set (&temp, 0);
7ab9ffdd 4806 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4807 {
4808 temp.bitfield.imm8 = overlap.bitfield.imm8;
4809 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4810 }
4811 else if (i.suffix == WORD_MNEM_SUFFIX)
4812 temp.bitfield.imm16 = overlap.bitfield.imm16;
4813 else if (i.suffix == QWORD_MNEM_SUFFIX)
4814 {
4815 temp.bitfield.imm64 = overlap.bitfield.imm64;
4816 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4817 }
4818 else
4819 temp.bitfield.imm32 = overlap.bitfield.imm32;
4820 overlap = temp;
29b0f896 4821 }
0dfbf9d7
L		 4822 else if (operand_type_equal (&overlap, &imm16_32_32s)
4823 || operand_type_equal (&overlap, &imm16_32)
4824 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4825 {
40fb9820 4826 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4827 overlap = imm16;
40fb9820 4828 else
65da13b5 4829 overlap = imm32s;
29b0f896 4830 }
0dfbf9d7
L		 4831 if (!operand_type_equal (&overlap, &imm8)
4832 && !operand_type_equal (&overlap, &imm8s)
4833 && !operand_type_equal (&overlap, &imm16)
4834 && !operand_type_equal (&overlap, &imm32)
4835 && !operand_type_equal (&overlap, &imm32s)
4836 && !operand_type_equal (&overlap, &imm64))
29b0f896 4837 {
4eed87de
AM		 4838 as_bad (_("no instruction mnemonic suffix given; "
4839 "can't determine immediate size"));
29b0f896
AM		 4840 return 0;
4841 }
4842 }
40fb9820 4843 i.types[j] = overlap;
29b0f896 4844
40fb9820
L		 4845 return 1;
4846}
4847
4848static int
4849finalize_imm (void)
4850{
bc0844ae 4851 unsigned int j, n;
29b0f896 4852
bc0844ae
L		 4853 /* Update the first 2 immediate operands. */
4854 n = i.operands > 2 ? 2 : i.operands;
4855 if (n)
4856 {
4857 for (j = 0; j < n; j++)
4858 if (update_imm (j) == 0)
4859 return 0;
40fb9820 4860
bc0844ae
L		 4861 /* The 3rd operand can't be immediate operand. */
4862 gas_assert (operand_type_check (i.types[2], imm) == 0);
4863 }
29b0f896
AM		 4864
4865 return 1;
4866}
4867
c0f3af97
L		 4868static int
4869bad_implicit_operand (int xmm)
4870{
91d6fa6a
NC		 4871 const char *ireg = xmm ? "xmm0" : "ymm0";
4872
c0f3af97
L		 4873 if (intel_syntax)
4874 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4875 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4876 else
4877 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4878 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4879 return 0;
4880}
4881
29b0f896 4882static int
e3bb37b5 4883process_operands (void)
29b0f896
AM		 4884{
4885 /* Default segment register this instruction will use for memory
4886 accesses. 0 means unknown. This is only for optimizing out
4887 unnecessary segment overrides. */
4888 const seg_entry *default_seg = 0;
4889
2426c15f 4890 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4891 {
91d6fa6a
NC		 4892 unsigned int dupl = i.operands;
4893 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4894 unsigned int j;
4895
c0f3af97 4896 /* The destination must be an xmm register. */
9c2799c2 4897 gas_assert (i.reg_operands
91d6fa6a 4898 && MAX_OPERANDS > dupl
7ab9ffdd 4899 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4900
4901 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4902 {
c0f3af97 4903 /* The first operand is implicit and must be xmm0. */
9c2799c2 4904 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4905 if (i.op[0].regs->reg_num != 0)
4906 return bad_implicit_operand (1);
4907
8cd7925b 4908 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4909 {
4910 /* Keep xmm0 for instructions with VEX prefix and 3
4911 sources. */
4912 goto duplicate;
4913 }
e2ec9d29 4914 else
c0f3af97
L		 4915 {
4916 /* We remove the first xmm0 and keep the number of
4917 operands unchanged, which in fact duplicates the
4918 destination. */
4919 for (j = 1; j < i.operands; j++)
4920 {
4921 i.op[j - 1] = i.op[j];
4922 i.types[j - 1] = i.types[j];
4923 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4924 }
4925 }
4926 }
4927 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4928 {
91d6fa6a 4929 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4930 && (i.tm.opcode_modifier.vexsources
4931 == VEX3SOURCES));
c0f3af97
L		 4932
4933 /* Add the implicit xmm0 for instructions with VEX prefix
4934 and 3 sources. */
4935 for (j = i.operands; j > 0; j--)
4936 {
4937 i.op[j] = i.op[j - 1];
4938 i.types[j] = i.types[j - 1];
4939 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4940 }
4941 i.op[0].regs
4942 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4943 i.types[0] = regxmm;
c0f3af97
L		 4944 i.tm.operand_types[0] = regxmm;
4945
4946 i.operands += 2;
4947 i.reg_operands += 2;
4948 i.tm.operands += 2;
4949
91d6fa6a 4950 dupl++;
c0f3af97 4951 dest++;
91d6fa6a
NC		 4952 i.op[dupl] = i.op[dest];
4953 i.types[dupl] = i.types[dest];
4954 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4955 }
c0f3af97
L		 4956 else
4957 {
4958duplicate:
4959 i.operands++;
4960 i.reg_operands++;
4961 i.tm.operands++;
4962
91d6fa6a
NC		 4963 i.op[dupl] = i.op[dest];
4964 i.types[dupl] = i.types[dest];
4965 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4966 }
4967
4968 if (i.tm.opcode_modifier.immext)
4969 process_immext ();
4970 }
4971 else if (i.tm.opcode_modifier.firstxmm0)
4972 {
4973 unsigned int j;
4974
4975 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4976 gas_assert (i.reg_operands
7ab9ffdd
L		 4977 && (operand_type_equal (&i.types[0], &regxmm)
4978 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4979 if (i.op[0].regs->reg_num != 0)
4980 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4981
4982 for (j = 1; j < i.operands; j++)
4983 {
4984 i.op[j - 1] = i.op[j];
4985 i.types[j - 1] = i.types[j];
4986
4987 /* We need to adjust fields in i.tm since they are used by
4988 build_modrm_byte. */
4989 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4990 }
4991
e2ec9d29
L		 4992 i.operands--;
4993 i.reg_operands--;
e2ec9d29
L		 4994 i.tm.operands--;
4995 }
4996 else if (i.tm.opcode_modifier.regkludge)
4997 {
4998 /* The imul $imm, %reg instruction is converted into
4999 imul $imm, %reg, %reg, and the clr %reg instruction
5000 is converted into xor %reg, %reg. */
5001
5002 unsigned int first_reg_op;
5003
5004 if (operand_type_check (i.types[0], reg))
5005 first_reg_op = 0;
5006 else
5007 first_reg_op = 1;
5008 /* Pretend we saw the extra register operand. */
9c2799c2 5009 gas_assert (i.reg_operands == 1
7ab9ffdd 5010 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5011 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5012 i.types[first_reg_op + 1] = i.types[first_reg_op];
5013 i.operands++;
5014 i.reg_operands++;
29b0f896
AM		 5015 }
5016
40fb9820 5017 if (i.tm.opcode_modifier.shortform)
29b0f896 5018 {
40fb9820
L		 5019 if (i.types[0].bitfield.sreg2
5020 || i.types[0].bitfield.sreg3)
29b0f896 5021 {
4eed87de
AM		 5022 if (i.tm.base_opcode == POP_SEG_SHORT
5023 && i.op[0].regs->reg_num == 1)
29b0f896 5024 {
a87af027 5025 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5026 return 0;
29b0f896 5027 }
4eed87de
AM		 5028 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5029 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5030 i.rex |= REX_B;
4eed87de
AM		 5031 }
5032 else
5033 {
7ab9ffdd 5034 /* The register or float register operand is in operand
85f10a01 5035 0 or 1. */
40fb9820 5036 unsigned int op;
7ab9ffdd
L		 5037
5038 if (i.types[0].bitfield.floatreg
5039 || operand_type_check (i.types[0], reg))
5040 op = 0;
5041 else
5042 op = 1;
4eed87de
AM		 5043 /* Register goes in low 3 bits of opcode. */
5044 i.tm.base_opcode |= i.op[op].regs->reg_num;
5045 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5046 i.rex |= REX_B;
40fb9820 5047 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5048 {
4eed87de
AM		 5049 /* Warn about some common errors, but press on regardless.
5050 The first case can be generated by gcc (<= 2.8.1). */
5051 if (i.operands == 2)
5052 {
5053 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5054 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5055 register_prefix, i.op[!intel_syntax].regs->reg_name,
5056 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5057 }
5058 else
5059 {
5060 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5061 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5062 register_prefix, i.op[0].regs->reg_name);
4eed87de 5063 }
29b0f896
AM		 5064 }
5065 }
5066 }
40fb9820 5067 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5068 {
5069 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5070 must be put into the modrm byte). Now, we make the modrm and
5071 index base bytes based on all the info we've collected. */
29b0f896
AM		 5072
5073 default_seg = build_modrm_byte ();
5074 }
8a2ed489 5075 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5076 {
5077 default_seg = &ds;
5078 }
40fb9820 5079 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5080 {
5081 /* For the string instructions that allow a segment override
5082 on one of their operands, the default segment is ds. */
5083 default_seg = &ds;
5084 }
5085
75178d9d
L		 5086 if (i.tm.base_opcode == 0x8d /* lea */
5087 && i.seg[0]
5088 && !quiet_warnings)
30123838 5089 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5090
5091 /* If a segment was explicitly specified, and the specified segment
5092 is not the default, use an opcode prefix to select it. If we
5093 never figured out what the default segment is, then default_seg
5094 will be zero at this point, and the specified segment prefix will
5095 always be used. */
29b0f896
AM		 5096 if ((i.seg[0]) && (i.seg[0] != default_seg))
5097 {
5098 if (!add_prefix (i.seg[0]->seg_prefix))
5099 return 0;
5100 }
5101 return 1;
5102}
5103
5104static const seg_entry *
e3bb37b5 5105build_modrm_byte (void)
29b0f896
AM		 5106{
5107 const seg_entry *default_seg = 0;
c0f3af97 5108 unsigned int source, dest;
8cd7925b 5109 int vex_3_sources;
c0f3af97
L		 5110
5111 /* The first operand of instructions with VEX prefix and 3 sources
5112 must be VEX_Imm4. */
8cd7925b 5113 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5114 if (vex_3_sources)
5115 {
91d6fa6a 5116 unsigned int nds, reg_slot;
4c2c6516 5117 expressionS *exp;
c0f3af97 5118
922d8de8 5119 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5120 && i.tm.opcode_modifier.immext)
5121 {
5122 dest = i.operands - 2;
5123 gas_assert (dest == 3);
5124 }
922d8de8 5125 else
a683cc34 5126 dest = i.operands - 1;
c0f3af97 5127 nds = dest - 1;
922d8de8 5128
a683cc34
SP		 5129 /* There are 2 kinds of instructions:
5130 1. 5 operands: 4 register operands or 3 register operands
5131 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5132 VexW0 or VexW1. The destination must be either XMM or YMM
5133 register.
5134 2. 4 operands: 4 register operands or 3 register operands
5135 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5136 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5137 || (i.reg_operands == 3 && i.mem_operands == 1))
5138 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5139 && (i.tm.opcode_modifier.veximmext
5140 || (i.imm_operands == 1
5141 && i.types[0].bitfield.vec_imm4
5142 && (i.tm.opcode_modifier.vexw == VEXW0
5143 || i.tm.opcode_modifier.vexw == VEXW1)
5144 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5145 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5146
5147 if (i.imm_operands == 0)
5148 {
5149 /* When there is no immediate operand, generate an 8bit
5150 immediate operand to encode the first operand. */
5151 exp = &im_expressions[i.imm_operands++];
5152 i.op[i.operands].imms = exp;
5153 i.types[i.operands] = imm8;
5154 i.operands++;
5155 /* If VexW1 is set, the first operand is the source and
5156 the second operand is encoded in the immediate operand. */
5157 if (i.tm.opcode_modifier.vexw == VEXW1)
5158 {
5159 source = 0;
5160 reg_slot = 1;
5161 }
5162 else
5163 {
5164 source = 1;
5165 reg_slot = 0;
5166 }
5167
5168 /* FMA swaps REG and NDS. */
5169 if (i.tm.cpu_flags.bitfield.cpufma)
5170 {
5171 unsigned int tmp;
5172 tmp = reg_slot;
5173 reg_slot = nds;
5174 nds = tmp;
5175 }
5176
24981e7b
L		 5177 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5178 &regxmm)
a683cc34
SP		 5179 || operand_type_equal (&i.tm.operand_types[reg_slot],
5180 &regymm));
5181 exp->X_op = O_constant;
5182 exp->X_add_number
5183 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5184 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5185 << 4);
a683cc34 5186 }
922d8de8 5187 else
a683cc34
SP		 5188 {
5189 unsigned int imm_slot;
5190
5191 if (i.tm.opcode_modifier.vexw == VEXW0)
5192 {
5193 /* If VexW0 is set, the third operand is the source and
5194 the second operand is encoded in the immediate
5195 operand. */
5196 source = 2;
5197 reg_slot = 1;
5198 }
5199 else
5200 {
5201 /* VexW1 is set, the second operand is the source and
5202 the third operand is encoded in the immediate
5203 operand. */
5204 source = 1;
5205 reg_slot = 2;
5206 }
5207
5208 if (i.tm.opcode_modifier.immext)
5209 {
5210 /* When ImmExt is set, the immdiate byte is the last
5211 operand. */
5212 imm_slot = i.operands - 1;
5213 source--;
5214 reg_slot--;
5215 }
5216 else
5217 {
5218 imm_slot = 0;
5219
5220 /* Turn on Imm8 so that output_imm will generate it. */
5221 i.types[imm_slot].bitfield.imm8 = 1;
5222 }
5223
24981e7b
L		 5224 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5225 &regxmm)
5226 || operand_type_equal (&i.tm.operand_types[reg_slot],
5227 &regymm));
a683cc34
SP		 5228 i.op[imm_slot].imms->X_add_number
5229 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5230 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5231 << 4);
a683cc34
SP		 5232 }
5233
5234 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5235 || operand_type_equal (&i.tm.operand_types[nds],
5236 &regymm));
dae39acc 5237 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5238 }
5239 else
5240 source = dest = 0;
29b0f896
AM		 5241
5242 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5243 implicit registers do not count. If there are 3 register
5244 operands, it must be a instruction with VexNDS. For a
5245 instruction with VexNDD, the destination register is encoded
5246 in VEX prefix. If there are 4 register operands, it must be
5247 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5248 if (i.mem_operands == 0
5249 && ((i.reg_operands == 2
2426c15f 5250 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5251 || (i.reg_operands == 3
2426c15f 5252 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5253 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5254 {
cab737b9
L		 5255 switch (i.operands)
5256 {
5257 case 2:
5258 source = 0;
5259 break;
5260 case 3:
c81128dc
L		 5261 /* When there are 3 operands, one of them may be immediate,
5262 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5263 the first operand must be shift count register (cl) or it
5264 is an instruction with VexNDS. */
9c2799c2 5265 gas_assert (i.imm_operands == 1
7ab9ffdd 5266 || (i.imm_operands == 0
2426c15f 5267 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5268 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5269 if (operand_type_check (i.types[0], imm)
5270 || i.types[0].bitfield.shiftcount)
5271 source = 1;
5272 else
5273 source = 0;
cab737b9
L		 5274 break;
5275 case 4:
368d64cc
L		 5276 /* When there are 4 operands, the first two must be 8bit
5277 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5278 one.
5279
5280 For instructions with VexNDS, if the first operand
5281 an imm8, the source operand is the 2nd one. If the last
5282 operand is imm8, the source operand is the first one. */
9c2799c2 5283 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5284 && i.types[0].bitfield.imm8
5285 && i.types[1].bitfield.imm8)
2426c15f 5286 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5287 && i.imm_operands == 1
5288 && (i.types[0].bitfield.imm8
5289 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5290 if (i.imm_operands == 2)
5291 source = 2;
5292 else
c0f3af97
L		 5293 {
5294 if (i.types[0].bitfield.imm8)
5295 source = 1;
5296 else
5297 source = 0;
5298 }
c0f3af97
L		 5299 break;
5300 case 5:
cab737b9
L		 5301 break;
5302 default:
5303 abort ();
5304 }
5305
c0f3af97
L		 5306 if (!vex_3_sources)
5307 {
5308 dest = source + 1;
5309
2426c15f 5310 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5311 {
5312 /* For instructions with VexNDS, the register-only
5313 source operand must be XMM or YMM register. It is
fa99fab2
L		 5314 encoded in VEX prefix. We need to clear RegMem bit
5315 before calling operand_type_equal. */
5316 i386_operand_type op = i.tm.operand_types[dest];
5317 op.bitfield.regmem = 0;
c0f3af97 5318 if ((dest + 1) >= i.operands
fa99fab2
L		 5319 || (!operand_type_equal (&op, &regxmm)
5320 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5321 abort ();
5322 i.vex.register_specifier = i.op[dest].regs;
5323 dest++;
5324 }
5325 }
29b0f896
AM		 5326
5327 i.rm.mode = 3;
5328 /* One of the register operands will be encoded in the i.tm.reg
5329 field, the other in the combined i.tm.mode and i.tm.regmem
5330 fields. If no form of this instruction supports a memory
5331 destination operand, then we assume the source operand may
5332 sometimes be a memory operand and so we need to store the
5333 destination in the i.rm.reg field. */
40fb9820
L		 5334 if (!i.tm.operand_types[dest].bitfield.regmem
5335 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5336 {
5337 i.rm.reg = i.op[dest].regs->reg_num;
5338 i.rm.regmem = i.op[source].regs->reg_num;
5339 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5340 i.rex |= REX_R;
29b0f896 5341 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5342 i.rex |= REX_B;
29b0f896
AM		 5343 }
5344 else
5345 {
5346 i.rm.reg = i.op[source].regs->reg_num;
5347 i.rm.regmem = i.op[dest].regs->reg_num;
5348 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5349 i.rex |= REX_B;
29b0f896 5350 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5351 i.rex |= REX_R;
29b0f896 5352 }
161a04f6 5353 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5354 {
40fb9820
L		 5355 if (!i.types[0].bitfield.control
5356 && !i.types[1].bitfield.control)
c4a530c5 5357 abort ();
161a04f6 5358 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5359 add_prefix (LOCK_PREFIX_OPCODE);
5360 }
29b0f896
AM		 5361 }
5362 else
5363 { /* If it's not 2 reg operands... */
c0f3af97
L		 5364 unsigned int mem;
5365
29b0f896
AM		 5366 if (i.mem_operands)
5367 {
5368 unsigned int fake_zero_displacement = 0;
99018f42 5369 unsigned int op;
4eed87de 5370
7ab9ffdd
L		 5371 for (op = 0; op < i.operands; op++)
5372 if (operand_type_check (i.types[op], anymem))
5373 break;
7ab9ffdd 5374 gas_assert (op < i.operands);
29b0f896
AM		 5375
5376 default_seg = &ds;
5377
5378 if (i.base_reg == 0)
5379 {
5380 i.rm.mode = 0;
5381 if (!i.disp_operands)
5382 fake_zero_displacement = 1;
5383 if (i.index_reg == 0)
5384 {
5385 /* Operand is just <disp> */
20f0a1fc 5386 if (flag_code == CODE_64BIT)
29b0f896
AM		 5387 {
5388 /* 64bit mode overwrites the 32bit absolute
5389 addressing by RIP relative addressing and
5390 absolute addressing is encoded by one of the
5391 redundant SIB forms. */
5392 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5393 i.sib.base = NO_BASE_REGISTER;
5394 i.sib.index = NO_INDEX_REGISTER;
fc225355 5395 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5396 ? disp32s : disp32);
20f0a1fc 5397 }
fc225355
L		 5398 else if ((flag_code == CODE_16BIT)
5399 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5400 {
5401 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5402 i.types[op] = disp16;
20f0a1fc
NC		 5403 }
5404 else
5405 {
5406 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5407 i.types[op] = disp32;
29b0f896
AM		 5408 }
5409 }
5410 else /* !i.base_reg && i.index_reg */
5411 {
db51cc60
L		 5412 if (i.index_reg->reg_num == RegEiz
5413 || i.index_reg->reg_num == RegRiz)
5414 i.sib.index = NO_INDEX_REGISTER;
5415 else
5416 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5417 i.sib.base = NO_BASE_REGISTER;
5418 i.sib.scale = i.log2_scale_factor;
5419 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5420 i.types[op].bitfield.disp8 = 0;
5421 i.types[op].bitfield.disp16 = 0;
5422 i.types[op].bitfield.disp64 = 0;
29b0f896 5423 if (flag_code != CODE_64BIT)
40fb9820
L		 5424 {
5425 /* Must be 32 bit */
5426 i.types[op].bitfield.disp32 = 1;
5427 i.types[op].bitfield.disp32s = 0;
5428 }
29b0f896 5429 else
40fb9820
L		 5430 {
5431 i.types[op].bitfield.disp32 = 0;
5432 i.types[op].bitfield.disp32s = 1;
5433 }
29b0f896 5434 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5435 i.rex |= REX_X;
29b0f896
AM		 5436 }
5437 }
5438 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5439 else if (i.base_reg->reg_num == RegRip ||
5440 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5441 {
5442 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5443 i.types[op].bitfield.disp8 = 0;
5444 i.types[op].bitfield.disp16 = 0;
5445 i.types[op].bitfield.disp32 = 0;
5446 i.types[op].bitfield.disp32s = 1;
5447 i.types[op].bitfield.disp64 = 0;
71903a11 5448 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5449 if (! i.disp_operands)
5450 fake_zero_displacement = 1;
29b0f896 5451 }
40fb9820 5452 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5453 {
5454 switch (i.base_reg->reg_num)
5455 {
5456 case 3: /* (%bx) */
5457 if (i.index_reg == 0)
5458 i.rm.regmem = 7;
5459 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5460 i.rm.regmem = i.index_reg->reg_num - 6;
5461 break;
5462 case 5: /* (%bp) */
5463 default_seg = &ss;
5464 if (i.index_reg == 0)
5465 {
5466 i.rm.regmem = 6;
40fb9820 5467 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5468 {
5469 /* fake (%bp) into 0(%bp) */
40fb9820 5470 i.types[op].bitfield.disp8 = 1;
252b5132 5471 fake_zero_displacement = 1;
29b0f896
AM		 5472 }
5473 }
5474 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5475 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5476 break;
5477 default: /* (%si) -> 4 or (%di) -> 5 */
5478 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5479 }
5480 i.rm.mode = mode_from_disp_size (i.types[op]);
5481 }
5482 else /* i.base_reg and 32/64 bit mode */
5483 {
5484 if (flag_code == CODE_64BIT
40fb9820
L		 5485 && operand_type_check (i.types[op], disp))
5486 {
5487 i386_operand_type temp;
0dfbf9d7 5488 operand_type_set (&temp, 0);
40fb9820
L		 5489 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5490 i.types[op] = temp;
5491 if (i.prefix[ADDR_PREFIX] == 0)
5492 i.types[op].bitfield.disp32s = 1;
5493 else
5494 i.types[op].bitfield.disp32 = 1;
5495 }
20f0a1fc 5496
29b0f896
AM		 5497 i.rm.regmem = i.base_reg->reg_num;
5498 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5499 i.rex |= REX_B;
29b0f896
AM		 5500 i.sib.base = i.base_reg->reg_num;
5501 /* x86-64 ignores REX prefix bit here to avoid decoder
5502 complications. */
5503 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5504 {
5505 default_seg = &ss;
5506 if (i.disp_operands == 0)
5507 {
5508 fake_zero_displacement = 1;
40fb9820 5509 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5510 }
5511 }
5512 else if (i.base_reg->reg_num == ESP_REG_NUM)
5513 {
5514 default_seg = &ss;
5515 }
5516 i.sib.scale = i.log2_scale_factor;
5517 if (i.index_reg == 0)
5518 {
5519 /* <disp>(%esp) becomes two byte modrm with no index
5520 register. We've already stored the code for esp
5521 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5522 Any base register besides %esp will not use the
5523 extra modrm byte. */
5524 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5525 }
5526 else
5527 {
db51cc60
L		 5528 if (i.index_reg->reg_num == RegEiz
5529 || i.index_reg->reg_num == RegRiz)
5530 i.sib.index = NO_INDEX_REGISTER;
5531 else
5532 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5533 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5534 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5535 i.rex |= REX_X;
29b0f896 5536 }
67a4f2b7
AO		 5537
5538 if (i.disp_operands
5539 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5540 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5541 i.rm.mode = 0;
5542 else
5543 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5544 }
252b5132 5545
29b0f896
AM		 5546 if (fake_zero_displacement)
5547 {
5548 /* Fakes a zero displacement assuming that i.types[op]
5549 holds the correct displacement size. */
5550 expressionS *exp;
5551
9c2799c2 5552 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5553 exp = &disp_expressions[i.disp_operands++];
5554 i.op[op].disps = exp;
5555 exp->X_op = O_constant;
5556 exp->X_add_number = 0;
5557 exp->X_add_symbol = (symbolS *) 0;
5558 exp->X_op_symbol = (symbolS *) 0;
5559 }
c0f3af97
L		 5560
5561 mem = op;
29b0f896 5562 }
c0f3af97
L		 5563 else
5564 mem = ~0;
252b5132 5565
8c43a48b 5566 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5567 {
5568 if (operand_type_check (i.types[0], imm))
5569 i.vex.register_specifier = NULL;
5570 else
5571 {
5572 /* VEX.vvvv encodes one of the sources when the first
5573 operand is not an immediate. */
1ef99a7b 5574 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5575 i.vex.register_specifier = i.op[0].regs;
5576 else
5577 i.vex.register_specifier = i.op[1].regs;
5578 }
5579
5580 /* Destination is a XMM register encoded in the ModRM.reg
5581 and VEX.R bit. */
5582 i.rm.reg = i.op[2].regs->reg_num;
5583 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5584 i.rex |= REX_R;
5585
5586 /* ModRM.rm and VEX.B encodes the other source. */
5587 if (!i.mem_operands)
5588 {
5589 i.rm.mode = 3;
5590
1ef99a7b 5591 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5592 i.rm.regmem = i.op[1].regs->reg_num;
5593 else
5594 i.rm.regmem = i.op[0].regs->reg_num;
5595
5596 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5597 i.rex |= REX_B;
5598 }
5599 }
2426c15f 5600 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5601 {
5602 i.vex.register_specifier = i.op[2].regs;
5603 if (!i.mem_operands)
5604 {
5605 i.rm.mode = 3;
5606 i.rm.regmem = i.op[1].regs->reg_num;
5607 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5608 i.rex |= REX_B;
5609 }
5610 }
29b0f896
AM		 5611 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5612 (if any) based on i.tm.extension_opcode. Again, we must be
5613 careful to make sure that segment/control/debug/test/MMX
5614 registers are coded into the i.rm.reg field. */
f88c9eb0 5615 else if (i.reg_operands)
29b0f896 5616 {
99018f42 5617 unsigned int op;
7ab9ffdd
L		 5618 unsigned int vex_reg = ~0;
5619
5620 for (op = 0; op < i.operands; op++)
5621 if (i.types[op].bitfield.reg8
5622 || i.types[op].bitfield.reg16
5623 || i.types[op].bitfield.reg32
5624 || i.types[op].bitfield.reg64
5625 || i.types[op].bitfield.regmmx
5626 || i.types[op].bitfield.regxmm
5627 || i.types[op].bitfield.regymm
5628 || i.types[op].bitfield.sreg2
5629 || i.types[op].bitfield.sreg3
5630 || i.types[op].bitfield.control
5631 || i.types[op].bitfield.debug
5632 || i.types[op].bitfield.test)
5633 break;
c0209578 5634
7ab9ffdd
L		 5635 if (vex_3_sources)
5636 op = dest;
2426c15f 5637 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5638 {
5639 /* For instructions with VexNDS, the register-only
5640 source operand is encoded in VEX prefix. */
5641 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5642
7ab9ffdd 5643 if (op > mem)
c0f3af97 5644 {
7ab9ffdd
L		 5645 vex_reg = op++;
5646 gas_assert (op < i.operands);
c0f3af97
L		 5647 }
5648 else
c0f3af97 5649 {
7ab9ffdd
L		 5650 vex_reg = op + 1;
5651 gas_assert (vex_reg < i.operands);
c0f3af97 5652 }
7ab9ffdd 5653 }
2426c15f 5654 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5655 {
5656 /* For instructions with VexNDD, there should be
5657 no memory operand and the register destination
5658 is encoded in VEX prefix. */
5659 gas_assert (i.mem_operands == 0
5660 && (op + 2) == i.operands);
5661 vex_reg = op + 1;
5662 }
5663 else
5664 gas_assert (op < i.operands);
99018f42 5665
7ab9ffdd
L		 5666 if (vex_reg != (unsigned int) ~0)
5667 {
5668 gas_assert (i.reg_operands == 2);
5669
5670 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5671 &regxmm)
7ab9ffdd
L		 5672 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5673 &regymm))
5674 abort ();
f88c9eb0 5675
7ab9ffdd
L		 5676 i.vex.register_specifier = i.op[vex_reg].regs;
5677 }
5678
1b9f0c97
L		 5679 /* Don't set OP operand twice. */
5680 if (vex_reg != op)
7ab9ffdd 5681 {
1b9f0c97
L		 5682 /* If there is an extension opcode to put here, the
5683 register number must be put into the regmem field. */
5684 if (i.tm.extension_opcode != None)
5685 {
5686 i.rm.regmem = i.op[op].regs->reg_num;
5687 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5688 i.rex |= REX_B;
5689 }
5690 else
5691 {
5692 i.rm.reg = i.op[op].regs->reg_num;
5693 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5694 i.rex |= REX_R;
5695 }
7ab9ffdd 5696 }
252b5132 5697
29b0f896
AM		 5698 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5699 must set it to 3 to indicate this is a register operand
5700 in the regmem field. */
5701 if (!i.mem_operands)
5702 i.rm.mode = 3;
5703 }
252b5132 5704
29b0f896 5705 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5706 if (i.tm.extension_opcode != None)
29b0f896
AM		 5707 i.rm.reg = i.tm.extension_opcode;
5708 }
5709 return default_seg;
5710}
252b5132 5711
29b0f896 5712static void
e3bb37b5 5713output_branch (void)
29b0f896
AM		 5714{
5715 char *p;
f8a5c266 5716 int size;
29b0f896
AM		 5717 int code16;
5718 int prefix;
5719 relax_substateT subtype;
5720 symbolS *sym;
5721 offsetT off;
5722
f8a5c266
L		 5723 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5724 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5725
5726 prefix = 0;
5727 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5728 {
29b0f896
AM		 5729 prefix = 1;
5730 i.prefixes -= 1;
5731 code16 ^= CODE16;
252b5132 5732 }
29b0f896
AM		 5733 /* Pentium4 branch hints. */
5734 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5735 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5736 {
29b0f896
AM		 5737 prefix++;
5738 i.prefixes--;
5739 }
5740 if (i.prefix[REX_PREFIX] != 0)
5741 {
5742 prefix++;
5743 i.prefixes--;
2f66722d
AM		 5744 }
5745
29b0f896
AM		 5746 if (i.prefixes != 0 && !intel_syntax)
5747 as_warn (_("skipping prefixes on this instruction"));
5748
5749 /* It's always a symbol; End frag & setup for relax.
5750 Make sure there is enough room in this frag for the largest
5751 instruction we may generate in md_convert_frag. This is 2
5752 bytes for the opcode and room for the prefix and largest
5753 displacement. */
5754 frag_grow (prefix + 2 + 4);
5755 /* Prefix and 1 opcode byte go in fr_fix. */
5756 p = frag_more (prefix + 1);
5757 if (i.prefix[DATA_PREFIX] != 0)
5758 *p++ = DATA_PREFIX_OPCODE;
5759 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5760 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5761 *p++ = i.prefix[SEG_PREFIX];
5762 if (i.prefix[REX_PREFIX] != 0)
5763 *p++ = i.prefix[REX_PREFIX];
5764 *p = i.tm.base_opcode;
5765
5766 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5767 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5768 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5769 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5770 else
f8a5c266 5771 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5772 subtype |= code16;
3e73aa7c 5773
29b0f896
AM		 5774 sym = i.op[0].disps->X_add_symbol;
5775 off = i.op[0].disps->X_add_number;
3e73aa7c 5776
29b0f896
AM		 5777 if (i.op[0].disps->X_op != O_constant
5778 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5779 {
29b0f896
AM		 5780 /* Handle complex expressions. */
5781 sym = make_expr_symbol (i.op[0].disps);
5782 off = 0;
5783 }
3e73aa7c 5784
29b0f896
AM		 5785 /* 1 possible extra opcode + 4 byte displacement go in var part.
5786 Pass reloc in fr_var. */
5787 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5788}
3e73aa7c 5789
29b0f896 5790static void
e3bb37b5 5791output_jump (void)
29b0f896
AM		 5792{
5793 char *p;
5794 int size;
3e02c1cc 5795 fixS *fixP;
29b0f896 5796
40fb9820 5797 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5798 {
5799 /* This is a loop or jecxz type instruction. */
5800 size = 1;
5801 if (i.prefix[ADDR_PREFIX] != 0)
5802 {
5803 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5804 i.prefixes -= 1;
5805 }
5806 /* Pentium4 branch hints. */
5807 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5808 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5809 {
5810 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5811 i.prefixes--;
3e73aa7c
JH		 5812 }
5813 }
29b0f896
AM		 5814 else
5815 {
5816 int code16;
3e73aa7c 5817
29b0f896
AM		 5818 code16 = 0;
5819 if (flag_code == CODE_16BIT)
5820 code16 = CODE16;
3e73aa7c 5821
29b0f896
AM		 5822 if (i.prefix[DATA_PREFIX] != 0)
5823 {
5824 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5825 i.prefixes -= 1;
5826 code16 ^= CODE16;
5827 }
252b5132 5828
29b0f896
AM		 5829 size = 4;
5830 if (code16)
5831 size = 2;
5832 }
9fcc94b6 5833
29b0f896
AM		 5834 if (i.prefix[REX_PREFIX] != 0)
5835 {
5836 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5837 i.prefixes -= 1;
5838 }
252b5132 5839
29b0f896
AM		 5840 if (i.prefixes != 0 && !intel_syntax)
5841 as_warn (_("skipping prefixes on this instruction"));
e0890092 5842
29b0f896
AM		 5843 p = frag_more (1 + size);
5844 *p++ = i.tm.base_opcode;
e0890092 5845
3e02c1cc
AM		 5846 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5847 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5848
5849 /* All jumps handled here are signed, but don't use a signed limit
5850 check for 32 and 16 bit jumps as we want to allow wrap around at
5851 4G and 64k respectively. */
5852 if (size == 1)
5853 fixP->fx_signed = 1;
29b0f896 5854}
e0890092 5855
29b0f896 5856static void
e3bb37b5 5857output_interseg_jump (void)
29b0f896
AM		 5858{
5859 char *p;
5860 int size;
5861 int prefix;
5862 int code16;
252b5132 5863
29b0f896
AM		 5864 code16 = 0;
5865 if (flag_code == CODE_16BIT)
5866 code16 = CODE16;
a217f122 5867
29b0f896
AM		 5868 prefix = 0;
5869 if (i.prefix[DATA_PREFIX] != 0)
5870 {
5871 prefix = 1;
5872 i.prefixes -= 1;
5873 code16 ^= CODE16;
5874 }
5875 if (i.prefix[REX_PREFIX] != 0)
5876 {
5877 prefix++;
5878 i.prefixes -= 1;
5879 }
252b5132 5880
29b0f896
AM		 5881 size = 4;
5882 if (code16)
5883 size = 2;
252b5132 5884
29b0f896
AM		 5885 if (i.prefixes != 0 && !intel_syntax)
5886 as_warn (_("skipping prefixes on this instruction"));
252b5132 5887
29b0f896
AM		 5888 /* 1 opcode; 2 segment; offset */
5889 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5890
29b0f896
AM		 5891 if (i.prefix[DATA_PREFIX] != 0)
5892 *p++ = DATA_PREFIX_OPCODE;
252b5132 5893
29b0f896
AM		 5894 if (i.prefix[REX_PREFIX] != 0)
5895 *p++ = i.prefix[REX_PREFIX];
252b5132 5896
29b0f896
AM		 5897 *p++ = i.tm.base_opcode;
5898 if (i.op[1].imms->X_op == O_constant)
5899 {
5900 offsetT n = i.op[1].imms->X_add_number;
252b5132 5901
29b0f896
AM		 5902 if (size == 2
5903 && !fits_in_unsigned_word (n)
5904 && !fits_in_signed_word (n))
5905 {
5906 as_bad (_("16-bit jump out of range"));
5907 return;
5908 }
5909 md_number_to_chars (p, n, size);
5910 }
5911 else
5912 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5913 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5914 if (i.op[0].imms->X_op != O_constant)
5915 as_bad (_("can't handle non absolute segment in `%s'"),
5916 i.tm.name);
5917 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5918}
a217f122 5919
29b0f896 5920static void
e3bb37b5 5921output_insn (void)
29b0f896 5922{
2bbd9c25
JJ		 5923 fragS *insn_start_frag;
5924 offsetT insn_start_off;
5925
29b0f896
AM		 5926 /* Tie dwarf2 debug info to the address at the start of the insn.
5927 We can't do this after the insn has been output as the current
5928 frag may have been closed off. eg. by frag_var. */
5929 dwarf2_emit_insn (0);
5930
2bbd9c25
JJ		 5931 insn_start_frag = frag_now;
5932 insn_start_off = frag_now_fix ();
5933
29b0f896 5934 /* Output jumps. */
40fb9820 5935 if (i.tm.opcode_modifier.jump)
29b0f896 5936 output_branch ();
40fb9820
L		 5937 else if (i.tm.opcode_modifier.jumpbyte
5938 || i.tm.opcode_modifier.jumpdword)
29b0f896 5939 output_jump ();
40fb9820 5940 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5941 output_interseg_jump ();
5942 else
5943 {
5944 /* Output normal instructions here. */
5945 char *p;
5946 unsigned char *q;
47465058 5947 unsigned int j;
331d2d0d 5948 unsigned int prefix;
4dffcebc 5949
c0f3af97
L		 5950 /* Since the VEX prefix contains the implicit prefix, we don't
5951 need the explicit prefix. */
5952 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5953 {
c0f3af97 5954 switch (i.tm.opcode_length)
bc4bd9ab 5955 {
c0f3af97
L		 5956 case 3:
5957 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5958 {
c0f3af97
L		 5959 prefix = (i.tm.base_opcode >> 24) & 0xff;
5960 goto check_prefix;
5961 }
5962 break;
5963 case 2:
5964 if ((i.tm.base_opcode & 0xff0000) != 0)
5965 {
5966 prefix = (i.tm.base_opcode >> 16) & 0xff;
5967 if (i.tm.cpu_flags.bitfield.cpupadlock)
5968 {
4dffcebc 5969check_prefix:
c0f3af97 5970 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5971 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5972 != REPE_PREFIX_OPCODE))
5973 add_prefix (prefix);
5974 }
5975 else
4dffcebc
L		 5976 add_prefix (prefix);
5977 }
c0f3af97
L		 5978 break;
5979 case 1:
5980 break;
5981 default:
5982 abort ();
bc4bd9ab 5983 }
c0f3af97
L		 5984
5985 /* The prefix bytes. */
5986 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5987 if (*q)
5988 FRAG_APPEND_1_CHAR (*q);
0f10071e 5989 }
252b5132 5990
c0f3af97
L		 5991 if (i.tm.opcode_modifier.vex)
5992 {
5993 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5994 if (*q)
5995 switch (j)
5996 {
5997 case REX_PREFIX:
5998 /* REX byte is encoded in VEX prefix. */
5999 break;
6000 case SEG_PREFIX:
6001 case ADDR_PREFIX:
6002 FRAG_APPEND_1_CHAR (*q);
6003 break;
6004 default:
6005 /* There should be no other prefixes for instructions
6006 with VEX prefix. */
6007 abort ();
6008 }
6009
6010 /* Now the VEX prefix. */
6011 p = frag_more (i.vex.length);
6012 for (j = 0; j < i.vex.length; j++)
6013 p[j] = i.vex.bytes[j];
6014 }
252b5132 6015
29b0f896 6016 /* Now the opcode; be careful about word order here! */
4dffcebc 6017 if (i.tm.opcode_length == 1)
29b0f896
AM		 6018 {
6019 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6020 }
6021 else
6022 {
4dffcebc 6023 switch (i.tm.opcode_length)
331d2d0d 6024 {
4dffcebc 6025 case 3:
331d2d0d
L		 6026 p = frag_more (3);
6027 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6028 break;
6029 case 2:
6030 p = frag_more (2);
6031 break;
6032 default:
6033 abort ();
6034 break;
331d2d0d 6035 }
0f10071e 6036
29b0f896
AM		 6037 /* Put out high byte first: can't use md_number_to_chars! */
6038 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6039 *p = i.tm.base_opcode & 0xff;
6040 }
3e73aa7c 6041
29b0f896 6042 /* Now the modrm byte and sib byte (if present). */
40fb9820 6043 if (i.tm.opcode_modifier.modrm)
29b0f896 6044 {
4a3523fa
L		 6045 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6046 | i.rm.reg << 3
6047 | i.rm.mode << 6));
29b0f896
AM		 6048 /* If i.rm.regmem == ESP (4)
6049 && i.rm.mode != (Register mode)
6050 && not 16 bit
6051 ==> need second modrm byte. */
6052 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6053 && i.rm.mode != 3
40fb9820 6054 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6055 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6056 | i.sib.index << 3
6057 | i.sib.scale << 6));
29b0f896 6058 }
3e73aa7c 6059
29b0f896 6060 if (i.disp_operands)
2bbd9c25 6061 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6062
29b0f896 6063 if (i.imm_operands)
2bbd9c25 6064 output_imm (insn_start_frag, insn_start_off);
29b0f896 6065 }
252b5132 6066
29b0f896
AM		 6067#ifdef DEBUG386
6068 if (flag_debug)
6069 {
7b81dfbb 6070 pi ("" /*line*/, &i);
29b0f896
AM		 6071 }
6072#endif /* DEBUG386 */
6073}
252b5132 6074
e205caa7
L		 6075/* Return the size of the displacement operand N. */
6076
6077static int
6078disp_size (unsigned int n)
6079{
6080 int size = 4;
40fb9820
L		 6081 if (i.types[n].bitfield.disp64)
6082 size = 8;
6083 else if (i.types[n].bitfield.disp8)
6084 size = 1;
6085 else if (i.types[n].bitfield.disp16)
6086 size = 2;
e205caa7
L		 6087 return size;
6088}
6089
6090/* Return the size of the immediate operand N. */
6091
6092static int
6093imm_size (unsigned int n)
6094{
6095 int size = 4;
40fb9820
L		 6096 if (i.types[n].bitfield.imm64)
6097 size = 8;
6098 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6099 size = 1;
6100 else if (i.types[n].bitfield.imm16)
6101 size = 2;
e205caa7
L		 6102 return size;
6103}
6104
29b0f896 6105static void
64e74474 6106output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6107{
6108 char *p;
6109 unsigned int n;
252b5132 6110
29b0f896
AM		 6111 for (n = 0; n < i.operands; n++)
6112 {
40fb9820 6113 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6114 {
6115 if (i.op[n].disps->X_op == O_constant)
6116 {
e205caa7 6117 int size = disp_size (n);
29b0f896 6118 offsetT val;
252b5132 6119
29b0f896
AM		 6120 val = offset_in_range (i.op[n].disps->X_add_number,
6121 size);
6122 p = frag_more (size);
6123 md_number_to_chars (p, val, size);
6124 }
6125 else
6126 {
f86103b7 6127 enum bfd_reloc_code_real reloc_type;
e205caa7 6128 int size = disp_size (n);
40fb9820 6129 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6130 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6131
e205caa7 6132 /* We can't have 8 bit displacement here. */
9c2799c2 6133 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6134
29b0f896
AM		 6135 /* The PC relative address is computed relative
6136 to the instruction boundary, so in case immediate
6137 fields follows, we need to adjust the value. */
6138 if (pcrel && i.imm_operands)
6139 {
29b0f896 6140 unsigned int n1;
e205caa7 6141 int sz = 0;
252b5132 6142
29b0f896 6143 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6144 if (operand_type_check (i.types[n1], imm))
252b5132 6145 {
e205caa7
L		 6146 /* Only one immediate is allowed for PC
6147 relative address. */
9c2799c2 6148 gas_assert (sz == 0);
e205caa7
L		 6149 sz = imm_size (n1);
6150 i.op[n].disps->X_add_number -= sz;
252b5132 6151 }
29b0f896 6152 /* We should find the immediate. */
9c2799c2 6153 gas_assert (sz != 0);
29b0f896 6154 }
520dc8e8 6155
29b0f896 6156 p = frag_more (size);
2bbd9c25 6157 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6158 if (GOT_symbol
2bbd9c25 6159 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6160 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6161 || reloc_type == BFD_RELOC_X86_64_32S
6162 || (reloc_type == BFD_RELOC_64
6163 && object_64bit))
d6ab8113
JB		 6164 && (i.op[n].disps->X_op == O_symbol
6165 || (i.op[n].disps->X_op == O_add
6166 && ((symbol_get_value_expression
6167 (i.op[n].disps->X_op_symbol)->X_op)
6168 == O_subtract))))
6169 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6170 {
6171 offsetT add;
6172
6173 if (insn_start_frag == frag_now)
6174 add = (p - frag_now->fr_literal) - insn_start_off;
6175 else
6176 {
6177 fragS *fr;
6178
6179 add = insn_start_frag->fr_fix - insn_start_off;
6180 for (fr = insn_start_frag->fr_next;
6181 fr && fr != frag_now; fr = fr->fr_next)
6182 add += fr->fr_fix;
6183 add += p - frag_now->fr_literal;
6184 }
6185
4fa24527 6186 if (!object_64bit)
7b81dfbb
AJ		 6187 {
6188 reloc_type = BFD_RELOC_386_GOTPC;
6189 i.op[n].imms->X_add_number += add;
6190 }
6191 else if (reloc_type == BFD_RELOC_64)
6192 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6193 else
7b81dfbb
AJ		 6194 /* Don't do the adjustment for x86-64, as there
6195 the pcrel addressing is relative to the _next_
6196 insn, and that is taken care of in other code. */
d6ab8113 6197 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6198 }
062cd5e7 6199 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6200 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6201 }
6202 }
6203 }
6204}
252b5132 6205
29b0f896 6206static void
64e74474 6207output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6208{
6209 char *p;
6210 unsigned int n;
252b5132 6211
29b0f896
AM		 6212 for (n = 0; n < i.operands; n++)
6213 {
40fb9820 6214 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6215 {
6216 if (i.op[n].imms->X_op == O_constant)
6217 {
e205caa7 6218 int size = imm_size (n);
29b0f896 6219 offsetT val;
b4cac588 6220
29b0f896
AM		 6221 val = offset_in_range (i.op[n].imms->X_add_number,
6222 size);
6223 p = frag_more (size);
6224 md_number_to_chars (p, val, size);
6225 }
6226 else
6227 {
6228 /* Not absolute_section.
6229 Need a 32-bit fixup (don't support 8bit
6230 non-absolute imms). Try to support other
6231 sizes ... */
f86103b7 6232 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6233 int size = imm_size (n);
6234 int sign;
29b0f896 6235
40fb9820 6236 if (i.types[n].bitfield.imm32s
a7d61044 6237 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6238 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6239 sign = 1;
e205caa7
L		 6240 else
6241 sign = 0;
520dc8e8 6242
29b0f896
AM		 6243 p = frag_more (size);
6244 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6245
2bbd9c25
JJ		 6246 /* This is tough to explain. We end up with this one if we
6247 * have operands that look like
6248 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6249 * obtain the absolute address of the GOT, and it is strongly
6250 * preferable from a performance point of view to avoid using
6251 * a runtime relocation for this. The actual sequence of
6252 * instructions often look something like:
6253 *
6254 * call .L66
6255 * .L66:
6256 * popl %ebx
6257 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6258 *
6259 * The call and pop essentially return the absolute address
6260 * of the label .L66 and store it in %ebx. The linker itself
6261 * will ultimately change the first operand of the addl so
6262 * that %ebx points to the GOT, but to keep things simple, the
6263 * .o file must have this operand set so that it generates not
6264 * the absolute address of .L66, but the absolute address of
6265 * itself. This allows the linker itself simply treat a GOTPC
6266 * relocation as asking for a pcrel offset to the GOT to be
6267 * added in, and the addend of the relocation is stored in the
6268 * operand field for the instruction itself.
6269 *
6270 * Our job here is to fix the operand so that it would add
6271 * the correct offset so that %ebx would point to itself. The
6272 * thing that is tricky is that .-.L66 will point to the
6273 * beginning of the instruction, so we need to further modify
6274 * the operand so that it will point to itself. There are
6275 * other cases where you have something like:
6276 *
6277 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6278 *
6279 * and here no correction would be required. Internally in
6280 * the assembler we treat operands of this form as not being
6281 * pcrel since the '.' is explicitly mentioned, and I wonder
6282 * whether it would simplify matters to do it this way. Who
6283 * knows. In earlier versions of the PIC patches, the
6284 * pcrel_adjust field was used to store the correction, but
6285 * since the expression is not pcrel, I felt it would be
6286 * confusing to do it this way. */
6287
d6ab8113 6288 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6289 || reloc_type == BFD_RELOC_X86_64_32S
6290 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6291 && GOT_symbol
6292 && GOT_symbol == i.op[n].imms->X_add_symbol
6293 && (i.op[n].imms->X_op == O_symbol
6294 || (i.op[n].imms->X_op == O_add
6295 && ((symbol_get_value_expression
6296 (i.op[n].imms->X_op_symbol)->X_op)
6297 == O_subtract))))
6298 {
2bbd9c25
JJ		 6299 offsetT add;
6300
6301 if (insn_start_frag == frag_now)
6302 add = (p - frag_now->fr_literal) - insn_start_off;
6303 else
6304 {
6305 fragS *fr;
6306
6307 add = insn_start_frag->fr_fix - insn_start_off;
6308 for (fr = insn_start_frag->fr_next;
6309 fr && fr != frag_now; fr = fr->fr_next)
6310 add += fr->fr_fix;
6311 add += p - frag_now->fr_literal;
6312 }
6313
4fa24527 6314 if (!object_64bit)
d6ab8113 6315 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6316 else if (size == 4)
d6ab8113 6317 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6318 else if (size == 8)
6319 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6320 i.op[n].imms->X_add_number += add;
29b0f896 6321 }
29b0f896
AM		 6322 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6323 i.op[n].imms, 0, reloc_type);
6324 }
6325 }
6326 }
252b5132
RH		 6327}
6328\f
d182319b
JB		 6329/* x86_cons_fix_new is called via the expression parsing code when a
6330 reloc is needed. We use this hook to get the correct .got reloc. */
6331static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6332static int cons_sign = -1;
6333
6334void
e3bb37b5 6335x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6336 expressionS *exp)
d182319b
JB		 6337{
6338 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6339
6340 got_reloc = NO_RELOC;
6341
6342#ifdef TE_PE
6343 if (exp->X_op == O_secrel)
6344 {
6345 exp->X_op = O_symbol;
6346 r = BFD_RELOC_32_SECREL;
6347 }
6348#endif
6349
6350 fix_new_exp (frag, off, len, exp, 0, r);
6351}
6352
718ddfc0
JB		 6353#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6354# define lex_got(reloc, adjust, types) NULL
6355#else
f3c180ae
AM		 6356/* Parse operands of the form
6357 <symbol>@GOTOFF+<nnn>
6358 and similar .plt or .got references.
6359
6360 If we find one, set up the correct relocation in RELOC and copy the
6361 input string, minus the `@GOTOFF' into a malloc'd buffer for
6362 parsing by the calling routine. Return this buffer, and if ADJUST
6363 is non-null set it to the length of the string we removed from the
6364 input line. Otherwise return NULL. */
6365static char *
91d6fa6a 6366lex_got (enum bfd_reloc_code_real *rel,
64e74474 6367 int *adjust,
40fb9820 6368 i386_operand_type *types)
f3c180ae 6369{
7b81dfbb
AJ		 6370 /* Some of the relocations depend on the size of what field is to
6371 be relocated. But in our callers i386_immediate and i386_displacement
6372 we don't yet know the operand size (this will be set by insn
6373 matching). Hence we record the word32 relocation here,
6374 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6375 static const struct {
6376 const char *str;
cff8d58a 6377 int len;
4fa24527 6378 const enum bfd_reloc_code_real rel[2];
40fb9820 6379 const i386_operand_type types64;
f3c180ae 6380 } gotrel[] = {
cff8d58a
L		 6381 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6382 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6383 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6384 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6385 BFD_RELOC_X86_64_PLT32 },
40fb9820 6386 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6387 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6388 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6389 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6390 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6391 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6392 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6393 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6394 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6395 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6396 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6397 BFD_RELOC_X86_64_TLSGD },
40fb9820 6398 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6399 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6400 _dummy_first_bfd_reloc_code_real },
40fb9820 6401 OPERAND_TYPE_NONE },
cff8d58a
L		 6402 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6403 BFD_RELOC_X86_64_TLSLD },
40fb9820 6404 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6405 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6406 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6407 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6408 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6409 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6410 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6411 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6412 _dummy_first_bfd_reloc_code_real },
40fb9820 6413 OPERAND_TYPE_NONE },
cff8d58a
L		 6414 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6415 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6416 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6417 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6418 _dummy_first_bfd_reloc_code_real },
40fb9820 6419 OPERAND_TYPE_NONE },
cff8d58a
L		 6420 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6421 _dummy_first_bfd_reloc_code_real },
40fb9820 6422 OPERAND_TYPE_NONE },
cff8d58a
L		 6423 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6424 BFD_RELOC_X86_64_GOT32 },
40fb9820 6425 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6426 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6427 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6428 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6429 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6430 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6431 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6432 };
6433 char *cp;
6434 unsigned int j;
6435
718ddfc0
JB		 6436 if (!IS_ELF)
6437 return NULL;
6438
f3c180ae 6439 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6440 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6441 return NULL;
6442
47465058 6443 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6444 {
cff8d58a 6445 int len = gotrel[j].len;
28f81592 6446 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6447 {
4fa24527 6448 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6449 {
28f81592
AM		 6450 int first, second;
6451 char *tmpbuf, *past_reloc;
f3c180ae 6452
91d6fa6a 6453 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6454 if (adjust)
6455 *adjust = len;
f3c180ae 6456
3956db08
JB		 6457 if (types)
6458 {
6459 if (flag_code != CODE_64BIT)
40fb9820
L		 6460 {
6461 types->bitfield.imm32 = 1;
6462 types->bitfield.disp32 = 1;
6463 }
3956db08
JB		 6464 else
6465 *types = gotrel[j].types64;
6466 }
6467
f3c180ae
AM		 6468 if (GOT_symbol == NULL)
6469 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6470
28f81592 6471 /* The length of the first part of our input line. */
f3c180ae 6472 first = cp - input_line_pointer;
28f81592
AM		 6473
6474 /* The second part goes from after the reloc token until
67c11a9b 6475 (and including) an end_of_line char or comma. */
28f81592 6476 past_reloc = cp + 1 + len;
67c11a9b
AM		 6477 cp = past_reloc;
6478 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6479 ++cp;
6480 second = cp + 1 - past_reloc;
28f81592
AM		 6481
6482 /* Allocate and copy string. The trailing NUL shouldn't
6483 be necessary, but be safe. */
1e9cc1c2 6484 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6485 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6486 if (second != 0 && *past_reloc != ' ')
6487 /* Replace the relocation token with ' ', so that
6488 errors like foo@GOTOFF1 will be detected. */
6489 tmpbuf[first++] = ' ';
6490 memcpy (tmpbuf + first, past_reloc, second);
6491 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6492 return tmpbuf;
6493 }
6494
4fa24527
JB		 6495 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6496 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6497 return NULL;
6498 }
6499 }
6500
6501 /* Might be a symbol version string. Don't as_bad here. */
6502 return NULL;
6503}
6504
f3c180ae 6505void
e3bb37b5 6506x86_cons (expressionS *exp, int size)
f3c180ae 6507{
ee86248c
JB		 6508 intel_syntax = -intel_syntax;
6509
3c7b9c2c 6510 exp->X_md = 0;
4fa24527 6511 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6512 {
6513 /* Handle @GOTOFF and the like in an expression. */
6514 char *save;
6515 char *gotfree_input_line;
6516 int adjust;
6517
6518 save = input_line_pointer;
3956db08 6519 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6520 if (gotfree_input_line)
6521 input_line_pointer = gotfree_input_line;
6522
6523 expression (exp);
6524
6525 if (gotfree_input_line)
6526 {
6527 /* expression () has merrily parsed up to the end of line,
6528 or a comma - in the wrong buffer. Transfer how far
6529 input_line_pointer has moved to the right buffer. */
6530 input_line_pointer = (save
6531 + (input_line_pointer - gotfree_input_line)
6532 + adjust);
6533 free (gotfree_input_line);
3992d3b7
AM		 6534 if (exp->X_op == O_constant
6535 || exp->X_op == O_absent
6536 || exp->X_op == O_illegal
0398aac5 6537 || exp->X_op == O_register
3992d3b7
AM		 6538 || exp->X_op == O_big)
6539 {
6540 char c = *input_line_pointer;
6541 *input_line_pointer = 0;
6542 as_bad (_("missing or invalid expression `%s'"), save);
6543 *input_line_pointer = c;
6544 }
f3c180ae
AM		 6545 }
6546 }
6547 else
6548 expression (exp);
ee86248c
JB		 6549
6550 intel_syntax = -intel_syntax;
6551
6552 if (intel_syntax)
6553 i386_intel_simplify (exp);
f3c180ae
AM		 6554}
6555#endif
6556
9f32dd5b
L		 6557static void
6558signed_cons (int size)
6482c264 6559{
d182319b
JB		 6560 if (flag_code == CODE_64BIT)
6561 cons_sign = 1;
6562 cons (size);
6563 cons_sign = -1;
6482c264
NC		 6564}
6565
d182319b 6566#ifdef TE_PE
6482c264
NC		 6567static void
6568pe_directive_secrel (dummy)
6569 int dummy ATTRIBUTE_UNUSED;
6570{
6571 expressionS exp;
6572
6573 do
6574 {
6575 expression (&exp);
6576 if (exp.X_op == O_symbol)
6577 exp.X_op = O_secrel;
6578
6579 emit_expr (&exp, 4);
6580 }
6581 while (*input_line_pointer++ == ',');
6582
6583 input_line_pointer--;
6584 demand_empty_rest_of_line ();
6585}
6482c264
NC		 6586#endif
6587
252b5132 6588static int
70e41ade 6589i386_immediate (char *imm_start)
252b5132
RH		 6590{
6591 char *save_input_line_pointer;
f3c180ae 6592 char *gotfree_input_line;
252b5132 6593 segT exp_seg = 0;
47926f60 6594 expressionS *exp;
40fb9820
L		 6595 i386_operand_type types;
6596
0dfbf9d7 6597 operand_type_set (&types, ~0);
252b5132
RH		 6598
6599 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6600 {
31b2323c
L		 6601 as_bad (_("at most %d immediate operands are allowed"),
6602 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6603 return 0;
6604 }
6605
6606 exp = &im_expressions[i.imm_operands++];
520dc8e8 6607 i.op[this_operand].imms = exp;
252b5132
RH		 6608
6609 if (is_space_char (*imm_start))
6610 ++imm_start;
6611
6612 save_input_line_pointer = input_line_pointer;
6613 input_line_pointer = imm_start;
6614
3956db08 6615 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6616 if (gotfree_input_line)
6617 input_line_pointer = gotfree_input_line;
252b5132
RH		 6618
6619 exp_seg = expression (exp);
6620
83183c0c 6621 SKIP_WHITESPACE ();
252b5132 6622 if (*input_line_pointer)
f3c180ae 6623 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6624
6625 input_line_pointer = save_input_line_pointer;
f3c180ae 6626 if (gotfree_input_line)
ee86248c
JB		 6627 {
6628 free (gotfree_input_line);
6629
6630 if (exp->X_op == O_constant || exp->X_op == O_register)
6631 exp->X_op = O_illegal;
6632 }
6633
6634 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6635}
252b5132 6636
ee86248c
JB		 6637static int
6638i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6639 i386_operand_type types, const char *imm_start)
6640{
6641 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6642 {
313c53d1
L		 6643 if (imm_start)
6644 as_bad (_("missing or invalid immediate expression `%s'"),
6645 imm_start);
3992d3b7 6646 return 0;
252b5132 6647 }
3e73aa7c 6648 else if (exp->X_op == O_constant)
252b5132 6649 {
47926f60 6650 /* Size it properly later. */
40fb9820 6651 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6652 /* If not 64bit, sign extend val. */
6653 if (flag_code != CODE_64BIT
4eed87de
AM		 6654 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6655 exp->X_add_number
6656 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6657 }
4c63da97 6658#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6659 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6660 && exp_seg != absolute_section
47926f60 6661 && exp_seg != text_section
24eab124
AM		 6662 && exp_seg != data_section
6663 && exp_seg != bss_section
6664 && exp_seg != undefined_section
f86103b7 6665 && !bfd_is_com_section (exp_seg))
252b5132 6666 {
d0b47220 6667 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6668 return 0;
6669 }
6670#endif
bb8f5920
L		 6671 else if (!intel_syntax && exp->X_op == O_register)
6672 {
313c53d1
L		 6673 if (imm_start)
6674 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6675 return 0;
6676 }
252b5132
RH		 6677 else
6678 {
6679 /* This is an address. The size of the address will be
24eab124 6680 determined later, depending on destination register,
3e73aa7c 6681 suffix, or the default for the section. */
40fb9820
L		 6682 i.types[this_operand].bitfield.imm8 = 1;
6683 i.types[this_operand].bitfield.imm16 = 1;
6684 i.types[this_operand].bitfield.imm32 = 1;
6685 i.types[this_operand].bitfield.imm32s = 1;
6686 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6687 i.types[this_operand] = operand_type_and (i.types[this_operand],
6688 types);
252b5132
RH		 6689 }
6690
6691 return 1;
6692}
6693
551c1ca1 6694static char *
e3bb37b5 6695i386_scale (char *scale)
252b5132 6696{
551c1ca1
AM		 6697 offsetT val;
6698 char *save = input_line_pointer;
252b5132 6699
551c1ca1
AM		 6700 input_line_pointer = scale;
6701 val = get_absolute_expression ();
6702
6703 switch (val)
252b5132 6704 {
551c1ca1 6705 case 1:
252b5132
RH		 6706 i.log2_scale_factor = 0;
6707 break;
551c1ca1 6708 case 2:
252b5132
RH		 6709 i.log2_scale_factor = 1;
6710 break;
551c1ca1 6711 case 4:
252b5132
RH		 6712 i.log2_scale_factor = 2;
6713 break;
551c1ca1 6714 case 8:
252b5132
RH		 6715 i.log2_scale_factor = 3;
6716 break;
6717 default:
a724f0f4
JB		 6718 {
6719 char sep = *input_line_pointer;
6720
6721 *input_line_pointer = '\0';
6722 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6723 scale);
6724 *input_line_pointer = sep;
6725 input_line_pointer = save;
6726 return NULL;
6727 }
252b5132 6728 }
29b0f896 6729 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6730 {
6731 as_warn (_("scale factor of %d without an index register"),
24eab124 6732 1 << i.log2_scale_factor);
252b5132 6733 i.log2_scale_factor = 0;
252b5132 6734 }
551c1ca1
AM		 6735 scale = input_line_pointer;
6736 input_line_pointer = save;
6737 return scale;
252b5132
RH		 6738}
6739
252b5132 6740static int
e3bb37b5 6741i386_displacement (char *disp_start, char *disp_end)
252b5132 6742{
29b0f896 6743 expressionS *exp;
252b5132
RH		 6744 segT exp_seg = 0;
6745 char *save_input_line_pointer;
f3c180ae 6746 char *gotfree_input_line;
40fb9820
L		 6747 int override;
6748 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6749 int ret;
252b5132 6750
31b2323c
L		 6751 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6752 {
6753 as_bad (_("at most %d displacement operands are allowed"),
6754 MAX_MEMORY_OPERANDS);
6755 return 0;
6756 }
6757
0dfbf9d7 6758 operand_type_set (&bigdisp, 0);
40fb9820
L		 6759 if ((i.types[this_operand].bitfield.jumpabsolute)
6760 || (!current_templates->start->opcode_modifier.jump
6761 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6762 {
40fb9820 6763 bigdisp.bitfield.disp32 = 1;
e05278af 6764 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6765 if (flag_code == CODE_64BIT)
6766 {
6767 if (!override)
6768 {
6769 bigdisp.bitfield.disp32s = 1;
6770 bigdisp.bitfield.disp64 = 1;
6771 }
6772 }
6773 else if ((flag_code == CODE_16BIT) ^ override)
6774 {
6775 bigdisp.bitfield.disp32 = 0;
6776 bigdisp.bitfield.disp16 = 1;
6777 }
e05278af
JB		 6778 }
6779 else
6780 {
6781 /* For PC-relative branches, the width of the displacement
6782 is dependent upon data size, not address size. */
e05278af 6783 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6784 if (flag_code == CODE_64BIT)
6785 {
6786 if (override || i.suffix == WORD_MNEM_SUFFIX)
6787 bigdisp.bitfield.disp16 = 1;
6788 else
6789 {
6790 bigdisp.bitfield.disp32 = 1;
6791 bigdisp.bitfield.disp32s = 1;
6792 }
6793 }
6794 else
e05278af
JB		 6795 {
6796 if (!override)
6797 override = (i.suffix == (flag_code != CODE_16BIT
6798 ? WORD_MNEM_SUFFIX
6799 : LONG_MNEM_SUFFIX));
40fb9820
L		 6800 bigdisp.bitfield.disp32 = 1;
6801 if ((flag_code == CODE_16BIT) ^ override)
6802 {
6803 bigdisp.bitfield.disp32 = 0;
6804 bigdisp.bitfield.disp16 = 1;
6805 }
e05278af 6806 }
e05278af 6807 }
c6fb90c8
L		 6808 i.types[this_operand] = operand_type_or (i.types[this_operand],
6809 bigdisp);
252b5132
RH		 6810
6811 exp = &disp_expressions[i.disp_operands];
520dc8e8 6812 i.op[this_operand].disps = exp;
252b5132
RH		 6813 i.disp_operands++;
6814 save_input_line_pointer = input_line_pointer;
6815 input_line_pointer = disp_start;
6816 END_STRING_AND_SAVE (disp_end);
6817
6818#ifndef GCC_ASM_O_HACK
6819#define GCC_ASM_O_HACK 0
6820#endif
6821#if GCC_ASM_O_HACK
6822 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6823 if (i.types[this_operand].bitfield.baseIndex
24eab124 6824 && displacement_string_end[-1] == '+')
252b5132
RH		 6825 {
6826 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6827 constraint within gcc asm statements.
6828 For instance:
6829
6830 #define _set_tssldt_desc(n,addr,limit,type) \
6831 __asm__ __volatile__ ( \
6832 "movw %w2,%0\n\t" \
6833 "movw %w1,2+%0\n\t" \
6834 "rorl $16,%1\n\t" \
6835 "movb %b1,4+%0\n\t" \
6836 "movb %4,5+%0\n\t" \
6837 "movb $0,6+%0\n\t" \
6838 "movb %h1,7+%0\n\t" \
6839 "rorl $16,%1" \
6840 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6841
6842 This works great except that the output assembler ends
6843 up looking a bit weird if it turns out that there is
6844 no offset. You end up producing code that looks like:
6845
6846 #APP
6847 movw $235,(%eax)
6848 movw %dx,2+(%eax)
6849 rorl $16,%edx
6850 movb %dl,4+(%eax)
6851 movb $137,5+(%eax)
6852 movb $0,6+(%eax)
6853 movb %dh,7+(%eax)
6854 rorl $16,%edx
6855 #NO_APP
6856
47926f60 6857 So here we provide the missing zero. */
24eab124
AM		 6858
6859 *displacement_string_end = '0';
252b5132
RH		 6860 }
6861#endif
3956db08 6862 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6863 if (gotfree_input_line)
6864 input_line_pointer = gotfree_input_line;
252b5132 6865
24eab124 6866 exp_seg = expression (exp);
252b5132 6867
636c26b0
AM		 6868 SKIP_WHITESPACE ();
6869 if (*input_line_pointer)
6870 as_bad (_("junk `%s' after expression"), input_line_pointer);
6871#if GCC_ASM_O_HACK
6872 RESTORE_END_STRING (disp_end + 1);
6873#endif
636c26b0 6874 input_line_pointer = save_input_line_pointer;
636c26b0 6875 if (gotfree_input_line)
ee86248c
JB		 6876 {
6877 free (gotfree_input_line);
6878
6879 if (exp->X_op == O_constant || exp->X_op == O_register)
6880 exp->X_op = O_illegal;
6881 }
6882
6883 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6884
6885 RESTORE_END_STRING (disp_end);
6886
6887 return ret;
6888}
6889
6890static int
6891i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6892 i386_operand_type types, const char *disp_start)
6893{
6894 i386_operand_type bigdisp;
6895 int ret = 1;
636c26b0 6896
24eab124
AM		 6897 /* We do this to make sure that the section symbol is in
6898 the symbol table. We will ultimately change the relocation
47926f60 6899 to be relative to the beginning of the section. */
1ae12ab7 6900 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6901 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6902 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6903 {
636c26b0 6904 if (exp->X_op != O_symbol)
3992d3b7 6905 goto inv_disp;
636c26b0 6906
e5cb08ac 6907 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 6908 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
6909 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 6910 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6911 exp->X_op = O_subtract;
6912 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6913 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6914 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6915 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6916 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6917 else
29b0f896 6918 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6919 }
252b5132 6920
3992d3b7
AM		 6921 else if (exp->X_op == O_absent
6922 || exp->X_op == O_illegal
ee86248c 6923 || exp->X_op == O_big)
2daf4fd8 6924 {
3992d3b7
AM		 6925 inv_disp:
6926 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6927 disp_start);
3992d3b7 6928 ret = 0;
2daf4fd8
AM		 6929 }
6930
0e1147d9
L		 6931 else if (flag_code == CODE_64BIT
6932 && !i.prefix[ADDR_PREFIX]
6933 && exp->X_op == O_constant)
6934 {
6935 /* Since displacement is signed extended to 64bit, don't allow
6936 disp32 and turn off disp32s if they are out of range. */
6937 i.types[this_operand].bitfield.disp32 = 0;
6938 if (!fits_in_signed_long (exp->X_add_number))
6939 {
6940 i.types[this_operand].bitfield.disp32s = 0;
6941 if (i.types[this_operand].bitfield.baseindex)
6942 {
6943 as_bad (_("0x%lx out range of signed 32bit displacement"),
6944 (long) exp->X_add_number);
6945 ret = 0;
6946 }
6947 }
6948 }
6949
4c63da97 6950#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6951 else if (exp->X_op != O_constant
6952 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6953 && exp_seg != absolute_section
6954 && exp_seg != text_section
6955 && exp_seg != data_section
6956 && exp_seg != bss_section
6957 && exp_seg != undefined_section
6958 && !bfd_is_com_section (exp_seg))
24eab124 6959 {
d0b47220 6960 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6961 ret = 0;
24eab124 6962 }
252b5132 6963#endif
3956db08 6964
40fb9820
L		 6965 /* Check if this is a displacement only operand. */
6966 bigdisp = i.types[this_operand];
6967 bigdisp.bitfield.disp8 = 0;
6968 bigdisp.bitfield.disp16 = 0;
6969 bigdisp.bitfield.disp32 = 0;
6970 bigdisp.bitfield.disp32s = 0;
6971 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6972 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6973 i.types[this_operand] = operand_type_and (i.types[this_operand],
6974 types);
3956db08 6975
3992d3b7 6976 return ret;
252b5132
RH		 6977}
6978
eecb386c 6979/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6980 Return 1 on success, 0 on a failure. */
6981
252b5132 6982static int
e3bb37b5 6983i386_index_check (const char *operand_string)
252b5132 6984{
3e73aa7c 6985 int ok;
fc0763e6 6986 const char *kind = "base/index";
24eab124 6987#if INFER_ADDR_PREFIX
eecb386c
AM		 6988 int fudged = 0;
6989
24eab124
AM		 6990 tryprefix:
6991#endif
3e73aa7c 6992 ok = 1;
fc0763e6
JB		 6993 if (current_templates->start->opcode_modifier.isstring
6994 && !current_templates->start->opcode_modifier.immext
6995 && (current_templates->end[-1].opcode_modifier.isstring
6996 || i.mem_operands))
6997 {
6998 /* Memory operands of string insns are special in that they only allow
6999 a single register (rDI, rSI, or rBX) as their memory address. */
7000 unsigned int expected;
7001
7002 kind = "string address";
7003
7004 if (current_templates->start->opcode_modifier.w)
7005 {
7006 i386_operand_type type = current_templates->end[-1].operand_types[0];
7007
7008 if (!type.bitfield.baseindex
7009 || ((!i.mem_operands != !intel_syntax)
7010 && current_templates->end[-1].operand_types[1]
7011 .bitfield.baseindex))
7012 type = current_templates->end[-1].operand_types[1];
7013 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7014 }
7015 else
7016 expected = 3 /* rBX */;
7017
7018 if (!i.base_reg || i.index_reg
7019 || operand_type_check (i.types[this_operand], disp))
7020 ok = -1;
7021 else if (!(flag_code == CODE_64BIT
7022 ? i.prefix[ADDR_PREFIX]
7023 ? i.base_reg->reg_type.bitfield.reg32
7024 : i.base_reg->reg_type.bitfield.reg64
7025 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7026 ? i.base_reg->reg_type.bitfield.reg32
7027 : i.base_reg->reg_type.bitfield.reg16))
7028 ok = 0;
7029 else if (i.base_reg->reg_num != expected)
7030 ok = -1;
7031
7032 if (ok < 0)
7033 {
7034 unsigned int j;
7035
7036 for (j = 0; j < i386_regtab_size; ++j)
7037 if ((flag_code == CODE_64BIT
7038 ? i.prefix[ADDR_PREFIX]
7039 ? i386_regtab[j].reg_type.bitfield.reg32
7040 : i386_regtab[j].reg_type.bitfield.reg64
7041 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7042 ? i386_regtab[j].reg_type.bitfield.reg32
7043 : i386_regtab[j].reg_type.bitfield.reg16)
7044 && i386_regtab[j].reg_num == expected)
7045 break;
9c2799c2 7046 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7047 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7048 operand_string,
7049 intel_syntax ? '[' : '(',
7050 register_prefix,
7051 i386_regtab[j].reg_name,
7052 intel_syntax ? ']' : ')');
7053 ok = 1;
7054 }
7055 }
7056 else if (flag_code == CODE_64BIT)
64e74474 7057 {
64e74474 7058 if ((i.base_reg
40fb9820
L		 7059 && ((i.prefix[ADDR_PREFIX] == 0
7060 && !i.base_reg->reg_type.bitfield.reg64)
7061 || (i.prefix[ADDR_PREFIX]
7062 && !i.base_reg->reg_type.bitfield.reg32))
7063 && (i.index_reg
9a04903e
JB		 7064 || i.base_reg->reg_num !=
7065 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7066 || (i.index_reg
40fb9820
L		 7067 && (!i.index_reg->reg_type.bitfield.baseindex
7068 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7069 && i.index_reg->reg_num != RegRiz
7070 && !i.index_reg->reg_type.bitfield.reg64
7071 )
40fb9820 7072 || (i.prefix[ADDR_PREFIX]
db51cc60 7073 && i.index_reg->reg_num != RegEiz
40fb9820 7074 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7075 ok = 0;
3e73aa7c
JH		 7076 }
7077 else
7078 {
7079 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7080 {
7081 /* 16bit checks. */
7082 if ((i.base_reg
40fb9820
L		 7083 && (!i.base_reg->reg_type.bitfield.reg16
7084 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7085 || (i.index_reg
40fb9820
L		 7086 && (!i.index_reg->reg_type.bitfield.reg16
7087 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7088 || !(i.base_reg
7089 && i.base_reg->reg_num < 6
7090 && i.index_reg->reg_num >= 6
7091 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7092 ok = 0;
7093 }
7094 else
e5cb08ac 7095 {
3e73aa7c
JH		 7096 /* 32bit checks. */
7097 if ((i.base_reg
40fb9820 7098 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7099 || (i.index_reg
db51cc60
L		 7100 && ((!i.index_reg->reg_type.bitfield.reg32
7101 && i.index_reg->reg_num != RegEiz)
40fb9820 7102 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7103 ok = 0;
3e73aa7c
JH		 7104 }
7105 }
7106 if (!ok)
24eab124
AM		 7107 {
7108#if INFER_ADDR_PREFIX
fc0763e6 7109 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7110 {
7111 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7112 i.prefixes += 1;
b23bac36
AM		 7113 /* Change the size of any displacement too. At most one of
7114 Disp16 or Disp32 is set.
7115 FIXME. There doesn't seem to be any real need for separate
7116 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7117 Removing them would probably clean up the code quite a lot. */
4eed87de 7118 if (flag_code != CODE_64BIT
40fb9820
L		 7119 && (i.types[this_operand].bitfield.disp16
7120 || i.types[this_operand].bitfield.disp32))
7121 i.types[this_operand]
c6fb90c8 7122 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7123 fudged = 1;
24eab124
AM		 7124 goto tryprefix;
7125 }
eecb386c 7126 if (fudged)
fc0763e6
JB		 7127 as_bad (_("`%s' is not a valid %s expression"),
7128 operand_string,
7129 kind);
eecb386c 7130 else
c388dee8 7131#endif
fc0763e6 7132 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7133 operand_string,
fc0763e6
JB		 7134 flag_code_names[i.prefix[ADDR_PREFIX]
7135 ? flag_code == CODE_32BIT
7136 ? CODE_16BIT
7137 : CODE_32BIT
7138 : flag_code],
7139 kind);
24eab124 7140 }
20f0a1fc 7141 return ok;
24eab124 7142}
252b5132 7143
fc0763e6 7144/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7145 on error. */
252b5132 7146
252b5132 7147static int
a7619375 7148i386_att_operand (char *operand_string)
252b5132 7149{
af6bdddf
AM		 7150 const reg_entry *r;
7151 char *end_op;
24eab124 7152 char *op_string = operand_string;
252b5132 7153
24eab124 7154 if (is_space_char (*op_string))
252b5132
RH		 7155 ++op_string;
7156
24eab124 7157 /* We check for an absolute prefix (differentiating,
47926f60 7158 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7159 if (*op_string == ABSOLUTE_PREFIX)
7160 {
7161 ++op_string;
7162 if (is_space_char (*op_string))
7163 ++op_string;
40fb9820 7164 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7165 }
252b5132 7166
47926f60 7167 /* Check if operand is a register. */
4d1bb795 7168 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7169 {
40fb9820
L		 7170 i386_operand_type temp;
7171
24eab124
AM		 7172 /* Check for a segment override by searching for ':' after a
7173 segment register. */
7174 op_string = end_op;
7175 if (is_space_char (*op_string))
7176 ++op_string;
40fb9820
L		 7177 if (*op_string == ':'
7178 && (r->reg_type.bitfield.sreg2
7179 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7180 {
7181 switch (r->reg_num)
7182 {
7183 case 0:
7184 i.seg[i.mem_operands] = &es;
7185 break;
7186 case 1:
7187 i.seg[i.mem_operands] = &cs;
7188 break;
7189 case 2:
7190 i.seg[i.mem_operands] = &ss;
7191 break;
7192 case 3:
7193 i.seg[i.mem_operands] = &ds;
7194 break;
7195 case 4:
7196 i.seg[i.mem_operands] = &fs;
7197 break;
7198 case 5:
7199 i.seg[i.mem_operands] = &gs;
7200 break;
7201 }
252b5132 7202
24eab124 7203 /* Skip the ':' and whitespace. */
252b5132
RH		 7204 ++op_string;
7205 if (is_space_char (*op_string))
24eab124 7206 ++op_string;
252b5132 7207
24eab124
AM		 7208 if (!is_digit_char (*op_string)
7209 && !is_identifier_char (*op_string)
7210 && *op_string != '('
7211 && *op_string != ABSOLUTE_PREFIX)
7212 {
7213 as_bad (_("bad memory operand `%s'"), op_string);
7214 return 0;
7215 }
47926f60 7216 /* Handle case of %es:*foo. */
24eab124
AM		 7217 if (*op_string == ABSOLUTE_PREFIX)
7218 {
7219 ++op_string;
7220 if (is_space_char (*op_string))
7221 ++op_string;
40fb9820 7222 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7223 }
7224 goto do_memory_reference;
7225 }
7226 if (*op_string)
7227 {
d0b47220 7228 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7229 return 0;
7230 }
40fb9820
L		 7231 temp = r->reg_type;
7232 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7233 i.types[this_operand] = operand_type_or (i.types[this_operand],
7234 temp);
7d5e4556 7235 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7236 i.op[this_operand].regs = r;
24eab124
AM		 7237 i.reg_operands++;
7238 }
af6bdddf
AM		 7239 else if (*op_string == REGISTER_PREFIX)
7240 {
7241 as_bad (_("bad register name `%s'"), op_string);
7242 return 0;
7243 }
24eab124 7244 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7245 {
24eab124 7246 ++op_string;
40fb9820 7247 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7248 {
d0b47220 7249 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7250 return 0;
7251 }
7252 if (!i386_immediate (op_string))
7253 return 0;
7254 }
7255 else if (is_digit_char (*op_string)
7256 || is_identifier_char (*op_string)
e5cb08ac 7257 || *op_string == '(')
24eab124 7258 {
47926f60 7259 /* This is a memory reference of some sort. */
af6bdddf 7260 char *base_string;
252b5132 7261
47926f60 7262 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7263 char *displacement_string_start;
7264 char *displacement_string_end;
252b5132 7265
24eab124 7266 do_memory_reference:
24eab124 7267 if ((i.mem_operands == 1
40fb9820 7268 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7269 || i.mem_operands == 2)
7270 {
7271 as_bad (_("too many memory references for `%s'"),
7272 current_templates->start->name);
7273 return 0;
7274 }
252b5132 7275
24eab124
AM		 7276 /* Check for base index form. We detect the base index form by
7277 looking for an ')' at the end of the operand, searching
7278 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7279 after the '('. */
af6bdddf 7280 base_string = op_string + strlen (op_string);
c3332e24 7281
af6bdddf
AM		 7282 --base_string;
7283 if (is_space_char (*base_string))
7284 --base_string;
252b5132 7285
47926f60 7286 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7287 displacement_string_start = op_string;
7288 displacement_string_end = base_string + 1;
252b5132 7289
24eab124
AM		 7290 if (*base_string == ')')
7291 {
af6bdddf 7292 char *temp_string;
24eab124
AM		 7293 unsigned int parens_balanced = 1;
7294 /* We've already checked that the number of left & right ()'s are
47926f60 7295 equal, so this loop will not be infinite. */
24eab124
AM		 7296 do
7297 {
7298 base_string--;
7299 if (*base_string == ')')
7300 parens_balanced++;
7301 if (*base_string == '(')
7302 parens_balanced--;
7303 }
7304 while (parens_balanced);
c3332e24 7305
af6bdddf 7306 temp_string = base_string;
c3332e24 7307
24eab124 7308 /* Skip past '(' and whitespace. */
252b5132
RH		 7309 ++base_string;
7310 if (is_space_char (*base_string))
24eab124 7311 ++base_string;
252b5132 7312
af6bdddf 7313 if (*base_string == ','
4eed87de
AM		 7314 || ((i.base_reg = parse_register (base_string, &end_op))
7315 != NULL))
252b5132 7316 {
af6bdddf 7317 displacement_string_end = temp_string;
252b5132 7318
40fb9820 7319 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7320
af6bdddf 7321 if (i.base_reg)
24eab124 7322 {
24eab124
AM		 7323 base_string = end_op;
7324 if (is_space_char (*base_string))
7325 ++base_string;
af6bdddf
AM		 7326 }
7327
7328 /* There may be an index reg or scale factor here. */
7329 if (*base_string == ',')
7330 {
7331 ++base_string;
7332 if (is_space_char (*base_string))
7333 ++base_string;
7334
4eed87de
AM		 7335 if ((i.index_reg = parse_register (base_string, &end_op))
7336 != NULL)
24eab124 7337 {
af6bdddf 7338 base_string = end_op;
24eab124
AM		 7339 if (is_space_char (*base_string))
7340 ++base_string;
af6bdddf
AM		 7341 if (*base_string == ',')
7342 {
7343 ++base_string;
7344 if (is_space_char (*base_string))
7345 ++base_string;
7346 }
e5cb08ac 7347 else if (*base_string != ')')
af6bdddf 7348 {
4eed87de
AM		 7349 as_bad (_("expecting `,' or `)' "
7350 "after index register in `%s'"),
af6bdddf
AM		 7351 operand_string);
7352 return 0;
7353 }
24eab124 7354 }
af6bdddf 7355 else if (*base_string == REGISTER_PREFIX)
24eab124 7356 {
af6bdddf 7357 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7358 return 0;
7359 }
252b5132 7360
47926f60 7361 /* Check for scale factor. */
551c1ca1 7362 if (*base_string != ')')
af6bdddf 7363 {
551c1ca1
AM		 7364 char *end_scale = i386_scale (base_string);
7365
7366 if (!end_scale)
af6bdddf 7367 return 0;
24eab124 7368
551c1ca1 7369 base_string = end_scale;
af6bdddf
AM		 7370 if (is_space_char (*base_string))
7371 ++base_string;
7372 if (*base_string != ')')
7373 {
4eed87de
AM		 7374 as_bad (_("expecting `)' "
7375 "after scale factor in `%s'"),
af6bdddf
AM		 7376 operand_string);
7377 return 0;
7378 }
7379 }
7380 else if (!i.index_reg)
24eab124 7381 {
4eed87de
AM		 7382 as_bad (_("expecting index register or scale factor "
7383 "after `,'; got '%c'"),
af6bdddf 7384 *base_string);
24eab124
AM		 7385 return 0;
7386 }
7387 }
af6bdddf 7388 else if (*base_string != ')')
24eab124 7389 {
4eed87de
AM		 7390 as_bad (_("expecting `,' or `)' "
7391 "after base register in `%s'"),
af6bdddf 7392 operand_string);
24eab124
AM		 7393 return 0;
7394 }
c3332e24 7395 }
af6bdddf 7396 else if (*base_string == REGISTER_PREFIX)
c3332e24 7397 {
af6bdddf 7398 as_bad (_("bad register name `%s'"), base_string);
24eab124 7399 return 0;
c3332e24 7400 }
24eab124
AM		 7401 }
7402
7403 /* If there's an expression beginning the operand, parse it,
7404 assuming displacement_string_start and
7405 displacement_string_end are meaningful. */
7406 if (displacement_string_start != displacement_string_end)
7407 {
7408 if (!i386_displacement (displacement_string_start,
7409 displacement_string_end))
7410 return 0;
7411 }
7412
7413 /* Special case for (%dx) while doing input/output op. */
7414 if (i.base_reg
0dfbf9d7
L		 7415 && operand_type_equal (&i.base_reg->reg_type,
7416 &reg16_inoutportreg)
24eab124
AM		 7417 && i.index_reg == 0
7418 && i.log2_scale_factor == 0
7419 && i.seg[i.mem_operands] == 0
40fb9820 7420 && !operand_type_check (i.types[this_operand], disp))
24eab124 7421 {
65da13b5 7422 i.types[this_operand] = inoutportreg;
24eab124
AM		 7423 return 1;
7424 }
7425
eecb386c
AM		 7426 if (i386_index_check (operand_string) == 0)
7427 return 0;
5c07affc 7428 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7429 i.mem_operands++;
7430 }
7431 else
ce8a8b2f
AM		 7432 {
7433 /* It's not a memory operand; argh! */
24eab124
AM		 7434 as_bad (_("invalid char %s beginning operand %d `%s'"),
7435 output_invalid (*op_string),
7436 this_operand + 1,
7437 op_string);
7438 return 0;
7439 }
47926f60 7440 return 1; /* Normal return. */
252b5132
RH		 7441}
7442\f
ee7fcc42
AM		 7443/* md_estimate_size_before_relax()
7444
7445 Called just before relax() for rs_machine_dependent frags. The x86
7446 assembler uses these frags to handle variable size jump
7447 instructions.
7448
7449 Any symbol that is now undefined will not become defined.
7450 Return the correct fr_subtype in the frag.
7451 Return the initial "guess for variable size of frag" to caller.
7452 The guess is actually the growth beyond the fixed part. Whatever
7453 we do to grow the fixed or variable part contributes to our
7454 returned value. */
7455
252b5132
RH		 7456int
7457md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7458 fragS *fragP;
7459 segT segment;
252b5132 7460{
252b5132 7461 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7462 check for un-relaxable symbols. On an ELF system, we can't relax
7463 an externally visible symbol, because it may be overridden by a
7464 shared library. */
7465 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7466#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7467 || (IS_ELF
31312f95 7468 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7469 || S_IS_WEAK (fragP->fr_symbol)
7470 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7471 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7472#endif
7473#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7474 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7475 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7476#endif
7477 )
252b5132 7478 {
b98ef147
AM		 7479 /* Symbol is undefined in this segment, or we need to keep a
7480 reloc so that weak symbols can be overridden. */
7481 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7482 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7483 unsigned char *opcode;
7484 int old_fr_fix;
f6af82bd 7485
ee7fcc42 7486 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7487 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7488 else if (size == 2)
f6af82bd
AM		 7489 reloc_type = BFD_RELOC_16_PCREL;
7490 else
7491 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7492
ee7fcc42
AM		 7493 old_fr_fix = fragP->fr_fix;
7494 opcode = (unsigned char *) fragP->fr_opcode;
7495
fddf5b5b 7496 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7497 {
fddf5b5b
AM		 7498 case UNCOND_JUMP:
7499 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7500 opcode[0] = 0xe9;
252b5132 7501 fragP->fr_fix += size;
062cd5e7
AS		 7502 fix_new (fragP, old_fr_fix, size,
7503 fragP->fr_symbol,
7504 fragP->fr_offset, 1,
7505 reloc_type);
252b5132
RH		 7506 break;
7507
fddf5b5b 7508 case COND_JUMP86:
412167cb
AM		 7509 if (size == 2
7510 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7511 {
7512 /* Negate the condition, and branch past an
7513 unconditional jump. */
7514 opcode[0] ^= 1;
7515 opcode[1] = 3;
7516 /* Insert an unconditional jump. */
7517 opcode[2] = 0xe9;
7518 /* We added two extra opcode bytes, and have a two byte
7519 offset. */
7520 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7521 fix_new (fragP, old_fr_fix + 2, 2,
7522 fragP->fr_symbol,
7523 fragP->fr_offset, 1,
7524 reloc_type);
fddf5b5b
AM		 7525 break;
7526 }
7527 /* Fall through. */
7528
7529 case COND_JUMP:
412167cb
AM		 7530 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7531 {
3e02c1cc
AM		 7532 fixS *fixP;
7533
412167cb 7534 fragP->fr_fix += 1;
3e02c1cc
AM		 7535 fixP = fix_new (fragP, old_fr_fix, 1,
7536 fragP->fr_symbol,
7537 fragP->fr_offset, 1,
7538 BFD_RELOC_8_PCREL);
7539 fixP->fx_signed = 1;
412167cb
AM		 7540 break;
7541 }
93c2a809 7542
24eab124 7543 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7544 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7545 opcode[1] = opcode[0] + 0x10;
f6af82bd 7546 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7547 /* We've added an opcode byte. */
7548 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7549 fix_new (fragP, old_fr_fix + 1, size,
7550 fragP->fr_symbol,
7551 fragP->fr_offset, 1,
7552 reloc_type);
252b5132 7553 break;
fddf5b5b
AM		 7554
7555 default:
7556 BAD_CASE (fragP->fr_subtype);
7557 break;
252b5132
RH		 7558 }
7559 frag_wane (fragP);
ee7fcc42 7560 return fragP->fr_fix - old_fr_fix;
252b5132 7561 }
93c2a809 7562
93c2a809
AM		 7563 /* Guess size depending on current relax state. Initially the relax
7564 state will correspond to a short jump and we return 1, because
7565 the variable part of the frag (the branch offset) is one byte
7566 long. However, we can relax a section more than once and in that
7567 case we must either set fr_subtype back to the unrelaxed state,
7568 or return the value for the appropriate branch. */
7569 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7570}
7571
47926f60
KH		 7572/* Called after relax() is finished.
7573
7574 In: Address of frag.
7575 fr_type == rs_machine_dependent.
7576 fr_subtype is what the address relaxed to.
7577
7578 Out: Any fixSs and constants are set up.
7579 Caller will turn frag into a ".space 0". */
7580
252b5132
RH		 7581void
7582md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7583 bfd *abfd ATTRIBUTE_UNUSED;
7584 segT sec ATTRIBUTE_UNUSED;
29b0f896 7585 fragS *fragP;
252b5132 7586{
29b0f896 7587 unsigned char *opcode;
252b5132 7588 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7589 offsetT target_address;
7590 offsetT opcode_address;
252b5132 7591 unsigned int extension = 0;
847f7ad4 7592 offsetT displacement_from_opcode_start;
252b5132
RH		 7593
7594 opcode = (unsigned char *) fragP->fr_opcode;
7595
47926f60 7596 /* Address we want to reach in file space. */
252b5132 7597 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7598
47926f60 7599 /* Address opcode resides at in file space. */
252b5132
RH		 7600 opcode_address = fragP->fr_address + fragP->fr_fix;
7601
47926f60 7602 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7603 displacement_from_opcode_start = target_address - opcode_address;
7604
fddf5b5b 7605 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7606 {
47926f60
KH		 7607 /* Don't have to change opcode. */
7608 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7609 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7610 }
7611 else
7612 {
7613 if (no_cond_jump_promotion
7614 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7615 as_warn_where (fragP->fr_file, fragP->fr_line,
7616 _("long jump required"));
252b5132 7617
fddf5b5b
AM		 7618 switch (fragP->fr_subtype)
7619 {
7620 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7621 extension = 4; /* 1 opcode + 4 displacement */
7622 opcode[0] = 0xe9;
7623 where_to_put_displacement = &opcode[1];
7624 break;
252b5132 7625
fddf5b5b
AM		 7626 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7627 extension = 2; /* 1 opcode + 2 displacement */
7628 opcode[0] = 0xe9;
7629 where_to_put_displacement = &opcode[1];
7630 break;
252b5132 7631
fddf5b5b
AM		 7632 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7633 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7634 extension = 5; /* 2 opcode + 4 displacement */
7635 opcode[1] = opcode[0] + 0x10;
7636 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7637 where_to_put_displacement = &opcode[2];
7638 break;
252b5132 7639
fddf5b5b
AM		 7640 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7641 extension = 3; /* 2 opcode + 2 displacement */
7642 opcode[1] = opcode[0] + 0x10;
7643 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7644 where_to_put_displacement = &opcode[2];
7645 break;
252b5132 7646
fddf5b5b
AM		 7647 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7648 extension = 4;
7649 opcode[0] ^= 1;
7650 opcode[1] = 3;
7651 opcode[2] = 0xe9;
7652 where_to_put_displacement = &opcode[3];
7653 break;
7654
7655 default:
7656 BAD_CASE (fragP->fr_subtype);
7657 break;
7658 }
252b5132 7659 }
fddf5b5b 7660
7b81dfbb
AJ		 7661 /* If size if less then four we are sure that the operand fits,
7662 but if it's 4, then it could be that the displacement is larger
7663 then -/+ 2GB. */
7664 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7665 && object_64bit
7666 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7667 + ((addressT) 1 << 31))
7668 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7669 {
7670 as_bad_where (fragP->fr_file, fragP->fr_line,
7671 _("jump target out of range"));
7672 /* Make us emit 0. */
7673 displacement_from_opcode_start = extension;
7674 }
47926f60 7675 /* Now put displacement after opcode. */
252b5132
RH		 7676 md_number_to_chars ((char *) where_to_put_displacement,
7677 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7678 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7679 fragP->fr_fix += extension;
7680}
7681\f
252b5132
RH		 7682/* Apply a fixup (fixS) to segment data, once it has been determined
7683 by our caller that we have all the info we need to fix it up.
7684
7685 On the 386, immediates, displacements, and data pointers are all in
7686 the same (little-endian) format, so we don't need to care about which
7687 we are handling. */
7688
94f592af 7689void
55cf6793 7690md_apply_fix (fixP, valP, seg)
47926f60
KH		 7691 /* The fix we're to put in. */
7692 fixS *fixP;
47926f60 7693 /* Pointer to the value of the bits. */
c6682705 7694 valueT *valP;
47926f60
KH		 7695 /* Segment fix is from. */
7696 segT seg ATTRIBUTE_UNUSED;
252b5132 7697{
94f592af 7698 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7699 valueT value = *valP;
252b5132 7700
f86103b7 7701#if !defined (TE_Mach)
93382f6d
AM		 7702 if (fixP->fx_pcrel)
7703 {
7704 switch (fixP->fx_r_type)
7705 {
5865bb77
ILT		 7706 default:
7707 break;
7708
d6ab8113
JB		 7709 case BFD_RELOC_64:
7710 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7711 break;
93382f6d 7712 case BFD_RELOC_32:
ae8887b5 7713 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7714 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7715 break;
7716 case BFD_RELOC_16:
7717 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7718 break;
7719 case BFD_RELOC_8:
7720 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7721 break;
7722 }
7723 }
252b5132 7724
a161fe53 7725 if (fixP->fx_addsy != NULL
31312f95 7726 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7727 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7728 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7729 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7730 && !use_rela_relocations)
252b5132 7731 {
31312f95
AM		 7732 /* This is a hack. There should be a better way to handle this.
7733 This covers for the fact that bfd_install_relocation will
7734 subtract the current location (for partial_inplace, PC relative
7735 relocations); see more below. */
252b5132 7736#ifndef OBJ_AOUT
718ddfc0 7737 if (IS_ELF
252b5132
RH		 7738#ifdef TE_PE
7739 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7740#endif
7741 )
7742 value += fixP->fx_where + fixP->fx_frag->fr_address;
7743#endif
7744#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7745 if (IS_ELF)
252b5132 7746 {
6539b54b 7747 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7748
6539b54b 7749 if ((sym_seg == seg
2f66722d 7750 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7751 && sym_seg != absolute_section))
af65af87 7752 && !generic_force_reloc (fixP))
2f66722d
AM		 7753 {
7754 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7755 bfd_install_relocation subtracts them out again. I think
7756 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7757 it. FIXME. */
7758 value += fixP->fx_where + fixP->fx_frag->fr_address;
7759 }
252b5132
RH		 7760 }
7761#endif
7762#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7763 /* For some reason, the PE format does not store a
7764 section address offset for a PC relative symbol. */
7765 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7766 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7767 value += md_pcrel_from (fixP);
7768#endif
7769 }
fbeb56a4
DK		 7770#if defined (OBJ_COFF) && defined (TE_PE)
7771 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7772 {
7773 value -= S_GET_VALUE (fixP->fx_addsy);
7774 }
7775#endif
252b5132
RH		 7776
7777 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7778 and we must not disappoint it. */
252b5132 7779#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7780 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7781 switch (fixP->fx_r_type)
7782 {
7783 case BFD_RELOC_386_PLT32:
3e73aa7c 7784 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7785 /* Make the jump instruction point to the address of the operand. At
7786 runtime we merely add the offset to the actual PLT entry. */
7787 value = -4;
7788 break;
31312f95 7789
13ae64f3
JJ		 7790 case BFD_RELOC_386_TLS_GD:
7791 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7792 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7793 case BFD_RELOC_386_TLS_IE:
7794 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7795 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7796 case BFD_RELOC_X86_64_TLSGD:
7797 case BFD_RELOC_X86_64_TLSLD:
7798 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7799 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7800 value = 0; /* Fully resolved at runtime. No addend. */
7801 /* Fallthrough */
7802 case BFD_RELOC_386_TLS_LE:
7803 case BFD_RELOC_386_TLS_LDO_32:
7804 case BFD_RELOC_386_TLS_LE_32:
7805 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7806 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7807 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7808 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7809 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7810 break;
7811
67a4f2b7
AO		 7812 case BFD_RELOC_386_TLS_DESC_CALL:
7813 case BFD_RELOC_X86_64_TLSDESC_CALL:
7814 value = 0; /* Fully resolved at runtime. No addend. */
7815 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7816 fixP->fx_done = 0;
7817 return;
7818
00f7efb6
JJ		 7819 case BFD_RELOC_386_GOT32:
7820 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7821 value = 0; /* Fully resolved at runtime. No addend. */
7822 break;
47926f60
KH		 7823
7824 case BFD_RELOC_VTABLE_INHERIT:
7825 case BFD_RELOC_VTABLE_ENTRY:
7826 fixP->fx_done = 0;
94f592af 7827 return;
47926f60
KH		 7828
7829 default:
7830 break;
7831 }
7832#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7833 *valP = value;
f86103b7 7834#endif /* !defined (TE_Mach) */
3e73aa7c 7835
3e73aa7c 7836 /* Are we finished with this relocation now? */
c6682705 7837 if (fixP->fx_addsy == NULL)
3e73aa7c 7838 fixP->fx_done = 1;
fbeb56a4
DK		 7839#if defined (OBJ_COFF) && defined (TE_PE)
7840 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7841 {
7842 fixP->fx_done = 0;
7843 /* Remember value for tc_gen_reloc. */
7844 fixP->fx_addnumber = value;
7845 /* Clear out the frag for now. */
7846 value = 0;
7847 }
7848#endif
3e73aa7c
JH		 7849 else if (use_rela_relocations)
7850 {
7851 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7852 /* Remember value for tc_gen_reloc. */
7853 fixP->fx_addnumber = value;
3e73aa7c
JH		 7854 value = 0;
7855 }
f86103b7 7856
94f592af 7857 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7858}
252b5132 7859\f
252b5132 7860char *
499ac353 7861md_atof (int type, char *litP, int *sizeP)
252b5132 7862{
499ac353
NC		 7863 /* This outputs the LITTLENUMs in REVERSE order;
7864 in accord with the bigendian 386. */
7865 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7866}
7867\f
2d545b82 7868static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7869
252b5132 7870static char *
e3bb37b5 7871output_invalid (int c)
252b5132 7872{
3882b010 7873 if (ISPRINT (c))
f9f21a03
L		 7874 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7875 "'%c'", c);
252b5132 7876 else
f9f21a03 7877 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7878 "(0x%x)", (unsigned char) c);
252b5132
RH		 7879 return output_invalid_buf;
7880}
7881
af6bdddf 7882/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7883
7884static const reg_entry *
4d1bb795 7885parse_real_register (char *reg_string, char **end_op)
252b5132 7886{
af6bdddf
AM		 7887 char *s = reg_string;
7888 char *p;
252b5132
RH		 7889 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7890 const reg_entry *r;
7891
7892 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7893 if (*s == REGISTER_PREFIX)
7894 ++s;
7895
7896 if (is_space_char (*s))
7897 ++s;
7898
7899 p = reg_name_given;
af6bdddf 7900 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7901 {
7902 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7903 return (const reg_entry *) NULL;
7904 s++;
252b5132
RH		 7905 }
7906
6588847e
DN		 7907 /* For naked regs, make sure that we are not dealing with an identifier.
7908 This prevents confusing an identifier like `eax_var' with register
7909 `eax'. */
7910 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7911 return (const reg_entry *) NULL;
7912
af6bdddf 7913 *end_op = s;
252b5132
RH		 7914
7915 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7916
5f47d35b 7917 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7918 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7919 {
5f47d35b
AM		 7920 if (is_space_char (*s))
7921 ++s;
7922 if (*s == '(')
7923 {
af6bdddf 7924 ++s;
5f47d35b
AM		 7925 if (is_space_char (*s))
7926 ++s;
7927 if (*s >= '0' && *s <= '7')
7928 {
db557034 7929 int fpr = *s - '0';
af6bdddf 7930 ++s;
5f47d35b
AM		 7931 if (is_space_char (*s))
7932 ++s;
7933 if (*s == ')')
7934 {
7935 *end_op = s + 1;
1e9cc1c2 7936 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7937 know (r);
7938 return r + fpr;
5f47d35b 7939 }
5f47d35b 7940 }
47926f60 7941 /* We have "%st(" then garbage. */
5f47d35b
AM		 7942 return (const reg_entry *) NULL;
7943 }
7944 }
7945
a60de03c
JB		 7946 if (r == NULL || allow_pseudo_reg)
7947 return r;
7948
0dfbf9d7 7949 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7950 return (const reg_entry *) NULL;
7951
192dc9c6
JB		 7952 if ((r->reg_type.bitfield.reg32
7953 || r->reg_type.bitfield.sreg3
7954 || r->reg_type.bitfield.control
7955 || r->reg_type.bitfield.debug
7956 || r->reg_type.bitfield.test)
7957 && !cpu_arch_flags.bitfield.cpui386)
7958 return (const reg_entry *) NULL;
7959
309d3373
JB		 7960 if (r->reg_type.bitfield.floatreg
7961 && !cpu_arch_flags.bitfield.cpu8087
7962 && !cpu_arch_flags.bitfield.cpu287
7963 && !cpu_arch_flags.bitfield.cpu387)
7964 return (const reg_entry *) NULL;
7965
192dc9c6
JB		 7966 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7967 return (const reg_entry *) NULL;
7968
7969 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7970 return (const reg_entry *) NULL;
7971
40f12533
L		 7972 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7973 return (const reg_entry *) NULL;
7974
db51cc60 7975 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7976 if (!allow_index_reg
db51cc60
L		 7977 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7978 return (const reg_entry *) NULL;
7979
a60de03c
JB		 7980 if (((r->reg_flags & (RegRex64 | RegRex))
7981 || r->reg_type.bitfield.reg64)
40fb9820 7982 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7983 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7984 && flag_code != CODE_64BIT)
20f0a1fc 7985 return (const reg_entry *) NULL;
1ae00879 7986
b7240065
JB		 7987 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7988 return (const reg_entry *) NULL;
7989
252b5132
RH		 7990 return r;
7991}
4d1bb795
JB		 7992
7993/* REG_STRING starts *before* REGISTER_PREFIX. */
7994
7995static const reg_entry *
7996parse_register (char *reg_string, char **end_op)
7997{
7998 const reg_entry *r;
7999
8000 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8001 r = parse_real_register (reg_string, end_op);
8002 else
8003 r = NULL;
8004 if (!r)
8005 {
8006 char *save = input_line_pointer;
8007 char c;
8008 symbolS *symbolP;
8009
8010 input_line_pointer = reg_string;
8011 c = get_symbol_end ();
8012 symbolP = symbol_find (reg_string);
8013 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8014 {
8015 const expressionS *e = symbol_get_value_expression (symbolP);
8016
0398aac5 8017 know (e->X_op == O_register);
4eed87de 8018 know (e->X_add_number >= 0
c3fe08fa 8019 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8020 r = i386_regtab + e->X_add_number;
8021 *end_op = input_line_pointer;
8022 }
8023 *input_line_pointer = c;
8024 input_line_pointer = save;
8025 }
8026 return r;
8027}
8028
8029int
8030i386_parse_name (char *name, expressionS *e, char *nextcharP)
8031{
8032 const reg_entry *r;
8033 char *end = input_line_pointer;
8034
8035 *end = *nextcharP;
8036 r = parse_register (name, &input_line_pointer);
8037 if (r && end <= input_line_pointer)
8038 {
8039 *nextcharP = *input_line_pointer;
8040 *input_line_pointer = 0;
8041 e->X_op = O_register;
8042 e->X_add_number = r - i386_regtab;
8043 return 1;
8044 }
8045 input_line_pointer = end;
8046 *end = 0;
ee86248c 8047 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8048}
8049
8050void
8051md_operand (expressionS *e)
8052{
ee86248c
JB		 8053 char *end;
8054 const reg_entry *r;
4d1bb795 8055
ee86248c
JB		 8056 switch (*input_line_pointer)
8057 {
8058 case REGISTER_PREFIX:
8059 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8060 if (r)
8061 {
8062 e->X_op = O_register;
8063 e->X_add_number = r - i386_regtab;
8064 input_line_pointer = end;
8065 }
ee86248c
JB		 8066 break;
8067
8068 case '[':
9c2799c2 8069 gas_assert (intel_syntax);
ee86248c
JB		 8070 end = input_line_pointer++;
8071 expression (e);
8072 if (*input_line_pointer == ']')
8073 {
8074 ++input_line_pointer;
8075 e->X_op_symbol = make_expr_symbol (e);
8076 e->X_add_symbol = NULL;
8077 e->X_add_number = 0;
8078 e->X_op = O_index;
8079 }
8080 else
8081 {
8082 e->X_op = O_absent;
8083 input_line_pointer = end;
8084 }
8085 break;
4d1bb795
JB		 8086 }
8087}
8088
252b5132 8089\f
4cc782b5 8090#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8091const char *md_shortopts = "kVQ:sqn";
252b5132 8092#else
12b55ccc 8093const char *md_shortopts = "qn";
252b5132 8094#endif
6e0b89ee 8095
3e73aa7c 8096#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8097#define OPTION_64 (OPTION_MD_BASE + 1)
8098#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8099#define OPTION_MARCH (OPTION_MD_BASE + 3)
8100#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8101#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8102#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8103#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8104#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8105#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8106#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8107#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8108#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
351f65ca 8109#define OPTION_N32 (OPTION_MD_BASE + 13)
b3b91714 8110
99ad8390
NC		 8111struct option md_longopts[] =
8112{
3e73aa7c 8113 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8114#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8115 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8116 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8117#endif
8118#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8119 {"n32", no_argument, NULL, OPTION_N32},
6e0b89ee 8120#endif
b3b91714 8121 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8122 {"march", required_argument, NULL, OPTION_MARCH},
8123 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8124 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8125 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8126 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8127 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8128 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8129 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8130 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8131 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8132 {NULL, no_argument, NULL, 0}
8133};
8134size_t md_longopts_size = sizeof (md_longopts);
8135
8136int
9103f4f4 8137md_parse_option (int c, char *arg)
252b5132 8138{
91d6fa6a 8139 unsigned int j;
6305a203 8140 char *arch, *next;
9103f4f4 8141
252b5132
RH		 8142 switch (c)
8143 {
12b55ccc
L		 8144 case 'n':
8145 optimize_align_code = 0;
8146 break;
8147
a38cf1db
AM		 8148 case 'q':
8149 quiet_warnings = 1;
252b5132
RH		 8150 break;
8151
8152#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8153 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8154 should be emitted or not. FIXME: Not implemented. */
8155 case 'Q':
252b5132
RH		 8156 break;
8157
8158 /* -V: SVR4 argument to print version ID. */
8159 case 'V':
8160 print_version_id ();
8161 break;
8162
a38cf1db
AM		 8163 /* -k: Ignore for FreeBSD compatibility. */
8164 case 'k':
252b5132 8165 break;
4cc782b5
ILT		 8166
8167 case 's':
8168 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8169 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8170 break;
99ad8390 8171#endif
321098a5
L		 8172#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8173 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8174 case OPTION_64:
8175 {
8176 const char **list, **l;
8177
3e73aa7c
JH		 8178 list = bfd_target_list ();
8179 for (l = list; *l != NULL; l++)
8620418b 8180 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8181 || strcmp (*l, "coff-x86-64") == 0
8182 || strcmp (*l, "pe-x86-64") == 0
8183 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8184 {
8185 default_arch = "x86_64";
8186 break;
8187 }
3e73aa7c 8188 if (*l == NULL)
6e0b89ee 8189 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8190 free (list);
8191 }
8192 break;
8193#endif
252b5132 8194
351f65ca
L		 8195#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8196 case OPTION_N32:
8197 if (IS_ELF)
8198 {
8199 const char **list, **l;
8200
8201 list = bfd_target_list ();
8202 for (l = list; *l != NULL; l++)
8203 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8204 {
8205 default_arch = "x86_64:32";
8206 break;
8207 }
8208 if (*l == NULL)
8209 as_fatal (_("No compiled in support for 32bit x86_64"));
8210 free (list);
8211 }
8212 else
8213 as_fatal (_("32bit x86_64 is only supported for ELF"));
8214 break;
8215#endif
8216
6e0b89ee
AM		 8217 case OPTION_32:
8218 default_arch = "i386";
8219 break;
8220
b3b91714
AM		 8221 case OPTION_DIVIDE:
8222#ifdef SVR4_COMMENT_CHARS
8223 {
8224 char *n, *t;
8225 const char *s;
8226
8227 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8228 t = n;
8229 for (s = i386_comment_chars; *s != '\0'; s++)
8230 if (*s != '/')
8231 *t++ = *s;
8232 *t = '\0';
8233 i386_comment_chars = n;
8234 }
8235#endif
8236 break;
8237
9103f4f4 8238 case OPTION_MARCH:
6305a203
L		 8239 arch = xstrdup (arg);
8240 do
9103f4f4 8241 {
6305a203
L		 8242 if (*arch == '.')
8243 as_fatal (_("Invalid -march= option: `%s'"), arg);
8244 next = strchr (arch, '+');
8245 if (next)
8246 *next++ = '\0';
91d6fa6a 8247 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8248 {
91d6fa6a 8249 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8250 {
6305a203 8251 /* Processor. */
1ded5609
JB		 8252 if (! cpu_arch[j].flags.bitfield.cpui386)
8253 continue;
8254
91d6fa6a 8255 cpu_arch_name = cpu_arch[j].name;
6305a203 8256 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8257 cpu_arch_flags = cpu_arch[j].flags;
8258 cpu_arch_isa = cpu_arch[j].type;
8259 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8260 if (!cpu_arch_tune_set)
8261 {
8262 cpu_arch_tune = cpu_arch_isa;
8263 cpu_arch_tune_flags = cpu_arch_isa_flags;
8264 }
8265 break;
8266 }
91d6fa6a
NC		 8267 else if (*cpu_arch [j].name == '.'
8268 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8269 {
8270 /* ISA entension. */
8271 i386_cpu_flags flags;
309d3373 8272
49021df2 8273 if (!cpu_arch[j].negated)
309d3373 8274 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8275 cpu_arch[j].flags);
309d3373
JB		 8276 else
8277 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8278 cpu_arch[j].flags);
0dfbf9d7 8279 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8280 {
8281 if (cpu_sub_arch_name)
8282 {
8283 char *name = cpu_sub_arch_name;
8284 cpu_sub_arch_name = concat (name,
91d6fa6a 8285 cpu_arch[j].name,
1bf57e9f 8286 (const char *) NULL);
6305a203
L		 8287 free (name);
8288 }
8289 else
91d6fa6a 8290 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8291 cpu_arch_flags = flags;
8292 }
8293 break;
ccc9c027 8294 }
9103f4f4 8295 }
6305a203 8296
91d6fa6a 8297 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8298 as_fatal (_("Invalid -march= option: `%s'"), arg);
8299
8300 arch = next;
9103f4f4 8301 }
6305a203 8302 while (next != NULL );
9103f4f4
L		 8303 break;
8304
8305 case OPTION_MTUNE:
8306 if (*arg == '.')
8307 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8308 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8309 {
91d6fa6a 8310 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8311 {
ccc9c027 8312 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8313 cpu_arch_tune = cpu_arch [j].type;
8314 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8315 break;
8316 }
8317 }
91d6fa6a 8318 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8319 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8320 break;
8321
1efbbeb4
L		 8322 case OPTION_MMNEMONIC:
8323 if (strcasecmp (arg, "att") == 0)
8324 intel_mnemonic = 0;
8325 else if (strcasecmp (arg, "intel") == 0)
8326 intel_mnemonic = 1;
8327 else
8328 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8329 break;
8330
8331 case OPTION_MSYNTAX:
8332 if (strcasecmp (arg, "att") == 0)
8333 intel_syntax = 0;
8334 else if (strcasecmp (arg, "intel") == 0)
8335 intel_syntax = 1;
8336 else
8337 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8338 break;
8339
8340 case OPTION_MINDEX_REG:
8341 allow_index_reg = 1;
8342 break;
8343
8344 case OPTION_MNAKED_REG:
8345 allow_naked_reg = 1;
8346 break;
8347
8348 case OPTION_MOLD_GCC:
8349 old_gcc = 1;
1efbbeb4
L		 8350 break;
8351
c0f3af97
L		 8352 case OPTION_MSSE2AVX:
8353 sse2avx = 1;
8354 break;
8355
daf50ae7
L		 8356 case OPTION_MSSE_CHECK:
8357 if (strcasecmp (arg, "error") == 0)
8358 sse_check = sse_check_error;
8359 else if (strcasecmp (arg, "warning") == 0)
8360 sse_check = sse_check_warning;
8361 else if (strcasecmp (arg, "none") == 0)
8362 sse_check = sse_check_none;
8363 else
8364 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8365 break;
8366
539f890d
L		 8367 case OPTION_MAVXSCALAR:
8368 if (strcasecmp (arg, "128") == 0)
8369 avxscalar = vex128;
8370 else if (strcasecmp (arg, "256") == 0)
8371 avxscalar = vex256;
8372 else
8373 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8374 break;
8375
252b5132
RH		 8376 default:
8377 return 0;
8378 }
8379 return 1;
8380}
8381
8a2c8fef
L		 8382#define MESSAGE_TEMPLATE \
8383" "
8384
8385static void
1ded5609 8386show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8387{
8388 static char message[] = MESSAGE_TEMPLATE;
8389 char *start = message + 27;
8390 char *p;
8391 int size = sizeof (MESSAGE_TEMPLATE);
8392 int left;
8393 const char *name;
8394 int len;
8395 unsigned int j;
8396
8397 p = start;
8398 left = size - (start - message);
8399 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8400 {
8401 /* Should it be skipped? */
8402 if (cpu_arch [j].skip)
8403 continue;
8404
8405 name = cpu_arch [j].name;
8406 len = cpu_arch [j].len;
8407 if (*name == '.')
8408 {
8409 /* It is an extension. Skip if we aren't asked to show it. */
8410 if (ext)
8411 {
8412 name++;
8413 len--;
8414 }
8415 else
8416 continue;
8417 }
8418 else if (ext)
8419 {
8420 /* It is an processor. Skip if we show only extension. */
8421 continue;
8422 }
1ded5609
JB		 8423 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8424 {
8425 /* It is an impossible processor - skip. */
8426 continue;
8427 }
8a2c8fef
L		 8428
8429 /* Reserve 2 spaces for ", " or ",\0" */
8430 left -= len + 2;
8431
8432 /* Check if there is any room. */
8433 if (left >= 0)
8434 {
8435 if (p != start)
8436 {
8437 *p++ = ',';
8438 *p++ = ' ';
8439 }
8440 p = mempcpy (p, name, len);
8441 }
8442 else
8443 {
8444 /* Output the current message now and start a new one. */
8445 *p++ = ',';
8446 *p = '\0';
8447 fprintf (stream, "%s\n", message);
8448 p = start;
8449 left = size - (start - message) - len - 2;
8450
8451 gas_assert (left >= 0);
8452
8453 p = mempcpy (p, name, len);
8454 }
8455 }
8456
8457 *p = '\0';
8458 fprintf (stream, "%s\n", message);
8459}
8460
252b5132 8461void
8a2c8fef 8462md_show_usage (FILE *stream)
252b5132 8463{
4cc782b5
ILT		 8464#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8465 fprintf (stream, _("\
a38cf1db
AM		 8466 -Q ignored\n\
8467 -V print assembler version number\n\
b3b91714
AM		 8468 -k ignored\n"));
8469#endif
8470 fprintf (stream, _("\
12b55ccc 8471 -n Do not optimize code alignment\n\
b3b91714
AM		 8472 -q quieten some warnings\n"));
8473#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8474 fprintf (stream, _("\
a38cf1db 8475 -s ignored\n"));
b3b91714 8476#endif
321098a5
L		 8477#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8478 || defined (TE_PE) || defined (TE_PEP))
751d281c 8479 fprintf (stream, _("\
351f65ca 8480 --32/--64/--n32 generate 32bit/64bit/n32bit code\n"));
751d281c 8481#endif
b3b91714
AM		 8482#ifdef SVR4_COMMENT_CHARS
8483 fprintf (stream, _("\
8484 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8485#else
8486 fprintf (stream, _("\
b3b91714 8487 --divide ignored\n"));
4cc782b5 8488#endif
9103f4f4 8489 fprintf (stream, _("\
6305a203 8490 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8491 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8492 show_arch (stream, 0, 1);
8a2c8fef
L		 8493 fprintf (stream, _("\
8494 EXTENSION is combination of:\n"));
1ded5609 8495 show_arch (stream, 1, 0);
6305a203 8496 fprintf (stream, _("\
8a2c8fef 8497 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8498 show_arch (stream, 0, 0);
ba104c83 8499 fprintf (stream, _("\
c0f3af97
L		 8500 -msse2avx encode SSE instructions with VEX prefix\n"));
8501 fprintf (stream, _("\
daf50ae7
L		 8502 -msse-check=[none|error|warning]\n\
8503 check SSE instructions\n"));
8504 fprintf (stream, _("\
539f890d
L		 8505 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8506 length\n"));
8507 fprintf (stream, _("\
ba104c83
L		 8508 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8509 fprintf (stream, _("\
8510 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8511 fprintf (stream, _("\
8512 -mindex-reg support pseudo index registers\n"));
8513 fprintf (stream, _("\
8514 -mnaked-reg don't require `%%' prefix for registers\n"));
8515 fprintf (stream, _("\
8516 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8517}
8518
3e73aa7c 8519#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8520 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8521 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8522
8523/* Pick the target format to use. */
8524
47926f60 8525const char *
e3bb37b5 8526i386_target_format (void)
252b5132 8527{
351f65ca
L		 8528 if (!strncmp (default_arch, "x86_64", 6))
8529 {
8530 update_code_flag (CODE_64BIT, 1);
8531 if (default_arch[6] == '\0')
8532 x86_elf_abi = X86_64_LP64_ABI;
8533 else
8534 x86_elf_abi = X86_64_ILP32_ABI;
8535 }
3e73aa7c 8536 else if (!strcmp (default_arch, "i386"))
78f12dd3 8537 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8538 else
8539 as_fatal (_("Unknown architecture"));
89507696
JB		 8540
8541 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8542 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8543 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8544 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8545
252b5132
RH		 8546 switch (OUTPUT_FLAVOR)
8547 {
9384f2ff 8548#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8549 case bfd_target_aout_flavour:
47926f60 8550 return AOUT_TARGET_FORMAT;
4c63da97 8551#endif
9384f2ff
AM		 8552#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8553# if defined (TE_PE) || defined (TE_PEP)
8554 case bfd_target_coff_flavour:
8555 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8556# elif defined (TE_GO32)
0561d57c
JK		 8557 case bfd_target_coff_flavour:
8558 return "coff-go32";
9384f2ff 8559# else
252b5132
RH		 8560 case bfd_target_coff_flavour:
8561 return "coff-i386";
9384f2ff 8562# endif
4c63da97 8563#endif
3e73aa7c 8564#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8565 case bfd_target_elf_flavour:
3e73aa7c 8566 {
351f65ca
L		 8567 const char *format;
8568
8569 switch (x86_elf_abi)
4fa24527 8570 {
351f65ca
L		 8571 default:
8572 format = ELF_TARGET_FORMAT;
8573 break;
8574 case X86_64_LP64_ABI:
8575 use_rela_relocations = 1;
4fa24527 8576 object_64bit = 1;
351f65ca
L		 8577 format = ELF_TARGET_FORMAT64;
8578 break;
8579 case X86_64_ILP32_ABI:
4fa24527 8580 use_rela_relocations = 1;
351f65ca
L		 8581 object_64bit = 1;
8582 format = ELF_TARGET_FORMAT32;
8583 break;
4fa24527 8584 }
3632d14b 8585 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8586 {
351f65ca 8587 if (x86_elf_abi != X86_64_LP64_ABI)
8a9036a4
L		 8588 as_fatal (_("Intel L1OM is 64bit only"));
8589 return ELF_TARGET_L1OM_FORMAT;
8590 }
8591 else
351f65ca 8592 return format;
3e73aa7c 8593 }
e57f8c65
TG		 8594#endif
8595#if defined (OBJ_MACH_O)
8596 case bfd_target_mach_o_flavour:
8597 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8598#endif
252b5132
RH		 8599 default:
8600 abort ();
8601 return NULL;
8602 }
8603}
8604
47926f60 8605#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8606
8607#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8608void
8609i386_elf_emit_arch_note (void)
a847613f 8610{
718ddfc0 8611 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8612 {
8613 char *p;
8614 asection *seg = now_seg;
8615 subsegT subseg = now_subseg;
8616 Elf_Internal_Note i_note;
8617 Elf_External_Note e_note;
8618 asection *note_secp;
8619 int len;
8620
8621 /* Create the .note section. */
8622 note_secp = subseg_new (".note", 0);
8623 bfd_set_section_flags (stdoutput,
8624 note_secp,
8625 SEC_HAS_CONTENTS | SEC_READONLY);
8626
8627 /* Process the arch string. */
8628 len = strlen (cpu_arch_name);
8629
8630 i_note.namesz = len + 1;
8631 i_note.descsz = 0;
8632 i_note.type = NT_ARCH;
8633 p = frag_more (sizeof (e_note.namesz));
8634 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8635 p = frag_more (sizeof (e_note.descsz));
8636 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8637 p = frag_more (sizeof (e_note.type));
8638 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8639 p = frag_more (len + 1);
8640 strcpy (p, cpu_arch_name);
8641
8642 frag_align (2, 0, 0);
8643
8644 subseg_set (seg, subseg);
8645 }
8646}
8647#endif
252b5132 8648\f
252b5132
RH		 8649symbolS *
8650md_undefined_symbol (name)
8651 char *name;
8652{
18dc2407
ILT		 8653 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8654 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8655 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8656 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8657 {
8658 if (!GOT_symbol)
8659 {
8660 if (symbol_find (name))
8661 as_bad (_("GOT already in symbol table"));
8662 GOT_symbol = symbol_new (name, undefined_section,
8663 (valueT) 0, &zero_address_frag);
8664 };
8665 return GOT_symbol;
8666 }
252b5132
RH		 8667 return 0;
8668}
8669
8670/* Round up a section size to the appropriate boundary. */
47926f60 8671
252b5132
RH		 8672valueT
8673md_section_align (segment, size)
ab9da554 8674 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8675 valueT size;
8676{
4c63da97
AM		 8677#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8678 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8679 {
8680 /* For a.out, force the section size to be aligned. If we don't do
8681 this, BFD will align it for us, but it will not write out the
8682 final bytes of the section. This may be a bug in BFD, but it is
8683 easier to fix it here since that is how the other a.out targets
8684 work. */
8685 int align;
8686
8687 align = bfd_get_section_alignment (stdoutput, segment);
8688 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8689 }
252b5132
RH		 8690#endif
8691
8692 return size;
8693}
8694
8695/* On the i386, PC-relative offsets are relative to the start of the
8696 next instruction. That is, the address of the offset, plus its
8697 size, since the offset is always the last part of the insn. */
8698
8699long
e3bb37b5 8700md_pcrel_from (fixS *fixP)
252b5132
RH		 8701{
8702 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8703}
8704
8705#ifndef I386COFF
8706
8707static void
e3bb37b5 8708s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8709{
29b0f896 8710 int temp;
252b5132 8711
8a75718c
JB		 8712#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8713 if (IS_ELF)
8714 obj_elf_section_change_hook ();
8715#endif
252b5132
RH		 8716 temp = get_absolute_expression ();
8717 subseg_set (bss_section, (subsegT) temp);
8718 demand_empty_rest_of_line ();
8719}
8720
8721#endif
8722
252b5132 8723void
e3bb37b5 8724i386_validate_fix (fixS *fixp)
252b5132
RH		 8725{
8726 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8727 {
23df1078
JH		 8728 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8729 {
4fa24527 8730 if (!object_64bit)
23df1078
JH		 8731 abort ();
8732 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8733 }
8734 else
8735 {
4fa24527 8736 if (!object_64bit)
d6ab8113
JB		 8737 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8738 else
8739 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8740 }
252b5132
RH		 8741 fixp->fx_subsy = 0;
8742 }
8743}
8744
252b5132
RH		 8745arelent *
8746tc_gen_reloc (section, fixp)
ab9da554 8747 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8748 fixS *fixp;
8749{
8750 arelent *rel;
8751 bfd_reloc_code_real_type code;
8752
8753 switch (fixp->fx_r_type)
8754 {
3e73aa7c
JH		 8755 case BFD_RELOC_X86_64_PLT32:
8756 case BFD_RELOC_X86_64_GOT32:
8757 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8758 case BFD_RELOC_386_PLT32:
8759 case BFD_RELOC_386_GOT32:
8760 case BFD_RELOC_386_GOTOFF:
8761 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8762 case BFD_RELOC_386_TLS_GD:
8763 case BFD_RELOC_386_TLS_LDM:
8764 case BFD_RELOC_386_TLS_LDO_32:
8765 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8766 case BFD_RELOC_386_TLS_IE:
8767 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8768 case BFD_RELOC_386_TLS_LE_32:
8769 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8770 case BFD_RELOC_386_TLS_GOTDESC:
8771 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8772 case BFD_RELOC_X86_64_TLSGD:
8773 case BFD_RELOC_X86_64_TLSLD:
8774 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8775 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8776 case BFD_RELOC_X86_64_GOTTPOFF:
8777 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8778 case BFD_RELOC_X86_64_TPOFF64:
8779 case BFD_RELOC_X86_64_GOTOFF64:
8780 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8781 case BFD_RELOC_X86_64_GOT64:
8782 case BFD_RELOC_X86_64_GOTPCREL64:
8783 case BFD_RELOC_X86_64_GOTPC64:
8784 case BFD_RELOC_X86_64_GOTPLT64:
8785 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8786 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8787 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8788 case BFD_RELOC_RVA:
8789 case BFD_RELOC_VTABLE_ENTRY:
8790 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8791#ifdef TE_PE
8792 case BFD_RELOC_32_SECREL:
8793#endif
252b5132
RH		 8794 code = fixp->fx_r_type;
8795 break;
dbbaec26
L		 8796 case BFD_RELOC_X86_64_32S:
8797 if (!fixp->fx_pcrel)
8798 {
8799 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8800 code = fixp->fx_r_type;
8801 break;
8802 }
252b5132 8803 default:
93382f6d 8804 if (fixp->fx_pcrel)
252b5132 8805 {
93382f6d
AM		 8806 switch (fixp->fx_size)
8807 {
8808 default:
b091f402
AM		 8809 as_bad_where (fixp->fx_file, fixp->fx_line,
8810 _("can not do %d byte pc-relative relocation"),
8811 fixp->fx_size);
93382f6d
AM		 8812 code = BFD_RELOC_32_PCREL;
8813 break;
8814 case 1: code = BFD_RELOC_8_PCREL; break;
8815 case 2: code = BFD_RELOC_16_PCREL; break;
8816 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8817#ifdef BFD64
8818 case 8: code = BFD_RELOC_64_PCREL; break;
8819#endif
93382f6d
AM		 8820 }
8821 }
8822 else
8823 {
8824 switch (fixp->fx_size)
8825 {
8826 default:
b091f402
AM		 8827 as_bad_where (fixp->fx_file, fixp->fx_line,
8828 _("can not do %d byte relocation"),
8829 fixp->fx_size);
93382f6d
AM		 8830 code = BFD_RELOC_32;
8831 break;
8832 case 1: code = BFD_RELOC_8; break;
8833 case 2: code = BFD_RELOC_16; break;
8834 case 4: code = BFD_RELOC_32; break;
937149dd 8835#ifdef BFD64
3e73aa7c 8836 case 8: code = BFD_RELOC_64; break;
937149dd 8837#endif
93382f6d 8838 }
252b5132
RH		 8839 }
8840 break;
8841 }
252b5132 8842
d182319b
JB		 8843 if ((code == BFD_RELOC_32
8844 || code == BFD_RELOC_32_PCREL
8845 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8846 && GOT_symbol
8847 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8848 {
4fa24527 8849 if (!object_64bit)
d6ab8113
JB		 8850 code = BFD_RELOC_386_GOTPC;
8851 else
8852 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8853 }
7b81dfbb
AJ		 8854 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8855 && GOT_symbol
8856 && fixp->fx_addsy == GOT_symbol)
8857 {
8858 code = BFD_RELOC_X86_64_GOTPC64;
8859 }
252b5132
RH		 8860
8861 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8862 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8863 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8864
8865 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8866
3e73aa7c
JH		 8867 if (!use_rela_relocations)
8868 {
8869 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8870 vtable entry to be used in the relocation's section offset. */
8871 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8872 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8873#if defined (OBJ_COFF) && defined (TE_PE)
8874 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8875 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8876 else
8877#endif
c6682705 8878 rel->addend = 0;
3e73aa7c
JH		 8879 }
8880 /* Use the rela in 64bit mode. */
252b5132 8881 else
3e73aa7c 8882 {
062cd5e7
AS		 8883 if (!fixp->fx_pcrel)
8884 rel->addend = fixp->fx_offset;
8885 else
8886 switch (code)
8887 {
8888 case BFD_RELOC_X86_64_PLT32:
8889 case BFD_RELOC_X86_64_GOT32:
8890 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8891 case BFD_RELOC_X86_64_TLSGD:
8892 case BFD_RELOC_X86_64_TLSLD:
8893 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8894 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8895 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8896 rel->addend = fixp->fx_offset - fixp->fx_size;
8897 break;
8898 default:
8899 rel->addend = (section->vma
8900 - fixp->fx_size
8901 + fixp->fx_addnumber
8902 + md_pcrel_from (fixp));
8903 break;
8904 }
3e73aa7c
JH		 8905 }
8906
252b5132
RH		 8907 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8908 if (rel->howto == NULL)
8909 {
8910 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8911 _("cannot represent relocation type %s"),
252b5132
RH		 8912 bfd_get_reloc_code_name (code));
8913 /* Set howto to a garbage value so that we can keep going. */
8914 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8915 gas_assert (rel->howto != NULL);
252b5132
RH		 8916 }
8917
8918 return rel;
8919}
8920
ee86248c 8921#include "tc-i386-intel.c"
54cfded0 8922
a60de03c
JB		 8923void
8924tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8925{
a60de03c
JB		 8926 int saved_naked_reg;
8927 char saved_register_dot;
54cfded0 8928
a60de03c
JB		 8929 saved_naked_reg = allow_naked_reg;
8930 allow_naked_reg = 1;
8931 saved_register_dot = register_chars['.'];
8932 register_chars['.'] = '.';
8933 allow_pseudo_reg = 1;
8934 expression_and_evaluate (exp);
8935 allow_pseudo_reg = 0;
8936 register_chars['.'] = saved_register_dot;
8937 allow_naked_reg = saved_naked_reg;
8938
e96d56a1 8939 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8940 {
a60de03c
JB		 8941 if ((addressT) exp->X_add_number < i386_regtab_size)
8942 {
8943 exp->X_op = O_constant;
8944 exp->X_add_number = i386_regtab[exp->X_add_number]
8945 .dw2_regnum[flag_code >> 1];
8946 }
8947 else
8948 exp->X_op = O_illegal;
54cfded0 8949 }
54cfded0
AM		 8950}
8951
8952void
8953tc_x86_frame_initial_instructions (void)
8954{
a60de03c
JB		 8955 static unsigned int sp_regno[2];
8956
8957 if (!sp_regno[flag_code >> 1])
8958 {
8959 char *saved_input = input_line_pointer;
8960 char sp[][4] = {"esp", "rsp"};
8961 expressionS exp;
a4447b93 8962
a60de03c
JB		 8963 input_line_pointer = sp[flag_code >> 1];
8964 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8965 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8966 sp_regno[flag_code >> 1] = exp.X_add_number;
8967 input_line_pointer = saved_input;
8968 }
a4447b93 8969
a60de03c 8970 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8971 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8972}
d2b2c203
DJ		 8973
8974int
8975i386_elf_section_type (const char *str, size_t len)
8976{
8977 if (flag_code == CODE_64BIT
8978 && len == sizeof ("unwind") - 1
8979 && strncmp (str, "unwind", 6) == 0)
8980 return SHT_X86_64_UNWIND;
8981
8982 return -1;
8983}
bb41ade5 8984
ad5fec3b
EB		 8985#ifdef TE_SOLARIS
8986void
8987i386_solaris_fix_up_eh_frame (segT sec)
8988{
8989 if (flag_code == CODE_64BIT)
8990 elf_section_type (sec) = SHT_X86_64_UNWIND;
8991}
8992#endif
8993
bb41ade5
AM		 8994#ifdef TE_PE
8995void
8996tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8997{
91d6fa6a 8998 expressionS exp;
bb41ade5 8999
91d6fa6a
NC		 9000 exp.X_op = O_secrel;
9001 exp.X_add_symbol = symbol;
9002 exp.X_add_number = 0;
9003 emit_expr (&exp, size);
bb41ade5
AM		 9004}
9005#endif
3b22753a
L		 9006
9007#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9008/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9009
01e1a5bc 9010bfd_vma
3b22753a
L		 9011x86_64_section_letter (int letter, char **ptr_msg)
9012{
9013 if (flag_code == CODE_64BIT)
9014 {
9015 if (letter == 'l')
9016 return SHF_X86_64_LARGE;
9017
8f3bae45 9018 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9019 }
3b22753a 9020 else
8f3bae45 9021 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9022 return -1;
9023}
9024
01e1a5bc 9025bfd_vma
3b22753a
L		 9026x86_64_section_word (char *str, size_t len)
9027{
8620418b 9028 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9029 return SHF_X86_64_LARGE;
9030
9031 return -1;
9032}
9033
9034static void
9035handle_large_common (int small ATTRIBUTE_UNUSED)
9036{
9037 if (flag_code != CODE_64BIT)
9038 {
9039 s_comm_internal (0, elf_common_parse);
9040 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9041 }
9042 else
9043 {
9044 static segT lbss_section;
9045 asection *saved_com_section_ptr = elf_com_section_ptr;
9046 asection *saved_bss_section = bss_section;
9047
9048 if (lbss_section == NULL)
9049 {
9050 flagword applicable;
9051 segT seg = now_seg;
9052 subsegT subseg = now_subseg;
9053
9054 /* The .lbss section is for local .largecomm symbols. */
9055 lbss_section = subseg_new (".lbss", 0);
9056 applicable = bfd_applicable_section_flags (stdoutput);
9057 bfd_set_section_flags (stdoutput, lbss_section,
9058 applicable & SEC_ALLOC);
9059 seg_info (lbss_section)->bss = 1;
9060
9061 subseg_set (seg, subseg);
9062 }
9063
9064 elf_com_section_ptr = &_bfd_elf_large_com_section;
9065 bss_section = lbss_section;
9066
9067 s_comm_internal (0, elf_common_parse);
9068
9069 elf_com_section_ptr = saved_com_section_ptr;
9070 bss_section = saved_bss_section;
9071 }
9072}
9073#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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