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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
d3ce72d0 176static const insn_template *match_template (void);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132
RH		 328
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes;
332 unsigned char prefix[MAX_PREFIXES];
333
334 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 335 addressing modes of this insn are encoded. */
252b5132 336 modrm_byte rm;
3e73aa7c 337 rex_byte rex;
43234a1e 338 rex_byte vrex;
252b5132 339 sib_byte sib;
c0f3af97 340 vex_prefix vex;
b6169b20 341
43234a1e
L		 342 /* Masking attributes. */
343 struct Mask_Operation *mask;
344
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation *rounding;
347
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation *broadcast;
350
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift;
353
b6169b20 354 /* Swap operand in encoding. */
4473e004 355 unsigned int swap_operand;
891edac4 356
a501d77e
L		 357 /* Prefer 8bit or 32bit displacement in encoding. */
358 enum
359 {
360 disp_encoding_default = 0,
361 disp_encoding_8bit,
362 disp_encoding_32bit
363 } disp_encoding;
f8a5c266 364
d5de92cf
L		 365 /* REP prefix. */
366 const char *rep_prefix;
367
165de32a
L		 368 /* HLE prefix. */
369 const char *hle_prefix;
42164a71 370
7e8b059b
L		 371 /* Have BND prefix. */
372 const char *bnd_prefix;
373
43234a1e
L		 374 /* Need VREX to support upper 16 registers. */
375 int need_vrex;
376
891edac4 377 /* Error message. */
a65babc9 378 enum i386_error error;
252b5132
RH		 379 };
380
381typedef struct _i386_insn i386_insn;
382
43234a1e
L		 383/* Link RC type with corresponding string, that'll be looked for in
384 asm. */
385struct RC_name
386{
387 enum rc_type type;
388 const char *name;
389 unsigned int len;
390};
391
392static const struct RC_name RC_NamesTable[] =
393{
394 { rne, STRING_COMMA_LEN ("rn-sae") },
395 { rd, STRING_COMMA_LEN ("rd-sae") },
396 { ru, STRING_COMMA_LEN ("ru-sae") },
397 { rz, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly, STRING_COMMA_LEN ("sae") },
399};
400
252b5132
RH		 401/* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 403const char extra_symbol_chars[] = "*%-([{"
252b5132 404#ifdef LEX_AT
32137342
NC		 405 "@"
406#endif
407#ifdef LEX_QM
408 "?"
252b5132 409#endif
32137342 410 ;
252b5132 411
29b0f896
AM		 412#if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 414 && !defined (TE_GNU) \
29b0f896 415 && !defined (TE_LINUX) \
8d63c93e
RM		 416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
29b0f896 418 && !defined (TE_FreeBSD) \
5b806d27 419 && !defined (TE_DragonFly) \
29b0f896 420 && !defined (TE_NetBSD)))
252b5132 421/* This array holds the chars that always start a comment. If the
b3b91714
AM		 422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424const char *i386_comment_chars = "#/";
425#define SVR4_COMMENT_CHARS 1
252b5132 426#define PREFIX_SEPARATOR '\\'
252b5132 427
b3b91714
AM		 428#else
429const char *i386_comment_chars = "#";
430#define PREFIX_SEPARATOR '/'
431#endif
432
252b5132
RH		 433/* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 437 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
252b5132 440 '/' isn't otherwise defined. */
b3b91714 441const char line_comment_chars[] = "#/";
252b5132 442
63a0b638 443const char line_separator_chars[] = ";";
252b5132 444
ce8a8b2f
AM		 445/* Chars that can be used to separate mant from exp in floating point
446 nums. */
252b5132
RH		 447const char EXP_CHARS[] = "eE";
448
ce8a8b2f
AM		 449/* Chars that mean this number is a floating point constant
450 As in 0f12.456
451 or 0d1.2345e12. */
252b5132
RH		 452const char FLT_CHARS[] = "fFdDxX";
453
ce8a8b2f 454/* Tables for lexical analysis. */
252b5132
RH		 455static char mnemonic_chars[256];
456static char register_chars[256];
457static char operand_chars[256];
458static char identifier_chars[256];
459static char digit_chars[256];
460
ce8a8b2f 461/* Lexical macros. */
252b5132
RH		 462#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463#define is_operand_char(x) (operand_chars[(unsigned char) x])
464#define is_register_char(x) (register_chars[(unsigned char) x])
465#define is_space_char(x) ((x) == ' ')
466#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467#define is_digit_char(x) (digit_chars[(unsigned char) x])
468
0234cb7c 469/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 470static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
471
472/* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
47926f60 475 assembler instruction). */
252b5132 476static char save_stack[32];
ce8a8b2f 477static char *save_stack_p;
252b5132
RH		 478#define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480#define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
482
47926f60 483/* The instruction we're assembling. */
252b5132
RH		 484static i386_insn i;
485
486/* Possible templates for current insn. */
487static const templates *current_templates;
488
31b2323c
L		 489/* Per instruction expressionS buffers: max displacements & immediates. */
490static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
491static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 492
47926f60 493/* Current operand we are working on. */
ee86248c 494static int this_operand = -1;
252b5132 495
3e73aa7c
JH		 496/* We support four different modes. FLAG_CODE variable is used to distinguish
497 these. */
498
499enum flag_code {
500 CODE_32BIT,
501 CODE_16BIT,
502 CODE_64BIT };
503
504static enum flag_code flag_code;
4fa24527 505static unsigned int object_64bit;
862be3fb 506static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 507static int use_rela_relocations = 0;
508
7af8ed2d
NC		 509#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
512
351f65ca
L		 513/* The ELF ABI to use. */
514enum x86_elf_abi
515{
516 I386_ABI,
7f56bc95
L		 517 X86_64_ABI,
518 X86_64_X32_ABI
351f65ca
L		 519};
520
521static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 522#endif
351f65ca 523
167ad85b
TG		 524#if defined (TE_PE) || defined (TE_PEP)
525/* Use big object file format. */
526static int use_big_obj = 0;
527#endif
528
8dcea932
L		 529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530/* 1 if generating code for a shared library. */
531static int shared = 0;
532#endif
533
47926f60
KH		 534/* 1 for intel syntax,
535 0 if att syntax. */
536static int intel_syntax = 0;
252b5132 537
e89c5eaa
L		 538/* 1 for Intel64 ISA,
539 0 if AMD64 ISA. */
540static int intel64;
541
1efbbeb4
L		 542/* 1 for intel mnemonic,
543 0 if att mnemonic. */
544static int intel_mnemonic = !SYSV386_COMPAT;
545
5209009a 546/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 547static int old_gcc = OLDGCC_COMPAT;
548
a60de03c
JB		 549/* 1 if pseudo registers are permitted. */
550static int allow_pseudo_reg = 0;
551
47926f60
KH		 552/* 1 if register prefix % not required. */
553static int allow_naked_reg = 0;
252b5132 554
7e8b059b
L		 555/* 1 if the assembler should add BND prefix for all control-tranferring
556 instructions supporting it, even if this prefix wasn't specified
557 explicitly. */
558static int add_bnd_prefix = 0;
559
ba104c83 560/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 561static int allow_index_reg = 0;
562
d022bddd
IT		 563/* 1 if the assembler should ignore LOCK prefix, even if it was
564 specified explicitly. */
565static int omit_lock_prefix = 0;
566
e4e00185
AS		 567/* 1 if the assembler should encode lfence, mfence, and sfence as
568 "lock addl $0, (%{re}sp)". */
569static int avoid_fence = 0;
570
0cb4071e
L		 571/* 1 if the assembler should generate relax relocations. */
572
573static int generate_relax_relocations
574 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
575
7bab8ab5 576static enum check_kind
daf50ae7 577 {
7bab8ab5
JB		 578 check_none = 0,
579 check_warning,
580 check_error
daf50ae7 581 }
7bab8ab5 582sse_check, operand_check = check_warning;
daf50ae7 583
2ca3ace5
L		 584/* Register prefix used for error message. */
585static const char *register_prefix = "%";
586
47926f60
KH		 587/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
588 leave, push, and pop instructions so that gcc has the same stack
589 frame as in 32 bit mode. */
590static char stackop_size = '\0';
eecb386c 591
12b55ccc
L		 592/* Non-zero to optimize code alignment. */
593int optimize_align_code = 1;
594
47926f60
KH		 595/* Non-zero to quieten some warnings. */
596static int quiet_warnings = 0;
a38cf1db 597
47926f60
KH		 598/* CPU name. */
599static const char *cpu_arch_name = NULL;
6305a203 600static char *cpu_sub_arch_name = NULL;
a38cf1db 601
47926f60 602/* CPU feature flags. */
40fb9820
L		 603static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
604
ccc9c027
L		 605/* If we have selected a cpu we are generating instructions for. */
606static int cpu_arch_tune_set = 0;
607
9103f4f4 608/* Cpu we are generating instructions for. */
fbf3f584 609enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 610
611/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 612static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 613
ccc9c027 614/* CPU instruction set architecture used. */
fbf3f584 615enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 616
9103f4f4 617/* CPU feature flags of instruction set architecture used. */
fbf3f584 618i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 619
fddf5b5b
AM		 620/* If set, conditional jumps are not automatically promoted to handle
621 larger than a byte offset. */
622static unsigned int no_cond_jump_promotion = 0;
623
c0f3af97
L		 624/* Encode SSE instructions with VEX prefix. */
625static unsigned int sse2avx;
626
539f890d
L		 627/* Encode scalar AVX instructions with specific vector length. */
628static enum
629 {
630 vex128 = 0,
631 vex256
632 } avxscalar;
633
43234a1e
L		 634/* Encode scalar EVEX LIG instructions with specific vector length. */
635static enum
636 {
637 evexl128 = 0,
638 evexl256,
639 evexl512
640 } evexlig;
641
642/* Encode EVEX WIG instructions with specific evex.w. */
643static enum
644 {
645 evexw0 = 0,
646 evexw1
647 } evexwig;
648
d3d3c6db
IT		 649/* Value to encode in EVEX RC bits, for SAE-only instructions. */
650static enum rc_type evexrcig = rne;
651
29b0f896 652/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 653static symbolS *GOT_symbol;
29b0f896 654
a4447b93
RH		 655/* The dwarf2 return column, adjusted for 32 or 64 bit. */
656unsigned int x86_dwarf2_return_column;
657
658/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
659int x86_cie_data_alignment;
660
252b5132 661/* Interface to relax_segment.
fddf5b5b
AM		 662 There are 3 major relax states for 386 jump insns because the
663 different types of jumps add different sizes to frags when we're
664 figuring out what sort of jump to choose to reach a given label. */
252b5132 665
47926f60 666/* Types. */
93c2a809
AM		 667#define UNCOND_JUMP 0
668#define COND_JUMP 1
669#define COND_JUMP86 2
fddf5b5b 670
47926f60 671/* Sizes. */
252b5132
RH		 672#define CODE16 1
673#define SMALL 0
29b0f896 674#define SMALL16 (SMALL | CODE16)
252b5132 675#define BIG 2
29b0f896 676#define BIG16 (BIG | CODE16)
252b5132
RH		 677
678#ifndef INLINE
679#ifdef __GNUC__
680#define INLINE __inline__
681#else
682#define INLINE
683#endif
684#endif
685
fddf5b5b
AM		 686#define ENCODE_RELAX_STATE(type, size) \
687 ((relax_substateT) (((type) << 2) | (size)))
688#define TYPE_FROM_RELAX_STATE(s) \
689 ((s) >> 2)
690#define DISP_SIZE_FROM_RELAX_STATE(s) \
691 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 692
693/* This table is used by relax_frag to promote short jumps to long
694 ones where necessary. SMALL (short) jumps may be promoted to BIG
695 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
696 don't allow a short jump in a 32 bit code segment to be promoted to
697 a 16 bit offset jump because it's slower (requires data size
698 prefix), and doesn't work, unless the destination is in the bottom
699 64k of the code segment (The top 16 bits of eip are zeroed). */
700
701const relax_typeS md_relax_table[] =
702{
24eab124
AM		 703 /* The fields are:
704 1) most positive reach of this state,
705 2) most negative reach of this state,
93c2a809 706 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 707 4) which index into the table to try if we can't fit into this one. */
252b5132 708
fddf5b5b 709 /* UNCOND_JUMP states. */
93c2a809
AM		 710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
712 /* dword jmp adds 4 bytes to frag:
713 0 extra opcode bytes, 4 displacement bytes. */
252b5132 714 {0, 0, 4, 0},
93c2a809
AM		 715 /* word jmp adds 2 byte2 to frag:
716 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 717 {0, 0, 2, 0},
718
93c2a809
AM		 719 /* COND_JUMP states. */
720 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
721 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
722 /* dword conditionals adds 5 bytes to frag:
723 1 extra opcode byte, 4 displacement bytes. */
724 {0, 0, 5, 0},
fddf5b5b 725 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 726 1 extra opcode byte, 2 displacement bytes. */
727 {0, 0, 3, 0},
728
729 /* COND_JUMP86 states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
732 /* dword conditionals adds 5 bytes to frag:
733 1 extra opcode byte, 4 displacement bytes. */
734 {0, 0, 5, 0},
735 /* word conditionals add 4 bytes to frag:
736 1 displacement byte and a 3 byte long branch insn. */
737 {0, 0, 4, 0}
252b5132
RH		 738};
739
9103f4f4
L		 740static const arch_entry cpu_arch[] =
741{
89507696
JB		 742 /* Do not replace the first two entries - i386_target_format()
743 relies on them being there in this order. */
8a2c8fef 744 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 745 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 747 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 749 CPU_NONE_FLAGS, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 751 CPU_I186_FLAGS, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 753 CPU_I286_FLAGS, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 755 CPU_I386_FLAGS, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 757 CPU_I486_FLAGS, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 759 CPU_I586_FLAGS, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 761 CPU_I686_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 763 CPU_I586_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 765 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 767 CPU_P2_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 769 CPU_P3_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 771 CPU_P4_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 773 CPU_CORE_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 775 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 777 CPU_CORE_FLAGS, 1 },
8a2c8fef 778 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 779 CPU_CORE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 781 CPU_CORE2_FLAGS, 1 },
8a2c8fef 782 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 783 CPU_CORE2_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 785 CPU_COREI7_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 787 CPU_L1OM_FLAGS, 0 },
7a9068fe 788 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 789 CPU_K1OM_FLAGS, 0 },
81486035 790 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 791 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 793 CPU_K6_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 795 CPU_K6_2_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 797 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 799 CPU_K8_FLAGS, 1 },
8a2c8fef 800 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 801 CPU_K8_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 803 CPU_K8_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 805 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 806 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 807 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 808 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 809 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 810 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 811 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 812 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 813 CPU_BDVER4_FLAGS, 0 },
029f3522 814 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 815 CPU_ZNVER1_FLAGS, 0 },
7b458c12 816 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 817 CPU_BTVER1_FLAGS, 0 },
7b458c12 818 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 819 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 821 CPU_8087_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 823 CPU_287_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 825 CPU_387_FLAGS, 0 },
1848e567
L		 826 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
827 CPU_687_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 829 CPU_MMX_FLAGS, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 831 CPU_SSE_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 833 CPU_SSE2_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 835 CPU_SSE3_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 843 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_AVX_FLAGS, 0 },
6c30d220 846 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_AVX2_FLAGS, 0 },
43234a1e 848 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_AVX512F_FLAGS, 0 },
43234a1e 850 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_AVX512CD_FLAGS, 0 },
43234a1e 852 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_AVX512ER_FLAGS, 0 },
43234a1e 854 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 856 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 858 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 860 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_VMX_FLAGS, 0 },
8729a6f6 864 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_SMX_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 870 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 874 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AES_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 880 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 882 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 884 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 886 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_F16C_FLAGS, 0 },
6c30d220 888 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_BMI2_FLAGS, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_FMA_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_FMA4_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_XOP_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_LWP_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_MOVBE_FLAGS, 0 },
60aa667e 900 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_CX16_FLAGS, 0 },
8a2c8fef 902 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_EPT_FLAGS, 0 },
6c30d220 904 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_LZCNT_FLAGS, 0 },
42164a71 906 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_HLE_FLAGS, 0 },
42164a71 908 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_RTM_FLAGS, 0 },
6c30d220 910 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_CLFLUSH_FLAGS, 0 },
22109423 914 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_NOP_FLAGS, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_SVME_FLAGS, 1 },
8a2c8fef 928 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_SVME_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_ABM_FLAGS, 0 },
87973e9f 934 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_BMI_FLAGS, 0 },
2a2a0f38 936 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_TBM_FLAGS, 0 },
e2e1fcde 938 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_ADX_FLAGS, 0 },
e2e1fcde 940 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 942 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_PRFCHW_FLAGS, 0 },
5c111e37 944 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_SMAP_FLAGS, 0 },
7e8b059b 946 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_MPX_FLAGS, 0 },
a0046408 948 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_SHA_FLAGS, 0 },
963f3586 950 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 952 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 954 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_SE1_FLAGS, 0 },
c5e7287a 956 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_CLWB_FLAGS, 0 },
9d8596f0 958 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 960 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 962 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 964 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_CLZERO_FLAGS, 0 },
9916071f 966 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_MWAITX_FLAGS, 0 },
8eab4136 968 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_OSPKE_FLAGS, 0 },
8bc52696 970 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65
L		 971 CPU_RDPID_FLAGS, 0 },
972};
973
974static const noarch_entry cpu_noarch[] =
975{
976 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 977 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
978 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
979 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 980 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
981 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 982 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
983 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
984 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
985 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
986 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
987 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 988 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 989 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 990 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
991 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
992 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
993 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
994 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
995 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
996 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
997 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
998 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
e413e4e9
AM		 999};
1000
704209c0 1001#ifdef I386COFF
a6c24e68
NC		 1002/* Like s_lcomm_internal in gas/read.c but the alignment string
1003 is allowed to be optional. */
1004
1005static symbolS *
1006pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1007{
1008 addressT align = 0;
1009
1010 SKIP_WHITESPACE ();
1011
7ab9ffdd 1012 if (needs_align
a6c24e68
NC		 1013 && *input_line_pointer == ',')
1014 {
1015 align = parse_align (needs_align - 1);
7ab9ffdd 1016
a6c24e68
NC		 1017 if (align == (addressT) -1)
1018 return NULL;
1019 }
1020 else
1021 {
1022 if (size >= 8)
1023 align = 3;
1024 else if (size >= 4)
1025 align = 2;
1026 else if (size >= 2)
1027 align = 1;
1028 else
1029 align = 0;
1030 }
1031
1032 bss_alloc (symbolP, size, align);
1033 return symbolP;
1034}
1035
704209c0 1036static void
a6c24e68
NC		 1037pe_lcomm (int needs_align)
1038{
1039 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1040}
704209c0 1041#endif
a6c24e68 1042
29b0f896
AM		 1043const pseudo_typeS md_pseudo_table[] =
1044{
1045#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1046 {"align", s_align_bytes, 0},
1047#else
1048 {"align", s_align_ptwo, 0},
1049#endif
1050 {"arch", set_cpu_arch, 0},
1051#ifndef I386COFF
1052 {"bss", s_bss, 0},
a6c24e68
NC		 1053#else
1054 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1055#endif
1056 {"ffloat", float_cons, 'f'},
1057 {"dfloat", float_cons, 'd'},
1058 {"tfloat", float_cons, 'x'},
1059 {"value", cons, 2},
d182319b 1060 {"slong", signed_cons, 4},
29b0f896
AM		 1061 {"noopt", s_ignore, 0},
1062 {"optim", s_ignore, 0},
1063 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1064 {"code16", set_code_flag, CODE_16BIT},
1065 {"code32", set_code_flag, CODE_32BIT},
1066 {"code64", set_code_flag, CODE_64BIT},
1067 {"intel_syntax", set_intel_syntax, 1},
1068 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1069 {"intel_mnemonic", set_intel_mnemonic, 1},
1070 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1071 {"allow_index_reg", set_allow_index_reg, 1},
1072 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1073 {"sse_check", set_check, 0},
1074 {"operand_check", set_check, 1},
3b22753a
L		 1075#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1076 {"largecomm", handle_large_common, 0},
07a53e5c 1077#else
e3bb37b5 1078 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1079 {"loc", dwarf2_directive_loc, 0},
1080 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1081#endif
6482c264
NC		 1082#ifdef TE_PE
1083 {"secrel32", pe_directive_secrel, 0},
1084#endif
29b0f896
AM		 1085 {0, 0, 0}
1086};
1087
1088/* For interface with expression (). */
1089extern char *input_line_pointer;
1090
1091/* Hash table for instruction mnemonic lookup. */
1092static struct hash_control *op_hash;
1093
1094/* Hash table for register lookup. */
1095static struct hash_control *reg_hash;
1096\f
252b5132 1097void
e3bb37b5 1098i386_align_code (fragS *fragP, int count)
252b5132 1099{
ce8a8b2f
AM		 1100 /* Various efficient no-op patterns for aligning code labels.
1101 Note: Don't try to assemble the instructions in the comments.
1102 0L and 0w are not legal. */
bad6e36d 1103 static const unsigned char f32_1[] =
252b5132 1104 {0x90}; /* nop */
bad6e36d 1105 static const unsigned char f32_2[] =
ccc9c027 1106 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1107 static const unsigned char f32_3[] =
252b5132 1108 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1109 static const unsigned char f32_4[] =
252b5132 1110 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1111 static const unsigned char f32_5[] =
252b5132
RH		 1112 {0x90, /* nop */
1113 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1114 static const unsigned char f32_6[] =
252b5132 1115 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1116 static const unsigned char f32_7[] =
252b5132 1117 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1118 static const unsigned char f32_8[] =
252b5132
RH		 1119 {0x90, /* nop */
1120 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1121 static const unsigned char f32_9[] =
252b5132
RH		 1122 {0x89,0xf6, /* movl %esi,%esi */
1123 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1124 static const unsigned char f32_10[] =
252b5132
RH		 1125 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1126 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1127 static const unsigned char f32_11[] =
252b5132
RH		 1128 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1129 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1130 static const unsigned char f32_12[] =
252b5132
RH		 1131 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1132 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1133 static const unsigned char f32_13[] =
252b5132
RH		 1134 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1135 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1136 static const unsigned char f32_14[] =
252b5132
RH		 1137 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1138 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1139 static const unsigned char f16_3[] =
c3332e24 1140 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1141 static const unsigned char f16_4[] =
252b5132 1142 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1143 static const unsigned char f16_5[] =
252b5132
RH		 1144 {0x90, /* nop */
1145 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1146 static const unsigned char f16_6[] =
252b5132
RH		 1147 {0x89,0xf6, /* mov %si,%si */
1148 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1149 static const unsigned char f16_7[] =
252b5132
RH		 1150 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1151 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1152 static const unsigned char f16_8[] =
252b5132
RH		 1153 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1154 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1155 static const unsigned char jump_31[] =
76bc74dc
L		 1156 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1157 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1158 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1159 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1160 static const unsigned char *const f32_patt[] = {
252b5132 1161 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1162 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1163 };
bad6e36d 1164 static const unsigned char *const f16_patt[] = {
76bc74dc 1165 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1166 };
ccc9c027 1167 /* nopl (%[re]ax) */
bad6e36d 1168 static const unsigned char alt_3[] =
ccc9c027
L		 1169 {0x0f,0x1f,0x00};
1170 /* nopl 0(%[re]ax) */
bad6e36d 1171 static const unsigned char alt_4[] =
ccc9c027
L		 1172 {0x0f,0x1f,0x40,0x00};
1173 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1174 static const unsigned char alt_5[] =
ccc9c027
L		 1175 {0x0f,0x1f,0x44,0x00,0x00};
1176 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1177 static const unsigned char alt_6[] =
ccc9c027
L		 1178 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopl 0L(%[re]ax) */
bad6e36d 1180 static const unsigned char alt_7[] =
ccc9c027
L		 1181 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1182 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1183 static const unsigned char alt_8[] =
ccc9c027
L		 1184 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1185 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1186 static const unsigned char alt_9[] =
ccc9c027
L		 1187 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1188 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1189 static const unsigned char alt_10[] =
ccc9c027 1190 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1191 static const unsigned char *const alt_patt[] = {
ccc9c027 1192 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1193 alt_9, alt_10
ccc9c027 1194 };
252b5132 1195
76bc74dc
L		 1196 /* Only align for at least a positive non-zero boundary. */
1197 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1198 return;
3e73aa7c 1199
ccc9c027
L		 1200 /* We need to decide which NOP sequence to use for 32bit and
1201 64bit. When -mtune= is used:
4eed87de 1202
76bc74dc
L		 1203 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1204 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1205 2. For the rest, alt_patt will be used.
1206
1207 When -mtune= isn't used, alt_patt will be used if
22109423 1208 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1209 be used.
ccc9c027
L		 1210
1211 When -march= or .arch is used, we can't use anything beyond
1212 cpu_arch_isa_flags. */
1213
1214 if (flag_code == CODE_16BIT)
1215 {
ccc9c027 1216 if (count > 8)
33fef721 1217 {
76bc74dc
L		 1218 memcpy (fragP->fr_literal + fragP->fr_fix,
1219 jump_31, count);
1220 /* Adjust jump offset. */
1221 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1222 }
76bc74dc
L		 1223 else
1224 memcpy (fragP->fr_literal + fragP->fr_fix,
1225 f16_patt[count - 1], count);
252b5132 1226 }
33fef721 1227 else
ccc9c027 1228 {
bad6e36d 1229 const unsigned char *const *patt = NULL;
ccc9c027 1230
fbf3f584 1231 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1232 {
1233 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1234 switch (cpu_arch_tune)
1235 {
1236 case PROCESSOR_UNKNOWN:
1237 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1238 optimize with nops. */
1239 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1240 patt = alt_patt;
ccc9c027
L		 1241 else
1242 patt = f32_patt;
1243 break;
ccc9c027
L		 1244 case PROCESSOR_PENTIUM4:
1245 case PROCESSOR_NOCONA:
ef05d495 1246 case PROCESSOR_CORE:
76bc74dc 1247 case PROCESSOR_CORE2:
bd5295b2 1248 case PROCESSOR_COREI7:
3632d14b 1249 case PROCESSOR_L1OM:
7a9068fe 1250 case PROCESSOR_K1OM:
76bc74dc 1251 case PROCESSOR_GENERIC64:
ccc9c027
L		 1252 case PROCESSOR_K6:
1253 case PROCESSOR_ATHLON:
1254 case PROCESSOR_K8:
4eed87de 1255 case PROCESSOR_AMDFAM10:
8aedb9fe 1256 case PROCESSOR_BD:
029f3522 1257 case PROCESSOR_ZNVER:
7b458c12 1258 case PROCESSOR_BT:
80b8656c 1259 patt = alt_patt;
ccc9c027 1260 break;
76bc74dc 1261 case PROCESSOR_I386:
ccc9c027
L		 1262 case PROCESSOR_I486:
1263 case PROCESSOR_PENTIUM:
2dde1948 1264 case PROCESSOR_PENTIUMPRO:
81486035 1265 case PROCESSOR_IAMCU:
ccc9c027
L		 1266 case PROCESSOR_GENERIC32:
1267 patt = f32_patt;
1268 break;
4eed87de 1269 }
ccc9c027
L		 1270 }
1271 else
1272 {
fbf3f584 1273 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1274 {
1275 case PROCESSOR_UNKNOWN:
e6a14101 1276 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1277 PROCESSOR_UNKNOWN. */
1278 abort ();
1279 break;
1280
76bc74dc 1281 case PROCESSOR_I386:
ccc9c027
L		 1282 case PROCESSOR_I486:
1283 case PROCESSOR_PENTIUM:
81486035 1284 case PROCESSOR_IAMCU:
ccc9c027
L		 1285 case PROCESSOR_K6:
1286 case PROCESSOR_ATHLON:
1287 case PROCESSOR_K8:
4eed87de 1288 case PROCESSOR_AMDFAM10:
8aedb9fe 1289 case PROCESSOR_BD:
029f3522 1290 case PROCESSOR_ZNVER:
7b458c12 1291 case PROCESSOR_BT:
ccc9c027
L		 1292 case PROCESSOR_GENERIC32:
1293 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1294 with nops. */
1295 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1296 patt = alt_patt;
ccc9c027
L		 1297 else
1298 patt = f32_patt;
1299 break;
76bc74dc
L		 1300 case PROCESSOR_PENTIUMPRO:
1301 case PROCESSOR_PENTIUM4:
1302 case PROCESSOR_NOCONA:
1303 case PROCESSOR_CORE:
ef05d495 1304 case PROCESSOR_CORE2:
bd5295b2 1305 case PROCESSOR_COREI7:
3632d14b 1306 case PROCESSOR_L1OM:
7a9068fe 1307 case PROCESSOR_K1OM:
22109423 1308 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1309 patt = alt_patt;
ccc9c027
L		 1310 else
1311 patt = f32_patt;
1312 break;
1313 case PROCESSOR_GENERIC64:
80b8656c 1314 patt = alt_patt;
ccc9c027 1315 break;
4eed87de 1316 }
ccc9c027
L		 1317 }
1318
76bc74dc
L		 1319 if (patt == f32_patt)
1320 {
1321 /* If the padding is less than 15 bytes, we use the normal
1322 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1323 its offset. */
1324 int limit;
76ba9986 1325
711eedef
L		 1326 /* For 64bit, the limit is 3 bytes. */
1327 if (flag_code == CODE_64BIT
1328 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1329 limit = 3;
1330 else
1331 limit = 15;
1332 if (count < limit)
76bc74dc
L		 1333 memcpy (fragP->fr_literal + fragP->fr_fix,
1334 patt[count - 1], count);
1335 else
1336 {
1337 memcpy (fragP->fr_literal + fragP->fr_fix,
1338 jump_31, count);
1339 /* Adjust jump offset. */
1340 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1341 }
1342 }
1343 else
1344 {
80b8656c
L		 1345 /* Maximum length of an instruction is 10 byte. If the
1346 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1347 we have to break it into smaller pieces. */
1348 int padding = count;
80b8656c 1349 while (padding > 10)
76bc74dc 1350 {
80b8656c 1351 padding -= 10;
76bc74dc 1352 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1353 patt [9], 10);
76bc74dc
L		 1354 }
1355
1356 if (padding)
1357 memcpy (fragP->fr_literal + fragP->fr_fix,
1358 patt [padding - 1], padding);
1359 }
ccc9c027 1360 }
33fef721 1361 fragP->fr_var = count;
252b5132
RH		 1362}
1363
c6fb90c8 1364static INLINE int
0dfbf9d7 1365operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1366{
0dfbf9d7 1367 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1368 {
1369 case 3:
0dfbf9d7 1370 if (x->array[2])
c6fb90c8
L		 1371 return 0;
1372 case 2:
0dfbf9d7 1373 if (x->array[1])
c6fb90c8
L		 1374 return 0;
1375 case 1:
0dfbf9d7 1376 return !x->array[0];
c6fb90c8
L		 1377 default:
1378 abort ();
1379 }
40fb9820
L		 1380}
1381
c6fb90c8 1382static INLINE void
0dfbf9d7 1383operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1384{
0dfbf9d7 1385 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1386 {
1387 case 3:
0dfbf9d7 1388 x->array[2] = v;
c6fb90c8 1389 case 2:
0dfbf9d7 1390 x->array[1] = v;
c6fb90c8 1391 case 1:
0dfbf9d7 1392 x->array[0] = v;
c6fb90c8
L		 1393 break;
1394 default:
1395 abort ();
1396 }
1397}
40fb9820 1398
c6fb90c8 1399static INLINE int
0dfbf9d7
L		 1400operand_type_equal (const union i386_operand_type *x,
1401 const union i386_operand_type *y)
c6fb90c8 1402{
0dfbf9d7 1403 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1404 {
1405 case 3:
0dfbf9d7 1406 if (x->array[2] != y->array[2])
c6fb90c8
L		 1407 return 0;
1408 case 2:
0dfbf9d7 1409 if (x->array[1] != y->array[1])
c6fb90c8
L		 1410 return 0;
1411 case 1:
0dfbf9d7 1412 return x->array[0] == y->array[0];
c6fb90c8
L		 1413 break;
1414 default:
1415 abort ();
1416 }
1417}
40fb9820 1418
0dfbf9d7
L		 1419static INLINE int
1420cpu_flags_all_zero (const union i386_cpu_flags *x)
1421{
1422 switch (ARRAY_SIZE(x->array))
1423 {
1424 case 3:
1425 if (x->array[2])
1426 return 0;
1427 case 2:
1428 if (x->array[1])
1429 return 0;
1430 case 1:
1431 return !x->array[0];
1432 default:
1433 abort ();
1434 }
1435}
1436
0dfbf9d7
L		 1437static INLINE int
1438cpu_flags_equal (const union i386_cpu_flags *x,
1439 const union i386_cpu_flags *y)
1440{
1441 switch (ARRAY_SIZE(x->array))
1442 {
1443 case 3:
1444 if (x->array[2] != y->array[2])
1445 return 0;
1446 case 2:
1447 if (x->array[1] != y->array[1])
1448 return 0;
1449 case 1:
1450 return x->array[0] == y->array[0];
1451 break;
1452 default:
1453 abort ();
1454 }
1455}
c6fb90c8
L		 1456
1457static INLINE int
1458cpu_flags_check_cpu64 (i386_cpu_flags f)
1459{
1460 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1461 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1462}
1463
c6fb90c8
L		 1464static INLINE i386_cpu_flags
1465cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1466{
c6fb90c8
L		 1467 switch (ARRAY_SIZE (x.array))
1468 {
1469 case 3:
1470 x.array [2] &= y.array [2];
1471 case 2:
1472 x.array [1] &= y.array [1];
1473 case 1:
1474 x.array [0] &= y.array [0];
1475 break;
1476 default:
1477 abort ();
1478 }
1479 return x;
1480}
40fb9820 1481
c6fb90c8
L		 1482static INLINE i386_cpu_flags
1483cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1484{
c6fb90c8 1485 switch (ARRAY_SIZE (x.array))
40fb9820 1486 {
c6fb90c8
L		 1487 case 3:
1488 x.array [2] |= y.array [2];
1489 case 2:
1490 x.array [1] |= y.array [1];
1491 case 1:
1492 x.array [0] |= y.array [0];
40fb9820
L		 1493 break;
1494 default:
1495 abort ();
1496 }
40fb9820
L		 1497 return x;
1498}
1499
309d3373
JB		 1500static INLINE i386_cpu_flags
1501cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1502{
1503 switch (ARRAY_SIZE (x.array))
1504 {
1505 case 3:
1506 x.array [2] &= ~y.array [2];
1507 case 2:
1508 x.array [1] &= ~y.array [1];
1509 case 1:
1510 x.array [0] &= ~y.array [0];
1511 break;
1512 default:
1513 abort ();
1514 }
1515 return x;
1516}
1517
81486035
L		 1518static int
1519valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1520{
1521 if (cpu_arch_isa == PROCESSOR_IAMCU)
1522 {
1523 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1524 i386_cpu_flags compat_flags;
1525 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1526 return cpu_flags_all_zero (&compat_flags);
1527 }
1528 else
1529 return 1;
1530}
1531
c0f3af97
L		 1532#define CPU_FLAGS_ARCH_MATCH 0x1
1533#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1534#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1535#define CPU_FLAGS_PCLMUL_MATCH 0x8
1536#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1537
a5ff0eb2 1538#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1539 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1540 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1541#define CPU_FLAGS_PERFECT_MATCH \
1542 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1543
1544/* Return CPU flags match bits. */
3629bb00 1545
40fb9820 1546static int
d3ce72d0 1547cpu_flags_match (const insn_template *t)
40fb9820 1548{
c0f3af97
L		 1549 i386_cpu_flags x = t->cpu_flags;
1550 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1551
1552 x.bitfield.cpu64 = 0;
1553 x.bitfield.cpuno64 = 0;
1554
0dfbf9d7 1555 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1556 {
1557 /* This instruction is available on all archs. */
1558 match |= CPU_FLAGS_32BIT_MATCH;
1559 }
3629bb00
L		 1560 else
1561 {
c0f3af97 1562 /* This instruction is available only on some archs. */
3629bb00
L		 1563 i386_cpu_flags cpu = cpu_arch_flags;
1564
3629bb00 1565 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1566 if (!cpu_flags_all_zero (&cpu))
1567 {
a5ff0eb2
L		 1568 if (x.bitfield.cpuavx)
1569 {
ce2f5b3c 1570 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1571 if (cpu.bitfield.cpuavx)
1572 {
1573 /* Check SSE2AVX. */
1574 if (!t->opcode_modifier.sse2avx|| sse2avx)
1575 {
1576 match |= (CPU_FLAGS_ARCH_MATCH
1577 | CPU_FLAGS_AVX_MATCH);
1578 /* Check AES. */
1579 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1580 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1581 /* Check PCLMUL. */
1582 if (!x.bitfield.cpupclmul
1583 || cpu.bitfield.cpupclmul)
1584 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1585 }
1586 }
1587 else
1588 match |= CPU_FLAGS_ARCH_MATCH;
1589 }
73b090a9
L		 1590 else if (x.bitfield.cpuavx512vl)
1591 {
1592 /* Match AVX512VL. */
1593 if (cpu.bitfield.cpuavx512vl)
1594 {
1595 /* Need another match. */
1596 cpu.bitfield.cpuavx512vl = 0;
1597 if (!cpu_flags_all_zero (&cpu))
1598 match |= CPU_FLAGS_32BIT_MATCH;
1599 else
1600 match |= CPU_FLAGS_ARCH_MATCH;
1601 }
1602 else
1603 match |= CPU_FLAGS_ARCH_MATCH;
1604 }
a5ff0eb2 1605 else
c0f3af97
L		 1606 match |= CPU_FLAGS_32BIT_MATCH;
1607 }
3629bb00 1608 }
c0f3af97 1609 return match;
40fb9820
L		 1610}
1611
c6fb90c8
L		 1612static INLINE i386_operand_type
1613operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1614{
c6fb90c8
L		 1615 switch (ARRAY_SIZE (x.array))
1616 {
1617 case 3:
1618 x.array [2] &= y.array [2];
1619 case 2:
1620 x.array [1] &= y.array [1];
1621 case 1:
1622 x.array [0] &= y.array [0];
1623 break;
1624 default:
1625 abort ();
1626 }
1627 return x;
40fb9820
L		 1628}
1629
c6fb90c8
L		 1630static INLINE i386_operand_type
1631operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1632{
c6fb90c8 1633 switch (ARRAY_SIZE (x.array))
40fb9820 1634 {
c6fb90c8
L		 1635 case 3:
1636 x.array [2] |= y.array [2];
1637 case 2:
1638 x.array [1] |= y.array [1];
1639 case 1:
1640 x.array [0] |= y.array [0];
40fb9820
L		 1641 break;
1642 default:
1643 abort ();
1644 }
c6fb90c8
L		 1645 return x;
1646}
40fb9820 1647
c6fb90c8
L		 1648static INLINE i386_operand_type
1649operand_type_xor (i386_operand_type x, i386_operand_type y)
1650{
1651 switch (ARRAY_SIZE (x.array))
1652 {
1653 case 3:
1654 x.array [2] ^= y.array [2];
1655 case 2:
1656 x.array [1] ^= y.array [1];
1657 case 1:
1658 x.array [0] ^= y.array [0];
1659 break;
1660 default:
1661 abort ();
1662 }
40fb9820
L		 1663 return x;
1664}
1665
1666static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1667static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1668static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1669static const i386_operand_type inoutportreg
1670 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1671static const i386_operand_type reg16_inoutportreg
1672 = OPERAND_TYPE_REG16_INOUTPORTREG;
1673static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1674static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1675static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1676static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1677static const i386_operand_type anydisp
1678 = OPERAND_TYPE_ANYDISP;
40fb9820 1679static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1680static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1681static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1682static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1683static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1684static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1685static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1686static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1687static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1688static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1689static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1690static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1691static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1692static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1693
1694enum operand_type
1695{
1696 reg,
40fb9820
L		 1697 imm,
1698 disp,
1699 anymem
1700};
1701
c6fb90c8 1702static INLINE int
40fb9820
L		 1703operand_type_check (i386_operand_type t, enum operand_type c)
1704{
1705 switch (c)
1706 {
1707 case reg:
1708 return (t.bitfield.reg8
1709 || t.bitfield.reg16
1710 || t.bitfield.reg32
1711 || t.bitfield.reg64);
1712
40fb9820
L		 1713 case imm:
1714 return (t.bitfield.imm8
1715 || t.bitfield.imm8s
1716 || t.bitfield.imm16
1717 || t.bitfield.imm32
1718 || t.bitfield.imm32s
1719 || t.bitfield.imm64);
1720
1721 case disp:
1722 return (t.bitfield.disp8
1723 || t.bitfield.disp16
1724 || t.bitfield.disp32
1725 || t.bitfield.disp32s
1726 || t.bitfield.disp64);
1727
1728 case anymem:
1729 return (t.bitfield.disp8
1730 || t.bitfield.disp16
1731 || t.bitfield.disp32
1732 || t.bitfield.disp32s
1733 || t.bitfield.disp64
1734 || t.bitfield.baseindex);
1735
1736 default:
1737 abort ();
1738 }
2cfe26b6
AM		 1739
1740 return 0;
40fb9820
L		 1741}
1742
5c07affc
L		 1743/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1744 operand J for instruction template T. */
1745
1746static INLINE int
d3ce72d0 1747match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1748{
1749 return !((i.types[j].bitfield.byte
1750 && !t->operand_types[j].bitfield.byte)
1751 || (i.types[j].bitfield.word
1752 && !t->operand_types[j].bitfield.word)
1753 || (i.types[j].bitfield.dword
1754 && !t->operand_types[j].bitfield.dword)
1755 || (i.types[j].bitfield.qword
1756 && !t->operand_types[j].bitfield.qword));
1757}
1758
1759/* Return 1 if there is no conflict in any size on operand J for
1760 instruction template T. */
1761
1762static INLINE int
d3ce72d0 1763match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1764{
1765 return (match_reg_size (t, j)
1766 && !((i.types[j].bitfield.unspecified
af508cb9 1767 && !i.broadcast
5c07affc
L		 1768 && !t->operand_types[j].bitfield.unspecified)
1769 || (i.types[j].bitfield.fword
1770 && !t->operand_types[j].bitfield.fword)
1771 || (i.types[j].bitfield.tbyte
1772 && !t->operand_types[j].bitfield.tbyte)
1773 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1774 && !t->operand_types[j].bitfield.xmmword)
1775 || (i.types[j].bitfield.ymmword
43234a1e
L		 1776 && !t->operand_types[j].bitfield.ymmword)
1777 || (i.types[j].bitfield.zmmword
1778 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1779}
1780
1781/* Return 1 if there is no size conflict on any operands for
1782 instruction template T. */
1783
1784static INLINE int
d3ce72d0 1785operand_size_match (const insn_template *t)
5c07affc
L		 1786{
1787 unsigned int j;
1788 int match = 1;
1789
1790 /* Don't check jump instructions. */
1791 if (t->opcode_modifier.jump
1792 || t->opcode_modifier.jumpbyte
1793 || t->opcode_modifier.jumpdword
1794 || t->opcode_modifier.jumpintersegment)
1795 return match;
1796
1797 /* Check memory and accumulator operand size. */
1798 for (j = 0; j < i.operands; j++)
1799 {
1800 if (t->operand_types[j].bitfield.anysize)
1801 continue;
1802
1803 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1804 {
1805 match = 0;
1806 break;
1807 }
1808
1809 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1810 {
1811 match = 0;
1812 break;
1813 }
1814 }
1815
891edac4 1816 if (match)
5c07affc 1817 return match;
891edac4
L		 1818 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1819 {
1820mismatch:
86e026a4 1821 i.error = operand_size_mismatch;
891edac4
L		 1822 return 0;
1823 }
5c07affc
L		 1824
1825 /* Check reverse. */
9c2799c2 1826 gas_assert (i.operands == 2);
5c07affc
L		 1827
1828 match = 1;
1829 for (j = 0; j < 2; j++)
1830 {
1831 if (t->operand_types[j].bitfield.acc
1832 && !match_reg_size (t, j ? 0 : 1))
891edac4 1833 goto mismatch;
5c07affc
L		 1834
1835 if (i.types[j].bitfield.mem
1836 && !match_mem_size (t, j ? 0 : 1))
891edac4 1837 goto mismatch;
5c07affc
L		 1838 }
1839
1840 return match;
1841}
1842
c6fb90c8 1843static INLINE int
40fb9820
L		 1844operand_type_match (i386_operand_type overlap,
1845 i386_operand_type given)
1846{
1847 i386_operand_type temp = overlap;
1848
1849 temp.bitfield.jumpabsolute = 0;
7d5e4556 1850 temp.bitfield.unspecified = 0;
5c07affc
L		 1851 temp.bitfield.byte = 0;
1852 temp.bitfield.word = 0;
1853 temp.bitfield.dword = 0;
1854 temp.bitfield.fword = 0;
1855 temp.bitfield.qword = 0;
1856 temp.bitfield.tbyte = 0;
1857 temp.bitfield.xmmword = 0;
c0f3af97 1858 temp.bitfield.ymmword = 0;
43234a1e 1859 temp.bitfield.zmmword = 0;
0dfbf9d7 1860 if (operand_type_all_zero (&temp))
891edac4 1861 goto mismatch;
40fb9820 1862
891edac4
L		 1863 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1864 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1865 return 1;
1866
1867mismatch:
a65babc9 1868 i.error = operand_type_mismatch;
891edac4 1869 return 0;
40fb9820
L		 1870}
1871
7d5e4556 1872/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1873 unless the expected operand type register overlap is null.
1874 Note that Acc in a template matches every size of reg. */
1875
c6fb90c8 1876static INLINE int
40fb9820
L		 1877operand_type_register_match (i386_operand_type m0,
1878 i386_operand_type g0,
1879 i386_operand_type t0,
1880 i386_operand_type m1,
1881 i386_operand_type g1,
1882 i386_operand_type t1)
1883{
1884 if (!operand_type_check (g0, reg))
1885 return 1;
1886
1887 if (!operand_type_check (g1, reg))
1888 return 1;
1889
1890 if (g0.bitfield.reg8 == g1.bitfield.reg8
1891 && g0.bitfield.reg16 == g1.bitfield.reg16
1892 && g0.bitfield.reg32 == g1.bitfield.reg32
1893 && g0.bitfield.reg64 == g1.bitfield.reg64)
1894 return 1;
1895
1896 if (m0.bitfield.acc)
1897 {
1898 t0.bitfield.reg8 = 1;
1899 t0.bitfield.reg16 = 1;
1900 t0.bitfield.reg32 = 1;
1901 t0.bitfield.reg64 = 1;
1902 }
1903
1904 if (m1.bitfield.acc)
1905 {
1906 t1.bitfield.reg8 = 1;
1907 t1.bitfield.reg16 = 1;
1908 t1.bitfield.reg32 = 1;
1909 t1.bitfield.reg64 = 1;
1910 }
1911
891edac4
L		 1912 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1913 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1914 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1915 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1916 return 1;
1917
a65babc9 1918 i.error = register_type_mismatch;
891edac4
L		 1919
1920 return 0;
40fb9820
L		 1921}
1922
4c692bc7
JB		 1923static INLINE unsigned int
1924register_number (const reg_entry *r)
1925{
1926 unsigned int nr = r->reg_num;
1927
1928 if (r->reg_flags & RegRex)
1929 nr += 8;
1930
200cbe0f
L		 1931 if (r->reg_flags & RegVRex)
1932 nr += 16;
1933
4c692bc7
JB		 1934 return nr;
1935}
1936
252b5132 1937static INLINE unsigned int
40fb9820 1938mode_from_disp_size (i386_operand_type t)
252b5132 1939{
43234a1e 1940 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1941 return 1;
1942 else if (t.bitfield.disp16
1943 || t.bitfield.disp32
1944 || t.bitfield.disp32s)
1945 return 2;
1946 else
1947 return 0;
252b5132
RH		 1948}
1949
1950static INLINE int
65879393 1951fits_in_signed_byte (addressT num)
252b5132 1952{
65879393 1953 return num + 0x80 <= 0xff;
47926f60 1954}
252b5132
RH		 1955
1956static INLINE int
65879393 1957fits_in_unsigned_byte (addressT num)
252b5132 1958{
65879393 1959 return num <= 0xff;
47926f60 1960}
252b5132
RH		 1961
1962static INLINE int
65879393 1963fits_in_unsigned_word (addressT num)
252b5132 1964{
65879393 1965 return num <= 0xffff;
47926f60 1966}
252b5132
RH		 1967
1968static INLINE int
65879393 1969fits_in_signed_word (addressT num)
252b5132 1970{
65879393 1971 return num + 0x8000 <= 0xffff;
47926f60 1972}
2a962e6d 1973
3e73aa7c 1974static INLINE int
65879393 1975fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1976{
1977#ifndef BFD64
1978 return 1;
1979#else
65879393 1980 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1981#endif
1982} /* fits_in_signed_long() */
2a962e6d 1983
3e73aa7c 1984static INLINE int
65879393 1985fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1986{
1987#ifndef BFD64
1988 return 1;
1989#else
65879393 1990 return num <= 0xffffffff;
3e73aa7c
JH		 1991#endif
1992} /* fits_in_unsigned_long() */
252b5132 1993
43234a1e
L		 1994static INLINE int
1995fits_in_vec_disp8 (offsetT num)
1996{
1997 int shift = i.memshift;
1998 unsigned int mask;
1999
2000 if (shift == -1)
2001 abort ();
2002
2003 mask = (1 << shift) - 1;
2004
2005 /* Return 0 if NUM isn't properly aligned. */
2006 if ((num & mask))
2007 return 0;
2008
2009 /* Check if NUM will fit in 8bit after shift. */
2010 return fits_in_signed_byte (num >> shift);
2011}
2012
a683cc34
SP		 2013static INLINE int
2014fits_in_imm4 (offsetT num)
2015{
2016 return (num & 0xf) == num;
2017}
2018
40fb9820 2019static i386_operand_type
e3bb37b5 2020smallest_imm_type (offsetT num)
252b5132 2021{
40fb9820 2022 i386_operand_type t;
7ab9ffdd 2023
0dfbf9d7 2024 operand_type_set (&t, 0);
40fb9820
L		 2025 t.bitfield.imm64 = 1;
2026
2027 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2028 {
2029 /* This code is disabled on the 486 because all the Imm1 forms
2030 in the opcode table are slower on the i486. They're the
2031 versions with the implicitly specified single-position
2032 displacement, which has another syntax if you really want to
2033 use that form. */
40fb9820
L		 2034 t.bitfield.imm1 = 1;
2035 t.bitfield.imm8 = 1;
2036 t.bitfield.imm8s = 1;
2037 t.bitfield.imm16 = 1;
2038 t.bitfield.imm32 = 1;
2039 t.bitfield.imm32s = 1;
2040 }
2041 else if (fits_in_signed_byte (num))
2042 {
2043 t.bitfield.imm8 = 1;
2044 t.bitfield.imm8s = 1;
2045 t.bitfield.imm16 = 1;
2046 t.bitfield.imm32 = 1;
2047 t.bitfield.imm32s = 1;
2048 }
2049 else if (fits_in_unsigned_byte (num))
2050 {
2051 t.bitfield.imm8 = 1;
2052 t.bitfield.imm16 = 1;
2053 t.bitfield.imm32 = 1;
2054 t.bitfield.imm32s = 1;
2055 }
2056 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2057 {
2058 t.bitfield.imm16 = 1;
2059 t.bitfield.imm32 = 1;
2060 t.bitfield.imm32s = 1;
2061 }
2062 else if (fits_in_signed_long (num))
2063 {
2064 t.bitfield.imm32 = 1;
2065 t.bitfield.imm32s = 1;
2066 }
2067 else if (fits_in_unsigned_long (num))
2068 t.bitfield.imm32 = 1;
2069
2070 return t;
47926f60 2071}
252b5132 2072
847f7ad4 2073static offsetT
e3bb37b5 2074offset_in_range (offsetT val, int size)
847f7ad4 2075{
508866be 2076 addressT mask;
ba2adb93 2077
847f7ad4
AM		 2078 switch (size)
2079 {
508866be
L		 2080 case 1: mask = ((addressT) 1 << 8) - 1; break;
2081 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2082 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2083#ifdef BFD64
2084 case 8: mask = ((addressT) 2 << 63) - 1; break;
2085#endif
47926f60 2086 default: abort ();
847f7ad4
AM		 2087 }
2088
9de868bf
L		 2089#ifdef BFD64
2090 /* If BFD64, sign extend val for 32bit address mode. */
2091 if (flag_code != CODE_64BIT
2092 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2093 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2094 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2095#endif
ba2adb93 2096
47926f60 2097 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2098 {
2099 char buf1[40], buf2[40];
2100
2101 sprint_value (buf1, val);
2102 sprint_value (buf2, val & mask);
2103 as_warn (_("%s shortened to %s"), buf1, buf2);
2104 }
2105 return val & mask;
2106}
2107
c32fa91d
L		 2108enum PREFIX_GROUP
2109{
2110 PREFIX_EXIST = 0,
2111 PREFIX_LOCK,
2112 PREFIX_REP,
2113 PREFIX_OTHER
2114};
2115
2116/* Returns
2117 a. PREFIX_EXIST if attempting to add a prefix where one from the
2118 same class already exists.
2119 b. PREFIX_LOCK if lock prefix is added.
2120 c. PREFIX_REP if rep/repne prefix is added.
2121 d. PREFIX_OTHER if other prefix is added.
2122 */
2123
2124static enum PREFIX_GROUP
e3bb37b5 2125add_prefix (unsigned int prefix)
252b5132 2126{
c32fa91d 2127 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2128 unsigned int q;
252b5132 2129
29b0f896
AM		 2130 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2131 && flag_code == CODE_64BIT)
b1905489 2132 {
161a04f6
L		 2133 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2134 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2135 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2136 ret = PREFIX_EXIST;
b1905489
JB		 2137 q = REX_PREFIX;
2138 }
3e73aa7c 2139 else
b1905489
JB		 2140 {
2141 switch (prefix)
2142 {
2143 default:
2144 abort ();
2145
2146 case CS_PREFIX_OPCODE:
2147 case DS_PREFIX_OPCODE:
2148 case ES_PREFIX_OPCODE:
2149 case FS_PREFIX_OPCODE:
2150 case GS_PREFIX_OPCODE:
2151 case SS_PREFIX_OPCODE:
2152 q = SEG_PREFIX;
2153 break;
2154
2155 case REPNE_PREFIX_OPCODE:
2156 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2157 q = REP_PREFIX;
2158 ret = PREFIX_REP;
2159 break;
2160
b1905489 2161 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2162 q = LOCK_PREFIX;
2163 ret = PREFIX_LOCK;
b1905489
JB		 2164 break;
2165
2166 case FWAIT_OPCODE:
2167 q = WAIT_PREFIX;
2168 break;
2169
2170 case ADDR_PREFIX_OPCODE:
2171 q = ADDR_PREFIX;
2172 break;
2173
2174 case DATA_PREFIX_OPCODE:
2175 q = DATA_PREFIX;
2176 break;
2177 }
2178 if (i.prefix[q] != 0)
c32fa91d 2179 ret = PREFIX_EXIST;
b1905489 2180 }
252b5132 2181
b1905489 2182 if (ret)
252b5132 2183 {
b1905489
JB		 2184 if (!i.prefix[q])
2185 ++i.prefixes;
2186 i.prefix[q] |= prefix;
252b5132 2187 }
b1905489
JB		 2188 else
2189 as_bad (_("same type of prefix used twice"));
252b5132 2190
252b5132
RH		 2191 return ret;
2192}
2193
2194static void
78f12dd3 2195update_code_flag (int value, int check)
eecb386c 2196{
78f12dd3
L		 2197 PRINTF_LIKE ((*as_error));
2198
1e9cc1c2 2199 flag_code = (enum flag_code) value;
40fb9820
L		 2200 if (flag_code == CODE_64BIT)
2201 {
2202 cpu_arch_flags.bitfield.cpu64 = 1;
2203 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2204 }
2205 else
2206 {
2207 cpu_arch_flags.bitfield.cpu64 = 0;
2208 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2209 }
2210 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2211 {
78f12dd3
L		 2212 if (check)
2213 as_error = as_fatal;
2214 else
2215 as_error = as_bad;
2216 (*as_error) (_("64bit mode not supported on `%s'."),
2217 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2218 }
40fb9820 2219 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2220 {
78f12dd3
L		 2221 if (check)
2222 as_error = as_fatal;
2223 else
2224 as_error = as_bad;
2225 (*as_error) (_("32bit mode not supported on `%s'."),
2226 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2227 }
eecb386c
AM		 2228 stackop_size = '\0';
2229}
2230
78f12dd3
L		 2231static void
2232set_code_flag (int value)
2233{
2234 update_code_flag (value, 0);
2235}
2236
eecb386c 2237static void
e3bb37b5 2238set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2239{
1e9cc1c2 2240 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2241 if (flag_code != CODE_16BIT)
2242 abort ();
2243 cpu_arch_flags.bitfield.cpu64 = 0;
2244 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2245 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2246}
2247
2248static void
e3bb37b5 2249set_intel_syntax (int syntax_flag)
252b5132
RH		 2250{
2251 /* Find out if register prefixing is specified. */
2252 int ask_naked_reg = 0;
2253
2254 SKIP_WHITESPACE ();
29b0f896 2255 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2256 {
d02603dc
NC		 2257 char *string;
2258 int e = get_symbol_name (&string);
252b5132 2259
47926f60 2260 if (strcmp (string, "prefix") == 0)
252b5132 2261 ask_naked_reg = 1;
47926f60 2262 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2263 ask_naked_reg = -1;
2264 else
d0b47220 2265 as_bad (_("bad argument to syntax directive."));
d02603dc 2266 (void) restore_line_pointer (e);
252b5132
RH		 2267 }
2268 demand_empty_rest_of_line ();
c3332e24 2269
252b5132
RH		 2270 intel_syntax = syntax_flag;
2271
2272 if (ask_naked_reg == 0)
f86103b7
AM		 2273 allow_naked_reg = (intel_syntax
2274 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2275 else
2276 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2277
ee86248c 2278 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2279
e4a3b5a4 2280 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2281 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2282 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2283}
2284
1efbbeb4
L		 2285static void
2286set_intel_mnemonic (int mnemonic_flag)
2287{
e1d4d893 2288 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2289}
2290
db51cc60
L		 2291static void
2292set_allow_index_reg (int flag)
2293{
2294 allow_index_reg = flag;
2295}
2296
cb19c032 2297static void
7bab8ab5 2298set_check (int what)
cb19c032 2299{
7bab8ab5
JB		 2300 enum check_kind *kind;
2301 const char *str;
2302
2303 if (what)
2304 {
2305 kind = &operand_check;
2306 str = "operand";
2307 }
2308 else
2309 {
2310 kind = &sse_check;
2311 str = "sse";
2312 }
2313
cb19c032
L		 2314 SKIP_WHITESPACE ();
2315
2316 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2317 {
d02603dc
NC		 2318 char *string;
2319 int e = get_symbol_name (&string);
cb19c032
L		 2320
2321 if (strcmp (string, "none") == 0)
7bab8ab5 2322 *kind = check_none;
cb19c032 2323 else if (strcmp (string, "warning") == 0)
7bab8ab5 2324 *kind = check_warning;
cb19c032 2325 else if (strcmp (string, "error") == 0)
7bab8ab5 2326 *kind = check_error;
cb19c032 2327 else
7bab8ab5 2328 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2329 (void) restore_line_pointer (e);
cb19c032
L		 2330 }
2331 else
7bab8ab5 2332 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2333
2334 demand_empty_rest_of_line ();
2335}
2336
8a9036a4
L		 2337static void
2338check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2339 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2340{
2341#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2342 static const char *arch;
2343
2344 /* Intel LIOM is only supported on ELF. */
2345 if (!IS_ELF)
2346 return;
2347
2348 if (!arch)
2349 {
2350 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2351 use default_arch. */
2352 arch = cpu_arch_name;
2353 if (!arch)
2354 arch = default_arch;
2355 }
2356
81486035
L		 2357 /* If we are targeting Intel MCU, we must enable it. */
2358 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2359 || new_flag.bitfield.cpuiamcu)
2360 return;
2361
3632d14b 2362 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2363 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2364 || new_flag.bitfield.cpul1om)
8a9036a4 2365 return;
76ba9986 2366
7a9068fe
L		 2367 /* If we are targeting Intel K1OM, we must enable it. */
2368 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2369 || new_flag.bitfield.cpuk1om)
2370 return;
2371
8a9036a4
L		 2372 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2373#endif
2374}
2375
e413e4e9 2376static void
e3bb37b5 2377set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2378{
47926f60 2379 SKIP_WHITESPACE ();
e413e4e9 2380
29b0f896 2381 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2382 {
d02603dc
NC		 2383 char *string;
2384 int e = get_symbol_name (&string);
91d6fa6a 2385 unsigned int j;
40fb9820 2386 i386_cpu_flags flags;
e413e4e9 2387
91d6fa6a 2388 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2389 {
91d6fa6a 2390 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2391 {
91d6fa6a 2392 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2393
5c6af06e
JB		 2394 if (*string != '.')
2395 {
91d6fa6a 2396 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2397 cpu_sub_arch_name = NULL;
91d6fa6a 2398 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2399 if (flag_code == CODE_64BIT)
2400 {
2401 cpu_arch_flags.bitfield.cpu64 = 1;
2402 cpu_arch_flags.bitfield.cpuno64 = 0;
2403 }
2404 else
2405 {
2406 cpu_arch_flags.bitfield.cpu64 = 0;
2407 cpu_arch_flags.bitfield.cpuno64 = 1;
2408 }
91d6fa6a
NC		 2409 cpu_arch_isa = cpu_arch[j].type;
2410 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2411 if (!cpu_arch_tune_set)
2412 {
2413 cpu_arch_tune = cpu_arch_isa;
2414 cpu_arch_tune_flags = cpu_arch_isa_flags;
2415 }
5c6af06e
JB		 2416 break;
2417 }
40fb9820 2418
293f5f65
L		 2419 flags = cpu_flags_or (cpu_arch_flags,
2420 cpu_arch[j].flags);
81486035
L		 2421
2422 if (!valid_iamcu_cpu_flags (&flags))
2423 as_fatal (_("`%s' isn't valid for Intel MCU"),
2424 cpu_arch[j].name);
2425 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2426 {
6305a203
L		 2427 if (cpu_sub_arch_name)
2428 {
2429 char *name = cpu_sub_arch_name;
2430 cpu_sub_arch_name = concat (name,
91d6fa6a 2431 cpu_arch[j].name,
1bf57e9f 2432 (const char *) NULL);
6305a203
L		 2433 free (name);
2434 }
2435 else
91d6fa6a 2436 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2437 cpu_arch_flags = flags;
a586129e 2438 cpu_arch_isa_flags = flags;
5c6af06e 2439 }
d02603dc 2440 (void) restore_line_pointer (e);
5c6af06e
JB		 2441 demand_empty_rest_of_line ();
2442 return;
e413e4e9
AM		 2443 }
2444 }
293f5f65
L		 2445
2446 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2447 {
2448 /* Disable an ISA entension. */
2449 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2450 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2451 {
2452 flags = cpu_flags_and_not (cpu_arch_flags,
2453 cpu_noarch[j].flags);
2454 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2455 {
2456 if (cpu_sub_arch_name)
2457 {
2458 char *name = cpu_sub_arch_name;
2459 cpu_sub_arch_name = concat (name, string,
2460 (const char *) NULL);
2461 free (name);
2462 }
2463 else
2464 cpu_sub_arch_name = xstrdup (string);
2465 cpu_arch_flags = flags;
2466 cpu_arch_isa_flags = flags;
2467 }
2468 (void) restore_line_pointer (e);
2469 demand_empty_rest_of_line ();
2470 return;
2471 }
2472
2473 j = ARRAY_SIZE (cpu_arch);
2474 }
2475
91d6fa6a 2476 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2477 as_bad (_("no such architecture: `%s'"), string);
2478
2479 *input_line_pointer = e;
2480 }
2481 else
2482 as_bad (_("missing cpu architecture"));
2483
fddf5b5b
AM		 2484 no_cond_jump_promotion = 0;
2485 if (*input_line_pointer == ','
29b0f896 2486 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2487 {
d02603dc
NC		 2488 char *string;
2489 char e;
2490
2491 ++input_line_pointer;
2492 e = get_symbol_name (&string);
fddf5b5b
AM		 2493
2494 if (strcmp (string, "nojumps") == 0)
2495 no_cond_jump_promotion = 1;
2496 else if (strcmp (string, "jumps") == 0)
2497 ;
2498 else
2499 as_bad (_("no such architecture modifier: `%s'"), string);
2500
d02603dc 2501 (void) restore_line_pointer (e);
fddf5b5b
AM		 2502 }
2503
e413e4e9
AM		 2504 demand_empty_rest_of_line ();
2505}
2506
8a9036a4
L		 2507enum bfd_architecture
2508i386_arch (void)
2509{
3632d14b 2510 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2511 {
2512 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2513 || flag_code != CODE_64BIT)
2514 as_fatal (_("Intel L1OM is 64bit ELF only"));
2515 return bfd_arch_l1om;
2516 }
7a9068fe
L		 2517 else if (cpu_arch_isa == PROCESSOR_K1OM)
2518 {
2519 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2520 || flag_code != CODE_64BIT)
2521 as_fatal (_("Intel K1OM is 64bit ELF only"));
2522 return bfd_arch_k1om;
2523 }
81486035
L		 2524 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2525 {
2526 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2527 || flag_code == CODE_64BIT)
2528 as_fatal (_("Intel MCU is 32bit ELF only"));
2529 return bfd_arch_iamcu;
2530 }
8a9036a4
L		 2531 else
2532 return bfd_arch_i386;
2533}
2534
b9d79e03 2535unsigned long
7016a5d5 2536i386_mach (void)
b9d79e03 2537{
351f65ca 2538 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2539 {
3632d14b 2540 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2541 {
351f65ca
L		 2542 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2543 || default_arch[6] != '\0')
8a9036a4
L		 2544 as_fatal (_("Intel L1OM is 64bit ELF only"));
2545 return bfd_mach_l1om;
2546 }
7a9068fe
L		 2547 else if (cpu_arch_isa == PROCESSOR_K1OM)
2548 {
2549 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2550 || default_arch[6] != '\0')
2551 as_fatal (_("Intel K1OM is 64bit ELF only"));
2552 return bfd_mach_k1om;
2553 }
351f65ca 2554 else if (default_arch[6] == '\0')
8a9036a4 2555 return bfd_mach_x86_64;
351f65ca
L		 2556 else
2557 return bfd_mach_x64_32;
8a9036a4 2558 }
5197d474
L		 2559 else if (!strcmp (default_arch, "i386")
2560 || !strcmp (default_arch, "iamcu"))
81486035
L		 2561 {
2562 if (cpu_arch_isa == PROCESSOR_IAMCU)
2563 {
2564 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2565 as_fatal (_("Intel MCU is 32bit ELF only"));
2566 return bfd_mach_i386_iamcu;
2567 }
2568 else
2569 return bfd_mach_i386_i386;
2570 }
b9d79e03 2571 else
2b5d6a91 2572 as_fatal (_("unknown architecture"));
b9d79e03 2573}
b9d79e03 2574\f
252b5132 2575void
7016a5d5 2576md_begin (void)
252b5132
RH		 2577{
2578 const char *hash_err;
2579
47926f60 2580 /* Initialize op_hash hash table. */
252b5132
RH		 2581 op_hash = hash_new ();
2582
2583 {
d3ce72d0 2584 const insn_template *optab;
29b0f896 2585 templates *core_optab;
252b5132 2586
47926f60
KH		 2587 /* Setup for loop. */
2588 optab = i386_optab;
add39d23 2589 core_optab = XNEW (templates);
252b5132
RH		 2590 core_optab->start = optab;
2591
2592 while (1)
2593 {
2594 ++optab;
2595 if (optab->name == NULL
2596 || strcmp (optab->name, (optab - 1)->name) != 0)
2597 {
2598 /* different name --> ship out current template list;
47926f60 2599 add to hash table; & begin anew. */
252b5132
RH		 2600 core_optab->end = optab;
2601 hash_err = hash_insert (op_hash,
2602 (optab - 1)->name,
5a49b8ac 2603 (void *) core_optab);
252b5132
RH		 2604 if (hash_err)
2605 {
b37df7c4 2606 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2607 (optab - 1)->name,
2608 hash_err);
2609 }
2610 if (optab->name == NULL)
2611 break;
add39d23 2612 core_optab = XNEW (templates);
252b5132
RH		 2613 core_optab->start = optab;
2614 }
2615 }
2616 }
2617
47926f60 2618 /* Initialize reg_hash hash table. */
252b5132
RH		 2619 reg_hash = hash_new ();
2620 {
29b0f896 2621 const reg_entry *regtab;
c3fe08fa 2622 unsigned int regtab_size = i386_regtab_size;
252b5132 2623
c3fe08fa 2624 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2625 {
5a49b8ac 2626 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2627 if (hash_err)
b37df7c4 2628 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2629 regtab->reg_name,
2630 hash_err);
252b5132
RH		 2631 }
2632 }
2633
47926f60 2634 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2635 {
29b0f896
AM		 2636 int c;
2637 char *p;
252b5132
RH		 2638
2639 for (c = 0; c < 256; c++)
2640 {
3882b010 2641 if (ISDIGIT (c))
252b5132
RH		 2642 {
2643 digit_chars[c] = c;
2644 mnemonic_chars[c] = c;
2645 register_chars[c] = c;
2646 operand_chars[c] = c;
2647 }
3882b010 2648 else if (ISLOWER (c))
252b5132
RH		 2649 {
2650 mnemonic_chars[c] = c;
2651 register_chars[c] = c;
2652 operand_chars[c] = c;
2653 }
3882b010 2654 else if (ISUPPER (c))
252b5132 2655 {
3882b010 2656 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2657 register_chars[c] = mnemonic_chars[c];
2658 operand_chars[c] = c;
2659 }
43234a1e
L		 2660 else if (c == '{' || c == '}')
2661 operand_chars[c] = c;
252b5132 2662
3882b010 2663 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2664 identifier_chars[c] = c;
2665 else if (c >= 128)
2666 {
2667 identifier_chars[c] = c;
2668 operand_chars[c] = c;
2669 }
2670 }
2671
2672#ifdef LEX_AT
2673 identifier_chars['@'] = '@';
32137342
NC		 2674#endif
2675#ifdef LEX_QM
2676 identifier_chars['?'] = '?';
2677 operand_chars['?'] = '?';
252b5132 2678#endif
252b5132 2679 digit_chars['-'] = '-';
c0f3af97 2680 mnemonic_chars['_'] = '_';
791fe849 2681 mnemonic_chars['-'] = '-';
0003779b 2682 mnemonic_chars['.'] = '.';
252b5132
RH		 2683 identifier_chars['_'] = '_';
2684 identifier_chars['.'] = '.';
2685
2686 for (p = operand_special_chars; *p != '\0'; p++)
2687 operand_chars[(unsigned char) *p] = *p;
2688 }
2689
a4447b93
RH		 2690 if (flag_code == CODE_64BIT)
2691 {
ca19b261
KT		 2692#if defined (OBJ_COFF) && defined (TE_PE)
2693 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2694 ? 32 : 16);
2695#else
a4447b93 2696 x86_dwarf2_return_column = 16;
ca19b261 2697#endif
61ff971f 2698 x86_cie_data_alignment = -8;
a4447b93
RH		 2699 }
2700 else
2701 {
2702 x86_dwarf2_return_column = 8;
2703 x86_cie_data_alignment = -4;
2704 }
252b5132
RH		 2705}
2706
2707void
e3bb37b5 2708i386_print_statistics (FILE *file)
252b5132
RH		 2709{
2710 hash_print_statistics (file, "i386 opcode", op_hash);
2711 hash_print_statistics (file, "i386 register", reg_hash);
2712}
2713\f
252b5132
RH		 2714#ifdef DEBUG386
2715
ce8a8b2f 2716/* Debugging routines for md_assemble. */
d3ce72d0 2717static void pte (insn_template *);
40fb9820 2718static void pt (i386_operand_type);
e3bb37b5
L		 2719static void pe (expressionS *);
2720static void ps (symbolS *);
252b5132
RH		 2721
2722static void
e3bb37b5 2723pi (char *line, i386_insn *x)
252b5132 2724{
09137c09 2725 unsigned int j;
252b5132
RH		 2726
2727 fprintf (stdout, "%s: template ", line);
2728 pte (&x->tm);
09f131f2
JH		 2729 fprintf (stdout, " address: base %s index %s scale %x\n",
2730 x->base_reg ? x->base_reg->reg_name : "none",
2731 x->index_reg ? x->index_reg->reg_name : "none",
2732 x->log2_scale_factor);
2733 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2734 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2735 fprintf (stdout, " sib: base %x index %x scale %x\n",
2736 x->sib.base, x->sib.index, x->sib.scale);
2737 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2738 (x->rex & REX_W) != 0,
2739 (x->rex & REX_R) != 0,
2740 (x->rex & REX_X) != 0,
2741 (x->rex & REX_B) != 0);
09137c09 2742 for (j = 0; j < x->operands; j++)
252b5132 2743 {
09137c09
SP		 2744 fprintf (stdout, " #%d: ", j + 1);
2745 pt (x->types[j]);
252b5132 2746 fprintf (stdout, "\n");
09137c09
SP		 2747 if (x->types[j].bitfield.reg8
2748 || x->types[j].bitfield.reg16
2749 || x->types[j].bitfield.reg32
2750 || x->types[j].bitfield.reg64
2751 || x->types[j].bitfield.regmmx
2752 || x->types[j].bitfield.regxmm
2753 || x->types[j].bitfield.regymm
43234a1e 2754 || x->types[j].bitfield.regzmm
09137c09
SP		 2755 || x->types[j].bitfield.sreg2
2756 || x->types[j].bitfield.sreg3
2757 || x->types[j].bitfield.control
2758 || x->types[j].bitfield.debug
2759 || x->types[j].bitfield.test)
2760 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2761 if (operand_type_check (x->types[j], imm))
2762 pe (x->op[j].imms);
2763 if (operand_type_check (x->types[j], disp))
2764 pe (x->op[j].disps);
252b5132
RH		 2765 }
2766}
2767
2768static void
d3ce72d0 2769pte (insn_template *t)
252b5132 2770{
09137c09 2771 unsigned int j;
252b5132 2772 fprintf (stdout, " %d operands ", t->operands);
47926f60 2773 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2774 if (t->extension_opcode != None)
2775 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2776 if (t->opcode_modifier.d)
252b5132 2777 fprintf (stdout, "D");
40fb9820 2778 if (t->opcode_modifier.w)
252b5132
RH		 2779 fprintf (stdout, "W");
2780 fprintf (stdout, "\n");
09137c09 2781 for (j = 0; j < t->operands; j++)
252b5132 2782 {
09137c09
SP		 2783 fprintf (stdout, " #%d type ", j + 1);
2784 pt (t->operand_types[j]);
252b5132
RH		 2785 fprintf (stdout, "\n");
2786 }
2787}
2788
2789static void
e3bb37b5 2790pe (expressionS *e)
252b5132 2791{
24eab124 2792 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2793 fprintf (stdout, " add_number %ld (%lx)\n",
2794 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2795 if (e->X_add_symbol)
2796 {
2797 fprintf (stdout, " add_symbol ");
2798 ps (e->X_add_symbol);
2799 fprintf (stdout, "\n");
2800 }
2801 if (e->X_op_symbol)
2802 {
2803 fprintf (stdout, " op_symbol ");
2804 ps (e->X_op_symbol);
2805 fprintf (stdout, "\n");
2806 }
2807}
2808
2809static void
e3bb37b5 2810ps (symbolS *s)
252b5132
RH		 2811{
2812 fprintf (stdout, "%s type %s%s",
2813 S_GET_NAME (s),
2814 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2815 segment_name (S_GET_SEGMENT (s)));
2816}
2817
7b81dfbb 2818static struct type_name
252b5132 2819 {
40fb9820
L		 2820 i386_operand_type mask;
2821 const char *name;
252b5132 2822 }
7b81dfbb 2823const type_names[] =
252b5132 2824{
40fb9820
L		 2825 { OPERAND_TYPE_REG8, "r8" },
2826 { OPERAND_TYPE_REG16, "r16" },
2827 { OPERAND_TYPE_REG32, "r32" },
2828 { OPERAND_TYPE_REG64, "r64" },
2829 { OPERAND_TYPE_IMM8, "i8" },
2830 { OPERAND_TYPE_IMM8, "i8s" },
2831 { OPERAND_TYPE_IMM16, "i16" },
2832 { OPERAND_TYPE_IMM32, "i32" },
2833 { OPERAND_TYPE_IMM32S, "i32s" },
2834 { OPERAND_TYPE_IMM64, "i64" },
2835 { OPERAND_TYPE_IMM1, "i1" },
2836 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2837 { OPERAND_TYPE_DISP8, "d8" },
2838 { OPERAND_TYPE_DISP16, "d16" },
2839 { OPERAND_TYPE_DISP32, "d32" },
2840 { OPERAND_TYPE_DISP32S, "d32s" },
2841 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2842 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2843 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2844 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2845 { OPERAND_TYPE_CONTROL, "control reg" },
2846 { OPERAND_TYPE_TEST, "test reg" },
2847 { OPERAND_TYPE_DEBUG, "debug reg" },
2848 { OPERAND_TYPE_FLOATREG, "FReg" },
2849 { OPERAND_TYPE_FLOATACC, "FAcc" },
2850 { OPERAND_TYPE_SREG2, "SReg2" },
2851 { OPERAND_TYPE_SREG3, "SReg3" },
2852 { OPERAND_TYPE_ACC, "Acc" },
2853 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2854 { OPERAND_TYPE_REGMMX, "rMMX" },
2855 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2856 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2857 { OPERAND_TYPE_REGZMM, "rZMM" },
2858 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2859 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2860};
2861
2862static void
40fb9820 2863pt (i386_operand_type t)
252b5132 2864{
40fb9820 2865 unsigned int j;
c6fb90c8 2866 i386_operand_type a;
252b5132 2867
40fb9820 2868 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2869 {
2870 a = operand_type_and (t, type_names[j].mask);
0349dc08 2871 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2872 fprintf (stdout, "%s, ", type_names[j].name);
2873 }
252b5132
RH		 2874 fflush (stdout);
2875}
2876
2877#endif /* DEBUG386 */
2878\f
252b5132 2879static bfd_reloc_code_real_type
3956db08 2880reloc (unsigned int size,
64e74474
AM		 2881 int pcrel,
2882 int sign,
2883 bfd_reloc_code_real_type other)
252b5132 2884{
47926f60 2885 if (other != NO_RELOC)
3956db08 2886 {
91d6fa6a 2887 reloc_howto_type *rel;
3956db08
JB		 2888
2889 if (size == 8)
2890 switch (other)
2891 {
64e74474
AM		 2892 case BFD_RELOC_X86_64_GOT32:
2893 return BFD_RELOC_X86_64_GOT64;
2894 break;
553d1284
L		 2895 case BFD_RELOC_X86_64_GOTPLT64:
2896 return BFD_RELOC_X86_64_GOTPLT64;
2897 break;
64e74474
AM		 2898 case BFD_RELOC_X86_64_PLTOFF64:
2899 return BFD_RELOC_X86_64_PLTOFF64;
2900 break;
2901 case BFD_RELOC_X86_64_GOTPC32:
2902 other = BFD_RELOC_X86_64_GOTPC64;
2903 break;
2904 case BFD_RELOC_X86_64_GOTPCREL:
2905 other = BFD_RELOC_X86_64_GOTPCREL64;
2906 break;
2907 case BFD_RELOC_X86_64_TPOFF32:
2908 other = BFD_RELOC_X86_64_TPOFF64;
2909 break;
2910 case BFD_RELOC_X86_64_DTPOFF32:
2911 other = BFD_RELOC_X86_64_DTPOFF64;
2912 break;
2913 default:
2914 break;
3956db08 2915 }
e05278af 2916
8ce3d284 2917#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2918 if (other == BFD_RELOC_SIZE32)
2919 {
2920 if (size == 8)
1ab668bf 2921 other = BFD_RELOC_SIZE64;
8fd4256d 2922 if (pcrel)
1ab668bf
AM		 2923 {
2924 as_bad (_("there are no pc-relative size relocations"));
2925 return NO_RELOC;
2926 }
8fd4256d 2927 }
8ce3d284 2928#endif
8fd4256d 2929
e05278af 2930 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2931 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2932 sign = -1;
2933
91d6fa6a
NC		 2934 rel = bfd_reloc_type_lookup (stdoutput, other);
2935 if (!rel)
3956db08 2936 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2937 else if (size != bfd_get_reloc_size (rel))
3956db08 2938 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2939 bfd_get_reloc_size (rel),
3956db08 2940 size);
91d6fa6a 2941 else if (pcrel && !rel->pc_relative)
3956db08 2942 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2943 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2944 && !sign)
91d6fa6a 2945 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2946 && sign > 0))
3956db08
JB		 2947 as_bad (_("relocated field and relocation type differ in signedness"));
2948 else
2949 return other;
2950 return NO_RELOC;
2951 }
252b5132
RH		 2952
2953 if (pcrel)
2954 {
3e73aa7c 2955 if (!sign)
3956db08 2956 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2957 switch (size)
2958 {
2959 case 1: return BFD_RELOC_8_PCREL;
2960 case 2: return BFD_RELOC_16_PCREL;
d258b828 2961 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2962 case 8: return BFD_RELOC_64_PCREL;
252b5132 2963 }
3956db08 2964 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2965 }
2966 else
2967 {
3956db08 2968 if (sign > 0)
e5cb08ac 2969 switch (size)
3e73aa7c
JH		 2970 {
2971 case 4: return BFD_RELOC_X86_64_32S;
2972 }
2973 else
2974 switch (size)
2975 {
2976 case 1: return BFD_RELOC_8;
2977 case 2: return BFD_RELOC_16;
2978 case 4: return BFD_RELOC_32;
2979 case 8: return BFD_RELOC_64;
2980 }
3956db08
JB		 2981 as_bad (_("cannot do %s %u byte relocation"),
2982 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2983 }
2984
0cc9e1d3 2985 return NO_RELOC;
252b5132
RH		 2986}
2987
47926f60
KH		 2988/* Here we decide which fixups can be adjusted to make them relative to
2989 the beginning of the section instead of the symbol. Basically we need
2990 to make sure that the dynamic relocations are done correctly, so in
2991 some cases we force the original symbol to be used. */
2992
252b5132 2993int
e3bb37b5 2994tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2995{
6d249963 2996#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2997 if (!IS_ELF)
31312f95
AM		 2998 return 1;
2999
a161fe53
AM		 3000 /* Don't adjust pc-relative references to merge sections in 64-bit
3001 mode. */
3002 if (use_rela_relocations
3003 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3004 && fixP->fx_pcrel)
252b5132 3005 return 0;
31312f95 3006
8d01d9a9
AJ		 3007 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3008 and changed later by validate_fix. */
3009 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3010 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3011 return 0;
3012
8fd4256d
L		 3013 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3014 for size relocations. */
3015 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3016 || fixP->fx_r_type == BFD_RELOC_SIZE64
3017 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3018 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3019 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3020 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3021 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3022 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3023 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3024 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3025 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3026 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3027 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3028 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3029 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3030 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3031 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3032 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3033 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3034 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3035 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3036 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3037 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3038 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3039 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3040 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3041 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3042 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3043 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3045 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3046 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3047 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3048 return 0;
31312f95 3049#endif
252b5132
RH		 3050 return 1;
3051}
252b5132 3052
b4cac588 3053static int
e3bb37b5 3054intel_float_operand (const char *mnemonic)
252b5132 3055{
9306ca4a
JB		 3056 /* Note that the value returned is meaningful only for opcodes with (memory)
3057 operands, hence the code here is free to improperly handle opcodes that
3058 have no operands (for better performance and smaller code). */
3059
3060 if (mnemonic[0] != 'f')
3061 return 0; /* non-math */
3062
3063 switch (mnemonic[1])
3064 {
3065 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3066 the fs segment override prefix not currently handled because no
3067 call path can make opcodes without operands get here */
3068 case 'i':
3069 return 2 /* integer op */;
3070 case 'l':
3071 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3072 return 3; /* fldcw/fldenv */
3073 break;
3074 case 'n':
3075 if (mnemonic[2] != 'o' /* fnop */)
3076 return 3; /* non-waiting control op */
3077 break;
3078 case 'r':
3079 if (mnemonic[2] == 's')
3080 return 3; /* frstor/frstpm */
3081 break;
3082 case 's':
3083 if (mnemonic[2] == 'a')
3084 return 3; /* fsave */
3085 if (mnemonic[2] == 't')
3086 {
3087 switch (mnemonic[3])
3088 {
3089 case 'c': /* fstcw */
3090 case 'd': /* fstdw */
3091 case 'e': /* fstenv */
3092 case 's': /* fsts[gw] */
3093 return 3;
3094 }
3095 }
3096 break;
3097 case 'x':
3098 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3099 return 0; /* fxsave/fxrstor are not really math ops */
3100 break;
3101 }
252b5132 3102
9306ca4a 3103 return 1;
252b5132
RH		 3104}
3105
c0f3af97
L		 3106/* Build the VEX prefix. */
3107
3108static void
d3ce72d0 3109build_vex_prefix (const insn_template *t)
c0f3af97
L		 3110{
3111 unsigned int register_specifier;
3112 unsigned int implied_prefix;
3113 unsigned int vector_length;
3114
3115 /* Check register specifier. */
3116 if (i.vex.register_specifier)
43234a1e
L		 3117 {
3118 register_specifier =
3119 ~register_number (i.vex.register_specifier) & 0xf;
3120 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3121 }
c0f3af97
L		 3122 else
3123 register_specifier = 0xf;
3124
fa99fab2
L		 3125 /* Use 2-byte VEX prefix by swappping destination and source
3126 operand. */
3127 if (!i.swap_operand
3128 && i.operands == i.reg_operands
7f399153 3129 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3130 && i.tm.opcode_modifier.s
3131 && i.rex == REX_B)
3132 {
3133 unsigned int xchg = i.operands - 1;
3134 union i386_op temp_op;
3135 i386_operand_type temp_type;
3136
3137 temp_type = i.types[xchg];
3138 i.types[xchg] = i.types[0];
3139 i.types[0] = temp_type;
3140 temp_op = i.op[xchg];
3141 i.op[xchg] = i.op[0];
3142 i.op[0] = temp_op;
3143
9c2799c2 3144 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3145
3146 i.rex = REX_R;
3147 xchg = i.rm.regmem;
3148 i.rm.regmem = i.rm.reg;
3149 i.rm.reg = xchg;
3150
3151 /* Use the next insn. */
3152 i.tm = t[1];
3153 }
3154
539f890d
L		 3155 if (i.tm.opcode_modifier.vex == VEXScalar)
3156 vector_length = avxscalar;
3157 else
3158 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3159
3160 switch ((i.tm.base_opcode >> 8) & 0xff)
3161 {
3162 case 0:
3163 implied_prefix = 0;
3164 break;
3165 case DATA_PREFIX_OPCODE:
3166 implied_prefix = 1;
3167 break;
3168 case REPE_PREFIX_OPCODE:
3169 implied_prefix = 2;
3170 break;
3171 case REPNE_PREFIX_OPCODE:
3172 implied_prefix = 3;
3173 break;
3174 default:
3175 abort ();
3176 }
3177
3178 /* Use 2-byte VEX prefix if possible. */
7f399153 3179 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3180 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3181 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3182 {
3183 /* 2-byte VEX prefix. */
3184 unsigned int r;
3185
3186 i.vex.length = 2;
3187 i.vex.bytes[0] = 0xc5;
3188
3189 /* Check the REX.R bit. */
3190 r = (i.rex & REX_R) ? 0 : 1;
3191 i.vex.bytes[1] = (r << 7
3192 | register_specifier << 3
3193 | vector_length << 2
3194 | implied_prefix);
3195 }
3196 else
3197 {
3198 /* 3-byte VEX prefix. */
3199 unsigned int m, w;
3200
f88c9eb0 3201 i.vex.length = 3;
f88c9eb0 3202
7f399153 3203 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3204 {
7f399153
L		 3205 case VEX0F:
3206 m = 0x1;
80de6e00 3207 i.vex.bytes[0] = 0xc4;
7f399153
L		 3208 break;
3209 case VEX0F38:
3210 m = 0x2;
80de6e00 3211 i.vex.bytes[0] = 0xc4;
7f399153
L		 3212 break;
3213 case VEX0F3A:
3214 m = 0x3;
80de6e00 3215 i.vex.bytes[0] = 0xc4;
7f399153
L		 3216 break;
3217 case XOP08:
5dd85c99
SP		 3218 m = 0x8;
3219 i.vex.bytes[0] = 0x8f;
7f399153
L		 3220 break;
3221 case XOP09:
f88c9eb0
SP		 3222 m = 0x9;
3223 i.vex.bytes[0] = 0x8f;
7f399153
L		 3224 break;
3225 case XOP0A:
f88c9eb0
SP		 3226 m = 0xa;
3227 i.vex.bytes[0] = 0x8f;
7f399153
L		 3228 break;
3229 default:
3230 abort ();
f88c9eb0 3231 }
c0f3af97 3232
c0f3af97
L		 3233 /* The high 3 bits of the second VEX byte are 1's compliment
3234 of RXB bits from REX. */
3235 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3236
3237 /* Check the REX.W bit. */
3238 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3239 if (i.tm.opcode_modifier.vexw == VEXW1)
3240 w = 1;
c0f3af97
L		 3241
3242 i.vex.bytes[2] = (w << 7
3243 | register_specifier << 3
3244 | vector_length << 2
3245 | implied_prefix);
3246 }
3247}
3248
43234a1e
L		 3249/* Build the EVEX prefix. */
3250
3251static void
3252build_evex_prefix (void)
3253{
3254 unsigned int register_specifier;
3255 unsigned int implied_prefix;
3256 unsigned int m, w;
3257 rex_byte vrex_used = 0;
3258
3259 /* Check register specifier. */
3260 if (i.vex.register_specifier)
3261 {
3262 gas_assert ((i.vrex & REX_X) == 0);
3263
3264 register_specifier = i.vex.register_specifier->reg_num;
3265 if ((i.vex.register_specifier->reg_flags & RegRex))
3266 register_specifier += 8;
3267 /* The upper 16 registers are encoded in the fourth byte of the
3268 EVEX prefix. */
3269 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3270 i.vex.bytes[3] = 0x8;
3271 register_specifier = ~register_specifier & 0xf;
3272 }
3273 else
3274 {
3275 register_specifier = 0xf;
3276
3277 /* Encode upper 16 vector index register in the fourth byte of
3278 the EVEX prefix. */
3279 if (!(i.vrex & REX_X))
3280 i.vex.bytes[3] = 0x8;
3281 else
3282 vrex_used |= REX_X;
3283 }
3284
3285 switch ((i.tm.base_opcode >> 8) & 0xff)
3286 {
3287 case 0:
3288 implied_prefix = 0;
3289 break;
3290 case DATA_PREFIX_OPCODE:
3291 implied_prefix = 1;
3292 break;
3293 case REPE_PREFIX_OPCODE:
3294 implied_prefix = 2;
3295 break;
3296 case REPNE_PREFIX_OPCODE:
3297 implied_prefix = 3;
3298 break;
3299 default:
3300 abort ();
3301 }
3302
3303 /* 4 byte EVEX prefix. */
3304 i.vex.length = 4;
3305 i.vex.bytes[0] = 0x62;
3306
3307 /* mmmm bits. */
3308 switch (i.tm.opcode_modifier.vexopcode)
3309 {
3310 case VEX0F:
3311 m = 1;
3312 break;
3313 case VEX0F38:
3314 m = 2;
3315 break;
3316 case VEX0F3A:
3317 m = 3;
3318 break;
3319 default:
3320 abort ();
3321 break;
3322 }
3323
3324 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3325 bits from REX. */
3326 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3327
3328 /* The fifth bit of the second EVEX byte is 1's compliment of the
3329 REX_R bit in VREX. */
3330 if (!(i.vrex & REX_R))
3331 i.vex.bytes[1] |= 0x10;
3332 else
3333 vrex_used |= REX_R;
3334
3335 if ((i.reg_operands + i.imm_operands) == i.operands)
3336 {
3337 /* When all operands are registers, the REX_X bit in REX is not
3338 used. We reuse it to encode the upper 16 registers, which is
3339 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3340 as 1's compliment. */
3341 if ((i.vrex & REX_B))
3342 {
3343 vrex_used |= REX_B;
3344 i.vex.bytes[1] &= ~0x40;
3345 }
3346 }
3347
3348 /* EVEX instructions shouldn't need the REX prefix. */
3349 i.vrex &= ~vrex_used;
3350 gas_assert (i.vrex == 0);
3351
3352 /* Check the REX.W bit. */
3353 w = (i.rex & REX_W) ? 1 : 0;
3354 if (i.tm.opcode_modifier.vexw)
3355 {
3356 if (i.tm.opcode_modifier.vexw == VEXW1)
3357 w = 1;
3358 }
3359 /* If w is not set it means we are dealing with WIG instruction. */
3360 else if (!w)
3361 {
3362 if (evexwig == evexw1)
3363 w = 1;
3364 }
3365
3366 /* Encode the U bit. */
3367 implied_prefix |= 0x4;
3368
3369 /* The third byte of the EVEX prefix. */
3370 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3371
3372 /* The fourth byte of the EVEX prefix. */
3373 /* The zeroing-masking bit. */
3374 if (i.mask && i.mask->zeroing)
3375 i.vex.bytes[3] |= 0x80;
3376
3377 /* Don't always set the broadcast bit if there is no RC. */
3378 if (!i.rounding)
3379 {
3380 /* Encode the vector length. */
3381 unsigned int vec_length;
3382
3383 switch (i.tm.opcode_modifier.evex)
3384 {
3385 case EVEXLIG: /* LL' is ignored */
3386 vec_length = evexlig << 5;
3387 break;
3388 case EVEX128:
3389 vec_length = 0 << 5;
3390 break;
3391 case EVEX256:
3392 vec_length = 1 << 5;
3393 break;
3394 case EVEX512:
3395 vec_length = 2 << 5;
3396 break;
3397 default:
3398 abort ();
3399 break;
3400 }
3401 i.vex.bytes[3] |= vec_length;
3402 /* Encode the broadcast bit. */
3403 if (i.broadcast)
3404 i.vex.bytes[3] |= 0x10;
3405 }
3406 else
3407 {
3408 if (i.rounding->type != saeonly)
3409 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3410 else
d3d3c6db 3411 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3412 }
3413
3414 if (i.mask && i.mask->mask)
3415 i.vex.bytes[3] |= i.mask->mask->reg_num;
3416}
3417
65da13b5
L		 3418static void
3419process_immext (void)
3420{
3421 expressionS *exp;
3422
4c692bc7
JB		 3423 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3424 && i.operands > 0)
65da13b5 3425 {
4c692bc7
JB		 3426 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3427 with an opcode suffix which is coded in the same place as an
3428 8-bit immediate field would be.
3429 Here we check those operands and remove them afterwards. */
65da13b5
L		 3430 unsigned int x;
3431
3432 for (x = 0; x < i.operands; x++)
4c692bc7 3433 if (register_number (i.op[x].regs) != x)
65da13b5 3434 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3435 register_prefix, i.op[x].regs->reg_name, x + 1,
3436 i.tm.name);
3437
3438 i.operands = 0;
65da13b5
L		 3439 }
3440
9916071f
AP		 3441 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3442 {
3443 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3444 suffix which is coded in the same place as an 8-bit immediate
3445 field would be.
3446 Here we check those operands and remove them afterwards. */
3447 unsigned int x;
3448
3449 if (i.operands != 3)
3450 abort();
3451
3452 for (x = 0; x < 2; x++)
3453 if (register_number (i.op[x].regs) != x)
3454 goto bad_register_operand;
3455
3456 /* Check for third operand for mwaitx/monitorx insn. */
3457 if (register_number (i.op[x].regs)
3458 != (x + (i.tm.extension_opcode == 0xfb)))
3459 {
3460bad_register_operand:
3461 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3462 register_prefix, i.op[x].regs->reg_name, x+1,
3463 i.tm.name);
3464 }
3465
3466 i.operands = 0;
3467 }
3468
c0f3af97 3469 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3470 which is coded in the same place as an 8-bit immediate field
3471 would be. Here we fake an 8-bit immediate operand from the
3472 opcode suffix stored in tm.extension_opcode.
3473
c1e679ec 3474 AVX instructions also use this encoding, for some of
c0f3af97 3475 3 argument instructions. */
65da13b5 3476
43234a1e 3477 gas_assert (i.imm_operands <= 1
7ab9ffdd 3478 && (i.operands <= 2
43234a1e
L		 3479 || ((i.tm.opcode_modifier.vex
3480 || i.tm.opcode_modifier.evex)
7ab9ffdd 3481 && i.operands <= 4)));
65da13b5
L		 3482
3483 exp = &im_expressions[i.imm_operands++];
3484 i.op[i.operands].imms = exp;
3485 i.types[i.operands] = imm8;
3486 i.operands++;
3487 exp->X_op = O_constant;
3488 exp->X_add_number = i.tm.extension_opcode;
3489 i.tm.extension_opcode = None;
3490}
3491
42164a71
L		 3492
3493static int
3494check_hle (void)
3495{
3496 switch (i.tm.opcode_modifier.hleprefixok)
3497 {
3498 default:
3499 abort ();
82c2def5 3500 case HLEPrefixNone:
165de32a
L		 3501 as_bad (_("invalid instruction `%s' after `%s'"),
3502 i.tm.name, i.hle_prefix);
42164a71 3503 return 0;
82c2def5 3504 case HLEPrefixLock:
42164a71
L		 3505 if (i.prefix[LOCK_PREFIX])
3506 return 1;
165de32a 3507 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3508 return 0;
82c2def5 3509 case HLEPrefixAny:
42164a71 3510 return 1;
82c2def5 3511 case HLEPrefixRelease:
42164a71
L		 3512 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3513 {
3514 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3515 i.tm.name);
3516 return 0;
3517 }
3518 if (i.mem_operands == 0
3519 || !operand_type_check (i.types[i.operands - 1], anymem))
3520 {
3521 as_bad (_("memory destination needed for instruction `%s'"
3522 " after `xrelease'"), i.tm.name);
3523 return 0;
3524 }
3525 return 1;
3526 }
3527}
3528
252b5132
RH		 3529/* This is the guts of the machine-dependent assembler. LINE points to a
3530 machine dependent instruction. This function is supposed to emit
3531 the frags/bytes it assembles to. */
3532
3533void
65da13b5 3534md_assemble (char *line)
252b5132 3535{
40fb9820 3536 unsigned int j;
252b5132 3537 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3538 const insn_template *t;
252b5132 3539
47926f60 3540 /* Initialize globals. */
252b5132
RH		 3541 memset (&i, '\0', sizeof (i));
3542 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3543 i.reloc[j] = NO_RELOC;
252b5132
RH		 3544 memset (disp_expressions, '\0', sizeof (disp_expressions));
3545 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3546 save_stack_p = save_stack;
252b5132
RH		 3547
3548 /* First parse an instruction mnemonic & call i386_operand for the operands.
3549 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3550 start of a (possibly prefixed) mnemonic. */
252b5132 3551
29b0f896
AM		 3552 line = parse_insn (line, mnemonic);
3553 if (line == NULL)
3554 return;
252b5132 3555
29b0f896 3556 line = parse_operands (line, mnemonic);
ee86248c 3557 this_operand = -1;
29b0f896
AM		 3558 if (line == NULL)
3559 return;
252b5132 3560
29b0f896
AM		 3561 /* Now we've parsed the mnemonic into a set of templates, and have the
3562 operands at hand. */
3563
3564 /* All intel opcodes have reversed operands except for "bound" and
3565 "enter". We also don't reverse intersegment "jmp" and "call"
3566 instructions with 2 immediate operands so that the immediate segment
050dfa73 3567 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3568 if (intel_syntax
3569 && i.operands > 1
29b0f896 3570 && (strcmp (mnemonic, "bound") != 0)
30123838 3571 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3572 && !(operand_type_check (i.types[0], imm)
3573 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3574 swap_operands ();
3575
ec56d5c0
JB		 3576 /* The order of the immediates should be reversed
3577 for 2 immediates extrq and insertq instructions */
3578 if (i.imm_operands == 2
3579 && (strcmp (mnemonic, "extrq") == 0
3580 || strcmp (mnemonic, "insertq") == 0))
3581 swap_2_operands (0, 1);
3582
29b0f896
AM		 3583 if (i.imm_operands)
3584 optimize_imm ();
3585
b300c311
L		 3586 /* Don't optimize displacement for movabs since it only takes 64bit
3587 displacement. */
3588 if (i.disp_operands
a501d77e 3589 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3590 && (flag_code != CODE_64BIT
3591 || strcmp (mnemonic, "movabs") != 0))
3592 optimize_disp ();
29b0f896
AM		 3593
3594 /* Next, we find a template that matches the given insn,
3595 making sure the overlap of the given operands types is consistent
3596 with the template operand types. */
252b5132 3597
fa99fab2 3598 if (!(t = match_template ()))
29b0f896 3599 return;
252b5132 3600
7bab8ab5 3601 if (sse_check != check_none
81f8a913 3602 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3603 && (i.tm.cpu_flags.bitfield.cpusse
3604 || i.tm.cpu_flags.bitfield.cpusse2
3605 || i.tm.cpu_flags.bitfield.cpusse3
3606 || i.tm.cpu_flags.bitfield.cpussse3
3607 || i.tm.cpu_flags.bitfield.cpusse4_1
3608 || i.tm.cpu_flags.bitfield.cpusse4_2))
3609 {
7bab8ab5 3610 (sse_check == check_warning
daf50ae7
L		 3611 ? as_warn
3612 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3613 }
3614
321fd21e
L		 3615 /* Zap movzx and movsx suffix. The suffix has been set from
3616 "word ptr" or "byte ptr" on the source operand in Intel syntax
3617 or extracted from mnemonic in AT&T syntax. But we'll use
3618 the destination register to choose the suffix for encoding. */
3619 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3620 {
321fd21e
L		 3621 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3622 there is no suffix, the default will be byte extension. */
3623 if (i.reg_operands != 2
3624 && !i.suffix
7ab9ffdd 3625 && intel_syntax)
321fd21e
L		 3626 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3627
3628 i.suffix = 0;
cd61ebfe 3629 }
24eab124 3630
40fb9820 3631 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3632 if (!add_prefix (FWAIT_OPCODE))
3633 return;
252b5132 3634
d5de92cf
L		 3635 /* Check if REP prefix is OK. */
3636 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3637 {
3638 as_bad (_("invalid instruction `%s' after `%s'"),
3639 i.tm.name, i.rep_prefix);
3640 return;
3641 }
3642
c1ba0266
L		 3643 /* Check for lock without a lockable instruction. Destination operand
3644 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3645 if (i.prefix[LOCK_PREFIX]
3646 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3647 || i.mem_operands == 0
3648 || (i.tm.base_opcode != 0x86
3649 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3650 {
3651 as_bad (_("expecting lockable instruction after `lock'"));
3652 return;
3653 }
3654
42164a71 3655 /* Check if HLE prefix is OK. */
165de32a 3656 if (i.hle_prefix && !check_hle ())
42164a71
L		 3657 return;
3658
7e8b059b
L		 3659 /* Check BND prefix. */
3660 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3661 as_bad (_("expecting valid branch instruction after `bnd'"));
3662
3663 if (i.tm.cpu_flags.bitfield.cpumpx
3664 && flag_code == CODE_64BIT
3665 && i.prefix[ADDR_PREFIX])
3666 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3667
3668 /* Insert BND prefix. */
3669 if (add_bnd_prefix
3670 && i.tm.opcode_modifier.bndprefixok
3671 && !i.prefix[BND_PREFIX])
3672 add_prefix (BND_PREFIX_OPCODE);
3673
29b0f896 3674 /* Check string instruction segment overrides. */
40fb9820 3675 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3676 {
3677 if (!check_string ())
5dd0794d 3678 return;
fc0763e6 3679 i.disp_operands = 0;
29b0f896 3680 }
5dd0794d 3681
29b0f896
AM		 3682 if (!process_suffix ())
3683 return;
e413e4e9 3684
bc0844ae
L		 3685 /* Update operand types. */
3686 for (j = 0; j < i.operands; j++)
3687 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3688
29b0f896
AM		 3689 /* Make still unresolved immediate matches conform to size of immediate
3690 given in i.suffix. */
3691 if (!finalize_imm ())
3692 return;
252b5132 3693
40fb9820 3694 if (i.types[0].bitfield.imm1)
29b0f896 3695 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3696
9afe6eb8
L		 3697 /* We only need to check those implicit registers for instructions
3698 with 3 operands or less. */
3699 if (i.operands <= 3)
3700 for (j = 0; j < i.operands; j++)
3701 if (i.types[j].bitfield.inoutportreg
3702 || i.types[j].bitfield.shiftcount
3703 || i.types[j].bitfield.acc
3704 || i.types[j].bitfield.floatacc)
3705 i.reg_operands--;
40fb9820 3706
c0f3af97
L		 3707 /* ImmExt should be processed after SSE2AVX. */
3708 if (!i.tm.opcode_modifier.sse2avx
3709 && i.tm.opcode_modifier.immext)
65da13b5 3710 process_immext ();
252b5132 3711
29b0f896
AM		 3712 /* For insns with operands there are more diddles to do to the opcode. */
3713 if (i.operands)
3714 {
3715 if (!process_operands ())
3716 return;
3717 }
40fb9820 3718 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3719 {
3720 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3721 as_warn (_("translating to `%sp'"), i.tm.name);
3722 }
252b5132 3723
9e5e5283
L		 3724 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3725 {
3726 if (flag_code == CODE_16BIT)
3727 {
3728 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3729 i.tm.name);
3730 return;
3731 }
c0f3af97 3732
9e5e5283
L		 3733 if (i.tm.opcode_modifier.vex)
3734 build_vex_prefix (t);
3735 else
3736 build_evex_prefix ();
3737 }
43234a1e 3738
5dd85c99
SP		 3739 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3740 instructions may define INT_OPCODE as well, so avoid this corner
3741 case for those instructions that use MODRM. */
3742 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3743 && !i.tm.opcode_modifier.modrm
3744 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3745 {
3746 i.tm.base_opcode = INT3_OPCODE;
3747 i.imm_operands = 0;
3748 }
252b5132 3749
40fb9820
L		 3750 if ((i.tm.opcode_modifier.jump
3751 || i.tm.opcode_modifier.jumpbyte
3752 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3753 && i.op[0].disps->X_op == O_constant)
3754 {
3755 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3756 the absolute address given by the constant. Since ix86 jumps and
3757 calls are pc relative, we need to generate a reloc. */
3758 i.op[0].disps->X_add_symbol = &abs_symbol;
3759 i.op[0].disps->X_op = O_symbol;
3760 }
252b5132 3761
40fb9820 3762 if (i.tm.opcode_modifier.rex64)
161a04f6 3763 i.rex |= REX_W;
252b5132 3764
29b0f896
AM		 3765 /* For 8 bit registers we need an empty rex prefix. Also if the
3766 instruction already has a prefix, we need to convert old
3767 registers to new ones. */
773f551c 3768
40fb9820 3769 if ((i.types[0].bitfield.reg8
29b0f896 3770 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3771 || (i.types[1].bitfield.reg8
29b0f896 3772 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3773 || ((i.types[0].bitfield.reg8
3774 || i.types[1].bitfield.reg8)
29b0f896
AM		 3775 && i.rex != 0))
3776 {
3777 int x;
726c5dcd 3778
29b0f896
AM		 3779 i.rex |= REX_OPCODE;
3780 for (x = 0; x < 2; x++)
3781 {
3782 /* Look for 8 bit operand that uses old registers. */
40fb9820 3783 if (i.types[x].bitfield.reg8
29b0f896 3784 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3785 {
29b0f896
AM		 3786 /* In case it is "hi" register, give up. */
3787 if (i.op[x].regs->reg_num > 3)
a540244d 3788 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3789 "instruction requiring REX prefix."),
a540244d 3790 register_prefix, i.op[x].regs->reg_name);
773f551c 3791
29b0f896
AM		 3792 /* Otherwise it is equivalent to the extended register.
3793 Since the encoding doesn't change this is merely
3794 cosmetic cleanup for debug output. */
3795
3796 i.op[x].regs = i.op[x].regs + 8;
773f551c 3797 }
29b0f896
AM		 3798 }
3799 }
773f551c 3800
7ab9ffdd 3801 if (i.rex != 0)
29b0f896
AM		 3802 add_prefix (REX_OPCODE | i.rex);
3803
3804 /* We are ready to output the insn. */
3805 output_insn ();
3806}
3807
3808static char *
e3bb37b5 3809parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3810{
3811 char *l = line;
3812 char *token_start = l;
3813 char *mnem_p;
5c6af06e 3814 int supported;
d3ce72d0 3815 const insn_template *t;
b6169b20 3816 char *dot_p = NULL;
29b0f896 3817
29b0f896
AM		 3818 while (1)
3819 {
3820 mnem_p = mnemonic;
3821 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3822 {
b6169b20
L		 3823 if (*mnem_p == '.')
3824 dot_p = mnem_p;
29b0f896
AM		 3825 mnem_p++;
3826 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3827 {
29b0f896
AM		 3828 as_bad (_("no such instruction: `%s'"), token_start);
3829 return NULL;
3830 }
3831 l++;
3832 }
3833 if (!is_space_char (*l)
3834 && *l != END_OF_INSN
e44823cf
JB		 3835 && (intel_syntax
3836 || (*l != PREFIX_SEPARATOR
3837 && *l != ',')))
29b0f896
AM		 3838 {
3839 as_bad (_("invalid character %s in mnemonic"),
3840 output_invalid (*l));
3841 return NULL;
3842 }
3843 if (token_start == l)
3844 {
e44823cf 3845 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3846 as_bad (_("expecting prefix; got nothing"));
3847 else
3848 as_bad (_("expecting mnemonic; got nothing"));
3849 return NULL;
3850 }
45288df1 3851
29b0f896 3852 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3853 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3854
29b0f896
AM		 3855 if (*l != END_OF_INSN
3856 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3857 && current_templates
40fb9820 3858 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3859 {
c6fb90c8 3860 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3861 {
3862 as_bad ((flag_code != CODE_64BIT
3863 ? _("`%s' is only supported in 64-bit mode")
3864 : _("`%s' is not supported in 64-bit mode")),
3865 current_templates->start->name);
3866 return NULL;
3867 }
29b0f896
AM		 3868 /* If we are in 16-bit mode, do not allow addr16 or data16.
3869 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3870 if ((current_templates->start->opcode_modifier.size16
3871 || current_templates->start->opcode_modifier.size32)
29b0f896 3872 && flag_code != CODE_64BIT
40fb9820 3873 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3874 ^ (flag_code == CODE_16BIT)))
3875 {
3876 as_bad (_("redundant %s prefix"),
3877 current_templates->start->name);
3878 return NULL;
45288df1 3879 }
29b0f896
AM		 3880 /* Add prefix, checking for repeated prefixes. */
3881 switch (add_prefix (current_templates->start->base_opcode))
3882 {
c32fa91d 3883 case PREFIX_EXIST:
29b0f896 3884 return NULL;
c32fa91d 3885 case PREFIX_REP:
42164a71 3886 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3887 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3888 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3889 i.bnd_prefix = current_templates->start->name;
42164a71 3890 else
d5de92cf 3891 i.rep_prefix = current_templates->start->name;
29b0f896 3892 break;
c32fa91d
L		 3893 default:
3894 break;
29b0f896
AM		 3895 }
3896 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3897 token_start = ++l;
3898 }
3899 else
3900 break;
3901 }
45288df1 3902
30a55f88 3903 if (!current_templates)
b6169b20 3904 {
f8a5c266
L		 3905 /* Check if we should swap operand or force 32bit displacement in
3906 encoding. */
30a55f88
L		 3907 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3908 i.swap_operand = 1;
8d63c93e 3909 else if (mnem_p - 3 == dot_p
a501d77e
L		 3910 && dot_p[1] == 'd'
3911 && dot_p[2] == '8')
3912 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3913 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3914 && dot_p[1] == 'd'
3915 && dot_p[2] == '3'
3916 && dot_p[3] == '2')
a501d77e 3917 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3918 else
3919 goto check_suffix;
3920 mnem_p = dot_p;
3921 *dot_p = '\0';
d3ce72d0 3922 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3923 }
3924
29b0f896
AM		 3925 if (!current_templates)
3926 {
b6169b20 3927check_suffix:
29b0f896
AM		 3928 /* See if we can get a match by trimming off a suffix. */
3929 switch (mnem_p[-1])
3930 {
3931 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3932 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3933 i.suffix = SHORT_MNEM_SUFFIX;
3934 else
29b0f896
AM		 3935 case BYTE_MNEM_SUFFIX:
3936 case QWORD_MNEM_SUFFIX:
3937 i.suffix = mnem_p[-1];
3938 mnem_p[-1] = '\0';
d3ce72d0
NC		 3939 current_templates = (const templates *) hash_find (op_hash,
3940 mnemonic);
29b0f896
AM		 3941 break;
3942 case SHORT_MNEM_SUFFIX:
3943 case LONG_MNEM_SUFFIX:
3944 if (!intel_syntax)
3945 {
3946 i.suffix = mnem_p[-1];
3947 mnem_p[-1] = '\0';
d3ce72d0
NC		 3948 current_templates = (const templates *) hash_find (op_hash,
3949 mnemonic);
29b0f896
AM		 3950 }
3951 break;
252b5132 3952
29b0f896
AM		 3953 /* Intel Syntax. */
3954 case 'd':
3955 if (intel_syntax)
3956 {
9306ca4a 3957 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3958 i.suffix = SHORT_MNEM_SUFFIX;
3959 else
3960 i.suffix = LONG_MNEM_SUFFIX;
3961 mnem_p[-1] = '\0';
d3ce72d0
NC		 3962 current_templates = (const templates *) hash_find (op_hash,
3963 mnemonic);
29b0f896
AM		 3964 }
3965 break;
3966 }
3967 if (!current_templates)
3968 {
3969 as_bad (_("no such instruction: `%s'"), token_start);
3970 return NULL;
3971 }
3972 }
252b5132 3973
40fb9820
L		 3974 if (current_templates->start->opcode_modifier.jump
3975 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3976 {
3977 /* Check for a branch hint. We allow ",pt" and ",pn" for
3978 predict taken and predict not taken respectively.
3979 I'm not sure that branch hints actually do anything on loop
3980 and jcxz insns (JumpByte) for current Pentium4 chips. They
3981 may work in the future and it doesn't hurt to accept them
3982 now. */
3983 if (l[0] == ',' && l[1] == 'p')
3984 {
3985 if (l[2] == 't')
3986 {
3987 if (!add_prefix (DS_PREFIX_OPCODE))
3988 return NULL;
3989 l += 3;
3990 }
3991 else if (l[2] == 'n')
3992 {
3993 if (!add_prefix (CS_PREFIX_OPCODE))
3994 return NULL;
3995 l += 3;
3996 }
3997 }
3998 }
3999 /* Any other comma loses. */
4000 if (*l == ',')
4001 {
4002 as_bad (_("invalid character %s in mnemonic"),
4003 output_invalid (*l));
4004 return NULL;
4005 }
252b5132 4006
29b0f896 4007 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4008 supported = 0;
4009 for (t = current_templates->start; t < current_templates->end; ++t)
4010 {
c0f3af97
L		 4011 supported |= cpu_flags_match (t);
4012 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4013 goto skip;
5c6af06e 4014 }
3629bb00 4015
c0f3af97 4016 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4017 {
4018 as_bad (flag_code == CODE_64BIT
4019 ? _("`%s' is not supported in 64-bit mode")
4020 : _("`%s' is only supported in 64-bit mode"),
4021 current_templates->start->name);
4022 return NULL;
4023 }
c0f3af97 4024 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4025 {
3629bb00 4026 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4027 current_templates->start->name,
41aacd83 4028 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4029 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4030 return NULL;
29b0f896 4031 }
3629bb00
L		 4032
4033skip:
4034 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4035 && (flag_code != CODE_16BIT))
29b0f896
AM		 4036 {
4037 as_warn (_("use .code16 to ensure correct addressing mode"));
4038 }
252b5132 4039
29b0f896
AM		 4040 return l;
4041}
252b5132 4042
29b0f896 4043static char *
e3bb37b5 4044parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4045{
4046 char *token_start;
3138f287 4047
29b0f896
AM		 4048 /* 1 if operand is pending after ','. */
4049 unsigned int expecting_operand = 0;
252b5132 4050
29b0f896
AM		 4051 /* Non-zero if operand parens not balanced. */
4052 unsigned int paren_not_balanced;
4053
4054 while (*l != END_OF_INSN)
4055 {
4056 /* Skip optional white space before operand. */
4057 if (is_space_char (*l))
4058 ++l;
d02603dc 4059 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4060 {
4061 as_bad (_("invalid character %s before operand %d"),
4062 output_invalid (*l),
4063 i.operands + 1);
4064 return NULL;
4065 }
d02603dc 4066 token_start = l; /* After white space. */
29b0f896
AM		 4067 paren_not_balanced = 0;
4068 while (paren_not_balanced || *l != ',')
4069 {
4070 if (*l == END_OF_INSN)
4071 {
4072 if (paren_not_balanced)
4073 {
4074 if (!intel_syntax)
4075 as_bad (_("unbalanced parenthesis in operand %d."),
4076 i.operands + 1);
4077 else
4078 as_bad (_("unbalanced brackets in operand %d."),
4079 i.operands + 1);
4080 return NULL;
4081 }
4082 else
4083 break; /* we are done */
4084 }
d02603dc 4085 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4086 {
4087 as_bad (_("invalid character %s in operand %d"),
4088 output_invalid (*l),
4089 i.operands + 1);
4090 return NULL;
4091 }
4092 if (!intel_syntax)
4093 {
4094 if (*l == '(')
4095 ++paren_not_balanced;
4096 if (*l == ')')
4097 --paren_not_balanced;
4098 }
4099 else
4100 {
4101 if (*l == '[')
4102 ++paren_not_balanced;
4103 if (*l == ']')
4104 --paren_not_balanced;
4105 }
4106 l++;
4107 }
4108 if (l != token_start)
4109 { /* Yes, we've read in another operand. */
4110 unsigned int operand_ok;
4111 this_operand = i.operands++;
7d5e4556 4112 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4113 if (i.operands > MAX_OPERANDS)
4114 {
4115 as_bad (_("spurious operands; (%d operands/instruction max)"),
4116 MAX_OPERANDS);
4117 return NULL;
4118 }
4119 /* Now parse operand adding info to 'i' as we go along. */
4120 END_STRING_AND_SAVE (l);
4121
4122 if (intel_syntax)
4123 operand_ok =
4124 i386_intel_operand (token_start,
4125 intel_float_operand (mnemonic));
4126 else
a7619375 4127 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4128
4129 RESTORE_END_STRING (l);
4130 if (!operand_ok)
4131 return NULL;
4132 }
4133 else
4134 {
4135 if (expecting_operand)
4136 {
4137 expecting_operand_after_comma:
4138 as_bad (_("expecting operand after ','; got nothing"));
4139 return NULL;
4140 }
4141 if (*l == ',')
4142 {
4143 as_bad (_("expecting operand before ','; got nothing"));
4144 return NULL;
4145 }
4146 }
7f3f1ea2 4147
29b0f896
AM		 4148 /* Now *l must be either ',' or END_OF_INSN. */
4149 if (*l == ',')
4150 {
4151 if (*++l == END_OF_INSN)
4152 {
4153 /* Just skip it, if it's \n complain. */
4154 goto expecting_operand_after_comma;
4155 }
4156 expecting_operand = 1;
4157 }
4158 }
4159 return l;
4160}
7f3f1ea2 4161
050dfa73 4162static void
4d456e3d 4163swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4164{
4165 union i386_op temp_op;
40fb9820 4166 i386_operand_type temp_type;
050dfa73 4167 enum bfd_reloc_code_real temp_reloc;
4eed87de 4168
050dfa73
MM		 4169 temp_type = i.types[xchg2];
4170 i.types[xchg2] = i.types[xchg1];
4171 i.types[xchg1] = temp_type;
4172 temp_op = i.op[xchg2];
4173 i.op[xchg2] = i.op[xchg1];
4174 i.op[xchg1] = temp_op;
4175 temp_reloc = i.reloc[xchg2];
4176 i.reloc[xchg2] = i.reloc[xchg1];
4177 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4178
4179 if (i.mask)
4180 {
4181 if (i.mask->operand == xchg1)
4182 i.mask->operand = xchg2;
4183 else if (i.mask->operand == xchg2)
4184 i.mask->operand = xchg1;
4185 }
4186 if (i.broadcast)
4187 {
4188 if (i.broadcast->operand == xchg1)
4189 i.broadcast->operand = xchg2;
4190 else if (i.broadcast->operand == xchg2)
4191 i.broadcast->operand = xchg1;
4192 }
4193 if (i.rounding)
4194 {
4195 if (i.rounding->operand == xchg1)
4196 i.rounding->operand = xchg2;
4197 else if (i.rounding->operand == xchg2)
4198 i.rounding->operand = xchg1;
4199 }
050dfa73
MM		 4200}
4201
29b0f896 4202static void
e3bb37b5 4203swap_operands (void)
29b0f896 4204{
b7c61d9a 4205 switch (i.operands)
050dfa73 4206 {
c0f3af97 4207 case 5:
b7c61d9a 4208 case 4:
4d456e3d 4209 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4210 case 3:
4211 case 2:
4d456e3d 4212 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4213 break;
4214 default:
4215 abort ();
29b0f896 4216 }
29b0f896
AM		 4217
4218 if (i.mem_operands == 2)
4219 {
4220 const seg_entry *temp_seg;
4221 temp_seg = i.seg[0];
4222 i.seg[0] = i.seg[1];
4223 i.seg[1] = temp_seg;
4224 }
4225}
252b5132 4226
29b0f896
AM		 4227/* Try to ensure constant immediates are represented in the smallest
4228 opcode possible. */
4229static void
e3bb37b5 4230optimize_imm (void)
29b0f896
AM		 4231{
4232 char guess_suffix = 0;
4233 int op;
252b5132 4234
29b0f896
AM		 4235 if (i.suffix)
4236 guess_suffix = i.suffix;
4237 else if (i.reg_operands)
4238 {
4239 /* Figure out a suffix from the last register operand specified.
4240 We can't do this properly yet, ie. excluding InOutPortReg,
4241 but the following works for instructions with immediates.
4242 In any case, we can't set i.suffix yet. */
4243 for (op = i.operands; --op >= 0;)
40fb9820 4244 if (i.types[op].bitfield.reg8)
7ab9ffdd 4245 {
40fb9820
L		 4246 guess_suffix = BYTE_MNEM_SUFFIX;
4247 break;
4248 }
4249 else if (i.types[op].bitfield.reg16)
252b5132 4250 {
40fb9820
L		 4251 guess_suffix = WORD_MNEM_SUFFIX;
4252 break;
4253 }
4254 else if (i.types[op].bitfield.reg32)
4255 {
4256 guess_suffix = LONG_MNEM_SUFFIX;
4257 break;
4258 }
4259 else if (i.types[op].bitfield.reg64)
4260 {
4261 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4262 break;
252b5132 4263 }
29b0f896
AM		 4264 }
4265 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4266 guess_suffix = WORD_MNEM_SUFFIX;
4267
4268 for (op = i.operands; --op >= 0;)
40fb9820 4269 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4270 {
4271 switch (i.op[op].imms->X_op)
252b5132 4272 {
29b0f896
AM		 4273 case O_constant:
4274 /* If a suffix is given, this operand may be shortened. */
4275 switch (guess_suffix)
252b5132 4276 {
29b0f896 4277 case LONG_MNEM_SUFFIX:
40fb9820
L		 4278 i.types[op].bitfield.imm32 = 1;
4279 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4280 break;
4281 case WORD_MNEM_SUFFIX:
40fb9820
L		 4282 i.types[op].bitfield.imm16 = 1;
4283 i.types[op].bitfield.imm32 = 1;
4284 i.types[op].bitfield.imm32s = 1;
4285 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4286 break;
4287 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4288 i.types[op].bitfield.imm8 = 1;
4289 i.types[op].bitfield.imm8s = 1;
4290 i.types[op].bitfield.imm16 = 1;
4291 i.types[op].bitfield.imm32 = 1;
4292 i.types[op].bitfield.imm32s = 1;
4293 i.types[op].bitfield.imm64 = 1;
29b0f896 4294 break;
252b5132 4295 }
252b5132 4296
29b0f896
AM		 4297 /* If this operand is at most 16 bits, convert it
4298 to a signed 16 bit number before trying to see
4299 whether it will fit in an even smaller size.
4300 This allows a 16-bit operand such as $0xffe0 to
4301 be recognised as within Imm8S range. */
40fb9820 4302 if ((i.types[op].bitfield.imm16)
29b0f896 4303 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4304 {
29b0f896
AM		 4305 i.op[op].imms->X_add_number =
4306 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4307 }
a28def75
L		 4308#ifdef BFD64
4309 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4310 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4311 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4312 == 0))
4313 {
4314 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4315 ^ ((offsetT) 1 << 31))
4316 - ((offsetT) 1 << 31));
4317 }
a28def75 4318#endif
40fb9820 4319 i.types[op]
c6fb90c8
L		 4320 = operand_type_or (i.types[op],
4321 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4322
29b0f896
AM		 4323 /* We must avoid matching of Imm32 templates when 64bit
4324 only immediate is available. */
4325 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4326 i.types[op].bitfield.imm32 = 0;
29b0f896 4327 break;
252b5132 4328
29b0f896
AM		 4329 case O_absent:
4330 case O_register:
4331 abort ();
4332
4333 /* Symbols and expressions. */
4334 default:
9cd96992
JB		 4335 /* Convert symbolic operand to proper sizes for matching, but don't
4336 prevent matching a set of insns that only supports sizes other
4337 than those matching the insn suffix. */
4338 {
40fb9820 4339 i386_operand_type mask, allowed;
d3ce72d0 4340 const insn_template *t;
9cd96992 4341
0dfbf9d7
L		 4342 operand_type_set (&mask, 0);
4343 operand_type_set (&allowed, 0);
40fb9820 4344
4eed87de
AM		 4345 for (t = current_templates->start;
4346 t < current_templates->end;
4347 ++t)
c6fb90c8
L		 4348 allowed = operand_type_or (allowed,
4349 t->operand_types[op]);
9cd96992
JB		 4350 switch (guess_suffix)
4351 {
4352 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4353 mask.bitfield.imm64 = 1;
4354 mask.bitfield.imm32s = 1;
9cd96992
JB		 4355 break;
4356 case LONG_MNEM_SUFFIX:
40fb9820 4357 mask.bitfield.imm32 = 1;
9cd96992
JB		 4358 break;
4359 case WORD_MNEM_SUFFIX:
40fb9820 4360 mask.bitfield.imm16 = 1;
9cd96992
JB		 4361 break;
4362 case BYTE_MNEM_SUFFIX:
40fb9820 4363 mask.bitfield.imm8 = 1;
9cd96992
JB		 4364 break;
4365 default:
9cd96992
JB		 4366 break;
4367 }
c6fb90c8 4368 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4369 if (!operand_type_all_zero (&allowed))
c6fb90c8 4370 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4371 }
29b0f896 4372 break;
252b5132 4373 }
29b0f896
AM		 4374 }
4375}
47926f60 4376
29b0f896
AM		 4377/* Try to use the smallest displacement type too. */
4378static void
e3bb37b5 4379optimize_disp (void)
29b0f896
AM		 4380{
4381 int op;
3e73aa7c 4382
29b0f896 4383 for (op = i.operands; --op >= 0;)
40fb9820 4384 if (operand_type_check (i.types[op], disp))
252b5132 4385 {
b300c311 4386 if (i.op[op].disps->X_op == O_constant)
252b5132 4387 {
91d6fa6a 4388 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4389
40fb9820 4390 if (i.types[op].bitfield.disp16
91d6fa6a 4391 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4392 {
4393 /* If this operand is at most 16 bits, convert
4394 to a signed 16 bit number and don't use 64bit
4395 displacement. */
91d6fa6a 4396 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4397 i.types[op].bitfield.disp64 = 0;
b300c311 4398 }
a28def75
L		 4399#ifdef BFD64
4400 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4401 if (i.types[op].bitfield.disp32
91d6fa6a 4402 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4403 {
4404 /* If this operand is at most 32 bits, convert
4405 to a signed 32 bit number and don't use 64bit
4406 displacement. */
91d6fa6a
NC		 4407 op_disp &= (((offsetT) 2 << 31) - 1);
4408 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4409 i.types[op].bitfield.disp64 = 0;
b300c311 4410 }
a28def75 4411#endif
91d6fa6a 4412 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4413 {
40fb9820
L		 4414 i.types[op].bitfield.disp8 = 0;
4415 i.types[op].bitfield.disp16 = 0;
4416 i.types[op].bitfield.disp32 = 0;
4417 i.types[op].bitfield.disp32s = 0;
4418 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4419 i.op[op].disps = 0;
4420 i.disp_operands--;
4421 }
4422 else if (flag_code == CODE_64BIT)
4423 {
91d6fa6a 4424 if (fits_in_signed_long (op_disp))
28a9d8f5 4425 {
40fb9820
L		 4426 i.types[op].bitfield.disp64 = 0;
4427 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4428 }
0e1147d9 4429 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4430 && fits_in_unsigned_long (op_disp))
40fb9820 4431 i.types[op].bitfield.disp32 = 1;
b300c311 4432 }
40fb9820
L		 4433 if ((i.types[op].bitfield.disp32
4434 || i.types[op].bitfield.disp32s
4435 || i.types[op].bitfield.disp16)
91d6fa6a 4436 && fits_in_signed_byte (op_disp))
40fb9820 4437 i.types[op].bitfield.disp8 = 1;
252b5132 4438 }
67a4f2b7
AO		 4439 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4440 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4441 {
4442 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4443 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4444 i.types[op].bitfield.disp8 = 0;
4445 i.types[op].bitfield.disp16 = 0;
4446 i.types[op].bitfield.disp32 = 0;
4447 i.types[op].bitfield.disp32s = 0;
4448 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4449 }
4450 else
b300c311 4451 /* We only support 64bit displacement on constants. */
40fb9820 4452 i.types[op].bitfield.disp64 = 0;
252b5132 4453 }
29b0f896
AM		 4454}
4455
6c30d220
L		 4456/* Check if operands are valid for the instruction. */
4457
4458static int
4459check_VecOperands (const insn_template *t)
4460{
43234a1e
L		 4461 unsigned int op;
4462
6c30d220
L		 4463 /* Without VSIB byte, we can't have a vector register for index. */
4464 if (!t->opcode_modifier.vecsib
4465 && i.index_reg
4466 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4467 || i.index_reg->reg_type.bitfield.regymm
4468 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4469 {
4470 i.error = unsupported_vector_index_register;
4471 return 1;
4472 }
4473
ad8ecc81
MZ		 4474 /* Check if default mask is allowed. */
4475 if (t->opcode_modifier.nodefmask
4476 && (!i.mask || i.mask->mask->reg_num == 0))
4477 {
4478 i.error = no_default_mask;
4479 return 1;
4480 }
4481
7bab8ab5
JB		 4482 /* For VSIB byte, we need a vector register for index, and all vector
4483 registers must be distinct. */
4484 if (t->opcode_modifier.vecsib)
4485 {
4486 if (!i.index_reg
6c30d220
L		 4487 || !((t->opcode_modifier.vecsib == VecSIB128
4488 && i.index_reg->reg_type.bitfield.regxmm)
4489 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4490 && i.index_reg->reg_type.bitfield.regymm)
4491 || (t->opcode_modifier.vecsib == VecSIB512
4492 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4493 {
4494 i.error = invalid_vsib_address;
4495 return 1;
4496 }
4497
43234a1e
L		 4498 gas_assert (i.reg_operands == 2 || i.mask);
4499 if (i.reg_operands == 2 && !i.mask)
4500 {
4501 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4502 || i.types[0].bitfield.regymm);
43234a1e 4503 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4504 || i.types[2].bitfield.regymm);
43234a1e
L		 4505 if (operand_check == check_none)
4506 return 0;
4507 if (register_number (i.op[0].regs)
4508 != register_number (i.index_reg)
4509 && register_number (i.op[2].regs)
4510 != register_number (i.index_reg)
4511 && register_number (i.op[0].regs)
4512 != register_number (i.op[2].regs))
4513 return 0;
4514 if (operand_check == check_error)
4515 {
4516 i.error = invalid_vector_register_set;
4517 return 1;
4518 }
4519 as_warn (_("mask, index, and destination registers should be distinct"));
4520 }
8444f82a
MZ		 4521 else if (i.reg_operands == 1 && i.mask)
4522 {
4523 if ((i.types[1].bitfield.regymm
4524 || i.types[1].bitfield.regzmm)
4525 && (register_number (i.op[1].regs)
4526 == register_number (i.index_reg)))
4527 {
4528 if (operand_check == check_error)
4529 {
4530 i.error = invalid_vector_register_set;
4531 return 1;
4532 }
4533 if (operand_check != check_none)
4534 as_warn (_("index and destination registers should be distinct"));
4535 }
4536 }
43234a1e 4537 }
7bab8ab5 4538
43234a1e
L		 4539 /* Check if broadcast is supported by the instruction and is applied
4540 to the memory operand. */
4541 if (i.broadcast)
4542 {
4543 int broadcasted_opnd_size;
4544
4545 /* Check if specified broadcast is supported in this instruction,
4546 and it's applied to memory operand of DWORD or QWORD type,
4547 depending on VecESize. */
4548 if (i.broadcast->type != t->opcode_modifier.broadcast
4549 || !i.types[i.broadcast->operand].bitfield.mem
4550 || (t->opcode_modifier.vecesize == 0
4551 && !i.types[i.broadcast->operand].bitfield.dword
4552 && !i.types[i.broadcast->operand].bitfield.unspecified)
4553 || (t->opcode_modifier.vecesize == 1
4554 && !i.types[i.broadcast->operand].bitfield.qword
4555 && !i.types[i.broadcast->operand].bitfield.unspecified))
4556 goto bad_broadcast;
4557
4558 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4559 if (i.broadcast->type == BROADCAST_1TO16)
4560 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4561 else if (i.broadcast->type == BROADCAST_1TO8)
4562 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4563 else if (i.broadcast->type == BROADCAST_1TO4)
4564 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4565 else if (i.broadcast->type == BROADCAST_1TO2)
4566 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4567 else
4568 goto bad_broadcast;
4569
4570 if ((broadcasted_opnd_size == 256
4571 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4572 || (broadcasted_opnd_size == 512
4573 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4574 {
4575 bad_broadcast:
4576 i.error = unsupported_broadcast;
4577 return 1;
4578 }
4579 }
4580 /* If broadcast is supported in this instruction, we need to check if
4581 operand of one-element size isn't specified without broadcast. */
4582 else if (t->opcode_modifier.broadcast && i.mem_operands)
4583 {
4584 /* Find memory operand. */
4585 for (op = 0; op < i.operands; op++)
4586 if (operand_type_check (i.types[op], anymem))
4587 break;
4588 gas_assert (op < i.operands);
4589 /* Check size of the memory operand. */
4590 if ((t->opcode_modifier.vecesize == 0
4591 && i.types[op].bitfield.dword)
4592 || (t->opcode_modifier.vecesize == 1
4593 && i.types[op].bitfield.qword))
4594 {
4595 i.error = broadcast_needed;
4596 return 1;
4597 }
4598 }
4599
4600 /* Check if requested masking is supported. */
4601 if (i.mask
4602 && (!t->opcode_modifier.masking
4603 || (i.mask->zeroing
4604 && t->opcode_modifier.masking == MERGING_MASKING)))
4605 {
4606 i.error = unsupported_masking;
4607 return 1;
4608 }
4609
4610 /* Check if masking is applied to dest operand. */
4611 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4612 {
4613 i.error = mask_not_on_destination;
4614 return 1;
4615 }
4616
43234a1e
L		 4617 /* Check RC/SAE. */
4618 if (i.rounding)
4619 {
4620 if ((i.rounding->type != saeonly
4621 && !t->opcode_modifier.staticrounding)
4622 || (i.rounding->type == saeonly
4623 && (t->opcode_modifier.staticrounding
4624 || !t->opcode_modifier.sae)))
4625 {
4626 i.error = unsupported_rc_sae;
4627 return 1;
4628 }
4629 /* If the instruction has several immediate operands and one of
4630 them is rounding, the rounding operand should be the last
4631 immediate operand. */
4632 if (i.imm_operands > 1
4633 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4634 {
43234a1e 4635 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4636 return 1;
4637 }
6c30d220
L		 4638 }
4639
43234a1e
L		 4640 /* Check vector Disp8 operand. */
4641 if (t->opcode_modifier.disp8memshift)
4642 {
4643 if (i.broadcast)
4644 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4645 else
4646 i.memshift = t->opcode_modifier.disp8memshift;
4647
4648 for (op = 0; op < i.operands; op++)
4649 if (operand_type_check (i.types[op], disp)
4650 && i.op[op].disps->X_op == O_constant)
4651 {
4652 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4653 int vec_disp8_ok
4654 = (i.disp_encoding != disp_encoding_32bit
4655 && fits_in_vec_disp8 (value));
43234a1e
L		 4656 if (t->operand_types [op].bitfield.vec_disp8)
4657 {
4658 if (vec_disp8_ok)
4659 i.types[op].bitfield.vec_disp8 = 1;
4660 else
4661 {
4662 /* Vector insn can only have Vec_Disp8/Disp32 in
4663 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4664 mode. */
4665 i.types[op].bitfield.disp8 = 0;
4666 if (flag_code != CODE_16BIT)
4667 i.types[op].bitfield.disp16 = 0;
4668 }
4669 }
4670 else if (flag_code != CODE_16BIT)
4671 {
4672 /* One form of this instruction supports vector Disp8.
4673 Try vector Disp8 if we need to use Disp32. */
4674 if (vec_disp8_ok && !fits_in_signed_byte (value))
4675 {
4676 i.error = try_vector_disp8;
4677 return 1;
4678 }
4679 }
4680 }
4681 }
4682 else
4683 i.memshift = -1;
4684
6c30d220
L		 4685 return 0;
4686}
4687
43f3e2ee 4688/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4689 operand types. */
4690
4691static int
4692VEX_check_operands (const insn_template *t)
4693{
43234a1e
L		 4694 /* VREX is only valid with EVEX prefix. */
4695 if (i.need_vrex && !t->opcode_modifier.evex)
4696 {
4697 i.error = invalid_register_operand;
4698 return 1;
4699 }
4700
a683cc34
SP		 4701 if (!t->opcode_modifier.vex)
4702 return 0;
4703
4704 /* Only check VEX_Imm4, which must be the first operand. */
4705 if (t->operand_types[0].bitfield.vec_imm4)
4706 {
4707 if (i.op[0].imms->X_op != O_constant
4708 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4709 {
a65babc9 4710 i.error = bad_imm4;
891edac4
L		 4711 return 1;
4712 }
a683cc34
SP		 4713
4714 /* Turn off Imm8 so that update_imm won't complain. */
4715 i.types[0] = vec_imm4;
4716 }
4717
4718 return 0;
4719}
4720
d3ce72d0 4721static const insn_template *
e3bb37b5 4722match_template (void)
29b0f896
AM		 4723{
4724 /* Points to template once we've found it. */
d3ce72d0 4725 const insn_template *t;
40fb9820 4726 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4727 i386_operand_type overlap4;
29b0f896 4728 unsigned int found_reverse_match;
40fb9820
L		 4729 i386_opcode_modifier suffix_check;
4730 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4731 int addr_prefix_disp;
a5c311ca 4732 unsigned int j;
3629bb00 4733 unsigned int found_cpu_match;
45664ddb 4734 unsigned int check_register;
5614d22c 4735 enum i386_error specific_error = 0;
29b0f896 4736
c0f3af97
L		 4737#if MAX_OPERANDS != 5
4738# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4739#endif
4740
29b0f896 4741 found_reverse_match = 0;
539e75ad 4742 addr_prefix_disp = -1;
40fb9820
L		 4743
4744 memset (&suffix_check, 0, sizeof (suffix_check));
4745 if (i.suffix == BYTE_MNEM_SUFFIX)
4746 suffix_check.no_bsuf = 1;
4747 else if (i.suffix == WORD_MNEM_SUFFIX)
4748 suffix_check.no_wsuf = 1;
4749 else if (i.suffix == SHORT_MNEM_SUFFIX)
4750 suffix_check.no_ssuf = 1;
4751 else if (i.suffix == LONG_MNEM_SUFFIX)
4752 suffix_check.no_lsuf = 1;
4753 else if (i.suffix == QWORD_MNEM_SUFFIX)
4754 suffix_check.no_qsuf = 1;
4755 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4756 suffix_check.no_ldsuf = 1;
29b0f896 4757
01559ecc
L		 4758 /* Must have right number of operands. */
4759 i.error = number_of_operands_mismatch;
4760
45aa61fe 4761 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4762 {
539e75ad
L		 4763 addr_prefix_disp = -1;
4764
29b0f896
AM		 4765 if (i.operands != t->operands)
4766 continue;
4767
50aecf8c 4768 /* Check processor support. */
a65babc9 4769 i.error = unsupported;
c0f3af97
L		 4770 found_cpu_match = (cpu_flags_match (t)
4771 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4772 if (!found_cpu_match)
4773 continue;
4774
e1d4d893 4775 /* Check old gcc support. */
a65babc9 4776 i.error = old_gcc_only;
e1d4d893
L		 4777 if (!old_gcc && t->opcode_modifier.oldgcc)
4778 continue;
4779
4780 /* Check AT&T mnemonic. */
a65babc9 4781 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4782 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4783 continue;
4784
e92bae62 4785 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4786 i.error = unsupported_syntax;
5c07affc 4787 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4788 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4789 || (intel64 && t->opcode_modifier.amd64)
4790 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4791 continue;
4792
20592a94 4793 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4794 i.error = invalid_instruction_suffix;
567e4e96
L		 4795 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4796 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4797 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4798 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4799 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4800 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4801 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4802 continue;
4803
5c07affc 4804 if (!operand_size_match (t))
7d5e4556 4805 continue;
539e75ad 4806
5c07affc
L		 4807 for (j = 0; j < MAX_OPERANDS; j++)
4808 operand_types[j] = t->operand_types[j];
4809
45aa61fe
AM		 4810 /* In general, don't allow 64-bit operands in 32-bit mode. */
4811 if (i.suffix == QWORD_MNEM_SUFFIX
4812 && flag_code != CODE_64BIT
4813 && (intel_syntax
40fb9820 4814 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4815 && !intel_float_operand (t->name))
4816 : intel_float_operand (t->name) != 2)
40fb9820 4817 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4818 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4819 && !operand_types[0].bitfield.regymm
4820 && !operand_types[0].bitfield.regzmm)
40fb9820 4821 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4822 && operand_types[t->operands > 1].bitfield.regxmm
4823 && operand_types[t->operands > 1].bitfield.regymm
4824 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4825 && (t->base_opcode != 0x0fc7
4826 || t->extension_opcode != 1 /* cmpxchg8b */))
4827 continue;
4828
192dc9c6
JB		 4829 /* In general, don't allow 32-bit operands on pre-386. */
4830 else if (i.suffix == LONG_MNEM_SUFFIX
4831 && !cpu_arch_flags.bitfield.cpui386
4832 && (intel_syntax
4833 ? (!t->opcode_modifier.ignoresize
4834 && !intel_float_operand (t->name))
4835 : intel_float_operand (t->name) != 2)
4836 && ((!operand_types[0].bitfield.regmmx
4837 && !operand_types[0].bitfield.regxmm)
4838 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4839 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4840 continue;
4841
29b0f896 4842 /* Do not verify operands when there are none. */
50aecf8c 4843 else
29b0f896 4844 {
c6fb90c8 4845 if (!t->operands)
2dbab7d5
L		 4846 /* We've found a match; break out of loop. */
4847 break;
29b0f896 4848 }
252b5132 4849
539e75ad
L		 4850 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4851 into Disp32/Disp16/Disp32 operand. */
4852 if (i.prefix[ADDR_PREFIX] != 0)
4853 {
40fb9820 4854 /* There should be only one Disp operand. */
539e75ad
L		 4855 switch (flag_code)
4856 {
4857 case CODE_16BIT:
40fb9820
L		 4858 for (j = 0; j < MAX_OPERANDS; j++)
4859 {
4860 if (operand_types[j].bitfield.disp16)
4861 {
4862 addr_prefix_disp = j;
4863 operand_types[j].bitfield.disp32 = 1;
4864 operand_types[j].bitfield.disp16 = 0;
4865 break;
4866 }
4867 }
539e75ad
L		 4868 break;
4869 case CODE_32BIT:
40fb9820
L		 4870 for (j = 0; j < MAX_OPERANDS; j++)
4871 {
4872 if (operand_types[j].bitfield.disp32)
4873 {
4874 addr_prefix_disp = j;
4875 operand_types[j].bitfield.disp32 = 0;
4876 operand_types[j].bitfield.disp16 = 1;
4877 break;
4878 }
4879 }
539e75ad
L		 4880 break;
4881 case CODE_64BIT:
40fb9820
L		 4882 for (j = 0; j < MAX_OPERANDS; j++)
4883 {
4884 if (operand_types[j].bitfield.disp64)
4885 {
4886 addr_prefix_disp = j;
4887 operand_types[j].bitfield.disp64 = 0;
4888 operand_types[j].bitfield.disp32 = 1;
4889 break;
4890 }
4891 }
539e75ad
L		 4892 break;
4893 }
539e75ad
L		 4894 }
4895
02a86693
L		 4896 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4897 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4898 continue;
4899
56ffb741
L		 4900 /* We check register size if needed. */
4901 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4902 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4903 switch (t->operands)
4904 {
4905 case 1:
40fb9820 4906 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4907 continue;
4908 break;
4909 case 2:
8b38ad71
L		 4910 /* xchg %eax, %eax is a special case. It is an aliase for nop
4911 only in 32bit mode and we can use opcode 0x90. In 64bit
4912 mode, we can't use 0x90 for xchg %eax, %eax since it should
4913 zero-extend %eax to %rax. */
4914 if (flag_code == CODE_64BIT
4915 && t->base_opcode == 0x90
0dfbf9d7
L		 4916 && operand_type_equal (&i.types [0], &acc32)
4917 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4918 continue;
b6169b20
L		 4919 if (i.swap_operand)
4920 {
4921 /* If we swap operand in encoding, we either match
4922 the next one or reverse direction of operands. */
4923 if (t->opcode_modifier.s)
4924 continue;
4925 else if (t->opcode_modifier.d)
4926 goto check_reverse;
4927 }
4928
29b0f896 4929 case 3:
fa99fab2
L		 4930 /* If we swap operand in encoding, we match the next one. */
4931 if (i.swap_operand && t->opcode_modifier.s)
4932 continue;
f48ff2ae 4933 case 4:
c0f3af97 4934 case 5:
c6fb90c8 4935 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4936 if (!operand_type_match (overlap0, i.types[0])
4937 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4938 || (check_register
4939 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4940 operand_types[0],
4941 overlap1, i.types[1],
4942 operand_types[1])))
29b0f896
AM		 4943 {
4944 /* Check if other direction is valid ... */
40fb9820 4945 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4946 continue;
4947
b6169b20 4948check_reverse:
29b0f896 4949 /* Try reversing direction of operands. */
c6fb90c8
L		 4950 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4951 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4952 if (!operand_type_match (overlap0, i.types[0])
4953 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4954 || (check_register
4955 && !operand_type_register_match (overlap0,
4956 i.types[0],
4957 operand_types[1],
4958 overlap1,
4959 i.types[1],
4960 operand_types[0])))
29b0f896
AM		 4961 {
4962 /* Does not match either direction. */
4963 continue;
4964 }
4965 /* found_reverse_match holds which of D or FloatDR
4966 we've found. */
40fb9820 4967 if (t->opcode_modifier.d)
8a2ed489 4968 found_reverse_match = Opcode_D;
40fb9820 4969 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4970 found_reverse_match = Opcode_FloatD;
4971 else
4972 found_reverse_match = 0;
40fb9820 4973 if (t->opcode_modifier.floatr)
8a2ed489 4974 found_reverse_match |= Opcode_FloatR;
29b0f896 4975 }
f48ff2ae 4976 else
29b0f896 4977 {
f48ff2ae 4978 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4979 switch (t->operands)
4980 {
c0f3af97
L		 4981 case 5:
4982 overlap4 = operand_type_and (i.types[4],
4983 operand_types[4]);
d1cbb4db 4984 case 4:
c6fb90c8
L		 4985 overlap3 = operand_type_and (i.types[3],
4986 operand_types[3]);
d1cbb4db 4987 case 3:
c6fb90c8
L		 4988 overlap2 = operand_type_and (i.types[2],
4989 operand_types[2]);
d1cbb4db
L		 4990 break;
4991 }
29b0f896 4992
f48ff2ae
L		 4993 switch (t->operands)
4994 {
c0f3af97
L		 4995 case 5:
4996 if (!operand_type_match (overlap4, i.types[4])
4997 || !operand_type_register_match (overlap3,
4998 i.types[3],
4999 operand_types[3],
5000 overlap4,
5001 i.types[4],
5002 operand_types[4]))
5003 continue;
f48ff2ae 5004 case 4:
40fb9820 5005 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5006 || (check_register
5007 && !operand_type_register_match (overlap2,
5008 i.types[2],
5009 operand_types[2],
5010 overlap3,
5011 i.types[3],
5012 operand_types[3])))
f48ff2ae
L		 5013 continue;
5014 case 3:
5015 /* Here we make use of the fact that there are no
5016 reverse match 3 operand instructions, and all 3
5017 operand instructions only need to be checked for
5018 register consistency between operands 2 and 3. */
40fb9820 5019 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5020 || (check_register
5021 && !operand_type_register_match (overlap1,
5022 i.types[1],
5023 operand_types[1],
5024 overlap2,
5025 i.types[2],
5026 operand_types[2])))
f48ff2ae
L		 5027 continue;
5028 break;
5029 }
29b0f896 5030 }
f48ff2ae 5031 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5032 slip through to break. */
5033 }
3629bb00 5034 if (!found_cpu_match)
29b0f896
AM		 5035 {
5036 found_reverse_match = 0;
5037 continue;
5038 }
c0f3af97 5039
5614d22c
JB		 5040 /* Check if vector and VEX operands are valid. */
5041 if (check_VecOperands (t) || VEX_check_operands (t))
5042 {
5043 specific_error = i.error;
5044 continue;
5045 }
a683cc34 5046
29b0f896
AM		 5047 /* We've found a match; break out of loop. */
5048 break;
5049 }
5050
5051 if (t == current_templates->end)
5052 {
5053 /* We found no match. */
a65babc9 5054 const char *err_msg;
5614d22c 5055 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5056 {
5057 default:
5058 abort ();
86e026a4 5059 case operand_size_mismatch:
a65babc9
L		 5060 err_msg = _("operand size mismatch");
5061 break;
5062 case operand_type_mismatch:
5063 err_msg = _("operand type mismatch");
5064 break;
5065 case register_type_mismatch:
5066 err_msg = _("register type mismatch");
5067 break;
5068 case number_of_operands_mismatch:
5069 err_msg = _("number of operands mismatch");
5070 break;
5071 case invalid_instruction_suffix:
5072 err_msg = _("invalid instruction suffix");
5073 break;
5074 case bad_imm4:
4a2608e3 5075 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5076 break;
5077 case old_gcc_only:
5078 err_msg = _("only supported with old gcc");
5079 break;
5080 case unsupported_with_intel_mnemonic:
5081 err_msg = _("unsupported with Intel mnemonic");
5082 break;
5083 case unsupported_syntax:
5084 err_msg = _("unsupported syntax");
5085 break;
5086 case unsupported:
35262a23 5087 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5088 current_templates->start->name);
5089 return NULL;
6c30d220
L		 5090 case invalid_vsib_address:
5091 err_msg = _("invalid VSIB address");
5092 break;
7bab8ab5
JB		 5093 case invalid_vector_register_set:
5094 err_msg = _("mask, index, and destination registers must be distinct");
5095 break;
6c30d220
L		 5096 case unsupported_vector_index_register:
5097 err_msg = _("unsupported vector index register");
5098 break;
43234a1e
L		 5099 case unsupported_broadcast:
5100 err_msg = _("unsupported broadcast");
5101 break;
5102 case broadcast_not_on_src_operand:
5103 err_msg = _("broadcast not on source memory operand");
5104 break;
5105 case broadcast_needed:
5106 err_msg = _("broadcast is needed for operand of such type");
5107 break;
5108 case unsupported_masking:
5109 err_msg = _("unsupported masking");
5110 break;
5111 case mask_not_on_destination:
5112 err_msg = _("mask not on destination operand");
5113 break;
5114 case no_default_mask:
5115 err_msg = _("default mask isn't allowed");
5116 break;
5117 case unsupported_rc_sae:
5118 err_msg = _("unsupported static rounding/sae");
5119 break;
5120 case rc_sae_operand_not_last_imm:
5121 if (intel_syntax)
5122 err_msg = _("RC/SAE operand must precede immediate operands");
5123 else
5124 err_msg = _("RC/SAE operand must follow immediate operands");
5125 break;
5126 case invalid_register_operand:
5127 err_msg = _("invalid register operand");
5128 break;
a65babc9
L		 5129 }
5130 as_bad (_("%s for `%s'"), err_msg,
891edac4 5131 current_templates->start->name);
fa99fab2 5132 return NULL;
29b0f896 5133 }
252b5132 5134
29b0f896
AM		 5135 if (!quiet_warnings)
5136 {
5137 if (!intel_syntax
40fb9820
L		 5138 && (i.types[0].bitfield.jumpabsolute
5139 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5140 {
5141 as_warn (_("indirect %s without `*'"), t->name);
5142 }
5143
40fb9820
L		 5144 if (t->opcode_modifier.isprefix
5145 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5146 {
5147 /* Warn them that a data or address size prefix doesn't
5148 affect assembly of the next line of code. */
5149 as_warn (_("stand-alone `%s' prefix"), t->name);
5150 }
5151 }
5152
5153 /* Copy the template we found. */
5154 i.tm = *t;
539e75ad
L		 5155
5156 if (addr_prefix_disp != -1)
5157 i.tm.operand_types[addr_prefix_disp]
5158 = operand_types[addr_prefix_disp];
5159
29b0f896
AM		 5160 if (found_reverse_match)
5161 {
5162 /* If we found a reverse match we must alter the opcode
5163 direction bit. found_reverse_match holds bits to change
5164 (different for int & float insns). */
5165
5166 i.tm.base_opcode ^= found_reverse_match;
5167
539e75ad
L		 5168 i.tm.operand_types[0] = operand_types[1];
5169 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5170 }
5171
fa99fab2 5172 return t;
29b0f896
AM		 5173}
5174
5175static int
e3bb37b5 5176check_string (void)
29b0f896 5177{
40fb9820
L		 5178 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5179 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5180 {
5181 if (i.seg[0] != NULL && i.seg[0] != &es)
5182 {
a87af027 5183 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5184 i.tm.name,
a87af027
JB		 5185 mem_op + 1,
5186 register_prefix);
29b0f896
AM		 5187 return 0;
5188 }
5189 /* There's only ever one segment override allowed per instruction.
5190 This instruction possibly has a legal segment override on the
5191 second operand, so copy the segment to where non-string
5192 instructions store it, allowing common code. */
5193 i.seg[0] = i.seg[1];
5194 }
40fb9820 5195 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5196 {
5197 if (i.seg[1] != NULL && i.seg[1] != &es)
5198 {
a87af027 5199 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5200 i.tm.name,
a87af027
JB		 5201 mem_op + 2,
5202 register_prefix);
29b0f896
AM		 5203 return 0;
5204 }
5205 }
5206 return 1;
5207}
5208
5209static int
543613e9 5210process_suffix (void)
29b0f896
AM		 5211{
5212 /* If matched instruction specifies an explicit instruction mnemonic
5213 suffix, use it. */
40fb9820
L		 5214 if (i.tm.opcode_modifier.size16)
5215 i.suffix = WORD_MNEM_SUFFIX;
5216 else if (i.tm.opcode_modifier.size32)
5217 i.suffix = LONG_MNEM_SUFFIX;
5218 else if (i.tm.opcode_modifier.size64)
5219 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5220 else if (i.reg_operands)
5221 {
5222 /* If there's no instruction mnemonic suffix we try to invent one
5223 based on register operands. */
5224 if (!i.suffix)
5225 {
5226 /* We take i.suffix from the last register operand specified,
5227 Destination register type is more significant than source
381d071f
L		 5228 register type. crc32 in SSE4.2 prefers source register
5229 type. */
5230 if (i.tm.base_opcode == 0xf20f38f1)
5231 {
40fb9820
L		 5232 if (i.types[0].bitfield.reg16)
5233 i.suffix = WORD_MNEM_SUFFIX;
5234 else if (i.types[0].bitfield.reg32)
5235 i.suffix = LONG_MNEM_SUFFIX;
5236 else if (i.types[0].bitfield.reg64)
5237 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5238 }
9344ff29 5239 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5240 {
40fb9820 5241 if (i.types[0].bitfield.reg8)
20592a94
L		 5242 i.suffix = BYTE_MNEM_SUFFIX;
5243 }
381d071f
L		 5244
5245 if (!i.suffix)
5246 {
5247 int op;
5248
20592a94
L		 5249 if (i.tm.base_opcode == 0xf20f38f1
5250 || i.tm.base_opcode == 0xf20f38f0)
5251 {
5252 /* We have to know the operand size for crc32. */
5253 as_bad (_("ambiguous memory operand size for `%s`"),
5254 i.tm.name);
5255 return 0;
5256 }
5257
381d071f 5258 for (op = i.operands; --op >= 0;)
40fb9820 5259 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5260 {
40fb9820
L		 5261 if (i.types[op].bitfield.reg8)
5262 {
5263 i.suffix = BYTE_MNEM_SUFFIX;
5264 break;
5265 }
5266 else if (i.types[op].bitfield.reg16)
5267 {
5268 i.suffix = WORD_MNEM_SUFFIX;
5269 break;
5270 }
5271 else if (i.types[op].bitfield.reg32)
5272 {
5273 i.suffix = LONG_MNEM_SUFFIX;
5274 break;
5275 }
5276 else if (i.types[op].bitfield.reg64)
5277 {
5278 i.suffix = QWORD_MNEM_SUFFIX;
5279 break;
5280 }
381d071f
L		 5281 }
5282 }
29b0f896
AM		 5283 }
5284 else if (i.suffix == BYTE_MNEM_SUFFIX)
5285 {
2eb952a4
L		 5286 if (intel_syntax
5287 && i.tm.opcode_modifier.ignoresize
5288 && i.tm.opcode_modifier.no_bsuf)
5289 i.suffix = 0;
5290 else if (!check_byte_reg ())
29b0f896
AM		 5291 return 0;
5292 }
5293 else if (i.suffix == LONG_MNEM_SUFFIX)
5294 {
2eb952a4
L		 5295 if (intel_syntax
5296 && i.tm.opcode_modifier.ignoresize
5297 && i.tm.opcode_modifier.no_lsuf)
5298 i.suffix = 0;
5299 else if (!check_long_reg ())
29b0f896
AM		 5300 return 0;
5301 }
5302 else if (i.suffix == QWORD_MNEM_SUFFIX)
5303 {
955e1e6a
L		 5304 if (intel_syntax
5305 && i.tm.opcode_modifier.ignoresize
5306 && i.tm.opcode_modifier.no_qsuf)
5307 i.suffix = 0;
5308 else if (!check_qword_reg ())
29b0f896
AM		 5309 return 0;
5310 }
5311 else if (i.suffix == WORD_MNEM_SUFFIX)
5312 {
2eb952a4
L		 5313 if (intel_syntax
5314 && i.tm.opcode_modifier.ignoresize
5315 && i.tm.opcode_modifier.no_wsuf)
5316 i.suffix = 0;
5317 else if (!check_word_reg ())
29b0f896
AM		 5318 return 0;
5319 }
c0f3af97 5320 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5321 || i.suffix == YMMWORD_MNEM_SUFFIX
5322 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5323 {
43234a1e 5324 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5325 should check if it is a valid suffix. */
5326 }
40fb9820 5327 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5328 /* Do nothing if the instruction is going to ignore the prefix. */
5329 ;
5330 else
5331 abort ();
5332 }
40fb9820 5333 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5334 && !i.suffix
5335 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5336 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5337 {
5338 i.suffix = stackop_size;
5339 }
9306ca4a
JB		 5340 else if (intel_syntax
5341 && !i.suffix
40fb9820
L		 5342 && (i.tm.operand_types[0].bitfield.jumpabsolute
5343 || i.tm.opcode_modifier.jumpbyte
5344 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5345 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5346 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5347 {
5348 switch (flag_code)
5349 {
5350 case CODE_64BIT:
40fb9820 5351 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5352 {
5353 i.suffix = QWORD_MNEM_SUFFIX;
5354 break;
5355 }
5356 case CODE_32BIT:
40fb9820 5357 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5358 i.suffix = LONG_MNEM_SUFFIX;
5359 break;
5360 case CODE_16BIT:
40fb9820 5361 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5362 i.suffix = WORD_MNEM_SUFFIX;
5363 break;
5364 }
5365 }
252b5132 5366
9306ca4a 5367 if (!i.suffix)
29b0f896 5368 {
9306ca4a
JB		 5369 if (!intel_syntax)
5370 {
40fb9820 5371 if (i.tm.opcode_modifier.w)
9306ca4a 5372 {
4eed87de
AM		 5373 as_bad (_("no instruction mnemonic suffix given and "
5374 "no register operands; can't size instruction"));
9306ca4a
JB		 5375 return 0;
5376 }
5377 }
5378 else
5379 {
40fb9820 5380 unsigned int suffixes;
7ab9ffdd 5381
40fb9820
L		 5382 suffixes = !i.tm.opcode_modifier.no_bsuf;
5383 if (!i.tm.opcode_modifier.no_wsuf)
5384 suffixes |= 1 << 1;
5385 if (!i.tm.opcode_modifier.no_lsuf)
5386 suffixes |= 1 << 2;
fc4adea1 5387 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5388 suffixes |= 1 << 3;
5389 if (!i.tm.opcode_modifier.no_ssuf)
5390 suffixes |= 1 << 4;
5391 if (!i.tm.opcode_modifier.no_qsuf)
5392 suffixes |= 1 << 5;
5393
5394 /* There are more than suffix matches. */
5395 if (i.tm.opcode_modifier.w
9306ca4a 5396 || ((suffixes & (suffixes - 1))
40fb9820
L		 5397 && !i.tm.opcode_modifier.defaultsize
5398 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5399 {
5400 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5401 return 0;
5402 }
5403 }
29b0f896 5404 }
252b5132 5405
9306ca4a
JB		 5406 /* Change the opcode based on the operand size given by i.suffix;
5407 We don't need to change things for byte insns. */
5408
582d5edd
L		 5409 if (i.suffix
5410 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5411 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5412 && i.suffix != YMMWORD_MNEM_SUFFIX
5413 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5414 {
5415 /* It's not a byte, select word/dword operation. */
40fb9820 5416 if (i.tm.opcode_modifier.w)
29b0f896 5417 {
40fb9820 5418 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5419 i.tm.base_opcode |= 8;
5420 else
5421 i.tm.base_opcode |= 1;
5422 }
0f3f3d8b 5423
29b0f896
AM		 5424 /* Now select between word & dword operations via the operand
5425 size prefix, except for instructions that will ignore this
5426 prefix anyway. */
ca61edf2 5427 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5428 {
ca61edf2
L		 5429 /* The address size override prefix changes the size of the
5430 first operand. */
40fb9820
L		 5431 if ((flag_code == CODE_32BIT
5432 && i.op->regs[0].reg_type.bitfield.reg16)
5433 || (flag_code != CODE_32BIT
5434 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5435 if (!add_prefix (ADDR_PREFIX_OPCODE))
5436 return 0;
5437 }
5438 else if (i.suffix != QWORD_MNEM_SUFFIX
5439 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5440 && !i.tm.opcode_modifier.ignoresize
5441 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5442 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5443 || (flag_code == CODE_64BIT
40fb9820 5444 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5445 {
5446 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5447
40fb9820 5448 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5449 prefix = ADDR_PREFIX_OPCODE;
252b5132 5450
29b0f896
AM		 5451 if (!add_prefix (prefix))
5452 return 0;
24eab124 5453 }
252b5132 5454
29b0f896
AM		 5455 /* Set mode64 for an operand. */
5456 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5457 && flag_code == CODE_64BIT
40fb9820 5458 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5459 {
5460 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5461 need rex64. cmpxchg8b is also a special case. */
5462 if (! (i.operands == 2
5463 && i.tm.base_opcode == 0x90
5464 && i.tm.extension_opcode == None
0dfbf9d7
L		 5465 && operand_type_equal (&i.types [0], &acc64)
5466 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5467 && ! (i.operands == 1
5468 && i.tm.base_opcode == 0xfc7
5469 && i.tm.extension_opcode == 1
40fb9820
L		 5470 && !operand_type_check (i.types [0], reg)
5471 && operand_type_check (i.types [0], anymem)))
f6bee062 5472 i.rex |= REX_W;
46e883c5 5473 }
3e73aa7c 5474
29b0f896
AM		 5475 /* Size floating point instruction. */
5476 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5477 if (i.tm.opcode_modifier.floatmf)
543613e9 5478 i.tm.base_opcode ^= 4;
29b0f896 5479 }
7ecd2f8b 5480
29b0f896
AM		 5481 return 1;
5482}
3e73aa7c 5483
29b0f896 5484static int
543613e9 5485check_byte_reg (void)
29b0f896
AM		 5486{
5487 int op;
543613e9 5488
29b0f896
AM		 5489 for (op = i.operands; --op >= 0;)
5490 {
5491 /* If this is an eight bit register, it's OK. If it's the 16 or
5492 32 bit version of an eight bit register, we will just use the
5493 low portion, and that's OK too. */
40fb9820 5494 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5495 continue;
5496
5a819eb9
JB		 5497 /* I/O port address operands are OK too. */
5498 if (i.tm.operand_types[op].bitfield.inoutportreg)
5499 continue;
5500
9344ff29
L		 5501 /* crc32 doesn't generate this warning. */
5502 if (i.tm.base_opcode == 0xf20f38f0)
5503 continue;
5504
40fb9820
L		 5505 if ((i.types[op].bitfield.reg16
5506 || i.types[op].bitfield.reg32
5507 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5508 && i.op[op].regs->reg_num < 4
5509 /* Prohibit these changes in 64bit mode, since the lowering
5510 would be more complicated. */
5511 && flag_code != CODE_64BIT)
29b0f896 5512 {
29b0f896 5513#if REGISTER_WARNINGS
5a819eb9 5514 if (!quiet_warnings)
a540244d
L		 5515 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5516 register_prefix,
40fb9820 5517 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5518 ? REGNAM_AL - REGNAM_AX
5519 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5520 register_prefix,
29b0f896
AM		 5521 i.op[op].regs->reg_name,
5522 i.suffix);
5523#endif
5524 continue;
5525 }
5526 /* Any other register is bad. */
40fb9820
L		 5527 if (i.types[op].bitfield.reg16
5528 || i.types[op].bitfield.reg32
5529 || i.types[op].bitfield.reg64
5530 || i.types[op].bitfield.regmmx
5531 || i.types[op].bitfield.regxmm
c0f3af97 5532 || i.types[op].bitfield.regymm
43234a1e 5533 || i.types[op].bitfield.regzmm
40fb9820
L		 5534 || i.types[op].bitfield.sreg2
5535 || i.types[op].bitfield.sreg3
5536 || i.types[op].bitfield.control
5537 || i.types[op].bitfield.debug
5538 || i.types[op].bitfield.test
5539 || i.types[op].bitfield.floatreg
5540 || i.types[op].bitfield.floatacc)
29b0f896 5541 {
a540244d
L		 5542 as_bad (_("`%s%s' not allowed with `%s%c'"),
5543 register_prefix,
29b0f896
AM		 5544 i.op[op].regs->reg_name,
5545 i.tm.name,
5546 i.suffix);
5547 return 0;
5548 }
5549 }
5550 return 1;
5551}
5552
5553static int
e3bb37b5 5554check_long_reg (void)
29b0f896
AM		 5555{
5556 int op;
5557
5558 for (op = i.operands; --op >= 0;)
5559 /* Reject eight bit registers, except where the template requires
5560 them. (eg. movzb) */
40fb9820
L		 5561 if (i.types[op].bitfield.reg8
5562 && (i.tm.operand_types[op].bitfield.reg16
5563 || i.tm.operand_types[op].bitfield.reg32
5564 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5565 {
a540244d
L		 5566 as_bad (_("`%s%s' not allowed with `%s%c'"),
5567 register_prefix,
29b0f896
AM		 5568 i.op[op].regs->reg_name,
5569 i.tm.name,
5570 i.suffix);
5571 return 0;
5572 }
e4630f71 5573 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5574 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5575 && i.types[op].bitfield.reg16
5576 && (i.tm.operand_types[op].bitfield.reg32
5577 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5578 {
5579 /* Prohibit these changes in the 64bit mode, since the
5580 lowering is more complicated. */
5581 if (flag_code == CODE_64BIT)
252b5132 5582 {
2b5d6a91 5583 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5584 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5585 i.suffix);
5586 return 0;
252b5132 5587 }
29b0f896 5588#if REGISTER_WARNINGS
cecf1424
JB		 5589 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5590 register_prefix,
5591 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5592 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5593#endif
252b5132 5594 }
e4630f71 5595 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5596 else if (i.types[op].bitfield.reg64
5597 && (i.tm.operand_types[op].bitfield.reg32
5598 || i.tm.operand_types[op].bitfield.acc))
252b5132 5599 {
34828aad 5600 if (intel_syntax
ca61edf2 5601 && i.tm.opcode_modifier.toqword
40fb9820 5602 && !i.types[0].bitfield.regxmm)
34828aad 5603 {
ca61edf2 5604 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5605 i.suffix = QWORD_MNEM_SUFFIX;
5606 }
5607 else
5608 {
2b5d6a91 5609 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5610 register_prefix, i.op[op].regs->reg_name,
5611 i.suffix);
5612 return 0;
5613 }
29b0f896
AM		 5614 }
5615 return 1;
5616}
252b5132 5617
29b0f896 5618static int
e3bb37b5 5619check_qword_reg (void)
29b0f896
AM		 5620{
5621 int op;
252b5132 5622
29b0f896
AM		 5623 for (op = i.operands; --op >= 0; )
5624 /* Reject eight bit registers, except where the template requires
5625 them. (eg. movzb) */
40fb9820
L		 5626 if (i.types[op].bitfield.reg8
5627 && (i.tm.operand_types[op].bitfield.reg16
5628 || i.tm.operand_types[op].bitfield.reg32
5629 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5630 {
a540244d
L		 5631 as_bad (_("`%s%s' not allowed with `%s%c'"),
5632 register_prefix,
29b0f896
AM		 5633 i.op[op].regs->reg_name,
5634 i.tm.name,
5635 i.suffix);
5636 return 0;
5637 }
e4630f71 5638 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5639 else if ((i.types[op].bitfield.reg16
5640 || i.types[op].bitfield.reg32)
5641 && (i.tm.operand_types[op].bitfield.reg32
5642 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5643 {
5644 /* Prohibit these changes in the 64bit mode, since the
5645 lowering is more complicated. */
34828aad 5646 if (intel_syntax
ca61edf2 5647 && i.tm.opcode_modifier.todword
40fb9820 5648 && !i.types[0].bitfield.regxmm)
34828aad 5649 {
ca61edf2 5650 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5651 i.suffix = LONG_MNEM_SUFFIX;
5652 }
5653 else
5654 {
2b5d6a91 5655 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5656 register_prefix, i.op[op].regs->reg_name,
5657 i.suffix);
5658 return 0;
5659 }
252b5132 5660 }
29b0f896
AM		 5661 return 1;
5662}
252b5132 5663
29b0f896 5664static int
e3bb37b5 5665check_word_reg (void)
29b0f896
AM		 5666{
5667 int op;
5668 for (op = i.operands; --op >= 0;)
5669 /* Reject eight bit registers, except where the template requires
5670 them. (eg. movzb) */
40fb9820
L		 5671 if (i.types[op].bitfield.reg8
5672 && (i.tm.operand_types[op].bitfield.reg16
5673 || i.tm.operand_types[op].bitfield.reg32
5674 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5675 {
a540244d
L		 5676 as_bad (_("`%s%s' not allowed with `%s%c'"),
5677 register_prefix,
29b0f896
AM		 5678 i.op[op].regs->reg_name,
5679 i.tm.name,
5680 i.suffix);
5681 return 0;
5682 }
e4630f71 5683 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5684 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5685 && (i.types[op].bitfield.reg32
5686 || i.types[op].bitfield.reg64)
40fb9820
L		 5687 && (i.tm.operand_types[op].bitfield.reg16
5688 || i.tm.operand_types[op].bitfield.acc))
252b5132 5689 {
29b0f896
AM		 5690 /* Prohibit these changes in the 64bit mode, since the
5691 lowering is more complicated. */
5692 if (flag_code == CODE_64BIT)
252b5132 5693 {
2b5d6a91 5694 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5695 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5696 i.suffix);
5697 return 0;
252b5132 5698 }
29b0f896 5699#if REGISTER_WARNINGS
cecf1424
JB		 5700 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5701 register_prefix,
5702 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5703 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5704#endif
5705 }
5706 return 1;
5707}
252b5132 5708
29b0f896 5709static int
40fb9820 5710update_imm (unsigned int j)
29b0f896 5711{
bc0844ae 5712 i386_operand_type overlap = i.types[j];
40fb9820
L		 5713 if ((overlap.bitfield.imm8
5714 || overlap.bitfield.imm8s
5715 || overlap.bitfield.imm16
5716 || overlap.bitfield.imm32
5717 || overlap.bitfield.imm32s
5718 || overlap.bitfield.imm64)
0dfbf9d7
L		 5719 && !operand_type_equal (&overlap, &imm8)
5720 && !operand_type_equal (&overlap, &imm8s)
5721 && !operand_type_equal (&overlap, &imm16)
5722 && !operand_type_equal (&overlap, &imm32)
5723 && !operand_type_equal (&overlap, &imm32s)
5724 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5725 {
5726 if (i.suffix)
5727 {
40fb9820
L		 5728 i386_operand_type temp;
5729
0dfbf9d7 5730 operand_type_set (&temp, 0);
7ab9ffdd 5731 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5732 {
5733 temp.bitfield.imm8 = overlap.bitfield.imm8;
5734 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5735 }
5736 else if (i.suffix == WORD_MNEM_SUFFIX)
5737 temp.bitfield.imm16 = overlap.bitfield.imm16;
5738 else if (i.suffix == QWORD_MNEM_SUFFIX)
5739 {
5740 temp.bitfield.imm64 = overlap.bitfield.imm64;
5741 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5742 }
5743 else
5744 temp.bitfield.imm32 = overlap.bitfield.imm32;
5745 overlap = temp;
29b0f896 5746 }
0dfbf9d7
L		 5747 else if (operand_type_equal (&overlap, &imm16_32_32s)
5748 || operand_type_equal (&overlap, &imm16_32)
5749 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5750 {
40fb9820 5751 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5752 overlap = imm16;
40fb9820 5753 else
65da13b5 5754 overlap = imm32s;
29b0f896 5755 }
0dfbf9d7
L		 5756 if (!operand_type_equal (&overlap, &imm8)
5757 && !operand_type_equal (&overlap, &imm8s)
5758 && !operand_type_equal (&overlap, &imm16)
5759 && !operand_type_equal (&overlap, &imm32)
5760 && !operand_type_equal (&overlap, &imm32s)
5761 && !operand_type_equal (&overlap, &imm64))
29b0f896 5762 {
4eed87de
AM		 5763 as_bad (_("no instruction mnemonic suffix given; "
5764 "can't determine immediate size"));
29b0f896
AM		 5765 return 0;
5766 }
5767 }
40fb9820 5768 i.types[j] = overlap;
29b0f896 5769
40fb9820
L		 5770 return 1;
5771}
5772
5773static int
5774finalize_imm (void)
5775{
bc0844ae 5776 unsigned int j, n;
29b0f896 5777
bc0844ae
L		 5778 /* Update the first 2 immediate operands. */
5779 n = i.operands > 2 ? 2 : i.operands;
5780 if (n)
5781 {
5782 for (j = 0; j < n; j++)
5783 if (update_imm (j) == 0)
5784 return 0;
40fb9820 5785
bc0844ae
L		 5786 /* The 3rd operand can't be immediate operand. */
5787 gas_assert (operand_type_check (i.types[2], imm) == 0);
5788 }
29b0f896
AM		 5789
5790 return 1;
5791}
5792
c0f3af97
L		 5793static int
5794bad_implicit_operand (int xmm)
5795{
91d6fa6a
NC		 5796 const char *ireg = xmm ? "xmm0" : "ymm0";
5797
c0f3af97
L		 5798 if (intel_syntax)
5799 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5800 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5801 else
5802 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5803 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5804 return 0;
5805}
5806
29b0f896 5807static int
e3bb37b5 5808process_operands (void)
29b0f896
AM		 5809{
5810 /* Default segment register this instruction will use for memory
5811 accesses. 0 means unknown. This is only for optimizing out
5812 unnecessary segment overrides. */
5813 const seg_entry *default_seg = 0;
5814
2426c15f 5815 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5816 {
91d6fa6a
NC		 5817 unsigned int dupl = i.operands;
5818 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5819 unsigned int j;
5820
c0f3af97 5821 /* The destination must be an xmm register. */
9c2799c2 5822 gas_assert (i.reg_operands
91d6fa6a 5823 && MAX_OPERANDS > dupl
7ab9ffdd 5824 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5825
5826 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5827 {
c0f3af97 5828 /* The first operand is implicit and must be xmm0. */
9c2799c2 5829 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5830 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5831 return bad_implicit_operand (1);
5832
8cd7925b 5833 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5834 {
5835 /* Keep xmm0 for instructions with VEX prefix and 3
5836 sources. */
5837 goto duplicate;
5838 }
e2ec9d29 5839 else
c0f3af97
L		 5840 {
5841 /* We remove the first xmm0 and keep the number of
5842 operands unchanged, which in fact duplicates the
5843 destination. */
5844 for (j = 1; j < i.operands; j++)
5845 {
5846 i.op[j - 1] = i.op[j];
5847 i.types[j - 1] = i.types[j];
5848 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5849 }
5850 }
5851 }
5852 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5853 {
91d6fa6a 5854 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5855 && (i.tm.opcode_modifier.vexsources
5856 == VEX3SOURCES));
c0f3af97
L		 5857
5858 /* Add the implicit xmm0 for instructions with VEX prefix
5859 and 3 sources. */
5860 for (j = i.operands; j > 0; j--)
5861 {
5862 i.op[j] = i.op[j - 1];
5863 i.types[j] = i.types[j - 1];
5864 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5865 }
5866 i.op[0].regs
5867 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5868 i.types[0] = regxmm;
c0f3af97
L		 5869 i.tm.operand_types[0] = regxmm;
5870
5871 i.operands += 2;
5872 i.reg_operands += 2;
5873 i.tm.operands += 2;
5874
91d6fa6a 5875 dupl++;
c0f3af97 5876 dest++;
91d6fa6a
NC		 5877 i.op[dupl] = i.op[dest];
5878 i.types[dupl] = i.types[dest];
5879 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5880 }
c0f3af97
L		 5881 else
5882 {
5883duplicate:
5884 i.operands++;
5885 i.reg_operands++;
5886 i.tm.operands++;
5887
91d6fa6a
NC		 5888 i.op[dupl] = i.op[dest];
5889 i.types[dupl] = i.types[dest];
5890 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5891 }
5892
5893 if (i.tm.opcode_modifier.immext)
5894 process_immext ();
5895 }
5896 else if (i.tm.opcode_modifier.firstxmm0)
5897 {
5898 unsigned int j;
5899
43234a1e 5900 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5901 gas_assert (i.reg_operands
7ab9ffdd 5902 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5903 || operand_type_equal (&i.types[0], &regymm)
5904 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5905 if (register_number (i.op[0].regs) != 0)
c0f3af97 5906 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5907
5908 for (j = 1; j < i.operands; j++)
5909 {
5910 i.op[j - 1] = i.op[j];
5911 i.types[j - 1] = i.types[j];
5912
5913 /* We need to adjust fields in i.tm since they are used by
5914 build_modrm_byte. */
5915 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5916 }
5917
e2ec9d29
L		 5918 i.operands--;
5919 i.reg_operands--;
e2ec9d29
L		 5920 i.tm.operands--;
5921 }
5922 else if (i.tm.opcode_modifier.regkludge)
5923 {
5924 /* The imul $imm, %reg instruction is converted into
5925 imul $imm, %reg, %reg, and the clr %reg instruction
5926 is converted into xor %reg, %reg. */
5927
5928 unsigned int first_reg_op;
5929
5930 if (operand_type_check (i.types[0], reg))
5931 first_reg_op = 0;
5932 else
5933 first_reg_op = 1;
5934 /* Pretend we saw the extra register operand. */
9c2799c2 5935 gas_assert (i.reg_operands == 1
7ab9ffdd 5936 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5937 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5938 i.types[first_reg_op + 1] = i.types[first_reg_op];
5939 i.operands++;
5940 i.reg_operands++;
29b0f896
AM		 5941 }
5942
40fb9820 5943 if (i.tm.opcode_modifier.shortform)
29b0f896 5944 {
40fb9820
L		 5945 if (i.types[0].bitfield.sreg2
5946 || i.types[0].bitfield.sreg3)
29b0f896 5947 {
4eed87de
AM		 5948 if (i.tm.base_opcode == POP_SEG_SHORT
5949 && i.op[0].regs->reg_num == 1)
29b0f896 5950 {
a87af027 5951 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5952 return 0;
29b0f896 5953 }
4eed87de
AM		 5954 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5955 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5956 i.rex |= REX_B;
4eed87de
AM		 5957 }
5958 else
5959 {
7ab9ffdd 5960 /* The register or float register operand is in operand
85f10a01 5961 0 or 1. */
40fb9820 5962 unsigned int op;
7ab9ffdd
L		 5963
5964 if (i.types[0].bitfield.floatreg
5965 || operand_type_check (i.types[0], reg))
5966 op = 0;
5967 else
5968 op = 1;
4eed87de
AM		 5969 /* Register goes in low 3 bits of opcode. */
5970 i.tm.base_opcode |= i.op[op].regs->reg_num;
5971 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5972 i.rex |= REX_B;
40fb9820 5973 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5974 {
4eed87de
AM		 5975 /* Warn about some common errors, but press on regardless.
5976 The first case can be generated by gcc (<= 2.8.1). */
5977 if (i.operands == 2)
5978 {
5979 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5980 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5981 register_prefix, i.op[!intel_syntax].regs->reg_name,
5982 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5983 }
5984 else
5985 {
5986 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5987 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5988 register_prefix, i.op[0].regs->reg_name);
4eed87de 5989 }
29b0f896
AM		 5990 }
5991 }
5992 }
40fb9820 5993 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5994 {
5995 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5996 must be put into the modrm byte). Now, we make the modrm and
5997 index base bytes based on all the info we've collected. */
29b0f896
AM		 5998
5999 default_seg = build_modrm_byte ();
6000 }
8a2ed489 6001 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6002 {
6003 default_seg = &ds;
6004 }
40fb9820 6005 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6006 {
6007 /* For the string instructions that allow a segment override
6008 on one of their operands, the default segment is ds. */
6009 default_seg = &ds;
6010 }
6011
75178d9d
L		 6012 if (i.tm.base_opcode == 0x8d /* lea */
6013 && i.seg[0]
6014 && !quiet_warnings)
30123838 6015 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6016
6017 /* If a segment was explicitly specified, and the specified segment
6018 is not the default, use an opcode prefix to select it. If we
6019 never figured out what the default segment is, then default_seg
6020 will be zero at this point, and the specified segment prefix will
6021 always be used. */
29b0f896
AM		 6022 if ((i.seg[0]) && (i.seg[0] != default_seg))
6023 {
6024 if (!add_prefix (i.seg[0]->seg_prefix))
6025 return 0;
6026 }
6027 return 1;
6028}
6029
6030static const seg_entry *
e3bb37b5 6031build_modrm_byte (void)
29b0f896
AM		 6032{
6033 const seg_entry *default_seg = 0;
c0f3af97 6034 unsigned int source, dest;
8cd7925b 6035 int vex_3_sources;
c0f3af97
L		 6036
6037 /* The first operand of instructions with VEX prefix and 3 sources
6038 must be VEX_Imm4. */
8cd7925b 6039 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6040 if (vex_3_sources)
6041 {
91d6fa6a 6042 unsigned int nds, reg_slot;
4c2c6516 6043 expressionS *exp;
c0f3af97 6044
922d8de8 6045 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6046 && i.tm.opcode_modifier.immext)
6047 {
6048 dest = i.operands - 2;
6049 gas_assert (dest == 3);
6050 }
922d8de8 6051 else
a683cc34 6052 dest = i.operands - 1;
c0f3af97 6053 nds = dest - 1;
922d8de8 6054
a683cc34
SP		 6055 /* There are 2 kinds of instructions:
6056 1. 5 operands: 4 register operands or 3 register operands
6057 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6058 VexW0 or VexW1. The destination must be either XMM, YMM or
6059 ZMM register.
a683cc34
SP		 6060 2. 4 operands: 4 register operands or 3 register operands
6061 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6062 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6063 || (i.reg_operands == 3 && i.mem_operands == 1))
6064 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6065 && (i.tm.opcode_modifier.veximmext
6066 || (i.imm_operands == 1
6067 && i.types[0].bitfield.vec_imm4
6068 && (i.tm.opcode_modifier.vexw == VEXW0
6069 || i.tm.opcode_modifier.vexw == VEXW1)
6070 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6071 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6072 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6073
6074 if (i.imm_operands == 0)
6075 {
6076 /* When there is no immediate operand, generate an 8bit
6077 immediate operand to encode the first operand. */
6078 exp = &im_expressions[i.imm_operands++];
6079 i.op[i.operands].imms = exp;
6080 i.types[i.operands] = imm8;
6081 i.operands++;
6082 /* If VexW1 is set, the first operand is the source and
6083 the second operand is encoded in the immediate operand. */
6084 if (i.tm.opcode_modifier.vexw == VEXW1)
6085 {
6086 source = 0;
6087 reg_slot = 1;
6088 }
6089 else
6090 {
6091 source = 1;
6092 reg_slot = 0;
6093 }
6094
6095 /* FMA swaps REG and NDS. */
6096 if (i.tm.cpu_flags.bitfield.cpufma)
6097 {
6098 unsigned int tmp;
6099 tmp = reg_slot;
6100 reg_slot = nds;
6101 nds = tmp;
6102 }
6103
24981e7b
L		 6104 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6105 &regxmm)
a683cc34 6106 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6107 &regymm)
6108 || operand_type_equal (&i.tm.operand_types[reg_slot],
6109 &regzmm));
a683cc34 6110 exp->X_op = O_constant;
4c692bc7 6111 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6112 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6113 }
922d8de8 6114 else
a683cc34
SP		 6115 {
6116 unsigned int imm_slot;
6117
6118 if (i.tm.opcode_modifier.vexw == VEXW0)
6119 {
6120 /* If VexW0 is set, the third operand is the source and
6121 the second operand is encoded in the immediate
6122 operand. */
6123 source = 2;
6124 reg_slot = 1;
6125 }
6126 else
6127 {
6128 /* VexW1 is set, the second operand is the source and
6129 the third operand is encoded in the immediate
6130 operand. */
6131 source = 1;
6132 reg_slot = 2;
6133 }
6134
6135 if (i.tm.opcode_modifier.immext)
6136 {
6137 /* When ImmExt is set, the immdiate byte is the last
6138 operand. */
6139 imm_slot = i.operands - 1;
6140 source--;
6141 reg_slot--;
6142 }
6143 else
6144 {
6145 imm_slot = 0;
6146
6147 /* Turn on Imm8 so that output_imm will generate it. */
6148 i.types[imm_slot].bitfield.imm8 = 1;
6149 }
6150
24981e7b
L		 6151 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6152 &regxmm)
6153 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6154 &regymm)
6155 || operand_type_equal (&i.tm.operand_types[reg_slot],
6156 &regzmm));
a683cc34 6157 i.op[imm_slot].imms->X_add_number
4c692bc7 6158 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6159 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6160 }
6161
6162 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6163 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6164 &regymm)
6165 || operand_type_equal (&i.tm.operand_types[nds],
6166 &regzmm));
dae39acc 6167 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6168 }
6169 else
6170 source = dest = 0;
29b0f896
AM		 6171
6172 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6173 implicit registers do not count. If there are 3 register
6174 operands, it must be a instruction with VexNDS. For a
6175 instruction with VexNDD, the destination register is encoded
6176 in VEX prefix. If there are 4 register operands, it must be
6177 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6178 if (i.mem_operands == 0
6179 && ((i.reg_operands == 2
2426c15f 6180 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6181 || (i.reg_operands == 3
2426c15f 6182 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6183 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6184 {
cab737b9
L		 6185 switch (i.operands)
6186 {
6187 case 2:
6188 source = 0;
6189 break;
6190 case 3:
c81128dc
L		 6191 /* When there are 3 operands, one of them may be immediate,
6192 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6193 the first operand must be shift count register (cl) or it
6194 is an instruction with VexNDS. */
9c2799c2 6195 gas_assert (i.imm_operands == 1
7ab9ffdd 6196 || (i.imm_operands == 0
2426c15f 6197 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6198 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6199 if (operand_type_check (i.types[0], imm)
6200 || i.types[0].bitfield.shiftcount)
6201 source = 1;
6202 else
6203 source = 0;
cab737b9
L		 6204 break;
6205 case 4:
368d64cc
L		 6206 /* When there are 4 operands, the first two must be 8bit
6207 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6208 one.
6209
6210 For instructions with VexNDS, if the first operand
6211 an imm8, the source operand is the 2nd one. If the last
6212 operand is imm8, the source operand is the first one. */
9c2799c2 6213 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6214 && i.types[0].bitfield.imm8
6215 && i.types[1].bitfield.imm8)
2426c15f 6216 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6217 && i.imm_operands == 1
6218 && (i.types[0].bitfield.imm8
43234a1e
L		 6219 || i.types[i.operands - 1].bitfield.imm8
6220 || i.rounding)));
9f2670f2
L		 6221 if (i.imm_operands == 2)
6222 source = 2;
6223 else
c0f3af97
L		 6224 {
6225 if (i.types[0].bitfield.imm8)
6226 source = 1;
6227 else
6228 source = 0;
6229 }
c0f3af97
L		 6230 break;
6231 case 5:
43234a1e
L		 6232 if (i.tm.opcode_modifier.evex)
6233 {
6234 /* For EVEX instructions, when there are 5 operands, the
6235 first one must be immediate operand. If the second one
6236 is immediate operand, the source operand is the 3th
6237 one. If the last one is immediate operand, the source
6238 operand is the 2nd one. */
6239 gas_assert (i.imm_operands == 2
6240 && i.tm.opcode_modifier.sae
6241 && operand_type_check (i.types[0], imm));
6242 if (operand_type_check (i.types[1], imm))
6243 source = 2;
6244 else if (operand_type_check (i.types[4], imm))
6245 source = 1;
6246 else
6247 abort ();
6248 }
cab737b9
L		 6249 break;
6250 default:
6251 abort ();
6252 }
6253
c0f3af97
L		 6254 if (!vex_3_sources)
6255 {
6256 dest = source + 1;
6257
43234a1e
L		 6258 /* RC/SAE operand could be between DEST and SRC. That happens
6259 when one operand is GPR and the other one is XMM/YMM/ZMM
6260 register. */
6261 if (i.rounding && i.rounding->operand == (int) dest)
6262 dest++;
6263
2426c15f 6264 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6265 {
43234a1e
L		 6266 /* For instructions with VexNDS, the register-only source
6267 operand must be 32/64bit integer, XMM, YMM or ZMM
6268 register. It is encoded in VEX prefix. We need to
6269 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6270
6271 i386_operand_type op;
6272 unsigned int vvvv;
6273
6274 /* Check register-only source operand when two source
6275 operands are swapped. */
6276 if (!i.tm.operand_types[source].bitfield.baseindex
6277 && i.tm.operand_types[dest].bitfield.baseindex)
6278 {
6279 vvvv = source;
6280 source = dest;
6281 }
6282 else
6283 vvvv = dest;
6284
6285 op = i.tm.operand_types[vvvv];
fa99fab2 6286 op.bitfield.regmem = 0;
c0f3af97 6287 if ((dest + 1) >= i.operands
ac4eb736
AM		 6288 || (!op.bitfield.reg32
6289 && op.bitfield.reg64
f12dc422 6290 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6291 && !operand_type_equal (&op, &regymm)
6292 && !operand_type_equal (&op, &regzmm)
6293 && !operand_type_equal (&op, &regmask)))
c0f3af97 6294 abort ();
f12dc422 6295 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6296 dest++;
6297 }
6298 }
29b0f896
AM		 6299
6300 i.rm.mode = 3;
6301 /* One of the register operands will be encoded in the i.tm.reg
6302 field, the other in the combined i.tm.mode and i.tm.regmem
6303 fields. If no form of this instruction supports a memory
6304 destination operand, then we assume the source operand may
6305 sometimes be a memory operand and so we need to store the
6306 destination in the i.rm.reg field. */
40fb9820
L		 6307 if (!i.tm.operand_types[dest].bitfield.regmem
6308 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6309 {
6310 i.rm.reg = i.op[dest].regs->reg_num;
6311 i.rm.regmem = i.op[source].regs->reg_num;
6312 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6313 i.rex |= REX_R;
43234a1e
L		 6314 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6315 i.vrex |= REX_R;
29b0f896 6316 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6317 i.rex |= REX_B;
43234a1e
L		 6318 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6319 i.vrex |= REX_B;
29b0f896
AM		 6320 }
6321 else
6322 {
6323 i.rm.reg = i.op[source].regs->reg_num;
6324 i.rm.regmem = i.op[dest].regs->reg_num;
6325 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6326 i.rex |= REX_B;
43234a1e
L		 6327 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6328 i.vrex |= REX_B;
29b0f896 6329 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6330 i.rex |= REX_R;
43234a1e
L		 6331 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6332 i.vrex |= REX_R;
29b0f896 6333 }
161a04f6 6334 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6335 {
40fb9820
L		 6336 if (!i.types[0].bitfield.control
6337 && !i.types[1].bitfield.control)
c4a530c5 6338 abort ();
161a04f6 6339 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6340 add_prefix (LOCK_PREFIX_OPCODE);
6341 }
29b0f896
AM		 6342 }
6343 else
6344 { /* If it's not 2 reg operands... */
c0f3af97
L		 6345 unsigned int mem;
6346
29b0f896
AM		 6347 if (i.mem_operands)
6348 {
6349 unsigned int fake_zero_displacement = 0;
99018f42 6350 unsigned int op;
4eed87de 6351
7ab9ffdd
L		 6352 for (op = 0; op < i.operands; op++)
6353 if (operand_type_check (i.types[op], anymem))
6354 break;
7ab9ffdd 6355 gas_assert (op < i.operands);
29b0f896 6356
6c30d220
L		 6357 if (i.tm.opcode_modifier.vecsib)
6358 {
6359 if (i.index_reg->reg_num == RegEiz
6360 || i.index_reg->reg_num == RegRiz)
6361 abort ();
6362
6363 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6364 if (!i.base_reg)
6365 {
6366 i.sib.base = NO_BASE_REGISTER;
6367 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6368 /* No Vec_Disp8 if there is no base. */
6369 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6370 i.types[op].bitfield.disp8 = 0;
6371 i.types[op].bitfield.disp16 = 0;
6372 i.types[op].bitfield.disp64 = 0;
6373 if (flag_code != CODE_64BIT)
6374 {
6375 /* Must be 32 bit */
6376 i.types[op].bitfield.disp32 = 1;
6377 i.types[op].bitfield.disp32s = 0;
6378 }
6379 else
6380 {
6381 i.types[op].bitfield.disp32 = 0;
6382 i.types[op].bitfield.disp32s = 1;
6383 }
6384 }
6385 i.sib.index = i.index_reg->reg_num;
6386 if ((i.index_reg->reg_flags & RegRex) != 0)
6387 i.rex |= REX_X;
43234a1e
L		 6388 if ((i.index_reg->reg_flags & RegVRex) != 0)
6389 i.vrex |= REX_X;
6c30d220
L		 6390 }
6391
29b0f896
AM		 6392 default_seg = &ds;
6393
6394 if (i.base_reg == 0)
6395 {
6396 i.rm.mode = 0;
6397 if (!i.disp_operands)
6c30d220
L		 6398 {
6399 fake_zero_displacement = 1;
6400 /* Instructions with VSIB byte need 32bit displacement
6401 if there is no base register. */
6402 if (i.tm.opcode_modifier.vecsib)
6403 i.types[op].bitfield.disp32 = 1;
6404 }
29b0f896
AM		 6405 if (i.index_reg == 0)
6406 {
6c30d220 6407 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6408 /* Operand is just <disp> */
20f0a1fc 6409 if (flag_code == CODE_64BIT)
29b0f896
AM		 6410 {
6411 /* 64bit mode overwrites the 32bit absolute
6412 addressing by RIP relative addressing and
6413 absolute addressing is encoded by one of the
6414 redundant SIB forms. */
6415 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6416 i.sib.base = NO_BASE_REGISTER;
6417 i.sib.index = NO_INDEX_REGISTER;
fc225355 6418 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6419 ? disp32s : disp32);
20f0a1fc 6420 }
fc225355
L		 6421 else if ((flag_code == CODE_16BIT)
6422 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6423 {
6424 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6425 i.types[op] = disp16;
20f0a1fc
NC		 6426 }
6427 else
6428 {
6429 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6430 i.types[op] = disp32;
29b0f896
AM		 6431 }
6432 }
6c30d220 6433 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6434 {
6c30d220 6435 /* !i.base_reg && i.index_reg */
db51cc60
L		 6436 if (i.index_reg->reg_num == RegEiz
6437 || i.index_reg->reg_num == RegRiz)
6438 i.sib.index = NO_INDEX_REGISTER;
6439 else
6440 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6441 i.sib.base = NO_BASE_REGISTER;
6442 i.sib.scale = i.log2_scale_factor;
6443 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6444 /* No Vec_Disp8 if there is no base. */
6445 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6446 i.types[op].bitfield.disp8 = 0;
6447 i.types[op].bitfield.disp16 = 0;
6448 i.types[op].bitfield.disp64 = 0;
29b0f896 6449 if (flag_code != CODE_64BIT)
40fb9820
L		 6450 {
6451 /* Must be 32 bit */
6452 i.types[op].bitfield.disp32 = 1;
6453 i.types[op].bitfield.disp32s = 0;
6454 }
29b0f896 6455 else
40fb9820
L		 6456 {
6457 i.types[op].bitfield.disp32 = 0;
6458 i.types[op].bitfield.disp32s = 1;
6459 }
29b0f896 6460 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6461 i.rex |= REX_X;
29b0f896
AM		 6462 }
6463 }
6464 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6465 else if (i.base_reg->reg_num == RegRip ||
6466 i.base_reg->reg_num == RegEip)
29b0f896 6467 {
6c30d220 6468 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6469 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6470 i.types[op].bitfield.disp8 = 0;
6471 i.types[op].bitfield.disp16 = 0;
6472 i.types[op].bitfield.disp32 = 0;
6473 i.types[op].bitfield.disp32s = 1;
6474 i.types[op].bitfield.disp64 = 0;
43234a1e 6475 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6476 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6477 if (! i.disp_operands)
6478 fake_zero_displacement = 1;
29b0f896 6479 }
40fb9820 6480 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6481 {
6c30d220 6482 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6483 switch (i.base_reg->reg_num)
6484 {
6485 case 3: /* (%bx) */
6486 if (i.index_reg == 0)
6487 i.rm.regmem = 7;
6488 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6489 i.rm.regmem = i.index_reg->reg_num - 6;
6490 break;
6491 case 5: /* (%bp) */
6492 default_seg = &ss;
6493 if (i.index_reg == 0)
6494 {
6495 i.rm.regmem = 6;
40fb9820 6496 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6497 {
6498 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6499 if (i.tm.operand_types[op].bitfield.vec_disp8)
6500 i.types[op].bitfield.vec_disp8 = 1;
6501 else
6502 i.types[op].bitfield.disp8 = 1;
252b5132 6503 fake_zero_displacement = 1;
29b0f896
AM		 6504 }
6505 }
6506 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6507 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6508 break;
6509 default: /* (%si) -> 4 or (%di) -> 5 */
6510 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6511 }
6512 i.rm.mode = mode_from_disp_size (i.types[op]);
6513 }
6514 else /* i.base_reg and 32/64 bit mode */
6515 {
6516 if (flag_code == CODE_64BIT
40fb9820
L		 6517 && operand_type_check (i.types[op], disp))
6518 {
6519 i386_operand_type temp;
0dfbf9d7 6520 operand_type_set (&temp, 0);
40fb9820 6521 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6522 temp.bitfield.vec_disp8
6523 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6524 i.types[op] = temp;
6525 if (i.prefix[ADDR_PREFIX] == 0)
6526 i.types[op].bitfield.disp32s = 1;
6527 else
6528 i.types[op].bitfield.disp32 = 1;
6529 }
20f0a1fc 6530
6c30d220
L		 6531 if (!i.tm.opcode_modifier.vecsib)
6532 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6533 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6534 i.rex |= REX_B;
29b0f896
AM		 6535 i.sib.base = i.base_reg->reg_num;
6536 /* x86-64 ignores REX prefix bit here to avoid decoder
6537 complications. */
848930b2
JB		 6538 if (!(i.base_reg->reg_flags & RegRex)
6539 && (i.base_reg->reg_num == EBP_REG_NUM
6540 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6541 default_seg = &ss;
848930b2 6542 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6543 {
848930b2 6544 fake_zero_displacement = 1;
43234a1e
L		 6545 if (i.tm.operand_types [op].bitfield.vec_disp8)
6546 i.types[op].bitfield.vec_disp8 = 1;
6547 else
6548 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6549 }
6550 i.sib.scale = i.log2_scale_factor;
6551 if (i.index_reg == 0)
6552 {
6c30d220 6553 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6554 /* <disp>(%esp) becomes two byte modrm with no index
6555 register. We've already stored the code for esp
6556 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6557 Any base register besides %esp will not use the
6558 extra modrm byte. */
6559 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6560 }
6c30d220 6561 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6562 {
db51cc60
L		 6563 if (i.index_reg->reg_num == RegEiz
6564 || i.index_reg->reg_num == RegRiz)
6565 i.sib.index = NO_INDEX_REGISTER;
6566 else
6567 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6568 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6569 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6570 i.rex |= REX_X;
29b0f896 6571 }
67a4f2b7
AO		 6572
6573 if (i.disp_operands
6574 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6575 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6576 i.rm.mode = 0;
6577 else
a501d77e
L		 6578 {
6579 if (!fake_zero_displacement
6580 && !i.disp_operands
6581 && i.disp_encoding)
6582 {
6583 fake_zero_displacement = 1;
6584 if (i.disp_encoding == disp_encoding_8bit)
6585 i.types[op].bitfield.disp8 = 1;
6586 else
6587 i.types[op].bitfield.disp32 = 1;
6588 }
6589 i.rm.mode = mode_from_disp_size (i.types[op]);
6590 }
29b0f896 6591 }
252b5132 6592
29b0f896
AM		 6593 if (fake_zero_displacement)
6594 {
6595 /* Fakes a zero displacement assuming that i.types[op]
6596 holds the correct displacement size. */
6597 expressionS *exp;
6598
9c2799c2 6599 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6600 exp = &disp_expressions[i.disp_operands++];
6601 i.op[op].disps = exp;
6602 exp->X_op = O_constant;
6603 exp->X_add_number = 0;
6604 exp->X_add_symbol = (symbolS *) 0;
6605 exp->X_op_symbol = (symbolS *) 0;
6606 }
c0f3af97
L		 6607
6608 mem = op;
29b0f896 6609 }
c0f3af97
L		 6610 else
6611 mem = ~0;
252b5132 6612
8c43a48b 6613 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6614 {
6615 if (operand_type_check (i.types[0], imm))
6616 i.vex.register_specifier = NULL;
6617 else
6618 {
6619 /* VEX.vvvv encodes one of the sources when the first
6620 operand is not an immediate. */
1ef99a7b 6621 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6622 i.vex.register_specifier = i.op[0].regs;
6623 else
6624 i.vex.register_specifier = i.op[1].regs;
6625 }
6626
6627 /* Destination is a XMM register encoded in the ModRM.reg
6628 and VEX.R bit. */
6629 i.rm.reg = i.op[2].regs->reg_num;
6630 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6631 i.rex |= REX_R;
6632
6633 /* ModRM.rm and VEX.B encodes the other source. */
6634 if (!i.mem_operands)
6635 {
6636 i.rm.mode = 3;
6637
1ef99a7b 6638 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6639 i.rm.regmem = i.op[1].regs->reg_num;
6640 else
6641 i.rm.regmem = i.op[0].regs->reg_num;
6642
6643 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6644 i.rex |= REX_B;
6645 }
6646 }
2426c15f 6647 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6648 {
6649 i.vex.register_specifier = i.op[2].regs;
6650 if (!i.mem_operands)
6651 {
6652 i.rm.mode = 3;
6653 i.rm.regmem = i.op[1].regs->reg_num;
6654 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6655 i.rex |= REX_B;
6656 }
6657 }
29b0f896
AM		 6658 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6659 (if any) based on i.tm.extension_opcode. Again, we must be
6660 careful to make sure that segment/control/debug/test/MMX
6661 registers are coded into the i.rm.reg field. */
f88c9eb0 6662 else if (i.reg_operands)
29b0f896 6663 {
99018f42 6664 unsigned int op;
7ab9ffdd
L		 6665 unsigned int vex_reg = ~0;
6666
6667 for (op = 0; op < i.operands; op++)
6668 if (i.types[op].bitfield.reg8
6669 || i.types[op].bitfield.reg16
6670 || i.types[op].bitfield.reg32
6671 || i.types[op].bitfield.reg64
6672 || i.types[op].bitfield.regmmx
6673 || i.types[op].bitfield.regxmm
6674 || i.types[op].bitfield.regymm
7e8b059b 6675 || i.types[op].bitfield.regbnd
43234a1e
L		 6676 || i.types[op].bitfield.regzmm
6677 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6678 || i.types[op].bitfield.sreg2
6679 || i.types[op].bitfield.sreg3
6680 || i.types[op].bitfield.control
6681 || i.types[op].bitfield.debug
6682 || i.types[op].bitfield.test)
6683 break;
c0209578 6684
7ab9ffdd
L		 6685 if (vex_3_sources)
6686 op = dest;
2426c15f 6687 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6688 {
6689 /* For instructions with VexNDS, the register-only
6690 source operand is encoded in VEX prefix. */
6691 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6692
7ab9ffdd 6693 if (op > mem)
c0f3af97 6694 {
7ab9ffdd
L		 6695 vex_reg = op++;
6696 gas_assert (op < i.operands);
c0f3af97
L		 6697 }
6698 else
c0f3af97 6699 {
f12dc422
L		 6700 /* Check register-only source operand when two source
6701 operands are swapped. */
6702 if (!i.tm.operand_types[op].bitfield.baseindex
6703 && i.tm.operand_types[op + 1].bitfield.baseindex)
6704 {
6705 vex_reg = op;
6706 op += 2;
6707 gas_assert (mem == (vex_reg + 1)
6708 && op < i.operands);
6709 }
6710 else
6711 {
6712 vex_reg = op + 1;
6713 gas_assert (vex_reg < i.operands);
6714 }
c0f3af97 6715 }
7ab9ffdd 6716 }
2426c15f 6717 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6718 {
f12dc422 6719 /* For instructions with VexNDD, the register destination
7ab9ffdd 6720 is encoded in VEX prefix. */
f12dc422
L		 6721 if (i.mem_operands == 0)
6722 {
6723 /* There is no memory operand. */
6724 gas_assert ((op + 2) == i.operands);
6725 vex_reg = op + 1;
6726 }
6727 else
8d63c93e 6728 {
f12dc422
L		 6729 /* There are only 2 operands. */
6730 gas_assert (op < 2 && i.operands == 2);
6731 vex_reg = 1;
6732 }
7ab9ffdd
L		 6733 }
6734 else
6735 gas_assert (op < i.operands);
99018f42 6736
7ab9ffdd
L		 6737 if (vex_reg != (unsigned int) ~0)
6738 {
f12dc422 6739 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6740
f12dc422
L		 6741 if (type->bitfield.reg32 != 1
6742 && type->bitfield.reg64 != 1
6743 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6744 && !operand_type_equal (type, &regymm)
6745 && !operand_type_equal (type, &regzmm)
6746 && !operand_type_equal (type, &regmask))
7ab9ffdd 6747 abort ();
f88c9eb0 6748
7ab9ffdd
L		 6749 i.vex.register_specifier = i.op[vex_reg].regs;
6750 }
6751
1b9f0c97
L		 6752 /* Don't set OP operand twice. */
6753 if (vex_reg != op)
7ab9ffdd 6754 {
1b9f0c97
L		 6755 /* If there is an extension opcode to put here, the
6756 register number must be put into the regmem field. */
6757 if (i.tm.extension_opcode != None)
6758 {
6759 i.rm.regmem = i.op[op].regs->reg_num;
6760 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6761 i.rex |= REX_B;
43234a1e
L		 6762 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6763 i.vrex |= REX_B;
1b9f0c97
L		 6764 }
6765 else
6766 {
6767 i.rm.reg = i.op[op].regs->reg_num;
6768 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6769 i.rex |= REX_R;
43234a1e
L		 6770 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6771 i.vrex |= REX_R;
1b9f0c97 6772 }
7ab9ffdd 6773 }
252b5132 6774
29b0f896
AM		 6775 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6776 must set it to 3 to indicate this is a register operand
6777 in the regmem field. */
6778 if (!i.mem_operands)
6779 i.rm.mode = 3;
6780 }
252b5132 6781
29b0f896 6782 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6783 if (i.tm.extension_opcode != None)
29b0f896
AM		 6784 i.rm.reg = i.tm.extension_opcode;
6785 }
6786 return default_seg;
6787}
252b5132 6788
29b0f896 6789static void
e3bb37b5 6790output_branch (void)
29b0f896
AM		 6791{
6792 char *p;
f8a5c266 6793 int size;
29b0f896
AM		 6794 int code16;
6795 int prefix;
6796 relax_substateT subtype;
6797 symbolS *sym;
6798 offsetT off;
6799
f8a5c266 6800 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6801 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6802
6803 prefix = 0;
6804 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6805 {
29b0f896
AM		 6806 prefix = 1;
6807 i.prefixes -= 1;
6808 code16 ^= CODE16;
252b5132 6809 }
29b0f896
AM		 6810 /* Pentium4 branch hints. */
6811 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6812 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6813 {
29b0f896
AM		 6814 prefix++;
6815 i.prefixes--;
6816 }
6817 if (i.prefix[REX_PREFIX] != 0)
6818 {
6819 prefix++;
6820 i.prefixes--;
2f66722d
AM		 6821 }
6822
7e8b059b
L		 6823 /* BND prefixed jump. */
6824 if (i.prefix[BND_PREFIX] != 0)
6825 {
6826 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6827 i.prefixes -= 1;
6828 }
6829
29b0f896
AM		 6830 if (i.prefixes != 0 && !intel_syntax)
6831 as_warn (_("skipping prefixes on this instruction"));
6832
6833 /* It's always a symbol; End frag & setup for relax.
6834 Make sure there is enough room in this frag for the largest
6835 instruction we may generate in md_convert_frag. This is 2
6836 bytes for the opcode and room for the prefix and largest
6837 displacement. */
6838 frag_grow (prefix + 2 + 4);
6839 /* Prefix and 1 opcode byte go in fr_fix. */
6840 p = frag_more (prefix + 1);
6841 if (i.prefix[DATA_PREFIX] != 0)
6842 *p++ = DATA_PREFIX_OPCODE;
6843 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6844 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6845 *p++ = i.prefix[SEG_PREFIX];
6846 if (i.prefix[REX_PREFIX] != 0)
6847 *p++ = i.prefix[REX_PREFIX];
6848 *p = i.tm.base_opcode;
6849
6850 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6851 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6852 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6853 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6854 else
f8a5c266 6855 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6856 subtype |= code16;
3e73aa7c 6857
29b0f896
AM		 6858 sym = i.op[0].disps->X_add_symbol;
6859 off = i.op[0].disps->X_add_number;
3e73aa7c 6860
29b0f896
AM		 6861 if (i.op[0].disps->X_op != O_constant
6862 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6863 {
29b0f896
AM		 6864 /* Handle complex expressions. */
6865 sym = make_expr_symbol (i.op[0].disps);
6866 off = 0;
6867 }
3e73aa7c 6868
29b0f896
AM		 6869 /* 1 possible extra opcode + 4 byte displacement go in var part.
6870 Pass reloc in fr_var. */
d258b828 6871 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6872}
3e73aa7c 6873
29b0f896 6874static void
e3bb37b5 6875output_jump (void)
29b0f896
AM		 6876{
6877 char *p;
6878 int size;
3e02c1cc 6879 fixS *fixP;
29b0f896 6880
40fb9820 6881 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6882 {
6883 /* This is a loop or jecxz type instruction. */
6884 size = 1;
6885 if (i.prefix[ADDR_PREFIX] != 0)
6886 {
6887 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6888 i.prefixes -= 1;
6889 }
6890 /* Pentium4 branch hints. */
6891 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6892 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6893 {
6894 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6895 i.prefixes--;
3e73aa7c
JH		 6896 }
6897 }
29b0f896
AM		 6898 else
6899 {
6900 int code16;
3e73aa7c 6901
29b0f896
AM		 6902 code16 = 0;
6903 if (flag_code == CODE_16BIT)
6904 code16 = CODE16;
3e73aa7c 6905
29b0f896
AM		 6906 if (i.prefix[DATA_PREFIX] != 0)
6907 {
6908 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6909 i.prefixes -= 1;
6910 code16 ^= CODE16;
6911 }
252b5132 6912
29b0f896
AM		 6913 size = 4;
6914 if (code16)
6915 size = 2;
6916 }
9fcc94b6 6917
29b0f896
AM		 6918 if (i.prefix[REX_PREFIX] != 0)
6919 {
6920 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6921 i.prefixes -= 1;
6922 }
252b5132 6923
7e8b059b
L		 6924 /* BND prefixed jump. */
6925 if (i.prefix[BND_PREFIX] != 0)
6926 {
6927 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6928 i.prefixes -= 1;
6929 }
6930
29b0f896
AM		 6931 if (i.prefixes != 0 && !intel_syntax)
6932 as_warn (_("skipping prefixes on this instruction"));
e0890092 6933
42164a71
L		 6934 p = frag_more (i.tm.opcode_length + size);
6935 switch (i.tm.opcode_length)
6936 {
6937 case 2:
6938 *p++ = i.tm.base_opcode >> 8;
6939 case 1:
6940 *p++ = i.tm.base_opcode;
6941 break;
6942 default:
6943 abort ();
6944 }
e0890092 6945
3e02c1cc 6946 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6947 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6948
6949 /* All jumps handled here are signed, but don't use a signed limit
6950 check for 32 and 16 bit jumps as we want to allow wrap around at
6951 4G and 64k respectively. */
6952 if (size == 1)
6953 fixP->fx_signed = 1;
29b0f896 6954}
e0890092 6955
29b0f896 6956static void
e3bb37b5 6957output_interseg_jump (void)
29b0f896
AM		 6958{
6959 char *p;
6960 int size;
6961 int prefix;
6962 int code16;
252b5132 6963
29b0f896
AM		 6964 code16 = 0;
6965 if (flag_code == CODE_16BIT)
6966 code16 = CODE16;
a217f122 6967
29b0f896
AM		 6968 prefix = 0;
6969 if (i.prefix[DATA_PREFIX] != 0)
6970 {
6971 prefix = 1;
6972 i.prefixes -= 1;
6973 code16 ^= CODE16;
6974 }
6975 if (i.prefix[REX_PREFIX] != 0)
6976 {
6977 prefix++;
6978 i.prefixes -= 1;
6979 }
252b5132 6980
29b0f896
AM		 6981 size = 4;
6982 if (code16)
6983 size = 2;
252b5132 6984
29b0f896
AM		 6985 if (i.prefixes != 0 && !intel_syntax)
6986 as_warn (_("skipping prefixes on this instruction"));
252b5132 6987
29b0f896
AM		 6988 /* 1 opcode; 2 segment; offset */
6989 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6990
29b0f896
AM		 6991 if (i.prefix[DATA_PREFIX] != 0)
6992 *p++ = DATA_PREFIX_OPCODE;
252b5132 6993
29b0f896
AM		 6994 if (i.prefix[REX_PREFIX] != 0)
6995 *p++ = i.prefix[REX_PREFIX];
252b5132 6996
29b0f896
AM		 6997 *p++ = i.tm.base_opcode;
6998 if (i.op[1].imms->X_op == O_constant)
6999 {
7000 offsetT n = i.op[1].imms->X_add_number;
252b5132 7001
29b0f896
AM		 7002 if (size == 2
7003 && !fits_in_unsigned_word (n)
7004 && !fits_in_signed_word (n))
7005 {
7006 as_bad (_("16-bit jump out of range"));
7007 return;
7008 }
7009 md_number_to_chars (p, n, size);
7010 }
7011 else
7012 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7013 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7014 if (i.op[0].imms->X_op != O_constant)
7015 as_bad (_("can't handle non absolute segment in `%s'"),
7016 i.tm.name);
7017 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7018}
a217f122 7019
29b0f896 7020static void
e3bb37b5 7021output_insn (void)
29b0f896 7022{
2bbd9c25
JJ		 7023 fragS *insn_start_frag;
7024 offsetT insn_start_off;
7025
29b0f896
AM		 7026 /* Tie dwarf2 debug info to the address at the start of the insn.
7027 We can't do this after the insn has been output as the current
7028 frag may have been closed off. eg. by frag_var. */
7029 dwarf2_emit_insn (0);
7030
2bbd9c25
JJ		 7031 insn_start_frag = frag_now;
7032 insn_start_off = frag_now_fix ();
7033
29b0f896 7034 /* Output jumps. */
40fb9820 7035 if (i.tm.opcode_modifier.jump)
29b0f896 7036 output_branch ();
40fb9820
L		 7037 else if (i.tm.opcode_modifier.jumpbyte
7038 || i.tm.opcode_modifier.jumpdword)
29b0f896 7039 output_jump ();
40fb9820 7040 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7041 output_interseg_jump ();
7042 else
7043 {
7044 /* Output normal instructions here. */
7045 char *p;
7046 unsigned char *q;
47465058 7047 unsigned int j;
331d2d0d 7048 unsigned int prefix;
4dffcebc 7049
e4e00185
AS		 7050 if (avoid_fence
7051 && i.tm.base_opcode == 0xfae
7052 && i.operands == 1
7053 && i.imm_operands == 1
7054 && (i.op[0].imms->X_add_number == 0xe8
7055 || i.op[0].imms->X_add_number == 0xf0
7056 || i.op[0].imms->X_add_number == 0xf8))
7057 {
7058 /* Encode lfence, mfence, and sfence as
7059 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7060 offsetT val = 0x240483f0ULL;
7061 p = frag_more (5);
7062 md_number_to_chars (p, val, 5);
7063 return;
7064 }
7065
d022bddd
IT		 7066 /* Some processors fail on LOCK prefix. This options makes
7067 assembler ignore LOCK prefix and serves as a workaround. */
7068 if (omit_lock_prefix)
7069 {
7070 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7071 return;
7072 i.prefix[LOCK_PREFIX] = 0;
7073 }
7074
43234a1e
L		 7075 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7076 don't need the explicit prefix. */
7077 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7078 {
c0f3af97 7079 switch (i.tm.opcode_length)
bc4bd9ab 7080 {
c0f3af97
L		 7081 case 3:
7082 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7083 {
c0f3af97
L		 7084 prefix = (i.tm.base_opcode >> 24) & 0xff;
7085 goto check_prefix;
7086 }
7087 break;
7088 case 2:
7089 if ((i.tm.base_opcode & 0xff0000) != 0)
7090 {
7091 prefix = (i.tm.base_opcode >> 16) & 0xff;
7092 if (i.tm.cpu_flags.bitfield.cpupadlock)
7093 {
4dffcebc 7094check_prefix:
c0f3af97 7095 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7096 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7097 != REPE_PREFIX_OPCODE))
7098 add_prefix (prefix);
7099 }
7100 else
4dffcebc
L		 7101 add_prefix (prefix);
7102 }
c0f3af97
L		 7103 break;
7104 case 1:
7105 break;
7106 default:
7107 abort ();
bc4bd9ab 7108 }
c0f3af97 7109
6d19a37a 7110#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7111 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7112 R_X86_64_GOTTPOFF relocation so that linker can safely
7113 perform IE->LE optimization. */
7114 if (x86_elf_abi == X86_64_X32_ABI
7115 && i.operands == 2
7116 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7117 && i.prefix[REX_PREFIX] == 0)
7118 add_prefix (REX_OPCODE);
6d19a37a 7119#endif
cf61b747 7120
c0f3af97
L		 7121 /* The prefix bytes. */
7122 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7123 if (*q)
7124 FRAG_APPEND_1_CHAR (*q);
0f10071e 7125 }
ae5c1c7b 7126 else
c0f3af97
L		 7127 {
7128 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7129 if (*q)
7130 switch (j)
7131 {
7132 case REX_PREFIX:
7133 /* REX byte is encoded in VEX prefix. */
7134 break;
7135 case SEG_PREFIX:
7136 case ADDR_PREFIX:
7137 FRAG_APPEND_1_CHAR (*q);
7138 break;
7139 default:
7140 /* There should be no other prefixes for instructions
7141 with VEX prefix. */
7142 abort ();
7143 }
7144
43234a1e
L		 7145 /* For EVEX instructions i.vrex should become 0 after
7146 build_evex_prefix. For VEX instructions upper 16 registers
7147 aren't available, so VREX should be 0. */
7148 if (i.vrex)
7149 abort ();
c0f3af97
L		 7150 /* Now the VEX prefix. */
7151 p = frag_more (i.vex.length);
7152 for (j = 0; j < i.vex.length; j++)
7153 p[j] = i.vex.bytes[j];
7154 }
252b5132 7155
29b0f896 7156 /* Now the opcode; be careful about word order here! */
4dffcebc 7157 if (i.tm.opcode_length == 1)
29b0f896
AM		 7158 {
7159 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7160 }
7161 else
7162 {
4dffcebc 7163 switch (i.tm.opcode_length)
331d2d0d 7164 {
43234a1e
L		 7165 case 4:
7166 p = frag_more (4);
7167 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7168 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7169 break;
4dffcebc 7170 case 3:
331d2d0d
L		 7171 p = frag_more (3);
7172 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7173 break;
7174 case 2:
7175 p = frag_more (2);
7176 break;
7177 default:
7178 abort ();
7179 break;
331d2d0d 7180 }
0f10071e 7181
29b0f896
AM		 7182 /* Put out high byte first: can't use md_number_to_chars! */
7183 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7184 *p = i.tm.base_opcode & 0xff;
7185 }
3e73aa7c 7186
29b0f896 7187 /* Now the modrm byte and sib byte (if present). */
40fb9820 7188 if (i.tm.opcode_modifier.modrm)
29b0f896 7189 {
4a3523fa
L		 7190 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7191 | i.rm.reg << 3
7192 | i.rm.mode << 6));
29b0f896
AM		 7193 /* If i.rm.regmem == ESP (4)
7194 && i.rm.mode != (Register mode)
7195 && not 16 bit
7196 ==> need second modrm byte. */
7197 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7198 && i.rm.mode != 3
40fb9820 7199 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7200 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7201 | i.sib.index << 3
7202 | i.sib.scale << 6));
29b0f896 7203 }
3e73aa7c 7204
29b0f896 7205 if (i.disp_operands)
2bbd9c25 7206 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7207
29b0f896 7208 if (i.imm_operands)
2bbd9c25 7209 output_imm (insn_start_frag, insn_start_off);
29b0f896 7210 }
252b5132 7211
29b0f896
AM		 7212#ifdef DEBUG386
7213 if (flag_debug)
7214 {
7b81dfbb 7215 pi ("" /*line*/, &i);
29b0f896
AM		 7216 }
7217#endif /* DEBUG386 */
7218}
252b5132 7219
e205caa7
L		 7220/* Return the size of the displacement operand N. */
7221
7222static int
7223disp_size (unsigned int n)
7224{
7225 int size = 4;
43234a1e
L		 7226
7227 /* Vec_Disp8 has to be 8bit. */
7228 if (i.types[n].bitfield.vec_disp8)
7229 size = 1;
7230 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7231 size = 8;
7232 else if (i.types[n].bitfield.disp8)
7233 size = 1;
7234 else if (i.types[n].bitfield.disp16)
7235 size = 2;
e205caa7
L		 7236 return size;
7237}
7238
7239/* Return the size of the immediate operand N. */
7240
7241static int
7242imm_size (unsigned int n)
7243{
7244 int size = 4;
40fb9820
L		 7245 if (i.types[n].bitfield.imm64)
7246 size = 8;
7247 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7248 size = 1;
7249 else if (i.types[n].bitfield.imm16)
7250 size = 2;
e205caa7
L		 7251 return size;
7252}
7253
29b0f896 7254static void
64e74474 7255output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7256{
7257 char *p;
7258 unsigned int n;
252b5132 7259
29b0f896
AM		 7260 for (n = 0; n < i.operands; n++)
7261 {
43234a1e
L		 7262 if (i.types[n].bitfield.vec_disp8
7263 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7264 {
7265 if (i.op[n].disps->X_op == O_constant)
7266 {
e205caa7 7267 int size = disp_size (n);
43234a1e 7268 offsetT val = i.op[n].disps->X_add_number;
252b5132 7269
43234a1e
L		 7270 if (i.types[n].bitfield.vec_disp8)
7271 val >>= i.memshift;
7272 val = offset_in_range (val, size);
29b0f896
AM		 7273 p = frag_more (size);
7274 md_number_to_chars (p, val, size);
7275 }
7276 else
7277 {
f86103b7 7278 enum bfd_reloc_code_real reloc_type;
e205caa7 7279 int size = disp_size (n);
40fb9820 7280 int sign = i.types[n].bitfield.disp32s;
29b0f896 7281 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7282 fixS *fixP;
29b0f896 7283
e205caa7 7284 /* We can't have 8 bit displacement here. */
9c2799c2 7285 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7286
29b0f896
AM		 7287 /* The PC relative address is computed relative
7288 to the instruction boundary, so in case immediate
7289 fields follows, we need to adjust the value. */
7290 if (pcrel && i.imm_operands)
7291 {
29b0f896 7292 unsigned int n1;
e205caa7 7293 int sz = 0;
252b5132 7294
29b0f896 7295 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7296 if (operand_type_check (i.types[n1], imm))
252b5132 7297 {
e205caa7
L		 7298 /* Only one immediate is allowed for PC
7299 relative address. */
9c2799c2 7300 gas_assert (sz == 0);
e205caa7
L		 7301 sz = imm_size (n1);
7302 i.op[n].disps->X_add_number -= sz;
252b5132 7303 }
29b0f896 7304 /* We should find the immediate. */
9c2799c2 7305 gas_assert (sz != 0);
29b0f896 7306 }
520dc8e8 7307
29b0f896 7308 p = frag_more (size);
d258b828 7309 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7310 if (GOT_symbol
2bbd9c25 7311 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7312 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7313 || reloc_type == BFD_RELOC_X86_64_32S
7314 || (reloc_type == BFD_RELOC_64
7315 && object_64bit))
d6ab8113
JB		 7316 && (i.op[n].disps->X_op == O_symbol
7317 || (i.op[n].disps->X_op == O_add
7318 && ((symbol_get_value_expression
7319 (i.op[n].disps->X_op_symbol)->X_op)
7320 == O_subtract))))
7321 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7322 {
7323 offsetT add;
7324
7325 if (insn_start_frag == frag_now)
7326 add = (p - frag_now->fr_literal) - insn_start_off;
7327 else
7328 {
7329 fragS *fr;
7330
7331 add = insn_start_frag->fr_fix - insn_start_off;
7332 for (fr = insn_start_frag->fr_next;
7333 fr && fr != frag_now; fr = fr->fr_next)
7334 add += fr->fr_fix;
7335 add += p - frag_now->fr_literal;
7336 }
7337
4fa24527 7338 if (!object_64bit)
7b81dfbb
AJ		 7339 {
7340 reloc_type = BFD_RELOC_386_GOTPC;
7341 i.op[n].imms->X_add_number += add;
7342 }
7343 else if (reloc_type == BFD_RELOC_64)
7344 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7345 else
7b81dfbb
AJ		 7346 /* Don't do the adjustment for x86-64, as there
7347 the pcrel addressing is relative to the _next_
7348 insn, and that is taken care of in other code. */
d6ab8113 7349 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7350 }
02a86693
L		 7351 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7352 size, i.op[n].disps, pcrel,
7353 reloc_type);
7354 /* Check for "call/jmp *mem", "mov mem, %reg",
7355 "test %reg, mem" and "binop mem, %reg" where binop
7356 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7357 instructions. Always generate R_386_GOT32X for
7358 "sym*GOT" operand in 32-bit mode. */
7359 if ((generate_relax_relocations
7360 || (!object_64bit
7361 && i.rm.mode == 0
7362 && i.rm.regmem == 5))
7363 && (i.rm.mode == 2
7364 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7365 && ((i.operands == 1
7366 && i.tm.base_opcode == 0xff
7367 && (i.rm.reg == 2 || i.rm.reg == 4))
7368 || (i.operands == 2
7369 && (i.tm.base_opcode == 0x8b
7370 || i.tm.base_opcode == 0x85
7371 || (i.tm.base_opcode & 0xc7) == 0x03))))
7372 {
7373 if (object_64bit)
7374 {
7375 fixP->fx_tcbit = i.rex != 0;
7376 if (i.base_reg
7377 && (i.base_reg->reg_num == RegRip
7378 || i.base_reg->reg_num == RegEip))
7379 fixP->fx_tcbit2 = 1;
7380 }
7381 else
7382 fixP->fx_tcbit2 = 1;
7383 }
29b0f896
AM		 7384 }
7385 }
7386 }
7387}
252b5132 7388
29b0f896 7389static void
64e74474 7390output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7391{
7392 char *p;
7393 unsigned int n;
252b5132 7394
29b0f896
AM		 7395 for (n = 0; n < i.operands; n++)
7396 {
43234a1e
L		 7397 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7398 if (i.rounding && (int) n == i.rounding->operand)
7399 continue;
7400
40fb9820 7401 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7402 {
7403 if (i.op[n].imms->X_op == O_constant)
7404 {
e205caa7 7405 int size = imm_size (n);
29b0f896 7406 offsetT val;
b4cac588 7407
29b0f896
AM		 7408 val = offset_in_range (i.op[n].imms->X_add_number,
7409 size);
7410 p = frag_more (size);
7411 md_number_to_chars (p, val, size);
7412 }
7413 else
7414 {
7415 /* Not absolute_section.
7416 Need a 32-bit fixup (don't support 8bit
7417 non-absolute imms). Try to support other
7418 sizes ... */
f86103b7 7419 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7420 int size = imm_size (n);
7421 int sign;
29b0f896 7422
40fb9820 7423 if (i.types[n].bitfield.imm32s
a7d61044 7424 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7425 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7426 sign = 1;
e205caa7
L		 7427 else
7428 sign = 0;
520dc8e8 7429
29b0f896 7430 p = frag_more (size);
d258b828 7431 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7432
2bbd9c25
JJ		 7433 /* This is tough to explain. We end up with this one if we
7434 * have operands that look like
7435 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7436 * obtain the absolute address of the GOT, and it is strongly
7437 * preferable from a performance point of view to avoid using
7438 * a runtime relocation for this. The actual sequence of
7439 * instructions often look something like:
7440 *
7441 * call .L66
7442 * .L66:
7443 * popl %ebx
7444 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7445 *
7446 * The call and pop essentially return the absolute address
7447 * of the label .L66 and store it in %ebx. The linker itself
7448 * will ultimately change the first operand of the addl so
7449 * that %ebx points to the GOT, but to keep things simple, the
7450 * .o file must have this operand set so that it generates not
7451 * the absolute address of .L66, but the absolute address of
7452 * itself. This allows the linker itself simply treat a GOTPC
7453 * relocation as asking for a pcrel offset to the GOT to be
7454 * added in, and the addend of the relocation is stored in the
7455 * operand field for the instruction itself.
7456 *
7457 * Our job here is to fix the operand so that it would add
7458 * the correct offset so that %ebx would point to itself. The
7459 * thing that is tricky is that .-.L66 will point to the
7460 * beginning of the instruction, so we need to further modify
7461 * the operand so that it will point to itself. There are
7462 * other cases where you have something like:
7463 *
7464 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7465 *
7466 * and here no correction would be required. Internally in
7467 * the assembler we treat operands of this form as not being
7468 * pcrel since the '.' is explicitly mentioned, and I wonder
7469 * whether it would simplify matters to do it this way. Who
7470 * knows. In earlier versions of the PIC patches, the
7471 * pcrel_adjust field was used to store the correction, but
7472 * since the expression is not pcrel, I felt it would be
7473 * confusing to do it this way. */
7474
d6ab8113 7475 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7476 || reloc_type == BFD_RELOC_X86_64_32S
7477 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7478 && GOT_symbol
7479 && GOT_symbol == i.op[n].imms->X_add_symbol
7480 && (i.op[n].imms->X_op == O_symbol
7481 || (i.op[n].imms->X_op == O_add
7482 && ((symbol_get_value_expression
7483 (i.op[n].imms->X_op_symbol)->X_op)
7484 == O_subtract))))
7485 {
2bbd9c25
JJ		 7486 offsetT add;
7487
7488 if (insn_start_frag == frag_now)
7489 add = (p - frag_now->fr_literal) - insn_start_off;
7490 else
7491 {
7492 fragS *fr;
7493
7494 add = insn_start_frag->fr_fix - insn_start_off;
7495 for (fr = insn_start_frag->fr_next;
7496 fr && fr != frag_now; fr = fr->fr_next)
7497 add += fr->fr_fix;
7498 add += p - frag_now->fr_literal;
7499 }
7500
4fa24527 7501 if (!object_64bit)
d6ab8113 7502 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7503 else if (size == 4)
d6ab8113 7504 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7505 else if (size == 8)
7506 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7507 i.op[n].imms->X_add_number += add;
29b0f896 7508 }
29b0f896
AM		 7509 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7510 i.op[n].imms, 0, reloc_type);
7511 }
7512 }
7513 }
252b5132
RH		 7514}
7515\f
d182319b
JB		 7516/* x86_cons_fix_new is called via the expression parsing code when a
7517 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7518static int cons_sign = -1;
7519
7520void
e3bb37b5 7521x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7522 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7523{
d258b828 7524 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7525
7526#ifdef TE_PE
7527 if (exp->X_op == O_secrel)
7528 {
7529 exp->X_op = O_symbol;
7530 r = BFD_RELOC_32_SECREL;
7531 }
7532#endif
7533
7534 fix_new_exp (frag, off, len, exp, 0, r);
7535}
7536
357d1bd8
L		 7537/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7538 purpose of the `.dc.a' internal pseudo-op. */
7539
7540int
7541x86_address_bytes (void)
7542{
7543 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7544 return 4;
7545 return stdoutput->arch_info->bits_per_address / 8;
7546}
7547
d382c579
TG		 7548#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7549 || defined (LEX_AT)
d258b828 7550# define lex_got(reloc, adjust, types) NULL
718ddfc0 7551#else
f3c180ae
AM		 7552/* Parse operands of the form
7553 <symbol>@GOTOFF+<nnn>
7554 and similar .plt or .got references.
7555
7556 If we find one, set up the correct relocation in RELOC and copy the
7557 input string, minus the `@GOTOFF' into a malloc'd buffer for
7558 parsing by the calling routine. Return this buffer, and if ADJUST
7559 is non-null set it to the length of the string we removed from the
7560 input line. Otherwise return NULL. */
7561static char *
91d6fa6a 7562lex_got (enum bfd_reloc_code_real *rel,
64e74474 7563 int *adjust,
d258b828 7564 i386_operand_type *types)
f3c180ae 7565{
7b81dfbb
AJ		 7566 /* Some of the relocations depend on the size of what field is to
7567 be relocated. But in our callers i386_immediate and i386_displacement
7568 we don't yet know the operand size (this will be set by insn
7569 matching). Hence we record the word32 relocation here,
7570 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7571 static const struct {
7572 const char *str;
cff8d58a 7573 int len;
4fa24527 7574 const enum bfd_reloc_code_real rel[2];
40fb9820 7575 const i386_operand_type types64;
f3c180ae 7576 } gotrel[] = {
8ce3d284 7577#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7578 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7579 BFD_RELOC_SIZE32 },
7580 OPERAND_TYPE_IMM32_64 },
8ce3d284 7581#endif
cff8d58a
L		 7582 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7583 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7584 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7585 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7586 BFD_RELOC_X86_64_PLT32 },
40fb9820 7587 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7588 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7589 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7590 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7591 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7592 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7593 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7594 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7595 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7596 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7597 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7598 BFD_RELOC_X86_64_TLSGD },
40fb9820 7599 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7600 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7601 _dummy_first_bfd_reloc_code_real },
40fb9820 7602 OPERAND_TYPE_NONE },
cff8d58a
L		 7603 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7604 BFD_RELOC_X86_64_TLSLD },
40fb9820 7605 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7606 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7607 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7608 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7609 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7610 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7611 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7612 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7613 _dummy_first_bfd_reloc_code_real },
40fb9820 7614 OPERAND_TYPE_NONE },
cff8d58a
L		 7615 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7616 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7617 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7618 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7619 _dummy_first_bfd_reloc_code_real },
40fb9820 7620 OPERAND_TYPE_NONE },
cff8d58a
L		 7621 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7622 _dummy_first_bfd_reloc_code_real },
40fb9820 7623 OPERAND_TYPE_NONE },
cff8d58a
L		 7624 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7625 BFD_RELOC_X86_64_GOT32 },
40fb9820 7626 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7627 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7628 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7629 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7630 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7631 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7632 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7633 };
7634 char *cp;
7635 unsigned int j;
7636
d382c579 7637#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7638 if (!IS_ELF)
7639 return NULL;
d382c579 7640#endif
718ddfc0 7641
f3c180ae 7642 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7643 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7644 return NULL;
7645
47465058 7646 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7647 {
cff8d58a 7648 int len = gotrel[j].len;
28f81592 7649 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7650 {
4fa24527 7651 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7652 {
28f81592
AM		 7653 int first, second;
7654 char *tmpbuf, *past_reloc;
f3c180ae 7655
91d6fa6a 7656 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7657
3956db08
JB		 7658 if (types)
7659 {
7660 if (flag_code != CODE_64BIT)
40fb9820
L		 7661 {
7662 types->bitfield.imm32 = 1;
7663 types->bitfield.disp32 = 1;
7664 }
3956db08
JB		 7665 else
7666 *types = gotrel[j].types64;
7667 }
7668
8fd4256d 7669 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7670 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7671
28f81592 7672 /* The length of the first part of our input line. */
f3c180ae 7673 first = cp - input_line_pointer;
28f81592
AM		 7674
7675 /* The second part goes from after the reloc token until
67c11a9b 7676 (and including) an end_of_line char or comma. */
28f81592 7677 past_reloc = cp + 1 + len;
67c11a9b
AM		 7678 cp = past_reloc;
7679 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7680 ++cp;
7681 second = cp + 1 - past_reloc;
28f81592
AM		 7682
7683 /* Allocate and copy string. The trailing NUL shouldn't
7684 be necessary, but be safe. */
add39d23 7685 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7686 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7687 if (second != 0 && *past_reloc != ' ')
7688 /* Replace the relocation token with ' ', so that
7689 errors like foo@GOTOFF1 will be detected. */
7690 tmpbuf[first++] = ' ';
af89796a
L		 7691 else
7692 /* Increment length by 1 if the relocation token is
7693 removed. */
7694 len++;
7695 if (adjust)
7696 *adjust = len;
0787a12d
AM		 7697 memcpy (tmpbuf + first, past_reloc, second);
7698 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7699 return tmpbuf;
7700 }
7701
4fa24527
JB		 7702 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7703 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7704 return NULL;
7705 }
7706 }
7707
7708 /* Might be a symbol version string. Don't as_bad here. */
7709 return NULL;
7710}
4e4f7c87 7711#endif
f3c180ae 7712
a988325c
NC		 7713#ifdef TE_PE
7714#ifdef lex_got
7715#undef lex_got
7716#endif
7717/* Parse operands of the form
7718 <symbol>@SECREL32+<nnn>
7719
7720 If we find one, set up the correct relocation in RELOC and copy the
7721 input string, minus the `@SECREL32' into a malloc'd buffer for
7722 parsing by the calling routine. Return this buffer, and if ADJUST
7723 is non-null set it to the length of the string we removed from the
34bca508
L		 7724 input line. Otherwise return NULL.
7725
a988325c
NC		 7726 This function is copied from the ELF version above adjusted for PE targets. */
7727
7728static char *
7729lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7730 int *adjust ATTRIBUTE_UNUSED,
d258b828 7731 i386_operand_type *types)
a988325c
NC		 7732{
7733 static const struct
7734 {
7735 const char *str;
7736 int len;
7737 const enum bfd_reloc_code_real rel[2];
7738 const i386_operand_type types64;
7739 }
7740 gotrel[] =
7741 {
7742 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7743 BFD_RELOC_32_SECREL },
7744 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7745 };
7746
7747 char *cp;
7748 unsigned j;
7749
7750 for (cp = input_line_pointer; *cp != '@'; cp++)
7751 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7752 return NULL;
7753
7754 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7755 {
7756 int len = gotrel[j].len;
7757
7758 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7759 {
7760 if (gotrel[j].rel[object_64bit] != 0)
7761 {
7762 int first, second;
7763 char *tmpbuf, *past_reloc;
7764
7765 *rel = gotrel[j].rel[object_64bit];
7766 if (adjust)
7767 *adjust = len;
7768
7769 if (types)
7770 {
7771 if (flag_code != CODE_64BIT)
7772 {
7773 types->bitfield.imm32 = 1;
7774 types->bitfield.disp32 = 1;
7775 }
7776 else
7777 *types = gotrel[j].types64;
7778 }
7779
7780 /* The length of the first part of our input line. */
7781 first = cp - input_line_pointer;
7782
7783 /* The second part goes from after the reloc token until
7784 (and including) an end_of_line char or comma. */
7785 past_reloc = cp + 1 + len;
7786 cp = past_reloc;
7787 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7788 ++cp;
7789 second = cp + 1 - past_reloc;
7790
7791 /* Allocate and copy string. The trailing NUL shouldn't
7792 be necessary, but be safe. */
add39d23 7793 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7794 memcpy (tmpbuf, input_line_pointer, first);
7795 if (second != 0 && *past_reloc != ' ')
7796 /* Replace the relocation token with ' ', so that
7797 errors like foo@SECLREL321 will be detected. */
7798 tmpbuf[first++] = ' ';
7799 memcpy (tmpbuf + first, past_reloc, second);
7800 tmpbuf[first + second] = '\0';
7801 return tmpbuf;
7802 }
7803
7804 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7805 gotrel[j].str, 1 << (5 + object_64bit));
7806 return NULL;
7807 }
7808 }
7809
7810 /* Might be a symbol version string. Don't as_bad here. */
7811 return NULL;
7812}
7813
7814#endif /* TE_PE */
7815
62ebcb5c 7816bfd_reloc_code_real_type
e3bb37b5 7817x86_cons (expressionS *exp, int size)
f3c180ae 7818{
62ebcb5c
AM		 7819 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7820
ee86248c
JB		 7821 intel_syntax = -intel_syntax;
7822
3c7b9c2c 7823 exp->X_md = 0;
4fa24527 7824 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7825 {
7826 /* Handle @GOTOFF and the like in an expression. */
7827 char *save;
7828 char *gotfree_input_line;
4a57f2cf 7829 int adjust = 0;
f3c180ae
AM		 7830
7831 save = input_line_pointer;
d258b828 7832 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7833 if (gotfree_input_line)
7834 input_line_pointer = gotfree_input_line;
7835
7836 expression (exp);
7837
7838 if (gotfree_input_line)
7839 {
7840 /* expression () has merrily parsed up to the end of line,
7841 or a comma - in the wrong buffer. Transfer how far
7842 input_line_pointer has moved to the right buffer. */
7843 input_line_pointer = (save
7844 + (input_line_pointer - gotfree_input_line)
7845 + adjust);
7846 free (gotfree_input_line);
3992d3b7
AM		 7847 if (exp->X_op == O_constant
7848 || exp->X_op == O_absent
7849 || exp->X_op == O_illegal
0398aac5 7850 || exp->X_op == O_register
3992d3b7
AM		 7851 || exp->X_op == O_big)
7852 {
7853 char c = *input_line_pointer;
7854 *input_line_pointer = 0;
7855 as_bad (_("missing or invalid expression `%s'"), save);
7856 *input_line_pointer = c;
7857 }
f3c180ae
AM		 7858 }
7859 }
7860 else
7861 expression (exp);
ee86248c
JB		 7862
7863 intel_syntax = -intel_syntax;
7864
7865 if (intel_syntax)
7866 i386_intel_simplify (exp);
62ebcb5c
AM		 7867
7868 return got_reloc;
f3c180ae 7869}
f3c180ae 7870
9f32dd5b
L		 7871static void
7872signed_cons (int size)
6482c264 7873{
d182319b
JB		 7874 if (flag_code == CODE_64BIT)
7875 cons_sign = 1;
7876 cons (size);
7877 cons_sign = -1;
6482c264
NC		 7878}
7879
d182319b 7880#ifdef TE_PE
6482c264 7881static void
7016a5d5 7882pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7883{
7884 expressionS exp;
7885
7886 do
7887 {
7888 expression (&exp);
7889 if (exp.X_op == O_symbol)
7890 exp.X_op = O_secrel;
7891
7892 emit_expr (&exp, 4);
7893 }
7894 while (*input_line_pointer++ == ',');
7895
7896 input_line_pointer--;
7897 demand_empty_rest_of_line ();
7898}
6482c264
NC		 7899#endif
7900
43234a1e
L		 7901/* Handle Vector operations. */
7902
7903static char *
7904check_VecOperations (char *op_string, char *op_end)
7905{
7906 const reg_entry *mask;
7907 const char *saved;
7908 char *end_op;
7909
7910 while (*op_string
7911 && (op_end == NULL || op_string < op_end))
7912 {
7913 saved = op_string;
7914 if (*op_string == '{')
7915 {
7916 op_string++;
7917
7918 /* Check broadcasts. */
7919 if (strncmp (op_string, "1to", 3) == 0)
7920 {
7921 int bcst_type;
7922
7923 if (i.broadcast)
7924 goto duplicated_vec_op;
7925
7926 op_string += 3;
7927 if (*op_string == '8')
7928 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7929 else if (*op_string == '4')
7930 bcst_type = BROADCAST_1TO4;
7931 else if (*op_string == '2')
7932 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7933 else if (*op_string == '1'
7934 && *(op_string+1) == '6')
7935 {
7936 bcst_type = BROADCAST_1TO16;
7937 op_string++;
7938 }
7939 else
7940 {
7941 as_bad (_("Unsupported broadcast: `%s'"), saved);
7942 return NULL;
7943 }
7944 op_string++;
7945
7946 broadcast_op.type = bcst_type;
7947 broadcast_op.operand = this_operand;
7948 i.broadcast = &broadcast_op;
7949 }
7950 /* Check masking operation. */
7951 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7952 {
7953 /* k0 can't be used for write mask. */
7954 if (mask->reg_num == 0)
7955 {
7956 as_bad (_("`%s' can't be used for write mask"),
7957 op_string);
7958 return NULL;
7959 }
7960
7961 if (!i.mask)
7962 {
7963 mask_op.mask = mask;
7964 mask_op.zeroing = 0;
7965 mask_op.operand = this_operand;
7966 i.mask = &mask_op;
7967 }
7968 else
7969 {
7970 if (i.mask->mask)
7971 goto duplicated_vec_op;
7972
7973 i.mask->mask = mask;
7974
7975 /* Only "{z}" is allowed here. No need to check
7976 zeroing mask explicitly. */
7977 if (i.mask->operand != this_operand)
7978 {
7979 as_bad (_("invalid write mask `%s'"), saved);
7980 return NULL;
7981 }
7982 }
7983
7984 op_string = end_op;
7985 }
7986 /* Check zeroing-flag for masking operation. */
7987 else if (*op_string == 'z')
7988 {
7989 if (!i.mask)
7990 {
7991 mask_op.mask = NULL;
7992 mask_op.zeroing = 1;
7993 mask_op.operand = this_operand;
7994 i.mask = &mask_op;
7995 }
7996 else
7997 {
7998 if (i.mask->zeroing)
7999 {
8000 duplicated_vec_op:
8001 as_bad (_("duplicated `%s'"), saved);
8002 return NULL;
8003 }
8004
8005 i.mask->zeroing = 1;
8006
8007 /* Only "{%k}" is allowed here. No need to check mask
8008 register explicitly. */
8009 if (i.mask->operand != this_operand)
8010 {
8011 as_bad (_("invalid zeroing-masking `%s'"),
8012 saved);
8013 return NULL;
8014 }
8015 }
8016
8017 op_string++;
8018 }
8019 else
8020 goto unknown_vec_op;
8021
8022 if (*op_string != '}')
8023 {
8024 as_bad (_("missing `}' in `%s'"), saved);
8025 return NULL;
8026 }
8027 op_string++;
8028 continue;
8029 }
8030 unknown_vec_op:
8031 /* We don't know this one. */
8032 as_bad (_("unknown vector operation: `%s'"), saved);
8033 return NULL;
8034 }
8035
8036 return op_string;
8037}
8038
252b5132 8039static int
70e41ade 8040i386_immediate (char *imm_start)
252b5132
RH		 8041{
8042 char *save_input_line_pointer;
f3c180ae 8043 char *gotfree_input_line;
252b5132 8044 segT exp_seg = 0;
47926f60 8045 expressionS *exp;
40fb9820
L		 8046 i386_operand_type types;
8047
0dfbf9d7 8048 operand_type_set (&types, ~0);
252b5132
RH		 8049
8050 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8051 {
31b2323c
L		 8052 as_bad (_("at most %d immediate operands are allowed"),
8053 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8054 return 0;
8055 }
8056
8057 exp = &im_expressions[i.imm_operands++];
520dc8e8 8058 i.op[this_operand].imms = exp;
252b5132
RH		 8059
8060 if (is_space_char (*imm_start))
8061 ++imm_start;
8062
8063 save_input_line_pointer = input_line_pointer;
8064 input_line_pointer = imm_start;
8065
d258b828 8066 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8067 if (gotfree_input_line)
8068 input_line_pointer = gotfree_input_line;
252b5132
RH		 8069
8070 exp_seg = expression (exp);
8071
83183c0c 8072 SKIP_WHITESPACE ();
43234a1e
L		 8073
8074 /* Handle vector operations. */
8075 if (*input_line_pointer == '{')
8076 {
8077 input_line_pointer = check_VecOperations (input_line_pointer,
8078 NULL);
8079 if (input_line_pointer == NULL)
8080 return 0;
8081 }
8082
252b5132 8083 if (*input_line_pointer)
f3c180ae 8084 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8085
8086 input_line_pointer = save_input_line_pointer;
f3c180ae 8087 if (gotfree_input_line)
ee86248c
JB		 8088 {
8089 free (gotfree_input_line);
8090
8091 if (exp->X_op == O_constant || exp->X_op == O_register)
8092 exp->X_op = O_illegal;
8093 }
8094
8095 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8096}
252b5132 8097
ee86248c
JB		 8098static int
8099i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8100 i386_operand_type types, const char *imm_start)
8101{
8102 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8103 {
313c53d1
L		 8104 if (imm_start)
8105 as_bad (_("missing or invalid immediate expression `%s'"),
8106 imm_start);
3992d3b7 8107 return 0;
252b5132 8108 }
3e73aa7c 8109 else if (exp->X_op == O_constant)
252b5132 8110 {
47926f60 8111 /* Size it properly later. */
40fb9820 8112 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8113 /* If not 64bit, sign extend val. */
8114 if (flag_code != CODE_64BIT
4eed87de
AM		 8115 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8116 exp->X_add_number
8117 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8118 }
4c63da97 8119#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8120 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8121 && exp_seg != absolute_section
47926f60 8122 && exp_seg != text_section
24eab124
AM		 8123 && exp_seg != data_section
8124 && exp_seg != bss_section
8125 && exp_seg != undefined_section
f86103b7 8126 && !bfd_is_com_section (exp_seg))
252b5132 8127 {
d0b47220 8128 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8129 return 0;
8130 }
8131#endif
a841bdf5 8132 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8133 {
313c53d1
L		 8134 if (imm_start)
8135 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8136 return 0;
8137 }
252b5132
RH		 8138 else
8139 {
8140 /* This is an address. The size of the address will be
24eab124 8141 determined later, depending on destination register,
3e73aa7c 8142 suffix, or the default for the section. */
40fb9820
L		 8143 i.types[this_operand].bitfield.imm8 = 1;
8144 i.types[this_operand].bitfield.imm16 = 1;
8145 i.types[this_operand].bitfield.imm32 = 1;
8146 i.types[this_operand].bitfield.imm32s = 1;
8147 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8148 i.types[this_operand] = operand_type_and (i.types[this_operand],
8149 types);
252b5132
RH		 8150 }
8151
8152 return 1;
8153}
8154
551c1ca1 8155static char *
e3bb37b5 8156i386_scale (char *scale)
252b5132 8157{
551c1ca1
AM		 8158 offsetT val;
8159 char *save = input_line_pointer;
252b5132 8160
551c1ca1
AM		 8161 input_line_pointer = scale;
8162 val = get_absolute_expression ();
8163
8164 switch (val)
252b5132 8165 {
551c1ca1 8166 case 1:
252b5132
RH		 8167 i.log2_scale_factor = 0;
8168 break;
551c1ca1 8169 case 2:
252b5132
RH		 8170 i.log2_scale_factor = 1;
8171 break;
551c1ca1 8172 case 4:
252b5132
RH		 8173 i.log2_scale_factor = 2;
8174 break;
551c1ca1 8175 case 8:
252b5132
RH		 8176 i.log2_scale_factor = 3;
8177 break;
8178 default:
a724f0f4
JB		 8179 {
8180 char sep = *input_line_pointer;
8181
8182 *input_line_pointer = '\0';
8183 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8184 scale);
8185 *input_line_pointer = sep;
8186 input_line_pointer = save;
8187 return NULL;
8188 }
252b5132 8189 }
29b0f896 8190 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8191 {
8192 as_warn (_("scale factor of %d without an index register"),
24eab124 8193 1 << i.log2_scale_factor);
252b5132 8194 i.log2_scale_factor = 0;
252b5132 8195 }
551c1ca1
AM		 8196 scale = input_line_pointer;
8197 input_line_pointer = save;
8198 return scale;
252b5132
RH		 8199}
8200
252b5132 8201static int
e3bb37b5 8202i386_displacement (char *disp_start, char *disp_end)
252b5132 8203{
29b0f896 8204 expressionS *exp;
252b5132
RH		 8205 segT exp_seg = 0;
8206 char *save_input_line_pointer;
f3c180ae 8207 char *gotfree_input_line;
40fb9820
L		 8208 int override;
8209 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8210 int ret;
252b5132 8211
31b2323c
L		 8212 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8213 {
8214 as_bad (_("at most %d displacement operands are allowed"),
8215 MAX_MEMORY_OPERANDS);
8216 return 0;
8217 }
8218
0dfbf9d7 8219 operand_type_set (&bigdisp, 0);
40fb9820
L		 8220 if ((i.types[this_operand].bitfield.jumpabsolute)
8221 || (!current_templates->start->opcode_modifier.jump
8222 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8223 {
40fb9820 8224 bigdisp.bitfield.disp32 = 1;
e05278af 8225 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8226 if (flag_code == CODE_64BIT)
8227 {
8228 if (!override)
8229 {
8230 bigdisp.bitfield.disp32s = 1;
8231 bigdisp.bitfield.disp64 = 1;
8232 }
8233 }
8234 else if ((flag_code == CODE_16BIT) ^ override)
8235 {
8236 bigdisp.bitfield.disp32 = 0;
8237 bigdisp.bitfield.disp16 = 1;
8238 }
e05278af
JB		 8239 }
8240 else
8241 {
8242 /* For PC-relative branches, the width of the displacement
8243 is dependent upon data size, not address size. */
e05278af 8244 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8245 if (flag_code == CODE_64BIT)
8246 {
8247 if (override || i.suffix == WORD_MNEM_SUFFIX)
8248 bigdisp.bitfield.disp16 = 1;
8249 else
8250 {
8251 bigdisp.bitfield.disp32 = 1;
8252 bigdisp.bitfield.disp32s = 1;
8253 }
8254 }
8255 else
e05278af
JB		 8256 {
8257 if (!override)
8258 override = (i.suffix == (flag_code != CODE_16BIT
8259 ? WORD_MNEM_SUFFIX
8260 : LONG_MNEM_SUFFIX));
40fb9820
L		 8261 bigdisp.bitfield.disp32 = 1;
8262 if ((flag_code == CODE_16BIT) ^ override)
8263 {
8264 bigdisp.bitfield.disp32 = 0;
8265 bigdisp.bitfield.disp16 = 1;
8266 }
e05278af 8267 }
e05278af 8268 }
c6fb90c8
L		 8269 i.types[this_operand] = operand_type_or (i.types[this_operand],
8270 bigdisp);
252b5132
RH		 8271
8272 exp = &disp_expressions[i.disp_operands];
520dc8e8 8273 i.op[this_operand].disps = exp;
252b5132
RH		 8274 i.disp_operands++;
8275 save_input_line_pointer = input_line_pointer;
8276 input_line_pointer = disp_start;
8277 END_STRING_AND_SAVE (disp_end);
8278
8279#ifndef GCC_ASM_O_HACK
8280#define GCC_ASM_O_HACK 0
8281#endif
8282#if GCC_ASM_O_HACK
8283 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8284 if (i.types[this_operand].bitfield.baseIndex
24eab124 8285 && displacement_string_end[-1] == '+')
252b5132
RH		 8286 {
8287 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8288 constraint within gcc asm statements.
8289 For instance:
8290
8291 #define _set_tssldt_desc(n,addr,limit,type) \
8292 __asm__ __volatile__ ( \
8293 "movw %w2,%0\n\t" \
8294 "movw %w1,2+%0\n\t" \
8295 "rorl $16,%1\n\t" \
8296 "movb %b1,4+%0\n\t" \
8297 "movb %4,5+%0\n\t" \
8298 "movb $0,6+%0\n\t" \
8299 "movb %h1,7+%0\n\t" \
8300 "rorl $16,%1" \
8301 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8302
8303 This works great except that the output assembler ends
8304 up looking a bit weird if it turns out that there is
8305 no offset. You end up producing code that looks like:
8306
8307 #APP
8308 movw $235,(%eax)
8309 movw %dx,2+(%eax)
8310 rorl $16,%edx
8311 movb %dl,4+(%eax)
8312 movb $137,5+(%eax)
8313 movb $0,6+(%eax)
8314 movb %dh,7+(%eax)
8315 rorl $16,%edx
8316 #NO_APP
8317
47926f60 8318 So here we provide the missing zero. */
24eab124
AM		 8319
8320 *displacement_string_end = '0';
252b5132
RH		 8321 }
8322#endif
d258b828 8323 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8324 if (gotfree_input_line)
8325 input_line_pointer = gotfree_input_line;
252b5132 8326
24eab124 8327 exp_seg = expression (exp);
252b5132 8328
636c26b0
AM		 8329 SKIP_WHITESPACE ();
8330 if (*input_line_pointer)
8331 as_bad (_("junk `%s' after expression"), input_line_pointer);
8332#if GCC_ASM_O_HACK
8333 RESTORE_END_STRING (disp_end + 1);
8334#endif
636c26b0 8335 input_line_pointer = save_input_line_pointer;
636c26b0 8336 if (gotfree_input_line)
ee86248c
JB		 8337 {
8338 free (gotfree_input_line);
8339
8340 if (exp->X_op == O_constant || exp->X_op == O_register)
8341 exp->X_op = O_illegal;
8342 }
8343
8344 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8345
8346 RESTORE_END_STRING (disp_end);
8347
8348 return ret;
8349}
8350
8351static int
8352i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8353 i386_operand_type types, const char *disp_start)
8354{
8355 i386_operand_type bigdisp;
8356 int ret = 1;
636c26b0 8357
24eab124
AM		 8358 /* We do this to make sure that the section symbol is in
8359 the symbol table. We will ultimately change the relocation
47926f60 8360 to be relative to the beginning of the section. */
1ae12ab7 8361 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8362 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8363 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8364 {
636c26b0 8365 if (exp->X_op != O_symbol)
3992d3b7 8366 goto inv_disp;
636c26b0 8367
e5cb08ac 8368 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8369 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8370 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8371 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8372 exp->X_op = O_subtract;
8373 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8374 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8375 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8376 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8377 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8378 else
29b0f896 8379 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8380 }
252b5132 8381
3992d3b7
AM		 8382 else if (exp->X_op == O_absent
8383 || exp->X_op == O_illegal
ee86248c 8384 || exp->X_op == O_big)
2daf4fd8 8385 {
3992d3b7
AM		 8386 inv_disp:
8387 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8388 disp_start);
3992d3b7 8389 ret = 0;
2daf4fd8
AM		 8390 }
8391
0e1147d9
L		 8392 else if (flag_code == CODE_64BIT
8393 && !i.prefix[ADDR_PREFIX]
8394 && exp->X_op == O_constant)
8395 {
8396 /* Since displacement is signed extended to 64bit, don't allow
8397 disp32 and turn off disp32s if they are out of range. */
8398 i.types[this_operand].bitfield.disp32 = 0;
8399 if (!fits_in_signed_long (exp->X_add_number))
8400 {
8401 i.types[this_operand].bitfield.disp32s = 0;
8402 if (i.types[this_operand].bitfield.baseindex)
8403 {
8404 as_bad (_("0x%lx out range of signed 32bit displacement"),
8405 (long) exp->X_add_number);
8406 ret = 0;
8407 }
8408 }
8409 }
8410
4c63da97 8411#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8412 else if (exp->X_op != O_constant
8413 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8414 && exp_seg != absolute_section
8415 && exp_seg != text_section
8416 && exp_seg != data_section
8417 && exp_seg != bss_section
8418 && exp_seg != undefined_section
8419 && !bfd_is_com_section (exp_seg))
24eab124 8420 {
d0b47220 8421 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8422 ret = 0;
24eab124 8423 }
252b5132 8424#endif
3956db08 8425
40fb9820
L		 8426 /* Check if this is a displacement only operand. */
8427 bigdisp = i.types[this_operand];
8428 bigdisp.bitfield.disp8 = 0;
8429 bigdisp.bitfield.disp16 = 0;
8430 bigdisp.bitfield.disp32 = 0;
8431 bigdisp.bitfield.disp32s = 0;
8432 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8433 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8434 i.types[this_operand] = operand_type_and (i.types[this_operand],
8435 types);
3956db08 8436
3992d3b7 8437 return ret;
252b5132
RH		 8438}
8439
eecb386c 8440/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8441 Return 1 on success, 0 on a failure. */
8442
252b5132 8443static int
e3bb37b5 8444i386_index_check (const char *operand_string)
252b5132 8445{
fc0763e6 8446 const char *kind = "base/index";
be05d201
L		 8447 enum flag_code addr_mode;
8448
8449 if (i.prefix[ADDR_PREFIX])
8450 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8451 else
8452 {
8453 addr_mode = flag_code;
8454
24eab124 8455#if INFER_ADDR_PREFIX
be05d201
L		 8456 if (i.mem_operands == 0)
8457 {
8458 /* Infer address prefix from the first memory operand. */
8459 const reg_entry *addr_reg = i.base_reg;
8460
8461 if (addr_reg == NULL)
8462 addr_reg = i.index_reg;
eecb386c 8463
be05d201
L		 8464 if (addr_reg)
8465 {
8466 if (addr_reg->reg_num == RegEip
8467 || addr_reg->reg_num == RegEiz
8468 || addr_reg->reg_type.bitfield.reg32)
8469 addr_mode = CODE_32BIT;
8470 else if (flag_code != CODE_64BIT
8471 && addr_reg->reg_type.bitfield.reg16)
8472 addr_mode = CODE_16BIT;
8473
8474 if (addr_mode != flag_code)
8475 {
8476 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8477 i.prefixes += 1;
8478 /* Change the size of any displacement too. At most one
8479 of Disp16 or Disp32 is set.
8480 FIXME. There doesn't seem to be any real need for
8481 separate Disp16 and Disp32 flags. The same goes for
8482 Imm16 and Imm32. Removing them would probably clean
8483 up the code quite a lot. */
8484 if (flag_code != CODE_64BIT
8485 && (i.types[this_operand].bitfield.disp16
8486 || i.types[this_operand].bitfield.disp32))
8487 i.types[this_operand]
8488 = operand_type_xor (i.types[this_operand], disp16_32);
8489 }
8490 }
8491 }
24eab124 8492#endif
be05d201
L		 8493 }
8494
fc0763e6
JB		 8495 if (current_templates->start->opcode_modifier.isstring
8496 && !current_templates->start->opcode_modifier.immext
8497 && (current_templates->end[-1].opcode_modifier.isstring
8498 || i.mem_operands))
8499 {
8500 /* Memory operands of string insns are special in that they only allow
8501 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8502 const reg_entry *expected_reg;
8503 static const char *di_si[][2] =
8504 {
8505 { "esi", "edi" },
8506 { "si", "di" },
8507 { "rsi", "rdi" }
8508 };
8509 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8510
8511 kind = "string address";
8512
8513 if (current_templates->start->opcode_modifier.w)
8514 {
8515 i386_operand_type type = current_templates->end[-1].operand_types[0];
8516
8517 if (!type.bitfield.baseindex
8518 || ((!i.mem_operands != !intel_syntax)
8519 && current_templates->end[-1].operand_types[1]
8520 .bitfield.baseindex))
8521 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8522 expected_reg = hash_find (reg_hash,
8523 di_si[addr_mode][type.bitfield.esseg]);
8524
fc0763e6
JB		 8525 }
8526 else
be05d201 8527 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8528
be05d201
L		 8529 if (i.base_reg != expected_reg
8530 || i.index_reg
fc0763e6 8531 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8532 {
be05d201
L		 8533 /* The second memory operand must have the same size as
8534 the first one. */
8535 if (i.mem_operands
8536 && i.base_reg
8537 && !((addr_mode == CODE_64BIT
8538 && i.base_reg->reg_type.bitfield.reg64)
8539 || (addr_mode == CODE_32BIT
8540 ? i.base_reg->reg_type.bitfield.reg32
8541 : i.base_reg->reg_type.bitfield.reg16)))
8542 goto bad_address;
8543
fc0763e6
JB		 8544 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8545 operand_string,
8546 intel_syntax ? '[' : '(',
8547 register_prefix,
be05d201 8548 expected_reg->reg_name,
fc0763e6 8549 intel_syntax ? ']' : ')');
be05d201 8550 return 1;
fc0763e6 8551 }
be05d201
L		 8552 else
8553 return 1;
8554
8555bad_address:
8556 as_bad (_("`%s' is not a valid %s expression"),
8557 operand_string, kind);
8558 return 0;
3e73aa7c
JH		 8559 }
8560 else
8561 {
be05d201
L		 8562 if (addr_mode != CODE_16BIT)
8563 {
8564 /* 32-bit/64-bit checks. */
8565 if ((i.base_reg
8566 && (addr_mode == CODE_64BIT
8567 ? !i.base_reg->reg_type.bitfield.reg64
8568 : !i.base_reg->reg_type.bitfield.reg32)
8569 && (i.index_reg
8570 || (i.base_reg->reg_num
8571 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8572 || (i.index_reg
8573 && !i.index_reg->reg_type.bitfield.regxmm
8574 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8575 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8576 && ((addr_mode == CODE_64BIT
8577 ? !(i.index_reg->reg_type.bitfield.reg64
8578 || i.index_reg->reg_num == RegRiz)
8579 : !(i.index_reg->reg_type.bitfield.reg32
8580 || i.index_reg->reg_num == RegEiz))
8581 || !i.index_reg->reg_type.bitfield.baseindex)))
8582 goto bad_address;
8583 }
8584 else
3e73aa7c 8585 {
be05d201 8586 /* 16-bit checks. */
3e73aa7c 8587 if ((i.base_reg
40fb9820
L		 8588 && (!i.base_reg->reg_type.bitfield.reg16
8589 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8590 || (i.index_reg
40fb9820
L		 8591 && (!i.index_reg->reg_type.bitfield.reg16
8592 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8593 || !(i.base_reg
8594 && i.base_reg->reg_num < 6
8595 && i.index_reg->reg_num >= 6
8596 && i.log2_scale_factor == 0))))
be05d201 8597 goto bad_address;
3e73aa7c
JH		 8598 }
8599 }
be05d201 8600 return 1;
24eab124 8601}
252b5132 8602
43234a1e
L		 8603/* Handle vector immediates. */
8604
8605static int
8606RC_SAE_immediate (const char *imm_start)
8607{
8608 unsigned int match_found, j;
8609 const char *pstr = imm_start;
8610 expressionS *exp;
8611
8612 if (*pstr != '{')
8613 return 0;
8614
8615 pstr++;
8616 match_found = 0;
8617 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8618 {
8619 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8620 {
8621 if (!i.rounding)
8622 {
8623 rc_op.type = RC_NamesTable[j].type;
8624 rc_op.operand = this_operand;
8625 i.rounding = &rc_op;
8626 }
8627 else
8628 {
8629 as_bad (_("duplicated `%s'"), imm_start);
8630 return 0;
8631 }
8632 pstr += RC_NamesTable[j].len;
8633 match_found = 1;
8634 break;
8635 }
8636 }
8637 if (!match_found)
8638 return 0;
8639
8640 if (*pstr++ != '}')
8641 {
8642 as_bad (_("Missing '}': '%s'"), imm_start);
8643 return 0;
8644 }
8645 /* RC/SAE immediate string should contain nothing more. */;
8646 if (*pstr != 0)
8647 {
8648 as_bad (_("Junk after '}': '%s'"), imm_start);
8649 return 0;
8650 }
8651
8652 exp = &im_expressions[i.imm_operands++];
8653 i.op[this_operand].imms = exp;
8654
8655 exp->X_op = O_constant;
8656 exp->X_add_number = 0;
8657 exp->X_add_symbol = (symbolS *) 0;
8658 exp->X_op_symbol = (symbolS *) 0;
8659
8660 i.types[this_operand].bitfield.imm8 = 1;
8661 return 1;
8662}
8663
fc0763e6 8664/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8665 on error. */
252b5132 8666
252b5132 8667static int
a7619375 8668i386_att_operand (char *operand_string)
252b5132 8669{
af6bdddf
AM		 8670 const reg_entry *r;
8671 char *end_op;
24eab124 8672 char *op_string = operand_string;
252b5132 8673
24eab124 8674 if (is_space_char (*op_string))
252b5132
RH		 8675 ++op_string;
8676
24eab124 8677 /* We check for an absolute prefix (differentiating,
47926f60 8678 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8679 if (*op_string == ABSOLUTE_PREFIX)
8680 {
8681 ++op_string;
8682 if (is_space_char (*op_string))
8683 ++op_string;
40fb9820 8684 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8685 }
252b5132 8686
47926f60 8687 /* Check if operand is a register. */
4d1bb795 8688 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8689 {
40fb9820
L		 8690 i386_operand_type temp;
8691
24eab124
AM		 8692 /* Check for a segment override by searching for ':' after a
8693 segment register. */
8694 op_string = end_op;
8695 if (is_space_char (*op_string))
8696 ++op_string;
40fb9820
L		 8697 if (*op_string == ':'
8698 && (r->reg_type.bitfield.sreg2
8699 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8700 {
8701 switch (r->reg_num)
8702 {
8703 case 0:
8704 i.seg[i.mem_operands] = &es;
8705 break;
8706 case 1:
8707 i.seg[i.mem_operands] = &cs;
8708 break;
8709 case 2:
8710 i.seg[i.mem_operands] = &ss;
8711 break;
8712 case 3:
8713 i.seg[i.mem_operands] = &ds;
8714 break;
8715 case 4:
8716 i.seg[i.mem_operands] = &fs;
8717 break;
8718 case 5:
8719 i.seg[i.mem_operands] = &gs;
8720 break;
8721 }
252b5132 8722
24eab124 8723 /* Skip the ':' and whitespace. */
252b5132
RH		 8724 ++op_string;
8725 if (is_space_char (*op_string))
24eab124 8726 ++op_string;
252b5132 8727
24eab124
AM		 8728 if (!is_digit_char (*op_string)
8729 && !is_identifier_char (*op_string)
8730 && *op_string != '('
8731 && *op_string != ABSOLUTE_PREFIX)
8732 {
8733 as_bad (_("bad memory operand `%s'"), op_string);
8734 return 0;
8735 }
47926f60 8736 /* Handle case of %es:*foo. */
24eab124
AM		 8737 if (*op_string == ABSOLUTE_PREFIX)
8738 {
8739 ++op_string;
8740 if (is_space_char (*op_string))
8741 ++op_string;
40fb9820 8742 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8743 }
8744 goto do_memory_reference;
8745 }
43234a1e
L		 8746
8747 /* Handle vector operations. */
8748 if (*op_string == '{')
8749 {
8750 op_string = check_VecOperations (op_string, NULL);
8751 if (op_string == NULL)
8752 return 0;
8753 }
8754
24eab124
AM		 8755 if (*op_string)
8756 {
d0b47220 8757 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8758 return 0;
8759 }
40fb9820
L		 8760 temp = r->reg_type;
8761 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8762 i.types[this_operand] = operand_type_or (i.types[this_operand],
8763 temp);
7d5e4556 8764 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8765 i.op[this_operand].regs = r;
24eab124
AM		 8766 i.reg_operands++;
8767 }
af6bdddf
AM		 8768 else if (*op_string == REGISTER_PREFIX)
8769 {
8770 as_bad (_("bad register name `%s'"), op_string);
8771 return 0;
8772 }
24eab124 8773 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8774 {
24eab124 8775 ++op_string;
40fb9820 8776 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8777 {
d0b47220 8778 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8779 return 0;
8780 }
8781 if (!i386_immediate (op_string))
8782 return 0;
8783 }
43234a1e
L		 8784 else if (RC_SAE_immediate (operand_string))
8785 {
8786 /* If it is a RC or SAE immediate, do nothing. */
8787 ;
8788 }
24eab124
AM		 8789 else if (is_digit_char (*op_string)
8790 || is_identifier_char (*op_string)
d02603dc 8791 || *op_string == '"'
e5cb08ac 8792 || *op_string == '(')
24eab124 8793 {
47926f60 8794 /* This is a memory reference of some sort. */
af6bdddf 8795 char *base_string;
252b5132 8796
47926f60 8797 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8798 char *displacement_string_start;
8799 char *displacement_string_end;
43234a1e 8800 char *vop_start;
252b5132 8801
24eab124 8802 do_memory_reference:
24eab124 8803 if ((i.mem_operands == 1
40fb9820 8804 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8805 || i.mem_operands == 2)
8806 {
8807 as_bad (_("too many memory references for `%s'"),
8808 current_templates->start->name);
8809 return 0;
8810 }
252b5132 8811
24eab124
AM		 8812 /* Check for base index form. We detect the base index form by
8813 looking for an ')' at the end of the operand, searching
8814 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8815 after the '('. */
af6bdddf 8816 base_string = op_string + strlen (op_string);
c3332e24 8817
43234a1e
L		 8818 /* Handle vector operations. */
8819 vop_start = strchr (op_string, '{');
8820 if (vop_start && vop_start < base_string)
8821 {
8822 if (check_VecOperations (vop_start, base_string) == NULL)
8823 return 0;
8824 base_string = vop_start;
8825 }
8826
af6bdddf
AM		 8827 --base_string;
8828 if (is_space_char (*base_string))
8829 --base_string;
252b5132 8830
47926f60 8831 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8832 displacement_string_start = op_string;
8833 displacement_string_end = base_string + 1;
252b5132 8834
24eab124
AM		 8835 if (*base_string == ')')
8836 {
af6bdddf 8837 char *temp_string;
24eab124
AM		 8838 unsigned int parens_balanced = 1;
8839 /* We've already checked that the number of left & right ()'s are
47926f60 8840 equal, so this loop will not be infinite. */
24eab124
AM		 8841 do
8842 {
8843 base_string--;
8844 if (*base_string == ')')
8845 parens_balanced++;
8846 if (*base_string == '(')
8847 parens_balanced--;
8848 }
8849 while (parens_balanced);
c3332e24 8850
af6bdddf 8851 temp_string = base_string;
c3332e24 8852
24eab124 8853 /* Skip past '(' and whitespace. */
252b5132
RH		 8854 ++base_string;
8855 if (is_space_char (*base_string))
24eab124 8856 ++base_string;
252b5132 8857
af6bdddf 8858 if (*base_string == ','
4eed87de
AM		 8859 || ((i.base_reg = parse_register (base_string, &end_op))
8860 != NULL))
252b5132 8861 {
af6bdddf 8862 displacement_string_end = temp_string;
252b5132 8863
40fb9820 8864 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8865
af6bdddf 8866 if (i.base_reg)
24eab124 8867 {
24eab124
AM		 8868 base_string = end_op;
8869 if (is_space_char (*base_string))
8870 ++base_string;
af6bdddf
AM		 8871 }
8872
8873 /* There may be an index reg or scale factor here. */
8874 if (*base_string == ',')
8875 {
8876 ++base_string;
8877 if (is_space_char (*base_string))
8878 ++base_string;
8879
4eed87de
AM		 8880 if ((i.index_reg = parse_register (base_string, &end_op))
8881 != NULL)
24eab124 8882 {
af6bdddf 8883 base_string = end_op;
24eab124
AM		 8884 if (is_space_char (*base_string))
8885 ++base_string;
af6bdddf
AM		 8886 if (*base_string == ',')
8887 {
8888 ++base_string;
8889 if (is_space_char (*base_string))
8890 ++base_string;
8891 }
e5cb08ac 8892 else if (*base_string != ')')
af6bdddf 8893 {
4eed87de
AM		 8894 as_bad (_("expecting `,' or `)' "
8895 "after index register in `%s'"),
af6bdddf
AM		 8896 operand_string);
8897 return 0;
8898 }
24eab124 8899 }
af6bdddf 8900 else if (*base_string == REGISTER_PREFIX)
24eab124 8901 {
f76bf5e0
L		 8902 end_op = strchr (base_string, ',');
8903 if (end_op)
8904 *end_op = '\0';
af6bdddf 8905 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8906 return 0;
8907 }
252b5132 8908
47926f60 8909 /* Check for scale factor. */
551c1ca1 8910 if (*base_string != ')')
af6bdddf 8911 {
551c1ca1
AM		 8912 char *end_scale = i386_scale (base_string);
8913
8914 if (!end_scale)
af6bdddf 8915 return 0;
24eab124 8916
551c1ca1 8917 base_string = end_scale;
af6bdddf
AM		 8918 if (is_space_char (*base_string))
8919 ++base_string;
8920 if (*base_string != ')')
8921 {
4eed87de
AM		 8922 as_bad (_("expecting `)' "
8923 "after scale factor in `%s'"),
af6bdddf
AM		 8924 operand_string);
8925 return 0;
8926 }
8927 }
8928 else if (!i.index_reg)
24eab124 8929 {
4eed87de
AM		 8930 as_bad (_("expecting index register or scale factor "
8931 "after `,'; got '%c'"),
af6bdddf 8932 *base_string);
24eab124
AM		 8933 return 0;
8934 }
8935 }
af6bdddf 8936 else if (*base_string != ')')
24eab124 8937 {
4eed87de
AM		 8938 as_bad (_("expecting `,' or `)' "
8939 "after base register in `%s'"),
af6bdddf 8940 operand_string);
24eab124
AM		 8941 return 0;
8942 }
c3332e24 8943 }
af6bdddf 8944 else if (*base_string == REGISTER_PREFIX)
c3332e24 8945 {
f76bf5e0
L		 8946 end_op = strchr (base_string, ',');
8947 if (end_op)
8948 *end_op = '\0';
af6bdddf 8949 as_bad (_("bad register name `%s'"), base_string);
24eab124 8950 return 0;
c3332e24 8951 }
24eab124
AM		 8952 }
8953
8954 /* If there's an expression beginning the operand, parse it,
8955 assuming displacement_string_start and
8956 displacement_string_end are meaningful. */
8957 if (displacement_string_start != displacement_string_end)
8958 {
8959 if (!i386_displacement (displacement_string_start,
8960 displacement_string_end))
8961 return 0;
8962 }
8963
8964 /* Special case for (%dx) while doing input/output op. */
8965 if (i.base_reg
0dfbf9d7
L		 8966 && operand_type_equal (&i.base_reg->reg_type,
8967 &reg16_inoutportreg)
24eab124
AM		 8968 && i.index_reg == 0
8969 && i.log2_scale_factor == 0
8970 && i.seg[i.mem_operands] == 0
40fb9820 8971 && !operand_type_check (i.types[this_operand], disp))
24eab124 8972 {
65da13b5 8973 i.types[this_operand] = inoutportreg;
24eab124
AM		 8974 return 1;
8975 }
8976
eecb386c
AM		 8977 if (i386_index_check (operand_string) == 0)
8978 return 0;
5c07affc 8979 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8980 i.mem_operands++;
8981 }
8982 else
ce8a8b2f
AM		 8983 {
8984 /* It's not a memory operand; argh! */
24eab124
AM		 8985 as_bad (_("invalid char %s beginning operand %d `%s'"),
8986 output_invalid (*op_string),
8987 this_operand + 1,
8988 op_string);
8989 return 0;
8990 }
47926f60 8991 return 1; /* Normal return. */
252b5132
RH		 8992}
8993\f
fa94de6b
RM		 8994/* Calculate the maximum variable size (i.e., excluding fr_fix)
8995 that an rs_machine_dependent frag may reach. */
8996
8997unsigned int
8998i386_frag_max_var (fragS *frag)
8999{
9000 /* The only relaxable frags are for jumps.
9001 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9002 gas_assert (frag->fr_type == rs_machine_dependent);
9003 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9004}
9005
b084df0b
L		 9006#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9007static int
8dcea932 9008elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9009{
9010 /* STT_GNU_IFUNC symbol must go through PLT. */
9011 if ((symbol_get_bfdsym (fr_symbol)->flags
9012 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9013 return 0;
9014
9015 if (!S_IS_EXTERNAL (fr_symbol))
9016 /* Symbol may be weak or local. */
9017 return !S_IS_WEAK (fr_symbol);
9018
8dcea932
L		 9019 /* Global symbols with non-default visibility can't be preempted. */
9020 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9021 return 1;
9022
9023 if (fr_var != NO_RELOC)
9024 switch ((enum bfd_reloc_code_real) fr_var)
9025 {
9026 case BFD_RELOC_386_PLT32:
9027 case BFD_RELOC_X86_64_PLT32:
9028 /* Symbol with PLT relocatin may be preempted. */
9029 return 0;
9030 default:
9031 abort ();
9032 }
9033
b084df0b
L		 9034 /* Global symbols with default visibility in a shared library may be
9035 preempted by another definition. */
8dcea932 9036 return !shared;
b084df0b
L		 9037}
9038#endif
9039
ee7fcc42
AM		 9040/* md_estimate_size_before_relax()
9041
9042 Called just before relax() for rs_machine_dependent frags. The x86
9043 assembler uses these frags to handle variable size jump
9044 instructions.
9045
9046 Any symbol that is now undefined will not become defined.
9047 Return the correct fr_subtype in the frag.
9048 Return the initial "guess for variable size of frag" to caller.
9049 The guess is actually the growth beyond the fixed part. Whatever
9050 we do to grow the fixed or variable part contributes to our
9051 returned value. */
9052
252b5132 9053int
7016a5d5 9054md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9055{
252b5132 9056 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9057 check for un-relaxable symbols. On an ELF system, we can't relax
9058 an externally visible symbol, because it may be overridden by a
9059 shared library. */
9060 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9061#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9062 || (IS_ELF
8dcea932
L		 9063 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9064 fragP->fr_var))
fbeb56a4
DK		 9065#endif
9066#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9067 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9068 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9069#endif
9070 )
252b5132 9071 {
b98ef147
AM		 9072 /* Symbol is undefined in this segment, or we need to keep a
9073 reloc so that weak symbols can be overridden. */
9074 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9075 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9076 unsigned char *opcode;
9077 int old_fr_fix;
f6af82bd 9078
ee7fcc42 9079 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9080 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9081 else if (size == 2)
f6af82bd
AM		 9082 reloc_type = BFD_RELOC_16_PCREL;
9083 else
9084 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9085
ee7fcc42
AM		 9086 old_fr_fix = fragP->fr_fix;
9087 opcode = (unsigned char *) fragP->fr_opcode;
9088
fddf5b5b 9089 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9090 {
fddf5b5b
AM		 9091 case UNCOND_JUMP:
9092 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9093 opcode[0] = 0xe9;
252b5132 9094 fragP->fr_fix += size;
062cd5e7
AS		 9095 fix_new (fragP, old_fr_fix, size,
9096 fragP->fr_symbol,
9097 fragP->fr_offset, 1,
9098 reloc_type);
252b5132
RH		 9099 break;
9100
fddf5b5b 9101 case COND_JUMP86:
412167cb
AM		 9102 if (size == 2
9103 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9104 {
9105 /* Negate the condition, and branch past an
9106 unconditional jump. */
9107 opcode[0] ^= 1;
9108 opcode[1] = 3;
9109 /* Insert an unconditional jump. */
9110 opcode[2] = 0xe9;
9111 /* We added two extra opcode bytes, and have a two byte
9112 offset. */
9113 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9114 fix_new (fragP, old_fr_fix + 2, 2,
9115 fragP->fr_symbol,
9116 fragP->fr_offset, 1,
9117 reloc_type);
fddf5b5b
AM		 9118 break;
9119 }
9120 /* Fall through. */
9121
9122 case COND_JUMP:
412167cb
AM		 9123 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9124 {
3e02c1cc
AM		 9125 fixS *fixP;
9126
412167cb 9127 fragP->fr_fix += 1;
3e02c1cc
AM		 9128 fixP = fix_new (fragP, old_fr_fix, 1,
9129 fragP->fr_symbol,
9130 fragP->fr_offset, 1,
9131 BFD_RELOC_8_PCREL);
9132 fixP->fx_signed = 1;
412167cb
AM		 9133 break;
9134 }
93c2a809 9135
24eab124 9136 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9137 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9138 opcode[1] = opcode[0] + 0x10;
f6af82bd 9139 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9140 /* We've added an opcode byte. */
9141 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9142 fix_new (fragP, old_fr_fix + 1, size,
9143 fragP->fr_symbol,
9144 fragP->fr_offset, 1,
9145 reloc_type);
252b5132 9146 break;
fddf5b5b
AM		 9147
9148 default:
9149 BAD_CASE (fragP->fr_subtype);
9150 break;
252b5132
RH		 9151 }
9152 frag_wane (fragP);
ee7fcc42 9153 return fragP->fr_fix - old_fr_fix;
252b5132 9154 }
93c2a809 9155
93c2a809
AM		 9156 /* Guess size depending on current relax state. Initially the relax
9157 state will correspond to a short jump and we return 1, because
9158 the variable part of the frag (the branch offset) is one byte
9159 long. However, we can relax a section more than once and in that
9160 case we must either set fr_subtype back to the unrelaxed state,
9161 or return the value for the appropriate branch. */
9162 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9163}
9164
47926f60
KH		 9165/* Called after relax() is finished.
9166
9167 In: Address of frag.
9168 fr_type == rs_machine_dependent.
9169 fr_subtype is what the address relaxed to.
9170
9171 Out: Any fixSs and constants are set up.
9172 Caller will turn frag into a ".space 0". */
9173
252b5132 9174void
7016a5d5
TG		 9175md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9176 fragS *fragP)
252b5132 9177{
29b0f896 9178 unsigned char *opcode;
252b5132 9179 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9180 offsetT target_address;
9181 offsetT opcode_address;
252b5132 9182 unsigned int extension = 0;
847f7ad4 9183 offsetT displacement_from_opcode_start;
252b5132
RH		 9184
9185 opcode = (unsigned char *) fragP->fr_opcode;
9186
47926f60 9187 /* Address we want to reach in file space. */
252b5132 9188 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9189
47926f60 9190 /* Address opcode resides at in file space. */
252b5132
RH		 9191 opcode_address = fragP->fr_address + fragP->fr_fix;
9192
47926f60 9193 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9194 displacement_from_opcode_start = target_address - opcode_address;
9195
fddf5b5b 9196 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9197 {
47926f60
KH		 9198 /* Don't have to change opcode. */
9199 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9200 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9201 }
9202 else
9203 {
9204 if (no_cond_jump_promotion
9205 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9206 as_warn_where (fragP->fr_file, fragP->fr_line,
9207 _("long jump required"));
252b5132 9208
fddf5b5b
AM		 9209 switch (fragP->fr_subtype)
9210 {
9211 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9212 extension = 4; /* 1 opcode + 4 displacement */
9213 opcode[0] = 0xe9;
9214 where_to_put_displacement = &opcode[1];
9215 break;
252b5132 9216
fddf5b5b
AM		 9217 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9218 extension = 2; /* 1 opcode + 2 displacement */
9219 opcode[0] = 0xe9;
9220 where_to_put_displacement = &opcode[1];
9221 break;
252b5132 9222
fddf5b5b
AM		 9223 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9224 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9225 extension = 5; /* 2 opcode + 4 displacement */
9226 opcode[1] = opcode[0] + 0x10;
9227 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9228 where_to_put_displacement = &opcode[2];
9229 break;
252b5132 9230
fddf5b5b
AM		 9231 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9232 extension = 3; /* 2 opcode + 2 displacement */
9233 opcode[1] = opcode[0] + 0x10;
9234 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9235 where_to_put_displacement = &opcode[2];
9236 break;
252b5132 9237
fddf5b5b
AM		 9238 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9239 extension = 4;
9240 opcode[0] ^= 1;
9241 opcode[1] = 3;
9242 opcode[2] = 0xe9;
9243 where_to_put_displacement = &opcode[3];
9244 break;
9245
9246 default:
9247 BAD_CASE (fragP->fr_subtype);
9248 break;
9249 }
252b5132 9250 }
fddf5b5b 9251
7b81dfbb
AJ		 9252 /* If size if less then four we are sure that the operand fits,
9253 but if it's 4, then it could be that the displacement is larger
9254 then -/+ 2GB. */
9255 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9256 && object_64bit
9257 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9258 + ((addressT) 1 << 31))
9259 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9260 {
9261 as_bad_where (fragP->fr_file, fragP->fr_line,
9262 _("jump target out of range"));
9263 /* Make us emit 0. */
9264 displacement_from_opcode_start = extension;
9265 }
47926f60 9266 /* Now put displacement after opcode. */
252b5132
RH		 9267 md_number_to_chars ((char *) where_to_put_displacement,
9268 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9269 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9270 fragP->fr_fix += extension;
9271}
9272\f
7016a5d5 9273/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9274 by our caller that we have all the info we need to fix it up.
9275
7016a5d5
TG		 9276 Parameter valP is the pointer to the value of the bits.
9277
252b5132
RH		 9278 On the 386, immediates, displacements, and data pointers are all in
9279 the same (little-endian) format, so we don't need to care about which
9280 we are handling. */
9281
94f592af 9282void
7016a5d5 9283md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9284{
94f592af 9285 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9286 valueT value = *valP;
252b5132 9287
f86103b7 9288#if !defined (TE_Mach)
93382f6d
AM		 9289 if (fixP->fx_pcrel)
9290 {
9291 switch (fixP->fx_r_type)
9292 {
5865bb77
ILT		 9293 default:
9294 break;
9295
d6ab8113
JB		 9296 case BFD_RELOC_64:
9297 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9298 break;
93382f6d 9299 case BFD_RELOC_32:
ae8887b5 9300 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9301 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9302 break;
9303 case BFD_RELOC_16:
9304 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9305 break;
9306 case BFD_RELOC_8:
9307 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9308 break;
9309 }
9310 }
252b5132 9311
a161fe53 9312 if (fixP->fx_addsy != NULL
31312f95 9313 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9314 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9315 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9316 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9317 && !use_rela_relocations)
252b5132 9318 {
31312f95
AM		 9319 /* This is a hack. There should be a better way to handle this.
9320 This covers for the fact that bfd_install_relocation will
9321 subtract the current location (for partial_inplace, PC relative
9322 relocations); see more below. */
252b5132 9323#ifndef OBJ_AOUT
718ddfc0 9324 if (IS_ELF
252b5132
RH		 9325#ifdef TE_PE
9326 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9327#endif
9328 )
9329 value += fixP->fx_where + fixP->fx_frag->fr_address;
9330#endif
9331#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9332 if (IS_ELF)
252b5132 9333 {
6539b54b 9334 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9335
6539b54b 9336 if ((sym_seg == seg
2f66722d 9337 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9338 && sym_seg != absolute_section))
af65af87 9339 && !generic_force_reloc (fixP))
2f66722d
AM		 9340 {
9341 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9342 bfd_install_relocation subtracts them out again. I think
9343 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9344 it. FIXME. */
9345 value += fixP->fx_where + fixP->fx_frag->fr_address;
9346 }
252b5132
RH		 9347 }
9348#endif
9349#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9350 /* For some reason, the PE format does not store a
9351 section address offset for a PC relative symbol. */
9352 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9353 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9354 value += md_pcrel_from (fixP);
9355#endif
9356 }
fbeb56a4 9357#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9358 if (fixP->fx_addsy != NULL
9359 && S_IS_WEAK (fixP->fx_addsy)
9360 /* PR 16858: Do not modify weak function references. */
9361 && ! fixP->fx_pcrel)
fbeb56a4 9362 {
296a8689
NC		 9363#if !defined (TE_PEP)
9364 /* For x86 PE weak function symbols are neither PC-relative
9365 nor do they set S_IS_FUNCTION. So the only reliable way
9366 to detect them is to check the flags of their containing
9367 section. */
9368 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9369 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9370 ;
9371 else
9372#endif
fbeb56a4
DK		 9373 value -= S_GET_VALUE (fixP->fx_addsy);
9374 }
9375#endif
252b5132
RH		 9376
9377 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9378 and we must not disappoint it. */
252b5132 9379#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9380 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9381 switch (fixP->fx_r_type)
9382 {
9383 case BFD_RELOC_386_PLT32:
3e73aa7c 9384 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9385 /* Make the jump instruction point to the address of the operand. At
9386 runtime we merely add the offset to the actual PLT entry. */
9387 value = -4;
9388 break;
31312f95 9389
13ae64f3
JJ		 9390 case BFD_RELOC_386_TLS_GD:
9391 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9392 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9393 case BFD_RELOC_386_TLS_IE:
9394 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9395 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9396 case BFD_RELOC_X86_64_TLSGD:
9397 case BFD_RELOC_X86_64_TLSLD:
9398 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9399 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9400 value = 0; /* Fully resolved at runtime. No addend. */
9401 /* Fallthrough */
9402 case BFD_RELOC_386_TLS_LE:
9403 case BFD_RELOC_386_TLS_LDO_32:
9404 case BFD_RELOC_386_TLS_LE_32:
9405 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9406 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9407 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9408 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9409 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9410 break;
9411
67a4f2b7
AO		 9412 case BFD_RELOC_386_TLS_DESC_CALL:
9413 case BFD_RELOC_X86_64_TLSDESC_CALL:
9414 value = 0; /* Fully resolved at runtime. No addend. */
9415 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9416 fixP->fx_done = 0;
9417 return;
9418
47926f60
KH		 9419 case BFD_RELOC_VTABLE_INHERIT:
9420 case BFD_RELOC_VTABLE_ENTRY:
9421 fixP->fx_done = 0;
94f592af 9422 return;
47926f60
KH		 9423
9424 default:
9425 break;
9426 }
9427#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9428 *valP = value;
f86103b7 9429#endif /* !defined (TE_Mach) */
3e73aa7c 9430
3e73aa7c 9431 /* Are we finished with this relocation now? */
c6682705 9432 if (fixP->fx_addsy == NULL)
3e73aa7c 9433 fixP->fx_done = 1;
fbeb56a4
DK		 9434#if defined (OBJ_COFF) && defined (TE_PE)
9435 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9436 {
9437 fixP->fx_done = 0;
9438 /* Remember value for tc_gen_reloc. */
9439 fixP->fx_addnumber = value;
9440 /* Clear out the frag for now. */
9441 value = 0;
9442 }
9443#endif
3e73aa7c
JH		 9444 else if (use_rela_relocations)
9445 {
9446 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9447 /* Remember value for tc_gen_reloc. */
9448 fixP->fx_addnumber = value;
3e73aa7c
JH		 9449 value = 0;
9450 }
f86103b7 9451
94f592af 9452 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9453}
252b5132 9454\f
6d4af3c2 9455const char *
499ac353 9456md_atof (int type, char *litP, int *sizeP)
252b5132 9457{
499ac353
NC		 9458 /* This outputs the LITTLENUMs in REVERSE order;
9459 in accord with the bigendian 386. */
9460 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9461}
9462\f
2d545b82 9463static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9464
252b5132 9465static char *
e3bb37b5 9466output_invalid (int c)
252b5132 9467{
3882b010 9468 if (ISPRINT (c))
f9f21a03
L		 9469 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9470 "'%c'", c);
252b5132 9471 else
f9f21a03 9472 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9473 "(0x%x)", (unsigned char) c);
252b5132
RH		 9474 return output_invalid_buf;
9475}
9476
af6bdddf 9477/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9478
9479static const reg_entry *
4d1bb795 9480parse_real_register (char *reg_string, char **end_op)
252b5132 9481{
af6bdddf
AM		 9482 char *s = reg_string;
9483 char *p;
252b5132
RH		 9484 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9485 const reg_entry *r;
9486
9487 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9488 if (*s == REGISTER_PREFIX)
9489 ++s;
9490
9491 if (is_space_char (*s))
9492 ++s;
9493
9494 p = reg_name_given;
af6bdddf 9495 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9496 {
9497 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9498 return (const reg_entry *) NULL;
9499 s++;
252b5132
RH		 9500 }
9501
6588847e
DN		 9502 /* For naked regs, make sure that we are not dealing with an identifier.
9503 This prevents confusing an identifier like `eax_var' with register
9504 `eax'. */
9505 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9506 return (const reg_entry *) NULL;
9507
af6bdddf 9508 *end_op = s;
252b5132
RH		 9509
9510 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9511
5f47d35b 9512 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9513 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9514 {
5f47d35b
AM		 9515 if (is_space_char (*s))
9516 ++s;
9517 if (*s == '(')
9518 {
af6bdddf 9519 ++s;
5f47d35b
AM		 9520 if (is_space_char (*s))
9521 ++s;
9522 if (*s >= '0' && *s <= '7')
9523 {
db557034 9524 int fpr = *s - '0';
af6bdddf 9525 ++s;
5f47d35b
AM		 9526 if (is_space_char (*s))
9527 ++s;
9528 if (*s == ')')
9529 {
9530 *end_op = s + 1;
1e9cc1c2 9531 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9532 know (r);
9533 return r + fpr;
5f47d35b 9534 }
5f47d35b 9535 }
47926f60 9536 /* We have "%st(" then garbage. */
5f47d35b
AM		 9537 return (const reg_entry *) NULL;
9538 }
9539 }
9540
a60de03c
JB		 9541 if (r == NULL || allow_pseudo_reg)
9542 return r;
9543
0dfbf9d7 9544 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9545 return (const reg_entry *) NULL;
9546
192dc9c6
JB		 9547 if ((r->reg_type.bitfield.reg32
9548 || r->reg_type.bitfield.sreg3
9549 || r->reg_type.bitfield.control
9550 || r->reg_type.bitfield.debug
9551 || r->reg_type.bitfield.test)
9552 && !cpu_arch_flags.bitfield.cpui386)
9553 return (const reg_entry *) NULL;
9554
309d3373
JB		 9555 if (r->reg_type.bitfield.floatreg
9556 && !cpu_arch_flags.bitfield.cpu8087
9557 && !cpu_arch_flags.bitfield.cpu287
9558 && !cpu_arch_flags.bitfield.cpu387)
9559 return (const reg_entry *) NULL;
9560
1848e567 9561 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9562 return (const reg_entry *) NULL;
9563
1848e567 9564 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9565 return (const reg_entry *) NULL;
9566
1848e567 9567 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9568 return (const reg_entry *) NULL;
9569
1848e567
L		 9570 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9571 return (const reg_entry *) NULL;
9572
9573 if (r->reg_type.bitfield.regmask
9574 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9575 return (const reg_entry *) NULL;
9576
db51cc60 9577 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9578 if (!allow_index_reg
db51cc60
L		 9579 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9580 return (const reg_entry *) NULL;
9581
43234a1e
L		 9582 /* Upper 16 vector register is only available with VREX in 64bit
9583 mode. */
9584 if ((r->reg_flags & RegVRex))
9585 {
9586 if (!cpu_arch_flags.bitfield.cpuvrex
9587 || flag_code != CODE_64BIT)
9588 return (const reg_entry *) NULL;
9589
9590 i.need_vrex = 1;
9591 }
9592
a60de03c
JB		 9593 if (((r->reg_flags & (RegRex64 | RegRex))
9594 || r->reg_type.bitfield.reg64)
40fb9820 9595 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9596 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9597 && flag_code != CODE_64BIT)
20f0a1fc 9598 return (const reg_entry *) NULL;
1ae00879 9599
b7240065
JB		 9600 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9601 return (const reg_entry *) NULL;
9602
252b5132
RH		 9603 return r;
9604}
4d1bb795
JB		 9605
9606/* REG_STRING starts *before* REGISTER_PREFIX. */
9607
9608static const reg_entry *
9609parse_register (char *reg_string, char **end_op)
9610{
9611 const reg_entry *r;
9612
9613 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9614 r = parse_real_register (reg_string, end_op);
9615 else
9616 r = NULL;
9617 if (!r)
9618 {
9619 char *save = input_line_pointer;
9620 char c;
9621 symbolS *symbolP;
9622
9623 input_line_pointer = reg_string;
d02603dc 9624 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9625 symbolP = symbol_find (reg_string);
9626 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9627 {
9628 const expressionS *e = symbol_get_value_expression (symbolP);
9629
0398aac5 9630 know (e->X_op == O_register);
4eed87de 9631 know (e->X_add_number >= 0
c3fe08fa 9632 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9633 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9634 if ((r->reg_flags & RegVRex))
9635 i.need_vrex = 1;
4d1bb795
JB		 9636 *end_op = input_line_pointer;
9637 }
9638 *input_line_pointer = c;
9639 input_line_pointer = save;
9640 }
9641 return r;
9642}
9643
9644int
9645i386_parse_name (char *name, expressionS *e, char *nextcharP)
9646{
9647 const reg_entry *r;
9648 char *end = input_line_pointer;
9649
9650 *end = *nextcharP;
9651 r = parse_register (name, &input_line_pointer);
9652 if (r && end <= input_line_pointer)
9653 {
9654 *nextcharP = *input_line_pointer;
9655 *input_line_pointer = 0;
9656 e->X_op = O_register;
9657 e->X_add_number = r - i386_regtab;
9658 return 1;
9659 }
9660 input_line_pointer = end;
9661 *end = 0;
ee86248c 9662 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9663}
9664
9665void
9666md_operand (expressionS *e)
9667{
ee86248c
JB		 9668 char *end;
9669 const reg_entry *r;
4d1bb795 9670
ee86248c
JB		 9671 switch (*input_line_pointer)
9672 {
9673 case REGISTER_PREFIX:
9674 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9675 if (r)
9676 {
9677 e->X_op = O_register;
9678 e->X_add_number = r - i386_regtab;
9679 input_line_pointer = end;
9680 }
ee86248c
JB		 9681 break;
9682
9683 case '[':
9c2799c2 9684 gas_assert (intel_syntax);
ee86248c
JB		 9685 end = input_line_pointer++;
9686 expression (e);
9687 if (*input_line_pointer == ']')
9688 {
9689 ++input_line_pointer;
9690 e->X_op_symbol = make_expr_symbol (e);
9691 e->X_add_symbol = NULL;
9692 e->X_add_number = 0;
9693 e->X_op = O_index;
9694 }
9695 else
9696 {
9697 e->X_op = O_absent;
9698 input_line_pointer = end;
9699 }
9700 break;
4d1bb795
JB		 9701 }
9702}
9703
252b5132 9704\f
4cc782b5 9705#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9706const char *md_shortopts = "kVQ:sqn";
252b5132 9707#else
12b55ccc 9708const char *md_shortopts = "qn";
252b5132 9709#endif
6e0b89ee 9710
3e73aa7c 9711#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9712#define OPTION_64 (OPTION_MD_BASE + 1)
9713#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9714#define OPTION_MARCH (OPTION_MD_BASE + 3)
9715#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9716#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9717#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9718#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9719#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9720#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9721#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9722#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9723#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9724#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9725#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9726#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9727#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9728#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9729#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9730#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9731#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9732#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9733#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9734#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9735#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9736#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9737
99ad8390
NC		 9738struct option md_longopts[] =
9739{
3e73aa7c 9740 {"32", no_argument, NULL, OPTION_32},
321098a5 9741#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9742 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9743 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9744#endif
9745#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9746 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9747 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9748#endif
b3b91714 9749 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9750 {"march", required_argument, NULL, OPTION_MARCH},
9751 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9752 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9753 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9754 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9755 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9756 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9757 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9758 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9759 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9760 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9761 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9762 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9763 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9764# if defined (TE_PE) || defined (TE_PEP)
9765 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9766#endif
d1982f93 9767 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9768 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9769 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9770 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9771 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9772 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9773 {NULL, no_argument, NULL, 0}
9774};
9775size_t md_longopts_size = sizeof (md_longopts);
9776
9777int
17b9d67d 9778md_parse_option (int c, const char *arg)
252b5132 9779{
91d6fa6a 9780 unsigned int j;
293f5f65 9781 char *arch, *next, *saved;
9103f4f4 9782
252b5132
RH		 9783 switch (c)
9784 {
12b55ccc
L		 9785 case 'n':
9786 optimize_align_code = 0;
9787 break;
9788
a38cf1db
AM		 9789 case 'q':
9790 quiet_warnings = 1;
252b5132
RH		 9791 break;
9792
9793#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9794 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9795 should be emitted or not. FIXME: Not implemented. */
9796 case 'Q':
252b5132
RH		 9797 break;
9798
9799 /* -V: SVR4 argument to print version ID. */
9800 case 'V':
9801 print_version_id ();
9802 break;
9803
a38cf1db
AM		 9804 /* -k: Ignore for FreeBSD compatibility. */
9805 case 'k':
252b5132 9806 break;
4cc782b5
ILT		 9807
9808 case 's':
9809 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9810 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9811 break;
8dcea932
L		 9812
9813 case OPTION_MSHARED:
9814 shared = 1;
9815 break;
99ad8390 9816#endif
321098a5 9817#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9818 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9819 case OPTION_64:
9820 {
9821 const char **list, **l;
9822
3e73aa7c
JH		 9823 list = bfd_target_list ();
9824 for (l = list; *l != NULL; l++)
8620418b 9825 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9826 || strcmp (*l, "coff-x86-64") == 0
9827 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9828 || strcmp (*l, "pei-x86-64") == 0
9829 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9830 {
9831 default_arch = "x86_64";
9832 break;
9833 }
3e73aa7c 9834 if (*l == NULL)
2b5d6a91 9835 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9836 free (list);
9837 }
9838 break;
9839#endif
252b5132 9840
351f65ca 9841#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9842 case OPTION_X32:
351f65ca
L		 9843 if (IS_ELF)
9844 {
9845 const char **list, **l;
9846
9847 list = bfd_target_list ();
9848 for (l = list; *l != NULL; l++)
9849 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9850 {
9851 default_arch = "x86_64:32";
9852 break;
9853 }
9854 if (*l == NULL)
2b5d6a91 9855 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9856 free (list);
9857 }
9858 else
9859 as_fatal (_("32bit x86_64 is only supported for ELF"));
9860 break;
9861#endif
9862
6e0b89ee
AM		 9863 case OPTION_32:
9864 default_arch = "i386";
9865 break;
9866
b3b91714
AM		 9867 case OPTION_DIVIDE:
9868#ifdef SVR4_COMMENT_CHARS
9869 {
9870 char *n, *t;
9871 const char *s;
9872
add39d23 9873 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9874 t = n;
9875 for (s = i386_comment_chars; *s != '\0'; s++)
9876 if (*s != '/')
9877 *t++ = *s;
9878 *t = '\0';
9879 i386_comment_chars = n;
9880 }
9881#endif
9882 break;
9883
9103f4f4 9884 case OPTION_MARCH:
293f5f65
L		 9885 saved = xstrdup (arg);
9886 arch = saved;
9887 /* Allow -march=+nosse. */
9888 if (*arch == '+')
9889 arch++;
6305a203 9890 do
9103f4f4 9891 {
6305a203 9892 if (*arch == '.')
2b5d6a91 9893 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9894 next = strchr (arch, '+');
9895 if (next)
9896 *next++ = '\0';
91d6fa6a 9897 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9898 {
91d6fa6a 9899 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9900 {
6305a203 9901 /* Processor. */
1ded5609
JB		 9902 if (! cpu_arch[j].flags.bitfield.cpui386)
9903 continue;
9904
91d6fa6a 9905 cpu_arch_name = cpu_arch[j].name;
6305a203 9906 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9907 cpu_arch_flags = cpu_arch[j].flags;
9908 cpu_arch_isa = cpu_arch[j].type;
9909 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9910 if (!cpu_arch_tune_set)
9911 {
9912 cpu_arch_tune = cpu_arch_isa;
9913 cpu_arch_tune_flags = cpu_arch_isa_flags;
9914 }
9915 break;
9916 }
91d6fa6a
NC		 9917 else if (*cpu_arch [j].name == '.'
9918 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9919 {
9920 /* ISA entension. */
9921 i386_cpu_flags flags;
309d3373 9922
293f5f65
L		 9923 flags = cpu_flags_or (cpu_arch_flags,
9924 cpu_arch[j].flags);
81486035
L		 9925
9926 if (!valid_iamcu_cpu_flags (&flags))
9927 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9928 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9929 {
9930 if (cpu_sub_arch_name)
9931 {
9932 char *name = cpu_sub_arch_name;
9933 cpu_sub_arch_name = concat (name,
91d6fa6a 9934 cpu_arch[j].name,
1bf57e9f 9935 (const char *) NULL);
6305a203
L		 9936 free (name);
9937 }
9938 else
91d6fa6a 9939 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9940 cpu_arch_flags = flags;
a586129e 9941 cpu_arch_isa_flags = flags;
6305a203
L		 9942 }
9943 break;
ccc9c027 9944 }
9103f4f4 9945 }
6305a203 9946
293f5f65
L		 9947 if (j >= ARRAY_SIZE (cpu_arch))
9948 {
9949 /* Disable an ISA entension. */
9950 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
9951 if (strcmp (arch, cpu_noarch [j].name) == 0)
9952 {
9953 i386_cpu_flags flags;
9954
9955 flags = cpu_flags_and_not (cpu_arch_flags,
9956 cpu_noarch[j].flags);
9957 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9958 {
9959 if (cpu_sub_arch_name)
9960 {
9961 char *name = cpu_sub_arch_name;
9962 cpu_sub_arch_name = concat (arch,
9963 (const char *) NULL);
9964 free (name);
9965 }
9966 else
9967 cpu_sub_arch_name = xstrdup (arch);
9968 cpu_arch_flags = flags;
9969 cpu_arch_isa_flags = flags;
9970 }
9971 break;
9972 }
9973
9974 if (j >= ARRAY_SIZE (cpu_noarch))
9975 j = ARRAY_SIZE (cpu_arch);
9976 }
9977
91d6fa6a 9978 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9979 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9980
9981 arch = next;
9103f4f4 9982 }
293f5f65
L		 9983 while (next != NULL);
9984 free (saved);
9103f4f4
L		 9985 break;
9986
9987 case OPTION_MTUNE:
9988 if (*arg == '.')
2b5d6a91 9989 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9990 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9991 {
91d6fa6a 9992 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9993 {
ccc9c027 9994 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9995 cpu_arch_tune = cpu_arch [j].type;
9996 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9997 break;
9998 }
9999 }
91d6fa6a 10000 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10001 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10002 break;
10003
1efbbeb4
L		 10004 case OPTION_MMNEMONIC:
10005 if (strcasecmp (arg, "att") == 0)
10006 intel_mnemonic = 0;
10007 else if (strcasecmp (arg, "intel") == 0)
10008 intel_mnemonic = 1;
10009 else
2b5d6a91 10010 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10011 break;
10012
10013 case OPTION_MSYNTAX:
10014 if (strcasecmp (arg, "att") == 0)
10015 intel_syntax = 0;
10016 else if (strcasecmp (arg, "intel") == 0)
10017 intel_syntax = 1;
10018 else
2b5d6a91 10019 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10020 break;
10021
10022 case OPTION_MINDEX_REG:
10023 allow_index_reg = 1;
10024 break;
10025
10026 case OPTION_MNAKED_REG:
10027 allow_naked_reg = 1;
10028 break;
10029
10030 case OPTION_MOLD_GCC:
10031 old_gcc = 1;
1efbbeb4
L		 10032 break;
10033
c0f3af97
L		 10034 case OPTION_MSSE2AVX:
10035 sse2avx = 1;
10036 break;
10037
daf50ae7
L		 10038 case OPTION_MSSE_CHECK:
10039 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10040 sse_check = check_error;
daf50ae7 10041 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10042 sse_check = check_warning;
daf50ae7 10043 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10044 sse_check = check_none;
daf50ae7 10045 else
2b5d6a91 10046 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10047 break;
10048
7bab8ab5
JB		 10049 case OPTION_MOPERAND_CHECK:
10050 if (strcasecmp (arg, "error") == 0)
10051 operand_check = check_error;
10052 else if (strcasecmp (arg, "warning") == 0)
10053 operand_check = check_warning;
10054 else if (strcasecmp (arg, "none") == 0)
10055 operand_check = check_none;
10056 else
10057 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10058 break;
10059
539f890d
L		 10060 case OPTION_MAVXSCALAR:
10061 if (strcasecmp (arg, "128") == 0)
10062 avxscalar = vex128;
10063 else if (strcasecmp (arg, "256") == 0)
10064 avxscalar = vex256;
10065 else
2b5d6a91 10066 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10067 break;
10068
7e8b059b
L		 10069 case OPTION_MADD_BND_PREFIX:
10070 add_bnd_prefix = 1;
10071 break;
10072
43234a1e
L		 10073 case OPTION_MEVEXLIG:
10074 if (strcmp (arg, "128") == 0)
10075 evexlig = evexl128;
10076 else if (strcmp (arg, "256") == 0)
10077 evexlig = evexl256;
10078 else if (strcmp (arg, "512") == 0)
10079 evexlig = evexl512;
10080 else
10081 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10082 break;
10083
d3d3c6db
IT		 10084 case OPTION_MEVEXRCIG:
10085 if (strcmp (arg, "rne") == 0)
10086 evexrcig = rne;
10087 else if (strcmp (arg, "rd") == 0)
10088 evexrcig = rd;
10089 else if (strcmp (arg, "ru") == 0)
10090 evexrcig = ru;
10091 else if (strcmp (arg, "rz") == 0)
10092 evexrcig = rz;
10093 else
10094 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10095 break;
10096
43234a1e
L		 10097 case OPTION_MEVEXWIG:
10098 if (strcmp (arg, "0") == 0)
10099 evexwig = evexw0;
10100 else if (strcmp (arg, "1") == 0)
10101 evexwig = evexw1;
10102 else
10103 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10104 break;
10105
167ad85b
TG		 10106# if defined (TE_PE) || defined (TE_PEP)
10107 case OPTION_MBIG_OBJ:
10108 use_big_obj = 1;
10109 break;
10110#endif
10111
d1982f93 10112 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10113 if (strcasecmp (arg, "yes") == 0)
10114 omit_lock_prefix = 1;
10115 else if (strcasecmp (arg, "no") == 0)
10116 omit_lock_prefix = 0;
10117 else
10118 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10119 break;
10120
e4e00185
AS		 10121 case OPTION_MFENCE_AS_LOCK_ADD:
10122 if (strcasecmp (arg, "yes") == 0)
10123 avoid_fence = 1;
10124 else if (strcasecmp (arg, "no") == 0)
10125 avoid_fence = 0;
10126 else
10127 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10128 break;
10129
0cb4071e
L		 10130 case OPTION_MRELAX_RELOCATIONS:
10131 if (strcasecmp (arg, "yes") == 0)
10132 generate_relax_relocations = 1;
10133 else if (strcasecmp (arg, "no") == 0)
10134 generate_relax_relocations = 0;
10135 else
10136 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10137 break;
10138
5db04b09 10139 case OPTION_MAMD64:
e89c5eaa 10140 intel64 = 0;
5db04b09
L		 10141 break;
10142
10143 case OPTION_MINTEL64:
e89c5eaa 10144 intel64 = 1;
5db04b09
L		 10145 break;
10146
252b5132
RH		 10147 default:
10148 return 0;
10149 }
10150 return 1;
10151}
10152
8a2c8fef
L		 10153#define MESSAGE_TEMPLATE \
10154" "
10155
293f5f65
L		 10156static char *
10157output_message (FILE *stream, char *p, char *message, char *start,
10158 int *left_p, const char *name, int len)
10159{
10160 int size = sizeof (MESSAGE_TEMPLATE);
10161 int left = *left_p;
10162
10163 /* Reserve 2 spaces for ", " or ",\0" */
10164 left -= len + 2;
10165
10166 /* Check if there is any room. */
10167 if (left >= 0)
10168 {
10169 if (p != start)
10170 {
10171 *p++ = ',';
10172 *p++ = ' ';
10173 }
10174 p = mempcpy (p, name, len);
10175 }
10176 else
10177 {
10178 /* Output the current message now and start a new one. */
10179 *p++ = ',';
10180 *p = '\0';
10181 fprintf (stream, "%s\n", message);
10182 p = start;
10183 left = size - (start - message) - len - 2;
10184
10185 gas_assert (left >= 0);
10186
10187 p = mempcpy (p, name, len);
10188 }
10189
10190 *left_p = left;
10191 return p;
10192}
10193
8a2c8fef 10194static void
1ded5609 10195show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10196{
10197 static char message[] = MESSAGE_TEMPLATE;
10198 char *start = message + 27;
10199 char *p;
10200 int size = sizeof (MESSAGE_TEMPLATE);
10201 int left;
10202 const char *name;
10203 int len;
10204 unsigned int j;
10205
10206 p = start;
10207 left = size - (start - message);
10208 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10209 {
10210 /* Should it be skipped? */
10211 if (cpu_arch [j].skip)
10212 continue;
10213
10214 name = cpu_arch [j].name;
10215 len = cpu_arch [j].len;
10216 if (*name == '.')
10217 {
10218 /* It is an extension. Skip if we aren't asked to show it. */
10219 if (ext)
10220 {
10221 name++;
10222 len--;
10223 }
10224 else
10225 continue;
10226 }
10227 else if (ext)
10228 {
10229 /* It is an processor. Skip if we show only extension. */
10230 continue;
10231 }
1ded5609
JB		 10232 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10233 {
10234 /* It is an impossible processor - skip. */
10235 continue;
10236 }
8a2c8fef 10237
293f5f65 10238 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10239 }
10240
293f5f65
L		 10241 /* Display disabled extensions. */
10242 if (ext)
10243 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10244 {
10245 name = cpu_noarch [j].name;
10246 len = cpu_noarch [j].len;
10247 p = output_message (stream, p, message, start, &left, name,
10248 len);
10249 }
10250
8a2c8fef
L		 10251 *p = '\0';
10252 fprintf (stream, "%s\n", message);
10253}
10254
252b5132 10255void
8a2c8fef 10256md_show_usage (FILE *stream)
252b5132 10257{
4cc782b5
ILT		 10258#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10259 fprintf (stream, _("\
a38cf1db
AM		 10260 -Q ignored\n\
10261 -V print assembler version number\n\
b3b91714
AM		 10262 -k ignored\n"));
10263#endif
10264 fprintf (stream, _("\
12b55ccc 10265 -n Do not optimize code alignment\n\
b3b91714
AM		 10266 -q quieten some warnings\n"));
10267#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10268 fprintf (stream, _("\
a38cf1db 10269 -s ignored\n"));
b3b91714 10270#endif
321098a5
L		 10271#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10272 || defined (TE_PE) || defined (TE_PEP))
751d281c 10273 fprintf (stream, _("\
570561f7 10274 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10275#endif
b3b91714
AM		 10276#ifdef SVR4_COMMENT_CHARS
10277 fprintf (stream, _("\
10278 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10279#else
10280 fprintf (stream, _("\
b3b91714 10281 --divide ignored\n"));
4cc782b5 10282#endif
9103f4f4 10283 fprintf (stream, _("\
6305a203 10284 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10285 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10286 show_arch (stream, 0, 1);
8a2c8fef
L		 10287 fprintf (stream, _("\
10288 EXTENSION is combination of:\n"));
1ded5609 10289 show_arch (stream, 1, 0);
6305a203 10290 fprintf (stream, _("\
8a2c8fef 10291 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10292 show_arch (stream, 0, 0);
ba104c83 10293 fprintf (stream, _("\
c0f3af97
L		 10294 -msse2avx encode SSE instructions with VEX prefix\n"));
10295 fprintf (stream, _("\
daf50ae7
L		 10296 -msse-check=[none|error|warning]\n\
10297 check SSE instructions\n"));
10298 fprintf (stream, _("\
7bab8ab5
JB		 10299 -moperand-check=[none|error|warning]\n\
10300 check operand combinations for validity\n"));
10301 fprintf (stream, _("\
539f890d
L		 10302 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10303 length\n"));
10304 fprintf (stream, _("\
43234a1e
L		 10305 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10306 length\n"));
10307 fprintf (stream, _("\
10308 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10309 for EVEX.W bit ignored instructions\n"));
10310 fprintf (stream, _("\
d3d3c6db
IT		 10311 -mevexrcig=[rne|rd|ru|rz]\n\
10312 encode EVEX instructions with specific EVEX.RC value\n\
10313 for SAE-only ignored instructions\n"));
10314 fprintf (stream, _("\
ba104c83
L		 10315 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10316 fprintf (stream, _("\
10317 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10318 fprintf (stream, _("\
10319 -mindex-reg support pseudo index registers\n"));
10320 fprintf (stream, _("\
10321 -mnaked-reg don't require `%%' prefix for registers\n"));
10322 fprintf (stream, _("\
10323 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10324 fprintf (stream, _("\
10325 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10326 fprintf (stream, _("\
10327 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10328# if defined (TE_PE) || defined (TE_PEP)
10329 fprintf (stream, _("\
10330 -mbig-obj generate big object files\n"));
10331#endif
d022bddd
IT		 10332 fprintf (stream, _("\
10333 -momit-lock-prefix=[no|yes]\n\
10334 strip all lock prefixes\n"));
5db04b09 10335 fprintf (stream, _("\
e4e00185
AS		 10336 -mfence-as-lock-add=[no|yes]\n\
10337 encode lfence, mfence and sfence as\n\
10338 lock addl $0x0, (%%{re}sp)\n"));
10339 fprintf (stream, _("\
0cb4071e
L		 10340 -mrelax-relocations=[no|yes]\n\
10341 generate relax relocations\n"));
10342 fprintf (stream, _("\
5db04b09
L		 10343 -mamd64 accept only AMD64 ISA\n"));
10344 fprintf (stream, _("\
10345 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10346}
10347
3e73aa7c 10348#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10349 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10350 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10351
10352/* Pick the target format to use. */
10353
47926f60 10354const char *
e3bb37b5 10355i386_target_format (void)
252b5132 10356{
351f65ca
L		 10357 if (!strncmp (default_arch, "x86_64", 6))
10358 {
10359 update_code_flag (CODE_64BIT, 1);
10360 if (default_arch[6] == '\0')
7f56bc95 10361 x86_elf_abi = X86_64_ABI;
351f65ca 10362 else
7f56bc95 10363 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10364 }
3e73aa7c 10365 else if (!strcmp (default_arch, "i386"))
78f12dd3 10366 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10367 else if (!strcmp (default_arch, "iamcu"))
10368 {
10369 update_code_flag (CODE_32BIT, 1);
10370 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10371 {
10372 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10373 cpu_arch_name = "iamcu";
10374 cpu_sub_arch_name = NULL;
10375 cpu_arch_flags = iamcu_flags;
10376 cpu_arch_isa = PROCESSOR_IAMCU;
10377 cpu_arch_isa_flags = iamcu_flags;
10378 if (!cpu_arch_tune_set)
10379 {
10380 cpu_arch_tune = cpu_arch_isa;
10381 cpu_arch_tune_flags = cpu_arch_isa_flags;
10382 }
10383 }
10384 else
10385 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10386 cpu_arch_name);
10387 }
3e73aa7c 10388 else
2b5d6a91 10389 as_fatal (_("unknown architecture"));
89507696
JB		 10390
10391 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10392 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10393 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10394 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10395
252b5132
RH		 10396 switch (OUTPUT_FLAVOR)
10397 {
9384f2ff 10398#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10399 case bfd_target_aout_flavour:
47926f60 10400 return AOUT_TARGET_FORMAT;
4c63da97 10401#endif
9384f2ff
AM		 10402#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10403# if defined (TE_PE) || defined (TE_PEP)
10404 case bfd_target_coff_flavour:
167ad85b
TG		 10405 if (flag_code == CODE_64BIT)
10406 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10407 else
10408 return "pe-i386";
9384f2ff 10409# elif defined (TE_GO32)
0561d57c
JK		 10410 case bfd_target_coff_flavour:
10411 return "coff-go32";
9384f2ff 10412# else
252b5132
RH		 10413 case bfd_target_coff_flavour:
10414 return "coff-i386";
9384f2ff 10415# endif
4c63da97 10416#endif
3e73aa7c 10417#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10418 case bfd_target_elf_flavour:
3e73aa7c 10419 {
351f65ca
L		 10420 const char *format;
10421
10422 switch (x86_elf_abi)
4fa24527 10423 {
351f65ca
L		 10424 default:
10425 format = ELF_TARGET_FORMAT;
10426 break;
7f56bc95 10427 case X86_64_ABI:
351f65ca 10428 use_rela_relocations = 1;
4fa24527 10429 object_64bit = 1;
351f65ca
L		 10430 format = ELF_TARGET_FORMAT64;
10431 break;
7f56bc95 10432 case X86_64_X32_ABI:
4fa24527 10433 use_rela_relocations = 1;
351f65ca 10434 object_64bit = 1;
862be3fb 10435 disallow_64bit_reloc = 1;
351f65ca
L		 10436 format = ELF_TARGET_FORMAT32;
10437 break;
4fa24527 10438 }
3632d14b 10439 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10440 {
7f56bc95 10441 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10442 as_fatal (_("Intel L1OM is 64bit only"));
10443 return ELF_TARGET_L1OM_FORMAT;
10444 }
b49f93f6 10445 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10446 {
10447 if (x86_elf_abi != X86_64_ABI)
10448 as_fatal (_("Intel K1OM is 64bit only"));
10449 return ELF_TARGET_K1OM_FORMAT;
10450 }
81486035
L		 10451 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10452 {
10453 if (x86_elf_abi != I386_ABI)
10454 as_fatal (_("Intel MCU is 32bit only"));
10455 return ELF_TARGET_IAMCU_FORMAT;
10456 }
8a9036a4 10457 else
351f65ca 10458 return format;
3e73aa7c 10459 }
e57f8c65
TG		 10460#endif
10461#if defined (OBJ_MACH_O)
10462 case bfd_target_mach_o_flavour:
d382c579
TG		 10463 if (flag_code == CODE_64BIT)
10464 {
10465 use_rela_relocations = 1;
10466 object_64bit = 1;
10467 return "mach-o-x86-64";
10468 }
10469 else
10470 return "mach-o-i386";
4c63da97 10471#endif
252b5132
RH		 10472 default:
10473 abort ();
10474 return NULL;
10475 }
10476}
10477
47926f60 10478#endif /* OBJ_MAYBE_ more than one */
252b5132 10479\f
252b5132 10480symbolS *
7016a5d5 10481md_undefined_symbol (char *name)
252b5132 10482{
18dc2407
ILT		 10483 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10484 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10485 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10486 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10487 {
10488 if (!GOT_symbol)
10489 {
10490 if (symbol_find (name))
10491 as_bad (_("GOT already in symbol table"));
10492 GOT_symbol = symbol_new (name, undefined_section,
10493 (valueT) 0, &zero_address_frag);
10494 };
10495 return GOT_symbol;
10496 }
252b5132
RH		 10497 return 0;
10498}
10499
10500/* Round up a section size to the appropriate boundary. */
47926f60 10501
252b5132 10502valueT
7016a5d5 10503md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10504{
4c63da97
AM		 10505#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10506 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10507 {
10508 /* For a.out, force the section size to be aligned. If we don't do
10509 this, BFD will align it for us, but it will not write out the
10510 final bytes of the section. This may be a bug in BFD, but it is
10511 easier to fix it here since that is how the other a.out targets
10512 work. */
10513 int align;
10514
10515 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10516 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10517 }
252b5132
RH		 10518#endif
10519
10520 return size;
10521}
10522
10523/* On the i386, PC-relative offsets are relative to the start of the
10524 next instruction. That is, the address of the offset, plus its
10525 size, since the offset is always the last part of the insn. */
10526
10527long
e3bb37b5 10528md_pcrel_from (fixS *fixP)
252b5132
RH		 10529{
10530 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10531}
10532
10533#ifndef I386COFF
10534
10535static void
e3bb37b5 10536s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10537{
29b0f896 10538 int temp;
252b5132 10539
8a75718c
JB		 10540#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10541 if (IS_ELF)
10542 obj_elf_section_change_hook ();
10543#endif
252b5132
RH		 10544 temp = get_absolute_expression ();
10545 subseg_set (bss_section, (subsegT) temp);
10546 demand_empty_rest_of_line ();
10547}
10548
10549#endif
10550
252b5132 10551void
e3bb37b5 10552i386_validate_fix (fixS *fixp)
252b5132 10553{
02a86693 10554 if (fixp->fx_subsy)
252b5132 10555 {
02a86693 10556 if (fixp->fx_subsy == GOT_symbol)
23df1078 10557 {
02a86693
L		 10558 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10559 {
10560 if (!object_64bit)
10561 abort ();
10562#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10563 if (fixp->fx_tcbit2)
56ceb5b5
L		 10564 fixp->fx_r_type = (fixp->fx_tcbit
10565 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10566 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10567 else
10568#endif
10569 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10570 }
d6ab8113 10571 else
02a86693
L		 10572 {
10573 if (!object_64bit)
10574 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10575 else
10576 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10577 }
10578 fixp->fx_subsy = 0;
23df1078 10579 }
252b5132 10580 }
02a86693
L		 10581#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10582 else if (!object_64bit)
10583 {
10584 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10585 && fixp->fx_tcbit2)
10586 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10587 }
10588#endif
252b5132
RH		 10589}
10590
252b5132 10591arelent *
7016a5d5 10592tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10593{
10594 arelent *rel;
10595 bfd_reloc_code_real_type code;
10596
10597 switch (fixp->fx_r_type)
10598 {
8ce3d284 10599#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10600 case BFD_RELOC_SIZE32:
10601 case BFD_RELOC_SIZE64:
10602 if (S_IS_DEFINED (fixp->fx_addsy)
10603 && !S_IS_EXTERNAL (fixp->fx_addsy))
10604 {
10605 /* Resolve size relocation against local symbol to size of
10606 the symbol plus addend. */
10607 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10608 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10609 && !fits_in_unsigned_long (value))
10610 as_bad_where (fixp->fx_file, fixp->fx_line,
10611 _("symbol size computation overflow"));
10612 fixp->fx_addsy = NULL;
10613 fixp->fx_subsy = NULL;
10614 md_apply_fix (fixp, (valueT *) &value, NULL);
10615 return NULL;
10616 }
8ce3d284 10617#endif
8fd4256d 10618
3e73aa7c
JH		 10619 case BFD_RELOC_X86_64_PLT32:
10620 case BFD_RELOC_X86_64_GOT32:
10621 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10622 case BFD_RELOC_X86_64_GOTPCRELX:
10623 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10624 case BFD_RELOC_386_PLT32:
10625 case BFD_RELOC_386_GOT32:
02a86693 10626 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10627 case BFD_RELOC_386_GOTOFF:
10628 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10629 case BFD_RELOC_386_TLS_GD:
10630 case BFD_RELOC_386_TLS_LDM:
10631 case BFD_RELOC_386_TLS_LDO_32:
10632 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10633 case BFD_RELOC_386_TLS_IE:
10634 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10635 case BFD_RELOC_386_TLS_LE_32:
10636 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10637 case BFD_RELOC_386_TLS_GOTDESC:
10638 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10639 case BFD_RELOC_X86_64_TLSGD:
10640 case BFD_RELOC_X86_64_TLSLD:
10641 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10642 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10643 case BFD_RELOC_X86_64_GOTTPOFF:
10644 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10645 case BFD_RELOC_X86_64_TPOFF64:
10646 case BFD_RELOC_X86_64_GOTOFF64:
10647 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10648 case BFD_RELOC_X86_64_GOT64:
10649 case BFD_RELOC_X86_64_GOTPCREL64:
10650 case BFD_RELOC_X86_64_GOTPC64:
10651 case BFD_RELOC_X86_64_GOTPLT64:
10652 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10653 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10654 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10655 case BFD_RELOC_RVA:
10656 case BFD_RELOC_VTABLE_ENTRY:
10657 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10658#ifdef TE_PE
10659 case BFD_RELOC_32_SECREL:
10660#endif
252b5132
RH		 10661 code = fixp->fx_r_type;
10662 break;
dbbaec26
L		 10663 case BFD_RELOC_X86_64_32S:
10664 if (!fixp->fx_pcrel)
10665 {
10666 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10667 code = fixp->fx_r_type;
10668 break;
10669 }
252b5132 10670 default:
93382f6d 10671 if (fixp->fx_pcrel)
252b5132 10672 {
93382f6d
AM		 10673 switch (fixp->fx_size)
10674 {
10675 default:
b091f402
AM		 10676 as_bad_where (fixp->fx_file, fixp->fx_line,
10677 _("can not do %d byte pc-relative relocation"),
10678 fixp->fx_size);
93382f6d
AM		 10679 code = BFD_RELOC_32_PCREL;
10680 break;
10681 case 1: code = BFD_RELOC_8_PCREL; break;
10682 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10683 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10684#ifdef BFD64
10685 case 8: code = BFD_RELOC_64_PCREL; break;
10686#endif
93382f6d
AM		 10687 }
10688 }
10689 else
10690 {
10691 switch (fixp->fx_size)
10692 {
10693 default:
b091f402
AM		 10694 as_bad_where (fixp->fx_file, fixp->fx_line,
10695 _("can not do %d byte relocation"),
10696 fixp->fx_size);
93382f6d
AM		 10697 code = BFD_RELOC_32;
10698 break;
10699 case 1: code = BFD_RELOC_8; break;
10700 case 2: code = BFD_RELOC_16; break;
10701 case 4: code = BFD_RELOC_32; break;
937149dd 10702#ifdef BFD64
3e73aa7c 10703 case 8: code = BFD_RELOC_64; break;
937149dd 10704#endif
93382f6d 10705 }
252b5132
RH		 10706 }
10707 break;
10708 }
252b5132 10709
d182319b
JB		 10710 if ((code == BFD_RELOC_32
10711 || code == BFD_RELOC_32_PCREL
10712 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10713 && GOT_symbol
10714 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10715 {
4fa24527 10716 if (!object_64bit)
d6ab8113
JB		 10717 code = BFD_RELOC_386_GOTPC;
10718 else
10719 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10720 }
7b81dfbb
AJ		 10721 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10722 && GOT_symbol
10723 && fixp->fx_addsy == GOT_symbol)
10724 {
10725 code = BFD_RELOC_X86_64_GOTPC64;
10726 }
252b5132 10727
add39d23
TS		 10728 rel = XNEW (arelent);
10729 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10730 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10731
10732 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10733
3e73aa7c
JH		 10734 if (!use_rela_relocations)
10735 {
10736 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10737 vtable entry to be used in the relocation's section offset. */
10738 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10739 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10740#if defined (OBJ_COFF) && defined (TE_PE)
10741 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10742 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10743 else
10744#endif
c6682705 10745 rel->addend = 0;
3e73aa7c
JH		 10746 }
10747 /* Use the rela in 64bit mode. */
252b5132 10748 else
3e73aa7c 10749 {
862be3fb
L		 10750 if (disallow_64bit_reloc)
10751 switch (code)
10752 {
862be3fb
L		 10753 case BFD_RELOC_X86_64_DTPOFF64:
10754 case BFD_RELOC_X86_64_TPOFF64:
10755 case BFD_RELOC_64_PCREL:
10756 case BFD_RELOC_X86_64_GOTOFF64:
10757 case BFD_RELOC_X86_64_GOT64:
10758 case BFD_RELOC_X86_64_GOTPCREL64:
10759 case BFD_RELOC_X86_64_GOTPC64:
10760 case BFD_RELOC_X86_64_GOTPLT64:
10761 case BFD_RELOC_X86_64_PLTOFF64:
10762 as_bad_where (fixp->fx_file, fixp->fx_line,
10763 _("cannot represent relocation type %s in x32 mode"),
10764 bfd_get_reloc_code_name (code));
10765 break;
10766 default:
10767 break;
10768 }
10769
062cd5e7
AS		 10770 if (!fixp->fx_pcrel)
10771 rel->addend = fixp->fx_offset;
10772 else
10773 switch (code)
10774 {
10775 case BFD_RELOC_X86_64_PLT32:
10776 case BFD_RELOC_X86_64_GOT32:
10777 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10778 case BFD_RELOC_X86_64_GOTPCRELX:
10779 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10780 case BFD_RELOC_X86_64_TLSGD:
10781 case BFD_RELOC_X86_64_TLSLD:
10782 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10783 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10784 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10785 rel->addend = fixp->fx_offset - fixp->fx_size;
10786 break;
10787 default:
10788 rel->addend = (section->vma
10789 - fixp->fx_size
10790 + fixp->fx_addnumber
10791 + md_pcrel_from (fixp));
10792 break;
10793 }
3e73aa7c
JH		 10794 }
10795
252b5132
RH		 10796 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10797 if (rel->howto == NULL)
10798 {
10799 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10800 _("cannot represent relocation type %s"),
252b5132
RH		 10801 bfd_get_reloc_code_name (code));
10802 /* Set howto to a garbage value so that we can keep going. */
10803 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10804 gas_assert (rel->howto != NULL);
252b5132
RH		 10805 }
10806
10807 return rel;
10808}
10809
ee86248c 10810#include "tc-i386-intel.c"
54cfded0 10811
a60de03c
JB		 10812void
10813tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10814{
a60de03c
JB		 10815 int saved_naked_reg;
10816 char saved_register_dot;
54cfded0 10817
a60de03c
JB		 10818 saved_naked_reg = allow_naked_reg;
10819 allow_naked_reg = 1;
10820 saved_register_dot = register_chars['.'];
10821 register_chars['.'] = '.';
10822 allow_pseudo_reg = 1;
10823 expression_and_evaluate (exp);
10824 allow_pseudo_reg = 0;
10825 register_chars['.'] = saved_register_dot;
10826 allow_naked_reg = saved_naked_reg;
10827
e96d56a1 10828 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10829 {
a60de03c
JB		 10830 if ((addressT) exp->X_add_number < i386_regtab_size)
10831 {
10832 exp->X_op = O_constant;
10833 exp->X_add_number = i386_regtab[exp->X_add_number]
10834 .dw2_regnum[flag_code >> 1];
10835 }
10836 else
10837 exp->X_op = O_illegal;
54cfded0 10838 }
54cfded0
AM		 10839}
10840
10841void
10842tc_x86_frame_initial_instructions (void)
10843{
a60de03c
JB		 10844 static unsigned int sp_regno[2];
10845
10846 if (!sp_regno[flag_code >> 1])
10847 {
10848 char *saved_input = input_line_pointer;
10849 char sp[][4] = {"esp", "rsp"};
10850 expressionS exp;
a4447b93 10851
a60de03c
JB		 10852 input_line_pointer = sp[flag_code >> 1];
10853 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10854 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10855 sp_regno[flag_code >> 1] = exp.X_add_number;
10856 input_line_pointer = saved_input;
10857 }
a4447b93 10858
61ff971f
L		 10859 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10860 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10861}
d2b2c203 10862
d7921315
L		 10863int
10864x86_dwarf2_addr_size (void)
10865{
10866#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10867 if (x86_elf_abi == X86_64_X32_ABI)
10868 return 4;
10869#endif
10870 return bfd_arch_bits_per_address (stdoutput) / 8;
10871}
10872
d2b2c203
DJ		 10873int
10874i386_elf_section_type (const char *str, size_t len)
10875{
10876 if (flag_code == CODE_64BIT
10877 && len == sizeof ("unwind") - 1
10878 && strncmp (str, "unwind", 6) == 0)
10879 return SHT_X86_64_UNWIND;
10880
10881 return -1;
10882}
bb41ade5 10883
ad5fec3b
EB		 10884#ifdef TE_SOLARIS
10885void
10886i386_solaris_fix_up_eh_frame (segT sec)
10887{
10888 if (flag_code == CODE_64BIT)
10889 elf_section_type (sec) = SHT_X86_64_UNWIND;
10890}
10891#endif
10892
bb41ade5
AM		 10893#ifdef TE_PE
10894void
10895tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10896{
91d6fa6a 10897 expressionS exp;
bb41ade5 10898
91d6fa6a
NC		 10899 exp.X_op = O_secrel;
10900 exp.X_add_symbol = symbol;
10901 exp.X_add_number = 0;
10902 emit_expr (&exp, size);
bb41ade5
AM		 10903}
10904#endif
3b22753a
L		 10905
10906#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10907/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10908
01e1a5bc 10909bfd_vma
6d4af3c2 10910x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10911{
10912 if (flag_code == CODE_64BIT)
10913 {
10914 if (letter == 'l')
10915 return SHF_X86_64_LARGE;
10916
8f3bae45 10917 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10918 }
3b22753a 10919 else
8f3bae45 10920 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10921 return -1;
10922}
10923
01e1a5bc 10924bfd_vma
3b22753a
L		 10925x86_64_section_word (char *str, size_t len)
10926{
8620418b 10927 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10928 return SHF_X86_64_LARGE;
10929
10930 return -1;
10931}
10932
10933static void
10934handle_large_common (int small ATTRIBUTE_UNUSED)
10935{
10936 if (flag_code != CODE_64BIT)
10937 {
10938 s_comm_internal (0, elf_common_parse);
10939 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10940 }
10941 else
10942 {
10943 static segT lbss_section;
10944 asection *saved_com_section_ptr = elf_com_section_ptr;
10945 asection *saved_bss_section = bss_section;
10946
10947 if (lbss_section == NULL)
10948 {
10949 flagword applicable;
10950 segT seg = now_seg;
10951 subsegT subseg = now_subseg;
10952
10953 /* The .lbss section is for local .largecomm symbols. */
10954 lbss_section = subseg_new (".lbss", 0);
10955 applicable = bfd_applicable_section_flags (stdoutput);
10956 bfd_set_section_flags (stdoutput, lbss_section,
10957 applicable & SEC_ALLOC);
10958 seg_info (lbss_section)->bss = 1;
10959
10960 subseg_set (seg, subseg);
10961 }
10962
10963 elf_com_section_ptr = &_bfd_elf_large_com_section;
10964 bss_section = lbss_section;
10965
10966 s_comm_internal (0, elf_common_parse);
10967
10968 elf_com_section_ptr = saved_com_section_ptr;
10969 bss_section = saved_bss_section;
10970 }
10971}
10972#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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