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gas/testsuite/
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
d3ce72d0
NC		 100 const insn_template *start;
101 const insn_template *end;
6305a203
L		 102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
6305a203
L		 117/* 386 opcode byte to code indirect addressing. */
118typedef struct
119{
120 unsigned base;
121 unsigned index;
122 unsigned scale;
123}
124sib_byte;
125
6305a203
L		 126/* x86 arch names, types and features */
127typedef struct
128{
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132}
133arch_entry;
134
e3bb37b5
L		 135static void set_code_flag (int);
136static void set_16bit_gcc_code_flag (int);
137static void set_intel_syntax (int);
1efbbeb4 138static void set_intel_mnemonic (int);
db51cc60 139static void set_allow_index_reg (int);
cb19c032 140static void set_sse_check (int);
e3bb37b5 141static void set_cpu_arch (int);
6482c264 142#ifdef TE_PE
e3bb37b5 143static void pe_directive_secrel (int);
6482c264 144#endif
e3bb37b5
L		 145static void signed_cons (int);
146static char *output_invalid (int c);
ee86248c
JB		 147static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
148 const char *);
149static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
150 const char *);
a7619375 151static int i386_att_operand (char *);
e3bb37b5 152static int i386_intel_operand (char *, int);
ee86248c
JB		 153static int i386_intel_simplify (expressionS *);
154static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 155static const reg_entry *parse_register (char *, char **);
156static char *parse_insn (char *, char *);
157static char *parse_operands (char *, const char *);
158static void swap_operands (void);
4d456e3d 159static void swap_2_operands (int, int);
e3bb37b5
L		 160static void optimize_imm (void);
161static void optimize_disp (void);
d3ce72d0 162static const insn_template *match_template (void);
e3bb37b5
L		 163static int check_string (void);
164static int process_suffix (void);
165static int check_byte_reg (void);
166static int check_long_reg (void);
167static int check_qword_reg (void);
168static int check_word_reg (void);
169static int finalize_imm (void);
170static int process_operands (void);
171static const seg_entry *build_modrm_byte (void);
172static void output_insn (void);
173static void output_imm (fragS *, offsetT);
174static void output_disp (fragS *, offsetT);
29b0f896 175#ifndef I386COFF
e3bb37b5 176static void s_bss (int);
252b5132 177#endif
17d4e2a2
L		 178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179static void handle_large_common (int small ATTRIBUTE_UNUSED);
180#endif
252b5132 181
a847613f 182static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 183
c0f3af97
L		 184/* VEX prefix. */
185typedef struct
186{
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
189 unsigned int length;
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
192} vex_prefix;
193
252b5132 194/* 'md_assemble ()' gathers together information and puts it into a
47926f60 195 i386_insn. */
252b5132 196
520dc8e8
AM		 197union i386_op
198 {
199 expressionS *disps;
200 expressionS *imms;
201 const reg_entry *regs;
202 };
203
252b5132
RH		 204struct _i386_insn
205 {
47926f60 206 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 207 insn_template tm;
252b5132 208
7d5e4556
L		 209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
252b5132
RH		 211 char suffix;
212
47926f60 213 /* OPERANDS gives the number of given operands. */
252b5132
RH		 214 unsigned int operands;
215
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
47926f60 218 operands. */
252b5132
RH		 219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
220
221 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 222 use OP[i] for the corresponding operand. */
40fb9820 223 i386_operand_type types[MAX_OPERANDS];
252b5132 224
520dc8e8
AM		 225 /* Displacement expression, immediate expression, or register for each
226 operand. */
227 union i386_op op[MAX_OPERANDS];
252b5132 228
3e73aa7c
JH		 229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231#define Operand_PCrel 1
232
252b5132 233 /* Relocation type for operand */
f86103b7 234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 235
252b5132
RH		 236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
241
242 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 243 explicit segment overrides are given. */
ce8a8b2f 244 const seg_entry *seg[2];
252b5132
RH		 245
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
250
251 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 252 addressing modes of this insn are encoded. */
252b5132 253 modrm_byte rm;
3e73aa7c 254 rex_byte rex;
252b5132 255 sib_byte sib;
c0f3af97 256 vex_prefix vex;
b6169b20
L		 257
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
252b5132
RH		 260 };
261
262typedef struct _i386_insn i386_insn;
263
264/* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
32137342 266const char extra_symbol_chars[] = "*%-(["
252b5132 267#ifdef LEX_AT
32137342
NC		 268 "@"
269#endif
270#ifdef LEX_QM
271 "?"
252b5132 272#endif
32137342 273 ;
252b5132 274
29b0f896
AM		 275#if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 277 && !defined (TE_GNU) \
29b0f896 278 && !defined (TE_LINUX) \
32137342 279 && !defined (TE_NETWARE) \
29b0f896
AM		 280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
252b5132 282/* This array holds the chars that always start a comment. If the
b3b91714
AM		 283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285const char *i386_comment_chars = "#/";
286#define SVR4_COMMENT_CHARS 1
252b5132 287#define PREFIX_SEPARATOR '\\'
252b5132 288
b3b91714
AM		 289#else
290const char *i386_comment_chars = "#";
291#define PREFIX_SEPARATOR '/'
292#endif
293
252b5132
RH		 294/* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 298 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
252b5132 301 '/' isn't otherwise defined. */
b3b91714 302const char line_comment_chars[] = "#/";
252b5132 303
63a0b638 304const char line_separator_chars[] = ";";
252b5132 305
ce8a8b2f
AM		 306/* Chars that can be used to separate mant from exp in floating point
307 nums. */
252b5132
RH		 308const char EXP_CHARS[] = "eE";
309
ce8a8b2f
AM		 310/* Chars that mean this number is a floating point constant
311 As in 0f12.456
312 or 0d1.2345e12. */
252b5132
RH		 313const char FLT_CHARS[] = "fFdDxX";
314
ce8a8b2f 315/* Tables for lexical analysis. */
252b5132
RH		 316static char mnemonic_chars[256];
317static char register_chars[256];
318static char operand_chars[256];
319static char identifier_chars[256];
320static char digit_chars[256];
321
ce8a8b2f 322/* Lexical macros. */
252b5132
RH		 323#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324#define is_operand_char(x) (operand_chars[(unsigned char) x])
325#define is_register_char(x) (register_chars[(unsigned char) x])
326#define is_space_char(x) ((x) == ' ')
327#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328#define is_digit_char(x) (digit_chars[(unsigned char) x])
329
0234cb7c 330/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 331static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
332
333/* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
47926f60 336 assembler instruction). */
252b5132 337static char save_stack[32];
ce8a8b2f 338static char *save_stack_p;
252b5132
RH		 339#define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341#define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
343
47926f60 344/* The instruction we're assembling. */
252b5132
RH		 345static i386_insn i;
346
347/* Possible templates for current insn. */
348static const templates *current_templates;
349
31b2323c
L		 350/* Per instruction expressionS buffers: max displacements & immediates. */
351static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
352static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 353
47926f60 354/* Current operand we are working on. */
ee86248c 355static int this_operand = -1;
252b5132 356
3e73aa7c
JH		 357/* We support four different modes. FLAG_CODE variable is used to distinguish
358 these. */
359
360enum flag_code {
361 CODE_32BIT,
362 CODE_16BIT,
363 CODE_64BIT };
364
365static enum flag_code flag_code;
4fa24527 366static unsigned int object_64bit;
3e73aa7c
JH		 367static int use_rela_relocations = 0;
368
369/* The names used to print error messages. */
b77a7acd 370static const char *flag_code_names[] =
3e73aa7c
JH		 371 {
372 "32",
373 "16",
374 "64"
375 };
252b5132 376
47926f60
KH		 377/* 1 for intel syntax,
378 0 if att syntax. */
379static int intel_syntax = 0;
252b5132 380
1efbbeb4
L		 381/* 1 for intel mnemonic,
382 0 if att mnemonic. */
383static int intel_mnemonic = !SYSV386_COMPAT;
384
5209009a 385/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 386static int old_gcc = OLDGCC_COMPAT;
387
a60de03c
JB		 388/* 1 if pseudo registers are permitted. */
389static int allow_pseudo_reg = 0;
390
47926f60
KH		 391/* 1 if register prefix % not required. */
392static int allow_naked_reg = 0;
252b5132 393
ba104c83 394/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 395static int allow_index_reg = 0;
396
daf50ae7
L		 397static enum
398 {
399 sse_check_none = 0,
400 sse_check_warning,
401 sse_check_error
402 }
403sse_check;
404
2ca3ace5
L		 405/* Register prefix used for error message. */
406static const char *register_prefix = "%";
407
47926f60
KH		 408/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411static char stackop_size = '\0';
eecb386c 412
12b55ccc
L		 413/* Non-zero to optimize code alignment. */
414int optimize_align_code = 1;
415
47926f60
KH		 416/* Non-zero to quieten some warnings. */
417static int quiet_warnings = 0;
a38cf1db 418
47926f60
KH		 419/* CPU name. */
420static const char *cpu_arch_name = NULL;
6305a203 421static char *cpu_sub_arch_name = NULL;
a38cf1db 422
47926f60 423/* CPU feature flags. */
40fb9820
L		 424static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
425
ccc9c027
L		 426/* If we have selected a cpu we are generating instructions for. */
427static int cpu_arch_tune_set = 0;
428
9103f4f4 429/* Cpu we are generating instructions for. */
fbf3f584 430enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 431
432/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 433static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 434
ccc9c027 435/* CPU instruction set architecture used. */
fbf3f584 436enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 437
9103f4f4 438/* CPU feature flags of instruction set architecture used. */
fbf3f584 439i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 440
fddf5b5b
AM		 441/* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443static unsigned int no_cond_jump_promotion = 0;
444
c0f3af97
L		 445/* Encode SSE instructions with VEX prefix. */
446static unsigned int sse2avx;
447
29b0f896 448/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 449static symbolS *GOT_symbol;
29b0f896 450
a4447b93
RH		 451/* The dwarf2 return column, adjusted for 32 or 64 bit. */
452unsigned int x86_dwarf2_return_column;
453
454/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455int x86_cie_data_alignment;
456
252b5132 457/* Interface to relax_segment.
fddf5b5b
AM		 458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
252b5132 461
47926f60 462/* Types. */
93c2a809
AM		 463#define UNCOND_JUMP 0
464#define COND_JUMP 1
465#define COND_JUMP86 2
fddf5b5b 466
47926f60 467/* Sizes. */
252b5132
RH		 468#define CODE16 1
469#define SMALL 0
29b0f896 470#define SMALL16 (SMALL | CODE16)
252b5132 471#define BIG 2
29b0f896 472#define BIG16 (BIG | CODE16)
252b5132
RH		 473
474#ifndef INLINE
475#ifdef __GNUC__
476#define INLINE __inline__
477#else
478#define INLINE
479#endif
480#endif
481
fddf5b5b
AM		 482#define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484#define TYPE_FROM_RELAX_STATE(s) \
485 ((s) >> 2)
486#define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 488
489/* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
496
497const relax_typeS md_relax_table[] =
498{
24eab124
AM		 499 /* The fields are:
500 1) most positive reach of this state,
501 2) most negative reach of this state,
93c2a809 502 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 503 4) which index into the table to try if we can't fit into this one. */
252b5132 504
fddf5b5b 505 /* UNCOND_JUMP states. */
93c2a809
AM		 506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
252b5132 510 {0, 0, 4, 0},
93c2a809
AM		 511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 513 {0, 0, 2, 0},
514
93c2a809
AM		 515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
520 {0, 0, 5, 0},
fddf5b5b 521 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 522 1 extra opcode byte, 2 displacement bytes. */
523 {0, 0, 3, 0},
524
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
530 {0, 0, 5, 0},
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
533 {0, 0, 4, 0}
252b5132
RH		 534};
535
9103f4f4
L		 536static const arch_entry cpu_arch[] =
537{
6305a203
L		 538 { "generic32", PROCESSOR_GENERIC32,
539 CPU_GENERIC32_FLAGS },
540 { "generic64", PROCESSOR_GENERIC64,
541 CPU_GENERIC64_FLAGS },
542 { "i8086", PROCESSOR_UNKNOWN,
543 CPU_NONE_FLAGS },
544 { "i186", PROCESSOR_UNKNOWN,
545 CPU_I186_FLAGS },
546 { "i286", PROCESSOR_UNKNOWN,
547 CPU_I286_FLAGS },
548 { "i386", PROCESSOR_I386,
549 CPU_I386_FLAGS },
550 { "i486", PROCESSOR_I486,
551 CPU_I486_FLAGS },
552 { "i586", PROCESSOR_PENTIUM,
553 CPU_I586_FLAGS },
554 { "i686", PROCESSOR_PENTIUMPRO,
555 CPU_I686_FLAGS },
556 { "pentium", PROCESSOR_PENTIUM,
557 CPU_I586_FLAGS },
558 { "pentiumpro", PROCESSOR_PENTIUMPRO,
559 CPU_I686_FLAGS },
560 { "pentiumii", PROCESSOR_PENTIUMPRO,
561 CPU_P2_FLAGS },
562 { "pentiumiii",PROCESSOR_PENTIUMPRO,
563 CPU_P3_FLAGS },
564 { "pentium4", PROCESSOR_PENTIUM4,
565 CPU_P4_FLAGS },
566 { "prescott", PROCESSOR_NOCONA,
567 CPU_CORE_FLAGS },
568 { "nocona", PROCESSOR_NOCONA,
569 CPU_NOCONA_FLAGS },
570 { "yonah", PROCESSOR_CORE,
571 CPU_CORE_FLAGS },
572 { "core", PROCESSOR_CORE,
573 CPU_CORE_FLAGS },
574 { "merom", PROCESSOR_CORE2,
575 CPU_CORE2_FLAGS },
576 { "core2", PROCESSOR_CORE2,
577 CPU_CORE2_FLAGS },
bd5295b2
L		 578 { "corei7", PROCESSOR_COREI7,
579 CPU_COREI7_FLAGS },
3632d14b 580 { "l1om", PROCESSOR_L1OM,
8a9036a4 581 CPU_L1OM_FLAGS },
6305a203
L		 582 { "k6", PROCESSOR_K6,
583 CPU_K6_FLAGS },
584 { "k6_2", PROCESSOR_K6,
585 CPU_K6_2_FLAGS },
586 { "athlon", PROCESSOR_ATHLON,
587 CPU_ATHLON_FLAGS },
588 { "sledgehammer", PROCESSOR_K8,
589 CPU_K8_FLAGS },
590 { "opteron", PROCESSOR_K8,
591 CPU_K8_FLAGS },
592 { "k8", PROCESSOR_K8,
593 CPU_K8_FLAGS },
594 { "amdfam10", PROCESSOR_AMDFAM10,
595 CPU_AMDFAM10_FLAGS },
309d3373
JB		 596 { ".8087", PROCESSOR_UNKNOWN,
597 CPU_8087_FLAGS },
598 { ".287", PROCESSOR_UNKNOWN,
599 CPU_287_FLAGS },
600 { ".387", PROCESSOR_UNKNOWN,
601 CPU_387_FLAGS },
602 { ".no87", PROCESSOR_UNKNOWN,
603 CPU_ANY87_FLAGS },
6305a203
L		 604 { ".mmx", PROCESSOR_UNKNOWN,
605 CPU_MMX_FLAGS },
309d3373
JB		 606 { ".nommx", PROCESSOR_UNKNOWN,
607 CPU_3DNOWA_FLAGS },
6305a203
L		 608 { ".sse", PROCESSOR_UNKNOWN,
609 CPU_SSE_FLAGS },
610 { ".sse2", PROCESSOR_UNKNOWN,
611 CPU_SSE2_FLAGS },
612 { ".sse3", PROCESSOR_UNKNOWN,
613 CPU_SSE3_FLAGS },
614 { ".ssse3", PROCESSOR_UNKNOWN,
615 CPU_SSSE3_FLAGS },
616 { ".sse4.1", PROCESSOR_UNKNOWN,
617 CPU_SSE4_1_FLAGS },
618 { ".sse4.2", PROCESSOR_UNKNOWN,
619 CPU_SSE4_2_FLAGS },
620 { ".sse4", PROCESSOR_UNKNOWN,
621 CPU_SSE4_2_FLAGS },
309d3373
JB		 622 { ".nosse", PROCESSOR_UNKNOWN,
623 CPU_ANY_SSE_FLAGS },
c0f3af97
L		 624 { ".avx", PROCESSOR_UNKNOWN,
625 CPU_AVX_FLAGS },
309d3373
JB		 626 { ".noavx", PROCESSOR_UNKNOWN,
627 CPU_ANY_AVX_FLAGS },
6305a203
L		 628 { ".vmx", PROCESSOR_UNKNOWN,
629 CPU_VMX_FLAGS },
630 { ".smx", PROCESSOR_UNKNOWN,
631 CPU_SMX_FLAGS },
f03fe4c1
L		 632 { ".xsave", PROCESSOR_UNKNOWN,
633 CPU_XSAVE_FLAGS },
c0f3af97
L		 634 { ".aes", PROCESSOR_UNKNOWN,
635 CPU_AES_FLAGS },
594ab6a3
L		 636 { ".pclmul", PROCESSOR_UNKNOWN,
637 CPU_PCLMUL_FLAGS },
c0f3af97 638 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 639 CPU_PCLMUL_FLAGS },
c0f3af97
L		 640 { ".fma", PROCESSOR_UNKNOWN,
641 CPU_FMA_FLAGS },
922d8de8
DR		 642 { ".fma4", PROCESSOR_UNKNOWN,
643 CPU_FMA4_FLAGS },
f88c9eb0
SP		 644 { ".lwp", PROCESSOR_UNKNOWN,
645 CPU_LWP_FLAGS },
f1f8f695
L		 646 { ".movbe", PROCESSOR_UNKNOWN,
647 CPU_MOVBE_FLAGS },
648 { ".ept", PROCESSOR_UNKNOWN,
649 CPU_EPT_FLAGS },
bd5295b2
L		 650 { ".clflush", PROCESSOR_UNKNOWN,
651 CPU_CLFLUSH_FLAGS },
652 { ".syscall", PROCESSOR_UNKNOWN,
653 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 654 { ".rdtscp", PROCESSOR_UNKNOWN,
655 CPU_RDTSCP_FLAGS },
6305a203
L		 656 { ".3dnow", PROCESSOR_UNKNOWN,
657 CPU_3DNOW_FLAGS },
658 { ".3dnowa", PROCESSOR_UNKNOWN,
659 CPU_3DNOWA_FLAGS },
660 { ".padlock", PROCESSOR_UNKNOWN,
661 CPU_PADLOCK_FLAGS },
662 { ".pacifica", PROCESSOR_UNKNOWN,
663 CPU_SVME_FLAGS },
664 { ".svme", PROCESSOR_UNKNOWN,
665 CPU_SVME_FLAGS },
666 { ".sse4a", PROCESSOR_UNKNOWN,
667 CPU_SSE4A_FLAGS },
668 { ".abm", PROCESSOR_UNKNOWN,
669 CPU_ABM_FLAGS },
e413e4e9
AM		 670};
671
704209c0 672#ifdef I386COFF
a6c24e68
NC		 673/* Like s_lcomm_internal in gas/read.c but the alignment string
674 is allowed to be optional. */
675
676static symbolS *
677pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
678{
679 addressT align = 0;
680
681 SKIP_WHITESPACE ();
682
7ab9ffdd 683 if (needs_align
a6c24e68
NC		 684 && *input_line_pointer == ',')
685 {
686 align = parse_align (needs_align - 1);
7ab9ffdd 687
a6c24e68
NC		 688 if (align == (addressT) -1)
689 return NULL;
690 }
691 else
692 {
693 if (size >= 8)
694 align = 3;
695 else if (size >= 4)
696 align = 2;
697 else if (size >= 2)
698 align = 1;
699 else
700 align = 0;
701 }
702
703 bss_alloc (symbolP, size, align);
704 return symbolP;
705}
706
704209c0 707static void
a6c24e68
NC		 708pe_lcomm (int needs_align)
709{
710 s_comm_internal (needs_align * 2, pe_lcomm_internal);
711}
704209c0 712#endif
a6c24e68 713
29b0f896
AM		 714const pseudo_typeS md_pseudo_table[] =
715{
716#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
717 {"align", s_align_bytes, 0},
718#else
719 {"align", s_align_ptwo, 0},
720#endif
721 {"arch", set_cpu_arch, 0},
722#ifndef I386COFF
723 {"bss", s_bss, 0},
a6c24e68
NC		 724#else
725 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 726#endif
727 {"ffloat", float_cons, 'f'},
728 {"dfloat", float_cons, 'd'},
729 {"tfloat", float_cons, 'x'},
730 {"value", cons, 2},
d182319b 731 {"slong", signed_cons, 4},
29b0f896
AM		 732 {"noopt", s_ignore, 0},
733 {"optim", s_ignore, 0},
734 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
735 {"code16", set_code_flag, CODE_16BIT},
736 {"code32", set_code_flag, CODE_32BIT},
737 {"code64", set_code_flag, CODE_64BIT},
738 {"intel_syntax", set_intel_syntax, 1},
739 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 740 {"intel_mnemonic", set_intel_mnemonic, 1},
741 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 742 {"allow_index_reg", set_allow_index_reg, 1},
743 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 744 {"sse_check", set_sse_check, 0},
3b22753a
L		 745#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
746 {"largecomm", handle_large_common, 0},
07a53e5c 747#else
e3bb37b5 748 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 749 {"loc", dwarf2_directive_loc, 0},
750 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 751#endif
6482c264
NC		 752#ifdef TE_PE
753 {"secrel32", pe_directive_secrel, 0},
754#endif
29b0f896
AM		 755 {0, 0, 0}
756};
757
758/* For interface with expression (). */
759extern char *input_line_pointer;
760
761/* Hash table for instruction mnemonic lookup. */
762static struct hash_control *op_hash;
763
764/* Hash table for register lookup. */
765static struct hash_control *reg_hash;
766\f
252b5132 767void
e3bb37b5 768i386_align_code (fragS *fragP, int count)
252b5132 769{
ce8a8b2f
AM		 770 /* Various efficient no-op patterns for aligning code labels.
771 Note: Don't try to assemble the instructions in the comments.
772 0L and 0w are not legal. */
252b5132
RH		 773 static const char f32_1[] =
774 {0x90}; /* nop */
775 static const char f32_2[] =
ccc9c027 776 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 777 static const char f32_3[] =
778 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
779 static const char f32_4[] =
780 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
781 static const char f32_5[] =
782 {0x90, /* nop */
783 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
784 static const char f32_6[] =
785 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
786 static const char f32_7[] =
787 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
788 static const char f32_8[] =
789 {0x90, /* nop */
790 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
791 static const char f32_9[] =
792 {0x89,0xf6, /* movl %esi,%esi */
793 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
794 static const char f32_10[] =
795 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
796 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
797 static const char f32_11[] =
798 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
799 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
800 static const char f32_12[] =
801 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
802 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
803 static const char f32_13[] =
804 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
805 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
806 static const char f32_14[] =
807 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
808 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 809 static const char f16_3[] =
810 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 811 static const char f16_4[] =
812 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
813 static const char f16_5[] =
814 {0x90, /* nop */
815 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
816 static const char f16_6[] =
817 {0x89,0xf6, /* mov %si,%si */
818 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
819 static const char f16_7[] =
820 {0x8d,0x74,0x00, /* lea 0(%si),%si */
821 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
822 static const char f16_8[] =
823 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
824 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 825 static const char jump_31[] =
826 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
828 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
829 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 830 static const char *const f32_patt[] = {
831 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 832 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 833 };
834 static const char *const f16_patt[] = {
76bc74dc 835 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 836 };
ccc9c027
L		 837 /* nopl (%[re]ax) */
838 static const char alt_3[] =
839 {0x0f,0x1f,0x00};
840 /* nopl 0(%[re]ax) */
841 static const char alt_4[] =
842 {0x0f,0x1f,0x40,0x00};
843 /* nopl 0(%[re]ax,%[re]ax,1) */
844 static const char alt_5[] =
845 {0x0f,0x1f,0x44,0x00,0x00};
846 /* nopw 0(%[re]ax,%[re]ax,1) */
847 static const char alt_6[] =
848 {0x66,0x0f,0x1f,0x44,0x00,0x00};
849 /* nopl 0L(%[re]ax) */
850 static const char alt_7[] =
851 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
852 /* nopl 0L(%[re]ax,%[re]ax,1) */
853 static const char alt_8[] =
854 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
855 /* nopw 0L(%[re]ax,%[re]ax,1) */
856 static const char alt_9[] =
857 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_10[] =
860 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
861 /* data16
862 nopw %cs:0L(%[re]ax,%[re]ax,1) */
863 static const char alt_long_11[] =
864 {0x66,
865 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 /* data16
867 data16
868 nopw %cs:0L(%[re]ax,%[re]ax,1) */
869 static const char alt_long_12[] =
870 {0x66,
871 0x66,
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 /* data16
874 data16
875 data16
876 nopw %cs:0L(%[re]ax,%[re]ax,1) */
877 static const char alt_long_13[] =
878 {0x66,
879 0x66,
880 0x66,
881 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
882 /* data16
883 data16
884 data16
885 data16
886 nopw %cs:0L(%[re]ax,%[re]ax,1) */
887 static const char alt_long_14[] =
888 {0x66,
889 0x66,
890 0x66,
891 0x66,
892 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
893 /* data16
894 data16
895 data16
896 data16
897 data16
898 nopw %cs:0L(%[re]ax,%[re]ax,1) */
899 static const char alt_long_15[] =
900 {0x66,
901 0x66,
902 0x66,
903 0x66,
904 0x66,
905 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
906 /* nopl 0(%[re]ax,%[re]ax,1)
907 nopw 0(%[re]ax,%[re]ax,1) */
908 static const char alt_short_11[] =
909 {0x0f,0x1f,0x44,0x00,0x00,
910 0x66,0x0f,0x1f,0x44,0x00,0x00};
911 /* nopw 0(%[re]ax,%[re]ax,1)
912 nopw 0(%[re]ax,%[re]ax,1) */
913 static const char alt_short_12[] =
914 {0x66,0x0f,0x1f,0x44,0x00,0x00,
915 0x66,0x0f,0x1f,0x44,0x00,0x00};
916 /* nopw 0(%[re]ax,%[re]ax,1)
917 nopl 0L(%[re]ax) */
918 static const char alt_short_13[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00,
920 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 /* nopl 0L(%[re]ax)
922 nopl 0L(%[re]ax) */
923 static const char alt_short_14[] =
924 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
925 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
926 /* nopl 0L(%[re]ax)
927 nopl 0L(%[re]ax,%[re]ax,1) */
928 static const char alt_short_15[] =
929 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
930 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 static const char *const alt_short_patt[] = {
932 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
933 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
934 alt_short_14, alt_short_15
935 };
936 static const char *const alt_long_patt[] = {
937 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
938 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
939 alt_long_14, alt_long_15
940 };
252b5132 941
76bc74dc
L		 942 /* Only align for at least a positive non-zero boundary. */
943 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 944 return;
3e73aa7c 945
ccc9c027
L		 946 /* We need to decide which NOP sequence to use for 32bit and
947 64bit. When -mtune= is used:
4eed87de 948
76bc74dc
L		 949 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
950 PROCESSOR_GENERIC32, f32_patt will be used.
951 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 952 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
953 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 954 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
955 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 956
76bc74dc
L		 957 When -mtune= isn't used, alt_long_patt will be used if
958 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
959 be used.
ccc9c027
L		 960
961 When -march= or .arch is used, we can't use anything beyond
962 cpu_arch_isa_flags. */
963
964 if (flag_code == CODE_16BIT)
965 {
ccc9c027 966 if (count > 8)
33fef721 967 {
76bc74dc
L		 968 memcpy (fragP->fr_literal + fragP->fr_fix,
969 jump_31, count);
970 /* Adjust jump offset. */
971 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 972 }
76bc74dc
L		 973 else
974 memcpy (fragP->fr_literal + fragP->fr_fix,
975 f16_patt[count - 1], count);
252b5132 976 }
33fef721 977 else
ccc9c027
L		 978 {
979 const char *const *patt = NULL;
980
fbf3f584 981 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 982 {
983 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
984 switch (cpu_arch_tune)
985 {
986 case PROCESSOR_UNKNOWN:
987 /* We use cpu_arch_isa_flags to check if we SHOULD
988 optimize for Cpu686. */
fbf3f584 989 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 990 patt = alt_long_patt;
ccc9c027
L		 991 else
992 patt = f32_patt;
993 break;
ccc9c027
L		 994 case PROCESSOR_PENTIUMPRO:
995 case PROCESSOR_PENTIUM4:
996 case PROCESSOR_NOCONA:
ef05d495 997 case PROCESSOR_CORE:
76bc74dc 998 case PROCESSOR_CORE2:
bd5295b2 999 case PROCESSOR_COREI7:
3632d14b 1000 case PROCESSOR_L1OM:
76bc74dc
L		 1001 case PROCESSOR_GENERIC64:
1002 patt = alt_long_patt;
1003 break;
ccc9c027
L		 1004 case PROCESSOR_K6:
1005 case PROCESSOR_ATHLON:
1006 case PROCESSOR_K8:
4eed87de 1007 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1008 patt = alt_short_patt;
1009 break;
76bc74dc 1010 case PROCESSOR_I386:
ccc9c027
L		 1011 case PROCESSOR_I486:
1012 case PROCESSOR_PENTIUM:
1013 case PROCESSOR_GENERIC32:
1014 patt = f32_patt;
1015 break;
4eed87de 1016 }
ccc9c027
L		 1017 }
1018 else
1019 {
fbf3f584 1020 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1021 {
1022 case PROCESSOR_UNKNOWN:
e6a14101 1023 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1024 PROCESSOR_UNKNOWN. */
1025 abort ();
1026 break;
1027
76bc74dc 1028 case PROCESSOR_I386:
ccc9c027
L		 1029 case PROCESSOR_I486:
1030 case PROCESSOR_PENTIUM:
ccc9c027
L		 1031 case PROCESSOR_K6:
1032 case PROCESSOR_ATHLON:
1033 case PROCESSOR_K8:
4eed87de 1034 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1035 case PROCESSOR_GENERIC32:
1036 /* We use cpu_arch_isa_flags to check if we CAN optimize
1037 for Cpu686. */
fbf3f584 1038 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1039 patt = alt_short_patt;
1040 else
1041 patt = f32_patt;
1042 break;
76bc74dc
L		 1043 case PROCESSOR_PENTIUMPRO:
1044 case PROCESSOR_PENTIUM4:
1045 case PROCESSOR_NOCONA:
1046 case PROCESSOR_CORE:
ef05d495 1047 case PROCESSOR_CORE2:
bd5295b2 1048 case PROCESSOR_COREI7:
3632d14b 1049 case PROCESSOR_L1OM:
fbf3f584 1050 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1051 patt = alt_long_patt;
1052 else
1053 patt = f32_patt;
1054 break;
1055 case PROCESSOR_GENERIC64:
76bc74dc 1056 patt = alt_long_patt;
ccc9c027 1057 break;
4eed87de 1058 }
ccc9c027
L		 1059 }
1060
76bc74dc
L		 1061 if (patt == f32_patt)
1062 {
1063 /* If the padding is less than 15 bytes, we use the normal
1064 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1065 its offset. */
1066 int limit;
76ba9986 1067
711eedef
L		 1068 /* For 64bit, the limit is 3 bytes. */
1069 if (flag_code == CODE_64BIT
1070 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1071 limit = 3;
1072 else
1073 limit = 15;
1074 if (count < limit)
76bc74dc
L		 1075 memcpy (fragP->fr_literal + fragP->fr_fix,
1076 patt[count - 1], count);
1077 else
1078 {
1079 memcpy (fragP->fr_literal + fragP->fr_fix,
1080 jump_31, count);
1081 /* Adjust jump offset. */
1082 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1083 }
1084 }
1085 else
1086 {
1087 /* Maximum length of an instruction is 15 byte. If the
1088 padding is greater than 15 bytes and we don't use jump,
1089 we have to break it into smaller pieces. */
1090 int padding = count;
1091 while (padding > 15)
1092 {
1093 padding -= 15;
1094 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1095 patt [14], 15);
1096 }
1097
1098 if (padding)
1099 memcpy (fragP->fr_literal + fragP->fr_fix,
1100 patt [padding - 1], padding);
1101 }
ccc9c027 1102 }
33fef721 1103 fragP->fr_var = count;
252b5132
RH		 1104}
1105
c6fb90c8 1106static INLINE int
0dfbf9d7 1107operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1108{
0dfbf9d7 1109 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1110 {
1111 case 3:
0dfbf9d7 1112 if (x->array[2])
c6fb90c8
L		 1113 return 0;
1114 case 2:
0dfbf9d7 1115 if (x->array[1])
c6fb90c8
L		 1116 return 0;
1117 case 1:
0dfbf9d7 1118 return !x->array[0];
c6fb90c8
L		 1119 default:
1120 abort ();
1121 }
40fb9820
L		 1122}
1123
c6fb90c8 1124static INLINE void
0dfbf9d7 1125operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1126{
0dfbf9d7 1127 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1128 {
1129 case 3:
0dfbf9d7 1130 x->array[2] = v;
c6fb90c8 1131 case 2:
0dfbf9d7 1132 x->array[1] = v;
c6fb90c8 1133 case 1:
0dfbf9d7 1134 x->array[0] = v;
c6fb90c8
L		 1135 break;
1136 default:
1137 abort ();
1138 }
1139}
40fb9820 1140
c6fb90c8 1141static INLINE int
0dfbf9d7
L		 1142operand_type_equal (const union i386_operand_type *x,
1143 const union i386_operand_type *y)
c6fb90c8 1144{
0dfbf9d7 1145 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1146 {
1147 case 3:
0dfbf9d7 1148 if (x->array[2] != y->array[2])
c6fb90c8
L		 1149 return 0;
1150 case 2:
0dfbf9d7 1151 if (x->array[1] != y->array[1])
c6fb90c8
L		 1152 return 0;
1153 case 1:
0dfbf9d7 1154 return x->array[0] == y->array[0];
c6fb90c8
L		 1155 break;
1156 default:
1157 abort ();
1158 }
1159}
40fb9820 1160
0dfbf9d7
L		 1161static INLINE int
1162cpu_flags_all_zero (const union i386_cpu_flags *x)
1163{
1164 switch (ARRAY_SIZE(x->array))
1165 {
1166 case 3:
1167 if (x->array[2])
1168 return 0;
1169 case 2:
1170 if (x->array[1])
1171 return 0;
1172 case 1:
1173 return !x->array[0];
1174 default:
1175 abort ();
1176 }
1177}
1178
1179static INLINE void
1180cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1181{
1182 switch (ARRAY_SIZE(x->array))
1183 {
1184 case 3:
1185 x->array[2] = v;
1186 case 2:
1187 x->array[1] = v;
1188 case 1:
1189 x->array[0] = v;
1190 break;
1191 default:
1192 abort ();
1193 }
1194}
1195
1196static INLINE int
1197cpu_flags_equal (const union i386_cpu_flags *x,
1198 const union i386_cpu_flags *y)
1199{
1200 switch (ARRAY_SIZE(x->array))
1201 {
1202 case 3:
1203 if (x->array[2] != y->array[2])
1204 return 0;
1205 case 2:
1206 if (x->array[1] != y->array[1])
1207 return 0;
1208 case 1:
1209 return x->array[0] == y->array[0];
1210 break;
1211 default:
1212 abort ();
1213 }
1214}
c6fb90c8
L		 1215
1216static INLINE int
1217cpu_flags_check_cpu64 (i386_cpu_flags f)
1218{
1219 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1220 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1221}
1222
c6fb90c8
L		 1223static INLINE i386_cpu_flags
1224cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1225{
c6fb90c8
L		 1226 switch (ARRAY_SIZE (x.array))
1227 {
1228 case 3:
1229 x.array [2] &= y.array [2];
1230 case 2:
1231 x.array [1] &= y.array [1];
1232 case 1:
1233 x.array [0] &= y.array [0];
1234 break;
1235 default:
1236 abort ();
1237 }
1238 return x;
1239}
40fb9820 1240
c6fb90c8
L		 1241static INLINE i386_cpu_flags
1242cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1243{
c6fb90c8 1244 switch (ARRAY_SIZE (x.array))
40fb9820 1245 {
c6fb90c8
L		 1246 case 3:
1247 x.array [2] |= y.array [2];
1248 case 2:
1249 x.array [1] |= y.array [1];
1250 case 1:
1251 x.array [0] |= y.array [0];
40fb9820
L		 1252 break;
1253 default:
1254 abort ();
1255 }
40fb9820
L		 1256 return x;
1257}
1258
309d3373
JB		 1259static INLINE i386_cpu_flags
1260cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1261{
1262 switch (ARRAY_SIZE (x.array))
1263 {
1264 case 3:
1265 x.array [2] &= ~y.array [2];
1266 case 2:
1267 x.array [1] &= ~y.array [1];
1268 case 1:
1269 x.array [0] &= ~y.array [0];
1270 break;
1271 default:
1272 abort ();
1273 }
1274 return x;
1275}
1276
c0f3af97
L		 1277#define CPU_FLAGS_ARCH_MATCH 0x1
1278#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1279#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1280#define CPU_FLAGS_PCLMUL_MATCH 0x8
1281#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1282
a5ff0eb2 1283#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1284 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1285 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1286#define CPU_FLAGS_PERFECT_MATCH \
1287 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1288
1289/* Return CPU flags match bits. */
3629bb00 1290
40fb9820 1291static int
d3ce72d0 1292cpu_flags_match (const insn_template *t)
40fb9820 1293{
c0f3af97
L		 1294 i386_cpu_flags x = t->cpu_flags;
1295 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1296
1297 x.bitfield.cpu64 = 0;
1298 x.bitfield.cpuno64 = 0;
1299
0dfbf9d7 1300 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1301 {
1302 /* This instruction is available on all archs. */
1303 match |= CPU_FLAGS_32BIT_MATCH;
1304 }
3629bb00
L		 1305 else
1306 {
c0f3af97 1307 /* This instruction is available only on some archs. */
3629bb00
L		 1308 i386_cpu_flags cpu = cpu_arch_flags;
1309
1310 cpu.bitfield.cpu64 = 0;
1311 cpu.bitfield.cpuno64 = 0;
1312 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1313 if (!cpu_flags_all_zero (&cpu))
1314 {
a5ff0eb2
L		 1315 if (x.bitfield.cpuavx)
1316 {
ce2f5b3c 1317 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1318 if (cpu.bitfield.cpuavx)
1319 {
1320 /* Check SSE2AVX. */
1321 if (!t->opcode_modifier.sse2avx|| sse2avx)
1322 {
1323 match |= (CPU_FLAGS_ARCH_MATCH
1324 | CPU_FLAGS_AVX_MATCH);
1325 /* Check AES. */
1326 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1327 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1328 /* Check PCLMUL. */
1329 if (!x.bitfield.cpupclmul
1330 || cpu.bitfield.cpupclmul)
1331 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1332 }
1333 }
1334 else
1335 match |= CPU_FLAGS_ARCH_MATCH;
1336 }
1337 else
c0f3af97
L		 1338 match |= CPU_FLAGS_32BIT_MATCH;
1339 }
3629bb00 1340 }
c0f3af97 1341 return match;
40fb9820
L		 1342}
1343
c6fb90c8
L		 1344static INLINE i386_operand_type
1345operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1346{
c6fb90c8
L		 1347 switch (ARRAY_SIZE (x.array))
1348 {
1349 case 3:
1350 x.array [2] &= y.array [2];
1351 case 2:
1352 x.array [1] &= y.array [1];
1353 case 1:
1354 x.array [0] &= y.array [0];
1355 break;
1356 default:
1357 abort ();
1358 }
1359 return x;
40fb9820
L		 1360}
1361
c6fb90c8
L		 1362static INLINE i386_operand_type
1363operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1364{
c6fb90c8 1365 switch (ARRAY_SIZE (x.array))
40fb9820 1366 {
c6fb90c8
L		 1367 case 3:
1368 x.array [2] |= y.array [2];
1369 case 2:
1370 x.array [1] |= y.array [1];
1371 case 1:
1372 x.array [0] |= y.array [0];
40fb9820
L		 1373 break;
1374 default:
1375 abort ();
1376 }
c6fb90c8
L		 1377 return x;
1378}
40fb9820 1379
c6fb90c8
L		 1380static INLINE i386_operand_type
1381operand_type_xor (i386_operand_type x, i386_operand_type y)
1382{
1383 switch (ARRAY_SIZE (x.array))
1384 {
1385 case 3:
1386 x.array [2] ^= y.array [2];
1387 case 2:
1388 x.array [1] ^= y.array [1];
1389 case 1:
1390 x.array [0] ^= y.array [0];
1391 break;
1392 default:
1393 abort ();
1394 }
40fb9820
L		 1395 return x;
1396}
1397
1398static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1399static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1400static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1401static const i386_operand_type inoutportreg
1402 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1403static const i386_operand_type reg16_inoutportreg
1404 = OPERAND_TYPE_REG16_INOUTPORTREG;
1405static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1406static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1407static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1408static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1409static const i386_operand_type anydisp
1410 = OPERAND_TYPE_ANYDISP;
40fb9820 1411static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1412static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1413static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1414static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1415static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1416static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1417static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1418static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1419static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1420static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1421static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1422
1423enum operand_type
1424{
1425 reg,
40fb9820
L		 1426 imm,
1427 disp,
1428 anymem
1429};
1430
c6fb90c8 1431static INLINE int
40fb9820
L		 1432operand_type_check (i386_operand_type t, enum operand_type c)
1433{
1434 switch (c)
1435 {
1436 case reg:
1437 return (t.bitfield.reg8
1438 || t.bitfield.reg16
1439 || t.bitfield.reg32
1440 || t.bitfield.reg64);
1441
40fb9820
L		 1442 case imm:
1443 return (t.bitfield.imm8
1444 || t.bitfield.imm8s
1445 || t.bitfield.imm16
1446 || t.bitfield.imm32
1447 || t.bitfield.imm32s
1448 || t.bitfield.imm64);
1449
1450 case disp:
1451 return (t.bitfield.disp8
1452 || t.bitfield.disp16
1453 || t.bitfield.disp32
1454 || t.bitfield.disp32s
1455 || t.bitfield.disp64);
1456
1457 case anymem:
1458 return (t.bitfield.disp8
1459 || t.bitfield.disp16
1460 || t.bitfield.disp32
1461 || t.bitfield.disp32s
1462 || t.bitfield.disp64
1463 || t.bitfield.baseindex);
1464
1465 default:
1466 abort ();
1467 }
2cfe26b6
AM		 1468
1469 return 0;
40fb9820
L		 1470}
1471
5c07affc
L		 1472/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1473 operand J for instruction template T. */
1474
1475static INLINE int
d3ce72d0 1476match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1477{
1478 return !((i.types[j].bitfield.byte
1479 && !t->operand_types[j].bitfield.byte)
1480 || (i.types[j].bitfield.word
1481 && !t->operand_types[j].bitfield.word)
1482 || (i.types[j].bitfield.dword
1483 && !t->operand_types[j].bitfield.dword)
1484 || (i.types[j].bitfield.qword
1485 && !t->operand_types[j].bitfield.qword));
1486}
1487
1488/* Return 1 if there is no conflict in any size on operand J for
1489 instruction template T. */
1490
1491static INLINE int
d3ce72d0 1492match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1493{
1494 return (match_reg_size (t, j)
1495 && !((i.types[j].bitfield.unspecified
1496 && !t->operand_types[j].bitfield.unspecified)
1497 || (i.types[j].bitfield.fword
1498 && !t->operand_types[j].bitfield.fword)
1499 || (i.types[j].bitfield.tbyte
1500 && !t->operand_types[j].bitfield.tbyte)
1501 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1502 && !t->operand_types[j].bitfield.xmmword)
1503 || (i.types[j].bitfield.ymmword
1504 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1505}
1506
1507/* Return 1 if there is no size conflict on any operands for
1508 instruction template T. */
1509
1510static INLINE int
d3ce72d0 1511operand_size_match (const insn_template *t)
5c07affc
L		 1512{
1513 unsigned int j;
1514 int match = 1;
1515
1516 /* Don't check jump instructions. */
1517 if (t->opcode_modifier.jump
1518 || t->opcode_modifier.jumpbyte
1519 || t->opcode_modifier.jumpdword
1520 || t->opcode_modifier.jumpintersegment)
1521 return match;
1522
1523 /* Check memory and accumulator operand size. */
1524 for (j = 0; j < i.operands; j++)
1525 {
1526 if (t->operand_types[j].bitfield.anysize)
1527 continue;
1528
1529 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1530 {
1531 match = 0;
1532 break;
1533 }
1534
1535 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1536 {
1537 match = 0;
1538 break;
1539 }
1540 }
1541
1542 if (match
1543 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1544 return match;
1545
1546 /* Check reverse. */
9c2799c2 1547 gas_assert (i.operands == 2);
5c07affc
L		 1548
1549 match = 1;
1550 for (j = 0; j < 2; j++)
1551 {
1552 if (t->operand_types[j].bitfield.acc
1553 && !match_reg_size (t, j ? 0 : 1))
1554 {
1555 match = 0;
1556 break;
1557 }
1558
1559 if (i.types[j].bitfield.mem
1560 && !match_mem_size (t, j ? 0 : 1))
1561 {
1562 match = 0;
1563 break;
1564 }
1565 }
1566
1567 return match;
1568}
1569
c6fb90c8 1570static INLINE int
40fb9820
L		 1571operand_type_match (i386_operand_type overlap,
1572 i386_operand_type given)
1573{
1574 i386_operand_type temp = overlap;
1575
1576 temp.bitfield.jumpabsolute = 0;
7d5e4556 1577 temp.bitfield.unspecified = 0;
5c07affc
L		 1578 temp.bitfield.byte = 0;
1579 temp.bitfield.word = 0;
1580 temp.bitfield.dword = 0;
1581 temp.bitfield.fword = 0;
1582 temp.bitfield.qword = 0;
1583 temp.bitfield.tbyte = 0;
1584 temp.bitfield.xmmword = 0;
c0f3af97 1585 temp.bitfield.ymmword = 0;
0dfbf9d7 1586 if (operand_type_all_zero (&temp))
40fb9820
L		 1587 return 0;
1588
1589 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1590 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1591}
1592
7d5e4556 1593/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1594 unless the expected operand type register overlap is null.
1595 Note that Acc in a template matches every size of reg. */
1596
c6fb90c8 1597static INLINE int
40fb9820
L		 1598operand_type_register_match (i386_operand_type m0,
1599 i386_operand_type g0,
1600 i386_operand_type t0,
1601 i386_operand_type m1,
1602 i386_operand_type g1,
1603 i386_operand_type t1)
1604{
1605 if (!operand_type_check (g0, reg))
1606 return 1;
1607
1608 if (!operand_type_check (g1, reg))
1609 return 1;
1610
1611 if (g0.bitfield.reg8 == g1.bitfield.reg8
1612 && g0.bitfield.reg16 == g1.bitfield.reg16
1613 && g0.bitfield.reg32 == g1.bitfield.reg32
1614 && g0.bitfield.reg64 == g1.bitfield.reg64)
1615 return 1;
1616
1617 if (m0.bitfield.acc)
1618 {
1619 t0.bitfield.reg8 = 1;
1620 t0.bitfield.reg16 = 1;
1621 t0.bitfield.reg32 = 1;
1622 t0.bitfield.reg64 = 1;
1623 }
1624
1625 if (m1.bitfield.acc)
1626 {
1627 t1.bitfield.reg8 = 1;
1628 t1.bitfield.reg16 = 1;
1629 t1.bitfield.reg32 = 1;
1630 t1.bitfield.reg64 = 1;
1631 }
1632
1633 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1634 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1635 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1636 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1637}
1638
252b5132 1639static INLINE unsigned int
40fb9820 1640mode_from_disp_size (i386_operand_type t)
252b5132 1641{
40fb9820
L		 1642 if (t.bitfield.disp8)
1643 return 1;
1644 else if (t.bitfield.disp16
1645 || t.bitfield.disp32
1646 || t.bitfield.disp32s)
1647 return 2;
1648 else
1649 return 0;
252b5132
RH		 1650}
1651
1652static INLINE int
e3bb37b5 1653fits_in_signed_byte (offsetT num)
252b5132
RH		 1654{
1655 return (num >= -128) && (num <= 127);
47926f60 1656}
252b5132
RH		 1657
1658static INLINE int
e3bb37b5 1659fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1660{
1661 return (num & 0xff) == num;
47926f60 1662}
252b5132
RH		 1663
1664static INLINE int
e3bb37b5 1665fits_in_unsigned_word (offsetT num)
252b5132
RH		 1666{
1667 return (num & 0xffff) == num;
47926f60 1668}
252b5132
RH		 1669
1670static INLINE int
e3bb37b5 1671fits_in_signed_word (offsetT num)
252b5132
RH		 1672{
1673 return (-32768 <= num) && (num <= 32767);
47926f60 1674}
2a962e6d 1675
3e73aa7c 1676static INLINE int
e3bb37b5 1677fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1678{
1679#ifndef BFD64
1680 return 1;
1681#else
1682 return (!(((offsetT) -1 << 31) & num)
1683 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1684#endif
1685} /* fits_in_signed_long() */
2a962e6d 1686
3e73aa7c 1687static INLINE int
e3bb37b5 1688fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1689{
1690#ifndef BFD64
1691 return 1;
1692#else
1693 return (num & (((offsetT) 2 << 31) - 1)) == num;
1694#endif
1695} /* fits_in_unsigned_long() */
252b5132 1696
40fb9820 1697static i386_operand_type
e3bb37b5 1698smallest_imm_type (offsetT num)
252b5132 1699{
40fb9820 1700 i386_operand_type t;
7ab9ffdd 1701
0dfbf9d7 1702 operand_type_set (&t, 0);
40fb9820
L		 1703 t.bitfield.imm64 = 1;
1704
1705 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1706 {
1707 /* This code is disabled on the 486 because all the Imm1 forms
1708 in the opcode table are slower on the i486. They're the
1709 versions with the implicitly specified single-position
1710 displacement, which has another syntax if you really want to
1711 use that form. */
40fb9820
L		 1712 t.bitfield.imm1 = 1;
1713 t.bitfield.imm8 = 1;
1714 t.bitfield.imm8s = 1;
1715 t.bitfield.imm16 = 1;
1716 t.bitfield.imm32 = 1;
1717 t.bitfield.imm32s = 1;
1718 }
1719 else if (fits_in_signed_byte (num))
1720 {
1721 t.bitfield.imm8 = 1;
1722 t.bitfield.imm8s = 1;
1723 t.bitfield.imm16 = 1;
1724 t.bitfield.imm32 = 1;
1725 t.bitfield.imm32s = 1;
1726 }
1727 else if (fits_in_unsigned_byte (num))
1728 {
1729 t.bitfield.imm8 = 1;
1730 t.bitfield.imm16 = 1;
1731 t.bitfield.imm32 = 1;
1732 t.bitfield.imm32s = 1;
1733 }
1734 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1735 {
1736 t.bitfield.imm16 = 1;
1737 t.bitfield.imm32 = 1;
1738 t.bitfield.imm32s = 1;
1739 }
1740 else if (fits_in_signed_long (num))
1741 {
1742 t.bitfield.imm32 = 1;
1743 t.bitfield.imm32s = 1;
1744 }
1745 else if (fits_in_unsigned_long (num))
1746 t.bitfield.imm32 = 1;
1747
1748 return t;
47926f60 1749}
252b5132 1750
847f7ad4 1751static offsetT
e3bb37b5 1752offset_in_range (offsetT val, int size)
847f7ad4 1753{
508866be 1754 addressT mask;
ba2adb93 1755
847f7ad4
AM		 1756 switch (size)
1757 {
508866be
L		 1758 case 1: mask = ((addressT) 1 << 8) - 1; break;
1759 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1760 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1761#ifdef BFD64
1762 case 8: mask = ((addressT) 2 << 63) - 1; break;
1763#endif
47926f60 1764 default: abort ();
847f7ad4
AM		 1765 }
1766
9de868bf
L		 1767#ifdef BFD64
1768 /* If BFD64, sign extend val for 32bit address mode. */
1769 if (flag_code != CODE_64BIT
1770 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1771 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1772 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1773#endif
ba2adb93 1774
47926f60 1775 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1776 {
1777 char buf1[40], buf2[40];
1778
1779 sprint_value (buf1, val);
1780 sprint_value (buf2, val & mask);
1781 as_warn (_("%s shortened to %s"), buf1, buf2);
1782 }
1783 return val & mask;
1784}
1785
252b5132
RH		 1786/* Returns 0 if attempting to add a prefix where one from the same
1787 class already exists, 1 if non rep/repne added, 2 if rep/repne
1788 added. */
1789static int
e3bb37b5 1790add_prefix (unsigned int prefix)
252b5132
RH		 1791{
1792 int ret = 1;
b1905489 1793 unsigned int q;
252b5132 1794
29b0f896
AM		 1795 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1796 && flag_code == CODE_64BIT)
b1905489 1797 {
161a04f6
L		 1798 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1799 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1800 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1801 ret = 0;
1802 q = REX_PREFIX;
1803 }
3e73aa7c 1804 else
b1905489
JB		 1805 {
1806 switch (prefix)
1807 {
1808 default:
1809 abort ();
1810
1811 case CS_PREFIX_OPCODE:
1812 case DS_PREFIX_OPCODE:
1813 case ES_PREFIX_OPCODE:
1814 case FS_PREFIX_OPCODE:
1815 case GS_PREFIX_OPCODE:
1816 case SS_PREFIX_OPCODE:
1817 q = SEG_PREFIX;
1818 break;
1819
1820 case REPNE_PREFIX_OPCODE:
1821 case REPE_PREFIX_OPCODE:
1822 ret = 2;
1823 /* fall thru */
1824 case LOCK_PREFIX_OPCODE:
1825 q = LOCKREP_PREFIX;
1826 break;
1827
1828 case FWAIT_OPCODE:
1829 q = WAIT_PREFIX;
1830 break;
1831
1832 case ADDR_PREFIX_OPCODE:
1833 q = ADDR_PREFIX;
1834 break;
1835
1836 case DATA_PREFIX_OPCODE:
1837 q = DATA_PREFIX;
1838 break;
1839 }
1840 if (i.prefix[q] != 0)
1841 ret = 0;
1842 }
252b5132 1843
b1905489 1844 if (ret)
252b5132 1845 {
b1905489
JB		 1846 if (!i.prefix[q])
1847 ++i.prefixes;
1848 i.prefix[q] |= prefix;
252b5132 1849 }
b1905489
JB		 1850 else
1851 as_bad (_("same type of prefix used twice"));
252b5132 1852
252b5132
RH		 1853 return ret;
1854}
1855
1856static void
e3bb37b5 1857set_code_flag (int value)
eecb386c 1858{
1e9cc1c2 1859 flag_code = (enum flag_code) value;
40fb9820
L		 1860 if (flag_code == CODE_64BIT)
1861 {
1862 cpu_arch_flags.bitfield.cpu64 = 1;
1863 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1864 }
1865 else
1866 {
1867 cpu_arch_flags.bitfield.cpu64 = 0;
1868 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1869 }
1870 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1871 {
1872 as_bad (_("64bit mode not supported on this CPU."));
1873 }
40fb9820 1874 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1875 {
1876 as_bad (_("32bit mode not supported on this CPU."));
1877 }
eecb386c
AM		 1878 stackop_size = '\0';
1879}
1880
1881static void
e3bb37b5 1882set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1883{
1e9cc1c2 1884 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1885 if (flag_code != CODE_16BIT)
1886 abort ();
1887 cpu_arch_flags.bitfield.cpu64 = 0;
1888 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1889 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1890}
1891
1892static void
e3bb37b5 1893set_intel_syntax (int syntax_flag)
252b5132
RH		 1894{
1895 /* Find out if register prefixing is specified. */
1896 int ask_naked_reg = 0;
1897
1898 SKIP_WHITESPACE ();
29b0f896 1899 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1900 {
1901 char *string = input_line_pointer;
1902 int e = get_symbol_end ();
1903
47926f60 1904 if (strcmp (string, "prefix") == 0)
252b5132 1905 ask_naked_reg = 1;
47926f60 1906 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1907 ask_naked_reg = -1;
1908 else
d0b47220 1909 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1910 *input_line_pointer = e;
1911 }
1912 demand_empty_rest_of_line ();
c3332e24 1913
252b5132
RH		 1914 intel_syntax = syntax_flag;
1915
1916 if (ask_naked_reg == 0)
f86103b7
AM		 1917 allow_naked_reg = (intel_syntax
1918 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1919 else
1920 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1921
ee86248c 1922 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1923
e4a3b5a4 1924 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1925 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1926 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1927}
1928
1efbbeb4
L		 1929static void
1930set_intel_mnemonic (int mnemonic_flag)
1931{
e1d4d893 1932 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1933}
1934
db51cc60
L		 1935static void
1936set_allow_index_reg (int flag)
1937{
1938 allow_index_reg = flag;
1939}
1940
cb19c032
L		 1941static void
1942set_sse_check (int dummy ATTRIBUTE_UNUSED)
1943{
1944 SKIP_WHITESPACE ();
1945
1946 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1947 {
1948 char *string = input_line_pointer;
1949 int e = get_symbol_end ();
1950
1951 if (strcmp (string, "none") == 0)
1952 sse_check = sse_check_none;
1953 else if (strcmp (string, "warning") == 0)
1954 sse_check = sse_check_warning;
1955 else if (strcmp (string, "error") == 0)
1956 sse_check = sse_check_error;
1957 else
1958 as_bad (_("bad argument to sse_check directive."));
1959 *input_line_pointer = e;
1960 }
1961 else
1962 as_bad (_("missing argument for sse_check directive"));
1963
1964 demand_empty_rest_of_line ();
1965}
1966
8a9036a4
L		 1967static void
1968check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 1969 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 1970{
1971#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1972 static const char *arch;
1973
1974 /* Intel LIOM is only supported on ELF. */
1975 if (!IS_ELF)
1976 return;
1977
1978 if (!arch)
1979 {
1980 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1981 use default_arch. */
1982 arch = cpu_arch_name;
1983 if (!arch)
1984 arch = default_arch;
1985 }
1986
3632d14b 1987 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 1988 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 1989 || new_flag.bitfield.cpul1om)
8a9036a4 1990 return;
76ba9986 1991
8a9036a4
L		 1992 as_bad (_("`%s' is not supported on `%s'"), name, arch);
1993#endif
1994}
1995
e413e4e9 1996static void
e3bb37b5 1997set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1998{
47926f60 1999 SKIP_WHITESPACE ();
e413e4e9 2000
29b0f896 2001 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2002 {
2003 char *string = input_line_pointer;
2004 int e = get_symbol_end ();
9103f4f4 2005 unsigned int i;
40fb9820 2006 i386_cpu_flags flags;
e413e4e9 2007
9103f4f4 2008 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 2009 {
2010 if (strcmp (string, cpu_arch[i].name) == 0)
2011 {
8a9036a4
L		 2012 check_cpu_arch_compatible (string, cpu_arch[i].flags);
2013
5c6af06e
JB		 2014 if (*string != '.')
2015 {
2016 cpu_arch_name = cpu_arch[i].name;
2017 cpu_sub_arch_name = NULL;
40fb9820
L		 2018 cpu_arch_flags = cpu_arch[i].flags;
2019 if (flag_code == CODE_64BIT)
2020 {
2021 cpu_arch_flags.bitfield.cpu64 = 1;
2022 cpu_arch_flags.bitfield.cpuno64 = 0;
2023 }
2024 else
2025 {
2026 cpu_arch_flags.bitfield.cpu64 = 0;
2027 cpu_arch_flags.bitfield.cpuno64 = 1;
2028 }
ccc9c027 2029 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 2030 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 2031 if (!cpu_arch_tune_set)
2032 {
2033 cpu_arch_tune = cpu_arch_isa;
2034 cpu_arch_tune_flags = cpu_arch_isa_flags;
2035 }
5c6af06e
JB		 2036 break;
2037 }
40fb9820 2038
309d3373
JB		 2039 if (strncmp (string + 1, "no", 2))
2040 flags = cpu_flags_or (cpu_arch_flags,
2041 cpu_arch[i].flags);
2042 else
2043 flags = cpu_flags_and_not (cpu_arch_flags,
2044 cpu_arch[i].flags);
0dfbf9d7 2045 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2046 {
6305a203
L		 2047 if (cpu_sub_arch_name)
2048 {
2049 char *name = cpu_sub_arch_name;
2050 cpu_sub_arch_name = concat (name,
2051 cpu_arch[i].name,
1bf57e9f 2052 (const char *) NULL);
6305a203
L		 2053 free (name);
2054 }
2055 else
2056 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 2057 cpu_arch_flags = flags;
5c6af06e
JB		 2058 }
2059 *input_line_pointer = e;
2060 demand_empty_rest_of_line ();
2061 return;
e413e4e9
AM		 2062 }
2063 }
9103f4f4 2064 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2065 as_bad (_("no such architecture: `%s'"), string);
2066
2067 *input_line_pointer = e;
2068 }
2069 else
2070 as_bad (_("missing cpu architecture"));
2071
fddf5b5b
AM		 2072 no_cond_jump_promotion = 0;
2073 if (*input_line_pointer == ','
29b0f896 2074 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2075 {
2076 char *string = ++input_line_pointer;
2077 int e = get_symbol_end ();
2078
2079 if (strcmp (string, "nojumps") == 0)
2080 no_cond_jump_promotion = 1;
2081 else if (strcmp (string, "jumps") == 0)
2082 ;
2083 else
2084 as_bad (_("no such architecture modifier: `%s'"), string);
2085
2086 *input_line_pointer = e;
2087 }
2088
e413e4e9
AM		 2089 demand_empty_rest_of_line ();
2090}
2091
8a9036a4
L		 2092enum bfd_architecture
2093i386_arch (void)
2094{
3632d14b 2095 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2096 {
2097 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2098 || flag_code != CODE_64BIT)
2099 as_fatal (_("Intel L1OM is 64bit ELF only"));
2100 return bfd_arch_l1om;
2101 }
2102 else
2103 return bfd_arch_i386;
2104}
2105
b9d79e03
JH		 2106unsigned long
2107i386_mach ()
2108{
2109 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2110 {
3632d14b 2111 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2112 {
2113 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2114 as_fatal (_("Intel L1OM is 64bit ELF only"));
2115 return bfd_mach_l1om;
2116 }
2117 else
2118 return bfd_mach_x86_64;
2119 }
b9d79e03
JH		 2120 else if (!strcmp (default_arch, "i386"))
2121 return bfd_mach_i386_i386;
2122 else
2123 as_fatal (_("Unknown architecture"));
2124}
b9d79e03 2125\f
252b5132
RH		 2126void
2127md_begin ()
2128{
2129 const char *hash_err;
2130
47926f60 2131 /* Initialize op_hash hash table. */
252b5132
RH		 2132 op_hash = hash_new ();
2133
2134 {
d3ce72d0 2135 const insn_template *optab;
29b0f896 2136 templates *core_optab;
252b5132 2137
47926f60
KH		 2138 /* Setup for loop. */
2139 optab = i386_optab;
252b5132
RH		 2140 core_optab = (templates *) xmalloc (sizeof (templates));
2141 core_optab->start = optab;
2142
2143 while (1)
2144 {
2145 ++optab;
2146 if (optab->name == NULL
2147 || strcmp (optab->name, (optab - 1)->name) != 0)
2148 {
2149 /* different name --> ship out current template list;
47926f60 2150 add to hash table; & begin anew. */
252b5132
RH		 2151 core_optab->end = optab;
2152 hash_err = hash_insert (op_hash,
2153 (optab - 1)->name,
5a49b8ac 2154 (void *) core_optab);
252b5132
RH		 2155 if (hash_err)
2156 {
252b5132
RH		 2157 as_fatal (_("Internal Error: Can't hash %s: %s"),
2158 (optab - 1)->name,
2159 hash_err);
2160 }
2161 if (optab->name == NULL)
2162 break;
2163 core_optab = (templates *) xmalloc (sizeof (templates));
2164 core_optab->start = optab;
2165 }
2166 }
2167 }
2168
47926f60 2169 /* Initialize reg_hash hash table. */
252b5132
RH		 2170 reg_hash = hash_new ();
2171 {
29b0f896 2172 const reg_entry *regtab;
c3fe08fa 2173 unsigned int regtab_size = i386_regtab_size;
252b5132 2174
c3fe08fa 2175 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2176 {
5a49b8ac 2177 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2178 if (hash_err)
3e73aa7c
JH		 2179 as_fatal (_("Internal Error: Can't hash %s: %s"),
2180 regtab->reg_name,
2181 hash_err);
252b5132
RH		 2182 }
2183 }
2184
47926f60 2185 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2186 {
29b0f896
AM		 2187 int c;
2188 char *p;
252b5132
RH		 2189
2190 for (c = 0; c < 256; c++)
2191 {
3882b010 2192 if (ISDIGIT (c))
252b5132
RH		 2193 {
2194 digit_chars[c] = c;
2195 mnemonic_chars[c] = c;
2196 register_chars[c] = c;
2197 operand_chars[c] = c;
2198 }
3882b010 2199 else if (ISLOWER (c))
252b5132
RH		 2200 {
2201 mnemonic_chars[c] = c;
2202 register_chars[c] = c;
2203 operand_chars[c] = c;
2204 }
3882b010 2205 else if (ISUPPER (c))
252b5132 2206 {
3882b010 2207 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2208 register_chars[c] = mnemonic_chars[c];
2209 operand_chars[c] = c;
2210 }
2211
3882b010 2212 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2213 identifier_chars[c] = c;
2214 else if (c >= 128)
2215 {
2216 identifier_chars[c] = c;
2217 operand_chars[c] = c;
2218 }
2219 }
2220
2221#ifdef LEX_AT
2222 identifier_chars['@'] = '@';
32137342
NC		 2223#endif
2224#ifdef LEX_QM
2225 identifier_chars['?'] = '?';
2226 operand_chars['?'] = '?';
252b5132 2227#endif
252b5132 2228 digit_chars['-'] = '-';
c0f3af97 2229 mnemonic_chars['_'] = '_';
791fe849 2230 mnemonic_chars['-'] = '-';
0003779b 2231 mnemonic_chars['.'] = '.';
252b5132
RH		 2232 identifier_chars['_'] = '_';
2233 identifier_chars['.'] = '.';
2234
2235 for (p = operand_special_chars; *p != '\0'; p++)
2236 operand_chars[(unsigned char) *p] = *p;
2237 }
2238
2239#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2240 if (IS_ELF)
252b5132
RH		 2241 {
2242 record_alignment (text_section, 2);
2243 record_alignment (data_section, 2);
2244 record_alignment (bss_section, 2);
2245 }
2246#endif
a4447b93
RH		 2247
2248 if (flag_code == CODE_64BIT)
2249 {
2250 x86_dwarf2_return_column = 16;
2251 x86_cie_data_alignment = -8;
2252 }
2253 else
2254 {
2255 x86_dwarf2_return_column = 8;
2256 x86_cie_data_alignment = -4;
2257 }
252b5132
RH		 2258}
2259
2260void
e3bb37b5 2261i386_print_statistics (FILE *file)
252b5132
RH		 2262{
2263 hash_print_statistics (file, "i386 opcode", op_hash);
2264 hash_print_statistics (file, "i386 register", reg_hash);
2265}
2266\f
252b5132
RH		 2267#ifdef DEBUG386
2268
ce8a8b2f 2269/* Debugging routines for md_assemble. */
d3ce72d0 2270static void pte (insn_template *);
40fb9820 2271static void pt (i386_operand_type);
e3bb37b5
L		 2272static void pe (expressionS *);
2273static void ps (symbolS *);
252b5132
RH		 2274
2275static void
e3bb37b5 2276pi (char *line, i386_insn *x)
252b5132 2277{
09f131f2 2278 unsigned int i;
252b5132
RH		 2279
2280 fprintf (stdout, "%s: template ", line);
2281 pte (&x->tm);
09f131f2
JH		 2282 fprintf (stdout, " address: base %s index %s scale %x\n",
2283 x->base_reg ? x->base_reg->reg_name : "none",
2284 x->index_reg ? x->index_reg->reg_name : "none",
2285 x->log2_scale_factor);
2286 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2287 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2288 fprintf (stdout, " sib: base %x index %x scale %x\n",
2289 x->sib.base, x->sib.index, x->sib.scale);
2290 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2291 (x->rex & REX_W) != 0,
2292 (x->rex & REX_R) != 0,
2293 (x->rex & REX_X) != 0,
2294 (x->rex & REX_B) != 0);
252b5132
RH		 2295 for (i = 0; i < x->operands; i++)
2296 {
2297 fprintf (stdout, " #%d: ", i + 1);
2298 pt (x->types[i]);
2299 fprintf (stdout, "\n");
40fb9820
L		 2300 if (x->types[i].bitfield.reg8
2301 || x->types[i].bitfield.reg16
2302 || x->types[i].bitfield.reg32
2303 || x->types[i].bitfield.reg64
2304 || x->types[i].bitfield.regmmx
2305 || x->types[i].bitfield.regxmm
c0f3af97 2306 || x->types[i].bitfield.regymm
40fb9820
L		 2307 || x->types[i].bitfield.sreg2
2308 || x->types[i].bitfield.sreg3
2309 || x->types[i].bitfield.control
2310 || x->types[i].bitfield.debug
2311 || x->types[i].bitfield.test)
520dc8e8 2312 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2313 if (operand_type_check (x->types[i], imm))
520dc8e8 2314 pe (x->op[i].imms);
40fb9820 2315 if (operand_type_check (x->types[i], disp))
520dc8e8 2316 pe (x->op[i].disps);
252b5132
RH		 2317 }
2318}
2319
2320static void
d3ce72d0 2321pte (insn_template *t)
252b5132 2322{
09f131f2 2323 unsigned int i;
252b5132 2324 fprintf (stdout, " %d operands ", t->operands);
47926f60 2325 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2326 if (t->extension_opcode != None)
2327 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2328 if (t->opcode_modifier.d)
252b5132 2329 fprintf (stdout, "D");
40fb9820 2330 if (t->opcode_modifier.w)
252b5132
RH		 2331 fprintf (stdout, "W");
2332 fprintf (stdout, "\n");
2333 for (i = 0; i < t->operands; i++)
2334 {
2335 fprintf (stdout, " #%d type ", i + 1);
2336 pt (t->operand_types[i]);
2337 fprintf (stdout, "\n");
2338 }
2339}
2340
2341static void
e3bb37b5 2342pe (expressionS *e)
252b5132 2343{
24eab124 2344 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2345 fprintf (stdout, " add_number %ld (%lx)\n",
2346 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2347 if (e->X_add_symbol)
2348 {
2349 fprintf (stdout, " add_symbol ");
2350 ps (e->X_add_symbol);
2351 fprintf (stdout, "\n");
2352 }
2353 if (e->X_op_symbol)
2354 {
2355 fprintf (stdout, " op_symbol ");
2356 ps (e->X_op_symbol);
2357 fprintf (stdout, "\n");
2358 }
2359}
2360
2361static void
e3bb37b5 2362ps (symbolS *s)
252b5132
RH		 2363{
2364 fprintf (stdout, "%s type %s%s",
2365 S_GET_NAME (s),
2366 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2367 segment_name (S_GET_SEGMENT (s)));
2368}
2369
7b81dfbb 2370static struct type_name
252b5132 2371 {
40fb9820
L		 2372 i386_operand_type mask;
2373 const char *name;
252b5132 2374 }
7b81dfbb 2375const type_names[] =
252b5132 2376{
40fb9820
L		 2377 { OPERAND_TYPE_REG8, "r8" },
2378 { OPERAND_TYPE_REG16, "r16" },
2379 { OPERAND_TYPE_REG32, "r32" },
2380 { OPERAND_TYPE_REG64, "r64" },
2381 { OPERAND_TYPE_IMM8, "i8" },
2382 { OPERAND_TYPE_IMM8, "i8s" },
2383 { OPERAND_TYPE_IMM16, "i16" },
2384 { OPERAND_TYPE_IMM32, "i32" },
2385 { OPERAND_TYPE_IMM32S, "i32s" },
2386 { OPERAND_TYPE_IMM64, "i64" },
2387 { OPERAND_TYPE_IMM1, "i1" },
2388 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2389 { OPERAND_TYPE_DISP8, "d8" },
2390 { OPERAND_TYPE_DISP16, "d16" },
2391 { OPERAND_TYPE_DISP32, "d32" },
2392 { OPERAND_TYPE_DISP32S, "d32s" },
2393 { OPERAND_TYPE_DISP64, "d64" },
2394 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2395 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2396 { OPERAND_TYPE_CONTROL, "control reg" },
2397 { OPERAND_TYPE_TEST, "test reg" },
2398 { OPERAND_TYPE_DEBUG, "debug reg" },
2399 { OPERAND_TYPE_FLOATREG, "FReg" },
2400 { OPERAND_TYPE_FLOATACC, "FAcc" },
2401 { OPERAND_TYPE_SREG2, "SReg2" },
2402 { OPERAND_TYPE_SREG3, "SReg3" },
2403 { OPERAND_TYPE_ACC, "Acc" },
2404 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2405 { OPERAND_TYPE_REGMMX, "rMMX" },
2406 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2407 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2408 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2409};
2410
2411static void
40fb9820 2412pt (i386_operand_type t)
252b5132 2413{
40fb9820 2414 unsigned int j;
c6fb90c8 2415 i386_operand_type a;
252b5132 2416
40fb9820 2417 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2418 {
2419 a = operand_type_and (t, type_names[j].mask);
0349dc08 2420 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2421 fprintf (stdout, "%s, ", type_names[j].name);
2422 }
252b5132
RH		 2423 fflush (stdout);
2424}
2425
2426#endif /* DEBUG386 */
2427\f
252b5132 2428static bfd_reloc_code_real_type
3956db08 2429reloc (unsigned int size,
64e74474
AM		 2430 int pcrel,
2431 int sign,
2432 bfd_reloc_code_real_type other)
252b5132 2433{
47926f60 2434 if (other != NO_RELOC)
3956db08
JB		 2435 {
2436 reloc_howto_type *reloc;
2437
2438 if (size == 8)
2439 switch (other)
2440 {
64e74474
AM		 2441 case BFD_RELOC_X86_64_GOT32:
2442 return BFD_RELOC_X86_64_GOT64;
2443 break;
2444 case BFD_RELOC_X86_64_PLTOFF64:
2445 return BFD_RELOC_X86_64_PLTOFF64;
2446 break;
2447 case BFD_RELOC_X86_64_GOTPC32:
2448 other = BFD_RELOC_X86_64_GOTPC64;
2449 break;
2450 case BFD_RELOC_X86_64_GOTPCREL:
2451 other = BFD_RELOC_X86_64_GOTPCREL64;
2452 break;
2453 case BFD_RELOC_X86_64_TPOFF32:
2454 other = BFD_RELOC_X86_64_TPOFF64;
2455 break;
2456 case BFD_RELOC_X86_64_DTPOFF32:
2457 other = BFD_RELOC_X86_64_DTPOFF64;
2458 break;
2459 default:
2460 break;
3956db08 2461 }
e05278af
JB		 2462
2463 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2464 if (size == 4 && flag_code != CODE_64BIT)
2465 sign = -1;
2466
3956db08
JB		 2467 reloc = bfd_reloc_type_lookup (stdoutput, other);
2468 if (!reloc)
2469 as_bad (_("unknown relocation (%u)"), other);
2470 else if (size != bfd_get_reloc_size (reloc))
2471 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2472 bfd_get_reloc_size (reloc),
2473 size);
2474 else if (pcrel && !reloc->pc_relative)
2475 as_bad (_("non-pc-relative relocation for pc-relative field"));
2476 else if ((reloc->complain_on_overflow == complain_overflow_signed
2477 && !sign)
2478 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2479 && sign > 0))
3956db08
JB		 2480 as_bad (_("relocated field and relocation type differ in signedness"));
2481 else
2482 return other;
2483 return NO_RELOC;
2484 }
252b5132
RH		 2485
2486 if (pcrel)
2487 {
3e73aa7c 2488 if (!sign)
3956db08 2489 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2490 switch (size)
2491 {
2492 case 1: return BFD_RELOC_8_PCREL;
2493 case 2: return BFD_RELOC_16_PCREL;
2494 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2495 case 8: return BFD_RELOC_64_PCREL;
252b5132 2496 }
3956db08 2497 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2498 }
2499 else
2500 {
3956db08 2501 if (sign > 0)
e5cb08ac 2502 switch (size)
3e73aa7c
JH		 2503 {
2504 case 4: return BFD_RELOC_X86_64_32S;
2505 }
2506 else
2507 switch (size)
2508 {
2509 case 1: return BFD_RELOC_8;
2510 case 2: return BFD_RELOC_16;
2511 case 4: return BFD_RELOC_32;
2512 case 8: return BFD_RELOC_64;
2513 }
3956db08
JB		 2514 as_bad (_("cannot do %s %u byte relocation"),
2515 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2516 }
2517
0cc9e1d3 2518 return NO_RELOC;
252b5132
RH		 2519}
2520
47926f60
KH		 2521/* Here we decide which fixups can be adjusted to make them relative to
2522 the beginning of the section instead of the symbol. Basically we need
2523 to make sure that the dynamic relocations are done correctly, so in
2524 some cases we force the original symbol to be used. */
2525
252b5132 2526int
e3bb37b5 2527tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2528{
6d249963 2529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2530 if (!IS_ELF)
31312f95
AM		 2531 return 1;
2532
a161fe53
AM		 2533 /* Don't adjust pc-relative references to merge sections in 64-bit
2534 mode. */
2535 if (use_rela_relocations
2536 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2537 && fixP->fx_pcrel)
252b5132 2538 return 0;
31312f95 2539
8d01d9a9
AJ		 2540 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2541 and changed later by validate_fix. */
2542 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2543 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2544 return 0;
2545
ce8a8b2f 2546 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2547 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2548 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2549 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2550 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2551 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2552 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2553 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2554 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2555 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2556 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2557 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2558 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2559 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2560 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2561 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2562 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2563 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2564 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2565 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2566 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2567 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2568 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2569 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2570 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2571 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2572 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2573 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2574 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2575 return 0;
31312f95 2576#endif
252b5132
RH		 2577 return 1;
2578}
252b5132 2579
b4cac588 2580static int
e3bb37b5 2581intel_float_operand (const char *mnemonic)
252b5132 2582{
9306ca4a
JB		 2583 /* Note that the value returned is meaningful only for opcodes with (memory)
2584 operands, hence the code here is free to improperly handle opcodes that
2585 have no operands (for better performance and smaller code). */
2586
2587 if (mnemonic[0] != 'f')
2588 return 0; /* non-math */
2589
2590 switch (mnemonic[1])
2591 {
2592 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2593 the fs segment override prefix not currently handled because no
2594 call path can make opcodes without operands get here */
2595 case 'i':
2596 return 2 /* integer op */;
2597 case 'l':
2598 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2599 return 3; /* fldcw/fldenv */
2600 break;
2601 case 'n':
2602 if (mnemonic[2] != 'o' /* fnop */)
2603 return 3; /* non-waiting control op */
2604 break;
2605 case 'r':
2606 if (mnemonic[2] == 's')
2607 return 3; /* frstor/frstpm */
2608 break;
2609 case 's':
2610 if (mnemonic[2] == 'a')
2611 return 3; /* fsave */
2612 if (mnemonic[2] == 't')
2613 {
2614 switch (mnemonic[3])
2615 {
2616 case 'c': /* fstcw */
2617 case 'd': /* fstdw */
2618 case 'e': /* fstenv */
2619 case 's': /* fsts[gw] */
2620 return 3;
2621 }
2622 }
2623 break;
2624 case 'x':
2625 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2626 return 0; /* fxsave/fxrstor are not really math ops */
2627 break;
2628 }
252b5132 2629
9306ca4a 2630 return 1;
252b5132
RH		 2631}
2632
c0f3af97
L		 2633/* Build the VEX prefix. */
2634
2635static void
d3ce72d0 2636build_vex_prefix (const insn_template *t)
c0f3af97
L		 2637{
2638 unsigned int register_specifier;
2639 unsigned int implied_prefix;
2640 unsigned int vector_length;
2641
2642 /* Check register specifier. */
2643 if (i.vex.register_specifier)
2644 {
2645 register_specifier = i.vex.register_specifier->reg_num;
2646 if ((i.vex.register_specifier->reg_flags & RegRex))
2647 register_specifier += 8;
2648 register_specifier = ~register_specifier & 0xf;
2649 }
2650 else
2651 register_specifier = 0xf;
2652
fa99fab2
L		 2653 /* Use 2-byte VEX prefix by swappping destination and source
2654 operand. */
2655 if (!i.swap_operand
2656 && i.operands == i.reg_operands
2657 && i.tm.opcode_modifier.vex0f
2658 && i.tm.opcode_modifier.s
2659 && i.rex == REX_B)
2660 {
2661 unsigned int xchg = i.operands - 1;
2662 union i386_op temp_op;
2663 i386_operand_type temp_type;
2664
2665 temp_type = i.types[xchg];
2666 i.types[xchg] = i.types[0];
2667 i.types[0] = temp_type;
2668 temp_op = i.op[xchg];
2669 i.op[xchg] = i.op[0];
2670 i.op[0] = temp_op;
2671
9c2799c2 2672 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2673
2674 i.rex = REX_R;
2675 xchg = i.rm.regmem;
2676 i.rm.regmem = i.rm.reg;
2677 i.rm.reg = xchg;
2678
2679 /* Use the next insn. */
2680 i.tm = t[1];
2681 }
2682
2bf05e57 2683 vector_length = i.tm.opcode_modifier.vex == 2 ? 1 : 0;
c0f3af97
L		 2684
2685 switch ((i.tm.base_opcode >> 8) & 0xff)
2686 {
2687 case 0:
2688 implied_prefix = 0;
2689 break;
2690 case DATA_PREFIX_OPCODE:
2691 implied_prefix = 1;
2692 break;
2693 case REPE_PREFIX_OPCODE:
2694 implied_prefix = 2;
2695 break;
2696 case REPNE_PREFIX_OPCODE:
2697 implied_prefix = 3;
2698 break;
2699 default:
2700 abort ();
2701 }
2702
2703 /* Use 2-byte VEX prefix if possible. */
2704 if (i.tm.opcode_modifier.vex0f
2705 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2706 {
2707 /* 2-byte VEX prefix. */
2708 unsigned int r;
2709
2710 i.vex.length = 2;
2711 i.vex.bytes[0] = 0xc5;
2712
2713 /* Check the REX.R bit. */
2714 r = (i.rex & REX_R) ? 0 : 1;
2715 i.vex.bytes[1] = (r << 7
2716 | register_specifier << 3
2717 | vector_length << 2
2718 | implied_prefix);
2719 }
2720 else
2721 {
2722 /* 3-byte VEX prefix. */
2723 unsigned int m, w;
2724
f88c9eb0
SP		 2725 i.vex.length = 3;
2726 i.vex.bytes[0] = 0xc4;
2727
c0f3af97
L		 2728 if (i.tm.opcode_modifier.vex0f)
2729 m = 0x1;
2730 else if (i.tm.opcode_modifier.vex0f38)
2731 m = 0x2;
2732 else if (i.tm.opcode_modifier.vex0f3a)
2733 m = 0x3;
f88c9eb0
SP		 2734 else if (i.tm.opcode_modifier.xop09)
2735 {
2736 m = 0x9;
2737 i.vex.bytes[0] = 0x8f;
2738 }
2739 else if (i.tm.opcode_modifier.xop0a)
2740 {
2741 m = 0xa;
2742 i.vex.bytes[0] = 0x8f;
2743 }
c0f3af97
L		 2744 else
2745 abort ();
2746
c0f3af97
L		 2747 /* The high 3 bits of the second VEX byte are 1's compliment
2748 of RXB bits from REX. */
2749 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2750
2751 /* Check the REX.W bit. */
2752 w = (i.rex & REX_W) ? 1 : 0;
2753 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2754 {
2755 if (w)
2756 abort ();
2757
2758 if (i.tm.opcode_modifier.vexw1)
2759 w = 1;
2760 }
2761
2762 i.vex.bytes[2] = (w << 7
2763 | register_specifier << 3
2764 | vector_length << 2
2765 | implied_prefix);
2766 }
2767}
2768
65da13b5
L		 2769static void
2770process_immext (void)
2771{
2772 expressionS *exp;
2773
2774 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2775 {
1fed0ba1
L		 2776 /* SSE3 Instructions have the fixed operands with an opcode
2777 suffix which is coded in the same place as an 8-bit immediate
2778 field would be. Here we check those operands and remove them
2779 afterwards. */
65da13b5
L		 2780 unsigned int x;
2781
2782 for (x = 0; x < i.operands; x++)
2783 if (i.op[x].regs->reg_num != x)
2784 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2785 register_prefix, i.op[x].regs->reg_name, x + 1,
2786 i.tm.name);
2787
2788 i.operands = 0;
65da13b5
L		 2789 }
2790
c0f3af97 2791 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2792 which is coded in the same place as an 8-bit immediate field
2793 would be. Here we fake an 8-bit immediate operand from the
2794 opcode suffix stored in tm.extension_opcode.
2795
c1e679ec 2796 AVX instructions also use this encoding, for some of
c0f3af97 2797 3 argument instructions. */
65da13b5 2798
9c2799c2 2799 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2800 && (i.operands <= 2
2801 || (i.tm.opcode_modifier.vex
2802 && i.operands <= 4)));
65da13b5
L		 2803
2804 exp = &im_expressions[i.imm_operands++];
2805 i.op[i.operands].imms = exp;
2806 i.types[i.operands] = imm8;
2807 i.operands++;
2808 exp->X_op = O_constant;
2809 exp->X_add_number = i.tm.extension_opcode;
2810 i.tm.extension_opcode = None;
2811}
2812
252b5132
RH		 2813/* This is the guts of the machine-dependent assembler. LINE points to a
2814 machine dependent instruction. This function is supposed to emit
2815 the frags/bytes it assembles to. */
2816
2817void
65da13b5 2818md_assemble (char *line)
252b5132 2819{
40fb9820 2820 unsigned int j;
252b5132 2821 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2822 const insn_template *t;
252b5132 2823
47926f60 2824 /* Initialize globals. */
252b5132
RH		 2825 memset (&i, '\0', sizeof (i));
2826 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2827 i.reloc[j] = NO_RELOC;
252b5132
RH		 2828 memset (disp_expressions, '\0', sizeof (disp_expressions));
2829 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2830 save_stack_p = save_stack;
252b5132
RH		 2831
2832 /* First parse an instruction mnemonic & call i386_operand for the operands.
2833 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2834 start of a (possibly prefixed) mnemonic. */
252b5132 2835
29b0f896
AM		 2836 line = parse_insn (line, mnemonic);
2837 if (line == NULL)
2838 return;
252b5132 2839
29b0f896 2840 line = parse_operands (line, mnemonic);
ee86248c 2841 this_operand = -1;
29b0f896
AM		 2842 if (line == NULL)
2843 return;
252b5132 2844
29b0f896
AM		 2845 /* Now we've parsed the mnemonic into a set of templates, and have the
2846 operands at hand. */
2847
2848 /* All intel opcodes have reversed operands except for "bound" and
2849 "enter". We also don't reverse intersegment "jmp" and "call"
2850 instructions with 2 immediate operands so that the immediate segment
050dfa73 2851 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2852 if (intel_syntax
2853 && i.operands > 1
29b0f896 2854 && (strcmp (mnemonic, "bound") != 0)
30123838 2855 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2856 && !(operand_type_check (i.types[0], imm)
2857 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2858 swap_operands ();
2859
ec56d5c0
JB		 2860 /* The order of the immediates should be reversed
2861 for 2 immediates extrq and insertq instructions */
2862 if (i.imm_operands == 2
2863 && (strcmp (mnemonic, "extrq") == 0
2864 || strcmp (mnemonic, "insertq") == 0))
2865 swap_2_operands (0, 1);
2866
29b0f896
AM		 2867 if (i.imm_operands)
2868 optimize_imm ();
2869
b300c311
L		 2870 /* Don't optimize displacement for movabs since it only takes 64bit
2871 displacement. */
2872 if (i.disp_operands
2873 && (flag_code != CODE_64BIT
2874 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2875 optimize_disp ();
2876
2877 /* Next, we find a template that matches the given insn,
2878 making sure the overlap of the given operands types is consistent
2879 with the template operand types. */
252b5132 2880
fa99fab2 2881 if (!(t = match_template ()))
29b0f896 2882 return;
252b5132 2883
daf50ae7 2884 if (sse_check != sse_check_none
81f8a913 2885 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2886 && (i.tm.cpu_flags.bitfield.cpusse
2887 || i.tm.cpu_flags.bitfield.cpusse2
2888 || i.tm.cpu_flags.bitfield.cpusse3
2889 || i.tm.cpu_flags.bitfield.cpussse3
2890 || i.tm.cpu_flags.bitfield.cpusse4_1
2891 || i.tm.cpu_flags.bitfield.cpusse4_2))
2892 {
2893 (sse_check == sse_check_warning
2894 ? as_warn
2895 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2896 }
2897
321fd21e
L		 2898 /* Zap movzx and movsx suffix. The suffix has been set from
2899 "word ptr" or "byte ptr" on the source operand in Intel syntax
2900 or extracted from mnemonic in AT&T syntax. But we'll use
2901 the destination register to choose the suffix for encoding. */
2902 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2903 {
321fd21e
L		 2904 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2905 there is no suffix, the default will be byte extension. */
2906 if (i.reg_operands != 2
2907 && !i.suffix
7ab9ffdd 2908 && intel_syntax)
321fd21e
L		 2909 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2910
2911 i.suffix = 0;
cd61ebfe 2912 }
24eab124 2913
40fb9820 2914 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2915 if (!add_prefix (FWAIT_OPCODE))
2916 return;
252b5132 2917
29b0f896 2918 /* Check string instruction segment overrides. */
40fb9820 2919 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2920 {
2921 if (!check_string ())
5dd0794d 2922 return;
fc0763e6 2923 i.disp_operands = 0;
29b0f896 2924 }
5dd0794d 2925
29b0f896
AM		 2926 if (!process_suffix ())
2927 return;
e413e4e9 2928
bc0844ae
L		 2929 /* Update operand types. */
2930 for (j = 0; j < i.operands; j++)
2931 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2932
29b0f896
AM		 2933 /* Make still unresolved immediate matches conform to size of immediate
2934 given in i.suffix. */
2935 if (!finalize_imm ())
2936 return;
252b5132 2937
40fb9820 2938 if (i.types[0].bitfield.imm1)
29b0f896 2939 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2940
9afe6eb8
L		 2941 /* We only need to check those implicit registers for instructions
2942 with 3 operands or less. */
2943 if (i.operands <= 3)
2944 for (j = 0; j < i.operands; j++)
2945 if (i.types[j].bitfield.inoutportreg
2946 || i.types[j].bitfield.shiftcount
2947 || i.types[j].bitfield.acc
2948 || i.types[j].bitfield.floatacc)
2949 i.reg_operands--;
40fb9820 2950
c0f3af97
L		 2951 /* ImmExt should be processed after SSE2AVX. */
2952 if (!i.tm.opcode_modifier.sse2avx
2953 && i.tm.opcode_modifier.immext)
65da13b5 2954 process_immext ();
252b5132 2955
29b0f896
AM		 2956 /* For insns with operands there are more diddles to do to the opcode. */
2957 if (i.operands)
2958 {
2959 if (!process_operands ())
2960 return;
2961 }
40fb9820 2962 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2963 {
2964 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2965 as_warn (_("translating to `%sp'"), i.tm.name);
2966 }
252b5132 2967
c0f3af97 2968 if (i.tm.opcode_modifier.vex)
fa99fab2 2969 build_vex_prefix (t);
c0f3af97 2970
29b0f896
AM		 2971 /* Handle conversion of 'int $3' --> special int3 insn. */
2972 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2973 {
2974 i.tm.base_opcode = INT3_OPCODE;
2975 i.imm_operands = 0;
2976 }
252b5132 2977
40fb9820
L		 2978 if ((i.tm.opcode_modifier.jump
2979 || i.tm.opcode_modifier.jumpbyte
2980 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2981 && i.op[0].disps->X_op == O_constant)
2982 {
2983 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2984 the absolute address given by the constant. Since ix86 jumps and
2985 calls are pc relative, we need to generate a reloc. */
2986 i.op[0].disps->X_add_symbol = &abs_symbol;
2987 i.op[0].disps->X_op = O_symbol;
2988 }
252b5132 2989
40fb9820 2990 if (i.tm.opcode_modifier.rex64)
161a04f6 2991 i.rex |= REX_W;
252b5132 2992
29b0f896
AM		 2993 /* For 8 bit registers we need an empty rex prefix. Also if the
2994 instruction already has a prefix, we need to convert old
2995 registers to new ones. */
773f551c 2996
40fb9820 2997 if ((i.types[0].bitfield.reg8
29b0f896 2998 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2999 || (i.types[1].bitfield.reg8
29b0f896 3000 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3001 || ((i.types[0].bitfield.reg8
3002 || i.types[1].bitfield.reg8)
29b0f896
AM		 3003 && i.rex != 0))
3004 {
3005 int x;
726c5dcd 3006
29b0f896
AM		 3007 i.rex |= REX_OPCODE;
3008 for (x = 0; x < 2; x++)
3009 {
3010 /* Look for 8 bit operand that uses old registers. */
40fb9820 3011 if (i.types[x].bitfield.reg8
29b0f896 3012 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3013 {
29b0f896
AM		 3014 /* In case it is "hi" register, give up. */
3015 if (i.op[x].regs->reg_num > 3)
a540244d 3016 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3017 "instruction requiring REX prefix."),
a540244d 3018 register_prefix, i.op[x].regs->reg_name);
773f551c 3019
29b0f896
AM		 3020 /* Otherwise it is equivalent to the extended register.
3021 Since the encoding doesn't change this is merely
3022 cosmetic cleanup for debug output. */
3023
3024 i.op[x].regs = i.op[x].regs + 8;
773f551c 3025 }
29b0f896
AM		 3026 }
3027 }
773f551c 3028
7ab9ffdd 3029 if (i.rex != 0)
29b0f896
AM		 3030 add_prefix (REX_OPCODE | i.rex);
3031
3032 /* We are ready to output the insn. */
3033 output_insn ();
3034}
3035
3036static char *
e3bb37b5 3037parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3038{
3039 char *l = line;
3040 char *token_start = l;
3041 char *mnem_p;
5c6af06e 3042 int supported;
d3ce72d0 3043 const insn_template *t;
b6169b20 3044 char *dot_p = NULL;
29b0f896
AM		 3045
3046 /* Non-zero if we found a prefix only acceptable with string insns. */
3047 const char *expecting_string_instruction = NULL;
45288df1 3048
29b0f896
AM		 3049 while (1)
3050 {
3051 mnem_p = mnemonic;
3052 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3053 {
b6169b20
L		 3054 if (*mnem_p == '.')
3055 dot_p = mnem_p;
29b0f896
AM		 3056 mnem_p++;
3057 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3058 {
29b0f896
AM		 3059 as_bad (_("no such instruction: `%s'"), token_start);
3060 return NULL;
3061 }
3062 l++;
3063 }
3064 if (!is_space_char (*l)
3065 && *l != END_OF_INSN
e44823cf
JB		 3066 && (intel_syntax
3067 || (*l != PREFIX_SEPARATOR
3068 && *l != ',')))
29b0f896
AM		 3069 {
3070 as_bad (_("invalid character %s in mnemonic"),
3071 output_invalid (*l));
3072 return NULL;
3073 }
3074 if (token_start == l)
3075 {
e44823cf 3076 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3077 as_bad (_("expecting prefix; got nothing"));
3078 else
3079 as_bad (_("expecting mnemonic; got nothing"));
3080 return NULL;
3081 }
45288df1 3082
29b0f896 3083 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3084 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3085
29b0f896
AM		 3086 if (*l != END_OF_INSN
3087 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3088 && current_templates
40fb9820 3089 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3090 {
c6fb90c8 3091 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3092 {
3093 as_bad ((flag_code != CODE_64BIT
3094 ? _("`%s' is only supported in 64-bit mode")
3095 : _("`%s' is not supported in 64-bit mode")),
3096 current_templates->start->name);
3097 return NULL;
3098 }
29b0f896
AM		 3099 /* If we are in 16-bit mode, do not allow addr16 or data16.
3100 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3101 if ((current_templates->start->opcode_modifier.size16
3102 || current_templates->start->opcode_modifier.size32)
29b0f896 3103 && flag_code != CODE_64BIT
40fb9820 3104 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3105 ^ (flag_code == CODE_16BIT)))
3106 {
3107 as_bad (_("redundant %s prefix"),
3108 current_templates->start->name);
3109 return NULL;
45288df1 3110 }
29b0f896
AM		 3111 /* Add prefix, checking for repeated prefixes. */
3112 switch (add_prefix (current_templates->start->base_opcode))
3113 {
3114 case 0:
3115 return NULL;
3116 case 2:
3117 expecting_string_instruction = current_templates->start->name;
3118 break;
3119 }
3120 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3121 token_start = ++l;
3122 }
3123 else
3124 break;
3125 }
45288df1 3126
30a55f88 3127 if (!current_templates)
b6169b20 3128 {
30a55f88
L		 3129 /* Check if we should swap operand in encoding. */
3130 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3131 i.swap_operand = 1;
3132 else
3133 goto check_suffix;
3134 mnem_p = dot_p;
3135 *dot_p = '\0';
d3ce72d0 3136 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3137 }
3138
29b0f896
AM		 3139 if (!current_templates)
3140 {
b6169b20 3141check_suffix:
29b0f896
AM		 3142 /* See if we can get a match by trimming off a suffix. */
3143 switch (mnem_p[-1])
3144 {
3145 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3146 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3147 i.suffix = SHORT_MNEM_SUFFIX;
3148 else
29b0f896
AM		 3149 case BYTE_MNEM_SUFFIX:
3150 case QWORD_MNEM_SUFFIX:
3151 i.suffix = mnem_p[-1];
3152 mnem_p[-1] = '\0';
d3ce72d0
NC		 3153 current_templates = (const templates *) hash_find (op_hash,
3154 mnemonic);
29b0f896
AM		 3155 break;
3156 case SHORT_MNEM_SUFFIX:
3157 case LONG_MNEM_SUFFIX:
3158 if (!intel_syntax)
3159 {
3160 i.suffix = mnem_p[-1];
3161 mnem_p[-1] = '\0';
d3ce72d0
NC		 3162 current_templates = (const templates *) hash_find (op_hash,
3163 mnemonic);
29b0f896
AM		 3164 }
3165 break;
252b5132 3166
29b0f896
AM		 3167 /* Intel Syntax. */
3168 case 'd':
3169 if (intel_syntax)
3170 {
9306ca4a 3171 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3172 i.suffix = SHORT_MNEM_SUFFIX;
3173 else
3174 i.suffix = LONG_MNEM_SUFFIX;
3175 mnem_p[-1] = '\0';
d3ce72d0
NC		 3176 current_templates = (const templates *) hash_find (op_hash,
3177 mnemonic);
29b0f896
AM		 3178 }
3179 break;
3180 }
3181 if (!current_templates)
3182 {
3183 as_bad (_("no such instruction: `%s'"), token_start);
3184 return NULL;
3185 }
3186 }
252b5132 3187
40fb9820
L		 3188 if (current_templates->start->opcode_modifier.jump
3189 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3190 {
3191 /* Check for a branch hint. We allow ",pt" and ",pn" for
3192 predict taken and predict not taken respectively.
3193 I'm not sure that branch hints actually do anything on loop
3194 and jcxz insns (JumpByte) for current Pentium4 chips. They
3195 may work in the future and it doesn't hurt to accept them
3196 now. */
3197 if (l[0] == ',' && l[1] == 'p')
3198 {
3199 if (l[2] == 't')
3200 {
3201 if (!add_prefix (DS_PREFIX_OPCODE))
3202 return NULL;
3203 l += 3;
3204 }
3205 else if (l[2] == 'n')
3206 {
3207 if (!add_prefix (CS_PREFIX_OPCODE))
3208 return NULL;
3209 l += 3;
3210 }
3211 }
3212 }
3213 /* Any other comma loses. */
3214 if (*l == ',')
3215 {
3216 as_bad (_("invalid character %s in mnemonic"),
3217 output_invalid (*l));
3218 return NULL;
3219 }
252b5132 3220
29b0f896 3221 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3222 supported = 0;
3223 for (t = current_templates->start; t < current_templates->end; ++t)
3224 {
c0f3af97
L		 3225 supported |= cpu_flags_match (t);
3226 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3227 goto skip;
5c6af06e 3228 }
3629bb00 3229
c0f3af97 3230 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3231 {
3232 as_bad (flag_code == CODE_64BIT
3233 ? _("`%s' is not supported in 64-bit mode")
3234 : _("`%s' is only supported in 64-bit mode"),
3235 current_templates->start->name);
3236 return NULL;
3237 }
c0f3af97 3238 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3239 {
3629bb00 3240 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3241 current_templates->start->name,
41aacd83 3242 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3243 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3244 return NULL;
29b0f896 3245 }
3629bb00
L		 3246
3247skip:
3248 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3249 && (flag_code != CODE_16BIT))
29b0f896
AM		 3250 {
3251 as_warn (_("use .code16 to ensure correct addressing mode"));
3252 }
252b5132 3253
29b0f896 3254 /* Check for rep/repne without a string instruction. */
f41bbced 3255 if (expecting_string_instruction)
29b0f896 3256 {
f41bbced
JB		 3257 static templates override;
3258
3259 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3260 if (t->opcode_modifier.isstring)
f41bbced
JB		 3261 break;
3262 if (t >= current_templates->end)
3263 {
3264 as_bad (_("expecting string instruction after `%s'"),
64e74474 3265 expecting_string_instruction);
f41bbced
JB		 3266 return NULL;
3267 }
3268 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3269 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3270 break;
3271 override.end = t;
3272 current_templates = &override;
29b0f896 3273 }
252b5132 3274
29b0f896
AM		 3275 return l;
3276}
252b5132 3277
29b0f896 3278static char *
e3bb37b5 3279parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3280{
3281 char *token_start;
3138f287 3282
29b0f896
AM		 3283 /* 1 if operand is pending after ','. */
3284 unsigned int expecting_operand = 0;
252b5132 3285
29b0f896
AM		 3286 /* Non-zero if operand parens not balanced. */
3287 unsigned int paren_not_balanced;
3288
3289 while (*l != END_OF_INSN)
3290 {
3291 /* Skip optional white space before operand. */
3292 if (is_space_char (*l))
3293 ++l;
3294 if (!is_operand_char (*l) && *l != END_OF_INSN)
3295 {
3296 as_bad (_("invalid character %s before operand %d"),
3297 output_invalid (*l),
3298 i.operands + 1);
3299 return NULL;
3300 }
3301 token_start = l; /* after white space */
3302 paren_not_balanced = 0;
3303 while (paren_not_balanced || *l != ',')
3304 {
3305 if (*l == END_OF_INSN)
3306 {
3307 if (paren_not_balanced)
3308 {
3309 if (!intel_syntax)
3310 as_bad (_("unbalanced parenthesis in operand %d."),
3311 i.operands + 1);
3312 else
3313 as_bad (_("unbalanced brackets in operand %d."),
3314 i.operands + 1);
3315 return NULL;
3316 }
3317 else
3318 break; /* we are done */
3319 }
3320 else if (!is_operand_char (*l) && !is_space_char (*l))
3321 {
3322 as_bad (_("invalid character %s in operand %d"),
3323 output_invalid (*l),
3324 i.operands + 1);
3325 return NULL;
3326 }
3327 if (!intel_syntax)
3328 {
3329 if (*l == '(')
3330 ++paren_not_balanced;
3331 if (*l == ')')
3332 --paren_not_balanced;
3333 }
3334 else
3335 {
3336 if (*l == '[')
3337 ++paren_not_balanced;
3338 if (*l == ']')
3339 --paren_not_balanced;
3340 }
3341 l++;
3342 }
3343 if (l != token_start)
3344 { /* Yes, we've read in another operand. */
3345 unsigned int operand_ok;
3346 this_operand = i.operands++;
7d5e4556 3347 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3348 if (i.operands > MAX_OPERANDS)
3349 {
3350 as_bad (_("spurious operands; (%d operands/instruction max)"),
3351 MAX_OPERANDS);
3352 return NULL;
3353 }
3354 /* Now parse operand adding info to 'i' as we go along. */
3355 END_STRING_AND_SAVE (l);
3356
3357 if (intel_syntax)
3358 operand_ok =
3359 i386_intel_operand (token_start,
3360 intel_float_operand (mnemonic));
3361 else
a7619375 3362 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3363
3364 RESTORE_END_STRING (l);
3365 if (!operand_ok)
3366 return NULL;
3367 }
3368 else
3369 {
3370 if (expecting_operand)
3371 {
3372 expecting_operand_after_comma:
3373 as_bad (_("expecting operand after ','; got nothing"));
3374 return NULL;
3375 }
3376 if (*l == ',')
3377 {
3378 as_bad (_("expecting operand before ','; got nothing"));
3379 return NULL;
3380 }
3381 }
7f3f1ea2 3382
29b0f896
AM		 3383 /* Now *l must be either ',' or END_OF_INSN. */
3384 if (*l == ',')
3385 {
3386 if (*++l == END_OF_INSN)
3387 {
3388 /* Just skip it, if it's \n complain. */
3389 goto expecting_operand_after_comma;
3390 }
3391 expecting_operand = 1;
3392 }
3393 }
3394 return l;
3395}
7f3f1ea2 3396
050dfa73 3397static void
4d456e3d 3398swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3399{
3400 union i386_op temp_op;
40fb9820 3401 i386_operand_type temp_type;
050dfa73 3402 enum bfd_reloc_code_real temp_reloc;
4eed87de 3403
050dfa73
MM		 3404 temp_type = i.types[xchg2];
3405 i.types[xchg2] = i.types[xchg1];
3406 i.types[xchg1] = temp_type;
3407 temp_op = i.op[xchg2];
3408 i.op[xchg2] = i.op[xchg1];
3409 i.op[xchg1] = temp_op;
3410 temp_reloc = i.reloc[xchg2];
3411 i.reloc[xchg2] = i.reloc[xchg1];
3412 i.reloc[xchg1] = temp_reloc;
3413}
3414
29b0f896 3415static void
e3bb37b5 3416swap_operands (void)
29b0f896 3417{
b7c61d9a 3418 switch (i.operands)
050dfa73 3419 {
c0f3af97 3420 case 5:
b7c61d9a 3421 case 4:
4d456e3d 3422 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3423 case 3:
3424 case 2:
4d456e3d 3425 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3426 break;
3427 default:
3428 abort ();
29b0f896 3429 }
29b0f896
AM		 3430
3431 if (i.mem_operands == 2)
3432 {
3433 const seg_entry *temp_seg;
3434 temp_seg = i.seg[0];
3435 i.seg[0] = i.seg[1];
3436 i.seg[1] = temp_seg;
3437 }
3438}
252b5132 3439
29b0f896
AM		 3440/* Try to ensure constant immediates are represented in the smallest
3441 opcode possible. */
3442static void
e3bb37b5 3443optimize_imm (void)
29b0f896
AM		 3444{
3445 char guess_suffix = 0;
3446 int op;
252b5132 3447
29b0f896
AM		 3448 if (i.suffix)
3449 guess_suffix = i.suffix;
3450 else if (i.reg_operands)
3451 {
3452 /* Figure out a suffix from the last register operand specified.
3453 We can't do this properly yet, ie. excluding InOutPortReg,
3454 but the following works for instructions with immediates.
3455 In any case, we can't set i.suffix yet. */
3456 for (op = i.operands; --op >= 0;)
40fb9820 3457 if (i.types[op].bitfield.reg8)
7ab9ffdd 3458 {
40fb9820
L		 3459 guess_suffix = BYTE_MNEM_SUFFIX;
3460 break;
3461 }
3462 else if (i.types[op].bitfield.reg16)
252b5132 3463 {
40fb9820
L		 3464 guess_suffix = WORD_MNEM_SUFFIX;
3465 break;
3466 }
3467 else if (i.types[op].bitfield.reg32)
3468 {
3469 guess_suffix = LONG_MNEM_SUFFIX;
3470 break;
3471 }
3472 else if (i.types[op].bitfield.reg64)
3473 {
3474 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3475 break;
252b5132 3476 }
29b0f896
AM		 3477 }
3478 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3479 guess_suffix = WORD_MNEM_SUFFIX;
3480
3481 for (op = i.operands; --op >= 0;)
40fb9820 3482 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3483 {
3484 switch (i.op[op].imms->X_op)
252b5132 3485 {
29b0f896
AM		 3486 case O_constant:
3487 /* If a suffix is given, this operand may be shortened. */
3488 switch (guess_suffix)
252b5132 3489 {
29b0f896 3490 case LONG_MNEM_SUFFIX:
40fb9820
L		 3491 i.types[op].bitfield.imm32 = 1;
3492 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3493 break;
3494 case WORD_MNEM_SUFFIX:
40fb9820
L		 3495 i.types[op].bitfield.imm16 = 1;
3496 i.types[op].bitfield.imm32 = 1;
3497 i.types[op].bitfield.imm32s = 1;
3498 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3499 break;
3500 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3501 i.types[op].bitfield.imm8 = 1;
3502 i.types[op].bitfield.imm8s = 1;
3503 i.types[op].bitfield.imm16 = 1;
3504 i.types[op].bitfield.imm32 = 1;
3505 i.types[op].bitfield.imm32s = 1;
3506 i.types[op].bitfield.imm64 = 1;
29b0f896 3507 break;
252b5132 3508 }
252b5132 3509
29b0f896
AM		 3510 /* If this operand is at most 16 bits, convert it
3511 to a signed 16 bit number before trying to see
3512 whether it will fit in an even smaller size.
3513 This allows a 16-bit operand such as $0xffe0 to
3514 be recognised as within Imm8S range. */
40fb9820 3515 if ((i.types[op].bitfield.imm16)
29b0f896 3516 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3517 {
29b0f896
AM		 3518 i.op[op].imms->X_add_number =
3519 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3520 }
40fb9820 3521 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3522 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3523 == 0))
3524 {
3525 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3526 ^ ((offsetT) 1 << 31))
3527 - ((offsetT) 1 << 31));
3528 }
40fb9820 3529 i.types[op]
c6fb90c8
L		 3530 = operand_type_or (i.types[op],
3531 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3532
29b0f896
AM		 3533 /* We must avoid matching of Imm32 templates when 64bit
3534 only immediate is available. */
3535 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3536 i.types[op].bitfield.imm32 = 0;
29b0f896 3537 break;
252b5132 3538
29b0f896
AM		 3539 case O_absent:
3540 case O_register:
3541 abort ();
3542
3543 /* Symbols and expressions. */
3544 default:
9cd96992
JB		 3545 /* Convert symbolic operand to proper sizes for matching, but don't
3546 prevent matching a set of insns that only supports sizes other
3547 than those matching the insn suffix. */
3548 {
40fb9820 3549 i386_operand_type mask, allowed;
d3ce72d0 3550 const insn_template *t;
9cd96992 3551
0dfbf9d7
L		 3552 operand_type_set (&mask, 0);
3553 operand_type_set (&allowed, 0);
40fb9820 3554
4eed87de
AM		 3555 for (t = current_templates->start;
3556 t < current_templates->end;
3557 ++t)
c6fb90c8
L		 3558 allowed = operand_type_or (allowed,
3559 t->operand_types[op]);
9cd96992
JB		 3560 switch (guess_suffix)
3561 {
3562 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3563 mask.bitfield.imm64 = 1;
3564 mask.bitfield.imm32s = 1;
9cd96992
JB		 3565 break;
3566 case LONG_MNEM_SUFFIX:
40fb9820 3567 mask.bitfield.imm32 = 1;
9cd96992
JB		 3568 break;
3569 case WORD_MNEM_SUFFIX:
40fb9820 3570 mask.bitfield.imm16 = 1;
9cd96992
JB		 3571 break;
3572 case BYTE_MNEM_SUFFIX:
40fb9820 3573 mask.bitfield.imm8 = 1;
9cd96992
JB		 3574 break;
3575 default:
9cd96992
JB		 3576 break;
3577 }
c6fb90c8 3578 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3579 if (!operand_type_all_zero (&allowed))
c6fb90c8 3580 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3581 }
29b0f896 3582 break;
252b5132 3583 }
29b0f896
AM		 3584 }
3585}
47926f60 3586
29b0f896
AM		 3587/* Try to use the smallest displacement type too. */
3588static void
e3bb37b5 3589optimize_disp (void)
29b0f896
AM		 3590{
3591 int op;
3e73aa7c 3592
29b0f896 3593 for (op = i.operands; --op >= 0;)
40fb9820 3594 if (operand_type_check (i.types[op], disp))
252b5132 3595 {
b300c311 3596 if (i.op[op].disps->X_op == O_constant)
252b5132 3597 {
b300c311 3598 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3599
40fb9820 3600 if (i.types[op].bitfield.disp16
b300c311
L		 3601 && (disp & ~(offsetT) 0xffff) == 0)
3602 {
3603 /* If this operand is at most 16 bits, convert
3604 to a signed 16 bit number and don't use 64bit
3605 displacement. */
3606 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3607 i.types[op].bitfield.disp64 = 0;
b300c311 3608 }
40fb9820 3609 if (i.types[op].bitfield.disp32
b300c311
L		 3610 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3611 {
3612 /* If this operand is at most 32 bits, convert
3613 to a signed 32 bit number and don't use 64bit
3614 displacement. */
3615 disp &= (((offsetT) 2 << 31) - 1);
3616 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3617 i.types[op].bitfield.disp64 = 0;
b300c311 3618 }
40fb9820 3619 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3620 {
40fb9820
L		 3621 i.types[op].bitfield.disp8 = 0;
3622 i.types[op].bitfield.disp16 = 0;
3623 i.types[op].bitfield.disp32 = 0;
3624 i.types[op].bitfield.disp32s = 0;
3625 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3626 i.op[op].disps = 0;
3627 i.disp_operands--;
3628 }
3629 else if (flag_code == CODE_64BIT)
3630 {
3631 if (fits_in_signed_long (disp))
28a9d8f5 3632 {
40fb9820
L		 3633 i.types[op].bitfield.disp64 = 0;
3634 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3635 }
0e1147d9
L		 3636 if (i.prefix[ADDR_PREFIX]
3637 && fits_in_unsigned_long (disp))
40fb9820 3638 i.types[op].bitfield.disp32 = 1;
b300c311 3639 }
40fb9820
L		 3640 if ((i.types[op].bitfield.disp32
3641 || i.types[op].bitfield.disp32s
3642 || i.types[op].bitfield.disp16)
b300c311 3643 && fits_in_signed_byte (disp))
40fb9820 3644 i.types[op].bitfield.disp8 = 1;
252b5132 3645 }
67a4f2b7
AO		 3646 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3647 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3648 {
3649 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3650 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3651 i.types[op].bitfield.disp8 = 0;
3652 i.types[op].bitfield.disp16 = 0;
3653 i.types[op].bitfield.disp32 = 0;
3654 i.types[op].bitfield.disp32s = 0;
3655 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3656 }
3657 else
b300c311 3658 /* We only support 64bit displacement on constants. */
40fb9820 3659 i.types[op].bitfield.disp64 = 0;
252b5132 3660 }
29b0f896
AM		 3661}
3662
d3ce72d0 3663static const insn_template *
e3bb37b5 3664match_template (void)
29b0f896
AM		 3665{
3666 /* Points to template once we've found it. */
d3ce72d0 3667 const insn_template *t;
40fb9820 3668 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3669 i386_operand_type overlap4;
29b0f896 3670 unsigned int found_reverse_match;
40fb9820
L		 3671 i386_opcode_modifier suffix_check;
3672 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3673 int addr_prefix_disp;
a5c311ca 3674 unsigned int j;
3629bb00 3675 unsigned int found_cpu_match;
45664ddb 3676 unsigned int check_register;
29b0f896 3677
c0f3af97
L		 3678#if MAX_OPERANDS != 5
3679# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3680#endif
3681
29b0f896 3682 found_reverse_match = 0;
539e75ad 3683 addr_prefix_disp = -1;
40fb9820
L		 3684
3685 memset (&suffix_check, 0, sizeof (suffix_check));
3686 if (i.suffix == BYTE_MNEM_SUFFIX)
3687 suffix_check.no_bsuf = 1;
3688 else if (i.suffix == WORD_MNEM_SUFFIX)
3689 suffix_check.no_wsuf = 1;
3690 else if (i.suffix == SHORT_MNEM_SUFFIX)
3691 suffix_check.no_ssuf = 1;
3692 else if (i.suffix == LONG_MNEM_SUFFIX)
3693 suffix_check.no_lsuf = 1;
3694 else if (i.suffix == QWORD_MNEM_SUFFIX)
3695 suffix_check.no_qsuf = 1;
3696 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3697 suffix_check.no_ldsuf = 1;
29b0f896 3698
45aa61fe 3699 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3700 {
539e75ad
L		 3701 addr_prefix_disp = -1;
3702
29b0f896
AM		 3703 /* Must have right number of operands. */
3704 if (i.operands != t->operands)
3705 continue;
3706
50aecf8c 3707 /* Check processor support. */
c0f3af97
L		 3708 found_cpu_match = (cpu_flags_match (t)
3709 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3710 if (!found_cpu_match)
3711 continue;
3712
e1d4d893
L		 3713 /* Check old gcc support. */
3714 if (!old_gcc && t->opcode_modifier.oldgcc)
3715 continue;
3716
3717 /* Check AT&T mnemonic. */
3718 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3719 continue;
3720
5c07affc
L		 3721 /* Check AT&T syntax Intel syntax. */
3722 if ((intel_syntax && t->opcode_modifier.attsyntax)
3723 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3724 continue;
3725
20592a94 3726 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3727 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3728 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3729 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3730 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3731 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3732 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3733 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3734 continue;
3735
5c07affc 3736 if (!operand_size_match (t))
7d5e4556 3737 continue;
539e75ad 3738
5c07affc
L		 3739 for (j = 0; j < MAX_OPERANDS; j++)
3740 operand_types[j] = t->operand_types[j];
3741
45aa61fe
AM		 3742 /* In general, don't allow 64-bit operands in 32-bit mode. */
3743 if (i.suffix == QWORD_MNEM_SUFFIX
3744 && flag_code != CODE_64BIT
3745 && (intel_syntax
40fb9820 3746 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3747 && !intel_float_operand (t->name))
3748 : intel_float_operand (t->name) != 2)
40fb9820 3749 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3750 && !operand_types[0].bitfield.regxmm
3751 && !operand_types[0].bitfield.regymm)
40fb9820 3752 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3753 && !!operand_types[t->operands > 1].bitfield.regxmm
3754 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3755 && (t->base_opcode != 0x0fc7
3756 || t->extension_opcode != 1 /* cmpxchg8b */))
3757 continue;
3758
192dc9c6
JB		 3759 /* In general, don't allow 32-bit operands on pre-386. */
3760 else if (i.suffix == LONG_MNEM_SUFFIX
3761 && !cpu_arch_flags.bitfield.cpui386
3762 && (intel_syntax
3763 ? (!t->opcode_modifier.ignoresize
3764 && !intel_float_operand (t->name))
3765 : intel_float_operand (t->name) != 2)
3766 && ((!operand_types[0].bitfield.regmmx
3767 && !operand_types[0].bitfield.regxmm)
3768 || (!operand_types[t->operands > 1].bitfield.regmmx
3769 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3770 continue;
3771
29b0f896 3772 /* Do not verify operands when there are none. */
50aecf8c 3773 else
29b0f896 3774 {
c6fb90c8 3775 if (!t->operands)
2dbab7d5
L		 3776 /* We've found a match; break out of loop. */
3777 break;
29b0f896 3778 }
252b5132 3779
539e75ad
L		 3780 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3781 into Disp32/Disp16/Disp32 operand. */
3782 if (i.prefix[ADDR_PREFIX] != 0)
3783 {
40fb9820 3784 /* There should be only one Disp operand. */
539e75ad
L		 3785 switch (flag_code)
3786 {
3787 case CODE_16BIT:
40fb9820
L		 3788 for (j = 0; j < MAX_OPERANDS; j++)
3789 {
3790 if (operand_types[j].bitfield.disp16)
3791 {
3792 addr_prefix_disp = j;
3793 operand_types[j].bitfield.disp32 = 1;
3794 operand_types[j].bitfield.disp16 = 0;
3795 break;
3796 }
3797 }
539e75ad
L		 3798 break;
3799 case CODE_32BIT:
40fb9820
L		 3800 for (j = 0; j < MAX_OPERANDS; j++)
3801 {
3802 if (operand_types[j].bitfield.disp32)
3803 {
3804 addr_prefix_disp = j;
3805 operand_types[j].bitfield.disp32 = 0;
3806 operand_types[j].bitfield.disp16 = 1;
3807 break;
3808 }
3809 }
539e75ad
L		 3810 break;
3811 case CODE_64BIT:
40fb9820
L		 3812 for (j = 0; j < MAX_OPERANDS; j++)
3813 {
3814 if (operand_types[j].bitfield.disp64)
3815 {
3816 addr_prefix_disp = j;
3817 operand_types[j].bitfield.disp64 = 0;
3818 operand_types[j].bitfield.disp32 = 1;
3819 break;
3820 }
3821 }
539e75ad
L		 3822 break;
3823 }
539e75ad
L		 3824 }
3825
45664ddb
L		 3826 /* We check register size only if size of operands can be
3827 encoded the canonical way. */
3828 check_register = t->opcode_modifier.w;
c6fb90c8 3829 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3830 switch (t->operands)
3831 {
3832 case 1:
40fb9820 3833 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3834 continue;
3835 break;
3836 case 2:
8b38ad71
L		 3837 /* xchg %eax, %eax is a special case. It is an aliase for nop
3838 only in 32bit mode and we can use opcode 0x90. In 64bit
3839 mode, we can't use 0x90 for xchg %eax, %eax since it should
3840 zero-extend %eax to %rax. */
3841 if (flag_code == CODE_64BIT
3842 && t->base_opcode == 0x90
0dfbf9d7
L		 3843 && operand_type_equal (&i.types [0], &acc32)
3844 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3845 continue;
b6169b20
L		 3846 if (i.swap_operand)
3847 {
3848 /* If we swap operand in encoding, we either match
3849 the next one or reverse direction of operands. */
3850 if (t->opcode_modifier.s)
3851 continue;
3852 else if (t->opcode_modifier.d)
3853 goto check_reverse;
3854 }
3855
29b0f896 3856 case 3:
fa99fab2
L		 3857 /* If we swap operand in encoding, we match the next one. */
3858 if (i.swap_operand && t->opcode_modifier.s)
3859 continue;
f48ff2ae 3860 case 4:
c0f3af97 3861 case 5:
c6fb90c8 3862 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3863 if (!operand_type_match (overlap0, i.types[0])
3864 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3865 || (check_register
3866 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3867 operand_types[0],
3868 overlap1, i.types[1],
3869 operand_types[1])))
29b0f896
AM		 3870 {
3871 /* Check if other direction is valid ... */
40fb9820 3872 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3873 continue;
3874
b6169b20 3875check_reverse:
29b0f896 3876 /* Try reversing direction of operands. */
c6fb90c8
L		 3877 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3878 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3879 if (!operand_type_match (overlap0, i.types[0])
3880 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3881 || (check_register
3882 && !operand_type_register_match (overlap0,
3883 i.types[0],
3884 operand_types[1],
3885 overlap1,
3886 i.types[1],
3887 operand_types[0])))
29b0f896
AM		 3888 {
3889 /* Does not match either direction. */
3890 continue;
3891 }
3892 /* found_reverse_match holds which of D or FloatDR
3893 we've found. */
40fb9820 3894 if (t->opcode_modifier.d)
8a2ed489 3895 found_reverse_match = Opcode_D;
40fb9820 3896 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3897 found_reverse_match = Opcode_FloatD;
3898 else
3899 found_reverse_match = 0;
40fb9820 3900 if (t->opcode_modifier.floatr)
8a2ed489 3901 found_reverse_match |= Opcode_FloatR;
29b0f896 3902 }
f48ff2ae 3903 else
29b0f896 3904 {
f48ff2ae 3905 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3906 switch (t->operands)
3907 {
c0f3af97
L		 3908 case 5:
3909 overlap4 = operand_type_and (i.types[4],
3910 operand_types[4]);
d1cbb4db 3911 case 4:
c6fb90c8
L		 3912 overlap3 = operand_type_and (i.types[3],
3913 operand_types[3]);
d1cbb4db 3914 case 3:
c6fb90c8
L		 3915 overlap2 = operand_type_and (i.types[2],
3916 operand_types[2]);
d1cbb4db
L		 3917 break;
3918 }
29b0f896 3919
f48ff2ae
L		 3920 switch (t->operands)
3921 {
c0f3af97
L		 3922 case 5:
3923 if (!operand_type_match (overlap4, i.types[4])
3924 || !operand_type_register_match (overlap3,
3925 i.types[3],
3926 operand_types[3],
3927 overlap4,
3928 i.types[4],
3929 operand_types[4]))
3930 continue;
f48ff2ae 3931 case 4:
40fb9820 3932 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3933 || (check_register
3934 && !operand_type_register_match (overlap2,
3935 i.types[2],
3936 operand_types[2],
3937 overlap3,
3938 i.types[3],
3939 operand_types[3])))
f48ff2ae
L		 3940 continue;
3941 case 3:
3942 /* Here we make use of the fact that there are no
3943 reverse match 3 operand instructions, and all 3
3944 operand instructions only need to be checked for
3945 register consistency between operands 2 and 3. */
40fb9820 3946 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3947 || (check_register
3948 && !operand_type_register_match (overlap1,
3949 i.types[1],
3950 operand_types[1],
3951 overlap2,
3952 i.types[2],
3953 operand_types[2])))
f48ff2ae
L		 3954 continue;
3955 break;
3956 }
29b0f896 3957 }
f48ff2ae 3958 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3959 slip through to break. */
3960 }
3629bb00 3961 if (!found_cpu_match)
29b0f896
AM		 3962 {
3963 found_reverse_match = 0;
3964 continue;
3965 }
c0f3af97 3966
29b0f896
AM		 3967 /* We've found a match; break out of loop. */
3968 break;
3969 }
3970
3971 if (t == current_templates->end)
3972 {
3973 /* We found no match. */
95f283e8
L		 3974 if (intel_syntax)
3975 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3976 current_templates->start->name);
3977 else
3978 as_bad (_("suffix or operands invalid for `%s'"),
3979 current_templates->start->name);
fa99fab2 3980 return NULL;
29b0f896 3981 }
252b5132 3982
29b0f896
AM		 3983 if (!quiet_warnings)
3984 {
3985 if (!intel_syntax
40fb9820
L		 3986 && (i.types[0].bitfield.jumpabsolute
3987 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3988 {
3989 as_warn (_("indirect %s without `*'"), t->name);
3990 }
3991
40fb9820
L		 3992 if (t->opcode_modifier.isprefix
3993 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3994 {
3995 /* Warn them that a data or address size prefix doesn't
3996 affect assembly of the next line of code. */
3997 as_warn (_("stand-alone `%s' prefix"), t->name);
3998 }
3999 }
4000
4001 /* Copy the template we found. */
4002 i.tm = *t;
539e75ad
L		 4003
4004 if (addr_prefix_disp != -1)
4005 i.tm.operand_types[addr_prefix_disp]
4006 = operand_types[addr_prefix_disp];
4007
29b0f896
AM		 4008 if (found_reverse_match)
4009 {
4010 /* If we found a reverse match we must alter the opcode
4011 direction bit. found_reverse_match holds bits to change
4012 (different for int & float insns). */
4013
4014 i.tm.base_opcode ^= found_reverse_match;
4015
539e75ad
L		 4016 i.tm.operand_types[0] = operand_types[1];
4017 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4018 }
4019
fa99fab2 4020 return t;
29b0f896
AM		 4021}
4022
4023static int
e3bb37b5 4024check_string (void)
29b0f896 4025{
40fb9820
L		 4026 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4027 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4028 {
4029 if (i.seg[0] != NULL && i.seg[0] != &es)
4030 {
a87af027 4031 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4032 i.tm.name,
a87af027
JB		 4033 mem_op + 1,
4034 register_prefix);
29b0f896
AM		 4035 return 0;
4036 }
4037 /* There's only ever one segment override allowed per instruction.
4038 This instruction possibly has a legal segment override on the
4039 second operand, so copy the segment to where non-string
4040 instructions store it, allowing common code. */
4041 i.seg[0] = i.seg[1];
4042 }
40fb9820 4043 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4044 {
4045 if (i.seg[1] != NULL && i.seg[1] != &es)
4046 {
a87af027 4047 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4048 i.tm.name,
a87af027
JB		 4049 mem_op + 2,
4050 register_prefix);
29b0f896
AM		 4051 return 0;
4052 }
4053 }
4054 return 1;
4055}
4056
4057static int
543613e9 4058process_suffix (void)
29b0f896
AM		 4059{
4060 /* If matched instruction specifies an explicit instruction mnemonic
4061 suffix, use it. */
40fb9820
L		 4062 if (i.tm.opcode_modifier.size16)
4063 i.suffix = WORD_MNEM_SUFFIX;
4064 else if (i.tm.opcode_modifier.size32)
4065 i.suffix = LONG_MNEM_SUFFIX;
4066 else if (i.tm.opcode_modifier.size64)
4067 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4068 else if (i.reg_operands)
4069 {
4070 /* If there's no instruction mnemonic suffix we try to invent one
4071 based on register operands. */
4072 if (!i.suffix)
4073 {
4074 /* We take i.suffix from the last register operand specified,
4075 Destination register type is more significant than source
381d071f
L		 4076 register type. crc32 in SSE4.2 prefers source register
4077 type. */
4078 if (i.tm.base_opcode == 0xf20f38f1)
4079 {
40fb9820
L		 4080 if (i.types[0].bitfield.reg16)
4081 i.suffix = WORD_MNEM_SUFFIX;
4082 else if (i.types[0].bitfield.reg32)
4083 i.suffix = LONG_MNEM_SUFFIX;
4084 else if (i.types[0].bitfield.reg64)
4085 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4086 }
9344ff29 4087 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4088 {
40fb9820 4089 if (i.types[0].bitfield.reg8)
20592a94
L		 4090 i.suffix = BYTE_MNEM_SUFFIX;
4091 }
381d071f
L		 4092
4093 if (!i.suffix)
4094 {
4095 int op;
4096
20592a94
L		 4097 if (i.tm.base_opcode == 0xf20f38f1
4098 || i.tm.base_opcode == 0xf20f38f0)
4099 {
4100 /* We have to know the operand size for crc32. */
4101 as_bad (_("ambiguous memory operand size for `%s`"),
4102 i.tm.name);
4103 return 0;
4104 }
4105
381d071f 4106 for (op = i.operands; --op >= 0;)
40fb9820 4107 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4108 {
40fb9820
L		 4109 if (i.types[op].bitfield.reg8)
4110 {
4111 i.suffix = BYTE_MNEM_SUFFIX;
4112 break;
4113 }
4114 else if (i.types[op].bitfield.reg16)
4115 {
4116 i.suffix = WORD_MNEM_SUFFIX;
4117 break;
4118 }
4119 else if (i.types[op].bitfield.reg32)
4120 {
4121 i.suffix = LONG_MNEM_SUFFIX;
4122 break;
4123 }
4124 else if (i.types[op].bitfield.reg64)
4125 {
4126 i.suffix = QWORD_MNEM_SUFFIX;
4127 break;
4128 }
381d071f
L		 4129 }
4130 }
29b0f896
AM		 4131 }
4132 else if (i.suffix == BYTE_MNEM_SUFFIX)
4133 {
4134 if (!check_byte_reg ())
4135 return 0;
4136 }
4137 else if (i.suffix == LONG_MNEM_SUFFIX)
4138 {
4139 if (!check_long_reg ())
4140 return 0;
4141 }
4142 else if (i.suffix == QWORD_MNEM_SUFFIX)
4143 {
955e1e6a
L		 4144 if (intel_syntax
4145 && i.tm.opcode_modifier.ignoresize
4146 && i.tm.opcode_modifier.no_qsuf)
4147 i.suffix = 0;
4148 else if (!check_qword_reg ())
29b0f896
AM		 4149 return 0;
4150 }
4151 else if (i.suffix == WORD_MNEM_SUFFIX)
4152 {
4153 if (!check_word_reg ())
4154 return 0;
4155 }
c0f3af97
L		 4156 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4157 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4158 {
c0f3af97 4159 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4160 should check if it is a valid suffix. */
4161 }
40fb9820 4162 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4163 /* Do nothing if the instruction is going to ignore the prefix. */
4164 ;
4165 else
4166 abort ();
4167 }
40fb9820 4168 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4169 && !i.suffix
4170 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4171 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4172 {
4173 i.suffix = stackop_size;
4174 }
9306ca4a
JB		 4175 else if (intel_syntax
4176 && !i.suffix
40fb9820
L		 4177 && (i.tm.operand_types[0].bitfield.jumpabsolute
4178 || i.tm.opcode_modifier.jumpbyte
4179 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4180 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4181 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4182 {
4183 switch (flag_code)
4184 {
4185 case CODE_64BIT:
40fb9820 4186 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4187 {
4188 i.suffix = QWORD_MNEM_SUFFIX;
4189 break;
4190 }
4191 case CODE_32BIT:
40fb9820 4192 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4193 i.suffix = LONG_MNEM_SUFFIX;
4194 break;
4195 case CODE_16BIT:
40fb9820 4196 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4197 i.suffix = WORD_MNEM_SUFFIX;
4198 break;
4199 }
4200 }
252b5132 4201
9306ca4a 4202 if (!i.suffix)
29b0f896 4203 {
9306ca4a
JB		 4204 if (!intel_syntax)
4205 {
40fb9820 4206 if (i.tm.opcode_modifier.w)
9306ca4a 4207 {
4eed87de
AM		 4208 as_bad (_("no instruction mnemonic suffix given and "
4209 "no register operands; can't size instruction"));
9306ca4a
JB		 4210 return 0;
4211 }
4212 }
4213 else
4214 {
40fb9820 4215 unsigned int suffixes;
7ab9ffdd 4216
40fb9820
L		 4217 suffixes = !i.tm.opcode_modifier.no_bsuf;
4218 if (!i.tm.opcode_modifier.no_wsuf)
4219 suffixes |= 1 << 1;
4220 if (!i.tm.opcode_modifier.no_lsuf)
4221 suffixes |= 1 << 2;
fc4adea1 4222 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4223 suffixes |= 1 << 3;
4224 if (!i.tm.opcode_modifier.no_ssuf)
4225 suffixes |= 1 << 4;
4226 if (!i.tm.opcode_modifier.no_qsuf)
4227 suffixes |= 1 << 5;
4228
4229 /* There are more than suffix matches. */
4230 if (i.tm.opcode_modifier.w
9306ca4a 4231 || ((suffixes & (suffixes - 1))
40fb9820
L		 4232 && !i.tm.opcode_modifier.defaultsize
4233 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4234 {
4235 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4236 return 0;
4237 }
4238 }
29b0f896 4239 }
252b5132 4240
9306ca4a
JB		 4241 /* Change the opcode based on the operand size given by i.suffix;
4242 We don't need to change things for byte insns. */
4243
582d5edd
L		 4244 if (i.suffix
4245 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4246 && i.suffix != XMMWORD_MNEM_SUFFIX
4247 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4248 {
4249 /* It's not a byte, select word/dword operation. */
40fb9820 4250 if (i.tm.opcode_modifier.w)
29b0f896 4251 {
40fb9820 4252 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4253 i.tm.base_opcode |= 8;
4254 else
4255 i.tm.base_opcode |= 1;
4256 }
0f3f3d8b 4257
29b0f896
AM		 4258 /* Now select between word & dword operations via the operand
4259 size prefix, except for instructions that will ignore this
4260 prefix anyway. */
ca61edf2 4261 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4262 {
ca61edf2
L		 4263 /* The address size override prefix changes the size of the
4264 first operand. */
40fb9820
L		 4265 if ((flag_code == CODE_32BIT
4266 && i.op->regs[0].reg_type.bitfield.reg16)
4267 || (flag_code != CODE_32BIT
4268 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4269 if (!add_prefix (ADDR_PREFIX_OPCODE))
4270 return 0;
4271 }
4272 else if (i.suffix != QWORD_MNEM_SUFFIX
4273 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4274 && !i.tm.opcode_modifier.ignoresize
4275 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4276 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4277 || (flag_code == CODE_64BIT
40fb9820 4278 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4279 {
4280 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4281
40fb9820 4282 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4283 prefix = ADDR_PREFIX_OPCODE;
252b5132 4284
29b0f896
AM		 4285 if (!add_prefix (prefix))
4286 return 0;
24eab124 4287 }
252b5132 4288
29b0f896
AM		 4289 /* Set mode64 for an operand. */
4290 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4291 && flag_code == CODE_64BIT
40fb9820 4292 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4293 {
4294 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4295 need rex64. cmpxchg8b is also a special case. */
4296 if (! (i.operands == 2
4297 && i.tm.base_opcode == 0x90
4298 && i.tm.extension_opcode == None
0dfbf9d7
L		 4299 && operand_type_equal (&i.types [0], &acc64)
4300 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4301 && ! (i.operands == 1
4302 && i.tm.base_opcode == 0xfc7
4303 && i.tm.extension_opcode == 1
40fb9820
L		 4304 && !operand_type_check (i.types [0], reg)
4305 && operand_type_check (i.types [0], anymem)))
f6bee062 4306 i.rex |= REX_W;
46e883c5 4307 }
3e73aa7c 4308
29b0f896
AM		 4309 /* Size floating point instruction. */
4310 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4311 if (i.tm.opcode_modifier.floatmf)
543613e9 4312 i.tm.base_opcode ^= 4;
29b0f896 4313 }
7ecd2f8b 4314
29b0f896
AM		 4315 return 1;
4316}
3e73aa7c 4317
29b0f896 4318static int
543613e9 4319check_byte_reg (void)
29b0f896
AM		 4320{
4321 int op;
543613e9 4322
29b0f896
AM		 4323 for (op = i.operands; --op >= 0;)
4324 {
4325 /* If this is an eight bit register, it's OK. If it's the 16 or
4326 32 bit version of an eight bit register, we will just use the
4327 low portion, and that's OK too. */
40fb9820 4328 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4329 continue;
4330
ca61edf2
L		 4331 /* Don't generate this warning if not needed. */
4332 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4333 continue;
4334
9344ff29
L		 4335 /* crc32 doesn't generate this warning. */
4336 if (i.tm.base_opcode == 0xf20f38f0)
4337 continue;
4338
40fb9820
L		 4339 if ((i.types[op].bitfield.reg16
4340 || i.types[op].bitfield.reg32
4341 || i.types[op].bitfield.reg64)
4342 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4343 {
4344 /* Prohibit these changes in the 64bit mode, since the
4345 lowering is more complicated. */
4346 if (flag_code == CODE_64BIT
40fb9820 4347 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4348 {
2ca3ace5
L		 4349 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4350 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4351 i.suffix);
4352 return 0;
4353 }
4354#if REGISTER_WARNINGS
4355 if (!quiet_warnings
40fb9820 4356 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4357 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4358 register_prefix,
40fb9820 4359 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4360 ? REGNAM_AL - REGNAM_AX
4361 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4362 register_prefix,
29b0f896
AM		 4363 i.op[op].regs->reg_name,
4364 i.suffix);
4365#endif
4366 continue;
4367 }
4368 /* Any other register is bad. */
40fb9820
L		 4369 if (i.types[op].bitfield.reg16
4370 || i.types[op].bitfield.reg32
4371 || i.types[op].bitfield.reg64
4372 || i.types[op].bitfield.regmmx
4373 || i.types[op].bitfield.regxmm
c0f3af97 4374 || i.types[op].bitfield.regymm
40fb9820
L		 4375 || i.types[op].bitfield.sreg2
4376 || i.types[op].bitfield.sreg3
4377 || i.types[op].bitfield.control
4378 || i.types[op].bitfield.debug
4379 || i.types[op].bitfield.test
4380 || i.types[op].bitfield.floatreg
4381 || i.types[op].bitfield.floatacc)
29b0f896 4382 {
a540244d
L		 4383 as_bad (_("`%s%s' not allowed with `%s%c'"),
4384 register_prefix,
29b0f896
AM		 4385 i.op[op].regs->reg_name,
4386 i.tm.name,
4387 i.suffix);
4388 return 0;
4389 }
4390 }
4391 return 1;
4392}
4393
4394static int
e3bb37b5 4395check_long_reg (void)
29b0f896
AM		 4396{
4397 int op;
4398
4399 for (op = i.operands; --op >= 0;)
4400 /* Reject eight bit registers, except where the template requires
4401 them. (eg. movzb) */
40fb9820
L		 4402 if (i.types[op].bitfield.reg8
4403 && (i.tm.operand_types[op].bitfield.reg16
4404 || i.tm.operand_types[op].bitfield.reg32
4405 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4406 {
a540244d
L		 4407 as_bad (_("`%s%s' not allowed with `%s%c'"),
4408 register_prefix,
29b0f896
AM		 4409 i.op[op].regs->reg_name,
4410 i.tm.name,
4411 i.suffix);
4412 return 0;
4413 }
4414 /* Warn if the e prefix on a general reg is missing. */
4415 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4416 && i.types[op].bitfield.reg16
4417 && (i.tm.operand_types[op].bitfield.reg32
4418 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4419 {
4420 /* Prohibit these changes in the 64bit mode, since the
4421 lowering is more complicated. */
4422 if (flag_code == CODE_64BIT)
252b5132 4423 {
2ca3ace5
L		 4424 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4425 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4426 i.suffix);
4427 return 0;
252b5132 4428 }
29b0f896
AM		 4429#if REGISTER_WARNINGS
4430 else
a540244d
L		 4431 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4432 register_prefix,
29b0f896 4433 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4434 register_prefix,
29b0f896
AM		 4435 i.op[op].regs->reg_name,
4436 i.suffix);
4437#endif
252b5132 4438 }
29b0f896 4439 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4440 else if (i.types[op].bitfield.reg64
4441 && (i.tm.operand_types[op].bitfield.reg32
4442 || i.tm.operand_types[op].bitfield.acc))
252b5132 4443 {
34828aad 4444 if (intel_syntax
ca61edf2 4445 && i.tm.opcode_modifier.toqword
40fb9820 4446 && !i.types[0].bitfield.regxmm)
34828aad 4447 {
ca61edf2 4448 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4449 i.suffix = QWORD_MNEM_SUFFIX;
4450 }
4451 else
4452 {
4453 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4454 register_prefix, i.op[op].regs->reg_name,
4455 i.suffix);
4456 return 0;
4457 }
29b0f896
AM		 4458 }
4459 return 1;
4460}
252b5132 4461
29b0f896 4462static int
e3bb37b5 4463check_qword_reg (void)
29b0f896
AM		 4464{
4465 int op;
252b5132 4466
29b0f896
AM		 4467 for (op = i.operands; --op >= 0; )
4468 /* Reject eight bit registers, except where the template requires
4469 them. (eg. movzb) */
40fb9820
L		 4470 if (i.types[op].bitfield.reg8
4471 && (i.tm.operand_types[op].bitfield.reg16
4472 || i.tm.operand_types[op].bitfield.reg32
4473 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4474 {
a540244d
L		 4475 as_bad (_("`%s%s' not allowed with `%s%c'"),
4476 register_prefix,
29b0f896
AM		 4477 i.op[op].regs->reg_name,
4478 i.tm.name,
4479 i.suffix);
4480 return 0;
4481 }
4482 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4483 else if ((i.types[op].bitfield.reg16
4484 || i.types[op].bitfield.reg32)
4485 && (i.tm.operand_types[op].bitfield.reg32
4486 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4487 {
4488 /* Prohibit these changes in the 64bit mode, since the
4489 lowering is more complicated. */
34828aad 4490 if (intel_syntax
ca61edf2 4491 && i.tm.opcode_modifier.todword
40fb9820 4492 && !i.types[0].bitfield.regxmm)
34828aad 4493 {
ca61edf2 4494 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4495 i.suffix = LONG_MNEM_SUFFIX;
4496 }
4497 else
4498 {
4499 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4500 register_prefix, i.op[op].regs->reg_name,
4501 i.suffix);
4502 return 0;
4503 }
252b5132 4504 }
29b0f896
AM		 4505 return 1;
4506}
252b5132 4507
29b0f896 4508static int
e3bb37b5 4509check_word_reg (void)
29b0f896
AM		 4510{
4511 int op;
4512 for (op = i.operands; --op >= 0;)
4513 /* Reject eight bit registers, except where the template requires
4514 them. (eg. movzb) */
40fb9820
L		 4515 if (i.types[op].bitfield.reg8
4516 && (i.tm.operand_types[op].bitfield.reg16
4517 || i.tm.operand_types[op].bitfield.reg32
4518 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4519 {
a540244d
L		 4520 as_bad (_("`%s%s' not allowed with `%s%c'"),
4521 register_prefix,
29b0f896
AM		 4522 i.op[op].regs->reg_name,
4523 i.tm.name,
4524 i.suffix);
4525 return 0;
4526 }
4527 /* Warn if the e prefix on a general reg is present. */
4528 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4529 && i.types[op].bitfield.reg32
4530 && (i.tm.operand_types[op].bitfield.reg16
4531 || i.tm.operand_types[op].bitfield.acc))
252b5132 4532 {
29b0f896
AM		 4533 /* Prohibit these changes in the 64bit mode, since the
4534 lowering is more complicated. */
4535 if (flag_code == CODE_64BIT)
252b5132 4536 {
2ca3ace5
L		 4537 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4538 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4539 i.suffix);
4540 return 0;
252b5132 4541 }
29b0f896
AM		 4542 else
4543#if REGISTER_WARNINGS
a540244d
L		 4544 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4545 register_prefix,
29b0f896 4546 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4547 register_prefix,
29b0f896
AM		 4548 i.op[op].regs->reg_name,
4549 i.suffix);
4550#endif
4551 }
4552 return 1;
4553}
252b5132 4554
29b0f896 4555static int
40fb9820 4556update_imm (unsigned int j)
29b0f896 4557{
bc0844ae 4558 i386_operand_type overlap = i.types[j];
40fb9820
L		 4559 if ((overlap.bitfield.imm8
4560 || overlap.bitfield.imm8s
4561 || overlap.bitfield.imm16
4562 || overlap.bitfield.imm32
4563 || overlap.bitfield.imm32s
4564 || overlap.bitfield.imm64)
0dfbf9d7
L		 4565 && !operand_type_equal (&overlap, &imm8)
4566 && !operand_type_equal (&overlap, &imm8s)
4567 && !operand_type_equal (&overlap, &imm16)
4568 && !operand_type_equal (&overlap, &imm32)
4569 && !operand_type_equal (&overlap, &imm32s)
4570 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4571 {
4572 if (i.suffix)
4573 {
40fb9820
L		 4574 i386_operand_type temp;
4575
0dfbf9d7 4576 operand_type_set (&temp, 0);
7ab9ffdd 4577 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4578 {
4579 temp.bitfield.imm8 = overlap.bitfield.imm8;
4580 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4581 }
4582 else if (i.suffix == WORD_MNEM_SUFFIX)
4583 temp.bitfield.imm16 = overlap.bitfield.imm16;
4584 else if (i.suffix == QWORD_MNEM_SUFFIX)
4585 {
4586 temp.bitfield.imm64 = overlap.bitfield.imm64;
4587 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4588 }
4589 else
4590 temp.bitfield.imm32 = overlap.bitfield.imm32;
4591 overlap = temp;
29b0f896 4592 }
0dfbf9d7
L		 4593 else if (operand_type_equal (&overlap, &imm16_32_32s)
4594 || operand_type_equal (&overlap, &imm16_32)
4595 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4596 {
40fb9820 4597 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4598 overlap = imm16;
40fb9820 4599 else
65da13b5 4600 overlap = imm32s;
29b0f896 4601 }
0dfbf9d7
L		 4602 if (!operand_type_equal (&overlap, &imm8)
4603 && !operand_type_equal (&overlap, &imm8s)
4604 && !operand_type_equal (&overlap, &imm16)
4605 && !operand_type_equal (&overlap, &imm32)
4606 && !operand_type_equal (&overlap, &imm32s)
4607 && !operand_type_equal (&overlap, &imm64))
29b0f896 4608 {
4eed87de
AM		 4609 as_bad (_("no instruction mnemonic suffix given; "
4610 "can't determine immediate size"));
29b0f896
AM		 4611 return 0;
4612 }
4613 }
40fb9820 4614 i.types[j] = overlap;
29b0f896 4615
40fb9820
L		 4616 return 1;
4617}
4618
4619static int
4620finalize_imm (void)
4621{
bc0844ae 4622 unsigned int j, n;
29b0f896 4623
bc0844ae
L		 4624 /* Update the first 2 immediate operands. */
4625 n = i.operands > 2 ? 2 : i.operands;
4626 if (n)
4627 {
4628 for (j = 0; j < n; j++)
4629 if (update_imm (j) == 0)
4630 return 0;
40fb9820 4631
bc0844ae
L		 4632 /* The 3rd operand can't be immediate operand. */
4633 gas_assert (operand_type_check (i.types[2], imm) == 0);
4634 }
29b0f896
AM		 4635
4636 return 1;
4637}
4638
c0f3af97
L		 4639static int
4640bad_implicit_operand (int xmm)
4641{
4642 const char *reg = xmm ? "xmm0" : "ymm0";
4643 if (intel_syntax)
4644 as_bad (_("the last operand of `%s' must be `%s%s'"),
4645 i.tm.name, register_prefix, reg);
4646 else
4647 as_bad (_("the first operand of `%s' must be `%s%s'"),
4648 i.tm.name, register_prefix, reg);
4649 return 0;
4650}
4651
29b0f896 4652static int
e3bb37b5 4653process_operands (void)
29b0f896
AM		 4654{
4655 /* Default segment register this instruction will use for memory
4656 accesses. 0 means unknown. This is only for optimizing out
4657 unnecessary segment overrides. */
4658 const seg_entry *default_seg = 0;
4659
c0f3af97
L		 4660 if (i.tm.opcode_modifier.sse2avx
4661 && (i.tm.opcode_modifier.vexnds
4662 || i.tm.opcode_modifier.vexndd))
29b0f896 4663 {
c0f3af97
L		 4664 unsigned int dup = i.operands;
4665 unsigned int dest = dup - 1;
9fcfb3d7
L		 4666 unsigned int j;
4667
c0f3af97 4668 /* The destination must be an xmm register. */
9c2799c2 4669 gas_assert (i.reg_operands
7ab9ffdd
L		 4670 && MAX_OPERANDS > dup
4671 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4672
4673 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4674 {
c0f3af97 4675 /* The first operand is implicit and must be xmm0. */
9c2799c2 4676 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4677 if (i.op[0].regs->reg_num != 0)
4678 return bad_implicit_operand (1);
4679
4680 if (i.tm.opcode_modifier.vex3sources)
4681 {
4682 /* Keep xmm0 for instructions with VEX prefix and 3
4683 sources. */
4684 goto duplicate;
4685 }
e2ec9d29 4686 else
c0f3af97
L		 4687 {
4688 /* We remove the first xmm0 and keep the number of
4689 operands unchanged, which in fact duplicates the
4690 destination. */
4691 for (j = 1; j < i.operands; j++)
4692 {
4693 i.op[j - 1] = i.op[j];
4694 i.types[j - 1] = i.types[j];
4695 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4696 }
4697 }
4698 }
4699 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4700 {
9c2799c2 4701 gas_assert ((MAX_OPERANDS - 1) > dup
7ab9ffdd 4702 && i.tm.opcode_modifier.vex3sources);
c0f3af97
L		 4703
4704 /* Add the implicit xmm0 for instructions with VEX prefix
4705 and 3 sources. */
4706 for (j = i.operands; j > 0; j--)
4707 {
4708 i.op[j] = i.op[j - 1];
4709 i.types[j] = i.types[j - 1];
4710 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4711 }
4712 i.op[0].regs
4713 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4714 i.types[0] = regxmm;
c0f3af97
L		 4715 i.tm.operand_types[0] = regxmm;
4716
4717 i.operands += 2;
4718 i.reg_operands += 2;
4719 i.tm.operands += 2;
4720
4721 dup++;
4722 dest++;
4723 i.op[dup] = i.op[dest];
4724 i.types[dup] = i.types[dest];
4725 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4726 }
c0f3af97
L		 4727 else
4728 {
4729duplicate:
4730 i.operands++;
4731 i.reg_operands++;
4732 i.tm.operands++;
4733
4734 i.op[dup] = i.op[dest];
4735 i.types[dup] = i.types[dest];
4736 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4737 }
4738
4739 if (i.tm.opcode_modifier.immext)
4740 process_immext ();
4741 }
4742 else if (i.tm.opcode_modifier.firstxmm0)
4743 {
4744 unsigned int j;
4745
4746 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4747 gas_assert (i.reg_operands
7ab9ffdd
L		 4748 && (operand_type_equal (&i.types[0], &regxmm)
4749 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4750 if (i.op[0].regs->reg_num != 0)
4751 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4752
4753 for (j = 1; j < i.operands; j++)
4754 {
4755 i.op[j - 1] = i.op[j];
4756 i.types[j - 1] = i.types[j];
4757
4758 /* We need to adjust fields in i.tm since they are used by
4759 build_modrm_byte. */
4760 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4761 }
4762
e2ec9d29
L		 4763 i.operands--;
4764 i.reg_operands--;
e2ec9d29
L		 4765 i.tm.operands--;
4766 }
4767 else if (i.tm.opcode_modifier.regkludge)
4768 {
4769 /* The imul $imm, %reg instruction is converted into
4770 imul $imm, %reg, %reg, and the clr %reg instruction
4771 is converted into xor %reg, %reg. */
4772
4773 unsigned int first_reg_op;
4774
4775 if (operand_type_check (i.types[0], reg))
4776 first_reg_op = 0;
4777 else
4778 first_reg_op = 1;
4779 /* Pretend we saw the extra register operand. */
9c2799c2 4780 gas_assert (i.reg_operands == 1
7ab9ffdd 4781 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4782 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4783 i.types[first_reg_op + 1] = i.types[first_reg_op];
4784 i.operands++;
4785 i.reg_operands++;
29b0f896
AM		 4786 }
4787
40fb9820 4788 if (i.tm.opcode_modifier.shortform)
29b0f896 4789 {
40fb9820
L		 4790 if (i.types[0].bitfield.sreg2
4791 || i.types[0].bitfield.sreg3)
29b0f896 4792 {
4eed87de
AM		 4793 if (i.tm.base_opcode == POP_SEG_SHORT
4794 && i.op[0].regs->reg_num == 1)
29b0f896 4795 {
a87af027 4796 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4797 return 0;
29b0f896 4798 }
4eed87de
AM		 4799 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4800 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4801 i.rex |= REX_B;
4eed87de
AM		 4802 }
4803 else
4804 {
7ab9ffdd 4805 /* The register or float register operand is in operand
85f10a01 4806 0 or 1. */
40fb9820 4807 unsigned int op;
7ab9ffdd
L		 4808
4809 if (i.types[0].bitfield.floatreg
4810 || operand_type_check (i.types[0], reg))
4811 op = 0;
4812 else
4813 op = 1;
4eed87de
AM		 4814 /* Register goes in low 3 bits of opcode. */
4815 i.tm.base_opcode |= i.op[op].regs->reg_num;
4816 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4817 i.rex |= REX_B;
40fb9820 4818 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4819 {
4eed87de
AM		 4820 /* Warn about some common errors, but press on regardless.
4821 The first case can be generated by gcc (<= 2.8.1). */
4822 if (i.operands == 2)
4823 {
4824 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4825 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4826 register_prefix, i.op[!intel_syntax].regs->reg_name,
4827 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4828 }
4829 else
4830 {
4831 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4832 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4833 register_prefix, i.op[0].regs->reg_name);
4eed87de 4834 }
29b0f896
AM		 4835 }
4836 }
4837 }
40fb9820 4838 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4839 {
4840 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4841 must be put into the modrm byte). Now, we make the modrm and
4842 index base bytes based on all the info we've collected. */
29b0f896
AM		 4843
4844 default_seg = build_modrm_byte ();
4845 }
8a2ed489 4846 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4847 {
4848 default_seg = &ds;
4849 }
40fb9820 4850 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4851 {
4852 /* For the string instructions that allow a segment override
4853 on one of their operands, the default segment is ds. */
4854 default_seg = &ds;
4855 }
4856
75178d9d
L		 4857 if (i.tm.base_opcode == 0x8d /* lea */
4858 && i.seg[0]
4859 && !quiet_warnings)
30123838 4860 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4861
4862 /* If a segment was explicitly specified, and the specified segment
4863 is not the default, use an opcode prefix to select it. If we
4864 never figured out what the default segment is, then default_seg
4865 will be zero at this point, and the specified segment prefix will
4866 always be used. */
29b0f896
AM		 4867 if ((i.seg[0]) && (i.seg[0] != default_seg))
4868 {
4869 if (!add_prefix (i.seg[0]->seg_prefix))
4870 return 0;
4871 }
4872 return 1;
4873}
4874
4875static const seg_entry *
e3bb37b5 4876build_modrm_byte (void)
29b0f896
AM		 4877{
4878 const seg_entry *default_seg = 0;
c0f3af97 4879 unsigned int source, dest;
7ab9ffdd 4880 int vex_3_sources;
c0f3af97
L		 4881
4882 /* The first operand of instructions with VEX prefix and 3 sources
4883 must be VEX_Imm4. */
4884 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4885 if (vex_3_sources)
4886 {
4887 unsigned int nds, reg;
4c2c6516 4888 expressionS *exp;
c0f3af97 4889
922d8de8
DR		 4890 if (i.tm.opcode_modifier.veximmext
4891 && i.tm.opcode_modifier.immext)
4892 {
4893 dest = i.operands - 2;
4894 gas_assert (dest == 3);
4895 }
4896 else
0bfee649 4897 dest = i.operands - 1;
c0f3af97 4898 nds = dest - 1;
922d8de8 4899
76ba9986
L		 4900 /* This instruction must have 4 register operands
4901 or 3 register operands plus 1 memory operand.
922d8de8
DR		 4902 It must have VexNDS and VexImmExt. */
4903 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4904 || (i.reg_operands == 3 && i.mem_operands == 1))
4905 && i.tm.opcode_modifier.vexnds
4906 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4907 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4908 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4909
0bfee649
L		 4910 /* Generate an 8bit immediate operand to encode the register
4911 operand. */
4c2c6516 4912 exp = &im_expressions[i.imm_operands++];
0bfee649
L		 4913 i.op[i.operands].imms = exp;
4914 i.types[i.operands] = imm8;
4915 i.operands++;
922d8de8
DR		 4916 /* If VexW1 is set, the first operand is the source and
4917 the second operand is encoded in the immediate operand. */
4918 if (i.tm.opcode_modifier.vexw1)
4919 {
4920 source = 0;
4921 reg = 1;
4922 }
4923 else
4924 {
4925 source = 1;
4926 reg = 0;
76ba9986 4927 }
922d8de8
DR		 4928 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], &regxmm)
4929 || operand_type_equal (&i.tm.operand_types[reg],
76ba9986 4930 &regymm))
922d8de8 4931 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
76ba9986 4932 || operand_type_equal (&i.tm.operand_types[nds],
922d8de8 4933 &regymm)));
0bfee649
L		 4934 exp->X_op = O_constant;
4935 exp->X_add_number
922d8de8 4936 = ((i.op[reg].regs->reg_num
76ba9986 4937 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4938 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4939 }
4940 else
4941 source = dest = 0;
29b0f896
AM		 4942
4943 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4944 implicit registers do not count. If there are 3 register
4945 operands, it must be a instruction with VexNDS. For a
4946 instruction with VexNDD, the destination register is encoded
4947 in VEX prefix. If there are 4 register operands, it must be
4948 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4949 if (i.mem_operands == 0
4950 && ((i.reg_operands == 2
f88c9eb0
SP		 4951 && !i.tm.opcode_modifier.vexndd
4952 && !i.tm.opcode_modifier.vexlwp)
7ab9ffdd
L		 4953 || (i.reg_operands == 3
4954 && i.tm.opcode_modifier.vexnds)
4955 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 4956 {
cab737b9
L		 4957 switch (i.operands)
4958 {
4959 case 2:
4960 source = 0;
4961 break;
4962 case 3:
c81128dc
L		 4963 /* When there are 3 operands, one of them may be immediate,
4964 which may be the first or the last operand. Otherwise,
c0f3af97
L		 4965 the first operand must be shift count register (cl) or it
4966 is an instruction with VexNDS. */
9c2799c2 4967 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 4968 || (i.imm_operands == 0
4969 && (i.tm.opcode_modifier.vexnds
4970 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 4971 if (operand_type_check (i.types[0], imm)
4972 || i.types[0].bitfield.shiftcount)
4973 source = 1;
4974 else
4975 source = 0;
cab737b9
L		 4976 break;
4977 case 4:
368d64cc
L		 4978 /* When there are 4 operands, the first two must be 8bit
4979 immediate operands. The source operand will be the 3rd
c0f3af97
L		 4980 one.
4981
4982 For instructions with VexNDS, if the first operand
4983 an imm8, the source operand is the 2nd one. If the last
4984 operand is imm8, the source operand is the first one. */
9c2799c2 4985 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 4986 && i.types[0].bitfield.imm8
4987 && i.types[1].bitfield.imm8)
4988 || (i.tm.opcode_modifier.vexnds
4989 && i.imm_operands == 1
4990 && (i.types[0].bitfield.imm8
4991 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 4992 if (i.tm.opcode_modifier.vexnds)
4993 {
4994 if (i.types[0].bitfield.imm8)
4995 source = 1;
4996 else
4997 source = 0;
4998 }
4999 else
5000 source = 2;
5001 break;
5002 case 5:
cab737b9
L		 5003 break;
5004 default:
5005 abort ();
5006 }
5007
c0f3af97
L		 5008 if (!vex_3_sources)
5009 {
5010 dest = source + 1;
5011
5012 if (i.tm.opcode_modifier.vexnds)
5013 {
5014 /* For instructions with VexNDS, the register-only
5015 source operand must be XMM or YMM register. It is
fa99fab2
L		 5016 encoded in VEX prefix. We need to clear RegMem bit
5017 before calling operand_type_equal. */
5018 i386_operand_type op = i.tm.operand_types[dest];
5019 op.bitfield.regmem = 0;
c0f3af97 5020 if ((dest + 1) >= i.operands
fa99fab2
L		 5021 || (!operand_type_equal (&op, &regxmm)
5022 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5023 abort ();
5024 i.vex.register_specifier = i.op[dest].regs;
5025 dest++;
5026 }
5027 }
29b0f896
AM		 5028
5029 i.rm.mode = 3;
5030 /* One of the register operands will be encoded in the i.tm.reg
5031 field, the other in the combined i.tm.mode and i.tm.regmem
5032 fields. If no form of this instruction supports a memory
5033 destination operand, then we assume the source operand may
5034 sometimes be a memory operand and so we need to store the
5035 destination in the i.rm.reg field. */
40fb9820
L		 5036 if (!i.tm.operand_types[dest].bitfield.regmem
5037 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5038 {
5039 i.rm.reg = i.op[dest].regs->reg_num;
5040 i.rm.regmem = i.op[source].regs->reg_num;
5041 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5042 i.rex |= REX_R;
29b0f896 5043 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5044 i.rex |= REX_B;
29b0f896
AM		 5045 }
5046 else
5047 {
5048 i.rm.reg = i.op[source].regs->reg_num;
5049 i.rm.regmem = i.op[dest].regs->reg_num;
5050 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5051 i.rex |= REX_B;
29b0f896 5052 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5053 i.rex |= REX_R;
29b0f896 5054 }
161a04f6 5055 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5056 {
40fb9820
L		 5057 if (!i.types[0].bitfield.control
5058 && !i.types[1].bitfield.control)
c4a530c5 5059 abort ();
161a04f6 5060 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5061 add_prefix (LOCK_PREFIX_OPCODE);
5062 }
29b0f896
AM		 5063 }
5064 else
5065 { /* If it's not 2 reg operands... */
c0f3af97
L		 5066 unsigned int mem;
5067
29b0f896
AM		 5068 if (i.mem_operands)
5069 {
5070 unsigned int fake_zero_displacement = 0;
99018f42 5071 unsigned int op;
4eed87de 5072
7ab9ffdd
L		 5073 for (op = 0; op < i.operands; op++)
5074 if (operand_type_check (i.types[op], anymem))
5075 break;
7ab9ffdd 5076 gas_assert (op < i.operands);
29b0f896
AM		 5077
5078 default_seg = &ds;
5079
5080 if (i.base_reg == 0)
5081 {
5082 i.rm.mode = 0;
5083 if (!i.disp_operands)
5084 fake_zero_displacement = 1;
5085 if (i.index_reg == 0)
5086 {
5087 /* Operand is just <disp> */
20f0a1fc 5088 if (flag_code == CODE_64BIT)
29b0f896
AM		 5089 {
5090 /* 64bit mode overwrites the 32bit absolute
5091 addressing by RIP relative addressing and
5092 absolute addressing is encoded by one of the
5093 redundant SIB forms. */
5094 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5095 i.sib.base = NO_BASE_REGISTER;
5096 i.sib.index = NO_INDEX_REGISTER;
fc225355 5097 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5098 ? disp32s : disp32);
20f0a1fc 5099 }
fc225355
L		 5100 else if ((flag_code == CODE_16BIT)
5101 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5102 {
5103 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5104 i.types[op] = disp16;
20f0a1fc
NC		 5105 }
5106 else
5107 {
5108 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5109 i.types[op] = disp32;
29b0f896
AM		 5110 }
5111 }
5112 else /* !i.base_reg && i.index_reg */
5113 {
db51cc60
L		 5114 if (i.index_reg->reg_num == RegEiz
5115 || i.index_reg->reg_num == RegRiz)
5116 i.sib.index = NO_INDEX_REGISTER;
5117 else
5118 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5119 i.sib.base = NO_BASE_REGISTER;
5120 i.sib.scale = i.log2_scale_factor;
5121 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5122 i.types[op].bitfield.disp8 = 0;
5123 i.types[op].bitfield.disp16 = 0;
5124 i.types[op].bitfield.disp64 = 0;
29b0f896 5125 if (flag_code != CODE_64BIT)
40fb9820
L		 5126 {
5127 /* Must be 32 bit */
5128 i.types[op].bitfield.disp32 = 1;
5129 i.types[op].bitfield.disp32s = 0;
5130 }
29b0f896 5131 else
40fb9820
L		 5132 {
5133 i.types[op].bitfield.disp32 = 0;
5134 i.types[op].bitfield.disp32s = 1;
5135 }
29b0f896 5136 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5137 i.rex |= REX_X;
29b0f896
AM		 5138 }
5139 }
5140 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5141 else if (i.base_reg->reg_num == RegRip ||
5142 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5143 {
5144 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5145 i.types[op].bitfield.disp8 = 0;
5146 i.types[op].bitfield.disp16 = 0;
5147 i.types[op].bitfield.disp32 = 0;
5148 i.types[op].bitfield.disp32s = 1;
5149 i.types[op].bitfield.disp64 = 0;
71903a11 5150 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5151 if (! i.disp_operands)
5152 fake_zero_displacement = 1;
29b0f896 5153 }
40fb9820 5154 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5155 {
5156 switch (i.base_reg->reg_num)
5157 {
5158 case 3: /* (%bx) */
5159 if (i.index_reg == 0)
5160 i.rm.regmem = 7;
5161 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5162 i.rm.regmem = i.index_reg->reg_num - 6;
5163 break;
5164 case 5: /* (%bp) */
5165 default_seg = &ss;
5166 if (i.index_reg == 0)
5167 {
5168 i.rm.regmem = 6;
40fb9820 5169 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5170 {
5171 /* fake (%bp) into 0(%bp) */
40fb9820 5172 i.types[op].bitfield.disp8 = 1;
252b5132 5173 fake_zero_displacement = 1;
29b0f896
AM		 5174 }
5175 }
5176 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5177 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5178 break;
5179 default: /* (%si) -> 4 or (%di) -> 5 */
5180 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5181 }
5182 i.rm.mode = mode_from_disp_size (i.types[op]);
5183 }
5184 else /* i.base_reg and 32/64 bit mode */
5185 {
5186 if (flag_code == CODE_64BIT
40fb9820
L		 5187 && operand_type_check (i.types[op], disp))
5188 {
5189 i386_operand_type temp;
0dfbf9d7 5190 operand_type_set (&temp, 0);
40fb9820
L		 5191 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5192 i.types[op] = temp;
5193 if (i.prefix[ADDR_PREFIX] == 0)
5194 i.types[op].bitfield.disp32s = 1;
5195 else
5196 i.types[op].bitfield.disp32 = 1;
5197 }
20f0a1fc 5198
29b0f896
AM		 5199 i.rm.regmem = i.base_reg->reg_num;
5200 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5201 i.rex |= REX_B;
29b0f896
AM		 5202 i.sib.base = i.base_reg->reg_num;
5203 /* x86-64 ignores REX prefix bit here to avoid decoder
5204 complications. */
5205 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5206 {
5207 default_seg = &ss;
5208 if (i.disp_operands == 0)
5209 {
5210 fake_zero_displacement = 1;
40fb9820 5211 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5212 }
5213 }
5214 else if (i.base_reg->reg_num == ESP_REG_NUM)
5215 {
5216 default_seg = &ss;
5217 }
5218 i.sib.scale = i.log2_scale_factor;
5219 if (i.index_reg == 0)
5220 {
5221 /* <disp>(%esp) becomes two byte modrm with no index
5222 register. We've already stored the code for esp
5223 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5224 Any base register besides %esp will not use the
5225 extra modrm byte. */
5226 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5227 }
5228 else
5229 {
db51cc60
L		 5230 if (i.index_reg->reg_num == RegEiz
5231 || i.index_reg->reg_num == RegRiz)
5232 i.sib.index = NO_INDEX_REGISTER;
5233 else
5234 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5235 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5236 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5237 i.rex |= REX_X;
29b0f896 5238 }
67a4f2b7
AO		 5239
5240 if (i.disp_operands
5241 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5242 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5243 i.rm.mode = 0;
5244 else
5245 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5246 }
252b5132 5247
29b0f896
AM		 5248 if (fake_zero_displacement)
5249 {
5250 /* Fakes a zero displacement assuming that i.types[op]
5251 holds the correct displacement size. */
5252 expressionS *exp;
5253
9c2799c2 5254 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5255 exp = &disp_expressions[i.disp_operands++];
5256 i.op[op].disps = exp;
5257 exp->X_op = O_constant;
5258 exp->X_add_number = 0;
5259 exp->X_add_symbol = (symbolS *) 0;
5260 exp->X_op_symbol = (symbolS *) 0;
5261 }
c0f3af97
L		 5262
5263 mem = op;
29b0f896 5264 }
c0f3af97
L		 5265 else
5266 mem = ~0;
252b5132 5267
f88c9eb0
SP		 5268 if (i.tm.opcode_modifier.vexlwp)
5269 {
5270 i.vex.register_specifier = i.op[2].regs;
5271 if (!i.mem_operands)
5272 {
5273 i.rm.mode = 3;
5274 i.rm.regmem = i.op[1].regs->reg_num;
5275 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5276 i.rex |= REX_B;
5277 }
5278 }
29b0f896
AM		 5279 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5280 (if any) based on i.tm.extension_opcode. Again, we must be
5281 careful to make sure that segment/control/debug/test/MMX
5282 registers are coded into the i.rm.reg field. */
f88c9eb0 5283 else if (i.reg_operands)
29b0f896 5284 {
99018f42 5285 unsigned int op;
7ab9ffdd
L		 5286 unsigned int vex_reg = ~0;
5287
5288 for (op = 0; op < i.operands; op++)
5289 if (i.types[op].bitfield.reg8
5290 || i.types[op].bitfield.reg16
5291 || i.types[op].bitfield.reg32
5292 || i.types[op].bitfield.reg64
5293 || i.types[op].bitfield.regmmx
5294 || i.types[op].bitfield.regxmm
5295 || i.types[op].bitfield.regymm
5296 || i.types[op].bitfield.sreg2
5297 || i.types[op].bitfield.sreg3
5298 || i.types[op].bitfield.control
5299 || i.types[op].bitfield.debug
5300 || i.types[op].bitfield.test)
5301 break;
c0209578 5302
7ab9ffdd
L		 5303 if (vex_3_sources)
5304 op = dest;
5305 else if (i.tm.opcode_modifier.vexnds)
5306 {
5307 /* For instructions with VexNDS, the register-only
5308 source operand is encoded in VEX prefix. */
5309 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5310
7ab9ffdd 5311 if (op > mem)
c0f3af97 5312 {
7ab9ffdd
L		 5313 vex_reg = op++;
5314 gas_assert (op < i.operands);
c0f3af97
L		 5315 }
5316 else
c0f3af97 5317 {
7ab9ffdd
L		 5318 vex_reg = op + 1;
5319 gas_assert (vex_reg < i.operands);
c0f3af97 5320 }
7ab9ffdd
L		 5321 }
5322 else if (i.tm.opcode_modifier.vexndd)
5323 {
5324 /* For instructions with VexNDD, there should be
5325 no memory operand and the register destination
5326 is encoded in VEX prefix. */
5327 gas_assert (i.mem_operands == 0
5328 && (op + 2) == i.operands);
5329 vex_reg = op + 1;
5330 }
5331 else
5332 gas_assert (op < i.operands);
99018f42 5333
7ab9ffdd
L		 5334 if (vex_reg != (unsigned int) ~0)
5335 {
5336 gas_assert (i.reg_operands == 2);
5337
5338 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5339 &regxmm)
7ab9ffdd
L		 5340 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5341 &regymm))
5342 abort ();
f88c9eb0 5343
7ab9ffdd
L		 5344 i.vex.register_specifier = i.op[vex_reg].regs;
5345 }
5346
5347 /* If there is an extension opcode to put here, the
5348 register number must be put into the regmem field. */
5349 if (i.tm.extension_opcode != None)
5350 {
5351 i.rm.regmem = i.op[op].regs->reg_num;
5352 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5353 i.rex |= REX_B;
5354 }
5355 else
5356 {
5357 i.rm.reg = i.op[op].regs->reg_num;
5358 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5359 i.rex |= REX_R;
5360 }
252b5132 5361
29b0f896
AM		 5362 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5363 must set it to 3 to indicate this is a register operand
5364 in the regmem field. */
5365 if (!i.mem_operands)
5366 i.rm.mode = 3;
5367 }
252b5132 5368
29b0f896 5369 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5370 if (i.tm.extension_opcode != None)
29b0f896
AM		 5371 i.rm.reg = i.tm.extension_opcode;
5372 }
5373 return default_seg;
5374}
252b5132 5375
29b0f896 5376static void
e3bb37b5 5377output_branch (void)
29b0f896
AM		 5378{
5379 char *p;
5380 int code16;
5381 int prefix;
5382 relax_substateT subtype;
5383 symbolS *sym;
5384 offsetT off;
5385
5386 code16 = 0;
5387 if (flag_code == CODE_16BIT)
5388 code16 = CODE16;
5389
5390 prefix = 0;
5391 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5392 {
29b0f896
AM		 5393 prefix = 1;
5394 i.prefixes -= 1;
5395 code16 ^= CODE16;
252b5132 5396 }
29b0f896
AM		 5397 /* Pentium4 branch hints. */
5398 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5399 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5400 {
29b0f896
AM		 5401 prefix++;
5402 i.prefixes--;
5403 }
5404 if (i.prefix[REX_PREFIX] != 0)
5405 {
5406 prefix++;
5407 i.prefixes--;
2f66722d
AM		 5408 }
5409
29b0f896
AM		 5410 if (i.prefixes != 0 && !intel_syntax)
5411 as_warn (_("skipping prefixes on this instruction"));
5412
5413 /* It's always a symbol; End frag & setup for relax.
5414 Make sure there is enough room in this frag for the largest
5415 instruction we may generate in md_convert_frag. This is 2
5416 bytes for the opcode and room for the prefix and largest
5417 displacement. */
5418 frag_grow (prefix + 2 + 4);
5419 /* Prefix and 1 opcode byte go in fr_fix. */
5420 p = frag_more (prefix + 1);
5421 if (i.prefix[DATA_PREFIX] != 0)
5422 *p++ = DATA_PREFIX_OPCODE;
5423 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5424 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5425 *p++ = i.prefix[SEG_PREFIX];
5426 if (i.prefix[REX_PREFIX] != 0)
5427 *p++ = i.prefix[REX_PREFIX];
5428 *p = i.tm.base_opcode;
5429
5430 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5431 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5432 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5433 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5434 else
5435 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5436 subtype |= code16;
3e73aa7c 5437
29b0f896
AM		 5438 sym = i.op[0].disps->X_add_symbol;
5439 off = i.op[0].disps->X_add_number;
3e73aa7c 5440
29b0f896
AM		 5441 if (i.op[0].disps->X_op != O_constant
5442 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5443 {
29b0f896
AM		 5444 /* Handle complex expressions. */
5445 sym = make_expr_symbol (i.op[0].disps);
5446 off = 0;
5447 }
3e73aa7c 5448
29b0f896
AM		 5449 /* 1 possible extra opcode + 4 byte displacement go in var part.
5450 Pass reloc in fr_var. */
5451 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5452}
3e73aa7c 5453
29b0f896 5454static void
e3bb37b5 5455output_jump (void)
29b0f896
AM		 5456{
5457 char *p;
5458 int size;
3e02c1cc 5459 fixS *fixP;
29b0f896 5460
40fb9820 5461 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5462 {
5463 /* This is a loop or jecxz type instruction. */
5464 size = 1;
5465 if (i.prefix[ADDR_PREFIX] != 0)
5466 {
5467 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5468 i.prefixes -= 1;
5469 }
5470 /* Pentium4 branch hints. */
5471 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5472 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5473 {
5474 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5475 i.prefixes--;
3e73aa7c
JH		 5476 }
5477 }
29b0f896
AM		 5478 else
5479 {
5480 int code16;
3e73aa7c 5481
29b0f896
AM		 5482 code16 = 0;
5483 if (flag_code == CODE_16BIT)
5484 code16 = CODE16;
3e73aa7c 5485
29b0f896
AM		 5486 if (i.prefix[DATA_PREFIX] != 0)
5487 {
5488 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5489 i.prefixes -= 1;
5490 code16 ^= CODE16;
5491 }
252b5132 5492
29b0f896
AM		 5493 size = 4;
5494 if (code16)
5495 size = 2;
5496 }
9fcc94b6 5497
29b0f896
AM		 5498 if (i.prefix[REX_PREFIX] != 0)
5499 {
5500 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5501 i.prefixes -= 1;
5502 }
252b5132 5503
29b0f896
AM		 5504 if (i.prefixes != 0 && !intel_syntax)
5505 as_warn (_("skipping prefixes on this instruction"));
e0890092 5506
29b0f896
AM		 5507 p = frag_more (1 + size);
5508 *p++ = i.tm.base_opcode;
e0890092 5509
3e02c1cc
AM		 5510 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5511 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5512
5513 /* All jumps handled here are signed, but don't use a signed limit
5514 check for 32 and 16 bit jumps as we want to allow wrap around at
5515 4G and 64k respectively. */
5516 if (size == 1)
5517 fixP->fx_signed = 1;
29b0f896 5518}
e0890092 5519
29b0f896 5520static void
e3bb37b5 5521output_interseg_jump (void)
29b0f896
AM		 5522{
5523 char *p;
5524 int size;
5525 int prefix;
5526 int code16;
252b5132 5527
29b0f896
AM		 5528 code16 = 0;
5529 if (flag_code == CODE_16BIT)
5530 code16 = CODE16;
a217f122 5531
29b0f896
AM		 5532 prefix = 0;
5533 if (i.prefix[DATA_PREFIX] != 0)
5534 {
5535 prefix = 1;
5536 i.prefixes -= 1;
5537 code16 ^= CODE16;
5538 }
5539 if (i.prefix[REX_PREFIX] != 0)
5540 {
5541 prefix++;
5542 i.prefixes -= 1;
5543 }
252b5132 5544
29b0f896
AM		 5545 size = 4;
5546 if (code16)
5547 size = 2;
252b5132 5548
29b0f896
AM		 5549 if (i.prefixes != 0 && !intel_syntax)
5550 as_warn (_("skipping prefixes on this instruction"));
252b5132 5551
29b0f896
AM		 5552 /* 1 opcode; 2 segment; offset */
5553 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5554
29b0f896
AM		 5555 if (i.prefix[DATA_PREFIX] != 0)
5556 *p++ = DATA_PREFIX_OPCODE;
252b5132 5557
29b0f896
AM		 5558 if (i.prefix[REX_PREFIX] != 0)
5559 *p++ = i.prefix[REX_PREFIX];
252b5132 5560
29b0f896
AM		 5561 *p++ = i.tm.base_opcode;
5562 if (i.op[1].imms->X_op == O_constant)
5563 {
5564 offsetT n = i.op[1].imms->X_add_number;
252b5132 5565
29b0f896
AM		 5566 if (size == 2
5567 && !fits_in_unsigned_word (n)
5568 && !fits_in_signed_word (n))
5569 {
5570 as_bad (_("16-bit jump out of range"));
5571 return;
5572 }
5573 md_number_to_chars (p, n, size);
5574 }
5575 else
5576 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5577 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5578 if (i.op[0].imms->X_op != O_constant)
5579 as_bad (_("can't handle non absolute segment in `%s'"),
5580 i.tm.name);
5581 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5582}
a217f122 5583
29b0f896 5584static void
e3bb37b5 5585output_insn (void)
29b0f896 5586{
2bbd9c25
JJ		 5587 fragS *insn_start_frag;
5588 offsetT insn_start_off;
5589
29b0f896
AM		 5590 /* Tie dwarf2 debug info to the address at the start of the insn.
5591 We can't do this after the insn has been output as the current
5592 frag may have been closed off. eg. by frag_var. */
5593 dwarf2_emit_insn (0);
5594
2bbd9c25
JJ		 5595 insn_start_frag = frag_now;
5596 insn_start_off = frag_now_fix ();
5597
29b0f896 5598 /* Output jumps. */
40fb9820 5599 if (i.tm.opcode_modifier.jump)
29b0f896 5600 output_branch ();
40fb9820
L		 5601 else if (i.tm.opcode_modifier.jumpbyte
5602 || i.tm.opcode_modifier.jumpdword)
29b0f896 5603 output_jump ();
40fb9820 5604 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5605 output_interseg_jump ();
5606 else
5607 {
5608 /* Output normal instructions here. */
5609 char *p;
5610 unsigned char *q;
47465058 5611 unsigned int j;
331d2d0d 5612 unsigned int prefix;
4dffcebc 5613
c0f3af97
L		 5614 /* Since the VEX prefix contains the implicit prefix, we don't
5615 need the explicit prefix. */
5616 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5617 {
c0f3af97 5618 switch (i.tm.opcode_length)
bc4bd9ab 5619 {
c0f3af97
L		 5620 case 3:
5621 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5622 {
c0f3af97
L		 5623 prefix = (i.tm.base_opcode >> 24) & 0xff;
5624 goto check_prefix;
5625 }
5626 break;
5627 case 2:
5628 if ((i.tm.base_opcode & 0xff0000) != 0)
5629 {
5630 prefix = (i.tm.base_opcode >> 16) & 0xff;
5631 if (i.tm.cpu_flags.bitfield.cpupadlock)
5632 {
4dffcebc 5633check_prefix:
c0f3af97
L		 5634 if (prefix != REPE_PREFIX_OPCODE
5635 || (i.prefix[LOCKREP_PREFIX]
5636 != REPE_PREFIX_OPCODE))
5637 add_prefix (prefix);
5638 }
5639 else
4dffcebc
L		 5640 add_prefix (prefix);
5641 }
c0f3af97
L		 5642 break;
5643 case 1:
5644 break;
5645 default:
5646 abort ();
bc4bd9ab 5647 }
c0f3af97
L		 5648
5649 /* The prefix bytes. */
5650 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5651 if (*q)
5652 FRAG_APPEND_1_CHAR (*q);
0f10071e 5653 }
252b5132 5654
c0f3af97
L		 5655 if (i.tm.opcode_modifier.vex)
5656 {
5657 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5658 if (*q)
5659 switch (j)
5660 {
5661 case REX_PREFIX:
5662 /* REX byte is encoded in VEX prefix. */
5663 break;
5664 case SEG_PREFIX:
5665 case ADDR_PREFIX:
5666 FRAG_APPEND_1_CHAR (*q);
5667 break;
5668 default:
5669 /* There should be no other prefixes for instructions
5670 with VEX prefix. */
5671 abort ();
5672 }
5673
5674 /* Now the VEX prefix. */
5675 p = frag_more (i.vex.length);
5676 for (j = 0; j < i.vex.length; j++)
5677 p[j] = i.vex.bytes[j];
5678 }
252b5132 5679
29b0f896 5680 /* Now the opcode; be careful about word order here! */
4dffcebc 5681 if (i.tm.opcode_length == 1)
29b0f896
AM		 5682 {
5683 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5684 }
5685 else
5686 {
4dffcebc 5687 switch (i.tm.opcode_length)
331d2d0d 5688 {
4dffcebc 5689 case 3:
331d2d0d
L		 5690 p = frag_more (3);
5691 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5692 break;
5693 case 2:
5694 p = frag_more (2);
5695 break;
5696 default:
5697 abort ();
5698 break;
331d2d0d 5699 }
0f10071e 5700
29b0f896
AM		 5701 /* Put out high byte first: can't use md_number_to_chars! */
5702 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5703 *p = i.tm.base_opcode & 0xff;
5704 }
3e73aa7c 5705
29b0f896 5706 /* Now the modrm byte and sib byte (if present). */
40fb9820 5707 if (i.tm.opcode_modifier.modrm)
29b0f896 5708 {
4a3523fa
L		 5709 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5710 | i.rm.reg << 3
5711 | i.rm.mode << 6));
29b0f896
AM		 5712 /* If i.rm.regmem == ESP (4)
5713 && i.rm.mode != (Register mode)
5714 && not 16 bit
5715 ==> need second modrm byte. */
5716 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5717 && i.rm.mode != 3
40fb9820 5718 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5719 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5720 | i.sib.index << 3
5721 | i.sib.scale << 6));
29b0f896 5722 }
3e73aa7c 5723
29b0f896 5724 if (i.disp_operands)
2bbd9c25 5725 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5726
29b0f896 5727 if (i.imm_operands)
2bbd9c25 5728 output_imm (insn_start_frag, insn_start_off);
29b0f896 5729 }
252b5132 5730
29b0f896
AM		 5731#ifdef DEBUG386
5732 if (flag_debug)
5733 {
7b81dfbb 5734 pi ("" /*line*/, &i);
29b0f896
AM		 5735 }
5736#endif /* DEBUG386 */
5737}
252b5132 5738
e205caa7
L		 5739/* Return the size of the displacement operand N. */
5740
5741static int
5742disp_size (unsigned int n)
5743{
5744 int size = 4;
40fb9820
L		 5745 if (i.types[n].bitfield.disp64)
5746 size = 8;
5747 else if (i.types[n].bitfield.disp8)
5748 size = 1;
5749 else if (i.types[n].bitfield.disp16)
5750 size = 2;
e205caa7
L		 5751 return size;
5752}
5753
5754/* Return the size of the immediate operand N. */
5755
5756static int
5757imm_size (unsigned int n)
5758{
5759 int size = 4;
40fb9820
L		 5760 if (i.types[n].bitfield.imm64)
5761 size = 8;
5762 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5763 size = 1;
5764 else if (i.types[n].bitfield.imm16)
5765 size = 2;
e205caa7
L		 5766 return size;
5767}
5768
29b0f896 5769static void
64e74474 5770output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5771{
5772 char *p;
5773 unsigned int n;
252b5132 5774
29b0f896
AM		 5775 for (n = 0; n < i.operands; n++)
5776 {
40fb9820 5777 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5778 {
5779 if (i.op[n].disps->X_op == O_constant)
5780 {
e205caa7 5781 int size = disp_size (n);
29b0f896 5782 offsetT val;
252b5132 5783
29b0f896
AM		 5784 val = offset_in_range (i.op[n].disps->X_add_number,
5785 size);
5786 p = frag_more (size);
5787 md_number_to_chars (p, val, size);
5788 }
5789 else
5790 {
f86103b7 5791 enum bfd_reloc_code_real reloc_type;
e205caa7 5792 int size = disp_size (n);
40fb9820 5793 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5794 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5795
e205caa7 5796 /* We can't have 8 bit displacement here. */
9c2799c2 5797 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5798
29b0f896
AM		 5799 /* The PC relative address is computed relative
5800 to the instruction boundary, so in case immediate
5801 fields follows, we need to adjust the value. */
5802 if (pcrel && i.imm_operands)
5803 {
29b0f896 5804 unsigned int n1;
e205caa7 5805 int sz = 0;
252b5132 5806
29b0f896 5807 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5808 if (operand_type_check (i.types[n1], imm))
252b5132 5809 {
e205caa7
L		 5810 /* Only one immediate is allowed for PC
5811 relative address. */
9c2799c2 5812 gas_assert (sz == 0);
e205caa7
L		 5813 sz = imm_size (n1);
5814 i.op[n].disps->X_add_number -= sz;
252b5132 5815 }
29b0f896 5816 /* We should find the immediate. */
9c2799c2 5817 gas_assert (sz != 0);
29b0f896 5818 }
520dc8e8 5819
29b0f896 5820 p = frag_more (size);
2bbd9c25 5821 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5822 if (GOT_symbol
2bbd9c25 5823 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5824 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5825 || reloc_type == BFD_RELOC_X86_64_32S
5826 || (reloc_type == BFD_RELOC_64
5827 && object_64bit))
d6ab8113
JB		 5828 && (i.op[n].disps->X_op == O_symbol
5829 || (i.op[n].disps->X_op == O_add
5830 && ((symbol_get_value_expression
5831 (i.op[n].disps->X_op_symbol)->X_op)
5832 == O_subtract))))
5833 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5834 {
5835 offsetT add;
5836
5837 if (insn_start_frag == frag_now)
5838 add = (p - frag_now->fr_literal) - insn_start_off;
5839 else
5840 {
5841 fragS *fr;
5842
5843 add = insn_start_frag->fr_fix - insn_start_off;
5844 for (fr = insn_start_frag->fr_next;
5845 fr && fr != frag_now; fr = fr->fr_next)
5846 add += fr->fr_fix;
5847 add += p - frag_now->fr_literal;
5848 }
5849
4fa24527 5850 if (!object_64bit)
7b81dfbb
AJ		 5851 {
5852 reloc_type = BFD_RELOC_386_GOTPC;
5853 i.op[n].imms->X_add_number += add;
5854 }
5855 else if (reloc_type == BFD_RELOC_64)
5856 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5857 else
7b81dfbb
AJ		 5858 /* Don't do the adjustment for x86-64, as there
5859 the pcrel addressing is relative to the _next_
5860 insn, and that is taken care of in other code. */
d6ab8113 5861 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5862 }
062cd5e7 5863 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5864 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5865 }
5866 }
5867 }
5868}
252b5132 5869
29b0f896 5870static void
64e74474 5871output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5872{
5873 char *p;
5874 unsigned int n;
252b5132 5875
29b0f896
AM		 5876 for (n = 0; n < i.operands; n++)
5877 {
40fb9820 5878 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5879 {
5880 if (i.op[n].imms->X_op == O_constant)
5881 {
e205caa7 5882 int size = imm_size (n);
29b0f896 5883 offsetT val;
b4cac588 5884
29b0f896
AM		 5885 val = offset_in_range (i.op[n].imms->X_add_number,
5886 size);
5887 p = frag_more (size);
5888 md_number_to_chars (p, val, size);
5889 }
5890 else
5891 {
5892 /* Not absolute_section.
5893 Need a 32-bit fixup (don't support 8bit
5894 non-absolute imms). Try to support other
5895 sizes ... */
f86103b7 5896 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5897 int size = imm_size (n);
5898 int sign;
29b0f896 5899
40fb9820 5900 if (i.types[n].bitfield.imm32s
a7d61044 5901 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5902 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5903 sign = 1;
e205caa7
L		 5904 else
5905 sign = 0;
520dc8e8 5906
29b0f896
AM		 5907 p = frag_more (size);
5908 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5909
2bbd9c25
JJ		 5910 /* This is tough to explain. We end up with this one if we
5911 * have operands that look like
5912 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5913 * obtain the absolute address of the GOT, and it is strongly
5914 * preferable from a performance point of view to avoid using
5915 * a runtime relocation for this. The actual sequence of
5916 * instructions often look something like:
5917 *
5918 * call .L66
5919 * .L66:
5920 * popl %ebx
5921 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5922 *
5923 * The call and pop essentially return the absolute address
5924 * of the label .L66 and store it in %ebx. The linker itself
5925 * will ultimately change the first operand of the addl so
5926 * that %ebx points to the GOT, but to keep things simple, the
5927 * .o file must have this operand set so that it generates not
5928 * the absolute address of .L66, but the absolute address of
5929 * itself. This allows the linker itself simply treat a GOTPC
5930 * relocation as asking for a pcrel offset to the GOT to be
5931 * added in, and the addend of the relocation is stored in the
5932 * operand field for the instruction itself.
5933 *
5934 * Our job here is to fix the operand so that it would add
5935 * the correct offset so that %ebx would point to itself. The
5936 * thing that is tricky is that .-.L66 will point to the
5937 * beginning of the instruction, so we need to further modify
5938 * the operand so that it will point to itself. There are
5939 * other cases where you have something like:
5940 *
5941 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5942 *
5943 * and here no correction would be required. Internally in
5944 * the assembler we treat operands of this form as not being
5945 * pcrel since the '.' is explicitly mentioned, and I wonder
5946 * whether it would simplify matters to do it this way. Who
5947 * knows. In earlier versions of the PIC patches, the
5948 * pcrel_adjust field was used to store the correction, but
5949 * since the expression is not pcrel, I felt it would be
5950 * confusing to do it this way. */
5951
d6ab8113 5952 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5953 || reloc_type == BFD_RELOC_X86_64_32S
5954 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5955 && GOT_symbol
5956 && GOT_symbol == i.op[n].imms->X_add_symbol
5957 && (i.op[n].imms->X_op == O_symbol
5958 || (i.op[n].imms->X_op == O_add
5959 && ((symbol_get_value_expression
5960 (i.op[n].imms->X_op_symbol)->X_op)
5961 == O_subtract))))
5962 {
2bbd9c25
JJ		 5963 offsetT add;
5964
5965 if (insn_start_frag == frag_now)
5966 add = (p - frag_now->fr_literal) - insn_start_off;
5967 else
5968 {
5969 fragS *fr;
5970
5971 add = insn_start_frag->fr_fix - insn_start_off;
5972 for (fr = insn_start_frag->fr_next;
5973 fr && fr != frag_now; fr = fr->fr_next)
5974 add += fr->fr_fix;
5975 add += p - frag_now->fr_literal;
5976 }
5977
4fa24527 5978 if (!object_64bit)
d6ab8113 5979 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5980 else if (size == 4)
d6ab8113 5981 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5982 else if (size == 8)
5983 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5984 i.op[n].imms->X_add_number += add;
29b0f896 5985 }
29b0f896
AM		 5986 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5987 i.op[n].imms, 0, reloc_type);
5988 }
5989 }
5990 }
252b5132
RH		 5991}
5992\f
d182319b
JB		 5993/* x86_cons_fix_new is called via the expression parsing code when a
5994 reloc is needed. We use this hook to get the correct .got reloc. */
5995static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5996static int cons_sign = -1;
5997
5998void
e3bb37b5 5999x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6000 expressionS *exp)
d182319b
JB		 6001{
6002 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6003
6004 got_reloc = NO_RELOC;
6005
6006#ifdef TE_PE
6007 if (exp->X_op == O_secrel)
6008 {
6009 exp->X_op = O_symbol;
6010 r = BFD_RELOC_32_SECREL;
6011 }
6012#endif
6013
6014 fix_new_exp (frag, off, len, exp, 0, r);
6015}
6016
718ddfc0
JB		 6017#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6018# define lex_got(reloc, adjust, types) NULL
6019#else
f3c180ae
AM		 6020/* Parse operands of the form
6021 <symbol>@GOTOFF+<nnn>
6022 and similar .plt or .got references.
6023
6024 If we find one, set up the correct relocation in RELOC and copy the
6025 input string, minus the `@GOTOFF' into a malloc'd buffer for
6026 parsing by the calling routine. Return this buffer, and if ADJUST
6027 is non-null set it to the length of the string we removed from the
6028 input line. Otherwise return NULL. */
6029static char *
3956db08 6030lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6031 int *adjust,
40fb9820 6032 i386_operand_type *types)
f3c180ae 6033{
7b81dfbb
AJ		 6034 /* Some of the relocations depend on the size of what field is to
6035 be relocated. But in our callers i386_immediate and i386_displacement
6036 we don't yet know the operand size (this will be set by insn
6037 matching). Hence we record the word32 relocation here,
6038 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6039 static const struct {
6040 const char *str;
4fa24527 6041 const enum bfd_reloc_code_real rel[2];
40fb9820 6042 const i386_operand_type types64;
f3c180ae 6043 } gotrel[] = {
1e9cc1c2 6044 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6045 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6046 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6047 { "PLT", { BFD_RELOC_386_PLT32,
6048 BFD_RELOC_X86_64_PLT32 },
40fb9820 6049 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6050 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6051 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6052 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6053 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6054 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6055 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6056 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6057 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6058 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6059 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6060 BFD_RELOC_X86_64_TLSGD },
40fb9820 6061 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6062 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6063 _dummy_first_bfd_reloc_code_real },
40fb9820 6064 OPERAND_TYPE_NONE },
1e9cc1c2 6065 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6066 BFD_RELOC_X86_64_TLSLD },
40fb9820 6067 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6068 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6069 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6070 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6071 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6072 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6073 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6074 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6075 _dummy_first_bfd_reloc_code_real },
40fb9820 6076 OPERAND_TYPE_NONE },
4eed87de
AM		 6077 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6078 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6079
40fb9820 6080 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6081 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6082 _dummy_first_bfd_reloc_code_real },
40fb9820 6083 OPERAND_TYPE_NONE },
4eed87de 6084 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6085 _dummy_first_bfd_reloc_code_real },
40fb9820 6086 OPERAND_TYPE_NONE },
4eed87de
AM		 6087 { "GOT", { BFD_RELOC_386_GOT32,
6088 BFD_RELOC_X86_64_GOT32 },
40fb9820 6089 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6090 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6091 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6092 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6093 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6094 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6095 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6096 };
6097 char *cp;
6098 unsigned int j;
6099
718ddfc0
JB		 6100 if (!IS_ELF)
6101 return NULL;
6102
f3c180ae 6103 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6104 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6105 return NULL;
6106
47465058 6107 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6108 {
6109 int len;
6110
6111 len = strlen (gotrel[j].str);
28f81592 6112 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6113 {
4fa24527 6114 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6115 {
28f81592
AM		 6116 int first, second;
6117 char *tmpbuf, *past_reloc;
f3c180ae 6118
4fa24527 6119 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6120 if (adjust)
6121 *adjust = len;
f3c180ae 6122
3956db08
JB		 6123 if (types)
6124 {
6125 if (flag_code != CODE_64BIT)
40fb9820
L		 6126 {
6127 types->bitfield.imm32 = 1;
6128 types->bitfield.disp32 = 1;
6129 }
3956db08
JB		 6130 else
6131 *types = gotrel[j].types64;
6132 }
6133
f3c180ae
AM		 6134 if (GOT_symbol == NULL)
6135 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6136
28f81592 6137 /* The length of the first part of our input line. */
f3c180ae 6138 first = cp - input_line_pointer;
28f81592
AM		 6139
6140 /* The second part goes from after the reloc token until
67c11a9b 6141 (and including) an end_of_line char or comma. */
28f81592 6142 past_reloc = cp + 1 + len;
67c11a9b
AM		 6143 cp = past_reloc;
6144 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6145 ++cp;
6146 second = cp + 1 - past_reloc;
28f81592
AM		 6147
6148 /* Allocate and copy string. The trailing NUL shouldn't
6149 be necessary, but be safe. */
1e9cc1c2 6150 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6151 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6152 if (second != 0 && *past_reloc != ' ')
6153 /* Replace the relocation token with ' ', so that
6154 errors like foo@GOTOFF1 will be detected. */
6155 tmpbuf[first++] = ' ';
6156 memcpy (tmpbuf + first, past_reloc, second);
6157 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6158 return tmpbuf;
6159 }
6160
4fa24527
JB		 6161 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6162 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6163 return NULL;
6164 }
6165 }
6166
6167 /* Might be a symbol version string. Don't as_bad here. */
6168 return NULL;
6169}
6170
f3c180ae 6171void
e3bb37b5 6172x86_cons (expressionS *exp, int size)
f3c180ae 6173{
ee86248c
JB		 6174 intel_syntax = -intel_syntax;
6175
4fa24527 6176 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6177 {
6178 /* Handle @GOTOFF and the like in an expression. */
6179 char *save;
6180 char *gotfree_input_line;
6181 int adjust;
6182
6183 save = input_line_pointer;
3956db08 6184 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6185 if (gotfree_input_line)
6186 input_line_pointer = gotfree_input_line;
6187
6188 expression (exp);
6189
6190 if (gotfree_input_line)
6191 {
6192 /* expression () has merrily parsed up to the end of line,
6193 or a comma - in the wrong buffer. Transfer how far
6194 input_line_pointer has moved to the right buffer. */
6195 input_line_pointer = (save
6196 + (input_line_pointer - gotfree_input_line)
6197 + adjust);
6198 free (gotfree_input_line);
3992d3b7
AM		 6199 if (exp->X_op == O_constant
6200 || exp->X_op == O_absent
6201 || exp->X_op == O_illegal
6202 || exp->X_op == O_register
6203 || exp->X_op == O_big)
6204 {
6205 char c = *input_line_pointer;
6206 *input_line_pointer = 0;
6207 as_bad (_("missing or invalid expression `%s'"), save);
6208 *input_line_pointer = c;
6209 }
f3c180ae
AM		 6210 }
6211 }
6212 else
6213 expression (exp);
ee86248c
JB		 6214
6215 intel_syntax = -intel_syntax;
6216
6217 if (intel_syntax)
6218 i386_intel_simplify (exp);
f3c180ae
AM		 6219}
6220#endif
6221
9f32dd5b
L		 6222static void
6223signed_cons (int size)
6482c264 6224{
d182319b
JB		 6225 if (flag_code == CODE_64BIT)
6226 cons_sign = 1;
6227 cons (size);
6228 cons_sign = -1;
6482c264
NC		 6229}
6230
d182319b 6231#ifdef TE_PE
6482c264
NC		 6232static void
6233pe_directive_secrel (dummy)
6234 int dummy ATTRIBUTE_UNUSED;
6235{
6236 expressionS exp;
6237
6238 do
6239 {
6240 expression (&exp);
6241 if (exp.X_op == O_symbol)
6242 exp.X_op = O_secrel;
6243
6244 emit_expr (&exp, 4);
6245 }
6246 while (*input_line_pointer++ == ',');
6247
6248 input_line_pointer--;
6249 demand_empty_rest_of_line ();
6250}
6482c264
NC		 6251#endif
6252
252b5132 6253static int
70e41ade 6254i386_immediate (char *imm_start)
252b5132
RH		 6255{
6256 char *save_input_line_pointer;
f3c180ae 6257 char *gotfree_input_line;
252b5132 6258 segT exp_seg = 0;
47926f60 6259 expressionS *exp;
40fb9820
L		 6260 i386_operand_type types;
6261
0dfbf9d7 6262 operand_type_set (&types, ~0);
252b5132
RH		 6263
6264 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6265 {
31b2323c
L		 6266 as_bad (_("at most %d immediate operands are allowed"),
6267 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6268 return 0;
6269 }
6270
6271 exp = &im_expressions[i.imm_operands++];
520dc8e8 6272 i.op[this_operand].imms = exp;
252b5132
RH		 6273
6274 if (is_space_char (*imm_start))
6275 ++imm_start;
6276
6277 save_input_line_pointer = input_line_pointer;
6278 input_line_pointer = imm_start;
6279
3956db08 6280 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6281 if (gotfree_input_line)
6282 input_line_pointer = gotfree_input_line;
252b5132
RH		 6283
6284 exp_seg = expression (exp);
6285
83183c0c 6286 SKIP_WHITESPACE ();
252b5132 6287 if (*input_line_pointer)
f3c180ae 6288 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6289
6290 input_line_pointer = save_input_line_pointer;
f3c180ae 6291 if (gotfree_input_line)
ee86248c
JB		 6292 {
6293 free (gotfree_input_line);
6294
6295 if (exp->X_op == O_constant || exp->X_op == O_register)
6296 exp->X_op = O_illegal;
6297 }
6298
6299 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6300}
252b5132 6301
ee86248c
JB		 6302static int
6303i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6304 i386_operand_type types, const char *imm_start)
6305{
6306 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6307 {
313c53d1
L		 6308 if (imm_start)
6309 as_bad (_("missing or invalid immediate expression `%s'"),
6310 imm_start);
3992d3b7 6311 return 0;
252b5132 6312 }
3e73aa7c 6313 else if (exp->X_op == O_constant)
252b5132 6314 {
47926f60 6315 /* Size it properly later. */
40fb9820 6316 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6317 /* If BFD64, sign extend val. */
4eed87de
AM		 6318 if (!use_rela_relocations
6319 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6320 exp->X_add_number
6321 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6322 }
4c63da97 6323#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6324 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6325 && exp_seg != absolute_section
47926f60 6326 && exp_seg != text_section
24eab124
AM		 6327 && exp_seg != data_section
6328 && exp_seg != bss_section
6329 && exp_seg != undefined_section
f86103b7 6330 && !bfd_is_com_section (exp_seg))
252b5132 6331 {
d0b47220 6332 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6333 return 0;
6334 }
6335#endif
bb8f5920
L		 6336 else if (!intel_syntax && exp->X_op == O_register)
6337 {
313c53d1
L		 6338 if (imm_start)
6339 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6340 return 0;
6341 }
252b5132
RH		 6342 else
6343 {
6344 /* This is an address. The size of the address will be
24eab124 6345 determined later, depending on destination register,
3e73aa7c 6346 suffix, or the default for the section. */
40fb9820
L		 6347 i.types[this_operand].bitfield.imm8 = 1;
6348 i.types[this_operand].bitfield.imm16 = 1;
6349 i.types[this_operand].bitfield.imm32 = 1;
6350 i.types[this_operand].bitfield.imm32s = 1;
6351 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6352 i.types[this_operand] = operand_type_and (i.types[this_operand],
6353 types);
252b5132
RH		 6354 }
6355
6356 return 1;
6357}
6358
551c1ca1 6359static char *
e3bb37b5 6360i386_scale (char *scale)
252b5132 6361{
551c1ca1
AM		 6362 offsetT val;
6363 char *save = input_line_pointer;
252b5132 6364
551c1ca1
AM		 6365 input_line_pointer = scale;
6366 val = get_absolute_expression ();
6367
6368 switch (val)
252b5132 6369 {
551c1ca1 6370 case 1:
252b5132
RH		 6371 i.log2_scale_factor = 0;
6372 break;
551c1ca1 6373 case 2:
252b5132
RH		 6374 i.log2_scale_factor = 1;
6375 break;
551c1ca1 6376 case 4:
252b5132
RH		 6377 i.log2_scale_factor = 2;
6378 break;
551c1ca1 6379 case 8:
252b5132
RH		 6380 i.log2_scale_factor = 3;
6381 break;
6382 default:
a724f0f4
JB		 6383 {
6384 char sep = *input_line_pointer;
6385
6386 *input_line_pointer = '\0';
6387 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6388 scale);
6389 *input_line_pointer = sep;
6390 input_line_pointer = save;
6391 return NULL;
6392 }
252b5132 6393 }
29b0f896 6394 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6395 {
6396 as_warn (_("scale factor of %d without an index register"),
24eab124 6397 1 << i.log2_scale_factor);
252b5132 6398 i.log2_scale_factor = 0;
252b5132 6399 }
551c1ca1
AM		 6400 scale = input_line_pointer;
6401 input_line_pointer = save;
6402 return scale;
252b5132
RH		 6403}
6404
252b5132 6405static int
e3bb37b5 6406i386_displacement (char *disp_start, char *disp_end)
252b5132 6407{
29b0f896 6408 expressionS *exp;
252b5132
RH		 6409 segT exp_seg = 0;
6410 char *save_input_line_pointer;
f3c180ae 6411 char *gotfree_input_line;
40fb9820
L		 6412 int override;
6413 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6414 int ret;
252b5132 6415
31b2323c
L		 6416 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6417 {
6418 as_bad (_("at most %d displacement operands are allowed"),
6419 MAX_MEMORY_OPERANDS);
6420 return 0;
6421 }
6422
0dfbf9d7 6423 operand_type_set (&bigdisp, 0);
40fb9820
L		 6424 if ((i.types[this_operand].bitfield.jumpabsolute)
6425 || (!current_templates->start->opcode_modifier.jump
6426 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6427 {
40fb9820 6428 bigdisp.bitfield.disp32 = 1;
e05278af 6429 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6430 if (flag_code == CODE_64BIT)
6431 {
6432 if (!override)
6433 {
6434 bigdisp.bitfield.disp32s = 1;
6435 bigdisp.bitfield.disp64 = 1;
6436 }
6437 }
6438 else if ((flag_code == CODE_16BIT) ^ override)
6439 {
6440 bigdisp.bitfield.disp32 = 0;
6441 bigdisp.bitfield.disp16 = 1;
6442 }
e05278af
JB		 6443 }
6444 else
6445 {
6446 /* For PC-relative branches, the width of the displacement
6447 is dependent upon data size, not address size. */
e05278af 6448 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6449 if (flag_code == CODE_64BIT)
6450 {
6451 if (override || i.suffix == WORD_MNEM_SUFFIX)
6452 bigdisp.bitfield.disp16 = 1;
6453 else
6454 {
6455 bigdisp.bitfield.disp32 = 1;
6456 bigdisp.bitfield.disp32s = 1;
6457 }
6458 }
6459 else
e05278af
JB		 6460 {
6461 if (!override)
6462 override = (i.suffix == (flag_code != CODE_16BIT
6463 ? WORD_MNEM_SUFFIX
6464 : LONG_MNEM_SUFFIX));
40fb9820
L		 6465 bigdisp.bitfield.disp32 = 1;
6466 if ((flag_code == CODE_16BIT) ^ override)
6467 {
6468 bigdisp.bitfield.disp32 = 0;
6469 bigdisp.bitfield.disp16 = 1;
6470 }
e05278af 6471 }
e05278af 6472 }
c6fb90c8
L		 6473 i.types[this_operand] = operand_type_or (i.types[this_operand],
6474 bigdisp);
252b5132
RH		 6475
6476 exp = &disp_expressions[i.disp_operands];
520dc8e8 6477 i.op[this_operand].disps = exp;
252b5132
RH		 6478 i.disp_operands++;
6479 save_input_line_pointer = input_line_pointer;
6480 input_line_pointer = disp_start;
6481 END_STRING_AND_SAVE (disp_end);
6482
6483#ifndef GCC_ASM_O_HACK
6484#define GCC_ASM_O_HACK 0
6485#endif
6486#if GCC_ASM_O_HACK
6487 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6488 if (i.types[this_operand].bitfield.baseIndex
24eab124 6489 && displacement_string_end[-1] == '+')
252b5132
RH		 6490 {
6491 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6492 constraint within gcc asm statements.
6493 For instance:
6494
6495 #define _set_tssldt_desc(n,addr,limit,type) \
6496 __asm__ __volatile__ ( \
6497 "movw %w2,%0\n\t" \
6498 "movw %w1,2+%0\n\t" \
6499 "rorl $16,%1\n\t" \
6500 "movb %b1,4+%0\n\t" \
6501 "movb %4,5+%0\n\t" \
6502 "movb $0,6+%0\n\t" \
6503 "movb %h1,7+%0\n\t" \
6504 "rorl $16,%1" \
6505 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6506
6507 This works great except that the output assembler ends
6508 up looking a bit weird if it turns out that there is
6509 no offset. You end up producing code that looks like:
6510
6511 #APP
6512 movw $235,(%eax)
6513 movw %dx,2+(%eax)
6514 rorl $16,%edx
6515 movb %dl,4+(%eax)
6516 movb $137,5+(%eax)
6517 movb $0,6+(%eax)
6518 movb %dh,7+(%eax)
6519 rorl $16,%edx
6520 #NO_APP
6521
47926f60 6522 So here we provide the missing zero. */
24eab124
AM		 6523
6524 *displacement_string_end = '0';
252b5132
RH		 6525 }
6526#endif
3956db08 6527 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6528 if (gotfree_input_line)
6529 input_line_pointer = gotfree_input_line;
252b5132 6530
24eab124 6531 exp_seg = expression (exp);
252b5132 6532
636c26b0
AM		 6533 SKIP_WHITESPACE ();
6534 if (*input_line_pointer)
6535 as_bad (_("junk `%s' after expression"), input_line_pointer);
6536#if GCC_ASM_O_HACK
6537 RESTORE_END_STRING (disp_end + 1);
6538#endif
636c26b0 6539 input_line_pointer = save_input_line_pointer;
636c26b0 6540 if (gotfree_input_line)
ee86248c
JB		 6541 {
6542 free (gotfree_input_line);
6543
6544 if (exp->X_op == O_constant || exp->X_op == O_register)
6545 exp->X_op = O_illegal;
6546 }
6547
6548 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6549
6550 RESTORE_END_STRING (disp_end);
6551
6552 return ret;
6553}
6554
6555static int
6556i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6557 i386_operand_type types, const char *disp_start)
6558{
6559 i386_operand_type bigdisp;
6560 int ret = 1;
636c26b0 6561
24eab124
AM		 6562 /* We do this to make sure that the section symbol is in
6563 the symbol table. We will ultimately change the relocation
47926f60 6564 to be relative to the beginning of the section. */
1ae12ab7 6565 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6566 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6567 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6568 {
636c26b0 6569 if (exp->X_op != O_symbol)
3992d3b7 6570 goto inv_disp;
636c26b0 6571
e5cb08ac 6572 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6573 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6574 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6575 exp->X_op = O_subtract;
6576 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6577 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6578 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6579 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6580 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6581 else
29b0f896 6582 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6583 }
252b5132 6584
3992d3b7
AM		 6585 else if (exp->X_op == O_absent
6586 || exp->X_op == O_illegal
ee86248c 6587 || exp->X_op == O_big)
2daf4fd8 6588 {
3992d3b7
AM		 6589 inv_disp:
6590 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6591 disp_start);
3992d3b7 6592 ret = 0;
2daf4fd8
AM		 6593 }
6594
0e1147d9
L		 6595 else if (flag_code == CODE_64BIT
6596 && !i.prefix[ADDR_PREFIX]
6597 && exp->X_op == O_constant)
6598 {
6599 /* Since displacement is signed extended to 64bit, don't allow
6600 disp32 and turn off disp32s if they are out of range. */
6601 i.types[this_operand].bitfield.disp32 = 0;
6602 if (!fits_in_signed_long (exp->X_add_number))
6603 {
6604 i.types[this_operand].bitfield.disp32s = 0;
6605 if (i.types[this_operand].bitfield.baseindex)
6606 {
6607 as_bad (_("0x%lx out range of signed 32bit displacement"),
6608 (long) exp->X_add_number);
6609 ret = 0;
6610 }
6611 }
6612 }
6613
4c63da97 6614#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6615 else if (exp->X_op != O_constant
6616 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6617 && exp_seg != absolute_section
6618 && exp_seg != text_section
6619 && exp_seg != data_section
6620 && exp_seg != bss_section
6621 && exp_seg != undefined_section
6622 && !bfd_is_com_section (exp_seg))
24eab124 6623 {
d0b47220 6624 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6625 ret = 0;
24eab124 6626 }
252b5132 6627#endif
3956db08 6628
40fb9820
L		 6629 /* Check if this is a displacement only operand. */
6630 bigdisp = i.types[this_operand];
6631 bigdisp.bitfield.disp8 = 0;
6632 bigdisp.bitfield.disp16 = 0;
6633 bigdisp.bitfield.disp32 = 0;
6634 bigdisp.bitfield.disp32s = 0;
6635 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6636 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6637 i.types[this_operand] = operand_type_and (i.types[this_operand],
6638 types);
3956db08 6639
3992d3b7 6640 return ret;
252b5132
RH		 6641}
6642
eecb386c 6643/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6644 Return 1 on success, 0 on a failure. */
6645
252b5132 6646static int
e3bb37b5 6647i386_index_check (const char *operand_string)
252b5132 6648{
3e73aa7c 6649 int ok;
fc0763e6 6650 const char *kind = "base/index";
24eab124 6651#if INFER_ADDR_PREFIX
eecb386c
AM		 6652 int fudged = 0;
6653
24eab124
AM		 6654 tryprefix:
6655#endif
3e73aa7c 6656 ok = 1;
fc0763e6
JB		 6657 if (current_templates->start->opcode_modifier.isstring
6658 && !current_templates->start->opcode_modifier.immext
6659 && (current_templates->end[-1].opcode_modifier.isstring
6660 || i.mem_operands))
6661 {
6662 /* Memory operands of string insns are special in that they only allow
6663 a single register (rDI, rSI, or rBX) as their memory address. */
6664 unsigned int expected;
6665
6666 kind = "string address";
6667
6668 if (current_templates->start->opcode_modifier.w)
6669 {
6670 i386_operand_type type = current_templates->end[-1].operand_types[0];
6671
6672 if (!type.bitfield.baseindex
6673 || ((!i.mem_operands != !intel_syntax)
6674 && current_templates->end[-1].operand_types[1]
6675 .bitfield.baseindex))
6676 type = current_templates->end[-1].operand_types[1];
6677 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6678 }
6679 else
6680 expected = 3 /* rBX */;
6681
6682 if (!i.base_reg || i.index_reg
6683 || operand_type_check (i.types[this_operand], disp))
6684 ok = -1;
6685 else if (!(flag_code == CODE_64BIT
6686 ? i.prefix[ADDR_PREFIX]
6687 ? i.base_reg->reg_type.bitfield.reg32
6688 : i.base_reg->reg_type.bitfield.reg64
6689 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6690 ? i.base_reg->reg_type.bitfield.reg32
6691 : i.base_reg->reg_type.bitfield.reg16))
6692 ok = 0;
6693 else if (i.base_reg->reg_num != expected)
6694 ok = -1;
6695
6696 if (ok < 0)
6697 {
6698 unsigned int j;
6699
6700 for (j = 0; j < i386_regtab_size; ++j)
6701 if ((flag_code == CODE_64BIT
6702 ? i.prefix[ADDR_PREFIX]
6703 ? i386_regtab[j].reg_type.bitfield.reg32
6704 : i386_regtab[j].reg_type.bitfield.reg64
6705 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6706 ? i386_regtab[j].reg_type.bitfield.reg32
6707 : i386_regtab[j].reg_type.bitfield.reg16)
6708 && i386_regtab[j].reg_num == expected)
6709 break;
9c2799c2 6710 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6711 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6712 operand_string,
6713 intel_syntax ? '[' : '(',
6714 register_prefix,
6715 i386_regtab[j].reg_name,
6716 intel_syntax ? ']' : ')');
6717 ok = 1;
6718 }
6719 }
6720 else if (flag_code == CODE_64BIT)
64e74474 6721 {
64e74474 6722 if ((i.base_reg
40fb9820
L		 6723 && ((i.prefix[ADDR_PREFIX] == 0
6724 && !i.base_reg->reg_type.bitfield.reg64)
6725 || (i.prefix[ADDR_PREFIX]
6726 && !i.base_reg->reg_type.bitfield.reg32))
6727 && (i.index_reg
9a04903e
JB		 6728 || i.base_reg->reg_num !=
6729 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6730 || (i.index_reg
40fb9820
L		 6731 && (!i.index_reg->reg_type.bitfield.baseindex
6732 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6733 && i.index_reg->reg_num != RegRiz
6734 && !i.index_reg->reg_type.bitfield.reg64
6735 )
40fb9820 6736 || (i.prefix[ADDR_PREFIX]
db51cc60 6737 && i.index_reg->reg_num != RegEiz
40fb9820 6738 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6739 ok = 0;
3e73aa7c
JH		 6740 }
6741 else
6742 {
6743 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6744 {
6745 /* 16bit checks. */
6746 if ((i.base_reg
40fb9820
L		 6747 && (!i.base_reg->reg_type.bitfield.reg16
6748 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6749 || (i.index_reg
40fb9820
L		 6750 && (!i.index_reg->reg_type.bitfield.reg16
6751 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6752 || !(i.base_reg
6753 && i.base_reg->reg_num < 6
6754 && i.index_reg->reg_num >= 6
6755 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6756 ok = 0;
6757 }
6758 else
e5cb08ac 6759 {
3e73aa7c
JH		 6760 /* 32bit checks. */
6761 if ((i.base_reg
40fb9820 6762 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6763 || (i.index_reg
db51cc60
L		 6764 && ((!i.index_reg->reg_type.bitfield.reg32
6765 && i.index_reg->reg_num != RegEiz)
40fb9820 6766 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6767 ok = 0;
3e73aa7c
JH		 6768 }
6769 }
6770 if (!ok)
24eab124
AM		 6771 {
6772#if INFER_ADDR_PREFIX
fc0763e6 6773 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6774 {
6775 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6776 i.prefixes += 1;
b23bac36
AM		 6777 /* Change the size of any displacement too. At most one of
6778 Disp16 or Disp32 is set.
6779 FIXME. There doesn't seem to be any real need for separate
6780 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6781 Removing them would probably clean up the code quite a lot. */
4eed87de 6782 if (flag_code != CODE_64BIT
40fb9820
L		 6783 && (i.types[this_operand].bitfield.disp16
6784 || i.types[this_operand].bitfield.disp32))
6785 i.types[this_operand]
c6fb90c8 6786 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6787 fudged = 1;
24eab124
AM		 6788 goto tryprefix;
6789 }
eecb386c 6790 if (fudged)
fc0763e6
JB		 6791 as_bad (_("`%s' is not a valid %s expression"),
6792 operand_string,
6793 kind);
eecb386c 6794 else
c388dee8 6795#endif
fc0763e6 6796 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6797 operand_string,
fc0763e6
JB		 6798 flag_code_names[i.prefix[ADDR_PREFIX]
6799 ? flag_code == CODE_32BIT
6800 ? CODE_16BIT
6801 : CODE_32BIT
6802 : flag_code],
6803 kind);
24eab124 6804 }
20f0a1fc 6805 return ok;
24eab124 6806}
252b5132 6807
fc0763e6 6808/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6809 on error. */
252b5132 6810
252b5132 6811static int
a7619375 6812i386_att_operand (char *operand_string)
252b5132 6813{
af6bdddf
AM		 6814 const reg_entry *r;
6815 char *end_op;
24eab124 6816 char *op_string = operand_string;
252b5132 6817
24eab124 6818 if (is_space_char (*op_string))
252b5132
RH		 6819 ++op_string;
6820
24eab124 6821 /* We check for an absolute prefix (differentiating,
47926f60 6822 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6823 if (*op_string == ABSOLUTE_PREFIX)
6824 {
6825 ++op_string;
6826 if (is_space_char (*op_string))
6827 ++op_string;
40fb9820 6828 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6829 }
252b5132 6830
47926f60 6831 /* Check if operand is a register. */
4d1bb795 6832 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6833 {
40fb9820
L		 6834 i386_operand_type temp;
6835
24eab124
AM		 6836 /* Check for a segment override by searching for ':' after a
6837 segment register. */
6838 op_string = end_op;
6839 if (is_space_char (*op_string))
6840 ++op_string;
40fb9820
L		 6841 if (*op_string == ':'
6842 && (r->reg_type.bitfield.sreg2
6843 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6844 {
6845 switch (r->reg_num)
6846 {
6847 case 0:
6848 i.seg[i.mem_operands] = &es;
6849 break;
6850 case 1:
6851 i.seg[i.mem_operands] = &cs;
6852 break;
6853 case 2:
6854 i.seg[i.mem_operands] = &ss;
6855 break;
6856 case 3:
6857 i.seg[i.mem_operands] = &ds;
6858 break;
6859 case 4:
6860 i.seg[i.mem_operands] = &fs;
6861 break;
6862 case 5:
6863 i.seg[i.mem_operands] = &gs;
6864 break;
6865 }
252b5132 6866
24eab124 6867 /* Skip the ':' and whitespace. */
252b5132
RH		 6868 ++op_string;
6869 if (is_space_char (*op_string))
24eab124 6870 ++op_string;
252b5132 6871
24eab124
AM		 6872 if (!is_digit_char (*op_string)
6873 && !is_identifier_char (*op_string)
6874 && *op_string != '('
6875 && *op_string != ABSOLUTE_PREFIX)
6876 {
6877 as_bad (_("bad memory operand `%s'"), op_string);
6878 return 0;
6879 }
47926f60 6880 /* Handle case of %es:*foo. */
24eab124
AM		 6881 if (*op_string == ABSOLUTE_PREFIX)
6882 {
6883 ++op_string;
6884 if (is_space_char (*op_string))
6885 ++op_string;
40fb9820 6886 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6887 }
6888 goto do_memory_reference;
6889 }
6890 if (*op_string)
6891 {
d0b47220 6892 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6893 return 0;
6894 }
40fb9820
L		 6895 temp = r->reg_type;
6896 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6897 i.types[this_operand] = operand_type_or (i.types[this_operand],
6898 temp);
7d5e4556 6899 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6900 i.op[this_operand].regs = r;
24eab124
AM		 6901 i.reg_operands++;
6902 }
af6bdddf
AM		 6903 else if (*op_string == REGISTER_PREFIX)
6904 {
6905 as_bad (_("bad register name `%s'"), op_string);
6906 return 0;
6907 }
24eab124 6908 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6909 {
24eab124 6910 ++op_string;
40fb9820 6911 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6912 {
d0b47220 6913 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6914 return 0;
6915 }
6916 if (!i386_immediate (op_string))
6917 return 0;
6918 }
6919 else if (is_digit_char (*op_string)
6920 || is_identifier_char (*op_string)
e5cb08ac 6921 || *op_string == '(')
24eab124 6922 {
47926f60 6923 /* This is a memory reference of some sort. */
af6bdddf 6924 char *base_string;
252b5132 6925
47926f60 6926 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6927 char *displacement_string_start;
6928 char *displacement_string_end;
252b5132 6929
24eab124 6930 do_memory_reference:
24eab124 6931 if ((i.mem_operands == 1
40fb9820 6932 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6933 || i.mem_operands == 2)
6934 {
6935 as_bad (_("too many memory references for `%s'"),
6936 current_templates->start->name);
6937 return 0;
6938 }
252b5132 6939
24eab124
AM		 6940 /* Check for base index form. We detect the base index form by
6941 looking for an ')' at the end of the operand, searching
6942 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6943 after the '('. */
af6bdddf 6944 base_string = op_string + strlen (op_string);
c3332e24 6945
af6bdddf
AM		 6946 --base_string;
6947 if (is_space_char (*base_string))
6948 --base_string;
252b5132 6949
47926f60 6950 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6951 displacement_string_start = op_string;
6952 displacement_string_end = base_string + 1;
252b5132 6953
24eab124
AM		 6954 if (*base_string == ')')
6955 {
af6bdddf 6956 char *temp_string;
24eab124
AM		 6957 unsigned int parens_balanced = 1;
6958 /* We've already checked that the number of left & right ()'s are
47926f60 6959 equal, so this loop will not be infinite. */
24eab124
AM		 6960 do
6961 {
6962 base_string--;
6963 if (*base_string == ')')
6964 parens_balanced++;
6965 if (*base_string == '(')
6966 parens_balanced--;
6967 }
6968 while (parens_balanced);
c3332e24 6969
af6bdddf 6970 temp_string = base_string;
c3332e24 6971
24eab124 6972 /* Skip past '(' and whitespace. */
252b5132
RH		 6973 ++base_string;
6974 if (is_space_char (*base_string))
24eab124 6975 ++base_string;
252b5132 6976
af6bdddf 6977 if (*base_string == ','
4eed87de
AM		 6978 || ((i.base_reg = parse_register (base_string, &end_op))
6979 != NULL))
252b5132 6980 {
af6bdddf 6981 displacement_string_end = temp_string;
252b5132 6982
40fb9820 6983 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6984
af6bdddf 6985 if (i.base_reg)
24eab124 6986 {
24eab124
AM		 6987 base_string = end_op;
6988 if (is_space_char (*base_string))
6989 ++base_string;
af6bdddf
AM		 6990 }
6991
6992 /* There may be an index reg or scale factor here. */
6993 if (*base_string == ',')
6994 {
6995 ++base_string;
6996 if (is_space_char (*base_string))
6997 ++base_string;
6998
4eed87de
AM		 6999 if ((i.index_reg = parse_register (base_string, &end_op))
7000 != NULL)
24eab124 7001 {
af6bdddf 7002 base_string = end_op;
24eab124
AM		 7003 if (is_space_char (*base_string))
7004 ++base_string;
af6bdddf
AM		 7005 if (*base_string == ',')
7006 {
7007 ++base_string;
7008 if (is_space_char (*base_string))
7009 ++base_string;
7010 }
e5cb08ac 7011 else if (*base_string != ')')
af6bdddf 7012 {
4eed87de
AM		 7013 as_bad (_("expecting `,' or `)' "
7014 "after index register in `%s'"),
af6bdddf
AM		 7015 operand_string);
7016 return 0;
7017 }
24eab124 7018 }
af6bdddf 7019 else if (*base_string == REGISTER_PREFIX)
24eab124 7020 {
af6bdddf 7021 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7022 return 0;
7023 }
252b5132 7024
47926f60 7025 /* Check for scale factor. */
551c1ca1 7026 if (*base_string != ')')
af6bdddf 7027 {
551c1ca1
AM		 7028 char *end_scale = i386_scale (base_string);
7029
7030 if (!end_scale)
af6bdddf 7031 return 0;
24eab124 7032
551c1ca1 7033 base_string = end_scale;
af6bdddf
AM		 7034 if (is_space_char (*base_string))
7035 ++base_string;
7036 if (*base_string != ')')
7037 {
4eed87de
AM		 7038 as_bad (_("expecting `)' "
7039 "after scale factor in `%s'"),
af6bdddf
AM		 7040 operand_string);
7041 return 0;
7042 }
7043 }
7044 else if (!i.index_reg)
24eab124 7045 {
4eed87de
AM		 7046 as_bad (_("expecting index register or scale factor "
7047 "after `,'; got '%c'"),
af6bdddf 7048 *base_string);
24eab124
AM		 7049 return 0;
7050 }
7051 }
af6bdddf 7052 else if (*base_string != ')')
24eab124 7053 {
4eed87de
AM		 7054 as_bad (_("expecting `,' or `)' "
7055 "after base register in `%s'"),
af6bdddf 7056 operand_string);
24eab124
AM		 7057 return 0;
7058 }
c3332e24 7059 }
af6bdddf 7060 else if (*base_string == REGISTER_PREFIX)
c3332e24 7061 {
af6bdddf 7062 as_bad (_("bad register name `%s'"), base_string);
24eab124 7063 return 0;
c3332e24 7064 }
24eab124
AM		 7065 }
7066
7067 /* If there's an expression beginning the operand, parse it,
7068 assuming displacement_string_start and
7069 displacement_string_end are meaningful. */
7070 if (displacement_string_start != displacement_string_end)
7071 {
7072 if (!i386_displacement (displacement_string_start,
7073 displacement_string_end))
7074 return 0;
7075 }
7076
7077 /* Special case for (%dx) while doing input/output op. */
7078 if (i.base_reg
0dfbf9d7
L		 7079 && operand_type_equal (&i.base_reg->reg_type,
7080 &reg16_inoutportreg)
24eab124
AM		 7081 && i.index_reg == 0
7082 && i.log2_scale_factor == 0
7083 && i.seg[i.mem_operands] == 0
40fb9820 7084 && !operand_type_check (i.types[this_operand], disp))
24eab124 7085 {
65da13b5 7086 i.types[this_operand] = inoutportreg;
24eab124
AM		 7087 return 1;
7088 }
7089
eecb386c
AM		 7090 if (i386_index_check (operand_string) == 0)
7091 return 0;
5c07affc 7092 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7093 i.mem_operands++;
7094 }
7095 else
ce8a8b2f
AM		 7096 {
7097 /* It's not a memory operand; argh! */
24eab124
AM		 7098 as_bad (_("invalid char %s beginning operand %d `%s'"),
7099 output_invalid (*op_string),
7100 this_operand + 1,
7101 op_string);
7102 return 0;
7103 }
47926f60 7104 return 1; /* Normal return. */
252b5132
RH		 7105}
7106\f
ee7fcc42
AM		 7107/* md_estimate_size_before_relax()
7108
7109 Called just before relax() for rs_machine_dependent frags. The x86
7110 assembler uses these frags to handle variable size jump
7111 instructions.
7112
7113 Any symbol that is now undefined will not become defined.
7114 Return the correct fr_subtype in the frag.
7115 Return the initial "guess for variable size of frag" to caller.
7116 The guess is actually the growth beyond the fixed part. Whatever
7117 we do to grow the fixed or variable part contributes to our
7118 returned value. */
7119
252b5132
RH		 7120int
7121md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7122 fragS *fragP;
7123 segT segment;
252b5132 7124{
252b5132 7125 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7126 check for un-relaxable symbols. On an ELF system, we can't relax
7127 an externally visible symbol, because it may be overridden by a
7128 shared library. */
7129 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7130#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7131 || (IS_ELF
31312f95 7132 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7133 || S_IS_WEAK (fragP->fr_symbol)
7134 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7135 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7136#endif
7137#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7138 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7139 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7140#endif
7141 )
252b5132 7142 {
b98ef147
AM		 7143 /* Symbol is undefined in this segment, or we need to keep a
7144 reloc so that weak symbols can be overridden. */
7145 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7146 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7147 unsigned char *opcode;
7148 int old_fr_fix;
f6af82bd 7149
ee7fcc42 7150 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7151 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7152 else if (size == 2)
f6af82bd
AM		 7153 reloc_type = BFD_RELOC_16_PCREL;
7154 else
7155 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7156
ee7fcc42
AM		 7157 old_fr_fix = fragP->fr_fix;
7158 opcode = (unsigned char *) fragP->fr_opcode;
7159
fddf5b5b 7160 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7161 {
fddf5b5b
AM		 7162 case UNCOND_JUMP:
7163 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7164 opcode[0] = 0xe9;
252b5132 7165 fragP->fr_fix += size;
062cd5e7
AS		 7166 fix_new (fragP, old_fr_fix, size,
7167 fragP->fr_symbol,
7168 fragP->fr_offset, 1,
7169 reloc_type);
252b5132
RH		 7170 break;
7171
fddf5b5b 7172 case COND_JUMP86:
412167cb
AM		 7173 if (size == 2
7174 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7175 {
7176 /* Negate the condition, and branch past an
7177 unconditional jump. */
7178 opcode[0] ^= 1;
7179 opcode[1] = 3;
7180 /* Insert an unconditional jump. */
7181 opcode[2] = 0xe9;
7182 /* We added two extra opcode bytes, and have a two byte
7183 offset. */
7184 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7185 fix_new (fragP, old_fr_fix + 2, 2,
7186 fragP->fr_symbol,
7187 fragP->fr_offset, 1,
7188 reloc_type);
fddf5b5b
AM		 7189 break;
7190 }
7191 /* Fall through. */
7192
7193 case COND_JUMP:
412167cb
AM		 7194 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7195 {
3e02c1cc
AM		 7196 fixS *fixP;
7197
412167cb 7198 fragP->fr_fix += 1;
3e02c1cc
AM		 7199 fixP = fix_new (fragP, old_fr_fix, 1,
7200 fragP->fr_symbol,
7201 fragP->fr_offset, 1,
7202 BFD_RELOC_8_PCREL);
7203 fixP->fx_signed = 1;
412167cb
AM		 7204 break;
7205 }
93c2a809 7206
24eab124 7207 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7208 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7209 opcode[1] = opcode[0] + 0x10;
f6af82bd 7210 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7211 /* We've added an opcode byte. */
7212 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7213 fix_new (fragP, old_fr_fix + 1, size,
7214 fragP->fr_symbol,
7215 fragP->fr_offset, 1,
7216 reloc_type);
252b5132 7217 break;
fddf5b5b
AM		 7218
7219 default:
7220 BAD_CASE (fragP->fr_subtype);
7221 break;
252b5132
RH		 7222 }
7223 frag_wane (fragP);
ee7fcc42 7224 return fragP->fr_fix - old_fr_fix;
252b5132 7225 }
93c2a809 7226
93c2a809
AM		 7227 /* Guess size depending on current relax state. Initially the relax
7228 state will correspond to a short jump and we return 1, because
7229 the variable part of the frag (the branch offset) is one byte
7230 long. However, we can relax a section more than once and in that
7231 case we must either set fr_subtype back to the unrelaxed state,
7232 or return the value for the appropriate branch. */
7233 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7234}
7235
47926f60
KH		 7236/* Called after relax() is finished.
7237
7238 In: Address of frag.
7239 fr_type == rs_machine_dependent.
7240 fr_subtype is what the address relaxed to.
7241
7242 Out: Any fixSs and constants are set up.
7243 Caller will turn frag into a ".space 0". */
7244
252b5132
RH		 7245void
7246md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7247 bfd *abfd ATTRIBUTE_UNUSED;
7248 segT sec ATTRIBUTE_UNUSED;
29b0f896 7249 fragS *fragP;
252b5132 7250{
29b0f896 7251 unsigned char *opcode;
252b5132 7252 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7253 offsetT target_address;
7254 offsetT opcode_address;
252b5132 7255 unsigned int extension = 0;
847f7ad4 7256 offsetT displacement_from_opcode_start;
252b5132
RH		 7257
7258 opcode = (unsigned char *) fragP->fr_opcode;
7259
47926f60 7260 /* Address we want to reach in file space. */
252b5132 7261 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7262
47926f60 7263 /* Address opcode resides at in file space. */
252b5132
RH		 7264 opcode_address = fragP->fr_address + fragP->fr_fix;
7265
47926f60 7266 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7267 displacement_from_opcode_start = target_address - opcode_address;
7268
fddf5b5b 7269 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7270 {
47926f60
KH		 7271 /* Don't have to change opcode. */
7272 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7273 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7274 }
7275 else
7276 {
7277 if (no_cond_jump_promotion
7278 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7279 as_warn_where (fragP->fr_file, fragP->fr_line,
7280 _("long jump required"));
252b5132 7281
fddf5b5b
AM		 7282 switch (fragP->fr_subtype)
7283 {
7284 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7285 extension = 4; /* 1 opcode + 4 displacement */
7286 opcode[0] = 0xe9;
7287 where_to_put_displacement = &opcode[1];
7288 break;
252b5132 7289
fddf5b5b
AM		 7290 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7291 extension = 2; /* 1 opcode + 2 displacement */
7292 opcode[0] = 0xe9;
7293 where_to_put_displacement = &opcode[1];
7294 break;
252b5132 7295
fddf5b5b
AM		 7296 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7297 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7298 extension = 5; /* 2 opcode + 4 displacement */
7299 opcode[1] = opcode[0] + 0x10;
7300 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7301 where_to_put_displacement = &opcode[2];
7302 break;
252b5132 7303
fddf5b5b
AM		 7304 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7305 extension = 3; /* 2 opcode + 2 displacement */
7306 opcode[1] = opcode[0] + 0x10;
7307 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7308 where_to_put_displacement = &opcode[2];
7309 break;
252b5132 7310
fddf5b5b
AM		 7311 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7312 extension = 4;
7313 opcode[0] ^= 1;
7314 opcode[1] = 3;
7315 opcode[2] = 0xe9;
7316 where_to_put_displacement = &opcode[3];
7317 break;
7318
7319 default:
7320 BAD_CASE (fragP->fr_subtype);
7321 break;
7322 }
252b5132 7323 }
fddf5b5b 7324
7b81dfbb
AJ		 7325 /* If size if less then four we are sure that the operand fits,
7326 but if it's 4, then it could be that the displacement is larger
7327 then -/+ 2GB. */
7328 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7329 && object_64bit
7330 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7331 + ((addressT) 1 << 31))
7332 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7333 {
7334 as_bad_where (fragP->fr_file, fragP->fr_line,
7335 _("jump target out of range"));
7336 /* Make us emit 0. */
7337 displacement_from_opcode_start = extension;
7338 }
47926f60 7339 /* Now put displacement after opcode. */
252b5132
RH		 7340 md_number_to_chars ((char *) where_to_put_displacement,
7341 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7342 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7343 fragP->fr_fix += extension;
7344}
7345\f
252b5132
RH		 7346/* Apply a fixup (fixS) to segment data, once it has been determined
7347 by our caller that we have all the info we need to fix it up.
7348
7349 On the 386, immediates, displacements, and data pointers are all in
7350 the same (little-endian) format, so we don't need to care about which
7351 we are handling. */
7352
94f592af 7353void
55cf6793 7354md_apply_fix (fixP, valP, seg)
47926f60
KH		 7355 /* The fix we're to put in. */
7356 fixS *fixP;
47926f60 7357 /* Pointer to the value of the bits. */
c6682705 7358 valueT *valP;
47926f60
KH		 7359 /* Segment fix is from. */
7360 segT seg ATTRIBUTE_UNUSED;
252b5132 7361{
94f592af 7362 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7363 valueT value = *valP;
252b5132 7364
f86103b7 7365#if !defined (TE_Mach)
93382f6d
AM		 7366 if (fixP->fx_pcrel)
7367 {
7368 switch (fixP->fx_r_type)
7369 {
5865bb77
ILT		 7370 default:
7371 break;
7372
d6ab8113
JB		 7373 case BFD_RELOC_64:
7374 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7375 break;
93382f6d 7376 case BFD_RELOC_32:
ae8887b5 7377 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7378 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7379 break;
7380 case BFD_RELOC_16:
7381 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7382 break;
7383 case BFD_RELOC_8:
7384 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7385 break;
7386 }
7387 }
252b5132 7388
a161fe53 7389 if (fixP->fx_addsy != NULL
31312f95 7390 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7391 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7392 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7393 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7394 && !use_rela_relocations)
252b5132 7395 {
31312f95
AM		 7396 /* This is a hack. There should be a better way to handle this.
7397 This covers for the fact that bfd_install_relocation will
7398 subtract the current location (for partial_inplace, PC relative
7399 relocations); see more below. */
252b5132 7400#ifndef OBJ_AOUT
718ddfc0 7401 if (IS_ELF
252b5132
RH		 7402#ifdef TE_PE
7403 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7404#endif
7405 )
7406 value += fixP->fx_where + fixP->fx_frag->fr_address;
7407#endif
7408#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7409 if (IS_ELF)
252b5132 7410 {
6539b54b 7411 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7412
6539b54b 7413 if ((sym_seg == seg
2f66722d 7414 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7415 && sym_seg != absolute_section))
af65af87 7416 && !generic_force_reloc (fixP))
2f66722d
AM		 7417 {
7418 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7419 bfd_install_relocation subtracts them out again. I think
7420 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7421 it. FIXME. */
7422 value += fixP->fx_where + fixP->fx_frag->fr_address;
7423 }
252b5132
RH		 7424 }
7425#endif
7426#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7427 /* For some reason, the PE format does not store a
7428 section address offset for a PC relative symbol. */
7429 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7430 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7431 value += md_pcrel_from (fixP);
7432#endif
7433 }
fbeb56a4
DK		 7434#if defined (OBJ_COFF) && defined (TE_PE)
7435 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7436 {
7437 value -= S_GET_VALUE (fixP->fx_addsy);
7438 }
7439#endif
252b5132
RH		 7440
7441 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7442 and we must not disappoint it. */
252b5132 7443#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7444 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7445 switch (fixP->fx_r_type)
7446 {
7447 case BFD_RELOC_386_PLT32:
3e73aa7c 7448 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7449 /* Make the jump instruction point to the address of the operand. At
7450 runtime we merely add the offset to the actual PLT entry. */
7451 value = -4;
7452 break;
31312f95 7453
13ae64f3
JJ		 7454 case BFD_RELOC_386_TLS_GD:
7455 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7456 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7457 case BFD_RELOC_386_TLS_IE:
7458 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7459 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7460 case BFD_RELOC_X86_64_TLSGD:
7461 case BFD_RELOC_X86_64_TLSLD:
7462 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7463 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7464 value = 0; /* Fully resolved at runtime. No addend. */
7465 /* Fallthrough */
7466 case BFD_RELOC_386_TLS_LE:
7467 case BFD_RELOC_386_TLS_LDO_32:
7468 case BFD_RELOC_386_TLS_LE_32:
7469 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7470 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7471 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7472 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7473 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7474 break;
7475
67a4f2b7
AO		 7476 case BFD_RELOC_386_TLS_DESC_CALL:
7477 case BFD_RELOC_X86_64_TLSDESC_CALL:
7478 value = 0; /* Fully resolved at runtime. No addend. */
7479 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7480 fixP->fx_done = 0;
7481 return;
7482
00f7efb6
JJ		 7483 case BFD_RELOC_386_GOT32:
7484 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7485 value = 0; /* Fully resolved at runtime. No addend. */
7486 break;
47926f60
KH		 7487
7488 case BFD_RELOC_VTABLE_INHERIT:
7489 case BFD_RELOC_VTABLE_ENTRY:
7490 fixP->fx_done = 0;
94f592af 7491 return;
47926f60
KH		 7492
7493 default:
7494 break;
7495 }
7496#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7497 *valP = value;
f86103b7 7498#endif /* !defined (TE_Mach) */
3e73aa7c 7499
3e73aa7c 7500 /* Are we finished with this relocation now? */
c6682705 7501 if (fixP->fx_addsy == NULL)
3e73aa7c 7502 fixP->fx_done = 1;
fbeb56a4
DK		 7503#if defined (OBJ_COFF) && defined (TE_PE)
7504 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7505 {
7506 fixP->fx_done = 0;
7507 /* Remember value for tc_gen_reloc. */
7508 fixP->fx_addnumber = value;
7509 /* Clear out the frag for now. */
7510 value = 0;
7511 }
7512#endif
3e73aa7c
JH		 7513 else if (use_rela_relocations)
7514 {
7515 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7516 /* Remember value for tc_gen_reloc. */
7517 fixP->fx_addnumber = value;
3e73aa7c
JH		 7518 value = 0;
7519 }
f86103b7 7520
94f592af 7521 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7522}
252b5132 7523\f
252b5132 7524char *
499ac353 7525md_atof (int type, char *litP, int *sizeP)
252b5132 7526{
499ac353
NC		 7527 /* This outputs the LITTLENUMs in REVERSE order;
7528 in accord with the bigendian 386. */
7529 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7530}
7531\f
2d545b82 7532static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7533
252b5132 7534static char *
e3bb37b5 7535output_invalid (int c)
252b5132 7536{
3882b010 7537 if (ISPRINT (c))
f9f21a03
L		 7538 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7539 "'%c'", c);
252b5132 7540 else
f9f21a03 7541 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7542 "(0x%x)", (unsigned char) c);
252b5132
RH		 7543 return output_invalid_buf;
7544}
7545
af6bdddf 7546/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7547
7548static const reg_entry *
4d1bb795 7549parse_real_register (char *reg_string, char **end_op)
252b5132 7550{
af6bdddf
AM		 7551 char *s = reg_string;
7552 char *p;
252b5132
RH		 7553 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7554 const reg_entry *r;
7555
7556 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7557 if (*s == REGISTER_PREFIX)
7558 ++s;
7559
7560 if (is_space_char (*s))
7561 ++s;
7562
7563 p = reg_name_given;
af6bdddf 7564 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7565 {
7566 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7567 return (const reg_entry *) NULL;
7568 s++;
252b5132
RH		 7569 }
7570
6588847e
DN		 7571 /* For naked regs, make sure that we are not dealing with an identifier.
7572 This prevents confusing an identifier like `eax_var' with register
7573 `eax'. */
7574 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7575 return (const reg_entry *) NULL;
7576
af6bdddf 7577 *end_op = s;
252b5132
RH		 7578
7579 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7580
5f47d35b 7581 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7582 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7583 {
5f47d35b
AM		 7584 if (is_space_char (*s))
7585 ++s;
7586 if (*s == '(')
7587 {
af6bdddf 7588 ++s;
5f47d35b
AM		 7589 if (is_space_char (*s))
7590 ++s;
7591 if (*s >= '0' && *s <= '7')
7592 {
db557034 7593 int fpr = *s - '0';
af6bdddf 7594 ++s;
5f47d35b
AM		 7595 if (is_space_char (*s))
7596 ++s;
7597 if (*s == ')')
7598 {
7599 *end_op = s + 1;
1e9cc1c2 7600 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7601 know (r);
7602 return r + fpr;
5f47d35b 7603 }
5f47d35b 7604 }
47926f60 7605 /* We have "%st(" then garbage. */
5f47d35b
AM		 7606 return (const reg_entry *) NULL;
7607 }
7608 }
7609
a60de03c
JB		 7610 if (r == NULL || allow_pseudo_reg)
7611 return r;
7612
0dfbf9d7 7613 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7614 return (const reg_entry *) NULL;
7615
192dc9c6
JB		 7616 if ((r->reg_type.bitfield.reg32
7617 || r->reg_type.bitfield.sreg3
7618 || r->reg_type.bitfield.control
7619 || r->reg_type.bitfield.debug
7620 || r->reg_type.bitfield.test)
7621 && !cpu_arch_flags.bitfield.cpui386)
7622 return (const reg_entry *) NULL;
7623
309d3373
JB		 7624 if (r->reg_type.bitfield.floatreg
7625 && !cpu_arch_flags.bitfield.cpu8087
7626 && !cpu_arch_flags.bitfield.cpu287
7627 && !cpu_arch_flags.bitfield.cpu387)
7628 return (const reg_entry *) NULL;
7629
192dc9c6
JB		 7630 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7631 return (const reg_entry *) NULL;
7632
7633 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7634 return (const reg_entry *) NULL;
7635
40f12533
L		 7636 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7637 return (const reg_entry *) NULL;
7638
db51cc60 7639 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7640 if (!allow_index_reg
db51cc60
L		 7641 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7642 return (const reg_entry *) NULL;
7643
a60de03c
JB		 7644 if (((r->reg_flags & (RegRex64 | RegRex))
7645 || r->reg_type.bitfield.reg64)
40fb9820 7646 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7647 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7648 && flag_code != CODE_64BIT)
20f0a1fc 7649 return (const reg_entry *) NULL;
1ae00879 7650
b7240065
JB		 7651 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7652 return (const reg_entry *) NULL;
7653
252b5132
RH		 7654 return r;
7655}
4d1bb795
JB		 7656
7657/* REG_STRING starts *before* REGISTER_PREFIX. */
7658
7659static const reg_entry *
7660parse_register (char *reg_string, char **end_op)
7661{
7662 const reg_entry *r;
7663
7664 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7665 r = parse_real_register (reg_string, end_op);
7666 else
7667 r = NULL;
7668 if (!r)
7669 {
7670 char *save = input_line_pointer;
7671 char c;
7672 symbolS *symbolP;
7673
7674 input_line_pointer = reg_string;
7675 c = get_symbol_end ();
7676 symbolP = symbol_find (reg_string);
7677 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7678 {
7679 const expressionS *e = symbol_get_value_expression (symbolP);
7680
7681 know (e->X_op == O_register);
4eed87de 7682 know (e->X_add_number >= 0
c3fe08fa 7683 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7684 r = i386_regtab + e->X_add_number;
7685 *end_op = input_line_pointer;
7686 }
7687 *input_line_pointer = c;
7688 input_line_pointer = save;
7689 }
7690 return r;
7691}
7692
7693int
7694i386_parse_name (char *name, expressionS *e, char *nextcharP)
7695{
7696 const reg_entry *r;
7697 char *end = input_line_pointer;
7698
7699 *end = *nextcharP;
7700 r = parse_register (name, &input_line_pointer);
7701 if (r && end <= input_line_pointer)
7702 {
7703 *nextcharP = *input_line_pointer;
7704 *input_line_pointer = 0;
7705 e->X_op = O_register;
7706 e->X_add_number = r - i386_regtab;
7707 return 1;
7708 }
7709 input_line_pointer = end;
7710 *end = 0;
ee86248c 7711 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7712}
7713
7714void
7715md_operand (expressionS *e)
7716{
ee86248c
JB		 7717 char *end;
7718 const reg_entry *r;
4d1bb795 7719
ee86248c
JB		 7720 switch (*input_line_pointer)
7721 {
7722 case REGISTER_PREFIX:
7723 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7724 if (r)
7725 {
7726 e->X_op = O_register;
7727 e->X_add_number = r - i386_regtab;
7728 input_line_pointer = end;
7729 }
ee86248c
JB		 7730 break;
7731
7732 case '[':
9c2799c2 7733 gas_assert (intel_syntax);
ee86248c
JB		 7734 end = input_line_pointer++;
7735 expression (e);
7736 if (*input_line_pointer == ']')
7737 {
7738 ++input_line_pointer;
7739 e->X_op_symbol = make_expr_symbol (e);
7740 e->X_add_symbol = NULL;
7741 e->X_add_number = 0;
7742 e->X_op = O_index;
7743 }
7744 else
7745 {
7746 e->X_op = O_absent;
7747 input_line_pointer = end;
7748 }
7749 break;
4d1bb795
JB		 7750 }
7751}
7752
252b5132 7753\f
4cc782b5 7754#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7755const char *md_shortopts = "kVQ:sqn";
252b5132 7756#else
12b55ccc 7757const char *md_shortopts = "qn";
252b5132 7758#endif
6e0b89ee 7759
3e73aa7c 7760#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7761#define OPTION_64 (OPTION_MD_BASE + 1)
7762#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7763#define OPTION_MARCH (OPTION_MD_BASE + 3)
7764#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7765#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7766#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7767#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7768#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7769#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7770#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7771#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7772
99ad8390
NC		 7773struct option md_longopts[] =
7774{
3e73aa7c 7775 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7776#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7777 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7778 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7779#endif
b3b91714 7780 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7781 {"march", required_argument, NULL, OPTION_MARCH},
7782 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7783 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7784 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7785 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7786 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7787 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7788 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7789 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7790 {NULL, no_argument, NULL, 0}
7791};
7792size_t md_longopts_size = sizeof (md_longopts);
7793
7794int
9103f4f4 7795md_parse_option (int c, char *arg)
252b5132 7796{
9103f4f4 7797 unsigned int i;
6305a203 7798 char *arch, *next;
9103f4f4 7799
252b5132
RH		 7800 switch (c)
7801 {
12b55ccc
L		 7802 case 'n':
7803 optimize_align_code = 0;
7804 break;
7805
a38cf1db
AM		 7806 case 'q':
7807 quiet_warnings = 1;
252b5132
RH		 7808 break;
7809
7810#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7811 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7812 should be emitted or not. FIXME: Not implemented. */
7813 case 'Q':
252b5132
RH		 7814 break;
7815
7816 /* -V: SVR4 argument to print version ID. */
7817 case 'V':
7818 print_version_id ();
7819 break;
7820
a38cf1db
AM		 7821 /* -k: Ignore for FreeBSD compatibility. */
7822 case 'k':
252b5132 7823 break;
4cc782b5
ILT		 7824
7825 case 's':
7826 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7827 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7828 break;
99ad8390 7829#endif
321098a5
L		 7830#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7831 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7832 case OPTION_64:
7833 {
7834 const char **list, **l;
7835
3e73aa7c
JH		 7836 list = bfd_target_list ();
7837 for (l = list; *l != NULL; l++)
8620418b 7838 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7839 || strcmp (*l, "coff-x86-64") == 0
7840 || strcmp (*l, "pe-x86-64") == 0
7841 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7842 {
7843 default_arch = "x86_64";
7844 break;
7845 }
3e73aa7c 7846 if (*l == NULL)
6e0b89ee 7847 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7848 free (list);
7849 }
7850 break;
7851#endif
252b5132 7852
6e0b89ee
AM		 7853 case OPTION_32:
7854 default_arch = "i386";
7855 break;
7856
b3b91714
AM		 7857 case OPTION_DIVIDE:
7858#ifdef SVR4_COMMENT_CHARS
7859 {
7860 char *n, *t;
7861 const char *s;
7862
7863 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7864 t = n;
7865 for (s = i386_comment_chars; *s != '\0'; s++)
7866 if (*s != '/')
7867 *t++ = *s;
7868 *t = '\0';
7869 i386_comment_chars = n;
7870 }
7871#endif
7872 break;
7873
9103f4f4 7874 case OPTION_MARCH:
6305a203
L		 7875 arch = xstrdup (arg);
7876 do
9103f4f4 7877 {
6305a203
L		 7878 if (*arch == '.')
7879 as_fatal (_("Invalid -march= option: `%s'"), arg);
7880 next = strchr (arch, '+');
7881 if (next)
7882 *next++ = '\0';
7883 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7884 {
6305a203 7885 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7886 {
6305a203
L		 7887 /* Processor. */
7888 cpu_arch_name = cpu_arch[i].name;
7889 cpu_sub_arch_name = NULL;
7890 cpu_arch_flags = cpu_arch[i].flags;
7891 cpu_arch_isa = cpu_arch[i].type;
7892 cpu_arch_isa_flags = cpu_arch[i].flags;
7893 if (!cpu_arch_tune_set)
7894 {
7895 cpu_arch_tune = cpu_arch_isa;
7896 cpu_arch_tune_flags = cpu_arch_isa_flags;
7897 }
7898 break;
7899 }
7900 else if (*cpu_arch [i].name == '.'
7901 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7902 {
7903 /* ISA entension. */
7904 i386_cpu_flags flags;
309d3373
JB		 7905
7906 if (strncmp (arch, "no", 2))
7907 flags = cpu_flags_or (cpu_arch_flags,
7908 cpu_arch[i].flags);
7909 else
7910 flags = cpu_flags_and_not (cpu_arch_flags,
7911 cpu_arch[i].flags);
0dfbf9d7 7912 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7913 {
7914 if (cpu_sub_arch_name)
7915 {
7916 char *name = cpu_sub_arch_name;
7917 cpu_sub_arch_name = concat (name,
7918 cpu_arch[i].name,
1bf57e9f 7919 (const char *) NULL);
6305a203
L		 7920 free (name);
7921 }
7922 else
7923 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7924 cpu_arch_flags = flags;
7925 }
7926 break;
ccc9c027 7927 }
9103f4f4 7928 }
6305a203
L		 7929
7930 if (i >= ARRAY_SIZE (cpu_arch))
7931 as_fatal (_("Invalid -march= option: `%s'"), arg);
7932
7933 arch = next;
9103f4f4 7934 }
6305a203 7935 while (next != NULL );
9103f4f4
L		 7936 break;
7937
7938 case OPTION_MTUNE:
7939 if (*arg == '.')
7940 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7941 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7942 {
7943 if (strcmp (arg, cpu_arch [i].name) == 0)
7944 {
ccc9c027 7945 cpu_arch_tune_set = 1;
9103f4f4
L		 7946 cpu_arch_tune = cpu_arch [i].type;
7947 cpu_arch_tune_flags = cpu_arch[i].flags;
7948 break;
7949 }
7950 }
7951 if (i >= ARRAY_SIZE (cpu_arch))
7952 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7953 break;
7954
1efbbeb4
L		 7955 case OPTION_MMNEMONIC:
7956 if (strcasecmp (arg, "att") == 0)
7957 intel_mnemonic = 0;
7958 else if (strcasecmp (arg, "intel") == 0)
7959 intel_mnemonic = 1;
7960 else
7961 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7962 break;
7963
7964 case OPTION_MSYNTAX:
7965 if (strcasecmp (arg, "att") == 0)
7966 intel_syntax = 0;
7967 else if (strcasecmp (arg, "intel") == 0)
7968 intel_syntax = 1;
7969 else
7970 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7971 break;
7972
7973 case OPTION_MINDEX_REG:
7974 allow_index_reg = 1;
7975 break;
7976
7977 case OPTION_MNAKED_REG:
7978 allow_naked_reg = 1;
7979 break;
7980
7981 case OPTION_MOLD_GCC:
7982 old_gcc = 1;
1efbbeb4
L		 7983 break;
7984
c0f3af97
L		 7985 case OPTION_MSSE2AVX:
7986 sse2avx = 1;
7987 break;
7988
daf50ae7
L		 7989 case OPTION_MSSE_CHECK:
7990 if (strcasecmp (arg, "error") == 0)
7991 sse_check = sse_check_error;
7992 else if (strcasecmp (arg, "warning") == 0)
7993 sse_check = sse_check_warning;
7994 else if (strcasecmp (arg, "none") == 0)
7995 sse_check = sse_check_none;
7996 else
7997 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7998 break;
7999
252b5132
RH		 8000 default:
8001 return 0;
8002 }
8003 return 1;
8004}
8005
8006void
8007md_show_usage (stream)
8008 FILE *stream;
8009{
4cc782b5
ILT		 8010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8011 fprintf (stream, _("\
a38cf1db
AM		 8012 -Q ignored\n\
8013 -V print assembler version number\n\
b3b91714
AM		 8014 -k ignored\n"));
8015#endif
8016 fprintf (stream, _("\
12b55ccc 8017 -n Do not optimize code alignment\n\
b3b91714
AM		 8018 -q quieten some warnings\n"));
8019#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8020 fprintf (stream, _("\
a38cf1db 8021 -s ignored\n"));
b3b91714 8022#endif
321098a5
L		 8023#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8024 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8025 fprintf (stream, _("\
8026 --32/--64 generate 32bit/64bit code\n"));
8027#endif
b3b91714
AM		 8028#ifdef SVR4_COMMENT_CHARS
8029 fprintf (stream, _("\
8030 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8031#else
8032 fprintf (stream, _("\
b3b91714 8033 --divide ignored\n"));
4cc782b5 8034#endif
9103f4f4 8035 fprintf (stream, _("\
6305a203
L		 8036 -march=CPU[,+EXTENSION...]\n\
8037 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8038 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8039 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8a9036a4
L		 8040 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8041 amdfam10, generic32, generic64\n\
599121aa 8042 EXTENSION is combination of:\n\
309d3373
JB		 8043 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8044 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8045 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2 8046 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
f88c9eb0 8047 svme, abm, padlock, fma4, lwp\n"));
6305a203 8048 fprintf (stream, _("\
2cb4f3d5
L		 8049 -mtune=CPU optimize for CPU, CPU is one of:\n\
8050 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8051 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8a9036a4
L		 8052 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8053 amdfam10, generic32, generic64\n"));
ba104c83 8054 fprintf (stream, _("\
c0f3af97
L		 8055 -msse2avx encode SSE instructions with VEX prefix\n"));
8056 fprintf (stream, _("\
daf50ae7
L		 8057 -msse-check=[none|error|warning]\n\
8058 check SSE instructions\n"));
8059 fprintf (stream, _("\
ba104c83
L		 8060 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8061 fprintf (stream, _("\
8062 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8063 fprintf (stream, _("\
8064 -mindex-reg support pseudo index registers\n"));
8065 fprintf (stream, _("\
8066 -mnaked-reg don't require `%%' prefix for registers\n"));
8067 fprintf (stream, _("\
8068 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8069}
8070
3e73aa7c 8071#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8072 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8073 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8074
8075/* Pick the target format to use. */
8076
47926f60 8077const char *
e3bb37b5 8078i386_target_format (void)
252b5132 8079{
3e73aa7c 8080 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8081 {
8082 set_code_flag (CODE_64BIT);
0dfbf9d7 8083 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8084 {
8085 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8086 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8087 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8088 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8089 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8090 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8091 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8092 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8093 cpu_arch_isa_flags.bitfield.cpusse = 1;
8094 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8095 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8096 }
0dfbf9d7 8097 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8098 {
8099 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8100 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8101 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8102 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8103 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8104 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8105 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8106 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8107 cpu_arch_tune_flags.bitfield.cpusse = 1;
8108 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8109 }
9103f4f4 8110 }
3e73aa7c 8111 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8112 {
8113 set_code_flag (CODE_32BIT);
0dfbf9d7 8114 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8115 {
8116 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8117 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8118 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8119 }
0dfbf9d7 8120 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8121 {
8122 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8123 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8124 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8125 }
9103f4f4 8126 }
3e73aa7c
JH		 8127 else
8128 as_fatal (_("Unknown architecture"));
252b5132
RH		 8129 switch (OUTPUT_FLAVOR)
8130 {
9384f2ff 8131#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8132 case bfd_target_aout_flavour:
47926f60 8133 return AOUT_TARGET_FORMAT;
4c63da97 8134#endif
9384f2ff
AM		 8135#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8136# if defined (TE_PE) || defined (TE_PEP)
8137 case bfd_target_coff_flavour:
8138 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8139# elif defined (TE_GO32)
0561d57c
JK		 8140 case bfd_target_coff_flavour:
8141 return "coff-go32";
9384f2ff 8142# else
252b5132
RH		 8143 case bfd_target_coff_flavour:
8144 return "coff-i386";
9384f2ff 8145# endif
4c63da97 8146#endif
3e73aa7c 8147#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8148 case bfd_target_elf_flavour:
3e73aa7c 8149 {
e5cb08ac 8150 if (flag_code == CODE_64BIT)
4fa24527
JB		 8151 {
8152 object_64bit = 1;
8153 use_rela_relocations = 1;
8154 }
3632d14b 8155 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8156 {
8157 if (flag_code != CODE_64BIT)
8158 as_fatal (_("Intel L1OM is 64bit only"));
8159 return ELF_TARGET_L1OM_FORMAT;
8160 }
8161 else
8162 return (flag_code == CODE_64BIT
8163 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8164 }
e57f8c65
TG		 8165#endif
8166#if defined (OBJ_MACH_O)
8167 case bfd_target_mach_o_flavour:
8168 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8169#endif
252b5132
RH		 8170 default:
8171 abort ();
8172 return NULL;
8173 }
8174}
8175
47926f60 8176#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8177
8178#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8179void
8180i386_elf_emit_arch_note (void)
a847613f 8181{
718ddfc0 8182 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8183 {
8184 char *p;
8185 asection *seg = now_seg;
8186 subsegT subseg = now_subseg;
8187 Elf_Internal_Note i_note;
8188 Elf_External_Note e_note;
8189 asection *note_secp;
8190 int len;
8191
8192 /* Create the .note section. */
8193 note_secp = subseg_new (".note", 0);
8194 bfd_set_section_flags (stdoutput,
8195 note_secp,
8196 SEC_HAS_CONTENTS | SEC_READONLY);
8197
8198 /* Process the arch string. */
8199 len = strlen (cpu_arch_name);
8200
8201 i_note.namesz = len + 1;
8202 i_note.descsz = 0;
8203 i_note.type = NT_ARCH;
8204 p = frag_more (sizeof (e_note.namesz));
8205 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8206 p = frag_more (sizeof (e_note.descsz));
8207 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8208 p = frag_more (sizeof (e_note.type));
8209 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8210 p = frag_more (len + 1);
8211 strcpy (p, cpu_arch_name);
8212
8213 frag_align (2, 0, 0);
8214
8215 subseg_set (seg, subseg);
8216 }
8217}
8218#endif
252b5132 8219\f
252b5132
RH		 8220symbolS *
8221md_undefined_symbol (name)
8222 char *name;
8223{
18dc2407
ILT		 8224 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8225 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8226 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8227 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8228 {
8229 if (!GOT_symbol)
8230 {
8231 if (symbol_find (name))
8232 as_bad (_("GOT already in symbol table"));
8233 GOT_symbol = symbol_new (name, undefined_section,
8234 (valueT) 0, &zero_address_frag);
8235 };
8236 return GOT_symbol;
8237 }
252b5132
RH		 8238 return 0;
8239}
8240
8241/* Round up a section size to the appropriate boundary. */
47926f60 8242
252b5132
RH		 8243valueT
8244md_section_align (segment, size)
ab9da554 8245 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8246 valueT size;
8247{
4c63da97
AM		 8248#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8249 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8250 {
8251 /* For a.out, force the section size to be aligned. If we don't do
8252 this, BFD will align it for us, but it will not write out the
8253 final bytes of the section. This may be a bug in BFD, but it is
8254 easier to fix it here since that is how the other a.out targets
8255 work. */
8256 int align;
8257
8258 align = bfd_get_section_alignment (stdoutput, segment);
8259 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8260 }
252b5132
RH		 8261#endif
8262
8263 return size;
8264}
8265
8266/* On the i386, PC-relative offsets are relative to the start of the
8267 next instruction. That is, the address of the offset, plus its
8268 size, since the offset is always the last part of the insn. */
8269
8270long
e3bb37b5 8271md_pcrel_from (fixS *fixP)
252b5132
RH		 8272{
8273 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8274}
8275
8276#ifndef I386COFF
8277
8278static void
e3bb37b5 8279s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8280{
29b0f896 8281 int temp;
252b5132 8282
8a75718c
JB		 8283#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8284 if (IS_ELF)
8285 obj_elf_section_change_hook ();
8286#endif
252b5132
RH		 8287 temp = get_absolute_expression ();
8288 subseg_set (bss_section, (subsegT) temp);
8289 demand_empty_rest_of_line ();
8290}
8291
8292#endif
8293
252b5132 8294void
e3bb37b5 8295i386_validate_fix (fixS *fixp)
252b5132
RH		 8296{
8297 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8298 {
23df1078
JH		 8299 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8300 {
4fa24527 8301 if (!object_64bit)
23df1078
JH		 8302 abort ();
8303 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8304 }
8305 else
8306 {
4fa24527 8307 if (!object_64bit)
d6ab8113
JB		 8308 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8309 else
8310 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8311 }
252b5132
RH		 8312 fixp->fx_subsy = 0;
8313 }
8314}
8315
252b5132
RH		 8316arelent *
8317tc_gen_reloc (section, fixp)
ab9da554 8318 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8319 fixS *fixp;
8320{
8321 arelent *rel;
8322 bfd_reloc_code_real_type code;
8323
8324 switch (fixp->fx_r_type)
8325 {
3e73aa7c
JH		 8326 case BFD_RELOC_X86_64_PLT32:
8327 case BFD_RELOC_X86_64_GOT32:
8328 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8329 case BFD_RELOC_386_PLT32:
8330 case BFD_RELOC_386_GOT32:
8331 case BFD_RELOC_386_GOTOFF:
8332 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8333 case BFD_RELOC_386_TLS_GD:
8334 case BFD_RELOC_386_TLS_LDM:
8335 case BFD_RELOC_386_TLS_LDO_32:
8336 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8337 case BFD_RELOC_386_TLS_IE:
8338 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8339 case BFD_RELOC_386_TLS_LE_32:
8340 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8341 case BFD_RELOC_386_TLS_GOTDESC:
8342 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8343 case BFD_RELOC_X86_64_TLSGD:
8344 case BFD_RELOC_X86_64_TLSLD:
8345 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8346 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8347 case BFD_RELOC_X86_64_GOTTPOFF:
8348 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8349 case BFD_RELOC_X86_64_TPOFF64:
8350 case BFD_RELOC_X86_64_GOTOFF64:
8351 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8352 case BFD_RELOC_X86_64_GOT64:
8353 case BFD_RELOC_X86_64_GOTPCREL64:
8354 case BFD_RELOC_X86_64_GOTPC64:
8355 case BFD_RELOC_X86_64_GOTPLT64:
8356 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8357 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8358 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8359 case BFD_RELOC_RVA:
8360 case BFD_RELOC_VTABLE_ENTRY:
8361 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8362#ifdef TE_PE
8363 case BFD_RELOC_32_SECREL:
8364#endif
252b5132
RH		 8365 code = fixp->fx_r_type;
8366 break;
dbbaec26
L		 8367 case BFD_RELOC_X86_64_32S:
8368 if (!fixp->fx_pcrel)
8369 {
8370 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8371 code = fixp->fx_r_type;
8372 break;
8373 }
252b5132 8374 default:
93382f6d 8375 if (fixp->fx_pcrel)
252b5132 8376 {
93382f6d
AM		 8377 switch (fixp->fx_size)
8378 {
8379 default:
b091f402
AM		 8380 as_bad_where (fixp->fx_file, fixp->fx_line,
8381 _("can not do %d byte pc-relative relocation"),
8382 fixp->fx_size);
93382f6d
AM		 8383 code = BFD_RELOC_32_PCREL;
8384 break;
8385 case 1: code = BFD_RELOC_8_PCREL; break;
8386 case 2: code = BFD_RELOC_16_PCREL; break;
8387 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8388#ifdef BFD64
8389 case 8: code = BFD_RELOC_64_PCREL; break;
8390#endif
93382f6d
AM		 8391 }
8392 }
8393 else
8394 {
8395 switch (fixp->fx_size)
8396 {
8397 default:
b091f402
AM		 8398 as_bad_where (fixp->fx_file, fixp->fx_line,
8399 _("can not do %d byte relocation"),
8400 fixp->fx_size);
93382f6d
AM		 8401 code = BFD_RELOC_32;
8402 break;
8403 case 1: code = BFD_RELOC_8; break;
8404 case 2: code = BFD_RELOC_16; break;
8405 case 4: code = BFD_RELOC_32; break;
937149dd 8406#ifdef BFD64
3e73aa7c 8407 case 8: code = BFD_RELOC_64; break;
937149dd 8408#endif
93382f6d 8409 }
252b5132
RH		 8410 }
8411 break;
8412 }
252b5132 8413
d182319b
JB		 8414 if ((code == BFD_RELOC_32
8415 || code == BFD_RELOC_32_PCREL
8416 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8417 && GOT_symbol
8418 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8419 {
4fa24527 8420 if (!object_64bit)
d6ab8113
JB		 8421 code = BFD_RELOC_386_GOTPC;
8422 else
8423 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8424 }
7b81dfbb
AJ		 8425 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8426 && GOT_symbol
8427 && fixp->fx_addsy == GOT_symbol)
8428 {
8429 code = BFD_RELOC_X86_64_GOTPC64;
8430 }
252b5132
RH		 8431
8432 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8433 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8434 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8435
8436 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8437
3e73aa7c
JH		 8438 if (!use_rela_relocations)
8439 {
8440 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8441 vtable entry to be used in the relocation's section offset. */
8442 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8443 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8444#if defined (OBJ_COFF) && defined (TE_PE)
8445 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8446 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8447 else
8448#endif
c6682705 8449 rel->addend = 0;
3e73aa7c
JH		 8450 }
8451 /* Use the rela in 64bit mode. */
252b5132 8452 else
3e73aa7c 8453 {
062cd5e7
AS		 8454 if (!fixp->fx_pcrel)
8455 rel->addend = fixp->fx_offset;
8456 else
8457 switch (code)
8458 {
8459 case BFD_RELOC_X86_64_PLT32:
8460 case BFD_RELOC_X86_64_GOT32:
8461 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8462 case BFD_RELOC_X86_64_TLSGD:
8463 case BFD_RELOC_X86_64_TLSLD:
8464 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8465 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8466 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8467 rel->addend = fixp->fx_offset - fixp->fx_size;
8468 break;
8469 default:
8470 rel->addend = (section->vma
8471 - fixp->fx_size
8472 + fixp->fx_addnumber
8473 + md_pcrel_from (fixp));
8474 break;
8475 }
3e73aa7c
JH		 8476 }
8477
252b5132
RH		 8478 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8479 if (rel->howto == NULL)
8480 {
8481 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8482 _("cannot represent relocation type %s"),
252b5132
RH		 8483 bfd_get_reloc_code_name (code));
8484 /* Set howto to a garbage value so that we can keep going. */
8485 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8486 gas_assert (rel->howto != NULL);
252b5132
RH		 8487 }
8488
8489 return rel;
8490}
8491
ee86248c 8492#include "tc-i386-intel.c"
54cfded0 8493
a60de03c
JB		 8494void
8495tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8496{
a60de03c
JB		 8497 int saved_naked_reg;
8498 char saved_register_dot;
54cfded0 8499
a60de03c
JB		 8500 saved_naked_reg = allow_naked_reg;
8501 allow_naked_reg = 1;
8502 saved_register_dot = register_chars['.'];
8503 register_chars['.'] = '.';
8504 allow_pseudo_reg = 1;
8505 expression_and_evaluate (exp);
8506 allow_pseudo_reg = 0;
8507 register_chars['.'] = saved_register_dot;
8508 allow_naked_reg = saved_naked_reg;
8509
8510 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8511 {
a60de03c
JB		 8512 if ((addressT) exp->X_add_number < i386_regtab_size)
8513 {
8514 exp->X_op = O_constant;
8515 exp->X_add_number = i386_regtab[exp->X_add_number]
8516 .dw2_regnum[flag_code >> 1];
8517 }
8518 else
8519 exp->X_op = O_illegal;
54cfded0 8520 }
54cfded0
AM		 8521}
8522
8523void
8524tc_x86_frame_initial_instructions (void)
8525{
a60de03c
JB		 8526 static unsigned int sp_regno[2];
8527
8528 if (!sp_regno[flag_code >> 1])
8529 {
8530 char *saved_input = input_line_pointer;
8531 char sp[][4] = {"esp", "rsp"};
8532 expressionS exp;
a4447b93 8533
a60de03c
JB		 8534 input_line_pointer = sp[flag_code >> 1];
8535 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8536 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8537 sp_regno[flag_code >> 1] = exp.X_add_number;
8538 input_line_pointer = saved_input;
8539 }
a4447b93 8540
a60de03c 8541 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8542 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8543}
d2b2c203
DJ		 8544
8545int
8546i386_elf_section_type (const char *str, size_t len)
8547{
8548 if (flag_code == CODE_64BIT
8549 && len == sizeof ("unwind") - 1
8550 && strncmp (str, "unwind", 6) == 0)
8551 return SHT_X86_64_UNWIND;
8552
8553 return -1;
8554}
bb41ade5 8555
ad5fec3b
EB		 8556#ifdef TE_SOLARIS
8557void
8558i386_solaris_fix_up_eh_frame (segT sec)
8559{
8560 if (flag_code == CODE_64BIT)
8561 elf_section_type (sec) = SHT_X86_64_UNWIND;
8562}
8563#endif
8564
bb41ade5
AM		 8565#ifdef TE_PE
8566void
8567tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8568{
8569 expressionS expr;
8570
8571 expr.X_op = O_secrel;
8572 expr.X_add_symbol = symbol;
8573 expr.X_add_number = 0;
8574 emit_expr (&expr, size);
8575}
8576#endif
3b22753a
L		 8577
8578#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8579/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8580
01e1a5bc 8581bfd_vma
3b22753a
L		 8582x86_64_section_letter (int letter, char **ptr_msg)
8583{
8584 if (flag_code == CODE_64BIT)
8585 {
8586 if (letter == 'l')
8587 return SHF_X86_64_LARGE;
8588
8589 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8590 }
3b22753a 8591 else
64e74474 8592 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8593 return -1;
8594}
8595
01e1a5bc 8596bfd_vma
3b22753a
L		 8597x86_64_section_word (char *str, size_t len)
8598{
8620418b 8599 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8600 return SHF_X86_64_LARGE;
8601
8602 return -1;
8603}
8604
8605static void
8606handle_large_common (int small ATTRIBUTE_UNUSED)
8607{
8608 if (flag_code != CODE_64BIT)
8609 {
8610 s_comm_internal (0, elf_common_parse);
8611 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8612 }
8613 else
8614 {
8615 static segT lbss_section;
8616 asection *saved_com_section_ptr = elf_com_section_ptr;
8617 asection *saved_bss_section = bss_section;
8618
8619 if (lbss_section == NULL)
8620 {
8621 flagword applicable;
8622 segT seg = now_seg;
8623 subsegT subseg = now_subseg;
8624
8625 /* The .lbss section is for local .largecomm symbols. */
8626 lbss_section = subseg_new (".lbss", 0);
8627 applicable = bfd_applicable_section_flags (stdoutput);
8628 bfd_set_section_flags (stdoutput, lbss_section,
8629 applicable & SEC_ALLOC);
8630 seg_info (lbss_section)->bss = 1;
8631
8632 subseg_set (seg, subseg);
8633 }
8634
8635 elf_com_section_ptr = &_bfd_elf_large_com_section;
8636 bss_section = lbss_section;
8637
8638 s_comm_internal (0, elf_common_parse);
8639
8640 elf_com_section_ptr = saved_com_section_ptr;
8641 bss_section = saved_bss_section;
8642 }
8643}
8644#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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