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Support for @GOTOFF in .long expressions.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4
NC		 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132
RH		 28
29#include <ctype.h>
30
31#include "as.h"
32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
252b5132
RH		 34#include "opcode/i386.h"
35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
252b5132
RH		 44#ifndef SCALE1_WHEN_NO_INDEX
45/* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49#define SCALE1_WHEN_NO_INDEX 1
50#endif
51
52#define true 1
53#define false 0
54
55static unsigned int mode_from_disp_size PARAMS ((unsigned int));
847f7ad4
AM		 56static int fits_in_signed_byte PARAMS ((offsetT));
57static int fits_in_unsigned_byte PARAMS ((offsetT));
58static int fits_in_unsigned_word PARAMS ((offsetT));
59static int fits_in_signed_word PARAMS ((offsetT));
3e73aa7c
JH		 60static int fits_in_unsigned_long PARAMS ((offsetT));
61static int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 62static int smallest_imm_type PARAMS ((offsetT));
63static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 64static int add_prefix PARAMS ((unsigned int));
3e73aa7c 65static void set_code_flag PARAMS ((int));
47926f60 66static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 67static void set_intel_syntax PARAMS ((int));
e413e4e9 68static void set_cpu_arch PARAMS ((int));
252b5132
RH		 69
70#ifdef BFD_ASSEMBLER
71static bfd_reloc_code_real_type reloc
3e73aa7c 72 PARAMS ((int, int, int, bfd_reloc_code_real_type));
f3c180ae
AM		 73#define RELOC_ENUM enum bfd_reloc_code_real
74#else
75#define RELOC_ENUM int
252b5132
RH		 76#endif
77
3e73aa7c
JH		 78#ifndef DEFAULT_ARCH
79#define DEFAULT_ARCH "i386"
80#endif
81static char *default_arch = DEFAULT_ARCH;
82
252b5132 83/* 'md_assemble ()' gathers together information and puts it into a
47926f60 84 i386_insn. */
252b5132 85
520dc8e8
AM		 86union i386_op
87 {
88 expressionS *disps;
89 expressionS *imms;
90 const reg_entry *regs;
91 };
92
252b5132
RH		 93struct _i386_insn
94 {
47926f60 95 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 96 template tm;
97
98 /* SUFFIX holds the instruction mnemonic suffix if given.
99 (e.g. 'l' for 'movl') */
100 char suffix;
101
47926f60 102 /* OPERANDS gives the number of given operands. */
252b5132
RH		 103 unsigned int operands;
104
105 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
106 of given register, displacement, memory operands and immediate
47926f60 107 operands. */
252b5132
RH		 108 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
109
110 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 111 use OP[i] for the corresponding operand. */
252b5132
RH		 112 unsigned int types[MAX_OPERANDS];
113
520dc8e8
AM		 114 /* Displacement expression, immediate expression, or register for each
115 operand. */
116 union i386_op op[MAX_OPERANDS];
252b5132 117
3e73aa7c
JH		 118 /* Flags for operands. */
119 unsigned int flags[MAX_OPERANDS];
120#define Operand_PCrel 1
121
252b5132 122 /* Relocation type for operand */
f3c180ae 123 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 124
252b5132
RH		 125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry *base_reg;
128 const reg_entry *index_reg;
129 unsigned int log2_scale_factor;
130
131 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 132 explicit segment overrides are given. */
ce8a8b2f 133 const seg_entry *seg[2];
252b5132
RH		 134
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes;
138 unsigned char prefix[MAX_PREFIXES];
139
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
142
143 modrm_byte rm;
3e73aa7c 144 rex_byte rex;
252b5132
RH		 145 sib_byte sib;
146 };
147
148typedef struct _i386_insn i386_insn;
149
150/* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
152#ifdef LEX_AT
153const char extra_symbol_chars[] = "*%-(@";
154#else
155const char extra_symbol_chars[] = "*%-(";
156#endif
157
158/* This array holds the chars that always start a comment. If the
ce8a8b2f 159 pre-processor is disabled, these aren't very useful. */
60bcf0fa 160#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
252b5132
RH		 161/* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163const char comment_chars[] = "#/";
164#define PREFIX_SEPARATOR '\\'
165#else
166const char comment_chars[] = "#";
167#define PREFIX_SEPARATOR '/'
168#endif
169
170/* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 174 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
252b5132 177 '/' isn't otherwise defined. */
60bcf0fa 178#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
252b5132
RH		 179const char line_comment_chars[] = "";
180#else
181const char line_comment_chars[] = "/";
182#endif
183
63a0b638 184const char line_separator_chars[] = ";";
252b5132 185
ce8a8b2f
AM		 186/* Chars that can be used to separate mant from exp in floating point
187 nums. */
252b5132
RH		 188const char EXP_CHARS[] = "eE";
189
ce8a8b2f
AM		 190/* Chars that mean this number is a floating point constant
191 As in 0f12.456
192 or 0d1.2345e12. */
252b5132
RH		 193const char FLT_CHARS[] = "fFdDxX";
194
ce8a8b2f 195/* Tables for lexical analysis. */
252b5132
RH		 196static char mnemonic_chars[256];
197static char register_chars[256];
198static char operand_chars[256];
199static char identifier_chars[256];
200static char digit_chars[256];
201
ce8a8b2f 202/* Lexical macros. */
252b5132
RH		 203#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204#define is_operand_char(x) (operand_chars[(unsigned char) x])
205#define is_register_char(x) (register_chars[(unsigned char) x])
206#define is_space_char(x) ((x) == ' ')
207#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208#define is_digit_char(x) (digit_chars[(unsigned char) x])
209
ce8a8b2f 210/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 211static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
212
213/* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
47926f60 216 assembler instruction). */
252b5132 217static char save_stack[32];
ce8a8b2f 218static char *save_stack_p;
252b5132
RH		 219#define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221#define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
223
47926f60 224/* The instruction we're assembling. */
252b5132
RH		 225static i386_insn i;
226
227/* Possible templates for current insn. */
228static const templates *current_templates;
229
47926f60 230/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 231static expressionS disp_expressions[2], im_expressions[2];
232
47926f60
KH		 233/* Current operand we are working on. */
234static int this_operand;
252b5132 235
3e73aa7c
JH		 236/* We support four different modes. FLAG_CODE variable is used to distinguish
237 these. */
238
239enum flag_code {
240 CODE_32BIT,
241 CODE_16BIT,
242 CODE_64BIT };
f3c180ae 243#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 244
245static enum flag_code flag_code;
246static int use_rela_relocations = 0;
247
248/* The names used to print error messages. */
b77a7acd 249static const char *flag_code_names[] =
3e73aa7c
JH		 250 {
251 "32",
252 "16",
253 "64"
254 };
252b5132 255
47926f60
KH		 256/* 1 for intel syntax,
257 0 if att syntax. */
258static int intel_syntax = 0;
252b5132 259
47926f60
KH		 260/* 1 if register prefix % not required. */
261static int allow_naked_reg = 0;
252b5132 262
47926f60
KH		 263/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
264 leave, push, and pop instructions so that gcc has the same stack
265 frame as in 32 bit mode. */
266static char stackop_size = '\0';
eecb386c 267
47926f60
KH		 268/* Non-zero to quieten some warnings. */
269static int quiet_warnings = 0;
a38cf1db 270
47926f60
KH		 271/* CPU name. */
272static const char *cpu_arch_name = NULL;
a38cf1db 273
47926f60 274/* CPU feature flags. */
3e73aa7c 275static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
a38cf1db 276
fddf5b5b
AM		 277/* If set, conditional jumps are not automatically promoted to handle
278 larger than a byte offset. */
279static unsigned int no_cond_jump_promotion = 0;
280
252b5132 281/* Interface to relax_segment.
fddf5b5b
AM		 282 There are 3 major relax states for 386 jump insns because the
283 different types of jumps add different sizes to frags when we're
284 figuring out what sort of jump to choose to reach a given label. */
252b5132 285
47926f60 286/* Types. */
fddf5b5b
AM		 287#define UNCOND_JUMP 1
288#define COND_JUMP 2
289#define COND_JUMP86 3
290
47926f60 291/* Sizes. */
252b5132
RH		 292#define CODE16 1
293#define SMALL 0
294#define SMALL16 (SMALL|CODE16)
295#define BIG 2
296#define BIG16 (BIG|CODE16)
297
298#ifndef INLINE
299#ifdef __GNUC__
300#define INLINE __inline__
301#else
302#define INLINE
303#endif
304#endif
305
fddf5b5b
AM		 306#define ENCODE_RELAX_STATE(type, size) \
307 ((relax_substateT) (((type) << 2) | (size)))
308#define TYPE_FROM_RELAX_STATE(s) \
309 ((s) >> 2)
310#define DISP_SIZE_FROM_RELAX_STATE(s) \
311 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 312
313/* This table is used by relax_frag to promote short jumps to long
314 ones where necessary. SMALL (short) jumps may be promoted to BIG
315 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
316 don't allow a short jump in a 32 bit code segment to be promoted to
317 a 16 bit offset jump because it's slower (requires data size
318 prefix), and doesn't work, unless the destination is in the bottom
319 64k of the code segment (The top 16 bits of eip are zeroed). */
320
321const relax_typeS md_relax_table[] =
322{
24eab124
AM		 323 /* The fields are:
324 1) most positive reach of this state,
325 2) most negative reach of this state,
326 3) how many bytes this mode will add to the size of the current frag
ce8a8b2f 327 4) which index into the table to try if we can't fit into this one. */
252b5132
RH		 328 {1, 1, 0, 0},
329 {1, 1, 0, 0},
330 {1, 1, 0, 0},
331 {1, 1, 0, 0},
332
fddf5b5b
AM		 333 /* UNCOND_JUMP states. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
338 {0, 0, 3, 0},
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
341 {0, 0, 1, 0},
342
343 /* COND_JUMP states. */
252b5132
RH		 344 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
345 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
346 /* dword conditionals adds 4 bytes to frag:
347 1 extra opcode byte, 3 extra displacement bytes. */
348 {0, 0, 4, 0},
349 /* word conditionals add 2 bytes to frag:
350 1 extra opcode byte, 1 extra displacement byte. */
351 {0, 0, 2, 0},
352
fddf5b5b
AM		 353 /* COND_JUMP86 states. */
354 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
355 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
356 /* dword conditionals adds 4 bytes to frag:
357 1 extra opcode byte, 3 extra displacement bytes. */
358 {0, 0, 4, 0},
359 /* word conditionals add 3 bytes to frag:
360 1 extra opcode byte, 2 extra displacement bytes. */
361 {0, 0, 3, 0}
252b5132
RH		 362};
363
e413e4e9
AM		 364static const arch_entry cpu_arch[] = {
365 {"i8086", Cpu086 },
366 {"i186", Cpu086|Cpu186 },
367 {"i286", Cpu086|Cpu186|Cpu286 },
368 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
369 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
370 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
371 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
372 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
373 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 374 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 375 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
376 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 377 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 378 {NULL, 0 }
379};
380
252b5132
RH		 381void
382i386_align_code (fragP, count)
383 fragS *fragP;
384 int count;
385{
ce8a8b2f
AM		 386 /* Various efficient no-op patterns for aligning code labels.
387 Note: Don't try to assemble the instructions in the comments.
388 0L and 0w are not legal. */
252b5132
RH		 389 static const char f32_1[] =
390 {0x90}; /* nop */
391 static const char f32_2[] =
392 {0x89,0xf6}; /* movl %esi,%esi */
393 static const char f32_3[] =
394 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
395 static const char f32_4[] =
396 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
397 static const char f32_5[] =
398 {0x90, /* nop */
399 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
400 static const char f32_6[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
402 static const char f32_7[] =
403 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
404 static const char f32_8[] =
405 {0x90, /* nop */
406 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
407 static const char f32_9[] =
408 {0x89,0xf6, /* movl %esi,%esi */
409 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
410 static const char f32_10[] =
411 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
412 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
413 static const char f32_11[] =
414 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
415 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
416 static const char f32_12[] =
417 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
418 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
419 static const char f32_13[] =
420 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
421 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
422 static const char f32_14[] =
423 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
424 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
425 static const char f32_15[] =
426 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
427 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 428 static const char f16_3[] =
429 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 430 static const char f16_4[] =
431 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
432 static const char f16_5[] =
433 {0x90, /* nop */
434 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
435 static const char f16_6[] =
436 {0x89,0xf6, /* mov %si,%si */
437 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
438 static const char f16_7[] =
439 {0x8d,0x74,0x00, /* lea 0(%si),%si */
440 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
441 static const char f16_8[] =
442 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
443 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
444 static const char *const f32_patt[] = {
445 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
446 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
447 };
448 static const char *const f16_patt[] = {
c3332e24 449 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 450 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
451 };
452
3e73aa7c
JH		 453 /* ??? We can't use these fillers for x86_64, since they often kills the
454 upper halves. Solve later. */
455 if (flag_code == CODE_64BIT)
456 count = 1;
457
252b5132
RH		 458 if (count > 0 && count <= 15)
459 {
3e73aa7c 460 if (flag_code == CODE_16BIT)
252b5132 461 {
47926f60
KH		 462 memcpy (fragP->fr_literal + fragP->fr_fix,
463 f16_patt[count - 1], count);
464 if (count > 8)
465 /* Adjust jump offset. */
252b5132
RH		 466 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
467 }
468 else
47926f60
KH		 469 memcpy (fragP->fr_literal + fragP->fr_fix,
470 f32_patt[count - 1], count);
252b5132
RH		 471 fragP->fr_var = count;
472 }
473}
474
475static char *output_invalid PARAMS ((int c));
476static int i386_operand PARAMS ((char *operand_string));
477static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
478static const reg_entry *parse_register PARAMS ((char *reg_string,
479 char **end_op));
480
481#ifndef I386COFF
482static void s_bss PARAMS ((int));
483#endif
484
ce8a8b2f 485symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
252b5132
RH		 486
487static INLINE unsigned int
488mode_from_disp_size (t)
489 unsigned int t;
490{
3e73aa7c 491 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 492}
493
494static INLINE int
495fits_in_signed_byte (num)
847f7ad4 496 offsetT num;
252b5132
RH		 497{
498 return (num >= -128) && (num <= 127);
47926f60 499}
252b5132
RH		 500
501static INLINE int
502fits_in_unsigned_byte (num)
847f7ad4 503 offsetT num;
252b5132
RH		 504{
505 return (num & 0xff) == num;
47926f60 506}
252b5132
RH		 507
508static INLINE int
509fits_in_unsigned_word (num)
847f7ad4 510 offsetT num;
252b5132
RH		 511{
512 return (num & 0xffff) == num;
47926f60 513}
252b5132
RH		 514
515static INLINE int
516fits_in_signed_word (num)
847f7ad4 517 offsetT num;
252b5132
RH		 518{
519 return (-32768 <= num) && (num <= 32767);
47926f60 520}
3e73aa7c
JH		 521static INLINE int
522fits_in_signed_long (num)
523 offsetT num ATTRIBUTE_UNUSED;
524{
525#ifndef BFD64
526 return 1;
527#else
528 return (!(((offsetT) -1 << 31) & num)
529 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
530#endif
531} /* fits_in_signed_long() */
532static INLINE int
533fits_in_unsigned_long (num)
534 offsetT num ATTRIBUTE_UNUSED;
535{
536#ifndef BFD64
537 return 1;
538#else
539 return (num & (((offsetT) 2 << 31) - 1)) == num;
540#endif
541} /* fits_in_unsigned_long() */
252b5132
RH		 542
543static int
544smallest_imm_type (num)
847f7ad4 545 offsetT num;
252b5132 546{
3e73aa7c
JH		 547 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
548 && !(cpu_arch_flags & (CpuUnknown)))
e413e4e9
AM		 549 {
550 /* This code is disabled on the 486 because all the Imm1 forms
551 in the opcode table are slower on the i486. They're the
552 versions with the implicitly specified single-position
553 displacement, which has another syntax if you really want to
554 use that form. */
555 if (num == 1)
3e73aa7c 556 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 557 }
252b5132 558 return (fits_in_signed_byte (num)
3e73aa7c 559 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 560 : fits_in_unsigned_byte (num)
3e73aa7c 561 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 562 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 563 ? (Imm16 | Imm32 | Imm32S | Imm64)
564 : fits_in_signed_long (num)
565 ? (Imm32 | Imm32S | Imm64)
566 : fits_in_unsigned_long (num)
567 ? (Imm32 | Imm64)
568 : Imm64);
47926f60 569}
252b5132 570
847f7ad4
AM		 571static offsetT
572offset_in_range (val, size)
573 offsetT val;
574 int size;
575{
508866be 576 addressT mask;
ba2adb93 577
847f7ad4
AM		 578 switch (size)
579 {
508866be
L		 580 case 1: mask = ((addressT) 1 << 8) - 1; break;
581 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 582 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 583#ifdef BFD64
584 case 8: mask = ((addressT) 2 << 63) - 1; break;
585#endif
47926f60 586 default: abort ();
847f7ad4
AM		 587 }
588
ba2adb93 589 /* If BFD64, sign extend val. */
3e73aa7c
JH		 590 if (!use_rela_relocations)
591 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
592 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 593
47926f60 594 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 595 {
596 char buf1[40], buf2[40];
597
598 sprint_value (buf1, val);
599 sprint_value (buf2, val & mask);
600 as_warn (_("%s shortened to %s"), buf1, buf2);
601 }
602 return val & mask;
603}
604
252b5132
RH		 605/* Returns 0 if attempting to add a prefix where one from the same
606 class already exists, 1 if non rep/repne added, 2 if rep/repne
607 added. */
608static int
609add_prefix (prefix)
610 unsigned int prefix;
611{
612 int ret = 1;
613 int q;
614
3e73aa7c
JH		 615 if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT)
616 q = REX_PREFIX;
617 else
618 switch (prefix)
619 {
620 default:
621 abort ();
622
623 case CS_PREFIX_OPCODE:
624 case DS_PREFIX_OPCODE:
625 case ES_PREFIX_OPCODE:
626 case FS_PREFIX_OPCODE:
627 case GS_PREFIX_OPCODE:
628 case SS_PREFIX_OPCODE:
629 q = SEG_PREFIX;
630 break;
252b5132 631
3e73aa7c
JH		 632 case REPNE_PREFIX_OPCODE:
633 case REPE_PREFIX_OPCODE:
634 ret = 2;
635 /* fall thru */
636 case LOCK_PREFIX_OPCODE:
637 q = LOCKREP_PREFIX;
638 break;
252b5132 639
3e73aa7c
JH		 640 case FWAIT_OPCODE:
641 q = WAIT_PREFIX;
642 break;
252b5132 643
3e73aa7c
JH		 644 case ADDR_PREFIX_OPCODE:
645 q = ADDR_PREFIX;
646 break;
252b5132 647
3e73aa7c
JH		 648 case DATA_PREFIX_OPCODE:
649 q = DATA_PREFIX;
650 break;
651 }
252b5132
RH		 652
653 if (i.prefix[q])
654 {
655 as_bad (_("same type of prefix used twice"));
656 return 0;
657 }
658
659 i.prefixes += 1;
660 i.prefix[q] = prefix;
661 return ret;
662}
663
664static void
3e73aa7c 665set_code_flag (value)
e5cb08ac 666 int value;
eecb386c 667{
3e73aa7c
JH		 668 flag_code = value;
669 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
670 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
671 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
672 {
673 as_bad (_("64bit mode not supported on this CPU."));
674 }
675 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
676 {
677 as_bad (_("32bit mode not supported on this CPU."));
678 }
eecb386c
AM		 679 stackop_size = '\0';
680}
681
682static void
3e73aa7c
JH		 683set_16bit_gcc_code_flag (new_code_flag)
684 int new_code_flag;
252b5132 685{
3e73aa7c
JH		 686 flag_code = new_code_flag;
687 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
688 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
689 stackop_size = 'l';
252b5132
RH		 690}
691
692static void
693set_intel_syntax (syntax_flag)
eecb386c 694 int syntax_flag;
252b5132
RH		 695{
696 /* Find out if register prefixing is specified. */
697 int ask_naked_reg = 0;
698
699 SKIP_WHITESPACE ();
700 if (! is_end_of_line[(unsigned char) *input_line_pointer])
701 {
702 char *string = input_line_pointer;
703 int e = get_symbol_end ();
704
47926f60 705 if (strcmp (string, "prefix") == 0)
252b5132 706 ask_naked_reg = 1;
47926f60 707 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 708 ask_naked_reg = -1;
709 else
d0b47220 710 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 711 *input_line_pointer = e;
712 }
713 demand_empty_rest_of_line ();
c3332e24 714
252b5132
RH		 715 intel_syntax = syntax_flag;
716
717 if (ask_naked_reg == 0)
718 {
719#ifdef BFD_ASSEMBLER
720 allow_naked_reg = (intel_syntax
24eab124 721 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 722#else
47926f60
KH		 723 /* Conservative default. */
724 allow_naked_reg = 0;
252b5132
RH		 725#endif
726 }
727 else
728 allow_naked_reg = (ask_naked_reg < 0);
729}
730
e413e4e9
AM		 731static void
732set_cpu_arch (dummy)
47926f60 733 int dummy ATTRIBUTE_UNUSED;
e413e4e9 734{
47926f60 735 SKIP_WHITESPACE ();
e413e4e9
AM		 736
737 if (! is_end_of_line[(unsigned char) *input_line_pointer])
738 {
739 char *string = input_line_pointer;
740 int e = get_symbol_end ();
741 int i;
742
743 for (i = 0; cpu_arch[i].name; i++)
744 {
745 if (strcmp (string, cpu_arch[i].name) == 0)
746 {
747 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 748 cpu_arch_flags = (cpu_arch[i].flags
749 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 750 break;
751 }
752 }
753 if (!cpu_arch[i].name)
754 as_bad (_("no such architecture: `%s'"), string);
755
756 *input_line_pointer = e;
757 }
758 else
759 as_bad (_("missing cpu architecture"));
760
fddf5b5b
AM		 761 no_cond_jump_promotion = 0;
762 if (*input_line_pointer == ','
763 && ! is_end_of_line[(unsigned char) input_line_pointer[1]])
764 {
765 char *string = ++input_line_pointer;
766 int e = get_symbol_end ();
767
768 if (strcmp (string, "nojumps") == 0)
769 no_cond_jump_promotion = 1;
770 else if (strcmp (string, "jumps") == 0)
771 ;
772 else
773 as_bad (_("no such architecture modifier: `%s'"), string);
774
775 *input_line_pointer = e;
776 }
777
e413e4e9
AM		 778 demand_empty_rest_of_line ();
779}
780
252b5132
RH		 781const pseudo_typeS md_pseudo_table[] =
782{
252b5132
RH		 783#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
784 {"align", s_align_bytes, 0},
785#else
786 {"align", s_align_ptwo, 0},
e413e4e9
AM		 787#endif
788 {"arch", set_cpu_arch, 0},
789#ifndef I386COFF
790 {"bss", s_bss, 0},
252b5132
RH		 791#endif
792 {"ffloat", float_cons, 'f'},
793 {"dfloat", float_cons, 'd'},
794 {"tfloat", float_cons, 'x'},
795 {"value", cons, 2},
796 {"noopt", s_ignore, 0},
797 {"optim", s_ignore, 0},
3e73aa7c
JH		 798 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
799 {"code16", set_code_flag, CODE_16BIT},
800 {"code32", set_code_flag, CODE_32BIT},
801 {"code64", set_code_flag, CODE_64BIT},
252b5132
RH		 802 {"intel_syntax", set_intel_syntax, 1},
803 {"att_syntax", set_intel_syntax, 0},
316e2c05
RH		 804 {"file", dwarf2_directive_file, 0},
805 {"loc", dwarf2_directive_loc, 0},
252b5132
RH		 806 {0, 0, 0}
807};
808
47926f60 809/* For interface with expression (). */
252b5132
RH		 810extern char *input_line_pointer;
811
47926f60 812/* Hash table for instruction mnemonic lookup. */
252b5132 813static struct hash_control *op_hash;
47926f60
KH		 814
815/* Hash table for register lookup. */
252b5132
RH		 816static struct hash_control *reg_hash;
817\f
b9d79e03
JH		 818#ifdef BFD_ASSEMBLER
819unsigned long
820i386_mach ()
821{
822 if (!strcmp (default_arch, "x86_64"))
823 return bfd_mach_x86_64;
824 else if (!strcmp (default_arch, "i386"))
825 return bfd_mach_i386_i386;
826 else
827 as_fatal (_("Unknown architecture"));
828}
829#endif
830\f
252b5132
RH		 831void
832md_begin ()
833{
834 const char *hash_err;
835
47926f60 836 /* Initialize op_hash hash table. */
252b5132
RH		 837 op_hash = hash_new ();
838
839 {
840 register const template *optab;
841 register templates *core_optab;
842
47926f60
KH		 843 /* Setup for loop. */
844 optab = i386_optab;
252b5132
RH		 845 core_optab = (templates *) xmalloc (sizeof (templates));
846 core_optab->start = optab;
847
848 while (1)
849 {
850 ++optab;
851 if (optab->name == NULL
852 || strcmp (optab->name, (optab - 1)->name) != 0)
853 {
854 /* different name --> ship out current template list;
47926f60 855 add to hash table; & begin anew. */
252b5132
RH		 856 core_optab->end = optab;
857 hash_err = hash_insert (op_hash,
858 (optab - 1)->name,
859 (PTR) core_optab);
860 if (hash_err)
861 {
252b5132
RH		 862 as_fatal (_("Internal Error: Can't hash %s: %s"),
863 (optab - 1)->name,
864 hash_err);
865 }
866 if (optab->name == NULL)
867 break;
868 core_optab = (templates *) xmalloc (sizeof (templates));
869 core_optab->start = optab;
870 }
871 }
872 }
873
47926f60 874 /* Initialize reg_hash hash table. */
252b5132
RH		 875 reg_hash = hash_new ();
876 {
877 register const reg_entry *regtab;
878
879 for (regtab = i386_regtab;
880 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
881 regtab++)
882 {
883 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
884 if (hash_err)
3e73aa7c
JH		 885 as_fatal (_("Internal Error: Can't hash %s: %s"),
886 regtab->reg_name,
887 hash_err);
252b5132
RH		 888 }
889 }
890
47926f60 891 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132
RH		 892 {
893 register int c;
894 register char *p;
895
896 for (c = 0; c < 256; c++)
897 {
898 if (isdigit (c))
899 {
900 digit_chars[c] = c;
901 mnemonic_chars[c] = c;
902 register_chars[c] = c;
903 operand_chars[c] = c;
904 }
905 else if (islower (c))
906 {
907 mnemonic_chars[c] = c;
908 register_chars[c] = c;
909 operand_chars[c] = c;
910 }
911 else if (isupper (c))
912 {
913 mnemonic_chars[c] = tolower (c);
914 register_chars[c] = mnemonic_chars[c];
915 operand_chars[c] = c;
916 }
917
918 if (isalpha (c) || isdigit (c))
919 identifier_chars[c] = c;
920 else if (c >= 128)
921 {
922 identifier_chars[c] = c;
923 operand_chars[c] = c;
924 }
925 }
926
927#ifdef LEX_AT
928 identifier_chars['@'] = '@';
929#endif
252b5132
RH		 930 digit_chars['-'] = '-';
931 identifier_chars['_'] = '_';
932 identifier_chars['.'] = '.';
933
934 for (p = operand_special_chars; *p != '\0'; p++)
935 operand_chars[(unsigned char) *p] = *p;
936 }
937
938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
939 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
940 {
941 record_alignment (text_section, 2);
942 record_alignment (data_section, 2);
943 record_alignment (bss_section, 2);
944 }
945#endif
946}
947
948void
949i386_print_statistics (file)
950 FILE *file;
951{
952 hash_print_statistics (file, "i386 opcode", op_hash);
953 hash_print_statistics (file, "i386 register", reg_hash);
954}
955\f
252b5132
RH		 956#ifdef DEBUG386
957
ce8a8b2f 958/* Debugging routines for md_assemble. */
252b5132
RH		 959static void pi PARAMS ((char *, i386_insn *));
960static void pte PARAMS ((template *));
961static void pt PARAMS ((unsigned int));
962static void pe PARAMS ((expressionS *));
963static void ps PARAMS ((symbolS *));
964
965static void
966pi (line, x)
967 char *line;
968 i386_insn *x;
969{
09f131f2 970 unsigned int i;
252b5132
RH		 971
972 fprintf (stdout, "%s: template ", line);
973 pte (&x->tm);
09f131f2
JH		 974 fprintf (stdout, " address: base %s index %s scale %x\n",
975 x->base_reg ? x->base_reg->reg_name : "none",
976 x->index_reg ? x->index_reg->reg_name : "none",
977 x->log2_scale_factor);
978 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 979 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 980 fprintf (stdout, " sib: base %x index %x scale %x\n",
981 x->sib.base, x->sib.index, x->sib.scale);
982 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
983 x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ);
252b5132
RH		 984 for (i = 0; i < x->operands; i++)
985 {
986 fprintf (stdout, " #%d: ", i + 1);
987 pt (x->types[i]);
988 fprintf (stdout, "\n");
989 if (x->types[i]
3f4438ab 990 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 991 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 992 if (x->types[i] & Imm)
520dc8e8 993 pe (x->op[i].imms);
252b5132 994 if (x->types[i] & Disp)
520dc8e8 995 pe (x->op[i].disps);
252b5132
RH		 996 }
997}
998
999static void
1000pte (t)
1001 template *t;
1002{
09f131f2 1003 unsigned int i;
252b5132 1004 fprintf (stdout, " %d operands ", t->operands);
47926f60 1005 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1006 if (t->extension_opcode != None)
1007 fprintf (stdout, "ext %x ", t->extension_opcode);
1008 if (t->opcode_modifier & D)
1009 fprintf (stdout, "D");
1010 if (t->opcode_modifier & W)
1011 fprintf (stdout, "W");
1012 fprintf (stdout, "\n");
1013 for (i = 0; i < t->operands; i++)
1014 {
1015 fprintf (stdout, " #%d type ", i + 1);
1016 pt (t->operand_types[i]);
1017 fprintf (stdout, "\n");
1018 }
1019}
1020
1021static void
1022pe (e)
1023 expressionS *e;
1024{
24eab124 1025 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1026 fprintf (stdout, " add_number %ld (%lx)\n",
1027 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1028 if (e->X_add_symbol)
1029 {
1030 fprintf (stdout, " add_symbol ");
1031 ps (e->X_add_symbol);
1032 fprintf (stdout, "\n");
1033 }
1034 if (e->X_op_symbol)
1035 {
1036 fprintf (stdout, " op_symbol ");
1037 ps (e->X_op_symbol);
1038 fprintf (stdout, "\n");
1039 }
1040}
1041
1042static void
1043ps (s)
1044 symbolS *s;
1045{
1046 fprintf (stdout, "%s type %s%s",
1047 S_GET_NAME (s),
1048 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1049 segment_name (S_GET_SEGMENT (s)));
1050}
1051
1052struct type_name
1053 {
1054 unsigned int mask;
1055 char *tname;
1056 }
1057
1058type_names[] =
1059{
1060 { Reg8, "r8" },
1061 { Reg16, "r16" },
1062 { Reg32, "r32" },
09f131f2 1063 { Reg64, "r64" },
252b5132
RH		 1064 { Imm8, "i8" },
1065 { Imm8S, "i8s" },
1066 { Imm16, "i16" },
1067 { Imm32, "i32" },
09f131f2
JH		 1068 { Imm32S, "i32s" },
1069 { Imm64, "i64" },
252b5132
RH		 1070 { Imm1, "i1" },
1071 { BaseIndex, "BaseIndex" },
1072 { Disp8, "d8" },
1073 { Disp16, "d16" },
1074 { Disp32, "d32" },
09f131f2
JH		 1075 { Disp32S, "d32s" },
1076 { Disp64, "d64" },
252b5132
RH		 1077 { InOutPortReg, "InOutPortReg" },
1078 { ShiftCount, "ShiftCount" },
1079 { Control, "control reg" },
1080 { Test, "test reg" },
1081 { Debug, "debug reg" },
1082 { FloatReg, "FReg" },
1083 { FloatAcc, "FAcc" },
1084 { SReg2, "SReg2" },
1085 { SReg3, "SReg3" },
1086 { Acc, "Acc" },
1087 { JumpAbsolute, "Jump Absolute" },
1088 { RegMMX, "rMMX" },
3f4438ab 1089 { RegXMM, "rXMM" },
252b5132
RH		 1090 { EsSeg, "es" },
1091 { 0, "" }
1092};
1093
1094static void
1095pt (t)
1096 unsigned int t;
1097{
1098 register struct type_name *ty;
1099
09f131f2
JH		 1100 for (ty = type_names; ty->mask; ty++)
1101 if (t & ty->mask)
1102 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1103 fflush (stdout);
1104}
1105
1106#endif /* DEBUG386 */
1107\f
1108int
1109tc_i386_force_relocation (fixp)
1110 struct fix *fixp;
1111{
1112#ifdef BFD_ASSEMBLER
1113 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1114 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1115 return 1;
1116 return 0;
1117#else
ce8a8b2f 1118 /* For COFF. */
f6af82bd 1119 return fixp->fx_r_type == 7;
252b5132
RH		 1120#endif
1121}
1122
1123#ifdef BFD_ASSEMBLER
252b5132
RH		 1124
1125static bfd_reloc_code_real_type
3e73aa7c 1126reloc (size, pcrel, sign, other)
252b5132
RH		 1127 int size;
1128 int pcrel;
3e73aa7c 1129 int sign;
252b5132
RH		 1130 bfd_reloc_code_real_type other;
1131{
47926f60
KH		 1132 if (other != NO_RELOC)
1133 return other;
252b5132
RH		 1134
1135 if (pcrel)
1136 {
3e73aa7c 1137 if (!sign)
e5cb08ac 1138 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1139 switch (size)
1140 {
1141 case 1: return BFD_RELOC_8_PCREL;
1142 case 2: return BFD_RELOC_16_PCREL;
1143 case 4: return BFD_RELOC_32_PCREL;
1144 }
d0b47220 1145 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1146 }
1147 else
1148 {
3e73aa7c 1149 if (sign)
e5cb08ac 1150 switch (size)
3e73aa7c
JH		 1151 {
1152 case 4: return BFD_RELOC_X86_64_32S;
1153 }
1154 else
1155 switch (size)
1156 {
1157 case 1: return BFD_RELOC_8;
1158 case 2: return BFD_RELOC_16;
1159 case 4: return BFD_RELOC_32;
1160 case 8: return BFD_RELOC_64;
1161 }
1162 as_bad (_("can not do %s %d byte relocation"),
1163 sign ? "signed" : "unsigned", size);
252b5132
RH		 1164 }
1165
bfb32b52 1166 abort ();
252b5132
RH		 1167 return BFD_RELOC_NONE;
1168}
1169
47926f60
KH		 1170/* Here we decide which fixups can be adjusted to make them relative to
1171 the beginning of the section instead of the symbol. Basically we need
1172 to make sure that the dynamic relocations are done correctly, so in
1173 some cases we force the original symbol to be used. */
1174
252b5132 1175int
c0c949c7 1176tc_i386_fix_adjustable (fixP)
47926f60 1177 fixS *fixP;
252b5132 1178{
6d249963 1179#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
79d292aa
ILT		 1180 /* Prevent all adjustments to global symbols, or else dynamic
1181 linking will not work correctly. */
b98ef147
AM		 1182 if (S_IS_EXTERNAL (fixP->fx_addsy)
1183 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 1184 return 0;
1185#endif
ce8a8b2f 1186 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1187 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1188 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1189 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3e73aa7c
JH		 1190 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1191 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1192 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1193 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1194 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1195 return 0;
1196 return 1;
1197}
1198#else
ec56dfb4
L		 1199#define reloc(SIZE,PCREL,SIGN,OTHER) 0
1200#define BFD_RELOC_16 0
1201#define BFD_RELOC_32 0
1202#define BFD_RELOC_16_PCREL 0
1203#define BFD_RELOC_32_PCREL 0
1204#define BFD_RELOC_386_PLT32 0
1205#define BFD_RELOC_386_GOT32 0
1206#define BFD_RELOC_386_GOTOFF 0
1207#define BFD_RELOC_X86_64_PLT32 0
1208#define BFD_RELOC_X86_64_GOT32 0
1209#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1210#endif
1211
47926f60 1212static int intel_float_operand PARAMS ((char *mnemonic));
b4cac588
AM		 1213
1214static int
252b5132
RH		 1215intel_float_operand (mnemonic)
1216 char *mnemonic;
1217{
47926f60 1218 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1219 return 2;
252b5132
RH		 1220
1221 if (mnemonic[0] == 'f')
1222 return 1;
1223
1224 return 0;
1225}
1226
1227/* This is the guts of the machine-dependent assembler. LINE points to a
1228 machine dependent instruction. This function is supposed to emit
1229 the frags/bytes it assembles to. */
1230
1231void
1232md_assemble (line)
1233 char *line;
1234{
47926f60 1235 /* Points to template once we've found it. */
252b5132
RH		 1236 const template *t;
1237
fddf5b5b
AM		 1238 /* Count the size of the instruction generated. Does not include
1239 variable part of jump insns before relax. */
252b5132
RH		 1240 int insn_size = 0;
1241
1242 int j;
1243
1244 char mnemonic[MAX_MNEM_SIZE];
1245
47926f60 1246 /* Initialize globals. */
252b5132
RH		 1247 memset (&i, '\0', sizeof (i));
1248 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1249 i.reloc[j] = NO_RELOC;
252b5132
RH		 1250 memset (disp_expressions, '\0', sizeof (disp_expressions));
1251 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1252 save_stack_p = save_stack;
252b5132
RH		 1253
1254 /* First parse an instruction mnemonic & call i386_operand for the operands.
1255 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1256 start of a (possibly prefixed) mnemonic. */
252b5132
RH		 1257 {
1258 char *l = line;
1259 char *token_start = l;
1260 char *mnem_p;
1261
47926f60 1262 /* Non-zero if we found a prefix only acceptable with string insns. */
252b5132
RH		 1263 const char *expecting_string_instruction = NULL;
1264
1265 while (1)
1266 {
1267 mnem_p = mnemonic;
1268 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1269 {
1270 mnem_p++;
1271 if (mnem_p >= mnemonic + sizeof (mnemonic))
1272 {
e413e4e9 1273 as_bad (_("no such instruction: `%s'"), token_start);
252b5132
RH		 1274 return;
1275 }
1276 l++;
1277 }
1278 if (!is_space_char (*l)
1279 && *l != END_OF_INSN
1280 && *l != PREFIX_SEPARATOR)
1281 {
1282 as_bad (_("invalid character %s in mnemonic"),
1283 output_invalid (*l));
1284 return;
1285 }
1286 if (token_start == l)
1287 {
1288 if (*l == PREFIX_SEPARATOR)
1289 as_bad (_("expecting prefix; got nothing"));
1290 else
1291 as_bad (_("expecting mnemonic; got nothing"));
1292 return;
1293 }
1294
1295 /* Look up instruction (or prefix) via hash table. */
1296 current_templates = hash_find (op_hash, mnemonic);
1297
1298 if (*l != END_OF_INSN
1299 && (! is_space_char (*l) || l[1] != END_OF_INSN)
1300 && current_templates
1301 && (current_templates->start->opcode_modifier & IsPrefix))
1302 {
1303 /* If we are in 16-bit mode, do not allow addr16 or data16.
1304 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1305 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1306 && (((current_templates->start->opcode_modifier & Size32) != 0)
3e73aa7c 1307 ^ (flag_code == CODE_16BIT)))
252b5132
RH		 1308 {
1309 as_bad (_("redundant %s prefix"),
1310 current_templates->start->name);
1311 return;
1312 }
1313 /* Add prefix, checking for repeated prefixes. */
1314 switch (add_prefix (current_templates->start->base_opcode))
1315 {
1316 case 0:
1317 return;
1318 case 2:
47926f60 1319 expecting_string_instruction = current_templates->start->name;
252b5132
RH		 1320 break;
1321 }
1322 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1323 token_start = ++l;
1324 }
1325 else
1326 break;
1327 }
1328
1329 if (!current_templates)
1330 {
24eab124 1331 /* See if we can get a match by trimming off a suffix. */
252b5132
RH		 1332 switch (mnem_p[-1])
1333 {
252b5132
RH		 1334 case WORD_MNEM_SUFFIX:
1335 case BYTE_MNEM_SUFFIX:
3e73aa7c 1336 case QWORD_MNEM_SUFFIX:
252b5132
RH		 1337 i.suffix = mnem_p[-1];
1338 mnem_p[-1] = '\0';
1339 current_templates = hash_find (op_hash, mnemonic);
24eab124 1340 break;
f16b83df
JH		 1341 case SHORT_MNEM_SUFFIX:
1342 case LONG_MNEM_SUFFIX:
1343 if (!intel_syntax)
1344 {
1345 i.suffix = mnem_p[-1];
1346 mnem_p[-1] = '\0';
1347 current_templates = hash_find (op_hash, mnemonic);
1348 }
1349 break;
24eab124 1350
ce8a8b2f 1351 /* Intel Syntax. */
f16b83df 1352 case 'd':
24eab124
AM		 1353 if (intel_syntax)
1354 {
f16b83df
JH		 1355 if (intel_float_operand (mnemonic))
1356 i.suffix = SHORT_MNEM_SUFFIX;
1357 else
1358 i.suffix = LONG_MNEM_SUFFIX;
24eab124
AM		 1359 mnem_p[-1] = '\0';
1360 current_templates = hash_find (op_hash, mnemonic);
24eab124 1361 }
f16b83df 1362 break;
252b5132
RH		 1363 }
1364 if (!current_templates)
1365 {
e413e4e9 1366 as_bad (_("no such instruction: `%s'"), token_start);
252b5132
RH		 1367 return;
1368 }
1369 }
1370
e413e4e9
AM		 1371 /* Check if instruction is supported on specified architecture. */
1372 if (cpu_arch_flags != 0)
1373 {
3e73aa7c
JH		 1374 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1375 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
e413e4e9
AM		 1376 {
1377 as_warn (_("`%s' is not supported on `%s'"),
1378 current_templates->start->name, cpu_arch_name);
1379 }
3e73aa7c 1380 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
e413e4e9
AM		 1381 {
1382 as_warn (_("use .code16 to ensure correct addressing mode"));
1383 }
1384 }
1385
ce8a8b2f 1386 /* Check for rep/repne without a string instruction. */
252b5132
RH		 1387 if (expecting_string_instruction
1388 && !(current_templates->start->opcode_modifier & IsString))
1389 {
1390 as_bad (_("expecting string instruction after `%s'"),
1391 expecting_string_instruction);
1392 return;
1393 }
1394
47926f60 1395 /* There may be operands to parse. */
252b5132
RH		 1396 if (*l != END_OF_INSN)
1397 {
47926f60 1398 /* 1 if operand is pending after ','. */
252b5132
RH		 1399 unsigned int expecting_operand = 0;
1400
47926f60 1401 /* Non-zero if operand parens not balanced. */
252b5132
RH		 1402 unsigned int paren_not_balanced;
1403
1404 do
1405 {
ce8a8b2f 1406 /* Skip optional white space before operand. */
252b5132
RH		 1407 if (is_space_char (*l))
1408 ++l;
1409 if (!is_operand_char (*l) && *l != END_OF_INSN)
1410 {
1411 as_bad (_("invalid character %s before operand %d"),
1412 output_invalid (*l),
1413 i.operands + 1);
1414 return;
1415 }
1416 token_start = l; /* after white space */
1417 paren_not_balanced = 0;
1418 while (paren_not_balanced || *l != ',')
1419 {
1420 if (*l == END_OF_INSN)
1421 {
1422 if (paren_not_balanced)
1423 {
24eab124 1424 if (!intel_syntax)
252b5132
RH		 1425 as_bad (_("unbalanced parenthesis in operand %d."),
1426 i.operands + 1);
24eab124 1427 else
252b5132
RH		 1428 as_bad (_("unbalanced brackets in operand %d."),
1429 i.operands + 1);
1430 return;
1431 }
1432 else
1433 break; /* we are done */
1434 }
1435 else if (!is_operand_char (*l) && !is_space_char (*l))
1436 {
1437 as_bad (_("invalid character %s in operand %d"),
1438 output_invalid (*l),
1439 i.operands + 1);
1440 return;
1441 }
24eab124
AM		 1442 if (!intel_syntax)
1443 {
252b5132
RH		 1444 if (*l == '(')
1445 ++paren_not_balanced;
1446 if (*l == ')')
1447 --paren_not_balanced;
24eab124
AM		 1448 }
1449 else
1450 {
252b5132
RH		 1451 if (*l == '[')
1452 ++paren_not_balanced;
1453 if (*l == ']')
1454 --paren_not_balanced;
24eab124 1455 }
252b5132
RH		 1456 l++;
1457 }
1458 if (l != token_start)
47926f60 1459 { /* Yes, we've read in another operand. */
252b5132
RH		 1460 unsigned int operand_ok;
1461 this_operand = i.operands++;
1462 if (i.operands > MAX_OPERANDS)
1463 {
1464 as_bad (_("spurious operands; (%d operands/instruction max)"),
1465 MAX_OPERANDS);
1466 return;
1467 }
47926f60 1468 /* Now parse operand adding info to 'i' as we go along. */
252b5132
RH		 1469 END_STRING_AND_SAVE (l);
1470
24eab124 1471 if (intel_syntax)
47926f60
KH		 1472 operand_ok =
1473 i386_intel_operand (token_start,
1474 intel_float_operand (mnemonic));
24eab124
AM		 1475 else
1476 operand_ok = i386_operand (token_start);
252b5132 1477
ce8a8b2f 1478 RESTORE_END_STRING (l);
252b5132
RH		 1479 if (!operand_ok)
1480 return;
1481 }
1482 else
1483 {
1484 if (expecting_operand)
1485 {
1486 expecting_operand_after_comma:
1487 as_bad (_("expecting operand after ','; got nothing"));
1488 return;
1489 }
1490 if (*l == ',')
1491 {
1492 as_bad (_("expecting operand before ','; got nothing"));
1493 return;
1494 }
1495 }
1496
ce8a8b2f 1497 /* Now *l must be either ',' or END_OF_INSN. */
252b5132
RH		 1498 if (*l == ',')
1499 {
1500 if (*++l == END_OF_INSN)
ce8a8b2f
AM		 1501 {
1502 /* Just skip it, if it's \n complain. */
252b5132
RH		 1503 goto expecting_operand_after_comma;
1504 }
1505 expecting_operand = 1;
1506 }
1507 }
ce8a8b2f 1508 while (*l != END_OF_INSN);
252b5132
RH		 1509 }
1510 }
1511
1512 /* Now we've parsed the mnemonic into a set of templates, and have the
1513 operands at hand.
1514
1515 Next, we find a template that matches the given insn,
1516 making sure the overlap of the given operands types is consistent
47926f60 1517 with the template operand types. */
252b5132
RH		 1518
1519#define MATCH(overlap, given, template) \
3138f287
AM		 1520 ((overlap & ~JumpAbsolute) \
1521 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
252b5132
RH		 1522
1523 /* If given types r0 and r1 are registers they must be of the same type
1524 unless the expected operand type register overlap is null.
1525 Note that Acc in a template matches every size of reg. */
1526#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1527 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1528 ((g0) & Reg) == ((g1) & Reg) || \
1529 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1530
1531 {
1532 register unsigned int overlap0, overlap1;
252b5132
RH		 1533 unsigned int overlap2;
1534 unsigned int found_reverse_match;
1535 int suffix_check;
1536
cc5ca5ce
AM		 1537 /* All intel opcodes have reversed operands except for "bound" and
1538 "enter". We also don't reverse intersegment "jmp" and "call"
1539 instructions with 2 immediate operands so that the immediate segment
1540 precedes the offset, as it does when in AT&T mode. "enter" and the
1541 intersegment "jmp" and "call" instructions are the only ones that
1542 have two immediate operands. */
520dc8e8 1543 if (intel_syntax && i.operands > 1
cc5ca5ce
AM		 1544 && (strcmp (mnemonic, "bound") != 0)
1545 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
252b5132 1546 {
520dc8e8 1547 union i386_op temp_op;
24eab124 1548 unsigned int temp_type;
f3c180ae 1549 RELOC_ENUM temp_reloc;
24eab124 1550 int xchg1 = 0;
ab9da554 1551 int xchg2 = 0;
252b5132 1552
24eab124
AM		 1553 if (i.operands == 2)
1554 {
1555 xchg1 = 0;
1556 xchg2 = 1;
1557 }
1558 else if (i.operands == 3)
1559 {
1560 xchg1 = 0;
1561 xchg2 = 2;
1562 }
520dc8e8
AM		 1563 temp_type = i.types[xchg2];
1564 i.types[xchg2] = i.types[xchg1];
1565 i.types[xchg1] = temp_type;
1566 temp_op = i.op[xchg2];
1567 i.op[xchg2] = i.op[xchg1];
1568 i.op[xchg1] = temp_op;
1ae12ab7
AM		 1569 temp_reloc = i.reloc[xchg2];
1570 i.reloc[xchg2] = i.reloc[xchg1];
1571 i.reloc[xchg1] = temp_reloc;
36bf8ab9
AM		 1572
1573 if (i.mem_operands == 2)
1574 {
1575 const seg_entry *temp_seg;
1576 temp_seg = i.seg[0];
1577 i.seg[0] = i.seg[1];
1578 i.seg[1] = temp_seg;
1579 }
24eab124 1580 }
773f551c
AM		 1581
1582 if (i.imm_operands)
1583 {
1584 /* Try to ensure constant immediates are represented in the smallest
1585 opcode possible. */
1586 char guess_suffix = 0;
1587 int op;
1588
1589 if (i.suffix)
1590 guess_suffix = i.suffix;
1591 else if (i.reg_operands)
1592 {
1593 /* Figure out a suffix from the last register operand specified.
1594 We can't do this properly yet, ie. excluding InOutPortReg,
1595 but the following works for instructions with immediates.
1596 In any case, we can't set i.suffix yet. */
47926f60 1597 for (op = i.operands; --op >= 0;)
773f551c
AM		 1598 if (i.types[op] & Reg)
1599 {
1600 if (i.types[op] & Reg8)
1601 guess_suffix = BYTE_MNEM_SUFFIX;
1602 else if (i.types[op] & Reg16)
1603 guess_suffix = WORD_MNEM_SUFFIX;
3e73aa7c
JH		 1604 else if (i.types[op] & Reg32)
1605 guess_suffix = LONG_MNEM_SUFFIX;
1606 else if (i.types[op] & Reg64)
1607 guess_suffix = QWORD_MNEM_SUFFIX;
773f551c
AM		 1608 break;
1609 }
1610 }
3e73aa7c 1611 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
726c5dcd
AM		 1612 guess_suffix = WORD_MNEM_SUFFIX;
1613
47926f60 1614 for (op = i.operands; --op >= 0;)
3e73aa7c 1615 if (i.types[op] & Imm)
773f551c 1616 {
3e73aa7c 1617 switch (i.op[op].imms->X_op)
e5cb08ac 1618 {
3e73aa7c
JH		 1619 case O_constant:
1620 /* If a suffix is given, this operand may be shortened. */
1621 switch (guess_suffix)
1622 {
1623 case LONG_MNEM_SUFFIX:
1624 i.types[op] |= Imm32 | Imm64;
1625 break;
1626 case WORD_MNEM_SUFFIX:
1627 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1628 break;
1629 case BYTE_MNEM_SUFFIX:
1630 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1631 break;
1632 }
773f551c 1633
e5cb08ac
KH		 1634 /* If this operand is at most 16 bits, convert it
1635 to a signed 16 bit number before trying to see
1636 whether it will fit in an even smaller size.
1637 This allows a 16-bit operand such as $0xffe0 to
1638 be recognised as within Imm8S range. */
3e73aa7c 1639 if ((i.types[op] & Imm16)
e5cb08ac 1640 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3e73aa7c
JH		 1641 {
1642 i.op[op].imms->X_add_number =
1643 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1644 }
1645 if ((i.types[op] & Imm32)
1646 && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0)
1647 {
1648 i.op[op].imms->X_add_number =
1649 (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1650 }
1651 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1652 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1653 if (guess_suffix == QWORD_MNEM_SUFFIX)
1654 i.types[op] &= ~Imm32;
1655 break;
1656 case O_absent:
1657 case O_register:
bfb32b52 1658 abort ();
3e73aa7c
JH		 1659 /* Symbols and expressions. */
1660 default:
1661 /* Convert symbolic operand to proper sizes for matching. */
1662 switch (guess_suffix)
1663 {
1664 case QWORD_MNEM_SUFFIX:
1665 i.types[op] = Imm64 | Imm32S;
1666 break;
1667 case LONG_MNEM_SUFFIX:
1668 i.types[op] = Imm32 | Imm64;
1669 break;
1670 case WORD_MNEM_SUFFIX:
1671 i.types[op] = Imm16 | Imm32 | Imm64;
1672 break;
1673 break;
1674 case BYTE_MNEM_SUFFIX:
1675 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1676 break;
1677 break;
1678 }
1679 break;
773f551c 1680 }
773f551c
AM		 1681 }
1682 }
1683
45288df1
AM		 1684 if (i.disp_operands)
1685 {
1686 /* Try to use the smallest displacement type too. */
1687 int op;
1688
47926f60 1689 for (op = i.operands; --op >= 0;)
45288df1 1690 if ((i.types[op] & Disp)
1ae12ab7 1691 && i.op[op].disps->X_op == O_constant)
45288df1
AM		 1692 {
1693 offsetT disp = i.op[op].disps->X_add_number;
1694
1695 if (i.types[op] & Disp16)
1696 {
1697 /* We know this operand is at most 16 bits, so
1698 convert to a signed 16 bit number before trying
1699 to see whether it will fit in an even smaller
1700 size. */
47926f60 1701
45288df1
AM		 1702 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1703 }
3e73aa7c
JH		 1704 else if (i.types[op] & Disp32)
1705 {
1706 /* We know this operand is at most 32 bits, so convert to a
1707 signed 32 bit number before trying to see whether it will
1708 fit in an even smaller size. */
1709 disp &= (((offsetT) 2 << 31) - 1);
1710 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1711 }
1712 if (flag_code == CODE_64BIT)
1713 {
1714 if (fits_in_signed_long (disp))
1715 i.types[op] |= Disp32S;
1716 if (fits_in_unsigned_long (disp))
1717 i.types[op] |= Disp32;
1718 }
1719 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1720 && fits_in_signed_byte (disp))
45288df1
AM		 1721 i.types[op] |= Disp8;
1722 }
1723 }
1724
252b5132
RH		 1725 overlap0 = 0;
1726 overlap1 = 0;
1727 overlap2 = 0;
1728 found_reverse_match = 0;
1729 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1730 ? No_bSuf
1731 : (i.suffix == WORD_MNEM_SUFFIX
1732 ? No_wSuf
1733 : (i.suffix == SHORT_MNEM_SUFFIX
1734 ? No_sSuf
1735 : (i.suffix == LONG_MNEM_SUFFIX
24eab124 1736 ? No_lSuf
3e73aa7c
JH		 1737 : (i.suffix == QWORD_MNEM_SUFFIX
1738 ? No_qSuf
1739 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
252b5132
RH		 1740
1741 for (t = current_templates->start;
1742 t < current_templates->end;
1743 t++)
1744 {
47926f60 1745 /* Must have right number of operands. */
252b5132
RH		 1746 if (i.operands != t->operands)
1747 continue;
1748
7f3f1ea2
AM		 1749 /* Check the suffix, except for some instructions in intel mode. */
1750 if ((t->opcode_modifier & suffix_check)
fa2255cb
DN		 1751 && !(intel_syntax
1752 && (t->opcode_modifier & IgnoreSize))
7f3f1ea2
AM		 1753 && !(intel_syntax
1754 && t->base_opcode == 0xd9
ce8a8b2f
AM		 1755 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1756 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
24eab124 1757 continue;
252b5132 1758
e2914f48 1759 /* Do not verify operands when there are none. */
252b5132 1760 else if (!t->operands)
e2914f48
JH		 1761 {
1762 if (t->cpu_flags & ~cpu_arch_flags)
1763 continue;
1764 /* We've found a match; break out of loop. */
1765 break;
e5cb08ac 1766 }
252b5132
RH		 1767
1768 overlap0 = i.types[0] & t->operand_types[0];
1769 switch (t->operands)
1770 {
1771 case 1:
1772 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1773 continue;
1774 break;
1775 case 2:
1776 case 3:
1777 overlap1 = i.types[1] & t->operand_types[1];
1778 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
1779 || !MATCH (overlap1, i.types[1], t->operand_types[1])
1780 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1781 t->operand_types[0],
1782 overlap1, i.types[1],
1783 t->operand_types[1]))
1784 {
47926f60 1785 /* Check if other direction is valid ... */
252b5132
RH		 1786 if ((t->opcode_modifier & (D|FloatD)) == 0)
1787 continue;
1788
47926f60 1789 /* Try reversing direction of operands. */
252b5132
RH		 1790 overlap0 = i.types[0] & t->operand_types[1];
1791 overlap1 = i.types[1] & t->operand_types[0];
1792 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
1793 || !MATCH (overlap1, i.types[1], t->operand_types[0])
1794 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1795 t->operand_types[1],
1796 overlap1, i.types[1],
1797 t->operand_types[0]))
1798 {
47926f60 1799 /* Does not match either direction. */
252b5132
RH		 1800 continue;
1801 }
1802 /* found_reverse_match holds which of D or FloatDR
1803 we've found. */
1804 found_reverse_match = t->opcode_modifier & (D|FloatDR);
252b5132 1805 }
47926f60 1806 /* Found a forward 2 operand match here. */
3e73aa7c 1807 else if (t->operands == 3)
252b5132
RH		 1808 {
1809 /* Here we make use of the fact that there are no
1810 reverse match 3 operand instructions, and all 3
1811 operand instructions only need to be checked for
1812 register consistency between operands 2 and 3. */
1813 overlap2 = i.types[2] & t->operand_types[2];
1814 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
1815 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
1816 t->operand_types[1],
1817 overlap2, i.types[2],
24eab124 1818 t->operand_types[2]))
252b5132 1819
24eab124 1820 continue;
252b5132 1821 }
47926f60 1822 /* Found either forward/reverse 2 or 3 operand match here:
ce8a8b2f 1823 slip through to break. */
252b5132 1824 }
3e73aa7c
JH		 1825 if (t->cpu_flags & ~cpu_arch_flags)
1826 {
1827 found_reverse_match = 0;
1828 continue;
1829 }
47926f60
KH		 1830 /* We've found a match; break out of loop. */
1831 break;
ce8a8b2f 1832 }
252b5132 1833 if (t == current_templates->end)
47926f60
KH		 1834 {
1835 /* We found no match. */
252b5132
RH		 1836 as_bad (_("suffix or operands invalid for `%s'"),
1837 current_templates->start->name);
1838 return;
1839 }
1840
a38cf1db 1841 if (!quiet_warnings)
3138f287 1842 {
a38cf1db
AM		 1843 if (!intel_syntax
1844 && ((i.types[0] & JumpAbsolute)
1845 != (t->operand_types[0] & JumpAbsolute)))
1846 {
1847 as_warn (_("indirect %s without `*'"), t->name);
1848 }
3138f287 1849
a38cf1db
AM		 1850 if ((t->opcode_modifier & (IsPrefix|IgnoreSize))
1851 == (IsPrefix|IgnoreSize))
1852 {
1853 /* Warn them that a data or address size prefix doesn't
1854 affect assembly of the next line of code. */
1855 as_warn (_("stand-alone `%s' prefix"), t->name);
1856 }
252b5132
RH		 1857 }
1858
1859 /* Copy the template we found. */
1860 i.tm = *t;
1861 if (found_reverse_match)
1862 {
7f3f1ea2
AM		 1863 /* If we found a reverse match we must alter the opcode
1864 direction bit. found_reverse_match holds bits to change
1865 (different for int & float insns). */
1866
1867 i.tm.base_opcode ^= found_reverse_match;
1868
252b5132
RH		 1869 i.tm.operand_types[0] = t->operand_types[1];
1870 i.tm.operand_types[1] = t->operand_types[0];
1871 }
1872
d0b47220 1873 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
e5cb08ac
KH		 1874 if (SYSV386_COMPAT
1875 && intel_syntax
1876 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1877 i.tm.base_opcode ^= FloatR;
252b5132
RH		 1878
1879 if (i.tm.opcode_modifier & FWait)
1880 if (! add_prefix (FWAIT_OPCODE))
1881 return;
1882
ce8a8b2f 1883 /* Check string instruction segment overrides. */
252b5132
RH		 1884 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1885 {
1886 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
1887 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
1888 {
1889 if (i.seg[0] != NULL && i.seg[0] != &es)
1890 {
1891 as_bad (_("`%s' operand %d must use `%%es' segment"),
1892 i.tm.name,
1893 mem_op + 1);
1894 return;
1895 }
1896 /* There's only ever one segment override allowed per instruction.
1897 This instruction possibly has a legal segment override on the
1898 second operand, so copy the segment to where non-string
1899 instructions store it, allowing common code. */
1900 i.seg[0] = i.seg[1];
1901 }
1902 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
1903 {
1904 if (i.seg[1] != NULL && i.seg[1] != &es)
1905 {
1906 as_bad (_("`%s' operand %d must use `%%es' segment"),
1907 i.tm.name,
1908 mem_op + 2);
1909 return;
1910 }
1911 }
1912 }
1913
3e73aa7c
JH		 1914 if (i.reg_operands && flag_code < CODE_64BIT)
1915 {
1916 int op;
e5cb08ac 1917 for (op = i.operands; --op >= 0;)
3e73aa7c
JH		 1918 if ((i.types[op] & Reg)
1919 && (i.op[op].regs->reg_flags & (RegRex64|RegRex)))
b96d3a20
JH		 1920 {
1921 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1922 i.op[op].regs->reg_name);
1923 return;
1924 }
3e73aa7c
JH		 1925 }
1926
252b5132
RH		 1927 /* If matched instruction specifies an explicit instruction mnemonic
1928 suffix, use it. */
3e73aa7c 1929 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
252b5132
RH		 1930 {
1931 if (i.tm.opcode_modifier & Size16)
1932 i.suffix = WORD_MNEM_SUFFIX;
3e73aa7c
JH		 1933 else if (i.tm.opcode_modifier & Size64)
1934 i.suffix = QWORD_MNEM_SUFFIX;
252b5132 1935 else
add0c677 1936 i.suffix = LONG_MNEM_SUFFIX;
252b5132
RH		 1937 }
1938 else if (i.reg_operands)
1939 {
1940 /* If there's no instruction mnemonic suffix we try to invent one
47926f60 1941 based on register operands. */
252b5132
RH		 1942 if (!i.suffix)
1943 {
1944 /* We take i.suffix from the last register operand specified,
1945 Destination register type is more significant than source
1946 register type. */
1947 int op;
47926f60 1948 for (op = i.operands; --op >= 0;)
cc5ca5ce
AM		 1949 if ((i.types[op] & Reg)
1950 && !(i.tm.operand_types[op] & InOutPortReg))
252b5132
RH		 1951 {
1952 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
1953 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
3e73aa7c 1954 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
add0c677 1955 LONG_MNEM_SUFFIX);
252b5132
RH		 1956 break;
1957 }
1958 }
1959 else if (i.suffix == BYTE_MNEM_SUFFIX)
1960 {
1961 int op;
47926f60 1962 for (op = i.operands; --op >= 0;)
252b5132
RH		 1963 {
1964 /* If this is an eight bit register, it's OK. If it's
1965 the 16 or 32 bit version of an eight bit register,
47926f60 1966 we will just use the low portion, and that's OK too. */
252b5132
RH		 1967 if (i.types[op] & Reg8)
1968 continue;
1969
47926f60 1970 /* movzx and movsx should not generate this warning. */
24eab124
AM		 1971 if (intel_syntax
1972 && (i.tm.base_opcode == 0xfb7
1973 || i.tm.base_opcode == 0xfb6
3e73aa7c 1974 || i.tm.base_opcode == 0x63
24eab124
AM		 1975 || i.tm.base_opcode == 0xfbe
1976 || i.tm.base_opcode == 0xfbf))
1977 continue;
252b5132 1978
520dc8e8 1979 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
252b5132
RH		 1980#if 0
1981 /* Check that the template allows eight bit regs
1982 This kills insns such as `orb $1,%edx', which
1983 maybe should be allowed. */
1984 && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
1985#endif
1986 )
1987 {
3e73aa7c
JH		 1988 /* Prohibit these changes in the 64bit mode, since
1989 the lowering is more complicated. */
1990 if (flag_code == CODE_64BIT
1991 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1992 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1993 i.op[op].regs->reg_name,
1994 i.suffix);
252b5132 1995#if REGISTER_WARNINGS
a38cf1db
AM		 1996 if (!quiet_warnings
1997 && (i.tm.operand_types[op] & InOutPortReg) == 0)
252b5132 1998 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
520dc8e8
AM		 1999 (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name,
2000 i.op[op].regs->reg_name,
252b5132
RH		 2001 i.suffix);
2002#endif
2003 continue;
2004 }
ce8a8b2f 2005 /* Any other register is bad. */
3f4438ab
AM		 2006 if (i.types[op] & (Reg | RegMMX | RegXMM
2007 | SReg2 | SReg3
2008 | Control | Debug | Test
2009 | FloatReg | FloatAcc))
252b5132
RH		 2010 {
2011 as_bad (_("`%%%s' not allowed with `%s%c'"),
520dc8e8 2012 i.op[op].regs->reg_name,
252b5132
RH		 2013 i.tm.name,
2014 i.suffix);
2015 return;
2016 }
2017 }
2018 }
add0c677 2019 else if (i.suffix == LONG_MNEM_SUFFIX)
252b5132
RH		 2020 {
2021 int op;
47926f60
KH		 2022
2023 for (op = i.operands; --op >= 0;)
252b5132
RH		 2024 /* Reject eight bit registers, except where the template
2025 requires them. (eg. movzb) */
2026 if ((i.types[op] & Reg8) != 0
47926f60 2027 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
252b5132
RH		 2028 {
2029 as_bad (_("`%%%s' not allowed with `%s%c'"),
520dc8e8 2030 i.op[op].regs->reg_name,
252b5132
RH		 2031 i.tm.name,
2032 i.suffix);
2033 return;
2034 }
252b5132 2035 /* Warn if the e prefix on a general reg is missing. */
3e73aa7c 2036 else if ((!quiet_warnings || flag_code == CODE_64BIT)
a38cf1db 2037 && (i.types[op] & Reg16) != 0
252b5132
RH		 2038 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2039 {
3e73aa7c
JH		 2040 /* Prohibit these changes in the 64bit mode, since
2041 the lowering is more complicated. */
2042 if (flag_code == CODE_64BIT)
2043 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2044 i.op[op].regs->reg_name,
2045 i.suffix);
2046#if REGISTER_WARNINGS
2047 else
2048 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2049 (i.op[op].regs + 8)->reg_name,
2050 i.op[op].regs->reg_name,
2051 i.suffix);
252b5132 2052#endif
3e73aa7c
JH		 2053 }
2054 /* Warn if the r prefix on a general reg is missing. */
2055 else if ((i.types[op] & Reg64) != 0
2056 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2057 {
2058 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2059 i.op[op].regs->reg_name,
2060 i.suffix);
2061 }
2062 }
2063 else if (i.suffix == QWORD_MNEM_SUFFIX)
2064 {
2065 int op;
3e73aa7c
JH		 2066
2067 for (op = i.operands; --op >= 0; )
2068 /* Reject eight bit registers, except where the template
2069 requires them. (eg. movzb) */
2070 if ((i.types[op] & Reg8) != 0
2071 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2072 {
2073 as_bad (_("`%%%s' not allowed with `%s%c'"),
2074 i.op[op].regs->reg_name,
2075 i.tm.name,
2076 i.suffix);
2077 return;
2078 }
2079 /* Warn if the e prefix on a general reg is missing. */
2080 else if (((i.types[op] & Reg16) != 0
2081 || (i.types[op] & Reg32) != 0)
2082 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2083 {
2084 /* Prohibit these changes in the 64bit mode, since
2085 the lowering is more complicated. */
2086 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2087 i.op[op].regs->reg_name,
2088 i.suffix);
2089 }
252b5132
RH		 2090 }
2091 else if (i.suffix == WORD_MNEM_SUFFIX)
2092 {
2093 int op;
47926f60 2094 for (op = i.operands; --op >= 0;)
252b5132
RH		 2095 /* Reject eight bit registers, except where the template
2096 requires them. (eg. movzb) */
2097 if ((i.types[op] & Reg8) != 0
2098 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2099 {
2100 as_bad (_("`%%%s' not allowed with `%s%c'"),
520dc8e8 2101 i.op[op].regs->reg_name,
252b5132
RH		 2102 i.tm.name,
2103 i.suffix);
2104 return;
2105 }
252b5132 2106 /* Warn if the e prefix on a general reg is present. */
3e73aa7c 2107 else if ((!quiet_warnings || flag_code == CODE_64BIT)
a38cf1db 2108 && (i.types[op] & Reg32) != 0
252b5132
RH		 2109 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
2110 {
3e73aa7c
JH		 2111 /* Prohibit these changes in the 64bit mode, since
2112 the lowering is more complicated. */
2113 if (flag_code == CODE_64BIT)
2114 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2115 i.op[op].regs->reg_name,
2116 i.suffix);
2117 else
2118#if REGISTER_WARNINGS
2119 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2120 (i.op[op].regs - 8)->reg_name,
2121 i.op[op].regs->reg_name,
2122 i.suffix);
252b5132 2123#endif
3e73aa7c 2124 }
252b5132 2125 }
fa2255cb
DN		 2126 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2127 /* Do nothing if the instruction is going to ignore the prefix. */
2128 ;
252b5132 2129 else
47926f60 2130 abort ();
252b5132 2131 }
eecb386c
AM		 2132 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2133 {
2134 i.suffix = stackop_size;
2135 }
252b5132
RH		 2136 /* Make still unresolved immediate matches conform to size of immediate
2137 given in i.suffix. Note: overlap2 cannot be an immediate! */
3e73aa7c 2138 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
252b5132 2139 && overlap0 != Imm8 && overlap0 != Imm8S
e5cb08ac 2140 && overlap0 != Imm16 && overlap0 != Imm32S
b77a7acd 2141 && overlap0 != Imm32 && overlap0 != Imm64)
252b5132
RH		 2142 {
2143 if (i.suffix)
2144 {
24eab124 2145 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
b77a7acd 2146 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
3e73aa7c 2147 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
252b5132 2148 }
3e73aa7c
JH		 2149 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2150 || overlap0 == (Imm16 | Imm32)
2151 || overlap0 == (Imm16 | Imm32S))
252b5132 2152 {
24eab124 2153 overlap0 =
3e73aa7c 2154 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
252b5132 2155 }
3e73aa7c
JH		 2156 if (overlap0 != Imm8 && overlap0 != Imm8S
2157 && overlap0 != Imm16 && overlap0 != Imm32S
2158 && overlap0 != Imm32 && overlap0 != Imm64)
252b5132
RH		 2159 {
2160 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2161 return;
2162 }
2163 }
3e73aa7c 2164 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
252b5132 2165 && overlap1 != Imm8 && overlap1 != Imm8S
e5cb08ac 2166 && overlap1 != Imm16 && overlap1 != Imm32S
b77a7acd 2167 && overlap1 != Imm32 && overlap1 != Imm64)
252b5132
RH		 2168 {
2169 if (i.suffix)
2170 {
24eab124 2171 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
b77a7acd
AJ		 2172 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2173 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
252b5132 2174 }
3e73aa7c
JH		 2175 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2176 || overlap1 == (Imm16 | Imm32)
2177 || overlap1 == (Imm16 | Imm32S))
252b5132 2178 {
24eab124 2179 overlap1 =
3e73aa7c 2180 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
252b5132 2181 }
3e73aa7c
JH		 2182 if (overlap1 != Imm8 && overlap1 != Imm8S
2183 && overlap1 != Imm16 && overlap1 != Imm32S
2184 && overlap1 != Imm32 && overlap1 != Imm64)
252b5132 2185 {
3e73aa7c 2186 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
252b5132
RH		 2187 return;
2188 }
2189 }
2190 assert ((overlap2 & Imm) == 0);
2191
2192 i.types[0] = overlap0;
2193 if (overlap0 & ImplicitRegister)
2194 i.reg_operands--;
2195 if (overlap0 & Imm1)
ce8a8b2f 2196 i.imm_operands = 0; /* kludge for shift insns. */
252b5132
RH		 2197
2198 i.types[1] = overlap1;
2199 if (overlap1 & ImplicitRegister)
2200 i.reg_operands--;
2201
2202 i.types[2] = overlap2;
2203 if (overlap2 & ImplicitRegister)
2204 i.reg_operands--;
2205
2206 /* Finalize opcode. First, we change the opcode based on the operand
2207 size given by i.suffix: We need not change things for byte insns. */
2208
2209 if (!i.suffix && (i.tm.opcode_modifier & W))
2210 {
2211 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2212 return;
2213 }
2214
ce8a8b2f 2215 /* For movzx and movsx, need to check the register type. */
252b5132 2216 if (intel_syntax
24eab124 2217 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
252b5132 2218 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
24eab124
AM		 2219 {
2220 unsigned int prefix = DATA_PREFIX_OPCODE;
252b5132 2221
520dc8e8 2222 if ((i.op[1].regs->reg_type & Reg16) != 0)
24eab124
AM		 2223 if (!add_prefix (prefix))
2224 return;
2225 }
252b5132
RH		 2226
2227 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2228 {
2229 /* It's not a byte, select word/dword operation. */
2230 if (i.tm.opcode_modifier & W)
2231 {
2232 if (i.tm.opcode_modifier & ShortForm)
2233 i.tm.base_opcode |= 8;
2234 else
2235 i.tm.base_opcode |= 1;
2236 }
2237 /* Now select between word & dword operations via the operand
2238 size prefix, except for instructions that will ignore this
2239 prefix anyway. */
3e73aa7c
JH		 2240 if (i.suffix != QWORD_MNEM_SUFFIX
2241 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
252b5132
RH		 2242 && !(i.tm.opcode_modifier & IgnoreSize))
2243 {
2244 unsigned int prefix = DATA_PREFIX_OPCODE;
2245 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2246 prefix = ADDR_PREFIX_OPCODE;
2247
2248 if (! add_prefix (prefix))
2249 return;
2250 }
3e73aa7c
JH		 2251
2252 /* Set mode64 for an operand. */
2253 if (i.suffix == QWORD_MNEM_SUFFIX
2254 && !(i.tm.opcode_modifier & NoRex64))
b96d3a20 2255 {
3e73aa7c 2256 i.rex.mode64 = 1;
b96d3a20
JH		 2257 if (flag_code < CODE_64BIT)
2258 {
e5cb08ac
KH		 2259 as_bad (_("64bit operations available only in 64bit modes."));
2260 return;
b96d3a20
JH		 2261 }
2262 }
3e73aa7c 2263
252b5132 2264 /* Size floating point instruction. */
f16b83df 2265 if (i.suffix == LONG_MNEM_SUFFIX)
252b5132
RH		 2266 {
2267 if (i.tm.opcode_modifier & FloatMF)
2268 i.tm.base_opcode ^= 4;
2269 }
252b5132
RH		 2270 }
2271
3f4438ab 2272 if (i.tm.opcode_modifier & ImmExt)
252b5132 2273 {
3f4438ab
AM		 2274 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2275 opcode suffix which is coded in the same place as an 8-bit
2276 immediate field would be. Here we fake an 8-bit immediate
2277 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132
RH		 2278
2279 expressionS *exp;
2280
47926f60 2281 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132
RH		 2282
2283 exp = &im_expressions[i.imm_operands++];
520dc8e8 2284 i.op[i.operands].imms = exp;
252b5132
RH		 2285 i.types[i.operands++] = Imm8;
2286 exp->X_op = O_constant;
2287 exp->X_add_number = i.tm.extension_opcode;
2288 i.tm.extension_opcode = None;
2289 }
2290
47926f60 2291 /* For insns with operands there are more diddles to do to the opcode. */
252b5132
RH		 2292 if (i.operands)
2293 {
24eab124 2294 /* Default segment register this instruction will use
252b5132
RH		 2295 for memory accesses. 0 means unknown.
2296 This is only for optimizing out unnecessary segment overrides. */
2297 const seg_entry *default_seg = 0;
2298
252b5132
RH		 2299 /* The imul $imm, %reg instruction is converted into
2300 imul $imm, %reg, %reg, and the clr %reg instruction
2301 is converted into xor %reg, %reg. */
2302 if (i.tm.opcode_modifier & regKludge)
2303 {
2304 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
47926f60
KH		 2305 /* Pretend we saw the extra register operand. */
2306 assert (i.op[first_reg_op + 1].regs == 0);
2307 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2308 i.types[first_reg_op + 1] = i.types[first_reg_op];
252b5132
RH		 2309 i.reg_operands = 2;
2310 }
2311
2312 if (i.tm.opcode_modifier & ShortForm)
2313 {
47926f60 2314 /* The register or float register operand is in operand 0 or 1. */
252b5132 2315 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
47926f60 2316 /* Register goes in low 3 bits of opcode. */
520dc8e8 2317 i.tm.base_opcode |= i.op[op].regs->reg_num;
3e73aa7c 2318 if (i.op[op].regs->reg_flags & RegRex)
e5cb08ac 2319 i.rex.extZ = 1;
a38cf1db 2320 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
252b5132
RH		 2321 {
2322 /* Warn about some common errors, but press on regardless.
2323 The first case can be generated by gcc (<= 2.8.1). */
2324 if (i.operands == 2)
2325 {
47926f60 2326 /* Reversed arguments on faddp, fsubp, etc. */
252b5132 2327 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
520dc8e8
AM		 2328 i.op[1].regs->reg_name,
2329 i.op[0].regs->reg_name);
252b5132
RH		 2330 }
2331 else
2332 {
47926f60 2333 /* Extraneous `l' suffix on fp insn. */
252b5132 2334 as_warn (_("translating to `%s %%%s'"), i.tm.name,
520dc8e8 2335 i.op[0].regs->reg_name);
252b5132
RH		 2336 }
2337 }
2338 }
2339 else if (i.tm.opcode_modifier & Modrm)
2340 {
2341 /* The opcode is completed (modulo i.tm.extension_opcode which
2342 must be put into the modrm byte).
2343 Now, we make the modrm & index base bytes based on all the
47926f60 2344 info we've collected. */
252b5132
RH		 2345
2346 /* i.reg_operands MUST be the number of real register operands;
47926f60 2347 implicit registers do not count. */
252b5132
RH		 2348 if (i.reg_operands == 2)
2349 {
2350 unsigned int source, dest;
2351 source = ((i.types[0]
3f4438ab
AM		 2352 & (Reg | RegMMX | RegXMM
2353 | SReg2 | SReg3
2354 | Control | Debug | Test))
252b5132
RH		 2355 ? 0 : 1);
2356 dest = source + 1;
2357
252b5132 2358 i.rm.mode = 3;
3f4438ab
AM		 2359 /* One of the register operands will be encoded in the
2360 i.tm.reg field, the other in the combined i.tm.mode
2361 and i.tm.regmem fields. If no form of this
2362 instruction supports a memory destination operand,
2363 then we assume the source operand may sometimes be
2364 a memory operand and so we need to store the
2365 destination in the i.rm.reg field. */
2366 if ((i.tm.operand_types[dest] & AnyMem) == 0)
252b5132 2367 {
520dc8e8
AM		 2368 i.rm.reg = i.op[dest].regs->reg_num;
2369 i.rm.regmem = i.op[source].regs->reg_num;
3e73aa7c 2370 if (i.op[dest].regs->reg_flags & RegRex)
e5cb08ac 2371 i.rex.extX = 1;
3e73aa7c 2372 if (i.op[source].regs->reg_flags & RegRex)
e5cb08ac 2373 i.rex.extZ = 1;
252b5132
RH		 2374 }
2375 else
2376 {
520dc8e8
AM		 2377 i.rm.reg = i.op[source].regs->reg_num;
2378 i.rm.regmem = i.op[dest].regs->reg_num;
3e73aa7c 2379 if (i.op[dest].regs->reg_flags & RegRex)
e5cb08ac 2380 i.rex.extZ = 1;
3e73aa7c 2381 if (i.op[source].regs->reg_flags & RegRex)
e5cb08ac 2382 i.rex.extX = 1;
252b5132
RH		 2383 }
2384 }
2385 else
47926f60 2386 { /* If it's not 2 reg operands... */
252b5132
RH		 2387 if (i.mem_operands)
2388 {
2389 unsigned int fake_zero_displacement = 0;
2390 unsigned int op = ((i.types[0] & AnyMem)
2391 ? 0
2392 : (i.types[1] & AnyMem) ? 1 : 2);
2393
2394 default_seg = &ds;
2395
2396 if (! i.base_reg)
2397 {
2398 i.rm.mode = 0;
2399 if (! i.disp_operands)
2400 fake_zero_displacement = 1;
2401 if (! i.index_reg)
2402 {
47926f60 2403 /* Operand is just <disp> */
3e73aa7c 2404 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
252b5132
RH		 2405 {
2406 i.rm.regmem = NO_BASE_REGISTER_16;
2407 i.types[op] &= ~Disp;
2408 i.types[op] |= Disp16;
2409 }
3e73aa7c 2410 else if (flag_code != CODE_64BIT)
252b5132
RH		 2411 {
2412 i.rm.regmem = NO_BASE_REGISTER;
2413 i.types[op] &= ~Disp;
2414 i.types[op] |= Disp32;
2415 }
3e73aa7c
JH		 2416 else
2417 {
e5cb08ac
KH		 2418 /* 64bit mode overwrites the 32bit
2419 absolute addressing by RIP relative
2420 addressing and absolute addressing
2421 is encoded by one of the redundant
2422 SIB forms. */
3e73aa7c
JH		 2423
2424 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2425 i.sib.base = NO_BASE_REGISTER;
2426 i.sib.index = NO_INDEX_REGISTER;
2427 i.types[op] &= ~Disp;
2428 i.types[op] |= Disp32S;
2429 }
252b5132 2430 }
47926f60 2431 else /* ! i.base_reg && i.index_reg */
252b5132
RH		 2432 {
2433 i.sib.index = i.index_reg->reg_num;
2434 i.sib.base = NO_BASE_REGISTER;
2435 i.sib.scale = i.log2_scale_factor;
2436 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2437 i.types[op] &= ~Disp;
3e73aa7c
JH		 2438 if (flag_code != CODE_64BIT)
2439 i.types[op] |= Disp32; /* Must be 32 bit */
2440 else
2441 i.types[op] |= Disp32S;
2442 if (i.index_reg->reg_flags & RegRex)
e5cb08ac 2443 i.rex.extY = 1;
252b5132
RH		 2444 }
2445 }
3e73aa7c
JH		 2446 /* RIP addressing for 64bit mode. */
2447 else if (i.base_reg->reg_type == BaseIndex)
2448 {
2449 i.rm.regmem = NO_BASE_REGISTER;
2450 i.types[op] &= ~Disp;
2451 i.types[op] |= Disp32S;
2452 i.flags[op] = Operand_PCrel;
2453 }
252b5132
RH		 2454 else if (i.base_reg->reg_type & Reg16)
2455 {
2456 switch (i.base_reg->reg_num)
2457 {
47926f60 2458 case 3: /* (%bx) */
252b5132
RH		 2459 if (! i.index_reg)
2460 i.rm.regmem = 7;
47926f60 2461 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
252b5132
RH		 2462 i.rm.regmem = i.index_reg->reg_num - 6;
2463 break;
47926f60 2464 case 5: /* (%bp) */
252b5132
RH		 2465 default_seg = &ss;
2466 if (! i.index_reg)
2467 {
2468 i.rm.regmem = 6;
2469 if ((i.types[op] & Disp) == 0)
2470 {
47926f60 2471 /* fake (%bp) into 0(%bp) */
252b5132
RH		 2472 i.types[op] |= Disp8;
2473 fake_zero_displacement = 1;
2474 }
2475 }
47926f60 2476 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
252b5132
RH		 2477 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2478 break;
47926f60 2479 default: /* (%si) -> 4 or (%di) -> 5 */
252b5132
RH		 2480 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2481 }
2482 i.rm.mode = mode_from_disp_size (i.types[op]);
2483 }
3e73aa7c 2484 else /* i.base_reg and 32/64 bit mode */
252b5132 2485 {
3e73aa7c
JH		 2486 if (flag_code == CODE_64BIT
2487 && (i.types[op] & Disp))
2488 {
2489 if (i.types[op] & Disp8)
2490 i.types[op] = Disp8 | Disp32S;
2491 else
2492 i.types[op] = Disp32S;
2493 }
252b5132 2494 i.rm.regmem = i.base_reg->reg_num;
3e73aa7c 2495 if (i.base_reg->reg_flags & RegRex)
e5cb08ac 2496 i.rex.extZ = 1;
252b5132 2497 i.sib.base = i.base_reg->reg_num;
3e73aa7c
JH		 2498 /* x86-64 ignores REX prefix bit here to avoid
2499 decoder complications. */
2500 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
252b5132
RH		 2501 {
2502 default_seg = &ss;
2503 if (i.disp_operands == 0)
2504 {
2505 fake_zero_displacement = 1;
2506 i.types[op] |= Disp8;
2507 }
2508 }
2509 else if (i.base_reg->reg_num == ESP_REG_NUM)
2510 {
2511 default_seg = &ss;
2512 }
2513 i.sib.scale = i.log2_scale_factor;
2514 if (! i.index_reg)
2515 {
2516 /* <disp>(%esp) becomes two byte modrm
2517 with no index register. We've already
2518 stored the code for esp in i.rm.regmem
2519 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2520 base register besides %esp will not use
2521 the extra modrm byte. */
2522 i.sib.index = NO_INDEX_REGISTER;
2523#if ! SCALE1_WHEN_NO_INDEX
2524 /* Another case where we force the second
2525 modrm byte. */
2526 if (i.log2_scale_factor)
2527 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2528#endif
2529 }
2530 else
2531 {
2532 i.sib.index = i.index_reg->reg_num;
2533 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3e73aa7c 2534 if (i.index_reg->reg_flags & RegRex)
e5cb08ac 2535 i.rex.extY = 1;
252b5132
RH		 2536 }
2537 i.rm.mode = mode_from_disp_size (i.types[op]);
2538 }
2539
2540 if (fake_zero_displacement)
2541 {
2542 /* Fakes a zero displacement assuming that i.types[op]
47926f60 2543 holds the correct displacement size. */
b4cac588
AM		 2544 expressionS *exp;
2545
520dc8e8 2546 assert (i.op[op].disps == 0);
252b5132 2547 exp = &disp_expressions[i.disp_operands++];
520dc8e8 2548 i.op[op].disps = exp;
252b5132
RH		 2549 exp->X_op = O_constant;
2550 exp->X_add_number = 0;
2551 exp->X_add_symbol = (symbolS *) 0;
2552 exp->X_op_symbol = (symbolS *) 0;
2553 }
2554 }
2555
2556 /* Fill in i.rm.reg or i.rm.regmem field with register
2557 operand (if any) based on i.tm.extension_opcode.
2558 Again, we must be careful to make sure that
2559 segment/control/debug/test/MMX registers are coded
47926f60 2560 into the i.rm.reg field. */
252b5132
RH		 2561 if (i.reg_operands)
2562 {
2563 unsigned int op =
2564 ((i.types[0]
3f4438ab
AM		 2565 & (Reg | RegMMX | RegXMM
2566 | SReg2 | SReg3
2567 | Control | Debug | Test))
252b5132
RH		 2568 ? 0
2569 : ((i.types[1]
3f4438ab
AM		 2570 & (Reg | RegMMX | RegXMM
2571 | SReg2 | SReg3
2572 | Control | Debug | Test))
252b5132
RH		 2573 ? 1
2574 : 2));
2575 /* If there is an extension opcode to put here, the
47926f60 2576 register number must be put into the regmem field. */
252b5132 2577 if (i.tm.extension_opcode != None)
3e73aa7c
JH		 2578 {
2579 i.rm.regmem = i.op[op].regs->reg_num;
2580 if (i.op[op].regs->reg_flags & RegRex)
e5cb08ac 2581 i.rex.extZ = 1;
3e73aa7c 2582 }
252b5132 2583 else
3e73aa7c
JH		 2584 {
2585 i.rm.reg = i.op[op].regs->reg_num;
2586 if (i.op[op].regs->reg_flags & RegRex)
e5cb08ac 2587 i.rex.extX = 1;
3e73aa7c 2588 }
252b5132
RH		 2589
2590 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2591 we must set it to 3 to indicate this is a register
2592 operand in the regmem field. */
2593 if (!i.mem_operands)
2594 i.rm.mode = 3;
2595 }
2596
47926f60 2597 /* Fill in i.rm.reg field with extension opcode (if any). */
252b5132
RH		 2598 if (i.tm.extension_opcode != None)
2599 i.rm.reg = i.tm.extension_opcode;
2600 }
2601 }
2602 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2603 {
47926f60
KH		 2604 if (i.tm.base_opcode == POP_SEG_SHORT
2605 && i.op[0].regs->reg_num == 1)
252b5132
RH		 2606 {
2607 as_bad (_("you can't `pop %%cs'"));
2608 return;
2609 }
520dc8e8 2610 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3e73aa7c
JH		 2611 if (i.op[0].regs->reg_flags & RegRex)
2612 i.rex.extZ = 1;
252b5132
RH		 2613 }
2614 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
2615 {
2616 default_seg = &ds;
2617 }
2618 else if ((i.tm.opcode_modifier & IsString) != 0)
2619 {
2620 /* For the string instructions that allow a segment override
2621 on one of their operands, the default segment is ds. */
2622 default_seg = &ds;
2623 }
2624
2625 /* If a segment was explicitly specified,
2626 and the specified segment is not the default,
2627 use an opcode prefix to select it.
2628 If we never figured out what the default segment is,
2629 then default_seg will be zero at this point,
2630 and the specified segment prefix will always be used. */
2631 if ((i.seg[0]) && (i.seg[0] != default_seg))
2632 {
2633 if (! add_prefix (i.seg[0]->seg_prefix))
2634 return;
2635 }
2636 }
a38cf1db 2637 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
252b5132 2638 {
24eab124
AM		 2639 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2640 as_warn (_("translating to `%sp'"), i.tm.name);
252b5132
RH		 2641 }
2642 }
2643
47926f60 2644 /* Handle conversion of 'int $3' --> special int3 insn. */
520dc8e8 2645 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
252b5132
RH		 2646 {
2647 i.tm.base_opcode = INT3_OPCODE;
2648 i.imm_operands = 0;
2649 }
2650
2f66722d 2651 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
520dc8e8 2652 && i.op[0].disps->X_op == O_constant)
2f66722d
AM		 2653 {
2654 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2655 the absolute address given by the constant. Since ix86 jumps and
2656 calls are pc relative, we need to generate a reloc. */
520dc8e8
AM		 2657 i.op[0].disps->X_add_symbol = &abs_symbol;
2658 i.op[0].disps->X_op = O_symbol;
2f66722d
AM		 2659 }
2660
3e73aa7c
JH		 2661 if (i.tm.opcode_modifier & Rex64)
2662 i.rex.mode64 = 1;
2663
2664 /* For 8bit registers we would need an empty rex prefix.
2665 Also in the case instruction is already having prefix,
2666 we need to convert old registers to new ones. */
2667
2668 if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64))
2669 || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64))
2670 || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2671 && ((i.types[0] & Reg8) || (i.types[1] & Reg8))))
2672 {
2673 int x;
e5cb08ac 2674 i.rex.empty = 1;
3e73aa7c
JH		 2675 for (x = 0; x < 2; x++)
2676 {
2677 /* Look for 8bit operand that does use old registers. */
2678 if (i.types[x] & Reg8
2679 && !(i.op[x].regs->reg_flags & RegRex64))
2680 {
2681 /* In case it is "hi" register, give up. */
2682 if (i.op[x].regs->reg_num > 3)
2683 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2684 i.op[x].regs->reg_name);
2685
2686 /* Otherwise it is equivalent to the extended register.
2687 Since the encoding don't change this is merely cosmetical
2688 cleanup for debug output. */
2689
2690 i.op[x].regs = i.op[x].regs + 8;
2691 }
2692 }
2693 }
2694
2695 if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2696 add_prefix (0x40
2697 | (i.rex.mode64 ? 8 : 0)
2698 | (i.rex.extX ? 4 : 0)
2699 | (i.rex.extY ? 2 : 0)
2700 | (i.rex.extZ ? 1 : 0));
2701
47926f60 2702 /* We are ready to output the insn. */
252b5132
RH		 2703 {
2704 register char *p;
2705
47926f60 2706 /* Output jumps. */
252b5132
RH		 2707 if (i.tm.opcode_modifier & Jump)
2708 {
a217f122
AM		 2709 int code16;
2710 int prefix;
252b5132 2711
a217f122 2712 code16 = 0;
3e73aa7c 2713 if (flag_code == CODE_16BIT)
a217f122
AM		 2714 code16 = CODE16;
2715
2716 prefix = 0;
2717 if (i.prefix[DATA_PREFIX])
252b5132 2718 {
a217f122 2719 prefix = 1;
252b5132 2720 i.prefixes -= 1;
a217f122 2721 code16 ^= CODE16;
252b5132 2722 }
3e73aa7c
JH		 2723 if (i.prefix[REX_PREFIX])
2724 {
2725 prefix++;
e5cb08ac 2726 i.prefixes--;
3e73aa7c 2727 }
252b5132 2728
a217f122 2729 if (i.prefixes != 0 && !intel_syntax)
252b5132
RH		 2730 as_warn (_("skipping prefixes on this instruction"));
2731
2f66722d
AM		 2732 /* It's always a symbol; End frag & setup for relax.
2733 Make sure there is enough room in this frag for the largest
2734 instruction we may generate in md_convert_frag. This is 2
2735 bytes for the opcode and room for the prefix and largest
2736 displacement. */
fddf5b5b 2737 frag_grow (prefix + 2 + 4);
2f66722d
AM		 2738 insn_size += prefix + 1;
2739 /* Prefix and 1 opcode byte go in fr_fix. */
2740 p = frag_more (prefix + 1);
3e73aa7c 2741 if (i.prefix[DATA_PREFIX])
2f66722d 2742 *p++ = DATA_PREFIX_OPCODE;
3e73aa7c
JH		 2743 if (i.prefix[REX_PREFIX])
2744 *p++ = i.prefix[REX_PREFIX];
2f66722d 2745 *p = i.tm.base_opcode;
ee7fcc42
AM		 2746 /* 1 possible extra opcode + displacement go in var part.
2747 Pass reloc in fr_var. */
2f66722d 2748 frag_var (rs_machine_dependent,
fddf5b5b 2749 1 + 4,
1ae12ab7 2750 i.reloc[0],
2f66722d
AM		 2751 ((unsigned char) *p == JUMP_PC_RELATIVE
2752 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
fddf5b5b
AM		 2753 : ((cpu_arch_flags & Cpu386) != 0
2754 ? ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16
2755 : ENCODE_RELAX_STATE (COND_JUMP86, SMALL) | code16)),
520dc8e8
AM		 2756 i.op[0].disps->X_add_symbol,
2757 i.op[0].disps->X_add_number,
2f66722d 2758 p);
252b5132
RH		 2759 }
2760 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
2761 {
a217f122 2762 int size;
252b5132 2763
a217f122 2764 if (i.tm.opcode_modifier & JumpByte)
252b5132 2765 {
a217f122
AM		 2766 /* This is a loop or jecxz type instruction. */
2767 size = 1;
252b5132
RH		 2768 if (i.prefix[ADDR_PREFIX])
2769 {
2770 insn_size += 1;
2771 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2772 i.prefixes -= 1;
2773 }
2774 }
2775 else
2776 {
a217f122
AM		 2777 int code16;
2778
2779 code16 = 0;
3e73aa7c 2780 if (flag_code == CODE_16BIT)
a217f122 2781 code16 = CODE16;
252b5132
RH		 2782
2783 if (i.prefix[DATA_PREFIX])
2784 {
2785 insn_size += 1;
2786 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2787 i.prefixes -= 1;
a217f122 2788 code16 ^= CODE16;
252b5132 2789 }
252b5132 2790
a217f122 2791 size = 4;
252b5132
RH		 2792 if (code16)
2793 size = 2;
2794 }
2795
3e73aa7c
JH		 2796 if (i.prefix[REX_PREFIX])
2797 {
2798 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
2799 insn_size++;
2800 i.prefixes -= 1;
2801 }
2802
a217f122 2803 if (i.prefixes != 0 && !intel_syntax)
252b5132
RH		 2804 as_warn (_("skipping prefixes on this instruction"));
2805
2806 if (fits_in_unsigned_byte (i.tm.base_opcode))
2807 {
2808 insn_size += 1 + size;
2809 p = frag_more (1 + size);
2810 }
2811 else
2812 {
47926f60 2813 /* Opcode can be at most two bytes. */
a217f122 2814 insn_size += 2 + size;
252b5132
RH		 2815 p = frag_more (2 + size);
2816 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2817 }
2818 *p++ = i.tm.base_opcode & 0xff;
2819
2f66722d 2820 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1ae12ab7 2821 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
252b5132
RH		 2822 }
2823 else if (i.tm.opcode_modifier & JumpInterSegment)
2824 {
2825 int size;
a217f122
AM		 2826 int prefix;
2827 int code16;
252b5132 2828
a217f122 2829 code16 = 0;
3e73aa7c 2830 if (flag_code == CODE_16BIT)
a217f122
AM		 2831 code16 = CODE16;
2832
2833 prefix = 0;
2834 if (i.prefix[DATA_PREFIX])
252b5132 2835 {
a217f122 2836 prefix = 1;
252b5132 2837 i.prefixes -= 1;
a217f122 2838 code16 ^= CODE16;
252b5132 2839 }
3e73aa7c
JH		 2840 if (i.prefix[REX_PREFIX])
2841 {
2842 prefix++;
2843 i.prefixes -= 1;
2844 }
252b5132
RH		 2845
2846 size = 4;
252b5132 2847 if (code16)
f6af82bd 2848 size = 2;
252b5132 2849
a217f122 2850 if (i.prefixes != 0 && !intel_syntax)
252b5132
RH		 2851 as_warn (_("skipping prefixes on this instruction"));
2852
47926f60
KH		 2853 /* 1 opcode; 2 segment; offset */
2854 insn_size += prefix + 1 + 2 + size;
252b5132 2855 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c
JH		 2856
2857 if (i.prefix[DATA_PREFIX])
252b5132 2858 *p++ = DATA_PREFIX_OPCODE;
3e73aa7c
JH		 2859
2860 if (i.prefix[REX_PREFIX])
2861 *p++ = i.prefix[REX_PREFIX];
2862
252b5132 2863 *p++ = i.tm.base_opcode;
520dc8e8 2864 if (i.op[1].imms->X_op == O_constant)
252b5132 2865 {
847f7ad4 2866 offsetT n = i.op[1].imms->X_add_number;
252b5132 2867
773f551c
AM		 2868 if (size == 2
2869 && !fits_in_unsigned_word (n)
2870 && !fits_in_signed_word (n))
252b5132
RH		 2871 {
2872 as_bad (_("16-bit jump out of range"));
2873 return;
2874 }
847f7ad4 2875 md_number_to_chars (p, n, size);
252b5132
RH		 2876 }
2877 else
2878 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1ae12ab7 2879 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
520dc8e8 2880 if (i.op[0].imms->X_op != O_constant)
252b5132
RH		 2881 as_bad (_("can't handle non absolute segment in `%s'"),
2882 i.tm.name);
520dc8e8 2883 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
252b5132
RH		 2884 }
2885 else
2886 {
47926f60 2887 /* Output normal instructions here. */
252b5132
RH		 2888 unsigned char *q;
2889
7bc70a8e
JH		 2890 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2891 byte for the SSE instructions to specify prefix they require. */
2892 if (i.tm.base_opcode & 0xff0000)
2893 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
2894
47926f60 2895 /* The prefix bytes. */
252b5132
RH		 2896 for (q = i.prefix;
2897 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
2898 q++)
2899 {
2900 if (*q)
2901 {
2902 insn_size += 1;
2903 p = frag_more (1);
2904 md_number_to_chars (p, (valueT) *q, 1);
2905 }
2906 }
2907
47926f60 2908 /* Now the opcode; be careful about word order here! */
252b5132
RH		 2909 if (fits_in_unsigned_byte (i.tm.base_opcode))
2910 {
2911 insn_size += 1;
2912 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
2913 }
7bc70a8e 2914 else
252b5132
RH		 2915 {
2916 insn_size += 2;
2917 p = frag_more (2);
47926f60 2918 /* Put out high byte first: can't use md_number_to_chars! */
252b5132
RH		 2919 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2920 *p = i.tm.base_opcode & 0xff;
2921 }
252b5132
RH		 2922
2923 /* Now the modrm byte and sib byte (if present). */
2924 if (i.tm.opcode_modifier & Modrm)
2925 {
2926 insn_size += 1;
2927 p = frag_more (1);
2928 md_number_to_chars (p,
2929 (valueT) (i.rm.regmem << 0
2930 | i.rm.reg << 3
2931 | i.rm.mode << 6),
2932 1);
2933 /* If i.rm.regmem == ESP (4)
2934 && i.rm.mode != (Register mode)
2935 && not 16 bit
2936 ==> need second modrm byte. */
2937 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
2938 && i.rm.mode != 3
2939 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
2940 {
2941 insn_size += 1;
2942 p = frag_more (1);
2943 md_number_to_chars (p,
2944 (valueT) (i.sib.base << 0
2945 | i.sib.index << 3
2946 | i.sib.scale << 6),
2947 1);
2948 }
2949 }
2950
2951 if (i.disp_operands)
2952 {
2953 register unsigned int n;
2954
2955 for (n = 0; n < i.operands; n++)
2956 {
520dc8e8 2957 if (i.types[n] & Disp)
252b5132 2958 {
520dc8e8 2959 if (i.op[n].disps->X_op == O_constant)
252b5132 2960 {
847f7ad4
AM		 2961 int size;
2962 offsetT val;
b4cac588 2963
847f7ad4 2964 size = 4;
3e73aa7c 2965 if (i.types[n] & (Disp8 | Disp16 | Disp64))
252b5132 2966 {
b4cac588 2967 size = 2;
b4cac588 2968 if (i.types[n] & Disp8)
847f7ad4 2969 size = 1;
3e73aa7c
JH		 2970 if (i.types[n] & Disp64)
2971 size = 8;
252b5132 2972 }
847f7ad4
AM		 2973 val = offset_in_range (i.op[n].disps->X_add_number,
2974 size);
b4cac588
AM		 2975 insn_size += size;
2976 p = frag_more (size);
847f7ad4 2977 md_number_to_chars (p, val, size);
252b5132 2978 }
252b5132 2979 else
520dc8e8
AM		 2980 {
2981 int size = 4;
3e73aa7c
JH		 2982 int sign = 0;
2983 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
2984
2985 /* The PC relative address is computed relative
2986 to the instruction boundary, so in case immediate
2987 fields follows, we need to adjust the value. */
2988 if (pcrel && i.imm_operands)
2989 {
2990 int imm_size = 4;
2991 register unsigned int n1;
2992
2993 for (n1 = 0; n1 < i.operands; n1++)
2994 if (i.types[n1] & Imm)
2995 {
2996 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
2997 {
2998 imm_size = 2;
2999 if (i.types[n1] & (Imm8 | Imm8S))
3000 imm_size = 1;
3001 if (i.types[n1] & Imm64)
3002 imm_size = 8;
3003 }
3004 break;
3005 }
3006 /* We should find the immediate. */
3007 if (n1 == i.operands)
bfb32b52 3008 abort ();
3e73aa7c
JH		 3009 i.op[n].disps->X_add_number -= imm_size;
3010 }
520dc8e8 3011
3e73aa7c
JH		 3012 if (i.types[n] & Disp32S)
3013 sign = 1;
3014
e5cb08ac 3015 if (i.types[n] & (Disp16 | Disp64))
3e73aa7c
JH		 3016 {
3017 size = 2;
3018 if (i.types[n] & Disp64)
3019 size = 8;
3020 }
520dc8e8
AM		 3021
3022 insn_size += size;
3023 p = frag_more (size);
3024 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3e73aa7c 3025 i.op[n].disps, pcrel,
1ae12ab7 3026 reloc (size, pcrel, sign, i.reloc[n]));
252b5132
RH		 3027 }
3028 }
3029 }
ce8a8b2f 3030 }
252b5132 3031
47926f60 3032 /* Output immediate. */
252b5132
RH		 3033 if (i.imm_operands)
3034 {
3035 register unsigned int n;
3036
3037 for (n = 0; n < i.operands; n++)
3038 {
520dc8e8 3039 if (i.types[n] & Imm)
252b5132 3040 {
520dc8e8 3041 if (i.op[n].imms->X_op == O_constant)
252b5132 3042 {
847f7ad4
AM		 3043 int size;
3044 offsetT val;
b4cac588 3045
847f7ad4 3046 size = 4;
3e73aa7c 3047 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3048 {
b4cac588 3049 size = 2;
b4cac588 3050 if (i.types[n] & (Imm8 | Imm8S))
847f7ad4 3051 size = 1;
3e73aa7c
JH		 3052 else if (i.types[n] & Imm64)
3053 size = 8;
252b5132 3054 }
847f7ad4
AM		 3055 val = offset_in_range (i.op[n].imms->X_add_number,
3056 size);
b4cac588
AM		 3057 insn_size += size;
3058 p = frag_more (size);
847f7ad4 3059 md_number_to_chars (p, val, size);
252b5132
RH		 3060 }
3061 else
ce8a8b2f
AM		 3062 {
3063 /* Not absolute_section.
3064 Need a 32-bit fixup (don't support 8bit
520dc8e8 3065 non-absolute imms). Try to support other
47926f60 3066 sizes ... */
f3c180ae 3067 RELOC_ENUM reloc_type;
520dc8e8 3068 int size = 4;
3e73aa7c 3069 int sign = 0;
252b5132 3070
3e73aa7c
JH		 3071 if ((i.types[n] & (Imm32S))
3072 && i.suffix == QWORD_MNEM_SUFFIX)
3073 sign = 1;
3074 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3075 {
3076 size = 2;
3077 if (i.types[n] & (Imm8 | Imm8S))
3078 size = 1;
3079 if (i.types[n] & Imm64)
3080 size = 8;
3081 }
520dc8e8 3082
252b5132
RH		 3083 insn_size += size;
3084 p = frag_more (size);
1ae12ab7 3085 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3086#ifdef BFD_ASSEMBLER
f6af82bd 3087 if (reloc_type == BFD_RELOC_32
252b5132 3088 && GOT_symbol
520dc8e8
AM		 3089 && GOT_symbol == i.op[n].imms->X_add_symbol
3090 && (i.op[n].imms->X_op == O_symbol
3091 || (i.op[n].imms->X_op == O_add
49309057 3092 && ((symbol_get_value_expression
520dc8e8 3093 (i.op[n].imms->X_op_symbol)->X_op)
252b5132
RH		 3094 == O_subtract))))
3095 {
3e73aa7c
JH		 3096 /* We don't support dynamic linking on x86-64 yet. */
3097 if (flag_code == CODE_64BIT)
bfb32b52 3098 abort ();
f6af82bd 3099 reloc_type = BFD_RELOC_386_GOTPC;
520dc8e8 3100 i.op[n].imms->X_add_number += 3;
252b5132
RH		 3101 }
3102#endif
3103 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
520dc8e8 3104 i.op[n].imms, 0, reloc_type);
252b5132
RH		 3105 }
3106 }
3107 }
ce8a8b2f 3108 }
252b5132
RH		 3109 }
3110
e346e481
RH		 3111 dwarf2_emit_insn (insn_size);
3112
252b5132
RH		 3113#ifdef DEBUG386
3114 if (flag_debug)
3115 {
3116 pi (line, &i);
3117 }
47926f60 3118#endif /* DEBUG386 */
252b5132
RH		 3119 }
3120}
3121\f
f3c180ae
AM		 3122#ifndef LEX_AT
3123static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3124
3125/* Parse operands of the form
3126 <symbol>@GOTOFF+<nnn>
3127 and similar .plt or .got references.
3128
3129 If we find one, set up the correct relocation in RELOC and copy the
3130 input string, minus the `@GOTOFF' into a malloc'd buffer for
3131 parsing by the calling routine. Return this buffer, and if ADJUST
3132 is non-null set it to the length of the string we removed from the
3133 input line. Otherwise return NULL. */
3134static char *
3135lex_got (reloc, adjust)
3136 RELOC_ENUM *reloc;
3137 int *adjust;
3138{
3139 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3140 static const struct {
3141 const char *str;
3142 const RELOC_ENUM rel[NUM_FLAG_CODE];
3143 } gotrel[] = {
3144 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3145 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3146 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3147 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3148 };
3149 char *cp;
3150 unsigned int j;
3151
3152 for (cp = input_line_pointer; *cp != '@'; cp++)
3153 if (is_end_of_line[(unsigned char) *cp])
3154 return NULL;
3155
3156 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3157 {
3158 int len;
3159
3160 len = strlen (gotrel[j].str);
3161 if (strncmp (cp + 1, gotrel[j].str, len) == 0)
3162 {
3163 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3164 {
3165 int first;
3166 char *tmpbuf;
3167
3168 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3169
3170 if (GOT_symbol == NULL)
3171 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3172
3173 /* Replace the relocation token with ' ', so that
3174 errors like foo@GOTOFF1 will be detected. */
3175 first = cp - input_line_pointer;
3176 tmpbuf = xmalloc (strlen (input_line_pointer));
3177 memcpy (tmpbuf, input_line_pointer, first);
3178 tmpbuf[first] = ' ';
3179 strcpy (tmpbuf + first + 1, cp + 1 + len);
3180 if (adjust)
3181 *adjust = len;
3182 return tmpbuf;
3183 }
3184
3185 as_bad (_("@%s reloc is not supported in %s bit mode"),
3186 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3187 return NULL;
3188 }
3189 }
3190
3191 /* Might be a symbol version string. Don't as_bad here. */
3192 return NULL;
3193}
3194
3195/* x86_cons_fix_new is called via the expression parsing code when a
3196 reloc is needed. We use this hook to get the correct .got reloc. */
3197static RELOC_ENUM got_reloc = NO_RELOC;
3198
3199void
3200x86_cons_fix_new (frag, off, len, exp)
3201 fragS *frag;
3202 unsigned int off;
3203 unsigned int len;
3204 expressionS *exp;
3205{
3206 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3207 got_reloc = NO_RELOC;
3208 fix_new_exp (frag, off, len, exp, 0, r);
3209}
3210
3211void
3212x86_cons (exp, size)
3213 expressionS *exp;
3214 int size;
3215{
3216 if (size == 4)
3217 {
3218 /* Handle @GOTOFF and the like in an expression. */
3219 char *save;
3220 char *gotfree_input_line;
3221 int adjust;
3222
3223 save = input_line_pointer;
3224 gotfree_input_line = lex_got (&got_reloc, &adjust);
3225 if (gotfree_input_line)
3226 input_line_pointer = gotfree_input_line;
3227
3228 expression (exp);
3229
3230 if (gotfree_input_line)
3231 {
3232 /* expression () has merrily parsed up to the end of line,
3233 or a comma - in the wrong buffer. Transfer how far
3234 input_line_pointer has moved to the right buffer. */
3235 input_line_pointer = (save
3236 + (input_line_pointer - gotfree_input_line)
3237 + adjust);
3238 free (gotfree_input_line);
3239 }
3240 }
3241 else
3242 expression (exp);
3243}
3244#endif
3245
252b5132
RH		 3246static int i386_immediate PARAMS ((char *));
3247
3248static int
3249i386_immediate (imm_start)
3250 char *imm_start;
3251{
3252 char *save_input_line_pointer;
f3c180ae
AM		 3253#ifndef LEX_AT
3254 char *gotfree_input_line;
3255#endif
252b5132 3256 segT exp_seg = 0;
47926f60 3257 expressionS *exp;
252b5132
RH		 3258
3259 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3260 {
d0b47220 3261 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3262 return 0;
3263 }
3264
3265 exp = &im_expressions[i.imm_operands++];
520dc8e8 3266 i.op[this_operand].imms = exp;
252b5132
RH		 3267
3268 if (is_space_char (*imm_start))
3269 ++imm_start;
3270
3271 save_input_line_pointer = input_line_pointer;
3272 input_line_pointer = imm_start;
3273
3274#ifndef LEX_AT
f3c180ae
AM		 3275 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3276 if (gotfree_input_line)
3277 input_line_pointer = gotfree_input_line;
252b5132
RH		 3278#endif
3279
3280 exp_seg = expression (exp);
3281
83183c0c 3282 SKIP_WHITESPACE ();
252b5132 3283 if (*input_line_pointer)
f3c180ae 3284 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3285
3286 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3287#ifndef LEX_AT
3288 if (gotfree_input_line)
3289 free (gotfree_input_line);
3290#endif
252b5132 3291
2daf4fd8 3292 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3293 {
47926f60 3294 /* Missing or bad expr becomes absolute 0. */
d0b47220 3295 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3296 imm_start);
252b5132
RH		 3297 exp->X_op = O_constant;
3298 exp->X_add_number = 0;
3299 exp->X_add_symbol = (symbolS *) 0;
3300 exp->X_op_symbol = (symbolS *) 0;
252b5132 3301 }
3e73aa7c 3302 else if (exp->X_op == O_constant)
252b5132 3303 {
47926f60 3304 /* Size it properly later. */
3e73aa7c
JH		 3305 i.types[this_operand] |= Imm64;
3306 /* If BFD64, sign extend val. */
3307 if (!use_rela_relocations)
3308 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3309 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3310 }
4c63da97 3311#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3312 else if (1
4c63da97 3313#ifdef BFD_ASSEMBLER
47926f60 3314 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3315#endif
47926f60 3316 && exp_seg != text_section
24eab124
AM		 3317 && exp_seg != data_section
3318 && exp_seg != bss_section
3319 && exp_seg != undefined_section
252b5132 3320#ifdef BFD_ASSEMBLER
24eab124 3321 && !bfd_is_com_section (exp_seg)
252b5132 3322#endif
24eab124 3323 )
252b5132 3324 {
4c63da97 3325#ifdef BFD_ASSEMBLER
d0b47220 3326 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3327#else
d0b47220 3328 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3329#endif
252b5132
RH		 3330 return 0;
3331 }
3332#endif
3333 else
3334 {
3335 /* This is an address. The size of the address will be
24eab124 3336 determined later, depending on destination register,
3e73aa7c
JH		 3337 suffix, or the default for the section. */
3338 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3339 }
3340
3341 return 1;
3342}
3343
3344static int i386_scale PARAMS ((char *));
3345
3346static int
3347i386_scale (scale)
3348 char *scale;
3349{
3350 if (!isdigit (*scale))
3351 goto bad_scale;
3352
3353 switch (*scale)
3354 {
3355 case '0':
3356 case '1':
3357 i.log2_scale_factor = 0;
3358 break;
3359 case '2':
3360 i.log2_scale_factor = 1;
3361 break;
3362 case '4':
3363 i.log2_scale_factor = 2;
3364 break;
3365 case '8':
3366 i.log2_scale_factor = 3;
3367 break;
3368 default:
3369 bad_scale:
3370 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3371 scale);
252b5132
RH		 3372 return 0;
3373 }
3374 if (i.log2_scale_factor != 0 && ! i.index_reg)
3375 {
3376 as_warn (_("scale factor of %d without an index register"),
24eab124 3377 1 << i.log2_scale_factor);
252b5132
RH		 3378#if SCALE1_WHEN_NO_INDEX
3379 i.log2_scale_factor = 0;
3380#endif
3381 }
3382 return 1;
3383}
3384
3385static int i386_displacement PARAMS ((char *, char *));
3386
3387static int
3388i386_displacement (disp_start, disp_end)
3389 char *disp_start;
3390 char *disp_end;
3391{
3392 register expressionS *exp;
3393 segT exp_seg = 0;
3394 char *save_input_line_pointer;
f3c180ae
AM		 3395#ifndef LEX_AT
3396 char *gotfree_input_line;
3397#endif
252b5132
RH		 3398 int bigdisp = Disp32;
3399
3e73aa7c 3400 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
252b5132 3401 bigdisp = Disp16;
3e73aa7c
JH		 3402 if (flag_code == CODE_64BIT)
3403 bigdisp = Disp64;
252b5132
RH		 3404 i.types[this_operand] |= bigdisp;
3405
3406 exp = &disp_expressions[i.disp_operands];
520dc8e8 3407 i.op[this_operand].disps = exp;
252b5132
RH		 3408 i.disp_operands++;
3409 save_input_line_pointer = input_line_pointer;
3410 input_line_pointer = disp_start;
3411 END_STRING_AND_SAVE (disp_end);
3412
3413#ifndef GCC_ASM_O_HACK
3414#define GCC_ASM_O_HACK 0
3415#endif
3416#if GCC_ASM_O_HACK
3417 END_STRING_AND_SAVE (disp_end + 1);
3418 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3419 && displacement_string_end[-1] == '+')
252b5132
RH		 3420 {
3421 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3422 constraint within gcc asm statements.
3423 For instance:
3424
3425 #define _set_tssldt_desc(n,addr,limit,type) \
3426 __asm__ __volatile__ ( \
3427 "movw %w2,%0\n\t" \
3428 "movw %w1,2+%0\n\t" \
3429 "rorl $16,%1\n\t" \
3430 "movb %b1,4+%0\n\t" \
3431 "movb %4,5+%0\n\t" \
3432 "movb $0,6+%0\n\t" \
3433 "movb %h1,7+%0\n\t" \
3434 "rorl $16,%1" \
3435 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3436
3437 This works great except that the output assembler ends
3438 up looking a bit weird if it turns out that there is
3439 no offset. You end up producing code that looks like:
3440
3441 #APP
3442 movw $235,(%eax)
3443 movw %dx,2+(%eax)
3444 rorl $16,%edx
3445 movb %dl,4+(%eax)
3446 movb $137,5+(%eax)
3447 movb $0,6+(%eax)
3448 movb %dh,7+(%eax)
3449 rorl $16,%edx
3450 #NO_APP
3451
47926f60 3452 So here we provide the missing zero. */
24eab124
AM		 3453
3454 *displacement_string_end = '0';
252b5132
RH		 3455 }
3456#endif
3457#ifndef LEX_AT
f3c180ae
AM		 3458 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3459 if (gotfree_input_line)
3460 input_line_pointer = gotfree_input_line;
252b5132
RH		 3461#endif
3462
24eab124 3463 exp_seg = expression (exp);
252b5132
RH		 3464
3465#ifdef BFD_ASSEMBLER
24eab124
AM		 3466 /* We do this to make sure that the section symbol is in
3467 the symbol table. We will ultimately change the relocation
47926f60 3468 to be relative to the beginning of the section. */
1ae12ab7
AM		 3469 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3470 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3471 {
e5cb08ac 3472 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3473 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3474 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3475 assert (exp->X_op == O_symbol);
3476 exp->X_op = O_subtract;
3477 exp->X_op_symbol = GOT_symbol;
1ae12ab7
AM		 3478 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3479 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3480 else
1ae12ab7 3481 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3482 }
252b5132
RH		 3483#endif
3484
24eab124
AM		 3485 SKIP_WHITESPACE ();
3486 if (*input_line_pointer)
f3c180ae 3487 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132 3488#if GCC_ASM_O_HACK
24eab124 3489 RESTORE_END_STRING (disp_end + 1);
252b5132 3490#endif
24eab124
AM		 3491 RESTORE_END_STRING (disp_end);
3492 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3493#ifndef LEX_AT
3494 if (gotfree_input_line)
3495 free (gotfree_input_line);
3496#endif
24eab124 3497
2daf4fd8
AM		 3498 if (exp->X_op == O_absent || exp->X_op == O_big)
3499 {
47926f60 3500 /* Missing or bad expr becomes absolute 0. */
d0b47220 3501 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3502 disp_start);
3503 exp->X_op = O_constant;
3504 exp->X_add_number = 0;
3505 exp->X_add_symbol = (symbolS *) 0;
3506 exp->X_op_symbol = (symbolS *) 0;
3507 }
3508
4c63da97 3509#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3510 if (exp->X_op != O_constant
4c63da97 3511#ifdef BFD_ASSEMBLER
45288df1 3512 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3513#endif
45288df1
AM		 3514 && exp_seg != text_section
3515 && exp_seg != data_section
3516 && exp_seg != bss_section
3517 && exp_seg != undefined_section)
24eab124 3518 {
4c63da97 3519#ifdef BFD_ASSEMBLER
d0b47220 3520 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3521#else
d0b47220 3522 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3523#endif
24eab124
AM		 3524 return 0;
3525 }
252b5132 3526#endif
3e73aa7c
JH		 3527 else if (flag_code == CODE_64BIT)
3528 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3529 return 1;
3530}
3531
e5cb08ac 3532static int i386_index_check PARAMS ((const char *));
252b5132 3533
eecb386c 3534/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3535 Return 1 on success, 0 on a failure. */
3536
252b5132 3537static int
eecb386c
AM		 3538i386_index_check (operand_string)
3539 const char *operand_string;
252b5132 3540{
3e73aa7c 3541 int ok;
24eab124 3542#if INFER_ADDR_PREFIX
eecb386c
AM		 3543 int fudged = 0;
3544
24eab124
AM		 3545 tryprefix:
3546#endif
3e73aa7c
JH		 3547 ok = 1;
3548 if (flag_code == CODE_64BIT)
3549 {
3550 /* 64bit checks. */
3551 if ((i.base_reg
3552 && ((i.base_reg->reg_type & Reg64) == 0)
3553 && (i.base_reg->reg_type != BaseIndex
3554 || i.index_reg))
3555 || (i.index_reg
3556 && ((i.index_reg->reg_type & (Reg64|BaseIndex))
3557 != (Reg64|BaseIndex))))
3558 ok = 0;
3559 }
3560 else
3561 {
3562 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3563 {
3564 /* 16bit checks. */
3565 if ((i.base_reg
3566 && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex))
3567 != (Reg16|BaseIndex)))
3568 || (i.index_reg
3569 && (((i.index_reg->reg_type & (Reg16|BaseIndex))
3570 != (Reg16|BaseIndex))
3571 || ! (i.base_reg
3572 && i.base_reg->reg_num < 6
3573 && i.index_reg->reg_num >= 6
3574 && i.log2_scale_factor == 0))))
3575 ok = 0;
3576 }
3577 else
e5cb08ac 3578 {
3e73aa7c
JH		 3579 /* 32bit checks. */
3580 if ((i.base_reg
3581 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3582 || (i.index_reg
3583 && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex))
3584 != (Reg32|BaseIndex))))
e5cb08ac 3585 ok = 0;
3e73aa7c
JH		 3586 }
3587 }
3588 if (!ok)
24eab124
AM		 3589 {
3590#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3591 if (flag_code != CODE_64BIT
3592 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3593 {
3594 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3595 i.prefixes += 1;
b23bac36
AM		 3596 /* Change the size of any displacement too. At most one of
3597 Disp16 or Disp32 is set.
3598 FIXME. There doesn't seem to be any real need for separate
3599 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3600 Removing them would probably clean up the code quite a lot. */
b23bac36
AM		 3601 if (i.types[this_operand] & (Disp16|Disp32))
3602 i.types[this_operand] ^= (Disp16|Disp32);
eecb386c 3603 fudged = 1;
24eab124
AM		 3604 goto tryprefix;
3605 }
eecb386c
AM		 3606 if (fudged)
3607 as_bad (_("`%s' is not a valid base/index expression"),
3608 operand_string);
3609 else
c388dee8 3610#endif
eecb386c
AM		 3611 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3612 operand_string,
3e73aa7c 3613 flag_code_names[flag_code]);
eecb386c 3614 return 0;
24eab124
AM		 3615 }
3616 return 1;
3617}
252b5132 3618
252b5132 3619/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 3620 on error. */
252b5132 3621
252b5132
RH		 3622static int
3623i386_operand (operand_string)
3624 char *operand_string;
3625{
af6bdddf
AM		 3626 const reg_entry *r;
3627 char *end_op;
24eab124 3628 char *op_string = operand_string;
252b5132 3629
24eab124 3630 if (is_space_char (*op_string))
252b5132
RH		 3631 ++op_string;
3632
24eab124 3633 /* We check for an absolute prefix (differentiating,
47926f60 3634 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 3635 if (*op_string == ABSOLUTE_PREFIX)
3636 {
3637 ++op_string;
3638 if (is_space_char (*op_string))
3639 ++op_string;
3640 i.types[this_operand] |= JumpAbsolute;
3641 }
252b5132 3642
47926f60 3643 /* Check if operand is a register. */
af6bdddf
AM		 3644 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3645 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 3646 {
24eab124
AM		 3647 /* Check for a segment override by searching for ':' after a
3648 segment register. */
3649 op_string = end_op;
3650 if (is_space_char (*op_string))
3651 ++op_string;
3652 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3653 {
3654 switch (r->reg_num)
3655 {
3656 case 0:
3657 i.seg[i.mem_operands] = &es;
3658 break;
3659 case 1:
3660 i.seg[i.mem_operands] = &cs;
3661 break;
3662 case 2:
3663 i.seg[i.mem_operands] = &ss;
3664 break;
3665 case 3:
3666 i.seg[i.mem_operands] = &ds;
3667 break;
3668 case 4:
3669 i.seg[i.mem_operands] = &fs;
3670 break;
3671 case 5:
3672 i.seg[i.mem_operands] = &gs;
3673 break;
3674 }
252b5132 3675
24eab124 3676 /* Skip the ':' and whitespace. */
252b5132
RH		 3677 ++op_string;
3678 if (is_space_char (*op_string))
24eab124 3679 ++op_string;
252b5132 3680
24eab124
AM		 3681 if (!is_digit_char (*op_string)
3682 && !is_identifier_char (*op_string)
3683 && *op_string != '('
3684 && *op_string != ABSOLUTE_PREFIX)
3685 {
3686 as_bad (_("bad memory operand `%s'"), op_string);
3687 return 0;
3688 }
47926f60 3689 /* Handle case of %es:*foo. */
24eab124
AM		 3690 if (*op_string == ABSOLUTE_PREFIX)
3691 {
3692 ++op_string;
3693 if (is_space_char (*op_string))
3694 ++op_string;
3695 i.types[this_operand] |= JumpAbsolute;
3696 }
3697 goto do_memory_reference;
3698 }
3699 if (*op_string)
3700 {
d0b47220 3701 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 3702 return 0;
3703 }
3704 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 3705 i.op[this_operand].regs = r;
24eab124
AM		 3706 i.reg_operands++;
3707 }
af6bdddf
AM		 3708 else if (*op_string == REGISTER_PREFIX)
3709 {
3710 as_bad (_("bad register name `%s'"), op_string);
3711 return 0;
3712 }
24eab124 3713 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 3714 {
24eab124
AM		 3715 ++op_string;
3716 if (i.types[this_operand] & JumpAbsolute)
3717 {
d0b47220 3718 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 3719 return 0;
3720 }
3721 if (!i386_immediate (op_string))
3722 return 0;
3723 }
3724 else if (is_digit_char (*op_string)
3725 || is_identifier_char (*op_string)
e5cb08ac 3726 || *op_string == '(')
24eab124 3727 {
47926f60 3728 /* This is a memory reference of some sort. */
af6bdddf 3729 char *base_string;
252b5132 3730
47926f60 3731 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 3732 char *displacement_string_start;
3733 char *displacement_string_end;
252b5132 3734
24eab124 3735 do_memory_reference:
24eab124
AM		 3736 if ((i.mem_operands == 1
3737 && (current_templates->start->opcode_modifier & IsString) == 0)
3738 || i.mem_operands == 2)
3739 {
3740 as_bad (_("too many memory references for `%s'"),
3741 current_templates->start->name);
3742 return 0;
3743 }
252b5132 3744
24eab124
AM		 3745 /* Check for base index form. We detect the base index form by
3746 looking for an ')' at the end of the operand, searching
3747 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3748 after the '('. */
af6bdddf 3749 base_string = op_string + strlen (op_string);
c3332e24 3750
af6bdddf
AM		 3751 --base_string;
3752 if (is_space_char (*base_string))
3753 --base_string;
252b5132 3754
47926f60 3755 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 3756 displacement_string_start = op_string;
3757 displacement_string_end = base_string + 1;
252b5132 3758
24eab124
AM		 3759 if (*base_string == ')')
3760 {
af6bdddf 3761 char *temp_string;
24eab124
AM		 3762 unsigned int parens_balanced = 1;
3763 /* We've already checked that the number of left & right ()'s are
47926f60 3764 equal, so this loop will not be infinite. */
24eab124
AM		 3765 do
3766 {
3767 base_string--;
3768 if (*base_string == ')')
3769 parens_balanced++;
3770 if (*base_string == '(')
3771 parens_balanced--;
3772 }
3773 while (parens_balanced);
c3332e24 3774
af6bdddf 3775 temp_string = base_string;
c3332e24 3776
24eab124 3777 /* Skip past '(' and whitespace. */
252b5132
RH		 3778 ++base_string;
3779 if (is_space_char (*base_string))
24eab124 3780 ++base_string;
252b5132 3781
af6bdddf
AM		 3782 if (*base_string == ','
3783 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3784 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 3785 {
af6bdddf 3786 displacement_string_end = temp_string;
252b5132 3787
af6bdddf 3788 i.types[this_operand] |= BaseIndex;
252b5132 3789
af6bdddf 3790 if (i.base_reg)
24eab124 3791 {
24eab124
AM		 3792 base_string = end_op;
3793 if (is_space_char (*base_string))
3794 ++base_string;
af6bdddf
AM		 3795 }
3796
3797 /* There may be an index reg or scale factor here. */
3798 if (*base_string == ',')
3799 {
3800 ++base_string;
3801 if (is_space_char (*base_string))
3802 ++base_string;
3803
3804 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3805 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 3806 {
af6bdddf 3807 base_string = end_op;
24eab124
AM		 3808 if (is_space_char (*base_string))
3809 ++base_string;
af6bdddf
AM		 3810 if (*base_string == ',')
3811 {
3812 ++base_string;
3813 if (is_space_char (*base_string))
3814 ++base_string;
3815 }
e5cb08ac 3816 else if (*base_string != ')')
af6bdddf
AM		 3817 {
3818 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3819 operand_string);
3820 return 0;
3821 }
24eab124 3822 }
af6bdddf 3823 else if (*base_string == REGISTER_PREFIX)
24eab124 3824 {
af6bdddf 3825 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 3826 return 0;
3827 }
252b5132 3828
47926f60 3829 /* Check for scale factor. */
af6bdddf
AM		 3830 if (isdigit ((unsigned char) *base_string))
3831 {
3832 if (!i386_scale (base_string))
3833 return 0;
24eab124 3834
af6bdddf
AM		 3835 ++base_string;
3836 if (is_space_char (*base_string))
3837 ++base_string;
3838 if (*base_string != ')')
3839 {
3840 as_bad (_("expecting `)' after scale factor in `%s'"),
3841 operand_string);
3842 return 0;
3843 }
3844 }
3845 else if (!i.index_reg)
24eab124 3846 {
af6bdddf
AM		 3847 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3848 *base_string);
24eab124
AM		 3849 return 0;
3850 }
3851 }
af6bdddf 3852 else if (*base_string != ')')
24eab124 3853 {
af6bdddf
AM		 3854 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3855 operand_string);
24eab124
AM		 3856 return 0;
3857 }
c3332e24 3858 }
af6bdddf 3859 else if (*base_string == REGISTER_PREFIX)
c3332e24 3860 {
af6bdddf 3861 as_bad (_("bad register name `%s'"), base_string);
24eab124 3862 return 0;
c3332e24 3863 }
24eab124
AM		 3864 }
3865
3866 /* If there's an expression beginning the operand, parse it,
3867 assuming displacement_string_start and
3868 displacement_string_end are meaningful. */
3869 if (displacement_string_start != displacement_string_end)
3870 {
3871 if (!i386_displacement (displacement_string_start,
3872 displacement_string_end))
3873 return 0;
3874 }
3875
3876 /* Special case for (%dx) while doing input/output op. */
3877 if (i.base_reg
3878 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
3879 && i.index_reg == 0
3880 && i.log2_scale_factor == 0
3881 && i.seg[i.mem_operands] == 0
3882 && (i.types[this_operand] & Disp) == 0)
3883 {
3884 i.types[this_operand] = InOutPortReg;
3885 return 1;
3886 }
3887
eecb386c
AM		 3888 if (i386_index_check (operand_string) == 0)
3889 return 0;
24eab124
AM		 3890 i.mem_operands++;
3891 }
3892 else
ce8a8b2f
AM		 3893 {
3894 /* It's not a memory operand; argh! */
24eab124
AM		 3895 as_bad (_("invalid char %s beginning operand %d `%s'"),
3896 output_invalid (*op_string),
3897 this_operand + 1,
3898 op_string);
3899 return 0;
3900 }
47926f60 3901 return 1; /* Normal return. */
252b5132
RH		 3902}
3903\f
ee7fcc42
AM		 3904/* md_estimate_size_before_relax()
3905
3906 Called just before relax() for rs_machine_dependent frags. The x86
3907 assembler uses these frags to handle variable size jump
3908 instructions.
3909
3910 Any symbol that is now undefined will not become defined.
3911 Return the correct fr_subtype in the frag.
3912 Return the initial "guess for variable size of frag" to caller.
3913 The guess is actually the growth beyond the fixed part. Whatever
3914 we do to grow the fixed or variable part contributes to our
3915 returned value. */
3916
252b5132
RH		 3917int
3918md_estimate_size_before_relax (fragP, segment)
3919 register fragS *fragP;
3920 register segT segment;
3921{
252b5132 3922 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 3923 check for un-relaxable symbols. On an ELF system, we can't relax
3924 an externally visible symbol, because it may be overridden by a
3925 shared library. */
3926 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 3927#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b98ef147
AM		 3928 || S_IS_EXTERNAL (fragP->fr_symbol)
3929 || S_IS_WEAK (fragP->fr_symbol)
3930#endif
3931 )
252b5132 3932 {
b98ef147
AM		 3933 /* Symbol is undefined in this segment, or we need to keep a
3934 reloc so that weak symbols can be overridden. */
3935 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 3936 RELOC_ENUM reloc_type;
ee7fcc42
AM		 3937 unsigned char *opcode;
3938 int old_fr_fix;
f6af82bd 3939
ee7fcc42
AM		 3940 if (fragP->fr_var != NO_RELOC)
3941 reloc_type = fragP->fr_var;
b98ef147 3942 else if (size == 2)
f6af82bd
AM		 3943 reloc_type = BFD_RELOC_16_PCREL;
3944 else
3945 reloc_type = BFD_RELOC_32_PCREL;
252b5132 3946
ee7fcc42
AM		 3947 old_fr_fix = fragP->fr_fix;
3948 opcode = (unsigned char *) fragP->fr_opcode;
3949
fddf5b5b 3950 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 3951 {
fddf5b5b
AM		 3952 case UNCOND_JUMP:
3953 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 3954 opcode[0] = 0xe9;
252b5132
RH		 3955 fragP->fr_fix += size;
3956 fix_new (fragP, old_fr_fix, size,
3957 fragP->fr_symbol,
3958 fragP->fr_offset, 1,
f6af82bd 3959 reloc_type);
252b5132
RH		 3960 break;
3961
fddf5b5b
AM		 3962 case COND_JUMP86:
3963 if (no_cond_jump_promotion)
3964 return 1;
3965 if (size == 2)
3966 {
3967 /* Negate the condition, and branch past an
3968 unconditional jump. */
3969 opcode[0] ^= 1;
3970 opcode[1] = 3;
3971 /* Insert an unconditional jump. */
3972 opcode[2] = 0xe9;
3973 /* We added two extra opcode bytes, and have a two byte
3974 offset. */
3975 fragP->fr_fix += 2 + 2;
3976 fix_new (fragP, old_fr_fix + 2, 2,
3977 fragP->fr_symbol,
3978 fragP->fr_offset, 1,
3979 reloc_type);
3980 break;
3981 }
3982 /* Fall through. */
3983
3984 case COND_JUMP:
3985 if (no_cond_jump_promotion)
3986 return 1;
24eab124 3987 /* This changes the byte-displacement jump 0x7N
fddf5b5b 3988 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 3989 opcode[1] = opcode[0] + 0x10;
f6af82bd 3990 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 3991 /* We've added an opcode byte. */
3992 fragP->fr_fix += 1 + size;
252b5132
RH		 3993 fix_new (fragP, old_fr_fix + 1, size,
3994 fragP->fr_symbol,
3995 fragP->fr_offset, 1,
f6af82bd 3996 reloc_type);
252b5132 3997 break;
fddf5b5b
AM		 3998
3999 default:
4000 BAD_CASE (fragP->fr_subtype);
4001 break;
252b5132
RH		 4002 }
4003 frag_wane (fragP);
ee7fcc42 4004 return fragP->fr_fix - old_fr_fix;
252b5132 4005 }
47926f60
KH		 4006 /* Guess a short jump. */
4007 return 1;
ee7fcc42
AM		 4008}
4009
47926f60
KH		 4010/* Called after relax() is finished.
4011
4012 In: Address of frag.
4013 fr_type == rs_machine_dependent.
4014 fr_subtype is what the address relaxed to.
4015
4016 Out: Any fixSs and constants are set up.
4017 Caller will turn frag into a ".space 0". */
4018
252b5132
RH		 4019#ifndef BFD_ASSEMBLER
4020void
4021md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4022 object_headers *headers ATTRIBUTE_UNUSED;
4023 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4024 register fragS *fragP;
4025#else
4026void
4027md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4028 bfd *abfd ATTRIBUTE_UNUSED;
4029 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4030 register fragS *fragP;
4031#endif
4032{
4033 register unsigned char *opcode;
4034 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4035 offsetT target_address;
4036 offsetT opcode_address;
252b5132 4037 unsigned int extension = 0;
847f7ad4 4038 offsetT displacement_from_opcode_start;
252b5132
RH		 4039
4040 opcode = (unsigned char *) fragP->fr_opcode;
4041
47926f60 4042 /* Address we want to reach in file space. */
252b5132 4043 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
47926f60
KH		 4044#ifdef BFD_ASSEMBLER
4045 /* Not needed otherwise? */
49309057 4046 target_address += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH		 4047#endif
4048
47926f60 4049 /* Address opcode resides at in file space. */
252b5132
RH		 4050 opcode_address = fragP->fr_address + fragP->fr_fix;
4051
47926f60 4052 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4053 displacement_from_opcode_start = target_address - opcode_address;
4054
fddf5b5b 4055 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4056 {
47926f60
KH		 4057 /* Don't have to change opcode. */
4058 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4059 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4060 }
4061 else
4062 {
4063 if (no_cond_jump_promotion
4064 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4065 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4066
fddf5b5b
AM		 4067 switch (fragP->fr_subtype)
4068 {
4069 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4070 extension = 4; /* 1 opcode + 4 displacement */
4071 opcode[0] = 0xe9;
4072 where_to_put_displacement = &opcode[1];
4073 break;
252b5132 4074
fddf5b5b
AM		 4075 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4076 extension = 2; /* 1 opcode + 2 displacement */
4077 opcode[0] = 0xe9;
4078 where_to_put_displacement = &opcode[1];
4079 break;
252b5132 4080
fddf5b5b
AM		 4081 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4082 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4083 extension = 5; /* 2 opcode + 4 displacement */
4084 opcode[1] = opcode[0] + 0x10;
4085 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4086 where_to_put_displacement = &opcode[2];
4087 break;
252b5132 4088
fddf5b5b
AM		 4089 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4090 extension = 3; /* 2 opcode + 2 displacement */
4091 opcode[1] = opcode[0] + 0x10;
4092 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4093 where_to_put_displacement = &opcode[2];
4094 break;
252b5132 4095
fddf5b5b
AM		 4096 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4097 extension = 4;
4098 opcode[0] ^= 1;
4099 opcode[1] = 3;
4100 opcode[2] = 0xe9;
4101 where_to_put_displacement = &opcode[3];
4102 break;
4103
4104 default:
4105 BAD_CASE (fragP->fr_subtype);
4106 break;
4107 }
252b5132 4108 }
fddf5b5b 4109
47926f60 4110 /* Now put displacement after opcode. */
252b5132
RH		 4111 md_number_to_chars ((char *) where_to_put_displacement,
4112 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4113 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4114 fragP->fr_fix += extension;
4115}
4116\f
47926f60
KH		 4117/* Size of byte displacement jmp. */
4118int md_short_jump_size = 2;
4119
4120/* Size of dword displacement jmp. */
4121int md_long_jump_size = 5;
252b5132 4122
47926f60
KH		 4123/* Size of relocation record. */
4124const int md_reloc_size = 8;
252b5132
RH		 4125
4126void
4127md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4128 char *ptr;
4129 addressT from_addr, to_addr;
ab9da554
ILT		 4130 fragS *frag ATTRIBUTE_UNUSED;
4131 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4132{
847f7ad4 4133 offsetT offset;
252b5132
RH		 4134
4135 offset = to_addr - (from_addr + 2);
47926f60
KH		 4136 /* Opcode for byte-disp jump. */
4137 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4138 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4139}
4140
4141void
4142md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4143 char *ptr;
4144 addressT from_addr, to_addr;
a38cf1db
AM		 4145 fragS *frag ATTRIBUTE_UNUSED;
4146 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4147{
847f7ad4 4148 offsetT offset;
252b5132 4149
a38cf1db
AM		 4150 offset = to_addr - (from_addr + 5);
4151 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4152 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4153}
4154\f
4155/* Apply a fixup (fixS) to segment data, once it has been determined
4156 by our caller that we have all the info we need to fix it up.
4157
4158 On the 386, immediates, displacements, and data pointers are all in
4159 the same (little-endian) format, so we don't need to care about which
4160 we are handling. */
4161
4162int
4163md_apply_fix3 (fixP, valp, seg)
47926f60
KH		 4164 /* The fix we're to put in. */
4165 fixS *fixP;
4166
4167 /* Pointer to the value of the bits. */
4168 valueT *valp;
4169
4170 /* Segment fix is from. */
4171 segT seg ATTRIBUTE_UNUSED;
252b5132
RH		 4172{
4173 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4174 valueT value = *valp;
4175
e1b283bb 4176#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4177 if (fixP->fx_pcrel)
4178 {
4179 switch (fixP->fx_r_type)
4180 {
5865bb77
ILT		 4181 default:
4182 break;
4183
93382f6d
AM		 4184 case BFD_RELOC_32:
4185 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4186 break;
4187 case BFD_RELOC_16:
4188 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4189 break;
4190 case BFD_RELOC_8:
4191 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4192 break;
4193 }
4194 }
252b5132 4195
0723899b
ILT		 4196 /* This is a hack. There should be a better way to handle this.
4197 This covers for the fact that bfd_install_relocation will
4198 subtract the current location (for partial_inplace, PC relative
4199 relocations); see more below. */
93382f6d
AM		 4200 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4201 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4202 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7c44d1d3 4203 && fixP->fx_addsy && !use_rela_relocations)
252b5132
RH		 4204 {
4205#ifndef OBJ_AOUT
4206 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4207#ifdef TE_PE
4208 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4209#endif
4210 )
4211 value += fixP->fx_where + fixP->fx_frag->fr_address;
4212#endif
4213#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4214 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4215 {
2f66722d
AM		 4216 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4217
4218 if ((fseg == seg
4219 || (symbol_section_p (fixP->fx_addsy)
4220 && fseg != absolute_section))
4221 && ! S_IS_EXTERNAL (fixP->fx_addsy)
4222 && ! S_IS_WEAK (fixP->fx_addsy)
4223 && S_IS_DEFINED (fixP->fx_addsy)
4224 && ! S_IS_COMMON (fixP->fx_addsy))
4225 {
4226 /* Yes, we add the values in twice. This is because
4227 bfd_perform_relocation subtracts them out again. I think
4228 bfd_perform_relocation is broken, but I don't dare change
4229 it. FIXME. */
4230 value += fixP->fx_where + fixP->fx_frag->fr_address;
4231 }
252b5132
RH		 4232 }
4233#endif
4234#if defined (OBJ_COFF) && defined (TE_PE)
4235 /* For some reason, the PE format does not store a section
24eab124 4236 address offset for a PC relative symbol. */
252b5132
RH		 4237 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4238 value += md_pcrel_from (fixP);
4239#endif
4240 }
4241
4242 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4243 and we must not dissappoint it. */
252b5132
RH		 4244#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4245 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4246 && fixP->fx_addsy)
47926f60
KH		 4247 switch (fixP->fx_r_type)
4248 {
4249 case BFD_RELOC_386_PLT32:
3e73aa7c 4250 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4251 /* Make the jump instruction point to the address of the operand. At
4252 runtime we merely add the offset to the actual PLT entry. */
4253 value = -4;
4254 break;
4255 case BFD_RELOC_386_GOTPC:
4256
4257/* This is tough to explain. We end up with this one if we have
252b5132
RH		 4258 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4259 * here is to obtain the absolute address of the GOT, and it is strongly
4260 * preferable from a performance point of view to avoid using a runtime
c3332e24 4261 * relocation for this. The actual sequence of instructions often look
252b5132 4262 * something like:
c3332e24 4263 *
24eab124 4264 * call .L66
252b5132 4265 * .L66:
24eab124
AM		 4266 * popl %ebx
4267 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
c3332e24 4268 *
24eab124 4269 * The call and pop essentially return the absolute address of
252b5132
RH		 4270 * the label .L66 and store it in %ebx. The linker itself will
4271 * ultimately change the first operand of the addl so that %ebx points to
4272 * the GOT, but to keep things simple, the .o file must have this operand
4273 * set so that it generates not the absolute address of .L66, but the
4274 * absolute address of itself. This allows the linker itself simply
4275 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4276 * added in, and the addend of the relocation is stored in the operand
4277 * field for the instruction itself.
c3332e24 4278 *
24eab124 4279 * Our job here is to fix the operand so that it would add the correct
252b5132
RH		 4280 * offset so that %ebx would point to itself. The thing that is tricky is
4281 * that .-.L66 will point to the beginning of the instruction, so we need
4282 * to further modify the operand so that it will point to itself.
4283 * There are other cases where you have something like:
c3332e24 4284 *
24eab124 4285 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
c3332e24 4286 *
252b5132 4287 * and here no correction would be required. Internally in the assembler
c3332e24 4288 * we treat operands of this form as not being pcrel since the '.' is
252b5132
RH		 4289 * explicitly mentioned, and I wonder whether it would simplify matters
4290 * to do it this way. Who knows. In earlier versions of the PIC patches,
4291 * the pcrel_adjust field was used to store the correction, but since the
47926f60
KH		 4292 * expression is not pcrel, I felt it would be confusing to do it this
4293 * way. */
4294
4295 value -= 1;
4296 break;
4297 case BFD_RELOC_386_GOT32:
3e73aa7c 4298 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4299 value = 0; /* Fully resolved at runtime. No addend. */
4300 break;
4301 case BFD_RELOC_386_GOTOFF:
3e73aa7c 4302 case BFD_RELOC_X86_64_GOTPCREL:
47926f60
KH		 4303 break;
4304
4305 case BFD_RELOC_VTABLE_INHERIT:
4306 case BFD_RELOC_VTABLE_ENTRY:
4307 fixP->fx_done = 0;
4308 return 1;
4309
4310 default:
4311 break;
4312 }
4313#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
93382f6d 4314 *valp = value;
47926f60 4315#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c
JH		 4316
4317#ifndef BFD_ASSEMBLER
252b5132 4318 md_number_to_chars (p, value, fixP->fx_size);
3e73aa7c
JH		 4319#else
4320 /* Are we finished with this relocation now? */
4321 if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0)
4322 fixP->fx_done = 1;
4323 else if (use_rela_relocations)
4324 {
4325 fixP->fx_no_overflow = 1;
4326 value = 0;
4327 }
4328 md_number_to_chars (p, value, fixP->fx_size);
4329#endif
252b5132
RH		 4330
4331 return 1;
4332}
252b5132 4333\f
252b5132
RH		 4334#define MAX_LITTLENUMS 6
4335
47926f60
KH		 4336/* Turn the string pointed to by litP into a floating point constant
4337 of type TYPE, and emit the appropriate bytes. The number of
4338 LITTLENUMS emitted is stored in *SIZEP. An error message is
4339 returned, or NULL on OK. */
4340
252b5132
RH		 4341char *
4342md_atof (type, litP, sizeP)
2ab9b79e 4343 int type;
252b5132
RH		 4344 char *litP;
4345 int *sizeP;
4346{
4347 int prec;
4348 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4349 LITTLENUM_TYPE *wordP;
4350 char *t;
4351
4352 switch (type)
4353 {
4354 case 'f':
4355 case 'F':
4356 prec = 2;
4357 break;
4358
4359 case 'd':
4360 case 'D':
4361 prec = 4;
4362 break;
4363
4364 case 'x':
4365 case 'X':
4366 prec = 5;
4367 break;
4368
4369 default:
4370 *sizeP = 0;
4371 return _("Bad call to md_atof ()");
4372 }
4373 t = atof_ieee (input_line_pointer, type, words);
4374 if (t)
4375 input_line_pointer = t;
4376
4377 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4378 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4379 the bigendian 386. */
4380 for (wordP = words + prec - 1; prec--;)
4381 {
4382 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4383 litP += sizeof (LITTLENUM_TYPE);
4384 }
4385 return 0;
4386}
4387\f
4388char output_invalid_buf[8];
4389
252b5132
RH		 4390static char *
4391output_invalid (c)
4392 int c;
4393{
4394 if (isprint (c))
4395 sprintf (output_invalid_buf, "'%c'", c);
4396 else
4397 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4398 return output_invalid_buf;
4399}
4400
af6bdddf 4401/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4402
4403static const reg_entry *
4404parse_register (reg_string, end_op)
4405 char *reg_string;
4406 char **end_op;
4407{
af6bdddf
AM		 4408 char *s = reg_string;
4409 char *p;
252b5132
RH		 4410 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4411 const reg_entry *r;
4412
4413 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4414 if (*s == REGISTER_PREFIX)
4415 ++s;
4416
4417 if (is_space_char (*s))
4418 ++s;
4419
4420 p = reg_name_given;
af6bdddf 4421 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4422 {
4423 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4424 return (const reg_entry *) NULL;
4425 s++;
252b5132
RH		 4426 }
4427
6588847e
DN		 4428 /* For naked regs, make sure that we are not dealing with an identifier.
4429 This prevents confusing an identifier like `eax_var' with register
4430 `eax'. */
4431 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4432 return (const reg_entry *) NULL;
4433
af6bdddf 4434 *end_op = s;
252b5132
RH		 4435
4436 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4437
5f47d35b 4438 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4439 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4440 {
5f47d35b
AM		 4441 if (is_space_char (*s))
4442 ++s;
4443 if (*s == '(')
4444 {
af6bdddf 4445 ++s;
5f47d35b
AM		 4446 if (is_space_char (*s))
4447 ++s;
4448 if (*s >= '0' && *s <= '7')
4449 {
4450 r = &i386_float_regtab[*s - '0'];
af6bdddf 4451 ++s;
5f47d35b
AM		 4452 if (is_space_char (*s))
4453 ++s;
4454 if (*s == ')')
4455 {
4456 *end_op = s + 1;
4457 return r;
4458 }
5f47d35b 4459 }
47926f60 4460 /* We have "%st(" then garbage. */
5f47d35b
AM		 4461 return (const reg_entry *) NULL;
4462 }
4463 }
4464
252b5132
RH		 4465 return r;
4466}
4467\f
4cc782b5 4468#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4469const char *md_shortopts = "kVQ:sq";
252b5132 4470#else
65172ab8 4471const char *md_shortopts = "q";
252b5132 4472#endif
6e0b89ee 4473
252b5132 4474struct option md_longopts[] = {
3e73aa7c
JH		 4475#define OPTION_32 (OPTION_MD_BASE + 0)
4476 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4477#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4478#define OPTION_64 (OPTION_MD_BASE + 1)
4479 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4480#endif
252b5132
RH		 4481 {NULL, no_argument, NULL, 0}
4482};
4483size_t md_longopts_size = sizeof (md_longopts);
4484
4485int
4486md_parse_option (c, arg)
4487 int c;
ab9da554 4488 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4489{
4490 switch (c)
4491 {
a38cf1db
AM		 4492 case 'q':
4493 quiet_warnings = 1;
252b5132
RH		 4494 break;
4495
4496#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4497 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4498 should be emitted or not. FIXME: Not implemented. */
4499 case 'Q':
252b5132
RH		 4500 break;
4501
4502 /* -V: SVR4 argument to print version ID. */
4503 case 'V':
4504 print_version_id ();
4505 break;
4506
a38cf1db
AM		 4507 /* -k: Ignore for FreeBSD compatibility. */
4508 case 'k':
252b5132 4509 break;
4cc782b5
ILT		 4510
4511 case 's':
4512 /* -s: On i386 Solaris, this tells the native assembler to use
4513 .stab instead of .stab.excl. We always use .stab anyhow. */
4514 break;
6e0b89ee 4515
3e73aa7c
JH		 4516 case OPTION_64:
4517 {
4518 const char **list, **l;
4519
3e73aa7c
JH		 4520 list = bfd_target_list ();
4521 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4522 if (strcmp (*l, "elf64-x86-64") == 0)
4523 {
4524 default_arch = "x86_64";
4525 break;
4526 }
3e73aa7c 4527 if (*l == NULL)
6e0b89ee 4528 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4529 free (list);
4530 }
4531 break;
4532#endif
252b5132 4533
6e0b89ee
AM		 4534 case OPTION_32:
4535 default_arch = "i386";
4536 break;
4537
252b5132
RH		 4538 default:
4539 return 0;
4540 }
4541 return 1;
4542}
4543
4544void
4545md_show_usage (stream)
4546 FILE *stream;
4547{
4cc782b5
ILT		 4548#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4549 fprintf (stream, _("\
a38cf1db
AM		 4550 -Q ignored\n\
4551 -V print assembler version number\n\
4552 -k ignored\n\
4553 -q quieten some warnings\n\
4554 -s ignored\n"));
4555#else
4556 fprintf (stream, _("\
4557 -q quieten some warnings\n"));
4cc782b5 4558#endif
252b5132
RH		 4559}
4560
4561#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4562#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4563 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4564
4565/* Pick the target format to use. */
4566
47926f60 4567const char *
252b5132
RH		 4568i386_target_format ()
4569{
3e73aa7c
JH		 4570 if (!strcmp (default_arch, "x86_64"))
4571 set_code_flag (CODE_64BIT);
4572 else if (!strcmp (default_arch, "i386"))
4573 set_code_flag (CODE_32BIT);
4574 else
4575 as_fatal (_("Unknown architecture"));
252b5132
RH		 4576 switch (OUTPUT_FLAVOR)
4577 {
4c63da97
AM		 4578#ifdef OBJ_MAYBE_AOUT
4579 case bfd_target_aout_flavour:
47926f60 4580 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4581#endif
4582#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4583 case bfd_target_coff_flavour:
4584 return "coff-i386";
4c63da97 4585#endif
3e73aa7c 4586#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4587 case bfd_target_elf_flavour:
3e73aa7c 4588 {
e5cb08ac
KH		 4589 if (flag_code == CODE_64BIT)
4590 use_rela_relocations = 1;
4591 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
3e73aa7c 4592 }
4c63da97 4593#endif
252b5132
RH		 4594 default:
4595 abort ();
4596 return NULL;
4597 }
4598}
4599
47926f60
KH		 4600#endif /* OBJ_MAYBE_ more than one */
4601#endif /* BFD_ASSEMBLER */
252b5132 4602\f
252b5132
RH		 4603symbolS *
4604md_undefined_symbol (name)
4605 char *name;
4606{
18dc2407
ILT		 4607 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4608 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4609 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4610 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 4611 {
4612 if (!GOT_symbol)
4613 {
4614 if (symbol_find (name))
4615 as_bad (_("GOT already in symbol table"));
4616 GOT_symbol = symbol_new (name, undefined_section,
4617 (valueT) 0, &zero_address_frag);
4618 };
4619 return GOT_symbol;
4620 }
252b5132
RH		 4621 return 0;
4622}
4623
4624/* Round up a section size to the appropriate boundary. */
47926f60 4625
252b5132
RH		 4626valueT
4627md_section_align (segment, size)
ab9da554 4628 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 4629 valueT size;
4630{
252b5132 4631#ifdef BFD_ASSEMBLER
4c63da97
AM		 4632#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4633 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4634 {
4635 /* For a.out, force the section size to be aligned. If we don't do
4636 this, BFD will align it for us, but it will not write out the
4637 final bytes of the section. This may be a bug in BFD, but it is
4638 easier to fix it here since that is how the other a.out targets
4639 work. */
4640 int align;
4641
4642 align = bfd_get_section_alignment (stdoutput, segment);
4643 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4644 }
252b5132
RH		 4645#endif
4646#endif
4647
4648 return size;
4649}
4650
4651/* On the i386, PC-relative offsets are relative to the start of the
4652 next instruction. That is, the address of the offset, plus its
4653 size, since the offset is always the last part of the insn. */
4654
4655long
4656md_pcrel_from (fixP)
4657 fixS *fixP;
4658{
4659 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4660}
4661
4662#ifndef I386COFF
4663
4664static void
4665s_bss (ignore)
ab9da554 4666 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4667{
4668 register int temp;
4669
4670 temp = get_absolute_expression ();
4671 subseg_set (bss_section, (subsegT) temp);
4672 demand_empty_rest_of_line ();
4673}
4674
4675#endif
4676
252b5132
RH		 4677#ifdef BFD_ASSEMBLER
4678
4679void
4680i386_validate_fix (fixp)
4681 fixS *fixp;
4682{
4683 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
4684 {
3e73aa7c 4685 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 4686 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
4687 {
4688 if (flag_code != CODE_64BIT)
4689 abort ();
4690 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
4691 }
4692 else
4693 {
4694 if (flag_code == CODE_64BIT)
4695 abort ();
4696 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
4697 }
252b5132
RH		 4698 fixp->fx_subsy = 0;
4699 }
4700}
4701
252b5132
RH		 4702arelent *
4703tc_gen_reloc (section, fixp)
ab9da554 4704 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 4705 fixS *fixp;
4706{
4707 arelent *rel;
4708 bfd_reloc_code_real_type code;
4709
4710 switch (fixp->fx_r_type)
4711 {
3e73aa7c
JH		 4712 case BFD_RELOC_X86_64_PLT32:
4713 case BFD_RELOC_X86_64_GOT32:
4714 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 4715 case BFD_RELOC_386_PLT32:
4716 case BFD_RELOC_386_GOT32:
4717 case BFD_RELOC_386_GOTOFF:
4718 case BFD_RELOC_386_GOTPC:
3e73aa7c 4719 case BFD_RELOC_X86_64_32S:
252b5132
RH		 4720 case BFD_RELOC_RVA:
4721 case BFD_RELOC_VTABLE_ENTRY:
4722 case BFD_RELOC_VTABLE_INHERIT:
4723 code = fixp->fx_r_type;
4724 break;
4725 default:
93382f6d 4726 if (fixp->fx_pcrel)
252b5132 4727 {
93382f6d
AM		 4728 switch (fixp->fx_size)
4729 {
4730 default:
d0b47220 4731 as_bad (_("can not do %d byte pc-relative relocation"),
93382f6d
AM		 4732 fixp->fx_size);
4733 code = BFD_RELOC_32_PCREL;
4734 break;
4735 case 1: code = BFD_RELOC_8_PCREL; break;
4736 case 2: code = BFD_RELOC_16_PCREL; break;
4737 case 4: code = BFD_RELOC_32_PCREL; break;
4738 }
4739 }
4740 else
4741 {
4742 switch (fixp->fx_size)
4743 {
4744 default:
d0b47220 4745 as_bad (_("can not do %d byte relocation"), fixp->fx_size);
93382f6d
AM		 4746 code = BFD_RELOC_32;
4747 break;
4748 case 1: code = BFD_RELOC_8; break;
4749 case 2: code = BFD_RELOC_16; break;
4750 case 4: code = BFD_RELOC_32; break;
3e73aa7c 4751 case 8: code = BFD_RELOC_64; break;
93382f6d 4752 }
252b5132
RH		 4753 }
4754 break;
4755 }
252b5132
RH		 4756
4757 if (code == BFD_RELOC_32
4758 && GOT_symbol
4759 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 4760 {
4761 /* We don't support GOTPC on 64bit targets. */
4762 if (flag_code == CODE_64BIT)
bfb32b52 4763 abort ();
3e73aa7c
JH		 4764 code = BFD_RELOC_386_GOTPC;
4765 }
252b5132
RH		 4766
4767 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 4768 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
4769 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 4770
4771 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 4772 if (!use_rela_relocations)
4773 {
4774 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4775 vtable entry to be used in the relocation's section offset. */
4776 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4777 rel->address = fixp->fx_offset;
252b5132 4778
3e73aa7c
JH		 4779 if (fixp->fx_pcrel)
4780 rel->addend = fixp->fx_addnumber;
4781 else
4782 rel->addend = 0;
4783 }
4784 /* Use the rela in 64bit mode. */
252b5132 4785 else
3e73aa7c
JH		 4786 {
4787 rel->addend = fixp->fx_offset;
3e73aa7c
JH		 4788 if (fixp->fx_pcrel)
4789 rel->addend -= fixp->fx_size;
4790 }
4791
252b5132
RH		 4792 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
4793 if (rel->howto == NULL)
4794 {
4795 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 4796 _("cannot represent relocation type %s"),
252b5132
RH		 4797 bfd_get_reloc_code_name (code));
4798 /* Set howto to a garbage value so that we can keep going. */
4799 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
4800 assert (rel->howto != NULL);
4801 }
4802
4803 return rel;
4804}
4805
47926f60 4806#else /* ! BFD_ASSEMBLER */
252b5132
RH		 4807
4808#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4809void
4810tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4811 char *where;
4812 fixS *fixP;
4813 relax_addressT segment_address_in_file;
4814{
47926f60
KH		 4815 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4816 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 4817
47926f60 4818 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 4819 long r_symbolnum;
4820
4821 know (fixP->fx_addsy != NULL);
4822
4823 md_number_to_chars (where,
4824 (valueT) (fixP->fx_frag->fr_address
4825 + fixP->fx_where - segment_address_in_file),
4826 4);
4827
4828 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4829 ? S_GET_TYPE (fixP->fx_addsy)
4830 : fixP->fx_addsy->sy_number);
4831
4832 where[6] = (r_symbolnum >> 16) & 0x0ff;
4833 where[5] = (r_symbolnum >> 8) & 0x0ff;
4834 where[4] = r_symbolnum & 0x0ff;
4835 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
4836 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
4837 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
4838}
4839
47926f60 4840#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 4841
4842#if defined (I386COFF)
4843
4844short
4845tc_coff_fix2rtype (fixP)
4846 fixS *fixP;
4847{
4848 if (fixP->fx_r_type == R_IMAGEBASE)
4849 return R_IMAGEBASE;
4850
4851 return (fixP->fx_pcrel ?
4852 (fixP->fx_size == 1 ? R_PCRBYTE :
4853 fixP->fx_size == 2 ? R_PCRWORD :
4854 R_PCRLONG) :
4855 (fixP->fx_size == 1 ? R_RELBYTE :
4856 fixP->fx_size == 2 ? R_RELWORD :
4857 R_DIR32));
4858}
4859
4860int
4861tc_coff_sizemachdep (frag)
4862 fragS *frag;
4863{
4864 if (frag->fr_next)
4865 return (frag->fr_next->fr_address - frag->fr_address);
4866 else
4867 return 0;
4868}
4869
47926f60 4870#endif /* I386COFF */
252b5132 4871
47926f60 4872#endif /* ! BFD_ASSEMBLER */
64a0c779
DN		 4873\f
4874/* Parse operands using Intel syntax. This implements a recursive descent
4875 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4876 Programmer's Guide.
4877
4878 FIXME: We do not recognize the full operand grammar defined in the MASM
4879 documentation. In particular, all the structure/union and
4880 high-level macro operands are missing.
4881
4882 Uppercase words are terminals, lower case words are non-terminals.
4883 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4884 bars '|' denote choices. Most grammar productions are implemented in
4885 functions called 'intel_<production>'.
4886
4887 Initial production is 'expr'.
4888
64a0c779
DN		 4889 addOp + | -
4890
4891 alpha [a-zA-Z]
4892
4893 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4894
4895 constant digits [[ radixOverride ]]
4896
4897 dataType BYTE | WORD | DWORD | QWORD | XWORD
4898
4899 digits decdigit
b77a7acd
AJ		 4900 | digits decdigit
4901 | digits hexdigit
64a0c779
DN		 4902
4903 decdigit [0-9]
4904
4905 e05 e05 addOp e06
b77a7acd 4906 | e06
64a0c779
DN		 4907
4908 e06 e06 mulOp e09
b77a7acd 4909 | e09
64a0c779
DN		 4910
4911 e09 OFFSET e10
4912 | e09 PTR e10
4913 | e09 : e10
4914 | e10
4915
4916 e10 e10 [ expr ]
b77a7acd 4917 | e11
64a0c779
DN		 4918
4919 e11 ( expr )
b77a7acd 4920 | [ expr ]
64a0c779
DN		 4921 | constant
4922 | dataType
4923 | id
4924 | $
4925 | register
4926
4927 => expr SHORT e05
b77a7acd 4928 | e05
64a0c779
DN		 4929
4930 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 4931 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 4932
4933 hexdigit a | b | c | d | e | f
b77a7acd 4934 | A | B | C | D | E | F
64a0c779
DN		 4935
4936 id alpha
b77a7acd 4937 | id alpha
64a0c779
DN		 4938 | id decdigit
4939
4940 mulOp * | / | MOD
4941
4942 quote " | '
4943
4944 register specialRegister
b77a7acd 4945 | gpRegister
64a0c779
DN		 4946 | byteRegister
4947
4948 segmentRegister CS | DS | ES | FS | GS | SS
4949
4950 specialRegister CR0 | CR2 | CR3
b77a7acd 4951 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 4952 | TR3 | TR4 | TR5 | TR6 | TR7
4953
64a0c779
DN		 4954 We simplify the grammar in obvious places (e.g., register parsing is
4955 done by calling parse_register) and eliminate immediate left recursion
4956 to implement a recursive-descent parser.
4957
4958 expr SHORT e05
b77a7acd 4959 | e05
64a0c779
DN		 4960
4961 e05 e06 e05'
4962
4963 e05' addOp e06 e05'
b77a7acd 4964 | Empty
64a0c779
DN		 4965
4966 e06 e09 e06'
4967
4968 e06' mulOp e09 e06'
b77a7acd 4969 | Empty
64a0c779
DN		 4970
4971 e09 OFFSET e10 e09'
b77a7acd 4972 | e10 e09'
64a0c779
DN		 4973
4974 e09' PTR e10 e09'
b77a7acd 4975 | : e10 e09'
64a0c779
DN		 4976 | Empty
4977
4978 e10 e11 e10'
4979
4980 e10' [ expr ] e10'
b77a7acd 4981 | Empty
64a0c779
DN		 4982
4983 e11 ( expr )
b77a7acd 4984 | [ expr ]
64a0c779
DN		 4985 | BYTE
4986 | WORD
4987 | DWORD
4988 | QWORD
4989 | XWORD
4990 | .
4991 | $
4992 | register
4993 | id
4994 | constant */
4995
4996/* Parsing structure for the intel syntax parser. Used to implement the
4997 semantic actions for the operand grammar. */
4998struct intel_parser_s
4999 {
5000 char *op_string; /* The string being parsed. */
5001 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5002 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5003 int is_mem; /* 1 if operand is memory reference. */
5004 const reg_entry *reg; /* Last register reference found. */
5005 char *disp; /* Displacement string being built. */
5006 };
5007
5008static struct intel_parser_s intel_parser;
5009
5010/* Token structure for parsing intel syntax. */
5011struct intel_token
5012 {
5013 int code; /* Token code. */
5014 const reg_entry *reg; /* Register entry for register tokens. */
5015 char *str; /* String representation. */
5016 };
5017
5018static struct intel_token cur_token, prev_token;
5019
50705ef4
AM		 5020/* Token codes for the intel parser. Since T_SHORT is already used
5021 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5022#define T_NIL -1
5023#define T_CONST 1
5024#define T_REG 2
5025#define T_BYTE 3
5026#define T_WORD 4
5027#define T_DWORD 5
5028#define T_QWORD 6
5029#define T_XWORD 7
50705ef4 5030#undef T_SHORT
64a0c779
DN		 5031#define T_SHORT 8
5032#define T_OFFSET 9
5033#define T_PTR 10
5034#define T_ID 11
5035
5036/* Prototypes for intel parser functions. */
5037static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5038static void intel_get_token PARAMS ((void));
5039static void intel_putback_token PARAMS ((void));
5040static int intel_expr PARAMS ((void));
5041static int intel_e05 PARAMS ((void));
5042static int intel_e05_1 PARAMS ((void));
5043static int intel_e06 PARAMS ((void));
5044static int intel_e06_1 PARAMS ((void));
5045static int intel_e09 PARAMS ((void));
5046static int intel_e09_1 PARAMS ((void));
5047static int intel_e10 PARAMS ((void));
5048static int intel_e10_1 PARAMS ((void));
5049static int intel_e11 PARAMS ((void));
64a0c779 5050
64a0c779
DN		 5051static int
5052i386_intel_operand (operand_string, got_a_float)
5053 char *operand_string;
5054 int got_a_float;
5055{
5056 int ret;
5057 char *p;
5058
5059 /* Initialize token holders. */
5060 cur_token.code = prev_token.code = T_NIL;
5061 cur_token.reg = prev_token.reg = NULL;
5062 cur_token.str = prev_token.str = NULL;
5063
5064 /* Initialize parser structure. */
e5cb08ac 5065 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5066 if (p == NULL)
5067 abort ();
5068 strcpy (intel_parser.op_string, operand_string);
5069 intel_parser.got_a_float = got_a_float;
5070 intel_parser.op_modifier = -1;
5071 intel_parser.is_mem = 0;
5072 intel_parser.reg = NULL;
e5cb08ac 5073 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5074 if (intel_parser.disp == NULL)
5075 abort ();
5076 intel_parser.disp[0] = '\0';
5077
5078 /* Read the first token and start the parser. */
5079 intel_get_token ();
5080 ret = intel_expr ();
5081
5082 if (ret)
5083 {
5084 /* If we found a memory reference, hand it over to i386_displacement
5085 to fill in the rest of the operand fields. */
5086 if (intel_parser.is_mem)
5087 {
5088 if ((i.mem_operands == 1
5089 && (current_templates->start->opcode_modifier & IsString) == 0)
5090 || i.mem_operands == 2)
5091 {
5092 as_bad (_("too many memory references for '%s'"),
5093 current_templates->start->name);
5094 ret = 0;
5095 }
5096 else
5097 {
5098 char *s = intel_parser.disp;
5099 i.mem_operands++;
5100
5101 /* Add the displacement expression. */
5102 if (*s != '\0')
5103 ret = i386_displacement (s, s + strlen (s))
5104 && i386_index_check (s);
5105 }
5106 }
5107
5108 /* Constant and OFFSET expressions are handled by i386_immediate. */
5109 else if (intel_parser.op_modifier == OFFSET_FLAT
5110 || intel_parser.reg == NULL)
5111 ret = i386_immediate (intel_parser.disp);
5112 }
5113
5114 free (p);
5115 free (intel_parser.disp);
5116
5117 return ret;
5118}
5119
64a0c779 5120/* expr SHORT e05
b77a7acd 5121 | e05 */
64a0c779
DN		 5122static int
5123intel_expr ()
5124{
5125 /* expr SHORT e05 */
5126 if (cur_token.code == T_SHORT)
5127 {
5128 intel_parser.op_modifier = SHORT;
5129 intel_match_token (T_SHORT);
5130
5131 return (intel_e05 ());
5132 }
5133
5134 /* expr e05 */
5135 else
5136 return intel_e05 ();
5137}
5138
64a0c779
DN		 5139/* e05 e06 e05'
5140
4a1805b1 5141 e05' addOp e06 e05'
64a0c779
DN		 5142 | Empty */
5143static int
5144intel_e05 ()
5145{
5146 return (intel_e06 () && intel_e05_1 ());
5147}
5148
5149static int
5150intel_e05_1 ()
5151{
5152 /* e05' addOp e06 e05' */
5153 if (cur_token.code == '+' || cur_token.code == '-')
5154 {
5155 strcat (intel_parser.disp, cur_token.str);
5156 intel_match_token (cur_token.code);
5157
5158 return (intel_e06 () && intel_e05_1 ());
5159 }
5160
5161 /* e05' Empty */
5162 else
5163 return 1;
4a1805b1 5164}
64a0c779
DN		 5165
5166/* e06 e09 e06'
5167
5168 e06' mulOp e09 e06'
b77a7acd 5169 | Empty */
64a0c779
DN		 5170static int
5171intel_e06 ()
5172{
5173 return (intel_e09 () && intel_e06_1 ());
5174}
5175
5176static int
5177intel_e06_1 ()
5178{
5179 /* e06' mulOp e09 e06' */
5180 if (cur_token.code == '*' || cur_token.code == '/')
5181 {
5182 strcat (intel_parser.disp, cur_token.str);
5183 intel_match_token (cur_token.code);
5184
5185 return (intel_e09 () && intel_e06_1 ());
5186 }
4a1805b1 5187
64a0c779 5188 /* e06' Empty */
4a1805b1 5189 else
64a0c779
DN		 5190 return 1;
5191}
5192
64a0c779 5193/* e09 OFFSET e10 e09'
b77a7acd 5194 | e10 e09'
64a0c779
DN		 5195
5196 e09' PTR e10 e09'
b77a7acd 5197 | : e10 e09'
64a0c779
DN		 5198 | Empty */
5199static int
5200intel_e09 ()
5201{
5202 /* e09 OFFSET e10 e09' */
5203 if (cur_token.code == T_OFFSET)
5204 {
5205 intel_parser.is_mem = 0;
5206 intel_parser.op_modifier = OFFSET_FLAT;
5207 intel_match_token (T_OFFSET);
5208
5209 return (intel_e10 () && intel_e09_1 ());
5210 }
5211
5212 /* e09 e10 e09' */
5213 else
5214 return (intel_e10 () && intel_e09_1 ());
5215}
5216
5217static int
5218intel_e09_1 ()
5219{
5220 /* e09' PTR e10 e09' */
5221 if (cur_token.code == T_PTR)
5222 {
5223 if (prev_token.code == T_BYTE)
5224 i.suffix = BYTE_MNEM_SUFFIX;
5225
5226 else if (prev_token.code == T_WORD)
5227 {
5228 if (intel_parser.got_a_float == 2) /* "fi..." */
5229 i.suffix = SHORT_MNEM_SUFFIX;
5230 else
5231 i.suffix = WORD_MNEM_SUFFIX;
5232 }
5233
5234 else if (prev_token.code == T_DWORD)
5235 {
5236 if (intel_parser.got_a_float == 1) /* "f..." */
5237 i.suffix = SHORT_MNEM_SUFFIX;
5238 else
5239 i.suffix = LONG_MNEM_SUFFIX;
5240 }
5241
5242 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5243 {
5244 if (intel_parser.got_a_float == 1) /* "f..." */
5245 i.suffix = LONG_MNEM_SUFFIX;
5246 else
3e73aa7c 5247 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5248 }
64a0c779
DN		 5249
5250 else if (prev_token.code == T_XWORD)
5251 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5252
5253 else
5254 {
5255 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5256 return 0;
5257 }
5258
5259 intel_match_token (T_PTR);
5260
5261 return (intel_e10 () && intel_e09_1 ());
5262 }
5263
5264 /* e09 : e10 e09' */
5265 else if (cur_token.code == ':')
5266 {
21d6c4af
DN		 5267 /* Mark as a memory operand only if it's not already known to be an
5268 offset expression. */
5269 if (intel_parser.op_modifier != OFFSET_FLAT)
5270 intel_parser.is_mem = 1;
64a0c779
DN		 5271
5272 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5273 }
5274
5275 /* e09' Empty */
5276 else
5277 return 1;
5278}
5279
5280/* e10 e11 e10'
5281
5282 e10' [ expr ] e10'
b77a7acd 5283 | Empty */
64a0c779
DN		 5284static int
5285intel_e10 ()
5286{
5287 return (intel_e11 () && intel_e10_1 ());
5288}
5289
5290static int
5291intel_e10_1 ()
5292{
5293 /* e10' [ expr ] e10' */
5294 if (cur_token.code == '[')
5295 {
5296 intel_match_token ('[');
21d6c4af
DN		 5297
5298 /* Mark as a memory operand only if it's not already known to be an
5299 offset expression. If it's an offset expression, we need to keep
5300 the brace in. */
5301 if (intel_parser.op_modifier != OFFSET_FLAT)
5302 intel_parser.is_mem = 1;
5303 else
5304 strcat (intel_parser.disp, "[");
4a1805b1 5305
64a0c779 5306 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5307 if (*intel_parser.disp != '\0'
5308 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5309 strcat (intel_parser.disp, "+");
5310
21d6c4af
DN		 5311 if (intel_expr () && intel_match_token (']'))
5312 {
5313 /* Preserve brackets when the operand is an offset expression. */
5314 if (intel_parser.op_modifier == OFFSET_FLAT)
5315 strcat (intel_parser.disp, "]");
5316
5317 return intel_e10_1 ();
5318 }
5319 else
5320 return 0;
64a0c779
DN		 5321 }
5322
5323 /* e10' Empty */
5324 else
5325 return 1;
5326}
5327
64a0c779 5328/* e11 ( expr )
b77a7acd 5329 | [ expr ]
64a0c779
DN		 5330 | BYTE
5331 | WORD
5332 | DWORD
5333 | QWORD
5334 | XWORD
4a1805b1 5335 | $
64a0c779
DN		 5336 | .
5337 | register
5338 | id
5339 | constant */
5340static int
5341intel_e11 ()
5342{
5343 /* e11 ( expr ) */
5344 if (cur_token.code == '(')
5345 {
5346 intel_match_token ('(');
5347 strcat (intel_parser.disp, "(");
5348
5349 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5350 {
5351 strcat (intel_parser.disp, ")");
5352 return 1;
5353 }
64a0c779
DN		 5354 else
5355 return 0;
5356 }
5357
5358 /* e11 [ expr ] */
5359 else if (cur_token.code == '[')
5360 {
5361 intel_match_token ('[');
21d6c4af
DN		 5362
5363 /* Mark as a memory operand only if it's not already known to be an
5364 offset expression. If it's an offset expression, we need to keep
5365 the brace in. */
5366 if (intel_parser.op_modifier != OFFSET_FLAT)
5367 intel_parser.is_mem = 1;
5368 else
5369 strcat (intel_parser.disp, "[");
4a1805b1 5370
64a0c779
DN		 5371 /* Operands for jump/call inside brackets denote absolute addresses. */
5372 if (current_templates->start->opcode_modifier & Jump
5373 || current_templates->start->opcode_modifier & JumpDword
5374 || current_templates->start->opcode_modifier & JumpByte
5375 || current_templates->start->opcode_modifier & JumpInterSegment)
5376 i.types[this_operand] |= JumpAbsolute;
5377
5378 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5379 if (*intel_parser.disp != '\0'
5380 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5381 strcat (intel_parser.disp, "+");
5382
21d6c4af
DN		 5383 if (intel_expr () && intel_match_token (']'))
5384 {
5385 /* Preserve brackets when the operand is an offset expression. */
5386 if (intel_parser.op_modifier == OFFSET_FLAT)
5387 strcat (intel_parser.disp, "]");
5388
5389 return 1;
5390 }
5391 else
5392 return 0;
64a0c779
DN		 5393 }
5394
4a1805b1 5395 /* e11 BYTE
64a0c779
DN		 5396 | WORD
5397 | DWORD
5398 | QWORD
5399 | XWORD */
5400 else if (cur_token.code == T_BYTE
5401 || cur_token.code == T_WORD
5402 || cur_token.code == T_DWORD
5403 || cur_token.code == T_QWORD
5404 || cur_token.code == T_XWORD)
5405 {
5406 intel_match_token (cur_token.code);
5407
5408 return 1;
5409 }
5410
5411 /* e11 $
5412 | . */
5413 else if (cur_token.code == '$' || cur_token.code == '.')
5414 {
5415 strcat (intel_parser.disp, cur_token.str);
5416 intel_match_token (cur_token.code);
21d6c4af
DN		 5417
5418 /* Mark as a memory operand only if it's not already known to be an
5419 offset expression. */
5420 if (intel_parser.op_modifier != OFFSET_FLAT)
5421 intel_parser.is_mem = 1;
64a0c779
DN		 5422
5423 return 1;
5424 }
5425
5426 /* e11 register */
5427 else if (cur_token.code == T_REG)
5428 {
5429 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5430
5431 intel_match_token (T_REG);
5432
5433 /* Check for segment change. */
5434 if (cur_token.code == ':')
5435 {
5436 if (reg->reg_type & (SReg2 | SReg3))
5437 {
5438 switch (reg->reg_num)
5439 {
5440 case 0:
5441 i.seg[i.mem_operands] = &es;
5442 break;
5443 case 1:
5444 i.seg[i.mem_operands] = &cs;
5445 break;
5446 case 2:
5447 i.seg[i.mem_operands] = &ss;
5448 break;
5449 case 3:
5450 i.seg[i.mem_operands] = &ds;
5451 break;
5452 case 4:
5453 i.seg[i.mem_operands] = &fs;
5454 break;
5455 case 5:
5456 i.seg[i.mem_operands] = &gs;
5457 break;
5458 }
5459 }
5460 else
5461 {
5462 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5463 return 0;
5464 }
5465 }
5466
5467 /* Not a segment register. Check for register scaling. */
5468 else if (cur_token.code == '*')
5469 {
5470 if (!intel_parser.is_mem)
5471 {
5472 as_bad (_("Register scaling only allowed in memory operands."));
5473 return 0;
5474 }
5475
4a1805b1 5476 /* What follows must be a valid scale. */
64a0c779
DN		 5477 if (intel_match_token ('*')
5478 && strchr ("01248", *cur_token.str))
5479 {
5480 i.index_reg = reg;
5481 i.types[this_operand] |= BaseIndex;
5482
5483 /* Set the scale after setting the register (otherwise,
5484 i386_scale will complain) */
5485 i386_scale (cur_token.str);
5486 intel_match_token (T_CONST);
5487 }
5488 else
5489 {
5490 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5491 cur_token.str);
5492 return 0;
5493 }
5494 }
5495
5496 /* No scaling. If this is a memory operand, the register is either a
5497 base register (first occurrence) or an index register (second
5498 occurrence). */
5499 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5500 {
5501 if (i.base_reg && i.index_reg)
5502 {
5503 as_bad (_("Too many register references in memory operand.\n"));
5504 return 0;
5505 }
5506
5507 if (i.base_reg == NULL)
5508 i.base_reg = reg;
5509 else
5510 i.index_reg = reg;
5511
5512 i.types[this_operand] |= BaseIndex;
5513 }
5514
5515 /* Offset modifier. Add the register to the displacement string to be
5516 parsed as an immediate expression after we're done. */
5517 else if (intel_parser.op_modifier == OFFSET_FLAT)
5518 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5519
64a0c779
DN		 5520 /* It's neither base nor index nor offset. */
5521 else
5522 {
5523 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5524 i.op[this_operand].regs = reg;
5525 i.reg_operands++;
5526 }
5527
5528 /* Since registers are not part of the displacement string (except
5529 when we're parsing offset operands), we may need to remove any
5530 preceding '+' from the displacement string. */
5531 if (*intel_parser.disp != '\0'
5532 && intel_parser.op_modifier != OFFSET_FLAT)
5533 {
5534 char *s = intel_parser.disp;
5535 s += strlen (s) - 1;
5536 if (*s == '+')
5537 *s = '\0';
5538 }
5539
5540 return 1;
5541 }
4a1805b1 5542
64a0c779
DN		 5543 /* e11 id */
5544 else if (cur_token.code == T_ID)
5545 {
5546 /* Add the identifier to the displacement string. */
5547 strcat (intel_parser.disp, cur_token.str);
5548 intel_match_token (T_ID);
5549
5550 /* The identifier represents a memory reference only if it's not
5551 preceded by an offset modifier. */
21d6c4af 5552 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 5553 intel_parser.is_mem = 1;
5554
5555 return 1;
5556 }
5557
5558 /* e11 constant */
5559 else if (cur_token.code == T_CONST
e5cb08ac 5560 || cur_token.code == '-'
64a0c779
DN		 5561 || cur_token.code == '+')
5562 {
5563 char *save_str;
5564
5565 /* Allow constants that start with `+' or `-'. */
5566 if (cur_token.code == '-' || cur_token.code == '+')
5567 {
5568 strcat (intel_parser.disp, cur_token.str);
5569 intel_match_token (cur_token.code);
5570 if (cur_token.code != T_CONST)
5571 {
5572 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5573 cur_token.str);
5574 return 0;
5575 }
5576 }
5577
e5cb08ac 5578 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 5579 if (save_str == NULL)
bc805888 5580 abort ();
64a0c779
DN		 5581 strcpy (save_str, cur_token.str);
5582
5583 /* Get the next token to check for register scaling. */
5584 intel_match_token (cur_token.code);
5585
5586 /* Check if this constant is a scaling factor for an index register. */
5587 if (cur_token.code == '*')
5588 {
5589 if (intel_match_token ('*') && cur_token.code == T_REG)
5590 {
5591 if (!intel_parser.is_mem)
5592 {
5593 as_bad (_("Register scaling only allowed in memory operands."));
5594 return 0;
5595 }
5596
4a1805b1 5597 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 5598 a valid scale. */
5599 if (strchr ("01248", *save_str))
5600 {
5601 i.index_reg = cur_token.reg;
5602 i.types[this_operand] |= BaseIndex;
5603
5604 /* Set the scale after setting the register (otherwise,
5605 i386_scale will complain) */
5606 i386_scale (save_str);
5607 intel_match_token (T_REG);
5608
5609 /* Since registers are not part of the displacement
5610 string, we may need to remove any preceding '+' from
5611 the displacement string. */
5612 if (*intel_parser.disp != '\0')
5613 {
5614 char *s = intel_parser.disp;
5615 s += strlen (s) - 1;
5616 if (*s == '+')
5617 *s = '\0';
5618 }
5619
5620 free (save_str);
5621
5622 return 1;
5623 }
5624 else
5625 return 0;
5626 }
5627
5628 /* The constant was not used for register scaling. Since we have
5629 already consumed the token following `*' we now need to put it
5630 back in the stream. */
5631 else
5632 intel_putback_token ();
5633 }
5634
5635 /* Add the constant to the displacement string. */
5636 strcat (intel_parser.disp, save_str);
5637 free (save_str);
5638
5639 return 1;
5640 }
5641
64a0c779
DN		 5642 as_bad (_("Unrecognized token '%s'"), cur_token.str);
5643 return 0;
5644}
5645
64a0c779
DN		 5646/* Match the given token against cur_token. If they match, read the next
5647 token from the operand string. */
5648static int
5649intel_match_token (code)
e5cb08ac 5650 int code;
64a0c779
DN		 5651{
5652 if (cur_token.code == code)
5653 {
5654 intel_get_token ();
5655 return 1;
5656 }
5657 else
5658 {
5659 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
5660 return 0;
5661 }
5662}
5663
64a0c779
DN		 5664/* Read a new token from intel_parser.op_string and store it in cur_token. */
5665static void
5666intel_get_token ()
5667{
5668 char *end_op;
5669 const reg_entry *reg;
5670 struct intel_token new_token;
5671
5672 new_token.code = T_NIL;
5673 new_token.reg = NULL;
5674 new_token.str = NULL;
5675
4a1805b1 5676 /* Free the memory allocated to the previous token and move
64a0c779
DN		 5677 cur_token to prev_token. */
5678 if (prev_token.str)
5679 free (prev_token.str);
5680
5681 prev_token = cur_token;
5682
5683 /* Skip whitespace. */
5684 while (is_space_char (*intel_parser.op_string))
5685 intel_parser.op_string++;
5686
5687 /* Return an empty token if we find nothing else on the line. */
5688 if (*intel_parser.op_string == '\0')
5689 {
5690 cur_token = new_token;
5691 return;
5692 }
5693
5694 /* The new token cannot be larger than the remainder of the operand
5695 string. */
e5cb08ac 5696 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 5697 if (new_token.str == NULL)
bc805888 5698 abort ();
64a0c779
DN		 5699 new_token.str[0] = '\0';
5700
5701 if (strchr ("0123456789", *intel_parser.op_string))
5702 {
5703 char *p = new_token.str;
5704 char *q = intel_parser.op_string;
5705 new_token.code = T_CONST;
5706
5707 /* Allow any kind of identifier char to encompass floating point and
5708 hexadecimal numbers. */
5709 while (is_identifier_char (*q))
5710 *p++ = *q++;
5711 *p = '\0';
5712
5713 /* Recognize special symbol names [0-9][bf]. */
5714 if (strlen (intel_parser.op_string) == 2
4a1805b1 5715 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 5716 || intel_parser.op_string[1] == 'f'))
5717 new_token.code = T_ID;
5718 }
5719
5720 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
5721 {
5722 new_token.code = *intel_parser.op_string;
5723 new_token.str[0] = *intel_parser.op_string;
5724 new_token.str[1] = '\0';
5725 }
5726
5727 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
5728 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
5729 {
5730 new_token.code = T_REG;
5731 new_token.reg = reg;
5732
5733 if (*intel_parser.op_string == REGISTER_PREFIX)
5734 {
5735 new_token.str[0] = REGISTER_PREFIX;
5736 new_token.str[1] = '\0';
5737 }
5738
5739 strcat (new_token.str, reg->reg_name);
5740 }
5741
5742 else if (is_identifier_char (*intel_parser.op_string))
5743 {
5744 char *p = new_token.str;
5745 char *q = intel_parser.op_string;
5746
5747 /* A '.' or '$' followed by an identifier char is an identifier.
5748 Otherwise, it's operator '.' followed by an expression. */
5749 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
5750 {
5751 new_token.code = *q;
5752 new_token.str[0] = *q;
5753 new_token.str[1] = '\0';
5754 }
5755 else
5756 {
5757 while (is_identifier_char (*q) || *q == '@')
5758 *p++ = *q++;
5759 *p = '\0';
5760
5761 if (strcasecmp (new_token.str, "BYTE") == 0)
5762 new_token.code = T_BYTE;
5763
5764 else if (strcasecmp (new_token.str, "WORD") == 0)
5765 new_token.code = T_WORD;
5766
5767 else if (strcasecmp (new_token.str, "DWORD") == 0)
5768 new_token.code = T_DWORD;
5769
5770 else if (strcasecmp (new_token.str, "QWORD") == 0)
5771 new_token.code = T_QWORD;
5772
5773 else if (strcasecmp (new_token.str, "XWORD") == 0)
5774 new_token.code = T_XWORD;
5775
5776 else if (strcasecmp (new_token.str, "PTR") == 0)
5777 new_token.code = T_PTR;
5778
5779 else if (strcasecmp (new_token.str, "SHORT") == 0)
5780 new_token.code = T_SHORT;
5781
5782 else if (strcasecmp (new_token.str, "OFFSET") == 0)
5783 {
5784 new_token.code = T_OFFSET;
5785
5786 /* ??? This is not mentioned in the MASM grammar but gcc
5787 makes use of it with -mintel-syntax. OFFSET may be
5788 followed by FLAT: */
5789 if (strncasecmp (q, " FLAT:", 6) == 0)
5790 strcat (new_token.str, " FLAT:");
5791 }
5792
5793 /* ??? This is not mentioned in the MASM grammar. */
5794 else if (strcasecmp (new_token.str, "FLAT") == 0)
5795 new_token.code = T_OFFSET;
5796
5797 else
5798 new_token.code = T_ID;
5799 }
5800 }
5801
5802 else
5803 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
5804
5805 intel_parser.op_string += strlen (new_token.str);
5806 cur_token = new_token;
5807}
5808
64a0c779
DN		 5809/* Put cur_token back into the token stream and make cur_token point to
5810 prev_token. */
5811static void
5812intel_putback_token ()
5813{
5814 intel_parser.op_string -= strlen (cur_token.str);
5815 free (cur_token.str);
5816 cur_token = prev_token;
4a1805b1 5817
64a0c779
DN		 5818 /* Forget prev_token. */
5819 prev_token.code = T_NIL;
5820 prev_token.reg = NULL;
5821 prev_token.str = NULL;
5822}
GDB Binutils - Deliverables
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