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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
43234a1e
L		 272 broadcast_needed,
273 unsupported_masking,
274 mask_not_on_destination,
275 no_default_mask,
276 unsupported_rc_sae,
277 rc_sae_operand_not_last_imm,
278 invalid_register_operand,
a65babc9
L		 279 };
280
252b5132
RH		 281struct _i386_insn
282 {
47926f60 283 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 284 insn_template tm;
252b5132 285
7d5e4556
L		 286 /* SUFFIX holds the instruction size suffix for byte, word, dword
287 or qword, if given. */
252b5132
RH		 288 char suffix;
289
47926f60 290 /* OPERANDS gives the number of given operands. */
252b5132
RH		 291 unsigned int operands;
292
293 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
294 of given register, displacement, memory operands and immediate
47926f60 295 operands. */
252b5132
RH		 296 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
297
298 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 299 use OP[i] for the corresponding operand. */
40fb9820 300 i386_operand_type types[MAX_OPERANDS];
252b5132 301
520dc8e8
AM		 302 /* Displacement expression, immediate expression, or register for each
303 operand. */
304 union i386_op op[MAX_OPERANDS];
252b5132 305
3e73aa7c
JH		 306 /* Flags for operands. */
307 unsigned int flags[MAX_OPERANDS];
308#define Operand_PCrel 1
309
252b5132 310 /* Relocation type for operand */
f86103b7 311 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 312
252b5132
RH		 313 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
314 the base index byte below. */
315 const reg_entry *base_reg;
316 const reg_entry *index_reg;
317 unsigned int log2_scale_factor;
318
319 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 320 explicit segment overrides are given. */
ce8a8b2f 321 const seg_entry *seg[2];
252b5132 322
8325cc63
JB		 323 /* Copied first memory operand string, for re-checking. */
324 char *memop1_string;
325
252b5132
RH		 326 /* PREFIX holds all the given prefix opcodes (usually null).
327 PREFIXES is the number of prefix opcodes. */
328 unsigned int prefixes;
329 unsigned char prefix[MAX_PREFIXES];
330
331 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 332 addressing modes of this insn are encoded. */
252b5132 333 modrm_byte rm;
3e73aa7c 334 rex_byte rex;
43234a1e 335 rex_byte vrex;
252b5132 336 sib_byte sib;
c0f3af97 337 vex_prefix vex;
b6169b20 338
43234a1e
L		 339 /* Masking attributes. */
340 struct Mask_Operation *mask;
341
342 /* Rounding control and SAE attributes. */
343 struct RC_Operation *rounding;
344
345 /* Broadcasting attributes. */
346 struct Broadcast_Operation *broadcast;
347
348 /* Compressed disp8*N attribute. */
349 unsigned int memshift;
350
86fa6981
L		 351 /* Prefer load or store in encoding. */
352 enum
353 {
354 dir_encoding_default = 0,
355 dir_encoding_load,
356 dir_encoding_store
357 } dir_encoding;
891edac4 358
a501d77e
L		 359 /* Prefer 8bit or 32bit displacement in encoding. */
360 enum
361 {
362 disp_encoding_default = 0,
363 disp_encoding_8bit,
364 disp_encoding_32bit
365 } disp_encoding;
f8a5c266 366
6b6b6807
L		 367 /* Prefer the REX byte in encoding. */
368 bfd_boolean rex_encoding;
369
b6f8c7c4
L		 370 /* Disable instruction size optimization. */
371 bfd_boolean no_optimize;
372
86fa6981
L		 373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
d5de92cf
L		 382 /* REP prefix. */
383 const char *rep_prefix;
384
165de32a
L		 385 /* HLE prefix. */
386 const char *hle_prefix;
42164a71 387
7e8b059b
L		 388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
04ef582a
L		 391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
891edac4 394 /* Error message. */
a65babc9 395 enum i386_error error;
252b5132
RH		 396 };
397
398typedef struct _i386_insn i386_insn;
399
43234a1e
L		 400/* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402struct RC_name
403{
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407};
408
409static const struct RC_name RC_NamesTable[] =
410{
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416};
417
252b5132
RH		 418/* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 420const char extra_symbol_chars[] = "*%-([{}"
252b5132 421#ifdef LEX_AT
32137342
NC		 422 "@"
423#endif
424#ifdef LEX_QM
425 "?"
252b5132 426#endif
32137342 427 ;
252b5132 428
29b0f896
AM		 429#if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 431 && !defined (TE_GNU) \
29b0f896 432 && !defined (TE_LINUX) \
8d63c93e 433 && !defined (TE_NACL) \
29b0f896 434 && !defined (TE_FreeBSD) \
5b806d27 435 && !defined (TE_DragonFly) \
29b0f896 436 && !defined (TE_NetBSD)))
252b5132 437/* This array holds the chars that always start a comment. If the
b3b91714
AM		 438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440const char *i386_comment_chars = "#/";
441#define SVR4_COMMENT_CHARS 1
252b5132 442#define PREFIX_SEPARATOR '\\'
252b5132 443
b3b91714
AM		 444#else
445const char *i386_comment_chars = "#";
446#define PREFIX_SEPARATOR '/'
447#endif
448
252b5132
RH		 449/* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 453 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
252b5132 456 '/' isn't otherwise defined. */
b3b91714 457const char line_comment_chars[] = "#/";
252b5132 458
63a0b638 459const char line_separator_chars[] = ";";
252b5132 460
ce8a8b2f
AM		 461/* Chars that can be used to separate mant from exp in floating point
462 nums. */
252b5132
RH		 463const char EXP_CHARS[] = "eE";
464
ce8a8b2f
AM		 465/* Chars that mean this number is a floating point constant
466 As in 0f12.456
467 or 0d1.2345e12. */
252b5132
RH		 468const char FLT_CHARS[] = "fFdDxX";
469
ce8a8b2f 470/* Tables for lexical analysis. */
252b5132
RH		 471static char mnemonic_chars[256];
472static char register_chars[256];
473static char operand_chars[256];
474static char identifier_chars[256];
475static char digit_chars[256];
476
ce8a8b2f 477/* Lexical macros. */
252b5132
RH		 478#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479#define is_operand_char(x) (operand_chars[(unsigned char) x])
480#define is_register_char(x) (register_chars[(unsigned char) x])
481#define is_space_char(x) ((x) == ' ')
482#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483#define is_digit_char(x) (digit_chars[(unsigned char) x])
484
0234cb7c 485/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 486static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
487
488/* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
47926f60 491 assembler instruction). */
252b5132 492static char save_stack[32];
ce8a8b2f 493static char *save_stack_p;
252b5132
RH		 494#define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496#define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
498
47926f60 499/* The instruction we're assembling. */
252b5132
RH		 500static i386_insn i;
501
502/* Possible templates for current insn. */
503static const templates *current_templates;
504
31b2323c
L		 505/* Per instruction expressionS buffers: max displacements & immediates. */
506static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 508
47926f60 509/* Current operand we are working on. */
ee86248c 510static int this_operand = -1;
252b5132 511
3e73aa7c
JH		 512/* We support four different modes. FLAG_CODE variable is used to distinguish
513 these. */
514
515enum flag_code {
516 CODE_32BIT,
517 CODE_16BIT,
518 CODE_64BIT };
519
520static enum flag_code flag_code;
4fa24527 521static unsigned int object_64bit;
862be3fb 522static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 523static int use_rela_relocations = 0;
524
7af8ed2d
NC		 525#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
528
351f65ca
L		 529/* The ELF ABI to use. */
530enum x86_elf_abi
531{
532 I386_ABI,
7f56bc95
L		 533 X86_64_ABI,
534 X86_64_X32_ABI
351f65ca
L		 535};
536
537static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 538#endif
351f65ca 539
167ad85b
TG		 540#if defined (TE_PE) || defined (TE_PEP)
541/* Use big object file format. */
542static int use_big_obj = 0;
543#endif
544
8dcea932
L		 545#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546/* 1 if generating code for a shared library. */
547static int shared = 0;
548#endif
549
47926f60
KH		 550/* 1 for intel syntax,
551 0 if att syntax. */
552static int intel_syntax = 0;
252b5132 553
e89c5eaa
L		 554/* 1 for Intel64 ISA,
555 0 if AMD64 ISA. */
556static int intel64;
557
1efbbeb4
L		 558/* 1 for intel mnemonic,
559 0 if att mnemonic. */
560static int intel_mnemonic = !SYSV386_COMPAT;
561
a60de03c
JB		 562/* 1 if pseudo registers are permitted. */
563static int allow_pseudo_reg = 0;
564
47926f60
KH		 565/* 1 if register prefix % not required. */
566static int allow_naked_reg = 0;
252b5132 567
33eaf5de 568/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 569 instructions supporting it, even if this prefix wasn't specified
570 explicitly. */
571static int add_bnd_prefix = 0;
572
ba104c83 573/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 574static int allow_index_reg = 0;
575
d022bddd
IT		 576/* 1 if the assembler should ignore LOCK prefix, even if it was
577 specified explicitly. */
578static int omit_lock_prefix = 0;
579
e4e00185
AS		 580/* 1 if the assembler should encode lfence, mfence, and sfence as
581 "lock addl $0, (%{re}sp)". */
582static int avoid_fence = 0;
583
0cb4071e
L		 584/* 1 if the assembler should generate relax relocations. */
585
586static int generate_relax_relocations
587 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
588
7bab8ab5 589static enum check_kind
daf50ae7 590 {
7bab8ab5
JB		 591 check_none = 0,
592 check_warning,
593 check_error
daf50ae7 594 }
7bab8ab5 595sse_check, operand_check = check_warning;
daf50ae7 596
b6f8c7c4
L		 597/* Optimization:
598 1. Clear the REX_W bit with register operand if possible.
599 2. Above plus use 128bit vector instruction to clear the full vector
600 register.
601 */
602static int optimize = 0;
603
604/* Optimization:
605 1. Clear the REX_W bit with register operand if possible.
606 2. Above plus use 128bit vector instruction to clear the full vector
607 register.
608 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
609 "testb $imm7,%r8".
610 */
611static int optimize_for_space = 0;
612
2ca3ace5
L		 613/* Register prefix used for error message. */
614static const char *register_prefix = "%";
615
47926f60
KH		 616/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
617 leave, push, and pop instructions so that gcc has the same stack
618 frame as in 32 bit mode. */
619static char stackop_size = '\0';
eecb386c 620
12b55ccc
L		 621/* Non-zero to optimize code alignment. */
622int optimize_align_code = 1;
623
47926f60
KH		 624/* Non-zero to quieten some warnings. */
625static int quiet_warnings = 0;
a38cf1db 626
47926f60
KH		 627/* CPU name. */
628static const char *cpu_arch_name = NULL;
6305a203 629static char *cpu_sub_arch_name = NULL;
a38cf1db 630
47926f60 631/* CPU feature flags. */
40fb9820
L		 632static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
633
ccc9c027
L		 634/* If we have selected a cpu we are generating instructions for. */
635static int cpu_arch_tune_set = 0;
636
9103f4f4 637/* Cpu we are generating instructions for. */
fbf3f584 638enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 639
640/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 641static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 642
ccc9c027 643/* CPU instruction set architecture used. */
fbf3f584 644enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 645
9103f4f4 646/* CPU feature flags of instruction set architecture used. */
fbf3f584 647i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 648
fddf5b5b
AM		 649/* If set, conditional jumps are not automatically promoted to handle
650 larger than a byte offset. */
651static unsigned int no_cond_jump_promotion = 0;
652
c0f3af97
L		 653/* Encode SSE instructions with VEX prefix. */
654static unsigned int sse2avx;
655
539f890d
L		 656/* Encode scalar AVX instructions with specific vector length. */
657static enum
658 {
659 vex128 = 0,
660 vex256
661 } avxscalar;
662
43234a1e
L		 663/* Encode scalar EVEX LIG instructions with specific vector length. */
664static enum
665 {
666 evexl128 = 0,
667 evexl256,
668 evexl512
669 } evexlig;
670
671/* Encode EVEX WIG instructions with specific evex.w. */
672static enum
673 {
674 evexw0 = 0,
675 evexw1
676 } evexwig;
677
d3d3c6db
IT		 678/* Value to encode in EVEX RC bits, for SAE-only instructions. */
679static enum rc_type evexrcig = rne;
680
29b0f896 681/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 682static symbolS *GOT_symbol;
29b0f896 683
a4447b93
RH		 684/* The dwarf2 return column, adjusted for 32 or 64 bit. */
685unsigned int x86_dwarf2_return_column;
686
687/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
688int x86_cie_data_alignment;
689
252b5132 690/* Interface to relax_segment.
fddf5b5b
AM		 691 There are 3 major relax states for 386 jump insns because the
692 different types of jumps add different sizes to frags when we're
693 figuring out what sort of jump to choose to reach a given label. */
252b5132 694
47926f60 695/* Types. */
93c2a809
AM		 696#define UNCOND_JUMP 0
697#define COND_JUMP 1
698#define COND_JUMP86 2
fddf5b5b 699
47926f60 700/* Sizes. */
252b5132
RH		 701#define CODE16 1
702#define SMALL 0
29b0f896 703#define SMALL16 (SMALL | CODE16)
252b5132 704#define BIG 2
29b0f896 705#define BIG16 (BIG | CODE16)
252b5132
RH		 706
707#ifndef INLINE
708#ifdef __GNUC__
709#define INLINE __inline__
710#else
711#define INLINE
712#endif
713#endif
714
fddf5b5b
AM		 715#define ENCODE_RELAX_STATE(type, size) \
716 ((relax_substateT) (((type) << 2) | (size)))
717#define TYPE_FROM_RELAX_STATE(s) \
718 ((s) >> 2)
719#define DISP_SIZE_FROM_RELAX_STATE(s) \
720 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 721
722/* This table is used by relax_frag to promote short jumps to long
723 ones where necessary. SMALL (short) jumps may be promoted to BIG
724 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
725 don't allow a short jump in a 32 bit code segment to be promoted to
726 a 16 bit offset jump because it's slower (requires data size
727 prefix), and doesn't work, unless the destination is in the bottom
728 64k of the code segment (The top 16 bits of eip are zeroed). */
729
730const relax_typeS md_relax_table[] =
731{
24eab124
AM		 732 /* The fields are:
733 1) most positive reach of this state,
734 2) most negative reach of this state,
93c2a809 735 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 736 4) which index into the table to try if we can't fit into this one. */
252b5132 737
fddf5b5b 738 /* UNCOND_JUMP states. */
93c2a809
AM		 739 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
741 /* dword jmp adds 4 bytes to frag:
742 0 extra opcode bytes, 4 displacement bytes. */
252b5132 743 {0, 0, 4, 0},
93c2a809
AM		 744 /* word jmp adds 2 byte2 to frag:
745 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 746 {0, 0, 2, 0},
747
93c2a809
AM		 748 /* COND_JUMP states. */
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
751 /* dword conditionals adds 5 bytes to frag:
752 1 extra opcode byte, 4 displacement bytes. */
753 {0, 0, 5, 0},
fddf5b5b 754 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 755 1 extra opcode byte, 2 displacement bytes. */
756 {0, 0, 3, 0},
757
758 /* COND_JUMP86 states. */
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
761 /* dword conditionals adds 5 bytes to frag:
762 1 extra opcode byte, 4 displacement bytes. */
763 {0, 0, 5, 0},
764 /* word conditionals add 4 bytes to frag:
765 1 displacement byte and a 3 byte long branch insn. */
766 {0, 0, 4, 0}
252b5132
RH		 767};
768
9103f4f4
L		 769static const arch_entry cpu_arch[] =
770{
89507696
JB		 771 /* Do not replace the first two entries - i386_target_format()
772 relies on them being there in this order. */
8a2c8fef 773 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 774 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 776 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 778 CPU_NONE_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 780 CPU_I186_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 782 CPU_I286_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 784 CPU_I386_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 786 CPU_I486_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 788 CPU_I586_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 790 CPU_I686_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 792 CPU_I586_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 794 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 796 CPU_P2_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 798 CPU_P3_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 800 CPU_P4_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 802 CPU_CORE_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 804 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 806 CPU_CORE_FLAGS, 1 },
8a2c8fef 807 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 808 CPU_CORE_FLAGS, 0 },
8a2c8fef 809 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 810 CPU_CORE2_FLAGS, 1 },
8a2c8fef 811 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 812 CPU_CORE2_FLAGS, 0 },
8a2c8fef 813 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 814 CPU_COREI7_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 816 CPU_L1OM_FLAGS, 0 },
7a9068fe 817 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 818 CPU_K1OM_FLAGS, 0 },
81486035 819 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 820 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 821 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 822 CPU_K6_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 824 CPU_K6_2_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 826 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 828 CPU_K8_FLAGS, 1 },
8a2c8fef 829 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 830 CPU_K8_FLAGS, 0 },
8a2c8fef 831 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 832 CPU_K8_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 834 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 835 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 836 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 837 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 838 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 839 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 840 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 841 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 842 CPU_BDVER4_FLAGS, 0 },
029f3522 843 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 844 CPU_ZNVER1_FLAGS, 0 },
a9660a6f
AP		 845 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
846 CPU_ZNVER2_FLAGS, 0 },
7b458c12 847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 848 CPU_BTVER1_FLAGS, 0 },
7b458c12 849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 850 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_8087_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_287_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_387_FLAGS, 0 },
1848e567
L		 857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 CPU_687_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_MMX_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_SSE_FLAGS, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_SSE2_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_SSE3_FLAGS, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX_FLAGS, 0 },
6c30d220 877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX2_FLAGS, 0 },
43234a1e 879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AVX512F_FLAGS, 0 },
43234a1e 881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_AVX512CD_FLAGS, 0 },
43234a1e 883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_AVX512ER_FLAGS, 0 },
43234a1e 885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_VMX_FLAGS, 0 },
8729a6f6 895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_SMX_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_AES_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_F16C_FLAGS, 0 },
6c30d220 919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_BMI2_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_FMA_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_FMA4_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_XOP_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_LWP_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_MOVBE_FLAGS, 0 },
60aa667e 931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_CX16_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_EPT_FLAGS, 0 },
6c30d220 935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_LZCNT_FLAGS, 0 },
42164a71 937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_HLE_FLAGS, 0 },
42164a71 939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_RTM_FLAGS, 0 },
6c30d220 941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_CLFLUSH_FLAGS, 0 },
22109423 945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_NOP_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SVME_FLAGS, 1 },
8a2c8fef 959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_SVME_FLAGS, 0 },
8a2c8fef 961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_ABM_FLAGS, 0 },
87973e9f 965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_BMI_FLAGS, 0 },
2a2a0f38 967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_TBM_FLAGS, 0 },
e2e1fcde 969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_ADX_FLAGS, 0 },
e2e1fcde 971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_PRFCHW_FLAGS, 0 },
5c111e37 975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_SMAP_FLAGS, 0 },
7e8b059b 977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_MPX_FLAGS, 0 },
a0046408 979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 980 CPU_SHA_FLAGS, 0 },
963f3586 981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 982 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 984 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 986 CPU_SE1_FLAGS, 0 },
c5e7287a 987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1006 CPU_CLZERO_FLAGS, 0 },
9916071f 1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1008 CPU_MWAITX_FLAGS, 0 },
8eab4136 1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1010 CPU_OSPKE_FLAGS, 0 },
8bc52696 1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1012 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 CPU_IBT_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1029 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1030 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1031 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1032 CPU_CLDEMOTE_FLAGS, 0 },
c0a30a9f
L		 1033 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1034 CPU_MOVDIRI_FLAGS, 0 },
1035 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1036 CPU_MOVDIR64B_FLAGS, 0 },
293f5f65
L		 1037};
1038
1039static const noarch_entry cpu_noarch[] =
1040{
1041 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1042 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1043 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1044 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1045 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1046 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1047 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1048 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1053 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1054 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1055 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1064 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1065 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1066 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1067 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1068 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1069 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1070 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1071 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
c0a30a9f
L		 1072 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1073 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
e413e4e9
AM		 1074};
1075
704209c0 1076#ifdef I386COFF
a6c24e68
NC		 1077/* Like s_lcomm_internal in gas/read.c but the alignment string
1078 is allowed to be optional. */
1079
1080static symbolS *
1081pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1082{
1083 addressT align = 0;
1084
1085 SKIP_WHITESPACE ();
1086
7ab9ffdd 1087 if (needs_align
a6c24e68
NC		 1088 && *input_line_pointer == ',')
1089 {
1090 align = parse_align (needs_align - 1);
7ab9ffdd 1091
a6c24e68
NC		 1092 if (align == (addressT) -1)
1093 return NULL;
1094 }
1095 else
1096 {
1097 if (size >= 8)
1098 align = 3;
1099 else if (size >= 4)
1100 align = 2;
1101 else if (size >= 2)
1102 align = 1;
1103 else
1104 align = 0;
1105 }
1106
1107 bss_alloc (symbolP, size, align);
1108 return symbolP;
1109}
1110
704209c0 1111static void
a6c24e68
NC		 1112pe_lcomm (int needs_align)
1113{
1114 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1115}
704209c0 1116#endif
a6c24e68 1117
29b0f896
AM		 1118const pseudo_typeS md_pseudo_table[] =
1119{
1120#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1121 {"align", s_align_bytes, 0},
1122#else
1123 {"align", s_align_ptwo, 0},
1124#endif
1125 {"arch", set_cpu_arch, 0},
1126#ifndef I386COFF
1127 {"bss", s_bss, 0},
a6c24e68
NC		 1128#else
1129 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1130#endif
1131 {"ffloat", float_cons, 'f'},
1132 {"dfloat", float_cons, 'd'},
1133 {"tfloat", float_cons, 'x'},
1134 {"value", cons, 2},
d182319b 1135 {"slong", signed_cons, 4},
29b0f896
AM		 1136 {"noopt", s_ignore, 0},
1137 {"optim", s_ignore, 0},
1138 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1139 {"code16", set_code_flag, CODE_16BIT},
1140 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1141#ifdef BFD64
29b0f896 1142 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1143#endif
29b0f896
AM		 1144 {"intel_syntax", set_intel_syntax, 1},
1145 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1146 {"intel_mnemonic", set_intel_mnemonic, 1},
1147 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1148 {"allow_index_reg", set_allow_index_reg, 1},
1149 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1150 {"sse_check", set_check, 0},
1151 {"operand_check", set_check, 1},
3b22753a
L		 1152#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1153 {"largecomm", handle_large_common, 0},
07a53e5c 1154#else
68d20676 1155 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1156 {"loc", dwarf2_directive_loc, 0},
1157 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1158#endif
6482c264
NC		 1159#ifdef TE_PE
1160 {"secrel32", pe_directive_secrel, 0},
1161#endif
29b0f896
AM		 1162 {0, 0, 0}
1163};
1164
1165/* For interface with expression (). */
1166extern char *input_line_pointer;
1167
1168/* Hash table for instruction mnemonic lookup. */
1169static struct hash_control *op_hash;
1170
1171/* Hash table for register lookup. */
1172static struct hash_control *reg_hash;
1173\f
ce8a8b2f
AM		 1174 /* Various efficient no-op patterns for aligning code labels.
1175 Note: Don't try to assemble the instructions in the comments.
1176 0L and 0w are not legal. */
62a02d25
L		 1177static const unsigned char f32_1[] =
1178 {0x90}; /* nop */
1179static const unsigned char f32_2[] =
1180 {0x66,0x90}; /* xchg %ax,%ax */
1181static const unsigned char f32_3[] =
1182 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1183static const unsigned char f32_4[] =
1184 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1185static const unsigned char f32_6[] =
1186 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1187static const unsigned char f32_7[] =
1188 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1189static const unsigned char f16_3[] =
3ae729d5 1190 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1191static const unsigned char f16_4[] =
3ae729d5
L		 1192 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1193static const unsigned char jump_disp8[] =
1194 {0xeb}; /* jmp disp8 */
1195static const unsigned char jump32_disp32[] =
1196 {0xe9}; /* jmp disp32 */
1197static const unsigned char jump16_disp32[] =
1198 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1199/* 32-bit NOPs patterns. */
1200static const unsigned char *const f32_patt[] = {
3ae729d5 1201 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1202};
1203/* 16-bit NOPs patterns. */
1204static const unsigned char *const f16_patt[] = {
3ae729d5 1205 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1206};
1207/* nopl (%[re]ax) */
1208static const unsigned char alt_3[] =
1209 {0x0f,0x1f,0x00};
1210/* nopl 0(%[re]ax) */
1211static const unsigned char alt_4[] =
1212 {0x0f,0x1f,0x40,0x00};
1213/* nopl 0(%[re]ax,%[re]ax,1) */
1214static const unsigned char alt_5[] =
1215 {0x0f,0x1f,0x44,0x00,0x00};
1216/* nopw 0(%[re]ax,%[re]ax,1) */
1217static const unsigned char alt_6[] =
1218 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1219/* nopl 0L(%[re]ax) */
1220static const unsigned char alt_7[] =
1221 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1222/* nopl 0L(%[re]ax,%[re]ax,1) */
1223static const unsigned char alt_8[] =
1224 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225/* nopw 0L(%[re]ax,%[re]ax,1) */
1226static const unsigned char alt_9[] =
1227 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1229static const unsigned char alt_10[] =
1230 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1231/* data16 nopw %cs:0L(%eax,%eax,1) */
1232static const unsigned char alt_11[] =
1233 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1234/* 32-bit and 64-bit NOPs patterns. */
1235static const unsigned char *const alt_patt[] = {
1236 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1237 alt_9, alt_10, alt_11
62a02d25
L		 1238};
1239
1240/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1241 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1242
1243static void
1244i386_output_nops (char *where, const unsigned char *const *patt,
1245 int count, int max_single_nop_size)
1246
1247{
3ae729d5
L		 1248 /* Place the longer NOP first. */
1249 int last;
1250 int offset;
1251 const unsigned char *nops = patt[max_single_nop_size - 1];
1252
1253 /* Use the smaller one if the requsted one isn't available. */
1254 if (nops == NULL)
62a02d25 1255 {
3ae729d5
L		 1256 max_single_nop_size--;
1257 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1258 }
1259
3ae729d5
L		 1260 last = count % max_single_nop_size;
1261
1262 count -= last;
1263 for (offset = 0; offset < count; offset += max_single_nop_size)
1264 memcpy (where + offset, nops, max_single_nop_size);
1265
1266 if (last)
1267 {
1268 nops = patt[last - 1];
1269 if (nops == NULL)
1270 {
1271 /* Use the smaller one plus one-byte NOP if the needed one
1272 isn't available. */
1273 last--;
1274 nops = patt[last - 1];
1275 memcpy (where + offset, nops, last);
1276 where[offset + last] = *patt[0];
1277 }
1278 else
1279 memcpy (where + offset, nops, last);
1280 }
62a02d25
L		 1281}
1282
3ae729d5
L		 1283static INLINE int
1284fits_in_imm7 (offsetT num)
1285{
1286 return (num & 0x7f) == num;
1287}
1288
1289static INLINE int
1290fits_in_imm31 (offsetT num)
1291{
1292 return (num & 0x7fffffff) == num;
1293}
62a02d25
L		 1294
1295/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1296 single NOP instruction LIMIT. */
1297
1298void
3ae729d5 1299i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1300{
3ae729d5 1301 const unsigned char *const *patt = NULL;
62a02d25 1302 int max_single_nop_size;
3ae729d5
L		 1303 /* Maximum number of NOPs before switching to jump over NOPs. */
1304 int max_number_of_nops;
62a02d25 1305
3ae729d5 1306 switch (fragP->fr_type)
62a02d25 1307 {
3ae729d5
L		 1308 case rs_fill_nop:
1309 case rs_align_code:
1310 break;
1311 default:
62a02d25
L		 1312 return;
1313 }
1314
ccc9c027
L		 1315 /* We need to decide which NOP sequence to use for 32bit and
1316 64bit. When -mtune= is used:
4eed87de 1317
76bc74dc
L		 1318 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1319 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1320 2. For the rest, alt_patt will be used.
1321
1322 When -mtune= isn't used, alt_patt will be used if
22109423 1323 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1324 be used.
ccc9c027
L		 1325
1326 When -march= or .arch is used, we can't use anything beyond
1327 cpu_arch_isa_flags. */
1328
1329 if (flag_code == CODE_16BIT)
1330 {
3ae729d5
L		 1331 patt = f16_patt;
1332 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1333 /* Limit number of NOPs to 2 in 16-bit mode. */
1334 max_number_of_nops = 2;
252b5132 1335 }
33fef721 1336 else
ccc9c027 1337 {
fbf3f584 1338 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1339 {
1340 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1341 switch (cpu_arch_tune)
1342 {
1343 case PROCESSOR_UNKNOWN:
1344 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1345 optimize with nops. */
1346 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1347 patt = alt_patt;
ccc9c027
L		 1348 else
1349 patt = f32_patt;
1350 break;
ccc9c027
L		 1351 case PROCESSOR_PENTIUM4:
1352 case PROCESSOR_NOCONA:
ef05d495 1353 case PROCESSOR_CORE:
76bc74dc 1354 case PROCESSOR_CORE2:
bd5295b2 1355 case PROCESSOR_COREI7:
3632d14b 1356 case PROCESSOR_L1OM:
7a9068fe 1357 case PROCESSOR_K1OM:
76bc74dc 1358 case PROCESSOR_GENERIC64:
ccc9c027
L		 1359 case PROCESSOR_K6:
1360 case PROCESSOR_ATHLON:
1361 case PROCESSOR_K8:
4eed87de 1362 case PROCESSOR_AMDFAM10:
8aedb9fe 1363 case PROCESSOR_BD:
029f3522 1364 case PROCESSOR_ZNVER:
7b458c12 1365 case PROCESSOR_BT:
80b8656c 1366 patt = alt_patt;
ccc9c027 1367 break;
76bc74dc 1368 case PROCESSOR_I386:
ccc9c027
L		 1369 case PROCESSOR_I486:
1370 case PROCESSOR_PENTIUM:
2dde1948 1371 case PROCESSOR_PENTIUMPRO:
81486035 1372 case PROCESSOR_IAMCU:
ccc9c027
L		 1373 case PROCESSOR_GENERIC32:
1374 patt = f32_patt;
1375 break;
4eed87de 1376 }
ccc9c027
L		 1377 }
1378 else
1379 {
fbf3f584 1380 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1381 {
1382 case PROCESSOR_UNKNOWN:
e6a14101 1383 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1384 PROCESSOR_UNKNOWN. */
1385 abort ();
1386 break;
1387
76bc74dc 1388 case PROCESSOR_I386:
ccc9c027
L		 1389 case PROCESSOR_I486:
1390 case PROCESSOR_PENTIUM:
81486035 1391 case PROCESSOR_IAMCU:
ccc9c027
L		 1392 case PROCESSOR_K6:
1393 case PROCESSOR_ATHLON:
1394 case PROCESSOR_K8:
4eed87de 1395 case PROCESSOR_AMDFAM10:
8aedb9fe 1396 case PROCESSOR_BD:
029f3522 1397 case PROCESSOR_ZNVER:
7b458c12 1398 case PROCESSOR_BT:
ccc9c027
L		 1399 case PROCESSOR_GENERIC32:
1400 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1401 with nops. */
1402 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1403 patt = alt_patt;
ccc9c027
L		 1404 else
1405 patt = f32_patt;
1406 break;
76bc74dc
L		 1407 case PROCESSOR_PENTIUMPRO:
1408 case PROCESSOR_PENTIUM4:
1409 case PROCESSOR_NOCONA:
1410 case PROCESSOR_CORE:
ef05d495 1411 case PROCESSOR_CORE2:
bd5295b2 1412 case PROCESSOR_COREI7:
3632d14b 1413 case PROCESSOR_L1OM:
7a9068fe 1414 case PROCESSOR_K1OM:
22109423 1415 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1416 patt = alt_patt;
ccc9c027
L		 1417 else
1418 patt = f32_patt;
1419 break;
1420 case PROCESSOR_GENERIC64:
80b8656c 1421 patt = alt_patt;
ccc9c027 1422 break;
4eed87de 1423 }
ccc9c027
L		 1424 }
1425
76bc74dc
L		 1426 if (patt == f32_patt)
1427 {
3ae729d5
L		 1428 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1429 /* Limit number of NOPs to 2 for older processors. */
1430 max_number_of_nops = 2;
76bc74dc
L		 1431 }
1432 else
1433 {
3ae729d5
L		 1434 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1435 /* Limit number of NOPs to 7 for newer processors. */
1436 max_number_of_nops = 7;
1437 }
1438 }
1439
1440 if (limit == 0)
1441 limit = max_single_nop_size;
1442
1443 if (fragP->fr_type == rs_fill_nop)
1444 {
1445 /* Output NOPs for .nop directive. */
1446 if (limit > max_single_nop_size)
1447 {
1448 as_bad_where (fragP->fr_file, fragP->fr_line,
1449 _("invalid single nop size: %d "
1450 "(expect within [0, %d])"),
1451 limit, max_single_nop_size);
1452 return;
1453 }
1454 }
1455 else
1456 fragP->fr_var = count;
1457
1458 if ((count / max_single_nop_size) > max_number_of_nops)
1459 {
1460 /* Generate jump over NOPs. */
1461 offsetT disp = count - 2;
1462 if (fits_in_imm7 (disp))
1463 {
1464 /* Use "jmp disp8" if possible. */
1465 count = disp;
1466 where[0] = jump_disp8[0];
1467 where[1] = count;
1468 where += 2;
1469 }
1470 else
1471 {
1472 unsigned int size_of_jump;
1473
1474 if (flag_code == CODE_16BIT)
1475 {
1476 where[0] = jump16_disp32[0];
1477 where[1] = jump16_disp32[1];
1478 size_of_jump = 2;
1479 }
1480 else
1481 {
1482 where[0] = jump32_disp32[0];
1483 size_of_jump = 1;
1484 }
1485
1486 count -= size_of_jump + 4;
1487 if (!fits_in_imm31 (count))
1488 {
1489 as_bad_where (fragP->fr_file, fragP->fr_line,
1490 _("jump over nop padding out of range"));
1491 return;
1492 }
1493
1494 md_number_to_chars (where + size_of_jump, count, 4);
1495 where += size_of_jump + 4;
76bc74dc 1496 }
ccc9c027 1497 }
3ae729d5
L		 1498
1499 /* Generate multiple NOPs. */
1500 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1501}
1502
c6fb90c8 1503static INLINE int
0dfbf9d7 1504operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1505{
0dfbf9d7 1506 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1507 {
1508 case 3:
0dfbf9d7 1509 if (x->array[2])
c6fb90c8 1510 return 0;
1a0670f3 1511 /* Fall through. */
c6fb90c8 1512 case 2:
0dfbf9d7 1513 if (x->array[1])
c6fb90c8 1514 return 0;
1a0670f3 1515 /* Fall through. */
c6fb90c8 1516 case 1:
0dfbf9d7 1517 return !x->array[0];
c6fb90c8
L		 1518 default:
1519 abort ();
1520 }
40fb9820
L		 1521}
1522
c6fb90c8 1523static INLINE void
0dfbf9d7 1524operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1525{
0dfbf9d7 1526 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1527 {
1528 case 3:
0dfbf9d7 1529 x->array[2] = v;
1a0670f3 1530 /* Fall through. */
c6fb90c8 1531 case 2:
0dfbf9d7 1532 x->array[1] = v;
1a0670f3 1533 /* Fall through. */
c6fb90c8 1534 case 1:
0dfbf9d7 1535 x->array[0] = v;
1a0670f3 1536 /* Fall through. */
c6fb90c8
L		 1537 break;
1538 default:
1539 abort ();
1540 }
1541}
40fb9820 1542
c6fb90c8 1543static INLINE int
0dfbf9d7
L		 1544operand_type_equal (const union i386_operand_type *x,
1545 const union i386_operand_type *y)
c6fb90c8 1546{
0dfbf9d7 1547 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1548 {
1549 case 3:
0dfbf9d7 1550 if (x->array[2] != y->array[2])
c6fb90c8 1551 return 0;
1a0670f3 1552 /* Fall through. */
c6fb90c8 1553 case 2:
0dfbf9d7 1554 if (x->array[1] != y->array[1])
c6fb90c8 1555 return 0;
1a0670f3 1556 /* Fall through. */
c6fb90c8 1557 case 1:
0dfbf9d7 1558 return x->array[0] == y->array[0];
c6fb90c8
L		 1559 break;
1560 default:
1561 abort ();
1562 }
1563}
40fb9820 1564
0dfbf9d7
L		 1565static INLINE int
1566cpu_flags_all_zero (const union i386_cpu_flags *x)
1567{
1568 switch (ARRAY_SIZE(x->array))
1569 {
53467f57
IT		 1570 case 4:
1571 if (x->array[3])
1572 return 0;
1573 /* Fall through. */
0dfbf9d7
L		 1574 case 3:
1575 if (x->array[2])
1576 return 0;
1a0670f3 1577 /* Fall through. */
0dfbf9d7
L		 1578 case 2:
1579 if (x->array[1])
1580 return 0;
1a0670f3 1581 /* Fall through. */
0dfbf9d7
L		 1582 case 1:
1583 return !x->array[0];
1584 default:
1585 abort ();
1586 }
1587}
1588
0dfbf9d7
L		 1589static INLINE int
1590cpu_flags_equal (const union i386_cpu_flags *x,
1591 const union i386_cpu_flags *y)
1592{
1593 switch (ARRAY_SIZE(x->array))
1594 {
53467f57
IT		 1595 case 4:
1596 if (x->array[3] != y->array[3])
1597 return 0;
1598 /* Fall through. */
0dfbf9d7
L		 1599 case 3:
1600 if (x->array[2] != y->array[2])
1601 return 0;
1a0670f3 1602 /* Fall through. */
0dfbf9d7
L		 1603 case 2:
1604 if (x->array[1] != y->array[1])
1605 return 0;
1a0670f3 1606 /* Fall through. */
0dfbf9d7
L		 1607 case 1:
1608 return x->array[0] == y->array[0];
1609 break;
1610 default:
1611 abort ();
1612 }
1613}
c6fb90c8
L		 1614
1615static INLINE int
1616cpu_flags_check_cpu64 (i386_cpu_flags f)
1617{
1618 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1619 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1620}
1621
c6fb90c8
L		 1622static INLINE i386_cpu_flags
1623cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1624{
c6fb90c8
L		 1625 switch (ARRAY_SIZE (x.array))
1626 {
53467f57
IT		 1627 case 4:
1628 x.array [3] &= y.array [3];
1629 /* Fall through. */
c6fb90c8
L		 1630 case 3:
1631 x.array [2] &= y.array [2];
1a0670f3 1632 /* Fall through. */
c6fb90c8
L		 1633 case 2:
1634 x.array [1] &= y.array [1];
1a0670f3 1635 /* Fall through. */
c6fb90c8
L		 1636 case 1:
1637 x.array [0] &= y.array [0];
1638 break;
1639 default:
1640 abort ();
1641 }
1642 return x;
1643}
40fb9820 1644
c6fb90c8
L		 1645static INLINE i386_cpu_flags
1646cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1647{
c6fb90c8 1648 switch (ARRAY_SIZE (x.array))
40fb9820 1649 {
53467f57
IT		 1650 case 4:
1651 x.array [3] |= y.array [3];
1652 /* Fall through. */
c6fb90c8
L		 1653 case 3:
1654 x.array [2] |= y.array [2];
1a0670f3 1655 /* Fall through. */
c6fb90c8
L		 1656 case 2:
1657 x.array [1] |= y.array [1];
1a0670f3 1658 /* Fall through. */
c6fb90c8
L		 1659 case 1:
1660 x.array [0] |= y.array [0];
40fb9820
L		 1661 break;
1662 default:
1663 abort ();
1664 }
40fb9820
L		 1665 return x;
1666}
1667
309d3373
JB		 1668static INLINE i386_cpu_flags
1669cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1670{
1671 switch (ARRAY_SIZE (x.array))
1672 {
53467f57
IT		 1673 case 4:
1674 x.array [3] &= ~y.array [3];
1675 /* Fall through. */
309d3373
JB		 1676 case 3:
1677 x.array [2] &= ~y.array [2];
1a0670f3 1678 /* Fall through. */
309d3373
JB		 1679 case 2:
1680 x.array [1] &= ~y.array [1];
1a0670f3 1681 /* Fall through. */
309d3373
JB		 1682 case 1:
1683 x.array [0] &= ~y.array [0];
1684 break;
1685 default:
1686 abort ();
1687 }
1688 return x;
1689}
1690
c0f3af97
L		 1691#define CPU_FLAGS_ARCH_MATCH 0x1
1692#define CPU_FLAGS_64BIT_MATCH 0x2
1693
c0f3af97 1694#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1695 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1696
1697/* Return CPU flags match bits. */
3629bb00 1698
40fb9820 1699static int
d3ce72d0 1700cpu_flags_match (const insn_template *t)
40fb9820 1701{
c0f3af97
L		 1702 i386_cpu_flags x = t->cpu_flags;
1703 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1704
1705 x.bitfield.cpu64 = 0;
1706 x.bitfield.cpuno64 = 0;
1707
0dfbf9d7 1708 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1709 {
1710 /* This instruction is available on all archs. */
db12e14e 1711 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1712 }
3629bb00
L		 1713 else
1714 {
c0f3af97 1715 /* This instruction is available only on some archs. */
3629bb00
L		 1716 i386_cpu_flags cpu = cpu_arch_flags;
1717
ab592e75
JB		 1718 /* AVX512VL is no standalone feature - match it and then strip it. */
1719 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1720 return match;
1721 x.bitfield.cpuavx512vl = 0;
1722
3629bb00 1723 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1724 if (!cpu_flags_all_zero (&cpu))
1725 {
a5ff0eb2
L		 1726 if (x.bitfield.cpuavx)
1727 {
929f69fa 1728 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1729 if (cpu.bitfield.cpuavx
1730 && (!t->opcode_modifier.sse2avx || sse2avx)
1731 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1732 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1733 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1734 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1735 }
929f69fa
JB		 1736 else if (x.bitfield.cpuavx512f)
1737 {
1738 /* We need to check a few extra flags with AVX512F. */
1739 if (cpu.bitfield.cpuavx512f
1740 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1741 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1742 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1743 match |= CPU_FLAGS_ARCH_MATCH;
1744 }
a5ff0eb2 1745 else
db12e14e 1746 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1747 }
3629bb00 1748 }
c0f3af97 1749 return match;
40fb9820
L		 1750}
1751
c6fb90c8
L		 1752static INLINE i386_operand_type
1753operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1754{
c6fb90c8
L		 1755 switch (ARRAY_SIZE (x.array))
1756 {
1757 case 3:
1758 x.array [2] &= y.array [2];
1a0670f3 1759 /* Fall through. */
c6fb90c8
L		 1760 case 2:
1761 x.array [1] &= y.array [1];
1a0670f3 1762 /* Fall through. */
c6fb90c8
L		 1763 case 1:
1764 x.array [0] &= y.array [0];
1765 break;
1766 default:
1767 abort ();
1768 }
1769 return x;
40fb9820
L		 1770}
1771
73053c1f
JB		 1772static INLINE i386_operand_type
1773operand_type_and_not (i386_operand_type x, i386_operand_type y)
1774{
1775 switch (ARRAY_SIZE (x.array))
1776 {
1777 case 3:
1778 x.array [2] &= ~y.array [2];
1779 /* Fall through. */
1780 case 2:
1781 x.array [1] &= ~y.array [1];
1782 /* Fall through. */
1783 case 1:
1784 x.array [0] &= ~y.array [0];
1785 break;
1786 default:
1787 abort ();
1788 }
1789 return x;
1790}
1791
c6fb90c8
L		 1792static INLINE i386_operand_type
1793operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1794{
c6fb90c8 1795 switch (ARRAY_SIZE (x.array))
40fb9820 1796 {
c6fb90c8
L		 1797 case 3:
1798 x.array [2] |= y.array [2];
1a0670f3 1799 /* Fall through. */
c6fb90c8
L		 1800 case 2:
1801 x.array [1] |= y.array [1];
1a0670f3 1802 /* Fall through. */
c6fb90c8
L		 1803 case 1:
1804 x.array [0] |= y.array [0];
40fb9820
L		 1805 break;
1806 default:
1807 abort ();
1808 }
c6fb90c8
L		 1809 return x;
1810}
40fb9820 1811
c6fb90c8
L		 1812static INLINE i386_operand_type
1813operand_type_xor (i386_operand_type x, i386_operand_type y)
1814{
1815 switch (ARRAY_SIZE (x.array))
1816 {
1817 case 3:
1818 x.array [2] ^= y.array [2];
1a0670f3 1819 /* Fall through. */
c6fb90c8
L		 1820 case 2:
1821 x.array [1] ^= y.array [1];
1a0670f3 1822 /* Fall through. */
c6fb90c8
L		 1823 case 1:
1824 x.array [0] ^= y.array [0];
1825 break;
1826 default:
1827 abort ();
1828 }
40fb9820
L		 1829 return x;
1830}
1831
1832static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1833static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
40fb9820
L		 1834static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1835static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1836static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1837static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1838static const i386_operand_type anydisp
1839 = OPERAND_TYPE_ANYDISP;
40fb9820 1840static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1841static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1842static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1843static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1844static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1845static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1846static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1847static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1848static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1849static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1850static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1851static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1852
1853enum operand_type
1854{
1855 reg,
40fb9820
L		 1856 imm,
1857 disp,
1858 anymem
1859};
1860
c6fb90c8 1861static INLINE int
40fb9820
L		 1862operand_type_check (i386_operand_type t, enum operand_type c)
1863{
1864 switch (c)
1865 {
1866 case reg:
dc821c5f 1867 return t.bitfield.reg;
40fb9820 1868
40fb9820
L		 1869 case imm:
1870 return (t.bitfield.imm8
1871 || t.bitfield.imm8s
1872 || t.bitfield.imm16
1873 || t.bitfield.imm32
1874 || t.bitfield.imm32s
1875 || t.bitfield.imm64);
1876
1877 case disp:
1878 return (t.bitfield.disp8
1879 || t.bitfield.disp16
1880 || t.bitfield.disp32
1881 || t.bitfield.disp32s
1882 || t.bitfield.disp64);
1883
1884 case anymem:
1885 return (t.bitfield.disp8
1886 || t.bitfield.disp16
1887 || t.bitfield.disp32
1888 || t.bitfield.disp32s
1889 || t.bitfield.disp64
1890 || t.bitfield.baseindex);
1891
1892 default:
1893 abort ();
1894 }
2cfe26b6
AM		 1895
1896 return 0;
40fb9820
L		 1897}
1898
7a54636a
L		 1899/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1900 between operand GIVEN and opeand WANTED for instruction template T. */
5c07affc
L		 1901
1902static INLINE int
7a54636a
L		 1903match_operand_size (const insn_template *t, unsigned int wanted,
1904 unsigned int given)
5c07affc 1905{
3ac21baa
JB		 1906 return !((i.types[given].bitfield.byte
1907 && !t->operand_types[wanted].bitfield.byte)
1908 || (i.types[given].bitfield.word
1909 && !t->operand_types[wanted].bitfield.word)
1910 || (i.types[given].bitfield.dword
1911 && !t->operand_types[wanted].bitfield.dword)
1912 || (i.types[given].bitfield.qword
1913 && !t->operand_types[wanted].bitfield.qword)
1914 || (i.types[given].bitfield.tbyte
1915 && !t->operand_types[wanted].bitfield.tbyte));
5c07affc
L		 1916}
1917
dd40ce22
L		 1918/* Return 1 if there is no conflict in SIMD register between operand
1919 GIVEN and opeand WANTED for instruction template T. */
1b54b8d7
JB		 1920
1921static INLINE int
dd40ce22
L		 1922match_simd_size (const insn_template *t, unsigned int wanted,
1923 unsigned int given)
1b54b8d7 1924{
3ac21baa
JB		 1925 return !((i.types[given].bitfield.xmmword
1926 && !t->operand_types[wanted].bitfield.xmmword)
1927 || (i.types[given].bitfield.ymmword
1928 && !t->operand_types[wanted].bitfield.ymmword)
1929 || (i.types[given].bitfield.zmmword
1930 && !t->operand_types[wanted].bitfield.zmmword));
1b54b8d7
JB		 1931}
1932
7a54636a
L		 1933/* Return 1 if there is no conflict in any size between operand GIVEN
1934 and opeand WANTED for instruction template T. */
5c07affc
L		 1935
1936static INLINE int
dd40ce22
L		 1937match_mem_size (const insn_template *t, unsigned int wanted,
1938 unsigned int given)
5c07affc 1939{
7a54636a 1940 return (match_operand_size (t, wanted, given)
3ac21baa 1941 && !((i.types[given].bitfield.unspecified
af508cb9 1942 && !i.broadcast
3ac21baa
JB		 1943 && !t->operand_types[wanted].bitfield.unspecified)
1944 || (i.types[given].bitfield.fword
1945 && !t->operand_types[wanted].bitfield.fword)
1b54b8d7
JB		 1946 /* For scalar opcode templates to allow register and memory
1947 operands at the same time, some special casing is needed
d6793fa1
JB		 1948 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1949 down-conversion vpmov*. */
3ac21baa 1950 || ((t->operand_types[wanted].bitfield.regsimd
1b54b8d7 1951 && !t->opcode_modifier.broadcast
3ac21baa
JB		 1952 && (t->operand_types[wanted].bitfield.byte
1953 || t->operand_types[wanted].bitfield.word
1954 || t->operand_types[wanted].bitfield.dword
1955 || t->operand_types[wanted].bitfield.qword))
1956 ? (i.types[given].bitfield.xmmword
1957 || i.types[given].bitfield.ymmword
1958 || i.types[given].bitfield.zmmword)
1959 : !match_simd_size(t, wanted, given))));
5c07affc
L		 1960}
1961
3ac21baa
JB		 1962/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1963 operands for instruction template T, and it has MATCH_REVERSE set if there
1964 is no size conflict on any operands for the template with operands reversed
1965 (and the template allows for reversing in the first place). */
5c07affc 1966
3ac21baa
JB		 1967#define MATCH_STRAIGHT 1
1968#define MATCH_REVERSE 2
1969
1970static INLINE unsigned int
d3ce72d0 1971operand_size_match (const insn_template *t)
5c07affc 1972{
3ac21baa 1973 unsigned int j, match = MATCH_STRAIGHT;
5c07affc
L		 1974
1975 /* Don't check jump instructions. */
1976 if (t->opcode_modifier.jump
1977 || t->opcode_modifier.jumpbyte
1978 || t->opcode_modifier.jumpdword
1979 || t->opcode_modifier.jumpintersegment)
1980 return match;
1981
1982 /* Check memory and accumulator operand size. */
1983 for (j = 0; j < i.operands; j++)
1984 {
1b54b8d7
JB		 1985 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1986 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1987 continue;
1988
1b54b8d7 1989 if (t->operand_types[j].bitfield.reg
7a54636a 1990 && !match_operand_size (t, j, j))
5c07affc
L		 1991 {
1992 match = 0;
1993 break;
1994 }
1995
1b54b8d7 1996 if (t->operand_types[j].bitfield.regsimd
3ac21baa 1997 && !match_simd_size (t, j, j))
1b54b8d7
JB		 1998 {
1999 match = 0;
2000 break;
2001 }
2002
2003 if (t->operand_types[j].bitfield.acc
7a54636a 2004 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
1b54b8d7
JB		 2005 {
2006 match = 0;
2007 break;
2008 }
2009
3ac21baa 2010 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
5c07affc
L		 2011 {
2012 match = 0;
2013 break;
2014 }
2015 }
2016
3ac21baa 2017 if (!t->opcode_modifier.d)
891edac4
L		 2018 {
2019mismatch:
3ac21baa
JB		 2020 if (!match)
2021 i.error = operand_size_mismatch;
2022 return match;
891edac4 2023 }
5c07affc
L		 2024
2025 /* Check reverse. */
9c2799c2 2026 gas_assert (i.operands == 2);
5c07affc 2027
5c07affc
L		 2028 for (j = 0; j < 2; j++)
2029 {
dc821c5f
JB		 2030 if ((t->operand_types[j].bitfield.reg
2031 || t->operand_types[j].bitfield.acc)
7a54636a 2032 && !match_operand_size (t, j, !j))
891edac4 2033 goto mismatch;
5c07affc 2034
3ac21baa
JB		 2035 if (i.types[!j].bitfield.mem
2036 && !match_mem_size (t, j, !j))
891edac4 2037 goto mismatch;
5c07affc
L		 2038 }
2039
3ac21baa 2040 return match | MATCH_REVERSE;
5c07affc
L		 2041}
2042
c6fb90c8 2043static INLINE int
40fb9820
L		 2044operand_type_match (i386_operand_type overlap,
2045 i386_operand_type given)
2046{
2047 i386_operand_type temp = overlap;
2048
2049 temp.bitfield.jumpabsolute = 0;
7d5e4556 2050 temp.bitfield.unspecified = 0;
5c07affc
L		 2051 temp.bitfield.byte = 0;
2052 temp.bitfield.word = 0;
2053 temp.bitfield.dword = 0;
2054 temp.bitfield.fword = 0;
2055 temp.bitfield.qword = 0;
2056 temp.bitfield.tbyte = 0;
2057 temp.bitfield.xmmword = 0;
c0f3af97 2058 temp.bitfield.ymmword = 0;
43234a1e 2059 temp.bitfield.zmmword = 0;
0dfbf9d7 2060 if (operand_type_all_zero (&temp))
891edac4 2061 goto mismatch;
40fb9820 2062
891edac4
L		 2063 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2064 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2065 return 1;
2066
2067mismatch:
a65babc9 2068 i.error = operand_type_mismatch;
891edac4 2069 return 0;
40fb9820
L		 2070}
2071
7d5e4556 2072/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2073 unless the expected operand type register overlap is null.
2074 Memory operand size of certain SIMD instructions is also being checked
2075 here. */
40fb9820 2076
c6fb90c8 2077static INLINE int
dc821c5f 2078operand_type_register_match (i386_operand_type g0,
40fb9820 2079 i386_operand_type t0,
40fb9820
L		 2080 i386_operand_type g1,
2081 i386_operand_type t1)
2082{
10c17abd
JB		 2083 if (!g0.bitfield.reg
2084 && !g0.bitfield.regsimd
2085 && (!operand_type_check (g0, anymem)
2086 || g0.bitfield.unspecified
2087 || !t0.bitfield.regsimd))
40fb9820
L		 2088 return 1;
2089
10c17abd
JB		 2090 if (!g1.bitfield.reg
2091 && !g1.bitfield.regsimd
2092 && (!operand_type_check (g1, anymem)
2093 || g1.bitfield.unspecified
2094 || !t1.bitfield.regsimd))
40fb9820
L		 2095 return 1;
2096
dc821c5f
JB		 2097 if (g0.bitfield.byte == g1.bitfield.byte
2098 && g0.bitfield.word == g1.bitfield.word
2099 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2100 && g0.bitfield.qword == g1.bitfield.qword
2101 && g0.bitfield.xmmword == g1.bitfield.xmmword
2102 && g0.bitfield.ymmword == g1.bitfield.ymmword
2103 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2104 return 1;
2105
dc821c5f
JB		 2106 if (!(t0.bitfield.byte & t1.bitfield.byte)
2107 && !(t0.bitfield.word & t1.bitfield.word)
2108 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2109 && !(t0.bitfield.qword & t1.bitfield.qword)
2110 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2111 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2112 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2113 return 1;
2114
a65babc9 2115 i.error = register_type_mismatch;
891edac4
L		 2116
2117 return 0;
40fb9820
L		 2118}
2119
4c692bc7
JB		 2120static INLINE unsigned int
2121register_number (const reg_entry *r)
2122{
2123 unsigned int nr = r->reg_num;
2124
2125 if (r->reg_flags & RegRex)
2126 nr += 8;
2127
200cbe0f
L		 2128 if (r->reg_flags & RegVRex)
2129 nr += 16;
2130
4c692bc7
JB		 2131 return nr;
2132}
2133
252b5132 2134static INLINE unsigned int
40fb9820 2135mode_from_disp_size (i386_operand_type t)
252b5132 2136{
b5014f7a 2137 if (t.bitfield.disp8)
40fb9820
L		 2138 return 1;
2139 else if (t.bitfield.disp16
2140 || t.bitfield.disp32
2141 || t.bitfield.disp32s)
2142 return 2;
2143 else
2144 return 0;
252b5132
RH		 2145}
2146
2147static INLINE int
65879393 2148fits_in_signed_byte (addressT num)
252b5132 2149{
65879393 2150 return num + 0x80 <= 0xff;
47926f60 2151}
252b5132
RH		 2152
2153static INLINE int
65879393 2154fits_in_unsigned_byte (addressT num)
252b5132 2155{
65879393 2156 return num <= 0xff;
47926f60 2157}
252b5132
RH		 2158
2159static INLINE int
65879393 2160fits_in_unsigned_word (addressT num)
252b5132 2161{
65879393 2162 return num <= 0xffff;
47926f60 2163}
252b5132
RH		 2164
2165static INLINE int
65879393 2166fits_in_signed_word (addressT num)
252b5132 2167{
65879393 2168 return num + 0x8000 <= 0xffff;
47926f60 2169}
2a962e6d 2170
3e73aa7c 2171static INLINE int
65879393 2172fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2173{
2174#ifndef BFD64
2175 return 1;
2176#else
65879393 2177 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2178#endif
2179} /* fits_in_signed_long() */
2a962e6d 2180
3e73aa7c 2181static INLINE int
65879393 2182fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2183{
2184#ifndef BFD64
2185 return 1;
2186#else
65879393 2187 return num <= 0xffffffff;
3e73aa7c
JH		 2188#endif
2189} /* fits_in_unsigned_long() */
252b5132 2190
43234a1e 2191static INLINE int
b5014f7a 2192fits_in_disp8 (offsetT num)
43234a1e
L		 2193{
2194 int shift = i.memshift;
2195 unsigned int mask;
2196
2197 if (shift == -1)
2198 abort ();
2199
2200 mask = (1 << shift) - 1;
2201
2202 /* Return 0 if NUM isn't properly aligned. */
2203 if ((num & mask))
2204 return 0;
2205
2206 /* Check if NUM will fit in 8bit after shift. */
2207 return fits_in_signed_byte (num >> shift);
2208}
2209
a683cc34
SP		 2210static INLINE int
2211fits_in_imm4 (offsetT num)
2212{
2213 return (num & 0xf) == num;
2214}
2215
40fb9820 2216static i386_operand_type
e3bb37b5 2217smallest_imm_type (offsetT num)
252b5132 2218{
40fb9820 2219 i386_operand_type t;
7ab9ffdd 2220
0dfbf9d7 2221 operand_type_set (&t, 0);
40fb9820
L		 2222 t.bitfield.imm64 = 1;
2223
2224 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2225 {
2226 /* This code is disabled on the 486 because all the Imm1 forms
2227 in the opcode table are slower on the i486. They're the
2228 versions with the implicitly specified single-position
2229 displacement, which has another syntax if you really want to
2230 use that form. */
40fb9820
L		 2231 t.bitfield.imm1 = 1;
2232 t.bitfield.imm8 = 1;
2233 t.bitfield.imm8s = 1;
2234 t.bitfield.imm16 = 1;
2235 t.bitfield.imm32 = 1;
2236 t.bitfield.imm32s = 1;
2237 }
2238 else if (fits_in_signed_byte (num))
2239 {
2240 t.bitfield.imm8 = 1;
2241 t.bitfield.imm8s = 1;
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2245 }
2246 else if (fits_in_unsigned_byte (num))
2247 {
2248 t.bitfield.imm8 = 1;
2249 t.bitfield.imm16 = 1;
2250 t.bitfield.imm32 = 1;
2251 t.bitfield.imm32s = 1;
2252 }
2253 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2254 {
2255 t.bitfield.imm16 = 1;
2256 t.bitfield.imm32 = 1;
2257 t.bitfield.imm32s = 1;
2258 }
2259 else if (fits_in_signed_long (num))
2260 {
2261 t.bitfield.imm32 = 1;
2262 t.bitfield.imm32s = 1;
2263 }
2264 else if (fits_in_unsigned_long (num))
2265 t.bitfield.imm32 = 1;
2266
2267 return t;
47926f60 2268}
252b5132 2269
847f7ad4 2270static offsetT
e3bb37b5 2271offset_in_range (offsetT val, int size)
847f7ad4 2272{
508866be 2273 addressT mask;
ba2adb93 2274
847f7ad4
AM		 2275 switch (size)
2276 {
508866be
L		 2277 case 1: mask = ((addressT) 1 << 8) - 1; break;
2278 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2279 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2280#ifdef BFD64
2281 case 8: mask = ((addressT) 2 << 63) - 1; break;
2282#endif
47926f60 2283 default: abort ();
847f7ad4
AM		 2284 }
2285
9de868bf
L		 2286#ifdef BFD64
2287 /* If BFD64, sign extend val for 32bit address mode. */
2288 if (flag_code != CODE_64BIT
2289 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2290 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2291 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2292#endif
ba2adb93 2293
47926f60 2294 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2295 {
2296 char buf1[40], buf2[40];
2297
2298 sprint_value (buf1, val);
2299 sprint_value (buf2, val & mask);
2300 as_warn (_("%s shortened to %s"), buf1, buf2);
2301 }
2302 return val & mask;
2303}
2304
c32fa91d
L		 2305enum PREFIX_GROUP
2306{
2307 PREFIX_EXIST = 0,
2308 PREFIX_LOCK,
2309 PREFIX_REP,
04ef582a 2310 PREFIX_DS,
c32fa91d
L		 2311 PREFIX_OTHER
2312};
2313
2314/* Returns
2315 a. PREFIX_EXIST if attempting to add a prefix where one from the
2316 same class already exists.
2317 b. PREFIX_LOCK if lock prefix is added.
2318 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2319 d. PREFIX_DS if ds prefix is added.
2320 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2321 */
2322
2323static enum PREFIX_GROUP
e3bb37b5 2324add_prefix (unsigned int prefix)
252b5132 2325{
c32fa91d 2326 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2327 unsigned int q;
252b5132 2328
29b0f896
AM		 2329 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2330 && flag_code == CODE_64BIT)
b1905489 2331 {
161a04f6 2332 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
44846f29
JB		 2333 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2334 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2335 || (i.prefix[REX_PREFIX] & prefix & REX_B))
c32fa91d 2336 ret = PREFIX_EXIST;
b1905489
JB		 2337 q = REX_PREFIX;
2338 }
3e73aa7c 2339 else
b1905489
JB		 2340 {
2341 switch (prefix)
2342 {
2343 default:
2344 abort ();
2345
b1905489 2346 case DS_PREFIX_OPCODE:
04ef582a
L		 2347 ret = PREFIX_DS;
2348 /* Fall through. */
2349 case CS_PREFIX_OPCODE:
b1905489
JB		 2350 case ES_PREFIX_OPCODE:
2351 case FS_PREFIX_OPCODE:
2352 case GS_PREFIX_OPCODE:
2353 case SS_PREFIX_OPCODE:
2354 q = SEG_PREFIX;
2355 break;
2356
2357 case REPNE_PREFIX_OPCODE:
2358 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2359 q = REP_PREFIX;
2360 ret = PREFIX_REP;
2361 break;
2362
b1905489 2363 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2364 q = LOCK_PREFIX;
2365 ret = PREFIX_LOCK;
b1905489
JB		 2366 break;
2367
2368 case FWAIT_OPCODE:
2369 q = WAIT_PREFIX;
2370 break;
2371
2372 case ADDR_PREFIX_OPCODE:
2373 q = ADDR_PREFIX;
2374 break;
2375
2376 case DATA_PREFIX_OPCODE:
2377 q = DATA_PREFIX;
2378 break;
2379 }
2380 if (i.prefix[q] != 0)
c32fa91d 2381 ret = PREFIX_EXIST;
b1905489 2382 }
252b5132 2383
b1905489 2384 if (ret)
252b5132 2385 {
b1905489
JB		 2386 if (!i.prefix[q])
2387 ++i.prefixes;
2388 i.prefix[q] |= prefix;
252b5132 2389 }
b1905489
JB		 2390 else
2391 as_bad (_("same type of prefix used twice"));
252b5132 2392
252b5132
RH		 2393 return ret;
2394}
2395
2396static void
78f12dd3 2397update_code_flag (int value, int check)
eecb386c 2398{
78f12dd3
L		 2399 PRINTF_LIKE ((*as_error));
2400
1e9cc1c2 2401 flag_code = (enum flag_code) value;
40fb9820
L		 2402 if (flag_code == CODE_64BIT)
2403 {
2404 cpu_arch_flags.bitfield.cpu64 = 1;
2405 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2406 }
2407 else
2408 {
2409 cpu_arch_flags.bitfield.cpu64 = 0;
2410 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2411 }
2412 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2413 {
78f12dd3
L		 2414 if (check)
2415 as_error = as_fatal;
2416 else
2417 as_error = as_bad;
2418 (*as_error) (_("64bit mode not supported on `%s'."),
2419 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2420 }
40fb9820 2421 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2422 {
78f12dd3
L		 2423 if (check)
2424 as_error = as_fatal;
2425 else
2426 as_error = as_bad;
2427 (*as_error) (_("32bit mode not supported on `%s'."),
2428 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2429 }
eecb386c
AM		 2430 stackop_size = '\0';
2431}
2432
78f12dd3
L		 2433static void
2434set_code_flag (int value)
2435{
2436 update_code_flag (value, 0);
2437}
2438
eecb386c 2439static void
e3bb37b5 2440set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2441{
1e9cc1c2 2442 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2443 if (flag_code != CODE_16BIT)
2444 abort ();
2445 cpu_arch_flags.bitfield.cpu64 = 0;
2446 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2447 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2448}
2449
2450static void
e3bb37b5 2451set_intel_syntax (int syntax_flag)
252b5132
RH		 2452{
2453 /* Find out if register prefixing is specified. */
2454 int ask_naked_reg = 0;
2455
2456 SKIP_WHITESPACE ();
29b0f896 2457 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2458 {
d02603dc
NC		 2459 char *string;
2460 int e = get_symbol_name (&string);
252b5132 2461
47926f60 2462 if (strcmp (string, "prefix") == 0)
252b5132 2463 ask_naked_reg = 1;
47926f60 2464 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2465 ask_naked_reg = -1;
2466 else
d0b47220 2467 as_bad (_("bad argument to syntax directive."));
d02603dc 2468 (void) restore_line_pointer (e);
252b5132
RH		 2469 }
2470 demand_empty_rest_of_line ();
c3332e24 2471
252b5132
RH		 2472 intel_syntax = syntax_flag;
2473
2474 if (ask_naked_reg == 0)
f86103b7
AM		 2475 allow_naked_reg = (intel_syntax
2476 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2477 else
2478 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2479
ee86248c 2480 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2481
e4a3b5a4 2482 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2483 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2484 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2485}
2486
1efbbeb4
L		 2487static void
2488set_intel_mnemonic (int mnemonic_flag)
2489{
e1d4d893 2490 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2491}
2492
db51cc60
L		 2493static void
2494set_allow_index_reg (int flag)
2495{
2496 allow_index_reg = flag;
2497}
2498
cb19c032 2499static void
7bab8ab5 2500set_check (int what)
cb19c032 2501{
7bab8ab5
JB		 2502 enum check_kind *kind;
2503 const char *str;
2504
2505 if (what)
2506 {
2507 kind = &operand_check;
2508 str = "operand";
2509 }
2510 else
2511 {
2512 kind = &sse_check;
2513 str = "sse";
2514 }
2515
cb19c032
L		 2516 SKIP_WHITESPACE ();
2517
2518 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2519 {
d02603dc
NC		 2520 char *string;
2521 int e = get_symbol_name (&string);
cb19c032
L		 2522
2523 if (strcmp (string, "none") == 0)
7bab8ab5 2524 *kind = check_none;
cb19c032 2525 else if (strcmp (string, "warning") == 0)
7bab8ab5 2526 *kind = check_warning;
cb19c032 2527 else if (strcmp (string, "error") == 0)
7bab8ab5 2528 *kind = check_error;
cb19c032 2529 else
7bab8ab5 2530 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2531 (void) restore_line_pointer (e);
cb19c032
L		 2532 }
2533 else
7bab8ab5 2534 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2535
2536 demand_empty_rest_of_line ();
2537}
2538
8a9036a4
L		 2539static void
2540check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2541 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2542{
2543#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2544 static const char *arch;
2545
2546 /* Intel LIOM is only supported on ELF. */
2547 if (!IS_ELF)
2548 return;
2549
2550 if (!arch)
2551 {
2552 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2553 use default_arch. */
2554 arch = cpu_arch_name;
2555 if (!arch)
2556 arch = default_arch;
2557 }
2558
81486035
L		 2559 /* If we are targeting Intel MCU, we must enable it. */
2560 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2561 || new_flag.bitfield.cpuiamcu)
2562 return;
2563
3632d14b 2564 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2565 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2566 || new_flag.bitfield.cpul1om)
8a9036a4 2567 return;
76ba9986 2568
7a9068fe
L		 2569 /* If we are targeting Intel K1OM, we must enable it. */
2570 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2571 || new_flag.bitfield.cpuk1om)
2572 return;
2573
8a9036a4
L		 2574 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2575#endif
2576}
2577
e413e4e9 2578static void
e3bb37b5 2579set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2580{
47926f60 2581 SKIP_WHITESPACE ();
e413e4e9 2582
29b0f896 2583 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2584 {
d02603dc
NC		 2585 char *string;
2586 int e = get_symbol_name (&string);
91d6fa6a 2587 unsigned int j;
40fb9820 2588 i386_cpu_flags flags;
e413e4e9 2589
91d6fa6a 2590 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2591 {
91d6fa6a 2592 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2593 {
91d6fa6a 2594 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2595
5c6af06e
JB		 2596 if (*string != '.')
2597 {
91d6fa6a 2598 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2599 cpu_sub_arch_name = NULL;
91d6fa6a 2600 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2601 if (flag_code == CODE_64BIT)
2602 {
2603 cpu_arch_flags.bitfield.cpu64 = 1;
2604 cpu_arch_flags.bitfield.cpuno64 = 0;
2605 }
2606 else
2607 {
2608 cpu_arch_flags.bitfield.cpu64 = 0;
2609 cpu_arch_flags.bitfield.cpuno64 = 1;
2610 }
91d6fa6a
NC		 2611 cpu_arch_isa = cpu_arch[j].type;
2612 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2613 if (!cpu_arch_tune_set)
2614 {
2615 cpu_arch_tune = cpu_arch_isa;
2616 cpu_arch_tune_flags = cpu_arch_isa_flags;
2617 }
5c6af06e
JB		 2618 break;
2619 }
40fb9820 2620
293f5f65
L		 2621 flags = cpu_flags_or (cpu_arch_flags,
2622 cpu_arch[j].flags);
81486035 2623
5b64d091 2624 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2625 {
6305a203
L		 2626 if (cpu_sub_arch_name)
2627 {
2628 char *name = cpu_sub_arch_name;
2629 cpu_sub_arch_name = concat (name,
91d6fa6a 2630 cpu_arch[j].name,
1bf57e9f 2631 (const char *) NULL);
6305a203
L		 2632 free (name);
2633 }
2634 else
91d6fa6a 2635 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2636 cpu_arch_flags = flags;
a586129e 2637 cpu_arch_isa_flags = flags;
5c6af06e 2638 }
0089dace
L		 2639 else
2640 cpu_arch_isa_flags
2641 = cpu_flags_or (cpu_arch_isa_flags,
2642 cpu_arch[j].flags);
d02603dc 2643 (void) restore_line_pointer (e);
5c6af06e
JB		 2644 demand_empty_rest_of_line ();
2645 return;
e413e4e9
AM		 2646 }
2647 }
293f5f65
L		 2648
2649 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2650 {
33eaf5de 2651 /* Disable an ISA extension. */
293f5f65
L		 2652 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2653 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2654 {
2655 flags = cpu_flags_and_not (cpu_arch_flags,
2656 cpu_noarch[j].flags);
2657 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2658 {
2659 if (cpu_sub_arch_name)
2660 {
2661 char *name = cpu_sub_arch_name;
2662 cpu_sub_arch_name = concat (name, string,
2663 (const char *) NULL);
2664 free (name);
2665 }
2666 else
2667 cpu_sub_arch_name = xstrdup (string);
2668 cpu_arch_flags = flags;
2669 cpu_arch_isa_flags = flags;
2670 }
2671 (void) restore_line_pointer (e);
2672 demand_empty_rest_of_line ();
2673 return;
2674 }
2675
2676 j = ARRAY_SIZE (cpu_arch);
2677 }
2678
91d6fa6a 2679 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2680 as_bad (_("no such architecture: `%s'"), string);
2681
2682 *input_line_pointer = e;
2683 }
2684 else
2685 as_bad (_("missing cpu architecture"));
2686
fddf5b5b
AM		 2687 no_cond_jump_promotion = 0;
2688 if (*input_line_pointer == ','
29b0f896 2689 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2690 {
d02603dc
NC		 2691 char *string;
2692 char e;
2693
2694 ++input_line_pointer;
2695 e = get_symbol_name (&string);
fddf5b5b
AM		 2696
2697 if (strcmp (string, "nojumps") == 0)
2698 no_cond_jump_promotion = 1;
2699 else if (strcmp (string, "jumps") == 0)
2700 ;
2701 else
2702 as_bad (_("no such architecture modifier: `%s'"), string);
2703
d02603dc 2704 (void) restore_line_pointer (e);
fddf5b5b
AM		 2705 }
2706
e413e4e9
AM		 2707 demand_empty_rest_of_line ();
2708}
2709
8a9036a4
L		 2710enum bfd_architecture
2711i386_arch (void)
2712{
3632d14b 2713 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2714 {
2715 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2716 || flag_code != CODE_64BIT)
2717 as_fatal (_("Intel L1OM is 64bit ELF only"));
2718 return bfd_arch_l1om;
2719 }
7a9068fe
L		 2720 else if (cpu_arch_isa == PROCESSOR_K1OM)
2721 {
2722 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2723 || flag_code != CODE_64BIT)
2724 as_fatal (_("Intel K1OM is 64bit ELF only"));
2725 return bfd_arch_k1om;
2726 }
81486035
L		 2727 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2728 {
2729 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2730 || flag_code == CODE_64BIT)
2731 as_fatal (_("Intel MCU is 32bit ELF only"));
2732 return bfd_arch_iamcu;
2733 }
8a9036a4
L		 2734 else
2735 return bfd_arch_i386;
2736}
2737
b9d79e03 2738unsigned long
7016a5d5 2739i386_mach (void)
b9d79e03 2740{
351f65ca 2741 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2742 {
3632d14b 2743 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2744 {
351f65ca
L		 2745 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2746 || default_arch[6] != '\0')
8a9036a4
L		 2747 as_fatal (_("Intel L1OM is 64bit ELF only"));
2748 return bfd_mach_l1om;
2749 }
7a9068fe
L		 2750 else if (cpu_arch_isa == PROCESSOR_K1OM)
2751 {
2752 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2753 || default_arch[6] != '\0')
2754 as_fatal (_("Intel K1OM is 64bit ELF only"));
2755 return bfd_mach_k1om;
2756 }
351f65ca 2757 else if (default_arch[6] == '\0')
8a9036a4 2758 return bfd_mach_x86_64;
351f65ca
L		 2759 else
2760 return bfd_mach_x64_32;
8a9036a4 2761 }
5197d474
L		 2762 else if (!strcmp (default_arch, "i386")
2763 || !strcmp (default_arch, "iamcu"))
81486035
L		 2764 {
2765 if (cpu_arch_isa == PROCESSOR_IAMCU)
2766 {
2767 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2768 as_fatal (_("Intel MCU is 32bit ELF only"));
2769 return bfd_mach_i386_iamcu;
2770 }
2771 else
2772 return bfd_mach_i386_i386;
2773 }
b9d79e03 2774 else
2b5d6a91 2775 as_fatal (_("unknown architecture"));
b9d79e03 2776}
b9d79e03 2777\f
252b5132 2778void
7016a5d5 2779md_begin (void)
252b5132
RH		 2780{
2781 const char *hash_err;
2782
86fa6981
L		 2783 /* Support pseudo prefixes like {disp32}. */
2784 lex_type ['{'] = LEX_BEGIN_NAME;
2785
47926f60 2786 /* Initialize op_hash hash table. */
252b5132
RH		 2787 op_hash = hash_new ();
2788
2789 {
d3ce72d0 2790 const insn_template *optab;
29b0f896 2791 templates *core_optab;
252b5132 2792
47926f60
KH		 2793 /* Setup for loop. */
2794 optab = i386_optab;
add39d23 2795 core_optab = XNEW (templates);
252b5132
RH		 2796 core_optab->start = optab;
2797
2798 while (1)
2799 {
2800 ++optab;
2801 if (optab->name == NULL
2802 || strcmp (optab->name, (optab - 1)->name) != 0)
2803 {
2804 /* different name --> ship out current template list;
47926f60 2805 add to hash table; & begin anew. */
252b5132
RH		 2806 core_optab->end = optab;
2807 hash_err = hash_insert (op_hash,
2808 (optab - 1)->name,
5a49b8ac 2809 (void *) core_optab);
252b5132
RH		 2810 if (hash_err)
2811 {
b37df7c4 2812 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2813 (optab - 1)->name,
2814 hash_err);
2815 }
2816 if (optab->name == NULL)
2817 break;
add39d23 2818 core_optab = XNEW (templates);
252b5132
RH		 2819 core_optab->start = optab;
2820 }
2821 }
2822 }
2823
47926f60 2824 /* Initialize reg_hash hash table. */
252b5132
RH		 2825 reg_hash = hash_new ();
2826 {
29b0f896 2827 const reg_entry *regtab;
c3fe08fa 2828 unsigned int regtab_size = i386_regtab_size;
252b5132 2829
c3fe08fa 2830 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2831 {
5a49b8ac 2832 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2833 if (hash_err)
b37df7c4 2834 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2835 regtab->reg_name,
2836 hash_err);
252b5132
RH		 2837 }
2838 }
2839
47926f60 2840 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2841 {
29b0f896
AM		 2842 int c;
2843 char *p;
252b5132
RH		 2844
2845 for (c = 0; c < 256; c++)
2846 {
3882b010 2847 if (ISDIGIT (c))
252b5132
RH		 2848 {
2849 digit_chars[c] = c;
2850 mnemonic_chars[c] = c;
2851 register_chars[c] = c;
2852 operand_chars[c] = c;
2853 }
3882b010 2854 else if (ISLOWER (c))
252b5132
RH		 2855 {
2856 mnemonic_chars[c] = c;
2857 register_chars[c] = c;
2858 operand_chars[c] = c;
2859 }
3882b010 2860 else if (ISUPPER (c))
252b5132 2861 {
3882b010 2862 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2863 register_chars[c] = mnemonic_chars[c];
2864 operand_chars[c] = c;
2865 }
43234a1e 2866 else if (c == '{' || c == '}')
86fa6981
L		 2867 {
2868 mnemonic_chars[c] = c;
2869 operand_chars[c] = c;
2870 }
252b5132 2871
3882b010 2872 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2873 identifier_chars[c] = c;
2874 else if (c >= 128)
2875 {
2876 identifier_chars[c] = c;
2877 operand_chars[c] = c;
2878 }
2879 }
2880
2881#ifdef LEX_AT
2882 identifier_chars['@'] = '@';
32137342
NC		 2883#endif
2884#ifdef LEX_QM
2885 identifier_chars['?'] = '?';
2886 operand_chars['?'] = '?';
252b5132 2887#endif
252b5132 2888 digit_chars['-'] = '-';
c0f3af97 2889 mnemonic_chars['_'] = '_';
791fe849 2890 mnemonic_chars['-'] = '-';
0003779b 2891 mnemonic_chars['.'] = '.';
252b5132
RH		 2892 identifier_chars['_'] = '_';
2893 identifier_chars['.'] = '.';
2894
2895 for (p = operand_special_chars; *p != '\0'; p++)
2896 operand_chars[(unsigned char) *p] = *p;
2897 }
2898
a4447b93
RH		 2899 if (flag_code == CODE_64BIT)
2900 {
ca19b261
KT		 2901#if defined (OBJ_COFF) && defined (TE_PE)
2902 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2903 ? 32 : 16);
2904#else
a4447b93 2905 x86_dwarf2_return_column = 16;
ca19b261 2906#endif
61ff971f 2907 x86_cie_data_alignment = -8;
a4447b93
RH		 2908 }
2909 else
2910 {
2911 x86_dwarf2_return_column = 8;
2912 x86_cie_data_alignment = -4;
2913 }
252b5132
RH		 2914}
2915
2916void
e3bb37b5 2917i386_print_statistics (FILE *file)
252b5132
RH		 2918{
2919 hash_print_statistics (file, "i386 opcode", op_hash);
2920 hash_print_statistics (file, "i386 register", reg_hash);
2921}
2922\f
252b5132
RH		 2923#ifdef DEBUG386
2924
ce8a8b2f 2925/* Debugging routines for md_assemble. */
d3ce72d0 2926static void pte (insn_template *);
40fb9820 2927static void pt (i386_operand_type);
e3bb37b5
L		 2928static void pe (expressionS *);
2929static void ps (symbolS *);
252b5132
RH		 2930
2931static void
e3bb37b5 2932pi (char *line, i386_insn *x)
252b5132 2933{
09137c09 2934 unsigned int j;
252b5132
RH		 2935
2936 fprintf (stdout, "%s: template ", line);
2937 pte (&x->tm);
09f131f2
JH		 2938 fprintf (stdout, " address: base %s index %s scale %x\n",
2939 x->base_reg ? x->base_reg->reg_name : "none",
2940 x->index_reg ? x->index_reg->reg_name : "none",
2941 x->log2_scale_factor);
2942 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2943 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2944 fprintf (stdout, " sib: base %x index %x scale %x\n",
2945 x->sib.base, x->sib.index, x->sib.scale);
2946 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2947 (x->rex & REX_W) != 0,
2948 (x->rex & REX_R) != 0,
2949 (x->rex & REX_X) != 0,
2950 (x->rex & REX_B) != 0);
09137c09 2951 for (j = 0; j < x->operands; j++)
252b5132 2952 {
09137c09
SP		 2953 fprintf (stdout, " #%d: ", j + 1);
2954 pt (x->types[j]);
252b5132 2955 fprintf (stdout, "\n");
dc821c5f 2956 if (x->types[j].bitfield.reg
09137c09 2957 || x->types[j].bitfield.regmmx
1b54b8d7 2958 || x->types[j].bitfield.regsimd
09137c09
SP		 2959 || x->types[j].bitfield.sreg2
2960 || x->types[j].bitfield.sreg3
2961 || x->types[j].bitfield.control
2962 || x->types[j].bitfield.debug
2963 || x->types[j].bitfield.test)
2964 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2965 if (operand_type_check (x->types[j], imm))
2966 pe (x->op[j].imms);
2967 if (operand_type_check (x->types[j], disp))
2968 pe (x->op[j].disps);
252b5132
RH		 2969 }
2970}
2971
2972static void
d3ce72d0 2973pte (insn_template *t)
252b5132 2974{
09137c09 2975 unsigned int j;
252b5132 2976 fprintf (stdout, " %d operands ", t->operands);
47926f60 2977 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2978 if (t->extension_opcode != None)
2979 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2980 if (t->opcode_modifier.d)
252b5132 2981 fprintf (stdout, "D");
40fb9820 2982 if (t->opcode_modifier.w)
252b5132
RH		 2983 fprintf (stdout, "W");
2984 fprintf (stdout, "\n");
09137c09 2985 for (j = 0; j < t->operands; j++)
252b5132 2986 {
09137c09
SP		 2987 fprintf (stdout, " #%d type ", j + 1);
2988 pt (t->operand_types[j]);
252b5132
RH		 2989 fprintf (stdout, "\n");
2990 }
2991}
2992
2993static void
e3bb37b5 2994pe (expressionS *e)
252b5132 2995{
24eab124 2996 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2997 fprintf (stdout, " add_number %ld (%lx)\n",
2998 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2999 if (e->X_add_symbol)
3000 {
3001 fprintf (stdout, " add_symbol ");
3002 ps (e->X_add_symbol);
3003 fprintf (stdout, "\n");
3004 }
3005 if (e->X_op_symbol)
3006 {
3007 fprintf (stdout, " op_symbol ");
3008 ps (e->X_op_symbol);
3009 fprintf (stdout, "\n");
3010 }
3011}
3012
3013static void
e3bb37b5 3014ps (symbolS *s)
252b5132
RH		 3015{
3016 fprintf (stdout, "%s type %s%s",
3017 S_GET_NAME (s),
3018 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3019 segment_name (S_GET_SEGMENT (s)));
3020}
3021
7b81dfbb 3022static struct type_name
252b5132 3023 {
40fb9820
L		 3024 i386_operand_type mask;
3025 const char *name;
252b5132 3026 }
7b81dfbb 3027const type_names[] =
252b5132 3028{
40fb9820
L		 3029 { OPERAND_TYPE_REG8, "r8" },
3030 { OPERAND_TYPE_REG16, "r16" },
3031 { OPERAND_TYPE_REG32, "r32" },
3032 { OPERAND_TYPE_REG64, "r64" },
3033 { OPERAND_TYPE_IMM8, "i8" },
3034 { OPERAND_TYPE_IMM8, "i8s" },
3035 { OPERAND_TYPE_IMM16, "i16" },
3036 { OPERAND_TYPE_IMM32, "i32" },
3037 { OPERAND_TYPE_IMM32S, "i32s" },
3038 { OPERAND_TYPE_IMM64, "i64" },
3039 { OPERAND_TYPE_IMM1, "i1" },
3040 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3041 { OPERAND_TYPE_DISP8, "d8" },
3042 { OPERAND_TYPE_DISP16, "d16" },
3043 { OPERAND_TYPE_DISP32, "d32" },
3044 { OPERAND_TYPE_DISP32S, "d32s" },
3045 { OPERAND_TYPE_DISP64, "d64" },
3046 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3047 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3048 { OPERAND_TYPE_CONTROL, "control reg" },
3049 { OPERAND_TYPE_TEST, "test reg" },
3050 { OPERAND_TYPE_DEBUG, "debug reg" },
3051 { OPERAND_TYPE_FLOATREG, "FReg" },
3052 { OPERAND_TYPE_FLOATACC, "FAcc" },
3053 { OPERAND_TYPE_SREG2, "SReg2" },
3054 { OPERAND_TYPE_SREG3, "SReg3" },
3055 { OPERAND_TYPE_ACC, "Acc" },
3056 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3057 { OPERAND_TYPE_REGMMX, "rMMX" },
3058 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3059 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3060 { OPERAND_TYPE_REGZMM, "rZMM" },
3061 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3062 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3063};
3064
3065static void
40fb9820 3066pt (i386_operand_type t)
252b5132 3067{
40fb9820 3068 unsigned int j;
c6fb90c8 3069 i386_operand_type a;
252b5132 3070
40fb9820 3071 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3072 {
3073 a = operand_type_and (t, type_names[j].mask);
0349dc08 3074 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3075 fprintf (stdout, "%s, ", type_names[j].name);
3076 }
252b5132
RH		 3077 fflush (stdout);
3078}
3079
3080#endif /* DEBUG386 */
3081\f
252b5132 3082static bfd_reloc_code_real_type
3956db08 3083reloc (unsigned int size,
64e74474
AM		 3084 int pcrel,
3085 int sign,
3086 bfd_reloc_code_real_type other)
252b5132 3087{
47926f60 3088 if (other != NO_RELOC)
3956db08 3089 {
91d6fa6a 3090 reloc_howto_type *rel;
3956db08
JB		 3091
3092 if (size == 8)
3093 switch (other)
3094 {
64e74474
AM		 3095 case BFD_RELOC_X86_64_GOT32:
3096 return BFD_RELOC_X86_64_GOT64;
3097 break;
553d1284
L		 3098 case BFD_RELOC_X86_64_GOTPLT64:
3099 return BFD_RELOC_X86_64_GOTPLT64;
3100 break;
64e74474
AM		 3101 case BFD_RELOC_X86_64_PLTOFF64:
3102 return BFD_RELOC_X86_64_PLTOFF64;
3103 break;
3104 case BFD_RELOC_X86_64_GOTPC32:
3105 other = BFD_RELOC_X86_64_GOTPC64;
3106 break;
3107 case BFD_RELOC_X86_64_GOTPCREL:
3108 other = BFD_RELOC_X86_64_GOTPCREL64;
3109 break;
3110 case BFD_RELOC_X86_64_TPOFF32:
3111 other = BFD_RELOC_X86_64_TPOFF64;
3112 break;
3113 case BFD_RELOC_X86_64_DTPOFF32:
3114 other = BFD_RELOC_X86_64_DTPOFF64;
3115 break;
3116 default:
3117 break;
3956db08 3118 }
e05278af 3119
8ce3d284 3120#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3121 if (other == BFD_RELOC_SIZE32)
3122 {
3123 if (size == 8)
1ab668bf 3124 other = BFD_RELOC_SIZE64;
8fd4256d 3125 if (pcrel)
1ab668bf
AM		 3126 {
3127 as_bad (_("there are no pc-relative size relocations"));
3128 return NO_RELOC;
3129 }
8fd4256d 3130 }
8ce3d284 3131#endif
8fd4256d 3132
e05278af 3133 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3134 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3135 sign = -1;
3136
91d6fa6a
NC		 3137 rel = bfd_reloc_type_lookup (stdoutput, other);
3138 if (!rel)
3956db08 3139 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3140 else if (size != bfd_get_reloc_size (rel))
3956db08 3141 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3142 bfd_get_reloc_size (rel),
3956db08 3143 size);
91d6fa6a 3144 else if (pcrel && !rel->pc_relative)
3956db08 3145 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3146 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3147 && !sign)
91d6fa6a 3148 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3149 && sign > 0))
3956db08
JB		 3150 as_bad (_("relocated field and relocation type differ in signedness"));
3151 else
3152 return other;
3153 return NO_RELOC;
3154 }
252b5132
RH		 3155
3156 if (pcrel)
3157 {
3e73aa7c 3158 if (!sign)
3956db08 3159 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3160 switch (size)
3161 {
3162 case 1: return BFD_RELOC_8_PCREL;
3163 case 2: return BFD_RELOC_16_PCREL;
d258b828 3164 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3165 case 8: return BFD_RELOC_64_PCREL;
252b5132 3166 }
3956db08 3167 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3168 }
3169 else
3170 {
3956db08 3171 if (sign > 0)
e5cb08ac 3172 switch (size)
3e73aa7c
JH		 3173 {
3174 case 4: return BFD_RELOC_X86_64_32S;
3175 }
3176 else
3177 switch (size)
3178 {
3179 case 1: return BFD_RELOC_8;
3180 case 2: return BFD_RELOC_16;
3181 case 4: return BFD_RELOC_32;
3182 case 8: return BFD_RELOC_64;
3183 }
3956db08
JB		 3184 as_bad (_("cannot do %s %u byte relocation"),
3185 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3186 }
3187
0cc9e1d3 3188 return NO_RELOC;
252b5132
RH		 3189}
3190
47926f60
KH		 3191/* Here we decide which fixups can be adjusted to make them relative to
3192 the beginning of the section instead of the symbol. Basically we need
3193 to make sure that the dynamic relocations are done correctly, so in
3194 some cases we force the original symbol to be used. */
3195
252b5132 3196int
e3bb37b5 3197tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3198{
6d249963 3199#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3200 if (!IS_ELF)
31312f95
AM		 3201 return 1;
3202
a161fe53
AM		 3203 /* Don't adjust pc-relative references to merge sections in 64-bit
3204 mode. */
3205 if (use_rela_relocations
3206 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3207 && fixP->fx_pcrel)
252b5132 3208 return 0;
31312f95 3209
8d01d9a9
AJ		 3210 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3211 and changed later by validate_fix. */
3212 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3213 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3214 return 0;
3215
8fd4256d
L		 3216 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3217 for size relocations. */
3218 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3219 || fixP->fx_r_type == BFD_RELOC_SIZE64
3220 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3221 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3222 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3223 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3233 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3239 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3241 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3242 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3243 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3245 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3247 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3248 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3249 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3250 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3251 return 0;
31312f95 3252#endif
252b5132
RH		 3253 return 1;
3254}
252b5132 3255
b4cac588 3256static int
e3bb37b5 3257intel_float_operand (const char *mnemonic)
252b5132 3258{
9306ca4a
JB		 3259 /* Note that the value returned is meaningful only for opcodes with (memory)
3260 operands, hence the code here is free to improperly handle opcodes that
3261 have no operands (for better performance and smaller code). */
3262
3263 if (mnemonic[0] != 'f')
3264 return 0; /* non-math */
3265
3266 switch (mnemonic[1])
3267 {
3268 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3269 the fs segment override prefix not currently handled because no
3270 call path can make opcodes without operands get here */
3271 case 'i':
3272 return 2 /* integer op */;
3273 case 'l':
3274 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3275 return 3; /* fldcw/fldenv */
3276 break;
3277 case 'n':
3278 if (mnemonic[2] != 'o' /* fnop */)
3279 return 3; /* non-waiting control op */
3280 break;
3281 case 'r':
3282 if (mnemonic[2] == 's')
3283 return 3; /* frstor/frstpm */
3284 break;
3285 case 's':
3286 if (mnemonic[2] == 'a')
3287 return 3; /* fsave */
3288 if (mnemonic[2] == 't')
3289 {
3290 switch (mnemonic[3])
3291 {
3292 case 'c': /* fstcw */
3293 case 'd': /* fstdw */
3294 case 'e': /* fstenv */
3295 case 's': /* fsts[gw] */
3296 return 3;
3297 }
3298 }
3299 break;
3300 case 'x':
3301 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3302 return 0; /* fxsave/fxrstor are not really math ops */
3303 break;
3304 }
252b5132 3305
9306ca4a 3306 return 1;
252b5132
RH		 3307}
3308
c0f3af97
L		 3309/* Build the VEX prefix. */
3310
3311static void
d3ce72d0 3312build_vex_prefix (const insn_template *t)
c0f3af97
L		 3313{
3314 unsigned int register_specifier;
3315 unsigned int implied_prefix;
3316 unsigned int vector_length;
3317
3318 /* Check register specifier. */
3319 if (i.vex.register_specifier)
43234a1e
L		 3320 {
3321 register_specifier =
3322 ~register_number (i.vex.register_specifier) & 0xf;
3323 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3324 }
c0f3af97
L		 3325 else
3326 register_specifier = 0xf;
3327
33eaf5de 3328 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3329 operand. */
86fa6981
L		 3330 if (i.vec_encoding != vex_encoding_vex3
3331 && i.dir_encoding == dir_encoding_default
fa99fab2 3332 && i.operands == i.reg_operands
7f399153 3333 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3334 && i.tm.opcode_modifier.load
fa99fab2
L		 3335 && i.rex == REX_B)
3336 {
3337 unsigned int xchg = i.operands - 1;
3338 union i386_op temp_op;
3339 i386_operand_type temp_type;
3340
3341 temp_type = i.types[xchg];
3342 i.types[xchg] = i.types[0];
3343 i.types[0] = temp_type;
3344 temp_op = i.op[xchg];
3345 i.op[xchg] = i.op[0];
3346 i.op[0] = temp_op;
3347
9c2799c2 3348 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3349
3350 i.rex = REX_R;
3351 xchg = i.rm.regmem;
3352 i.rm.regmem = i.rm.reg;
3353 i.rm.reg = xchg;
3354
3355 /* Use the next insn. */
3356 i.tm = t[1];
3357 }
3358
539f890d
L		 3359 if (i.tm.opcode_modifier.vex == VEXScalar)
3360 vector_length = avxscalar;
10c17abd
JB		 3361 else if (i.tm.opcode_modifier.vex == VEX256)
3362 vector_length = 1;
539f890d 3363 else
10c17abd 3364 {
c7213af9 3365 int op;
10c17abd 3366
c7213af9
L		 3367 /* Determine vector length from the last multi-length vector
3368 operand. */
10c17abd 3369 vector_length = 0;
c7213af9 3370 for (op = t->operands - 1; op >= 0; op--)
10c17abd
JB		 3371 if (t->operand_types[op].bitfield.xmmword
3372 && t->operand_types[op].bitfield.ymmword
3373 && i.types[op].bitfield.ymmword)
3374 {
3375 vector_length = 1;
3376 break;
3377 }
3378 }
c0f3af97
L		 3379
3380 switch ((i.tm.base_opcode >> 8) & 0xff)
3381 {
3382 case 0:
3383 implied_prefix = 0;
3384 break;
3385 case DATA_PREFIX_OPCODE:
3386 implied_prefix = 1;
3387 break;
3388 case REPE_PREFIX_OPCODE:
3389 implied_prefix = 2;
3390 break;
3391 case REPNE_PREFIX_OPCODE:
3392 implied_prefix = 3;
3393 break;
3394 default:
3395 abort ();
3396 }
3397
3398 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3399 if (i.vec_encoding != vex_encoding_vex3
3400 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3401 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3402 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3403 {
3404 /* 2-byte VEX prefix. */
3405 unsigned int r;
3406
3407 i.vex.length = 2;
3408 i.vex.bytes[0] = 0xc5;
3409
3410 /* Check the REX.R bit. */
3411 r = (i.rex & REX_R) ? 0 : 1;
3412 i.vex.bytes[1] = (r << 7
3413 | register_specifier << 3
3414 | vector_length << 2
3415 | implied_prefix);
3416 }
3417 else
3418 {
3419 /* 3-byte VEX prefix. */
3420 unsigned int m, w;
3421
f88c9eb0 3422 i.vex.length = 3;
f88c9eb0 3423
7f399153 3424 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3425 {
7f399153
L		 3426 case VEX0F:
3427 m = 0x1;
80de6e00 3428 i.vex.bytes[0] = 0xc4;
7f399153
L		 3429 break;
3430 case VEX0F38:
3431 m = 0x2;
80de6e00 3432 i.vex.bytes[0] = 0xc4;
7f399153
L		 3433 break;
3434 case VEX0F3A:
3435 m = 0x3;
80de6e00 3436 i.vex.bytes[0] = 0xc4;
7f399153
L		 3437 break;
3438 case XOP08:
5dd85c99
SP		 3439 m = 0x8;
3440 i.vex.bytes[0] = 0x8f;
7f399153
L		 3441 break;
3442 case XOP09:
f88c9eb0
SP		 3443 m = 0x9;
3444 i.vex.bytes[0] = 0x8f;
7f399153
L		 3445 break;
3446 case XOP0A:
f88c9eb0
SP		 3447 m = 0xa;
3448 i.vex.bytes[0] = 0x8f;
7f399153
L		 3449 break;
3450 default:
3451 abort ();
f88c9eb0 3452 }
c0f3af97 3453
c0f3af97
L		 3454 /* The high 3 bits of the second VEX byte are 1's compliment
3455 of RXB bits from REX. */
3456 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3457
3458 /* Check the REX.W bit. */
3459 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3460 if (i.tm.opcode_modifier.vexw == VEXW1)
3461 w = 1;
c0f3af97
L		 3462
3463 i.vex.bytes[2] = (w << 7
3464 | register_specifier << 3
3465 | vector_length << 2
3466 | implied_prefix);
3467 }
3468}
3469
e771e7c9
JB		 3470static INLINE bfd_boolean
3471is_evex_encoding (const insn_template *t)
3472{
7091c612 3473 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
e771e7c9
JB		 3474 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3475 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3476}
3477
43234a1e
L		 3478/* Build the EVEX prefix. */
3479
3480static void
3481build_evex_prefix (void)
3482{
3483 unsigned int register_specifier;
3484 unsigned int implied_prefix;
3485 unsigned int m, w;
3486 rex_byte vrex_used = 0;
3487
3488 /* Check register specifier. */
3489 if (i.vex.register_specifier)
3490 {
3491 gas_assert ((i.vrex & REX_X) == 0);
3492
3493 register_specifier = i.vex.register_specifier->reg_num;
3494 if ((i.vex.register_specifier->reg_flags & RegRex))
3495 register_specifier += 8;
3496 /* The upper 16 registers are encoded in the fourth byte of the
3497 EVEX prefix. */
3498 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3499 i.vex.bytes[3] = 0x8;
3500 register_specifier = ~register_specifier & 0xf;
3501 }
3502 else
3503 {
3504 register_specifier = 0xf;
3505
3506 /* Encode upper 16 vector index register in the fourth byte of
3507 the EVEX prefix. */
3508 if (!(i.vrex & REX_X))
3509 i.vex.bytes[3] = 0x8;
3510 else
3511 vrex_used |= REX_X;
3512 }
3513
3514 switch ((i.tm.base_opcode >> 8) & 0xff)
3515 {
3516 case 0:
3517 implied_prefix = 0;
3518 break;
3519 case DATA_PREFIX_OPCODE:
3520 implied_prefix = 1;
3521 break;
3522 case REPE_PREFIX_OPCODE:
3523 implied_prefix = 2;
3524 break;
3525 case REPNE_PREFIX_OPCODE:
3526 implied_prefix = 3;
3527 break;
3528 default:
3529 abort ();
3530 }
3531
3532 /* 4 byte EVEX prefix. */
3533 i.vex.length = 4;
3534 i.vex.bytes[0] = 0x62;
3535
3536 /* mmmm bits. */
3537 switch (i.tm.opcode_modifier.vexopcode)
3538 {
3539 case VEX0F:
3540 m = 1;
3541 break;
3542 case VEX0F38:
3543 m = 2;
3544 break;
3545 case VEX0F3A:
3546 m = 3;
3547 break;
3548 default:
3549 abort ();
3550 break;
3551 }
3552
3553 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3554 bits from REX. */
3555 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3556
3557 /* The fifth bit of the second EVEX byte is 1's compliment of the
3558 REX_R bit in VREX. */
3559 if (!(i.vrex & REX_R))
3560 i.vex.bytes[1] |= 0x10;
3561 else
3562 vrex_used |= REX_R;
3563
3564 if ((i.reg_operands + i.imm_operands) == i.operands)
3565 {
3566 /* When all operands are registers, the REX_X bit in REX is not
3567 used. We reuse it to encode the upper 16 registers, which is
3568 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3569 as 1's compliment. */
3570 if ((i.vrex & REX_B))
3571 {
3572 vrex_used |= REX_B;
3573 i.vex.bytes[1] &= ~0x40;
3574 }
3575 }
3576
3577 /* EVEX instructions shouldn't need the REX prefix. */
3578 i.vrex &= ~vrex_used;
3579 gas_assert (i.vrex == 0);
3580
3581 /* Check the REX.W bit. */
3582 w = (i.rex & REX_W) ? 1 : 0;
3583 if (i.tm.opcode_modifier.vexw)
3584 {
3585 if (i.tm.opcode_modifier.vexw == VEXW1)
3586 w = 1;
3587 }
3588 /* If w is not set it means we are dealing with WIG instruction. */
3589 else if (!w)
3590 {
3591 if (evexwig == evexw1)
3592 w = 1;
3593 }
3594
3595 /* Encode the U bit. */
3596 implied_prefix |= 0x4;
3597
3598 /* The third byte of the EVEX prefix. */
3599 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3600
3601 /* The fourth byte of the EVEX prefix. */
3602 /* The zeroing-masking bit. */
3603 if (i.mask && i.mask->zeroing)
3604 i.vex.bytes[3] |= 0x80;
3605
3606 /* Don't always set the broadcast bit if there is no RC. */
3607 if (!i.rounding)
3608 {
3609 /* Encode the vector length. */
3610 unsigned int vec_length;
3611
e771e7c9
JB		 3612 if (!i.tm.opcode_modifier.evex
3613 || i.tm.opcode_modifier.evex == EVEXDYN)
3614 {
c7213af9 3615 int op;
e771e7c9 3616
c7213af9
L		 3617 /* Determine vector length from the last multi-length vector
3618 operand. */
e771e7c9 3619 vec_length = 0;
c7213af9 3620 for (op = i.operands - 1; op >= 0; op--)
e771e7c9
JB		 3621 if (i.tm.operand_types[op].bitfield.xmmword
3622 + i.tm.operand_types[op].bitfield.ymmword
3623 + i.tm.operand_types[op].bitfield.zmmword > 1)
3624 {
3625 if (i.types[op].bitfield.zmmword)
c7213af9
L		 3626 {
3627 i.tm.opcode_modifier.evex = EVEX512;
3628 break;
3629 }
e771e7c9 3630 else if (i.types[op].bitfield.ymmword)
c7213af9
L		 3631 {
3632 i.tm.opcode_modifier.evex = EVEX256;
3633 break;
3634 }
e771e7c9 3635 else if (i.types[op].bitfield.xmmword)
c7213af9
L		 3636 {
3637 i.tm.opcode_modifier.evex = EVEX128;
3638 break;
3639 }
625cbd7a
JB		 3640 else if (i.broadcast && (int) op == i.broadcast->operand)
3641 {
3642 switch ((i.tm.operand_types[op].bitfield.dword ? 4 : 8)
3643 * i.broadcast->type)
3644 {
3645 case 64:
3646 i.tm.opcode_modifier.evex = EVEX512;
3647 break;
3648 case 32:
3649 i.tm.opcode_modifier.evex = EVEX256;
3650 break;
3651 case 16:
3652 i.tm.opcode_modifier.evex = EVEX128;
3653 break;
3654 default:
c7213af9 3655 abort ();
625cbd7a 3656 }
c7213af9 3657 break;
625cbd7a 3658 }
e771e7c9 3659 }
c7213af9
L		 3660
3661 if (op < 0)
3662 abort ();
e771e7c9
JB		 3663 }
3664
43234a1e
L		 3665 switch (i.tm.opcode_modifier.evex)
3666 {
3667 case EVEXLIG: /* LL' is ignored */
3668 vec_length = evexlig << 5;
3669 break;
3670 case EVEX128:
3671 vec_length = 0 << 5;
3672 break;
3673 case EVEX256:
3674 vec_length = 1 << 5;
3675 break;
3676 case EVEX512:
3677 vec_length = 2 << 5;
3678 break;
3679 default:
3680 abort ();
3681 break;
3682 }
3683 i.vex.bytes[3] |= vec_length;
3684 /* Encode the broadcast bit. */
3685 if (i.broadcast)
3686 i.vex.bytes[3] |= 0x10;
3687 }
3688 else
3689 {
3690 if (i.rounding->type != saeonly)
3691 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3692 else
d3d3c6db 3693 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3694 }
3695
3696 if (i.mask && i.mask->mask)
3697 i.vex.bytes[3] |= i.mask->mask->reg_num;
3698}
3699
65da13b5
L		 3700static void
3701process_immext (void)
3702{
3703 expressionS *exp;
3704
4c692bc7
JB		 3705 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3706 && i.operands > 0)
65da13b5 3707 {
4c692bc7
JB		 3708 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3709 with an opcode suffix which is coded in the same place as an
3710 8-bit immediate field would be.
3711 Here we check those operands and remove them afterwards. */
65da13b5
L		 3712 unsigned int x;
3713
3714 for (x = 0; x < i.operands; x++)
4c692bc7 3715 if (register_number (i.op[x].regs) != x)
65da13b5 3716 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3717 register_prefix, i.op[x].regs->reg_name, x + 1,
3718 i.tm.name);
3719
3720 i.operands = 0;
65da13b5
L		 3721 }
3722
9916071f
AP		 3723 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3724 {
3725 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3726 suffix which is coded in the same place as an 8-bit immediate
3727 field would be.
3728 Here we check those operands and remove them afterwards. */
3729 unsigned int x;
3730
3731 if (i.operands != 3)
3732 abort();
3733
3734 for (x = 0; x < 2; x++)
3735 if (register_number (i.op[x].regs) != x)
3736 goto bad_register_operand;
3737
3738 /* Check for third operand for mwaitx/monitorx insn. */
3739 if (register_number (i.op[x].regs)
3740 != (x + (i.tm.extension_opcode == 0xfb)))
3741 {
3742bad_register_operand:
3743 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3744 register_prefix, i.op[x].regs->reg_name, x+1,
3745 i.tm.name);
3746 }
3747
3748 i.operands = 0;
3749 }
3750
c0f3af97 3751 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3752 which is coded in the same place as an 8-bit immediate field
3753 would be. Here we fake an 8-bit immediate operand from the
3754 opcode suffix stored in tm.extension_opcode.
3755
c1e679ec 3756 AVX instructions also use this encoding, for some of
c0f3af97 3757 3 argument instructions. */
65da13b5 3758
43234a1e 3759 gas_assert (i.imm_operands <= 1
7ab9ffdd 3760 && (i.operands <= 2
43234a1e 3761 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3762 || i.tm.opcode_modifier.vexopcode
3763 || is_evex_encoding (&i.tm))
7ab9ffdd 3764 && i.operands <= 4)));
65da13b5
L		 3765
3766 exp = &im_expressions[i.imm_operands++];
3767 i.op[i.operands].imms = exp;
3768 i.types[i.operands] = imm8;
3769 i.operands++;
3770 exp->X_op = O_constant;
3771 exp->X_add_number = i.tm.extension_opcode;
3772 i.tm.extension_opcode = None;
3773}
3774
42164a71
L		 3775
3776static int
3777check_hle (void)
3778{
3779 switch (i.tm.opcode_modifier.hleprefixok)
3780 {
3781 default:
3782 abort ();
82c2def5 3783 case HLEPrefixNone:
165de32a
L		 3784 as_bad (_("invalid instruction `%s' after `%s'"),
3785 i.tm.name, i.hle_prefix);
42164a71 3786 return 0;
82c2def5 3787 case HLEPrefixLock:
42164a71
L		 3788 if (i.prefix[LOCK_PREFIX])
3789 return 1;
165de32a 3790 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3791 return 0;
82c2def5 3792 case HLEPrefixAny:
42164a71 3793 return 1;
82c2def5 3794 case HLEPrefixRelease:
42164a71
L		 3795 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3796 {
3797 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3798 i.tm.name);
3799 return 0;
3800 }
3801 if (i.mem_operands == 0
3802 || !operand_type_check (i.types[i.operands - 1], anymem))
3803 {
3804 as_bad (_("memory destination needed for instruction `%s'"
3805 " after `xrelease'"), i.tm.name);
3806 return 0;
3807 }
3808 return 1;
3809 }
3810}
3811
b6f8c7c4
L		 3812/* Try the shortest encoding by shortening operand size. */
3813
3814static void
3815optimize_encoding (void)
3816{
3817 int j;
3818
3819 if (optimize_for_space
3820 && i.reg_operands == 1
3821 && i.imm_operands == 1
3822 && !i.types[1].bitfield.byte
3823 && i.op[0].imms->X_op == O_constant
3824 && fits_in_imm7 (i.op[0].imms->X_add_number)
3825 && ((i.tm.base_opcode == 0xa8
3826 && i.tm.extension_opcode == None)
3827 || (i.tm.base_opcode == 0xf6
3828 && i.tm.extension_opcode == 0x0)))
3829 {
3830 /* Optimize: -Os:
3831 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3832 */
3833 unsigned int base_regnum = i.op[1].regs->reg_num;
3834 if (flag_code == CODE_64BIT || base_regnum < 4)
3835 {
3836 i.types[1].bitfield.byte = 1;
3837 /* Ignore the suffix. */
3838 i.suffix = 0;
3839 if (base_regnum >= 4
3840 && !(i.op[1].regs->reg_flags & RegRex))
3841 {
3842 /* Handle SP, BP, SI and DI registers. */
3843 if (i.types[1].bitfield.word)
3844 j = 16;
3845 else if (i.types[1].bitfield.dword)
3846 j = 32;
3847 else
3848 j = 48;
3849 i.op[1].regs -= j;
3850 }
3851 }
3852 }
3853 else if (flag_code == CODE_64BIT
d3d50934
L		 3854 && ((i.types[1].bitfield.qword
3855 && i.reg_operands == 1
b6f8c7c4
L		 3856 && i.imm_operands == 1
3857 && i.op[0].imms->X_op == O_constant
3858 && ((i.tm.base_opcode == 0xb0
3859 && i.tm.extension_opcode == None
3860 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3861 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3862 && (((i.tm.base_opcode == 0x24
3863 || i.tm.base_opcode == 0xa8)
3864 && i.tm.extension_opcode == None)
3865 || (i.tm.base_opcode == 0x80
3866 && i.tm.extension_opcode == 0x4)
3867 || ((i.tm.base_opcode == 0xf6
3868 || i.tm.base_opcode == 0xc6)
3869 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3870 || (i.types[0].bitfield.qword
3871 && ((i.reg_operands == 2
3872 && i.op[0].regs == i.op[1].regs
3873 && ((i.tm.base_opcode == 0x30
3874 || i.tm.base_opcode == 0x28)
3875 && i.tm.extension_opcode == None))
3876 || (i.reg_operands == 1
3877 && i.operands == 1
3878 && i.tm.base_opcode == 0x30
3879 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3880 {
3881 /* Optimize: -O:
3882 andq $imm31, %r64 -> andl $imm31, %r32
3883 testq $imm31, %r64 -> testl $imm31, %r32
3884 xorq %r64, %r64 -> xorl %r32, %r32
3885 subq %r64, %r64 -> subl %r32, %r32
3886 movq $imm31, %r64 -> movl $imm31, %r32
3887 movq $imm32, %r64 -> movl $imm32, %r32
3888 */
3889 i.tm.opcode_modifier.norex64 = 1;
3890 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3891 {
3892 /* Handle
3893 movq $imm31, %r64 -> movl $imm31, %r32
3894 movq $imm32, %r64 -> movl $imm32, %r32
3895 */
3896 i.tm.operand_types[0].bitfield.imm32 = 1;
3897 i.tm.operand_types[0].bitfield.imm32s = 0;
3898 i.tm.operand_types[0].bitfield.imm64 = 0;
3899 i.types[0].bitfield.imm32 = 1;
3900 i.types[0].bitfield.imm32s = 0;
3901 i.types[0].bitfield.imm64 = 0;
3902 i.types[1].bitfield.dword = 1;
3903 i.types[1].bitfield.qword = 0;
3904 if (i.tm.base_opcode == 0xc6)
3905 {
3906 /* Handle
3907 movq $imm31, %r64 -> movl $imm31, %r32
3908 */
3909 i.tm.base_opcode = 0xb0;
3910 i.tm.extension_opcode = None;
3911 i.tm.opcode_modifier.shortform = 1;
3912 i.tm.opcode_modifier.modrm = 0;
3913 }
3914 }
3915 }
3916 else if (optimize > 1
3917 && i.reg_operands == 3
3918 && i.op[0].regs == i.op[1].regs
3919 && !i.types[2].bitfield.xmmword
3920 && (i.tm.opcode_modifier.vex
7a69eac3 3921 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 3922 && !i.rounding
e771e7c9 3923 && is_evex_encoding (&i.tm)
80c34c38
L		 3924 && (i.vec_encoding != vex_encoding_evex
3925 || i.tm.cpu_flags.bitfield.cpuavx512vl
7091c612
JB		 3926 || (i.tm.operand_types[2].bitfield.zmmword
3927 && i.types[2].bitfield.ymmword)
0089dace 3928 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3929 && ((i.tm.base_opcode == 0x55
3930 || i.tm.base_opcode == 0x6655
3931 || i.tm.base_opcode == 0x66df
3932 || i.tm.base_opcode == 0x57
3933 || i.tm.base_opcode == 0x6657
8305403a
L		 3934 || i.tm.base_opcode == 0x66ef
3935 || i.tm.base_opcode == 0x66f8
3936 || i.tm.base_opcode == 0x66f9
3937 || i.tm.base_opcode == 0x66fa
3938 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3939 && i.tm.extension_opcode == None))
3940 {
3941 /* Optimize: -O2:
8305403a
L		 3942 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3943 vpsubq and vpsubw:
b6f8c7c4
L		 3944 EVEX VOP %zmmM, %zmmM, %zmmN
3945 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3946 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3947 EVEX VOP %ymmM, %ymmM, %ymmN
3948 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3949 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3950 VEX VOP %ymmM, %ymmM, %ymmN
3951 -> VEX VOP %xmmM, %xmmM, %xmmN
3952 VOP, one of vpandn and vpxor:
3953 VEX VOP %ymmM, %ymmM, %ymmN
3954 -> VEX VOP %xmmM, %xmmM, %xmmN
3955 VOP, one of vpandnd and vpandnq:
3956 EVEX VOP %zmmM, %zmmM, %zmmN
3957 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3958 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3959 EVEX VOP %ymmM, %ymmM, %ymmN
3960 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3961 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3962 VOP, one of vpxord and vpxorq:
3963 EVEX VOP %zmmM, %zmmM, %zmmN
3964 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3965 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3966 EVEX VOP %ymmM, %ymmM, %ymmN
3967 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3968 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3969 */
e771e7c9 3970 if (is_evex_encoding (&i.tm))
b6f8c7c4 3971 {
0089dace 3972 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3973 i.tm.opcode_modifier.evex = EVEX128;
3974 else
3975 {
3976 i.tm.opcode_modifier.vex = VEX128;
3977 i.tm.opcode_modifier.vexw = VEXW0;
3978 i.tm.opcode_modifier.evex = 0;
3979 }
3980 }
3981 else
3982 i.tm.opcode_modifier.vex = VEX128;
3983
3984 if (i.tm.opcode_modifier.vex)
3985 for (j = 0; j < 3; j++)
3986 {
3987 i.types[j].bitfield.xmmword = 1;
3988 i.types[j].bitfield.ymmword = 0;
3989 }
3990 }
3991}
3992
252b5132
RH		 3993/* This is the guts of the machine-dependent assembler. LINE points to a
3994 machine dependent instruction. This function is supposed to emit
3995 the frags/bytes it assembles to. */
3996
3997void
65da13b5 3998md_assemble (char *line)
252b5132 3999{
40fb9820 4000 unsigned int j;
83b16ac6 4001 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 4002 const insn_template *t;
252b5132 4003
47926f60 4004 /* Initialize globals. */
252b5132
RH		 4005 memset (&i, '\0', sizeof (i));
4006 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 4007 i.reloc[j] = NO_RELOC;
252b5132
RH		 4008 memset (disp_expressions, '\0', sizeof (disp_expressions));
4009 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 4010 save_stack_p = save_stack;
252b5132
RH		 4011
4012 /* First parse an instruction mnemonic & call i386_operand for the operands.
4013 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 4014 start of a (possibly prefixed) mnemonic. */
252b5132 4015
29b0f896
AM		 4016 line = parse_insn (line, mnemonic);
4017 if (line == NULL)
4018 return;
83b16ac6 4019 mnem_suffix = i.suffix;
252b5132 4020
29b0f896 4021 line = parse_operands (line, mnemonic);
ee86248c 4022 this_operand = -1;
8325cc63
JB		 4023 xfree (i.memop1_string);
4024 i.memop1_string = NULL;
29b0f896
AM		 4025 if (line == NULL)
4026 return;
252b5132 4027
29b0f896
AM		 4028 /* Now we've parsed the mnemonic into a set of templates, and have the
4029 operands at hand. */
4030
4031 /* All intel opcodes have reversed operands except for "bound" and
4032 "enter". We also don't reverse intersegment "jmp" and "call"
4033 instructions with 2 immediate operands so that the immediate segment
050dfa73 4034 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 4035 if (intel_syntax
4036 && i.operands > 1
29b0f896 4037 && (strcmp (mnemonic, "bound") != 0)
30123838 4038 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 4039 && !(operand_type_check (i.types[0], imm)
4040 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 4041 swap_operands ();
4042
ec56d5c0
JB		 4043 /* The order of the immediates should be reversed
4044 for 2 immediates extrq and insertq instructions */
4045 if (i.imm_operands == 2
4046 && (strcmp (mnemonic, "extrq") == 0
4047 || strcmp (mnemonic, "insertq") == 0))
4048 swap_2_operands (0, 1);
4049
29b0f896
AM		 4050 if (i.imm_operands)
4051 optimize_imm ();
4052
b300c311
L		 4053 /* Don't optimize displacement for movabs since it only takes 64bit
4054 displacement. */
4055 if (i.disp_operands
a501d77e 4056 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4057 && (flag_code != CODE_64BIT
4058 || strcmp (mnemonic, "movabs") != 0))
4059 optimize_disp ();
29b0f896
AM		 4060
4061 /* Next, we find a template that matches the given insn,
4062 making sure the overlap of the given operands types is consistent
4063 with the template operand types. */
252b5132 4064
83b16ac6 4065 if (!(t = match_template (mnem_suffix)))
29b0f896 4066 return;
252b5132 4067
7bab8ab5 4068 if (sse_check != check_none
81f8a913 4069 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4070 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4071 && (i.tm.cpu_flags.bitfield.cpusse
4072 || i.tm.cpu_flags.bitfield.cpusse2
4073 || i.tm.cpu_flags.bitfield.cpusse3
4074 || i.tm.cpu_flags.bitfield.cpussse3
4075 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4076 || i.tm.cpu_flags.bitfield.cpusse4_2
4077 || i.tm.cpu_flags.bitfield.cpupclmul
4078 || i.tm.cpu_flags.bitfield.cpuaes
4079 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4080 {
7bab8ab5 4081 (sse_check == check_warning
daf50ae7
L		 4082 ? as_warn
4083 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4084 }
4085
321fd21e
L		 4086 /* Zap movzx and movsx suffix. The suffix has been set from
4087 "word ptr" or "byte ptr" on the source operand in Intel syntax
4088 or extracted from mnemonic in AT&T syntax. But we'll use
4089 the destination register to choose the suffix for encoding. */
4090 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4091 {
321fd21e
L		 4092 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4093 there is no suffix, the default will be byte extension. */
4094 if (i.reg_operands != 2
4095 && !i.suffix
7ab9ffdd 4096 && intel_syntax)
321fd21e
L		 4097 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4098
4099 i.suffix = 0;
cd61ebfe 4100 }
24eab124 4101
40fb9820 4102 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4103 if (!add_prefix (FWAIT_OPCODE))
4104 return;
252b5132 4105
d5de92cf
L		 4106 /* Check if REP prefix is OK. */
4107 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4108 {
4109 as_bad (_("invalid instruction `%s' after `%s'"),
4110 i.tm.name, i.rep_prefix);
4111 return;
4112 }
4113
c1ba0266
L		 4114 /* Check for lock without a lockable instruction. Destination operand
4115 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4116 if (i.prefix[LOCK_PREFIX]
4117 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4118 || i.mem_operands == 0
4119 || (i.tm.base_opcode != 0x86
4120 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4121 {
4122 as_bad (_("expecting lockable instruction after `lock'"));
4123 return;
4124 }
4125
42164a71 4126 /* Check if HLE prefix is OK. */
165de32a 4127 if (i.hle_prefix && !check_hle ())
42164a71
L		 4128 return;
4129
7e8b059b
L		 4130 /* Check BND prefix. */
4131 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4132 as_bad (_("expecting valid branch instruction after `bnd'"));
4133
04ef582a 4134 /* Check NOTRACK prefix. */
9fef80d6
L		 4135 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4136 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4137
327e8c42
JB		 4138 if (i.tm.cpu_flags.bitfield.cpumpx)
4139 {
4140 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4141 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4142 else if (flag_code != CODE_16BIT
4143 ? i.prefix[ADDR_PREFIX]
4144 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4145 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4146 }
7e8b059b
L		 4147
4148 /* Insert BND prefix. */
76d3a78a
JB		 4149 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4150 {
4151 if (!i.prefix[BND_PREFIX])
4152 add_prefix (BND_PREFIX_OPCODE);
4153 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4154 {
4155 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4156 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4157 }
4158 }
7e8b059b 4159
29b0f896 4160 /* Check string instruction segment overrides. */
40fb9820 4161 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4162 {
4163 if (!check_string ())
5dd0794d 4164 return;
fc0763e6 4165 i.disp_operands = 0;
29b0f896 4166 }
5dd0794d 4167
b6f8c7c4
L		 4168 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4169 optimize_encoding ();
4170
29b0f896
AM		 4171 if (!process_suffix ())
4172 return;
e413e4e9 4173
bc0844ae
L		 4174 /* Update operand types. */
4175 for (j = 0; j < i.operands; j++)
4176 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4177
29b0f896
AM		 4178 /* Make still unresolved immediate matches conform to size of immediate
4179 given in i.suffix. */
4180 if (!finalize_imm ())
4181 return;
252b5132 4182
40fb9820 4183 if (i.types[0].bitfield.imm1)
29b0f896 4184 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4185
9afe6eb8
L		 4186 /* We only need to check those implicit registers for instructions
4187 with 3 operands or less. */
4188 if (i.operands <= 3)
4189 for (j = 0; j < i.operands; j++)
4190 if (i.types[j].bitfield.inoutportreg
4191 || i.types[j].bitfield.shiftcount
1b54b8d7 4192 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4193 i.reg_operands--;
40fb9820 4194
c0f3af97
L		 4195 /* ImmExt should be processed after SSE2AVX. */
4196 if (!i.tm.opcode_modifier.sse2avx
4197 && i.tm.opcode_modifier.immext)
65da13b5 4198 process_immext ();
252b5132 4199
29b0f896
AM		 4200 /* For insns with operands there are more diddles to do to the opcode. */
4201 if (i.operands)
4202 {
4203 if (!process_operands ())
4204 return;
4205 }
40fb9820 4206 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4207 {
4208 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4209 as_warn (_("translating to `%sp'"), i.tm.name);
4210 }
252b5132 4211
e771e7c9
JB		 4212 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4213 || is_evex_encoding (&i.tm))
9e5e5283
L		 4214 {
4215 if (flag_code == CODE_16BIT)
4216 {
4217 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4218 i.tm.name);
4219 return;
4220 }
c0f3af97 4221
9e5e5283
L		 4222 if (i.tm.opcode_modifier.vex)
4223 build_vex_prefix (t);
4224 else
4225 build_evex_prefix ();
4226 }
43234a1e 4227
5dd85c99
SP		 4228 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4229 instructions may define INT_OPCODE as well, so avoid this corner
4230 case for those instructions that use MODRM. */
4231 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4232 && !i.tm.opcode_modifier.modrm
4233 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4234 {
4235 i.tm.base_opcode = INT3_OPCODE;
4236 i.imm_operands = 0;
4237 }
252b5132 4238
40fb9820
L		 4239 if ((i.tm.opcode_modifier.jump
4240 || i.tm.opcode_modifier.jumpbyte
4241 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4242 && i.op[0].disps->X_op == O_constant)
4243 {
4244 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4245 the absolute address given by the constant. Since ix86 jumps and
4246 calls are pc relative, we need to generate a reloc. */
4247 i.op[0].disps->X_add_symbol = &abs_symbol;
4248 i.op[0].disps->X_op = O_symbol;
4249 }
252b5132 4250
40fb9820 4251 if (i.tm.opcode_modifier.rex64)
161a04f6 4252 i.rex |= REX_W;
252b5132 4253
29b0f896
AM		 4254 /* For 8 bit registers we need an empty rex prefix. Also if the
4255 instruction already has a prefix, we need to convert old
4256 registers to new ones. */
773f551c 4257
dc821c5f 4258 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4259 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4260 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4261 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4262 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4263 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4264 && i.rex != 0))
4265 {
4266 int x;
726c5dcd 4267
29b0f896
AM		 4268 i.rex |= REX_OPCODE;
4269 for (x = 0; x < 2; x++)
4270 {
4271 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4272 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4273 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4274 {
29b0f896
AM		 4275 /* In case it is "hi" register, give up. */
4276 if (i.op[x].regs->reg_num > 3)
a540244d 4277 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4278 "instruction requiring REX prefix."),
a540244d 4279 register_prefix, i.op[x].regs->reg_name);
773f551c 4280
29b0f896
AM		 4281 /* Otherwise it is equivalent to the extended register.
4282 Since the encoding doesn't change this is merely
4283 cosmetic cleanup for debug output. */
4284
4285 i.op[x].regs = i.op[x].regs + 8;
773f551c 4286 }
29b0f896
AM		 4287 }
4288 }
773f551c 4289
6b6b6807
L		 4290 if (i.rex == 0 && i.rex_encoding)
4291 {
4292 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4293 that uses legacy register. If it is "hi" register, don't add
4294 the REX_OPCODE byte. */
4295 int x;
4296 for (x = 0; x < 2; x++)
4297 if (i.types[x].bitfield.reg
4298 && i.types[x].bitfield.byte
4299 && (i.op[x].regs->reg_flags & RegRex64) == 0
4300 && i.op[x].regs->reg_num > 3)
4301 {
4302 i.rex_encoding = FALSE;
4303 break;
4304 }
4305
4306 if (i.rex_encoding)
4307 i.rex = REX_OPCODE;
4308 }
4309
7ab9ffdd 4310 if (i.rex != 0)
29b0f896
AM		 4311 add_prefix (REX_OPCODE | i.rex);
4312
4313 /* We are ready to output the insn. */
4314 output_insn ();
4315}
4316
4317static char *
e3bb37b5 4318parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4319{
4320 char *l = line;
4321 char *token_start = l;
4322 char *mnem_p;
5c6af06e 4323 int supported;
d3ce72d0 4324 const insn_template *t;
b6169b20 4325 char *dot_p = NULL;
29b0f896 4326
29b0f896
AM		 4327 while (1)
4328 {
4329 mnem_p = mnemonic;
4330 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4331 {
b6169b20
L		 4332 if (*mnem_p == '.')
4333 dot_p = mnem_p;
29b0f896
AM		 4334 mnem_p++;
4335 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4336 {
29b0f896
AM		 4337 as_bad (_("no such instruction: `%s'"), token_start);
4338 return NULL;
4339 }
4340 l++;
4341 }
4342 if (!is_space_char (*l)
4343 && *l != END_OF_INSN
e44823cf
JB		 4344 && (intel_syntax
4345 || (*l != PREFIX_SEPARATOR
4346 && *l != ',')))
29b0f896
AM		 4347 {
4348 as_bad (_("invalid character %s in mnemonic"),
4349 output_invalid (*l));
4350 return NULL;
4351 }
4352 if (token_start == l)
4353 {
e44823cf 4354 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4355 as_bad (_("expecting prefix; got nothing"));
4356 else
4357 as_bad (_("expecting mnemonic; got nothing"));
4358 return NULL;
4359 }
45288df1 4360
29b0f896 4361 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4362 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4363
29b0f896
AM		 4364 if (*l != END_OF_INSN
4365 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4366 && current_templates
40fb9820 4367 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4368 {
c6fb90c8 4369 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4370 {
4371 as_bad ((flag_code != CODE_64BIT
4372 ? _("`%s' is only supported in 64-bit mode")
4373 : _("`%s' is not supported in 64-bit mode")),
4374 current_templates->start->name);
4375 return NULL;
4376 }
29b0f896
AM		 4377 /* If we are in 16-bit mode, do not allow addr16 or data16.
4378 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4379 if ((current_templates->start->opcode_modifier.size16
4380 || current_templates->start->opcode_modifier.size32)
29b0f896 4381 && flag_code != CODE_64BIT
40fb9820 4382 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4383 ^ (flag_code == CODE_16BIT)))
4384 {
4385 as_bad (_("redundant %s prefix"),
4386 current_templates->start->name);
4387 return NULL;
45288df1 4388 }
86fa6981 4389 if (current_templates->start->opcode_length == 0)
29b0f896 4390 {
86fa6981
L		 4391 /* Handle pseudo prefixes. */
4392 switch (current_templates->start->base_opcode)
4393 {
4394 case 0x0:
4395 /* {disp8} */
4396 i.disp_encoding = disp_encoding_8bit;
4397 break;
4398 case 0x1:
4399 /* {disp32} */
4400 i.disp_encoding = disp_encoding_32bit;
4401 break;
4402 case 0x2:
4403 /* {load} */
4404 i.dir_encoding = dir_encoding_load;
4405 break;
4406 case 0x3:
4407 /* {store} */
4408 i.dir_encoding = dir_encoding_store;
4409 break;
4410 case 0x4:
4411 /* {vex2} */
4412 i.vec_encoding = vex_encoding_vex2;
4413 break;
4414 case 0x5:
4415 /* {vex3} */
4416 i.vec_encoding = vex_encoding_vex3;
4417 break;
4418 case 0x6:
4419 /* {evex} */
4420 i.vec_encoding = vex_encoding_evex;
4421 break;
6b6b6807
L		 4422 case 0x7:
4423 /* {rex} */
4424 i.rex_encoding = TRUE;
4425 break;
b6f8c7c4
L		 4426 case 0x8:
4427 /* {nooptimize} */
4428 i.no_optimize = TRUE;
4429 break;
86fa6981
L		 4430 default:
4431 abort ();
4432 }
4433 }
4434 else
4435 {
4436 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4437 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4438 {
4e9ac44a
L		 4439 case PREFIX_EXIST:
4440 return NULL;
4441 case PREFIX_DS:
d777820b 4442 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4443 i.notrack_prefix = current_templates->start->name;
4444 break;
4445 case PREFIX_REP:
4446 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4447 i.hle_prefix = current_templates->start->name;
4448 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4449 i.bnd_prefix = current_templates->start->name;
4450 else
4451 i.rep_prefix = current_templates->start->name;
4452 break;
4453 default:
4454 break;
86fa6981 4455 }
29b0f896
AM		 4456 }
4457 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4458 token_start = ++l;
4459 }
4460 else
4461 break;
4462 }
45288df1 4463
30a55f88 4464 if (!current_templates)
b6169b20 4465 {
f8a5c266
L		 4466 /* Check if we should swap operand or force 32bit displacement in
4467 encoding. */
30a55f88 4468 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4469 i.dir_encoding = dir_encoding_store;
8d63c93e 4470 else if (mnem_p - 3 == dot_p
a501d77e
L		 4471 && dot_p[1] == 'd'
4472 && dot_p[2] == '8')
4473 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4474 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4475 && dot_p[1] == 'd'
4476 && dot_p[2] == '3'
4477 && dot_p[3] == '2')
a501d77e 4478 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4479 else
4480 goto check_suffix;
4481 mnem_p = dot_p;
4482 *dot_p = '\0';
d3ce72d0 4483 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4484 }
4485
29b0f896
AM		 4486 if (!current_templates)
4487 {
b6169b20 4488check_suffix:
29b0f896
AM		 4489 /* See if we can get a match by trimming off a suffix. */
4490 switch (mnem_p[-1])
4491 {
4492 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4493 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4494 i.suffix = SHORT_MNEM_SUFFIX;
4495 else
1a0670f3 4496 /* Fall through. */
29b0f896
AM		 4497 case BYTE_MNEM_SUFFIX:
4498 case QWORD_MNEM_SUFFIX:
4499 i.suffix = mnem_p[-1];
4500 mnem_p[-1] = '\0';
d3ce72d0
NC		 4501 current_templates = (const templates *) hash_find (op_hash,
4502 mnemonic);
29b0f896
AM		 4503 break;
4504 case SHORT_MNEM_SUFFIX:
4505 case LONG_MNEM_SUFFIX:
4506 if (!intel_syntax)
4507 {
4508 i.suffix = mnem_p[-1];
4509 mnem_p[-1] = '\0';
d3ce72d0
NC		 4510 current_templates = (const templates *) hash_find (op_hash,
4511 mnemonic);
29b0f896
AM		 4512 }
4513 break;
252b5132 4514
29b0f896
AM		 4515 /* Intel Syntax. */
4516 case 'd':
4517 if (intel_syntax)
4518 {
9306ca4a 4519 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4520 i.suffix = SHORT_MNEM_SUFFIX;
4521 else
4522 i.suffix = LONG_MNEM_SUFFIX;
4523 mnem_p[-1] = '\0';
d3ce72d0
NC		 4524 current_templates = (const templates *) hash_find (op_hash,
4525 mnemonic);
29b0f896
AM		 4526 }
4527 break;
4528 }
4529 if (!current_templates)
4530 {
4531 as_bad (_("no such instruction: `%s'"), token_start);
4532 return NULL;
4533 }
4534 }
252b5132 4535
40fb9820
L		 4536 if (current_templates->start->opcode_modifier.jump
4537 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4538 {
4539 /* Check for a branch hint. We allow ",pt" and ",pn" for
4540 predict taken and predict not taken respectively.
4541 I'm not sure that branch hints actually do anything on loop
4542 and jcxz insns (JumpByte) for current Pentium4 chips. They
4543 may work in the future and it doesn't hurt to accept them
4544 now. */
4545 if (l[0] == ',' && l[1] == 'p')
4546 {
4547 if (l[2] == 't')
4548 {
4549 if (!add_prefix (DS_PREFIX_OPCODE))
4550 return NULL;
4551 l += 3;
4552 }
4553 else if (l[2] == 'n')
4554 {
4555 if (!add_prefix (CS_PREFIX_OPCODE))
4556 return NULL;
4557 l += 3;
4558 }
4559 }
4560 }
4561 /* Any other comma loses. */
4562 if (*l == ',')
4563 {
4564 as_bad (_("invalid character %s in mnemonic"),
4565 output_invalid (*l));
4566 return NULL;
4567 }
252b5132 4568
29b0f896 4569 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4570 supported = 0;
4571 for (t = current_templates->start; t < current_templates->end; ++t)
4572 {
c0f3af97
L		 4573 supported |= cpu_flags_match (t);
4574 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4575 {
4576 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4577 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4578
548d0ee6
JB		 4579 return l;
4580 }
29b0f896 4581 }
3629bb00 4582
548d0ee6
JB		 4583 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4584 as_bad (flag_code == CODE_64BIT
4585 ? _("`%s' is not supported in 64-bit mode")
4586 : _("`%s' is only supported in 64-bit mode"),
4587 current_templates->start->name);
4588 else
4589 as_bad (_("`%s' is not supported on `%s%s'"),
4590 current_templates->start->name,
4591 cpu_arch_name ? cpu_arch_name : default_arch,
4592 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4593
548d0ee6 4594 return NULL;
29b0f896 4595}
252b5132 4596
29b0f896 4597static char *
e3bb37b5 4598parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4599{
4600 char *token_start;
3138f287 4601
29b0f896
AM		 4602 /* 1 if operand is pending after ','. */
4603 unsigned int expecting_operand = 0;
252b5132 4604
29b0f896
AM		 4605 /* Non-zero if operand parens not balanced. */
4606 unsigned int paren_not_balanced;
4607
4608 while (*l != END_OF_INSN)
4609 {
4610 /* Skip optional white space before operand. */
4611 if (is_space_char (*l))
4612 ++l;
d02603dc 4613 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4614 {
4615 as_bad (_("invalid character %s before operand %d"),
4616 output_invalid (*l),
4617 i.operands + 1);
4618 return NULL;
4619 }
d02603dc 4620 token_start = l; /* After white space. */
29b0f896
AM		 4621 paren_not_balanced = 0;
4622 while (paren_not_balanced || *l != ',')
4623 {
4624 if (*l == END_OF_INSN)
4625 {
4626 if (paren_not_balanced)
4627 {
4628 if (!intel_syntax)
4629 as_bad (_("unbalanced parenthesis in operand %d."),
4630 i.operands + 1);
4631 else
4632 as_bad (_("unbalanced brackets in operand %d."),
4633 i.operands + 1);
4634 return NULL;
4635 }
4636 else
4637 break; /* we are done */
4638 }
d02603dc 4639 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4640 {
4641 as_bad (_("invalid character %s in operand %d"),
4642 output_invalid (*l),
4643 i.operands + 1);
4644 return NULL;
4645 }
4646 if (!intel_syntax)
4647 {
4648 if (*l == '(')
4649 ++paren_not_balanced;
4650 if (*l == ')')
4651 --paren_not_balanced;
4652 }
4653 else
4654 {
4655 if (*l == '[')
4656 ++paren_not_balanced;
4657 if (*l == ']')
4658 --paren_not_balanced;
4659 }
4660 l++;
4661 }
4662 if (l != token_start)
4663 { /* Yes, we've read in another operand. */
4664 unsigned int operand_ok;
4665 this_operand = i.operands++;
4666 if (i.operands > MAX_OPERANDS)
4667 {
4668 as_bad (_("spurious operands; (%d operands/instruction max)"),
4669 MAX_OPERANDS);
4670 return NULL;
4671 }
9d46ce34 4672 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4673 /* Now parse operand adding info to 'i' as we go along. */
4674 END_STRING_AND_SAVE (l);
4675
4676 if (intel_syntax)
4677 operand_ok =
4678 i386_intel_operand (token_start,
4679 intel_float_operand (mnemonic));
4680 else
a7619375 4681 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4682
4683 RESTORE_END_STRING (l);
4684 if (!operand_ok)
4685 return NULL;
4686 }
4687 else
4688 {
4689 if (expecting_operand)
4690 {
4691 expecting_operand_after_comma:
4692 as_bad (_("expecting operand after ','; got nothing"));
4693 return NULL;
4694 }
4695 if (*l == ',')
4696 {
4697 as_bad (_("expecting operand before ','; got nothing"));
4698 return NULL;
4699 }
4700 }
7f3f1ea2 4701
29b0f896
AM		 4702 /* Now *l must be either ',' or END_OF_INSN. */
4703 if (*l == ',')
4704 {
4705 if (*++l == END_OF_INSN)
4706 {
4707 /* Just skip it, if it's \n complain. */
4708 goto expecting_operand_after_comma;
4709 }
4710 expecting_operand = 1;
4711 }
4712 }
4713 return l;
4714}
7f3f1ea2 4715
050dfa73 4716static void
4d456e3d 4717swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4718{
4719 union i386_op temp_op;
40fb9820 4720 i386_operand_type temp_type;
050dfa73 4721 enum bfd_reloc_code_real temp_reloc;
4eed87de 4722
050dfa73
MM		 4723 temp_type = i.types[xchg2];
4724 i.types[xchg2] = i.types[xchg1];
4725 i.types[xchg1] = temp_type;
4726 temp_op = i.op[xchg2];
4727 i.op[xchg2] = i.op[xchg1];
4728 i.op[xchg1] = temp_op;
4729 temp_reloc = i.reloc[xchg2];
4730 i.reloc[xchg2] = i.reloc[xchg1];
4731 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4732
4733 if (i.mask)
4734 {
4735 if (i.mask->operand == xchg1)
4736 i.mask->operand = xchg2;
4737 else if (i.mask->operand == xchg2)
4738 i.mask->operand = xchg1;
4739 }
4740 if (i.broadcast)
4741 {
4742 if (i.broadcast->operand == xchg1)
4743 i.broadcast->operand = xchg2;
4744 else if (i.broadcast->operand == xchg2)
4745 i.broadcast->operand = xchg1;
4746 }
4747 if (i.rounding)
4748 {
4749 if (i.rounding->operand == xchg1)
4750 i.rounding->operand = xchg2;
4751 else if (i.rounding->operand == xchg2)
4752 i.rounding->operand = xchg1;
4753 }
050dfa73
MM		 4754}
4755
29b0f896 4756static void
e3bb37b5 4757swap_operands (void)
29b0f896 4758{
b7c61d9a 4759 switch (i.operands)
050dfa73 4760 {
c0f3af97 4761 case 5:
b7c61d9a 4762 case 4:
4d456e3d 4763 swap_2_operands (1, i.operands - 2);
1a0670f3 4764 /* Fall through. */
b7c61d9a
L		 4765 case 3:
4766 case 2:
4d456e3d 4767 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4768 break;
4769 default:
4770 abort ();
29b0f896 4771 }
29b0f896
AM		 4772
4773 if (i.mem_operands == 2)
4774 {
4775 const seg_entry *temp_seg;
4776 temp_seg = i.seg[0];
4777 i.seg[0] = i.seg[1];
4778 i.seg[1] = temp_seg;
4779 }
4780}
252b5132 4781
29b0f896
AM		 4782/* Try to ensure constant immediates are represented in the smallest
4783 opcode possible. */
4784static void
e3bb37b5 4785optimize_imm (void)
29b0f896
AM		 4786{
4787 char guess_suffix = 0;
4788 int op;
252b5132 4789
29b0f896
AM		 4790 if (i.suffix)
4791 guess_suffix = i.suffix;
4792 else if (i.reg_operands)
4793 {
4794 /* Figure out a suffix from the last register operand specified.
4795 We can't do this properly yet, ie. excluding InOutPortReg,
4796 but the following works for instructions with immediates.
4797 In any case, we can't set i.suffix yet. */
4798 for (op = i.operands; --op >= 0;)
dc821c5f 4799 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4800 {
40fb9820
L		 4801 guess_suffix = BYTE_MNEM_SUFFIX;
4802 break;
4803 }
dc821c5f 4804 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4805 {
40fb9820
L		 4806 guess_suffix = WORD_MNEM_SUFFIX;
4807 break;
4808 }
dc821c5f 4809 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4810 {
4811 guess_suffix = LONG_MNEM_SUFFIX;
4812 break;
4813 }
dc821c5f 4814 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4815 {
4816 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4817 break;
252b5132 4818 }
29b0f896
AM		 4819 }
4820 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4821 guess_suffix = WORD_MNEM_SUFFIX;
4822
4823 for (op = i.operands; --op >= 0;)
40fb9820 4824 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4825 {
4826 switch (i.op[op].imms->X_op)
252b5132 4827 {
29b0f896
AM		 4828 case O_constant:
4829 /* If a suffix is given, this operand may be shortened. */
4830 switch (guess_suffix)
252b5132 4831 {
29b0f896 4832 case LONG_MNEM_SUFFIX:
40fb9820
L		 4833 i.types[op].bitfield.imm32 = 1;
4834 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4835 break;
4836 case WORD_MNEM_SUFFIX:
40fb9820
L		 4837 i.types[op].bitfield.imm16 = 1;
4838 i.types[op].bitfield.imm32 = 1;
4839 i.types[op].bitfield.imm32s = 1;
4840 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4841 break;
4842 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4843 i.types[op].bitfield.imm8 = 1;
4844 i.types[op].bitfield.imm8s = 1;
4845 i.types[op].bitfield.imm16 = 1;
4846 i.types[op].bitfield.imm32 = 1;
4847 i.types[op].bitfield.imm32s = 1;
4848 i.types[op].bitfield.imm64 = 1;
29b0f896 4849 break;
252b5132 4850 }
252b5132 4851
29b0f896
AM		 4852 /* If this operand is at most 16 bits, convert it
4853 to a signed 16 bit number before trying to see
4854 whether it will fit in an even smaller size.
4855 This allows a 16-bit operand such as $0xffe0 to
4856 be recognised as within Imm8S range. */
40fb9820 4857 if ((i.types[op].bitfield.imm16)
29b0f896 4858 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4859 {
29b0f896
AM		 4860 i.op[op].imms->X_add_number =
4861 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4862 }
a28def75
L		 4863#ifdef BFD64
4864 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4865 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4866 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4867 == 0))
4868 {
4869 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4870 ^ ((offsetT) 1 << 31))
4871 - ((offsetT) 1 << 31));
4872 }
a28def75 4873#endif
40fb9820 4874 i.types[op]
c6fb90c8
L		 4875 = operand_type_or (i.types[op],
4876 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4877
29b0f896
AM		 4878 /* We must avoid matching of Imm32 templates when 64bit
4879 only immediate is available. */
4880 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4881 i.types[op].bitfield.imm32 = 0;
29b0f896 4882 break;
252b5132 4883
29b0f896
AM		 4884 case O_absent:
4885 case O_register:
4886 abort ();
4887
4888 /* Symbols and expressions. */
4889 default:
9cd96992
JB		 4890 /* Convert symbolic operand to proper sizes for matching, but don't
4891 prevent matching a set of insns that only supports sizes other
4892 than those matching the insn suffix. */
4893 {
40fb9820 4894 i386_operand_type mask, allowed;
d3ce72d0 4895 const insn_template *t;
9cd96992 4896
0dfbf9d7
L		 4897 operand_type_set (&mask, 0);
4898 operand_type_set (&allowed, 0);
40fb9820 4899
4eed87de
AM		 4900 for (t = current_templates->start;
4901 t < current_templates->end;
4902 ++t)
c6fb90c8
L		 4903 allowed = operand_type_or (allowed,
4904 t->operand_types[op]);
9cd96992
JB		 4905 switch (guess_suffix)
4906 {
4907 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4908 mask.bitfield.imm64 = 1;
4909 mask.bitfield.imm32s = 1;
9cd96992
JB		 4910 break;
4911 case LONG_MNEM_SUFFIX:
40fb9820 4912 mask.bitfield.imm32 = 1;
9cd96992
JB		 4913 break;
4914 case WORD_MNEM_SUFFIX:
40fb9820 4915 mask.bitfield.imm16 = 1;
9cd96992
JB		 4916 break;
4917 case BYTE_MNEM_SUFFIX:
40fb9820 4918 mask.bitfield.imm8 = 1;
9cd96992
JB		 4919 break;
4920 default:
9cd96992
JB		 4921 break;
4922 }
c6fb90c8 4923 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4924 if (!operand_type_all_zero (&allowed))
c6fb90c8 4925 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4926 }
29b0f896 4927 break;
252b5132 4928 }
29b0f896
AM		 4929 }
4930}
47926f60 4931
29b0f896
AM		 4932/* Try to use the smallest displacement type too. */
4933static void
e3bb37b5 4934optimize_disp (void)
29b0f896
AM		 4935{
4936 int op;
3e73aa7c 4937
29b0f896 4938 for (op = i.operands; --op >= 0;)
40fb9820 4939 if (operand_type_check (i.types[op], disp))
252b5132 4940 {
b300c311 4941 if (i.op[op].disps->X_op == O_constant)
252b5132 4942 {
91d6fa6a 4943 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4944
40fb9820 4945 if (i.types[op].bitfield.disp16
91d6fa6a 4946 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4947 {
4948 /* If this operand is at most 16 bits, convert
4949 to a signed 16 bit number and don't use 64bit
4950 displacement. */
91d6fa6a 4951 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4952 i.types[op].bitfield.disp64 = 0;
b300c311 4953 }
a28def75
L		 4954#ifdef BFD64
4955 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4956 if (i.types[op].bitfield.disp32
91d6fa6a 4957 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4958 {
4959 /* If this operand is at most 32 bits, convert
4960 to a signed 32 bit number and don't use 64bit
4961 displacement. */
91d6fa6a
NC		 4962 op_disp &= (((offsetT) 2 << 31) - 1);
4963 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4964 i.types[op].bitfield.disp64 = 0;
b300c311 4965 }
a28def75 4966#endif
91d6fa6a 4967 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4968 {
40fb9820
L		 4969 i.types[op].bitfield.disp8 = 0;
4970 i.types[op].bitfield.disp16 = 0;
4971 i.types[op].bitfield.disp32 = 0;
4972 i.types[op].bitfield.disp32s = 0;
4973 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4974 i.op[op].disps = 0;
4975 i.disp_operands--;
4976 }
4977 else if (flag_code == CODE_64BIT)
4978 {
91d6fa6a 4979 if (fits_in_signed_long (op_disp))
28a9d8f5 4980 {
40fb9820
L		 4981 i.types[op].bitfield.disp64 = 0;
4982 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4983 }
0e1147d9 4984 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4985 && fits_in_unsigned_long (op_disp))
40fb9820 4986 i.types[op].bitfield.disp32 = 1;
b300c311 4987 }
40fb9820
L		 4988 if ((i.types[op].bitfield.disp32
4989 || i.types[op].bitfield.disp32s
4990 || i.types[op].bitfield.disp16)
b5014f7a 4991 && fits_in_disp8 (op_disp))
40fb9820 4992 i.types[op].bitfield.disp8 = 1;
252b5132 4993 }
67a4f2b7
AO		 4994 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4995 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4996 {
4997 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4998 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4999 i.types[op].bitfield.disp8 = 0;
5000 i.types[op].bitfield.disp16 = 0;
5001 i.types[op].bitfield.disp32 = 0;
5002 i.types[op].bitfield.disp32s = 0;
5003 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 5004 }
5005 else
b300c311 5006 /* We only support 64bit displacement on constants. */
40fb9820 5007 i.types[op].bitfield.disp64 = 0;
252b5132 5008 }
29b0f896
AM		 5009}
5010
6c30d220
L		 5011/* Check if operands are valid for the instruction. */
5012
5013static int
5014check_VecOperands (const insn_template *t)
5015{
43234a1e 5016 unsigned int op;
e2195274
JB		 5017 i386_cpu_flags cpu;
5018 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5019
5020 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5021 any one operand are implicity requiring AVX512VL support if the actual
5022 operand size is YMMword or XMMword. Since this function runs after
5023 template matching, there's no need to check for YMMword/XMMword in
5024 the template. */
5025 cpu = cpu_flags_and (t->cpu_flags, avx512);
5026 if (!cpu_flags_all_zero (&cpu)
5027 && !t->cpu_flags.bitfield.cpuavx512vl
5028 && !cpu_arch_flags.bitfield.cpuavx512vl)
5029 {
5030 for (op = 0; op < t->operands; ++op)
5031 {
5032 if (t->operand_types[op].bitfield.zmmword
5033 && (i.types[op].bitfield.ymmword
5034 || i.types[op].bitfield.xmmword))
5035 {
5036 i.error = unsupported;
5037 return 1;
5038 }
5039 }
5040 }
43234a1e 5041
6c30d220
L		 5042 /* Without VSIB byte, we can't have a vector register for index. */
5043 if (!t->opcode_modifier.vecsib
5044 && i.index_reg
1b54b8d7
JB		 5045 && (i.index_reg->reg_type.bitfield.xmmword
5046 || i.index_reg->reg_type.bitfield.ymmword
5047 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5048 {
5049 i.error = unsupported_vector_index_register;
5050 return 1;
5051 }
5052
ad8ecc81
MZ		 5053 /* Check if default mask is allowed. */
5054 if (t->opcode_modifier.nodefmask
5055 && (!i.mask || i.mask->mask->reg_num == 0))
5056 {
5057 i.error = no_default_mask;
5058 return 1;
5059 }
5060
7bab8ab5
JB		 5061 /* For VSIB byte, we need a vector register for index, and all vector
5062 registers must be distinct. */
5063 if (t->opcode_modifier.vecsib)
5064 {
5065 if (!i.index_reg
6c30d220 5066 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5067 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5068 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5069 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5070 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5071 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5072 {
5073 i.error = invalid_vsib_address;
5074 return 1;
5075 }
5076
43234a1e
L		 5077 gas_assert (i.reg_operands == 2 || i.mask);
5078 if (i.reg_operands == 2 && !i.mask)
5079 {
1b54b8d7
JB		 5080 gas_assert (i.types[0].bitfield.regsimd);
5081 gas_assert (i.types[0].bitfield.xmmword
5082 || i.types[0].bitfield.ymmword);
5083 gas_assert (i.types[2].bitfield.regsimd);
5084 gas_assert (i.types[2].bitfield.xmmword
5085 || i.types[2].bitfield.ymmword);
43234a1e
L		 5086 if (operand_check == check_none)
5087 return 0;
5088 if (register_number (i.op[0].regs)
5089 != register_number (i.index_reg)
5090 && register_number (i.op[2].regs)
5091 != register_number (i.index_reg)
5092 && register_number (i.op[0].regs)
5093 != register_number (i.op[2].regs))
5094 return 0;
5095 if (operand_check == check_error)
5096 {
5097 i.error = invalid_vector_register_set;
5098 return 1;
5099 }
5100 as_warn (_("mask, index, and destination registers should be distinct"));
5101 }
8444f82a
MZ		 5102 else if (i.reg_operands == 1 && i.mask)
5103 {
1b54b8d7
JB		 5104 if (i.types[1].bitfield.regsimd
5105 && (i.types[1].bitfield.xmmword
5106 || i.types[1].bitfield.ymmword
5107 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5108 && (register_number (i.op[1].regs)
5109 == register_number (i.index_reg)))
5110 {
5111 if (operand_check == check_error)
5112 {
5113 i.error = invalid_vector_register_set;
5114 return 1;
5115 }
5116 if (operand_check != check_none)
5117 as_warn (_("index and destination registers should be distinct"));
5118 }
5119 }
43234a1e 5120 }
7bab8ab5 5121
43234a1e
L		 5122 /* Check if broadcast is supported by the instruction and is applied
5123 to the memory operand. */
5124 if (i.broadcast)
5125 {
8e6e0792 5126 i386_operand_type type, overlap;
43234a1e
L		 5127
5128 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5129 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5130 op = i.broadcast->operand;
8e6e0792 5131 if (!t->opcode_modifier.broadcast
32546502 5132 || !i.types[op].bitfield.mem
c39e5b26
JB		 5133 || (!i.types[op].bitfield.unspecified
5134 && (t->operand_types[op].bitfield.dword
5135 ? !i.types[op].bitfield.dword
5136 : !i.types[op].bitfield.qword)))
43234a1e
L		 5137 {
5138 bad_broadcast:
5139 i.error = unsupported_broadcast;
5140 return 1;
5141 }
8e6e0792
JB		 5142
5143 operand_type_set (&type, 0);
c39e5b26 5144 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5145 {
5146 case 8:
5147 type.bitfield.qword = 1;
5148 break;
5149 case 16:
5150 type.bitfield.xmmword = 1;
5151 break;
5152 case 32:
5153 type.bitfield.ymmword = 1;
5154 break;
5155 case 64:
5156 type.bitfield.zmmword = 1;
5157 break;
5158 default:
5159 goto bad_broadcast;
5160 }
5161
5162 overlap = operand_type_and (type, t->operand_types[op]);
5163 if (operand_type_all_zero (&overlap))
5164 goto bad_broadcast;
5165
5166 if (t->opcode_modifier.checkregsize)
5167 {
5168 unsigned int j;
5169
e2195274 5170 type.bitfield.baseindex = 1;
8e6e0792
JB		 5171 for (j = 0; j < i.operands; ++j)
5172 {
5173 if (j != op
5174 && !operand_type_register_match(i.types[j],
5175 t->operand_types[j],
5176 type,
5177 t->operand_types[op]))
5178 goto bad_broadcast;
5179 }
5180 }
43234a1e
L		 5181 }
5182 /* If broadcast is supported in this instruction, we need to check if
5183 operand of one-element size isn't specified without broadcast. */
5184 else if (t->opcode_modifier.broadcast && i.mem_operands)
5185 {
5186 /* Find memory operand. */
5187 for (op = 0; op < i.operands; op++)
5188 if (operand_type_check (i.types[op], anymem))
5189 break;
5190 gas_assert (op < i.operands);
5191 /* Check size of the memory operand. */
c39e5b26
JB		 5192 if (t->operand_types[op].bitfield.dword
5193 ? i.types[op].bitfield.dword
5194 : i.types[op].bitfield.qword)
43234a1e
L		 5195 {
5196 i.error = broadcast_needed;
5197 return 1;
5198 }
5199 }
c39e5b26
JB		 5200 else
5201 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5202
5203 /* Check if requested masking is supported. */
5204 if (i.mask
5205 && (!t->opcode_modifier.masking
5206 || (i.mask->zeroing
5207 && t->opcode_modifier.masking == MERGING_MASKING)))
5208 {
5209 i.error = unsupported_masking;
5210 return 1;
5211 }
5212
5213 /* Check if masking is applied to dest operand. */
5214 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5215 {
5216 i.error = mask_not_on_destination;
5217 return 1;
5218 }
5219
43234a1e
L		 5220 /* Check RC/SAE. */
5221 if (i.rounding)
5222 {
5223 if ((i.rounding->type != saeonly
5224 && !t->opcode_modifier.staticrounding)
5225 || (i.rounding->type == saeonly
5226 && (t->opcode_modifier.staticrounding
5227 || !t->opcode_modifier.sae)))
5228 {
5229 i.error = unsupported_rc_sae;
5230 return 1;
5231 }
5232 /* If the instruction has several immediate operands and one of
5233 them is rounding, the rounding operand should be the last
5234 immediate operand. */
5235 if (i.imm_operands > 1
5236 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5237 {
43234a1e 5238 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5239 return 1;
5240 }
6c30d220
L		 5241 }
5242
43234a1e 5243 /* Check vector Disp8 operand. */
b5014f7a
JB		 5244 if (t->opcode_modifier.disp8memshift
5245 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5246 {
5247 if (i.broadcast)
c39e5b26 5248 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
7091c612 5249 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
43234a1e 5250 i.memshift = t->opcode_modifier.disp8memshift;
7091c612
JB		 5251 else
5252 {
5253 const i386_operand_type *type = NULL;
5254
5255 i.memshift = 0;
5256 for (op = 0; op < i.operands; op++)
5257 if (operand_type_check (i.types[op], anymem))
5258 {
5259 if (t->operand_types[op].bitfield.xmmword
5260 + t->operand_types[op].bitfield.ymmword
5261 + t->operand_types[op].bitfield.zmmword <= 1)
5262 type = &t->operand_types[op];
5263 else if (!i.types[op].bitfield.unspecified)
5264 type = &i.types[op];
5265 }
5266 else if (i.types[op].bitfield.regsimd)
5267 {
5268 if (i.types[op].bitfield.zmmword)
5269 i.memshift = 6;
5270 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5271 i.memshift = 5;
5272 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5273 i.memshift = 4;
5274 }
5275
5276 if (type)
5277 {
5278 if (type->bitfield.zmmword)
5279 i.memshift = 6;
5280 else if (type->bitfield.ymmword)
5281 i.memshift = 5;
5282 else if (type->bitfield.xmmword)
5283 i.memshift = 4;
5284 }
5285
5286 /* For the check in fits_in_disp8(). */
5287 if (i.memshift == 0)
5288 i.memshift = -1;
5289 }
43234a1e
L		 5290
5291 for (op = 0; op < i.operands; op++)
5292 if (operand_type_check (i.types[op], disp)
5293 && i.op[op].disps->X_op == O_constant)
5294 {
b5014f7a 5295 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5296 {
b5014f7a
JB		 5297 i.types[op].bitfield.disp8 = 1;
5298 return 0;
43234a1e 5299 }
b5014f7a 5300 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5301 }
5302 }
b5014f7a
JB		 5303
5304 i.memshift = 0;
43234a1e 5305
6c30d220
L		 5306 return 0;
5307}
5308
43f3e2ee 5309/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5310 operand types. */
5311
5312static int
5313VEX_check_operands (const insn_template *t)
5314{
86fa6981 5315 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5316 {
86fa6981 5317 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5318 if (!is_evex_encoding (t))
86fa6981
L		 5319 {
5320 i.error = unsupported;
5321 return 1;
5322 }
5323 return 0;
43234a1e
L		 5324 }
5325
a683cc34 5326 if (!t->opcode_modifier.vex)
86fa6981
L		 5327 {
5328 /* This instruction template doesn't have VEX prefix. */
5329 if (i.vec_encoding != vex_encoding_default)
5330 {
5331 i.error = unsupported;
5332 return 1;
5333 }
5334 return 0;
5335 }
a683cc34
SP		 5336
5337 /* Only check VEX_Imm4, which must be the first operand. */
5338 if (t->operand_types[0].bitfield.vec_imm4)
5339 {
5340 if (i.op[0].imms->X_op != O_constant
5341 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5342 {
a65babc9 5343 i.error = bad_imm4;
891edac4
L		 5344 return 1;
5345 }
a683cc34
SP		 5346
5347 /* Turn off Imm8 so that update_imm won't complain. */
5348 i.types[0] = vec_imm4;
5349 }
5350
5351 return 0;
5352}
5353
d3ce72d0 5354static const insn_template *
83b16ac6 5355match_template (char mnem_suffix)
29b0f896
AM		 5356{
5357 /* Points to template once we've found it. */
d3ce72d0 5358 const insn_template *t;
40fb9820 5359 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5360 i386_operand_type overlap4;
29b0f896 5361 unsigned int found_reverse_match;
83b16ac6 5362 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5363 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5364 int addr_prefix_disp;
a5c311ca 5365 unsigned int j;
3ac21baa 5366 unsigned int found_cpu_match, size_match;
45664ddb 5367 unsigned int check_register;
5614d22c 5368 enum i386_error specific_error = 0;
29b0f896 5369
c0f3af97
L		 5370#if MAX_OPERANDS != 5
5371# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5372#endif
5373
29b0f896 5374 found_reverse_match = 0;
539e75ad 5375 addr_prefix_disp = -1;
40fb9820
L		 5376
5377 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5378 if (intel_syntax && i.broadcast)
5379 /* nothing */;
5380 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5381 suffix_check.no_bsuf = 1;
5382 else if (i.suffix == WORD_MNEM_SUFFIX)
5383 suffix_check.no_wsuf = 1;
5384 else if (i.suffix == SHORT_MNEM_SUFFIX)
5385 suffix_check.no_ssuf = 1;
5386 else if (i.suffix == LONG_MNEM_SUFFIX)
5387 suffix_check.no_lsuf = 1;
5388 else if (i.suffix == QWORD_MNEM_SUFFIX)
5389 suffix_check.no_qsuf = 1;
5390 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5391 suffix_check.no_ldsuf = 1;
29b0f896 5392
83b16ac6
JB		 5393 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5394 if (intel_syntax)
5395 {
5396 switch (mnem_suffix)
5397 {
5398 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5399 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5400 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5401 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5402 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5403 }
5404 }
5405
01559ecc
L		 5406 /* Must have right number of operands. */
5407 i.error = number_of_operands_mismatch;
5408
45aa61fe 5409 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5410 {
539e75ad
L		 5411 addr_prefix_disp = -1;
5412
29b0f896
AM		 5413 if (i.operands != t->operands)
5414 continue;
5415
50aecf8c 5416 /* Check processor support. */
a65babc9 5417 i.error = unsupported;
c0f3af97
L		 5418 found_cpu_match = (cpu_flags_match (t)
5419 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5420 if (!found_cpu_match)
5421 continue;
5422
e1d4d893 5423 /* Check AT&T mnemonic. */
a65babc9 5424 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5425 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5426 continue;
5427
e92bae62 5428 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5429 i.error = unsupported_syntax;
5c07affc 5430 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5431 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5432 || (intel64 && t->opcode_modifier.amd64)
5433 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5434 continue;
5435
20592a94 5436 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5437 i.error = invalid_instruction_suffix;
567e4e96
L		 5438 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5439 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5440 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5441 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5442 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5443 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5444 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5445 continue;
83b16ac6
JB		 5446 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5447 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5448 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5449 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5450 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5451 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5452 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5453 continue;
29b0f896 5454
3ac21baa
JB		 5455 size_match = operand_size_match (t);
5456 if (!size_match)
7d5e4556 5457 continue;
539e75ad 5458
5c07affc
L		 5459 for (j = 0; j < MAX_OPERANDS; j++)
5460 operand_types[j] = t->operand_types[j];
5461
45aa61fe
AM		 5462 /* In general, don't allow 64-bit operands in 32-bit mode. */
5463 if (i.suffix == QWORD_MNEM_SUFFIX
5464 && flag_code != CODE_64BIT
5465 && (intel_syntax
40fb9820 5466 ? (!t->opcode_modifier.ignoresize
625cbd7a 5467 && !t->opcode_modifier.broadcast
45aa61fe
AM		 5468 && !intel_float_operand (t->name))
5469 : intel_float_operand (t->name) != 2)
40fb9820 5470 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5471 && !operand_types[0].bitfield.regsimd)
40fb9820 5472 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5473 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5474 && (t->base_opcode != 0x0fc7
5475 || t->extension_opcode != 1 /* cmpxchg8b */))
5476 continue;
5477
192dc9c6
JB		 5478 /* In general, don't allow 32-bit operands on pre-386. */
5479 else if (i.suffix == LONG_MNEM_SUFFIX
5480 && !cpu_arch_flags.bitfield.cpui386
5481 && (intel_syntax
5482 ? (!t->opcode_modifier.ignoresize
5483 && !intel_float_operand (t->name))
5484 : intel_float_operand (t->name) != 2)
5485 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5486 && !operand_types[0].bitfield.regsimd)
192dc9c6 5487 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5488 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5489 continue;
5490
29b0f896 5491 /* Do not verify operands when there are none. */
50aecf8c 5492 else
29b0f896 5493 {
c6fb90c8 5494 if (!t->operands)
2dbab7d5
L		 5495 /* We've found a match; break out of loop. */
5496 break;
29b0f896 5497 }
252b5132 5498
539e75ad
L		 5499 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5500 into Disp32/Disp16/Disp32 operand. */
5501 if (i.prefix[ADDR_PREFIX] != 0)
5502 {
40fb9820 5503 /* There should be only one Disp operand. */
539e75ad
L		 5504 switch (flag_code)
5505 {
5506 case CODE_16BIT:
40fb9820
L		 5507 for (j = 0; j < MAX_OPERANDS; j++)
5508 {
5509 if (operand_types[j].bitfield.disp16)
5510 {
5511 addr_prefix_disp = j;
5512 operand_types[j].bitfield.disp32 = 1;
5513 operand_types[j].bitfield.disp16 = 0;
5514 break;
5515 }
5516 }
539e75ad
L		 5517 break;
5518 case CODE_32BIT:
40fb9820
L		 5519 for (j = 0; j < MAX_OPERANDS; j++)
5520 {
5521 if (operand_types[j].bitfield.disp32)
5522 {
5523 addr_prefix_disp = j;
5524 operand_types[j].bitfield.disp32 = 0;
5525 operand_types[j].bitfield.disp16 = 1;
5526 break;
5527 }
5528 }
539e75ad
L		 5529 break;
5530 case CODE_64BIT:
40fb9820
L		 5531 for (j = 0; j < MAX_OPERANDS; j++)
5532 {
5533 if (operand_types[j].bitfield.disp64)
5534 {
5535 addr_prefix_disp = j;
5536 operand_types[j].bitfield.disp64 = 0;
5537 operand_types[j].bitfield.disp32 = 1;
5538 break;
5539 }
5540 }
539e75ad
L		 5541 break;
5542 }
539e75ad
L		 5543 }
5544
02a86693
L		 5545 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5546 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5547 continue;
5548
56ffb741 5549 /* We check register size if needed. */
e2195274
JB		 5550 if (t->opcode_modifier.checkregsize)
5551 {
5552 check_register = (1 << t->operands) - 1;
5553 if (i.broadcast)
5554 check_register &= ~(1 << i.broadcast->operand);
5555 }
5556 else
5557 check_register = 0;
5558
c6fb90c8 5559 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5560 switch (t->operands)
5561 {
5562 case 1:
40fb9820 5563 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5564 continue;
5565 break;
5566 case 2:
33eaf5de 5567 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5568 only in 32bit mode and we can use opcode 0x90. In 64bit
5569 mode, we can't use 0x90 for xchg %eax, %eax since it should
5570 zero-extend %eax to %rax. */
5571 if (flag_code == CODE_64BIT
5572 && t->base_opcode == 0x90
0dfbf9d7
L		 5573 && operand_type_equal (&i.types [0], &acc32)
5574 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5575 continue;
1212781b
JB		 5576 /* xrelease mov %eax, <disp> is another special case. It must not
5577 match the accumulator-only encoding of mov. */
5578 if (flag_code != CODE_64BIT
5579 && i.hle_prefix
5580 && t->base_opcode == 0xa0
5581 && i.types[0].bitfield.acc
5582 && operand_type_check (i.types[1], anymem))
5583 continue;
3ac21baa
JB		 5584 if (!(size_match & MATCH_STRAIGHT))
5585 goto check_reverse;
86fa6981
L		 5586 /* If we want store form, we reverse direction of operands. */
5587 if (i.dir_encoding == dir_encoding_store
5588 && t->opcode_modifier.d)
5589 goto check_reverse;
1a0670f3 5590 /* Fall through. */
b6169b20 5591
29b0f896 5592 case 3:
86fa6981
L		 5593 /* If we want store form, we skip the current load. */
5594 if (i.dir_encoding == dir_encoding_store
5595 && i.mem_operands == 0
5596 && t->opcode_modifier.load)
fa99fab2 5597 continue;
1a0670f3 5598 /* Fall through. */
f48ff2ae 5599 case 4:
c0f3af97 5600 case 5:
c6fb90c8 5601 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5602 if (!operand_type_match (overlap0, i.types[0])
5603 || !operand_type_match (overlap1, i.types[1])
e2195274 5604 || ((check_register & 3) == 3
dc821c5f 5605 && !operand_type_register_match (i.types[0],
40fb9820 5606 operand_types[0],
dc821c5f 5607 i.types[1],
40fb9820 5608 operand_types[1])))
29b0f896
AM		 5609 {
5610 /* Check if other direction is valid ... */
38e314eb 5611 if (!t->opcode_modifier.d)
29b0f896
AM		 5612 continue;
5613
b6169b20 5614check_reverse:
3ac21baa
JB		 5615 if (!(size_match & MATCH_REVERSE))
5616 continue;
29b0f896 5617 /* Try reversing direction of operands. */
c6fb90c8
L		 5618 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5619 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5620 if (!operand_type_match (overlap0, i.types[0])
5621 || !operand_type_match (overlap1, i.types[1])
45664ddb 5622 || (check_register
dc821c5f 5623 && !operand_type_register_match (i.types[0],
45664ddb 5624 operand_types[1],
45664ddb
L		 5625 i.types[1],
5626 operand_types[0])))
29b0f896
AM		 5627 {
5628 /* Does not match either direction. */
5629 continue;
5630 }
38e314eb 5631 /* found_reverse_match holds which of D or FloatR
29b0f896 5632 we've found. */
38e314eb
JB		 5633 if (!t->opcode_modifier.d)
5634 found_reverse_match = 0;
5635 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5636 found_reverse_match = Opcode_FloatD;
5637 else
38e314eb 5638 found_reverse_match = Opcode_D;
40fb9820 5639 if (t->opcode_modifier.floatr)
8a2ed489 5640 found_reverse_match |= Opcode_FloatR;
29b0f896 5641 }
f48ff2ae 5642 else
29b0f896 5643 {
f48ff2ae 5644 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5645 switch (t->operands)
5646 {
c0f3af97
L		 5647 case 5:
5648 overlap4 = operand_type_and (i.types[4],
5649 operand_types[4]);
1a0670f3 5650 /* Fall through. */
d1cbb4db 5651 case 4:
c6fb90c8
L		 5652 overlap3 = operand_type_and (i.types[3],
5653 operand_types[3]);
1a0670f3 5654 /* Fall through. */
d1cbb4db 5655 case 3:
c6fb90c8
L		 5656 overlap2 = operand_type_and (i.types[2],
5657 operand_types[2]);
d1cbb4db
L		 5658 break;
5659 }
29b0f896 5660
f48ff2ae
L		 5661 switch (t->operands)
5662 {
c0f3af97
L		 5663 case 5:
5664 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5665 || !operand_type_register_match (i.types[3],
c0f3af97 5666 operand_types[3],
c0f3af97
L		 5667 i.types[4],
5668 operand_types[4]))
5669 continue;
1a0670f3 5670 /* Fall through. */
f48ff2ae 5671 case 4:
40fb9820 5672 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5673 || ((check_register & 0xa) == 0xa
5674 && !operand_type_register_match (i.types[1],
f7768225
JB		 5675 operand_types[1],
5676 i.types[3],
e2195274
JB		 5677 operand_types[3]))
5678 || ((check_register & 0xc) == 0xc
5679 && !operand_type_register_match (i.types[2],
5680 operand_types[2],
5681 i.types[3],
5682 operand_types[3])))
f48ff2ae 5683 continue;
1a0670f3 5684 /* Fall through. */
f48ff2ae
L		 5685 case 3:
5686 /* Here we make use of the fact that there are no
23e42951 5687 reverse match 3 operand instructions. */
40fb9820 5688 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5689 || ((check_register & 5) == 5
5690 && !operand_type_register_match (i.types[0],
23e42951
JB		 5691 operand_types[0],
5692 i.types[2],
e2195274
JB		 5693 operand_types[2]))
5694 || ((check_register & 6) == 6
5695 && !operand_type_register_match (i.types[1],
5696 operand_types[1],
5697 i.types[2],
5698 operand_types[2])))
f48ff2ae
L		 5699 continue;
5700 break;
5701 }
29b0f896 5702 }
f48ff2ae 5703 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5704 slip through to break. */
5705 }
3629bb00 5706 if (!found_cpu_match)
29b0f896
AM		 5707 {
5708 found_reverse_match = 0;
5709 continue;
5710 }
c0f3af97 5711
5614d22c
JB		 5712 /* Check if vector and VEX operands are valid. */
5713 if (check_VecOperands (t) || VEX_check_operands (t))
5714 {
5715 specific_error = i.error;
5716 continue;
5717 }
a683cc34 5718
29b0f896
AM		 5719 /* We've found a match; break out of loop. */
5720 break;
5721 }
5722
5723 if (t == current_templates->end)
5724 {
5725 /* We found no match. */
a65babc9 5726 const char *err_msg;
5614d22c 5727 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5728 {
5729 default:
5730 abort ();
86e026a4 5731 case operand_size_mismatch:
a65babc9
L		 5732 err_msg = _("operand size mismatch");
5733 break;
5734 case operand_type_mismatch:
5735 err_msg = _("operand type mismatch");
5736 break;
5737 case register_type_mismatch:
5738 err_msg = _("register type mismatch");
5739 break;
5740 case number_of_operands_mismatch:
5741 err_msg = _("number of operands mismatch");
5742 break;
5743 case invalid_instruction_suffix:
5744 err_msg = _("invalid instruction suffix");
5745 break;
5746 case bad_imm4:
4a2608e3 5747 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5748 break;
a65babc9
L		 5749 case unsupported_with_intel_mnemonic:
5750 err_msg = _("unsupported with Intel mnemonic");
5751 break;
5752 case unsupported_syntax:
5753 err_msg = _("unsupported syntax");
5754 break;
5755 case unsupported:
35262a23 5756 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5757 current_templates->start->name);
5758 return NULL;
6c30d220
L		 5759 case invalid_vsib_address:
5760 err_msg = _("invalid VSIB address");
5761 break;
7bab8ab5
JB		 5762 case invalid_vector_register_set:
5763 err_msg = _("mask, index, and destination registers must be distinct");
5764 break;
6c30d220
L		 5765 case unsupported_vector_index_register:
5766 err_msg = _("unsupported vector index register");
5767 break;
43234a1e
L		 5768 case unsupported_broadcast:
5769 err_msg = _("unsupported broadcast");
5770 break;
43234a1e
L		 5771 case broadcast_needed:
5772 err_msg = _("broadcast is needed for operand of such type");
5773 break;
5774 case unsupported_masking:
5775 err_msg = _("unsupported masking");
5776 break;
5777 case mask_not_on_destination:
5778 err_msg = _("mask not on destination operand");
5779 break;
5780 case no_default_mask:
5781 err_msg = _("default mask isn't allowed");
5782 break;
5783 case unsupported_rc_sae:
5784 err_msg = _("unsupported static rounding/sae");
5785 break;
5786 case rc_sae_operand_not_last_imm:
5787 if (intel_syntax)
5788 err_msg = _("RC/SAE operand must precede immediate operands");
5789 else
5790 err_msg = _("RC/SAE operand must follow immediate operands");
5791 break;
5792 case invalid_register_operand:
5793 err_msg = _("invalid register operand");
5794 break;
a65babc9
L		 5795 }
5796 as_bad (_("%s for `%s'"), err_msg,
891edac4 5797 current_templates->start->name);
fa99fab2 5798 return NULL;
29b0f896 5799 }
252b5132 5800
29b0f896
AM		 5801 if (!quiet_warnings)
5802 {
5803 if (!intel_syntax
40fb9820
L		 5804 && (i.types[0].bitfield.jumpabsolute
5805 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5806 {
5807 as_warn (_("indirect %s without `*'"), t->name);
5808 }
5809
40fb9820
L		 5810 if (t->opcode_modifier.isprefix
5811 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5812 {
5813 /* Warn them that a data or address size prefix doesn't
5814 affect assembly of the next line of code. */
5815 as_warn (_("stand-alone `%s' prefix"), t->name);
5816 }
5817 }
5818
5819 /* Copy the template we found. */
5820 i.tm = *t;
539e75ad
L		 5821
5822 if (addr_prefix_disp != -1)
5823 i.tm.operand_types[addr_prefix_disp]
5824 = operand_types[addr_prefix_disp];
5825
29b0f896
AM		 5826 if (found_reverse_match)
5827 {
5828 /* If we found a reverse match we must alter the opcode
5829 direction bit. found_reverse_match holds bits to change
5830 (different for int & float insns). */
5831
5832 i.tm.base_opcode ^= found_reverse_match;
5833
539e75ad
L		 5834 i.tm.operand_types[0] = operand_types[1];
5835 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5836 }
5837
fa99fab2 5838 return t;
29b0f896
AM		 5839}
5840
5841static int
e3bb37b5 5842check_string (void)
29b0f896 5843{
40fb9820
L		 5844 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5845 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5846 {
5847 if (i.seg[0] != NULL && i.seg[0] != &es)
5848 {
a87af027 5849 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5850 i.tm.name,
a87af027
JB		 5851 mem_op + 1,
5852 register_prefix);
29b0f896
AM		 5853 return 0;
5854 }
5855 /* There's only ever one segment override allowed per instruction.
5856 This instruction possibly has a legal segment override on the
5857 second operand, so copy the segment to where non-string
5858 instructions store it, allowing common code. */
5859 i.seg[0] = i.seg[1];
5860 }
40fb9820 5861 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5862 {
5863 if (i.seg[1] != NULL && i.seg[1] != &es)
5864 {
a87af027 5865 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5866 i.tm.name,
a87af027
JB		 5867 mem_op + 2,
5868 register_prefix);
29b0f896
AM		 5869 return 0;
5870 }
5871 }
5872 return 1;
5873}
5874
5875static int
543613e9 5876process_suffix (void)
29b0f896
AM		 5877{
5878 /* If matched instruction specifies an explicit instruction mnemonic
5879 suffix, use it. */
40fb9820
L		 5880 if (i.tm.opcode_modifier.size16)
5881 i.suffix = WORD_MNEM_SUFFIX;
5882 else if (i.tm.opcode_modifier.size32)
5883 i.suffix = LONG_MNEM_SUFFIX;
5884 else if (i.tm.opcode_modifier.size64)
5885 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5886 else if (i.reg_operands)
5887 {
5888 /* If there's no instruction mnemonic suffix we try to invent one
5889 based on register operands. */
5890 if (!i.suffix)
5891 {
5892 /* We take i.suffix from the last register operand specified,
5893 Destination register type is more significant than source
381d071f
L		 5894 register type. crc32 in SSE4.2 prefers source register
5895 type. */
5896 if (i.tm.base_opcode == 0xf20f38f1)
5897 {
dc821c5f 5898 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5899 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5900 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5901 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5902 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5903 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5904 }
9344ff29 5905 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5906 {
dc821c5f 5907 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5908 i.suffix = BYTE_MNEM_SUFFIX;
5909 }
381d071f
L		 5910
5911 if (!i.suffix)
5912 {
5913 int op;
5914
20592a94
L		 5915 if (i.tm.base_opcode == 0xf20f38f1
5916 || i.tm.base_opcode == 0xf20f38f0)
5917 {
5918 /* We have to know the operand size for crc32. */
5919 as_bad (_("ambiguous memory operand size for `%s`"),
5920 i.tm.name);
5921 return 0;
5922 }
5923
381d071f 5924 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5925 if (!i.tm.operand_types[op].bitfield.inoutportreg
5926 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5927 {
8819ada6
JB		 5928 if (!i.types[op].bitfield.reg)
5929 continue;
5930 if (i.types[op].bitfield.byte)
5931 i.suffix = BYTE_MNEM_SUFFIX;
5932 else if (i.types[op].bitfield.word)
5933 i.suffix = WORD_MNEM_SUFFIX;
5934 else if (i.types[op].bitfield.dword)
5935 i.suffix = LONG_MNEM_SUFFIX;
5936 else if (i.types[op].bitfield.qword)
5937 i.suffix = QWORD_MNEM_SUFFIX;
5938 else
5939 continue;
5940 break;
381d071f
L		 5941 }
5942 }
29b0f896
AM		 5943 }
5944 else if (i.suffix == BYTE_MNEM_SUFFIX)
5945 {
2eb952a4
L		 5946 if (intel_syntax
5947 && i.tm.opcode_modifier.ignoresize
5948 && i.tm.opcode_modifier.no_bsuf)
5949 i.suffix = 0;
5950 else if (!check_byte_reg ())
29b0f896
AM		 5951 return 0;
5952 }
5953 else if (i.suffix == LONG_MNEM_SUFFIX)
5954 {
2eb952a4
L		 5955 if (intel_syntax
5956 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5957 && i.tm.opcode_modifier.no_lsuf
5958 && !i.tm.opcode_modifier.todword
5959 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5960 i.suffix = 0;
5961 else if (!check_long_reg ())
29b0f896
AM		 5962 return 0;
5963 }
5964 else if (i.suffix == QWORD_MNEM_SUFFIX)
5965 {
955e1e6a
L		 5966 if (intel_syntax
5967 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5968 && i.tm.opcode_modifier.no_qsuf
5969 && !i.tm.opcode_modifier.todword
5970 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5971 i.suffix = 0;
5972 else if (!check_qword_reg ())
29b0f896
AM		 5973 return 0;
5974 }
5975 else if (i.suffix == WORD_MNEM_SUFFIX)
5976 {
2eb952a4
L		 5977 if (intel_syntax
5978 && i.tm.opcode_modifier.ignoresize
5979 && i.tm.opcode_modifier.no_wsuf)
5980 i.suffix = 0;
5981 else if (!check_word_reg ())
29b0f896
AM		 5982 return 0;
5983 }
40fb9820 5984 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5985 /* Do nothing if the instruction is going to ignore the prefix. */
5986 ;
5987 else
5988 abort ();
5989 }
40fb9820 5990 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5991 && !i.suffix
5992 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5993 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5994 {
5995 i.suffix = stackop_size;
5996 }
9306ca4a
JB		 5997 else if (intel_syntax
5998 && !i.suffix
40fb9820
L		 5999 && (i.tm.operand_types[0].bitfield.jumpabsolute
6000 || i.tm.opcode_modifier.jumpbyte
6001 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 6002 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6003 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 6004 {
6005 switch (flag_code)
6006 {
6007 case CODE_64BIT:
40fb9820 6008 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 6009 {
6010 i.suffix = QWORD_MNEM_SUFFIX;
6011 break;
6012 }
1a0670f3 6013 /* Fall through. */
9306ca4a 6014 case CODE_32BIT:
40fb9820 6015 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 6016 i.suffix = LONG_MNEM_SUFFIX;
6017 break;
6018 case CODE_16BIT:
40fb9820 6019 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 6020 i.suffix = WORD_MNEM_SUFFIX;
6021 break;
6022 }
6023 }
252b5132 6024
9306ca4a 6025 if (!i.suffix)
29b0f896 6026 {
9306ca4a
JB		 6027 if (!intel_syntax)
6028 {
40fb9820 6029 if (i.tm.opcode_modifier.w)
9306ca4a 6030 {
4eed87de
AM		 6031 as_bad (_("no instruction mnemonic suffix given and "
6032 "no register operands; can't size instruction"));
9306ca4a
JB		 6033 return 0;
6034 }
6035 }
6036 else
6037 {
40fb9820 6038 unsigned int suffixes;
7ab9ffdd 6039
40fb9820
L		 6040 suffixes = !i.tm.opcode_modifier.no_bsuf;
6041 if (!i.tm.opcode_modifier.no_wsuf)
6042 suffixes |= 1 << 1;
6043 if (!i.tm.opcode_modifier.no_lsuf)
6044 suffixes |= 1 << 2;
fc4adea1 6045 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 6046 suffixes |= 1 << 3;
6047 if (!i.tm.opcode_modifier.no_ssuf)
6048 suffixes |= 1 << 4;
c2b9da16 6049 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 6050 suffixes |= 1 << 5;
6051
6052 /* There are more than suffix matches. */
6053 if (i.tm.opcode_modifier.w
9306ca4a 6054 || ((suffixes & (suffixes - 1))
40fb9820
L		 6055 && !i.tm.opcode_modifier.defaultsize
6056 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 6057 {
6058 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6059 return 0;
6060 }
6061 }
29b0f896 6062 }
252b5132 6063
d2224064
JB		 6064 /* Change the opcode based on the operand size given by i.suffix. */
6065 switch (i.suffix)
29b0f896 6066 {
d2224064
JB		 6067 /* Size floating point instruction. */
6068 case LONG_MNEM_SUFFIX:
6069 if (i.tm.opcode_modifier.floatmf)
6070 {
6071 i.tm.base_opcode ^= 4;
6072 break;
6073 }
6074 /* fall through */
6075 case WORD_MNEM_SUFFIX:
6076 case QWORD_MNEM_SUFFIX:
29b0f896 6077 /* It's not a byte, select word/dword operation. */
40fb9820 6078 if (i.tm.opcode_modifier.w)
29b0f896 6079 {
40fb9820 6080 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 6081 i.tm.base_opcode |= 8;
6082 else
6083 i.tm.base_opcode |= 1;
6084 }
d2224064
JB		 6085 /* fall through */
6086 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 6087 /* Now select between word & dword operations via the operand
6088 size prefix, except for instructions that will ignore this
6089 prefix anyway. */
75c0a438
L		 6090 if (i.reg_operands > 0
6091 && i.types[0].bitfield.reg
6092 && i.tm.opcode_modifier.addrprefixopreg
6093 && (i.tm.opcode_modifier.immext
6094 || i.operands == 1))
cb712a9e 6095 {
ca61edf2
L		 6096 /* The address size override prefix changes the size of the
6097 first operand. */
40fb9820 6098 if ((flag_code == CODE_32BIT
75c0a438 6099 && i.op[0].regs->reg_type.bitfield.word)
40fb9820 6100 || (flag_code != CODE_32BIT
75c0a438 6101 && i.op[0].regs->reg_type.bitfield.dword))
cb712a9e
L		 6102 if (!add_prefix (ADDR_PREFIX_OPCODE))
6103 return 0;
6104 }
6105 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6106 && !i.tm.opcode_modifier.ignoresize
6107 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 6108 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6109 || (flag_code == CODE_64BIT
40fb9820 6110 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6111 {
6112 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6113
40fb9820 6114 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6115 prefix = ADDR_PREFIX_OPCODE;
252b5132 6116
29b0f896
AM		 6117 if (!add_prefix (prefix))
6118 return 0;
24eab124 6119 }
252b5132 6120
29b0f896
AM		 6121 /* Set mode64 for an operand. */
6122 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6123 && flag_code == CODE_64BIT
d2224064 6124 && !i.tm.opcode_modifier.norex64
46e883c5 6125 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6126 need rex64. */
6127 && ! (i.operands == 2
6128 && i.tm.base_opcode == 0x90
6129 && i.tm.extension_opcode == None
6130 && operand_type_equal (&i.types [0], &acc64)
6131 && operand_type_equal (&i.types [1], &acc64)))
6132 i.rex |= REX_W;
3e73aa7c 6133
d2224064 6134 break;
29b0f896 6135 }
7ecd2f8b 6136
c0a30a9f
L		 6137 if (i.reg_operands != 0
6138 && i.operands > 1
6139 && i.tm.opcode_modifier.addrprefixopreg
6140 && !i.tm.opcode_modifier.immext)
6141 {
6142 /* Check invalid register operand when the address size override
6143 prefix changes the size of register operands. */
6144 unsigned int op;
6145 enum { need_word, need_dword, need_qword } need;
6146
6147 if (flag_code == CODE_32BIT)
6148 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6149 else
6150 {
6151 if (i.prefix[ADDR_PREFIX])
6152 need = need_dword;
6153 else
6154 need = flag_code == CODE_64BIT ? need_qword : need_word;
6155 }
6156
6157 for (op = 0; op < i.operands; op++)
6158 if (i.types[op].bitfield.reg
6159 && ((need == need_word
6160 && !i.op[op].regs->reg_type.bitfield.word)
6161 || (need == need_dword
6162 && !i.op[op].regs->reg_type.bitfield.dword)
6163 || (need == need_qword
6164 && !i.op[op].regs->reg_type.bitfield.qword)))
6165 {
6166 as_bad (_("invalid register operand size for `%s'"),
6167 i.tm.name);
6168 return 0;
6169 }
6170 }
6171
29b0f896
AM		 6172 return 1;
6173}
3e73aa7c 6174
29b0f896 6175static int
543613e9 6176check_byte_reg (void)
29b0f896
AM		 6177{
6178 int op;
543613e9 6179
29b0f896
AM		 6180 for (op = i.operands; --op >= 0;)
6181 {
dc821c5f
JB		 6182 /* Skip non-register operands. */
6183 if (!i.types[op].bitfield.reg)
6184 continue;
6185
29b0f896
AM		 6186 /* If this is an eight bit register, it's OK. If it's the 16 or
6187 32 bit version of an eight bit register, we will just use the
6188 low portion, and that's OK too. */
dc821c5f 6189 if (i.types[op].bitfield.byte)
29b0f896
AM		 6190 continue;
6191
5a819eb9
JB		 6192 /* I/O port address operands are OK too. */
6193 if (i.tm.operand_types[op].bitfield.inoutportreg)
6194 continue;
6195
9344ff29
L		 6196 /* crc32 doesn't generate this warning. */
6197 if (i.tm.base_opcode == 0xf20f38f0)
6198 continue;
6199
dc821c5f
JB		 6200 if ((i.types[op].bitfield.word
6201 || i.types[op].bitfield.dword
6202 || i.types[op].bitfield.qword)
5a819eb9
JB		 6203 && i.op[op].regs->reg_num < 4
6204 /* Prohibit these changes in 64bit mode, since the lowering
6205 would be more complicated. */
6206 && flag_code != CODE_64BIT)
29b0f896 6207 {
29b0f896 6208#if REGISTER_WARNINGS
5a819eb9 6209 if (!quiet_warnings)
a540244d
L		 6210 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6211 register_prefix,
dc821c5f 6212 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6213 ? REGNAM_AL - REGNAM_AX
6214 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6215 register_prefix,
29b0f896
AM		 6216 i.op[op].regs->reg_name,
6217 i.suffix);
6218#endif
6219 continue;
6220 }
6221 /* Any other register is bad. */
dc821c5f 6222 if (i.types[op].bitfield.reg
40fb9820 6223 || i.types[op].bitfield.regmmx
1b54b8d7 6224 || i.types[op].bitfield.regsimd
40fb9820
L		 6225 || i.types[op].bitfield.sreg2
6226 || i.types[op].bitfield.sreg3
6227 || i.types[op].bitfield.control
6228 || i.types[op].bitfield.debug
ca0d63fe 6229 || i.types[op].bitfield.test)
29b0f896 6230 {
a540244d
L		 6231 as_bad (_("`%s%s' not allowed with `%s%c'"),
6232 register_prefix,
29b0f896
AM		 6233 i.op[op].regs->reg_name,
6234 i.tm.name,
6235 i.suffix);
6236 return 0;
6237 }
6238 }
6239 return 1;
6240}
6241
6242static int
e3bb37b5 6243check_long_reg (void)
29b0f896
AM		 6244{
6245 int op;
6246
6247 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6248 /* Skip non-register operands. */
6249 if (!i.types[op].bitfield.reg)
6250 continue;
29b0f896
AM		 6251 /* Reject eight bit registers, except where the template requires
6252 them. (eg. movzb) */
dc821c5f
JB		 6253 else if (i.types[op].bitfield.byte
6254 && (i.tm.operand_types[op].bitfield.reg
6255 || i.tm.operand_types[op].bitfield.acc)
6256 && (i.tm.operand_types[op].bitfield.word
6257 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6258 {
a540244d
L		 6259 as_bad (_("`%s%s' not allowed with `%s%c'"),
6260 register_prefix,
29b0f896
AM		 6261 i.op[op].regs->reg_name,
6262 i.tm.name,
6263 i.suffix);
6264 return 0;
6265 }
e4630f71 6266 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6267 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6268 && i.types[op].bitfield.word
6269 && (i.tm.operand_types[op].bitfield.reg
6270 || i.tm.operand_types[op].bitfield.acc)
6271 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6272 {
6273 /* Prohibit these changes in the 64bit mode, since the
6274 lowering is more complicated. */
6275 if (flag_code == CODE_64BIT)
252b5132 6276 {
2b5d6a91 6277 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6278 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6279 i.suffix);
6280 return 0;
252b5132 6281 }
29b0f896 6282#if REGISTER_WARNINGS
cecf1424
JB		 6283 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6284 register_prefix,
6285 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6286 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6287#endif
252b5132 6288 }
e4630f71 6289 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6290 else if (i.types[op].bitfield.qword
6291 && (i.tm.operand_types[op].bitfield.reg
6292 || i.tm.operand_types[op].bitfield.acc)
6293 && i.tm.operand_types[op].bitfield.dword)
252b5132 6294 {
34828aad 6295 if (intel_syntax
ca61edf2 6296 && i.tm.opcode_modifier.toqword
1b54b8d7 6297 && !i.types[0].bitfield.regsimd)
34828aad 6298 {
ca61edf2 6299 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6300 i.suffix = QWORD_MNEM_SUFFIX;
6301 }
6302 else
6303 {
2b5d6a91 6304 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6305 register_prefix, i.op[op].regs->reg_name,
6306 i.suffix);
6307 return 0;
6308 }
29b0f896
AM		 6309 }
6310 return 1;
6311}
252b5132 6312
29b0f896 6313static int
e3bb37b5 6314check_qword_reg (void)
29b0f896
AM		 6315{
6316 int op;
252b5132 6317
29b0f896 6318 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6319 /* Skip non-register operands. */
6320 if (!i.types[op].bitfield.reg)
6321 continue;
29b0f896
AM		 6322 /* Reject eight bit registers, except where the template requires
6323 them. (eg. movzb) */
dc821c5f
JB		 6324 else if (i.types[op].bitfield.byte
6325 && (i.tm.operand_types[op].bitfield.reg
6326 || i.tm.operand_types[op].bitfield.acc)
6327 && (i.tm.operand_types[op].bitfield.word
6328 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6329 {
a540244d
L		 6330 as_bad (_("`%s%s' not allowed with `%s%c'"),
6331 register_prefix,
29b0f896
AM		 6332 i.op[op].regs->reg_name,
6333 i.tm.name,
6334 i.suffix);
6335 return 0;
6336 }
e4630f71 6337 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6338 else if ((i.types[op].bitfield.word
6339 || i.types[op].bitfield.dword)
6340 && (i.tm.operand_types[op].bitfield.reg
6341 || i.tm.operand_types[op].bitfield.acc)
6342 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6343 {
6344 /* Prohibit these changes in the 64bit mode, since the
6345 lowering is more complicated. */
34828aad 6346 if (intel_syntax
ca61edf2 6347 && i.tm.opcode_modifier.todword
1b54b8d7 6348 && !i.types[0].bitfield.regsimd)
34828aad 6349 {
ca61edf2 6350 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6351 i.suffix = LONG_MNEM_SUFFIX;
6352 }
6353 else
6354 {
2b5d6a91 6355 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6356 register_prefix, i.op[op].regs->reg_name,
6357 i.suffix);
6358 return 0;
6359 }
252b5132 6360 }
29b0f896
AM		 6361 return 1;
6362}
252b5132 6363
29b0f896 6364static int
e3bb37b5 6365check_word_reg (void)
29b0f896
AM		 6366{
6367 int op;
6368 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6369 /* Skip non-register operands. */
6370 if (!i.types[op].bitfield.reg)
6371 continue;
29b0f896
AM		 6372 /* Reject eight bit registers, except where the template requires
6373 them. (eg. movzb) */
dc821c5f
JB		 6374 else if (i.types[op].bitfield.byte
6375 && (i.tm.operand_types[op].bitfield.reg
6376 || i.tm.operand_types[op].bitfield.acc)
6377 && (i.tm.operand_types[op].bitfield.word
6378 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6379 {
a540244d
L		 6380 as_bad (_("`%s%s' not allowed with `%s%c'"),
6381 register_prefix,
29b0f896
AM		 6382 i.op[op].regs->reg_name,
6383 i.tm.name,
6384 i.suffix);
6385 return 0;
6386 }
e4630f71 6387 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6388 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6389 && (i.types[op].bitfield.dword
6390 || i.types[op].bitfield.qword)
6391 && (i.tm.operand_types[op].bitfield.reg
6392 || i.tm.operand_types[op].bitfield.acc)
6393 && i.tm.operand_types[op].bitfield.word)
252b5132 6394 {
29b0f896
AM		 6395 /* Prohibit these changes in the 64bit mode, since the
6396 lowering is more complicated. */
6397 if (flag_code == CODE_64BIT)
252b5132 6398 {
2b5d6a91 6399 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6400 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6401 i.suffix);
6402 return 0;
252b5132 6403 }
29b0f896 6404#if REGISTER_WARNINGS
cecf1424
JB		 6405 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6406 register_prefix,
6407 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6408 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6409#endif
6410 }
6411 return 1;
6412}
252b5132 6413
29b0f896 6414static int
40fb9820 6415update_imm (unsigned int j)
29b0f896 6416{
bc0844ae 6417 i386_operand_type overlap = i.types[j];
40fb9820
L		 6418 if ((overlap.bitfield.imm8
6419 || overlap.bitfield.imm8s
6420 || overlap.bitfield.imm16
6421 || overlap.bitfield.imm32
6422 || overlap.bitfield.imm32s
6423 || overlap.bitfield.imm64)
0dfbf9d7
L		 6424 && !operand_type_equal (&overlap, &imm8)
6425 && !operand_type_equal (&overlap, &imm8s)
6426 && !operand_type_equal (&overlap, &imm16)
6427 && !operand_type_equal (&overlap, &imm32)
6428 && !operand_type_equal (&overlap, &imm32s)
6429 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6430 {
6431 if (i.suffix)
6432 {
40fb9820
L		 6433 i386_operand_type temp;
6434
0dfbf9d7 6435 operand_type_set (&temp, 0);
7ab9ffdd 6436 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6437 {
6438 temp.bitfield.imm8 = overlap.bitfield.imm8;
6439 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6440 }
6441 else if (i.suffix == WORD_MNEM_SUFFIX)
6442 temp.bitfield.imm16 = overlap.bitfield.imm16;
6443 else if (i.suffix == QWORD_MNEM_SUFFIX)
6444 {
6445 temp.bitfield.imm64 = overlap.bitfield.imm64;
6446 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6447 }
6448 else
6449 temp.bitfield.imm32 = overlap.bitfield.imm32;
6450 overlap = temp;
29b0f896 6451 }
0dfbf9d7
L		 6452 else if (operand_type_equal (&overlap, &imm16_32_32s)
6453 || operand_type_equal (&overlap, &imm16_32)
6454 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6455 {
40fb9820 6456 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6457 overlap = imm16;
40fb9820 6458 else
65da13b5 6459 overlap = imm32s;
29b0f896 6460 }
0dfbf9d7
L		 6461 if (!operand_type_equal (&overlap, &imm8)
6462 && !operand_type_equal (&overlap, &imm8s)
6463 && !operand_type_equal (&overlap, &imm16)
6464 && !operand_type_equal (&overlap, &imm32)
6465 && !operand_type_equal (&overlap, &imm32s)
6466 && !operand_type_equal (&overlap, &imm64))
29b0f896 6467 {
4eed87de
AM		 6468 as_bad (_("no instruction mnemonic suffix given; "
6469 "can't determine immediate size"));
29b0f896
AM		 6470 return 0;
6471 }
6472 }
40fb9820 6473 i.types[j] = overlap;
29b0f896 6474
40fb9820
L		 6475 return 1;
6476}
6477
6478static int
6479finalize_imm (void)
6480{
bc0844ae 6481 unsigned int j, n;
29b0f896 6482
bc0844ae
L		 6483 /* Update the first 2 immediate operands. */
6484 n = i.operands > 2 ? 2 : i.operands;
6485 if (n)
6486 {
6487 for (j = 0; j < n; j++)
6488 if (update_imm (j) == 0)
6489 return 0;
40fb9820 6490
bc0844ae
L		 6491 /* The 3rd operand can't be immediate operand. */
6492 gas_assert (operand_type_check (i.types[2], imm) == 0);
6493 }
29b0f896
AM		 6494
6495 return 1;
6496}
6497
6498static int
e3bb37b5 6499process_operands (void)
29b0f896
AM		 6500{
6501 /* Default segment register this instruction will use for memory
6502 accesses. 0 means unknown. This is only for optimizing out
6503 unnecessary segment overrides. */
6504 const seg_entry *default_seg = 0;
6505
2426c15f 6506 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6507 {
91d6fa6a
NC		 6508 unsigned int dupl = i.operands;
6509 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6510 unsigned int j;
6511
c0f3af97 6512 /* The destination must be an xmm register. */
9c2799c2 6513 gas_assert (i.reg_operands
91d6fa6a 6514 && MAX_OPERANDS > dupl
7ab9ffdd 6515 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6516
1b54b8d7
JB		 6517 if (i.tm.operand_types[0].bitfield.acc
6518 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6519 {
8cd7925b 6520 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6521 {
6522 /* Keep xmm0 for instructions with VEX prefix and 3
6523 sources. */
1b54b8d7
JB		 6524 i.tm.operand_types[0].bitfield.acc = 0;
6525 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6526 goto duplicate;
6527 }
e2ec9d29 6528 else
c0f3af97
L		 6529 {
6530 /* We remove the first xmm0 and keep the number of
6531 operands unchanged, which in fact duplicates the
6532 destination. */
6533 for (j = 1; j < i.operands; j++)
6534 {
6535 i.op[j - 1] = i.op[j];
6536 i.types[j - 1] = i.types[j];
6537 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6538 }
6539 }
6540 }
6541 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6542 {
91d6fa6a 6543 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6544 && (i.tm.opcode_modifier.vexsources
6545 == VEX3SOURCES));
c0f3af97
L		 6546
6547 /* Add the implicit xmm0 for instructions with VEX prefix
6548 and 3 sources. */
6549 for (j = i.operands; j > 0; j--)
6550 {
6551 i.op[j] = i.op[j - 1];
6552 i.types[j] = i.types[j - 1];
6553 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6554 }
6555 i.op[0].regs
6556 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6557 i.types[0] = regxmm;
c0f3af97
L		 6558 i.tm.operand_types[0] = regxmm;
6559
6560 i.operands += 2;
6561 i.reg_operands += 2;
6562 i.tm.operands += 2;
6563
91d6fa6a 6564 dupl++;
c0f3af97 6565 dest++;
91d6fa6a
NC		 6566 i.op[dupl] = i.op[dest];
6567 i.types[dupl] = i.types[dest];
6568 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6569 }
c0f3af97
L		 6570 else
6571 {
6572duplicate:
6573 i.operands++;
6574 i.reg_operands++;
6575 i.tm.operands++;
6576
91d6fa6a
NC		 6577 i.op[dupl] = i.op[dest];
6578 i.types[dupl] = i.types[dest];
6579 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6580 }
6581
6582 if (i.tm.opcode_modifier.immext)
6583 process_immext ();
6584 }
1b54b8d7
JB		 6585 else if (i.tm.operand_types[0].bitfield.acc
6586 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6587 {
6588 unsigned int j;
6589
9fcfb3d7
L		 6590 for (j = 1; j < i.operands; j++)
6591 {
6592 i.op[j - 1] = i.op[j];
6593 i.types[j - 1] = i.types[j];
6594
6595 /* We need to adjust fields in i.tm since they are used by
6596 build_modrm_byte. */
6597 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6598 }
6599
e2ec9d29
L		 6600 i.operands--;
6601 i.reg_operands--;
e2ec9d29
L		 6602 i.tm.operands--;
6603 }
920d2ddc
IT		 6604 else if (i.tm.opcode_modifier.implicitquadgroup)
6605 {
a477a8c4
JB		 6606 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6607
920d2ddc 6608 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6609 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6610 regnum = register_number (i.op[1].regs);
6611 first_reg_in_group = regnum & ~3;
6612 last_reg_in_group = first_reg_in_group + 3;
6613 if (regnum != first_reg_in_group)
6614 as_warn (_("source register `%s%s' implicitly denotes"
6615 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6616 register_prefix, i.op[1].regs->reg_name,
6617 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6618 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6619 i.tm.name);
6620 }
e2ec9d29
L		 6621 else if (i.tm.opcode_modifier.regkludge)
6622 {
6623 /* The imul $imm, %reg instruction is converted into
6624 imul $imm, %reg, %reg, and the clr %reg instruction
6625 is converted into xor %reg, %reg. */
6626
6627 unsigned int first_reg_op;
6628
6629 if (operand_type_check (i.types[0], reg))
6630 first_reg_op = 0;
6631 else
6632 first_reg_op = 1;
6633 /* Pretend we saw the extra register operand. */
9c2799c2 6634 gas_assert (i.reg_operands == 1
7ab9ffdd 6635 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6636 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6637 i.types[first_reg_op + 1] = i.types[first_reg_op];
6638 i.operands++;
6639 i.reg_operands++;
29b0f896
AM		 6640 }
6641
40fb9820 6642 if (i.tm.opcode_modifier.shortform)
29b0f896 6643 {
40fb9820
L		 6644 if (i.types[0].bitfield.sreg2
6645 || i.types[0].bitfield.sreg3)
29b0f896 6646 {
4eed87de
AM		 6647 if (i.tm.base_opcode == POP_SEG_SHORT
6648 && i.op[0].regs->reg_num == 1)
29b0f896 6649 {
a87af027 6650 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6651 return 0;
29b0f896 6652 }
4eed87de
AM		 6653 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6654 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6655 i.rex |= REX_B;
4eed87de
AM		 6656 }
6657 else
6658 {
7ab9ffdd 6659 /* The register or float register operand is in operand
85f10a01 6660 0 or 1. */
40fb9820 6661 unsigned int op;
7ab9ffdd 6662
ca0d63fe 6663 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6664 || operand_type_check (i.types[0], reg))
6665 op = 0;
6666 else
6667 op = 1;
4eed87de
AM		 6668 /* Register goes in low 3 bits of opcode. */
6669 i.tm.base_opcode |= i.op[op].regs->reg_num;
6670 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6671 i.rex |= REX_B;
40fb9820 6672 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6673 {
4eed87de
AM		 6674 /* Warn about some common errors, but press on regardless.
6675 The first case can be generated by gcc (<= 2.8.1). */
6676 if (i.operands == 2)
6677 {
6678 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6679 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6680 register_prefix, i.op[!intel_syntax].regs->reg_name,
6681 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6682 }
6683 else
6684 {
6685 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6686 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6687 register_prefix, i.op[0].regs->reg_name);
4eed87de 6688 }
29b0f896
AM		 6689 }
6690 }
6691 }
40fb9820 6692 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6693 {
6694 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6695 must be put into the modrm byte). Now, we make the modrm and
6696 index base bytes based on all the info we've collected. */
29b0f896
AM		 6697
6698 default_seg = build_modrm_byte ();
6699 }
8a2ed489 6700 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6701 {
6702 default_seg = &ds;
6703 }
40fb9820 6704 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6705 {
6706 /* For the string instructions that allow a segment override
6707 on one of their operands, the default segment is ds. */
6708 default_seg = &ds;
6709 }
6710
75178d9d
L		 6711 if (i.tm.base_opcode == 0x8d /* lea */
6712 && i.seg[0]
6713 && !quiet_warnings)
30123838 6714 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6715
6716 /* If a segment was explicitly specified, and the specified segment
6717 is not the default, use an opcode prefix to select it. If we
6718 never figured out what the default segment is, then default_seg
6719 will be zero at this point, and the specified segment prefix will
6720 always be used. */
29b0f896
AM		 6721 if ((i.seg[0]) && (i.seg[0] != default_seg))
6722 {
6723 if (!add_prefix (i.seg[0]->seg_prefix))
6724 return 0;
6725 }
6726 return 1;
6727}
6728
6729static const seg_entry *
e3bb37b5 6730build_modrm_byte (void)
29b0f896
AM		 6731{
6732 const seg_entry *default_seg = 0;
c0f3af97 6733 unsigned int source, dest;
8cd7925b 6734 int vex_3_sources;
c0f3af97 6735
8cd7925b 6736 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6737 if (vex_3_sources)
6738 {
91d6fa6a 6739 unsigned int nds, reg_slot;
4c2c6516 6740 expressionS *exp;
c0f3af97 6741
6b8d3588 6742 dest = i.operands - 1;
c0f3af97 6743 nds = dest - 1;
922d8de8 6744
a683cc34 6745 /* There are 2 kinds of instructions:
bed3d976
JB		 6746 1. 5 operands: 4 register operands or 3 register operands
6747 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6748 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 6749 ZMM register.
bed3d976 6750 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 6751 plus 1 memory operand, with VexXDS. */
922d8de8 6752 gas_assert ((i.reg_operands == 4
bed3d976
JB		 6753 || (i.reg_operands == 3 && i.mem_operands == 1))
6754 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 6755 && i.tm.opcode_modifier.vexw
6756 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 6757
48db9223
JB		 6758 /* If VexW1 is set, the first non-immediate operand is the source and
6759 the second non-immediate one is encoded in the immediate operand. */
6760 if (i.tm.opcode_modifier.vexw == VEXW1)
6761 {
6762 source = i.imm_operands;
6763 reg_slot = i.imm_operands + 1;
6764 }
6765 else
6766 {
6767 source = i.imm_operands + 1;
6768 reg_slot = i.imm_operands;
6769 }
6770
a683cc34 6771 if (i.imm_operands == 0)
bed3d976
JB		 6772 {
6773 /* When there is no immediate operand, generate an 8bit
6774 immediate operand to encode the first operand. */
6775 exp = &im_expressions[i.imm_operands++];
6776 i.op[i.operands].imms = exp;
6777 i.types[i.operands] = imm8;
6778 i.operands++;
6779
6780 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6781 exp->X_op = O_constant;
6782 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6783 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6784 }
922d8de8 6785 else
bed3d976
JB		 6786 {
6787 unsigned int imm_slot;
a683cc34 6788
2f1bada2
JB		 6789 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6790
bed3d976
JB		 6791 if (i.tm.opcode_modifier.immext)
6792 {
6793 /* When ImmExt is set, the immediate byte is the last
6794 operand. */
6795 imm_slot = i.operands - 1;
6796 source--;
6797 reg_slot--;
6798 }
6799 else
6800 {
6801 imm_slot = 0;
6802
6803 /* Turn on Imm8 so that output_imm will generate it. */
6804 i.types[imm_slot].bitfield.imm8 = 1;
6805 }
6806
6807 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6808 i.op[imm_slot].imms->X_add_number
6809 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6810 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 6811 }
a683cc34 6812
10c17abd 6813 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6814 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6815 }
6816 else
6817 source = dest = 0;
29b0f896
AM		 6818
6819 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6820 implicit registers do not count. If there are 3 register
6821 operands, it must be a instruction with VexNDS. For a
6822 instruction with VexNDD, the destination register is encoded
6823 in VEX prefix. If there are 4 register operands, it must be
6824 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6825 if (i.mem_operands == 0
6826 && ((i.reg_operands == 2
2426c15f 6827 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6828 || (i.reg_operands == 3
2426c15f 6829 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6830 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6831 {
cab737b9
L		 6832 switch (i.operands)
6833 {
6834 case 2:
6835 source = 0;
6836 break;
6837 case 3:
c81128dc
L		 6838 /* When there are 3 operands, one of them may be immediate,
6839 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6840 the first operand must be shift count register (cl) or it
6841 is an instruction with VexNDS. */
9c2799c2 6842 gas_assert (i.imm_operands == 1
7ab9ffdd 6843 || (i.imm_operands == 0
2426c15f 6844 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6845 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6846 if (operand_type_check (i.types[0], imm)
6847 || i.types[0].bitfield.shiftcount)
6848 source = 1;
6849 else
6850 source = 0;
cab737b9
L		 6851 break;
6852 case 4:
368d64cc
L		 6853 /* When there are 4 operands, the first two must be 8bit
6854 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6855 one.
6856
6857 For instructions with VexNDS, if the first operand
6858 an imm8, the source operand is the 2nd one. If the last
6859 operand is imm8, the source operand is the first one. */
9c2799c2 6860 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6861 && i.types[0].bitfield.imm8
6862 && i.types[1].bitfield.imm8)
2426c15f 6863 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6864 && i.imm_operands == 1
6865 && (i.types[0].bitfield.imm8
43234a1e
L		 6866 || i.types[i.operands - 1].bitfield.imm8
6867 || i.rounding)));
9f2670f2
L		 6868 if (i.imm_operands == 2)
6869 source = 2;
6870 else
c0f3af97
L		 6871 {
6872 if (i.types[0].bitfield.imm8)
6873 source = 1;
6874 else
6875 source = 0;
6876 }
c0f3af97
L		 6877 break;
6878 case 5:
e771e7c9 6879 if (is_evex_encoding (&i.tm))
43234a1e
L		 6880 {
6881 /* For EVEX instructions, when there are 5 operands, the
6882 first one must be immediate operand. If the second one
6883 is immediate operand, the source operand is the 3th
6884 one. If the last one is immediate operand, the source
6885 operand is the 2nd one. */
6886 gas_assert (i.imm_operands == 2
6887 && i.tm.opcode_modifier.sae
6888 && operand_type_check (i.types[0], imm));
6889 if (operand_type_check (i.types[1], imm))
6890 source = 2;
6891 else if (operand_type_check (i.types[4], imm))
6892 source = 1;
6893 else
6894 abort ();
6895 }
cab737b9
L		 6896 break;
6897 default:
6898 abort ();
6899 }
6900
c0f3af97
L		 6901 if (!vex_3_sources)
6902 {
6903 dest = source + 1;
6904
43234a1e
L		 6905 /* RC/SAE operand could be between DEST and SRC. That happens
6906 when one operand is GPR and the other one is XMM/YMM/ZMM
6907 register. */
6908 if (i.rounding && i.rounding->operand == (int) dest)
6909 dest++;
6910
2426c15f 6911 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6912 {
43234a1e 6913 /* For instructions with VexNDS, the register-only source
c5d0745b 6914 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6915 register. It is encoded in VEX prefix. We need to
6916 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6917
6918 i386_operand_type op;
6919 unsigned int vvvv;
6920
6921 /* Check register-only source operand when two source
6922 operands are swapped. */
6923 if (!i.tm.operand_types[source].bitfield.baseindex
6924 && i.tm.operand_types[dest].bitfield.baseindex)
6925 {
6926 vvvv = source;
6927 source = dest;
6928 }
6929 else
6930 vvvv = dest;
6931
6932 op = i.tm.operand_types[vvvv];
fa99fab2 6933 op.bitfield.regmem = 0;
c0f3af97 6934 if ((dest + 1) >= i.operands
dc821c5f
JB		 6935 || ((!op.bitfield.reg
6936 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6937 && !op.bitfield.regsimd
43234a1e 6938 && !operand_type_equal (&op, &regmask)))
c0f3af97 6939 abort ();
f12dc422 6940 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6941 dest++;
6942 }
6943 }
29b0f896
AM		 6944
6945 i.rm.mode = 3;
6946 /* One of the register operands will be encoded in the i.tm.reg
6947 field, the other in the combined i.tm.mode and i.tm.regmem
6948 fields. If no form of this instruction supports a memory
6949 destination operand, then we assume the source operand may
6950 sometimes be a memory operand and so we need to store the
6951 destination in the i.rm.reg field. */
40fb9820
L		 6952 if (!i.tm.operand_types[dest].bitfield.regmem
6953 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6954 {
6955 i.rm.reg = i.op[dest].regs->reg_num;
6956 i.rm.regmem = i.op[source].regs->reg_num;
6957 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6958 i.rex |= REX_R;
43234a1e
L		 6959 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6960 i.vrex |= REX_R;
29b0f896 6961 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6962 i.rex |= REX_B;
43234a1e
L		 6963 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6964 i.vrex |= REX_B;
29b0f896
AM		 6965 }
6966 else
6967 {
6968 i.rm.reg = i.op[source].regs->reg_num;
6969 i.rm.regmem = i.op[dest].regs->reg_num;
6970 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6971 i.rex |= REX_B;
43234a1e
L		 6972 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6973 i.vrex |= REX_B;
29b0f896 6974 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6975 i.rex |= REX_R;
43234a1e
L		 6976 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6977 i.vrex |= REX_R;
29b0f896 6978 }
e0c7f900 6979 if (flag_code != CODE_64BIT && (i.rex & REX_R))
c4a530c5 6980 {
e0c7f900 6981 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
c4a530c5 6982 abort ();
e0c7f900 6983 i.rex &= ~REX_R;
c4a530c5
JB		 6984 add_prefix (LOCK_PREFIX_OPCODE);
6985 }
29b0f896
AM		 6986 }
6987 else
6988 { /* If it's not 2 reg operands... */
c0f3af97
L		 6989 unsigned int mem;
6990
29b0f896
AM		 6991 if (i.mem_operands)
6992 {
6993 unsigned int fake_zero_displacement = 0;
99018f42 6994 unsigned int op;
4eed87de 6995
7ab9ffdd
L		 6996 for (op = 0; op < i.operands; op++)
6997 if (operand_type_check (i.types[op], anymem))
6998 break;
7ab9ffdd 6999 gas_assert (op < i.operands);
29b0f896 7000
6c30d220
L		 7001 if (i.tm.opcode_modifier.vecsib)
7002 {
7003 if (i.index_reg->reg_num == RegEiz
7004 || i.index_reg->reg_num == RegRiz)
7005 abort ();
7006
7007 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7008 if (!i.base_reg)
7009 {
7010 i.sib.base = NO_BASE_REGISTER;
7011 i.sib.scale = i.log2_scale_factor;
7012 i.types[op].bitfield.disp8 = 0;
7013 i.types[op].bitfield.disp16 = 0;
7014 i.types[op].bitfield.disp64 = 0;
43083a50 7015 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 7016 {
7017 /* Must be 32 bit */
7018 i.types[op].bitfield.disp32 = 1;
7019 i.types[op].bitfield.disp32s = 0;
7020 }
7021 else
7022 {
7023 i.types[op].bitfield.disp32 = 0;
7024 i.types[op].bitfield.disp32s = 1;
7025 }
7026 }
7027 i.sib.index = i.index_reg->reg_num;
7028 if ((i.index_reg->reg_flags & RegRex) != 0)
7029 i.rex |= REX_X;
43234a1e
L		 7030 if ((i.index_reg->reg_flags & RegVRex) != 0)
7031 i.vrex |= REX_X;
6c30d220
L		 7032 }
7033
29b0f896
AM		 7034 default_seg = &ds;
7035
7036 if (i.base_reg == 0)
7037 {
7038 i.rm.mode = 0;
7039 if (!i.disp_operands)
9bb129e8 7040 fake_zero_displacement = 1;
29b0f896
AM		 7041 if (i.index_reg == 0)
7042 {
73053c1f
JB		 7043 i386_operand_type newdisp;
7044
6c30d220 7045 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7046 /* Operand is just <disp> */
20f0a1fc 7047 if (flag_code == CODE_64BIT)
29b0f896
AM		 7048 {
7049 /* 64bit mode overwrites the 32bit absolute
7050 addressing by RIP relative addressing and
7051 absolute addressing is encoded by one of the
7052 redundant SIB forms. */
7053 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7054 i.sib.base = NO_BASE_REGISTER;
7055 i.sib.index = NO_INDEX_REGISTER;
73053c1f 7056 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 7057 }
fc225355
L		 7058 else if ((flag_code == CODE_16BIT)
7059 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 7060 {
7061 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 7062 newdisp = disp16;
20f0a1fc
NC		 7063 }
7064 else
7065 {
7066 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 7067 newdisp = disp32;
29b0f896 7068 }
73053c1f
JB		 7069 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7070 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 7071 }
6c30d220 7072 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7073 {
6c30d220 7074 /* !i.base_reg && i.index_reg */
db51cc60
L		 7075 if (i.index_reg->reg_num == RegEiz
7076 || i.index_reg->reg_num == RegRiz)
7077 i.sib.index = NO_INDEX_REGISTER;
7078 else
7079 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7080 i.sib.base = NO_BASE_REGISTER;
7081 i.sib.scale = i.log2_scale_factor;
7082 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 7083 i.types[op].bitfield.disp8 = 0;
7084 i.types[op].bitfield.disp16 = 0;
7085 i.types[op].bitfield.disp64 = 0;
43083a50 7086 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 7087 {
7088 /* Must be 32 bit */
7089 i.types[op].bitfield.disp32 = 1;
7090 i.types[op].bitfield.disp32s = 0;
7091 }
29b0f896 7092 else
40fb9820
L		 7093 {
7094 i.types[op].bitfield.disp32 = 0;
7095 i.types[op].bitfield.disp32s = 1;
7096 }
29b0f896 7097 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7098 i.rex |= REX_X;
29b0f896
AM		 7099 }
7100 }
7101 /* RIP addressing for 64bit mode. */
9a04903e
JB		 7102 else if (i.base_reg->reg_num == RegRip ||
7103 i.base_reg->reg_num == RegEip)
29b0f896 7104 {
6c30d220 7105 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7106 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 7107 i.types[op].bitfield.disp8 = 0;
7108 i.types[op].bitfield.disp16 = 0;
7109 i.types[op].bitfield.disp32 = 0;
7110 i.types[op].bitfield.disp32s = 1;
7111 i.types[op].bitfield.disp64 = 0;
71903a11 7112 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 7113 if (! i.disp_operands)
7114 fake_zero_displacement = 1;
29b0f896 7115 }
dc821c5f 7116 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 7117 {
6c30d220 7118 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7119 switch (i.base_reg->reg_num)
7120 {
7121 case 3: /* (%bx) */
7122 if (i.index_reg == 0)
7123 i.rm.regmem = 7;
7124 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7125 i.rm.regmem = i.index_reg->reg_num - 6;
7126 break;
7127 case 5: /* (%bp) */
7128 default_seg = &ss;
7129 if (i.index_reg == 0)
7130 {
7131 i.rm.regmem = 6;
40fb9820 7132 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7133 {
7134 /* fake (%bp) into 0(%bp) */
b5014f7a 7135 i.types[op].bitfield.disp8 = 1;
252b5132 7136 fake_zero_displacement = 1;
29b0f896
AM		 7137 }
7138 }
7139 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7140 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7141 break;
7142 default: /* (%si) -> 4 or (%di) -> 5 */
7143 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7144 }
7145 i.rm.mode = mode_from_disp_size (i.types[op]);
7146 }
7147 else /* i.base_reg and 32/64 bit mode */
7148 {
7149 if (flag_code == CODE_64BIT
40fb9820
L		 7150 && operand_type_check (i.types[op], disp))
7151 {
73053c1f
JB		 7152 i.types[op].bitfield.disp16 = 0;
7153 i.types[op].bitfield.disp64 = 0;
40fb9820 7154 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7155 {
7156 i.types[op].bitfield.disp32 = 0;
7157 i.types[op].bitfield.disp32s = 1;
7158 }
40fb9820 7159 else
73053c1f
JB		 7160 {
7161 i.types[op].bitfield.disp32 = 1;
7162 i.types[op].bitfield.disp32s = 0;
7163 }
40fb9820 7164 }
20f0a1fc 7165
6c30d220
L		 7166 if (!i.tm.opcode_modifier.vecsib)
7167 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7168 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7169 i.rex |= REX_B;
29b0f896
AM		 7170 i.sib.base = i.base_reg->reg_num;
7171 /* x86-64 ignores REX prefix bit here to avoid decoder
7172 complications. */
848930b2
JB		 7173 if (!(i.base_reg->reg_flags & RegRex)
7174 && (i.base_reg->reg_num == EBP_REG_NUM
7175 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7176 default_seg = &ss;
848930b2 7177 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7178 {
848930b2 7179 fake_zero_displacement = 1;
b5014f7a 7180 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7181 }
7182 i.sib.scale = i.log2_scale_factor;
7183 if (i.index_reg == 0)
7184 {
6c30d220 7185 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7186 /* <disp>(%esp) becomes two byte modrm with no index
7187 register. We've already stored the code for esp
7188 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7189 Any base register besides %esp will not use the
7190 extra modrm byte. */
7191 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7192 }
6c30d220 7193 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7194 {
db51cc60
L		 7195 if (i.index_reg->reg_num == RegEiz
7196 || i.index_reg->reg_num == RegRiz)
7197 i.sib.index = NO_INDEX_REGISTER;
7198 else
7199 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7200 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7201 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7202 i.rex |= REX_X;
29b0f896 7203 }
67a4f2b7
AO		 7204
7205 if (i.disp_operands
7206 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7207 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7208 i.rm.mode = 0;
7209 else
a501d77e
L		 7210 {
7211 if (!fake_zero_displacement
7212 && !i.disp_operands
7213 && i.disp_encoding)
7214 {
7215 fake_zero_displacement = 1;
7216 if (i.disp_encoding == disp_encoding_8bit)
7217 i.types[op].bitfield.disp8 = 1;
7218 else
7219 i.types[op].bitfield.disp32 = 1;
7220 }
7221 i.rm.mode = mode_from_disp_size (i.types[op]);
7222 }
29b0f896 7223 }
252b5132 7224
29b0f896
AM		 7225 if (fake_zero_displacement)
7226 {
7227 /* Fakes a zero displacement assuming that i.types[op]
7228 holds the correct displacement size. */
7229 expressionS *exp;
7230
9c2799c2 7231 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7232 exp = &disp_expressions[i.disp_operands++];
7233 i.op[op].disps = exp;
7234 exp->X_op = O_constant;
7235 exp->X_add_number = 0;
7236 exp->X_add_symbol = (symbolS *) 0;
7237 exp->X_op_symbol = (symbolS *) 0;
7238 }
c0f3af97
L		 7239
7240 mem = op;
29b0f896 7241 }
c0f3af97
L		 7242 else
7243 mem = ~0;
252b5132 7244
8c43a48b 7245 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7246 {
7247 if (operand_type_check (i.types[0], imm))
7248 i.vex.register_specifier = NULL;
7249 else
7250 {
7251 /* VEX.vvvv encodes one of the sources when the first
7252 operand is not an immediate. */
1ef99a7b 7253 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7254 i.vex.register_specifier = i.op[0].regs;
7255 else
7256 i.vex.register_specifier = i.op[1].regs;
7257 }
7258
7259 /* Destination is a XMM register encoded in the ModRM.reg
7260 and VEX.R bit. */
7261 i.rm.reg = i.op[2].regs->reg_num;
7262 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7263 i.rex |= REX_R;
7264
7265 /* ModRM.rm and VEX.B encodes the other source. */
7266 if (!i.mem_operands)
7267 {
7268 i.rm.mode = 3;
7269
1ef99a7b 7270 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7271 i.rm.regmem = i.op[1].regs->reg_num;
7272 else
7273 i.rm.regmem = i.op[0].regs->reg_num;
7274
7275 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7276 i.rex |= REX_B;
7277 }
7278 }
2426c15f 7279 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7280 {
7281 i.vex.register_specifier = i.op[2].regs;
7282 if (!i.mem_operands)
7283 {
7284 i.rm.mode = 3;
7285 i.rm.regmem = i.op[1].regs->reg_num;
7286 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7287 i.rex |= REX_B;
7288 }
7289 }
29b0f896
AM		 7290 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7291 (if any) based on i.tm.extension_opcode. Again, we must be
7292 careful to make sure that segment/control/debug/test/MMX
7293 registers are coded into the i.rm.reg field. */
f88c9eb0 7294 else if (i.reg_operands)
29b0f896 7295 {
99018f42 7296 unsigned int op;
7ab9ffdd
L		 7297 unsigned int vex_reg = ~0;
7298
7299 for (op = 0; op < i.operands; op++)
dc821c5f 7300 if (i.types[op].bitfield.reg
7ab9ffdd 7301 || i.types[op].bitfield.regmmx
1b54b8d7 7302 || i.types[op].bitfield.regsimd
7e8b059b 7303 || i.types[op].bitfield.regbnd
43234a1e 7304 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7305 || i.types[op].bitfield.sreg2
7306 || i.types[op].bitfield.sreg3
7307 || i.types[op].bitfield.control
7308 || i.types[op].bitfield.debug
7309 || i.types[op].bitfield.test)
7310 break;
c0209578 7311
7ab9ffdd
L		 7312 if (vex_3_sources)
7313 op = dest;
2426c15f 7314 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7315 {
7316 /* For instructions with VexNDS, the register-only
7317 source operand is encoded in VEX prefix. */
7318 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7319
7ab9ffdd 7320 if (op > mem)
c0f3af97 7321 {
7ab9ffdd
L		 7322 vex_reg = op++;
7323 gas_assert (op < i.operands);
c0f3af97
L		 7324 }
7325 else
c0f3af97 7326 {
f12dc422
L		 7327 /* Check register-only source operand when two source
7328 operands are swapped. */
7329 if (!i.tm.operand_types[op].bitfield.baseindex
7330 && i.tm.operand_types[op + 1].bitfield.baseindex)
7331 {
7332 vex_reg = op;
7333 op += 2;
7334 gas_assert (mem == (vex_reg + 1)
7335 && op < i.operands);
7336 }
7337 else
7338 {
7339 vex_reg = op + 1;
7340 gas_assert (vex_reg < i.operands);
7341 }
c0f3af97 7342 }
7ab9ffdd 7343 }
2426c15f 7344 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7345 {
f12dc422 7346 /* For instructions with VexNDD, the register destination
7ab9ffdd 7347 is encoded in VEX prefix. */
f12dc422
L		 7348 if (i.mem_operands == 0)
7349 {
7350 /* There is no memory operand. */
7351 gas_assert ((op + 2) == i.operands);
7352 vex_reg = op + 1;
7353 }
7354 else
8d63c93e 7355 {
ed438a93
JB		 7356 /* There are only 2 non-immediate operands. */
7357 gas_assert (op < i.imm_operands + 2
7358 && i.operands == i.imm_operands + 2);
7359 vex_reg = i.imm_operands + 1;
f12dc422 7360 }
7ab9ffdd
L		 7361 }
7362 else
7363 gas_assert (op < i.operands);
99018f42 7364
7ab9ffdd
L		 7365 if (vex_reg != (unsigned int) ~0)
7366 {
f12dc422 7367 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7368
dc821c5f
JB		 7369 if ((!type->bitfield.reg
7370 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7371 && !type->bitfield.regsimd
43234a1e 7372 && !operand_type_equal (type, &regmask))
7ab9ffdd 7373 abort ();
f88c9eb0 7374
7ab9ffdd
L		 7375 i.vex.register_specifier = i.op[vex_reg].regs;
7376 }
7377
1b9f0c97
L		 7378 /* Don't set OP operand twice. */
7379 if (vex_reg != op)
7ab9ffdd 7380 {
1b9f0c97
L		 7381 /* If there is an extension opcode to put here, the
7382 register number must be put into the regmem field. */
7383 if (i.tm.extension_opcode != None)
7384 {
7385 i.rm.regmem = i.op[op].regs->reg_num;
7386 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7387 i.rex |= REX_B;
43234a1e
L		 7388 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7389 i.vrex |= REX_B;
1b9f0c97
L		 7390 }
7391 else
7392 {
7393 i.rm.reg = i.op[op].regs->reg_num;
7394 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7395 i.rex |= REX_R;
43234a1e
L		 7396 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7397 i.vrex |= REX_R;
1b9f0c97 7398 }
7ab9ffdd 7399 }
252b5132 7400
29b0f896
AM		 7401 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7402 must set it to 3 to indicate this is a register operand
7403 in the regmem field. */
7404 if (!i.mem_operands)
7405 i.rm.mode = 3;
7406 }
252b5132 7407
29b0f896 7408 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7409 if (i.tm.extension_opcode != None)
29b0f896
AM		 7410 i.rm.reg = i.tm.extension_opcode;
7411 }
7412 return default_seg;
7413}
252b5132 7414
29b0f896 7415static void
e3bb37b5 7416output_branch (void)
29b0f896
AM		 7417{
7418 char *p;
f8a5c266 7419 int size;
29b0f896
AM		 7420 int code16;
7421 int prefix;
7422 relax_substateT subtype;
7423 symbolS *sym;
7424 offsetT off;
7425
f8a5c266 7426 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7427 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7428
7429 prefix = 0;
7430 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7431 {
29b0f896
AM		 7432 prefix = 1;
7433 i.prefixes -= 1;
7434 code16 ^= CODE16;
252b5132 7435 }
29b0f896
AM		 7436 /* Pentium4 branch hints. */
7437 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7438 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7439 {
29b0f896
AM		 7440 prefix++;
7441 i.prefixes--;
7442 }
7443 if (i.prefix[REX_PREFIX] != 0)
7444 {
7445 prefix++;
7446 i.prefixes--;
2f66722d
AM		 7447 }
7448
7e8b059b
L		 7449 /* BND prefixed jump. */
7450 if (i.prefix[BND_PREFIX] != 0)
7451 {
7452 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7453 i.prefixes -= 1;
7454 }
7455
29b0f896
AM		 7456 if (i.prefixes != 0 && !intel_syntax)
7457 as_warn (_("skipping prefixes on this instruction"));
7458
7459 /* It's always a symbol; End frag & setup for relax.
7460 Make sure there is enough room in this frag for the largest
7461 instruction we may generate in md_convert_frag. This is 2
7462 bytes for the opcode and room for the prefix and largest
7463 displacement. */
7464 frag_grow (prefix + 2 + 4);
7465 /* Prefix and 1 opcode byte go in fr_fix. */
7466 p = frag_more (prefix + 1);
7467 if (i.prefix[DATA_PREFIX] != 0)
7468 *p++ = DATA_PREFIX_OPCODE;
7469 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7470 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7471 *p++ = i.prefix[SEG_PREFIX];
7472 if (i.prefix[REX_PREFIX] != 0)
7473 *p++ = i.prefix[REX_PREFIX];
7474 *p = i.tm.base_opcode;
7475
7476 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7477 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7478 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7479 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7480 else
f8a5c266 7481 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7482 subtype |= code16;
3e73aa7c 7483
29b0f896
AM		 7484 sym = i.op[0].disps->X_add_symbol;
7485 off = i.op[0].disps->X_add_number;
3e73aa7c 7486
29b0f896
AM		 7487 if (i.op[0].disps->X_op != O_constant
7488 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7489 {
29b0f896
AM		 7490 /* Handle complex expressions. */
7491 sym = make_expr_symbol (i.op[0].disps);
7492 off = 0;
7493 }
3e73aa7c 7494
29b0f896
AM		 7495 /* 1 possible extra opcode + 4 byte displacement go in var part.
7496 Pass reloc in fr_var. */
d258b828 7497 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7498}
3e73aa7c 7499
bd7ab16b
L		 7500#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7501/* Return TRUE iff PLT32 relocation should be used for branching to
7502 symbol S. */
7503
7504static bfd_boolean
7505need_plt32_p (symbolS *s)
7506{
7507 /* PLT32 relocation is ELF only. */
7508 if (!IS_ELF)
7509 return FALSE;
7510
7511 /* Since there is no need to prepare for PLT branch on x86-64, we
7512 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7513 be used as a marker for 32-bit PC-relative branches. */
7514 if (!object_64bit)
7515 return FALSE;
7516
7517 /* Weak or undefined symbol need PLT32 relocation. */
7518 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7519 return TRUE;
7520
7521 /* Non-global symbol doesn't need PLT32 relocation. */
7522 if (! S_IS_EXTERNAL (s))
7523 return FALSE;
7524
7525 /* Other global symbols need PLT32 relocation. NB: Symbol with
7526 non-default visibilities are treated as normal global symbol
7527 so that PLT32 relocation can be used as a marker for 32-bit
7528 PC-relative branches. It is useful for linker relaxation. */
7529 return TRUE;
7530}
7531#endif
7532
29b0f896 7533static void
e3bb37b5 7534output_jump (void)
29b0f896
AM		 7535{
7536 char *p;
7537 int size;
3e02c1cc 7538 fixS *fixP;
bd7ab16b 7539 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7540
40fb9820 7541 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7542 {
7543 /* This is a loop or jecxz type instruction. */
7544 size = 1;
7545 if (i.prefix[ADDR_PREFIX] != 0)
7546 {
7547 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7548 i.prefixes -= 1;
7549 }
7550 /* Pentium4 branch hints. */
7551 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7552 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7553 {
7554 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7555 i.prefixes--;
3e73aa7c
JH		 7556 }
7557 }
29b0f896
AM		 7558 else
7559 {
7560 int code16;
3e73aa7c 7561
29b0f896
AM		 7562 code16 = 0;
7563 if (flag_code == CODE_16BIT)
7564 code16 = CODE16;
3e73aa7c 7565
29b0f896
AM		 7566 if (i.prefix[DATA_PREFIX] != 0)
7567 {
7568 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7569 i.prefixes -= 1;
7570 code16 ^= CODE16;
7571 }
252b5132 7572
29b0f896
AM		 7573 size = 4;
7574 if (code16)
7575 size = 2;
7576 }
9fcc94b6 7577
29b0f896
AM		 7578 if (i.prefix[REX_PREFIX] != 0)
7579 {
7580 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7581 i.prefixes -= 1;
7582 }
252b5132 7583
7e8b059b
L		 7584 /* BND prefixed jump. */
7585 if (i.prefix[BND_PREFIX] != 0)
7586 {
7587 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7588 i.prefixes -= 1;
7589 }
7590
29b0f896
AM		 7591 if (i.prefixes != 0 && !intel_syntax)
7592 as_warn (_("skipping prefixes on this instruction"));
e0890092 7593
42164a71
L		 7594 p = frag_more (i.tm.opcode_length + size);
7595 switch (i.tm.opcode_length)
7596 {
7597 case 2:
7598 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7599 /* Fall through. */
42164a71
L		 7600 case 1:
7601 *p++ = i.tm.base_opcode;
7602 break;
7603 default:
7604 abort ();
7605 }
e0890092 7606
bd7ab16b
L		 7607#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7608 if (size == 4
7609 && jump_reloc == NO_RELOC
7610 && need_plt32_p (i.op[0].disps->X_add_symbol))
7611 jump_reloc = BFD_RELOC_X86_64_PLT32;
7612#endif
7613
7614 jump_reloc = reloc (size, 1, 1, jump_reloc);
7615
3e02c1cc 7616 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7617 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7618
7619 /* All jumps handled here are signed, but don't use a signed limit
7620 check for 32 and 16 bit jumps as we want to allow wrap around at
7621 4G and 64k respectively. */
7622 if (size == 1)
7623 fixP->fx_signed = 1;
29b0f896 7624}
e0890092 7625
29b0f896 7626static void
e3bb37b5 7627output_interseg_jump (void)
29b0f896
AM		 7628{
7629 char *p;
7630 int size;
7631 int prefix;
7632 int code16;
252b5132 7633
29b0f896
AM		 7634 code16 = 0;
7635 if (flag_code == CODE_16BIT)
7636 code16 = CODE16;
a217f122 7637
29b0f896
AM		 7638 prefix = 0;
7639 if (i.prefix[DATA_PREFIX] != 0)
7640 {
7641 prefix = 1;
7642 i.prefixes -= 1;
7643 code16 ^= CODE16;
7644 }
7645 if (i.prefix[REX_PREFIX] != 0)
7646 {
7647 prefix++;
7648 i.prefixes -= 1;
7649 }
252b5132 7650
29b0f896
AM		 7651 size = 4;
7652 if (code16)
7653 size = 2;
252b5132 7654
29b0f896
AM		 7655 if (i.prefixes != 0 && !intel_syntax)
7656 as_warn (_("skipping prefixes on this instruction"));
252b5132 7657
29b0f896
AM		 7658 /* 1 opcode; 2 segment; offset */
7659 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7660
29b0f896
AM		 7661 if (i.prefix[DATA_PREFIX] != 0)
7662 *p++ = DATA_PREFIX_OPCODE;
252b5132 7663
29b0f896
AM		 7664 if (i.prefix[REX_PREFIX] != 0)
7665 *p++ = i.prefix[REX_PREFIX];
252b5132 7666
29b0f896
AM		 7667 *p++ = i.tm.base_opcode;
7668 if (i.op[1].imms->X_op == O_constant)
7669 {
7670 offsetT n = i.op[1].imms->X_add_number;
252b5132 7671
29b0f896
AM		 7672 if (size == 2
7673 && !fits_in_unsigned_word (n)
7674 && !fits_in_signed_word (n))
7675 {
7676 as_bad (_("16-bit jump out of range"));
7677 return;
7678 }
7679 md_number_to_chars (p, n, size);
7680 }
7681 else
7682 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7683 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7684 if (i.op[0].imms->X_op != O_constant)
7685 as_bad (_("can't handle non absolute segment in `%s'"),
7686 i.tm.name);
7687 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7688}
a217f122 7689
29b0f896 7690static void
e3bb37b5 7691output_insn (void)
29b0f896 7692{
2bbd9c25
JJ		 7693 fragS *insn_start_frag;
7694 offsetT insn_start_off;
7695
29b0f896
AM		 7696 /* Tie dwarf2 debug info to the address at the start of the insn.
7697 We can't do this after the insn has been output as the current
7698 frag may have been closed off. eg. by frag_var. */
7699 dwarf2_emit_insn (0);
7700
2bbd9c25
JJ		 7701 insn_start_frag = frag_now;
7702 insn_start_off = frag_now_fix ();
7703
29b0f896 7704 /* Output jumps. */
40fb9820 7705 if (i.tm.opcode_modifier.jump)
29b0f896 7706 output_branch ();
40fb9820
L		 7707 else if (i.tm.opcode_modifier.jumpbyte
7708 || i.tm.opcode_modifier.jumpdword)
29b0f896 7709 output_jump ();
40fb9820 7710 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7711 output_interseg_jump ();
7712 else
7713 {
7714 /* Output normal instructions here. */
7715 char *p;
7716 unsigned char *q;
47465058 7717 unsigned int j;
331d2d0d 7718 unsigned int prefix;
4dffcebc 7719
e4e00185
AS		 7720 if (avoid_fence
7721 && i.tm.base_opcode == 0xfae
7722 && i.operands == 1
7723 && i.imm_operands == 1
7724 && (i.op[0].imms->X_add_number == 0xe8
7725 || i.op[0].imms->X_add_number == 0xf0
7726 || i.op[0].imms->X_add_number == 0xf8))
7727 {
7728 /* Encode lfence, mfence, and sfence as
7729 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7730 offsetT val = 0x240483f0ULL;
7731 p = frag_more (5);
7732 md_number_to_chars (p, val, 5);
7733 return;
7734 }
7735
d022bddd
IT		 7736 /* Some processors fail on LOCK prefix. This options makes
7737 assembler ignore LOCK prefix and serves as a workaround. */
7738 if (omit_lock_prefix)
7739 {
7740 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7741 return;
7742 i.prefix[LOCK_PREFIX] = 0;
7743 }
7744
43234a1e
L		 7745 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7746 don't need the explicit prefix. */
7747 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7748 {
c0f3af97 7749 switch (i.tm.opcode_length)
bc4bd9ab 7750 {
c0f3af97
L		 7751 case 3:
7752 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7753 {
c0f3af97 7754 prefix = (i.tm.base_opcode >> 24) & 0xff;
bd59a631 7755 add_prefix (prefix);
c0f3af97
L		 7756 }
7757 break;
7758 case 2:
7759 if ((i.tm.base_opcode & 0xff0000) != 0)
7760 {
7761 prefix = (i.tm.base_opcode >> 16) & 0xff;
bd59a631
JB		 7762 if (!i.tm.cpu_flags.bitfield.cpupadlock
7763 || prefix != REPE_PREFIX_OPCODE
7764 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
4dffcebc
L		 7765 add_prefix (prefix);
7766 }
c0f3af97
L		 7767 break;
7768 case 1:
7769 break;
390c91cf
L		 7770 case 0:
7771 /* Check for pseudo prefixes. */
7772 as_bad_where (insn_start_frag->fr_file,
7773 insn_start_frag->fr_line,
7774 _("pseudo prefix without instruction"));
7775 return;
c0f3af97
L		 7776 default:
7777 abort ();
bc4bd9ab 7778 }
c0f3af97 7779
6d19a37a 7780#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7781 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7782 R_X86_64_GOTTPOFF relocation so that linker can safely
7783 perform IE->LE optimization. */
7784 if (x86_elf_abi == X86_64_X32_ABI
7785 && i.operands == 2
7786 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7787 && i.prefix[REX_PREFIX] == 0)
7788 add_prefix (REX_OPCODE);
6d19a37a 7789#endif
cf61b747 7790
c0f3af97
L		 7791 /* The prefix bytes. */
7792 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7793 if (*q)
7794 FRAG_APPEND_1_CHAR (*q);
0f10071e 7795 }
ae5c1c7b 7796 else
c0f3af97
L		 7797 {
7798 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7799 if (*q)
7800 switch (j)
7801 {
7802 case REX_PREFIX:
7803 /* REX byte is encoded in VEX prefix. */
7804 break;
7805 case SEG_PREFIX:
7806 case ADDR_PREFIX:
7807 FRAG_APPEND_1_CHAR (*q);
7808 break;
7809 default:
7810 /* There should be no other prefixes for instructions
7811 with VEX prefix. */
7812 abort ();
7813 }
7814
43234a1e
L		 7815 /* For EVEX instructions i.vrex should become 0 after
7816 build_evex_prefix. For VEX instructions upper 16 registers
7817 aren't available, so VREX should be 0. */
7818 if (i.vrex)
7819 abort ();
c0f3af97
L		 7820 /* Now the VEX prefix. */
7821 p = frag_more (i.vex.length);
7822 for (j = 0; j < i.vex.length; j++)
7823 p[j] = i.vex.bytes[j];
7824 }
252b5132 7825
29b0f896 7826 /* Now the opcode; be careful about word order here! */
4dffcebc 7827 if (i.tm.opcode_length == 1)
29b0f896
AM		 7828 {
7829 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7830 }
7831 else
7832 {
4dffcebc 7833 switch (i.tm.opcode_length)
331d2d0d 7834 {
43234a1e
L		 7835 case 4:
7836 p = frag_more (4);
7837 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7838 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7839 break;
4dffcebc 7840 case 3:
331d2d0d
L		 7841 p = frag_more (3);
7842 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7843 break;
7844 case 2:
7845 p = frag_more (2);
7846 break;
7847 default:
7848 abort ();
7849 break;
331d2d0d 7850 }
0f10071e 7851
29b0f896
AM		 7852 /* Put out high byte first: can't use md_number_to_chars! */
7853 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7854 *p = i.tm.base_opcode & 0xff;
7855 }
3e73aa7c 7856
29b0f896 7857 /* Now the modrm byte and sib byte (if present). */
40fb9820 7858 if (i.tm.opcode_modifier.modrm)
29b0f896 7859 {
4a3523fa
L		 7860 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7861 | i.rm.reg << 3
7862 | i.rm.mode << 6));
29b0f896
AM		 7863 /* If i.rm.regmem == ESP (4)
7864 && i.rm.mode != (Register mode)
7865 && not 16 bit
7866 ==> need second modrm byte. */
7867 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7868 && i.rm.mode != 3
dc821c5f 7869 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7870 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7871 | i.sib.index << 3
7872 | i.sib.scale << 6));
29b0f896 7873 }
3e73aa7c 7874
29b0f896 7875 if (i.disp_operands)
2bbd9c25 7876 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7877
29b0f896 7878 if (i.imm_operands)
2bbd9c25 7879 output_imm (insn_start_frag, insn_start_off);
29b0f896 7880 }
252b5132 7881
29b0f896
AM		 7882#ifdef DEBUG386
7883 if (flag_debug)
7884 {
7b81dfbb 7885 pi ("" /*line*/, &i);
29b0f896
AM		 7886 }
7887#endif /* DEBUG386 */
7888}
252b5132 7889
e205caa7
L		 7890/* Return the size of the displacement operand N. */
7891
7892static int
7893disp_size (unsigned int n)
7894{
7895 int size = 4;
43234a1e 7896
b5014f7a 7897 if (i.types[n].bitfield.disp64)
40fb9820
L		 7898 size = 8;
7899 else if (i.types[n].bitfield.disp8)
7900 size = 1;
7901 else if (i.types[n].bitfield.disp16)
7902 size = 2;
e205caa7
L		 7903 return size;
7904}
7905
7906/* Return the size of the immediate operand N. */
7907
7908static int
7909imm_size (unsigned int n)
7910{
7911 int size = 4;
40fb9820
L		 7912 if (i.types[n].bitfield.imm64)
7913 size = 8;
7914 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7915 size = 1;
7916 else if (i.types[n].bitfield.imm16)
7917 size = 2;
e205caa7
L		 7918 return size;
7919}
7920
29b0f896 7921static void
64e74474 7922output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7923{
7924 char *p;
7925 unsigned int n;
252b5132 7926
29b0f896
AM		 7927 for (n = 0; n < i.operands; n++)
7928 {
b5014f7a 7929 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7930 {
7931 if (i.op[n].disps->X_op == O_constant)
7932 {
e205caa7 7933 int size = disp_size (n);
43234a1e 7934 offsetT val = i.op[n].disps->X_add_number;
252b5132 7935
b5014f7a 7936 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7937 p = frag_more (size);
7938 md_number_to_chars (p, val, size);
7939 }
7940 else
7941 {
f86103b7 7942 enum bfd_reloc_code_real reloc_type;
e205caa7 7943 int size = disp_size (n);
40fb9820 7944 int sign = i.types[n].bitfield.disp32s;
29b0f896 7945 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7946 fixS *fixP;
29b0f896 7947
e205caa7 7948 /* We can't have 8 bit displacement here. */
9c2799c2 7949 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7950
29b0f896
AM		 7951 /* The PC relative address is computed relative
7952 to the instruction boundary, so in case immediate
7953 fields follows, we need to adjust the value. */
7954 if (pcrel && i.imm_operands)
7955 {
29b0f896 7956 unsigned int n1;
e205caa7 7957 int sz = 0;
252b5132 7958
29b0f896 7959 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7960 if (operand_type_check (i.types[n1], imm))
252b5132 7961 {
e205caa7
L		 7962 /* Only one immediate is allowed for PC
7963 relative address. */
9c2799c2 7964 gas_assert (sz == 0);
e205caa7
L		 7965 sz = imm_size (n1);
7966 i.op[n].disps->X_add_number -= sz;
252b5132 7967 }
29b0f896 7968 /* We should find the immediate. */
9c2799c2 7969 gas_assert (sz != 0);
29b0f896 7970 }
520dc8e8 7971
29b0f896 7972 p = frag_more (size);
d258b828 7973 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7974 if (GOT_symbol
2bbd9c25 7975 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7976 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7977 || reloc_type == BFD_RELOC_X86_64_32S
7978 || (reloc_type == BFD_RELOC_64
7979 && object_64bit))
d6ab8113
JB		 7980 && (i.op[n].disps->X_op == O_symbol
7981 || (i.op[n].disps->X_op == O_add
7982 && ((symbol_get_value_expression
7983 (i.op[n].disps->X_op_symbol)->X_op)
7984 == O_subtract))))
7985 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7986 {
7987 offsetT add;
7988
7989 if (insn_start_frag == frag_now)
7990 add = (p - frag_now->fr_literal) - insn_start_off;
7991 else
7992 {
7993 fragS *fr;
7994
7995 add = insn_start_frag->fr_fix - insn_start_off;
7996 for (fr = insn_start_frag->fr_next;
7997 fr && fr != frag_now; fr = fr->fr_next)
7998 add += fr->fr_fix;
7999 add += p - frag_now->fr_literal;
8000 }
8001
4fa24527 8002 if (!object_64bit)
7b81dfbb
AJ		 8003 {
8004 reloc_type = BFD_RELOC_386_GOTPC;
8005 i.op[n].imms->X_add_number += add;
8006 }
8007 else if (reloc_type == BFD_RELOC_64)
8008 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 8009 else
7b81dfbb
AJ		 8010 /* Don't do the adjustment for x86-64, as there
8011 the pcrel addressing is relative to the _next_
8012 insn, and that is taken care of in other code. */
d6ab8113 8013 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 8014 }
02a86693
L		 8015 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8016 size, i.op[n].disps, pcrel,
8017 reloc_type);
8018 /* Check for "call/jmp *mem", "mov mem, %reg",
8019 "test %reg, mem" and "binop mem, %reg" where binop
8020 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 8021 instructions. Always generate R_386_GOT32X for
8022 "sym*GOT" operand in 32-bit mode. */
8023 if ((generate_relax_relocations
8024 || (!object_64bit
8025 && i.rm.mode == 0
8026 && i.rm.regmem == 5))
8027 && (i.rm.mode == 2
8028 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 8029 && ((i.operands == 1
8030 && i.tm.base_opcode == 0xff
8031 && (i.rm.reg == 2 || i.rm.reg == 4))
8032 || (i.operands == 2
8033 && (i.tm.base_opcode == 0x8b
8034 || i.tm.base_opcode == 0x85
8035 || (i.tm.base_opcode & 0xc7) == 0x03))))
8036 {
8037 if (object_64bit)
8038 {
8039 fixP->fx_tcbit = i.rex != 0;
8040 if (i.base_reg
8041 && (i.base_reg->reg_num == RegRip
8042 || i.base_reg->reg_num == RegEip))
8043 fixP->fx_tcbit2 = 1;
8044 }
8045 else
8046 fixP->fx_tcbit2 = 1;
8047 }
29b0f896
AM		 8048 }
8049 }
8050 }
8051}
252b5132 8052
29b0f896 8053static void
64e74474 8054output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 8055{
8056 char *p;
8057 unsigned int n;
252b5132 8058
29b0f896
AM		 8059 for (n = 0; n < i.operands; n++)
8060 {
43234a1e
L		 8061 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8062 if (i.rounding && (int) n == i.rounding->operand)
8063 continue;
8064
40fb9820 8065 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 8066 {
8067 if (i.op[n].imms->X_op == O_constant)
8068 {
e205caa7 8069 int size = imm_size (n);
29b0f896 8070 offsetT val;
b4cac588 8071
29b0f896
AM		 8072 val = offset_in_range (i.op[n].imms->X_add_number,
8073 size);
8074 p = frag_more (size);
8075 md_number_to_chars (p, val, size);
8076 }
8077 else
8078 {
8079 /* Not absolute_section.
8080 Need a 32-bit fixup (don't support 8bit
8081 non-absolute imms). Try to support other
8082 sizes ... */
f86103b7 8083 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 8084 int size = imm_size (n);
8085 int sign;
29b0f896 8086
40fb9820 8087 if (i.types[n].bitfield.imm32s
a7d61044 8088 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 8089 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 8090 sign = 1;
e205caa7
L		 8091 else
8092 sign = 0;
520dc8e8 8093
29b0f896 8094 p = frag_more (size);
d258b828 8095 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 8096
2bbd9c25
JJ		 8097 /* This is tough to explain. We end up with this one if we
8098 * have operands that look like
8099 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8100 * obtain the absolute address of the GOT, and it is strongly
8101 * preferable from a performance point of view to avoid using
8102 * a runtime relocation for this. The actual sequence of
8103 * instructions often look something like:
8104 *
8105 * call .L66
8106 * .L66:
8107 * popl %ebx
8108 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8109 *
8110 * The call and pop essentially return the absolute address
8111 * of the label .L66 and store it in %ebx. The linker itself
8112 * will ultimately change the first operand of the addl so
8113 * that %ebx points to the GOT, but to keep things simple, the
8114 * .o file must have this operand set so that it generates not
8115 * the absolute address of .L66, but the absolute address of
8116 * itself. This allows the linker itself simply treat a GOTPC
8117 * relocation as asking for a pcrel offset to the GOT to be
8118 * added in, and the addend of the relocation is stored in the
8119 * operand field for the instruction itself.
8120 *
8121 * Our job here is to fix the operand so that it would add
8122 * the correct offset so that %ebx would point to itself. The
8123 * thing that is tricky is that .-.L66 will point to the
8124 * beginning of the instruction, so we need to further modify
8125 * the operand so that it will point to itself. There are
8126 * other cases where you have something like:
8127 *
8128 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8129 *
8130 * and here no correction would be required. Internally in
8131 * the assembler we treat operands of this form as not being
8132 * pcrel since the '.' is explicitly mentioned, and I wonder
8133 * whether it would simplify matters to do it this way. Who
8134 * knows. In earlier versions of the PIC patches, the
8135 * pcrel_adjust field was used to store the correction, but
8136 * since the expression is not pcrel, I felt it would be
8137 * confusing to do it this way. */
8138
d6ab8113 8139 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8140 || reloc_type == BFD_RELOC_X86_64_32S
8141 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8142 && GOT_symbol
8143 && GOT_symbol == i.op[n].imms->X_add_symbol
8144 && (i.op[n].imms->X_op == O_symbol
8145 || (i.op[n].imms->X_op == O_add
8146 && ((symbol_get_value_expression
8147 (i.op[n].imms->X_op_symbol)->X_op)
8148 == O_subtract))))
8149 {
2bbd9c25
JJ		 8150 offsetT add;
8151
8152 if (insn_start_frag == frag_now)
8153 add = (p - frag_now->fr_literal) - insn_start_off;
8154 else
8155 {
8156 fragS *fr;
8157
8158 add = insn_start_frag->fr_fix - insn_start_off;
8159 for (fr = insn_start_frag->fr_next;
8160 fr && fr != frag_now; fr = fr->fr_next)
8161 add += fr->fr_fix;
8162 add += p - frag_now->fr_literal;
8163 }
8164
4fa24527 8165 if (!object_64bit)
d6ab8113 8166 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8167 else if (size == 4)
d6ab8113 8168 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8169 else if (size == 8)
8170 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8171 i.op[n].imms->X_add_number += add;
29b0f896 8172 }
29b0f896
AM		 8173 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8174 i.op[n].imms, 0, reloc_type);
8175 }
8176 }
8177 }
252b5132
RH		 8178}
8179\f
d182319b
JB		 8180/* x86_cons_fix_new is called via the expression parsing code when a
8181 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8182static int cons_sign = -1;
8183
8184void
e3bb37b5 8185x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8186 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8187{
d258b828 8188 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8189
8190#ifdef TE_PE
8191 if (exp->X_op == O_secrel)
8192 {
8193 exp->X_op = O_symbol;
8194 r = BFD_RELOC_32_SECREL;
8195 }
8196#endif
8197
8198 fix_new_exp (frag, off, len, exp, 0, r);
8199}
8200
357d1bd8
L		 8201/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8202 purpose of the `.dc.a' internal pseudo-op. */
8203
8204int
8205x86_address_bytes (void)
8206{
8207 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8208 return 4;
8209 return stdoutput->arch_info->bits_per_address / 8;
8210}
8211
d382c579
TG		 8212#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8213 || defined (LEX_AT)
d258b828 8214# define lex_got(reloc, adjust, types) NULL
718ddfc0 8215#else
f3c180ae
AM		 8216/* Parse operands of the form
8217 <symbol>@GOTOFF+<nnn>
8218 and similar .plt or .got references.
8219
8220 If we find one, set up the correct relocation in RELOC and copy the
8221 input string, minus the `@GOTOFF' into a malloc'd buffer for
8222 parsing by the calling routine. Return this buffer, and if ADJUST
8223 is non-null set it to the length of the string we removed from the
8224 input line. Otherwise return NULL. */
8225static char *
91d6fa6a 8226lex_got (enum bfd_reloc_code_real *rel,
64e74474 8227 int *adjust,
d258b828 8228 i386_operand_type *types)
f3c180ae 8229{
7b81dfbb
AJ		 8230 /* Some of the relocations depend on the size of what field is to
8231 be relocated. But in our callers i386_immediate and i386_displacement
8232 we don't yet know the operand size (this will be set by insn
8233 matching). Hence we record the word32 relocation here,
8234 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8235 static const struct {
8236 const char *str;
cff8d58a 8237 int len;
4fa24527 8238 const enum bfd_reloc_code_real rel[2];
40fb9820 8239 const i386_operand_type types64;
f3c180ae 8240 } gotrel[] = {
8ce3d284 8241#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8242 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8243 BFD_RELOC_SIZE32 },
8244 OPERAND_TYPE_IMM32_64 },
8ce3d284 8245#endif
cff8d58a
L		 8246 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8247 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8248 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8249 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8250 BFD_RELOC_X86_64_PLT32 },
40fb9820 8251 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8252 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8253 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8254 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8255 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8256 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8257 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8258 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8259 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8260 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8261 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8262 BFD_RELOC_X86_64_TLSGD },
40fb9820 8263 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8264 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8265 _dummy_first_bfd_reloc_code_real },
40fb9820 8266 OPERAND_TYPE_NONE },
cff8d58a
L		 8267 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8268 BFD_RELOC_X86_64_TLSLD },
40fb9820 8269 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8270 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8271 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8272 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8273 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8274 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8275 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8276 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8277 _dummy_first_bfd_reloc_code_real },
40fb9820 8278 OPERAND_TYPE_NONE },
cff8d58a
L		 8279 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8280 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8281 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8282 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8283 _dummy_first_bfd_reloc_code_real },
40fb9820 8284 OPERAND_TYPE_NONE },
cff8d58a
L		 8285 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8286 _dummy_first_bfd_reloc_code_real },
40fb9820 8287 OPERAND_TYPE_NONE },
cff8d58a
L		 8288 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8289 BFD_RELOC_X86_64_GOT32 },
40fb9820 8290 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8291 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8292 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8293 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8294 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8295 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8296 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8297 };
8298 char *cp;
8299 unsigned int j;
8300
d382c579 8301#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8302 if (!IS_ELF)
8303 return NULL;
d382c579 8304#endif
718ddfc0 8305
f3c180ae 8306 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8307 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8308 return NULL;
8309
47465058 8310 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8311 {
cff8d58a 8312 int len = gotrel[j].len;
28f81592 8313 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8314 {
4fa24527 8315 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8316 {
28f81592
AM		 8317 int first, second;
8318 char *tmpbuf, *past_reloc;
f3c180ae 8319
91d6fa6a 8320 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8321
3956db08
JB		 8322 if (types)
8323 {
8324 if (flag_code != CODE_64BIT)
40fb9820
L		 8325 {
8326 types->bitfield.imm32 = 1;
8327 types->bitfield.disp32 = 1;
8328 }
3956db08
JB		 8329 else
8330 *types = gotrel[j].types64;
8331 }
8332
8fd4256d 8333 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8334 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8335
28f81592 8336 /* The length of the first part of our input line. */
f3c180ae 8337 first = cp - input_line_pointer;
28f81592
AM		 8338
8339 /* The second part goes from after the reloc token until
67c11a9b 8340 (and including) an end_of_line char or comma. */
28f81592 8341 past_reloc = cp + 1 + len;
67c11a9b
AM		 8342 cp = past_reloc;
8343 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8344 ++cp;
8345 second = cp + 1 - past_reloc;
28f81592
AM		 8346
8347 /* Allocate and copy string. The trailing NUL shouldn't
8348 be necessary, but be safe. */
add39d23 8349 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8350 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8351 if (second != 0 && *past_reloc != ' ')
8352 /* Replace the relocation token with ' ', so that
8353 errors like foo@GOTOFF1 will be detected. */
8354 tmpbuf[first++] = ' ';
af89796a
L		 8355 else
8356 /* Increment length by 1 if the relocation token is
8357 removed. */
8358 len++;
8359 if (adjust)
8360 *adjust = len;
0787a12d
AM		 8361 memcpy (tmpbuf + first, past_reloc, second);
8362 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8363 return tmpbuf;
8364 }
8365
4fa24527
JB		 8366 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8367 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8368 return NULL;
8369 }
8370 }
8371
8372 /* Might be a symbol version string. Don't as_bad here. */
8373 return NULL;
8374}
4e4f7c87 8375#endif
f3c180ae 8376
a988325c
NC		 8377#ifdef TE_PE
8378#ifdef lex_got
8379#undef lex_got
8380#endif
8381/* Parse operands of the form
8382 <symbol>@SECREL32+<nnn>
8383
8384 If we find one, set up the correct relocation in RELOC and copy the
8385 input string, minus the `@SECREL32' into a malloc'd buffer for
8386 parsing by the calling routine. Return this buffer, and if ADJUST
8387 is non-null set it to the length of the string we removed from the
34bca508
L		 8388 input line. Otherwise return NULL.
8389
a988325c
NC		 8390 This function is copied from the ELF version above adjusted for PE targets. */
8391
8392static char *
8393lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8394 int *adjust ATTRIBUTE_UNUSED,
d258b828 8395 i386_operand_type *types)
a988325c
NC		 8396{
8397 static const struct
8398 {
8399 const char *str;
8400 int len;
8401 const enum bfd_reloc_code_real rel[2];
8402 const i386_operand_type types64;
8403 }
8404 gotrel[] =
8405 {
8406 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8407 BFD_RELOC_32_SECREL },
8408 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8409 };
8410
8411 char *cp;
8412 unsigned j;
8413
8414 for (cp = input_line_pointer; *cp != '@'; cp++)
8415 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8416 return NULL;
8417
8418 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8419 {
8420 int len = gotrel[j].len;
8421
8422 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8423 {
8424 if (gotrel[j].rel[object_64bit] != 0)
8425 {
8426 int first, second;
8427 char *tmpbuf, *past_reloc;
8428
8429 *rel = gotrel[j].rel[object_64bit];
8430 if (adjust)
8431 *adjust = len;
8432
8433 if (types)
8434 {
8435 if (flag_code != CODE_64BIT)
8436 {
8437 types->bitfield.imm32 = 1;
8438 types->bitfield.disp32 = 1;
8439 }
8440 else
8441 *types = gotrel[j].types64;
8442 }
8443
8444 /* The length of the first part of our input line. */
8445 first = cp - input_line_pointer;
8446
8447 /* The second part goes from after the reloc token until
8448 (and including) an end_of_line char or comma. */
8449 past_reloc = cp + 1 + len;
8450 cp = past_reloc;
8451 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8452 ++cp;
8453 second = cp + 1 - past_reloc;
8454
8455 /* Allocate and copy string. The trailing NUL shouldn't
8456 be necessary, but be safe. */
add39d23 8457 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8458 memcpy (tmpbuf, input_line_pointer, first);
8459 if (second != 0 && *past_reloc != ' ')
8460 /* Replace the relocation token with ' ', so that
8461 errors like foo@SECLREL321 will be detected. */
8462 tmpbuf[first++] = ' ';
8463 memcpy (tmpbuf + first, past_reloc, second);
8464 tmpbuf[first + second] = '\0';
8465 return tmpbuf;
8466 }
8467
8468 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8469 gotrel[j].str, 1 << (5 + object_64bit));
8470 return NULL;
8471 }
8472 }
8473
8474 /* Might be a symbol version string. Don't as_bad here. */
8475 return NULL;
8476}
8477
8478#endif /* TE_PE */
8479
62ebcb5c 8480bfd_reloc_code_real_type
e3bb37b5 8481x86_cons (expressionS *exp, int size)
f3c180ae 8482{
62ebcb5c
AM		 8483 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8484
ee86248c
JB		 8485 intel_syntax = -intel_syntax;
8486
3c7b9c2c 8487 exp->X_md = 0;
4fa24527 8488 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8489 {
8490 /* Handle @GOTOFF and the like in an expression. */
8491 char *save;
8492 char *gotfree_input_line;
4a57f2cf 8493 int adjust = 0;
f3c180ae
AM		 8494
8495 save = input_line_pointer;
d258b828 8496 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8497 if (gotfree_input_line)
8498 input_line_pointer = gotfree_input_line;
8499
8500 expression (exp);
8501
8502 if (gotfree_input_line)
8503 {
8504 /* expression () has merrily parsed up to the end of line,
8505 or a comma - in the wrong buffer. Transfer how far
8506 input_line_pointer has moved to the right buffer. */
8507 input_line_pointer = (save
8508 + (input_line_pointer - gotfree_input_line)
8509 + adjust);
8510 free (gotfree_input_line);
3992d3b7
AM		 8511 if (exp->X_op == O_constant
8512 || exp->X_op == O_absent
8513 || exp->X_op == O_illegal
0398aac5 8514 || exp->X_op == O_register
3992d3b7
AM		 8515 || exp->X_op == O_big)
8516 {
8517 char c = *input_line_pointer;
8518 *input_line_pointer = 0;
8519 as_bad (_("missing or invalid expression `%s'"), save);
8520 *input_line_pointer = c;
8521 }
f3c180ae
AM		 8522 }
8523 }
8524 else
8525 expression (exp);
ee86248c
JB		 8526
8527 intel_syntax = -intel_syntax;
8528
8529 if (intel_syntax)
8530 i386_intel_simplify (exp);
62ebcb5c
AM		 8531
8532 return got_reloc;
f3c180ae 8533}
f3c180ae 8534
9f32dd5b
L		 8535static void
8536signed_cons (int size)
6482c264 8537{
d182319b
JB		 8538 if (flag_code == CODE_64BIT)
8539 cons_sign = 1;
8540 cons (size);
8541 cons_sign = -1;
6482c264
NC		 8542}
8543
d182319b 8544#ifdef TE_PE
6482c264 8545static void
7016a5d5 8546pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8547{
8548 expressionS exp;
8549
8550 do
8551 {
8552 expression (&exp);
8553 if (exp.X_op == O_symbol)
8554 exp.X_op = O_secrel;
8555
8556 emit_expr (&exp, 4);
8557 }
8558 while (*input_line_pointer++ == ',');
8559
8560 input_line_pointer--;
8561 demand_empty_rest_of_line ();
8562}
6482c264
NC		 8563#endif
8564
43234a1e
L		 8565/* Handle Vector operations. */
8566
8567static char *
8568check_VecOperations (char *op_string, char *op_end)
8569{
8570 const reg_entry *mask;
8571 const char *saved;
8572 char *end_op;
8573
8574 while (*op_string
8575 && (op_end == NULL || op_string < op_end))
8576 {
8577 saved = op_string;
8578 if (*op_string == '{')
8579 {
8580 op_string++;
8581
8582 /* Check broadcasts. */
8583 if (strncmp (op_string, "1to", 3) == 0)
8584 {
8585 int bcst_type;
8586
8587 if (i.broadcast)
8588 goto duplicated_vec_op;
8589
8590 op_string += 3;
8591 if (*op_string == '8')
8e6e0792 8592 bcst_type = 8;
b28d1bda 8593 else if (*op_string == '4')
8e6e0792 8594 bcst_type = 4;
b28d1bda 8595 else if (*op_string == '2')
8e6e0792 8596 bcst_type = 2;
43234a1e
L		 8597 else if (*op_string == '1'
8598 && *(op_string+1) == '6')
8599 {
8e6e0792 8600 bcst_type = 16;
43234a1e
L		 8601 op_string++;
8602 }
8603 else
8604 {
8605 as_bad (_("Unsupported broadcast: `%s'"), saved);
8606 return NULL;
8607 }
8608 op_string++;
8609
8610 broadcast_op.type = bcst_type;
8611 broadcast_op.operand = this_operand;
8612 i.broadcast = &broadcast_op;
8613 }
8614 /* Check masking operation. */
8615 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8616 {
8617 /* k0 can't be used for write mask. */
6d2cd6b2 8618 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8619 {
6d2cd6b2
JB		 8620 as_bad (_("`%s%s' can't be used for write mask"),
8621 register_prefix, mask->reg_name);
43234a1e
L		 8622 return NULL;
8623 }
8624
8625 if (!i.mask)
8626 {
8627 mask_op.mask = mask;
8628 mask_op.zeroing = 0;
8629 mask_op.operand = this_operand;
8630 i.mask = &mask_op;
8631 }
8632 else
8633 {
8634 if (i.mask->mask)
8635 goto duplicated_vec_op;
8636
8637 i.mask->mask = mask;
8638
8639 /* Only "{z}" is allowed here. No need to check
8640 zeroing mask explicitly. */
8641 if (i.mask->operand != this_operand)
8642 {
8643 as_bad (_("invalid write mask `%s'"), saved);
8644 return NULL;
8645 }
8646 }
8647
8648 op_string = end_op;
8649 }
8650 /* Check zeroing-flag for masking operation. */
8651 else if (*op_string == 'z')
8652 {
8653 if (!i.mask)
8654 {
8655 mask_op.mask = NULL;
8656 mask_op.zeroing = 1;
8657 mask_op.operand = this_operand;
8658 i.mask = &mask_op;
8659 }
8660 else
8661 {
8662 if (i.mask->zeroing)
8663 {
8664 duplicated_vec_op:
8665 as_bad (_("duplicated `%s'"), saved);
8666 return NULL;
8667 }
8668
8669 i.mask->zeroing = 1;
8670
8671 /* Only "{%k}" is allowed here. No need to check mask
8672 register explicitly. */
8673 if (i.mask->operand != this_operand)
8674 {
8675 as_bad (_("invalid zeroing-masking `%s'"),
8676 saved);
8677 return NULL;
8678 }
8679 }
8680
8681 op_string++;
8682 }
8683 else
8684 goto unknown_vec_op;
8685
8686 if (*op_string != '}')
8687 {
8688 as_bad (_("missing `}' in `%s'"), saved);
8689 return NULL;
8690 }
8691 op_string++;
0ba3a731
L		 8692
8693 /* Strip whitespace since the addition of pseudo prefixes
8694 changed how the scrubber treats '{'. */
8695 if (is_space_char (*op_string))
8696 ++op_string;
8697
43234a1e
L		 8698 continue;
8699 }
8700 unknown_vec_op:
8701 /* We don't know this one. */
8702 as_bad (_("unknown vector operation: `%s'"), saved);
8703 return NULL;
8704 }
8705
6d2cd6b2
JB		 8706 if (i.mask && i.mask->zeroing && !i.mask->mask)
8707 {
8708 as_bad (_("zeroing-masking only allowed with write mask"));
8709 return NULL;
8710 }
8711
43234a1e
L		 8712 return op_string;
8713}
8714
252b5132 8715static int
70e41ade 8716i386_immediate (char *imm_start)
252b5132
RH		 8717{
8718 char *save_input_line_pointer;
f3c180ae 8719 char *gotfree_input_line;
252b5132 8720 segT exp_seg = 0;
47926f60 8721 expressionS *exp;
40fb9820
L		 8722 i386_operand_type types;
8723
0dfbf9d7 8724 operand_type_set (&types, ~0);
252b5132
RH		 8725
8726 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8727 {
31b2323c
L		 8728 as_bad (_("at most %d immediate operands are allowed"),
8729 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8730 return 0;
8731 }
8732
8733 exp = &im_expressions[i.imm_operands++];
520dc8e8 8734 i.op[this_operand].imms = exp;
252b5132
RH		 8735
8736 if (is_space_char (*imm_start))
8737 ++imm_start;
8738
8739 save_input_line_pointer = input_line_pointer;
8740 input_line_pointer = imm_start;
8741
d258b828 8742 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8743 if (gotfree_input_line)
8744 input_line_pointer = gotfree_input_line;
252b5132
RH		 8745
8746 exp_seg = expression (exp);
8747
83183c0c 8748 SKIP_WHITESPACE ();
43234a1e
L		 8749
8750 /* Handle vector operations. */
8751 if (*input_line_pointer == '{')
8752 {
8753 input_line_pointer = check_VecOperations (input_line_pointer,
8754 NULL);
8755 if (input_line_pointer == NULL)
8756 return 0;
8757 }
8758
252b5132 8759 if (*input_line_pointer)
f3c180ae 8760 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8761
8762 input_line_pointer = save_input_line_pointer;
f3c180ae 8763 if (gotfree_input_line)
ee86248c
JB		 8764 {
8765 free (gotfree_input_line);
8766
8767 if (exp->X_op == O_constant || exp->X_op == O_register)
8768 exp->X_op = O_illegal;
8769 }
8770
8771 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8772}
252b5132 8773
ee86248c
JB		 8774static int
8775i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8776 i386_operand_type types, const char *imm_start)
8777{
8778 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8779 {
313c53d1
L		 8780 if (imm_start)
8781 as_bad (_("missing or invalid immediate expression `%s'"),
8782 imm_start);
3992d3b7 8783 return 0;
252b5132 8784 }
3e73aa7c 8785 else if (exp->X_op == O_constant)
252b5132 8786 {
47926f60 8787 /* Size it properly later. */
40fb9820 8788 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8789 /* If not 64bit, sign extend val. */
8790 if (flag_code != CODE_64BIT
4eed87de
AM		 8791 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8792 exp->X_add_number
8793 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8794 }
4c63da97 8795#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8796 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8797 && exp_seg != absolute_section
47926f60 8798 && exp_seg != text_section
24eab124
AM		 8799 && exp_seg != data_section
8800 && exp_seg != bss_section
8801 && exp_seg != undefined_section
f86103b7 8802 && !bfd_is_com_section (exp_seg))
252b5132 8803 {
d0b47220 8804 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8805 return 0;
8806 }
8807#endif
a841bdf5 8808 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8809 {
313c53d1
L		 8810 if (imm_start)
8811 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8812 return 0;
8813 }
252b5132
RH		 8814 else
8815 {
8816 /* This is an address. The size of the address will be
24eab124 8817 determined later, depending on destination register,
3e73aa7c 8818 suffix, or the default for the section. */
40fb9820
L		 8819 i.types[this_operand].bitfield.imm8 = 1;
8820 i.types[this_operand].bitfield.imm16 = 1;
8821 i.types[this_operand].bitfield.imm32 = 1;
8822 i.types[this_operand].bitfield.imm32s = 1;
8823 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8824 i.types[this_operand] = operand_type_and (i.types[this_operand],
8825 types);
252b5132
RH		 8826 }
8827
8828 return 1;
8829}
8830
551c1ca1 8831static char *
e3bb37b5 8832i386_scale (char *scale)
252b5132 8833{
551c1ca1
AM		 8834 offsetT val;
8835 char *save = input_line_pointer;
252b5132 8836
551c1ca1
AM		 8837 input_line_pointer = scale;
8838 val = get_absolute_expression ();
8839
8840 switch (val)
252b5132 8841 {
551c1ca1 8842 case 1:
252b5132
RH		 8843 i.log2_scale_factor = 0;
8844 break;
551c1ca1 8845 case 2:
252b5132
RH		 8846 i.log2_scale_factor = 1;
8847 break;
551c1ca1 8848 case 4:
252b5132
RH		 8849 i.log2_scale_factor = 2;
8850 break;
551c1ca1 8851 case 8:
252b5132
RH		 8852 i.log2_scale_factor = 3;
8853 break;
8854 default:
a724f0f4
JB		 8855 {
8856 char sep = *input_line_pointer;
8857
8858 *input_line_pointer = '\0';
8859 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8860 scale);
8861 *input_line_pointer = sep;
8862 input_line_pointer = save;
8863 return NULL;
8864 }
252b5132 8865 }
29b0f896 8866 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8867 {
8868 as_warn (_("scale factor of %d without an index register"),
24eab124 8869 1 << i.log2_scale_factor);
252b5132 8870 i.log2_scale_factor = 0;
252b5132 8871 }
551c1ca1
AM		 8872 scale = input_line_pointer;
8873 input_line_pointer = save;
8874 return scale;
252b5132
RH		 8875}
8876
252b5132 8877static int
e3bb37b5 8878i386_displacement (char *disp_start, char *disp_end)
252b5132 8879{
29b0f896 8880 expressionS *exp;
252b5132
RH		 8881 segT exp_seg = 0;
8882 char *save_input_line_pointer;
f3c180ae 8883 char *gotfree_input_line;
40fb9820
L		 8884 int override;
8885 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8886 int ret;
252b5132 8887
31b2323c
L		 8888 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8889 {
8890 as_bad (_("at most %d displacement operands are allowed"),
8891 MAX_MEMORY_OPERANDS);
8892 return 0;
8893 }
8894
0dfbf9d7 8895 operand_type_set (&bigdisp, 0);
40fb9820
L		 8896 if ((i.types[this_operand].bitfield.jumpabsolute)
8897 || (!current_templates->start->opcode_modifier.jump
8898 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8899 {
40fb9820 8900 bigdisp.bitfield.disp32 = 1;
e05278af 8901 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8902 if (flag_code == CODE_64BIT)
8903 {
8904 if (!override)
8905 {
8906 bigdisp.bitfield.disp32s = 1;
8907 bigdisp.bitfield.disp64 = 1;
8908 }
8909 }
8910 else if ((flag_code == CODE_16BIT) ^ override)
8911 {
8912 bigdisp.bitfield.disp32 = 0;
8913 bigdisp.bitfield.disp16 = 1;
8914 }
e05278af
JB		 8915 }
8916 else
8917 {
8918 /* For PC-relative branches, the width of the displacement
8919 is dependent upon data size, not address size. */
e05278af 8920 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8921 if (flag_code == CODE_64BIT)
8922 {
8923 if (override || i.suffix == WORD_MNEM_SUFFIX)
8924 bigdisp.bitfield.disp16 = 1;
8925 else
8926 {
8927 bigdisp.bitfield.disp32 = 1;
8928 bigdisp.bitfield.disp32s = 1;
8929 }
8930 }
8931 else
e05278af
JB		 8932 {
8933 if (!override)
8934 override = (i.suffix == (flag_code != CODE_16BIT
8935 ? WORD_MNEM_SUFFIX
8936 : LONG_MNEM_SUFFIX));
40fb9820
L		 8937 bigdisp.bitfield.disp32 = 1;
8938 if ((flag_code == CODE_16BIT) ^ override)
8939 {
8940 bigdisp.bitfield.disp32 = 0;
8941 bigdisp.bitfield.disp16 = 1;
8942 }
e05278af 8943 }
e05278af 8944 }
c6fb90c8
L		 8945 i.types[this_operand] = operand_type_or (i.types[this_operand],
8946 bigdisp);
252b5132
RH		 8947
8948 exp = &disp_expressions[i.disp_operands];
520dc8e8 8949 i.op[this_operand].disps = exp;
252b5132
RH		 8950 i.disp_operands++;
8951 save_input_line_pointer = input_line_pointer;
8952 input_line_pointer = disp_start;
8953 END_STRING_AND_SAVE (disp_end);
8954
8955#ifndef GCC_ASM_O_HACK
8956#define GCC_ASM_O_HACK 0
8957#endif
8958#if GCC_ASM_O_HACK
8959 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8960 if (i.types[this_operand].bitfield.baseIndex
24eab124 8961 && displacement_string_end[-1] == '+')
252b5132
RH		 8962 {
8963 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8964 constraint within gcc asm statements.
8965 For instance:
8966
8967 #define _set_tssldt_desc(n,addr,limit,type) \
8968 __asm__ __volatile__ ( \
8969 "movw %w2,%0\n\t" \
8970 "movw %w1,2+%0\n\t" \
8971 "rorl $16,%1\n\t" \
8972 "movb %b1,4+%0\n\t" \
8973 "movb %4,5+%0\n\t" \
8974 "movb $0,6+%0\n\t" \
8975 "movb %h1,7+%0\n\t" \
8976 "rorl $16,%1" \
8977 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8978
8979 This works great except that the output assembler ends
8980 up looking a bit weird if it turns out that there is
8981 no offset. You end up producing code that looks like:
8982
8983 #APP
8984 movw $235,(%eax)
8985 movw %dx,2+(%eax)
8986 rorl $16,%edx
8987 movb %dl,4+(%eax)
8988 movb $137,5+(%eax)
8989 movb $0,6+(%eax)
8990 movb %dh,7+(%eax)
8991 rorl $16,%edx
8992 #NO_APP
8993
47926f60 8994 So here we provide the missing zero. */
24eab124
AM		 8995
8996 *displacement_string_end = '0';
252b5132
RH		 8997 }
8998#endif
d258b828 8999 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 9000 if (gotfree_input_line)
9001 input_line_pointer = gotfree_input_line;
252b5132 9002
24eab124 9003 exp_seg = expression (exp);
252b5132 9004
636c26b0
AM		 9005 SKIP_WHITESPACE ();
9006 if (*input_line_pointer)
9007 as_bad (_("junk `%s' after expression"), input_line_pointer);
9008#if GCC_ASM_O_HACK
9009 RESTORE_END_STRING (disp_end + 1);
9010#endif
636c26b0 9011 input_line_pointer = save_input_line_pointer;
636c26b0 9012 if (gotfree_input_line)
ee86248c
JB		 9013 {
9014 free (gotfree_input_line);
9015
9016 if (exp->X_op == O_constant || exp->X_op == O_register)
9017 exp->X_op = O_illegal;
9018 }
9019
9020 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9021
9022 RESTORE_END_STRING (disp_end);
9023
9024 return ret;
9025}
9026
9027static int
9028i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9029 i386_operand_type types, const char *disp_start)
9030{
9031 i386_operand_type bigdisp;
9032 int ret = 1;
636c26b0 9033
24eab124
AM		 9034 /* We do this to make sure that the section symbol is in
9035 the symbol table. We will ultimately change the relocation
47926f60 9036 to be relative to the beginning of the section. */
1ae12ab7 9037 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 9038 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9039 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 9040 {
636c26b0 9041 if (exp->X_op != O_symbol)
3992d3b7 9042 goto inv_disp;
636c26b0 9043
e5cb08ac 9044 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 9045 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9046 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 9047 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 9048 exp->X_op = O_subtract;
9049 exp->X_op_symbol = GOT_symbol;
1ae12ab7 9050 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 9051 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 9052 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9053 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 9054 else
29b0f896 9055 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 9056 }
252b5132 9057
3992d3b7
AM		 9058 else if (exp->X_op == O_absent
9059 || exp->X_op == O_illegal
ee86248c 9060 || exp->X_op == O_big)
2daf4fd8 9061 {
3992d3b7
AM		 9062 inv_disp:
9063 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 9064 disp_start);
3992d3b7 9065 ret = 0;
2daf4fd8
AM		 9066 }
9067
0e1147d9
L		 9068 else if (flag_code == CODE_64BIT
9069 && !i.prefix[ADDR_PREFIX]
9070 && exp->X_op == O_constant)
9071 {
9072 /* Since displacement is signed extended to 64bit, don't allow
9073 disp32 and turn off disp32s if they are out of range. */
9074 i.types[this_operand].bitfield.disp32 = 0;
9075 if (!fits_in_signed_long (exp->X_add_number))
9076 {
9077 i.types[this_operand].bitfield.disp32s = 0;
9078 if (i.types[this_operand].bitfield.baseindex)
9079 {
9080 as_bad (_("0x%lx out range of signed 32bit displacement"),
9081 (long) exp->X_add_number);
9082 ret = 0;
9083 }
9084 }
9085 }
9086
4c63da97 9087#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 9088 else if (exp->X_op != O_constant
9089 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9090 && exp_seg != absolute_section
9091 && exp_seg != text_section
9092 && exp_seg != data_section
9093 && exp_seg != bss_section
9094 && exp_seg != undefined_section
9095 && !bfd_is_com_section (exp_seg))
24eab124 9096 {
d0b47220 9097 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 9098 ret = 0;
24eab124 9099 }
252b5132 9100#endif
3956db08 9101
40fb9820
L		 9102 /* Check if this is a displacement only operand. */
9103 bigdisp = i.types[this_operand];
9104 bigdisp.bitfield.disp8 = 0;
9105 bigdisp.bitfield.disp16 = 0;
9106 bigdisp.bitfield.disp32 = 0;
9107 bigdisp.bitfield.disp32s = 0;
9108 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 9109 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 9110 i.types[this_operand] = operand_type_and (i.types[this_operand],
9111 types);
3956db08 9112
3992d3b7 9113 return ret;
252b5132
RH		 9114}
9115
2abc2bec
JB		 9116/* Return the active addressing mode, taking address override and
9117 registers forming the address into consideration. Update the
9118 address override prefix if necessary. */
47926f60 9119
2abc2bec
JB		 9120static enum flag_code
9121i386_addressing_mode (void)
252b5132 9122{
be05d201
L		 9123 enum flag_code addr_mode;
9124
9125 if (i.prefix[ADDR_PREFIX])
9126 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9127 else
9128 {
9129 addr_mode = flag_code;
9130
24eab124 9131#if INFER_ADDR_PREFIX
be05d201
L		 9132 if (i.mem_operands == 0)
9133 {
9134 /* Infer address prefix from the first memory operand. */
9135 const reg_entry *addr_reg = i.base_reg;
9136
9137 if (addr_reg == NULL)
9138 addr_reg = i.index_reg;
eecb386c 9139
be05d201
L		 9140 if (addr_reg)
9141 {
9142 if (addr_reg->reg_num == RegEip
9143 || addr_reg->reg_num == RegEiz
dc821c5f 9144 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9145 addr_mode = CODE_32BIT;
9146 else if (flag_code != CODE_64BIT
dc821c5f 9147 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9148 addr_mode = CODE_16BIT;
9149
9150 if (addr_mode != flag_code)
9151 {
9152 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9153 i.prefixes += 1;
9154 /* Change the size of any displacement too. At most one
9155 of Disp16 or Disp32 is set.
9156 FIXME. There doesn't seem to be any real need for
9157 separate Disp16 and Disp32 flags. The same goes for
9158 Imm16 and Imm32. Removing them would probably clean
9159 up the code quite a lot. */
9160 if (flag_code != CODE_64BIT
9161 && (i.types[this_operand].bitfield.disp16
9162 || i.types[this_operand].bitfield.disp32))
9163 i.types[this_operand]
9164 = operand_type_xor (i.types[this_operand], disp16_32);
9165 }
9166 }
9167 }
24eab124 9168#endif
be05d201
L		 9169 }
9170
2abc2bec
JB		 9171 return addr_mode;
9172}
9173
9174/* Make sure the memory operand we've been dealt is valid.
9175 Return 1 on success, 0 on a failure. */
9176
9177static int
9178i386_index_check (const char *operand_string)
9179{
9180 const char *kind = "base/index";
9181 enum flag_code addr_mode = i386_addressing_mode ();
9182
fc0763e6
JB		 9183 if (current_templates->start->opcode_modifier.isstring
9184 && !current_templates->start->opcode_modifier.immext
9185 && (current_templates->end[-1].opcode_modifier.isstring
9186 || i.mem_operands))
9187 {
9188 /* Memory operands of string insns are special in that they only allow
9189 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9190 const reg_entry *expected_reg;
9191 static const char *di_si[][2] =
9192 {
9193 { "esi", "edi" },
9194 { "si", "di" },
9195 { "rsi", "rdi" }
9196 };
9197 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9198
9199 kind = "string address";
9200
8325cc63 9201 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9202 {
9203 i386_operand_type type = current_templates->end[-1].operand_types[0];
9204
9205 if (!type.bitfield.baseindex
9206 || ((!i.mem_operands != !intel_syntax)
9207 && current_templates->end[-1].operand_types[1]
9208 .bitfield.baseindex))
9209 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9210 expected_reg = hash_find (reg_hash,
9211 di_si[addr_mode][type.bitfield.esseg]);
9212
fc0763e6
JB		 9213 }
9214 else
be05d201 9215 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9216
be05d201
L		 9217 if (i.base_reg != expected_reg
9218 || i.index_reg
fc0763e6 9219 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9220 {
be05d201
L		 9221 /* The second memory operand must have the same size as
9222 the first one. */
9223 if (i.mem_operands
9224 && i.base_reg
9225 && !((addr_mode == CODE_64BIT
dc821c5f 9226 && i.base_reg->reg_type.bitfield.qword)
be05d201 9227 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9228 ? i.base_reg->reg_type.bitfield.dword
9229 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9230 goto bad_address;
9231
fc0763e6
JB		 9232 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9233 operand_string,
9234 intel_syntax ? '[' : '(',
9235 register_prefix,
be05d201 9236 expected_reg->reg_name,
fc0763e6 9237 intel_syntax ? ']' : ')');
be05d201 9238 return 1;
fc0763e6 9239 }
be05d201
L		 9240 else
9241 return 1;
9242
9243bad_address:
9244 as_bad (_("`%s' is not a valid %s expression"),
9245 operand_string, kind);
9246 return 0;
3e73aa7c
JH		 9247 }
9248 else
9249 {
be05d201
L		 9250 if (addr_mode != CODE_16BIT)
9251 {
9252 /* 32-bit/64-bit checks. */
9253 if ((i.base_reg
9254 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9255 ? !i.base_reg->reg_type.bitfield.qword
9256 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9257 && (i.index_reg
9258 || (i.base_reg->reg_num
9259 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9260 || (i.index_reg
1b54b8d7
JB		 9261 && !i.index_reg->reg_type.bitfield.xmmword
9262 && !i.index_reg->reg_type.bitfield.ymmword
9263 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9264 && ((addr_mode == CODE_64BIT
dc821c5f 9265 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9266 || i.index_reg->reg_num == RegRiz)
dc821c5f 9267 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9268 || i.index_reg->reg_num == RegEiz))
9269 || !i.index_reg->reg_type.bitfield.baseindex)))
9270 goto bad_address;
8178be5b
JB		 9271
9272 /* bndmk, bndldx, and bndstx have special restrictions. */
9273 if (current_templates->start->base_opcode == 0xf30f1b
9274 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9275 {
9276 /* They cannot use RIP-relative addressing. */
9277 if (i.base_reg && i.base_reg->reg_num == RegRip)
9278 {
9279 as_bad (_("`%s' cannot be used here"), operand_string);
9280 return 0;
9281 }
9282
9283 /* bndldx and bndstx ignore their scale factor. */
9284 if (current_templates->start->base_opcode != 0xf30f1b
9285 && i.log2_scale_factor)
9286 as_warn (_("register scaling is being ignored here"));
9287 }
be05d201
L		 9288 }
9289 else
3e73aa7c 9290 {
be05d201 9291 /* 16-bit checks. */
3e73aa7c 9292 if ((i.base_reg
dc821c5f 9293 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9294 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9295 || (i.index_reg
dc821c5f 9296 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9297 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9298 || !(i.base_reg
9299 && i.base_reg->reg_num < 6
9300 && i.index_reg->reg_num >= 6
9301 && i.log2_scale_factor == 0))))
be05d201 9302 goto bad_address;
3e73aa7c
JH		 9303 }
9304 }
be05d201 9305 return 1;
24eab124 9306}
252b5132 9307
43234a1e
L		 9308/* Handle vector immediates. */
9309
9310static int
9311RC_SAE_immediate (const char *imm_start)
9312{
9313 unsigned int match_found, j;
9314 const char *pstr = imm_start;
9315 expressionS *exp;
9316
9317 if (*pstr != '{')
9318 return 0;
9319
9320 pstr++;
9321 match_found = 0;
9322 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9323 {
9324 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9325 {
9326 if (!i.rounding)
9327 {
9328 rc_op.type = RC_NamesTable[j].type;
9329 rc_op.operand = this_operand;
9330 i.rounding = &rc_op;
9331 }
9332 else
9333 {
9334 as_bad (_("duplicated `%s'"), imm_start);
9335 return 0;
9336 }
9337 pstr += RC_NamesTable[j].len;
9338 match_found = 1;
9339 break;
9340 }
9341 }
9342 if (!match_found)
9343 return 0;
9344
9345 if (*pstr++ != '}')
9346 {
9347 as_bad (_("Missing '}': '%s'"), imm_start);
9348 return 0;
9349 }
9350 /* RC/SAE immediate string should contain nothing more. */;
9351 if (*pstr != 0)
9352 {
9353 as_bad (_("Junk after '}': '%s'"), imm_start);
9354 return 0;
9355 }
9356
9357 exp = &im_expressions[i.imm_operands++];
9358 i.op[this_operand].imms = exp;
9359
9360 exp->X_op = O_constant;
9361 exp->X_add_number = 0;
9362 exp->X_add_symbol = (symbolS *) 0;
9363 exp->X_op_symbol = (symbolS *) 0;
9364
9365 i.types[this_operand].bitfield.imm8 = 1;
9366 return 1;
9367}
9368
8325cc63
JB		 9369/* Only string instructions can have a second memory operand, so
9370 reduce current_templates to just those if it contains any. */
9371static int
9372maybe_adjust_templates (void)
9373{
9374 const insn_template *t;
9375
9376 gas_assert (i.mem_operands == 1);
9377
9378 for (t = current_templates->start; t < current_templates->end; ++t)
9379 if (t->opcode_modifier.isstring)
9380 break;
9381
9382 if (t < current_templates->end)
9383 {
9384 static templates aux_templates;
9385 bfd_boolean recheck;
9386
9387 aux_templates.start = t;
9388 for (; t < current_templates->end; ++t)
9389 if (!t->opcode_modifier.isstring)
9390 break;
9391 aux_templates.end = t;
9392
9393 /* Determine whether to re-check the first memory operand. */
9394 recheck = (aux_templates.start != current_templates->start
9395 || t != current_templates->end);
9396
9397 current_templates = &aux_templates;
9398
9399 if (recheck)
9400 {
9401 i.mem_operands = 0;
9402 if (i.memop1_string != NULL
9403 && i386_index_check (i.memop1_string) == 0)
9404 return 0;
9405 i.mem_operands = 1;
9406 }
9407 }
9408
9409 return 1;
9410}
9411
fc0763e6 9412/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9413 on error. */
252b5132 9414
252b5132 9415static int
a7619375 9416i386_att_operand (char *operand_string)
252b5132 9417{
af6bdddf
AM		 9418 const reg_entry *r;
9419 char *end_op;
24eab124 9420 char *op_string = operand_string;
252b5132 9421
24eab124 9422 if (is_space_char (*op_string))
252b5132
RH		 9423 ++op_string;
9424
24eab124 9425 /* We check for an absolute prefix (differentiating,
47926f60 9426 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9427 if (*op_string == ABSOLUTE_PREFIX)
9428 {
9429 ++op_string;
9430 if (is_space_char (*op_string))
9431 ++op_string;
40fb9820 9432 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9433 }
252b5132 9434
47926f60 9435 /* Check if operand is a register. */
4d1bb795 9436 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9437 {
40fb9820
L		 9438 i386_operand_type temp;
9439
24eab124
AM		 9440 /* Check for a segment override by searching for ':' after a
9441 segment register. */
9442 op_string = end_op;
9443 if (is_space_char (*op_string))
9444 ++op_string;
40fb9820
L		 9445 if (*op_string == ':'
9446 && (r->reg_type.bitfield.sreg2
9447 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9448 {
9449 switch (r->reg_num)
9450 {
9451 case 0:
9452 i.seg[i.mem_operands] = &es;
9453 break;
9454 case 1:
9455 i.seg[i.mem_operands] = &cs;
9456 break;
9457 case 2:
9458 i.seg[i.mem_operands] = &ss;
9459 break;
9460 case 3:
9461 i.seg[i.mem_operands] = &ds;
9462 break;
9463 case 4:
9464 i.seg[i.mem_operands] = &fs;
9465 break;
9466 case 5:
9467 i.seg[i.mem_operands] = &gs;
9468 break;
9469 }
252b5132 9470
24eab124 9471 /* Skip the ':' and whitespace. */
252b5132
RH		 9472 ++op_string;
9473 if (is_space_char (*op_string))
24eab124 9474 ++op_string;
252b5132 9475
24eab124
AM		 9476 if (!is_digit_char (*op_string)
9477 && !is_identifier_char (*op_string)
9478 && *op_string != '('
9479 && *op_string != ABSOLUTE_PREFIX)
9480 {
9481 as_bad (_("bad memory operand `%s'"), op_string);
9482 return 0;
9483 }
47926f60 9484 /* Handle case of %es:*foo. */
24eab124
AM		 9485 if (*op_string == ABSOLUTE_PREFIX)
9486 {
9487 ++op_string;
9488 if (is_space_char (*op_string))
9489 ++op_string;
40fb9820 9490 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9491 }
9492 goto do_memory_reference;
9493 }
43234a1e
L		 9494
9495 /* Handle vector operations. */
9496 if (*op_string == '{')
9497 {
9498 op_string = check_VecOperations (op_string, NULL);
9499 if (op_string == NULL)
9500 return 0;
9501 }
9502
24eab124
AM		 9503 if (*op_string)
9504 {
d0b47220 9505 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9506 return 0;
9507 }
40fb9820
L		 9508 temp = r->reg_type;
9509 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9510 i.types[this_operand] = operand_type_or (i.types[this_operand],
9511 temp);
7d5e4556 9512 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9513 i.op[this_operand].regs = r;
24eab124
AM		 9514 i.reg_operands++;
9515 }
af6bdddf
AM		 9516 else if (*op_string == REGISTER_PREFIX)
9517 {
9518 as_bad (_("bad register name `%s'"), op_string);
9519 return 0;
9520 }
24eab124 9521 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9522 {
24eab124 9523 ++op_string;
40fb9820 9524 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9525 {
d0b47220 9526 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9527 return 0;
9528 }
9529 if (!i386_immediate (op_string))
9530 return 0;
9531 }
43234a1e
L		 9532 else if (RC_SAE_immediate (operand_string))
9533 {
9534 /* If it is a RC or SAE immediate, do nothing. */
9535 ;
9536 }
24eab124
AM		 9537 else if (is_digit_char (*op_string)
9538 || is_identifier_char (*op_string)
d02603dc 9539 || *op_string == '"'
e5cb08ac 9540 || *op_string == '(')
24eab124 9541 {
47926f60 9542 /* This is a memory reference of some sort. */
af6bdddf 9543 char *base_string;
252b5132 9544
47926f60 9545 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9546 char *displacement_string_start;
9547 char *displacement_string_end;
43234a1e 9548 char *vop_start;
252b5132 9549
24eab124 9550 do_memory_reference:
8325cc63
JB		 9551 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9552 return 0;
24eab124 9553 if ((i.mem_operands == 1
40fb9820 9554 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9555 || i.mem_operands == 2)
9556 {
9557 as_bad (_("too many memory references for `%s'"),
9558 current_templates->start->name);
9559 return 0;
9560 }
252b5132 9561
24eab124
AM		 9562 /* Check for base index form. We detect the base index form by
9563 looking for an ')' at the end of the operand, searching
9564 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9565 after the '('. */
af6bdddf 9566 base_string = op_string + strlen (op_string);
c3332e24 9567
43234a1e
L		 9568 /* Handle vector operations. */
9569 vop_start = strchr (op_string, '{');
9570 if (vop_start && vop_start < base_string)
9571 {
9572 if (check_VecOperations (vop_start, base_string) == NULL)
9573 return 0;
9574 base_string = vop_start;
9575 }
9576
af6bdddf
AM		 9577 --base_string;
9578 if (is_space_char (*base_string))
9579 --base_string;
252b5132 9580
47926f60 9581 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9582 displacement_string_start = op_string;
9583 displacement_string_end = base_string + 1;
252b5132 9584
24eab124
AM		 9585 if (*base_string == ')')
9586 {
af6bdddf 9587 char *temp_string;
24eab124
AM		 9588 unsigned int parens_balanced = 1;
9589 /* We've already checked that the number of left & right ()'s are
47926f60 9590 equal, so this loop will not be infinite. */
24eab124
AM		 9591 do
9592 {
9593 base_string--;
9594 if (*base_string == ')')
9595 parens_balanced++;
9596 if (*base_string == '(')
9597 parens_balanced--;
9598 }
9599 while (parens_balanced);
c3332e24 9600
af6bdddf 9601 temp_string = base_string;
c3332e24 9602
24eab124 9603 /* Skip past '(' and whitespace. */
252b5132
RH		 9604 ++base_string;
9605 if (is_space_char (*base_string))
24eab124 9606 ++base_string;
252b5132 9607
af6bdddf 9608 if (*base_string == ','
4eed87de
AM		 9609 || ((i.base_reg = parse_register (base_string, &end_op))
9610 != NULL))
252b5132 9611 {
af6bdddf 9612 displacement_string_end = temp_string;
252b5132 9613
40fb9820 9614 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9615
af6bdddf 9616 if (i.base_reg)
24eab124 9617 {
24eab124
AM		 9618 base_string = end_op;
9619 if (is_space_char (*base_string))
9620 ++base_string;
af6bdddf
AM		 9621 }
9622
9623 /* There may be an index reg or scale factor here. */
9624 if (*base_string == ',')
9625 {
9626 ++base_string;
9627 if (is_space_char (*base_string))
9628 ++base_string;
9629
4eed87de
AM		 9630 if ((i.index_reg = parse_register (base_string, &end_op))
9631 != NULL)
24eab124 9632 {
af6bdddf 9633 base_string = end_op;
24eab124
AM		 9634 if (is_space_char (*base_string))
9635 ++base_string;
af6bdddf
AM		 9636 if (*base_string == ',')
9637 {
9638 ++base_string;
9639 if (is_space_char (*base_string))
9640 ++base_string;
9641 }
e5cb08ac 9642 else if (*base_string != ')')
af6bdddf 9643 {
4eed87de
AM		 9644 as_bad (_("expecting `,' or `)' "
9645 "after index register in `%s'"),
af6bdddf
AM		 9646 operand_string);
9647 return 0;
9648 }
24eab124 9649 }
af6bdddf 9650 else if (*base_string == REGISTER_PREFIX)
24eab124 9651 {
f76bf5e0
L		 9652 end_op = strchr (base_string, ',');
9653 if (end_op)
9654 *end_op = '\0';
af6bdddf 9655 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9656 return 0;
9657 }
252b5132 9658
47926f60 9659 /* Check for scale factor. */
551c1ca1 9660 if (*base_string != ')')
af6bdddf 9661 {
551c1ca1
AM		 9662 char *end_scale = i386_scale (base_string);
9663
9664 if (!end_scale)
af6bdddf 9665 return 0;
24eab124 9666
551c1ca1 9667 base_string = end_scale;
af6bdddf
AM		 9668 if (is_space_char (*base_string))
9669 ++base_string;
9670 if (*base_string != ')')
9671 {
4eed87de
AM		 9672 as_bad (_("expecting `)' "
9673 "after scale factor in `%s'"),
af6bdddf
AM		 9674 operand_string);
9675 return 0;
9676 }
9677 }
9678 else if (!i.index_reg)
24eab124 9679 {
4eed87de
AM		 9680 as_bad (_("expecting index register or scale factor "
9681 "after `,'; got '%c'"),
af6bdddf 9682 *base_string);
24eab124
AM		 9683 return 0;
9684 }
9685 }
af6bdddf 9686 else if (*base_string != ')')
24eab124 9687 {
4eed87de
AM		 9688 as_bad (_("expecting `,' or `)' "
9689 "after base register in `%s'"),
af6bdddf 9690 operand_string);
24eab124
AM		 9691 return 0;
9692 }
c3332e24 9693 }
af6bdddf 9694 else if (*base_string == REGISTER_PREFIX)
c3332e24 9695 {
f76bf5e0
L		 9696 end_op = strchr (base_string, ',');
9697 if (end_op)
9698 *end_op = '\0';
af6bdddf 9699 as_bad (_("bad register name `%s'"), base_string);
24eab124 9700 return 0;
c3332e24 9701 }
24eab124
AM		 9702 }
9703
9704 /* If there's an expression beginning the operand, parse it,
9705 assuming displacement_string_start and
9706 displacement_string_end are meaningful. */
9707 if (displacement_string_start != displacement_string_end)
9708 {
9709 if (!i386_displacement (displacement_string_start,
9710 displacement_string_end))
9711 return 0;
9712 }
9713
9714 /* Special case for (%dx) while doing input/output op. */
9715 if (i.base_reg
2fb5be8d 9716 && i.base_reg->reg_type.bitfield.inoutportreg
24eab124
AM		 9717 && i.index_reg == 0
9718 && i.log2_scale_factor == 0
9719 && i.seg[i.mem_operands] == 0
40fb9820 9720 && !operand_type_check (i.types[this_operand], disp))
24eab124 9721 {
2fb5be8d 9722 i.types[this_operand] = i.base_reg->reg_type;
24eab124
AM		 9723 return 1;
9724 }
9725
eecb386c
AM		 9726 if (i386_index_check (operand_string) == 0)
9727 return 0;
5c07affc 9728 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9729 if (i.mem_operands == 0)
9730 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9731 i.mem_operands++;
9732 }
9733 else
ce8a8b2f
AM		 9734 {
9735 /* It's not a memory operand; argh! */
24eab124
AM		 9736 as_bad (_("invalid char %s beginning operand %d `%s'"),
9737 output_invalid (*op_string),
9738 this_operand + 1,
9739 op_string);
9740 return 0;
9741 }
47926f60 9742 return 1; /* Normal return. */
252b5132
RH		 9743}
9744\f
fa94de6b
RM		 9745/* Calculate the maximum variable size (i.e., excluding fr_fix)
9746 that an rs_machine_dependent frag may reach. */
9747
9748unsigned int
9749i386_frag_max_var (fragS *frag)
9750{
9751 /* The only relaxable frags are for jumps.
9752 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9753 gas_assert (frag->fr_type == rs_machine_dependent);
9754 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9755}
9756
b084df0b
L		 9757#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9758static int
8dcea932 9759elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9760{
9761 /* STT_GNU_IFUNC symbol must go through PLT. */
9762 if ((symbol_get_bfdsym (fr_symbol)->flags
9763 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9764 return 0;
9765
9766 if (!S_IS_EXTERNAL (fr_symbol))
9767 /* Symbol may be weak or local. */
9768 return !S_IS_WEAK (fr_symbol);
9769
8dcea932
L		 9770 /* Global symbols with non-default visibility can't be preempted. */
9771 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9772 return 1;
9773
9774 if (fr_var != NO_RELOC)
9775 switch ((enum bfd_reloc_code_real) fr_var)
9776 {
9777 case BFD_RELOC_386_PLT32:
9778 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9779 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9780 return 0;
9781 default:
9782 abort ();
9783 }
9784
b084df0b
L		 9785 /* Global symbols with default visibility in a shared library may be
9786 preempted by another definition. */
8dcea932 9787 return !shared;
b084df0b
L		 9788}
9789#endif
9790
ee7fcc42
AM		 9791/* md_estimate_size_before_relax()
9792
9793 Called just before relax() for rs_machine_dependent frags. The x86
9794 assembler uses these frags to handle variable size jump
9795 instructions.
9796
9797 Any symbol that is now undefined will not become defined.
9798 Return the correct fr_subtype in the frag.
9799 Return the initial "guess for variable size of frag" to caller.
9800 The guess is actually the growth beyond the fixed part. Whatever
9801 we do to grow the fixed or variable part contributes to our
9802 returned value. */
9803
252b5132 9804int
7016a5d5 9805md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9806{
252b5132 9807 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9808 check for un-relaxable symbols. On an ELF system, we can't relax
9809 an externally visible symbol, because it may be overridden by a
9810 shared library. */
9811 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9812#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9813 || (IS_ELF
8dcea932
L		 9814 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9815 fragP->fr_var))
fbeb56a4
DK		 9816#endif
9817#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9818 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9819 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9820#endif
9821 )
252b5132 9822 {
b98ef147
AM		 9823 /* Symbol is undefined in this segment, or we need to keep a
9824 reloc so that weak symbols can be overridden. */
9825 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9826 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9827 unsigned char *opcode;
9828 int old_fr_fix;
f6af82bd 9829
ee7fcc42 9830 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9831 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9832 else if (size == 2)
f6af82bd 9833 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9834#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9835 else if (need_plt32_p (fragP->fr_symbol))
9836 reloc_type = BFD_RELOC_X86_64_PLT32;
9837#endif
f6af82bd
AM		 9838 else
9839 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9840
ee7fcc42
AM		 9841 old_fr_fix = fragP->fr_fix;
9842 opcode = (unsigned char *) fragP->fr_opcode;
9843
fddf5b5b 9844 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9845 {
fddf5b5b
AM		 9846 case UNCOND_JUMP:
9847 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9848 opcode[0] = 0xe9;
252b5132 9849 fragP->fr_fix += size;
062cd5e7
AS		 9850 fix_new (fragP, old_fr_fix, size,
9851 fragP->fr_symbol,
9852 fragP->fr_offset, 1,
9853 reloc_type);
252b5132
RH		 9854 break;
9855
fddf5b5b 9856 case COND_JUMP86:
412167cb
AM		 9857 if (size == 2
9858 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9859 {
9860 /* Negate the condition, and branch past an
9861 unconditional jump. */
9862 opcode[0] ^= 1;
9863 opcode[1] = 3;
9864 /* Insert an unconditional jump. */
9865 opcode[2] = 0xe9;
9866 /* We added two extra opcode bytes, and have a two byte
9867 offset. */
9868 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9869 fix_new (fragP, old_fr_fix + 2, 2,
9870 fragP->fr_symbol,
9871 fragP->fr_offset, 1,
9872 reloc_type);
fddf5b5b
AM		 9873 break;
9874 }
9875 /* Fall through. */
9876
9877 case COND_JUMP:
412167cb
AM		 9878 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9879 {
3e02c1cc
AM		 9880 fixS *fixP;
9881
412167cb 9882 fragP->fr_fix += 1;
3e02c1cc
AM		 9883 fixP = fix_new (fragP, old_fr_fix, 1,
9884 fragP->fr_symbol,
9885 fragP->fr_offset, 1,
9886 BFD_RELOC_8_PCREL);
9887 fixP->fx_signed = 1;
412167cb
AM		 9888 break;
9889 }
93c2a809 9890
24eab124 9891 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9892 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9893 opcode[1] = opcode[0] + 0x10;
f6af82bd 9894 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9895 /* We've added an opcode byte. */
9896 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9897 fix_new (fragP, old_fr_fix + 1, size,
9898 fragP->fr_symbol,
9899 fragP->fr_offset, 1,
9900 reloc_type);
252b5132 9901 break;
fddf5b5b
AM		 9902
9903 default:
9904 BAD_CASE (fragP->fr_subtype);
9905 break;
252b5132
RH		 9906 }
9907 frag_wane (fragP);
ee7fcc42 9908 return fragP->fr_fix - old_fr_fix;
252b5132 9909 }
93c2a809 9910
93c2a809
AM		 9911 /* Guess size depending on current relax state. Initially the relax
9912 state will correspond to a short jump and we return 1, because
9913 the variable part of the frag (the branch offset) is one byte
9914 long. However, we can relax a section more than once and in that
9915 case we must either set fr_subtype back to the unrelaxed state,
9916 or return the value for the appropriate branch. */
9917 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9918}
9919
47926f60
KH		 9920/* Called after relax() is finished.
9921
9922 In: Address of frag.
9923 fr_type == rs_machine_dependent.
9924 fr_subtype is what the address relaxed to.
9925
9926 Out: Any fixSs and constants are set up.
9927 Caller will turn frag into a ".space 0". */
9928
252b5132 9929void
7016a5d5
TG		 9930md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9931 fragS *fragP)
252b5132 9932{
29b0f896 9933 unsigned char *opcode;
252b5132 9934 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9935 offsetT target_address;
9936 offsetT opcode_address;
252b5132 9937 unsigned int extension = 0;
847f7ad4 9938 offsetT displacement_from_opcode_start;
252b5132
RH		 9939
9940 opcode = (unsigned char *) fragP->fr_opcode;
9941
47926f60 9942 /* Address we want to reach in file space. */
252b5132 9943 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9944
47926f60 9945 /* Address opcode resides at in file space. */
252b5132
RH		 9946 opcode_address = fragP->fr_address + fragP->fr_fix;
9947
47926f60 9948 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9949 displacement_from_opcode_start = target_address - opcode_address;
9950
fddf5b5b 9951 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9952 {
47926f60
KH		 9953 /* Don't have to change opcode. */
9954 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9955 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9956 }
9957 else
9958 {
9959 if (no_cond_jump_promotion
9960 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9961 as_warn_where (fragP->fr_file, fragP->fr_line,
9962 _("long jump required"));
252b5132 9963
fddf5b5b
AM		 9964 switch (fragP->fr_subtype)
9965 {
9966 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9967 extension = 4; /* 1 opcode + 4 displacement */
9968 opcode[0] = 0xe9;
9969 where_to_put_displacement = &opcode[1];
9970 break;
252b5132 9971
fddf5b5b
AM		 9972 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9973 extension = 2; /* 1 opcode + 2 displacement */
9974 opcode[0] = 0xe9;
9975 where_to_put_displacement = &opcode[1];
9976 break;
252b5132 9977
fddf5b5b
AM		 9978 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9979 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9980 extension = 5; /* 2 opcode + 4 displacement */
9981 opcode[1] = opcode[0] + 0x10;
9982 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9983 where_to_put_displacement = &opcode[2];
9984 break;
252b5132 9985
fddf5b5b
AM		 9986 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9987 extension = 3; /* 2 opcode + 2 displacement */
9988 opcode[1] = opcode[0] + 0x10;
9989 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9990 where_to_put_displacement = &opcode[2];
9991 break;
252b5132 9992
fddf5b5b
AM		 9993 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9994 extension = 4;
9995 opcode[0] ^= 1;
9996 opcode[1] = 3;
9997 opcode[2] = 0xe9;
9998 where_to_put_displacement = &opcode[3];
9999 break;
10000
10001 default:
10002 BAD_CASE (fragP->fr_subtype);
10003 break;
10004 }
252b5132 10005 }
fddf5b5b 10006
7b81dfbb
AJ		 10007 /* If size if less then four we are sure that the operand fits,
10008 but if it's 4, then it could be that the displacement is larger
10009 then -/+ 2GB. */
10010 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10011 && object_64bit
10012 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 10013 + ((addressT) 1 << 31))
10014 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 10015 {
10016 as_bad_where (fragP->fr_file, fragP->fr_line,
10017 _("jump target out of range"));
10018 /* Make us emit 0. */
10019 displacement_from_opcode_start = extension;
10020 }
47926f60 10021 /* Now put displacement after opcode. */
252b5132
RH		 10022 md_number_to_chars ((char *) where_to_put_displacement,
10023 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 10024 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 10025 fragP->fr_fix += extension;
10026}
10027\f
7016a5d5 10028/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 10029 by our caller that we have all the info we need to fix it up.
10030
7016a5d5
TG		 10031 Parameter valP is the pointer to the value of the bits.
10032
252b5132
RH		 10033 On the 386, immediates, displacements, and data pointers are all in
10034 the same (little-endian) format, so we don't need to care about which
10035 we are handling. */
10036
94f592af 10037void
7016a5d5 10038md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 10039{
94f592af 10040 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 10041 valueT value = *valP;
252b5132 10042
f86103b7 10043#if !defined (TE_Mach)
93382f6d
AM		 10044 if (fixP->fx_pcrel)
10045 {
10046 switch (fixP->fx_r_type)
10047 {
5865bb77
ILT		 10048 default:
10049 break;
10050
d6ab8113
JB		 10051 case BFD_RELOC_64:
10052 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10053 break;
93382f6d 10054 case BFD_RELOC_32:
ae8887b5 10055 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 10056 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10057 break;
10058 case BFD_RELOC_16:
10059 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10060 break;
10061 case BFD_RELOC_8:
10062 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10063 break;
10064 }
10065 }
252b5132 10066
a161fe53 10067 if (fixP->fx_addsy != NULL
31312f95 10068 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 10069 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 10070 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 10071 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 10072 && !use_rela_relocations)
252b5132 10073 {
31312f95
AM		 10074 /* This is a hack. There should be a better way to handle this.
10075 This covers for the fact that bfd_install_relocation will
10076 subtract the current location (for partial_inplace, PC relative
10077 relocations); see more below. */
252b5132 10078#ifndef OBJ_AOUT
718ddfc0 10079 if (IS_ELF
252b5132
RH		 10080#ifdef TE_PE
10081 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10082#endif
10083 )
10084 value += fixP->fx_where + fixP->fx_frag->fr_address;
10085#endif
10086#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10087 if (IS_ELF)
252b5132 10088 {
6539b54b 10089 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 10090
6539b54b 10091 if ((sym_seg == seg
2f66722d 10092 || (symbol_section_p (fixP->fx_addsy)
6539b54b 10093 && sym_seg != absolute_section))
af65af87 10094 && !generic_force_reloc (fixP))
2f66722d
AM		 10095 {
10096 /* Yes, we add the values in twice. This is because
6539b54b
AM		 10097 bfd_install_relocation subtracts them out again. I think
10098 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 10099 it. FIXME. */
10100 value += fixP->fx_where + fixP->fx_frag->fr_address;
10101 }
252b5132
RH		 10102 }
10103#endif
10104#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 10105 /* For some reason, the PE format does not store a
10106 section address offset for a PC relative symbol. */
10107 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 10108 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 10109 value += md_pcrel_from (fixP);
10110#endif
10111 }
fbeb56a4 10112#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 10113 if (fixP->fx_addsy != NULL
10114 && S_IS_WEAK (fixP->fx_addsy)
10115 /* PR 16858: Do not modify weak function references. */
10116 && ! fixP->fx_pcrel)
fbeb56a4 10117 {
296a8689
NC		 10118#if !defined (TE_PEP)
10119 /* For x86 PE weak function symbols are neither PC-relative
10120 nor do they set S_IS_FUNCTION. So the only reliable way
10121 to detect them is to check the flags of their containing
10122 section. */
10123 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10124 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10125 ;
10126 else
10127#endif
fbeb56a4
DK		 10128 value -= S_GET_VALUE (fixP->fx_addsy);
10129 }
10130#endif
252b5132
RH		 10131
10132 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10133 and we must not disappoint it. */
252b5132 10134#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10135 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10136 switch (fixP->fx_r_type)
10137 {
10138 case BFD_RELOC_386_PLT32:
3e73aa7c 10139 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10140 /* Make the jump instruction point to the address of the operand. At
10141 runtime we merely add the offset to the actual PLT entry. */
10142 value = -4;
10143 break;
31312f95 10144
13ae64f3
JJ		 10145 case BFD_RELOC_386_TLS_GD:
10146 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10147 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10148 case BFD_RELOC_386_TLS_IE:
10149 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10150 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10151 case BFD_RELOC_X86_64_TLSGD:
10152 case BFD_RELOC_X86_64_TLSLD:
10153 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10154 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10155 value = 0; /* Fully resolved at runtime. No addend. */
10156 /* Fallthrough */
10157 case BFD_RELOC_386_TLS_LE:
10158 case BFD_RELOC_386_TLS_LDO_32:
10159 case BFD_RELOC_386_TLS_LE_32:
10160 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10161 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10162 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10163 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10164 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10165 break;
10166
67a4f2b7
AO		 10167 case BFD_RELOC_386_TLS_DESC_CALL:
10168 case BFD_RELOC_X86_64_TLSDESC_CALL:
10169 value = 0; /* Fully resolved at runtime. No addend. */
10170 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10171 fixP->fx_done = 0;
10172 return;
10173
47926f60
KH		 10174 case BFD_RELOC_VTABLE_INHERIT:
10175 case BFD_RELOC_VTABLE_ENTRY:
10176 fixP->fx_done = 0;
94f592af 10177 return;
47926f60
KH		 10178
10179 default:
10180 break;
10181 }
10182#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10183 *valP = value;
f86103b7 10184#endif /* !defined (TE_Mach) */
3e73aa7c 10185
3e73aa7c 10186 /* Are we finished with this relocation now? */
c6682705 10187 if (fixP->fx_addsy == NULL)
3e73aa7c 10188 fixP->fx_done = 1;
fbeb56a4
DK		 10189#if defined (OBJ_COFF) && defined (TE_PE)
10190 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10191 {
10192 fixP->fx_done = 0;
10193 /* Remember value for tc_gen_reloc. */
10194 fixP->fx_addnumber = value;
10195 /* Clear out the frag for now. */
10196 value = 0;
10197 }
10198#endif
3e73aa7c
JH		 10199 else if (use_rela_relocations)
10200 {
10201 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10202 /* Remember value for tc_gen_reloc. */
10203 fixP->fx_addnumber = value;
3e73aa7c
JH		 10204 value = 0;
10205 }
f86103b7 10206
94f592af 10207 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10208}
252b5132 10209\f
6d4af3c2 10210const char *
499ac353 10211md_atof (int type, char *litP, int *sizeP)
252b5132 10212{
499ac353
NC		 10213 /* This outputs the LITTLENUMs in REVERSE order;
10214 in accord with the bigendian 386. */
10215 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10216}
10217\f
2d545b82 10218static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10219
252b5132 10220static char *
e3bb37b5 10221output_invalid (int c)
252b5132 10222{
3882b010 10223 if (ISPRINT (c))
f9f21a03
L		 10224 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10225 "'%c'", c);
252b5132 10226 else
f9f21a03 10227 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10228 "(0x%x)", (unsigned char) c);
252b5132
RH		 10229 return output_invalid_buf;
10230}
10231
af6bdddf 10232/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10233
10234static const reg_entry *
4d1bb795 10235parse_real_register (char *reg_string, char **end_op)
252b5132 10236{
af6bdddf
AM		 10237 char *s = reg_string;
10238 char *p;
252b5132
RH		 10239 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10240 const reg_entry *r;
10241
10242 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10243 if (*s == REGISTER_PREFIX)
10244 ++s;
10245
10246 if (is_space_char (*s))
10247 ++s;
10248
10249 p = reg_name_given;
af6bdddf 10250 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10251 {
10252 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10253 return (const reg_entry *) NULL;
10254 s++;
252b5132
RH		 10255 }
10256
6588847e
DN		 10257 /* For naked regs, make sure that we are not dealing with an identifier.
10258 This prevents confusing an identifier like `eax_var' with register
10259 `eax'. */
10260 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10261 return (const reg_entry *) NULL;
10262
af6bdddf 10263 *end_op = s;
252b5132
RH		 10264
10265 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10266
5f47d35b 10267 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10268 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10269 {
0e0eea78
JB		 10270 if (!cpu_arch_flags.bitfield.cpu8087
10271 && !cpu_arch_flags.bitfield.cpu287
10272 && !cpu_arch_flags.bitfield.cpu387)
10273 return (const reg_entry *) NULL;
10274
5f47d35b
AM		 10275 if (is_space_char (*s))
10276 ++s;
10277 if (*s == '(')
10278 {
af6bdddf 10279 ++s;
5f47d35b
AM		 10280 if (is_space_char (*s))
10281 ++s;
10282 if (*s >= '0' && *s <= '7')
10283 {
db557034 10284 int fpr = *s - '0';
af6bdddf 10285 ++s;
5f47d35b
AM		 10286 if (is_space_char (*s))
10287 ++s;
10288 if (*s == ')')
10289 {
10290 *end_op = s + 1;
1e9cc1c2 10291 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10292 know (r);
10293 return r + fpr;
5f47d35b 10294 }
5f47d35b 10295 }
47926f60 10296 /* We have "%st(" then garbage. */
5f47d35b
AM		 10297 return (const reg_entry *) NULL;
10298 }
10299 }
10300
a60de03c
JB		 10301 if (r == NULL || allow_pseudo_reg)
10302 return r;
10303
0dfbf9d7 10304 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10305 return (const reg_entry *) NULL;
10306
dc821c5f 10307 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10308 || r->reg_type.bitfield.sreg3
10309 || r->reg_type.bitfield.control
10310 || r->reg_type.bitfield.debug
10311 || r->reg_type.bitfield.test)
10312 && !cpu_arch_flags.bitfield.cpui386)
10313 return (const reg_entry *) NULL;
10314
6e041cf4 10315 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10316 return (const reg_entry *) NULL;
10317
6e041cf4
JB		 10318 if (!cpu_arch_flags.bitfield.cpuavx512f)
10319 {
10320 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10321 return (const reg_entry *) NULL;
40f12533 10322
6e041cf4
JB		 10323 if (!cpu_arch_flags.bitfield.cpuavx)
10324 {
10325 if (r->reg_type.bitfield.ymmword)
10326 return (const reg_entry *) NULL;
1848e567 10327
6e041cf4
JB		 10328 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10329 return (const reg_entry *) NULL;
10330 }
10331 }
43234a1e 10332
1adf7f56
JB		 10333 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10334 return (const reg_entry *) NULL;
10335
db51cc60 10336 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10337 if (!allow_index_reg
db51cc60
L		 10338 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10339 return (const reg_entry *) NULL;
10340
1d3f8286
JB		 10341 /* Upper 16 vector registers are only available with VREX in 64bit
10342 mode, and require EVEX encoding. */
10343 if (r->reg_flags & RegVRex)
43234a1e
L		 10344 {
10345 if (!cpu_arch_flags.bitfield.cpuvrex
10346 || flag_code != CODE_64BIT)
10347 return (const reg_entry *) NULL;
1d3f8286
JB		 10348
10349 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10350 }
10351
4787f4a5
JB		 10352 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10353 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
1ae00879 10354 && flag_code != CODE_64BIT)
20f0a1fc 10355 return (const reg_entry *) NULL;
1ae00879 10356
b7240065
JB		 10357 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10358 return (const reg_entry *) NULL;
10359
252b5132
RH		 10360 return r;
10361}
4d1bb795
JB		 10362
10363/* REG_STRING starts *before* REGISTER_PREFIX. */
10364
10365static const reg_entry *
10366parse_register (char *reg_string, char **end_op)
10367{
10368 const reg_entry *r;
10369
10370 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10371 r = parse_real_register (reg_string, end_op);
10372 else
10373 r = NULL;
10374 if (!r)
10375 {
10376 char *save = input_line_pointer;
10377 char c;
10378 symbolS *symbolP;
10379
10380 input_line_pointer = reg_string;
d02603dc 10381 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10382 symbolP = symbol_find (reg_string);
10383 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10384 {
10385 const expressionS *e = symbol_get_value_expression (symbolP);
10386
0398aac5 10387 know (e->X_op == O_register);
4eed87de 10388 know (e->X_add_number >= 0
c3fe08fa 10389 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10390 r = i386_regtab + e->X_add_number;
d3bb6b49 10391 if ((r->reg_flags & RegVRex))
86fa6981 10392 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10393 *end_op = input_line_pointer;
10394 }
10395 *input_line_pointer = c;
10396 input_line_pointer = save;
10397 }
10398 return r;
10399}
10400
10401int
10402i386_parse_name (char *name, expressionS *e, char *nextcharP)
10403{
10404 const reg_entry *r;
10405 char *end = input_line_pointer;
10406
10407 *end = *nextcharP;
10408 r = parse_register (name, &input_line_pointer);
10409 if (r && end <= input_line_pointer)
10410 {
10411 *nextcharP = *input_line_pointer;
10412 *input_line_pointer = 0;
10413 e->X_op = O_register;
10414 e->X_add_number = r - i386_regtab;
10415 return 1;
10416 }
10417 input_line_pointer = end;
10418 *end = 0;
ee86248c 10419 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10420}
10421
10422void
10423md_operand (expressionS *e)
10424{
ee86248c
JB		 10425 char *end;
10426 const reg_entry *r;
4d1bb795 10427
ee86248c
JB		 10428 switch (*input_line_pointer)
10429 {
10430 case REGISTER_PREFIX:
10431 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10432 if (r)
10433 {
10434 e->X_op = O_register;
10435 e->X_add_number = r - i386_regtab;
10436 input_line_pointer = end;
10437 }
ee86248c
JB		 10438 break;
10439
10440 case '[':
9c2799c2 10441 gas_assert (intel_syntax);
ee86248c
JB		 10442 end = input_line_pointer++;
10443 expression (e);
10444 if (*input_line_pointer == ']')
10445 {
10446 ++input_line_pointer;
10447 e->X_op_symbol = make_expr_symbol (e);
10448 e->X_add_symbol = NULL;
10449 e->X_add_number = 0;
10450 e->X_op = O_index;
10451 }
10452 else
10453 {
10454 e->X_op = O_absent;
10455 input_line_pointer = end;
10456 }
10457 break;
4d1bb795
JB		 10458 }
10459}
10460
252b5132 10461\f
4cc782b5 10462#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10463const char *md_shortopts = "kVQ:sqnO::";
252b5132 10464#else
b6f8c7c4 10465const char *md_shortopts = "qnO::";
252b5132 10466#endif
6e0b89ee 10467
3e73aa7c 10468#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10469#define OPTION_64 (OPTION_MD_BASE + 1)
10470#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10471#define OPTION_MARCH (OPTION_MD_BASE + 3)
10472#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10473#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10474#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10475#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10476#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10477#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10478#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10479#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10480#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10481#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10482#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10483#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10484#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10485#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10486#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10487#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10488#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10489#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10490#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10491#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10492#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10493
99ad8390
NC		 10494struct option md_longopts[] =
10495{
3e73aa7c 10496 {"32", no_argument, NULL, OPTION_32},
321098a5 10497#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10498 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10499 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10500#endif
10501#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10502 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10503 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10504#endif
b3b91714 10505 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10506 {"march", required_argument, NULL, OPTION_MARCH},
10507 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10508 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10509 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10510 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10511 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10512 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10513 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10514 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10515 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10516 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10517 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10518 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10519# if defined (TE_PE) || defined (TE_PEP)
10520 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10521#endif
d1982f93 10522 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10523 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10524 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10525 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10526 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10527 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10528 {NULL, no_argument, NULL, 0}
10529};
10530size_t md_longopts_size = sizeof (md_longopts);
10531
10532int
17b9d67d 10533md_parse_option (int c, const char *arg)
252b5132 10534{
91d6fa6a 10535 unsigned int j;
293f5f65 10536 char *arch, *next, *saved;
9103f4f4 10537
252b5132
RH		 10538 switch (c)
10539 {
12b55ccc
L		 10540 case 'n':
10541 optimize_align_code = 0;
10542 break;
10543
a38cf1db
AM		 10544 case 'q':
10545 quiet_warnings = 1;
252b5132
RH		 10546 break;
10547
10548#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10549 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10550 should be emitted or not. FIXME: Not implemented. */
10551 case 'Q':
252b5132
RH		 10552 break;
10553
10554 /* -V: SVR4 argument to print version ID. */
10555 case 'V':
10556 print_version_id ();
10557 break;
10558
a38cf1db
AM		 10559 /* -k: Ignore for FreeBSD compatibility. */
10560 case 'k':
252b5132 10561 break;
4cc782b5
ILT		 10562
10563 case 's':
10564 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10565 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10566 break;
8dcea932
L		 10567
10568 case OPTION_MSHARED:
10569 shared = 1;
10570 break;
99ad8390 10571#endif
321098a5 10572#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10574 case OPTION_64:
10575 {
10576 const char **list, **l;
10577
3e73aa7c
JH		 10578 list = bfd_target_list ();
10579 for (l = list; *l != NULL; l++)
8620418b 10580 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10581 || strcmp (*l, "coff-x86-64") == 0
10582 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10583 || strcmp (*l, "pei-x86-64") == 0
10584 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10585 {
10586 default_arch = "x86_64";
10587 break;
10588 }
3e73aa7c 10589 if (*l == NULL)
2b5d6a91 10590 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10591 free (list);
10592 }
10593 break;
10594#endif
252b5132 10595
351f65ca 10596#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10597 case OPTION_X32:
351f65ca
L		 10598 if (IS_ELF)
10599 {
10600 const char **list, **l;
10601
10602 list = bfd_target_list ();
10603 for (l = list; *l != NULL; l++)
10604 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10605 {
10606 default_arch = "x86_64:32";
10607 break;
10608 }
10609 if (*l == NULL)
2b5d6a91 10610 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10611 free (list);
10612 }
10613 else
10614 as_fatal (_("32bit x86_64 is only supported for ELF"));
10615 break;
10616#endif
10617
6e0b89ee
AM		 10618 case OPTION_32:
10619 default_arch = "i386";
10620 break;
10621
b3b91714
AM		 10622 case OPTION_DIVIDE:
10623#ifdef SVR4_COMMENT_CHARS
10624 {
10625 char *n, *t;
10626 const char *s;
10627
add39d23 10628 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10629 t = n;
10630 for (s = i386_comment_chars; *s != '\0'; s++)
10631 if (*s != '/')
10632 *t++ = *s;
10633 *t = '\0';
10634 i386_comment_chars = n;
10635 }
10636#endif
10637 break;
10638
9103f4f4 10639 case OPTION_MARCH:
293f5f65
L		 10640 saved = xstrdup (arg);
10641 arch = saved;
10642 /* Allow -march=+nosse. */
10643 if (*arch == '+')
10644 arch++;
6305a203 10645 do
9103f4f4 10646 {
6305a203 10647 if (*arch == '.')
2b5d6a91 10648 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10649 next = strchr (arch, '+');
10650 if (next)
10651 *next++ = '\0';
91d6fa6a 10652 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10653 {
91d6fa6a 10654 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10655 {
6305a203 10656 /* Processor. */
1ded5609
JB		 10657 if (! cpu_arch[j].flags.bitfield.cpui386)
10658 continue;
10659
91d6fa6a 10660 cpu_arch_name = cpu_arch[j].name;
6305a203 10661 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10662 cpu_arch_flags = cpu_arch[j].flags;
10663 cpu_arch_isa = cpu_arch[j].type;
10664 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10665 if (!cpu_arch_tune_set)
10666 {
10667 cpu_arch_tune = cpu_arch_isa;
10668 cpu_arch_tune_flags = cpu_arch_isa_flags;
10669 }
10670 break;
10671 }
91d6fa6a
NC		 10672 else if (*cpu_arch [j].name == '.'
10673 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10674 {
33eaf5de 10675 /* ISA extension. */
6305a203 10676 i386_cpu_flags flags;
309d3373 10677
293f5f65
L		 10678 flags = cpu_flags_or (cpu_arch_flags,
10679 cpu_arch[j].flags);
81486035 10680
5b64d091 10681 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10682 {
10683 if (cpu_sub_arch_name)
10684 {
10685 char *name = cpu_sub_arch_name;
10686 cpu_sub_arch_name = concat (name,
91d6fa6a 10687 cpu_arch[j].name,
1bf57e9f 10688 (const char *) NULL);
6305a203
L		 10689 free (name);
10690 }
10691 else
91d6fa6a 10692 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10693 cpu_arch_flags = flags;
a586129e 10694 cpu_arch_isa_flags = flags;
6305a203 10695 }
0089dace
L		 10696 else
10697 cpu_arch_isa_flags
10698 = cpu_flags_or (cpu_arch_isa_flags,
10699 cpu_arch[j].flags);
6305a203 10700 break;
ccc9c027 10701 }
9103f4f4 10702 }
6305a203 10703
293f5f65
L		 10704 if (j >= ARRAY_SIZE (cpu_arch))
10705 {
33eaf5de 10706 /* Disable an ISA extension. */
293f5f65
L		 10707 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10708 if (strcmp (arch, cpu_noarch [j].name) == 0)
10709 {
10710 i386_cpu_flags flags;
10711
10712 flags = cpu_flags_and_not (cpu_arch_flags,
10713 cpu_noarch[j].flags);
10714 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10715 {
10716 if (cpu_sub_arch_name)
10717 {
10718 char *name = cpu_sub_arch_name;
10719 cpu_sub_arch_name = concat (arch,
10720 (const char *) NULL);
10721 free (name);
10722 }
10723 else
10724 cpu_sub_arch_name = xstrdup (arch);
10725 cpu_arch_flags = flags;
10726 cpu_arch_isa_flags = flags;
10727 }
10728 break;
10729 }
10730
10731 if (j >= ARRAY_SIZE (cpu_noarch))
10732 j = ARRAY_SIZE (cpu_arch);
10733 }
10734
91d6fa6a 10735 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10736 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10737
10738 arch = next;
9103f4f4 10739 }
293f5f65
L		 10740 while (next != NULL);
10741 free (saved);
9103f4f4
L		 10742 break;
10743
10744 case OPTION_MTUNE:
10745 if (*arg == '.')
2b5d6a91 10746 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10747 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10748 {
91d6fa6a 10749 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10750 {
ccc9c027 10751 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10752 cpu_arch_tune = cpu_arch [j].type;
10753 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10754 break;
10755 }
10756 }
91d6fa6a 10757 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10758 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10759 break;
10760
1efbbeb4
L		 10761 case OPTION_MMNEMONIC:
10762 if (strcasecmp (arg, "att") == 0)
10763 intel_mnemonic = 0;
10764 else if (strcasecmp (arg, "intel") == 0)
10765 intel_mnemonic = 1;
10766 else
2b5d6a91 10767 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10768 break;
10769
10770 case OPTION_MSYNTAX:
10771 if (strcasecmp (arg, "att") == 0)
10772 intel_syntax = 0;
10773 else if (strcasecmp (arg, "intel") == 0)
10774 intel_syntax = 1;
10775 else
2b5d6a91 10776 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10777 break;
10778
10779 case OPTION_MINDEX_REG:
10780 allow_index_reg = 1;
10781 break;
10782
10783 case OPTION_MNAKED_REG:
10784 allow_naked_reg = 1;
10785 break;
10786
c0f3af97
L		 10787 case OPTION_MSSE2AVX:
10788 sse2avx = 1;
10789 break;
10790
daf50ae7
L		 10791 case OPTION_MSSE_CHECK:
10792 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10793 sse_check = check_error;
daf50ae7 10794 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10795 sse_check = check_warning;
daf50ae7 10796 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10797 sse_check = check_none;
daf50ae7 10798 else
2b5d6a91 10799 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10800 break;
10801
7bab8ab5
JB		 10802 case OPTION_MOPERAND_CHECK:
10803 if (strcasecmp (arg, "error") == 0)
10804 operand_check = check_error;
10805 else if (strcasecmp (arg, "warning") == 0)
10806 operand_check = check_warning;
10807 else if (strcasecmp (arg, "none") == 0)
10808 operand_check = check_none;
10809 else
10810 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10811 break;
10812
539f890d
L		 10813 case OPTION_MAVXSCALAR:
10814 if (strcasecmp (arg, "128") == 0)
10815 avxscalar = vex128;
10816 else if (strcasecmp (arg, "256") == 0)
10817 avxscalar = vex256;
10818 else
2b5d6a91 10819 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10820 break;
10821
7e8b059b
L		 10822 case OPTION_MADD_BND_PREFIX:
10823 add_bnd_prefix = 1;
10824 break;
10825
43234a1e
L		 10826 case OPTION_MEVEXLIG:
10827 if (strcmp (arg, "128") == 0)
10828 evexlig = evexl128;
10829 else if (strcmp (arg, "256") == 0)
10830 evexlig = evexl256;
10831 else if (strcmp (arg, "512") == 0)
10832 evexlig = evexl512;
10833 else
10834 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10835 break;
10836
d3d3c6db
IT		 10837 case OPTION_MEVEXRCIG:
10838 if (strcmp (arg, "rne") == 0)
10839 evexrcig = rne;
10840 else if (strcmp (arg, "rd") == 0)
10841 evexrcig = rd;
10842 else if (strcmp (arg, "ru") == 0)
10843 evexrcig = ru;
10844 else if (strcmp (arg, "rz") == 0)
10845 evexrcig = rz;
10846 else
10847 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10848 break;
10849
43234a1e
L		 10850 case OPTION_MEVEXWIG:
10851 if (strcmp (arg, "0") == 0)
10852 evexwig = evexw0;
10853 else if (strcmp (arg, "1") == 0)
10854 evexwig = evexw1;
10855 else
10856 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10857 break;
10858
167ad85b
TG		 10859# if defined (TE_PE) || defined (TE_PEP)
10860 case OPTION_MBIG_OBJ:
10861 use_big_obj = 1;
10862 break;
10863#endif
10864
d1982f93 10865 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10866 if (strcasecmp (arg, "yes") == 0)
10867 omit_lock_prefix = 1;
10868 else if (strcasecmp (arg, "no") == 0)
10869 omit_lock_prefix = 0;
10870 else
10871 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10872 break;
10873
e4e00185
AS		 10874 case OPTION_MFENCE_AS_LOCK_ADD:
10875 if (strcasecmp (arg, "yes") == 0)
10876 avoid_fence = 1;
10877 else if (strcasecmp (arg, "no") == 0)
10878 avoid_fence = 0;
10879 else
10880 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10881 break;
10882
0cb4071e
L		 10883 case OPTION_MRELAX_RELOCATIONS:
10884 if (strcasecmp (arg, "yes") == 0)
10885 generate_relax_relocations = 1;
10886 else if (strcasecmp (arg, "no") == 0)
10887 generate_relax_relocations = 0;
10888 else
10889 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10890 break;
10891
5db04b09 10892 case OPTION_MAMD64:
e89c5eaa 10893 intel64 = 0;
5db04b09
L		 10894 break;
10895
10896 case OPTION_MINTEL64:
e89c5eaa 10897 intel64 = 1;
5db04b09
L		 10898 break;
10899
b6f8c7c4
L		 10900 case 'O':
10901 if (arg == NULL)
10902 {
10903 optimize = 1;
10904 /* Turn off -Os. */
10905 optimize_for_space = 0;
10906 }
10907 else if (*arg == 's')
10908 {
10909 optimize_for_space = 1;
10910 /* Turn on all encoding optimizations. */
10911 optimize = -1;
10912 }
10913 else
10914 {
10915 optimize = atoi (arg);
10916 /* Turn off -Os. */
10917 optimize_for_space = 0;
10918 }
10919 break;
10920
252b5132
RH		 10921 default:
10922 return 0;
10923 }
10924 return 1;
10925}
10926
8a2c8fef
L		 10927#define MESSAGE_TEMPLATE \
10928" "
10929
293f5f65
L		 10930static char *
10931output_message (FILE *stream, char *p, char *message, char *start,
10932 int *left_p, const char *name, int len)
10933{
10934 int size = sizeof (MESSAGE_TEMPLATE);
10935 int left = *left_p;
10936
10937 /* Reserve 2 spaces for ", " or ",\0" */
10938 left -= len + 2;
10939
10940 /* Check if there is any room. */
10941 if (left >= 0)
10942 {
10943 if (p != start)
10944 {
10945 *p++ = ',';
10946 *p++ = ' ';
10947 }
10948 p = mempcpy (p, name, len);
10949 }
10950 else
10951 {
10952 /* Output the current message now and start a new one. */
10953 *p++ = ',';
10954 *p = '\0';
10955 fprintf (stream, "%s\n", message);
10956 p = start;
10957 left = size - (start - message) - len - 2;
10958
10959 gas_assert (left >= 0);
10960
10961 p = mempcpy (p, name, len);
10962 }
10963
10964 *left_p = left;
10965 return p;
10966}
10967
8a2c8fef 10968static void
1ded5609 10969show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10970{
10971 static char message[] = MESSAGE_TEMPLATE;
10972 char *start = message + 27;
10973 char *p;
10974 int size = sizeof (MESSAGE_TEMPLATE);
10975 int left;
10976 const char *name;
10977 int len;
10978 unsigned int j;
10979
10980 p = start;
10981 left = size - (start - message);
10982 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10983 {
10984 /* Should it be skipped? */
10985 if (cpu_arch [j].skip)
10986 continue;
10987
10988 name = cpu_arch [j].name;
10989 len = cpu_arch [j].len;
10990 if (*name == '.')
10991 {
10992 /* It is an extension. Skip if we aren't asked to show it. */
10993 if (ext)
10994 {
10995 name++;
10996 len--;
10997 }
10998 else
10999 continue;
11000 }
11001 else if (ext)
11002 {
11003 /* It is an processor. Skip if we show only extension. */
11004 continue;
11005 }
1ded5609
JB		 11006 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11007 {
11008 /* It is an impossible processor - skip. */
11009 continue;
11010 }
8a2c8fef 11011
293f5f65 11012 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 11013 }
11014
293f5f65
L		 11015 /* Display disabled extensions. */
11016 if (ext)
11017 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11018 {
11019 name = cpu_noarch [j].name;
11020 len = cpu_noarch [j].len;
11021 p = output_message (stream, p, message, start, &left, name,
11022 len);
11023 }
11024
8a2c8fef
L		 11025 *p = '\0';
11026 fprintf (stream, "%s\n", message);
11027}
11028
252b5132 11029void
8a2c8fef 11030md_show_usage (FILE *stream)
252b5132 11031{
4cc782b5
ILT		 11032#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11033 fprintf (stream, _("\
a38cf1db
AM		 11034 -Q ignored\n\
11035 -V print assembler version number\n\
b3b91714
AM		 11036 -k ignored\n"));
11037#endif
11038 fprintf (stream, _("\
12b55ccc 11039 -n Do not optimize code alignment\n\
b3b91714
AM		 11040 -q quieten some warnings\n"));
11041#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11042 fprintf (stream, _("\
a38cf1db 11043 -s ignored\n"));
b3b91714 11044#endif
321098a5
L		 11045#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11046 || defined (TE_PE) || defined (TE_PEP))
751d281c 11047 fprintf (stream, _("\
570561f7 11048 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 11049#endif
b3b91714
AM		 11050#ifdef SVR4_COMMENT_CHARS
11051 fprintf (stream, _("\
11052 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 11053#else
11054 fprintf (stream, _("\
b3b91714 11055 --divide ignored\n"));
4cc782b5 11056#endif
9103f4f4 11057 fprintf (stream, _("\
6305a203 11058 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 11059 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 11060 show_arch (stream, 0, 1);
8a2c8fef
L		 11061 fprintf (stream, _("\
11062 EXTENSION is combination of:\n"));
1ded5609 11063 show_arch (stream, 1, 0);
6305a203 11064 fprintf (stream, _("\
8a2c8fef 11065 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 11066 show_arch (stream, 0, 0);
ba104c83 11067 fprintf (stream, _("\
c0f3af97
L		 11068 -msse2avx encode SSE instructions with VEX prefix\n"));
11069 fprintf (stream, _("\
daf50ae7
L		 11070 -msse-check=[none|error|warning]\n\
11071 check SSE instructions\n"));
11072 fprintf (stream, _("\
7bab8ab5
JB		 11073 -moperand-check=[none|error|warning]\n\
11074 check operand combinations for validity\n"));
11075 fprintf (stream, _("\
539f890d
L		 11076 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11077 length\n"));
11078 fprintf (stream, _("\
43234a1e
L		 11079 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11080 length\n"));
11081 fprintf (stream, _("\
11082 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11083 for EVEX.W bit ignored instructions\n"));
11084 fprintf (stream, _("\
d3d3c6db
IT		 11085 -mevexrcig=[rne|rd|ru|rz]\n\
11086 encode EVEX instructions with specific EVEX.RC value\n\
11087 for SAE-only ignored instructions\n"));
11088 fprintf (stream, _("\
ba104c83
L		 11089 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11090 fprintf (stream, _("\
11091 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11092 fprintf (stream, _("\
11093 -mindex-reg support pseudo index registers\n"));
11094 fprintf (stream, _("\
11095 -mnaked-reg don't require `%%' prefix for registers\n"));
11096 fprintf (stream, _("\
7e8b059b 11097 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 11098 fprintf (stream, _("\
11099 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 11100# if defined (TE_PE) || defined (TE_PEP)
11101 fprintf (stream, _("\
11102 -mbig-obj generate big object files\n"));
11103#endif
d022bddd
IT		 11104 fprintf (stream, _("\
11105 -momit-lock-prefix=[no|yes]\n\
11106 strip all lock prefixes\n"));
5db04b09 11107 fprintf (stream, _("\
e4e00185
AS		 11108 -mfence-as-lock-add=[no|yes]\n\
11109 encode lfence, mfence and sfence as\n\
11110 lock addl $0x0, (%%{re}sp)\n"));
11111 fprintf (stream, _("\
0cb4071e
L		 11112 -mrelax-relocations=[no|yes]\n\
11113 generate relax relocations\n"));
11114 fprintf (stream, _("\
5db04b09
L		 11115 -mamd64 accept only AMD64 ISA\n"));
11116 fprintf (stream, _("\
11117 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 11118}
11119
3e73aa7c 11120#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11121 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11122 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11123
11124/* Pick the target format to use. */
11125
47926f60 11126const char *
e3bb37b5 11127i386_target_format (void)
252b5132 11128{
351f65ca
L		 11129 if (!strncmp (default_arch, "x86_64", 6))
11130 {
11131 update_code_flag (CODE_64BIT, 1);
11132 if (default_arch[6] == '\0')
7f56bc95 11133 x86_elf_abi = X86_64_ABI;
351f65ca 11134 else
7f56bc95 11135 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11136 }
3e73aa7c 11137 else if (!strcmp (default_arch, "i386"))
78f12dd3 11138 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11139 else if (!strcmp (default_arch, "iamcu"))
11140 {
11141 update_code_flag (CODE_32BIT, 1);
11142 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11143 {
11144 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11145 cpu_arch_name = "iamcu";
11146 cpu_sub_arch_name = NULL;
11147 cpu_arch_flags = iamcu_flags;
11148 cpu_arch_isa = PROCESSOR_IAMCU;
11149 cpu_arch_isa_flags = iamcu_flags;
11150 if (!cpu_arch_tune_set)
11151 {
11152 cpu_arch_tune = cpu_arch_isa;
11153 cpu_arch_tune_flags = cpu_arch_isa_flags;
11154 }
11155 }
8d471ec1 11156 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11157 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11158 cpu_arch_name);
11159 }
3e73aa7c 11160 else
2b5d6a91 11161 as_fatal (_("unknown architecture"));
89507696
JB		 11162
11163 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11164 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11165 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11166 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11167
252b5132
RH		 11168 switch (OUTPUT_FLAVOR)
11169 {
9384f2ff 11170#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11171 case bfd_target_aout_flavour:
47926f60 11172 return AOUT_TARGET_FORMAT;
4c63da97 11173#endif
9384f2ff
AM		 11174#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11175# if defined (TE_PE) || defined (TE_PEP)
11176 case bfd_target_coff_flavour:
167ad85b
TG		 11177 if (flag_code == CODE_64BIT)
11178 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11179 else
11180 return "pe-i386";
9384f2ff 11181# elif defined (TE_GO32)
0561d57c
JK		 11182 case bfd_target_coff_flavour:
11183 return "coff-go32";
9384f2ff 11184# else
252b5132
RH		 11185 case bfd_target_coff_flavour:
11186 return "coff-i386";
9384f2ff 11187# endif
4c63da97 11188#endif
3e73aa7c 11189#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11190 case bfd_target_elf_flavour:
3e73aa7c 11191 {
351f65ca
L		 11192 const char *format;
11193
11194 switch (x86_elf_abi)
4fa24527 11195 {
351f65ca
L		 11196 default:
11197 format = ELF_TARGET_FORMAT;
11198 break;
7f56bc95 11199 case X86_64_ABI:
351f65ca 11200 use_rela_relocations = 1;
4fa24527 11201 object_64bit = 1;
351f65ca
L		 11202 format = ELF_TARGET_FORMAT64;
11203 break;
7f56bc95 11204 case X86_64_X32_ABI:
4fa24527 11205 use_rela_relocations = 1;
351f65ca 11206 object_64bit = 1;
862be3fb 11207 disallow_64bit_reloc = 1;
351f65ca
L		 11208 format = ELF_TARGET_FORMAT32;
11209 break;
4fa24527 11210 }
3632d14b 11211 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11212 {
7f56bc95 11213 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11214 as_fatal (_("Intel L1OM is 64bit only"));
11215 return ELF_TARGET_L1OM_FORMAT;
11216 }
b49f93f6 11217 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11218 {
11219 if (x86_elf_abi != X86_64_ABI)
11220 as_fatal (_("Intel K1OM is 64bit only"));
11221 return ELF_TARGET_K1OM_FORMAT;
11222 }
81486035
L		 11223 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11224 {
11225 if (x86_elf_abi != I386_ABI)
11226 as_fatal (_("Intel MCU is 32bit only"));
11227 return ELF_TARGET_IAMCU_FORMAT;
11228 }
8a9036a4 11229 else
351f65ca 11230 return format;
3e73aa7c 11231 }
e57f8c65
TG		 11232#endif
11233#if defined (OBJ_MACH_O)
11234 case bfd_target_mach_o_flavour:
d382c579
TG		 11235 if (flag_code == CODE_64BIT)
11236 {
11237 use_rela_relocations = 1;
11238 object_64bit = 1;
11239 return "mach-o-x86-64";
11240 }
11241 else
11242 return "mach-o-i386";
4c63da97 11243#endif
252b5132
RH		 11244 default:
11245 abort ();
11246 return NULL;
11247 }
11248}
11249
47926f60 11250#endif /* OBJ_MAYBE_ more than one */
252b5132 11251\f
252b5132 11252symbolS *
7016a5d5 11253md_undefined_symbol (char *name)
252b5132 11254{
18dc2407
ILT		 11255 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11256 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11257 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11258 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11259 {
11260 if (!GOT_symbol)
11261 {
11262 if (symbol_find (name))
11263 as_bad (_("GOT already in symbol table"));
11264 GOT_symbol = symbol_new (name, undefined_section,
11265 (valueT) 0, &zero_address_frag);
11266 };
11267 return GOT_symbol;
11268 }
252b5132
RH		 11269 return 0;
11270}
11271
11272/* Round up a section size to the appropriate boundary. */
47926f60 11273
252b5132 11274valueT
7016a5d5 11275md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11276{
4c63da97
AM		 11277#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11278 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11279 {
11280 /* For a.out, force the section size to be aligned. If we don't do
11281 this, BFD will align it for us, but it will not write out the
11282 final bytes of the section. This may be a bug in BFD, but it is
11283 easier to fix it here since that is how the other a.out targets
11284 work. */
11285 int align;
11286
11287 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11288 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11289 }
252b5132
RH		 11290#endif
11291
11292 return size;
11293}
11294
11295/* On the i386, PC-relative offsets are relative to the start of the
11296 next instruction. That is, the address of the offset, plus its
11297 size, since the offset is always the last part of the insn. */
11298
11299long
e3bb37b5 11300md_pcrel_from (fixS *fixP)
252b5132
RH		 11301{
11302 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11303}
11304
11305#ifndef I386COFF
11306
11307static void
e3bb37b5 11308s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11309{
29b0f896 11310 int temp;
252b5132 11311
8a75718c
JB		 11312#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11313 if (IS_ELF)
11314 obj_elf_section_change_hook ();
11315#endif
252b5132
RH		 11316 temp = get_absolute_expression ();
11317 subseg_set (bss_section, (subsegT) temp);
11318 demand_empty_rest_of_line ();
11319}
11320
11321#endif
11322
252b5132 11323void
e3bb37b5 11324i386_validate_fix (fixS *fixp)
252b5132 11325{
02a86693 11326 if (fixp->fx_subsy)
252b5132 11327 {
02a86693 11328 if (fixp->fx_subsy == GOT_symbol)
23df1078 11329 {
02a86693
L		 11330 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11331 {
11332 if (!object_64bit)
11333 abort ();
11334#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11335 if (fixp->fx_tcbit2)
56ceb5b5
L		 11336 fixp->fx_r_type = (fixp->fx_tcbit
11337 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11338 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11339 else
11340#endif
11341 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11342 }
d6ab8113 11343 else
02a86693
L		 11344 {
11345 if (!object_64bit)
11346 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11347 else
11348 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11349 }
11350 fixp->fx_subsy = 0;
23df1078 11351 }
252b5132 11352 }
02a86693
L		 11353#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11354 else if (!object_64bit)
11355 {
11356 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11357 && fixp->fx_tcbit2)
11358 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11359 }
11360#endif
252b5132
RH		 11361}
11362
252b5132 11363arelent *
7016a5d5 11364tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11365{
11366 arelent *rel;
11367 bfd_reloc_code_real_type code;
11368
11369 switch (fixp->fx_r_type)
11370 {
8ce3d284 11371#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11372 case BFD_RELOC_SIZE32:
11373 case BFD_RELOC_SIZE64:
11374 if (S_IS_DEFINED (fixp->fx_addsy)
11375 && !S_IS_EXTERNAL (fixp->fx_addsy))
11376 {
11377 /* Resolve size relocation against local symbol to size of
11378 the symbol plus addend. */
11379 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11380 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11381 && !fits_in_unsigned_long (value))
11382 as_bad_where (fixp->fx_file, fixp->fx_line,
11383 _("symbol size computation overflow"));
11384 fixp->fx_addsy = NULL;
11385 fixp->fx_subsy = NULL;
11386 md_apply_fix (fixp, (valueT *) &value, NULL);
11387 return NULL;
11388 }
8ce3d284 11389#endif
1a0670f3 11390 /* Fall through. */
8fd4256d 11391
3e73aa7c
JH		 11392 case BFD_RELOC_X86_64_PLT32:
11393 case BFD_RELOC_X86_64_GOT32:
11394 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11395 case BFD_RELOC_X86_64_GOTPCRELX:
11396 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11397 case BFD_RELOC_386_PLT32:
11398 case BFD_RELOC_386_GOT32:
02a86693 11399 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11400 case BFD_RELOC_386_GOTOFF:
11401 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11402 case BFD_RELOC_386_TLS_GD:
11403 case BFD_RELOC_386_TLS_LDM:
11404 case BFD_RELOC_386_TLS_LDO_32:
11405 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11406 case BFD_RELOC_386_TLS_IE:
11407 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11408 case BFD_RELOC_386_TLS_LE_32:
11409 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11410 case BFD_RELOC_386_TLS_GOTDESC:
11411 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11412 case BFD_RELOC_X86_64_TLSGD:
11413 case BFD_RELOC_X86_64_TLSLD:
11414 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11415 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11416 case BFD_RELOC_X86_64_GOTTPOFF:
11417 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11418 case BFD_RELOC_X86_64_TPOFF64:
11419 case BFD_RELOC_X86_64_GOTOFF64:
11420 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11421 case BFD_RELOC_X86_64_GOT64:
11422 case BFD_RELOC_X86_64_GOTPCREL64:
11423 case BFD_RELOC_X86_64_GOTPC64:
11424 case BFD_RELOC_X86_64_GOTPLT64:
11425 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11426 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11427 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11428 case BFD_RELOC_RVA:
11429 case BFD_RELOC_VTABLE_ENTRY:
11430 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11431#ifdef TE_PE
11432 case BFD_RELOC_32_SECREL:
11433#endif
252b5132
RH		 11434 code = fixp->fx_r_type;
11435 break;
dbbaec26
L		 11436 case BFD_RELOC_X86_64_32S:
11437 if (!fixp->fx_pcrel)
11438 {
11439 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11440 code = fixp->fx_r_type;
11441 break;
11442 }
1a0670f3 11443 /* Fall through. */
252b5132 11444 default:
93382f6d 11445 if (fixp->fx_pcrel)
252b5132 11446 {
93382f6d
AM		 11447 switch (fixp->fx_size)
11448 {
11449 default:
b091f402
AM		 11450 as_bad_where (fixp->fx_file, fixp->fx_line,
11451 _("can not do %d byte pc-relative relocation"),
11452 fixp->fx_size);
93382f6d
AM		 11453 code = BFD_RELOC_32_PCREL;
11454 break;
11455 case 1: code = BFD_RELOC_8_PCREL; break;
11456 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11457 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11458#ifdef BFD64
11459 case 8: code = BFD_RELOC_64_PCREL; break;
11460#endif
93382f6d
AM		 11461 }
11462 }
11463 else
11464 {
11465 switch (fixp->fx_size)
11466 {
11467 default:
b091f402
AM		 11468 as_bad_where (fixp->fx_file, fixp->fx_line,
11469 _("can not do %d byte relocation"),
11470 fixp->fx_size);
93382f6d
AM		 11471 code = BFD_RELOC_32;
11472 break;
11473 case 1: code = BFD_RELOC_8; break;
11474 case 2: code = BFD_RELOC_16; break;
11475 case 4: code = BFD_RELOC_32; break;
937149dd 11476#ifdef BFD64
3e73aa7c 11477 case 8: code = BFD_RELOC_64; break;
937149dd 11478#endif
93382f6d 11479 }
252b5132
RH		 11480 }
11481 break;
11482 }
252b5132 11483
d182319b
JB		 11484 if ((code == BFD_RELOC_32
11485 || code == BFD_RELOC_32_PCREL
11486 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11487 && GOT_symbol
11488 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11489 {
4fa24527 11490 if (!object_64bit)
d6ab8113
JB		 11491 code = BFD_RELOC_386_GOTPC;
11492 else
11493 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11494 }
7b81dfbb
AJ		 11495 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11496 && GOT_symbol
11497 && fixp->fx_addsy == GOT_symbol)
11498 {
11499 code = BFD_RELOC_X86_64_GOTPC64;
11500 }
252b5132 11501
add39d23
TS		 11502 rel = XNEW (arelent);
11503 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11504 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11505
11506 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11507
3e73aa7c
JH		 11508 if (!use_rela_relocations)
11509 {
11510 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11511 vtable entry to be used in the relocation's section offset. */
11512 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11513 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11514#if defined (OBJ_COFF) && defined (TE_PE)
11515 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11516 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11517 else
11518#endif
c6682705 11519 rel->addend = 0;
3e73aa7c
JH		 11520 }
11521 /* Use the rela in 64bit mode. */
252b5132 11522 else
3e73aa7c 11523 {
862be3fb
L		 11524 if (disallow_64bit_reloc)
11525 switch (code)
11526 {
862be3fb
L		 11527 case BFD_RELOC_X86_64_DTPOFF64:
11528 case BFD_RELOC_X86_64_TPOFF64:
11529 case BFD_RELOC_64_PCREL:
11530 case BFD_RELOC_X86_64_GOTOFF64:
11531 case BFD_RELOC_X86_64_GOT64:
11532 case BFD_RELOC_X86_64_GOTPCREL64:
11533 case BFD_RELOC_X86_64_GOTPC64:
11534 case BFD_RELOC_X86_64_GOTPLT64:
11535 case BFD_RELOC_X86_64_PLTOFF64:
11536 as_bad_where (fixp->fx_file, fixp->fx_line,
11537 _("cannot represent relocation type %s in x32 mode"),
11538 bfd_get_reloc_code_name (code));
11539 break;
11540 default:
11541 break;
11542 }
11543
062cd5e7
AS		 11544 if (!fixp->fx_pcrel)
11545 rel->addend = fixp->fx_offset;
11546 else
11547 switch (code)
11548 {
11549 case BFD_RELOC_X86_64_PLT32:
11550 case BFD_RELOC_X86_64_GOT32:
11551 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11552 case BFD_RELOC_X86_64_GOTPCRELX:
11553 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11554 case BFD_RELOC_X86_64_TLSGD:
11555 case BFD_RELOC_X86_64_TLSLD:
11556 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11557 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11558 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11559 rel->addend = fixp->fx_offset - fixp->fx_size;
11560 break;
11561 default:
11562 rel->addend = (section->vma
11563 - fixp->fx_size
11564 + fixp->fx_addnumber
11565 + md_pcrel_from (fixp));
11566 break;
11567 }
3e73aa7c
JH		 11568 }
11569
252b5132
RH		 11570 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11571 if (rel->howto == NULL)
11572 {
11573 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11574 _("cannot represent relocation type %s"),
252b5132
RH		 11575 bfd_get_reloc_code_name (code));
11576 /* Set howto to a garbage value so that we can keep going. */
11577 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11578 gas_assert (rel->howto != NULL);
252b5132
RH		 11579 }
11580
11581 return rel;
11582}
11583
ee86248c 11584#include "tc-i386-intel.c"
54cfded0 11585
a60de03c
JB		 11586void
11587tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11588{
a60de03c
JB		 11589 int saved_naked_reg;
11590 char saved_register_dot;
54cfded0 11591
a60de03c
JB		 11592 saved_naked_reg = allow_naked_reg;
11593 allow_naked_reg = 1;
11594 saved_register_dot = register_chars['.'];
11595 register_chars['.'] = '.';
11596 allow_pseudo_reg = 1;
11597 expression_and_evaluate (exp);
11598 allow_pseudo_reg = 0;
11599 register_chars['.'] = saved_register_dot;
11600 allow_naked_reg = saved_naked_reg;
11601
e96d56a1 11602 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11603 {
a60de03c
JB		 11604 if ((addressT) exp->X_add_number < i386_regtab_size)
11605 {
11606 exp->X_op = O_constant;
11607 exp->X_add_number = i386_regtab[exp->X_add_number]
11608 .dw2_regnum[flag_code >> 1];
11609 }
11610 else
11611 exp->X_op = O_illegal;
54cfded0 11612 }
54cfded0
AM		 11613}
11614
11615void
11616tc_x86_frame_initial_instructions (void)
11617{
a60de03c
JB		 11618 static unsigned int sp_regno[2];
11619
11620 if (!sp_regno[flag_code >> 1])
11621 {
11622 char *saved_input = input_line_pointer;
11623 char sp[][4] = {"esp", "rsp"};
11624 expressionS exp;
a4447b93 11625
a60de03c
JB		 11626 input_line_pointer = sp[flag_code >> 1];
11627 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11628 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11629 sp_regno[flag_code >> 1] = exp.X_add_number;
11630 input_line_pointer = saved_input;
11631 }
a4447b93 11632
61ff971f
L		 11633 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11634 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11635}
d2b2c203 11636
d7921315
L		 11637int
11638x86_dwarf2_addr_size (void)
11639{
11640#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11641 if (x86_elf_abi == X86_64_X32_ABI)
11642 return 4;
11643#endif
11644 return bfd_arch_bits_per_address (stdoutput) / 8;
11645}
11646
d2b2c203
DJ		 11647int
11648i386_elf_section_type (const char *str, size_t len)
11649{
11650 if (flag_code == CODE_64BIT
11651 && len == sizeof ("unwind") - 1
11652 && strncmp (str, "unwind", 6) == 0)
11653 return SHT_X86_64_UNWIND;
11654
11655 return -1;
11656}
bb41ade5 11657
ad5fec3b
EB		 11658#ifdef TE_SOLARIS
11659void
11660i386_solaris_fix_up_eh_frame (segT sec)
11661{
11662 if (flag_code == CODE_64BIT)
11663 elf_section_type (sec) = SHT_X86_64_UNWIND;
11664}
11665#endif
11666
bb41ade5
AM		 11667#ifdef TE_PE
11668void
11669tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11670{
91d6fa6a 11671 expressionS exp;
bb41ade5 11672
91d6fa6a
NC		 11673 exp.X_op = O_secrel;
11674 exp.X_add_symbol = symbol;
11675 exp.X_add_number = 0;
11676 emit_expr (&exp, size);
bb41ade5
AM		 11677}
11678#endif
3b22753a
L		 11679
11680#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11681/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11682
01e1a5bc 11683bfd_vma
6d4af3c2 11684x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11685{
11686 if (flag_code == CODE_64BIT)
11687 {
11688 if (letter == 'l')
11689 return SHF_X86_64_LARGE;
11690
8f3bae45 11691 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11692 }
3b22753a 11693 else
8f3bae45 11694 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11695 return -1;
11696}
11697
01e1a5bc 11698bfd_vma
3b22753a
L		 11699x86_64_section_word (char *str, size_t len)
11700{
8620418b 11701 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11702 return SHF_X86_64_LARGE;
11703
11704 return -1;
11705}
11706
11707static void
11708handle_large_common (int small ATTRIBUTE_UNUSED)
11709{
11710 if (flag_code != CODE_64BIT)
11711 {
11712 s_comm_internal (0, elf_common_parse);
11713 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11714 }
11715 else
11716 {
11717 static segT lbss_section;
11718 asection *saved_com_section_ptr = elf_com_section_ptr;
11719 asection *saved_bss_section = bss_section;
11720
11721 if (lbss_section == NULL)
11722 {
11723 flagword applicable;
11724 segT seg = now_seg;
11725 subsegT subseg = now_subseg;
11726
11727 /* The .lbss section is for local .largecomm symbols. */
11728 lbss_section = subseg_new (".lbss", 0);
11729 applicable = bfd_applicable_section_flags (stdoutput);
11730 bfd_set_section_flags (stdoutput, lbss_section,
11731 applicable & SEC_ALLOC);
11732 seg_info (lbss_section)->bss = 1;
11733
11734 subseg_set (seg, subseg);
11735 }
11736
11737 elf_com_section_ptr = &_bfd_elf_large_com_section;
11738 bss_section = lbss_section;
11739
11740 s_comm_internal (0, elf_common_parse);
11741
11742 elf_com_section_ptr = saved_com_section_ptr;
11743 bss_section = saved_bss_section;
11744 }
11745}
11746#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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