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Add R_X86_64_PC32_BND/R_X86_64_PLT32_BND suppor to gold
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
7e8b059b 70#define BND_PREFIX REP_PREFIX
c32fa91d
L		 71#define LOCK_PREFIX 5
72#define REX_PREFIX 6 /* must come last. */
73#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 74
75/* we define the syntax here (modulo base,index,scale syntax) */
76#define REGISTER_PREFIX '%'
77#define IMMEDIATE_PREFIX '$'
78#define ABSOLUTE_PREFIX '*'
79
80/* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82#define WORD_MNEM_SUFFIX 'w'
83#define BYTE_MNEM_SUFFIX 'b'
84#define SHORT_MNEM_SUFFIX 's'
85#define LONG_MNEM_SUFFIX 'l'
86#define QWORD_MNEM_SUFFIX 'q'
87#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 88#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 89#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 90/* Intel Syntax. Use a non-ascii letter since since it never appears
91 in instructions. */
92#define LONG_DOUBLE_MNEM_SUFFIX '\1'
93
94#define END_OF_INSN '\0'
95
96/*
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
101 END.
102 */
103typedef struct
104{
d3ce72d0
NC		 105 const insn_template *start;
106 const insn_template *end;
6305a203
L		 107}
108templates;
109
110/* 386 operand encoding bytes: see 386 book for details of this. */
111typedef struct
112{
113 unsigned int regmem; /* codes register or memory operand */
114 unsigned int reg; /* codes register operand (or extended opcode) */
115 unsigned int mode; /* how to interpret regmem & reg */
116}
117modrm_byte;
118
119/* x86-64 extension prefix. */
120typedef int rex_byte;
121
6305a203
L		 122/* 386 opcode byte to code indirect addressing. */
123typedef struct
124{
125 unsigned base;
126 unsigned index;
127 unsigned scale;
128}
129sib_byte;
130
6305a203
L		 131/* x86 arch names, types and features */
132typedef struct
133{
134 const char *name; /* arch name */
8a2c8fef 135 unsigned int len; /* arch string length */
6305a203
L		 136 enum processor_type type; /* arch type */
137 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 138 unsigned int skip; /* show_arch should skip this. */
22109423 139 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 140}
141arch_entry;
142
78f12dd3 143static void update_code_flag (int, int);
e3bb37b5
L		 144static void set_code_flag (int);
145static void set_16bit_gcc_code_flag (int);
146static void set_intel_syntax (int);
1efbbeb4 147static void set_intel_mnemonic (int);
db51cc60 148static void set_allow_index_reg (int);
7bab8ab5 149static void set_check (int);
e3bb37b5 150static void set_cpu_arch (int);
6482c264 151#ifdef TE_PE
e3bb37b5 152static void pe_directive_secrel (int);
6482c264 153#endif
e3bb37b5
L		 154static void signed_cons (int);
155static char *output_invalid (int c);
ee86248c
JB		 156static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
157 const char *);
158static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
159 const char *);
a7619375 160static int i386_att_operand (char *);
e3bb37b5 161static int i386_intel_operand (char *, int);
ee86248c
JB		 162static int i386_intel_simplify (expressionS *);
163static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 164static const reg_entry *parse_register (char *, char **);
165static char *parse_insn (char *, char *);
166static char *parse_operands (char *, const char *);
167static void swap_operands (void);
4d456e3d 168static void swap_2_operands (int, int);
e3bb37b5
L		 169static void optimize_imm (void);
170static void optimize_disp (void);
d3ce72d0 171static const insn_template *match_template (void);
e3bb37b5
L		 172static int check_string (void);
173static int process_suffix (void);
174static int check_byte_reg (void);
175static int check_long_reg (void);
176static int check_qword_reg (void);
177static int check_word_reg (void);
178static int finalize_imm (void);
179static int process_operands (void);
180static const seg_entry *build_modrm_byte (void);
181static void output_insn (void);
182static void output_imm (fragS *, offsetT);
183static void output_disp (fragS *, offsetT);
29b0f896 184#ifndef I386COFF
e3bb37b5 185static void s_bss (int);
252b5132 186#endif
17d4e2a2
L		 187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188static void handle_large_common (int small ATTRIBUTE_UNUSED);
189#endif
252b5132 190
a847613f 191static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 192
43234a1e
L		 193/* This struct describes rounding control and SAE in the instruction. */
194struct RC_Operation
195{
196 enum rc_type
197 {
198 rne = 0,
199 rd,
200 ru,
201 rz,
202 saeonly
203 } type;
204 int operand;
205};
206
207static struct RC_Operation rc_op;
208
209/* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212struct Mask_Operation
213{
214 const reg_entry *mask;
215 unsigned int zeroing;
216 /* The operand where this operation is associated. */
217 int operand;
218};
219
220static struct Mask_Operation mask_op;
221
222/* The struct describes broadcasting, applied to OPERAND. FACTOR is
223 broadcast factor. */
224struct Broadcast_Operation
225{
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
227 int type;
228
229 /* Index of broadcasted operand. */
230 int operand;
231};
232
233static struct Broadcast_Operation broadcast_op;
234
c0f3af97
L		 235/* VEX prefix. */
236typedef struct
237{
43234a1e
L		 238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes[4];
c0f3af97
L		 240 unsigned int length;
241 /* Destination or source register specifier. */
242 const reg_entry *register_specifier;
243} vex_prefix;
244
252b5132 245/* 'md_assemble ()' gathers together information and puts it into a
47926f60 246 i386_insn. */
252b5132 247
520dc8e8
AM		 248union i386_op
249 {
250 expressionS *disps;
251 expressionS *imms;
252 const reg_entry *regs;
253 };
254
a65babc9
L		 255enum i386_error
256 {
86e026a4 257 operand_size_mismatch,
a65babc9
L		 258 operand_type_mismatch,
259 register_type_mismatch,
260 number_of_operands_mismatch,
261 invalid_instruction_suffix,
262 bad_imm4,
263 old_gcc_only,
264 unsupported_with_intel_mnemonic,
265 unsupported_syntax,
6c30d220
L		 266 unsupported,
267 invalid_vsib_address,
7bab8ab5 268 invalid_vector_register_set,
43234a1e
L		 269 unsupported_vector_index_register,
270 unsupported_broadcast,
271 broadcast_not_on_src_operand,
272 broadcast_needed,
273 unsupported_masking,
274 mask_not_on_destination,
275 no_default_mask,
276 unsupported_rc_sae,
277 rc_sae_operand_not_last_imm,
278 invalid_register_operand,
279 try_vector_disp8
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132
RH		 323
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes;
327 unsigned char prefix[MAX_PREFIXES];
328
329 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 330 addressing modes of this insn are encoded. */
252b5132 331 modrm_byte rm;
3e73aa7c 332 rex_byte rex;
43234a1e 333 rex_byte vrex;
252b5132 334 sib_byte sib;
c0f3af97 335 vex_prefix vex;
b6169b20 336
43234a1e
L		 337 /* Masking attributes. */
338 struct Mask_Operation *mask;
339
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation *rounding;
342
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation *broadcast;
345
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift;
348
b6169b20 349 /* Swap operand in encoding. */
4473e004 350 unsigned int swap_operand;
891edac4 351
a501d77e
L		 352 /* Prefer 8bit or 32bit displacement in encoding. */
353 enum
354 {
355 disp_encoding_default = 0,
356 disp_encoding_8bit,
357 disp_encoding_32bit
358 } disp_encoding;
f8a5c266 359
d5de92cf
L		 360 /* REP prefix. */
361 const char *rep_prefix;
362
165de32a
L		 363 /* HLE prefix. */
364 const char *hle_prefix;
42164a71 365
7e8b059b
L		 366 /* Have BND prefix. */
367 const char *bnd_prefix;
368
43234a1e
L		 369 /* Need VREX to support upper 16 registers. */
370 int need_vrex;
371
891edac4 372 /* Error message. */
a65babc9 373 enum i386_error error;
252b5132
RH		 374 };
375
376typedef struct _i386_insn i386_insn;
377
43234a1e
L		 378/* Link RC type with corresponding string, that'll be looked for in
379 asm. */
380struct RC_name
381{
382 enum rc_type type;
383 const char *name;
384 unsigned int len;
385};
386
387static const struct RC_name RC_NamesTable[] =
388{
389 { rne, STRING_COMMA_LEN ("rn-sae") },
390 { rd, STRING_COMMA_LEN ("rd-sae") },
391 { ru, STRING_COMMA_LEN ("ru-sae") },
392 { rz, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly, STRING_COMMA_LEN ("sae") },
394};
395
252b5132
RH		 396/* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 398const char extra_symbol_chars[] = "*%-([{"
252b5132 399#ifdef LEX_AT
32137342
NC		 400 "@"
401#endif
402#ifdef LEX_QM
403 "?"
252b5132 404#endif
32137342 405 ;
252b5132 406
29b0f896
AM		 407#if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 409 && !defined (TE_GNU) \
29b0f896 410 && !defined (TE_LINUX) \
8d63c93e
RM		 411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
29b0f896 413 && !defined (TE_FreeBSD) \
5b806d27 414 && !defined (TE_DragonFly) \
29b0f896 415 && !defined (TE_NetBSD)))
252b5132 416/* This array holds the chars that always start a comment. If the
b3b91714
AM		 417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419const char *i386_comment_chars = "#/";
420#define SVR4_COMMENT_CHARS 1
252b5132 421#define PREFIX_SEPARATOR '\\'
252b5132 422
b3b91714
AM		 423#else
424const char *i386_comment_chars = "#";
425#define PREFIX_SEPARATOR '/'
426#endif
427
252b5132
RH		 428/* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 432 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
252b5132 435 '/' isn't otherwise defined. */
b3b91714 436const char line_comment_chars[] = "#/";
252b5132 437
63a0b638 438const char line_separator_chars[] = ";";
252b5132 439
ce8a8b2f
AM		 440/* Chars that can be used to separate mant from exp in floating point
441 nums. */
252b5132
RH		 442const char EXP_CHARS[] = "eE";
443
ce8a8b2f
AM		 444/* Chars that mean this number is a floating point constant
445 As in 0f12.456
446 or 0d1.2345e12. */
252b5132
RH		 447const char FLT_CHARS[] = "fFdDxX";
448
ce8a8b2f 449/* Tables for lexical analysis. */
252b5132
RH		 450static char mnemonic_chars[256];
451static char register_chars[256];
452static char operand_chars[256];
453static char identifier_chars[256];
454static char digit_chars[256];
455
ce8a8b2f 456/* Lexical macros. */
252b5132
RH		 457#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458#define is_operand_char(x) (operand_chars[(unsigned char) x])
459#define is_register_char(x) (register_chars[(unsigned char) x])
460#define is_space_char(x) ((x) == ' ')
461#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462#define is_digit_char(x) (digit_chars[(unsigned char) x])
463
0234cb7c 464/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 465static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
466
467/* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
47926f60 470 assembler instruction). */
252b5132 471static char save_stack[32];
ce8a8b2f 472static char *save_stack_p;
252b5132
RH		 473#define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475#define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
477
47926f60 478/* The instruction we're assembling. */
252b5132
RH		 479static i386_insn i;
480
481/* Possible templates for current insn. */
482static const templates *current_templates;
483
31b2323c
L		 484/* Per instruction expressionS buffers: max displacements & immediates. */
485static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
486static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 487
47926f60 488/* Current operand we are working on. */
ee86248c 489static int this_operand = -1;
252b5132 490
3e73aa7c
JH		 491/* We support four different modes. FLAG_CODE variable is used to distinguish
492 these. */
493
494enum flag_code {
495 CODE_32BIT,
496 CODE_16BIT,
497 CODE_64BIT };
498
499static enum flag_code flag_code;
4fa24527 500static unsigned int object_64bit;
862be3fb 501static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 502static int use_rela_relocations = 0;
503
7af8ed2d
NC		 504#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
507
351f65ca
L		 508/* The ELF ABI to use. */
509enum x86_elf_abi
510{
511 I386_ABI,
7f56bc95
L		 512 X86_64_ABI,
513 X86_64_X32_ABI
351f65ca
L		 514};
515
516static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 517#endif
351f65ca 518
47926f60
KH		 519/* 1 for intel syntax,
520 0 if att syntax. */
521static int intel_syntax = 0;
252b5132 522
1efbbeb4
L		 523/* 1 for intel mnemonic,
524 0 if att mnemonic. */
525static int intel_mnemonic = !SYSV386_COMPAT;
526
5209009a 527/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 528static int old_gcc = OLDGCC_COMPAT;
529
a60de03c
JB		 530/* 1 if pseudo registers are permitted. */
531static int allow_pseudo_reg = 0;
532
47926f60
KH		 533/* 1 if register prefix % not required. */
534static int allow_naked_reg = 0;
252b5132 535
7e8b059b
L		 536/* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
538 explicitly. */
539static int add_bnd_prefix = 0;
540
ba104c83 541/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 542static int allow_index_reg = 0;
543
7bab8ab5 544static enum check_kind
daf50ae7 545 {
7bab8ab5
JB		 546 check_none = 0,
547 check_warning,
548 check_error
daf50ae7 549 }
7bab8ab5 550sse_check, operand_check = check_warning;
daf50ae7 551
2ca3ace5
L		 552/* Register prefix used for error message. */
553static const char *register_prefix = "%";
554
47926f60
KH		 555/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558static char stackop_size = '\0';
eecb386c 559
12b55ccc
L		 560/* Non-zero to optimize code alignment. */
561int optimize_align_code = 1;
562
47926f60
KH		 563/* Non-zero to quieten some warnings. */
564static int quiet_warnings = 0;
a38cf1db 565
47926f60
KH		 566/* CPU name. */
567static const char *cpu_arch_name = NULL;
6305a203 568static char *cpu_sub_arch_name = NULL;
a38cf1db 569
47926f60 570/* CPU feature flags. */
40fb9820
L		 571static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
572
ccc9c027
L		 573/* If we have selected a cpu we are generating instructions for. */
574static int cpu_arch_tune_set = 0;
575
9103f4f4 576/* Cpu we are generating instructions for. */
fbf3f584 577enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 578
579/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 580static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 581
ccc9c027 582/* CPU instruction set architecture used. */
fbf3f584 583enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 584
9103f4f4 585/* CPU feature flags of instruction set architecture used. */
fbf3f584 586i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 587
fddf5b5b
AM		 588/* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590static unsigned int no_cond_jump_promotion = 0;
591
c0f3af97
L		 592/* Encode SSE instructions with VEX prefix. */
593static unsigned int sse2avx;
594
539f890d
L		 595/* Encode scalar AVX instructions with specific vector length. */
596static enum
597 {
598 vex128 = 0,
599 vex256
600 } avxscalar;
601
43234a1e
L		 602/* Encode scalar EVEX LIG instructions with specific vector length. */
603static enum
604 {
605 evexl128 = 0,
606 evexl256,
607 evexl512
608 } evexlig;
609
610/* Encode EVEX WIG instructions with specific evex.w. */
611static enum
612 {
613 evexw0 = 0,
614 evexw1
615 } evexwig;
616
29b0f896 617/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 618static symbolS *GOT_symbol;
29b0f896 619
a4447b93
RH		 620/* The dwarf2 return column, adjusted for 32 or 64 bit. */
621unsigned int x86_dwarf2_return_column;
622
623/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624int x86_cie_data_alignment;
625
252b5132 626/* Interface to relax_segment.
fddf5b5b
AM		 627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
252b5132 630
47926f60 631/* Types. */
93c2a809
AM		 632#define UNCOND_JUMP 0
633#define COND_JUMP 1
634#define COND_JUMP86 2
fddf5b5b 635
47926f60 636/* Sizes. */
252b5132
RH		 637#define CODE16 1
638#define SMALL 0
29b0f896 639#define SMALL16 (SMALL | CODE16)
252b5132 640#define BIG 2
29b0f896 641#define BIG16 (BIG | CODE16)
252b5132
RH		 642
643#ifndef INLINE
644#ifdef __GNUC__
645#define INLINE __inline__
646#else
647#define INLINE
648#endif
649#endif
650
fddf5b5b
AM		 651#define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653#define TYPE_FROM_RELAX_STATE(s) \
654 ((s) >> 2)
655#define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 657
658/* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
665
666const relax_typeS md_relax_table[] =
667{
24eab124
AM		 668 /* The fields are:
669 1) most positive reach of this state,
670 2) most negative reach of this state,
93c2a809 671 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 672 4) which index into the table to try if we can't fit into this one. */
252b5132 673
fddf5b5b 674 /* UNCOND_JUMP states. */
93c2a809
AM		 675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
252b5132 679 {0, 0, 4, 0},
93c2a809
AM		 680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 682 {0, 0, 2, 0},
683
93c2a809
AM		 684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
689 {0, 0, 5, 0},
fddf5b5b 690 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 691 1 extra opcode byte, 2 displacement bytes. */
692 {0, 0, 3, 0},
693
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
699 {0, 0, 5, 0},
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
702 {0, 0, 4, 0}
252b5132
RH		 703};
704
9103f4f4
L		 705static const arch_entry cpu_arch[] =
706{
89507696
JB		 707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
8a2c8fef 709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 710 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 712 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 714 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 716 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 718 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 720 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 722 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 724 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 726 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 728 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 730 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 732 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 734 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 736 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 738 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 740 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 742 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 744 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 746 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 748 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 750 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 752 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
754 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 756 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 758 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 760 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 762 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 764 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 766 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 768 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 770 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 772 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
774 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 775 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
776 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 777 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
778 CPU_BTVER1_FLAGS, 0, 0 },
779 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
780 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 782 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 784 CPU_287_FLAGS, 0, 0 },
8a2c8fef 785 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 786 CPU_387_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 788 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 789 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 790 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 791 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 792 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 793 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 794 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 795 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 796 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 798 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 800 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 802 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 804 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 806 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 808 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 809 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 810 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 811 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
812 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 813 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
814 CPU_AVX512F_FLAGS, 0, 0 },
815 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
816 CPU_AVX512CD_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
818 CPU_AVX512ER_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
820 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 822 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 823 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 824 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 825 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
826 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 830 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 831 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 832 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 834 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 836 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 838 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 839 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 840 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 841 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 842 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 843 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 844 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 845 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
846 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 848 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 850 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 852 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 854 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 856 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 857 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
858 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 860 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 861 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
862 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 863 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
864 CPU_HLE_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
866 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 867 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
868 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 870 CPU_CLFLUSH_FLAGS, 0, 0 },
871 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
872 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 874 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 876 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 878 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 880 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 882 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 884 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 886 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 888 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 890 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 891 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
892 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 893 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
894 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 895 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
896 CPU_ADX_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
898 CPU_RDSEED_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
900 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 901 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
902 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 903 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
904 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 905 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
906 CPU_SHA_FLAGS, 0, 0 },
e413e4e9
AM		 907};
908
704209c0 909#ifdef I386COFF
a6c24e68
NC		 910/* Like s_lcomm_internal in gas/read.c but the alignment string
911 is allowed to be optional. */
912
913static symbolS *
914pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
915{
916 addressT align = 0;
917
918 SKIP_WHITESPACE ();
919
7ab9ffdd 920 if (needs_align
a6c24e68
NC		 921 && *input_line_pointer == ',')
922 {
923 align = parse_align (needs_align - 1);
7ab9ffdd 924
a6c24e68
NC		 925 if (align == (addressT) -1)
926 return NULL;
927 }
928 else
929 {
930 if (size >= 8)
931 align = 3;
932 else if (size >= 4)
933 align = 2;
934 else if (size >= 2)
935 align = 1;
936 else
937 align = 0;
938 }
939
940 bss_alloc (symbolP, size, align);
941 return symbolP;
942}
943
704209c0 944static void
a6c24e68
NC		 945pe_lcomm (int needs_align)
946{
947 s_comm_internal (needs_align * 2, pe_lcomm_internal);
948}
704209c0 949#endif
a6c24e68 950
29b0f896
AM		 951const pseudo_typeS md_pseudo_table[] =
952{
953#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
954 {"align", s_align_bytes, 0},
955#else
956 {"align", s_align_ptwo, 0},
957#endif
958 {"arch", set_cpu_arch, 0},
959#ifndef I386COFF
960 {"bss", s_bss, 0},
a6c24e68
NC		 961#else
962 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 963#endif
964 {"ffloat", float_cons, 'f'},
965 {"dfloat", float_cons, 'd'},
966 {"tfloat", float_cons, 'x'},
967 {"value", cons, 2},
d182319b 968 {"slong", signed_cons, 4},
29b0f896
AM		 969 {"noopt", s_ignore, 0},
970 {"optim", s_ignore, 0},
971 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
972 {"code16", set_code_flag, CODE_16BIT},
973 {"code32", set_code_flag, CODE_32BIT},
974 {"code64", set_code_flag, CODE_64BIT},
975 {"intel_syntax", set_intel_syntax, 1},
976 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 977 {"intel_mnemonic", set_intel_mnemonic, 1},
978 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 979 {"allow_index_reg", set_allow_index_reg, 1},
980 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 981 {"sse_check", set_check, 0},
982 {"operand_check", set_check, 1},
3b22753a
L		 983#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
984 {"largecomm", handle_large_common, 0},
07a53e5c 985#else
e3bb37b5 986 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 987 {"loc", dwarf2_directive_loc, 0},
988 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 989#endif
6482c264
NC		 990#ifdef TE_PE
991 {"secrel32", pe_directive_secrel, 0},
992#endif
29b0f896
AM		 993 {0, 0, 0}
994};
995
996/* For interface with expression (). */
997extern char *input_line_pointer;
998
999/* Hash table for instruction mnemonic lookup. */
1000static struct hash_control *op_hash;
1001
1002/* Hash table for register lookup. */
1003static struct hash_control *reg_hash;
1004\f
252b5132 1005void
e3bb37b5 1006i386_align_code (fragS *fragP, int count)
252b5132 1007{
ce8a8b2f
AM		 1008 /* Various efficient no-op patterns for aligning code labels.
1009 Note: Don't try to assemble the instructions in the comments.
1010 0L and 0w are not legal. */
252b5132
RH		 1011 static const char f32_1[] =
1012 {0x90}; /* nop */
1013 static const char f32_2[] =
ccc9c027 1014 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1015 static const char f32_3[] =
1016 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1017 static const char f32_4[] =
1018 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1019 static const char f32_5[] =
1020 {0x90, /* nop */
1021 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1022 static const char f32_6[] =
1023 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1024 static const char f32_7[] =
1025 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1026 static const char f32_8[] =
1027 {0x90, /* nop */
1028 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1029 static const char f32_9[] =
1030 {0x89,0xf6, /* movl %esi,%esi */
1031 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1032 static const char f32_10[] =
1033 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1034 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1035 static const char f32_11[] =
1036 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1037 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1038 static const char f32_12[] =
1039 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1040 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1041 static const char f32_13[] =
1042 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_14[] =
1045 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1047 static const char f16_3[] =
1048 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1049 static const char f16_4[] =
1050 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1051 static const char f16_5[] =
1052 {0x90, /* nop */
1053 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1054 static const char f16_6[] =
1055 {0x89,0xf6, /* mov %si,%si */
1056 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1057 static const char f16_7[] =
1058 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1059 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1060 static const char f16_8[] =
1061 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1062 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1063 static const char jump_31[] =
1064 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1065 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1066 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1067 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1068 static const char *const f32_patt[] = {
1069 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1070 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1071 };
1072 static const char *const f16_patt[] = {
76bc74dc 1073 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1074 };
ccc9c027
L		 1075 /* nopl (%[re]ax) */
1076 static const char alt_3[] =
1077 {0x0f,0x1f,0x00};
1078 /* nopl 0(%[re]ax) */
1079 static const char alt_4[] =
1080 {0x0f,0x1f,0x40,0x00};
1081 /* nopl 0(%[re]ax,%[re]ax,1) */
1082 static const char alt_5[] =
1083 {0x0f,0x1f,0x44,0x00,0x00};
1084 /* nopw 0(%[re]ax,%[re]ax,1) */
1085 static const char alt_6[] =
1086 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1087 /* nopl 0L(%[re]ax) */
1088 static const char alt_7[] =
1089 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1090 /* nopl 0L(%[re]ax,%[re]ax,1) */
1091 static const char alt_8[] =
1092 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1093 /* nopw 0L(%[re]ax,%[re]ax,1) */
1094 static const char alt_9[] =
1095 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1096 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1097 static const char alt_10[] =
1098 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1099 /* data16
1100 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1101 static const char alt_long_11[] =
1102 {0x66,
1103 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1104 /* data16
1105 data16
1106 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_long_12[] =
1108 {0x66,
1109 0x66,
1110 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1111 /* data16
1112 data16
1113 data16
1114 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1115 static const char alt_long_13[] =
1116 {0x66,
1117 0x66,
1118 0x66,
1119 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1120 /* data16
1121 data16
1122 data16
1123 data16
1124 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_long_14[] =
1126 {0x66,
1127 0x66,
1128 0x66,
1129 0x66,
1130 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 /* data16
1132 data16
1133 data16
1134 data16
1135 data16
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_15[] =
1138 {0x66,
1139 0x66,
1140 0x66,
1141 0x66,
1142 0x66,
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopl 0(%[re]ax,%[re]ax,1)
1145 nopw 0(%[re]ax,%[re]ax,1) */
1146 static const char alt_short_11[] =
1147 {0x0f,0x1f,0x44,0x00,0x00,
1148 0x66,0x0f,0x1f,0x44,0x00,0x00};
1149 /* nopw 0(%[re]ax,%[re]ax,1)
1150 nopw 0(%[re]ax,%[re]ax,1) */
1151 static const char alt_short_12[] =
1152 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1153 0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopw 0(%[re]ax,%[re]ax,1)
1155 nopl 0L(%[re]ax) */
1156 static const char alt_short_13[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1158 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1159 /* nopl 0L(%[re]ax)
1160 nopl 0L(%[re]ax) */
1161 static const char alt_short_14[] =
1162 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1163 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1164 /* nopl 0L(%[re]ax)
1165 nopl 0L(%[re]ax,%[re]ax,1) */
1166 static const char alt_short_15[] =
1167 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1168 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 static const char *const alt_short_patt[] = {
1170 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1171 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1172 alt_short_14, alt_short_15
1173 };
1174 static const char *const alt_long_patt[] = {
1175 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1176 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1177 alt_long_14, alt_long_15
1178 };
252b5132 1179
76bc74dc
L		 1180 /* Only align for at least a positive non-zero boundary. */
1181 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1182 return;
3e73aa7c 1183
ccc9c027
L		 1184 /* We need to decide which NOP sequence to use for 32bit and
1185 64bit. When -mtune= is used:
4eed87de 1186
76bc74dc
L		 1187 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1188 PROCESSOR_GENERIC32, f32_patt will be used.
1189 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1190 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1191 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1192 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1193 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1194 will be used.
ccc9c027 1195
76bc74dc 1196 When -mtune= isn't used, alt_long_patt will be used if
22109423 1197 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1198 be used.
ccc9c027
L		 1199
1200 When -march= or .arch is used, we can't use anything beyond
1201 cpu_arch_isa_flags. */
1202
1203 if (flag_code == CODE_16BIT)
1204 {
ccc9c027 1205 if (count > 8)
33fef721 1206 {
76bc74dc
L		 1207 memcpy (fragP->fr_literal + fragP->fr_fix,
1208 jump_31, count);
1209 /* Adjust jump offset. */
1210 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1211 }
76bc74dc
L		 1212 else
1213 memcpy (fragP->fr_literal + fragP->fr_fix,
1214 f16_patt[count - 1], count);
252b5132 1215 }
33fef721 1216 else
ccc9c027
L		 1217 {
1218 const char *const *patt = NULL;
1219
fbf3f584 1220 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1221 {
1222 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1223 switch (cpu_arch_tune)
1224 {
1225 case PROCESSOR_UNKNOWN:
1226 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1227 optimize with nops. */
1228 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1229 patt = alt_long_patt;
ccc9c027
L		 1230 else
1231 patt = f32_patt;
1232 break;
ccc9c027
L		 1233 case PROCESSOR_PENTIUM4:
1234 case PROCESSOR_NOCONA:
ef05d495 1235 case PROCESSOR_CORE:
76bc74dc 1236 case PROCESSOR_CORE2:
bd5295b2 1237 case PROCESSOR_COREI7:
3632d14b 1238 case PROCESSOR_L1OM:
7a9068fe 1239 case PROCESSOR_K1OM:
76bc74dc
L		 1240 case PROCESSOR_GENERIC64:
1241 patt = alt_long_patt;
1242 break;
ccc9c027
L		 1243 case PROCESSOR_K6:
1244 case PROCESSOR_ATHLON:
1245 case PROCESSOR_K8:
4eed87de 1246 case PROCESSOR_AMDFAM10:
8aedb9fe 1247 case PROCESSOR_BD:
7b458c12 1248 case PROCESSOR_BT:
ccc9c027
L		 1249 patt = alt_short_patt;
1250 break;
76bc74dc 1251 case PROCESSOR_I386:
ccc9c027
L		 1252 case PROCESSOR_I486:
1253 case PROCESSOR_PENTIUM:
2dde1948 1254 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1255 case PROCESSOR_GENERIC32:
1256 patt = f32_patt;
1257 break;
4eed87de 1258 }
ccc9c027
L		 1259 }
1260 else
1261 {
fbf3f584 1262 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1263 {
1264 case PROCESSOR_UNKNOWN:
e6a14101 1265 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1266 PROCESSOR_UNKNOWN. */
1267 abort ();
1268 break;
1269
76bc74dc 1270 case PROCESSOR_I386:
ccc9c027
L		 1271 case PROCESSOR_I486:
1272 case PROCESSOR_PENTIUM:
ccc9c027
L		 1273 case PROCESSOR_K6:
1274 case PROCESSOR_ATHLON:
1275 case PROCESSOR_K8:
4eed87de 1276 case PROCESSOR_AMDFAM10:
8aedb9fe 1277 case PROCESSOR_BD:
7b458c12 1278 case PROCESSOR_BT:
ccc9c027
L		 1279 case PROCESSOR_GENERIC32:
1280 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1281 with nops. */
1282 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1283 patt = alt_short_patt;
1284 else
1285 patt = f32_patt;
1286 break;
76bc74dc
L		 1287 case PROCESSOR_PENTIUMPRO:
1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
1290 case PROCESSOR_CORE:
ef05d495 1291 case PROCESSOR_CORE2:
bd5295b2 1292 case PROCESSOR_COREI7:
3632d14b 1293 case PROCESSOR_L1OM:
7a9068fe 1294 case PROCESSOR_K1OM:
22109423 1295 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1296 patt = alt_long_patt;
1297 else
1298 patt = f32_patt;
1299 break;
1300 case PROCESSOR_GENERIC64:
76bc74dc 1301 patt = alt_long_patt;
ccc9c027 1302 break;
4eed87de 1303 }
ccc9c027
L		 1304 }
1305
76bc74dc
L		 1306 if (patt == f32_patt)
1307 {
1308 /* If the padding is less than 15 bytes, we use the normal
1309 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1310 its offset. */
1311 int limit;
76ba9986 1312
711eedef
L		 1313 /* For 64bit, the limit is 3 bytes. */
1314 if (flag_code == CODE_64BIT
1315 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1316 limit = 3;
1317 else
1318 limit = 15;
1319 if (count < limit)
76bc74dc
L		 1320 memcpy (fragP->fr_literal + fragP->fr_fix,
1321 patt[count - 1], count);
1322 else
1323 {
1324 memcpy (fragP->fr_literal + fragP->fr_fix,
1325 jump_31, count);
1326 /* Adjust jump offset. */
1327 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1328 }
1329 }
1330 else
1331 {
1332 /* Maximum length of an instruction is 15 byte. If the
1333 padding is greater than 15 bytes and we don't use jump,
1334 we have to break it into smaller pieces. */
1335 int padding = count;
1336 while (padding > 15)
1337 {
1338 padding -= 15;
1339 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1340 patt [14], 15);
1341 }
1342
1343 if (padding)
1344 memcpy (fragP->fr_literal + fragP->fr_fix,
1345 patt [padding - 1], padding);
1346 }
ccc9c027 1347 }
33fef721 1348 fragP->fr_var = count;
252b5132
RH		 1349}
1350
c6fb90c8 1351static INLINE int
0dfbf9d7 1352operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1353{
0dfbf9d7 1354 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1355 {
1356 case 3:
0dfbf9d7 1357 if (x->array[2])
c6fb90c8
L		 1358 return 0;
1359 case 2:
0dfbf9d7 1360 if (x->array[1])
c6fb90c8
L		 1361 return 0;
1362 case 1:
0dfbf9d7 1363 return !x->array[0];
c6fb90c8
L		 1364 default:
1365 abort ();
1366 }
40fb9820
L		 1367}
1368
c6fb90c8 1369static INLINE void
0dfbf9d7 1370operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1371{
0dfbf9d7 1372 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1373 {
1374 case 3:
0dfbf9d7 1375 x->array[2] = v;
c6fb90c8 1376 case 2:
0dfbf9d7 1377 x->array[1] = v;
c6fb90c8 1378 case 1:
0dfbf9d7 1379 x->array[0] = v;
c6fb90c8
L		 1380 break;
1381 default:
1382 abort ();
1383 }
1384}
40fb9820 1385
c6fb90c8 1386static INLINE int
0dfbf9d7
L		 1387operand_type_equal (const union i386_operand_type *x,
1388 const union i386_operand_type *y)
c6fb90c8 1389{
0dfbf9d7 1390 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1391 {
1392 case 3:
0dfbf9d7 1393 if (x->array[2] != y->array[2])
c6fb90c8
L		 1394 return 0;
1395 case 2:
0dfbf9d7 1396 if (x->array[1] != y->array[1])
c6fb90c8
L		 1397 return 0;
1398 case 1:
0dfbf9d7 1399 return x->array[0] == y->array[0];
c6fb90c8
L		 1400 break;
1401 default:
1402 abort ();
1403 }
1404}
40fb9820 1405
0dfbf9d7
L		 1406static INLINE int
1407cpu_flags_all_zero (const union i386_cpu_flags *x)
1408{
1409 switch (ARRAY_SIZE(x->array))
1410 {
1411 case 3:
1412 if (x->array[2])
1413 return 0;
1414 case 2:
1415 if (x->array[1])
1416 return 0;
1417 case 1:
1418 return !x->array[0];
1419 default:
1420 abort ();
1421 }
1422}
1423
1424static INLINE void
1425cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1426{
1427 switch (ARRAY_SIZE(x->array))
1428 {
1429 case 3:
1430 x->array[2] = v;
1431 case 2:
1432 x->array[1] = v;
1433 case 1:
1434 x->array[0] = v;
1435 break;
1436 default:
1437 abort ();
1438 }
1439}
1440
1441static INLINE int
1442cpu_flags_equal (const union i386_cpu_flags *x,
1443 const union i386_cpu_flags *y)
1444{
1445 switch (ARRAY_SIZE(x->array))
1446 {
1447 case 3:
1448 if (x->array[2] != y->array[2])
1449 return 0;
1450 case 2:
1451 if (x->array[1] != y->array[1])
1452 return 0;
1453 case 1:
1454 return x->array[0] == y->array[0];
1455 break;
1456 default:
1457 abort ();
1458 }
1459}
c6fb90c8
L		 1460
1461static INLINE int
1462cpu_flags_check_cpu64 (i386_cpu_flags f)
1463{
1464 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1465 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1466}
1467
c6fb90c8
L		 1468static INLINE i386_cpu_flags
1469cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1470{
c6fb90c8
L		 1471 switch (ARRAY_SIZE (x.array))
1472 {
1473 case 3:
1474 x.array [2] &= y.array [2];
1475 case 2:
1476 x.array [1] &= y.array [1];
1477 case 1:
1478 x.array [0] &= y.array [0];
1479 break;
1480 default:
1481 abort ();
1482 }
1483 return x;
1484}
40fb9820 1485
c6fb90c8
L		 1486static INLINE i386_cpu_flags
1487cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1488{
c6fb90c8 1489 switch (ARRAY_SIZE (x.array))
40fb9820 1490 {
c6fb90c8
L		 1491 case 3:
1492 x.array [2] |= y.array [2];
1493 case 2:
1494 x.array [1] |= y.array [1];
1495 case 1:
1496 x.array [0] |= y.array [0];
40fb9820
L		 1497 break;
1498 default:
1499 abort ();
1500 }
40fb9820
L		 1501 return x;
1502}
1503
309d3373
JB		 1504static INLINE i386_cpu_flags
1505cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1506{
1507 switch (ARRAY_SIZE (x.array))
1508 {
1509 case 3:
1510 x.array [2] &= ~y.array [2];
1511 case 2:
1512 x.array [1] &= ~y.array [1];
1513 case 1:
1514 x.array [0] &= ~y.array [0];
1515 break;
1516 default:
1517 abort ();
1518 }
1519 return x;
1520}
1521
c0f3af97
L		 1522#define CPU_FLAGS_ARCH_MATCH 0x1
1523#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1524#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1525#define CPU_FLAGS_PCLMUL_MATCH 0x8
1526#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1527
a5ff0eb2 1528#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1529 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1530 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1531#define CPU_FLAGS_PERFECT_MATCH \
1532 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1533
1534/* Return CPU flags match bits. */
3629bb00 1535
40fb9820 1536static int
d3ce72d0 1537cpu_flags_match (const insn_template *t)
40fb9820 1538{
c0f3af97
L		 1539 i386_cpu_flags x = t->cpu_flags;
1540 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1541
1542 x.bitfield.cpu64 = 0;
1543 x.bitfield.cpuno64 = 0;
1544
0dfbf9d7 1545 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1546 {
1547 /* This instruction is available on all archs. */
1548 match |= CPU_FLAGS_32BIT_MATCH;
1549 }
3629bb00
L		 1550 else
1551 {
c0f3af97 1552 /* This instruction is available only on some archs. */
3629bb00
L		 1553 i386_cpu_flags cpu = cpu_arch_flags;
1554
1555 cpu.bitfield.cpu64 = 0;
1556 cpu.bitfield.cpuno64 = 0;
1557 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1558 if (!cpu_flags_all_zero (&cpu))
1559 {
a5ff0eb2
L		 1560 if (x.bitfield.cpuavx)
1561 {
ce2f5b3c 1562 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1563 if (cpu.bitfield.cpuavx)
1564 {
1565 /* Check SSE2AVX. */
1566 if (!t->opcode_modifier.sse2avx|| sse2avx)
1567 {
1568 match |= (CPU_FLAGS_ARCH_MATCH
1569 | CPU_FLAGS_AVX_MATCH);
1570 /* Check AES. */
1571 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1572 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1573 /* Check PCLMUL. */
1574 if (!x.bitfield.cpupclmul
1575 || cpu.bitfield.cpupclmul)
1576 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1577 }
1578 }
1579 else
1580 match |= CPU_FLAGS_ARCH_MATCH;
1581 }
1582 else
c0f3af97
L		 1583 match |= CPU_FLAGS_32BIT_MATCH;
1584 }
3629bb00 1585 }
c0f3af97 1586 return match;
40fb9820
L		 1587}
1588
c6fb90c8
L		 1589static INLINE i386_operand_type
1590operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1591{
c6fb90c8
L		 1592 switch (ARRAY_SIZE (x.array))
1593 {
1594 case 3:
1595 x.array [2] &= y.array [2];
1596 case 2:
1597 x.array [1] &= y.array [1];
1598 case 1:
1599 x.array [0] &= y.array [0];
1600 break;
1601 default:
1602 abort ();
1603 }
1604 return x;
40fb9820
L		 1605}
1606
c6fb90c8
L		 1607static INLINE i386_operand_type
1608operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1609{
c6fb90c8 1610 switch (ARRAY_SIZE (x.array))
40fb9820 1611 {
c6fb90c8
L		 1612 case 3:
1613 x.array [2] |= y.array [2];
1614 case 2:
1615 x.array [1] |= y.array [1];
1616 case 1:
1617 x.array [0] |= y.array [0];
40fb9820
L		 1618 break;
1619 default:
1620 abort ();
1621 }
c6fb90c8
L		 1622 return x;
1623}
40fb9820 1624
c6fb90c8
L		 1625static INLINE i386_operand_type
1626operand_type_xor (i386_operand_type x, i386_operand_type y)
1627{
1628 switch (ARRAY_SIZE (x.array))
1629 {
1630 case 3:
1631 x.array [2] ^= y.array [2];
1632 case 2:
1633 x.array [1] ^= y.array [1];
1634 case 1:
1635 x.array [0] ^= y.array [0];
1636 break;
1637 default:
1638 abort ();
1639 }
40fb9820
L		 1640 return x;
1641}
1642
1643static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1644static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1645static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1646static const i386_operand_type inoutportreg
1647 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1648static const i386_operand_type reg16_inoutportreg
1649 = OPERAND_TYPE_REG16_INOUTPORTREG;
1650static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1651static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1652static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1653static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1654static const i386_operand_type anydisp
1655 = OPERAND_TYPE_ANYDISP;
40fb9820 1656static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1657static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1658static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1659static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1660static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1661static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1662static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1663static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1664static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1665static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1666static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1667static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1668static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1669static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
7e8b059b 1670static const i386_operand_type regbnd = OPERAND_TYPE_REGBND;
43234a1e 1671static const i386_operand_type vec_disp8 = OPERAND_TYPE_VEC_DISP8;
40fb9820
L		 1672
1673enum operand_type
1674{
1675 reg,
40fb9820
L		 1676 imm,
1677 disp,
1678 anymem
1679};
1680
c6fb90c8 1681static INLINE int
40fb9820
L		 1682operand_type_check (i386_operand_type t, enum operand_type c)
1683{
1684 switch (c)
1685 {
1686 case reg:
1687 return (t.bitfield.reg8
1688 || t.bitfield.reg16
1689 || t.bitfield.reg32
1690 || t.bitfield.reg64);
1691
40fb9820
L		 1692 case imm:
1693 return (t.bitfield.imm8
1694 || t.bitfield.imm8s
1695 || t.bitfield.imm16
1696 || t.bitfield.imm32
1697 || t.bitfield.imm32s
1698 || t.bitfield.imm64);
1699
1700 case disp:
1701 return (t.bitfield.disp8
1702 || t.bitfield.disp16
1703 || t.bitfield.disp32
1704 || t.bitfield.disp32s
1705 || t.bitfield.disp64);
1706
1707 case anymem:
1708 return (t.bitfield.disp8
1709 || t.bitfield.disp16
1710 || t.bitfield.disp32
1711 || t.bitfield.disp32s
1712 || t.bitfield.disp64
1713 || t.bitfield.baseindex);
1714
1715 default:
1716 abort ();
1717 }
2cfe26b6
AM		 1718
1719 return 0;
40fb9820
L		 1720}
1721
5c07affc
L		 1722/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1723 operand J for instruction template T. */
1724
1725static INLINE int
d3ce72d0 1726match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1727{
1728 return !((i.types[j].bitfield.byte
1729 && !t->operand_types[j].bitfield.byte)
1730 || (i.types[j].bitfield.word
1731 && !t->operand_types[j].bitfield.word)
1732 || (i.types[j].bitfield.dword
1733 && !t->operand_types[j].bitfield.dword)
1734 || (i.types[j].bitfield.qword
1735 && !t->operand_types[j].bitfield.qword));
1736}
1737
1738/* Return 1 if there is no conflict in any size on operand J for
1739 instruction template T. */
1740
1741static INLINE int
d3ce72d0 1742match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1743{
1744 return (match_reg_size (t, j)
1745 && !((i.types[j].bitfield.unspecified
1746 && !t->operand_types[j].bitfield.unspecified)
1747 || (i.types[j].bitfield.fword
1748 && !t->operand_types[j].bitfield.fword)
1749 || (i.types[j].bitfield.tbyte
1750 && !t->operand_types[j].bitfield.tbyte)
1751 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1752 && !t->operand_types[j].bitfield.xmmword)
1753 || (i.types[j].bitfield.ymmword
43234a1e
L		 1754 && !t->operand_types[j].bitfield.ymmword)
1755 || (i.types[j].bitfield.zmmword
1756 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1757}
1758
1759/* Return 1 if there is no size conflict on any operands for
1760 instruction template T. */
1761
1762static INLINE int
d3ce72d0 1763operand_size_match (const insn_template *t)
5c07affc
L		 1764{
1765 unsigned int j;
1766 int match = 1;
1767
1768 /* Don't check jump instructions. */
1769 if (t->opcode_modifier.jump
1770 || t->opcode_modifier.jumpbyte
1771 || t->opcode_modifier.jumpdword
1772 || t->opcode_modifier.jumpintersegment)
1773 return match;
1774
1775 /* Check memory and accumulator operand size. */
1776 for (j = 0; j < i.operands; j++)
1777 {
1778 if (t->operand_types[j].bitfield.anysize)
1779 continue;
1780
1781 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1782 {
1783 match = 0;
1784 break;
1785 }
1786
1787 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1788 {
1789 match = 0;
1790 break;
1791 }
1792 }
1793
891edac4 1794 if (match)
5c07affc 1795 return match;
891edac4
L		 1796 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1797 {
1798mismatch:
86e026a4 1799 i.error = operand_size_mismatch;
891edac4
L		 1800 return 0;
1801 }
5c07affc
L		 1802
1803 /* Check reverse. */
9c2799c2 1804 gas_assert (i.operands == 2);
5c07affc
L		 1805
1806 match = 1;
1807 for (j = 0; j < 2; j++)
1808 {
1809 if (t->operand_types[j].bitfield.acc
1810 && !match_reg_size (t, j ? 0 : 1))
891edac4 1811 goto mismatch;
5c07affc
L		 1812
1813 if (i.types[j].bitfield.mem
1814 && !match_mem_size (t, j ? 0 : 1))
891edac4 1815 goto mismatch;
5c07affc
L		 1816 }
1817
1818 return match;
1819}
1820
c6fb90c8 1821static INLINE int
40fb9820
L		 1822operand_type_match (i386_operand_type overlap,
1823 i386_operand_type given)
1824{
1825 i386_operand_type temp = overlap;
1826
1827 temp.bitfield.jumpabsolute = 0;
7d5e4556 1828 temp.bitfield.unspecified = 0;
5c07affc
L		 1829 temp.bitfield.byte = 0;
1830 temp.bitfield.word = 0;
1831 temp.bitfield.dword = 0;
1832 temp.bitfield.fword = 0;
1833 temp.bitfield.qword = 0;
1834 temp.bitfield.tbyte = 0;
1835 temp.bitfield.xmmword = 0;
c0f3af97 1836 temp.bitfield.ymmword = 0;
43234a1e 1837 temp.bitfield.zmmword = 0;
0dfbf9d7 1838 if (operand_type_all_zero (&temp))
891edac4 1839 goto mismatch;
40fb9820 1840
891edac4
L		 1841 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1842 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1843 return 1;
1844
1845mismatch:
a65babc9 1846 i.error = operand_type_mismatch;
891edac4 1847 return 0;
40fb9820
L		 1848}
1849
7d5e4556 1850/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1851 unless the expected operand type register overlap is null.
1852 Note that Acc in a template matches every size of reg. */
1853
c6fb90c8 1854static INLINE int
40fb9820
L		 1855operand_type_register_match (i386_operand_type m0,
1856 i386_operand_type g0,
1857 i386_operand_type t0,
1858 i386_operand_type m1,
1859 i386_operand_type g1,
1860 i386_operand_type t1)
1861{
1862 if (!operand_type_check (g0, reg))
1863 return 1;
1864
1865 if (!operand_type_check (g1, reg))
1866 return 1;
1867
1868 if (g0.bitfield.reg8 == g1.bitfield.reg8
1869 && g0.bitfield.reg16 == g1.bitfield.reg16
1870 && g0.bitfield.reg32 == g1.bitfield.reg32
1871 && g0.bitfield.reg64 == g1.bitfield.reg64)
1872 return 1;
1873
1874 if (m0.bitfield.acc)
1875 {
1876 t0.bitfield.reg8 = 1;
1877 t0.bitfield.reg16 = 1;
1878 t0.bitfield.reg32 = 1;
1879 t0.bitfield.reg64 = 1;
1880 }
1881
1882 if (m1.bitfield.acc)
1883 {
1884 t1.bitfield.reg8 = 1;
1885 t1.bitfield.reg16 = 1;
1886 t1.bitfield.reg32 = 1;
1887 t1.bitfield.reg64 = 1;
1888 }
1889
891edac4
L		 1890 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1891 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1892 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1893 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1894 return 1;
1895
a65babc9 1896 i.error = register_type_mismatch;
891edac4
L		 1897
1898 return 0;
40fb9820
L		 1899}
1900
4c692bc7
JB		 1901static INLINE unsigned int
1902register_number (const reg_entry *r)
1903{
1904 unsigned int nr = r->reg_num;
1905
1906 if (r->reg_flags & RegRex)
1907 nr += 8;
1908
1909 return nr;
1910}
1911
252b5132 1912static INLINE unsigned int
40fb9820 1913mode_from_disp_size (i386_operand_type t)
252b5132 1914{
43234a1e 1915 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1916 return 1;
1917 else if (t.bitfield.disp16
1918 || t.bitfield.disp32
1919 || t.bitfield.disp32s)
1920 return 2;
1921 else
1922 return 0;
252b5132
RH		 1923}
1924
1925static INLINE int
e3bb37b5 1926fits_in_signed_byte (offsetT num)
252b5132
RH		 1927{
1928 return (num >= -128) && (num <= 127);
47926f60 1929}
252b5132
RH		 1930
1931static INLINE int
e3bb37b5 1932fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1933{
1934 return (num & 0xff) == num;
47926f60 1935}
252b5132
RH		 1936
1937static INLINE int
e3bb37b5 1938fits_in_unsigned_word (offsetT num)
252b5132
RH		 1939{
1940 return (num & 0xffff) == num;
47926f60 1941}
252b5132
RH		 1942
1943static INLINE int
e3bb37b5 1944fits_in_signed_word (offsetT num)
252b5132
RH		 1945{
1946 return (-32768 <= num) && (num <= 32767);
47926f60 1947}
2a962e6d 1948
3e73aa7c 1949static INLINE int
e3bb37b5 1950fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1951{
1952#ifndef BFD64
1953 return 1;
1954#else
1955 return (!(((offsetT) -1 << 31) & num)
1956 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1957#endif
1958} /* fits_in_signed_long() */
2a962e6d 1959
3e73aa7c 1960static INLINE int
e3bb37b5 1961fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1962{
1963#ifndef BFD64
1964 return 1;
1965#else
1966 return (num & (((offsetT) 2 << 31) - 1)) == num;
1967#endif
1968} /* fits_in_unsigned_long() */
252b5132 1969
43234a1e
L		 1970static INLINE int
1971fits_in_vec_disp8 (offsetT num)
1972{
1973 int shift = i.memshift;
1974 unsigned int mask;
1975
1976 if (shift == -1)
1977 abort ();
1978
1979 mask = (1 << shift) - 1;
1980
1981 /* Return 0 if NUM isn't properly aligned. */
1982 if ((num & mask))
1983 return 0;
1984
1985 /* Check if NUM will fit in 8bit after shift. */
1986 return fits_in_signed_byte (num >> shift);
1987}
1988
a683cc34
SP		 1989static INLINE int
1990fits_in_imm4 (offsetT num)
1991{
1992 return (num & 0xf) == num;
1993}
1994
40fb9820 1995static i386_operand_type
e3bb37b5 1996smallest_imm_type (offsetT num)
252b5132 1997{
40fb9820 1998 i386_operand_type t;
7ab9ffdd 1999
0dfbf9d7 2000 operand_type_set (&t, 0);
40fb9820
L		 2001 t.bitfield.imm64 = 1;
2002
2003 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2004 {
2005 /* This code is disabled on the 486 because all the Imm1 forms
2006 in the opcode table are slower on the i486. They're the
2007 versions with the implicitly specified single-position
2008 displacement, which has another syntax if you really want to
2009 use that form. */
40fb9820
L		 2010 t.bitfield.imm1 = 1;
2011 t.bitfield.imm8 = 1;
2012 t.bitfield.imm8s = 1;
2013 t.bitfield.imm16 = 1;
2014 t.bitfield.imm32 = 1;
2015 t.bitfield.imm32s = 1;
2016 }
2017 else if (fits_in_signed_byte (num))
2018 {
2019 t.bitfield.imm8 = 1;
2020 t.bitfield.imm8s = 1;
2021 t.bitfield.imm16 = 1;
2022 t.bitfield.imm32 = 1;
2023 t.bitfield.imm32s = 1;
2024 }
2025 else if (fits_in_unsigned_byte (num))
2026 {
2027 t.bitfield.imm8 = 1;
2028 t.bitfield.imm16 = 1;
2029 t.bitfield.imm32 = 1;
2030 t.bitfield.imm32s = 1;
2031 }
2032 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2033 {
2034 t.bitfield.imm16 = 1;
2035 t.bitfield.imm32 = 1;
2036 t.bitfield.imm32s = 1;
2037 }
2038 else if (fits_in_signed_long (num))
2039 {
2040 t.bitfield.imm32 = 1;
2041 t.bitfield.imm32s = 1;
2042 }
2043 else if (fits_in_unsigned_long (num))
2044 t.bitfield.imm32 = 1;
2045
2046 return t;
47926f60 2047}
252b5132 2048
847f7ad4 2049static offsetT
e3bb37b5 2050offset_in_range (offsetT val, int size)
847f7ad4 2051{
508866be 2052 addressT mask;
ba2adb93 2053
847f7ad4
AM		 2054 switch (size)
2055 {
508866be
L		 2056 case 1: mask = ((addressT) 1 << 8) - 1; break;
2057 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2058 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2059#ifdef BFD64
2060 case 8: mask = ((addressT) 2 << 63) - 1; break;
2061#endif
47926f60 2062 default: abort ();
847f7ad4
AM		 2063 }
2064
9de868bf
L		 2065#ifdef BFD64
2066 /* If BFD64, sign extend val for 32bit address mode. */
2067 if (flag_code != CODE_64BIT
2068 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2069 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2070 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2071#endif
ba2adb93 2072
47926f60 2073 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2074 {
2075 char buf1[40], buf2[40];
2076
2077 sprint_value (buf1, val);
2078 sprint_value (buf2, val & mask);
2079 as_warn (_("%s shortened to %s"), buf1, buf2);
2080 }
2081 return val & mask;
2082}
2083
c32fa91d
L		 2084enum PREFIX_GROUP
2085{
2086 PREFIX_EXIST = 0,
2087 PREFIX_LOCK,
2088 PREFIX_REP,
2089 PREFIX_OTHER
2090};
2091
2092/* Returns
2093 a. PREFIX_EXIST if attempting to add a prefix where one from the
2094 same class already exists.
2095 b. PREFIX_LOCK if lock prefix is added.
2096 c. PREFIX_REP if rep/repne prefix is added.
2097 d. PREFIX_OTHER if other prefix is added.
2098 */
2099
2100static enum PREFIX_GROUP
e3bb37b5 2101add_prefix (unsigned int prefix)
252b5132 2102{
c32fa91d 2103 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2104 unsigned int q;
252b5132 2105
29b0f896
AM		 2106 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2107 && flag_code == CODE_64BIT)
b1905489 2108 {
161a04f6
L		 2109 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2110 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2111 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2112 ret = PREFIX_EXIST;
b1905489
JB		 2113 q = REX_PREFIX;
2114 }
3e73aa7c 2115 else
b1905489
JB		 2116 {
2117 switch (prefix)
2118 {
2119 default:
2120 abort ();
2121
2122 case CS_PREFIX_OPCODE:
2123 case DS_PREFIX_OPCODE:
2124 case ES_PREFIX_OPCODE:
2125 case FS_PREFIX_OPCODE:
2126 case GS_PREFIX_OPCODE:
2127 case SS_PREFIX_OPCODE:
2128 q = SEG_PREFIX;
2129 break;
2130
2131 case REPNE_PREFIX_OPCODE:
2132 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2133 q = REP_PREFIX;
2134 ret = PREFIX_REP;
2135 break;
2136
b1905489 2137 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2138 q = LOCK_PREFIX;
2139 ret = PREFIX_LOCK;
b1905489
JB		 2140 break;
2141
2142 case FWAIT_OPCODE:
2143 q = WAIT_PREFIX;
2144 break;
2145
2146 case ADDR_PREFIX_OPCODE:
2147 q = ADDR_PREFIX;
2148 break;
2149
2150 case DATA_PREFIX_OPCODE:
2151 q = DATA_PREFIX;
2152 break;
2153 }
2154 if (i.prefix[q] != 0)
c32fa91d 2155 ret = PREFIX_EXIST;
b1905489 2156 }
252b5132 2157
b1905489 2158 if (ret)
252b5132 2159 {
b1905489
JB		 2160 if (!i.prefix[q])
2161 ++i.prefixes;
2162 i.prefix[q] |= prefix;
252b5132 2163 }
b1905489
JB		 2164 else
2165 as_bad (_("same type of prefix used twice"));
252b5132 2166
252b5132
RH		 2167 return ret;
2168}
2169
2170static void
78f12dd3 2171update_code_flag (int value, int check)
eecb386c 2172{
78f12dd3
L		 2173 PRINTF_LIKE ((*as_error));
2174
1e9cc1c2 2175 flag_code = (enum flag_code) value;
40fb9820
L		 2176 if (flag_code == CODE_64BIT)
2177 {
2178 cpu_arch_flags.bitfield.cpu64 = 1;
2179 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2180 }
2181 else
2182 {
2183 cpu_arch_flags.bitfield.cpu64 = 0;
2184 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2185 }
2186 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2187 {
78f12dd3
L		 2188 if (check)
2189 as_error = as_fatal;
2190 else
2191 as_error = as_bad;
2192 (*as_error) (_("64bit mode not supported on `%s'."),
2193 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2194 }
40fb9820 2195 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2196 {
78f12dd3
L		 2197 if (check)
2198 as_error = as_fatal;
2199 else
2200 as_error = as_bad;
2201 (*as_error) (_("32bit mode not supported on `%s'."),
2202 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2203 }
eecb386c
AM		 2204 stackop_size = '\0';
2205}
2206
78f12dd3
L		 2207static void
2208set_code_flag (int value)
2209{
2210 update_code_flag (value, 0);
2211}
2212
eecb386c 2213static void
e3bb37b5 2214set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2215{
1e9cc1c2 2216 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2217 if (flag_code != CODE_16BIT)
2218 abort ();
2219 cpu_arch_flags.bitfield.cpu64 = 0;
2220 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2221 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2222}
2223
2224static void
e3bb37b5 2225set_intel_syntax (int syntax_flag)
252b5132
RH		 2226{
2227 /* Find out if register prefixing is specified. */
2228 int ask_naked_reg = 0;
2229
2230 SKIP_WHITESPACE ();
29b0f896 2231 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2232 {
2233 char *string = input_line_pointer;
2234 int e = get_symbol_end ();
2235
47926f60 2236 if (strcmp (string, "prefix") == 0)
252b5132 2237 ask_naked_reg = 1;
47926f60 2238 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2239 ask_naked_reg = -1;
2240 else
d0b47220 2241 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2242 *input_line_pointer = e;
2243 }
2244 demand_empty_rest_of_line ();
c3332e24 2245
252b5132
RH		 2246 intel_syntax = syntax_flag;
2247
2248 if (ask_naked_reg == 0)
f86103b7
AM		 2249 allow_naked_reg = (intel_syntax
2250 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2251 else
2252 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2253
ee86248c 2254 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2255
e4a3b5a4 2256 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2257 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2258 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2259}
2260
1efbbeb4
L		 2261static void
2262set_intel_mnemonic (int mnemonic_flag)
2263{
e1d4d893 2264 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2265}
2266
db51cc60
L		 2267static void
2268set_allow_index_reg (int flag)
2269{
2270 allow_index_reg = flag;
2271}
2272
cb19c032 2273static void
7bab8ab5 2274set_check (int what)
cb19c032 2275{
7bab8ab5
JB		 2276 enum check_kind *kind;
2277 const char *str;
2278
2279 if (what)
2280 {
2281 kind = &operand_check;
2282 str = "operand";
2283 }
2284 else
2285 {
2286 kind = &sse_check;
2287 str = "sse";
2288 }
2289
cb19c032
L		 2290 SKIP_WHITESPACE ();
2291
2292 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2293 {
2294 char *string = input_line_pointer;
2295 int e = get_symbol_end ();
2296
2297 if (strcmp (string, "none") == 0)
7bab8ab5 2298 *kind = check_none;
cb19c032 2299 else if (strcmp (string, "warning") == 0)
7bab8ab5 2300 *kind = check_warning;
cb19c032 2301 else if (strcmp (string, "error") == 0)
7bab8ab5 2302 *kind = check_error;
cb19c032 2303 else
7bab8ab5 2304 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2305 *input_line_pointer = e;
2306 }
2307 else
7bab8ab5 2308 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2309
2310 demand_empty_rest_of_line ();
2311}
2312
8a9036a4
L		 2313static void
2314check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2315 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2316{
2317#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2318 static const char *arch;
2319
2320 /* Intel LIOM is only supported on ELF. */
2321 if (!IS_ELF)
2322 return;
2323
2324 if (!arch)
2325 {
2326 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2327 use default_arch. */
2328 arch = cpu_arch_name;
2329 if (!arch)
2330 arch = default_arch;
2331 }
2332
3632d14b 2333 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2334 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2335 || new_flag.bitfield.cpul1om)
8a9036a4 2336 return;
76ba9986 2337
7a9068fe
L		 2338 /* If we are targeting Intel K1OM, we must enable it. */
2339 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2340 || new_flag.bitfield.cpuk1om)
2341 return;
2342
8a9036a4
L		 2343 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2344#endif
2345}
2346
e413e4e9 2347static void
e3bb37b5 2348set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2349{
47926f60 2350 SKIP_WHITESPACE ();
e413e4e9 2351
29b0f896 2352 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2353 {
2354 char *string = input_line_pointer;
2355 int e = get_symbol_end ();
91d6fa6a 2356 unsigned int j;
40fb9820 2357 i386_cpu_flags flags;
e413e4e9 2358
91d6fa6a 2359 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2360 {
91d6fa6a 2361 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2362 {
91d6fa6a 2363 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2364
5c6af06e
JB		 2365 if (*string != '.')
2366 {
91d6fa6a 2367 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2368 cpu_sub_arch_name = NULL;
91d6fa6a 2369 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2370 if (flag_code == CODE_64BIT)
2371 {
2372 cpu_arch_flags.bitfield.cpu64 = 1;
2373 cpu_arch_flags.bitfield.cpuno64 = 0;
2374 }
2375 else
2376 {
2377 cpu_arch_flags.bitfield.cpu64 = 0;
2378 cpu_arch_flags.bitfield.cpuno64 = 1;
2379 }
91d6fa6a
NC		 2380 cpu_arch_isa = cpu_arch[j].type;
2381 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2382 if (!cpu_arch_tune_set)
2383 {
2384 cpu_arch_tune = cpu_arch_isa;
2385 cpu_arch_tune_flags = cpu_arch_isa_flags;
2386 }
5c6af06e
JB		 2387 break;
2388 }
40fb9820 2389
22109423 2390 if (!cpu_arch[j].negated)
309d3373 2391 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2392 cpu_arch[j].flags);
309d3373
JB		 2393 else
2394 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2395 cpu_arch[j].flags);
0dfbf9d7 2396 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2397 {
6305a203
L		 2398 if (cpu_sub_arch_name)
2399 {
2400 char *name = cpu_sub_arch_name;
2401 cpu_sub_arch_name = concat (name,
91d6fa6a 2402 cpu_arch[j].name,
1bf57e9f 2403 (const char *) NULL);
6305a203
L		 2404 free (name);
2405 }
2406 else
91d6fa6a 2407 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2408 cpu_arch_flags = flags;
a586129e 2409 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2410 }
2411 *input_line_pointer = e;
2412 demand_empty_rest_of_line ();
2413 return;
e413e4e9
AM		 2414 }
2415 }
91d6fa6a 2416 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2417 as_bad (_("no such architecture: `%s'"), string);
2418
2419 *input_line_pointer = e;
2420 }
2421 else
2422 as_bad (_("missing cpu architecture"));
2423
fddf5b5b
AM		 2424 no_cond_jump_promotion = 0;
2425 if (*input_line_pointer == ','
29b0f896 2426 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2427 {
2428 char *string = ++input_line_pointer;
2429 int e = get_symbol_end ();
2430
2431 if (strcmp (string, "nojumps") == 0)
2432 no_cond_jump_promotion = 1;
2433 else if (strcmp (string, "jumps") == 0)
2434 ;
2435 else
2436 as_bad (_("no such architecture modifier: `%s'"), string);
2437
2438 *input_line_pointer = e;
2439 }
2440
e413e4e9
AM		 2441 demand_empty_rest_of_line ();
2442}
2443
8a9036a4
L		 2444enum bfd_architecture
2445i386_arch (void)
2446{
3632d14b 2447 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2448 {
2449 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2450 || flag_code != CODE_64BIT)
2451 as_fatal (_("Intel L1OM is 64bit ELF only"));
2452 return bfd_arch_l1om;
2453 }
7a9068fe
L		 2454 else if (cpu_arch_isa == PROCESSOR_K1OM)
2455 {
2456 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2457 || flag_code != CODE_64BIT)
2458 as_fatal (_("Intel K1OM is 64bit ELF only"));
2459 return bfd_arch_k1om;
2460 }
8a9036a4
L		 2461 else
2462 return bfd_arch_i386;
2463}
2464
b9d79e03 2465unsigned long
7016a5d5 2466i386_mach (void)
b9d79e03 2467{
351f65ca 2468 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2469 {
3632d14b 2470 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2471 {
351f65ca
L		 2472 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2473 || default_arch[6] != '\0')
8a9036a4
L		 2474 as_fatal (_("Intel L1OM is 64bit ELF only"));
2475 return bfd_mach_l1om;
2476 }
7a9068fe
L		 2477 else if (cpu_arch_isa == PROCESSOR_K1OM)
2478 {
2479 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2480 || default_arch[6] != '\0')
2481 as_fatal (_("Intel K1OM is 64bit ELF only"));
2482 return bfd_mach_k1om;
2483 }
351f65ca 2484 else if (default_arch[6] == '\0')
8a9036a4 2485 return bfd_mach_x86_64;
351f65ca
L		 2486 else
2487 return bfd_mach_x64_32;
8a9036a4 2488 }
b9d79e03
JH		 2489 else if (!strcmp (default_arch, "i386"))
2490 return bfd_mach_i386_i386;
2491 else
2b5d6a91 2492 as_fatal (_("unknown architecture"));
b9d79e03 2493}
b9d79e03 2494\f
252b5132 2495void
7016a5d5 2496md_begin (void)
252b5132
RH		 2497{
2498 const char *hash_err;
2499
47926f60 2500 /* Initialize op_hash hash table. */
252b5132
RH		 2501 op_hash = hash_new ();
2502
2503 {
d3ce72d0 2504 const insn_template *optab;
29b0f896 2505 templates *core_optab;
252b5132 2506
47926f60
KH		 2507 /* Setup for loop. */
2508 optab = i386_optab;
252b5132
RH		 2509 core_optab = (templates *) xmalloc (sizeof (templates));
2510 core_optab->start = optab;
2511
2512 while (1)
2513 {
2514 ++optab;
2515 if (optab->name == NULL
2516 || strcmp (optab->name, (optab - 1)->name) != 0)
2517 {
2518 /* different name --> ship out current template list;
47926f60 2519 add to hash table; & begin anew. */
252b5132
RH		 2520 core_optab->end = optab;
2521 hash_err = hash_insert (op_hash,
2522 (optab - 1)->name,
5a49b8ac 2523 (void *) core_optab);
252b5132
RH		 2524 if (hash_err)
2525 {
b37df7c4 2526 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2527 (optab - 1)->name,
2528 hash_err);
2529 }
2530 if (optab->name == NULL)
2531 break;
2532 core_optab = (templates *) xmalloc (sizeof (templates));
2533 core_optab->start = optab;
2534 }
2535 }
2536 }
2537
47926f60 2538 /* Initialize reg_hash hash table. */
252b5132
RH		 2539 reg_hash = hash_new ();
2540 {
29b0f896 2541 const reg_entry *regtab;
c3fe08fa 2542 unsigned int regtab_size = i386_regtab_size;
252b5132 2543
c3fe08fa 2544 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2545 {
5a49b8ac 2546 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2547 if (hash_err)
b37df7c4 2548 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2549 regtab->reg_name,
2550 hash_err);
252b5132
RH		 2551 }
2552 }
2553
47926f60 2554 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2555 {
29b0f896
AM		 2556 int c;
2557 char *p;
252b5132
RH		 2558
2559 for (c = 0; c < 256; c++)
2560 {
3882b010 2561 if (ISDIGIT (c))
252b5132
RH		 2562 {
2563 digit_chars[c] = c;
2564 mnemonic_chars[c] = c;
2565 register_chars[c] = c;
2566 operand_chars[c] = c;
2567 }
3882b010 2568 else if (ISLOWER (c))
252b5132
RH		 2569 {
2570 mnemonic_chars[c] = c;
2571 register_chars[c] = c;
2572 operand_chars[c] = c;
2573 }
3882b010 2574 else if (ISUPPER (c))
252b5132 2575 {
3882b010 2576 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2577 register_chars[c] = mnemonic_chars[c];
2578 operand_chars[c] = c;
2579 }
43234a1e
L		 2580 else if (c == '{' || c == '}')
2581 operand_chars[c] = c;
252b5132 2582
3882b010 2583 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2584 identifier_chars[c] = c;
2585 else if (c >= 128)
2586 {
2587 identifier_chars[c] = c;
2588 operand_chars[c] = c;
2589 }
2590 }
2591
2592#ifdef LEX_AT
2593 identifier_chars['@'] = '@';
32137342
NC		 2594#endif
2595#ifdef LEX_QM
2596 identifier_chars['?'] = '?';
2597 operand_chars['?'] = '?';
252b5132 2598#endif
252b5132 2599 digit_chars['-'] = '-';
c0f3af97 2600 mnemonic_chars['_'] = '_';
791fe849 2601 mnemonic_chars['-'] = '-';
0003779b 2602 mnemonic_chars['.'] = '.';
252b5132
RH		 2603 identifier_chars['_'] = '_';
2604 identifier_chars['.'] = '.';
2605
2606 for (p = operand_special_chars; *p != '\0'; p++)
2607 operand_chars[(unsigned char) *p] = *p;
2608 }
2609
a4447b93
RH		 2610 if (flag_code == CODE_64BIT)
2611 {
ca19b261
KT		 2612#if defined (OBJ_COFF) && defined (TE_PE)
2613 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2614 ? 32 : 16);
2615#else
a4447b93 2616 x86_dwarf2_return_column = 16;
ca19b261 2617#endif
61ff971f 2618 x86_cie_data_alignment = -8;
a4447b93
RH		 2619 }
2620 else
2621 {
2622 x86_dwarf2_return_column = 8;
2623 x86_cie_data_alignment = -4;
2624 }
252b5132
RH		 2625}
2626
2627void
e3bb37b5 2628i386_print_statistics (FILE *file)
252b5132
RH		 2629{
2630 hash_print_statistics (file, "i386 opcode", op_hash);
2631 hash_print_statistics (file, "i386 register", reg_hash);
2632}
2633\f
252b5132
RH		 2634#ifdef DEBUG386
2635
ce8a8b2f 2636/* Debugging routines for md_assemble. */
d3ce72d0 2637static void pte (insn_template *);
40fb9820 2638static void pt (i386_operand_type);
e3bb37b5
L		 2639static void pe (expressionS *);
2640static void ps (symbolS *);
252b5132
RH		 2641
2642static void
e3bb37b5 2643pi (char *line, i386_insn *x)
252b5132 2644{
09137c09 2645 unsigned int j;
252b5132
RH		 2646
2647 fprintf (stdout, "%s: template ", line);
2648 pte (&x->tm);
09f131f2
JH		 2649 fprintf (stdout, " address: base %s index %s scale %x\n",
2650 x->base_reg ? x->base_reg->reg_name : "none",
2651 x->index_reg ? x->index_reg->reg_name : "none",
2652 x->log2_scale_factor);
2653 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2654 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2655 fprintf (stdout, " sib: base %x index %x scale %x\n",
2656 x->sib.base, x->sib.index, x->sib.scale);
2657 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2658 (x->rex & REX_W) != 0,
2659 (x->rex & REX_R) != 0,
2660 (x->rex & REX_X) != 0,
2661 (x->rex & REX_B) != 0);
09137c09 2662 for (j = 0; j < x->operands; j++)
252b5132 2663 {
09137c09
SP		 2664 fprintf (stdout, " #%d: ", j + 1);
2665 pt (x->types[j]);
252b5132 2666 fprintf (stdout, "\n");
09137c09
SP		 2667 if (x->types[j].bitfield.reg8
2668 || x->types[j].bitfield.reg16
2669 || x->types[j].bitfield.reg32
2670 || x->types[j].bitfield.reg64
2671 || x->types[j].bitfield.regmmx
2672 || x->types[j].bitfield.regxmm
2673 || x->types[j].bitfield.regymm
43234a1e 2674 || x->types[j].bitfield.regzmm
09137c09
SP		 2675 || x->types[j].bitfield.sreg2
2676 || x->types[j].bitfield.sreg3
2677 || x->types[j].bitfield.control
2678 || x->types[j].bitfield.debug
2679 || x->types[j].bitfield.test)
2680 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2681 if (operand_type_check (x->types[j], imm))
2682 pe (x->op[j].imms);
2683 if (operand_type_check (x->types[j], disp))
2684 pe (x->op[j].disps);
252b5132
RH		 2685 }
2686}
2687
2688static void
d3ce72d0 2689pte (insn_template *t)
252b5132 2690{
09137c09 2691 unsigned int j;
252b5132 2692 fprintf (stdout, " %d operands ", t->operands);
47926f60 2693 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2694 if (t->extension_opcode != None)
2695 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2696 if (t->opcode_modifier.d)
252b5132 2697 fprintf (stdout, "D");
40fb9820 2698 if (t->opcode_modifier.w)
252b5132
RH		 2699 fprintf (stdout, "W");
2700 fprintf (stdout, "\n");
09137c09 2701 for (j = 0; j < t->operands; j++)
252b5132 2702 {
09137c09
SP		 2703 fprintf (stdout, " #%d type ", j + 1);
2704 pt (t->operand_types[j]);
252b5132
RH		 2705 fprintf (stdout, "\n");
2706 }
2707}
2708
2709static void
e3bb37b5 2710pe (expressionS *e)
252b5132 2711{
24eab124 2712 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2713 fprintf (stdout, " add_number %ld (%lx)\n",
2714 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2715 if (e->X_add_symbol)
2716 {
2717 fprintf (stdout, " add_symbol ");
2718 ps (e->X_add_symbol);
2719 fprintf (stdout, "\n");
2720 }
2721 if (e->X_op_symbol)
2722 {
2723 fprintf (stdout, " op_symbol ");
2724 ps (e->X_op_symbol);
2725 fprintf (stdout, "\n");
2726 }
2727}
2728
2729static void
e3bb37b5 2730ps (symbolS *s)
252b5132
RH		 2731{
2732 fprintf (stdout, "%s type %s%s",
2733 S_GET_NAME (s),
2734 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2735 segment_name (S_GET_SEGMENT (s)));
2736}
2737
7b81dfbb 2738static struct type_name
252b5132 2739 {
40fb9820
L		 2740 i386_operand_type mask;
2741 const char *name;
252b5132 2742 }
7b81dfbb 2743const type_names[] =
252b5132 2744{
40fb9820
L		 2745 { OPERAND_TYPE_REG8, "r8" },
2746 { OPERAND_TYPE_REG16, "r16" },
2747 { OPERAND_TYPE_REG32, "r32" },
2748 { OPERAND_TYPE_REG64, "r64" },
2749 { OPERAND_TYPE_IMM8, "i8" },
2750 { OPERAND_TYPE_IMM8, "i8s" },
2751 { OPERAND_TYPE_IMM16, "i16" },
2752 { OPERAND_TYPE_IMM32, "i32" },
2753 { OPERAND_TYPE_IMM32S, "i32s" },
2754 { OPERAND_TYPE_IMM64, "i64" },
2755 { OPERAND_TYPE_IMM1, "i1" },
2756 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2757 { OPERAND_TYPE_DISP8, "d8" },
2758 { OPERAND_TYPE_DISP16, "d16" },
2759 { OPERAND_TYPE_DISP32, "d32" },
2760 { OPERAND_TYPE_DISP32S, "d32s" },
2761 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2762 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2763 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2764 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2765 { OPERAND_TYPE_CONTROL, "control reg" },
2766 { OPERAND_TYPE_TEST, "test reg" },
2767 { OPERAND_TYPE_DEBUG, "debug reg" },
2768 { OPERAND_TYPE_FLOATREG, "FReg" },
2769 { OPERAND_TYPE_FLOATACC, "FAcc" },
2770 { OPERAND_TYPE_SREG2, "SReg2" },
2771 { OPERAND_TYPE_SREG3, "SReg3" },
2772 { OPERAND_TYPE_ACC, "Acc" },
2773 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2774 { OPERAND_TYPE_REGMMX, "rMMX" },
2775 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2776 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2777 { OPERAND_TYPE_REGZMM, "rZMM" },
2778 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2779 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2780};
2781
2782static void
40fb9820 2783pt (i386_operand_type t)
252b5132 2784{
40fb9820 2785 unsigned int j;
c6fb90c8 2786 i386_operand_type a;
252b5132 2787
40fb9820 2788 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2789 {
2790 a = operand_type_and (t, type_names[j].mask);
0349dc08 2791 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2792 fprintf (stdout, "%s, ", type_names[j].name);
2793 }
252b5132
RH		 2794 fflush (stdout);
2795}
2796
2797#endif /* DEBUG386 */
2798\f
252b5132 2799static bfd_reloc_code_real_type
3956db08 2800reloc (unsigned int size,
64e74474
AM		 2801 int pcrel,
2802 int sign,
c3320543 2803 int bnd_prefix,
64e74474 2804 bfd_reloc_code_real_type other)
252b5132 2805{
47926f60 2806 if (other != NO_RELOC)
3956db08 2807 {
91d6fa6a 2808 reloc_howto_type *rel;
3956db08
JB		 2809
2810 if (size == 8)
2811 switch (other)
2812 {
64e74474
AM		 2813 case BFD_RELOC_X86_64_GOT32:
2814 return BFD_RELOC_X86_64_GOT64;
2815 break;
2816 case BFD_RELOC_X86_64_PLTOFF64:
2817 return BFD_RELOC_X86_64_PLTOFF64;
2818 break;
2819 case BFD_RELOC_X86_64_GOTPC32:
2820 other = BFD_RELOC_X86_64_GOTPC64;
2821 break;
2822 case BFD_RELOC_X86_64_GOTPCREL:
2823 other = BFD_RELOC_X86_64_GOTPCREL64;
2824 break;
2825 case BFD_RELOC_X86_64_TPOFF32:
2826 other = BFD_RELOC_X86_64_TPOFF64;
2827 break;
2828 case BFD_RELOC_X86_64_DTPOFF32:
2829 other = BFD_RELOC_X86_64_DTPOFF64;
2830 break;
2831 default:
2832 break;
3956db08 2833 }
e05278af 2834
8ce3d284 2835#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2836 if (other == BFD_RELOC_SIZE32)
2837 {
2838 if (size == 8)
2839 return BFD_RELOC_SIZE64;
2840 if (pcrel)
2841 as_bad (_("there are no pc-relative size relocations"));
2842 }
8ce3d284 2843#endif
8fd4256d 2844
e05278af 2845 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2846 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2847 sign = -1;
2848
91d6fa6a
NC		 2849 rel = bfd_reloc_type_lookup (stdoutput, other);
2850 if (!rel)
3956db08 2851 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2852 else if (size != bfd_get_reloc_size (rel))
3956db08 2853 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2854 bfd_get_reloc_size (rel),
3956db08 2855 size);
91d6fa6a 2856 else if (pcrel && !rel->pc_relative)
3956db08 2857 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2858 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2859 && !sign)
91d6fa6a 2860 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2861 && sign > 0))
3956db08
JB		 2862 as_bad (_("relocated field and relocation type differ in signedness"));
2863 else
2864 return other;
2865 return NO_RELOC;
2866 }
252b5132
RH		 2867
2868 if (pcrel)
2869 {
3e73aa7c 2870 if (!sign)
3956db08 2871 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2872 switch (size)
2873 {
2874 case 1: return BFD_RELOC_8_PCREL;
2875 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2876 case 4: return (bnd_prefix && object_64bit
2877 ? BFD_RELOC_X86_64_PC32_BND
2878 : BFD_RELOC_32_PCREL);
d6ab8113 2879 case 8: return BFD_RELOC_64_PCREL;
252b5132 2880 }
3956db08 2881 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2882 }
2883 else
2884 {
3956db08 2885 if (sign > 0)
e5cb08ac 2886 switch (size)
3e73aa7c
JH		 2887 {
2888 case 4: return BFD_RELOC_X86_64_32S;
2889 }
2890 else
2891 switch (size)
2892 {
2893 case 1: return BFD_RELOC_8;
2894 case 2: return BFD_RELOC_16;
2895 case 4: return BFD_RELOC_32;
2896 case 8: return BFD_RELOC_64;
2897 }
3956db08
JB		 2898 as_bad (_("cannot do %s %u byte relocation"),
2899 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2900 }
2901
0cc9e1d3 2902 return NO_RELOC;
252b5132
RH		 2903}
2904
47926f60
KH		 2905/* Here we decide which fixups can be adjusted to make them relative to
2906 the beginning of the section instead of the symbol. Basically we need
2907 to make sure that the dynamic relocations are done correctly, so in
2908 some cases we force the original symbol to be used. */
2909
252b5132 2910int
e3bb37b5 2911tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2912{
6d249963 2913#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2914 if (!IS_ELF)
31312f95
AM		 2915 return 1;
2916
a161fe53
AM		 2917 /* Don't adjust pc-relative references to merge sections in 64-bit
2918 mode. */
2919 if (use_rela_relocations
2920 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2921 && fixP->fx_pcrel)
252b5132 2922 return 0;
31312f95 2923
8d01d9a9
AJ		 2924 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2925 and changed later by validate_fix. */
2926 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2927 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2928 return 0;
2929
8fd4256d
L		 2930 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2931 for size relocations. */
2932 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2933 || fixP->fx_r_type == BFD_RELOC_SIZE64
2934 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2935 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2936 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2944 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2945 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2946 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2947 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2949 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2950 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2951 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2954 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2955 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2956 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2957 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2958 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2959 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2960 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2961 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2962 return 0;
31312f95 2963#endif
252b5132
RH		 2964 return 1;
2965}
252b5132 2966
b4cac588 2967static int
e3bb37b5 2968intel_float_operand (const char *mnemonic)
252b5132 2969{
9306ca4a
JB		 2970 /* Note that the value returned is meaningful only for opcodes with (memory)
2971 operands, hence the code here is free to improperly handle opcodes that
2972 have no operands (for better performance and smaller code). */
2973
2974 if (mnemonic[0] != 'f')
2975 return 0; /* non-math */
2976
2977 switch (mnemonic[1])
2978 {
2979 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2980 the fs segment override prefix not currently handled because no
2981 call path can make opcodes without operands get here */
2982 case 'i':
2983 return 2 /* integer op */;
2984 case 'l':
2985 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2986 return 3; /* fldcw/fldenv */
2987 break;
2988 case 'n':
2989 if (mnemonic[2] != 'o' /* fnop */)
2990 return 3; /* non-waiting control op */
2991 break;
2992 case 'r':
2993 if (mnemonic[2] == 's')
2994 return 3; /* frstor/frstpm */
2995 break;
2996 case 's':
2997 if (mnemonic[2] == 'a')
2998 return 3; /* fsave */
2999 if (mnemonic[2] == 't')
3000 {
3001 switch (mnemonic[3])
3002 {
3003 case 'c': /* fstcw */
3004 case 'd': /* fstdw */
3005 case 'e': /* fstenv */
3006 case 's': /* fsts[gw] */
3007 return 3;
3008 }
3009 }
3010 break;
3011 case 'x':
3012 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3013 return 0; /* fxsave/fxrstor are not really math ops */
3014 break;
3015 }
252b5132 3016
9306ca4a 3017 return 1;
252b5132
RH		 3018}
3019
c0f3af97
L		 3020/* Build the VEX prefix. */
3021
3022static void
d3ce72d0 3023build_vex_prefix (const insn_template *t)
c0f3af97
L		 3024{
3025 unsigned int register_specifier;
3026 unsigned int implied_prefix;
3027 unsigned int vector_length;
3028
3029 /* Check register specifier. */
3030 if (i.vex.register_specifier)
43234a1e
L		 3031 {
3032 register_specifier =
3033 ~register_number (i.vex.register_specifier) & 0xf;
3034 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3035 }
c0f3af97
L		 3036 else
3037 register_specifier = 0xf;
3038
fa99fab2
L		 3039 /* Use 2-byte VEX prefix by swappping destination and source
3040 operand. */
3041 if (!i.swap_operand
3042 && i.operands == i.reg_operands
7f399153 3043 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3044 && i.tm.opcode_modifier.s
3045 && i.rex == REX_B)
3046 {
3047 unsigned int xchg = i.operands - 1;
3048 union i386_op temp_op;
3049 i386_operand_type temp_type;
3050
3051 temp_type = i.types[xchg];
3052 i.types[xchg] = i.types[0];
3053 i.types[0] = temp_type;
3054 temp_op = i.op[xchg];
3055 i.op[xchg] = i.op[0];
3056 i.op[0] = temp_op;
3057
9c2799c2 3058 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3059
3060 i.rex = REX_R;
3061 xchg = i.rm.regmem;
3062 i.rm.regmem = i.rm.reg;
3063 i.rm.reg = xchg;
3064
3065 /* Use the next insn. */
3066 i.tm = t[1];
3067 }
3068
539f890d
L		 3069 if (i.tm.opcode_modifier.vex == VEXScalar)
3070 vector_length = avxscalar;
3071 else
3072 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3073
3074 switch ((i.tm.base_opcode >> 8) & 0xff)
3075 {
3076 case 0:
3077 implied_prefix = 0;
3078 break;
3079 case DATA_PREFIX_OPCODE:
3080 implied_prefix = 1;
3081 break;
3082 case REPE_PREFIX_OPCODE:
3083 implied_prefix = 2;
3084 break;
3085 case REPNE_PREFIX_OPCODE:
3086 implied_prefix = 3;
3087 break;
3088 default:
3089 abort ();
3090 }
3091
3092 /* Use 2-byte VEX prefix if possible. */
7f399153 3093 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3094 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3095 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3096 {
3097 /* 2-byte VEX prefix. */
3098 unsigned int r;
3099
3100 i.vex.length = 2;
3101 i.vex.bytes[0] = 0xc5;
3102
3103 /* Check the REX.R bit. */
3104 r = (i.rex & REX_R) ? 0 : 1;
3105 i.vex.bytes[1] = (r << 7
3106 | register_specifier << 3
3107 | vector_length << 2
3108 | implied_prefix);
3109 }
3110 else
3111 {
3112 /* 3-byte VEX prefix. */
3113 unsigned int m, w;
3114
f88c9eb0 3115 i.vex.length = 3;
f88c9eb0 3116
7f399153 3117 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3118 {
7f399153
L		 3119 case VEX0F:
3120 m = 0x1;
80de6e00 3121 i.vex.bytes[0] = 0xc4;
7f399153
L		 3122 break;
3123 case VEX0F38:
3124 m = 0x2;
80de6e00 3125 i.vex.bytes[0] = 0xc4;
7f399153
L		 3126 break;
3127 case VEX0F3A:
3128 m = 0x3;
80de6e00 3129 i.vex.bytes[0] = 0xc4;
7f399153
L		 3130 break;
3131 case XOP08:
5dd85c99
SP		 3132 m = 0x8;
3133 i.vex.bytes[0] = 0x8f;
7f399153
L		 3134 break;
3135 case XOP09:
f88c9eb0
SP		 3136 m = 0x9;
3137 i.vex.bytes[0] = 0x8f;
7f399153
L		 3138 break;
3139 case XOP0A:
f88c9eb0
SP		 3140 m = 0xa;
3141 i.vex.bytes[0] = 0x8f;
7f399153
L		 3142 break;
3143 default:
3144 abort ();
f88c9eb0 3145 }
c0f3af97 3146
c0f3af97
L		 3147 /* The high 3 bits of the second VEX byte are 1's compliment
3148 of RXB bits from REX. */
3149 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3150
3151 /* Check the REX.W bit. */
3152 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3153 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3154 {
3155 if (w)
3156 abort ();
3157
1ef99a7b 3158 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3159 w = 1;
3160 }
3161
3162 i.vex.bytes[2] = (w << 7
3163 | register_specifier << 3
3164 | vector_length << 2
3165 | implied_prefix);
3166 }
3167}
3168
43234a1e
L		 3169/* Build the EVEX prefix. */
3170
3171static void
3172build_evex_prefix (void)
3173{
3174 unsigned int register_specifier;
3175 unsigned int implied_prefix;
3176 unsigned int m, w;
3177 rex_byte vrex_used = 0;
3178
3179 /* Check register specifier. */
3180 if (i.vex.register_specifier)
3181 {
3182 gas_assert ((i.vrex & REX_X) == 0);
3183
3184 register_specifier = i.vex.register_specifier->reg_num;
3185 if ((i.vex.register_specifier->reg_flags & RegRex))
3186 register_specifier += 8;
3187 /* The upper 16 registers are encoded in the fourth byte of the
3188 EVEX prefix. */
3189 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3190 i.vex.bytes[3] = 0x8;
3191 register_specifier = ~register_specifier & 0xf;
3192 }
3193 else
3194 {
3195 register_specifier = 0xf;
3196
3197 /* Encode upper 16 vector index register in the fourth byte of
3198 the EVEX prefix. */
3199 if (!(i.vrex & REX_X))
3200 i.vex.bytes[3] = 0x8;
3201 else
3202 vrex_used |= REX_X;
3203 }
3204
3205 switch ((i.tm.base_opcode >> 8) & 0xff)
3206 {
3207 case 0:
3208 implied_prefix = 0;
3209 break;
3210 case DATA_PREFIX_OPCODE:
3211 implied_prefix = 1;
3212 break;
3213 case REPE_PREFIX_OPCODE:
3214 implied_prefix = 2;
3215 break;
3216 case REPNE_PREFIX_OPCODE:
3217 implied_prefix = 3;
3218 break;
3219 default:
3220 abort ();
3221 }
3222
3223 /* 4 byte EVEX prefix. */
3224 i.vex.length = 4;
3225 i.vex.bytes[0] = 0x62;
3226
3227 /* mmmm bits. */
3228 switch (i.tm.opcode_modifier.vexopcode)
3229 {
3230 case VEX0F:
3231 m = 1;
3232 break;
3233 case VEX0F38:
3234 m = 2;
3235 break;
3236 case VEX0F3A:
3237 m = 3;
3238 break;
3239 default:
3240 abort ();
3241 break;
3242 }
3243
3244 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3245 bits from REX. */
3246 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3247
3248 /* The fifth bit of the second EVEX byte is 1's compliment of the
3249 REX_R bit in VREX. */
3250 if (!(i.vrex & REX_R))
3251 i.vex.bytes[1] |= 0x10;
3252 else
3253 vrex_used |= REX_R;
3254
3255 if ((i.reg_operands + i.imm_operands) == i.operands)
3256 {
3257 /* When all operands are registers, the REX_X bit in REX is not
3258 used. We reuse it to encode the upper 16 registers, which is
3259 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3260 as 1's compliment. */
3261 if ((i.vrex & REX_B))
3262 {
3263 vrex_used |= REX_B;
3264 i.vex.bytes[1] &= ~0x40;
3265 }
3266 }
3267
3268 /* EVEX instructions shouldn't need the REX prefix. */
3269 i.vrex &= ~vrex_used;
3270 gas_assert (i.vrex == 0);
3271
3272 /* Check the REX.W bit. */
3273 w = (i.rex & REX_W) ? 1 : 0;
3274 if (i.tm.opcode_modifier.vexw)
3275 {
3276 if (i.tm.opcode_modifier.vexw == VEXW1)
3277 w = 1;
3278 }
3279 /* If w is not set it means we are dealing with WIG instruction. */
3280 else if (!w)
3281 {
3282 if (evexwig == evexw1)
3283 w = 1;
3284 }
3285
3286 /* Encode the U bit. */
3287 implied_prefix |= 0x4;
3288
3289 /* The third byte of the EVEX prefix. */
3290 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3291
3292 /* The fourth byte of the EVEX prefix. */
3293 /* The zeroing-masking bit. */
3294 if (i.mask && i.mask->zeroing)
3295 i.vex.bytes[3] |= 0x80;
3296
3297 /* Don't always set the broadcast bit if there is no RC. */
3298 if (!i.rounding)
3299 {
3300 /* Encode the vector length. */
3301 unsigned int vec_length;
3302
3303 switch (i.tm.opcode_modifier.evex)
3304 {
3305 case EVEXLIG: /* LL' is ignored */
3306 vec_length = evexlig << 5;
3307 break;
3308 case EVEX128:
3309 vec_length = 0 << 5;
3310 break;
3311 case EVEX256:
3312 vec_length = 1 << 5;
3313 break;
3314 case EVEX512:
3315 vec_length = 2 << 5;
3316 break;
3317 default:
3318 abort ();
3319 break;
3320 }
3321 i.vex.bytes[3] |= vec_length;
3322 /* Encode the broadcast bit. */
3323 if (i.broadcast)
3324 i.vex.bytes[3] |= 0x10;
3325 }
3326 else
3327 {
3328 if (i.rounding->type != saeonly)
3329 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3330 else
3331 i.vex.bytes[3] |= 0x10;
3332 }
3333
3334 if (i.mask && i.mask->mask)
3335 i.vex.bytes[3] |= i.mask->mask->reg_num;
3336}
3337
65da13b5
L		 3338static void
3339process_immext (void)
3340{
3341 expressionS *exp;
3342
4c692bc7
JB		 3343 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3344 && i.operands > 0)
65da13b5 3345 {
4c692bc7
JB		 3346 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3347 with an opcode suffix which is coded in the same place as an
3348 8-bit immediate field would be.
3349 Here we check those operands and remove them afterwards. */
65da13b5
L		 3350 unsigned int x;
3351
3352 for (x = 0; x < i.operands; x++)
4c692bc7 3353 if (register_number (i.op[x].regs) != x)
65da13b5 3354 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3355 register_prefix, i.op[x].regs->reg_name, x + 1,
3356 i.tm.name);
3357
3358 i.operands = 0;
65da13b5
L		 3359 }
3360
c0f3af97 3361 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3362 which is coded in the same place as an 8-bit immediate field
3363 would be. Here we fake an 8-bit immediate operand from the
3364 opcode suffix stored in tm.extension_opcode.
3365
c1e679ec 3366 AVX instructions also use this encoding, for some of
c0f3af97 3367 3 argument instructions. */
65da13b5 3368
43234a1e 3369 gas_assert (i.imm_operands <= 1
7ab9ffdd 3370 && (i.operands <= 2
43234a1e
L		 3371 || ((i.tm.opcode_modifier.vex
3372 || i.tm.opcode_modifier.evex)
7ab9ffdd 3373 && i.operands <= 4)));
65da13b5
L		 3374
3375 exp = &im_expressions[i.imm_operands++];
3376 i.op[i.operands].imms = exp;
3377 i.types[i.operands] = imm8;
3378 i.operands++;
3379 exp->X_op = O_constant;
3380 exp->X_add_number = i.tm.extension_opcode;
3381 i.tm.extension_opcode = None;
3382}
3383
42164a71
L		 3384
3385static int
3386check_hle (void)
3387{
3388 switch (i.tm.opcode_modifier.hleprefixok)
3389 {
3390 default:
3391 abort ();
82c2def5 3392 case HLEPrefixNone:
165de32a
L		 3393 as_bad (_("invalid instruction `%s' after `%s'"),
3394 i.tm.name, i.hle_prefix);
42164a71 3395 return 0;
82c2def5 3396 case HLEPrefixLock:
42164a71
L		 3397 if (i.prefix[LOCK_PREFIX])
3398 return 1;
165de32a 3399 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3400 return 0;
82c2def5 3401 case HLEPrefixAny:
42164a71 3402 return 1;
82c2def5 3403 case HLEPrefixRelease:
42164a71
L		 3404 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3405 {
3406 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3407 i.tm.name);
3408 return 0;
3409 }
3410 if (i.mem_operands == 0
3411 || !operand_type_check (i.types[i.operands - 1], anymem))
3412 {
3413 as_bad (_("memory destination needed for instruction `%s'"
3414 " after `xrelease'"), i.tm.name);
3415 return 0;
3416 }
3417 return 1;
3418 }
3419}
3420
252b5132
RH		 3421/* This is the guts of the machine-dependent assembler. LINE points to a
3422 machine dependent instruction. This function is supposed to emit
3423 the frags/bytes it assembles to. */
3424
3425void
65da13b5 3426md_assemble (char *line)
252b5132 3427{
40fb9820 3428 unsigned int j;
252b5132 3429 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3430 const insn_template *t;
252b5132 3431
47926f60 3432 /* Initialize globals. */
252b5132
RH		 3433 memset (&i, '\0', sizeof (i));
3434 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3435 i.reloc[j] = NO_RELOC;
252b5132
RH		 3436 memset (disp_expressions, '\0', sizeof (disp_expressions));
3437 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3438 save_stack_p = save_stack;
252b5132
RH		 3439
3440 /* First parse an instruction mnemonic & call i386_operand for the operands.
3441 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3442 start of a (possibly prefixed) mnemonic. */
252b5132 3443
29b0f896
AM		 3444 line = parse_insn (line, mnemonic);
3445 if (line == NULL)
3446 return;
252b5132 3447
29b0f896 3448 line = parse_operands (line, mnemonic);
ee86248c 3449 this_operand = -1;
29b0f896
AM		 3450 if (line == NULL)
3451 return;
252b5132 3452
29b0f896
AM		 3453 /* Now we've parsed the mnemonic into a set of templates, and have the
3454 operands at hand. */
3455
3456 /* All intel opcodes have reversed operands except for "bound" and
3457 "enter". We also don't reverse intersegment "jmp" and "call"
3458 instructions with 2 immediate operands so that the immediate segment
050dfa73 3459 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3460 if (intel_syntax
3461 && i.operands > 1
29b0f896 3462 && (strcmp (mnemonic, "bound") != 0)
30123838 3463 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3464 && !(operand_type_check (i.types[0], imm)
3465 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3466 swap_operands ();
3467
ec56d5c0
JB		 3468 /* The order of the immediates should be reversed
3469 for 2 immediates extrq and insertq instructions */
3470 if (i.imm_operands == 2
3471 && (strcmp (mnemonic, "extrq") == 0
3472 || strcmp (mnemonic, "insertq") == 0))
3473 swap_2_operands (0, 1);
3474
29b0f896
AM		 3475 if (i.imm_operands)
3476 optimize_imm ();
3477
b300c311
L		 3478 /* Don't optimize displacement for movabs since it only takes 64bit
3479 displacement. */
3480 if (i.disp_operands
a501d77e 3481 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3482 && (flag_code != CODE_64BIT
3483 || strcmp (mnemonic, "movabs") != 0))
3484 optimize_disp ();
29b0f896
AM		 3485
3486 /* Next, we find a template that matches the given insn,
3487 making sure the overlap of the given operands types is consistent
3488 with the template operand types. */
252b5132 3489
fa99fab2 3490 if (!(t = match_template ()))
29b0f896 3491 return;
252b5132 3492
7bab8ab5 3493 if (sse_check != check_none
81f8a913 3494 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3495 && (i.tm.cpu_flags.bitfield.cpusse
3496 || i.tm.cpu_flags.bitfield.cpusse2
3497 || i.tm.cpu_flags.bitfield.cpusse3
3498 || i.tm.cpu_flags.bitfield.cpussse3
3499 || i.tm.cpu_flags.bitfield.cpusse4_1
3500 || i.tm.cpu_flags.bitfield.cpusse4_2))
3501 {
7bab8ab5 3502 (sse_check == check_warning
daf50ae7
L		 3503 ? as_warn
3504 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3505 }
3506
321fd21e
L		 3507 /* Zap movzx and movsx suffix. The suffix has been set from
3508 "word ptr" or "byte ptr" on the source operand in Intel syntax
3509 or extracted from mnemonic in AT&T syntax. But we'll use
3510 the destination register to choose the suffix for encoding. */
3511 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3512 {
321fd21e
L		 3513 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3514 there is no suffix, the default will be byte extension. */
3515 if (i.reg_operands != 2
3516 && !i.suffix
7ab9ffdd 3517 && intel_syntax)
321fd21e
L		 3518 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3519
3520 i.suffix = 0;
cd61ebfe 3521 }
24eab124 3522
40fb9820 3523 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3524 if (!add_prefix (FWAIT_OPCODE))
3525 return;
252b5132 3526
d5de92cf
L		 3527 /* Check if REP prefix is OK. */
3528 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3529 {
3530 as_bad (_("invalid instruction `%s' after `%s'"),
3531 i.tm.name, i.rep_prefix);
3532 return;
3533 }
3534
c1ba0266
L		 3535 /* Check for lock without a lockable instruction. Destination operand
3536 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3537 if (i.prefix[LOCK_PREFIX]
3538 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3539 || i.mem_operands == 0
3540 || (i.tm.base_opcode != 0x86
3541 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3542 {
3543 as_bad (_("expecting lockable instruction after `lock'"));
3544 return;
3545 }
3546
42164a71 3547 /* Check if HLE prefix is OK. */
165de32a 3548 if (i.hle_prefix && !check_hle ())
42164a71
L		 3549 return;
3550
7e8b059b
L		 3551 /* Check BND prefix. */
3552 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3553 as_bad (_("expecting valid branch instruction after `bnd'"));
3554
3555 if (i.tm.cpu_flags.bitfield.cpumpx
3556 && flag_code == CODE_64BIT
3557 && i.prefix[ADDR_PREFIX])
3558 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3559
3560 /* Insert BND prefix. */
3561 if (add_bnd_prefix
3562 && i.tm.opcode_modifier.bndprefixok
3563 && !i.prefix[BND_PREFIX])
3564 add_prefix (BND_PREFIX_OPCODE);
3565
29b0f896 3566 /* Check string instruction segment overrides. */
40fb9820 3567 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3568 {
3569 if (!check_string ())
5dd0794d 3570 return;
fc0763e6 3571 i.disp_operands = 0;
29b0f896 3572 }
5dd0794d 3573
29b0f896
AM		 3574 if (!process_suffix ())
3575 return;
e413e4e9 3576
bc0844ae
L		 3577 /* Update operand types. */
3578 for (j = 0; j < i.operands; j++)
3579 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3580
29b0f896
AM		 3581 /* Make still unresolved immediate matches conform to size of immediate
3582 given in i.suffix. */
3583 if (!finalize_imm ())
3584 return;
252b5132 3585
40fb9820 3586 if (i.types[0].bitfield.imm1)
29b0f896 3587 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3588
9afe6eb8
L		 3589 /* We only need to check those implicit registers for instructions
3590 with 3 operands or less. */
3591 if (i.operands <= 3)
3592 for (j = 0; j < i.operands; j++)
3593 if (i.types[j].bitfield.inoutportreg
3594 || i.types[j].bitfield.shiftcount
3595 || i.types[j].bitfield.acc
3596 || i.types[j].bitfield.floatacc)
3597 i.reg_operands--;
40fb9820 3598
c0f3af97
L		 3599 /* ImmExt should be processed after SSE2AVX. */
3600 if (!i.tm.opcode_modifier.sse2avx
3601 && i.tm.opcode_modifier.immext)
65da13b5 3602 process_immext ();
252b5132 3603
29b0f896
AM		 3604 /* For insns with operands there are more diddles to do to the opcode. */
3605 if (i.operands)
3606 {
3607 if (!process_operands ())
3608 return;
3609 }
40fb9820 3610 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3611 {
3612 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3613 as_warn (_("translating to `%sp'"), i.tm.name);
3614 }
252b5132 3615
c0f3af97 3616 if (i.tm.opcode_modifier.vex)
fa99fab2 3617 build_vex_prefix (t);
c0f3af97 3618
43234a1e
L		 3619 if (i.tm.opcode_modifier.evex)
3620 build_evex_prefix ();
3621
5dd85c99
SP		 3622 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3623 instructions may define INT_OPCODE as well, so avoid this corner
3624 case for those instructions that use MODRM. */
3625 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3626 && !i.tm.opcode_modifier.modrm
3627 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3628 {
3629 i.tm.base_opcode = INT3_OPCODE;
3630 i.imm_operands = 0;
3631 }
252b5132 3632
40fb9820
L		 3633 if ((i.tm.opcode_modifier.jump
3634 || i.tm.opcode_modifier.jumpbyte
3635 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3636 && i.op[0].disps->X_op == O_constant)
3637 {
3638 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3639 the absolute address given by the constant. Since ix86 jumps and
3640 calls are pc relative, we need to generate a reloc. */
3641 i.op[0].disps->X_add_symbol = &abs_symbol;
3642 i.op[0].disps->X_op = O_symbol;
3643 }
252b5132 3644
40fb9820 3645 if (i.tm.opcode_modifier.rex64)
161a04f6 3646 i.rex |= REX_W;
252b5132 3647
29b0f896
AM		 3648 /* For 8 bit registers we need an empty rex prefix. Also if the
3649 instruction already has a prefix, we need to convert old
3650 registers to new ones. */
773f551c 3651
40fb9820 3652 if ((i.types[0].bitfield.reg8
29b0f896 3653 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3654 || (i.types[1].bitfield.reg8
29b0f896 3655 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3656 || ((i.types[0].bitfield.reg8
3657 || i.types[1].bitfield.reg8)
29b0f896
AM		 3658 && i.rex != 0))
3659 {
3660 int x;
726c5dcd 3661
29b0f896
AM		 3662 i.rex |= REX_OPCODE;
3663 for (x = 0; x < 2; x++)
3664 {
3665 /* Look for 8 bit operand that uses old registers. */
40fb9820 3666 if (i.types[x].bitfield.reg8
29b0f896 3667 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3668 {
29b0f896
AM		 3669 /* In case it is "hi" register, give up. */
3670 if (i.op[x].regs->reg_num > 3)
a540244d 3671 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3672 "instruction requiring REX prefix."),
a540244d 3673 register_prefix, i.op[x].regs->reg_name);
773f551c 3674
29b0f896
AM		 3675 /* Otherwise it is equivalent to the extended register.
3676 Since the encoding doesn't change this is merely
3677 cosmetic cleanup for debug output. */
3678
3679 i.op[x].regs = i.op[x].regs + 8;
773f551c 3680 }
29b0f896
AM		 3681 }
3682 }
773f551c 3683
7ab9ffdd 3684 if (i.rex != 0)
29b0f896
AM		 3685 add_prefix (REX_OPCODE | i.rex);
3686
3687 /* We are ready to output the insn. */
3688 output_insn ();
3689}
3690
3691static char *
e3bb37b5 3692parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3693{
3694 char *l = line;
3695 char *token_start = l;
3696 char *mnem_p;
5c6af06e 3697 int supported;
d3ce72d0 3698 const insn_template *t;
b6169b20 3699 char *dot_p = NULL;
29b0f896 3700
29b0f896
AM		 3701 while (1)
3702 {
3703 mnem_p = mnemonic;
3704 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3705 {
b6169b20
L		 3706 if (*mnem_p == '.')
3707 dot_p = mnem_p;
29b0f896
AM		 3708 mnem_p++;
3709 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3710 {
29b0f896
AM		 3711 as_bad (_("no such instruction: `%s'"), token_start);
3712 return NULL;
3713 }
3714 l++;
3715 }
3716 if (!is_space_char (*l)
3717 && *l != END_OF_INSN
e44823cf
JB		 3718 && (intel_syntax
3719 || (*l != PREFIX_SEPARATOR
3720 && *l != ',')))
29b0f896
AM		 3721 {
3722 as_bad (_("invalid character %s in mnemonic"),
3723 output_invalid (*l));
3724 return NULL;
3725 }
3726 if (token_start == l)
3727 {
e44823cf 3728 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3729 as_bad (_("expecting prefix; got nothing"));
3730 else
3731 as_bad (_("expecting mnemonic; got nothing"));
3732 return NULL;
3733 }
45288df1 3734
29b0f896 3735 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3736 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3737
29b0f896
AM		 3738 if (*l != END_OF_INSN
3739 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3740 && current_templates
40fb9820 3741 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3742 {
c6fb90c8 3743 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3744 {
3745 as_bad ((flag_code != CODE_64BIT
3746 ? _("`%s' is only supported in 64-bit mode")
3747 : _("`%s' is not supported in 64-bit mode")),
3748 current_templates->start->name);
3749 return NULL;
3750 }
29b0f896
AM		 3751 /* If we are in 16-bit mode, do not allow addr16 or data16.
3752 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3753 if ((current_templates->start->opcode_modifier.size16
3754 || current_templates->start->opcode_modifier.size32)
29b0f896 3755 && flag_code != CODE_64BIT
40fb9820 3756 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3757 ^ (flag_code == CODE_16BIT)))
3758 {
3759 as_bad (_("redundant %s prefix"),
3760 current_templates->start->name);
3761 return NULL;
45288df1 3762 }
29b0f896
AM		 3763 /* Add prefix, checking for repeated prefixes. */
3764 switch (add_prefix (current_templates->start->base_opcode))
3765 {
c32fa91d 3766 case PREFIX_EXIST:
29b0f896 3767 return NULL;
c32fa91d 3768 case PREFIX_REP:
42164a71 3769 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3770 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3771 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3772 i.bnd_prefix = current_templates->start->name;
42164a71 3773 else
d5de92cf 3774 i.rep_prefix = current_templates->start->name;
29b0f896 3775 break;
c32fa91d
L		 3776 default:
3777 break;
29b0f896
AM		 3778 }
3779 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3780 token_start = ++l;
3781 }
3782 else
3783 break;
3784 }
45288df1 3785
30a55f88 3786 if (!current_templates)
b6169b20 3787 {
f8a5c266
L		 3788 /* Check if we should swap operand or force 32bit displacement in
3789 encoding. */
30a55f88
L		 3790 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3791 i.swap_operand = 1;
8d63c93e 3792 else if (mnem_p - 3 == dot_p
a501d77e
L		 3793 && dot_p[1] == 'd'
3794 && dot_p[2] == '8')
3795 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3796 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3797 && dot_p[1] == 'd'
3798 && dot_p[2] == '3'
3799 && dot_p[3] == '2')
a501d77e 3800 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3801 else
3802 goto check_suffix;
3803 mnem_p = dot_p;
3804 *dot_p = '\0';
d3ce72d0 3805 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3806 }
3807
29b0f896
AM		 3808 if (!current_templates)
3809 {
b6169b20 3810check_suffix:
29b0f896
AM		 3811 /* See if we can get a match by trimming off a suffix. */
3812 switch (mnem_p[-1])
3813 {
3814 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3815 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3816 i.suffix = SHORT_MNEM_SUFFIX;
3817 else
29b0f896
AM		 3818 case BYTE_MNEM_SUFFIX:
3819 case QWORD_MNEM_SUFFIX:
3820 i.suffix = mnem_p[-1];
3821 mnem_p[-1] = '\0';
d3ce72d0
NC		 3822 current_templates = (const templates *) hash_find (op_hash,
3823 mnemonic);
29b0f896
AM		 3824 break;
3825 case SHORT_MNEM_SUFFIX:
3826 case LONG_MNEM_SUFFIX:
3827 if (!intel_syntax)
3828 {
3829 i.suffix = mnem_p[-1];
3830 mnem_p[-1] = '\0';
d3ce72d0
NC		 3831 current_templates = (const templates *) hash_find (op_hash,
3832 mnemonic);
29b0f896
AM		 3833 }
3834 break;
252b5132 3835
29b0f896
AM		 3836 /* Intel Syntax. */
3837 case 'd':
3838 if (intel_syntax)
3839 {
9306ca4a 3840 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3841 i.suffix = SHORT_MNEM_SUFFIX;
3842 else
3843 i.suffix = LONG_MNEM_SUFFIX;
3844 mnem_p[-1] = '\0';
d3ce72d0
NC		 3845 current_templates = (const templates *) hash_find (op_hash,
3846 mnemonic);
29b0f896
AM		 3847 }
3848 break;
3849 }
3850 if (!current_templates)
3851 {
3852 as_bad (_("no such instruction: `%s'"), token_start);
3853 return NULL;
3854 }
3855 }
252b5132 3856
40fb9820
L		 3857 if (current_templates->start->opcode_modifier.jump
3858 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3859 {
3860 /* Check for a branch hint. We allow ",pt" and ",pn" for
3861 predict taken and predict not taken respectively.
3862 I'm not sure that branch hints actually do anything on loop
3863 and jcxz insns (JumpByte) for current Pentium4 chips. They
3864 may work in the future and it doesn't hurt to accept them
3865 now. */
3866 if (l[0] == ',' && l[1] == 'p')
3867 {
3868 if (l[2] == 't')
3869 {
3870 if (!add_prefix (DS_PREFIX_OPCODE))
3871 return NULL;
3872 l += 3;
3873 }
3874 else if (l[2] == 'n')
3875 {
3876 if (!add_prefix (CS_PREFIX_OPCODE))
3877 return NULL;
3878 l += 3;
3879 }
3880 }
3881 }
3882 /* Any other comma loses. */
3883 if (*l == ',')
3884 {
3885 as_bad (_("invalid character %s in mnemonic"),
3886 output_invalid (*l));
3887 return NULL;
3888 }
252b5132 3889
29b0f896 3890 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3891 supported = 0;
3892 for (t = current_templates->start; t < current_templates->end; ++t)
3893 {
c0f3af97
L		 3894 supported |= cpu_flags_match (t);
3895 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3896 goto skip;
5c6af06e 3897 }
3629bb00 3898
c0f3af97 3899 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3900 {
3901 as_bad (flag_code == CODE_64BIT
3902 ? _("`%s' is not supported in 64-bit mode")
3903 : _("`%s' is only supported in 64-bit mode"),
3904 current_templates->start->name);
3905 return NULL;
3906 }
c0f3af97 3907 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3908 {
3629bb00 3909 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3910 current_templates->start->name,
41aacd83 3911 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3912 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3913 return NULL;
29b0f896 3914 }
3629bb00
L		 3915
3916skip:
3917 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3918 && (flag_code != CODE_16BIT))
29b0f896
AM		 3919 {
3920 as_warn (_("use .code16 to ensure correct addressing mode"));
3921 }
252b5132 3922
29b0f896
AM		 3923 return l;
3924}
252b5132 3925
29b0f896 3926static char *
e3bb37b5 3927parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3928{
3929 char *token_start;
3138f287 3930
29b0f896
AM		 3931 /* 1 if operand is pending after ','. */
3932 unsigned int expecting_operand = 0;
252b5132 3933
29b0f896
AM		 3934 /* Non-zero if operand parens not balanced. */
3935 unsigned int paren_not_balanced;
3936
3937 while (*l != END_OF_INSN)
3938 {
3939 /* Skip optional white space before operand. */
3940 if (is_space_char (*l))
3941 ++l;
3942 if (!is_operand_char (*l) && *l != END_OF_INSN)
3943 {
3944 as_bad (_("invalid character %s before operand %d"),
3945 output_invalid (*l),
3946 i.operands + 1);
3947 return NULL;
3948 }
3949 token_start = l; /* after white space */
3950 paren_not_balanced = 0;
3951 while (paren_not_balanced || *l != ',')
3952 {
3953 if (*l == END_OF_INSN)
3954 {
3955 if (paren_not_balanced)
3956 {
3957 if (!intel_syntax)
3958 as_bad (_("unbalanced parenthesis in operand %d."),
3959 i.operands + 1);
3960 else
3961 as_bad (_("unbalanced brackets in operand %d."),
3962 i.operands + 1);
3963 return NULL;
3964 }
3965 else
3966 break; /* we are done */
3967 }
3968 else if (!is_operand_char (*l) && !is_space_char (*l))
3969 {
3970 as_bad (_("invalid character %s in operand %d"),
3971 output_invalid (*l),
3972 i.operands + 1);
3973 return NULL;
3974 }
3975 if (!intel_syntax)
3976 {
3977 if (*l == '(')
3978 ++paren_not_balanced;
3979 if (*l == ')')
3980 --paren_not_balanced;
3981 }
3982 else
3983 {
3984 if (*l == '[')
3985 ++paren_not_balanced;
3986 if (*l == ']')
3987 --paren_not_balanced;
3988 }
3989 l++;
3990 }
3991 if (l != token_start)
3992 { /* Yes, we've read in another operand. */
3993 unsigned int operand_ok;
3994 this_operand = i.operands++;
7d5e4556 3995 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3996 if (i.operands > MAX_OPERANDS)
3997 {
3998 as_bad (_("spurious operands; (%d operands/instruction max)"),
3999 MAX_OPERANDS);
4000 return NULL;
4001 }
4002 /* Now parse operand adding info to 'i' as we go along. */
4003 END_STRING_AND_SAVE (l);
4004
4005 if (intel_syntax)
4006 operand_ok =
4007 i386_intel_operand (token_start,
4008 intel_float_operand (mnemonic));
4009 else
a7619375 4010 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4011
4012 RESTORE_END_STRING (l);
4013 if (!operand_ok)
4014 return NULL;
4015 }
4016 else
4017 {
4018 if (expecting_operand)
4019 {
4020 expecting_operand_after_comma:
4021 as_bad (_("expecting operand after ','; got nothing"));
4022 return NULL;
4023 }
4024 if (*l == ',')
4025 {
4026 as_bad (_("expecting operand before ','; got nothing"));
4027 return NULL;
4028 }
4029 }
7f3f1ea2 4030
29b0f896
AM		 4031 /* Now *l must be either ',' or END_OF_INSN. */
4032 if (*l == ',')
4033 {
4034 if (*++l == END_OF_INSN)
4035 {
4036 /* Just skip it, if it's \n complain. */
4037 goto expecting_operand_after_comma;
4038 }
4039 expecting_operand = 1;
4040 }
4041 }
4042 return l;
4043}
7f3f1ea2 4044
050dfa73 4045static void
4d456e3d 4046swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4047{
4048 union i386_op temp_op;
40fb9820 4049 i386_operand_type temp_type;
050dfa73 4050 enum bfd_reloc_code_real temp_reloc;
4eed87de 4051
050dfa73
MM		 4052 temp_type = i.types[xchg2];
4053 i.types[xchg2] = i.types[xchg1];
4054 i.types[xchg1] = temp_type;
4055 temp_op = i.op[xchg2];
4056 i.op[xchg2] = i.op[xchg1];
4057 i.op[xchg1] = temp_op;
4058 temp_reloc = i.reloc[xchg2];
4059 i.reloc[xchg2] = i.reloc[xchg1];
4060 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4061
4062 if (i.mask)
4063 {
4064 if (i.mask->operand == xchg1)
4065 i.mask->operand = xchg2;
4066 else if (i.mask->operand == xchg2)
4067 i.mask->operand = xchg1;
4068 }
4069 if (i.broadcast)
4070 {
4071 if (i.broadcast->operand == xchg1)
4072 i.broadcast->operand = xchg2;
4073 else if (i.broadcast->operand == xchg2)
4074 i.broadcast->operand = xchg1;
4075 }
4076 if (i.rounding)
4077 {
4078 if (i.rounding->operand == xchg1)
4079 i.rounding->operand = xchg2;
4080 else if (i.rounding->operand == xchg2)
4081 i.rounding->operand = xchg1;
4082 }
050dfa73
MM		 4083}
4084
29b0f896 4085static void
e3bb37b5 4086swap_operands (void)
29b0f896 4087{
b7c61d9a 4088 switch (i.operands)
050dfa73 4089 {
c0f3af97 4090 case 5:
b7c61d9a 4091 case 4:
4d456e3d 4092 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4093 case 3:
4094 case 2:
4d456e3d 4095 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4096 break;
4097 default:
4098 abort ();
29b0f896 4099 }
29b0f896
AM		 4100
4101 if (i.mem_operands == 2)
4102 {
4103 const seg_entry *temp_seg;
4104 temp_seg = i.seg[0];
4105 i.seg[0] = i.seg[1];
4106 i.seg[1] = temp_seg;
4107 }
4108}
252b5132 4109
29b0f896
AM		 4110/* Try to ensure constant immediates are represented in the smallest
4111 opcode possible. */
4112static void
e3bb37b5 4113optimize_imm (void)
29b0f896
AM		 4114{
4115 char guess_suffix = 0;
4116 int op;
252b5132 4117
29b0f896
AM		 4118 if (i.suffix)
4119 guess_suffix = i.suffix;
4120 else if (i.reg_operands)
4121 {
4122 /* Figure out a suffix from the last register operand specified.
4123 We can't do this properly yet, ie. excluding InOutPortReg,
4124 but the following works for instructions with immediates.
4125 In any case, we can't set i.suffix yet. */
4126 for (op = i.operands; --op >= 0;)
40fb9820 4127 if (i.types[op].bitfield.reg8)
7ab9ffdd 4128 {
40fb9820
L		 4129 guess_suffix = BYTE_MNEM_SUFFIX;
4130 break;
4131 }
4132 else if (i.types[op].bitfield.reg16)
252b5132 4133 {
40fb9820
L		 4134 guess_suffix = WORD_MNEM_SUFFIX;
4135 break;
4136 }
4137 else if (i.types[op].bitfield.reg32)
4138 {
4139 guess_suffix = LONG_MNEM_SUFFIX;
4140 break;
4141 }
4142 else if (i.types[op].bitfield.reg64)
4143 {
4144 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4145 break;
252b5132 4146 }
29b0f896
AM		 4147 }
4148 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4149 guess_suffix = WORD_MNEM_SUFFIX;
4150
4151 for (op = i.operands; --op >= 0;)
40fb9820 4152 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4153 {
4154 switch (i.op[op].imms->X_op)
252b5132 4155 {
29b0f896
AM		 4156 case O_constant:
4157 /* If a suffix is given, this operand may be shortened. */
4158 switch (guess_suffix)
252b5132 4159 {
29b0f896 4160 case LONG_MNEM_SUFFIX:
40fb9820
L		 4161 i.types[op].bitfield.imm32 = 1;
4162 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4163 break;
4164 case WORD_MNEM_SUFFIX:
40fb9820
L		 4165 i.types[op].bitfield.imm16 = 1;
4166 i.types[op].bitfield.imm32 = 1;
4167 i.types[op].bitfield.imm32s = 1;
4168 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4169 break;
4170 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4171 i.types[op].bitfield.imm8 = 1;
4172 i.types[op].bitfield.imm8s = 1;
4173 i.types[op].bitfield.imm16 = 1;
4174 i.types[op].bitfield.imm32 = 1;
4175 i.types[op].bitfield.imm32s = 1;
4176 i.types[op].bitfield.imm64 = 1;
29b0f896 4177 break;
252b5132 4178 }
252b5132 4179
29b0f896
AM		 4180 /* If this operand is at most 16 bits, convert it
4181 to a signed 16 bit number before trying to see
4182 whether it will fit in an even smaller size.
4183 This allows a 16-bit operand such as $0xffe0 to
4184 be recognised as within Imm8S range. */
40fb9820 4185 if ((i.types[op].bitfield.imm16)
29b0f896 4186 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4187 {
29b0f896
AM		 4188 i.op[op].imms->X_add_number =
4189 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4190 }
40fb9820 4191 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4192 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4193 == 0))
4194 {
4195 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4196 ^ ((offsetT) 1 << 31))
4197 - ((offsetT) 1 << 31));
4198 }
40fb9820 4199 i.types[op]
c6fb90c8
L		 4200 = operand_type_or (i.types[op],
4201 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4202
29b0f896
AM		 4203 /* We must avoid matching of Imm32 templates when 64bit
4204 only immediate is available. */
4205 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4206 i.types[op].bitfield.imm32 = 0;
29b0f896 4207 break;
252b5132 4208
29b0f896
AM		 4209 case O_absent:
4210 case O_register:
4211 abort ();
4212
4213 /* Symbols and expressions. */
4214 default:
9cd96992
JB		 4215 /* Convert symbolic operand to proper sizes for matching, but don't
4216 prevent matching a set of insns that only supports sizes other
4217 than those matching the insn suffix. */
4218 {
40fb9820 4219 i386_operand_type mask, allowed;
d3ce72d0 4220 const insn_template *t;
9cd96992 4221
0dfbf9d7
L		 4222 operand_type_set (&mask, 0);
4223 operand_type_set (&allowed, 0);
40fb9820 4224
4eed87de
AM		 4225 for (t = current_templates->start;
4226 t < current_templates->end;
4227 ++t)
c6fb90c8
L		 4228 allowed = operand_type_or (allowed,
4229 t->operand_types[op]);
9cd96992
JB		 4230 switch (guess_suffix)
4231 {
4232 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4233 mask.bitfield.imm64 = 1;
4234 mask.bitfield.imm32s = 1;
9cd96992
JB		 4235 break;
4236 case LONG_MNEM_SUFFIX:
40fb9820 4237 mask.bitfield.imm32 = 1;
9cd96992
JB		 4238 break;
4239 case WORD_MNEM_SUFFIX:
40fb9820 4240 mask.bitfield.imm16 = 1;
9cd96992
JB		 4241 break;
4242 case BYTE_MNEM_SUFFIX:
40fb9820 4243 mask.bitfield.imm8 = 1;
9cd96992
JB		 4244 break;
4245 default:
9cd96992
JB		 4246 break;
4247 }
c6fb90c8 4248 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4249 if (!operand_type_all_zero (&allowed))
c6fb90c8 4250 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4251 }
29b0f896 4252 break;
252b5132 4253 }
29b0f896
AM		 4254 }
4255}
47926f60 4256
29b0f896
AM		 4257/* Try to use the smallest displacement type too. */
4258static void
e3bb37b5 4259optimize_disp (void)
29b0f896
AM		 4260{
4261 int op;
3e73aa7c 4262
29b0f896 4263 for (op = i.operands; --op >= 0;)
40fb9820 4264 if (operand_type_check (i.types[op], disp))
252b5132 4265 {
b300c311 4266 if (i.op[op].disps->X_op == O_constant)
252b5132 4267 {
91d6fa6a 4268 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4269
40fb9820 4270 if (i.types[op].bitfield.disp16
91d6fa6a 4271 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4272 {
4273 /* If this operand is at most 16 bits, convert
4274 to a signed 16 bit number and don't use 64bit
4275 displacement. */
91d6fa6a 4276 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4277 i.types[op].bitfield.disp64 = 0;
b300c311 4278 }
40fb9820 4279 if (i.types[op].bitfield.disp32
91d6fa6a 4280 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4281 {
4282 /* If this operand is at most 32 bits, convert
4283 to a signed 32 bit number and don't use 64bit
4284 displacement. */
91d6fa6a
NC		 4285 op_disp &= (((offsetT) 2 << 31) - 1);
4286 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4287 i.types[op].bitfield.disp64 = 0;
b300c311 4288 }
91d6fa6a 4289 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4290 {
40fb9820
L		 4291 i.types[op].bitfield.disp8 = 0;
4292 i.types[op].bitfield.disp16 = 0;
4293 i.types[op].bitfield.disp32 = 0;
4294 i.types[op].bitfield.disp32s = 0;
4295 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4296 i.op[op].disps = 0;
4297 i.disp_operands--;
4298 }
4299 else if (flag_code == CODE_64BIT)
4300 {
91d6fa6a 4301 if (fits_in_signed_long (op_disp))
28a9d8f5 4302 {
40fb9820
L		 4303 i.types[op].bitfield.disp64 = 0;
4304 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4305 }
0e1147d9 4306 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4307 && fits_in_unsigned_long (op_disp))
40fb9820 4308 i.types[op].bitfield.disp32 = 1;
b300c311 4309 }
40fb9820
L		 4310 if ((i.types[op].bitfield.disp32
4311 || i.types[op].bitfield.disp32s
4312 || i.types[op].bitfield.disp16)
91d6fa6a 4313 && fits_in_signed_byte (op_disp))
40fb9820 4314 i.types[op].bitfield.disp8 = 1;
252b5132 4315 }
67a4f2b7
AO		 4316 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4317 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4318 {
4319 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4320 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4321 i.types[op].bitfield.disp8 = 0;
4322 i.types[op].bitfield.disp16 = 0;
4323 i.types[op].bitfield.disp32 = 0;
4324 i.types[op].bitfield.disp32s = 0;
4325 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4326 }
4327 else
b300c311 4328 /* We only support 64bit displacement on constants. */
40fb9820 4329 i.types[op].bitfield.disp64 = 0;
252b5132 4330 }
29b0f896
AM		 4331}
4332
6c30d220
L		 4333/* Check if operands are valid for the instruction. */
4334
4335static int
4336check_VecOperands (const insn_template *t)
4337{
43234a1e
L		 4338 unsigned int op;
4339
6c30d220
L		 4340 /* Without VSIB byte, we can't have a vector register for index. */
4341 if (!t->opcode_modifier.vecsib
4342 && i.index_reg
4343 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4344 || i.index_reg->reg_type.bitfield.regymm
4345 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4346 {
4347 i.error = unsupported_vector_index_register;
4348 return 1;
4349 }
4350
ad8ecc81
MZ		 4351 /* Check if default mask is allowed. */
4352 if (t->opcode_modifier.nodefmask
4353 && (!i.mask || i.mask->mask->reg_num == 0))
4354 {
4355 i.error = no_default_mask;
4356 return 1;
4357 }
4358
7bab8ab5
JB		 4359 /* For VSIB byte, we need a vector register for index, and all vector
4360 registers must be distinct. */
4361 if (t->opcode_modifier.vecsib)
4362 {
4363 if (!i.index_reg
6c30d220
L		 4364 || !((t->opcode_modifier.vecsib == VecSIB128
4365 && i.index_reg->reg_type.bitfield.regxmm)
4366 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4367 && i.index_reg->reg_type.bitfield.regymm)
4368 || (t->opcode_modifier.vecsib == VecSIB512
4369 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4370 {
4371 i.error = invalid_vsib_address;
4372 return 1;
4373 }
4374
43234a1e
L		 4375 gas_assert (i.reg_operands == 2 || i.mask);
4376 if (i.reg_operands == 2 && !i.mask)
4377 {
4378 gas_assert (i.types[0].bitfield.regxmm
4379 || i.types[0].bitfield.regymm
4380 || i.types[0].bitfield.regzmm);
4381 gas_assert (i.types[2].bitfield.regxmm
4382 || i.types[2].bitfield.regymm
4383 || i.types[2].bitfield.regzmm);
4384 if (operand_check == check_none)
4385 return 0;
4386 if (register_number (i.op[0].regs)
4387 != register_number (i.index_reg)
4388 && register_number (i.op[2].regs)
4389 != register_number (i.index_reg)
4390 && register_number (i.op[0].regs)
4391 != register_number (i.op[2].regs))
4392 return 0;
4393 if (operand_check == check_error)
4394 {
4395 i.error = invalid_vector_register_set;
4396 return 1;
4397 }
4398 as_warn (_("mask, index, and destination registers should be distinct"));
4399 }
4400 }
7bab8ab5 4401
43234a1e
L		 4402 /* Check if broadcast is supported by the instruction and is applied
4403 to the memory operand. */
4404 if (i.broadcast)
4405 {
4406 int broadcasted_opnd_size;
4407
4408 /* Check if specified broadcast is supported in this instruction,
4409 and it's applied to memory operand of DWORD or QWORD type,
4410 depending on VecESize. */
4411 if (i.broadcast->type != t->opcode_modifier.broadcast
4412 || !i.types[i.broadcast->operand].bitfield.mem
4413 || (t->opcode_modifier.vecesize == 0
4414 && !i.types[i.broadcast->operand].bitfield.dword
4415 && !i.types[i.broadcast->operand].bitfield.unspecified)
4416 || (t->opcode_modifier.vecesize == 1
4417 && !i.types[i.broadcast->operand].bitfield.qword
4418 && !i.types[i.broadcast->operand].bitfield.unspecified))
4419 goto bad_broadcast;
4420
4421 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4422 if (i.broadcast->type == BROADCAST_1TO16)
4423 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4424 else if (i.broadcast->type == BROADCAST_1TO8)
4425 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4426 else
4427 goto bad_broadcast;
4428
4429 if ((broadcasted_opnd_size == 256
4430 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4431 || (broadcasted_opnd_size == 512
4432 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4433 {
4434 bad_broadcast:
4435 i.error = unsupported_broadcast;
4436 return 1;
4437 }
4438 }
4439 /* If broadcast is supported in this instruction, we need to check if
4440 operand of one-element size isn't specified without broadcast. */
4441 else if (t->opcode_modifier.broadcast && i.mem_operands)
4442 {
4443 /* Find memory operand. */
4444 for (op = 0; op < i.operands; op++)
4445 if (operand_type_check (i.types[op], anymem))
4446 break;
4447 gas_assert (op < i.operands);
4448 /* Check size of the memory operand. */
4449 if ((t->opcode_modifier.vecesize == 0
4450 && i.types[op].bitfield.dword)
4451 || (t->opcode_modifier.vecesize == 1
4452 && i.types[op].bitfield.qword))
4453 {
4454 i.error = broadcast_needed;
4455 return 1;
4456 }
4457 }
4458
4459 /* Check if requested masking is supported. */
4460 if (i.mask
4461 && (!t->opcode_modifier.masking
4462 || (i.mask->zeroing
4463 && t->opcode_modifier.masking == MERGING_MASKING)))
4464 {
4465 i.error = unsupported_masking;
4466 return 1;
4467 }
4468
4469 /* Check if masking is applied to dest operand. */
4470 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4471 {
4472 i.error = mask_not_on_destination;
4473 return 1;
4474 }
4475
43234a1e
L		 4476 /* Check RC/SAE. */
4477 if (i.rounding)
4478 {
4479 if ((i.rounding->type != saeonly
4480 && !t->opcode_modifier.staticrounding)
4481 || (i.rounding->type == saeonly
4482 && (t->opcode_modifier.staticrounding
4483 || !t->opcode_modifier.sae)))
4484 {
4485 i.error = unsupported_rc_sae;
4486 return 1;
4487 }
4488 /* If the instruction has several immediate operands and one of
4489 them is rounding, the rounding operand should be the last
4490 immediate operand. */
4491 if (i.imm_operands > 1
4492 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4493 {
43234a1e 4494 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4495 return 1;
4496 }
6c30d220
L		 4497 }
4498
43234a1e
L		 4499 /* Check vector Disp8 operand. */
4500 if (t->opcode_modifier.disp8memshift)
4501 {
4502 if (i.broadcast)
4503 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4504 else
4505 i.memshift = t->opcode_modifier.disp8memshift;
4506
4507 for (op = 0; op < i.operands; op++)
4508 if (operand_type_check (i.types[op], disp)
4509 && i.op[op].disps->X_op == O_constant)
4510 {
4511 offsetT value = i.op[op].disps->X_add_number;
4512 int vec_disp8_ok = fits_in_vec_disp8 (value);
4513 if (t->operand_types [op].bitfield.vec_disp8)
4514 {
4515 if (vec_disp8_ok)
4516 i.types[op].bitfield.vec_disp8 = 1;
4517 else
4518 {
4519 /* Vector insn can only have Vec_Disp8/Disp32 in
4520 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4521 mode. */
4522 i.types[op].bitfield.disp8 = 0;
4523 if (flag_code != CODE_16BIT)
4524 i.types[op].bitfield.disp16 = 0;
4525 }
4526 }
4527 else if (flag_code != CODE_16BIT)
4528 {
4529 /* One form of this instruction supports vector Disp8.
4530 Try vector Disp8 if we need to use Disp32. */
4531 if (vec_disp8_ok && !fits_in_signed_byte (value))
4532 {
4533 i.error = try_vector_disp8;
4534 return 1;
4535 }
4536 }
4537 }
4538 }
4539 else
4540 i.memshift = -1;
4541
6c30d220
L		 4542 return 0;
4543}
4544
43f3e2ee 4545/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4546 operand types. */
4547
4548static int
4549VEX_check_operands (const insn_template *t)
4550{
43234a1e
L		 4551 /* VREX is only valid with EVEX prefix. */
4552 if (i.need_vrex && !t->opcode_modifier.evex)
4553 {
4554 i.error = invalid_register_operand;
4555 return 1;
4556 }
4557
a683cc34
SP		 4558 if (!t->opcode_modifier.vex)
4559 return 0;
4560
4561 /* Only check VEX_Imm4, which must be the first operand. */
4562 if (t->operand_types[0].bitfield.vec_imm4)
4563 {
4564 if (i.op[0].imms->X_op != O_constant
4565 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4566 {
a65babc9 4567 i.error = bad_imm4;
891edac4
L		 4568 return 1;
4569 }
a683cc34
SP		 4570
4571 /* Turn off Imm8 so that update_imm won't complain. */
4572 i.types[0] = vec_imm4;
4573 }
4574
4575 return 0;
4576}
4577
d3ce72d0 4578static const insn_template *
e3bb37b5 4579match_template (void)
29b0f896
AM		 4580{
4581 /* Points to template once we've found it. */
d3ce72d0 4582 const insn_template *t;
40fb9820 4583 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4584 i386_operand_type overlap4;
29b0f896 4585 unsigned int found_reverse_match;
40fb9820
L		 4586 i386_opcode_modifier suffix_check;
4587 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4588 int addr_prefix_disp;
a5c311ca 4589 unsigned int j;
3629bb00 4590 unsigned int found_cpu_match;
45664ddb 4591 unsigned int check_register;
5614d22c 4592 enum i386_error specific_error = 0;
29b0f896 4593
c0f3af97
L		 4594#if MAX_OPERANDS != 5
4595# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4596#endif
4597
29b0f896 4598 found_reverse_match = 0;
539e75ad 4599 addr_prefix_disp = -1;
40fb9820
L		 4600
4601 memset (&suffix_check, 0, sizeof (suffix_check));
4602 if (i.suffix == BYTE_MNEM_SUFFIX)
4603 suffix_check.no_bsuf = 1;
4604 else if (i.suffix == WORD_MNEM_SUFFIX)
4605 suffix_check.no_wsuf = 1;
4606 else if (i.suffix == SHORT_MNEM_SUFFIX)
4607 suffix_check.no_ssuf = 1;
4608 else if (i.suffix == LONG_MNEM_SUFFIX)
4609 suffix_check.no_lsuf = 1;
4610 else if (i.suffix == QWORD_MNEM_SUFFIX)
4611 suffix_check.no_qsuf = 1;
4612 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4613 suffix_check.no_ldsuf = 1;
29b0f896 4614
01559ecc
L		 4615 /* Must have right number of operands. */
4616 i.error = number_of_operands_mismatch;
4617
45aa61fe 4618 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4619 {
539e75ad
L		 4620 addr_prefix_disp = -1;
4621
29b0f896
AM		 4622 if (i.operands != t->operands)
4623 continue;
4624
50aecf8c 4625 /* Check processor support. */
a65babc9 4626 i.error = unsupported;
c0f3af97
L		 4627 found_cpu_match = (cpu_flags_match (t)
4628 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4629 if (!found_cpu_match)
4630 continue;
4631
e1d4d893 4632 /* Check old gcc support. */
a65babc9 4633 i.error = old_gcc_only;
e1d4d893
L		 4634 if (!old_gcc && t->opcode_modifier.oldgcc)
4635 continue;
4636
4637 /* Check AT&T mnemonic. */
a65babc9 4638 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4639 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4640 continue;
4641
891edac4 4642 /* Check AT&T/Intel syntax. */
a65babc9 4643 i.error = unsupported_syntax;
5c07affc
L		 4644 if ((intel_syntax && t->opcode_modifier.attsyntax)
4645 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4646 continue;
4647
20592a94 4648 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4649 i.error = invalid_instruction_suffix;
567e4e96
L		 4650 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4651 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4652 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4653 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4654 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4655 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4656 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4657 continue;
4658
5c07affc 4659 if (!operand_size_match (t))
7d5e4556 4660 continue;
539e75ad 4661
5c07affc
L		 4662 for (j = 0; j < MAX_OPERANDS; j++)
4663 operand_types[j] = t->operand_types[j];
4664
45aa61fe
AM		 4665 /* In general, don't allow 64-bit operands in 32-bit mode. */
4666 if (i.suffix == QWORD_MNEM_SUFFIX
4667 && flag_code != CODE_64BIT
4668 && (intel_syntax
40fb9820 4669 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4670 && !intel_float_operand (t->name))
4671 : intel_float_operand (t->name) != 2)
40fb9820 4672 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4673 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4674 && !operand_types[0].bitfield.regymm
4675 && !operand_types[0].bitfield.regzmm)
40fb9820 4676 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97 4677 && !!operand_types[t->operands > 1].bitfield.regxmm
43234a1e
L		 4678 && !!operand_types[t->operands > 1].bitfield.regymm
4679 && !!operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4680 && (t->base_opcode != 0x0fc7
4681 || t->extension_opcode != 1 /* cmpxchg8b */))
4682 continue;
4683
192dc9c6
JB		 4684 /* In general, don't allow 32-bit operands on pre-386. */
4685 else if (i.suffix == LONG_MNEM_SUFFIX
4686 && !cpu_arch_flags.bitfield.cpui386
4687 && (intel_syntax
4688 ? (!t->opcode_modifier.ignoresize
4689 && !intel_float_operand (t->name))
4690 : intel_float_operand (t->name) != 2)
4691 && ((!operand_types[0].bitfield.regmmx
4692 && !operand_types[0].bitfield.regxmm)
4693 || (!operand_types[t->operands > 1].bitfield.regmmx
4694 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4695 continue;
4696
29b0f896 4697 /* Do not verify operands when there are none. */
50aecf8c 4698 else
29b0f896 4699 {
c6fb90c8 4700 if (!t->operands)
2dbab7d5
L		 4701 /* We've found a match; break out of loop. */
4702 break;
29b0f896 4703 }
252b5132 4704
539e75ad
L		 4705 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4706 into Disp32/Disp16/Disp32 operand. */
4707 if (i.prefix[ADDR_PREFIX] != 0)
4708 {
40fb9820 4709 /* There should be only one Disp operand. */
539e75ad
L		 4710 switch (flag_code)
4711 {
4712 case CODE_16BIT:
40fb9820
L		 4713 for (j = 0; j < MAX_OPERANDS; j++)
4714 {
4715 if (operand_types[j].bitfield.disp16)
4716 {
4717 addr_prefix_disp = j;
4718 operand_types[j].bitfield.disp32 = 1;
4719 operand_types[j].bitfield.disp16 = 0;
4720 break;
4721 }
4722 }
539e75ad
L		 4723 break;
4724 case CODE_32BIT:
40fb9820
L		 4725 for (j = 0; j < MAX_OPERANDS; j++)
4726 {
4727 if (operand_types[j].bitfield.disp32)
4728 {
4729 addr_prefix_disp = j;
4730 operand_types[j].bitfield.disp32 = 0;
4731 operand_types[j].bitfield.disp16 = 1;
4732 break;
4733 }
4734 }
539e75ad
L		 4735 break;
4736 case CODE_64BIT:
40fb9820
L		 4737 for (j = 0; j < MAX_OPERANDS; j++)
4738 {
4739 if (operand_types[j].bitfield.disp64)
4740 {
4741 addr_prefix_disp = j;
4742 operand_types[j].bitfield.disp64 = 0;
4743 operand_types[j].bitfield.disp32 = 1;
4744 break;
4745 }
4746 }
539e75ad
L		 4747 break;
4748 }
539e75ad
L		 4749 }
4750
56ffb741
L		 4751 /* We check register size if needed. */
4752 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4753 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4754 switch (t->operands)
4755 {
4756 case 1:
40fb9820 4757 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4758 continue;
4759 break;
4760 case 2:
8b38ad71
L		 4761 /* xchg %eax, %eax is a special case. It is an aliase for nop
4762 only in 32bit mode and we can use opcode 0x90. In 64bit
4763 mode, we can't use 0x90 for xchg %eax, %eax since it should
4764 zero-extend %eax to %rax. */
4765 if (flag_code == CODE_64BIT
4766 && t->base_opcode == 0x90
0dfbf9d7
L		 4767 && operand_type_equal (&i.types [0], &acc32)
4768 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4769 continue;
b6169b20
L		 4770 if (i.swap_operand)
4771 {
4772 /* If we swap operand in encoding, we either match
4773 the next one or reverse direction of operands. */
4774 if (t->opcode_modifier.s)
4775 continue;
4776 else if (t->opcode_modifier.d)
4777 goto check_reverse;
4778 }
4779
29b0f896 4780 case 3:
fa99fab2
L		 4781 /* If we swap operand in encoding, we match the next one. */
4782 if (i.swap_operand && t->opcode_modifier.s)
4783 continue;
f48ff2ae 4784 case 4:
c0f3af97 4785 case 5:
c6fb90c8 4786 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4787 if (!operand_type_match (overlap0, i.types[0])
4788 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4789 || (check_register
4790 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4791 operand_types[0],
4792 overlap1, i.types[1],
4793 operand_types[1])))
29b0f896
AM		 4794 {
4795 /* Check if other direction is valid ... */
40fb9820 4796 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4797 continue;
4798
b6169b20 4799check_reverse:
29b0f896 4800 /* Try reversing direction of operands. */
c6fb90c8
L		 4801 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4802 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4803 if (!operand_type_match (overlap0, i.types[0])
4804 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4805 || (check_register
4806 && !operand_type_register_match (overlap0,
4807 i.types[0],
4808 operand_types[1],
4809 overlap1,
4810 i.types[1],
4811 operand_types[0])))
29b0f896
AM		 4812 {
4813 /* Does not match either direction. */
4814 continue;
4815 }
4816 /* found_reverse_match holds which of D or FloatDR
4817 we've found. */
40fb9820 4818 if (t->opcode_modifier.d)
8a2ed489 4819 found_reverse_match = Opcode_D;
40fb9820 4820 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4821 found_reverse_match = Opcode_FloatD;
4822 else
4823 found_reverse_match = 0;
40fb9820 4824 if (t->opcode_modifier.floatr)
8a2ed489 4825 found_reverse_match |= Opcode_FloatR;
29b0f896 4826 }
f48ff2ae 4827 else
29b0f896 4828 {
f48ff2ae 4829 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4830 switch (t->operands)
4831 {
c0f3af97
L		 4832 case 5:
4833 overlap4 = operand_type_and (i.types[4],
4834 operand_types[4]);
d1cbb4db 4835 case 4:
c6fb90c8
L		 4836 overlap3 = operand_type_and (i.types[3],
4837 operand_types[3]);
d1cbb4db 4838 case 3:
c6fb90c8
L		 4839 overlap2 = operand_type_and (i.types[2],
4840 operand_types[2]);
d1cbb4db
L		 4841 break;
4842 }
29b0f896 4843
f48ff2ae
L		 4844 switch (t->operands)
4845 {
c0f3af97
L		 4846 case 5:
4847 if (!operand_type_match (overlap4, i.types[4])
4848 || !operand_type_register_match (overlap3,
4849 i.types[3],
4850 operand_types[3],
4851 overlap4,
4852 i.types[4],
4853 operand_types[4]))
4854 continue;
f48ff2ae 4855 case 4:
40fb9820 4856 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4857 || (check_register
4858 && !operand_type_register_match (overlap2,
4859 i.types[2],
4860 operand_types[2],
4861 overlap3,
4862 i.types[3],
4863 operand_types[3])))
f48ff2ae
L		 4864 continue;
4865 case 3:
4866 /* Here we make use of the fact that there are no
4867 reverse match 3 operand instructions, and all 3
4868 operand instructions only need to be checked for
4869 register consistency between operands 2 and 3. */
40fb9820 4870 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4871 || (check_register
4872 && !operand_type_register_match (overlap1,
4873 i.types[1],
4874 operand_types[1],
4875 overlap2,
4876 i.types[2],
4877 operand_types[2])))
f48ff2ae
L		 4878 continue;
4879 break;
4880 }
29b0f896 4881 }
f48ff2ae 4882 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4883 slip through to break. */
4884 }
3629bb00 4885 if (!found_cpu_match)
29b0f896
AM		 4886 {
4887 found_reverse_match = 0;
4888 continue;
4889 }
c0f3af97 4890
5614d22c
JB		 4891 /* Check if vector and VEX operands are valid. */
4892 if (check_VecOperands (t) || VEX_check_operands (t))
4893 {
4894 specific_error = i.error;
4895 continue;
4896 }
a683cc34 4897
29b0f896
AM		 4898 /* We've found a match; break out of loop. */
4899 break;
4900 }
4901
4902 if (t == current_templates->end)
4903 {
4904 /* We found no match. */
a65babc9 4905 const char *err_msg;
5614d22c 4906 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4907 {
4908 default:
4909 abort ();
86e026a4 4910 case operand_size_mismatch:
a65babc9
L		 4911 err_msg = _("operand size mismatch");
4912 break;
4913 case operand_type_mismatch:
4914 err_msg = _("operand type mismatch");
4915 break;
4916 case register_type_mismatch:
4917 err_msg = _("register type mismatch");
4918 break;
4919 case number_of_operands_mismatch:
4920 err_msg = _("number of operands mismatch");
4921 break;
4922 case invalid_instruction_suffix:
4923 err_msg = _("invalid instruction suffix");
4924 break;
4925 case bad_imm4:
4a2608e3 4926 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4927 break;
4928 case old_gcc_only:
4929 err_msg = _("only supported with old gcc");
4930 break;
4931 case unsupported_with_intel_mnemonic:
4932 err_msg = _("unsupported with Intel mnemonic");
4933 break;
4934 case unsupported_syntax:
4935 err_msg = _("unsupported syntax");
4936 break;
4937 case unsupported:
35262a23 4938 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4939 current_templates->start->name);
4940 return NULL;
6c30d220
L		 4941 case invalid_vsib_address:
4942 err_msg = _("invalid VSIB address");
4943 break;
7bab8ab5
JB		 4944 case invalid_vector_register_set:
4945 err_msg = _("mask, index, and destination registers must be distinct");
4946 break;
6c30d220
L		 4947 case unsupported_vector_index_register:
4948 err_msg = _("unsupported vector index register");
4949 break;
43234a1e
L		 4950 case unsupported_broadcast:
4951 err_msg = _("unsupported broadcast");
4952 break;
4953 case broadcast_not_on_src_operand:
4954 err_msg = _("broadcast not on source memory operand");
4955 break;
4956 case broadcast_needed:
4957 err_msg = _("broadcast is needed for operand of such type");
4958 break;
4959 case unsupported_masking:
4960 err_msg = _("unsupported masking");
4961 break;
4962 case mask_not_on_destination:
4963 err_msg = _("mask not on destination operand");
4964 break;
4965 case no_default_mask:
4966 err_msg = _("default mask isn't allowed");
4967 break;
4968 case unsupported_rc_sae:
4969 err_msg = _("unsupported static rounding/sae");
4970 break;
4971 case rc_sae_operand_not_last_imm:
4972 if (intel_syntax)
4973 err_msg = _("RC/SAE operand must precede immediate operands");
4974 else
4975 err_msg = _("RC/SAE operand must follow immediate operands");
4976 break;
4977 case invalid_register_operand:
4978 err_msg = _("invalid register operand");
4979 break;
a65babc9
L		 4980 }
4981 as_bad (_("%s for `%s'"), err_msg,
891edac4 4982 current_templates->start->name);
fa99fab2 4983 return NULL;
29b0f896 4984 }
252b5132 4985
29b0f896
AM		 4986 if (!quiet_warnings)
4987 {
4988 if (!intel_syntax
40fb9820
L		 4989 && (i.types[0].bitfield.jumpabsolute
4990 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4991 {
4992 as_warn (_("indirect %s without `*'"), t->name);
4993 }
4994
40fb9820
L		 4995 if (t->opcode_modifier.isprefix
4996 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4997 {
4998 /* Warn them that a data or address size prefix doesn't
4999 affect assembly of the next line of code. */
5000 as_warn (_("stand-alone `%s' prefix"), t->name);
5001 }
5002 }
5003
5004 /* Copy the template we found. */
5005 i.tm = *t;
539e75ad
L		 5006
5007 if (addr_prefix_disp != -1)
5008 i.tm.operand_types[addr_prefix_disp]
5009 = operand_types[addr_prefix_disp];
5010
29b0f896
AM		 5011 if (found_reverse_match)
5012 {
5013 /* If we found a reverse match we must alter the opcode
5014 direction bit. found_reverse_match holds bits to change
5015 (different for int & float insns). */
5016
5017 i.tm.base_opcode ^= found_reverse_match;
5018
539e75ad
L		 5019 i.tm.operand_types[0] = operand_types[1];
5020 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5021 }
5022
fa99fab2 5023 return t;
29b0f896
AM		 5024}
5025
5026static int
e3bb37b5 5027check_string (void)
29b0f896 5028{
40fb9820
L		 5029 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5030 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5031 {
5032 if (i.seg[0] != NULL && i.seg[0] != &es)
5033 {
a87af027 5034 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5035 i.tm.name,
a87af027
JB		 5036 mem_op + 1,
5037 register_prefix);
29b0f896
AM		 5038 return 0;
5039 }
5040 /* There's only ever one segment override allowed per instruction.
5041 This instruction possibly has a legal segment override on the
5042 second operand, so copy the segment to where non-string
5043 instructions store it, allowing common code. */
5044 i.seg[0] = i.seg[1];
5045 }
40fb9820 5046 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5047 {
5048 if (i.seg[1] != NULL && i.seg[1] != &es)
5049 {
a87af027 5050 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5051 i.tm.name,
a87af027
JB		 5052 mem_op + 2,
5053 register_prefix);
29b0f896
AM		 5054 return 0;
5055 }
5056 }
5057 return 1;
5058}
5059
5060static int
543613e9 5061process_suffix (void)
29b0f896
AM		 5062{
5063 /* If matched instruction specifies an explicit instruction mnemonic
5064 suffix, use it. */
40fb9820
L		 5065 if (i.tm.opcode_modifier.size16)
5066 i.suffix = WORD_MNEM_SUFFIX;
5067 else if (i.tm.opcode_modifier.size32)
5068 i.suffix = LONG_MNEM_SUFFIX;
5069 else if (i.tm.opcode_modifier.size64)
5070 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5071 else if (i.reg_operands)
5072 {
5073 /* If there's no instruction mnemonic suffix we try to invent one
5074 based on register operands. */
5075 if (!i.suffix)
5076 {
5077 /* We take i.suffix from the last register operand specified,
5078 Destination register type is more significant than source
381d071f
L		 5079 register type. crc32 in SSE4.2 prefers source register
5080 type. */
5081 if (i.tm.base_opcode == 0xf20f38f1)
5082 {
40fb9820
L		 5083 if (i.types[0].bitfield.reg16)
5084 i.suffix = WORD_MNEM_SUFFIX;
5085 else if (i.types[0].bitfield.reg32)
5086 i.suffix = LONG_MNEM_SUFFIX;
5087 else if (i.types[0].bitfield.reg64)
5088 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5089 }
9344ff29 5090 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5091 {
40fb9820 5092 if (i.types[0].bitfield.reg8)
20592a94
L		 5093 i.suffix = BYTE_MNEM_SUFFIX;
5094 }
381d071f
L		 5095
5096 if (!i.suffix)
5097 {
5098 int op;
5099
20592a94
L		 5100 if (i.tm.base_opcode == 0xf20f38f1
5101 || i.tm.base_opcode == 0xf20f38f0)
5102 {
5103 /* We have to know the operand size for crc32. */
5104 as_bad (_("ambiguous memory operand size for `%s`"),
5105 i.tm.name);
5106 return 0;
5107 }
5108
381d071f 5109 for (op = i.operands; --op >= 0;)
40fb9820 5110 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5111 {
40fb9820
L		 5112 if (i.types[op].bitfield.reg8)
5113 {
5114 i.suffix = BYTE_MNEM_SUFFIX;
5115 break;
5116 }
5117 else if (i.types[op].bitfield.reg16)
5118 {
5119 i.suffix = WORD_MNEM_SUFFIX;
5120 break;
5121 }
5122 else if (i.types[op].bitfield.reg32)
5123 {
5124 i.suffix = LONG_MNEM_SUFFIX;
5125 break;
5126 }
5127 else if (i.types[op].bitfield.reg64)
5128 {
5129 i.suffix = QWORD_MNEM_SUFFIX;
5130 break;
5131 }
381d071f
L		 5132 }
5133 }
29b0f896
AM		 5134 }
5135 else if (i.suffix == BYTE_MNEM_SUFFIX)
5136 {
2eb952a4
L		 5137 if (intel_syntax
5138 && i.tm.opcode_modifier.ignoresize
5139 && i.tm.opcode_modifier.no_bsuf)
5140 i.suffix = 0;
5141 else if (!check_byte_reg ())
29b0f896
AM		 5142 return 0;
5143 }
5144 else if (i.suffix == LONG_MNEM_SUFFIX)
5145 {
2eb952a4
L		 5146 if (intel_syntax
5147 && i.tm.opcode_modifier.ignoresize
5148 && i.tm.opcode_modifier.no_lsuf)
5149 i.suffix = 0;
5150 else if (!check_long_reg ())
29b0f896
AM		 5151 return 0;
5152 }
5153 else if (i.suffix == QWORD_MNEM_SUFFIX)
5154 {
955e1e6a
L		 5155 if (intel_syntax
5156 && i.tm.opcode_modifier.ignoresize
5157 && i.tm.opcode_modifier.no_qsuf)
5158 i.suffix = 0;
5159 else if (!check_qword_reg ())
29b0f896
AM		 5160 return 0;
5161 }
5162 else if (i.suffix == WORD_MNEM_SUFFIX)
5163 {
2eb952a4
L		 5164 if (intel_syntax
5165 && i.tm.opcode_modifier.ignoresize
5166 && i.tm.opcode_modifier.no_wsuf)
5167 i.suffix = 0;
5168 else if (!check_word_reg ())
29b0f896
AM		 5169 return 0;
5170 }
c0f3af97 5171 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5172 || i.suffix == YMMWORD_MNEM_SUFFIX
5173 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5174 {
43234a1e 5175 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5176 should check if it is a valid suffix. */
5177 }
40fb9820 5178 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5179 /* Do nothing if the instruction is going to ignore the prefix. */
5180 ;
5181 else
5182 abort ();
5183 }
40fb9820 5184 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5185 && !i.suffix
5186 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5187 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5188 {
5189 i.suffix = stackop_size;
5190 }
9306ca4a
JB		 5191 else if (intel_syntax
5192 && !i.suffix
40fb9820
L		 5193 && (i.tm.operand_types[0].bitfield.jumpabsolute
5194 || i.tm.opcode_modifier.jumpbyte
5195 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5196 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5197 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5198 {
5199 switch (flag_code)
5200 {
5201 case CODE_64BIT:
40fb9820 5202 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5203 {
5204 i.suffix = QWORD_MNEM_SUFFIX;
5205 break;
5206 }
5207 case CODE_32BIT:
40fb9820 5208 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5209 i.suffix = LONG_MNEM_SUFFIX;
5210 break;
5211 case CODE_16BIT:
40fb9820 5212 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5213 i.suffix = WORD_MNEM_SUFFIX;
5214 break;
5215 }
5216 }
252b5132 5217
9306ca4a 5218 if (!i.suffix)
29b0f896 5219 {
9306ca4a
JB		 5220 if (!intel_syntax)
5221 {
40fb9820 5222 if (i.tm.opcode_modifier.w)
9306ca4a 5223 {
4eed87de
AM		 5224 as_bad (_("no instruction mnemonic suffix given and "
5225 "no register operands; can't size instruction"));
9306ca4a
JB		 5226 return 0;
5227 }
5228 }
5229 else
5230 {
40fb9820 5231 unsigned int suffixes;
7ab9ffdd 5232
40fb9820
L		 5233 suffixes = !i.tm.opcode_modifier.no_bsuf;
5234 if (!i.tm.opcode_modifier.no_wsuf)
5235 suffixes |= 1 << 1;
5236 if (!i.tm.opcode_modifier.no_lsuf)
5237 suffixes |= 1 << 2;
fc4adea1 5238 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5239 suffixes |= 1 << 3;
5240 if (!i.tm.opcode_modifier.no_ssuf)
5241 suffixes |= 1 << 4;
5242 if (!i.tm.opcode_modifier.no_qsuf)
5243 suffixes |= 1 << 5;
5244
5245 /* There are more than suffix matches. */
5246 if (i.tm.opcode_modifier.w
9306ca4a 5247 || ((suffixes & (suffixes - 1))
40fb9820
L		 5248 && !i.tm.opcode_modifier.defaultsize
5249 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5250 {
5251 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5252 return 0;
5253 }
5254 }
29b0f896 5255 }
252b5132 5256
9306ca4a
JB		 5257 /* Change the opcode based on the operand size given by i.suffix;
5258 We don't need to change things for byte insns. */
5259
582d5edd
L		 5260 if (i.suffix
5261 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5262 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5263 && i.suffix != YMMWORD_MNEM_SUFFIX
5264 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5265 {
5266 /* It's not a byte, select word/dword operation. */
40fb9820 5267 if (i.tm.opcode_modifier.w)
29b0f896 5268 {
40fb9820 5269 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5270 i.tm.base_opcode |= 8;
5271 else
5272 i.tm.base_opcode |= 1;
5273 }
0f3f3d8b 5274
29b0f896
AM		 5275 /* Now select between word & dword operations via the operand
5276 size prefix, except for instructions that will ignore this
5277 prefix anyway. */
ca61edf2 5278 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5279 {
ca61edf2
L		 5280 /* The address size override prefix changes the size of the
5281 first operand. */
40fb9820
L		 5282 if ((flag_code == CODE_32BIT
5283 && i.op->regs[0].reg_type.bitfield.reg16)
5284 || (flag_code != CODE_32BIT
5285 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5286 if (!add_prefix (ADDR_PREFIX_OPCODE))
5287 return 0;
5288 }
5289 else if (i.suffix != QWORD_MNEM_SUFFIX
5290 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5291 && !i.tm.opcode_modifier.ignoresize
5292 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5293 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5294 || (flag_code == CODE_64BIT
40fb9820 5295 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5296 {
5297 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5298
40fb9820 5299 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5300 prefix = ADDR_PREFIX_OPCODE;
252b5132 5301
29b0f896
AM		 5302 if (!add_prefix (prefix))
5303 return 0;
24eab124 5304 }
252b5132 5305
29b0f896
AM		 5306 /* Set mode64 for an operand. */
5307 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5308 && flag_code == CODE_64BIT
40fb9820 5309 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5310 {
5311 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5312 need rex64. cmpxchg8b is also a special case. */
5313 if (! (i.operands == 2
5314 && i.tm.base_opcode == 0x90
5315 && i.tm.extension_opcode == None
0dfbf9d7
L		 5316 && operand_type_equal (&i.types [0], &acc64)
5317 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5318 && ! (i.operands == 1
5319 && i.tm.base_opcode == 0xfc7
5320 && i.tm.extension_opcode == 1
40fb9820
L		 5321 && !operand_type_check (i.types [0], reg)
5322 && operand_type_check (i.types [0], anymem)))
f6bee062 5323 i.rex |= REX_W;
46e883c5 5324 }
3e73aa7c 5325
29b0f896
AM		 5326 /* Size floating point instruction. */
5327 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5328 if (i.tm.opcode_modifier.floatmf)
543613e9 5329 i.tm.base_opcode ^= 4;
29b0f896 5330 }
7ecd2f8b 5331
29b0f896
AM		 5332 return 1;
5333}
3e73aa7c 5334
29b0f896 5335static int
543613e9 5336check_byte_reg (void)
29b0f896
AM		 5337{
5338 int op;
543613e9 5339
29b0f896
AM		 5340 for (op = i.operands; --op >= 0;)
5341 {
5342 /* If this is an eight bit register, it's OK. If it's the 16 or
5343 32 bit version of an eight bit register, we will just use the
5344 low portion, and that's OK too. */
40fb9820 5345 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5346 continue;
5347
5a819eb9
JB		 5348 /* I/O port address operands are OK too. */
5349 if (i.tm.operand_types[op].bitfield.inoutportreg)
5350 continue;
5351
9344ff29
L		 5352 /* crc32 doesn't generate this warning. */
5353 if (i.tm.base_opcode == 0xf20f38f0)
5354 continue;
5355
40fb9820
L		 5356 if ((i.types[op].bitfield.reg16
5357 || i.types[op].bitfield.reg32
5358 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5359 && i.op[op].regs->reg_num < 4
5360 /* Prohibit these changes in 64bit mode, since the lowering
5361 would be more complicated. */
5362 && flag_code != CODE_64BIT)
29b0f896 5363 {
29b0f896 5364#if REGISTER_WARNINGS
5a819eb9 5365 if (!quiet_warnings)
a540244d
L		 5366 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5367 register_prefix,
40fb9820 5368 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5369 ? REGNAM_AL - REGNAM_AX
5370 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5371 register_prefix,
29b0f896
AM		 5372 i.op[op].regs->reg_name,
5373 i.suffix);
5374#endif
5375 continue;
5376 }
5377 /* Any other register is bad. */
40fb9820
L		 5378 if (i.types[op].bitfield.reg16
5379 || i.types[op].bitfield.reg32
5380 || i.types[op].bitfield.reg64
5381 || i.types[op].bitfield.regmmx
5382 || i.types[op].bitfield.regxmm
c0f3af97 5383 || i.types[op].bitfield.regymm
43234a1e 5384 || i.types[op].bitfield.regzmm
40fb9820
L		 5385 || i.types[op].bitfield.sreg2
5386 || i.types[op].bitfield.sreg3
5387 || i.types[op].bitfield.control
5388 || i.types[op].bitfield.debug
5389 || i.types[op].bitfield.test
5390 || i.types[op].bitfield.floatreg
5391 || i.types[op].bitfield.floatacc)
29b0f896 5392 {
a540244d
L		 5393 as_bad (_("`%s%s' not allowed with `%s%c'"),
5394 register_prefix,
29b0f896
AM		 5395 i.op[op].regs->reg_name,
5396 i.tm.name,
5397 i.suffix);
5398 return 0;
5399 }
5400 }
5401 return 1;
5402}
5403
5404static int
e3bb37b5 5405check_long_reg (void)
29b0f896
AM		 5406{
5407 int op;
5408
5409 for (op = i.operands; --op >= 0;)
5410 /* Reject eight bit registers, except where the template requires
5411 them. (eg. movzb) */
40fb9820
L		 5412 if (i.types[op].bitfield.reg8
5413 && (i.tm.operand_types[op].bitfield.reg16
5414 || i.tm.operand_types[op].bitfield.reg32
5415 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5416 {
a540244d
L		 5417 as_bad (_("`%s%s' not allowed with `%s%c'"),
5418 register_prefix,
29b0f896
AM		 5419 i.op[op].regs->reg_name,
5420 i.tm.name,
5421 i.suffix);
5422 return 0;
5423 }
e4630f71 5424 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5425 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5426 && i.types[op].bitfield.reg16
5427 && (i.tm.operand_types[op].bitfield.reg32
5428 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5429 {
5430 /* Prohibit these changes in the 64bit mode, since the
5431 lowering is more complicated. */
5432 if (flag_code == CODE_64BIT)
252b5132 5433 {
2b5d6a91 5434 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5435 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5436 i.suffix);
5437 return 0;
252b5132 5438 }
29b0f896 5439#if REGISTER_WARNINGS
cecf1424
JB		 5440 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5441 register_prefix,
5442 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5443 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5444#endif
252b5132 5445 }
e4630f71 5446 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5447 else if (i.types[op].bitfield.reg64
5448 && (i.tm.operand_types[op].bitfield.reg32
5449 || i.tm.operand_types[op].bitfield.acc))
252b5132 5450 {
34828aad 5451 if (intel_syntax
ca61edf2 5452 && i.tm.opcode_modifier.toqword
40fb9820 5453 && !i.types[0].bitfield.regxmm)
34828aad 5454 {
ca61edf2 5455 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5456 i.suffix = QWORD_MNEM_SUFFIX;
5457 }
5458 else
5459 {
2b5d6a91 5460 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5461 register_prefix, i.op[op].regs->reg_name,
5462 i.suffix);
5463 return 0;
5464 }
29b0f896
AM		 5465 }
5466 return 1;
5467}
252b5132 5468
29b0f896 5469static int
e3bb37b5 5470check_qword_reg (void)
29b0f896
AM		 5471{
5472 int op;
252b5132 5473
29b0f896
AM		 5474 for (op = i.operands; --op >= 0; )
5475 /* Reject eight bit registers, except where the template requires
5476 them. (eg. movzb) */
40fb9820
L		 5477 if (i.types[op].bitfield.reg8
5478 && (i.tm.operand_types[op].bitfield.reg16
5479 || i.tm.operand_types[op].bitfield.reg32
5480 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5481 {
a540244d
L		 5482 as_bad (_("`%s%s' not allowed with `%s%c'"),
5483 register_prefix,
29b0f896
AM		 5484 i.op[op].regs->reg_name,
5485 i.tm.name,
5486 i.suffix);
5487 return 0;
5488 }
e4630f71 5489 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5490 else if ((i.types[op].bitfield.reg16
5491 || i.types[op].bitfield.reg32)
5492 && (i.tm.operand_types[op].bitfield.reg32
5493 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5494 {
5495 /* Prohibit these changes in the 64bit mode, since the
5496 lowering is more complicated. */
34828aad 5497 if (intel_syntax
ca61edf2 5498 && i.tm.opcode_modifier.todword
40fb9820 5499 && !i.types[0].bitfield.regxmm)
34828aad 5500 {
ca61edf2 5501 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5502 i.suffix = LONG_MNEM_SUFFIX;
5503 }
5504 else
5505 {
2b5d6a91 5506 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5507 register_prefix, i.op[op].regs->reg_name,
5508 i.suffix);
5509 return 0;
5510 }
252b5132 5511 }
29b0f896
AM		 5512 return 1;
5513}
252b5132 5514
29b0f896 5515static int
e3bb37b5 5516check_word_reg (void)
29b0f896
AM		 5517{
5518 int op;
5519 for (op = i.operands; --op >= 0;)
5520 /* Reject eight bit registers, except where the template requires
5521 them. (eg. movzb) */
40fb9820
L		 5522 if (i.types[op].bitfield.reg8
5523 && (i.tm.operand_types[op].bitfield.reg16
5524 || i.tm.operand_types[op].bitfield.reg32
5525 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5526 {
a540244d
L		 5527 as_bad (_("`%s%s' not allowed with `%s%c'"),
5528 register_prefix,
29b0f896
AM		 5529 i.op[op].regs->reg_name,
5530 i.tm.name,
5531 i.suffix);
5532 return 0;
5533 }
e4630f71 5534 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5535 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5536 && (i.types[op].bitfield.reg32
5537 || i.types[op].bitfield.reg64)
40fb9820
L		 5538 && (i.tm.operand_types[op].bitfield.reg16
5539 || i.tm.operand_types[op].bitfield.acc))
252b5132 5540 {
29b0f896
AM		 5541 /* Prohibit these changes in the 64bit mode, since the
5542 lowering is more complicated. */
5543 if (flag_code == CODE_64BIT)
252b5132 5544 {
2b5d6a91 5545 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5546 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5547 i.suffix);
5548 return 0;
252b5132 5549 }
29b0f896 5550#if REGISTER_WARNINGS
cecf1424
JB		 5551 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5552 register_prefix,
5553 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5554 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5555#endif
5556 }
5557 return 1;
5558}
252b5132 5559
29b0f896 5560static int
40fb9820 5561update_imm (unsigned int j)
29b0f896 5562{
bc0844ae 5563 i386_operand_type overlap = i.types[j];
40fb9820
L		 5564 if ((overlap.bitfield.imm8
5565 || overlap.bitfield.imm8s
5566 || overlap.bitfield.imm16
5567 || overlap.bitfield.imm32
5568 || overlap.bitfield.imm32s
5569 || overlap.bitfield.imm64)
0dfbf9d7
L		 5570 && !operand_type_equal (&overlap, &imm8)
5571 && !operand_type_equal (&overlap, &imm8s)
5572 && !operand_type_equal (&overlap, &imm16)
5573 && !operand_type_equal (&overlap, &imm32)
5574 && !operand_type_equal (&overlap, &imm32s)
5575 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5576 {
5577 if (i.suffix)
5578 {
40fb9820
L		 5579 i386_operand_type temp;
5580
0dfbf9d7 5581 operand_type_set (&temp, 0);
7ab9ffdd 5582 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5583 {
5584 temp.bitfield.imm8 = overlap.bitfield.imm8;
5585 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5586 }
5587 else if (i.suffix == WORD_MNEM_SUFFIX)
5588 temp.bitfield.imm16 = overlap.bitfield.imm16;
5589 else if (i.suffix == QWORD_MNEM_SUFFIX)
5590 {
5591 temp.bitfield.imm64 = overlap.bitfield.imm64;
5592 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5593 }
5594 else
5595 temp.bitfield.imm32 = overlap.bitfield.imm32;
5596 overlap = temp;
29b0f896 5597 }
0dfbf9d7
L		 5598 else if (operand_type_equal (&overlap, &imm16_32_32s)
5599 || operand_type_equal (&overlap, &imm16_32)
5600 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5601 {
40fb9820 5602 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5603 overlap = imm16;
40fb9820 5604 else
65da13b5 5605 overlap = imm32s;
29b0f896 5606 }
0dfbf9d7
L		 5607 if (!operand_type_equal (&overlap, &imm8)
5608 && !operand_type_equal (&overlap, &imm8s)
5609 && !operand_type_equal (&overlap, &imm16)
5610 && !operand_type_equal (&overlap, &imm32)
5611 && !operand_type_equal (&overlap, &imm32s)
5612 && !operand_type_equal (&overlap, &imm64))
29b0f896 5613 {
4eed87de
AM		 5614 as_bad (_("no instruction mnemonic suffix given; "
5615 "can't determine immediate size"));
29b0f896
AM		 5616 return 0;
5617 }
5618 }
40fb9820 5619 i.types[j] = overlap;
29b0f896 5620
40fb9820
L		 5621 return 1;
5622}
5623
5624static int
5625finalize_imm (void)
5626{
bc0844ae 5627 unsigned int j, n;
29b0f896 5628
bc0844ae
L		 5629 /* Update the first 2 immediate operands. */
5630 n = i.operands > 2 ? 2 : i.operands;
5631 if (n)
5632 {
5633 for (j = 0; j < n; j++)
5634 if (update_imm (j) == 0)
5635 return 0;
40fb9820 5636
bc0844ae
L		 5637 /* The 3rd operand can't be immediate operand. */
5638 gas_assert (operand_type_check (i.types[2], imm) == 0);
5639 }
29b0f896
AM		 5640
5641 return 1;
5642}
5643
c0f3af97
L		 5644static int
5645bad_implicit_operand (int xmm)
5646{
91d6fa6a
NC		 5647 const char *ireg = xmm ? "xmm0" : "ymm0";
5648
c0f3af97
L		 5649 if (intel_syntax)
5650 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5651 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5652 else
5653 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5654 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5655 return 0;
5656}
5657
29b0f896 5658static int
e3bb37b5 5659process_operands (void)
29b0f896
AM		 5660{
5661 /* Default segment register this instruction will use for memory
5662 accesses. 0 means unknown. This is only for optimizing out
5663 unnecessary segment overrides. */
5664 const seg_entry *default_seg = 0;
5665
2426c15f 5666 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5667 {
91d6fa6a
NC		 5668 unsigned int dupl = i.operands;
5669 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5670 unsigned int j;
5671
c0f3af97 5672 /* The destination must be an xmm register. */
9c2799c2 5673 gas_assert (i.reg_operands
91d6fa6a 5674 && MAX_OPERANDS > dupl
7ab9ffdd 5675 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5676
5677 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5678 {
c0f3af97 5679 /* The first operand is implicit and must be xmm0. */
9c2799c2 5680 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5681 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5682 return bad_implicit_operand (1);
5683
8cd7925b 5684 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5685 {
5686 /* Keep xmm0 for instructions with VEX prefix and 3
5687 sources. */
5688 goto duplicate;
5689 }
e2ec9d29 5690 else
c0f3af97
L		 5691 {
5692 /* We remove the first xmm0 and keep the number of
5693 operands unchanged, which in fact duplicates the
5694 destination. */
5695 for (j = 1; j < i.operands; j++)
5696 {
5697 i.op[j - 1] = i.op[j];
5698 i.types[j - 1] = i.types[j];
5699 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5700 }
5701 }
5702 }
5703 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5704 {
91d6fa6a 5705 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5706 && (i.tm.opcode_modifier.vexsources
5707 == VEX3SOURCES));
c0f3af97
L		 5708
5709 /* Add the implicit xmm0 for instructions with VEX prefix
5710 and 3 sources. */
5711 for (j = i.operands; j > 0; j--)
5712 {
5713 i.op[j] = i.op[j - 1];
5714 i.types[j] = i.types[j - 1];
5715 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5716 }
5717 i.op[0].regs
5718 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5719 i.types[0] = regxmm;
c0f3af97
L		 5720 i.tm.operand_types[0] = regxmm;
5721
5722 i.operands += 2;
5723 i.reg_operands += 2;
5724 i.tm.operands += 2;
5725
91d6fa6a 5726 dupl++;
c0f3af97 5727 dest++;
91d6fa6a
NC		 5728 i.op[dupl] = i.op[dest];
5729 i.types[dupl] = i.types[dest];
5730 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5731 }
c0f3af97
L		 5732 else
5733 {
5734duplicate:
5735 i.operands++;
5736 i.reg_operands++;
5737 i.tm.operands++;
5738
91d6fa6a
NC		 5739 i.op[dupl] = i.op[dest];
5740 i.types[dupl] = i.types[dest];
5741 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5742 }
5743
5744 if (i.tm.opcode_modifier.immext)
5745 process_immext ();
5746 }
5747 else if (i.tm.opcode_modifier.firstxmm0)
5748 {
5749 unsigned int j;
5750
43234a1e 5751 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5752 gas_assert (i.reg_operands
7ab9ffdd 5753 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5754 || operand_type_equal (&i.types[0], &regymm)
5755 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5756 if (register_number (i.op[0].regs) != 0)
c0f3af97 5757 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5758
5759 for (j = 1; j < i.operands; j++)
5760 {
5761 i.op[j - 1] = i.op[j];
5762 i.types[j - 1] = i.types[j];
5763
5764 /* We need to adjust fields in i.tm since they are used by
5765 build_modrm_byte. */
5766 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5767 }
5768
e2ec9d29
L		 5769 i.operands--;
5770 i.reg_operands--;
e2ec9d29
L		 5771 i.tm.operands--;
5772 }
5773 else if (i.tm.opcode_modifier.regkludge)
5774 {
5775 /* The imul $imm, %reg instruction is converted into
5776 imul $imm, %reg, %reg, and the clr %reg instruction
5777 is converted into xor %reg, %reg. */
5778
5779 unsigned int first_reg_op;
5780
5781 if (operand_type_check (i.types[0], reg))
5782 first_reg_op = 0;
5783 else
5784 first_reg_op = 1;
5785 /* Pretend we saw the extra register operand. */
9c2799c2 5786 gas_assert (i.reg_operands == 1
7ab9ffdd 5787 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5788 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5789 i.types[first_reg_op + 1] = i.types[first_reg_op];
5790 i.operands++;
5791 i.reg_operands++;
29b0f896
AM		 5792 }
5793
40fb9820 5794 if (i.tm.opcode_modifier.shortform)
29b0f896 5795 {
40fb9820
L		 5796 if (i.types[0].bitfield.sreg2
5797 || i.types[0].bitfield.sreg3)
29b0f896 5798 {
4eed87de
AM		 5799 if (i.tm.base_opcode == POP_SEG_SHORT
5800 && i.op[0].regs->reg_num == 1)
29b0f896 5801 {
a87af027 5802 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5803 return 0;
29b0f896 5804 }
4eed87de
AM		 5805 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5806 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5807 i.rex |= REX_B;
4eed87de
AM		 5808 }
5809 else
5810 {
7ab9ffdd 5811 /* The register or float register operand is in operand
85f10a01 5812 0 or 1. */
40fb9820 5813 unsigned int op;
7ab9ffdd
L		 5814
5815 if (i.types[0].bitfield.floatreg
5816 || operand_type_check (i.types[0], reg))
5817 op = 0;
5818 else
5819 op = 1;
4eed87de
AM		 5820 /* Register goes in low 3 bits of opcode. */
5821 i.tm.base_opcode |= i.op[op].regs->reg_num;
5822 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5823 i.rex |= REX_B;
40fb9820 5824 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5825 {
4eed87de
AM		 5826 /* Warn about some common errors, but press on regardless.
5827 The first case can be generated by gcc (<= 2.8.1). */
5828 if (i.operands == 2)
5829 {
5830 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5831 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5832 register_prefix, i.op[!intel_syntax].regs->reg_name,
5833 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5834 }
5835 else
5836 {
5837 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5838 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5839 register_prefix, i.op[0].regs->reg_name);
4eed87de 5840 }
29b0f896
AM		 5841 }
5842 }
5843 }
40fb9820 5844 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5845 {
5846 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5847 must be put into the modrm byte). Now, we make the modrm and
5848 index base bytes based on all the info we've collected. */
29b0f896
AM		 5849
5850 default_seg = build_modrm_byte ();
5851 }
8a2ed489 5852 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5853 {
5854 default_seg = &ds;
5855 }
40fb9820 5856 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5857 {
5858 /* For the string instructions that allow a segment override
5859 on one of their operands, the default segment is ds. */
5860 default_seg = &ds;
5861 }
5862
75178d9d
L		 5863 if (i.tm.base_opcode == 0x8d /* lea */
5864 && i.seg[0]
5865 && !quiet_warnings)
30123838 5866 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5867
5868 /* If a segment was explicitly specified, and the specified segment
5869 is not the default, use an opcode prefix to select it. If we
5870 never figured out what the default segment is, then default_seg
5871 will be zero at this point, and the specified segment prefix will
5872 always be used. */
29b0f896
AM		 5873 if ((i.seg[0]) && (i.seg[0] != default_seg))
5874 {
5875 if (!add_prefix (i.seg[0]->seg_prefix))
5876 return 0;
5877 }
5878 return 1;
5879}
5880
5881static const seg_entry *
e3bb37b5 5882build_modrm_byte (void)
29b0f896
AM		 5883{
5884 const seg_entry *default_seg = 0;
c0f3af97 5885 unsigned int source, dest;
8cd7925b 5886 int vex_3_sources;
c0f3af97
L		 5887
5888 /* The first operand of instructions with VEX prefix and 3 sources
5889 must be VEX_Imm4. */
8cd7925b 5890 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5891 if (vex_3_sources)
5892 {
91d6fa6a 5893 unsigned int nds, reg_slot;
4c2c6516 5894 expressionS *exp;
c0f3af97 5895
922d8de8 5896 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5897 && i.tm.opcode_modifier.immext)
5898 {
5899 dest = i.operands - 2;
5900 gas_assert (dest == 3);
5901 }
922d8de8 5902 else
a683cc34 5903 dest = i.operands - 1;
c0f3af97 5904 nds = dest - 1;
922d8de8 5905
a683cc34
SP		 5906 /* There are 2 kinds of instructions:
5907 1. 5 operands: 4 register operands or 3 register operands
5908 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5909 VexW0 or VexW1. The destination must be either XMM, YMM or
5910 ZMM register.
a683cc34
SP		 5911 2. 4 operands: 4 register operands or 3 register operands
5912 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5913 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5914 || (i.reg_operands == 3 && i.mem_operands == 1))
5915 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5916 && (i.tm.opcode_modifier.veximmext
5917 || (i.imm_operands == 1
5918 && i.types[0].bitfield.vec_imm4
5919 && (i.tm.opcode_modifier.vexw == VEXW0
5920 || i.tm.opcode_modifier.vexw == VEXW1)
5921 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5922 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5923 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5924
5925 if (i.imm_operands == 0)
5926 {
5927 /* When there is no immediate operand, generate an 8bit
5928 immediate operand to encode the first operand. */
5929 exp = &im_expressions[i.imm_operands++];
5930 i.op[i.operands].imms = exp;
5931 i.types[i.operands] = imm8;
5932 i.operands++;
5933 /* If VexW1 is set, the first operand is the source and
5934 the second operand is encoded in the immediate operand. */
5935 if (i.tm.opcode_modifier.vexw == VEXW1)
5936 {
5937 source = 0;
5938 reg_slot = 1;
5939 }
5940 else
5941 {
5942 source = 1;
5943 reg_slot = 0;
5944 }
5945
5946 /* FMA swaps REG and NDS. */
5947 if (i.tm.cpu_flags.bitfield.cpufma)
5948 {
5949 unsigned int tmp;
5950 tmp = reg_slot;
5951 reg_slot = nds;
5952 nds = tmp;
5953 }
5954
24981e7b
L		 5955 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5956 &regxmm)
a683cc34 5957 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5958 &regymm)
5959 || operand_type_equal (&i.tm.operand_types[reg_slot],
5960 &regzmm));
a683cc34 5961 exp->X_op = O_constant;
4c692bc7 5962 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5963 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5964 }
922d8de8 5965 else
a683cc34
SP		 5966 {
5967 unsigned int imm_slot;
5968
5969 if (i.tm.opcode_modifier.vexw == VEXW0)
5970 {
5971 /* If VexW0 is set, the third operand is the source and
5972 the second operand is encoded in the immediate
5973 operand. */
5974 source = 2;
5975 reg_slot = 1;
5976 }
5977 else
5978 {
5979 /* VexW1 is set, the second operand is the source and
5980 the third operand is encoded in the immediate
5981 operand. */
5982 source = 1;
5983 reg_slot = 2;
5984 }
5985
5986 if (i.tm.opcode_modifier.immext)
5987 {
5988 /* When ImmExt is set, the immdiate byte is the last
5989 operand. */
5990 imm_slot = i.operands - 1;
5991 source--;
5992 reg_slot--;
5993 }
5994 else
5995 {
5996 imm_slot = 0;
5997
5998 /* Turn on Imm8 so that output_imm will generate it. */
5999 i.types[imm_slot].bitfield.imm8 = 1;
6000 }
6001
24981e7b
L		 6002 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6003 &regxmm)
6004 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6005 &regymm)
6006 || operand_type_equal (&i.tm.operand_types[reg_slot],
6007 &regzmm));
a683cc34 6008 i.op[imm_slot].imms->X_add_number
4c692bc7 6009 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6010 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6011 }
6012
6013 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6014 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6015 &regymm)
6016 || operand_type_equal (&i.tm.operand_types[nds],
6017 &regzmm));
dae39acc 6018 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6019 }
6020 else
6021 source = dest = 0;
29b0f896
AM		 6022
6023 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6024 implicit registers do not count. If there are 3 register
6025 operands, it must be a instruction with VexNDS. For a
6026 instruction with VexNDD, the destination register is encoded
6027 in VEX prefix. If there are 4 register operands, it must be
6028 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6029 if (i.mem_operands == 0
6030 && ((i.reg_operands == 2
2426c15f 6031 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6032 || (i.reg_operands == 3
2426c15f 6033 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6034 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6035 {
cab737b9
L		 6036 switch (i.operands)
6037 {
6038 case 2:
6039 source = 0;
6040 break;
6041 case 3:
c81128dc
L		 6042 /* When there are 3 operands, one of them may be immediate,
6043 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6044 the first operand must be shift count register (cl) or it
6045 is an instruction with VexNDS. */
9c2799c2 6046 gas_assert (i.imm_operands == 1
7ab9ffdd 6047 || (i.imm_operands == 0
2426c15f 6048 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6049 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6050 if (operand_type_check (i.types[0], imm)
6051 || i.types[0].bitfield.shiftcount)
6052 source = 1;
6053 else
6054 source = 0;
cab737b9
L		 6055 break;
6056 case 4:
368d64cc
L		 6057 /* When there are 4 operands, the first two must be 8bit
6058 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6059 one.
6060
6061 For instructions with VexNDS, if the first operand
6062 an imm8, the source operand is the 2nd one. If the last
6063 operand is imm8, the source operand is the first one. */
9c2799c2 6064 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6065 && i.types[0].bitfield.imm8
6066 && i.types[1].bitfield.imm8)
2426c15f 6067 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6068 && i.imm_operands == 1
6069 && (i.types[0].bitfield.imm8
43234a1e
L		 6070 || i.types[i.operands - 1].bitfield.imm8
6071 || i.rounding)));
9f2670f2
L		 6072 if (i.imm_operands == 2)
6073 source = 2;
6074 else
c0f3af97
L		 6075 {
6076 if (i.types[0].bitfield.imm8)
6077 source = 1;
6078 else
6079 source = 0;
6080 }
c0f3af97
L		 6081 break;
6082 case 5:
43234a1e
L		 6083 if (i.tm.opcode_modifier.evex)
6084 {
6085 /* For EVEX instructions, when there are 5 operands, the
6086 first one must be immediate operand. If the second one
6087 is immediate operand, the source operand is the 3th
6088 one. If the last one is immediate operand, the source
6089 operand is the 2nd one. */
6090 gas_assert (i.imm_operands == 2
6091 && i.tm.opcode_modifier.sae
6092 && operand_type_check (i.types[0], imm));
6093 if (operand_type_check (i.types[1], imm))
6094 source = 2;
6095 else if (operand_type_check (i.types[4], imm))
6096 source = 1;
6097 else
6098 abort ();
6099 }
cab737b9
L		 6100 break;
6101 default:
6102 abort ();
6103 }
6104
c0f3af97
L		 6105 if (!vex_3_sources)
6106 {
6107 dest = source + 1;
6108
43234a1e
L		 6109 /* RC/SAE operand could be between DEST and SRC. That happens
6110 when one operand is GPR and the other one is XMM/YMM/ZMM
6111 register. */
6112 if (i.rounding && i.rounding->operand == (int) dest)
6113 dest++;
6114
2426c15f 6115 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6116 {
43234a1e
L		 6117 /* For instructions with VexNDS, the register-only source
6118 operand must be 32/64bit integer, XMM, YMM or ZMM
6119 register. It is encoded in VEX prefix. We need to
6120 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6121
6122 i386_operand_type op;
6123 unsigned int vvvv;
6124
6125 /* Check register-only source operand when two source
6126 operands are swapped. */
6127 if (!i.tm.operand_types[source].bitfield.baseindex
6128 && i.tm.operand_types[dest].bitfield.baseindex)
6129 {
6130 vvvv = source;
6131 source = dest;
6132 }
6133 else
6134 vvvv = dest;
6135
6136 op = i.tm.operand_types[vvvv];
fa99fab2 6137 op.bitfield.regmem = 0;
c0f3af97 6138 if ((dest + 1) >= i.operands
f12dc422
L		 6139 || (op.bitfield.reg32 != 1
6140 && !op.bitfield.reg64 != 1
6141 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6142 && !operand_type_equal (&op, &regymm)
6143 && !operand_type_equal (&op, &regzmm)
6144 && !operand_type_equal (&op, &regmask)))
c0f3af97 6145 abort ();
f12dc422 6146 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6147 dest++;
6148 }
6149 }
29b0f896
AM		 6150
6151 i.rm.mode = 3;
6152 /* One of the register operands will be encoded in the i.tm.reg
6153 field, the other in the combined i.tm.mode and i.tm.regmem
6154 fields. If no form of this instruction supports a memory
6155 destination operand, then we assume the source operand may
6156 sometimes be a memory operand and so we need to store the
6157 destination in the i.rm.reg field. */
40fb9820
L		 6158 if (!i.tm.operand_types[dest].bitfield.regmem
6159 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6160 {
6161 i.rm.reg = i.op[dest].regs->reg_num;
6162 i.rm.regmem = i.op[source].regs->reg_num;
6163 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6164 i.rex |= REX_R;
43234a1e
L		 6165 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6166 i.vrex |= REX_R;
29b0f896 6167 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6168 i.rex |= REX_B;
43234a1e
L		 6169 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6170 i.vrex |= REX_B;
29b0f896
AM		 6171 }
6172 else
6173 {
6174 i.rm.reg = i.op[source].regs->reg_num;
6175 i.rm.regmem = i.op[dest].regs->reg_num;
6176 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6177 i.rex |= REX_B;
43234a1e
L		 6178 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6179 i.vrex |= REX_B;
29b0f896 6180 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6181 i.rex |= REX_R;
43234a1e
L		 6182 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6183 i.vrex |= REX_R;
29b0f896 6184 }
161a04f6 6185 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6186 {
40fb9820
L		 6187 if (!i.types[0].bitfield.control
6188 && !i.types[1].bitfield.control)
c4a530c5 6189 abort ();
161a04f6 6190 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6191 add_prefix (LOCK_PREFIX_OPCODE);
6192 }
29b0f896
AM		 6193 }
6194 else
6195 { /* If it's not 2 reg operands... */
c0f3af97
L		 6196 unsigned int mem;
6197
29b0f896
AM		 6198 if (i.mem_operands)
6199 {
6200 unsigned int fake_zero_displacement = 0;
99018f42 6201 unsigned int op;
4eed87de 6202
7ab9ffdd
L		 6203 for (op = 0; op < i.operands; op++)
6204 if (operand_type_check (i.types[op], anymem))
6205 break;
7ab9ffdd 6206 gas_assert (op < i.operands);
29b0f896 6207
6c30d220
L		 6208 if (i.tm.opcode_modifier.vecsib)
6209 {
6210 if (i.index_reg->reg_num == RegEiz
6211 || i.index_reg->reg_num == RegRiz)
6212 abort ();
6213
6214 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6215 if (!i.base_reg)
6216 {
6217 i.sib.base = NO_BASE_REGISTER;
6218 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6219 /* No Vec_Disp8 if there is no base. */
6220 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6221 i.types[op].bitfield.disp8 = 0;
6222 i.types[op].bitfield.disp16 = 0;
6223 i.types[op].bitfield.disp64 = 0;
6224 if (flag_code != CODE_64BIT)
6225 {
6226 /* Must be 32 bit */
6227 i.types[op].bitfield.disp32 = 1;
6228 i.types[op].bitfield.disp32s = 0;
6229 }
6230 else
6231 {
6232 i.types[op].bitfield.disp32 = 0;
6233 i.types[op].bitfield.disp32s = 1;
6234 }
6235 }
6236 i.sib.index = i.index_reg->reg_num;
6237 if ((i.index_reg->reg_flags & RegRex) != 0)
6238 i.rex |= REX_X;
43234a1e
L		 6239 if ((i.index_reg->reg_flags & RegVRex) != 0)
6240 i.vrex |= REX_X;
6c30d220
L		 6241 }
6242
29b0f896
AM		 6243 default_seg = &ds;
6244
6245 if (i.base_reg == 0)
6246 {
6247 i.rm.mode = 0;
6248 if (!i.disp_operands)
6c30d220
L		 6249 {
6250 fake_zero_displacement = 1;
6251 /* Instructions with VSIB byte need 32bit displacement
6252 if there is no base register. */
6253 if (i.tm.opcode_modifier.vecsib)
6254 i.types[op].bitfield.disp32 = 1;
6255 }
29b0f896
AM		 6256 if (i.index_reg == 0)
6257 {
6c30d220 6258 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6259 /* Operand is just <disp> */
20f0a1fc 6260 if (flag_code == CODE_64BIT)
29b0f896
AM		 6261 {
6262 /* 64bit mode overwrites the 32bit absolute
6263 addressing by RIP relative addressing and
6264 absolute addressing is encoded by one of the
6265 redundant SIB forms. */
6266 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6267 i.sib.base = NO_BASE_REGISTER;
6268 i.sib.index = NO_INDEX_REGISTER;
fc225355 6269 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6270 ? disp32s : disp32);
20f0a1fc 6271 }
fc225355
L		 6272 else if ((flag_code == CODE_16BIT)
6273 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6274 {
6275 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6276 i.types[op] = disp16;
20f0a1fc
NC		 6277 }
6278 else
6279 {
6280 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6281 i.types[op] = disp32;
29b0f896
AM		 6282 }
6283 }
6c30d220 6284 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6285 {
6c30d220 6286 /* !i.base_reg && i.index_reg */
db51cc60
L		 6287 if (i.index_reg->reg_num == RegEiz
6288 || i.index_reg->reg_num == RegRiz)
6289 i.sib.index = NO_INDEX_REGISTER;
6290 else
6291 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6292 i.sib.base = NO_BASE_REGISTER;
6293 i.sib.scale = i.log2_scale_factor;
6294 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6295 /* No Vec_Disp8 if there is no base. */
6296 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6297 i.types[op].bitfield.disp8 = 0;
6298 i.types[op].bitfield.disp16 = 0;
6299 i.types[op].bitfield.disp64 = 0;
29b0f896 6300 if (flag_code != CODE_64BIT)
40fb9820
L		 6301 {
6302 /* Must be 32 bit */
6303 i.types[op].bitfield.disp32 = 1;
6304 i.types[op].bitfield.disp32s = 0;
6305 }
29b0f896 6306 else
40fb9820
L		 6307 {
6308 i.types[op].bitfield.disp32 = 0;
6309 i.types[op].bitfield.disp32s = 1;
6310 }
29b0f896 6311 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6312 i.rex |= REX_X;
29b0f896
AM		 6313 }
6314 }
6315 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6316 else if (i.base_reg->reg_num == RegRip ||
6317 i.base_reg->reg_num == RegEip)
29b0f896 6318 {
6c30d220 6319 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6320 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6321 i.types[op].bitfield.disp8 = 0;
6322 i.types[op].bitfield.disp16 = 0;
6323 i.types[op].bitfield.disp32 = 0;
6324 i.types[op].bitfield.disp32s = 1;
6325 i.types[op].bitfield.disp64 = 0;
43234a1e 6326 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6327 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6328 if (! i.disp_operands)
6329 fake_zero_displacement = 1;
29b0f896 6330 }
40fb9820 6331 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6332 {
6c30d220 6333 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6334 switch (i.base_reg->reg_num)
6335 {
6336 case 3: /* (%bx) */
6337 if (i.index_reg == 0)
6338 i.rm.regmem = 7;
6339 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6340 i.rm.regmem = i.index_reg->reg_num - 6;
6341 break;
6342 case 5: /* (%bp) */
6343 default_seg = &ss;
6344 if (i.index_reg == 0)
6345 {
6346 i.rm.regmem = 6;
40fb9820 6347 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6348 {
6349 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6350 if (i.tm.operand_types[op].bitfield.vec_disp8)
6351 i.types[op].bitfield.vec_disp8 = 1;
6352 else
6353 i.types[op].bitfield.disp8 = 1;
252b5132 6354 fake_zero_displacement = 1;
29b0f896
AM		 6355 }
6356 }
6357 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6358 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6359 break;
6360 default: /* (%si) -> 4 or (%di) -> 5 */
6361 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6362 }
6363 i.rm.mode = mode_from_disp_size (i.types[op]);
6364 }
6365 else /* i.base_reg and 32/64 bit mode */
6366 {
6367 if (flag_code == CODE_64BIT
40fb9820
L		 6368 && operand_type_check (i.types[op], disp))
6369 {
6370 i386_operand_type temp;
0dfbf9d7 6371 operand_type_set (&temp, 0);
40fb9820 6372 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6373 temp.bitfield.vec_disp8
6374 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6375 i.types[op] = temp;
6376 if (i.prefix[ADDR_PREFIX] == 0)
6377 i.types[op].bitfield.disp32s = 1;
6378 else
6379 i.types[op].bitfield.disp32 = 1;
6380 }
20f0a1fc 6381
6c30d220
L		 6382 if (!i.tm.opcode_modifier.vecsib)
6383 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6384 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6385 i.rex |= REX_B;
29b0f896
AM		 6386 i.sib.base = i.base_reg->reg_num;
6387 /* x86-64 ignores REX prefix bit here to avoid decoder
6388 complications. */
848930b2
JB		 6389 if (!(i.base_reg->reg_flags & RegRex)
6390 && (i.base_reg->reg_num == EBP_REG_NUM
6391 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6392 default_seg = &ss;
848930b2 6393 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6394 {
848930b2 6395 fake_zero_displacement = 1;
43234a1e
L		 6396 if (i.tm.operand_types [op].bitfield.vec_disp8)
6397 i.types[op].bitfield.vec_disp8 = 1;
6398 else
6399 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6400 }
6401 i.sib.scale = i.log2_scale_factor;
6402 if (i.index_reg == 0)
6403 {
6c30d220 6404 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6405 /* <disp>(%esp) becomes two byte modrm with no index
6406 register. We've already stored the code for esp
6407 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6408 Any base register besides %esp will not use the
6409 extra modrm byte. */
6410 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6411 }
6c30d220 6412 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6413 {
db51cc60
L		 6414 if (i.index_reg->reg_num == RegEiz
6415 || i.index_reg->reg_num == RegRiz)
6416 i.sib.index = NO_INDEX_REGISTER;
6417 else
6418 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6419 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6420 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6421 i.rex |= REX_X;
29b0f896 6422 }
67a4f2b7
AO		 6423
6424 if (i.disp_operands
6425 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6426 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6427 i.rm.mode = 0;
6428 else
a501d77e
L		 6429 {
6430 if (!fake_zero_displacement
6431 && !i.disp_operands
6432 && i.disp_encoding)
6433 {
6434 fake_zero_displacement = 1;
6435 if (i.disp_encoding == disp_encoding_8bit)
6436 i.types[op].bitfield.disp8 = 1;
6437 else
6438 i.types[op].bitfield.disp32 = 1;
6439 }
6440 i.rm.mode = mode_from_disp_size (i.types[op]);
6441 }
29b0f896 6442 }
252b5132 6443
29b0f896
AM		 6444 if (fake_zero_displacement)
6445 {
6446 /* Fakes a zero displacement assuming that i.types[op]
6447 holds the correct displacement size. */
6448 expressionS *exp;
6449
9c2799c2 6450 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6451 exp = &disp_expressions[i.disp_operands++];
6452 i.op[op].disps = exp;
6453 exp->X_op = O_constant;
6454 exp->X_add_number = 0;
6455 exp->X_add_symbol = (symbolS *) 0;
6456 exp->X_op_symbol = (symbolS *) 0;
6457 }
c0f3af97
L		 6458
6459 mem = op;
29b0f896 6460 }
c0f3af97
L		 6461 else
6462 mem = ~0;
252b5132 6463
8c43a48b 6464 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6465 {
6466 if (operand_type_check (i.types[0], imm))
6467 i.vex.register_specifier = NULL;
6468 else
6469 {
6470 /* VEX.vvvv encodes one of the sources when the first
6471 operand is not an immediate. */
1ef99a7b 6472 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6473 i.vex.register_specifier = i.op[0].regs;
6474 else
6475 i.vex.register_specifier = i.op[1].regs;
6476 }
6477
6478 /* Destination is a XMM register encoded in the ModRM.reg
6479 and VEX.R bit. */
6480 i.rm.reg = i.op[2].regs->reg_num;
6481 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6482 i.rex |= REX_R;
6483
6484 /* ModRM.rm and VEX.B encodes the other source. */
6485 if (!i.mem_operands)
6486 {
6487 i.rm.mode = 3;
6488
1ef99a7b 6489 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6490 i.rm.regmem = i.op[1].regs->reg_num;
6491 else
6492 i.rm.regmem = i.op[0].regs->reg_num;
6493
6494 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6495 i.rex |= REX_B;
6496 }
6497 }
2426c15f 6498 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6499 {
6500 i.vex.register_specifier = i.op[2].regs;
6501 if (!i.mem_operands)
6502 {
6503 i.rm.mode = 3;
6504 i.rm.regmem = i.op[1].regs->reg_num;
6505 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6506 i.rex |= REX_B;
6507 }
6508 }
29b0f896
AM		 6509 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6510 (if any) based on i.tm.extension_opcode. Again, we must be
6511 careful to make sure that segment/control/debug/test/MMX
6512 registers are coded into the i.rm.reg field. */
f88c9eb0 6513 else if (i.reg_operands)
29b0f896 6514 {
99018f42 6515 unsigned int op;
7ab9ffdd
L		 6516 unsigned int vex_reg = ~0;
6517
6518 for (op = 0; op < i.operands; op++)
6519 if (i.types[op].bitfield.reg8
6520 || i.types[op].bitfield.reg16
6521 || i.types[op].bitfield.reg32
6522 || i.types[op].bitfield.reg64
6523 || i.types[op].bitfield.regmmx
6524 || i.types[op].bitfield.regxmm
6525 || i.types[op].bitfield.regymm
7e8b059b 6526 || i.types[op].bitfield.regbnd
43234a1e
L		 6527 || i.types[op].bitfield.regzmm
6528 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6529 || i.types[op].bitfield.sreg2
6530 || i.types[op].bitfield.sreg3
6531 || i.types[op].bitfield.control
6532 || i.types[op].bitfield.debug
6533 || i.types[op].bitfield.test)
6534 break;
c0209578 6535
7ab9ffdd
L		 6536 if (vex_3_sources)
6537 op = dest;
2426c15f 6538 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6539 {
6540 /* For instructions with VexNDS, the register-only
6541 source operand is encoded in VEX prefix. */
6542 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6543
7ab9ffdd 6544 if (op > mem)
c0f3af97 6545 {
7ab9ffdd
L		 6546 vex_reg = op++;
6547 gas_assert (op < i.operands);
c0f3af97
L		 6548 }
6549 else
c0f3af97 6550 {
f12dc422
L		 6551 /* Check register-only source operand when two source
6552 operands are swapped. */
6553 if (!i.tm.operand_types[op].bitfield.baseindex
6554 && i.tm.operand_types[op + 1].bitfield.baseindex)
6555 {
6556 vex_reg = op;
6557 op += 2;
6558 gas_assert (mem == (vex_reg + 1)
6559 && op < i.operands);
6560 }
6561 else
6562 {
6563 vex_reg = op + 1;
6564 gas_assert (vex_reg < i.operands);
6565 }
c0f3af97 6566 }
7ab9ffdd 6567 }
2426c15f 6568 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6569 {
f12dc422 6570 /* For instructions with VexNDD, the register destination
7ab9ffdd 6571 is encoded in VEX prefix. */
f12dc422
L		 6572 if (i.mem_operands == 0)
6573 {
6574 /* There is no memory operand. */
6575 gas_assert ((op + 2) == i.operands);
6576 vex_reg = op + 1;
6577 }
6578 else
8d63c93e 6579 {
f12dc422
L		 6580 /* There are only 2 operands. */
6581 gas_assert (op < 2 && i.operands == 2);
6582 vex_reg = 1;
6583 }
7ab9ffdd
L		 6584 }
6585 else
6586 gas_assert (op < i.operands);
99018f42 6587
7ab9ffdd
L		 6588 if (vex_reg != (unsigned int) ~0)
6589 {
f12dc422 6590 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6591
f12dc422
L		 6592 if (type->bitfield.reg32 != 1
6593 && type->bitfield.reg64 != 1
6594 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6595 && !operand_type_equal (type, &regymm)
6596 && !operand_type_equal (type, &regzmm)
6597 && !operand_type_equal (type, &regmask))
7ab9ffdd 6598 abort ();
f88c9eb0 6599
7ab9ffdd
L		 6600 i.vex.register_specifier = i.op[vex_reg].regs;
6601 }
6602
1b9f0c97
L		 6603 /* Don't set OP operand twice. */
6604 if (vex_reg != op)
7ab9ffdd 6605 {
1b9f0c97
L		 6606 /* If there is an extension opcode to put here, the
6607 register number must be put into the regmem field. */
6608 if (i.tm.extension_opcode != None)
6609 {
6610 i.rm.regmem = i.op[op].regs->reg_num;
6611 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6612 i.rex |= REX_B;
43234a1e
L		 6613 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6614 i.vrex |= REX_B;
1b9f0c97
L		 6615 }
6616 else
6617 {
6618 i.rm.reg = i.op[op].regs->reg_num;
6619 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6620 i.rex |= REX_R;
43234a1e
L		 6621 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6622 i.vrex |= REX_R;
1b9f0c97 6623 }
7ab9ffdd 6624 }
252b5132 6625
29b0f896
AM		 6626 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6627 must set it to 3 to indicate this is a register operand
6628 in the regmem field. */
6629 if (!i.mem_operands)
6630 i.rm.mode = 3;
6631 }
252b5132 6632
29b0f896 6633 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6634 if (i.tm.extension_opcode != None)
29b0f896
AM		 6635 i.rm.reg = i.tm.extension_opcode;
6636 }
6637 return default_seg;
6638}
252b5132 6639
29b0f896 6640static void
e3bb37b5 6641output_branch (void)
29b0f896
AM		 6642{
6643 char *p;
f8a5c266 6644 int size;
29b0f896
AM		 6645 int code16;
6646 int prefix;
6647 relax_substateT subtype;
6648 symbolS *sym;
6649 offsetT off;
6650
f8a5c266 6651 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6652 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6653
6654 prefix = 0;
6655 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6656 {
29b0f896
AM		 6657 prefix = 1;
6658 i.prefixes -= 1;
6659 code16 ^= CODE16;
252b5132 6660 }
29b0f896
AM		 6661 /* Pentium4 branch hints. */
6662 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6663 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6664 {
29b0f896
AM		 6665 prefix++;
6666 i.prefixes--;
6667 }
6668 if (i.prefix[REX_PREFIX] != 0)
6669 {
6670 prefix++;
6671 i.prefixes--;
2f66722d
AM		 6672 }
6673
7e8b059b
L		 6674 /* BND prefixed jump. */
6675 if (i.prefix[BND_PREFIX] != 0)
6676 {
6677 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6678 i.prefixes -= 1;
6679 }
6680
29b0f896
AM		 6681 if (i.prefixes != 0 && !intel_syntax)
6682 as_warn (_("skipping prefixes on this instruction"));
6683
6684 /* It's always a symbol; End frag & setup for relax.
6685 Make sure there is enough room in this frag for the largest
6686 instruction we may generate in md_convert_frag. This is 2
6687 bytes for the opcode and room for the prefix and largest
6688 displacement. */
6689 frag_grow (prefix + 2 + 4);
6690 /* Prefix and 1 opcode byte go in fr_fix. */
6691 p = frag_more (prefix + 1);
6692 if (i.prefix[DATA_PREFIX] != 0)
6693 *p++ = DATA_PREFIX_OPCODE;
6694 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6695 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6696 *p++ = i.prefix[SEG_PREFIX];
6697 if (i.prefix[REX_PREFIX] != 0)
6698 *p++ = i.prefix[REX_PREFIX];
6699 *p = i.tm.base_opcode;
6700
6701 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6702 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6703 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6704 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6705 else
f8a5c266 6706 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6707 subtype |= code16;
3e73aa7c 6708
29b0f896
AM		 6709 sym = i.op[0].disps->X_add_symbol;
6710 off = i.op[0].disps->X_add_number;
3e73aa7c 6711
29b0f896
AM		 6712 if (i.op[0].disps->X_op != O_constant
6713 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6714 {
29b0f896
AM		 6715 /* Handle complex expressions. */
6716 sym = make_expr_symbol (i.op[0].disps);
6717 off = 0;
6718 }
3e73aa7c 6719
29b0f896
AM		 6720 /* 1 possible extra opcode + 4 byte displacement go in var part.
6721 Pass reloc in fr_var. */
c3320543
L		 6722 frag_var (rs_machine_dependent, 5,
6723 ((!object_64bit
6724 || i.reloc[0] != NO_RELOC
6725 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6726 ? i.reloc[0]
6727 : BFD_RELOC_X86_64_PC32_BND),
6728 subtype, sym, off, p);
29b0f896 6729}
3e73aa7c 6730
29b0f896 6731static void
e3bb37b5 6732output_jump (void)
29b0f896
AM		 6733{
6734 char *p;
6735 int size;
3e02c1cc 6736 fixS *fixP;
29b0f896 6737
40fb9820 6738 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6739 {
6740 /* This is a loop or jecxz type instruction. */
6741 size = 1;
6742 if (i.prefix[ADDR_PREFIX] != 0)
6743 {
6744 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6745 i.prefixes -= 1;
6746 }
6747 /* Pentium4 branch hints. */
6748 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6749 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6750 {
6751 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6752 i.prefixes--;
3e73aa7c
JH		 6753 }
6754 }
29b0f896
AM		 6755 else
6756 {
6757 int code16;
3e73aa7c 6758
29b0f896
AM		 6759 code16 = 0;
6760 if (flag_code == CODE_16BIT)
6761 code16 = CODE16;
3e73aa7c 6762
29b0f896
AM		 6763 if (i.prefix[DATA_PREFIX] != 0)
6764 {
6765 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6766 i.prefixes -= 1;
6767 code16 ^= CODE16;
6768 }
252b5132 6769
29b0f896
AM		 6770 size = 4;
6771 if (code16)
6772 size = 2;
6773 }
9fcc94b6 6774
29b0f896
AM		 6775 if (i.prefix[REX_PREFIX] != 0)
6776 {
6777 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6778 i.prefixes -= 1;
6779 }
252b5132 6780
7e8b059b
L		 6781 /* BND prefixed jump. */
6782 if (i.prefix[BND_PREFIX] != 0)
6783 {
6784 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6785 i.prefixes -= 1;
6786 }
6787
29b0f896
AM		 6788 if (i.prefixes != 0 && !intel_syntax)
6789 as_warn (_("skipping prefixes on this instruction"));
e0890092 6790
42164a71
L		 6791 p = frag_more (i.tm.opcode_length + size);
6792 switch (i.tm.opcode_length)
6793 {
6794 case 2:
6795 *p++ = i.tm.base_opcode >> 8;
6796 case 1:
6797 *p++ = i.tm.base_opcode;
6798 break;
6799 default:
6800 abort ();
6801 }
e0890092 6802
3e02c1cc 6803 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6804 i.op[0].disps, 1, reloc (size, 1, 1,
6805 (i.bnd_prefix != NULL
6806 || add_bnd_prefix),
6807 i.reloc[0]));
3e02c1cc
AM		 6808
6809 /* All jumps handled here are signed, but don't use a signed limit
6810 check for 32 and 16 bit jumps as we want to allow wrap around at
6811 4G and 64k respectively. */
6812 if (size == 1)
6813 fixP->fx_signed = 1;
29b0f896 6814}
e0890092 6815
29b0f896 6816static void
e3bb37b5 6817output_interseg_jump (void)
29b0f896
AM		 6818{
6819 char *p;
6820 int size;
6821 int prefix;
6822 int code16;
252b5132 6823
29b0f896
AM		 6824 code16 = 0;
6825 if (flag_code == CODE_16BIT)
6826 code16 = CODE16;
a217f122 6827
29b0f896
AM		 6828 prefix = 0;
6829 if (i.prefix[DATA_PREFIX] != 0)
6830 {
6831 prefix = 1;
6832 i.prefixes -= 1;
6833 code16 ^= CODE16;
6834 }
6835 if (i.prefix[REX_PREFIX] != 0)
6836 {
6837 prefix++;
6838 i.prefixes -= 1;
6839 }
252b5132 6840
29b0f896
AM		 6841 size = 4;
6842 if (code16)
6843 size = 2;
252b5132 6844
29b0f896
AM		 6845 if (i.prefixes != 0 && !intel_syntax)
6846 as_warn (_("skipping prefixes on this instruction"));
252b5132 6847
29b0f896
AM		 6848 /* 1 opcode; 2 segment; offset */
6849 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6850
29b0f896
AM		 6851 if (i.prefix[DATA_PREFIX] != 0)
6852 *p++ = DATA_PREFIX_OPCODE;
252b5132 6853
29b0f896
AM		 6854 if (i.prefix[REX_PREFIX] != 0)
6855 *p++ = i.prefix[REX_PREFIX];
252b5132 6856
29b0f896
AM		 6857 *p++ = i.tm.base_opcode;
6858 if (i.op[1].imms->X_op == O_constant)
6859 {
6860 offsetT n = i.op[1].imms->X_add_number;
252b5132 6861
29b0f896
AM		 6862 if (size == 2
6863 && !fits_in_unsigned_word (n)
6864 && !fits_in_signed_word (n))
6865 {
6866 as_bad (_("16-bit jump out of range"));
6867 return;
6868 }
6869 md_number_to_chars (p, n, size);
6870 }
6871 else
6872 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6873 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6874 if (i.op[0].imms->X_op != O_constant)
6875 as_bad (_("can't handle non absolute segment in `%s'"),
6876 i.tm.name);
6877 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6878}
a217f122 6879
29b0f896 6880static void
e3bb37b5 6881output_insn (void)
29b0f896 6882{
2bbd9c25
JJ		 6883 fragS *insn_start_frag;
6884 offsetT insn_start_off;
6885
29b0f896
AM		 6886 /* Tie dwarf2 debug info to the address at the start of the insn.
6887 We can't do this after the insn has been output as the current
6888 frag may have been closed off. eg. by frag_var. */
6889 dwarf2_emit_insn (0);
6890
2bbd9c25
JJ		 6891 insn_start_frag = frag_now;
6892 insn_start_off = frag_now_fix ();
6893
29b0f896 6894 /* Output jumps. */
40fb9820 6895 if (i.tm.opcode_modifier.jump)
29b0f896 6896 output_branch ();
40fb9820
L		 6897 else if (i.tm.opcode_modifier.jumpbyte
6898 || i.tm.opcode_modifier.jumpdword)
29b0f896 6899 output_jump ();
40fb9820 6900 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6901 output_interseg_jump ();
6902 else
6903 {
6904 /* Output normal instructions here. */
6905 char *p;
6906 unsigned char *q;
47465058 6907 unsigned int j;
331d2d0d 6908 unsigned int prefix;
4dffcebc 6909
43234a1e
L		 6910 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6911 don't need the explicit prefix. */
6912 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6913 {
c0f3af97 6914 switch (i.tm.opcode_length)
bc4bd9ab 6915 {
c0f3af97
L		 6916 case 3:
6917 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6918 {
c0f3af97
L		 6919 prefix = (i.tm.base_opcode >> 24) & 0xff;
6920 goto check_prefix;
6921 }
6922 break;
6923 case 2:
6924 if ((i.tm.base_opcode & 0xff0000) != 0)
6925 {
6926 prefix = (i.tm.base_opcode >> 16) & 0xff;
6927 if (i.tm.cpu_flags.bitfield.cpupadlock)
6928 {
4dffcebc 6929check_prefix:
c0f3af97 6930 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6931 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6932 != REPE_PREFIX_OPCODE))
6933 add_prefix (prefix);
6934 }
6935 else
4dffcebc
L		 6936 add_prefix (prefix);
6937 }
c0f3af97
L		 6938 break;
6939 case 1:
6940 break;
6941 default:
6942 abort ();
bc4bd9ab 6943 }
c0f3af97
L		 6944
6945 /* The prefix bytes. */
6946 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6947 if (*q)
6948 FRAG_APPEND_1_CHAR (*q);
0f10071e 6949 }
ae5c1c7b 6950 else
c0f3af97
L		 6951 {
6952 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6953 if (*q)
6954 switch (j)
6955 {
6956 case REX_PREFIX:
6957 /* REX byte is encoded in VEX prefix. */
6958 break;
6959 case SEG_PREFIX:
6960 case ADDR_PREFIX:
6961 FRAG_APPEND_1_CHAR (*q);
6962 break;
6963 default:
6964 /* There should be no other prefixes for instructions
6965 with VEX prefix. */
6966 abort ();
6967 }
6968
43234a1e
L		 6969 /* For EVEX instructions i.vrex should become 0 after
6970 build_evex_prefix. For VEX instructions upper 16 registers
6971 aren't available, so VREX should be 0. */
6972 if (i.vrex)
6973 abort ();
c0f3af97
L		 6974 /* Now the VEX prefix. */
6975 p = frag_more (i.vex.length);
6976 for (j = 0; j < i.vex.length; j++)
6977 p[j] = i.vex.bytes[j];
6978 }
252b5132 6979
29b0f896 6980 /* Now the opcode; be careful about word order here! */
4dffcebc 6981 if (i.tm.opcode_length == 1)
29b0f896
AM		 6982 {
6983 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6984 }
6985 else
6986 {
4dffcebc 6987 switch (i.tm.opcode_length)
331d2d0d 6988 {
43234a1e
L		 6989 case 4:
6990 p = frag_more (4);
6991 *p++ = (i.tm.base_opcode >> 24) & 0xff;
6992 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6993 break;
4dffcebc 6994 case 3:
331d2d0d
L		 6995 p = frag_more (3);
6996 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6997 break;
6998 case 2:
6999 p = frag_more (2);
7000 break;
7001 default:
7002 abort ();
7003 break;
331d2d0d 7004 }
0f10071e 7005
29b0f896
AM		 7006 /* Put out high byte first: can't use md_number_to_chars! */
7007 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7008 *p = i.tm.base_opcode & 0xff;
7009 }
3e73aa7c 7010
29b0f896 7011 /* Now the modrm byte and sib byte (if present). */
40fb9820 7012 if (i.tm.opcode_modifier.modrm)
29b0f896 7013 {
4a3523fa
L		 7014 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7015 | i.rm.reg << 3
7016 | i.rm.mode << 6));
29b0f896
AM		 7017 /* If i.rm.regmem == ESP (4)
7018 && i.rm.mode != (Register mode)
7019 && not 16 bit
7020 ==> need second modrm byte. */
7021 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7022 && i.rm.mode != 3
40fb9820 7023 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7024 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7025 | i.sib.index << 3
7026 | i.sib.scale << 6));
29b0f896 7027 }
3e73aa7c 7028
29b0f896 7029 if (i.disp_operands)
2bbd9c25 7030 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7031
29b0f896 7032 if (i.imm_operands)
2bbd9c25 7033 output_imm (insn_start_frag, insn_start_off);
29b0f896 7034 }
252b5132 7035
29b0f896
AM		 7036#ifdef DEBUG386
7037 if (flag_debug)
7038 {
7b81dfbb 7039 pi ("" /*line*/, &i);
29b0f896
AM		 7040 }
7041#endif /* DEBUG386 */
7042}
252b5132 7043
e205caa7
L		 7044/* Return the size of the displacement operand N. */
7045
7046static int
7047disp_size (unsigned int n)
7048{
7049 int size = 4;
43234a1e
L		 7050
7051 /* Vec_Disp8 has to be 8bit. */
7052 if (i.types[n].bitfield.vec_disp8)
7053 size = 1;
7054 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7055 size = 8;
7056 else if (i.types[n].bitfield.disp8)
7057 size = 1;
7058 else if (i.types[n].bitfield.disp16)
7059 size = 2;
e205caa7
L		 7060 return size;
7061}
7062
7063/* Return the size of the immediate operand N. */
7064
7065static int
7066imm_size (unsigned int n)
7067{
7068 int size = 4;
40fb9820
L		 7069 if (i.types[n].bitfield.imm64)
7070 size = 8;
7071 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7072 size = 1;
7073 else if (i.types[n].bitfield.imm16)
7074 size = 2;
e205caa7
L		 7075 return size;
7076}
7077
29b0f896 7078static void
64e74474 7079output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7080{
7081 char *p;
7082 unsigned int n;
252b5132 7083
29b0f896
AM		 7084 for (n = 0; n < i.operands; n++)
7085 {
43234a1e
L		 7086 if (i.types[n].bitfield.vec_disp8
7087 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7088 {
7089 if (i.op[n].disps->X_op == O_constant)
7090 {
e205caa7 7091 int size = disp_size (n);
43234a1e 7092 offsetT val = i.op[n].disps->X_add_number;
252b5132 7093
43234a1e
L		 7094 if (i.types[n].bitfield.vec_disp8)
7095 val >>= i.memshift;
7096 val = offset_in_range (val, size);
29b0f896
AM		 7097 p = frag_more (size);
7098 md_number_to_chars (p, val, size);
7099 }
7100 else
7101 {
f86103b7 7102 enum bfd_reloc_code_real reloc_type;
e205caa7 7103 int size = disp_size (n);
40fb9820 7104 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7105 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7106
e205caa7 7107 /* We can't have 8 bit displacement here. */
9c2799c2 7108 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7109
29b0f896
AM		 7110 /* The PC relative address is computed relative
7111 to the instruction boundary, so in case immediate
7112 fields follows, we need to adjust the value. */
7113 if (pcrel && i.imm_operands)
7114 {
29b0f896 7115 unsigned int n1;
e205caa7 7116 int sz = 0;
252b5132 7117
29b0f896 7118 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7119 if (operand_type_check (i.types[n1], imm))
252b5132 7120 {
e205caa7
L		 7121 /* Only one immediate is allowed for PC
7122 relative address. */
9c2799c2 7123 gas_assert (sz == 0);
e205caa7
L		 7124 sz = imm_size (n1);
7125 i.op[n].disps->X_add_number -= sz;
252b5132 7126 }
29b0f896 7127 /* We should find the immediate. */
9c2799c2 7128 gas_assert (sz != 0);
29b0f896 7129 }
520dc8e8 7130
29b0f896 7131 p = frag_more (size);
c3320543
L		 7132 reloc_type = reloc (size, pcrel, sign,
7133 (i.bnd_prefix != NULL
7134 || add_bnd_prefix),
7135 i.reloc[n]);
d6ab8113 7136 if (GOT_symbol
2bbd9c25 7137 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7138 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7139 || reloc_type == BFD_RELOC_X86_64_32S
7140 || (reloc_type == BFD_RELOC_64
7141 && object_64bit))
d6ab8113
JB		 7142 && (i.op[n].disps->X_op == O_symbol
7143 || (i.op[n].disps->X_op == O_add
7144 && ((symbol_get_value_expression
7145 (i.op[n].disps->X_op_symbol)->X_op)
7146 == O_subtract))))
7147 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7148 {
7149 offsetT add;
7150
7151 if (insn_start_frag == frag_now)
7152 add = (p - frag_now->fr_literal) - insn_start_off;
7153 else
7154 {
7155 fragS *fr;
7156
7157 add = insn_start_frag->fr_fix - insn_start_off;
7158 for (fr = insn_start_frag->fr_next;
7159 fr && fr != frag_now; fr = fr->fr_next)
7160 add += fr->fr_fix;
7161 add += p - frag_now->fr_literal;
7162 }
7163
4fa24527 7164 if (!object_64bit)
7b81dfbb
AJ		 7165 {
7166 reloc_type = BFD_RELOC_386_GOTPC;
7167 i.op[n].imms->X_add_number += add;
7168 }
7169 else if (reloc_type == BFD_RELOC_64)
7170 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7171 else
7b81dfbb
AJ		 7172 /* Don't do the adjustment for x86-64, as there
7173 the pcrel addressing is relative to the _next_
7174 insn, and that is taken care of in other code. */
d6ab8113 7175 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7176 }
062cd5e7 7177 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7178 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7179 }
7180 }
7181 }
7182}
252b5132 7183
29b0f896 7184static void
64e74474 7185output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7186{
7187 char *p;
7188 unsigned int n;
252b5132 7189
29b0f896
AM		 7190 for (n = 0; n < i.operands; n++)
7191 {
43234a1e
L		 7192 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7193 if (i.rounding && (int) n == i.rounding->operand)
7194 continue;
7195
40fb9820 7196 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7197 {
7198 if (i.op[n].imms->X_op == O_constant)
7199 {
e205caa7 7200 int size = imm_size (n);
29b0f896 7201 offsetT val;
b4cac588 7202
29b0f896
AM		 7203 val = offset_in_range (i.op[n].imms->X_add_number,
7204 size);
7205 p = frag_more (size);
7206 md_number_to_chars (p, val, size);
7207 }
7208 else
7209 {
7210 /* Not absolute_section.
7211 Need a 32-bit fixup (don't support 8bit
7212 non-absolute imms). Try to support other
7213 sizes ... */
f86103b7 7214 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7215 int size = imm_size (n);
7216 int sign;
29b0f896 7217
40fb9820 7218 if (i.types[n].bitfield.imm32s
a7d61044 7219 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7220 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7221 sign = 1;
e205caa7
L		 7222 else
7223 sign = 0;
520dc8e8 7224
29b0f896 7225 p = frag_more (size);
c3320543 7226 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7227
2bbd9c25
JJ		 7228 /* This is tough to explain. We end up with this one if we
7229 * have operands that look like
7230 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7231 * obtain the absolute address of the GOT, and it is strongly
7232 * preferable from a performance point of view to avoid using
7233 * a runtime relocation for this. The actual sequence of
7234 * instructions often look something like:
7235 *
7236 * call .L66
7237 * .L66:
7238 * popl %ebx
7239 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7240 *
7241 * The call and pop essentially return the absolute address
7242 * of the label .L66 and store it in %ebx. The linker itself
7243 * will ultimately change the first operand of the addl so
7244 * that %ebx points to the GOT, but to keep things simple, the
7245 * .o file must have this operand set so that it generates not
7246 * the absolute address of .L66, but the absolute address of
7247 * itself. This allows the linker itself simply treat a GOTPC
7248 * relocation as asking for a pcrel offset to the GOT to be
7249 * added in, and the addend of the relocation is stored in the
7250 * operand field for the instruction itself.
7251 *
7252 * Our job here is to fix the operand so that it would add
7253 * the correct offset so that %ebx would point to itself. The
7254 * thing that is tricky is that .-.L66 will point to the
7255 * beginning of the instruction, so we need to further modify
7256 * the operand so that it will point to itself. There are
7257 * other cases where you have something like:
7258 *
7259 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7260 *
7261 * and here no correction would be required. Internally in
7262 * the assembler we treat operands of this form as not being
7263 * pcrel since the '.' is explicitly mentioned, and I wonder
7264 * whether it would simplify matters to do it this way. Who
7265 * knows. In earlier versions of the PIC patches, the
7266 * pcrel_adjust field was used to store the correction, but
7267 * since the expression is not pcrel, I felt it would be
7268 * confusing to do it this way. */
7269
d6ab8113 7270 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7271 || reloc_type == BFD_RELOC_X86_64_32S
7272 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7273 && GOT_symbol
7274 && GOT_symbol == i.op[n].imms->X_add_symbol
7275 && (i.op[n].imms->X_op == O_symbol
7276 || (i.op[n].imms->X_op == O_add
7277 && ((symbol_get_value_expression
7278 (i.op[n].imms->X_op_symbol)->X_op)
7279 == O_subtract))))
7280 {
2bbd9c25
JJ		 7281 offsetT add;
7282
7283 if (insn_start_frag == frag_now)
7284 add = (p - frag_now->fr_literal) - insn_start_off;
7285 else
7286 {
7287 fragS *fr;
7288
7289 add = insn_start_frag->fr_fix - insn_start_off;
7290 for (fr = insn_start_frag->fr_next;
7291 fr && fr != frag_now; fr = fr->fr_next)
7292 add += fr->fr_fix;
7293 add += p - frag_now->fr_literal;
7294 }
7295
4fa24527 7296 if (!object_64bit)
d6ab8113 7297 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7298 else if (size == 4)
d6ab8113 7299 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7300 else if (size == 8)
7301 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7302 i.op[n].imms->X_add_number += add;
29b0f896 7303 }
29b0f896
AM		 7304 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7305 i.op[n].imms, 0, reloc_type);
7306 }
7307 }
7308 }
252b5132
RH		 7309}
7310\f
d182319b
JB		 7311/* x86_cons_fix_new is called via the expression parsing code when a
7312 reloc is needed. We use this hook to get the correct .got reloc. */
7313static enum bfd_reloc_code_real got_reloc = NO_RELOC;
7314static int cons_sign = -1;
7315
7316void
e3bb37b5 7317x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 7318 expressionS *exp)
d182319b 7319{
c3320543 7320 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, 0, got_reloc);
d182319b
JB		 7321
7322 got_reloc = NO_RELOC;
7323
7324#ifdef TE_PE
7325 if (exp->X_op == O_secrel)
7326 {
7327 exp->X_op = O_symbol;
7328 r = BFD_RELOC_32_SECREL;
7329 }
7330#endif
7331
7332 fix_new_exp (frag, off, len, exp, 0, r);
7333}
7334
357d1bd8
L		 7335/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7336 purpose of the `.dc.a' internal pseudo-op. */
7337
7338int
7339x86_address_bytes (void)
7340{
7341 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7342 return 4;
7343 return stdoutput->arch_info->bits_per_address / 8;
7344}
7345
d382c579
TG		 7346#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7347 || defined (LEX_AT)
718ddfc0
JB		 7348# define lex_got(reloc, adjust, types) NULL
7349#else
f3c180ae
AM		 7350/* Parse operands of the form
7351 <symbol>@GOTOFF+<nnn>
7352 and similar .plt or .got references.
7353
7354 If we find one, set up the correct relocation in RELOC and copy the
7355 input string, minus the `@GOTOFF' into a malloc'd buffer for
7356 parsing by the calling routine. Return this buffer, and if ADJUST
7357 is non-null set it to the length of the string we removed from the
7358 input line. Otherwise return NULL. */
7359static char *
91d6fa6a 7360lex_got (enum bfd_reloc_code_real *rel,
64e74474 7361 int *adjust,
c3320543
L		 7362 i386_operand_type *types,
7363 int bnd_prefix)
f3c180ae 7364{
7b81dfbb
AJ		 7365 /* Some of the relocations depend on the size of what field is to
7366 be relocated. But in our callers i386_immediate and i386_displacement
7367 we don't yet know the operand size (this will be set by insn
7368 matching). Hence we record the word32 relocation here,
7369 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7370 static const struct {
7371 const char *str;
cff8d58a 7372 int len;
4fa24527 7373 const enum bfd_reloc_code_real rel[2];
40fb9820 7374 const i386_operand_type types64;
f3c180ae 7375 } gotrel[] = {
8ce3d284 7376#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7377 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7378 BFD_RELOC_SIZE32 },
7379 OPERAND_TYPE_IMM32_64 },
8ce3d284 7380#endif
cff8d58a
L		 7381 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7382 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7383 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7384 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7385 BFD_RELOC_X86_64_PLT32 },
40fb9820 7386 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7387 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7388 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7389 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7390 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7391 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7392 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7393 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7394 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7395 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7396 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7397 BFD_RELOC_X86_64_TLSGD },
40fb9820 7398 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7399 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7400 _dummy_first_bfd_reloc_code_real },
40fb9820 7401 OPERAND_TYPE_NONE },
cff8d58a
L		 7402 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7403 BFD_RELOC_X86_64_TLSLD },
40fb9820 7404 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7405 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7406 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7407 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7408 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7409 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7410 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7411 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7412 _dummy_first_bfd_reloc_code_real },
40fb9820 7413 OPERAND_TYPE_NONE },
cff8d58a
L		 7414 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7415 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7416 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7417 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7418 _dummy_first_bfd_reloc_code_real },
40fb9820 7419 OPERAND_TYPE_NONE },
cff8d58a
L		 7420 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7421 _dummy_first_bfd_reloc_code_real },
40fb9820 7422 OPERAND_TYPE_NONE },
cff8d58a
L		 7423 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7424 BFD_RELOC_X86_64_GOT32 },
40fb9820 7425 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7426 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7427 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7428 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7429 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7430 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7431 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7432 };
7433 char *cp;
7434 unsigned int j;
7435
d382c579 7436#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7437 if (!IS_ELF)
7438 return NULL;
d382c579 7439#endif
718ddfc0 7440
f3c180ae 7441 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7442 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7443 return NULL;
7444
47465058 7445 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7446 {
cff8d58a 7447 int len = gotrel[j].len;
28f81592 7448 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7449 {
4fa24527 7450 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7451 {
28f81592
AM		 7452 int first, second;
7453 char *tmpbuf, *past_reloc;
f3c180ae 7454
91d6fa6a 7455 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7456
3956db08
JB		 7457 if (types)
7458 {
7459 if (flag_code != CODE_64BIT)
40fb9820
L		 7460 {
7461 types->bitfield.imm32 = 1;
7462 types->bitfield.disp32 = 1;
7463 }
3956db08
JB		 7464 else
7465 *types = gotrel[j].types64;
7466 }
7467
8fd4256d 7468 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7469 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7470
28f81592 7471 /* The length of the first part of our input line. */
f3c180ae 7472 first = cp - input_line_pointer;
28f81592
AM		 7473
7474 /* The second part goes from after the reloc token until
67c11a9b 7475 (and including) an end_of_line char or comma. */
28f81592 7476 past_reloc = cp + 1 + len;
67c11a9b
AM		 7477 cp = past_reloc;
7478 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7479 ++cp;
7480 second = cp + 1 - past_reloc;
28f81592
AM		 7481
7482 /* Allocate and copy string. The trailing NUL shouldn't
7483 be necessary, but be safe. */
1e9cc1c2 7484 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7485 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7486 if (second != 0 && *past_reloc != ' ')
7487 /* Replace the relocation token with ' ', so that
7488 errors like foo@GOTOFF1 will be detected. */
7489 tmpbuf[first++] = ' ';
af89796a
L		 7490 else
7491 /* Increment length by 1 if the relocation token is
7492 removed. */
7493 len++;
7494 if (adjust)
7495 *adjust = len;
0787a12d
AM		 7496 memcpy (tmpbuf + first, past_reloc, second);
7497 tmpbuf[first + second] = '\0';
c3320543
L		 7498 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7499 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7500 return tmpbuf;
7501 }
7502
4fa24527
JB		 7503 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7504 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7505 return NULL;
7506 }
7507 }
7508
7509 /* Might be a symbol version string. Don't as_bad here. */
7510 return NULL;
7511}
4e4f7c87 7512#endif
f3c180ae 7513
a988325c
NC		 7514#ifdef TE_PE
7515#ifdef lex_got
7516#undef lex_got
7517#endif
7518/* Parse operands of the form
7519 <symbol>@SECREL32+<nnn>
7520
7521 If we find one, set up the correct relocation in RELOC and copy the
7522 input string, minus the `@SECREL32' into a malloc'd buffer for
7523 parsing by the calling routine. Return this buffer, and if ADJUST
7524 is non-null set it to the length of the string we removed from the
34bca508
L		 7525 input line. Otherwise return NULL.
7526
a988325c
NC		 7527 This function is copied from the ELF version above adjusted for PE targets. */
7528
7529static char *
7530lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7531 int *adjust ATTRIBUTE_UNUSED,
7532 i386_operand_type *types ATTRIBUTE_UNUSED)
7533{
7534 static const struct
7535 {
7536 const char *str;
7537 int len;
7538 const enum bfd_reloc_code_real rel[2];
7539 const i386_operand_type types64;
7540 }
7541 gotrel[] =
7542 {
7543 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7544 BFD_RELOC_32_SECREL },
7545 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7546 };
7547
7548 char *cp;
7549 unsigned j;
7550
7551 for (cp = input_line_pointer; *cp != '@'; cp++)
7552 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7553 return NULL;
7554
7555 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7556 {
7557 int len = gotrel[j].len;
7558
7559 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7560 {
7561 if (gotrel[j].rel[object_64bit] != 0)
7562 {
7563 int first, second;
7564 char *tmpbuf, *past_reloc;
7565
7566 *rel = gotrel[j].rel[object_64bit];
7567 if (adjust)
7568 *adjust = len;
7569
7570 if (types)
7571 {
7572 if (flag_code != CODE_64BIT)
7573 {
7574 types->bitfield.imm32 = 1;
7575 types->bitfield.disp32 = 1;
7576 }
7577 else
7578 *types = gotrel[j].types64;
7579 }
7580
7581 /* The length of the first part of our input line. */
7582 first = cp - input_line_pointer;
7583
7584 /* The second part goes from after the reloc token until
7585 (and including) an end_of_line char or comma. */
7586 past_reloc = cp + 1 + len;
7587 cp = past_reloc;
7588 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7589 ++cp;
7590 second = cp + 1 - past_reloc;
7591
7592 /* Allocate and copy string. The trailing NUL shouldn't
7593 be necessary, but be safe. */
7594 tmpbuf = (char *) xmalloc (first + second + 2);
7595 memcpy (tmpbuf, input_line_pointer, first);
7596 if (second != 0 && *past_reloc != ' ')
7597 /* Replace the relocation token with ' ', so that
7598 errors like foo@SECLREL321 will be detected. */
7599 tmpbuf[first++] = ' ';
7600 memcpy (tmpbuf + first, past_reloc, second);
7601 tmpbuf[first + second] = '\0';
7602 return tmpbuf;
7603 }
7604
7605 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7606 gotrel[j].str, 1 << (5 + object_64bit));
7607 return NULL;
7608 }
7609 }
7610
7611 /* Might be a symbol version string. Don't as_bad here. */
7612 return NULL;
7613}
7614
7615#endif /* TE_PE */
7616
f3c180ae 7617void
e3bb37b5 7618x86_cons (expressionS *exp, int size)
f3c180ae 7619{
ee86248c
JB		 7620 intel_syntax = -intel_syntax;
7621
3c7b9c2c 7622 exp->X_md = 0;
4fa24527 7623 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7624 {
7625 /* Handle @GOTOFF and the like in an expression. */
7626 char *save;
7627 char *gotfree_input_line;
4a57f2cf 7628 int adjust = 0;
f3c180ae
AM		 7629
7630 save = input_line_pointer;
c3320543 7631 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7632 if (gotfree_input_line)
7633 input_line_pointer = gotfree_input_line;
7634
7635 expression (exp);
7636
7637 if (gotfree_input_line)
7638 {
7639 /* expression () has merrily parsed up to the end of line,
7640 or a comma - in the wrong buffer. Transfer how far
7641 input_line_pointer has moved to the right buffer. */
7642 input_line_pointer = (save
7643 + (input_line_pointer - gotfree_input_line)
7644 + adjust);
7645 free (gotfree_input_line);
3992d3b7
AM		 7646 if (exp->X_op == O_constant
7647 || exp->X_op == O_absent
7648 || exp->X_op == O_illegal
0398aac5 7649 || exp->X_op == O_register
3992d3b7
AM		 7650 || exp->X_op == O_big)
7651 {
7652 char c = *input_line_pointer;
7653 *input_line_pointer = 0;
7654 as_bad (_("missing or invalid expression `%s'"), save);
7655 *input_line_pointer = c;
7656 }
f3c180ae
AM		 7657 }
7658 }
7659 else
7660 expression (exp);
ee86248c
JB		 7661
7662 intel_syntax = -intel_syntax;
7663
7664 if (intel_syntax)
7665 i386_intel_simplify (exp);
f3c180ae 7666}
f3c180ae 7667
9f32dd5b
L		 7668static void
7669signed_cons (int size)
6482c264 7670{
d182319b
JB		 7671 if (flag_code == CODE_64BIT)
7672 cons_sign = 1;
7673 cons (size);
7674 cons_sign = -1;
6482c264
NC		 7675}
7676
d182319b 7677#ifdef TE_PE
6482c264 7678static void
7016a5d5 7679pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7680{
7681 expressionS exp;
7682
7683 do
7684 {
7685 expression (&exp);
7686 if (exp.X_op == O_symbol)
7687 exp.X_op = O_secrel;
7688
7689 emit_expr (&exp, 4);
7690 }
7691 while (*input_line_pointer++ == ',');
7692
7693 input_line_pointer--;
7694 demand_empty_rest_of_line ();
7695}
6482c264
NC		 7696#endif
7697
43234a1e
L		 7698/* Handle Vector operations. */
7699
7700static char *
7701check_VecOperations (char *op_string, char *op_end)
7702{
7703 const reg_entry *mask;
7704 const char *saved;
7705 char *end_op;
7706
7707 while (*op_string
7708 && (op_end == NULL || op_string < op_end))
7709 {
7710 saved = op_string;
7711 if (*op_string == '{')
7712 {
7713 op_string++;
7714
7715 /* Check broadcasts. */
7716 if (strncmp (op_string, "1to", 3) == 0)
7717 {
7718 int bcst_type;
7719
7720 if (i.broadcast)
7721 goto duplicated_vec_op;
7722
7723 op_string += 3;
7724 if (*op_string == '8')
7725 bcst_type = BROADCAST_1TO8;
7726 else if (*op_string == '1'
7727 && *(op_string+1) == '6')
7728 {
7729 bcst_type = BROADCAST_1TO16;
7730 op_string++;
7731 }
7732 else
7733 {
7734 as_bad (_("Unsupported broadcast: `%s'"), saved);
7735 return NULL;
7736 }
7737 op_string++;
7738
7739 broadcast_op.type = bcst_type;
7740 broadcast_op.operand = this_operand;
7741 i.broadcast = &broadcast_op;
7742 }
7743 /* Check masking operation. */
7744 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7745 {
7746 /* k0 can't be used for write mask. */
7747 if (mask->reg_num == 0)
7748 {
7749 as_bad (_("`%s' can't be used for write mask"),
7750 op_string);
7751 return NULL;
7752 }
7753
7754 if (!i.mask)
7755 {
7756 mask_op.mask = mask;
7757 mask_op.zeroing = 0;
7758 mask_op.operand = this_operand;
7759 i.mask = &mask_op;
7760 }
7761 else
7762 {
7763 if (i.mask->mask)
7764 goto duplicated_vec_op;
7765
7766 i.mask->mask = mask;
7767
7768 /* Only "{z}" is allowed here. No need to check
7769 zeroing mask explicitly. */
7770 if (i.mask->operand != this_operand)
7771 {
7772 as_bad (_("invalid write mask `%s'"), saved);
7773 return NULL;
7774 }
7775 }
7776
7777 op_string = end_op;
7778 }
7779 /* Check zeroing-flag for masking operation. */
7780 else if (*op_string == 'z')
7781 {
7782 if (!i.mask)
7783 {
7784 mask_op.mask = NULL;
7785 mask_op.zeroing = 1;
7786 mask_op.operand = this_operand;
7787 i.mask = &mask_op;
7788 }
7789 else
7790 {
7791 if (i.mask->zeroing)
7792 {
7793 duplicated_vec_op:
7794 as_bad (_("duplicated `%s'"), saved);
7795 return NULL;
7796 }
7797
7798 i.mask->zeroing = 1;
7799
7800 /* Only "{%k}" is allowed here. No need to check mask
7801 register explicitly. */
7802 if (i.mask->operand != this_operand)
7803 {
7804 as_bad (_("invalid zeroing-masking `%s'"),
7805 saved);
7806 return NULL;
7807 }
7808 }
7809
7810 op_string++;
7811 }
7812 else
7813 goto unknown_vec_op;
7814
7815 if (*op_string != '}')
7816 {
7817 as_bad (_("missing `}' in `%s'"), saved);
7818 return NULL;
7819 }
7820 op_string++;
7821 continue;
7822 }
7823 unknown_vec_op:
7824 /* We don't know this one. */
7825 as_bad (_("unknown vector operation: `%s'"), saved);
7826 return NULL;
7827 }
7828
7829 return op_string;
7830}
7831
252b5132 7832static int
70e41ade 7833i386_immediate (char *imm_start)
252b5132
RH		 7834{
7835 char *save_input_line_pointer;
f3c180ae 7836 char *gotfree_input_line;
252b5132 7837 segT exp_seg = 0;
47926f60 7838 expressionS *exp;
40fb9820
L		 7839 i386_operand_type types;
7840
0dfbf9d7 7841 operand_type_set (&types, ~0);
252b5132
RH		 7842
7843 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7844 {
31b2323c
L		 7845 as_bad (_("at most %d immediate operands are allowed"),
7846 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7847 return 0;
7848 }
7849
7850 exp = &im_expressions[i.imm_operands++];
520dc8e8 7851 i.op[this_operand].imms = exp;
252b5132
RH		 7852
7853 if (is_space_char (*imm_start))
7854 ++imm_start;
7855
7856 save_input_line_pointer = input_line_pointer;
7857 input_line_pointer = imm_start;
7858
c3320543
L		 7859 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7860 (i.bnd_prefix != NULL
7861 || add_bnd_prefix));
f3c180ae
AM		 7862 if (gotfree_input_line)
7863 input_line_pointer = gotfree_input_line;
252b5132
RH		 7864
7865 exp_seg = expression (exp);
7866
83183c0c 7867 SKIP_WHITESPACE ();
43234a1e
L		 7868
7869 /* Handle vector operations. */
7870 if (*input_line_pointer == '{')
7871 {
7872 input_line_pointer = check_VecOperations (input_line_pointer,
7873 NULL);
7874 if (input_line_pointer == NULL)
7875 return 0;
7876 }
7877
252b5132 7878 if (*input_line_pointer)
f3c180ae 7879 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7880
7881 input_line_pointer = save_input_line_pointer;
f3c180ae 7882 if (gotfree_input_line)
ee86248c
JB		 7883 {
7884 free (gotfree_input_line);
7885
7886 if (exp->X_op == O_constant || exp->X_op == O_register)
7887 exp->X_op = O_illegal;
7888 }
7889
7890 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7891}
252b5132 7892
ee86248c
JB		 7893static int
7894i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7895 i386_operand_type types, const char *imm_start)
7896{
7897 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7898 {
313c53d1
L		 7899 if (imm_start)
7900 as_bad (_("missing or invalid immediate expression `%s'"),
7901 imm_start);
3992d3b7 7902 return 0;
252b5132 7903 }
3e73aa7c 7904 else if (exp->X_op == O_constant)
252b5132 7905 {
47926f60 7906 /* Size it properly later. */
40fb9820 7907 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7908 /* If not 64bit, sign extend val. */
7909 if (flag_code != CODE_64BIT
4eed87de
AM		 7910 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7911 exp->X_add_number
7912 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7913 }
4c63da97 7914#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7915 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7916 && exp_seg != absolute_section
47926f60 7917 && exp_seg != text_section
24eab124
AM		 7918 && exp_seg != data_section
7919 && exp_seg != bss_section
7920 && exp_seg != undefined_section
f86103b7 7921 && !bfd_is_com_section (exp_seg))
252b5132 7922 {
d0b47220 7923 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7924 return 0;
7925 }
7926#endif
bb8f5920
L		 7927 else if (!intel_syntax && exp->X_op == O_register)
7928 {
313c53d1
L		 7929 if (imm_start)
7930 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7931 return 0;
7932 }
252b5132
RH		 7933 else
7934 {
7935 /* This is an address. The size of the address will be
24eab124 7936 determined later, depending on destination register,
3e73aa7c 7937 suffix, or the default for the section. */
40fb9820
L		 7938 i.types[this_operand].bitfield.imm8 = 1;
7939 i.types[this_operand].bitfield.imm16 = 1;
7940 i.types[this_operand].bitfield.imm32 = 1;
7941 i.types[this_operand].bitfield.imm32s = 1;
7942 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7943 i.types[this_operand] = operand_type_and (i.types[this_operand],
7944 types);
252b5132
RH		 7945 }
7946
7947 return 1;
7948}
7949
551c1ca1 7950static char *
e3bb37b5 7951i386_scale (char *scale)
252b5132 7952{
551c1ca1
AM		 7953 offsetT val;
7954 char *save = input_line_pointer;
252b5132 7955
551c1ca1
AM		 7956 input_line_pointer = scale;
7957 val = get_absolute_expression ();
7958
7959 switch (val)
252b5132 7960 {
551c1ca1 7961 case 1:
252b5132
RH		 7962 i.log2_scale_factor = 0;
7963 break;
551c1ca1 7964 case 2:
252b5132
RH		 7965 i.log2_scale_factor = 1;
7966 break;
551c1ca1 7967 case 4:
252b5132
RH		 7968 i.log2_scale_factor = 2;
7969 break;
551c1ca1 7970 case 8:
252b5132
RH		 7971 i.log2_scale_factor = 3;
7972 break;
7973 default:
a724f0f4
JB		 7974 {
7975 char sep = *input_line_pointer;
7976
7977 *input_line_pointer = '\0';
7978 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7979 scale);
7980 *input_line_pointer = sep;
7981 input_line_pointer = save;
7982 return NULL;
7983 }
252b5132 7984 }
29b0f896 7985 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7986 {
7987 as_warn (_("scale factor of %d without an index register"),
24eab124 7988 1 << i.log2_scale_factor);
252b5132 7989 i.log2_scale_factor = 0;
252b5132 7990 }
551c1ca1
AM		 7991 scale = input_line_pointer;
7992 input_line_pointer = save;
7993 return scale;
252b5132
RH		 7994}
7995
252b5132 7996static int
e3bb37b5 7997i386_displacement (char *disp_start, char *disp_end)
252b5132 7998{
29b0f896 7999 expressionS *exp;
252b5132
RH		 8000 segT exp_seg = 0;
8001 char *save_input_line_pointer;
f3c180ae 8002 char *gotfree_input_line;
40fb9820
L		 8003 int override;
8004 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8005 int ret;
252b5132 8006
31b2323c
L		 8007 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8008 {
8009 as_bad (_("at most %d displacement operands are allowed"),
8010 MAX_MEMORY_OPERANDS);
8011 return 0;
8012 }
8013
0dfbf9d7 8014 operand_type_set (&bigdisp, 0);
40fb9820
L		 8015 if ((i.types[this_operand].bitfield.jumpabsolute)
8016 || (!current_templates->start->opcode_modifier.jump
8017 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8018 {
40fb9820 8019 bigdisp.bitfield.disp32 = 1;
e05278af 8020 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8021 if (flag_code == CODE_64BIT)
8022 {
8023 if (!override)
8024 {
8025 bigdisp.bitfield.disp32s = 1;
8026 bigdisp.bitfield.disp64 = 1;
8027 }
8028 }
8029 else if ((flag_code == CODE_16BIT) ^ override)
8030 {
8031 bigdisp.bitfield.disp32 = 0;
8032 bigdisp.bitfield.disp16 = 1;
8033 }
e05278af
JB		 8034 }
8035 else
8036 {
8037 /* For PC-relative branches, the width of the displacement
8038 is dependent upon data size, not address size. */
e05278af 8039 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8040 if (flag_code == CODE_64BIT)
8041 {
8042 if (override || i.suffix == WORD_MNEM_SUFFIX)
8043 bigdisp.bitfield.disp16 = 1;
8044 else
8045 {
8046 bigdisp.bitfield.disp32 = 1;
8047 bigdisp.bitfield.disp32s = 1;
8048 }
8049 }
8050 else
e05278af
JB		 8051 {
8052 if (!override)
8053 override = (i.suffix == (flag_code != CODE_16BIT
8054 ? WORD_MNEM_SUFFIX
8055 : LONG_MNEM_SUFFIX));
40fb9820
L		 8056 bigdisp.bitfield.disp32 = 1;
8057 if ((flag_code == CODE_16BIT) ^ override)
8058 {
8059 bigdisp.bitfield.disp32 = 0;
8060 bigdisp.bitfield.disp16 = 1;
8061 }
e05278af 8062 }
e05278af 8063 }
c6fb90c8
L		 8064 i.types[this_operand] = operand_type_or (i.types[this_operand],
8065 bigdisp);
252b5132
RH		 8066
8067 exp = &disp_expressions[i.disp_operands];
520dc8e8 8068 i.op[this_operand].disps = exp;
252b5132
RH		 8069 i.disp_operands++;
8070 save_input_line_pointer = input_line_pointer;
8071 input_line_pointer = disp_start;
8072 END_STRING_AND_SAVE (disp_end);
8073
8074#ifndef GCC_ASM_O_HACK
8075#define GCC_ASM_O_HACK 0
8076#endif
8077#if GCC_ASM_O_HACK
8078 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8079 if (i.types[this_operand].bitfield.baseIndex
24eab124 8080 && displacement_string_end[-1] == '+')
252b5132
RH		 8081 {
8082 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8083 constraint within gcc asm statements.
8084 For instance:
8085
8086 #define _set_tssldt_desc(n,addr,limit,type) \
8087 __asm__ __volatile__ ( \
8088 "movw %w2,%0\n\t" \
8089 "movw %w1,2+%0\n\t" \
8090 "rorl $16,%1\n\t" \
8091 "movb %b1,4+%0\n\t" \
8092 "movb %4,5+%0\n\t" \
8093 "movb $0,6+%0\n\t" \
8094 "movb %h1,7+%0\n\t" \
8095 "rorl $16,%1" \
8096 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8097
8098 This works great except that the output assembler ends
8099 up looking a bit weird if it turns out that there is
8100 no offset. You end up producing code that looks like:
8101
8102 #APP
8103 movw $235,(%eax)
8104 movw %dx,2+(%eax)
8105 rorl $16,%edx
8106 movb %dl,4+(%eax)
8107 movb $137,5+(%eax)
8108 movb $0,6+(%eax)
8109 movb %dh,7+(%eax)
8110 rorl $16,%edx
8111 #NO_APP
8112
47926f60 8113 So here we provide the missing zero. */
24eab124
AM		 8114
8115 *displacement_string_end = '0';
252b5132
RH		 8116 }
8117#endif
c3320543
L		 8118 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8119 (i.bnd_prefix != NULL
8120 || add_bnd_prefix));
f3c180ae
AM		 8121 if (gotfree_input_line)
8122 input_line_pointer = gotfree_input_line;
252b5132 8123
24eab124 8124 exp_seg = expression (exp);
252b5132 8125
636c26b0
AM		 8126 SKIP_WHITESPACE ();
8127 if (*input_line_pointer)
8128 as_bad (_("junk `%s' after expression"), input_line_pointer);
8129#if GCC_ASM_O_HACK
8130 RESTORE_END_STRING (disp_end + 1);
8131#endif
636c26b0 8132 input_line_pointer = save_input_line_pointer;
636c26b0 8133 if (gotfree_input_line)
ee86248c
JB		 8134 {
8135 free (gotfree_input_line);
8136
8137 if (exp->X_op == O_constant || exp->X_op == O_register)
8138 exp->X_op = O_illegal;
8139 }
8140
8141 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8142
8143 RESTORE_END_STRING (disp_end);
8144
8145 return ret;
8146}
8147
8148static int
8149i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8150 i386_operand_type types, const char *disp_start)
8151{
8152 i386_operand_type bigdisp;
8153 int ret = 1;
636c26b0 8154
24eab124
AM		 8155 /* We do this to make sure that the section symbol is in
8156 the symbol table. We will ultimately change the relocation
47926f60 8157 to be relative to the beginning of the section. */
1ae12ab7 8158 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8159 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8160 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8161 {
636c26b0 8162 if (exp->X_op != O_symbol)
3992d3b7 8163 goto inv_disp;
636c26b0 8164
e5cb08ac 8165 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8166 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8167 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8168 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8169 exp->X_op = O_subtract;
8170 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8171 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8172 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8173 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8174 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8175 else
29b0f896 8176 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8177 }
252b5132 8178
3992d3b7
AM		 8179 else if (exp->X_op == O_absent
8180 || exp->X_op == O_illegal
ee86248c 8181 || exp->X_op == O_big)
2daf4fd8 8182 {
3992d3b7
AM		 8183 inv_disp:
8184 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8185 disp_start);
3992d3b7 8186 ret = 0;
2daf4fd8
AM		 8187 }
8188
0e1147d9
L		 8189 else if (flag_code == CODE_64BIT
8190 && !i.prefix[ADDR_PREFIX]
8191 && exp->X_op == O_constant)
8192 {
8193 /* Since displacement is signed extended to 64bit, don't allow
8194 disp32 and turn off disp32s if they are out of range. */
8195 i.types[this_operand].bitfield.disp32 = 0;
8196 if (!fits_in_signed_long (exp->X_add_number))
8197 {
8198 i.types[this_operand].bitfield.disp32s = 0;
8199 if (i.types[this_operand].bitfield.baseindex)
8200 {
8201 as_bad (_("0x%lx out range of signed 32bit displacement"),
8202 (long) exp->X_add_number);
8203 ret = 0;
8204 }
8205 }
8206 }
8207
4c63da97 8208#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8209 else if (exp->X_op != O_constant
8210 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8211 && exp_seg != absolute_section
8212 && exp_seg != text_section
8213 && exp_seg != data_section
8214 && exp_seg != bss_section
8215 && exp_seg != undefined_section
8216 && !bfd_is_com_section (exp_seg))
24eab124 8217 {
d0b47220 8218 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8219 ret = 0;
24eab124 8220 }
252b5132 8221#endif
3956db08 8222
40fb9820
L		 8223 /* Check if this is a displacement only operand. */
8224 bigdisp = i.types[this_operand];
8225 bigdisp.bitfield.disp8 = 0;
8226 bigdisp.bitfield.disp16 = 0;
8227 bigdisp.bitfield.disp32 = 0;
8228 bigdisp.bitfield.disp32s = 0;
8229 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8230 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8231 i.types[this_operand] = operand_type_and (i.types[this_operand],
8232 types);
3956db08 8233
3992d3b7 8234 return ret;
252b5132
RH		 8235}
8236
eecb386c 8237/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8238 Return 1 on success, 0 on a failure. */
8239
252b5132 8240static int
e3bb37b5 8241i386_index_check (const char *operand_string)
252b5132 8242{
fc0763e6 8243 const char *kind = "base/index";
be05d201
L		 8244 enum flag_code addr_mode;
8245
8246 if (i.prefix[ADDR_PREFIX])
8247 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8248 else
8249 {
8250 addr_mode = flag_code;
8251
24eab124 8252#if INFER_ADDR_PREFIX
be05d201
L		 8253 if (i.mem_operands == 0)
8254 {
8255 /* Infer address prefix from the first memory operand. */
8256 const reg_entry *addr_reg = i.base_reg;
8257
8258 if (addr_reg == NULL)
8259 addr_reg = i.index_reg;
eecb386c 8260
be05d201
L		 8261 if (addr_reg)
8262 {
8263 if (addr_reg->reg_num == RegEip
8264 || addr_reg->reg_num == RegEiz
8265 || addr_reg->reg_type.bitfield.reg32)
8266 addr_mode = CODE_32BIT;
8267 else if (flag_code != CODE_64BIT
8268 && addr_reg->reg_type.bitfield.reg16)
8269 addr_mode = CODE_16BIT;
8270
8271 if (addr_mode != flag_code)
8272 {
8273 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8274 i.prefixes += 1;
8275 /* Change the size of any displacement too. At most one
8276 of Disp16 or Disp32 is set.
8277 FIXME. There doesn't seem to be any real need for
8278 separate Disp16 and Disp32 flags. The same goes for
8279 Imm16 and Imm32. Removing them would probably clean
8280 up the code quite a lot. */
8281 if (flag_code != CODE_64BIT
8282 && (i.types[this_operand].bitfield.disp16
8283 || i.types[this_operand].bitfield.disp32))
8284 i.types[this_operand]
8285 = operand_type_xor (i.types[this_operand], disp16_32);
8286 }
8287 }
8288 }
24eab124 8289#endif
be05d201
L		 8290 }
8291
fc0763e6
JB		 8292 if (current_templates->start->opcode_modifier.isstring
8293 && !current_templates->start->opcode_modifier.immext
8294 && (current_templates->end[-1].opcode_modifier.isstring
8295 || i.mem_operands))
8296 {
8297 /* Memory operands of string insns are special in that they only allow
8298 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8299 const reg_entry *expected_reg;
8300 static const char *di_si[][2] =
8301 {
8302 { "esi", "edi" },
8303 { "si", "di" },
8304 { "rsi", "rdi" }
8305 };
8306 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8307
8308 kind = "string address";
8309
8310 if (current_templates->start->opcode_modifier.w)
8311 {
8312 i386_operand_type type = current_templates->end[-1].operand_types[0];
8313
8314 if (!type.bitfield.baseindex
8315 || ((!i.mem_operands != !intel_syntax)
8316 && current_templates->end[-1].operand_types[1]
8317 .bitfield.baseindex))
8318 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8319 expected_reg = hash_find (reg_hash,
8320 di_si[addr_mode][type.bitfield.esseg]);
8321
fc0763e6
JB		 8322 }
8323 else
be05d201 8324 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8325
be05d201
L		 8326 if (i.base_reg != expected_reg
8327 || i.index_reg
fc0763e6 8328 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8329 {
be05d201
L		 8330 /* The second memory operand must have the same size as
8331 the first one. */
8332 if (i.mem_operands
8333 && i.base_reg
8334 && !((addr_mode == CODE_64BIT
8335 && i.base_reg->reg_type.bitfield.reg64)
8336 || (addr_mode == CODE_32BIT
8337 ? i.base_reg->reg_type.bitfield.reg32
8338 : i.base_reg->reg_type.bitfield.reg16)))
8339 goto bad_address;
8340
fc0763e6
JB		 8341 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8342 operand_string,
8343 intel_syntax ? '[' : '(',
8344 register_prefix,
be05d201 8345 expected_reg->reg_name,
fc0763e6 8346 intel_syntax ? ']' : ')');
be05d201 8347 return 1;
fc0763e6 8348 }
be05d201
L		 8349 else
8350 return 1;
8351
8352bad_address:
8353 as_bad (_("`%s' is not a valid %s expression"),
8354 operand_string, kind);
8355 return 0;
3e73aa7c
JH		 8356 }
8357 else
8358 {
be05d201
L		 8359 if (addr_mode != CODE_16BIT)
8360 {
8361 /* 32-bit/64-bit checks. */
8362 if ((i.base_reg
8363 && (addr_mode == CODE_64BIT
8364 ? !i.base_reg->reg_type.bitfield.reg64
8365 : !i.base_reg->reg_type.bitfield.reg32)
8366 && (i.index_reg
8367 || (i.base_reg->reg_num
8368 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8369 || (i.index_reg
8370 && !i.index_reg->reg_type.bitfield.regxmm
8371 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8372 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8373 && ((addr_mode == CODE_64BIT
8374 ? !(i.index_reg->reg_type.bitfield.reg64
8375 || i.index_reg->reg_num == RegRiz)
8376 : !(i.index_reg->reg_type.bitfield.reg32
8377 || i.index_reg->reg_num == RegEiz))
8378 || !i.index_reg->reg_type.bitfield.baseindex)))
8379 goto bad_address;
8380 }
8381 else
3e73aa7c 8382 {
be05d201 8383 /* 16-bit checks. */
3e73aa7c 8384 if ((i.base_reg
40fb9820
L		 8385 && (!i.base_reg->reg_type.bitfield.reg16
8386 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8387 || (i.index_reg
40fb9820
L		 8388 && (!i.index_reg->reg_type.bitfield.reg16
8389 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8390 || !(i.base_reg
8391 && i.base_reg->reg_num < 6
8392 && i.index_reg->reg_num >= 6
8393 && i.log2_scale_factor == 0))))
be05d201 8394 goto bad_address;
3e73aa7c
JH		 8395 }
8396 }
be05d201 8397 return 1;
24eab124 8398}
252b5132 8399
43234a1e
L		 8400/* Handle vector immediates. */
8401
8402static int
8403RC_SAE_immediate (const char *imm_start)
8404{
8405 unsigned int match_found, j;
8406 const char *pstr = imm_start;
8407 expressionS *exp;
8408
8409 if (*pstr != '{')
8410 return 0;
8411
8412 pstr++;
8413 match_found = 0;
8414 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8415 {
8416 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8417 {
8418 if (!i.rounding)
8419 {
8420 rc_op.type = RC_NamesTable[j].type;
8421 rc_op.operand = this_operand;
8422 i.rounding = &rc_op;
8423 }
8424 else
8425 {
8426 as_bad (_("duplicated `%s'"), imm_start);
8427 return 0;
8428 }
8429 pstr += RC_NamesTable[j].len;
8430 match_found = 1;
8431 break;
8432 }
8433 }
8434 if (!match_found)
8435 return 0;
8436
8437 if (*pstr++ != '}')
8438 {
8439 as_bad (_("Missing '}': '%s'"), imm_start);
8440 return 0;
8441 }
8442 /* RC/SAE immediate string should contain nothing more. */;
8443 if (*pstr != 0)
8444 {
8445 as_bad (_("Junk after '}': '%s'"), imm_start);
8446 return 0;
8447 }
8448
8449 exp = &im_expressions[i.imm_operands++];
8450 i.op[this_operand].imms = exp;
8451
8452 exp->X_op = O_constant;
8453 exp->X_add_number = 0;
8454 exp->X_add_symbol = (symbolS *) 0;
8455 exp->X_op_symbol = (symbolS *) 0;
8456
8457 i.types[this_operand].bitfield.imm8 = 1;
8458 return 1;
8459}
8460
fc0763e6 8461/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8462 on error. */
252b5132 8463
252b5132 8464static int
a7619375 8465i386_att_operand (char *operand_string)
252b5132 8466{
af6bdddf
AM		 8467 const reg_entry *r;
8468 char *end_op;
24eab124 8469 char *op_string = operand_string;
252b5132 8470
24eab124 8471 if (is_space_char (*op_string))
252b5132
RH		 8472 ++op_string;
8473
24eab124 8474 /* We check for an absolute prefix (differentiating,
47926f60 8475 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8476 if (*op_string == ABSOLUTE_PREFIX)
8477 {
8478 ++op_string;
8479 if (is_space_char (*op_string))
8480 ++op_string;
40fb9820 8481 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8482 }
252b5132 8483
47926f60 8484 /* Check if operand is a register. */
4d1bb795 8485 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8486 {
40fb9820
L		 8487 i386_operand_type temp;
8488
24eab124
AM		 8489 /* Check for a segment override by searching for ':' after a
8490 segment register. */
8491 op_string = end_op;
8492 if (is_space_char (*op_string))
8493 ++op_string;
40fb9820
L		 8494 if (*op_string == ':'
8495 && (r->reg_type.bitfield.sreg2
8496 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8497 {
8498 switch (r->reg_num)
8499 {
8500 case 0:
8501 i.seg[i.mem_operands] = &es;
8502 break;
8503 case 1:
8504 i.seg[i.mem_operands] = &cs;
8505 break;
8506 case 2:
8507 i.seg[i.mem_operands] = &ss;
8508 break;
8509 case 3:
8510 i.seg[i.mem_operands] = &ds;
8511 break;
8512 case 4:
8513 i.seg[i.mem_operands] = &fs;
8514 break;
8515 case 5:
8516 i.seg[i.mem_operands] = &gs;
8517 break;
8518 }
252b5132 8519
24eab124 8520 /* Skip the ':' and whitespace. */
252b5132
RH		 8521 ++op_string;
8522 if (is_space_char (*op_string))
24eab124 8523 ++op_string;
252b5132 8524
24eab124
AM		 8525 if (!is_digit_char (*op_string)
8526 && !is_identifier_char (*op_string)
8527 && *op_string != '('
8528 && *op_string != ABSOLUTE_PREFIX)
8529 {
8530 as_bad (_("bad memory operand `%s'"), op_string);
8531 return 0;
8532 }
47926f60 8533 /* Handle case of %es:*foo. */
24eab124
AM		 8534 if (*op_string == ABSOLUTE_PREFIX)
8535 {
8536 ++op_string;
8537 if (is_space_char (*op_string))
8538 ++op_string;
40fb9820 8539 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8540 }
8541 goto do_memory_reference;
8542 }
43234a1e
L		 8543
8544 /* Handle vector operations. */
8545 if (*op_string == '{')
8546 {
8547 op_string = check_VecOperations (op_string, NULL);
8548 if (op_string == NULL)
8549 return 0;
8550 }
8551
24eab124
AM		 8552 if (*op_string)
8553 {
d0b47220 8554 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8555 return 0;
8556 }
40fb9820
L		 8557 temp = r->reg_type;
8558 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8559 i.types[this_operand] = operand_type_or (i.types[this_operand],
8560 temp);
7d5e4556 8561 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8562 i.op[this_operand].regs = r;
24eab124
AM		 8563 i.reg_operands++;
8564 }
af6bdddf
AM		 8565 else if (*op_string == REGISTER_PREFIX)
8566 {
8567 as_bad (_("bad register name `%s'"), op_string);
8568 return 0;
8569 }
24eab124 8570 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8571 {
24eab124 8572 ++op_string;
40fb9820 8573 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8574 {
d0b47220 8575 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8576 return 0;
8577 }
8578 if (!i386_immediate (op_string))
8579 return 0;
8580 }
43234a1e
L		 8581 else if (RC_SAE_immediate (operand_string))
8582 {
8583 /* If it is a RC or SAE immediate, do nothing. */
8584 ;
8585 }
24eab124
AM		 8586 else if (is_digit_char (*op_string)
8587 || is_identifier_char (*op_string)
e5cb08ac 8588 || *op_string == '(')
24eab124 8589 {
47926f60 8590 /* This is a memory reference of some sort. */
af6bdddf 8591 char *base_string;
252b5132 8592
47926f60 8593 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8594 char *displacement_string_start;
8595 char *displacement_string_end;
43234a1e 8596 char *vop_start;
252b5132 8597
24eab124 8598 do_memory_reference:
24eab124 8599 if ((i.mem_operands == 1
40fb9820 8600 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8601 || i.mem_operands == 2)
8602 {
8603 as_bad (_("too many memory references for `%s'"),
8604 current_templates->start->name);
8605 return 0;
8606 }
252b5132 8607
24eab124
AM		 8608 /* Check for base index form. We detect the base index form by
8609 looking for an ')' at the end of the operand, searching
8610 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8611 after the '('. */
af6bdddf 8612 base_string = op_string + strlen (op_string);
c3332e24 8613
43234a1e
L		 8614 /* Handle vector operations. */
8615 vop_start = strchr (op_string, '{');
8616 if (vop_start && vop_start < base_string)
8617 {
8618 if (check_VecOperations (vop_start, base_string) == NULL)
8619 return 0;
8620 base_string = vop_start;
8621 }
8622
af6bdddf
AM		 8623 --base_string;
8624 if (is_space_char (*base_string))
8625 --base_string;
252b5132 8626
47926f60 8627 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8628 displacement_string_start = op_string;
8629 displacement_string_end = base_string + 1;
252b5132 8630
24eab124
AM		 8631 if (*base_string == ')')
8632 {
af6bdddf 8633 char *temp_string;
24eab124
AM		 8634 unsigned int parens_balanced = 1;
8635 /* We've already checked that the number of left & right ()'s are
47926f60 8636 equal, so this loop will not be infinite. */
24eab124
AM		 8637 do
8638 {
8639 base_string--;
8640 if (*base_string == ')')
8641 parens_balanced++;
8642 if (*base_string == '(')
8643 parens_balanced--;
8644 }
8645 while (parens_balanced);
c3332e24 8646
af6bdddf 8647 temp_string = base_string;
c3332e24 8648
24eab124 8649 /* Skip past '(' and whitespace. */
252b5132
RH		 8650 ++base_string;
8651 if (is_space_char (*base_string))
24eab124 8652 ++base_string;
252b5132 8653
af6bdddf 8654 if (*base_string == ','
4eed87de
AM		 8655 || ((i.base_reg = parse_register (base_string, &end_op))
8656 != NULL))
252b5132 8657 {
af6bdddf 8658 displacement_string_end = temp_string;
252b5132 8659
40fb9820 8660 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8661
af6bdddf 8662 if (i.base_reg)
24eab124 8663 {
24eab124
AM		 8664 base_string = end_op;
8665 if (is_space_char (*base_string))
8666 ++base_string;
af6bdddf
AM		 8667 }
8668
8669 /* There may be an index reg or scale factor here. */
8670 if (*base_string == ',')
8671 {
8672 ++base_string;
8673 if (is_space_char (*base_string))
8674 ++base_string;
8675
4eed87de
AM		 8676 if ((i.index_reg = parse_register (base_string, &end_op))
8677 != NULL)
24eab124 8678 {
af6bdddf 8679 base_string = end_op;
24eab124
AM		 8680 if (is_space_char (*base_string))
8681 ++base_string;
af6bdddf
AM		 8682 if (*base_string == ',')
8683 {
8684 ++base_string;
8685 if (is_space_char (*base_string))
8686 ++base_string;
8687 }
e5cb08ac 8688 else if (*base_string != ')')
af6bdddf 8689 {
4eed87de
AM		 8690 as_bad (_("expecting `,' or `)' "
8691 "after index register in `%s'"),
af6bdddf
AM		 8692 operand_string);
8693 return 0;
8694 }
24eab124 8695 }
af6bdddf 8696 else if (*base_string == REGISTER_PREFIX)
24eab124 8697 {
f76bf5e0
L		 8698 end_op = strchr (base_string, ',');
8699 if (end_op)
8700 *end_op = '\0';
af6bdddf 8701 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8702 return 0;
8703 }
252b5132 8704
47926f60 8705 /* Check for scale factor. */
551c1ca1 8706 if (*base_string != ')')
af6bdddf 8707 {
551c1ca1
AM		 8708 char *end_scale = i386_scale (base_string);
8709
8710 if (!end_scale)
af6bdddf 8711 return 0;
24eab124 8712
551c1ca1 8713 base_string = end_scale;
af6bdddf
AM		 8714 if (is_space_char (*base_string))
8715 ++base_string;
8716 if (*base_string != ')')
8717 {
4eed87de
AM		 8718 as_bad (_("expecting `)' "
8719 "after scale factor in `%s'"),
af6bdddf
AM		 8720 operand_string);
8721 return 0;
8722 }
8723 }
8724 else if (!i.index_reg)
24eab124 8725 {
4eed87de
AM		 8726 as_bad (_("expecting index register or scale factor "
8727 "after `,'; got '%c'"),
af6bdddf 8728 *base_string);
24eab124
AM		 8729 return 0;
8730 }
8731 }
af6bdddf 8732 else if (*base_string != ')')
24eab124 8733 {
4eed87de
AM		 8734 as_bad (_("expecting `,' or `)' "
8735 "after base register in `%s'"),
af6bdddf 8736 operand_string);
24eab124
AM		 8737 return 0;
8738 }
c3332e24 8739 }
af6bdddf 8740 else if (*base_string == REGISTER_PREFIX)
c3332e24 8741 {
f76bf5e0
L		 8742 end_op = strchr (base_string, ',');
8743 if (end_op)
8744 *end_op = '\0';
af6bdddf 8745 as_bad (_("bad register name `%s'"), base_string);
24eab124 8746 return 0;
c3332e24 8747 }
24eab124
AM		 8748 }
8749
8750 /* If there's an expression beginning the operand, parse it,
8751 assuming displacement_string_start and
8752 displacement_string_end are meaningful. */
8753 if (displacement_string_start != displacement_string_end)
8754 {
8755 if (!i386_displacement (displacement_string_start,
8756 displacement_string_end))
8757 return 0;
8758 }
8759
8760 /* Special case for (%dx) while doing input/output op. */
8761 if (i.base_reg
0dfbf9d7
L		 8762 && operand_type_equal (&i.base_reg->reg_type,
8763 &reg16_inoutportreg)
24eab124
AM		 8764 && i.index_reg == 0
8765 && i.log2_scale_factor == 0
8766 && i.seg[i.mem_operands] == 0
40fb9820 8767 && !operand_type_check (i.types[this_operand], disp))
24eab124 8768 {
65da13b5 8769 i.types[this_operand] = inoutportreg;
24eab124
AM		 8770 return 1;
8771 }
8772
eecb386c
AM		 8773 if (i386_index_check (operand_string) == 0)
8774 return 0;
5c07affc 8775 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8776 i.mem_operands++;
8777 }
8778 else
ce8a8b2f
AM		 8779 {
8780 /* It's not a memory operand; argh! */
24eab124
AM		 8781 as_bad (_("invalid char %s beginning operand %d `%s'"),
8782 output_invalid (*op_string),
8783 this_operand + 1,
8784 op_string);
8785 return 0;
8786 }
47926f60 8787 return 1; /* Normal return. */
252b5132
RH		 8788}
8789\f
fa94de6b
RM		 8790/* Calculate the maximum variable size (i.e., excluding fr_fix)
8791 that an rs_machine_dependent frag may reach. */
8792
8793unsigned int
8794i386_frag_max_var (fragS *frag)
8795{
8796 /* The only relaxable frags are for jumps.
8797 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8798 gas_assert (frag->fr_type == rs_machine_dependent);
8799 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8800}
8801
ee7fcc42
AM		 8802/* md_estimate_size_before_relax()
8803
8804 Called just before relax() for rs_machine_dependent frags. The x86
8805 assembler uses these frags to handle variable size jump
8806 instructions.
8807
8808 Any symbol that is now undefined will not become defined.
8809 Return the correct fr_subtype in the frag.
8810 Return the initial "guess for variable size of frag" to caller.
8811 The guess is actually the growth beyond the fixed part. Whatever
8812 we do to grow the fixed or variable part contributes to our
8813 returned value. */
8814
252b5132 8815int
7016a5d5 8816md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8817{
252b5132 8818 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8819 check for un-relaxable symbols. On an ELF system, we can't relax
8820 an externally visible symbol, because it may be overridden by a
8821 shared library. */
8822 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8823#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8824 || (IS_ELF
31312f95 8825 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8826 || S_IS_WEAK (fragP->fr_symbol)
8827 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8828 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8829#endif
8830#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8831 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8832 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8833#endif
8834 )
252b5132 8835 {
b98ef147
AM		 8836 /* Symbol is undefined in this segment, or we need to keep a
8837 reloc so that weak symbols can be overridden. */
8838 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8839 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8840 unsigned char *opcode;
8841 int old_fr_fix;
f6af82bd 8842
ee7fcc42 8843 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8844 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8845 else if (size == 2)
f6af82bd
AM		 8846 reloc_type = BFD_RELOC_16_PCREL;
8847 else
8848 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8849
ee7fcc42
AM		 8850 old_fr_fix = fragP->fr_fix;
8851 opcode = (unsigned char *) fragP->fr_opcode;
8852
fddf5b5b 8853 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8854 {
fddf5b5b
AM		 8855 case UNCOND_JUMP:
8856 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8857 opcode[0] = 0xe9;
252b5132 8858 fragP->fr_fix += size;
062cd5e7
AS		 8859 fix_new (fragP, old_fr_fix, size,
8860 fragP->fr_symbol,
8861 fragP->fr_offset, 1,
8862 reloc_type);
252b5132
RH		 8863 break;
8864
fddf5b5b 8865 case COND_JUMP86:
412167cb
AM		 8866 if (size == 2
8867 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8868 {
8869 /* Negate the condition, and branch past an
8870 unconditional jump. */
8871 opcode[0] ^= 1;
8872 opcode[1] = 3;
8873 /* Insert an unconditional jump. */
8874 opcode[2] = 0xe9;
8875 /* We added two extra opcode bytes, and have a two byte
8876 offset. */
8877 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8878 fix_new (fragP, old_fr_fix + 2, 2,
8879 fragP->fr_symbol,
8880 fragP->fr_offset, 1,
8881 reloc_type);
fddf5b5b
AM		 8882 break;
8883 }
8884 /* Fall through. */
8885
8886 case COND_JUMP:
412167cb
AM		 8887 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8888 {
3e02c1cc
AM		 8889 fixS *fixP;
8890
412167cb 8891 fragP->fr_fix += 1;
3e02c1cc
AM		 8892 fixP = fix_new (fragP, old_fr_fix, 1,
8893 fragP->fr_symbol,
8894 fragP->fr_offset, 1,
8895 BFD_RELOC_8_PCREL);
8896 fixP->fx_signed = 1;
412167cb
AM		 8897 break;
8898 }
93c2a809 8899
24eab124 8900 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8901 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8902 opcode[1] = opcode[0] + 0x10;
f6af82bd 8903 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8904 /* We've added an opcode byte. */
8905 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8906 fix_new (fragP, old_fr_fix + 1, size,
8907 fragP->fr_symbol,
8908 fragP->fr_offset, 1,
8909 reloc_type);
252b5132 8910 break;
fddf5b5b
AM		 8911
8912 default:
8913 BAD_CASE (fragP->fr_subtype);
8914 break;
252b5132
RH		 8915 }
8916 frag_wane (fragP);
ee7fcc42 8917 return fragP->fr_fix - old_fr_fix;
252b5132 8918 }
93c2a809 8919
93c2a809
AM		 8920 /* Guess size depending on current relax state. Initially the relax
8921 state will correspond to a short jump and we return 1, because
8922 the variable part of the frag (the branch offset) is one byte
8923 long. However, we can relax a section more than once and in that
8924 case we must either set fr_subtype back to the unrelaxed state,
8925 or return the value for the appropriate branch. */
8926 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8927}
8928
47926f60
KH		 8929/* Called after relax() is finished.
8930
8931 In: Address of frag.
8932 fr_type == rs_machine_dependent.
8933 fr_subtype is what the address relaxed to.
8934
8935 Out: Any fixSs and constants are set up.
8936 Caller will turn frag into a ".space 0". */
8937
252b5132 8938void
7016a5d5
TG		 8939md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8940 fragS *fragP)
252b5132 8941{
29b0f896 8942 unsigned char *opcode;
252b5132 8943 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8944 offsetT target_address;
8945 offsetT opcode_address;
252b5132 8946 unsigned int extension = 0;
847f7ad4 8947 offsetT displacement_from_opcode_start;
252b5132
RH		 8948
8949 opcode = (unsigned char *) fragP->fr_opcode;
8950
47926f60 8951 /* Address we want to reach in file space. */
252b5132 8952 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8953
47926f60 8954 /* Address opcode resides at in file space. */
252b5132
RH		 8955 opcode_address = fragP->fr_address + fragP->fr_fix;
8956
47926f60 8957 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8958 displacement_from_opcode_start = target_address - opcode_address;
8959
fddf5b5b 8960 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8961 {
47926f60
KH		 8962 /* Don't have to change opcode. */
8963 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8964 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8965 }
8966 else
8967 {
8968 if (no_cond_jump_promotion
8969 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8970 as_warn_where (fragP->fr_file, fragP->fr_line,
8971 _("long jump required"));
252b5132 8972
fddf5b5b
AM		 8973 switch (fragP->fr_subtype)
8974 {
8975 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8976 extension = 4; /* 1 opcode + 4 displacement */
8977 opcode[0] = 0xe9;
8978 where_to_put_displacement = &opcode[1];
8979 break;
252b5132 8980
fddf5b5b
AM		 8981 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8982 extension = 2; /* 1 opcode + 2 displacement */
8983 opcode[0] = 0xe9;
8984 where_to_put_displacement = &opcode[1];
8985 break;
252b5132 8986
fddf5b5b
AM		 8987 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8988 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8989 extension = 5; /* 2 opcode + 4 displacement */
8990 opcode[1] = opcode[0] + 0x10;
8991 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8992 where_to_put_displacement = &opcode[2];
8993 break;
252b5132 8994
fddf5b5b
AM		 8995 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8996 extension = 3; /* 2 opcode + 2 displacement */
8997 opcode[1] = opcode[0] + 0x10;
8998 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8999 where_to_put_displacement = &opcode[2];
9000 break;
252b5132 9001
fddf5b5b
AM		 9002 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9003 extension = 4;
9004 opcode[0] ^= 1;
9005 opcode[1] = 3;
9006 opcode[2] = 0xe9;
9007 where_to_put_displacement = &opcode[3];
9008 break;
9009
9010 default:
9011 BAD_CASE (fragP->fr_subtype);
9012 break;
9013 }
252b5132 9014 }
fddf5b5b 9015
7b81dfbb
AJ		 9016 /* If size if less then four we are sure that the operand fits,
9017 but if it's 4, then it could be that the displacement is larger
9018 then -/+ 2GB. */
9019 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9020 && object_64bit
9021 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9022 + ((addressT) 1 << 31))
9023 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9024 {
9025 as_bad_where (fragP->fr_file, fragP->fr_line,
9026 _("jump target out of range"));
9027 /* Make us emit 0. */
9028 displacement_from_opcode_start = extension;
9029 }
47926f60 9030 /* Now put displacement after opcode. */
252b5132
RH		 9031 md_number_to_chars ((char *) where_to_put_displacement,
9032 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9033 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9034 fragP->fr_fix += extension;
9035}
9036\f
7016a5d5 9037/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9038 by our caller that we have all the info we need to fix it up.
9039
7016a5d5
TG		 9040 Parameter valP is the pointer to the value of the bits.
9041
252b5132
RH		 9042 On the 386, immediates, displacements, and data pointers are all in
9043 the same (little-endian) format, so we don't need to care about which
9044 we are handling. */
9045
94f592af 9046void
7016a5d5 9047md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9048{
94f592af 9049 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9050 valueT value = *valP;
252b5132 9051
f86103b7 9052#if !defined (TE_Mach)
93382f6d
AM		 9053 if (fixP->fx_pcrel)
9054 {
9055 switch (fixP->fx_r_type)
9056 {
5865bb77
ILT		 9057 default:
9058 break;
9059
d6ab8113
JB		 9060 case BFD_RELOC_64:
9061 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9062 break;
93382f6d 9063 case BFD_RELOC_32:
ae8887b5 9064 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9065 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9066 break;
9067 case BFD_RELOC_16:
9068 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9069 break;
9070 case BFD_RELOC_8:
9071 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9072 break;
9073 }
9074 }
252b5132 9075
a161fe53 9076 if (fixP->fx_addsy != NULL
31312f95 9077 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9078 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9079 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9080 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9081 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9082 && !use_rela_relocations)
252b5132 9083 {
31312f95
AM		 9084 /* This is a hack. There should be a better way to handle this.
9085 This covers for the fact that bfd_install_relocation will
9086 subtract the current location (for partial_inplace, PC relative
9087 relocations); see more below. */
252b5132 9088#ifndef OBJ_AOUT
718ddfc0 9089 if (IS_ELF
252b5132
RH		 9090#ifdef TE_PE
9091 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9092#endif
9093 )
9094 value += fixP->fx_where + fixP->fx_frag->fr_address;
9095#endif
9096#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9097 if (IS_ELF)
252b5132 9098 {
6539b54b 9099 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9100
6539b54b 9101 if ((sym_seg == seg
2f66722d 9102 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9103 && sym_seg != absolute_section))
af65af87 9104 && !generic_force_reloc (fixP))
2f66722d
AM		 9105 {
9106 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9107 bfd_install_relocation subtracts them out again. I think
9108 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9109 it. FIXME. */
9110 value += fixP->fx_where + fixP->fx_frag->fr_address;
9111 }
252b5132
RH		 9112 }
9113#endif
9114#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9115 /* For some reason, the PE format does not store a
9116 section address offset for a PC relative symbol. */
9117 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9118 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9119 value += md_pcrel_from (fixP);
9120#endif
9121 }
fbeb56a4
DK		 9122#if defined (OBJ_COFF) && defined (TE_PE)
9123 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9124 {
9125 value -= S_GET_VALUE (fixP->fx_addsy);
9126 }
9127#endif
252b5132
RH		 9128
9129 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9130 and we must not disappoint it. */
252b5132 9131#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9132 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9133 switch (fixP->fx_r_type)
9134 {
9135 case BFD_RELOC_386_PLT32:
3e73aa7c 9136 case BFD_RELOC_X86_64_PLT32:
c3320543 9137 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9138 /* Make the jump instruction point to the address of the operand. At
9139 runtime we merely add the offset to the actual PLT entry. */
9140 value = -4;
9141 break;
31312f95 9142
13ae64f3
JJ		 9143 case BFD_RELOC_386_TLS_GD:
9144 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9145 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9146 case BFD_RELOC_386_TLS_IE:
9147 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9148 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9149 case BFD_RELOC_X86_64_TLSGD:
9150 case BFD_RELOC_X86_64_TLSLD:
9151 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9152 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9153 value = 0; /* Fully resolved at runtime. No addend. */
9154 /* Fallthrough */
9155 case BFD_RELOC_386_TLS_LE:
9156 case BFD_RELOC_386_TLS_LDO_32:
9157 case BFD_RELOC_386_TLS_LE_32:
9158 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9159 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9160 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9161 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9162 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9163 break;
9164
67a4f2b7
AO		 9165 case BFD_RELOC_386_TLS_DESC_CALL:
9166 case BFD_RELOC_X86_64_TLSDESC_CALL:
9167 value = 0; /* Fully resolved at runtime. No addend. */
9168 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9169 fixP->fx_done = 0;
9170 return;
9171
00f7efb6
JJ		 9172 case BFD_RELOC_386_GOT32:
9173 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9174 value = 0; /* Fully resolved at runtime. No addend. */
9175 break;
47926f60
KH		 9176
9177 case BFD_RELOC_VTABLE_INHERIT:
9178 case BFD_RELOC_VTABLE_ENTRY:
9179 fixP->fx_done = 0;
94f592af 9180 return;
47926f60
KH		 9181
9182 default:
9183 break;
9184 }
9185#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9186 *valP = value;
f86103b7 9187#endif /* !defined (TE_Mach) */
3e73aa7c 9188
3e73aa7c 9189 /* Are we finished with this relocation now? */
c6682705 9190 if (fixP->fx_addsy == NULL)
3e73aa7c 9191 fixP->fx_done = 1;
fbeb56a4
DK		 9192#if defined (OBJ_COFF) && defined (TE_PE)
9193 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9194 {
9195 fixP->fx_done = 0;
9196 /* Remember value for tc_gen_reloc. */
9197 fixP->fx_addnumber = value;
9198 /* Clear out the frag for now. */
9199 value = 0;
9200 }
9201#endif
3e73aa7c
JH		 9202 else if (use_rela_relocations)
9203 {
9204 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9205 /* Remember value for tc_gen_reloc. */
9206 fixP->fx_addnumber = value;
3e73aa7c
JH		 9207 value = 0;
9208 }
f86103b7 9209
94f592af 9210 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9211}
252b5132 9212\f
252b5132 9213char *
499ac353 9214md_atof (int type, char *litP, int *sizeP)
252b5132 9215{
499ac353
NC		 9216 /* This outputs the LITTLENUMs in REVERSE order;
9217 in accord with the bigendian 386. */
9218 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9219}
9220\f
2d545b82 9221static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9222
252b5132 9223static char *
e3bb37b5 9224output_invalid (int c)
252b5132 9225{
3882b010 9226 if (ISPRINT (c))
f9f21a03
L		 9227 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9228 "'%c'", c);
252b5132 9229 else
f9f21a03 9230 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9231 "(0x%x)", (unsigned char) c);
252b5132
RH		 9232 return output_invalid_buf;
9233}
9234
af6bdddf 9235/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9236
9237static const reg_entry *
4d1bb795 9238parse_real_register (char *reg_string, char **end_op)
252b5132 9239{
af6bdddf
AM		 9240 char *s = reg_string;
9241 char *p;
252b5132
RH		 9242 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9243 const reg_entry *r;
9244
9245 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9246 if (*s == REGISTER_PREFIX)
9247 ++s;
9248
9249 if (is_space_char (*s))
9250 ++s;
9251
9252 p = reg_name_given;
af6bdddf 9253 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9254 {
9255 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9256 return (const reg_entry *) NULL;
9257 s++;
252b5132
RH		 9258 }
9259
6588847e
DN		 9260 /* For naked regs, make sure that we are not dealing with an identifier.
9261 This prevents confusing an identifier like `eax_var' with register
9262 `eax'. */
9263 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9264 return (const reg_entry *) NULL;
9265
af6bdddf 9266 *end_op = s;
252b5132
RH		 9267
9268 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9269
5f47d35b 9270 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9271 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9272 {
5f47d35b
AM		 9273 if (is_space_char (*s))
9274 ++s;
9275 if (*s == '(')
9276 {
af6bdddf 9277 ++s;
5f47d35b
AM		 9278 if (is_space_char (*s))
9279 ++s;
9280 if (*s >= '0' && *s <= '7')
9281 {
db557034 9282 int fpr = *s - '0';
af6bdddf 9283 ++s;
5f47d35b
AM		 9284 if (is_space_char (*s))
9285 ++s;
9286 if (*s == ')')
9287 {
9288 *end_op = s + 1;
1e9cc1c2 9289 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9290 know (r);
9291 return r + fpr;
5f47d35b 9292 }
5f47d35b 9293 }
47926f60 9294 /* We have "%st(" then garbage. */
5f47d35b
AM		 9295 return (const reg_entry *) NULL;
9296 }
9297 }
9298
a60de03c
JB		 9299 if (r == NULL || allow_pseudo_reg)
9300 return r;
9301
0dfbf9d7 9302 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9303 return (const reg_entry *) NULL;
9304
192dc9c6
JB		 9305 if ((r->reg_type.bitfield.reg32
9306 || r->reg_type.bitfield.sreg3
9307 || r->reg_type.bitfield.control
9308 || r->reg_type.bitfield.debug
9309 || r->reg_type.bitfield.test)
9310 && !cpu_arch_flags.bitfield.cpui386)
9311 return (const reg_entry *) NULL;
9312
309d3373
JB		 9313 if (r->reg_type.bitfield.floatreg
9314 && !cpu_arch_flags.bitfield.cpu8087
9315 && !cpu_arch_flags.bitfield.cpu287
9316 && !cpu_arch_flags.bitfield.cpu387)
9317 return (const reg_entry *) NULL;
9318
192dc9c6
JB		 9319 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9320 return (const reg_entry *) NULL;
9321
9322 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9323 return (const reg_entry *) NULL;
9324
40f12533
L		 9325 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9326 return (const reg_entry *) NULL;
9327
43234a1e
L		 9328 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9329 && !cpu_arch_flags.bitfield.cpuavx512f)
9330 return (const reg_entry *) NULL;
9331
db51cc60 9332 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9333 if (!allow_index_reg
db51cc60
L		 9334 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9335 return (const reg_entry *) NULL;
9336
43234a1e
L		 9337 /* Upper 16 vector register is only available with VREX in 64bit
9338 mode. */
9339 if ((r->reg_flags & RegVRex))
9340 {
9341 if (!cpu_arch_flags.bitfield.cpuvrex
9342 || flag_code != CODE_64BIT)
9343 return (const reg_entry *) NULL;
9344
9345 i.need_vrex = 1;
9346 }
9347
a60de03c
JB		 9348 if (((r->reg_flags & (RegRex64 | RegRex))
9349 || r->reg_type.bitfield.reg64)
40fb9820 9350 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9351 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9352 && flag_code != CODE_64BIT)
20f0a1fc 9353 return (const reg_entry *) NULL;
1ae00879 9354
b7240065
JB		 9355 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9356 return (const reg_entry *) NULL;
9357
252b5132
RH		 9358 return r;
9359}
4d1bb795
JB		 9360
9361/* REG_STRING starts *before* REGISTER_PREFIX. */
9362
9363static const reg_entry *
9364parse_register (char *reg_string, char **end_op)
9365{
9366 const reg_entry *r;
9367
9368 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9369 r = parse_real_register (reg_string, end_op);
9370 else
9371 r = NULL;
9372 if (!r)
9373 {
9374 char *save = input_line_pointer;
9375 char c;
9376 symbolS *symbolP;
9377
9378 input_line_pointer = reg_string;
9379 c = get_symbol_end ();
9380 symbolP = symbol_find (reg_string);
9381 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9382 {
9383 const expressionS *e = symbol_get_value_expression (symbolP);
9384
0398aac5 9385 know (e->X_op == O_register);
4eed87de 9386 know (e->X_add_number >= 0
c3fe08fa 9387 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 9388 r = i386_regtab + e->X_add_number;
9389 *end_op = input_line_pointer;
9390 }
9391 *input_line_pointer = c;
9392 input_line_pointer = save;
9393 }
9394 return r;
9395}
9396
9397int
9398i386_parse_name (char *name, expressionS *e, char *nextcharP)
9399{
9400 const reg_entry *r;
9401 char *end = input_line_pointer;
9402
9403 *end = *nextcharP;
9404 r = parse_register (name, &input_line_pointer);
9405 if (r && end <= input_line_pointer)
9406 {
9407 *nextcharP = *input_line_pointer;
9408 *input_line_pointer = 0;
9409 e->X_op = O_register;
9410 e->X_add_number = r - i386_regtab;
9411 return 1;
9412 }
9413 input_line_pointer = end;
9414 *end = 0;
ee86248c 9415 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9416}
9417
9418void
9419md_operand (expressionS *e)
9420{
ee86248c
JB		 9421 char *end;
9422 const reg_entry *r;
4d1bb795 9423
ee86248c
JB		 9424 switch (*input_line_pointer)
9425 {
9426 case REGISTER_PREFIX:
9427 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9428 if (r)
9429 {
9430 e->X_op = O_register;
9431 e->X_add_number = r - i386_regtab;
9432 input_line_pointer = end;
9433 }
ee86248c
JB		 9434 break;
9435
9436 case '[':
9c2799c2 9437 gas_assert (intel_syntax);
ee86248c
JB		 9438 end = input_line_pointer++;
9439 expression (e);
9440 if (*input_line_pointer == ']')
9441 {
9442 ++input_line_pointer;
9443 e->X_op_symbol = make_expr_symbol (e);
9444 e->X_add_symbol = NULL;
9445 e->X_add_number = 0;
9446 e->X_op = O_index;
9447 }
9448 else
9449 {
9450 e->X_op = O_absent;
9451 input_line_pointer = end;
9452 }
9453 break;
4d1bb795
JB		 9454 }
9455}
9456
252b5132 9457\f
4cc782b5 9458#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9459const char *md_shortopts = "kVQ:sqn";
252b5132 9460#else
12b55ccc 9461const char *md_shortopts = "qn";
252b5132 9462#endif
6e0b89ee 9463
3e73aa7c 9464#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9465#define OPTION_64 (OPTION_MD_BASE + 1)
9466#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9467#define OPTION_MARCH (OPTION_MD_BASE + 3)
9468#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9469#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9470#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9471#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9472#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9473#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9474#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9475#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9476#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9477#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9478#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9479#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9480#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9481#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
b3b91714 9482
99ad8390
NC		 9483struct option md_longopts[] =
9484{
3e73aa7c 9485 {"32", no_argument, NULL, OPTION_32},
321098a5 9486#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9487 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9488 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9489#endif
9490#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9491 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9492#endif
b3b91714 9493 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9494 {"march", required_argument, NULL, OPTION_MARCH},
9495 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9496 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9497 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9498 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9499 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9500 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9501 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9502 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9503 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9504 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9505 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9506 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9507 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
252b5132
RH		 9508 {NULL, no_argument, NULL, 0}
9509};
9510size_t md_longopts_size = sizeof (md_longopts);
9511
9512int
9103f4f4 9513md_parse_option (int c, char *arg)
252b5132 9514{
91d6fa6a 9515 unsigned int j;
6305a203 9516 char *arch, *next;
9103f4f4 9517
252b5132
RH		 9518 switch (c)
9519 {
12b55ccc
L		 9520 case 'n':
9521 optimize_align_code = 0;
9522 break;
9523
a38cf1db
AM		 9524 case 'q':
9525 quiet_warnings = 1;
252b5132
RH		 9526 break;
9527
9528#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9529 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9530 should be emitted or not. FIXME: Not implemented. */
9531 case 'Q':
252b5132
RH		 9532 break;
9533
9534 /* -V: SVR4 argument to print version ID. */
9535 case 'V':
9536 print_version_id ();
9537 break;
9538
a38cf1db
AM		 9539 /* -k: Ignore for FreeBSD compatibility. */
9540 case 'k':
252b5132 9541 break;
4cc782b5
ILT		 9542
9543 case 's':
9544 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9545 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9546 break;
99ad8390 9547#endif
321098a5 9548#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9549 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9550 case OPTION_64:
9551 {
9552 const char **list, **l;
9553
3e73aa7c
JH		 9554 list = bfd_target_list ();
9555 for (l = list; *l != NULL; l++)
8620418b 9556 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9557 || strcmp (*l, "coff-x86-64") == 0
9558 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9559 || strcmp (*l, "pei-x86-64") == 0
9560 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9561 {
9562 default_arch = "x86_64";
9563 break;
9564 }
3e73aa7c 9565 if (*l == NULL)
2b5d6a91 9566 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9567 free (list);
9568 }
9569 break;
9570#endif
252b5132 9571
351f65ca 9572#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9573 case OPTION_X32:
351f65ca
L		 9574 if (IS_ELF)
9575 {
9576 const char **list, **l;
9577
9578 list = bfd_target_list ();
9579 for (l = list; *l != NULL; l++)
9580 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9581 {
9582 default_arch = "x86_64:32";
9583 break;
9584 }
9585 if (*l == NULL)
2b5d6a91 9586 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9587 free (list);
9588 }
9589 else
9590 as_fatal (_("32bit x86_64 is only supported for ELF"));
9591 break;
9592#endif
9593
6e0b89ee
AM		 9594 case OPTION_32:
9595 default_arch = "i386";
9596 break;
9597
b3b91714
AM		 9598 case OPTION_DIVIDE:
9599#ifdef SVR4_COMMENT_CHARS
9600 {
9601 char *n, *t;
9602 const char *s;
9603
9604 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9605 t = n;
9606 for (s = i386_comment_chars; *s != '\0'; s++)
9607 if (*s != '/')
9608 *t++ = *s;
9609 *t = '\0';
9610 i386_comment_chars = n;
9611 }
9612#endif
9613 break;
9614
9103f4f4 9615 case OPTION_MARCH:
6305a203
L		 9616 arch = xstrdup (arg);
9617 do
9103f4f4 9618 {
6305a203 9619 if (*arch == '.')
2b5d6a91 9620 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9621 next = strchr (arch, '+');
9622 if (next)
9623 *next++ = '\0';
91d6fa6a 9624 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9625 {
91d6fa6a 9626 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9627 {
6305a203 9628 /* Processor. */
1ded5609
JB		 9629 if (! cpu_arch[j].flags.bitfield.cpui386)
9630 continue;
9631
91d6fa6a 9632 cpu_arch_name = cpu_arch[j].name;
6305a203 9633 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9634 cpu_arch_flags = cpu_arch[j].flags;
9635 cpu_arch_isa = cpu_arch[j].type;
9636 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9637 if (!cpu_arch_tune_set)
9638 {
9639 cpu_arch_tune = cpu_arch_isa;
9640 cpu_arch_tune_flags = cpu_arch_isa_flags;
9641 }
9642 break;
9643 }
91d6fa6a
NC		 9644 else if (*cpu_arch [j].name == '.'
9645 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9646 {
9647 /* ISA entension. */
9648 i386_cpu_flags flags;
309d3373 9649
49021df2 9650 if (!cpu_arch[j].negated)
309d3373 9651 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9652 cpu_arch[j].flags);
309d3373
JB		 9653 else
9654 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9655 cpu_arch[j].flags);
0dfbf9d7 9656 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9657 {
9658 if (cpu_sub_arch_name)
9659 {
9660 char *name = cpu_sub_arch_name;
9661 cpu_sub_arch_name = concat (name,
91d6fa6a 9662 cpu_arch[j].name,
1bf57e9f 9663 (const char *) NULL);
6305a203
L		 9664 free (name);
9665 }
9666 else
91d6fa6a 9667 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9668 cpu_arch_flags = flags;
a586129e 9669 cpu_arch_isa_flags = flags;
6305a203
L		 9670 }
9671 break;
ccc9c027 9672 }
9103f4f4 9673 }
6305a203 9674
91d6fa6a 9675 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9676 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9677
9678 arch = next;
9103f4f4 9679 }
6305a203 9680 while (next != NULL );
9103f4f4
L		 9681 break;
9682
9683 case OPTION_MTUNE:
9684 if (*arg == '.')
2b5d6a91 9685 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9686 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9687 {
91d6fa6a 9688 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9689 {
ccc9c027 9690 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9691 cpu_arch_tune = cpu_arch [j].type;
9692 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9693 break;
9694 }
9695 }
91d6fa6a 9696 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9697 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9698 break;
9699
1efbbeb4
L		 9700 case OPTION_MMNEMONIC:
9701 if (strcasecmp (arg, "att") == 0)
9702 intel_mnemonic = 0;
9703 else if (strcasecmp (arg, "intel") == 0)
9704 intel_mnemonic = 1;
9705 else
2b5d6a91 9706 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9707 break;
9708
9709 case OPTION_MSYNTAX:
9710 if (strcasecmp (arg, "att") == 0)
9711 intel_syntax = 0;
9712 else if (strcasecmp (arg, "intel") == 0)
9713 intel_syntax = 1;
9714 else
2b5d6a91 9715 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9716 break;
9717
9718 case OPTION_MINDEX_REG:
9719 allow_index_reg = 1;
9720 break;
9721
9722 case OPTION_MNAKED_REG:
9723 allow_naked_reg = 1;
9724 break;
9725
9726 case OPTION_MOLD_GCC:
9727 old_gcc = 1;
1efbbeb4
L		 9728 break;
9729
c0f3af97
L		 9730 case OPTION_MSSE2AVX:
9731 sse2avx = 1;
9732 break;
9733
daf50ae7
L		 9734 case OPTION_MSSE_CHECK:
9735 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9736 sse_check = check_error;
daf50ae7 9737 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9738 sse_check = check_warning;
daf50ae7 9739 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9740 sse_check = check_none;
daf50ae7 9741 else
2b5d6a91 9742 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9743 break;
9744
7bab8ab5
JB		 9745 case OPTION_MOPERAND_CHECK:
9746 if (strcasecmp (arg, "error") == 0)
9747 operand_check = check_error;
9748 else if (strcasecmp (arg, "warning") == 0)
9749 operand_check = check_warning;
9750 else if (strcasecmp (arg, "none") == 0)
9751 operand_check = check_none;
9752 else
9753 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9754 break;
9755
539f890d
L		 9756 case OPTION_MAVXSCALAR:
9757 if (strcasecmp (arg, "128") == 0)
9758 avxscalar = vex128;
9759 else if (strcasecmp (arg, "256") == 0)
9760 avxscalar = vex256;
9761 else
2b5d6a91 9762 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9763 break;
9764
7e8b059b
L		 9765 case OPTION_MADD_BND_PREFIX:
9766 add_bnd_prefix = 1;
9767 break;
9768
43234a1e
L		 9769 case OPTION_MEVEXLIG:
9770 if (strcmp (arg, "128") == 0)
9771 evexlig = evexl128;
9772 else if (strcmp (arg, "256") == 0)
9773 evexlig = evexl256;
9774 else if (strcmp (arg, "512") == 0)
9775 evexlig = evexl512;
9776 else
9777 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9778 break;
9779
9780 case OPTION_MEVEXWIG:
9781 if (strcmp (arg, "0") == 0)
9782 evexwig = evexw0;
9783 else if (strcmp (arg, "1") == 0)
9784 evexwig = evexw1;
9785 else
9786 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9787 break;
9788
252b5132
RH		 9789 default:
9790 return 0;
9791 }
9792 return 1;
9793}
9794
8a2c8fef
L		 9795#define MESSAGE_TEMPLATE \
9796" "
9797
9798static void
1ded5609 9799show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9800{
9801 static char message[] = MESSAGE_TEMPLATE;
9802 char *start = message + 27;
9803 char *p;
9804 int size = sizeof (MESSAGE_TEMPLATE);
9805 int left;
9806 const char *name;
9807 int len;
9808 unsigned int j;
9809
9810 p = start;
9811 left = size - (start - message);
9812 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9813 {
9814 /* Should it be skipped? */
9815 if (cpu_arch [j].skip)
9816 continue;
9817
9818 name = cpu_arch [j].name;
9819 len = cpu_arch [j].len;
9820 if (*name == '.')
9821 {
9822 /* It is an extension. Skip if we aren't asked to show it. */
9823 if (ext)
9824 {
9825 name++;
9826 len--;
9827 }
9828 else
9829 continue;
9830 }
9831 else if (ext)
9832 {
9833 /* It is an processor. Skip if we show only extension. */
9834 continue;
9835 }
1ded5609
JB		 9836 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9837 {
9838 /* It is an impossible processor - skip. */
9839 continue;
9840 }
8a2c8fef
L		 9841
9842 /* Reserve 2 spaces for ", " or ",\0" */
9843 left -= len + 2;
9844
9845 /* Check if there is any room. */
9846 if (left >= 0)
9847 {
9848 if (p != start)
9849 {
9850 *p++ = ',';
9851 *p++ = ' ';
9852 }
9853 p = mempcpy (p, name, len);
9854 }
9855 else
9856 {
9857 /* Output the current message now and start a new one. */
9858 *p++ = ',';
9859 *p = '\0';
9860 fprintf (stream, "%s\n", message);
9861 p = start;
9862 left = size - (start - message) - len - 2;
8d63c93e 9863
8a2c8fef
L		 9864 gas_assert (left >= 0);
9865
9866 p = mempcpy (p, name, len);
9867 }
9868 }
9869
9870 *p = '\0';
9871 fprintf (stream, "%s\n", message);
9872}
9873
252b5132 9874void
8a2c8fef 9875md_show_usage (FILE *stream)
252b5132 9876{
4cc782b5
ILT		 9877#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9878 fprintf (stream, _("\
a38cf1db
AM		 9879 -Q ignored\n\
9880 -V print assembler version number\n\
b3b91714
AM		 9881 -k ignored\n"));
9882#endif
9883 fprintf (stream, _("\
12b55ccc 9884 -n Do not optimize code alignment\n\
b3b91714
AM		 9885 -q quieten some warnings\n"));
9886#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9887 fprintf (stream, _("\
a38cf1db 9888 -s ignored\n"));
b3b91714 9889#endif
321098a5
L		 9890#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9891 || defined (TE_PE) || defined (TE_PEP))
751d281c 9892 fprintf (stream, _("\
570561f7 9893 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9894#endif
b3b91714
AM		 9895#ifdef SVR4_COMMENT_CHARS
9896 fprintf (stream, _("\
9897 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9898#else
9899 fprintf (stream, _("\
b3b91714 9900 --divide ignored\n"));
4cc782b5 9901#endif
9103f4f4 9902 fprintf (stream, _("\
6305a203 9903 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9904 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9905 show_arch (stream, 0, 1);
8a2c8fef
L		 9906 fprintf (stream, _("\
9907 EXTENSION is combination of:\n"));
1ded5609 9908 show_arch (stream, 1, 0);
6305a203 9909 fprintf (stream, _("\
8a2c8fef 9910 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9911 show_arch (stream, 0, 0);
ba104c83 9912 fprintf (stream, _("\
c0f3af97
L		 9913 -msse2avx encode SSE instructions with VEX prefix\n"));
9914 fprintf (stream, _("\
daf50ae7
L		 9915 -msse-check=[none|error|warning]\n\
9916 check SSE instructions\n"));
9917 fprintf (stream, _("\
7bab8ab5
JB		 9918 -moperand-check=[none|error|warning]\n\
9919 check operand combinations for validity\n"));
9920 fprintf (stream, _("\
539f890d
L		 9921 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9922 length\n"));
9923 fprintf (stream, _("\
43234a1e
L		 9924 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9925 length\n"));
9926 fprintf (stream, _("\
9927 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9928 for EVEX.W bit ignored instructions\n"));
9929 fprintf (stream, _("\
ba104c83
L		 9930 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9931 fprintf (stream, _("\
9932 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9933 fprintf (stream, _("\
9934 -mindex-reg support pseudo index registers\n"));
9935 fprintf (stream, _("\
9936 -mnaked-reg don't require `%%' prefix for registers\n"));
9937 fprintf (stream, _("\
9938 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9939 fprintf (stream, _("\
9940 -madd-bnd-prefix add BND prefix for all valid branches\n"));
252b5132
RH		 9941}
9942
3e73aa7c 9943#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9944 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9945 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9946
9947/* Pick the target format to use. */
9948
47926f60 9949const char *
e3bb37b5 9950i386_target_format (void)
252b5132 9951{
351f65ca
L		 9952 if (!strncmp (default_arch, "x86_64", 6))
9953 {
9954 update_code_flag (CODE_64BIT, 1);
9955 if (default_arch[6] == '\0')
7f56bc95 9956 x86_elf_abi = X86_64_ABI;
351f65ca 9957 else
7f56bc95 9958 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9959 }
3e73aa7c 9960 else if (!strcmp (default_arch, "i386"))
78f12dd3 9961 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9962 else
2b5d6a91 9963 as_fatal (_("unknown architecture"));
89507696
JB		 9964
9965 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9966 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9967 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9968 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9969
252b5132
RH		 9970 switch (OUTPUT_FLAVOR)
9971 {
9384f2ff 9972#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 9973 case bfd_target_aout_flavour:
47926f60 9974 return AOUT_TARGET_FORMAT;
4c63da97 9975#endif
9384f2ff
AM		 9976#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9977# if defined (TE_PE) || defined (TE_PEP)
9978 case bfd_target_coff_flavour:
9979 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9980# elif defined (TE_GO32)
0561d57c
JK		 9981 case bfd_target_coff_flavour:
9982 return "coff-go32";
9384f2ff 9983# else
252b5132
RH		 9984 case bfd_target_coff_flavour:
9985 return "coff-i386";
9384f2ff 9986# endif
4c63da97 9987#endif
3e73aa7c 9988#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 9989 case bfd_target_elf_flavour:
3e73aa7c 9990 {
351f65ca
L		 9991 const char *format;
9992
9993 switch (x86_elf_abi)
4fa24527 9994 {
351f65ca
L		 9995 default:
9996 format = ELF_TARGET_FORMAT;
9997 break;
7f56bc95 9998 case X86_64_ABI:
351f65ca 9999 use_rela_relocations = 1;
4fa24527 10000 object_64bit = 1;
351f65ca
L		 10001 format = ELF_TARGET_FORMAT64;
10002 break;
7f56bc95 10003 case X86_64_X32_ABI:
4fa24527 10004 use_rela_relocations = 1;
351f65ca 10005 object_64bit = 1;
862be3fb 10006 disallow_64bit_reloc = 1;
351f65ca
L		 10007 format = ELF_TARGET_FORMAT32;
10008 break;
4fa24527 10009 }
3632d14b 10010 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10011 {
7f56bc95 10012 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10013 as_fatal (_("Intel L1OM is 64bit only"));
10014 return ELF_TARGET_L1OM_FORMAT;
10015 }
7a9068fe
L		 10016 if (cpu_arch_isa == PROCESSOR_K1OM)
10017 {
10018 if (x86_elf_abi != X86_64_ABI)
10019 as_fatal (_("Intel K1OM is 64bit only"));
10020 return ELF_TARGET_K1OM_FORMAT;
10021 }
8a9036a4 10022 else
351f65ca 10023 return format;
3e73aa7c 10024 }
e57f8c65
TG		 10025#endif
10026#if defined (OBJ_MACH_O)
10027 case bfd_target_mach_o_flavour:
d382c579
TG		 10028 if (flag_code == CODE_64BIT)
10029 {
10030 use_rela_relocations = 1;
10031 object_64bit = 1;
10032 return "mach-o-x86-64";
10033 }
10034 else
10035 return "mach-o-i386";
4c63da97 10036#endif
252b5132
RH		 10037 default:
10038 abort ();
10039 return NULL;
10040 }
10041}
10042
47926f60 10043#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10044
10045#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10046void
10047i386_elf_emit_arch_note (void)
a847613f 10048{
718ddfc0 10049 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10050 {
10051 char *p;
10052 asection *seg = now_seg;
10053 subsegT subseg = now_subseg;
10054 Elf_Internal_Note i_note;
10055 Elf_External_Note e_note;
10056 asection *note_secp;
10057 int len;
10058
10059 /* Create the .note section. */
10060 note_secp = subseg_new (".note", 0);
10061 bfd_set_section_flags (stdoutput,
10062 note_secp,
10063 SEC_HAS_CONTENTS | SEC_READONLY);
10064
10065 /* Process the arch string. */
10066 len = strlen (cpu_arch_name);
10067
10068 i_note.namesz = len + 1;
10069 i_note.descsz = 0;
10070 i_note.type = NT_ARCH;
10071 p = frag_more (sizeof (e_note.namesz));
10072 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10073 p = frag_more (sizeof (e_note.descsz));
10074 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10075 p = frag_more (sizeof (e_note.type));
10076 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10077 p = frag_more (len + 1);
10078 strcpy (p, cpu_arch_name);
10079
10080 frag_align (2, 0, 0);
10081
10082 subseg_set (seg, subseg);
10083 }
10084}
10085#endif
252b5132 10086\f
252b5132 10087symbolS *
7016a5d5 10088md_undefined_symbol (char *name)
252b5132 10089{
18dc2407
ILT		 10090 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10091 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10092 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10093 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10094 {
10095 if (!GOT_symbol)
10096 {
10097 if (symbol_find (name))
10098 as_bad (_("GOT already in symbol table"));
10099 GOT_symbol = symbol_new (name, undefined_section,
10100 (valueT) 0, &zero_address_frag);
10101 };
10102 return GOT_symbol;
10103 }
252b5132
RH		 10104 return 0;
10105}
10106
10107/* Round up a section size to the appropriate boundary. */
47926f60 10108
252b5132 10109valueT
7016a5d5 10110md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10111{
4c63da97
AM		 10112#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10113 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10114 {
10115 /* For a.out, force the section size to be aligned. If we don't do
10116 this, BFD will align it for us, but it will not write out the
10117 final bytes of the section. This may be a bug in BFD, but it is
10118 easier to fix it here since that is how the other a.out targets
10119 work. */
10120 int align;
10121
10122 align = bfd_get_section_alignment (stdoutput, segment);
10123 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10124 }
252b5132
RH		 10125#endif
10126
10127 return size;
10128}
10129
10130/* On the i386, PC-relative offsets are relative to the start of the
10131 next instruction. That is, the address of the offset, plus its
10132 size, since the offset is always the last part of the insn. */
10133
10134long
e3bb37b5 10135md_pcrel_from (fixS *fixP)
252b5132
RH		 10136{
10137 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10138}
10139
10140#ifndef I386COFF
10141
10142static void
e3bb37b5 10143s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10144{
29b0f896 10145 int temp;
252b5132 10146
8a75718c
JB		 10147#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10148 if (IS_ELF)
10149 obj_elf_section_change_hook ();
10150#endif
252b5132
RH		 10151 temp = get_absolute_expression ();
10152 subseg_set (bss_section, (subsegT) temp);
10153 demand_empty_rest_of_line ();
10154}
10155
10156#endif
10157
252b5132 10158void
e3bb37b5 10159i386_validate_fix (fixS *fixp)
252b5132
RH		 10160{
10161 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10162 {
23df1078
JH		 10163 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10164 {
4fa24527 10165 if (!object_64bit)
23df1078
JH		 10166 abort ();
10167 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10168 }
10169 else
10170 {
4fa24527 10171 if (!object_64bit)
d6ab8113
JB		 10172 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10173 else
10174 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10175 }
252b5132
RH		 10176 fixp->fx_subsy = 0;
10177 }
10178}
10179
252b5132 10180arelent *
7016a5d5 10181tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10182{
10183 arelent *rel;
10184 bfd_reloc_code_real_type code;
10185
10186 switch (fixp->fx_r_type)
10187 {
8ce3d284 10188#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10189 case BFD_RELOC_SIZE32:
10190 case BFD_RELOC_SIZE64:
10191 if (S_IS_DEFINED (fixp->fx_addsy)
10192 && !S_IS_EXTERNAL (fixp->fx_addsy))
10193 {
10194 /* Resolve size relocation against local symbol to size of
10195 the symbol plus addend. */
10196 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10197 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10198 && !fits_in_unsigned_long (value))
10199 as_bad_where (fixp->fx_file, fixp->fx_line,
10200 _("symbol size computation overflow"));
10201 fixp->fx_addsy = NULL;
10202 fixp->fx_subsy = NULL;
10203 md_apply_fix (fixp, (valueT *) &value, NULL);
10204 return NULL;
10205 }
8ce3d284 10206#endif
8fd4256d 10207
3e73aa7c 10208 case BFD_RELOC_X86_64_PLT32:
c3320543 10209 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10210 case BFD_RELOC_X86_64_GOT32:
10211 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10212 case BFD_RELOC_386_PLT32:
10213 case BFD_RELOC_386_GOT32:
10214 case BFD_RELOC_386_GOTOFF:
10215 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10216 case BFD_RELOC_386_TLS_GD:
10217 case BFD_RELOC_386_TLS_LDM:
10218 case BFD_RELOC_386_TLS_LDO_32:
10219 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10220 case BFD_RELOC_386_TLS_IE:
10221 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10222 case BFD_RELOC_386_TLS_LE_32:
10223 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10224 case BFD_RELOC_386_TLS_GOTDESC:
10225 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10226 case BFD_RELOC_X86_64_TLSGD:
10227 case BFD_RELOC_X86_64_TLSLD:
10228 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10229 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10230 case BFD_RELOC_X86_64_GOTTPOFF:
10231 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10232 case BFD_RELOC_X86_64_TPOFF64:
10233 case BFD_RELOC_X86_64_GOTOFF64:
10234 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10235 case BFD_RELOC_X86_64_GOT64:
10236 case BFD_RELOC_X86_64_GOTPCREL64:
10237 case BFD_RELOC_X86_64_GOTPC64:
10238 case BFD_RELOC_X86_64_GOTPLT64:
10239 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10240 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10241 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10242 case BFD_RELOC_RVA:
10243 case BFD_RELOC_VTABLE_ENTRY:
10244 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10245#ifdef TE_PE
10246 case BFD_RELOC_32_SECREL:
10247#endif
252b5132
RH		 10248 code = fixp->fx_r_type;
10249 break;
dbbaec26
L		 10250 case BFD_RELOC_X86_64_32S:
10251 if (!fixp->fx_pcrel)
10252 {
10253 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10254 code = fixp->fx_r_type;
10255 break;
10256 }
252b5132 10257 default:
93382f6d 10258 if (fixp->fx_pcrel)
252b5132 10259 {
93382f6d
AM		 10260 switch (fixp->fx_size)
10261 {
10262 default:
b091f402
AM		 10263 as_bad_where (fixp->fx_file, fixp->fx_line,
10264 _("can not do %d byte pc-relative relocation"),
10265 fixp->fx_size);
93382f6d
AM		 10266 code = BFD_RELOC_32_PCREL;
10267 break;
10268 case 1: code = BFD_RELOC_8_PCREL; break;
10269 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10270 case 4:
10271 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10272 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10273 break;
d6ab8113
JB		 10274#ifdef BFD64
10275 case 8: code = BFD_RELOC_64_PCREL; break;
10276#endif
93382f6d
AM		 10277 }
10278 }
10279 else
10280 {
10281 switch (fixp->fx_size)
10282 {
10283 default:
b091f402
AM		 10284 as_bad_where (fixp->fx_file, fixp->fx_line,
10285 _("can not do %d byte relocation"),
10286 fixp->fx_size);
93382f6d
AM		 10287 code = BFD_RELOC_32;
10288 break;
10289 case 1: code = BFD_RELOC_8; break;
10290 case 2: code = BFD_RELOC_16; break;
10291 case 4: code = BFD_RELOC_32; break;
937149dd 10292#ifdef BFD64
3e73aa7c 10293 case 8: code = BFD_RELOC_64; break;
937149dd 10294#endif
93382f6d 10295 }
252b5132
RH		 10296 }
10297 break;
10298 }
252b5132 10299
d182319b
JB		 10300 if ((code == BFD_RELOC_32
10301 || code == BFD_RELOC_32_PCREL
10302 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10303 && GOT_symbol
10304 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10305 {
4fa24527 10306 if (!object_64bit)
d6ab8113
JB		 10307 code = BFD_RELOC_386_GOTPC;
10308 else
10309 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10310 }
7b81dfbb
AJ		 10311 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10312 && GOT_symbol
10313 && fixp->fx_addsy == GOT_symbol)
10314 {
10315 code = BFD_RELOC_X86_64_GOTPC64;
10316 }
252b5132
RH		 10317
10318 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10319 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10320 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10321
10322 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10323
3e73aa7c
JH		 10324 if (!use_rela_relocations)
10325 {
10326 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10327 vtable entry to be used in the relocation's section offset. */
10328 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10329 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10330#if defined (OBJ_COFF) && defined (TE_PE)
10331 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10332 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10333 else
10334#endif
c6682705 10335 rel->addend = 0;
3e73aa7c
JH		 10336 }
10337 /* Use the rela in 64bit mode. */
252b5132 10338 else
3e73aa7c 10339 {
862be3fb
L		 10340 if (disallow_64bit_reloc)
10341 switch (code)
10342 {
862be3fb
L		 10343 case BFD_RELOC_X86_64_DTPOFF64:
10344 case BFD_RELOC_X86_64_TPOFF64:
10345 case BFD_RELOC_64_PCREL:
10346 case BFD_RELOC_X86_64_GOTOFF64:
10347 case BFD_RELOC_X86_64_GOT64:
10348 case BFD_RELOC_X86_64_GOTPCREL64:
10349 case BFD_RELOC_X86_64_GOTPC64:
10350 case BFD_RELOC_X86_64_GOTPLT64:
10351 case BFD_RELOC_X86_64_PLTOFF64:
10352 as_bad_where (fixp->fx_file, fixp->fx_line,
10353 _("cannot represent relocation type %s in x32 mode"),
10354 bfd_get_reloc_code_name (code));
10355 break;
10356 default:
10357 break;
10358 }
10359
062cd5e7
AS		 10360 if (!fixp->fx_pcrel)
10361 rel->addend = fixp->fx_offset;
10362 else
10363 switch (code)
10364 {
10365 case BFD_RELOC_X86_64_PLT32:
c3320543 10366 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10367 case BFD_RELOC_X86_64_GOT32:
10368 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10369 case BFD_RELOC_X86_64_TLSGD:
10370 case BFD_RELOC_X86_64_TLSLD:
10371 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10372 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10373 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10374 rel->addend = fixp->fx_offset - fixp->fx_size;
10375 break;
10376 default:
10377 rel->addend = (section->vma
10378 - fixp->fx_size
10379 + fixp->fx_addnumber
10380 + md_pcrel_from (fixp));
10381 break;
10382 }
3e73aa7c
JH		 10383 }
10384
252b5132
RH		 10385 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10386 if (rel->howto == NULL)
10387 {
10388 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10389 _("cannot represent relocation type %s"),
252b5132
RH		 10390 bfd_get_reloc_code_name (code));
10391 /* Set howto to a garbage value so that we can keep going. */
10392 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10393 gas_assert (rel->howto != NULL);
252b5132
RH		 10394 }
10395
10396 return rel;
10397}
10398
ee86248c 10399#include "tc-i386-intel.c"
54cfded0 10400
a60de03c
JB		 10401void
10402tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10403{
a60de03c
JB		 10404 int saved_naked_reg;
10405 char saved_register_dot;
54cfded0 10406
a60de03c
JB		 10407 saved_naked_reg = allow_naked_reg;
10408 allow_naked_reg = 1;
10409 saved_register_dot = register_chars['.'];
10410 register_chars['.'] = '.';
10411 allow_pseudo_reg = 1;
10412 expression_and_evaluate (exp);
10413 allow_pseudo_reg = 0;
10414 register_chars['.'] = saved_register_dot;
10415 allow_naked_reg = saved_naked_reg;
10416
e96d56a1 10417 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10418 {
a60de03c
JB		 10419 if ((addressT) exp->X_add_number < i386_regtab_size)
10420 {
10421 exp->X_op = O_constant;
10422 exp->X_add_number = i386_regtab[exp->X_add_number]
10423 .dw2_regnum[flag_code >> 1];
10424 }
10425 else
10426 exp->X_op = O_illegal;
54cfded0 10427 }
54cfded0
AM		 10428}
10429
10430void
10431tc_x86_frame_initial_instructions (void)
10432{
a60de03c
JB		 10433 static unsigned int sp_regno[2];
10434
10435 if (!sp_regno[flag_code >> 1])
10436 {
10437 char *saved_input = input_line_pointer;
10438 char sp[][4] = {"esp", "rsp"};
10439 expressionS exp;
a4447b93 10440
a60de03c
JB		 10441 input_line_pointer = sp[flag_code >> 1];
10442 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10443 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10444 sp_regno[flag_code >> 1] = exp.X_add_number;
10445 input_line_pointer = saved_input;
10446 }
a4447b93 10447
61ff971f
L		 10448 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10449 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10450}
d2b2c203 10451
d7921315
L		 10452int
10453x86_dwarf2_addr_size (void)
10454{
10455#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10456 if (x86_elf_abi == X86_64_X32_ABI)
10457 return 4;
10458#endif
10459 return bfd_arch_bits_per_address (stdoutput) / 8;
10460}
10461
d2b2c203
DJ		 10462int
10463i386_elf_section_type (const char *str, size_t len)
10464{
10465 if (flag_code == CODE_64BIT
10466 && len == sizeof ("unwind") - 1
10467 && strncmp (str, "unwind", 6) == 0)
10468 return SHT_X86_64_UNWIND;
10469
10470 return -1;
10471}
bb41ade5 10472
ad5fec3b
EB		 10473#ifdef TE_SOLARIS
10474void
10475i386_solaris_fix_up_eh_frame (segT sec)
10476{
10477 if (flag_code == CODE_64BIT)
10478 elf_section_type (sec) = SHT_X86_64_UNWIND;
10479}
10480#endif
10481
bb41ade5
AM		 10482#ifdef TE_PE
10483void
10484tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10485{
91d6fa6a 10486 expressionS exp;
bb41ade5 10487
91d6fa6a
NC		 10488 exp.X_op = O_secrel;
10489 exp.X_add_symbol = symbol;
10490 exp.X_add_number = 0;
10491 emit_expr (&exp, size);
bb41ade5
AM		 10492}
10493#endif
3b22753a
L		 10494
10495#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10496/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10497
01e1a5bc 10498bfd_vma
3b22753a
L		 10499x86_64_section_letter (int letter, char **ptr_msg)
10500{
10501 if (flag_code == CODE_64BIT)
10502 {
10503 if (letter == 'l')
10504 return SHF_X86_64_LARGE;
10505
8f3bae45 10506 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10507 }
3b22753a 10508 else
8f3bae45 10509 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10510 return -1;
10511}
10512
01e1a5bc 10513bfd_vma
3b22753a
L		 10514x86_64_section_word (char *str, size_t len)
10515{
8620418b 10516 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10517 return SHF_X86_64_LARGE;
10518
10519 return -1;
10520}
10521
10522static void
10523handle_large_common (int small ATTRIBUTE_UNUSED)
10524{
10525 if (flag_code != CODE_64BIT)
10526 {
10527 s_comm_internal (0, elf_common_parse);
10528 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10529 }
10530 else
10531 {
10532 static segT lbss_section;
10533 asection *saved_com_section_ptr = elf_com_section_ptr;
10534 asection *saved_bss_section = bss_section;
10535
10536 if (lbss_section == NULL)
10537 {
10538 flagword applicable;
10539 segT seg = now_seg;
10540 subsegT subseg = now_subseg;
10541
10542 /* The .lbss section is for local .largecomm symbols. */
10543 lbss_section = subseg_new (".lbss", 0);
10544 applicable = bfd_applicable_section_flags (stdoutput);
10545 bfd_set_section_flags (stdoutput, lbss_section,
10546 applicable & SEC_ALLOC);
10547 seg_info (lbss_section)->bss = 1;
10548
10549 subseg_set (seg, subseg);
10550 }
10551
10552 elf_com_section_ptr = &_bfd_elf_large_com_section;
10553 bss_section = lbss_section;
10554
10555 s_comm_internal (0, elf_common_parse);
10556
10557 elf_com_section_ptr = saved_com_section_ptr;
10558 bss_section = saved_bss_section;
10559 }
10560}
10561#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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