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* dwarf2read.c (read_initial_length): Handle older, non-standard,
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
107static void output_imm PARAMS ((void));
108static void output_disp PARAMS ((void));
109#ifndef I386COFF
110static void s_bss PARAMS ((int));
252b5132
RH		 111#endif
112
a847613f 113static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 114
252b5132 115/* 'md_assemble ()' gathers together information and puts it into a
47926f60 116 i386_insn. */
252b5132 117
520dc8e8
AM		 118union i386_op
119 {
120 expressionS *disps;
121 expressionS *imms;
122 const reg_entry *regs;
123 };
124
252b5132
RH		 125struct _i386_insn
126 {
47926f60 127 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 128 template tm;
129
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
132 char suffix;
133
47926f60 134 /* OPERANDS gives the number of given operands. */
252b5132
RH		 135 unsigned int operands;
136
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
47926f60 139 operands. */
252b5132
RH		 140 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
141
142 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 143 use OP[i] for the corresponding operand. */
252b5132
RH		 144 unsigned int types[MAX_OPERANDS];
145
520dc8e8
AM		 146 /* Displacement expression, immediate expression, or register for each
147 operand. */
148 union i386_op op[MAX_OPERANDS];
252b5132 149
3e73aa7c
JH		 150 /* Flags for operands. */
151 unsigned int flags[MAX_OPERANDS];
152#define Operand_PCrel 1
153
252b5132 154 /* Relocation type for operand */
f3c180ae 155 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 156
252b5132
RH		 157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry *base_reg;
160 const reg_entry *index_reg;
161 unsigned int log2_scale_factor;
162
163 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 164 explicit segment overrides are given. */
ce8a8b2f 165 const seg_entry *seg[2];
252b5132
RH		 166
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes;
170 unsigned char prefix[MAX_PREFIXES];
171
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
174
175 modrm_byte rm;
3e73aa7c 176 rex_byte rex;
252b5132
RH		 177 sib_byte sib;
178 };
179
180typedef struct _i386_insn i386_insn;
181
182/* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
184#ifdef LEX_AT
200dbde8 185const char extra_symbol_chars[] = "*%-(@[";
252b5132 186#else
200dbde8 187const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 188#endif
189
29b0f896
AM		 190#if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
252b5132 195/* This array holds the chars that always start a comment. If the
ce8a8b2f 196 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 197const char comment_chars[] = "#/";
198#define PREFIX_SEPARATOR '\\'
252b5132
RH		 199
200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
252b5132 208const char line_comment_chars[] = "";
29b0f896 209
252b5132 210#else
29b0f896
AM		 211/* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213const char comment_chars[] = "#";
214#define PREFIX_SEPARATOR '/'
215
252b5132
RH		 216const char line_comment_chars[] = "/";
217#endif
218
63a0b638 219const char line_separator_chars[] = ";";
252b5132 220
ce8a8b2f
AM		 221/* Chars that can be used to separate mant from exp in floating point
222 nums. */
252b5132
RH		 223const char EXP_CHARS[] = "eE";
224
ce8a8b2f
AM		 225/* Chars that mean this number is a floating point constant
226 As in 0f12.456
227 or 0d1.2345e12. */
252b5132
RH		 228const char FLT_CHARS[] = "fFdDxX";
229
ce8a8b2f 230/* Tables for lexical analysis. */
252b5132
RH		 231static char mnemonic_chars[256];
232static char register_chars[256];
233static char operand_chars[256];
234static char identifier_chars[256];
235static char digit_chars[256];
236
ce8a8b2f 237/* Lexical macros. */
252b5132
RH		 238#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239#define is_operand_char(x) (operand_chars[(unsigned char) x])
240#define is_register_char(x) (register_chars[(unsigned char) x])
241#define is_space_char(x) ((x) == ' ')
242#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243#define is_digit_char(x) (digit_chars[(unsigned char) x])
244
ce8a8b2f 245/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 246static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
247
248/* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
47926f60 251 assembler instruction). */
252b5132 252static char save_stack[32];
ce8a8b2f 253static char *save_stack_p;
252b5132
RH		 254#define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256#define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
258
47926f60 259/* The instruction we're assembling. */
252b5132
RH		 260static i386_insn i;
261
262/* Possible templates for current insn. */
263static const templates *current_templates;
264
47926f60 265/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 266static expressionS disp_expressions[2], im_expressions[2];
267
47926f60
KH		 268/* Current operand we are working on. */
269static int this_operand;
252b5132 270
3e73aa7c
JH		 271/* We support four different modes. FLAG_CODE variable is used to distinguish
272 these. */
273
274enum flag_code {
275 CODE_32BIT,
276 CODE_16BIT,
277 CODE_64BIT };
f3c180ae 278#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 279
280static enum flag_code flag_code;
281static int use_rela_relocations = 0;
282
283/* The names used to print error messages. */
b77a7acd 284static const char *flag_code_names[] =
3e73aa7c
JH		 285 {
286 "32",
287 "16",
288 "64"
289 };
252b5132 290
47926f60
KH		 291/* 1 for intel syntax,
292 0 if att syntax. */
293static int intel_syntax = 0;
252b5132 294
47926f60
KH		 295/* 1 if register prefix % not required. */
296static int allow_naked_reg = 0;
252b5132 297
47926f60
KH		 298/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301static char stackop_size = '\0';
eecb386c 302
47926f60
KH		 303/* Non-zero to quieten some warnings. */
304static int quiet_warnings = 0;
a38cf1db 305
47926f60
KH		 306/* CPU name. */
307static const char *cpu_arch_name = NULL;
a38cf1db 308
47926f60 309/* CPU feature flags. */
29b0f896 310static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 311
fddf5b5b
AM		 312/* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314static unsigned int no_cond_jump_promotion = 0;
315
29b0f896
AM		 316/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
317symbolS *GOT_symbol;
318
252b5132 319/* Interface to relax_segment.
fddf5b5b
AM		 320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
252b5132 323
47926f60 324/* Types. */
93c2a809
AM		 325#define UNCOND_JUMP 0
326#define COND_JUMP 1
327#define COND_JUMP86 2
fddf5b5b 328
47926f60 329/* Sizes. */
252b5132
RH		 330#define CODE16 1
331#define SMALL 0
29b0f896 332#define SMALL16 (SMALL | CODE16)
252b5132 333#define BIG 2
29b0f896 334#define BIG16 (BIG | CODE16)
252b5132
RH		 335
336#ifndef INLINE
337#ifdef __GNUC__
338#define INLINE __inline__
339#else
340#define INLINE
341#endif
342#endif
343
fddf5b5b
AM		 344#define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346#define TYPE_FROM_RELAX_STATE(s) \
347 ((s) >> 2)
348#define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 350
351/* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
358
359const relax_typeS md_relax_table[] =
360{
24eab124
AM		 361 /* The fields are:
362 1) most positive reach of this state,
363 2) most negative reach of this state,
93c2a809 364 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 365 4) which index into the table to try if we can't fit into this one. */
252b5132 366
fddf5b5b 367 /* UNCOND_JUMP states. */
93c2a809
AM		 368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
252b5132 372 {0, 0, 4, 0},
93c2a809
AM		 373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 375 {0, 0, 2, 0},
376
93c2a809
AM		 377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
382 {0, 0, 5, 0},
fddf5b5b 383 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 384 1 extra opcode byte, 2 displacement bytes. */
385 {0, 0, 3, 0},
386
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
392 {0, 0, 5, 0},
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
395 {0, 0, 4, 0}
252b5132
RH		 396};
397
e413e4e9
AM		 398static const arch_entry cpu_arch[] = {
399 {"i8086", Cpu086 },
400 {"i186", Cpu086|Cpu186 },
401 {"i286", Cpu086|Cpu186|Cpu286 },
402 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
403 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
404 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
405 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
406 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 408 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 409 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
410 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 411 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 412 {NULL, 0 }
413};
414
29b0f896
AM		 415const pseudo_typeS md_pseudo_table[] =
416{
417#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes, 0},
419#else
420 {"align", s_align_ptwo, 0},
421#endif
422 {"arch", set_cpu_arch, 0},
423#ifndef I386COFF
424 {"bss", s_bss, 0},
425#endif
426 {"ffloat", float_cons, 'f'},
427 {"dfloat", float_cons, 'd'},
428 {"tfloat", float_cons, 'x'},
429 {"value", cons, 2},
430 {"noopt", s_ignore, 0},
431 {"optim", s_ignore, 0},
432 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
433 {"code16", set_code_flag, CODE_16BIT},
434 {"code32", set_code_flag, CODE_32BIT},
435 {"code64", set_code_flag, CODE_64BIT},
436 {"intel_syntax", set_intel_syntax, 1},
437 {"att_syntax", set_intel_syntax, 0},
c6682705 438 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896
AM		 439 {"loc", dwarf2_directive_loc, 0},
440 {0, 0, 0}
441};
442
443/* For interface with expression (). */
444extern char *input_line_pointer;
445
446/* Hash table for instruction mnemonic lookup. */
447static struct hash_control *op_hash;
448
449/* Hash table for register lookup. */
450static struct hash_control *reg_hash;
451\f
252b5132
RH		 452void
453i386_align_code (fragP, count)
454 fragS *fragP;
455 int count;
456{
ce8a8b2f
AM		 457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
252b5132
RH		 460 static const char f32_1[] =
461 {0x90}; /* nop */
462 static const char f32_2[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5[] =
469 {0x90, /* nop */
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8[] =
476 {0x90, /* nop */
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 499 static const char f16_3[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 501 static const char f16_4[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5[] =
504 {0x90, /* nop */
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt[] = {
516 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
517 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
518 };
519 static const char *const f16_patt[] = {
c3332e24 520 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 521 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
522 };
523
3e73aa7c
JH		 524 /* ??? We can't use these fillers for x86_64, since they often kills the
525 upper halves. Solve later. */
526 if (flag_code == CODE_64BIT)
527 count = 1;
528
252b5132
RH		 529 if (count > 0 && count <= 15)
530 {
3e73aa7c 531 if (flag_code == CODE_16BIT)
252b5132 532 {
47926f60
KH		 533 memcpy (fragP->fr_literal + fragP->fr_fix,
534 f16_patt[count - 1], count);
535 if (count > 8)
536 /* Adjust jump offset. */
252b5132
RH		 537 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
538 }
539 else
47926f60
KH		 540 memcpy (fragP->fr_literal + fragP->fr_fix,
541 f32_patt[count - 1], count);
252b5132
RH		 542 fragP->fr_var = count;
543 }
544}
545
252b5132
RH		 546static INLINE unsigned int
547mode_from_disp_size (t)
548 unsigned int t;
549{
3e73aa7c 550 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 551}
552
553static INLINE int
554fits_in_signed_byte (num)
847f7ad4 555 offsetT num;
252b5132
RH		 556{
557 return (num >= -128) && (num <= 127);
47926f60 558}
252b5132
RH		 559
560static INLINE int
561fits_in_unsigned_byte (num)
847f7ad4 562 offsetT num;
252b5132
RH		 563{
564 return (num & 0xff) == num;
47926f60 565}
252b5132
RH		 566
567static INLINE int
568fits_in_unsigned_word (num)
847f7ad4 569 offsetT num;
252b5132
RH		 570{
571 return (num & 0xffff) == num;
47926f60 572}
252b5132
RH		 573
574static INLINE int
575fits_in_signed_word (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (-32768 <= num) && (num <= 32767);
47926f60 579}
3e73aa7c
JH		 580static INLINE int
581fits_in_signed_long (num)
582 offsetT num ATTRIBUTE_UNUSED;
583{
584#ifndef BFD64
585 return 1;
586#else
587 return (!(((offsetT) -1 << 31) & num)
588 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
589#endif
590} /* fits_in_signed_long() */
591static INLINE int
592fits_in_unsigned_long (num)
593 offsetT num ATTRIBUTE_UNUSED;
594{
595#ifndef BFD64
596 return 1;
597#else
598 return (num & (((offsetT) 2 << 31) - 1)) == num;
599#endif
600} /* fits_in_unsigned_long() */
252b5132
RH		 601
602static int
603smallest_imm_type (num)
847f7ad4 604 offsetT num;
252b5132 605{
a847613f 606 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 607 {
608 /* This code is disabled on the 486 because all the Imm1 forms
609 in the opcode table are slower on the i486. They're the
610 versions with the implicitly specified single-position
611 displacement, which has another syntax if you really want to
612 use that form. */
613 if (num == 1)
3e73aa7c 614 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 615 }
252b5132 616 return (fits_in_signed_byte (num)
3e73aa7c 617 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 618 : fits_in_unsigned_byte (num)
3e73aa7c 619 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 620 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 621 ? (Imm16 | Imm32 | Imm32S | Imm64)
622 : fits_in_signed_long (num)
623 ? (Imm32 | Imm32S | Imm64)
624 : fits_in_unsigned_long (num)
625 ? (Imm32 | Imm64)
626 : Imm64);
47926f60 627}
252b5132 628
847f7ad4
AM		 629static offsetT
630offset_in_range (val, size)
631 offsetT val;
632 int size;
633{
508866be 634 addressT mask;
ba2adb93 635
847f7ad4
AM		 636 switch (size)
637 {
508866be
L		 638 case 1: mask = ((addressT) 1 << 8) - 1; break;
639 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 640 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 641#ifdef BFD64
642 case 8: mask = ((addressT) 2 << 63) - 1; break;
643#endif
47926f60 644 default: abort ();
847f7ad4
AM		 645 }
646
ba2adb93 647 /* If BFD64, sign extend val. */
3e73aa7c
JH		 648 if (!use_rela_relocations)
649 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
650 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 651
47926f60 652 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 653 {
654 char buf1[40], buf2[40];
655
656 sprint_value (buf1, val);
657 sprint_value (buf2, val & mask);
658 as_warn (_("%s shortened to %s"), buf1, buf2);
659 }
660 return val & mask;
661}
662
252b5132
RH		 663/* Returns 0 if attempting to add a prefix where one from the same
664 class already exists, 1 if non rep/repne added, 2 if rep/repne
665 added. */
666static int
667add_prefix (prefix)
668 unsigned int prefix;
669{
670 int ret = 1;
671 int q;
672
29b0f896
AM		 673 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
674 && flag_code == CODE_64BIT)
3e73aa7c
JH		 675 q = REX_PREFIX;
676 else
677 switch (prefix)
678 {
679 default:
680 abort ();
681
682 case CS_PREFIX_OPCODE:
683 case DS_PREFIX_OPCODE:
684 case ES_PREFIX_OPCODE:
685 case FS_PREFIX_OPCODE:
686 case GS_PREFIX_OPCODE:
687 case SS_PREFIX_OPCODE:
688 q = SEG_PREFIX;
689 break;
252b5132 690
3e73aa7c
JH		 691 case REPNE_PREFIX_OPCODE:
692 case REPE_PREFIX_OPCODE:
693 ret = 2;
694 /* fall thru */
695 case LOCK_PREFIX_OPCODE:
696 q = LOCKREP_PREFIX;
697 break;
252b5132 698
3e73aa7c
JH		 699 case FWAIT_OPCODE:
700 q = WAIT_PREFIX;
701 break;
252b5132 702
3e73aa7c
JH		 703 case ADDR_PREFIX_OPCODE:
704 q = ADDR_PREFIX;
705 break;
252b5132 706
3e73aa7c
JH		 707 case DATA_PREFIX_OPCODE:
708 q = DATA_PREFIX;
709 break;
710 }
252b5132 711
29b0f896 712 if (i.prefix[q] != 0)
252b5132
RH		 713 {
714 as_bad (_("same type of prefix used twice"));
715 return 0;
716 }
717
718 i.prefixes += 1;
719 i.prefix[q] = prefix;
720 return ret;
721}
722
723static void
3e73aa7c 724set_code_flag (value)
e5cb08ac 725 int value;
eecb386c 726{
3e73aa7c
JH		 727 flag_code = value;
728 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
729 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
730 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
731 {
732 as_bad (_("64bit mode not supported on this CPU."));
733 }
734 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
735 {
736 as_bad (_("32bit mode not supported on this CPU."));
737 }
eecb386c
AM		 738 stackop_size = '\0';
739}
740
741static void
3e73aa7c
JH		 742set_16bit_gcc_code_flag (new_code_flag)
743 int new_code_flag;
252b5132 744{
3e73aa7c
JH		 745 flag_code = new_code_flag;
746 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
747 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
748 stackop_size = 'l';
252b5132
RH		 749}
750
751static void
752set_intel_syntax (syntax_flag)
eecb386c 753 int syntax_flag;
252b5132
RH		 754{
755 /* Find out if register prefixing is specified. */
756 int ask_naked_reg = 0;
757
758 SKIP_WHITESPACE ();
29b0f896 759 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 760 {
761 char *string = input_line_pointer;
762 int e = get_symbol_end ();
763
47926f60 764 if (strcmp (string, "prefix") == 0)
252b5132 765 ask_naked_reg = 1;
47926f60 766 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 767 ask_naked_reg = -1;
768 else
d0b47220 769 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 770 *input_line_pointer = e;
771 }
772 demand_empty_rest_of_line ();
c3332e24 773
252b5132
RH		 774 intel_syntax = syntax_flag;
775
776 if (ask_naked_reg == 0)
777 {
778#ifdef BFD_ASSEMBLER
779 allow_naked_reg = (intel_syntax
24eab124 780 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 781#else
47926f60
KH		 782 /* Conservative default. */
783 allow_naked_reg = 0;
252b5132
RH		 784#endif
785 }
786 else
787 allow_naked_reg = (ask_naked_reg < 0);
788}
789
e413e4e9
AM		 790static void
791set_cpu_arch (dummy)
47926f60 792 int dummy ATTRIBUTE_UNUSED;
e413e4e9 793{
47926f60 794 SKIP_WHITESPACE ();
e413e4e9 795
29b0f896 796 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 797 {
798 char *string = input_line_pointer;
799 int e = get_symbol_end ();
800 int i;
801
802 for (i = 0; cpu_arch[i].name; i++)
803 {
804 if (strcmp (string, cpu_arch[i].name) == 0)
805 {
806 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 807 cpu_arch_flags = (cpu_arch[i].flags
808 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 809 break;
810 }
811 }
812 if (!cpu_arch[i].name)
813 as_bad (_("no such architecture: `%s'"), string);
814
815 *input_line_pointer = e;
816 }
817 else
818 as_bad (_("missing cpu architecture"));
819
fddf5b5b
AM		 820 no_cond_jump_promotion = 0;
821 if (*input_line_pointer == ','
29b0f896 822 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 823 {
824 char *string = ++input_line_pointer;
825 int e = get_symbol_end ();
826
827 if (strcmp (string, "nojumps") == 0)
828 no_cond_jump_promotion = 1;
829 else if (strcmp (string, "jumps") == 0)
830 ;
831 else
832 as_bad (_("no such architecture modifier: `%s'"), string);
833
834 *input_line_pointer = e;
835 }
836
e413e4e9
AM		 837 demand_empty_rest_of_line ();
838}
839
b9d79e03
JH		 840#ifdef BFD_ASSEMBLER
841unsigned long
842i386_mach ()
843{
844 if (!strcmp (default_arch, "x86_64"))
845 return bfd_mach_x86_64;
846 else if (!strcmp (default_arch, "i386"))
847 return bfd_mach_i386_i386;
848 else
849 as_fatal (_("Unknown architecture"));
850}
851#endif
852\f
252b5132
RH		 853void
854md_begin ()
855{
856 const char *hash_err;
857
47926f60 858 /* Initialize op_hash hash table. */
252b5132
RH		 859 op_hash = hash_new ();
860
861 {
29b0f896
AM		 862 const template *optab;
863 templates *core_optab;
252b5132 864
47926f60
KH		 865 /* Setup for loop. */
866 optab = i386_optab;
252b5132
RH		 867 core_optab = (templates *) xmalloc (sizeof (templates));
868 core_optab->start = optab;
869
870 while (1)
871 {
872 ++optab;
873 if (optab->name == NULL
874 || strcmp (optab->name, (optab - 1)->name) != 0)
875 {
876 /* different name --> ship out current template list;
47926f60 877 add to hash table; & begin anew. */
252b5132
RH		 878 core_optab->end = optab;
879 hash_err = hash_insert (op_hash,
880 (optab - 1)->name,
881 (PTR) core_optab);
882 if (hash_err)
883 {
252b5132
RH		 884 as_fatal (_("Internal Error: Can't hash %s: %s"),
885 (optab - 1)->name,
886 hash_err);
887 }
888 if (optab->name == NULL)
889 break;
890 core_optab = (templates *) xmalloc (sizeof (templates));
891 core_optab->start = optab;
892 }
893 }
894 }
895
47926f60 896 /* Initialize reg_hash hash table. */
252b5132
RH		 897 reg_hash = hash_new ();
898 {
29b0f896 899 const reg_entry *regtab;
252b5132
RH		 900
901 for (regtab = i386_regtab;
902 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
903 regtab++)
904 {
905 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
906 if (hash_err)
3e73aa7c
JH		 907 as_fatal (_("Internal Error: Can't hash %s: %s"),
908 regtab->reg_name,
909 hash_err);
252b5132
RH		 910 }
911 }
912
47926f60 913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 914 {
29b0f896
AM		 915 int c;
916 char *p;
252b5132
RH		 917
918 for (c = 0; c < 256; c++)
919 {
3882b010 920 if (ISDIGIT (c))
252b5132
RH		 921 {
922 digit_chars[c] = c;
923 mnemonic_chars[c] = c;
924 register_chars[c] = c;
925 operand_chars[c] = c;
926 }
3882b010 927 else if (ISLOWER (c))
252b5132
RH		 928 {
929 mnemonic_chars[c] = c;
930 register_chars[c] = c;
931 operand_chars[c] = c;
932 }
3882b010 933 else if (ISUPPER (c))
252b5132 934 {
3882b010 935 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 936 register_chars[c] = mnemonic_chars[c];
937 operand_chars[c] = c;
938 }
939
3882b010 940 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 941 identifier_chars[c] = c;
942 else if (c >= 128)
943 {
944 identifier_chars[c] = c;
945 operand_chars[c] = c;
946 }
947 }
948
949#ifdef LEX_AT
950 identifier_chars['@'] = '@';
951#endif
252b5132
RH		 952 digit_chars['-'] = '-';
953 identifier_chars['_'] = '_';
954 identifier_chars['.'] = '.';
955
956 for (p = operand_special_chars; *p != '\0'; p++)
957 operand_chars[(unsigned char) *p] = *p;
958 }
959
960#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
961 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
962 {
963 record_alignment (text_section, 2);
964 record_alignment (data_section, 2);
965 record_alignment (bss_section, 2);
966 }
967#endif
968}
969
970void
971i386_print_statistics (file)
972 FILE *file;
973{
974 hash_print_statistics (file, "i386 opcode", op_hash);
975 hash_print_statistics (file, "i386 register", reg_hash);
976}
977\f
252b5132
RH		 978#ifdef DEBUG386
979
ce8a8b2f 980/* Debugging routines for md_assemble. */
252b5132
RH		 981static void pi PARAMS ((char *, i386_insn *));
982static void pte PARAMS ((template *));
983static void pt PARAMS ((unsigned int));
984static void pe PARAMS ((expressionS *));
985static void ps PARAMS ((symbolS *));
986
987static void
988pi (line, x)
989 char *line;
990 i386_insn *x;
991{
09f131f2 992 unsigned int i;
252b5132
RH		 993
994 fprintf (stdout, "%s: template ", line);
995 pte (&x->tm);
09f131f2
JH		 996 fprintf (stdout, " address: base %s index %s scale %x\n",
997 x->base_reg ? x->base_reg->reg_name : "none",
998 x->index_reg ? x->index_reg->reg_name : "none",
999 x->log2_scale_factor);
1000 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1001 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1002 fprintf (stdout, " sib: base %x index %x scale %x\n",
1003 x->sib.base, x->sib.index, x->sib.scale);
1004 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1005 (x->rex & REX_MODE64) != 0,
1006 (x->rex & REX_EXTX) != 0,
1007 (x->rex & REX_EXTY) != 0,
1008 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1009 for (i = 0; i < x->operands; i++)
1010 {
1011 fprintf (stdout, " #%d: ", i + 1);
1012 pt (x->types[i]);
1013 fprintf (stdout, "\n");
1014 if (x->types[i]
3f4438ab 1015 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1016 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1017 if (x->types[i] & Imm)
520dc8e8 1018 pe (x->op[i].imms);
252b5132 1019 if (x->types[i] & Disp)
520dc8e8 1020 pe (x->op[i].disps);
252b5132
RH		 1021 }
1022}
1023
1024static void
1025pte (t)
1026 template *t;
1027{
09f131f2 1028 unsigned int i;
252b5132 1029 fprintf (stdout, " %d operands ", t->operands);
47926f60 1030 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1031 if (t->extension_opcode != None)
1032 fprintf (stdout, "ext %x ", t->extension_opcode);
1033 if (t->opcode_modifier & D)
1034 fprintf (stdout, "D");
1035 if (t->opcode_modifier & W)
1036 fprintf (stdout, "W");
1037 fprintf (stdout, "\n");
1038 for (i = 0; i < t->operands; i++)
1039 {
1040 fprintf (stdout, " #%d type ", i + 1);
1041 pt (t->operand_types[i]);
1042 fprintf (stdout, "\n");
1043 }
1044}
1045
1046static void
1047pe (e)
1048 expressionS *e;
1049{
24eab124 1050 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1051 fprintf (stdout, " add_number %ld (%lx)\n",
1052 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1053 if (e->X_add_symbol)
1054 {
1055 fprintf (stdout, " add_symbol ");
1056 ps (e->X_add_symbol);
1057 fprintf (stdout, "\n");
1058 }
1059 if (e->X_op_symbol)
1060 {
1061 fprintf (stdout, " op_symbol ");
1062 ps (e->X_op_symbol);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068ps (s)
1069 symbolS *s;
1070{
1071 fprintf (stdout, "%s type %s%s",
1072 S_GET_NAME (s),
1073 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1074 segment_name (S_GET_SEGMENT (s)));
1075}
1076
1077struct type_name
1078 {
1079 unsigned int mask;
1080 char *tname;
1081 }
1082
29b0f896 1083static const type_names[] =
252b5132
RH		 1084{
1085 { Reg8, "r8" },
1086 { Reg16, "r16" },
1087 { Reg32, "r32" },
09f131f2 1088 { Reg64, "r64" },
252b5132
RH		 1089 { Imm8, "i8" },
1090 { Imm8S, "i8s" },
1091 { Imm16, "i16" },
1092 { Imm32, "i32" },
09f131f2
JH		 1093 { Imm32S, "i32s" },
1094 { Imm64, "i64" },
252b5132
RH		 1095 { Imm1, "i1" },
1096 { BaseIndex, "BaseIndex" },
1097 { Disp8, "d8" },
1098 { Disp16, "d16" },
1099 { Disp32, "d32" },
09f131f2
JH		 1100 { Disp32S, "d32s" },
1101 { Disp64, "d64" },
252b5132
RH		 1102 { InOutPortReg, "InOutPortReg" },
1103 { ShiftCount, "ShiftCount" },
1104 { Control, "control reg" },
1105 { Test, "test reg" },
1106 { Debug, "debug reg" },
1107 { FloatReg, "FReg" },
1108 { FloatAcc, "FAcc" },
1109 { SReg2, "SReg2" },
1110 { SReg3, "SReg3" },
1111 { Acc, "Acc" },
1112 { JumpAbsolute, "Jump Absolute" },
1113 { RegMMX, "rMMX" },
3f4438ab 1114 { RegXMM, "rXMM" },
252b5132
RH		 1115 { EsSeg, "es" },
1116 { 0, "" }
1117};
1118
1119static void
1120pt (t)
1121 unsigned int t;
1122{
29b0f896 1123 const struct type_name *ty;
252b5132 1124
09f131f2
JH		 1125 for (ty = type_names; ty->mask; ty++)
1126 if (t & ty->mask)
1127 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1128 fflush (stdout);
1129}
1130
1131#endif /* DEBUG386 */
1132\f
252b5132 1133#ifdef BFD_ASSEMBLER
29b0f896
AM		 1134static bfd_reloc_code_real_type reloc
1135 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1136
1137static bfd_reloc_code_real_type
3e73aa7c 1138reloc (size, pcrel, sign, other)
252b5132
RH		 1139 int size;
1140 int pcrel;
3e73aa7c 1141 int sign;
252b5132
RH		 1142 bfd_reloc_code_real_type other;
1143{
47926f60
KH		 1144 if (other != NO_RELOC)
1145 return other;
252b5132
RH		 1146
1147 if (pcrel)
1148 {
3e73aa7c 1149 if (!sign)
e5cb08ac 1150 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1151 switch (size)
1152 {
1153 case 1: return BFD_RELOC_8_PCREL;
1154 case 2: return BFD_RELOC_16_PCREL;
1155 case 4: return BFD_RELOC_32_PCREL;
1156 }
d0b47220 1157 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1158 }
1159 else
1160 {
3e73aa7c 1161 if (sign)
e5cb08ac 1162 switch (size)
3e73aa7c
JH		 1163 {
1164 case 4: return BFD_RELOC_X86_64_32S;
1165 }
1166 else
1167 switch (size)
1168 {
1169 case 1: return BFD_RELOC_8;
1170 case 2: return BFD_RELOC_16;
1171 case 4: return BFD_RELOC_32;
1172 case 8: return BFD_RELOC_64;
1173 }
1174 as_bad (_("can not do %s %d byte relocation"),
1175 sign ? "signed" : "unsigned", size);
252b5132
RH		 1176 }
1177
bfb32b52 1178 abort ();
252b5132
RH		 1179 return BFD_RELOC_NONE;
1180}
1181
47926f60
KH		 1182/* Here we decide which fixups can be adjusted to make them relative to
1183 the beginning of the section instead of the symbol. Basically we need
1184 to make sure that the dynamic relocations are done correctly, so in
1185 some cases we force the original symbol to be used. */
1186
252b5132 1187int
c0c949c7 1188tc_i386_fix_adjustable (fixP)
47926f60 1189 fixS *fixP;
252b5132 1190{
6d249963 1191#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
79d292aa
ILT		 1192 /* Prevent all adjustments to global symbols, or else dynamic
1193 linking will not work correctly. */
b98ef147 1194 if (S_IS_EXTERNAL (fixP->fx_addsy)
3bf057fa
AS		 1195 || S_IS_WEAK (fixP->fx_addsy)
1196 /* Don't adjust pc-relative references to merge sections in 64-bit
1197 mode. */
1198 || (use_rela_relocations
1199 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1200 && fixP->fx_pcrel))
252b5132
RH		 1201 return 0;
1202#endif
ce8a8b2f 1203 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1204 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1205 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1206 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1207 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1208 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1209 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1210 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1211 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1212 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1213 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1214 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1215 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1216 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1217 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1218 return 0;
1219 return 1;
1220}
1221#else
ec56dfb4 1222#define reloc(SIZE,PCREL,SIGN,OTHER) 0
c6682705 1223#define BFD_RELOC_8 0
ec56dfb4
L		 1224#define BFD_RELOC_16 0
1225#define BFD_RELOC_32 0
c6682705 1226#define BFD_RELOC_8_PCREL 0
ec56dfb4
L		 1227#define BFD_RELOC_16_PCREL 0
1228#define BFD_RELOC_32_PCREL 0
1229#define BFD_RELOC_386_PLT32 0
1230#define BFD_RELOC_386_GOT32 0
1231#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1232#define BFD_RELOC_386_TLS_GD 0
1233#define BFD_RELOC_386_TLS_LDM 0
1234#define BFD_RELOC_386_TLS_LDO_32 0
1235#define BFD_RELOC_386_TLS_IE_32 0
1236#define BFD_RELOC_386_TLS_LE_32 0
1237#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1238#define BFD_RELOC_X86_64_PLT32 0
1239#define BFD_RELOC_X86_64_GOT32 0
1240#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1241#endif
1242
29b0f896 1243static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1244
1245static int
252b5132 1246intel_float_operand (mnemonic)
29b0f896 1247 const char *mnemonic;
252b5132 1248{
47926f60 1249 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1250 return 2;
252b5132
RH		 1251
1252 if (mnemonic[0] == 'f')
1253 return 1;
1254
1255 return 0;
1256}
1257
1258/* This is the guts of the machine-dependent assembler. LINE points to a
1259 machine dependent instruction. This function is supposed to emit
1260 the frags/bytes it assembles to. */
1261
1262void
1263md_assemble (line)
1264 char *line;
1265{
252b5132 1266 int j;
252b5132
RH		 1267 char mnemonic[MAX_MNEM_SIZE];
1268
47926f60 1269 /* Initialize globals. */
252b5132
RH		 1270 memset (&i, '\0', sizeof (i));
1271 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1272 i.reloc[j] = NO_RELOC;
252b5132
RH		 1273 memset (disp_expressions, '\0', sizeof (disp_expressions));
1274 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1275 save_stack_p = save_stack;
252b5132
RH		 1276
1277 /* First parse an instruction mnemonic & call i386_operand for the operands.
1278 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1279 start of a (possibly prefixed) mnemonic. */
252b5132 1280
29b0f896
AM		 1281 line = parse_insn (line, mnemonic);
1282 if (line == NULL)
1283 return;
252b5132 1284
29b0f896
AM		 1285 line = parse_operands (line, mnemonic);
1286 if (line == NULL)
1287 return;
252b5132 1288
29b0f896
AM		 1289 /* Now we've parsed the mnemonic into a set of templates, and have the
1290 operands at hand. */
1291
1292 /* All intel opcodes have reversed operands except for "bound" and
1293 "enter". We also don't reverse intersegment "jmp" and "call"
1294 instructions with 2 immediate operands so that the immediate segment
1295 precedes the offset, as it does when in AT&T mode. "enter" and the
1296 intersegment "jmp" and "call" instructions are the only ones that
1297 have two immediate operands. */
1298 if (intel_syntax && i.operands > 1
1299 && (strcmp (mnemonic, "bound") != 0)
1300 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1301 swap_operands ();
1302
1303 if (i.imm_operands)
1304 optimize_imm ();
1305
1306 if (i.disp_operands)
1307 optimize_disp ();
1308
1309 /* Next, we find a template that matches the given insn,
1310 making sure the overlap of the given operands types is consistent
1311 with the template operand types. */
252b5132 1312
29b0f896
AM		 1313 if (!match_template ())
1314 return;
252b5132 1315
cd61ebfe
AM		 1316 if (intel_syntax)
1317 {
1318 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1319 if (SYSV386_COMPAT
1320 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1321 i.tm.base_opcode ^= FloatR;
1322
1323 /* Zap movzx and movsx suffix. The suffix may have been set from
1324 "word ptr" or "byte ptr" on the source operand, but we'll use
1325 the suffix later to choose the destination register. */
1326 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1327 i.suffix = 0;
1328 }
24eab124 1329
29b0f896
AM		 1330 if (i.tm.opcode_modifier & FWait)
1331 if (!add_prefix (FWAIT_OPCODE))
1332 return;
252b5132 1333
29b0f896
AM		 1334 /* Check string instruction segment overrides. */
1335 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1336 {
1337 if (!check_string ())
5dd0794d 1338 return;
29b0f896 1339 }
5dd0794d 1340
29b0f896
AM		 1341 if (!process_suffix ())
1342 return;
e413e4e9 1343
29b0f896
AM		 1344 /* Make still unresolved immediate matches conform to size of immediate
1345 given in i.suffix. */
1346 if (!finalize_imm ())
1347 return;
252b5132 1348
29b0f896
AM		 1349 if (i.types[0] & Imm1)
1350 i.imm_operands = 0; /* kludge for shift insns. */
1351 if (i.types[0] & ImplicitRegister)
1352 i.reg_operands--;
1353 if (i.types[1] & ImplicitRegister)
1354 i.reg_operands--;
1355 if (i.types[2] & ImplicitRegister)
1356 i.reg_operands--;
252b5132 1357
29b0f896
AM		 1358 if (i.tm.opcode_modifier & ImmExt)
1359 {
1360 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1361 opcode suffix which is coded in the same place as an 8-bit
1362 immediate field would be. Here we fake an 8-bit immediate
1363 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1364
29b0f896 1365 expressionS *exp;
252b5132 1366
29b0f896 1367 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1368
29b0f896
AM		 1369 exp = &im_expressions[i.imm_operands++];
1370 i.op[i.operands].imms = exp;
1371 i.types[i.operands++] = Imm8;
1372 exp->X_op = O_constant;
1373 exp->X_add_number = i.tm.extension_opcode;
1374 i.tm.extension_opcode = None;
1375 }
252b5132 1376
29b0f896
AM		 1377 /* For insns with operands there are more diddles to do to the opcode. */
1378 if (i.operands)
1379 {
1380 if (!process_operands ())
1381 return;
1382 }
1383 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1384 {
1385 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1386 as_warn (_("translating to `%sp'"), i.tm.name);
1387 }
252b5132 1388
29b0f896
AM		 1389 /* Handle conversion of 'int $3' --> special int3 insn. */
1390 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1391 {
1392 i.tm.base_opcode = INT3_OPCODE;
1393 i.imm_operands = 0;
1394 }
252b5132 1395
29b0f896
AM		 1396 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1397 && i.op[0].disps->X_op == O_constant)
1398 {
1399 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1400 the absolute address given by the constant. Since ix86 jumps and
1401 calls are pc relative, we need to generate a reloc. */
1402 i.op[0].disps->X_add_symbol = &abs_symbol;
1403 i.op[0].disps->X_op = O_symbol;
1404 }
252b5132 1405
29b0f896
AM		 1406 if ((i.tm.opcode_modifier & Rex64) != 0)
1407 i.rex |= REX_MODE64;
252b5132 1408
29b0f896
AM		 1409 /* For 8 bit registers we need an empty rex prefix. Also if the
1410 instruction already has a prefix, we need to convert old
1411 registers to new ones. */
773f551c 1412
29b0f896
AM		 1413 if (((i.types[0] & Reg8) != 0
1414 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1415 || ((i.types[1] & Reg8) != 0
1416 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1417 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1418 && i.rex != 0))
1419 {
1420 int x;
726c5dcd 1421
29b0f896
AM		 1422 i.rex |= REX_OPCODE;
1423 for (x = 0; x < 2; x++)
1424 {
1425 /* Look for 8 bit operand that uses old registers. */
1426 if ((i.types[x] & Reg8) != 0
1427 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1428 {
29b0f896
AM		 1429 /* In case it is "hi" register, give up. */
1430 if (i.op[x].regs->reg_num > 3)
1431 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1432 i.op[x].regs->reg_name);
773f551c 1433
29b0f896
AM		 1434 /* Otherwise it is equivalent to the extended register.
1435 Since the encoding doesn't change this is merely
1436 cosmetic cleanup for debug output. */
1437
1438 i.op[x].regs = i.op[x].regs + 8;
773f551c 1439 }
29b0f896
AM		 1440 }
1441 }
773f551c 1442
29b0f896
AM		 1443 if (i.rex != 0)
1444 add_prefix (REX_OPCODE | i.rex);
1445
1446 /* We are ready to output the insn. */
1447 output_insn ();
1448}
1449
1450static char *
1451parse_insn (line, mnemonic)
1452 char *line;
1453 char *mnemonic;
1454{
1455 char *l = line;
1456 char *token_start = l;
1457 char *mnem_p;
1458
1459 /* Non-zero if we found a prefix only acceptable with string insns. */
1460 const char *expecting_string_instruction = NULL;
45288df1 1461
29b0f896
AM		 1462 while (1)
1463 {
1464 mnem_p = mnemonic;
1465 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1466 {
1467 mnem_p++;
1468 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1469 {
29b0f896
AM		 1470 as_bad (_("no such instruction: `%s'"), token_start);
1471 return NULL;
1472 }
1473 l++;
1474 }
1475 if (!is_space_char (*l)
1476 && *l != END_OF_INSN
1477 && *l != PREFIX_SEPARATOR
1478 && *l != ',')
1479 {
1480 as_bad (_("invalid character %s in mnemonic"),
1481 output_invalid (*l));
1482 return NULL;
1483 }
1484 if (token_start == l)
1485 {
1486 if (*l == PREFIX_SEPARATOR)
1487 as_bad (_("expecting prefix; got nothing"));
1488 else
1489 as_bad (_("expecting mnemonic; got nothing"));
1490 return NULL;
1491 }
45288df1 1492
29b0f896
AM		 1493 /* Look up instruction (or prefix) via hash table. */
1494 current_templates = hash_find (op_hash, mnemonic);
47926f60 1495
29b0f896
AM		 1496 if (*l != END_OF_INSN
1497 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1498 && current_templates
1499 && (current_templates->start->opcode_modifier & IsPrefix))
1500 {
1501 /* If we are in 16-bit mode, do not allow addr16 or data16.
1502 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1503 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1504 && flag_code != CODE_64BIT
1505 && (((current_templates->start->opcode_modifier & Size32) != 0)
1506 ^ (flag_code == CODE_16BIT)))
1507 {
1508 as_bad (_("redundant %s prefix"),
1509 current_templates->start->name);
1510 return NULL;
45288df1 1511 }
29b0f896
AM		 1512 /* Add prefix, checking for repeated prefixes. */
1513 switch (add_prefix (current_templates->start->base_opcode))
1514 {
1515 case 0:
1516 return NULL;
1517 case 2:
1518 expecting_string_instruction = current_templates->start->name;
1519 break;
1520 }
1521 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1522 token_start = ++l;
1523 }
1524 else
1525 break;
1526 }
45288df1 1527
29b0f896
AM		 1528 if (!current_templates)
1529 {
1530 /* See if we can get a match by trimming off a suffix. */
1531 switch (mnem_p[-1])
1532 {
1533 case WORD_MNEM_SUFFIX:
1534 case BYTE_MNEM_SUFFIX:
1535 case QWORD_MNEM_SUFFIX:
1536 i.suffix = mnem_p[-1];
1537 mnem_p[-1] = '\0';
1538 current_templates = hash_find (op_hash, mnemonic);
1539 break;
1540 case SHORT_MNEM_SUFFIX:
1541 case LONG_MNEM_SUFFIX:
1542 if (!intel_syntax)
1543 {
1544 i.suffix = mnem_p[-1];
1545 mnem_p[-1] = '\0';
1546 current_templates = hash_find (op_hash, mnemonic);
1547 }
1548 break;
252b5132 1549
29b0f896
AM		 1550 /* Intel Syntax. */
1551 case 'd':
1552 if (intel_syntax)
1553 {
1554 if (intel_float_operand (mnemonic))
1555 i.suffix = SHORT_MNEM_SUFFIX;
1556 else
1557 i.suffix = LONG_MNEM_SUFFIX;
1558 mnem_p[-1] = '\0';
1559 current_templates = hash_find (op_hash, mnemonic);
1560 }
1561 break;
1562 }
1563 if (!current_templates)
1564 {
1565 as_bad (_("no such instruction: `%s'"), token_start);
1566 return NULL;
1567 }
1568 }
252b5132 1569
29b0f896
AM		 1570 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1571 {
1572 /* Check for a branch hint. We allow ",pt" and ",pn" for
1573 predict taken and predict not taken respectively.
1574 I'm not sure that branch hints actually do anything on loop
1575 and jcxz insns (JumpByte) for current Pentium4 chips. They
1576 may work in the future and it doesn't hurt to accept them
1577 now. */
1578 if (l[0] == ',' && l[1] == 'p')
1579 {
1580 if (l[2] == 't')
1581 {
1582 if (!add_prefix (DS_PREFIX_OPCODE))
1583 return NULL;
1584 l += 3;
1585 }
1586 else if (l[2] == 'n')
1587 {
1588 if (!add_prefix (CS_PREFIX_OPCODE))
1589 return NULL;
1590 l += 3;
1591 }
1592 }
1593 }
1594 /* Any other comma loses. */
1595 if (*l == ',')
1596 {
1597 as_bad (_("invalid character %s in mnemonic"),
1598 output_invalid (*l));
1599 return NULL;
1600 }
252b5132 1601
29b0f896
AM		 1602 /* Check if instruction is supported on specified architecture. */
1603 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1604 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1605 {
1606 as_warn (_("`%s' is not supported on `%s'"),
1607 current_templates->start->name, cpu_arch_name);
1608 }
1609 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1610 {
1611 as_warn (_("use .code16 to ensure correct addressing mode"));
1612 }
252b5132 1613
29b0f896
AM		 1614 /* Check for rep/repne without a string instruction. */
1615 if (expecting_string_instruction
1616 && !(current_templates->start->opcode_modifier & IsString))
1617 {
1618 as_bad (_("expecting string instruction after `%s'"),
1619 expecting_string_instruction);
1620 return NULL;
1621 }
252b5132 1622
29b0f896
AM		 1623 return l;
1624}
252b5132 1625
29b0f896
AM		 1626static char *
1627parse_operands (l, mnemonic)
1628 char *l;
1629 const char *mnemonic;
1630{
1631 char *token_start;
3138f287 1632
29b0f896
AM		 1633 /* 1 if operand is pending after ','. */
1634 unsigned int expecting_operand = 0;
252b5132 1635
29b0f896
AM		 1636 /* Non-zero if operand parens not balanced. */
1637 unsigned int paren_not_balanced;
1638
1639 while (*l != END_OF_INSN)
1640 {
1641 /* Skip optional white space before operand. */
1642 if (is_space_char (*l))
1643 ++l;
1644 if (!is_operand_char (*l) && *l != END_OF_INSN)
1645 {
1646 as_bad (_("invalid character %s before operand %d"),
1647 output_invalid (*l),
1648 i.operands + 1);
1649 return NULL;
1650 }
1651 token_start = l; /* after white space */
1652 paren_not_balanced = 0;
1653 while (paren_not_balanced || *l != ',')
1654 {
1655 if (*l == END_OF_INSN)
1656 {
1657 if (paren_not_balanced)
1658 {
1659 if (!intel_syntax)
1660 as_bad (_("unbalanced parenthesis in operand %d."),
1661 i.operands + 1);
1662 else
1663 as_bad (_("unbalanced brackets in operand %d."),
1664 i.operands + 1);
1665 return NULL;
1666 }
1667 else
1668 break; /* we are done */
1669 }
1670 else if (!is_operand_char (*l) && !is_space_char (*l))
1671 {
1672 as_bad (_("invalid character %s in operand %d"),
1673 output_invalid (*l),
1674 i.operands + 1);
1675 return NULL;
1676 }
1677 if (!intel_syntax)
1678 {
1679 if (*l == '(')
1680 ++paren_not_balanced;
1681 if (*l == ')')
1682 --paren_not_balanced;
1683 }
1684 else
1685 {
1686 if (*l == '[')
1687 ++paren_not_balanced;
1688 if (*l == ']')
1689 --paren_not_balanced;
1690 }
1691 l++;
1692 }
1693 if (l != token_start)
1694 { /* Yes, we've read in another operand. */
1695 unsigned int operand_ok;
1696 this_operand = i.operands++;
1697 if (i.operands > MAX_OPERANDS)
1698 {
1699 as_bad (_("spurious operands; (%d operands/instruction max)"),
1700 MAX_OPERANDS);
1701 return NULL;
1702 }
1703 /* Now parse operand adding info to 'i' as we go along. */
1704 END_STRING_AND_SAVE (l);
1705
1706 if (intel_syntax)
1707 operand_ok =
1708 i386_intel_operand (token_start,
1709 intel_float_operand (mnemonic));
1710 else
1711 operand_ok = i386_operand (token_start);
1712
1713 RESTORE_END_STRING (l);
1714 if (!operand_ok)
1715 return NULL;
1716 }
1717 else
1718 {
1719 if (expecting_operand)
1720 {
1721 expecting_operand_after_comma:
1722 as_bad (_("expecting operand after ','; got nothing"));
1723 return NULL;
1724 }
1725 if (*l == ',')
1726 {
1727 as_bad (_("expecting operand before ','; got nothing"));
1728 return NULL;
1729 }
1730 }
7f3f1ea2 1731
29b0f896
AM		 1732 /* Now *l must be either ',' or END_OF_INSN. */
1733 if (*l == ',')
1734 {
1735 if (*++l == END_OF_INSN)
1736 {
1737 /* Just skip it, if it's \n complain. */
1738 goto expecting_operand_after_comma;
1739 }
1740 expecting_operand = 1;
1741 }
1742 }
1743 return l;
1744}
7f3f1ea2 1745
29b0f896
AM		 1746static void
1747swap_operands ()
1748{
1749 union i386_op temp_op;
1750 unsigned int temp_type;
1751 RELOC_ENUM temp_reloc;
1752 int xchg1 = 0;
1753 int xchg2 = 0;
252b5132 1754
29b0f896
AM		 1755 if (i.operands == 2)
1756 {
1757 xchg1 = 0;
1758 xchg2 = 1;
1759 }
1760 else if (i.operands == 3)
1761 {
1762 xchg1 = 0;
1763 xchg2 = 2;
1764 }
1765 temp_type = i.types[xchg2];
1766 i.types[xchg2] = i.types[xchg1];
1767 i.types[xchg1] = temp_type;
1768 temp_op = i.op[xchg2];
1769 i.op[xchg2] = i.op[xchg1];
1770 i.op[xchg1] = temp_op;
1771 temp_reloc = i.reloc[xchg2];
1772 i.reloc[xchg2] = i.reloc[xchg1];
1773 i.reloc[xchg1] = temp_reloc;
1774
1775 if (i.mem_operands == 2)
1776 {
1777 const seg_entry *temp_seg;
1778 temp_seg = i.seg[0];
1779 i.seg[0] = i.seg[1];
1780 i.seg[1] = temp_seg;
1781 }
1782}
252b5132 1783
29b0f896
AM		 1784/* Try to ensure constant immediates are represented in the smallest
1785 opcode possible. */
1786static void
1787optimize_imm ()
1788{
1789 char guess_suffix = 0;
1790 int op;
252b5132 1791
29b0f896
AM		 1792 if (i.suffix)
1793 guess_suffix = i.suffix;
1794 else if (i.reg_operands)
1795 {
1796 /* Figure out a suffix from the last register operand specified.
1797 We can't do this properly yet, ie. excluding InOutPortReg,
1798 but the following works for instructions with immediates.
1799 In any case, we can't set i.suffix yet. */
1800 for (op = i.operands; --op >= 0;)
1801 if (i.types[op] & Reg)
252b5132 1802 {
29b0f896
AM		 1803 if (i.types[op] & Reg8)
1804 guess_suffix = BYTE_MNEM_SUFFIX;
1805 else if (i.types[op] & Reg16)
1806 guess_suffix = WORD_MNEM_SUFFIX;
1807 else if (i.types[op] & Reg32)
1808 guess_suffix = LONG_MNEM_SUFFIX;
1809 else if (i.types[op] & Reg64)
1810 guess_suffix = QWORD_MNEM_SUFFIX;
1811 break;
252b5132 1812 }
29b0f896
AM		 1813 }
1814 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1815 guess_suffix = WORD_MNEM_SUFFIX;
1816
1817 for (op = i.operands; --op >= 0;)
1818 if (i.types[op] & Imm)
1819 {
1820 switch (i.op[op].imms->X_op)
252b5132 1821 {
29b0f896
AM		 1822 case O_constant:
1823 /* If a suffix is given, this operand may be shortened. */
1824 switch (guess_suffix)
252b5132 1825 {
29b0f896
AM		 1826 case LONG_MNEM_SUFFIX:
1827 i.types[op] |= Imm32 | Imm64;
1828 break;
1829 case WORD_MNEM_SUFFIX:
1830 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1831 break;
1832 case BYTE_MNEM_SUFFIX:
1833 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1834 break;
252b5132 1835 }
252b5132 1836
29b0f896
AM		 1837 /* If this operand is at most 16 bits, convert it
1838 to a signed 16 bit number before trying to see
1839 whether it will fit in an even smaller size.
1840 This allows a 16-bit operand such as $0xffe0 to
1841 be recognised as within Imm8S range. */
1842 if ((i.types[op] & Imm16)
1843 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1844 {
29b0f896
AM		 1845 i.op[op].imms->X_add_number =
1846 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1847 }
1848 if ((i.types[op] & Imm32)
1849 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1850 == 0))
1851 {
1852 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1853 ^ ((offsetT) 1 << 31))
1854 - ((offsetT) 1 << 31));
1855 }
1856 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1857
29b0f896
AM		 1858 /* We must avoid matching of Imm32 templates when 64bit
1859 only immediate is available. */
1860 if (guess_suffix == QWORD_MNEM_SUFFIX)
1861 i.types[op] &= ~Imm32;
1862 break;
252b5132 1863
29b0f896
AM		 1864 case O_absent:
1865 case O_register:
1866 abort ();
1867
1868 /* Symbols and expressions. */
1869 default:
1870 /* Convert symbolic operand to proper sizes for matching. */
1871 switch (guess_suffix)
1872 {
1873 case QWORD_MNEM_SUFFIX:
1874 i.types[op] = Imm64 | Imm32S;
1875 break;
1876 case LONG_MNEM_SUFFIX:
1877 i.types[op] = Imm32 | Imm64;
1878 break;
1879 case WORD_MNEM_SUFFIX:
1880 i.types[op] = Imm16 | Imm32 | Imm64;
1881 break;
1882 break;
1883 case BYTE_MNEM_SUFFIX:
1884 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1885 break;
1886 break;
252b5132 1887 }
29b0f896 1888 break;
252b5132 1889 }
29b0f896
AM		 1890 }
1891}
47926f60 1892
29b0f896
AM		 1893/* Try to use the smallest displacement type too. */
1894static void
1895optimize_disp ()
1896{
1897 int op;
3e73aa7c 1898
29b0f896
AM		 1899 for (op = i.operands; --op >= 0;)
1900 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1901 {
29b0f896
AM		 1902 offsetT disp = i.op[op].disps->X_add_number;
1903
1904 if (i.types[op] & Disp16)
252b5132 1905 {
29b0f896
AM		 1906 /* We know this operand is at most 16 bits, so
1907 convert to a signed 16 bit number before trying
1908 to see whether it will fit in an even smaller
1909 size. */
1910
1911 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1912 }
29b0f896 1913 else if (i.types[op] & Disp32)
252b5132 1914 {
29b0f896
AM		 1915 /* We know this operand is at most 32 bits, so convert to a
1916 signed 32 bit number before trying to see whether it will
1917 fit in an even smaller size. */
1918 disp &= (((offsetT) 2 << 31) - 1);
1919 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1920 }
29b0f896 1921 if (flag_code == CODE_64BIT)
252b5132 1922 {
29b0f896
AM		 1923 if (fits_in_signed_long (disp))
1924 i.types[op] |= Disp32S;
1925 if (fits_in_unsigned_long (disp))
1926 i.types[op] |= Disp32;
252b5132 1927 }
29b0f896
AM		 1928 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1929 && fits_in_signed_byte (disp))
1930 i.types[op] |= Disp8;
252b5132 1931 }
29b0f896
AM		 1932}
1933
1934static int
1935match_template ()
1936{
1937 /* Points to template once we've found it. */
1938 const template *t;
1939 unsigned int overlap0, overlap1, overlap2;
1940 unsigned int found_reverse_match;
1941 int suffix_check;
1942
1943#define MATCH(overlap, given, template) \
1944 ((overlap & ~JumpAbsolute) \
1945 && (((given) & (BaseIndex | JumpAbsolute)) \
1946 == ((overlap) & (BaseIndex | JumpAbsolute))))
1947
1948 /* If given types r0 and r1 are registers they must be of the same type
1949 unless the expected operand type register overlap is null.
1950 Note that Acc in a template matches every size of reg. */
1951#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1952 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1953 || ((g0) & Reg) == ((g1) & Reg) \
1954 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1955
1956 overlap0 = 0;
1957 overlap1 = 0;
1958 overlap2 = 0;
1959 found_reverse_match = 0;
1960 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1961 ? No_bSuf
1962 : (i.suffix == WORD_MNEM_SUFFIX
1963 ? No_wSuf
1964 : (i.suffix == SHORT_MNEM_SUFFIX
1965 ? No_sSuf
1966 : (i.suffix == LONG_MNEM_SUFFIX
1967 ? No_lSuf
1968 : (i.suffix == QWORD_MNEM_SUFFIX
1969 ? No_qSuf
1970 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1971 ? No_xSuf : 0))))));
1972
1973 for (t = current_templates->start;
1974 t < current_templates->end;
1975 t++)
1976 {
1977 /* Must have right number of operands. */
1978 if (i.operands != t->operands)
1979 continue;
1980
1981 /* Check the suffix, except for some instructions in intel mode. */
1982 if ((t->opcode_modifier & suffix_check)
1983 && !(intel_syntax
1984 && (t->opcode_modifier & IgnoreSize))
1985 && !(intel_syntax
1986 && t->base_opcode == 0xd9
1987 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1988 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1989 continue;
1990
1991 /* Do not verify operands when there are none. */
1992 else if (!t->operands)
1993 {
1994 if (t->cpu_flags & ~cpu_arch_flags)
1995 continue;
1996 /* We've found a match; break out of loop. */
1997 break;
1998 }
252b5132 1999
29b0f896
AM		 2000 overlap0 = i.types[0] & t->operand_types[0];
2001 switch (t->operands)
2002 {
2003 case 1:
2004 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2005 continue;
2006 break;
2007 case 2:
2008 case 3:
2009 overlap1 = i.types[1] & t->operand_types[1];
2010 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2011 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2012 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2013 t->operand_types[0],
2014 overlap1, i.types[1],
2015 t->operand_types[1]))
2016 {
2017 /* Check if other direction is valid ... */
2018 if ((t->opcode_modifier & (D | FloatD)) == 0)
2019 continue;
2020
2021 /* Try reversing direction of operands. */
2022 overlap0 = i.types[0] & t->operand_types[1];
2023 overlap1 = i.types[1] & t->operand_types[0];
2024 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2025 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2026 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2027 t->operand_types[1],
2028 overlap1, i.types[1],
2029 t->operand_types[0]))
2030 {
2031 /* Does not match either direction. */
2032 continue;
2033 }
2034 /* found_reverse_match holds which of D or FloatDR
2035 we've found. */
2036 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2037 }
2038 /* Found a forward 2 operand match here. */
2039 else if (t->operands == 3)
2040 {
2041 /* Here we make use of the fact that there are no
2042 reverse match 3 operand instructions, and all 3
2043 operand instructions only need to be checked for
2044 register consistency between operands 2 and 3. */
2045 overlap2 = i.types[2] & t->operand_types[2];
2046 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2047 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2048 t->operand_types[1],
2049 overlap2, i.types[2],
2050 t->operand_types[2]))
2051
2052 continue;
2053 }
2054 /* Found either forward/reverse 2 or 3 operand match here:
2055 slip through to break. */
2056 }
2057 if (t->cpu_flags & ~cpu_arch_flags)
2058 {
2059 found_reverse_match = 0;
2060 continue;
2061 }
2062 /* We've found a match; break out of loop. */
2063 break;
2064 }
2065
2066 if (t == current_templates->end)
2067 {
2068 /* We found no match. */
2069 as_bad (_("suffix or operands invalid for `%s'"),
2070 current_templates->start->name);
2071 return 0;
2072 }
252b5132 2073
29b0f896
AM		 2074 if (!quiet_warnings)
2075 {
2076 if (!intel_syntax
2077 && ((i.types[0] & JumpAbsolute)
2078 != (t->operand_types[0] & JumpAbsolute)))
2079 {
2080 as_warn (_("indirect %s without `*'"), t->name);
2081 }
2082
2083 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2084 == (IsPrefix | IgnoreSize))
2085 {
2086 /* Warn them that a data or address size prefix doesn't
2087 affect assembly of the next line of code. */
2088 as_warn (_("stand-alone `%s' prefix"), t->name);
2089 }
2090 }
2091
2092 /* Copy the template we found. */
2093 i.tm = *t;
2094 if (found_reverse_match)
2095 {
2096 /* If we found a reverse match we must alter the opcode
2097 direction bit. found_reverse_match holds bits to change
2098 (different for int & float insns). */
2099
2100 i.tm.base_opcode ^= found_reverse_match;
2101
2102 i.tm.operand_types[0] = t->operand_types[1];
2103 i.tm.operand_types[1] = t->operand_types[0];
2104 }
2105
2106 return 1;
2107}
2108
2109static int
2110check_string ()
2111{
2112 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2113 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2114 {
2115 if (i.seg[0] != NULL && i.seg[0] != &es)
2116 {
2117 as_bad (_("`%s' operand %d must use `%%es' segment"),
2118 i.tm.name,
2119 mem_op + 1);
2120 return 0;
2121 }
2122 /* There's only ever one segment override allowed per instruction.
2123 This instruction possibly has a legal segment override on the
2124 second operand, so copy the segment to where non-string
2125 instructions store it, allowing common code. */
2126 i.seg[0] = i.seg[1];
2127 }
2128 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2129 {
2130 if (i.seg[1] != NULL && i.seg[1] != &es)
2131 {
2132 as_bad (_("`%s' operand %d must use `%%es' segment"),
2133 i.tm.name,
2134 mem_op + 2);
2135 return 0;
2136 }
2137 }
2138 return 1;
2139}
2140
2141static int
2142process_suffix ()
2143{
2144 /* If matched instruction specifies an explicit instruction mnemonic
2145 suffix, use it. */
2146 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2147 {
2148 if (i.tm.opcode_modifier & Size16)
2149 i.suffix = WORD_MNEM_SUFFIX;
2150 else if (i.tm.opcode_modifier & Size64)
2151 i.suffix = QWORD_MNEM_SUFFIX;
2152 else
2153 i.suffix = LONG_MNEM_SUFFIX;
2154 }
2155 else if (i.reg_operands)
2156 {
2157 /* If there's no instruction mnemonic suffix we try to invent one
2158 based on register operands. */
2159 if (!i.suffix)
2160 {
2161 /* We take i.suffix from the last register operand specified,
2162 Destination register type is more significant than source
2163 register type. */
2164 int op;
2165 for (op = i.operands; --op >= 0;)
2166 if ((i.types[op] & Reg)
2167 && !(i.tm.operand_types[op] & InOutPortReg))
2168 {
2169 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2170 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2171 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2172 LONG_MNEM_SUFFIX);
2173 break;
2174 }
2175 }
2176 else if (i.suffix == BYTE_MNEM_SUFFIX)
2177 {
2178 if (!check_byte_reg ())
2179 return 0;
2180 }
2181 else if (i.suffix == LONG_MNEM_SUFFIX)
2182 {
2183 if (!check_long_reg ())
2184 return 0;
2185 }
2186 else if (i.suffix == QWORD_MNEM_SUFFIX)
2187 {
2188 if (!check_qword_reg ())
2189 return 0;
2190 }
2191 else if (i.suffix == WORD_MNEM_SUFFIX)
2192 {
2193 if (!check_word_reg ())
2194 return 0;
2195 }
2196 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2197 /* Do nothing if the instruction is going to ignore the prefix. */
2198 ;
2199 else
2200 abort ();
2201 }
2202 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2203 {
2204 i.suffix = stackop_size;
2205 }
252b5132 2206
29b0f896
AM		 2207 /* Change the opcode based on the operand size given by i.suffix;
2208 We need not change things for byte insns. */
252b5132 2209
29b0f896
AM		 2210 if (!i.suffix && (i.tm.opcode_modifier & W))
2211 {
2212 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2213 return 0;
2214 }
252b5132 2215
29b0f896
AM		 2216 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2217 {
2218 /* It's not a byte, select word/dword operation. */
2219 if (i.tm.opcode_modifier & W)
2220 {
2221 if (i.tm.opcode_modifier & ShortForm)
2222 i.tm.base_opcode |= 8;
2223 else
2224 i.tm.base_opcode |= 1;
2225 }
0f3f3d8b 2226
29b0f896
AM		 2227 /* Now select between word & dword operations via the operand
2228 size prefix, except for instructions that will ignore this
2229 prefix anyway. */
2230 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2231 && !(i.tm.opcode_modifier & IgnoreSize)
2232 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2233 || (flag_code == CODE_64BIT
2234 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2235 {
2236 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2237 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2238 prefix = ADDR_PREFIX_OPCODE;
252b5132 2239
29b0f896
AM		 2240 if (!add_prefix (prefix))
2241 return 0;
24eab124 2242 }
252b5132 2243
29b0f896
AM		 2244 /* Set mode64 for an operand. */
2245 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2246 && flag_code == CODE_64BIT
29b0f896 2247 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2248 i.rex |= REX_MODE64;
3e73aa7c 2249
29b0f896
AM		 2250 /* Size floating point instruction. */
2251 if (i.suffix == LONG_MNEM_SUFFIX)
2252 {
2253 if (i.tm.opcode_modifier & FloatMF)
2254 i.tm.base_opcode ^= 4;
2255 }
2256 }
7ecd2f8b 2257
29b0f896
AM		 2258 return 1;
2259}
3e73aa7c 2260
29b0f896
AM		 2261static int
2262check_byte_reg ()
2263{
2264 int op;
2265 for (op = i.operands; --op >= 0;)
2266 {
2267 /* If this is an eight bit register, it's OK. If it's the 16 or
2268 32 bit version of an eight bit register, we will just use the
2269 low portion, and that's OK too. */
2270 if (i.types[op] & Reg8)
2271 continue;
2272
2273 /* movzx and movsx should not generate this warning. */
2274 if (intel_syntax
2275 && (i.tm.base_opcode == 0xfb7
2276 || i.tm.base_opcode == 0xfb6
2277 || i.tm.base_opcode == 0x63
2278 || i.tm.base_opcode == 0xfbe
2279 || i.tm.base_opcode == 0xfbf))
2280 continue;
2281
2282 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2283#if 0
2284 /* Check that the template allows eight bit regs. This
2285 kills insns such as `orb $1,%edx', which maybe should be
2286 allowed. */
2287 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2288#endif
2289 )
2290 {
2291 /* Prohibit these changes in the 64bit mode, since the
2292 lowering is more complicated. */
2293 if (flag_code == CODE_64BIT
2294 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2295 {
0f3f3d8b 2296 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2297 i.op[op].regs->reg_name,
2298 i.suffix);
2299 return 0;
2300 }
2301#if REGISTER_WARNINGS
2302 if (!quiet_warnings
2303 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2304 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2305 (i.op[op].regs + (i.types[op] & Reg16
2306 ? REGNAM_AL - REGNAM_AX
2307 : REGNAM_AL - REGNAM_EAX))->reg_name,
2308 i.op[op].regs->reg_name,
2309 i.suffix);
2310#endif
2311 continue;
2312 }
2313 /* Any other register is bad. */
2314 if (i.types[op] & (Reg | RegMMX | RegXMM
2315 | SReg2 | SReg3
2316 | Control | Debug | Test
2317 | FloatReg | FloatAcc))
2318 {
2319 as_bad (_("`%%%s' not allowed with `%s%c'"),
2320 i.op[op].regs->reg_name,
2321 i.tm.name,
2322 i.suffix);
2323 return 0;
2324 }
2325 }
2326 return 1;
2327}
2328
2329static int
2330check_long_reg ()
2331{
2332 int op;
2333
2334 for (op = i.operands; --op >= 0;)
2335 /* Reject eight bit registers, except where the template requires
2336 them. (eg. movzb) */
2337 if ((i.types[op] & Reg8) != 0
2338 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2339 {
2340 as_bad (_("`%%%s' not allowed with `%s%c'"),
2341 i.op[op].regs->reg_name,
2342 i.tm.name,
2343 i.suffix);
2344 return 0;
2345 }
2346 /* Warn if the e prefix on a general reg is missing. */
2347 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2348 && (i.types[op] & Reg16) != 0
2349 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2350 {
2351 /* Prohibit these changes in the 64bit mode, since the
2352 lowering is more complicated. */
2353 if (flag_code == CODE_64BIT)
252b5132 2354 {
0f3f3d8b 2355 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2356 i.op[op].regs->reg_name,
2357 i.suffix);
2358 return 0;
252b5132 2359 }
29b0f896
AM		 2360#if REGISTER_WARNINGS
2361 else
2362 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2363 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2364 i.op[op].regs->reg_name,
2365 i.suffix);
2366#endif
252b5132 2367 }
29b0f896
AM		 2368 /* Warn if the r prefix on a general reg is missing. */
2369 else if ((i.types[op] & Reg64) != 0
2370 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2371 {
0f3f3d8b 2372 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2373 i.op[op].regs->reg_name,
2374 i.suffix);
2375 return 0;
2376 }
2377 return 1;
2378}
252b5132 2379
29b0f896
AM		 2380static int
2381check_qword_reg ()
2382{
2383 int op;
252b5132 2384
29b0f896
AM		 2385 for (op = i.operands; --op >= 0; )
2386 /* Reject eight bit registers, except where the template requires
2387 them. (eg. movzb) */
2388 if ((i.types[op] & Reg8) != 0
2389 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2390 {
2391 as_bad (_("`%%%s' not allowed with `%s%c'"),
2392 i.op[op].regs->reg_name,
2393 i.tm.name,
2394 i.suffix);
2395 return 0;
2396 }
2397 /* Warn if the e prefix on a general reg is missing. */
2398 else if (((i.types[op] & Reg16) != 0
2399 || (i.types[op] & Reg32) != 0)
2400 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2401 {
2402 /* Prohibit these changes in the 64bit mode, since the
2403 lowering is more complicated. */
0f3f3d8b 2404 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2405 i.op[op].regs->reg_name,
2406 i.suffix);
2407 return 0;
252b5132 2408 }
29b0f896
AM		 2409 return 1;
2410}
252b5132 2411
29b0f896
AM		 2412static int
2413check_word_reg ()
2414{
2415 int op;
2416 for (op = i.operands; --op >= 0;)
2417 /* Reject eight bit registers, except where the template requires
2418 them. (eg. movzb) */
2419 if ((i.types[op] & Reg8) != 0
2420 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2421 {
2422 as_bad (_("`%%%s' not allowed with `%s%c'"),
2423 i.op[op].regs->reg_name,
2424 i.tm.name,
2425 i.suffix);
2426 return 0;
2427 }
2428 /* Warn if the e prefix on a general reg is present. */
2429 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2430 && (i.types[op] & Reg32) != 0
2431 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2432 {
29b0f896
AM		 2433 /* Prohibit these changes in the 64bit mode, since the
2434 lowering is more complicated. */
2435 if (flag_code == CODE_64BIT)
252b5132 2436 {
0f3f3d8b 2437 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2438 i.op[op].regs->reg_name,
2439 i.suffix);
2440 return 0;
252b5132 2441 }
29b0f896
AM		 2442 else
2443#if REGISTER_WARNINGS
2444 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2445 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2446 i.op[op].regs->reg_name,
2447 i.suffix);
2448#endif
2449 }
2450 return 1;
2451}
252b5132 2452
29b0f896
AM		 2453static int
2454finalize_imm ()
2455{
2456 unsigned int overlap0, overlap1, overlap2;
2457
2458 overlap0 = i.types[0] & i.tm.operand_types[0];
2459 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2460 && overlap0 != Imm8 && overlap0 != Imm8S
2461 && overlap0 != Imm16 && overlap0 != Imm32S
2462 && overlap0 != Imm32 && overlap0 != Imm64)
2463 {
2464 if (i.suffix)
2465 {
2466 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2467 ? Imm8 | Imm8S
2468 : (i.suffix == WORD_MNEM_SUFFIX
2469 ? Imm16
2470 : (i.suffix == QWORD_MNEM_SUFFIX
2471 ? Imm64 | Imm32S
2472 : Imm32)));
2473 }
2474 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2475 || overlap0 == (Imm16 | Imm32)
2476 || overlap0 == (Imm16 | Imm32S))
2477 {
2478 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2479 ? Imm16 : Imm32S);
2480 }
2481 if (overlap0 != Imm8 && overlap0 != Imm8S
2482 && overlap0 != Imm16 && overlap0 != Imm32S
2483 && overlap0 != Imm32 && overlap0 != Imm64)
2484 {
2485 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2486 return 0;
2487 }
2488 }
2489 i.types[0] = overlap0;
2490
2491 overlap1 = i.types[1] & i.tm.operand_types[1];
2492 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2493 && overlap1 != Imm8 && overlap1 != Imm8S
2494 && overlap1 != Imm16 && overlap1 != Imm32S
2495 && overlap1 != Imm32 && overlap1 != Imm64)
2496 {
2497 if (i.suffix)
2498 {
2499 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2500 ? Imm8 | Imm8S
2501 : (i.suffix == WORD_MNEM_SUFFIX
2502 ? Imm16
2503 : (i.suffix == QWORD_MNEM_SUFFIX
2504 ? Imm64 | Imm32S
2505 : Imm32)));
2506 }
2507 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2508 || overlap1 == (Imm16 | Imm32)
2509 || overlap1 == (Imm16 | Imm32S))
2510 {
2511 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2512 ? Imm16 : Imm32S);
2513 }
2514 if (overlap1 != Imm8 && overlap1 != Imm8S
2515 && overlap1 != Imm16 && overlap1 != Imm32S
2516 && overlap1 != Imm32 && overlap1 != Imm64)
2517 {
2518 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2519 return 0;
2520 }
2521 }
2522 i.types[1] = overlap1;
2523
2524 overlap2 = i.types[2] & i.tm.operand_types[2];
2525 assert ((overlap2 & Imm) == 0);
2526 i.types[2] = overlap2;
2527
2528 return 1;
2529}
2530
2531static int
2532process_operands ()
2533{
2534 /* Default segment register this instruction will use for memory
2535 accesses. 0 means unknown. This is only for optimizing out
2536 unnecessary segment overrides. */
2537 const seg_entry *default_seg = 0;
2538
2539 /* The imul $imm, %reg instruction is converted into
2540 imul $imm, %reg, %reg, and the clr %reg instruction
2541 is converted into xor %reg, %reg. */
2542 if (i.tm.opcode_modifier & regKludge)
2543 {
2544 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2545 /* Pretend we saw the extra register operand. */
2546 assert (i.op[first_reg_op + 1].regs == 0);
2547 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2548 i.types[first_reg_op + 1] = i.types[first_reg_op];
2549 i.reg_operands = 2;
2550 }
2551
2552 if (i.tm.opcode_modifier & ShortForm)
2553 {
2554 /* The register or float register operand is in operand 0 or 1. */
2555 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2556 /* Register goes in low 3 bits of opcode. */
2557 i.tm.base_opcode |= i.op[op].regs->reg_num;
2558 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2559 i.rex |= REX_EXTZ;
2560 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2561 {
2562 /* Warn about some common errors, but press on regardless.
2563 The first case can be generated by gcc (<= 2.8.1). */
2564 if (i.operands == 2)
2565 {
2566 /* Reversed arguments on faddp, fsubp, etc. */
2567 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2568 i.op[1].regs->reg_name,
2569 i.op[0].regs->reg_name);
2570 }
2571 else
2572 {
2573 /* Extraneous `l' suffix on fp insn. */
2574 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2575 i.op[0].regs->reg_name);
2576 }
2577 }
2578 }
2579 else if (i.tm.opcode_modifier & Modrm)
2580 {
2581 /* The opcode is completed (modulo i.tm.extension_opcode which
2582 must be put into the modrm byte).
2583 Now, we make the modrm & index base bytes based on all the
2584 info we've collected. */
2585
2586 default_seg = build_modrm_byte ();
2587 }
2588 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2589 {
2590 if (i.tm.base_opcode == POP_SEG_SHORT
2591 && i.op[0].regs->reg_num == 1)
2592 {
2593 as_bad (_("you can't `pop %%cs'"));
2594 return 0;
2595 }
2596 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2597 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2598 i.rex |= REX_EXTZ;
2599 }
2600 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2601 {
2602 default_seg = &ds;
2603 }
2604 else if ((i.tm.opcode_modifier & IsString) != 0)
2605 {
2606 /* For the string instructions that allow a segment override
2607 on one of their operands, the default segment is ds. */
2608 default_seg = &ds;
2609 }
2610
2611 /* If a segment was explicitly specified,
2612 and the specified segment is not the default,
2613 use an opcode prefix to select it.
2614 If we never figured out what the default segment is,
2615 then default_seg will be zero at this point,
2616 and the specified segment prefix will always be used. */
2617 if ((i.seg[0]) && (i.seg[0] != default_seg))
2618 {
2619 if (!add_prefix (i.seg[0]->seg_prefix))
2620 return 0;
2621 }
2622 return 1;
2623}
2624
2625static const seg_entry *
2626build_modrm_byte ()
2627{
2628 const seg_entry *default_seg = 0;
2629
2630 /* i.reg_operands MUST be the number of real register operands;
2631 implicit registers do not count. */
2632 if (i.reg_operands == 2)
2633 {
2634 unsigned int source, dest;
2635 source = ((i.types[0]
2636 & (Reg | RegMMX | RegXMM
2637 | SReg2 | SReg3
2638 | Control | Debug | Test))
2639 ? 0 : 1);
2640 dest = source + 1;
2641
2642 i.rm.mode = 3;
2643 /* One of the register operands will be encoded in the i.tm.reg
2644 field, the other in the combined i.tm.mode and i.tm.regmem
2645 fields. If no form of this instruction supports a memory
2646 destination operand, then we assume the source operand may
2647 sometimes be a memory operand and so we need to store the
2648 destination in the i.rm.reg field. */
2649 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2650 {
2651 i.rm.reg = i.op[dest].regs->reg_num;
2652 i.rm.regmem = i.op[source].regs->reg_num;
2653 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2654 i.rex |= REX_EXTX;
2655 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2656 i.rex |= REX_EXTZ;
2657 }
2658 else
2659 {
2660 i.rm.reg = i.op[source].regs->reg_num;
2661 i.rm.regmem = i.op[dest].regs->reg_num;
2662 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2663 i.rex |= REX_EXTZ;
2664 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2665 i.rex |= REX_EXTX;
2666 }
2667 }
2668 else
2669 { /* If it's not 2 reg operands... */
2670 if (i.mem_operands)
2671 {
2672 unsigned int fake_zero_displacement = 0;
2673 unsigned int op = ((i.types[0] & AnyMem)
2674 ? 0
2675 : (i.types[1] & AnyMem) ? 1 : 2);
2676
2677 default_seg = &ds;
2678
2679 if (i.base_reg == 0)
2680 {
2681 i.rm.mode = 0;
2682 if (!i.disp_operands)
2683 fake_zero_displacement = 1;
2684 if (i.index_reg == 0)
2685 {
2686 /* Operand is just <disp> */
2687 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2688 && (flag_code != CODE_64BIT))
2689 {
2690 i.rm.regmem = NO_BASE_REGISTER_16;
2691 i.types[op] &= ~Disp;
2692 i.types[op] |= Disp16;
2693 }
2694 else if (flag_code != CODE_64BIT
2695 || (i.prefix[ADDR_PREFIX] != 0))
2696 {
2697 i.rm.regmem = NO_BASE_REGISTER;
2698 i.types[op] &= ~Disp;
2699 i.types[op] |= Disp32;
2700 }
2701 else
2702 {
2703 /* 64bit mode overwrites the 32bit absolute
2704 addressing by RIP relative addressing and
2705 absolute addressing is encoded by one of the
2706 redundant SIB forms. */
2707 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2708 i.sib.base = NO_BASE_REGISTER;
2709 i.sib.index = NO_INDEX_REGISTER;
2710 i.types[op] &= ~Disp;
2711 i.types[op] |= Disp32S;
2712 }
2713 }
2714 else /* !i.base_reg && i.index_reg */
2715 {
2716 i.sib.index = i.index_reg->reg_num;
2717 i.sib.base = NO_BASE_REGISTER;
2718 i.sib.scale = i.log2_scale_factor;
2719 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2720 i.types[op] &= ~Disp;
2721 if (flag_code != CODE_64BIT)
2722 i.types[op] |= Disp32; /* Must be 32 bit */
2723 else
2724 i.types[op] |= Disp32S;
2725 if ((i.index_reg->reg_flags & RegRex) != 0)
2726 i.rex |= REX_EXTY;
2727 }
2728 }
2729 /* RIP addressing for 64bit mode. */
2730 else if (i.base_reg->reg_type == BaseIndex)
2731 {
2732 i.rm.regmem = NO_BASE_REGISTER;
2733 i.types[op] &= ~Disp;
2734 i.types[op] |= Disp32S;
2735 i.flags[op] = Operand_PCrel;
2736 }
2737 else if (i.base_reg->reg_type & Reg16)
2738 {
2739 switch (i.base_reg->reg_num)
2740 {
2741 case 3: /* (%bx) */
2742 if (i.index_reg == 0)
2743 i.rm.regmem = 7;
2744 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2745 i.rm.regmem = i.index_reg->reg_num - 6;
2746 break;
2747 case 5: /* (%bp) */
2748 default_seg = &ss;
2749 if (i.index_reg == 0)
2750 {
2751 i.rm.regmem = 6;
2752 if ((i.types[op] & Disp) == 0)
2753 {
2754 /* fake (%bp) into 0(%bp) */
2755 i.types[op] |= Disp8;
252b5132 2756 fake_zero_displacement = 1;
29b0f896
AM		 2757 }
2758 }
2759 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2760 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2761 break;
2762 default: /* (%si) -> 4 or (%di) -> 5 */
2763 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2764 }
2765 i.rm.mode = mode_from_disp_size (i.types[op]);
2766 }
2767 else /* i.base_reg and 32/64 bit mode */
2768 {
2769 if (flag_code == CODE_64BIT
2770 && (i.types[op] & Disp))
2771 {
2772 if (i.types[op] & Disp8)
2773 i.types[op] = Disp8 | Disp32S;
2774 else
2775 i.types[op] = Disp32S;
2776 }
2777 i.rm.regmem = i.base_reg->reg_num;
2778 if ((i.base_reg->reg_flags & RegRex) != 0)
2779 i.rex |= REX_EXTZ;
2780 i.sib.base = i.base_reg->reg_num;
2781 /* x86-64 ignores REX prefix bit here to avoid decoder
2782 complications. */
2783 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2784 {
2785 default_seg = &ss;
2786 if (i.disp_operands == 0)
2787 {
2788 fake_zero_displacement = 1;
2789 i.types[op] |= Disp8;
2790 }
2791 }
2792 else if (i.base_reg->reg_num == ESP_REG_NUM)
2793 {
2794 default_seg = &ss;
2795 }
2796 i.sib.scale = i.log2_scale_factor;
2797 if (i.index_reg == 0)
2798 {
2799 /* <disp>(%esp) becomes two byte modrm with no index
2800 register. We've already stored the code for esp
2801 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2802 Any base register besides %esp will not use the
2803 extra modrm byte. */
2804 i.sib.index = NO_INDEX_REGISTER;
2805#if !SCALE1_WHEN_NO_INDEX
2806 /* Another case where we force the second modrm byte. */
2807 if (i.log2_scale_factor)
2808 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2809#endif
29b0f896
AM		 2810 }
2811 else
2812 {
2813 i.sib.index = i.index_reg->reg_num;
2814 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2815 if ((i.index_reg->reg_flags & RegRex) != 0)
2816 i.rex |= REX_EXTY;
2817 }
2818 i.rm.mode = mode_from_disp_size (i.types[op]);
2819 }
252b5132 2820
29b0f896
AM		 2821 if (fake_zero_displacement)
2822 {
2823 /* Fakes a zero displacement assuming that i.types[op]
2824 holds the correct displacement size. */
2825 expressionS *exp;
2826
2827 assert (i.op[op].disps == 0);
2828 exp = &disp_expressions[i.disp_operands++];
2829 i.op[op].disps = exp;
2830 exp->X_op = O_constant;
2831 exp->X_add_number = 0;
2832 exp->X_add_symbol = (symbolS *) 0;
2833 exp->X_op_symbol = (symbolS *) 0;
2834 }
2835 }
252b5132 2836
29b0f896
AM		 2837 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2838 (if any) based on i.tm.extension_opcode. Again, we must be
2839 careful to make sure that segment/control/debug/test/MMX
2840 registers are coded into the i.rm.reg field. */
2841 if (i.reg_operands)
2842 {
2843 unsigned int op =
2844 ((i.types[0]
2845 & (Reg | RegMMX | RegXMM
2846 | SReg2 | SReg3
2847 | Control | Debug | Test))
2848 ? 0
2849 : ((i.types[1]
2850 & (Reg | RegMMX | RegXMM
2851 | SReg2 | SReg3
2852 | Control | Debug | Test))
2853 ? 1
2854 : 2));
2855 /* If there is an extension opcode to put here, the register
2856 number must be put into the regmem field. */
2857 if (i.tm.extension_opcode != None)
2858 {
2859 i.rm.regmem = i.op[op].regs->reg_num;
2860 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2861 i.rex |= REX_EXTZ;
2862 }
2863 else
2864 {
2865 i.rm.reg = i.op[op].regs->reg_num;
2866 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2867 i.rex |= REX_EXTX;
2868 }
252b5132 2869
29b0f896
AM		 2870 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2871 must set it to 3 to indicate this is a register operand
2872 in the regmem field. */
2873 if (!i.mem_operands)
2874 i.rm.mode = 3;
2875 }
252b5132 2876
29b0f896
AM		 2877 /* Fill in i.rm.reg field with extension opcode (if any). */
2878 if (i.tm.extension_opcode != None)
2879 i.rm.reg = i.tm.extension_opcode;
2880 }
2881 return default_seg;
2882}
252b5132 2883
29b0f896
AM		 2884static void
2885output_branch ()
2886{
2887 char *p;
2888 int code16;
2889 int prefix;
2890 relax_substateT subtype;
2891 symbolS *sym;
2892 offsetT off;
2893
2894 code16 = 0;
2895 if (flag_code == CODE_16BIT)
2896 code16 = CODE16;
2897
2898 prefix = 0;
2899 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2900 {
29b0f896
AM		 2901 prefix = 1;
2902 i.prefixes -= 1;
2903 code16 ^= CODE16;
252b5132 2904 }
29b0f896
AM		 2905 /* Pentium4 branch hints. */
2906 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2907 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2908 {
29b0f896
AM		 2909 prefix++;
2910 i.prefixes--;
2911 }
2912 if (i.prefix[REX_PREFIX] != 0)
2913 {
2914 prefix++;
2915 i.prefixes--;
2f66722d
AM		 2916 }
2917
29b0f896
AM		 2918 if (i.prefixes != 0 && !intel_syntax)
2919 as_warn (_("skipping prefixes on this instruction"));
2920
2921 /* It's always a symbol; End frag & setup for relax.
2922 Make sure there is enough room in this frag for the largest
2923 instruction we may generate in md_convert_frag. This is 2
2924 bytes for the opcode and room for the prefix and largest
2925 displacement. */
2926 frag_grow (prefix + 2 + 4);
2927 /* Prefix and 1 opcode byte go in fr_fix. */
2928 p = frag_more (prefix + 1);
2929 if (i.prefix[DATA_PREFIX] != 0)
2930 *p++ = DATA_PREFIX_OPCODE;
2931 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2932 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2933 *p++ = i.prefix[SEG_PREFIX];
2934 if (i.prefix[REX_PREFIX] != 0)
2935 *p++ = i.prefix[REX_PREFIX];
2936 *p = i.tm.base_opcode;
2937
2938 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2939 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2940 else if ((cpu_arch_flags & Cpu386) != 0)
2941 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2942 else
2943 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2944 subtype |= code16;
3e73aa7c 2945
29b0f896
AM		 2946 sym = i.op[0].disps->X_add_symbol;
2947 off = i.op[0].disps->X_add_number;
3e73aa7c 2948
29b0f896
AM		 2949 if (i.op[0].disps->X_op != O_constant
2950 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2951 {
29b0f896
AM		 2952 /* Handle complex expressions. */
2953 sym = make_expr_symbol (i.op[0].disps);
2954 off = 0;
2955 }
3e73aa7c 2956
29b0f896
AM		 2957 /* 1 possible extra opcode + 4 byte displacement go in var part.
2958 Pass reloc in fr_var. */
2959 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2960}
3e73aa7c 2961
29b0f896
AM		 2962static void
2963output_jump ()
2964{
2965 char *p;
2966 int size;
2967
2968 if (i.tm.opcode_modifier & JumpByte)
2969 {
2970 /* This is a loop or jecxz type instruction. */
2971 size = 1;
2972 if (i.prefix[ADDR_PREFIX] != 0)
2973 {
2974 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2975 i.prefixes -= 1;
2976 }
2977 /* Pentium4 branch hints. */
2978 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2979 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2980 {
2981 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
2982 i.prefixes--;
3e73aa7c
JH		 2983 }
2984 }
29b0f896
AM		 2985 else
2986 {
2987 int code16;
3e73aa7c 2988
29b0f896
AM		 2989 code16 = 0;
2990 if (flag_code == CODE_16BIT)
2991 code16 = CODE16;
3e73aa7c 2992
29b0f896
AM		 2993 if (i.prefix[DATA_PREFIX] != 0)
2994 {
2995 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2996 i.prefixes -= 1;
2997 code16 ^= CODE16;
2998 }
252b5132 2999
29b0f896
AM		 3000 size = 4;
3001 if (code16)
3002 size = 2;
3003 }
9fcc94b6 3004
29b0f896
AM		 3005 if (i.prefix[REX_PREFIX] != 0)
3006 {
3007 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3008 i.prefixes -= 1;
3009 }
252b5132 3010
29b0f896
AM		 3011 if (i.prefixes != 0 && !intel_syntax)
3012 as_warn (_("skipping prefixes on this instruction"));
e0890092 3013
29b0f896
AM		 3014 p = frag_more (1 + size);
3015 *p++ = i.tm.base_opcode;
e0890092 3016
062cd5e7
AS		 3017 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3018 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3019}
e0890092 3020
29b0f896
AM		 3021static void
3022output_interseg_jump ()
3023{
3024 char *p;
3025 int size;
3026 int prefix;
3027 int code16;
252b5132 3028
29b0f896
AM		 3029 code16 = 0;
3030 if (flag_code == CODE_16BIT)
3031 code16 = CODE16;
a217f122 3032
29b0f896
AM		 3033 prefix = 0;
3034 if (i.prefix[DATA_PREFIX] != 0)
3035 {
3036 prefix = 1;
3037 i.prefixes -= 1;
3038 code16 ^= CODE16;
3039 }
3040 if (i.prefix[REX_PREFIX] != 0)
3041 {
3042 prefix++;
3043 i.prefixes -= 1;
3044 }
252b5132 3045
29b0f896
AM		 3046 size = 4;
3047 if (code16)
3048 size = 2;
252b5132 3049
29b0f896
AM		 3050 if (i.prefixes != 0 && !intel_syntax)
3051 as_warn (_("skipping prefixes on this instruction"));
252b5132 3052
29b0f896
AM		 3053 /* 1 opcode; 2 segment; offset */
3054 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3055
29b0f896
AM		 3056 if (i.prefix[DATA_PREFIX] != 0)
3057 *p++ = DATA_PREFIX_OPCODE;
252b5132 3058
29b0f896
AM		 3059 if (i.prefix[REX_PREFIX] != 0)
3060 *p++ = i.prefix[REX_PREFIX];
252b5132 3061
29b0f896
AM		 3062 *p++ = i.tm.base_opcode;
3063 if (i.op[1].imms->X_op == O_constant)
3064 {
3065 offsetT n = i.op[1].imms->X_add_number;
252b5132 3066
29b0f896
AM		 3067 if (size == 2
3068 && !fits_in_unsigned_word (n)
3069 && !fits_in_signed_word (n))
3070 {
3071 as_bad (_("16-bit jump out of range"));
3072 return;
3073 }
3074 md_number_to_chars (p, n, size);
3075 }
3076 else
3077 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3078 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3079 if (i.op[0].imms->X_op != O_constant)
3080 as_bad (_("can't handle non absolute segment in `%s'"),
3081 i.tm.name);
3082 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3083}
a217f122 3084
29b0f896
AM		 3085static void
3086output_insn ()
3087{
3088 /* Tie dwarf2 debug info to the address at the start of the insn.
3089 We can't do this after the insn has been output as the current
3090 frag may have been closed off. eg. by frag_var. */
3091 dwarf2_emit_insn (0);
3092
3093 /* Output jumps. */
3094 if (i.tm.opcode_modifier & Jump)
3095 output_branch ();
3096 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3097 output_jump ();
3098 else if (i.tm.opcode_modifier & JumpInterSegment)
3099 output_interseg_jump ();
3100 else
3101 {
3102 /* Output normal instructions here. */
3103 char *p;
3104 unsigned char *q;
252b5132 3105
29b0f896
AM		 3106 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3107 byte for the SSE instructions to specify a prefix they require. */
3108 if (i.tm.base_opcode & 0xff0000)
3109 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3110
29b0f896
AM		 3111 /* The prefix bytes. */
3112 for (q = i.prefix;
3113 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3114 q++)
3115 {
3116 if (*q)
3117 {
3118 p = frag_more (1);
3119 md_number_to_chars (p, (valueT) *q, 1);
3120 }
3121 }
252b5132 3122
29b0f896
AM		 3123 /* Now the opcode; be careful about word order here! */
3124 if (fits_in_unsigned_byte (i.tm.base_opcode))
3125 {
3126 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3127 }
3128 else
3129 {
3130 p = frag_more (2);
3131 /* Put out high byte first: can't use md_number_to_chars! */
3132 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3133 *p = i.tm.base_opcode & 0xff;
3134 }
3e73aa7c 3135
29b0f896
AM		 3136 /* Now the modrm byte and sib byte (if present). */
3137 if (i.tm.opcode_modifier & Modrm)
3138 {
3139 p = frag_more (1);
3140 md_number_to_chars (p,
3141 (valueT) (i.rm.regmem << 0
3142 | i.rm.reg << 3
3143 | i.rm.mode << 6),
3144 1);
3145 /* If i.rm.regmem == ESP (4)
3146 && i.rm.mode != (Register mode)
3147 && not 16 bit
3148 ==> need second modrm byte. */
3149 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3150 && i.rm.mode != 3
3151 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3152 {
3153 p = frag_more (1);
3154 md_number_to_chars (p,
3155 (valueT) (i.sib.base << 0
3156 | i.sib.index << 3
3157 | i.sib.scale << 6),
3158 1);
3159 }
3160 }
3e73aa7c 3161
29b0f896
AM		 3162 if (i.disp_operands)
3163 output_disp ();
3e73aa7c 3164
29b0f896
AM		 3165 if (i.imm_operands)
3166 output_imm ();
3167 }
252b5132 3168
29b0f896
AM		 3169#ifdef DEBUG386
3170 if (flag_debug)
3171 {
3172 pi (line, &i);
3173 }
3174#endif /* DEBUG386 */
3175}
252b5132 3176
29b0f896
AM		 3177static void
3178output_disp ()
3179{
3180 char *p;
3181 unsigned int n;
252b5132 3182
29b0f896
AM		 3183 for (n = 0; n < i.operands; n++)
3184 {
3185 if (i.types[n] & Disp)
3186 {
3187 if (i.op[n].disps->X_op == O_constant)
3188 {
3189 int size;
3190 offsetT val;
252b5132 3191
29b0f896
AM		 3192 size = 4;
3193 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3194 {
3195 size = 2;
3196 if (i.types[n] & Disp8)
3197 size = 1;
3198 if (i.types[n] & Disp64)
3199 size = 8;
3200 }
3201 val = offset_in_range (i.op[n].disps->X_add_number,
3202 size);
3203 p = frag_more (size);
3204 md_number_to_chars (p, val, size);
3205 }
3206 else
3207 {
3208 int size = 4;
3209 int sign = 0;
3210 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3211
3212 /* The PC relative address is computed relative
3213 to the instruction boundary, so in case immediate
3214 fields follows, we need to adjust the value. */
3215 if (pcrel && i.imm_operands)
3216 {
3217 int imm_size = 4;
3218 unsigned int n1;
252b5132 3219
29b0f896
AM		 3220 for (n1 = 0; n1 < i.operands; n1++)
3221 if (i.types[n1] & Imm)
252b5132 3222 {
29b0f896 3223 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3224 {
29b0f896
AM		 3225 imm_size = 2;
3226 if (i.types[n1] & (Imm8 | Imm8S))
3227 imm_size = 1;
3228 if (i.types[n1] & Imm64)
3229 imm_size = 8;
252b5132 3230 }
29b0f896 3231 break;
252b5132 3232 }
29b0f896
AM		 3233 /* We should find the immediate. */
3234 if (n1 == i.operands)
3235 abort ();
3236 i.op[n].disps->X_add_number -= imm_size;
3237 }
520dc8e8 3238
29b0f896
AM		 3239 if (i.types[n] & Disp32S)
3240 sign = 1;
3e73aa7c 3241
29b0f896
AM		 3242 if (i.types[n] & (Disp16 | Disp64))
3243 {
3244 size = 2;
3245 if (i.types[n] & Disp64)
3246 size = 8;
3247 }
520dc8e8 3248
29b0f896 3249 p = frag_more (size);
062cd5e7
AS		 3250 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3251 i.op[n].disps, pcrel,
3252 reloc (size, pcrel, sign, i.reloc[n]));
29b0f896
AM		 3253 }
3254 }
3255 }
3256}
252b5132 3257
29b0f896
AM		 3258static void
3259output_imm ()
3260{
3261 char *p;
3262 unsigned int n;
252b5132 3263
29b0f896
AM		 3264 for (n = 0; n < i.operands; n++)
3265 {
3266 if (i.types[n] & Imm)
3267 {
3268 if (i.op[n].imms->X_op == O_constant)
3269 {
3270 int size;
3271 offsetT val;
b4cac588 3272
29b0f896
AM		 3273 size = 4;
3274 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3275 {
3276 size = 2;
3277 if (i.types[n] & (Imm8 | Imm8S))
3278 size = 1;
3279 else if (i.types[n] & Imm64)
3280 size = 8;
3281 }
3282 val = offset_in_range (i.op[n].imms->X_add_number,
3283 size);
3284 p = frag_more (size);
3285 md_number_to_chars (p, val, size);
3286 }
3287 else
3288 {
3289 /* Not absolute_section.
3290 Need a 32-bit fixup (don't support 8bit
3291 non-absolute imms). Try to support other
3292 sizes ... */
3293 RELOC_ENUM reloc_type;
3294 int size = 4;
3295 int sign = 0;
3296
3297 if ((i.types[n] & (Imm32S))
3298 && i.suffix == QWORD_MNEM_SUFFIX)
3299 sign = 1;
3300 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3301 {
3302 size = 2;
3303 if (i.types[n] & (Imm8 | Imm8S))
3304 size = 1;
3305 if (i.types[n] & Imm64)
3306 size = 8;
3307 }
520dc8e8 3308
29b0f896
AM		 3309 p = frag_more (size);
3310 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3311#ifdef BFD_ASSEMBLER
29b0f896
AM		 3312 if (reloc_type == BFD_RELOC_32
3313 && GOT_symbol
3314 && GOT_symbol == i.op[n].imms->X_add_symbol
3315 && (i.op[n].imms->X_op == O_symbol
3316 || (i.op[n].imms->X_op == O_add
3317 && ((symbol_get_value_expression
3318 (i.op[n].imms->X_op_symbol)->X_op)
3319 == O_subtract))))
3320 {
3321 /* We don't support dynamic linking on x86-64 yet. */
3322 if (flag_code == CODE_64BIT)
3323 abort ();
3324 reloc_type = BFD_RELOC_386_GOTPC;
3325 i.op[n].imms->X_add_number += 3;
3326 }
252b5132 3327#endif
29b0f896
AM		 3328 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3329 i.op[n].imms, 0, reloc_type);
3330 }
3331 }
3332 }
252b5132
RH		 3333}
3334\f
f3c180ae
AM		 3335#ifndef LEX_AT
3336static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3337
3338/* Parse operands of the form
3339 <symbol>@GOTOFF+<nnn>
3340 and similar .plt or .got references.
3341
3342 If we find one, set up the correct relocation in RELOC and copy the
3343 input string, minus the `@GOTOFF' into a malloc'd buffer for
3344 parsing by the calling routine. Return this buffer, and if ADJUST
3345 is non-null set it to the length of the string we removed from the
3346 input line. Otherwise return NULL. */
3347static char *
3348lex_got (reloc, adjust)
3349 RELOC_ENUM *reloc;
3350 int *adjust;
3351{
3352 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3353 static const struct {
3354 const char *str;
3355 const RELOC_ENUM rel[NUM_FLAG_CODE];
3356 } gotrel[] = {
13ae64f3
JJ		 3357 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3358 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3359 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3360 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } },
3361 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3362 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } },
3363 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } },
3364 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3365 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } },
3366 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3367 };
3368 char *cp;
3369 unsigned int j;
3370
3371 for (cp = input_line_pointer; *cp != '@'; cp++)
3372 if (is_end_of_line[(unsigned char) *cp])
3373 return NULL;
3374
3375 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3376 {
3377 int len;
3378
3379 len = strlen (gotrel[j].str);
28f81592 3380 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3381 {
3382 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3383 {
28f81592
AM		 3384 int first, second;
3385 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3386
3387 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3388 if (adjust)
3389 *adjust = len;
f3c180ae
AM		 3390
3391 if (GOT_symbol == NULL)
3392 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3393
3394 /* Replace the relocation token with ' ', so that
3395 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3396
3397 /* The length of the first part of our input line. */
f3c180ae 3398 first = cp - input_line_pointer;
28f81592
AM		 3399
3400 /* The second part goes from after the reloc token until
3401 (and including) an end_of_line char. Don't use strlen
3402 here as the end_of_line char may not be a NUL. */
3403 past_reloc = cp + 1 + len;
3404 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3405 ;
3406 second = cp - past_reloc;
3407
3408 /* Allocate and copy string. The trailing NUL shouldn't
3409 be necessary, but be safe. */
3410 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3411 memcpy (tmpbuf, input_line_pointer, first);
3412 tmpbuf[first] = ' ';
28f81592
AM		 3413 memcpy (tmpbuf + first + 1, past_reloc, second);
3414 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3415 return tmpbuf;
3416 }
3417
3418 as_bad (_("@%s reloc is not supported in %s bit mode"),
3419 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3420 return NULL;
3421 }
3422 }
3423
3424 /* Might be a symbol version string. Don't as_bad here. */
3425 return NULL;
3426}
3427
3428/* x86_cons_fix_new is called via the expression parsing code when a
3429 reloc is needed. We use this hook to get the correct .got reloc. */
3430static RELOC_ENUM got_reloc = NO_RELOC;
3431
3432void
3433x86_cons_fix_new (frag, off, len, exp)
3434 fragS *frag;
3435 unsigned int off;
3436 unsigned int len;
3437 expressionS *exp;
3438{
3439 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3440 got_reloc = NO_RELOC;
3441 fix_new_exp (frag, off, len, exp, 0, r);
3442}
3443
3444void
3445x86_cons (exp, size)
3446 expressionS *exp;
3447 int size;
3448{
3449 if (size == 4)
3450 {
3451 /* Handle @GOTOFF and the like in an expression. */
3452 char *save;
3453 char *gotfree_input_line;
3454 int adjust;
3455
3456 save = input_line_pointer;
3457 gotfree_input_line = lex_got (&got_reloc, &adjust);
3458 if (gotfree_input_line)
3459 input_line_pointer = gotfree_input_line;
3460
3461 expression (exp);
3462
3463 if (gotfree_input_line)
3464 {
3465 /* expression () has merrily parsed up to the end of line,
3466 or a comma - in the wrong buffer. Transfer how far
3467 input_line_pointer has moved to the right buffer. */
3468 input_line_pointer = (save
3469 + (input_line_pointer - gotfree_input_line)
3470 + adjust);
3471 free (gotfree_input_line);
3472 }
3473 }
3474 else
3475 expression (exp);
3476}
3477#endif
3478
252b5132
RH		 3479static int i386_immediate PARAMS ((char *));
3480
3481static int
3482i386_immediate (imm_start)
3483 char *imm_start;
3484{
3485 char *save_input_line_pointer;
f3c180ae
AM		 3486#ifndef LEX_AT
3487 char *gotfree_input_line;
3488#endif
252b5132 3489 segT exp_seg = 0;
47926f60 3490 expressionS *exp;
252b5132
RH		 3491
3492 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3493 {
d0b47220 3494 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3495 return 0;
3496 }
3497
3498 exp = &im_expressions[i.imm_operands++];
520dc8e8 3499 i.op[this_operand].imms = exp;
252b5132
RH		 3500
3501 if (is_space_char (*imm_start))
3502 ++imm_start;
3503
3504 save_input_line_pointer = input_line_pointer;
3505 input_line_pointer = imm_start;
3506
3507#ifndef LEX_AT
f3c180ae
AM		 3508 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3509 if (gotfree_input_line)
3510 input_line_pointer = gotfree_input_line;
252b5132
RH		 3511#endif
3512
3513 exp_seg = expression (exp);
3514
83183c0c 3515 SKIP_WHITESPACE ();
252b5132 3516 if (*input_line_pointer)
f3c180ae 3517 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3518
3519 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3520#ifndef LEX_AT
3521 if (gotfree_input_line)
3522 free (gotfree_input_line);
3523#endif
252b5132 3524
2daf4fd8 3525 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3526 {
47926f60 3527 /* Missing or bad expr becomes absolute 0. */
d0b47220 3528 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3529 imm_start);
252b5132
RH		 3530 exp->X_op = O_constant;
3531 exp->X_add_number = 0;
3532 exp->X_add_symbol = (symbolS *) 0;
3533 exp->X_op_symbol = (symbolS *) 0;
252b5132 3534 }
3e73aa7c 3535 else if (exp->X_op == O_constant)
252b5132 3536 {
47926f60 3537 /* Size it properly later. */
3e73aa7c
JH		 3538 i.types[this_operand] |= Imm64;
3539 /* If BFD64, sign extend val. */
3540 if (!use_rela_relocations)
3541 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3542 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3543 }
4c63da97 3544#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3545 else if (1
4c63da97 3546#ifdef BFD_ASSEMBLER
47926f60 3547 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3548#endif
47926f60 3549 && exp_seg != text_section
24eab124
AM		 3550 && exp_seg != data_section
3551 && exp_seg != bss_section
3552 && exp_seg != undefined_section
252b5132 3553#ifdef BFD_ASSEMBLER
24eab124 3554 && !bfd_is_com_section (exp_seg)
252b5132 3555#endif
24eab124 3556 )
252b5132 3557 {
4c63da97 3558#ifdef BFD_ASSEMBLER
d0b47220 3559 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3560#else
d0b47220 3561 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3562#endif
252b5132
RH		 3563 return 0;
3564 }
3565#endif
3566 else
3567 {
3568 /* This is an address. The size of the address will be
24eab124 3569 determined later, depending on destination register,
3e73aa7c
JH		 3570 suffix, or the default for the section. */
3571 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3572 }
3573
3574 return 1;
3575}
3576
551c1ca1 3577static char *i386_scale PARAMS ((char *));
252b5132 3578
551c1ca1 3579static char *
252b5132
RH		 3580i386_scale (scale)
3581 char *scale;
3582{
551c1ca1
AM		 3583 offsetT val;
3584 char *save = input_line_pointer;
252b5132 3585
551c1ca1
AM		 3586 input_line_pointer = scale;
3587 val = get_absolute_expression ();
3588
3589 switch (val)
252b5132 3590 {
551c1ca1
AM		 3591 case 0:
3592 case 1:
252b5132
RH		 3593 i.log2_scale_factor = 0;
3594 break;
551c1ca1 3595 case 2:
252b5132
RH		 3596 i.log2_scale_factor = 1;
3597 break;
551c1ca1 3598 case 4:
252b5132
RH		 3599 i.log2_scale_factor = 2;
3600 break;
551c1ca1 3601 case 8:
252b5132
RH		 3602 i.log2_scale_factor = 3;
3603 break;
3604 default:
252b5132 3605 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3606 scale);
551c1ca1
AM		 3607 input_line_pointer = save;
3608 return NULL;
252b5132 3609 }
29b0f896 3610 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3611 {
3612 as_warn (_("scale factor of %d without an index register"),
24eab124 3613 1 << i.log2_scale_factor);
252b5132
RH		 3614#if SCALE1_WHEN_NO_INDEX
3615 i.log2_scale_factor = 0;
3616#endif
3617 }
551c1ca1
AM		 3618 scale = input_line_pointer;
3619 input_line_pointer = save;
3620 return scale;
252b5132
RH		 3621}
3622
3623static int i386_displacement PARAMS ((char *, char *));
3624
3625static int
3626i386_displacement (disp_start, disp_end)
3627 char *disp_start;
3628 char *disp_end;
3629{
29b0f896 3630 expressionS *exp;
252b5132
RH		 3631 segT exp_seg = 0;
3632 char *save_input_line_pointer;
f3c180ae
AM		 3633#ifndef LEX_AT
3634 char *gotfree_input_line;
3635#endif
252b5132
RH		 3636 int bigdisp = Disp32;
3637
3e73aa7c 3638 if (flag_code == CODE_64BIT)
7ecd2f8b 3639 {
29b0f896
AM		 3640 if (i.prefix[ADDR_PREFIX] == 0)
3641 bigdisp = Disp64;
7ecd2f8b
JH		 3642 }
3643 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3644 bigdisp = Disp16;
252b5132
RH		 3645 i.types[this_operand] |= bigdisp;
3646
3647 exp = &disp_expressions[i.disp_operands];
520dc8e8 3648 i.op[this_operand].disps = exp;
252b5132
RH		 3649 i.disp_operands++;
3650 save_input_line_pointer = input_line_pointer;
3651 input_line_pointer = disp_start;
3652 END_STRING_AND_SAVE (disp_end);
3653
3654#ifndef GCC_ASM_O_HACK
3655#define GCC_ASM_O_HACK 0
3656#endif
3657#if GCC_ASM_O_HACK
3658 END_STRING_AND_SAVE (disp_end + 1);
3659 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3660 && displacement_string_end[-1] == '+')
252b5132
RH		 3661 {
3662 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3663 constraint within gcc asm statements.
3664 For instance:
3665
3666 #define _set_tssldt_desc(n,addr,limit,type) \
3667 __asm__ __volatile__ ( \
3668 "movw %w2,%0\n\t" \
3669 "movw %w1,2+%0\n\t" \
3670 "rorl $16,%1\n\t" \
3671 "movb %b1,4+%0\n\t" \
3672 "movb %4,5+%0\n\t" \
3673 "movb $0,6+%0\n\t" \
3674 "movb %h1,7+%0\n\t" \
3675 "rorl $16,%1" \
3676 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3677
3678 This works great except that the output assembler ends
3679 up looking a bit weird if it turns out that there is
3680 no offset. You end up producing code that looks like:
3681
3682 #APP
3683 movw $235,(%eax)
3684 movw %dx,2+(%eax)
3685 rorl $16,%edx
3686 movb %dl,4+(%eax)
3687 movb $137,5+(%eax)
3688 movb $0,6+(%eax)
3689 movb %dh,7+(%eax)
3690 rorl $16,%edx
3691 #NO_APP
3692
47926f60 3693 So here we provide the missing zero. */
24eab124
AM		 3694
3695 *displacement_string_end = '0';
252b5132
RH		 3696 }
3697#endif
3698#ifndef LEX_AT
f3c180ae
AM		 3699 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3700 if (gotfree_input_line)
3701 input_line_pointer = gotfree_input_line;
252b5132
RH		 3702#endif
3703
24eab124 3704 exp_seg = expression (exp);
252b5132 3705
636c26b0
AM		 3706 SKIP_WHITESPACE ();
3707 if (*input_line_pointer)
3708 as_bad (_("junk `%s' after expression"), input_line_pointer);
3709#if GCC_ASM_O_HACK
3710 RESTORE_END_STRING (disp_end + 1);
3711#endif
3712 RESTORE_END_STRING (disp_end);
3713 input_line_pointer = save_input_line_pointer;
3714#ifndef LEX_AT
3715 if (gotfree_input_line)
3716 free (gotfree_input_line);
3717#endif
3718
252b5132 3719#ifdef BFD_ASSEMBLER
24eab124
AM		 3720 /* We do this to make sure that the section symbol is in
3721 the symbol table. We will ultimately change the relocation
47926f60 3722 to be relative to the beginning of the section. */
1ae12ab7
AM		 3723 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3724 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3725 {
636c26b0
AM		 3726 if (exp->X_op != O_symbol)
3727 {
3728 as_bad (_("bad expression used with @%s"),
3729 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3730 ? "GOTPCREL"
3731 : "GOTOFF"));
3732 return 0;
3733 }
3734
e5cb08ac 3735 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3736 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3737 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3738 exp->X_op = O_subtract;
3739 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3740 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3741 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3742 else
29b0f896 3743 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3744 }
252b5132
RH		 3745#endif
3746
2daf4fd8
AM		 3747 if (exp->X_op == O_absent || exp->X_op == O_big)
3748 {
47926f60 3749 /* Missing or bad expr becomes absolute 0. */
d0b47220 3750 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3751 disp_start);
3752 exp->X_op = O_constant;
3753 exp->X_add_number = 0;
3754 exp->X_add_symbol = (symbolS *) 0;
3755 exp->X_op_symbol = (symbolS *) 0;
3756 }
3757
4c63da97 3758#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3759 if (exp->X_op != O_constant
4c63da97 3760#ifdef BFD_ASSEMBLER
45288df1 3761 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3762#endif
45288df1
AM		 3763 && exp_seg != text_section
3764 && exp_seg != data_section
3765 && exp_seg != bss_section
3766 && exp_seg != undefined_section)
24eab124 3767 {
4c63da97 3768#ifdef BFD_ASSEMBLER
d0b47220 3769 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3770#else
d0b47220 3771 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3772#endif
24eab124
AM		 3773 return 0;
3774 }
252b5132 3775#endif
3e73aa7c
JH		 3776 else if (flag_code == CODE_64BIT)
3777 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3778 return 1;
3779}
3780
e5cb08ac 3781static int i386_index_check PARAMS ((const char *));
252b5132 3782
eecb386c 3783/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3784 Return 1 on success, 0 on a failure. */
3785
252b5132 3786static int
eecb386c
AM		 3787i386_index_check (operand_string)
3788 const char *operand_string;
252b5132 3789{
3e73aa7c 3790 int ok;
24eab124 3791#if INFER_ADDR_PREFIX
eecb386c
AM		 3792 int fudged = 0;
3793
24eab124
AM		 3794 tryprefix:
3795#endif
3e73aa7c
JH		 3796 ok = 1;
3797 if (flag_code == CODE_64BIT)
3798 {
7ecd2f8b
JH		 3799 if (i.prefix[ADDR_PREFIX] == 0)
3800 {
3801 /* 64bit checks. */
3802 if ((i.base_reg
3803 && ((i.base_reg->reg_type & Reg64) == 0)
3804 && (i.base_reg->reg_type != BaseIndex
3805 || i.index_reg))
3806 || (i.index_reg
29b0f896
AM		 3807 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3808 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3809 ok = 0;
3810 }
3811 else
3812 {
3813 /* 32bit checks. */
3814 if ((i.base_reg
3815 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3816 || (i.index_reg
29b0f896
AM		 3817 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3818 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3819 ok = 0;
3820 }
3e73aa7c
JH		 3821 }
3822 else
3823 {
3824 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3825 {
3826 /* 16bit checks. */
3827 if ((i.base_reg
29b0f896
AM		 3828 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3829 != (Reg16 | BaseIndex)))
3e73aa7c 3830 || (i.index_reg
29b0f896
AM		 3831 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3832 != (Reg16 | BaseIndex))
3833 || !(i.base_reg
3834 && i.base_reg->reg_num < 6
3835 && i.index_reg->reg_num >= 6
3836 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3837 ok = 0;
3838 }
3839 else
e5cb08ac 3840 {
3e73aa7c
JH		 3841 /* 32bit checks. */
3842 if ((i.base_reg
3843 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3844 || (i.index_reg
29b0f896
AM		 3845 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3846 != (Reg32 | BaseIndex))))
e5cb08ac 3847 ok = 0;
3e73aa7c
JH		 3848 }
3849 }
3850 if (!ok)
24eab124
AM		 3851 {
3852#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3853 if (flag_code != CODE_64BIT
3854 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3855 {
3856 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3857 i.prefixes += 1;
b23bac36
AM		 3858 /* Change the size of any displacement too. At most one of
3859 Disp16 or Disp32 is set.
3860 FIXME. There doesn't seem to be any real need for separate
3861 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3862 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 3863 if (i.types[this_operand] & (Disp16 | Disp32))
3864 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 3865 fudged = 1;
24eab124
AM		 3866 goto tryprefix;
3867 }
eecb386c
AM		 3868 if (fudged)
3869 as_bad (_("`%s' is not a valid base/index expression"),
3870 operand_string);
3871 else
c388dee8 3872#endif
eecb386c
AM		 3873 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3874 operand_string,
3e73aa7c 3875 flag_code_names[flag_code]);
eecb386c 3876 return 0;
24eab124
AM		 3877 }
3878 return 1;
3879}
252b5132 3880
252b5132 3881/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 3882 on error. */
252b5132 3883
252b5132
RH		 3884static int
3885i386_operand (operand_string)
3886 char *operand_string;
3887{
af6bdddf
AM		 3888 const reg_entry *r;
3889 char *end_op;
24eab124 3890 char *op_string = operand_string;
252b5132 3891
24eab124 3892 if (is_space_char (*op_string))
252b5132
RH		 3893 ++op_string;
3894
24eab124 3895 /* We check for an absolute prefix (differentiating,
47926f60 3896 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 3897 if (*op_string == ABSOLUTE_PREFIX)
3898 {
3899 ++op_string;
3900 if (is_space_char (*op_string))
3901 ++op_string;
3902 i.types[this_operand] |= JumpAbsolute;
3903 }
252b5132 3904
47926f60 3905 /* Check if operand is a register. */
af6bdddf
AM		 3906 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3907 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 3908 {
24eab124
AM		 3909 /* Check for a segment override by searching for ':' after a
3910 segment register. */
3911 op_string = end_op;
3912 if (is_space_char (*op_string))
3913 ++op_string;
3914 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3915 {
3916 switch (r->reg_num)
3917 {
3918 case 0:
3919 i.seg[i.mem_operands] = &es;
3920 break;
3921 case 1:
3922 i.seg[i.mem_operands] = &cs;
3923 break;
3924 case 2:
3925 i.seg[i.mem_operands] = &ss;
3926 break;
3927 case 3:
3928 i.seg[i.mem_operands] = &ds;
3929 break;
3930 case 4:
3931 i.seg[i.mem_operands] = &fs;
3932 break;
3933 case 5:
3934 i.seg[i.mem_operands] = &gs;
3935 break;
3936 }
252b5132 3937
24eab124 3938 /* Skip the ':' and whitespace. */
252b5132
RH		 3939 ++op_string;
3940 if (is_space_char (*op_string))
24eab124 3941 ++op_string;
252b5132 3942
24eab124
AM		 3943 if (!is_digit_char (*op_string)
3944 && !is_identifier_char (*op_string)
3945 && *op_string != '('
3946 && *op_string != ABSOLUTE_PREFIX)
3947 {
3948 as_bad (_("bad memory operand `%s'"), op_string);
3949 return 0;
3950 }
47926f60 3951 /* Handle case of %es:*foo. */
24eab124
AM		 3952 if (*op_string == ABSOLUTE_PREFIX)
3953 {
3954 ++op_string;
3955 if (is_space_char (*op_string))
3956 ++op_string;
3957 i.types[this_operand] |= JumpAbsolute;
3958 }
3959 goto do_memory_reference;
3960 }
3961 if (*op_string)
3962 {
d0b47220 3963 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 3964 return 0;
3965 }
3966 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 3967 i.op[this_operand].regs = r;
24eab124
AM		 3968 i.reg_operands++;
3969 }
af6bdddf
AM		 3970 else if (*op_string == REGISTER_PREFIX)
3971 {
3972 as_bad (_("bad register name `%s'"), op_string);
3973 return 0;
3974 }
24eab124 3975 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 3976 {
24eab124
AM		 3977 ++op_string;
3978 if (i.types[this_operand] & JumpAbsolute)
3979 {
d0b47220 3980 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 3981 return 0;
3982 }
3983 if (!i386_immediate (op_string))
3984 return 0;
3985 }
3986 else if (is_digit_char (*op_string)
3987 || is_identifier_char (*op_string)
e5cb08ac 3988 || *op_string == '(')
24eab124 3989 {
47926f60 3990 /* This is a memory reference of some sort. */
af6bdddf 3991 char *base_string;
252b5132 3992
47926f60 3993 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 3994 char *displacement_string_start;
3995 char *displacement_string_end;
252b5132 3996
24eab124 3997 do_memory_reference:
24eab124
AM		 3998 if ((i.mem_operands == 1
3999 && (current_templates->start->opcode_modifier & IsString) == 0)
4000 || i.mem_operands == 2)
4001 {
4002 as_bad (_("too many memory references for `%s'"),
4003 current_templates->start->name);
4004 return 0;
4005 }
252b5132 4006
24eab124
AM		 4007 /* Check for base index form. We detect the base index form by
4008 looking for an ')' at the end of the operand, searching
4009 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4010 after the '('. */
af6bdddf 4011 base_string = op_string + strlen (op_string);
c3332e24 4012
af6bdddf
AM		 4013 --base_string;
4014 if (is_space_char (*base_string))
4015 --base_string;
252b5132 4016
47926f60 4017 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4018 displacement_string_start = op_string;
4019 displacement_string_end = base_string + 1;
252b5132 4020
24eab124
AM		 4021 if (*base_string == ')')
4022 {
af6bdddf 4023 char *temp_string;
24eab124
AM		 4024 unsigned int parens_balanced = 1;
4025 /* We've already checked that the number of left & right ()'s are
47926f60 4026 equal, so this loop will not be infinite. */
24eab124
AM		 4027 do
4028 {
4029 base_string--;
4030 if (*base_string == ')')
4031 parens_balanced++;
4032 if (*base_string == '(')
4033 parens_balanced--;
4034 }
4035 while (parens_balanced);
c3332e24 4036
af6bdddf 4037 temp_string = base_string;
c3332e24 4038
24eab124 4039 /* Skip past '(' and whitespace. */
252b5132
RH		 4040 ++base_string;
4041 if (is_space_char (*base_string))
24eab124 4042 ++base_string;
252b5132 4043
af6bdddf
AM		 4044 if (*base_string == ','
4045 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4046 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4047 {
af6bdddf 4048 displacement_string_end = temp_string;
252b5132 4049
af6bdddf 4050 i.types[this_operand] |= BaseIndex;
252b5132 4051
af6bdddf 4052 if (i.base_reg)
24eab124 4053 {
24eab124
AM		 4054 base_string = end_op;
4055 if (is_space_char (*base_string))
4056 ++base_string;
af6bdddf
AM		 4057 }
4058
4059 /* There may be an index reg or scale factor here. */
4060 if (*base_string == ',')
4061 {
4062 ++base_string;
4063 if (is_space_char (*base_string))
4064 ++base_string;
4065
4066 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4067 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4068 {
af6bdddf 4069 base_string = end_op;
24eab124
AM		 4070 if (is_space_char (*base_string))
4071 ++base_string;
af6bdddf
AM		 4072 if (*base_string == ',')
4073 {
4074 ++base_string;
4075 if (is_space_char (*base_string))
4076 ++base_string;
4077 }
e5cb08ac 4078 else if (*base_string != ')')
af6bdddf
AM		 4079 {
4080 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4081 operand_string);
4082 return 0;
4083 }
24eab124 4084 }
af6bdddf 4085 else if (*base_string == REGISTER_PREFIX)
24eab124 4086 {
af6bdddf 4087 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4088 return 0;
4089 }
252b5132 4090
47926f60 4091 /* Check for scale factor. */
551c1ca1 4092 if (*base_string != ')')
af6bdddf 4093 {
551c1ca1
AM		 4094 char *end_scale = i386_scale (base_string);
4095
4096 if (!end_scale)
af6bdddf 4097 return 0;
24eab124 4098
551c1ca1 4099 base_string = end_scale;
af6bdddf
AM		 4100 if (is_space_char (*base_string))
4101 ++base_string;
4102 if (*base_string != ')')
4103 {
4104 as_bad (_("expecting `)' after scale factor in `%s'"),
4105 operand_string);
4106 return 0;
4107 }
4108 }
4109 else if (!i.index_reg)
24eab124 4110 {
af6bdddf
AM		 4111 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4112 *base_string);
24eab124
AM		 4113 return 0;
4114 }
4115 }
af6bdddf 4116 else if (*base_string != ')')
24eab124 4117 {
af6bdddf
AM		 4118 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4119 operand_string);
24eab124
AM		 4120 return 0;
4121 }
c3332e24 4122 }
af6bdddf 4123 else if (*base_string == REGISTER_PREFIX)
c3332e24 4124 {
af6bdddf 4125 as_bad (_("bad register name `%s'"), base_string);
24eab124 4126 return 0;
c3332e24 4127 }
24eab124
AM		 4128 }
4129
4130 /* If there's an expression beginning the operand, parse it,
4131 assuming displacement_string_start and
4132 displacement_string_end are meaningful. */
4133 if (displacement_string_start != displacement_string_end)
4134 {
4135 if (!i386_displacement (displacement_string_start,
4136 displacement_string_end))
4137 return 0;
4138 }
4139
4140 /* Special case for (%dx) while doing input/output op. */
4141 if (i.base_reg
4142 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4143 && i.index_reg == 0
4144 && i.log2_scale_factor == 0
4145 && i.seg[i.mem_operands] == 0
4146 && (i.types[this_operand] & Disp) == 0)
4147 {
4148 i.types[this_operand] = InOutPortReg;
4149 return 1;
4150 }
4151
eecb386c
AM		 4152 if (i386_index_check (operand_string) == 0)
4153 return 0;
24eab124
AM		 4154 i.mem_operands++;
4155 }
4156 else
ce8a8b2f
AM		 4157 {
4158 /* It's not a memory operand; argh! */
24eab124
AM		 4159 as_bad (_("invalid char %s beginning operand %d `%s'"),
4160 output_invalid (*op_string),
4161 this_operand + 1,
4162 op_string);
4163 return 0;
4164 }
47926f60 4165 return 1; /* Normal return. */
252b5132
RH		 4166}
4167\f
ee7fcc42
AM		 4168/* md_estimate_size_before_relax()
4169
4170 Called just before relax() for rs_machine_dependent frags. The x86
4171 assembler uses these frags to handle variable size jump
4172 instructions.
4173
4174 Any symbol that is now undefined will not become defined.
4175 Return the correct fr_subtype in the frag.
4176 Return the initial "guess for variable size of frag" to caller.
4177 The guess is actually the growth beyond the fixed part. Whatever
4178 we do to grow the fixed or variable part contributes to our
4179 returned value. */
4180
252b5132
RH		 4181int
4182md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4183 fragS *fragP;
4184 segT segment;
252b5132 4185{
252b5132 4186 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4187 check for un-relaxable symbols. On an ELF system, we can't relax
4188 an externally visible symbol, because it may be overridden by a
4189 shared library. */
4190 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4191#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b98ef147
AM		 4192 || S_IS_EXTERNAL (fragP->fr_symbol)
4193 || S_IS_WEAK (fragP->fr_symbol)
4194#endif
4195 )
252b5132 4196 {
b98ef147
AM		 4197 /* Symbol is undefined in this segment, or we need to keep a
4198 reloc so that weak symbols can be overridden. */
4199 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4200 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4201 unsigned char *opcode;
4202 int old_fr_fix;
f6af82bd 4203
ee7fcc42
AM		 4204 if (fragP->fr_var != NO_RELOC)
4205 reloc_type = fragP->fr_var;
b98ef147 4206 else if (size == 2)
f6af82bd
AM		 4207 reloc_type = BFD_RELOC_16_PCREL;
4208 else
4209 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4210
ee7fcc42
AM		 4211 old_fr_fix = fragP->fr_fix;
4212 opcode = (unsigned char *) fragP->fr_opcode;
4213
fddf5b5b 4214 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4215 {
fddf5b5b
AM		 4216 case UNCOND_JUMP:
4217 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4218 opcode[0] = 0xe9;
252b5132 4219 fragP->fr_fix += size;
062cd5e7
AS		 4220 fix_new (fragP, old_fr_fix, size,
4221 fragP->fr_symbol,
4222 fragP->fr_offset, 1,
4223 reloc_type);
252b5132
RH		 4224 break;
4225
fddf5b5b 4226 case COND_JUMP86:
412167cb
AM		 4227 if (size == 2
4228 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4229 {
4230 /* Negate the condition, and branch past an
4231 unconditional jump. */
4232 opcode[0] ^= 1;
4233 opcode[1] = 3;
4234 /* Insert an unconditional jump. */
4235 opcode[2] = 0xe9;
4236 /* We added two extra opcode bytes, and have a two byte
4237 offset. */
4238 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4239 fix_new (fragP, old_fr_fix + 2, 2,
4240 fragP->fr_symbol,
4241 fragP->fr_offset, 1,
4242 reloc_type);
fddf5b5b
AM		 4243 break;
4244 }
4245 /* Fall through. */
4246
4247 case COND_JUMP:
412167cb
AM		 4248 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4249 {
4250 fragP->fr_fix += 1;
4251 fix_new (fragP, old_fr_fix, 1,
4252 fragP->fr_symbol,
4253 fragP->fr_offset, 1,
4254 BFD_RELOC_8_PCREL);
4255 break;
4256 }
93c2a809 4257
24eab124 4258 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4259 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4260 opcode[1] = opcode[0] + 0x10;
f6af82bd 4261 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4262 /* We've added an opcode byte. */
4263 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4264 fix_new (fragP, old_fr_fix + 1, size,
4265 fragP->fr_symbol,
4266 fragP->fr_offset, 1,
4267 reloc_type);
252b5132 4268 break;
fddf5b5b
AM		 4269
4270 default:
4271 BAD_CASE (fragP->fr_subtype);
4272 break;
252b5132
RH		 4273 }
4274 frag_wane (fragP);
ee7fcc42 4275 return fragP->fr_fix - old_fr_fix;
252b5132 4276 }
93c2a809 4277
93c2a809
AM		 4278 /* Guess size depending on current relax state. Initially the relax
4279 state will correspond to a short jump and we return 1, because
4280 the variable part of the frag (the branch offset) is one byte
4281 long. However, we can relax a section more than once and in that
4282 case we must either set fr_subtype back to the unrelaxed state,
4283 or return the value for the appropriate branch. */
4284 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4285}
4286
47926f60
KH		 4287/* Called after relax() is finished.
4288
4289 In: Address of frag.
4290 fr_type == rs_machine_dependent.
4291 fr_subtype is what the address relaxed to.
4292
4293 Out: Any fixSs and constants are set up.
4294 Caller will turn frag into a ".space 0". */
4295
252b5132
RH		 4296#ifndef BFD_ASSEMBLER
4297void
4298md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4299 object_headers *headers ATTRIBUTE_UNUSED;
4300 segT sec ATTRIBUTE_UNUSED;
29b0f896 4301 fragS *fragP;
252b5132
RH		 4302#else
4303void
4304md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4305 bfd *abfd ATTRIBUTE_UNUSED;
4306 segT sec ATTRIBUTE_UNUSED;
29b0f896 4307 fragS *fragP;
252b5132
RH		 4308#endif
4309{
29b0f896 4310 unsigned char *opcode;
252b5132 4311 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4312 offsetT target_address;
4313 offsetT opcode_address;
252b5132 4314 unsigned int extension = 0;
847f7ad4 4315 offsetT displacement_from_opcode_start;
252b5132
RH		 4316
4317 opcode = (unsigned char *) fragP->fr_opcode;
4318
47926f60 4319 /* Address we want to reach in file space. */
252b5132 4320 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4321
47926f60 4322 /* Address opcode resides at in file space. */
252b5132
RH		 4323 opcode_address = fragP->fr_address + fragP->fr_fix;
4324
47926f60 4325 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4326 displacement_from_opcode_start = target_address - opcode_address;
4327
fddf5b5b 4328 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4329 {
47926f60
KH		 4330 /* Don't have to change opcode. */
4331 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4332 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4333 }
4334 else
4335 {
4336 if (no_cond_jump_promotion
4337 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4338 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4339
fddf5b5b
AM		 4340 switch (fragP->fr_subtype)
4341 {
4342 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4343 extension = 4; /* 1 opcode + 4 displacement */
4344 opcode[0] = 0xe9;
4345 where_to_put_displacement = &opcode[1];
4346 break;
252b5132 4347
fddf5b5b
AM		 4348 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4349 extension = 2; /* 1 opcode + 2 displacement */
4350 opcode[0] = 0xe9;
4351 where_to_put_displacement = &opcode[1];
4352 break;
252b5132 4353
fddf5b5b
AM		 4354 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4355 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4356 extension = 5; /* 2 opcode + 4 displacement */
4357 opcode[1] = opcode[0] + 0x10;
4358 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4359 where_to_put_displacement = &opcode[2];
4360 break;
252b5132 4361
fddf5b5b
AM		 4362 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4363 extension = 3; /* 2 opcode + 2 displacement */
4364 opcode[1] = opcode[0] + 0x10;
4365 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4366 where_to_put_displacement = &opcode[2];
4367 break;
252b5132 4368
fddf5b5b
AM		 4369 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4370 extension = 4;
4371 opcode[0] ^= 1;
4372 opcode[1] = 3;
4373 opcode[2] = 0xe9;
4374 where_to_put_displacement = &opcode[3];
4375 break;
4376
4377 default:
4378 BAD_CASE (fragP->fr_subtype);
4379 break;
4380 }
252b5132 4381 }
fddf5b5b 4382
47926f60 4383 /* Now put displacement after opcode. */
252b5132
RH		 4384 md_number_to_chars ((char *) where_to_put_displacement,
4385 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4386 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4387 fragP->fr_fix += extension;
4388}
4389\f
47926f60
KH		 4390/* Size of byte displacement jmp. */
4391int md_short_jump_size = 2;
4392
4393/* Size of dword displacement jmp. */
4394int md_long_jump_size = 5;
252b5132 4395
47926f60
KH		 4396/* Size of relocation record. */
4397const int md_reloc_size = 8;
252b5132
RH		 4398
4399void
4400md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4401 char *ptr;
4402 addressT from_addr, to_addr;
ab9da554
ILT		 4403 fragS *frag ATTRIBUTE_UNUSED;
4404 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4405{
847f7ad4 4406 offsetT offset;
252b5132
RH		 4407
4408 offset = to_addr - (from_addr + 2);
47926f60
KH		 4409 /* Opcode for byte-disp jump. */
4410 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4411 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4412}
4413
4414void
4415md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4416 char *ptr;
4417 addressT from_addr, to_addr;
a38cf1db
AM		 4418 fragS *frag ATTRIBUTE_UNUSED;
4419 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4420{
847f7ad4 4421 offsetT offset;
252b5132 4422
a38cf1db
AM		 4423 offset = to_addr - (from_addr + 5);
4424 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4425 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4426}
4427\f
4428/* Apply a fixup (fixS) to segment data, once it has been determined
4429 by our caller that we have all the info we need to fix it up.
4430
4431 On the 386, immediates, displacements, and data pointers are all in
4432 the same (little-endian) format, so we don't need to care about which
4433 we are handling. */
4434
94f592af
NC		 4435void
4436md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4437 /* The fix we're to put in. */
4438 fixS *fixP;
47926f60 4439 /* Pointer to the value of the bits. */
c6682705 4440 valueT *valP;
47926f60
KH		 4441 /* Segment fix is from. */
4442 segT seg ATTRIBUTE_UNUSED;
252b5132 4443{
94f592af 4444 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4445 valueT value = *valP;
252b5132 4446
e1b283bb 4447#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4448 if (fixP->fx_pcrel)
4449 {
4450 switch (fixP->fx_r_type)
4451 {
5865bb77
ILT		 4452 default:
4453 break;
4454
93382f6d
AM		 4455 case BFD_RELOC_32:
4456 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4457 break;
4458 case BFD_RELOC_16:
4459 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4460 break;
4461 case BFD_RELOC_8:
4462 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4463 break;
4464 }
4465 }
252b5132 4466
0723899b
ILT		 4467 /* This is a hack. There should be a better way to handle this.
4468 This covers for the fact that bfd_install_relocation will
4469 subtract the current location (for partial_inplace, PC relative
4470 relocations); see more below. */
93382f6d
AM		 4471 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4472 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4473 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7c44d1d3 4474 && fixP->fx_addsy && !use_rela_relocations)
252b5132
RH		 4475 {
4476#ifndef OBJ_AOUT
4477 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4478#ifdef TE_PE
4479 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4480#endif
4481 )
4482 value += fixP->fx_where + fixP->fx_frag->fr_address;
4483#endif
4484#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4485 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4486 {
2f66722d
AM		 4487 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4488
4489 if ((fseg == seg
4490 || (symbol_section_p (fixP->fx_addsy)
4491 && fseg != absolute_section))
29b0f896
AM		 4492 && !S_IS_EXTERNAL (fixP->fx_addsy)
4493 && !S_IS_WEAK (fixP->fx_addsy)
2f66722d 4494 && S_IS_DEFINED (fixP->fx_addsy)
29b0f896 4495 && !S_IS_COMMON (fixP->fx_addsy))
2f66722d
AM		 4496 {
4497 /* Yes, we add the values in twice. This is because
4498 bfd_perform_relocation subtracts them out again. I think
4499 bfd_perform_relocation is broken, but I don't dare change
4500 it. FIXME. */
4501 value += fixP->fx_where + fixP->fx_frag->fr_address;
4502 }
252b5132
RH		 4503 }
4504#endif
4505#if defined (OBJ_COFF) && defined (TE_PE)
4506 /* For some reason, the PE format does not store a section
24eab124 4507 address offset for a PC relative symbol. */
252b5132
RH		 4508 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4509 value += md_pcrel_from (fixP);
4510#endif
4511 }
4512
4513 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4514 and we must not dissappoint it. */
252b5132
RH		 4515#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4516 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4517 && fixP->fx_addsy)
47926f60
KH		 4518 switch (fixP->fx_r_type)
4519 {
4520 case BFD_RELOC_386_PLT32:
3e73aa7c 4521 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4522 /* Make the jump instruction point to the address of the operand. At
4523 runtime we merely add the offset to the actual PLT entry. */
4524 value = -4;
4525 break;
4526 case BFD_RELOC_386_GOTPC:
4527
4528/* This is tough to explain. We end up with this one if we have
252b5132
RH		 4529 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4530 * here is to obtain the absolute address of the GOT, and it is strongly
4531 * preferable from a performance point of view to avoid using a runtime
c3332e24 4532 * relocation for this. The actual sequence of instructions often look
252b5132 4533 * something like:
c3332e24 4534 *
24eab124 4535 * call .L66
252b5132 4536 * .L66:
24eab124
AM		 4537 * popl %ebx
4538 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
c3332e24 4539 *
24eab124 4540 * The call and pop essentially return the absolute address of
252b5132
RH		 4541 * the label .L66 and store it in %ebx. The linker itself will
4542 * ultimately change the first operand of the addl so that %ebx points to
4543 * the GOT, but to keep things simple, the .o file must have this operand
4544 * set so that it generates not the absolute address of .L66, but the
4545 * absolute address of itself. This allows the linker itself simply
4546 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4547 * added in, and the addend of the relocation is stored in the operand
4548 * field for the instruction itself.
c3332e24 4549 *
24eab124 4550 * Our job here is to fix the operand so that it would add the correct
252b5132
RH		 4551 * offset so that %ebx would point to itself. The thing that is tricky is
4552 * that .-.L66 will point to the beginning of the instruction, so we need
4553 * to further modify the operand so that it will point to itself.
4554 * There are other cases where you have something like:
c3332e24 4555 *
24eab124 4556 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
c3332e24 4557 *
252b5132 4558 * and here no correction would be required. Internally in the assembler
c3332e24 4559 * we treat operands of this form as not being pcrel since the '.' is
252b5132
RH		 4560 * explicitly mentioned, and I wonder whether it would simplify matters
4561 * to do it this way. Who knows. In earlier versions of the PIC patches,
4562 * the pcrel_adjust field was used to store the correction, but since the
47926f60
KH		 4563 * expression is not pcrel, I felt it would be confusing to do it this
4564 * way. */
4565
4566 value -= 1;
4567 break;
4568 case BFD_RELOC_386_GOT32:
13ae64f3
JJ		 4569 case BFD_RELOC_386_TLS_GD:
4570 case BFD_RELOC_386_TLS_LDM:
4571 case BFD_RELOC_386_TLS_LDO_32:
4572 case BFD_RELOC_386_TLS_IE_32:
4573 case BFD_RELOC_386_TLS_LE_32:
4574 case BFD_RELOC_386_TLS_LE:
3e73aa7c 4575 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4576 value = 0; /* Fully resolved at runtime. No addend. */
4577 break;
4578 case BFD_RELOC_386_GOTOFF:
3e73aa7c 4579 case BFD_RELOC_X86_64_GOTPCREL:
47926f60
KH		 4580 break;
4581
4582 case BFD_RELOC_VTABLE_INHERIT:
4583 case BFD_RELOC_VTABLE_ENTRY:
4584 fixP->fx_done = 0;
94f592af 4585 return;
47926f60
KH		 4586
4587 default:
4588 break;
4589 }
4590#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4591 *valP = value;
47926f60 4592#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4593
3e73aa7c 4594 /* Are we finished with this relocation now? */
c6682705 4595 if (fixP->fx_addsy == NULL)
3e73aa7c 4596 fixP->fx_done = 1;
94f592af 4597#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4598 else if (use_rela_relocations)
4599 {
4600 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4601 /* Remember value for tc_gen_reloc. */
4602 fixP->fx_addnumber = value;
3e73aa7c
JH		 4603 value = 0;
4604 }
3e73aa7c 4605#endif
94f592af 4606 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4607}
252b5132 4608\f
252b5132
RH		 4609#define MAX_LITTLENUMS 6
4610
47926f60
KH		 4611/* Turn the string pointed to by litP into a floating point constant
4612 of type TYPE, and emit the appropriate bytes. The number of
4613 LITTLENUMS emitted is stored in *SIZEP. An error message is
4614 returned, or NULL on OK. */
4615
252b5132
RH		 4616char *
4617md_atof (type, litP, sizeP)
2ab9b79e 4618 int type;
252b5132
RH		 4619 char *litP;
4620 int *sizeP;
4621{
4622 int prec;
4623 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4624 LITTLENUM_TYPE *wordP;
4625 char *t;
4626
4627 switch (type)
4628 {
4629 case 'f':
4630 case 'F':
4631 prec = 2;
4632 break;
4633
4634 case 'd':
4635 case 'D':
4636 prec = 4;
4637 break;
4638
4639 case 'x':
4640 case 'X':
4641 prec = 5;
4642 break;
4643
4644 default:
4645 *sizeP = 0;
4646 return _("Bad call to md_atof ()");
4647 }
4648 t = atof_ieee (input_line_pointer, type, words);
4649 if (t)
4650 input_line_pointer = t;
4651
4652 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4653 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4654 the bigendian 386. */
4655 for (wordP = words + prec - 1; prec--;)
4656 {
4657 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4658 litP += sizeof (LITTLENUM_TYPE);
4659 }
4660 return 0;
4661}
4662\f
4663char output_invalid_buf[8];
4664
252b5132
RH		 4665static char *
4666output_invalid (c)
4667 int c;
4668{
3882b010 4669 if (ISPRINT (c))
252b5132
RH		 4670 sprintf (output_invalid_buf, "'%c'", c);
4671 else
4672 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4673 return output_invalid_buf;
4674}
4675
af6bdddf 4676/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4677
4678static const reg_entry *
4679parse_register (reg_string, end_op)
4680 char *reg_string;
4681 char **end_op;
4682{
af6bdddf
AM		 4683 char *s = reg_string;
4684 char *p;
252b5132
RH		 4685 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4686 const reg_entry *r;
4687
4688 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4689 if (*s == REGISTER_PREFIX)
4690 ++s;
4691
4692 if (is_space_char (*s))
4693 ++s;
4694
4695 p = reg_name_given;
af6bdddf 4696 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4697 {
4698 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4699 return (const reg_entry *) NULL;
4700 s++;
252b5132
RH		 4701 }
4702
6588847e
DN		 4703 /* For naked regs, make sure that we are not dealing with an identifier.
4704 This prevents confusing an identifier like `eax_var' with register
4705 `eax'. */
4706 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4707 return (const reg_entry *) NULL;
4708
af6bdddf 4709 *end_op = s;
252b5132
RH		 4710
4711 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4712
5f47d35b 4713 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4714 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4715 {
5f47d35b
AM		 4716 if (is_space_char (*s))
4717 ++s;
4718 if (*s == '(')
4719 {
af6bdddf 4720 ++s;
5f47d35b
AM		 4721 if (is_space_char (*s))
4722 ++s;
4723 if (*s >= '0' && *s <= '7')
4724 {
4725 r = &i386_float_regtab[*s - '0'];
af6bdddf 4726 ++s;
5f47d35b
AM		 4727 if (is_space_char (*s))
4728 ++s;
4729 if (*s == ')')
4730 {
4731 *end_op = s + 1;
4732 return r;
4733 }
5f47d35b 4734 }
47926f60 4735 /* We have "%st(" then garbage. */
5f47d35b
AM		 4736 return (const reg_entry *) NULL;
4737 }
4738 }
4739
1ae00879 4740 if (r != NULL
29b0f896 4741 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4742 && flag_code != CODE_64BIT)
4743 {
4744 return (const reg_entry *) NULL;
4745 }
4746
252b5132
RH		 4747 return r;
4748}
4749\f
4cc782b5 4750#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4751const char *md_shortopts = "kVQ:sq";
252b5132 4752#else
65172ab8 4753const char *md_shortopts = "q";
252b5132 4754#endif
6e0b89ee 4755
252b5132 4756struct option md_longopts[] = {
3e73aa7c
JH		 4757#define OPTION_32 (OPTION_MD_BASE + 0)
4758 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4759#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4760#define OPTION_64 (OPTION_MD_BASE + 1)
4761 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4762#endif
252b5132
RH		 4763 {NULL, no_argument, NULL, 0}
4764};
4765size_t md_longopts_size = sizeof (md_longopts);
4766
4767int
4768md_parse_option (c, arg)
4769 int c;
ab9da554 4770 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4771{
4772 switch (c)
4773 {
a38cf1db
AM		 4774 case 'q':
4775 quiet_warnings = 1;
252b5132
RH		 4776 break;
4777
4778#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4779 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4780 should be emitted or not. FIXME: Not implemented. */
4781 case 'Q':
252b5132
RH		 4782 break;
4783
4784 /* -V: SVR4 argument to print version ID. */
4785 case 'V':
4786 print_version_id ();
4787 break;
4788
a38cf1db
AM		 4789 /* -k: Ignore for FreeBSD compatibility. */
4790 case 'k':
252b5132 4791 break;
4cc782b5
ILT		 4792
4793 case 's':
4794 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4795 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4796 break;
6e0b89ee 4797
3e73aa7c
JH		 4798 case OPTION_64:
4799 {
4800 const char **list, **l;
4801
3e73aa7c
JH		 4802 list = bfd_target_list ();
4803 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4804 if (strcmp (*l, "elf64-x86-64") == 0)
4805 {
4806 default_arch = "x86_64";
4807 break;
4808 }
3e73aa7c 4809 if (*l == NULL)
6e0b89ee 4810 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4811 free (list);
4812 }
4813 break;
4814#endif
252b5132 4815
6e0b89ee
AM		 4816 case OPTION_32:
4817 default_arch = "i386";
4818 break;
4819
252b5132
RH		 4820 default:
4821 return 0;
4822 }
4823 return 1;
4824}
4825
4826void
4827md_show_usage (stream)
4828 FILE *stream;
4829{
4cc782b5
ILT		 4830#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4831 fprintf (stream, _("\
a38cf1db
AM		 4832 -Q ignored\n\
4833 -V print assembler version number\n\
4834 -k ignored\n\
4835 -q quieten some warnings\n\
4836 -s ignored\n"));
4837#else
4838 fprintf (stream, _("\
4839 -q quieten some warnings\n"));
4cc782b5 4840#endif
252b5132
RH		 4841}
4842
4843#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4844#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4845 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4846
4847/* Pick the target format to use. */
4848
47926f60 4849const char *
252b5132
RH		 4850i386_target_format ()
4851{
3e73aa7c
JH		 4852 if (!strcmp (default_arch, "x86_64"))
4853 set_code_flag (CODE_64BIT);
4854 else if (!strcmp (default_arch, "i386"))
4855 set_code_flag (CODE_32BIT);
4856 else
4857 as_fatal (_("Unknown architecture"));
252b5132
RH		 4858 switch (OUTPUT_FLAVOR)
4859 {
4c63da97
AM		 4860#ifdef OBJ_MAYBE_AOUT
4861 case bfd_target_aout_flavour:
47926f60 4862 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4863#endif
4864#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4865 case bfd_target_coff_flavour:
4866 return "coff-i386";
4c63da97 4867#endif
3e73aa7c 4868#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4869 case bfd_target_elf_flavour:
3e73aa7c 4870 {
e5cb08ac
KH		 4871 if (flag_code == CODE_64BIT)
4872 use_rela_relocations = 1;
4873 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
3e73aa7c 4874 }
4c63da97 4875#endif
252b5132
RH		 4876 default:
4877 abort ();
4878 return NULL;
4879 }
4880}
4881
47926f60 4882#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4883
4884#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4885void i386_elf_emit_arch_note ()
4886{
4887 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4888 && cpu_arch_name != NULL)
4889 {
4890 char *p;
4891 asection *seg = now_seg;
4892 subsegT subseg = now_subseg;
4893 Elf_Internal_Note i_note;
4894 Elf_External_Note e_note;
4895 asection *note_secp;
4896 int len;
4897
4898 /* Create the .note section. */
4899 note_secp = subseg_new (".note", 0);
4900 bfd_set_section_flags (stdoutput,
4901 note_secp,
4902 SEC_HAS_CONTENTS | SEC_READONLY);
4903
4904 /* Process the arch string. */
4905 len = strlen (cpu_arch_name);
4906
4907 i_note.namesz = len + 1;
4908 i_note.descsz = 0;
4909 i_note.type = NT_ARCH;
4910 p = frag_more (sizeof (e_note.namesz));
4911 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4912 p = frag_more (sizeof (e_note.descsz));
4913 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4914 p = frag_more (sizeof (e_note.type));
4915 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4916 p = frag_more (len + 1);
4917 strcpy (p, cpu_arch_name);
4918
4919 frag_align (2, 0, 0);
4920
4921 subseg_set (seg, subseg);
4922 }
4923}
4924#endif
47926f60 4925#endif /* BFD_ASSEMBLER */
252b5132 4926\f
252b5132
RH		 4927symbolS *
4928md_undefined_symbol (name)
4929 char *name;
4930{
18dc2407
ILT		 4931 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4932 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4933 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4934 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 4935 {
4936 if (!GOT_symbol)
4937 {
4938 if (symbol_find (name))
4939 as_bad (_("GOT already in symbol table"));
4940 GOT_symbol = symbol_new (name, undefined_section,
4941 (valueT) 0, &zero_address_frag);
4942 };
4943 return GOT_symbol;
4944 }
252b5132
RH		 4945 return 0;
4946}
4947
4948/* Round up a section size to the appropriate boundary. */
47926f60 4949
252b5132
RH		 4950valueT
4951md_section_align (segment, size)
ab9da554 4952 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 4953 valueT size;
4954{
252b5132 4955#ifdef BFD_ASSEMBLER
4c63da97
AM		 4956#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4957 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4958 {
4959 /* For a.out, force the section size to be aligned. If we don't do
4960 this, BFD will align it for us, but it will not write out the
4961 final bytes of the section. This may be a bug in BFD, but it is
4962 easier to fix it here since that is how the other a.out targets
4963 work. */
4964 int align;
4965
4966 align = bfd_get_section_alignment (stdoutput, segment);
4967 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4968 }
252b5132
RH		 4969#endif
4970#endif
4971
4972 return size;
4973}
4974
4975/* On the i386, PC-relative offsets are relative to the start of the
4976 next instruction. That is, the address of the offset, plus its
4977 size, since the offset is always the last part of the insn. */
4978
4979long
4980md_pcrel_from (fixP)
4981 fixS *fixP;
4982{
4983 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4984}
4985
4986#ifndef I386COFF
4987
4988static void
4989s_bss (ignore)
ab9da554 4990 int ignore ATTRIBUTE_UNUSED;
252b5132 4991{
29b0f896 4992 int temp;
252b5132
RH		 4993
4994 temp = get_absolute_expression ();
4995 subseg_set (bss_section, (subsegT) temp);
4996 demand_empty_rest_of_line ();
4997}
4998
4999#endif
5000
252b5132
RH		 5001#ifdef BFD_ASSEMBLER
5002
5003void
5004i386_validate_fix (fixp)
5005 fixS *fixp;
5006{
5007 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5008 {
3e73aa7c 5009 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5010 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5011 {
5012 if (flag_code != CODE_64BIT)
5013 abort ();
5014 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5015 }
5016 else
5017 {
5018 if (flag_code == CODE_64BIT)
5019 abort ();
5020 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5021 }
252b5132
RH		 5022 fixp->fx_subsy = 0;
5023 }
5024}
5025
252b5132
RH		 5026arelent *
5027tc_gen_reloc (section, fixp)
ab9da554 5028 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5029 fixS *fixp;
5030{
5031 arelent *rel;
5032 bfd_reloc_code_real_type code;
5033
5034 switch (fixp->fx_r_type)
5035 {
3e73aa7c
JH		 5036 case BFD_RELOC_X86_64_PLT32:
5037 case BFD_RELOC_X86_64_GOT32:
5038 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5039 case BFD_RELOC_386_PLT32:
5040 case BFD_RELOC_386_GOT32:
5041 case BFD_RELOC_386_GOTOFF:
5042 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5043 case BFD_RELOC_386_TLS_GD:
5044 case BFD_RELOC_386_TLS_LDM:
5045 case BFD_RELOC_386_TLS_LDO_32:
5046 case BFD_RELOC_386_TLS_IE_32:
5047 case BFD_RELOC_386_TLS_LE_32:
5048 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5049 case BFD_RELOC_X86_64_32S:
252b5132
RH		 5050 case BFD_RELOC_RVA:
5051 case BFD_RELOC_VTABLE_ENTRY:
5052 case BFD_RELOC_VTABLE_INHERIT:
5053 code = fixp->fx_r_type;
5054 break;
5055 default:
93382f6d 5056 if (fixp->fx_pcrel)
252b5132 5057 {
93382f6d
AM		 5058 switch (fixp->fx_size)
5059 {
5060 default:
b091f402
AM		 5061 as_bad_where (fixp->fx_file, fixp->fx_line,
5062 _("can not do %d byte pc-relative relocation"),
5063 fixp->fx_size);
93382f6d
AM		 5064 code = BFD_RELOC_32_PCREL;
5065 break;
5066 case 1: code = BFD_RELOC_8_PCREL; break;
5067 case 2: code = BFD_RELOC_16_PCREL; break;
5068 case 4: code = BFD_RELOC_32_PCREL; break;
5069 }
5070 }
5071 else
5072 {
5073 switch (fixp->fx_size)
5074 {
5075 default:
b091f402
AM		 5076 as_bad_where (fixp->fx_file, fixp->fx_line,
5077 _("can not do %d byte relocation"),
5078 fixp->fx_size);
93382f6d
AM		 5079 code = BFD_RELOC_32;
5080 break;
5081 case 1: code = BFD_RELOC_8; break;
5082 case 2: code = BFD_RELOC_16; break;
5083 case 4: code = BFD_RELOC_32; break;
937149dd 5084#ifdef BFD64
3e73aa7c 5085 case 8: code = BFD_RELOC_64; break;
937149dd 5086#endif
93382f6d 5087 }
252b5132
RH		 5088 }
5089 break;
5090 }
252b5132
RH		 5091
5092 if (code == BFD_RELOC_32
5093 && GOT_symbol
5094 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5095 {
5096 /* We don't support GOTPC on 64bit targets. */
5097 if (flag_code == CODE_64BIT)
bfb32b52 5098 abort ();
3e73aa7c
JH		 5099 code = BFD_RELOC_386_GOTPC;
5100 }
252b5132
RH		 5101
5102 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5103 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5104 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5105
5106 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5107 if (!use_rela_relocations)
5108 {
5109 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5110 vtable entry to be used in the relocation's section offset. */
5111 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5112 rel->address = fixp->fx_offset;
252b5132 5113
c6682705 5114 rel->addend = 0;
3e73aa7c
JH		 5115 }
5116 /* Use the rela in 64bit mode. */
252b5132 5117 else
3e73aa7c 5118 {
062cd5e7
AS		 5119 if (!fixp->fx_pcrel)
5120 rel->addend = fixp->fx_offset;
5121 else
5122 switch (code)
5123 {
5124 case BFD_RELOC_X86_64_PLT32:
5125 case BFD_RELOC_X86_64_GOT32:
5126 case BFD_RELOC_X86_64_GOTPCREL:
5127 rel->addend = fixp->fx_offset - fixp->fx_size;
5128 break;
5129 default:
5130 rel->addend = (section->vma
5131 - fixp->fx_size
5132 + fixp->fx_addnumber
5133 + md_pcrel_from (fixp));
5134 break;
5135 }
3e73aa7c
JH		 5136 }
5137
252b5132
RH		 5138 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5139 if (rel->howto == NULL)
5140 {
5141 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5142 _("cannot represent relocation type %s"),
252b5132
RH		 5143 bfd_get_reloc_code_name (code));
5144 /* Set howto to a garbage value so that we can keep going. */
5145 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5146 assert (rel->howto != NULL);
5147 }
5148
5149 return rel;
5150}
5151
29b0f896 5152#else /* !BFD_ASSEMBLER */
252b5132
RH		 5153
5154#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5155void
5156tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5157 char *where;
5158 fixS *fixP;
5159 relax_addressT segment_address_in_file;
5160{
47926f60
KH		 5161 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5162 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5163
47926f60 5164 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5165 long r_symbolnum;
5166
5167 know (fixP->fx_addsy != NULL);
5168
5169 md_number_to_chars (where,
5170 (valueT) (fixP->fx_frag->fr_address
5171 + fixP->fx_where - segment_address_in_file),
5172 4);
5173
5174 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5175 ? S_GET_TYPE (fixP->fx_addsy)
5176 : fixP->fx_addsy->sy_number);
5177
5178 where[6] = (r_symbolnum >> 16) & 0x0ff;
5179 where[5] = (r_symbolnum >> 8) & 0x0ff;
5180 where[4] = r_symbolnum & 0x0ff;
5181 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5182 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5183 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5184}
5185
47926f60 5186#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5187
5188#if defined (I386COFF)
5189
5190short
5191tc_coff_fix2rtype (fixP)
5192 fixS *fixP;
5193{
5194 if (fixP->fx_r_type == R_IMAGEBASE)
5195 return R_IMAGEBASE;
5196
5197 return (fixP->fx_pcrel ?
5198 (fixP->fx_size == 1 ? R_PCRBYTE :
5199 fixP->fx_size == 2 ? R_PCRWORD :
5200 R_PCRLONG) :
5201 (fixP->fx_size == 1 ? R_RELBYTE :
5202 fixP->fx_size == 2 ? R_RELWORD :
5203 R_DIR32));
5204}
5205
5206int
5207tc_coff_sizemachdep (frag)
5208 fragS *frag;
5209{
5210 if (frag->fr_next)
5211 return (frag->fr_next->fr_address - frag->fr_address);
5212 else
5213 return 0;
5214}
5215
47926f60 5216#endif /* I386COFF */
252b5132 5217
29b0f896 5218#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5219\f
5220/* Parse operands using Intel syntax. This implements a recursive descent
5221 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5222 Programmer's Guide.
5223
5224 FIXME: We do not recognize the full operand grammar defined in the MASM
5225 documentation. In particular, all the structure/union and
5226 high-level macro operands are missing.
5227
5228 Uppercase words are terminals, lower case words are non-terminals.
5229 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5230 bars '|' denote choices. Most grammar productions are implemented in
5231 functions called 'intel_<production>'.
5232
5233 Initial production is 'expr'.
5234
64a0c779
DN		 5235 addOp + | -
5236
5237 alpha [a-zA-Z]
5238
5239 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5240
5241 constant digits [[ radixOverride ]]
5242
5243 dataType BYTE | WORD | DWORD | QWORD | XWORD
5244
5245 digits decdigit
b77a7acd
AJ		 5246 | digits decdigit
5247 | digits hexdigit
64a0c779
DN		 5248
5249 decdigit [0-9]
5250
5251 e05 e05 addOp e06
b77a7acd 5252 | e06
64a0c779
DN		 5253
5254 e06 e06 mulOp e09
b77a7acd 5255 | e09
64a0c779
DN		 5256
5257 e09 OFFSET e10
5258 | e09 PTR e10
5259 | e09 : e10
5260 | e10
5261
5262 e10 e10 [ expr ]
b77a7acd 5263 | e11
64a0c779
DN		 5264
5265 e11 ( expr )
b77a7acd 5266 | [ expr ]
64a0c779
DN		 5267 | constant
5268 | dataType
5269 | id
5270 | $
5271 | register
5272
5273 => expr SHORT e05
b77a7acd 5274 | e05
64a0c779
DN		 5275
5276 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5277 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5278
5279 hexdigit a | b | c | d | e | f
b77a7acd 5280 | A | B | C | D | E | F
64a0c779
DN		 5281
5282 id alpha
b77a7acd 5283 | id alpha
64a0c779
DN		 5284 | id decdigit
5285
5286 mulOp * | / | MOD
5287
5288 quote " | '
5289
5290 register specialRegister
b77a7acd 5291 | gpRegister
64a0c779
DN		 5292 | byteRegister
5293
5294 segmentRegister CS | DS | ES | FS | GS | SS
5295
5296 specialRegister CR0 | CR2 | CR3
b77a7acd 5297 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5298 | TR3 | TR4 | TR5 | TR6 | TR7
5299
64a0c779
DN		 5300 We simplify the grammar in obvious places (e.g., register parsing is
5301 done by calling parse_register) and eliminate immediate left recursion
5302 to implement a recursive-descent parser.
5303
5304 expr SHORT e05
b77a7acd 5305 | e05
64a0c779
DN		 5306
5307 e05 e06 e05'
5308
5309 e05' addOp e06 e05'
b77a7acd 5310 | Empty
64a0c779
DN		 5311
5312 e06 e09 e06'
5313
5314 e06' mulOp e09 e06'
b77a7acd 5315 | Empty
64a0c779
DN		 5316
5317 e09 OFFSET e10 e09'
b77a7acd 5318 | e10 e09'
64a0c779
DN		 5319
5320 e09' PTR e10 e09'
b77a7acd 5321 | : e10 e09'
64a0c779
DN		 5322 | Empty
5323
5324 e10 e11 e10'
5325
5326 e10' [ expr ] e10'
b77a7acd 5327 | Empty
64a0c779
DN		 5328
5329 e11 ( expr )
b77a7acd 5330 | [ expr ]
64a0c779
DN		 5331 | BYTE
5332 | WORD
5333 | DWORD
5334 | QWORD
5335 | XWORD
5336 | .
5337 | $
5338 | register
5339 | id
5340 | constant */
5341
5342/* Parsing structure for the intel syntax parser. Used to implement the
5343 semantic actions for the operand grammar. */
5344struct intel_parser_s
5345 {
5346 char *op_string; /* The string being parsed. */
5347 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5348 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5349 int is_mem; /* 1 if operand is memory reference. */
5350 const reg_entry *reg; /* Last register reference found. */
5351 char *disp; /* Displacement string being built. */
5352 };
5353
5354static struct intel_parser_s intel_parser;
5355
5356/* Token structure for parsing intel syntax. */
5357struct intel_token
5358 {
5359 int code; /* Token code. */
5360 const reg_entry *reg; /* Register entry for register tokens. */
5361 char *str; /* String representation. */
5362 };
5363
5364static struct intel_token cur_token, prev_token;
5365
50705ef4
AM		 5366/* Token codes for the intel parser. Since T_SHORT is already used
5367 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5368#define T_NIL -1
5369#define T_CONST 1
5370#define T_REG 2
5371#define T_BYTE 3
5372#define T_WORD 4
5373#define T_DWORD 5
5374#define T_QWORD 6
5375#define T_XWORD 7
50705ef4 5376#undef T_SHORT
64a0c779
DN		 5377#define T_SHORT 8
5378#define T_OFFSET 9
5379#define T_PTR 10
5380#define T_ID 11
5381
5382/* Prototypes for intel parser functions. */
5383static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5384static void intel_get_token PARAMS ((void));
5385static void intel_putback_token PARAMS ((void));
5386static int intel_expr PARAMS ((void));
5387static int intel_e05 PARAMS ((void));
5388static int intel_e05_1 PARAMS ((void));
5389static int intel_e06 PARAMS ((void));
5390static int intel_e06_1 PARAMS ((void));
5391static int intel_e09 PARAMS ((void));
5392static int intel_e09_1 PARAMS ((void));
5393static int intel_e10 PARAMS ((void));
5394static int intel_e10_1 PARAMS ((void));
5395static int intel_e11 PARAMS ((void));
64a0c779 5396
64a0c779
DN		 5397static int
5398i386_intel_operand (operand_string, got_a_float)
5399 char *operand_string;
5400 int got_a_float;
5401{
5402 int ret;
5403 char *p;
5404
5405 /* Initialize token holders. */
5406 cur_token.code = prev_token.code = T_NIL;
5407 cur_token.reg = prev_token.reg = NULL;
5408 cur_token.str = prev_token.str = NULL;
5409
5410 /* Initialize parser structure. */
e5cb08ac 5411 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5412 if (p == NULL)
5413 abort ();
5414 strcpy (intel_parser.op_string, operand_string);
5415 intel_parser.got_a_float = got_a_float;
5416 intel_parser.op_modifier = -1;
5417 intel_parser.is_mem = 0;
5418 intel_parser.reg = NULL;
e5cb08ac 5419 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5420 if (intel_parser.disp == NULL)
5421 abort ();
5422 intel_parser.disp[0] = '\0';
5423
5424 /* Read the first token and start the parser. */
5425 intel_get_token ();
5426 ret = intel_expr ();
5427
5428 if (ret)
5429 {
5430 /* If we found a memory reference, hand it over to i386_displacement
5431 to fill in the rest of the operand fields. */
5432 if (intel_parser.is_mem)
5433 {
5434 if ((i.mem_operands == 1
5435 && (current_templates->start->opcode_modifier & IsString) == 0)
5436 || i.mem_operands == 2)
5437 {
5438 as_bad (_("too many memory references for '%s'"),
5439 current_templates->start->name);
5440 ret = 0;
5441 }
5442 else
5443 {
5444 char *s = intel_parser.disp;
5445 i.mem_operands++;
5446
5447 /* Add the displacement expression. */
5448 if (*s != '\0')
5449 ret = i386_displacement (s, s + strlen (s))
5450 && i386_index_check (s);
5451 }
5452 }
5453
5454 /* Constant and OFFSET expressions are handled by i386_immediate. */
5455 else if (intel_parser.op_modifier == OFFSET_FLAT
5456 || intel_parser.reg == NULL)
5457 ret = i386_immediate (intel_parser.disp);
5458 }
5459
5460 free (p);
5461 free (intel_parser.disp);
5462
5463 return ret;
5464}
5465
64a0c779 5466/* expr SHORT e05
b77a7acd 5467 | e05 */
64a0c779
DN		 5468static int
5469intel_expr ()
5470{
5471 /* expr SHORT e05 */
5472 if (cur_token.code == T_SHORT)
5473 {
5474 intel_parser.op_modifier = SHORT;
5475 intel_match_token (T_SHORT);
5476
5477 return (intel_e05 ());
5478 }
5479
5480 /* expr e05 */
5481 else
5482 return intel_e05 ();
5483}
5484
64a0c779
DN		 5485/* e05 e06 e05'
5486
4a1805b1 5487 e05' addOp e06 e05'
64a0c779
DN		 5488 | Empty */
5489static int
5490intel_e05 ()
5491{
5492 return (intel_e06 () && intel_e05_1 ());
5493}
5494
5495static int
5496intel_e05_1 ()
5497{
5498 /* e05' addOp e06 e05' */
5499 if (cur_token.code == '+' || cur_token.code == '-')
5500 {
5501 strcat (intel_parser.disp, cur_token.str);
5502 intel_match_token (cur_token.code);
5503
5504 return (intel_e06 () && intel_e05_1 ());
5505 }
5506
5507 /* e05' Empty */
5508 else
5509 return 1;
4a1805b1 5510}
64a0c779
DN		 5511
5512/* e06 e09 e06'
5513
5514 e06' mulOp e09 e06'
b77a7acd 5515 | Empty */
64a0c779
DN		 5516static int
5517intel_e06 ()
5518{
5519 return (intel_e09 () && intel_e06_1 ());
5520}
5521
5522static int
5523intel_e06_1 ()
5524{
5525 /* e06' mulOp e09 e06' */
5526 if (cur_token.code == '*' || cur_token.code == '/')
5527 {
5528 strcat (intel_parser.disp, cur_token.str);
5529 intel_match_token (cur_token.code);
5530
5531 return (intel_e09 () && intel_e06_1 ());
5532 }
4a1805b1 5533
64a0c779 5534 /* e06' Empty */
4a1805b1 5535 else
64a0c779
DN		 5536 return 1;
5537}
5538
64a0c779 5539/* e09 OFFSET e10 e09'
b77a7acd 5540 | e10 e09'
64a0c779
DN		 5541
5542 e09' PTR e10 e09'
b77a7acd 5543 | : e10 e09'
64a0c779
DN		 5544 | Empty */
5545static int
5546intel_e09 ()
5547{
5548 /* e09 OFFSET e10 e09' */
5549 if (cur_token.code == T_OFFSET)
5550 {
5551 intel_parser.is_mem = 0;
5552 intel_parser.op_modifier = OFFSET_FLAT;
5553 intel_match_token (T_OFFSET);
5554
5555 return (intel_e10 () && intel_e09_1 ());
5556 }
5557
5558 /* e09 e10 e09' */
5559 else
5560 return (intel_e10 () && intel_e09_1 ());
5561}
5562
5563static int
5564intel_e09_1 ()
5565{
5566 /* e09' PTR e10 e09' */
5567 if (cur_token.code == T_PTR)
5568 {
5569 if (prev_token.code == T_BYTE)
5570 i.suffix = BYTE_MNEM_SUFFIX;
5571
5572 else if (prev_token.code == T_WORD)
5573 {
5574 if (intel_parser.got_a_float == 2) /* "fi..." */
5575 i.suffix = SHORT_MNEM_SUFFIX;
5576 else
5577 i.suffix = WORD_MNEM_SUFFIX;
5578 }
5579
5580 else if (prev_token.code == T_DWORD)
5581 {
5582 if (intel_parser.got_a_float == 1) /* "f..." */
5583 i.suffix = SHORT_MNEM_SUFFIX;
5584 else
5585 i.suffix = LONG_MNEM_SUFFIX;
5586 }
5587
5588 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5589 {
5590 if (intel_parser.got_a_float == 1) /* "f..." */
5591 i.suffix = LONG_MNEM_SUFFIX;
5592 else
3e73aa7c 5593 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5594 }
64a0c779
DN		 5595
5596 else if (prev_token.code == T_XWORD)
5597 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5598
5599 else
5600 {
5601 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5602 return 0;
5603 }
5604
5605 intel_match_token (T_PTR);
5606
5607 return (intel_e10 () && intel_e09_1 ());
5608 }
5609
5610 /* e09 : e10 e09' */
5611 else if (cur_token.code == ':')
5612 {
21d6c4af
DN		 5613 /* Mark as a memory operand only if it's not already known to be an
5614 offset expression. */
5615 if (intel_parser.op_modifier != OFFSET_FLAT)
5616 intel_parser.is_mem = 1;
64a0c779
DN		 5617
5618 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5619 }
5620
5621 /* e09' Empty */
5622 else
5623 return 1;
5624}
5625
5626/* e10 e11 e10'
5627
5628 e10' [ expr ] e10'
b77a7acd 5629 | Empty */
64a0c779
DN		 5630static int
5631intel_e10 ()
5632{
5633 return (intel_e11 () && intel_e10_1 ());
5634}
5635
5636static int
5637intel_e10_1 ()
5638{
5639 /* e10' [ expr ] e10' */
5640 if (cur_token.code == '[')
5641 {
5642 intel_match_token ('[');
21d6c4af
DN		 5643
5644 /* Mark as a memory operand only if it's not already known to be an
5645 offset expression. If it's an offset expression, we need to keep
5646 the brace in. */
5647 if (intel_parser.op_modifier != OFFSET_FLAT)
5648 intel_parser.is_mem = 1;
5649 else
5650 strcat (intel_parser.disp, "[");
4a1805b1 5651
64a0c779 5652 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5653 if (*intel_parser.disp != '\0'
5654 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5655 strcat (intel_parser.disp, "+");
5656
21d6c4af
DN		 5657 if (intel_expr () && intel_match_token (']'))
5658 {
5659 /* Preserve brackets when the operand is an offset expression. */
5660 if (intel_parser.op_modifier == OFFSET_FLAT)
5661 strcat (intel_parser.disp, "]");
5662
5663 return intel_e10_1 ();
5664 }
5665 else
5666 return 0;
64a0c779
DN		 5667 }
5668
5669 /* e10' Empty */
5670 else
5671 return 1;
5672}
5673
64a0c779 5674/* e11 ( expr )
b77a7acd 5675 | [ expr ]
64a0c779
DN		 5676 | BYTE
5677 | WORD
5678 | DWORD
5679 | QWORD
5680 | XWORD
4a1805b1 5681 | $
64a0c779
DN		 5682 | .
5683 | register
5684 | id
5685 | constant */
5686static int
5687intel_e11 ()
5688{
5689 /* e11 ( expr ) */
5690 if (cur_token.code == '(')
5691 {
5692 intel_match_token ('(');
5693 strcat (intel_parser.disp, "(");
5694
5695 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5696 {
5697 strcat (intel_parser.disp, ")");
5698 return 1;
5699 }
64a0c779
DN		 5700 else
5701 return 0;
5702 }
5703
5704 /* e11 [ expr ] */
5705 else if (cur_token.code == '[')
5706 {
5707 intel_match_token ('[');
21d6c4af
DN		 5708
5709 /* Mark as a memory operand only if it's not already known to be an
5710 offset expression. If it's an offset expression, we need to keep
5711 the brace in. */
5712 if (intel_parser.op_modifier != OFFSET_FLAT)
5713 intel_parser.is_mem = 1;
5714 else
5715 strcat (intel_parser.disp, "[");
4a1805b1 5716
64a0c779
DN		 5717 /* Operands for jump/call inside brackets denote absolute addresses. */
5718 if (current_templates->start->opcode_modifier & Jump
5719 || current_templates->start->opcode_modifier & JumpDword
5720 || current_templates->start->opcode_modifier & JumpByte
5721 || current_templates->start->opcode_modifier & JumpInterSegment)
5722 i.types[this_operand] |= JumpAbsolute;
5723
5724 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5725 if (*intel_parser.disp != '\0'
5726 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5727 strcat (intel_parser.disp, "+");
5728
21d6c4af
DN		 5729 if (intel_expr () && intel_match_token (']'))
5730 {
5731 /* Preserve brackets when the operand is an offset expression. */
5732 if (intel_parser.op_modifier == OFFSET_FLAT)
5733 strcat (intel_parser.disp, "]");
5734
5735 return 1;
5736 }
5737 else
5738 return 0;
64a0c779
DN		 5739 }
5740
4a1805b1 5741 /* e11 BYTE
64a0c779
DN		 5742 | WORD
5743 | DWORD
5744 | QWORD
5745 | XWORD */
5746 else if (cur_token.code == T_BYTE
5747 || cur_token.code == T_WORD
5748 || cur_token.code == T_DWORD
5749 || cur_token.code == T_QWORD
5750 || cur_token.code == T_XWORD)
5751 {
5752 intel_match_token (cur_token.code);
5753
5754 return 1;
5755 }
5756
5757 /* e11 $
5758 | . */
5759 else if (cur_token.code == '$' || cur_token.code == '.')
5760 {
5761 strcat (intel_parser.disp, cur_token.str);
5762 intel_match_token (cur_token.code);
21d6c4af
DN		 5763
5764 /* Mark as a memory operand only if it's not already known to be an
5765 offset expression. */
5766 if (intel_parser.op_modifier != OFFSET_FLAT)
5767 intel_parser.is_mem = 1;
64a0c779
DN		 5768
5769 return 1;
5770 }
5771
5772 /* e11 register */
5773 else if (cur_token.code == T_REG)
5774 {
5775 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5776
5777 intel_match_token (T_REG);
5778
5779 /* Check for segment change. */
5780 if (cur_token.code == ':')
5781 {
5782 if (reg->reg_type & (SReg2 | SReg3))
5783 {
5784 switch (reg->reg_num)
5785 {
5786 case 0:
5787 i.seg[i.mem_operands] = &es;
5788 break;
5789 case 1:
5790 i.seg[i.mem_operands] = &cs;
5791 break;
5792 case 2:
5793 i.seg[i.mem_operands] = &ss;
5794 break;
5795 case 3:
5796 i.seg[i.mem_operands] = &ds;
5797 break;
5798 case 4:
5799 i.seg[i.mem_operands] = &fs;
5800 break;
5801 case 5:
5802 i.seg[i.mem_operands] = &gs;
5803 break;
5804 }
5805 }
5806 else
5807 {
5808 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5809 return 0;
5810 }
5811 }
5812
5813 /* Not a segment register. Check for register scaling. */
5814 else if (cur_token.code == '*')
5815 {
5816 if (!intel_parser.is_mem)
5817 {
5818 as_bad (_("Register scaling only allowed in memory operands."));
5819 return 0;
5820 }
5821
4a1805b1 5822 /* What follows must be a valid scale. */
64a0c779
DN		 5823 if (intel_match_token ('*')
5824 && strchr ("01248", *cur_token.str))
5825 {
5826 i.index_reg = reg;
5827 i.types[this_operand] |= BaseIndex;
5828
5829 /* Set the scale after setting the register (otherwise,
5830 i386_scale will complain) */
5831 i386_scale (cur_token.str);
5832 intel_match_token (T_CONST);
5833 }
5834 else
5835 {
5836 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5837 cur_token.str);
5838 return 0;
5839 }
5840 }
5841
5842 /* No scaling. If this is a memory operand, the register is either a
5843 base register (first occurrence) or an index register (second
5844 occurrence). */
5845 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5846 {
5847 if (i.base_reg && i.index_reg)
5848 {
5849 as_bad (_("Too many register references in memory operand.\n"));
5850 return 0;
5851 }
5852
5853 if (i.base_reg == NULL)
5854 i.base_reg = reg;
5855 else
5856 i.index_reg = reg;
5857
5858 i.types[this_operand] |= BaseIndex;
5859 }
5860
5861 /* Offset modifier. Add the register to the displacement string to be
5862 parsed as an immediate expression after we're done. */
5863 else if (intel_parser.op_modifier == OFFSET_FLAT)
5864 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5865
64a0c779
DN		 5866 /* It's neither base nor index nor offset. */
5867 else
5868 {
5869 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5870 i.op[this_operand].regs = reg;
5871 i.reg_operands++;
5872 }
5873
5874 /* Since registers are not part of the displacement string (except
5875 when we're parsing offset operands), we may need to remove any
5876 preceding '+' from the displacement string. */
5877 if (*intel_parser.disp != '\0'
5878 && intel_parser.op_modifier != OFFSET_FLAT)
5879 {
5880 char *s = intel_parser.disp;
5881 s += strlen (s) - 1;
5882 if (*s == '+')
5883 *s = '\0';
5884 }
5885
5886 return 1;
5887 }
4a1805b1 5888
64a0c779
DN		 5889 /* e11 id */
5890 else if (cur_token.code == T_ID)
5891 {
5892 /* Add the identifier to the displacement string. */
5893 strcat (intel_parser.disp, cur_token.str);
5894 intel_match_token (T_ID);
5895
5896 /* The identifier represents a memory reference only if it's not
5897 preceded by an offset modifier. */
21d6c4af 5898 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 5899 intel_parser.is_mem = 1;
5900
5901 return 1;
5902 }
5903
5904 /* e11 constant */
5905 else if (cur_token.code == T_CONST
e5cb08ac 5906 || cur_token.code == '-'
64a0c779
DN		 5907 || cur_token.code == '+')
5908 {
5909 char *save_str;
5910
5911 /* Allow constants that start with `+' or `-'. */
5912 if (cur_token.code == '-' || cur_token.code == '+')
5913 {
5914 strcat (intel_parser.disp, cur_token.str);
5915 intel_match_token (cur_token.code);
5916 if (cur_token.code != T_CONST)
5917 {
5918 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5919 cur_token.str);
5920 return 0;
5921 }
5922 }
5923
e5cb08ac 5924 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 5925 if (save_str == NULL)
bc805888 5926 abort ();
64a0c779
DN		 5927 strcpy (save_str, cur_token.str);
5928
5929 /* Get the next token to check for register scaling. */
5930 intel_match_token (cur_token.code);
5931
5932 /* Check if this constant is a scaling factor for an index register. */
5933 if (cur_token.code == '*')
5934 {
5935 if (intel_match_token ('*') && cur_token.code == T_REG)
5936 {
5937 if (!intel_parser.is_mem)
5938 {
5939 as_bad (_("Register scaling only allowed in memory operands."));
5940 return 0;
5941 }
5942
4a1805b1 5943 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 5944 a valid scale. */
5945 if (strchr ("01248", *save_str))
5946 {
5947 i.index_reg = cur_token.reg;
5948 i.types[this_operand] |= BaseIndex;
5949
5950 /* Set the scale after setting the register (otherwise,
5951 i386_scale will complain) */
5952 i386_scale (save_str);
5953 intel_match_token (T_REG);
5954
5955 /* Since registers are not part of the displacement
5956 string, we may need to remove any preceding '+' from
5957 the displacement string. */
5958 if (*intel_parser.disp != '\0')
5959 {
5960 char *s = intel_parser.disp;
5961 s += strlen (s) - 1;
5962 if (*s == '+')
5963 *s = '\0';
5964 }
5965
5966 free (save_str);
5967
5968 return 1;
5969 }
5970 else
5971 return 0;
5972 }
5973
5974 /* The constant was not used for register scaling. Since we have
5975 already consumed the token following `*' we now need to put it
5976 back in the stream. */
5977 else
5978 intel_putback_token ();
5979 }
5980
5981 /* Add the constant to the displacement string. */
5982 strcat (intel_parser.disp, save_str);
5983 free (save_str);
5984
5985 return 1;
5986 }
5987
64a0c779
DN		 5988 as_bad (_("Unrecognized token '%s'"), cur_token.str);
5989 return 0;
5990}
5991
64a0c779
DN		 5992/* Match the given token against cur_token. If they match, read the next
5993 token from the operand string. */
5994static int
5995intel_match_token (code)
e5cb08ac 5996 int code;
64a0c779
DN		 5997{
5998 if (cur_token.code == code)
5999 {
6000 intel_get_token ();
6001 return 1;
6002 }
6003 else
6004 {
6005 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6006 return 0;
6007 }
6008}
6009
64a0c779
DN		 6010/* Read a new token from intel_parser.op_string and store it in cur_token. */
6011static void
6012intel_get_token ()
6013{
6014 char *end_op;
6015 const reg_entry *reg;
6016 struct intel_token new_token;
6017
6018 new_token.code = T_NIL;
6019 new_token.reg = NULL;
6020 new_token.str = NULL;
6021
4a1805b1 6022 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6023 cur_token to prev_token. */
6024 if (prev_token.str)
6025 free (prev_token.str);
6026
6027 prev_token = cur_token;
6028
6029 /* Skip whitespace. */
6030 while (is_space_char (*intel_parser.op_string))
6031 intel_parser.op_string++;
6032
6033 /* Return an empty token if we find nothing else on the line. */
6034 if (*intel_parser.op_string == '\0')
6035 {
6036 cur_token = new_token;
6037 return;
6038 }
6039
6040 /* The new token cannot be larger than the remainder of the operand
6041 string. */
e5cb08ac 6042 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6043 if (new_token.str == NULL)
bc805888 6044 abort ();
64a0c779
DN		 6045 new_token.str[0] = '\0';
6046
6047 if (strchr ("0123456789", *intel_parser.op_string))
6048 {
6049 char *p = new_token.str;
6050 char *q = intel_parser.op_string;
6051 new_token.code = T_CONST;
6052
6053 /* Allow any kind of identifier char to encompass floating point and
6054 hexadecimal numbers. */
6055 while (is_identifier_char (*q))
6056 *p++ = *q++;
6057 *p = '\0';
6058
6059 /* Recognize special symbol names [0-9][bf]. */
6060 if (strlen (intel_parser.op_string) == 2
4a1805b1 6061 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6062 || intel_parser.op_string[1] == 'f'))
6063 new_token.code = T_ID;
6064 }
6065
6066 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6067 {
6068 new_token.code = *intel_parser.op_string;
6069 new_token.str[0] = *intel_parser.op_string;
6070 new_token.str[1] = '\0';
6071 }
6072
6073 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6074 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6075 {
6076 new_token.code = T_REG;
6077 new_token.reg = reg;
6078
6079 if (*intel_parser.op_string == REGISTER_PREFIX)
6080 {
6081 new_token.str[0] = REGISTER_PREFIX;
6082 new_token.str[1] = '\0';
6083 }
6084
6085 strcat (new_token.str, reg->reg_name);
6086 }
6087
6088 else if (is_identifier_char (*intel_parser.op_string))
6089 {
6090 char *p = new_token.str;
6091 char *q = intel_parser.op_string;
6092
6093 /* A '.' or '$' followed by an identifier char is an identifier.
6094 Otherwise, it's operator '.' followed by an expression. */
6095 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6096 {
6097 new_token.code = *q;
6098 new_token.str[0] = *q;
6099 new_token.str[1] = '\0';
6100 }
6101 else
6102 {
6103 while (is_identifier_char (*q) || *q == '@')
6104 *p++ = *q++;
6105 *p = '\0';
6106
6107 if (strcasecmp (new_token.str, "BYTE") == 0)
6108 new_token.code = T_BYTE;
6109
6110 else if (strcasecmp (new_token.str, "WORD") == 0)
6111 new_token.code = T_WORD;
6112
6113 else if (strcasecmp (new_token.str, "DWORD") == 0)
6114 new_token.code = T_DWORD;
6115
6116 else if (strcasecmp (new_token.str, "QWORD") == 0)
6117 new_token.code = T_QWORD;
6118
6119 else if (strcasecmp (new_token.str, "XWORD") == 0)
6120 new_token.code = T_XWORD;
6121
6122 else if (strcasecmp (new_token.str, "PTR") == 0)
6123 new_token.code = T_PTR;
6124
6125 else if (strcasecmp (new_token.str, "SHORT") == 0)
6126 new_token.code = T_SHORT;
6127
6128 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6129 {
6130 new_token.code = T_OFFSET;
6131
6132 /* ??? This is not mentioned in the MASM grammar but gcc
6133 makes use of it with -mintel-syntax. OFFSET may be
6134 followed by FLAT: */
6135 if (strncasecmp (q, " FLAT:", 6) == 0)
6136 strcat (new_token.str, " FLAT:");
6137 }
6138
6139 /* ??? This is not mentioned in the MASM grammar. */
6140 else if (strcasecmp (new_token.str, "FLAT") == 0)
6141 new_token.code = T_OFFSET;
6142
6143 else
6144 new_token.code = T_ID;
6145 }
6146 }
6147
6148 else
6149 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6150
6151 intel_parser.op_string += strlen (new_token.str);
6152 cur_token = new_token;
6153}
6154
64a0c779
DN		 6155/* Put cur_token back into the token stream and make cur_token point to
6156 prev_token. */
6157static void
6158intel_putback_token ()
6159{
6160 intel_parser.op_string -= strlen (cur_token.str);
6161 free (cur_token.str);
6162 cur_token = prev_token;
4a1805b1 6163
64a0c779
DN		 6164 /* Forget prev_token. */
6165 prev_token.code = T_NIL;
6166 prev_token.reg = NULL;
6167 prev_token.str = NULL;
6168}
GDB Binutils - Deliverables
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