projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gas/ELF: slightly relax elf/file*.d expectations
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
8dcea932
L		 521#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522/* 1 if generating code for a shared library. */
523static int shared = 0;
524#endif
525
47926f60
KH		 526/* 1 for intel syntax,
527 0 if att syntax. */
528static int intel_syntax = 0;
252b5132 529
1efbbeb4
L		 530/* 1 for intel mnemonic,
531 0 if att mnemonic. */
532static int intel_mnemonic = !SYSV386_COMPAT;
533
5209009a 534/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 535static int old_gcc = OLDGCC_COMPAT;
536
a60de03c
JB		 537/* 1 if pseudo registers are permitted. */
538static int allow_pseudo_reg = 0;
539
47926f60
KH		 540/* 1 if register prefix % not required. */
541static int allow_naked_reg = 0;
252b5132 542
7e8b059b
L		 543/* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
545 explicitly. */
546static int add_bnd_prefix = 0;
547
ba104c83 548/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 549static int allow_index_reg = 0;
550
d022bddd
IT		 551/* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553static int omit_lock_prefix = 0;
554
7bab8ab5 555static enum check_kind
daf50ae7 556 {
7bab8ab5
JB		 557 check_none = 0,
558 check_warning,
559 check_error
daf50ae7 560 }
7bab8ab5 561sse_check, operand_check = check_warning;
daf50ae7 562
2ca3ace5
L		 563/* Register prefix used for error message. */
564static const char *register_prefix = "%";
565
47926f60
KH		 566/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569static char stackop_size = '\0';
eecb386c 570
12b55ccc
L		 571/* Non-zero to optimize code alignment. */
572int optimize_align_code = 1;
573
47926f60
KH		 574/* Non-zero to quieten some warnings. */
575static int quiet_warnings = 0;
a38cf1db 576
47926f60
KH		 577/* CPU name. */
578static const char *cpu_arch_name = NULL;
6305a203 579static char *cpu_sub_arch_name = NULL;
a38cf1db 580
47926f60 581/* CPU feature flags. */
40fb9820
L		 582static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
583
ccc9c027
L		 584/* If we have selected a cpu we are generating instructions for. */
585static int cpu_arch_tune_set = 0;
586
9103f4f4 587/* Cpu we are generating instructions for. */
fbf3f584 588enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 589
590/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 591static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 592
ccc9c027 593/* CPU instruction set architecture used. */
fbf3f584 594enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 595
9103f4f4 596/* CPU feature flags of instruction set architecture used. */
fbf3f584 597i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 598
fddf5b5b
AM		 599/* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601static unsigned int no_cond_jump_promotion = 0;
602
c0f3af97
L		 603/* Encode SSE instructions with VEX prefix. */
604static unsigned int sse2avx;
605
539f890d
L		 606/* Encode scalar AVX instructions with specific vector length. */
607static enum
608 {
609 vex128 = 0,
610 vex256
611 } avxscalar;
612
43234a1e
L		 613/* Encode scalar EVEX LIG instructions with specific vector length. */
614static enum
615 {
616 evexl128 = 0,
617 evexl256,
618 evexl512
619 } evexlig;
620
621/* Encode EVEX WIG instructions with specific evex.w. */
622static enum
623 {
624 evexw0 = 0,
625 evexw1
626 } evexwig;
627
d3d3c6db
IT		 628/* Value to encode in EVEX RC bits, for SAE-only instructions. */
629static enum rc_type evexrcig = rne;
630
29b0f896 631/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 632static symbolS *GOT_symbol;
29b0f896 633
a4447b93
RH		 634/* The dwarf2 return column, adjusted for 32 or 64 bit. */
635unsigned int x86_dwarf2_return_column;
636
637/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638int x86_cie_data_alignment;
639
252b5132 640/* Interface to relax_segment.
fddf5b5b
AM		 641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
252b5132 644
47926f60 645/* Types. */
93c2a809
AM		 646#define UNCOND_JUMP 0
647#define COND_JUMP 1
648#define COND_JUMP86 2
fddf5b5b 649
47926f60 650/* Sizes. */
252b5132
RH		 651#define CODE16 1
652#define SMALL 0
29b0f896 653#define SMALL16 (SMALL | CODE16)
252b5132 654#define BIG 2
29b0f896 655#define BIG16 (BIG | CODE16)
252b5132
RH		 656
657#ifndef INLINE
658#ifdef __GNUC__
659#define INLINE __inline__
660#else
661#define INLINE
662#endif
663#endif
664
fddf5b5b
AM		 665#define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667#define TYPE_FROM_RELAX_STATE(s) \
668 ((s) >> 2)
669#define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 671
672/* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
679
680const relax_typeS md_relax_table[] =
681{
24eab124
AM		 682 /* The fields are:
683 1) most positive reach of this state,
684 2) most negative reach of this state,
93c2a809 685 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 686 4) which index into the table to try if we can't fit into this one. */
252b5132 687
fddf5b5b 688 /* UNCOND_JUMP states. */
93c2a809
AM		 689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
252b5132 693 {0, 0, 4, 0},
93c2a809
AM		 694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 696 {0, 0, 2, 0},
697
93c2a809
AM		 698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
703 {0, 0, 5, 0},
fddf5b5b 704 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 705 1 extra opcode byte, 2 displacement bytes. */
706 {0, 0, 3, 0},
707
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
713 {0, 0, 5, 0},
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
716 {0, 0, 4, 0}
252b5132
RH		 717};
718
9103f4f4
L		 719static const arch_entry cpu_arch[] =
720{
89507696
JB		 721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
8a2c8fef 723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 724 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 726 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 728 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 730 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 732 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 734 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 736 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 738 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 740 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 742 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 744 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 748 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 750 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 752 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 754 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 756 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 760 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 762 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 764 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 766 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
768 CPU_K1OM_FLAGS, 0, 0 },
81486035
L		 769 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
770 CPU_IAMCU_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 772 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 774 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 776 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 778 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 780 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 782 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 784 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 785 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 786 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 787 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 788 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 789 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
790 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 791 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
792 CPU_BDVER4_FLAGS, 0, 0 },
029f3522 793 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
3739860c 794 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 795 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
796 CPU_BTVER1_FLAGS, 0, 0 },
797 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
798 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 800 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 802 CPU_287_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 804 CPU_387_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 806 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 807 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 808 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 810 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 811 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 812 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 813 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 814 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 816 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 817 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 824 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 826 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 827 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 829 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
830 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 831 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
832 CPU_AVX512F_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
834 CPU_AVX512CD_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
836 CPU_AVX512ER_FLAGS, 0, 0 },
837 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
838 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 839 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
840 CPU_AVX512DQ_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
842 CPU_AVX512BW_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
844 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 846 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 847 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 848 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 849 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
850 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 852 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 855 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 856 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 857 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
858 CPU_XSAVEC_FLAGS, 0, 0 },
859 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
860 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 862 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 864 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 866 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 867 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 868 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 869 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 870 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 871 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 872 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 873 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
874 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 876 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 878 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 880 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 882 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 884 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 885 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
886 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 888 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 889 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
890 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 891 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
892 CPU_HLE_FLAGS, 0, 0 },
893 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
894 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 895 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
896 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 898 CPU_CLFLUSH_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
900 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 902 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 904 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 906 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 908 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 910 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 912 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 914 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 916 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 917 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 918 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 919 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
920 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 921 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
922 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 923 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
924 CPU_ADX_FLAGS, 0, 0 },
925 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
926 CPU_RDSEED_FLAGS, 0, 0 },
927 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
928 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 929 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
930 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 931 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
932 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 933 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
934 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 935 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
936 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 937 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
938 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 939 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
940 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 941 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
942 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 943 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
944 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 945 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
946 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 947 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
948 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 949 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
950 CPU_CLZERO_FLAGS, 0, 0 },
9916071f
AP		 951 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
952 CPU_MWAITX_FLAGS, 0, 0 },
e413e4e9
AM		 953};
954
704209c0 955#ifdef I386COFF
a6c24e68
NC		 956/* Like s_lcomm_internal in gas/read.c but the alignment string
957 is allowed to be optional. */
958
959static symbolS *
960pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
961{
962 addressT align = 0;
963
964 SKIP_WHITESPACE ();
965
7ab9ffdd 966 if (needs_align
a6c24e68
NC		 967 && *input_line_pointer == ',')
968 {
969 align = parse_align (needs_align - 1);
7ab9ffdd 970
a6c24e68
NC		 971 if (align == (addressT) -1)
972 return NULL;
973 }
974 else
975 {
976 if (size >= 8)
977 align = 3;
978 else if (size >= 4)
979 align = 2;
980 else if (size >= 2)
981 align = 1;
982 else
983 align = 0;
984 }
985
986 bss_alloc (symbolP, size, align);
987 return symbolP;
988}
989
704209c0 990static void
a6c24e68
NC		 991pe_lcomm (int needs_align)
992{
993 s_comm_internal (needs_align * 2, pe_lcomm_internal);
994}
704209c0 995#endif
a6c24e68 996
29b0f896
AM		 997const pseudo_typeS md_pseudo_table[] =
998{
999#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1000 {"align", s_align_bytes, 0},
1001#else
1002 {"align", s_align_ptwo, 0},
1003#endif
1004 {"arch", set_cpu_arch, 0},
1005#ifndef I386COFF
1006 {"bss", s_bss, 0},
a6c24e68
NC		 1007#else
1008 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1009#endif
1010 {"ffloat", float_cons, 'f'},
1011 {"dfloat", float_cons, 'd'},
1012 {"tfloat", float_cons, 'x'},
1013 {"value", cons, 2},
d182319b 1014 {"slong", signed_cons, 4},
29b0f896
AM		 1015 {"noopt", s_ignore, 0},
1016 {"optim", s_ignore, 0},
1017 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1018 {"code16", set_code_flag, CODE_16BIT},
1019 {"code32", set_code_flag, CODE_32BIT},
1020 {"code64", set_code_flag, CODE_64BIT},
1021 {"intel_syntax", set_intel_syntax, 1},
1022 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1023 {"intel_mnemonic", set_intel_mnemonic, 1},
1024 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1025 {"allow_index_reg", set_allow_index_reg, 1},
1026 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1027 {"sse_check", set_check, 0},
1028 {"operand_check", set_check, 1},
3b22753a
L		 1029#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1030 {"largecomm", handle_large_common, 0},
07a53e5c 1031#else
e3bb37b5 1032 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1033 {"loc", dwarf2_directive_loc, 0},
1034 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1035#endif
6482c264
NC		 1036#ifdef TE_PE
1037 {"secrel32", pe_directive_secrel, 0},
1038#endif
29b0f896
AM		 1039 {0, 0, 0}
1040};
1041
1042/* For interface with expression (). */
1043extern char *input_line_pointer;
1044
1045/* Hash table for instruction mnemonic lookup. */
1046static struct hash_control *op_hash;
1047
1048/* Hash table for register lookup. */
1049static struct hash_control *reg_hash;
1050\f
252b5132 1051void
e3bb37b5 1052i386_align_code (fragS *fragP, int count)
252b5132 1053{
ce8a8b2f
AM		 1054 /* Various efficient no-op patterns for aligning code labels.
1055 Note: Don't try to assemble the instructions in the comments.
1056 0L and 0w are not legal. */
252b5132
RH		 1057 static const char f32_1[] =
1058 {0x90}; /* nop */
1059 static const char f32_2[] =
ccc9c027 1060 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1061 static const char f32_3[] =
1062 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1063 static const char f32_4[] =
1064 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1065 static const char f32_5[] =
1066 {0x90, /* nop */
1067 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1068 static const char f32_6[] =
1069 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1070 static const char f32_7[] =
1071 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1072 static const char f32_8[] =
1073 {0x90, /* nop */
1074 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1075 static const char f32_9[] =
1076 {0x89,0xf6, /* movl %esi,%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f32_10[] =
1079 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1081 static const char f32_11[] =
1082 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_12[] =
1085 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1086 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1087 static const char f32_13[] =
1088 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_14[] =
1091 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1092 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1093 static const char f16_3[] =
1094 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1095 static const char f16_4[] =
1096 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1097 static const char f16_5[] =
1098 {0x90, /* nop */
1099 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1100 static const char f16_6[] =
1101 {0x89,0xf6, /* mov %si,%si */
1102 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1103 static const char f16_7[] =
1104 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1105 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1106 static const char f16_8[] =
1107 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1109 static const char jump_31[] =
1110 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1111 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1112 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1113 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1114 static const char *const f32_patt[] = {
1115 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1116 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1117 };
1118 static const char *const f16_patt[] = {
76bc74dc 1119 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1120 };
ccc9c027
L		 1121 /* nopl (%[re]ax) */
1122 static const char alt_3[] =
1123 {0x0f,0x1f,0x00};
1124 /* nopl 0(%[re]ax) */
1125 static const char alt_4[] =
1126 {0x0f,0x1f,0x40,0x00};
1127 /* nopl 0(%[re]ax,%[re]ax,1) */
1128 static const char alt_5[] =
1129 {0x0f,0x1f,0x44,0x00,0x00};
1130 /* nopw 0(%[re]ax,%[re]ax,1) */
1131 static const char alt_6[] =
1132 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1133 /* nopl 0L(%[re]ax) */
1134 static const char alt_7[] =
1135 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1136 /* nopl 0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_8[] =
1138 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 /* nopw 0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_9[] =
1141 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_10[] =
1144 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1145 static const char *const alt_patt[] = {
ccc9c027 1146 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1147 alt_9, alt_10
ccc9c027 1148 };
252b5132 1149
76bc74dc
L		 1150 /* Only align for at least a positive non-zero boundary. */
1151 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1152 return;
3e73aa7c 1153
ccc9c027
L		 1154 /* We need to decide which NOP sequence to use for 32bit and
1155 64bit. When -mtune= is used:
4eed87de 1156
76bc74dc
L		 1157 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1158 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1159 2. For the rest, alt_patt will be used.
1160
1161 When -mtune= isn't used, alt_patt will be used if
22109423 1162 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1163 be used.
ccc9c027
L		 1164
1165 When -march= or .arch is used, we can't use anything beyond
1166 cpu_arch_isa_flags. */
1167
1168 if (flag_code == CODE_16BIT)
1169 {
ccc9c027 1170 if (count > 8)
33fef721 1171 {
76bc74dc
L		 1172 memcpy (fragP->fr_literal + fragP->fr_fix,
1173 jump_31, count);
1174 /* Adjust jump offset. */
1175 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1176 }
76bc74dc
L		 1177 else
1178 memcpy (fragP->fr_literal + fragP->fr_fix,
1179 f16_patt[count - 1], count);
252b5132 1180 }
33fef721 1181 else
ccc9c027
L		 1182 {
1183 const char *const *patt = NULL;
1184
fbf3f584 1185 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1186 {
1187 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1188 switch (cpu_arch_tune)
1189 {
1190 case PROCESSOR_UNKNOWN:
1191 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1192 optimize with nops. */
1193 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1194 patt = alt_patt;
ccc9c027
L		 1195 else
1196 patt = f32_patt;
1197 break;
ccc9c027
L		 1198 case PROCESSOR_PENTIUM4:
1199 case PROCESSOR_NOCONA:
ef05d495 1200 case PROCESSOR_CORE:
76bc74dc 1201 case PROCESSOR_CORE2:
bd5295b2 1202 case PROCESSOR_COREI7:
3632d14b 1203 case PROCESSOR_L1OM:
7a9068fe 1204 case PROCESSOR_K1OM:
76bc74dc 1205 case PROCESSOR_GENERIC64:
ccc9c027
L		 1206 case PROCESSOR_K6:
1207 case PROCESSOR_ATHLON:
1208 case PROCESSOR_K8:
4eed87de 1209 case PROCESSOR_AMDFAM10:
8aedb9fe 1210 case PROCESSOR_BD:
029f3522 1211 case PROCESSOR_ZNVER:
7b458c12 1212 case PROCESSOR_BT:
80b8656c 1213 patt = alt_patt;
ccc9c027 1214 break;
76bc74dc 1215 case PROCESSOR_I386:
ccc9c027
L		 1216 case PROCESSOR_I486:
1217 case PROCESSOR_PENTIUM:
2dde1948 1218 case PROCESSOR_PENTIUMPRO:
81486035 1219 case PROCESSOR_IAMCU:
ccc9c027
L		 1220 case PROCESSOR_GENERIC32:
1221 patt = f32_patt;
1222 break;
4eed87de 1223 }
ccc9c027
L		 1224 }
1225 else
1226 {
fbf3f584 1227 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1228 {
1229 case PROCESSOR_UNKNOWN:
e6a14101 1230 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1231 PROCESSOR_UNKNOWN. */
1232 abort ();
1233 break;
1234
76bc74dc 1235 case PROCESSOR_I386:
ccc9c027
L		 1236 case PROCESSOR_I486:
1237 case PROCESSOR_PENTIUM:
81486035 1238 case PROCESSOR_IAMCU:
ccc9c027
L		 1239 case PROCESSOR_K6:
1240 case PROCESSOR_ATHLON:
1241 case PROCESSOR_K8:
4eed87de 1242 case PROCESSOR_AMDFAM10:
8aedb9fe 1243 case PROCESSOR_BD:
029f3522 1244 case PROCESSOR_ZNVER:
7b458c12 1245 case PROCESSOR_BT:
ccc9c027
L		 1246 case PROCESSOR_GENERIC32:
1247 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1248 with nops. */
1249 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1250 patt = alt_patt;
ccc9c027
L		 1251 else
1252 patt = f32_patt;
1253 break;
76bc74dc
L		 1254 case PROCESSOR_PENTIUMPRO:
1255 case PROCESSOR_PENTIUM4:
1256 case PROCESSOR_NOCONA:
1257 case PROCESSOR_CORE:
ef05d495 1258 case PROCESSOR_CORE2:
bd5295b2 1259 case PROCESSOR_COREI7:
3632d14b 1260 case PROCESSOR_L1OM:
7a9068fe 1261 case PROCESSOR_K1OM:
22109423 1262 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1263 patt = alt_patt;
ccc9c027
L		 1264 else
1265 patt = f32_patt;
1266 break;
1267 case PROCESSOR_GENERIC64:
80b8656c 1268 patt = alt_patt;
ccc9c027 1269 break;
4eed87de 1270 }
ccc9c027
L		 1271 }
1272
76bc74dc
L		 1273 if (patt == f32_patt)
1274 {
1275 /* If the padding is less than 15 bytes, we use the normal
1276 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1277 its offset. */
1278 int limit;
76ba9986 1279
711eedef
L		 1280 /* For 64bit, the limit is 3 bytes. */
1281 if (flag_code == CODE_64BIT
1282 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1283 limit = 3;
1284 else
1285 limit = 15;
1286 if (count < limit)
76bc74dc
L		 1287 memcpy (fragP->fr_literal + fragP->fr_fix,
1288 patt[count - 1], count);
1289 else
1290 {
1291 memcpy (fragP->fr_literal + fragP->fr_fix,
1292 jump_31, count);
1293 /* Adjust jump offset. */
1294 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1295 }
1296 }
1297 else
1298 {
80b8656c
L		 1299 /* Maximum length of an instruction is 10 byte. If the
1300 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1301 we have to break it into smaller pieces. */
1302 int padding = count;
80b8656c 1303 while (padding > 10)
76bc74dc 1304 {
80b8656c 1305 padding -= 10;
76bc74dc 1306 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1307 patt [9], 10);
76bc74dc
L		 1308 }
1309
1310 if (padding)
1311 memcpy (fragP->fr_literal + fragP->fr_fix,
1312 patt [padding - 1], padding);
1313 }
ccc9c027 1314 }
33fef721 1315 fragP->fr_var = count;
252b5132
RH		 1316}
1317
c6fb90c8 1318static INLINE int
0dfbf9d7 1319operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1320{
0dfbf9d7 1321 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1322 {
1323 case 3:
0dfbf9d7 1324 if (x->array[2])
c6fb90c8
L		 1325 return 0;
1326 case 2:
0dfbf9d7 1327 if (x->array[1])
c6fb90c8
L		 1328 return 0;
1329 case 1:
0dfbf9d7 1330 return !x->array[0];
c6fb90c8
L		 1331 default:
1332 abort ();
1333 }
40fb9820
L		 1334}
1335
c6fb90c8 1336static INLINE void
0dfbf9d7 1337operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1338{
0dfbf9d7 1339 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1340 {
1341 case 3:
0dfbf9d7 1342 x->array[2] = v;
c6fb90c8 1343 case 2:
0dfbf9d7 1344 x->array[1] = v;
c6fb90c8 1345 case 1:
0dfbf9d7 1346 x->array[0] = v;
c6fb90c8
L		 1347 break;
1348 default:
1349 abort ();
1350 }
1351}
40fb9820 1352
c6fb90c8 1353static INLINE int
0dfbf9d7
L		 1354operand_type_equal (const union i386_operand_type *x,
1355 const union i386_operand_type *y)
c6fb90c8 1356{
0dfbf9d7 1357 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1358 {
1359 case 3:
0dfbf9d7 1360 if (x->array[2] != y->array[2])
c6fb90c8
L		 1361 return 0;
1362 case 2:
0dfbf9d7 1363 if (x->array[1] != y->array[1])
c6fb90c8
L		 1364 return 0;
1365 case 1:
0dfbf9d7 1366 return x->array[0] == y->array[0];
c6fb90c8
L		 1367 break;
1368 default:
1369 abort ();
1370 }
1371}
40fb9820 1372
0dfbf9d7
L		 1373static INLINE int
1374cpu_flags_all_zero (const union i386_cpu_flags *x)
1375{
1376 switch (ARRAY_SIZE(x->array))
1377 {
1378 case 3:
1379 if (x->array[2])
1380 return 0;
1381 case 2:
1382 if (x->array[1])
1383 return 0;
1384 case 1:
1385 return !x->array[0];
1386 default:
1387 abort ();
1388 }
1389}
1390
0dfbf9d7
L		 1391static INLINE int
1392cpu_flags_equal (const union i386_cpu_flags *x,
1393 const union i386_cpu_flags *y)
1394{
1395 switch (ARRAY_SIZE(x->array))
1396 {
1397 case 3:
1398 if (x->array[2] != y->array[2])
1399 return 0;
1400 case 2:
1401 if (x->array[1] != y->array[1])
1402 return 0;
1403 case 1:
1404 return x->array[0] == y->array[0];
1405 break;
1406 default:
1407 abort ();
1408 }
1409}
c6fb90c8
L		 1410
1411static INLINE int
1412cpu_flags_check_cpu64 (i386_cpu_flags f)
1413{
1414 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1415 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1416}
1417
c6fb90c8
L		 1418static INLINE i386_cpu_flags
1419cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1420{
c6fb90c8
L		 1421 switch (ARRAY_SIZE (x.array))
1422 {
1423 case 3:
1424 x.array [2] &= y.array [2];
1425 case 2:
1426 x.array [1] &= y.array [1];
1427 case 1:
1428 x.array [0] &= y.array [0];
1429 break;
1430 default:
1431 abort ();
1432 }
1433 return x;
1434}
40fb9820 1435
c6fb90c8
L		 1436static INLINE i386_cpu_flags
1437cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1438{
c6fb90c8 1439 switch (ARRAY_SIZE (x.array))
40fb9820 1440 {
c6fb90c8
L		 1441 case 3:
1442 x.array [2] |= y.array [2];
1443 case 2:
1444 x.array [1] |= y.array [1];
1445 case 1:
1446 x.array [0] |= y.array [0];
40fb9820
L		 1447 break;
1448 default:
1449 abort ();
1450 }
40fb9820
L		 1451 return x;
1452}
1453
309d3373
JB		 1454static INLINE i386_cpu_flags
1455cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1456{
1457 switch (ARRAY_SIZE (x.array))
1458 {
1459 case 3:
1460 x.array [2] &= ~y.array [2];
1461 case 2:
1462 x.array [1] &= ~y.array [1];
1463 case 1:
1464 x.array [0] &= ~y.array [0];
1465 break;
1466 default:
1467 abort ();
1468 }
1469 return x;
1470}
1471
81486035
L		 1472static int
1473valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1474{
1475 if (cpu_arch_isa == PROCESSOR_IAMCU)
1476 {
1477 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1478 i386_cpu_flags compat_flags;
1479 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1480 return cpu_flags_all_zero (&compat_flags);
1481 }
1482 else
1483 return 1;
1484}
1485
c0f3af97
L		 1486#define CPU_FLAGS_ARCH_MATCH 0x1
1487#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1488#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1489#define CPU_FLAGS_PCLMUL_MATCH 0x8
1490#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1491
a5ff0eb2 1492#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1493 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1494 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1495#define CPU_FLAGS_PERFECT_MATCH \
1496 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1497
1498/* Return CPU flags match bits. */
3629bb00 1499
40fb9820 1500static int
d3ce72d0 1501cpu_flags_match (const insn_template *t)
40fb9820 1502{
c0f3af97
L		 1503 i386_cpu_flags x = t->cpu_flags;
1504 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1505
1506 x.bitfield.cpu64 = 0;
1507 x.bitfield.cpuno64 = 0;
1508
0dfbf9d7 1509 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1510 {
1511 /* This instruction is available on all archs. */
1512 match |= CPU_FLAGS_32BIT_MATCH;
1513 }
3629bb00
L		 1514 else
1515 {
c0f3af97 1516 /* This instruction is available only on some archs. */
3629bb00
L		 1517 i386_cpu_flags cpu = cpu_arch_flags;
1518
1519 cpu.bitfield.cpu64 = 0;
1520 cpu.bitfield.cpuno64 = 0;
1521 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1522 if (!cpu_flags_all_zero (&cpu))
1523 {
a5ff0eb2
L		 1524 if (x.bitfield.cpuavx)
1525 {
ce2f5b3c 1526 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1527 if (cpu.bitfield.cpuavx)
1528 {
1529 /* Check SSE2AVX. */
1530 if (!t->opcode_modifier.sse2avx|| sse2avx)
1531 {
1532 match |= (CPU_FLAGS_ARCH_MATCH
1533 | CPU_FLAGS_AVX_MATCH);
1534 /* Check AES. */
1535 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1536 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1537 /* Check PCLMUL. */
1538 if (!x.bitfield.cpupclmul
1539 || cpu.bitfield.cpupclmul)
1540 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1541 }
1542 }
1543 else
1544 match |= CPU_FLAGS_ARCH_MATCH;
1545 }
1546 else
c0f3af97
L		 1547 match |= CPU_FLAGS_32BIT_MATCH;
1548 }
3629bb00 1549 }
c0f3af97 1550 return match;
40fb9820
L		 1551}
1552
c6fb90c8
L		 1553static INLINE i386_operand_type
1554operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1555{
c6fb90c8
L		 1556 switch (ARRAY_SIZE (x.array))
1557 {
1558 case 3:
1559 x.array [2] &= y.array [2];
1560 case 2:
1561 x.array [1] &= y.array [1];
1562 case 1:
1563 x.array [0] &= y.array [0];
1564 break;
1565 default:
1566 abort ();
1567 }
1568 return x;
40fb9820
L		 1569}
1570
c6fb90c8
L		 1571static INLINE i386_operand_type
1572operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1573{
c6fb90c8 1574 switch (ARRAY_SIZE (x.array))
40fb9820 1575 {
c6fb90c8
L		 1576 case 3:
1577 x.array [2] |= y.array [2];
1578 case 2:
1579 x.array [1] |= y.array [1];
1580 case 1:
1581 x.array [0] |= y.array [0];
40fb9820
L		 1582 break;
1583 default:
1584 abort ();
1585 }
c6fb90c8
L		 1586 return x;
1587}
40fb9820 1588
c6fb90c8
L		 1589static INLINE i386_operand_type
1590operand_type_xor (i386_operand_type x, i386_operand_type y)
1591{
1592 switch (ARRAY_SIZE (x.array))
1593 {
1594 case 3:
1595 x.array [2] ^= y.array [2];
1596 case 2:
1597 x.array [1] ^= y.array [1];
1598 case 1:
1599 x.array [0] ^= y.array [0];
1600 break;
1601 default:
1602 abort ();
1603 }
40fb9820
L		 1604 return x;
1605}
1606
1607static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1608static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1609static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1610static const i386_operand_type inoutportreg
1611 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1612static const i386_operand_type reg16_inoutportreg
1613 = OPERAND_TYPE_REG16_INOUTPORTREG;
1614static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1615static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1616static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1617static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1618static const i386_operand_type anydisp
1619 = OPERAND_TYPE_ANYDISP;
40fb9820 1620static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1621static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1622static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1623static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1624static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1625static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1626static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1627static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1628static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1629static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1630static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1631static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1632static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1633static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1634
1635enum operand_type
1636{
1637 reg,
40fb9820
L		 1638 imm,
1639 disp,
1640 anymem
1641};
1642
c6fb90c8 1643static INLINE int
40fb9820
L		 1644operand_type_check (i386_operand_type t, enum operand_type c)
1645{
1646 switch (c)
1647 {
1648 case reg:
1649 return (t.bitfield.reg8
1650 || t.bitfield.reg16
1651 || t.bitfield.reg32
1652 || t.bitfield.reg64);
1653
40fb9820
L		 1654 case imm:
1655 return (t.bitfield.imm8
1656 || t.bitfield.imm8s
1657 || t.bitfield.imm16
1658 || t.bitfield.imm32
1659 || t.bitfield.imm32s
1660 || t.bitfield.imm64);
1661
1662 case disp:
1663 return (t.bitfield.disp8
1664 || t.bitfield.disp16
1665 || t.bitfield.disp32
1666 || t.bitfield.disp32s
1667 || t.bitfield.disp64);
1668
1669 case anymem:
1670 return (t.bitfield.disp8
1671 || t.bitfield.disp16
1672 || t.bitfield.disp32
1673 || t.bitfield.disp32s
1674 || t.bitfield.disp64
1675 || t.bitfield.baseindex);
1676
1677 default:
1678 abort ();
1679 }
2cfe26b6
AM		 1680
1681 return 0;
40fb9820
L		 1682}
1683
5c07affc
L		 1684/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1685 operand J for instruction template T. */
1686
1687static INLINE int
d3ce72d0 1688match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1689{
1690 return !((i.types[j].bitfield.byte
1691 && !t->operand_types[j].bitfield.byte)
1692 || (i.types[j].bitfield.word
1693 && !t->operand_types[j].bitfield.word)
1694 || (i.types[j].bitfield.dword
1695 && !t->operand_types[j].bitfield.dword)
1696 || (i.types[j].bitfield.qword
1697 && !t->operand_types[j].bitfield.qword));
1698}
1699
1700/* Return 1 if there is no conflict in any size on operand J for
1701 instruction template T. */
1702
1703static INLINE int
d3ce72d0 1704match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1705{
1706 return (match_reg_size (t, j)
1707 && !((i.types[j].bitfield.unspecified
af508cb9 1708 && !i.broadcast
5c07affc
L		 1709 && !t->operand_types[j].bitfield.unspecified)
1710 || (i.types[j].bitfield.fword
1711 && !t->operand_types[j].bitfield.fword)
1712 || (i.types[j].bitfield.tbyte
1713 && !t->operand_types[j].bitfield.tbyte)
1714 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1715 && !t->operand_types[j].bitfield.xmmword)
1716 || (i.types[j].bitfield.ymmword
43234a1e
L		 1717 && !t->operand_types[j].bitfield.ymmword)
1718 || (i.types[j].bitfield.zmmword
1719 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1720}
1721
1722/* Return 1 if there is no size conflict on any operands for
1723 instruction template T. */
1724
1725static INLINE int
d3ce72d0 1726operand_size_match (const insn_template *t)
5c07affc
L		 1727{
1728 unsigned int j;
1729 int match = 1;
1730
1731 /* Don't check jump instructions. */
1732 if (t->opcode_modifier.jump
1733 || t->opcode_modifier.jumpbyte
1734 || t->opcode_modifier.jumpdword
1735 || t->opcode_modifier.jumpintersegment)
1736 return match;
1737
1738 /* Check memory and accumulator operand size. */
1739 for (j = 0; j < i.operands; j++)
1740 {
1741 if (t->operand_types[j].bitfield.anysize)
1742 continue;
1743
1744 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1745 {
1746 match = 0;
1747 break;
1748 }
1749
1750 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1751 {
1752 match = 0;
1753 break;
1754 }
1755 }
1756
891edac4 1757 if (match)
5c07affc 1758 return match;
891edac4
L		 1759 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1760 {
1761mismatch:
86e026a4 1762 i.error = operand_size_mismatch;
891edac4
L		 1763 return 0;
1764 }
5c07affc
L		 1765
1766 /* Check reverse. */
9c2799c2 1767 gas_assert (i.operands == 2);
5c07affc
L		 1768
1769 match = 1;
1770 for (j = 0; j < 2; j++)
1771 {
1772 if (t->operand_types[j].bitfield.acc
1773 && !match_reg_size (t, j ? 0 : 1))
891edac4 1774 goto mismatch;
5c07affc
L		 1775
1776 if (i.types[j].bitfield.mem
1777 && !match_mem_size (t, j ? 0 : 1))
891edac4 1778 goto mismatch;
5c07affc
L		 1779 }
1780
1781 return match;
1782}
1783
c6fb90c8 1784static INLINE int
40fb9820
L		 1785operand_type_match (i386_operand_type overlap,
1786 i386_operand_type given)
1787{
1788 i386_operand_type temp = overlap;
1789
1790 temp.bitfield.jumpabsolute = 0;
7d5e4556 1791 temp.bitfield.unspecified = 0;
5c07affc
L		 1792 temp.bitfield.byte = 0;
1793 temp.bitfield.word = 0;
1794 temp.bitfield.dword = 0;
1795 temp.bitfield.fword = 0;
1796 temp.bitfield.qword = 0;
1797 temp.bitfield.tbyte = 0;
1798 temp.bitfield.xmmword = 0;
c0f3af97 1799 temp.bitfield.ymmword = 0;
43234a1e 1800 temp.bitfield.zmmword = 0;
0dfbf9d7 1801 if (operand_type_all_zero (&temp))
891edac4 1802 goto mismatch;
40fb9820 1803
891edac4
L		 1804 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1805 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1806 return 1;
1807
1808mismatch:
a65babc9 1809 i.error = operand_type_mismatch;
891edac4 1810 return 0;
40fb9820
L		 1811}
1812
7d5e4556 1813/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1814 unless the expected operand type register overlap is null.
1815 Note that Acc in a template matches every size of reg. */
1816
c6fb90c8 1817static INLINE int
40fb9820
L		 1818operand_type_register_match (i386_operand_type m0,
1819 i386_operand_type g0,
1820 i386_operand_type t0,
1821 i386_operand_type m1,
1822 i386_operand_type g1,
1823 i386_operand_type t1)
1824{
1825 if (!operand_type_check (g0, reg))
1826 return 1;
1827
1828 if (!operand_type_check (g1, reg))
1829 return 1;
1830
1831 if (g0.bitfield.reg8 == g1.bitfield.reg8
1832 && g0.bitfield.reg16 == g1.bitfield.reg16
1833 && g0.bitfield.reg32 == g1.bitfield.reg32
1834 && g0.bitfield.reg64 == g1.bitfield.reg64)
1835 return 1;
1836
1837 if (m0.bitfield.acc)
1838 {
1839 t0.bitfield.reg8 = 1;
1840 t0.bitfield.reg16 = 1;
1841 t0.bitfield.reg32 = 1;
1842 t0.bitfield.reg64 = 1;
1843 }
1844
1845 if (m1.bitfield.acc)
1846 {
1847 t1.bitfield.reg8 = 1;
1848 t1.bitfield.reg16 = 1;
1849 t1.bitfield.reg32 = 1;
1850 t1.bitfield.reg64 = 1;
1851 }
1852
891edac4
L		 1853 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1854 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1855 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1856 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1857 return 1;
1858
a65babc9 1859 i.error = register_type_mismatch;
891edac4
L		 1860
1861 return 0;
40fb9820
L		 1862}
1863
4c692bc7
JB		 1864static INLINE unsigned int
1865register_number (const reg_entry *r)
1866{
1867 unsigned int nr = r->reg_num;
1868
1869 if (r->reg_flags & RegRex)
1870 nr += 8;
1871
1872 return nr;
1873}
1874
252b5132 1875static INLINE unsigned int
40fb9820 1876mode_from_disp_size (i386_operand_type t)
252b5132 1877{
43234a1e 1878 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1879 return 1;
1880 else if (t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s)
1883 return 2;
1884 else
1885 return 0;
252b5132
RH		 1886}
1887
1888static INLINE int
65879393 1889fits_in_signed_byte (addressT num)
252b5132 1890{
65879393 1891 return num + 0x80 <= 0xff;
47926f60 1892}
252b5132
RH		 1893
1894static INLINE int
65879393 1895fits_in_unsigned_byte (addressT num)
252b5132 1896{
65879393 1897 return num <= 0xff;
47926f60 1898}
252b5132
RH		 1899
1900static INLINE int
65879393 1901fits_in_unsigned_word (addressT num)
252b5132 1902{
65879393 1903 return num <= 0xffff;
47926f60 1904}
252b5132
RH		 1905
1906static INLINE int
65879393 1907fits_in_signed_word (addressT num)
252b5132 1908{
65879393 1909 return num + 0x8000 <= 0xffff;
47926f60 1910}
2a962e6d 1911
3e73aa7c 1912static INLINE int
65879393 1913fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1914{
1915#ifndef BFD64
1916 return 1;
1917#else
65879393 1918 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1919#endif
1920} /* fits_in_signed_long() */
2a962e6d 1921
3e73aa7c 1922static INLINE int
65879393 1923fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1924{
1925#ifndef BFD64
1926 return 1;
1927#else
65879393 1928 return num <= 0xffffffff;
3e73aa7c
JH		 1929#endif
1930} /* fits_in_unsigned_long() */
252b5132 1931
43234a1e
L		 1932static INLINE int
1933fits_in_vec_disp8 (offsetT num)
1934{
1935 int shift = i.memshift;
1936 unsigned int mask;
1937
1938 if (shift == -1)
1939 abort ();
1940
1941 mask = (1 << shift) - 1;
1942
1943 /* Return 0 if NUM isn't properly aligned. */
1944 if ((num & mask))
1945 return 0;
1946
1947 /* Check if NUM will fit in 8bit after shift. */
1948 return fits_in_signed_byte (num >> shift);
1949}
1950
a683cc34
SP		 1951static INLINE int
1952fits_in_imm4 (offsetT num)
1953{
1954 return (num & 0xf) == num;
1955}
1956
40fb9820 1957static i386_operand_type
e3bb37b5 1958smallest_imm_type (offsetT num)
252b5132 1959{
40fb9820 1960 i386_operand_type t;
7ab9ffdd 1961
0dfbf9d7 1962 operand_type_set (&t, 0);
40fb9820
L		 1963 t.bitfield.imm64 = 1;
1964
1965 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1966 {
1967 /* This code is disabled on the 486 because all the Imm1 forms
1968 in the opcode table are slower on the i486. They're the
1969 versions with the implicitly specified single-position
1970 displacement, which has another syntax if you really want to
1971 use that form. */
40fb9820
L		 1972 t.bitfield.imm1 = 1;
1973 t.bitfield.imm8 = 1;
1974 t.bitfield.imm8s = 1;
1975 t.bitfield.imm16 = 1;
1976 t.bitfield.imm32 = 1;
1977 t.bitfield.imm32s = 1;
1978 }
1979 else if (fits_in_signed_byte (num))
1980 {
1981 t.bitfield.imm8 = 1;
1982 t.bitfield.imm8s = 1;
1983 t.bitfield.imm16 = 1;
1984 t.bitfield.imm32 = 1;
1985 t.bitfield.imm32s = 1;
1986 }
1987 else if (fits_in_unsigned_byte (num))
1988 {
1989 t.bitfield.imm8 = 1;
1990 t.bitfield.imm16 = 1;
1991 t.bitfield.imm32 = 1;
1992 t.bitfield.imm32s = 1;
1993 }
1994 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1995 {
1996 t.bitfield.imm16 = 1;
1997 t.bitfield.imm32 = 1;
1998 t.bitfield.imm32s = 1;
1999 }
2000 else if (fits_in_signed_long (num))
2001 {
2002 t.bitfield.imm32 = 1;
2003 t.bitfield.imm32s = 1;
2004 }
2005 else if (fits_in_unsigned_long (num))
2006 t.bitfield.imm32 = 1;
2007
2008 return t;
47926f60 2009}
252b5132 2010
847f7ad4 2011static offsetT
e3bb37b5 2012offset_in_range (offsetT val, int size)
847f7ad4 2013{
508866be 2014 addressT mask;
ba2adb93 2015
847f7ad4
AM		 2016 switch (size)
2017 {
508866be
L		 2018 case 1: mask = ((addressT) 1 << 8) - 1; break;
2019 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2020 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2021#ifdef BFD64
2022 case 8: mask = ((addressT) 2 << 63) - 1; break;
2023#endif
47926f60 2024 default: abort ();
847f7ad4
AM		 2025 }
2026
9de868bf
L		 2027#ifdef BFD64
2028 /* If BFD64, sign extend val for 32bit address mode. */
2029 if (flag_code != CODE_64BIT
2030 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2031 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2032 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2033#endif
ba2adb93 2034
47926f60 2035 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2036 {
2037 char buf1[40], buf2[40];
2038
2039 sprint_value (buf1, val);
2040 sprint_value (buf2, val & mask);
2041 as_warn (_("%s shortened to %s"), buf1, buf2);
2042 }
2043 return val & mask;
2044}
2045
c32fa91d
L		 2046enum PREFIX_GROUP
2047{
2048 PREFIX_EXIST = 0,
2049 PREFIX_LOCK,
2050 PREFIX_REP,
2051 PREFIX_OTHER
2052};
2053
2054/* Returns
2055 a. PREFIX_EXIST if attempting to add a prefix where one from the
2056 same class already exists.
2057 b. PREFIX_LOCK if lock prefix is added.
2058 c. PREFIX_REP if rep/repne prefix is added.
2059 d. PREFIX_OTHER if other prefix is added.
2060 */
2061
2062static enum PREFIX_GROUP
e3bb37b5 2063add_prefix (unsigned int prefix)
252b5132 2064{
c32fa91d 2065 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2066 unsigned int q;
252b5132 2067
29b0f896
AM		 2068 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2069 && flag_code == CODE_64BIT)
b1905489 2070 {
161a04f6
L		 2071 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2072 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2073 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2074 ret = PREFIX_EXIST;
b1905489
JB		 2075 q = REX_PREFIX;
2076 }
3e73aa7c 2077 else
b1905489
JB		 2078 {
2079 switch (prefix)
2080 {
2081 default:
2082 abort ();
2083
2084 case CS_PREFIX_OPCODE:
2085 case DS_PREFIX_OPCODE:
2086 case ES_PREFIX_OPCODE:
2087 case FS_PREFIX_OPCODE:
2088 case GS_PREFIX_OPCODE:
2089 case SS_PREFIX_OPCODE:
2090 q = SEG_PREFIX;
2091 break;
2092
2093 case REPNE_PREFIX_OPCODE:
2094 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2095 q = REP_PREFIX;
2096 ret = PREFIX_REP;
2097 break;
2098
b1905489 2099 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2100 q = LOCK_PREFIX;
2101 ret = PREFIX_LOCK;
b1905489
JB		 2102 break;
2103
2104 case FWAIT_OPCODE:
2105 q = WAIT_PREFIX;
2106 break;
2107
2108 case ADDR_PREFIX_OPCODE:
2109 q = ADDR_PREFIX;
2110 break;
2111
2112 case DATA_PREFIX_OPCODE:
2113 q = DATA_PREFIX;
2114 break;
2115 }
2116 if (i.prefix[q] != 0)
c32fa91d 2117 ret = PREFIX_EXIST;
b1905489 2118 }
252b5132 2119
b1905489 2120 if (ret)
252b5132 2121 {
b1905489
JB		 2122 if (!i.prefix[q])
2123 ++i.prefixes;
2124 i.prefix[q] |= prefix;
252b5132 2125 }
b1905489
JB		 2126 else
2127 as_bad (_("same type of prefix used twice"));
252b5132 2128
252b5132
RH		 2129 return ret;
2130}
2131
2132static void
78f12dd3 2133update_code_flag (int value, int check)
eecb386c 2134{
78f12dd3
L		 2135 PRINTF_LIKE ((*as_error));
2136
1e9cc1c2 2137 flag_code = (enum flag_code) value;
40fb9820
L		 2138 if (flag_code == CODE_64BIT)
2139 {
2140 cpu_arch_flags.bitfield.cpu64 = 1;
2141 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2142 }
2143 else
2144 {
2145 cpu_arch_flags.bitfield.cpu64 = 0;
2146 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2147 }
2148 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2149 {
78f12dd3
L		 2150 if (check)
2151 as_error = as_fatal;
2152 else
2153 as_error = as_bad;
2154 (*as_error) (_("64bit mode not supported on `%s'."),
2155 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2156 }
40fb9820 2157 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2158 {
78f12dd3
L		 2159 if (check)
2160 as_error = as_fatal;
2161 else
2162 as_error = as_bad;
2163 (*as_error) (_("32bit mode not supported on `%s'."),
2164 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2165 }
eecb386c
AM		 2166 stackop_size = '\0';
2167}
2168
78f12dd3
L		 2169static void
2170set_code_flag (int value)
2171{
2172 update_code_flag (value, 0);
2173}
2174
eecb386c 2175static void
e3bb37b5 2176set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2177{
1e9cc1c2 2178 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2179 if (flag_code != CODE_16BIT)
2180 abort ();
2181 cpu_arch_flags.bitfield.cpu64 = 0;
2182 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2183 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2184}
2185
2186static void
e3bb37b5 2187set_intel_syntax (int syntax_flag)
252b5132
RH		 2188{
2189 /* Find out if register prefixing is specified. */
2190 int ask_naked_reg = 0;
2191
2192 SKIP_WHITESPACE ();
29b0f896 2193 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2194 {
d02603dc
NC		 2195 char *string;
2196 int e = get_symbol_name (&string);
252b5132 2197
47926f60 2198 if (strcmp (string, "prefix") == 0)
252b5132 2199 ask_naked_reg = 1;
47926f60 2200 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2201 ask_naked_reg = -1;
2202 else
d0b47220 2203 as_bad (_("bad argument to syntax directive."));
d02603dc 2204 (void) restore_line_pointer (e);
252b5132
RH		 2205 }
2206 demand_empty_rest_of_line ();
c3332e24 2207
252b5132
RH		 2208 intel_syntax = syntax_flag;
2209
2210 if (ask_naked_reg == 0)
f86103b7
AM		 2211 allow_naked_reg = (intel_syntax
2212 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2213 else
2214 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2215
ee86248c 2216 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2217
e4a3b5a4 2218 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2219 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2220 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2221}
2222
1efbbeb4
L		 2223static void
2224set_intel_mnemonic (int mnemonic_flag)
2225{
e1d4d893 2226 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2227}
2228
db51cc60
L		 2229static void
2230set_allow_index_reg (int flag)
2231{
2232 allow_index_reg = flag;
2233}
2234
cb19c032 2235static void
7bab8ab5 2236set_check (int what)
cb19c032 2237{
7bab8ab5
JB		 2238 enum check_kind *kind;
2239 const char *str;
2240
2241 if (what)
2242 {
2243 kind = &operand_check;
2244 str = "operand";
2245 }
2246 else
2247 {
2248 kind = &sse_check;
2249 str = "sse";
2250 }
2251
cb19c032
L		 2252 SKIP_WHITESPACE ();
2253
2254 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2255 {
d02603dc
NC		 2256 char *string;
2257 int e = get_symbol_name (&string);
cb19c032
L		 2258
2259 if (strcmp (string, "none") == 0)
7bab8ab5 2260 *kind = check_none;
cb19c032 2261 else if (strcmp (string, "warning") == 0)
7bab8ab5 2262 *kind = check_warning;
cb19c032 2263 else if (strcmp (string, "error") == 0)
7bab8ab5 2264 *kind = check_error;
cb19c032 2265 else
7bab8ab5 2266 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2267 (void) restore_line_pointer (e);
cb19c032
L		 2268 }
2269 else
7bab8ab5 2270 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2271
2272 demand_empty_rest_of_line ();
2273}
2274
8a9036a4
L		 2275static void
2276check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2277 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2278{
2279#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2280 static const char *arch;
2281
2282 /* Intel LIOM is only supported on ELF. */
2283 if (!IS_ELF)
2284 return;
2285
2286 if (!arch)
2287 {
2288 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2289 use default_arch. */
2290 arch = cpu_arch_name;
2291 if (!arch)
2292 arch = default_arch;
2293 }
2294
81486035
L		 2295 /* If we are targeting Intel MCU, we must enable it. */
2296 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2297 || new_flag.bitfield.cpuiamcu)
2298 return;
2299
3632d14b 2300 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2301 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2302 || new_flag.bitfield.cpul1om)
8a9036a4 2303 return;
76ba9986 2304
7a9068fe
L		 2305 /* If we are targeting Intel K1OM, we must enable it. */
2306 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2307 || new_flag.bitfield.cpuk1om)
2308 return;
2309
8a9036a4
L		 2310 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2311#endif
2312}
2313
e413e4e9 2314static void
e3bb37b5 2315set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2316{
47926f60 2317 SKIP_WHITESPACE ();
e413e4e9 2318
29b0f896 2319 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2320 {
d02603dc
NC		 2321 char *string;
2322 int e = get_symbol_name (&string);
91d6fa6a 2323 unsigned int j;
40fb9820 2324 i386_cpu_flags flags;
e413e4e9 2325
91d6fa6a 2326 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2327 {
91d6fa6a 2328 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2329 {
91d6fa6a 2330 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2331
5c6af06e
JB		 2332 if (*string != '.')
2333 {
91d6fa6a 2334 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2335 cpu_sub_arch_name = NULL;
91d6fa6a 2336 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2337 if (flag_code == CODE_64BIT)
2338 {
2339 cpu_arch_flags.bitfield.cpu64 = 1;
2340 cpu_arch_flags.bitfield.cpuno64 = 0;
2341 }
2342 else
2343 {
2344 cpu_arch_flags.bitfield.cpu64 = 0;
2345 cpu_arch_flags.bitfield.cpuno64 = 1;
2346 }
91d6fa6a
NC		 2347 cpu_arch_isa = cpu_arch[j].type;
2348 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2349 if (!cpu_arch_tune_set)
2350 {
2351 cpu_arch_tune = cpu_arch_isa;
2352 cpu_arch_tune_flags = cpu_arch_isa_flags;
2353 }
5c6af06e
JB		 2354 break;
2355 }
40fb9820 2356
22109423 2357 if (!cpu_arch[j].negated)
309d3373 2358 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2359 cpu_arch[j].flags);
309d3373
JB		 2360 else
2361 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2362 cpu_arch[j].flags);
81486035
L		 2363
2364 if (!valid_iamcu_cpu_flags (&flags))
2365 as_fatal (_("`%s' isn't valid for Intel MCU"),
2366 cpu_arch[j].name);
2367 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2368 {
6305a203
L		 2369 if (cpu_sub_arch_name)
2370 {
2371 char *name = cpu_sub_arch_name;
2372 cpu_sub_arch_name = concat (name,
91d6fa6a 2373 cpu_arch[j].name,
1bf57e9f 2374 (const char *) NULL);
6305a203
L		 2375 free (name);
2376 }
2377 else
91d6fa6a 2378 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2379 cpu_arch_flags = flags;
a586129e 2380 cpu_arch_isa_flags = flags;
5c6af06e 2381 }
d02603dc 2382 (void) restore_line_pointer (e);
5c6af06e
JB		 2383 demand_empty_rest_of_line ();
2384 return;
e413e4e9
AM		 2385 }
2386 }
91d6fa6a 2387 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2388 as_bad (_("no such architecture: `%s'"), string);
2389
2390 *input_line_pointer = e;
2391 }
2392 else
2393 as_bad (_("missing cpu architecture"));
2394
fddf5b5b
AM		 2395 no_cond_jump_promotion = 0;
2396 if (*input_line_pointer == ','
29b0f896 2397 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2398 {
d02603dc
NC		 2399 char *string;
2400 char e;
2401
2402 ++input_line_pointer;
2403 e = get_symbol_name (&string);
fddf5b5b
AM		 2404
2405 if (strcmp (string, "nojumps") == 0)
2406 no_cond_jump_promotion = 1;
2407 else if (strcmp (string, "jumps") == 0)
2408 ;
2409 else
2410 as_bad (_("no such architecture modifier: `%s'"), string);
2411
d02603dc 2412 (void) restore_line_pointer (e);
fddf5b5b
AM		 2413 }
2414
e413e4e9
AM		 2415 demand_empty_rest_of_line ();
2416}
2417
8a9036a4
L		 2418enum bfd_architecture
2419i386_arch (void)
2420{
3632d14b 2421 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2422 {
2423 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2424 || flag_code != CODE_64BIT)
2425 as_fatal (_("Intel L1OM is 64bit ELF only"));
2426 return bfd_arch_l1om;
2427 }
7a9068fe
L		 2428 else if (cpu_arch_isa == PROCESSOR_K1OM)
2429 {
2430 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2431 || flag_code != CODE_64BIT)
2432 as_fatal (_("Intel K1OM is 64bit ELF only"));
2433 return bfd_arch_k1om;
2434 }
81486035
L		 2435 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2436 {
2437 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2438 || flag_code == CODE_64BIT)
2439 as_fatal (_("Intel MCU is 32bit ELF only"));
2440 return bfd_arch_iamcu;
2441 }
8a9036a4
L		 2442 else
2443 return bfd_arch_i386;
2444}
2445
b9d79e03 2446unsigned long
7016a5d5 2447i386_mach (void)
b9d79e03 2448{
351f65ca 2449 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2450 {
3632d14b 2451 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2452 {
351f65ca
L		 2453 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2454 || default_arch[6] != '\0')
8a9036a4
L		 2455 as_fatal (_("Intel L1OM is 64bit ELF only"));
2456 return bfd_mach_l1om;
2457 }
7a9068fe
L		 2458 else if (cpu_arch_isa == PROCESSOR_K1OM)
2459 {
2460 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2461 || default_arch[6] != '\0')
2462 as_fatal (_("Intel K1OM is 64bit ELF only"));
2463 return bfd_mach_k1om;
2464 }
351f65ca 2465 else if (default_arch[6] == '\0')
8a9036a4 2466 return bfd_mach_x86_64;
351f65ca
L		 2467 else
2468 return bfd_mach_x64_32;
8a9036a4 2469 }
5197d474
L		 2470 else if (!strcmp (default_arch, "i386")
2471 || !strcmp (default_arch, "iamcu"))
81486035
L		 2472 {
2473 if (cpu_arch_isa == PROCESSOR_IAMCU)
2474 {
2475 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2476 as_fatal (_("Intel MCU is 32bit ELF only"));
2477 return bfd_mach_i386_iamcu;
2478 }
2479 else
2480 return bfd_mach_i386_i386;
2481 }
b9d79e03 2482 else
2b5d6a91 2483 as_fatal (_("unknown architecture"));
b9d79e03 2484}
b9d79e03 2485\f
252b5132 2486void
7016a5d5 2487md_begin (void)
252b5132
RH		 2488{
2489 const char *hash_err;
2490
47926f60 2491 /* Initialize op_hash hash table. */
252b5132
RH		 2492 op_hash = hash_new ();
2493
2494 {
d3ce72d0 2495 const insn_template *optab;
29b0f896 2496 templates *core_optab;
252b5132 2497
47926f60
KH		 2498 /* Setup for loop. */
2499 optab = i386_optab;
252b5132
RH		 2500 core_optab = (templates *) xmalloc (sizeof (templates));
2501 core_optab->start = optab;
2502
2503 while (1)
2504 {
2505 ++optab;
2506 if (optab->name == NULL
2507 || strcmp (optab->name, (optab - 1)->name) != 0)
2508 {
2509 /* different name --> ship out current template list;
47926f60 2510 add to hash table; & begin anew. */
252b5132
RH		 2511 core_optab->end = optab;
2512 hash_err = hash_insert (op_hash,
2513 (optab - 1)->name,
5a49b8ac 2514 (void *) core_optab);
252b5132
RH		 2515 if (hash_err)
2516 {
b37df7c4 2517 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2518 (optab - 1)->name,
2519 hash_err);
2520 }
2521 if (optab->name == NULL)
2522 break;
2523 core_optab = (templates *) xmalloc (sizeof (templates));
2524 core_optab->start = optab;
2525 }
2526 }
2527 }
2528
47926f60 2529 /* Initialize reg_hash hash table. */
252b5132
RH		 2530 reg_hash = hash_new ();
2531 {
29b0f896 2532 const reg_entry *regtab;
c3fe08fa 2533 unsigned int regtab_size = i386_regtab_size;
252b5132 2534
c3fe08fa 2535 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2536 {
5a49b8ac 2537 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2538 if (hash_err)
b37df7c4 2539 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2540 regtab->reg_name,
2541 hash_err);
252b5132
RH		 2542 }
2543 }
2544
47926f60 2545 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2546 {
29b0f896
AM		 2547 int c;
2548 char *p;
252b5132
RH		 2549
2550 for (c = 0; c < 256; c++)
2551 {
3882b010 2552 if (ISDIGIT (c))
252b5132
RH		 2553 {
2554 digit_chars[c] = c;
2555 mnemonic_chars[c] = c;
2556 register_chars[c] = c;
2557 operand_chars[c] = c;
2558 }
3882b010 2559 else if (ISLOWER (c))
252b5132
RH		 2560 {
2561 mnemonic_chars[c] = c;
2562 register_chars[c] = c;
2563 operand_chars[c] = c;
2564 }
3882b010 2565 else if (ISUPPER (c))
252b5132 2566 {
3882b010 2567 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2568 register_chars[c] = mnemonic_chars[c];
2569 operand_chars[c] = c;
2570 }
43234a1e
L		 2571 else if (c == '{' || c == '}')
2572 operand_chars[c] = c;
252b5132 2573
3882b010 2574 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2575 identifier_chars[c] = c;
2576 else if (c >= 128)
2577 {
2578 identifier_chars[c] = c;
2579 operand_chars[c] = c;
2580 }
2581 }
2582
2583#ifdef LEX_AT
2584 identifier_chars['@'] = '@';
32137342
NC		 2585#endif
2586#ifdef LEX_QM
2587 identifier_chars['?'] = '?';
2588 operand_chars['?'] = '?';
252b5132 2589#endif
252b5132 2590 digit_chars['-'] = '-';
c0f3af97 2591 mnemonic_chars['_'] = '_';
791fe849 2592 mnemonic_chars['-'] = '-';
0003779b 2593 mnemonic_chars['.'] = '.';
252b5132
RH		 2594 identifier_chars['_'] = '_';
2595 identifier_chars['.'] = '.';
2596
2597 for (p = operand_special_chars; *p != '\0'; p++)
2598 operand_chars[(unsigned char) *p] = *p;
2599 }
2600
a4447b93
RH		 2601 if (flag_code == CODE_64BIT)
2602 {
ca19b261
KT		 2603#if defined (OBJ_COFF) && defined (TE_PE)
2604 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2605 ? 32 : 16);
2606#else
a4447b93 2607 x86_dwarf2_return_column = 16;
ca19b261 2608#endif
61ff971f 2609 x86_cie_data_alignment = -8;
a4447b93
RH		 2610 }
2611 else
2612 {
2613 x86_dwarf2_return_column = 8;
2614 x86_cie_data_alignment = -4;
2615 }
252b5132
RH		 2616}
2617
2618void
e3bb37b5 2619i386_print_statistics (FILE *file)
252b5132
RH		 2620{
2621 hash_print_statistics (file, "i386 opcode", op_hash);
2622 hash_print_statistics (file, "i386 register", reg_hash);
2623}
2624\f
252b5132
RH		 2625#ifdef DEBUG386
2626
ce8a8b2f 2627/* Debugging routines for md_assemble. */
d3ce72d0 2628static void pte (insn_template *);
40fb9820 2629static void pt (i386_operand_type);
e3bb37b5
L		 2630static void pe (expressionS *);
2631static void ps (symbolS *);
252b5132
RH		 2632
2633static void
e3bb37b5 2634pi (char *line, i386_insn *x)
252b5132 2635{
09137c09 2636 unsigned int j;
252b5132
RH		 2637
2638 fprintf (stdout, "%s: template ", line);
2639 pte (&x->tm);
09f131f2
JH		 2640 fprintf (stdout, " address: base %s index %s scale %x\n",
2641 x->base_reg ? x->base_reg->reg_name : "none",
2642 x->index_reg ? x->index_reg->reg_name : "none",
2643 x->log2_scale_factor);
2644 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2645 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2646 fprintf (stdout, " sib: base %x index %x scale %x\n",
2647 x->sib.base, x->sib.index, x->sib.scale);
2648 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2649 (x->rex & REX_W) != 0,
2650 (x->rex & REX_R) != 0,
2651 (x->rex & REX_X) != 0,
2652 (x->rex & REX_B) != 0);
09137c09 2653 for (j = 0; j < x->operands; j++)
252b5132 2654 {
09137c09
SP		 2655 fprintf (stdout, " #%d: ", j + 1);
2656 pt (x->types[j]);
252b5132 2657 fprintf (stdout, "\n");
09137c09
SP		 2658 if (x->types[j].bitfield.reg8
2659 || x->types[j].bitfield.reg16
2660 || x->types[j].bitfield.reg32
2661 || x->types[j].bitfield.reg64
2662 || x->types[j].bitfield.regmmx
2663 || x->types[j].bitfield.regxmm
2664 || x->types[j].bitfield.regymm
43234a1e 2665 || x->types[j].bitfield.regzmm
09137c09
SP		 2666 || x->types[j].bitfield.sreg2
2667 || x->types[j].bitfield.sreg3
2668 || x->types[j].bitfield.control
2669 || x->types[j].bitfield.debug
2670 || x->types[j].bitfield.test)
2671 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2672 if (operand_type_check (x->types[j], imm))
2673 pe (x->op[j].imms);
2674 if (operand_type_check (x->types[j], disp))
2675 pe (x->op[j].disps);
252b5132
RH		 2676 }
2677}
2678
2679static void
d3ce72d0 2680pte (insn_template *t)
252b5132 2681{
09137c09 2682 unsigned int j;
252b5132 2683 fprintf (stdout, " %d operands ", t->operands);
47926f60 2684 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2685 if (t->extension_opcode != None)
2686 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2687 if (t->opcode_modifier.d)
252b5132 2688 fprintf (stdout, "D");
40fb9820 2689 if (t->opcode_modifier.w)
252b5132
RH		 2690 fprintf (stdout, "W");
2691 fprintf (stdout, "\n");
09137c09 2692 for (j = 0; j < t->operands; j++)
252b5132 2693 {
09137c09
SP		 2694 fprintf (stdout, " #%d type ", j + 1);
2695 pt (t->operand_types[j]);
252b5132
RH		 2696 fprintf (stdout, "\n");
2697 }
2698}
2699
2700static void
e3bb37b5 2701pe (expressionS *e)
252b5132 2702{
24eab124 2703 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2704 fprintf (stdout, " add_number %ld (%lx)\n",
2705 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2706 if (e->X_add_symbol)
2707 {
2708 fprintf (stdout, " add_symbol ");
2709 ps (e->X_add_symbol);
2710 fprintf (stdout, "\n");
2711 }
2712 if (e->X_op_symbol)
2713 {
2714 fprintf (stdout, " op_symbol ");
2715 ps (e->X_op_symbol);
2716 fprintf (stdout, "\n");
2717 }
2718}
2719
2720static void
e3bb37b5 2721ps (symbolS *s)
252b5132
RH		 2722{
2723 fprintf (stdout, "%s type %s%s",
2724 S_GET_NAME (s),
2725 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2726 segment_name (S_GET_SEGMENT (s)));
2727}
2728
7b81dfbb 2729static struct type_name
252b5132 2730 {
40fb9820
L		 2731 i386_operand_type mask;
2732 const char *name;
252b5132 2733 }
7b81dfbb 2734const type_names[] =
252b5132 2735{
40fb9820
L		 2736 { OPERAND_TYPE_REG8, "r8" },
2737 { OPERAND_TYPE_REG16, "r16" },
2738 { OPERAND_TYPE_REG32, "r32" },
2739 { OPERAND_TYPE_REG64, "r64" },
2740 { OPERAND_TYPE_IMM8, "i8" },
2741 { OPERAND_TYPE_IMM8, "i8s" },
2742 { OPERAND_TYPE_IMM16, "i16" },
2743 { OPERAND_TYPE_IMM32, "i32" },
2744 { OPERAND_TYPE_IMM32S, "i32s" },
2745 { OPERAND_TYPE_IMM64, "i64" },
2746 { OPERAND_TYPE_IMM1, "i1" },
2747 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2748 { OPERAND_TYPE_DISP8, "d8" },
2749 { OPERAND_TYPE_DISP16, "d16" },
2750 { OPERAND_TYPE_DISP32, "d32" },
2751 { OPERAND_TYPE_DISP32S, "d32s" },
2752 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2753 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2754 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2755 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2756 { OPERAND_TYPE_CONTROL, "control reg" },
2757 { OPERAND_TYPE_TEST, "test reg" },
2758 { OPERAND_TYPE_DEBUG, "debug reg" },
2759 { OPERAND_TYPE_FLOATREG, "FReg" },
2760 { OPERAND_TYPE_FLOATACC, "FAcc" },
2761 { OPERAND_TYPE_SREG2, "SReg2" },
2762 { OPERAND_TYPE_SREG3, "SReg3" },
2763 { OPERAND_TYPE_ACC, "Acc" },
2764 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2765 { OPERAND_TYPE_REGMMX, "rMMX" },
2766 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2767 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2768 { OPERAND_TYPE_REGZMM, "rZMM" },
2769 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2770 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2771};
2772
2773static void
40fb9820 2774pt (i386_operand_type t)
252b5132 2775{
40fb9820 2776 unsigned int j;
c6fb90c8 2777 i386_operand_type a;
252b5132 2778
40fb9820 2779 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2780 {
2781 a = operand_type_and (t, type_names[j].mask);
0349dc08 2782 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2783 fprintf (stdout, "%s, ", type_names[j].name);
2784 }
252b5132
RH		 2785 fflush (stdout);
2786}
2787
2788#endif /* DEBUG386 */
2789\f
252b5132 2790static bfd_reloc_code_real_type
3956db08 2791reloc (unsigned int size,
64e74474
AM		 2792 int pcrel,
2793 int sign,
2794 bfd_reloc_code_real_type other)
252b5132 2795{
47926f60 2796 if (other != NO_RELOC)
3956db08 2797 {
91d6fa6a 2798 reloc_howto_type *rel;
3956db08
JB		 2799
2800 if (size == 8)
2801 switch (other)
2802 {
64e74474
AM		 2803 case BFD_RELOC_X86_64_GOT32:
2804 return BFD_RELOC_X86_64_GOT64;
2805 break;
553d1284
L		 2806 case BFD_RELOC_X86_64_GOTPLT64:
2807 return BFD_RELOC_X86_64_GOTPLT64;
2808 break;
64e74474
AM		 2809 case BFD_RELOC_X86_64_PLTOFF64:
2810 return BFD_RELOC_X86_64_PLTOFF64;
2811 break;
2812 case BFD_RELOC_X86_64_GOTPC32:
2813 other = BFD_RELOC_X86_64_GOTPC64;
2814 break;
2815 case BFD_RELOC_X86_64_GOTPCREL:
2816 other = BFD_RELOC_X86_64_GOTPCREL64;
2817 break;
2818 case BFD_RELOC_X86_64_TPOFF32:
2819 other = BFD_RELOC_X86_64_TPOFF64;
2820 break;
2821 case BFD_RELOC_X86_64_DTPOFF32:
2822 other = BFD_RELOC_X86_64_DTPOFF64;
2823 break;
2824 default:
2825 break;
3956db08 2826 }
e05278af 2827
8ce3d284 2828#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2829 if (other == BFD_RELOC_SIZE32)
2830 {
2831 if (size == 8)
1ab668bf 2832 other = BFD_RELOC_SIZE64;
8fd4256d 2833 if (pcrel)
1ab668bf
AM		 2834 {
2835 as_bad (_("there are no pc-relative size relocations"));
2836 return NO_RELOC;
2837 }
8fd4256d 2838 }
8ce3d284 2839#endif
8fd4256d 2840
e05278af 2841 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2842 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2843 sign = -1;
2844
91d6fa6a
NC		 2845 rel = bfd_reloc_type_lookup (stdoutput, other);
2846 if (!rel)
3956db08 2847 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2848 else if (size != bfd_get_reloc_size (rel))
3956db08 2849 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2850 bfd_get_reloc_size (rel),
3956db08 2851 size);
91d6fa6a 2852 else if (pcrel && !rel->pc_relative)
3956db08 2853 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2854 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2855 && !sign)
91d6fa6a 2856 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2857 && sign > 0))
3956db08
JB		 2858 as_bad (_("relocated field and relocation type differ in signedness"));
2859 else
2860 return other;
2861 return NO_RELOC;
2862 }
252b5132
RH		 2863
2864 if (pcrel)
2865 {
3e73aa7c 2866 if (!sign)
3956db08 2867 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2868 switch (size)
2869 {
2870 case 1: return BFD_RELOC_8_PCREL;
2871 case 2: return BFD_RELOC_16_PCREL;
d258b828 2872 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2873 case 8: return BFD_RELOC_64_PCREL;
252b5132 2874 }
3956db08 2875 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2876 }
2877 else
2878 {
3956db08 2879 if (sign > 0)
e5cb08ac 2880 switch (size)
3e73aa7c
JH		 2881 {
2882 case 4: return BFD_RELOC_X86_64_32S;
2883 }
2884 else
2885 switch (size)
2886 {
2887 case 1: return BFD_RELOC_8;
2888 case 2: return BFD_RELOC_16;
2889 case 4: return BFD_RELOC_32;
2890 case 8: return BFD_RELOC_64;
2891 }
3956db08
JB		 2892 as_bad (_("cannot do %s %u byte relocation"),
2893 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2894 }
2895
0cc9e1d3 2896 return NO_RELOC;
252b5132
RH		 2897}
2898
47926f60
KH		 2899/* Here we decide which fixups can be adjusted to make them relative to
2900 the beginning of the section instead of the symbol. Basically we need
2901 to make sure that the dynamic relocations are done correctly, so in
2902 some cases we force the original symbol to be used. */
2903
252b5132 2904int
e3bb37b5 2905tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2906{
6d249963 2907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2908 if (!IS_ELF)
31312f95
AM		 2909 return 1;
2910
a161fe53
AM		 2911 /* Don't adjust pc-relative references to merge sections in 64-bit
2912 mode. */
2913 if (use_rela_relocations
2914 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2915 && fixP->fx_pcrel)
252b5132 2916 return 0;
31312f95 2917
8d01d9a9
AJ		 2918 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2919 and changed later by validate_fix. */
2920 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2921 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2922 return 0;
2923
8fd4256d
L		 2924 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2925 for size relocations. */
2926 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2927 || fixP->fx_r_type == BFD_RELOC_SIZE64
2928 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2929 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2930 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 2931 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 2932 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2933 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2942 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2943 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2944 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 2945 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
2946 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 2947 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2949 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2950 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2951 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2955 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2956 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2957 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2958 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2959 return 0;
31312f95 2960#endif
252b5132
RH		 2961 return 1;
2962}
252b5132 2963
b4cac588 2964static int
e3bb37b5 2965intel_float_operand (const char *mnemonic)
252b5132 2966{
9306ca4a
JB		 2967 /* Note that the value returned is meaningful only for opcodes with (memory)
2968 operands, hence the code here is free to improperly handle opcodes that
2969 have no operands (for better performance and smaller code). */
2970
2971 if (mnemonic[0] != 'f')
2972 return 0; /* non-math */
2973
2974 switch (mnemonic[1])
2975 {
2976 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2977 the fs segment override prefix not currently handled because no
2978 call path can make opcodes without operands get here */
2979 case 'i':
2980 return 2 /* integer op */;
2981 case 'l':
2982 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2983 return 3; /* fldcw/fldenv */
2984 break;
2985 case 'n':
2986 if (mnemonic[2] != 'o' /* fnop */)
2987 return 3; /* non-waiting control op */
2988 break;
2989 case 'r':
2990 if (mnemonic[2] == 's')
2991 return 3; /* frstor/frstpm */
2992 break;
2993 case 's':
2994 if (mnemonic[2] == 'a')
2995 return 3; /* fsave */
2996 if (mnemonic[2] == 't')
2997 {
2998 switch (mnemonic[3])
2999 {
3000 case 'c': /* fstcw */
3001 case 'd': /* fstdw */
3002 case 'e': /* fstenv */
3003 case 's': /* fsts[gw] */
3004 return 3;
3005 }
3006 }
3007 break;
3008 case 'x':
3009 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3010 return 0; /* fxsave/fxrstor are not really math ops */
3011 break;
3012 }
252b5132 3013
9306ca4a 3014 return 1;
252b5132
RH		 3015}
3016
c0f3af97
L		 3017/* Build the VEX prefix. */
3018
3019static void
d3ce72d0 3020build_vex_prefix (const insn_template *t)
c0f3af97
L		 3021{
3022 unsigned int register_specifier;
3023 unsigned int implied_prefix;
3024 unsigned int vector_length;
3025
3026 /* Check register specifier. */
3027 if (i.vex.register_specifier)
43234a1e
L		 3028 {
3029 register_specifier =
3030 ~register_number (i.vex.register_specifier) & 0xf;
3031 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3032 }
c0f3af97
L		 3033 else
3034 register_specifier = 0xf;
3035
fa99fab2
L		 3036 /* Use 2-byte VEX prefix by swappping destination and source
3037 operand. */
3038 if (!i.swap_operand
3039 && i.operands == i.reg_operands
7f399153 3040 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3041 && i.tm.opcode_modifier.s
3042 && i.rex == REX_B)
3043 {
3044 unsigned int xchg = i.operands - 1;
3045 union i386_op temp_op;
3046 i386_operand_type temp_type;
3047
3048 temp_type = i.types[xchg];
3049 i.types[xchg] = i.types[0];
3050 i.types[0] = temp_type;
3051 temp_op = i.op[xchg];
3052 i.op[xchg] = i.op[0];
3053 i.op[0] = temp_op;
3054
9c2799c2 3055 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3056
3057 i.rex = REX_R;
3058 xchg = i.rm.regmem;
3059 i.rm.regmem = i.rm.reg;
3060 i.rm.reg = xchg;
3061
3062 /* Use the next insn. */
3063 i.tm = t[1];
3064 }
3065
539f890d
L		 3066 if (i.tm.opcode_modifier.vex == VEXScalar)
3067 vector_length = avxscalar;
3068 else
3069 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3070
3071 switch ((i.tm.base_opcode >> 8) & 0xff)
3072 {
3073 case 0:
3074 implied_prefix = 0;
3075 break;
3076 case DATA_PREFIX_OPCODE:
3077 implied_prefix = 1;
3078 break;
3079 case REPE_PREFIX_OPCODE:
3080 implied_prefix = 2;
3081 break;
3082 case REPNE_PREFIX_OPCODE:
3083 implied_prefix = 3;
3084 break;
3085 default:
3086 abort ();
3087 }
3088
3089 /* Use 2-byte VEX prefix if possible. */
7f399153 3090 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3091 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3092 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3093 {
3094 /* 2-byte VEX prefix. */
3095 unsigned int r;
3096
3097 i.vex.length = 2;
3098 i.vex.bytes[0] = 0xc5;
3099
3100 /* Check the REX.R bit. */
3101 r = (i.rex & REX_R) ? 0 : 1;
3102 i.vex.bytes[1] = (r << 7
3103 | register_specifier << 3
3104 | vector_length << 2
3105 | implied_prefix);
3106 }
3107 else
3108 {
3109 /* 3-byte VEX prefix. */
3110 unsigned int m, w;
3111
f88c9eb0 3112 i.vex.length = 3;
f88c9eb0 3113
7f399153 3114 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3115 {
7f399153
L		 3116 case VEX0F:
3117 m = 0x1;
80de6e00 3118 i.vex.bytes[0] = 0xc4;
7f399153
L		 3119 break;
3120 case VEX0F38:
3121 m = 0x2;
80de6e00 3122 i.vex.bytes[0] = 0xc4;
7f399153
L		 3123 break;
3124 case VEX0F3A:
3125 m = 0x3;
80de6e00 3126 i.vex.bytes[0] = 0xc4;
7f399153
L		 3127 break;
3128 case XOP08:
5dd85c99
SP		 3129 m = 0x8;
3130 i.vex.bytes[0] = 0x8f;
7f399153
L		 3131 break;
3132 case XOP09:
f88c9eb0
SP		 3133 m = 0x9;
3134 i.vex.bytes[0] = 0x8f;
7f399153
L		 3135 break;
3136 case XOP0A:
f88c9eb0
SP		 3137 m = 0xa;
3138 i.vex.bytes[0] = 0x8f;
7f399153
L		 3139 break;
3140 default:
3141 abort ();
f88c9eb0 3142 }
c0f3af97 3143
c0f3af97
L		 3144 /* The high 3 bits of the second VEX byte are 1's compliment
3145 of RXB bits from REX. */
3146 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3147
3148 /* Check the REX.W bit. */
3149 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3150 if (i.tm.opcode_modifier.vexw == VEXW1)
3151 w = 1;
c0f3af97
L		 3152
3153 i.vex.bytes[2] = (w << 7
3154 | register_specifier << 3
3155 | vector_length << 2
3156 | implied_prefix);
3157 }
3158}
3159
43234a1e
L		 3160/* Build the EVEX prefix. */
3161
3162static void
3163build_evex_prefix (void)
3164{
3165 unsigned int register_specifier;
3166 unsigned int implied_prefix;
3167 unsigned int m, w;
3168 rex_byte vrex_used = 0;
3169
3170 /* Check register specifier. */
3171 if (i.vex.register_specifier)
3172 {
3173 gas_assert ((i.vrex & REX_X) == 0);
3174
3175 register_specifier = i.vex.register_specifier->reg_num;
3176 if ((i.vex.register_specifier->reg_flags & RegRex))
3177 register_specifier += 8;
3178 /* The upper 16 registers are encoded in the fourth byte of the
3179 EVEX prefix. */
3180 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3181 i.vex.bytes[3] = 0x8;
3182 register_specifier = ~register_specifier & 0xf;
3183 }
3184 else
3185 {
3186 register_specifier = 0xf;
3187
3188 /* Encode upper 16 vector index register in the fourth byte of
3189 the EVEX prefix. */
3190 if (!(i.vrex & REX_X))
3191 i.vex.bytes[3] = 0x8;
3192 else
3193 vrex_used |= REX_X;
3194 }
3195
3196 switch ((i.tm.base_opcode >> 8) & 0xff)
3197 {
3198 case 0:
3199 implied_prefix = 0;
3200 break;
3201 case DATA_PREFIX_OPCODE:
3202 implied_prefix = 1;
3203 break;
3204 case REPE_PREFIX_OPCODE:
3205 implied_prefix = 2;
3206 break;
3207 case REPNE_PREFIX_OPCODE:
3208 implied_prefix = 3;
3209 break;
3210 default:
3211 abort ();
3212 }
3213
3214 /* 4 byte EVEX prefix. */
3215 i.vex.length = 4;
3216 i.vex.bytes[0] = 0x62;
3217
3218 /* mmmm bits. */
3219 switch (i.tm.opcode_modifier.vexopcode)
3220 {
3221 case VEX0F:
3222 m = 1;
3223 break;
3224 case VEX0F38:
3225 m = 2;
3226 break;
3227 case VEX0F3A:
3228 m = 3;
3229 break;
3230 default:
3231 abort ();
3232 break;
3233 }
3234
3235 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3236 bits from REX. */
3237 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3238
3239 /* The fifth bit of the second EVEX byte is 1's compliment of the
3240 REX_R bit in VREX. */
3241 if (!(i.vrex & REX_R))
3242 i.vex.bytes[1] |= 0x10;
3243 else
3244 vrex_used |= REX_R;
3245
3246 if ((i.reg_operands + i.imm_operands) == i.operands)
3247 {
3248 /* When all operands are registers, the REX_X bit in REX is not
3249 used. We reuse it to encode the upper 16 registers, which is
3250 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3251 as 1's compliment. */
3252 if ((i.vrex & REX_B))
3253 {
3254 vrex_used |= REX_B;
3255 i.vex.bytes[1] &= ~0x40;
3256 }
3257 }
3258
3259 /* EVEX instructions shouldn't need the REX prefix. */
3260 i.vrex &= ~vrex_used;
3261 gas_assert (i.vrex == 0);
3262
3263 /* Check the REX.W bit. */
3264 w = (i.rex & REX_W) ? 1 : 0;
3265 if (i.tm.opcode_modifier.vexw)
3266 {
3267 if (i.tm.opcode_modifier.vexw == VEXW1)
3268 w = 1;
3269 }
3270 /* If w is not set it means we are dealing with WIG instruction. */
3271 else if (!w)
3272 {
3273 if (evexwig == evexw1)
3274 w = 1;
3275 }
3276
3277 /* Encode the U bit. */
3278 implied_prefix |= 0x4;
3279
3280 /* The third byte of the EVEX prefix. */
3281 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3282
3283 /* The fourth byte of the EVEX prefix. */
3284 /* The zeroing-masking bit. */
3285 if (i.mask && i.mask->zeroing)
3286 i.vex.bytes[3] |= 0x80;
3287
3288 /* Don't always set the broadcast bit if there is no RC. */
3289 if (!i.rounding)
3290 {
3291 /* Encode the vector length. */
3292 unsigned int vec_length;
3293
3294 switch (i.tm.opcode_modifier.evex)
3295 {
3296 case EVEXLIG: /* LL' is ignored */
3297 vec_length = evexlig << 5;
3298 break;
3299 case EVEX128:
3300 vec_length = 0 << 5;
3301 break;
3302 case EVEX256:
3303 vec_length = 1 << 5;
3304 break;
3305 case EVEX512:
3306 vec_length = 2 << 5;
3307 break;
3308 default:
3309 abort ();
3310 break;
3311 }
3312 i.vex.bytes[3] |= vec_length;
3313 /* Encode the broadcast bit. */
3314 if (i.broadcast)
3315 i.vex.bytes[3] |= 0x10;
3316 }
3317 else
3318 {
3319 if (i.rounding->type != saeonly)
3320 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3321 else
d3d3c6db 3322 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3323 }
3324
3325 if (i.mask && i.mask->mask)
3326 i.vex.bytes[3] |= i.mask->mask->reg_num;
3327}
3328
65da13b5
L		 3329static void
3330process_immext (void)
3331{
3332 expressionS *exp;
3333
4c692bc7
JB		 3334 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3335 && i.operands > 0)
65da13b5 3336 {
4c692bc7
JB		 3337 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3338 with an opcode suffix which is coded in the same place as an
3339 8-bit immediate field would be.
3340 Here we check those operands and remove them afterwards. */
65da13b5
L		 3341 unsigned int x;
3342
3343 for (x = 0; x < i.operands; x++)
4c692bc7 3344 if (register_number (i.op[x].regs) != x)
65da13b5 3345 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3346 register_prefix, i.op[x].regs->reg_name, x + 1,
3347 i.tm.name);
3348
3349 i.operands = 0;
65da13b5
L		 3350 }
3351
9916071f
AP		 3352 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3353 {
3354 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3355 suffix which is coded in the same place as an 8-bit immediate
3356 field would be.
3357 Here we check those operands and remove them afterwards. */
3358 unsigned int x;
3359
3360 if (i.operands != 3)
3361 abort();
3362
3363 for (x = 0; x < 2; x++)
3364 if (register_number (i.op[x].regs) != x)
3365 goto bad_register_operand;
3366
3367 /* Check for third operand for mwaitx/monitorx insn. */
3368 if (register_number (i.op[x].regs)
3369 != (x + (i.tm.extension_opcode == 0xfb)))
3370 {
3371bad_register_operand:
3372 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3373 register_prefix, i.op[x].regs->reg_name, x+1,
3374 i.tm.name);
3375 }
3376
3377 i.operands = 0;
3378 }
3379
c0f3af97 3380 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3381 which is coded in the same place as an 8-bit immediate field
3382 would be. Here we fake an 8-bit immediate operand from the
3383 opcode suffix stored in tm.extension_opcode.
3384
c1e679ec 3385 AVX instructions also use this encoding, for some of
c0f3af97 3386 3 argument instructions. */
65da13b5 3387
43234a1e 3388 gas_assert (i.imm_operands <= 1
7ab9ffdd 3389 && (i.operands <= 2
43234a1e
L		 3390 || ((i.tm.opcode_modifier.vex
3391 || i.tm.opcode_modifier.evex)
7ab9ffdd 3392 && i.operands <= 4)));
65da13b5
L		 3393
3394 exp = &im_expressions[i.imm_operands++];
3395 i.op[i.operands].imms = exp;
3396 i.types[i.operands] = imm8;
3397 i.operands++;
3398 exp->X_op = O_constant;
3399 exp->X_add_number = i.tm.extension_opcode;
3400 i.tm.extension_opcode = None;
3401}
3402
42164a71
L		 3403
3404static int
3405check_hle (void)
3406{
3407 switch (i.tm.opcode_modifier.hleprefixok)
3408 {
3409 default:
3410 abort ();
82c2def5 3411 case HLEPrefixNone:
165de32a
L		 3412 as_bad (_("invalid instruction `%s' after `%s'"),
3413 i.tm.name, i.hle_prefix);
42164a71 3414 return 0;
82c2def5 3415 case HLEPrefixLock:
42164a71
L		 3416 if (i.prefix[LOCK_PREFIX])
3417 return 1;
165de32a 3418 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3419 return 0;
82c2def5 3420 case HLEPrefixAny:
42164a71 3421 return 1;
82c2def5 3422 case HLEPrefixRelease:
42164a71
L		 3423 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3424 {
3425 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3426 i.tm.name);
3427 return 0;
3428 }
3429 if (i.mem_operands == 0
3430 || !operand_type_check (i.types[i.operands - 1], anymem))
3431 {
3432 as_bad (_("memory destination needed for instruction `%s'"
3433 " after `xrelease'"), i.tm.name);
3434 return 0;
3435 }
3436 return 1;
3437 }
3438}
3439
252b5132
RH		 3440/* This is the guts of the machine-dependent assembler. LINE points to a
3441 machine dependent instruction. This function is supposed to emit
3442 the frags/bytes it assembles to. */
3443
3444void
65da13b5 3445md_assemble (char *line)
252b5132 3446{
40fb9820 3447 unsigned int j;
252b5132 3448 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3449 const insn_template *t;
252b5132 3450
47926f60 3451 /* Initialize globals. */
252b5132
RH		 3452 memset (&i, '\0', sizeof (i));
3453 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3454 i.reloc[j] = NO_RELOC;
252b5132
RH		 3455 memset (disp_expressions, '\0', sizeof (disp_expressions));
3456 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3457 save_stack_p = save_stack;
252b5132
RH		 3458
3459 /* First parse an instruction mnemonic & call i386_operand for the operands.
3460 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3461 start of a (possibly prefixed) mnemonic. */
252b5132 3462
29b0f896
AM		 3463 line = parse_insn (line, mnemonic);
3464 if (line == NULL)
3465 return;
252b5132 3466
29b0f896 3467 line = parse_operands (line, mnemonic);
ee86248c 3468 this_operand = -1;
29b0f896
AM		 3469 if (line == NULL)
3470 return;
252b5132 3471
29b0f896
AM		 3472 /* Now we've parsed the mnemonic into a set of templates, and have the
3473 operands at hand. */
3474
3475 /* All intel opcodes have reversed operands except for "bound" and
3476 "enter". We also don't reverse intersegment "jmp" and "call"
3477 instructions with 2 immediate operands so that the immediate segment
050dfa73 3478 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3479 if (intel_syntax
3480 && i.operands > 1
29b0f896 3481 && (strcmp (mnemonic, "bound") != 0)
30123838 3482 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3483 && !(operand_type_check (i.types[0], imm)
3484 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3485 swap_operands ();
3486
ec56d5c0
JB		 3487 /* The order of the immediates should be reversed
3488 for 2 immediates extrq and insertq instructions */
3489 if (i.imm_operands == 2
3490 && (strcmp (mnemonic, "extrq") == 0
3491 || strcmp (mnemonic, "insertq") == 0))
3492 swap_2_operands (0, 1);
3493
29b0f896
AM		 3494 if (i.imm_operands)
3495 optimize_imm ();
3496
b300c311
L		 3497 /* Don't optimize displacement for movabs since it only takes 64bit
3498 displacement. */
3499 if (i.disp_operands
a501d77e 3500 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3501 && (flag_code != CODE_64BIT
3502 || strcmp (mnemonic, "movabs") != 0))
3503 optimize_disp ();
29b0f896
AM		 3504
3505 /* Next, we find a template that matches the given insn,
3506 making sure the overlap of the given operands types is consistent
3507 with the template operand types. */
252b5132 3508
fa99fab2 3509 if (!(t = match_template ()))
29b0f896 3510 return;
252b5132 3511
7bab8ab5 3512 if (sse_check != check_none
81f8a913 3513 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3514 && (i.tm.cpu_flags.bitfield.cpusse
3515 || i.tm.cpu_flags.bitfield.cpusse2
3516 || i.tm.cpu_flags.bitfield.cpusse3
3517 || i.tm.cpu_flags.bitfield.cpussse3
3518 || i.tm.cpu_flags.bitfield.cpusse4_1
3519 || i.tm.cpu_flags.bitfield.cpusse4_2))
3520 {
7bab8ab5 3521 (sse_check == check_warning
daf50ae7
L		 3522 ? as_warn
3523 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3524 }
3525
321fd21e
L		 3526 /* Zap movzx and movsx suffix. The suffix has been set from
3527 "word ptr" or "byte ptr" on the source operand in Intel syntax
3528 or extracted from mnemonic in AT&T syntax. But we'll use
3529 the destination register to choose the suffix for encoding. */
3530 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3531 {
321fd21e
L		 3532 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3533 there is no suffix, the default will be byte extension. */
3534 if (i.reg_operands != 2
3535 && !i.suffix
7ab9ffdd 3536 && intel_syntax)
321fd21e
L		 3537 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3538
3539 i.suffix = 0;
cd61ebfe 3540 }
24eab124 3541
40fb9820 3542 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3543 if (!add_prefix (FWAIT_OPCODE))
3544 return;
252b5132 3545
d5de92cf
L		 3546 /* Check if REP prefix is OK. */
3547 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3548 {
3549 as_bad (_("invalid instruction `%s' after `%s'"),
3550 i.tm.name, i.rep_prefix);
3551 return;
3552 }
3553
c1ba0266
L		 3554 /* Check for lock without a lockable instruction. Destination operand
3555 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3556 if (i.prefix[LOCK_PREFIX]
3557 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3558 || i.mem_operands == 0
3559 || (i.tm.base_opcode != 0x86
3560 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3561 {
3562 as_bad (_("expecting lockable instruction after `lock'"));
3563 return;
3564 }
3565
42164a71 3566 /* Check if HLE prefix is OK. */
165de32a 3567 if (i.hle_prefix && !check_hle ())
42164a71
L		 3568 return;
3569
7e8b059b
L		 3570 /* Check BND prefix. */
3571 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3572 as_bad (_("expecting valid branch instruction after `bnd'"));
3573
3574 if (i.tm.cpu_flags.bitfield.cpumpx
3575 && flag_code == CODE_64BIT
3576 && i.prefix[ADDR_PREFIX])
3577 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3578
3579 /* Insert BND prefix. */
3580 if (add_bnd_prefix
3581 && i.tm.opcode_modifier.bndprefixok
3582 && !i.prefix[BND_PREFIX])
3583 add_prefix (BND_PREFIX_OPCODE);
3584
29b0f896 3585 /* Check string instruction segment overrides. */
40fb9820 3586 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3587 {
3588 if (!check_string ())
5dd0794d 3589 return;
fc0763e6 3590 i.disp_operands = 0;
29b0f896 3591 }
5dd0794d 3592
29b0f896
AM		 3593 if (!process_suffix ())
3594 return;
e413e4e9 3595
bc0844ae
L		 3596 /* Update operand types. */
3597 for (j = 0; j < i.operands; j++)
3598 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3599
29b0f896
AM		 3600 /* Make still unresolved immediate matches conform to size of immediate
3601 given in i.suffix. */
3602 if (!finalize_imm ())
3603 return;
252b5132 3604
40fb9820 3605 if (i.types[0].bitfield.imm1)
29b0f896 3606 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3607
9afe6eb8
L		 3608 /* We only need to check those implicit registers for instructions
3609 with 3 operands or less. */
3610 if (i.operands <= 3)
3611 for (j = 0; j < i.operands; j++)
3612 if (i.types[j].bitfield.inoutportreg
3613 || i.types[j].bitfield.shiftcount
3614 || i.types[j].bitfield.acc
3615 || i.types[j].bitfield.floatacc)
3616 i.reg_operands--;
40fb9820 3617
c0f3af97
L		 3618 /* ImmExt should be processed after SSE2AVX. */
3619 if (!i.tm.opcode_modifier.sse2avx
3620 && i.tm.opcode_modifier.immext)
65da13b5 3621 process_immext ();
252b5132 3622
29b0f896
AM		 3623 /* For insns with operands there are more diddles to do to the opcode. */
3624 if (i.operands)
3625 {
3626 if (!process_operands ())
3627 return;
3628 }
40fb9820 3629 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3630 {
3631 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3632 as_warn (_("translating to `%sp'"), i.tm.name);
3633 }
252b5132 3634
9e5e5283
L		 3635 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3636 {
3637 if (flag_code == CODE_16BIT)
3638 {
3639 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3640 i.tm.name);
3641 return;
3642 }
c0f3af97 3643
9e5e5283
L		 3644 if (i.tm.opcode_modifier.vex)
3645 build_vex_prefix (t);
3646 else
3647 build_evex_prefix ();
3648 }
43234a1e 3649
5dd85c99
SP		 3650 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3651 instructions may define INT_OPCODE as well, so avoid this corner
3652 case for those instructions that use MODRM. */
3653 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3654 && !i.tm.opcode_modifier.modrm
3655 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3656 {
3657 i.tm.base_opcode = INT3_OPCODE;
3658 i.imm_operands = 0;
3659 }
252b5132 3660
40fb9820
L		 3661 if ((i.tm.opcode_modifier.jump
3662 || i.tm.opcode_modifier.jumpbyte
3663 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3664 && i.op[0].disps->X_op == O_constant)
3665 {
3666 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3667 the absolute address given by the constant. Since ix86 jumps and
3668 calls are pc relative, we need to generate a reloc. */
3669 i.op[0].disps->X_add_symbol = &abs_symbol;
3670 i.op[0].disps->X_op = O_symbol;
3671 }
252b5132 3672
40fb9820 3673 if (i.tm.opcode_modifier.rex64)
161a04f6 3674 i.rex |= REX_W;
252b5132 3675
29b0f896
AM		 3676 /* For 8 bit registers we need an empty rex prefix. Also if the
3677 instruction already has a prefix, we need to convert old
3678 registers to new ones. */
773f551c 3679
40fb9820 3680 if ((i.types[0].bitfield.reg8
29b0f896 3681 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3682 || (i.types[1].bitfield.reg8
29b0f896 3683 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3684 || ((i.types[0].bitfield.reg8
3685 || i.types[1].bitfield.reg8)
29b0f896
AM		 3686 && i.rex != 0))
3687 {
3688 int x;
726c5dcd 3689
29b0f896
AM		 3690 i.rex |= REX_OPCODE;
3691 for (x = 0; x < 2; x++)
3692 {
3693 /* Look for 8 bit operand that uses old registers. */
40fb9820 3694 if (i.types[x].bitfield.reg8
29b0f896 3695 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3696 {
29b0f896
AM		 3697 /* In case it is "hi" register, give up. */
3698 if (i.op[x].regs->reg_num > 3)
a540244d 3699 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3700 "instruction requiring REX prefix."),
a540244d 3701 register_prefix, i.op[x].regs->reg_name);
773f551c 3702
29b0f896
AM		 3703 /* Otherwise it is equivalent to the extended register.
3704 Since the encoding doesn't change this is merely
3705 cosmetic cleanup for debug output. */
3706
3707 i.op[x].regs = i.op[x].regs + 8;
773f551c 3708 }
29b0f896
AM		 3709 }
3710 }
773f551c 3711
7ab9ffdd 3712 if (i.rex != 0)
29b0f896
AM		 3713 add_prefix (REX_OPCODE | i.rex);
3714
3715 /* We are ready to output the insn. */
3716 output_insn ();
3717}
3718
3719static char *
e3bb37b5 3720parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3721{
3722 char *l = line;
3723 char *token_start = l;
3724 char *mnem_p;
5c6af06e 3725 int supported;
d3ce72d0 3726 const insn_template *t;
b6169b20 3727 char *dot_p = NULL;
29b0f896 3728
29b0f896
AM		 3729 while (1)
3730 {
3731 mnem_p = mnemonic;
3732 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3733 {
b6169b20
L		 3734 if (*mnem_p == '.')
3735 dot_p = mnem_p;
29b0f896
AM		 3736 mnem_p++;
3737 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3738 {
29b0f896
AM		 3739 as_bad (_("no such instruction: `%s'"), token_start);
3740 return NULL;
3741 }
3742 l++;
3743 }
3744 if (!is_space_char (*l)
3745 && *l != END_OF_INSN
e44823cf
JB		 3746 && (intel_syntax
3747 || (*l != PREFIX_SEPARATOR
3748 && *l != ',')))
29b0f896
AM		 3749 {
3750 as_bad (_("invalid character %s in mnemonic"),
3751 output_invalid (*l));
3752 return NULL;
3753 }
3754 if (token_start == l)
3755 {
e44823cf 3756 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3757 as_bad (_("expecting prefix; got nothing"));
3758 else
3759 as_bad (_("expecting mnemonic; got nothing"));
3760 return NULL;
3761 }
45288df1 3762
29b0f896 3763 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3764 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3765
29b0f896
AM		 3766 if (*l != END_OF_INSN
3767 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3768 && current_templates
40fb9820 3769 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3770 {
c6fb90c8 3771 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3772 {
3773 as_bad ((flag_code != CODE_64BIT
3774 ? _("`%s' is only supported in 64-bit mode")
3775 : _("`%s' is not supported in 64-bit mode")),
3776 current_templates->start->name);
3777 return NULL;
3778 }
29b0f896
AM		 3779 /* If we are in 16-bit mode, do not allow addr16 or data16.
3780 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3781 if ((current_templates->start->opcode_modifier.size16
3782 || current_templates->start->opcode_modifier.size32)
29b0f896 3783 && flag_code != CODE_64BIT
40fb9820 3784 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3785 ^ (flag_code == CODE_16BIT)))
3786 {
3787 as_bad (_("redundant %s prefix"),
3788 current_templates->start->name);
3789 return NULL;
45288df1 3790 }
29b0f896
AM		 3791 /* Add prefix, checking for repeated prefixes. */
3792 switch (add_prefix (current_templates->start->base_opcode))
3793 {
c32fa91d 3794 case PREFIX_EXIST:
29b0f896 3795 return NULL;
c32fa91d 3796 case PREFIX_REP:
42164a71 3797 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3798 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3799 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3800 i.bnd_prefix = current_templates->start->name;
42164a71 3801 else
d5de92cf 3802 i.rep_prefix = current_templates->start->name;
29b0f896 3803 break;
c32fa91d
L		 3804 default:
3805 break;
29b0f896
AM		 3806 }
3807 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3808 token_start = ++l;
3809 }
3810 else
3811 break;
3812 }
45288df1 3813
30a55f88 3814 if (!current_templates)
b6169b20 3815 {
f8a5c266
L		 3816 /* Check if we should swap operand or force 32bit displacement in
3817 encoding. */
30a55f88
L		 3818 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3819 i.swap_operand = 1;
8d63c93e 3820 else if (mnem_p - 3 == dot_p
a501d77e
L		 3821 && dot_p[1] == 'd'
3822 && dot_p[2] == '8')
3823 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3824 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3825 && dot_p[1] == 'd'
3826 && dot_p[2] == '3'
3827 && dot_p[3] == '2')
a501d77e 3828 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3829 else
3830 goto check_suffix;
3831 mnem_p = dot_p;
3832 *dot_p = '\0';
d3ce72d0 3833 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3834 }
3835
29b0f896
AM		 3836 if (!current_templates)
3837 {
b6169b20 3838check_suffix:
29b0f896
AM		 3839 /* See if we can get a match by trimming off a suffix. */
3840 switch (mnem_p[-1])
3841 {
3842 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3843 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3844 i.suffix = SHORT_MNEM_SUFFIX;
3845 else
29b0f896
AM		 3846 case BYTE_MNEM_SUFFIX:
3847 case QWORD_MNEM_SUFFIX:
3848 i.suffix = mnem_p[-1];
3849 mnem_p[-1] = '\0';
d3ce72d0
NC		 3850 current_templates = (const templates *) hash_find (op_hash,
3851 mnemonic);
29b0f896
AM		 3852 break;
3853 case SHORT_MNEM_SUFFIX:
3854 case LONG_MNEM_SUFFIX:
3855 if (!intel_syntax)
3856 {
3857 i.suffix = mnem_p[-1];
3858 mnem_p[-1] = '\0';
d3ce72d0
NC		 3859 current_templates = (const templates *) hash_find (op_hash,
3860 mnemonic);
29b0f896
AM		 3861 }
3862 break;
252b5132 3863
29b0f896
AM		 3864 /* Intel Syntax. */
3865 case 'd':
3866 if (intel_syntax)
3867 {
9306ca4a 3868 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3869 i.suffix = SHORT_MNEM_SUFFIX;
3870 else
3871 i.suffix = LONG_MNEM_SUFFIX;
3872 mnem_p[-1] = '\0';
d3ce72d0
NC		 3873 current_templates = (const templates *) hash_find (op_hash,
3874 mnemonic);
29b0f896
AM		 3875 }
3876 break;
3877 }
3878 if (!current_templates)
3879 {
3880 as_bad (_("no such instruction: `%s'"), token_start);
3881 return NULL;
3882 }
3883 }
252b5132 3884
40fb9820
L		 3885 if (current_templates->start->opcode_modifier.jump
3886 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3887 {
3888 /* Check for a branch hint. We allow ",pt" and ",pn" for
3889 predict taken and predict not taken respectively.
3890 I'm not sure that branch hints actually do anything on loop
3891 and jcxz insns (JumpByte) for current Pentium4 chips. They
3892 may work in the future and it doesn't hurt to accept them
3893 now. */
3894 if (l[0] == ',' && l[1] == 'p')
3895 {
3896 if (l[2] == 't')
3897 {
3898 if (!add_prefix (DS_PREFIX_OPCODE))
3899 return NULL;
3900 l += 3;
3901 }
3902 else if (l[2] == 'n')
3903 {
3904 if (!add_prefix (CS_PREFIX_OPCODE))
3905 return NULL;
3906 l += 3;
3907 }
3908 }
3909 }
3910 /* Any other comma loses. */
3911 if (*l == ',')
3912 {
3913 as_bad (_("invalid character %s in mnemonic"),
3914 output_invalid (*l));
3915 return NULL;
3916 }
252b5132 3917
29b0f896 3918 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3919 supported = 0;
3920 for (t = current_templates->start; t < current_templates->end; ++t)
3921 {
c0f3af97
L		 3922 supported |= cpu_flags_match (t);
3923 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3924 goto skip;
5c6af06e 3925 }
3629bb00 3926
c0f3af97 3927 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3928 {
3929 as_bad (flag_code == CODE_64BIT
3930 ? _("`%s' is not supported in 64-bit mode")
3931 : _("`%s' is only supported in 64-bit mode"),
3932 current_templates->start->name);
3933 return NULL;
3934 }
c0f3af97 3935 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3936 {
3629bb00 3937 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3938 current_templates->start->name,
41aacd83 3939 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3940 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3941 return NULL;
29b0f896 3942 }
3629bb00
L		 3943
3944skip:
3945 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3946 && (flag_code != CODE_16BIT))
29b0f896
AM		 3947 {
3948 as_warn (_("use .code16 to ensure correct addressing mode"));
3949 }
252b5132 3950
29b0f896
AM		 3951 return l;
3952}
252b5132 3953
29b0f896 3954static char *
e3bb37b5 3955parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3956{
3957 char *token_start;
3138f287 3958
29b0f896
AM		 3959 /* 1 if operand is pending after ','. */
3960 unsigned int expecting_operand = 0;
252b5132 3961
29b0f896
AM		 3962 /* Non-zero if operand parens not balanced. */
3963 unsigned int paren_not_balanced;
3964
3965 while (*l != END_OF_INSN)
3966 {
3967 /* Skip optional white space before operand. */
3968 if (is_space_char (*l))
3969 ++l;
d02603dc 3970 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 3971 {
3972 as_bad (_("invalid character %s before operand %d"),
3973 output_invalid (*l),
3974 i.operands + 1);
3975 return NULL;
3976 }
d02603dc 3977 token_start = l; /* After white space. */
29b0f896
AM		 3978 paren_not_balanced = 0;
3979 while (paren_not_balanced || *l != ',')
3980 {
3981 if (*l == END_OF_INSN)
3982 {
3983 if (paren_not_balanced)
3984 {
3985 if (!intel_syntax)
3986 as_bad (_("unbalanced parenthesis in operand %d."),
3987 i.operands + 1);
3988 else
3989 as_bad (_("unbalanced brackets in operand %d."),
3990 i.operands + 1);
3991 return NULL;
3992 }
3993 else
3994 break; /* we are done */
3995 }
d02603dc 3996 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 3997 {
3998 as_bad (_("invalid character %s in operand %d"),
3999 output_invalid (*l),
4000 i.operands + 1);
4001 return NULL;
4002 }
4003 if (!intel_syntax)
4004 {
4005 if (*l == '(')
4006 ++paren_not_balanced;
4007 if (*l == ')')
4008 --paren_not_balanced;
4009 }
4010 else
4011 {
4012 if (*l == '[')
4013 ++paren_not_balanced;
4014 if (*l == ']')
4015 --paren_not_balanced;
4016 }
4017 l++;
4018 }
4019 if (l != token_start)
4020 { /* Yes, we've read in another operand. */
4021 unsigned int operand_ok;
4022 this_operand = i.operands++;
7d5e4556 4023 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4024 if (i.operands > MAX_OPERANDS)
4025 {
4026 as_bad (_("spurious operands; (%d operands/instruction max)"),
4027 MAX_OPERANDS);
4028 return NULL;
4029 }
4030 /* Now parse operand adding info to 'i' as we go along. */
4031 END_STRING_AND_SAVE (l);
4032
4033 if (intel_syntax)
4034 operand_ok =
4035 i386_intel_operand (token_start,
4036 intel_float_operand (mnemonic));
4037 else
a7619375 4038 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4039
4040 RESTORE_END_STRING (l);
4041 if (!operand_ok)
4042 return NULL;
4043 }
4044 else
4045 {
4046 if (expecting_operand)
4047 {
4048 expecting_operand_after_comma:
4049 as_bad (_("expecting operand after ','; got nothing"));
4050 return NULL;
4051 }
4052 if (*l == ',')
4053 {
4054 as_bad (_("expecting operand before ','; got nothing"));
4055 return NULL;
4056 }
4057 }
7f3f1ea2 4058
29b0f896
AM		 4059 /* Now *l must be either ',' or END_OF_INSN. */
4060 if (*l == ',')
4061 {
4062 if (*++l == END_OF_INSN)
4063 {
4064 /* Just skip it, if it's \n complain. */
4065 goto expecting_operand_after_comma;
4066 }
4067 expecting_operand = 1;
4068 }
4069 }
4070 return l;
4071}
7f3f1ea2 4072
050dfa73 4073static void
4d456e3d 4074swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4075{
4076 union i386_op temp_op;
40fb9820 4077 i386_operand_type temp_type;
050dfa73 4078 enum bfd_reloc_code_real temp_reloc;
4eed87de 4079
050dfa73
MM		 4080 temp_type = i.types[xchg2];
4081 i.types[xchg2] = i.types[xchg1];
4082 i.types[xchg1] = temp_type;
4083 temp_op = i.op[xchg2];
4084 i.op[xchg2] = i.op[xchg1];
4085 i.op[xchg1] = temp_op;
4086 temp_reloc = i.reloc[xchg2];
4087 i.reloc[xchg2] = i.reloc[xchg1];
4088 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4089
4090 if (i.mask)
4091 {
4092 if (i.mask->operand == xchg1)
4093 i.mask->operand = xchg2;
4094 else if (i.mask->operand == xchg2)
4095 i.mask->operand = xchg1;
4096 }
4097 if (i.broadcast)
4098 {
4099 if (i.broadcast->operand == xchg1)
4100 i.broadcast->operand = xchg2;
4101 else if (i.broadcast->operand == xchg2)
4102 i.broadcast->operand = xchg1;
4103 }
4104 if (i.rounding)
4105 {
4106 if (i.rounding->operand == xchg1)
4107 i.rounding->operand = xchg2;
4108 else if (i.rounding->operand == xchg2)
4109 i.rounding->operand = xchg1;
4110 }
050dfa73
MM		 4111}
4112
29b0f896 4113static void
e3bb37b5 4114swap_operands (void)
29b0f896 4115{
b7c61d9a 4116 switch (i.operands)
050dfa73 4117 {
c0f3af97 4118 case 5:
b7c61d9a 4119 case 4:
4d456e3d 4120 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4121 case 3:
4122 case 2:
4d456e3d 4123 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4124 break;
4125 default:
4126 abort ();
29b0f896 4127 }
29b0f896
AM		 4128
4129 if (i.mem_operands == 2)
4130 {
4131 const seg_entry *temp_seg;
4132 temp_seg = i.seg[0];
4133 i.seg[0] = i.seg[1];
4134 i.seg[1] = temp_seg;
4135 }
4136}
252b5132 4137
29b0f896
AM		 4138/* Try to ensure constant immediates are represented in the smallest
4139 opcode possible. */
4140static void
e3bb37b5 4141optimize_imm (void)
29b0f896
AM		 4142{
4143 char guess_suffix = 0;
4144 int op;
252b5132 4145
29b0f896
AM		 4146 if (i.suffix)
4147 guess_suffix = i.suffix;
4148 else if (i.reg_operands)
4149 {
4150 /* Figure out a suffix from the last register operand specified.
4151 We can't do this properly yet, ie. excluding InOutPortReg,
4152 but the following works for instructions with immediates.
4153 In any case, we can't set i.suffix yet. */
4154 for (op = i.operands; --op >= 0;)
40fb9820 4155 if (i.types[op].bitfield.reg8)
7ab9ffdd 4156 {
40fb9820
L		 4157 guess_suffix = BYTE_MNEM_SUFFIX;
4158 break;
4159 }
4160 else if (i.types[op].bitfield.reg16)
252b5132 4161 {
40fb9820
L		 4162 guess_suffix = WORD_MNEM_SUFFIX;
4163 break;
4164 }
4165 else if (i.types[op].bitfield.reg32)
4166 {
4167 guess_suffix = LONG_MNEM_SUFFIX;
4168 break;
4169 }
4170 else if (i.types[op].bitfield.reg64)
4171 {
4172 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4173 break;
252b5132 4174 }
29b0f896
AM		 4175 }
4176 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4177 guess_suffix = WORD_MNEM_SUFFIX;
4178
4179 for (op = i.operands; --op >= 0;)
40fb9820 4180 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4181 {
4182 switch (i.op[op].imms->X_op)
252b5132 4183 {
29b0f896
AM		 4184 case O_constant:
4185 /* If a suffix is given, this operand may be shortened. */
4186 switch (guess_suffix)
252b5132 4187 {
29b0f896 4188 case LONG_MNEM_SUFFIX:
40fb9820
L		 4189 i.types[op].bitfield.imm32 = 1;
4190 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4191 break;
4192 case WORD_MNEM_SUFFIX:
40fb9820
L		 4193 i.types[op].bitfield.imm16 = 1;
4194 i.types[op].bitfield.imm32 = 1;
4195 i.types[op].bitfield.imm32s = 1;
4196 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4197 break;
4198 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4199 i.types[op].bitfield.imm8 = 1;
4200 i.types[op].bitfield.imm8s = 1;
4201 i.types[op].bitfield.imm16 = 1;
4202 i.types[op].bitfield.imm32 = 1;
4203 i.types[op].bitfield.imm32s = 1;
4204 i.types[op].bitfield.imm64 = 1;
29b0f896 4205 break;
252b5132 4206 }
252b5132 4207
29b0f896
AM		 4208 /* If this operand is at most 16 bits, convert it
4209 to a signed 16 bit number before trying to see
4210 whether it will fit in an even smaller size.
4211 This allows a 16-bit operand such as $0xffe0 to
4212 be recognised as within Imm8S range. */
40fb9820 4213 if ((i.types[op].bitfield.imm16)
29b0f896 4214 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4215 {
29b0f896
AM		 4216 i.op[op].imms->X_add_number =
4217 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4218 }
40fb9820 4219 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4220 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4221 == 0))
4222 {
4223 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4224 ^ ((offsetT) 1 << 31))
4225 - ((offsetT) 1 << 31));
4226 }
40fb9820 4227 i.types[op]
c6fb90c8
L		 4228 = operand_type_or (i.types[op],
4229 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4230
29b0f896
AM		 4231 /* We must avoid matching of Imm32 templates when 64bit
4232 only immediate is available. */
4233 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4234 i.types[op].bitfield.imm32 = 0;
29b0f896 4235 break;
252b5132 4236
29b0f896
AM		 4237 case O_absent:
4238 case O_register:
4239 abort ();
4240
4241 /* Symbols and expressions. */
4242 default:
9cd96992
JB		 4243 /* Convert symbolic operand to proper sizes for matching, but don't
4244 prevent matching a set of insns that only supports sizes other
4245 than those matching the insn suffix. */
4246 {
40fb9820 4247 i386_operand_type mask, allowed;
d3ce72d0 4248 const insn_template *t;
9cd96992 4249
0dfbf9d7
L		 4250 operand_type_set (&mask, 0);
4251 operand_type_set (&allowed, 0);
40fb9820 4252
4eed87de
AM		 4253 for (t = current_templates->start;
4254 t < current_templates->end;
4255 ++t)
c6fb90c8
L		 4256 allowed = operand_type_or (allowed,
4257 t->operand_types[op]);
9cd96992
JB		 4258 switch (guess_suffix)
4259 {
4260 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4261 mask.bitfield.imm64 = 1;
4262 mask.bitfield.imm32s = 1;
9cd96992
JB		 4263 break;
4264 case LONG_MNEM_SUFFIX:
40fb9820 4265 mask.bitfield.imm32 = 1;
9cd96992
JB		 4266 break;
4267 case WORD_MNEM_SUFFIX:
40fb9820 4268 mask.bitfield.imm16 = 1;
9cd96992
JB		 4269 break;
4270 case BYTE_MNEM_SUFFIX:
40fb9820 4271 mask.bitfield.imm8 = 1;
9cd96992
JB		 4272 break;
4273 default:
9cd96992
JB		 4274 break;
4275 }
c6fb90c8 4276 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4277 if (!operand_type_all_zero (&allowed))
c6fb90c8 4278 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4279 }
29b0f896 4280 break;
252b5132 4281 }
29b0f896
AM		 4282 }
4283}
47926f60 4284
29b0f896
AM		 4285/* Try to use the smallest displacement type too. */
4286static void
e3bb37b5 4287optimize_disp (void)
29b0f896
AM		 4288{
4289 int op;
3e73aa7c 4290
29b0f896 4291 for (op = i.operands; --op >= 0;)
40fb9820 4292 if (operand_type_check (i.types[op], disp))
252b5132 4293 {
b300c311 4294 if (i.op[op].disps->X_op == O_constant)
252b5132 4295 {
91d6fa6a 4296 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4297
40fb9820 4298 if (i.types[op].bitfield.disp16
91d6fa6a 4299 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4300 {
4301 /* If this operand is at most 16 bits, convert
4302 to a signed 16 bit number and don't use 64bit
4303 displacement. */
91d6fa6a 4304 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4305 i.types[op].bitfield.disp64 = 0;
b300c311 4306 }
40fb9820 4307 if (i.types[op].bitfield.disp32
91d6fa6a 4308 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4309 {
4310 /* If this operand is at most 32 bits, convert
4311 to a signed 32 bit number and don't use 64bit
4312 displacement. */
91d6fa6a
NC		 4313 op_disp &= (((offsetT) 2 << 31) - 1);
4314 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4315 i.types[op].bitfield.disp64 = 0;
b300c311 4316 }
91d6fa6a 4317 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4318 {
40fb9820
L		 4319 i.types[op].bitfield.disp8 = 0;
4320 i.types[op].bitfield.disp16 = 0;
4321 i.types[op].bitfield.disp32 = 0;
4322 i.types[op].bitfield.disp32s = 0;
4323 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4324 i.op[op].disps = 0;
4325 i.disp_operands--;
4326 }
4327 else if (flag_code == CODE_64BIT)
4328 {
91d6fa6a 4329 if (fits_in_signed_long (op_disp))
28a9d8f5 4330 {
40fb9820
L		 4331 i.types[op].bitfield.disp64 = 0;
4332 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4333 }
0e1147d9 4334 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4335 && fits_in_unsigned_long (op_disp))
40fb9820 4336 i.types[op].bitfield.disp32 = 1;
b300c311 4337 }
40fb9820
L		 4338 if ((i.types[op].bitfield.disp32
4339 || i.types[op].bitfield.disp32s
4340 || i.types[op].bitfield.disp16)
91d6fa6a 4341 && fits_in_signed_byte (op_disp))
40fb9820 4342 i.types[op].bitfield.disp8 = 1;
252b5132 4343 }
67a4f2b7
AO		 4344 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4345 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4346 {
4347 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4348 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4349 i.types[op].bitfield.disp8 = 0;
4350 i.types[op].bitfield.disp16 = 0;
4351 i.types[op].bitfield.disp32 = 0;
4352 i.types[op].bitfield.disp32s = 0;
4353 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4354 }
4355 else
b300c311 4356 /* We only support 64bit displacement on constants. */
40fb9820 4357 i.types[op].bitfield.disp64 = 0;
252b5132 4358 }
29b0f896
AM		 4359}
4360
6c30d220
L		 4361/* Check if operands are valid for the instruction. */
4362
4363static int
4364check_VecOperands (const insn_template *t)
4365{
43234a1e
L		 4366 unsigned int op;
4367
6c30d220
L		 4368 /* Without VSIB byte, we can't have a vector register for index. */
4369 if (!t->opcode_modifier.vecsib
4370 && i.index_reg
4371 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4372 || i.index_reg->reg_type.bitfield.regymm
4373 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4374 {
4375 i.error = unsupported_vector_index_register;
4376 return 1;
4377 }
4378
ad8ecc81
MZ		 4379 /* Check if default mask is allowed. */
4380 if (t->opcode_modifier.nodefmask
4381 && (!i.mask || i.mask->mask->reg_num == 0))
4382 {
4383 i.error = no_default_mask;
4384 return 1;
4385 }
4386
7bab8ab5
JB		 4387 /* For VSIB byte, we need a vector register for index, and all vector
4388 registers must be distinct. */
4389 if (t->opcode_modifier.vecsib)
4390 {
4391 if (!i.index_reg
6c30d220
L		 4392 || !((t->opcode_modifier.vecsib == VecSIB128
4393 && i.index_reg->reg_type.bitfield.regxmm)
4394 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4395 && i.index_reg->reg_type.bitfield.regymm)
4396 || (t->opcode_modifier.vecsib == VecSIB512
4397 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4398 {
4399 i.error = invalid_vsib_address;
4400 return 1;
4401 }
4402
43234a1e
L		 4403 gas_assert (i.reg_operands == 2 || i.mask);
4404 if (i.reg_operands == 2 && !i.mask)
4405 {
4406 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4407 || i.types[0].bitfield.regymm);
43234a1e 4408 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4409 || i.types[2].bitfield.regymm);
43234a1e
L		 4410 if (operand_check == check_none)
4411 return 0;
4412 if (register_number (i.op[0].regs)
4413 != register_number (i.index_reg)
4414 && register_number (i.op[2].regs)
4415 != register_number (i.index_reg)
4416 && register_number (i.op[0].regs)
4417 != register_number (i.op[2].regs))
4418 return 0;
4419 if (operand_check == check_error)
4420 {
4421 i.error = invalid_vector_register_set;
4422 return 1;
4423 }
4424 as_warn (_("mask, index, and destination registers should be distinct"));
4425 }
8444f82a
MZ		 4426 else if (i.reg_operands == 1 && i.mask)
4427 {
4428 if ((i.types[1].bitfield.regymm
4429 || i.types[1].bitfield.regzmm)
4430 && (register_number (i.op[1].regs)
4431 == register_number (i.index_reg)))
4432 {
4433 if (operand_check == check_error)
4434 {
4435 i.error = invalid_vector_register_set;
4436 return 1;
4437 }
4438 if (operand_check != check_none)
4439 as_warn (_("index and destination registers should be distinct"));
4440 }
4441 }
43234a1e 4442 }
7bab8ab5 4443
43234a1e
L		 4444 /* Check if broadcast is supported by the instruction and is applied
4445 to the memory operand. */
4446 if (i.broadcast)
4447 {
4448 int broadcasted_opnd_size;
4449
4450 /* Check if specified broadcast is supported in this instruction,
4451 and it's applied to memory operand of DWORD or QWORD type,
4452 depending on VecESize. */
4453 if (i.broadcast->type != t->opcode_modifier.broadcast
4454 || !i.types[i.broadcast->operand].bitfield.mem
4455 || (t->opcode_modifier.vecesize == 0
4456 && !i.types[i.broadcast->operand].bitfield.dword
4457 && !i.types[i.broadcast->operand].bitfield.unspecified)
4458 || (t->opcode_modifier.vecesize == 1
4459 && !i.types[i.broadcast->operand].bitfield.qword
4460 && !i.types[i.broadcast->operand].bitfield.unspecified))
4461 goto bad_broadcast;
4462
4463 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4464 if (i.broadcast->type == BROADCAST_1TO16)
4465 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4466 else if (i.broadcast->type == BROADCAST_1TO8)
4467 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4468 else if (i.broadcast->type == BROADCAST_1TO4)
4469 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4470 else if (i.broadcast->type == BROADCAST_1TO2)
4471 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4472 else
4473 goto bad_broadcast;
4474
4475 if ((broadcasted_opnd_size == 256
4476 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4477 || (broadcasted_opnd_size == 512
4478 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4479 {
4480 bad_broadcast:
4481 i.error = unsupported_broadcast;
4482 return 1;
4483 }
4484 }
4485 /* If broadcast is supported in this instruction, we need to check if
4486 operand of one-element size isn't specified without broadcast. */
4487 else if (t->opcode_modifier.broadcast && i.mem_operands)
4488 {
4489 /* Find memory operand. */
4490 for (op = 0; op < i.operands; op++)
4491 if (operand_type_check (i.types[op], anymem))
4492 break;
4493 gas_assert (op < i.operands);
4494 /* Check size of the memory operand. */
4495 if ((t->opcode_modifier.vecesize == 0
4496 && i.types[op].bitfield.dword)
4497 || (t->opcode_modifier.vecesize == 1
4498 && i.types[op].bitfield.qword))
4499 {
4500 i.error = broadcast_needed;
4501 return 1;
4502 }
4503 }
4504
4505 /* Check if requested masking is supported. */
4506 if (i.mask
4507 && (!t->opcode_modifier.masking
4508 || (i.mask->zeroing
4509 && t->opcode_modifier.masking == MERGING_MASKING)))
4510 {
4511 i.error = unsupported_masking;
4512 return 1;
4513 }
4514
4515 /* Check if masking is applied to dest operand. */
4516 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4517 {
4518 i.error = mask_not_on_destination;
4519 return 1;
4520 }
4521
43234a1e
L		 4522 /* Check RC/SAE. */
4523 if (i.rounding)
4524 {
4525 if ((i.rounding->type != saeonly
4526 && !t->opcode_modifier.staticrounding)
4527 || (i.rounding->type == saeonly
4528 && (t->opcode_modifier.staticrounding
4529 || !t->opcode_modifier.sae)))
4530 {
4531 i.error = unsupported_rc_sae;
4532 return 1;
4533 }
4534 /* If the instruction has several immediate operands and one of
4535 them is rounding, the rounding operand should be the last
4536 immediate operand. */
4537 if (i.imm_operands > 1
4538 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4539 {
43234a1e 4540 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4541 return 1;
4542 }
6c30d220
L		 4543 }
4544
43234a1e
L		 4545 /* Check vector Disp8 operand. */
4546 if (t->opcode_modifier.disp8memshift)
4547 {
4548 if (i.broadcast)
4549 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4550 else
4551 i.memshift = t->opcode_modifier.disp8memshift;
4552
4553 for (op = 0; op < i.operands; op++)
4554 if (operand_type_check (i.types[op], disp)
4555 && i.op[op].disps->X_op == O_constant)
4556 {
4557 offsetT value = i.op[op].disps->X_add_number;
4558 int vec_disp8_ok = fits_in_vec_disp8 (value);
4559 if (t->operand_types [op].bitfield.vec_disp8)
4560 {
4561 if (vec_disp8_ok)
4562 i.types[op].bitfield.vec_disp8 = 1;
4563 else
4564 {
4565 /* Vector insn can only have Vec_Disp8/Disp32 in
4566 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4567 mode. */
4568 i.types[op].bitfield.disp8 = 0;
4569 if (flag_code != CODE_16BIT)
4570 i.types[op].bitfield.disp16 = 0;
4571 }
4572 }
4573 else if (flag_code != CODE_16BIT)
4574 {
4575 /* One form of this instruction supports vector Disp8.
4576 Try vector Disp8 if we need to use Disp32. */
4577 if (vec_disp8_ok && !fits_in_signed_byte (value))
4578 {
4579 i.error = try_vector_disp8;
4580 return 1;
4581 }
4582 }
4583 }
4584 }
4585 else
4586 i.memshift = -1;
4587
6c30d220
L		 4588 return 0;
4589}
4590
43f3e2ee 4591/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4592 operand types. */
4593
4594static int
4595VEX_check_operands (const insn_template *t)
4596{
43234a1e
L		 4597 /* VREX is only valid with EVEX prefix. */
4598 if (i.need_vrex && !t->opcode_modifier.evex)
4599 {
4600 i.error = invalid_register_operand;
4601 return 1;
4602 }
4603
a683cc34
SP		 4604 if (!t->opcode_modifier.vex)
4605 return 0;
4606
4607 /* Only check VEX_Imm4, which must be the first operand. */
4608 if (t->operand_types[0].bitfield.vec_imm4)
4609 {
4610 if (i.op[0].imms->X_op != O_constant
4611 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4612 {
a65babc9 4613 i.error = bad_imm4;
891edac4
L		 4614 return 1;
4615 }
a683cc34
SP		 4616
4617 /* Turn off Imm8 so that update_imm won't complain. */
4618 i.types[0] = vec_imm4;
4619 }
4620
4621 return 0;
4622}
4623
d3ce72d0 4624static const insn_template *
e3bb37b5 4625match_template (void)
29b0f896
AM		 4626{
4627 /* Points to template once we've found it. */
d3ce72d0 4628 const insn_template *t;
40fb9820 4629 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4630 i386_operand_type overlap4;
29b0f896 4631 unsigned int found_reverse_match;
40fb9820
L		 4632 i386_opcode_modifier suffix_check;
4633 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4634 int addr_prefix_disp;
a5c311ca 4635 unsigned int j;
3629bb00 4636 unsigned int found_cpu_match;
45664ddb 4637 unsigned int check_register;
5614d22c 4638 enum i386_error specific_error = 0;
29b0f896 4639
c0f3af97
L		 4640#if MAX_OPERANDS != 5
4641# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4642#endif
4643
29b0f896 4644 found_reverse_match = 0;
539e75ad 4645 addr_prefix_disp = -1;
40fb9820
L		 4646
4647 memset (&suffix_check, 0, sizeof (suffix_check));
4648 if (i.suffix == BYTE_MNEM_SUFFIX)
4649 suffix_check.no_bsuf = 1;
4650 else if (i.suffix == WORD_MNEM_SUFFIX)
4651 suffix_check.no_wsuf = 1;
4652 else if (i.suffix == SHORT_MNEM_SUFFIX)
4653 suffix_check.no_ssuf = 1;
4654 else if (i.suffix == LONG_MNEM_SUFFIX)
4655 suffix_check.no_lsuf = 1;
4656 else if (i.suffix == QWORD_MNEM_SUFFIX)
4657 suffix_check.no_qsuf = 1;
4658 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4659 suffix_check.no_ldsuf = 1;
29b0f896 4660
01559ecc
L		 4661 /* Must have right number of operands. */
4662 i.error = number_of_operands_mismatch;
4663
45aa61fe 4664 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4665 {
539e75ad
L		 4666 addr_prefix_disp = -1;
4667
29b0f896
AM		 4668 if (i.operands != t->operands)
4669 continue;
4670
50aecf8c 4671 /* Check processor support. */
a65babc9 4672 i.error = unsupported;
c0f3af97
L		 4673 found_cpu_match = (cpu_flags_match (t)
4674 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4675 if (!found_cpu_match)
4676 continue;
4677
e1d4d893 4678 /* Check old gcc support. */
a65babc9 4679 i.error = old_gcc_only;
e1d4d893
L		 4680 if (!old_gcc && t->opcode_modifier.oldgcc)
4681 continue;
4682
4683 /* Check AT&T mnemonic. */
a65babc9 4684 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4685 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4686 continue;
4687
891edac4 4688 /* Check AT&T/Intel syntax. */
a65babc9 4689 i.error = unsupported_syntax;
5c07affc
L		 4690 if ((intel_syntax && t->opcode_modifier.attsyntax)
4691 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4692 continue;
4693
20592a94 4694 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4695 i.error = invalid_instruction_suffix;
567e4e96
L		 4696 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4697 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4698 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4699 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4700 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4701 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4702 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4703 continue;
4704
5c07affc 4705 if (!operand_size_match (t))
7d5e4556 4706 continue;
539e75ad 4707
5c07affc
L		 4708 for (j = 0; j < MAX_OPERANDS; j++)
4709 operand_types[j] = t->operand_types[j];
4710
45aa61fe
AM		 4711 /* In general, don't allow 64-bit operands in 32-bit mode. */
4712 if (i.suffix == QWORD_MNEM_SUFFIX
4713 && flag_code != CODE_64BIT
4714 && (intel_syntax
40fb9820 4715 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4716 && !intel_float_operand (t->name))
4717 : intel_float_operand (t->name) != 2)
40fb9820 4718 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4719 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4720 && !operand_types[0].bitfield.regymm
4721 && !operand_types[0].bitfield.regzmm)
40fb9820 4722 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4723 && operand_types[t->operands > 1].bitfield.regxmm
4724 && operand_types[t->operands > 1].bitfield.regymm
4725 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4726 && (t->base_opcode != 0x0fc7
4727 || t->extension_opcode != 1 /* cmpxchg8b */))
4728 continue;
4729
192dc9c6
JB		 4730 /* In general, don't allow 32-bit operands on pre-386. */
4731 else if (i.suffix == LONG_MNEM_SUFFIX
4732 && !cpu_arch_flags.bitfield.cpui386
4733 && (intel_syntax
4734 ? (!t->opcode_modifier.ignoresize
4735 && !intel_float_operand (t->name))
4736 : intel_float_operand (t->name) != 2)
4737 && ((!operand_types[0].bitfield.regmmx
4738 && !operand_types[0].bitfield.regxmm)
4739 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4740 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4741 continue;
4742
29b0f896 4743 /* Do not verify operands when there are none. */
50aecf8c 4744 else
29b0f896 4745 {
c6fb90c8 4746 if (!t->operands)
2dbab7d5
L		 4747 /* We've found a match; break out of loop. */
4748 break;
29b0f896 4749 }
252b5132 4750
539e75ad
L		 4751 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4752 into Disp32/Disp16/Disp32 operand. */
4753 if (i.prefix[ADDR_PREFIX] != 0)
4754 {
40fb9820 4755 /* There should be only one Disp operand. */
539e75ad
L		 4756 switch (flag_code)
4757 {
4758 case CODE_16BIT:
40fb9820
L		 4759 for (j = 0; j < MAX_OPERANDS; j++)
4760 {
4761 if (operand_types[j].bitfield.disp16)
4762 {
4763 addr_prefix_disp = j;
4764 operand_types[j].bitfield.disp32 = 1;
4765 operand_types[j].bitfield.disp16 = 0;
4766 break;
4767 }
4768 }
539e75ad
L		 4769 break;
4770 case CODE_32BIT:
40fb9820
L		 4771 for (j = 0; j < MAX_OPERANDS; j++)
4772 {
4773 if (operand_types[j].bitfield.disp32)
4774 {
4775 addr_prefix_disp = j;
4776 operand_types[j].bitfield.disp32 = 0;
4777 operand_types[j].bitfield.disp16 = 1;
4778 break;
4779 }
4780 }
539e75ad
L		 4781 break;
4782 case CODE_64BIT:
40fb9820
L		 4783 for (j = 0; j < MAX_OPERANDS; j++)
4784 {
4785 if (operand_types[j].bitfield.disp64)
4786 {
4787 addr_prefix_disp = j;
4788 operand_types[j].bitfield.disp64 = 0;
4789 operand_types[j].bitfield.disp32 = 1;
4790 break;
4791 }
4792 }
539e75ad
L		 4793 break;
4794 }
539e75ad
L		 4795 }
4796
02a86693
L		 4797 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4798 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4799 continue;
4800
56ffb741
L		 4801 /* We check register size if needed. */
4802 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4803 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4804 switch (t->operands)
4805 {
4806 case 1:
40fb9820 4807 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4808 continue;
4809 break;
4810 case 2:
8b38ad71
L		 4811 /* xchg %eax, %eax is a special case. It is an aliase for nop
4812 only in 32bit mode and we can use opcode 0x90. In 64bit
4813 mode, we can't use 0x90 for xchg %eax, %eax since it should
4814 zero-extend %eax to %rax. */
4815 if (flag_code == CODE_64BIT
4816 && t->base_opcode == 0x90
0dfbf9d7
L		 4817 && operand_type_equal (&i.types [0], &acc32)
4818 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4819 continue;
b6169b20
L		 4820 if (i.swap_operand)
4821 {
4822 /* If we swap operand in encoding, we either match
4823 the next one or reverse direction of operands. */
4824 if (t->opcode_modifier.s)
4825 continue;
4826 else if (t->opcode_modifier.d)
4827 goto check_reverse;
4828 }
4829
29b0f896 4830 case 3:
fa99fab2
L		 4831 /* If we swap operand in encoding, we match the next one. */
4832 if (i.swap_operand && t->opcode_modifier.s)
4833 continue;
f48ff2ae 4834 case 4:
c0f3af97 4835 case 5:
c6fb90c8 4836 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4837 if (!operand_type_match (overlap0, i.types[0])
4838 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4839 || (check_register
4840 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4841 operand_types[0],
4842 overlap1, i.types[1],
4843 operand_types[1])))
29b0f896
AM		 4844 {
4845 /* Check if other direction is valid ... */
40fb9820 4846 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4847 continue;
4848
b6169b20 4849check_reverse:
29b0f896 4850 /* Try reversing direction of operands. */
c6fb90c8
L		 4851 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4852 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4853 if (!operand_type_match (overlap0, i.types[0])
4854 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4855 || (check_register
4856 && !operand_type_register_match (overlap0,
4857 i.types[0],
4858 operand_types[1],
4859 overlap1,
4860 i.types[1],
4861 operand_types[0])))
29b0f896
AM		 4862 {
4863 /* Does not match either direction. */
4864 continue;
4865 }
4866 /* found_reverse_match holds which of D or FloatDR
4867 we've found. */
40fb9820 4868 if (t->opcode_modifier.d)
8a2ed489 4869 found_reverse_match = Opcode_D;
40fb9820 4870 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4871 found_reverse_match = Opcode_FloatD;
4872 else
4873 found_reverse_match = 0;
40fb9820 4874 if (t->opcode_modifier.floatr)
8a2ed489 4875 found_reverse_match |= Opcode_FloatR;
29b0f896 4876 }
f48ff2ae 4877 else
29b0f896 4878 {
f48ff2ae 4879 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4880 switch (t->operands)
4881 {
c0f3af97
L		 4882 case 5:
4883 overlap4 = operand_type_and (i.types[4],
4884 operand_types[4]);
d1cbb4db 4885 case 4:
c6fb90c8
L		 4886 overlap3 = operand_type_and (i.types[3],
4887 operand_types[3]);
d1cbb4db 4888 case 3:
c6fb90c8
L		 4889 overlap2 = operand_type_and (i.types[2],
4890 operand_types[2]);
d1cbb4db
L		 4891 break;
4892 }
29b0f896 4893
f48ff2ae
L		 4894 switch (t->operands)
4895 {
c0f3af97
L		 4896 case 5:
4897 if (!operand_type_match (overlap4, i.types[4])
4898 || !operand_type_register_match (overlap3,
4899 i.types[3],
4900 operand_types[3],
4901 overlap4,
4902 i.types[4],
4903 operand_types[4]))
4904 continue;
f48ff2ae 4905 case 4:
40fb9820 4906 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4907 || (check_register
4908 && !operand_type_register_match (overlap2,
4909 i.types[2],
4910 operand_types[2],
4911 overlap3,
4912 i.types[3],
4913 operand_types[3])))
f48ff2ae
L		 4914 continue;
4915 case 3:
4916 /* Here we make use of the fact that there are no
4917 reverse match 3 operand instructions, and all 3
4918 operand instructions only need to be checked for
4919 register consistency between operands 2 and 3. */
40fb9820 4920 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4921 || (check_register
4922 && !operand_type_register_match (overlap1,
4923 i.types[1],
4924 operand_types[1],
4925 overlap2,
4926 i.types[2],
4927 operand_types[2])))
f48ff2ae
L		 4928 continue;
4929 break;
4930 }
29b0f896 4931 }
f48ff2ae 4932 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4933 slip through to break. */
4934 }
3629bb00 4935 if (!found_cpu_match)
29b0f896
AM		 4936 {
4937 found_reverse_match = 0;
4938 continue;
4939 }
c0f3af97 4940
5614d22c
JB		 4941 /* Check if vector and VEX operands are valid. */
4942 if (check_VecOperands (t) || VEX_check_operands (t))
4943 {
4944 specific_error = i.error;
4945 continue;
4946 }
a683cc34 4947
29b0f896
AM		 4948 /* We've found a match; break out of loop. */
4949 break;
4950 }
4951
4952 if (t == current_templates->end)
4953 {
4954 /* We found no match. */
a65babc9 4955 const char *err_msg;
5614d22c 4956 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4957 {
4958 default:
4959 abort ();
86e026a4 4960 case operand_size_mismatch:
a65babc9
L		 4961 err_msg = _("operand size mismatch");
4962 break;
4963 case operand_type_mismatch:
4964 err_msg = _("operand type mismatch");
4965 break;
4966 case register_type_mismatch:
4967 err_msg = _("register type mismatch");
4968 break;
4969 case number_of_operands_mismatch:
4970 err_msg = _("number of operands mismatch");
4971 break;
4972 case invalid_instruction_suffix:
4973 err_msg = _("invalid instruction suffix");
4974 break;
4975 case bad_imm4:
4a2608e3 4976 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4977 break;
4978 case old_gcc_only:
4979 err_msg = _("only supported with old gcc");
4980 break;
4981 case unsupported_with_intel_mnemonic:
4982 err_msg = _("unsupported with Intel mnemonic");
4983 break;
4984 case unsupported_syntax:
4985 err_msg = _("unsupported syntax");
4986 break;
4987 case unsupported:
35262a23 4988 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4989 current_templates->start->name);
4990 return NULL;
6c30d220
L		 4991 case invalid_vsib_address:
4992 err_msg = _("invalid VSIB address");
4993 break;
7bab8ab5
JB		 4994 case invalid_vector_register_set:
4995 err_msg = _("mask, index, and destination registers must be distinct");
4996 break;
6c30d220
L		 4997 case unsupported_vector_index_register:
4998 err_msg = _("unsupported vector index register");
4999 break;
43234a1e
L		 5000 case unsupported_broadcast:
5001 err_msg = _("unsupported broadcast");
5002 break;
5003 case broadcast_not_on_src_operand:
5004 err_msg = _("broadcast not on source memory operand");
5005 break;
5006 case broadcast_needed:
5007 err_msg = _("broadcast is needed for operand of such type");
5008 break;
5009 case unsupported_masking:
5010 err_msg = _("unsupported masking");
5011 break;
5012 case mask_not_on_destination:
5013 err_msg = _("mask not on destination operand");
5014 break;
5015 case no_default_mask:
5016 err_msg = _("default mask isn't allowed");
5017 break;
5018 case unsupported_rc_sae:
5019 err_msg = _("unsupported static rounding/sae");
5020 break;
5021 case rc_sae_operand_not_last_imm:
5022 if (intel_syntax)
5023 err_msg = _("RC/SAE operand must precede immediate operands");
5024 else
5025 err_msg = _("RC/SAE operand must follow immediate operands");
5026 break;
5027 case invalid_register_operand:
5028 err_msg = _("invalid register operand");
5029 break;
a65babc9
L		 5030 }
5031 as_bad (_("%s for `%s'"), err_msg,
891edac4 5032 current_templates->start->name);
fa99fab2 5033 return NULL;
29b0f896 5034 }
252b5132 5035
29b0f896
AM		 5036 if (!quiet_warnings)
5037 {
5038 if (!intel_syntax
40fb9820
L		 5039 && (i.types[0].bitfield.jumpabsolute
5040 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5041 {
5042 as_warn (_("indirect %s without `*'"), t->name);
5043 }
5044
40fb9820
L		 5045 if (t->opcode_modifier.isprefix
5046 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5047 {
5048 /* Warn them that a data or address size prefix doesn't
5049 affect assembly of the next line of code. */
5050 as_warn (_("stand-alone `%s' prefix"), t->name);
5051 }
5052 }
5053
5054 /* Copy the template we found. */
5055 i.tm = *t;
539e75ad
L		 5056
5057 if (addr_prefix_disp != -1)
5058 i.tm.operand_types[addr_prefix_disp]
5059 = operand_types[addr_prefix_disp];
5060
29b0f896
AM		 5061 if (found_reverse_match)
5062 {
5063 /* If we found a reverse match we must alter the opcode
5064 direction bit. found_reverse_match holds bits to change
5065 (different for int & float insns). */
5066
5067 i.tm.base_opcode ^= found_reverse_match;
5068
539e75ad
L		 5069 i.tm.operand_types[0] = operand_types[1];
5070 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5071 }
5072
fa99fab2 5073 return t;
29b0f896
AM		 5074}
5075
5076static int
e3bb37b5 5077check_string (void)
29b0f896 5078{
40fb9820
L		 5079 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5080 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5081 {
5082 if (i.seg[0] != NULL && i.seg[0] != &es)
5083 {
a87af027 5084 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5085 i.tm.name,
a87af027
JB		 5086 mem_op + 1,
5087 register_prefix);
29b0f896
AM		 5088 return 0;
5089 }
5090 /* There's only ever one segment override allowed per instruction.
5091 This instruction possibly has a legal segment override on the
5092 second operand, so copy the segment to where non-string
5093 instructions store it, allowing common code. */
5094 i.seg[0] = i.seg[1];
5095 }
40fb9820 5096 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5097 {
5098 if (i.seg[1] != NULL && i.seg[1] != &es)
5099 {
a87af027 5100 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5101 i.tm.name,
a87af027
JB		 5102 mem_op + 2,
5103 register_prefix);
29b0f896
AM		 5104 return 0;
5105 }
5106 }
5107 return 1;
5108}
5109
5110static int
543613e9 5111process_suffix (void)
29b0f896
AM		 5112{
5113 /* If matched instruction specifies an explicit instruction mnemonic
5114 suffix, use it. */
40fb9820
L		 5115 if (i.tm.opcode_modifier.size16)
5116 i.suffix = WORD_MNEM_SUFFIX;
5117 else if (i.tm.opcode_modifier.size32)
5118 i.suffix = LONG_MNEM_SUFFIX;
5119 else if (i.tm.opcode_modifier.size64)
5120 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5121 else if (i.reg_operands)
5122 {
5123 /* If there's no instruction mnemonic suffix we try to invent one
5124 based on register operands. */
5125 if (!i.suffix)
5126 {
5127 /* We take i.suffix from the last register operand specified,
5128 Destination register type is more significant than source
381d071f
L		 5129 register type. crc32 in SSE4.2 prefers source register
5130 type. */
5131 if (i.tm.base_opcode == 0xf20f38f1)
5132 {
40fb9820
L		 5133 if (i.types[0].bitfield.reg16)
5134 i.suffix = WORD_MNEM_SUFFIX;
5135 else if (i.types[0].bitfield.reg32)
5136 i.suffix = LONG_MNEM_SUFFIX;
5137 else if (i.types[0].bitfield.reg64)
5138 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5139 }
9344ff29 5140 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5141 {
40fb9820 5142 if (i.types[0].bitfield.reg8)
20592a94
L		 5143 i.suffix = BYTE_MNEM_SUFFIX;
5144 }
381d071f
L		 5145
5146 if (!i.suffix)
5147 {
5148 int op;
5149
20592a94
L		 5150 if (i.tm.base_opcode == 0xf20f38f1
5151 || i.tm.base_opcode == 0xf20f38f0)
5152 {
5153 /* We have to know the operand size for crc32. */
5154 as_bad (_("ambiguous memory operand size for `%s`"),
5155 i.tm.name);
5156 return 0;
5157 }
5158
381d071f 5159 for (op = i.operands; --op >= 0;)
40fb9820 5160 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5161 {
40fb9820
L		 5162 if (i.types[op].bitfield.reg8)
5163 {
5164 i.suffix = BYTE_MNEM_SUFFIX;
5165 break;
5166 }
5167 else if (i.types[op].bitfield.reg16)
5168 {
5169 i.suffix = WORD_MNEM_SUFFIX;
5170 break;
5171 }
5172 else if (i.types[op].bitfield.reg32)
5173 {
5174 i.suffix = LONG_MNEM_SUFFIX;
5175 break;
5176 }
5177 else if (i.types[op].bitfield.reg64)
5178 {
5179 i.suffix = QWORD_MNEM_SUFFIX;
5180 break;
5181 }
381d071f
L		 5182 }
5183 }
29b0f896
AM		 5184 }
5185 else if (i.suffix == BYTE_MNEM_SUFFIX)
5186 {
2eb952a4
L		 5187 if (intel_syntax
5188 && i.tm.opcode_modifier.ignoresize
5189 && i.tm.opcode_modifier.no_bsuf)
5190 i.suffix = 0;
5191 else if (!check_byte_reg ())
29b0f896
AM		 5192 return 0;
5193 }
5194 else if (i.suffix == LONG_MNEM_SUFFIX)
5195 {
2eb952a4
L		 5196 if (intel_syntax
5197 && i.tm.opcode_modifier.ignoresize
5198 && i.tm.opcode_modifier.no_lsuf)
5199 i.suffix = 0;
5200 else if (!check_long_reg ())
29b0f896
AM		 5201 return 0;
5202 }
5203 else if (i.suffix == QWORD_MNEM_SUFFIX)
5204 {
955e1e6a
L		 5205 if (intel_syntax
5206 && i.tm.opcode_modifier.ignoresize
5207 && i.tm.opcode_modifier.no_qsuf)
5208 i.suffix = 0;
5209 else if (!check_qword_reg ())
29b0f896
AM		 5210 return 0;
5211 }
5212 else if (i.suffix == WORD_MNEM_SUFFIX)
5213 {
2eb952a4
L		 5214 if (intel_syntax
5215 && i.tm.opcode_modifier.ignoresize
5216 && i.tm.opcode_modifier.no_wsuf)
5217 i.suffix = 0;
5218 else if (!check_word_reg ())
29b0f896
AM		 5219 return 0;
5220 }
c0f3af97 5221 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5222 || i.suffix == YMMWORD_MNEM_SUFFIX
5223 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5224 {
43234a1e 5225 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5226 should check if it is a valid suffix. */
5227 }
40fb9820 5228 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5229 /* Do nothing if the instruction is going to ignore the prefix. */
5230 ;
5231 else
5232 abort ();
5233 }
40fb9820 5234 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5235 && !i.suffix
5236 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5237 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5238 {
5239 i.suffix = stackop_size;
5240 }
9306ca4a
JB		 5241 else if (intel_syntax
5242 && !i.suffix
40fb9820
L		 5243 && (i.tm.operand_types[0].bitfield.jumpabsolute
5244 || i.tm.opcode_modifier.jumpbyte
5245 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5246 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5247 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5248 {
5249 switch (flag_code)
5250 {
5251 case CODE_64BIT:
40fb9820 5252 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5253 {
5254 i.suffix = QWORD_MNEM_SUFFIX;
5255 break;
5256 }
5257 case CODE_32BIT:
40fb9820 5258 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5259 i.suffix = LONG_MNEM_SUFFIX;
5260 break;
5261 case CODE_16BIT:
40fb9820 5262 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5263 i.suffix = WORD_MNEM_SUFFIX;
5264 break;
5265 }
5266 }
252b5132 5267
9306ca4a 5268 if (!i.suffix)
29b0f896 5269 {
9306ca4a
JB		 5270 if (!intel_syntax)
5271 {
40fb9820 5272 if (i.tm.opcode_modifier.w)
9306ca4a 5273 {
4eed87de
AM		 5274 as_bad (_("no instruction mnemonic suffix given and "
5275 "no register operands; can't size instruction"));
9306ca4a
JB		 5276 return 0;
5277 }
5278 }
5279 else
5280 {
40fb9820 5281 unsigned int suffixes;
7ab9ffdd 5282
40fb9820
L		 5283 suffixes = !i.tm.opcode_modifier.no_bsuf;
5284 if (!i.tm.opcode_modifier.no_wsuf)
5285 suffixes |= 1 << 1;
5286 if (!i.tm.opcode_modifier.no_lsuf)
5287 suffixes |= 1 << 2;
fc4adea1 5288 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5289 suffixes |= 1 << 3;
5290 if (!i.tm.opcode_modifier.no_ssuf)
5291 suffixes |= 1 << 4;
5292 if (!i.tm.opcode_modifier.no_qsuf)
5293 suffixes |= 1 << 5;
5294
5295 /* There are more than suffix matches. */
5296 if (i.tm.opcode_modifier.w
9306ca4a 5297 || ((suffixes & (suffixes - 1))
40fb9820
L		 5298 && !i.tm.opcode_modifier.defaultsize
5299 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5300 {
5301 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5302 return 0;
5303 }
5304 }
29b0f896 5305 }
252b5132 5306
9306ca4a
JB		 5307 /* Change the opcode based on the operand size given by i.suffix;
5308 We don't need to change things for byte insns. */
5309
582d5edd
L		 5310 if (i.suffix
5311 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5312 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5313 && i.suffix != YMMWORD_MNEM_SUFFIX
5314 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5315 {
5316 /* It's not a byte, select word/dword operation. */
40fb9820 5317 if (i.tm.opcode_modifier.w)
29b0f896 5318 {
40fb9820 5319 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5320 i.tm.base_opcode |= 8;
5321 else
5322 i.tm.base_opcode |= 1;
5323 }
0f3f3d8b 5324
29b0f896
AM		 5325 /* Now select between word & dword operations via the operand
5326 size prefix, except for instructions that will ignore this
5327 prefix anyway. */
ca61edf2 5328 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5329 {
ca61edf2
L		 5330 /* The address size override prefix changes the size of the
5331 first operand. */
40fb9820
L		 5332 if ((flag_code == CODE_32BIT
5333 && i.op->regs[0].reg_type.bitfield.reg16)
5334 || (flag_code != CODE_32BIT
5335 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5336 if (!add_prefix (ADDR_PREFIX_OPCODE))
5337 return 0;
5338 }
5339 else if (i.suffix != QWORD_MNEM_SUFFIX
5340 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5341 && !i.tm.opcode_modifier.ignoresize
5342 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5343 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5344 || (flag_code == CODE_64BIT
40fb9820 5345 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5346 {
5347 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5348
40fb9820 5349 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5350 prefix = ADDR_PREFIX_OPCODE;
252b5132 5351
29b0f896
AM		 5352 if (!add_prefix (prefix))
5353 return 0;
24eab124 5354 }
252b5132 5355
29b0f896
AM		 5356 /* Set mode64 for an operand. */
5357 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5358 && flag_code == CODE_64BIT
40fb9820 5359 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5360 {
5361 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5362 need rex64. cmpxchg8b is also a special case. */
5363 if (! (i.operands == 2
5364 && i.tm.base_opcode == 0x90
5365 && i.tm.extension_opcode == None
0dfbf9d7
L		 5366 && operand_type_equal (&i.types [0], &acc64)
5367 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5368 && ! (i.operands == 1
5369 && i.tm.base_opcode == 0xfc7
5370 && i.tm.extension_opcode == 1
40fb9820
L		 5371 && !operand_type_check (i.types [0], reg)
5372 && operand_type_check (i.types [0], anymem)))
f6bee062 5373 i.rex |= REX_W;
46e883c5 5374 }
3e73aa7c 5375
29b0f896
AM		 5376 /* Size floating point instruction. */
5377 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5378 if (i.tm.opcode_modifier.floatmf)
543613e9 5379 i.tm.base_opcode ^= 4;
29b0f896 5380 }
7ecd2f8b 5381
29b0f896
AM		 5382 return 1;
5383}
3e73aa7c 5384
29b0f896 5385static int
543613e9 5386check_byte_reg (void)
29b0f896
AM		 5387{
5388 int op;
543613e9 5389
29b0f896
AM		 5390 for (op = i.operands; --op >= 0;)
5391 {
5392 /* If this is an eight bit register, it's OK. If it's the 16 or
5393 32 bit version of an eight bit register, we will just use the
5394 low portion, and that's OK too. */
40fb9820 5395 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5396 continue;
5397
5a819eb9
JB		 5398 /* I/O port address operands are OK too. */
5399 if (i.tm.operand_types[op].bitfield.inoutportreg)
5400 continue;
5401
9344ff29
L		 5402 /* crc32 doesn't generate this warning. */
5403 if (i.tm.base_opcode == 0xf20f38f0)
5404 continue;
5405
40fb9820
L		 5406 if ((i.types[op].bitfield.reg16
5407 || i.types[op].bitfield.reg32
5408 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5409 && i.op[op].regs->reg_num < 4
5410 /* Prohibit these changes in 64bit mode, since the lowering
5411 would be more complicated. */
5412 && flag_code != CODE_64BIT)
29b0f896 5413 {
29b0f896 5414#if REGISTER_WARNINGS
5a819eb9 5415 if (!quiet_warnings)
a540244d
L		 5416 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5417 register_prefix,
40fb9820 5418 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5419 ? REGNAM_AL - REGNAM_AX
5420 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5421 register_prefix,
29b0f896
AM		 5422 i.op[op].regs->reg_name,
5423 i.suffix);
5424#endif
5425 continue;
5426 }
5427 /* Any other register is bad. */
40fb9820
L		 5428 if (i.types[op].bitfield.reg16
5429 || i.types[op].bitfield.reg32
5430 || i.types[op].bitfield.reg64
5431 || i.types[op].bitfield.regmmx
5432 || i.types[op].bitfield.regxmm
c0f3af97 5433 || i.types[op].bitfield.regymm
43234a1e 5434 || i.types[op].bitfield.regzmm
40fb9820
L		 5435 || i.types[op].bitfield.sreg2
5436 || i.types[op].bitfield.sreg3
5437 || i.types[op].bitfield.control
5438 || i.types[op].bitfield.debug
5439 || i.types[op].bitfield.test
5440 || i.types[op].bitfield.floatreg
5441 || i.types[op].bitfield.floatacc)
29b0f896 5442 {
a540244d
L		 5443 as_bad (_("`%s%s' not allowed with `%s%c'"),
5444 register_prefix,
29b0f896
AM		 5445 i.op[op].regs->reg_name,
5446 i.tm.name,
5447 i.suffix);
5448 return 0;
5449 }
5450 }
5451 return 1;
5452}
5453
5454static int
e3bb37b5 5455check_long_reg (void)
29b0f896
AM		 5456{
5457 int op;
5458
5459 for (op = i.operands; --op >= 0;)
5460 /* Reject eight bit registers, except where the template requires
5461 them. (eg. movzb) */
40fb9820
L		 5462 if (i.types[op].bitfield.reg8
5463 && (i.tm.operand_types[op].bitfield.reg16
5464 || i.tm.operand_types[op].bitfield.reg32
5465 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5466 {
a540244d
L		 5467 as_bad (_("`%s%s' not allowed with `%s%c'"),
5468 register_prefix,
29b0f896
AM		 5469 i.op[op].regs->reg_name,
5470 i.tm.name,
5471 i.suffix);
5472 return 0;
5473 }
e4630f71 5474 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5475 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5476 && i.types[op].bitfield.reg16
5477 && (i.tm.operand_types[op].bitfield.reg32
5478 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5479 {
5480 /* Prohibit these changes in the 64bit mode, since the
5481 lowering is more complicated. */
5482 if (flag_code == CODE_64BIT)
252b5132 5483 {
2b5d6a91 5484 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5485 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5486 i.suffix);
5487 return 0;
252b5132 5488 }
29b0f896 5489#if REGISTER_WARNINGS
cecf1424
JB		 5490 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5491 register_prefix,
5492 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5493 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5494#endif
252b5132 5495 }
e4630f71 5496 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5497 else if (i.types[op].bitfield.reg64
5498 && (i.tm.operand_types[op].bitfield.reg32
5499 || i.tm.operand_types[op].bitfield.acc))
252b5132 5500 {
34828aad 5501 if (intel_syntax
ca61edf2 5502 && i.tm.opcode_modifier.toqword
40fb9820 5503 && !i.types[0].bitfield.regxmm)
34828aad 5504 {
ca61edf2 5505 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5506 i.suffix = QWORD_MNEM_SUFFIX;
5507 }
5508 else
5509 {
2b5d6a91 5510 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5511 register_prefix, i.op[op].regs->reg_name,
5512 i.suffix);
5513 return 0;
5514 }
29b0f896
AM		 5515 }
5516 return 1;
5517}
252b5132 5518
29b0f896 5519static int
e3bb37b5 5520check_qword_reg (void)
29b0f896
AM		 5521{
5522 int op;
252b5132 5523
29b0f896
AM		 5524 for (op = i.operands; --op >= 0; )
5525 /* Reject eight bit registers, except where the template requires
5526 them. (eg. movzb) */
40fb9820
L		 5527 if (i.types[op].bitfield.reg8
5528 && (i.tm.operand_types[op].bitfield.reg16
5529 || i.tm.operand_types[op].bitfield.reg32
5530 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5531 {
a540244d
L		 5532 as_bad (_("`%s%s' not allowed with `%s%c'"),
5533 register_prefix,
29b0f896
AM		 5534 i.op[op].regs->reg_name,
5535 i.tm.name,
5536 i.suffix);
5537 return 0;
5538 }
e4630f71 5539 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5540 else if ((i.types[op].bitfield.reg16
5541 || i.types[op].bitfield.reg32)
5542 && (i.tm.operand_types[op].bitfield.reg32
5543 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5544 {
5545 /* Prohibit these changes in the 64bit mode, since the
5546 lowering is more complicated. */
34828aad 5547 if (intel_syntax
ca61edf2 5548 && i.tm.opcode_modifier.todword
40fb9820 5549 && !i.types[0].bitfield.regxmm)
34828aad 5550 {
ca61edf2 5551 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5552 i.suffix = LONG_MNEM_SUFFIX;
5553 }
5554 else
5555 {
2b5d6a91 5556 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5557 register_prefix, i.op[op].regs->reg_name,
5558 i.suffix);
5559 return 0;
5560 }
252b5132 5561 }
29b0f896
AM		 5562 return 1;
5563}
252b5132 5564
29b0f896 5565static int
e3bb37b5 5566check_word_reg (void)
29b0f896
AM		 5567{
5568 int op;
5569 for (op = i.operands; --op >= 0;)
5570 /* Reject eight bit registers, except where the template requires
5571 them. (eg. movzb) */
40fb9820
L		 5572 if (i.types[op].bitfield.reg8
5573 && (i.tm.operand_types[op].bitfield.reg16
5574 || i.tm.operand_types[op].bitfield.reg32
5575 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5576 {
a540244d
L		 5577 as_bad (_("`%s%s' not allowed with `%s%c'"),
5578 register_prefix,
29b0f896
AM		 5579 i.op[op].regs->reg_name,
5580 i.tm.name,
5581 i.suffix);
5582 return 0;
5583 }
e4630f71 5584 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5585 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5586 && (i.types[op].bitfield.reg32
5587 || i.types[op].bitfield.reg64)
40fb9820
L		 5588 && (i.tm.operand_types[op].bitfield.reg16
5589 || i.tm.operand_types[op].bitfield.acc))
252b5132 5590 {
29b0f896
AM		 5591 /* Prohibit these changes in the 64bit mode, since the
5592 lowering is more complicated. */
5593 if (flag_code == CODE_64BIT)
252b5132 5594 {
2b5d6a91 5595 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5596 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5597 i.suffix);
5598 return 0;
252b5132 5599 }
29b0f896 5600#if REGISTER_WARNINGS
cecf1424
JB		 5601 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5602 register_prefix,
5603 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5604 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5605#endif
5606 }
5607 return 1;
5608}
252b5132 5609
29b0f896 5610static int
40fb9820 5611update_imm (unsigned int j)
29b0f896 5612{
bc0844ae 5613 i386_operand_type overlap = i.types[j];
40fb9820
L		 5614 if ((overlap.bitfield.imm8
5615 || overlap.bitfield.imm8s
5616 || overlap.bitfield.imm16
5617 || overlap.bitfield.imm32
5618 || overlap.bitfield.imm32s
5619 || overlap.bitfield.imm64)
0dfbf9d7
L		 5620 && !operand_type_equal (&overlap, &imm8)
5621 && !operand_type_equal (&overlap, &imm8s)
5622 && !operand_type_equal (&overlap, &imm16)
5623 && !operand_type_equal (&overlap, &imm32)
5624 && !operand_type_equal (&overlap, &imm32s)
5625 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5626 {
5627 if (i.suffix)
5628 {
40fb9820
L		 5629 i386_operand_type temp;
5630
0dfbf9d7 5631 operand_type_set (&temp, 0);
7ab9ffdd 5632 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5633 {
5634 temp.bitfield.imm8 = overlap.bitfield.imm8;
5635 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5636 }
5637 else if (i.suffix == WORD_MNEM_SUFFIX)
5638 temp.bitfield.imm16 = overlap.bitfield.imm16;
5639 else if (i.suffix == QWORD_MNEM_SUFFIX)
5640 {
5641 temp.bitfield.imm64 = overlap.bitfield.imm64;
5642 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5643 }
5644 else
5645 temp.bitfield.imm32 = overlap.bitfield.imm32;
5646 overlap = temp;
29b0f896 5647 }
0dfbf9d7
L		 5648 else if (operand_type_equal (&overlap, &imm16_32_32s)
5649 || operand_type_equal (&overlap, &imm16_32)
5650 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5651 {
40fb9820 5652 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5653 overlap = imm16;
40fb9820 5654 else
65da13b5 5655 overlap = imm32s;
29b0f896 5656 }
0dfbf9d7
L		 5657 if (!operand_type_equal (&overlap, &imm8)
5658 && !operand_type_equal (&overlap, &imm8s)
5659 && !operand_type_equal (&overlap, &imm16)
5660 && !operand_type_equal (&overlap, &imm32)
5661 && !operand_type_equal (&overlap, &imm32s)
5662 && !operand_type_equal (&overlap, &imm64))
29b0f896 5663 {
4eed87de
AM		 5664 as_bad (_("no instruction mnemonic suffix given; "
5665 "can't determine immediate size"));
29b0f896
AM		 5666 return 0;
5667 }
5668 }
40fb9820 5669 i.types[j] = overlap;
29b0f896 5670
40fb9820
L		 5671 return 1;
5672}
5673
5674static int
5675finalize_imm (void)
5676{
bc0844ae 5677 unsigned int j, n;
29b0f896 5678
bc0844ae
L		 5679 /* Update the first 2 immediate operands. */
5680 n = i.operands > 2 ? 2 : i.operands;
5681 if (n)
5682 {
5683 for (j = 0; j < n; j++)
5684 if (update_imm (j) == 0)
5685 return 0;
40fb9820 5686
bc0844ae
L		 5687 /* The 3rd operand can't be immediate operand. */
5688 gas_assert (operand_type_check (i.types[2], imm) == 0);
5689 }
29b0f896
AM		 5690
5691 return 1;
5692}
5693
c0f3af97
L		 5694static int
5695bad_implicit_operand (int xmm)
5696{
91d6fa6a
NC		 5697 const char *ireg = xmm ? "xmm0" : "ymm0";
5698
c0f3af97
L		 5699 if (intel_syntax)
5700 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5701 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5702 else
5703 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5704 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5705 return 0;
5706}
5707
29b0f896 5708static int
e3bb37b5 5709process_operands (void)
29b0f896
AM		 5710{
5711 /* Default segment register this instruction will use for memory
5712 accesses. 0 means unknown. This is only for optimizing out
5713 unnecessary segment overrides. */
5714 const seg_entry *default_seg = 0;
5715
2426c15f 5716 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5717 {
91d6fa6a
NC		 5718 unsigned int dupl = i.operands;
5719 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5720 unsigned int j;
5721
c0f3af97 5722 /* The destination must be an xmm register. */
9c2799c2 5723 gas_assert (i.reg_operands
91d6fa6a 5724 && MAX_OPERANDS > dupl
7ab9ffdd 5725 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5726
5727 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5728 {
c0f3af97 5729 /* The first operand is implicit and must be xmm0. */
9c2799c2 5730 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5731 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5732 return bad_implicit_operand (1);
5733
8cd7925b 5734 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5735 {
5736 /* Keep xmm0 for instructions with VEX prefix and 3
5737 sources. */
5738 goto duplicate;
5739 }
e2ec9d29 5740 else
c0f3af97
L		 5741 {
5742 /* We remove the first xmm0 and keep the number of
5743 operands unchanged, which in fact duplicates the
5744 destination. */
5745 for (j = 1; j < i.operands; j++)
5746 {
5747 i.op[j - 1] = i.op[j];
5748 i.types[j - 1] = i.types[j];
5749 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5750 }
5751 }
5752 }
5753 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5754 {
91d6fa6a 5755 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5756 && (i.tm.opcode_modifier.vexsources
5757 == VEX3SOURCES));
c0f3af97
L		 5758
5759 /* Add the implicit xmm0 for instructions with VEX prefix
5760 and 3 sources. */
5761 for (j = i.operands; j > 0; j--)
5762 {
5763 i.op[j] = i.op[j - 1];
5764 i.types[j] = i.types[j - 1];
5765 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5766 }
5767 i.op[0].regs
5768 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5769 i.types[0] = regxmm;
c0f3af97
L		 5770 i.tm.operand_types[0] = regxmm;
5771
5772 i.operands += 2;
5773 i.reg_operands += 2;
5774 i.tm.operands += 2;
5775
91d6fa6a 5776 dupl++;
c0f3af97 5777 dest++;
91d6fa6a
NC		 5778 i.op[dupl] = i.op[dest];
5779 i.types[dupl] = i.types[dest];
5780 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5781 }
c0f3af97
L		 5782 else
5783 {
5784duplicate:
5785 i.operands++;
5786 i.reg_operands++;
5787 i.tm.operands++;
5788
91d6fa6a
NC		 5789 i.op[dupl] = i.op[dest];
5790 i.types[dupl] = i.types[dest];
5791 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5792 }
5793
5794 if (i.tm.opcode_modifier.immext)
5795 process_immext ();
5796 }
5797 else if (i.tm.opcode_modifier.firstxmm0)
5798 {
5799 unsigned int j;
5800
43234a1e 5801 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5802 gas_assert (i.reg_operands
7ab9ffdd 5803 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5804 || operand_type_equal (&i.types[0], &regymm)
5805 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5806 if (register_number (i.op[0].regs) != 0)
c0f3af97 5807 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5808
5809 for (j = 1; j < i.operands; j++)
5810 {
5811 i.op[j - 1] = i.op[j];
5812 i.types[j - 1] = i.types[j];
5813
5814 /* We need to adjust fields in i.tm since they are used by
5815 build_modrm_byte. */
5816 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5817 }
5818
e2ec9d29
L		 5819 i.operands--;
5820 i.reg_operands--;
e2ec9d29
L		 5821 i.tm.operands--;
5822 }
5823 else if (i.tm.opcode_modifier.regkludge)
5824 {
5825 /* The imul $imm, %reg instruction is converted into
5826 imul $imm, %reg, %reg, and the clr %reg instruction
5827 is converted into xor %reg, %reg. */
5828
5829 unsigned int first_reg_op;
5830
5831 if (operand_type_check (i.types[0], reg))
5832 first_reg_op = 0;
5833 else
5834 first_reg_op = 1;
5835 /* Pretend we saw the extra register operand. */
9c2799c2 5836 gas_assert (i.reg_operands == 1
7ab9ffdd 5837 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5838 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5839 i.types[first_reg_op + 1] = i.types[first_reg_op];
5840 i.operands++;
5841 i.reg_operands++;
29b0f896
AM		 5842 }
5843
40fb9820 5844 if (i.tm.opcode_modifier.shortform)
29b0f896 5845 {
40fb9820
L		 5846 if (i.types[0].bitfield.sreg2
5847 || i.types[0].bitfield.sreg3)
29b0f896 5848 {
4eed87de
AM		 5849 if (i.tm.base_opcode == POP_SEG_SHORT
5850 && i.op[0].regs->reg_num == 1)
29b0f896 5851 {
a87af027 5852 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5853 return 0;
29b0f896 5854 }
4eed87de
AM		 5855 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5856 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5857 i.rex |= REX_B;
4eed87de
AM		 5858 }
5859 else
5860 {
7ab9ffdd 5861 /* The register or float register operand is in operand
85f10a01 5862 0 or 1. */
40fb9820 5863 unsigned int op;
7ab9ffdd
L		 5864
5865 if (i.types[0].bitfield.floatreg
5866 || operand_type_check (i.types[0], reg))
5867 op = 0;
5868 else
5869 op = 1;
4eed87de
AM		 5870 /* Register goes in low 3 bits of opcode. */
5871 i.tm.base_opcode |= i.op[op].regs->reg_num;
5872 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5873 i.rex |= REX_B;
40fb9820 5874 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5875 {
4eed87de
AM		 5876 /* Warn about some common errors, but press on regardless.
5877 The first case can be generated by gcc (<= 2.8.1). */
5878 if (i.operands == 2)
5879 {
5880 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5881 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5882 register_prefix, i.op[!intel_syntax].regs->reg_name,
5883 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5884 }
5885 else
5886 {
5887 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5888 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5889 register_prefix, i.op[0].regs->reg_name);
4eed87de 5890 }
29b0f896
AM		 5891 }
5892 }
5893 }
40fb9820 5894 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5895 {
5896 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5897 must be put into the modrm byte). Now, we make the modrm and
5898 index base bytes based on all the info we've collected. */
29b0f896
AM		 5899
5900 default_seg = build_modrm_byte ();
5901 }
8a2ed489 5902 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5903 {
5904 default_seg = &ds;
5905 }
40fb9820 5906 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5907 {
5908 /* For the string instructions that allow a segment override
5909 on one of their operands, the default segment is ds. */
5910 default_seg = &ds;
5911 }
5912
75178d9d
L		 5913 if (i.tm.base_opcode == 0x8d /* lea */
5914 && i.seg[0]
5915 && !quiet_warnings)
30123838 5916 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5917
5918 /* If a segment was explicitly specified, and the specified segment
5919 is not the default, use an opcode prefix to select it. If we
5920 never figured out what the default segment is, then default_seg
5921 will be zero at this point, and the specified segment prefix will
5922 always be used. */
29b0f896
AM		 5923 if ((i.seg[0]) && (i.seg[0] != default_seg))
5924 {
5925 if (!add_prefix (i.seg[0]->seg_prefix))
5926 return 0;
5927 }
5928 return 1;
5929}
5930
5931static const seg_entry *
e3bb37b5 5932build_modrm_byte (void)
29b0f896
AM		 5933{
5934 const seg_entry *default_seg = 0;
c0f3af97 5935 unsigned int source, dest;
8cd7925b 5936 int vex_3_sources;
c0f3af97
L		 5937
5938 /* The first operand of instructions with VEX prefix and 3 sources
5939 must be VEX_Imm4. */
8cd7925b 5940 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5941 if (vex_3_sources)
5942 {
91d6fa6a 5943 unsigned int nds, reg_slot;
4c2c6516 5944 expressionS *exp;
c0f3af97 5945
922d8de8 5946 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5947 && i.tm.opcode_modifier.immext)
5948 {
5949 dest = i.operands - 2;
5950 gas_assert (dest == 3);
5951 }
922d8de8 5952 else
a683cc34 5953 dest = i.operands - 1;
c0f3af97 5954 nds = dest - 1;
922d8de8 5955
a683cc34
SP		 5956 /* There are 2 kinds of instructions:
5957 1. 5 operands: 4 register operands or 3 register operands
5958 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5959 VexW0 or VexW1. The destination must be either XMM, YMM or
5960 ZMM register.
a683cc34
SP		 5961 2. 4 operands: 4 register operands or 3 register operands
5962 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5963 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5964 || (i.reg_operands == 3 && i.mem_operands == 1))
5965 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5966 && (i.tm.opcode_modifier.veximmext
5967 || (i.imm_operands == 1
5968 && i.types[0].bitfield.vec_imm4
5969 && (i.tm.opcode_modifier.vexw == VEXW0
5970 || i.tm.opcode_modifier.vexw == VEXW1)
5971 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5972 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5973 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5974
5975 if (i.imm_operands == 0)
5976 {
5977 /* When there is no immediate operand, generate an 8bit
5978 immediate operand to encode the first operand. */
5979 exp = &im_expressions[i.imm_operands++];
5980 i.op[i.operands].imms = exp;
5981 i.types[i.operands] = imm8;
5982 i.operands++;
5983 /* If VexW1 is set, the first operand is the source and
5984 the second operand is encoded in the immediate operand. */
5985 if (i.tm.opcode_modifier.vexw == VEXW1)
5986 {
5987 source = 0;
5988 reg_slot = 1;
5989 }
5990 else
5991 {
5992 source = 1;
5993 reg_slot = 0;
5994 }
5995
5996 /* FMA swaps REG and NDS. */
5997 if (i.tm.cpu_flags.bitfield.cpufma)
5998 {
5999 unsigned int tmp;
6000 tmp = reg_slot;
6001 reg_slot = nds;
6002 nds = tmp;
6003 }
6004
24981e7b
L		 6005 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6006 &regxmm)
a683cc34 6007 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6008 &regymm)
6009 || operand_type_equal (&i.tm.operand_types[reg_slot],
6010 &regzmm));
a683cc34 6011 exp->X_op = O_constant;
4c692bc7 6012 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6013 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6014 }
922d8de8 6015 else
a683cc34
SP		 6016 {
6017 unsigned int imm_slot;
6018
6019 if (i.tm.opcode_modifier.vexw == VEXW0)
6020 {
6021 /* If VexW0 is set, the third operand is the source and
6022 the second operand is encoded in the immediate
6023 operand. */
6024 source = 2;
6025 reg_slot = 1;
6026 }
6027 else
6028 {
6029 /* VexW1 is set, the second operand is the source and
6030 the third operand is encoded in the immediate
6031 operand. */
6032 source = 1;
6033 reg_slot = 2;
6034 }
6035
6036 if (i.tm.opcode_modifier.immext)
6037 {
6038 /* When ImmExt is set, the immdiate byte is the last
6039 operand. */
6040 imm_slot = i.operands - 1;
6041 source--;
6042 reg_slot--;
6043 }
6044 else
6045 {
6046 imm_slot = 0;
6047
6048 /* Turn on Imm8 so that output_imm will generate it. */
6049 i.types[imm_slot].bitfield.imm8 = 1;
6050 }
6051
24981e7b
L		 6052 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6053 &regxmm)
6054 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6055 &regymm)
6056 || operand_type_equal (&i.tm.operand_types[reg_slot],
6057 &regzmm));
a683cc34 6058 i.op[imm_slot].imms->X_add_number
4c692bc7 6059 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6060 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6061 }
6062
6063 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6064 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6065 &regymm)
6066 || operand_type_equal (&i.tm.operand_types[nds],
6067 &regzmm));
dae39acc 6068 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6069 }
6070 else
6071 source = dest = 0;
29b0f896
AM		 6072
6073 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6074 implicit registers do not count. If there are 3 register
6075 operands, it must be a instruction with VexNDS. For a
6076 instruction with VexNDD, the destination register is encoded
6077 in VEX prefix. If there are 4 register operands, it must be
6078 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6079 if (i.mem_operands == 0
6080 && ((i.reg_operands == 2
2426c15f 6081 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6082 || (i.reg_operands == 3
2426c15f 6083 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6084 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6085 {
cab737b9
L		 6086 switch (i.operands)
6087 {
6088 case 2:
6089 source = 0;
6090 break;
6091 case 3:
c81128dc
L		 6092 /* When there are 3 operands, one of them may be immediate,
6093 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6094 the first operand must be shift count register (cl) or it
6095 is an instruction with VexNDS. */
9c2799c2 6096 gas_assert (i.imm_operands == 1
7ab9ffdd 6097 || (i.imm_operands == 0
2426c15f 6098 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6099 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6100 if (operand_type_check (i.types[0], imm)
6101 || i.types[0].bitfield.shiftcount)
6102 source = 1;
6103 else
6104 source = 0;
cab737b9
L		 6105 break;
6106 case 4:
368d64cc
L		 6107 /* When there are 4 operands, the first two must be 8bit
6108 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6109 one.
6110
6111 For instructions with VexNDS, if the first operand
6112 an imm8, the source operand is the 2nd one. If the last
6113 operand is imm8, the source operand is the first one. */
9c2799c2 6114 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6115 && i.types[0].bitfield.imm8
6116 && i.types[1].bitfield.imm8)
2426c15f 6117 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6118 && i.imm_operands == 1
6119 && (i.types[0].bitfield.imm8
43234a1e
L		 6120 || i.types[i.operands - 1].bitfield.imm8
6121 || i.rounding)));
9f2670f2
L		 6122 if (i.imm_operands == 2)
6123 source = 2;
6124 else
c0f3af97
L		 6125 {
6126 if (i.types[0].bitfield.imm8)
6127 source = 1;
6128 else
6129 source = 0;
6130 }
c0f3af97
L		 6131 break;
6132 case 5:
43234a1e
L		 6133 if (i.tm.opcode_modifier.evex)
6134 {
6135 /* For EVEX instructions, when there are 5 operands, the
6136 first one must be immediate operand. If the second one
6137 is immediate operand, the source operand is the 3th
6138 one. If the last one is immediate operand, the source
6139 operand is the 2nd one. */
6140 gas_assert (i.imm_operands == 2
6141 && i.tm.opcode_modifier.sae
6142 && operand_type_check (i.types[0], imm));
6143 if (operand_type_check (i.types[1], imm))
6144 source = 2;
6145 else if (operand_type_check (i.types[4], imm))
6146 source = 1;
6147 else
6148 abort ();
6149 }
cab737b9
L		 6150 break;
6151 default:
6152 abort ();
6153 }
6154
c0f3af97
L		 6155 if (!vex_3_sources)
6156 {
6157 dest = source + 1;
6158
43234a1e
L		 6159 /* RC/SAE operand could be between DEST and SRC. That happens
6160 when one operand is GPR and the other one is XMM/YMM/ZMM
6161 register. */
6162 if (i.rounding && i.rounding->operand == (int) dest)
6163 dest++;
6164
2426c15f 6165 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6166 {
43234a1e
L		 6167 /* For instructions with VexNDS, the register-only source
6168 operand must be 32/64bit integer, XMM, YMM or ZMM
6169 register. It is encoded in VEX prefix. We need to
6170 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6171
6172 i386_operand_type op;
6173 unsigned int vvvv;
6174
6175 /* Check register-only source operand when two source
6176 operands are swapped. */
6177 if (!i.tm.operand_types[source].bitfield.baseindex
6178 && i.tm.operand_types[dest].bitfield.baseindex)
6179 {
6180 vvvv = source;
6181 source = dest;
6182 }
6183 else
6184 vvvv = dest;
6185
6186 op = i.tm.operand_types[vvvv];
fa99fab2 6187 op.bitfield.regmem = 0;
c0f3af97 6188 if ((dest + 1) >= i.operands
ac4eb736
AM		 6189 || (!op.bitfield.reg32
6190 && op.bitfield.reg64
f12dc422 6191 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6192 && !operand_type_equal (&op, &regymm)
6193 && !operand_type_equal (&op, &regzmm)
6194 && !operand_type_equal (&op, &regmask)))
c0f3af97 6195 abort ();
f12dc422 6196 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6197 dest++;
6198 }
6199 }
29b0f896
AM		 6200
6201 i.rm.mode = 3;
6202 /* One of the register operands will be encoded in the i.tm.reg
6203 field, the other in the combined i.tm.mode and i.tm.regmem
6204 fields. If no form of this instruction supports a memory
6205 destination operand, then we assume the source operand may
6206 sometimes be a memory operand and so we need to store the
6207 destination in the i.rm.reg field. */
40fb9820
L		 6208 if (!i.tm.operand_types[dest].bitfield.regmem
6209 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6210 {
6211 i.rm.reg = i.op[dest].regs->reg_num;
6212 i.rm.regmem = i.op[source].regs->reg_num;
6213 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6214 i.rex |= REX_R;
43234a1e
L		 6215 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6216 i.vrex |= REX_R;
29b0f896 6217 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6218 i.rex |= REX_B;
43234a1e
L		 6219 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6220 i.vrex |= REX_B;
29b0f896
AM		 6221 }
6222 else
6223 {
6224 i.rm.reg = i.op[source].regs->reg_num;
6225 i.rm.regmem = i.op[dest].regs->reg_num;
6226 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6227 i.rex |= REX_B;
43234a1e
L		 6228 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6229 i.vrex |= REX_B;
29b0f896 6230 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6231 i.rex |= REX_R;
43234a1e
L		 6232 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6233 i.vrex |= REX_R;
29b0f896 6234 }
161a04f6 6235 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6236 {
40fb9820
L		 6237 if (!i.types[0].bitfield.control
6238 && !i.types[1].bitfield.control)
c4a530c5 6239 abort ();
161a04f6 6240 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6241 add_prefix (LOCK_PREFIX_OPCODE);
6242 }
29b0f896
AM		 6243 }
6244 else
6245 { /* If it's not 2 reg operands... */
c0f3af97
L		 6246 unsigned int mem;
6247
29b0f896
AM		 6248 if (i.mem_operands)
6249 {
6250 unsigned int fake_zero_displacement = 0;
99018f42 6251 unsigned int op;
4eed87de 6252
7ab9ffdd
L		 6253 for (op = 0; op < i.operands; op++)
6254 if (operand_type_check (i.types[op], anymem))
6255 break;
7ab9ffdd 6256 gas_assert (op < i.operands);
29b0f896 6257
6c30d220
L		 6258 if (i.tm.opcode_modifier.vecsib)
6259 {
6260 if (i.index_reg->reg_num == RegEiz
6261 || i.index_reg->reg_num == RegRiz)
6262 abort ();
6263
6264 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6265 if (!i.base_reg)
6266 {
6267 i.sib.base = NO_BASE_REGISTER;
6268 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6269 /* No Vec_Disp8 if there is no base. */
6270 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6271 i.types[op].bitfield.disp8 = 0;
6272 i.types[op].bitfield.disp16 = 0;
6273 i.types[op].bitfield.disp64 = 0;
6274 if (flag_code != CODE_64BIT)
6275 {
6276 /* Must be 32 bit */
6277 i.types[op].bitfield.disp32 = 1;
6278 i.types[op].bitfield.disp32s = 0;
6279 }
6280 else
6281 {
6282 i.types[op].bitfield.disp32 = 0;
6283 i.types[op].bitfield.disp32s = 1;
6284 }
6285 }
6286 i.sib.index = i.index_reg->reg_num;
6287 if ((i.index_reg->reg_flags & RegRex) != 0)
6288 i.rex |= REX_X;
43234a1e
L		 6289 if ((i.index_reg->reg_flags & RegVRex) != 0)
6290 i.vrex |= REX_X;
6c30d220
L		 6291 }
6292
29b0f896
AM		 6293 default_seg = &ds;
6294
6295 if (i.base_reg == 0)
6296 {
6297 i.rm.mode = 0;
6298 if (!i.disp_operands)
6c30d220
L		 6299 {
6300 fake_zero_displacement = 1;
6301 /* Instructions with VSIB byte need 32bit displacement
6302 if there is no base register. */
6303 if (i.tm.opcode_modifier.vecsib)
6304 i.types[op].bitfield.disp32 = 1;
6305 }
29b0f896
AM		 6306 if (i.index_reg == 0)
6307 {
6c30d220 6308 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6309 /* Operand is just <disp> */
20f0a1fc 6310 if (flag_code == CODE_64BIT)
29b0f896
AM		 6311 {
6312 /* 64bit mode overwrites the 32bit absolute
6313 addressing by RIP relative addressing and
6314 absolute addressing is encoded by one of the
6315 redundant SIB forms. */
6316 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6317 i.sib.base = NO_BASE_REGISTER;
6318 i.sib.index = NO_INDEX_REGISTER;
fc225355 6319 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6320 ? disp32s : disp32);
20f0a1fc 6321 }
fc225355
L		 6322 else if ((flag_code == CODE_16BIT)
6323 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6324 {
6325 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6326 i.types[op] = disp16;
20f0a1fc
NC		 6327 }
6328 else
6329 {
6330 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6331 i.types[op] = disp32;
29b0f896
AM		 6332 }
6333 }
6c30d220 6334 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6335 {
6c30d220 6336 /* !i.base_reg && i.index_reg */
db51cc60
L		 6337 if (i.index_reg->reg_num == RegEiz
6338 || i.index_reg->reg_num == RegRiz)
6339 i.sib.index = NO_INDEX_REGISTER;
6340 else
6341 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6342 i.sib.base = NO_BASE_REGISTER;
6343 i.sib.scale = i.log2_scale_factor;
6344 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6345 /* No Vec_Disp8 if there is no base. */
6346 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6347 i.types[op].bitfield.disp8 = 0;
6348 i.types[op].bitfield.disp16 = 0;
6349 i.types[op].bitfield.disp64 = 0;
29b0f896 6350 if (flag_code != CODE_64BIT)
40fb9820
L		 6351 {
6352 /* Must be 32 bit */
6353 i.types[op].bitfield.disp32 = 1;
6354 i.types[op].bitfield.disp32s = 0;
6355 }
29b0f896 6356 else
40fb9820
L		 6357 {
6358 i.types[op].bitfield.disp32 = 0;
6359 i.types[op].bitfield.disp32s = 1;
6360 }
29b0f896 6361 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6362 i.rex |= REX_X;
29b0f896
AM		 6363 }
6364 }
6365 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6366 else if (i.base_reg->reg_num == RegRip ||
6367 i.base_reg->reg_num == RegEip)
29b0f896 6368 {
6c30d220 6369 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6370 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6371 i.types[op].bitfield.disp8 = 0;
6372 i.types[op].bitfield.disp16 = 0;
6373 i.types[op].bitfield.disp32 = 0;
6374 i.types[op].bitfield.disp32s = 1;
6375 i.types[op].bitfield.disp64 = 0;
43234a1e 6376 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6377 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6378 if (! i.disp_operands)
6379 fake_zero_displacement = 1;
29b0f896 6380 }
40fb9820 6381 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6382 {
6c30d220 6383 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6384 switch (i.base_reg->reg_num)
6385 {
6386 case 3: /* (%bx) */
6387 if (i.index_reg == 0)
6388 i.rm.regmem = 7;
6389 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6390 i.rm.regmem = i.index_reg->reg_num - 6;
6391 break;
6392 case 5: /* (%bp) */
6393 default_seg = &ss;
6394 if (i.index_reg == 0)
6395 {
6396 i.rm.regmem = 6;
40fb9820 6397 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6398 {
6399 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6400 if (i.tm.operand_types[op].bitfield.vec_disp8)
6401 i.types[op].bitfield.vec_disp8 = 1;
6402 else
6403 i.types[op].bitfield.disp8 = 1;
252b5132 6404 fake_zero_displacement = 1;
29b0f896
AM		 6405 }
6406 }
6407 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6408 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6409 break;
6410 default: /* (%si) -> 4 or (%di) -> 5 */
6411 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6412 }
6413 i.rm.mode = mode_from_disp_size (i.types[op]);
6414 }
6415 else /* i.base_reg and 32/64 bit mode */
6416 {
6417 if (flag_code == CODE_64BIT
40fb9820
L		 6418 && operand_type_check (i.types[op], disp))
6419 {
6420 i386_operand_type temp;
0dfbf9d7 6421 operand_type_set (&temp, 0);
40fb9820 6422 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6423 temp.bitfield.vec_disp8
6424 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6425 i.types[op] = temp;
6426 if (i.prefix[ADDR_PREFIX] == 0)
6427 i.types[op].bitfield.disp32s = 1;
6428 else
6429 i.types[op].bitfield.disp32 = 1;
6430 }
20f0a1fc 6431
6c30d220
L		 6432 if (!i.tm.opcode_modifier.vecsib)
6433 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6434 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6435 i.rex |= REX_B;
29b0f896
AM		 6436 i.sib.base = i.base_reg->reg_num;
6437 /* x86-64 ignores REX prefix bit here to avoid decoder
6438 complications. */
848930b2
JB		 6439 if (!(i.base_reg->reg_flags & RegRex)
6440 && (i.base_reg->reg_num == EBP_REG_NUM
6441 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6442 default_seg = &ss;
848930b2 6443 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6444 {
848930b2 6445 fake_zero_displacement = 1;
43234a1e
L		 6446 if (i.tm.operand_types [op].bitfield.vec_disp8)
6447 i.types[op].bitfield.vec_disp8 = 1;
6448 else
6449 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6450 }
6451 i.sib.scale = i.log2_scale_factor;
6452 if (i.index_reg == 0)
6453 {
6c30d220 6454 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6455 /* <disp>(%esp) becomes two byte modrm with no index
6456 register. We've already stored the code for esp
6457 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6458 Any base register besides %esp will not use the
6459 extra modrm byte. */
6460 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6461 }
6c30d220 6462 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6463 {
db51cc60
L		 6464 if (i.index_reg->reg_num == RegEiz
6465 || i.index_reg->reg_num == RegRiz)
6466 i.sib.index = NO_INDEX_REGISTER;
6467 else
6468 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6469 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6470 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6471 i.rex |= REX_X;
29b0f896 6472 }
67a4f2b7
AO		 6473
6474 if (i.disp_operands
6475 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6476 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6477 i.rm.mode = 0;
6478 else
a501d77e
L		 6479 {
6480 if (!fake_zero_displacement
6481 && !i.disp_operands
6482 && i.disp_encoding)
6483 {
6484 fake_zero_displacement = 1;
6485 if (i.disp_encoding == disp_encoding_8bit)
6486 i.types[op].bitfield.disp8 = 1;
6487 else
6488 i.types[op].bitfield.disp32 = 1;
6489 }
6490 i.rm.mode = mode_from_disp_size (i.types[op]);
6491 }
29b0f896 6492 }
252b5132 6493
29b0f896
AM		 6494 if (fake_zero_displacement)
6495 {
6496 /* Fakes a zero displacement assuming that i.types[op]
6497 holds the correct displacement size. */
6498 expressionS *exp;
6499
9c2799c2 6500 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6501 exp = &disp_expressions[i.disp_operands++];
6502 i.op[op].disps = exp;
6503 exp->X_op = O_constant;
6504 exp->X_add_number = 0;
6505 exp->X_add_symbol = (symbolS *) 0;
6506 exp->X_op_symbol = (symbolS *) 0;
6507 }
c0f3af97
L		 6508
6509 mem = op;
29b0f896 6510 }
c0f3af97
L		 6511 else
6512 mem = ~0;
252b5132 6513
8c43a48b 6514 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6515 {
6516 if (operand_type_check (i.types[0], imm))
6517 i.vex.register_specifier = NULL;
6518 else
6519 {
6520 /* VEX.vvvv encodes one of the sources when the first
6521 operand is not an immediate. */
1ef99a7b 6522 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6523 i.vex.register_specifier = i.op[0].regs;
6524 else
6525 i.vex.register_specifier = i.op[1].regs;
6526 }
6527
6528 /* Destination is a XMM register encoded in the ModRM.reg
6529 and VEX.R bit. */
6530 i.rm.reg = i.op[2].regs->reg_num;
6531 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6532 i.rex |= REX_R;
6533
6534 /* ModRM.rm and VEX.B encodes the other source. */
6535 if (!i.mem_operands)
6536 {
6537 i.rm.mode = 3;
6538
1ef99a7b 6539 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6540 i.rm.regmem = i.op[1].regs->reg_num;
6541 else
6542 i.rm.regmem = i.op[0].regs->reg_num;
6543
6544 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6545 i.rex |= REX_B;
6546 }
6547 }
2426c15f 6548 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6549 {
6550 i.vex.register_specifier = i.op[2].regs;
6551 if (!i.mem_operands)
6552 {
6553 i.rm.mode = 3;
6554 i.rm.regmem = i.op[1].regs->reg_num;
6555 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6556 i.rex |= REX_B;
6557 }
6558 }
29b0f896
AM		 6559 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6560 (if any) based on i.tm.extension_opcode. Again, we must be
6561 careful to make sure that segment/control/debug/test/MMX
6562 registers are coded into the i.rm.reg field. */
f88c9eb0 6563 else if (i.reg_operands)
29b0f896 6564 {
99018f42 6565 unsigned int op;
7ab9ffdd
L		 6566 unsigned int vex_reg = ~0;
6567
6568 for (op = 0; op < i.operands; op++)
6569 if (i.types[op].bitfield.reg8
6570 || i.types[op].bitfield.reg16
6571 || i.types[op].bitfield.reg32
6572 || i.types[op].bitfield.reg64
6573 || i.types[op].bitfield.regmmx
6574 || i.types[op].bitfield.regxmm
6575 || i.types[op].bitfield.regymm
7e8b059b 6576 || i.types[op].bitfield.regbnd
43234a1e
L		 6577 || i.types[op].bitfield.regzmm
6578 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6579 || i.types[op].bitfield.sreg2
6580 || i.types[op].bitfield.sreg3
6581 || i.types[op].bitfield.control
6582 || i.types[op].bitfield.debug
6583 || i.types[op].bitfield.test)
6584 break;
c0209578 6585
7ab9ffdd
L		 6586 if (vex_3_sources)
6587 op = dest;
2426c15f 6588 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6589 {
6590 /* For instructions with VexNDS, the register-only
6591 source operand is encoded in VEX prefix. */
6592 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6593
7ab9ffdd 6594 if (op > mem)
c0f3af97 6595 {
7ab9ffdd
L		 6596 vex_reg = op++;
6597 gas_assert (op < i.operands);
c0f3af97
L		 6598 }
6599 else
c0f3af97 6600 {
f12dc422
L		 6601 /* Check register-only source operand when two source
6602 operands are swapped. */
6603 if (!i.tm.operand_types[op].bitfield.baseindex
6604 && i.tm.operand_types[op + 1].bitfield.baseindex)
6605 {
6606 vex_reg = op;
6607 op += 2;
6608 gas_assert (mem == (vex_reg + 1)
6609 && op < i.operands);
6610 }
6611 else
6612 {
6613 vex_reg = op + 1;
6614 gas_assert (vex_reg < i.operands);
6615 }
c0f3af97 6616 }
7ab9ffdd 6617 }
2426c15f 6618 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6619 {
f12dc422 6620 /* For instructions with VexNDD, the register destination
7ab9ffdd 6621 is encoded in VEX prefix. */
f12dc422
L		 6622 if (i.mem_operands == 0)
6623 {
6624 /* There is no memory operand. */
6625 gas_assert ((op + 2) == i.operands);
6626 vex_reg = op + 1;
6627 }
6628 else
8d63c93e 6629 {
f12dc422
L		 6630 /* There are only 2 operands. */
6631 gas_assert (op < 2 && i.operands == 2);
6632 vex_reg = 1;
6633 }
7ab9ffdd
L		 6634 }
6635 else
6636 gas_assert (op < i.operands);
99018f42 6637
7ab9ffdd
L		 6638 if (vex_reg != (unsigned int) ~0)
6639 {
f12dc422 6640 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6641
f12dc422
L		 6642 if (type->bitfield.reg32 != 1
6643 && type->bitfield.reg64 != 1
6644 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6645 && !operand_type_equal (type, &regymm)
6646 && !operand_type_equal (type, &regzmm)
6647 && !operand_type_equal (type, &regmask))
7ab9ffdd 6648 abort ();
f88c9eb0 6649
7ab9ffdd
L		 6650 i.vex.register_specifier = i.op[vex_reg].regs;
6651 }
6652
1b9f0c97
L		 6653 /* Don't set OP operand twice. */
6654 if (vex_reg != op)
7ab9ffdd 6655 {
1b9f0c97
L		 6656 /* If there is an extension opcode to put here, the
6657 register number must be put into the regmem field. */
6658 if (i.tm.extension_opcode != None)
6659 {
6660 i.rm.regmem = i.op[op].regs->reg_num;
6661 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6662 i.rex |= REX_B;
43234a1e
L		 6663 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6664 i.vrex |= REX_B;
1b9f0c97
L		 6665 }
6666 else
6667 {
6668 i.rm.reg = i.op[op].regs->reg_num;
6669 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6670 i.rex |= REX_R;
43234a1e
L		 6671 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6672 i.vrex |= REX_R;
1b9f0c97 6673 }
7ab9ffdd 6674 }
252b5132 6675
29b0f896
AM		 6676 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6677 must set it to 3 to indicate this is a register operand
6678 in the regmem field. */
6679 if (!i.mem_operands)
6680 i.rm.mode = 3;
6681 }
252b5132 6682
29b0f896 6683 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6684 if (i.tm.extension_opcode != None)
29b0f896
AM		 6685 i.rm.reg = i.tm.extension_opcode;
6686 }
6687 return default_seg;
6688}
252b5132 6689
29b0f896 6690static void
e3bb37b5 6691output_branch (void)
29b0f896
AM		 6692{
6693 char *p;
f8a5c266 6694 int size;
29b0f896
AM		 6695 int code16;
6696 int prefix;
6697 relax_substateT subtype;
6698 symbolS *sym;
6699 offsetT off;
6700
f8a5c266 6701 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6702 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6703
6704 prefix = 0;
6705 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6706 {
29b0f896
AM		 6707 prefix = 1;
6708 i.prefixes -= 1;
6709 code16 ^= CODE16;
252b5132 6710 }
29b0f896
AM		 6711 /* Pentium4 branch hints. */
6712 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6713 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6714 {
29b0f896
AM		 6715 prefix++;
6716 i.prefixes--;
6717 }
6718 if (i.prefix[REX_PREFIX] != 0)
6719 {
6720 prefix++;
6721 i.prefixes--;
2f66722d
AM		 6722 }
6723
7e8b059b
L		 6724 /* BND prefixed jump. */
6725 if (i.prefix[BND_PREFIX] != 0)
6726 {
6727 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6728 i.prefixes -= 1;
6729 }
6730
29b0f896
AM		 6731 if (i.prefixes != 0 && !intel_syntax)
6732 as_warn (_("skipping prefixes on this instruction"));
6733
6734 /* It's always a symbol; End frag & setup for relax.
6735 Make sure there is enough room in this frag for the largest
6736 instruction we may generate in md_convert_frag. This is 2
6737 bytes for the opcode and room for the prefix and largest
6738 displacement. */
6739 frag_grow (prefix + 2 + 4);
6740 /* Prefix and 1 opcode byte go in fr_fix. */
6741 p = frag_more (prefix + 1);
6742 if (i.prefix[DATA_PREFIX] != 0)
6743 *p++ = DATA_PREFIX_OPCODE;
6744 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6745 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6746 *p++ = i.prefix[SEG_PREFIX];
6747 if (i.prefix[REX_PREFIX] != 0)
6748 *p++ = i.prefix[REX_PREFIX];
6749 *p = i.tm.base_opcode;
6750
6751 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6752 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6753 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6754 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6755 else
f8a5c266 6756 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6757 subtype |= code16;
3e73aa7c 6758
29b0f896
AM		 6759 sym = i.op[0].disps->X_add_symbol;
6760 off = i.op[0].disps->X_add_number;
3e73aa7c 6761
29b0f896
AM		 6762 if (i.op[0].disps->X_op != O_constant
6763 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6764 {
29b0f896
AM		 6765 /* Handle complex expressions. */
6766 sym = make_expr_symbol (i.op[0].disps);
6767 off = 0;
6768 }
3e73aa7c 6769
29b0f896
AM		 6770 /* 1 possible extra opcode + 4 byte displacement go in var part.
6771 Pass reloc in fr_var. */
d258b828 6772 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6773}
3e73aa7c 6774
29b0f896 6775static void
e3bb37b5 6776output_jump (void)
29b0f896
AM		 6777{
6778 char *p;
6779 int size;
3e02c1cc 6780 fixS *fixP;
29b0f896 6781
40fb9820 6782 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6783 {
6784 /* This is a loop or jecxz type instruction. */
6785 size = 1;
6786 if (i.prefix[ADDR_PREFIX] != 0)
6787 {
6788 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6789 i.prefixes -= 1;
6790 }
6791 /* Pentium4 branch hints. */
6792 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6793 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6794 {
6795 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6796 i.prefixes--;
3e73aa7c
JH		 6797 }
6798 }
29b0f896
AM		 6799 else
6800 {
6801 int code16;
3e73aa7c 6802
29b0f896
AM		 6803 code16 = 0;
6804 if (flag_code == CODE_16BIT)
6805 code16 = CODE16;
3e73aa7c 6806
29b0f896
AM		 6807 if (i.prefix[DATA_PREFIX] != 0)
6808 {
6809 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6810 i.prefixes -= 1;
6811 code16 ^= CODE16;
6812 }
252b5132 6813
29b0f896
AM		 6814 size = 4;
6815 if (code16)
6816 size = 2;
6817 }
9fcc94b6 6818
29b0f896
AM		 6819 if (i.prefix[REX_PREFIX] != 0)
6820 {
6821 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6822 i.prefixes -= 1;
6823 }
252b5132 6824
7e8b059b
L		 6825 /* BND prefixed jump. */
6826 if (i.prefix[BND_PREFIX] != 0)
6827 {
6828 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6829 i.prefixes -= 1;
6830 }
6831
29b0f896
AM		 6832 if (i.prefixes != 0 && !intel_syntax)
6833 as_warn (_("skipping prefixes on this instruction"));
e0890092 6834
42164a71
L		 6835 p = frag_more (i.tm.opcode_length + size);
6836 switch (i.tm.opcode_length)
6837 {
6838 case 2:
6839 *p++ = i.tm.base_opcode >> 8;
6840 case 1:
6841 *p++ = i.tm.base_opcode;
6842 break;
6843 default:
6844 abort ();
6845 }
e0890092 6846
3e02c1cc 6847 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6848 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6849
6850 /* All jumps handled here are signed, but don't use a signed limit
6851 check for 32 and 16 bit jumps as we want to allow wrap around at
6852 4G and 64k respectively. */
6853 if (size == 1)
6854 fixP->fx_signed = 1;
29b0f896 6855}
e0890092 6856
29b0f896 6857static void
e3bb37b5 6858output_interseg_jump (void)
29b0f896
AM		 6859{
6860 char *p;
6861 int size;
6862 int prefix;
6863 int code16;
252b5132 6864
29b0f896
AM		 6865 code16 = 0;
6866 if (flag_code == CODE_16BIT)
6867 code16 = CODE16;
a217f122 6868
29b0f896
AM		 6869 prefix = 0;
6870 if (i.prefix[DATA_PREFIX] != 0)
6871 {
6872 prefix = 1;
6873 i.prefixes -= 1;
6874 code16 ^= CODE16;
6875 }
6876 if (i.prefix[REX_PREFIX] != 0)
6877 {
6878 prefix++;
6879 i.prefixes -= 1;
6880 }
252b5132 6881
29b0f896
AM		 6882 size = 4;
6883 if (code16)
6884 size = 2;
252b5132 6885
29b0f896
AM		 6886 if (i.prefixes != 0 && !intel_syntax)
6887 as_warn (_("skipping prefixes on this instruction"));
252b5132 6888
29b0f896
AM		 6889 /* 1 opcode; 2 segment; offset */
6890 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6891
29b0f896
AM		 6892 if (i.prefix[DATA_PREFIX] != 0)
6893 *p++ = DATA_PREFIX_OPCODE;
252b5132 6894
29b0f896
AM		 6895 if (i.prefix[REX_PREFIX] != 0)
6896 *p++ = i.prefix[REX_PREFIX];
252b5132 6897
29b0f896
AM		 6898 *p++ = i.tm.base_opcode;
6899 if (i.op[1].imms->X_op == O_constant)
6900 {
6901 offsetT n = i.op[1].imms->X_add_number;
252b5132 6902
29b0f896
AM		 6903 if (size == 2
6904 && !fits_in_unsigned_word (n)
6905 && !fits_in_signed_word (n))
6906 {
6907 as_bad (_("16-bit jump out of range"));
6908 return;
6909 }
6910 md_number_to_chars (p, n, size);
6911 }
6912 else
6913 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6914 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6915 if (i.op[0].imms->X_op != O_constant)
6916 as_bad (_("can't handle non absolute segment in `%s'"),
6917 i.tm.name);
6918 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6919}
a217f122 6920
29b0f896 6921static void
e3bb37b5 6922output_insn (void)
29b0f896 6923{
2bbd9c25
JJ		 6924 fragS *insn_start_frag;
6925 offsetT insn_start_off;
6926
29b0f896
AM		 6927 /* Tie dwarf2 debug info to the address at the start of the insn.
6928 We can't do this after the insn has been output as the current
6929 frag may have been closed off. eg. by frag_var. */
6930 dwarf2_emit_insn (0);
6931
2bbd9c25
JJ		 6932 insn_start_frag = frag_now;
6933 insn_start_off = frag_now_fix ();
6934
29b0f896 6935 /* Output jumps. */
40fb9820 6936 if (i.tm.opcode_modifier.jump)
29b0f896 6937 output_branch ();
40fb9820
L		 6938 else if (i.tm.opcode_modifier.jumpbyte
6939 || i.tm.opcode_modifier.jumpdword)
29b0f896 6940 output_jump ();
40fb9820 6941 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6942 output_interseg_jump ();
6943 else
6944 {
6945 /* Output normal instructions here. */
6946 char *p;
6947 unsigned char *q;
47465058 6948 unsigned int j;
331d2d0d 6949 unsigned int prefix;
4dffcebc 6950
d022bddd
IT		 6951 /* Some processors fail on LOCK prefix. This options makes
6952 assembler ignore LOCK prefix and serves as a workaround. */
6953 if (omit_lock_prefix)
6954 {
6955 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6956 return;
6957 i.prefix[LOCK_PREFIX] = 0;
6958 }
6959
43234a1e
L		 6960 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6961 don't need the explicit prefix. */
6962 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6963 {
c0f3af97 6964 switch (i.tm.opcode_length)
bc4bd9ab 6965 {
c0f3af97
L		 6966 case 3:
6967 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6968 {
c0f3af97
L		 6969 prefix = (i.tm.base_opcode >> 24) & 0xff;
6970 goto check_prefix;
6971 }
6972 break;
6973 case 2:
6974 if ((i.tm.base_opcode & 0xff0000) != 0)
6975 {
6976 prefix = (i.tm.base_opcode >> 16) & 0xff;
6977 if (i.tm.cpu_flags.bitfield.cpupadlock)
6978 {
4dffcebc 6979check_prefix:
c0f3af97 6980 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6981 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6982 != REPE_PREFIX_OPCODE))
6983 add_prefix (prefix);
6984 }
6985 else
4dffcebc
L		 6986 add_prefix (prefix);
6987 }
c0f3af97
L		 6988 break;
6989 case 1:
6990 break;
6991 default:
6992 abort ();
bc4bd9ab 6993 }
c0f3af97 6994
6d19a37a 6995#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6996 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6997 R_X86_64_GOTTPOFF relocation so that linker can safely
6998 perform IE->LE optimization. */
6999 if (x86_elf_abi == X86_64_X32_ABI
7000 && i.operands == 2
7001 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7002 && i.prefix[REX_PREFIX] == 0)
7003 add_prefix (REX_OPCODE);
6d19a37a 7004#endif
cf61b747 7005
c0f3af97
L		 7006 /* The prefix bytes. */
7007 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7008 if (*q)
7009 FRAG_APPEND_1_CHAR (*q);
0f10071e 7010 }
ae5c1c7b 7011 else
c0f3af97
L		 7012 {
7013 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7014 if (*q)
7015 switch (j)
7016 {
7017 case REX_PREFIX:
7018 /* REX byte is encoded in VEX prefix. */
7019 break;
7020 case SEG_PREFIX:
7021 case ADDR_PREFIX:
7022 FRAG_APPEND_1_CHAR (*q);
7023 break;
7024 default:
7025 /* There should be no other prefixes for instructions
7026 with VEX prefix. */
7027 abort ();
7028 }
7029
43234a1e
L		 7030 /* For EVEX instructions i.vrex should become 0 after
7031 build_evex_prefix. For VEX instructions upper 16 registers
7032 aren't available, so VREX should be 0. */
7033 if (i.vrex)
7034 abort ();
c0f3af97
L		 7035 /* Now the VEX prefix. */
7036 p = frag_more (i.vex.length);
7037 for (j = 0; j < i.vex.length; j++)
7038 p[j] = i.vex.bytes[j];
7039 }
252b5132 7040
29b0f896 7041 /* Now the opcode; be careful about word order here! */
4dffcebc 7042 if (i.tm.opcode_length == 1)
29b0f896
AM		 7043 {
7044 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7045 }
7046 else
7047 {
4dffcebc 7048 switch (i.tm.opcode_length)
331d2d0d 7049 {
43234a1e
L		 7050 case 4:
7051 p = frag_more (4);
7052 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7053 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7054 break;
4dffcebc 7055 case 3:
331d2d0d
L		 7056 p = frag_more (3);
7057 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7058 break;
7059 case 2:
7060 p = frag_more (2);
7061 break;
7062 default:
7063 abort ();
7064 break;
331d2d0d 7065 }
0f10071e 7066
29b0f896
AM		 7067 /* Put out high byte first: can't use md_number_to_chars! */
7068 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7069 *p = i.tm.base_opcode & 0xff;
7070 }
3e73aa7c 7071
29b0f896 7072 /* Now the modrm byte and sib byte (if present). */
40fb9820 7073 if (i.tm.opcode_modifier.modrm)
29b0f896 7074 {
4a3523fa
L		 7075 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7076 | i.rm.reg << 3
7077 | i.rm.mode << 6));
29b0f896
AM		 7078 /* If i.rm.regmem == ESP (4)
7079 && i.rm.mode != (Register mode)
7080 && not 16 bit
7081 ==> need second modrm byte. */
7082 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7083 && i.rm.mode != 3
40fb9820 7084 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7085 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7086 | i.sib.index << 3
7087 | i.sib.scale << 6));
29b0f896 7088 }
3e73aa7c 7089
29b0f896 7090 if (i.disp_operands)
2bbd9c25 7091 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7092
29b0f896 7093 if (i.imm_operands)
2bbd9c25 7094 output_imm (insn_start_frag, insn_start_off);
29b0f896 7095 }
252b5132 7096
29b0f896
AM		 7097#ifdef DEBUG386
7098 if (flag_debug)
7099 {
7b81dfbb 7100 pi ("" /*line*/, &i);
29b0f896
AM		 7101 }
7102#endif /* DEBUG386 */
7103}
252b5132 7104
e205caa7
L		 7105/* Return the size of the displacement operand N. */
7106
7107static int
7108disp_size (unsigned int n)
7109{
7110 int size = 4;
43234a1e
L		 7111
7112 /* Vec_Disp8 has to be 8bit. */
7113 if (i.types[n].bitfield.vec_disp8)
7114 size = 1;
7115 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7116 size = 8;
7117 else if (i.types[n].bitfield.disp8)
7118 size = 1;
7119 else if (i.types[n].bitfield.disp16)
7120 size = 2;
e205caa7
L		 7121 return size;
7122}
7123
7124/* Return the size of the immediate operand N. */
7125
7126static int
7127imm_size (unsigned int n)
7128{
7129 int size = 4;
40fb9820
L		 7130 if (i.types[n].bitfield.imm64)
7131 size = 8;
7132 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7133 size = 1;
7134 else if (i.types[n].bitfield.imm16)
7135 size = 2;
e205caa7
L		 7136 return size;
7137}
7138
29b0f896 7139static void
64e74474 7140output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7141{
7142 char *p;
7143 unsigned int n;
252b5132 7144
29b0f896
AM		 7145 for (n = 0; n < i.operands; n++)
7146 {
43234a1e
L		 7147 if (i.types[n].bitfield.vec_disp8
7148 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7149 {
7150 if (i.op[n].disps->X_op == O_constant)
7151 {
e205caa7 7152 int size = disp_size (n);
43234a1e 7153 offsetT val = i.op[n].disps->X_add_number;
252b5132 7154
43234a1e
L		 7155 if (i.types[n].bitfield.vec_disp8)
7156 val >>= i.memshift;
7157 val = offset_in_range (val, size);
29b0f896
AM		 7158 p = frag_more (size);
7159 md_number_to_chars (p, val, size);
7160 }
7161 else
7162 {
f86103b7 7163 enum bfd_reloc_code_real reloc_type;
e205caa7 7164 int size = disp_size (n);
40fb9820 7165 int sign = i.types[n].bitfield.disp32s;
29b0f896 7166 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7167 fixS *fixP;
29b0f896 7168
e205caa7 7169 /* We can't have 8 bit displacement here. */
9c2799c2 7170 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7171
29b0f896
AM		 7172 /* The PC relative address is computed relative
7173 to the instruction boundary, so in case immediate
7174 fields follows, we need to adjust the value. */
7175 if (pcrel && i.imm_operands)
7176 {
29b0f896 7177 unsigned int n1;
e205caa7 7178 int sz = 0;
252b5132 7179
29b0f896 7180 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7181 if (operand_type_check (i.types[n1], imm))
252b5132 7182 {
e205caa7
L		 7183 /* Only one immediate is allowed for PC
7184 relative address. */
9c2799c2 7185 gas_assert (sz == 0);
e205caa7
L		 7186 sz = imm_size (n1);
7187 i.op[n].disps->X_add_number -= sz;
252b5132 7188 }
29b0f896 7189 /* We should find the immediate. */
9c2799c2 7190 gas_assert (sz != 0);
29b0f896 7191 }
520dc8e8 7192
29b0f896 7193 p = frag_more (size);
d258b828 7194 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7195 if (GOT_symbol
2bbd9c25 7196 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7197 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7198 || reloc_type == BFD_RELOC_X86_64_32S
7199 || (reloc_type == BFD_RELOC_64
7200 && object_64bit))
d6ab8113
JB		 7201 && (i.op[n].disps->X_op == O_symbol
7202 || (i.op[n].disps->X_op == O_add
7203 && ((symbol_get_value_expression
7204 (i.op[n].disps->X_op_symbol)->X_op)
7205 == O_subtract))))
7206 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7207 {
7208 offsetT add;
7209
7210 if (insn_start_frag == frag_now)
7211 add = (p - frag_now->fr_literal) - insn_start_off;
7212 else
7213 {
7214 fragS *fr;
7215
7216 add = insn_start_frag->fr_fix - insn_start_off;
7217 for (fr = insn_start_frag->fr_next;
7218 fr && fr != frag_now; fr = fr->fr_next)
7219 add += fr->fr_fix;
7220 add += p - frag_now->fr_literal;
7221 }
7222
4fa24527 7223 if (!object_64bit)
7b81dfbb
AJ		 7224 {
7225 reloc_type = BFD_RELOC_386_GOTPC;
7226 i.op[n].imms->X_add_number += add;
7227 }
7228 else if (reloc_type == BFD_RELOC_64)
7229 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7230 else
7b81dfbb
AJ		 7231 /* Don't do the adjustment for x86-64, as there
7232 the pcrel addressing is relative to the _next_
7233 insn, and that is taken care of in other code. */
d6ab8113 7234 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7235 }
02a86693
L		 7236 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7237 size, i.op[n].disps, pcrel,
7238 reloc_type);
7239 /* Check for "call/jmp *mem", "mov mem, %reg",
7240 "test %reg, mem" and "binop mem, %reg" where binop
7241 is one of adc, add, and, cmp, or, sbb, sub, xor
7242 instructions. */
7243 if ((i.rm.mode == 2
7244 || (i.rm.mode == 0 && i.rm.regmem == 5))
7245 && ((i.operands == 1
7246 && i.tm.base_opcode == 0xff
7247 && (i.rm.reg == 2 || i.rm.reg == 4))
7248 || (i.operands == 2
7249 && (i.tm.base_opcode == 0x8b
7250 || i.tm.base_opcode == 0x85
7251 || (i.tm.base_opcode & 0xc7) == 0x03))))
7252 {
7253 if (object_64bit)
7254 {
7255 fixP->fx_tcbit = i.rex != 0;
7256 if (i.base_reg
7257 && (i.base_reg->reg_num == RegRip
7258 || i.base_reg->reg_num == RegEip))
7259 fixP->fx_tcbit2 = 1;
7260 }
7261 else
7262 fixP->fx_tcbit2 = 1;
7263 }
29b0f896
AM		 7264 }
7265 }
7266 }
7267}
252b5132 7268
29b0f896 7269static void
64e74474 7270output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7271{
7272 char *p;
7273 unsigned int n;
252b5132 7274
29b0f896
AM		 7275 for (n = 0; n < i.operands; n++)
7276 {
43234a1e
L		 7277 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7278 if (i.rounding && (int) n == i.rounding->operand)
7279 continue;
7280
40fb9820 7281 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7282 {
7283 if (i.op[n].imms->X_op == O_constant)
7284 {
e205caa7 7285 int size = imm_size (n);
29b0f896 7286 offsetT val;
b4cac588 7287
29b0f896
AM		 7288 val = offset_in_range (i.op[n].imms->X_add_number,
7289 size);
7290 p = frag_more (size);
7291 md_number_to_chars (p, val, size);
7292 }
7293 else
7294 {
7295 /* Not absolute_section.
7296 Need a 32-bit fixup (don't support 8bit
7297 non-absolute imms). Try to support other
7298 sizes ... */
f86103b7 7299 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7300 int size = imm_size (n);
7301 int sign;
29b0f896 7302
40fb9820 7303 if (i.types[n].bitfield.imm32s
a7d61044 7304 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7305 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7306 sign = 1;
e205caa7
L		 7307 else
7308 sign = 0;
520dc8e8 7309
29b0f896 7310 p = frag_more (size);
d258b828 7311 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7312
2bbd9c25
JJ		 7313 /* This is tough to explain. We end up with this one if we
7314 * have operands that look like
7315 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7316 * obtain the absolute address of the GOT, and it is strongly
7317 * preferable from a performance point of view to avoid using
7318 * a runtime relocation for this. The actual sequence of
7319 * instructions often look something like:
7320 *
7321 * call .L66
7322 * .L66:
7323 * popl %ebx
7324 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7325 *
7326 * The call and pop essentially return the absolute address
7327 * of the label .L66 and store it in %ebx. The linker itself
7328 * will ultimately change the first operand of the addl so
7329 * that %ebx points to the GOT, but to keep things simple, the
7330 * .o file must have this operand set so that it generates not
7331 * the absolute address of .L66, but the absolute address of
7332 * itself. This allows the linker itself simply treat a GOTPC
7333 * relocation as asking for a pcrel offset to the GOT to be
7334 * added in, and the addend of the relocation is stored in the
7335 * operand field for the instruction itself.
7336 *
7337 * Our job here is to fix the operand so that it would add
7338 * the correct offset so that %ebx would point to itself. The
7339 * thing that is tricky is that .-.L66 will point to the
7340 * beginning of the instruction, so we need to further modify
7341 * the operand so that it will point to itself. There are
7342 * other cases where you have something like:
7343 *
7344 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7345 *
7346 * and here no correction would be required. Internally in
7347 * the assembler we treat operands of this form as not being
7348 * pcrel since the '.' is explicitly mentioned, and I wonder
7349 * whether it would simplify matters to do it this way. Who
7350 * knows. In earlier versions of the PIC patches, the
7351 * pcrel_adjust field was used to store the correction, but
7352 * since the expression is not pcrel, I felt it would be
7353 * confusing to do it this way. */
7354
d6ab8113 7355 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7356 || reloc_type == BFD_RELOC_X86_64_32S
7357 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7358 && GOT_symbol
7359 && GOT_symbol == i.op[n].imms->X_add_symbol
7360 && (i.op[n].imms->X_op == O_symbol
7361 || (i.op[n].imms->X_op == O_add
7362 && ((symbol_get_value_expression
7363 (i.op[n].imms->X_op_symbol)->X_op)
7364 == O_subtract))))
7365 {
2bbd9c25
JJ		 7366 offsetT add;
7367
7368 if (insn_start_frag == frag_now)
7369 add = (p - frag_now->fr_literal) - insn_start_off;
7370 else
7371 {
7372 fragS *fr;
7373
7374 add = insn_start_frag->fr_fix - insn_start_off;
7375 for (fr = insn_start_frag->fr_next;
7376 fr && fr != frag_now; fr = fr->fr_next)
7377 add += fr->fr_fix;
7378 add += p - frag_now->fr_literal;
7379 }
7380
4fa24527 7381 if (!object_64bit)
d6ab8113 7382 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7383 else if (size == 4)
d6ab8113 7384 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7385 else if (size == 8)
7386 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7387 i.op[n].imms->X_add_number += add;
29b0f896 7388 }
29b0f896
AM		 7389 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7390 i.op[n].imms, 0, reloc_type);
7391 }
7392 }
7393 }
252b5132
RH		 7394}
7395\f
d182319b
JB		 7396/* x86_cons_fix_new is called via the expression parsing code when a
7397 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7398static int cons_sign = -1;
7399
7400void
e3bb37b5 7401x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7402 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7403{
d258b828 7404 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7405
7406#ifdef TE_PE
7407 if (exp->X_op == O_secrel)
7408 {
7409 exp->X_op = O_symbol;
7410 r = BFD_RELOC_32_SECREL;
7411 }
7412#endif
7413
7414 fix_new_exp (frag, off, len, exp, 0, r);
7415}
7416
357d1bd8
L		 7417/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7418 purpose of the `.dc.a' internal pseudo-op. */
7419
7420int
7421x86_address_bytes (void)
7422{
7423 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7424 return 4;
7425 return stdoutput->arch_info->bits_per_address / 8;
7426}
7427
d382c579
TG		 7428#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7429 || defined (LEX_AT)
d258b828 7430# define lex_got(reloc, adjust, types) NULL
718ddfc0 7431#else
f3c180ae
AM		 7432/* Parse operands of the form
7433 <symbol>@GOTOFF+<nnn>
7434 and similar .plt or .got references.
7435
7436 If we find one, set up the correct relocation in RELOC and copy the
7437 input string, minus the `@GOTOFF' into a malloc'd buffer for
7438 parsing by the calling routine. Return this buffer, and if ADJUST
7439 is non-null set it to the length of the string we removed from the
7440 input line. Otherwise return NULL. */
7441static char *
91d6fa6a 7442lex_got (enum bfd_reloc_code_real *rel,
64e74474 7443 int *adjust,
d258b828 7444 i386_operand_type *types)
f3c180ae 7445{
7b81dfbb
AJ		 7446 /* Some of the relocations depend on the size of what field is to
7447 be relocated. But in our callers i386_immediate and i386_displacement
7448 we don't yet know the operand size (this will be set by insn
7449 matching). Hence we record the word32 relocation here,
7450 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7451 static const struct {
7452 const char *str;
cff8d58a 7453 int len;
4fa24527 7454 const enum bfd_reloc_code_real rel[2];
40fb9820 7455 const i386_operand_type types64;
f3c180ae 7456 } gotrel[] = {
8ce3d284 7457#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7458 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7459 BFD_RELOC_SIZE32 },
7460 OPERAND_TYPE_IMM32_64 },
8ce3d284 7461#endif
cff8d58a
L		 7462 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7463 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7464 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7465 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7466 BFD_RELOC_X86_64_PLT32 },
40fb9820 7467 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7468 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7469 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7470 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7471 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7472 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7473 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7474 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7475 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7476 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7477 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7478 BFD_RELOC_X86_64_TLSGD },
40fb9820 7479 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7480 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7481 _dummy_first_bfd_reloc_code_real },
40fb9820 7482 OPERAND_TYPE_NONE },
cff8d58a
L		 7483 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7484 BFD_RELOC_X86_64_TLSLD },
40fb9820 7485 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7486 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7487 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7488 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7489 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7490 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7491 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7492 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7493 _dummy_first_bfd_reloc_code_real },
40fb9820 7494 OPERAND_TYPE_NONE },
cff8d58a
L		 7495 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7496 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7497 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7498 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7499 _dummy_first_bfd_reloc_code_real },
40fb9820 7500 OPERAND_TYPE_NONE },
cff8d58a
L		 7501 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7502 _dummy_first_bfd_reloc_code_real },
40fb9820 7503 OPERAND_TYPE_NONE },
cff8d58a
L		 7504 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7505 BFD_RELOC_X86_64_GOT32 },
40fb9820 7506 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7507 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7508 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7509 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7510 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7511 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7512 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7513 };
7514 char *cp;
7515 unsigned int j;
7516
d382c579 7517#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7518 if (!IS_ELF)
7519 return NULL;
d382c579 7520#endif
718ddfc0 7521
f3c180ae 7522 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7523 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7524 return NULL;
7525
47465058 7526 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7527 {
cff8d58a 7528 int len = gotrel[j].len;
28f81592 7529 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7530 {
4fa24527 7531 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7532 {
28f81592
AM		 7533 int first, second;
7534 char *tmpbuf, *past_reloc;
f3c180ae 7535
91d6fa6a 7536 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7537
3956db08
JB		 7538 if (types)
7539 {
7540 if (flag_code != CODE_64BIT)
40fb9820
L		 7541 {
7542 types->bitfield.imm32 = 1;
7543 types->bitfield.disp32 = 1;
7544 }
3956db08
JB		 7545 else
7546 *types = gotrel[j].types64;
7547 }
7548
8fd4256d 7549 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7550 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7551
28f81592 7552 /* The length of the first part of our input line. */
f3c180ae 7553 first = cp - input_line_pointer;
28f81592
AM		 7554
7555 /* The second part goes from after the reloc token until
67c11a9b 7556 (and including) an end_of_line char or comma. */
28f81592 7557 past_reloc = cp + 1 + len;
67c11a9b
AM		 7558 cp = past_reloc;
7559 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7560 ++cp;
7561 second = cp + 1 - past_reloc;
28f81592
AM		 7562
7563 /* Allocate and copy string. The trailing NUL shouldn't
7564 be necessary, but be safe. */
1e9cc1c2 7565 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7566 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7567 if (second != 0 && *past_reloc != ' ')
7568 /* Replace the relocation token with ' ', so that
7569 errors like foo@GOTOFF1 will be detected. */
7570 tmpbuf[first++] = ' ';
af89796a
L		 7571 else
7572 /* Increment length by 1 if the relocation token is
7573 removed. */
7574 len++;
7575 if (adjust)
7576 *adjust = len;
0787a12d
AM		 7577 memcpy (tmpbuf + first, past_reloc, second);
7578 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7579 return tmpbuf;
7580 }
7581
4fa24527
JB		 7582 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7583 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7584 return NULL;
7585 }
7586 }
7587
7588 /* Might be a symbol version string. Don't as_bad here. */
7589 return NULL;
7590}
4e4f7c87 7591#endif
f3c180ae 7592
a988325c
NC		 7593#ifdef TE_PE
7594#ifdef lex_got
7595#undef lex_got
7596#endif
7597/* Parse operands of the form
7598 <symbol>@SECREL32+<nnn>
7599
7600 If we find one, set up the correct relocation in RELOC and copy the
7601 input string, minus the `@SECREL32' into a malloc'd buffer for
7602 parsing by the calling routine. Return this buffer, and if ADJUST
7603 is non-null set it to the length of the string we removed from the
34bca508
L		 7604 input line. Otherwise return NULL.
7605
a988325c
NC		 7606 This function is copied from the ELF version above adjusted for PE targets. */
7607
7608static char *
7609lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7610 int *adjust ATTRIBUTE_UNUSED,
d258b828 7611 i386_operand_type *types)
a988325c
NC		 7612{
7613 static const struct
7614 {
7615 const char *str;
7616 int len;
7617 const enum bfd_reloc_code_real rel[2];
7618 const i386_operand_type types64;
7619 }
7620 gotrel[] =
7621 {
7622 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7623 BFD_RELOC_32_SECREL },
7624 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7625 };
7626
7627 char *cp;
7628 unsigned j;
7629
7630 for (cp = input_line_pointer; *cp != '@'; cp++)
7631 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7632 return NULL;
7633
7634 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7635 {
7636 int len = gotrel[j].len;
7637
7638 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7639 {
7640 if (gotrel[j].rel[object_64bit] != 0)
7641 {
7642 int first, second;
7643 char *tmpbuf, *past_reloc;
7644
7645 *rel = gotrel[j].rel[object_64bit];
7646 if (adjust)
7647 *adjust = len;
7648
7649 if (types)
7650 {
7651 if (flag_code != CODE_64BIT)
7652 {
7653 types->bitfield.imm32 = 1;
7654 types->bitfield.disp32 = 1;
7655 }
7656 else
7657 *types = gotrel[j].types64;
7658 }
7659
7660 /* The length of the first part of our input line. */
7661 first = cp - input_line_pointer;
7662
7663 /* The second part goes from after the reloc token until
7664 (and including) an end_of_line char or comma. */
7665 past_reloc = cp + 1 + len;
7666 cp = past_reloc;
7667 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7668 ++cp;
7669 second = cp + 1 - past_reloc;
7670
7671 /* Allocate and copy string. The trailing NUL shouldn't
7672 be necessary, but be safe. */
7673 tmpbuf = (char *) xmalloc (first + second + 2);
7674 memcpy (tmpbuf, input_line_pointer, first);
7675 if (second != 0 && *past_reloc != ' ')
7676 /* Replace the relocation token with ' ', so that
7677 errors like foo@SECLREL321 will be detected. */
7678 tmpbuf[first++] = ' ';
7679 memcpy (tmpbuf + first, past_reloc, second);
7680 tmpbuf[first + second] = '\0';
7681 return tmpbuf;
7682 }
7683
7684 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7685 gotrel[j].str, 1 << (5 + object_64bit));
7686 return NULL;
7687 }
7688 }
7689
7690 /* Might be a symbol version string. Don't as_bad here. */
7691 return NULL;
7692}
7693
7694#endif /* TE_PE */
7695
62ebcb5c 7696bfd_reloc_code_real_type
e3bb37b5 7697x86_cons (expressionS *exp, int size)
f3c180ae 7698{
62ebcb5c
AM		 7699 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7700
ee86248c
JB		 7701 intel_syntax = -intel_syntax;
7702
3c7b9c2c 7703 exp->X_md = 0;
4fa24527 7704 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7705 {
7706 /* Handle @GOTOFF and the like in an expression. */
7707 char *save;
7708 char *gotfree_input_line;
4a57f2cf 7709 int adjust = 0;
f3c180ae
AM		 7710
7711 save = input_line_pointer;
d258b828 7712 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7713 if (gotfree_input_line)
7714 input_line_pointer = gotfree_input_line;
7715
7716 expression (exp);
7717
7718 if (gotfree_input_line)
7719 {
7720 /* expression () has merrily parsed up to the end of line,
7721 or a comma - in the wrong buffer. Transfer how far
7722 input_line_pointer has moved to the right buffer. */
7723 input_line_pointer = (save
7724 + (input_line_pointer - gotfree_input_line)
7725 + adjust);
7726 free (gotfree_input_line);
3992d3b7
AM		 7727 if (exp->X_op == O_constant
7728 || exp->X_op == O_absent
7729 || exp->X_op == O_illegal
0398aac5 7730 || exp->X_op == O_register
3992d3b7
AM		 7731 || exp->X_op == O_big)
7732 {
7733 char c = *input_line_pointer;
7734 *input_line_pointer = 0;
7735 as_bad (_("missing or invalid expression `%s'"), save);
7736 *input_line_pointer = c;
7737 }
f3c180ae
AM		 7738 }
7739 }
7740 else
7741 expression (exp);
ee86248c
JB		 7742
7743 intel_syntax = -intel_syntax;
7744
7745 if (intel_syntax)
7746 i386_intel_simplify (exp);
62ebcb5c
AM		 7747
7748 return got_reloc;
f3c180ae 7749}
f3c180ae 7750
9f32dd5b
L		 7751static void
7752signed_cons (int size)
6482c264 7753{
d182319b
JB		 7754 if (flag_code == CODE_64BIT)
7755 cons_sign = 1;
7756 cons (size);
7757 cons_sign = -1;
6482c264
NC		 7758}
7759
d182319b 7760#ifdef TE_PE
6482c264 7761static void
7016a5d5 7762pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7763{
7764 expressionS exp;
7765
7766 do
7767 {
7768 expression (&exp);
7769 if (exp.X_op == O_symbol)
7770 exp.X_op = O_secrel;
7771
7772 emit_expr (&exp, 4);
7773 }
7774 while (*input_line_pointer++ == ',');
7775
7776 input_line_pointer--;
7777 demand_empty_rest_of_line ();
7778}
6482c264
NC		 7779#endif
7780
43234a1e
L		 7781/* Handle Vector operations. */
7782
7783static char *
7784check_VecOperations (char *op_string, char *op_end)
7785{
7786 const reg_entry *mask;
7787 const char *saved;
7788 char *end_op;
7789
7790 while (*op_string
7791 && (op_end == NULL || op_string < op_end))
7792 {
7793 saved = op_string;
7794 if (*op_string == '{')
7795 {
7796 op_string++;
7797
7798 /* Check broadcasts. */
7799 if (strncmp (op_string, "1to", 3) == 0)
7800 {
7801 int bcst_type;
7802
7803 if (i.broadcast)
7804 goto duplicated_vec_op;
7805
7806 op_string += 3;
7807 if (*op_string == '8')
7808 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7809 else if (*op_string == '4')
7810 bcst_type = BROADCAST_1TO4;
7811 else if (*op_string == '2')
7812 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7813 else if (*op_string == '1'
7814 && *(op_string+1) == '6')
7815 {
7816 bcst_type = BROADCAST_1TO16;
7817 op_string++;
7818 }
7819 else
7820 {
7821 as_bad (_("Unsupported broadcast: `%s'"), saved);
7822 return NULL;
7823 }
7824 op_string++;
7825
7826 broadcast_op.type = bcst_type;
7827 broadcast_op.operand = this_operand;
7828 i.broadcast = &broadcast_op;
7829 }
7830 /* Check masking operation. */
7831 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7832 {
7833 /* k0 can't be used for write mask. */
7834 if (mask->reg_num == 0)
7835 {
7836 as_bad (_("`%s' can't be used for write mask"),
7837 op_string);
7838 return NULL;
7839 }
7840
7841 if (!i.mask)
7842 {
7843 mask_op.mask = mask;
7844 mask_op.zeroing = 0;
7845 mask_op.operand = this_operand;
7846 i.mask = &mask_op;
7847 }
7848 else
7849 {
7850 if (i.mask->mask)
7851 goto duplicated_vec_op;
7852
7853 i.mask->mask = mask;
7854
7855 /* Only "{z}" is allowed here. No need to check
7856 zeroing mask explicitly. */
7857 if (i.mask->operand != this_operand)
7858 {
7859 as_bad (_("invalid write mask `%s'"), saved);
7860 return NULL;
7861 }
7862 }
7863
7864 op_string = end_op;
7865 }
7866 /* Check zeroing-flag for masking operation. */
7867 else if (*op_string == 'z')
7868 {
7869 if (!i.mask)
7870 {
7871 mask_op.mask = NULL;
7872 mask_op.zeroing = 1;
7873 mask_op.operand = this_operand;
7874 i.mask = &mask_op;
7875 }
7876 else
7877 {
7878 if (i.mask->zeroing)
7879 {
7880 duplicated_vec_op:
7881 as_bad (_("duplicated `%s'"), saved);
7882 return NULL;
7883 }
7884
7885 i.mask->zeroing = 1;
7886
7887 /* Only "{%k}" is allowed here. No need to check mask
7888 register explicitly. */
7889 if (i.mask->operand != this_operand)
7890 {
7891 as_bad (_("invalid zeroing-masking `%s'"),
7892 saved);
7893 return NULL;
7894 }
7895 }
7896
7897 op_string++;
7898 }
7899 else
7900 goto unknown_vec_op;
7901
7902 if (*op_string != '}')
7903 {
7904 as_bad (_("missing `}' in `%s'"), saved);
7905 return NULL;
7906 }
7907 op_string++;
7908 continue;
7909 }
7910 unknown_vec_op:
7911 /* We don't know this one. */
7912 as_bad (_("unknown vector operation: `%s'"), saved);
7913 return NULL;
7914 }
7915
7916 return op_string;
7917}
7918
252b5132 7919static int
70e41ade 7920i386_immediate (char *imm_start)
252b5132
RH		 7921{
7922 char *save_input_line_pointer;
f3c180ae 7923 char *gotfree_input_line;
252b5132 7924 segT exp_seg = 0;
47926f60 7925 expressionS *exp;
40fb9820
L		 7926 i386_operand_type types;
7927
0dfbf9d7 7928 operand_type_set (&types, ~0);
252b5132
RH		 7929
7930 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7931 {
31b2323c
L		 7932 as_bad (_("at most %d immediate operands are allowed"),
7933 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7934 return 0;
7935 }
7936
7937 exp = &im_expressions[i.imm_operands++];
520dc8e8 7938 i.op[this_operand].imms = exp;
252b5132
RH		 7939
7940 if (is_space_char (*imm_start))
7941 ++imm_start;
7942
7943 save_input_line_pointer = input_line_pointer;
7944 input_line_pointer = imm_start;
7945
d258b828 7946 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7947 if (gotfree_input_line)
7948 input_line_pointer = gotfree_input_line;
252b5132
RH		 7949
7950 exp_seg = expression (exp);
7951
83183c0c 7952 SKIP_WHITESPACE ();
43234a1e
L		 7953
7954 /* Handle vector operations. */
7955 if (*input_line_pointer == '{')
7956 {
7957 input_line_pointer = check_VecOperations (input_line_pointer,
7958 NULL);
7959 if (input_line_pointer == NULL)
7960 return 0;
7961 }
7962
252b5132 7963 if (*input_line_pointer)
f3c180ae 7964 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7965
7966 input_line_pointer = save_input_line_pointer;
f3c180ae 7967 if (gotfree_input_line)
ee86248c
JB		 7968 {
7969 free (gotfree_input_line);
7970
7971 if (exp->X_op == O_constant || exp->X_op == O_register)
7972 exp->X_op = O_illegal;
7973 }
7974
7975 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7976}
252b5132 7977
ee86248c
JB		 7978static int
7979i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7980 i386_operand_type types, const char *imm_start)
7981{
7982 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7983 {
313c53d1
L		 7984 if (imm_start)
7985 as_bad (_("missing or invalid immediate expression `%s'"),
7986 imm_start);
3992d3b7 7987 return 0;
252b5132 7988 }
3e73aa7c 7989 else if (exp->X_op == O_constant)
252b5132 7990 {
47926f60 7991 /* Size it properly later. */
40fb9820 7992 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7993 /* If not 64bit, sign extend val. */
7994 if (flag_code != CODE_64BIT
4eed87de
AM		 7995 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7996 exp->X_add_number
7997 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7998 }
4c63da97 7999#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8000 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8001 && exp_seg != absolute_section
47926f60 8002 && exp_seg != text_section
24eab124
AM		 8003 && exp_seg != data_section
8004 && exp_seg != bss_section
8005 && exp_seg != undefined_section
f86103b7 8006 && !bfd_is_com_section (exp_seg))
252b5132 8007 {
d0b47220 8008 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8009 return 0;
8010 }
8011#endif
a841bdf5 8012 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8013 {
313c53d1
L		 8014 if (imm_start)
8015 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8016 return 0;
8017 }
252b5132
RH		 8018 else
8019 {
8020 /* This is an address. The size of the address will be
24eab124 8021 determined later, depending on destination register,
3e73aa7c 8022 suffix, or the default for the section. */
40fb9820
L		 8023 i.types[this_operand].bitfield.imm8 = 1;
8024 i.types[this_operand].bitfield.imm16 = 1;
8025 i.types[this_operand].bitfield.imm32 = 1;
8026 i.types[this_operand].bitfield.imm32s = 1;
8027 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8028 i.types[this_operand] = operand_type_and (i.types[this_operand],
8029 types);
252b5132
RH		 8030 }
8031
8032 return 1;
8033}
8034
551c1ca1 8035static char *
e3bb37b5 8036i386_scale (char *scale)
252b5132 8037{
551c1ca1
AM		 8038 offsetT val;
8039 char *save = input_line_pointer;
252b5132 8040
551c1ca1
AM		 8041 input_line_pointer = scale;
8042 val = get_absolute_expression ();
8043
8044 switch (val)
252b5132 8045 {
551c1ca1 8046 case 1:
252b5132
RH		 8047 i.log2_scale_factor = 0;
8048 break;
551c1ca1 8049 case 2:
252b5132
RH		 8050 i.log2_scale_factor = 1;
8051 break;
551c1ca1 8052 case 4:
252b5132
RH		 8053 i.log2_scale_factor = 2;
8054 break;
551c1ca1 8055 case 8:
252b5132
RH		 8056 i.log2_scale_factor = 3;
8057 break;
8058 default:
a724f0f4
JB		 8059 {
8060 char sep = *input_line_pointer;
8061
8062 *input_line_pointer = '\0';
8063 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8064 scale);
8065 *input_line_pointer = sep;
8066 input_line_pointer = save;
8067 return NULL;
8068 }
252b5132 8069 }
29b0f896 8070 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8071 {
8072 as_warn (_("scale factor of %d without an index register"),
24eab124 8073 1 << i.log2_scale_factor);
252b5132 8074 i.log2_scale_factor = 0;
252b5132 8075 }
551c1ca1
AM		 8076 scale = input_line_pointer;
8077 input_line_pointer = save;
8078 return scale;
252b5132
RH		 8079}
8080
252b5132 8081static int
e3bb37b5 8082i386_displacement (char *disp_start, char *disp_end)
252b5132 8083{
29b0f896 8084 expressionS *exp;
252b5132
RH		 8085 segT exp_seg = 0;
8086 char *save_input_line_pointer;
f3c180ae 8087 char *gotfree_input_line;
40fb9820
L		 8088 int override;
8089 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8090 int ret;
252b5132 8091
31b2323c
L		 8092 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8093 {
8094 as_bad (_("at most %d displacement operands are allowed"),
8095 MAX_MEMORY_OPERANDS);
8096 return 0;
8097 }
8098
0dfbf9d7 8099 operand_type_set (&bigdisp, 0);
40fb9820
L		 8100 if ((i.types[this_operand].bitfield.jumpabsolute)
8101 || (!current_templates->start->opcode_modifier.jump
8102 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8103 {
40fb9820 8104 bigdisp.bitfield.disp32 = 1;
e05278af 8105 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8106 if (flag_code == CODE_64BIT)
8107 {
8108 if (!override)
8109 {
8110 bigdisp.bitfield.disp32s = 1;
8111 bigdisp.bitfield.disp64 = 1;
8112 }
8113 }
8114 else if ((flag_code == CODE_16BIT) ^ override)
8115 {
8116 bigdisp.bitfield.disp32 = 0;
8117 bigdisp.bitfield.disp16 = 1;
8118 }
e05278af
JB		 8119 }
8120 else
8121 {
8122 /* For PC-relative branches, the width of the displacement
8123 is dependent upon data size, not address size. */
e05278af 8124 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8125 if (flag_code == CODE_64BIT)
8126 {
8127 if (override || i.suffix == WORD_MNEM_SUFFIX)
8128 bigdisp.bitfield.disp16 = 1;
8129 else
8130 {
8131 bigdisp.bitfield.disp32 = 1;
8132 bigdisp.bitfield.disp32s = 1;
8133 }
8134 }
8135 else
e05278af
JB		 8136 {
8137 if (!override)
8138 override = (i.suffix == (flag_code != CODE_16BIT
8139 ? WORD_MNEM_SUFFIX
8140 : LONG_MNEM_SUFFIX));
40fb9820
L		 8141 bigdisp.bitfield.disp32 = 1;
8142 if ((flag_code == CODE_16BIT) ^ override)
8143 {
8144 bigdisp.bitfield.disp32 = 0;
8145 bigdisp.bitfield.disp16 = 1;
8146 }
e05278af 8147 }
e05278af 8148 }
c6fb90c8
L		 8149 i.types[this_operand] = operand_type_or (i.types[this_operand],
8150 bigdisp);
252b5132
RH		 8151
8152 exp = &disp_expressions[i.disp_operands];
520dc8e8 8153 i.op[this_operand].disps = exp;
252b5132
RH		 8154 i.disp_operands++;
8155 save_input_line_pointer = input_line_pointer;
8156 input_line_pointer = disp_start;
8157 END_STRING_AND_SAVE (disp_end);
8158
8159#ifndef GCC_ASM_O_HACK
8160#define GCC_ASM_O_HACK 0
8161#endif
8162#if GCC_ASM_O_HACK
8163 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8164 if (i.types[this_operand].bitfield.baseIndex
24eab124 8165 && displacement_string_end[-1] == '+')
252b5132
RH		 8166 {
8167 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8168 constraint within gcc asm statements.
8169 For instance:
8170
8171 #define _set_tssldt_desc(n,addr,limit,type) \
8172 __asm__ __volatile__ ( \
8173 "movw %w2,%0\n\t" \
8174 "movw %w1,2+%0\n\t" \
8175 "rorl $16,%1\n\t" \
8176 "movb %b1,4+%0\n\t" \
8177 "movb %4,5+%0\n\t" \
8178 "movb $0,6+%0\n\t" \
8179 "movb %h1,7+%0\n\t" \
8180 "rorl $16,%1" \
8181 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8182
8183 This works great except that the output assembler ends
8184 up looking a bit weird if it turns out that there is
8185 no offset. You end up producing code that looks like:
8186
8187 #APP
8188 movw $235,(%eax)
8189 movw %dx,2+(%eax)
8190 rorl $16,%edx
8191 movb %dl,4+(%eax)
8192 movb $137,5+(%eax)
8193 movb $0,6+(%eax)
8194 movb %dh,7+(%eax)
8195 rorl $16,%edx
8196 #NO_APP
8197
47926f60 8198 So here we provide the missing zero. */
24eab124
AM		 8199
8200 *displacement_string_end = '0';
252b5132
RH		 8201 }
8202#endif
d258b828 8203 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8204 if (gotfree_input_line)
8205 input_line_pointer = gotfree_input_line;
252b5132 8206
24eab124 8207 exp_seg = expression (exp);
252b5132 8208
636c26b0
AM		 8209 SKIP_WHITESPACE ();
8210 if (*input_line_pointer)
8211 as_bad (_("junk `%s' after expression"), input_line_pointer);
8212#if GCC_ASM_O_HACK
8213 RESTORE_END_STRING (disp_end + 1);
8214#endif
636c26b0 8215 input_line_pointer = save_input_line_pointer;
636c26b0 8216 if (gotfree_input_line)
ee86248c
JB		 8217 {
8218 free (gotfree_input_line);
8219
8220 if (exp->X_op == O_constant || exp->X_op == O_register)
8221 exp->X_op = O_illegal;
8222 }
8223
8224 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8225
8226 RESTORE_END_STRING (disp_end);
8227
8228 return ret;
8229}
8230
8231static int
8232i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8233 i386_operand_type types, const char *disp_start)
8234{
8235 i386_operand_type bigdisp;
8236 int ret = 1;
636c26b0 8237
24eab124
AM		 8238 /* We do this to make sure that the section symbol is in
8239 the symbol table. We will ultimately change the relocation
47926f60 8240 to be relative to the beginning of the section. */
1ae12ab7 8241 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8242 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8243 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8244 {
636c26b0 8245 if (exp->X_op != O_symbol)
3992d3b7 8246 goto inv_disp;
636c26b0 8247
e5cb08ac 8248 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8249 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8250 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8251 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8252 exp->X_op = O_subtract;
8253 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8254 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8255 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8256 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8257 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8258 else
29b0f896 8259 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8260 }
252b5132 8261
3992d3b7
AM		 8262 else if (exp->X_op == O_absent
8263 || exp->X_op == O_illegal
ee86248c 8264 || exp->X_op == O_big)
2daf4fd8 8265 {
3992d3b7
AM		 8266 inv_disp:
8267 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8268 disp_start);
3992d3b7 8269 ret = 0;
2daf4fd8
AM		 8270 }
8271
0e1147d9
L		 8272 else if (flag_code == CODE_64BIT
8273 && !i.prefix[ADDR_PREFIX]
8274 && exp->X_op == O_constant)
8275 {
8276 /* Since displacement is signed extended to 64bit, don't allow
8277 disp32 and turn off disp32s if they are out of range. */
8278 i.types[this_operand].bitfield.disp32 = 0;
8279 if (!fits_in_signed_long (exp->X_add_number))
8280 {
8281 i.types[this_operand].bitfield.disp32s = 0;
8282 if (i.types[this_operand].bitfield.baseindex)
8283 {
8284 as_bad (_("0x%lx out range of signed 32bit displacement"),
8285 (long) exp->X_add_number);
8286 ret = 0;
8287 }
8288 }
8289 }
8290
4c63da97 8291#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8292 else if (exp->X_op != O_constant
8293 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8294 && exp_seg != absolute_section
8295 && exp_seg != text_section
8296 && exp_seg != data_section
8297 && exp_seg != bss_section
8298 && exp_seg != undefined_section
8299 && !bfd_is_com_section (exp_seg))
24eab124 8300 {
d0b47220 8301 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8302 ret = 0;
24eab124 8303 }
252b5132 8304#endif
3956db08 8305
40fb9820
L		 8306 /* Check if this is a displacement only operand. */
8307 bigdisp = i.types[this_operand];
8308 bigdisp.bitfield.disp8 = 0;
8309 bigdisp.bitfield.disp16 = 0;
8310 bigdisp.bitfield.disp32 = 0;
8311 bigdisp.bitfield.disp32s = 0;
8312 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8313 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8314 i.types[this_operand] = operand_type_and (i.types[this_operand],
8315 types);
3956db08 8316
3992d3b7 8317 return ret;
252b5132
RH		 8318}
8319
eecb386c 8320/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8321 Return 1 on success, 0 on a failure. */
8322
252b5132 8323static int
e3bb37b5 8324i386_index_check (const char *operand_string)
252b5132 8325{
fc0763e6 8326 const char *kind = "base/index";
be05d201
L		 8327 enum flag_code addr_mode;
8328
8329 if (i.prefix[ADDR_PREFIX])
8330 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8331 else
8332 {
8333 addr_mode = flag_code;
8334
24eab124 8335#if INFER_ADDR_PREFIX
be05d201
L		 8336 if (i.mem_operands == 0)
8337 {
8338 /* Infer address prefix from the first memory operand. */
8339 const reg_entry *addr_reg = i.base_reg;
8340
8341 if (addr_reg == NULL)
8342 addr_reg = i.index_reg;
eecb386c 8343
be05d201
L		 8344 if (addr_reg)
8345 {
8346 if (addr_reg->reg_num == RegEip
8347 || addr_reg->reg_num == RegEiz
8348 || addr_reg->reg_type.bitfield.reg32)
8349 addr_mode = CODE_32BIT;
8350 else if (flag_code != CODE_64BIT
8351 && addr_reg->reg_type.bitfield.reg16)
8352 addr_mode = CODE_16BIT;
8353
8354 if (addr_mode != flag_code)
8355 {
8356 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8357 i.prefixes += 1;
8358 /* Change the size of any displacement too. At most one
8359 of Disp16 or Disp32 is set.
8360 FIXME. There doesn't seem to be any real need for
8361 separate Disp16 and Disp32 flags. The same goes for
8362 Imm16 and Imm32. Removing them would probably clean
8363 up the code quite a lot. */
8364 if (flag_code != CODE_64BIT
8365 && (i.types[this_operand].bitfield.disp16
8366 || i.types[this_operand].bitfield.disp32))
8367 i.types[this_operand]
8368 = operand_type_xor (i.types[this_operand], disp16_32);
8369 }
8370 }
8371 }
24eab124 8372#endif
be05d201
L		 8373 }
8374
fc0763e6
JB		 8375 if (current_templates->start->opcode_modifier.isstring
8376 && !current_templates->start->opcode_modifier.immext
8377 && (current_templates->end[-1].opcode_modifier.isstring
8378 || i.mem_operands))
8379 {
8380 /* Memory operands of string insns are special in that they only allow
8381 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8382 const reg_entry *expected_reg;
8383 static const char *di_si[][2] =
8384 {
8385 { "esi", "edi" },
8386 { "si", "di" },
8387 { "rsi", "rdi" }
8388 };
8389 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8390
8391 kind = "string address";
8392
8393 if (current_templates->start->opcode_modifier.w)
8394 {
8395 i386_operand_type type = current_templates->end[-1].operand_types[0];
8396
8397 if (!type.bitfield.baseindex
8398 || ((!i.mem_operands != !intel_syntax)
8399 && current_templates->end[-1].operand_types[1]
8400 .bitfield.baseindex))
8401 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8402 expected_reg = hash_find (reg_hash,
8403 di_si[addr_mode][type.bitfield.esseg]);
8404
fc0763e6
JB		 8405 }
8406 else
be05d201 8407 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8408
be05d201
L		 8409 if (i.base_reg != expected_reg
8410 || i.index_reg
fc0763e6 8411 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8412 {
be05d201
L		 8413 /* The second memory operand must have the same size as
8414 the first one. */
8415 if (i.mem_operands
8416 && i.base_reg
8417 && !((addr_mode == CODE_64BIT
8418 && i.base_reg->reg_type.bitfield.reg64)
8419 || (addr_mode == CODE_32BIT
8420 ? i.base_reg->reg_type.bitfield.reg32
8421 : i.base_reg->reg_type.bitfield.reg16)))
8422 goto bad_address;
8423
fc0763e6
JB		 8424 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8425 operand_string,
8426 intel_syntax ? '[' : '(',
8427 register_prefix,
be05d201 8428 expected_reg->reg_name,
fc0763e6 8429 intel_syntax ? ']' : ')');
be05d201 8430 return 1;
fc0763e6 8431 }
be05d201
L		 8432 else
8433 return 1;
8434
8435bad_address:
8436 as_bad (_("`%s' is not a valid %s expression"),
8437 operand_string, kind);
8438 return 0;
3e73aa7c
JH		 8439 }
8440 else
8441 {
be05d201
L		 8442 if (addr_mode != CODE_16BIT)
8443 {
8444 /* 32-bit/64-bit checks. */
8445 if ((i.base_reg
8446 && (addr_mode == CODE_64BIT
8447 ? !i.base_reg->reg_type.bitfield.reg64
8448 : !i.base_reg->reg_type.bitfield.reg32)
8449 && (i.index_reg
8450 || (i.base_reg->reg_num
8451 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8452 || (i.index_reg
8453 && !i.index_reg->reg_type.bitfield.regxmm
8454 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8455 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8456 && ((addr_mode == CODE_64BIT
8457 ? !(i.index_reg->reg_type.bitfield.reg64
8458 || i.index_reg->reg_num == RegRiz)
8459 : !(i.index_reg->reg_type.bitfield.reg32
8460 || i.index_reg->reg_num == RegEiz))
8461 || !i.index_reg->reg_type.bitfield.baseindex)))
8462 goto bad_address;
8463 }
8464 else
3e73aa7c 8465 {
be05d201 8466 /* 16-bit checks. */
3e73aa7c 8467 if ((i.base_reg
40fb9820
L		 8468 && (!i.base_reg->reg_type.bitfield.reg16
8469 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8470 || (i.index_reg
40fb9820
L		 8471 && (!i.index_reg->reg_type.bitfield.reg16
8472 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8473 || !(i.base_reg
8474 && i.base_reg->reg_num < 6
8475 && i.index_reg->reg_num >= 6
8476 && i.log2_scale_factor == 0))))
be05d201 8477 goto bad_address;
3e73aa7c
JH		 8478 }
8479 }
be05d201 8480 return 1;
24eab124 8481}
252b5132 8482
43234a1e
L		 8483/* Handle vector immediates. */
8484
8485static int
8486RC_SAE_immediate (const char *imm_start)
8487{
8488 unsigned int match_found, j;
8489 const char *pstr = imm_start;
8490 expressionS *exp;
8491
8492 if (*pstr != '{')
8493 return 0;
8494
8495 pstr++;
8496 match_found = 0;
8497 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8498 {
8499 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8500 {
8501 if (!i.rounding)
8502 {
8503 rc_op.type = RC_NamesTable[j].type;
8504 rc_op.operand = this_operand;
8505 i.rounding = &rc_op;
8506 }
8507 else
8508 {
8509 as_bad (_("duplicated `%s'"), imm_start);
8510 return 0;
8511 }
8512 pstr += RC_NamesTable[j].len;
8513 match_found = 1;
8514 break;
8515 }
8516 }
8517 if (!match_found)
8518 return 0;
8519
8520 if (*pstr++ != '}')
8521 {
8522 as_bad (_("Missing '}': '%s'"), imm_start);
8523 return 0;
8524 }
8525 /* RC/SAE immediate string should contain nothing more. */;
8526 if (*pstr != 0)
8527 {
8528 as_bad (_("Junk after '}': '%s'"), imm_start);
8529 return 0;
8530 }
8531
8532 exp = &im_expressions[i.imm_operands++];
8533 i.op[this_operand].imms = exp;
8534
8535 exp->X_op = O_constant;
8536 exp->X_add_number = 0;
8537 exp->X_add_symbol = (symbolS *) 0;
8538 exp->X_op_symbol = (symbolS *) 0;
8539
8540 i.types[this_operand].bitfield.imm8 = 1;
8541 return 1;
8542}
8543
fc0763e6 8544/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8545 on error. */
252b5132 8546
252b5132 8547static int
a7619375 8548i386_att_operand (char *operand_string)
252b5132 8549{
af6bdddf
AM		 8550 const reg_entry *r;
8551 char *end_op;
24eab124 8552 char *op_string = operand_string;
252b5132 8553
24eab124 8554 if (is_space_char (*op_string))
252b5132
RH		 8555 ++op_string;
8556
24eab124 8557 /* We check for an absolute prefix (differentiating,
47926f60 8558 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8559 if (*op_string == ABSOLUTE_PREFIX)
8560 {
8561 ++op_string;
8562 if (is_space_char (*op_string))
8563 ++op_string;
40fb9820 8564 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8565 }
252b5132 8566
47926f60 8567 /* Check if operand is a register. */
4d1bb795 8568 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8569 {
40fb9820
L		 8570 i386_operand_type temp;
8571
24eab124
AM		 8572 /* Check for a segment override by searching for ':' after a
8573 segment register. */
8574 op_string = end_op;
8575 if (is_space_char (*op_string))
8576 ++op_string;
40fb9820
L		 8577 if (*op_string == ':'
8578 && (r->reg_type.bitfield.sreg2
8579 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8580 {
8581 switch (r->reg_num)
8582 {
8583 case 0:
8584 i.seg[i.mem_operands] = &es;
8585 break;
8586 case 1:
8587 i.seg[i.mem_operands] = &cs;
8588 break;
8589 case 2:
8590 i.seg[i.mem_operands] = &ss;
8591 break;
8592 case 3:
8593 i.seg[i.mem_operands] = &ds;
8594 break;
8595 case 4:
8596 i.seg[i.mem_operands] = &fs;
8597 break;
8598 case 5:
8599 i.seg[i.mem_operands] = &gs;
8600 break;
8601 }
252b5132 8602
24eab124 8603 /* Skip the ':' and whitespace. */
252b5132
RH		 8604 ++op_string;
8605 if (is_space_char (*op_string))
24eab124 8606 ++op_string;
252b5132 8607
24eab124
AM		 8608 if (!is_digit_char (*op_string)
8609 && !is_identifier_char (*op_string)
8610 && *op_string != '('
8611 && *op_string != ABSOLUTE_PREFIX)
8612 {
8613 as_bad (_("bad memory operand `%s'"), op_string);
8614 return 0;
8615 }
47926f60 8616 /* Handle case of %es:*foo. */
24eab124
AM		 8617 if (*op_string == ABSOLUTE_PREFIX)
8618 {
8619 ++op_string;
8620 if (is_space_char (*op_string))
8621 ++op_string;
40fb9820 8622 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8623 }
8624 goto do_memory_reference;
8625 }
43234a1e
L		 8626
8627 /* Handle vector operations. */
8628 if (*op_string == '{')
8629 {
8630 op_string = check_VecOperations (op_string, NULL);
8631 if (op_string == NULL)
8632 return 0;
8633 }
8634
24eab124
AM		 8635 if (*op_string)
8636 {
d0b47220 8637 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8638 return 0;
8639 }
40fb9820
L		 8640 temp = r->reg_type;
8641 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8642 i.types[this_operand] = operand_type_or (i.types[this_operand],
8643 temp);
7d5e4556 8644 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8645 i.op[this_operand].regs = r;
24eab124
AM		 8646 i.reg_operands++;
8647 }
af6bdddf
AM		 8648 else if (*op_string == REGISTER_PREFIX)
8649 {
8650 as_bad (_("bad register name `%s'"), op_string);
8651 return 0;
8652 }
24eab124 8653 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8654 {
24eab124 8655 ++op_string;
40fb9820 8656 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8657 {
d0b47220 8658 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8659 return 0;
8660 }
8661 if (!i386_immediate (op_string))
8662 return 0;
8663 }
43234a1e
L		 8664 else if (RC_SAE_immediate (operand_string))
8665 {
8666 /* If it is a RC or SAE immediate, do nothing. */
8667 ;
8668 }
24eab124
AM		 8669 else if (is_digit_char (*op_string)
8670 || is_identifier_char (*op_string)
d02603dc 8671 || *op_string == '"'
e5cb08ac 8672 || *op_string == '(')
24eab124 8673 {
47926f60 8674 /* This is a memory reference of some sort. */
af6bdddf 8675 char *base_string;
252b5132 8676
47926f60 8677 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8678 char *displacement_string_start;
8679 char *displacement_string_end;
43234a1e 8680 char *vop_start;
252b5132 8681
24eab124 8682 do_memory_reference:
24eab124 8683 if ((i.mem_operands == 1
40fb9820 8684 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8685 || i.mem_operands == 2)
8686 {
8687 as_bad (_("too many memory references for `%s'"),
8688 current_templates->start->name);
8689 return 0;
8690 }
252b5132 8691
24eab124
AM		 8692 /* Check for base index form. We detect the base index form by
8693 looking for an ')' at the end of the operand, searching
8694 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8695 after the '('. */
af6bdddf 8696 base_string = op_string + strlen (op_string);
c3332e24 8697
43234a1e
L		 8698 /* Handle vector operations. */
8699 vop_start = strchr (op_string, '{');
8700 if (vop_start && vop_start < base_string)
8701 {
8702 if (check_VecOperations (vop_start, base_string) == NULL)
8703 return 0;
8704 base_string = vop_start;
8705 }
8706
af6bdddf
AM		 8707 --base_string;
8708 if (is_space_char (*base_string))
8709 --base_string;
252b5132 8710
47926f60 8711 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8712 displacement_string_start = op_string;
8713 displacement_string_end = base_string + 1;
252b5132 8714
24eab124
AM		 8715 if (*base_string == ')')
8716 {
af6bdddf 8717 char *temp_string;
24eab124
AM		 8718 unsigned int parens_balanced = 1;
8719 /* We've already checked that the number of left & right ()'s are
47926f60 8720 equal, so this loop will not be infinite. */
24eab124
AM		 8721 do
8722 {
8723 base_string--;
8724 if (*base_string == ')')
8725 parens_balanced++;
8726 if (*base_string == '(')
8727 parens_balanced--;
8728 }
8729 while (parens_balanced);
c3332e24 8730
af6bdddf 8731 temp_string = base_string;
c3332e24 8732
24eab124 8733 /* Skip past '(' and whitespace. */
252b5132
RH		 8734 ++base_string;
8735 if (is_space_char (*base_string))
24eab124 8736 ++base_string;
252b5132 8737
af6bdddf 8738 if (*base_string == ','
4eed87de
AM		 8739 || ((i.base_reg = parse_register (base_string, &end_op))
8740 != NULL))
252b5132 8741 {
af6bdddf 8742 displacement_string_end = temp_string;
252b5132 8743
40fb9820 8744 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8745
af6bdddf 8746 if (i.base_reg)
24eab124 8747 {
24eab124
AM		 8748 base_string = end_op;
8749 if (is_space_char (*base_string))
8750 ++base_string;
af6bdddf
AM		 8751 }
8752
8753 /* There may be an index reg or scale factor here. */
8754 if (*base_string == ',')
8755 {
8756 ++base_string;
8757 if (is_space_char (*base_string))
8758 ++base_string;
8759
4eed87de
AM		 8760 if ((i.index_reg = parse_register (base_string, &end_op))
8761 != NULL)
24eab124 8762 {
af6bdddf 8763 base_string = end_op;
24eab124
AM		 8764 if (is_space_char (*base_string))
8765 ++base_string;
af6bdddf
AM		 8766 if (*base_string == ',')
8767 {
8768 ++base_string;
8769 if (is_space_char (*base_string))
8770 ++base_string;
8771 }
e5cb08ac 8772 else if (*base_string != ')')
af6bdddf 8773 {
4eed87de
AM		 8774 as_bad (_("expecting `,' or `)' "
8775 "after index register in `%s'"),
af6bdddf
AM		 8776 operand_string);
8777 return 0;
8778 }
24eab124 8779 }
af6bdddf 8780 else if (*base_string == REGISTER_PREFIX)
24eab124 8781 {
f76bf5e0
L		 8782 end_op = strchr (base_string, ',');
8783 if (end_op)
8784 *end_op = '\0';
af6bdddf 8785 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8786 return 0;
8787 }
252b5132 8788
47926f60 8789 /* Check for scale factor. */
551c1ca1 8790 if (*base_string != ')')
af6bdddf 8791 {
551c1ca1
AM		 8792 char *end_scale = i386_scale (base_string);
8793
8794 if (!end_scale)
af6bdddf 8795 return 0;
24eab124 8796
551c1ca1 8797 base_string = end_scale;
af6bdddf
AM		 8798 if (is_space_char (*base_string))
8799 ++base_string;
8800 if (*base_string != ')')
8801 {
4eed87de
AM		 8802 as_bad (_("expecting `)' "
8803 "after scale factor in `%s'"),
af6bdddf
AM		 8804 operand_string);
8805 return 0;
8806 }
8807 }
8808 else if (!i.index_reg)
24eab124 8809 {
4eed87de
AM		 8810 as_bad (_("expecting index register or scale factor "
8811 "after `,'; got '%c'"),
af6bdddf 8812 *base_string);
24eab124
AM		 8813 return 0;
8814 }
8815 }
af6bdddf 8816 else if (*base_string != ')')
24eab124 8817 {
4eed87de
AM		 8818 as_bad (_("expecting `,' or `)' "
8819 "after base register in `%s'"),
af6bdddf 8820 operand_string);
24eab124
AM		 8821 return 0;
8822 }
c3332e24 8823 }
af6bdddf 8824 else if (*base_string == REGISTER_PREFIX)
c3332e24 8825 {
f76bf5e0
L		 8826 end_op = strchr (base_string, ',');
8827 if (end_op)
8828 *end_op = '\0';
af6bdddf 8829 as_bad (_("bad register name `%s'"), base_string);
24eab124 8830 return 0;
c3332e24 8831 }
24eab124
AM		 8832 }
8833
8834 /* If there's an expression beginning the operand, parse it,
8835 assuming displacement_string_start and
8836 displacement_string_end are meaningful. */
8837 if (displacement_string_start != displacement_string_end)
8838 {
8839 if (!i386_displacement (displacement_string_start,
8840 displacement_string_end))
8841 return 0;
8842 }
8843
8844 /* Special case for (%dx) while doing input/output op. */
8845 if (i.base_reg
0dfbf9d7
L		 8846 && operand_type_equal (&i.base_reg->reg_type,
8847 &reg16_inoutportreg)
24eab124
AM		 8848 && i.index_reg == 0
8849 && i.log2_scale_factor == 0
8850 && i.seg[i.mem_operands] == 0
40fb9820 8851 && !operand_type_check (i.types[this_operand], disp))
24eab124 8852 {
65da13b5 8853 i.types[this_operand] = inoutportreg;
24eab124
AM		 8854 return 1;
8855 }
8856
eecb386c
AM		 8857 if (i386_index_check (operand_string) == 0)
8858 return 0;
5c07affc 8859 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8860 i.mem_operands++;
8861 }
8862 else
ce8a8b2f
AM		 8863 {
8864 /* It's not a memory operand; argh! */
24eab124
AM		 8865 as_bad (_("invalid char %s beginning operand %d `%s'"),
8866 output_invalid (*op_string),
8867 this_operand + 1,
8868 op_string);
8869 return 0;
8870 }
47926f60 8871 return 1; /* Normal return. */
252b5132
RH		 8872}
8873\f
fa94de6b
RM		 8874/* Calculate the maximum variable size (i.e., excluding fr_fix)
8875 that an rs_machine_dependent frag may reach. */
8876
8877unsigned int
8878i386_frag_max_var (fragS *frag)
8879{
8880 /* The only relaxable frags are for jumps.
8881 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8882 gas_assert (frag->fr_type == rs_machine_dependent);
8883 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8884}
8885
b084df0b
L		 8886#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8887static int
8dcea932 8888elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8889{
8890 /* STT_GNU_IFUNC symbol must go through PLT. */
8891 if ((symbol_get_bfdsym (fr_symbol)->flags
8892 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8893 return 0;
8894
8895 if (!S_IS_EXTERNAL (fr_symbol))
8896 /* Symbol may be weak or local. */
8897 return !S_IS_WEAK (fr_symbol);
8898
8dcea932
L		 8899 /* Global symbols with non-default visibility can't be preempted. */
8900 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8901 return 1;
8902
8903 if (fr_var != NO_RELOC)
8904 switch ((enum bfd_reloc_code_real) fr_var)
8905 {
8906 case BFD_RELOC_386_PLT32:
8907 case BFD_RELOC_X86_64_PLT32:
8908 /* Symbol with PLT relocatin may be preempted. */
8909 return 0;
8910 default:
8911 abort ();
8912 }
8913
b084df0b
L		 8914 /* Global symbols with default visibility in a shared library may be
8915 preempted by another definition. */
8dcea932 8916 return !shared;
b084df0b
L		 8917}
8918#endif
8919
ee7fcc42
AM		 8920/* md_estimate_size_before_relax()
8921
8922 Called just before relax() for rs_machine_dependent frags. The x86
8923 assembler uses these frags to handle variable size jump
8924 instructions.
8925
8926 Any symbol that is now undefined will not become defined.
8927 Return the correct fr_subtype in the frag.
8928 Return the initial "guess for variable size of frag" to caller.
8929 The guess is actually the growth beyond the fixed part. Whatever
8930 we do to grow the fixed or variable part contributes to our
8931 returned value. */
8932
252b5132 8933int
7016a5d5 8934md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8935{
252b5132 8936 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8937 check for un-relaxable symbols. On an ELF system, we can't relax
8938 an externally visible symbol, because it may be overridden by a
8939 shared library. */
8940 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8941#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8942 || (IS_ELF
8dcea932
L		 8943 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
8944 fragP->fr_var))
fbeb56a4
DK		 8945#endif
8946#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8947 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8948 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8949#endif
8950 )
252b5132 8951 {
b98ef147
AM		 8952 /* Symbol is undefined in this segment, or we need to keep a
8953 reloc so that weak symbols can be overridden. */
8954 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8955 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8956 unsigned char *opcode;
8957 int old_fr_fix;
f6af82bd 8958
ee7fcc42 8959 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8960 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8961 else if (size == 2)
f6af82bd
AM		 8962 reloc_type = BFD_RELOC_16_PCREL;
8963 else
8964 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8965
ee7fcc42
AM		 8966 old_fr_fix = fragP->fr_fix;
8967 opcode = (unsigned char *) fragP->fr_opcode;
8968
fddf5b5b 8969 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8970 {
fddf5b5b
AM		 8971 case UNCOND_JUMP:
8972 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8973 opcode[0] = 0xe9;
252b5132 8974 fragP->fr_fix += size;
062cd5e7
AS		 8975 fix_new (fragP, old_fr_fix, size,
8976 fragP->fr_symbol,
8977 fragP->fr_offset, 1,
8978 reloc_type);
252b5132
RH		 8979 break;
8980
fddf5b5b 8981 case COND_JUMP86:
412167cb
AM		 8982 if (size == 2
8983 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8984 {
8985 /* Negate the condition, and branch past an
8986 unconditional jump. */
8987 opcode[0] ^= 1;
8988 opcode[1] = 3;
8989 /* Insert an unconditional jump. */
8990 opcode[2] = 0xe9;
8991 /* We added two extra opcode bytes, and have a two byte
8992 offset. */
8993 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8994 fix_new (fragP, old_fr_fix + 2, 2,
8995 fragP->fr_symbol,
8996 fragP->fr_offset, 1,
8997 reloc_type);
fddf5b5b
AM		 8998 break;
8999 }
9000 /* Fall through. */
9001
9002 case COND_JUMP:
412167cb
AM		 9003 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9004 {
3e02c1cc
AM		 9005 fixS *fixP;
9006
412167cb 9007 fragP->fr_fix += 1;
3e02c1cc
AM		 9008 fixP = fix_new (fragP, old_fr_fix, 1,
9009 fragP->fr_symbol,
9010 fragP->fr_offset, 1,
9011 BFD_RELOC_8_PCREL);
9012 fixP->fx_signed = 1;
412167cb
AM		 9013 break;
9014 }
93c2a809 9015
24eab124 9016 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9017 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9018 opcode[1] = opcode[0] + 0x10;
f6af82bd 9019 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9020 /* We've added an opcode byte. */
9021 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9022 fix_new (fragP, old_fr_fix + 1, size,
9023 fragP->fr_symbol,
9024 fragP->fr_offset, 1,
9025 reloc_type);
252b5132 9026 break;
fddf5b5b
AM		 9027
9028 default:
9029 BAD_CASE (fragP->fr_subtype);
9030 break;
252b5132
RH		 9031 }
9032 frag_wane (fragP);
ee7fcc42 9033 return fragP->fr_fix - old_fr_fix;
252b5132 9034 }
93c2a809 9035
93c2a809
AM		 9036 /* Guess size depending on current relax state. Initially the relax
9037 state will correspond to a short jump and we return 1, because
9038 the variable part of the frag (the branch offset) is one byte
9039 long. However, we can relax a section more than once and in that
9040 case we must either set fr_subtype back to the unrelaxed state,
9041 or return the value for the appropriate branch. */
9042 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9043}
9044
47926f60
KH		 9045/* Called after relax() is finished.
9046
9047 In: Address of frag.
9048 fr_type == rs_machine_dependent.
9049 fr_subtype is what the address relaxed to.
9050
9051 Out: Any fixSs and constants are set up.
9052 Caller will turn frag into a ".space 0". */
9053
252b5132 9054void
7016a5d5
TG		 9055md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9056 fragS *fragP)
252b5132 9057{
29b0f896 9058 unsigned char *opcode;
252b5132 9059 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9060 offsetT target_address;
9061 offsetT opcode_address;
252b5132 9062 unsigned int extension = 0;
847f7ad4 9063 offsetT displacement_from_opcode_start;
252b5132
RH		 9064
9065 opcode = (unsigned char *) fragP->fr_opcode;
9066
47926f60 9067 /* Address we want to reach in file space. */
252b5132 9068 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9069
47926f60 9070 /* Address opcode resides at in file space. */
252b5132
RH		 9071 opcode_address = fragP->fr_address + fragP->fr_fix;
9072
47926f60 9073 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9074 displacement_from_opcode_start = target_address - opcode_address;
9075
fddf5b5b 9076 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9077 {
47926f60
KH		 9078 /* Don't have to change opcode. */
9079 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9080 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9081 }
9082 else
9083 {
9084 if (no_cond_jump_promotion
9085 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9086 as_warn_where (fragP->fr_file, fragP->fr_line,
9087 _("long jump required"));
252b5132 9088
fddf5b5b
AM		 9089 switch (fragP->fr_subtype)
9090 {
9091 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9092 extension = 4; /* 1 opcode + 4 displacement */
9093 opcode[0] = 0xe9;
9094 where_to_put_displacement = &opcode[1];
9095 break;
252b5132 9096
fddf5b5b
AM		 9097 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9098 extension = 2; /* 1 opcode + 2 displacement */
9099 opcode[0] = 0xe9;
9100 where_to_put_displacement = &opcode[1];
9101 break;
252b5132 9102
fddf5b5b
AM		 9103 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9104 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9105 extension = 5; /* 2 opcode + 4 displacement */
9106 opcode[1] = opcode[0] + 0x10;
9107 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9108 where_to_put_displacement = &opcode[2];
9109 break;
252b5132 9110
fddf5b5b
AM		 9111 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9112 extension = 3; /* 2 opcode + 2 displacement */
9113 opcode[1] = opcode[0] + 0x10;
9114 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9115 where_to_put_displacement = &opcode[2];
9116 break;
252b5132 9117
fddf5b5b
AM		 9118 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9119 extension = 4;
9120 opcode[0] ^= 1;
9121 opcode[1] = 3;
9122 opcode[2] = 0xe9;
9123 where_to_put_displacement = &opcode[3];
9124 break;
9125
9126 default:
9127 BAD_CASE (fragP->fr_subtype);
9128 break;
9129 }
252b5132 9130 }
fddf5b5b 9131
7b81dfbb
AJ		 9132 /* If size if less then four we are sure that the operand fits,
9133 but if it's 4, then it could be that the displacement is larger
9134 then -/+ 2GB. */
9135 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9136 && object_64bit
9137 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9138 + ((addressT) 1 << 31))
9139 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9140 {
9141 as_bad_where (fragP->fr_file, fragP->fr_line,
9142 _("jump target out of range"));
9143 /* Make us emit 0. */
9144 displacement_from_opcode_start = extension;
9145 }
47926f60 9146 /* Now put displacement after opcode. */
252b5132
RH		 9147 md_number_to_chars ((char *) where_to_put_displacement,
9148 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9149 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9150 fragP->fr_fix += extension;
9151}
9152\f
7016a5d5 9153/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9154 by our caller that we have all the info we need to fix it up.
9155
7016a5d5
TG		 9156 Parameter valP is the pointer to the value of the bits.
9157
252b5132
RH		 9158 On the 386, immediates, displacements, and data pointers are all in
9159 the same (little-endian) format, so we don't need to care about which
9160 we are handling. */
9161
94f592af 9162void
7016a5d5 9163md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9164{
94f592af 9165 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9166 valueT value = *valP;
252b5132 9167
f86103b7 9168#if !defined (TE_Mach)
93382f6d
AM		 9169 if (fixP->fx_pcrel)
9170 {
9171 switch (fixP->fx_r_type)
9172 {
5865bb77
ILT		 9173 default:
9174 break;
9175
d6ab8113
JB		 9176 case BFD_RELOC_64:
9177 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9178 break;
93382f6d 9179 case BFD_RELOC_32:
ae8887b5 9180 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9181 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9182 break;
9183 case BFD_RELOC_16:
9184 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9185 break;
9186 case BFD_RELOC_8:
9187 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9188 break;
9189 }
9190 }
252b5132 9191
a161fe53 9192 if (fixP->fx_addsy != NULL
31312f95 9193 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9194 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9195 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9196 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9197 && !use_rela_relocations)
252b5132 9198 {
31312f95
AM		 9199 /* This is a hack. There should be a better way to handle this.
9200 This covers for the fact that bfd_install_relocation will
9201 subtract the current location (for partial_inplace, PC relative
9202 relocations); see more below. */
252b5132 9203#ifndef OBJ_AOUT
718ddfc0 9204 if (IS_ELF
252b5132
RH		 9205#ifdef TE_PE
9206 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9207#endif
9208 )
9209 value += fixP->fx_where + fixP->fx_frag->fr_address;
9210#endif
9211#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9212 if (IS_ELF)
252b5132 9213 {
6539b54b 9214 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9215
6539b54b 9216 if ((sym_seg == seg
2f66722d 9217 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9218 && sym_seg != absolute_section))
af65af87 9219 && !generic_force_reloc (fixP))
2f66722d
AM		 9220 {
9221 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9222 bfd_install_relocation subtracts them out again. I think
9223 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9224 it. FIXME. */
9225 value += fixP->fx_where + fixP->fx_frag->fr_address;
9226 }
252b5132
RH		 9227 }
9228#endif
9229#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9230 /* For some reason, the PE format does not store a
9231 section address offset for a PC relative symbol. */
9232 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9233 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9234 value += md_pcrel_from (fixP);
9235#endif
9236 }
fbeb56a4 9237#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9238 if (fixP->fx_addsy != NULL
9239 && S_IS_WEAK (fixP->fx_addsy)
9240 /* PR 16858: Do not modify weak function references. */
9241 && ! fixP->fx_pcrel)
fbeb56a4 9242 {
296a8689
NC		 9243#if !defined (TE_PEP)
9244 /* For x86 PE weak function symbols are neither PC-relative
9245 nor do they set S_IS_FUNCTION. So the only reliable way
9246 to detect them is to check the flags of their containing
9247 section. */
9248 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9249 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9250 ;
9251 else
9252#endif
fbeb56a4
DK		 9253 value -= S_GET_VALUE (fixP->fx_addsy);
9254 }
9255#endif
252b5132
RH		 9256
9257 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9258 and we must not disappoint it. */
252b5132 9259#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9260 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9261 switch (fixP->fx_r_type)
9262 {
9263 case BFD_RELOC_386_PLT32:
3e73aa7c 9264 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9265 /* Make the jump instruction point to the address of the operand. At
9266 runtime we merely add the offset to the actual PLT entry. */
9267 value = -4;
9268 break;
31312f95 9269
13ae64f3
JJ		 9270 case BFD_RELOC_386_TLS_GD:
9271 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9272 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9273 case BFD_RELOC_386_TLS_IE:
9274 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9275 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9276 case BFD_RELOC_X86_64_TLSGD:
9277 case BFD_RELOC_X86_64_TLSLD:
9278 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9279 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9280 value = 0; /* Fully resolved at runtime. No addend. */
9281 /* Fallthrough */
9282 case BFD_RELOC_386_TLS_LE:
9283 case BFD_RELOC_386_TLS_LDO_32:
9284 case BFD_RELOC_386_TLS_LE_32:
9285 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9286 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9287 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9288 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9289 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9290 break;
9291
67a4f2b7
AO		 9292 case BFD_RELOC_386_TLS_DESC_CALL:
9293 case BFD_RELOC_X86_64_TLSDESC_CALL:
9294 value = 0; /* Fully resolved at runtime. No addend. */
9295 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9296 fixP->fx_done = 0;
9297 return;
9298
00f7efb6
JJ		 9299 case BFD_RELOC_386_GOT32:
9300 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9301 value = 0; /* Fully resolved at runtime. No addend. */
9302 break;
47926f60
KH		 9303
9304 case BFD_RELOC_VTABLE_INHERIT:
9305 case BFD_RELOC_VTABLE_ENTRY:
9306 fixP->fx_done = 0;
94f592af 9307 return;
47926f60
KH		 9308
9309 default:
9310 break;
9311 }
9312#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9313 *valP = value;
f86103b7 9314#endif /* !defined (TE_Mach) */
3e73aa7c 9315
3e73aa7c 9316 /* Are we finished with this relocation now? */
c6682705 9317 if (fixP->fx_addsy == NULL)
3e73aa7c 9318 fixP->fx_done = 1;
fbeb56a4
DK		 9319#if defined (OBJ_COFF) && defined (TE_PE)
9320 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9321 {
9322 fixP->fx_done = 0;
9323 /* Remember value for tc_gen_reloc. */
9324 fixP->fx_addnumber = value;
9325 /* Clear out the frag for now. */
9326 value = 0;
9327 }
9328#endif
3e73aa7c
JH		 9329 else if (use_rela_relocations)
9330 {
9331 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9332 /* Remember value for tc_gen_reloc. */
9333 fixP->fx_addnumber = value;
3e73aa7c
JH		 9334 value = 0;
9335 }
f86103b7 9336
94f592af 9337 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9338}
252b5132 9339\f
252b5132 9340char *
499ac353 9341md_atof (int type, char *litP, int *sizeP)
252b5132 9342{
499ac353
NC		 9343 /* This outputs the LITTLENUMs in REVERSE order;
9344 in accord with the bigendian 386. */
9345 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9346}
9347\f
2d545b82 9348static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9349
252b5132 9350static char *
e3bb37b5 9351output_invalid (int c)
252b5132 9352{
3882b010 9353 if (ISPRINT (c))
f9f21a03
L		 9354 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9355 "'%c'", c);
252b5132 9356 else
f9f21a03 9357 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9358 "(0x%x)", (unsigned char) c);
252b5132
RH		 9359 return output_invalid_buf;
9360}
9361
af6bdddf 9362/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9363
9364static const reg_entry *
4d1bb795 9365parse_real_register (char *reg_string, char **end_op)
252b5132 9366{
af6bdddf
AM		 9367 char *s = reg_string;
9368 char *p;
252b5132
RH		 9369 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9370 const reg_entry *r;
9371
9372 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9373 if (*s == REGISTER_PREFIX)
9374 ++s;
9375
9376 if (is_space_char (*s))
9377 ++s;
9378
9379 p = reg_name_given;
af6bdddf 9380 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9381 {
9382 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9383 return (const reg_entry *) NULL;
9384 s++;
252b5132
RH		 9385 }
9386
6588847e
DN		 9387 /* For naked regs, make sure that we are not dealing with an identifier.
9388 This prevents confusing an identifier like `eax_var' with register
9389 `eax'. */
9390 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9391 return (const reg_entry *) NULL;
9392
af6bdddf 9393 *end_op = s;
252b5132
RH		 9394
9395 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9396
5f47d35b 9397 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9398 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9399 {
5f47d35b
AM		 9400 if (is_space_char (*s))
9401 ++s;
9402 if (*s == '(')
9403 {
af6bdddf 9404 ++s;
5f47d35b
AM		 9405 if (is_space_char (*s))
9406 ++s;
9407 if (*s >= '0' && *s <= '7')
9408 {
db557034 9409 int fpr = *s - '0';
af6bdddf 9410 ++s;
5f47d35b
AM		 9411 if (is_space_char (*s))
9412 ++s;
9413 if (*s == ')')
9414 {
9415 *end_op = s + 1;
1e9cc1c2 9416 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9417 know (r);
9418 return r + fpr;
5f47d35b 9419 }
5f47d35b 9420 }
47926f60 9421 /* We have "%st(" then garbage. */
5f47d35b
AM		 9422 return (const reg_entry *) NULL;
9423 }
9424 }
9425
a60de03c
JB		 9426 if (r == NULL || allow_pseudo_reg)
9427 return r;
9428
0dfbf9d7 9429 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9430 return (const reg_entry *) NULL;
9431
192dc9c6
JB		 9432 if ((r->reg_type.bitfield.reg32
9433 || r->reg_type.bitfield.sreg3
9434 || r->reg_type.bitfield.control
9435 || r->reg_type.bitfield.debug
9436 || r->reg_type.bitfield.test)
9437 && !cpu_arch_flags.bitfield.cpui386)
9438 return (const reg_entry *) NULL;
9439
309d3373
JB		 9440 if (r->reg_type.bitfield.floatreg
9441 && !cpu_arch_flags.bitfield.cpu8087
9442 && !cpu_arch_flags.bitfield.cpu287
9443 && !cpu_arch_flags.bitfield.cpu387)
9444 return (const reg_entry *) NULL;
9445
192dc9c6
JB		 9446 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9447 return (const reg_entry *) NULL;
9448
9449 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9450 return (const reg_entry *) NULL;
9451
40f12533
L		 9452 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9453 return (const reg_entry *) NULL;
9454
43234a1e
L		 9455 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9456 && !cpu_arch_flags.bitfield.cpuavx512f)
9457 return (const reg_entry *) NULL;
9458
db51cc60 9459 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9460 if (!allow_index_reg
db51cc60
L		 9461 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9462 return (const reg_entry *) NULL;
9463
43234a1e
L		 9464 /* Upper 16 vector register is only available with VREX in 64bit
9465 mode. */
9466 if ((r->reg_flags & RegVRex))
9467 {
9468 if (!cpu_arch_flags.bitfield.cpuvrex
9469 || flag_code != CODE_64BIT)
9470 return (const reg_entry *) NULL;
9471
9472 i.need_vrex = 1;
9473 }
9474
a60de03c
JB		 9475 if (((r->reg_flags & (RegRex64 | RegRex))
9476 || r->reg_type.bitfield.reg64)
40fb9820 9477 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9478 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9479 && flag_code != CODE_64BIT)
20f0a1fc 9480 return (const reg_entry *) NULL;
1ae00879 9481
b7240065
JB		 9482 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9483 return (const reg_entry *) NULL;
9484
252b5132
RH		 9485 return r;
9486}
4d1bb795
JB		 9487
9488/* REG_STRING starts *before* REGISTER_PREFIX. */
9489
9490static const reg_entry *
9491parse_register (char *reg_string, char **end_op)
9492{
9493 const reg_entry *r;
9494
9495 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9496 r = parse_real_register (reg_string, end_op);
9497 else
9498 r = NULL;
9499 if (!r)
9500 {
9501 char *save = input_line_pointer;
9502 char c;
9503 symbolS *symbolP;
9504
9505 input_line_pointer = reg_string;
d02603dc 9506 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9507 symbolP = symbol_find (reg_string);
9508 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9509 {
9510 const expressionS *e = symbol_get_value_expression (symbolP);
9511
0398aac5 9512 know (e->X_op == O_register);
4eed87de 9513 know (e->X_add_number >= 0
c3fe08fa 9514 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9515 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9516 if ((r->reg_flags & RegVRex))
9517 i.need_vrex = 1;
4d1bb795
JB		 9518 *end_op = input_line_pointer;
9519 }
9520 *input_line_pointer = c;
9521 input_line_pointer = save;
9522 }
9523 return r;
9524}
9525
9526int
9527i386_parse_name (char *name, expressionS *e, char *nextcharP)
9528{
9529 const reg_entry *r;
9530 char *end = input_line_pointer;
9531
9532 *end = *nextcharP;
9533 r = parse_register (name, &input_line_pointer);
9534 if (r && end <= input_line_pointer)
9535 {
9536 *nextcharP = *input_line_pointer;
9537 *input_line_pointer = 0;
9538 e->X_op = O_register;
9539 e->X_add_number = r - i386_regtab;
9540 return 1;
9541 }
9542 input_line_pointer = end;
9543 *end = 0;
ee86248c 9544 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9545}
9546
9547void
9548md_operand (expressionS *e)
9549{
ee86248c
JB		 9550 char *end;
9551 const reg_entry *r;
4d1bb795 9552
ee86248c
JB		 9553 switch (*input_line_pointer)
9554 {
9555 case REGISTER_PREFIX:
9556 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9557 if (r)
9558 {
9559 e->X_op = O_register;
9560 e->X_add_number = r - i386_regtab;
9561 input_line_pointer = end;
9562 }
ee86248c
JB		 9563 break;
9564
9565 case '[':
9c2799c2 9566 gas_assert (intel_syntax);
ee86248c
JB		 9567 end = input_line_pointer++;
9568 expression (e);
9569 if (*input_line_pointer == ']')
9570 {
9571 ++input_line_pointer;
9572 e->X_op_symbol = make_expr_symbol (e);
9573 e->X_add_symbol = NULL;
9574 e->X_add_number = 0;
9575 e->X_op = O_index;
9576 }
9577 else
9578 {
9579 e->X_op = O_absent;
9580 input_line_pointer = end;
9581 }
9582 break;
4d1bb795
JB		 9583 }
9584}
9585
252b5132 9586\f
4cc782b5 9587#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9588const char *md_shortopts = "kVQ:sqn";
252b5132 9589#else
12b55ccc 9590const char *md_shortopts = "qn";
252b5132 9591#endif
6e0b89ee 9592
3e73aa7c 9593#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9594#define OPTION_64 (OPTION_MD_BASE + 1)
9595#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9596#define OPTION_MARCH (OPTION_MD_BASE + 3)
9597#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9598#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9599#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9600#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9601#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9602#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9603#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9604#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9605#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9606#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9607#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9608#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9609#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9610#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9611#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9612#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9613#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9614#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9615#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9616#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
b3b91714 9617
99ad8390
NC		 9618struct option md_longopts[] =
9619{
3e73aa7c 9620 {"32", no_argument, NULL, OPTION_32},
321098a5 9621#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9622 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9623 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9624#endif
9625#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9626 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9627 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9628#endif
b3b91714 9629 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9630 {"march", required_argument, NULL, OPTION_MARCH},
9631 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9632 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9633 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9634 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9635 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9636 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9637 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9638 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9639 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9640 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9641 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9642 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9643 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9644# if defined (TE_PE) || defined (TE_PEP)
9645 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9646#endif
a5094208 9647 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9648 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9649 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9650 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9651 {NULL, no_argument, NULL, 0}
9652};
9653size_t md_longopts_size = sizeof (md_longopts);
9654
9655int
9103f4f4 9656md_parse_option (int c, char *arg)
252b5132 9657{
91d6fa6a 9658 unsigned int j;
6305a203 9659 char *arch, *next;
9103f4f4 9660
252b5132
RH		 9661 switch (c)
9662 {
12b55ccc
L		 9663 case 'n':
9664 optimize_align_code = 0;
9665 break;
9666
a38cf1db
AM		 9667 case 'q':
9668 quiet_warnings = 1;
252b5132
RH		 9669 break;
9670
9671#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9672 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9673 should be emitted or not. FIXME: Not implemented. */
9674 case 'Q':
252b5132
RH		 9675 break;
9676
9677 /* -V: SVR4 argument to print version ID. */
9678 case 'V':
9679 print_version_id ();
9680 break;
9681
a38cf1db
AM		 9682 /* -k: Ignore for FreeBSD compatibility. */
9683 case 'k':
252b5132 9684 break;
4cc782b5
ILT		 9685
9686 case 's':
9687 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9688 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9689 break;
8dcea932
L		 9690
9691 case OPTION_MSHARED:
9692 shared = 1;
9693 break;
99ad8390 9694#endif
321098a5 9695#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9696 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9697 case OPTION_64:
9698 {
9699 const char **list, **l;
9700
3e73aa7c
JH		 9701 list = bfd_target_list ();
9702 for (l = list; *l != NULL; l++)
8620418b 9703 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9704 || strcmp (*l, "coff-x86-64") == 0
9705 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9706 || strcmp (*l, "pei-x86-64") == 0
9707 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9708 {
9709 default_arch = "x86_64";
9710 break;
9711 }
3e73aa7c 9712 if (*l == NULL)
2b5d6a91 9713 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9714 free (list);
9715 }
9716 break;
9717#endif
252b5132 9718
351f65ca 9719#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9720 case OPTION_X32:
351f65ca
L		 9721 if (IS_ELF)
9722 {
9723 const char **list, **l;
9724
9725 list = bfd_target_list ();
9726 for (l = list; *l != NULL; l++)
9727 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9728 {
9729 default_arch = "x86_64:32";
9730 break;
9731 }
9732 if (*l == NULL)
2b5d6a91 9733 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9734 free (list);
9735 }
9736 else
9737 as_fatal (_("32bit x86_64 is only supported for ELF"));
9738 break;
9739#endif
9740
6e0b89ee
AM		 9741 case OPTION_32:
9742 default_arch = "i386";
9743 break;
9744
b3b91714
AM		 9745 case OPTION_DIVIDE:
9746#ifdef SVR4_COMMENT_CHARS
9747 {
9748 char *n, *t;
9749 const char *s;
9750
9751 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9752 t = n;
9753 for (s = i386_comment_chars; *s != '\0'; s++)
9754 if (*s != '/')
9755 *t++ = *s;
9756 *t = '\0';
9757 i386_comment_chars = n;
9758 }
9759#endif
9760 break;
9761
9103f4f4 9762 case OPTION_MARCH:
6305a203
L		 9763 arch = xstrdup (arg);
9764 do
9103f4f4 9765 {
6305a203 9766 if (*arch == '.')
2b5d6a91 9767 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9768 next = strchr (arch, '+');
9769 if (next)
9770 *next++ = '\0';
91d6fa6a 9771 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9772 {
91d6fa6a 9773 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9774 {
6305a203 9775 /* Processor. */
1ded5609
JB		 9776 if (! cpu_arch[j].flags.bitfield.cpui386)
9777 continue;
9778
91d6fa6a 9779 cpu_arch_name = cpu_arch[j].name;
6305a203 9780 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9781 cpu_arch_flags = cpu_arch[j].flags;
9782 cpu_arch_isa = cpu_arch[j].type;
9783 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9784 if (!cpu_arch_tune_set)
9785 {
9786 cpu_arch_tune = cpu_arch_isa;
9787 cpu_arch_tune_flags = cpu_arch_isa_flags;
9788 }
9789 break;
9790 }
91d6fa6a
NC		 9791 else if (*cpu_arch [j].name == '.'
9792 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9793 {
9794 /* ISA entension. */
9795 i386_cpu_flags flags;
309d3373 9796
49021df2 9797 if (!cpu_arch[j].negated)
309d3373 9798 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9799 cpu_arch[j].flags);
309d3373
JB		 9800 else
9801 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9802 cpu_arch[j].flags);
81486035
L		 9803
9804 if (!valid_iamcu_cpu_flags (&flags))
9805 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9806 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9807 {
9808 if (cpu_sub_arch_name)
9809 {
9810 char *name = cpu_sub_arch_name;
9811 cpu_sub_arch_name = concat (name,
91d6fa6a 9812 cpu_arch[j].name,
1bf57e9f 9813 (const char *) NULL);
6305a203
L		 9814 free (name);
9815 }
9816 else
91d6fa6a 9817 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9818 cpu_arch_flags = flags;
a586129e 9819 cpu_arch_isa_flags = flags;
6305a203
L		 9820 }
9821 break;
ccc9c027 9822 }
9103f4f4 9823 }
6305a203 9824
91d6fa6a 9825 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9826 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9827
9828 arch = next;
9103f4f4 9829 }
6305a203 9830 while (next != NULL );
9103f4f4
L		 9831 break;
9832
9833 case OPTION_MTUNE:
9834 if (*arg == '.')
2b5d6a91 9835 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9836 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9837 {
91d6fa6a 9838 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9839 {
ccc9c027 9840 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9841 cpu_arch_tune = cpu_arch [j].type;
9842 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9843 break;
9844 }
9845 }
91d6fa6a 9846 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9847 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9848 break;
9849
1efbbeb4
L		 9850 case OPTION_MMNEMONIC:
9851 if (strcasecmp (arg, "att") == 0)
9852 intel_mnemonic = 0;
9853 else if (strcasecmp (arg, "intel") == 0)
9854 intel_mnemonic = 1;
9855 else
2b5d6a91 9856 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9857 break;
9858
9859 case OPTION_MSYNTAX:
9860 if (strcasecmp (arg, "att") == 0)
9861 intel_syntax = 0;
9862 else if (strcasecmp (arg, "intel") == 0)
9863 intel_syntax = 1;
9864 else
2b5d6a91 9865 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9866 break;
9867
9868 case OPTION_MINDEX_REG:
9869 allow_index_reg = 1;
9870 break;
9871
9872 case OPTION_MNAKED_REG:
9873 allow_naked_reg = 1;
9874 break;
9875
9876 case OPTION_MOLD_GCC:
9877 old_gcc = 1;
1efbbeb4
L		 9878 break;
9879
c0f3af97
L		 9880 case OPTION_MSSE2AVX:
9881 sse2avx = 1;
9882 break;
9883
daf50ae7
L		 9884 case OPTION_MSSE_CHECK:
9885 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9886 sse_check = check_error;
daf50ae7 9887 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9888 sse_check = check_warning;
daf50ae7 9889 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9890 sse_check = check_none;
daf50ae7 9891 else
2b5d6a91 9892 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9893 break;
9894
7bab8ab5
JB		 9895 case OPTION_MOPERAND_CHECK:
9896 if (strcasecmp (arg, "error") == 0)
9897 operand_check = check_error;
9898 else if (strcasecmp (arg, "warning") == 0)
9899 operand_check = check_warning;
9900 else if (strcasecmp (arg, "none") == 0)
9901 operand_check = check_none;
9902 else
9903 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9904 break;
9905
539f890d
L		 9906 case OPTION_MAVXSCALAR:
9907 if (strcasecmp (arg, "128") == 0)
9908 avxscalar = vex128;
9909 else if (strcasecmp (arg, "256") == 0)
9910 avxscalar = vex256;
9911 else
2b5d6a91 9912 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9913 break;
9914
7e8b059b
L		 9915 case OPTION_MADD_BND_PREFIX:
9916 add_bnd_prefix = 1;
9917 break;
9918
43234a1e
L		 9919 case OPTION_MEVEXLIG:
9920 if (strcmp (arg, "128") == 0)
9921 evexlig = evexl128;
9922 else if (strcmp (arg, "256") == 0)
9923 evexlig = evexl256;
9924 else if (strcmp (arg, "512") == 0)
9925 evexlig = evexl512;
9926 else
9927 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9928 break;
9929
d3d3c6db
IT		 9930 case OPTION_MEVEXRCIG:
9931 if (strcmp (arg, "rne") == 0)
9932 evexrcig = rne;
9933 else if (strcmp (arg, "rd") == 0)
9934 evexrcig = rd;
9935 else if (strcmp (arg, "ru") == 0)
9936 evexrcig = ru;
9937 else if (strcmp (arg, "rz") == 0)
9938 evexrcig = rz;
9939 else
9940 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9941 break;
9942
43234a1e
L		 9943 case OPTION_MEVEXWIG:
9944 if (strcmp (arg, "0") == 0)
9945 evexwig = evexw0;
9946 else if (strcmp (arg, "1") == 0)
9947 evexwig = evexw1;
9948 else
9949 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9950 break;
9951
167ad85b
TG		 9952# if defined (TE_PE) || defined (TE_PEP)
9953 case OPTION_MBIG_OBJ:
9954 use_big_obj = 1;
9955 break;
9956#endif
9957
a5094208 9958 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9959 if (strcasecmp (arg, "yes") == 0)
9960 omit_lock_prefix = 1;
9961 else if (strcasecmp (arg, "no") == 0)
9962 omit_lock_prefix = 0;
9963 else
9964 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9965 break;
9966
5db04b09
L		 9967 case OPTION_MAMD64:
9968 cpu_arch_flags.bitfield.cpuamd64 = 1;
9969 cpu_arch_flags.bitfield.cpuintel64 = 0;
9970 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
9971 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
9972 break;
9973
9974 case OPTION_MINTEL64:
9975 cpu_arch_flags.bitfield.cpuamd64 = 0;
9976 cpu_arch_flags.bitfield.cpuintel64 = 1;
9977 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
9978 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
9979 break;
9980
252b5132
RH		 9981 default:
9982 return 0;
9983 }
9984 return 1;
9985}
9986
8a2c8fef
L		 9987#define MESSAGE_TEMPLATE \
9988" "
9989
9990static void
1ded5609 9991show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9992{
9993 static char message[] = MESSAGE_TEMPLATE;
9994 char *start = message + 27;
9995 char *p;
9996 int size = sizeof (MESSAGE_TEMPLATE);
9997 int left;
9998 const char *name;
9999 int len;
10000 unsigned int j;
10001
10002 p = start;
10003 left = size - (start - message);
10004 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10005 {
10006 /* Should it be skipped? */
10007 if (cpu_arch [j].skip)
10008 continue;
10009
10010 name = cpu_arch [j].name;
10011 len = cpu_arch [j].len;
10012 if (*name == '.')
10013 {
10014 /* It is an extension. Skip if we aren't asked to show it. */
10015 if (ext)
10016 {
10017 name++;
10018 len--;
10019 }
10020 else
10021 continue;
10022 }
10023 else if (ext)
10024 {
10025 /* It is an processor. Skip if we show only extension. */
10026 continue;
10027 }
1ded5609
JB		 10028 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10029 {
10030 /* It is an impossible processor - skip. */
10031 continue;
10032 }
8a2c8fef
L		 10033
10034 /* Reserve 2 spaces for ", " or ",\0" */
10035 left -= len + 2;
10036
10037 /* Check if there is any room. */
10038 if (left >= 0)
10039 {
10040 if (p != start)
10041 {
10042 *p++ = ',';
10043 *p++ = ' ';
10044 }
10045 p = mempcpy (p, name, len);
10046 }
10047 else
10048 {
10049 /* Output the current message now and start a new one. */
10050 *p++ = ',';
10051 *p = '\0';
10052 fprintf (stream, "%s\n", message);
10053 p = start;
10054 left = size - (start - message) - len - 2;
8d63c93e 10055
8a2c8fef
L		 10056 gas_assert (left >= 0);
10057
10058 p = mempcpy (p, name, len);
10059 }
10060 }
10061
10062 *p = '\0';
10063 fprintf (stream, "%s\n", message);
10064}
10065
252b5132 10066void
8a2c8fef 10067md_show_usage (FILE *stream)
252b5132 10068{
4cc782b5
ILT		 10069#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10070 fprintf (stream, _("\
a38cf1db
AM		 10071 -Q ignored\n\
10072 -V print assembler version number\n\
b3b91714
AM		 10073 -k ignored\n"));
10074#endif
10075 fprintf (stream, _("\
12b55ccc 10076 -n Do not optimize code alignment\n\
b3b91714
AM		 10077 -q quieten some warnings\n"));
10078#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10079 fprintf (stream, _("\
a38cf1db 10080 -s ignored\n"));
b3b91714 10081#endif
321098a5
L		 10082#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10083 || defined (TE_PE) || defined (TE_PEP))
751d281c 10084 fprintf (stream, _("\
570561f7 10085 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10086#endif
b3b91714
AM		 10087#ifdef SVR4_COMMENT_CHARS
10088 fprintf (stream, _("\
10089 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10090#else
10091 fprintf (stream, _("\
b3b91714 10092 --divide ignored\n"));
4cc782b5 10093#endif
9103f4f4 10094 fprintf (stream, _("\
6305a203 10095 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10096 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10097 show_arch (stream, 0, 1);
8a2c8fef
L		 10098 fprintf (stream, _("\
10099 EXTENSION is combination of:\n"));
1ded5609 10100 show_arch (stream, 1, 0);
6305a203 10101 fprintf (stream, _("\
8a2c8fef 10102 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10103 show_arch (stream, 0, 0);
ba104c83 10104 fprintf (stream, _("\
c0f3af97
L		 10105 -msse2avx encode SSE instructions with VEX prefix\n"));
10106 fprintf (stream, _("\
daf50ae7
L		 10107 -msse-check=[none|error|warning]\n\
10108 check SSE instructions\n"));
10109 fprintf (stream, _("\
7bab8ab5
JB		 10110 -moperand-check=[none|error|warning]\n\
10111 check operand combinations for validity\n"));
10112 fprintf (stream, _("\
539f890d
L		 10113 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10114 length\n"));
10115 fprintf (stream, _("\
43234a1e
L		 10116 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10117 length\n"));
10118 fprintf (stream, _("\
10119 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10120 for EVEX.W bit ignored instructions\n"));
10121 fprintf (stream, _("\
d3d3c6db
IT		 10122 -mevexrcig=[rne|rd|ru|rz]\n\
10123 encode EVEX instructions with specific EVEX.RC value\n\
10124 for SAE-only ignored instructions\n"));
10125 fprintf (stream, _("\
ba104c83
L		 10126 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10127 fprintf (stream, _("\
10128 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10129 fprintf (stream, _("\
10130 -mindex-reg support pseudo index registers\n"));
10131 fprintf (stream, _("\
10132 -mnaked-reg don't require `%%' prefix for registers\n"));
10133 fprintf (stream, _("\
10134 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10135 fprintf (stream, _("\
10136 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10137 fprintf (stream, _("\
10138 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10139# if defined (TE_PE) || defined (TE_PEP)
10140 fprintf (stream, _("\
10141 -mbig-obj generate big object files\n"));
10142#endif
d022bddd
IT		 10143 fprintf (stream, _("\
10144 -momit-lock-prefix=[no|yes]\n\
10145 strip all lock prefixes\n"));
5db04b09
L		 10146 fprintf (stream, _("\
10147 -mamd64 accept only AMD64 ISA\n"));
10148 fprintf (stream, _("\
10149 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10150}
10151
3e73aa7c 10152#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10153 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10154 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10155
10156/* Pick the target format to use. */
10157
47926f60 10158const char *
e3bb37b5 10159i386_target_format (void)
252b5132 10160{
351f65ca
L		 10161 if (!strncmp (default_arch, "x86_64", 6))
10162 {
10163 update_code_flag (CODE_64BIT, 1);
10164 if (default_arch[6] == '\0')
7f56bc95 10165 x86_elf_abi = X86_64_ABI;
351f65ca 10166 else
7f56bc95 10167 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10168 }
3e73aa7c 10169 else if (!strcmp (default_arch, "i386"))
78f12dd3 10170 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10171 else if (!strcmp (default_arch, "iamcu"))
10172 {
10173 update_code_flag (CODE_32BIT, 1);
10174 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10175 {
10176 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10177 cpu_arch_name = "iamcu";
10178 cpu_sub_arch_name = NULL;
10179 cpu_arch_flags = iamcu_flags;
10180 cpu_arch_isa = PROCESSOR_IAMCU;
10181 cpu_arch_isa_flags = iamcu_flags;
10182 if (!cpu_arch_tune_set)
10183 {
10184 cpu_arch_tune = cpu_arch_isa;
10185 cpu_arch_tune_flags = cpu_arch_isa_flags;
10186 }
10187 }
10188 else
10189 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10190 cpu_arch_name);
10191 }
3e73aa7c 10192 else
2b5d6a91 10193 as_fatal (_("unknown architecture"));
89507696
JB		 10194
10195 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10196 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10197 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10198 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10199
252b5132
RH		 10200 switch (OUTPUT_FLAVOR)
10201 {
9384f2ff 10202#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10203 case bfd_target_aout_flavour:
47926f60 10204 return AOUT_TARGET_FORMAT;
4c63da97 10205#endif
9384f2ff
AM		 10206#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10207# if defined (TE_PE) || defined (TE_PEP)
10208 case bfd_target_coff_flavour:
167ad85b
TG		 10209 if (flag_code == CODE_64BIT)
10210 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10211 else
10212 return "pe-i386";
9384f2ff 10213# elif defined (TE_GO32)
0561d57c
JK		 10214 case bfd_target_coff_flavour:
10215 return "coff-go32";
9384f2ff 10216# else
252b5132
RH		 10217 case bfd_target_coff_flavour:
10218 return "coff-i386";
9384f2ff 10219# endif
4c63da97 10220#endif
3e73aa7c 10221#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10222 case bfd_target_elf_flavour:
3e73aa7c 10223 {
351f65ca
L		 10224 const char *format;
10225
10226 switch (x86_elf_abi)
4fa24527 10227 {
351f65ca
L		 10228 default:
10229 format = ELF_TARGET_FORMAT;
10230 break;
7f56bc95 10231 case X86_64_ABI:
351f65ca 10232 use_rela_relocations = 1;
4fa24527 10233 object_64bit = 1;
351f65ca
L		 10234 format = ELF_TARGET_FORMAT64;
10235 break;
7f56bc95 10236 case X86_64_X32_ABI:
4fa24527 10237 use_rela_relocations = 1;
351f65ca 10238 object_64bit = 1;
862be3fb 10239 disallow_64bit_reloc = 1;
351f65ca
L		 10240 format = ELF_TARGET_FORMAT32;
10241 break;
4fa24527 10242 }
3632d14b 10243 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10244 {
7f56bc95 10245 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10246 as_fatal (_("Intel L1OM is 64bit only"));
10247 return ELF_TARGET_L1OM_FORMAT;
10248 }
b49f93f6 10249 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10250 {
10251 if (x86_elf_abi != X86_64_ABI)
10252 as_fatal (_("Intel K1OM is 64bit only"));
10253 return ELF_TARGET_K1OM_FORMAT;
10254 }
81486035
L		 10255 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10256 {
10257 if (x86_elf_abi != I386_ABI)
10258 as_fatal (_("Intel MCU is 32bit only"));
10259 return ELF_TARGET_IAMCU_FORMAT;
10260 }
8a9036a4 10261 else
351f65ca 10262 return format;
3e73aa7c 10263 }
e57f8c65
TG		 10264#endif
10265#if defined (OBJ_MACH_O)
10266 case bfd_target_mach_o_flavour:
d382c579
TG		 10267 if (flag_code == CODE_64BIT)
10268 {
10269 use_rela_relocations = 1;
10270 object_64bit = 1;
10271 return "mach-o-x86-64";
10272 }
10273 else
10274 return "mach-o-i386";
4c63da97 10275#endif
252b5132
RH		 10276 default:
10277 abort ();
10278 return NULL;
10279 }
10280}
10281
47926f60 10282#endif /* OBJ_MAYBE_ more than one */
252b5132 10283\f
252b5132 10284symbolS *
7016a5d5 10285md_undefined_symbol (char *name)
252b5132 10286{
18dc2407
ILT		 10287 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10288 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10289 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10290 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10291 {
10292 if (!GOT_symbol)
10293 {
10294 if (symbol_find (name))
10295 as_bad (_("GOT already in symbol table"));
10296 GOT_symbol = symbol_new (name, undefined_section,
10297 (valueT) 0, &zero_address_frag);
10298 };
10299 return GOT_symbol;
10300 }
252b5132
RH		 10301 return 0;
10302}
10303
10304/* Round up a section size to the appropriate boundary. */
47926f60 10305
252b5132 10306valueT
7016a5d5 10307md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10308{
4c63da97
AM		 10309#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10310 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10311 {
10312 /* For a.out, force the section size to be aligned. If we don't do
10313 this, BFD will align it for us, but it will not write out the
10314 final bytes of the section. This may be a bug in BFD, but it is
10315 easier to fix it here since that is how the other a.out targets
10316 work. */
10317 int align;
10318
10319 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10320 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10321 }
252b5132
RH		 10322#endif
10323
10324 return size;
10325}
10326
10327/* On the i386, PC-relative offsets are relative to the start of the
10328 next instruction. That is, the address of the offset, plus its
10329 size, since the offset is always the last part of the insn. */
10330
10331long
e3bb37b5 10332md_pcrel_from (fixS *fixP)
252b5132
RH		 10333{
10334 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10335}
10336
10337#ifndef I386COFF
10338
10339static void
e3bb37b5 10340s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10341{
29b0f896 10342 int temp;
252b5132 10343
8a75718c
JB		 10344#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10345 if (IS_ELF)
10346 obj_elf_section_change_hook ();
10347#endif
252b5132
RH		 10348 temp = get_absolute_expression ();
10349 subseg_set (bss_section, (subsegT) temp);
10350 demand_empty_rest_of_line ();
10351}
10352
10353#endif
10354
252b5132 10355void
e3bb37b5 10356i386_validate_fix (fixS *fixp)
252b5132 10357{
02a86693 10358 if (fixp->fx_subsy)
252b5132 10359 {
02a86693 10360 if (fixp->fx_subsy == GOT_symbol)
23df1078 10361 {
02a86693
L		 10362 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10363 {
10364 if (!object_64bit)
10365 abort ();
10366#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10367 if (fixp->fx_tcbit2)
56ceb5b5
L		 10368 fixp->fx_r_type = (fixp->fx_tcbit
10369 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10370 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10371 else
10372#endif
10373 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10374 }
d6ab8113 10375 else
02a86693
L		 10376 {
10377 if (!object_64bit)
10378 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10379 else
10380 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10381 }
10382 fixp->fx_subsy = 0;
23df1078 10383 }
252b5132 10384 }
02a86693
L		 10385#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10386 else if (!object_64bit)
10387 {
10388 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10389 && fixp->fx_tcbit2)
10390 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10391 }
10392#endif
252b5132
RH		 10393}
10394
252b5132 10395arelent *
7016a5d5 10396tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10397{
10398 arelent *rel;
10399 bfd_reloc_code_real_type code;
10400
10401 switch (fixp->fx_r_type)
10402 {
8ce3d284 10403#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10404 case BFD_RELOC_SIZE32:
10405 case BFD_RELOC_SIZE64:
10406 if (S_IS_DEFINED (fixp->fx_addsy)
10407 && !S_IS_EXTERNAL (fixp->fx_addsy))
10408 {
10409 /* Resolve size relocation against local symbol to size of
10410 the symbol plus addend. */
10411 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10412 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10413 && !fits_in_unsigned_long (value))
10414 as_bad_where (fixp->fx_file, fixp->fx_line,
10415 _("symbol size computation overflow"));
10416 fixp->fx_addsy = NULL;
10417 fixp->fx_subsy = NULL;
10418 md_apply_fix (fixp, (valueT *) &value, NULL);
10419 return NULL;
10420 }
8ce3d284 10421#endif
8fd4256d 10422
3e73aa7c
JH		 10423 case BFD_RELOC_X86_64_PLT32:
10424 case BFD_RELOC_X86_64_GOT32:
10425 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10426 case BFD_RELOC_X86_64_GOTPCRELX:
10427 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10428 case BFD_RELOC_386_PLT32:
10429 case BFD_RELOC_386_GOT32:
02a86693 10430 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10431 case BFD_RELOC_386_GOTOFF:
10432 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10433 case BFD_RELOC_386_TLS_GD:
10434 case BFD_RELOC_386_TLS_LDM:
10435 case BFD_RELOC_386_TLS_LDO_32:
10436 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10437 case BFD_RELOC_386_TLS_IE:
10438 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10439 case BFD_RELOC_386_TLS_LE_32:
10440 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10441 case BFD_RELOC_386_TLS_GOTDESC:
10442 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10443 case BFD_RELOC_X86_64_TLSGD:
10444 case BFD_RELOC_X86_64_TLSLD:
10445 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10446 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10447 case BFD_RELOC_X86_64_GOTTPOFF:
10448 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10449 case BFD_RELOC_X86_64_TPOFF64:
10450 case BFD_RELOC_X86_64_GOTOFF64:
10451 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10452 case BFD_RELOC_X86_64_GOT64:
10453 case BFD_RELOC_X86_64_GOTPCREL64:
10454 case BFD_RELOC_X86_64_GOTPC64:
10455 case BFD_RELOC_X86_64_GOTPLT64:
10456 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10457 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10458 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10459 case BFD_RELOC_RVA:
10460 case BFD_RELOC_VTABLE_ENTRY:
10461 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10462#ifdef TE_PE
10463 case BFD_RELOC_32_SECREL:
10464#endif
252b5132
RH		 10465 code = fixp->fx_r_type;
10466 break;
dbbaec26
L		 10467 case BFD_RELOC_X86_64_32S:
10468 if (!fixp->fx_pcrel)
10469 {
10470 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10471 code = fixp->fx_r_type;
10472 break;
10473 }
252b5132 10474 default:
93382f6d 10475 if (fixp->fx_pcrel)
252b5132 10476 {
93382f6d
AM		 10477 switch (fixp->fx_size)
10478 {
10479 default:
b091f402
AM		 10480 as_bad_where (fixp->fx_file, fixp->fx_line,
10481 _("can not do %d byte pc-relative relocation"),
10482 fixp->fx_size);
93382f6d
AM		 10483 code = BFD_RELOC_32_PCREL;
10484 break;
10485 case 1: code = BFD_RELOC_8_PCREL; break;
10486 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10487 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10488#ifdef BFD64
10489 case 8: code = BFD_RELOC_64_PCREL; break;
10490#endif
93382f6d
AM		 10491 }
10492 }
10493 else
10494 {
10495 switch (fixp->fx_size)
10496 {
10497 default:
b091f402
AM		 10498 as_bad_where (fixp->fx_file, fixp->fx_line,
10499 _("can not do %d byte relocation"),
10500 fixp->fx_size);
93382f6d
AM		 10501 code = BFD_RELOC_32;
10502 break;
10503 case 1: code = BFD_RELOC_8; break;
10504 case 2: code = BFD_RELOC_16; break;
10505 case 4: code = BFD_RELOC_32; break;
937149dd 10506#ifdef BFD64
3e73aa7c 10507 case 8: code = BFD_RELOC_64; break;
937149dd 10508#endif
93382f6d 10509 }
252b5132
RH		 10510 }
10511 break;
10512 }
252b5132 10513
d182319b
JB		 10514 if ((code == BFD_RELOC_32
10515 || code == BFD_RELOC_32_PCREL
10516 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10517 && GOT_symbol
10518 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10519 {
4fa24527 10520 if (!object_64bit)
d6ab8113
JB		 10521 code = BFD_RELOC_386_GOTPC;
10522 else
10523 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10524 }
7b81dfbb
AJ		 10525 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10526 && GOT_symbol
10527 && fixp->fx_addsy == GOT_symbol)
10528 {
10529 code = BFD_RELOC_X86_64_GOTPC64;
10530 }
252b5132
RH		 10531
10532 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10533 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10534 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10535
10536 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10537
3e73aa7c
JH		 10538 if (!use_rela_relocations)
10539 {
10540 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10541 vtable entry to be used in the relocation's section offset. */
10542 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10543 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10544#if defined (OBJ_COFF) && defined (TE_PE)
10545 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10546 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10547 else
10548#endif
c6682705 10549 rel->addend = 0;
3e73aa7c
JH		 10550 }
10551 /* Use the rela in 64bit mode. */
252b5132 10552 else
3e73aa7c 10553 {
862be3fb
L		 10554 if (disallow_64bit_reloc)
10555 switch (code)
10556 {
862be3fb
L		 10557 case BFD_RELOC_X86_64_DTPOFF64:
10558 case BFD_RELOC_X86_64_TPOFF64:
10559 case BFD_RELOC_64_PCREL:
10560 case BFD_RELOC_X86_64_GOTOFF64:
10561 case BFD_RELOC_X86_64_GOT64:
10562 case BFD_RELOC_X86_64_GOTPCREL64:
10563 case BFD_RELOC_X86_64_GOTPC64:
10564 case BFD_RELOC_X86_64_GOTPLT64:
10565 case BFD_RELOC_X86_64_PLTOFF64:
10566 as_bad_where (fixp->fx_file, fixp->fx_line,
10567 _("cannot represent relocation type %s in x32 mode"),
10568 bfd_get_reloc_code_name (code));
10569 break;
10570 default:
10571 break;
10572 }
10573
062cd5e7
AS		 10574 if (!fixp->fx_pcrel)
10575 rel->addend = fixp->fx_offset;
10576 else
10577 switch (code)
10578 {
10579 case BFD_RELOC_X86_64_PLT32:
10580 case BFD_RELOC_X86_64_GOT32:
10581 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10582 case BFD_RELOC_X86_64_GOTPCRELX:
10583 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10584 case BFD_RELOC_X86_64_TLSGD:
10585 case BFD_RELOC_X86_64_TLSLD:
10586 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10587 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10588 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10589 rel->addend = fixp->fx_offset - fixp->fx_size;
10590 break;
10591 default:
10592 rel->addend = (section->vma
10593 - fixp->fx_size
10594 + fixp->fx_addnumber
10595 + md_pcrel_from (fixp));
10596 break;
10597 }
3e73aa7c
JH		 10598 }
10599
252b5132
RH		 10600 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10601 if (rel->howto == NULL)
10602 {
10603 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10604 _("cannot represent relocation type %s"),
252b5132
RH		 10605 bfd_get_reloc_code_name (code));
10606 /* Set howto to a garbage value so that we can keep going. */
10607 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10608 gas_assert (rel->howto != NULL);
252b5132
RH		 10609 }
10610
10611 return rel;
10612}
10613
ee86248c 10614#include "tc-i386-intel.c"
54cfded0 10615
a60de03c
JB		 10616void
10617tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10618{
a60de03c
JB		 10619 int saved_naked_reg;
10620 char saved_register_dot;
54cfded0 10621
a60de03c
JB		 10622 saved_naked_reg = allow_naked_reg;
10623 allow_naked_reg = 1;
10624 saved_register_dot = register_chars['.'];
10625 register_chars['.'] = '.';
10626 allow_pseudo_reg = 1;
10627 expression_and_evaluate (exp);
10628 allow_pseudo_reg = 0;
10629 register_chars['.'] = saved_register_dot;
10630 allow_naked_reg = saved_naked_reg;
10631
e96d56a1 10632 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10633 {
a60de03c
JB		 10634 if ((addressT) exp->X_add_number < i386_regtab_size)
10635 {
10636 exp->X_op = O_constant;
10637 exp->X_add_number = i386_regtab[exp->X_add_number]
10638 .dw2_regnum[flag_code >> 1];
10639 }
10640 else
10641 exp->X_op = O_illegal;
54cfded0 10642 }
54cfded0
AM		 10643}
10644
10645void
10646tc_x86_frame_initial_instructions (void)
10647{
a60de03c
JB		 10648 static unsigned int sp_regno[2];
10649
10650 if (!sp_regno[flag_code >> 1])
10651 {
10652 char *saved_input = input_line_pointer;
10653 char sp[][4] = {"esp", "rsp"};
10654 expressionS exp;
a4447b93 10655
a60de03c
JB		 10656 input_line_pointer = sp[flag_code >> 1];
10657 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10658 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10659 sp_regno[flag_code >> 1] = exp.X_add_number;
10660 input_line_pointer = saved_input;
10661 }
a4447b93 10662
61ff971f
L		 10663 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10664 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10665}
d2b2c203 10666
d7921315
L		 10667int
10668x86_dwarf2_addr_size (void)
10669{
10670#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10671 if (x86_elf_abi == X86_64_X32_ABI)
10672 return 4;
10673#endif
10674 return bfd_arch_bits_per_address (stdoutput) / 8;
10675}
10676
d2b2c203
DJ		 10677int
10678i386_elf_section_type (const char *str, size_t len)
10679{
10680 if (flag_code == CODE_64BIT
10681 && len == sizeof ("unwind") - 1
10682 && strncmp (str, "unwind", 6) == 0)
10683 return SHT_X86_64_UNWIND;
10684
10685 return -1;
10686}
bb41ade5 10687
ad5fec3b
EB		 10688#ifdef TE_SOLARIS
10689void
10690i386_solaris_fix_up_eh_frame (segT sec)
10691{
10692 if (flag_code == CODE_64BIT)
10693 elf_section_type (sec) = SHT_X86_64_UNWIND;
10694}
10695#endif
10696
bb41ade5
AM		 10697#ifdef TE_PE
10698void
10699tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10700{
91d6fa6a 10701 expressionS exp;
bb41ade5 10702
91d6fa6a
NC		 10703 exp.X_op = O_secrel;
10704 exp.X_add_symbol = symbol;
10705 exp.X_add_number = 0;
10706 emit_expr (&exp, size);
bb41ade5
AM		 10707}
10708#endif
3b22753a
L		 10709
10710#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10711/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10712
01e1a5bc 10713bfd_vma
3b22753a
L		 10714x86_64_section_letter (int letter, char **ptr_msg)
10715{
10716 if (flag_code == CODE_64BIT)
10717 {
10718 if (letter == 'l')
10719 return SHF_X86_64_LARGE;
10720
8f3bae45 10721 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10722 }
3b22753a 10723 else
8f3bae45 10724 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10725 return -1;
10726}
10727
01e1a5bc 10728bfd_vma
3b22753a
L		 10729x86_64_section_word (char *str, size_t len)
10730{
8620418b 10731 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10732 return SHF_X86_64_LARGE;
10733
10734 return -1;
10735}
10736
10737static void
10738handle_large_common (int small ATTRIBUTE_UNUSED)
10739{
10740 if (flag_code != CODE_64BIT)
10741 {
10742 s_comm_internal (0, elf_common_parse);
10743 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10744 }
10745 else
10746 {
10747 static segT lbss_section;
10748 asection *saved_com_section_ptr = elf_com_section_ptr;
10749 asection *saved_bss_section = bss_section;
10750
10751 if (lbss_section == NULL)
10752 {
10753 flagword applicable;
10754 segT seg = now_seg;
10755 subsegT subseg = now_subseg;
10756
10757 /* The .lbss section is for local .largecomm symbols. */
10758 lbss_section = subseg_new (".lbss", 0);
10759 applicable = bfd_applicable_section_flags (stdoutput);
10760 bfd_set_section_flags (stdoutput, lbss_section,
10761 applicable & SEC_ALLOC);
10762 seg_info (lbss_section)->bss = 1;
10763
10764 subseg_set (seg, subseg);
10765 }
10766
10767 elf_com_section_ptr = &_bfd_elf_large_com_section;
10768 bss_section = lbss_section;
10769
10770 s_comm_internal (0, elf_common_parse);
10771
10772 elf_com_section_ptr = saved_com_section_ptr;
10773 bss_section = saved_bss_section;
10774 }
10775}
10776#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 2.218445 seconds and 4 git commands to generate.