projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
*** empty log message ***
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
99 const template *start;
100 const template *end;
101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
116/* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119#define DREX_OC0(x) (((x) & 1) != 0)
120#define DREX_OC1(x) (((x) & 2) != 0)
121
122#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
124
125/* OC mappings */
126#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
130
131#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
133
134/* Information needed to create the DREX byte in SSE5 instructions. */
135typedef struct
136{
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
141} drex_byte;
142
143/* 386 opcode byte to code indirect addressing. */
144typedef struct
145{
146 unsigned base;
147 unsigned index;
148 unsigned scale;
149}
150sib_byte;
151
152enum processor_type
153{
154 PROCESSOR_UNKNOWN,
155 PROCESSOR_I386,
156 PROCESSOR_I486,
157 PROCESSOR_PENTIUM,
158 PROCESSOR_PENTIUMPRO,
159 PROCESSOR_PENTIUM4,
160 PROCESSOR_NOCONA,
161 PROCESSOR_CORE,
162 PROCESSOR_CORE2,
163 PROCESSOR_K6,
164 PROCESSOR_ATHLON,
165 PROCESSOR_K8,
166 PROCESSOR_GENERIC32,
167 PROCESSOR_GENERIC64,
168 PROCESSOR_AMDFAM10
169};
170
171/* x86 arch names, types and features */
172typedef struct
173{
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
177}
178arch_entry;
179
e3bb37b5
L		 180static void set_code_flag (int);
181static void set_16bit_gcc_code_flag (int);
182static void set_intel_syntax (int);
1efbbeb4 183static void set_intel_mnemonic (int);
db51cc60 184static void set_allow_index_reg (int);
e3bb37b5 185static void set_cpu_arch (int);
6482c264 186#ifdef TE_PE
e3bb37b5 187static void pe_directive_secrel (int);
6482c264 188#endif
e3bb37b5
L		 189static void signed_cons (int);
190static char *output_invalid (int c);
a7619375 191static int i386_att_operand (char *);
e3bb37b5
L		 192static int i386_intel_operand (char *, int);
193static const reg_entry *parse_register (char *, char **);
194static char *parse_insn (char *, char *);
195static char *parse_operands (char *, const char *);
196static void swap_operands (void);
4d456e3d 197static void swap_2_operands (int, int);
e3bb37b5
L		 198static void optimize_imm (void);
199static void optimize_disp (void);
200static int match_template (void);
201static int check_string (void);
202static int process_suffix (void);
203static int check_byte_reg (void);
204static int check_long_reg (void);
205static int check_qword_reg (void);
206static int check_word_reg (void);
207static int finalize_imm (void);
85f10a01 208static void process_drex (void);
e3bb37b5
L		 209static int process_operands (void);
210static const seg_entry *build_modrm_byte (void);
211static void output_insn (void);
212static void output_imm (fragS *, offsetT);
213static void output_disp (fragS *, offsetT);
29b0f896 214#ifndef I386COFF
e3bb37b5 215static void s_bss (int);
252b5132 216#endif
17d4e2a2
L		 217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218static void handle_large_common (int small ATTRIBUTE_UNUSED);
219#endif
252b5132 220
a847613f 221static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 222
252b5132 223/* 'md_assemble ()' gathers together information and puts it into a
47926f60 224 i386_insn. */
252b5132 225
520dc8e8
AM		 226union i386_op
227 {
228 expressionS *disps;
229 expressionS *imms;
230 const reg_entry *regs;
231 };
232
252b5132
RH		 233struct _i386_insn
234 {
47926f60 235 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 236 template tm;
237
7d5e4556
L		 238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
252b5132
RH		 240 char suffix;
241
47926f60 242 /* OPERANDS gives the number of given operands. */
252b5132
RH		 243 unsigned int operands;
244
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
47926f60 247 operands. */
252b5132
RH		 248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
249
250 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 251 use OP[i] for the corresponding operand. */
40fb9820 252 i386_operand_type types[MAX_OPERANDS];
252b5132 253
520dc8e8
AM		 254 /* Displacement expression, immediate expression, or register for each
255 operand. */
256 union i386_op op[MAX_OPERANDS];
252b5132 257
3e73aa7c
JH		 258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260#define Operand_PCrel 1
261
252b5132 262 /* Relocation type for operand */
f86103b7 263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 264
252b5132
RH		 265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
270
271 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 272 explicit segment overrides are given. */
ce8a8b2f 273 const seg_entry *seg[2];
252b5132
RH		 274
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
279
280 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
252b5132
RH		 283
284 modrm_byte rm;
3e73aa7c 285 rex_byte rex;
252b5132 286 sib_byte sib;
85f10a01 287 drex_byte drex;
252b5132
RH		 288 };
289
290typedef struct _i386_insn i386_insn;
291
292/* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
32137342 294const char extra_symbol_chars[] = "*%-(["
252b5132 295#ifdef LEX_AT
32137342
NC		 296 "@"
297#endif
298#ifdef LEX_QM
299 "?"
252b5132 300#endif
32137342 301 ;
252b5132 302
29b0f896
AM		 303#if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 305 && !defined (TE_GNU) \
29b0f896 306 && !defined (TE_LINUX) \
32137342 307 && !defined (TE_NETWARE) \
29b0f896
AM		 308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
252b5132 310/* This array holds the chars that always start a comment. If the
b3b91714
AM		 311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313const char *i386_comment_chars = "#/";
314#define SVR4_COMMENT_CHARS 1
252b5132 315#define PREFIX_SEPARATOR '\\'
252b5132 316
b3b91714
AM		 317#else
318const char *i386_comment_chars = "#";
319#define PREFIX_SEPARATOR '/'
320#endif
321
252b5132
RH		 322/* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 326 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
252b5132 329 '/' isn't otherwise defined. */
b3b91714 330const char line_comment_chars[] = "#/";
252b5132 331
63a0b638 332const char line_separator_chars[] = ";";
252b5132 333
ce8a8b2f
AM		 334/* Chars that can be used to separate mant from exp in floating point
335 nums. */
252b5132
RH		 336const char EXP_CHARS[] = "eE";
337
ce8a8b2f
AM		 338/* Chars that mean this number is a floating point constant
339 As in 0f12.456
340 or 0d1.2345e12. */
252b5132
RH		 341const char FLT_CHARS[] = "fFdDxX";
342
ce8a8b2f 343/* Tables for lexical analysis. */
252b5132
RH		 344static char mnemonic_chars[256];
345static char register_chars[256];
346static char operand_chars[256];
347static char identifier_chars[256];
348static char digit_chars[256];
349
ce8a8b2f 350/* Lexical macros. */
252b5132
RH		 351#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352#define is_operand_char(x) (operand_chars[(unsigned char) x])
353#define is_register_char(x) (register_chars[(unsigned char) x])
354#define is_space_char(x) ((x) == ' ')
355#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356#define is_digit_char(x) (digit_chars[(unsigned char) x])
357
0234cb7c 358/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 359static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
360
361/* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
47926f60 364 assembler instruction). */
252b5132 365static char save_stack[32];
ce8a8b2f 366static char *save_stack_p;
252b5132
RH		 367#define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369#define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
371
47926f60 372/* The instruction we're assembling. */
252b5132
RH		 373static i386_insn i;
374
375/* Possible templates for current insn. */
376static const templates *current_templates;
377
31b2323c
L		 378/* Per instruction expressionS buffers: max displacements & immediates. */
379static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 381
47926f60
KH		 382/* Current operand we are working on. */
383static int this_operand;
252b5132 384
3e73aa7c
JH		 385/* We support four different modes. FLAG_CODE variable is used to distinguish
386 these. */
387
388enum flag_code {
389 CODE_32BIT,
390 CODE_16BIT,
391 CODE_64BIT };
392
393static enum flag_code flag_code;
4fa24527 394static unsigned int object_64bit;
3e73aa7c
JH		 395static int use_rela_relocations = 0;
396
397/* The names used to print error messages. */
b77a7acd 398static const char *flag_code_names[] =
3e73aa7c
JH		 399 {
400 "32",
401 "16",
402 "64"
403 };
252b5132 404
47926f60
KH		 405/* 1 for intel syntax,
406 0 if att syntax. */
407static int intel_syntax = 0;
252b5132 408
1efbbeb4
L		 409/* 1 for intel mnemonic,
410 0 if att mnemonic. */
411static int intel_mnemonic = !SYSV386_COMPAT;
412
5209009a 413/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 414static int old_gcc = OLDGCC_COMPAT;
415
a60de03c
JB		 416/* 1 if pseudo registers are permitted. */
417static int allow_pseudo_reg = 0;
418
47926f60
KH		 419/* 1 if register prefix % not required. */
420static int allow_naked_reg = 0;
252b5132 421
ba104c83 422/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 423static int allow_index_reg = 0;
424
2ca3ace5
L		 425/* Register prefix used for error message. */
426static const char *register_prefix = "%";
427
47926f60
KH		 428/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431static char stackop_size = '\0';
eecb386c 432
12b55ccc
L		 433/* Non-zero to optimize code alignment. */
434int optimize_align_code = 1;
435
47926f60
KH		 436/* Non-zero to quieten some warnings. */
437static int quiet_warnings = 0;
a38cf1db 438
47926f60
KH		 439/* CPU name. */
440static const char *cpu_arch_name = NULL;
6305a203 441static char *cpu_sub_arch_name = NULL;
a38cf1db 442
47926f60 443/* CPU feature flags. */
40fb9820
L		 444static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
445
ccc9c027
L		 446/* If we have selected a cpu we are generating instructions for. */
447static int cpu_arch_tune_set = 0;
448
9103f4f4
L		 449/* Cpu we are generating instructions for. */
450static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
451
452/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 453static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 454
ccc9c027
L		 455/* CPU instruction set architecture used. */
456static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
457
9103f4f4 458/* CPU feature flags of instruction set architecture used. */
40fb9820 459static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 460
fddf5b5b
AM		 461/* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463static unsigned int no_cond_jump_promotion = 0;
464
29b0f896 465/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 466static symbolS *GOT_symbol;
29b0f896 467
a4447b93
RH		 468/* The dwarf2 return column, adjusted for 32 or 64 bit. */
469unsigned int x86_dwarf2_return_column;
470
471/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
472int x86_cie_data_alignment;
473
252b5132 474/* Interface to relax_segment.
fddf5b5b
AM		 475 There are 3 major relax states for 386 jump insns because the
476 different types of jumps add different sizes to frags when we're
477 figuring out what sort of jump to choose to reach a given label. */
252b5132 478
47926f60 479/* Types. */
93c2a809
AM		 480#define UNCOND_JUMP 0
481#define COND_JUMP 1
482#define COND_JUMP86 2
fddf5b5b 483
47926f60 484/* Sizes. */
252b5132
RH		 485#define CODE16 1
486#define SMALL 0
29b0f896 487#define SMALL16 (SMALL | CODE16)
252b5132 488#define BIG 2
29b0f896 489#define BIG16 (BIG | CODE16)
252b5132
RH		 490
491#ifndef INLINE
492#ifdef __GNUC__
493#define INLINE __inline__
494#else
495#define INLINE
496#endif
497#endif
498
fddf5b5b
AM		 499#define ENCODE_RELAX_STATE(type, size) \
500 ((relax_substateT) (((type) << 2) | (size)))
501#define TYPE_FROM_RELAX_STATE(s) \
502 ((s) >> 2)
503#define DISP_SIZE_FROM_RELAX_STATE(s) \
504 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 505
506/* This table is used by relax_frag to promote short jumps to long
507 ones where necessary. SMALL (short) jumps may be promoted to BIG
508 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
509 don't allow a short jump in a 32 bit code segment to be promoted to
510 a 16 bit offset jump because it's slower (requires data size
511 prefix), and doesn't work, unless the destination is in the bottom
512 64k of the code segment (The top 16 bits of eip are zeroed). */
513
514const relax_typeS md_relax_table[] =
515{
24eab124
AM		 516 /* The fields are:
517 1) most positive reach of this state,
518 2) most negative reach of this state,
93c2a809 519 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 520 4) which index into the table to try if we can't fit into this one. */
252b5132 521
fddf5b5b 522 /* UNCOND_JUMP states. */
93c2a809
AM		 523 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
524 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
525 /* dword jmp adds 4 bytes to frag:
526 0 extra opcode bytes, 4 displacement bytes. */
252b5132 527 {0, 0, 4, 0},
93c2a809
AM		 528 /* word jmp adds 2 byte2 to frag:
529 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 530 {0, 0, 2, 0},
531
93c2a809
AM		 532 /* COND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
535 /* dword conditionals adds 5 bytes to frag:
536 1 extra opcode byte, 4 displacement bytes. */
537 {0, 0, 5, 0},
fddf5b5b 538 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 539 1 extra opcode byte, 2 displacement bytes. */
540 {0, 0, 3, 0},
541
542 /* COND_JUMP86 states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
547 {0, 0, 5, 0},
548 /* word conditionals add 4 bytes to frag:
549 1 displacement byte and a 3 byte long branch insn. */
550 {0, 0, 4, 0}
252b5132
RH		 551};
552
9103f4f4
L		 553static const arch_entry cpu_arch[] =
554{
6305a203
L		 555 { "generic32", PROCESSOR_GENERIC32,
556 CPU_GENERIC32_FLAGS },
557 { "generic64", PROCESSOR_GENERIC64,
558 CPU_GENERIC64_FLAGS },
559 { "i8086", PROCESSOR_UNKNOWN,
560 CPU_NONE_FLAGS },
561 { "i186", PROCESSOR_UNKNOWN,
562 CPU_I186_FLAGS },
563 { "i286", PROCESSOR_UNKNOWN,
564 CPU_I286_FLAGS },
565 { "i386", PROCESSOR_I386,
566 CPU_I386_FLAGS },
567 { "i486", PROCESSOR_I486,
568 CPU_I486_FLAGS },
569 { "i586", PROCESSOR_PENTIUM,
570 CPU_I586_FLAGS },
571 { "i686", PROCESSOR_PENTIUMPRO,
572 CPU_I686_FLAGS },
573 { "pentium", PROCESSOR_PENTIUM,
574 CPU_I586_FLAGS },
575 { "pentiumpro", PROCESSOR_PENTIUMPRO,
576 CPU_I686_FLAGS },
577 { "pentiumii", PROCESSOR_PENTIUMPRO,
578 CPU_P2_FLAGS },
579 { "pentiumiii",PROCESSOR_PENTIUMPRO,
580 CPU_P3_FLAGS },
581 { "pentium4", PROCESSOR_PENTIUM4,
582 CPU_P4_FLAGS },
583 { "prescott", PROCESSOR_NOCONA,
584 CPU_CORE_FLAGS },
585 { "nocona", PROCESSOR_NOCONA,
586 CPU_NOCONA_FLAGS },
587 { "yonah", PROCESSOR_CORE,
588 CPU_CORE_FLAGS },
589 { "core", PROCESSOR_CORE,
590 CPU_CORE_FLAGS },
591 { "merom", PROCESSOR_CORE2,
592 CPU_CORE2_FLAGS },
593 { "core2", PROCESSOR_CORE2,
594 CPU_CORE2_FLAGS },
595 { "k6", PROCESSOR_K6,
596 CPU_K6_FLAGS },
597 { "k6_2", PROCESSOR_K6,
598 CPU_K6_2_FLAGS },
599 { "athlon", PROCESSOR_ATHLON,
600 CPU_ATHLON_FLAGS },
601 { "sledgehammer", PROCESSOR_K8,
602 CPU_K8_FLAGS },
603 { "opteron", PROCESSOR_K8,
604 CPU_K8_FLAGS },
605 { "k8", PROCESSOR_K8,
606 CPU_K8_FLAGS },
607 { "amdfam10", PROCESSOR_AMDFAM10,
608 CPU_AMDFAM10_FLAGS },
609 { ".mmx", PROCESSOR_UNKNOWN,
610 CPU_MMX_FLAGS },
611 { ".sse", PROCESSOR_UNKNOWN,
612 CPU_SSE_FLAGS },
613 { ".sse2", PROCESSOR_UNKNOWN,
614 CPU_SSE2_FLAGS },
615 { ".sse3", PROCESSOR_UNKNOWN,
616 CPU_SSE3_FLAGS },
617 { ".ssse3", PROCESSOR_UNKNOWN,
618 CPU_SSSE3_FLAGS },
619 { ".sse4.1", PROCESSOR_UNKNOWN,
620 CPU_SSE4_1_FLAGS },
621 { ".sse4.2", PROCESSOR_UNKNOWN,
622 CPU_SSE4_2_FLAGS },
623 { ".sse4", PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS },
625 { ".vmx", PROCESSOR_UNKNOWN,
626 CPU_VMX_FLAGS },
627 { ".smx", PROCESSOR_UNKNOWN,
628 CPU_SMX_FLAGS },
f03fe4c1
L		 629 { ".xsave", PROCESSOR_UNKNOWN,
630 CPU_XSAVE_FLAGS },
6305a203
L		 631 { ".3dnow", PROCESSOR_UNKNOWN,
632 CPU_3DNOW_FLAGS },
633 { ".3dnowa", PROCESSOR_UNKNOWN,
634 CPU_3DNOWA_FLAGS },
635 { ".padlock", PROCESSOR_UNKNOWN,
636 CPU_PADLOCK_FLAGS },
637 { ".pacifica", PROCESSOR_UNKNOWN,
638 CPU_SVME_FLAGS },
639 { ".svme", PROCESSOR_UNKNOWN,
640 CPU_SVME_FLAGS },
641 { ".sse4a", PROCESSOR_UNKNOWN,
642 CPU_SSE4A_FLAGS },
643 { ".abm", PROCESSOR_UNKNOWN,
644 CPU_ABM_FLAGS },
645 { ".sse5", PROCESSOR_UNKNOWN,
646 CPU_SSE5_FLAGS },
e413e4e9
AM		 647};
648
29b0f896
AM		 649const pseudo_typeS md_pseudo_table[] =
650{
651#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
652 {"align", s_align_bytes, 0},
653#else
654 {"align", s_align_ptwo, 0},
655#endif
656 {"arch", set_cpu_arch, 0},
657#ifndef I386COFF
658 {"bss", s_bss, 0},
659#endif
660 {"ffloat", float_cons, 'f'},
661 {"dfloat", float_cons, 'd'},
662 {"tfloat", float_cons, 'x'},
663 {"value", cons, 2},
d182319b 664 {"slong", signed_cons, 4},
29b0f896
AM		 665 {"noopt", s_ignore, 0},
666 {"optim", s_ignore, 0},
667 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
668 {"code16", set_code_flag, CODE_16BIT},
669 {"code32", set_code_flag, CODE_32BIT},
670 {"code64", set_code_flag, CODE_64BIT},
671 {"intel_syntax", set_intel_syntax, 1},
672 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 673 {"intel_mnemonic", set_intel_mnemonic, 1},
674 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 675 {"allow_index_reg", set_allow_index_reg, 1},
676 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 677#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
678 {"largecomm", handle_large_common, 0},
07a53e5c 679#else
e3bb37b5 680 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 681 {"loc", dwarf2_directive_loc, 0},
682 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 683#endif
6482c264
NC		 684#ifdef TE_PE
685 {"secrel32", pe_directive_secrel, 0},
686#endif
29b0f896
AM		 687 {0, 0, 0}
688};
689
690/* For interface with expression (). */
691extern char *input_line_pointer;
692
693/* Hash table for instruction mnemonic lookup. */
694static struct hash_control *op_hash;
695
696/* Hash table for register lookup. */
697static struct hash_control *reg_hash;
698\f
252b5132 699void
e3bb37b5 700i386_align_code (fragS *fragP, int count)
252b5132 701{
ce8a8b2f
AM		 702 /* Various efficient no-op patterns for aligning code labels.
703 Note: Don't try to assemble the instructions in the comments.
704 0L and 0w are not legal. */
252b5132
RH		 705 static const char f32_1[] =
706 {0x90}; /* nop */
707 static const char f32_2[] =
ccc9c027 708 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 709 static const char f32_3[] =
710 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
711 static const char f32_4[] =
712 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_5[] =
714 {0x90, /* nop */
715 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
716 static const char f32_6[] =
717 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
718 static const char f32_7[] =
719 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_8[] =
721 {0x90, /* nop */
722 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
723 static const char f32_9[] =
724 {0x89,0xf6, /* movl %esi,%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_10[] =
727 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_11[] =
730 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
731 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
732 static const char f32_12[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
735 static const char f32_13[] =
736 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f32_14[] =
739 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
740 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 741 static const char f16_3[] =
742 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 743 static const char f16_4[] =
744 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_5[] =
746 {0x90, /* nop */
747 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
748 static const char f16_6[] =
749 {0x89,0xf6, /* mov %si,%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_7[] =
752 {0x8d,0x74,0x00, /* lea 0(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char f16_8[] =
755 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
756 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 757 static const char jump_31[] =
758 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
759 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
760 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
761 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 762 static const char *const f32_patt[] = {
763 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 764 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 765 };
766 static const char *const f16_patt[] = {
76bc74dc 767 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 768 };
ccc9c027
L		 769 /* nopl (%[re]ax) */
770 static const char alt_3[] =
771 {0x0f,0x1f,0x00};
772 /* nopl 0(%[re]ax) */
773 static const char alt_4[] =
774 {0x0f,0x1f,0x40,0x00};
775 /* nopl 0(%[re]ax,%[re]ax,1) */
776 static const char alt_5[] =
777 {0x0f,0x1f,0x44,0x00,0x00};
778 /* nopw 0(%[re]ax,%[re]ax,1) */
779 static const char alt_6[] =
780 {0x66,0x0f,0x1f,0x44,0x00,0x00};
781 /* nopl 0L(%[re]ax) */
782 static const char alt_7[] =
783 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
784 /* nopl 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_8[] =
786 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw 0L(%[re]ax,%[re]ax,1) */
788 static const char alt_9[] =
789 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
791 static const char alt_10[] =
792 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
793 /* data16
794 nopw %cs:0L(%[re]ax,%[re]ax,1) */
795 static const char alt_long_11[] =
796 {0x66,
797 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
798 /* data16
799 data16
800 nopw %cs:0L(%[re]ax,%[re]ax,1) */
801 static const char alt_long_12[] =
802 {0x66,
803 0x66,
804 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
805 /* data16
806 data16
807 data16
808 nopw %cs:0L(%[re]ax,%[re]ax,1) */
809 static const char alt_long_13[] =
810 {0x66,
811 0x66,
812 0x66,
813 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
814 /* data16
815 data16
816 data16
817 data16
818 nopw %cs:0L(%[re]ax,%[re]ax,1) */
819 static const char alt_long_14[] =
820 {0x66,
821 0x66,
822 0x66,
823 0x66,
824 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
825 /* data16
826 data16
827 data16
828 data16
829 data16
830 nopw %cs:0L(%[re]ax,%[re]ax,1) */
831 static const char alt_long_15[] =
832 {0x66,
833 0x66,
834 0x66,
835 0x66,
836 0x66,
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopl 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_11[] =
841 {0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
844 nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_short_12[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopw 0(%[re]ax,%[re]ax,1)
849 nopl 0L(%[re]ax) */
850 static const char alt_short_13[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
853 /* nopl 0L(%[re]ax)
854 nopl 0L(%[re]ax) */
855 static const char alt_short_14[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
858 /* nopl 0L(%[re]ax)
859 nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_short_15[] =
861 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
862 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 static const char *const alt_short_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
866 alt_short_14, alt_short_15
867 };
868 static const char *const alt_long_patt[] = {
869 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
870 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
871 alt_long_14, alt_long_15
872 };
252b5132 873
76bc74dc
L		 874 /* Only align for at least a positive non-zero boundary. */
875 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 876 return;
3e73aa7c 877
ccc9c027
L		 878 /* We need to decide which NOP sequence to use for 32bit and
879 64bit. When -mtune= is used:
4eed87de 880
76bc74dc
L		 881 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
882 PROCESSOR_GENERIC32, f32_patt will be used.
883 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
884 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
885 alt_long_patt will be used.
886 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
887 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 888
76bc74dc
L		 889 When -mtune= isn't used, alt_long_patt will be used if
890 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
891 be used.
ccc9c027
L		 892
893 When -march= or .arch is used, we can't use anything beyond
894 cpu_arch_isa_flags. */
895
896 if (flag_code == CODE_16BIT)
897 {
ccc9c027 898 if (count > 8)
33fef721 899 {
76bc74dc
L		 900 memcpy (fragP->fr_literal + fragP->fr_fix,
901 jump_31, count);
902 /* Adjust jump offset. */
903 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 904 }
76bc74dc
L		 905 else
906 memcpy (fragP->fr_literal + fragP->fr_fix,
907 f16_patt[count - 1], count);
252b5132 908 }
33fef721 909 else
ccc9c027
L		 910 {
911 const char *const *patt = NULL;
912
913 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
914 {
915 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
916 switch (cpu_arch_tune)
917 {
918 case PROCESSOR_UNKNOWN:
919 /* We use cpu_arch_isa_flags to check if we SHOULD
920 optimize for Cpu686. */
40fb9820 921 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 922 patt = alt_long_patt;
ccc9c027
L		 923 else
924 patt = f32_patt;
925 break;
ccc9c027
L		 926 case PROCESSOR_PENTIUMPRO:
927 case PROCESSOR_PENTIUM4:
928 case PROCESSOR_NOCONA:
ef05d495 929 case PROCESSOR_CORE:
76bc74dc
L		 930 case PROCESSOR_CORE2:
931 case PROCESSOR_GENERIC64:
932 patt = alt_long_patt;
933 break;
ccc9c027
L		 934 case PROCESSOR_K6:
935 case PROCESSOR_ATHLON:
936 case PROCESSOR_K8:
4eed87de 937 case PROCESSOR_AMDFAM10:
ccc9c027
L		 938 patt = alt_short_patt;
939 break;
76bc74dc 940 case PROCESSOR_I386:
ccc9c027
L		 941 case PROCESSOR_I486:
942 case PROCESSOR_PENTIUM:
943 case PROCESSOR_GENERIC32:
944 patt = f32_patt;
945 break;
4eed87de 946 }
ccc9c027
L		 947 }
948 else
949 {
950 switch (cpu_arch_tune)
951 {
952 case PROCESSOR_UNKNOWN:
953 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
954 PROCESSOR_UNKNOWN. */
955 abort ();
956 break;
957
76bc74dc 958 case PROCESSOR_I386:
ccc9c027
L		 959 case PROCESSOR_I486:
960 case PROCESSOR_PENTIUM:
ccc9c027
L		 961 case PROCESSOR_K6:
962 case PROCESSOR_ATHLON:
963 case PROCESSOR_K8:
4eed87de 964 case PROCESSOR_AMDFAM10:
ccc9c027
L		 965 case PROCESSOR_GENERIC32:
966 /* We use cpu_arch_isa_flags to check if we CAN optimize
967 for Cpu686. */
40fb9820 968 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 969 patt = alt_short_patt;
970 else
971 patt = f32_patt;
972 break;
76bc74dc
L		 973 case PROCESSOR_PENTIUMPRO:
974 case PROCESSOR_PENTIUM4:
975 case PROCESSOR_NOCONA:
976 case PROCESSOR_CORE:
ef05d495 977 case PROCESSOR_CORE2:
40fb9820 978 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 979 patt = alt_long_patt;
980 else
981 patt = f32_patt;
982 break;
983 case PROCESSOR_GENERIC64:
76bc74dc 984 patt = alt_long_patt;
ccc9c027 985 break;
4eed87de 986 }
ccc9c027
L		 987 }
988
76bc74dc
L		 989 if (patt == f32_patt)
990 {
991 /* If the padding is less than 15 bytes, we use the normal
992 ones. Otherwise, we use a jump instruction and adjust
993 its offset. */
994 if (count < 15)
995 memcpy (fragP->fr_literal + fragP->fr_fix,
996 patt[count - 1], count);
997 else
998 {
999 memcpy (fragP->fr_literal + fragP->fr_fix,
1000 jump_31, count);
1001 /* Adjust jump offset. */
1002 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1003 }
1004 }
1005 else
1006 {
1007 /* Maximum length of an instruction is 15 byte. If the
1008 padding is greater than 15 bytes and we don't use jump,
1009 we have to break it into smaller pieces. */
1010 int padding = count;
1011 while (padding > 15)
1012 {
1013 padding -= 15;
1014 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1015 patt [14], 15);
1016 }
1017
1018 if (padding)
1019 memcpy (fragP->fr_literal + fragP->fr_fix,
1020 patt [padding - 1], padding);
1021 }
ccc9c027 1022 }
33fef721 1023 fragP->fr_var = count;
252b5132
RH		 1024}
1025
c6fb90c8 1026static INLINE int
0dfbf9d7 1027operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1028{
0dfbf9d7 1029 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1030 {
1031 case 3:
0dfbf9d7 1032 if (x->array[2])
c6fb90c8
L		 1033 return 0;
1034 case 2:
0dfbf9d7 1035 if (x->array[1])
c6fb90c8
L		 1036 return 0;
1037 case 1:
0dfbf9d7 1038 return !x->array[0];
c6fb90c8
L		 1039 default:
1040 abort ();
1041 }
40fb9820
L		 1042}
1043
c6fb90c8 1044static INLINE void
0dfbf9d7 1045operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1046{
0dfbf9d7 1047 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1048 {
1049 case 3:
0dfbf9d7 1050 x->array[2] = v;
c6fb90c8 1051 case 2:
0dfbf9d7 1052 x->array[1] = v;
c6fb90c8 1053 case 1:
0dfbf9d7 1054 x->array[0] = v;
c6fb90c8
L		 1055 break;
1056 default:
1057 abort ();
1058 }
1059}
40fb9820 1060
c6fb90c8 1061static INLINE int
0dfbf9d7
L		 1062operand_type_equal (const union i386_operand_type *x,
1063 const union i386_operand_type *y)
c6fb90c8 1064{
0dfbf9d7 1065 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1066 {
1067 case 3:
0dfbf9d7 1068 if (x->array[2] != y->array[2])
c6fb90c8
L		 1069 return 0;
1070 case 2:
0dfbf9d7 1071 if (x->array[1] != y->array[1])
c6fb90c8
L		 1072 return 0;
1073 case 1:
0dfbf9d7 1074 return x->array[0] == y->array[0];
c6fb90c8
L		 1075 break;
1076 default:
1077 abort ();
1078 }
1079}
40fb9820 1080
0dfbf9d7
L		 1081static INLINE int
1082cpu_flags_all_zero (const union i386_cpu_flags *x)
1083{
1084 switch (ARRAY_SIZE(x->array))
1085 {
1086 case 3:
1087 if (x->array[2])
1088 return 0;
1089 case 2:
1090 if (x->array[1])
1091 return 0;
1092 case 1:
1093 return !x->array[0];
1094 default:
1095 abort ();
1096 }
1097}
1098
1099static INLINE void
1100cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1101{
1102 switch (ARRAY_SIZE(x->array))
1103 {
1104 case 3:
1105 x->array[2] = v;
1106 case 2:
1107 x->array[1] = v;
1108 case 1:
1109 x->array[0] = v;
1110 break;
1111 default:
1112 abort ();
1113 }
1114}
1115
1116static INLINE int
1117cpu_flags_equal (const union i386_cpu_flags *x,
1118 const union i386_cpu_flags *y)
1119{
1120 switch (ARRAY_SIZE(x->array))
1121 {
1122 case 3:
1123 if (x->array[2] != y->array[2])
1124 return 0;
1125 case 2:
1126 if (x->array[1] != y->array[1])
1127 return 0;
1128 case 1:
1129 return x->array[0] == y->array[0];
1130 break;
1131 default:
1132 abort ();
1133 }
1134}
c6fb90c8
L		 1135
1136static INLINE int
1137cpu_flags_check_cpu64 (i386_cpu_flags f)
1138{
1139 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1140 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1141}
1142
c6fb90c8
L		 1143static INLINE i386_cpu_flags
1144cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1145{
c6fb90c8
L		 1146 switch (ARRAY_SIZE (x.array))
1147 {
1148 case 3:
1149 x.array [2] &= y.array [2];
1150 case 2:
1151 x.array [1] &= y.array [1];
1152 case 1:
1153 x.array [0] &= y.array [0];
1154 break;
1155 default:
1156 abort ();
1157 }
1158 return x;
1159}
40fb9820 1160
c6fb90c8
L		 1161static INLINE i386_cpu_flags
1162cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1163{
c6fb90c8 1164 switch (ARRAY_SIZE (x.array))
40fb9820 1165 {
c6fb90c8
L		 1166 case 3:
1167 x.array [2] |= y.array [2];
1168 case 2:
1169 x.array [1] |= y.array [1];
1170 case 1:
1171 x.array [0] |= y.array [0];
40fb9820
L		 1172 break;
1173 default:
1174 abort ();
1175 }
40fb9820
L		 1176 return x;
1177}
1178
3629bb00
L		 1179/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1180 1 if compatible with arch, 0 if there is no match. */
1181
40fb9820
L		 1182static int
1183cpu_flags_match (i386_cpu_flags x)
1184{
3629bb00 1185 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1186
1187 x.bitfield.cpu64 = 0;
1188 x.bitfield.cpuno64 = 0;
1189
0dfbf9d7 1190 if (cpu_flags_all_zero (&x))
3629bb00
L		 1191 overlap |= 1;
1192 else
1193 {
1194 i386_cpu_flags cpu = cpu_arch_flags;
1195
1196 cpu.bitfield.cpu64 = 0;
1197 cpu.bitfield.cpuno64 = 0;
1198 cpu = cpu_flags_and (x, cpu);
0dfbf9d7 1199 overlap |= cpu_flags_all_zero (&cpu) ? 0 : 1;
3629bb00
L		 1200 }
1201 return overlap;
40fb9820
L		 1202}
1203
c6fb90c8
L		 1204static INLINE i386_operand_type
1205operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1206{
c6fb90c8
L		 1207 switch (ARRAY_SIZE (x.array))
1208 {
1209 case 3:
1210 x.array [2] &= y.array [2];
1211 case 2:
1212 x.array [1] &= y.array [1];
1213 case 1:
1214 x.array [0] &= y.array [0];
1215 break;
1216 default:
1217 abort ();
1218 }
1219 return x;
40fb9820
L		 1220}
1221
c6fb90c8
L		 1222static INLINE i386_operand_type
1223operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1224{
c6fb90c8 1225 switch (ARRAY_SIZE (x.array))
40fb9820 1226 {
c6fb90c8
L		 1227 case 3:
1228 x.array [2] |= y.array [2];
1229 case 2:
1230 x.array [1] |= y.array [1];
1231 case 1:
1232 x.array [0] |= y.array [0];
40fb9820
L		 1233 break;
1234 default:
1235 abort ();
1236 }
c6fb90c8
L		 1237 return x;
1238}
40fb9820 1239
c6fb90c8
L		 1240static INLINE i386_operand_type
1241operand_type_xor (i386_operand_type x, i386_operand_type y)
1242{
1243 switch (ARRAY_SIZE (x.array))
1244 {
1245 case 3:
1246 x.array [2] ^= y.array [2];
1247 case 2:
1248 x.array [1] ^= y.array [1];
1249 case 1:
1250 x.array [0] ^= y.array [0];
1251 break;
1252 default:
1253 abort ();
1254 }
40fb9820
L		 1255 return x;
1256}
1257
1258static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1259static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1260static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1261static const i386_operand_type inoutportreg
1262 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1263static const i386_operand_type reg16_inoutportreg
1264 = OPERAND_TYPE_REG16_INOUTPORTREG;
1265static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1266static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1267static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1268static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1269static const i386_operand_type anydisp
1270 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1271static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1272static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1273static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1274static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1275static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1276static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1277static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1278static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1279static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1280static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1281
1282enum operand_type
1283{
1284 reg,
40fb9820
L		 1285 imm,
1286 disp,
1287 anymem
1288};
1289
c6fb90c8 1290static INLINE int
40fb9820
L		 1291operand_type_check (i386_operand_type t, enum operand_type c)
1292{
1293 switch (c)
1294 {
1295 case reg:
1296 return (t.bitfield.reg8
1297 || t.bitfield.reg16
1298 || t.bitfield.reg32
1299 || t.bitfield.reg64);
1300
40fb9820
L		 1301 case imm:
1302 return (t.bitfield.imm8
1303 || t.bitfield.imm8s
1304 || t.bitfield.imm16
1305 || t.bitfield.imm32
1306 || t.bitfield.imm32s
1307 || t.bitfield.imm64);
1308
1309 case disp:
1310 return (t.bitfield.disp8
1311 || t.bitfield.disp16
1312 || t.bitfield.disp32
1313 || t.bitfield.disp32s
1314 || t.bitfield.disp64);
1315
1316 case anymem:
1317 return (t.bitfield.disp8
1318 || t.bitfield.disp16
1319 || t.bitfield.disp32
1320 || t.bitfield.disp32s
1321 || t.bitfield.disp64
1322 || t.bitfield.baseindex);
1323
1324 default:
1325 abort ();
1326 }
1327}
1328
5c07affc
L		 1329/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1330 operand J for instruction template T. */
1331
1332static INLINE int
1333match_reg_size (const template *t, unsigned int j)
1334{
1335 return !((i.types[j].bitfield.byte
1336 && !t->operand_types[j].bitfield.byte)
1337 || (i.types[j].bitfield.word
1338 && !t->operand_types[j].bitfield.word)
1339 || (i.types[j].bitfield.dword
1340 && !t->operand_types[j].bitfield.dword)
1341 || (i.types[j].bitfield.qword
1342 && !t->operand_types[j].bitfield.qword));
1343}
1344
1345/* Return 1 if there is no conflict in any size on operand J for
1346 instruction template T. */
1347
1348static INLINE int
1349match_mem_size (const template *t, unsigned int j)
1350{
1351 return (match_reg_size (t, j)
1352 && !((i.types[j].bitfield.unspecified
1353 && !t->operand_types[j].bitfield.unspecified)
1354 || (i.types[j].bitfield.fword
1355 && !t->operand_types[j].bitfield.fword)
1356 || (i.types[j].bitfield.tbyte
1357 && !t->operand_types[j].bitfield.tbyte)
1358 || (i.types[j].bitfield.xmmword
1359 && !t->operand_types[j].bitfield.xmmword)));
1360}
1361
1362/* Return 1 if there is no size conflict on any operands for
1363 instruction template T. */
1364
1365static INLINE int
1366operand_size_match (const template *t)
1367{
1368 unsigned int j;
1369 int match = 1;
1370
1371 /* Don't check jump instructions. */
1372 if (t->opcode_modifier.jump
1373 || t->opcode_modifier.jumpbyte
1374 || t->opcode_modifier.jumpdword
1375 || t->opcode_modifier.jumpintersegment)
1376 return match;
1377
1378 /* Check memory and accumulator operand size. */
1379 for (j = 0; j < i.operands; j++)
1380 {
1381 if (t->operand_types[j].bitfield.anysize)
1382 continue;
1383
1384 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1385 {
1386 match = 0;
1387 break;
1388 }
1389
1390 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1391 {
1392 match = 0;
1393 break;
1394 }
1395 }
1396
1397 if (match
1398 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1399 return match;
1400
1401 /* Check reverse. */
1402 assert (i.operands == 2);
1403
1404 match = 1;
1405 for (j = 0; j < 2; j++)
1406 {
1407 if (t->operand_types[j].bitfield.acc
1408 && !match_reg_size (t, j ? 0 : 1))
1409 {
1410 match = 0;
1411 break;
1412 }
1413
1414 if (i.types[j].bitfield.mem
1415 && !match_mem_size (t, j ? 0 : 1))
1416 {
1417 match = 0;
1418 break;
1419 }
1420 }
1421
1422 return match;
1423}
1424
c6fb90c8 1425static INLINE int
40fb9820
L		 1426operand_type_match (i386_operand_type overlap,
1427 i386_operand_type given)
1428{
1429 i386_operand_type temp = overlap;
1430
1431 temp.bitfield.jumpabsolute = 0;
7d5e4556 1432 temp.bitfield.unspecified = 0;
5c07affc
L		 1433 temp.bitfield.byte = 0;
1434 temp.bitfield.word = 0;
1435 temp.bitfield.dword = 0;
1436 temp.bitfield.fword = 0;
1437 temp.bitfield.qword = 0;
1438 temp.bitfield.tbyte = 0;
1439 temp.bitfield.xmmword = 0;
0dfbf9d7 1440 if (operand_type_all_zero (&temp))
40fb9820
L		 1441 return 0;
1442
1443 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1444 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1445}
1446
7d5e4556 1447/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1448 unless the expected operand type register overlap is null.
1449 Note that Acc in a template matches every size of reg. */
1450
c6fb90c8 1451static INLINE int
40fb9820
L		 1452operand_type_register_match (i386_operand_type m0,
1453 i386_operand_type g0,
1454 i386_operand_type t0,
1455 i386_operand_type m1,
1456 i386_operand_type g1,
1457 i386_operand_type t1)
1458{
1459 if (!operand_type_check (g0, reg))
1460 return 1;
1461
1462 if (!operand_type_check (g1, reg))
1463 return 1;
1464
1465 if (g0.bitfield.reg8 == g1.bitfield.reg8
1466 && g0.bitfield.reg16 == g1.bitfield.reg16
1467 && g0.bitfield.reg32 == g1.bitfield.reg32
1468 && g0.bitfield.reg64 == g1.bitfield.reg64)
1469 return 1;
1470
1471 if (m0.bitfield.acc)
1472 {
1473 t0.bitfield.reg8 = 1;
1474 t0.bitfield.reg16 = 1;
1475 t0.bitfield.reg32 = 1;
1476 t0.bitfield.reg64 = 1;
1477 }
1478
1479 if (m1.bitfield.acc)
1480 {
1481 t1.bitfield.reg8 = 1;
1482 t1.bitfield.reg16 = 1;
1483 t1.bitfield.reg32 = 1;
1484 t1.bitfield.reg64 = 1;
1485 }
1486
1487 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1488 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1489 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1490 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1491}
1492
252b5132 1493static INLINE unsigned int
40fb9820 1494mode_from_disp_size (i386_operand_type t)
252b5132 1495{
40fb9820
L		 1496 if (t.bitfield.disp8)
1497 return 1;
1498 else if (t.bitfield.disp16
1499 || t.bitfield.disp32
1500 || t.bitfield.disp32s)
1501 return 2;
1502 else
1503 return 0;
252b5132
RH		 1504}
1505
1506static INLINE int
e3bb37b5 1507fits_in_signed_byte (offsetT num)
252b5132
RH		 1508{
1509 return (num >= -128) && (num <= 127);
47926f60 1510}
252b5132
RH		 1511
1512static INLINE int
e3bb37b5 1513fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1514{
1515 return (num & 0xff) == num;
47926f60 1516}
252b5132
RH		 1517
1518static INLINE int
e3bb37b5 1519fits_in_unsigned_word (offsetT num)
252b5132
RH		 1520{
1521 return (num & 0xffff) == num;
47926f60 1522}
252b5132
RH		 1523
1524static INLINE int
e3bb37b5 1525fits_in_signed_word (offsetT num)
252b5132
RH		 1526{
1527 return (-32768 <= num) && (num <= 32767);
47926f60 1528}
2a962e6d 1529
3e73aa7c 1530static INLINE int
e3bb37b5 1531fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1532{
1533#ifndef BFD64
1534 return 1;
1535#else
1536 return (!(((offsetT) -1 << 31) & num)
1537 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1538#endif
1539} /* fits_in_signed_long() */
2a962e6d 1540
3e73aa7c 1541static INLINE int
e3bb37b5 1542fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1543{
1544#ifndef BFD64
1545 return 1;
1546#else
1547 return (num & (((offsetT) 2 << 31) - 1)) == num;
1548#endif
1549} /* fits_in_unsigned_long() */
252b5132 1550
40fb9820 1551static i386_operand_type
e3bb37b5 1552smallest_imm_type (offsetT num)
252b5132 1553{
40fb9820
L		 1554 i386_operand_type t;
1555
0dfbf9d7 1556 operand_type_set (&t, 0);
40fb9820
L		 1557 t.bitfield.imm64 = 1;
1558
1559 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1560 {
1561 /* This code is disabled on the 486 because all the Imm1 forms
1562 in the opcode table are slower on the i486. They're the
1563 versions with the implicitly specified single-position
1564 displacement, which has another syntax if you really want to
1565 use that form. */
40fb9820
L		 1566 t.bitfield.imm1 = 1;
1567 t.bitfield.imm8 = 1;
1568 t.bitfield.imm8s = 1;
1569 t.bitfield.imm16 = 1;
1570 t.bitfield.imm32 = 1;
1571 t.bitfield.imm32s = 1;
1572 }
1573 else if (fits_in_signed_byte (num))
1574 {
1575 t.bitfield.imm8 = 1;
1576 t.bitfield.imm8s = 1;
1577 t.bitfield.imm16 = 1;
1578 t.bitfield.imm32 = 1;
1579 t.bitfield.imm32s = 1;
1580 }
1581 else if (fits_in_unsigned_byte (num))
1582 {
1583 t.bitfield.imm8 = 1;
1584 t.bitfield.imm16 = 1;
1585 t.bitfield.imm32 = 1;
1586 t.bitfield.imm32s = 1;
1587 }
1588 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1589 {
1590 t.bitfield.imm16 = 1;
1591 t.bitfield.imm32 = 1;
1592 t.bitfield.imm32s = 1;
1593 }
1594 else if (fits_in_signed_long (num))
1595 {
1596 t.bitfield.imm32 = 1;
1597 t.bitfield.imm32s = 1;
1598 }
1599 else if (fits_in_unsigned_long (num))
1600 t.bitfield.imm32 = 1;
1601
1602 return t;
47926f60 1603}
252b5132 1604
847f7ad4 1605static offsetT
e3bb37b5 1606offset_in_range (offsetT val, int size)
847f7ad4 1607{
508866be 1608 addressT mask;
ba2adb93 1609
847f7ad4
AM		 1610 switch (size)
1611 {
508866be
L		 1612 case 1: mask = ((addressT) 1 << 8) - 1; break;
1613 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1614 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1615#ifdef BFD64
1616 case 8: mask = ((addressT) 2 << 63) - 1; break;
1617#endif
47926f60 1618 default: abort ();
847f7ad4
AM		 1619 }
1620
ba2adb93 1621 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1622 if (!use_rela_relocations)
1623 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1624 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1625
47926f60 1626 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1627 {
1628 char buf1[40], buf2[40];
1629
1630 sprint_value (buf1, val);
1631 sprint_value (buf2, val & mask);
1632 as_warn (_("%s shortened to %s"), buf1, buf2);
1633 }
1634 return val & mask;
1635}
1636
252b5132
RH		 1637/* Returns 0 if attempting to add a prefix where one from the same
1638 class already exists, 1 if non rep/repne added, 2 if rep/repne
1639 added. */
1640static int
e3bb37b5 1641add_prefix (unsigned int prefix)
252b5132
RH		 1642{
1643 int ret = 1;
b1905489 1644 unsigned int q;
252b5132 1645
29b0f896
AM		 1646 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1647 && flag_code == CODE_64BIT)
b1905489 1648 {
161a04f6
L		 1649 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1650 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1651 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1652 ret = 0;
1653 q = REX_PREFIX;
1654 }
3e73aa7c 1655 else
b1905489
JB		 1656 {
1657 switch (prefix)
1658 {
1659 default:
1660 abort ();
1661
1662 case CS_PREFIX_OPCODE:
1663 case DS_PREFIX_OPCODE:
1664 case ES_PREFIX_OPCODE:
1665 case FS_PREFIX_OPCODE:
1666 case GS_PREFIX_OPCODE:
1667 case SS_PREFIX_OPCODE:
1668 q = SEG_PREFIX;
1669 break;
1670
1671 case REPNE_PREFIX_OPCODE:
1672 case REPE_PREFIX_OPCODE:
1673 ret = 2;
1674 /* fall thru */
1675 case LOCK_PREFIX_OPCODE:
1676 q = LOCKREP_PREFIX;
1677 break;
1678
1679 case FWAIT_OPCODE:
1680 q = WAIT_PREFIX;
1681 break;
1682
1683 case ADDR_PREFIX_OPCODE:
1684 q = ADDR_PREFIX;
1685 break;
1686
1687 case DATA_PREFIX_OPCODE:
1688 q = DATA_PREFIX;
1689 break;
1690 }
1691 if (i.prefix[q] != 0)
1692 ret = 0;
1693 }
252b5132 1694
b1905489 1695 if (ret)
252b5132 1696 {
b1905489
JB		 1697 if (!i.prefix[q])
1698 ++i.prefixes;
1699 i.prefix[q] |= prefix;
252b5132 1700 }
b1905489
JB		 1701 else
1702 as_bad (_("same type of prefix used twice"));
252b5132 1703
252b5132
RH		 1704 return ret;
1705}
1706
1707static void
e3bb37b5 1708set_code_flag (int value)
eecb386c 1709{
3e73aa7c 1710 flag_code = value;
40fb9820
L		 1711 if (flag_code == CODE_64BIT)
1712 {
1713 cpu_arch_flags.bitfield.cpu64 = 1;
1714 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1715 }
1716 else
1717 {
1718 cpu_arch_flags.bitfield.cpu64 = 0;
1719 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1720 }
1721 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1722 {
1723 as_bad (_("64bit mode not supported on this CPU."));
1724 }
40fb9820 1725 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1726 {
1727 as_bad (_("32bit mode not supported on this CPU."));
1728 }
eecb386c
AM		 1729 stackop_size = '\0';
1730}
1731
1732static void
e3bb37b5 1733set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1734{
3e73aa7c 1735 flag_code = new_code_flag;
40fb9820
L		 1736 if (flag_code != CODE_16BIT)
1737 abort ();
1738 cpu_arch_flags.bitfield.cpu64 = 0;
1739 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1740 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1741}
1742
1743static void
e3bb37b5 1744set_intel_syntax (int syntax_flag)
252b5132
RH		 1745{
1746 /* Find out if register prefixing is specified. */
1747 int ask_naked_reg = 0;
1748
1749 SKIP_WHITESPACE ();
29b0f896 1750 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1751 {
1752 char *string = input_line_pointer;
1753 int e = get_symbol_end ();
1754
47926f60 1755 if (strcmp (string, "prefix") == 0)
252b5132 1756 ask_naked_reg = 1;
47926f60 1757 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1758 ask_naked_reg = -1;
1759 else
d0b47220 1760 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1761 *input_line_pointer = e;
1762 }
1763 demand_empty_rest_of_line ();
c3332e24 1764
252b5132
RH		 1765 intel_syntax = syntax_flag;
1766
1767 if (ask_naked_reg == 0)
f86103b7
AM		 1768 allow_naked_reg = (intel_syntax
1769 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1770 else
1771 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1772
e4a3b5a4 1773 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1774 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1775 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1776}
1777
1efbbeb4
L		 1778static void
1779set_intel_mnemonic (int mnemonic_flag)
1780{
e1d4d893 1781 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1782}
1783
db51cc60
L		 1784static void
1785set_allow_index_reg (int flag)
1786{
1787 allow_index_reg = flag;
1788}
1789
e413e4e9 1790static void
e3bb37b5 1791set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1792{
47926f60 1793 SKIP_WHITESPACE ();
e413e4e9 1794
29b0f896 1795 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1796 {
1797 char *string = input_line_pointer;
1798 int e = get_symbol_end ();
9103f4f4 1799 unsigned int i;
40fb9820 1800 i386_cpu_flags flags;
e413e4e9 1801
9103f4f4 1802 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1803 {
1804 if (strcmp (string, cpu_arch[i].name) == 0)
1805 {
5c6af06e
JB		 1806 if (*string != '.')
1807 {
1808 cpu_arch_name = cpu_arch[i].name;
1809 cpu_sub_arch_name = NULL;
40fb9820
L		 1810 cpu_arch_flags = cpu_arch[i].flags;
1811 if (flag_code == CODE_64BIT)
1812 {
1813 cpu_arch_flags.bitfield.cpu64 = 1;
1814 cpu_arch_flags.bitfield.cpuno64 = 0;
1815 }
1816 else
1817 {
1818 cpu_arch_flags.bitfield.cpu64 = 0;
1819 cpu_arch_flags.bitfield.cpuno64 = 1;
1820 }
ccc9c027 1821 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1822 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1823 if (!cpu_arch_tune_set)
1824 {
1825 cpu_arch_tune = cpu_arch_isa;
1826 cpu_arch_tune_flags = cpu_arch_isa_flags;
1827 }
5c6af06e
JB		 1828 break;
1829 }
40fb9820 1830
c6fb90c8
L		 1831 flags = cpu_flags_or (cpu_arch_flags,
1832 cpu_arch[i].flags);
0dfbf9d7 1833 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1834 {
6305a203
L		 1835 if (cpu_sub_arch_name)
1836 {
1837 char *name = cpu_sub_arch_name;
1838 cpu_sub_arch_name = concat (name,
1839 cpu_arch[i].name,
1bf57e9f 1840 (const char *) NULL);
6305a203
L		 1841 free (name);
1842 }
1843 else
1844 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1845 cpu_arch_flags = flags;
5c6af06e
JB		 1846 }
1847 *input_line_pointer = e;
1848 demand_empty_rest_of_line ();
1849 return;
e413e4e9
AM		 1850 }
1851 }
9103f4f4 1852 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1853 as_bad (_("no such architecture: `%s'"), string);
1854
1855 *input_line_pointer = e;
1856 }
1857 else
1858 as_bad (_("missing cpu architecture"));
1859
fddf5b5b
AM		 1860 no_cond_jump_promotion = 0;
1861 if (*input_line_pointer == ','
29b0f896 1862 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1863 {
1864 char *string = ++input_line_pointer;
1865 int e = get_symbol_end ();
1866
1867 if (strcmp (string, "nojumps") == 0)
1868 no_cond_jump_promotion = 1;
1869 else if (strcmp (string, "jumps") == 0)
1870 ;
1871 else
1872 as_bad (_("no such architecture modifier: `%s'"), string);
1873
1874 *input_line_pointer = e;
1875 }
1876
e413e4e9
AM		 1877 demand_empty_rest_of_line ();
1878}
1879
b9d79e03
JH		 1880unsigned long
1881i386_mach ()
1882{
1883 if (!strcmp (default_arch, "x86_64"))
1884 return bfd_mach_x86_64;
1885 else if (!strcmp (default_arch, "i386"))
1886 return bfd_mach_i386_i386;
1887 else
1888 as_fatal (_("Unknown architecture"));
1889}
b9d79e03 1890\f
252b5132
RH		 1891void
1892md_begin ()
1893{
1894 const char *hash_err;
1895
47926f60 1896 /* Initialize op_hash hash table. */
252b5132
RH		 1897 op_hash = hash_new ();
1898
1899 {
29b0f896
AM		 1900 const template *optab;
1901 templates *core_optab;
252b5132 1902
47926f60
KH		 1903 /* Setup for loop. */
1904 optab = i386_optab;
252b5132
RH		 1905 core_optab = (templates *) xmalloc (sizeof (templates));
1906 core_optab->start = optab;
1907
1908 while (1)
1909 {
1910 ++optab;
1911 if (optab->name == NULL
1912 || strcmp (optab->name, (optab - 1)->name) != 0)
1913 {
1914 /* different name --> ship out current template list;
47926f60 1915 add to hash table; & begin anew. */
252b5132
RH		 1916 core_optab->end = optab;
1917 hash_err = hash_insert (op_hash,
1918 (optab - 1)->name,
1919 (PTR) core_optab);
1920 if (hash_err)
1921 {
252b5132
RH		 1922 as_fatal (_("Internal Error: Can't hash %s: %s"),
1923 (optab - 1)->name,
1924 hash_err);
1925 }
1926 if (optab->name == NULL)
1927 break;
1928 core_optab = (templates *) xmalloc (sizeof (templates));
1929 core_optab->start = optab;
1930 }
1931 }
1932 }
1933
47926f60 1934 /* Initialize reg_hash hash table. */
252b5132
RH		 1935 reg_hash = hash_new ();
1936 {
29b0f896 1937 const reg_entry *regtab;
c3fe08fa 1938 unsigned int regtab_size = i386_regtab_size;
252b5132 1939
c3fe08fa 1940 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1941 {
1942 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1943 if (hash_err)
3e73aa7c
JH		 1944 as_fatal (_("Internal Error: Can't hash %s: %s"),
1945 regtab->reg_name,
1946 hash_err);
252b5132
RH		 1947 }
1948 }
1949
47926f60 1950 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1951 {
29b0f896
AM		 1952 int c;
1953 char *p;
252b5132
RH		 1954
1955 for (c = 0; c < 256; c++)
1956 {
3882b010 1957 if (ISDIGIT (c))
252b5132
RH		 1958 {
1959 digit_chars[c] = c;
1960 mnemonic_chars[c] = c;
1961 register_chars[c] = c;
1962 operand_chars[c] = c;
1963 }
3882b010 1964 else if (ISLOWER (c))
252b5132
RH		 1965 {
1966 mnemonic_chars[c] = c;
1967 register_chars[c] = c;
1968 operand_chars[c] = c;
1969 }
3882b010 1970 else if (ISUPPER (c))
252b5132 1971 {
3882b010 1972 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1973 register_chars[c] = mnemonic_chars[c];
1974 operand_chars[c] = c;
1975 }
1976
3882b010 1977 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1978 identifier_chars[c] = c;
1979 else if (c >= 128)
1980 {
1981 identifier_chars[c] = c;
1982 operand_chars[c] = c;
1983 }
1984 }
1985
1986#ifdef LEX_AT
1987 identifier_chars['@'] = '@';
32137342
NC		 1988#endif
1989#ifdef LEX_QM
1990 identifier_chars['?'] = '?';
1991 operand_chars['?'] = '?';
252b5132 1992#endif
252b5132 1993 digit_chars['-'] = '-';
791fe849 1994 mnemonic_chars['-'] = '-';
0003779b 1995 mnemonic_chars['.'] = '.';
252b5132
RH		 1996 identifier_chars['_'] = '_';
1997 identifier_chars['.'] = '.';
1998
1999 for (p = operand_special_chars; *p != '\0'; p++)
2000 operand_chars[(unsigned char) *p] = *p;
2001 }
2002
2003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2004 if (IS_ELF)
252b5132
RH		 2005 {
2006 record_alignment (text_section, 2);
2007 record_alignment (data_section, 2);
2008 record_alignment (bss_section, 2);
2009 }
2010#endif
a4447b93
RH		 2011
2012 if (flag_code == CODE_64BIT)
2013 {
2014 x86_dwarf2_return_column = 16;
2015 x86_cie_data_alignment = -8;
2016 }
2017 else
2018 {
2019 x86_dwarf2_return_column = 8;
2020 x86_cie_data_alignment = -4;
2021 }
252b5132
RH		 2022}
2023
2024void
e3bb37b5 2025i386_print_statistics (FILE *file)
252b5132
RH		 2026{
2027 hash_print_statistics (file, "i386 opcode", op_hash);
2028 hash_print_statistics (file, "i386 register", reg_hash);
2029}
2030\f
252b5132
RH		 2031#ifdef DEBUG386
2032
ce8a8b2f 2033/* Debugging routines for md_assemble. */
e3bb37b5 2034static void pte (template *);
40fb9820 2035static void pt (i386_operand_type);
e3bb37b5
L		 2036static void pe (expressionS *);
2037static void ps (symbolS *);
252b5132
RH		 2038
2039static void
e3bb37b5 2040pi (char *line, i386_insn *x)
252b5132 2041{
09f131f2 2042 unsigned int i;
252b5132
RH		 2043
2044 fprintf (stdout, "%s: template ", line);
2045 pte (&x->tm);
09f131f2
JH		 2046 fprintf (stdout, " address: base %s index %s scale %x\n",
2047 x->base_reg ? x->base_reg->reg_name : "none",
2048 x->index_reg ? x->index_reg->reg_name : "none",
2049 x->log2_scale_factor);
2050 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2051 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2052 fprintf (stdout, " sib: base %x index %x scale %x\n",
2053 x->sib.base, x->sib.index, x->sib.scale);
2054 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2055 (x->rex & REX_W) != 0,
2056 (x->rex & REX_R) != 0,
2057 (x->rex & REX_X) != 0,
2058 (x->rex & REX_B) != 0);
85f10a01
MM		 2059 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2060 x->drex.reg, x->drex.rex);
252b5132
RH		 2061 for (i = 0; i < x->operands; i++)
2062 {
2063 fprintf (stdout, " #%d: ", i + 1);
2064 pt (x->types[i]);
2065 fprintf (stdout, "\n");
40fb9820
L		 2066 if (x->types[i].bitfield.reg8
2067 || x->types[i].bitfield.reg16
2068 || x->types[i].bitfield.reg32
2069 || x->types[i].bitfield.reg64
2070 || x->types[i].bitfield.regmmx
2071 || x->types[i].bitfield.regxmm
2072 || x->types[i].bitfield.sreg2
2073 || x->types[i].bitfield.sreg3
2074 || x->types[i].bitfield.control
2075 || x->types[i].bitfield.debug
2076 || x->types[i].bitfield.test)
520dc8e8 2077 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2078 if (operand_type_check (x->types[i], imm))
520dc8e8 2079 pe (x->op[i].imms);
40fb9820 2080 if (operand_type_check (x->types[i], disp))
520dc8e8 2081 pe (x->op[i].disps);
252b5132
RH		 2082 }
2083}
2084
2085static void
e3bb37b5 2086pte (template *t)
252b5132 2087{
09f131f2 2088 unsigned int i;
252b5132 2089 fprintf (stdout, " %d operands ", t->operands);
47926f60 2090 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2091 if (t->extension_opcode != None)
2092 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2093 if (t->opcode_modifier.d)
252b5132 2094 fprintf (stdout, "D");
40fb9820 2095 if (t->opcode_modifier.w)
252b5132
RH		 2096 fprintf (stdout, "W");
2097 fprintf (stdout, "\n");
2098 for (i = 0; i < t->operands; i++)
2099 {
2100 fprintf (stdout, " #%d type ", i + 1);
2101 pt (t->operand_types[i]);
2102 fprintf (stdout, "\n");
2103 }
2104}
2105
2106static void
e3bb37b5 2107pe (expressionS *e)
252b5132 2108{
24eab124 2109 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2110 fprintf (stdout, " add_number %ld (%lx)\n",
2111 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2112 if (e->X_add_symbol)
2113 {
2114 fprintf (stdout, " add_symbol ");
2115 ps (e->X_add_symbol);
2116 fprintf (stdout, "\n");
2117 }
2118 if (e->X_op_symbol)
2119 {
2120 fprintf (stdout, " op_symbol ");
2121 ps (e->X_op_symbol);
2122 fprintf (stdout, "\n");
2123 }
2124}
2125
2126static void
e3bb37b5 2127ps (symbolS *s)
252b5132
RH		 2128{
2129 fprintf (stdout, "%s type %s%s",
2130 S_GET_NAME (s),
2131 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2132 segment_name (S_GET_SEGMENT (s)));
2133}
2134
7b81dfbb 2135static struct type_name
252b5132 2136 {
40fb9820
L		 2137 i386_operand_type mask;
2138 const char *name;
252b5132 2139 }
7b81dfbb 2140const type_names[] =
252b5132 2141{
40fb9820
L		 2142 { OPERAND_TYPE_REG8, "r8" },
2143 { OPERAND_TYPE_REG16, "r16" },
2144 { OPERAND_TYPE_REG32, "r32" },
2145 { OPERAND_TYPE_REG64, "r64" },
2146 { OPERAND_TYPE_IMM8, "i8" },
2147 { OPERAND_TYPE_IMM8, "i8s" },
2148 { OPERAND_TYPE_IMM16, "i16" },
2149 { OPERAND_TYPE_IMM32, "i32" },
2150 { OPERAND_TYPE_IMM32S, "i32s" },
2151 { OPERAND_TYPE_IMM64, "i64" },
2152 { OPERAND_TYPE_IMM1, "i1" },
2153 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2154 { OPERAND_TYPE_DISP8, "d8" },
2155 { OPERAND_TYPE_DISP16, "d16" },
2156 { OPERAND_TYPE_DISP32, "d32" },
2157 { OPERAND_TYPE_DISP32S, "d32s" },
2158 { OPERAND_TYPE_DISP64, "d64" },
2159 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2160 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2161 { OPERAND_TYPE_CONTROL, "control reg" },
2162 { OPERAND_TYPE_TEST, "test reg" },
2163 { OPERAND_TYPE_DEBUG, "debug reg" },
2164 { OPERAND_TYPE_FLOATREG, "FReg" },
2165 { OPERAND_TYPE_FLOATACC, "FAcc" },
2166 { OPERAND_TYPE_SREG2, "SReg2" },
2167 { OPERAND_TYPE_SREG3, "SReg3" },
2168 { OPERAND_TYPE_ACC, "Acc" },
2169 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2170 { OPERAND_TYPE_REGMMX, "rMMX" },
2171 { OPERAND_TYPE_REGXMM, "rXMM" },
2172 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2173};
2174
2175static void
40fb9820 2176pt (i386_operand_type t)
252b5132 2177{
40fb9820 2178 unsigned int j;
c6fb90c8 2179 i386_operand_type a;
252b5132 2180
40fb9820 2181 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2182 {
2183 a = operand_type_and (t, type_names[j].mask);
2184 if (!UINTS_ALL_ZERO (a))
2185 fprintf (stdout, "%s, ", type_names[j].name);
2186 }
252b5132
RH		 2187 fflush (stdout);
2188}
2189
2190#endif /* DEBUG386 */
2191\f
252b5132 2192static bfd_reloc_code_real_type
3956db08 2193reloc (unsigned int size,
64e74474
AM		 2194 int pcrel,
2195 int sign,
2196 bfd_reloc_code_real_type other)
252b5132 2197{
47926f60 2198 if (other != NO_RELOC)
3956db08
JB		 2199 {
2200 reloc_howto_type *reloc;
2201
2202 if (size == 8)
2203 switch (other)
2204 {
64e74474
AM		 2205 case BFD_RELOC_X86_64_GOT32:
2206 return BFD_RELOC_X86_64_GOT64;
2207 break;
2208 case BFD_RELOC_X86_64_PLTOFF64:
2209 return BFD_RELOC_X86_64_PLTOFF64;
2210 break;
2211 case BFD_RELOC_X86_64_GOTPC32:
2212 other = BFD_RELOC_X86_64_GOTPC64;
2213 break;
2214 case BFD_RELOC_X86_64_GOTPCREL:
2215 other = BFD_RELOC_X86_64_GOTPCREL64;
2216 break;
2217 case BFD_RELOC_X86_64_TPOFF32:
2218 other = BFD_RELOC_X86_64_TPOFF64;
2219 break;
2220 case BFD_RELOC_X86_64_DTPOFF32:
2221 other = BFD_RELOC_X86_64_DTPOFF64;
2222 break;
2223 default:
2224 break;
3956db08 2225 }
e05278af
JB		 2226
2227 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2228 if (size == 4 && flag_code != CODE_64BIT)
2229 sign = -1;
2230
3956db08
JB		 2231 reloc = bfd_reloc_type_lookup (stdoutput, other);
2232 if (!reloc)
2233 as_bad (_("unknown relocation (%u)"), other);
2234 else if (size != bfd_get_reloc_size (reloc))
2235 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2236 bfd_get_reloc_size (reloc),
2237 size);
2238 else if (pcrel && !reloc->pc_relative)
2239 as_bad (_("non-pc-relative relocation for pc-relative field"));
2240 else if ((reloc->complain_on_overflow == complain_overflow_signed
2241 && !sign)
2242 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2243 && sign > 0))
3956db08
JB		 2244 as_bad (_("relocated field and relocation type differ in signedness"));
2245 else
2246 return other;
2247 return NO_RELOC;
2248 }
252b5132
RH		 2249
2250 if (pcrel)
2251 {
3e73aa7c 2252 if (!sign)
3956db08 2253 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2254 switch (size)
2255 {
2256 case 1: return BFD_RELOC_8_PCREL;
2257 case 2: return BFD_RELOC_16_PCREL;
2258 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2259 case 8: return BFD_RELOC_64_PCREL;
252b5132 2260 }
3956db08 2261 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2262 }
2263 else
2264 {
3956db08 2265 if (sign > 0)
e5cb08ac 2266 switch (size)
3e73aa7c
JH		 2267 {
2268 case 4: return BFD_RELOC_X86_64_32S;
2269 }
2270 else
2271 switch (size)
2272 {
2273 case 1: return BFD_RELOC_8;
2274 case 2: return BFD_RELOC_16;
2275 case 4: return BFD_RELOC_32;
2276 case 8: return BFD_RELOC_64;
2277 }
3956db08
JB		 2278 as_bad (_("cannot do %s %u byte relocation"),
2279 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2280 }
2281
bfb32b52 2282 abort ();
252b5132
RH		 2283 return BFD_RELOC_NONE;
2284}
2285
47926f60
KH		 2286/* Here we decide which fixups can be adjusted to make them relative to
2287 the beginning of the section instead of the symbol. Basically we need
2288 to make sure that the dynamic relocations are done correctly, so in
2289 some cases we force the original symbol to be used. */
2290
252b5132 2291int
e3bb37b5 2292tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2293{
6d249963 2294#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2295 if (!IS_ELF)
31312f95
AM		 2296 return 1;
2297
a161fe53
AM		 2298 /* Don't adjust pc-relative references to merge sections in 64-bit
2299 mode. */
2300 if (use_rela_relocations
2301 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2302 && fixP->fx_pcrel)
252b5132 2303 return 0;
31312f95 2304
8d01d9a9
AJ		 2305 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2306 and changed later by validate_fix. */
2307 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2308 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2309 return 0;
2310
ce8a8b2f 2311 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2312 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2313 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2314 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2315 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2316 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2317 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2318 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2319 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2320 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2321 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2322 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2323 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2324 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2325 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2326 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2327 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2328 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2329 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2330 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2331 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2332 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2333 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2334 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2335 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2336 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2337 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2338 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2339 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2340 return 0;
31312f95 2341#endif
252b5132
RH		 2342 return 1;
2343}
252b5132 2344
b4cac588 2345static int
e3bb37b5 2346intel_float_operand (const char *mnemonic)
252b5132 2347{
9306ca4a
JB		 2348 /* Note that the value returned is meaningful only for opcodes with (memory)
2349 operands, hence the code here is free to improperly handle opcodes that
2350 have no operands (for better performance and smaller code). */
2351
2352 if (mnemonic[0] != 'f')
2353 return 0; /* non-math */
2354
2355 switch (mnemonic[1])
2356 {
2357 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2358 the fs segment override prefix not currently handled because no
2359 call path can make opcodes without operands get here */
2360 case 'i':
2361 return 2 /* integer op */;
2362 case 'l':
2363 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2364 return 3; /* fldcw/fldenv */
2365 break;
2366 case 'n':
2367 if (mnemonic[2] != 'o' /* fnop */)
2368 return 3; /* non-waiting control op */
2369 break;
2370 case 'r':
2371 if (mnemonic[2] == 's')
2372 return 3; /* frstor/frstpm */
2373 break;
2374 case 's':
2375 if (mnemonic[2] == 'a')
2376 return 3; /* fsave */
2377 if (mnemonic[2] == 't')
2378 {
2379 switch (mnemonic[3])
2380 {
2381 case 'c': /* fstcw */
2382 case 'd': /* fstdw */
2383 case 'e': /* fstenv */
2384 case 's': /* fsts[gw] */
2385 return 3;
2386 }
2387 }
2388 break;
2389 case 'x':
2390 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2391 return 0; /* fxsave/fxrstor are not really math ops */
2392 break;
2393 }
252b5132 2394
9306ca4a 2395 return 1;
252b5132
RH		 2396}
2397
65da13b5
L		 2398static void
2399process_immext (void)
2400{
2401 expressionS *exp;
2402
2403 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2404 {
1fed0ba1
L		 2405 /* SSE3 Instructions have the fixed operands with an opcode
2406 suffix which is coded in the same place as an 8-bit immediate
2407 field would be. Here we check those operands and remove them
2408 afterwards. */
65da13b5
L		 2409 unsigned int x;
2410
2411 for (x = 0; x < i.operands; x++)
2412 if (i.op[x].regs->reg_num != x)
2413 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2414 register_prefix, i.op[x].regs->reg_name, x + 1,
2415 i.tm.name);
2416
2417 i.operands = 0;
65da13b5
L		 2418 }
2419
2420 /* These AMD 3DNow! and SSE2 Instructions have an opcode suffix
2421 which is coded in the same place as an 8-bit immediate field
2422 would be. Here we fake an 8-bit immediate operand from the
2423 opcode suffix stored in tm.extension_opcode.
2424
2425 SSE5 also uses this encoding, for some of its 3 argument
2426 instructions. */
2427
2428 assert (i.imm_operands == 0
2429 && (i.operands <= 2
2430 || (i.tm.cpu_flags.bitfield.cpusse5
2431 && i.operands <= 3)));
2432
2433 exp = &im_expressions[i.imm_operands++];
2434 i.op[i.operands].imms = exp;
2435 i.types[i.operands] = imm8;
2436 i.operands++;
2437 exp->X_op = O_constant;
2438 exp->X_add_number = i.tm.extension_opcode;
2439 i.tm.extension_opcode = None;
2440}
2441
252b5132
RH		 2442/* This is the guts of the machine-dependent assembler. LINE points to a
2443 machine dependent instruction. This function is supposed to emit
2444 the frags/bytes it assembles to. */
2445
2446void
65da13b5 2447md_assemble (char *line)
252b5132 2448{
40fb9820 2449 unsigned int j;
252b5132
RH		 2450 char mnemonic[MAX_MNEM_SIZE];
2451
47926f60 2452 /* Initialize globals. */
252b5132
RH		 2453 memset (&i, '\0', sizeof (i));
2454 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2455 i.reloc[j] = NO_RELOC;
252b5132
RH		 2456 memset (disp_expressions, '\0', sizeof (disp_expressions));
2457 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2458 save_stack_p = save_stack;
252b5132
RH		 2459
2460 /* First parse an instruction mnemonic & call i386_operand for the operands.
2461 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2462 start of a (possibly prefixed) mnemonic. */
252b5132 2463
29b0f896
AM		 2464 line = parse_insn (line, mnemonic);
2465 if (line == NULL)
2466 return;
252b5132 2467
29b0f896
AM		 2468 line = parse_operands (line, mnemonic);
2469 if (line == NULL)
2470 return;
252b5132 2471
29b0f896
AM		 2472 /* Now we've parsed the mnemonic into a set of templates, and have the
2473 operands at hand. */
2474
2475 /* All intel opcodes have reversed operands except for "bound" and
2476 "enter". We also don't reverse intersegment "jmp" and "call"
2477 instructions with 2 immediate operands so that the immediate segment
050dfa73 2478 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2479 if (intel_syntax
2480 && i.operands > 1
29b0f896 2481 && (strcmp (mnemonic, "bound") != 0)
30123838 2482 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2483 && !(operand_type_check (i.types[0], imm)
2484 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2485 swap_operands ();
2486
ec56d5c0
JB		 2487 /* The order of the immediates should be reversed
2488 for 2 immediates extrq and insertq instructions */
2489 if (i.imm_operands == 2
2490 && (strcmp (mnemonic, "extrq") == 0
2491 || strcmp (mnemonic, "insertq") == 0))
2492 swap_2_operands (0, 1);
2493
29b0f896
AM		 2494 if (i.imm_operands)
2495 optimize_imm ();
2496
b300c311
L		 2497 /* Don't optimize displacement for movabs since it only takes 64bit
2498 displacement. */
2499 if (i.disp_operands
2500 && (flag_code != CODE_64BIT
2501 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2502 optimize_disp ();
2503
2504 /* Next, we find a template that matches the given insn,
2505 making sure the overlap of the given operands types is consistent
2506 with the template operand types. */
252b5132 2507
29b0f896
AM		 2508 if (!match_template ())
2509 return;
252b5132 2510
321fd21e
L		 2511 /* Zap movzx and movsx suffix. The suffix has been set from
2512 "word ptr" or "byte ptr" on the source operand in Intel syntax
2513 or extracted from mnemonic in AT&T syntax. But we'll use
2514 the destination register to choose the suffix for encoding. */
2515 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2516 {
321fd21e
L		 2517 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2518 there is no suffix, the default will be byte extension. */
2519 if (i.reg_operands != 2
2520 && !i.suffix
2521 && intel_syntax)
2522 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2523
2524 i.suffix = 0;
cd61ebfe 2525 }
24eab124 2526
40fb9820 2527 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2528 if (!add_prefix (FWAIT_OPCODE))
2529 return;
252b5132 2530
29b0f896 2531 /* Check string instruction segment overrides. */
40fb9820 2532 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2533 {
2534 if (!check_string ())
5dd0794d 2535 return;
29b0f896 2536 }
5dd0794d 2537
29b0f896
AM		 2538 if (!process_suffix ())
2539 return;
e413e4e9 2540
29b0f896
AM		 2541 /* Make still unresolved immediate matches conform to size of immediate
2542 given in i.suffix. */
2543 if (!finalize_imm ())
2544 return;
252b5132 2545
40fb9820 2546 if (i.types[0].bitfield.imm1)
29b0f896 2547 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2548
40fb9820 2549 for (j = 0; j < 3; j++)
c6fb90c8
L		 2550 if (i.types[j].bitfield.inoutportreg
2551 || i.types[j].bitfield.shiftcount
2552 || i.types[j].bitfield.acc
2553 || i.types[j].bitfield.floatacc)
40fb9820
L		 2554 i.reg_operands--;
2555
2556 if (i.tm.opcode_modifier.immext)
65da13b5 2557 process_immext ();
252b5132 2558
29b0f896
AM		 2559 /* For insns with operands there are more diddles to do to the opcode. */
2560 if (i.operands)
2561 {
2562 if (!process_operands ())
2563 return;
2564 }
40fb9820 2565 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2566 {
2567 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2568 as_warn (_("translating to `%sp'"), i.tm.name);
2569 }
252b5132 2570
29b0f896
AM		 2571 /* Handle conversion of 'int $3' --> special int3 insn. */
2572 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2573 {
2574 i.tm.base_opcode = INT3_OPCODE;
2575 i.imm_operands = 0;
2576 }
252b5132 2577
40fb9820
L		 2578 if ((i.tm.opcode_modifier.jump
2579 || i.tm.opcode_modifier.jumpbyte
2580 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2581 && i.op[0].disps->X_op == O_constant)
2582 {
2583 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2584 the absolute address given by the constant. Since ix86 jumps and
2585 calls are pc relative, we need to generate a reloc. */
2586 i.op[0].disps->X_add_symbol = &abs_symbol;
2587 i.op[0].disps->X_op = O_symbol;
2588 }
252b5132 2589
40fb9820 2590 if (i.tm.opcode_modifier.rex64)
161a04f6 2591 i.rex |= REX_W;
252b5132 2592
29b0f896
AM		 2593 /* For 8 bit registers we need an empty rex prefix. Also if the
2594 instruction already has a prefix, we need to convert old
2595 registers to new ones. */
773f551c 2596
40fb9820 2597 if ((i.types[0].bitfield.reg8
29b0f896 2598 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2599 || (i.types[1].bitfield.reg8
29b0f896 2600 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2601 || ((i.types[0].bitfield.reg8
2602 || i.types[1].bitfield.reg8)
29b0f896
AM		 2603 && i.rex != 0))
2604 {
2605 int x;
726c5dcd 2606
29b0f896
AM		 2607 i.rex |= REX_OPCODE;
2608 for (x = 0; x < 2; x++)
2609 {
2610 /* Look for 8 bit operand that uses old registers. */
40fb9820 2611 if (i.types[x].bitfield.reg8
29b0f896 2612 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2613 {
29b0f896
AM		 2614 /* In case it is "hi" register, give up. */
2615 if (i.op[x].regs->reg_num > 3)
a540244d 2616 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2617 "instruction requiring REX prefix."),
a540244d 2618 register_prefix, i.op[x].regs->reg_name);
773f551c 2619
29b0f896
AM		 2620 /* Otherwise it is equivalent to the extended register.
2621 Since the encoding doesn't change this is merely
2622 cosmetic cleanup for debug output. */
2623
2624 i.op[x].regs = i.op[x].regs + 8;
773f551c 2625 }
29b0f896
AM		 2626 }
2627 }
773f551c 2628
85f10a01
MM		 2629 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2630 REX prefix. */
2631 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2632 {
2633 i.drex.rex = i.rex;
2634 i.rex = 0;
2635 }
2636 else if (i.rex != 0)
29b0f896
AM		 2637 add_prefix (REX_OPCODE | i.rex);
2638
2639 /* We are ready to output the insn. */
2640 output_insn ();
2641}
2642
2643static char *
e3bb37b5 2644parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2645{
2646 char *l = line;
2647 char *token_start = l;
2648 char *mnem_p;
5c6af06e
JB		 2649 int supported;
2650 const template *t;
29b0f896
AM		 2651
2652 /* Non-zero if we found a prefix only acceptable with string insns. */
2653 const char *expecting_string_instruction = NULL;
45288df1 2654
29b0f896
AM		 2655 while (1)
2656 {
2657 mnem_p = mnemonic;
2658 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2659 {
2660 mnem_p++;
2661 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2662 {
29b0f896
AM		 2663 as_bad (_("no such instruction: `%s'"), token_start);
2664 return NULL;
2665 }
2666 l++;
2667 }
2668 if (!is_space_char (*l)
2669 && *l != END_OF_INSN
e44823cf
JB		 2670 && (intel_syntax
2671 || (*l != PREFIX_SEPARATOR
2672 && *l != ',')))
29b0f896
AM		 2673 {
2674 as_bad (_("invalid character %s in mnemonic"),
2675 output_invalid (*l));
2676 return NULL;
2677 }
2678 if (token_start == l)
2679 {
e44823cf 2680 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2681 as_bad (_("expecting prefix; got nothing"));
2682 else
2683 as_bad (_("expecting mnemonic; got nothing"));
2684 return NULL;
2685 }
45288df1 2686
29b0f896
AM		 2687 /* Look up instruction (or prefix) via hash table. */
2688 current_templates = hash_find (op_hash, mnemonic);
47926f60 2689
29b0f896
AM		 2690 if (*l != END_OF_INSN
2691 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2692 && current_templates
40fb9820 2693 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2694 {
c6fb90c8 2695 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2696 {
2697 as_bad ((flag_code != CODE_64BIT
2698 ? _("`%s' is only supported in 64-bit mode")
2699 : _("`%s' is not supported in 64-bit mode")),
2700 current_templates->start->name);
2701 return NULL;
2702 }
29b0f896
AM		 2703 /* If we are in 16-bit mode, do not allow addr16 or data16.
2704 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2705 if ((current_templates->start->opcode_modifier.size16
2706 || current_templates->start->opcode_modifier.size32)
29b0f896 2707 && flag_code != CODE_64BIT
40fb9820 2708 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2709 ^ (flag_code == CODE_16BIT)))
2710 {
2711 as_bad (_("redundant %s prefix"),
2712 current_templates->start->name);
2713 return NULL;
45288df1 2714 }
29b0f896
AM		 2715 /* Add prefix, checking for repeated prefixes. */
2716 switch (add_prefix (current_templates->start->base_opcode))
2717 {
2718 case 0:
2719 return NULL;
2720 case 2:
2721 expecting_string_instruction = current_templates->start->name;
2722 break;
2723 }
2724 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2725 token_start = ++l;
2726 }
2727 else
2728 break;
2729 }
45288df1 2730
29b0f896
AM		 2731 if (!current_templates)
2732 {
2733 /* See if we can get a match by trimming off a suffix. */
2734 switch (mnem_p[-1])
2735 {
2736 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2737 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2738 i.suffix = SHORT_MNEM_SUFFIX;
2739 else
29b0f896
AM		 2740 case BYTE_MNEM_SUFFIX:
2741 case QWORD_MNEM_SUFFIX:
2742 i.suffix = mnem_p[-1];
2743 mnem_p[-1] = '\0';
2744 current_templates = hash_find (op_hash, mnemonic);
2745 break;
2746 case SHORT_MNEM_SUFFIX:
2747 case LONG_MNEM_SUFFIX:
2748 if (!intel_syntax)
2749 {
2750 i.suffix = mnem_p[-1];
2751 mnem_p[-1] = '\0';
2752 current_templates = hash_find (op_hash, mnemonic);
2753 }
2754 break;
252b5132 2755
29b0f896
AM		 2756 /* Intel Syntax. */
2757 case 'd':
2758 if (intel_syntax)
2759 {
9306ca4a 2760 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2761 i.suffix = SHORT_MNEM_SUFFIX;
2762 else
2763 i.suffix = LONG_MNEM_SUFFIX;
2764 mnem_p[-1] = '\0';
2765 current_templates = hash_find (op_hash, mnemonic);
2766 }
2767 break;
2768 }
2769 if (!current_templates)
2770 {
2771 as_bad (_("no such instruction: `%s'"), token_start);
2772 return NULL;
2773 }
2774 }
252b5132 2775
40fb9820
L		 2776 if (current_templates->start->opcode_modifier.jump
2777 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2778 {
2779 /* Check for a branch hint. We allow ",pt" and ",pn" for
2780 predict taken and predict not taken respectively.
2781 I'm not sure that branch hints actually do anything on loop
2782 and jcxz insns (JumpByte) for current Pentium4 chips. They
2783 may work in the future and it doesn't hurt to accept them
2784 now. */
2785 if (l[0] == ',' && l[1] == 'p')
2786 {
2787 if (l[2] == 't')
2788 {
2789 if (!add_prefix (DS_PREFIX_OPCODE))
2790 return NULL;
2791 l += 3;
2792 }
2793 else if (l[2] == 'n')
2794 {
2795 if (!add_prefix (CS_PREFIX_OPCODE))
2796 return NULL;
2797 l += 3;
2798 }
2799 }
2800 }
2801 /* Any other comma loses. */
2802 if (*l == ',')
2803 {
2804 as_bad (_("invalid character %s in mnemonic"),
2805 output_invalid (*l));
2806 return NULL;
2807 }
252b5132 2808
29b0f896 2809 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2810 supported = 0;
2811 for (t = current_templates->start; t < current_templates->end; ++t)
2812 {
3629bb00
L		 2813 supported |= cpu_flags_match (t->cpu_flags);
2814 if (supported == 3)
2815 goto skip;
5c6af06e 2816 }
3629bb00 2817
5c6af06e
JB		 2818 if (!(supported & 2))
2819 {
2820 as_bad (flag_code == CODE_64BIT
2821 ? _("`%s' is not supported in 64-bit mode")
2822 : _("`%s' is only supported in 64-bit mode"),
2823 current_templates->start->name);
2824 return NULL;
2825 }
2826 if (!(supported & 1))
29b0f896 2827 {
3629bb00
L		 2828 as_bad (_("`%s' is not supported on `%s%s'"),
2829 current_templates->start->name, cpu_arch_name,
2830 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2831 return NULL;
29b0f896 2832 }
3629bb00
L		 2833
2834skip:
2835 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2836 && (flag_code != CODE_16BIT))
29b0f896
AM		 2837 {
2838 as_warn (_("use .code16 to ensure correct addressing mode"));
2839 }
252b5132 2840
29b0f896 2841 /* Check for rep/repne without a string instruction. */
f41bbced 2842 if (expecting_string_instruction)
29b0f896 2843 {
f41bbced
JB		 2844 static templates override;
2845
2846 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2847 if (t->opcode_modifier.isstring)
f41bbced
JB		 2848 break;
2849 if (t >= current_templates->end)
2850 {
2851 as_bad (_("expecting string instruction after `%s'"),
64e74474 2852 expecting_string_instruction);
f41bbced
JB		 2853 return NULL;
2854 }
2855 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2856 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2857 break;
2858 override.end = t;
2859 current_templates = &override;
29b0f896 2860 }
252b5132 2861
29b0f896
AM		 2862 return l;
2863}
252b5132 2864
29b0f896 2865static char *
e3bb37b5 2866parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2867{
2868 char *token_start;
3138f287 2869
29b0f896
AM		 2870 /* 1 if operand is pending after ','. */
2871 unsigned int expecting_operand = 0;
252b5132 2872
29b0f896
AM		 2873 /* Non-zero if operand parens not balanced. */
2874 unsigned int paren_not_balanced;
2875
2876 while (*l != END_OF_INSN)
2877 {
2878 /* Skip optional white space before operand. */
2879 if (is_space_char (*l))
2880 ++l;
2881 if (!is_operand_char (*l) && *l != END_OF_INSN)
2882 {
2883 as_bad (_("invalid character %s before operand %d"),
2884 output_invalid (*l),
2885 i.operands + 1);
2886 return NULL;
2887 }
2888 token_start = l; /* after white space */
2889 paren_not_balanced = 0;
2890 while (paren_not_balanced || *l != ',')
2891 {
2892 if (*l == END_OF_INSN)
2893 {
2894 if (paren_not_balanced)
2895 {
2896 if (!intel_syntax)
2897 as_bad (_("unbalanced parenthesis in operand %d."),
2898 i.operands + 1);
2899 else
2900 as_bad (_("unbalanced brackets in operand %d."),
2901 i.operands + 1);
2902 return NULL;
2903 }
2904 else
2905 break; /* we are done */
2906 }
2907 else if (!is_operand_char (*l) && !is_space_char (*l))
2908 {
2909 as_bad (_("invalid character %s in operand %d"),
2910 output_invalid (*l),
2911 i.operands + 1);
2912 return NULL;
2913 }
2914 if (!intel_syntax)
2915 {
2916 if (*l == '(')
2917 ++paren_not_balanced;
2918 if (*l == ')')
2919 --paren_not_balanced;
2920 }
2921 else
2922 {
2923 if (*l == '[')
2924 ++paren_not_balanced;
2925 if (*l == ']')
2926 --paren_not_balanced;
2927 }
2928 l++;
2929 }
2930 if (l != token_start)
2931 { /* Yes, we've read in another operand. */
2932 unsigned int operand_ok;
2933 this_operand = i.operands++;
7d5e4556 2934 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 2935 if (i.operands > MAX_OPERANDS)
2936 {
2937 as_bad (_("spurious operands; (%d operands/instruction max)"),
2938 MAX_OPERANDS);
2939 return NULL;
2940 }
2941 /* Now parse operand adding info to 'i' as we go along. */
2942 END_STRING_AND_SAVE (l);
2943
2944 if (intel_syntax)
2945 operand_ok =
2946 i386_intel_operand (token_start,
2947 intel_float_operand (mnemonic));
2948 else
a7619375 2949 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 2950
2951 RESTORE_END_STRING (l);
2952 if (!operand_ok)
2953 return NULL;
2954 }
2955 else
2956 {
2957 if (expecting_operand)
2958 {
2959 expecting_operand_after_comma:
2960 as_bad (_("expecting operand after ','; got nothing"));
2961 return NULL;
2962 }
2963 if (*l == ',')
2964 {
2965 as_bad (_("expecting operand before ','; got nothing"));
2966 return NULL;
2967 }
2968 }
7f3f1ea2 2969
29b0f896
AM		 2970 /* Now *l must be either ',' or END_OF_INSN. */
2971 if (*l == ',')
2972 {
2973 if (*++l == END_OF_INSN)
2974 {
2975 /* Just skip it, if it's \n complain. */
2976 goto expecting_operand_after_comma;
2977 }
2978 expecting_operand = 1;
2979 }
2980 }
2981 return l;
2982}
7f3f1ea2 2983
050dfa73 2984static void
4d456e3d 2985swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2986{
2987 union i386_op temp_op;
40fb9820 2988 i386_operand_type temp_type;
050dfa73 2989 enum bfd_reloc_code_real temp_reloc;
4eed87de 2990
050dfa73
MM		 2991 temp_type = i.types[xchg2];
2992 i.types[xchg2] = i.types[xchg1];
2993 i.types[xchg1] = temp_type;
2994 temp_op = i.op[xchg2];
2995 i.op[xchg2] = i.op[xchg1];
2996 i.op[xchg1] = temp_op;
2997 temp_reloc = i.reloc[xchg2];
2998 i.reloc[xchg2] = i.reloc[xchg1];
2999 i.reloc[xchg1] = temp_reloc;
3000}
3001
29b0f896 3002static void
e3bb37b5 3003swap_operands (void)
29b0f896 3004{
b7c61d9a 3005 switch (i.operands)
050dfa73 3006 {
b7c61d9a 3007 case 4:
4d456e3d 3008 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3009 case 3:
3010 case 2:
4d456e3d 3011 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3012 break;
3013 default:
3014 abort ();
29b0f896 3015 }
29b0f896
AM		 3016
3017 if (i.mem_operands == 2)
3018 {
3019 const seg_entry *temp_seg;
3020 temp_seg = i.seg[0];
3021 i.seg[0] = i.seg[1];
3022 i.seg[1] = temp_seg;
3023 }
3024}
252b5132 3025
29b0f896
AM		 3026/* Try to ensure constant immediates are represented in the smallest
3027 opcode possible. */
3028static void
e3bb37b5 3029optimize_imm (void)
29b0f896
AM		 3030{
3031 char guess_suffix = 0;
3032 int op;
252b5132 3033
29b0f896
AM		 3034 if (i.suffix)
3035 guess_suffix = i.suffix;
3036 else if (i.reg_operands)
3037 {
3038 /* Figure out a suffix from the last register operand specified.
3039 We can't do this properly yet, ie. excluding InOutPortReg,
3040 but the following works for instructions with immediates.
3041 In any case, we can't set i.suffix yet. */
3042 for (op = i.operands; --op >= 0;)
40fb9820
L		 3043 if (i.types[op].bitfield.reg8)
3044 {
3045 guess_suffix = BYTE_MNEM_SUFFIX;
3046 break;
3047 }
3048 else if (i.types[op].bitfield.reg16)
252b5132 3049 {
40fb9820
L		 3050 guess_suffix = WORD_MNEM_SUFFIX;
3051 break;
3052 }
3053 else if (i.types[op].bitfield.reg32)
3054 {
3055 guess_suffix = LONG_MNEM_SUFFIX;
3056 break;
3057 }
3058 else if (i.types[op].bitfield.reg64)
3059 {
3060 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3061 break;
252b5132 3062 }
29b0f896
AM		 3063 }
3064 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3065 guess_suffix = WORD_MNEM_SUFFIX;
3066
3067 for (op = i.operands; --op >= 0;)
40fb9820 3068 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3069 {
3070 switch (i.op[op].imms->X_op)
252b5132 3071 {
29b0f896
AM		 3072 case O_constant:
3073 /* If a suffix is given, this operand may be shortened. */
3074 switch (guess_suffix)
252b5132 3075 {
29b0f896 3076 case LONG_MNEM_SUFFIX:
40fb9820
L		 3077 i.types[op].bitfield.imm32 = 1;
3078 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3079 break;
3080 case WORD_MNEM_SUFFIX:
40fb9820
L		 3081 i.types[op].bitfield.imm16 = 1;
3082 i.types[op].bitfield.imm32 = 1;
3083 i.types[op].bitfield.imm32s = 1;
3084 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3085 break;
3086 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3087 i.types[op].bitfield.imm8 = 1;
3088 i.types[op].bitfield.imm8s = 1;
3089 i.types[op].bitfield.imm16 = 1;
3090 i.types[op].bitfield.imm32 = 1;
3091 i.types[op].bitfield.imm32s = 1;
3092 i.types[op].bitfield.imm64 = 1;
29b0f896 3093 break;
252b5132 3094 }
252b5132 3095
29b0f896
AM		 3096 /* If this operand is at most 16 bits, convert it
3097 to a signed 16 bit number before trying to see
3098 whether it will fit in an even smaller size.
3099 This allows a 16-bit operand such as $0xffe0 to
3100 be recognised as within Imm8S range. */
40fb9820 3101 if ((i.types[op].bitfield.imm16)
29b0f896 3102 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3103 {
29b0f896
AM		 3104 i.op[op].imms->X_add_number =
3105 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3106 }
40fb9820 3107 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3108 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3109 == 0))
3110 {
3111 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3112 ^ ((offsetT) 1 << 31))
3113 - ((offsetT) 1 << 31));
3114 }
40fb9820 3115 i.types[op]
c6fb90c8
L		 3116 = operand_type_or (i.types[op],
3117 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3118
29b0f896
AM		 3119 /* We must avoid matching of Imm32 templates when 64bit
3120 only immediate is available. */
3121 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3122 i.types[op].bitfield.imm32 = 0;
29b0f896 3123 break;
252b5132 3124
29b0f896
AM		 3125 case O_absent:
3126 case O_register:
3127 abort ();
3128
3129 /* Symbols and expressions. */
3130 default:
9cd96992
JB		 3131 /* Convert symbolic operand to proper sizes for matching, but don't
3132 prevent matching a set of insns that only supports sizes other
3133 than those matching the insn suffix. */
3134 {
40fb9820 3135 i386_operand_type mask, allowed;
9cd96992
JB		 3136 const template *t;
3137
0dfbf9d7
L		 3138 operand_type_set (&mask, 0);
3139 operand_type_set (&allowed, 0);
40fb9820 3140
4eed87de
AM		 3141 for (t = current_templates->start;
3142 t < current_templates->end;
3143 ++t)
c6fb90c8
L		 3144 allowed = operand_type_or (allowed,
3145 t->operand_types[op]);
9cd96992
JB		 3146 switch (guess_suffix)
3147 {
3148 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3149 mask.bitfield.imm64 = 1;
3150 mask.bitfield.imm32s = 1;
9cd96992
JB		 3151 break;
3152 case LONG_MNEM_SUFFIX:
40fb9820 3153 mask.bitfield.imm32 = 1;
9cd96992
JB		 3154 break;
3155 case WORD_MNEM_SUFFIX:
40fb9820 3156 mask.bitfield.imm16 = 1;
9cd96992
JB		 3157 break;
3158 case BYTE_MNEM_SUFFIX:
40fb9820 3159 mask.bitfield.imm8 = 1;
9cd96992
JB		 3160 break;
3161 default:
9cd96992
JB		 3162 break;
3163 }
c6fb90c8 3164 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3165 if (!operand_type_all_zero (&allowed))
c6fb90c8 3166 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3167 }
29b0f896 3168 break;
252b5132 3169 }
29b0f896
AM		 3170 }
3171}
47926f60 3172
29b0f896
AM		 3173/* Try to use the smallest displacement type too. */
3174static void
e3bb37b5 3175optimize_disp (void)
29b0f896
AM		 3176{
3177 int op;
3e73aa7c 3178
29b0f896 3179 for (op = i.operands; --op >= 0;)
40fb9820 3180 if (operand_type_check (i.types[op], disp))
252b5132 3181 {
b300c311 3182 if (i.op[op].disps->X_op == O_constant)
252b5132 3183 {
b300c311 3184 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3185
40fb9820 3186 if (i.types[op].bitfield.disp16
b300c311
L		 3187 && (disp & ~(offsetT) 0xffff) == 0)
3188 {
3189 /* If this operand is at most 16 bits, convert
3190 to a signed 16 bit number and don't use 64bit
3191 displacement. */
3192 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3193 i.types[op].bitfield.disp64 = 0;
b300c311 3194 }
40fb9820 3195 if (i.types[op].bitfield.disp32
b300c311
L		 3196 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3197 {
3198 /* If this operand is at most 32 bits, convert
3199 to a signed 32 bit number and don't use 64bit
3200 displacement. */
3201 disp &= (((offsetT) 2 << 31) - 1);
3202 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3203 i.types[op].bitfield.disp64 = 0;
b300c311 3204 }
40fb9820 3205 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3206 {
40fb9820
L		 3207 i.types[op].bitfield.disp8 = 0;
3208 i.types[op].bitfield.disp16 = 0;
3209 i.types[op].bitfield.disp32 = 0;
3210 i.types[op].bitfield.disp32s = 0;
3211 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3212 i.op[op].disps = 0;
3213 i.disp_operands--;
3214 }
3215 else if (flag_code == CODE_64BIT)
3216 {
3217 if (fits_in_signed_long (disp))
28a9d8f5 3218 {
40fb9820
L		 3219 i.types[op].bitfield.disp64 = 0;
3220 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3221 }
b300c311 3222 if (fits_in_unsigned_long (disp))
40fb9820 3223 i.types[op].bitfield.disp32 = 1;
b300c311 3224 }
40fb9820
L		 3225 if ((i.types[op].bitfield.disp32
3226 || i.types[op].bitfield.disp32s
3227 || i.types[op].bitfield.disp16)
b300c311 3228 && fits_in_signed_byte (disp))
40fb9820 3229 i.types[op].bitfield.disp8 = 1;
252b5132 3230 }
67a4f2b7
AO		 3231 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3232 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3233 {
3234 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3235 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3236 i.types[op].bitfield.disp8 = 0;
3237 i.types[op].bitfield.disp16 = 0;
3238 i.types[op].bitfield.disp32 = 0;
3239 i.types[op].bitfield.disp32s = 0;
3240 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3241 }
3242 else
b300c311 3243 /* We only support 64bit displacement on constants. */
40fb9820 3244 i.types[op].bitfield.disp64 = 0;
252b5132 3245 }
29b0f896
AM		 3246}
3247
3248static int
e3bb37b5 3249match_template (void)
29b0f896
AM		 3250{
3251 /* Points to template once we've found it. */
3252 const template *t;
40fb9820 3253 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 3254 unsigned int found_reverse_match;
40fb9820
L		 3255 i386_opcode_modifier suffix_check;
3256 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3257 int addr_prefix_disp;
a5c311ca 3258 unsigned int j;
3629bb00 3259 unsigned int found_cpu_match;
45664ddb 3260 unsigned int check_register;
29b0f896 3261
f48ff2ae
L		 3262#if MAX_OPERANDS != 4
3263# error "MAX_OPERANDS must be 4."
3264#endif
3265
29b0f896 3266 found_reverse_match = 0;
539e75ad 3267 addr_prefix_disp = -1;
40fb9820
L		 3268
3269 memset (&suffix_check, 0, sizeof (suffix_check));
3270 if (i.suffix == BYTE_MNEM_SUFFIX)
3271 suffix_check.no_bsuf = 1;
3272 else if (i.suffix == WORD_MNEM_SUFFIX)
3273 suffix_check.no_wsuf = 1;
3274 else if (i.suffix == SHORT_MNEM_SUFFIX)
3275 suffix_check.no_ssuf = 1;
3276 else if (i.suffix == LONG_MNEM_SUFFIX)
3277 suffix_check.no_lsuf = 1;
3278 else if (i.suffix == QWORD_MNEM_SUFFIX)
3279 suffix_check.no_qsuf = 1;
3280 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3281 suffix_check.no_ldsuf = 1;
29b0f896 3282
45aa61fe 3283 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3284 {
539e75ad
L		 3285 addr_prefix_disp = -1;
3286
29b0f896
AM		 3287 /* Must have right number of operands. */
3288 if (i.operands != t->operands)
3289 continue;
3290
50aecf8c
L		 3291 /* Check processor support. */
3292 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3293 if (!found_cpu_match)
3294 continue;
3295
e1d4d893
L		 3296 /* Check old gcc support. */
3297 if (!old_gcc && t->opcode_modifier.oldgcc)
3298 continue;
3299
3300 /* Check AT&T mnemonic. */
3301 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3302 continue;
3303
5c07affc
L		 3304 /* Check AT&T syntax Intel syntax. */
3305 if ((intel_syntax && t->opcode_modifier.attsyntax)
3306 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3307 continue;
3308
20592a94 3309 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3310 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3311 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3312 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3313 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3314 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3315 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3316 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3317 continue;
3318
5c07affc 3319 if (!operand_size_match (t))
7d5e4556 3320 continue;
539e75ad 3321
5c07affc
L		 3322 for (j = 0; j < MAX_OPERANDS; j++)
3323 operand_types[j] = t->operand_types[j];
3324
45aa61fe
AM		 3325 /* In general, don't allow 64-bit operands in 32-bit mode. */
3326 if (i.suffix == QWORD_MNEM_SUFFIX
3327 && flag_code != CODE_64BIT
3328 && (intel_syntax
40fb9820 3329 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3330 && !intel_float_operand (t->name))
3331 : intel_float_operand (t->name) != 2)
40fb9820
L		 3332 && ((!operand_types[0].bitfield.regmmx
3333 && !operand_types[0].bitfield.regxmm)
3334 || (!operand_types[t->operands > 1].bitfield.regmmx
3335 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3336 && (t->base_opcode != 0x0fc7
3337 || t->extension_opcode != 1 /* cmpxchg8b */))
3338 continue;
3339
29b0f896 3340 /* Do not verify operands when there are none. */
50aecf8c 3341 else
29b0f896 3342 {
c6fb90c8 3343 if (!t->operands)
2dbab7d5
L		 3344 /* We've found a match; break out of loop. */
3345 break;
29b0f896 3346 }
252b5132 3347
539e75ad
L		 3348 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3349 into Disp32/Disp16/Disp32 operand. */
3350 if (i.prefix[ADDR_PREFIX] != 0)
3351 {
40fb9820 3352 /* There should be only one Disp operand. */
539e75ad
L		 3353 switch (flag_code)
3354 {
3355 case CODE_16BIT:
40fb9820
L		 3356 for (j = 0; j < MAX_OPERANDS; j++)
3357 {
3358 if (operand_types[j].bitfield.disp16)
3359 {
3360 addr_prefix_disp = j;
3361 operand_types[j].bitfield.disp32 = 1;
3362 operand_types[j].bitfield.disp16 = 0;
3363 break;
3364 }
3365 }
539e75ad
L		 3366 break;
3367 case CODE_32BIT:
40fb9820
L		 3368 for (j = 0; j < MAX_OPERANDS; j++)
3369 {
3370 if (operand_types[j].bitfield.disp32)
3371 {
3372 addr_prefix_disp = j;
3373 operand_types[j].bitfield.disp32 = 0;
3374 operand_types[j].bitfield.disp16 = 1;
3375 break;
3376 }
3377 }
539e75ad
L		 3378 break;
3379 case CODE_64BIT:
40fb9820
L		 3380 for (j = 0; j < MAX_OPERANDS; j++)
3381 {
3382 if (operand_types[j].bitfield.disp64)
3383 {
3384 addr_prefix_disp = j;
3385 operand_types[j].bitfield.disp64 = 0;
3386 operand_types[j].bitfield.disp32 = 1;
3387 break;
3388 }
3389 }
539e75ad
L		 3390 break;
3391 }
539e75ad
L		 3392 }
3393
45664ddb
L		 3394 /* We check register size only if size of operands can be
3395 encoded the canonical way. */
3396 check_register = t->opcode_modifier.w;
c6fb90c8 3397 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3398 switch (t->operands)
3399 {
3400 case 1:
40fb9820 3401 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3402 continue;
3403 break;
3404 case 2:
8b38ad71
L		 3405 /* xchg %eax, %eax is a special case. It is an aliase for nop
3406 only in 32bit mode and we can use opcode 0x90. In 64bit
3407 mode, we can't use 0x90 for xchg %eax, %eax since it should
3408 zero-extend %eax to %rax. */
3409 if (flag_code == CODE_64BIT
3410 && t->base_opcode == 0x90
0dfbf9d7
L		 3411 && operand_type_equal (&i.types [0], &acc32)
3412 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3413 continue;
29b0f896 3414 case 3:
f48ff2ae 3415 case 4:
c6fb90c8 3416 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3417 if (!operand_type_match (overlap0, i.types[0])
3418 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3419 || (check_register
3420 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3421 operand_types[0],
3422 overlap1, i.types[1],
3423 operand_types[1])))
29b0f896
AM		 3424 {
3425 /* Check if other direction is valid ... */
40fb9820 3426 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3427 continue;
3428
3429 /* Try reversing direction of operands. */
c6fb90c8
L		 3430 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3431 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3432 if (!operand_type_match (overlap0, i.types[0])
3433 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3434 || (check_register
3435 && !operand_type_register_match (overlap0,
3436 i.types[0],
3437 operand_types[1],
3438 overlap1,
3439 i.types[1],
3440 operand_types[0])))
29b0f896
AM		 3441 {
3442 /* Does not match either direction. */
3443 continue;
3444 }
3445 /* found_reverse_match holds which of D or FloatDR
3446 we've found. */
40fb9820 3447 if (t->opcode_modifier.d)
8a2ed489 3448 found_reverse_match = Opcode_D;
40fb9820 3449 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3450 found_reverse_match = Opcode_FloatD;
3451 else
3452 found_reverse_match = 0;
40fb9820 3453 if (t->opcode_modifier.floatr)
8a2ed489 3454 found_reverse_match |= Opcode_FloatR;
29b0f896 3455 }
f48ff2ae 3456 else
29b0f896 3457 {
f48ff2ae 3458 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3459 switch (t->operands)
3460 {
3461 case 4:
c6fb90c8
L		 3462 overlap3 = operand_type_and (i.types[3],
3463 operand_types[3]);
d1cbb4db 3464 case 3:
c6fb90c8
L		 3465 overlap2 = operand_type_and (i.types[2],
3466 operand_types[2]);
d1cbb4db
L		 3467 break;
3468 }
29b0f896 3469
f48ff2ae
L		 3470 switch (t->operands)
3471 {
3472 case 4:
40fb9820 3473 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3474 || (check_register
3475 && !operand_type_register_match (overlap2,
3476 i.types[2],
3477 operand_types[2],
3478 overlap3,
3479 i.types[3],
3480 operand_types[3])))
f48ff2ae
L		 3481 continue;
3482 case 3:
3483 /* Here we make use of the fact that there are no
3484 reverse match 3 operand instructions, and all 3
3485 operand instructions only need to be checked for
3486 register consistency between operands 2 and 3. */
40fb9820 3487 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3488 || (check_register
3489 && !operand_type_register_match (overlap1,
3490 i.types[1],
3491 operand_types[1],
3492 overlap2,
3493 i.types[2],
3494 operand_types[2])))
f48ff2ae
L		 3495 continue;
3496 break;
3497 }
29b0f896 3498 }
f48ff2ae 3499 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3500 slip through to break. */
3501 }
3629bb00 3502 if (!found_cpu_match)
29b0f896
AM		 3503 {
3504 found_reverse_match = 0;
3505 continue;
3506 }
3507 /* We've found a match; break out of loop. */
3508 break;
3509 }
3510
3511 if (t == current_templates->end)
3512 {
3513 /* We found no match. */
3514 as_bad (_("suffix or operands invalid for `%s'"),
3515 current_templates->start->name);
3516 return 0;
3517 }
252b5132 3518
29b0f896
AM		 3519 if (!quiet_warnings)
3520 {
3521 if (!intel_syntax
40fb9820
L		 3522 && (i.types[0].bitfield.jumpabsolute
3523 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3524 {
3525 as_warn (_("indirect %s without `*'"), t->name);
3526 }
3527
40fb9820
L		 3528 if (t->opcode_modifier.isprefix
3529 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3530 {
3531 /* Warn them that a data or address size prefix doesn't
3532 affect assembly of the next line of code. */
3533 as_warn (_("stand-alone `%s' prefix"), t->name);
3534 }
3535 }
3536
3537 /* Copy the template we found. */
3538 i.tm = *t;
539e75ad
L		 3539
3540 if (addr_prefix_disp != -1)
3541 i.tm.operand_types[addr_prefix_disp]
3542 = operand_types[addr_prefix_disp];
3543
29b0f896
AM		 3544 if (found_reverse_match)
3545 {
3546 /* If we found a reverse match we must alter the opcode
3547 direction bit. found_reverse_match holds bits to change
3548 (different for int & float insns). */
3549
3550 i.tm.base_opcode ^= found_reverse_match;
3551
539e75ad
L		 3552 i.tm.operand_types[0] = operand_types[1];
3553 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3554 }
3555
3556 return 1;
3557}
3558
3559static int
e3bb37b5 3560check_string (void)
29b0f896 3561{
40fb9820
L		 3562 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3563 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3564 {
3565 if (i.seg[0] != NULL && i.seg[0] != &es)
3566 {
3567 as_bad (_("`%s' operand %d must use `%%es' segment"),
3568 i.tm.name,
3569 mem_op + 1);
3570 return 0;
3571 }
3572 /* There's only ever one segment override allowed per instruction.
3573 This instruction possibly has a legal segment override on the
3574 second operand, so copy the segment to where non-string
3575 instructions store it, allowing common code. */
3576 i.seg[0] = i.seg[1];
3577 }
40fb9820 3578 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3579 {
3580 if (i.seg[1] != NULL && i.seg[1] != &es)
3581 {
3582 as_bad (_("`%s' operand %d must use `%%es' segment"),
3583 i.tm.name,
3584 mem_op + 2);
3585 return 0;
3586 }
3587 }
3588 return 1;
3589}
3590
3591static int
543613e9 3592process_suffix (void)
29b0f896
AM		 3593{
3594 /* If matched instruction specifies an explicit instruction mnemonic
3595 suffix, use it. */
40fb9820
L		 3596 if (i.tm.opcode_modifier.size16)
3597 i.suffix = WORD_MNEM_SUFFIX;
3598 else if (i.tm.opcode_modifier.size32)
3599 i.suffix = LONG_MNEM_SUFFIX;
3600 else if (i.tm.opcode_modifier.size64)
3601 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3602 else if (i.reg_operands)
3603 {
3604 /* If there's no instruction mnemonic suffix we try to invent one
3605 based on register operands. */
3606 if (!i.suffix)
3607 {
3608 /* We take i.suffix from the last register operand specified,
3609 Destination register type is more significant than source
381d071f
L		 3610 register type. crc32 in SSE4.2 prefers source register
3611 type. */
3612 if (i.tm.base_opcode == 0xf20f38f1)
3613 {
40fb9820
L		 3614 if (i.types[0].bitfield.reg16)
3615 i.suffix = WORD_MNEM_SUFFIX;
3616 else if (i.types[0].bitfield.reg32)
3617 i.suffix = LONG_MNEM_SUFFIX;
3618 else if (i.types[0].bitfield.reg64)
3619 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3620 }
9344ff29 3621 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3622 {
40fb9820 3623 if (i.types[0].bitfield.reg8)
20592a94
L		 3624 i.suffix = BYTE_MNEM_SUFFIX;
3625 }
381d071f
L		 3626
3627 if (!i.suffix)
3628 {
3629 int op;
3630
20592a94
L		 3631 if (i.tm.base_opcode == 0xf20f38f1
3632 || i.tm.base_opcode == 0xf20f38f0)
3633 {
3634 /* We have to know the operand size for crc32. */
3635 as_bad (_("ambiguous memory operand size for `%s`"),
3636 i.tm.name);
3637 return 0;
3638 }
3639
381d071f 3640 for (op = i.operands; --op >= 0;)
40fb9820 3641 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3642 {
40fb9820
L		 3643 if (i.types[op].bitfield.reg8)
3644 {
3645 i.suffix = BYTE_MNEM_SUFFIX;
3646 break;
3647 }
3648 else if (i.types[op].bitfield.reg16)
3649 {
3650 i.suffix = WORD_MNEM_SUFFIX;
3651 break;
3652 }
3653 else if (i.types[op].bitfield.reg32)
3654 {
3655 i.suffix = LONG_MNEM_SUFFIX;
3656 break;
3657 }
3658 else if (i.types[op].bitfield.reg64)
3659 {
3660 i.suffix = QWORD_MNEM_SUFFIX;
3661 break;
3662 }
381d071f
L		 3663 }
3664 }
29b0f896
AM		 3665 }
3666 else if (i.suffix == BYTE_MNEM_SUFFIX)
3667 {
3668 if (!check_byte_reg ())
3669 return 0;
3670 }
3671 else if (i.suffix == LONG_MNEM_SUFFIX)
3672 {
3673 if (!check_long_reg ())
3674 return 0;
3675 }
3676 else if (i.suffix == QWORD_MNEM_SUFFIX)
3677 {
955e1e6a
L		 3678 if (intel_syntax
3679 && i.tm.opcode_modifier.ignoresize
3680 && i.tm.opcode_modifier.no_qsuf)
3681 i.suffix = 0;
3682 else if (!check_qword_reg ())
29b0f896
AM		 3683 return 0;
3684 }
3685 else if (i.suffix == WORD_MNEM_SUFFIX)
3686 {
3687 if (!check_word_reg ())
3688 return 0;
3689 }
582d5edd
L		 3690 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3691 {
3692 /* Skip if the instruction has x suffix. match_template
3693 should check if it is a valid suffix. */
3694 }
40fb9820 3695 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3696 /* Do nothing if the instruction is going to ignore the prefix. */
3697 ;
3698 else
3699 abort ();
3700 }
40fb9820 3701 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3702 && !i.suffix
3703 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3704 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3705 {
3706 i.suffix = stackop_size;
3707 }
9306ca4a
JB		 3708 else if (intel_syntax
3709 && !i.suffix
40fb9820
L		 3710 && (i.tm.operand_types[0].bitfield.jumpabsolute
3711 || i.tm.opcode_modifier.jumpbyte
3712 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3713 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3714 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3715 {
3716 switch (flag_code)
3717 {
3718 case CODE_64BIT:
40fb9820 3719 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3720 {
3721 i.suffix = QWORD_MNEM_SUFFIX;
3722 break;
3723 }
3724 case CODE_32BIT:
40fb9820 3725 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3726 i.suffix = LONG_MNEM_SUFFIX;
3727 break;
3728 case CODE_16BIT:
40fb9820 3729 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3730 i.suffix = WORD_MNEM_SUFFIX;
3731 break;
3732 }
3733 }
252b5132 3734
9306ca4a 3735 if (!i.suffix)
29b0f896 3736 {
9306ca4a
JB		 3737 if (!intel_syntax)
3738 {
40fb9820 3739 if (i.tm.opcode_modifier.w)
9306ca4a 3740 {
4eed87de
AM		 3741 as_bad (_("no instruction mnemonic suffix given and "
3742 "no register operands; can't size instruction"));
9306ca4a
JB		 3743 return 0;
3744 }
3745 }
3746 else
3747 {
40fb9820
L		 3748 unsigned int suffixes;
3749
3750 suffixes = !i.tm.opcode_modifier.no_bsuf;
3751 if (!i.tm.opcode_modifier.no_wsuf)
3752 suffixes |= 1 << 1;
3753 if (!i.tm.opcode_modifier.no_lsuf)
3754 suffixes |= 1 << 2;
fc4adea1 3755 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3756 suffixes |= 1 << 3;
3757 if (!i.tm.opcode_modifier.no_ssuf)
3758 suffixes |= 1 << 4;
3759 if (!i.tm.opcode_modifier.no_qsuf)
3760 suffixes |= 1 << 5;
3761
3762 /* There are more than suffix matches. */
3763 if (i.tm.opcode_modifier.w
9306ca4a 3764 || ((suffixes & (suffixes - 1))
40fb9820
L		 3765 && !i.tm.opcode_modifier.defaultsize
3766 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3767 {
3768 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3769 return 0;
3770 }
3771 }
29b0f896 3772 }
252b5132 3773
9306ca4a
JB		 3774 /* Change the opcode based on the operand size given by i.suffix;
3775 We don't need to change things for byte insns. */
3776
582d5edd
L		 3777 if (i.suffix
3778 && i.suffix != BYTE_MNEM_SUFFIX
3779 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3780 {
3781 /* It's not a byte, select word/dword operation. */
40fb9820 3782 if (i.tm.opcode_modifier.w)
29b0f896 3783 {
40fb9820 3784 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3785 i.tm.base_opcode |= 8;
3786 else
3787 i.tm.base_opcode |= 1;
3788 }
0f3f3d8b 3789
29b0f896
AM		 3790 /* Now select between word & dword operations via the operand
3791 size prefix, except for instructions that will ignore this
3792 prefix anyway. */
ca61edf2 3793 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3794 {
ca61edf2
L		 3795 /* The address size override prefix changes the size of the
3796 first operand. */
40fb9820
L		 3797 if ((flag_code == CODE_32BIT
3798 && i.op->regs[0].reg_type.bitfield.reg16)
3799 || (flag_code != CODE_32BIT
3800 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3801 if (!add_prefix (ADDR_PREFIX_OPCODE))
3802 return 0;
3803 }
3804 else if (i.suffix != QWORD_MNEM_SUFFIX
3805 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3806 && !i.tm.opcode_modifier.ignoresize
3807 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3808 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3809 || (flag_code == CODE_64BIT
40fb9820 3810 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3811 {
3812 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3813
40fb9820 3814 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3815 prefix = ADDR_PREFIX_OPCODE;
252b5132 3816
29b0f896
AM		 3817 if (!add_prefix (prefix))
3818 return 0;
24eab124 3819 }
252b5132 3820
29b0f896
AM		 3821 /* Set mode64 for an operand. */
3822 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3823 && flag_code == CODE_64BIT
40fb9820 3824 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3825 {
3826 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3827 need rex64. cmpxchg8b is also a special case. */
3828 if (! (i.operands == 2
3829 && i.tm.base_opcode == 0x90
3830 && i.tm.extension_opcode == None
0dfbf9d7
L		 3831 && operand_type_equal (&i.types [0], &acc64)
3832 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 3833 && ! (i.operands == 1
3834 && i.tm.base_opcode == 0xfc7
3835 && i.tm.extension_opcode == 1
40fb9820
L		 3836 && !operand_type_check (i.types [0], reg)
3837 && operand_type_check (i.types [0], anymem)))
f6bee062 3838 i.rex |= REX_W;
46e883c5 3839 }
3e73aa7c 3840
29b0f896
AM		 3841 /* Size floating point instruction. */
3842 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3843 if (i.tm.opcode_modifier.floatmf)
543613e9 3844 i.tm.base_opcode ^= 4;
29b0f896 3845 }
7ecd2f8b 3846
29b0f896
AM		 3847 return 1;
3848}
3e73aa7c 3849
29b0f896 3850static int
543613e9 3851check_byte_reg (void)
29b0f896
AM		 3852{
3853 int op;
543613e9 3854
29b0f896
AM		 3855 for (op = i.operands; --op >= 0;)
3856 {
3857 /* If this is an eight bit register, it's OK. If it's the 16 or
3858 32 bit version of an eight bit register, we will just use the
3859 low portion, and that's OK too. */
40fb9820 3860 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3861 continue;
3862
ca61edf2
L		 3863 /* Don't generate this warning if not needed. */
3864 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3865 continue;
3866
9344ff29
L		 3867 /* crc32 doesn't generate this warning. */
3868 if (i.tm.base_opcode == 0xf20f38f0)
3869 continue;
3870
40fb9820
L		 3871 if ((i.types[op].bitfield.reg16
3872 || i.types[op].bitfield.reg32
3873 || i.types[op].bitfield.reg64)
3874 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3875 {
3876 /* Prohibit these changes in the 64bit mode, since the
3877 lowering is more complicated. */
3878 if (flag_code == CODE_64BIT
40fb9820 3879 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3880 {
2ca3ace5
L		 3881 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3882 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3883 i.suffix);
3884 return 0;
3885 }
3886#if REGISTER_WARNINGS
3887 if (!quiet_warnings
40fb9820 3888 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3889 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3890 register_prefix,
40fb9820 3891 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3892 ? REGNAM_AL - REGNAM_AX
3893 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3894 register_prefix,
29b0f896
AM		 3895 i.op[op].regs->reg_name,
3896 i.suffix);
3897#endif
3898 continue;
3899 }
3900 /* Any other register is bad. */
40fb9820
L		 3901 if (i.types[op].bitfield.reg16
3902 || i.types[op].bitfield.reg32
3903 || i.types[op].bitfield.reg64
3904 || i.types[op].bitfield.regmmx
3905 || i.types[op].bitfield.regxmm
3906 || i.types[op].bitfield.sreg2
3907 || i.types[op].bitfield.sreg3
3908 || i.types[op].bitfield.control
3909 || i.types[op].bitfield.debug
3910 || i.types[op].bitfield.test
3911 || i.types[op].bitfield.floatreg
3912 || i.types[op].bitfield.floatacc)
29b0f896 3913 {
a540244d
L		 3914 as_bad (_("`%s%s' not allowed with `%s%c'"),
3915 register_prefix,
29b0f896
AM		 3916 i.op[op].regs->reg_name,
3917 i.tm.name,
3918 i.suffix);
3919 return 0;
3920 }
3921 }
3922 return 1;
3923}
3924
3925static int
e3bb37b5 3926check_long_reg (void)
29b0f896
AM		 3927{
3928 int op;
3929
3930 for (op = i.operands; --op >= 0;)
3931 /* Reject eight bit registers, except where the template requires
3932 them. (eg. movzb) */
40fb9820
L		 3933 if (i.types[op].bitfield.reg8
3934 && (i.tm.operand_types[op].bitfield.reg16
3935 || i.tm.operand_types[op].bitfield.reg32
3936 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3937 {
a540244d
L		 3938 as_bad (_("`%s%s' not allowed with `%s%c'"),
3939 register_prefix,
29b0f896
AM		 3940 i.op[op].regs->reg_name,
3941 i.tm.name,
3942 i.suffix);
3943 return 0;
3944 }
3945 /* Warn if the e prefix on a general reg is missing. */
3946 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3947 && i.types[op].bitfield.reg16
3948 && (i.tm.operand_types[op].bitfield.reg32
3949 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3950 {
3951 /* Prohibit these changes in the 64bit mode, since the
3952 lowering is more complicated. */
3953 if (flag_code == CODE_64BIT)
252b5132 3954 {
2ca3ace5
L		 3955 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3956 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3957 i.suffix);
3958 return 0;
252b5132 3959 }
29b0f896
AM		 3960#if REGISTER_WARNINGS
3961 else
a540244d
L		 3962 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3963 register_prefix,
29b0f896 3964 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3965 register_prefix,
29b0f896
AM		 3966 i.op[op].regs->reg_name,
3967 i.suffix);
3968#endif
252b5132 3969 }
29b0f896 3970 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3971 else if (i.types[op].bitfield.reg64
3972 && (i.tm.operand_types[op].bitfield.reg32
3973 || i.tm.operand_types[op].bitfield.acc))
252b5132 3974 {
34828aad 3975 if (intel_syntax
ca61edf2 3976 && i.tm.opcode_modifier.toqword
40fb9820 3977 && !i.types[0].bitfield.regxmm)
34828aad 3978 {
ca61edf2 3979 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3980 i.suffix = QWORD_MNEM_SUFFIX;
3981 }
3982 else
3983 {
3984 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3985 register_prefix, i.op[op].regs->reg_name,
3986 i.suffix);
3987 return 0;
3988 }
29b0f896
AM		 3989 }
3990 return 1;
3991}
252b5132 3992
29b0f896 3993static int
e3bb37b5 3994check_qword_reg (void)
29b0f896
AM		 3995{
3996 int op;
252b5132 3997
29b0f896
AM		 3998 for (op = i.operands; --op >= 0; )
3999 /* Reject eight bit registers, except where the template requires
4000 them. (eg. movzb) */
40fb9820
L		 4001 if (i.types[op].bitfield.reg8
4002 && (i.tm.operand_types[op].bitfield.reg16
4003 || i.tm.operand_types[op].bitfield.reg32
4004 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4005 {
a540244d
L		 4006 as_bad (_("`%s%s' not allowed with `%s%c'"),
4007 register_prefix,
29b0f896
AM		 4008 i.op[op].regs->reg_name,
4009 i.tm.name,
4010 i.suffix);
4011 return 0;
4012 }
4013 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4014 else if ((i.types[op].bitfield.reg16
4015 || i.types[op].bitfield.reg32)
4016 && (i.tm.operand_types[op].bitfield.reg32
4017 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4018 {
4019 /* Prohibit these changes in the 64bit mode, since the
4020 lowering is more complicated. */
34828aad 4021 if (intel_syntax
ca61edf2 4022 && i.tm.opcode_modifier.todword
40fb9820 4023 && !i.types[0].bitfield.regxmm)
34828aad 4024 {
ca61edf2 4025 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4026 i.suffix = LONG_MNEM_SUFFIX;
4027 }
4028 else
4029 {
4030 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4031 register_prefix, i.op[op].regs->reg_name,
4032 i.suffix);
4033 return 0;
4034 }
252b5132 4035 }
29b0f896
AM		 4036 return 1;
4037}
252b5132 4038
29b0f896 4039static int
e3bb37b5 4040check_word_reg (void)
29b0f896
AM		 4041{
4042 int op;
4043 for (op = i.operands; --op >= 0;)
4044 /* Reject eight bit registers, except where the template requires
4045 them. (eg. movzb) */
40fb9820
L		 4046 if (i.types[op].bitfield.reg8
4047 && (i.tm.operand_types[op].bitfield.reg16
4048 || i.tm.operand_types[op].bitfield.reg32
4049 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4050 {
a540244d
L		 4051 as_bad (_("`%s%s' not allowed with `%s%c'"),
4052 register_prefix,
29b0f896
AM		 4053 i.op[op].regs->reg_name,
4054 i.tm.name,
4055 i.suffix);
4056 return 0;
4057 }
4058 /* Warn if the e prefix on a general reg is present. */
4059 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4060 && i.types[op].bitfield.reg32
4061 && (i.tm.operand_types[op].bitfield.reg16
4062 || i.tm.operand_types[op].bitfield.acc))
252b5132 4063 {
29b0f896
AM		 4064 /* Prohibit these changes in the 64bit mode, since the
4065 lowering is more complicated. */
4066 if (flag_code == CODE_64BIT)
252b5132 4067 {
2ca3ace5
L		 4068 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4069 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4070 i.suffix);
4071 return 0;
252b5132 4072 }
29b0f896
AM		 4073 else
4074#if REGISTER_WARNINGS
a540244d
L		 4075 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4076 register_prefix,
29b0f896 4077 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4078 register_prefix,
29b0f896
AM		 4079 i.op[op].regs->reg_name,
4080 i.suffix);
4081#endif
4082 }
4083 return 1;
4084}
252b5132 4085
29b0f896 4086static int
40fb9820 4087update_imm (unsigned int j)
29b0f896 4088{
40fb9820
L		 4089 i386_operand_type overlap;
4090
c6fb90c8 4091 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4092 if ((overlap.bitfield.imm8
4093 || overlap.bitfield.imm8s
4094 || overlap.bitfield.imm16
4095 || overlap.bitfield.imm32
4096 || overlap.bitfield.imm32s
4097 || overlap.bitfield.imm64)
0dfbf9d7
L		 4098 && !operand_type_equal (&overlap, &imm8)
4099 && !operand_type_equal (&overlap, &imm8s)
4100 && !operand_type_equal (&overlap, &imm16)
4101 && !operand_type_equal (&overlap, &imm32)
4102 && !operand_type_equal (&overlap, &imm32s)
4103 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4104 {
4105 if (i.suffix)
4106 {
40fb9820
L		 4107 i386_operand_type temp;
4108
0dfbf9d7 4109 operand_type_set (&temp, 0);
40fb9820
L		 4110 if (i.suffix == BYTE_MNEM_SUFFIX)
4111 {
4112 temp.bitfield.imm8 = overlap.bitfield.imm8;
4113 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4114 }
4115 else if (i.suffix == WORD_MNEM_SUFFIX)
4116 temp.bitfield.imm16 = overlap.bitfield.imm16;
4117 else if (i.suffix == QWORD_MNEM_SUFFIX)
4118 {
4119 temp.bitfield.imm64 = overlap.bitfield.imm64;
4120 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4121 }
4122 else
4123 temp.bitfield.imm32 = overlap.bitfield.imm32;
4124 overlap = temp;
29b0f896 4125 }
0dfbf9d7
L		 4126 else if (operand_type_equal (&overlap, &imm16_32_32s)
4127 || operand_type_equal (&overlap, &imm16_32)
4128 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4129 {
40fb9820 4130 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4131 overlap = imm16;
40fb9820 4132 else
65da13b5 4133 overlap = imm32s;
29b0f896 4134 }
0dfbf9d7
L		 4135 if (!operand_type_equal (&overlap, &imm8)
4136 && !operand_type_equal (&overlap, &imm8s)
4137 && !operand_type_equal (&overlap, &imm16)
4138 && !operand_type_equal (&overlap, &imm32)
4139 && !operand_type_equal (&overlap, &imm32s)
4140 && !operand_type_equal (&overlap, &imm64))
29b0f896 4141 {
4eed87de
AM		 4142 as_bad (_("no instruction mnemonic suffix given; "
4143 "can't determine immediate size"));
29b0f896
AM		 4144 return 0;
4145 }
4146 }
40fb9820 4147 i.types[j] = overlap;
29b0f896 4148
40fb9820
L		 4149 return 1;
4150}
4151
4152static int
4153finalize_imm (void)
4154{
4155 unsigned int j;
29b0f896 4156
40fb9820
L		 4157 for (j = 0; j < 2; j++)
4158 if (update_imm (j) == 0)
4159 return 0;
4160
c6fb90c8 4161 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4162 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4163
4164 return 1;
4165}
4166
85f10a01
MM		 4167static void
4168process_drex (void)
4169{
5dd15031
JJ		 4170 i.drex.modrm_reg = 0;
4171 i.drex.modrm_regmem = 0;
85f10a01
MM		 4172
4173 /* SSE5 4 operand instructions must have the destination the same as
4174 one of the inputs. Figure out the destination register and cache
4175 it away in the drex field, and remember which fields to use for
4176 the modrm byte. */
4177 if (i.tm.opcode_modifier.drex
4178 && i.tm.opcode_modifier.drexv
4179 && i.operands == 4)
4180 {
4181 i.tm.extension_opcode = None;
4182
4183 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4184 if (i.types[0].bitfield.regxmm != 0
4185 && i.types[1].bitfield.regxmm != 0
4186 && i.types[2].bitfield.regxmm != 0
4187 && i.types[3].bitfield.regxmm != 0
4188 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4189 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4190 {
4191 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4192 operand_type_set (&i.types[0], 0);
4193 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4194 i.reg_operands -= 2;
4195
4196 /* There are two different ways to encode a 4 operand
4197 instruction with all registers that uses OC1 set to
4198 0 or 1. Favor setting OC1 to 0 since this mimics the
4199 actions of other SSE5 assemblers. Use modrm encoding 2
4200 for register/register. Include the high order bit that
4201 is normally stored in the REX byte in the register
4202 field. */
4203 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4204 i.drex.modrm_reg = 2;
4205 i.drex.modrm_regmem = 1;
4206 i.drex.reg = (i.op[3].regs->reg_num
4207 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4208 }
4209
4210 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4211 else if (i.types[0].bitfield.regxmm != 0
4212 && i.types[1].bitfield.regxmm != 0
4213 && (i.types[2].bitfield.regxmm
4214 || operand_type_check (i.types[2], anymem))
4215 && i.types[3].bitfield.regxmm != 0
4216 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4217 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4218 {
4219 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4220 operand_type_set (&i.types[0], 0);
4221 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4222 i.reg_operands -= 2;
4223
4224 /* Specify the modrm encoding for memory addressing. Include
4225 the high order bit that is normally stored in the REX byte
4226 in the register field. */
4227 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4228 i.drex.modrm_reg = 1;
4229 i.drex.modrm_regmem = 2;
4230 i.drex.reg = (i.op[3].regs->reg_num
4231 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4232 }
4233
4234 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4235 else if (i.types[0].bitfield.regxmm != 0
4236 && operand_type_check (i.types[1], anymem) != 0
4237 && i.types[2].bitfield.regxmm != 0
4238 && i.types[3].bitfield.regxmm != 0
4239 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4240 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4241 {
4242 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4243 operand_type_set (&i.types[0], 0);
4244 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4245 i.reg_operands -= 2;
4246
4247 /* Specify the modrm encoding for memory addressing. Include
4248 the high order bit that is normally stored in the REX byte
4249 in the register field. */
4250 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4251 i.drex.modrm_reg = 2;
4252 i.drex.modrm_regmem = 1;
4253 i.drex.reg = (i.op[3].regs->reg_num
4254 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4255 }
4256
4257 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4258 else if (i.types[0].bitfield.regxmm != 0
4259 && i.types[1].bitfield.regxmm != 0
4260 && i.types[2].bitfield.regxmm != 0
4261 && i.types[3].bitfield.regxmm != 0
4262 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4263 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4264 {
4265 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4266 operand_type_set (&i.types[2], 0);
4267 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4268 i.reg_operands -= 2;
4269
4270 /* There are two different ways to encode a 4 operand
4271 instruction with all registers that uses OC1 set to
4272 0 or 1. Favor setting OC1 to 0 since this mimics the
4273 actions of other SSE5 assemblers. Use modrm encoding
4274 2 for register/register. Include the high order bit that
4275 is normally stored in the REX byte in the register
4276 field. */
4277 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4278 i.drex.modrm_reg = 1;
4279 i.drex.modrm_regmem = 0;
4280
4281 /* Remember the register, including the upper bits */
4282 i.drex.reg = (i.op[3].regs->reg_num
4283 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4284 }
4285
4286 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4287 else if (i.types[0].bitfield.regxmm != 0
4288 && (i.types[1].bitfield.regxmm
4289 || operand_type_check (i.types[1], anymem))
4290 && i.types[2].bitfield.regxmm != 0
4291 && i.types[3].bitfield.regxmm != 0
4292 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4293 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4294 {
4295 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4296 operand_type_set (&i.types[2], 0);
4297 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4298 i.reg_operands -= 2;
4299
4300 /* Specify the modrm encoding and remember the register
4301 including the bits normally stored in the REX byte. */
4302 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4303 i.drex.modrm_reg = 0;
4304 i.drex.modrm_regmem = 1;
4305 i.drex.reg = (i.op[3].regs->reg_num
4306 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4307 }
4308
4309 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4310 else if (operand_type_check (i.types[0], anymem) != 0
4311 && i.types[1].bitfield.regxmm != 0
4312 && i.types[2].bitfield.regxmm != 0
4313 && i.types[3].bitfield.regxmm != 0
4314 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4315 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4316 {
4317 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4318 operand_type_set (&i.types[2], 0);
4319 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4320 i.reg_operands -= 2;
4321
4322 /* Specify the modrm encoding and remember the register
4323 including the bits normally stored in the REX byte. */
4324 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4325 i.drex.modrm_reg = 1;
4326 i.drex.modrm_regmem = 0;
4327 i.drex.reg = (i.op[3].regs->reg_num
4328 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4329 }
4330
4331 else
4332 as_bad (_("Incorrect operands for the '%s' instruction"),
4333 i.tm.name);
4334 }
4335
4336 /* SSE5 instructions with the DREX byte where the only memory operand
4337 is in the 2nd argument, and the first and last xmm register must
4338 match, and is encoded in the DREX byte. */
4339 else if (i.tm.opcode_modifier.drex
4340 && !i.tm.opcode_modifier.drexv
4341 && i.operands == 4)
4342 {
4343 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4344 if (i.types[0].bitfield.regxmm != 0
4345 && (i.types[1].bitfield.regxmm
4346 || operand_type_check(i.types[1], anymem))
4347 && i.types[2].bitfield.regxmm != 0
4348 && i.types[3].bitfield.regxmm != 0
4349 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4350 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4351 {
4352 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4353 operand_type_set (&i.types[0], 0);
4354 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4355 i.reg_operands -= 2;
4356
4357 /* Specify the modrm encoding and remember the register
4358 including the high bit normally stored in the REX
4359 byte. */
4360 i.drex.modrm_reg = 2;
4361 i.drex.modrm_regmem = 1;
4362 i.drex.reg = (i.op[3].regs->reg_num
4363 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4364 }
4365
4366 else
4367 as_bad (_("Incorrect operands for the '%s' instruction"),
4368 i.tm.name);
4369 }
4370
4371 /* SSE5 3 operand instructions that the result is a register, being
4372 either operand can be a memory operand, using OC0 to note which
4373 one is the memory. */
4374 else if (i.tm.opcode_modifier.drex
4375 && i.tm.opcode_modifier.drexv
4376 && i.operands == 3)
4377 {
4378 i.tm.extension_opcode = None;
4379
4380 /* Case 1: 3 operand insn, src1 = register. */
4381 if (i.types[0].bitfield.regxmm != 0
4382 && i.types[1].bitfield.regxmm != 0
4383 && i.types[2].bitfield.regxmm != 0)
4384 {
4385 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4386 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4387 i.reg_operands--;
4388
4389 /* Specify the modrm encoding and remember the register
4390 including the high bit normally stored in the REX byte. */
4391 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4392 i.drex.modrm_reg = 1;
4393 i.drex.modrm_regmem = 0;
4394 i.drex.reg = (i.op[2].regs->reg_num
4395 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4396 }
4397
4398 /* Case 2: 3 operand insn, src1 = memory. */
4399 else if (operand_type_check (i.types[0], anymem) != 0
4400 && i.types[1].bitfield.regxmm != 0
4401 && i.types[2].bitfield.regxmm != 0)
4402 {
4403 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4404 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4405 i.reg_operands--;
4406
4407 /* Specify the modrm encoding and remember the register
4408 including the high bit normally stored in the REX
4409 byte. */
4410 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4411 i.drex.modrm_reg = 1;
4412 i.drex.modrm_regmem = 0;
4413 i.drex.reg = (i.op[2].regs->reg_num
4414 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4415 }
4416
4417 /* Case 3: 3 operand insn, src2 = memory. */
4418 else if (i.types[0].bitfield.regxmm != 0
4419 && operand_type_check (i.types[1], anymem) != 0
4420 && i.types[2].bitfield.regxmm != 0)
4421 {
4422 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4423 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4424 i.reg_operands--;
4425
4426 /* Specify the modrm encoding and remember the register
4427 including the high bit normally stored in the REX byte. */
4428 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4429 i.drex.modrm_reg = 0;
4430 i.drex.modrm_regmem = 1;
4431 i.drex.reg = (i.op[2].regs->reg_num
4432 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4433 }
4434
4435 else
4436 as_bad (_("Incorrect operands for the '%s' instruction"),
4437 i.tm.name);
4438 }
4439
4440 /* SSE5 4 operand instructions that are the comparison instructions
4441 where the first operand is the immediate value of the comparison
4442 to be done. */
4443 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4444 {
4445 /* Case 1: 4 operand insn, src1 = reg/memory. */
4446 if (operand_type_check (i.types[0], imm) != 0
4447 && (i.types[1].bitfield.regxmm
4448 || operand_type_check (i.types[1], anymem))
4449 && i.types[2].bitfield.regxmm != 0
4450 && i.types[3].bitfield.regxmm != 0)
4451 {
4452 /* clear the arguments that are stored in drex */
0dfbf9d7 4453 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4454 i.reg_operands--;
4455
4456 /* Specify the modrm encoding and remember the register
4457 including the high bit normally stored in the REX byte. */
4458 i.drex.modrm_reg = 2;
4459 i.drex.modrm_regmem = 1;
4460 i.drex.reg = (i.op[3].regs->reg_num
4461 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4462 }
4463
4464 /* Case 2: 3 operand insn with ImmExt that places the
4465 opcode_extension as an immediate argument. This is used for
4466 all of the varients of comparison that supplies the appropriate
4467 value as part of the instruction. */
4468 else if ((i.types[0].bitfield.regxmm
4469 || operand_type_check (i.types[0], anymem))
4470 && i.types[1].bitfield.regxmm != 0
4471 && i.types[2].bitfield.regxmm != 0
4472 && operand_type_check (i.types[3], imm) != 0)
4473 {
4474 /* clear the arguments that are stored in drex */
0dfbf9d7 4475 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4476 i.reg_operands--;
4477
4478 /* Specify the modrm encoding and remember the register
4479 including the high bit normally stored in the REX byte. */
4480 i.drex.modrm_reg = 1;
4481 i.drex.modrm_regmem = 0;
4482 i.drex.reg = (i.op[2].regs->reg_num
4483 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4484 }
4485
4486 else
4487 as_bad (_("Incorrect operands for the '%s' instruction"),
4488 i.tm.name);
4489 }
4490
4491 else if (i.tm.opcode_modifier.drex
4492 || i.tm.opcode_modifier.drexv
4493 || i.tm.opcode_modifier.drexc)
4494 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4495}
4496
29b0f896 4497static int
e3bb37b5 4498process_operands (void)
29b0f896
AM		 4499{
4500 /* Default segment register this instruction will use for memory
4501 accesses. 0 means unknown. This is only for optimizing out
4502 unnecessary segment overrides. */
4503 const seg_entry *default_seg = 0;
4504
85f10a01
MM		 4505 /* Handle all of the DREX munging that SSE5 needs. */
4506 if (i.tm.opcode_modifier.drex
4507 || i.tm.opcode_modifier.drexv
4508 || i.tm.opcode_modifier.drexc)
4509 process_drex ();
4510
e2ec9d29 4511 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4512 {
9fcfb3d7
L		 4513 unsigned int j;
4514
e2ec9d29 4515 /* The first operand is implicit and must be xmm0. */
0dfbf9d7
L		 4516 assert (i.reg_operands
4517 && operand_type_equal (&i.types[0], &regxmm));
e2ec9d29
L		 4518 if (i.op[0].regs->reg_num != 0)
4519 {
4520 if (intel_syntax)
4521 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4522 i.tm.name, register_prefix);
4523 else
4524 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4525 i.tm.name, register_prefix);
4526 return 0;
4527 }
9fcfb3d7
L		 4528
4529 for (j = 1; j < i.operands; j++)
4530 {
4531 i.op[j - 1] = i.op[j];
4532 i.types[j - 1] = i.types[j];
4533
4534 /* We need to adjust fields in i.tm since they are used by
4535 build_modrm_byte. */
4536 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4537 }
4538
e2ec9d29
L		 4539 i.operands--;
4540 i.reg_operands--;
e2ec9d29
L		 4541 i.tm.operands--;
4542 }
4543 else if (i.tm.opcode_modifier.regkludge)
4544 {
4545 /* The imul $imm, %reg instruction is converted into
4546 imul $imm, %reg, %reg, and the clr %reg instruction
4547 is converted into xor %reg, %reg. */
4548
4549 unsigned int first_reg_op;
4550
4551 if (operand_type_check (i.types[0], reg))
4552 first_reg_op = 0;
4553 else
4554 first_reg_op = 1;
4555 /* Pretend we saw the extra register operand. */
4556 assert (i.reg_operands == 1
4557 && i.op[first_reg_op + 1].regs == 0);
4558 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4559 i.types[first_reg_op + 1] = i.types[first_reg_op];
4560 i.operands++;
4561 i.reg_operands++;
29b0f896
AM		 4562 }
4563
40fb9820 4564 if (i.tm.opcode_modifier.shortform)
29b0f896 4565 {
40fb9820
L		 4566 if (i.types[0].bitfield.sreg2
4567 || i.types[0].bitfield.sreg3)
29b0f896 4568 {
4eed87de
AM		 4569 if (i.tm.base_opcode == POP_SEG_SHORT
4570 && i.op[0].regs->reg_num == 1)
29b0f896 4571 {
4eed87de
AM		 4572 as_bad (_("you can't `pop %%cs'"));
4573 return 0;
29b0f896 4574 }
4eed87de
AM		 4575 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4576 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4577 i.rex |= REX_B;
4eed87de
AM		 4578 }
4579 else
4580 {
85f10a01
MM		 4581 /* The register or float register operand is in operand
4582 0 or 1. */
40fb9820
L		 4583 unsigned int op;
4584
4585 if (i.types[0].bitfield.floatreg
4586 || operand_type_check (i.types[0], reg))
4587 op = 0;
4588 else
4589 op = 1;
4eed87de
AM		 4590 /* Register goes in low 3 bits of opcode. */
4591 i.tm.base_opcode |= i.op[op].regs->reg_num;
4592 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4593 i.rex |= REX_B;
40fb9820 4594 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4595 {
4eed87de
AM		 4596 /* Warn about some common errors, but press on regardless.
4597 The first case can be generated by gcc (<= 2.8.1). */
4598 if (i.operands == 2)
4599 {
4600 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4601 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4602 register_prefix, i.op[1].regs->reg_name,
4603 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4604 }
4605 else
4606 {
4607 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4608 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4609 register_prefix, i.op[0].regs->reg_name);
4eed87de 4610 }
29b0f896
AM		 4611 }
4612 }
4613 }
40fb9820 4614 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4615 {
4616 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4617 must be put into the modrm byte). Now, we make the modrm and
4618 index base bytes based on all the info we've collected. */
29b0f896
AM		 4619
4620 default_seg = build_modrm_byte ();
4621 }
8a2ed489 4622 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4623 {
4624 default_seg = &ds;
4625 }
40fb9820 4626 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4627 {
4628 /* For the string instructions that allow a segment override
4629 on one of their operands, the default segment is ds. */
4630 default_seg = &ds;
4631 }
4632
75178d9d
L		 4633 if (i.tm.base_opcode == 0x8d /* lea */
4634 && i.seg[0]
4635 && !quiet_warnings)
30123838 4636 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4637
4638 /* If a segment was explicitly specified, and the specified segment
4639 is not the default, use an opcode prefix to select it. If we
4640 never figured out what the default segment is, then default_seg
4641 will be zero at this point, and the specified segment prefix will
4642 always be used. */
29b0f896
AM		 4643 if ((i.seg[0]) && (i.seg[0] != default_seg))
4644 {
4645 if (!add_prefix (i.seg[0]->seg_prefix))
4646 return 0;
4647 }
4648 return 1;
4649}
4650
4651static const seg_entry *
e3bb37b5 4652build_modrm_byte (void)
29b0f896
AM		 4653{
4654 const seg_entry *default_seg = 0;
4655
85f10a01
MM		 4656 /* SSE5 4 operand instructions are encoded in such a way that one of
4657 the inputs must match the destination register. Process_drex hides
4658 the 3rd argument in the drex field, so that by the time we get
4659 here, it looks to GAS as if this is a 2 operand instruction. */
4660 if ((i.tm.opcode_modifier.drex
4661 || i.tm.opcode_modifier.drexv
b5016f89 4662 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4663 && i.reg_operands == 2)
4664 {
4665 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4666 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4667
4668 i.rm.reg = reg->reg_num;
4669 i.rm.regmem = regmem->reg_num;
4670 i.rm.mode = 3;
4671 if ((reg->reg_flags & RegRex) != 0)
4672 i.rex |= REX_R;
4673 if ((regmem->reg_flags & RegRex) != 0)
4674 i.rex |= REX_B;
4675 }
4676
29b0f896
AM		 4677 /* i.reg_operands MUST be the number of real register operands;
4678 implicit registers do not count. */
85f10a01 4679 else if (i.reg_operands == 2)
29b0f896
AM		 4680 {
4681 unsigned int source, dest;
cab737b9
L		 4682
4683 switch (i.operands)
4684 {
4685 case 2:
4686 source = 0;
4687 break;
4688 case 3:
c81128dc
L		 4689 /* When there are 3 operands, one of them may be immediate,
4690 which may be the first or the last operand. Otherwise,
4691 the first operand must be shift count register (cl). */
4692 assert (i.imm_operands == 1
4693 || (i.imm_operands == 0
40fb9820
L		 4694 && i.types[0].bitfield.shiftcount));
4695 if (operand_type_check (i.types[0], imm)
4696 || i.types[0].bitfield.shiftcount)
4697 source = 1;
4698 else
4699 source = 0;
cab737b9
L		 4700 break;
4701 case 4:
368d64cc
L		 4702 /* When there are 4 operands, the first two must be 8bit
4703 immediate operands. The source operand will be the 3rd
4704 one. */
cab737b9 4705 assert (i.imm_operands == 2
368d64cc
L		 4706 && i.types[0].bitfield.imm8
4707 && i.types[1].bitfield.imm8);
cab737b9
L		 4708 source = 2;
4709 break;
4710 default:
4711 abort ();
4712 }
4713
29b0f896
AM		 4714 dest = source + 1;
4715
4716 i.rm.mode = 3;
4717 /* One of the register operands will be encoded in the i.tm.reg
4718 field, the other in the combined i.tm.mode and i.tm.regmem
4719 fields. If no form of this instruction supports a memory
4720 destination operand, then we assume the source operand may
4721 sometimes be a memory operand and so we need to store the
4722 destination in the i.rm.reg field. */
40fb9820
L		 4723 if (!i.tm.operand_types[dest].bitfield.regmem
4724 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4725 {
4726 i.rm.reg = i.op[dest].regs->reg_num;
4727 i.rm.regmem = i.op[source].regs->reg_num;
4728 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4729 i.rex |= REX_R;
29b0f896 4730 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4731 i.rex |= REX_B;
29b0f896
AM		 4732 }
4733 else
4734 {
4735 i.rm.reg = i.op[source].regs->reg_num;
4736 i.rm.regmem = i.op[dest].regs->reg_num;
4737 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4738 i.rex |= REX_B;
29b0f896 4739 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4740 i.rex |= REX_R;
29b0f896 4741 }
161a04f6 4742 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4743 {
40fb9820
L		 4744 if (!i.types[0].bitfield.control
4745 && !i.types[1].bitfield.control)
c4a530c5 4746 abort ();
161a04f6 4747 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4748 add_prefix (LOCK_PREFIX_OPCODE);
4749 }
29b0f896
AM		 4750 }
4751 else
4752 { /* If it's not 2 reg operands... */
4753 if (i.mem_operands)
4754 {
4755 unsigned int fake_zero_displacement = 0;
99018f42 4756 unsigned int op;
4eed87de 4757
85f10a01
MM		 4758 /* This has been precalculated for SSE5 instructions
4759 that have a DREX field earlier in process_drex. */
b5016f89
L		 4760 if (i.tm.opcode_modifier.drex
4761 || i.tm.opcode_modifier.drexv
4762 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4763 op = i.drex.modrm_regmem;
4764 else
4765 {
c0209578
L		 4766 for (op = 0; op < i.operands; op++)
4767 if (operand_type_check (i.types[op], anymem))
4768 break;
4769 assert (op < i.operands);
85f10a01 4770 }
29b0f896
AM		 4771
4772 default_seg = &ds;
4773
4774 if (i.base_reg == 0)
4775 {
4776 i.rm.mode = 0;
4777 if (!i.disp_operands)
4778 fake_zero_displacement = 1;
4779 if (i.index_reg == 0)
4780 {
4781 /* Operand is just <disp> */
20f0a1fc 4782 if (flag_code == CODE_64BIT)
29b0f896
AM		 4783 {
4784 /* 64bit mode overwrites the 32bit absolute
4785 addressing by RIP relative addressing and
4786 absolute addressing is encoded by one of the
4787 redundant SIB forms. */
4788 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4789 i.sib.base = NO_BASE_REGISTER;
4790 i.sib.index = NO_INDEX_REGISTER;
fc225355 4791 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4792 ? disp32s : disp32);
20f0a1fc 4793 }
fc225355
L		 4794 else if ((flag_code == CODE_16BIT)
4795 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4796 {
4797 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4798 i.types[op] = disp16;
20f0a1fc
NC		 4799 }
4800 else
4801 {
4802 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4803 i.types[op] = disp32;
29b0f896
AM		 4804 }
4805 }
4806 else /* !i.base_reg && i.index_reg */
4807 {
db51cc60
L		 4808 if (i.index_reg->reg_num == RegEiz
4809 || i.index_reg->reg_num == RegRiz)
4810 i.sib.index = NO_INDEX_REGISTER;
4811 else
4812 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4813 i.sib.base = NO_BASE_REGISTER;
4814 i.sib.scale = i.log2_scale_factor;
4815 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4816 i.types[op].bitfield.disp8 = 0;
4817 i.types[op].bitfield.disp16 = 0;
4818 i.types[op].bitfield.disp64 = 0;
29b0f896 4819 if (flag_code != CODE_64BIT)
40fb9820
L		 4820 {
4821 /* Must be 32 bit */
4822 i.types[op].bitfield.disp32 = 1;
4823 i.types[op].bitfield.disp32s = 0;
4824 }
29b0f896 4825 else
40fb9820
L		 4826 {
4827 i.types[op].bitfield.disp32 = 0;
4828 i.types[op].bitfield.disp32s = 1;
4829 }
29b0f896 4830 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4831 i.rex |= REX_X;
29b0f896
AM		 4832 }
4833 }
4834 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4835 else if (i.base_reg->reg_num == RegRip ||
4836 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4837 {
4838 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4839 i.types[op].bitfield.disp8 = 0;
4840 i.types[op].bitfield.disp16 = 0;
4841 i.types[op].bitfield.disp32 = 0;
4842 i.types[op].bitfield.disp32s = 1;
4843 i.types[op].bitfield.disp64 = 0;
71903a11 4844 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4845 if (! i.disp_operands)
4846 fake_zero_displacement = 1;
29b0f896 4847 }
40fb9820 4848 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4849 {
4850 switch (i.base_reg->reg_num)
4851 {
4852 case 3: /* (%bx) */
4853 if (i.index_reg == 0)
4854 i.rm.regmem = 7;
4855 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4856 i.rm.regmem = i.index_reg->reg_num - 6;
4857 break;
4858 case 5: /* (%bp) */
4859 default_seg = &ss;
4860 if (i.index_reg == 0)
4861 {
4862 i.rm.regmem = 6;
40fb9820 4863 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4864 {
4865 /* fake (%bp) into 0(%bp) */
40fb9820 4866 i.types[op].bitfield.disp8 = 1;
252b5132 4867 fake_zero_displacement = 1;
29b0f896
AM		 4868 }
4869 }
4870 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4871 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4872 break;
4873 default: /* (%si) -> 4 or (%di) -> 5 */
4874 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4875 }
4876 i.rm.mode = mode_from_disp_size (i.types[op]);
4877 }
4878 else /* i.base_reg and 32/64 bit mode */
4879 {
4880 if (flag_code == CODE_64BIT
40fb9820
L		 4881 && operand_type_check (i.types[op], disp))
4882 {
4883 i386_operand_type temp;
0dfbf9d7 4884 operand_type_set (&temp, 0);
40fb9820
L		 4885 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4886 i.types[op] = temp;
4887 if (i.prefix[ADDR_PREFIX] == 0)
4888 i.types[op].bitfield.disp32s = 1;
4889 else
4890 i.types[op].bitfield.disp32 = 1;
4891 }
20f0a1fc 4892
29b0f896
AM		 4893 i.rm.regmem = i.base_reg->reg_num;
4894 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4895 i.rex |= REX_B;
29b0f896
AM		 4896 i.sib.base = i.base_reg->reg_num;
4897 /* x86-64 ignores REX prefix bit here to avoid decoder
4898 complications. */
4899 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4900 {
4901 default_seg = &ss;
4902 if (i.disp_operands == 0)
4903 {
4904 fake_zero_displacement = 1;
40fb9820 4905 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4906 }
4907 }
4908 else if (i.base_reg->reg_num == ESP_REG_NUM)
4909 {
4910 default_seg = &ss;
4911 }
4912 i.sib.scale = i.log2_scale_factor;
4913 if (i.index_reg == 0)
4914 {
4915 /* <disp>(%esp) becomes two byte modrm with no index
4916 register. We've already stored the code for esp
4917 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4918 Any base register besides %esp will not use the
4919 extra modrm byte. */
4920 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4921 }
4922 else
4923 {
db51cc60
L		 4924 if (i.index_reg->reg_num == RegEiz
4925 || i.index_reg->reg_num == RegRiz)
4926 i.sib.index = NO_INDEX_REGISTER;
4927 else
4928 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4929 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4930 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4931 i.rex |= REX_X;
29b0f896 4932 }
67a4f2b7
AO		 4933
4934 if (i.disp_operands
4935 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4936 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4937 i.rm.mode = 0;
4938 else
4939 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4940 }
252b5132 4941
29b0f896
AM		 4942 if (fake_zero_displacement)
4943 {
4944 /* Fakes a zero displacement assuming that i.types[op]
4945 holds the correct displacement size. */
4946 expressionS *exp;
4947
4948 assert (i.op[op].disps == 0);
4949 exp = &disp_expressions[i.disp_operands++];
4950 i.op[op].disps = exp;
4951 exp->X_op = O_constant;
4952 exp->X_add_number = 0;
4953 exp->X_add_symbol = (symbolS *) 0;
4954 exp->X_op_symbol = (symbolS *) 0;
4955 }
4956 }
252b5132 4957
29b0f896
AM		 4958 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4959 (if any) based on i.tm.extension_opcode. Again, we must be
4960 careful to make sure that segment/control/debug/test/MMX
4961 registers are coded into the i.rm.reg field. */
4962 if (i.reg_operands)
4963 {
99018f42
L		 4964 unsigned int op;
4965
85f10a01
MM		 4966 /* This has been precalculated for SSE5 instructions
4967 that have a DREX field earlier in process_drex. */
b5016f89
L		 4968 if (i.tm.opcode_modifier.drex
4969 || i.tm.opcode_modifier.drexv
4970 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4971 {
4972 op = i.drex.modrm_reg;
4973 i.rm.reg = i.op[op].regs->reg_num;
4974 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4975 i.rex |= REX_R;
4976 }
4977 else
4978 {
c0209578
L		 4979 for (op = 0; op < i.operands; op++)
4980 if (i.types[op].bitfield.reg8
4981 || i.types[op].bitfield.reg16
4982 || i.types[op].bitfield.reg32
4983 || i.types[op].bitfield.reg64
4984 || i.types[op].bitfield.regmmx
4985 || i.types[op].bitfield.regxmm
4986 || i.types[op].bitfield.sreg2
4987 || i.types[op].bitfield.sreg3
4988 || i.types[op].bitfield.control
4989 || i.types[op].bitfield.debug
4990 || i.types[op].bitfield.test)
4991 break;
4992
4993 assert (op < i.operands);
99018f42 4994
85f10a01
MM		 4995 /* If there is an extension opcode to put here, the
4996 register number must be put into the regmem field. */
c0209578
L		 4997 if (i.tm.extension_opcode != None)
4998 {
4999 i.rm.regmem = i.op[op].regs->reg_num;
5000 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5001 i.rex |= REX_B;
5002 }
5003 else
5004 {
5005 i.rm.reg = i.op[op].regs->reg_num;
5006 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5007 i.rex |= REX_R;
5008 }
85f10a01 5009 }
252b5132 5010
29b0f896
AM		 5011 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5012 must set it to 3 to indicate this is a register operand
5013 in the regmem field. */
5014 if (!i.mem_operands)
5015 i.rm.mode = 3;
5016 }
252b5132 5017
29b0f896 5018 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5019 if (i.tm.extension_opcode != None
5020 && !(i.tm.opcode_modifier.drex
5021 || i.tm.opcode_modifier.drexv
5022 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5023 i.rm.reg = i.tm.extension_opcode;
5024 }
5025 return default_seg;
5026}
252b5132 5027
29b0f896 5028static void
e3bb37b5 5029output_branch (void)
29b0f896
AM		 5030{
5031 char *p;
5032 int code16;
5033 int prefix;
5034 relax_substateT subtype;
5035 symbolS *sym;
5036 offsetT off;
5037
5038 code16 = 0;
5039 if (flag_code == CODE_16BIT)
5040 code16 = CODE16;
5041
5042 prefix = 0;
5043 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5044 {
29b0f896
AM		 5045 prefix = 1;
5046 i.prefixes -= 1;
5047 code16 ^= CODE16;
252b5132 5048 }
29b0f896
AM		 5049 /* Pentium4 branch hints. */
5050 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5051 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5052 {
29b0f896
AM		 5053 prefix++;
5054 i.prefixes--;
5055 }
5056 if (i.prefix[REX_PREFIX] != 0)
5057 {
5058 prefix++;
5059 i.prefixes--;
2f66722d
AM		 5060 }
5061
29b0f896
AM		 5062 if (i.prefixes != 0 && !intel_syntax)
5063 as_warn (_("skipping prefixes on this instruction"));
5064
5065 /* It's always a symbol; End frag & setup for relax.
5066 Make sure there is enough room in this frag for the largest
5067 instruction we may generate in md_convert_frag. This is 2
5068 bytes for the opcode and room for the prefix and largest
5069 displacement. */
5070 frag_grow (prefix + 2 + 4);
5071 /* Prefix and 1 opcode byte go in fr_fix. */
5072 p = frag_more (prefix + 1);
5073 if (i.prefix[DATA_PREFIX] != 0)
5074 *p++ = DATA_PREFIX_OPCODE;
5075 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5076 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5077 *p++ = i.prefix[SEG_PREFIX];
5078 if (i.prefix[REX_PREFIX] != 0)
5079 *p++ = i.prefix[REX_PREFIX];
5080 *p = i.tm.base_opcode;
5081
5082 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5083 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5084 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5085 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5086 else
5087 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5088 subtype |= code16;
3e73aa7c 5089
29b0f896
AM		 5090 sym = i.op[0].disps->X_add_symbol;
5091 off = i.op[0].disps->X_add_number;
3e73aa7c 5092
29b0f896
AM		 5093 if (i.op[0].disps->X_op != O_constant
5094 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5095 {
29b0f896
AM		 5096 /* Handle complex expressions. */
5097 sym = make_expr_symbol (i.op[0].disps);
5098 off = 0;
5099 }
3e73aa7c 5100
29b0f896
AM		 5101 /* 1 possible extra opcode + 4 byte displacement go in var part.
5102 Pass reloc in fr_var. */
5103 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5104}
3e73aa7c 5105
29b0f896 5106static void
e3bb37b5 5107output_jump (void)
29b0f896
AM		 5108{
5109 char *p;
5110 int size;
3e02c1cc 5111 fixS *fixP;
29b0f896 5112
40fb9820 5113 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5114 {
5115 /* This is a loop or jecxz type instruction. */
5116 size = 1;
5117 if (i.prefix[ADDR_PREFIX] != 0)
5118 {
5119 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5120 i.prefixes -= 1;
5121 }
5122 /* Pentium4 branch hints. */
5123 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5124 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5125 {
5126 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5127 i.prefixes--;
3e73aa7c
JH		 5128 }
5129 }
29b0f896
AM		 5130 else
5131 {
5132 int code16;
3e73aa7c 5133
29b0f896
AM		 5134 code16 = 0;
5135 if (flag_code == CODE_16BIT)
5136 code16 = CODE16;
3e73aa7c 5137
29b0f896
AM		 5138 if (i.prefix[DATA_PREFIX] != 0)
5139 {
5140 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5141 i.prefixes -= 1;
5142 code16 ^= CODE16;
5143 }
252b5132 5144
29b0f896
AM		 5145 size = 4;
5146 if (code16)
5147 size = 2;
5148 }
9fcc94b6 5149
29b0f896
AM		 5150 if (i.prefix[REX_PREFIX] != 0)
5151 {
5152 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5153 i.prefixes -= 1;
5154 }
252b5132 5155
29b0f896
AM		 5156 if (i.prefixes != 0 && !intel_syntax)
5157 as_warn (_("skipping prefixes on this instruction"));
e0890092 5158
29b0f896
AM		 5159 p = frag_more (1 + size);
5160 *p++ = i.tm.base_opcode;
e0890092 5161
3e02c1cc
AM		 5162 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5163 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5164
5165 /* All jumps handled here are signed, but don't use a signed limit
5166 check for 32 and 16 bit jumps as we want to allow wrap around at
5167 4G and 64k respectively. */
5168 if (size == 1)
5169 fixP->fx_signed = 1;
29b0f896 5170}
e0890092 5171
29b0f896 5172static void
e3bb37b5 5173output_interseg_jump (void)
29b0f896
AM		 5174{
5175 char *p;
5176 int size;
5177 int prefix;
5178 int code16;
252b5132 5179
29b0f896
AM		 5180 code16 = 0;
5181 if (flag_code == CODE_16BIT)
5182 code16 = CODE16;
a217f122 5183
29b0f896
AM		 5184 prefix = 0;
5185 if (i.prefix[DATA_PREFIX] != 0)
5186 {
5187 prefix = 1;
5188 i.prefixes -= 1;
5189 code16 ^= CODE16;
5190 }
5191 if (i.prefix[REX_PREFIX] != 0)
5192 {
5193 prefix++;
5194 i.prefixes -= 1;
5195 }
252b5132 5196
29b0f896
AM		 5197 size = 4;
5198 if (code16)
5199 size = 2;
252b5132 5200
29b0f896
AM		 5201 if (i.prefixes != 0 && !intel_syntax)
5202 as_warn (_("skipping prefixes on this instruction"));
252b5132 5203
29b0f896
AM		 5204 /* 1 opcode; 2 segment; offset */
5205 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5206
29b0f896
AM		 5207 if (i.prefix[DATA_PREFIX] != 0)
5208 *p++ = DATA_PREFIX_OPCODE;
252b5132 5209
29b0f896
AM		 5210 if (i.prefix[REX_PREFIX] != 0)
5211 *p++ = i.prefix[REX_PREFIX];
252b5132 5212
29b0f896
AM		 5213 *p++ = i.tm.base_opcode;
5214 if (i.op[1].imms->X_op == O_constant)
5215 {
5216 offsetT n = i.op[1].imms->X_add_number;
252b5132 5217
29b0f896
AM		 5218 if (size == 2
5219 && !fits_in_unsigned_word (n)
5220 && !fits_in_signed_word (n))
5221 {
5222 as_bad (_("16-bit jump out of range"));
5223 return;
5224 }
5225 md_number_to_chars (p, n, size);
5226 }
5227 else
5228 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5229 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5230 if (i.op[0].imms->X_op != O_constant)
5231 as_bad (_("can't handle non absolute segment in `%s'"),
5232 i.tm.name);
5233 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5234}
a217f122 5235
29b0f896 5236static void
e3bb37b5 5237output_insn (void)
29b0f896 5238{
2bbd9c25
JJ		 5239 fragS *insn_start_frag;
5240 offsetT insn_start_off;
5241
29b0f896
AM		 5242 /* Tie dwarf2 debug info to the address at the start of the insn.
5243 We can't do this after the insn has been output as the current
5244 frag may have been closed off. eg. by frag_var. */
5245 dwarf2_emit_insn (0);
5246
2bbd9c25
JJ		 5247 insn_start_frag = frag_now;
5248 insn_start_off = frag_now_fix ();
5249
29b0f896 5250 /* Output jumps. */
40fb9820 5251 if (i.tm.opcode_modifier.jump)
29b0f896 5252 output_branch ();
40fb9820
L		 5253 else if (i.tm.opcode_modifier.jumpbyte
5254 || i.tm.opcode_modifier.jumpdword)
29b0f896 5255 output_jump ();
40fb9820 5256 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5257 output_interseg_jump ();
5258 else
5259 {
5260 /* Output normal instructions here. */
5261 char *p;
5262 unsigned char *q;
47465058 5263 unsigned int j;
331d2d0d 5264 unsigned int prefix;
4dffcebc
L		 5265
5266 switch (i.tm.opcode_length)
bc4bd9ab 5267 {
4dffcebc 5268 case 3:
331d2d0d
L		 5269 if (i.tm.base_opcode & 0xff000000)
5270 {
5271 prefix = (i.tm.base_opcode >> 24) & 0xff;
5272 goto check_prefix;
5273 }
4dffcebc
L		 5274 break;
5275 case 2:
5276 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5277 {
4dffcebc
L		 5278 prefix = (i.tm.base_opcode >> 16) & 0xff;
5279 if (i.tm.cpu_flags.bitfield.cpupadlock)
5280 {
5281check_prefix:
5282 if (prefix != REPE_PREFIX_OPCODE
5283 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5284 add_prefix (prefix);
5285 }
5286 else
bc4bd9ab
MK		 5287 add_prefix (prefix);
5288 }
4dffcebc
L		 5289 break;
5290 case 1:
5291 break;
5292 default:
5293 abort ();
0f10071e 5294 }
252b5132 5295
29b0f896 5296 /* The prefix bytes. */
47465058
L		 5297 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5298 if (*q)
5299 FRAG_APPEND_1_CHAR (*q);
252b5132 5300
29b0f896 5301 /* Now the opcode; be careful about word order here! */
4dffcebc 5302 if (i.tm.opcode_length == 1)
29b0f896
AM		 5303 {
5304 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5305 }
5306 else
5307 {
4dffcebc 5308 switch (i.tm.opcode_length)
331d2d0d 5309 {
4dffcebc 5310 case 3:
331d2d0d
L		 5311 p = frag_more (3);
5312 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5313 break;
5314 case 2:
5315 p = frag_more (2);
5316 break;
5317 default:
5318 abort ();
5319 break;
331d2d0d 5320 }
0f10071e 5321
29b0f896
AM		 5322 /* Put out high byte first: can't use md_number_to_chars! */
5323 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5324 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5325
5326 /* On SSE5, encode the OC1 bit in the DREX field if this
5327 encoding has multiple formats. */
5328 if (i.tm.opcode_modifier.drex
5329 && i.tm.opcode_modifier.drexv
5330 && DREX_OC1 (i.tm.extension_opcode))
5331 *p |= DREX_OC1_MASK;
29b0f896 5332 }
3e73aa7c 5333
29b0f896 5334 /* Now the modrm byte and sib byte (if present). */
40fb9820 5335 if (i.tm.opcode_modifier.modrm)
29b0f896 5336 {
4a3523fa
L		 5337 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5338 | i.rm.reg << 3
5339 | i.rm.mode << 6));
29b0f896
AM		 5340 /* If i.rm.regmem == ESP (4)
5341 && i.rm.mode != (Register mode)
5342 && not 16 bit
5343 ==> need second modrm byte. */
5344 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5345 && i.rm.mode != 3
40fb9820 5346 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5347 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5348 | i.sib.index << 3
5349 | i.sib.scale << 6));
29b0f896 5350 }
3e73aa7c 5351
85f10a01
MM		 5352 /* Write the DREX byte if needed. */
5353 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5354 {
5355 p = frag_more (1);
5356 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5357
5358 /* Encode the OC0 bit if this encoding has multiple
5359 formats. */
5360 if ((i.tm.opcode_modifier.drex
5361 || i.tm.opcode_modifier.drexv)
5362 && DREX_OC0 (i.tm.extension_opcode))
5363 *p |= DREX_OC0_MASK;
5364 }
5365
29b0f896 5366 if (i.disp_operands)
2bbd9c25 5367 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5368
29b0f896 5369 if (i.imm_operands)
2bbd9c25 5370 output_imm (insn_start_frag, insn_start_off);
29b0f896 5371 }
252b5132 5372
29b0f896
AM		 5373#ifdef DEBUG386
5374 if (flag_debug)
5375 {
7b81dfbb 5376 pi ("" /*line*/, &i);
29b0f896
AM		 5377 }
5378#endif /* DEBUG386 */
5379}
252b5132 5380
e205caa7
L		 5381/* Return the size of the displacement operand N. */
5382
5383static int
5384disp_size (unsigned int n)
5385{
5386 int size = 4;
40fb9820
L		 5387 if (i.types[n].bitfield.disp64)
5388 size = 8;
5389 else if (i.types[n].bitfield.disp8)
5390 size = 1;
5391 else if (i.types[n].bitfield.disp16)
5392 size = 2;
e205caa7
L		 5393 return size;
5394}
5395
5396/* Return the size of the immediate operand N. */
5397
5398static int
5399imm_size (unsigned int n)
5400{
5401 int size = 4;
40fb9820
L		 5402 if (i.types[n].bitfield.imm64)
5403 size = 8;
5404 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5405 size = 1;
5406 else if (i.types[n].bitfield.imm16)
5407 size = 2;
e205caa7
L		 5408 return size;
5409}
5410
29b0f896 5411static void
64e74474 5412output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5413{
5414 char *p;
5415 unsigned int n;
252b5132 5416
29b0f896
AM		 5417 for (n = 0; n < i.operands; n++)
5418 {
40fb9820 5419 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5420 {
5421 if (i.op[n].disps->X_op == O_constant)
5422 {
e205caa7 5423 int size = disp_size (n);
29b0f896 5424 offsetT val;
252b5132 5425
29b0f896
AM		 5426 val = offset_in_range (i.op[n].disps->X_add_number,
5427 size);
5428 p = frag_more (size);
5429 md_number_to_chars (p, val, size);
5430 }
5431 else
5432 {
f86103b7 5433 enum bfd_reloc_code_real reloc_type;
e205caa7 5434 int size = disp_size (n);
40fb9820 5435 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5436 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5437
e205caa7 5438 /* We can't have 8 bit displacement here. */
40fb9820 5439 assert (!i.types[n].bitfield.disp8);
e205caa7 5440
29b0f896
AM		 5441 /* The PC relative address is computed relative
5442 to the instruction boundary, so in case immediate
5443 fields follows, we need to adjust the value. */
5444 if (pcrel && i.imm_operands)
5445 {
29b0f896 5446 unsigned int n1;
e205caa7 5447 int sz = 0;
252b5132 5448
29b0f896 5449 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5450 if (operand_type_check (i.types[n1], imm))
252b5132 5451 {
e205caa7
L		 5452 /* Only one immediate is allowed for PC
5453 relative address. */
5454 assert (sz == 0);
5455 sz = imm_size (n1);
5456 i.op[n].disps->X_add_number -= sz;
252b5132 5457 }
29b0f896 5458 /* We should find the immediate. */
e205caa7 5459 assert (sz != 0);
29b0f896 5460 }
520dc8e8 5461
29b0f896 5462 p = frag_more (size);
2bbd9c25 5463 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5464 if (GOT_symbol
2bbd9c25 5465 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5466 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5467 || reloc_type == BFD_RELOC_X86_64_32S
5468 || (reloc_type == BFD_RELOC_64
5469 && object_64bit))
d6ab8113
JB		 5470 && (i.op[n].disps->X_op == O_symbol
5471 || (i.op[n].disps->X_op == O_add
5472 && ((symbol_get_value_expression
5473 (i.op[n].disps->X_op_symbol)->X_op)
5474 == O_subtract))))
5475 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5476 {
5477 offsetT add;
5478
5479 if (insn_start_frag == frag_now)
5480 add = (p - frag_now->fr_literal) - insn_start_off;
5481 else
5482 {
5483 fragS *fr;
5484
5485 add = insn_start_frag->fr_fix - insn_start_off;
5486 for (fr = insn_start_frag->fr_next;
5487 fr && fr != frag_now; fr = fr->fr_next)
5488 add += fr->fr_fix;
5489 add += p - frag_now->fr_literal;
5490 }
5491
4fa24527 5492 if (!object_64bit)
7b81dfbb
AJ		 5493 {
5494 reloc_type = BFD_RELOC_386_GOTPC;
5495 i.op[n].imms->X_add_number += add;
5496 }
5497 else if (reloc_type == BFD_RELOC_64)
5498 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5499 else
7b81dfbb
AJ		 5500 /* Don't do the adjustment for x86-64, as there
5501 the pcrel addressing is relative to the _next_
5502 insn, and that is taken care of in other code. */
d6ab8113 5503 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5504 }
062cd5e7 5505 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5506 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5507 }
5508 }
5509 }
5510}
252b5132 5511
29b0f896 5512static void
64e74474 5513output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5514{
5515 char *p;
5516 unsigned int n;
252b5132 5517
29b0f896
AM		 5518 for (n = 0; n < i.operands; n++)
5519 {
40fb9820 5520 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5521 {
5522 if (i.op[n].imms->X_op == O_constant)
5523 {
e205caa7 5524 int size = imm_size (n);
29b0f896 5525 offsetT val;
b4cac588 5526
29b0f896
AM		 5527 val = offset_in_range (i.op[n].imms->X_add_number,
5528 size);
5529 p = frag_more (size);
5530 md_number_to_chars (p, val, size);
5531 }
5532 else
5533 {
5534 /* Not absolute_section.
5535 Need a 32-bit fixup (don't support 8bit
5536 non-absolute imms). Try to support other
5537 sizes ... */
f86103b7 5538 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5539 int size = imm_size (n);
5540 int sign;
29b0f896 5541
40fb9820 5542 if (i.types[n].bitfield.imm32s
a7d61044 5543 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5544 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5545 sign = 1;
e205caa7
L		 5546 else
5547 sign = 0;
520dc8e8 5548
29b0f896
AM		 5549 p = frag_more (size);
5550 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5551
2bbd9c25
JJ		 5552 /* This is tough to explain. We end up with this one if we
5553 * have operands that look like
5554 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5555 * obtain the absolute address of the GOT, and it is strongly
5556 * preferable from a performance point of view to avoid using
5557 * a runtime relocation for this. The actual sequence of
5558 * instructions often look something like:
5559 *
5560 * call .L66
5561 * .L66:
5562 * popl %ebx
5563 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5564 *
5565 * The call and pop essentially return the absolute address
5566 * of the label .L66 and store it in %ebx. The linker itself
5567 * will ultimately change the first operand of the addl so
5568 * that %ebx points to the GOT, but to keep things simple, the
5569 * .o file must have this operand set so that it generates not
5570 * the absolute address of .L66, but the absolute address of
5571 * itself. This allows the linker itself simply treat a GOTPC
5572 * relocation as asking for a pcrel offset to the GOT to be
5573 * added in, and the addend of the relocation is stored in the
5574 * operand field for the instruction itself.
5575 *
5576 * Our job here is to fix the operand so that it would add
5577 * the correct offset so that %ebx would point to itself. The
5578 * thing that is tricky is that .-.L66 will point to the
5579 * beginning of the instruction, so we need to further modify
5580 * the operand so that it will point to itself. There are
5581 * other cases where you have something like:
5582 *
5583 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5584 *
5585 * and here no correction would be required. Internally in
5586 * the assembler we treat operands of this form as not being
5587 * pcrel since the '.' is explicitly mentioned, and I wonder
5588 * whether it would simplify matters to do it this way. Who
5589 * knows. In earlier versions of the PIC patches, the
5590 * pcrel_adjust field was used to store the correction, but
5591 * since the expression is not pcrel, I felt it would be
5592 * confusing to do it this way. */
5593
d6ab8113 5594 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5595 || reloc_type == BFD_RELOC_X86_64_32S
5596 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5597 && GOT_symbol
5598 && GOT_symbol == i.op[n].imms->X_add_symbol
5599 && (i.op[n].imms->X_op == O_symbol
5600 || (i.op[n].imms->X_op == O_add
5601 && ((symbol_get_value_expression
5602 (i.op[n].imms->X_op_symbol)->X_op)
5603 == O_subtract))))
5604 {
2bbd9c25
JJ		 5605 offsetT add;
5606
5607 if (insn_start_frag == frag_now)
5608 add = (p - frag_now->fr_literal) - insn_start_off;
5609 else
5610 {
5611 fragS *fr;
5612
5613 add = insn_start_frag->fr_fix - insn_start_off;
5614 for (fr = insn_start_frag->fr_next;
5615 fr && fr != frag_now; fr = fr->fr_next)
5616 add += fr->fr_fix;
5617 add += p - frag_now->fr_literal;
5618 }
5619
4fa24527 5620 if (!object_64bit)
d6ab8113 5621 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5622 else if (size == 4)
d6ab8113 5623 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5624 else if (size == 8)
5625 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5626 i.op[n].imms->X_add_number += add;
29b0f896 5627 }
29b0f896
AM		 5628 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5629 i.op[n].imms, 0, reloc_type);
5630 }
5631 }
5632 }
252b5132
RH		 5633}
5634\f
d182319b
JB		 5635/* x86_cons_fix_new is called via the expression parsing code when a
5636 reloc is needed. We use this hook to get the correct .got reloc. */
5637static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5638static int cons_sign = -1;
5639
5640void
e3bb37b5 5641x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5642 expressionS *exp)
d182319b
JB		 5643{
5644 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5645
5646 got_reloc = NO_RELOC;
5647
5648#ifdef TE_PE
5649 if (exp->X_op == O_secrel)
5650 {
5651 exp->X_op = O_symbol;
5652 r = BFD_RELOC_32_SECREL;
5653 }
5654#endif
5655
5656 fix_new_exp (frag, off, len, exp, 0, r);
5657}
5658
718ddfc0
JB		 5659#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5660# define lex_got(reloc, adjust, types) NULL
5661#else
f3c180ae
AM		 5662/* Parse operands of the form
5663 <symbol>@GOTOFF+<nnn>
5664 and similar .plt or .got references.
5665
5666 If we find one, set up the correct relocation in RELOC and copy the
5667 input string, minus the `@GOTOFF' into a malloc'd buffer for
5668 parsing by the calling routine. Return this buffer, and if ADJUST
5669 is non-null set it to the length of the string we removed from the
5670 input line. Otherwise return NULL. */
5671static char *
3956db08 5672lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5673 int *adjust,
40fb9820 5674 i386_operand_type *types)
f3c180ae 5675{
7b81dfbb
AJ		 5676 /* Some of the relocations depend on the size of what field is to
5677 be relocated. But in our callers i386_immediate and i386_displacement
5678 we don't yet know the operand size (this will be set by insn
5679 matching). Hence we record the word32 relocation here,
5680 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5681 static const struct {
5682 const char *str;
4fa24527 5683 const enum bfd_reloc_code_real rel[2];
40fb9820 5684 const i386_operand_type types64;
f3c180ae 5685 } gotrel[] = {
4eed87de
AM		 5686 { "PLTOFF", { 0,
5687 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5688 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5689 { "PLT", { BFD_RELOC_386_PLT32,
5690 BFD_RELOC_X86_64_PLT32 },
40fb9820 5691 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5692 { "GOTPLT", { 0,
5693 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5694 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5695 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5696 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5697 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5698 { "GOTPCREL", { 0,
5699 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5700 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5701 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5702 BFD_RELOC_X86_64_TLSGD },
40fb9820 5703 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5704 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5705 0 },
40fb9820 5706 OPERAND_TYPE_NONE },
4eed87de
AM		 5707 { "TLSLD", { 0,
5708 BFD_RELOC_X86_64_TLSLD },
40fb9820 5709 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5710 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5711 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5712 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5713 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5714 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5715 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5716 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5717 0 },
40fb9820 5718 OPERAND_TYPE_NONE },
4eed87de
AM		 5719 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5720 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5721
5722 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5723 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5724 0 },
40fb9820 5725 OPERAND_TYPE_NONE },
4eed87de
AM		 5726 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5727 0 },
40fb9820 5728 OPERAND_TYPE_NONE },
4eed87de
AM		 5729 { "GOT", { BFD_RELOC_386_GOT32,
5730 BFD_RELOC_X86_64_GOT32 },
40fb9820 5731 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5732 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5733 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5734 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5735 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5736 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5737 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5738 };
5739 char *cp;
5740 unsigned int j;
5741
718ddfc0
JB		 5742 if (!IS_ELF)
5743 return NULL;
5744
f3c180ae 5745 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5746 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5747 return NULL;
5748
47465058 5749 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5750 {
5751 int len;
5752
5753 len = strlen (gotrel[j].str);
28f81592 5754 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5755 {
4fa24527 5756 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5757 {
28f81592
AM		 5758 int first, second;
5759 char *tmpbuf, *past_reloc;
f3c180ae 5760
4fa24527 5761 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5762 if (adjust)
5763 *adjust = len;
f3c180ae 5764
3956db08
JB		 5765 if (types)
5766 {
5767 if (flag_code != CODE_64BIT)
40fb9820
L		 5768 {
5769 types->bitfield.imm32 = 1;
5770 types->bitfield.disp32 = 1;
5771 }
3956db08
JB		 5772 else
5773 *types = gotrel[j].types64;
5774 }
5775
f3c180ae
AM		 5776 if (GOT_symbol == NULL)
5777 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5778
28f81592 5779 /* The length of the first part of our input line. */
f3c180ae 5780 first = cp - input_line_pointer;
28f81592
AM		 5781
5782 /* The second part goes from after the reloc token until
67c11a9b 5783 (and including) an end_of_line char or comma. */
28f81592 5784 past_reloc = cp + 1 + len;
67c11a9b
AM		 5785 cp = past_reloc;
5786 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5787 ++cp;
5788 second = cp + 1 - past_reloc;
28f81592
AM		 5789
5790 /* Allocate and copy string. The trailing NUL shouldn't
5791 be necessary, but be safe. */
5792 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5793 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5794 if (second != 0 && *past_reloc != ' ')
5795 /* Replace the relocation token with ' ', so that
5796 errors like foo@GOTOFF1 will be detected. */
5797 tmpbuf[first++] = ' ';
5798 memcpy (tmpbuf + first, past_reloc, second);
5799 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5800 return tmpbuf;
5801 }
5802
4fa24527
JB		 5803 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5804 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5805 return NULL;
5806 }
5807 }
5808
5809 /* Might be a symbol version string. Don't as_bad here. */
5810 return NULL;
5811}
5812
f3c180ae 5813void
e3bb37b5 5814x86_cons (expressionS *exp, int size)
f3c180ae 5815{
4fa24527 5816 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5817 {
5818 /* Handle @GOTOFF and the like in an expression. */
5819 char *save;
5820 char *gotfree_input_line;
5821 int adjust;
5822
5823 save = input_line_pointer;
3956db08 5824 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5825 if (gotfree_input_line)
5826 input_line_pointer = gotfree_input_line;
5827
5828 expression (exp);
5829
5830 if (gotfree_input_line)
5831 {
5832 /* expression () has merrily parsed up to the end of line,
5833 or a comma - in the wrong buffer. Transfer how far
5834 input_line_pointer has moved to the right buffer. */
5835 input_line_pointer = (save
5836 + (input_line_pointer - gotfree_input_line)
5837 + adjust);
5838 free (gotfree_input_line);
3992d3b7
AM		 5839 if (exp->X_op == O_constant
5840 || exp->X_op == O_absent
5841 || exp->X_op == O_illegal
5842 || exp->X_op == O_register
5843 || exp->X_op == O_big)
5844 {
5845 char c = *input_line_pointer;
5846 *input_line_pointer = 0;
5847 as_bad (_("missing or invalid expression `%s'"), save);
5848 *input_line_pointer = c;
5849 }
f3c180ae
AM		 5850 }
5851 }
5852 else
5853 expression (exp);
5854}
5855#endif
5856
d182319b 5857static void signed_cons (int size)
6482c264 5858{
d182319b
JB		 5859 if (flag_code == CODE_64BIT)
5860 cons_sign = 1;
5861 cons (size);
5862 cons_sign = -1;
6482c264
NC		 5863}
5864
d182319b 5865#ifdef TE_PE
6482c264
NC		 5866static void
5867pe_directive_secrel (dummy)
5868 int dummy ATTRIBUTE_UNUSED;
5869{
5870 expressionS exp;
5871
5872 do
5873 {
5874 expression (&exp);
5875 if (exp.X_op == O_symbol)
5876 exp.X_op = O_secrel;
5877
5878 emit_expr (&exp, 4);
5879 }
5880 while (*input_line_pointer++ == ',');
5881
5882 input_line_pointer--;
5883 demand_empty_rest_of_line ();
5884}
6482c264
NC		 5885#endif
5886
252b5132 5887static int
70e41ade 5888i386_immediate (char *imm_start)
252b5132
RH		 5889{
5890 char *save_input_line_pointer;
f3c180ae 5891 char *gotfree_input_line;
252b5132 5892 segT exp_seg = 0;
47926f60 5893 expressionS *exp;
40fb9820
L		 5894 i386_operand_type types;
5895
0dfbf9d7 5896 operand_type_set (&types, ~0);
252b5132
RH		 5897
5898 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5899 {
31b2323c
L		 5900 as_bad (_("at most %d immediate operands are allowed"),
5901 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5902 return 0;
5903 }
5904
5905 exp = &im_expressions[i.imm_operands++];
520dc8e8 5906 i.op[this_operand].imms = exp;
252b5132
RH		 5907
5908 if (is_space_char (*imm_start))
5909 ++imm_start;
5910
5911 save_input_line_pointer = input_line_pointer;
5912 input_line_pointer = imm_start;
5913
3956db08 5914 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5915 if (gotfree_input_line)
5916 input_line_pointer = gotfree_input_line;
252b5132
RH		 5917
5918 exp_seg = expression (exp);
5919
83183c0c 5920 SKIP_WHITESPACE ();
252b5132 5921 if (*input_line_pointer)
f3c180ae 5922 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5923
5924 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5925 if (gotfree_input_line)
5926 free (gotfree_input_line);
252b5132 5927
3992d3b7
AM		 5928 if (exp->X_op == O_absent
5929 || exp->X_op == O_illegal
5930 || exp->X_op == O_big
5931 || (gotfree_input_line
5932 && (exp->X_op == O_constant
5933 || exp->X_op == O_register)))
252b5132 5934 {
3992d3b7 5935 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5936 imm_start);
3992d3b7 5937 return 0;
252b5132 5938 }
3e73aa7c 5939 else if (exp->X_op == O_constant)
252b5132 5940 {
47926f60 5941 /* Size it properly later. */
40fb9820 5942 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5943 /* If BFD64, sign extend val. */
4eed87de
AM		 5944 if (!use_rela_relocations
5945 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5946 exp->X_add_number
5947 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5948 }
4c63da97 5949#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5950 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5951 && exp_seg != absolute_section
47926f60 5952 && exp_seg != text_section
24eab124
AM		 5953 && exp_seg != data_section
5954 && exp_seg != bss_section
5955 && exp_seg != undefined_section
f86103b7 5956 && !bfd_is_com_section (exp_seg))
252b5132 5957 {
d0b47220 5958 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5959 return 0;
5960 }
5961#endif
bb8f5920
L		 5962 else if (!intel_syntax && exp->X_op == O_register)
5963 {
5964 as_bad (_("illegal immediate register operand %s"), imm_start);
5965 return 0;
5966 }
252b5132
RH		 5967 else
5968 {
5969 /* This is an address. The size of the address will be
24eab124 5970 determined later, depending on destination register,
3e73aa7c 5971 suffix, or the default for the section. */
40fb9820
L		 5972 i.types[this_operand].bitfield.imm8 = 1;
5973 i.types[this_operand].bitfield.imm16 = 1;
5974 i.types[this_operand].bitfield.imm32 = 1;
5975 i.types[this_operand].bitfield.imm32s = 1;
5976 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5977 i.types[this_operand] = operand_type_and (i.types[this_operand],
5978 types);
252b5132
RH		 5979 }
5980
5981 return 1;
5982}
5983
551c1ca1 5984static char *
e3bb37b5 5985i386_scale (char *scale)
252b5132 5986{
551c1ca1
AM		 5987 offsetT val;
5988 char *save = input_line_pointer;
252b5132 5989
551c1ca1
AM		 5990 input_line_pointer = scale;
5991 val = get_absolute_expression ();
5992
5993 switch (val)
252b5132 5994 {
551c1ca1 5995 case 1:
252b5132
RH		 5996 i.log2_scale_factor = 0;
5997 break;
551c1ca1 5998 case 2:
252b5132
RH		 5999 i.log2_scale_factor = 1;
6000 break;
551c1ca1 6001 case 4:
252b5132
RH		 6002 i.log2_scale_factor = 2;
6003 break;
551c1ca1 6004 case 8:
252b5132
RH		 6005 i.log2_scale_factor = 3;
6006 break;
6007 default:
a724f0f4
JB		 6008 {
6009 char sep = *input_line_pointer;
6010
6011 *input_line_pointer = '\0';
6012 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6013 scale);
6014 *input_line_pointer = sep;
6015 input_line_pointer = save;
6016 return NULL;
6017 }
252b5132 6018 }
29b0f896 6019 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6020 {
6021 as_warn (_("scale factor of %d without an index register"),
24eab124 6022 1 << i.log2_scale_factor);
252b5132 6023 i.log2_scale_factor = 0;
252b5132 6024 }
551c1ca1
AM		 6025 scale = input_line_pointer;
6026 input_line_pointer = save;
6027 return scale;
252b5132
RH		 6028}
6029
252b5132 6030static int
e3bb37b5 6031i386_displacement (char *disp_start, char *disp_end)
252b5132 6032{
29b0f896 6033 expressionS *exp;
252b5132
RH		 6034 segT exp_seg = 0;
6035 char *save_input_line_pointer;
f3c180ae 6036 char *gotfree_input_line;
40fb9820
L		 6037 int override;
6038 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6039 int ret;
252b5132 6040
31b2323c
L		 6041 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6042 {
6043 as_bad (_("at most %d displacement operands are allowed"),
6044 MAX_MEMORY_OPERANDS);
6045 return 0;
6046 }
6047
0dfbf9d7 6048 operand_type_set (&bigdisp, 0);
40fb9820
L		 6049 if ((i.types[this_operand].bitfield.jumpabsolute)
6050 || (!current_templates->start->opcode_modifier.jump
6051 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6052 {
40fb9820 6053 bigdisp.bitfield.disp32 = 1;
e05278af 6054 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6055 if (flag_code == CODE_64BIT)
6056 {
6057 if (!override)
6058 {
6059 bigdisp.bitfield.disp32s = 1;
6060 bigdisp.bitfield.disp64 = 1;
6061 }
6062 }
6063 else if ((flag_code == CODE_16BIT) ^ override)
6064 {
6065 bigdisp.bitfield.disp32 = 0;
6066 bigdisp.bitfield.disp16 = 1;
6067 }
e05278af
JB		 6068 }
6069 else
6070 {
6071 /* For PC-relative branches, the width of the displacement
6072 is dependent upon data size, not address size. */
e05278af 6073 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6074 if (flag_code == CODE_64BIT)
6075 {
6076 if (override || i.suffix == WORD_MNEM_SUFFIX)
6077 bigdisp.bitfield.disp16 = 1;
6078 else
6079 {
6080 bigdisp.bitfield.disp32 = 1;
6081 bigdisp.bitfield.disp32s = 1;
6082 }
6083 }
6084 else
e05278af
JB		 6085 {
6086 if (!override)
6087 override = (i.suffix == (flag_code != CODE_16BIT
6088 ? WORD_MNEM_SUFFIX
6089 : LONG_MNEM_SUFFIX));
40fb9820
L		 6090 bigdisp.bitfield.disp32 = 1;
6091 if ((flag_code == CODE_16BIT) ^ override)
6092 {
6093 bigdisp.bitfield.disp32 = 0;
6094 bigdisp.bitfield.disp16 = 1;
6095 }
e05278af 6096 }
e05278af 6097 }
c6fb90c8
L		 6098 i.types[this_operand] = operand_type_or (i.types[this_operand],
6099 bigdisp);
252b5132
RH		 6100
6101 exp = &disp_expressions[i.disp_operands];
520dc8e8 6102 i.op[this_operand].disps = exp;
252b5132
RH		 6103 i.disp_operands++;
6104 save_input_line_pointer = input_line_pointer;
6105 input_line_pointer = disp_start;
6106 END_STRING_AND_SAVE (disp_end);
6107
6108#ifndef GCC_ASM_O_HACK
6109#define GCC_ASM_O_HACK 0
6110#endif
6111#if GCC_ASM_O_HACK
6112 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6113 if (i.types[this_operand].bitfield.baseIndex
24eab124 6114 && displacement_string_end[-1] == '+')
252b5132
RH		 6115 {
6116 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6117 constraint within gcc asm statements.
6118 For instance:
6119
6120 #define _set_tssldt_desc(n,addr,limit,type) \
6121 __asm__ __volatile__ ( \
6122 "movw %w2,%0\n\t" \
6123 "movw %w1,2+%0\n\t" \
6124 "rorl $16,%1\n\t" \
6125 "movb %b1,4+%0\n\t" \
6126 "movb %4,5+%0\n\t" \
6127 "movb $0,6+%0\n\t" \
6128 "movb %h1,7+%0\n\t" \
6129 "rorl $16,%1" \
6130 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6131
6132 This works great except that the output assembler ends
6133 up looking a bit weird if it turns out that there is
6134 no offset. You end up producing code that looks like:
6135
6136 #APP
6137 movw $235,(%eax)
6138 movw %dx,2+(%eax)
6139 rorl $16,%edx
6140 movb %dl,4+(%eax)
6141 movb $137,5+(%eax)
6142 movb $0,6+(%eax)
6143 movb %dh,7+(%eax)
6144 rorl $16,%edx
6145 #NO_APP
6146
47926f60 6147 So here we provide the missing zero. */
24eab124
AM		 6148
6149 *displacement_string_end = '0';
252b5132
RH		 6150 }
6151#endif
3956db08 6152 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6153 if (gotfree_input_line)
6154 input_line_pointer = gotfree_input_line;
252b5132 6155
24eab124 6156 exp_seg = expression (exp);
252b5132 6157
636c26b0
AM		 6158 SKIP_WHITESPACE ();
6159 if (*input_line_pointer)
6160 as_bad (_("junk `%s' after expression"), input_line_pointer);
6161#if GCC_ASM_O_HACK
6162 RESTORE_END_STRING (disp_end + 1);
6163#endif
636c26b0 6164 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6165 if (gotfree_input_line)
6166 free (gotfree_input_line);
3992d3b7 6167 ret = 1;
636c26b0 6168
24eab124
AM		 6169 /* We do this to make sure that the section symbol is in
6170 the symbol table. We will ultimately change the relocation
47926f60 6171 to be relative to the beginning of the section. */
1ae12ab7 6172 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6173 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6174 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6175 {
636c26b0 6176 if (exp->X_op != O_symbol)
3992d3b7 6177 goto inv_disp;
636c26b0 6178
e5cb08ac 6179 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6180 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6181 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6182 exp->X_op = O_subtract;
6183 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6184 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6185 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6186 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6187 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6188 else
29b0f896 6189 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6190 }
252b5132 6191
3992d3b7
AM		 6192 else if (exp->X_op == O_absent
6193 || exp->X_op == O_illegal
6194 || exp->X_op == O_big
6195 || (gotfree_input_line
6196 && (exp->X_op == O_constant
6197 || exp->X_op == O_register)))
2daf4fd8 6198 {
3992d3b7
AM		 6199 inv_disp:
6200 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6201 disp_start);
3992d3b7 6202 ret = 0;
2daf4fd8
AM		 6203 }
6204
4c63da97 6205#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6206 else if (exp->X_op != O_constant
6207 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6208 && exp_seg != absolute_section
6209 && exp_seg != text_section
6210 && exp_seg != data_section
6211 && exp_seg != bss_section
6212 && exp_seg != undefined_section
6213 && !bfd_is_com_section (exp_seg))
24eab124 6214 {
d0b47220 6215 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6216 ret = 0;
24eab124 6217 }
252b5132 6218#endif
3956db08 6219
3992d3b7
AM		 6220 RESTORE_END_STRING (disp_end);
6221
40fb9820
L		 6222 /* Check if this is a displacement only operand. */
6223 bigdisp = i.types[this_operand];
6224 bigdisp.bitfield.disp8 = 0;
6225 bigdisp.bitfield.disp16 = 0;
6226 bigdisp.bitfield.disp32 = 0;
6227 bigdisp.bitfield.disp32s = 0;
6228 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6229 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6230 i.types[this_operand] = operand_type_and (i.types[this_operand],
6231 types);
3956db08 6232
3992d3b7 6233 return ret;
252b5132
RH		 6234}
6235
eecb386c 6236/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6237 Return 1 on success, 0 on a failure. */
6238
252b5132 6239static int
e3bb37b5 6240i386_index_check (const char *operand_string)
252b5132 6241{
3e73aa7c 6242 int ok;
24eab124 6243#if INFER_ADDR_PREFIX
eecb386c
AM		 6244 int fudged = 0;
6245
24eab124
AM		 6246 tryprefix:
6247#endif
3e73aa7c 6248 ok = 1;
75178d9d 6249 if (flag_code == CODE_64BIT)
64e74474 6250 {
64e74474 6251 if ((i.base_reg
40fb9820
L		 6252 && ((i.prefix[ADDR_PREFIX] == 0
6253 && !i.base_reg->reg_type.bitfield.reg64)
6254 || (i.prefix[ADDR_PREFIX]
6255 && !i.base_reg->reg_type.bitfield.reg32))
6256 && (i.index_reg
9a04903e
JB		 6257 || i.base_reg->reg_num !=
6258 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6259 || (i.index_reg
40fb9820
L		 6260 && (!i.index_reg->reg_type.bitfield.baseindex
6261 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6262 && i.index_reg->reg_num != RegRiz
6263 && !i.index_reg->reg_type.bitfield.reg64
6264 )
40fb9820 6265 || (i.prefix[ADDR_PREFIX]
db51cc60 6266 && i.index_reg->reg_num != RegEiz
40fb9820 6267 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6268 ok = 0;
3e73aa7c
JH		 6269 }
6270 else
6271 {
6272 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6273 {
6274 /* 16bit checks. */
6275 if ((i.base_reg
40fb9820
L		 6276 && (!i.base_reg->reg_type.bitfield.reg16
6277 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6278 || (i.index_reg
40fb9820
L		 6279 && (!i.index_reg->reg_type.bitfield.reg16
6280 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6281 || !(i.base_reg
6282 && i.base_reg->reg_num < 6
6283 && i.index_reg->reg_num >= 6
6284 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6285 ok = 0;
6286 }
6287 else
e5cb08ac 6288 {
3e73aa7c
JH		 6289 /* 32bit checks. */
6290 if ((i.base_reg
40fb9820 6291 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6292 || (i.index_reg
db51cc60
L		 6293 && ((!i.index_reg->reg_type.bitfield.reg32
6294 && i.index_reg->reg_num != RegEiz)
40fb9820 6295 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6296 ok = 0;
3e73aa7c
JH		 6297 }
6298 }
6299 if (!ok)
24eab124
AM		 6300 {
6301#if INFER_ADDR_PREFIX
20f0a1fc 6302 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6303 {
6304 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6305 i.prefixes += 1;
b23bac36
AM		 6306 /* Change the size of any displacement too. At most one of
6307 Disp16 or Disp32 is set.
6308 FIXME. There doesn't seem to be any real need for separate
6309 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6310 Removing them would probably clean up the code quite a lot. */
4eed87de 6311 if (flag_code != CODE_64BIT
40fb9820
L		 6312 && (i.types[this_operand].bitfield.disp16
6313 || i.types[this_operand].bitfield.disp32))
6314 i.types[this_operand]
c6fb90c8 6315 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6316 fudged = 1;
24eab124
AM		 6317 goto tryprefix;
6318 }
eecb386c
AM		 6319 if (fudged)
6320 as_bad (_("`%s' is not a valid base/index expression"),
6321 operand_string);
6322 else
c388dee8 6323#endif
eecb386c
AM		 6324 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6325 operand_string,
3e73aa7c 6326 flag_code_names[flag_code]);
24eab124 6327 }
20f0a1fc 6328 return ok;
24eab124 6329}
252b5132 6330
252b5132 6331/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6332 on error. */
252b5132 6333
252b5132 6334static int
a7619375 6335i386_att_operand (char *operand_string)
252b5132 6336{
af6bdddf
AM		 6337 const reg_entry *r;
6338 char *end_op;
24eab124 6339 char *op_string = operand_string;
252b5132 6340
24eab124 6341 if (is_space_char (*op_string))
252b5132
RH		 6342 ++op_string;
6343
24eab124 6344 /* We check for an absolute prefix (differentiating,
47926f60 6345 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6346 if (*op_string == ABSOLUTE_PREFIX)
6347 {
6348 ++op_string;
6349 if (is_space_char (*op_string))
6350 ++op_string;
40fb9820 6351 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6352 }
252b5132 6353
47926f60 6354 /* Check if operand is a register. */
4d1bb795 6355 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6356 {
40fb9820
L		 6357 i386_operand_type temp;
6358
24eab124
AM		 6359 /* Check for a segment override by searching for ':' after a
6360 segment register. */
6361 op_string = end_op;
6362 if (is_space_char (*op_string))
6363 ++op_string;
40fb9820
L		 6364 if (*op_string == ':'
6365 && (r->reg_type.bitfield.sreg2
6366 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6367 {
6368 switch (r->reg_num)
6369 {
6370 case 0:
6371 i.seg[i.mem_operands] = &es;
6372 break;
6373 case 1:
6374 i.seg[i.mem_operands] = &cs;
6375 break;
6376 case 2:
6377 i.seg[i.mem_operands] = &ss;
6378 break;
6379 case 3:
6380 i.seg[i.mem_operands] = &ds;
6381 break;
6382 case 4:
6383 i.seg[i.mem_operands] = &fs;
6384 break;
6385 case 5:
6386 i.seg[i.mem_operands] = &gs;
6387 break;
6388 }
252b5132 6389
24eab124 6390 /* Skip the ':' and whitespace. */
252b5132
RH		 6391 ++op_string;
6392 if (is_space_char (*op_string))
24eab124 6393 ++op_string;
252b5132 6394
24eab124
AM		 6395 if (!is_digit_char (*op_string)
6396 && !is_identifier_char (*op_string)
6397 && *op_string != '('
6398 && *op_string != ABSOLUTE_PREFIX)
6399 {
6400 as_bad (_("bad memory operand `%s'"), op_string);
6401 return 0;
6402 }
47926f60 6403 /* Handle case of %es:*foo. */
24eab124
AM		 6404 if (*op_string == ABSOLUTE_PREFIX)
6405 {
6406 ++op_string;
6407 if (is_space_char (*op_string))
6408 ++op_string;
40fb9820 6409 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6410 }
6411 goto do_memory_reference;
6412 }
6413 if (*op_string)
6414 {
d0b47220 6415 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6416 return 0;
6417 }
40fb9820
L		 6418 temp = r->reg_type;
6419 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6420 i.types[this_operand] = operand_type_or (i.types[this_operand],
6421 temp);
7d5e4556 6422 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6423 i.op[this_operand].regs = r;
24eab124
AM		 6424 i.reg_operands++;
6425 }
af6bdddf
AM		 6426 else if (*op_string == REGISTER_PREFIX)
6427 {
6428 as_bad (_("bad register name `%s'"), op_string);
6429 return 0;
6430 }
24eab124 6431 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6432 {
24eab124 6433 ++op_string;
40fb9820 6434 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6435 {
d0b47220 6436 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6437 return 0;
6438 }
6439 if (!i386_immediate (op_string))
6440 return 0;
6441 }
6442 else if (is_digit_char (*op_string)
6443 || is_identifier_char (*op_string)
e5cb08ac 6444 || *op_string == '(')
24eab124 6445 {
47926f60 6446 /* This is a memory reference of some sort. */
af6bdddf 6447 char *base_string;
252b5132 6448
47926f60 6449 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6450 char *displacement_string_start;
6451 char *displacement_string_end;
252b5132 6452
24eab124 6453 do_memory_reference:
24eab124 6454 if ((i.mem_operands == 1
40fb9820 6455 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6456 || i.mem_operands == 2)
6457 {
6458 as_bad (_("too many memory references for `%s'"),
6459 current_templates->start->name);
6460 return 0;
6461 }
252b5132 6462
24eab124
AM		 6463 /* Check for base index form. We detect the base index form by
6464 looking for an ')' at the end of the operand, searching
6465 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6466 after the '('. */
af6bdddf 6467 base_string = op_string + strlen (op_string);
c3332e24 6468
af6bdddf
AM		 6469 --base_string;
6470 if (is_space_char (*base_string))
6471 --base_string;
252b5132 6472
47926f60 6473 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6474 displacement_string_start = op_string;
6475 displacement_string_end = base_string + 1;
252b5132 6476
24eab124
AM		 6477 if (*base_string == ')')
6478 {
af6bdddf 6479 char *temp_string;
24eab124
AM		 6480 unsigned int parens_balanced = 1;
6481 /* We've already checked that the number of left & right ()'s are
47926f60 6482 equal, so this loop will not be infinite. */
24eab124
AM		 6483 do
6484 {
6485 base_string--;
6486 if (*base_string == ')')
6487 parens_balanced++;
6488 if (*base_string == '(')
6489 parens_balanced--;
6490 }
6491 while (parens_balanced);
c3332e24 6492
af6bdddf 6493 temp_string = base_string;
c3332e24 6494
24eab124 6495 /* Skip past '(' and whitespace. */
252b5132
RH		 6496 ++base_string;
6497 if (is_space_char (*base_string))
24eab124 6498 ++base_string;
252b5132 6499
af6bdddf 6500 if (*base_string == ','
4eed87de
AM		 6501 || ((i.base_reg = parse_register (base_string, &end_op))
6502 != NULL))
252b5132 6503 {
af6bdddf 6504 displacement_string_end = temp_string;
252b5132 6505
40fb9820 6506 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6507
af6bdddf 6508 if (i.base_reg)
24eab124 6509 {
24eab124
AM		 6510 base_string = end_op;
6511 if (is_space_char (*base_string))
6512 ++base_string;
af6bdddf
AM		 6513 }
6514
6515 /* There may be an index reg or scale factor here. */
6516 if (*base_string == ',')
6517 {
6518 ++base_string;
6519 if (is_space_char (*base_string))
6520 ++base_string;
6521
4eed87de
AM		 6522 if ((i.index_reg = parse_register (base_string, &end_op))
6523 != NULL)
24eab124 6524 {
af6bdddf 6525 base_string = end_op;
24eab124
AM		 6526 if (is_space_char (*base_string))
6527 ++base_string;
af6bdddf
AM		 6528 if (*base_string == ',')
6529 {
6530 ++base_string;
6531 if (is_space_char (*base_string))
6532 ++base_string;
6533 }
e5cb08ac 6534 else if (*base_string != ')')
af6bdddf 6535 {
4eed87de
AM		 6536 as_bad (_("expecting `,' or `)' "
6537 "after index register in `%s'"),
af6bdddf
AM		 6538 operand_string);
6539 return 0;
6540 }
24eab124 6541 }
af6bdddf 6542 else if (*base_string == REGISTER_PREFIX)
24eab124 6543 {
af6bdddf 6544 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6545 return 0;
6546 }
252b5132 6547
47926f60 6548 /* Check for scale factor. */
551c1ca1 6549 if (*base_string != ')')
af6bdddf 6550 {
551c1ca1
AM		 6551 char *end_scale = i386_scale (base_string);
6552
6553 if (!end_scale)
af6bdddf 6554 return 0;
24eab124 6555
551c1ca1 6556 base_string = end_scale;
af6bdddf
AM		 6557 if (is_space_char (*base_string))
6558 ++base_string;
6559 if (*base_string != ')')
6560 {
4eed87de
AM		 6561 as_bad (_("expecting `)' "
6562 "after scale factor in `%s'"),
af6bdddf
AM		 6563 operand_string);
6564 return 0;
6565 }
6566 }
6567 else if (!i.index_reg)
24eab124 6568 {
4eed87de
AM		 6569 as_bad (_("expecting index register or scale factor "
6570 "after `,'; got '%c'"),
af6bdddf 6571 *base_string);
24eab124
AM		 6572 return 0;
6573 }
6574 }
af6bdddf 6575 else if (*base_string != ')')
24eab124 6576 {
4eed87de
AM		 6577 as_bad (_("expecting `,' or `)' "
6578 "after base register in `%s'"),
af6bdddf 6579 operand_string);
24eab124
AM		 6580 return 0;
6581 }
c3332e24 6582 }
af6bdddf 6583 else if (*base_string == REGISTER_PREFIX)
c3332e24 6584 {
af6bdddf 6585 as_bad (_("bad register name `%s'"), base_string);
24eab124 6586 return 0;
c3332e24 6587 }
24eab124
AM		 6588 }
6589
6590 /* If there's an expression beginning the operand, parse it,
6591 assuming displacement_string_start and
6592 displacement_string_end are meaningful. */
6593 if (displacement_string_start != displacement_string_end)
6594 {
6595 if (!i386_displacement (displacement_string_start,
6596 displacement_string_end))
6597 return 0;
6598 }
6599
6600 /* Special case for (%dx) while doing input/output op. */
6601 if (i.base_reg
0dfbf9d7
L		 6602 && operand_type_equal (&i.base_reg->reg_type,
6603 &reg16_inoutportreg)
24eab124
AM		 6604 && i.index_reg == 0
6605 && i.log2_scale_factor == 0
6606 && i.seg[i.mem_operands] == 0
40fb9820 6607 && !operand_type_check (i.types[this_operand], disp))
24eab124 6608 {
65da13b5 6609 i.types[this_operand] = inoutportreg;
24eab124
AM		 6610 return 1;
6611 }
6612
eecb386c
AM		 6613 if (i386_index_check (operand_string) == 0)
6614 return 0;
5c07affc 6615 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6616 i.mem_operands++;
6617 }
6618 else
ce8a8b2f
AM		 6619 {
6620 /* It's not a memory operand; argh! */
24eab124
AM		 6621 as_bad (_("invalid char %s beginning operand %d `%s'"),
6622 output_invalid (*op_string),
6623 this_operand + 1,
6624 op_string);
6625 return 0;
6626 }
47926f60 6627 return 1; /* Normal return. */
252b5132
RH		 6628}
6629\f
ee7fcc42
AM		 6630/* md_estimate_size_before_relax()
6631
6632 Called just before relax() for rs_machine_dependent frags. The x86
6633 assembler uses these frags to handle variable size jump
6634 instructions.
6635
6636 Any symbol that is now undefined will not become defined.
6637 Return the correct fr_subtype in the frag.
6638 Return the initial "guess for variable size of frag" to caller.
6639 The guess is actually the growth beyond the fixed part. Whatever
6640 we do to grow the fixed or variable part contributes to our
6641 returned value. */
6642
252b5132
RH		 6643int
6644md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6645 fragS *fragP;
6646 segT segment;
252b5132 6647{
252b5132 6648 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6649 check for un-relaxable symbols. On an ELF system, we can't relax
6650 an externally visible symbol, because it may be overridden by a
6651 shared library. */
6652 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6653#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6654 || (IS_ELF
31312f95
AM		 6655 && (S_IS_EXTERNAL (fragP->fr_symbol)
6656 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6657#endif
6658 )
252b5132 6659 {
b98ef147
AM		 6660 /* Symbol is undefined in this segment, or we need to keep a
6661 reloc so that weak symbols can be overridden. */
6662 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6663 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6664 unsigned char *opcode;
6665 int old_fr_fix;
f6af82bd 6666
ee7fcc42
AM		 6667 if (fragP->fr_var != NO_RELOC)
6668 reloc_type = fragP->fr_var;
b98ef147 6669 else if (size == 2)
f6af82bd
AM		 6670 reloc_type = BFD_RELOC_16_PCREL;
6671 else
6672 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6673
ee7fcc42
AM		 6674 old_fr_fix = fragP->fr_fix;
6675 opcode = (unsigned char *) fragP->fr_opcode;
6676
fddf5b5b 6677 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6678 {
fddf5b5b
AM		 6679 case UNCOND_JUMP:
6680 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6681 opcode[0] = 0xe9;
252b5132 6682 fragP->fr_fix += size;
062cd5e7
AS		 6683 fix_new (fragP, old_fr_fix, size,
6684 fragP->fr_symbol,
6685 fragP->fr_offset, 1,
6686 reloc_type);
252b5132
RH		 6687 break;
6688
fddf5b5b 6689 case COND_JUMP86:
412167cb
AM		 6690 if (size == 2
6691 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6692 {
6693 /* Negate the condition, and branch past an
6694 unconditional jump. */
6695 opcode[0] ^= 1;
6696 opcode[1] = 3;
6697 /* Insert an unconditional jump. */
6698 opcode[2] = 0xe9;
6699 /* We added two extra opcode bytes, and have a two byte
6700 offset. */
6701 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6702 fix_new (fragP, old_fr_fix + 2, 2,
6703 fragP->fr_symbol,
6704 fragP->fr_offset, 1,
6705 reloc_type);
fddf5b5b
AM		 6706 break;
6707 }
6708 /* Fall through. */
6709
6710 case COND_JUMP:
412167cb
AM		 6711 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6712 {
3e02c1cc
AM		 6713 fixS *fixP;
6714
412167cb 6715 fragP->fr_fix += 1;
3e02c1cc
AM		 6716 fixP = fix_new (fragP, old_fr_fix, 1,
6717 fragP->fr_symbol,
6718 fragP->fr_offset, 1,
6719 BFD_RELOC_8_PCREL);
6720 fixP->fx_signed = 1;
412167cb
AM		 6721 break;
6722 }
93c2a809 6723
24eab124 6724 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6725 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6726 opcode[1] = opcode[0] + 0x10;
f6af82bd 6727 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6728 /* We've added an opcode byte. */
6729 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6730 fix_new (fragP, old_fr_fix + 1, size,
6731 fragP->fr_symbol,
6732 fragP->fr_offset, 1,
6733 reloc_type);
252b5132 6734 break;
fddf5b5b
AM		 6735
6736 default:
6737 BAD_CASE (fragP->fr_subtype);
6738 break;
252b5132
RH		 6739 }
6740 frag_wane (fragP);
ee7fcc42 6741 return fragP->fr_fix - old_fr_fix;
252b5132 6742 }
93c2a809 6743
93c2a809
AM		 6744 /* Guess size depending on current relax state. Initially the relax
6745 state will correspond to a short jump and we return 1, because
6746 the variable part of the frag (the branch offset) is one byte
6747 long. However, we can relax a section more than once and in that
6748 case we must either set fr_subtype back to the unrelaxed state,
6749 or return the value for the appropriate branch. */
6750 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6751}
6752
47926f60
KH		 6753/* Called after relax() is finished.
6754
6755 In: Address of frag.
6756 fr_type == rs_machine_dependent.
6757 fr_subtype is what the address relaxed to.
6758
6759 Out: Any fixSs and constants are set up.
6760 Caller will turn frag into a ".space 0". */
6761
252b5132
RH		 6762void
6763md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6764 bfd *abfd ATTRIBUTE_UNUSED;
6765 segT sec ATTRIBUTE_UNUSED;
29b0f896 6766 fragS *fragP;
252b5132 6767{
29b0f896 6768 unsigned char *opcode;
252b5132 6769 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6770 offsetT target_address;
6771 offsetT opcode_address;
252b5132 6772 unsigned int extension = 0;
847f7ad4 6773 offsetT displacement_from_opcode_start;
252b5132
RH		 6774
6775 opcode = (unsigned char *) fragP->fr_opcode;
6776
47926f60 6777 /* Address we want to reach in file space. */
252b5132 6778 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6779
47926f60 6780 /* Address opcode resides at in file space. */
252b5132
RH		 6781 opcode_address = fragP->fr_address + fragP->fr_fix;
6782
47926f60 6783 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6784 displacement_from_opcode_start = target_address - opcode_address;
6785
fddf5b5b 6786 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6787 {
47926f60
KH		 6788 /* Don't have to change opcode. */
6789 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6790 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6791 }
6792 else
6793 {
6794 if (no_cond_jump_promotion
6795 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6796 as_warn_where (fragP->fr_file, fragP->fr_line,
6797 _("long jump required"));
252b5132 6798
fddf5b5b
AM		 6799 switch (fragP->fr_subtype)
6800 {
6801 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6802 extension = 4; /* 1 opcode + 4 displacement */
6803 opcode[0] = 0xe9;
6804 where_to_put_displacement = &opcode[1];
6805 break;
252b5132 6806
fddf5b5b
AM		 6807 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6808 extension = 2; /* 1 opcode + 2 displacement */
6809 opcode[0] = 0xe9;
6810 where_to_put_displacement = &opcode[1];
6811 break;
252b5132 6812
fddf5b5b
AM		 6813 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6814 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6815 extension = 5; /* 2 opcode + 4 displacement */
6816 opcode[1] = opcode[0] + 0x10;
6817 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6818 where_to_put_displacement = &opcode[2];
6819 break;
252b5132 6820
fddf5b5b
AM		 6821 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6822 extension = 3; /* 2 opcode + 2 displacement */
6823 opcode[1] = opcode[0] + 0x10;
6824 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6825 where_to_put_displacement = &opcode[2];
6826 break;
252b5132 6827
fddf5b5b
AM		 6828 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6829 extension = 4;
6830 opcode[0] ^= 1;
6831 opcode[1] = 3;
6832 opcode[2] = 0xe9;
6833 where_to_put_displacement = &opcode[3];
6834 break;
6835
6836 default:
6837 BAD_CASE (fragP->fr_subtype);
6838 break;
6839 }
252b5132 6840 }
fddf5b5b 6841
7b81dfbb
AJ		 6842 /* If size if less then four we are sure that the operand fits,
6843 but if it's 4, then it could be that the displacement is larger
6844 then -/+ 2GB. */
6845 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6846 && object_64bit
6847 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6848 + ((addressT) 1 << 31))
6849 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6850 {
6851 as_bad_where (fragP->fr_file, fragP->fr_line,
6852 _("jump target out of range"));
6853 /* Make us emit 0. */
6854 displacement_from_opcode_start = extension;
6855 }
47926f60 6856 /* Now put displacement after opcode. */
252b5132
RH		 6857 md_number_to_chars ((char *) where_to_put_displacement,
6858 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6859 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6860 fragP->fr_fix += extension;
6861}
6862\f
252b5132
RH		 6863/* Apply a fixup (fixS) to segment data, once it has been determined
6864 by our caller that we have all the info we need to fix it up.
6865
6866 On the 386, immediates, displacements, and data pointers are all in
6867 the same (little-endian) format, so we don't need to care about which
6868 we are handling. */
6869
94f592af 6870void
55cf6793 6871md_apply_fix (fixP, valP, seg)
47926f60
KH		 6872 /* The fix we're to put in. */
6873 fixS *fixP;
47926f60 6874 /* Pointer to the value of the bits. */
c6682705 6875 valueT *valP;
47926f60
KH		 6876 /* Segment fix is from. */
6877 segT seg ATTRIBUTE_UNUSED;
252b5132 6878{
94f592af 6879 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6880 valueT value = *valP;
252b5132 6881
f86103b7 6882#if !defined (TE_Mach)
93382f6d
AM		 6883 if (fixP->fx_pcrel)
6884 {
6885 switch (fixP->fx_r_type)
6886 {
5865bb77
ILT		 6887 default:
6888 break;
6889
d6ab8113
JB		 6890 case BFD_RELOC_64:
6891 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6892 break;
93382f6d 6893 case BFD_RELOC_32:
ae8887b5 6894 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6895 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6896 break;
6897 case BFD_RELOC_16:
6898 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6899 break;
6900 case BFD_RELOC_8:
6901 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6902 break;
6903 }
6904 }
252b5132 6905
a161fe53 6906 if (fixP->fx_addsy != NULL
31312f95 6907 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6908 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6909 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6910 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6911 && !use_rela_relocations)
252b5132 6912 {
31312f95
AM		 6913 /* This is a hack. There should be a better way to handle this.
6914 This covers for the fact that bfd_install_relocation will
6915 subtract the current location (for partial_inplace, PC relative
6916 relocations); see more below. */
252b5132 6917#ifndef OBJ_AOUT
718ddfc0 6918 if (IS_ELF
252b5132
RH		 6919#ifdef TE_PE
6920 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6921#endif
6922 )
6923 value += fixP->fx_where + fixP->fx_frag->fr_address;
6924#endif
6925#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6926 if (IS_ELF)
252b5132 6927 {
6539b54b 6928 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6929
6539b54b 6930 if ((sym_seg == seg
2f66722d 6931 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6932 && sym_seg != absolute_section))
ae6063d4 6933 && !generic_force_reloc (fixP))
2f66722d
AM		 6934 {
6935 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6936 bfd_install_relocation subtracts them out again. I think
6937 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6938 it. FIXME. */
6939 value += fixP->fx_where + fixP->fx_frag->fr_address;
6940 }
252b5132
RH		 6941 }
6942#endif
6943#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6944 /* For some reason, the PE format does not store a
6945 section address offset for a PC relative symbol. */
6946 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6947 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6948 value += md_pcrel_from (fixP);
6949#endif
6950 }
6951
6952 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6953 and we must not disappoint it. */
252b5132 6954#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6955 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6956 switch (fixP->fx_r_type)
6957 {
6958 case BFD_RELOC_386_PLT32:
3e73aa7c 6959 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6960 /* Make the jump instruction point to the address of the operand. At
6961 runtime we merely add the offset to the actual PLT entry. */
6962 value = -4;
6963 break;
31312f95 6964
13ae64f3
JJ		 6965 case BFD_RELOC_386_TLS_GD:
6966 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6967 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6968 case BFD_RELOC_386_TLS_IE:
6969 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6970 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6971 case BFD_RELOC_X86_64_TLSGD:
6972 case BFD_RELOC_X86_64_TLSLD:
6973 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6974 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6975 value = 0; /* Fully resolved at runtime. No addend. */
6976 /* Fallthrough */
6977 case BFD_RELOC_386_TLS_LE:
6978 case BFD_RELOC_386_TLS_LDO_32:
6979 case BFD_RELOC_386_TLS_LE_32:
6980 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6981 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6982 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6983 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6984 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6985 break;
6986
67a4f2b7
AO		 6987 case BFD_RELOC_386_TLS_DESC_CALL:
6988 case BFD_RELOC_X86_64_TLSDESC_CALL:
6989 value = 0; /* Fully resolved at runtime. No addend. */
6990 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6991 fixP->fx_done = 0;
6992 return;
6993
00f7efb6
JJ		 6994 case BFD_RELOC_386_GOT32:
6995 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6996 value = 0; /* Fully resolved at runtime. No addend. */
6997 break;
47926f60
KH		 6998
6999 case BFD_RELOC_VTABLE_INHERIT:
7000 case BFD_RELOC_VTABLE_ENTRY:
7001 fixP->fx_done = 0;
94f592af 7002 return;
47926f60
KH		 7003
7004 default:
7005 break;
7006 }
7007#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7008 *valP = value;
f86103b7 7009#endif /* !defined (TE_Mach) */
3e73aa7c 7010
3e73aa7c 7011 /* Are we finished with this relocation now? */
c6682705 7012 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7013 fixP->fx_done = 1;
7014 else if (use_rela_relocations)
7015 {
7016 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7017 /* Remember value for tc_gen_reloc. */
7018 fixP->fx_addnumber = value;
3e73aa7c
JH		 7019 value = 0;
7020 }
f86103b7 7021
94f592af 7022 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7023}
252b5132 7024\f
252b5132 7025char *
499ac353 7026md_atof (int type, char *litP, int *sizeP)
252b5132 7027{
499ac353
NC		 7028 /* This outputs the LITTLENUMs in REVERSE order;
7029 in accord with the bigendian 386. */
7030 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7031}
7032\f
2d545b82 7033static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7034
252b5132 7035static char *
e3bb37b5 7036output_invalid (int c)
252b5132 7037{
3882b010 7038 if (ISPRINT (c))
f9f21a03
L		 7039 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7040 "'%c'", c);
252b5132 7041 else
f9f21a03 7042 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7043 "(0x%x)", (unsigned char) c);
252b5132
RH		 7044 return output_invalid_buf;
7045}
7046
af6bdddf 7047/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7048
7049static const reg_entry *
4d1bb795 7050parse_real_register (char *reg_string, char **end_op)
252b5132 7051{
af6bdddf
AM		 7052 char *s = reg_string;
7053 char *p;
252b5132
RH		 7054 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7055 const reg_entry *r;
7056
7057 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7058 if (*s == REGISTER_PREFIX)
7059 ++s;
7060
7061 if (is_space_char (*s))
7062 ++s;
7063
7064 p = reg_name_given;
af6bdddf 7065 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7066 {
7067 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7068 return (const reg_entry *) NULL;
7069 s++;
252b5132
RH		 7070 }
7071
6588847e
DN		 7072 /* For naked regs, make sure that we are not dealing with an identifier.
7073 This prevents confusing an identifier like `eax_var' with register
7074 `eax'. */
7075 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7076 return (const reg_entry *) NULL;
7077
af6bdddf 7078 *end_op = s;
252b5132
RH		 7079
7080 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7081
5f47d35b 7082 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7083 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7084 {
5f47d35b
AM		 7085 if (is_space_char (*s))
7086 ++s;
7087 if (*s == '(')
7088 {
af6bdddf 7089 ++s;
5f47d35b
AM		 7090 if (is_space_char (*s))
7091 ++s;
7092 if (*s >= '0' && *s <= '7')
7093 {
db557034 7094 int fpr = *s - '0';
af6bdddf 7095 ++s;
5f47d35b
AM		 7096 if (is_space_char (*s))
7097 ++s;
7098 if (*s == ')')
7099 {
7100 *end_op = s + 1;
db557034
AM		 7101 r = hash_find (reg_hash, "st(0)");
7102 know (r);
7103 return r + fpr;
5f47d35b 7104 }
5f47d35b 7105 }
47926f60 7106 /* We have "%st(" then garbage. */
5f47d35b
AM		 7107 return (const reg_entry *) NULL;
7108 }
7109 }
7110
a60de03c
JB		 7111 if (r == NULL || allow_pseudo_reg)
7112 return r;
7113
0dfbf9d7 7114 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7115 return (const reg_entry *) NULL;
7116
db51cc60 7117 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7118 if (!allow_index_reg
db51cc60
L		 7119 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7120 return (const reg_entry *) NULL;
7121
a60de03c
JB		 7122 if (((r->reg_flags & (RegRex64 | RegRex))
7123 || r->reg_type.bitfield.reg64)
40fb9820 7124 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7125 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7126 && flag_code != CODE_64BIT)
20f0a1fc 7127 return (const reg_entry *) NULL;
1ae00879 7128
b7240065
JB		 7129 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7130 return (const reg_entry *) NULL;
7131
252b5132
RH		 7132 return r;
7133}
4d1bb795
JB		 7134
7135/* REG_STRING starts *before* REGISTER_PREFIX. */
7136
7137static const reg_entry *
7138parse_register (char *reg_string, char **end_op)
7139{
7140 const reg_entry *r;
7141
7142 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7143 r = parse_real_register (reg_string, end_op);
7144 else
7145 r = NULL;
7146 if (!r)
7147 {
7148 char *save = input_line_pointer;
7149 char c;
7150 symbolS *symbolP;
7151
7152 input_line_pointer = reg_string;
7153 c = get_symbol_end ();
7154 symbolP = symbol_find (reg_string);
7155 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7156 {
7157 const expressionS *e = symbol_get_value_expression (symbolP);
7158
7159 know (e->X_op == O_register);
4eed87de 7160 know (e->X_add_number >= 0
c3fe08fa 7161 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7162 r = i386_regtab + e->X_add_number;
7163 *end_op = input_line_pointer;
7164 }
7165 *input_line_pointer = c;
7166 input_line_pointer = save;
7167 }
7168 return r;
7169}
7170
7171int
7172i386_parse_name (char *name, expressionS *e, char *nextcharP)
7173{
7174 const reg_entry *r;
7175 char *end = input_line_pointer;
7176
7177 *end = *nextcharP;
7178 r = parse_register (name, &input_line_pointer);
7179 if (r && end <= input_line_pointer)
7180 {
7181 *nextcharP = *input_line_pointer;
7182 *input_line_pointer = 0;
7183 e->X_op = O_register;
7184 e->X_add_number = r - i386_regtab;
7185 return 1;
7186 }
7187 input_line_pointer = end;
7188 *end = 0;
7189 return 0;
7190}
7191
7192void
7193md_operand (expressionS *e)
7194{
7195 if (*input_line_pointer == REGISTER_PREFIX)
7196 {
7197 char *end;
7198 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7199
7200 if (r)
7201 {
7202 e->X_op = O_register;
7203 e->X_add_number = r - i386_regtab;
7204 input_line_pointer = end;
7205 }
7206 }
7207}
7208
252b5132 7209\f
4cc782b5 7210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7211const char *md_shortopts = "kVQ:sqn";
252b5132 7212#else
12b55ccc 7213const char *md_shortopts = "qn";
252b5132 7214#endif
6e0b89ee 7215
3e73aa7c 7216#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7217#define OPTION_64 (OPTION_MD_BASE + 1)
7218#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7219#define OPTION_MARCH (OPTION_MD_BASE + 3)
7220#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7221#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7222#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7223#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7224#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7225#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 7226
99ad8390
NC		 7227struct option md_longopts[] =
7228{
3e73aa7c 7229 {"32", no_argument, NULL, OPTION_32},
99ad8390 7230#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7231 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7232#endif
b3b91714 7233 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7234 {"march", required_argument, NULL, OPTION_MARCH},
7235 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7236 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7237 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7238 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7239 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7240 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 7241 {NULL, no_argument, NULL, 0}
7242};
7243size_t md_longopts_size = sizeof (md_longopts);
7244
7245int
9103f4f4 7246md_parse_option (int c, char *arg)
252b5132 7247{
9103f4f4 7248 unsigned int i;
6305a203 7249 char *arch, *next;
9103f4f4 7250
252b5132
RH		 7251 switch (c)
7252 {
12b55ccc
L		 7253 case 'n':
7254 optimize_align_code = 0;
7255 break;
7256
a38cf1db
AM		 7257 case 'q':
7258 quiet_warnings = 1;
252b5132
RH		 7259 break;
7260
7261#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7262 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7263 should be emitted or not. FIXME: Not implemented. */
7264 case 'Q':
252b5132
RH		 7265 break;
7266
7267 /* -V: SVR4 argument to print version ID. */
7268 case 'V':
7269 print_version_id ();
7270 break;
7271
a38cf1db
AM		 7272 /* -k: Ignore for FreeBSD compatibility. */
7273 case 'k':
252b5132 7274 break;
4cc782b5
ILT		 7275
7276 case 's':
7277 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7278 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7279 break;
99ad8390
NC		 7280#endif
7281#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7282 case OPTION_64:
7283 {
7284 const char **list, **l;
7285
3e73aa7c
JH		 7286 list = bfd_target_list ();
7287 for (l = list; *l != NULL; l++)
8620418b 7288 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7289 || strcmp (*l, "coff-x86-64") == 0
7290 || strcmp (*l, "pe-x86-64") == 0
7291 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7292 {
7293 default_arch = "x86_64";
7294 break;
7295 }
3e73aa7c 7296 if (*l == NULL)
6e0b89ee 7297 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7298 free (list);
7299 }
7300 break;
7301#endif
252b5132 7302
6e0b89ee
AM		 7303 case OPTION_32:
7304 default_arch = "i386";
7305 break;
7306
b3b91714
AM		 7307 case OPTION_DIVIDE:
7308#ifdef SVR4_COMMENT_CHARS
7309 {
7310 char *n, *t;
7311 const char *s;
7312
7313 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7314 t = n;
7315 for (s = i386_comment_chars; *s != '\0'; s++)
7316 if (*s != '/')
7317 *t++ = *s;
7318 *t = '\0';
7319 i386_comment_chars = n;
7320 }
7321#endif
7322 break;
7323
9103f4f4 7324 case OPTION_MARCH:
6305a203
L		 7325 arch = xstrdup (arg);
7326 do
9103f4f4 7327 {
6305a203
L		 7328 if (*arch == '.')
7329 as_fatal (_("Invalid -march= option: `%s'"), arg);
7330 next = strchr (arch, '+');
7331 if (next)
7332 *next++ = '\0';
7333 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7334 {
6305a203 7335 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7336 {
6305a203
L		 7337 /* Processor. */
7338 cpu_arch_name = cpu_arch[i].name;
7339 cpu_sub_arch_name = NULL;
7340 cpu_arch_flags = cpu_arch[i].flags;
7341 cpu_arch_isa = cpu_arch[i].type;
7342 cpu_arch_isa_flags = cpu_arch[i].flags;
7343 if (!cpu_arch_tune_set)
7344 {
7345 cpu_arch_tune = cpu_arch_isa;
7346 cpu_arch_tune_flags = cpu_arch_isa_flags;
7347 }
7348 break;
7349 }
7350 else if (*cpu_arch [i].name == '.'
7351 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7352 {
7353 /* ISA entension. */
7354 i386_cpu_flags flags;
7355 flags = cpu_flags_or (cpu_arch_flags,
7356 cpu_arch[i].flags);
0dfbf9d7 7357 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7358 {
7359 if (cpu_sub_arch_name)
7360 {
7361 char *name = cpu_sub_arch_name;
7362 cpu_sub_arch_name = concat (name,
7363 cpu_arch[i].name,
1bf57e9f 7364 (const char *) NULL);
6305a203
L		 7365 free (name);
7366 }
7367 else
7368 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7369 cpu_arch_flags = flags;
7370 }
7371 break;
ccc9c027 7372 }
9103f4f4 7373 }
6305a203
L		 7374
7375 if (i >= ARRAY_SIZE (cpu_arch))
7376 as_fatal (_("Invalid -march= option: `%s'"), arg);
7377
7378 arch = next;
9103f4f4 7379 }
6305a203 7380 while (next != NULL );
9103f4f4
L		 7381 break;
7382
7383 case OPTION_MTUNE:
7384 if (*arg == '.')
7385 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7386 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7387 {
7388 if (strcmp (arg, cpu_arch [i].name) == 0)
7389 {
ccc9c027 7390 cpu_arch_tune_set = 1;
9103f4f4
L		 7391 cpu_arch_tune = cpu_arch [i].type;
7392 cpu_arch_tune_flags = cpu_arch[i].flags;
7393 break;
7394 }
7395 }
7396 if (i >= ARRAY_SIZE (cpu_arch))
7397 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7398 break;
7399
1efbbeb4
L		 7400 case OPTION_MMNEMONIC:
7401 if (strcasecmp (arg, "att") == 0)
7402 intel_mnemonic = 0;
7403 else if (strcasecmp (arg, "intel") == 0)
7404 intel_mnemonic = 1;
7405 else
7406 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7407 break;
7408
7409 case OPTION_MSYNTAX:
7410 if (strcasecmp (arg, "att") == 0)
7411 intel_syntax = 0;
7412 else if (strcasecmp (arg, "intel") == 0)
7413 intel_syntax = 1;
7414 else
7415 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7416 break;
7417
7418 case OPTION_MINDEX_REG:
7419 allow_index_reg = 1;
7420 break;
7421
7422 case OPTION_MNAKED_REG:
7423 allow_naked_reg = 1;
7424 break;
7425
7426 case OPTION_MOLD_GCC:
7427 old_gcc = 1;
1efbbeb4
L		 7428 break;
7429
252b5132
RH		 7430 default:
7431 return 0;
7432 }
7433 return 1;
7434}
7435
7436void
7437md_show_usage (stream)
7438 FILE *stream;
7439{
4cc782b5
ILT		 7440#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7441 fprintf (stream, _("\
a38cf1db
AM		 7442 -Q ignored\n\
7443 -V print assembler version number\n\
b3b91714
AM		 7444 -k ignored\n"));
7445#endif
7446 fprintf (stream, _("\
12b55ccc 7447 -n Do not optimize code alignment\n\
b3b91714
AM		 7448 -q quieten some warnings\n"));
7449#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7450 fprintf (stream, _("\
a38cf1db 7451 -s ignored\n"));
b3b91714 7452#endif
751d281c
L		 7453#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7454 fprintf (stream, _("\
7455 --32/--64 generate 32bit/64bit code\n"));
7456#endif
b3b91714
AM		 7457#ifdef SVR4_COMMENT_CHARS
7458 fprintf (stream, _("\
7459 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7460#else
7461 fprintf (stream, _("\
b3b91714 7462 --divide ignored\n"));
4cc782b5 7463#endif
9103f4f4 7464 fprintf (stream, _("\
6305a203
L		 7465 -march=CPU[,+EXTENSION...]\n\
7466 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7467 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7468 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7469 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7470 generic32, generic64\n\
599121aa
L		 7471 EXTENSION is combination of:\n\
7472 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f03fe4c1
L		 7473 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7474 abm, padlock\n"));
6305a203 7475 fprintf (stream, _("\
2cb4f3d5
L		 7476 -mtune=CPU optimize for CPU, CPU is one of:\n\
7477 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7478 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7479 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7480 generic32, generic64\n"));
ba104c83
L		 7481 fprintf (stream, _("\
7482 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7483 fprintf (stream, _("\
7484 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7485 fprintf (stream, _("\
7486 -mindex-reg support pseudo index registers\n"));
7487 fprintf (stream, _("\
7488 -mnaked-reg don't require `%%' prefix for registers\n"));
7489 fprintf (stream, _("\
7490 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7491}
7492
3e73aa7c 7493#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7494 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7495
7496/* Pick the target format to use. */
7497
47926f60 7498const char *
e3bb37b5 7499i386_target_format (void)
252b5132 7500{
3e73aa7c 7501 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7502 {
7503 set_code_flag (CODE_64BIT);
0dfbf9d7 7504 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7505 {
7506 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7507 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7508 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7509 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7510 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7511 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7512 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7513 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7514 cpu_arch_isa_flags.bitfield.cpusse = 1;
7515 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7516 }
0dfbf9d7 7517 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7518 {
7519 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7520 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7521 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7522 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7523 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7524 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7525 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7526 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 7527 cpu_arch_tune_flags.bitfield.cpusse = 1;
7528 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7529 }
9103f4f4 7530 }
3e73aa7c 7531 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7532 {
7533 set_code_flag (CODE_32BIT);
0dfbf9d7 7534 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7535 {
7536 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7537 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7538 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7539 }
0dfbf9d7 7540 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7541 {
7542 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7543 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7544 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7545 }
9103f4f4 7546 }
3e73aa7c
JH		 7547 else
7548 as_fatal (_("Unknown architecture"));
252b5132
RH		 7549 switch (OUTPUT_FLAVOR)
7550 {
872ce6ff
L		 7551#ifdef TE_PEP
7552 case bfd_target_coff_flavour:
7553 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7554 break;
7555#endif
4c63da97
AM		 7556#ifdef OBJ_MAYBE_AOUT
7557 case bfd_target_aout_flavour:
47926f60 7558 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7559#endif
7560#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7561 case bfd_target_coff_flavour:
7562 return "coff-i386";
4c63da97 7563#endif
3e73aa7c 7564#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7565 case bfd_target_elf_flavour:
3e73aa7c 7566 {
e5cb08ac 7567 if (flag_code == CODE_64BIT)
4fa24527
JB		 7568 {
7569 object_64bit = 1;
7570 use_rela_relocations = 1;
7571 }
9d7cbccd 7572 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7573 }
4c63da97 7574#endif
252b5132
RH		 7575 default:
7576 abort ();
7577 return NULL;
7578 }
7579}
7580
47926f60 7581#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7582
7583#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7584void
7585i386_elf_emit_arch_note (void)
a847613f 7586{
718ddfc0 7587 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7588 {
7589 char *p;
7590 asection *seg = now_seg;
7591 subsegT subseg = now_subseg;
7592 Elf_Internal_Note i_note;
7593 Elf_External_Note e_note;
7594 asection *note_secp;
7595 int len;
7596
7597 /* Create the .note section. */
7598 note_secp = subseg_new (".note", 0);
7599 bfd_set_section_flags (stdoutput,
7600 note_secp,
7601 SEC_HAS_CONTENTS | SEC_READONLY);
7602
7603 /* Process the arch string. */
7604 len = strlen (cpu_arch_name);
7605
7606 i_note.namesz = len + 1;
7607 i_note.descsz = 0;
7608 i_note.type = NT_ARCH;
7609 p = frag_more (sizeof (e_note.namesz));
7610 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7611 p = frag_more (sizeof (e_note.descsz));
7612 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7613 p = frag_more (sizeof (e_note.type));
7614 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7615 p = frag_more (len + 1);
7616 strcpy (p, cpu_arch_name);
7617
7618 frag_align (2, 0, 0);
7619
7620 subseg_set (seg, subseg);
7621 }
7622}
7623#endif
252b5132 7624\f
252b5132
RH		 7625symbolS *
7626md_undefined_symbol (name)
7627 char *name;
7628{
18dc2407
ILT		 7629 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7630 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7631 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7632 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7633 {
7634 if (!GOT_symbol)
7635 {
7636 if (symbol_find (name))
7637 as_bad (_("GOT already in symbol table"));
7638 GOT_symbol = symbol_new (name, undefined_section,
7639 (valueT) 0, &zero_address_frag);
7640 };
7641 return GOT_symbol;
7642 }
252b5132
RH		 7643 return 0;
7644}
7645
7646/* Round up a section size to the appropriate boundary. */
47926f60 7647
252b5132
RH		 7648valueT
7649md_section_align (segment, size)
ab9da554 7650 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7651 valueT size;
7652{
4c63da97
AM		 7653#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7654 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7655 {
7656 /* For a.out, force the section size to be aligned. If we don't do
7657 this, BFD will align it for us, but it will not write out the
7658 final bytes of the section. This may be a bug in BFD, but it is
7659 easier to fix it here since that is how the other a.out targets
7660 work. */
7661 int align;
7662
7663 align = bfd_get_section_alignment (stdoutput, segment);
7664 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7665 }
252b5132
RH		 7666#endif
7667
7668 return size;
7669}
7670
7671/* On the i386, PC-relative offsets are relative to the start of the
7672 next instruction. That is, the address of the offset, plus its
7673 size, since the offset is always the last part of the insn. */
7674
7675long
e3bb37b5 7676md_pcrel_from (fixS *fixP)
252b5132
RH		 7677{
7678 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7679}
7680
7681#ifndef I386COFF
7682
7683static void
e3bb37b5 7684s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7685{
29b0f896 7686 int temp;
252b5132 7687
8a75718c
JB		 7688#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7689 if (IS_ELF)
7690 obj_elf_section_change_hook ();
7691#endif
252b5132
RH		 7692 temp = get_absolute_expression ();
7693 subseg_set (bss_section, (subsegT) temp);
7694 demand_empty_rest_of_line ();
7695}
7696
7697#endif
7698
252b5132 7699void
e3bb37b5 7700i386_validate_fix (fixS *fixp)
252b5132
RH		 7701{
7702 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7703 {
23df1078
JH		 7704 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7705 {
4fa24527 7706 if (!object_64bit)
23df1078
JH		 7707 abort ();
7708 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7709 }
7710 else
7711 {
4fa24527 7712 if (!object_64bit)
d6ab8113
JB		 7713 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7714 else
7715 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7716 }
252b5132
RH		 7717 fixp->fx_subsy = 0;
7718 }
7719}
7720
252b5132
RH		 7721arelent *
7722tc_gen_reloc (section, fixp)
ab9da554 7723 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7724 fixS *fixp;
7725{
7726 arelent *rel;
7727 bfd_reloc_code_real_type code;
7728
7729 switch (fixp->fx_r_type)
7730 {
3e73aa7c
JH		 7731 case BFD_RELOC_X86_64_PLT32:
7732 case BFD_RELOC_X86_64_GOT32:
7733 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7734 case BFD_RELOC_386_PLT32:
7735 case BFD_RELOC_386_GOT32:
7736 case BFD_RELOC_386_GOTOFF:
7737 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7738 case BFD_RELOC_386_TLS_GD:
7739 case BFD_RELOC_386_TLS_LDM:
7740 case BFD_RELOC_386_TLS_LDO_32:
7741 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7742 case BFD_RELOC_386_TLS_IE:
7743 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7744 case BFD_RELOC_386_TLS_LE_32:
7745 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7746 case BFD_RELOC_386_TLS_GOTDESC:
7747 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7748 case BFD_RELOC_X86_64_TLSGD:
7749 case BFD_RELOC_X86_64_TLSLD:
7750 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7751 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7752 case BFD_RELOC_X86_64_GOTTPOFF:
7753 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7754 case BFD_RELOC_X86_64_TPOFF64:
7755 case BFD_RELOC_X86_64_GOTOFF64:
7756 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7757 case BFD_RELOC_X86_64_GOT64:
7758 case BFD_RELOC_X86_64_GOTPCREL64:
7759 case BFD_RELOC_X86_64_GOTPC64:
7760 case BFD_RELOC_X86_64_GOTPLT64:
7761 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7762 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7763 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7764 case BFD_RELOC_RVA:
7765 case BFD_RELOC_VTABLE_ENTRY:
7766 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7767#ifdef TE_PE
7768 case BFD_RELOC_32_SECREL:
7769#endif
252b5132
RH		 7770 code = fixp->fx_r_type;
7771 break;
dbbaec26
L		 7772 case BFD_RELOC_X86_64_32S:
7773 if (!fixp->fx_pcrel)
7774 {
7775 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7776 code = fixp->fx_r_type;
7777 break;
7778 }
252b5132 7779 default:
93382f6d 7780 if (fixp->fx_pcrel)
252b5132 7781 {
93382f6d
AM		 7782 switch (fixp->fx_size)
7783 {
7784 default:
b091f402
AM		 7785 as_bad_where (fixp->fx_file, fixp->fx_line,
7786 _("can not do %d byte pc-relative relocation"),
7787 fixp->fx_size);
93382f6d
AM		 7788 code = BFD_RELOC_32_PCREL;
7789 break;
7790 case 1: code = BFD_RELOC_8_PCREL; break;
7791 case 2: code = BFD_RELOC_16_PCREL; break;
7792 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7793#ifdef BFD64
7794 case 8: code = BFD_RELOC_64_PCREL; break;
7795#endif
93382f6d
AM		 7796 }
7797 }
7798 else
7799 {
7800 switch (fixp->fx_size)
7801 {
7802 default:
b091f402
AM		 7803 as_bad_where (fixp->fx_file, fixp->fx_line,
7804 _("can not do %d byte relocation"),
7805 fixp->fx_size);
93382f6d
AM		 7806 code = BFD_RELOC_32;
7807 break;
7808 case 1: code = BFD_RELOC_8; break;
7809 case 2: code = BFD_RELOC_16; break;
7810 case 4: code = BFD_RELOC_32; break;
937149dd 7811#ifdef BFD64
3e73aa7c 7812 case 8: code = BFD_RELOC_64; break;
937149dd 7813#endif
93382f6d 7814 }
252b5132
RH		 7815 }
7816 break;
7817 }
252b5132 7818
d182319b
JB		 7819 if ((code == BFD_RELOC_32
7820 || code == BFD_RELOC_32_PCREL
7821 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7822 && GOT_symbol
7823 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7824 {
4fa24527 7825 if (!object_64bit)
d6ab8113
JB		 7826 code = BFD_RELOC_386_GOTPC;
7827 else
7828 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7829 }
7b81dfbb
AJ		 7830 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7831 && GOT_symbol
7832 && fixp->fx_addsy == GOT_symbol)
7833 {
7834 code = BFD_RELOC_X86_64_GOTPC64;
7835 }
252b5132
RH		 7836
7837 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7838 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7839 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7840
7841 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7842
3e73aa7c
JH		 7843 if (!use_rela_relocations)
7844 {
7845 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7846 vtable entry to be used in the relocation's section offset. */
7847 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7848 rel->address = fixp->fx_offset;
252b5132 7849
c6682705 7850 rel->addend = 0;
3e73aa7c
JH		 7851 }
7852 /* Use the rela in 64bit mode. */
252b5132 7853 else
3e73aa7c 7854 {
062cd5e7
AS		 7855 if (!fixp->fx_pcrel)
7856 rel->addend = fixp->fx_offset;
7857 else
7858 switch (code)
7859 {
7860 case BFD_RELOC_X86_64_PLT32:
7861 case BFD_RELOC_X86_64_GOT32:
7862 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7863 case BFD_RELOC_X86_64_TLSGD:
7864 case BFD_RELOC_X86_64_TLSLD:
7865 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7866 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7867 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7868 rel->addend = fixp->fx_offset - fixp->fx_size;
7869 break;
7870 default:
7871 rel->addend = (section->vma
7872 - fixp->fx_size
7873 + fixp->fx_addnumber
7874 + md_pcrel_from (fixp));
7875 break;
7876 }
3e73aa7c
JH		 7877 }
7878
252b5132
RH		 7879 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7880 if (rel->howto == NULL)
7881 {
7882 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7883 _("cannot represent relocation type %s"),
252b5132
RH		 7884 bfd_get_reloc_code_name (code));
7885 /* Set howto to a garbage value so that we can keep going. */
7886 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7887 assert (rel->howto != NULL);
7888 }
7889
7890 return rel;
7891}
7892
64a0c779
DN		 7893\f
7894/* Parse operands using Intel syntax. This implements a recursive descent
7895 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7896 Programmer's Guide.
7897
7898 FIXME: We do not recognize the full operand grammar defined in the MASM
7899 documentation. In particular, all the structure/union and
7900 high-level macro operands are missing.
7901
7902 Uppercase words are terminals, lower case words are non-terminals.
7903 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7904 bars '|' denote choices. Most grammar productions are implemented in
7905 functions called 'intel_<production>'.
7906
7907 Initial production is 'expr'.
7908
9306ca4a 7909 addOp + | -
64a0c779
DN		 7910
7911 alpha [a-zA-Z]
7912
9306ca4a
JB		 7913 binOp & | AND | \| | OR | ^ | XOR
7914
64a0c779
DN		 7915 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7916
7917 constant digits [[ radixOverride ]]
7918
9306ca4a 7919 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7920
7921 digits decdigit
b77a7acd
AJ		 7922 | digits decdigit
7923 | digits hexdigit
64a0c779
DN		 7924
7925 decdigit [0-9]
7926
9306ca4a
JB		 7927 e04 e04 addOp e05
7928 | e05
7929
7930 e05 e05 binOp e06
b77a7acd 7931 | e06
64a0c779
DN		 7932
7933 e06 e06 mulOp e09
b77a7acd 7934 | e09
64a0c779
DN		 7935
7936 e09 OFFSET e10
a724f0f4
JB		 7937 | SHORT e10
7938 | + e10
7939 | - e10
9306ca4a
JB		 7940 | ~ e10
7941 | NOT e10
64a0c779
DN		 7942 | e09 PTR e10
7943 | e09 : e10
7944 | e10
7945
7946 e10 e10 [ expr ]
b77a7acd 7947 | e11
64a0c779
DN		 7948
7949 e11 ( expr )
b77a7acd 7950 | [ expr ]
64a0c779
DN		 7951 | constant
7952 | dataType
7953 | id
7954 | $
7955 | register
7956
a724f0f4 7957 => expr expr cmpOp e04
9306ca4a 7958 | e04
64a0c779
DN		 7959
7960 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7961 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7962
7963 hexdigit a | b | c | d | e | f
b77a7acd 7964 | A | B | C | D | E | F
64a0c779
DN		 7965
7966 id alpha
b77a7acd 7967 | id alpha
64a0c779
DN		 7968 | id decdigit
7969
9306ca4a 7970 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7971
7972 quote " | '
7973
7974 register specialRegister
b77a7acd 7975 | gpRegister
64a0c779
DN		 7976 | byteRegister
7977
7978 segmentRegister CS | DS | ES | FS | GS | SS
7979
9306ca4a 7980 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7981 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7982 | TR3 | TR4 | TR5 | TR6 | TR7
7983
64a0c779
DN		 7984 We simplify the grammar in obvious places (e.g., register parsing is
7985 done by calling parse_register) and eliminate immediate left recursion
7986 to implement a recursive-descent parser.
7987
a724f0f4
JB		 7988 expr e04 expr'
7989
7990 expr' cmpOp e04 expr'
7991 | Empty
9306ca4a
JB		 7992
7993 e04 e05 e04'
7994
7995 e04' addOp e05 e04'
7996 | Empty
64a0c779
DN		 7997
7998 e05 e06 e05'
7999
9306ca4a 8000 e05' binOp e06 e05'
b77a7acd 8001 | Empty
64a0c779
DN		 8002
8003 e06 e09 e06'
8004
8005 e06' mulOp e09 e06'
b77a7acd 8006 | Empty
64a0c779
DN		 8007
8008 e09 OFFSET e10 e09'
a724f0f4
JB		 8009 | SHORT e10'
8010 | + e10'
8011 | - e10'
8012 | ~ e10'
8013 | NOT e10'
b77a7acd 8014 | e10 e09'
64a0c779
DN		 8015
8016 e09' PTR e10 e09'
b77a7acd 8017 | : e10 e09'
64a0c779
DN		 8018 | Empty
8019
8020 e10 e11 e10'
8021
8022 e10' [ expr ] e10'
b77a7acd 8023 | Empty
64a0c779
DN		 8024
8025 e11 ( expr )
b77a7acd 8026 | [ expr ]
64a0c779
DN		 8027 | BYTE
8028 | WORD
8029 | DWORD
9306ca4a 8030 | FWORD
64a0c779 8031 | QWORD
9306ca4a
JB		 8032 | TBYTE
8033 | OWORD
8034 | XMMWORD
64a0c779
DN		 8035 | .
8036 | $
8037 | register
8038 | id
8039 | constant */
8040
8041/* Parsing structure for the intel syntax parser. Used to implement the
8042 semantic actions for the operand grammar. */
8043struct intel_parser_s
8044 {
8045 char *op_string; /* The string being parsed. */
8046 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8047 int op_modifier; /* Operand modifier. */
64a0c779 8048 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8049 int in_offset; /* >=1 if parsing operand of offset. */
8050 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8051 const reg_entry *reg; /* Last register reference found. */
8052 char *disp; /* Displacement string being built. */
a724f0f4 8053 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8054 };
8055
8056static struct intel_parser_s intel_parser;
8057
8058/* Token structure for parsing intel syntax. */
8059struct intel_token
8060 {
8061 int code; /* Token code. */
8062 const reg_entry *reg; /* Register entry for register tokens. */
8063 char *str; /* String representation. */
8064 };
8065
8066static struct intel_token cur_token, prev_token;
8067
50705ef4
AM		 8068/* Token codes for the intel parser. Since T_SHORT is already used
8069 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8070#define T_NIL -1
8071#define T_CONST 1
8072#define T_REG 2
8073#define T_BYTE 3
8074#define T_WORD 4
9306ca4a
JB		 8075#define T_DWORD 5
8076#define T_FWORD 6
8077#define T_QWORD 7
8078#define T_TBYTE 8
8079#define T_XMMWORD 9
50705ef4 8080#undef T_SHORT
9306ca4a
JB		 8081#define T_SHORT 10
8082#define T_OFFSET 11
8083#define T_PTR 12
8084#define T_ID 13
8085#define T_SHL 14
8086#define T_SHR 15
64a0c779
DN		 8087
8088/* Prototypes for intel parser functions. */
e3bb37b5
L		 8089static int intel_match_token (int);
8090static void intel_putback_token (void);
8091static void intel_get_token (void);
8092static int intel_expr (void);
8093static int intel_e04 (void);
8094static int intel_e05 (void);
8095static int intel_e06 (void);
8096static int intel_e09 (void);
8097static int intel_e10 (void);
8098static int intel_e11 (void);
64a0c779 8099
64a0c779 8100static int
e3bb37b5 8101i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8102{
8103 int ret;
8104 char *p;
8105
a724f0f4
JB		 8106 p = intel_parser.op_string = xstrdup (operand_string);
8107 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8108
8109 for (;;)
64a0c779 8110 {
a724f0f4
JB		 8111 /* Initialize token holders. */
8112 cur_token.code = prev_token.code = T_NIL;
8113 cur_token.reg = prev_token.reg = NULL;
8114 cur_token.str = prev_token.str = NULL;
8115
8116 /* Initialize parser structure. */
8117 intel_parser.got_a_float = got_a_float;
8118 intel_parser.op_modifier = 0;
8119 intel_parser.is_mem = 0;
8120 intel_parser.in_offset = 0;
8121 intel_parser.in_bracket = 0;
8122 intel_parser.reg = NULL;
8123 intel_parser.disp[0] = '\0';
8124 intel_parser.next_operand = NULL;
8125
8126 /* Read the first token and start the parser. */
8127 intel_get_token ();
8128 ret = intel_expr ();
8129
8130 if (!ret)
8131 break;
8132
9306ca4a
JB		 8133 if (cur_token.code != T_NIL)
8134 {
8135 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8136 current_templates->start->name, cur_token.str);
8137 ret = 0;
8138 }
64a0c779
DN		 8139 /* If we found a memory reference, hand it over to i386_displacement
8140 to fill in the rest of the operand fields. */
9306ca4a 8141 else if (intel_parser.is_mem)
64a0c779
DN		 8142 {
8143 if ((i.mem_operands == 1
40fb9820 8144 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8145 || i.mem_operands == 2)
8146 {
8147 as_bad (_("too many memory references for '%s'"),
8148 current_templates->start->name);
8149 ret = 0;
8150 }
8151 else
8152 {
8153 char *s = intel_parser.disp;
5c07affc 8154 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 8155 i.mem_operands++;
8156
a724f0f4
JB		 8157 if (!quiet_warnings && intel_parser.is_mem < 0)
8158 /* See the comments in intel_bracket_expr. */
8159 as_warn (_("Treating `%s' as memory reference"), operand_string);
8160
64a0c779
DN		 8161 /* Add the displacement expression. */
8162 if (*s != '\0')
a4622f40
AM		 8163 ret = i386_displacement (s, s + strlen (s));
8164 if (ret)
a724f0f4
JB		 8165 {
8166 /* Swap base and index in 16-bit memory operands like
8167 [si+bx]. Since i386_index_check is also used in AT&T
8168 mode we have to do that here. */
8169 if (i.base_reg
8170 && i.index_reg
40fb9820
L		 8171 && i.base_reg->reg_type.bitfield.reg16
8172 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8173 && i.base_reg->reg_num >= 6
8174 && i.index_reg->reg_num < 6)
8175 {
8176 const reg_entry *base = i.index_reg;
8177
8178 i.index_reg = i.base_reg;
8179 i.base_reg = base;
8180 }
8181 ret = i386_index_check (operand_string);
8182 }
64a0c779
DN		 8183 }
8184 }
8185
8186 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8187 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8188 || intel_parser.reg == NULL)
b7240065
JB		 8189 {
8190 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8191 {
8192 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8193 as_warn (_("Segment override ignored"));
8194 i.seg[i.mem_operands] = NULL;
8195 }
8196 ret = i386_immediate (intel_parser.disp);
8197 }
a724f0f4
JB		 8198
8199 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8200 ret = 0;
a724f0f4
JB		 8201 if (!ret || !intel_parser.next_operand)
8202 break;
8203 intel_parser.op_string = intel_parser.next_operand;
8204 this_operand = i.operands++;
7d5e4556 8205 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8206 }
8207
8208 free (p);
8209 free (intel_parser.disp);
8210
8211 return ret;
8212}
8213
a724f0f4
JB		 8214#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8215
8216/* expr e04 expr'
8217
8218 expr' cmpOp e04 expr'
8219 | Empty */
64a0c779 8220static int
e3bb37b5 8221intel_expr (void)
64a0c779 8222{
a724f0f4
JB		 8223 /* XXX Implement the comparison operators. */
8224 return intel_e04 ();
9306ca4a
JB		 8225}
8226
a724f0f4 8227/* e04 e05 e04'
9306ca4a 8228
a724f0f4 8229 e04' addOp e05 e04'
9306ca4a
JB		 8230 | Empty */
8231static int
e3bb37b5 8232intel_e04 (void)
9306ca4a 8233{
a724f0f4 8234 int nregs = -1;
9306ca4a 8235
a724f0f4 8236 for (;;)
9306ca4a 8237 {
a724f0f4
JB		 8238 if (!intel_e05())
8239 return 0;
9306ca4a 8240
a724f0f4
JB		 8241 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8242 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 8243
a724f0f4
JB		 8244 if (cur_token.code == '+')
8245 nregs = -1;
8246 else if (cur_token.code == '-')
8247 nregs = NUM_ADDRESS_REGS;
8248 else
8249 return 1;
64a0c779 8250
a724f0f4
JB		 8251 strcat (intel_parser.disp, cur_token.str);
8252 intel_match_token (cur_token.code);
8253 }
64a0c779
DN		 8254}
8255
64a0c779
DN		 8256/* e05 e06 e05'
8257
9306ca4a 8258 e05' binOp e06 e05'
64a0c779
DN		 8259 | Empty */
8260static int
e3bb37b5 8261intel_e05 (void)
64a0c779 8262{
a724f0f4 8263 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8264
a724f0f4 8265 for (;;)
64a0c779 8266 {
a724f0f4
JB		 8267 if (!intel_e06())
8268 return 0;
8269
4eed87de
AM		 8270 if (cur_token.code == '&'
8271 || cur_token.code == '|'
8272 || cur_token.code == '^')
a724f0f4
JB		 8273 {
8274 char str[2];
8275
8276 str[0] = cur_token.code;
8277 str[1] = 0;
8278 strcat (intel_parser.disp, str);
8279 }
8280 else
8281 break;
9306ca4a 8282
64a0c779
DN		 8283 intel_match_token (cur_token.code);
8284
a724f0f4
JB		 8285 if (nregs < 0)
8286 nregs = ~nregs;
64a0c779 8287 }
a724f0f4
JB		 8288 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8289 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8290 return 1;
4a1805b1 8291}
64a0c779
DN		 8292
8293/* e06 e09 e06'
8294
8295 e06' mulOp e09 e06'
b77a7acd 8296 | Empty */
64a0c779 8297static int
e3bb37b5 8298intel_e06 (void)
64a0c779 8299{
a724f0f4 8300 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8301
a724f0f4 8302 for (;;)
64a0c779 8303 {
a724f0f4
JB		 8304 if (!intel_e09())
8305 return 0;
9306ca4a 8306
4eed87de
AM		 8307 if (cur_token.code == '*'
8308 || cur_token.code == '/'
8309 || cur_token.code == '%')
a724f0f4
JB		 8310 {
8311 char str[2];
9306ca4a 8312
a724f0f4
JB		 8313 str[0] = cur_token.code;
8314 str[1] = 0;
8315 strcat (intel_parser.disp, str);
8316 }
8317 else if (cur_token.code == T_SHL)
8318 strcat (intel_parser.disp, "<<");
8319 else if (cur_token.code == T_SHR)
8320 strcat (intel_parser.disp, ">>");
8321 else
8322 break;
9306ca4a 8323
64e74474 8324 intel_match_token (cur_token.code);
64a0c779 8325
a724f0f4
JB		 8326 if (nregs < 0)
8327 nregs = ~nregs;
64a0c779 8328 }
a724f0f4
JB		 8329 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8330 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8331 return 1;
64a0c779
DN		 8332}
8333
a724f0f4
JB		 8334/* e09 OFFSET e09
8335 | SHORT e09
8336 | + e09
8337 | - e09
8338 | ~ e09
8339 | NOT e09
9306ca4a
JB		 8340 | e10 e09'
8341
64a0c779 8342 e09' PTR e10 e09'
b77a7acd 8343 | : e10 e09'
64a0c779
DN		 8344 | Empty */
8345static int
e3bb37b5 8346intel_e09 (void)
64a0c779 8347{
a724f0f4
JB		 8348 int nregs = ~NUM_ADDRESS_REGS;
8349 int in_offset = 0;
8350
8351 for (;;)
64a0c779 8352 {
a724f0f4
JB		 8353 /* Don't consume constants here. */
8354 if (cur_token.code == '+' || cur_token.code == '-')
8355 {
8356 /* Need to look one token ahead - if the next token
8357 is a constant, the current token is its sign. */
8358 int next_code;
8359
8360 intel_match_token (cur_token.code);
8361 next_code = cur_token.code;
8362 intel_putback_token ();
8363 if (next_code == T_CONST)
8364 break;
8365 }
8366
8367 /* e09 OFFSET e09 */
8368 if (cur_token.code == T_OFFSET)
8369 {
8370 if (!in_offset++)
8371 ++intel_parser.in_offset;
8372 }
8373
8374 /* e09 SHORT e09 */
8375 else if (cur_token.code == T_SHORT)
8376 intel_parser.op_modifier |= 1 << T_SHORT;
8377
8378 /* e09 + e09 */
8379 else if (cur_token.code == '+')
8380 strcat (intel_parser.disp, "+");
8381
8382 /* e09 - e09
8383 | ~ e09
8384 | NOT e09 */
8385 else if (cur_token.code == '-' || cur_token.code == '~')
8386 {
8387 char str[2];
64a0c779 8388
a724f0f4
JB		 8389 if (nregs < 0)
8390 nregs = ~nregs;
8391 str[0] = cur_token.code;
8392 str[1] = 0;
8393 strcat (intel_parser.disp, str);
8394 }
8395
8396 /* e09 e10 e09' */
8397 else
8398 break;
8399
8400 intel_match_token (cur_token.code);
64a0c779
DN		 8401 }
8402
a724f0f4 8403 for (;;)
9306ca4a 8404 {
a724f0f4
JB		 8405 if (!intel_e10 ())
8406 return 0;
9306ca4a 8407
a724f0f4
JB		 8408 /* e09' PTR e10 e09' */
8409 if (cur_token.code == T_PTR)
8410 {
8411 char suffix;
9306ca4a 8412
a724f0f4 8413 if (prev_token.code == T_BYTE)
7d5e4556
L		 8414 {
8415 suffix = BYTE_MNEM_SUFFIX;
8416 i.types[this_operand].bitfield.byte = 1;
8417 }
9306ca4a 8418
a724f0f4
JB		 8419 else if (prev_token.code == T_WORD)
8420 {
34b772a6
JB		 8421 if ((current_templates->start->name[0] == 'l'
8422 && current_templates->start->name[2] == 's'
8423 && current_templates->start->name[3] == 0)
8424 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 8425 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8426 else if (intel_parser.got_a_float == 2) /* "fi..." */
8427 suffix = SHORT_MNEM_SUFFIX;
8428 else
8429 suffix = WORD_MNEM_SUFFIX;
7d5e4556 8430 i.types[this_operand].bitfield.word = 1;
a724f0f4 8431 }
64a0c779 8432
a724f0f4
JB		 8433 else if (prev_token.code == T_DWORD)
8434 {
34b772a6
JB		 8435 if ((current_templates->start->name[0] == 'l'
8436 && current_templates->start->name[2] == 's'
8437 && current_templates->start->name[3] == 0)
8438 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 8439 suffix = WORD_MNEM_SUFFIX;
8440 else if (flag_code == CODE_16BIT
40fb9820
L		 8441 && (current_templates->start->opcode_modifier.jump
8442 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8443 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8444 else if (intel_parser.got_a_float == 1) /* "f..." */
8445 suffix = SHORT_MNEM_SUFFIX;
8446 else
8447 suffix = LONG_MNEM_SUFFIX;
7d5e4556 8448 i.types[this_operand].bitfield.dword = 1;
a724f0f4 8449 }
9306ca4a 8450
a724f0f4
JB		 8451 else if (prev_token.code == T_FWORD)
8452 {
8453 if (current_templates->start->name[0] == 'l'
8454 && current_templates->start->name[2] == 's'
8455 && current_templates->start->name[3] == 0)
8456 suffix = LONG_MNEM_SUFFIX;
8457 else if (!intel_parser.got_a_float)
8458 {
8459 if (flag_code == CODE_16BIT)
8460 add_prefix (DATA_PREFIX_OPCODE);
8461 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8462 }
8463 else
8464 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 8465 i.types[this_operand].bitfield.fword = 1;
a724f0f4 8466 }
64a0c779 8467
a724f0f4
JB		 8468 else if (prev_token.code == T_QWORD)
8469 {
34b772a6
JB		 8470 if (current_templates->start->base_opcode == 0x62 /* bound */
8471 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 8472 suffix = LONG_MNEM_SUFFIX;
8473 else
34b772a6 8474 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 8475 i.types[this_operand].bitfield.qword = 1;
a724f0f4 8476 }
64a0c779 8477
a724f0f4
JB		 8478 else if (prev_token.code == T_TBYTE)
8479 {
8480 if (intel_parser.got_a_float == 1)
8481 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8482 else
8483 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8484 }
9306ca4a 8485
a724f0f4 8486 else if (prev_token.code == T_XMMWORD)
9306ca4a 8487 {
582d5edd 8488 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 8489 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 8490 }
64a0c779 8491
f16b83df 8492 else
a724f0f4
JB		 8493 {
8494 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8495 return 0;
8496 }
8497
7d5e4556
L		 8498 i.types[this_operand].bitfield.unspecified = 0;
8499
435acd52
JB		 8500 /* Operands for jump/call using 'ptr' notation denote absolute
8501 addresses. */
40fb9820
L		 8502 if (current_templates->start->opcode_modifier.jump
8503 || current_templates->start->opcode_modifier.jumpdword)
8504 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8505
a724f0f4
JB		 8506 if (current_templates->start->base_opcode == 0x8d /* lea */)
8507 ;
8508 else if (!i.suffix)
8509 i.suffix = suffix;
8510 else if (i.suffix != suffix)
8511 {
8512 as_bad (_("Conflicting operand modifiers"));
8513 return 0;
8514 }
64a0c779 8515
9306ca4a
JB		 8516 }
8517
a724f0f4
JB		 8518 /* e09' : e10 e09' */
8519 else if (cur_token.code == ':')
9306ca4a 8520 {
a724f0f4
JB		 8521 if (prev_token.code != T_REG)
8522 {
8523 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8524 segment/group identifier (which we don't have), using comma
8525 as the operand separator there is even less consistent, since
8526 there all branches only have a single operand. */
8527 if (this_operand != 0
8528 || intel_parser.in_offset
8529 || intel_parser.in_bracket
40fb9820
L		 8530 || (!current_templates->start->opcode_modifier.jump
8531 && !current_templates->start->opcode_modifier.jumpdword
8532 && !current_templates->start->opcode_modifier.jumpintersegment
8533 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8534 return intel_match_token (T_NIL);
8535 /* Remember the start of the 2nd operand and terminate 1st
8536 operand here.
8537 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8538 another expression), but it gets at least the simplest case
8539 (a plain number or symbol on the left side) right. */
8540 intel_parser.next_operand = intel_parser.op_string;
8541 *--intel_parser.op_string = '\0';
8542 return intel_match_token (':');
8543 }
9306ca4a 8544 }
64a0c779 8545
a724f0f4 8546 /* e09' Empty */
64a0c779 8547 else
a724f0f4 8548 break;
64a0c779 8549
a724f0f4
JB		 8550 intel_match_token (cur_token.code);
8551
8552 }
8553
8554 if (in_offset)
8555 {
8556 --intel_parser.in_offset;
8557 if (nregs < 0)
8558 nregs = ~nregs;
8559 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8560 {
a724f0f4 8561 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8562 return 0;
8563 }
a724f0f4
JB		 8564 intel_parser.op_modifier |= 1 << T_OFFSET;
8565 }
9306ca4a 8566
a724f0f4
JB		 8567 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8568 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8569 return 1;
8570}
64a0c779 8571
a724f0f4 8572static int
e3bb37b5 8573intel_bracket_expr (void)
a724f0f4
JB		 8574{
8575 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8576 const char *start = intel_parser.op_string;
8577 int len;
8578
8579 if (i.op[this_operand].regs)
8580 return intel_match_token (T_NIL);
8581
8582 intel_match_token ('[');
8583
8584 /* Mark as a memory operand only if it's not already known to be an
8585 offset expression. If it's an offset expression, we need to keep
8586 the brace in. */
8587 if (!intel_parser.in_offset)
8588 {
8589 ++intel_parser.in_bracket;
435acd52
JB		 8590
8591 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8592 if (current_templates->start->opcode_modifier.jump
8593 || current_templates->start->opcode_modifier.jumpdword)
8594 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8595
a724f0f4
JB		 8596 /* Unfortunately gas always diverged from MASM in a respect that can't
8597 be easily fixed without risking to break code sequences likely to be
8598 encountered (the testsuite even check for this): MASM doesn't consider
8599 an expression inside brackets unconditionally as a memory reference.
8600 When that is e.g. a constant, an offset expression, or the sum of the
8601 two, this is still taken as a constant load. gas, however, always
8602 treated these as memory references. As a compromise, we'll try to make
8603 offset expressions inside brackets work the MASM way (since that's
8604 less likely to be found in real world code), but make constants alone
8605 continue to work the traditional gas way. In either case, issue a
8606 warning. */
8607 intel_parser.op_modifier &= ~was_offset;
64a0c779 8608 }
a724f0f4 8609 else
64e74474 8610 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8611
8612 /* Add a '+' to the displacement string if necessary. */
8613 if (*intel_parser.disp != '\0'
8614 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8615 strcat (intel_parser.disp, "+");
64a0c779 8616
a724f0f4
JB		 8617 if (intel_expr ()
8618 && (len = intel_parser.op_string - start - 1,
8619 intel_match_token (']')))
64a0c779 8620 {
a724f0f4
JB		 8621 /* Preserve brackets when the operand is an offset expression. */
8622 if (intel_parser.in_offset)
8623 strcat (intel_parser.disp, "]");
8624 else
8625 {
8626 --intel_parser.in_bracket;
8627 if (i.base_reg || i.index_reg)
8628 intel_parser.is_mem = 1;
8629 if (!intel_parser.is_mem)
8630 {
8631 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8632 /* Defer the warning until all of the operand was parsed. */
8633 intel_parser.is_mem = -1;
8634 else if (!quiet_warnings)
4eed87de
AM		 8635 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8636 len, start, len, start);
a724f0f4
JB		 8637 }
8638 }
8639 intel_parser.op_modifier |= was_offset;
64a0c779 8640
a724f0f4 8641 return 1;
64a0c779 8642 }
a724f0f4 8643 return 0;
64a0c779
DN		 8644}
8645
8646/* e10 e11 e10'
8647
8648 e10' [ expr ] e10'
b77a7acd 8649 | Empty */
64a0c779 8650static int
e3bb37b5 8651intel_e10 (void)
64a0c779 8652{
a724f0f4
JB		 8653 if (!intel_e11 ())
8654 return 0;
64a0c779 8655
a724f0f4 8656 while (cur_token.code == '[')
64a0c779 8657 {
a724f0f4 8658 if (!intel_bracket_expr ())
21d6c4af 8659 return 0;
64a0c779
DN		 8660 }
8661
a724f0f4 8662 return 1;
64a0c779
DN		 8663}
8664
64a0c779 8665/* e11 ( expr )
b77a7acd 8666 | [ expr ]
64a0c779
DN		 8667 | BYTE
8668 | WORD
8669 | DWORD
9306ca4a 8670 | FWORD
64a0c779 8671 | QWORD
9306ca4a
JB		 8672 | TBYTE
8673 | OWORD
8674 | XMMWORD
4a1805b1 8675 | $
64a0c779
DN		 8676 | .
8677 | register
8678 | id
8679 | constant */
8680static int
e3bb37b5 8681intel_e11 (void)
64a0c779 8682{
a724f0f4 8683 switch (cur_token.code)
64a0c779 8684 {
a724f0f4
JB		 8685 /* e11 ( expr ) */
8686 case '(':
64a0c779
DN		 8687 intel_match_token ('(');
8688 strcat (intel_parser.disp, "(");
8689
8690 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8691 {
8692 strcat (intel_parser.disp, ")");
8693 return 1;
8694 }
a724f0f4 8695 return 0;
4a1805b1 8696
a724f0f4
JB		 8697 /* e11 [ expr ] */
8698 case '[':
a724f0f4 8699 return intel_bracket_expr ();
64a0c779 8700
a724f0f4
JB		 8701 /* e11 $
8702 | . */
8703 case '.':
64a0c779
DN		 8704 strcat (intel_parser.disp, cur_token.str);
8705 intel_match_token (cur_token.code);
21d6c4af
DN		 8706
8707 /* Mark as a memory operand only if it's not already known to be an
8708 offset expression. */
a724f0f4 8709 if (!intel_parser.in_offset)
21d6c4af 8710 intel_parser.is_mem = 1;
64a0c779
DN		 8711
8712 return 1;
64a0c779 8713
a724f0f4
JB		 8714 /* e11 register */
8715 case T_REG:
8716 {
8717 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8718
a724f0f4 8719 intel_match_token (T_REG);
64a0c779 8720
a724f0f4
JB		 8721 /* Check for segment change. */
8722 if (cur_token.code == ':')
8723 {
40fb9820
L		 8724 if (!reg->reg_type.bitfield.sreg2
8725 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8726 {
4eed87de
AM		 8727 as_bad (_("`%s' is not a valid segment register"),
8728 reg->reg_name);
a724f0f4
JB		 8729 return 0;
8730 }
b7240065
JB		 8731 else if (i.mem_operands >= 2)
8732 as_warn (_("Segment override ignored"));
a724f0f4
JB		 8733 else if (i.seg[i.mem_operands])
8734 as_warn (_("Extra segment override ignored"));
8735 else
8736 {
8737 if (!intel_parser.in_offset)
8738 intel_parser.is_mem = 1;
8739 switch (reg->reg_num)
8740 {
8741 case 0:
8742 i.seg[i.mem_operands] = &es;
8743 break;
8744 case 1:
8745 i.seg[i.mem_operands] = &cs;
8746 break;
8747 case 2:
8748 i.seg[i.mem_operands] = &ss;
8749 break;
8750 case 3:
8751 i.seg[i.mem_operands] = &ds;
8752 break;
8753 case 4:
8754 i.seg[i.mem_operands] = &fs;
8755 break;
8756 case 5:
8757 i.seg[i.mem_operands] = &gs;
8758 break;
8759 }
8760 }
8761 }
64a0c779 8762
b7240065
JB		 8763 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
8764 {
8765 as_bad (_("cannot use `FLAT' here"));
8766 return 0;
8767 }
8768
a724f0f4
JB		 8769 /* Not a segment register. Check for register scaling. */
8770 else if (cur_token.code == '*')
8771 {
8772 if (!intel_parser.in_bracket)
8773 {
8774 as_bad (_("Register scaling only allowed in memory operands"));
8775 return 0;
8776 }
64a0c779 8777
40fb9820 8778 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8779 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8780 else if (i.index_reg)
8781 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8782
a724f0f4
JB		 8783 /* What follows must be a valid scale. */
8784 intel_match_token ('*');
8785 i.index_reg = reg;
40fb9820 8786 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8787
a724f0f4
JB		 8788 /* Set the scale after setting the register (otherwise,
8789 i386_scale will complain) */
8790 if (cur_token.code == '+' || cur_token.code == '-')
8791 {
8792 char *str, sign = cur_token.code;
8793 intel_match_token (cur_token.code);
8794 if (cur_token.code != T_CONST)
8795 {
8796 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8797 cur_token.str);
8798 return 0;
8799 }
8800 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8801 strcpy (str + 1, cur_token.str);
8802 *str = sign;
8803 if (!i386_scale (str))
8804 return 0;
8805 free (str);
8806 }
8807 else if (!i386_scale (cur_token.str))
64a0c779 8808 return 0;
a724f0f4
JB		 8809 intel_match_token (cur_token.code);
8810 }
64a0c779 8811
a724f0f4
JB		 8812 /* No scaling. If this is a memory operand, the register is either a
8813 base register (first occurrence) or an index register (second
8814 occurrence). */
7b0441f6 8815 else if (intel_parser.in_bracket)
a724f0f4 8816 {
64a0c779 8817
a724f0f4
JB		 8818 if (!i.base_reg)
8819 i.base_reg = reg;
8820 else if (!i.index_reg)
8821 i.index_reg = reg;
8822 else
8823 {
8824 as_bad (_("Too many register references in memory operand"));
8825 return 0;
8826 }
64a0c779 8827
40fb9820 8828 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8829 }
4a1805b1 8830
4d1bb795
JB		 8831 /* It's neither base nor index. */
8832 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8833 {
40fb9820
L		 8834 i386_operand_type temp = reg->reg_type;
8835 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8836 i.types[this_operand] = operand_type_or (i.types[this_operand],
8837 temp);
7d5e4556 8838 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 8839 i.op[this_operand].regs = reg;
8840 i.reg_operands++;
8841 }
8842 else
8843 {
8844 as_bad (_("Invalid use of register"));
8845 return 0;
8846 }
64a0c779 8847
a724f0f4
JB		 8848 /* Since registers are not part of the displacement string (except
8849 when we're parsing offset operands), we may need to remove any
8850 preceding '+' from the displacement string. */
8851 if (*intel_parser.disp != '\0'
8852 && !intel_parser.in_offset)
8853 {
8854 char *s = intel_parser.disp;
8855 s += strlen (s) - 1;
8856 if (*s == '+')
8857 *s = '\0';
8858 }
4a1805b1 8859
a724f0f4
JB		 8860 return 1;
8861 }
8862
8863 /* e11 BYTE
8864 | WORD
8865 | DWORD
8866 | FWORD
8867 | QWORD
8868 | TBYTE
8869 | OWORD
8870 | XMMWORD */
8871 case T_BYTE:
8872 case T_WORD:
8873 case T_DWORD:
8874 case T_FWORD:
8875 case T_QWORD:
8876 case T_TBYTE:
8877 case T_XMMWORD:
8878 intel_match_token (cur_token.code);
64a0c779 8879
a724f0f4
JB		 8880 if (cur_token.code == T_PTR)
8881 return 1;
8882
8883 /* It must have been an identifier. */
8884 intel_putback_token ();
8885 cur_token.code = T_ID;
8886 /* FALLTHRU */
8887
8888 /* e11 id
8889 | constant */
8890 case T_ID:
8891 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8892 {
8893 symbolS *symbolP;
8894
a724f0f4
JB		 8895 /* The identifier represents a memory reference only if it's not
8896 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8897 symbolP = symbol_find(cur_token.str);
8898 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8899 intel_parser.is_mem = 1;
8900 }
a724f0f4 8901 /* FALLTHRU */
64a0c779 8902
a724f0f4
JB		 8903 case T_CONST:
8904 case '-':
8905 case '+':
8906 {
8907 char *save_str, sign = 0;
64a0c779 8908
a724f0f4
JB		 8909 /* Allow constants that start with `+' or `-'. */
8910 if (cur_token.code == '-' || cur_token.code == '+')
8911 {
8912 sign = cur_token.code;
8913 intel_match_token (cur_token.code);
8914 if (cur_token.code != T_CONST)
8915 {
8916 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8917 cur_token.str);
8918 return 0;
8919 }
8920 }
64a0c779 8921
a724f0f4
JB		 8922 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8923 strcpy (save_str + !!sign, cur_token.str);
8924 if (sign)
8925 *save_str = sign;
64a0c779 8926
a724f0f4
JB		 8927 /* Get the next token to check for register scaling. */
8928 intel_match_token (cur_token.code);
64a0c779 8929
4eed87de
AM		 8930 /* Check if this constant is a scaling factor for an
8931 index register. */
a724f0f4
JB		 8932 if (cur_token.code == '*')
8933 {
8934 if (intel_match_token ('*') && cur_token.code == T_REG)
8935 {
8936 const reg_entry *reg = cur_token.reg;
8937
8938 if (!intel_parser.in_bracket)
8939 {
4eed87de
AM		 8940 as_bad (_("Register scaling only allowed "
8941 "in memory operands"));
a724f0f4
JB		 8942 return 0;
8943 }
8944
4eed87de
AM		 8945 /* Disallow things like [1*si].
8946 sp and esp are invalid as index. */
40fb9820 8947 if (reg->reg_type.bitfield.reg16)
4eed87de 8948 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8949 else if (i.index_reg)
4eed87de 8950 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8951
8952 /* The constant is followed by `* reg', so it must be
8953 a valid scale. */
8954 i.index_reg = reg;
40fb9820 8955 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8956
8957 /* Set the scale after setting the register (otherwise,
8958 i386_scale will complain) */
8959 if (!i386_scale (save_str))
64a0c779 8960 return 0;
a724f0f4
JB		 8961 intel_match_token (T_REG);
8962
8963 /* Since registers are not part of the displacement
8964 string, we may need to remove any preceding '+' from
8965 the displacement string. */
8966 if (*intel_parser.disp != '\0')
8967 {
8968 char *s = intel_parser.disp;
8969 s += strlen (s) - 1;
8970 if (*s == '+')
8971 *s = '\0';
8972 }
8973
8974 free (save_str);
8975
8976 return 1;
8977 }
64a0c779 8978
a724f0f4
JB		 8979 /* The constant was not used for register scaling. Since we have
8980 already consumed the token following `*' we now need to put it
8981 back in the stream. */
64a0c779 8982 intel_putback_token ();
a724f0f4 8983 }
64a0c779 8984
a724f0f4
JB		 8985 /* Add the constant to the displacement string. */
8986 strcat (intel_parser.disp, save_str);
8987 free (save_str);
64a0c779 8988
a724f0f4
JB		 8989 return 1;
8990 }
64a0c779
DN		 8991 }
8992
64a0c779
DN		 8993 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8994 return 0;
8995}
8996
64a0c779
DN		 8997/* Match the given token against cur_token. If they match, read the next
8998 token from the operand string. */
8999static int
e3bb37b5 9000intel_match_token (int code)
64a0c779
DN		 9001{
9002 if (cur_token.code == code)
9003 {
9004 intel_get_token ();
9005 return 1;
9006 }
9007 else
9008 {
0477af35 9009 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9010 return 0;
9011 }
9012}
9013
64a0c779
DN		 9014/* Read a new token from intel_parser.op_string and store it in cur_token. */
9015static void
e3bb37b5 9016intel_get_token (void)
64a0c779
DN		 9017{
9018 char *end_op;
9019 const reg_entry *reg;
9020 struct intel_token new_token;
9021
9022 new_token.code = T_NIL;
9023 new_token.reg = NULL;
9024 new_token.str = NULL;
9025
4a1805b1 9026 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9027 cur_token to prev_token. */
9028 if (prev_token.str)
9029 free (prev_token.str);
9030
9031 prev_token = cur_token;
9032
9033 /* Skip whitespace. */
9034 while (is_space_char (*intel_parser.op_string))
9035 intel_parser.op_string++;
9036
9037 /* Return an empty token if we find nothing else on the line. */
9038 if (*intel_parser.op_string == '\0')
9039 {
9040 cur_token = new_token;
9041 return;
9042 }
9043
9044 /* The new token cannot be larger than the remainder of the operand
9045 string. */
a724f0f4 9046 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9047 new_token.str[0] = '\0';
9048
9049 if (strchr ("0123456789", *intel_parser.op_string))
9050 {
9051 char *p = new_token.str;
9052 char *q = intel_parser.op_string;
9053 new_token.code = T_CONST;
9054
9055 /* Allow any kind of identifier char to encompass floating point and
9056 hexadecimal numbers. */
9057 while (is_identifier_char (*q))
9058 *p++ = *q++;
9059 *p = '\0';
9060
9061 /* Recognize special symbol names [0-9][bf]. */
9062 if (strlen (intel_parser.op_string) == 2
4a1805b1 9063 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9064 || intel_parser.op_string[1] == 'f'))
9065 new_token.code = T_ID;
9066 }
9067
4d1bb795 9068 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9069 {
4d1bb795
JB		 9070 size_t len = end_op - intel_parser.op_string;
9071
64a0c779
DN		 9072 new_token.code = T_REG;
9073 new_token.reg = reg;
9074
4d1bb795
JB		 9075 memcpy (new_token.str, intel_parser.op_string, len);
9076 new_token.str[len] = '\0';
64a0c779
DN		 9077 }
9078
9079 else if (is_identifier_char (*intel_parser.op_string))
9080 {
9081 char *p = new_token.str;
9082 char *q = intel_parser.op_string;
9083
9084 /* A '.' or '$' followed by an identifier char is an identifier.
9085 Otherwise, it's operator '.' followed by an expression. */
9086 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9087 {
9306ca4a
JB		 9088 new_token.code = '.';
9089 new_token.str[0] = '.';
64a0c779
DN		 9090 new_token.str[1] = '\0';
9091 }
9092 else
9093 {
9094 while (is_identifier_char (*q) || *q == '@')
9095 *p++ = *q++;
9096 *p = '\0';
9097
9306ca4a
JB		 9098 if (strcasecmp (new_token.str, "NOT") == 0)
9099 new_token.code = '~';
9100
9101 else if (strcasecmp (new_token.str, "MOD") == 0)
9102 new_token.code = '%';
9103
9104 else if (strcasecmp (new_token.str, "AND") == 0)
9105 new_token.code = '&';
9106
9107 else if (strcasecmp (new_token.str, "OR") == 0)
9108 new_token.code = '|';
9109
9110 else if (strcasecmp (new_token.str, "XOR") == 0)
9111 new_token.code = '^';
9112
9113 else if (strcasecmp (new_token.str, "SHL") == 0)
9114 new_token.code = T_SHL;
9115
9116 else if (strcasecmp (new_token.str, "SHR") == 0)
9117 new_token.code = T_SHR;
9118
9119 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9120 new_token.code = T_BYTE;
9121
9122 else if (strcasecmp (new_token.str, "WORD") == 0)
9123 new_token.code = T_WORD;
9124
9125 else if (strcasecmp (new_token.str, "DWORD") == 0)
9126 new_token.code = T_DWORD;
9127
9306ca4a
JB		 9128 else if (strcasecmp (new_token.str, "FWORD") == 0)
9129 new_token.code = T_FWORD;
9130
64a0c779
DN		 9131 else if (strcasecmp (new_token.str, "QWORD") == 0)
9132 new_token.code = T_QWORD;
9133
9306ca4a
JB		 9134 else if (strcasecmp (new_token.str, "TBYTE") == 0
9135 /* XXX remove (gcc still uses it) */
9136 || strcasecmp (new_token.str, "XWORD") == 0)
9137 new_token.code = T_TBYTE;
9138
9139 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9140 || strcasecmp (new_token.str, "OWORD") == 0)
9141 new_token.code = T_XMMWORD;
64a0c779
DN		 9142
9143 else if (strcasecmp (new_token.str, "PTR") == 0)
9144 new_token.code = T_PTR;
9145
9146 else if (strcasecmp (new_token.str, "SHORT") == 0)
9147 new_token.code = T_SHORT;
9148
9149 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9150 {
9151 new_token.code = T_OFFSET;
9152
9153 /* ??? This is not mentioned in the MASM grammar but gcc
9154 makes use of it with -mintel-syntax. OFFSET may be
9155 followed by FLAT: */
9156 if (strncasecmp (q, " FLAT:", 6) == 0)
9157 strcat (new_token.str, " FLAT:");
9158 }
9159
64a0c779
DN		 9160 else
9161 new_token.code = T_ID;
9162 }
9163 }
9164
9306ca4a
JB		 9165 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9166 {
9167 new_token.code = *intel_parser.op_string;
9168 new_token.str[0] = *intel_parser.op_string;
9169 new_token.str[1] = '\0';
9170 }
9171
9172 else if (strchr ("<>", *intel_parser.op_string)
9173 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9174 {
9175 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9176 new_token.str[0] = *intel_parser.op_string;
9177 new_token.str[1] = *intel_parser.op_string;
9178 new_token.str[2] = '\0';
9179 }
9180
64a0c779 9181 else
0477af35 9182 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9183
9184 intel_parser.op_string += strlen (new_token.str);
9185 cur_token = new_token;
9186}
9187
64a0c779
DN		 9188/* Put cur_token back into the token stream and make cur_token point to
9189 prev_token. */
9190static void
e3bb37b5 9191intel_putback_token (void)
64a0c779 9192{
a724f0f4
JB		 9193 if (cur_token.code != T_NIL)
9194 {
9195 intel_parser.op_string -= strlen (cur_token.str);
9196 free (cur_token.str);
9197 }
64a0c779 9198 cur_token = prev_token;
4a1805b1 9199
64a0c779
DN		 9200 /* Forget prev_token. */
9201 prev_token.code = T_NIL;
9202 prev_token.reg = NULL;
9203 prev_token.str = NULL;
9204}
54cfded0 9205
a60de03c
JB		 9206void
9207tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9208{
a60de03c
JB		 9209 int saved_naked_reg;
9210 char saved_register_dot;
54cfded0 9211
a60de03c
JB		 9212 saved_naked_reg = allow_naked_reg;
9213 allow_naked_reg = 1;
9214 saved_register_dot = register_chars['.'];
9215 register_chars['.'] = '.';
9216 allow_pseudo_reg = 1;
9217 expression_and_evaluate (exp);
9218 allow_pseudo_reg = 0;
9219 register_chars['.'] = saved_register_dot;
9220 allow_naked_reg = saved_naked_reg;
9221
9222 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9223 {
a60de03c
JB		 9224 if ((addressT) exp->X_add_number < i386_regtab_size)
9225 {
9226 exp->X_op = O_constant;
9227 exp->X_add_number = i386_regtab[exp->X_add_number]
9228 .dw2_regnum[flag_code >> 1];
9229 }
9230 else
9231 exp->X_op = O_illegal;
54cfded0 9232 }
54cfded0
AM		 9233}
9234
9235void
9236tc_x86_frame_initial_instructions (void)
9237{
a60de03c
JB		 9238 static unsigned int sp_regno[2];
9239
9240 if (!sp_regno[flag_code >> 1])
9241 {
9242 char *saved_input = input_line_pointer;
9243 char sp[][4] = {"esp", "rsp"};
9244 expressionS exp;
a4447b93 9245
a60de03c
JB		 9246 input_line_pointer = sp[flag_code >> 1];
9247 tc_x86_parse_to_dw2regnum (&exp);
9248 assert (exp.X_op == O_constant);
9249 sp_regno[flag_code >> 1] = exp.X_add_number;
9250 input_line_pointer = saved_input;
9251 }
a4447b93 9252
a60de03c 9253 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9254 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9255}
d2b2c203
DJ		 9256
9257int
9258i386_elf_section_type (const char *str, size_t len)
9259{
9260 if (flag_code == CODE_64BIT
9261 && len == sizeof ("unwind") - 1
9262 && strncmp (str, "unwind", 6) == 0)
9263 return SHT_X86_64_UNWIND;
9264
9265 return -1;
9266}
bb41ade5
AM		 9267
9268#ifdef TE_PE
9269void
9270tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9271{
9272 expressionS expr;
9273
9274 expr.X_op = O_secrel;
9275 expr.X_add_symbol = symbol;
9276 expr.X_add_number = 0;
9277 emit_expr (&expr, size);
9278}
9279#endif
3b22753a
L		 9280
9281#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9282/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9283
9284int
9285x86_64_section_letter (int letter, char **ptr_msg)
9286{
9287 if (flag_code == CODE_64BIT)
9288 {
9289 if (letter == 'l')
9290 return SHF_X86_64_LARGE;
9291
9292 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9293 }
3b22753a 9294 else
64e74474 9295 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9296 return -1;
9297}
9298
9299int
9300x86_64_section_word (char *str, size_t len)
9301{
8620418b 9302 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9303 return SHF_X86_64_LARGE;
9304
9305 return -1;
9306}
9307
9308static void
9309handle_large_common (int small ATTRIBUTE_UNUSED)
9310{
9311 if (flag_code != CODE_64BIT)
9312 {
9313 s_comm_internal (0, elf_common_parse);
9314 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9315 }
9316 else
9317 {
9318 static segT lbss_section;
9319 asection *saved_com_section_ptr = elf_com_section_ptr;
9320 asection *saved_bss_section = bss_section;
9321
9322 if (lbss_section == NULL)
9323 {
9324 flagword applicable;
9325 segT seg = now_seg;
9326 subsegT subseg = now_subseg;
9327
9328 /* The .lbss section is for local .largecomm symbols. */
9329 lbss_section = subseg_new (".lbss", 0);
9330 applicable = bfd_applicable_section_flags (stdoutput);
9331 bfd_set_section_flags (stdoutput, lbss_section,
9332 applicable & SEC_ALLOC);
9333 seg_info (lbss_section)->bss = 1;
9334
9335 subseg_set (seg, subseg);
9336 }
9337
9338 elf_com_section_ptr = &_bfd_elf_large_com_section;
9339 bss_section = lbss_section;
9340
9341 s_comm_internal (0, elf_common_parse);
9342
9343 elf_com_section_ptr = saved_com_section_ptr;
9344 bss_section = saved_bss_section;
9345 }
9346}
9347#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.08698 seconds and 4 git commands to generate.