Make -mlittle-endian switch set the target_big_endian variable to false.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.h
CommitLineData
252b5132 1/* tc-i386.h -- Header file for tc-i386.c
f7e42eb4 2 Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
0f10071e 3 2001, 2002, 2003, 2004
f7e42eb4 4 Free Software Foundation, Inc.
252b5132
RH
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23#ifndef TC_I386
24#define TC_I386 1
25
f86103b7
AM
26#ifndef BFD_ASSEMBLER
27#error So, do you know what you are doing?
28#endif
29
252b5132
RH
30#ifdef ANSI_PROTOTYPES
31struct fix;
32#endif
33
34#define TARGET_BYTES_BIG_ENDIAN 0
35
252b5132 36#define TARGET_ARCH bfd_arch_i386
b9d79e03 37#define TARGET_MACH (i386_mach ())
b7c92712 38extern unsigned long i386_mach (void);
252b5132 39
cac5b87b
DB
40#ifdef TE_FreeBSD
41#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
42#endif
252b5132 43#ifdef TE_NetBSD
4c63da97 44#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
252b5132
RH
45#endif
46#ifdef TE_386BSD
4c63da97 47#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
252b5132
RH
48#endif
49#ifdef TE_LINUX
4c63da97 50#define AOUT_TARGET_FORMAT "a.out-i386-linux"
252b5132
RH
51#endif
52#ifdef TE_Mach
4c63da97 53#define AOUT_TARGET_FORMAT "a.out-mach3"
252b5132
RH
54#endif
55#ifdef TE_DYNIX
4c63da97 56#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
252b5132 57#endif
4c63da97
AM
58#ifndef AOUT_TARGET_FORMAT
59#define AOUT_TARGET_FORMAT "a.out-i386"
252b5132 60#endif
252b5132 61
4ada7262
DB
62#ifdef TE_FreeBSD
63#define ELF_TARGET_FORMAT "elf32-i386-freebsd"
64#endif
65#ifndef ELF_TARGET_FORMAT
66#define ELF_TARGET_FORMAT "elf32-i386"
67#endif
68
3e73aa7c
JH
69#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
70 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4c63da97
AM
71extern const char *i386_target_format PARAMS ((void));
72#define TARGET_FORMAT i386_target_format ()
73#else
252b5132 74#ifdef OBJ_ELF
4ada7262 75#define TARGET_FORMAT ELF_TARGET_FORMAT
252b5132 76#endif
4c63da97
AM
77#ifdef OBJ_AOUT
78#define TARGET_FORMAT AOUT_TARGET_FORMAT
252b5132
RH
79#endif
80#endif
81
a847613f
AM
82#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
83#define md_end i386_elf_emit_arch_note
84extern void i386_elf_emit_arch_note PARAMS ((void));
85#endif
86
18e1d487
AM
87#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
88
6088b00e 89#define LOCAL_LABELS_FB 1
252b5132
RH
90
91extern const char extra_symbol_chars[];
92#define tc_symbol_chars extra_symbol_chars
93
94#define MAX_OPERANDS 3 /* max operands per insn */
95#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
96#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
97
98/* Prefixes will be emitted in the order defined below.
99 WAIT_PREFIX must be the first prefix since FWAIT is really is an
4a4f25cf 100 instruction, and so must come before any prefixes. */
252b5132
RH
101#define WAIT_PREFIX 0
102#define LOCKREP_PREFIX 1
103#define ADDR_PREFIX 2
104#define DATA_PREFIX 3
105#define SEG_PREFIX 4
3e73aa7c
JH
106#define REX_PREFIX 5 /* must come last. */
107#define MAX_PREFIXES 6 /* max prefixes per opcode */
252b5132
RH
108
109/* we define the syntax here (modulo base,index,scale syntax) */
110#define REGISTER_PREFIX '%'
111#define IMMEDIATE_PREFIX '$'
112#define ABSOLUTE_PREFIX '*'
113
114#define TWO_BYTE_OPCODE_ESCAPE 0x0f
115#define NOP_OPCODE (char) 0x90
116
117/* register numbers */
118#define EBP_REG_NUM 5
119#define ESP_REG_NUM 4
120
121/* modrm_byte.regmem for twobyte escape */
122#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
123/* index_base_byte.index for no index register addressing */
124#define NO_INDEX_REGISTER ESP_REG_NUM
125/* index_base_byte.base for no base register addressing */
126#define NO_BASE_REGISTER EBP_REG_NUM
127#define NO_BASE_REGISTER_16 6
128
129/* these are the instruction mnemonic suffixes. */
252b5132
RH
130#define WORD_MNEM_SUFFIX 'w'
131#define BYTE_MNEM_SUFFIX 'b'
132#define SHORT_MNEM_SUFFIX 's'
133#define LONG_MNEM_SUFFIX 'l'
3e73aa7c 134#define QWORD_MNEM_SUFFIX 'q'
252b5132
RH
135/* Intel Syntax */
136#define LONG_DOUBLE_MNEM_SUFFIX 'x'
252b5132
RH
137
138/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
139#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
140#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
141
142#define END_OF_INSN '\0'
143
252b5132
RH
144typedef struct
145{
146 /* instruction name sans width suffix ("mov" for movl insns) */
147 char *name;
148
149 /* how many operands */
150 unsigned int operands;
151
152 /* base_opcode is the fundamental opcode byte without optional
153 prefix(es). */
154 unsigned int base_opcode;
155
156 /* extension_opcode is the 3 bit extension for group <n> insns.
157 This field is also used to store the 8-bit opcode suffix for the
158 AMD 3DNow! instructions.
159 If this template has no extension opcode (the usual case) use None */
160 unsigned int extension_opcode;
4a4f25cf 161#define None 0xffff /* If no extension_opcode is possible. */
252b5132 162
e413e4e9
AM
163 /* cpu feature flags */
164 unsigned int cpu_flags;
165#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
166#define Cpu186 0x2 /* i186 or better required */
167#define Cpu286 0x4 /* i286 or better required */
168#define Cpu386 0x8 /* i386 or better required */
169#define Cpu486 0x10 /* i486 or better required */
170#define Cpu586 0x20 /* i585 or better required */
171#define Cpu686 0x40 /* i686 or better required */
6f8c0c4c
JH
172#define CpuP4 0x80 /* Pentium4 or better required */
173#define CpuK6 0x100 /* AMD K6 or better required*/
174#define CpuAthlon 0x200 /* AMD Athlon or better required*/
175#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
176#define CpuMMX 0x800 /* MMX support required */
5c6af06e
JB
177#define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */
178#define CpuSSE 0x2000 /* Streaming SIMD extensions required */
179#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */
180#define Cpu3dnow 0x8000 /* 3dnow! support required */
181#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
182#define CpuPNI 0x20000 /* Prescott New Instructions required */
183#define CpuPadLock 0x40000 /* VIA PadLock required */
3e73aa7c
JH
184
185 /* These flags are set by gas depending on the flag_code. */
186#define Cpu64 0x4000000 /* 64bit support required */
187#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
188
189 /* The default value for unknown CPUs - enable all features to avoid problems. */
5c6af06e 190#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock)
e413e4e9 191
252b5132
RH
192 /* the bits in opcode_modifier are used to generate the final opcode from
193 the base_opcode. These bits also are used to detect alternate forms of
194 the same instruction */
195 unsigned int opcode_modifier;
196
197 /* opcode_modifier bits: */
198#define W 0x1 /* set if operands can be words or dwords
199 encoded the canonical way */
200#define D 0x2 /* D = 0 if Reg --> Regmem;
201 D = 1 if Regmem --> Reg: MUST BE 0x2 */
202#define Modrm 0x4
252b5132
RH
203#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
204#define ShortForm 0x10 /* register is in low 3 bits of opcode */
205#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
4a4f25cf 206#define Jump 0x40 /* special case for jump insns. */
252b5132
RH
207#define JumpDword 0x80 /* call and jump */
208#define JumpByte 0x100 /* loop and jecxz */
209#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
210#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
211#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
4a4f25cf 212#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
252b5132
RH
213#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
214#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
3e73aa7c
JH
215#define Size64 0x8000 /* needs size prefix if in 16-bit mode */
216#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
217#define DefaultSize 0x20000 /* default insn size depends on mode */
218#define No_bSuf 0x40000 /* b suffix on instruction illegal */
219#define No_wSuf 0x80000 /* w suffix on instruction illegal */
220#define No_lSuf 0x100000 /* l suffix on instruction illegal */
221#define No_sSuf 0x200000 /* s suffix on instruction illegal */
222#define No_qSuf 0x400000 /* q suffix on instruction illegal */
223#define No_xSuf 0x800000 /* x suffix on instruction illegal */
224#define FWait 0x1000000 /* instruction needs FWAIT */
225#define IsString 0x2000000 /* quick test for string instructions */
226#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
227#define IsPrefix 0x8000000 /* opcode is a prefix */
228#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
229#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
230#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
231#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
252b5132
RH
232
233 /* operand_types[i] describes the type of operand i. This is made
234 by OR'ing together all of the possible type masks. (e.g.
235 'operand_types[i] = Reg|Imm' specifies that operand i can be
e413e4e9 236 either a register or an immediate operand. */
252b5132 237 unsigned int operand_types[3];
e413e4e9
AM
238
239 /* operand_types[i] bits */
240 /* register */
241#define Reg8 0x1 /* 8 bit reg */
242#define Reg16 0x2 /* 16 bit reg */
243#define Reg32 0x4 /* 32 bit reg */
3e73aa7c 244#define Reg64 0x8 /* 64 bit reg */
e413e4e9 245 /* immediate */
3e73aa7c
JH
246#define Imm8 0x10 /* 8 bit immediate */
247#define Imm8S 0x20 /* 8 bit immediate sign extended */
248#define Imm16 0x40 /* 16 bit immediate */
249#define Imm32 0x80 /* 32 bit immediate */
250#define Imm32S 0x100 /* 32 bit immediate sign extended */
251#define Imm64 0x200 /* 64 bit immediate */
252#define Imm1 0x400 /* 1 bit immediate */
e413e4e9 253 /* memory */
3e73aa7c 254#define BaseIndex 0x800
e413e4e9
AM
255 /* Disp8,16,32 are used in different ways, depending on the
256 instruction. For jumps, they specify the size of the PC relative
257 displacement, for baseindex type instructions, they specify the
258 size of the offset relative to the base register, and for memory
259 offset instructions such as `mov 1234,%al' they specify the size of
260 the offset relative to the segment base. */
3e73aa7c
JH
261#define Disp8 0x1000 /* 8 bit displacement */
262#define Disp16 0x2000 /* 16 bit displacement */
263#define Disp32 0x4000 /* 32 bit displacement */
264#define Disp32S 0x8000 /* 32 bit signed displacement */
265#define Disp64 0x10000 /* 64 bit displacement */
e413e4e9 266 /* specials */
3e73aa7c
JH
267#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
268#define ShiftCount 0x40000 /* register to hold shift cound = cl */
269#define Control 0x80000 /* Control register */
270#define Debug 0x100000 /* Debug register */
271#define Test 0x200000 /* Test register */
272#define FloatReg 0x400000 /* Float register */
273#define FloatAcc 0x800000 /* Float stack top %st(0) */
274#define SReg2 0x1000000 /* 2 bit segment register */
275#define SReg3 0x2000000 /* 3 bit segment register */
276#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
277#define JumpAbsolute 0x8000000
278#define RegMMX 0x10000000 /* MMX register */
279#define RegXMM 0x20000000 /* XMM registers in PIII */
280#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
281
e413e4e9
AM
282 /* InvMem is for instructions with a modrm byte that only allow a
283 general register encoding in the i.tm.mode and i.tm.regmem fields,
284 eg. control reg moves. They really ought to support a memory form,
285 but don't, so we add an InvMem flag to the register operand to
286 indicate that it should be encoded in the i.tm.regmem field. */
3e73aa7c 287#define InvMem 0x80000000
e413e4e9 288
3e73aa7c
JH
289#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
290#define WordReg (Reg16|Reg32|Reg64)
e413e4e9 291#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
3e73aa7c
JH
292#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
293#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
294#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
295#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
e413e4e9
AM
296 /* The following aliases are defined because the opcode table
297 carefully specifies the allowed memory types for each instruction.
298 At the moment we can only tell a memory reference size by the
299 instruction suffix, so there's not much point in defining Mem8,
300 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
301 the suffix directly to check memory operands. */
302#define LLongMem AnyMem /* 64 bits (or more) */
303#define LongMem AnyMem /* 32 bit memory ref */
304#define ShortMem AnyMem /* 16 bit memory ref */
305#define WordMem AnyMem /* 16 or 32 bit memory ref */
306#define ByteMem AnyMem /* 8 bit memory ref */
252b5132
RH
307}
308template;
309
310/*
311 'templates' is for grouping together 'template' structures for opcodes
312 of the same name. This is only used for storing the insns in the grand
313 ole hash table of insns.
314 The templates themselves start at START and range up to (but not including)
315 END.
316 */
317typedef struct
e413e4e9
AM
318{
319 const template *start;
320 const template *end;
321}
322templates;
252b5132
RH
323
324/* these are for register name --> number & type hash lookup */
325typedef struct
e413e4e9
AM
326{
327 char *reg_name;
328 unsigned int reg_type;
3e73aa7c
JH
329 unsigned int reg_flags;
330#define RegRex 0x1 /* Extended register. */
331#define RegRex64 0x2 /* Extended 8 bit register. */
e413e4e9
AM
332 unsigned int reg_num;
333}
252b5132
RH
334reg_entry;
335
336typedef struct
e413e4e9
AM
337{
338 char *seg_name;
339 unsigned int seg_prefix;
340}
252b5132
RH
341seg_entry;
342
4a4f25cf 343/* 386 operand encoding bytes: see 386 book for details of this. */
252b5132 344typedef struct
e413e4e9
AM
345{
346 unsigned int regmem; /* codes register or memory operand */
347 unsigned int reg; /* codes register operand (or extended opcode) */
348 unsigned int mode; /* how to interpret regmem & reg */
349}
252b5132
RH
350modrm_byte;
351
3e73aa7c 352/* x86-64 extension prefix. */
29b0f896
AM
353typedef int rex_byte;
354#define REX_OPCODE 0x40
355
356/* Indicates 64 bit operand size. */
357#define REX_MODE64 8
358/* High extension to reg field of modrm byte. */
359#define REX_EXTX 4
360/* High extension to SIB index field. */
361#define REX_EXTY 2
362/* High extension to base field of modrm or SIB, or reg field of opcode. */
363#define REX_EXTZ 1
3e73aa7c 364
4a4f25cf 365/* 386 opcode byte to code indirect addressing. */
252b5132 366typedef struct
e413e4e9
AM
367{
368 unsigned base;
369 unsigned index;
370 unsigned scale;
371}
252b5132
RH
372sib_byte;
373
e413e4e9
AM
374/* x86 arch names and features */
375typedef struct
376{
377 const char *name; /* arch name */
378 unsigned int flags; /* cpu feature flags */
379}
380arch_entry;
381
252b5132 382/* The name of the global offset table generated by the compiler. Allow
4a4f25cf 383 this to be overridden if need be. */
252b5132
RH
384#ifndef GLOBAL_OFFSET_TABLE_NAME
385#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
386#endif
387
6088b00e
AM
388#ifndef LEX_AT
389#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
390extern void x86_cons PARAMS ((expressionS *, int));
391
392#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
393extern void x86_cons_fix_new
394 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
6482c264
NC
395#endif
396
397#ifdef TE_PE
398#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP)
399extern void x86_pe_cons_fix_new
400 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
6088b00e
AM
401#endif
402
403#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
404
6088b00e
AM
405#define NO_RELOC BFD_RELOC_NONE
406
252b5132 407void i386_validate_fix PARAMS ((struct fix *));
a161fe53 408#define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
6088b00e
AM
409
410#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
411extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
412
a161fe53
AM
413/* Values passed to md_apply_fix3 don't include the symbol value. */
414#define MD_APPLY_SYM_VALUE(FIX) 0
3ca4bdc3
AM
415
416/* ELF wants external syms kept, as does PE COFF. */
ae6063d4
AM
417#if defined (TE_PE) && defined (STRICT_PE_FORMAT)
418#define EXTERN_FORCE_RELOC \
3ca4bdc3
AM
419 (OUTPUT_FLAVOR == bfd_target_elf_flavour \
420 || OUTPUT_FLAVOR == bfd_target_coff_flavour)
421#else
422#define EXTERN_FORCE_RELOC \
423 (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132
RH
424#endif
425
a161fe53
AM
426/* This expression evaluates to true if the relocation is for a local
427 object for which we still want to do the relocation at runtime.
428 False if we are willing to perform this relocation while building
429 the .o file. GOTOFF does not need to be checked here because it is
430 not pcrel. I am not sure if some of the others are ever used with
6088b00e
AM
431 pcrel, but it is easier to be safe than sorry. */
432
a161fe53
AM
433#define TC_FORCE_RELOCATION_LOCAL(FIX) \
434 (!(FIX)->fx_pcrel \
435 || (FIX)->fx_plt \
436 || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
437 || (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \
438 || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
439 || TC_FORCE_RELOCATION (FIX))
6088b00e 440
252b5132
RH
441#define md_operand(x)
442
443extern const struct relax_type md_relax_table[];
444#define TC_GENERIC_RELAX_TABLE md_relax_table
445
12b55ccc
L
446extern int optimize_align_code;
447
252b5132 448#define md_do_align(n, fill, len, max, around) \
12b55ccc
L
449if ((n) \
450 && !need_pass_2 \
451 && optimize_align_code \
452 && (!(fill) \
453 || ((char)*(fill) == (char)0x90 && (len) == 1)) \
b9e57a38 454 && subseg_text_p (now_seg)) \
252b5132 455 { \
0a9ef439 456 frag_align_code ((n), (max)); \
252b5132
RH
457 goto around; \
458 }
459
0a9ef439
RH
460#define MAX_MEM_FOR_RS_ALIGN_CODE 15
461
252b5132
RH
462extern void i386_align_code PARAMS ((fragS *, int));
463
464#define HANDLE_ALIGN(fragP) \
465if (fragP->fr_type == rs_align_code) \
466 i386_align_code (fragP, (fragP->fr_next->fr_address \
467 - fragP->fr_address \
468 - fragP->fr_fix));
469
252b5132
RH
470void i386_print_statistics PARAMS ((FILE *));
471#define tc_print_statistics i386_print_statistics
472
473#define md_number_to_chars number_to_chars_littleendian
474
475#ifdef SCO_ELF
476#define tc_init_after_args() sco_id ()
477extern void sco_id PARAMS ((void));
478#endif
479
54cfded0 480/* We want .cfi_* pseudo-ops for generating unwind info. */
a4447b93 481#define TARGET_USE_CFIPOP 1
54cfded0 482
a4447b93
RH
483extern unsigned int x86_dwarf2_return_column;
484#define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
485
486extern int x86_cie_data_alignment;
487#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
54cfded0
AM
488
489#define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
a4447b93 490extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
54cfded0
AM
491
492#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
493extern void tc_x86_frame_initial_instructions PARAMS ((void));
494
d2b2c203
DJ
495#define md_elf_section_type(str,len) i386_elf_section_type (str, len)
496extern int i386_elf_section_type PARAMS ((const char *, size_t len));
497
bb41ade5
AM
498#ifdef TE_PE
499
500#define O_secrel O_md1
501
502#define TC_DWARF2_EMIT_OFFSET tc_pe_dwarf2_emit_offset
503void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
504
505#endif /* TE_PE */
506
6088b00e 507#endif /* TC_I386 */
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