Commit | Line | Data |
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305d537e | 1 | /* tc-i860.c -- Assembler for the Intel i860 architecture. |
14218d5f | 2 | Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003 |
305d537e JE |
3 | Free Software Foundation, Inc. |
4 | ||
5 | Brought back from the dead and completely reworked | |
6 | by Jason Eckhardt <jle@cygnus.com>. | |
252b5132 RH |
7 | |
8 | This file is part of GAS, the GNU Assembler. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License along | |
21 | with GAS; see the file COPYING. If not, write to the Free Software | |
22 | Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
305d537e JE |
24 | #include <stdio.h> |
25 | #include <string.h> | |
252b5132 | 26 | #include "as.h" |
3882b010 | 27 | #include "safe-ctype.h" |
305d537e | 28 | #include "subsegs.h" |
252b5132 | 29 | #include "opcode/i860.h" |
305d537e | 30 | #include "elf/i860.h" |
252b5132 | 31 | |
252b5132 | 32 | |
305d537e | 33 | /* The opcode hash table. */ |
252b5132 RH |
34 | static struct hash_control *op_hash = NULL; |
35 | ||
305d537e JE |
36 | /* These characters always start a comment. */ |
37 | const char comment_chars[] = "#!/"; | |
252b5132 | 38 | |
305d537e | 39 | /* These characters start a comment at the beginning of a line. */ |
252b5132 RH |
40 | const char line_comment_chars[] = "#/"; |
41 | ||
63a0b638 | 42 | const char line_separator_chars[] = ";"; |
252b5132 | 43 | |
305d537e JE |
44 | /* Characters that can be used to separate the mantissa from the exponent |
45 | in floating point numbers. */ | |
252b5132 RH |
46 | const char EXP_CHARS[] = "eE"; |
47 | ||
305d537e JE |
48 | /* Characters that indicate this number is a floating point constant. |
49 | As in 0f12.456 or 0d1.2345e12. */ | |
252b5132 RH |
50 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
51 | ||
87505968 JE |
52 | /* Register prefix (depends on syntax). */ |
53 | static char reg_prefix; | |
305d537e | 54 | |
673a54e3 JE |
55 | #define MAX_FIXUPS 2 |
56 | ||
252b5132 | 57 | struct i860_it |
305d537e JE |
58 | { |
59 | char *error; | |
60 | unsigned long opcode; | |
305d537e | 61 | enum expand_type expand; |
673a54e3 JE |
62 | struct i860_fi |
63 | { | |
64 | expressionS exp; | |
65 | bfd_reloc_code_real_type reloc; | |
66 | int pcrel; | |
67 | valueT fup; | |
68 | } fi[MAX_FIXUPS]; | |
305d537e JE |
69 | } the_insn; |
70 | ||
673a54e3 JE |
71 | /* The current fixup count. */ |
72 | static int fc; | |
73 | ||
305d537e | 74 | static char *expr_end; |
252b5132 | 75 | |
305d537e JE |
76 | /* Indicates error if a pseudo operation was expanded after a branch. */ |
77 | static char last_expand; | |
252b5132 | 78 | |
305d537e JE |
79 | /* If true, then warn if any pseudo operations were expanded. */ |
80 | static int target_warn_expand = 0; | |
252b5132 | 81 | |
14218d5f JE |
82 | /* If true, then XP support is enabled. */ |
83 | static int target_xp = 0; | |
84 | ||
87505968 JE |
85 | /* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax). */ |
86 | static int target_intel_syntax = 0; | |
87 | ||
88 | ||
305d537e | 89 | /* Prototypes. */ |
7734b6e9 JE |
90 | static void i860_process_insn (char *); |
91 | static void s_dual (int); | |
92 | static void s_enddual (int); | |
93 | static void s_atmp (int); | |
94 | static int i860_get_expression (char *); | |
95 | static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *); | |
305d537e | 96 | #ifdef DEBUG_I860 |
7734b6e9 | 97 | static void print_insn (struct i860_it *); |
305d537e | 98 | #endif |
252b5132 | 99 | |
305d537e JE |
100 | const pseudo_typeS md_pseudo_table[] = |
101 | { | |
102 | #ifdef OBJ_ELF | |
103 | {"align", s_align_bytes, 0}, | |
104 | #endif | |
105 | {"dual", s_dual, 0}, | |
106 | {"enddual", s_enddual, 0}, | |
107 | {"atmp", s_atmp, 0}, | |
108 | {NULL, 0, 0}, | |
109 | }; | |
110 | ||
305d537e | 111 | /* Dual-instruction mode handling. */ |
252b5132 RH |
112 | enum dual |
113 | { | |
114 | DUAL_OFF = 0, DUAL_ON, DUAL_DDOT, DUAL_ONDDOT, | |
115 | }; | |
305d537e JE |
116 | static enum dual dual_mode = DUAL_OFF; |
117 | ||
305d537e | 118 | /* Handle ".dual" directive. */ |
252b5132 | 119 | static void |
7734b6e9 | 120 | s_dual (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 121 | { |
5ea0549d JE |
122 | if (target_intel_syntax) |
123 | dual_mode = DUAL_ON; | |
124 | else | |
125 | as_bad (_("Directive .dual available only with -mintel-syntax option")); | |
252b5132 RH |
126 | } |
127 | ||
305d537e | 128 | /* Handle ".enddual" directive. */ |
252b5132 | 129 | static void |
7734b6e9 | 130 | s_enddual (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 131 | { |
5ea0549d JE |
132 | if (target_intel_syntax) |
133 | dual_mode = DUAL_OFF; | |
134 | else | |
135 | as_bad (_("Directive .enddual available only with -mintel-syntax option")); | |
252b5132 RH |
136 | } |
137 | ||
305d537e JE |
138 | /* Temporary register used when expanding assembler pseudo operations. */ |
139 | static int atmp = 31; | |
252b5132 RH |
140 | |
141 | static void | |
7734b6e9 | 142 | s_atmp (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 143 | { |
5ea0549d JE |
144 | int temp; |
145 | ||
146 | if (! target_intel_syntax) | |
147 | { | |
148 | as_bad (_("Directive .atmp available only with -mintel-syntax option")); | |
149 | demand_empty_rest_of_line (); | |
150 | return; | |
151 | } | |
152 | ||
252b5132 RH |
153 | if (strncmp (input_line_pointer, "sp", 2) == 0) |
154 | { | |
155 | input_line_pointer += 2; | |
156 | atmp = 2; | |
157 | } | |
158 | else if (strncmp (input_line_pointer, "fp", 2) == 0) | |
159 | { | |
160 | input_line_pointer += 2; | |
161 | atmp = 3; | |
162 | } | |
163 | else if (strncmp (input_line_pointer, "r", 1) == 0) | |
164 | { | |
165 | input_line_pointer += 1; | |
166 | temp = get_absolute_expression (); | |
167 | if (temp >= 0 && temp <= 31) | |
168 | atmp = temp; | |
169 | else | |
170 | as_bad (_("Unknown temporary pseudo register")); | |
171 | } | |
172 | else | |
173 | { | |
174 | as_bad (_("Unknown temporary pseudo register")); | |
175 | } | |
176 | demand_empty_rest_of_line (); | |
177 | } | |
178 | ||
179 | /* This function is called once, at assembler startup time. It should | |
305d537e JE |
180 | set up all the tables and data structures that the MD part of the |
181 | assembler will need. */ | |
252b5132 | 182 | void |
7734b6e9 | 183 | md_begin (void) |
252b5132 | 184 | { |
305d537e | 185 | const char *retval = NULL; |
252b5132 | 186 | int lose = 0; |
305d537e | 187 | unsigned int i = 0; |
252b5132 RH |
188 | |
189 | op_hash = hash_new (); | |
190 | ||
305d537e | 191 | while (i860_opcodes[i].name != NULL) |
252b5132 RH |
192 | { |
193 | const char *name = i860_opcodes[i].name; | |
305d537e | 194 | retval = hash_insert (op_hash, name, (PTR)&i860_opcodes[i]); |
252b5132 RH |
195 | if (retval != NULL) |
196 | { | |
197 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
198 | i860_opcodes[i].name, retval); | |
199 | lose = 1; | |
200 | } | |
201 | do | |
202 | { | |
203 | if (i860_opcodes[i].match & i860_opcodes[i].lose) | |
204 | { | |
305d537e JE |
205 | fprintf (stderr, |
206 | _("internal error: losing opcode: `%s' \"%s\"\n"), | |
252b5132 RH |
207 | i860_opcodes[i].name, i860_opcodes[i].args); |
208 | lose = 1; | |
209 | } | |
210 | ++i; | |
211 | } | |
305d537e JE |
212 | while (i860_opcodes[i].name != NULL |
213 | && strcmp (i860_opcodes[i].name, name) == 0); | |
252b5132 RH |
214 | } |
215 | ||
216 | if (lose) | |
305d537e | 217 | as_fatal (_("Defective assembler. No assembly attempted.")); |
87505968 JE |
218 | |
219 | /* Set the register prefix for either Intel or AT&T/SVR4 syntax. */ | |
220 | reg_prefix = target_intel_syntax ? 0 : '%'; | |
252b5132 RH |
221 | } |
222 | ||
305d537e JE |
223 | /* This is the core of the machine-dependent assembler. STR points to a |
224 | machine dependent instruction. This function emits the frags/bytes | |
225 | it assembles to. */ | |
252b5132 | 226 | void |
7734b6e9 | 227 | md_assemble (char *str) |
252b5132 | 228 | { |
305d537e JE |
229 | char *destp; |
230 | int num_opcodes = 1; | |
252b5132 RH |
231 | int i; |
232 | struct i860_it pseudo[3]; | |
233 | ||
234 | assert (str); | |
673a54e3 | 235 | fc = 0; |
252b5132 | 236 | |
305d537e JE |
237 | /* Assemble the instruction. */ |
238 | i860_process_insn (str); | |
239 | ||
240 | /* Check for expandable flag to produce pseudo-instructions. This | |
241 | is an undesirable feature that should be avoided. */ | |
14218d5f | 242 | if (the_insn.expand != 0 && the_insn.expand != XP_ONLY |
673a54e3 | 243 | && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT |
305d537e | 244 | | OP_SEL_GOTOFF | OP_SEL_PLT))) |
252b5132 RH |
245 | { |
246 | for (i = 0; i < 3; i++) | |
247 | pseudo[i] = the_insn; | |
248 | ||
673a54e3 | 249 | fc = 1; |
252b5132 RH |
250 | switch (the_insn.expand) |
251 | { | |
252 | ||
253 | case E_DELAY: | |
305d537e | 254 | num_opcodes = 1; |
252b5132 RH |
255 | break; |
256 | ||
257 | case E_MOV: | |
673a54e3 JE |
258 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
259 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
260 | && (the_insn.fi[0].exp.X_add_number < (1 << 15) | |
261 | && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) | |
252b5132 | 262 | break; |
305d537e JE |
263 | |
264 | /* Emit "or l%const,r0,ireg_dest". */ | |
252b5132 | 265 | pseudo[0].opcode = (the_insn.opcode & 0x001f0000) | 0xe4000000; |
673a54e3 | 266 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); |
305d537e JE |
267 | |
268 | /* Emit "orh h%const,ireg_dest,ireg_dest". */ | |
269 | pseudo[1].opcode = (the_insn.opcode & 0x03ffffff) | 0xec000000 | |
270 | | ((the_insn.opcode & 0x001f0000) << 5); | |
673a54e3 | 271 | pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); |
305d537e JE |
272 | |
273 | num_opcodes = 2; | |
252b5132 RH |
274 | break; |
275 | ||
276 | case E_ADDR: | |
673a54e3 JE |
277 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
278 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
279 | && (the_insn.fi[0].exp.X_add_number < (1 << 15) | |
280 | && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) | |
252b5132 | 281 | break; |
305d537e JE |
282 | |
283 | /* Emit "orh ha%addr_expr,r0,r31". */ | |
252b5132 | 284 | pseudo[0].opcode = 0xec000000 | (atmp << 16); |
673a54e3 | 285 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_HA); |
305d537e JE |
286 | |
287 | /* Emit "l%addr_expr(r31),ireg_dest". We pick up the fixup | |
288 | information from the original instruction. */ | |
289 | pseudo[1].opcode = (the_insn.opcode & ~0x03e00000) | (atmp << 21); | |
673a54e3 | 290 | pseudo[1].fi[0].fup = the_insn.fi[0].fup | OP_SEL_L; |
305d537e JE |
291 | |
292 | num_opcodes = 2; | |
252b5132 RH |
293 | break; |
294 | ||
305d537e | 295 | case E_U32: |
673a54e3 JE |
296 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
297 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
298 | && (the_insn.fi[0].exp.X_add_number < (1 << 16) | |
299 | && the_insn.fi[0].exp.X_add_number >= 0)) | |
252b5132 | 300 | break; |
305d537e JE |
301 | |
302 | /* Emit "$(opcode)h h%const,ireg_src2,r31". */ | |
303 | pseudo[0].opcode = (the_insn.opcode & 0xf3e0ffff) | 0x0c000000 | |
304 | | (atmp << 16); | |
673a54e3 | 305 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); |
305d537e JE |
306 | |
307 | /* Emit "$(opcode) l%const,r31,ireg_dest". */ | |
308 | pseudo[1].opcode = (the_insn.opcode & 0xf01f0000) | 0x04000000 | |
309 | | (atmp << 21); | |
673a54e3 | 310 | pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); |
305d537e JE |
311 | |
312 | num_opcodes = 2; | |
252b5132 RH |
313 | break; |
314 | ||
305d537e | 315 | case E_AND: |
673a54e3 JE |
316 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
317 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
318 | && (the_insn.fi[0].exp.X_add_number < (1 << 16) | |
319 | && the_insn.fi[0].exp.X_add_number >= 0)) | |
252b5132 | 320 | break; |
305d537e JE |
321 | |
322 | /* Emit "andnot h%const,ireg_src2,r31". */ | |
323 | pseudo[0].opcode = (the_insn.opcode & 0x03e0ffff) | 0xd4000000 | |
324 | | (atmp << 16); | |
673a54e3 JE |
325 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); |
326 | pseudo[0].fi[0].exp.X_add_number = | |
327 | -1 - the_insn.fi[0].exp.X_add_number; | |
305d537e JE |
328 | |
329 | /* Emit "andnot l%const,r31,ireg_dest". */ | |
330 | pseudo[1].opcode = (the_insn.opcode & 0x001f0000) | 0xd4000000 | |
331 | | (atmp << 21); | |
673a54e3 JE |
332 | pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); |
333 | pseudo[1].fi[0].exp.X_add_number = | |
334 | -1 - the_insn.fi[0].exp.X_add_number; | |
305d537e JE |
335 | |
336 | num_opcodes = 2; | |
252b5132 RH |
337 | break; |
338 | ||
339 | case E_S32: | |
673a54e3 JE |
340 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
341 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
342 | && (the_insn.fi[0].exp.X_add_number < (1 << 15) | |
343 | && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) | |
252b5132 | 344 | break; |
305d537e JE |
345 | |
346 | /* Emit "orh h%const,r0,r31". */ | |
252b5132 | 347 | pseudo[0].opcode = 0xec000000 | (atmp << 16); |
673a54e3 | 348 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); |
305d537e JE |
349 | |
350 | /* Emit "or l%const,r31,r31". */ | |
252b5132 | 351 | pseudo[1].opcode = 0xe4000000 | (atmp << 21) | (atmp << 16); |
673a54e3 | 352 | pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); |
305d537e JE |
353 | |
354 | /* Emit "r31,ireg_src2,ireg_dest". */ | |
252b5132 | 355 | pseudo[2].opcode = (the_insn.opcode & ~0x0400ffff) | (atmp << 11); |
673a54e3 | 356 | pseudo[2].fi[0].fup = OP_IMM_S16; |
305d537e JE |
357 | |
358 | num_opcodes = 3; | |
252b5132 RH |
359 | break; |
360 | ||
361 | default: | |
362 | as_fatal (_("failed sanity check.")); | |
363 | } | |
364 | ||
365 | the_insn = pseudo[0]; | |
305d537e JE |
366 | |
367 | /* Warn if an opcode is expanded after a delayed branch. */ | |
368 | if (num_opcodes > 1 && last_expand == 1) | |
252b5132 | 369 | as_warn (_("Expanded opcode after delayed branch: `%s'"), str); |
305d537e JE |
370 | |
371 | /* Warn if an opcode is expanded in dual mode. */ | |
372 | if (num_opcodes > 1 && dual_mode != DUAL_OFF) | |
252b5132 | 373 | as_warn (_("Expanded opcode in dual mode: `%s'"), str); |
305d537e JE |
374 | |
375 | /* Notify if any expansions happen. */ | |
376 | if (target_warn_expand && num_opcodes > 1) | |
377 | as_warn (_("An instruction was expanded (%s)"), str); | |
252b5132 RH |
378 | } |
379 | ||
380 | i = 0; | |
381 | do | |
305d537e | 382 | { |
673a54e3 JE |
383 | int tmp; |
384 | ||
305d537e JE |
385 | /* Output the opcode. Note that the i860 always reads instructions |
386 | as little-endian data. */ | |
387 | destp = frag_more (4); | |
388 | number_to_chars_littleendian (destp, the_insn.opcode, 4); | |
252b5132 | 389 | |
305d537e | 390 | /* Check for expanded opcode after branch or in dual mode. */ |
673a54e3 JE |
391 | last_expand = the_insn.fi[0].pcrel; |
392 | ||
393 | /* Output the symbol-dependent stuff. Only btne and bte will ever | |
394 | loop more than once here, since only they (possibly) have more | |
395 | than one fixup. */ | |
396 | for (tmp = 0; tmp < fc; tmp++) | |
397 | { | |
398 | if (the_insn.fi[tmp].fup != OP_NONE) | |
399 | { | |
400 | fixS *fix; | |
401 | fix = fix_new_exp (frag_now, | |
402 | destp - frag_now->fr_literal, | |
403 | 4, | |
404 | &the_insn.fi[tmp].exp, | |
405 | the_insn.fi[tmp].pcrel, | |
406 | the_insn.fi[tmp].reloc); | |
407 | ||
408 | /* Despite the odd name, this is a scratch field. We use | |
409 | it to encode operand type information. */ | |
410 | fix->fx_addnumber = the_insn.fi[tmp].fup; | |
411 | } | |
412 | } | |
252b5132 RH |
413 | the_insn = pseudo[++i]; |
414 | } | |
305d537e | 415 | while (--num_opcodes > 0); |
252b5132 RH |
416 | |
417 | } | |
418 | ||
305d537e | 419 | /* Assemble the instruction pointed to by STR. */ |
252b5132 | 420 | static void |
7734b6e9 | 421 | i860_process_insn (char *str) |
252b5132 RH |
422 | { |
423 | char *s; | |
424 | const char *args; | |
425 | char c; | |
252b5132 | 426 | struct i860_opcode *insn; |
305d537e | 427 | char *args_start; |
252b5132 RH |
428 | unsigned long opcode; |
429 | unsigned int mask; | |
430 | int match = 0; | |
431 | int comma = 0; | |
432 | ||
305d537e JE |
433 | #if 1 /* For compiler warnings. */ |
434 | args = 0; | |
435 | insn = 0; | |
436 | args_start = 0; | |
437 | opcode = 0; | |
438 | #endif | |
252b5132 | 439 | |
3882b010 | 440 | for (s = str; ISLOWER (*s) || *s == '.' || *s == '3' |
305d537e | 441 | || *s == '2' || *s == '1'; ++s) |
252b5132 | 442 | ; |
305d537e | 443 | |
252b5132 RH |
444 | switch (*s) |
445 | { | |
252b5132 RH |
446 | case '\0': |
447 | break; | |
448 | ||
449 | case ',': | |
450 | comma = 1; | |
451 | ||
452 | /*FALLTHROUGH*/ | |
453 | ||
454 | case ' ': | |
455 | *s++ = '\0'; | |
456 | break; | |
457 | ||
458 | default: | |
459 | as_fatal (_("Unknown opcode: `%s'"), str); | |
460 | } | |
461 | ||
305d537e | 462 | /* Check for dual mode ("d.") opcode prefix. */ |
252b5132 | 463 | if (strncmp (str, "d.", 2) == 0) |
305d537e | 464 | { |
252b5132 RH |
465 | if (dual_mode == DUAL_ON) |
466 | dual_mode = DUAL_ONDDOT; | |
467 | else | |
468 | dual_mode = DUAL_DDOT; | |
469 | str += 2; | |
470 | } | |
471 | ||
472 | if ((insn = (struct i860_opcode *) hash_find (op_hash, str)) == NULL) | |
473 | { | |
474 | if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT) | |
475 | str -= 2; | |
476 | as_bad (_("Unknown opcode: `%s'"), str); | |
477 | return; | |
478 | } | |
305d537e | 479 | |
252b5132 | 480 | if (comma) |
305d537e JE |
481 | *--s = ','; |
482 | ||
483 | args_start = s; | |
252b5132 RH |
484 | for (;;) |
485 | { | |
673a54e3 | 486 | int t; |
252b5132 RH |
487 | opcode = insn->match; |
488 | memset (&the_insn, '\0', sizeof (the_insn)); | |
b645cb17 | 489 | fc = 0; |
673a54e3 JE |
490 | for (t = 0; t < MAX_FIXUPS; t++) |
491 | { | |
492 | the_insn.fi[t].reloc = BFD_RELOC_NONE; | |
493 | the_insn.fi[t].pcrel = 0; | |
494 | the_insn.fi[t].fup = OP_NONE; | |
495 | } | |
252b5132 | 496 | |
305d537e JE |
497 | /* Build the opcode, checking as we go that the operands match. */ |
498 | for (args = insn->args; ; ++args) | |
252b5132 | 499 | { |
673a54e3 JE |
500 | if (fc > MAX_FIXUPS) |
501 | abort (); | |
502 | ||
252b5132 RH |
503 | switch (*args) |
504 | { | |
505 | ||
305d537e JE |
506 | /* End of args. */ |
507 | case '\0': | |
252b5132 | 508 | if (*s == '\0') |
305d537e | 509 | match = 1; |
252b5132 RH |
510 | break; |
511 | ||
305d537e | 512 | /* These must match exactly. */ |
252b5132 | 513 | case '+': |
305d537e | 514 | case '(': |
252b5132 RH |
515 | case ')': |
516 | case ',': | |
517 | case ' ': | |
518 | if (*s++ == *args) | |
519 | continue; | |
520 | break; | |
521 | ||
305d537e JE |
522 | /* Must be at least one digit. */ |
523 | case '#': | |
3882b010 | 524 | if (ISDIGIT (*s++)) |
252b5132 | 525 | { |
3882b010 | 526 | while (ISDIGIT (*s)) |
305d537e | 527 | ++s; |
252b5132 RH |
528 | continue; |
529 | } | |
530 | break; | |
531 | ||
305d537e JE |
532 | /* Next operand must be a register. */ |
533 | case '1': | |
252b5132 RH |
534 | case '2': |
535 | case 'd': | |
305d537e JE |
536 | /* Check for register prefix if necessary. */ |
537 | if (reg_prefix && *s != reg_prefix) | |
538 | goto error; | |
87505968 | 539 | else if (reg_prefix) |
305d537e JE |
540 | s++; |
541 | ||
252b5132 RH |
542 | switch (*s) |
543 | { | |
305d537e JE |
544 | /* Frame pointer. */ |
545 | case 'f': | |
252b5132 RH |
546 | s++; |
547 | if (*s++ == 'p') | |
548 | { | |
549 | mask = 0x3; | |
550 | break; | |
551 | } | |
552 | goto error; | |
553 | ||
305d537e JE |
554 | /* Stack pointer. */ |
555 | case 's': | |
252b5132 RH |
556 | s++; |
557 | if (*s++ == 'p') | |
558 | { | |
559 | mask = 0x2; | |
560 | break; | |
561 | } | |
562 | goto error; | |
563 | ||
305d537e JE |
564 | /* Any register r0..r31. */ |
565 | case 'r': | |
252b5132 | 566 | s++; |
3882b010 | 567 | if (!ISDIGIT (c = *s++)) |
252b5132 RH |
568 | { |
569 | goto error; | |
570 | } | |
3882b010 | 571 | if (ISDIGIT (*s)) |
252b5132 RH |
572 | { |
573 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
305d537e | 574 | goto error; |
252b5132 RH |
575 | } |
576 | else | |
305d537e | 577 | c -= '0'; |
252b5132 RH |
578 | mask = c; |
579 | break; | |
580 | ||
305d537e JE |
581 | /* Not this opcode. */ |
582 | default: | |
252b5132 RH |
583 | goto error; |
584 | } | |
305d537e JE |
585 | |
586 | /* Obtained the register, now place it in the opcode. */ | |
252b5132 RH |
587 | switch (*args) |
588 | { | |
252b5132 RH |
589 | case '1': |
590 | opcode |= mask << 11; | |
591 | continue; | |
592 | ||
593 | case '2': | |
594 | opcode |= mask << 21; | |
595 | continue; | |
596 | ||
597 | case 'd': | |
598 | opcode |= mask << 16; | |
599 | continue; | |
600 | ||
601 | } | |
602 | break; | |
603 | ||
305d537e JE |
604 | /* Next operand is a floating point register. */ |
605 | case 'e': | |
252b5132 RH |
606 | case 'f': |
607 | case 'g': | |
305d537e JE |
608 | /* Check for register prefix if necessary. */ |
609 | if (reg_prefix && *s != reg_prefix) | |
610 | goto error; | |
87505968 | 611 | else if (reg_prefix) |
305d537e JE |
612 | s++; |
613 | ||
3882b010 | 614 | if (*s++ == 'f' && ISDIGIT (*s)) |
252b5132 RH |
615 | { |
616 | mask = *s++; | |
3882b010 | 617 | if (ISDIGIT (*s)) |
252b5132 RH |
618 | { |
619 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
620 | if (mask >= 32) | |
621 | { | |
622 | break; | |
623 | } | |
624 | } | |
625 | else | |
305d537e JE |
626 | mask -= '0'; |
627 | ||
252b5132 RH |
628 | switch (*args) |
629 | { | |
630 | ||
631 | case 'e': | |
632 | opcode |= mask << 11; | |
633 | continue; | |
634 | ||
635 | case 'f': | |
636 | opcode |= mask << 21; | |
637 | continue; | |
638 | ||
639 | case 'g': | |
640 | opcode |= mask << 16; | |
305d537e JE |
641 | if ((opcode & (1 << 10)) && mask != 0 |
642 | && (mask == ((opcode >> 11) & 0x1f))) | |
643 | as_warn (_("Pipelined instruction: fsrc1 = fdest")); | |
252b5132 RH |
644 | continue; |
645 | } | |
646 | } | |
647 | break; | |
648 | ||
305d537e JE |
649 | /* Next operand must be a control register. */ |
650 | case 'c': | |
651 | /* Check for register prefix if necessary. */ | |
652 | if (reg_prefix && *s != reg_prefix) | |
653 | goto error; | |
87505968 | 654 | else if (reg_prefix) |
305d537e JE |
655 | s++; |
656 | ||
252b5132 RH |
657 | if (strncmp (s, "fir", 3) == 0) |
658 | { | |
659 | opcode |= 0x0 << 21; | |
660 | s += 3; | |
661 | continue; | |
662 | } | |
663 | if (strncmp (s, "psr", 3) == 0) | |
664 | { | |
665 | opcode |= 0x1 << 21; | |
666 | s += 3; | |
667 | continue; | |
668 | } | |
669 | if (strncmp (s, "dirbase", 7) == 0) | |
670 | { | |
671 | opcode |= 0x2 << 21; | |
672 | s += 7; | |
673 | continue; | |
674 | } | |
675 | if (strncmp (s, "db", 2) == 0) | |
676 | { | |
677 | opcode |= 0x3 << 21; | |
678 | s += 2; | |
679 | continue; | |
680 | } | |
681 | if (strncmp (s, "fsr", 3) == 0) | |
682 | { | |
683 | opcode |= 0x4 << 21; | |
684 | s += 3; | |
685 | continue; | |
686 | } | |
687 | if (strncmp (s, "epsr", 4) == 0) | |
688 | { | |
689 | opcode |= 0x5 << 21; | |
690 | s += 4; | |
691 | continue; | |
692 | } | |
14218d5f JE |
693 | /* The remaining control registers are XP only. */ |
694 | if (target_xp && strncmp (s, "bear", 4) == 0) | |
695 | { | |
696 | opcode |= 0x6 << 21; | |
697 | s += 4; | |
698 | continue; | |
699 | } | |
700 | if (target_xp && strncmp (s, "ccr", 3) == 0) | |
701 | { | |
702 | opcode |= 0x7 << 21; | |
703 | s += 3; | |
704 | continue; | |
705 | } | |
706 | if (target_xp && strncmp (s, "p0", 2) == 0) | |
707 | { | |
708 | opcode |= 0x8 << 21; | |
709 | s += 2; | |
710 | continue; | |
711 | } | |
712 | if (target_xp && strncmp (s, "p1", 2) == 0) | |
713 | { | |
714 | opcode |= 0x9 << 21; | |
715 | s += 2; | |
716 | continue; | |
717 | } | |
718 | if (target_xp && strncmp (s, "p2", 2) == 0) | |
719 | { | |
720 | opcode |= 0xa << 21; | |
721 | s += 2; | |
722 | continue; | |
723 | } | |
724 | if (target_xp && strncmp (s, "p3", 2) == 0) | |
725 | { | |
726 | opcode |= 0xb << 21; | |
727 | s += 2; | |
728 | continue; | |
729 | } | |
252b5132 RH |
730 | break; |
731 | ||
305d537e JE |
732 | /* 5-bit immediate in src1. */ |
733 | case '5': | |
734 | if (! i860_get_expression (s)) | |
252b5132 RH |
735 | { |
736 | s = expr_end; | |
673a54e3 JE |
737 | the_insn.fi[fc].fup |= OP_IMM_U5; |
738 | fc++; | |
252b5132 RH |
739 | continue; |
740 | } | |
741 | break; | |
742 | ||
305d537e JE |
743 | /* 26-bit immediate, relative branch (lbroff). */ |
744 | case 'l': | |
673a54e3 JE |
745 | the_insn.fi[fc].pcrel = 1; |
746 | the_insn.fi[fc].fup |= OP_IMM_BR26; | |
252b5132 RH |
747 | goto immediate; |
748 | ||
305d537e JE |
749 | /* 16-bit split immediate, relative branch (sbroff). */ |
750 | case 'r': | |
673a54e3 JE |
751 | the_insn.fi[fc].pcrel = 1; |
752 | the_insn.fi[fc].fup |= OP_IMM_BR16; | |
252b5132 RH |
753 | goto immediate; |
754 | ||
305d537e JE |
755 | /* 16-bit split immediate. */ |
756 | case 's': | |
673a54e3 | 757 | the_insn.fi[fc].fup |= OP_IMM_SPLIT16; |
305d537e JE |
758 | goto immediate; |
759 | ||
760 | /* 16-bit split immediate, byte aligned (st.b). */ | |
761 | case 'S': | |
673a54e3 | 762 | the_insn.fi[fc].fup |= OP_IMM_SPLIT16; |
305d537e JE |
763 | goto immediate; |
764 | ||
765 | /* 16-bit split immediate, half-word aligned (st.s). */ | |
766 | case 'T': | |
673a54e3 | 767 | the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN2); |
305d537e JE |
768 | goto immediate; |
769 | ||
770 | /* 16-bit split immediate, word aligned (st.l). */ | |
771 | case 'U': | |
673a54e3 | 772 | the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN4); |
305d537e JE |
773 | goto immediate; |
774 | ||
775 | /* 16-bit immediate. */ | |
776 | case 'i': | |
673a54e3 | 777 | the_insn.fi[fc].fup |= OP_IMM_S16; |
305d537e JE |
778 | goto immediate; |
779 | ||
780 | /* 16-bit immediate, byte aligned (ld.b). */ | |
781 | case 'I': | |
673a54e3 | 782 | the_insn.fi[fc].fup |= OP_IMM_S16; |
305d537e JE |
783 | goto immediate; |
784 | ||
785 | /* 16-bit immediate, half-word aligned (ld.s). */ | |
786 | case 'J': | |
673a54e3 | 787 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN2); |
252b5132 RH |
788 | goto immediate; |
789 | ||
305d537e JE |
790 | /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l). */ |
791 | case 'K': | |
792 | if (insn->name[0] == 'l') | |
673a54e3 | 793 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN4); |
252b5132 | 794 | else |
673a54e3 | 795 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE2 | OP_ALIGN4); |
305d537e JE |
796 | goto immediate; |
797 | ||
798 | /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d). */ | |
799 | case 'L': | |
673a54e3 | 800 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN8); |
252b5132 RH |
801 | goto immediate; |
802 | ||
305d537e JE |
803 | /* 16-bit immediate, quad-word aligned (fld.q, fst.q). */ |
804 | case 'M': | |
673a54e3 | 805 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN16); |
252b5132 RH |
806 | |
807 | /*FALLTHROUGH*/ | |
808 | ||
305d537e JE |
809 | /* Handle the immediate for either the Intel syntax or |
810 | SVR4 syntax. The Intel syntax is "ha%immediate" | |
811 | whereas SVR4 syntax is "[immediate]@ha". */ | |
252b5132 | 812 | immediate: |
87505968 | 813 | if (target_intel_syntax == 0) |
305d537e | 814 | { |
87505968 JE |
815 | /* AT&T/SVR4 syntax. */ |
816 | if (*s == ' ') | |
817 | s++; | |
818 | ||
819 | /* Note that if i860_get_expression() fails, we will still | |
820 | have created U entries in the symbol table for the | |
821 | 'symbols' in the input string. Try not to create U | |
822 | symbols for registers, etc. */ | |
823 | if (! i860_get_expression (s)) | |
824 | s = expr_end; | |
825 | else | |
826 | goto error; | |
827 | ||
828 | if (strncmp (s, "@ha", 3) == 0) | |
829 | { | |
830 | the_insn.fi[fc].fup |= OP_SEL_HA; | |
831 | s += 3; | |
832 | } | |
833 | else if (strncmp (s, "@h", 2) == 0) | |
834 | { | |
835 | the_insn.fi[fc].fup |= OP_SEL_H; | |
836 | s += 2; | |
837 | } | |
838 | else if (strncmp (s, "@l", 2) == 0) | |
839 | { | |
840 | the_insn.fi[fc].fup |= OP_SEL_L; | |
841 | s += 2; | |
842 | } | |
843 | else if (strncmp (s, "@gotoff", 7) == 0 | |
844 | || strncmp (s, "@GOTOFF", 7) == 0) | |
845 | { | |
846 | as_bad (_("Assembler does not yet support PIC")); | |
847 | the_insn.fi[fc].fup |= OP_SEL_GOTOFF; | |
848 | s += 7; | |
849 | } | |
850 | else if (strncmp (s, "@got", 4) == 0 | |
851 | || strncmp (s, "@GOT", 4) == 0) | |
852 | { | |
853 | as_bad (_("Assembler does not yet support PIC")); | |
854 | the_insn.fi[fc].fup |= OP_SEL_GOT; | |
855 | s += 4; | |
856 | } | |
857 | else if (strncmp (s, "@plt", 4) == 0 | |
858 | || strncmp (s, "@PLT", 4) == 0) | |
859 | { | |
860 | as_bad (_("Assembler does not yet support PIC")); | |
861 | the_insn.fi[fc].fup |= OP_SEL_PLT; | |
862 | s += 4; | |
863 | } | |
305d537e | 864 | |
87505968 JE |
865 | the_insn.expand = insn->expand; |
866 | fc++; | |
673a54e3 | 867 | |
87505968 | 868 | continue; |
252b5132 | 869 | } |
87505968 | 870 | else |
252b5132 | 871 | { |
87505968 JE |
872 | /* Intel syntax. */ |
873 | if (*s == ' ') | |
874 | s++; | |
875 | if (strncmp (s, "ha%", 3) == 0) | |
876 | { | |
877 | the_insn.fi[fc].fup |= OP_SEL_HA; | |
878 | s += 3; | |
879 | } | |
880 | else if (strncmp (s, "h%", 2) == 0) | |
881 | { | |
882 | the_insn.fi[fc].fup |= OP_SEL_H; | |
883 | s += 2; | |
884 | } | |
885 | else if (strncmp (s, "l%", 2) == 0) | |
886 | { | |
887 | the_insn.fi[fc].fup |= OP_SEL_L; | |
888 | s += 2; | |
889 | } | |
890 | the_insn.expand = insn->expand; | |
891 | ||
892 | /* Note that if i860_get_expression() fails, we will still | |
893 | have created U entries in the symbol table for the | |
894 | 'symbols' in the input string. Try not to create U | |
895 | symbols for registers, etc. */ | |
896 | if (! i860_get_expression (s)) | |
897 | s = expr_end; | |
898 | else | |
899 | goto error; | |
900 | ||
901 | fc++; | |
902 | continue; | |
252b5132 | 903 | } |
252b5132 RH |
904 | break; |
905 | ||
906 | default: | |
907 | as_fatal (_("failed sanity check.")); | |
908 | } | |
909 | break; | |
910 | } | |
911 | error: | |
912 | if (match == 0) | |
913 | { | |
914 | /* Args don't match. */ | |
305d537e JE |
915 | if (insn[1].name != NULL |
916 | && ! strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
917 | { |
918 | ++insn; | |
305d537e | 919 | s = args_start; |
252b5132 RH |
920 | continue; |
921 | } | |
922 | else | |
923 | { | |
305d537e | 924 | as_bad (_("Illegal operands for %s"), insn->name); |
252b5132 RH |
925 | return; |
926 | } | |
927 | } | |
928 | break; | |
929 | } | |
930 | ||
07c7854e JE |
931 | /* Set the dual bit on this instruction if necessary. */ |
932 | if (dual_mode != DUAL_OFF) | |
933 | { | |
934 | if ((opcode & 0xfc000000) == 0x48000000 || opcode == 0xb0000000) | |
935 | { | |
0acc96e1 JE |
936 | /* The instruction is a flop or a fnop, so set its dual bit |
937 | (but check that it is 8-byte aligned). */ | |
938 | if (((frag_now->fr_address + frag_now_fix_octets ()) & 7) == 0) | |
939 | opcode |= (1 << 9); | |
940 | else | |
941 | as_bad (_("'d.%s' must be 8-byte aligned"), insn->name); | |
942 | ||
07c7854e JE |
943 | if (dual_mode == DUAL_DDOT) |
944 | dual_mode = DUAL_OFF; | |
945 | else if (dual_mode == DUAL_ONDDOT) | |
946 | dual_mode = DUAL_ON; | |
947 | } | |
948 | else if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT) | |
949 | as_bad (_("Prefix 'd.' invalid for instruction `%s'"), insn->name); | |
950 | } | |
951 | ||
252b5132 | 952 | the_insn.opcode = opcode; |
14218d5f JE |
953 | |
954 | /* Only recognize XP instructions when the user has requested it. */ | |
955 | if (insn->expand == XP_ONLY && ! target_xp) | |
956 | as_bad (_("Unknown opcode: `%s'"), insn->name); | |
252b5132 RH |
957 | } |
958 | ||
959 | static int | |
7734b6e9 | 960 | i860_get_expression (char *str) |
252b5132 RH |
961 | { |
962 | char *save_in; | |
963 | segT seg; | |
964 | ||
965 | save_in = input_line_pointer; | |
966 | input_line_pointer = str; | |
673a54e3 | 967 | seg = expression (&the_insn.fi[fc].exp); |
252b5132 RH |
968 | if (seg != absolute_section |
969 | && seg != undefined_section | |
970 | && ! SEG_NORMAL (seg)) | |
971 | { | |
972 | the_insn.error = _("bad segment"); | |
973 | expr_end = input_line_pointer; | |
974 | input_line_pointer = save_in; | |
975 | return 1; | |
976 | } | |
977 | expr_end = input_line_pointer; | |
978 | input_line_pointer = save_in; | |
979 | return 0; | |
980 | } | |
981 | ||
305d537e JE |
982 | /* Turn a string in input_line_pointer into a floating point constant of |
983 | type TYPE, and store the appropriate bytes in *LITP. The number of | |
984 | LITTLENUMS emitted is stored in *SIZEP. An error message is returned, | |
985 | or NULL on OK. */ | |
252b5132 | 986 | |
305d537e | 987 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
988 | #define MAX_LITTLENUMS 6 |
989 | ||
990 | char * | |
7734b6e9 | 991 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
992 | { |
993 | int prec; | |
994 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
995 | LITTLENUM_TYPE *wordP; | |
996 | char *t; | |
252b5132 RH |
997 | |
998 | switch (type) | |
999 | { | |
252b5132 RH |
1000 | case 'f': |
1001 | case 'F': | |
1002 | case 's': | |
1003 | case 'S': | |
1004 | prec = 2; | |
1005 | break; | |
1006 | ||
1007 | case 'd': | |
1008 | case 'D': | |
1009 | case 'r': | |
1010 | case 'R': | |
1011 | prec = 4; | |
1012 | break; | |
1013 | ||
1014 | case 'x': | |
1015 | case 'X': | |
1016 | prec = 6; | |
1017 | break; | |
1018 | ||
1019 | case 'p': | |
1020 | case 'P': | |
1021 | prec = 6; | |
1022 | break; | |
1023 | ||
1024 | default: | |
1025 | *sizeP = 0; | |
1026 | return _("Bad call to MD_ATOF()"); | |
1027 | } | |
1028 | t = atof_ieee (input_line_pointer, type, words); | |
1029 | if (t) | |
1030 | input_line_pointer = t; | |
1031 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
1032 | for (wordP = words; prec--;) | |
1033 | { | |
1034 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); | |
1035 | litP += sizeof (LITTLENUM_TYPE); | |
1036 | } | |
1037 | return 0; | |
1038 | } | |
1039 | ||
305d537e | 1040 | /* Write out in current endian mode. */ |
252b5132 | 1041 | void |
7734b6e9 | 1042 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 | 1043 | { |
305d537e JE |
1044 | if (target_big_endian) |
1045 | number_to_chars_bigendian (buf, val, n); | |
1046 | else | |
1047 | number_to_chars_littleendian (buf, val, n); | |
252b5132 RH |
1048 | } |
1049 | ||
305d537e | 1050 | /* This should never be called for i860. */ |
252b5132 | 1051 | int |
7734b6e9 JE |
1052 | md_estimate_size_before_relax (register fragS *fragP ATTRIBUTE_UNUSED, |
1053 | segT segtype ATTRIBUTE_UNUSED) | |
252b5132 RH |
1054 | { |
1055 | as_fatal (_("i860_estimate_size_before_relax\n")); | |
1056 | } | |
1057 | ||
305d537e | 1058 | #ifdef DEBUG_I860 |
252b5132 | 1059 | static void |
7734b6e9 | 1060 | print_insn (struct i860_it *insn) |
252b5132 RH |
1061 | { |
1062 | if (insn->error) | |
305d537e JE |
1063 | fprintf (stderr, "ERROR: %s\n", insn->error); |
1064 | ||
1065 | fprintf (stderr, "opcode = 0x%08lx\t", insn->opcode); | |
1066 | fprintf (stderr, "expand = 0x%x\t", insn->expand); | |
1067 | fprintf (stderr, "reloc = %s\t\n", | |
1068 | bfd_get_reloc_code_name (insn->reloc)); | |
252b5132 RH |
1069 | fprintf (stderr, "exp = {\n"); |
1070 | fprintf (stderr, "\t\tX_add_symbol = %s\n", | |
1071 | insn->exp.X_add_symbol ? | |
1072 | (S_GET_NAME (insn->exp.X_add_symbol) ? | |
1073 | S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0"); | |
1074 | fprintf (stderr, "\t\tX_op_symbol = %s\n", | |
1075 | insn->exp.X_op_symbol ? | |
1076 | (S_GET_NAME (insn->exp.X_op_symbol) ? | |
1077 | S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0"); | |
305d537e | 1078 | fprintf (stderr, "\t\tX_add_number = %lx\n", |
252b5132 RH |
1079 | insn->exp.X_add_number); |
1080 | fprintf (stderr, "}\n"); | |
1081 | } | |
305d537e JE |
1082 | #endif /* DEBUG_I860 */ |
1083 | ||
252b5132 | 1084 | \f |
305d537e | 1085 | #ifdef OBJ_ELF |
5a38dc70 | 1086 | const char *md_shortopts = "VQ:"; |
305d537e | 1087 | #else |
5a38dc70 | 1088 | const char *md_shortopts = ""; |
305d537e JE |
1089 | #endif |
1090 | ||
305d537e JE |
1091 | #define OPTION_EB (OPTION_MD_BASE + 0) |
1092 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
1093 | #define OPTION_WARN_EXPAND (OPTION_MD_BASE + 2) | |
14218d5f | 1094 | #define OPTION_XP (OPTION_MD_BASE + 3) |
87505968 | 1095 | #define OPTION_INTEL_SYNTAX (OPTION_MD_BASE + 4) |
305d537e | 1096 | |
252b5132 | 1097 | struct option md_longopts[] = { |
305d537e JE |
1098 | { "EB", no_argument, NULL, OPTION_EB }, |
1099 | { "EL", no_argument, NULL, OPTION_EL }, | |
1100 | { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND }, | |
14218d5f | 1101 | { "mxp", no_argument, NULL, OPTION_XP }, |
87505968 | 1102 | { "mintel-syntax",no_argument, NULL, OPTION_INTEL_SYNTAX }, |
305d537e | 1103 | { NULL, no_argument, NULL, 0 } |
252b5132 | 1104 | }; |
305d537e JE |
1105 | size_t md_longopts_size = sizeof (md_longopts); |
1106 | ||
252b5132 | 1107 | int |
7734b6e9 | 1108 | md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) |
252b5132 | 1109 | { |
305d537e JE |
1110 | switch (c) |
1111 | { | |
1112 | case OPTION_EB: | |
1113 | target_big_endian = 1; | |
1114 | break; | |
1115 | ||
1116 | case OPTION_EL: | |
1117 | target_big_endian = 0; | |
1118 | break; | |
1119 | ||
1120 | case OPTION_WARN_EXPAND: | |
1121 | target_warn_expand = 1; | |
1122 | break; | |
1123 | ||
14218d5f JE |
1124 | case OPTION_XP: |
1125 | target_xp = 1; | |
1126 | break; | |
1127 | ||
87505968 JE |
1128 | case OPTION_INTEL_SYNTAX: |
1129 | target_intel_syntax = 1; | |
1130 | break; | |
1131 | ||
305d537e JE |
1132 | #ifdef OBJ_ELF |
1133 | /* SVR4 argument compatibility (-V): print version ID. */ | |
1134 | case 'V': | |
1135 | print_version_id (); | |
1136 | break; | |
1137 | ||
1138 | /* SVR4 argument compatibility (-Qy, -Qn): controls whether | |
1139 | a .comment section should be emitted or not (ignored). */ | |
1140 | case 'Q': | |
1141 | break; | |
1142 | #endif | |
1143 | ||
1144 | default: | |
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | return 1; | |
252b5132 RH |
1149 | } |
1150 | ||
1151 | void | |
7734b6e9 | 1152 | md_show_usage (FILE *stream) |
252b5132 | 1153 | { |
305d537e JE |
1154 | fprintf (stream, _("\ |
1155 | -EL generate code for little endian mode (default)\n\ | |
1156 | -EB generate code for big endian mode\n\ | |
14218d5f | 1157 | -mwarn-expand warn if pseudo operations are expanded\n\ |
87505968 JE |
1158 | -mxp enable i860XP support (disabled by default)\n\ |
1159 | -mintel-syntax enable Intel syntax (default to AT&T/SVR4)\n")); | |
305d537e JE |
1160 | #ifdef OBJ_ELF |
1161 | /* SVR4 compatibility flags. */ | |
1162 | fprintf (stream, _("\ | |
1163 | -V print assembler version number\n\ | |
1164 | -Qy, -Qn ignored\n")); | |
1165 | #endif | |
252b5132 | 1166 | } |
305d537e | 1167 | |
252b5132 | 1168 | \f |
305d537e JE |
1169 | /* We have no need to default values of symbols. */ |
1170 | symbolS * | |
7734b6e9 | 1171 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
305d537e JE |
1172 | { |
1173 | return 0; | |
1174 | } | |
1175 | ||
305d537e | 1176 | /* The i860 denotes auto-increment with '++'. */ |
252b5132 | 1177 | void |
7734b6e9 | 1178 | md_operand (expressionS *exp) |
252b5132 | 1179 | { |
305d537e | 1180 | char *s; |
252b5132 | 1181 | |
f869cfc6 | 1182 | for (s = input_line_pointer; *s; s++) |
252b5132 | 1183 | { |
305d537e | 1184 | if (s[0] == '+' && s[1] == '+') |
252b5132 | 1185 | { |
305d537e JE |
1186 | input_line_pointer += 2; |
1187 | exp->X_op = O_register; | |
1188 | break; | |
252b5132 | 1189 | } |
305d537e JE |
1190 | } |
1191 | } | |
1192 | ||
305d537e JE |
1193 | /* Round up a section size to the appropriate boundary. */ |
1194 | valueT | |
7734b6e9 JE |
1195 | md_section_align (segT segment ATTRIBUTE_UNUSED, |
1196 | valueT size ATTRIBUTE_UNUSED) | |
305d537e JE |
1197 | { |
1198 | /* Byte alignment is fine. */ | |
1199 | return size; | |
1200 | } | |
1201 | ||
305d537e JE |
1202 | /* On the i860, a PC-relative offset is relative to the address of the |
1203 | of the offset plus its size. */ | |
1204 | long | |
7734b6e9 | 1205 | md_pcrel_from (fixS *fixP) |
305d537e JE |
1206 | { |
1207 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
1208 | } | |
252b5132 | 1209 | |
305d537e JE |
1210 | /* Determine the relocation needed for non PC-relative 16-bit immediates. |
1211 | Also adjust the given immediate as necessary. Finally, check that | |
1212 | all constraints (such as alignment) are satisfied. */ | |
1213 | static bfd_reloc_code_real_type | |
7734b6e9 | 1214 | obtain_reloc_for_imm16 (fixS *fix, long *val) |
305d537e JE |
1215 | { |
1216 | valueT fup = fix->fx_addnumber; | |
4a4f25cf | 1217 | bfd_reloc_code_real_type reloc; |
305d537e JE |
1218 | |
1219 | if (fix->fx_pcrel) | |
1220 | abort (); | |
1221 | ||
1222 | /* Check alignment restrictions. */ | |
1223 | if ((fup & OP_ALIGN2) && (*val & 0x1)) | |
1224 | as_bad_where (fix->fx_file, fix->fx_line, | |
1225 | _("This immediate requires 0 MOD 2 alignment")); | |
1226 | else if ((fup & OP_ALIGN4) && (*val & 0x3)) | |
1227 | as_bad_where (fix->fx_file, fix->fx_line, | |
1228 | _("This immediate requires 0 MOD 4 alignment")); | |
1229 | else if ((fup & OP_ALIGN8) && (*val & 0x7)) | |
1230 | as_bad_where (fix->fx_file, fix->fx_line, | |
1231 | _("This immediate requires 0 MOD 8 alignment")); | |
1232 | else if ((fup & OP_ALIGN16) && (*val & 0xf)) | |
1233 | as_bad_where (fix->fx_file, fix->fx_line, | |
1234 | _("This immediate requires 0 MOD 16 alignment")); | |
1235 | ||
1236 | if (fup & OP_SEL_HA) | |
1237 | { | |
1238 | *val = (*val >> 16) + (*val & 0x8000 ? 1 : 0); | |
1239 | reloc = BFD_RELOC_860_HIGHADJ; | |
1240 | } | |
1241 | else if (fup & OP_SEL_H) | |
1242 | { | |
1243 | *val >>= 16; | |
1244 | reloc = BFD_RELOC_860_HIGH; | |
1245 | } | |
1246 | else if (fup & OP_SEL_L) | |
1247 | { | |
1248 | int num_encode; | |
1249 | if (fup & OP_IMM_SPLIT16) | |
252b5132 | 1250 | { |
305d537e | 1251 | if (fup & OP_ENCODE1) |
252b5132 | 1252 | { |
305d537e JE |
1253 | num_encode = 1; |
1254 | reloc = BFD_RELOC_860_SPLIT1; | |
1255 | } | |
1256 | else if (fup & OP_ENCODE2) | |
1257 | { | |
1258 | num_encode = 2; | |
1259 | reloc = BFD_RELOC_860_SPLIT2; | |
252b5132 RH |
1260 | } |
1261 | else | |
1262 | { | |
305d537e JE |
1263 | num_encode = 0; |
1264 | reloc = BFD_RELOC_860_SPLIT0; | |
252b5132 | 1265 | } |
305d537e JE |
1266 | } |
1267 | else | |
1268 | { | |
1269 | if (fup & OP_ENCODE1) | |
252b5132 | 1270 | { |
305d537e JE |
1271 | num_encode = 1; |
1272 | reloc = BFD_RELOC_860_LOW1; | |
252b5132 | 1273 | } |
305d537e | 1274 | else if (fup & OP_ENCODE2) |
252b5132 | 1275 | { |
305d537e JE |
1276 | num_encode = 2; |
1277 | reloc = BFD_RELOC_860_LOW2; | |
1278 | } | |
1279 | else if (fup & OP_ENCODE3) | |
1280 | { | |
1281 | num_encode = 3; | |
1282 | reloc = BFD_RELOC_860_LOW3; | |
252b5132 RH |
1283 | } |
1284 | else | |
1285 | { | |
305d537e JE |
1286 | num_encode = 0; |
1287 | reloc = BFD_RELOC_860_LOW0; | |
252b5132 | 1288 | } |
252b5132 | 1289 | } |
305d537e JE |
1290 | |
1291 | /* Preserve size encode bits. */ | |
1292 | *val &= ~((1 << num_encode) - 1); | |
252b5132 | 1293 | } |
305d537e JE |
1294 | else |
1295 | { | |
1296 | /* No selector. What reloc do we generate (???)? */ | |
1297 | reloc = BFD_RELOC_32; | |
1298 | } | |
1299 | ||
1300 | return reloc; | |
252b5132 RH |
1301 | } |
1302 | ||
305d537e JE |
1303 | /* Attempt to simplify or eliminate a fixup. To indicate that a fixup |
1304 | has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL, | |
1305 | we will have to generate a reloc entry. */ | |
94f592af NC |
1306 | |
1307 | void | |
7734b6e9 | 1308 | md_apply_fix3 (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
305d537e | 1309 | { |
305d537e | 1310 | char *buf; |
a161fe53 | 1311 | long val = *valP; |
305d537e JE |
1312 | unsigned long insn; |
1313 | valueT fup; | |
252b5132 | 1314 | |
305d537e | 1315 | buf = fix->fx_frag->fr_literal + fix->fx_where; |
252b5132 | 1316 | |
305d537e JE |
1317 | /* Recall that earlier we stored the opcode little-endian. */ |
1318 | insn = bfd_getl32 (buf); | |
252b5132 | 1319 | |
305d537e JE |
1320 | /* We stored a fix-up in this oddly-named scratch field. */ |
1321 | fup = fix->fx_addnumber; | |
1322 | ||
1323 | /* Determine the necessary relocations as well as inserting an | |
1324 | immediate into the instruction. */ | |
673a54e3 | 1325 | if (fup & OP_IMM_U5) |
252b5132 | 1326 | { |
305d537e JE |
1327 | if (val & ~0x1f) |
1328 | as_bad_where (fix->fx_file, fix->fx_line, | |
1329 | _("5-bit immediate too large")); | |
1330 | if (fix->fx_addsy) | |
1331 | as_bad_where (fix->fx_file, fix->fx_line, | |
1332 | _("5-bit field must be absolute")); | |
1333 | ||
1334 | insn |= (val & 0x1f) << 11; | |
1335 | bfd_putl32 (insn, buf); | |
1336 | fix->fx_r_type = BFD_RELOC_NONE; | |
1337 | fix->fx_done = 1; | |
252b5132 | 1338 | } |
305d537e | 1339 | else if (fup & OP_IMM_S16) |
252b5132 | 1340 | { |
305d537e | 1341 | fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val); |
252b5132 | 1342 | |
305d537e | 1343 | /* Insert the immediate. */ |
ded0649c JE |
1344 | if (fix->fx_addsy) |
1345 | fix->fx_done = 0; | |
1346 | else | |
1347 | { | |
1348 | insn |= val & 0xffff; | |
1349 | bfd_putl32 (insn, buf); | |
1350 | fix->fx_r_type = BFD_RELOC_NONE; | |
1351 | fix->fx_done = 1; | |
1352 | } | |
305d537e JE |
1353 | } |
1354 | else if (fup & OP_IMM_U16) | |
94f592af NC |
1355 | abort (); |
1356 | ||
305d537e JE |
1357 | else if (fup & OP_IMM_SPLIT16) |
1358 | { | |
1359 | fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val); | |
1360 | ||
1361 | /* Insert the immediate. */ | |
ded0649c JE |
1362 | if (fix->fx_addsy) |
1363 | fix->fx_done = 0; | |
1364 | else | |
1365 | { | |
1366 | insn |= val & 0x7ff; | |
1367 | insn |= (val & 0xf800) << 5; | |
1368 | bfd_putl32 (insn, buf); | |
1369 | fix->fx_r_type = BFD_RELOC_NONE; | |
1370 | fix->fx_done = 1; | |
1371 | } | |
4a4f25cf | 1372 | } |
305d537e | 1373 | else if (fup & OP_IMM_BR16) |
252b5132 | 1374 | { |
305d537e JE |
1375 | if (val & 0x3) |
1376 | as_bad_where (fix->fx_file, fix->fx_line, | |
1377 | _("A branch offset requires 0 MOD 4 alignment")); | |
1378 | ||
1379 | val = val >> 2; | |
1380 | ||
1381 | /* Insert the immediate. */ | |
ded0649c JE |
1382 | if (fix->fx_addsy) |
1383 | { | |
1384 | fix->fx_done = 0; | |
1385 | fix->fx_r_type = BFD_RELOC_860_PC16; | |
1386 | } | |
1387 | else | |
1388 | { | |
1389 | insn |= (val & 0x7ff); | |
1390 | insn |= ((val & 0xf800) << 5); | |
1391 | bfd_putl32 (insn, buf); | |
1392 | fix->fx_r_type = BFD_RELOC_NONE; | |
1393 | fix->fx_done = 1; | |
1394 | } | |
252b5132 | 1395 | } |
305d537e | 1396 | else if (fup & OP_IMM_BR26) |
252b5132 | 1397 | { |
305d537e JE |
1398 | if (val & 0x3) |
1399 | as_bad_where (fix->fx_file, fix->fx_line, | |
1400 | _("A branch offset requires 0 MOD 4 alignment")); | |
252b5132 | 1401 | |
305d537e | 1402 | val >>= 2; |
252b5132 | 1403 | |
305d537e | 1404 | /* Insert the immediate. */ |
ded0649c JE |
1405 | if (fix->fx_addsy) |
1406 | { | |
1407 | fix->fx_r_type = BFD_RELOC_860_PC26; | |
1408 | fix->fx_done = 0; | |
1409 | } | |
1410 | else | |
1411 | { | |
1412 | insn |= (val & 0x3ffffff); | |
1413 | bfd_putl32 (insn, buf); | |
1414 | fix->fx_r_type = BFD_RELOC_NONE; | |
1415 | fix->fx_done = 1; | |
1416 | } | |
305d537e JE |
1417 | } |
1418 | else if (fup != OP_NONE) | |
1419 | { | |
4a4f25cf | 1420 | as_bad_where (fix->fx_file, fix->fx_line, |
d444b726 | 1421 | _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup); |
305d537e JE |
1422 | abort (); |
1423 | } | |
1424 | else | |
1425 | { | |
1426 | /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000" | |
1427 | reach here (???). */ | |
ded0649c JE |
1428 | if (fix->fx_addsy) |
1429 | { | |
1430 | fix->fx_r_type = BFD_RELOC_32; | |
1431 | fix->fx_done = 0; | |
1432 | } | |
1433 | else | |
1434 | { | |
1435 | insn |= (val & 0xffffffff); | |
1436 | bfd_putl32 (insn, buf); | |
1437 | fix->fx_r_type = BFD_RELOC_NONE; | |
1438 | fix->fx_done = 1; | |
1439 | } | |
305d537e | 1440 | } |
252b5132 RH |
1441 | } |
1442 | ||
305d537e JE |
1443 | /* Generate a machine dependent reloc from a fixup. */ |
1444 | arelent* | |
7734b6e9 JE |
1445 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, |
1446 | fixS *fixp) | |
252b5132 | 1447 | { |
305d537e | 1448 | arelent *reloc; |
252b5132 | 1449 | |
305d537e JE |
1450 | reloc = xmalloc (sizeof (*reloc)); |
1451 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
1452 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
1453 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1454 | reloc->addend = fixp->fx_offset; | |
1455 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
252b5132 | 1456 | |
305d537e | 1457 | if (! reloc->howto) |
252b5132 | 1458 | { |
305d537e JE |
1459 | as_bad_where (fixp->fx_file, fixp->fx_line, |
1460 | "Cannot represent %s relocation in object file", | |
1461 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
252b5132 | 1462 | } |
305d537e | 1463 | return reloc; |
252b5132 | 1464 | } |