Commit | Line | Data |
---|---|---|
305d537e | 1 | /* tc-i860.c -- Assembler for the Intel i860 architecture. |
5a38dc70 | 2 | Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002 |
305d537e JE |
3 | Free Software Foundation, Inc. |
4 | ||
5 | Brought back from the dead and completely reworked | |
6 | by Jason Eckhardt <jle@cygnus.com>. | |
252b5132 RH |
7 | |
8 | This file is part of GAS, the GNU Assembler. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License along | |
21 | with GAS; see the file COPYING. If not, write to the Free Software | |
22 | Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
305d537e JE |
24 | #include <stdio.h> |
25 | #include <string.h> | |
252b5132 | 26 | #include "as.h" |
3882b010 | 27 | #include "safe-ctype.h" |
305d537e | 28 | #include "subsegs.h" |
252b5132 | 29 | #include "opcode/i860.h" |
305d537e | 30 | #include "elf/i860.h" |
252b5132 | 31 | |
305d537e JE |
32 | /* Defined by default since this is primarily a SVR4/860 assembler. |
33 | However, I'm trying to leave the door open for Intel syntax. Of course, | |
34 | if full support for anything other than SVR4 is done, then we should | |
35 | select this based on a command-line flag. */ | |
36 | #define SYNTAX_SVR4 | |
252b5132 | 37 | |
305d537e | 38 | /* The opcode hash table. */ |
252b5132 RH |
39 | static struct hash_control *op_hash = NULL; |
40 | ||
305d537e JE |
41 | /* These characters always start a comment. */ |
42 | const char comment_chars[] = "#!/"; | |
252b5132 | 43 | |
305d537e | 44 | /* These characters start a comment at the beginning of a line. */ |
252b5132 RH |
45 | const char line_comment_chars[] = "#/"; |
46 | ||
63a0b638 | 47 | const char line_separator_chars[] = ";"; |
252b5132 | 48 | |
305d537e JE |
49 | /* Characters that can be used to separate the mantissa from the exponent |
50 | in floating point numbers. */ | |
252b5132 RH |
51 | const char EXP_CHARS[] = "eE"; |
52 | ||
305d537e JE |
53 | /* Characters that indicate this number is a floating point constant. |
54 | As in 0f12.456 or 0d1.2345e12. */ | |
252b5132 RH |
55 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
56 | ||
305d537e JE |
57 | /* Register prefix. */ |
58 | #ifdef SYNTAX_SVR4 | |
59 | static const char reg_prefix = '%'; | |
60 | #else | |
61 | static const char reg_prefix = 0; | |
62 | #endif | |
63 | ||
673a54e3 JE |
64 | #define MAX_FIXUPS 2 |
65 | ||
252b5132 | 66 | struct i860_it |
305d537e JE |
67 | { |
68 | char *error; | |
69 | unsigned long opcode; | |
305d537e | 70 | enum expand_type expand; |
673a54e3 JE |
71 | struct i860_fi |
72 | { | |
73 | expressionS exp; | |
74 | bfd_reloc_code_real_type reloc; | |
75 | int pcrel; | |
76 | valueT fup; | |
77 | } fi[MAX_FIXUPS]; | |
305d537e JE |
78 | } the_insn; |
79 | ||
673a54e3 JE |
80 | /* The current fixup count. */ |
81 | static int fc; | |
82 | ||
305d537e | 83 | static char *expr_end; |
252b5132 | 84 | |
305d537e JE |
85 | /* Indicates error if a pseudo operation was expanded after a branch. */ |
86 | static char last_expand; | |
252b5132 | 87 | |
305d537e JE |
88 | /* If true, then warn if any pseudo operations were expanded. */ |
89 | static int target_warn_expand = 0; | |
252b5132 | 90 | |
305d537e JE |
91 | /* Prototypes. */ |
92 | static void i860_process_insn PARAMS ((char *)); | |
93 | static void s_dual PARAMS ((int)); | |
94 | static void s_enddual PARAMS ((int)); | |
95 | static void s_atmp PARAMS ((int)); | |
96 | static int i860_get_expression PARAMS ((char *)); | |
97 | static bfd_reloc_code_real_type obtain_reloc_for_imm16 | |
98 | PARAMS ((fixS *, long *)); | |
99 | #ifdef DEBUG_I860 | |
100 | static void print_insn PARAMS ((struct i860_it *)); | |
101 | #endif | |
252b5132 | 102 | |
305d537e JE |
103 | const pseudo_typeS md_pseudo_table[] = |
104 | { | |
105 | #ifdef OBJ_ELF | |
106 | {"align", s_align_bytes, 0}, | |
107 | #endif | |
108 | {"dual", s_dual, 0}, | |
109 | {"enddual", s_enddual, 0}, | |
110 | {"atmp", s_atmp, 0}, | |
111 | {NULL, 0, 0}, | |
112 | }; | |
113 | ||
305d537e | 114 | /* Dual-instruction mode handling. */ |
252b5132 RH |
115 | enum dual |
116 | { | |
117 | DUAL_OFF = 0, DUAL_ON, DUAL_DDOT, DUAL_ONDDOT, | |
118 | }; | |
305d537e JE |
119 | static enum dual dual_mode = DUAL_OFF; |
120 | ||
305d537e | 121 | /* Handle ".dual" directive. */ |
252b5132 | 122 | static void |
305d537e JE |
123 | s_dual (ignore) |
124 | int ignore ATTRIBUTE_UNUSED; | |
252b5132 RH |
125 | { |
126 | dual_mode = DUAL_ON; | |
127 | } | |
128 | ||
305d537e | 129 | /* Handle ".enddual" directive. */ |
252b5132 | 130 | static void |
305d537e JE |
131 | s_enddual (ignore) |
132 | int ignore ATTRIBUTE_UNUSED; | |
252b5132 RH |
133 | { |
134 | dual_mode = DUAL_OFF; | |
135 | } | |
136 | ||
305d537e JE |
137 | /* Temporary register used when expanding assembler pseudo operations. */ |
138 | static int atmp = 31; | |
252b5132 RH |
139 | |
140 | static void | |
305d537e JE |
141 | s_atmp (ignore) |
142 | int ignore ATTRIBUTE_UNUSED; | |
252b5132 RH |
143 | { |
144 | register int temp; | |
145 | if (strncmp (input_line_pointer, "sp", 2) == 0) | |
146 | { | |
147 | input_line_pointer += 2; | |
148 | atmp = 2; | |
149 | } | |
150 | else if (strncmp (input_line_pointer, "fp", 2) == 0) | |
151 | { | |
152 | input_line_pointer += 2; | |
153 | atmp = 3; | |
154 | } | |
155 | else if (strncmp (input_line_pointer, "r", 1) == 0) | |
156 | { | |
157 | input_line_pointer += 1; | |
158 | temp = get_absolute_expression (); | |
159 | if (temp >= 0 && temp <= 31) | |
160 | atmp = temp; | |
161 | else | |
162 | as_bad (_("Unknown temporary pseudo register")); | |
163 | } | |
164 | else | |
165 | { | |
166 | as_bad (_("Unknown temporary pseudo register")); | |
167 | } | |
168 | demand_empty_rest_of_line (); | |
169 | } | |
170 | ||
171 | /* This function is called once, at assembler startup time. It should | |
305d537e JE |
172 | set up all the tables and data structures that the MD part of the |
173 | assembler will need. */ | |
252b5132 RH |
174 | void |
175 | md_begin () | |
176 | { | |
305d537e | 177 | const char *retval = NULL; |
252b5132 | 178 | int lose = 0; |
305d537e | 179 | unsigned int i = 0; |
252b5132 RH |
180 | |
181 | op_hash = hash_new (); | |
182 | ||
305d537e | 183 | while (i860_opcodes[i].name != NULL) |
252b5132 RH |
184 | { |
185 | const char *name = i860_opcodes[i].name; | |
305d537e | 186 | retval = hash_insert (op_hash, name, (PTR)&i860_opcodes[i]); |
252b5132 RH |
187 | if (retval != NULL) |
188 | { | |
189 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
190 | i860_opcodes[i].name, retval); | |
191 | lose = 1; | |
192 | } | |
193 | do | |
194 | { | |
195 | if (i860_opcodes[i].match & i860_opcodes[i].lose) | |
196 | { | |
305d537e JE |
197 | fprintf (stderr, |
198 | _("internal error: losing opcode: `%s' \"%s\"\n"), | |
252b5132 RH |
199 | i860_opcodes[i].name, i860_opcodes[i].args); |
200 | lose = 1; | |
201 | } | |
202 | ++i; | |
203 | } | |
305d537e JE |
204 | while (i860_opcodes[i].name != NULL |
205 | && strcmp (i860_opcodes[i].name, name) == 0); | |
252b5132 RH |
206 | } |
207 | ||
208 | if (lose) | |
305d537e | 209 | as_fatal (_("Defective assembler. No assembly attempted.")); |
252b5132 RH |
210 | } |
211 | ||
305d537e JE |
212 | /* This is the core of the machine-dependent assembler. STR points to a |
213 | machine dependent instruction. This function emits the frags/bytes | |
214 | it assembles to. */ | |
252b5132 RH |
215 | void |
216 | md_assemble (str) | |
217 | char *str; | |
218 | { | |
305d537e JE |
219 | char *destp; |
220 | int num_opcodes = 1; | |
252b5132 RH |
221 | int i; |
222 | struct i860_it pseudo[3]; | |
223 | ||
224 | assert (str); | |
673a54e3 | 225 | fc = 0; |
252b5132 | 226 | |
305d537e JE |
227 | /* Assemble the instruction. */ |
228 | i860_process_insn (str); | |
229 | ||
230 | /* Check for expandable flag to produce pseudo-instructions. This | |
231 | is an undesirable feature that should be avoided. */ | |
232 | if (the_insn.expand != 0 | |
673a54e3 | 233 | && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT |
305d537e | 234 | | OP_SEL_GOTOFF | OP_SEL_PLT))) |
252b5132 RH |
235 | { |
236 | for (i = 0; i < 3; i++) | |
237 | pseudo[i] = the_insn; | |
238 | ||
673a54e3 | 239 | fc = 1; |
252b5132 RH |
240 | switch (the_insn.expand) |
241 | { | |
242 | ||
243 | case E_DELAY: | |
305d537e | 244 | num_opcodes = 1; |
252b5132 RH |
245 | break; |
246 | ||
247 | case E_MOV: | |
673a54e3 JE |
248 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
249 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
250 | && (the_insn.fi[0].exp.X_add_number < (1 << 15) | |
251 | && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) | |
252b5132 | 252 | break; |
305d537e JE |
253 | |
254 | /* Emit "or l%const,r0,ireg_dest". */ | |
252b5132 | 255 | pseudo[0].opcode = (the_insn.opcode & 0x001f0000) | 0xe4000000; |
673a54e3 | 256 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); |
305d537e JE |
257 | |
258 | /* Emit "orh h%const,ireg_dest,ireg_dest". */ | |
259 | pseudo[1].opcode = (the_insn.opcode & 0x03ffffff) | 0xec000000 | |
260 | | ((the_insn.opcode & 0x001f0000) << 5); | |
673a54e3 | 261 | pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); |
305d537e JE |
262 | |
263 | num_opcodes = 2; | |
252b5132 RH |
264 | break; |
265 | ||
266 | case E_ADDR: | |
673a54e3 JE |
267 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
268 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
269 | && (the_insn.fi[0].exp.X_add_number < (1 << 15) | |
270 | && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) | |
252b5132 | 271 | break; |
305d537e JE |
272 | |
273 | /* Emit "orh ha%addr_expr,r0,r31". */ | |
252b5132 | 274 | pseudo[0].opcode = 0xec000000 | (atmp << 16); |
673a54e3 | 275 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_HA); |
305d537e JE |
276 | |
277 | /* Emit "l%addr_expr(r31),ireg_dest". We pick up the fixup | |
278 | information from the original instruction. */ | |
279 | pseudo[1].opcode = (the_insn.opcode & ~0x03e00000) | (atmp << 21); | |
673a54e3 | 280 | pseudo[1].fi[0].fup = the_insn.fi[0].fup | OP_SEL_L; |
305d537e JE |
281 | |
282 | num_opcodes = 2; | |
252b5132 RH |
283 | break; |
284 | ||
305d537e | 285 | case E_U32: |
673a54e3 JE |
286 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
287 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
288 | && (the_insn.fi[0].exp.X_add_number < (1 << 16) | |
289 | && the_insn.fi[0].exp.X_add_number >= 0)) | |
252b5132 | 290 | break; |
305d537e JE |
291 | |
292 | /* Emit "$(opcode)h h%const,ireg_src2,r31". */ | |
293 | pseudo[0].opcode = (the_insn.opcode & 0xf3e0ffff) | 0x0c000000 | |
294 | | (atmp << 16); | |
673a54e3 | 295 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); |
305d537e JE |
296 | |
297 | /* Emit "$(opcode) l%const,r31,ireg_dest". */ | |
298 | pseudo[1].opcode = (the_insn.opcode & 0xf01f0000) | 0x04000000 | |
299 | | (atmp << 21); | |
673a54e3 | 300 | pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); |
305d537e JE |
301 | |
302 | num_opcodes = 2; | |
252b5132 RH |
303 | break; |
304 | ||
305d537e | 305 | case E_AND: |
673a54e3 JE |
306 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
307 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
308 | && (the_insn.fi[0].exp.X_add_number < (1 << 16) | |
309 | && the_insn.fi[0].exp.X_add_number >= 0)) | |
252b5132 | 310 | break; |
305d537e JE |
311 | |
312 | /* Emit "andnot h%const,ireg_src2,r31". */ | |
313 | pseudo[0].opcode = (the_insn.opcode & 0x03e0ffff) | 0xd4000000 | |
314 | | (atmp << 16); | |
673a54e3 JE |
315 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); |
316 | pseudo[0].fi[0].exp.X_add_number = | |
317 | -1 - the_insn.fi[0].exp.X_add_number; | |
305d537e JE |
318 | |
319 | /* Emit "andnot l%const,r31,ireg_dest". */ | |
320 | pseudo[1].opcode = (the_insn.opcode & 0x001f0000) | 0xd4000000 | |
321 | | (atmp << 21); | |
673a54e3 JE |
322 | pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); |
323 | pseudo[1].fi[0].exp.X_add_number = | |
324 | -1 - the_insn.fi[0].exp.X_add_number; | |
305d537e JE |
325 | |
326 | num_opcodes = 2; | |
252b5132 RH |
327 | break; |
328 | ||
329 | case E_S32: | |
673a54e3 JE |
330 | if (the_insn.fi[0].exp.X_add_symbol == NULL |
331 | && the_insn.fi[0].exp.X_op_symbol == NULL | |
332 | && (the_insn.fi[0].exp.X_add_number < (1 << 15) | |
333 | && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) | |
252b5132 | 334 | break; |
305d537e JE |
335 | |
336 | /* Emit "orh h%const,r0,r31". */ | |
252b5132 | 337 | pseudo[0].opcode = 0xec000000 | (atmp << 16); |
673a54e3 | 338 | pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); |
305d537e JE |
339 | |
340 | /* Emit "or l%const,r31,r31". */ | |
252b5132 | 341 | pseudo[1].opcode = 0xe4000000 | (atmp << 21) | (atmp << 16); |
673a54e3 | 342 | pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); |
305d537e JE |
343 | |
344 | /* Emit "r31,ireg_src2,ireg_dest". */ | |
252b5132 | 345 | pseudo[2].opcode = (the_insn.opcode & ~0x0400ffff) | (atmp << 11); |
673a54e3 | 346 | pseudo[2].fi[0].fup = OP_IMM_S16; |
305d537e JE |
347 | |
348 | num_opcodes = 3; | |
252b5132 RH |
349 | break; |
350 | ||
351 | default: | |
352 | as_fatal (_("failed sanity check.")); | |
353 | } | |
354 | ||
355 | the_insn = pseudo[0]; | |
305d537e JE |
356 | |
357 | /* Warn if an opcode is expanded after a delayed branch. */ | |
358 | if (num_opcodes > 1 && last_expand == 1) | |
252b5132 | 359 | as_warn (_("Expanded opcode after delayed branch: `%s'"), str); |
305d537e JE |
360 | |
361 | /* Warn if an opcode is expanded in dual mode. */ | |
362 | if (num_opcodes > 1 && dual_mode != DUAL_OFF) | |
252b5132 | 363 | as_warn (_("Expanded opcode in dual mode: `%s'"), str); |
305d537e JE |
364 | |
365 | /* Notify if any expansions happen. */ | |
366 | if (target_warn_expand && num_opcodes > 1) | |
367 | as_warn (_("An instruction was expanded (%s)"), str); | |
252b5132 RH |
368 | } |
369 | ||
370 | i = 0; | |
371 | do | |
305d537e | 372 | { |
673a54e3 JE |
373 | int tmp; |
374 | ||
305d537e JE |
375 | /* Output the opcode. Note that the i860 always reads instructions |
376 | as little-endian data. */ | |
377 | destp = frag_more (4); | |
378 | number_to_chars_littleendian (destp, the_insn.opcode, 4); | |
252b5132 | 379 | |
305d537e | 380 | /* Check for expanded opcode after branch or in dual mode. */ |
673a54e3 JE |
381 | last_expand = the_insn.fi[0].pcrel; |
382 | ||
383 | /* Output the symbol-dependent stuff. Only btne and bte will ever | |
384 | loop more than once here, since only they (possibly) have more | |
385 | than one fixup. */ | |
386 | for (tmp = 0; tmp < fc; tmp++) | |
387 | { | |
388 | if (the_insn.fi[tmp].fup != OP_NONE) | |
389 | { | |
390 | fixS *fix; | |
391 | fix = fix_new_exp (frag_now, | |
392 | destp - frag_now->fr_literal, | |
393 | 4, | |
394 | &the_insn.fi[tmp].exp, | |
395 | the_insn.fi[tmp].pcrel, | |
396 | the_insn.fi[tmp].reloc); | |
397 | ||
398 | /* Despite the odd name, this is a scratch field. We use | |
399 | it to encode operand type information. */ | |
400 | fix->fx_addnumber = the_insn.fi[tmp].fup; | |
401 | } | |
402 | } | |
252b5132 RH |
403 | the_insn = pseudo[++i]; |
404 | } | |
305d537e | 405 | while (--num_opcodes > 0); |
252b5132 RH |
406 | |
407 | } | |
408 | ||
305d537e | 409 | /* Assemble the instruction pointed to by STR. */ |
252b5132 | 410 | static void |
305d537e | 411 | i860_process_insn (str) |
252b5132 RH |
412 | char *str; |
413 | { | |
414 | char *s; | |
415 | const char *args; | |
416 | char c; | |
252b5132 | 417 | struct i860_opcode *insn; |
305d537e | 418 | char *args_start; |
252b5132 RH |
419 | unsigned long opcode; |
420 | unsigned int mask; | |
421 | int match = 0; | |
422 | int comma = 0; | |
423 | ||
305d537e JE |
424 | #if 1 /* For compiler warnings. */ |
425 | args = 0; | |
426 | insn = 0; | |
427 | args_start = 0; | |
428 | opcode = 0; | |
429 | #endif | |
252b5132 | 430 | |
3882b010 | 431 | for (s = str; ISLOWER (*s) || *s == '.' || *s == '3' |
305d537e | 432 | || *s == '2' || *s == '1'; ++s) |
252b5132 | 433 | ; |
305d537e | 434 | |
252b5132 RH |
435 | switch (*s) |
436 | { | |
252b5132 RH |
437 | case '\0': |
438 | break; | |
439 | ||
440 | case ',': | |
441 | comma = 1; | |
442 | ||
443 | /*FALLTHROUGH*/ | |
444 | ||
445 | case ' ': | |
446 | *s++ = '\0'; | |
447 | break; | |
448 | ||
449 | default: | |
450 | as_fatal (_("Unknown opcode: `%s'"), str); | |
451 | } | |
452 | ||
305d537e | 453 | /* Check for dual mode ("d.") opcode prefix. */ |
252b5132 | 454 | if (strncmp (str, "d.", 2) == 0) |
305d537e | 455 | { |
252b5132 RH |
456 | if (dual_mode == DUAL_ON) |
457 | dual_mode = DUAL_ONDDOT; | |
458 | else | |
459 | dual_mode = DUAL_DDOT; | |
460 | str += 2; | |
461 | } | |
462 | ||
463 | if ((insn = (struct i860_opcode *) hash_find (op_hash, str)) == NULL) | |
464 | { | |
465 | if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT) | |
466 | str -= 2; | |
467 | as_bad (_("Unknown opcode: `%s'"), str); | |
468 | return; | |
469 | } | |
305d537e | 470 | |
252b5132 | 471 | if (comma) |
305d537e JE |
472 | *--s = ','; |
473 | ||
474 | args_start = s; | |
252b5132 RH |
475 | for (;;) |
476 | { | |
673a54e3 | 477 | int t; |
252b5132 RH |
478 | opcode = insn->match; |
479 | memset (&the_insn, '\0', sizeof (the_insn)); | |
673a54e3 JE |
480 | for (t = 0; t < MAX_FIXUPS; t++) |
481 | { | |
482 | the_insn.fi[t].reloc = BFD_RELOC_NONE; | |
483 | the_insn.fi[t].pcrel = 0; | |
484 | the_insn.fi[t].fup = OP_NONE; | |
485 | } | |
252b5132 | 486 | |
305d537e JE |
487 | /* Build the opcode, checking as we go that the operands match. */ |
488 | for (args = insn->args; ; ++args) | |
252b5132 | 489 | { |
673a54e3 JE |
490 | if (fc > MAX_FIXUPS) |
491 | abort (); | |
492 | ||
252b5132 RH |
493 | switch (*args) |
494 | { | |
495 | ||
305d537e JE |
496 | /* End of args. */ |
497 | case '\0': | |
252b5132 | 498 | if (*s == '\0') |
305d537e | 499 | match = 1; |
252b5132 RH |
500 | break; |
501 | ||
305d537e | 502 | /* These must match exactly. */ |
252b5132 | 503 | case '+': |
305d537e | 504 | case '(': |
252b5132 RH |
505 | case ')': |
506 | case ',': | |
507 | case ' ': | |
508 | if (*s++ == *args) | |
509 | continue; | |
510 | break; | |
511 | ||
305d537e JE |
512 | /* Must be at least one digit. */ |
513 | case '#': | |
3882b010 | 514 | if (ISDIGIT (*s++)) |
252b5132 | 515 | { |
3882b010 | 516 | while (ISDIGIT (*s)) |
305d537e | 517 | ++s; |
252b5132 RH |
518 | continue; |
519 | } | |
520 | break; | |
521 | ||
305d537e JE |
522 | /* Next operand must be a register. */ |
523 | case '1': | |
252b5132 RH |
524 | case '2': |
525 | case 'd': | |
305d537e JE |
526 | /* Check for register prefix if necessary. */ |
527 | if (reg_prefix && *s != reg_prefix) | |
528 | goto error; | |
529 | else | |
530 | s++; | |
531 | ||
252b5132 RH |
532 | switch (*s) |
533 | { | |
305d537e JE |
534 | /* Frame pointer. */ |
535 | case 'f': | |
252b5132 RH |
536 | s++; |
537 | if (*s++ == 'p') | |
538 | { | |
539 | mask = 0x3; | |
540 | break; | |
541 | } | |
542 | goto error; | |
543 | ||
305d537e JE |
544 | /* Stack pointer. */ |
545 | case 's': | |
252b5132 RH |
546 | s++; |
547 | if (*s++ == 'p') | |
548 | { | |
549 | mask = 0x2; | |
550 | break; | |
551 | } | |
552 | goto error; | |
553 | ||
305d537e JE |
554 | /* Any register r0..r31. */ |
555 | case 'r': | |
252b5132 | 556 | s++; |
3882b010 | 557 | if (!ISDIGIT (c = *s++)) |
252b5132 RH |
558 | { |
559 | goto error; | |
560 | } | |
3882b010 | 561 | if (ISDIGIT (*s)) |
252b5132 RH |
562 | { |
563 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
305d537e | 564 | goto error; |
252b5132 RH |
565 | } |
566 | else | |
305d537e | 567 | c -= '0'; |
252b5132 RH |
568 | mask = c; |
569 | break; | |
570 | ||
305d537e JE |
571 | /* Not this opcode. */ |
572 | default: | |
252b5132 RH |
573 | goto error; |
574 | } | |
305d537e JE |
575 | |
576 | /* Obtained the register, now place it in the opcode. */ | |
252b5132 RH |
577 | switch (*args) |
578 | { | |
252b5132 RH |
579 | case '1': |
580 | opcode |= mask << 11; | |
581 | continue; | |
582 | ||
583 | case '2': | |
584 | opcode |= mask << 21; | |
585 | continue; | |
586 | ||
587 | case 'd': | |
588 | opcode |= mask << 16; | |
589 | continue; | |
590 | ||
591 | } | |
592 | break; | |
593 | ||
305d537e JE |
594 | /* Next operand is a floating point register. */ |
595 | case 'e': | |
252b5132 RH |
596 | case 'f': |
597 | case 'g': | |
305d537e JE |
598 | /* Check for register prefix if necessary. */ |
599 | if (reg_prefix && *s != reg_prefix) | |
600 | goto error; | |
601 | else | |
602 | s++; | |
603 | ||
3882b010 | 604 | if (*s++ == 'f' && ISDIGIT (*s)) |
252b5132 RH |
605 | { |
606 | mask = *s++; | |
3882b010 | 607 | if (ISDIGIT (*s)) |
252b5132 RH |
608 | { |
609 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
610 | if (mask >= 32) | |
611 | { | |
612 | break; | |
613 | } | |
614 | } | |
615 | else | |
305d537e JE |
616 | mask -= '0'; |
617 | ||
252b5132 RH |
618 | switch (*args) |
619 | { | |
620 | ||
621 | case 'e': | |
622 | opcode |= mask << 11; | |
623 | continue; | |
624 | ||
625 | case 'f': | |
626 | opcode |= mask << 21; | |
627 | continue; | |
628 | ||
629 | case 'g': | |
630 | opcode |= mask << 16; | |
631 | if (dual_mode != DUAL_OFF) | |
305d537e | 632 | opcode |= (1 << 9); |
252b5132 RH |
633 | if (dual_mode == DUAL_DDOT) |
634 | dual_mode = DUAL_OFF; | |
635 | if (dual_mode == DUAL_ONDDOT) | |
636 | dual_mode = DUAL_ON; | |
305d537e JE |
637 | if ((opcode & (1 << 10)) && mask != 0 |
638 | && (mask == ((opcode >> 11) & 0x1f))) | |
639 | as_warn (_("Pipelined instruction: fsrc1 = fdest")); | |
252b5132 RH |
640 | continue; |
641 | } | |
642 | } | |
643 | break; | |
644 | ||
305d537e JE |
645 | /* Next operand must be a control register. */ |
646 | case 'c': | |
647 | /* Check for register prefix if necessary. */ | |
648 | if (reg_prefix && *s != reg_prefix) | |
649 | goto error; | |
650 | else | |
651 | s++; | |
652 | ||
252b5132 RH |
653 | if (strncmp (s, "fir", 3) == 0) |
654 | { | |
655 | opcode |= 0x0 << 21; | |
656 | s += 3; | |
657 | continue; | |
658 | } | |
659 | if (strncmp (s, "psr", 3) == 0) | |
660 | { | |
661 | opcode |= 0x1 << 21; | |
662 | s += 3; | |
663 | continue; | |
664 | } | |
665 | if (strncmp (s, "dirbase", 7) == 0) | |
666 | { | |
667 | opcode |= 0x2 << 21; | |
668 | s += 7; | |
669 | continue; | |
670 | } | |
671 | if (strncmp (s, "db", 2) == 0) | |
672 | { | |
673 | opcode |= 0x3 << 21; | |
674 | s += 2; | |
675 | continue; | |
676 | } | |
677 | if (strncmp (s, "fsr", 3) == 0) | |
678 | { | |
679 | opcode |= 0x4 << 21; | |
680 | s += 3; | |
681 | continue; | |
682 | } | |
683 | if (strncmp (s, "epsr", 4) == 0) | |
684 | { | |
685 | opcode |= 0x5 << 21; | |
686 | s += 4; | |
687 | continue; | |
688 | } | |
689 | break; | |
690 | ||
305d537e JE |
691 | /* 5-bit immediate in src1. */ |
692 | case '5': | |
693 | if (! i860_get_expression (s)) | |
252b5132 RH |
694 | { |
695 | s = expr_end; | |
673a54e3 JE |
696 | the_insn.fi[fc].fup |= OP_IMM_U5; |
697 | fc++; | |
252b5132 RH |
698 | continue; |
699 | } | |
700 | break; | |
701 | ||
305d537e JE |
702 | /* 26-bit immediate, relative branch (lbroff). */ |
703 | case 'l': | |
673a54e3 JE |
704 | the_insn.fi[fc].pcrel = 1; |
705 | the_insn.fi[fc].fup |= OP_IMM_BR26; | |
252b5132 RH |
706 | goto immediate; |
707 | ||
305d537e JE |
708 | /* 16-bit split immediate, relative branch (sbroff). */ |
709 | case 'r': | |
673a54e3 JE |
710 | the_insn.fi[fc].pcrel = 1; |
711 | the_insn.fi[fc].fup |= OP_IMM_BR16; | |
252b5132 RH |
712 | goto immediate; |
713 | ||
305d537e JE |
714 | /* 16-bit split immediate. */ |
715 | case 's': | |
673a54e3 | 716 | the_insn.fi[fc].fup |= OP_IMM_SPLIT16; |
305d537e JE |
717 | goto immediate; |
718 | ||
719 | /* 16-bit split immediate, byte aligned (st.b). */ | |
720 | case 'S': | |
673a54e3 | 721 | the_insn.fi[fc].fup |= OP_IMM_SPLIT16; |
305d537e JE |
722 | goto immediate; |
723 | ||
724 | /* 16-bit split immediate, half-word aligned (st.s). */ | |
725 | case 'T': | |
673a54e3 | 726 | the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN2); |
305d537e JE |
727 | goto immediate; |
728 | ||
729 | /* 16-bit split immediate, word aligned (st.l). */ | |
730 | case 'U': | |
673a54e3 | 731 | the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN4); |
305d537e JE |
732 | goto immediate; |
733 | ||
734 | /* 16-bit immediate. */ | |
735 | case 'i': | |
673a54e3 | 736 | the_insn.fi[fc].fup |= OP_IMM_S16; |
305d537e JE |
737 | goto immediate; |
738 | ||
739 | /* 16-bit immediate, byte aligned (ld.b). */ | |
740 | case 'I': | |
673a54e3 | 741 | the_insn.fi[fc].fup |= OP_IMM_S16; |
305d537e JE |
742 | goto immediate; |
743 | ||
744 | /* 16-bit immediate, half-word aligned (ld.s). */ | |
745 | case 'J': | |
673a54e3 | 746 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN2); |
252b5132 RH |
747 | goto immediate; |
748 | ||
305d537e JE |
749 | /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l). */ |
750 | case 'K': | |
751 | if (insn->name[0] == 'l') | |
673a54e3 | 752 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN4); |
252b5132 | 753 | else |
673a54e3 | 754 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE2 | OP_ALIGN4); |
305d537e JE |
755 | goto immediate; |
756 | ||
757 | /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d). */ | |
758 | case 'L': | |
673a54e3 | 759 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN8); |
252b5132 RH |
760 | goto immediate; |
761 | ||
305d537e JE |
762 | /* 16-bit immediate, quad-word aligned (fld.q, fst.q). */ |
763 | case 'M': | |
673a54e3 | 764 | the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN16); |
252b5132 RH |
765 | |
766 | /*FALLTHROUGH*/ | |
767 | ||
305d537e JE |
768 | /* Handle the immediate for either the Intel syntax or |
769 | SVR4 syntax. The Intel syntax is "ha%immediate" | |
770 | whereas SVR4 syntax is "[immediate]@ha". */ | |
252b5132 | 771 | immediate: |
305d537e JE |
772 | #ifdef SYNTAX_SVR4 |
773 | if (*s == ' ') | |
774 | s++; | |
775 | ||
776 | /* Note that if i860_get_expression() fails, we will still | |
777 | have created U entries in the symbol table for the | |
778 | 'symbols' in the input string. Try not to create U | |
779 | symbols for registers, etc. */ | |
780 | if (! i860_get_expression (s)) | |
781 | s = expr_end; | |
782 | else | |
783 | goto error; | |
784 | ||
785 | if (strncmp (s, "@ha", 3) == 0) | |
786 | { | |
673a54e3 | 787 | the_insn.fi[fc].fup |= OP_SEL_HA; |
305d537e JE |
788 | s += 3; |
789 | } | |
790 | else if (strncmp (s, "@h", 2) == 0) | |
791 | { | |
673a54e3 | 792 | the_insn.fi[fc].fup |= OP_SEL_H; |
305d537e JE |
793 | s += 2; |
794 | } | |
795 | else if (strncmp (s, "@l", 2) == 0) | |
796 | { | |
673a54e3 | 797 | the_insn.fi[fc].fup |= OP_SEL_L; |
305d537e JE |
798 | s += 2; |
799 | } | |
800 | else if (strncmp (s, "@gotoff", 7) == 0 | |
801 | || strncmp (s, "@GOTOFF", 7) == 0) | |
802 | { | |
803 | as_bad (_("Assembler does not yet support PIC")); | |
673a54e3 | 804 | the_insn.fi[fc].fup |= OP_SEL_GOTOFF; |
305d537e JE |
805 | s += 7; |
806 | } | |
807 | else if (strncmp (s, "@got", 4) == 0 | |
808 | || strncmp (s, "@GOT", 4) == 0) | |
809 | { | |
810 | as_bad (_("Assembler does not yet support PIC")); | |
673a54e3 | 811 | the_insn.fi[fc].fup |= OP_SEL_GOT; |
305d537e JE |
812 | s += 4; |
813 | } | |
814 | else if (strncmp (s, "@plt", 4) == 0 | |
815 | || strncmp (s, "@PLT", 4) == 0) | |
816 | { | |
817 | as_bad (_("Assembler does not yet support PIC")); | |
673a54e3 | 818 | the_insn.fi[fc].fup |= OP_SEL_PLT; |
305d537e JE |
819 | s += 4; |
820 | } | |
821 | ||
822 | the_insn.expand = insn->expand; | |
673a54e3 JE |
823 | fc++; |
824 | ||
305d537e JE |
825 | continue; |
826 | #else /* ! SYNTAX_SVR4 */ | |
252b5132 RH |
827 | if (*s == ' ') |
828 | s++; | |
829 | if (strncmp (s, "ha%", 3) == 0) | |
830 | { | |
673a54e3 | 831 | the_insn.fi[fc].fup |= OP_SEL_HA; |
252b5132 RH |
832 | s += 3; |
833 | } | |
834 | else if (strncmp (s, "h%", 2) == 0) | |
835 | { | |
673a54e3 | 836 | the_insn.fi[fc].fup |= OP_SEL_H; |
252b5132 RH |
837 | s += 2; |
838 | } | |
839 | else if (strncmp (s, "l%", 2) == 0) | |
840 | { | |
673a54e3 | 841 | the_insn.fi[fc].fup |= OP_SEL_L; |
252b5132 RH |
842 | s += 2; |
843 | } | |
844 | the_insn.expand = insn->expand; | |
845 | ||
305d537e JE |
846 | /* Note that if i860_get_expression() fails, we will still |
847 | have created U entries in the symbol table for the | |
848 | 'symbols' in the input string. Try not to create U | |
849 | symbols for registers, etc. */ | |
850 | if (! i860_get_expression (s)) | |
851 | s = expr_end; | |
852 | else | |
853 | goto error; | |
252b5132 | 854 | |
673a54e3 | 855 | fc++; |
305d537e JE |
856 | continue; |
857 | #endif /* SYNTAX_SVR4 */ | |
252b5132 RH |
858 | break; |
859 | ||
860 | default: | |
861 | as_fatal (_("failed sanity check.")); | |
862 | } | |
863 | break; | |
864 | } | |
865 | error: | |
866 | if (match == 0) | |
867 | { | |
868 | /* Args don't match. */ | |
305d537e JE |
869 | if (insn[1].name != NULL |
870 | && ! strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
871 | { |
872 | ++insn; | |
305d537e | 873 | s = args_start; |
252b5132 RH |
874 | continue; |
875 | } | |
876 | else | |
877 | { | |
305d537e | 878 | as_bad (_("Illegal operands for %s"), insn->name); |
252b5132 RH |
879 | return; |
880 | } | |
881 | } | |
882 | break; | |
883 | } | |
884 | ||
885 | the_insn.opcode = opcode; | |
886 | } | |
887 | ||
888 | static int | |
305d537e | 889 | i860_get_expression (str) |
252b5132 RH |
890 | char *str; |
891 | { | |
892 | char *save_in; | |
893 | segT seg; | |
894 | ||
895 | save_in = input_line_pointer; | |
896 | input_line_pointer = str; | |
673a54e3 | 897 | seg = expression (&the_insn.fi[fc].exp); |
252b5132 RH |
898 | if (seg != absolute_section |
899 | && seg != undefined_section | |
900 | && ! SEG_NORMAL (seg)) | |
901 | { | |
902 | the_insn.error = _("bad segment"); | |
903 | expr_end = input_line_pointer; | |
904 | input_line_pointer = save_in; | |
905 | return 1; | |
906 | } | |
907 | expr_end = input_line_pointer; | |
908 | input_line_pointer = save_in; | |
909 | return 0; | |
910 | } | |
911 | ||
305d537e JE |
912 | /* Turn a string in input_line_pointer into a floating point constant of |
913 | type TYPE, and store the appropriate bytes in *LITP. The number of | |
914 | LITTLENUMS emitted is stored in *SIZEP. An error message is returned, | |
915 | or NULL on OK. */ | |
252b5132 | 916 | |
305d537e | 917 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
918 | #define MAX_LITTLENUMS 6 |
919 | ||
920 | char * | |
921 | md_atof (type, litP, sizeP) | |
922 | char type; | |
923 | char *litP; | |
924 | int *sizeP; | |
925 | { | |
926 | int prec; | |
927 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
928 | LITTLENUM_TYPE *wordP; | |
929 | char *t; | |
252b5132 RH |
930 | |
931 | switch (type) | |
932 | { | |
252b5132 RH |
933 | case 'f': |
934 | case 'F': | |
935 | case 's': | |
936 | case 'S': | |
937 | prec = 2; | |
938 | break; | |
939 | ||
940 | case 'd': | |
941 | case 'D': | |
942 | case 'r': | |
943 | case 'R': | |
944 | prec = 4; | |
945 | break; | |
946 | ||
947 | case 'x': | |
948 | case 'X': | |
949 | prec = 6; | |
950 | break; | |
951 | ||
952 | case 'p': | |
953 | case 'P': | |
954 | prec = 6; | |
955 | break; | |
956 | ||
957 | default: | |
958 | *sizeP = 0; | |
959 | return _("Bad call to MD_ATOF()"); | |
960 | } | |
961 | t = atof_ieee (input_line_pointer, type, words); | |
962 | if (t) | |
963 | input_line_pointer = t; | |
964 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
965 | for (wordP = words; prec--;) | |
966 | { | |
967 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); | |
968 | litP += sizeof (LITTLENUM_TYPE); | |
969 | } | |
970 | return 0; | |
971 | } | |
972 | ||
305d537e | 973 | /* Write out in current endian mode. */ |
252b5132 RH |
974 | void |
975 | md_number_to_chars (buf, val, n) | |
976 | char *buf; | |
977 | valueT val; | |
978 | int n; | |
979 | { | |
305d537e JE |
980 | if (target_big_endian) |
981 | number_to_chars_bigendian (buf, val, n); | |
982 | else | |
983 | number_to_chars_littleendian (buf, val, n); | |
252b5132 RH |
984 | } |
985 | ||
305d537e | 986 | /* This should never be called for i860. */ |
252b5132 RH |
987 | int |
988 | md_estimate_size_before_relax (fragP, segtype) | |
305d537e JE |
989 | register fragS *fragP ATTRIBUTE_UNUSED; |
990 | segT segtype ATTRIBUTE_UNUSED; | |
252b5132 RH |
991 | { |
992 | as_fatal (_("i860_estimate_size_before_relax\n")); | |
993 | } | |
994 | ||
305d537e | 995 | #ifdef DEBUG_I860 |
252b5132 RH |
996 | static void |
997 | print_insn (insn) | |
998 | struct i860_it *insn; | |
999 | { | |
1000 | if (insn->error) | |
305d537e JE |
1001 | fprintf (stderr, "ERROR: %s\n", insn->error); |
1002 | ||
1003 | fprintf (stderr, "opcode = 0x%08lx\t", insn->opcode); | |
1004 | fprintf (stderr, "expand = 0x%x\t", insn->expand); | |
1005 | fprintf (stderr, "reloc = %s\t\n", | |
1006 | bfd_get_reloc_code_name (insn->reloc)); | |
252b5132 RH |
1007 | fprintf (stderr, "exp = {\n"); |
1008 | fprintf (stderr, "\t\tX_add_symbol = %s\n", | |
1009 | insn->exp.X_add_symbol ? | |
1010 | (S_GET_NAME (insn->exp.X_add_symbol) ? | |
1011 | S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0"); | |
1012 | fprintf (stderr, "\t\tX_op_symbol = %s\n", | |
1013 | insn->exp.X_op_symbol ? | |
1014 | (S_GET_NAME (insn->exp.X_op_symbol) ? | |
1015 | S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0"); | |
305d537e | 1016 | fprintf (stderr, "\t\tX_add_number = %lx\n", |
252b5132 RH |
1017 | insn->exp.X_add_number); |
1018 | fprintf (stderr, "}\n"); | |
1019 | } | |
305d537e JE |
1020 | #endif /* DEBUG_I860 */ |
1021 | ||
252b5132 | 1022 | \f |
305d537e | 1023 | #ifdef OBJ_ELF |
5a38dc70 | 1024 | const char *md_shortopts = "VQ:"; |
305d537e | 1025 | #else |
5a38dc70 | 1026 | const char *md_shortopts = ""; |
305d537e JE |
1027 | #endif |
1028 | ||
305d537e JE |
1029 | #define OPTION_EB (OPTION_MD_BASE + 0) |
1030 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
1031 | #define OPTION_WARN_EXPAND (OPTION_MD_BASE + 2) | |
1032 | ||
252b5132 | 1033 | struct option md_longopts[] = { |
305d537e JE |
1034 | { "EB", no_argument, NULL, OPTION_EB }, |
1035 | { "EL", no_argument, NULL, OPTION_EL }, | |
1036 | { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND }, | |
1037 | { NULL, no_argument, NULL, 0 } | |
252b5132 | 1038 | }; |
305d537e JE |
1039 | size_t md_longopts_size = sizeof (md_longopts); |
1040 | ||
252b5132 RH |
1041 | int |
1042 | md_parse_option (c, arg) | |
1043 | int c; | |
305d537e | 1044 | char *arg ATTRIBUTE_UNUSED; |
252b5132 | 1045 | { |
305d537e JE |
1046 | switch (c) |
1047 | { | |
1048 | case OPTION_EB: | |
1049 | target_big_endian = 1; | |
1050 | break; | |
1051 | ||
1052 | case OPTION_EL: | |
1053 | target_big_endian = 0; | |
1054 | break; | |
1055 | ||
1056 | case OPTION_WARN_EXPAND: | |
1057 | target_warn_expand = 1; | |
1058 | break; | |
1059 | ||
1060 | #ifdef OBJ_ELF | |
1061 | /* SVR4 argument compatibility (-V): print version ID. */ | |
1062 | case 'V': | |
1063 | print_version_id (); | |
1064 | break; | |
1065 | ||
1066 | /* SVR4 argument compatibility (-Qy, -Qn): controls whether | |
1067 | a .comment section should be emitted or not (ignored). */ | |
1068 | case 'Q': | |
1069 | break; | |
1070 | #endif | |
1071 | ||
1072 | default: | |
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | return 1; | |
252b5132 RH |
1077 | } |
1078 | ||
1079 | void | |
1080 | md_show_usage (stream) | |
1081 | FILE *stream; | |
1082 | { | |
305d537e JE |
1083 | fprintf (stream, _("\ |
1084 | -EL generate code for little endian mode (default)\n\ | |
1085 | -EB generate code for big endian mode\n\ | |
1086 | -mwarn-expand warn if pseudo operations are expanded\n")); | |
1087 | #ifdef OBJ_ELF | |
1088 | /* SVR4 compatibility flags. */ | |
1089 | fprintf (stream, _("\ | |
1090 | -V print assembler version number\n\ | |
1091 | -Qy, -Qn ignored\n")); | |
1092 | #endif | |
252b5132 | 1093 | } |
305d537e | 1094 | |
252b5132 | 1095 | \f |
305d537e JE |
1096 | /* We have no need to default values of symbols. */ |
1097 | symbolS * | |
1098 | md_undefined_symbol (name) | |
1099 | char *name ATTRIBUTE_UNUSED; | |
1100 | { | |
1101 | return 0; | |
1102 | } | |
1103 | ||
305d537e | 1104 | /* The i860 denotes auto-increment with '++'. */ |
252b5132 | 1105 | void |
305d537e JE |
1106 | md_operand (exp) |
1107 | expressionS *exp; | |
252b5132 | 1108 | { |
305d537e | 1109 | char *s; |
252b5132 | 1110 | |
f869cfc6 | 1111 | for (s = input_line_pointer; *s; s++) |
252b5132 | 1112 | { |
305d537e | 1113 | if (s[0] == '+' && s[1] == '+') |
252b5132 | 1114 | { |
305d537e JE |
1115 | input_line_pointer += 2; |
1116 | exp->X_op = O_register; | |
1117 | break; | |
252b5132 | 1118 | } |
305d537e JE |
1119 | } |
1120 | } | |
1121 | ||
305d537e JE |
1122 | /* Round up a section size to the appropriate boundary. */ |
1123 | valueT | |
1124 | md_section_align (segment, size) | |
1125 | segT segment ATTRIBUTE_UNUSED; | |
1126 | valueT size ATTRIBUTE_UNUSED; | |
1127 | { | |
1128 | /* Byte alignment is fine. */ | |
1129 | return size; | |
1130 | } | |
1131 | ||
305d537e JE |
1132 | /* On the i860, a PC-relative offset is relative to the address of the |
1133 | of the offset plus its size. */ | |
1134 | long | |
1135 | md_pcrel_from (fixP) | |
1136 | fixS *fixP; | |
1137 | { | |
1138 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
1139 | } | |
252b5132 | 1140 | |
305d537e JE |
1141 | /* Determine the relocation needed for non PC-relative 16-bit immediates. |
1142 | Also adjust the given immediate as necessary. Finally, check that | |
1143 | all constraints (such as alignment) are satisfied. */ | |
1144 | static bfd_reloc_code_real_type | |
1145 | obtain_reloc_for_imm16 (fix, val) | |
1146 | fixS *fix; | |
1147 | long *val; | |
1148 | { | |
1149 | valueT fup = fix->fx_addnumber; | |
4a4f25cf | 1150 | bfd_reloc_code_real_type reloc; |
305d537e JE |
1151 | |
1152 | if (fix->fx_pcrel) | |
1153 | abort (); | |
1154 | ||
1155 | /* Check alignment restrictions. */ | |
1156 | if ((fup & OP_ALIGN2) && (*val & 0x1)) | |
1157 | as_bad_where (fix->fx_file, fix->fx_line, | |
1158 | _("This immediate requires 0 MOD 2 alignment")); | |
1159 | else if ((fup & OP_ALIGN4) && (*val & 0x3)) | |
1160 | as_bad_where (fix->fx_file, fix->fx_line, | |
1161 | _("This immediate requires 0 MOD 4 alignment")); | |
1162 | else if ((fup & OP_ALIGN8) && (*val & 0x7)) | |
1163 | as_bad_where (fix->fx_file, fix->fx_line, | |
1164 | _("This immediate requires 0 MOD 8 alignment")); | |
1165 | else if ((fup & OP_ALIGN16) && (*val & 0xf)) | |
1166 | as_bad_where (fix->fx_file, fix->fx_line, | |
1167 | _("This immediate requires 0 MOD 16 alignment")); | |
1168 | ||
1169 | if (fup & OP_SEL_HA) | |
1170 | { | |
1171 | *val = (*val >> 16) + (*val & 0x8000 ? 1 : 0); | |
1172 | reloc = BFD_RELOC_860_HIGHADJ; | |
1173 | } | |
1174 | else if (fup & OP_SEL_H) | |
1175 | { | |
1176 | *val >>= 16; | |
1177 | reloc = BFD_RELOC_860_HIGH; | |
1178 | } | |
1179 | else if (fup & OP_SEL_L) | |
1180 | { | |
1181 | int num_encode; | |
1182 | if (fup & OP_IMM_SPLIT16) | |
252b5132 | 1183 | { |
305d537e | 1184 | if (fup & OP_ENCODE1) |
252b5132 | 1185 | { |
305d537e JE |
1186 | num_encode = 1; |
1187 | reloc = BFD_RELOC_860_SPLIT1; | |
1188 | } | |
1189 | else if (fup & OP_ENCODE2) | |
1190 | { | |
1191 | num_encode = 2; | |
1192 | reloc = BFD_RELOC_860_SPLIT2; | |
252b5132 RH |
1193 | } |
1194 | else | |
1195 | { | |
305d537e JE |
1196 | num_encode = 0; |
1197 | reloc = BFD_RELOC_860_SPLIT0; | |
252b5132 | 1198 | } |
305d537e JE |
1199 | } |
1200 | else | |
1201 | { | |
1202 | if (fup & OP_ENCODE1) | |
252b5132 | 1203 | { |
305d537e JE |
1204 | num_encode = 1; |
1205 | reloc = BFD_RELOC_860_LOW1; | |
252b5132 | 1206 | } |
305d537e | 1207 | else if (fup & OP_ENCODE2) |
252b5132 | 1208 | { |
305d537e JE |
1209 | num_encode = 2; |
1210 | reloc = BFD_RELOC_860_LOW2; | |
1211 | } | |
1212 | else if (fup & OP_ENCODE3) | |
1213 | { | |
1214 | num_encode = 3; | |
1215 | reloc = BFD_RELOC_860_LOW3; | |
252b5132 RH |
1216 | } |
1217 | else | |
1218 | { | |
305d537e JE |
1219 | num_encode = 0; |
1220 | reloc = BFD_RELOC_860_LOW0; | |
252b5132 | 1221 | } |
252b5132 | 1222 | } |
305d537e JE |
1223 | |
1224 | /* Preserve size encode bits. */ | |
1225 | *val &= ~((1 << num_encode) - 1); | |
252b5132 | 1226 | } |
305d537e JE |
1227 | else |
1228 | { | |
1229 | /* No selector. What reloc do we generate (???)? */ | |
1230 | reloc = BFD_RELOC_32; | |
1231 | } | |
1232 | ||
1233 | return reloc; | |
252b5132 RH |
1234 | } |
1235 | ||
305d537e JE |
1236 | /* Attempt to simplify or eliminate a fixup. To indicate that a fixup |
1237 | has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL, | |
1238 | we will have to generate a reloc entry. */ | |
94f592af NC |
1239 | |
1240 | void | |
1241 | md_apply_fix3 (fix, valP, seg) | |
1242 | fixS * fix; | |
1243 | valueT * valP; | |
305d537e JE |
1244 | segT seg ATTRIBUTE_UNUSED; |
1245 | { | |
305d537e | 1246 | char *buf; |
a161fe53 | 1247 | long val = *valP; |
305d537e JE |
1248 | unsigned long insn; |
1249 | valueT fup; | |
252b5132 | 1250 | |
305d537e | 1251 | buf = fix->fx_frag->fr_literal + fix->fx_where; |
252b5132 | 1252 | |
305d537e JE |
1253 | /* Recall that earlier we stored the opcode little-endian. */ |
1254 | insn = bfd_getl32 (buf); | |
252b5132 | 1255 | |
305d537e JE |
1256 | /* We stored a fix-up in this oddly-named scratch field. */ |
1257 | fup = fix->fx_addnumber; | |
1258 | ||
1259 | /* Determine the necessary relocations as well as inserting an | |
1260 | immediate into the instruction. */ | |
673a54e3 | 1261 | if (fup & OP_IMM_U5) |
252b5132 | 1262 | { |
305d537e JE |
1263 | if (val & ~0x1f) |
1264 | as_bad_where (fix->fx_file, fix->fx_line, | |
1265 | _("5-bit immediate too large")); | |
1266 | if (fix->fx_addsy) | |
1267 | as_bad_where (fix->fx_file, fix->fx_line, | |
1268 | _("5-bit field must be absolute")); | |
1269 | ||
1270 | insn |= (val & 0x1f) << 11; | |
1271 | bfd_putl32 (insn, buf); | |
1272 | fix->fx_r_type = BFD_RELOC_NONE; | |
1273 | fix->fx_done = 1; | |
252b5132 | 1274 | } |
305d537e | 1275 | else if (fup & OP_IMM_S16) |
252b5132 | 1276 | { |
305d537e | 1277 | fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val); |
252b5132 | 1278 | |
305d537e | 1279 | /* Insert the immediate. */ |
ded0649c JE |
1280 | if (fix->fx_addsy) |
1281 | fix->fx_done = 0; | |
1282 | else | |
1283 | { | |
1284 | insn |= val & 0xffff; | |
1285 | bfd_putl32 (insn, buf); | |
1286 | fix->fx_r_type = BFD_RELOC_NONE; | |
1287 | fix->fx_done = 1; | |
1288 | } | |
305d537e JE |
1289 | } |
1290 | else if (fup & OP_IMM_U16) | |
94f592af NC |
1291 | abort (); |
1292 | ||
305d537e JE |
1293 | else if (fup & OP_IMM_SPLIT16) |
1294 | { | |
1295 | fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val); | |
1296 | ||
1297 | /* Insert the immediate. */ | |
ded0649c JE |
1298 | if (fix->fx_addsy) |
1299 | fix->fx_done = 0; | |
1300 | else | |
1301 | { | |
1302 | insn |= val & 0x7ff; | |
1303 | insn |= (val & 0xf800) << 5; | |
1304 | bfd_putl32 (insn, buf); | |
1305 | fix->fx_r_type = BFD_RELOC_NONE; | |
1306 | fix->fx_done = 1; | |
1307 | } | |
4a4f25cf | 1308 | } |
305d537e | 1309 | else if (fup & OP_IMM_BR16) |
252b5132 | 1310 | { |
305d537e JE |
1311 | if (val & 0x3) |
1312 | as_bad_where (fix->fx_file, fix->fx_line, | |
1313 | _("A branch offset requires 0 MOD 4 alignment")); | |
1314 | ||
1315 | val = val >> 2; | |
1316 | ||
1317 | /* Insert the immediate. */ | |
ded0649c JE |
1318 | if (fix->fx_addsy) |
1319 | { | |
1320 | fix->fx_done = 0; | |
1321 | fix->fx_r_type = BFD_RELOC_860_PC16; | |
1322 | } | |
1323 | else | |
1324 | { | |
1325 | insn |= (val & 0x7ff); | |
1326 | insn |= ((val & 0xf800) << 5); | |
1327 | bfd_putl32 (insn, buf); | |
1328 | fix->fx_r_type = BFD_RELOC_NONE; | |
1329 | fix->fx_done = 1; | |
1330 | } | |
252b5132 | 1331 | } |
305d537e | 1332 | else if (fup & OP_IMM_BR26) |
252b5132 | 1333 | { |
305d537e JE |
1334 | if (val & 0x3) |
1335 | as_bad_where (fix->fx_file, fix->fx_line, | |
1336 | _("A branch offset requires 0 MOD 4 alignment")); | |
252b5132 | 1337 | |
305d537e | 1338 | val >>= 2; |
252b5132 | 1339 | |
305d537e | 1340 | /* Insert the immediate. */ |
ded0649c JE |
1341 | if (fix->fx_addsy) |
1342 | { | |
1343 | fix->fx_r_type = BFD_RELOC_860_PC26; | |
1344 | fix->fx_done = 0; | |
1345 | } | |
1346 | else | |
1347 | { | |
1348 | insn |= (val & 0x3ffffff); | |
1349 | bfd_putl32 (insn, buf); | |
1350 | fix->fx_r_type = BFD_RELOC_NONE; | |
1351 | fix->fx_done = 1; | |
1352 | } | |
305d537e JE |
1353 | } |
1354 | else if (fup != OP_NONE) | |
1355 | { | |
4a4f25cf | 1356 | as_bad_where (fix->fx_file, fix->fx_line, |
d444b726 | 1357 | _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup); |
305d537e JE |
1358 | abort (); |
1359 | } | |
1360 | else | |
1361 | { | |
1362 | /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000" | |
1363 | reach here (???). */ | |
ded0649c JE |
1364 | if (fix->fx_addsy) |
1365 | { | |
1366 | fix->fx_r_type = BFD_RELOC_32; | |
1367 | fix->fx_done = 0; | |
1368 | } | |
1369 | else | |
1370 | { | |
1371 | insn |= (val & 0xffffffff); | |
1372 | bfd_putl32 (insn, buf); | |
1373 | fix->fx_r_type = BFD_RELOC_NONE; | |
1374 | fix->fx_done = 1; | |
1375 | } | |
305d537e | 1376 | } |
252b5132 RH |
1377 | } |
1378 | ||
305d537e JE |
1379 | /* Generate a machine dependent reloc from a fixup. */ |
1380 | arelent* | |
1381 | tc_gen_reloc (section, fixp) | |
1382 | asection *section ATTRIBUTE_UNUSED; | |
1383 | fixS *fixp; | |
252b5132 | 1384 | { |
305d537e | 1385 | arelent *reloc; |
252b5132 | 1386 | |
305d537e JE |
1387 | reloc = xmalloc (sizeof (*reloc)); |
1388 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
1389 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
1390 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1391 | reloc->addend = fixp->fx_offset; | |
1392 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
252b5132 | 1393 | |
305d537e | 1394 | if (! reloc->howto) |
252b5132 | 1395 | { |
305d537e JE |
1396 | as_bad_where (fixp->fx_file, fixp->fx_line, |
1397 | "Cannot represent %s relocation in object file", | |
1398 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
252b5132 | 1399 | } |
305d537e | 1400 | return reloc; |
252b5132 | 1401 | } |