Commit | Line | Data |
---|---|---|
542e1629 RP |
1 | /* tc-i960.c - All the i80960-specific stuff |
2 | Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc. | |
a39116f1 RP |
3 | |
4 | This file is part of GAS. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
fecd2382 | 19 | |
fecd2382 RP |
20 | /* See comment on md_parse_option for 80960-specific invocation options. */ |
21 | ||
22 | /****************************************************************************** | |
23 | * i80690 NOTE!!!: | |
24 | * Header, symbol, and relocation info will be used on the host machine | |
25 | * only -- only executable code is actually downloaded to the i80960. | |
26 | * Therefore, leave all such information in host byte order. | |
27 | * | |
28 | * (That's a slight lie -- we DO download some header information, but | |
29 | * the downloader converts the file format and corrects the byte-ordering | |
30 | * of the relevant fields while doing so.) | |
31 | * | |
32 | ***************************************************************************** */ | |
33 | ||
34 | /* There are 4 different lengths of (potentially) symbol-based displacements | |
35 | * in the 80960 instruction set, each of which could require address fix-ups | |
36 | * and (in the case of external symbols) emission of relocation directives: | |
37 | * | |
38 | * 32-bit (MEMB) | |
39 | * This is a standard length for the base assembler and requires no | |
40 | * special action. | |
41 | * | |
42 | * 13-bit (COBR) | |
43 | * This is a non-standard length, but the base assembler has a hook for | |
44 | * bit field address fixups: the fixS structure can point to a descriptor | |
45 | * of the field, in which case our md_number_to_field() routine gets called | |
46 | * to process it. | |
47 | * | |
48 | * I made the hook a little cleaner by having fix_new() (in the base | |
49 | * assembler) return a pointer to the fixS in question. And I made it a | |
50 | * little simpler by storing the field size (in this case 13) instead of | |
51 | * of a pointer to another structure: 80960 displacements are ALWAYS | |
52 | * stored in the low-order bits of a 4-byte word. | |
53 | * | |
54 | * Since the target of a COBR cannot be external, no relocation directives | |
55 | * for this size displacement have to be generated. But the base assembler | |
56 | * had to be modified to issue error messages if the symbol did turn out | |
57 | * to be external. | |
58 | * | |
59 | * 24-bit (CTRL) | |
60 | * Fixups are handled as for the 13-bit case (except that 24 is stored | |
61 | * in the fixS). | |
62 | * | |
63 | * The relocation directive generated is the same as that for the 32-bit | |
64 | * displacement, except that it's PC-relative (the 32-bit displacement | |
65 | * never is). The i80960 version of the linker needs a mod to | |
66 | * distinguish and handle the 24-bit case. | |
67 | * | |
68 | * 12-bit (MEMA) | |
69 | * MEMA formats are always promoted to MEMB (32-bit) if the displacement | |
70 | * is based on a symbol, because it could be relocated at link time. | |
71 | * The only time we use the 12-bit format is if an absolute value of | |
72 | * less than 4096 is specified, in which case we need neither a fixup nor | |
73 | * a relocation directive. | |
74 | */ | |
75 | ||
76 | #include <stdio.h> | |
77 | #include <ctype.h> | |
78 | ||
79 | #include "as.h" | |
80 | ||
81 | #include "obstack.h" | |
82 | ||
a39116f1 | 83 | #include "opcode/i960.h" |
fecd2382 RP |
84 | |
85 | extern char *input_line_pointer; | |
86 | extern struct hash_control *po_hash; | |
fecd2382 RP |
87 | extern char *next_object_file_charP; |
88 | ||
89 | #ifdef OBJ_COFF | |
90 | int md_reloc_size = sizeof(struct reloc); | |
91 | #else /* OBJ_COFF */ | |
92 | int md_reloc_size = sizeof(struct relocation_info); | |
93 | #endif /* OBJ_COFF */ | |
94 | ||
a39116f1 RP |
95 | /*************************** |
96 | * Local i80960 routines * | |
97 | ************************** */ | |
fecd2382 RP |
98 | |
99 | static void brcnt_emit(); /* Emit branch-prediction instrumentation code */ | |
100 | static char * brlab_next(); /* Return next branch local label */ | |
a39116f1 | 101 | void brtab_emit(); /* Emit br-predict instrumentation table */ |
fecd2382 RP |
102 | static void cobr_fmt(); /* Generate COBR instruction */ |
103 | static void ctrl_fmt(); /* Generate CTRL instruction */ | |
104 | static char * emit(); /* Emit (internally) binary */ | |
105 | static int get_args(); /* Break arguments out of comma-separated list */ | |
106 | static void get_cdisp(); /* Handle COBR or CTRL displacement */ | |
107 | static char * get_ispec(); /* Find index specification string */ | |
108 | static int get_regnum(); /* Translate text to register number */ | |
109 | static int i_scan(); /* Lexical scan of instruction source */ | |
110 | static void mem_fmt(); /* Generate MEMA or MEMB instruction */ | |
111 | static void mema_to_memb(); /* Convert MEMA instruction to MEMB format */ | |
112 | static segT parse_expr(); /* Parse an expression */ | |
113 | static int parse_ldconst();/* Parse and replace a 'ldconst' pseudo-op */ | |
114 | static void parse_memop(); /* Parse a memory operand */ | |
115 | static void parse_po(); /* Parse machine-dependent pseudo-op */ | |
116 | static void parse_regop(); /* Parse a register operand */ | |
117 | static void reg_fmt(); /* Generate a REG format instruction */ | |
a39116f1 | 118 | void reloc_callj(); /* Relocate a 'callj' instruction */ |
fecd2382 RP |
119 | static void relax_cobr(); /* "De-optimize" cobr into compare/branch */ |
120 | static void s_leafproc(); /* Process '.leafproc' pseudo-op */ | |
121 | static void s_sysproc(); /* Process '.sysproc' pseudo-op */ | |
122 | static int shift_ok(); /* Will a 'shlo' substiture for a 'ldconst'? */ | |
123 | static void syntax(); /* Give syntax error */ | |
124 | static int targ_has_sfr(); /* Target chip supports spec-func register? */ | |
125 | static int targ_has_iclass();/* Target chip supports instruction set? */ | |
126 | /* static void unlink_sym(); */ /* Remove a symbol from the symbol list */ | |
127 | ||
128 | /* See md_parse_option() for meanings of these options */ | |
09952cd9 KR |
129 | static char norelax; /* True if -norelax switch seen */ |
130 | static char instrument_branches; /* True if -b switch seen */ | |
fecd2382 RP |
131 | |
132 | /* Characters that always start a comment. | |
133 | * If the pre-processor is disabled, these aren't very useful. | |
134 | */ | |
135 | char comment_chars[] = "#"; | |
136 | ||
137 | /* Characters that only start a comment at the beginning of | |
138 | * a line. If the line seems to have the form '# 123 filename' | |
139 | * .line and .file directives will appear in the pre-processed output. | |
140 | * | |
141 | * Note that input_file.c hand checks for '#' at the beginning of the | |
142 | * first line of the input file. This is because the compiler outputs | |
143 | * #NO_APP at the beginning of its output. | |
144 | */ | |
145 | ||
146 | /* Also note that comments started like this one will always work. */ | |
147 | ||
148 | char line_comment_chars[] = ""; | |
149 | ||
150 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
151 | char EXP_CHARS[] = "eE"; | |
152 | ||
153 | /* Chars that mean this number is a floating point constant, | |
154 | * as in 0f12.456 or 0d1.2345e12 | |
155 | */ | |
156 | char FLT_CHARS[] = "fFdDtT"; | |
157 | ||
158 | ||
159 | /* Table used by base assembler to relax addresses based on varying length | |
160 | * instructions. The fields are: | |
161 | * 1) most positive reach of this state, | |
162 | * 2) most negative reach of this state, | |
163 | * 3) how many bytes this mode will add to the size of the current frag | |
164 | * 4) which index into the table to try if we can't fit into this one. | |
165 | * | |
166 | * For i80960, the only application is the (de-)optimization of cobr | |
167 | * instructions into separate compare and branch instructions when a 13-bit | |
168 | * displacement won't hack it. | |
169 | */ | |
170 | const relax_typeS | |
a39116f1 RP |
171 | md_relax_table[] = { |
172 | {0, 0, 0,0}, /* State 0 => no more relaxation possible */ | |
173 | {4088, -4096, 0,2}, /* State 1: conditional branch (cobr) */ | |
174 | {0x800000-8,-0x800000,4,0}, /* State 2: compare (reg) & branch (ctrl) */ | |
175 | }; | |
fecd2382 RP |
176 | |
177 | ||
178 | /* These are the machine dependent pseudo-ops. | |
179 | * | |
180 | * This table describes all the machine specific pseudo-ops the assembler | |
181 | * has to support. The fields are: | |
182 | * pseudo-op name without dot | |
183 | * function to call to execute this pseudo-op | |
184 | * integer arg to pass to the function | |
185 | */ | |
186 | #define S_LEAFPROC 1 | |
187 | #define S_SYSPROC 2 | |
188 | ||
09952cd9 KR |
189 | const pseudo_typeS md_pseudo_table[] = { |
190 | { "bss", s_lcomm, 1 }, | |
191 | { "extended", float_cons, 't' }, | |
192 | { "leafproc", parse_po, S_LEAFPROC }, | |
193 | { "sysproc", parse_po, S_SYSPROC }, | |
194 | ||
195 | { "word", cons, 4 }, | |
196 | { "quad", big_cons, 16 }, | |
197 | ||
198 | { 0, 0, 0 } | |
199 | }; | |
fecd2382 RP |
200 | \f |
201 | /* Macros to extract info from an 'expressionS' structure 'e' */ | |
202 | #define adds(e) e.X_add_symbol | |
203 | #define subs(e) e.X_subtract_symbol | |
204 | #define offs(e) e.X_add_number | |
205 | #define segs(e) e.X_seg | |
a39116f1 RP |
206 | |
207 | ||
208 | /* Branch-prediction bits for CTRL/COBR format opcodes */ | |
fecd2382 RP |
209 | #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */ |
210 | #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */ | |
211 | #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */ | |
a39116f1 RP |
212 | |
213 | ||
214 | /* Some instruction opcodes that we need explicitly */ | |
fecd2382 RP |
215 | #define BE 0x12000000 |
216 | #define BG 0x11000000 | |
217 | #define BGE 0x13000000 | |
218 | #define BL 0x14000000 | |
219 | #define BLE 0x16000000 | |
220 | #define BNE 0x15000000 | |
221 | #define BNO 0x10000000 | |
222 | #define BO 0x17000000 | |
223 | #define CHKBIT 0x5a002700 | |
224 | #define CMPI 0x5a002080 | |
225 | #define CMPO 0x5a002000 | |
a39116f1 | 226 | |
fecd2382 RP |
227 | #define B 0x08000000 |
228 | #define BAL 0x0b000000 | |
229 | #define CALL 0x09000000 | |
230 | #define CALLS 0x66003800 | |
231 | #define RET 0x0a000000 | |
a39116f1 RP |
232 | |
233 | ||
234 | /* These masks are used to build up a set of MEMB mode bits. */ | |
fecd2382 RP |
235 | #define A_BIT 0x0400 |
236 | #define I_BIT 0x0800 | |
237 | #define MEMB_BIT 0x1000 | |
238 | #define D_BIT 0x2000 | |
a39116f1 RP |
239 | |
240 | ||
241 | /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is used) */ | |
fecd2382 | 242 | #define MEMA_ABASE 0x2000 |
a39116f1 RP |
243 | |
244 | /* Info from which a MEMA or MEMB format instruction can be generated */ | |
245 | typedef struct { | |
246 | long opcode; /* (First) 32 bits of instruction */ | |
247 | int disp; /* 0-(none), 12- or, 32-bit displacement needed */ | |
248 | char *e; /* The expression in the source instruction from | |
fecd2382 RP |
249 | * which the displacement should be determined |
250 | */ | |
a39116f1 | 251 | } memS; |
fecd2382 RP |
252 | |
253 | ||
254 | /* The two pieces of info we need to generate a register operand */ | |
255 | struct regop { | |
256 | int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */ | |
257 | int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */ | |
258 | int n; /* Register number or literal value */ | |
259 | }; | |
260 | ||
261 | ||
262 | /* Number and assembler mnemonic for all registers that can appear in operands */ | |
263 | static struct { | |
264 | char *reg_name; | |
265 | int reg_num; | |
266 | } regnames[] = { | |
267 | { "pfp", 0 }, { "sp", 1 }, { "rip", 2 }, { "r3", 3 }, | |
268 | { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 }, | |
269 | { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 }, | |
270 | { "r12", 12 }, { "r13", 13 }, { "r14", 14 }, { "r15", 15 }, | |
271 | { "g0", 16 }, { "g1", 17 }, { "g2", 18 }, { "g3", 19 }, | |
272 | { "g4", 20 }, { "g5", 21 }, { "g6", 22 }, { "g7", 23 }, | |
273 | { "g8", 24 }, { "g9", 25 }, { "g10", 26 }, { "g11", 27 }, | |
274 | { "g12", 28 }, { "g13", 29 }, { "g14", 30 }, { "fp", 31 }, | |
a39116f1 | 275 | |
fecd2382 RP |
276 | /* Numbers for special-function registers are for assembler internal |
277 | * use only: they are scaled back to range [0-31] for binary output. | |
278 | */ | |
279 | # define SF0 32 | |
a39116f1 | 280 | |
fecd2382 RP |
281 | { "sf0", 32 }, { "sf1", 33 }, { "sf2", 34 }, { "sf3", 35 }, |
282 | { "sf4", 36 }, { "sf5", 37 }, { "sf6", 38 }, { "sf7", 39 }, | |
283 | { "sf8", 40 }, { "sf9", 41 }, { "sf10",42 }, { "sf11",43 }, | |
284 | { "sf12",44 }, { "sf13",45 }, { "sf14",46 }, { "sf15",47 }, | |
285 | { "sf16",48 }, { "sf17",49 }, { "sf18",50 }, { "sf19",51 }, | |
286 | { "sf20",52 }, { "sf21",53 }, { "sf22",54 }, { "sf23",55 }, | |
287 | { "sf24",56 }, { "sf25",57 }, { "sf26",58 }, { "sf27",59 }, | |
288 | { "sf28",60 }, { "sf29",61 }, { "sf30",62 }, { "sf31",63 }, | |
a39116f1 | 289 | |
fecd2382 RP |
290 | /* Numbers for floating point registers are for assembler internal use |
291 | * only: they are scaled back to [0-3] for binary output. | |
292 | */ | |
293 | # define FP0 64 | |
a39116f1 | 294 | |
fecd2382 | 295 | { "fp0", 64 }, { "fp1", 65 }, { "fp2", 66 }, { "fp3", 67 }, |
a39116f1 | 296 | |
fecd2382 RP |
297 | { NULL, 0 }, /* END OF LIST */ |
298 | }; | |
299 | ||
300 | #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0)) | |
301 | #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0)) | |
302 | #define IS_FP_REG(n) ((n) >= FP0) | |
303 | ||
304 | /* Number and assembler mnemonic for all registers that can appear as 'abase' | |
305 | * (indirect addressing) registers. | |
306 | */ | |
307 | static struct { | |
308 | char *areg_name; | |
309 | int areg_num; | |
310 | } aregs[] = { | |
311 | { "(pfp)", 0 }, { "(sp)", 1 }, { "(rip)", 2 }, { "(r3)", 3 }, | |
312 | { "(r4)", 4 }, { "(r5)", 5 }, { "(r6)", 6 }, { "(r7)", 7 }, | |
313 | { "(r8)", 8 }, { "(r9)", 9 }, { "(r10)", 10 }, { "(r11)", 11 }, | |
314 | { "(r12)", 12 }, { "(r13)", 13 }, { "(r14)", 14 }, { "(r15)", 15 }, | |
315 | { "(g0)", 16 }, { "(g1)", 17 }, { "(g2)", 18 }, { "(g3)", 19 }, | |
316 | { "(g4)", 20 }, { "(g5)", 21 }, { "(g6)", 22 }, { "(g7)", 23 }, | |
317 | { "(g8)", 24 }, { "(g9)", 25 }, { "(g10)", 26 }, { "(g11)", 27 }, | |
318 | { "(g12)", 28 }, { "(g13)", 29 }, { "(g14)", 30 }, { "(fp)", 31 }, | |
a39116f1 | 319 | |
fecd2382 RP |
320 | # define IPREL 32 |
321 | /* for assembler internal use only: this number never appears in binary | |
322 | * output. | |
323 | */ | |
324 | { "(ip)", IPREL }, | |
a39116f1 | 325 | |
fecd2382 RP |
326 | { NULL, 0 }, /* END OF LIST */ |
327 | }; | |
328 | ||
329 | ||
330 | /* Hash tables */ | |
331 | static struct hash_control *op_hash = NULL; /* Opcode mnemonics */ | |
332 | static struct hash_control *reg_hash = NULL; /* Register name hash table */ | |
333 | static struct hash_control *areg_hash = NULL; /* Abase register hash table */ | |
334 | ||
335 | ||
336 | /* Architecture for which we are assembling */ | |
337 | #define ARCH_ANY 0 /* Default: no architecture checking done */ | |
338 | #define ARCH_KA 1 | |
339 | #define ARCH_KB 2 | |
340 | #define ARCH_MC 3 | |
341 | #define ARCH_CA 4 | |
342 | int architecture = ARCH_ANY; /* Architecture requested on invocation line */ | |
343 | int iclasses_seen = 0; /* OR of instruction classes (I_* constants) | |
344 | * for which we've actually assembled | |
345 | * instructions. | |
346 | */ | |
347 | ||
348 | ||
349 | /* BRANCH-PREDICTION INSTRUMENTATION | |
350 | * | |
351 | * The following supports generation of branch-prediction instrumentation | |
352 | * (turned on by -b switch). The instrumentation collects counts | |
353 | * of branches taken/not-taken for later input to a utility that will | |
354 | * set the branch prediction bits of the instructions in accordance with | |
355 | * the behavior observed. (Note that the KX series does not have | |
356 | * brach-prediction.) | |
357 | * | |
358 | * The instrumentation consists of: | |
359 | * | |
360 | * (1) before and after each conditional branch, a call to an external | |
361 | * routine that increments and steps over an inline counter. The | |
362 | * counter itself, initialized to 0, immediately follows the call | |
363 | * instruction. For each branch, the counter following the branch | |
364 | * is the number of times the branch was not taken, and the difference | |
365 | * between the counters is the number of times it was taken. An | |
366 | * example of an instrumented conditional branch: | |
367 | * | |
368 | * call BR_CNT_FUNC | |
369 | * .word 0 | |
370 | * LBRANCH23: be label | |
371 | * call BR_CNT_FUNC | |
372 | * .word 0 | |
373 | * | |
374 | * (2) a table of pointers to the instrumented branches, so that an | |
375 | * external postprocessing routine can locate all of the counters. | |
376 | * the table begins with a 2-word header: a pointer to the next in | |
377 | * a linked list of such tables (initialized to 0); and a count | |
378 | * of the number of entries in the table (exclusive of the header. | |
379 | * | |
380 | * Note that input source code is expected to already contain calls | |
381 | * an external routine that will link the branch local table into a | |
382 | * list of such tables. | |
383 | */ | |
384 | ||
385 | static int br_cnt = 0; /* Number of branches instrumented so far. | |
386 | * Also used to generate unique local labels | |
387 | * for each instrumented branch | |
388 | */ | |
389 | ||
390 | #define BR_LABEL_BASE "LBRANCH" | |
a39116f1 RP |
391 | /* Basename of local labels on instrumented |
392 | * branches, to avoid conflict with compiler- | |
393 | * generated local labels. | |
394 | */ | |
fecd2382 RP |
395 | |
396 | #define BR_CNT_FUNC "__inc_branch" | |
a39116f1 RP |
397 | /* Name of the external routine that will |
398 | * increment (and step over) an inline counter. | |
399 | */ | |
fecd2382 RP |
400 | |
401 | #define BR_TAB_NAME "__BRANCH_TABLE__" | |
a39116f1 RP |
402 | /* Name of the table of pointers to branches. |
403 | * A local (i.e., non-external) symbol. | |
404 | */ | |
fecd2382 RP |
405 | \f |
406 | /***************************************************************************** | |
407 | * md_begin: One-time initialization. | |
408 | * | |
409 | * Set up hash tables. | |
410 | * | |
411 | **************************************************************************** */ | |
412 | void | |
a39116f1 | 413 | md_begin() |
fecd2382 RP |
414 | { |
415 | int i; /* Loop counter */ | |
416 | const struct i960_opcode *oP; /* Pointer into opcode table */ | |
417 | char *retval; /* Value returned by hash functions */ | |
a39116f1 | 418 | |
fecd2382 RP |
419 | if (((op_hash = hash_new()) == 0) |
420 | || ((reg_hash = hash_new()) == 0) | |
421 | || ((areg_hash = hash_new()) == 0)) { | |
422 | as_fatal("virtual memory exceeded"); | |
423 | } | |
a39116f1 | 424 | |
fecd2382 RP |
425 | retval = ""; /* For some reason, the base assembler uses an empty |
426 | * string for "no error message", instead of a NULL | |
427 | * pointer. | |
428 | */ | |
a39116f1 | 429 | |
fecd2382 RP |
430 | for (oP=i960_opcodes; oP->name && !*retval; oP++) { |
431 | retval = hash_insert(op_hash, oP->name, oP); | |
432 | } | |
a39116f1 | 433 | |
fecd2382 RP |
434 | for (i=0; regnames[i].reg_name && !*retval; i++) { |
435 | retval = hash_insert(reg_hash, regnames[i].reg_name, | |
436 | ®names[i].reg_num); | |
437 | } | |
a39116f1 | 438 | |
fecd2382 RP |
439 | for (i=0; aregs[i].areg_name && !*retval; i++){ |
440 | retval = hash_insert(areg_hash, aregs[i].areg_name, | |
441 | &aregs[i].areg_num); | |
442 | } | |
a39116f1 | 443 | |
fecd2382 RP |
444 | if (*retval) { |
445 | as_fatal("Hashing returned \"%s\".", retval); | |
446 | } | |
447 | } /* md_begin() */ | |
448 | ||
449 | /***************************************************************************** | |
450 | * md_end: One-time final cleanup | |
451 | * | |
452 | * None necessary | |
453 | * | |
454 | **************************************************************************** */ | |
455 | void | |
a39116f1 | 456 | md_end() |
fecd2382 RP |
457 | { |
458 | } | |
459 | ||
460 | /***************************************************************************** | |
461 | * md_assemble: Assemble an instruction | |
462 | * | |
463 | * Assumptions about the passed-in text: | |
464 | * - all comments, labels removed | |
465 | * - text is an instruction | |
466 | * - all white space compressed to single blanks | |
467 | * - all character constants have been replaced with decimal | |
468 | * | |
469 | **************************************************************************** */ | |
470 | void | |
a39116f1 RP |
471 | md_assemble(textP) |
472 | char *textP; /* Source text of instruction */ | |
fecd2382 RP |
473 | { |
474 | char *args[4]; /* Parsed instruction text, containing NO whitespace: | |
475 | * arg[0]->opcode mnemonic | |
476 | * arg[1-3]->operands, with char constants | |
477 | * replaced by decimal numbers | |
478 | */ | |
479 | int n_ops; /* Number of instruction operands */ | |
09952cd9 | 480 | int callx; |
fecd2382 | 481 | struct i960_opcode *oP; |
a39116f1 | 482 | /* Pointer to instruction description */ |
fecd2382 | 483 | int branch_predict; |
a39116f1 RP |
484 | /* TRUE iff opcode mnemonic included branch-prediction |
485 | * suffix (".f" or ".t") | |
486 | */ | |
fecd2382 RP |
487 | long bp_bits; /* Setting of branch-prediction bit(s) to be OR'd |
488 | * into instruction opcode of CTRL/COBR format | |
489 | * instructions. | |
490 | */ | |
491 | int n; /* Offset of last character in opcode mnemonic */ | |
a39116f1 | 492 | |
fecd2382 | 493 | static const char bp_error_msg[] = "branch prediction invalid on this opcode"; |
a39116f1 RP |
494 | |
495 | ||
fecd2382 | 496 | /* Parse instruction into opcode and operands */ |
542e1629 | 497 | memset(args, '\0', sizeof(args)); |
fecd2382 RP |
498 | n_ops = i_scan(textP, args); |
499 | if (n_ops == -1){ | |
500 | return; /* Error message already issued */ | |
501 | } | |
a39116f1 | 502 | |
fecd2382 RP |
503 | /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */ |
504 | if (!strcmp(args[0],"ldconst")){ | |
505 | n_ops = parse_ldconst(args); | |
506 | if (n_ops == -1){ | |
507 | return; | |
508 | } | |
509 | } | |
09952cd9 KR |
510 | |
511 | ||
a39116f1 | 512 | |
fecd2382 RP |
513 | /* Check for branch-prediction suffix on opcode mnemonic, strip it off */ |
514 | n = strlen(args[0]) - 1; | |
515 | branch_predict = 0; | |
516 | bp_bits = 0; | |
517 | if (args[0][n-1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')){ | |
518 | /* We could check here to see if the target architecture | |
519 | * supports branch prediction, but why bother? The bit | |
520 | * will just be ignored by processors that don't use it. | |
521 | */ | |
522 | branch_predict = 1; | |
523 | bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN; | |
524 | args[0][n-1] = '\0'; /* Strip suffix from opcode mnemonic */ | |
525 | } | |
a39116f1 | 526 | |
fecd2382 RP |
527 | /* Look up opcode mnemonic in table and check number of operands. |
528 | * Check that opcode is legal for the target architecture. | |
529 | * If all looks good, assemble instruction. | |
530 | */ | |
531 | oP = (struct i960_opcode *) hash_find(op_hash, args[0]); | |
532 | if (!oP || !targ_has_iclass(oP->iclass)) { | |
533 | as_bad("invalid opcode, \"%s\".", args[0]); | |
a39116f1 | 534 | |
fecd2382 RP |
535 | } else if (n_ops != oP->num_ops) { |
536 | as_bad("improper number of operands. expecting %d, got %d", oP->num_ops, n_ops); | |
a39116f1 | 537 | |
fecd2382 RP |
538 | } else { |
539 | switch (oP->format){ | |
540 | case FBRA: | |
541 | case CTRL: | |
542 | ctrl_fmt(args[1], oP->opcode | bp_bits, oP->num_ops); | |
543 | if (oP->format == FBRA){ | |
544 | /* Now generate a 'bno' to same arg */ | |
545 | ctrl_fmt(args[1], BNO | bp_bits, 1); | |
546 | } | |
547 | break; | |
548 | case COBR: | |
549 | case COJ: | |
550 | cobr_fmt(args, oP->opcode | bp_bits, oP); | |
551 | break; | |
552 | case REG: | |
553 | if (branch_predict){ | |
554 | as_warn(bp_error_msg); | |
555 | } | |
556 | reg_fmt(args, oP); | |
557 | break; | |
558 | case MEM1: | |
09952cd9 KR |
559 | if (args[0][0] == 'c' && args[0][1] == 'a') |
560 | { | |
561 | if (branch_predict) | |
562 | { | |
563 | as_warn(bp_error_msg); | |
564 | } | |
565 | mem_fmt(args, oP, 1); | |
566 | break; | |
567 | } | |
fecd2382 RP |
568 | case MEM2: |
569 | case MEM4: | |
570 | case MEM8: | |
571 | case MEM12: | |
572 | case MEM16: | |
573 | if (branch_predict){ | |
574 | as_warn(bp_error_msg); | |
575 | } | |
09952cd9 | 576 | mem_fmt(args, oP, 0); |
fecd2382 RP |
577 | break; |
578 | case CALLJ: | |
579 | if (branch_predict){ | |
580 | as_warn(bp_error_msg); | |
581 | } | |
582 | /* Output opcode & set up "fixup" (relocation); | |
583 | * flag relocation as 'callj' type. | |
584 | */ | |
585 | know(oP->num_ops == 1); | |
586 | get_cdisp(args[1], "CTRL", oP->opcode, 24, 0, 1); | |
587 | break; | |
588 | default: | |
589 | BAD_CASE(oP->format); | |
590 | break; | |
591 | } | |
592 | } | |
593 | } /* md_assemble() */ | |
594 | ||
595 | /***************************************************************************** | |
596 | * md_number_to_chars: convert a number to target byte order | |
597 | * | |
598 | **************************************************************************** */ | |
599 | void | |
a39116f1 RP |
600 | md_number_to_chars(buf, value, n) |
601 | char *buf; /* Put output here */ | |
602 | long value; /* The integer to be converted */ | |
603 | int n; /* Number of bytes to output (significant bytes | |
604 | * in 'value') | |
605 | */ | |
fecd2382 RP |
606 | { |
607 | while (n--){ | |
608 | *buf++ = value; | |
609 | value >>= 8; | |
610 | } | |
a39116f1 | 611 | |
fecd2382 RP |
612 | /* XXX line number probably botched for this warning message. */ |
613 | if (value != 0 && value != -1){ | |
614 | as_bad("Displacement too long for instruction field length."); | |
615 | } | |
a39116f1 | 616 | |
a79c6033 | 617 | return; |
fecd2382 RP |
618 | } /* md_number_to_chars() */ |
619 | ||
620 | /***************************************************************************** | |
621 | * md_chars_to_number: convert from target byte order to host byte order. | |
622 | * | |
623 | **************************************************************************** */ | |
624 | int | |
a39116f1 RP |
625 | md_chars_to_number(val, n) |
626 | unsigned char *val; /* Value in target byte order */ | |
627 | int n; /* Number of bytes in the input */ | |
fecd2382 RP |
628 | { |
629 | int retval; | |
a39116f1 | 630 | |
fecd2382 RP |
631 | for (retval=0; n--;){ |
632 | retval <<= 8; | |
633 | retval |= val[n]; | |
634 | } | |
635 | return retval; | |
636 | } | |
637 | ||
638 | ||
639 | #define MAX_LITTLENUMS 6 | |
640 | #define LNUM_SIZE sizeof(LITTLENUM_TYPE) | |
641 | ||
642 | /***************************************************************************** | |
643 | * md_atof: convert ascii to floating point | |
644 | * | |
645 | * Turn a string at input_line_pointer into a floating point constant of type | |
646 | * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS | |
647 | * emitted is returned at 'sizeP'. An error message is returned, or a pointer | |
648 | * to an empty message if OK. | |
649 | * | |
650 | * Note we call the i386 floating point routine, rather than complicating | |
651 | * things with more files or symbolic links. | |
652 | * | |
653 | **************************************************************************** */ | |
654 | char * md_atof(type, litP, sizeP) | |
655 | int type; | |
656 | char *litP; | |
657 | int *sizeP; | |
658 | { | |
659 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
660 | LITTLENUM_TYPE *wordP; | |
661 | int prec; | |
662 | char *t; | |
663 | char *atof_ieee(); | |
a39116f1 | 664 | |
fecd2382 RP |
665 | switch(type) { |
666 | case 'f': | |
667 | case 'F': | |
668 | prec = 2; | |
669 | break; | |
a39116f1 | 670 | |
fecd2382 RP |
671 | case 'd': |
672 | case 'D': | |
673 | prec = 4; | |
674 | break; | |
a39116f1 | 675 | |
fecd2382 RP |
676 | case 't': |
677 | case 'T': | |
678 | prec = 5; | |
679 | type = 'x'; /* That's what atof_ieee() understands */ | |
680 | break; | |
a39116f1 | 681 | |
fecd2382 RP |
682 | default: |
683 | *sizeP=0; | |
684 | return "Bad call to md_atof()"; | |
685 | } | |
a39116f1 | 686 | |
fecd2382 RP |
687 | t = atof_ieee(input_line_pointer, type, words); |
688 | if (t){ | |
689 | input_line_pointer = t; | |
690 | } | |
a39116f1 | 691 | |
fecd2382 | 692 | *sizeP = prec * LNUM_SIZE; |
a39116f1 | 693 | |
fecd2382 RP |
694 | /* Output the LITTLENUMs in REVERSE order in accord with i80960 |
695 | * word-order. (Dunno why atof_ieee doesn't do it in the right | |
696 | * order in the first place -- probably because it's a hack of | |
697 | * atof_m68k.) | |
698 | */ | |
a39116f1 | 699 | |
fecd2382 RP |
700 | for(wordP = words + prec - 1; prec--;){ |
701 | md_number_to_chars(litP, (long) (*wordP--), LNUM_SIZE); | |
702 | litP += sizeof(LITTLENUM_TYPE); | |
703 | } | |
a39116f1 | 704 | |
fecd2382 RP |
705 | return ""; /* Someone should teach Dean about null pointers */ |
706 | } | |
707 | ||
708 | ||
709 | /***************************************************************************** | |
710 | * md_number_to_imm | |
711 | * | |
712 | **************************************************************************** */ | |
713 | void | |
a39116f1 RP |
714 | md_number_to_imm(buf, val, n) |
715 | char *buf; | |
716 | long val; | |
717 | int n; | |
fecd2382 RP |
718 | { |
719 | md_number_to_chars(buf, val, n); | |
720 | } | |
721 | ||
722 | ||
723 | /***************************************************************************** | |
724 | * md_number_to_disp | |
725 | * | |
726 | **************************************************************************** */ | |
727 | void | |
a39116f1 RP |
728 | md_number_to_disp(buf, val, n) |
729 | char *buf; | |
730 | long val; | |
731 | int n; | |
fecd2382 RP |
732 | { |
733 | md_number_to_chars(buf, val, n); | |
734 | } | |
735 | ||
736 | /***************************************************************************** | |
737 | * md_number_to_field: | |
738 | * | |
739 | * Stick a value (an address fixup) into a bit field of | |
740 | * previously-generated instruction. | |
741 | * | |
742 | **************************************************************************** */ | |
743 | void | |
a39116f1 RP |
744 | md_number_to_field(instrP, val, bfixP) |
745 | char *instrP; /* Pointer to instruction to be fixed */ | |
746 | long val; /* Address fixup value */ | |
747 | bit_fixS *bfixP; /* Description of bit field to be fixed up */ | |
fecd2382 RP |
748 | { |
749 | int numbits; /* Length of bit field to be fixed */ | |
750 | long instr; /* 32-bit instruction to be fixed-up */ | |
751 | long sign; /* 0 or -1, according to sign bit of 'val' */ | |
a39116f1 | 752 | |
fecd2382 RP |
753 | /* Convert instruction back to host byte order |
754 | */ | |
755 | instr = md_chars_to_number(instrP, 4); | |
a39116f1 | 756 | |
fecd2382 RP |
757 | /* Surprise! -- we stored the number of bits |
758 | * to be modified rather than a pointer to a structure. | |
759 | */ | |
760 | numbits = (int)bfixP; | |
761 | if (numbits == 1){ | |
762 | /* This is a no-op, stuck here by reloc_callj() */ | |
763 | return; | |
764 | } | |
a39116f1 | 765 | |
fecd2382 | 766 | know ((numbits==13) || (numbits==24)); |
a39116f1 | 767 | |
fecd2382 RP |
768 | /* Propagate sign bit of 'val' for the given number of bits. |
769 | * Result should be all 0 or all 1 | |
770 | */ | |
771 | sign = val >> ((int)numbits - 1); | |
772 | if (((val < 0) && (sign != -1)) | |
a39116f1 RP |
773 | || ((val > 0) && (sign != 0))){ |
774 | as_bad("Fixup of %d too large for field width of %d", | |
775 | val, numbits); | |
fecd2382 RP |
776 | } else { |
777 | /* Put bit field into instruction and write back in target | |
778 | * byte order. | |
779 | */ | |
780 | val &= ~(-1 << (int)numbits); /* Clear unused sign bits */ | |
781 | instr |= val; | |
782 | md_number_to_chars(instrP, instr, 4); | |
783 | } | |
784 | } /* md_number_to_field() */ | |
785 | ||
786 | ||
787 | /***************************************************************************** | |
788 | * md_parse_option | |
789 | * Invocation line includes a switch not recognized by the base assembler. | |
790 | * See if it's a processor-specific option. For the 960, these are: | |
791 | * | |
792 | * -norelax: | |
793 | * Conditional branch instructions that require displacements | |
794 | * greater than 13 bits (or that have external targets) should | |
795 | * generate errors. The default is to replace each such | |
796 | * instruction with the corresponding compare (or chkbit) and | |
797 | * branch instructions. Note that the Intel "j" cobr directives | |
798 | * are ALWAYS "de-optimized" in this way when necessary, | |
799 | * regardless of the setting of this option. | |
800 | * | |
801 | * -b: | |
802 | * Add code to collect information about branches taken, for | |
803 | * later optimization of branch prediction bits by a separate | |
804 | * tool. COBR and CNTL format instructions have branch | |
805 | * prediction bits (in the CX architecture); if "BR" represents | |
806 | * an instruction in one of these classes, the following rep- | |
807 | * resents the code generated by the assembler: | |
808 | * | |
809 | * call <increment routine> | |
810 | * .word 0 # pre-counter | |
811 | * Label: BR | |
812 | * call <increment routine> | |
813 | * .word 0 # post-counter | |
814 | * | |
815 | * A table of all such "Labels" is also generated. | |
816 | * | |
817 | * | |
818 | * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA: | |
819 | * Select the 80960 architecture. Instructions or features not | |
820 | * supported by the selected architecture cause fatal errors. | |
821 | * The default is to generate code for any instruction or feature | |
822 | * that is supported by SOME version of the 960 (even if this | |
823 | * means mixing architectures!). | |
824 | * | |
825 | **************************************************************************** */ | |
826 | int | |
a39116f1 RP |
827 | md_parse_option(argP, cntP, vecP) |
828 | char **argP; | |
829 | int *cntP; | |
830 | char ***vecP; | |
fecd2382 RP |
831 | { |
832 | char *p; | |
833 | struct tabentry { char *flag; int arch; }; | |
834 | static struct tabentry arch_tab[] = { | |
835 | "KA", ARCH_KA, | |
836 | "KB", ARCH_KB, | |
837 | "SA", ARCH_KA, /* Synonym for KA */ | |
838 | "SB", ARCH_KB, /* Synonym for KB */ | |
839 | "KC", ARCH_MC, /* Synonym for MC */ | |
840 | "MC", ARCH_MC, | |
841 | "CA", ARCH_CA, | |
842 | NULL, 0 | |
a39116f1 | 843 | }; |
fecd2382 | 844 | struct tabentry *tp; |
09952cd9 KR |
845 | if (!strcmp(*argP,"linkrelax")){ |
846 | linkrelax = 1; | |
847 | flagseen ['L'] = 1; | |
848 | } else if (!strcmp(*argP,"norelax")){ | |
fecd2382 | 849 | norelax = 1; |
a39116f1 | 850 | |
fecd2382 RP |
851 | } else if (**argP == 'b'){ |
852 | instrument_branches = 1; | |
a39116f1 | 853 | |
fecd2382 RP |
854 | } else if (**argP == 'A'){ |
855 | p = (*argP) + 1; | |
a39116f1 | 856 | |
fecd2382 RP |
857 | for (tp = arch_tab; tp->flag != NULL; tp++){ |
858 | if (!strcmp(p,tp->flag)){ | |
859 | break; | |
860 | } | |
861 | } | |
a39116f1 | 862 | |
fecd2382 RP |
863 | if (tp->flag == NULL){ |
864 | as_bad("unknown architecture: %s", p); | |
865 | } else { | |
866 | architecture = tp->arch; | |
867 | } | |
868 | } else { | |
869 | /* Unknown option */ | |
870 | (*argP)++; | |
871 | return 0; | |
872 | } | |
873 | **argP = '\0'; /* Done parsing this switch */ | |
874 | return 1; | |
875 | } | |
876 | ||
877 | /***************************************************************************** | |
878 | * md_convert_frag: | |
879 | * Called by base assembler after address relaxation is finished: modify | |
880 | * variable fragments according to how much relaxation was done. | |
881 | * | |
882 | * If the fragment substate is still 1, a 13-bit displacement was enough | |
883 | * to reach the symbol in question. Set up an address fixup, but otherwise | |
884 | * leave the cobr instruction alone. | |
885 | * | |
886 | * If the fragment substate is 2, a 13-bit displacement was not enough. | |
887 | * Replace the cobr with a two instructions (a compare and a branch). | |
888 | * | |
889 | **************************************************************************** */ | |
890 | void | |
a39116f1 | 891 | md_convert_frag(headers, fragP) |
a79c6033 | 892 | object_headers *headers; |
a39116f1 | 893 | fragS * fragP; |
fecd2382 RP |
894 | { |
895 | fixS *fixP; /* Structure describing needed address fix */ | |
a39116f1 | 896 | |
fecd2382 RP |
897 | switch (fragP->fr_subtype){ |
898 | case 1: | |
899 | /* LEAVE SINGLE COBR INSTRUCTION */ | |
900 | fixP = fix_new(fragP, | |
901 | fragP->fr_opcode-fragP->fr_literal, | |
902 | 4, | |
903 | fragP->fr_symbol, | |
904 | 0, | |
905 | fragP->fr_offset, | |
906 | 1, | |
907 | 0); | |
a39116f1 | 908 | |
fecd2382 RP |
909 | fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */ |
910 | break; | |
911 | case 2: | |
912 | /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */ | |
913 | relax_cobr(fragP); | |
914 | break; | |
915 | default: | |
916 | BAD_CASE(fragP->fr_subtype); | |
917 | break; | |
918 | } | |
919 | } | |
920 | ||
921 | /***************************************************************************** | |
922 | * md_estimate_size_before_relax: How much does it look like *fragP will grow? | |
923 | * | |
924 | * Called by base assembler just before address relaxation. | |
925 | * Return the amount by which the fragment will grow. | |
926 | * | |
927 | * Any symbol that is now undefined will not become defined; cobr's | |
928 | * based on undefined symbols will have to be replaced with a compare | |
929 | * instruction and a branch instruction, and the code fragment will grow | |
930 | * by 4 bytes. | |
931 | * | |
932 | **************************************************************************** */ | |
933 | int | |
a39116f1 RP |
934 | md_estimate_size_before_relax(fragP, segment_type) |
935 | register fragS *fragP; | |
936 | register segT segment_type; | |
fecd2382 RP |
937 | { |
938 | /* If symbol is undefined in this segment, go to "relaxed" state | |
939 | * (compare and branch instructions instead of cobr) right now. | |
940 | */ | |
941 | if (S_GET_SEGMENT(fragP->fr_symbol) != segment_type) { | |
942 | relax_cobr(fragP); | |
943 | return 4; | |
944 | } | |
945 | return 0; | |
946 | } /* md_estimate_size_before_relax() */ | |
947 | ||
948 | ||
949 | /***************************************************************************** | |
950 | * md_ri_to_chars: | |
951 | * This routine exists in order to overcome machine byte-order problems | |
952 | * when dealing with bit-field entries in the relocation_info struct. | |
953 | * | |
954 | * But relocation info will be used on the host machine only (only | |
955 | * executable code is actually downloaded to the i80960). Therefore, | |
956 | * we leave it in host byte order. | |
957 | * | |
958 | **************************************************************************** */ | |
a79c6033 RP |
959 | void md_ri_to_chars(where, ri) |
960 | char *where; | |
961 | struct relocation_info *ri; | |
fecd2382 | 962 | { |
a79c6033 | 963 | *((struct relocation_info *) where) = *ri; /* structure assignment */ |
fecd2382 RP |
964 | } /* md_ri_to_chars() */ |
965 | ||
fecd2382 RP |
966 | #ifndef WORKING_DOT_WORD |
967 | ||
968 | int md_short_jump_size = 0; | |
969 | int md_long_jump_size = 0; | |
970 | ||
971 | void md_create_short_jump(ptr, from_addr, to_addr, frag, to_symbol) | |
972 | char *ptr; | |
973 | long from_addr; | |
974 | long to_addr; | |
975 | fragS *frag; | |
976 | symbolS *to_symbol; | |
977 | { | |
a39116f1 | 978 | as_fatal("failed sanity check."); |
fecd2382 RP |
979 | } |
980 | ||
981 | void | |
a39116f1 RP |
982 | md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol) |
983 | char *ptr; | |
984 | long from_addr, to_addr; | |
985 | fragS *frag; | |
986 | symbolS *to_symbol; | |
fecd2382 | 987 | { |
a39116f1 | 988 | as_fatal("failed sanity check."); |
fecd2382 RP |
989 | } |
990 | #endif | |
991 | \f | |
a39116f1 RP |
992 | /************************************************************* |
993 | * * | |
994 | * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER * | |
995 | * * | |
996 | ************************************************************ */ | |
fecd2382 RP |
997 | |
998 | ||
999 | ||
1000 | /***************************************************************************** | |
1001 | * brcnt_emit: Emit code to increment inline branch counter. | |
1002 | * | |
1003 | * See the comments above the declaration of 'br_cnt' for details on | |
1004 | * branch-prediction instrumentation. | |
1005 | **************************************************************************** */ | |
1006 | static void | |
a39116f1 | 1007 | brcnt_emit() |
fecd2382 RP |
1008 | { |
1009 | ctrl_fmt(BR_CNT_FUNC,CALL,1);/* Emit call to "increment" routine */ | |
1010 | emit(0); /* Emit inline counter to be incremented */ | |
1011 | } | |
1012 | ||
1013 | /***************************************************************************** | |
1014 | * brlab_next: generate the next branch local label | |
1015 | * | |
1016 | * See the comments above the declaration of 'br_cnt' for details on | |
1017 | * branch-prediction instrumentation. | |
1018 | **************************************************************************** */ | |
1019 | static char * | |
a39116f1 | 1020 | brlab_next() |
fecd2382 RP |
1021 | { |
1022 | static char buf[20]; | |
a39116f1 | 1023 | |
fecd2382 RP |
1024 | sprintf(buf, "%s%d", BR_LABEL_BASE, br_cnt++); |
1025 | return buf; | |
1026 | } | |
1027 | ||
1028 | /***************************************************************************** | |
1029 | * brtab_emit: generate the fetch-prediction branch table. | |
1030 | * | |
1031 | * See the comments above the declaration of 'br_cnt' for details on | |
1032 | * branch-prediction instrumentation. | |
1033 | * | |
1034 | * The code emitted here would be functionally equivalent to the following | |
1035 | * example assembler source. | |
1036 | * | |
1037 | * .data | |
1038 | * .align 2 | |
1039 | * BR_TAB_NAME: | |
1040 | * .word 0 # link to next table | |
1041 | * .word 3 # length of table | |
1042 | * .word LBRANCH0 # 1st entry in table proper | |
1043 | * .word LBRANCH1 | |
1044 | * .word LBRANCH2 | |
1045 | ***************************************************************************** */ | |
1046 | void | |
a39116f1 | 1047 | brtab_emit() |
fecd2382 RP |
1048 | { |
1049 | int i; | |
1050 | char buf[20]; | |
1051 | char *p; /* Where the binary was output to */ | |
1052 | fixS *fixP; /*->description of deferred address fixup */ | |
a39116f1 | 1053 | |
fecd2382 RP |
1054 | if (!instrument_branches){ |
1055 | return; | |
1056 | } | |
a39116f1 | 1057 | |
fecd2382 RP |
1058 | subseg_new(SEG_DATA,0); /* .data */ |
1059 | frag_align(2,0); /* .align 2 */ | |
1060 | record_alignment(now_seg,2); | |
1061 | colon(BR_TAB_NAME); /* BR_TAB_NAME: */ | |
1062 | emit(0); /* .word 0 #link to next table */ | |
1063 | emit(br_cnt); /* .word n #length of table */ | |
a39116f1 | 1064 | |
fecd2382 RP |
1065 | for (i=0; i<br_cnt; i++){ |
1066 | sprintf(buf, "%s%d", BR_LABEL_BASE, i); | |
1067 | p = emit(0); | |
1068 | fixP = fix_new(frag_now, | |
1069 | p - frag_now->fr_literal, | |
1070 | 4, | |
1071 | symbol_find(buf), | |
1072 | 0, | |
1073 | 0, | |
1074 | 0, | |
1075 | 0); | |
09952cd9 | 1076 | fixP->fx_im_disp = 2; /* 32-bit displacement fix */ |
fecd2382 RP |
1077 | } |
1078 | } | |
1079 | ||
1080 | /***************************************************************************** | |
1081 | * cobr_fmt: generate a COBR-format instruction | |
1082 | * | |
1083 | **************************************************************************** */ | |
1084 | static | |
a39116f1 RP |
1085 | void |
1086 | cobr_fmt(arg, opcode, oP) | |
1087 | char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */ | |
1088 | long opcode; /* Opcode, with branch-prediction bits already set | |
1089 | * if necessary. | |
1090 | */ | |
1091 | struct i960_opcode *oP; | |
1092 | /*->description of instruction */ | |
fecd2382 RP |
1093 | { |
1094 | long instr; /* 32-bit instruction */ | |
1095 | struct regop regop; /* Description of register operand */ | |
1096 | int n; /* Number of operands */ | |
1097 | int var_frag; /* 1 if varying length code fragment should | |
1098 | * be emitted; 0 if an address fix | |
1099 | * should be emitted. | |
1100 | */ | |
a39116f1 | 1101 | |
fecd2382 RP |
1102 | instr = opcode; |
1103 | n = oP->num_ops; | |
a39116f1 | 1104 | |
fecd2382 RP |
1105 | if (n >= 1) { |
1106 | /* First operand (if any) of a COBR is always a register | |
1107 | * operand. Parse it. | |
1108 | */ | |
1109 | parse_regop(®op, arg[1], oP->operand[0]); | |
1110 | instr |= (regop.n << 19) | (regop.mode << 13); | |
1111 | } | |
1112 | if (n >= 2) { | |
1113 | /* Second operand (if any) of a COBR is always a register | |
1114 | * operand. Parse it. | |
1115 | */ | |
1116 | parse_regop(®op, arg[2], oP->operand[1]); | |
1117 | instr |= (regop.n << 14) | regop.special; | |
1118 | } | |
a39116f1 RP |
1119 | |
1120 | ||
fecd2382 RP |
1121 | if (n < 3){ |
1122 | emit(instr); | |
a39116f1 | 1123 | |
fecd2382 RP |
1124 | } else { |
1125 | if (instrument_branches){ | |
1126 | brcnt_emit(); | |
1127 | colon(brlab_next()); | |
1128 | } | |
a39116f1 | 1129 | |
fecd2382 RP |
1130 | /* A third operand to a COBR is always a displacement. |
1131 | * Parse it; if it's relaxable (a cobr "j" directive, or any | |
1132 | * cobr other than bbs/bbc when the "-norelax" option is not in | |
1133 | * use) set up a variable code fragment; otherwise set up an | |
1134 | * address fix. | |
1135 | */ | |
1136 | var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */ | |
1137 | get_cdisp(arg[3], "COBR", instr, 13, var_frag, 0); | |
a39116f1 | 1138 | |
fecd2382 RP |
1139 | if (instrument_branches){ |
1140 | brcnt_emit(); | |
1141 | } | |
1142 | } | |
1143 | } /* cobr_fmt() */ | |
1144 | ||
1145 | ||
1146 | /***************************************************************************** | |
1147 | * ctrl_fmt: generate a CTRL-format instruction | |
1148 | * | |
1149 | **************************************************************************** */ | |
1150 | static | |
a39116f1 RP |
1151 | void |
1152 | ctrl_fmt(targP, opcode, num_ops) | |
1153 | char *targP; /* Pointer to text of lone operand (if any) */ | |
1154 | long opcode; /* Template of instruction */ | |
1155 | int num_ops; /* Number of operands */ | |
fecd2382 RP |
1156 | { |
1157 | int instrument; /* TRUE iff we should add instrumentation to track | |
1158 | * how often the branch is taken | |
1159 | */ | |
a39116f1 RP |
1160 | |
1161 | ||
fecd2382 RP |
1162 | if (num_ops == 0){ |
1163 | emit(opcode); /* Output opcode */ | |
1164 | } else { | |
a39116f1 | 1165 | |
fecd2382 | 1166 | instrument = instrument_branches && (opcode!=CALL) |
a39116f1 RP |
1167 | && (opcode!=B) && (opcode!=RET) && (opcode!=BAL); |
1168 | ||
fecd2382 RP |
1169 | if (instrument){ |
1170 | brcnt_emit(); | |
1171 | colon(brlab_next()); | |
1172 | } | |
a39116f1 | 1173 | |
fecd2382 RP |
1174 | /* The operand MUST be an ip-relative displacment. Parse it |
1175 | * and set up address fix for the instruction we just output. | |
1176 | */ | |
1177 | get_cdisp(targP, "CTRL", opcode, 24, 0, 0); | |
a39116f1 | 1178 | |
fecd2382 RP |
1179 | if (instrument){ |
1180 | brcnt_emit(); | |
1181 | } | |
1182 | } | |
a39116f1 | 1183 | |
fecd2382 RP |
1184 | } |
1185 | ||
1186 | ||
1187 | /***************************************************************************** | |
1188 | * emit: output instruction binary | |
1189 | * | |
1190 | * Output instruction binary, in target byte order, 4 bytes at a time. | |
1191 | * Return pointer to where it was placed. | |
1192 | * | |
1193 | **************************************************************************** */ | |
1194 | static | |
a39116f1 RP |
1195 | char * |
1196 | emit(instr) | |
1197 | long instr; /* Word to be output, host byte order */ | |
fecd2382 RP |
1198 | { |
1199 | char *toP; /* Where to output it */ | |
a39116f1 | 1200 | |
fecd2382 RP |
1201 | toP = frag_more(4); /* Allocate storage */ |
1202 | md_number_to_chars(toP, instr, 4); /* Convert to target byte order */ | |
1203 | return toP; | |
1204 | } | |
1205 | ||
1206 | ||
1207 | /***************************************************************************** | |
1208 | * get_args: break individual arguments out of comma-separated list | |
1209 | * | |
1210 | * Input assumptions: | |
1211 | * - all comments and labels have been removed | |
1212 | * - all strings of whitespace have been collapsed to a single blank. | |
1213 | * - all character constants ('x') have been replaced with decimal | |
1214 | * | |
1215 | * Output: | |
1216 | * args[0] is untouched. args[1] points to first operand, etc. All args: | |
1217 | * - are NULL-terminated | |
1218 | * - contain no whitespace | |
1219 | * | |
1220 | * Return value: | |
1221 | * Number of operands (0,1,2, or 3) or -1 on error. | |
1222 | * | |
1223 | **************************************************************************** */ | |
1224 | static int get_args(p, args) | |
a39116f1 RP |
1225 | register char *p; /* Pointer to comma-separated operands; MUCKED BY US */ |
1226 | char *args[]; /* Output arg: pointers to operands placed in args[1-3]. | |
1227 | * MUST ACCOMMODATE 4 ENTRIES (args[0-3]). | |
1228 | */ | |
fecd2382 RP |
1229 | { |
1230 | register int n; /* Number of operands */ | |
1231 | register char *to; | |
a39116f1 RP |
1232 | /* char buf[4]; */ |
1233 | /* int len; */ | |
1234 | ||
1235 | ||
fecd2382 RP |
1236 | /* Skip lead white space */ |
1237 | while (*p == ' '){ | |
1238 | p++; | |
1239 | } | |
a39116f1 | 1240 | |
fecd2382 RP |
1241 | if (*p == '\0'){ |
1242 | return 0; | |
1243 | } | |
a39116f1 | 1244 | |
fecd2382 RP |
1245 | n = 1; |
1246 | args[1] = p; | |
a39116f1 | 1247 | |
fecd2382 RP |
1248 | /* Squeze blanks out by moving non-blanks toward start of string. |
1249 | * Isolate operands, whenever comma is found. | |
1250 | */ | |
1251 | to = p; | |
1252 | while (*p != '\0'){ | |
a39116f1 | 1253 | |
fecd2382 RP |
1254 | if (*p == ' '){ |
1255 | p++; | |
a39116f1 | 1256 | |
fecd2382 | 1257 | } else if (*p == ','){ |
a39116f1 | 1258 | |
fecd2382 RP |
1259 | /* Start of operand */ |
1260 | if (n == 3){ | |
1261 | as_bad("too many operands"); | |
1262 | return -1; | |
1263 | } | |
1264 | *to++ = '\0'; /* Terminate argument */ | |
1265 | args[++n] = to; /* Start next argument */ | |
1266 | p++; | |
a39116f1 | 1267 | |
fecd2382 RP |
1268 | } else { |
1269 | *to++ = *p++; | |
1270 | } | |
1271 | } | |
1272 | *to = '\0'; | |
1273 | return n; | |
1274 | } | |
1275 | ||
1276 | ||
1277 | /***************************************************************************** | |
1278 | * get_cdisp: handle displacement for a COBR or CTRL instruction. | |
1279 | * | |
1280 | * Parse displacement for a COBR or CTRL instruction. | |
1281 | * | |
1282 | * If successful, output the instruction opcode and set up for it, | |
1283 | * depending on the arg 'var_frag', either: | |
1284 | * o an address fixup to be done when all symbol values are known, or | |
1285 | * o a varying length code fragment, with address fixup info. This | |
1286 | * will be done for cobr instructions that may have to be relaxed | |
1287 | * in to compare/branch instructions (8 bytes) if the final address | |
1288 | * displacement is greater than 13 bits. | |
1289 | * | |
1290 | **************************************************************************** */ | |
1291 | static | |
a39116f1 RP |
1292 | void |
1293 | get_cdisp(dispP, ifmtP, instr, numbits, var_frag, callj) | |
1294 | char *dispP; /*->displacement as specified in source instruction */ | |
1295 | char *ifmtP; /*->"COBR" or "CTRL" (for use in error message) */ | |
1296 | long instr; /* Instruction needing the displacement */ | |
1297 | int numbits; /* # bits of displacement (13 for COBR, 24 for CTRL) */ | |
1298 | int var_frag; /* 1 if varying length code fragment should be emitted; | |
1299 | * 0 if an address fix should be emitted. | |
1300 | */ | |
1301 | int callj; /* 1 if callj relocation should be done; else 0 */ | |
fecd2382 RP |
1302 | { |
1303 | expressionS e; /* Parsed expression */ | |
1304 | fixS *fixP; /* Structure describing needed address fix */ | |
1305 | char *outP; /* Where instruction binary is output to */ | |
a39116f1 | 1306 | |
fecd2382 | 1307 | fixP = NULL; |
a39116f1 | 1308 | |
fecd2382 | 1309 | switch (parse_expr(dispP,&e)) { |
a39116f1 | 1310 | |
fecd2382 RP |
1311 | case SEG_GOOF: |
1312 | as_bad("expression syntax error"); | |
1313 | break; | |
a39116f1 | 1314 | |
fecd2382 RP |
1315 | case SEG_TEXT: |
1316 | case SEG_UNKNOWN: | |
1317 | if (var_frag) { | |
1318 | outP = frag_more(8); /* Allocate worst-case storage */ | |
1319 | md_number_to_chars(outP, instr, 4); | |
1320 | frag_variant(rs_machine_dependent, 4, 4, 1, | |
a39116f1 | 1321 | adds(e), offs(e), outP, 0, 0); |
fecd2382 RP |
1322 | } else { |
1323 | /* Set up a new fix structure, so address can be updated | |
1324 | * when all symbol values are known. | |
1325 | */ | |
1326 | outP = emit(instr); | |
1327 | fixP = fix_new(frag_now, | |
1328 | outP - frag_now->fr_literal, | |
1329 | 4, | |
1330 | adds(e), | |
1331 | 0, | |
1332 | offs(e), | |
1333 | 1, | |
1334 | 0); | |
a39116f1 | 1335 | |
fecd2382 | 1336 | fixP->fx_callj = callj; |
a39116f1 | 1337 | |
fecd2382 RP |
1338 | /* We want to modify a bit field when the address is |
1339 | * known. But we don't need all the garbage in the | |
1340 | * bit_fix structure. So we're going to lie and store | |
1341 | * the number of bits affected instead of a pointer. | |
1342 | */ | |
1343 | fixP->fx_bit_fixP = (bit_fixS *) numbits; | |
1344 | } | |
1345 | break; | |
a39116f1 | 1346 | |
fecd2382 RP |
1347 | case SEG_DATA: |
1348 | case SEG_BSS: | |
1349 | as_bad("attempt to branch into different segment"); | |
1350 | break; | |
a39116f1 | 1351 | |
fecd2382 RP |
1352 | default: |
1353 | as_bad("target of %s instruction must be a label", ifmtP); | |
1354 | break; | |
1355 | } | |
1356 | } | |
1357 | ||
1358 | ||
1359 | /***************************************************************************** | |
1360 | * get_ispec: parse a memory operand for an index specification | |
1361 | * | |
1362 | * Here, an "index specification" is taken to be anything surrounded | |
1363 | * by square brackets and NOT followed by anything else. | |
1364 | * | |
1365 | * If it's found, detach it from the input string, remove the surrounding | |
1366 | * square brackets, and return a pointer to it. Otherwise, return NULL. | |
1367 | * | |
1368 | **************************************************************************** */ | |
1369 | static | |
a39116f1 RP |
1370 | char * |
1371 | get_ispec(textP) | |
1372 | char *textP; /*->memory operand from source instruction, no white space */ | |
fecd2382 RP |
1373 | { |
1374 | char *start; /*->start of index specification */ | |
1375 | char *end; /*->end of index specification */ | |
a39116f1 | 1376 | |
fecd2382 RP |
1377 | /* Find opening square bracket, if any |
1378 | */ | |
a79c6033 | 1379 | start = strchr(textP, '['); |
a39116f1 | 1380 | |
fecd2382 | 1381 | if (start != NULL){ |
a39116f1 | 1382 | |
fecd2382 RP |
1383 | /* Eliminate '[', detach from rest of operand */ |
1384 | *start++ = '\0'; | |
a39116f1 | 1385 | |
a79c6033 | 1386 | end = strchr(start, ']'); |
a39116f1 | 1387 | |
fecd2382 RP |
1388 | if (end == NULL){ |
1389 | as_bad("unmatched '['"); | |
a39116f1 | 1390 | |
fecd2382 RP |
1391 | } else { |
1392 | /* Eliminate ']' and make sure it was the last thing | |
1393 | * in the string. | |
1394 | */ | |
1395 | *end = '\0'; | |
1396 | if (*(end+1) != '\0'){ | |
1397 | as_bad("garbage after index spec ignored"); | |
1398 | } | |
1399 | } | |
1400 | } | |
1401 | return start; | |
1402 | } | |
1403 | ||
1404 | /***************************************************************************** | |
1405 | * get_regnum: | |
1406 | * | |
1407 | * Look up a (suspected) register name in the register table and return the | |
1408 | * associated register number (or -1 if not found). | |
1409 | * | |
1410 | **************************************************************************** */ | |
1411 | static | |
a39116f1 RP |
1412 | int |
1413 | get_regnum(regname) | |
1414 | char *regname; /* Suspected register name */ | |
fecd2382 RP |
1415 | { |
1416 | int *rP; | |
a39116f1 | 1417 | |
fecd2382 RP |
1418 | rP = (int *) hash_find(reg_hash, regname); |
1419 | return (rP == NULL) ? -1 : *rP; | |
1420 | } | |
1421 | ||
1422 | ||
1423 | /***************************************************************************** | |
1424 | * i_scan: perform lexical scan of ascii assembler instruction. | |
1425 | * | |
1426 | * Input assumptions: | |
1427 | * - input string is an i80960 instruction (not a pseudo-op) | |
1428 | * - all comments and labels have been removed | |
1429 | * - all strings of whitespace have been collapsed to a single blank. | |
1430 | * | |
1431 | * Output: | |
1432 | * args[0] points to opcode, other entries point to operands. All strings: | |
1433 | * - are NULL-terminated | |
1434 | * - contain no whitespace | |
1435 | * - have character constants ('x') replaced with a decimal number | |
1436 | * | |
1437 | * Return value: | |
1438 | * Number of operands (0,1,2, or 3) or -1 on error. | |
1439 | * | |
1440 | **************************************************************************** */ | |
1441 | static int i_scan(iP, args) | |
a39116f1 RP |
1442 | register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */ |
1443 | char *args[]; /* Output arg: pointers to opcode and operands placed | |
1444 | * here. MUST ACCOMMODATE 4 ENTRIES. | |
1445 | */ | |
fecd2382 | 1446 | { |
a39116f1 | 1447 | |
fecd2382 RP |
1448 | /* Isolate opcode */ |
1449 | if (*(iP) == ' ') { | |
1450 | iP++; | |
1451 | } /* Skip lead space, if any */ | |
1452 | args[0] = iP; | |
1453 | for (; *iP != ' '; iP++) { | |
1454 | if (*iP == '\0') { | |
1455 | /* There are no operands */ | |
1456 | if (args[0] == iP) { | |
1457 | /* We never moved: there was no opcode either! */ | |
1458 | as_bad("missing opcode"); | |
1459 | return -1; | |
1460 | } | |
1461 | return 0; | |
1462 | } | |
1463 | } | |
1464 | *iP++ = '\0'; /* Terminate opcode */ | |
1465 | return(get_args(iP, args)); | |
1466 | } /* i_scan() */ | |
1467 | ||
1468 | ||
1469 | /***************************************************************************** | |
1470 | * mem_fmt: generate a MEMA- or MEMB-format instruction | |
1471 | * | |
1472 | **************************************************************************** */ | |
09952cd9 | 1473 | static void mem_fmt(args, oP, callx) |
a39116f1 RP |
1474 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ |
1475 | struct i960_opcode *oP; /* Pointer to description of instruction */ | |
09952cd9 | 1476 | int callx; /* Is this a callx opcode */ |
fecd2382 RP |
1477 | { |
1478 | int i; /* Loop counter */ | |
1479 | struct regop regop; /* Description of register operand */ | |
1480 | char opdesc; /* Operand descriptor byte */ | |
1481 | memS instr; /* Description of binary to be output */ | |
1482 | char *outP; /* Where the binary was output to */ | |
1483 | expressionS expr; /* Parsed expression */ | |
1484 | fixS *fixP; /*->description of deferred address fixup */ | |
a39116f1 | 1485 | |
542e1629 | 1486 | memset(&instr, '\0', sizeof(memS)); |
fecd2382 | 1487 | instr.opcode = oP->opcode; |
a39116f1 | 1488 | |
fecd2382 RP |
1489 | /* Process operands. */ |
1490 | for (i = 1; i <= oP->num_ops; i++){ | |
1491 | opdesc = oP->operand[i-1]; | |
a39116f1 | 1492 | |
fecd2382 RP |
1493 | if (MEMOP(opdesc)){ |
1494 | parse_memop(&instr, args[i], oP->format); | |
1495 | } else { | |
1496 | parse_regop(®op, args[i], opdesc); | |
1497 | instr.opcode |= regop.n << 19; | |
1498 | } | |
1499 | } | |
a39116f1 | 1500 | |
fecd2382 RP |
1501 | /* Output opcode */ |
1502 | outP = emit(instr.opcode); | |
a39116f1 | 1503 | |
fecd2382 RP |
1504 | if (instr.disp == 0){ |
1505 | return; | |
1506 | } | |
a39116f1 | 1507 | |
fecd2382 RP |
1508 | /* Parse and process the displacement */ |
1509 | switch (parse_expr(instr.e,&expr)){ | |
a39116f1 | 1510 | |
fecd2382 RP |
1511 | case SEG_GOOF: |
1512 | as_bad("expression syntax error"); | |
1513 | break; | |
a39116f1 | 1514 | |
fecd2382 RP |
1515 | case SEG_ABSOLUTE: |
1516 | if (instr.disp == 32){ | |
1517 | (void) emit(offs(expr)); /* Output displacement */ | |
1518 | } else { | |
1519 | /* 12-bit displacement */ | |
1520 | if (offs(expr) & ~0xfff){ | |
1521 | /* Won't fit in 12 bits: convert already-output | |
1522 | * instruction to MEMB format, output | |
1523 | * displacement. | |
1524 | */ | |
1525 | mema_to_memb(outP); | |
1526 | (void) emit(offs(expr)); | |
1527 | } else { | |
1528 | /* WILL fit in 12 bits: OR into opcode and | |
1529 | * overwrite the binary we already put out | |
1530 | */ | |
1531 | instr.opcode |= offs(expr); | |
1532 | md_number_to_chars(outP, instr.opcode, 4); | |
1533 | } | |
1534 | } | |
1535 | break; | |
a39116f1 | 1536 | |
fecd2382 RP |
1537 | case SEG_DIFFERENCE: |
1538 | case SEG_TEXT: | |
1539 | case SEG_DATA: | |
1540 | case SEG_BSS: | |
1541 | case SEG_UNKNOWN: | |
1542 | if (instr.disp == 12){ | |
1543 | /* Displacement is dependent on a symbol, whose value | |
1544 | * may change at link time. We HAVE to reserve 32 bits. | |
1545 | * Convert already-output opcode to MEMB format. | |
1546 | */ | |
1547 | mema_to_memb(outP); | |
1548 | } | |
a39116f1 | 1549 | |
fecd2382 RP |
1550 | /* Output 0 displacement and set up address fixup for when |
1551 | * this symbol's value becomes known. | |
1552 | */ | |
1553 | outP = emit((long) 0); | |
1554 | fixP = fix_new(frag_now, | |
1555 | outP - frag_now->fr_literal, | |
1556 | 4, | |
1557 | adds(expr), | |
1558 | subs(expr), | |
1559 | offs(expr), | |
1560 | 0, | |
09952cd9 KR |
1561 | NO_RELOC); |
1562 | fixP->fx_im_disp = 2; /* 32-bit displacement fix */ | |
1563 | fixP->fx_bsr = callx; /*SAC LD RELAX HACK */ /* Mark reloc as being in i stream */ | |
fecd2382 | 1564 | break; |
a39116f1 | 1565 | |
fecd2382 RP |
1566 | default: |
1567 | BAD_CASE(segs(expr)); | |
1568 | break; | |
1569 | } | |
1570 | } /* memfmt() */ | |
1571 | ||
1572 | ||
1573 | /***************************************************************************** | |
1574 | * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode. | |
1575 | * | |
1576 | * There are 2 possible MEMA formats: | |
1577 | * - displacement only | |
1578 | * - displacement + abase | |
1579 | * | |
1580 | * They are distinguished by the setting of the MEMA_ABASE bit. | |
1581 | * | |
1582 | **************************************************************************** */ | |
1583 | static void mema_to_memb(opcodeP) | |
a39116f1 | 1584 | char *opcodeP; /* Where to find the opcode, in target byte order */ |
fecd2382 RP |
1585 | { |
1586 | long opcode; /* Opcode in host byte order */ | |
1587 | long mode; /* Mode bits for MEMB instruction */ | |
a39116f1 | 1588 | |
fecd2382 RP |
1589 | opcode = md_chars_to_number(opcodeP, 4); |
1590 | know(!(opcode & MEMB_BIT)); | |
a39116f1 | 1591 | |
fecd2382 RP |
1592 | mode = MEMB_BIT | D_BIT; |
1593 | if (opcode & MEMA_ABASE){ | |
1594 | mode |= A_BIT; | |
1595 | } | |
a39116f1 | 1596 | |
fecd2382 RP |
1597 | opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */ |
1598 | opcode |= mode; /* Set MEMB mode bits */ | |
a39116f1 | 1599 | |
fecd2382 RP |
1600 | md_number_to_chars(opcodeP, opcode, 4); |
1601 | } /* mema_to_memb() */ | |
1602 | ||
1603 | ||
1604 | /***************************************************************************** | |
1605 | * parse_expr: parse an expression | |
1606 | * | |
1607 | * Use base assembler's expression parser to parse an expression. | |
1608 | * It, unfortunately, runs off a global which we have to save/restore | |
1609 | * in order to make it work for us. | |
1610 | * | |
1611 | * An empty expression string is treated as an absolute 0. | |
1612 | * | |
1613 | * Return "segment" to which the expression evaluates. | |
1614 | * Return SEG_GOOF regardless of expression evaluation if entire input | |
1615 | * string is not consumed in the evaluation -- tolerate no dangling junk! | |
1616 | * | |
1617 | **************************************************************************** */ | |
1618 | static | |
a39116f1 RP |
1619 | segT |
1620 | parse_expr(textP, expP) | |
1621 | char *textP; /* Text of expression to be parsed */ | |
1622 | expressionS *expP; /* Where to put the results of parsing */ | |
fecd2382 RP |
1623 | { |
1624 | char *save_in; /* Save global here */ | |
1625 | segT seg; /* Segment to which expression evaluates */ | |
1626 | symbolS *symP; | |
a39116f1 | 1627 | |
fecd2382 | 1628 | know(textP); |
a39116f1 | 1629 | |
fecd2382 RP |
1630 | if (*textP == '\0') { |
1631 | /* Treat empty string as absolute 0 */ | |
1632 | expP->X_add_symbol = expP->X_subtract_symbol = NULL; | |
1633 | expP->X_add_number = 0; | |
1634 | seg = expP->X_seg = SEG_ABSOLUTE; | |
a39116f1 | 1635 | |
fecd2382 RP |
1636 | } else { |
1637 | save_in = input_line_pointer; /* Save global */ | |
1638 | input_line_pointer = textP; /* Make parser work for us */ | |
a39116f1 | 1639 | |
fecd2382 RP |
1640 | seg = expression(expP); |
1641 | if (input_line_pointer - textP != strlen(textP)) { | |
1642 | /* Did not consume all of the input */ | |
1643 | seg = SEG_GOOF; | |
1644 | } | |
1645 | symP = expP->X_add_symbol; | |
1646 | if (symP && (hash_find(reg_hash, S_GET_NAME(symP)))) { | |
1647 | /* Register name in an expression */ | |
1648 | seg = SEG_GOOF; | |
1649 | } | |
a39116f1 | 1650 | |
fecd2382 RP |
1651 | input_line_pointer = save_in; /* Restore global */ |
1652 | } | |
1653 | return seg; | |
1654 | } | |
1655 | ||
1656 | ||
1657 | /***************************************************************************** | |
1658 | * parse_ldcont: | |
1659 | * Parse and replace a 'ldconst' pseudo-instruction with an appropriate | |
1660 | * i80960 instruction. | |
1661 | * | |
1662 | * Assumes the input consists of: | |
1663 | * arg[0] opcode mnemonic ('ldconst') | |
1664 | * arg[1] first operand (constant) | |
1665 | * arg[2] name of register to be loaded | |
1666 | * | |
1667 | * Replaces opcode and/or operands as appropriate. | |
1668 | * | |
1669 | * Returns the new number of arguments, or -1 on failure. | |
1670 | * | |
1671 | **************************************************************************** */ | |
1672 | static | |
a39116f1 RP |
1673 | int |
1674 | parse_ldconst(arg) | |
1675 | char *arg[]; /* See above */ | |
fecd2382 RP |
1676 | { |
1677 | int n; /* Constant to be loaded */ | |
1678 | int shift; /* Shift count for "shlo" instruction */ | |
1679 | static char buf[5]; /* Literal for first operand */ | |
1680 | static char buf2[5]; /* Literal for second operand */ | |
1681 | expressionS e; /* Parsed expression */ | |
a39116f1 RP |
1682 | |
1683 | ||
fecd2382 | 1684 | arg[3] = NULL; /* So we can tell at the end if it got used or not */ |
a39116f1 | 1685 | |
fecd2382 | 1686 | switch(parse_expr(arg[1],&e)){ |
a39116f1 | 1687 | |
fecd2382 RP |
1688 | case SEG_TEXT: |
1689 | case SEG_DATA: | |
1690 | case SEG_BSS: | |
1691 | case SEG_UNKNOWN: | |
1692 | case SEG_DIFFERENCE: | |
1693 | /* We're dependent on one or more symbols -- use "lda" */ | |
1694 | arg[0] = "lda"; | |
1695 | break; | |
a39116f1 | 1696 | |
fecd2382 RP |
1697 | case SEG_ABSOLUTE: |
1698 | /* Try the following mappings: | |
1699 | * ldconst 0,<reg> ->mov 0,<reg> | |
1700 | * ldconst 31,<reg> ->mov 31,<reg> | |
1701 | * ldconst 32,<reg> ->addo 1,31,<reg> | |
1702 | * ldconst 62,<reg> ->addo 31,31,<reg> | |
1703 | * ldconst 64,<reg> ->shlo 8,3,<reg> | |
1704 | * ldconst -1,<reg> ->subo 1,0,<reg> | |
1705 | * ldconst -31,<reg>->subo 31,0,<reg> | |
1706 | * | |
1707 | * anthing else becomes: | |
1708 | * lda xxx,<reg> | |
1709 | */ | |
1710 | n = offs(e); | |
1711 | if ((0 <= n) && (n <= 31)){ | |
1712 | arg[0] = "mov"; | |
a39116f1 | 1713 | |
fecd2382 RP |
1714 | } else if ((-31 <= n) && (n <= -1)){ |
1715 | arg[0] = "subo"; | |
1716 | arg[3] = arg[2]; | |
1717 | sprintf(buf, "%d", -n); | |
1718 | arg[1] = buf; | |
1719 | arg[2] = "0"; | |
a39116f1 | 1720 | |
fecd2382 RP |
1721 | } else if ((32 <= n) && (n <= 62)){ |
1722 | arg[0] = "addo"; | |
1723 | arg[3] = arg[2]; | |
1724 | arg[1] = "31"; | |
1725 | sprintf(buf, "%d", n-31); | |
1726 | arg[2] = buf; | |
a39116f1 | 1727 | |
fecd2382 RP |
1728 | } else if ((shift = shift_ok(n)) != 0){ |
1729 | arg[0] = "shlo"; | |
1730 | arg[3] = arg[2]; | |
1731 | sprintf(buf, "%d", shift); | |
1732 | arg[1] = buf; | |
1733 | sprintf(buf2, "%d", n >> shift); | |
1734 | arg[2] = buf2; | |
a39116f1 | 1735 | |
fecd2382 RP |
1736 | } else { |
1737 | arg[0] = "lda"; | |
1738 | } | |
1739 | break; | |
a39116f1 | 1740 | |
fecd2382 RP |
1741 | default: |
1742 | as_bad("invalid constant"); | |
1743 | return -1; | |
1744 | break; | |
1745 | } | |
1746 | return (arg[3] == 0) ? 2: 3; | |
1747 | } | |
1748 | ||
1749 | /***************************************************************************** | |
1750 | * parse_memop: parse a memory operand | |
1751 | * | |
1752 | * This routine is based on the observation that the 4 mode bits of the | |
1753 | * MEMB format, taken individually, have fairly consistent meaning: | |
1754 | * | |
1755 | * M3 (bit 13): 1 if displacement is present (D_BIT) | |
1756 | * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT) | |
1757 | * M1 (bit 11): 1 if index is present (I_BIT) | |
1758 | * M0 (bit 10): 1 if abase is present (A_BIT) | |
1759 | * | |
1760 | * So we parse the memory operand and set bits in the mode as we find | |
1761 | * things. Then at the end, if we go to MEMB format, we need only set | |
1762 | * the MEMB bit (M2) and our mode is built for us. | |
1763 | * | |
1764 | * Unfortunately, I said "fairly consistent". The exceptions: | |
1765 | * | |
1766 | * DBIA | |
1767 | * 0100 Would seem illegal, but means "abase-only". | |
1768 | * | |
1769 | * 0101 Would seem to mean "abase-only" -- it means IP-relative. | |
1770 | * Must be converted to 0100. | |
1771 | * | |
1772 | * 0110 Would seem to mean "index-only", but is reserved. | |
1773 | * We turn on the D bit and provide a 0 displacement. | |
1774 | * | |
1775 | * The other thing to observe is that we parse from the right, peeling | |
1776 | * things * off as we go: first any index spec, then any abase, then | |
1777 | * the displacement. | |
1778 | * | |
1779 | **************************************************************************** */ | |
1780 | static | |
a39116f1 RP |
1781 | void |
1782 | parse_memop(memP, argP, optype) | |
1783 | memS *memP; /* Where to put the results */ | |
1784 | char *argP; /* Text of the operand to be parsed */ | |
1785 | int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */ | |
fecd2382 RP |
1786 | { |
1787 | char *indexP; /* Pointer to index specification with "[]" removed */ | |
1788 | char *p; /* Temp char pointer */ | |
1789 | char iprel_flag;/* True if this is an IP-relative operand */ | |
1790 | int regnum; /* Register number */ | |
1791 | int scale; /* Scale factor: 1,2,4,8, or 16. Later converted | |
1792 | * to internal format (0,1,2,3,4 respectively). | |
1793 | */ | |
1794 | int mode; /* MEMB mode bits */ | |
1795 | int *intP; /* Pointer to register number */ | |
a39116f1 | 1796 | |
fecd2382 RP |
1797 | /* The following table contains the default scale factors for each |
1798 | * type of memory instruction. It is accessed using (optype-MEM1) | |
1799 | * as an index -- thus it assumes the 'optype' constants are assigned | |
1800 | * consecutive values, in the order they appear in this table | |
1801 | */ | |
1802 | static int def_scale[] = { | |
1803 | 1, /* MEM1 */ | |
1804 | 2, /* MEM2 */ | |
1805 | 4, /* MEM4 */ | |
1806 | 8, /* MEM8 */ | |
1807 | -1, /* MEM12 -- no valid default */ | |
1808 | 16 /* MEM16 */ | |
a39116f1 RP |
1809 | }; |
1810 | ||
1811 | ||
fecd2382 | 1812 | iprel_flag = mode = 0; |
a39116f1 | 1813 | |
fecd2382 RP |
1814 | /* Any index present? */ |
1815 | indexP = get_ispec(argP); | |
1816 | if (indexP) { | |
1817 | p = strchr(indexP, '*'); | |
1818 | if (p == NULL) { | |
1819 | /* No explicit scale -- use default for this | |
1820 | *instruction type. | |
1821 | */ | |
1822 | scale = def_scale[ optype - MEM1 ]; | |
1823 | } else { | |
1824 | *p++ = '\0'; /* Eliminate '*' */ | |
a39116f1 | 1825 | |
fecd2382 RP |
1826 | /* Now indexP->a '\0'-terminated register name, |
1827 | * and p->a scale factor. | |
1828 | */ | |
a39116f1 | 1829 | |
fecd2382 RP |
1830 | if (!strcmp(p,"16")){ |
1831 | scale = 16; | |
1832 | } else if (strchr("1248",*p) && (p[1] == '\0')){ | |
1833 | scale = *p - '0'; | |
1834 | } else { | |
1835 | scale = -1; | |
1836 | } | |
1837 | } | |
a39116f1 | 1838 | |
fecd2382 RP |
1839 | regnum = get_regnum(indexP); /* Get index reg. # */ |
1840 | if (!IS_RG_REG(regnum)){ | |
1841 | as_bad("invalid index register"); | |
1842 | return; | |
1843 | } | |
a39116f1 | 1844 | |
fecd2382 RP |
1845 | /* Convert scale to its binary encoding */ |
1846 | switch (scale){ | |
1847 | case 1: scale = 0 << 7; break; | |
1848 | case 2: scale = 1 << 7; break; | |
1849 | case 4: scale = 2 << 7; break; | |
1850 | case 8: scale = 3 << 7; break; | |
1851 | case 16: scale = 4 << 7; break; | |
1852 | default: as_bad("invalid scale factor"); return; | |
1853 | }; | |
a39116f1 | 1854 | |
fecd2382 RP |
1855 | memP->opcode |= scale | regnum; /* Set index bits in opcode */ |
1856 | mode |= I_BIT; /* Found a valid index spec */ | |
1857 | } | |
a39116f1 | 1858 | |
fecd2382 RP |
1859 | /* Any abase (Register Indirect) specification present? */ |
1860 | if ((p = strrchr(argP,'(')) != NULL) { | |
1861 | /* "(" is there -- does it start a legal abase spec? | |
1862 | * (If not it could be part of a displacement expression.) | |
1863 | */ | |
1864 | intP = (int *) hash_find(areg_hash, p); | |
1865 | if (intP != NULL){ | |
1866 | /* Got an abase here */ | |
1867 | regnum = *intP; | |
1868 | *p = '\0'; /* discard register spec */ | |
1869 | if (regnum == IPREL){ | |
1870 | /* We have to specialcase ip-rel mode */ | |
1871 | iprel_flag = 1; | |
1872 | } else { | |
1873 | memP->opcode |= regnum << 14; | |
1874 | mode |= A_BIT; | |
1875 | } | |
1876 | } | |
1877 | } | |
a39116f1 | 1878 | |
fecd2382 RP |
1879 | /* Any expression present? */ |
1880 | memP->e = argP; | |
1881 | if (*argP != '\0'){ | |
1882 | mode |= D_BIT; | |
1883 | } | |
a39116f1 | 1884 | |
fecd2382 RP |
1885 | /* Special-case ip-relative addressing */ |
1886 | if (iprel_flag){ | |
1887 | if (mode & I_BIT){ | |
1888 | syntax(); | |
1889 | } else { | |
1890 | memP->opcode |= 5 << 10; /* IP-relative mode */ | |
1891 | memP->disp = 32; | |
1892 | } | |
1893 | return; | |
1894 | } | |
a39116f1 | 1895 | |
fecd2382 RP |
1896 | /* Handle all other modes */ |
1897 | switch (mode){ | |
1898 | case D_BIT | A_BIT: | |
1899 | /* Go with MEMA instruction format for now (grow to MEMB later | |
1900 | * if 12 bits is not enough for the displacement). | |
1901 | * MEMA format has a single mode bit: set it to indicate | |
1902 | * that abase is present. | |
1903 | */ | |
1904 | memP->opcode |= MEMA_ABASE; | |
1905 | memP->disp = 12; | |
1906 | break; | |
a39116f1 | 1907 | |
fecd2382 RP |
1908 | case D_BIT: |
1909 | /* Go with MEMA instruction format for now (grow to MEMB later | |
1910 | * if 12 bits is not enough for the displacement). | |
1911 | */ | |
1912 | memP->disp = 12; | |
1913 | break; | |
a39116f1 | 1914 | |
fecd2382 RP |
1915 | case A_BIT: |
1916 | /* For some reason, the bit string for this mode is not | |
1917 | * consistent: it should be 0 (exclusive of the MEMB bit), | |
1918 | * so we set it "by hand" here. | |
1919 | */ | |
1920 | memP->opcode |= MEMB_BIT; | |
1921 | break; | |
a39116f1 | 1922 | |
fecd2382 RP |
1923 | case A_BIT | I_BIT: |
1924 | /* set MEMB bit in mode, and OR in mode bits */ | |
1925 | memP->opcode |= mode | MEMB_BIT; | |
1926 | break; | |
a39116f1 | 1927 | |
fecd2382 RP |
1928 | case I_BIT: |
1929 | /* Treat missing displacement as displacement of 0 */ | |
1930 | mode |= D_BIT; | |
1931 | /*********************** | |
1932 | * Fall into next case * | |
1933 | ********************** */ | |
1934 | case D_BIT | A_BIT | I_BIT: | |
1935 | case D_BIT | I_BIT: | |
1936 | /* set MEMB bit in mode, and OR in mode bits */ | |
1937 | memP->opcode |= mode | MEMB_BIT; | |
1938 | memP->disp = 32; | |
1939 | break; | |
a39116f1 | 1940 | |
fecd2382 RP |
1941 | default: |
1942 | syntax(); | |
1943 | break; | |
1944 | } | |
1945 | } | |
1946 | ||
1947 | /***************************************************************************** | |
1948 | * parse_po: parse machine-dependent pseudo-op | |
1949 | * | |
1950 | * This is a top-level routine for machine-dependent pseudo-ops. It slurps | |
1951 | * up the rest of the input line, breaks out the individual arguments, | |
1952 | * and dispatches them to the correct handler. | |
1953 | **************************************************************************** */ | |
1954 | static | |
a39116f1 RP |
1955 | void |
1956 | parse_po(po_num) | |
1957 | int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */ | |
fecd2382 RP |
1958 | { |
1959 | char *args[4]; /* Pointers operands, with no embedded whitespace. | |
1960 | * arg[0] unused. | |
1961 | * arg[1-3]->operands | |
1962 | */ | |
1963 | int n_ops; /* Number of operands */ | |
1964 | char *p; /* Pointer to beginning of unparsed argument string */ | |
1965 | char eol; /* Character that indicated end of line */ | |
a39116f1 | 1966 | |
fecd2382 | 1967 | extern char is_end_of_line[]; |
a39116f1 | 1968 | |
fecd2382 RP |
1969 | /* Advance input pointer to end of line. */ |
1970 | p = input_line_pointer; | |
1971 | while (!is_end_of_line[ *input_line_pointer ]){ | |
1972 | input_line_pointer++; | |
1973 | } | |
1974 | eol = *input_line_pointer; /* Save end-of-line char */ | |
1975 | *input_line_pointer = '\0'; /* Terminate argument list */ | |
a39116f1 | 1976 | |
fecd2382 RP |
1977 | /* Parse out operands */ |
1978 | n_ops = get_args(p, args); | |
1979 | if (n_ops == -1){ | |
1980 | return; | |
1981 | } | |
a39116f1 | 1982 | |
fecd2382 RP |
1983 | /* Dispatch to correct handler */ |
1984 | switch(po_num){ | |
1985 | case S_SYSPROC: s_sysproc(n_ops, args); break; | |
1986 | case S_LEAFPROC: s_leafproc(n_ops, args); break; | |
1987 | default: BAD_CASE(po_num); break; | |
1988 | } | |
a39116f1 | 1989 | |
fecd2382 RP |
1990 | /* Restore eol, so line numbers get updated correctly. Base assembler |
1991 | * assumes we leave input pointer pointing at char following the eol. | |
1992 | */ | |
1993 | *input_line_pointer++ = eol; | |
1994 | } | |
1995 | ||
1996 | /***************************************************************************** | |
1997 | * parse_regop: parse a register operand. | |
1998 | * | |
1999 | * In case of illegal operand, issue a message and return some valid | |
2000 | * information so instruction processing can continue. | |
2001 | **************************************************************************** */ | |
2002 | static | |
a39116f1 RP |
2003 | void |
2004 | parse_regop(regopP, optext, opdesc) | |
2005 | struct regop *regopP; /* Where to put description of register operand */ | |
2006 | char *optext; /* Text of operand */ | |
2007 | char opdesc; /* Descriptor byte: what's legal for this operand */ | |
fecd2382 RP |
2008 | { |
2009 | int n; /* Register number */ | |
2010 | expressionS e; /* Parsed expression */ | |
a39116f1 | 2011 | |
fecd2382 RP |
2012 | /* See if operand is a register */ |
2013 | n = get_regnum(optext); | |
2014 | if (n >= 0){ | |
2015 | if (IS_RG_REG(n)){ | |
2016 | /* global or local register */ | |
2017 | if (!REG_ALIGN(opdesc,n)){ | |
2018 | as_bad("unaligned register"); | |
2019 | } | |
2020 | regopP->n = n; | |
2021 | regopP->mode = 0; | |
2022 | regopP->special = 0; | |
2023 | return; | |
2024 | } else if (IS_FP_REG(n) && FP_OK(opdesc)){ | |
2025 | /* Floating point register, and it's allowed */ | |
2026 | regopP->n = n - FP0; | |
2027 | regopP->mode = 1; | |
2028 | regopP->special = 0; | |
2029 | return; | |
2030 | } else if (IS_SF_REG(n) && SFR_OK(opdesc)){ | |
2031 | /* Special-function register, and it's allowed */ | |
2032 | regopP->n = n - SF0; | |
2033 | regopP->mode = 0; | |
2034 | regopP->special = 1; | |
2035 | if (!targ_has_sfr(regopP->n)){ | |
2036 | as_bad("no such sfr in this architecture"); | |
2037 | } | |
2038 | return; | |
2039 | } | |
2040 | } else if (LIT_OK(opdesc)){ | |
2041 | /* | |
2042 | * How about a literal? | |
2043 | */ | |
2044 | regopP->mode = 1; | |
2045 | regopP->special = 0; | |
2046 | if (FP_OK(opdesc)){ /* floating point literal acceptable */ | |
2047 | /* Skip over 0f, 0d, or 0e prefix */ | |
2048 | if ( (optext[0] == '0') | |
a39116f1 RP |
2049 | && (optext[1] >= 'd') |
2050 | && (optext[1] <= 'f') ){ | |
fecd2382 RP |
2051 | optext += 2; |
2052 | } | |
a39116f1 | 2053 | |
fecd2382 RP |
2054 | if (!strcmp(optext,"0.0") || !strcmp(optext,"0") ){ |
2055 | regopP->n = 0x10; | |
2056 | return; | |
2057 | } | |
2058 | if (!strcmp(optext,"1.0") || !strcmp(optext,"1") ){ | |
2059 | regopP->n = 0x16; | |
2060 | return; | |
2061 | } | |
a39116f1 | 2062 | |
fecd2382 RP |
2063 | } else { /* fixed point literal acceptable */ |
2064 | if ((parse_expr(optext,&e) != SEG_ABSOLUTE) | |
a39116f1 | 2065 | || (offs(e) < 0) || (offs(e) > 31)){ |
fecd2382 RP |
2066 | as_bad("illegal literal"); |
2067 | offs(e) = 0; | |
2068 | } | |
2069 | regopP->n = offs(e); | |
2070 | return; | |
2071 | } | |
2072 | } | |
a39116f1 | 2073 | |
fecd2382 RP |
2074 | /* Nothing worked */ |
2075 | syntax(); | |
2076 | regopP->mode = 0; /* Register r0 is always a good one */ | |
2077 | regopP->n = 0; | |
2078 | regopP->special = 0; | |
2079 | } /* parse_regop() */ | |
2080 | ||
2081 | /***************************************************************************** | |
2082 | * reg_fmt: generate a REG-format instruction | |
2083 | * | |
2084 | **************************************************************************** */ | |
2085 | static void reg_fmt(args, oP) | |
a39116f1 RP |
2086 | char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */ |
2087 | struct i960_opcode *oP; /* Pointer to description of instruction */ | |
fecd2382 RP |
2088 | { |
2089 | long instr; /* Binary to be output */ | |
2090 | struct regop regop; /* Description of register operand */ | |
2091 | int n_ops; /* Number of operands */ | |
a39116f1 RP |
2092 | |
2093 | ||
fecd2382 RP |
2094 | instr = oP->opcode; |
2095 | n_ops = oP->num_ops; | |
a39116f1 | 2096 | |
fecd2382 RP |
2097 | if (n_ops >= 1){ |
2098 | parse_regop(®op, args[1], oP->operand[0]); | |
a39116f1 | 2099 | |
fecd2382 RP |
2100 | if ((n_ops == 1) && !(instr & M3)){ |
2101 | /* 1-operand instruction in which the dst field should | |
2102 | * be used (instead of src1). | |
2103 | */ | |
2104 | regop.n <<= 19; | |
2105 | if (regop.special){ | |
2106 | regop.mode = regop.special; | |
2107 | } | |
2108 | regop.mode <<= 13; | |
2109 | regop.special = 0; | |
2110 | } else { | |
2111 | /* regop.n goes in bit 0, needs no shifting */ | |
2112 | regop.mode <<= 11; | |
2113 | regop.special <<= 5; | |
2114 | } | |
2115 | instr |= regop.n | regop.mode | regop.special; | |
2116 | } | |
a39116f1 | 2117 | |
fecd2382 RP |
2118 | if (n_ops >= 2) { |
2119 | parse_regop(®op, args[2], oP->operand[1]); | |
a39116f1 | 2120 | |
fecd2382 RP |
2121 | if ((n_ops == 2) && !(instr & M3)){ |
2122 | /* 2-operand instruction in which the dst field should | |
2123 | * be used instead of src2). | |
2124 | */ | |
2125 | regop.n <<= 19; | |
2126 | if (regop.special){ | |
2127 | regop.mode = regop.special; | |
2128 | } | |
2129 | regop.mode <<= 13; | |
2130 | regop.special = 0; | |
2131 | } else { | |
2132 | regop.n <<= 14; | |
2133 | regop.mode <<= 12; | |
2134 | regop.special <<= 6; | |
2135 | } | |
2136 | instr |= regop.n | regop.mode | regop.special; | |
2137 | } | |
2138 | if (n_ops == 3){ | |
2139 | parse_regop(®op, args[3], oP->operand[2]); | |
2140 | if (regop.special){ | |
2141 | regop.mode = regop.special; | |
2142 | } | |
2143 | instr |= (regop.n <<= 19) | (regop.mode <<= 13); | |
2144 | } | |
2145 | emit(instr); | |
2146 | } | |
2147 | ||
2148 | ||
2149 | /***************************************************************************** | |
2150 | * relax_cobr: | |
2151 | * Replace cobr instruction in a code fragment with equivalent branch and | |
2152 | * compare instructions, so it can reach beyond a 13-bit displacement. | |
2153 | * Set up an address fix/relocation for the new branch instruction. | |
2154 | * | |
2155 | **************************************************************************** */ | |
2156 | ||
2157 | /* This "conditional jump" table maps cobr instructions into equivalent | |
2158 | * compare and branch opcodes. | |
2159 | */ | |
2160 | static | |
a39116f1 RP |
2161 | struct { |
2162 | long compare; | |
2163 | long branch; | |
2164 | } coj[] = { /* COBR OPCODE: */ | |
2165 | CHKBIT, BNO, /* 0x30 - bbc */ | |
2166 | CMPO, BG, /* 0x31 - cmpobg */ | |
2167 | CMPO, BE, /* 0x32 - cmpobe */ | |
2168 | CMPO, BGE, /* 0x33 - cmpobge */ | |
2169 | CMPO, BL, /* 0x34 - cmpobl */ | |
2170 | CMPO, BNE, /* 0x35 - cmpobne */ | |
2171 | CMPO, BLE, /* 0x36 - cmpoble */ | |
2172 | CHKBIT, BO, /* 0x37 - bbs */ | |
2173 | CMPI, BNO, /* 0x38 - cmpibno */ | |
2174 | CMPI, BG, /* 0x39 - cmpibg */ | |
2175 | CMPI, BE, /* 0x3a - cmpibe */ | |
2176 | CMPI, BGE, /* 0x3b - cmpibge */ | |
2177 | CMPI, BL, /* 0x3c - cmpibl */ | |
2178 | CMPI, BNE, /* 0x3d - cmpibne */ | |
2179 | CMPI, BLE, /* 0x3e - cmpible */ | |
2180 | CMPI, BO, /* 0x3f - cmpibo */ | |
2181 | }; | |
fecd2382 RP |
2182 | |
2183 | static | |
a39116f1 RP |
2184 | void |
2185 | relax_cobr(fragP) | |
2186 | register fragS *fragP; /* fragP->fr_opcode is assumed to point to | |
2187 | * the cobr instruction, which comes at the | |
2188 | * end of the code fragment. | |
2189 | */ | |
fecd2382 RP |
2190 | { |
2191 | int opcode, src1, src2, m1, s2; | |
a39116f1 | 2192 | /* Bit fields from cobr instruction */ |
fecd2382 RP |
2193 | long bp_bits; /* Branch prediction bits from cobr instruction */ |
2194 | long instr; /* A single i960 instruction */ | |
2195 | char *iP; /*->instruction to be replaced */ | |
2196 | fixS *fixP; /* Relocation that can be done at assembly time */ | |
a39116f1 | 2197 | |
fecd2382 RP |
2198 | /* PICK UP & PARSE COBR INSTRUCTION */ |
2199 | iP = fragP->fr_opcode; | |
2200 | instr = md_chars_to_number(iP, 4); | |
2201 | opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */ | |
2202 | src1 = (instr >> 19) & 0x1f; | |
2203 | m1 = (instr >> 13) & 1; | |
2204 | s2 = instr & 1; | |
2205 | src2 = (instr >> 14) & 0x1f; | |
2206 | bp_bits= instr & BP_MASK; | |
a39116f1 | 2207 | |
fecd2382 RP |
2208 | /* GENERATE AND OUTPUT COMPARE INSTRUCTION */ |
2209 | instr = coj[opcode].compare | |
a39116f1 | 2210 | | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); |
fecd2382 | 2211 | md_number_to_chars(iP, instr, 4); |
a39116f1 | 2212 | |
fecd2382 RP |
2213 | /* OUTPUT BRANCH INSTRUCTION */ |
2214 | md_number_to_chars(iP+4, coj[opcode].branch | bp_bits, 4); | |
a39116f1 | 2215 | |
fecd2382 RP |
2216 | /* SET UP ADDRESS FIXUP/RELOCATION */ |
2217 | fixP = fix_new(fragP, | |
2218 | iP+4 - fragP->fr_literal, | |
2219 | 4, | |
2220 | fragP->fr_symbol, | |
2221 | 0, | |
2222 | fragP->fr_offset, | |
2223 | 1, | |
2224 | 0); | |
a39116f1 | 2225 | |
fecd2382 | 2226 | fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */ |
a39116f1 | 2227 | |
fecd2382 RP |
2228 | fragP->fr_fix += 4; |
2229 | frag_wane(fragP); | |
2230 | } | |
2231 | ||
2232 | ||
2233 | /***************************************************************************** | |
2234 | * reloc_callj: Relocate a 'callj' instruction | |
2235 | * | |
2236 | * This is a "non-(GNU)-standard" machine-dependent hook. The base | |
2237 | * assembler calls it when it decides it can relocate an address at | |
2238 | * assembly time instead of emitting a relocation directive. | |
2239 | * | |
2240 | * Check to see if the relocation involves a 'callj' instruction to a: | |
2241 | * sysproc: Replace the default 'call' instruction with a 'calls' | |
2242 | * leafproc: Replace the default 'call' instruction with a 'bal'. | |
2243 | * other proc: Do nothing. | |
2244 | * | |
2245 | * See b.out.h for details on the 'n_other' field in a symbol structure. | |
2246 | * | |
2247 | * IMPORTANT!: | |
2248 | * Assumes the caller has already figured out, in the case of a leafproc, | |
2249 | * to use the 'bal' entry point, and has substituted that symbol into the | |
2250 | * passed fixup structure. | |
2251 | * | |
2252 | **************************************************************************** */ | |
2253 | void reloc_callj(fixP) | |
2254 | fixS *fixP; /* Relocation that can be done at assembly time */ | |
2255 | { | |
2256 | char *where; /*->the binary for the instruction being relocated */ | |
a39116f1 | 2257 | |
fecd2382 RP |
2258 | if (!fixP->fx_callj) { |
2259 | return; | |
2260 | } /* This wasn't a callj instruction in the first place */ | |
09952cd9 | 2261 | |
fecd2382 | 2262 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
a39116f1 | 2263 | |
fecd2382 RP |
2264 | if (TC_S_IS_SYSPROC(fixP->fx_addsy)) { |
2265 | /* Symbol is a .sysproc: replace 'call' with 'calls'. | |
2266 | * System procedure number is (other-1). | |
2267 | */ | |
2268 | md_number_to_chars(where, CALLS|TC_S_GET_SYSPROC(fixP->fx_addsy), 4); | |
a39116f1 | 2269 | |
fecd2382 RP |
2270 | /* Nothing else needs to be done for this instruction. |
2271 | * Make sure 'md_number_to_field()' will perform a no-op. | |
2272 | */ | |
2273 | fixP->fx_bit_fixP = (bit_fixS *) 1; | |
a39116f1 | 2274 | |
fecd2382 RP |
2275 | } else if (TC_S_IS_CALLNAME(fixP->fx_addsy)) { |
2276 | /* Should not happen: see block comment above */ | |
2277 | as_fatal("Trying to 'bal' to %s", S_GET_NAME(fixP->fx_addsy)); | |
a39116f1 | 2278 | |
fecd2382 RP |
2279 | } else if (TC_S_IS_BALNAME(fixP->fx_addsy)) { |
2280 | /* Replace 'call' with 'bal'; both instructions have | |
2281 | * the same format, so calling code should complete | |
2282 | * relocation as if nothing happened here. | |
2283 | */ | |
2284 | md_number_to_chars(where, BAL, 4); | |
2285 | } else if (TC_S_IS_BADPROC(fixP->fx_addsy)) { | |
2286 | as_bad("Looks like a proc, but can't tell what kind.\n"); | |
2287 | } /* switch on proc type */ | |
2288 | ||
2289 | /* else Symbol is neither a sysproc nor a leafproc */ | |
2290 | ||
2291 | return; | |
2292 | } /* reloc_callj() */ | |
2293 | ||
2294 | ||
2295 | /***************************************************************************** | |
2296 | * s_leafproc: process .leafproc pseudo-op | |
2297 | * | |
2298 | * .leafproc takes two arguments, the second one is optional: | |
2299 | * arg[1]: name of 'call' entry point to leaf procedure | |
2300 | * arg[2]: name of 'bal' entry point to leaf procedure | |
2301 | * | |
2302 | * If the two arguments are identical, or if the second one is missing, | |
2303 | * the first argument is taken to be the 'bal' entry point. | |
2304 | * | |
2305 | * If there are 2 distinct arguments, we must make sure that the 'bal' | |
2306 | * entry point immediately follows the 'call' entry point in the linked | |
2307 | * list of symbols. | |
2308 | * | |
2309 | **************************************************************************** */ | |
2310 | static void s_leafproc(n_ops, args) | |
2311 | int n_ops; /* Number of operands */ | |
2312 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ | |
2313 | { | |
2314 | symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */ | |
2315 | symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */ | |
a39116f1 | 2316 | |
fecd2382 RP |
2317 | if ((n_ops != 1) && (n_ops != 2)) { |
2318 | as_bad("should have 1 or 2 operands"); | |
2319 | return; | |
2320 | } /* Check number of arguments */ | |
a39116f1 | 2321 | |
fecd2382 RP |
2322 | /* Find or create symbol for 'call' entry point. */ |
2323 | callP = symbol_find_or_make(args[1]); | |
a39116f1 | 2324 | |
fecd2382 RP |
2325 | if (TC_S_IS_CALLNAME(callP)) { |
2326 | as_warn("Redefining leafproc %s", S_GET_NAME(callP)); | |
2327 | } /* is leafproc */ | |
a39116f1 | 2328 | |
fecd2382 RP |
2329 | /* If that was the only argument, use it as the 'bal' entry point. |
2330 | * Otherwise, mark it as the 'call' entry point and find or create | |
2331 | * another symbol for the 'bal' entry point. | |
2332 | */ | |
2333 | if ((n_ops == 1) || !strcmp(args[1],args[2])) { | |
2334 | TC_S_FORCE_TO_BALNAME(callP); | |
a39116f1 | 2335 | |
fecd2382 RP |
2336 | } else { |
2337 | TC_S_FORCE_TO_CALLNAME(callP); | |
a39116f1 | 2338 | |
fecd2382 RP |
2339 | balP = symbol_find_or_make(args[2]); |
2340 | if (TC_S_IS_CALLNAME(balP)) { | |
2341 | as_warn("Redefining leafproc %s", S_GET_NAME(balP)); | |
2342 | } | |
2343 | TC_S_FORCE_TO_BALNAME(balP); | |
a39116f1 | 2344 | |
fecd2382 RP |
2345 | tc_set_bal_of_call(callP, balP); |
2346 | } /* if only one arg, or the args are the same */ | |
a39116f1 | 2347 | |
fecd2382 RP |
2348 | return; |
2349 | } /* s_leafproc() */ | |
2350 | ||
2351 | ||
2352 | /* | |
2353 | * s_sysproc: process .sysproc pseudo-op | |
2354 | * | |
2355 | * .sysproc takes two arguments: | |
2356 | * arg[1]: name of entry point to system procedure | |
2357 | * arg[2]: 'entry_num' (index) of system procedure in the range | |
2358 | * [0,31] inclusive. | |
2359 | * | |
2360 | * For [ab].out, we store the 'entrynum' in the 'n_other' field of | |
2361 | * the symbol. Since that entry is normally 0, we bias 'entrynum' | |
2362 | * by adding 1 to it. It must be unbiased before it is used. | |
2363 | */ | |
2364 | static void s_sysproc(n_ops, args) | |
2365 | int n_ops; /* Number of operands */ | |
2366 | char *args[]; /* args[1]->1st operand, args[2]->2nd operand */ | |
2367 | { | |
2368 | expressionS exp; | |
2369 | symbolS *symP; | |
a39116f1 | 2370 | |
fecd2382 RP |
2371 | if (n_ops != 2) { |
2372 | as_bad("should have two operands"); | |
2373 | return; | |
2374 | } /* bad arg count */ | |
a39116f1 | 2375 | |
fecd2382 RP |
2376 | /* Parse "entry_num" argument and check it for validity. */ |
2377 | if ((parse_expr(args[2],&exp) != SEG_ABSOLUTE) | |
2378 | || (offs(exp) < 0) | |
2379 | || (offs(exp) > 31)) { | |
2380 | as_bad("'entry_num' must be absolute number in [0,31]"); | |
2381 | return; | |
2382 | } | |
a39116f1 | 2383 | |
fecd2382 RP |
2384 | /* Find/make symbol and stick entry number (biased by +1) into it */ |
2385 | symP = symbol_find_or_make(args[1]); | |
a39116f1 | 2386 | |
fecd2382 RP |
2387 | if (TC_S_IS_SYSPROC(symP)) { |
2388 | as_warn("Redefining entrynum for sysproc %s", S_GET_NAME(symP)); | |
2389 | } /* redefining */ | |
a39116f1 | 2390 | |
fecd2382 RP |
2391 | TC_S_SET_SYSPROC(symP, offs(exp)); /* encode entry number */ |
2392 | TC_S_FORCE_TO_SYSPROC(symP); | |
a39116f1 | 2393 | |
fecd2382 RP |
2394 | return; |
2395 | } /* s_sysproc() */ | |
2396 | ||
2397 | ||
2398 | /***************************************************************************** | |
2399 | * shift_ok: | |
2400 | * Determine if a "shlo" instruction can be used to implement a "ldconst". | |
2401 | * This means that some number X < 32 can be shifted left to produce the | |
2402 | * constant of interest. | |
2403 | * | |
2404 | * Return the shift count, or 0 if we can't do it. | |
2405 | * Caller calculates X by shifting original constant right 'shift' places. | |
2406 | * | |
2407 | **************************************************************************** */ | |
2408 | static | |
a39116f1 RP |
2409 | int |
2410 | shift_ok(n) | |
2411 | int n; /* The constant of interest */ | |
fecd2382 RP |
2412 | { |
2413 | int shift; /* The shift count */ | |
a39116f1 | 2414 | |
fecd2382 RP |
2415 | if (n <= 0){ |
2416 | /* Can't do it for negative numbers */ | |
2417 | return 0; | |
2418 | } | |
a39116f1 | 2419 | |
fecd2382 RP |
2420 | /* Shift 'n' right until a 1 is about to be lost */ |
2421 | for (shift = 0; (n & 1) == 0; shift++){ | |
2422 | n >>= 1; | |
2423 | } | |
a39116f1 | 2424 | |
fecd2382 RP |
2425 | if (n >= 32){ |
2426 | return 0; | |
2427 | } | |
2428 | return shift; | |
2429 | } | |
2430 | ||
2431 | ||
2432 | /***************************************************************************** | |
2433 | * syntax: issue syntax error | |
2434 | * | |
2435 | **************************************************************************** */ | |
2436 | static void syntax() { | |
2437 | as_bad("syntax error"); | |
2438 | } /* syntax() */ | |
2439 | ||
2440 | ||
2441 | /***************************************************************************** | |
2442 | * targ_has_sfr: | |
2443 | * Return TRUE iff the target architecture supports the specified | |
2444 | * special-function register (sfr). | |
2445 | * | |
2446 | **************************************************************************** */ | |
2447 | static | |
a39116f1 RP |
2448 | int |
2449 | targ_has_sfr(n) | |
2450 | int n; /* Number (0-31) of sfr */ | |
fecd2382 RP |
2451 | { |
2452 | switch (architecture){ | |
2453 | case ARCH_KA: | |
2454 | case ARCH_KB: | |
2455 | case ARCH_MC: | |
2456 | return 0; | |
2457 | case ARCH_CA: | |
2458 | default: | |
2459 | return ((0<=n) && (n<=2)); | |
2460 | } | |
2461 | } | |
2462 | ||
2463 | ||
2464 | /***************************************************************************** | |
2465 | * targ_has_iclass: | |
2466 | * Return TRUE iff the target architecture supports the indicated | |
2467 | * class of instructions. | |
2468 | * | |
2469 | **************************************************************************** */ | |
2470 | static | |
a39116f1 RP |
2471 | int |
2472 | targ_has_iclass(ic) | |
2473 | int ic; /* Instruction class; one of: | |
2474 | * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM | |
2475 | */ | |
fecd2382 RP |
2476 | { |
2477 | iclasses_seen |= ic; | |
2478 | switch (architecture){ | |
2479 | case ARCH_KA: return ic & (I_BASE | I_KX); | |
2480 | case ARCH_KB: return ic & (I_BASE | I_KX | I_FP | I_DEC); | |
2481 | case ARCH_MC: return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL); | |
2482 | case ARCH_CA: return ic & (I_BASE | I_CX | I_CASIM); | |
2483 | default: | |
2484 | if ((iclasses_seen & (I_KX|I_FP|I_DEC|I_MIL)) | |
a39116f1 | 2485 | && (iclasses_seen & I_CX)){ |
fecd2382 RP |
2486 | as_warn("architecture of opcode conflicts with that of earlier instruction(s)"); |
2487 | iclasses_seen &= ~ic; | |
2488 | } | |
2489 | return 1; | |
2490 | } | |
2491 | } | |
2492 | ||
2493 | ||
2494 | /* Parse an operand that is machine-specific. | |
2495 | We just return without modifying the expression if we have nothing | |
2496 | to do. */ | |
2497 | ||
2498 | /* ARGSUSED */ | |
2499 | void | |
a39116f1 RP |
2500 | md_operand (expressionP) |
2501 | expressionS *expressionP; | |
fecd2382 RP |
2502 | { |
2503 | } | |
2504 | ||
2505 | /* We have no need to default values of symbols. */ | |
2506 | ||
2507 | /* ARGSUSED */ | |
2508 | symbolS *md_undefined_symbol(name) | |
2509 | char *name; | |
2510 | { | |
2511 | return 0; | |
2512 | } /* md_undefined_symbol() */ | |
2513 | ||
2514 | /* Exactly what point is a PC-relative offset relative TO? | |
2515 | On the i960, they're relative to the address of the instruction, | |
2516 | which we have set up as the address of the fixup too. */ | |
2517 | long | |
a39116f1 RP |
2518 | md_pcrel_from (fixP) |
2519 | fixS *fixP; | |
fecd2382 | 2520 | { |
a39116f1 | 2521 | return fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
2522 | } |
2523 | ||
2524 | void | |
a39116f1 RP |
2525 | md_apply_fix(fixP, val) |
2526 | fixS *fixP; | |
2527 | long val; | |
fecd2382 RP |
2528 | { |
2529 | char *place = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a39116f1 | 2530 | |
fecd2382 | 2531 | if (!fixP->fx_bit_fixP) { |
a39116f1 | 2532 | |
fecd2382 RP |
2533 | switch (fixP->fx_im_disp) { |
2534 | case 0: | |
2535 | fixP->fx_addnumber = val; | |
2536 | md_number_to_imm(place, val, fixP->fx_size, fixP); | |
2537 | break; | |
2538 | case 1: | |
2539 | md_number_to_disp(place, | |
a39116f1 RP |
2540 | fixP->fx_pcrel ? val + fixP->fx_pcrel_adjust : val, |
2541 | fixP->fx_size); | |
fecd2382 RP |
2542 | break; |
2543 | case 2: /* fix requested for .long .word etc */ | |
2544 | md_number_to_chars(place, val, fixP->fx_size); | |
2545 | break; | |
2546 | default: | |
2547 | as_fatal("Internal error in md_apply_fix() in file \"%s\"", __FILE__); | |
2548 | } /* OVE: maybe one ought to put _imm _disp _chars in one md-func */ | |
2549 | } else { | |
2550 | md_number_to_field(place, val, fixP->fx_bit_fixP); | |
2551 | } | |
a39116f1 | 2552 | |
fecd2382 RP |
2553 | return; |
2554 | } /* md_apply_fix() */ | |
2555 | ||
2556 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
a79c6033 RP |
2557 | void tc_bout_fix_to_chars(where, fixP, segment_address_in_file) |
2558 | char *where; | |
2559 | fixS *fixP; | |
2560 | relax_addressT segment_address_in_file; | |
fecd2382 | 2561 | { |
a79c6033 RP |
2562 | static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 }; |
2563 | struct relocation_info ri; | |
2564 | symbolS *symbolP; | |
2565 | ||
fecd2382 | 2566 | /* JF this is for paranoia */ |
542e1629 | 2567 | memset((char *)&ri, '\0', sizeof(ri)); |
09952cd9 KR |
2568 | symbolP = fixP->fx_addsy; |
2569 | know(symbolP != 0 || fixP->fx_r_type != NO_RELOC); | |
2570 | ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */ | |
a79c6033 RP |
2571 | /* These two 'cuz of NS32K */ |
2572 | ri.r_callj = fixP->fx_callj; | |
09952cd9 KR |
2573 | if(fixP->fx_bit_fixP) { |
2574 | ri.r_length = 1; | |
2575 | } | |
2576 | else { | |
2577 | ri.r_length = nbytes_r_length[fixP->fx_size]; | |
2578 | } | |
a79c6033 RP |
2579 | ri.r_pcrel = fixP->fx_pcrel; |
2580 | ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file; | |
2581 | ||
09952cd9 KR |
2582 | if (fixP->fx_r_type != NO_RELOC) |
2583 | { | |
2584 | switch (fixP->fx_r_type) | |
2585 | { | |
2586 | case rs_align: | |
2587 | ri.r_index = -2; | |
2588 | ri.r_pcrel = 1; | |
2589 | ri.r_length = fixP->fx_size - 1; | |
2590 | break; | |
2591 | case rs_org: | |
2592 | ri.r_index = -2; | |
2593 | ri.r_pcrel = 0; | |
2594 | break; | |
2595 | case rs_fill: | |
2596 | ri.r_index = -1; | |
2597 | break; | |
2598 | default: | |
2599 | abort (); | |
2600 | } | |
2601 | ri.r_extern = 0; | |
2602 | } | |
2603 | else if (linkrelax || !S_IS_DEFINED(symbolP)) { | |
a79c6033 RP |
2604 | ri.r_extern = 1; |
2605 | ri.r_index = symbolP->sy_number; | |
2606 | } else { | |
2607 | ri.r_extern = 0; | |
2608 | ri.r_index = S_GET_TYPE(symbolP); | |
fecd2382 | 2609 | } |
a79c6033 RP |
2610 | |
2611 | /* Output the relocation information in machine-dependent form. */ | |
2612 | md_ri_to_chars(where, &ri); | |
2613 | ||
2614 | return; | |
2615 | } /* tc_bout_fix_to_chars() */ | |
fecd2382 | 2616 | |
fecd2382 RP |
2617 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
2618 | ||
2619 | /* Align an address by rounding it up to the specified boundary. | |
2620 | */ | |
2621 | long md_section_align(seg, addr) | |
2622 | segT seg; | |
2623 | long addr; /* Address to be rounded up */ | |
2624 | { | |
2625 | return((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg])); | |
2626 | } /* md_section_align() */ | |
2627 | ||
2628 | #ifdef OBJ_COFF | |
2629 | void tc_headers_hook(headers) | |
2630 | object_headers *headers; | |
2631 | { | |
a39116f1 RP |
2632 | /* FIXME: remove this line */ /* unsigned short arch_flag = 0; */ |
2633 | ||
fecd2382 RP |
2634 | if (iclasses_seen == I_BASE){ |
2635 | headers->filehdr.f_flags |= F_I960CORE; | |
2636 | } else if (iclasses_seen & I_CX){ | |
2637 | headers->filehdr.f_flags |= F_I960CA; | |
2638 | } else if (iclasses_seen & I_MIL){ | |
2639 | headers->filehdr.f_flags |= F_I960MC; | |
2640 | } else if (iclasses_seen & (I_DEC|I_FP)){ | |
2641 | headers->filehdr.f_flags |= F_I960KB; | |
2642 | } else { | |
2643 | headers->filehdr.f_flags |= F_I960KA; | |
2644 | } /* set arch flag */ | |
a39116f1 | 2645 | |
fecd2382 RP |
2646 | if (flagseen['R']) { |
2647 | headers->filehdr.f_magic = I960RWMAGIC; | |
2648 | headers->aouthdr.magic = OMAGIC; | |
2649 | } else { | |
2650 | headers->filehdr.f_magic = I960ROMAGIC; | |
2651 | headers->aouthdr.magic = NMAGIC; | |
2652 | } /* set magic numbers */ | |
2653 | ||
2654 | return; | |
2655 | } /* tc_headers_hook() */ | |
2656 | #endif /* OBJ_COFF */ | |
2657 | ||
2658 | /* | |
2659 | * Things going on here: | |
2660 | * | |
2661 | * For bout, We need to assure a couple of simplifying | |
2662 | * assumptions about leafprocs for the linker: the leafproc | |
2663 | * entry symbols will be defined in the same assembly in | |
2664 | * which they're declared with the '.leafproc' directive; | |
2665 | * and if a leafproc has both 'call' and 'bal' entry points | |
2666 | * they are both global or both local. | |
2667 | * | |
2668 | * For coff, the call symbol has a second aux entry that | |
2669 | * contains the bal entry point. The bal symbol becomes a | |
2670 | * label. | |
2671 | * | |
2672 | * For coff representation, the call symbol has a second aux entry that | |
2673 | * contains the bal entry point. The bal symbol becomes a label. | |
2674 | * | |
2675 | */ | |
2676 | ||
2677 | void tc_crawl_symbol_chain(headers) | |
2678 | object_headers *headers; | |
2679 | { | |
2680 | symbolS *symbolP; | |
a39116f1 | 2681 | |
fecd2382 RP |
2682 | for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next(symbolP)) { |
2683 | #ifdef OBJ_COFF | |
2684 | if (TC_S_IS_SYSPROC(symbolP)) { | |
2685 | /* second aux entry already contains the sysproc number */ | |
2686 | S_SET_NUMBER_AUXILIARY(symbolP, 2); | |
2687 | S_SET_STORAGE_CLASS(symbolP, C_SCALL); | |
2688 | S_SET_DATA_TYPE(symbolP, S_GET_DATA_TYPE(symbolP) | (DT_FCN << N_BTSHFT)); | |
2689 | continue; | |
2690 | } /* rewrite sysproc */ | |
2691 | #endif /* OBJ_COFF */ | |
a39116f1 | 2692 | |
fecd2382 RP |
2693 | if (!TC_S_IS_BALNAME(symbolP) && !TC_S_IS_CALLNAME(symbolP)) { |
2694 | continue; | |
2695 | } /* Not a leafproc symbol */ | |
a39116f1 | 2696 | |
fecd2382 RP |
2697 | if (!S_IS_DEFINED(symbolP)) { |
2698 | as_bad("leafproc symbol '%s' undefined", S_GET_NAME(symbolP)); | |
2699 | } /* undefined leaf */ | |
a39116f1 | 2700 | |
fecd2382 RP |
2701 | if (TC_S_IS_CALLNAME(symbolP)) { |
2702 | symbolS *balP = tc_get_bal_of_call(symbolP); | |
2703 | if (S_IS_EXTERNAL(symbolP) != S_IS_EXTERNAL(balP)) { | |
2704 | S_SET_EXTERNAL(symbolP); | |
2705 | S_SET_EXTERNAL(balP); | |
2706 | as_warn("Warning: making leafproc entries %s and %s both global\n", | |
2707 | S_GET_NAME(symbolP), S_GET_NAME(balP)); | |
2708 | } /* externality mismatch */ | |
2709 | } /* if callname */ | |
2710 | } /* walk the symbol chain */ | |
a39116f1 | 2711 | |
fecd2382 RP |
2712 | return; |
2713 | } /* tc_crawl_symbol_chain() */ | |
2714 | ||
2715 | /* | |
2716 | * For aout or bout, the bal immediately follows the call. | |
2717 | * | |
2718 | * For coff, we cheat and store a pointer to the bal symbol | |
2719 | * in the second aux entry of the call. | |
2720 | */ | |
2721 | ||
2722 | void tc_set_bal_of_call(callP, balP) | |
2723 | symbolS *callP; | |
2724 | symbolS *balP; | |
2725 | { | |
2726 | know(TC_S_IS_CALLNAME(callP)); | |
2727 | know(TC_S_IS_BALNAME(balP)); | |
2728 | ||
2729 | #ifdef OBJ_COFF | |
a39116f1 | 2730 | |
fecd2382 RP |
2731 | callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP; |
2732 | S_SET_NUMBER_AUXILIARY(callP,2); | |
a39116f1 | 2733 | |
fecd2382 | 2734 | #elif defined(OBJ_AOUT) || defined(OBJ_BOUT) |
a39116f1 | 2735 | |
fecd2382 RP |
2736 | /* If the 'bal' entry doesn't immediately follow the 'call' |
2737 | * symbol, unlink it from the symbol list and re-insert it. | |
2738 | */ | |
2739 | if (symbol_next(callP) != balP) { | |
2740 | symbol_remove(balP, &symbol_rootP, &symbol_lastP); | |
2741 | symbol_append(balP, callP, &symbol_rootP, &symbol_lastP); | |
2742 | } /* if not in order */ | |
a39116f1 | 2743 | |
fecd2382 RP |
2744 | #else |
2745 | (as yet unwritten.); | |
2746 | #endif /* switch on OBJ_FORMAT */ | |
2747 | ||
2748 | return; | |
2749 | } /* tc_set_bal_of_call() */ | |
2750 | ||
2751 | char *_tc_get_bal_of_call(callP) | |
2752 | symbolS *callP; | |
2753 | { | |
2754 | symbolS *retval; | |
a39116f1 | 2755 | |
fecd2382 | 2756 | know(TC_S_IS_CALLNAME(callP)); |
a39116f1 | 2757 | |
fecd2382 RP |
2758 | #ifdef OBJ_COFF |
2759 | retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry); | |
2760 | #elif defined(OBJ_AOUT) || defined(OBJ_BOUT) | |
2761 | retval = symbol_next(callP); | |
2762 | #else | |
2763 | (as yet unwritten.); | |
2764 | #endif /* switch on OBJ_FORMAT */ | |
a39116f1 | 2765 | |
fecd2382 RP |
2766 | know(TC_S_IS_BALNAME(retval)); |
2767 | return((char *) retval); | |
2768 | } /* _tc_get_bal_of_call() */ | |
2769 | ||
2770 | void tc_coff_symbol_emit_hook(symbolP) | |
2771 | symbolS *symbolP; | |
2772 | { | |
2773 | if (TC_S_IS_CALLNAME(symbolP)) { | |
2774 | #ifdef OBJ_COFF | |
2775 | symbolS *balP = tc_get_bal_of_call(symbolP); | |
2776 | ||
2777 | /* second aux entry contains the bal entry point */ | |
a39116f1 | 2778 | /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */ |
fecd2382 RP |
2779 | symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE(balP); |
2780 | S_SET_STORAGE_CLASS(symbolP, (!SF_GET_LOCAL(symbolP) ? C_LEAFEXT : C_LEAFSTAT)); | |
2781 | S_SET_DATA_TYPE(symbolP, S_GET_DATA_TYPE(symbolP) | (DT_FCN << N_BTSHFT)); | |
2782 | /* fix up the bal symbol */ | |
2783 | S_SET_STORAGE_CLASS(balP, C_LABEL); | |
2784 | #endif /* OBJ_COFF */ | |
2785 | } /* only on calls */ | |
2786 | ||
2787 | return; | |
2788 | } /* tc_coff_symbol_emit_hook() */ | |
2789 | ||
09952cd9 KR |
2790 | void |
2791 | i960_handle_align (fragp) | |
2792 | fragS *fragp; | |
2793 | { | |
2794 | fixS *fixp; | |
2795 | segT old_seg = now_seg, this_seg; | |
2796 | int old_subseg = now_subseg; | |
2797 | int pad_size; | |
2798 | extern struct frag *text_last_frag, *data_last_frag; | |
2799 | ||
2800 | if (!linkrelax) | |
2801 | return; | |
2802 | ||
2803 | /* The text section "ends" with another alignment reloc, to which we | |
2804 | aren't adding padding. */ | |
2805 | if (fragp->fr_next == text_last_frag | |
2806 | || fragp->fr_next == data_last_frag) | |
2807 | { | |
2808 | return; | |
2809 | } | |
2810 | ||
2811 | /* alignment directive */ | |
2812 | fixp = fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, 0, | |
2813 | (int) fragp->fr_type); | |
2814 | } | |
2815 | ||
fecd2382 RP |
2816 | /* |
2817 | * Local Variables: | |
2818 | * comment-column: 0 | |
2819 | * fill-column: 131 | |
2820 | * End: | |
2821 | */ | |
2822 | ||
8b228fe9 | 2823 | /* end of tc-i960.c */ |