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Work around targets that don't yet define JB_PC or JB_ELEMENT_SIZE.
[deliverable/binutils-gdb.git] / gas / config / tc-ia64.c
CommitLineData
800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
e0c9811a 2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
800eeca4
JW		 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
800eeca4
JW		 35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
542d6675
KH		 38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
800eeca4
JW		 42
43 */
44
45#include "as.h"
46#include "dwarf2dbg.h"
47#include "subsegs.h"
48
49#include "opcode/ia64.h"
50
51#include "elf/ia64.h"
52
53#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54#define MIN(a,b) ((a) < (b) ? (a) : (b))
55
56#define NUM_SLOTS 4
57#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58#define CURR_SLOT md.slot[md.curr_slot]
59
60#define O_pseudo_fixup (O_max + 1)
61
62enum special_section
63 {
64 SPECIAL_SECTION_BSS = 0,
65 SPECIAL_SECTION_SBSS,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
71 };
72
73enum reloc_func
74 {
75 FUNC_FPTR_RELATIVE,
76 FUNC_GP_RELATIVE,
77 FUNC_LT_RELATIVE,
c67e42c9 78 FUNC_PC_RELATIVE,
800eeca4
JW		 79 FUNC_PLT_RELATIVE,
80 FUNC_SEC_RELATIVE,
81 FUNC_SEG_RELATIVE,
82 FUNC_LTV_RELATIVE,
83 FUNC_LT_FPTR_RELATIVE,
84 };
85
86enum reg_symbol
87 {
88 REG_GR = 0,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
95 REG_CFM,
96 REG_PR,
97 REG_PR_ROT,
98 REG_PSR,
99 REG_PSR_L,
100 REG_PSR_UM,
101 /* The following are pseudo-registers for use by gas only. */
102 IND_CPUID,
103 IND_DBR,
104 IND_DTR,
105 IND_ITR,
106 IND_IBR,
107 IND_MEM,
108 IND_MSR,
109 IND_PKR,
110 IND_PMC,
111 IND_PMD,
112 IND_RR,
542d6675 113 /* The following pseudo-registers are used for unwind directives only: */
e0c9811a
JW		 114 REG_PSP,
115 REG_PRIUNAT,
800eeca4
JW		 116 REG_NUM
117 };
118
119enum dynreg_type
120 {
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
124 DYNREG_NUM_TYPES
125 };
126
127/* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
130 instruction. */
131struct label_fix
542d6675
KH		 132{
133 struct label_fix *next;
134 struct symbol *sym;
135};
800eeca4
JW		 136
137extern int target_big_endian;
138
139/* Characters which always start a comment. */
140const char comment_chars[] = "";
141
142/* Characters which start a comment at the beginning of a line. */
143const char line_comment_chars[] = "#";
144
145/* Characters which may be used to separate multiple commands on a
146 single line. */
147const char line_separator_chars[] = ";";
148
149/* Characters which are used to indicate an exponent in a floating
150 point number. */
151const char EXP_CHARS[] = "eE";
152
153/* Characters which mean that a number is a floating point constant,
154 as in 0d1.0. */
155const char FLT_CHARS[] = "rRsSfFdDxXpP";
156
542d6675 157/* ia64-specific option processing: */
800eeca4 158
44f5c83a 159const char *md_shortopts = "m:N:x::";
800eeca4
JW		 160
161struct option md_longopts[] =
162 {
c43c2cc5
JW		 163#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
165#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
800eeca4
JW		 167 };
168
169size_t md_longopts_size = sizeof (md_longopts);
170
171static struct
172 {
173 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
174 struct hash_control *reg_hash; /* register name hash table */
175 struct hash_control *dynreg_hash; /* dynamic register hash table */
176 struct hash_control *const_hash; /* constant hash table */
177 struct hash_control *entry_hash; /* code entry hint hash table */
178
179 symbolS *regsym[REG_NUM];
180
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
184 expressionS qp;
185
186 unsigned int
197865e8 187 manual_bundling : 1,
800eeca4
JW		 188 debug_dv: 1,
189 detect_dv: 1,
190 explicit_mode : 1, /* which mode we're in */
191 default_explicit_mode : 1, /* which mode is the default */
192 mode_explicitly_set : 1, /* was the current mode explicitly set? */
193 auto_align : 1;
194
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197865e8 197 the end_of_insn_group for the last instruction in a bundle. */
800eeca4
JW		 198 int curr_slot;
199 int num_slots_in_use;
200 struct slot
201 {
202 unsigned int
203 end_of_insn_group : 1,
204 manual_bundling_on : 1,
205 manual_bundling_off : 1;
206 signed char user_template; /* user-selected template, if any */
207 unsigned char qp_regno; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
211 int num_fixups;
212 struct insn_fix
213 {
214 bfd_reloc_code_real_type code;
215 enum ia64_opnd opnd; /* type of operand in need of fix */
216 unsigned int is_pcrel : 1; /* is operand pc-relative? */
217 expressionS expr; /* the value to be inserted */
218 }
219 fixup[2]; /* at most two fixups per insn */
220 struct ia64_opcode *idesc;
221 struct label_fix *label_fixups;
f1bcba5b 222 struct label_fix *tag_fixups;
800eeca4
JW		 223 struct unw_rec_list *unwind_record; /* Unwind directive. */
224 expressionS opnd[6];
225 char *src_file;
226 unsigned int src_line;
227 struct dwarf2_line_info debug_line;
228 }
229 slot[NUM_SLOTS];
230
231 segT last_text_seg;
232
233 struct dynreg
234 {
235 struct dynreg *next; /* next dynamic register */
236 const char *name;
237 unsigned short base; /* the base register number */
238 unsigned short num_regs; /* # of registers in this set */
239 }
240 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
241
242 flagword flags; /* ELF-header flags */
243
244 struct mem_offset {
245 unsigned hint:1; /* is this hint currently valid? */
246 bfd_vma offset; /* mem.offset offset */
247 bfd_vma base; /* mem.offset base */
248 } mem_offset;
249
250 int path; /* number of alt. entry points seen */
251 const char **entry_labels; /* labels of all alternate paths in
542d6675 252 the current DV-checking block. */
800eeca4 253 int maxpaths; /* size currently allocated for
542d6675 254 entry_labels */
800eeca4
JW		 255 }
256md;
257
542d6675 258/* application registers: */
800eeca4 259
e0c9811a
JW		 260#define AR_K0 0
261#define AR_K7 7
262#define AR_RSC 16
263#define AR_BSP 17
264#define AR_BSPSTORE 18
265#define AR_RNAT 19
266#define AR_UNAT 36
267#define AR_FPSR 40
268#define AR_ITC 44
269#define AR_PFS 64
270#define AR_LC 65
800eeca4
JW		 271
272static const struct
273 {
274 const char *name;
275 int regnum;
276 }
277ar[] =
278 {
279 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
280 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
281 {"ar.rsc", 16}, {"ar.bsp", 17},
282 {"ar.bspstore", 18}, {"ar.rnat", 19},
283 {"ar.fcr", 21}, {"ar.eflag", 24},
284 {"ar.csd", 25}, {"ar.ssd", 26},
285 {"ar.cflg", 27}, {"ar.fsr", 28},
286 {"ar.fir", 29}, {"ar.fdr", 30},
287 {"ar.ccv", 32}, {"ar.unat", 36},
288 {"ar.fpsr", 40}, {"ar.itc", 44},
289 {"ar.pfs", 64}, {"ar.lc", 65},
197865e8 290 {"ar.ec", 66},
800eeca4
JW		 291 };
292
293#define CR_IPSR 16
294#define CR_ISR 17
295#define CR_IIP 19
296#define CR_IFA 20
297#define CR_ITIR 21
298#define CR_IIPA 22
299#define CR_IFS 23
300#define CR_IIM 24
301#define CR_IHA 25
302#define CR_IVR 65
303#define CR_TPR 66
304#define CR_EOI 67
305#define CR_IRR0 68
306#define CR_IRR3 71
307#define CR_LRR0 80
308#define CR_LRR1 81
309
542d6675 310/* control registers: */
800eeca4
JW		 311static const struct
312 {
313 const char *name;
314 int regnum;
315 }
316cr[] =
317 {
318 {"cr.dcr", 0},
319 {"cr.itm", 1},
320 {"cr.iva", 2},
321 {"cr.pta", 8},
322 {"cr.gpta", 9},
323 {"cr.ipsr", 16},
324 {"cr.isr", 17},
325 {"cr.iip", 19},
326 {"cr.ifa", 20},
327 {"cr.itir", 21},
328 {"cr.iipa", 22},
329 {"cr.ifs", 23},
330 {"cr.iim", 24},
331 {"cr.iha", 25},
332 {"cr.lid", 64},
333 {"cr.ivr", 65},
334 {"cr.tpr", 66},
335 {"cr.eoi", 67},
336 {"cr.irr0", 68},
337 {"cr.irr1", 69},
338 {"cr.irr2", 70},
339 {"cr.irr3", 71},
340 {"cr.itv", 72},
341 {"cr.pmv", 73},
342 {"cr.cmcv", 74},
343 {"cr.lrr0", 80},
344 {"cr.lrr1", 81}
345 };
346
347#define PSR_MFL 4
348#define PSR_IC 13
349#define PSR_DFL 18
350#define PSR_CPL 32
351
352static const struct const_desc
353 {
354 const char *name;
355 valueT value;
356 }
357const_bits[] =
358 {
542d6675 359 /* PSR constant masks: */
800eeca4
JW		 360
361 /* 0: reserved */
362 {"psr.be", ((valueT) 1) << 1},
363 {"psr.up", ((valueT) 1) << 2},
364 {"psr.ac", ((valueT) 1) << 3},
365 {"psr.mfl", ((valueT) 1) << 4},
366 {"psr.mfh", ((valueT) 1) << 5},
367 /* 6-12: reserved */
368 {"psr.ic", ((valueT) 1) << 13},
369 {"psr.i", ((valueT) 1) << 14},
370 {"psr.pk", ((valueT) 1) << 15},
371 /* 16: reserved */
372 {"psr.dt", ((valueT) 1) << 17},
373 {"psr.dfl", ((valueT) 1) << 18},
374 {"psr.dfh", ((valueT) 1) << 19},
375 {"psr.sp", ((valueT) 1) << 20},
376 {"psr.pp", ((valueT) 1) << 21},
377 {"psr.di", ((valueT) 1) << 22},
378 {"psr.si", ((valueT) 1) << 23},
379 {"psr.db", ((valueT) 1) << 24},
380 {"psr.lp", ((valueT) 1) << 25},
381 {"psr.tb", ((valueT) 1) << 26},
382 {"psr.rt", ((valueT) 1) << 27},
383 /* 28-31: reserved */
384 /* 32-33: cpl (current privilege level) */
385 {"psr.is", ((valueT) 1) << 34},
386 {"psr.mc", ((valueT) 1) << 35},
387 {"psr.it", ((valueT) 1) << 36},
388 {"psr.id", ((valueT) 1) << 37},
389 {"psr.da", ((valueT) 1) << 38},
390 {"psr.dd", ((valueT) 1) << 39},
391 {"psr.ss", ((valueT) 1) << 40},
392 /* 41-42: ri (restart instruction) */
393 {"psr.ed", ((valueT) 1) << 43},
394 {"psr.bn", ((valueT) 1) << 44},
395 };
396
542d6675 397/* indirect register-sets/memory: */
800eeca4
JW		 398
399static const struct
400 {
401 const char *name;
402 int regnum;
403 }
404indirect_reg[] =
405 {
406 { "CPUID", IND_CPUID },
407 { "cpuid", IND_CPUID },
408 { "dbr", IND_DBR },
409 { "dtr", IND_DTR },
410 { "itr", IND_ITR },
411 { "ibr", IND_IBR },
412 { "msr", IND_MSR },
413 { "pkr", IND_PKR },
414 { "pmc", IND_PMC },
415 { "pmd", IND_PMD },
416 { "rr", IND_RR },
417 };
418
419/* Pseudo functions used to indicate relocation types (these functions
420 start with an at sign (@). */
421static struct
422 {
423 const char *name;
424 enum pseudo_type
425 {
426 PSEUDO_FUNC_NONE,
427 PSEUDO_FUNC_RELOC,
428 PSEUDO_FUNC_CONST,
e0c9811a 429 PSEUDO_FUNC_REG,
800eeca4
JW		 430 PSEUDO_FUNC_FLOAT
431 }
432 type;
433 union
434 {
435 unsigned long ival;
436 symbolS *sym;
437 }
438 u;
439 }
440pseudo_func[] =
441 {
542d6675 442 /* reloc pseudo functions (these must come first!): */
800eeca4
JW		 443 { "fptr", PSEUDO_FUNC_RELOC },
444 { "gprel", PSEUDO_FUNC_RELOC },
445 { "ltoff", PSEUDO_FUNC_RELOC },
c67e42c9 446 { "pcrel", PSEUDO_FUNC_RELOC },
800eeca4
JW		 447 { "pltoff", PSEUDO_FUNC_RELOC },
448 { "secrel", PSEUDO_FUNC_RELOC },
449 { "segrel", PSEUDO_FUNC_RELOC },
450 { "ltv", PSEUDO_FUNC_RELOC },
451 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
452
542d6675 453 /* mbtype4 constants: */
800eeca4
JW		 454 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
455 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
456 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
457 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
458 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
459
542d6675 460 /* fclass constants: */
bf3ca999 461 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
800eeca4
JW		 462 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
463 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
464 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
465 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
466 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
467 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
468 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
469 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
TW		 470
471 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a 472
542d6675 473 /* unwind-related constants: */
e0c9811a
JW		 474 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
475 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
476 { "nt", PSEUDO_FUNC_CONST, { 2 } },
477
542d6675 478 /* unwind-related registers: */
e0c9811a 479 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
800eeca4
JW		 480 };
481
542d6675 482/* 41-bit nop opcodes (one per unit): */
800eeca4
JW		 483static const bfd_vma nop[IA64_NUM_UNITS] =
484 {
485 0x0000000000LL, /* NIL => break 0 */
486 0x0008000000LL, /* I-unit nop */
487 0x0008000000LL, /* M-unit nop */
488 0x4000000000LL, /* B-unit nop */
489 0x0008000000LL, /* F-unit nop */
490 0x0008000000LL, /* L-"unit" nop */
491 0x0008000000LL, /* X-unit nop */
492 };
493
494/* Can't be `const' as it's passed to input routines (which have the
495 habit of setting temporary sentinels. */
496static char special_section_name[][20] =
497 {
498 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
499 {".IA_64.unwind"}, {".IA_64.unwind_info"}
500 };
501
502/* The best template for a particular sequence of up to three
503 instructions: */
504#define N IA64_NUM_TYPES
505static unsigned char best_template[N][N][N];
506#undef N
507
508/* Resource dependencies currently in effect */
509static struct rsrc {
510 int depind; /* dependency index */
511 const struct ia64_dependency *dependency; /* actual dependency */
512 unsigned specific:1, /* is this a specific bit/regno? */
513 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
514 int index; /* specific regno/bit within dependency */
515 int note; /* optional qualifying note (0 if none) */
516#define STATE_NONE 0
517#define STATE_STOP 1
518#define STATE_SRLZ 2
519 int insn_srlz; /* current insn serialization state */
520 int data_srlz; /* current data serialization state */
521 int qp_regno; /* qualifying predicate for this usage */
522 char *file; /* what file marked this dependency */
523 int line; /* what line marked this dependency */
524 struct mem_offset mem_offset; /* optional memory offset hint */
7484b8e6 525 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
800eeca4
JW		 526 int path; /* corresponding code entry index */
527} *regdeps = NULL;
528static int regdepslen = 0;
529static int regdepstotlen = 0;
530static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
531static const char *dv_sem[] = { "none", "implied", "impliedf",
139368c9 532 "data", "instr", "specific", "stop", "other" };
7484b8e6 533static const char *dv_cmp_type[] = { "none", "OR", "AND" };
800eeca4
JW		 534
535/* Current state of PR mutexation */
536static struct qpmutex {
537 valueT prmask;
538 int path;
539} *qp_mutexes = NULL; /* QP mutex bitmasks */
540static int qp_mutexeslen = 0;
541static int qp_mutexestotlen = 0;
197865e8 542static valueT qp_safe_across_calls = 0;
800eeca4
JW		 543
544/* Current state of PR implications */
545static struct qp_imply {
546 unsigned p1:6;
547 unsigned p2:6;
548 unsigned p2_branched:1;
549 int path;
550} *qp_implies = NULL;
551static int qp_implieslen = 0;
552static int qp_impliestotlen = 0;
553
197865e8
KH		 554/* Keep track of static GR values so that indirect register usage can
555 sometimes be tracked. */
800eeca4
JW		 556static struct gr {
557 unsigned known:1;
558 int path;
559 valueT value;
560} gr_values[128] = {{ 1, 0 }};
561
562/* These are the routines required to output the various types of
563 unwind records. */
564
565typedef struct unw_rec_list {
566 unwind_record r;
e0c9811a 567 unsigned long slot_number;
800eeca4
JW		 568 struct unw_rec_list *next;
569} unw_rec_list;
570
571#define SLOT_NUM_NOT_SET -1
572
e0c9811a
JW		 573static struct
574{
575 unsigned long next_slot_number;
576
577 /* Maintain a list of unwind entries for the current function. */
578 unw_rec_list *list;
579 unw_rec_list *tail;
800eeca4 580
e0c9811a
JW		 581 /* Any unwind entires that should be attached to the current slot
582 that an insn is being constructed for. */
583 unw_rec_list *current_entry;
800eeca4 584
e0c9811a
JW		 585 /* These are used to create the unwind table entry for this function. */
586 symbolS *proc_start;
587 symbolS *proc_end;
588 symbolS *info; /* pointer to unwind info */
589 symbolS *personality_routine;
800eeca4 590
e0c9811a
JW		 591 /* TRUE if processing unwind directives in a prologue region. */
592 int prologue;
30d25259 593 int prologue_mask;
e0c9811a 594} unwind;
800eeca4
JW		 595
596typedef void (*vbyte_func) PARAMS ((int, char *, char *));
597
542d6675 598/* Forward delarations: */
800eeca4
JW		 599static int ar_is_in_integer_unit PARAMS ((int regnum));
600static void set_section PARAMS ((char *name));
601static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
602 unsigned int, unsigned int));
603static void dot_radix PARAMS ((int));
604static void dot_special_section PARAMS ((int));
605static void dot_proc PARAMS ((int));
606static void dot_fframe PARAMS ((int));
607static void dot_vframe PARAMS ((int));
150f24a2
JW		 608static void dot_vframesp PARAMS ((int));
609static void dot_vframepsp PARAMS ((int));
800eeca4
JW		 610static void dot_save PARAMS ((int));
611static void dot_restore PARAMS ((int));
150f24a2
JW		 612static void dot_restorereg PARAMS ((int));
613static void dot_restorereg_p PARAMS ((int));
800eeca4
JW		 614static void dot_handlerdata PARAMS ((int));
615static void dot_unwentry PARAMS ((int));
616static void dot_altrp PARAMS ((int));
e0c9811a 617static void dot_savemem PARAMS ((int));
800eeca4
JW		 618static void dot_saveg PARAMS ((int));
619static void dot_savef PARAMS ((int));
620static void dot_saveb PARAMS ((int));
621static void dot_savegf PARAMS ((int));
622static void dot_spill PARAMS ((int));
150f24a2
JW		 623static void dot_spillreg PARAMS ((int));
624static void dot_spillmem PARAMS ((int));
625static void dot_spillreg_p PARAMS ((int));
626static void dot_spillmem_p PARAMS ((int));
627static void dot_label_state PARAMS ((int));
628static void dot_copy_state PARAMS ((int));
800eeca4
JW		 629static void dot_unwabi PARAMS ((int));
630static void dot_personality PARAMS ((int));
631static void dot_body PARAMS ((int));
632static void dot_prologue PARAMS ((int));
633static void dot_endp PARAMS ((int));
634static void dot_template PARAMS ((int));
635static void dot_regstk PARAMS ((int));
636static void dot_rot PARAMS ((int));
637static void dot_byteorder PARAMS ((int));
638static void dot_psr PARAMS ((int));
639static void dot_alias PARAMS ((int));
640static void dot_ln PARAMS ((int));
641static char *parse_section_name PARAMS ((void));
642static void dot_xdata PARAMS ((int));
643static void stmt_float_cons PARAMS ((int));
644static void stmt_cons_ua PARAMS ((int));
645static void dot_xfloat_cons PARAMS ((int));
646static void dot_xstringer PARAMS ((int));
647static void dot_xdata_ua PARAMS ((int));
648static void dot_xfloat_cons_ua PARAMS ((int));
150f24a2 649static void print_prmask PARAMS ((valueT mask));
800eeca4
JW		 650static void dot_pred_rel PARAMS ((int));
651static void dot_reg_val PARAMS ((int));
652static void dot_dv_mode PARAMS ((int));
653static void dot_entry PARAMS ((int));
654static void dot_mem_offset PARAMS ((int));
e0c9811a 655static void add_unwind_entry PARAMS((unw_rec_list *ptr));
542d6675 656static symbolS *declare_register PARAMS ((const char *name, int regnum));
800eeca4
JW		 657static void declare_register_set PARAMS ((const char *, int, int));
658static unsigned int operand_width PARAMS ((enum ia64_opnd));
659static int operand_match PARAMS ((const struct ia64_opcode *idesc,
660 int index, expressionS *e));
661static int parse_operand PARAMS ((expressionS *e));
662static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
663static void build_insn PARAMS ((struct slot *, bfd_vma *));
664static void emit_one_bundle PARAMS ((void));
665static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
197865e8 666static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
800eeca4
JW		 667 bfd_reloc_code_real_type r_type));
668static void insn_group_break PARAMS ((int, int, int));
150f24a2
JW		 669static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
670 struct rsrc *, int depind, int path));
800eeca4
JW		 671static void add_qp_mutex PARAMS((valueT mask));
672static void add_qp_imply PARAMS((int p1, int p2));
673static void clear_qp_branch_flag PARAMS((valueT mask));
674static void clear_qp_mutex PARAMS((valueT mask));
675static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
676static void clear_register_values PARAMS ((void));
677static void print_dependency PARAMS ((const char *action, int depind));
150f24a2
JW		 678static void instruction_serialization PARAMS ((void));
679static void data_serialization PARAMS ((void));
680static void remove_marked_resource PARAMS ((struct rsrc *));
800eeca4 681static int is_conditional_branch PARAMS ((struct ia64_opcode *));
150f24a2 682static int is_taken_branch PARAMS ((struct ia64_opcode *));
800eeca4 683static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
150f24a2
JW		 684static int depends_on PARAMS ((int, struct ia64_opcode *));
685static int specify_resource PARAMS ((const struct ia64_dependency *,
686 struct ia64_opcode *, int, struct rsrc [], int, int));
800eeca4
JW		 687static int check_dv PARAMS((struct ia64_opcode *idesc));
688static void check_dependencies PARAMS((struct ia64_opcode *));
689static void mark_resources PARAMS((struct ia64_opcode *));
690static void update_dependencies PARAMS((struct ia64_opcode *));
691static void note_register_values PARAMS((struct ia64_opcode *));
150f24a2
JW		 692static int qp_mutex PARAMS ((int, int, int));
693static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
694static void output_vbyte_mem PARAMS ((int, char *, char *));
695static void count_output PARAMS ((int, char *, char *));
696static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
697static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
800eeca4 698static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 699static void output_P1_format PARAMS ((vbyte_func, int));
700static void output_P2_format PARAMS ((vbyte_func, int, int));
701static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
702static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
703static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
704static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
705static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
706static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
707static void output_P9_format PARAMS ((vbyte_func, int, int));
708static void output_P10_format PARAMS ((vbyte_func, int, int));
709static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
710static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800eeca4
JW		 711static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
712static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 713static char format_ab_reg PARAMS ((int, int));
714static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
715 unsigned long));
716static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
717static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
718 unsigned long));
719static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
720static void free_list_records PARAMS ((unw_rec_list *));
721static unw_rec_list *output_prologue PARAMS ((void));
722static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
723static unw_rec_list *output_body PARAMS ((void));
724static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
725static unw_rec_list *output_mem_stack_v PARAMS ((void));
726static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
727static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
728static unw_rec_list *output_rp_when PARAMS ((void));
729static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
730static unw_rec_list *output_rp_br PARAMS ((unsigned int));
731static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
732static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
733static unw_rec_list *output_pfs_when PARAMS ((void));
734static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
735static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
736static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
737static unw_rec_list *output_preds_when PARAMS ((void));
738static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
739static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
740static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
741static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
742static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
743static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
744static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
745static unw_rec_list *output_br_mem PARAMS ((unsigned int));
746static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
747static unw_rec_list *output_spill_base PARAMS ((unsigned int));
748static unw_rec_list *output_unat_when PARAMS ((void));
749static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
750static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
751static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
752static unw_rec_list *output_lc_when PARAMS ((void));
753static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
754static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
755static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
756static unw_rec_list *output_fpsr_when PARAMS ((void));
757static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
758static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
759static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
760static unw_rec_list *output_priunat_when_gr PARAMS ((void));
761static unw_rec_list *output_priunat_when_mem PARAMS ((void));
762static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
763static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
764static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
765static unw_rec_list *output_bsp_when PARAMS ((void));
766static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
767static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
768static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
769static unw_rec_list *output_bspstore_when PARAMS ((void));
770static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
771static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
772static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
773static unw_rec_list *output_rnat_when PARAMS ((void));
774static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
775static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
776static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
777static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
778static unw_rec_list *output_epilogue PARAMS ((unsigned long));
779static unw_rec_list *output_label_state PARAMS ((unsigned long));
780static unw_rec_list *output_copy_state PARAMS ((unsigned long));
781static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
782static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
783static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
784 unsigned int));
785static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
786 unsigned int));
787static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
788 unsigned int));
789static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
790 unsigned int, unsigned int));
791static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
792static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
793static int calc_record_size PARAMS ((unw_rec_list *));
794static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
795static int count_bits PARAMS ((unsigned long));
796static unsigned long slot_index PARAMS ((unsigned long, unsigned long));
797static void fixup_unw_records PARAMS ((unw_rec_list *));
798static int output_unw_records PARAMS ((unw_rec_list *, void **));
799static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
800static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
801static int generate_unwind_image PARAMS ((void));
800eeca4
JW		 802
803/* Determine if application register REGNUM resides in the integer
804 unit (as opposed to the memory unit). */
805static int
806ar_is_in_integer_unit (reg)
807 int reg;
808{
809 reg -= REG_AR;
810
811 return (reg == 64 /* pfs */
812 || reg == 65 /* lc */
813 || reg == 66 /* ec */
814 /* ??? ias accepts and puts these in the integer unit. */
815 || (reg >= 112 && reg <= 127));
816}
817
818/* Switch to section NAME and create section if necessary. It's
819 rather ugly that we have to manipulate input_line_pointer but I
820 don't see any other way to accomplish the same thing without
821 changing obj-elf.c (which may be the Right Thing, in the end). */
822static void
823set_section (name)
824 char *name;
825{
826 char *saved_input_line_pointer;
827
828 saved_input_line_pointer = input_line_pointer;
829 input_line_pointer = name;
830 obj_elf_section (0);
831 input_line_pointer = saved_input_line_pointer;
832}
833
834/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
835
836flagword
837ia64_elf_section_flags (flags, attr, type)
838 flagword flags;
839 int attr, type;
840{
841 if (attr & SHF_IA_64_SHORT)
842 flags |= SEC_SMALL_DATA;
843 return flags;
844}
845
846static unsigned int
847set_regstack (ins, locs, outs, rots)
848 unsigned int ins, locs, outs, rots;
849{
542d6675
KH		 850 /* Size of frame. */
851 unsigned int sof;
800eeca4
JW		 852
853 sof = ins + locs + outs;
854 if (sof > 96)
855 {
856 as_bad ("Size of frame exceeds maximum of 96 registers");
857 return 0;
858 }
859 if (rots > sof)
860 {
861 as_warn ("Size of rotating registers exceeds frame size");
862 return 0;
863 }
864 md.in.base = REG_GR + 32;
865 md.loc.base = md.in.base + ins;
866 md.out.base = md.loc.base + locs;
867
868 md.in.num_regs = ins;
869 md.loc.num_regs = locs;
870 md.out.num_regs = outs;
871 md.rot.num_regs = rots;
872 return sof;
873}
874
875void
876ia64_flush_insns ()
877{
878 struct label_fix *lfix;
879 segT saved_seg;
880 subsegT saved_subseg;
881
882 if (!md.last_text_seg)
883 return;
884
885 saved_seg = now_seg;
886 saved_subseg = now_subseg;
887
888 subseg_set (md.last_text_seg, 0);
889
890 while (md.num_slots_in_use > 0)
891 emit_one_bundle (); /* force out queued instructions */
892
893 /* In case there are labels following the last instruction, resolve
542d6675 894 those now: */
800eeca4
JW		 895 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
896 {
897 S_SET_VALUE (lfix->sym, frag_now_fix ());
898 symbol_set_frag (lfix->sym, frag_now);
899 }
900 CURR_SLOT.label_fixups = 0;
f1bcba5b
JW		 901 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
902 {
903 S_SET_VALUE (lfix->sym, frag_now_fix ());
904 symbol_set_frag (lfix->sym, frag_now);
905 }
906 CURR_SLOT.tag_fixups = 0;
800eeca4
JW		 907
908 subseg_set (saved_seg, saved_subseg);
f1bcba5b
JW		 909
910 if (md.qp.X_op == O_register)
911 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW		 912}
913
914void
915ia64_do_align (nbytes)
916 int nbytes;
917{
918 char *saved_input_line_pointer = input_line_pointer;
919
920 input_line_pointer = "";
921 s_align_bytes (nbytes);
922 input_line_pointer = saved_input_line_pointer;
923}
924
925void
926ia64_cons_align (nbytes)
927 int nbytes;
928{
929 if (md.auto_align)
930 {
931 char *saved_input_line_pointer = input_line_pointer;
932 input_line_pointer = "";
933 s_align_bytes (nbytes);
934 input_line_pointer = saved_input_line_pointer;
935 }
936}
937
938/* Output COUNT bytes to a memory location. */
939static unsigned char *vbyte_mem_ptr = NULL;
940
197865e8 941void
800eeca4
JW		 942output_vbyte_mem (count, ptr, comment)
943 int count;
944 char *ptr;
945 char *comment;
946{
947 int x;
948 if (vbyte_mem_ptr == NULL)
949 abort ();
950
951 if (count == 0)
952 return;
953 for (x = 0; x < count; x++)
954 *(vbyte_mem_ptr++) = ptr[x];
955}
956
957/* Count the number of bytes required for records. */
958static int vbyte_count = 0;
197865e8 959void
800eeca4
JW		 960count_output (count, ptr, comment)
961 int count;
962 char *ptr;
963 char *comment;
964{
965 vbyte_count += count;
966}
967
968static void
969output_R1_format (f, rtype, rlen)
970 vbyte_func f;
971 unw_record_type rtype;
972 int rlen;
973{
e0c9811a 974 int r = 0;
800eeca4
JW		 975 char byte;
976 if (rlen > 0x1f)
977 {
978 output_R3_format (f, rtype, rlen);
979 return;
980 }
197865e8 981
e0c9811a
JW		 982 if (rtype == body)
983 r = 1;
984 else if (rtype != prologue)
985 as_bad ("record type is not valid");
986
800eeca4
JW		 987 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
988 (*f) (1, &byte, NULL);
989}
990
991static void
992output_R2_format (f, mask, grsave, rlen)
993 vbyte_func f;
994 int mask, grsave;
995 unsigned long rlen;
996{
997 char bytes[20];
998 int count = 2;
999 mask = (mask & 0x0f);
1000 grsave = (grsave & 0x7f);
1001
1002 bytes[0] = (UNW_R2 | (mask >> 1));
1003 bytes[1] = (((mask & 0x01) << 7) | grsave);
1004 count += output_leb128 (bytes + 2, rlen, 0);
1005 (*f) (count, bytes, NULL);
1006}
1007
1008static void
1009output_R3_format (f, rtype, rlen)
1010 vbyte_func f;
1011 unw_record_type rtype;
1012 unsigned long rlen;
1013{
e0c9811a 1014 int r = 0, count;
800eeca4
JW		 1015 char bytes[20];
1016 if (rlen <= 0x1f)
1017 {
1018 output_R1_format (f, rtype, rlen);
1019 return;
1020 }
197865e8 1021
e0c9811a
JW		 1022 if (rtype == body)
1023 r = 1;
1024 else if (rtype != prologue)
1025 as_bad ("record type is not valid");
800eeca4
JW		 1026 bytes[0] = (UNW_R3 | r);
1027 count = output_leb128 (bytes + 1, rlen, 0);
1028 (*f) (count + 1, bytes, NULL);
1029}
1030
1031static void
1032output_P1_format (f, brmask)
1033 vbyte_func f;
1034 int brmask;
1035{
1036 char byte;
1037 byte = UNW_P1 | (brmask & 0x1f);
1038 (*f) (1, &byte, NULL);
1039}
1040
1041static void
1042output_P2_format (f, brmask, gr)
1043 vbyte_func f;
1044 int brmask;
1045 int gr;
1046{
1047 char bytes[2];
1048 brmask = (brmask & 0x1f);
1049 bytes[0] = UNW_P2 | (brmask >> 1);
1050 bytes[1] = (((brmask & 1) << 7) | gr);
1051 (*f) (2, bytes, NULL);
1052}
1053
1054static void
1055output_P3_format (f, rtype, reg)
1056 vbyte_func f;
1057 unw_record_type rtype;
1058 int reg;
1059{
1060 char bytes[2];
e0c9811a 1061 int r = 0;
800eeca4
JW		 1062 reg = (reg & 0x7f);
1063 switch (rtype)
542d6675 1064 {
800eeca4
JW		 1065 case psp_gr:
1066 r = 0;
1067 break;
1068 case rp_gr:
1069 r = 1;
1070 break;
1071 case pfs_gr:
1072 r = 2;
1073 break;
1074 case preds_gr:
1075 r = 3;
1076 break;
1077 case unat_gr:
1078 r = 4;
1079 break;
1080 case lc_gr:
1081 r = 5;
1082 break;
1083 case rp_br:
1084 r = 6;
1085 break;
1086 case rnat_gr:
1087 r = 7;
1088 break;
1089 case bsp_gr:
1090 r = 8;
1091 break;
1092 case bspstore_gr:
1093 r = 9;
1094 break;
1095 case fpsr_gr:
1096 r = 10;
1097 break;
1098 case priunat_gr:
1099 r = 11;
1100 break;
1101 default:
1102 as_bad ("Invalid record type for P3 format.");
542d6675 1103 }
800eeca4
JW		 1104 bytes[0] = (UNW_P3 | (r >> 1));
1105 bytes[1] = (((r & 1) << 7) | reg);
1106 (*f) (2, bytes, NULL);
1107}
1108
800eeca4 1109static void
e0c9811a 1110output_P4_format (f, imask, imask_size)
800eeca4 1111 vbyte_func f;
e0c9811a
JW		 1112 unsigned char *imask;
1113 unsigned long imask_size;
800eeca4 1114{
e0c9811a
JW		 1115 imask[0] = UNW_P4;
1116 (*f) (imask_size, imask, NULL);
800eeca4
JW		 1117}
1118
1119static void
1120output_P5_format (f, grmask, frmask)
1121 vbyte_func f;
1122 int grmask;
1123 unsigned long frmask;
1124{
1125 char bytes[4];
1126 grmask = (grmask & 0x0f);
1127
1128 bytes[0] = UNW_P5;
1129 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1130 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1131 bytes[3] = (frmask & 0x000000ff);
1132 (*f) (4, bytes, NULL);
1133}
1134
1135static void
1136output_P6_format (f, rtype, rmask)
1137 vbyte_func f;
1138 unw_record_type rtype;
1139 int rmask;
1140{
1141 char byte;
e0c9811a 1142 int r = 0;
197865e8 1143
e0c9811a
JW		 1144 if (rtype == gr_mem)
1145 r = 1;
1146 else if (rtype != fr_mem)
1147 as_bad ("Invalid record type for format P6");
800eeca4
JW		 1148 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1149 (*f) (1, &byte, NULL);
1150}
1151
1152static void
1153output_P7_format (f, rtype, w1, w2)
1154 vbyte_func f;
1155 unw_record_type rtype;
1156 unsigned long w1;
1157 unsigned long w2;
1158{
1159 char bytes[20];
1160 int count = 1;
e0c9811a 1161 int r = 0;
800eeca4
JW		 1162 count += output_leb128 (bytes + 1, w1, 0);
1163 switch (rtype)
1164 {
542d6675
KH		 1165 case mem_stack_f:
1166 r = 0;
1167 count += output_leb128 (bytes + count, w2 >> 4, 0);
1168 break;
1169 case mem_stack_v:
1170 r = 1;
1171 break;
1172 case spill_base:
1173 r = 2;
1174 break;
1175 case psp_sprel:
1176 r = 3;
1177 break;
1178 case rp_when:
1179 r = 4;
1180 break;
1181 case rp_psprel:
1182 r = 5;
1183 break;
1184 case pfs_when:
1185 r = 6;
1186 break;
1187 case pfs_psprel:
1188 r = 7;
1189 break;
1190 case preds_when:
1191 r = 8;
1192 break;
1193 case preds_psprel:
1194 r = 9;
1195 break;
1196 case lc_when:
1197 r = 10;
1198 break;
1199 case lc_psprel:
1200 r = 11;
1201 break;
1202 case unat_when:
1203 r = 12;
1204 break;
1205 case unat_psprel:
1206 r = 13;
1207 break;
1208 case fpsr_when:
1209 r = 14;
1210 break;
1211 case fpsr_psprel:
1212 r = 15;
1213 break;
1214 default:
1215 break;
800eeca4
JW		 1216 }
1217 bytes[0] = (UNW_P7 | r);
1218 (*f) (count, bytes, NULL);
1219}
1220
1221static void
1222output_P8_format (f, rtype, t)
1223 vbyte_func f;
1224 unw_record_type rtype;
1225 unsigned long t;
1226{
1227 char bytes[20];
e0c9811a 1228 int r = 0;
800eeca4
JW		 1229 int count = 2;
1230 bytes[0] = UNW_P8;
1231 switch (rtype)
1232 {
542d6675
KH		 1233 case rp_sprel:
1234 r = 1;
1235 break;
1236 case pfs_sprel:
1237 r = 2;
1238 break;
1239 case preds_sprel:
1240 r = 3;
1241 break;
1242 case lc_sprel:
1243 r = 4;
1244 break;
1245 case unat_sprel:
1246 r = 5;
1247 break;
1248 case fpsr_sprel:
1249 r = 6;
1250 break;
1251 case bsp_when:
1252 r = 7;
1253 break;
1254 case bsp_psprel:
1255 r = 8;
1256 break;
1257 case bsp_sprel:
1258 r = 9;
1259 break;
1260 case bspstore_when:
1261 r = 10;
1262 break;
1263 case bspstore_psprel:
1264 r = 11;
1265 break;
1266 case bspstore_sprel:
1267 r = 12;
1268 break;
1269 case rnat_when:
1270 r = 13;
1271 break;
1272 case rnat_psprel:
1273 r = 14;
1274 break;
1275 case rnat_sprel:
1276 r = 15;
1277 break;
1278 case priunat_when_gr:
1279 r = 16;
1280 break;
1281 case priunat_psprel:
1282 r = 17;
1283 break;
1284 case priunat_sprel:
1285 r = 18;
1286 break;
1287 case priunat_when_mem:
1288 r = 19;
1289 break;
1290 default:
1291 break;
800eeca4
JW		 1292 }
1293 bytes[1] = r;
1294 count += output_leb128 (bytes + 2, t, 0);
1295 (*f) (count, bytes, NULL);
1296}
1297
1298static void
1299output_P9_format (f, grmask, gr)
1300 vbyte_func f;
1301 int grmask;
1302 int gr;
1303{
1304 char bytes[3];
1305 bytes[0] = UNW_P9;
1306 bytes[1] = (grmask & 0x0f);
1307 bytes[2] = (gr & 0x7f);
1308 (*f) (3, bytes, NULL);
1309}
1310
1311static void
1312output_P10_format (f, abi, context)
1313 vbyte_func f;
1314 int abi;
1315 int context;
1316{
1317 char bytes[3];
1318 bytes[0] = UNW_P10;
1319 bytes[1] = (abi & 0xff);
1320 bytes[2] = (context & 0xff);
1321 (*f) (3, bytes, NULL);
1322}
1323
1324static void
1325output_B1_format (f, rtype, label)
1326 vbyte_func f;
1327 unw_record_type rtype;
1328 unsigned long label;
1329{
1330 char byte;
e0c9811a 1331 int r = 0;
197865e8 1332 if (label > 0x1f)
800eeca4
JW		 1333 {
1334 output_B4_format (f, rtype, label);
1335 return;
1336 }
e0c9811a
JW		 1337 if (rtype == copy_state)
1338 r = 1;
1339 else if (rtype != label_state)
1340 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1341
1342 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1343 (*f) (1, &byte, NULL);
1344}
1345
1346static void
1347output_B2_format (f, ecount, t)
1348 vbyte_func f;
1349 unsigned long ecount;
1350 unsigned long t;
1351{
1352 char bytes[20];
1353 int count = 1;
1354 if (ecount > 0x1f)
1355 {
1356 output_B3_format (f, ecount, t);
1357 return;
1358 }
1359 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1360 count += output_leb128 (bytes + 1, t, 0);
1361 (*f) (count, bytes, NULL);
1362}
1363
1364static void
1365output_B3_format (f, ecount, t)
1366 vbyte_func f;
1367 unsigned long ecount;
1368 unsigned long t;
1369{
1370 char bytes[20];
1371 int count = 1;
1372 if (ecount <= 0x1f)
1373 {
1374 output_B2_format (f, ecount, t);
1375 return;
1376 }
1377 bytes[0] = UNW_B3;
1378 count += output_leb128 (bytes + 1, t, 0);
1379 count += output_leb128 (bytes + count, ecount, 0);
1380 (*f) (count, bytes, NULL);
1381}
1382
1383static void
1384output_B4_format (f, rtype, label)
1385 vbyte_func f;
1386 unw_record_type rtype;
1387 unsigned long label;
1388{
1389 char bytes[20];
e0c9811a 1390 int r = 0;
800eeca4 1391 int count = 1;
197865e8 1392 if (label <= 0x1f)
800eeca4
JW		 1393 {
1394 output_B1_format (f, rtype, label);
1395 return;
1396 }
197865e8 1397
e0c9811a
JW		 1398 if (rtype == copy_state)
1399 r = 1;
1400 else if (rtype != label_state)
1401 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1402
1403 bytes[0] = (UNW_B4 | (r << 3));
1404 count += output_leb128 (bytes + 1, label, 0);
1405 (*f) (count, bytes, NULL);
1406}
1407
1408static char
e0c9811a 1409format_ab_reg (ab, reg)
542d6675
KH		 1410 int ab;
1411 int reg;
800eeca4
JW		 1412{
1413 int ret;
e0c9811a 1414 ab = (ab & 3);
800eeca4 1415 reg = (reg & 0x1f);
e0c9811a 1416 ret = (ab << 5) | reg;
800eeca4
JW		 1417 return ret;
1418}
1419
1420static void
e0c9811a 1421output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW		 1422 vbyte_func f;
1423 unw_record_type rtype;
e0c9811a 1424 int ab, reg;
800eeca4
JW		 1425 unsigned long t;
1426 unsigned long w1;
1427{
1428 char bytes[20];
e0c9811a 1429 int r = 0;
800eeca4
JW		 1430 int count = 2;
1431 bytes[0] = UNW_X1;
197865e8 1432
e0c9811a
JW		 1433 if (rtype == spill_sprel)
1434 r = 1;
1435 else if (rtype != spill_psprel)
1436 as_bad ("Invalid record type for format X1");
1437 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1438 count += output_leb128 (bytes + 2, t, 0);
1439 count += output_leb128 (bytes + count, w1, 0);
1440 (*f) (count, bytes, NULL);
1441}
1442
1443static void
e0c9811a 1444output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1445 vbyte_func f;
e0c9811a 1446 int ab, reg;
800eeca4
JW		 1447 int x, y, treg;
1448 unsigned long t;
1449{
1450 char bytes[20];
800eeca4
JW		 1451 int count = 3;
1452 bytes[0] = UNW_X2;
e0c9811a 1453 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1454 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1455 count += output_leb128 (bytes + 3, t, 0);
1456 (*f) (count, bytes, NULL);
1457}
1458
1459static void
e0c9811a 1460output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW		 1461 vbyte_func f;
1462 unw_record_type rtype;
1463 int qp;
e0c9811a 1464 int ab, reg;
800eeca4
JW		 1465 unsigned long t;
1466 unsigned long w1;
1467{
1468 char bytes[20];
e0c9811a 1469 int r = 0;
800eeca4 1470 int count = 3;
e0c9811a
JW		 1471 bytes[0] = UNW_X3;
1472
1473 if (rtype == spill_sprel_p)
1474 r = 1;
1475 else if (rtype != spill_psprel_p)
1476 as_bad ("Invalid record type for format X3");
800eeca4 1477 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1478 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW		 1479 count += output_leb128 (bytes + 3, t, 0);
1480 count += output_leb128 (bytes + count, w1, 0);
1481 (*f) (count, bytes, NULL);
1482}
1483
1484static void
e0c9811a 1485output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW		 1486 vbyte_func f;
1487 int qp;
e0c9811a 1488 int ab, reg;
800eeca4
JW		 1489 int x, y, treg;
1490 unsigned long t;
1491{
1492 char bytes[20];
800eeca4 1493 int count = 4;
e0c9811a 1494 bytes[0] = UNW_X4;
800eeca4 1495 bytes[1] = (qp & 0x3f);
e0c9811a 1496 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1497 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1498 count += output_leb128 (bytes + 4, t, 0);
1499 (*f) (count, bytes, NULL);
1500}
1501
1502/* This function allocates a record list structure, and initializes fields. */
542d6675 1503
800eeca4 1504static unw_rec_list *
197865e8 1505alloc_record (unw_record_type t)
800eeca4
JW		 1506{
1507 unw_rec_list *ptr;
1508 ptr = xmalloc (sizeof (*ptr));
1509 ptr->next = NULL;
1510 ptr->slot_number = SLOT_NUM_NOT_SET;
1511 ptr->r.type = t;
1512 return ptr;
1513}
1514
800eeca4 1515/* This function frees an entire list of record structures. */
542d6675 1516
800eeca4
JW		 1517void
1518free_list_records (unw_rec_list *first)
1519{
1520 unw_rec_list *ptr;
542d6675 1521 for (ptr = first; ptr != NULL;)
800eeca4
JW		 1522 {
1523 unw_rec_list *tmp = ptr;
e0c9811a
JW		 1524
1525 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1526 && tmp->r.record.r.mask.i)
1527 free (tmp->r.record.r.mask.i);
1528
800eeca4
JW		 1529 ptr = ptr->next;
1530 free (tmp);
1531 }
1532}
1533
1534static unw_rec_list *
1535output_prologue ()
1536{
1537 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1538 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW		 1539 return ptr;
1540}
1541
1542static unw_rec_list *
1543output_prologue_gr (saved_mask, reg)
1544 unsigned int saved_mask;
1545 unsigned int reg;
1546{
1547 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW		 1548 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1549 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW		 1550 ptr->r.record.r.grsave = reg;
1551 return ptr;
1552}
1553
1554static unw_rec_list *
1555output_body ()
1556{
1557 unw_rec_list *ptr = alloc_record (body);
1558 return ptr;
1559}
1560
1561static unw_rec_list *
1562output_mem_stack_f (size)
1563 unsigned int size;
1564{
1565 unw_rec_list *ptr = alloc_record (mem_stack_f);
1566 ptr->r.record.p.size = size;
1567 return ptr;
1568}
1569
1570static unw_rec_list *
1571output_mem_stack_v ()
1572{
1573 unw_rec_list *ptr = alloc_record (mem_stack_v);
1574 return ptr;
1575}
1576
1577static unw_rec_list *
1578output_psp_gr (gr)
1579 unsigned int gr;
1580{
1581 unw_rec_list *ptr = alloc_record (psp_gr);
1582 ptr->r.record.p.gr = gr;
1583 return ptr;
1584}
1585
1586static unw_rec_list *
1587output_psp_sprel (offset)
1588 unsigned int offset;
1589{
1590 unw_rec_list *ptr = alloc_record (psp_sprel);
542d6675 1591 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1592 return ptr;
1593}
1594
1595static unw_rec_list *
1596output_rp_when ()
1597{
1598 unw_rec_list *ptr = alloc_record (rp_when);
1599 return ptr;
1600}
1601
1602static unw_rec_list *
1603output_rp_gr (gr)
1604 unsigned int gr;
1605{
1606 unw_rec_list *ptr = alloc_record (rp_gr);
1607 ptr->r.record.p.gr = gr;
1608 return ptr;
1609}
1610
1611static unw_rec_list *
1612output_rp_br (br)
1613 unsigned int br;
1614{
1615 unw_rec_list *ptr = alloc_record (rp_br);
1616 ptr->r.record.p.br = br;
1617 return ptr;
1618}
1619
1620static unw_rec_list *
1621output_rp_psprel (offset)
1622 unsigned int offset;
1623{
1624 unw_rec_list *ptr = alloc_record (rp_psprel);
542d6675 1625 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1626 return ptr;
1627}
1628
1629static unw_rec_list *
1630output_rp_sprel (offset)
1631 unsigned int offset;
1632{
1633 unw_rec_list *ptr = alloc_record (rp_sprel);
542d6675 1634 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1635 return ptr;
1636}
1637
1638static unw_rec_list *
1639output_pfs_when ()
1640{
1641 unw_rec_list *ptr = alloc_record (pfs_when);
1642 return ptr;
1643}
1644
1645static unw_rec_list *
1646output_pfs_gr (gr)
1647 unsigned int gr;
1648{
1649 unw_rec_list *ptr = alloc_record (pfs_gr);
1650 ptr->r.record.p.gr = gr;
1651 return ptr;
1652}
1653
1654static unw_rec_list *
1655output_pfs_psprel (offset)
1656 unsigned int offset;
1657{
1658 unw_rec_list *ptr = alloc_record (pfs_psprel);
542d6675 1659 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1660 return ptr;
1661}
1662
1663static unw_rec_list *
1664output_pfs_sprel (offset)
1665 unsigned int offset;
1666{
1667 unw_rec_list *ptr = alloc_record (pfs_sprel);
542d6675 1668 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1669 return ptr;
1670}
1671
1672static unw_rec_list *
1673output_preds_when ()
1674{
1675 unw_rec_list *ptr = alloc_record (preds_when);
1676 return ptr;
1677}
1678
1679static unw_rec_list *
1680output_preds_gr (gr)
1681 unsigned int gr;
1682{
1683 unw_rec_list *ptr = alloc_record (preds_gr);
1684 ptr->r.record.p.gr = gr;
1685 return ptr;
1686}
1687
1688static unw_rec_list *
1689output_preds_psprel (offset)
1690 unsigned int offset;
1691{
1692 unw_rec_list *ptr = alloc_record (preds_psprel);
542d6675 1693 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1694 return ptr;
1695}
1696
1697static unw_rec_list *
1698output_preds_sprel (offset)
1699 unsigned int offset;
1700{
1701 unw_rec_list *ptr = alloc_record (preds_sprel);
542d6675 1702 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1703 return ptr;
1704}
1705
1706static unw_rec_list *
1707output_fr_mem (mask)
1708 unsigned int mask;
1709{
1710 unw_rec_list *ptr = alloc_record (fr_mem);
1711 ptr->r.record.p.rmask = mask;
1712 return ptr;
1713}
1714
1715static unw_rec_list *
1716output_frgr_mem (gr_mask, fr_mask)
1717 unsigned int gr_mask;
1718 unsigned int fr_mask;
1719{
1720 unw_rec_list *ptr = alloc_record (frgr_mem);
1721 ptr->r.record.p.grmask = gr_mask;
1722 ptr->r.record.p.frmask = fr_mask;
1723 return ptr;
1724}
1725
1726static unw_rec_list *
1727output_gr_gr (mask, reg)
1728 unsigned int mask;
1729 unsigned int reg;
1730{
1731 unw_rec_list *ptr = alloc_record (gr_gr);
1732 ptr->r.record.p.grmask = mask;
1733 ptr->r.record.p.gr = reg;
1734 return ptr;
1735}
1736
1737static unw_rec_list *
1738output_gr_mem (mask)
1739 unsigned int mask;
1740{
1741 unw_rec_list *ptr = alloc_record (gr_mem);
1742 ptr->r.record.p.rmask = mask;
1743 return ptr;
1744}
1745
1746static unw_rec_list *
1747output_br_mem (unsigned int mask)
1748{
1749 unw_rec_list *ptr = alloc_record (br_mem);
1750 ptr->r.record.p.brmask = mask;
1751 return ptr;
1752}
1753
1754static unw_rec_list *
1755output_br_gr (save_mask, reg)
1756 unsigned int save_mask;
1757 unsigned int reg;
1758{
1759 unw_rec_list *ptr = alloc_record (br_gr);
1760 ptr->r.record.p.brmask = save_mask;
1761 ptr->r.record.p.gr = reg;
1762 return ptr;
1763}
1764
1765static unw_rec_list *
1766output_spill_base (offset)
1767 unsigned int offset;
1768{
1769 unw_rec_list *ptr = alloc_record (spill_base);
542d6675 1770 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1771 return ptr;
1772}
1773
1774static unw_rec_list *
1775output_unat_when ()
1776{
1777 unw_rec_list *ptr = alloc_record (unat_when);
1778 return ptr;
1779}
1780
1781static unw_rec_list *
1782output_unat_gr (gr)
1783 unsigned int gr;
1784{
1785 unw_rec_list *ptr = alloc_record (unat_gr);
1786 ptr->r.record.p.gr = gr;
1787 return ptr;
1788}
1789
1790static unw_rec_list *
1791output_unat_psprel (offset)
1792 unsigned int offset;
1793{
1794 unw_rec_list *ptr = alloc_record (unat_psprel);
542d6675 1795 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1796 return ptr;
1797}
1798
1799static unw_rec_list *
1800output_unat_sprel (offset)
1801 unsigned int offset;
1802{
1803 unw_rec_list *ptr = alloc_record (unat_sprel);
542d6675 1804 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1805 return ptr;
1806}
1807
1808static unw_rec_list *
1809output_lc_when ()
1810{
1811 unw_rec_list *ptr = alloc_record (lc_when);
1812 return ptr;
1813}
1814
1815static unw_rec_list *
1816output_lc_gr (gr)
1817 unsigned int gr;
1818{
1819 unw_rec_list *ptr = alloc_record (lc_gr);
1820 ptr->r.record.p.gr = gr;
1821 return ptr;
1822}
1823
1824static unw_rec_list *
1825output_lc_psprel (offset)
1826 unsigned int offset;
1827{
1828 unw_rec_list *ptr = alloc_record (lc_psprel);
542d6675 1829 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1830 return ptr;
1831}
1832
1833static unw_rec_list *
1834output_lc_sprel (offset)
1835 unsigned int offset;
1836{
1837 unw_rec_list *ptr = alloc_record (lc_sprel);
542d6675 1838 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1839 return ptr;
1840}
1841
1842static unw_rec_list *
1843output_fpsr_when ()
1844{
1845 unw_rec_list *ptr = alloc_record (fpsr_when);
1846 return ptr;
1847}
1848
1849static unw_rec_list *
1850output_fpsr_gr (gr)
1851 unsigned int gr;
1852{
1853 unw_rec_list *ptr = alloc_record (fpsr_gr);
1854 ptr->r.record.p.gr = gr;
1855 return ptr;
1856}
1857
1858static unw_rec_list *
1859output_fpsr_psprel (offset)
1860 unsigned int offset;
1861{
1862 unw_rec_list *ptr = alloc_record (fpsr_psprel);
542d6675 1863 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1864 return ptr;
1865}
1866
1867static unw_rec_list *
1868output_fpsr_sprel (offset)
1869 unsigned int offset;
1870{
1871 unw_rec_list *ptr = alloc_record (fpsr_sprel);
542d6675 1872 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1873 return ptr;
1874}
1875
1876static unw_rec_list *
1877output_priunat_when_gr ()
1878{
1879 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1880 return ptr;
1881}
1882
1883static unw_rec_list *
1884output_priunat_when_mem ()
1885{
1886 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1887 return ptr;
1888}
1889
1890static unw_rec_list *
1891output_priunat_gr (gr)
1892 unsigned int gr;
1893{
1894 unw_rec_list *ptr = alloc_record (priunat_gr);
1895 ptr->r.record.p.gr = gr;
1896 return ptr;
1897}
1898
1899static unw_rec_list *
1900output_priunat_psprel (offset)
1901 unsigned int offset;
1902{
1903 unw_rec_list *ptr = alloc_record (priunat_psprel);
542d6675 1904 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1905 return ptr;
1906}
1907
1908static unw_rec_list *
1909output_priunat_sprel (offset)
1910 unsigned int offset;
1911{
1912 unw_rec_list *ptr = alloc_record (priunat_sprel);
542d6675 1913 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1914 return ptr;
1915}
1916
1917static unw_rec_list *
1918output_bsp_when ()
1919{
1920 unw_rec_list *ptr = alloc_record (bsp_when);
1921 return ptr;
1922}
1923
1924static unw_rec_list *
1925output_bsp_gr (gr)
1926 unsigned int gr;
1927{
1928 unw_rec_list *ptr = alloc_record (bsp_gr);
1929 ptr->r.record.p.gr = gr;
1930 return ptr;
1931}
1932
1933static unw_rec_list *
1934output_bsp_psprel (offset)
1935 unsigned int offset;
1936{
1937 unw_rec_list *ptr = alloc_record (bsp_psprel);
542d6675 1938 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1939 return ptr;
1940}
1941
1942static unw_rec_list *
1943output_bsp_sprel (offset)
1944 unsigned int offset;
1945{
1946 unw_rec_list *ptr = alloc_record (bsp_sprel);
542d6675 1947 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1948 return ptr;
1949}
1950
1951static unw_rec_list *
1952output_bspstore_when ()
1953{
1954 unw_rec_list *ptr = alloc_record (bspstore_when);
1955 return ptr;
1956}
1957
1958static unw_rec_list *
1959output_bspstore_gr (gr)
1960 unsigned int gr;
1961{
1962 unw_rec_list *ptr = alloc_record (bspstore_gr);
1963 ptr->r.record.p.gr = gr;
1964 return ptr;
1965}
1966
1967static unw_rec_list *
1968output_bspstore_psprel (offset)
1969 unsigned int offset;
1970{
1971 unw_rec_list *ptr = alloc_record (bspstore_psprel);
542d6675 1972 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1973 return ptr;
1974}
1975
1976static unw_rec_list *
1977output_bspstore_sprel (offset)
1978 unsigned int offset;
1979{
1980 unw_rec_list *ptr = alloc_record (bspstore_sprel);
542d6675 1981 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1982 return ptr;
1983}
1984
1985static unw_rec_list *
1986output_rnat_when ()
1987{
1988 unw_rec_list *ptr = alloc_record (rnat_when);
1989 return ptr;
1990}
1991
1992static unw_rec_list *
1993output_rnat_gr (gr)
1994 unsigned int gr;
1995{
1996 unw_rec_list *ptr = alloc_record (rnat_gr);
1997 ptr->r.record.p.gr = gr;
1998 return ptr;
1999}
2000
2001static unw_rec_list *
2002output_rnat_psprel (offset)
2003 unsigned int offset;
2004{
2005 unw_rec_list *ptr = alloc_record (rnat_psprel);
542d6675 2006 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2007 return ptr;
2008}
2009
2010static unw_rec_list *
2011output_rnat_sprel (offset)
2012 unsigned int offset;
2013{
2014 unw_rec_list *ptr = alloc_record (rnat_sprel);
542d6675 2015 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2016 return ptr;
2017}
2018
2019static unw_rec_list *
e0c9811a
JW		 2020output_unwabi (abi, context)
2021 unsigned long abi;
2022 unsigned long context;
800eeca4 2023{
e0c9811a
JW		 2024 unw_rec_list *ptr = alloc_record (unwabi);
2025 ptr->r.record.p.abi = abi;
2026 ptr->r.record.p.context = context;
800eeca4
JW		 2027 return ptr;
2028}
2029
2030static unw_rec_list *
e0c9811a 2031output_epilogue (unsigned long ecount)
800eeca4 2032{
e0c9811a
JW		 2033 unw_rec_list *ptr = alloc_record (epilogue);
2034 ptr->r.record.b.ecount = ecount;
800eeca4
JW		 2035 return ptr;
2036}
2037
2038static unw_rec_list *
e0c9811a 2039output_label_state (unsigned long label)
800eeca4 2040{
e0c9811a
JW		 2041 unw_rec_list *ptr = alloc_record (label_state);
2042 ptr->r.record.b.label = label;
800eeca4
JW		 2043 return ptr;
2044}
2045
2046static unw_rec_list *
e0c9811a
JW		 2047output_copy_state (unsigned long label)
2048{
2049 unw_rec_list *ptr = alloc_record (copy_state);
2050 ptr->r.record.b.label = label;
2051 return ptr;
2052}
2053
2054static unw_rec_list *
2055output_spill_psprel (ab, reg, offset)
2056 unsigned int ab;
800eeca4
JW		 2057 unsigned int reg;
2058 unsigned int offset;
2059{
2060 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 2061 ptr->r.record.x.ab = ab;
800eeca4 2062 ptr->r.record.x.reg = reg;
542d6675 2063 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2064 return ptr;
2065}
2066
2067static unw_rec_list *
e0c9811a
JW		 2068output_spill_sprel (ab, reg, offset)
2069 unsigned int ab;
800eeca4
JW		 2070 unsigned int reg;
2071 unsigned int offset;
2072{
2073 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 2074 ptr->r.record.x.ab = ab;
800eeca4 2075 ptr->r.record.x.reg = reg;
542d6675 2076 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2077 return ptr;
2078}
2079
2080static unw_rec_list *
e0c9811a
JW		 2081output_spill_psprel_p (ab, reg, offset, predicate)
2082 unsigned int ab;
800eeca4
JW		 2083 unsigned int reg;
2084 unsigned int offset;
2085 unsigned int predicate;
2086{
2087 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 2088 ptr->r.record.x.ab = ab;
800eeca4 2089 ptr->r.record.x.reg = reg;
542d6675 2090 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2091 ptr->r.record.x.qp = predicate;
2092 return ptr;
2093}
2094
2095static unw_rec_list *
e0c9811a
JW		 2096output_spill_sprel_p (ab, reg, offset, predicate)
2097 unsigned int ab;
800eeca4
JW		 2098 unsigned int reg;
2099 unsigned int offset;
2100 unsigned int predicate;
2101{
2102 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 2103 ptr->r.record.x.ab = ab;
800eeca4 2104 ptr->r.record.x.reg = reg;
542d6675 2105 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2106 ptr->r.record.x.qp = predicate;
2107 return ptr;
2108}
2109
2110static unw_rec_list *
e0c9811a
JW		 2111output_spill_reg (ab, reg, targ_reg, xy)
2112 unsigned int ab;
800eeca4
JW		 2113 unsigned int reg;
2114 unsigned int targ_reg;
2115 unsigned int xy;
2116{
2117 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 2118 ptr->r.record.x.ab = ab;
800eeca4
JW		 2119 ptr->r.record.x.reg = reg;
2120 ptr->r.record.x.treg = targ_reg;
2121 ptr->r.record.x.xy = xy;
2122 return ptr;
2123}
2124
2125static unw_rec_list *
e0c9811a
JW		 2126output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2127 unsigned int ab;
800eeca4
JW		 2128 unsigned int reg;
2129 unsigned int targ_reg;
2130 unsigned int xy;
2131 unsigned int predicate;
2132{
2133 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 2134 ptr->r.record.x.ab = ab;
800eeca4
JW		 2135 ptr->r.record.x.reg = reg;
2136 ptr->r.record.x.treg = targ_reg;
2137 ptr->r.record.x.xy = xy;
2138 ptr->r.record.x.qp = predicate;
2139 return ptr;
2140}
2141
197865e8 2142/* Given a unw_rec_list process the correct format with the
800eeca4 2143 specified function. */
542d6675 2144
800eeca4
JW		 2145static void
2146process_one_record (ptr, f)
2147 unw_rec_list *ptr;
2148 vbyte_func f;
2149{
e0c9811a
JW		 2150 unsigned long fr_mask, gr_mask;
2151
197865e8 2152 switch (ptr->r.type)
800eeca4 2153 {
542d6675
KH		 2154 case gr_mem:
2155 case fr_mem:
2156 case br_mem:
2157 case frgr_mem:
2158 /* These are taken care of by prologue/prologue_gr. */
2159 break;
e0c9811a 2160
542d6675
KH		 2161 case prologue_gr:
2162 case prologue:
2163 if (ptr->r.type == prologue_gr)
2164 output_R2_format (f, ptr->r.record.r.grmask,
2165 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2166 else
800eeca4 2167 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
542d6675
KH		 2168
2169 /* Output descriptor(s) for union of register spills (if any). */
2170 gr_mask = ptr->r.record.r.mask.gr_mem;
2171 fr_mask = ptr->r.record.r.mask.fr_mem;
2172 if (fr_mask)
2173 {
2174 if ((fr_mask & ~0xfUL) == 0)
2175 output_P6_format (f, fr_mem, fr_mask);
2176 else
2177 {
2178 output_P5_format (f, gr_mask, fr_mask);
2179 gr_mask = 0;
2180 }
2181 }
2182 if (gr_mask)
2183 output_P6_format (f, gr_mem, gr_mask);
2184 if (ptr->r.record.r.mask.br_mem)
2185 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2186
2187 /* output imask descriptor if necessary: */
2188 if (ptr->r.record.r.mask.i)
2189 output_P4_format (f, ptr->r.record.r.mask.i,
2190 ptr->r.record.r.imask_size);
2191 break;
2192
2193 case body:
2194 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2195 break;
2196 case mem_stack_f:
2197 case mem_stack_v:
2198 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2199 ptr->r.record.p.size);
2200 break;
2201 case psp_gr:
2202 case rp_gr:
2203 case pfs_gr:
2204 case preds_gr:
2205 case unat_gr:
2206 case lc_gr:
2207 case fpsr_gr:
2208 case priunat_gr:
2209 case bsp_gr:
2210 case bspstore_gr:
2211 case rnat_gr:
2212 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2213 break;
2214 case rp_br:
2215 output_P3_format (f, rp_br, ptr->r.record.p.br);
2216 break;
2217 case psp_sprel:
2218 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2219 break;
2220 case rp_when:
2221 case pfs_when:
2222 case preds_when:
2223 case unat_when:
2224 case lc_when:
2225 case fpsr_when:
2226 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2227 break;
2228 case rp_psprel:
2229 case pfs_psprel:
2230 case preds_psprel:
2231 case unat_psprel:
2232 case lc_psprel:
2233 case fpsr_psprel:
2234 case spill_base:
2235 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2236 break;
2237 case rp_sprel:
2238 case pfs_sprel:
2239 case preds_sprel:
2240 case unat_sprel:
2241 case lc_sprel:
2242 case fpsr_sprel:
2243 case priunat_sprel:
2244 case bsp_sprel:
2245 case bspstore_sprel:
2246 case rnat_sprel:
2247 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2248 break;
2249 case gr_gr:
2250 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2251 break;
2252 case br_gr:
2253 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2254 break;
2255 case spill_mask:
2256 as_bad ("spill_mask record unimplemented.");
2257 break;
2258 case priunat_when_gr:
2259 case priunat_when_mem:
2260 case bsp_when:
2261 case bspstore_when:
2262 case rnat_when:
2263 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2264 break;
2265 case priunat_psprel:
2266 case bsp_psprel:
2267 case bspstore_psprel:
2268 case rnat_psprel:
2269 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2270 break;
2271 case unwabi:
2272 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2273 break;
2274 case epilogue:
2275 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2276 break;
2277 case label_state:
2278 case copy_state:
2279 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2280 break;
2281 case spill_psprel:
2282 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2283 ptr->r.record.x.reg, ptr->r.record.x.t,
2284 ptr->r.record.x.pspoff);
2285 break;
2286 case spill_sprel:
2287 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2288 ptr->r.record.x.reg, ptr->r.record.x.t,
2289 ptr->r.record.x.spoff);
2290 break;
2291 case spill_reg:
2292 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2293 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2294 ptr->r.record.x.treg, ptr->r.record.x.t);
2295 break;
2296 case spill_psprel_p:
2297 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2298 ptr->r.record.x.ab, ptr->r.record.x.reg,
2299 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2300 break;
2301 case spill_sprel_p:
2302 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2303 ptr->r.record.x.ab, ptr->r.record.x.reg,
2304 ptr->r.record.x.t, ptr->r.record.x.spoff);
2305 break;
2306 case spill_reg_p:
2307 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2308 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2309 ptr->r.record.x.xy, ptr->r.record.x.treg,
2310 ptr->r.record.x.t);
2311 break;
2312 default:
2313 as_bad ("record_type_not_valid");
2314 break;
800eeca4
JW		 2315 }
2316}
2317
197865e8 2318/* Given a unw_rec_list list, process all the records with
800eeca4
JW		 2319 the specified function. */
2320static void
2321process_unw_records (list, f)
2322 unw_rec_list *list;
2323 vbyte_func f;
2324{
2325 unw_rec_list *ptr;
2326 for (ptr = list; ptr; ptr = ptr->next)
2327 process_one_record (ptr, f);
2328}
2329
2330/* Determine the size of a record list in bytes. */
2331static int
2332calc_record_size (list)
2333 unw_rec_list *list;
2334{
2335 vbyte_count = 0;
2336 process_unw_records (list, count_output);
2337 return vbyte_count;
2338}
2339
e0c9811a
JW		 2340/* Update IMASK bitmask to reflect the fact that one or more registers
2341 of type TYPE are saved starting at instruction with index T. If N
2342 bits are set in REGMASK, it is assumed that instructions T through
2343 T+N-1 save these registers.
2344
2345 TYPE values:
2346 0: no save
2347 1: instruction saves next fp reg
2348 2: instruction saves next general reg
2349 3: instruction saves next branch reg */
2350static void
2351set_imask (region, regmask, t, type)
2352 unw_rec_list *region;
2353 unsigned long regmask;
2354 unsigned long t;
2355 unsigned int type;
2356{
2357 unsigned char *imask;
2358 unsigned long imask_size;
2359 unsigned int i;
2360 int pos;
2361
2362 imask = region->r.record.r.mask.i;
2363 imask_size = region->r.record.r.imask_size;
2364 if (!imask)
2365 {
542d6675 2366 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
e0c9811a
JW		 2367 imask = xmalloc (imask_size);
2368 memset (imask, 0, imask_size);
2369
2370 region->r.record.r.imask_size = imask_size;
2371 region->r.record.r.mask.i = imask;
2372 }
2373
542d6675
KH		 2374 i = (t / 4) + 1;
2375 pos = 2 * (3 - t % 4);
e0c9811a
JW		 2376 while (regmask)
2377 {
2378 if (i >= imask_size)
2379 {
2380 as_bad ("Ignoring attempt to spill beyond end of region");
2381 return;
2382 }
2383
2384 imask[i] |= (type & 0x3) << pos;
197865e8 2385
e0c9811a
JW		 2386 regmask &= (regmask - 1);
2387 pos -= 2;
2388 if (pos < 0)
2389 {
2390 pos = 0;
2391 ++i;
2392 }
2393 }
2394}
2395
2396static int
2397count_bits (unsigned long mask)
2398{
2399 int n = 0;
2400
2401 while (mask)
2402 {
2403 mask &= mask - 1;
2404 ++n;
2405 }
2406 return n;
2407}
2408
2409unsigned long
2410slot_index (unsigned long slot_addr, unsigned long first_addr)
2411{
542d6675 2412 return (3 * ((slot_addr >> 4) - (first_addr >> 4))
e0c9811a
JW		 2413 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2414}
2415
800eeca4
JW		 2416/* Given a complete record list, process any records which have
2417 unresolved fields, (ie length counts for a prologue). After
197865e8 2418 this has been run, all neccessary information should be available
800eeca4 2419 within each record to generate an image. */
542d6675 2420
800eeca4
JW		 2421static void
2422fixup_unw_records (list)
2423 unw_rec_list *list;
2424{
e0c9811a
JW		 2425 unw_rec_list *ptr, *region = 0;
2426 unsigned long first_addr = 0, rlen = 0, t;
2427
800eeca4
JW		 2428 for (ptr = list; ptr; ptr = ptr->next)
2429 {
2430 if (ptr->slot_number == SLOT_NUM_NOT_SET)
542d6675 2431 as_bad (" Insn slot not set in unwind record.");
e0c9811a 2432 t = slot_index (ptr->slot_number, first_addr);
800eeca4
JW		 2433 switch (ptr->r.type)
2434 {
542d6675
KH		 2435 case prologue:
2436 case prologue_gr:
2437 case body:
2438 {
2439 unw_rec_list *last;
2440 int size, dir_len = 0;
2441 unsigned long last_addr;
2442
2443 first_addr = ptr->slot_number;
2444 ptr->slot_number = 0;
2445 /* Find either the next body/prologue start, or the end of
2446 the list, and determine the size of the region. */
2447 last_addr = unwind.next_slot_number;
2448 for (last = ptr->next; last != NULL; last = last->next)
2449 if (last->r.type == prologue || last->r.type == prologue_gr
2450 || last->r.type == body)
2451 {
2452 last_addr = last->slot_number;
2453 break;
2454 }
2455 else if (!last->next)
2456 {
2457 /* In the absence of an explicit .body directive,
2458 the prologue ends after the last instruction
2459 covered by an unwind directive. */
2460 if (ptr->r.type != body)
2461 {
2462 last_addr = last->slot_number;
2463 switch (last->r.type)
2464 {
2465 case frgr_mem:
2466 dir_len = (count_bits (last->r.record.p.frmask)
2467 + count_bits (last->r.record.p.grmask));
2468 break;
2469 case fr_mem:
2470 case gr_mem:
2471 dir_len += count_bits (last->r.record.p.rmask);
2472 break;
2473 case br_mem:
2474 case br_gr:
2475 dir_len += count_bits (last->r.record.p.brmask);
2476 break;
2477 case gr_gr:
2478 dir_len += count_bits (last->r.record.p.grmask);
2479 break;
2480 default:
2481 dir_len = 1;
2482 break;
2483 }
2484 }
2485 break;
2486 }
2487 size = slot_index (last_addr, first_addr) + dir_len;
2488 rlen = ptr->r.record.r.rlen = size;
2489 region = ptr;
e0c9811a 2490 break;
542d6675
KH		 2491 }
2492 case epilogue:
2493 ptr->r.record.b.t = rlen - 1 - t;
2494 break;
e0c9811a 2495
542d6675
KH		 2496 case mem_stack_f:
2497 case mem_stack_v:
2498 case rp_when:
2499 case pfs_when:
2500 case preds_when:
2501 case unat_when:
2502 case lc_when:
2503 case fpsr_when:
2504 case priunat_when_gr:
2505 case priunat_when_mem:
2506 case bsp_when:
2507 case bspstore_when:
2508 case rnat_when:
2509 ptr->r.record.p.t = t;
2510 break;
e0c9811a 2511
542d6675
KH		 2512 case spill_reg:
2513 case spill_sprel:
2514 case spill_psprel:
2515 case spill_reg_p:
2516 case spill_sprel_p:
2517 case spill_psprel_p:
2518 ptr->r.record.x.t = t;
2519 break;
e0c9811a 2520
542d6675
KH		 2521 case frgr_mem:
2522 if (!region)
2523 {
2524 as_bad ("frgr_mem record before region record!\n");
2525 return;
2526 }
2527 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2528 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2529 set_imask (region, ptr->r.record.p.frmask, t, 1);
2530 set_imask (region, ptr->r.record.p.grmask, t, 2);
2531 break;
2532 case fr_mem:
2533 if (!region)
2534 {
2535 as_bad ("fr_mem record before region record!\n");
2536 return;
2537 }
2538 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2539 set_imask (region, ptr->r.record.p.rmask, t, 1);
2540 break;
2541 case gr_mem:
2542 if (!region)
2543 {
2544 as_bad ("gr_mem record before region record!\n");
2545 return;
2546 }
2547 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2548 set_imask (region, ptr->r.record.p.rmask, t, 2);
2549 break;
2550 case br_mem:
2551 if (!region)
2552 {
2553 as_bad ("br_mem record before region record!\n");
2554 return;
2555 }
2556 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2557 set_imask (region, ptr->r.record.p.brmask, t, 3);
2558 break;
e0c9811a 2559
542d6675
KH		 2560 case gr_gr:
2561 if (!region)
2562 {
2563 as_bad ("gr_gr record before region record!\n");
2564 return;
2565 }
2566 set_imask (region, ptr->r.record.p.grmask, t, 2);
2567 break;
2568 case br_gr:
2569 if (!region)
2570 {
2571 as_bad ("br_gr record before region record!\n");
2572 return;
2573 }
2574 set_imask (region, ptr->r.record.p.brmask, t, 3);
2575 break;
e0c9811a 2576
542d6675
KH		 2577 default:
2578 break;
800eeca4
JW		 2579 }
2580 }
2581}
2582
2583/* Generate an unwind image from a record list. Returns the number of
2584 bytes in the resulting image. The memory image itselof is returned
2585 in the 'ptr' parameter. */
2586static int
2587output_unw_records (list, ptr)
2588 unw_rec_list *list;
2589 void **ptr;
2590{
2591 int size, x, extra = 0;
2592 unsigned char *mem;
2593
2594 fixup_unw_records (list);
2595 size = calc_record_size (list);
2596
2597 /* pad to 8 byte boundry. */
2598 x = size % 8;
2599 if (x != 0)
2600 extra = 8 - x;
2601 /* Add 8 for the header + 8 more bytes for the personality offset. */
2602 mem = xmalloc (size + extra + 16);
2603
2604 vbyte_mem_ptr = mem + 8;
2605 /* Clear the padding area and personality. */
2606 memset (mem + 8 + size, 0 , extra + 8);
2607 /* Initialize the header area. */
efcc5914
JW		 2608 md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
2609 | (unwind.personality_routine
2610 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2611 : 0)
e4c58b25
JW		 2612 | ((size + extra) / 8)), /* length (dwords) */
2613 8);
800eeca4
JW		 2614
2615 process_unw_records (list, output_vbyte_mem);
2616
2617 *ptr = mem;
2618 return size + extra + 16;
2619}
2620
e0c9811a
JW		 2621static int
2622convert_expr_to_ab_reg (e, ab, regp)
2623 expressionS *e;
2624 unsigned int *ab;
2625 unsigned int *regp;
2626{
2627 unsigned int reg;
2628
2629 if (e->X_op != O_register)
2630 return 0;
2631
2632 reg = e->X_add_number;
2633 if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
2634 {
2635 *ab = 0;
2636 *regp = reg - REG_GR;
2637 }
2638 else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
2639 || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
2640 {
2641 *ab = 1;
2642 *regp = reg - REG_FR;
2643 }
2644 else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
2645 {
2646 *ab = 2;
2647 *regp = reg - REG_BR;
2648 }
2649 else
2650 {
2651 *ab = 3;
2652 switch (reg)
2653 {
2654 case REG_PR: *regp = 0; break;
2655 case REG_PSP: *regp = 1; break;
2656 case REG_PRIUNAT: *regp = 2; break;
2657 case REG_BR + 0: *regp = 3; break;
2658 case REG_AR + AR_BSP: *regp = 4; break;
2659 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2660 case REG_AR + AR_RNAT: *regp = 6; break;
2661 case REG_AR + AR_UNAT: *regp = 7; break;
2662 case REG_AR + AR_FPSR: *regp = 8; break;
2663 case REG_AR + AR_PFS: *regp = 9; break;
2664 case REG_AR + AR_LC: *regp = 10; break;
2665
2666 default:
2667 return 0;
2668 }
2669 }
2670 return 1;
197865e8 2671}
e0c9811a
JW		 2672
2673static int
2674convert_expr_to_xy_reg (e, xy, regp)
2675 expressionS *e;
2676 unsigned int *xy;
2677 unsigned int *regp;
2678{
2679 unsigned int reg;
2680
2681 if (e->X_op != O_register)
2682 return 0;
2683
2684 reg = e->X_add_number;
2685
2686 if (reg >= REG_GR && reg <= REG_GR + 127)
2687 {
2688 *xy = 0;
2689 *regp = reg - REG_GR;
2690 }
2691 else if (reg >= REG_FR && reg <= REG_FR + 127)
2692 {
2693 *xy = 1;
2694 *regp = reg - REG_FR;
2695 }
2696 else if (reg >= REG_BR && reg <= REG_BR + 7)
2697 {
2698 *xy = 2;
2699 *regp = reg - REG_BR;
2700 }
2701 else
2702 return -1;
2703 return 1;
197865e8 2704}
e0c9811a 2705
800eeca4
JW		 2706static void
2707dot_radix (dummy)
2708 int dummy;
2709{
2710 int radix;
2711
2712 SKIP_WHITESPACE ();
2713 radix = *input_line_pointer++;
2714
2715 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2716 {
2717 as_bad ("Radix `%c' unsupported", *input_line_pointer);
542d6675 2718 ignore_rest_of_line ();
800eeca4
JW		 2719 return;
2720 }
2721}
2722
2723/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2724static void
2725dot_special_section (which)
2726 int which;
2727{
2728 set_section ((char *) special_section_name[which]);
2729}
2730
2731static void
2732add_unwind_entry (ptr)
2733 unw_rec_list *ptr;
2734{
e0c9811a
JW		 2735 if (unwind.tail)
2736 unwind.tail->next = ptr;
800eeca4 2737 else
e0c9811a
JW		 2738 unwind.list = ptr;
2739 unwind.tail = ptr;
800eeca4
JW		 2740
2741 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW		 2742 if (unwind.current_entry == NULL)
2743 unwind.current_entry = ptr;
800eeca4
JW		 2744}
2745
197865e8 2746static void
800eeca4
JW		 2747dot_fframe (dummy)
2748 int dummy;
2749{
2750 expressionS e;
e0c9811a 2751
800eeca4 2752 parse_operand (&e);
197865e8 2753
800eeca4
JW		 2754 if (e.X_op != O_constant)
2755 as_bad ("Operand to .fframe must be a constant");
2756 else
e0c9811a
JW		 2757 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2758}
2759
197865e8 2760static void
e0c9811a
JW		 2761dot_vframe (dummy)
2762 int dummy;
2763{
2764 expressionS e;
2765 unsigned reg;
2766
2767 parse_operand (&e);
2768 reg = e.X_add_number - REG_GR;
2769 if (e.X_op == O_register && reg < 128)
800eeca4 2770 {
e0c9811a 2771 add_unwind_entry (output_mem_stack_v ());
30d25259
RH		 2772 if (! (unwind.prologue_mask & 2))
2773 add_unwind_entry (output_psp_gr (reg));
800eeca4 2774 }
e0c9811a
JW		 2775 else
2776 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW		 2777}
2778
197865e8 2779static void
e0c9811a 2780dot_vframesp (dummy)
800eeca4
JW		 2781 int dummy;
2782{
e0c9811a
JW		 2783 expressionS e;
2784
2785 parse_operand (&e);
2786 if (e.X_op == O_constant)
2787 {
2788 add_unwind_entry (output_mem_stack_v ());
2789 add_unwind_entry (output_psp_sprel (e.X_add_number));
2790 }
2791 else
2792 as_bad ("First operand to .vframesp must be a general register");
2793}
2794
197865e8 2795static void
e0c9811a
JW		 2796dot_vframepsp (dummy)
2797 int dummy;
2798{
2799 expressionS e;
2800
2801 parse_operand (&e);
2802 if (e.X_op == O_constant)
2803 {
2804 add_unwind_entry (output_mem_stack_v ());
2805 add_unwind_entry (output_psp_sprel (e.X_add_number));
2806 }
2807 else
2808 as_bad ("First operand to .vframepsp must be a general register");
800eeca4
JW		 2809}
2810
197865e8 2811static void
800eeca4
JW		 2812dot_save (dummy)
2813 int dummy;
2814{
2815 expressionS e1, e2;
2816 int sep;
2817 int reg1, reg2;
2818
2819 sep = parse_operand (&e1);
2820 if (sep != ',')
2821 as_bad ("No second operand to .save");
2822 sep = parse_operand (&e2);
2823
e0c9811a 2824 reg1 = e1.X_add_number;
800eeca4 2825 reg2 = e2.X_add_number - REG_GR;
197865e8 2826
800eeca4 2827 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 2828 if (e1.X_op == O_register)
800eeca4 2829 {
542d6675 2830 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
800eeca4
JW		 2831 {
2832 switch (reg1)
2833 {
542d6675
KH		 2834 case REG_AR + AR_BSP:
2835 add_unwind_entry (output_bsp_when ());
2836 add_unwind_entry (output_bsp_gr (reg2));
2837 break;
2838 case REG_AR + AR_BSPSTORE:
2839 add_unwind_entry (output_bspstore_when ());
2840 add_unwind_entry (output_bspstore_gr (reg2));
2841 break;
2842 case REG_AR + AR_RNAT:
2843 add_unwind_entry (output_rnat_when ());
2844 add_unwind_entry (output_rnat_gr (reg2));
2845 break;
2846 case REG_AR + AR_UNAT:
2847 add_unwind_entry (output_unat_when ());
2848 add_unwind_entry (output_unat_gr (reg2));
2849 break;
2850 case REG_AR + AR_FPSR:
2851 add_unwind_entry (output_fpsr_when ());
2852 add_unwind_entry (output_fpsr_gr (reg2));
2853 break;
2854 case REG_AR + AR_PFS:
2855 add_unwind_entry (output_pfs_when ());
2856 if (! (unwind.prologue_mask & 4))
2857 add_unwind_entry (output_pfs_gr (reg2));
2858 break;
2859 case REG_AR + AR_LC:
2860 add_unwind_entry (output_lc_when ());
2861 add_unwind_entry (output_lc_gr (reg2));
2862 break;
2863 case REG_BR:
2864 add_unwind_entry (output_rp_when ());
2865 if (! (unwind.prologue_mask & 8))
2866 add_unwind_entry (output_rp_gr (reg2));
2867 break;
2868 case REG_PR:
2869 add_unwind_entry (output_preds_when ());
2870 if (! (unwind.prologue_mask & 1))
2871 add_unwind_entry (output_preds_gr (reg2));
2872 break;
2873 case REG_PRIUNAT:
2874 add_unwind_entry (output_priunat_when_gr ());
2875 add_unwind_entry (output_priunat_gr (reg2));
2876 break;
2877 default:
2878 as_bad ("First operand not a valid register");
800eeca4
JW		 2879 }
2880 }
2881 else
2882 as_bad (" Second operand not a valid register");
2883 }
2884 else
e0c9811a 2885 as_bad ("First operand not a register");
800eeca4
JW		 2886}
2887
197865e8 2888static void
800eeca4
JW		 2889dot_restore (dummy)
2890 int dummy;
2891{
e0c9811a
JW		 2892 expressionS e1, e2;
2893 unsigned long ecount = 0;
2894 int sep;
2895
2896 sep = parse_operand (&e1);
2897 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2898 {
2899 as_bad ("First operand to .restore must be stack pointer (sp)");
2900 return;
2901 }
2902
2903 if (sep == ',')
2904 {
2905 parse_operand (&e2);
2906 if (e1.X_op != O_constant)
2907 {
2908 as_bad ("Second operand to .restore must be constant");
2909 return;
2910 }
2911 ecount = e1.X_op;
2912 }
2913 add_unwind_entry (output_epilogue (ecount));
2914}
2915
197865e8 2916static void
e0c9811a
JW		 2917dot_restorereg (dummy)
2918 int dummy;
2919{
2920 unsigned int ab, reg;
2921 expressionS e;
2922
2923 parse_operand (&e);
2924
2925 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
2926 {
2927 as_bad ("First operand to .restorereg must be a preserved register");
2928 return;
2929 }
2930 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
2931}
2932
197865e8 2933static void
e0c9811a
JW		 2934dot_restorereg_p (dummy)
2935 int dummy;
2936{
2937 unsigned int qp, ab, reg;
2938 expressionS e1, e2;
2939 int sep;
2940
2941 sep = parse_operand (&e1);
2942 if (sep != ',')
2943 {
2944 as_bad ("No second operand to .restorereg.p");
2945 return;
2946 }
2947
2948 parse_operand (&e2);
2949
2950 qp = e1.X_add_number - REG_P;
2951 if (e1.X_op != O_register || qp > 63)
2952 {
2953 as_bad ("First operand to .restorereg.p must be a predicate");
2954 return;
2955 }
2956
2957 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
2958 {
2959 as_bad ("Second operand to .restorereg.p must be a preserved register");
2960 return;
2961 }
2962 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW		 2963}
2964
2965static int
2966generate_unwind_image ()
2967{
2968 int size;
2969 unsigned char *unw_rec;
800eeca4 2970
10850f29
JW		 2971 /* Force out pending instructions, to make sure all unwind records have
2972 a valid slot_number field. */
2973 ia64_flush_insns ();
2974
800eeca4 2975 /* Generate the unwind record. */
150f24a2 2976 size = output_unw_records (unwind.list, (void **) &unw_rec);
e0c9811a
JW		 2977 if (size % 8 != 0)
2978 as_bad ("Unwind record is not a multiple of 8 bytes.");
800eeca4
JW		 2979
2980 /* If there are unwind records, switch sections, and output the info. */
2981 if (size != 0)
2982 {
800eeca4 2983 unsigned char *where;
800eeca4 2984 expressionS exp;
800eeca4
JW		 2985 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
2986
2987 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 2988 unwind.info = expr_build_dot ();
800eeca4 2989
542d6675 2990 where = (unsigned char *) frag_more (size);
800eeca4
JW		 2991
2992 /* Issue a label for this address, and keep track of it to put it
2993 in the unwind section. */
2994
2995 /* Copy the information from the unwind record into this section. The
2996 data is already in the correct byte order. */
2997 memcpy (where, unw_rec, size);
2998 /* Add the personality address to the image. */
e0c9811a 2999 if (unwind.personality_routine != 0)
542d6675 3000 {
800eeca4 3001 exp.X_op = O_symbol;
e0c9811a 3002 exp.X_add_symbol = unwind.personality_routine;
800eeca4
JW		 3003 exp.X_add_number = 0;
3004 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
3005 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
e0c9811a 3006 unwind.personality_routine = 0;
542d6675 3007 }
800eeca4
JW		 3008 obj_elf_previous (0);
3009 }
3010
e0c9811a
JW		 3011 free_list_records (unwind.list);
3012 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW		 3013
3014 return size;
3015}
3016
197865e8 3017static void
542d6675 3018dot_handlerdata (dummy)
800eeca4
JW		 3019 int dummy;
3020{
3021 generate_unwind_image ();
e0c9811a 3022 demand_empty_rest_of_line ();
800eeca4
JW		 3023}
3024
197865e8 3025static void
800eeca4
JW		 3026dot_unwentry (dummy)
3027 int dummy;
3028{
e0c9811a 3029 demand_empty_rest_of_line ();
800eeca4
JW		 3030}
3031
197865e8 3032static void
800eeca4
JW		 3033dot_altrp (dummy)
3034 int dummy;
3035{
e0c9811a
JW		 3036 expressionS e;
3037 unsigned reg;
3038
3039 parse_operand (&e);
3040 reg = e.X_add_number - REG_BR;
3041 if (e.X_op == O_register && reg < 8)
3042 add_unwind_entry (output_rp_br (reg));
3043 else
3044 as_bad ("First operand not a valid branch register");
800eeca4
JW		 3045}
3046
197865e8 3047static void
e0c9811a
JW		 3048dot_savemem (psprel)
3049 int psprel;
800eeca4
JW		 3050{
3051 expressionS e1, e2;
3052 int sep;
3053 int reg1, val;
3054
3055 sep = parse_operand (&e1);
3056 if (sep != ',')
e0c9811a 3057 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW		 3058 sep = parse_operand (&e2);
3059
e0c9811a 3060 reg1 = e1.X_add_number;
800eeca4 3061 val = e2.X_add_number;
197865e8 3062
800eeca4 3063 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3064 if (e1.X_op == O_register)
800eeca4
JW		 3065 {
3066 if (e2.X_op == O_constant)
3067 {
3068 switch (reg1)
3069 {
542d6675
KH		 3070 case REG_AR + AR_BSP:
3071 add_unwind_entry (output_bsp_when ());
3072 add_unwind_entry ((psprel
3073 ? output_bsp_psprel
3074 : output_bsp_sprel) (val));
3075 break;
3076 case REG_AR + AR_BSPSTORE:
3077 add_unwind_entry (output_bspstore_when ());
3078 add_unwind_entry ((psprel
3079 ? output_bspstore_psprel
3080 : output_bspstore_sprel) (val));
3081 break;
3082 case REG_AR + AR_RNAT:
3083 add_unwind_entry (output_rnat_when ());
3084 add_unwind_entry ((psprel
3085 ? output_rnat_psprel
3086 : output_rnat_sprel) (val));
3087 break;
3088 case REG_AR + AR_UNAT:
3089 add_unwind_entry (output_unat_when ());
3090 add_unwind_entry ((psprel
3091 ? output_unat_psprel
3092 : output_unat_sprel) (val));
3093 break;
3094 case REG_AR + AR_FPSR:
3095 add_unwind_entry (output_fpsr_when ());
3096 add_unwind_entry ((psprel
3097 ? output_fpsr_psprel
3098 : output_fpsr_sprel) (val));
3099 break;
3100 case REG_AR + AR_PFS:
3101 add_unwind_entry (output_pfs_when ());
3102 add_unwind_entry ((psprel
3103 ? output_pfs_psprel
3104 : output_pfs_sprel) (val));
3105 break;
3106 case REG_AR + AR_LC:
3107 add_unwind_entry (output_lc_when ());
3108 add_unwind_entry ((psprel
3109 ? output_lc_psprel
3110 : output_lc_sprel) (val));
3111 break;
3112 case REG_BR:
3113 add_unwind_entry (output_rp_when ());
3114 add_unwind_entry ((psprel
3115 ? output_rp_psprel
3116 : output_rp_sprel) (val));
3117 break;
3118 case REG_PR:
3119 add_unwind_entry (output_preds_when ());
3120 add_unwind_entry ((psprel
3121 ? output_preds_psprel
3122 : output_preds_sprel) (val));
3123 break;
3124 case REG_PRIUNAT:
3125 add_unwind_entry (output_priunat_when_mem ());
3126 add_unwind_entry ((psprel
3127 ? output_priunat_psprel
3128 : output_priunat_sprel) (val));
3129 break;
3130 default:
3131 as_bad ("First operand not a valid register");
800eeca4
JW		 3132 }
3133 }
3134 else
3135 as_bad (" Second operand not a valid constant");
3136 }
3137 else
e0c9811a 3138 as_bad ("First operand not a register");
800eeca4
JW		 3139}
3140
197865e8 3141static void
800eeca4
JW		 3142dot_saveg (dummy)
3143 int dummy;
3144{
3145 expressionS e1, e2;
3146 int sep;
3147 sep = parse_operand (&e1);
3148 if (sep == ',')
3149 parse_operand (&e2);
197865e8 3150
800eeca4
JW		 3151 if (e1.X_op != O_constant)
3152 as_bad ("First operand to .save.g must be a constant.");
3153 else
3154 {
3155 int grmask = e1.X_add_number;
3156 if (sep != ',')
3157 add_unwind_entry (output_gr_mem (grmask));
3158 else
542d6675 3159 {
800eeca4 3160 int reg = e2.X_add_number - REG_GR;
542d6675 3161 if (e2.X_op == O_register && reg >= 0 && reg < 128)
800eeca4
JW		 3162 add_unwind_entry (output_gr_gr (grmask, reg));
3163 else
3164 as_bad ("Second operand is an invalid register.");
3165 }
3166 }
3167}
3168
197865e8 3169static void
800eeca4
JW		 3170dot_savef (dummy)
3171 int dummy;
3172{
e0c9811a 3173 expressionS e1;
800eeca4
JW		 3174 int sep;
3175 sep = parse_operand (&e1);
197865e8 3176
800eeca4
JW		 3177 if (e1.X_op != O_constant)
3178 as_bad ("Operand to .save.f must be a constant.");
3179 else
e0c9811a 3180 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW		 3181}
3182
197865e8 3183static void
800eeca4
JW		 3184dot_saveb (dummy)
3185 int dummy;
3186{
e0c9811a
JW		 3187 expressionS e1, e2;
3188 unsigned int reg;
3189 unsigned char sep;
3190 int brmask;
3191
800eeca4 3192 sep = parse_operand (&e1);
800eeca4 3193 if (e1.X_op != O_constant)
800eeca4 3194 {
e0c9811a
JW		 3195 as_bad ("First operand to .save.b must be a constant.");
3196 return;
800eeca4 3197 }
e0c9811a
JW		 3198 brmask = e1.X_add_number;
3199
3200 if (sep == ',')
3201 {
3202 sep = parse_operand (&e2);
3203 reg = e2.X_add_number - REG_GR;
3204 if (e2.X_op != O_register || reg > 127)
3205 {
3206 as_bad ("Second operand to .save.b must be a general register.");
3207 return;
3208 }
3209 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3210 }
3211 else
3212 add_unwind_entry (output_br_mem (brmask));
3213
3214 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3215 ignore_rest_of_line ();
800eeca4
JW		 3216}
3217
197865e8 3218static void
800eeca4
JW		 3219dot_savegf (dummy)
3220 int dummy;
3221{
3222 expressionS e1, e2;
3223 int sep;
3224 sep = parse_operand (&e1);
3225 if (sep == ',')
3226 parse_operand (&e2);
197865e8 3227
800eeca4
JW		 3228 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3229 as_bad ("Both operands of .save.gf must be constants.");
3230 else
3231 {
3232 int grmask = e1.X_add_number;
3233 int frmask = e2.X_add_number;
3234 add_unwind_entry (output_frgr_mem (grmask, frmask));
3235 }
3236}
3237
197865e8 3238static void
800eeca4
JW		 3239dot_spill (dummy)
3240 int dummy;
3241{
3242 expressionS e;
e0c9811a
JW		 3243 unsigned char sep;
3244
3245 sep = parse_operand (&e);
3246 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3247 ignore_rest_of_line ();
197865e8 3248
800eeca4
JW		 3249 if (e.X_op != O_constant)
3250 as_bad ("Operand to .spill must be a constant");
3251 else
e0c9811a
JW		 3252 add_unwind_entry (output_spill_base (e.X_add_number));
3253}
3254
3255static void
3256dot_spillreg (dummy)
3257 int dummy;
3258{
3259 int sep, ab, xy, reg, treg;
3260 expressionS e1, e2;
3261
3262 sep = parse_operand (&e1);
3263 if (sep != ',')
3264 {
3265 as_bad ("No second operand to .spillreg");
3266 return;
3267 }
3268
3269 parse_operand (&e2);
3270
3271 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3272 {
e0c9811a
JW		 3273 as_bad ("First operand to .spillreg must be a preserved register");
3274 return;
800eeca4 3275 }
e0c9811a
JW		 3276
3277 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3278 {
3279 as_bad ("Second operand to .spillreg must be a register");
3280 return;
3281 }
3282
3283 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3284}
3285
3286static void
3287dot_spillmem (psprel)
3288 int psprel;
3289{
3290 expressionS e1, e2;
3291 int sep, ab, reg;
3292
3293 sep = parse_operand (&e1);
3294 if (sep != ',')
3295 {
3296 as_bad ("Second operand missing");
3297 return;
3298 }
3299
3300 parse_operand (&e2);
3301
3302 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3303 {
3304 as_bad ("First operand to .spill%s must be a preserved register",
3305 psprel ? "psp" : "sp");
3306 return;
3307 }
3308
3309 if (e2.X_op != O_constant)
3310 {
3311 as_bad ("Second operand to .spill%s must be a constant",
3312 psprel ? "psp" : "sp");
3313 return;
3314 }
3315
3316 if (psprel)
3317 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3318 else
3319 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3320}
3321
3322static void
3323dot_spillreg_p (dummy)
3324 int dummy;
3325{
3326 int sep, ab, xy, reg, treg;
3327 expressionS e1, e2, e3;
3328 unsigned int qp;
3329
3330 sep = parse_operand (&e1);
3331 if (sep != ',')
3332 {
3333 as_bad ("No second and third operand to .spillreg.p");
3334 return;
3335 }
3336
3337 sep = parse_operand (&e2);
3338 if (sep != ',')
3339 {
3340 as_bad ("No third operand to .spillreg.p");
3341 return;
3342 }
3343
3344 parse_operand (&e3);
3345
3346 qp = e1.X_add_number - REG_P;
3347
3348 if (e1.X_op != O_register || qp > 63)
3349 {
3350 as_bad ("First operand to .spillreg.p must be a predicate");
3351 return;
3352 }
3353
3354 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3355 {
3356 as_bad ("Second operand to .spillreg.p must be a preserved register");
3357 return;
3358 }
3359
3360 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3361 {
3362 as_bad ("Third operand to .spillreg.p must be a register");
3363 return;
3364 }
3365
3366 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3367}
3368
3369static void
3370dot_spillmem_p (psprel)
3371 int psprel;
3372{
3373 expressionS e1, e2, e3;
3374 int sep, ab, reg;
3375 unsigned int qp;
3376
3377 sep = parse_operand (&e1);
3378 if (sep != ',')
3379 {
3380 as_bad ("Second operand missing");
3381 return;
3382 }
3383
3384 parse_operand (&e2);
3385 if (sep != ',')
3386 {
3387 as_bad ("Second operand missing");
3388 return;
3389 }
3390
3391 parse_operand (&e3);
3392
3393 qp = e1.X_add_number - REG_P;
3394 if (e1.X_op != O_register || qp > 63)
3395 {
3396 as_bad ("First operand to .spill%s_p must be a predicate",
3397 psprel ? "psp" : "sp");
3398 return;
3399 }
3400
3401 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3402 {
3403 as_bad ("Second operand to .spill%s_p must be a preserved register",
3404 psprel ? "psp" : "sp");
3405 return;
3406 }
3407
3408 if (e3.X_op != O_constant)
3409 {
3410 as_bad ("Third operand to .spill%s_p must be a constant",
3411 psprel ? "psp" : "sp");
3412 return;
3413 }
3414
3415 if (psprel)
3416 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3417 else
3418 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3419}
3420
3421static void
3422dot_label_state (dummy)
3423 int dummy;
3424{
3425 expressionS e;
3426
3427 parse_operand (&e);
3428 if (e.X_op != O_constant)
3429 {
3430 as_bad ("Operand to .label_state must be a constant");
3431 return;
3432 }
3433 add_unwind_entry (output_label_state (e.X_add_number));
3434}
3435
3436static void
3437dot_copy_state (dummy)
3438 int dummy;
3439{
3440 expressionS e;
3441
3442 parse_operand (&e);
3443 if (e.X_op != O_constant)
3444 {
3445 as_bad ("Operand to .copy_state must be a constant");
3446 return;
3447 }
3448 add_unwind_entry (output_copy_state (e.X_add_number));
800eeca4
JW		 3449}
3450
197865e8 3451static void
800eeca4
JW		 3452dot_unwabi (dummy)
3453 int dummy;
3454{
e0c9811a
JW		 3455 expressionS e1, e2;
3456 unsigned char sep;
3457
3458 sep = parse_operand (&e1);
3459 if (sep != ',')
3460 {
3461 as_bad ("Second operand to .unwabi missing");
3462 return;
3463 }
3464 sep = parse_operand (&e2);
3465 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3466 ignore_rest_of_line ();
3467
3468 if (e1.X_op != O_constant)
3469 {
3470 as_bad ("First operand to .unwabi must be a constant");
3471 return;
3472 }
3473
3474 if (e2.X_op != O_constant)
3475 {
3476 as_bad ("Second operand to .unwabi must be a constant");
3477 return;
3478 }
3479
3480 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW		 3481}
3482
197865e8 3483static void
800eeca4
JW		 3484dot_personality (dummy)
3485 int dummy;
3486{
3487 char *name, *p, c;
3488 SKIP_WHITESPACE ();
3489 name = input_line_pointer;
3490 c = get_symbol_end ();
3491 p = input_line_pointer;
e0c9811a 3492 unwind.personality_routine = symbol_find_or_make (name);
800eeca4
JW		 3493 *p = c;
3494 SKIP_WHITESPACE ();
3495 demand_empty_rest_of_line ();
3496}
3497
3498static void
3499dot_proc (dummy)
3500 int dummy;
3501{
3502 char *name, *p, c;
3503 symbolS *sym;
3504
e0c9811a
JW		 3505 unwind.proc_start = expr_build_dot ();
3506 /* Parse names of main and alternate entry points and mark them as
542d6675 3507 function symbols: */
800eeca4
JW		 3508 while (1)
3509 {
3510 SKIP_WHITESPACE ();
3511 name = input_line_pointer;
3512 c = get_symbol_end ();
3513 p = input_line_pointer;
3514 sym = symbol_find_or_make (name);
e0c9811a 3515 if (unwind.proc_start == 0)
542d6675 3516 {
e0c9811a 3517 unwind.proc_start = sym;
800eeca4
JW		 3518 }
3519 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3520 *p = c;
3521 SKIP_WHITESPACE ();
3522 if (*input_line_pointer != ',')
3523 break;
3524 ++input_line_pointer;
3525 }
3526 demand_empty_rest_of_line ();
3527 ia64_do_align (16);
3528
e0c9811a
JW		 3529 unwind.list = unwind.tail = unwind.current_entry = NULL;
3530 unwind.personality_routine = 0;
800eeca4
JW		 3531}
3532
3533static void
3534dot_body (dummy)
3535 int dummy;
3536{
e0c9811a 3537 unwind.prologue = 0;
30d25259
RH		 3538 unwind.prologue_mask = 0;
3539
800eeca4 3540 add_unwind_entry (output_body ());
e0c9811a 3541 demand_empty_rest_of_line ();
800eeca4
JW		 3542}
3543
3544static void
3545dot_prologue (dummy)
3546 int dummy;
3547{
e0c9811a 3548 unsigned char sep;
30d25259 3549 int mask = 0, grsave;
e0c9811a 3550
e0c9811a 3551 if (!is_it_end_of_statement ())
800eeca4
JW		 3552 {
3553 expressionS e1, e2;
800eeca4
JW		 3554 sep = parse_operand (&e1);
3555 if (sep != ',')
3556 as_bad ("No second operand to .prologue");
3557 sep = parse_operand (&e2);
e0c9811a 3558 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
542d6675 3559 ignore_rest_of_line ();
800eeca4
JW		 3560
3561 if (e1.X_op == O_constant)
542d6675 3562 {
30d25259
RH		 3563 mask = e1.X_add_number;
3564
800eeca4 3565 if (e2.X_op == O_constant)
30d25259
RH		 3566 grsave = e2.X_add_number;
3567 else if (e2.X_op == O_register
3568 && (grsave = e2.X_add_number - REG_GR) < 128)
3569 ;
800eeca4 3570 else
30d25259
RH		 3571 as_bad ("Second operand not a constant or general register");
3572
3573 add_unwind_entry (output_prologue_gr (mask, grsave));
800eeca4
JW		 3574 }
3575 else
3576 as_bad ("First operand not a constant");
3577 }
3578 else
3579 add_unwind_entry (output_prologue ());
30d25259
RH		 3580
3581 unwind.prologue = 1;
3582 unwind.prologue_mask = mask;
800eeca4
JW		 3583}
3584
3585static void
3586dot_endp (dummy)
3587 int dummy;
3588{
3589 expressionS e;
3590 unsigned char *ptr;
44f5c83a 3591 int bytes_per_address;
800eeca4
JW		 3592 long where;
3593 segT saved_seg;
3594 subsegT saved_subseg;
3595
3596 saved_seg = now_seg;
3597 saved_subseg = now_subseg;
3598
3599 expression (&e);
3600 demand_empty_rest_of_line ();
3601
3602 insn_group_break (1, 0, 0);
800eeca4
JW		 3603
3604 /* If there was a .handlerdata, we haven't generated an image yet. */
e0c9811a 3605 if (unwind.info == 0)
800eeca4
JW		 3606 {
3607 generate_unwind_image ();
3608 }
3609
3610 subseg_set (md.last_text_seg, 0);
e0c9811a 3611 unwind.proc_end = expr_build_dot ();
800eeca4
JW		 3612
3613 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3614 ptr = frag_more (24);
3615 where = frag_now_fix () - 24;
44f5c83a 3616 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
800eeca4
JW		 3617
3618 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3619 e.X_op = O_pseudo_fixup;
3620 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3621 e.X_add_number = 0;
e0c9811a 3622 e.X_add_symbol = unwind.proc_start;
44f5c83a 3623 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
800eeca4
JW		 3624
3625 e.X_op = O_pseudo_fixup;
3626 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3627 e.X_add_number = 0;
e0c9811a 3628 e.X_add_symbol = unwind.proc_end;
44f5c83a 3629 ia64_cons_fix_new (frag_now, where + bytes_per_address, bytes_per_address, &e);
800eeca4 3630
e0c9811a 3631 if (unwind.info != 0)
800eeca4
JW		 3632 {
3633 e.X_op = O_pseudo_fixup;
3634 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3635 e.X_add_number = 0;
e0c9811a 3636 e.X_add_symbol = unwind.info;
44f5c83a 3637 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), bytes_per_address, &e);
800eeca4
JW		 3638 }
3639 else
44f5c83a 3640 md_number_to_chars (ptr + (bytes_per_address * 2), 0, bytes_per_address);
800eeca4
JW		 3641
3642 subseg_set (saved_seg, saved_subseg);
e0c9811a 3643 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW		 3644}
3645
3646static void
3647dot_template (template)
3648 int template;
3649{
3650 CURR_SLOT.user_template = template;
3651}
3652
3653static void
3654dot_regstk (dummy)
3655 int dummy;
3656{
3657 int ins, locs, outs, rots;
3658
3659 if (is_it_end_of_statement ())
3660 ins = locs = outs = rots = 0;
3661 else
3662 {
3663 ins = get_absolute_expression ();
3664 if (*input_line_pointer++ != ',')
3665 goto err;
3666 locs = get_absolute_expression ();
3667 if (*input_line_pointer++ != ',')
3668 goto err;
3669 outs = get_absolute_expression ();
3670 if (*input_line_pointer++ != ',')
3671 goto err;
3672 rots = get_absolute_expression ();
3673 }
3674 set_regstack (ins, locs, outs, rots);
3675 return;
3676
3677 err:
3678 as_bad ("Comma expected");
3679 ignore_rest_of_line ();
3680}
3681
3682static void
3683dot_rot (type)
3684 int type;
3685{
3686 unsigned num_regs, num_alloced = 0;
3687 struct dynreg **drpp, *dr;
3688 int ch, base_reg = 0;
3689 char *name, *start;
3690 size_t len;
3691
3692 switch (type)
3693 {
3694 case DYNREG_GR: base_reg = REG_GR + 32; break;
3695 case DYNREG_FR: base_reg = REG_FR + 32; break;
3696 case DYNREG_PR: base_reg = REG_P + 16; break;
3697 default: break;
3698 }
3699
542d6675 3700 /* First, remove existing names from hash table. */
800eeca4
JW		 3701 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3702 {
3703 hash_delete (md.dynreg_hash, dr->name);
3704 dr->num_regs = 0;
3705 }
3706
3707 drpp = &md.dynreg[type];
3708 while (1)
3709 {
3710 start = input_line_pointer;
3711 ch = get_symbol_end ();
3712 *input_line_pointer = ch;
3713 len = (input_line_pointer - start);
3714
3715 SKIP_WHITESPACE ();
3716 if (*input_line_pointer != '[')
3717 {
3718 as_bad ("Expected '['");
3719 goto err;
3720 }
3721 ++input_line_pointer; /* skip '[' */
3722
3723 num_regs = get_absolute_expression ();
3724
3725 if (*input_line_pointer++ != ']')
3726 {
3727 as_bad ("Expected ']'");
3728 goto err;
3729 }
3730 SKIP_WHITESPACE ();
3731
3732 num_alloced += num_regs;
3733 switch (type)
3734 {
3735 case DYNREG_GR:
3736 if (num_alloced > md.rot.num_regs)
3737 {
3738 as_bad ("Used more than the declared %d rotating registers",
3739 md.rot.num_regs);
3740 goto err;
3741 }
3742 break;
3743 case DYNREG_FR:
3744 if (num_alloced > 96)
3745 {
3746 as_bad ("Used more than the available 96 rotating registers");
3747 goto err;
3748 }
3749 break;
3750 case DYNREG_PR:
3751 if (num_alloced > 48)
3752 {
3753 as_bad ("Used more than the available 48 rotating registers");
3754 goto err;
3755 }
3756 break;
3757
3758 default:
3759 break;
3760 }
3761
3762 name = obstack_alloc (&notes, len + 1);
3763 memcpy (name, start, len);
3764 name[len] = '\0';
3765
3766 if (!*drpp)
3767 {
3768 *drpp = obstack_alloc (&notes, sizeof (*dr));
3769 memset (*drpp, 0, sizeof (*dr));
3770 }
3771
3772 dr = *drpp;
3773 dr->name = name;
3774 dr->num_regs = num_regs;
3775 dr->base = base_reg;
3776 drpp = &dr->next;
3777 base_reg += num_regs;
3778
3779 if (hash_insert (md.dynreg_hash, name, dr))
3780 {
3781 as_bad ("Attempt to redefine register set `%s'", name);
3782 goto err;
3783 }
3784
3785 if (*input_line_pointer != ',')
3786 break;
3787 ++input_line_pointer; /* skip comma */
3788 SKIP_WHITESPACE ();
3789 }
3790 demand_empty_rest_of_line ();
3791 return;
3792
3793 err:
3794 ignore_rest_of_line ();
3795}
3796
3797static void
3798dot_byteorder (byteorder)
3799 int byteorder;
3800{
3801 target_big_endian = byteorder;
3802}
3803
3804static void
3805dot_psr (dummy)
3806 int dummy;
3807{
3808 char *option;
3809 int ch;
3810
3811 while (1)
3812 {
3813 option = input_line_pointer;
3814 ch = get_symbol_end ();
3815 if (strcmp (option, "lsb") == 0)
3816 md.flags &= ~EF_IA_64_BE;
3817 else if (strcmp (option, "msb") == 0)
3818 md.flags |= EF_IA_64_BE;
3819 else if (strcmp (option, "abi32") == 0)
3820 md.flags &= ~EF_IA_64_ABI64;
3821 else if (strcmp (option, "abi64") == 0)
3822 md.flags |= EF_IA_64_ABI64;
3823 else
3824 as_bad ("Unknown psr option `%s'", option);
3825 *input_line_pointer = ch;
3826
3827 SKIP_WHITESPACE ();
3828 if (*input_line_pointer != ',')
3829 break;
3830
3831 ++input_line_pointer;
3832 SKIP_WHITESPACE ();
3833 }
3834 demand_empty_rest_of_line ();
3835}
3836
3837static void
3838dot_alias (dummy)
3839 int dummy;
3840{
3841 as_bad (".alias not implemented yet");
3842}
3843
3844static void
3845dot_ln (dummy)
3846 int dummy;
3847{
3848 new_logical_line (0, get_absolute_expression ());
3849 demand_empty_rest_of_line ();
3850}
3851
542d6675 3852static char *
800eeca4
JW		 3853parse_section_name ()
3854{
3855 char *name;
3856 int len;
3857
3858 SKIP_WHITESPACE ();
3859 if (*input_line_pointer != '"')
3860 {
3861 as_bad ("Missing section name");
3862 ignore_rest_of_line ();
3863 return 0;
3864 }
3865 name = demand_copy_C_string (&len);
3866 if (!name)
3867 {
3868 ignore_rest_of_line ();
3869 return 0;
3870 }
3871 SKIP_WHITESPACE ();
3872 if (*input_line_pointer != ',')
3873 {
3874 as_bad ("Comma expected after section name");
3875 ignore_rest_of_line ();
3876 return 0;
3877 }
3878 ++input_line_pointer; /* skip comma */
3879 return name;
3880}
3881
3882static void
3883dot_xdata (size)
3884 int size;
3885{
3886 char *name = parse_section_name ();
3887 if (!name)
3888 return;
3889
3890 set_section (name);
3891 cons (size);
3892 obj_elf_previous (0);
3893}
3894
3895/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
542d6675 3896
800eeca4
JW		 3897static void
3898stmt_float_cons (kind)
3899 int kind;
3900{
3901 size_t size;
3902
3903 switch (kind)
3904 {
3905 case 'd': size = 8; break;
3906 case 'x': size = 10; break;
3907
3908 case 'f':
3909 default:
3910 size = 4;
3911 break;
3912 }
3913 ia64_do_align (size);
3914 float_cons (kind);
3915}
3916
3917static void
3918stmt_cons_ua (size)
3919 int size;
3920{
3921 int saved_auto_align = md.auto_align;
3922
3923 md.auto_align = 0;
3924 cons (size);
3925 md.auto_align = saved_auto_align;
3926}
3927
3928static void
3929dot_xfloat_cons (kind)
3930 int kind;
3931{
3932 char *name = parse_section_name ();
3933 if (!name)
3934 return;
3935
3936 set_section (name);
3937 stmt_float_cons (kind);
3938 obj_elf_previous (0);
3939}
3940
3941static void
3942dot_xstringer (zero)
3943 int zero;
3944{
3945 char *name = parse_section_name ();
3946 if (!name)
3947 return;
3948
3949 set_section (name);
3950 stringer (zero);
3951 obj_elf_previous (0);
3952}
3953
3954static void
3955dot_xdata_ua (size)
3956 int size;
3957{
3958 int saved_auto_align = md.auto_align;
3959 char *name = parse_section_name ();
3960 if (!name)
3961 return;
3962
3963 set_section (name);
3964 md.auto_align = 0;
3965 cons (size);
3966 md.auto_align = saved_auto_align;
3967 obj_elf_previous (0);
3968}
3969
3970static void
3971dot_xfloat_cons_ua (kind)
3972 int kind;
3973{
3974 int saved_auto_align = md.auto_align;
3975 char *name = parse_section_name ();
3976 if (!name)
3977 return;
3978
3979 set_section (name);
3980 md.auto_align = 0;
3981 stmt_float_cons (kind);
3982 md.auto_align = saved_auto_align;
3983 obj_elf_previous (0);
3984}
3985
3986/* .reg.val <regname>,value */
542d6675 3987
800eeca4
JW		 3988static void
3989dot_reg_val (dummy)
542d6675 3990 int dummy;
800eeca4
JW		 3991{
3992 expressionS reg;
3993
3994 expression (&reg);
3995 if (reg.X_op != O_register)
3996 {
3997 as_bad (_("Register name expected"));
3998 ignore_rest_of_line ();
3999 }
4000 else if (*input_line_pointer++ != ',')
4001 {
4002 as_bad (_("Comma expected"));
4003 ignore_rest_of_line ();
4004 }
197865e8 4005 else
800eeca4
JW		 4006 {
4007 valueT value = get_absolute_expression ();
4008 int regno = reg.X_add_number;
542d6675
KH		 4009 if (regno < REG_GR || regno > REG_GR + 128)
4010 as_warn (_("Register value annotation ignored"));
800eeca4 4011 else
542d6675
KH		 4012 {
4013 gr_values[regno - REG_GR].known = 1;
4014 gr_values[regno - REG_GR].value = value;
4015 gr_values[regno - REG_GR].path = md.path;
4016 }
800eeca4
JW		 4017 }
4018 demand_empty_rest_of_line ();
4019}
4020
197865e8 4021/* select dv checking mode
800eeca4
JW		 4022 .auto
4023 .explicit
4024 .default
4025
197865e8 4026 A stop is inserted when changing modes
800eeca4 4027 */
542d6675 4028
800eeca4
JW		 4029static void
4030dot_dv_mode (type)
542d6675 4031 int type;
800eeca4
JW		 4032{
4033 if (md.manual_bundling)
4034 as_warn (_("Directive invalid within a bundle"));
4035
4036 if (type == 'E' || type == 'A')
4037 md.mode_explicitly_set = 0;
4038 else
4039 md.mode_explicitly_set = 1;
4040
4041 md.detect_dv = 1;
4042 switch (type)
4043 {
4044 case 'A':
4045 case 'a':
4046 if (md.explicit_mode)
542d6675 4047 insn_group_break (1, 0, 0);
800eeca4
JW		 4048 md.explicit_mode = 0;
4049 break;
4050 case 'E':
4051 case 'e':
4052 if (!md.explicit_mode)
542d6675 4053 insn_group_break (1, 0, 0);
800eeca4
JW		 4054 md.explicit_mode = 1;
4055 break;
4056 default:
4057 case 'd':
4058 if (md.explicit_mode != md.default_explicit_mode)
542d6675 4059 insn_group_break (1, 0, 0);
800eeca4
JW		 4060 md.explicit_mode = md.default_explicit_mode;
4061 md.mode_explicitly_set = 0;
4062 break;
4063 }
4064}
4065
4066static void
4067print_prmask (mask)
542d6675 4068 valueT mask;
800eeca4
JW		 4069{
4070 int regno;
4071 char *comma = "";
542d6675 4072 for (regno = 0; regno < 64; regno++)
800eeca4 4073 {
542d6675
KH		 4074 if (mask & ((valueT) 1 << regno))
4075 {
4076 fprintf (stderr, "%s p%d", comma, regno);
4077 comma = ",";
4078 }
800eeca4
JW		 4079 }
4080}
4081
4082/*
4083 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4084 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4085 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4086 .pred.safe_across_calls p1 [, p2 [,...]]
4087 */
542d6675 4088
800eeca4
JW		 4089static void
4090dot_pred_rel (type)
542d6675 4091 int type;
800eeca4
JW		 4092{
4093 valueT mask = 0;
4094 int count = 0;
4095 int p1 = -1, p2 = -1;
4096
4097 if (type == 0)
4098 {
4099 if (*input_line_pointer != '"')
542d6675
KH		 4100 {
4101 as_bad (_("Missing predicate relation type"));
4102 ignore_rest_of_line ();
4103 return;
4104 }
197865e8 4105 else
542d6675
KH		 4106 {
4107 int len;
4108 char *form = demand_copy_C_string (&len);
4109 if (strcmp (form, "mutex") == 0)
4110 type = 'm';
4111 else if (strcmp (form, "clear") == 0)
4112 type = 'c';
4113 else if (strcmp (form, "imply") == 0)
4114 type = 'i';
4115 else
4116 {
4117 as_bad (_("Unrecognized predicate relation type"));
4118 ignore_rest_of_line ();
4119 return;
4120 }
4121 }
800eeca4 4122 if (*input_line_pointer == ',')
542d6675 4123 ++input_line_pointer;
800eeca4
JW		 4124 SKIP_WHITESPACE ();
4125 }
4126
4127 SKIP_WHITESPACE ();
4128 while (1)
4129 {
4130 valueT bit = 1;
4131 int regno;
197865e8 4132
800eeca4 4133 if (toupper (*input_line_pointer) != 'P'
542d6675
KH		 4134 || (regno = atoi (++input_line_pointer)) < 0
4135 || regno > 63)
4136 {
4137 as_bad (_("Predicate register expected"));
4138 ignore_rest_of_line ();
4139 return;
4140 }
800eeca4 4141 while (isdigit (*input_line_pointer))
542d6675 4142 ++input_line_pointer;
800eeca4 4143 if (p1 == -1)
542d6675 4144 p1 = regno;
800eeca4 4145 else if (p2 == -1)
542d6675 4146 p2 = regno;
800eeca4
JW		 4147 bit <<= regno;
4148 if (mask & bit)
542d6675
KH		 4149 as_warn (_("Duplicate predicate register ignored"));
4150 mask |= bit;
4151 count++;
4152 /* See if it's a range. */
800eeca4 4153 if (*input_line_pointer == '-')
542d6675
KH		 4154 {
4155 valueT stop = 1;
4156 ++input_line_pointer;
4157
4158 if (toupper (*input_line_pointer) != 'P'
4159 || (regno = atoi (++input_line_pointer)) < 0
4160 || regno > 63)
4161 {
4162 as_bad (_("Predicate register expected"));
4163 ignore_rest_of_line ();
4164 return;
4165 }
4166 while (isdigit (*input_line_pointer))
4167 ++input_line_pointer;
4168 stop <<= regno;
4169 if (bit >= stop)
4170 {
4171 as_bad (_("Bad register range"));
4172 ignore_rest_of_line ();
4173 return;
4174 }
4175 while (bit < stop)
4176 {
4177 bit <<= 1;
4178 mask |= bit;
4179 count++;
4180 }
4181 SKIP_WHITESPACE ();
4182 }
800eeca4 4183 if (*input_line_pointer != ',')
542d6675 4184 break;
800eeca4
JW		 4185 ++input_line_pointer;
4186 SKIP_WHITESPACE ();
4187 }
4188
4189 switch (type)
4190 {
4191 case 'c':
4192 if (count == 0)
542d6675 4193 mask = ~(valueT) 0;
800eeca4 4194 clear_qp_mutex (mask);
197865e8 4195 clear_qp_implies (mask, (valueT) 0);
800eeca4
JW		 4196 break;
4197 case 'i':
4198 if (count != 2 || p1 == -1 || p2 == -1)
542d6675 4199 as_bad (_("Predicate source and target required"));
800eeca4 4200 else if (p1 == 0 || p2 == 0)
542d6675 4201 as_bad (_("Use of p0 is not valid in this context"));
800eeca4 4202 else
542d6675 4203 add_qp_imply (p1, p2);
800eeca4
JW		 4204 break;
4205 case 'm':
4206 if (count < 2)
542d6675
KH		 4207 {
4208 as_bad (_("At least two PR arguments expected"));
4209 break;
4210 }
800eeca4 4211 else if (mask & 1)
542d6675
KH		 4212 {
4213 as_bad (_("Use of p0 is not valid in this context"));
4214 break;
4215 }
800eeca4
JW		 4216 add_qp_mutex (mask);
4217 break;
4218 case 's':
4219 /* note that we don't override any existing relations */
4220 if (count == 0)
542d6675
KH		 4221 {
4222 as_bad (_("At least one PR argument expected"));
4223 break;
4224 }
800eeca4 4225 if (md.debug_dv)
542d6675
KH		 4226 {
4227 fprintf (stderr, "Safe across calls: ");
4228 print_prmask (mask);
4229 fprintf (stderr, "\n");
4230 }
800eeca4
JW		 4231 qp_safe_across_calls = mask;
4232 break;
4233 }
4234 demand_empty_rest_of_line ();
4235}
4236
4237/* .entry label [, label [, ...]]
4238 Hint to DV code that the given labels are to be considered entry points.
542d6675
KH		 4239 Otherwise, only global labels are considered entry points. */
4240
800eeca4
JW		 4241static void
4242dot_entry (dummy)
542d6675 4243 int dummy;
800eeca4
JW		 4244{
4245 const char *err;
4246 char *name;
4247 int c;
4248 symbolS *symbolP;
4249
4250 do
4251 {
4252 name = input_line_pointer;
4253 c = get_symbol_end ();
4254 symbolP = symbol_find_or_make (name);
4255
4256 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4257 if (err)
542d6675
KH		 4258 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4259 name, err);
800eeca4
JW		 4260
4261 *input_line_pointer = c;
4262 SKIP_WHITESPACE ();
4263 c = *input_line_pointer;
4264 if (c == ',')
4265 {
4266 input_line_pointer++;
4267 SKIP_WHITESPACE ();
4268 if (*input_line_pointer == '\n')
4269 c = '\n';
4270 }
4271 }
4272 while (c == ',');
4273
4274 demand_empty_rest_of_line ();
4275}
4276
197865e8 4277/* .mem.offset offset, base
542d6675
KH		 4278 "base" is used to distinguish between offsets from a different base. */
4279
800eeca4
JW		 4280static void
4281dot_mem_offset (dummy)
4282 int dummy;
4283{
4284 md.mem_offset.hint = 1;
4285 md.mem_offset.offset = get_absolute_expression ();
4286 if (*input_line_pointer != ',')
4287 {
4288 as_bad (_("Comma expected"));
4289 ignore_rest_of_line ();
4290 return;
4291 }
4292 ++input_line_pointer;
4293 md.mem_offset.base = get_absolute_expression ();
4294 demand_empty_rest_of_line ();
4295}
4296
542d6675 4297/* ia64-specific pseudo-ops: */
800eeca4
JW		 4298const pseudo_typeS md_pseudo_table[] =
4299 {
4300 { "radix", dot_radix, 0 },
4301 { "lcomm", s_lcomm_bytes, 1 },
4302 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4303 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4304 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4305 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4306 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4307 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4308 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4309 { "proc", dot_proc, 0 },
4310 { "body", dot_body, 0 },
4311 { "prologue", dot_prologue, 0 },
4312 { "endp", dot_endp },
4313 { "file", dwarf2_directive_file },
4314 { "loc", dwarf2_directive_loc },
4315
4316 { "fframe", dot_fframe },
4317 { "vframe", dot_vframe },
e0c9811a
JW		 4318 { "vframesp", dot_vframesp },
4319 { "vframepsp", dot_vframepsp },
800eeca4
JW		 4320 { "save", dot_save },
4321 { "restore", dot_restore },
e0c9811a
JW		 4322 { "restorereg", dot_restorereg },
4323 { "restorereg.p", dot_restorereg_p },
800eeca4
JW		 4324 { "handlerdata", dot_handlerdata },
4325 { "unwentry", dot_unwentry },
e0c9811a
JW		 4326 { "altrp", dot_altrp },
4327 { "savesp", dot_savemem, 0 },
4328 { "savepsp", dot_savemem, 1 },
800eeca4
JW		 4329 { "save.g", dot_saveg },
4330 { "save.f", dot_savef },
4331 { "save.b", dot_saveb },
4332 { "save.gf", dot_savegf },
4333 { "spill", dot_spill },
e0c9811a
JW		 4334 { "spillreg", dot_spillreg },
4335 { "spillsp", dot_spillmem, 0 },
4336 { "spillpsp", dot_spillmem, 1 },
4337 { "spillreg.p", dot_spillreg_p },
4338 { "spillsp.p", dot_spillmem_p, 0 },
4339 { "spillpsp.p", dot_spillmem_p, 1 },
197865e8
KH		 4340 { "label_state", dot_label_state },
4341 { "copy_state", dot_copy_state },
800eeca4
JW		 4342 { "unwabi", dot_unwabi },
4343 { "personality", dot_personality },
4344#if 0
4345 { "estate", dot_estate },
4346#endif
4347 { "mii", dot_template, 0x0 },
4348 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4349 { "mlx", dot_template, 0x2 },
4350 { "mmi", dot_template, 0x4 },
4351 { "mfi", dot_template, 0x6 },
4352 { "mmf", dot_template, 0x7 },
4353 { "mib", dot_template, 0x8 },
4354 { "mbb", dot_template, 0x9 },
4355 { "bbb", dot_template, 0xb },
4356 { "mmb", dot_template, 0xc },
4357 { "mfb", dot_template, 0xe },
4358#if 0
4359 { "lb", dot_scope, 0 },
4360 { "le", dot_scope, 1 },
4361#endif
4362 { "align", s_align_bytes, 0 },
4363 { "regstk", dot_regstk, 0 },
4364 { "rotr", dot_rot, DYNREG_GR },
4365 { "rotf", dot_rot, DYNREG_FR },
4366 { "rotp", dot_rot, DYNREG_PR },
4367 { "lsb", dot_byteorder, 0 },
4368 { "msb", dot_byteorder, 1 },
4369 { "psr", dot_psr, 0 },
4370 { "alias", dot_alias, 0 },
4371 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4372
4373 { "xdata1", dot_xdata, 1 },
4374 { "xdata2", dot_xdata, 2 },
4375 { "xdata4", dot_xdata, 4 },
4376 { "xdata8", dot_xdata, 8 },
4377 { "xreal4", dot_xfloat_cons, 'f' },
4378 { "xreal8", dot_xfloat_cons, 'd' },
4379 { "xreal10", dot_xfloat_cons, 'x' },
4380 { "xstring", dot_xstringer, 0 },
4381 { "xstringz", dot_xstringer, 1 },
4382
542d6675 4383 /* unaligned versions: */
800eeca4
JW		 4384 { "xdata2.ua", dot_xdata_ua, 2 },
4385 { "xdata4.ua", dot_xdata_ua, 4 },
4386 { "xdata8.ua", dot_xdata_ua, 8 },
4387 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4388 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4389 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4390
4391 /* annotations/DV checking support */
4392 { "entry", dot_entry, 0 },
4393 { "mem.offset", dot_mem_offset },
4394 { "pred.rel", dot_pred_rel, 0 },
4395 { "pred.rel.clear", dot_pred_rel, 'c' },
4396 { "pred.rel.imply", dot_pred_rel, 'i' },
4397 { "pred.rel.mutex", dot_pred_rel, 'm' },
4398 { "pred.safe_across_calls", dot_pred_rel, 's' },
4399 { "reg.val", dot_reg_val },
4400 { "auto", dot_dv_mode, 'a' },
4401 { "explicit", dot_dv_mode, 'e' },
4402 { "default", dot_dv_mode, 'd' },
4403
4404 { NULL, 0, 0 }
4405 };
4406
4407static const struct pseudo_opcode
4408 {
4409 const char *name;
4410 void (*handler) (int);
4411 int arg;
4412 }
4413pseudo_opcode[] =
4414 {
4415 /* these are more like pseudo-ops, but don't start with a dot */
4416 { "data1", cons, 1 },
4417 { "data2", cons, 2 },
4418 { "data4", cons, 4 },
4419 { "data8", cons, 8 },
4420 { "real4", stmt_float_cons, 'f' },
4421 { "real8", stmt_float_cons, 'd' },
4422 { "real10", stmt_float_cons, 'x' },
4423 { "string", stringer, 0 },
4424 { "stringz", stringer, 1 },
4425
542d6675 4426 /* unaligned versions: */
800eeca4
JW		 4427 { "data2.ua", stmt_cons_ua, 2 },
4428 { "data4.ua", stmt_cons_ua, 4 },
4429 { "data8.ua", stmt_cons_ua, 8 },
4430 { "real4.ua", float_cons, 'f' },
4431 { "real8.ua", float_cons, 'd' },
4432 { "real10.ua", float_cons, 'x' },
4433 };
4434
4435/* Declare a register by creating a symbol for it and entering it in
4436 the symbol table. */
542d6675
KH		 4437
4438static symbolS *
800eeca4
JW		 4439declare_register (name, regnum)
4440 const char *name;
4441 int regnum;
4442{
4443 const char *err;
4444 symbolS *sym;
4445
4446 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4447
4448 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4449 if (err)
4450 as_fatal ("Inserting \"%s\" into register table failed: %s",
4451 name, err);
4452
4453 return sym;
4454}
4455
4456static void
4457declare_register_set (prefix, num_regs, base_regnum)
4458 const char *prefix;
4459 int num_regs;
4460 int base_regnum;
4461{
4462 char name[8];
4463 int i;
4464
4465 for (i = 0; i < num_regs; ++i)
4466 {
4467 sprintf (name, "%s%u", prefix, i);
4468 declare_register (name, base_regnum + i);
4469 }
4470}
4471
4472static unsigned int
4473operand_width (opnd)
4474 enum ia64_opnd opnd;
4475{
4476 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4477 unsigned int bits = 0;
4478 int i;
4479
4480 bits = 0;
4481 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4482 bits += odesc->field[i].bits;
4483
4484 return bits;
4485}
4486
4487static int
4488operand_match (idesc, index, e)
4489 const struct ia64_opcode *idesc;
4490 int index;
4491 expressionS *e;
4492{
4493 enum ia64_opnd opnd = idesc->operands[index];
4494 int bits, relocatable = 0;
4495 struct insn_fix *fix;
4496 bfd_signed_vma val;
4497
4498 switch (opnd)
4499 {
542d6675 4500 /* constants: */
800eeca4
JW		 4501
4502 case IA64_OPND_AR_CCV:
4503 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4504 return 1;
4505 break;
4506
4507 case IA64_OPND_AR_PFS:
4508 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4509 return 1;
4510 break;
4511
4512 case IA64_OPND_GR0:
4513 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4514 return 1;
4515 break;
4516
4517 case IA64_OPND_IP:
4518 if (e->X_op == O_register && e->X_add_number == REG_IP)
4519 return 1;
4520 break;
4521
4522 case IA64_OPND_PR:
4523 if (e->X_op == O_register && e->X_add_number == REG_PR)
4524 return 1;
4525 break;
4526
4527 case IA64_OPND_PR_ROT:
4528 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4529 return 1;
4530 break;
4531
4532 case IA64_OPND_PSR:
4533 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4534 return 1;
4535 break;
4536
4537 case IA64_OPND_PSR_L:
4538 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4539 return 1;
4540 break;
4541
4542 case IA64_OPND_PSR_UM:
4543 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4544 return 1;
4545 break;
4546
4547 case IA64_OPND_C1:
4548 if (e->X_op == O_constant && e->X_add_number == 1)
4549 return 1;
4550 break;
4551
4552 case IA64_OPND_C8:
4553 if (e->X_op == O_constant && e->X_add_number == 8)
4554 return 1;
4555 break;
4556
4557 case IA64_OPND_C16:
4558 if (e->X_op == O_constant && e->X_add_number == 16)
4559 return 1;
4560 break;
4561
542d6675 4562 /* register operands: */
800eeca4
JW		 4563
4564 case IA64_OPND_AR3:
4565 if (e->X_op == O_register && e->X_add_number >= REG_AR
4566 && e->X_add_number < REG_AR + 128)
4567 return 1;
4568 break;
4569
4570 case IA64_OPND_B1:
4571 case IA64_OPND_B2:
4572 if (e->X_op == O_register && e->X_add_number >= REG_BR
4573 && e->X_add_number < REG_BR + 8)
4574 return 1;
4575 break;
4576
4577 case IA64_OPND_CR3:
4578 if (e->X_op == O_register && e->X_add_number >= REG_CR
4579 && e->X_add_number < REG_CR + 128)
4580 return 1;
4581 break;
4582
4583 case IA64_OPND_F1:
4584 case IA64_OPND_F2:
4585 case IA64_OPND_F3:
4586 case IA64_OPND_F4:
4587 if (e->X_op == O_register && e->X_add_number >= REG_FR
4588 && e->X_add_number < REG_FR + 128)
4589 return 1;
4590 break;
4591
4592 case IA64_OPND_P1:
4593 case IA64_OPND_P2:
4594 if (e->X_op == O_register && e->X_add_number >= REG_P
4595 && e->X_add_number < REG_P + 64)
4596 return 1;
4597 break;
4598
4599 case IA64_OPND_R1:
4600 case IA64_OPND_R2:
4601 case IA64_OPND_R3:
4602 if (e->X_op == O_register && e->X_add_number >= REG_GR
4603 && e->X_add_number < REG_GR + 128)
4604 return 1;
4605 break;
4606
4607 case IA64_OPND_R3_2:
4608 if (e->X_op == O_register && e->X_add_number >= REG_GR
4609 && e->X_add_number < REG_GR + 4)
4610 return 1;
4611 break;
4612
542d6675 4613 /* indirect operands: */
800eeca4
JW		 4614 case IA64_OPND_CPUID_R3:
4615 case IA64_OPND_DBR_R3:
4616 case IA64_OPND_DTR_R3:
4617 case IA64_OPND_ITR_R3:
4618 case IA64_OPND_IBR_R3:
4619 case IA64_OPND_MSR_R3:
4620 case IA64_OPND_PKR_R3:
4621 case IA64_OPND_PMC_R3:
4622 case IA64_OPND_PMD_R3:
4623 case IA64_OPND_RR_R3:
4624 if (e->X_op == O_index && e->X_op_symbol
4625 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4626 == opnd - IA64_OPND_CPUID_R3))
4627 return 1;
4628 break;
4629
4630 case IA64_OPND_MR3:
4631 if (e->X_op == O_index && !e->X_op_symbol)
4632 return 1;
4633 break;
4634
542d6675 4635 /* immediate operands: */
800eeca4
JW		 4636 case IA64_OPND_CNT2a:
4637 case IA64_OPND_LEN4:
4638 case IA64_OPND_LEN6:
4639 bits = operand_width (idesc->operands[index]);
4640 if (e->X_op == O_constant
4641 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4642 return 1;
4643 break;
4644
4645 case IA64_OPND_CNT2b:
4646 if (e->X_op == O_constant
4647 && (bfd_vma) (e->X_add_number - 1) < 3)
4648 return 1;
4649 break;
4650
4651 case IA64_OPND_CNT2c:
4652 val = e->X_add_number;
4653 if (e->X_op == O_constant
4654 && (val == 0 || val == 7 || val == 15 || val == 16))
4655 return 1;
4656 break;
4657
4658 case IA64_OPND_SOR:
4659 /* SOR must be an integer multiple of 8 */
4660 if (e->X_add_number & 0x7)
4661 break;
4662 case IA64_OPND_SOF:
4663 case IA64_OPND_SOL:
4664 if (e->X_op == O_constant &&
4665 (bfd_vma) e->X_add_number <= 96)
4666 return 1;
4667 break;
4668
4669 case IA64_OPND_IMMU62:
4670 if (e->X_op == O_constant)
542d6675 4671 {
800eeca4 4672 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
542d6675
KH		 4673 return 1;
4674 }
197865e8 4675 else
542d6675
KH		 4676 {
4677 /* FIXME -- need 62-bit relocation type */
4678 as_bad (_("62-bit relocation not yet implemented"));
4679 }
800eeca4
JW		 4680 break;
4681
4682 case IA64_OPND_IMMU64:
4683 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4684 || e->X_op == O_subtract)
4685 {
4686 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4687 fix->code = BFD_RELOC_IA64_IMM64;
4688 if (e->X_op != O_subtract)
4689 {
4690 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4691 if (e->X_op == O_pseudo_fixup)
4692 e->X_op = O_symbol;
4693 }
4694
4695 fix->opnd = idesc->operands[index];
4696 fix->expr = *e;
4697 fix->is_pcrel = 0;
4698 ++CURR_SLOT.num_fixups;
4699 return 1;
4700 }
4701 else if (e->X_op == O_constant)
4702 return 1;
4703 break;
4704
4705 case IA64_OPND_CCNT5:
4706 case IA64_OPND_CNT5:
4707 case IA64_OPND_CNT6:
4708 case IA64_OPND_CPOS6a:
4709 case IA64_OPND_CPOS6b:
4710 case IA64_OPND_CPOS6c:
4711 case IA64_OPND_IMMU2:
4712 case IA64_OPND_IMMU7a:
4713 case IA64_OPND_IMMU7b:
800eeca4
JW		 4714 case IA64_OPND_IMMU21:
4715 case IA64_OPND_IMMU24:
4716 case IA64_OPND_MBTYPE4:
4717 case IA64_OPND_MHTYPE8:
4718 case IA64_OPND_POS6:
4719 bits = operand_width (idesc->operands[index]);
4720 if (e->X_op == O_constant
4721 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4722 return 1;
4723 break;
4724
bf3ca999
TW		 4725 case IA64_OPND_IMMU9:
4726 bits = operand_width (idesc->operands[index]);
4727 if (e->X_op == O_constant
4728 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
542d6675
KH		 4729 {
4730 int lobits = e->X_add_number & 0x3;
4731 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
4732 e->X_add_number |= (bfd_vma) 0x3;
4733 return 1;
4734 }
bf3ca999
TW		 4735 break;
4736
800eeca4
JW		 4737 case IA64_OPND_IMM44:
4738 /* least 16 bits must be zero */
4739 if ((e->X_add_number & 0xffff) != 0)
542d6675 4740 as_warn (_("lower 16 bits of mask ignored"));
800eeca4
JW		 4741
4742 if (e->X_op == O_constant
4743 && ((e->X_add_number >= 0
4744 && e->X_add_number < ((bfd_vma) 1 << 44))
4745 || (e->X_add_number < 0
4746 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
542d6675
KH		 4747 {
4748 /* sign-extend */
4749 if (e->X_add_number >= 0
4750 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4751 {
4752 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4753 }
4754 return 1;
4755 }
800eeca4
JW		 4756 break;
4757
4758 case IA64_OPND_IMM17:
4759 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4760 if (e->X_op == O_constant
4761 && ((e->X_add_number >= 0
4762 && e->X_add_number < ((bfd_vma) 1 << 17))
4763 || (e->X_add_number < 0
4764 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
542d6675
KH		 4765 {
4766 /* sign-extend */
4767 if (e->X_add_number >= 0
4768 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4769 {
4770 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
4771 }
4772 return 1;
4773 }
800eeca4
JW		 4774 break;
4775
4776 case IA64_OPND_IMM14:
4777 case IA64_OPND_IMM22:
4778 relocatable = 1;
4779 case IA64_OPND_IMM1:
4780 case IA64_OPND_IMM8:
4781 case IA64_OPND_IMM8U4:
4782 case IA64_OPND_IMM8M1:
4783 case IA64_OPND_IMM8M1U4:
4784 case IA64_OPND_IMM8M1U8:
4785 case IA64_OPND_IMM9a:
4786 case IA64_OPND_IMM9b:
4787 bits = operand_width (idesc->operands[index]);
4788 if (relocatable && (e->X_op == O_symbol
4789 || e->X_op == O_subtract
4790 || e->X_op == O_pseudo_fixup))
4791 {
4792 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4793
4794 if (idesc->operands[index] == IA64_OPND_IMM14)
4795 fix->code = BFD_RELOC_IA64_IMM14;
4796 else
4797 fix->code = BFD_RELOC_IA64_IMM22;
4798
4799 if (e->X_op != O_subtract)
4800 {
4801 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4802 if (e->X_op == O_pseudo_fixup)
4803 e->X_op = O_symbol;
4804 }
4805
4806 fix->opnd = idesc->operands[index];
4807 fix->expr = *e;
4808 fix->is_pcrel = 0;
4809 ++CURR_SLOT.num_fixups;
4810 return 1;
4811 }
4812 else if (e->X_op != O_constant
4813 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4814 return 0;
4815
4816 if (opnd == IA64_OPND_IMM8M1U4)
4817 {
4818 /* Zero is not valid for unsigned compares that take an adjusted
4819 constant immediate range. */
4820 if (e->X_add_number == 0)
4821 return 0;
4822
4823 /* Sign-extend 32-bit unsigned numbers, so that the following range
4824 checks will work. */
4825 val = e->X_add_number;
197865e8
KH		 4826 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4827 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 4828 val = ((val << 32) >> 32);
4829
4830 /* Check for 0x100000000. This is valid because
4831 0x100000000-1 is the same as ((uint32_t) -1). */
4832 if (val == ((bfd_signed_vma) 1 << 32))
4833 return 1;
4834
4835 val = val - 1;
4836 }
4837 else if (opnd == IA64_OPND_IMM8M1U8)
4838 {
4839 /* Zero is not valid for unsigned compares that take an adjusted
4840 constant immediate range. */
4841 if (e->X_add_number == 0)
4842 return 0;
4843
4844 /* Check for 0x10000000000000000. */
4845 if (e->X_op == O_big)
4846 {
4847 if (generic_bignum[0] == 0
4848 && generic_bignum[1] == 0
4849 && generic_bignum[2] == 0
4850 && generic_bignum[3] == 0
4851 && generic_bignum[4] == 1)
4852 return 1;
4853 else
4854 return 0;
4855 }
4856 else
4857 val = e->X_add_number - 1;
4858 }
4859 else if (opnd == IA64_OPND_IMM8M1)
4860 val = e->X_add_number - 1;
4861 else if (opnd == IA64_OPND_IMM8U4)
4862 {
4863 /* Sign-extend 32-bit unsigned numbers, so that the following range
4864 checks will work. */
4865 val = e->X_add_number;
197865e8
KH		 4866 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4867 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 4868 val = ((val << 32) >> 32);
4869 }
4870 else
4871 val = e->X_add_number;
4872
4873 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
4874 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
4875 return 1;
4876 break;
4877
4878 case IA64_OPND_INC3:
4879 /* +/- 1, 4, 8, 16 */
4880 val = e->X_add_number;
4881 if (val < 0)
4882 val = -val;
4883 if (e->X_op == O_constant
4884 && (val == 1 || val == 4 || val == 8 || val == 16))
4885 return 1;
4886 break;
4887
4888 case IA64_OPND_TGT25:
4889 case IA64_OPND_TGT25b:
4890 case IA64_OPND_TGT25c:
4891 case IA64_OPND_TGT64:
4892 if (e->X_op == O_symbol)
4893 {
4894 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4895 if (opnd == IA64_OPND_TGT25)
4896 fix->code = BFD_RELOC_IA64_PCREL21F;
4897 else if (opnd == IA64_OPND_TGT25b)
4898 fix->code = BFD_RELOC_IA64_PCREL21M;
4899 else if (opnd == IA64_OPND_TGT25c)
4900 fix->code = BFD_RELOC_IA64_PCREL21B;
542d6675 4901 else if (opnd == IA64_OPND_TGT64)
c67e42c9
RH		 4902 fix->code = BFD_RELOC_IA64_PCREL60B;
4903 else
4904 abort ();
4905
800eeca4
JW		 4906 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4907 fix->opnd = idesc->operands[index];
4908 fix->expr = *e;
4909 fix->is_pcrel = 1;
4910 ++CURR_SLOT.num_fixups;
4911 return 1;
4912 }
4913 case IA64_OPND_TAG13:
4914 case IA64_OPND_TAG13b:
4915 switch (e->X_op)
4916 {
4917 case O_constant:
4918 return 1;
4919
4920 case O_symbol:
4921 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4922 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4923 fix->opnd = idesc->operands[index];
4924 fix->expr = *e;
4925 fix->is_pcrel = 1;
4926 ++CURR_SLOT.num_fixups;
4927 return 1;
4928
4929 default:
4930 break;
4931 }
4932 break;
4933
4934 default:
4935 break;
4936 }
4937 return 0;
4938}
4939
4940static int
4941parse_operand (e)
4942 expressionS *e;
4943{
4944 int sep = '\0';
4945
4946 memset (e, 0, sizeof (*e));
4947 e->X_op = O_absent;
4948 SKIP_WHITESPACE ();
4949 if (*input_line_pointer != '}')
4950 expression (e);
4951 sep = *input_line_pointer++;
4952
4953 if (sep == '}')
4954 {
4955 if (!md.manual_bundling)
4956 as_warn ("Found '}' when manual bundling is off");
4957 else
4958 CURR_SLOT.manual_bundling_off = 1;
4959 md.manual_bundling = 0;
4960 sep = '\0';
4961 }
4962 return sep;
4963}
4964
4965/* Returns the next entry in the opcode table that matches the one in
4966 IDESC, and frees the entry in IDESC. If no matching entry is
197865e8 4967 found, NULL is returned instead. */
800eeca4
JW		 4968
4969static struct ia64_opcode *
4970get_next_opcode (struct ia64_opcode *idesc)
4971{
4972 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
4973 ia64_free_opcode (idesc);
4974 return next;
4975}
4976
4977/* Parse the operands for the opcode and find the opcode variant that
4978 matches the specified operands, or NULL if no match is possible. */
542d6675
KH		 4979
4980static struct ia64_opcode *
800eeca4
JW		 4981parse_operands (idesc)
4982 struct ia64_opcode *idesc;
4983{
4984 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
4985 int sep = 0;
4986 enum ia64_opnd expected_operand = IA64_OPND_NIL;
4987 char mnemonic[129];
4988 char *first_arg = 0, *end, *saved_input_pointer;
4989 unsigned int sof;
4990
4991 assert (strlen (idesc->name) <= 128);
4992
4993 strcpy (mnemonic, idesc->name);
4994 if (idesc->operands[2] == IA64_OPND_SOF)
4995 {
4996 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4997 can't parse the first operand until we have parsed the
4998 remaining operands of the "alloc" instruction. */
4999 SKIP_WHITESPACE ();
5000 first_arg = input_line_pointer;
5001 end = strchr (input_line_pointer, '=');
5002 if (!end)
5003 {
5004 as_bad ("Expected separator `='");
5005 return 0;
5006 }
5007 input_line_pointer = end + 1;
5008 ++i;
5009 ++num_outputs;
5010 }
5011
5012 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5013 {
5014 sep = parse_operand (CURR_SLOT.opnd + i);
5015 if (CURR_SLOT.opnd[i].X_op == O_absent)
5016 break;
5017
5018 ++num_operands;
5019
5020 if (sep != '=' && sep != ',')
5021 break;
5022
5023 if (sep == '=')
5024 {
5025 if (num_outputs > 0)
5026 as_bad ("Duplicate equal sign (=) in instruction");
5027 else
5028 num_outputs = i + 1;
5029 }
5030 }
5031 if (sep != '\0')
5032 {
5033 as_bad ("Illegal operand separator `%c'", sep);
5034 return 0;
5035 }
197865e8 5036
800eeca4
JW		 5037 if (idesc->operands[2] == IA64_OPND_SOF)
5038 {
5039 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5040 know (strcmp (idesc->name, "alloc") == 0);
5041 if (num_operands == 5 /* first_arg not included in this count! */
5042 && CURR_SLOT.opnd[2].X_op == O_constant
5043 && CURR_SLOT.opnd[3].X_op == O_constant
5044 && CURR_SLOT.opnd[4].X_op == O_constant
5045 && CURR_SLOT.opnd[5].X_op == O_constant)
5046 {
5047 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5048 CURR_SLOT.opnd[3].X_add_number,
5049 CURR_SLOT.opnd[4].X_add_number,
5050 CURR_SLOT.opnd[5].X_add_number);
5051
542d6675 5052 /* now we can parse the first arg: */
800eeca4
JW		 5053 saved_input_pointer = input_line_pointer;
5054 input_line_pointer = first_arg;
5055 sep = parse_operand (CURR_SLOT.opnd + 0);
5056 if (sep != '=')
5057 --num_outputs; /* force error */
5058 input_line_pointer = saved_input_pointer;
5059
5060 CURR_SLOT.opnd[2].X_add_number = sof;
5061 CURR_SLOT.opnd[3].X_add_number
5062 = sof - CURR_SLOT.opnd[4].X_add_number;
5063 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5064 }
5065 }
5066
5067 highest_unmatched_operand = 0;
5068 expected_operand = idesc->operands[0];
5069 for (; idesc; idesc = get_next_opcode (idesc))
5070 {
5071 if (num_outputs != idesc->num_outputs)
5072 continue; /* mismatch in # of outputs */
5073
5074 CURR_SLOT.num_fixups = 0;
5075 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5076 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
5077 break;
5078
5079 if (i != num_operands)
5080 {
5081 if (i > highest_unmatched_operand)
5082 {
5083 highest_unmatched_operand = i;
5084 expected_operand = idesc->operands[i];
5085 }
5086 continue;
5087 }
5088
5089 if (num_operands < NELEMS (idesc->operands)
5090 && idesc->operands[num_operands])
5091 continue; /* mismatch in number of arguments */
5092
5093 break;
5094 }
5095 if (!idesc)
5096 {
5097 if (expected_operand)
5098 as_bad ("Operand %u of `%s' should be %s",
5099 highest_unmatched_operand + 1, mnemonic,
5100 elf64_ia64_operands[expected_operand].desc);
5101 else
5102 as_bad ("Operand mismatch");
5103 return 0;
5104 }
5105 return idesc;
5106}
5107
5108static void
5109build_insn (slot, insnp)
5110 struct slot *slot;
5111 bfd_vma *insnp;
5112{
5113 const struct ia64_operand *odesc, *o2desc;
5114 struct ia64_opcode *idesc = slot->idesc;
5115 bfd_signed_vma insn, val;
5116 const char *err;
5117 int i;
5118
5119 insn = idesc->opcode | slot->qp_regno;
5120
5121 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5122 {
c67e42c9
RH		 5123 if (slot->opnd[i].X_op == O_register
5124 || slot->opnd[i].X_op == O_constant
5125 || slot->opnd[i].X_op == O_index)
5126 val = slot->opnd[i].X_add_number;
5127 else if (slot->opnd[i].X_op == O_big)
800eeca4 5128 {
c67e42c9
RH		 5129 /* This must be the value 0x10000000000000000. */
5130 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5131 val = 0;
5132 }
5133 else
5134 val = 0;
5135
5136 switch (idesc->operands[i])
5137 {
5138 case IA64_OPND_IMMU64:
800eeca4
JW		 5139 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5140 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5141 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5142 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH		 5143 continue;
5144
5145 case IA64_OPND_IMMU62:
542d6675
KH		 5146 val &= 0x3fffffffffffffffULL;
5147 if (val != slot->opnd[i].X_add_number)
5148 as_warn (_("Value truncated to 62 bits"));
5149 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5150 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 5151 continue;
800eeca4 5152
c67e42c9
RH		 5153 case IA64_OPND_TGT64:
5154 val >>= 4;
5155 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5156 insn |= ((((val >> 59) & 0x1) << 36)
5157 | (((val >> 0) & 0xfffff) << 13));
5158 continue;
800eeca4 5159
c67e42c9
RH		 5160 case IA64_OPND_AR3:
5161 val -= REG_AR;
5162 break;
5163
5164 case IA64_OPND_B1:
5165 case IA64_OPND_B2:
5166 val -= REG_BR;
5167 break;
5168
5169 case IA64_OPND_CR3:
5170 val -= REG_CR;
5171 break;
5172
5173 case IA64_OPND_F1:
5174 case IA64_OPND_F2:
5175 case IA64_OPND_F3:
5176 case IA64_OPND_F4:
5177 val -= REG_FR;
5178 break;
5179
5180 case IA64_OPND_P1:
5181 case IA64_OPND_P2:
5182 val -= REG_P;
5183 break;
5184
5185 case IA64_OPND_R1:
5186 case IA64_OPND_R2:
5187 case IA64_OPND_R3:
5188 case IA64_OPND_R3_2:
5189 case IA64_OPND_CPUID_R3:
5190 case IA64_OPND_DBR_R3:
5191 case IA64_OPND_DTR_R3:
5192 case IA64_OPND_ITR_R3:
5193 case IA64_OPND_IBR_R3:
5194 case IA64_OPND_MR3:
5195 case IA64_OPND_MSR_R3:
5196 case IA64_OPND_PKR_R3:
5197 case IA64_OPND_PMC_R3:
5198 case IA64_OPND_PMD_R3:
197865e8 5199 case IA64_OPND_RR_R3:
c67e42c9
RH		 5200 val -= REG_GR;
5201 break;
5202
5203 default:
5204 break;
5205 }
5206
5207 odesc = elf64_ia64_operands + idesc->operands[i];
5208 err = (*odesc->insert) (odesc, val, &insn);
5209 if (err)
5210 as_bad_where (slot->src_file, slot->src_line,
5211 "Bad operand value: %s", err);
5212 if (idesc->flags & IA64_OPCODE_PSEUDO)
5213 {
5214 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5215 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5216 {
5217 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5218 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5219 }
c67e42c9
RH		 5220 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5221 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5222 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5223 {
c67e42c9
RH		 5224 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5225 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW		 5226 }
5227 }
5228 }
5229 *insnp = insn;
5230}
5231
5232static void
5233emit_one_bundle ()
5234{
5235 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5236 unsigned int manual_bundling = 0;
5237 enum ia64_unit required_unit, insn_unit = 0;
5238 enum ia64_insn_type type[3], insn_type;
5239 unsigned int template, orig_template;
542d6675 5240 bfd_vma insn[3] = { -1, -1, -1 };
800eeca4
JW		 5241 struct ia64_opcode *idesc;
5242 int end_of_insn_group = 0, user_template = -1;
5243 int n, i, j, first, curr;
e0c9811a 5244 unw_rec_list *ptr, *prev;
800eeca4
JW		 5245 bfd_vma t0 = 0, t1 = 0;
5246 struct label_fix *lfix;
5247 struct insn_fix *ifix;
5248 char mnemonic[16];
5249 fixS *fix;
5250 char *f;
5251
5252 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5253 know (first >= 0 & first < NUM_SLOTS);
5254 n = MIN (3, md.num_slots_in_use);
5255
5256 /* Determine template: user user_template if specified, best match
542d6675 5257 otherwise: */
800eeca4
JW		 5258
5259 if (md.slot[first].user_template >= 0)
5260 user_template = template = md.slot[first].user_template;
5261 else
5262 {
032efc85 5263 /* Auto select appropriate template. */
800eeca4
JW		 5264 memset (type, 0, sizeof (type));
5265 curr = first;
5266 for (i = 0; i < n; ++i)
5267 {
032efc85
RH		 5268 if (md.slot[curr].label_fixups && i != 0)
5269 break;
800eeca4
JW		 5270 type[i] = md.slot[curr].idesc->type;
5271 curr = (curr + 1) % NUM_SLOTS;
5272 }
5273 template = best_template[type[0]][type[1]][type[2]];
5274 }
5275
542d6675 5276 /* initialize instructions with appropriate nops: */
800eeca4
JW		 5277 for (i = 0; i < 3; ++i)
5278 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5279
5280 f = frag_more (16);
5281
542d6675 5282 /* now fill in slots with as many insns as possible: */
800eeca4
JW		 5283 curr = first;
5284 idesc = md.slot[curr].idesc;
5285 end_of_insn_group = 0;
5286 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5287 {
e0c9811a
JW		 5288 /* Set the slot number for prologue/body records now as those
5289 refer to the current point, not the point after the
542d6675 5290 instruction has been issued: */
10850f29
JW		 5291 /* Don't try to delete prologue/body records here, as that will cause
5292 them to also be deleted from the master list of unwind records. */
e0c9811a 5293 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
10850f29
JW		 5294 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5295 || ptr->r.type == body)
5296 ptr->slot_number = (unsigned long) f + i;
e0c9811a 5297
800eeca4
JW		 5298 if (idesc->flags & IA64_OPCODE_SLOT2)
5299 {
5300 if (manual_bundling && i != 2)
5301 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5302 "`%s' must be last in bundle", idesc->name);
5303 else
5304 i = 2;
5305 }
5306 if (idesc->flags & IA64_OPCODE_LAST)
5307 {
5308 int required_slot, required_template;
5309
5310 /* If we need a stop bit after an M slot, our only choice is
5311 template 5 (M;;MI). If we need a stop bit after a B
5312 slot, our only choice is to place it at the end of the
5313 bundle, because the only available templates are MIB,
5314 MBB, BBB, MMB, and MFB. We don't handle anything other
5315 than M and B slots because these are the only kind of
5316 instructions that can have the IA64_OPCODE_LAST bit set. */
5317 required_template = template;
5318 switch (idesc->type)
5319 {
5320 case IA64_TYPE_M:
5321 required_slot = 0;
5322 required_template = 5;
5323 break;
5324
5325 case IA64_TYPE_B:
5326 required_slot = 2;
5327 break;
5328
5329 default:
5330 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5331 "Internal error: don't know how to force %s to end"
5332 "of instruction group", idesc->name);
5333 required_slot = i;
5334 break;
5335 }
5336 if (manual_bundling && i != required_slot)
5337 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5338 "`%s' must be last in instruction group",
5339 idesc->name);
5340 if (required_slot < i)
5341 /* Can't fit this instruction. */
5342 break;
5343
5344 i = required_slot;
5345 if (required_template != template)
5346 {
5347 /* If we switch the template, we need to reset the NOPs
5348 after slot i. The slot-types of the instructions ahead
5349 of i never change, so we don't need to worry about
5350 changing NOPs in front of this slot. */
5351 for (j = i; j < 3; ++j)
5352 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5353 }
5354 template = required_template;
5355 }
5356 if (curr != first && md.slot[curr].label_fixups)
5357 {
5358 if (manual_bundling_on)
5359 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5360 "Label must be first in a bundle");
5361 /* This insn must go into the first slot of a bundle. */
5362 break;
5363 }
5364
5365 manual_bundling_on = md.slot[curr].manual_bundling_on;
5366 manual_bundling_off = md.slot[curr].manual_bundling_off;
5367
5368 if (manual_bundling_on)
5369 {
5370 if (curr == first)
5371 manual_bundling = 1;
5372 else
5373 break; /* need to start a new bundle */
5374 }
5375
5376 if (end_of_insn_group && md.num_slots_in_use >= 1)
5377 {
5378 /* We need an instruction group boundary in the middle of a
5379 bundle. See if we can switch to an other template with
5380 an appropriate boundary. */
5381
5382 orig_template = template;
5383 if (i == 1 && (user_template == 4
5384 || (user_template < 0
5385 && (ia64_templ_desc[template].exec_unit[0]
5386 == IA64_UNIT_M))))
5387 {
5388 template = 5;
5389 end_of_insn_group = 0;
5390 }
5391 else if (i == 2 && (user_template == 0
5392 || (user_template < 0
5393 && (ia64_templ_desc[template].exec_unit[1]
5394 == IA64_UNIT_I)))
5395 /* This test makes sure we don't switch the template if
5396 the next instruction is one that needs to be first in
5397 an instruction group. Since all those instructions are
5398 in the M group, there is no way such an instruction can
5399 fit in this bundle even if we switch the template. The
5400 reason we have to check for this is that otherwise we
5401 may end up generating "MI;;I M.." which has the deadly
5402 effect that the second M instruction is no longer the
5403 first in the bundle! --davidm 99/12/16 */
5404 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5405 {
5406 template = 1;
5407 end_of_insn_group = 0;
5408 }
5409 else if (curr != first)
5410 /* can't fit this insn */
5411 break;
5412
5413 if (template != orig_template)
5414 /* if we switch the template, we need to reset the NOPs
5415 after slot i. The slot-types of the instructions ahead
5416 of i never change, so we don't need to worry about
5417 changing NOPs in front of this slot. */
5418 for (j = i; j < 3; ++j)
5419 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5420 }
5421 required_unit = ia64_templ_desc[template].exec_unit[i];
5422
542d6675 5423 /* resolve dynamic opcodes such as "break" and "nop": */
800eeca4
JW		 5424 if (idesc->type == IA64_TYPE_DYN)
5425 {
5426 if ((strcmp (idesc->name, "nop") == 0)
5427 || (strcmp (idesc->name, "break") == 0))
5428 insn_unit = required_unit;
5429 else if (strcmp (idesc->name, "chk.s") == 0)
5430 {
5431 insn_unit = IA64_UNIT_M;
5432 if (required_unit == IA64_UNIT_I)
5433 insn_unit = IA64_UNIT_I;
5434 }
5435 else
5436 as_fatal ("emit_one_bundle: unexpected dynamic op");
5437
5438 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
3d56ab85 5439 ia64_free_opcode (idesc);
800eeca4
JW		 5440 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5441#if 0
5442 know (!idesc->next); /* no resolved dynamic ops have collisions */
5443#endif
5444 }
5445 else
5446 {
5447 insn_type = idesc->type;
5448 insn_unit = IA64_UNIT_NIL;
5449 switch (insn_type)
5450 {
5451 case IA64_TYPE_A:
5452 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5453 insn_unit = required_unit;
5454 break;
542d6675 5455 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
800eeca4
JW		 5456 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5457 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5458 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5459 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5460 default: break;
5461 }
5462 }
5463
5464 if (insn_unit != required_unit)
5465 {
5466 if (required_unit == IA64_UNIT_L
542d6675 5467 && insn_unit == IA64_UNIT_I
800eeca4
JW		 5468 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5469 {
5470 /* we got ourselves an MLX template but the current
197865e8 5471 instruction isn't an X-unit, or an I-unit instruction
800eeca4
JW		 5472 that can go into the X slot of an MLX template. Duh. */
5473 if (md.num_slots_in_use >= NUM_SLOTS)
5474 {
5475 as_bad_where (md.slot[curr].src_file,
5476 md.slot[curr].src_line,
5477 "`%s' can't go in X slot of "
5478 "MLX template", idesc->name);
542d6675 5479 /* drop this insn so we don't livelock: */
800eeca4
JW		 5480 --md.num_slots_in_use;
5481 }
5482 break;
5483 }
5484 continue; /* try next slot */
5485 }
5486
5487 if (debug_type == DEBUG_DWARF2)
5488 {
5489 bfd_vma addr;
5490
f1bcba5b 5491 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
800eeca4
JW		 5492 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5493 }
5494
5495 build_insn (md.slot + curr, insn + i);
5496
10850f29
JW		 5497 /* Set slot counts for non prologue/body unwind records. */
5498 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5499 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5500 && ptr->r.type != body)
5501 ptr->slot_number = (unsigned long) f + i;
5502 md.slot[curr].unwind_record = NULL;
e0c9811a 5503 unwind.next_slot_number = (unsigned long) f + i + ((i == 2)?(0x10-2):1);
10850f29 5504
800eeca4
JW		 5505 if (required_unit == IA64_UNIT_L)
5506 {
5507 know (i == 1);
5508 /* skip one slot for long/X-unit instructions */
5509 ++i;
5510 }
5511 --md.num_slots_in_use;
5512
542d6675 5513 /* now is a good time to fix up the labels for this insn: */
800eeca4
JW		 5514 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5515 {
5516 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5517 symbol_set_frag (lfix->sym, frag_now);
5518 }
f1bcba5b
JW		 5519 /* and fix up the tags also. */
5520 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
5521 {
5522 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
5523 symbol_set_frag (lfix->sym, frag_now);
5524 }
800eeca4
JW		 5525
5526 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5527 {
5528 ifix = md.slot[curr].fixup + j;
5529 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
5530 &ifix->expr, ifix->is_pcrel, ifix->code);
5531 fix->tc_fix_data.opnd = ifix->opnd;
5532 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5533 fix->fx_file = md.slot[curr].src_file;
5534 fix->fx_line = md.slot[curr].src_line;
5535 }
5536
5537 end_of_insn_group = md.slot[curr].end_of_insn_group;
5538
542d6675 5539 /* clear slot: */
800eeca4
JW		 5540 ia64_free_opcode (md.slot[curr].idesc);
5541 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5542 md.slot[curr].user_template = -1;
5543
5544 if (manual_bundling_off)
5545 {
5546 manual_bundling = 0;
5547 break;
5548 }
5549 curr = (curr + 1) % NUM_SLOTS;
5550 idesc = md.slot[curr].idesc;
5551 }
5552 if (manual_bundling)
5553 {
5554 if (md.num_slots_in_use > 0)
5555 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5556 "`%s' does not fit into %s template",
5557 idesc->name, ia64_templ_desc[template].name);
5558 else
5559 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5560 "Missing '}' at end of file");
5561 }
5562 know (md.num_slots_in_use < NUM_SLOTS);
5563
5564 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5565 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5566
44f5c83a
JW		 5567 number_to_chars_littleendian (f + 0, t0, 8);
5568 number_to_chars_littleendian (f + 8, t1, 8);
800eeca4
JW		 5569}
5570
5571int
5572md_parse_option (c, arg)
5573 int c;
5574 char *arg;
5575{
800eeca4
JW		 5576 switch (c)
5577 {
c43c2cc5 5578 /* Switches from the Intel assembler. */
44f5c83a 5579 case 'm':
800eeca4
JW		 5580 if (strcmp (arg, "ilp64") == 0
5581 || strcmp (arg, "lp64") == 0
5582 || strcmp (arg, "p64") == 0)
5583 {
5584 md.flags |= EF_IA_64_ABI64;
5585 }
5586 else if (strcmp (arg, "ilp32") == 0)
5587 {
5588 md.flags &= ~EF_IA_64_ABI64;
5589 }
5590 else if (strcmp (arg, "le") == 0)
5591 {
5592 md.flags &= ~EF_IA_64_BE;
5593 }
5594 else if (strcmp (arg, "be") == 0)
5595 {
5596 md.flags |= EF_IA_64_BE;
5597 }
5598 else
5599 return 0;
5600 break;
5601
5602 case 'N':
5603 if (strcmp (arg, "so") == 0)
5604 {
542d6675 5605 /* Suppress signon message. */
800eeca4
JW		 5606 }
5607 else if (strcmp (arg, "pi") == 0)
5608 {
5609 /* Reject privileged instructions. FIXME */
5610 }
5611 else if (strcmp (arg, "us") == 0)
5612 {
5613 /* Allow union of signed and unsigned range. FIXME */
5614 }
5615 else if (strcmp (arg, "close_fcalls") == 0)
5616 {
5617 /* Do not resolve global function calls. */
5618 }
5619 else
5620 return 0;
5621 break;
5622
5623 case 'C':
5624 /* temp[="prefix"] Insert temporary labels into the object file
5625 symbol table prefixed by "prefix".
5626 Default prefix is ":temp:".
5627 */
5628 break;
5629
5630 case 'a':
5631 /* ??? Conflicts with gas' listing option. */
5632 /* indirect=<tgt> Assume unannotated indirect branches behavior
5633 according to <tgt> --
5634 exit: branch out from the current context (default)
5635 labels: all labels in context may be branch targets
5636 */
5637 break;
5638
5639 case 'x':
5640 /* -X conflicts with an ignored option, use -x instead */
5641 md.detect_dv = 1;
5642 if (!arg || strcmp (arg, "explicit") == 0)
542d6675
KH		 5643 {
5644 /* set default mode to explicit */
5645 md.default_explicit_mode = 1;
5646 break;
5647 }
800eeca4 5648 else if (strcmp (arg, "auto") == 0)
542d6675
KH		 5649 {
5650 md.default_explicit_mode = 0;
5651 }
800eeca4 5652 else if (strcmp (arg, "debug") == 0)
542d6675
KH		 5653 {
5654 md.debug_dv = 1;
5655 }
800eeca4 5656 else if (strcmp (arg, "debugx") == 0)
542d6675
KH		 5657 {
5658 md.default_explicit_mode = 1;
5659 md.debug_dv = 1;
5660 }
800eeca4 5661 else
542d6675
KH		 5662 {
5663 as_bad (_("Unrecognized option '-x%s'"), arg);
5664 }
800eeca4
JW		 5665 break;
5666
5667 case 'S':
5668 /* nops Print nops statistics. */
5669 break;
5670
c43c2cc5
JW		 5671 /* GNU specific switches for gcc. */
5672 case OPTION_MCONSTANT_GP:
5673 md.flags |= EF_IA_64_CONS_GP;
5674 break;
5675
5676 case OPTION_MAUTO_PIC:
5677 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
5678 break;
5679
800eeca4
JW		 5680 default:
5681 return 0;
5682 }
5683
5684 return 1;
5685}
5686
5687void
5688md_show_usage (stream)
5689 FILE *stream;
5690{
542d6675 5691 fputs (_("\
800eeca4 5692IA-64 options:\n\
44f5c83a
JW		 5693 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
5694 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
800eeca4
JW		 5695 -x | -xexplicit turn on dependency violation checking (default)\n\
5696 -xauto automagically remove dependency violations\n\
5697 -xdebug debug dependency violation checker\n"),
5698 stream);
5699}
5700
44576e1f
RH		 5701/* Return true if TYPE fits in TEMPL at SLOT. */
5702
5703static int
800eeca4
JW		 5704match (int templ, int type, int slot)
5705{
5706 enum ia64_unit unit;
5707 int result;
5708
5709 unit = ia64_templ_desc[templ].exec_unit[slot];
5710 switch (type)
5711 {
5712 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5713 case IA64_TYPE_A:
5714 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5715 break;
5716 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5717 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5718 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5719 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5720 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5721 default: result = 0; break;
5722 }
5723 return result;
5724}
5725
44576e1f
RH		 5726/* Add a bit of extra goodness if a nop of type F or B would fit
5727 in TEMPL at SLOT. */
5728
5729static inline int
5730extra_goodness (int templ, int slot)
5731{
ebeeafe6 5732 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
44576e1f 5733 return 2;
ebeeafe6 5734 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
44576e1f
RH		 5735 return 1;
5736 return 0;
5737}
5738
800eeca4
JW		 5739/* This function is called once, at assembler startup time. It sets
5740 up all the tables, etc. that the MD part of the assembler will need
5741 that can be determined before arguments are parsed. */
5742void
5743md_begin ()
5744{
44f5c83a 5745 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
800eeca4
JW		 5746 const char *err;
5747 char name[8];
5748
5749 md.auto_align = 1;
5750 md.explicit_mode = md.default_explicit_mode;
5751
5752 bfd_set_section_alignment (stdoutput, text_section, 4);
5753
44f5c83a 5754 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
800eeca4 5755 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
542d6675
KH		 5756 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5757 &zero_address_frag);
800eeca4
JW		 5758
5759 pseudo_func[FUNC_GP_RELATIVE].u.sym =
542d6675
KH		 5760 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5761 &zero_address_frag);
800eeca4
JW		 5762
5763 pseudo_func[FUNC_LT_RELATIVE].u.sym =
542d6675
KH		 5764 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5765 &zero_address_frag);
800eeca4 5766
c67e42c9 5767 pseudo_func[FUNC_PC_RELATIVE].u.sym =
542d6675
KH		 5768 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5769 &zero_address_frag);
c67e42c9 5770
800eeca4 5771 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
542d6675
KH		 5772 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5773 &zero_address_frag);
800eeca4
JW		 5774
5775 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
542d6675
KH		 5776 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5777 &zero_address_frag);
800eeca4
JW		 5778
5779 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
542d6675
KH		 5780 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5781 &zero_address_frag);
800eeca4
JW		 5782
5783 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
542d6675
KH		 5784 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5785 &zero_address_frag);
800eeca4
JW		 5786
5787 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
542d6675
KH		 5788 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5789 &zero_address_frag);
800eeca4 5790
197865e8 5791 /* Compute the table of best templates. We compute goodness as a
44576e1f
RH		 5792 base 4 value, in which each match counts for 3, each F counts
5793 for 2, each B counts for 1. This should maximize the number of
5794 F and B nops in the chosen bundles, which is good because these
5795 pipelines are least likely to be overcommitted. */
800eeca4
JW		 5796 for (i = 0; i < IA64_NUM_TYPES; ++i)
5797 for (j = 0; j < IA64_NUM_TYPES; ++j)
5798 for (k = 0; k < IA64_NUM_TYPES; ++k)
5799 {
5800 best = 0;
5801 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
5802 {
5803 goodness = 0;
5804 if (match (t, i, 0))
5805 {
5806 if (match (t, j, 1))
5807 {
5808 if (match (t, k, 2))
44576e1f 5809 goodness = 3 + 3 + 3;
800eeca4 5810 else
44576e1f 5811 goodness = 3 + 3 + extra_goodness (t, 2);
800eeca4
JW		 5812 }
5813 else if (match (t, j, 2))
44576e1f 5814 goodness = 3 + 3 + extra_goodness (t, 1);
800eeca4 5815 else
44576e1f
RH		 5816 {
5817 goodness = 3;
5818 goodness += extra_goodness (t, 1);
5819 goodness += extra_goodness (t, 2);
5820 }
800eeca4
JW		 5821 }
5822 else if (match (t, i, 1))
5823 {
5824 if (match (t, j, 2))
44576e1f 5825 goodness = 3 + 3;
800eeca4 5826 else
44576e1f 5827 goodness = 3 + extra_goodness (t, 2);
800eeca4
JW		 5828 }
5829 else if (match (t, i, 2))
44576e1f 5830 goodness = 3 + extra_goodness (t, 1);
800eeca4
JW		 5831
5832 if (goodness > best)
5833 {
5834 best = goodness;
5835 best_template[i][j][k] = t;
5836 }
5837 }
5838 }
5839
5840 for (i = 0; i < NUM_SLOTS; ++i)
5841 md.slot[i].user_template = -1;
5842
5843 md.pseudo_hash = hash_new ();
5844 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
5845 {
5846 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
5847 (void *) (pseudo_opcode + i));
5848 if (err)
5849 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5850 pseudo_opcode[i].name, err);
5851 }
5852
5853 md.reg_hash = hash_new ();
5854 md.dynreg_hash = hash_new ();
5855 md.const_hash = hash_new ();
5856 md.entry_hash = hash_new ();
5857
542d6675 5858 /* general registers: */
800eeca4
JW		 5859
5860 total = 128;
5861 for (i = 0; i < total; ++i)
5862 {
5863 sprintf (name, "r%d", i - REG_GR);
5864 md.regsym[i] = declare_register (name, i);
5865 }
5866
542d6675 5867 /* floating point registers: */
800eeca4
JW		 5868 total += 128;
5869 for (; i < total; ++i)
5870 {
5871 sprintf (name, "f%d", i - REG_FR);
5872 md.regsym[i] = declare_register (name, i);
5873 }
5874
542d6675 5875 /* application registers: */
800eeca4
JW		 5876 total += 128;
5877 ar_base = i;
5878 for (; i < total; ++i)
5879 {
5880 sprintf (name, "ar%d", i - REG_AR);
5881 md.regsym[i] = declare_register (name, i);
5882 }
5883
542d6675 5884 /* control registers: */
800eeca4
JW		 5885 total += 128;
5886 cr_base = i;
5887 for (; i < total; ++i)
5888 {
5889 sprintf (name, "cr%d", i - REG_CR);
5890 md.regsym[i] = declare_register (name, i);
5891 }
5892
542d6675 5893 /* predicate registers: */
800eeca4
JW		 5894 total += 64;
5895 for (; i < total; ++i)
5896 {
5897 sprintf (name, "p%d", i - REG_P);
5898 md.regsym[i] = declare_register (name, i);
5899 }
5900
542d6675 5901 /* branch registers: */
800eeca4
JW		 5902 total += 8;
5903 for (; i < total; ++i)
5904 {
5905 sprintf (name, "b%d", i - REG_BR);
5906 md.regsym[i] = declare_register (name, i);
5907 }
5908
5909 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
5910 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
5911 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
5912 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
5913 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
5914 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
5915 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
5916
5917 for (i = 0; i < NELEMS (indirect_reg); ++i)
5918 {
5919 regnum = indirect_reg[i].regnum;
5920 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
5921 }
5922
542d6675 5923 /* define synonyms for application registers: */
800eeca4
JW		 5924 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
5925 md.regsym[i] = declare_register (ar[i - REG_AR].name,
5926 REG_AR + ar[i - REG_AR].regnum);
5927
542d6675 5928 /* define synonyms for control registers: */
800eeca4
JW		 5929 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
5930 md.regsym[i] = declare_register (cr[i - REG_CR].name,
5931 REG_CR + cr[i - REG_CR].regnum);
5932
5933 declare_register ("gp", REG_GR + 1);
5934 declare_register ("sp", REG_GR + 12);
5935 declare_register ("rp", REG_BR + 0);
5936
542d6675 5937 /* pseudo-registers used to specify unwind info: */
e0c9811a
JW		 5938 declare_register ("psp", REG_PSP);
5939
800eeca4
JW		 5940 declare_register_set ("ret", 4, REG_GR + 8);
5941 declare_register_set ("farg", 8, REG_FR + 8);
5942 declare_register_set ("fret", 8, REG_FR + 8);
5943
5944 for (i = 0; i < NELEMS (const_bits); ++i)
5945 {
5946 err = hash_insert (md.const_hash, const_bits[i].name,
5947 (PTR) (const_bits + i));
5948 if (err)
5949 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5950 name, err);
5951 }
5952
44f5c83a
JW		 5953 /* Set the architecture and machine depending on defaults and command line
5954 options. */
5955 if (md.flags & EF_IA_64_ABI64)
5956 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
5957 else
5958 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
5959
5960 if (! ok)
5961 as_warn (_("Could not set architecture and machine"));
800eeca4
JW		 5962
5963 md.mem_offset.hint = 0;
5964 md.path = 0;
5965 md.maxpaths = 0;
5966 md.entry_labels = NULL;
5967}
5968
44f5c83a
JW		 5969/* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
5970 because that is called after md_parse_option which is where we do the
5971 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
5972 default endianness. */
5973
5974void
5975ia64_init (argc, argv)
5976 int argc;
5977 char **argv;
5978{
5979 md.flags = EF_IA_64_ABI64;
5980 if (TARGET_BYTES_BIG_ENDIAN)
5981 md.flags |= EF_IA_64_BE;
5982}
5983
5984/* Return a string for the target object file format. */
5985
5986const char *
5987ia64_target_format ()
5988{
5989 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
5990 {
5991 if (md.flags & EF_IA_64_ABI64)
5992 return "elf64-ia64-big";
5993 else
5994 return "elf32-ia64-big";
5995 }
5996 else
5997 return "unknown-format";
5998}
5999
800eeca4
JW		 6000void
6001ia64_end_of_source ()
6002{
542d6675 6003 /* terminate insn group upon reaching end of file: */
800eeca4
JW		 6004 insn_group_break (1, 0, 0);
6005
542d6675 6006 /* emits slots we haven't written yet: */
800eeca4
JW		 6007 ia64_flush_insns ();
6008
6009 bfd_set_private_flags (stdoutput, md.flags);
6010
6011 if (debug_type == DEBUG_DWARF2)
6012 dwarf2_finish ();
6013
6014 md.mem_offset.hint = 0;
6015}
6016
6017void
6018ia64_start_line ()
6019{
f1bcba5b
JW		 6020 if (md.qp.X_op == O_register)
6021 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW		 6022 md.qp.X_op = O_absent;
6023
6024 if (ignore_input ())
6025 return;
6026
6027 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6028 {
6029 if (md.detect_dv && !md.explicit_mode)
542d6675 6030 as_warn (_("Explicit stops are ignored in auto mode"));
800eeca4 6031 else
542d6675 6032 insn_group_break (1, 0, 0);
800eeca4
JW		 6033 }
6034}
6035
f1bcba5b
JW		 6036/* This is a hook for ia64_frob_label, so that it can distinguish tags from
6037 labels. */
6038static int defining_tag = 0;
6039
800eeca4
JW		 6040int
6041ia64_unrecognized_line (ch)
6042 int ch;
6043{
6044 switch (ch)
6045 {
6046 case '(':
6047 expression (&md.qp);
6048 if (*input_line_pointer++ != ')')
6049 {
6050 as_bad ("Expected ')'");
6051 return 0;
6052 }
6053 if (md.qp.X_op != O_register)
6054 {
6055 as_bad ("Qualifying predicate expected");
6056 return 0;
6057 }
6058 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6059 {
6060 as_bad ("Predicate register expected");
6061 return 0;
6062 }
6063 return 1;
6064
6065 case '{':
6066 if (md.manual_bundling)
6067 as_warn ("Found '{' when manual bundling is already turned on");
6068 else
6069 CURR_SLOT.manual_bundling_on = 1;
6070 md.manual_bundling = 1;
6071
542d6675
KH		 6072 /* Bundling is only acceptable in explicit mode
6073 or when in default automatic mode. */
800eeca4 6074 if (md.detect_dv && !md.explicit_mode)
542d6675
KH		 6075 {
6076 if (!md.mode_explicitly_set
6077 && !md.default_explicit_mode)
6078 dot_dv_mode ('E');
6079 else
6080 as_warn (_("Found '{' after explicit switch to automatic mode"));
6081 }
800eeca4
JW		 6082 return 1;
6083
6084 case '}':
6085 if (!md.manual_bundling)
6086 as_warn ("Found '}' when manual bundling is off");
6087 else
6088 PREV_SLOT.manual_bundling_off = 1;
6089 md.manual_bundling = 0;
6090
6091 /* switch back to automatic mode, if applicable */
197865e8 6092 if (md.detect_dv
542d6675
KH		 6093 && md.explicit_mode
6094 && !md.mode_explicitly_set
6095 && !md.default_explicit_mode)
6096 dot_dv_mode ('A');
800eeca4
JW		 6097
6098 /* Allow '{' to follow on the same line. We also allow ";;", but that
6099 happens automatically because ';' is an end of line marker. */
6100 SKIP_WHITESPACE ();
6101 if (input_line_pointer[0] == '{')
6102 {
6103 input_line_pointer++;
6104 return ia64_unrecognized_line ('{');
6105 }
6106
6107 demand_empty_rest_of_line ();
6108 return 1;
6109
f1bcba5b
JW		 6110 case '[':
6111 {
6112 char *s;
6113 char c;
6114 symbolS *tag;
6115
6116 if (md.qp.X_op == O_register)
6117 {
6118 as_bad ("Tag must come before qualifying predicate.");
6119 return 0;
6120 }
6121 s = input_line_pointer;
6122 c = get_symbol_end ();
6123 if (c != ':')
6124 {
6125 /* Put ':' back for error messages' sake. */
6126 *input_line_pointer++ = ':';
6127 as_bad ("Expected ':'");
6128 return 0;
6129 }
6130 defining_tag = 1;
6131 tag = colon (s);
6132 defining_tag = 0;
6133 /* Put ':' back for error messages' sake. */
6134 *input_line_pointer++ = ':';
6135 if (*input_line_pointer++ != ']')
6136 {
6137 as_bad ("Expected ']'");
6138 return 0;
6139 }
6140 if (! tag)
6141 {
6142 as_bad ("Tag name expected");
6143 return 0;
6144 }
6145 return 1;
6146 }
6147
800eeca4
JW		 6148 default:
6149 break;
6150 }
542d6675
KH		 6151
6152 /* Not a valid line. */
6153 return 0;
800eeca4
JW		 6154}
6155
6156void
6157ia64_frob_label (sym)
6158 struct symbol *sym;
6159{
6160 struct label_fix *fix;
6161
f1bcba5b
JW		 6162 /* Tags need special handling since they are not bundle breaks like
6163 labels. */
6164 if (defining_tag)
6165 {
6166 fix = obstack_alloc (&notes, sizeof (*fix));
6167 fix->sym = sym;
6168 fix->next = CURR_SLOT.tag_fixups;
6169 CURR_SLOT.tag_fixups = fix;
6170
6171 return;
6172 }
6173
800eeca4
JW		 6174 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6175 {
6176 md.last_text_seg = now_seg;
6177 fix = obstack_alloc (&notes, sizeof (*fix));
6178 fix->sym = sym;
6179 fix->next = CURR_SLOT.label_fixups;
6180 CURR_SLOT.label_fixups = fix;
6181
542d6675 6182 /* Keep track of how many code entry points we've seen. */
800eeca4 6183 if (md.path == md.maxpaths)
542d6675
KH		 6184 {
6185 md.maxpaths += 20;
6186 md.entry_labels = (const char **)
6187 xrealloc ((void *) md.entry_labels,
6188 md.maxpaths * sizeof (char *));
6189 }
800eeca4
JW		 6190 md.entry_labels[md.path++] = S_GET_NAME (sym);
6191 }
6192}
6193
6194void
6195ia64_flush_pending_output ()
6196{
6197 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6198 {
6199 /* ??? This causes many unnecessary stop bits to be emitted.
6200 Unfortunately, it isn't clear if it is safe to remove this. */
6201 insn_group_break (1, 0, 0);
6202 ia64_flush_insns ();
6203 }
6204}
6205
6206/* Do ia64-specific expression optimization. All that's done here is
6207 to transform index expressions that are either due to the indexing
6208 of rotating registers or due to the indexing of indirect register
6209 sets. */
6210int
6211ia64_optimize_expr (l, op, r)
6212 expressionS *l;
6213 operatorT op;
6214 expressionS *r;
6215{
6216 unsigned num_regs;
6217
6218 if (op == O_index)
6219 {
6220 if (l->X_op == O_register && r->X_op == O_constant)
6221 {
6222 num_regs = (l->X_add_number >> 16);
6223 if ((unsigned) r->X_add_number >= num_regs)
6224 {
6225 if (!num_regs)
6226 as_bad ("No current frame");
6227 else
6228 as_bad ("Index out of range 0..%u", num_regs - 1);
6229 r->X_add_number = 0;
6230 }
6231 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6232 return 1;
6233 }
6234 else if (l->X_op == O_register && r->X_op == O_register)
6235 {
6236 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6237 || l->X_add_number == IND_MEM)
6238 {
6239 as_bad ("Indirect register set name expected");
6240 l->X_add_number = IND_CPUID;
6241 }
6242 l->X_op = O_index;
6243 l->X_op_symbol = md.regsym[l->X_add_number];
6244 l->X_add_number = r->X_add_number;
6245 return 1;
6246 }
6247 }
6248 return 0;
6249}
6250
6251int
6252ia64_parse_name (name, e)
6253 char *name;
6254 expressionS *e;
6255{
6256 struct const_desc *cdesc;
6257 struct dynreg *dr = 0;
6258 unsigned int regnum;
6259 struct symbol *sym;
6260 char *end;
6261
542d6675 6262 /* first see if NAME is a known register name: */
800eeca4
JW		 6263 sym = hash_find (md.reg_hash, name);
6264 if (sym)
6265 {
6266 e->X_op = O_register;
6267 e->X_add_number = S_GET_VALUE (sym);
6268 return 1;
6269 }
6270
6271 cdesc = hash_find (md.const_hash, name);
6272 if (cdesc)
6273 {
6274 e->X_op = O_constant;
6275 e->X_add_number = cdesc->value;
6276 return 1;
6277 }
6278
542d6675 6279 /* check for inN, locN, or outN: */
800eeca4
JW		 6280 switch (name[0])
6281 {
6282 case 'i':
6283 if (name[1] == 'n' && isdigit (name[2]))
6284 {
6285 dr = &md.in;
6286 name += 2;
6287 }
6288 break;
6289
6290 case 'l':
6291 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6292 {
6293 dr = &md.loc;
6294 name += 3;
6295 }
6296 break;
6297
6298 case 'o':
6299 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6300 {
6301 dr = &md.out;
6302 name += 3;
6303 }
6304 break;
6305
6306 default:
6307 break;
6308 }
6309
6310 if (dr)
6311 {
542d6675 6312 /* The name is inN, locN, or outN; parse the register number. */
800eeca4
JW		 6313 regnum = strtoul (name, &end, 10);
6314 if (end > name && *end == '\0')
6315 {
6316 if ((unsigned) regnum >= dr->num_regs)
6317 {
6318 if (!dr->num_regs)
6319 as_bad ("No current frame");
6320 else
542d6675
KH		 6321 as_bad ("Register number out of range 0..%u",
6322 dr->num_regs - 1);
800eeca4
JW		 6323 regnum = 0;
6324 }
6325 e->X_op = O_register;
6326 e->X_add_number = dr->base + regnum;
6327 return 1;
6328 }
6329 }
6330
6331 if ((dr = hash_find (md.dynreg_hash, name)))
6332 {
6333 /* We've got ourselves the name of a rotating register set.
542d6675
KH		 6334 Store the base register number in the low 16 bits of
6335 X_add_number and the size of the register set in the top 16
6336 bits. */
800eeca4
JW		 6337 e->X_op = O_register;
6338 e->X_add_number = dr->base | (dr->num_regs << 16);
6339 return 1;
6340 }
6341 return 0;
6342}
6343
6344/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6345
6346char *
6347ia64_canonicalize_symbol_name (name)
6348 char *name;
6349{
542d6675
KH		 6350 size_t len = strlen (name);
6351 if (len > 1 && name[len - 1] == '#')
6352 name[len - 1] = '\0';
800eeca4
JW		 6353 return name;
6354}
6355
6356static int
6357is_conditional_branch (idesc)
542d6675 6358 struct ia64_opcode *idesc;
800eeca4
JW		 6359{
6360 return (strncmp (idesc->name, "br", 2) == 0
542d6675
KH		 6361 && (strcmp (idesc->name, "br") == 0
6362 || strncmp (idesc->name, "br.cond", 7) == 0
6363 || strncmp (idesc->name, "br.call", 7) == 0
6364 || strncmp (idesc->name, "br.ret", 6) == 0
6365 || strcmp (idesc->name, "brl") == 0
6366 || strncmp (idesc->name, "brl.cond", 7) == 0
6367 || strncmp (idesc->name, "brl.call", 7) == 0
6368 || strncmp (idesc->name, "brl.ret", 6) == 0));
800eeca4
JW		 6369}
6370
6371/* Return whether the given opcode is a taken branch. If there's any doubt,
542d6675
KH		 6372 returns zero. */
6373
800eeca4
JW		 6374static int
6375is_taken_branch (idesc)
542d6675 6376 struct ia64_opcode *idesc;
800eeca4
JW		 6377{
6378 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
542d6675 6379 || strncmp (idesc->name, "br.ia", 5) == 0);
800eeca4
JW		 6380}
6381
6382/* Return whether the given opcode is an interruption or rfi. If there's any
542d6675
KH		 6383 doubt, returns zero. */
6384
800eeca4
JW		 6385static int
6386is_interruption_or_rfi (idesc)
542d6675 6387 struct ia64_opcode *idesc;
800eeca4
JW		 6388{
6389 if (strcmp (idesc->name, "rfi") == 0)
6390 return 1;
6391 return 0;
6392}
6393
6394/* Returns the index of the given dependency in the opcode's list of chks, or
6395 -1 if there is no dependency. */
542d6675 6396
800eeca4
JW		 6397static int
6398depends_on (depind, idesc)
542d6675
KH		 6399 int depind;
6400 struct ia64_opcode *idesc;
800eeca4
JW		 6401{
6402 int i;
6403 const struct ia64_opcode_dependency *dep = idesc->dependencies;
542d6675 6404 for (i = 0; i < dep->nchks; i++)
800eeca4 6405 {
542d6675
KH		 6406 if (depind == DEP (dep->chks[i]))
6407 return i;
800eeca4
JW		 6408 }
6409 return -1;
6410}
6411
6412/* Determine a set of specific resources used for a particular resource
6413 class. Returns the number of specific resources identified For those
6414 cases which are not determinable statically, the resource returned is
197865e8 6415 marked nonspecific.
800eeca4
JW		 6416
6417 Meanings of value in 'NOTE':
6418 1) only read/write when the register number is explicitly encoded in the
6419 insn.
6420 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
197865e8 6421 accesses CFM when qualifying predicate is in the rotating region.
800eeca4
JW		 6422 3) general register value is used to specify an indirect register; not
6423 determinable statically.
6424 4) only read the given resource when bits 7:0 of the indirect index
6425 register value does not match the register number of the resource; not
6426 determinable statically.
6427 5) all rules are implementation specific.
6428 6) only when both the index specified by the reader and the index specified
6429 by the writer have the same value in bits 63:61; not determinable
197865e8 6430 statically.
800eeca4 6431 7) only access the specified resource when the corresponding mask bit is
197865e8 6432 set
800eeca4
JW		 6433 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6434 only read when these insns reference FR2-31
6435 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6436 written when these insns write FR32-127
6437 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6438 instruction
6439 11) The target predicates are written independently of PR[qp], but source
6440 registers are only read if PR[qp] is true. Since the state of PR[qp]
6441 cannot statically be determined, all source registers are marked used.
6442 12) This insn only reads the specified predicate register when that
6443 register is the PR[qp].
6444 13) This reference to ld-c only applies to teh GR whose value is loaded
197865e8 6445 with data returned from memory, not the post-incremented address register.
800eeca4
JW		 6446 14) The RSE resource includes the implementation-specific RSE internal
6447 state resources. At least one (and possibly more) of these resources are
6448 read by each instruction listed in IC:rse-readers. At least one (and
6449 possibly more) of these resources are written by each insn listed in
197865e8 6450 IC:rse-writers.
800eeca4 6451 15+16) Represents reserved instructions, which the assembler does not
197865e8 6452 generate.
800eeca4
JW		 6453
6454 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6455 this code; there are no dependency violations based on memory access.
800eeca4
JW		 6456*/
6457
6458#define MAX_SPECS 256
6459#define DV_CHK 1
6460#define DV_REG 0
6461
6462static int
6463specify_resource (dep, idesc, type, specs, note, path)
542d6675
KH		 6464 const struct ia64_dependency *dep;
6465 struct ia64_opcode *idesc;
6466 int type; /* is this a DV chk or a DV reg? */
6467 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6468 int note; /* resource note for this insn's usage */
6469 int path; /* which execution path to examine */
800eeca4
JW		 6470{
6471 int count = 0;
6472 int i;
6473 int rsrc_write = 0;
6474 struct rsrc tmpl;
197865e8 6475
800eeca4
JW		 6476 if (dep->mode == IA64_DV_WAW
6477 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6478 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6479 rsrc_write = 1;
6480
6481 /* template for any resources we identify */
6482 tmpl.dependency = dep;
6483 tmpl.note = note;
6484 tmpl.insn_srlz = tmpl.data_srlz = 0;
6485 tmpl.qp_regno = CURR_SLOT.qp_regno;
6486 tmpl.link_to_qp_branch = 1;
6487 tmpl.mem_offset.hint = 0;
6488 tmpl.specific = 1;
6489 tmpl.index = 0;
7484b8e6 6490 tmpl.cmp_type = CMP_NONE;
800eeca4
JW		 6491
6492#define UNHANDLED \
6493as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6494dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6495#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6496
6497 /* we don't need to track these */
6498 if (dep->semantics == IA64_DVS_NONE)
6499 return 0;
6500
6501 switch (dep->specifier)
6502 {
6503 case IA64_RS_AR_K:
6504 if (note == 1)
542d6675
KH		 6505 {
6506 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6507 {
6508 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6509 if (regno >= 0 && regno <= 7)
6510 {
6511 specs[count] = tmpl;
6512 specs[count++].index = regno;
6513 }
6514 }
6515 }
800eeca4 6516 else if (note == 0)
542d6675
KH		 6517 {
6518 for (i = 0; i < 8; i++)
6519 {
6520 specs[count] = tmpl;
6521 specs[count++].index = i;
6522 }
6523 }
800eeca4 6524 else
542d6675
KH		 6525 {
6526 UNHANDLED;
6527 }
800eeca4
JW		 6528 break;
6529
6530 case IA64_RS_AR_UNAT:
6531 /* This is a mov =AR or mov AR= instruction. */
6532 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6533 {
6534 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6535 if (regno == AR_UNAT)
6536 {
6537 specs[count++] = tmpl;
6538 }
6539 }
6540 else
6541 {
6542 /* This is a spill/fill, or other instruction that modifies the
6543 unat register. */
6544
6545 /* Unless we can determine the specific bits used, mark the whole
6546 thing; bits 8:3 of the memory address indicate the bit used in
6547 UNAT. The .mem.offset hint may be used to eliminate a small
6548 subset of conflicts. */
6549 specs[count] = tmpl;
6550 if (md.mem_offset.hint)
6551 {
542d6675
KH		 6552 if (md.debug_dv)
6553 fprintf (stderr, " Using hint for spill/fill\n");
6554 /* The index isn't actually used, just set it to something
6555 approximating the bit index. */
800eeca4
JW		 6556 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6557 specs[count].mem_offset.hint = 1;
6558 specs[count].mem_offset.offset = md.mem_offset.offset;
6559 specs[count++].mem_offset.base = md.mem_offset.base;
6560 }
6561 else
6562 {
6563 specs[count++].specific = 0;
6564 }
6565 }
6566 break;
6567
6568 case IA64_RS_AR:
6569 if (note == 1)
542d6675
KH		 6570 {
6571 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6572 {
6573 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6574 if ((regno >= 8 && regno <= 15)
6575 || (regno >= 20 && regno <= 23)
6576 || (regno >= 31 && regno <= 39)
6577 || (regno >= 41 && regno <= 47)
6578 || (regno >= 67 && regno <= 111))
6579 {
6580 specs[count] = tmpl;
6581 specs[count++].index = regno;
6582 }
6583 }
6584 }
800eeca4 6585 else
542d6675
KH		 6586 {
6587 UNHANDLED;
6588 }
800eeca4
JW		 6589 break;
6590
6591 case IA64_RS_ARb:
6592 if (note == 1)
542d6675
KH		 6593 {
6594 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6595 {
6596 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6597 if ((regno >= 48 && regno <= 63)
6598 || (regno >= 112 && regno <= 127))
6599 {
6600 specs[count] = tmpl;
6601 specs[count++].index = regno;
6602 }
6603 }
6604 }
800eeca4 6605 else if (note == 0)
542d6675
KH		 6606 {
6607 for (i = 48; i < 64; i++)
6608 {
6609 specs[count] = tmpl;
6610 specs[count++].index = i;
6611 }
6612 for (i = 112; i < 128; i++)
6613 {
6614 specs[count] = tmpl;
6615 specs[count++].index = i;
6616 }
6617 }
197865e8 6618 else
542d6675
KH		 6619 {
6620 UNHANDLED;
6621 }
800eeca4
JW		 6622 break;
6623
6624 case IA64_RS_BR:
6625 if (note != 1)
542d6675
KH		 6626 {
6627 UNHANDLED;
6628 }
800eeca4 6629 else
542d6675
KH		 6630 {
6631 if (rsrc_write)
6632 {
6633 for (i = 0; i < idesc->num_outputs; i++)
6634 if (idesc->operands[i] == IA64_OPND_B1
6635 || idesc->operands[i] == IA64_OPND_B2)
6636 {
6637 specs[count] = tmpl;
6638 specs[count++].index =
6639 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6640 }
6641 }
6642 else
6643 {
6644 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
6645 if (idesc->operands[i] == IA64_OPND_B1
6646 || idesc->operands[i] == IA64_OPND_B2)
6647 {
6648 specs[count] = tmpl;
6649 specs[count++].index =
6650 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6651 }
6652 }
6653 }
800eeca4
JW		 6654 break;
6655
6656 case IA64_RS_CPUID: /* four or more registers */
6657 if (note == 3)
542d6675
KH		 6658 {
6659 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6660 {
6661 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6662 if (regno >= 0 && regno < NELEMS (gr_values)
6663 && KNOWN (regno))
6664 {
6665 specs[count] = tmpl;
6666 specs[count++].index = gr_values[regno].value & 0xFF;
6667 }
6668 else
6669 {
6670 specs[count] = tmpl;
6671 specs[count++].specific = 0;
6672 }
6673 }
6674 }
800eeca4 6675 else
542d6675
KH		 6676 {
6677 UNHANDLED;
6678 }
800eeca4
JW		 6679 break;
6680
6681 case IA64_RS_DBR: /* four or more registers */
6682 if (note == 3)
542d6675
KH		 6683 {
6684 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6685 {
6686 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6687 if (regno >= 0 && regno < NELEMS (gr_values)
6688 && KNOWN (regno))
6689 {
6690 specs[count] = tmpl;
6691 specs[count++].index = gr_values[regno].value & 0xFF;
6692 }
6693 else
6694 {
6695 specs[count] = tmpl;
6696 specs[count++].specific = 0;
6697 }
6698 }
6699 }
800eeca4 6700 else if (note == 0 && !rsrc_write)
542d6675
KH		 6701 {
6702 specs[count] = tmpl;
6703 specs[count++].specific = 0;
6704 }
800eeca4 6705 else
542d6675
KH		 6706 {
6707 UNHANDLED;
6708 }
800eeca4
JW		 6709 break;
6710
6711 case IA64_RS_IBR: /* four or more registers */
6712 if (note == 3)
542d6675
KH		 6713 {
6714 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6715 {
6716 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6717 if (regno >= 0 && regno < NELEMS (gr_values)
6718 && KNOWN (regno))
6719 {
6720 specs[count] = tmpl;
6721 specs[count++].index = gr_values[regno].value & 0xFF;
6722 }
6723 else
6724 {
6725 specs[count] = tmpl;
6726 specs[count++].specific = 0;
6727 }
6728 }
6729 }
800eeca4 6730 else
542d6675
KH		 6731 {
6732 UNHANDLED;
6733 }
800eeca4
JW		 6734 break;
6735
6736 case IA64_RS_MSR:
6737 if (note == 5)
6738 {
6739 /* These are implementation specific. Force all references to
6740 conflict with all other references. */
6741 specs[count] = tmpl;
6742 specs[count++].specific = 0;
6743 }
6744 else
6745 {
6746 UNHANDLED;
6747 }
6748 break;
6749
6750 case IA64_RS_PKR: /* 16 or more registers */
6751 if (note == 3 || note == 4)
542d6675
KH		 6752 {
6753 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6754 {
6755 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6756 if (regno >= 0 && regno < NELEMS (gr_values)
6757 && KNOWN (regno))
6758 {
6759 if (note == 3)
6760 {
6761 specs[count] = tmpl;
6762 specs[count++].index = gr_values[regno].value & 0xFF;
6763 }
6764 else
6765 for (i = 0; i < NELEMS (gr_values); i++)
6766 {
6767 /* Uses all registers *except* the one in R3. */
6768 if (i != (gr_values[regno].value & 0xFF))
6769 {
6770 specs[count] = tmpl;
6771 specs[count++].index = i;
6772 }
6773 }
6774 }
6775 else
6776 {
6777 specs[count] = tmpl;
6778 specs[count++].specific = 0;
6779 }
6780 }
6781 }
6782 else if (note == 0)
6783 {
6784 /* probe et al. */
6785 specs[count] = tmpl;
6786 specs[count++].specific = 0;
6787 }
6788 break;
6789
6790 case IA64_RS_PMC: /* four or more registers */
6791 if (note == 3)
6792 {
6793 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
6794 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
6795
6796 {
6797 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
6798 ? 1 : !rsrc_write);
6799 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
6800 if (regno >= 0 && regno < NELEMS (gr_values)
6801 && KNOWN (regno))
6802 {
6803 specs[count] = tmpl;
6804 specs[count++].index = gr_values[regno].value & 0xFF;
6805 }
6806 else
6807 {
6808 specs[count] = tmpl;
6809 specs[count++].specific = 0;
6810 }
6811 }
6812 }
6813 else
6814 {
6815 UNHANDLED;
6816 }
800eeca4
JW		 6817 break;
6818
6819 case IA64_RS_PMD: /* four or more registers */
6820 if (note == 3)
542d6675
KH		 6821 {
6822 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
6823 {
6824 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6825 if (regno >= 0 && regno < NELEMS (gr_values)
6826 && KNOWN (regno))
6827 {
6828 specs[count] = tmpl;
6829 specs[count++].index = gr_values[regno].value & 0xFF;
6830 }
6831 else
6832 {
6833 specs[count] = tmpl;
6834 specs[count++].specific = 0;
6835 }
6836 }
6837 }
800eeca4 6838 else
542d6675
KH		 6839 {
6840 UNHANDLED;
6841 }
800eeca4
JW		 6842 break;
6843
6844 case IA64_RS_RR: /* eight registers */
6845 if (note == 6)
542d6675
KH		 6846 {
6847 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
6848 {
6849 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6850 if (regno >= 0 && regno < NELEMS (gr_values)
6851 && KNOWN (regno))
6852 {
6853 specs[count] = tmpl;
6854 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
6855 }
6856 else
6857 {
6858 specs[count] = tmpl;
6859 specs[count++].specific = 0;
6860 }
6861 }
6862 }
800eeca4 6863 else if (note == 0 && !rsrc_write)
542d6675
KH		 6864 {
6865 specs[count] = tmpl;
6866 specs[count++].specific = 0;
6867 }
197865e8 6868 else
542d6675
KH		 6869 {
6870 UNHANDLED;
6871 }
800eeca4
JW		 6872 break;
6873
6874 case IA64_RS_CR_IRR:
197865e8 6875 if (note == 0)
542d6675
KH		 6876 {
6877 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6878 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
6879 if (rsrc_write
6880 && idesc->operands[1] == IA64_OPND_CR3
6881 && regno == CR_IVR)
6882 {
6883 for (i = 0; i < 4; i++)
6884 {
6885 specs[count] = tmpl;
6886 specs[count++].index = CR_IRR0 + i;
6887 }
6888 }
6889 }
800eeca4 6890 else if (note == 1)
542d6675
KH		 6891 {
6892 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6893 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6894 && regno >= CR_IRR0
6895 && regno <= CR_IRR3)
6896 {
6897 specs[count] = tmpl;
6898 specs[count++].index = regno;
6899 }
6900 }
800eeca4 6901 else
542d6675
KH		 6902 {
6903 UNHANDLED;
6904 }
800eeca4
JW		 6905 break;
6906
6907 case IA64_RS_CR_LRR:
6908 if (note != 1)
542d6675
KH		 6909 {
6910 UNHANDLED;
6911 }
197865e8 6912 else
542d6675
KH		 6913 {
6914 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6915 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6916 && (regno == CR_LRR0 || regno == CR_LRR1))
6917 {
6918 specs[count] = tmpl;
6919 specs[count++].index = regno;
6920 }
6921 }
800eeca4
JW		 6922 break;
6923
6924 case IA64_RS_CR:
6925 if (note == 1)
542d6675
KH		 6926 {
6927 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
6928 {
6929 specs[count] = tmpl;
6930 specs[count++].index =
6931 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6932 }
6933 }
800eeca4 6934 else
542d6675
KH		 6935 {
6936 UNHANDLED;
6937 }
800eeca4
JW		 6938 break;
6939
6940 case IA64_RS_FR:
6941 case IA64_RS_FRb:
6942 if (note != 1)
542d6675
KH		 6943 {
6944 UNHANDLED;
6945 }
800eeca4 6946 else if (rsrc_write)
542d6675
KH		 6947 {
6948 if (dep->specifier == IA64_RS_FRb
6949 && idesc->operands[0] == IA64_OPND_F1)
6950 {
6951 specs[count] = tmpl;
6952 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
6953 }
6954 }
800eeca4 6955 else
542d6675
KH		 6956 {
6957 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
6958 {
6959 if (idesc->operands[i] == IA64_OPND_F2
6960 || idesc->operands[i] == IA64_OPND_F3
6961 || idesc->operands[i] == IA64_OPND_F4)
6962 {
6963 specs[count] = tmpl;
6964 specs[count++].index =
6965 CURR_SLOT.opnd[i].X_add_number - REG_FR;
6966 }
6967 }
6968 }
800eeca4
JW		 6969 break;
6970
6971 case IA64_RS_GR:
6972 if (note == 13)
542d6675
KH		 6973 {
6974 /* This reference applies only to the GR whose value is loaded with
6975 data returned from memory. */
6976 specs[count] = tmpl;
6977 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
6978 }
800eeca4 6979 else if (note == 1)
542d6675
KH		 6980 {
6981 if (rsrc_write)
6982 {
6983 for (i = 0; i < idesc->num_outputs; i++)
50b81f19
JW		 6984 if (idesc->operands[i] == IA64_OPND_R1
6985 || idesc->operands[i] == IA64_OPND_R2
6986 || idesc->operands[i] == IA64_OPND_R3)
6987 {
6988 specs[count] = tmpl;
197865e8 6989 specs[count++].index =
50b81f19
JW		 6990 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6991 }
6992 if (idesc->flags & IA64_OPCODE_POSTINC)
6993 for (i = 0; i < NELEMS (idesc->operands); i++)
6994 if (idesc->operands[i] == IA64_OPND_MR3)
6995 {
6996 specs[count] = tmpl;
6997 specs[count++].index =
6998 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6999 }
542d6675
KH		 7000 }
7001 else
7002 {
7003 /* Look for anything that reads a GR. */
7004 for (i = 0; i < NELEMS (idesc->operands); i++)
7005 {
7006 if (idesc->operands[i] == IA64_OPND_MR3
7007 || idesc->operands[i] == IA64_OPND_CPUID_R3
7008 || idesc->operands[i] == IA64_OPND_DBR_R3
7009 || idesc->operands[i] == IA64_OPND_IBR_R3
800eeca4 7010 || idesc->operands[i] == IA64_OPND_MSR_R3
542d6675
KH		 7011 || idesc->operands[i] == IA64_OPND_PKR_R3
7012 || idesc->operands[i] == IA64_OPND_PMC_R3
7013 || idesc->operands[i] == IA64_OPND_PMD_R3
7014 || idesc->operands[i] == IA64_OPND_RR_R3
7015 || ((i >= idesc->num_outputs)
7016 && (idesc->operands[i] == IA64_OPND_R1
7017 || idesc->operands[i] == IA64_OPND_R2
7018 || idesc->operands[i] == IA64_OPND_R3
50b81f19
JW		 7019 /* addl source register. */
7020 || idesc->operands[i] == IA64_OPND_R3_2)))
542d6675
KH		 7021 {
7022 specs[count] = tmpl;
7023 specs[count++].index =
7024 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7025 }
7026 }
7027 }
7028 }
197865e8 7029 else
542d6675
KH		 7030 {
7031 UNHANDLED;
7032 }
800eeca4
JW		 7033 break;
7034
139368c9
JW		 7035 /* This is the same as IA64_RS_PRr, except that the register range is
7036 from 1 - 15, and there are no rotating register reads/writes here. */
800eeca4
JW		 7037 case IA64_RS_PR:
7038 if (note == 0)
542d6675 7039 {
139368c9 7040 for (i = 1; i < 16; i++)
542d6675 7041 {
139368c9
JW		 7042 specs[count] = tmpl;
7043 specs[count++].index = i;
7044 }
7045 }
7046 else if (note == 7)
7047 {
7048 valueT mask = 0;
7049 /* Mark only those registers indicated by the mask. */
7050 if (rsrc_write)
7051 {
7052 mask = CURR_SLOT.opnd[2].X_add_number;
7053 for (i = 1; i < 16; i++)
7054 if (mask & ((valueT) 1 << i))
7055 {
7056 specs[count] = tmpl;
7057 specs[count++].index = i;
7058 }
7059 }
7060 else
7061 {
7062 UNHANDLED;
7063 }
7064 }
7065 else if (note == 11) /* note 11 implies note 1 as well */
7066 {
7067 if (rsrc_write)
7068 {
7069 for (i = 0; i < idesc->num_outputs; i++)
7070 {
7071 if (idesc->operands[i] == IA64_OPND_P1
7072 || idesc->operands[i] == IA64_OPND_P2)
7073 {
7074 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7075 if (regno >= 1 && regno < 16)
7076 {
7077 specs[count] = tmpl;
7078 specs[count++].index = regno;
7079 }
7080 }
7081 }
7082 }
7083 else
7084 {
7085 UNHANDLED;
7086 }
7087 }
7088 else if (note == 12)
7089 {
7090 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7091 {
7092 specs[count] = tmpl;
7093 specs[count++].index = CURR_SLOT.qp_regno;
7094 }
7095 }
7096 else if (note == 1)
7097 {
7098 if (rsrc_write)
7099 {
7100 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7101 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7102 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7103 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7104
7105 if ((idesc->operands[0] == IA64_OPND_P1
7106 || idesc->operands[0] == IA64_OPND_P2)
7107 && p1 >= 1 && p1 < 16)
542d6675
KH		 7108 {
7109 specs[count] = tmpl;
139368c9
JW		 7110 specs[count].cmp_type =
7111 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7112 specs[count++].index = p1;
7113 }
7114 if ((idesc->operands[1] == IA64_OPND_P1
7115 || idesc->operands[1] == IA64_OPND_P2)
7116 && p2 >= 1 && p2 < 16)
7117 {
7118 specs[count] = tmpl;
7119 specs[count].cmp_type =
7120 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7121 specs[count++].index = p2;
542d6675
KH		 7122 }
7123 }
7124 else
7125 {
139368c9 7126 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
542d6675
KH		 7127 {
7128 specs[count] = tmpl;
139368c9
JW		 7129 specs[count++].index = CURR_SLOT.qp_regno;
7130 }
7131 if (idesc->operands[1] == IA64_OPND_PR)
7132 {
7133 for (i = 1; i < 16; i++)
7134 {
7135 specs[count] = tmpl;
7136 specs[count++].index = i;
7137 }
542d6675
KH		 7138 }
7139 }
7140 }
139368c9
JW		 7141 else
7142 {
7143 UNHANDLED;
7144 }
7145 break;
7146
7147 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7148 simplified cases of this. */
7149 case IA64_RS_PRr:
7150 if (note == 0)
7151 {
7152 for (i = 16; i < 63; i++)
7153 {
7154 specs[count] = tmpl;
7155 specs[count++].index = i;
7156 }
7157 }
800eeca4 7158 else if (note == 7)
542d6675
KH		 7159 {
7160 valueT mask = 0;
7161 /* Mark only those registers indicated by the mask. */
7162 if (rsrc_write
7163 && idesc->operands[0] == IA64_OPND_PR)
7164 {
7165 mask = CURR_SLOT.opnd[2].X_add_number;
139368c9
JW		 7166 if (mask & ((valueT) 1<<16))
7167 for (i = 16; i < 63; i++)
7168 {
7169 specs[count] = tmpl;
7170 specs[count++].index = i;
7171 }
542d6675
KH		 7172 }
7173 else if (rsrc_write
7174 && idesc->operands[0] == IA64_OPND_PR_ROT)
7175 {
7176 for (i = 16; i < 63; i++)
7177 {
7178 specs[count] = tmpl;
7179 specs[count++].index = i;
7180 }
7181 }
7182 else
7183 {
7184 UNHANDLED;
7185 }
7186 }
800eeca4 7187 else if (note == 11) /* note 11 implies note 1 as well */
542d6675
KH		 7188 {
7189 if (rsrc_write)
7190 {
7191 for (i = 0; i < idesc->num_outputs; i++)
7192 {
7193 if (idesc->operands[i] == IA64_OPND_P1
7194 || idesc->operands[i] == IA64_OPND_P2)
7195 {
7196 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
139368c9 7197 if (regno >= 16 && regno < 63)
542d6675
KH		 7198 {
7199 specs[count] = tmpl;
7200 specs[count++].index = regno;
7201 }
7202 }
7203 }
7204 }
7205 else
7206 {
7207 UNHANDLED;
7208 }
7209 }
800eeca4 7210 else if (note == 12)
542d6675 7211 {
139368c9 7212 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH		 7213 {
7214 specs[count] = tmpl;
7215 specs[count++].index = CURR_SLOT.qp_regno;
7216 }
7217 }
800eeca4 7218 else if (note == 1)
542d6675
KH		 7219 {
7220 if (rsrc_write)
7221 {
7222 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7223 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7484b8e6
TW		 7224 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7225 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7226
542d6675
KH		 7227 if ((idesc->operands[0] == IA64_OPND_P1
7228 || idesc->operands[0] == IA64_OPND_P2)
139368c9 7229 && p1 >= 16 && p1 < 63)
542d6675
KH		 7230 {
7231 specs[count] = tmpl;
4a4f25cf 7232 specs[count].cmp_type =
7484b8e6 7233 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
542d6675
KH		 7234 specs[count++].index = p1;
7235 }
7236 if ((idesc->operands[1] == IA64_OPND_P1
7237 || idesc->operands[1] == IA64_OPND_P2)
139368c9 7238 && p2 >= 16 && p2 < 63)
542d6675
KH		 7239 {
7240 specs[count] = tmpl;
4a4f25cf 7241 specs[count].cmp_type =
7484b8e6 7242 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
542d6675
KH		 7243 specs[count++].index = p2;
7244 }
7245 }
7246 else
7247 {
139368c9 7248 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH		 7249 {
7250 specs[count] = tmpl;
7251 specs[count++].index = CURR_SLOT.qp_regno;
7252 }
7253 if (idesc->operands[1] == IA64_OPND_PR)
7254 {
139368c9 7255 for (i = 16; i < 63; i++)
542d6675
KH		 7256 {
7257 specs[count] = tmpl;
7258 specs[count++].index = i;
7259 }
7260 }
7261 }
7262 }
197865e8 7263 else
542d6675
KH		 7264 {
7265 UNHANDLED;
7266 }
800eeca4
JW		 7267 break;
7268
7269 case IA64_RS_PSR:
197865e8 7270 /* Verify that the instruction is using the PSR bit indicated in
542d6675 7271 dep->regindex. */
800eeca4 7272 if (note == 0)
542d6675
KH		 7273 {
7274 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7275 {
7276 if (dep->regindex < 6)
7277 {
7278 specs[count++] = tmpl;
7279 }
7280 }
7281 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7282 {
7283 if (dep->regindex < 32
7284 || dep->regindex == 35
7285 || dep->regindex == 36
7286 || (!rsrc_write && dep->regindex == PSR_CPL))
7287 {
7288 specs[count++] = tmpl;
7289 }
7290 }
7291 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7292 {
7293 if (dep->regindex < 32
7294 || dep->regindex == 35
7295 || dep->regindex == 36
7296 || (rsrc_write && dep->regindex == PSR_CPL))
7297 {
7298 specs[count++] = tmpl;
7299 }
7300 }
7301 else
7302 {
7303 /* Several PSR bits have very specific dependencies. */
7304 switch (dep->regindex)
7305 {
7306 default:
7307 specs[count++] = tmpl;
7308 break;
7309 case PSR_IC:
7310 if (rsrc_write)
7311 {
7312 specs[count++] = tmpl;
7313 }
7314 else
7315 {
7316 /* Only certain CR accesses use PSR.ic */
7317 if (idesc->operands[0] == IA64_OPND_CR3
7318 || idesc->operands[1] == IA64_OPND_CR3)
7319 {
7320 int index =
7321 ((idesc->operands[0] == IA64_OPND_CR3)
7322 ? 0 : 1);
7323 int regno =
7324 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7325
7326 switch (regno)
7327 {
7328 default:
7329 break;
7330 case CR_ITIR:
7331 case CR_IFS:
7332 case CR_IIM:
7333 case CR_IIP:
7334 case CR_IPSR:
7335 case CR_ISR:
7336 case CR_IFA:
7337 case CR_IHA:
7338 case CR_IIPA:
7339 specs[count++] = tmpl;
7340 break;
7341 }
7342 }
7343 }
7344 break;
7345 case PSR_CPL:
7346 if (rsrc_write)
7347 {
7348 specs[count++] = tmpl;
7349 }
7350 else
7351 {
7352 /* Only some AR accesses use cpl */
7353 if (idesc->operands[0] == IA64_OPND_AR3
7354 || idesc->operands[1] == IA64_OPND_AR3)
7355 {
7356 int index =
7357 ((idesc->operands[0] == IA64_OPND_AR3)
7358 ? 0 : 1);
7359 int regno =
7360 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7361
7362 if (regno == AR_ITC
7363 || (index == 0
7364 && (regno == AR_ITC
7365 || regno == AR_RSC
7366 || (regno >= AR_K0
7367 && regno <= AR_K7))))
7368 {
7369 specs[count++] = tmpl;
7370 }
7371 }
7372 else
7373 {
7374 specs[count++] = tmpl;
7375 }
7376 break;
7377 }
7378 }
7379 }
7380 }
800eeca4 7381 else if (note == 7)
542d6675
KH		 7382 {
7383 valueT mask = 0;
7384 if (idesc->operands[0] == IA64_OPND_IMMU24)
7385 {
7386 mask = CURR_SLOT.opnd[0].X_add_number;
7387 }
7388 else
7389 {
7390 UNHANDLED;
7391 }
7392 if (mask & ((valueT) 1 << dep->regindex))
7393 {
7394 specs[count++] = tmpl;
7395 }
7396 }
800eeca4 7397 else if (note == 8)
542d6675
KH		 7398 {
7399 int min = dep->regindex == PSR_DFL ? 2 : 32;
7400 int max = dep->regindex == PSR_DFL ? 31 : 127;
7401 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7402 for (i = 0; i < NELEMS (idesc->operands); i++)
7403 {
7404 if (idesc->operands[i] == IA64_OPND_F1
7405 || idesc->operands[i] == IA64_OPND_F2
7406 || idesc->operands[i] == IA64_OPND_F3
7407 || idesc->operands[i] == IA64_OPND_F4)
7408 {
7409 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7410 if (reg >= min && reg <= max)
7411 {
7412 specs[count++] = tmpl;
7413 }
7414 }
7415 }
7416 }
800eeca4 7417 else if (note == 9)
542d6675
KH		 7418 {
7419 int min = dep->regindex == PSR_MFL ? 2 : 32;
7420 int max = dep->regindex == PSR_MFL ? 31 : 127;
7421 /* mfh is read on writes to FR32-127; mfl is read on writes to
7422 FR2-31 */
7423 for (i = 0; i < idesc->num_outputs; i++)
7424 {
7425 if (idesc->operands[i] == IA64_OPND_F1)
7426 {
7427 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7428 if (reg >= min && reg <= max)
7429 {
7430 specs[count++] = tmpl;
7431 }
7432 }
7433 }
7434 }
800eeca4 7435 else if (note == 10)
542d6675
KH		 7436 {
7437 for (i = 0; i < NELEMS (idesc->operands); i++)
7438 {
7439 if (idesc->operands[i] == IA64_OPND_R1
7440 || idesc->operands[i] == IA64_OPND_R2
7441 || idesc->operands[i] == IA64_OPND_R3)
7442 {
7443 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7444 if (regno >= 16 && regno <= 31)
7445 {
7446 specs[count++] = tmpl;
7447 }
7448 }
7449 }
7450 }
800eeca4 7451 else
542d6675
KH		 7452 {
7453 UNHANDLED;
7454 }
800eeca4
JW		 7455 break;
7456
7457 case IA64_RS_AR_FPSR:
7458 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
542d6675
KH		 7459 {
7460 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7461 if (regno == AR_FPSR)
7462 {
7463 specs[count++] = tmpl;
7464 }
7465 }
800eeca4 7466 else
542d6675
KH		 7467 {
7468 specs[count++] = tmpl;
7469 }
800eeca4
JW		 7470 break;
7471
197865e8 7472 case IA64_RS_ARX:
800eeca4
JW		 7473 /* Handle all AR[REG] resources */
7474 if (note == 0 || note == 1)
542d6675
KH		 7475 {
7476 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7477 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7478 && regno == dep->regindex)
7479 {
7480 specs[count++] = tmpl;
7481 }
7482 /* other AR[REG] resources may be affected by AR accesses */
7483 else if (idesc->operands[0] == IA64_OPND_AR3)
7484 {
7485 /* AR[] writes */
7486 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7487 switch (dep->regindex)
7488 {
7489 default:
7490 break;
7491 case AR_BSP:
7492 case AR_RNAT:
7493 if (regno == AR_BSPSTORE)
7494 {
7495 specs[count++] = tmpl;
7496 }
7497 case AR_RSC:
7498 if (!rsrc_write &&
7499 (regno == AR_BSPSTORE
7500 || regno == AR_RNAT))
7501 {
7502 specs[count++] = tmpl;
7503 }
7504 break;
7505 }
7506 }
7507 else if (idesc->operands[1] == IA64_OPND_AR3)
7508 {
7509 /* AR[] reads */
7510 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7511 switch (dep->regindex)
7512 {
7513 default:
7514 break;
7515 case AR_RSC:
7516 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7517 {
7518 specs[count++] = tmpl;
7519 }
7520 break;
7521 }
7522 }
7523 else
7524 {
7525 specs[count++] = tmpl;
7526 }
7527 }
800eeca4 7528 else
542d6675
KH		 7529 {
7530 UNHANDLED;
7531 }
800eeca4
JW		 7532 break;
7533
7534 case IA64_RS_CRX:
7535 /* Handle all CR[REG] resources */
7536 if (note == 0 || note == 1)
542d6675
KH		 7537 {
7538 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7539 {
7540 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7541 if (regno == dep->regindex)
7542 {
7543 specs[count++] = tmpl;
7544 }
7545 else if (!rsrc_write)
7546 {
7547 /* Reads from CR[IVR] affect other resources. */
7548 if (regno == CR_IVR)
7549 {
7550 if ((dep->regindex >= CR_IRR0
7551 && dep->regindex <= CR_IRR3)
7552 || dep->regindex == CR_TPR)
7553 {
7554 specs[count++] = tmpl;
7555 }
7556 }
7557 }
7558 }
7559 else
7560 {
7561 specs[count++] = tmpl;
7562 }
7563 }
800eeca4 7564 else
542d6675
KH		 7565 {
7566 UNHANDLED;
7567 }
800eeca4
JW		 7568 break;
7569
7570 case IA64_RS_INSERVICE:
7571 /* look for write of EOI (67) or read of IVR (65) */
7572 if ((idesc->operands[0] == IA64_OPND_CR3
542d6675
KH		 7573 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7574 || (idesc->operands[1] == IA64_OPND_CR3
7575 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7576 {
7577 specs[count++] = tmpl;
7578 }
800eeca4
JW		 7579 break;
7580
7581 case IA64_RS_GR0:
7582 if (note == 1)
542d6675
KH		 7583 {
7584 specs[count++] = tmpl;
7585 }
800eeca4 7586 else
542d6675
KH		 7587 {
7588 UNHANDLED;
7589 }
800eeca4
JW		 7590 break;
7591
7592 case IA64_RS_CFM:
7593 if (note != 2)
542d6675
KH		 7594 {
7595 specs[count++] = tmpl;
7596 }
800eeca4 7597 else
542d6675
KH		 7598 {
7599 /* Check if any of the registers accessed are in the rotating region.
7600 mov to/from pr accesses CFM only when qp_regno is in the rotating
7601 region */
7602 for (i = 0; i < NELEMS (idesc->operands); i++)
7603 {
7604 if (idesc->operands[i] == IA64_OPND_R1
7605 || idesc->operands[i] == IA64_OPND_R2
7606 || idesc->operands[i] == IA64_OPND_R3)
7607 {
7608 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7609 /* Assumes that md.rot.num_regs is always valid */
7610 if (md.rot.num_regs > 0
7611 && num > 31
7612 && num < 31 + md.rot.num_regs)
7613 {
7614 specs[count] = tmpl;
7615 specs[count++].specific = 0;
7616 }
7617 }
7618 else if (idesc->operands[i] == IA64_OPND_F1
7619 || idesc->operands[i] == IA64_OPND_F2
7620 || idesc->operands[i] == IA64_OPND_F3
7621 || idesc->operands[i] == IA64_OPND_F4)
7622 {
7623 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7624 if (num > 31)
7625 {
7626 specs[count] = tmpl;
7627 specs[count++].specific = 0;
7628 }
7629 }
7630 else if (idesc->operands[i] == IA64_OPND_P1
7631 || idesc->operands[i] == IA64_OPND_P2)
7632 {
7633 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7634 if (num > 15)
7635 {
7636 specs[count] = tmpl;
7637 specs[count++].specific = 0;
7638 }
7639 }
7640 }
7641 if (CURR_SLOT.qp_regno > 15)
7642 {
7643 specs[count] = tmpl;
7644 specs[count++].specific = 0;
7645 }
7646 }
800eeca4
JW		 7647 break;
7648
139368c9
JW		 7649 /* This is the same as IA64_RS_PRr, except simplified to account for
7650 the fact that there is only one register. */
800eeca4
JW		 7651 case IA64_RS_PR63:
7652 if (note == 0)
542d6675
KH		 7653 {
7654 specs[count++] = tmpl;
7655 }
139368c9
JW		 7656 else if (note == 7)
7657 {
7658 valueT mask = 0;
7659 if (idesc->operands[2] == IA64_OPND_IMM17)
7660 mask = CURR_SLOT.opnd[2].X_add_number;
7661 if (mask & ((valueT) 1 << 63))
7662 specs[count++] = tmpl;
7663 }
800eeca4 7664 else if (note == 11)
542d6675
KH		 7665 {
7666 if ((idesc->operands[0] == IA64_OPND_P1
7667 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7668 || (idesc->operands[1] == IA64_OPND_P2
7669 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7670 {
7671 specs[count++] = tmpl;
7672 }
7673 }
800eeca4 7674 else if (note == 12)
542d6675
KH		 7675 {
7676 if (CURR_SLOT.qp_regno == 63)
7677 {
7678 specs[count++] = tmpl;
7679 }
7680 }
800eeca4 7681 else if (note == 1)
542d6675
KH		 7682 {
7683 if (rsrc_write)
7684 {
7484b8e6
TW		 7685 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7686 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7687 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7688 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7689
4a4f25cf 7690 if (p1 == 63
7484b8e6
TW		 7691 && (idesc->operands[0] == IA64_OPND_P1
7692 || idesc->operands[0] == IA64_OPND_P2))
7693 {
7694 specs[count] = tmpl;
4a4f25cf 7695 specs[count++].cmp_type =
7484b8e6
TW		 7696 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7697 }
7698 if (p2 == 63
7699 && (idesc->operands[1] == IA64_OPND_P1
7700 || idesc->operands[1] == IA64_OPND_P2))
7701 {
7702 specs[count] = tmpl;
4a4f25cf 7703 specs[count++].cmp_type =
7484b8e6
TW		 7704 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7705 }
542d6675
KH		 7706 }
7707 else
7708 {
7709 if (CURR_SLOT.qp_regno == 63)
7710 {
7711 specs[count++] = tmpl;
7712 }
7713 }
7714 }
800eeca4 7715 else
542d6675
KH		 7716 {
7717 UNHANDLED;
7718 }
800eeca4
JW		 7719 break;
7720
7721 case IA64_RS_RSE:
7722 /* FIXME we can identify some individual RSE written resources, but RSE
542d6675
KH		 7723 read resources have not yet been completely identified, so for now
7724 treat RSE as a single resource */
800eeca4 7725 if (strncmp (idesc->name, "mov", 3) == 0)
542d6675
KH		 7726 {
7727 if (rsrc_write)
7728 {
7729 if (idesc->operands[0] == IA64_OPND_AR3
7730 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7731 {
7732 specs[count] = tmpl;
7733 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7734 }
7735 }
7736 else
7737 {
7738 if (idesc->operands[0] == IA64_OPND_AR3)
7739 {
7740 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7741 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7742 {
7743 specs[count++] = tmpl;
7744 }
7745 }
7746 else if (idesc->operands[1] == IA64_OPND_AR3)
7747 {
7748 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7749 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7750 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7751 {
7752 specs[count++] = tmpl;
7753 }
7754 }
7755 }
7756 }
197865e8 7757 else
542d6675
KH		 7758 {
7759 specs[count++] = tmpl;
7760 }
800eeca4
JW		 7761 break;
7762
7763 case IA64_RS_ANY:
7764 /* FIXME -- do any of these need to be non-specific? */
7765 specs[count++] = tmpl;
7766 break;
7767
7768 default:
7769 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7770 break;
7771 }
7772
7773 return count;
7774}
7775
7776/* Clear branch flags on marked resources. This breaks the link between the
542d6675
KH		 7777 QP of the marking instruction and a subsequent branch on the same QP. */
7778
800eeca4
JW		 7779static void
7780clear_qp_branch_flag (mask)
542d6675 7781 valueT mask;
800eeca4
JW		 7782{
7783 int i;
542d6675 7784 for (i = 0; i < regdepslen; i++)
800eeca4 7785 {
197865e8 7786 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
800eeca4 7787 if ((bit & mask) != 0)
542d6675
KH		 7788 {
7789 regdeps[i].link_to_qp_branch = 0;
7790 }
800eeca4
JW		 7791 }
7792}
7793
197865e8 7794/* Remove any mutexes which contain any of the PRs indicated in the mask.
800eeca4 7795
542d6675
KH		 7796 Any changes to a PR clears the mutex relations which include that PR. */
7797
800eeca4
JW		 7798static void
7799clear_qp_mutex (mask)
542d6675 7800 valueT mask;
800eeca4
JW		 7801{
7802 int i;
7803
7804 i = 0;
7805 while (i < qp_mutexeslen)
7806 {
7807 if ((qp_mutexes[i].prmask & mask) != 0)
542d6675
KH		 7808 {
7809 if (md.debug_dv)
7810 {
7811 fprintf (stderr, " Clearing mutex relation");
7812 print_prmask (qp_mutexes[i].prmask);
7813 fprintf (stderr, "\n");
7814 }
7815 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
7816 }
800eeca4 7817 else
542d6675 7818 ++i;
800eeca4
JW		 7819 }
7820}
7821
7822/* Clear implies relations which contain PRs in the given masks.
7823 P1_MASK indicates the source of the implies relation, while P2_MASK
542d6675
KH		 7824 indicates the implied PR. */
7825
800eeca4
JW		 7826static void
7827clear_qp_implies (p1_mask, p2_mask)
542d6675
KH		 7828 valueT p1_mask;
7829 valueT p2_mask;
800eeca4
JW		 7830{
7831 int i;
7832
7833 i = 0;
7834 while (i < qp_implieslen)
7835 {
197865e8 7836 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
542d6675
KH		 7837 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
7838 {
7839 if (md.debug_dv)
7840 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
7841 qp_implies[i].p1, qp_implies[i].p2);
7842 qp_implies[i] = qp_implies[--qp_implieslen];
7843 }
197865e8 7844 else
542d6675 7845 ++i;
800eeca4
JW		 7846 }
7847}
7848
542d6675
KH		 7849/* Add the PRs specified to the list of implied relations. */
7850
800eeca4
JW		 7851static void
7852add_qp_imply (p1, p2)
542d6675 7853 int p1, p2;
800eeca4
JW		 7854{
7855 valueT mask;
7856 valueT bit;
7857 int i;
7858
542d6675 7859 /* p0 is not meaningful here. */
800eeca4
JW		 7860 if (p1 == 0 || p2 == 0)
7861 abort ();
7862
7863 if (p1 == p2)
7864 return;
7865
542d6675
KH		 7866 /* If it exists already, ignore it. */
7867 for (i = 0; i < qp_implieslen; i++)
800eeca4 7868 {
197865e8 7869 if (qp_implies[i].p1 == p1
542d6675
KH		 7870 && qp_implies[i].p2 == p2
7871 && qp_implies[i].path == md.path
7872 && !qp_implies[i].p2_branched)
7873 return;
800eeca4
JW		 7874 }
7875
7876 if (qp_implieslen == qp_impliestotlen)
7877 {
7878 qp_impliestotlen += 20;
7879 qp_implies = (struct qp_imply *)
542d6675
KH		 7880 xrealloc ((void *) qp_implies,
7881 qp_impliestotlen * sizeof (struct qp_imply));
800eeca4
JW		 7882 }
7883 if (md.debug_dv)
7884 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
7885 qp_implies[qp_implieslen].p1 = p1;
7886 qp_implies[qp_implieslen].p2 = p2;
7887 qp_implies[qp_implieslen].path = md.path;
7888 qp_implies[qp_implieslen++].p2_branched = 0;
7889
7890 /* Add in the implied transitive relations; for everything that p2 implies,
7891 make p1 imply that, too; for everything that implies p1, make it imply p2
197865e8 7892 as well. */
542d6675 7893 for (i = 0; i < qp_implieslen; i++)
800eeca4
JW		 7894 {
7895 if (qp_implies[i].p1 == p2)
542d6675 7896 add_qp_imply (p1, qp_implies[i].p2);
800eeca4 7897 if (qp_implies[i].p2 == p1)
542d6675 7898 add_qp_imply (qp_implies[i].p1, p2);
800eeca4
JW		 7899 }
7900 /* Add in mutex relations implied by this implies relation; for each mutex
197865e8
KH		 7901 relation containing p2, duplicate it and replace p2 with p1. */
7902 bit = (valueT) 1 << p1;
7903 mask = (valueT) 1 << p2;
542d6675 7904 for (i = 0; i < qp_mutexeslen; i++)
800eeca4
JW		 7905 {
7906 if (qp_mutexes[i].prmask & mask)
542d6675 7907 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
800eeca4
JW		 7908 }
7909}
7910
800eeca4
JW		 7911/* Add the PRs specified in the mask to the mutex list; this means that only
7912 one of the PRs can be true at any time. PR0 should never be included in
7913 the mask. */
542d6675 7914
800eeca4
JW		 7915static void
7916add_qp_mutex (mask)
542d6675 7917 valueT mask;
800eeca4
JW		 7918{
7919 if (mask & 0x1)
7920 abort ();
7921
7922 if (qp_mutexeslen == qp_mutexestotlen)
7923 {
7924 qp_mutexestotlen += 20;
7925 qp_mutexes = (struct qpmutex *)
542d6675
KH		 7926 xrealloc ((void *) qp_mutexes,
7927 qp_mutexestotlen * sizeof (struct qpmutex));
800eeca4
JW		 7928 }
7929 if (md.debug_dv)
7930 {
7931 fprintf (stderr, " Registering mutex on");
7932 print_prmask (mask);
7933 fprintf (stderr, "\n");
7934 }
7935 qp_mutexes[qp_mutexeslen].path = md.path;
7936 qp_mutexes[qp_mutexeslen++].prmask = mask;
7937}
7938
7939static void
7940clear_register_values ()
7941{
7942 int i;
7943 if (md.debug_dv)
7944 fprintf (stderr, " Clearing register values\n");
542d6675 7945 for (i = 1; i < NELEMS (gr_values); i++)
800eeca4
JW		 7946 gr_values[i].known = 0;
7947}
7948
7949/* Keep track of register values/changes which affect DV tracking.
7950
7951 optimization note: should add a flag to classes of insns where otherwise we
542d6675 7952 have to examine a group of strings to identify them. */
800eeca4 7953
800eeca4
JW		 7954static void
7955note_register_values (idesc)
542d6675 7956 struct ia64_opcode *idesc;
800eeca4
JW		 7957{
7958 valueT qp_changemask = 0;
7959 int i;
7960
542d6675
KH		 7961 /* Invalidate values for registers being written to. */
7962 for (i = 0; i < idesc->num_outputs; i++)
800eeca4 7963 {
197865e8 7964 if (idesc->operands[i] == IA64_OPND_R1
542d6675
KH		 7965 || idesc->operands[i] == IA64_OPND_R2
7966 || idesc->operands[i] == IA64_OPND_R3)
7967 {
7968 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7969 if (regno > 0 && regno < NELEMS (gr_values))
7970 gr_values[regno].known = 0;
7971 }
50b81f19
JW		 7972 else if (idesc->operands[i] == IA64_OPND_R3_2)
7973 {
7974 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7975 if (regno > 0 && regno < 4)
7976 gr_values[regno].known = 0;
7977 }
197865e8 7978 else if (idesc->operands[i] == IA64_OPND_P1
542d6675
KH		 7979 || idesc->operands[i] == IA64_OPND_P2)
7980 {
7981 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7982 qp_changemask |= (valueT) 1 << regno;
7983 }
800eeca4 7984 else if (idesc->operands[i] == IA64_OPND_PR)
542d6675
KH		 7985 {
7986 if (idesc->operands[2] & (valueT) 0x10000)
7987 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
7988 else
7989 qp_changemask = idesc->operands[2];
7990 break;
7991 }
800eeca4 7992 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
542d6675
KH		 7993 {
7994 if (idesc->operands[1] & ((valueT) 1 << 43))
7995 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
7996 else
7997 qp_changemask = idesc->operands[1];
7998 qp_changemask &= ~(valueT) 0xFFFF;
7999 break;
8000 }
8001 }
8002
8003 /* Always clear qp branch flags on any PR change. */
8004 /* FIXME there may be exceptions for certain compares. */
800eeca4
JW		 8005 clear_qp_branch_flag (qp_changemask);
8006
542d6675 8007 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
800eeca4
JW		 8008 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8009 {
197865e8 8010 qp_changemask |= ~(valueT) 0xFFFF;
800eeca4 8011 if (strcmp (idesc->name, "clrrrb.pr") != 0)
542d6675
KH		 8012 {
8013 for (i = 32; i < 32 + md.rot.num_regs; i++)
8014 gr_values[i].known = 0;
8015 }
800eeca4
JW		 8016 clear_qp_mutex (qp_changemask);
8017 clear_qp_implies (qp_changemask, qp_changemask);
8018 }
542d6675
KH		 8019 /* After a call, all register values are undefined, except those marked
8020 as "safe". */
800eeca4 8021 else if (strncmp (idesc->name, "br.call", 6) == 0
542d6675 8022 || strncmp (idesc->name, "brl.call", 7) == 0)
800eeca4 8023 {
56d27c17 8024 /* FIXME keep GR values which are marked as "safe_across_calls" */
800eeca4
JW		 8025 clear_register_values ();
8026 clear_qp_mutex (~qp_safe_across_calls);
8027 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8028 clear_qp_branch_flag (~qp_safe_across_calls);
8029 }
e9718fe1 8030 else if (is_interruption_or_rfi (idesc)
542d6675 8031 || is_taken_branch (idesc))
e9718fe1
TW		 8032 {
8033 clear_register_values ();
197865e8
KH		 8034 clear_qp_mutex (~(valueT) 0);
8035 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
e9718fe1 8036 }
542d6675 8037 /* Look for mutex and implies relations. */
197865e8 8038 else if ((idesc->operands[0] == IA64_OPND_P1
542d6675
KH		 8039 || idesc->operands[0] == IA64_OPND_P2)
8040 && (idesc->operands[1] == IA64_OPND_P1
8041 || idesc->operands[1] == IA64_OPND_P2))
800eeca4
JW		 8042 {
8043 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
197865e8
KH		 8044 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8045 valueT p1mask = (valueT) 1 << p1;
8046 valueT p2mask = (valueT) 1 << p2;
800eeca4 8047
542d6675 8048 /* If one of the PRs is PR0, we can't really do anything. */
800eeca4 8049 if (p1 == 0 || p2 == 0)
542d6675
KH		 8050 {
8051 if (md.debug_dv)
8052 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8053 }
800eeca4 8054 /* In general, clear mutexes and implies which include P1 or P2,
542d6675 8055 with the following exceptions. */
800eeca4 8056 else if (strstr (idesc->name, ".or.andcm") != NULL)
542d6675
KH		 8057 {
8058 add_qp_mutex (p1mask | p2mask);
8059 clear_qp_implies (p2mask, p1mask);
8060 }
800eeca4 8061 else if (strstr (idesc->name, ".and.orcm") != NULL)
542d6675
KH		 8062 {
8063 add_qp_mutex (p1mask | p2mask);
8064 clear_qp_implies (p1mask, p2mask);
8065 }
800eeca4 8066 else if (strstr (idesc->name, ".and") != NULL)
542d6675
KH		 8067 {
8068 clear_qp_implies (0, p1mask | p2mask);
8069 }
800eeca4 8070 else if (strstr (idesc->name, ".or") != NULL)
542d6675
KH		 8071 {
8072 clear_qp_mutex (p1mask | p2mask);
8073 clear_qp_implies (p1mask | p2mask, 0);
8074 }
800eeca4 8075 else
542d6675
KH		 8076 {
8077 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
8078 if (strstr (idesc->name, ".unc") != NULL)
8079 {
8080 add_qp_mutex (p1mask | p2mask);
8081 if (CURR_SLOT.qp_regno != 0)
8082 {
8083 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8084 CURR_SLOT.qp_regno);
8085 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8086 CURR_SLOT.qp_regno);
8087 }
8088 }
8089 else if (CURR_SLOT.qp_regno == 0)
8090 {
8091 add_qp_mutex (p1mask | p2mask);
8092 }
8093 else
8094 {
8095 clear_qp_mutex (p1mask | p2mask);
8096 }
8097 }
8098 }
8099 /* Look for mov imm insns into GRs. */
800eeca4 8100 else if (idesc->operands[0] == IA64_OPND_R1
542d6675
KH		 8101 && (idesc->operands[1] == IA64_OPND_IMM22
8102 || idesc->operands[1] == IA64_OPND_IMMU64)
8103 && (strcmp (idesc->name, "mov") == 0
8104 || strcmp (idesc->name, "movl") == 0))
800eeca4
JW		 8105 {
8106 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
542d6675
KH		 8107 if (regno > 0 && regno < NELEMS (gr_values))
8108 {
8109 gr_values[regno].known = 1;
8110 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
8111 gr_values[regno].path = md.path;
8112 if (md.debug_dv)
8113 fprintf (stderr, " Know gr%d = 0x%llx\n",
8114 regno, gr_values[regno].value);
8115 }
800eeca4 8116 }
197865e8 8117 else
800eeca4
JW		 8118 {
8119 clear_qp_mutex (qp_changemask);
8120 clear_qp_implies (qp_changemask, qp_changemask);
8121 }
8122}
8123
542d6675
KH		 8124/* Return whether the given predicate registers are currently mutex. */
8125
800eeca4
JW		 8126static int
8127qp_mutex (p1, p2, path)
542d6675
KH		 8128 int p1;
8129 int p2;
8130 int path;
800eeca4
JW		 8131{
8132 int i;
8133 valueT mask;
8134
8135 if (p1 != p2)
8136 {
542d6675
KH		 8137 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
8138 for (i = 0; i < qp_mutexeslen; i++)
8139 {
8140 if (qp_mutexes[i].path >= path
8141 && (qp_mutexes[i].prmask & mask) == mask)
8142 return 1;
8143 }
800eeca4
JW		 8144 }
8145 return 0;
8146}
8147
8148/* Return whether the given resource is in the given insn's list of chks
8149 Return 1 if the conflict is absolutely determined, 2 if it's a potential
542d6675
KH		 8150 conflict. */
8151
800eeca4
JW		 8152static int
8153resources_match (rs, idesc, note, qp_regno, path)
542d6675
KH		 8154 struct rsrc *rs;
8155 struct ia64_opcode *idesc;
8156 int note;
8157 int qp_regno;
8158 int path;
800eeca4
JW		 8159{
8160 struct rsrc specs[MAX_SPECS];
8161 int count;
8162
8163 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8164 we don't need to check. One exception is note 11, which indicates that
8165 target predicates are written regardless of PR[qp]. */
197865e8 8166 if (qp_mutex (rs->qp_regno, qp_regno, path)
800eeca4
JW		 8167 && note != 11)
8168 return 0;
8169
8170 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
8171 while (count-- > 0)
8172 {
8173 /* UNAT checking is a bit more specific than other resources */
8174 if (rs->dependency->specifier == IA64_RS_AR_UNAT
542d6675
KH		 8175 && specs[count].mem_offset.hint
8176 && rs->mem_offset.hint)
8177 {
8178 if (rs->mem_offset.base == specs[count].mem_offset.base)
8179 {
8180 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
8181 ((specs[count].mem_offset.offset >> 3) & 0x3F))
8182 return 1;
8183 else
8184 continue;
8185 }
8186 }
800eeca4 8187
7484b8e6 8188 /* Skip apparent PR write conflicts where both writes are an AND or both
4a4f25cf 8189 writes are an OR. */
7484b8e6 8190 if (rs->dependency->specifier == IA64_RS_PR
afa680f8 8191 || rs->dependency->specifier == IA64_RS_PRr
7484b8e6
TW		 8192 || rs->dependency->specifier == IA64_RS_PR63)
8193 {
8194 if (specs[count].cmp_type != CMP_NONE
8195 && specs[count].cmp_type == rs->cmp_type)
8196 {
8197 if (md.debug_dv)
8198 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
8199 dv_mode[rs->dependency->mode],
afa680f8 8200 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6
TW		 8201 specs[count].index : 63);
8202 continue;
8203 }
8204 if (md.debug_dv)
4a4f25cf 8205 fprintf (stderr,
7484b8e6
TW		 8206 " %s on parallel compare conflict %s vs %s on PR%d\n",
8207 dv_mode[rs->dependency->mode],
4a4f25cf 8208 dv_cmp_type[rs->cmp_type],
7484b8e6 8209 dv_cmp_type[specs[count].cmp_type],
afa680f8 8210 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6 8211 specs[count].index : 63);
4a4f25cf 8212
7484b8e6
TW		 8213 }
8214
800eeca4 8215 /* If either resource is not specific, conservatively assume a conflict
197865e8 8216 */
800eeca4 8217 if (!specs[count].specific || !rs->specific)
542d6675 8218 return 2;
800eeca4 8219 else if (specs[count].index == rs->index)
542d6675 8220 return 1;
800eeca4
JW		 8221 }
8222#if 0
8223 if (md.debug_dv)
8224 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
8225#endif
8226
8227 return 0;
8228}
8229
8230/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8231 insert a stop to create the break. Update all resource dependencies
8232 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8233 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8234 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
542d6675 8235 instruction. */
800eeca4
JW		 8236
8237static void
8238insn_group_break (insert_stop, qp_regno, save_current)
542d6675
KH		 8239 int insert_stop;
8240 int qp_regno;
8241 int save_current;
800eeca4
JW		 8242{
8243 int i;
8244
8245 if (insert_stop && md.num_slots_in_use > 0)
8246 PREV_SLOT.end_of_insn_group = 1;
8247
8248 if (md.debug_dv)
8249 {
197865e8 8250 fprintf (stderr, " Insn group break%s",
542d6675 8251 (insert_stop ? " (w/stop)" : ""));
800eeca4 8252 if (qp_regno != 0)
542d6675 8253 fprintf (stderr, " effective for QP=%d", qp_regno);
800eeca4
JW		 8254 fprintf (stderr, "\n");
8255 }
8256
8257 i = 0;
8258 while (i < regdepslen)
8259 {
8260 const struct ia64_dependency *dep = regdeps[i].dependency;
8261
8262 if (qp_regno != 0
542d6675
KH		 8263 && regdeps[i].qp_regno != qp_regno)
8264 {
8265 ++i;
8266 continue;
8267 }
800eeca4
JW		 8268
8269 if (save_current
542d6675
KH		 8270 && CURR_SLOT.src_file == regdeps[i].file
8271 && CURR_SLOT.src_line == regdeps[i].line)
8272 {
8273 ++i;
8274 continue;
8275 }
800eeca4
JW		 8276
8277 /* clear dependencies which are automatically cleared by a stop, or
542d6675 8278 those that have reached the appropriate state of insn serialization */
800eeca4 8279 if (dep->semantics == IA64_DVS_IMPLIED
542d6675
KH		 8280 || dep->semantics == IA64_DVS_IMPLIEDF
8281 || regdeps[i].insn_srlz == STATE_SRLZ)
8282 {
8283 print_dependency ("Removing", i);
8284 regdeps[i] = regdeps[--regdepslen];
8285 }
800eeca4 8286 else
542d6675
KH		 8287 {
8288 if (dep->semantics == IA64_DVS_DATA
8289 || dep->semantics == IA64_DVS_INSTR
800eeca4 8290 || dep->semantics == IA64_DVS_SPECIFIC)
542d6675
KH		 8291 {
8292 if (regdeps[i].insn_srlz == STATE_NONE)
8293 regdeps[i].insn_srlz = STATE_STOP;
8294 if (regdeps[i].data_srlz == STATE_NONE)
8295 regdeps[i].data_srlz = STATE_STOP;
8296 }
8297 ++i;
8298 }
800eeca4
JW		 8299 }
8300}
8301
542d6675
KH		 8302/* Add the given resource usage spec to the list of active dependencies. */
8303
197865e8 8304static void
800eeca4 8305mark_resource (idesc, dep, spec, depind, path)
542d6675
KH		 8306 struct ia64_opcode *idesc;
8307 const struct ia64_dependency *dep;
8308 struct rsrc *spec;
8309 int depind;
8310 int path;
800eeca4
JW		 8311{
8312 if (regdepslen == regdepstotlen)
8313 {
8314 regdepstotlen += 20;
8315 regdeps = (struct rsrc *)
542d6675
KH		 8316 xrealloc ((void *) regdeps,
8317 regdepstotlen * sizeof(struct rsrc));
800eeca4
JW		 8318 }
8319
8320 regdeps[regdepslen] = *spec;
8321 regdeps[regdepslen].depind = depind;
8322 regdeps[regdepslen].path = path;
8323 regdeps[regdepslen].file = CURR_SLOT.src_file;
8324 regdeps[regdepslen].line = CURR_SLOT.src_line;
8325
8326 print_dependency ("Adding", regdepslen);
8327
8328 ++regdepslen;
8329}
8330
8331static void
8332print_dependency (action, depind)
542d6675
KH		 8333 const char *action;
8334 int depind;
800eeca4
JW		 8335{
8336 if (md.debug_dv)
8337 {
197865e8 8338 fprintf (stderr, " %s %s '%s'",
542d6675
KH		 8339 action, dv_mode[(regdeps[depind].dependency)->mode],
8340 (regdeps[depind].dependency)->name);
800eeca4 8341 if (regdeps[depind].specific && regdeps[depind].index != 0)
542d6675 8342 fprintf (stderr, " (%d)", regdeps[depind].index);
800eeca4 8343 if (regdeps[depind].mem_offset.hint)
542d6675
KH		 8344 fprintf (stderr, " 0x%llx+0x%llx",
8345 regdeps[depind].mem_offset.base,
8346 regdeps[depind].mem_offset.offset);
800eeca4
JW		 8347 fprintf (stderr, "\n");
8348 }
8349}
8350
8351static void
8352instruction_serialization ()
8353{
8354 int i;
8355 if (md.debug_dv)
8356 fprintf (stderr, " Instruction serialization\n");
542d6675 8357 for (i = 0; i < regdepslen; i++)
800eeca4
JW		 8358 if (regdeps[i].insn_srlz == STATE_STOP)
8359 regdeps[i].insn_srlz = STATE_SRLZ;
8360}
8361
8362static void
8363data_serialization ()
8364{
8365 int i = 0;
8366 if (md.debug_dv)
8367 fprintf (stderr, " Data serialization\n");
8368 while (i < regdepslen)
8369 {
8370 if (regdeps[i].data_srlz == STATE_STOP
542d6675
KH		 8371 /* Note: as of 991210, all "other" dependencies are cleared by a
8372 data serialization. This might change with new tables */
8373 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8374 {
8375 print_dependency ("Removing", i);
8376 regdeps[i] = regdeps[--regdepslen];
8377 }
800eeca4 8378 else
542d6675 8379 ++i;
800eeca4
JW		 8380 }
8381}
8382
542d6675
KH		 8383/* Insert stops and serializations as needed to avoid DVs. */
8384
800eeca4
JW		 8385static void
8386remove_marked_resource (rs)
542d6675 8387 struct rsrc *rs;
800eeca4
JW		 8388{
8389 switch (rs->dependency->semantics)
8390 {
8391 case IA64_DVS_SPECIFIC:
8392 if (md.debug_dv)
8393 fprintf (stderr, "Implementation-specific, assume worst case...\n");
197865e8 8394 /* ...fall through... */
800eeca4
JW		 8395 case IA64_DVS_INSTR:
8396 if (md.debug_dv)
542d6675 8397 fprintf (stderr, "Inserting instr serialization\n");
800eeca4 8398 if (rs->insn_srlz < STATE_STOP)
542d6675 8399 insn_group_break (1, 0, 0);
800eeca4 8400 if (rs->insn_srlz < STATE_SRLZ)
542d6675
KH		 8401 {
8402 int oldqp = CURR_SLOT.qp_regno;
8403 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8404 /* Manually jam a srlz.i insn into the stream */
8405 CURR_SLOT.qp_regno = 0;
8406 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8407 instruction_serialization ();
8408 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8409 if (++md.num_slots_in_use >= NUM_SLOTS)
8410 emit_one_bundle ();
8411 CURR_SLOT.qp_regno = oldqp;
8412 CURR_SLOT.idesc = oldidesc;
8413 }
800eeca4
JW		 8414 insn_group_break (1, 0, 0);
8415 break;
8416 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
542d6675
KH		 8417 "other" types of DV are eliminated
8418 by a data serialization */
800eeca4
JW		 8419 case IA64_DVS_DATA:
8420 if (md.debug_dv)
542d6675 8421 fprintf (stderr, "Inserting data serialization\n");
800eeca4 8422 if (rs->data_srlz < STATE_STOP)
542d6675 8423 insn_group_break (1, 0, 0);
800eeca4 8424 {
542d6675
KH		 8425 int oldqp = CURR_SLOT.qp_regno;
8426 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8427 /* Manually jam a srlz.d insn into the stream */
8428 CURR_SLOT.qp_regno = 0;
8429 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8430 data_serialization ();
8431 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8432 if (++md.num_slots_in_use >= NUM_SLOTS)
8433 emit_one_bundle ();
8434 CURR_SLOT.qp_regno = oldqp;
8435 CURR_SLOT.idesc = oldidesc;
800eeca4
JW		 8436 }
8437 break;
8438 case IA64_DVS_IMPLIED:
8439 case IA64_DVS_IMPLIEDF:
8440 if (md.debug_dv)
542d6675 8441 fprintf (stderr, "Inserting stop\n");
800eeca4
JW		 8442 insn_group_break (1, 0, 0);
8443 break;
8444 default:
8445 break;
8446 }
8447}
8448
8449/* Check the resources used by the given opcode against the current dependency
197865e8 8450 list.
800eeca4
JW		 8451
8452 The check is run once for each execution path encountered. In this case,
8453 a unique execution path is the sequence of instructions following a code
8454 entry point, e.g. the following has three execution paths, one starting
8455 at L0, one at L1, and one at L2.
197865e8 8456
800eeca4
JW		 8457 L0: nop
8458 L1: add
8459 L2: add
197865e8 8460 br.ret
800eeca4 8461*/
542d6675 8462
800eeca4
JW		 8463static void
8464check_dependencies (idesc)
542d6675 8465 struct ia64_opcode *idesc;
800eeca4
JW		 8466{
8467 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8468 int path;
8469 int i;
8470
8471 /* Note that the number of marked resources may change within the
197865e8 8472 loop if in auto mode. */
800eeca4
JW		 8473 i = 0;
8474 while (i < regdepslen)
8475 {
8476 struct rsrc *rs = &regdeps[i];
8477 const struct ia64_dependency *dep = rs->dependency;
8478 int chkind;
8479 int note;
8480 int start_over = 0;
8481
8482 if (dep->semantics == IA64_DVS_NONE
542d6675
KH		 8483 || (chkind = depends_on (rs->depind, idesc)) == -1)
8484 {
8485 ++i;
8486 continue;
8487 }
8488
8489 note = NOTE (opdeps->chks[chkind]);
8490
8491 /* Check this resource against each execution path seen thus far. */
8492 for (path = 0; path <= md.path; path++)
8493 {
8494 int matchtype;
8495
8496 /* If the dependency wasn't on the path being checked, ignore it. */
8497 if (rs->path < path)
8498 continue;
8499
8500 /* If the QP for this insn implies a QP which has branched, don't
8501 bother checking. Ed. NOTE: I don't think this check is terribly
8502 useful; what's the point of generating code which will only be
8503 reached if its QP is zero?
8504 This code was specifically inserted to handle the following code,
8505 based on notes from Intel's DV checking code, where p1 implies p2.
8506
8507 mov r4 = 2
8508 (p2) br.cond L
8509 (p1) mov r4 = 7
8510 */
8511 if (CURR_SLOT.qp_regno != 0)
8512 {
8513 int skip = 0;
8514 int implies;
8515 for (implies = 0; implies < qp_implieslen; implies++)
8516 {
8517 if (qp_implies[implies].path >= path
8518 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8519 && qp_implies[implies].p2_branched)
8520 {
8521 skip = 1;
8522 break;
8523 }
8524 }
8525 if (skip)
8526 continue;
8527 }
8528
8529 if ((matchtype = resources_match (rs, idesc, note,
8530 CURR_SLOT.qp_regno, path)) != 0)
8531 {
8532 char msg[1024];
8533 char pathmsg[256] = "";
8534 char indexmsg[256] = "";
8535 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8536
8537 if (path != 0)
8538 sprintf (pathmsg, " when entry is at label '%s'",
8539 md.entry_labels[path - 1]);
8540 if (rs->specific && rs->index != 0)
8541 sprintf (indexmsg, ", specific resource number is %d",
8542 rs->index);
8543 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8544 idesc->name,
8545 (certain ? "violates" : "may violate"),
8546 dv_mode[dep->mode], dep->name,
8547 dv_sem[dep->semantics],
8548 pathmsg, indexmsg);
8549
8550 if (md.explicit_mode)
8551 {
8552 as_warn ("%s", msg);
8553 if (path < md.path)
8554 as_warn (_("Only the first path encountering the conflict "
8555 "is reported"));
8556 as_warn_where (rs->file, rs->line,
8557 _("This is the location of the "
8558 "conflicting usage"));
8559 /* Don't bother checking other paths, to avoid duplicating
8560 the same warning */
8561 break;
8562 }
8563 else
8564 {
8565 if (md.debug_dv)
8566 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
8567
8568 remove_marked_resource (rs);
8569
8570 /* since the set of dependencies has changed, start over */
8571 /* FIXME -- since we're removing dvs as we go, we
8572 probably don't really need to start over... */
8573 start_over = 1;
8574 break;
8575 }
8576 }
8577 }
800eeca4 8578 if (start_over)
542d6675 8579 i = 0;
800eeca4 8580 else
542d6675 8581 ++i;
800eeca4
JW		 8582 }
8583}
8584
542d6675
KH		 8585/* Register new dependencies based on the given opcode. */
8586
800eeca4
JW		 8587static void
8588mark_resources (idesc)
542d6675 8589 struct ia64_opcode *idesc;
800eeca4
JW		 8590{
8591 int i;
8592 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8593 int add_only_qp_reads = 0;
8594
8595 /* A conditional branch only uses its resources if it is taken; if it is
8596 taken, we stop following that path. The other branch types effectively
8597 *always* write their resources. If it's not taken, register only QP
197865e8 8598 reads. */
800eeca4
JW		 8599 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8600 {
8601 add_only_qp_reads = 1;
8602 }
8603
8604 if (md.debug_dv)
8605 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8606
542d6675 8607 for (i = 0; i < opdeps->nregs; i++)
800eeca4
JW		 8608 {
8609 const struct ia64_dependency *dep;
8610 struct rsrc specs[MAX_SPECS];
8611 int note;
8612 int path;
8613 int count;
197865e8 8614
800eeca4 8615 dep = ia64_find_dependency (opdeps->regs[i]);
542d6675 8616 note = NOTE (opdeps->regs[i]);
800eeca4
JW		 8617
8618 if (add_only_qp_reads
542d6675
KH		 8619 && !(dep->mode == IA64_DV_WAR
8620 && (dep->specifier == IA64_RS_PR
139368c9 8621 || dep->specifier == IA64_RS_PRr
542d6675
KH		 8622 || dep->specifier == IA64_RS_PR63)))
8623 continue;
800eeca4
JW		 8624
8625 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8626
8627#if 0
8628 if (md.debug_dv && !count)
542d6675
KH		 8629 fprintf (stderr, " No %s %s usage found (path %d)\n",
8630 dv_mode[dep->mode], dep->name, md.path);
800eeca4 8631#endif
197865e8 8632
800eeca4 8633 while (count-- > 0)
542d6675
KH		 8634 {
8635 mark_resource (idesc, dep, &specs[count],
8636 DEP (opdeps->regs[i]), md.path);
8637 }
800eeca4
JW		 8638
8639 /* The execution path may affect register values, which may in turn
542d6675 8640 affect which indirect-access resources are accessed. */
800eeca4 8641 switch (dep->specifier)
542d6675
KH		 8642 {
8643 default:
8644 break;
8645 case IA64_RS_CPUID:
8646 case IA64_RS_DBR:
8647 case IA64_RS_IBR:
800eeca4 8648 case IA64_RS_MSR:
542d6675
KH		 8649 case IA64_RS_PKR:
8650 case IA64_RS_PMC:
8651 case IA64_RS_PMD:
8652 case IA64_RS_RR:
8653 for (path = 0; path < md.path; path++)
8654 {
8655 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8656 while (count-- > 0)
8657 mark_resource (idesc, dep, &specs[count],
8658 DEP (opdeps->regs[i]), path);
8659 }
8660 break;
8661 }
8662 }
8663}
8664
8665/* Remove dependencies when they no longer apply. */
8666
800eeca4
JW		 8667static void
8668update_dependencies (idesc)
542d6675 8669 struct ia64_opcode *idesc;
800eeca4
JW		 8670{
8671 int i;
8672
8673 if (strcmp (idesc->name, "srlz.i") == 0)
8674 {
8675 instruction_serialization ();
8676 }
8677 else if (strcmp (idesc->name, "srlz.d") == 0)
8678 {
8679 data_serialization ();
8680 }
8681 else if (is_interruption_or_rfi (idesc)
542d6675 8682 || is_taken_branch (idesc))
800eeca4 8683 {
542d6675
KH		 8684 /* Although technically the taken branch doesn't clear dependencies
8685 which require a srlz.[id], we don't follow the branch; the next
8686 instruction is assumed to start with a clean slate. */
800eeca4 8687 regdepslen = 0;
800eeca4
JW		 8688 md.path = 0;
8689 }
8690 else if (is_conditional_branch (idesc)
542d6675 8691 && CURR_SLOT.qp_regno != 0)
800eeca4
JW		 8692 {
8693 int is_call = strstr (idesc->name, ".call") != NULL;
8694
542d6675
KH		 8695 for (i = 0; i < qp_implieslen; i++)
8696 {
8697 /* If the conditional branch's predicate is implied by the predicate
8698 in an existing dependency, remove that dependency. */
8699 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8700 {
8701 int depind = 0;
8702 /* Note that this implied predicate takes a branch so that if
8703 a later insn generates a DV but its predicate implies this
8704 one, we can avoid the false DV warning. */
8705 qp_implies[i].p2_branched = 1;
8706 while (depind < regdepslen)
8707 {
8708 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8709 {
8710 print_dependency ("Removing", depind);
8711 regdeps[depind] = regdeps[--regdepslen];
8712 }
8713 else
8714 ++depind;
8715 }
8716 }
8717 }
800eeca4 8718 /* Any marked resources which have this same predicate should be
542d6675
KH		 8719 cleared, provided that the QP hasn't been modified between the
8720 marking instruction and the branch. */
800eeca4 8721 if (is_call)
542d6675
KH		 8722 {
8723 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8724 }
800eeca4 8725 else
542d6675
KH		 8726 {
8727 i = 0;
8728 while (i < regdepslen)
8729 {
8730 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8731 && regdeps[i].link_to_qp_branch
8732 && (regdeps[i].file != CURR_SLOT.src_file
8733 || regdeps[i].line != CURR_SLOT.src_line))
8734 {
8735 /* Treat like a taken branch */
8736 print_dependency ("Removing", i);
8737 regdeps[i] = regdeps[--regdepslen];
8738 }
8739 else
8740 ++i;
8741 }
8742 }
800eeca4
JW		 8743 }
8744}
8745
8746/* Examine the current instruction for dependency violations. */
542d6675 8747
800eeca4
JW		 8748static int
8749check_dv (idesc)
542d6675 8750 struct ia64_opcode *idesc;
800eeca4
JW		 8751{
8752 if (md.debug_dv)
8753 {
197865e8 8754 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
542d6675
KH		 8755 idesc->name, CURR_SLOT.src_line,
8756 idesc->dependencies->nchks,
8757 idesc->dependencies->nregs);
800eeca4
JW		 8758 }
8759
197865e8 8760 /* Look through the list of currently marked resources; if the current
800eeca4 8761 instruction has the dependency in its chks list which uses that resource,
542d6675 8762 check against the specific resources used. */
800eeca4
JW		 8763 check_dependencies (idesc);
8764
542d6675
KH		 8765 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8766 then add them to the list of marked resources. */
800eeca4
JW		 8767 mark_resources (idesc);
8768
8769 /* There are several types of dependency semantics, and each has its own
197865e8
KH		 8770 requirements for being cleared
8771
800eeca4
JW		 8772 Instruction serialization (insns separated by interruption, rfi, or
8773 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8774
8775 Data serialization (instruction serialization, or writer + srlz.d +
8776 reader, where writer and srlz.d are in separate groups) clears
8777 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8778 always be the case).
8779
8780 Instruction group break (groups separated by stop, taken branch,
8781 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8782 */
8783 update_dependencies (idesc);
8784
8785 /* Sometimes, knowing a register value allows us to avoid giving a false DV
197865e8 8786 warning. Keep track of as many as possible that are useful. */
800eeca4
JW		 8787 note_register_values (idesc);
8788
197865e8 8789 /* We don't need or want this anymore. */
800eeca4
JW		 8790 md.mem_offset.hint = 0;
8791
8792 return 0;
8793}
8794
8795/* Translate one line of assembly. Pseudo ops and labels do not show
8796 here. */
8797void
8798md_assemble (str)
8799 char *str;
8800{
8801 char *saved_input_line_pointer, *mnemonic;
8802 const struct pseudo_opcode *pdesc;
8803 struct ia64_opcode *idesc;
8804 unsigned char qp_regno;
8805 unsigned int flags;
8806 int ch;
8807
8808 saved_input_line_pointer = input_line_pointer;
8809 input_line_pointer = str;
8810
542d6675 8811 /* extract the opcode (mnemonic): */
800eeca4
JW		 8812
8813 mnemonic = input_line_pointer;
8814 ch = get_symbol_end ();
8815 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
8816 if (pdesc)
8817 {
8818 *input_line_pointer = ch;
8819 (*pdesc->handler) (pdesc->arg);
8820 goto done;
8821 }
8822
542d6675 8823 /* Find the instruction descriptor matching the arguments. */
800eeca4
JW		 8824
8825 idesc = ia64_find_opcode (mnemonic);
8826 *input_line_pointer = ch;
8827 if (!idesc)
8828 {
8829 as_bad ("Unknown opcode `%s'", mnemonic);
8830 goto done;
8831 }
8832
8833 idesc = parse_operands (idesc);
8834 if (!idesc)
8835 goto done;
8836
542d6675 8837 /* Handle the dynamic ops we can handle now: */
800eeca4
JW		 8838 if (idesc->type == IA64_TYPE_DYN)
8839 {
8840 if (strcmp (idesc->name, "add") == 0)
8841 {
8842 if (CURR_SLOT.opnd[2].X_op == O_register
8843 && CURR_SLOT.opnd[2].X_add_number < 4)
8844 mnemonic = "addl";
8845 else
8846 mnemonic = "adds";
3d56ab85 8847 ia64_free_opcode (idesc);
800eeca4
JW		 8848 idesc = ia64_find_opcode (mnemonic);
8849#if 0
8850 know (!idesc->next);
8851#endif
8852 }
8853 else if (strcmp (idesc->name, "mov") == 0)
8854 {
8855 enum ia64_opnd opnd1, opnd2;
8856 int rop;
8857
8858 opnd1 = idesc->operands[0];
8859 opnd2 = idesc->operands[1];
8860 if (opnd1 == IA64_OPND_AR3)
8861 rop = 0;
8862 else if (opnd2 == IA64_OPND_AR3)
8863 rop = 1;
8864 else
8865 abort ();
8866 if (CURR_SLOT.opnd[rop].X_op == O_register
8867 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
8868 mnemonic = "mov.i";
8869 else
8870 mnemonic = "mov.m";
3d56ab85 8871 ia64_free_opcode (idesc);
800eeca4
JW		 8872 idesc = ia64_find_opcode (mnemonic);
8873 while (idesc != NULL
8874 && (idesc->operands[0] != opnd1
8875 || idesc->operands[1] != opnd2))
8876 idesc = get_next_opcode (idesc);
8877 }
8878 }
8879
8880 qp_regno = 0;
8881 if (md.qp.X_op == O_register)
f1bcba5b
JW		 8882 {
8883 qp_regno = md.qp.X_add_number - REG_P;
8884 md.qp.X_op = O_absent;
8885 }
800eeca4
JW		 8886
8887 flags = idesc->flags;
8888
8889 if ((flags & IA64_OPCODE_FIRST) != 0)
8890 insn_group_break (1, 0, 0);
8891
8892 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
8893 {
8894 as_bad ("`%s' cannot be predicated", idesc->name);
8895 goto done;
8896 }
8897
542d6675 8898 /* Build the instruction. */
800eeca4
JW		 8899 CURR_SLOT.qp_regno = qp_regno;
8900 CURR_SLOT.idesc = idesc;
8901 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
8902 if (debug_type == DEBUG_DWARF2)
8903 dwarf2_where (&CURR_SLOT.debug_line);
8904
8905 /* Add unwind entry, if there is one. */
e0c9811a 8906 if (unwind.current_entry)
800eeca4 8907 {
e0c9811a
JW		 8908 CURR_SLOT.unwind_record = unwind.current_entry;
8909 unwind.current_entry = NULL;
800eeca4
JW		 8910 }
8911
542d6675 8912 /* Check for dependency violations. */
800eeca4 8913 if (md.detect_dv)
542d6675 8914 check_dv (idesc);
800eeca4
JW		 8915
8916 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8917 if (++md.num_slots_in_use >= NUM_SLOTS)
8918 emit_one_bundle ();
8919
8920 if ((flags & IA64_OPCODE_LAST) != 0)
8921 insn_group_break (1, 0, 0);
8922
8923 md.last_text_seg = now_seg;
8924
8925 done:
8926 input_line_pointer = saved_input_line_pointer;
8927}
8928
8929/* Called when symbol NAME cannot be found in the symbol table.
8930 Should be used for dynamic valued symbols only. */
542d6675
KH		 8931
8932symbolS *
800eeca4
JW		 8933md_undefined_symbol (name)
8934 char *name;
8935{
8936 return 0;
8937}
8938
8939/* Called for any expression that can not be recognized. When the
8940 function is called, `input_line_pointer' will point to the start of
8941 the expression. */
542d6675 8942
800eeca4
JW		 8943void
8944md_operand (e)
8945 expressionS *e;
8946{
8947 enum pseudo_type pseudo_type;
e0c9811a 8948 const char *name;
800eeca4
JW		 8949 size_t len;
8950 int ch, i;
8951
8952 switch (*input_line_pointer)
8953 {
8954 case '@':
542d6675 8955 /* Find what relocation pseudo-function we're dealing with. */
800eeca4
JW		 8956 pseudo_type = 0;
8957 ch = *++input_line_pointer;
8958 for (i = 0; i < NELEMS (pseudo_func); ++i)
8959 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
8960 {
8961 len = strlen (pseudo_func[i].name);
8962 if (strncmp (pseudo_func[i].name + 1,
8963 input_line_pointer + 1, len - 1) == 0
8964 && !is_part_of_name (input_line_pointer[len]))
8965 {
8966 input_line_pointer += len;
8967 pseudo_type = pseudo_func[i].type;
8968 break;
8969 }
8970 }
8971 switch (pseudo_type)
8972 {
8973 case PSEUDO_FUNC_RELOC:
8974 SKIP_WHITESPACE ();
8975 if (*input_line_pointer != '(')
8976 {
8977 as_bad ("Expected '('");
8978 goto err;
8979 }
542d6675
KH		 8980 /* Skip '('. */
8981 ++input_line_pointer;
800eeca4
JW		 8982 expression (e);
8983 if (*input_line_pointer++ != ')')
8984 {
8985 as_bad ("Missing ')'");
8986 goto err;
8987 }
8988 if (e->X_op != O_symbol)
8989 {
8990 if (e->X_op != O_pseudo_fixup)
8991 {
8992 as_bad ("Not a symbolic expression");
8993 goto err;
8994 }
8995 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
8996 && i == FUNC_LT_RELATIVE)
8997 i = FUNC_LT_FPTR_RELATIVE;
8998 else
8999 {
9000 as_bad ("Illegal combination of relocation functions");
9001 goto err;
9002 }
9003 }
542d6675
KH		 9004 /* Make sure gas doesn't get rid of local symbols that are used
9005 in relocs. */
800eeca4
JW		 9006 e->X_op = O_pseudo_fixup;
9007 e->X_op_symbol = pseudo_func[i].u.sym;
9008 break;
9009
9010 case PSEUDO_FUNC_CONST:
9011 e->X_op = O_constant;
9012 e->X_add_number = pseudo_func[i].u.ival;
9013 break;
9014
e0c9811a
JW		 9015 case PSEUDO_FUNC_REG:
9016 e->X_op = O_register;
9017 e->X_add_number = pseudo_func[i].u.ival;
9018 break;
9019
800eeca4 9020 default:
e0c9811a
JW		 9021 name = input_line_pointer - 1;
9022 get_symbol_end ();
9023 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW		 9024 goto err;
9025 }
9026 break;
9027
9028 case '[':
9029 ++input_line_pointer;
9030 expression (e);
9031 if (*input_line_pointer != ']')
9032 {
9033 as_bad ("Closing bracket misssing");
9034 goto err;
9035 }
9036 else
9037 {
9038 if (e->X_op != O_register)
9039 as_bad ("Register expected as index");
9040
9041 ++input_line_pointer;
9042 e->X_op = O_index;
9043 }
9044 break;
9045
9046 default:
9047 break;
9048 }
9049 return;
9050
9051 err:
9052 ignore_rest_of_line ();
9053}
9054
9055/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9056 a section symbol plus some offset. For relocs involving @fptr(),
9057 directives we don't want such adjustments since we need to have the
9058 original symbol's name in the reloc. */
9059int
9060ia64_fix_adjustable (fix)
9061 fixS *fix;
9062{
9063 /* Prevent all adjustments to global symbols */
9064 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9065 return 0;
9066
9067 switch (fix->fx_r_type)
9068 {
9069 case BFD_RELOC_IA64_FPTR64I:
9070 case BFD_RELOC_IA64_FPTR32MSB:
9071 case BFD_RELOC_IA64_FPTR32LSB:
9072 case BFD_RELOC_IA64_FPTR64MSB:
9073 case BFD_RELOC_IA64_FPTR64LSB:
9074 case BFD_RELOC_IA64_LTOFF_FPTR22:
9075 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9076 return 0;
9077 default:
9078 break;
9079 }
9080
9081 return 1;
9082}
9083
9084int
9085ia64_force_relocation (fix)
9086 fixS *fix;
9087{
9088 switch (fix->fx_r_type)
9089 {
9090 case BFD_RELOC_IA64_FPTR64I:
9091 case BFD_RELOC_IA64_FPTR32MSB:
9092 case BFD_RELOC_IA64_FPTR32LSB:
9093 case BFD_RELOC_IA64_FPTR64MSB:
9094 case BFD_RELOC_IA64_FPTR64LSB:
9095
9096 case BFD_RELOC_IA64_LTOFF22:
9097 case BFD_RELOC_IA64_LTOFF64I:
9098 case BFD_RELOC_IA64_LTOFF_FPTR22:
9099 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9100 case BFD_RELOC_IA64_PLTOFF22:
9101 case BFD_RELOC_IA64_PLTOFF64I:
9102 case BFD_RELOC_IA64_PLTOFF64MSB:
9103 case BFD_RELOC_IA64_PLTOFF64LSB:
9104 return 1;
9105
9106 default:
9107 return 0;
9108 }
9109 return 0;
9110}
9111
9112/* Decide from what point a pc-relative relocation is relative to,
9113 relative to the pc-relative fixup. Er, relatively speaking. */
9114long
9115ia64_pcrel_from_section (fix, sec)
9116 fixS *fix;
9117 segT sec;
9118{
9119 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
197865e8 9120
800eeca4
JW		 9121 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
9122 off &= ~0xfUL;
9123
9124 return off;
9125}
9126
9127/* This is called whenever some data item (not an instruction) needs a
9128 fixup. We pick the right reloc code depending on the byteorder
9129 currently in effect. */
9130void
9131ia64_cons_fix_new (f, where, nbytes, exp)
9132 fragS *f;
9133 int where;
9134 int nbytes;
9135 expressionS *exp;
9136{
9137 bfd_reloc_code_real_type code;
9138 fixS *fix;
9139
9140 switch (nbytes)
9141 {
9142 /* There are no reloc for 8 and 16 bit quantities, but we allow
9143 them here since they will work fine as long as the expression
9144 is fully defined at the end of the pass over the source file. */
9145 case 1: code = BFD_RELOC_8; break;
9146 case 2: code = BFD_RELOC_16; break;
9147 case 4:
9148 if (target_big_endian)
9149 code = BFD_RELOC_IA64_DIR32MSB;
9150 else
9151 code = BFD_RELOC_IA64_DIR32LSB;
9152 break;
9153
9154 case 8:
9155 if (target_big_endian)
9156 code = BFD_RELOC_IA64_DIR64MSB;
9157 else
9158 code = BFD_RELOC_IA64_DIR64LSB;
9159 break;
9160
9161 default:
9162 as_bad ("Unsupported fixup size %d", nbytes);
9163 ignore_rest_of_line ();
9164 return;
9165 }
9166 if (exp->X_op == O_pseudo_fixup)
9167 {
9168 /* ??? */
9169 exp->X_op = O_symbol;
9170 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
9171 }
9172 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
9173 /* We need to store the byte order in effect in case we're going
9174 to fix an 8 or 16 bit relocation (for which there no real
9175 relocs available). See md_apply_fix(). */
9176 fix->tc_fix_data.bigendian = target_big_endian;
9177}
9178
9179/* Return the actual relocation we wish to associate with the pseudo
9180 reloc described by SYM and R_TYPE. SYM should be one of the
197865e8 9181 symbols in the pseudo_func array, or NULL. */
800eeca4
JW		 9182
9183static bfd_reloc_code_real_type
9184ia64_gen_real_reloc_type (sym, r_type)
9185 struct symbol *sym;
9186 bfd_reloc_code_real_type r_type;
9187{
9188 bfd_reloc_code_real_type new = 0;
9189
9190 if (sym == NULL)
9191 {
9192 return r_type;
9193 }
9194
9195 switch (S_GET_VALUE (sym))
9196 {
9197 case FUNC_FPTR_RELATIVE:
9198 switch (r_type)
9199 {
9200 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
9201 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
9202 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
9203 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
9204 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
9205 default: break;
9206 }
9207 break;
9208
9209 case FUNC_GP_RELATIVE:
9210 switch (r_type)
9211 {
9212 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
9213 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
9214 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
9215 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
9216 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
9217 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
9218 default: break;
9219 }
9220 break;
9221
9222 case FUNC_LT_RELATIVE:
9223 switch (r_type)
9224 {
9225 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
9226 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
9227 default: break;
9228 }
9229 break;
9230
c67e42c9
RH		 9231 case FUNC_PC_RELATIVE:
9232 switch (r_type)
9233 {
9234 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
9235 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
9236 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
9237 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
9238 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
9239 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
9240 default: break;
9241 }
9242 break;
9243
800eeca4
JW		 9244 case FUNC_PLT_RELATIVE:
9245 switch (r_type)
9246 {
9247 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
9248 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
9249 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
9250 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
9251 default: break;
9252 }
9253 break;
9254
9255 case FUNC_SEC_RELATIVE:
9256 switch (r_type)
9257 {
9258 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
9259 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
9260 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
9261 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
9262 default: break;
9263 }
9264 break;
9265
9266 case FUNC_SEG_RELATIVE:
9267 switch (r_type)
9268 {
9269 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
9270 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
9271 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
9272 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
9273 default: break;
9274 }
9275 break;
9276
9277 case FUNC_LTV_RELATIVE:
9278 switch (r_type)
9279 {
9280 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
9281 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
9282 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
9283 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
9284 default: break;
9285 }
9286 break;
9287
9288 case FUNC_LT_FPTR_RELATIVE:
9289 switch (r_type)
9290 {
9291 case BFD_RELOC_IA64_IMM22:
9292 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9293 case BFD_RELOC_IA64_IMM64:
9294 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9295 default:
9296 break;
9297 }
9298 break;
9299 default:
9300 abort ();
9301 }
9302 /* Hmmmm. Should this ever occur? */
9303 if (new)
9304 return new;
9305 else
9306 return r_type;
9307}
9308
9309/* Here is where generate the appropriate reloc for pseudo relocation
9310 functions. */
9311void
9312ia64_validate_fix (fix)
9313 fixS *fix;
9314{
9315 switch (fix->fx_r_type)
9316 {
9317 case BFD_RELOC_IA64_FPTR64I:
9318 case BFD_RELOC_IA64_FPTR32MSB:
9319 case BFD_RELOC_IA64_FPTR64LSB:
9320 case BFD_RELOC_IA64_LTOFF_FPTR22:
9321 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9322 if (fix->fx_offset != 0)
9323 as_bad_where (fix->fx_file, fix->fx_line,
9324 "No addend allowed in @fptr() relocation");
9325 break;
9326 default:
9327 break;
9328 }
9329
9330 return;
9331}
9332
9333static void
9334fix_insn (fix, odesc, value)
9335 fixS *fix;
9336 const struct ia64_operand *odesc;
9337 valueT value;
9338{
9339 bfd_vma insn[3], t0, t1, control_bits;
9340 const char *err;
9341 char *fixpos;
9342 long slot;
9343
9344 slot = fix->fx_where & 0x3;
9345 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9346
c67e42c9 9347 /* Bundles are always in little-endian byte order */
800eeca4
JW		 9348 t0 = bfd_getl64 (fixpos);
9349 t1 = bfd_getl64 (fixpos + 8);
9350 control_bits = t0 & 0x1f;
9351 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9352 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9353 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9354
c67e42c9
RH		 9355 err = NULL;
9356 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 9357 {
c67e42c9
RH		 9358 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9359 insn[2] |= (((value & 0x7f) << 13)
9360 | (((value >> 7) & 0x1ff) << 27)
9361 | (((value >> 16) & 0x1f) << 22)
9362 | (((value >> 21) & 0x1) << 21)
9363 | (((value >> 63) & 0x1) << 36));
800eeca4 9364 }
c67e42c9
RH		 9365 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9366 {
9367 if (value & ~0x3fffffffffffffffULL)
9368 err = "integer operand out of range";
9369 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9370 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9371 }
9372 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9373 {
9374 value >>= 4;
9375 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9376 insn[2] |= ((((value >> 59) & 0x1) << 36)
9377 | (((value >> 0) & 0xfffff) << 13));
9378 }
9379 else
9380 err = (*odesc->insert) (odesc, value, insn + slot);
9381
9382 if (err)
9383 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW		 9384
9385 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9386 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
44f5c83a
JW		 9387 number_to_chars_littleendian (fixpos + 0, t0, 8);
9388 number_to_chars_littleendian (fixpos + 8, t1, 8);
800eeca4
JW		 9389}
9390
9391/* Attempt to simplify or even eliminate a fixup. The return value is
9392 ignored; perhaps it was once meaningful, but now it is historical.
9393 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9394
9395 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
197865e8 9396 (if possible). */
800eeca4
JW		 9397int
9398md_apply_fix3 (fix, valuep, seg)
9399 fixS *fix;
9400 valueT *valuep;
9401 segT seg;
9402{
9403 char *fixpos;
9404 valueT value = *valuep;
9405 int adjust = 0;
9406
9407 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9408
9409 if (fix->fx_pcrel)
9410 {
9411 switch (fix->fx_r_type)
9412 {
9413 case BFD_RELOC_IA64_DIR32MSB:
9414 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9415 adjust = 1;
9416 break;
9417
9418 case BFD_RELOC_IA64_DIR32LSB:
9419 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9420 adjust = 1;
9421 break;
9422
9423 case BFD_RELOC_IA64_DIR64MSB:
9424 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9425 adjust = 1;
9426 break;
9427
9428 case BFD_RELOC_IA64_DIR64LSB:
9429 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9430 adjust = 1;
9431 break;
9432
9433 default:
9434 break;
9435 }
9436 }
9437 if (fix->fx_addsy)
9438 {
9439 switch (fix->fx_r_type)
9440 {
9441 case 0:
9442 as_bad_where (fix->fx_file, fix->fx_line,
9443 "%s must have a constant value",
9444 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9445 break;
9446
9447 default:
9448 break;
9449 }
9450
9451 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
542d6675 9452 work. There should be a better way to handle this. */
800eeca4
JW		 9453 if (adjust)
9454 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9455 }
9456 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9457 {
9458 if (fix->tc_fix_data.bigendian)
9459 number_to_chars_bigendian (fixpos, value, fix->fx_size);
9460 else
9461 number_to_chars_littleendian (fixpos, value, fix->fx_size);
9462 fix->fx_done = 1;
9463 return 1;
9464 }
9465 else
9466 {
9467 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
9468 fix->fx_done = 1;
9469 return 1;
9470 }
9471 return 1;
9472}
9473
9474/* Generate the BFD reloc to be stuck in the object file from the
9475 fixup used internally in the assembler. */
542d6675
KH		 9476
9477arelent *
800eeca4
JW		 9478tc_gen_reloc (sec, fixp)
9479 asection *sec;
9480 fixS *fixp;
9481{
9482 arelent *reloc;
9483
9484 reloc = xmalloc (sizeof (*reloc));
9485 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9486 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9487 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9488 reloc->addend = fixp->fx_offset;
9489 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9490
9491 if (!reloc->howto)
9492 {
9493 as_bad_where (fixp->fx_file, fixp->fx_line,
9494 "Cannot represent %s relocation in object file",
9495 bfd_get_reloc_code_name (fixp->fx_r_type));
9496 }
9497 return reloc;
9498}
9499
9500/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 9501 of type TYPE, and store the appropriate bytes in *LIT. The number
9502 of LITTLENUMS emitted is stored in *SIZE. An error message is
800eeca4
JW		 9503 returned, or NULL on OK. */
9504
9505#define MAX_LITTLENUMS 5
9506
542d6675 9507char *
800eeca4
JW		 9508md_atof (type, lit, size)
9509 int type;
9510 char *lit;
9511 int *size;
9512{
9513 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9514 LITTLENUM_TYPE *word;
9515 char *t;
9516 int prec;
9517
9518 switch (type)
9519 {
9520 /* IEEE floats */
9521 case 'f':
9522 case 'F':
9523 case 's':
9524 case 'S':
9525 prec = 2;
9526 break;
9527
9528 case 'd':
9529 case 'D':
9530 case 'r':
9531 case 'R':
9532 prec = 4;
9533 break;
9534
9535 case 'x':
9536 case 'X':
9537 case 'p':
9538 case 'P':
9539 prec = 5;
9540 break;
9541
9542 default:
9543 *size = 0;
9544 return "Bad call to MD_ATOF()";
9545 }
9546 t = atof_ieee (input_line_pointer, type, words);
9547 if (t)
9548 input_line_pointer = t;
9549 *size = prec * sizeof (LITTLENUM_TYPE);
9550
9551 for (word = words + prec - 1; prec--;)
9552 {
9553 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9554 lit += sizeof (LITTLENUM_TYPE);
9555 }
9556 return 0;
9557}
9558
9559/* Round up a section's size to the appropriate boundary. */
9560valueT
9561md_section_align (seg, size)
9562 segT seg;
9563 valueT size;
9564{
9565 int align = bfd_get_section_alignment (stdoutput, seg);
197865e8 9566 valueT mask = ((valueT) 1 << align) - 1;
800eeca4
JW		 9567
9568 return (size + mask) & ~mask;
9569}
9570
9571/* Handle ia64 specific semantics of the align directive. */
9572
9573int
9574ia64_md_do_align (n, fill, len, max)
9575 int n;
9576 const char *fill;
9577 int len;
9578 int max;
9579{
9580 /* Fill any pending bundle with nops. */
9581 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
9582 ia64_flush_insns ();
9583
9584 /* When we align code in a text section, emit a bundle of 3 nops instead of
9585 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9586 N is log base 2 of the requested alignment. */
9587 if (fill == NULL
9588 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
9589 && n > 4)
9590 {
9591 /* Use mfi bundle of nops with no stop bits. */
9592 static const unsigned char be_nop[]
9593 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9594 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9595 static const unsigned char le_nop[]
9596 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9597 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
197865e8 9598
800eeca4
JW		 9599 /* Make sure we are on a 16-byte boundary, in case someone has been
9600 putting data into a text section. */
9601 frag_align (4, 0, 0);
9602
9603 if (target_big_endian)
9604 frag_align_pattern (n, be_nop, 16, max);
9605 else
9606 frag_align_pattern (n, le_nop, 16, max);
9607 return 1;
9608 }
9609
9610 return 0;
9611}
GDB Binutils - Deliverables
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