projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
IA-64 ELF support.
[deliverable/binutils-gdb.git] / gas / config / tc-ia64.c
CommitLineData
800eeca4
JW		 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
35 .save
36 .vframe
37 - labels are wrong if automatic alignment is introduced
38 (e.g., checkout the second real10 definition in test-data.s)
39 - DV-related stuff:
40 <reg>.safe_across_calls and any other DV-related directives I don't
41 have documentation for.
42 verify mod-sched-brs reads/writes are checked/marked (and other
43 notes)
44
45 */
46
47#include "as.h"
48#include "dwarf2dbg.h"
49#include "subsegs.h"
50
51#include "opcode/ia64.h"
52
53#include "elf/ia64.h"
54
55#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
56#define MIN(a,b) ((a) < (b) ? (a) : (b))
57
58#define NUM_SLOTS 4
59#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
60#define CURR_SLOT md.slot[md.curr_slot]
61
62#define O_pseudo_fixup (O_max + 1)
63
64enum special_section
65 {
66 SPECIAL_SECTION_BSS = 0,
67 SPECIAL_SECTION_SBSS,
68 SPECIAL_SECTION_SDATA,
69 SPECIAL_SECTION_RODATA,
70 SPECIAL_SECTION_COMMENT,
71 SPECIAL_SECTION_UNWIND,
72 SPECIAL_SECTION_UNWIND_INFO
73 };
74
75enum reloc_func
76 {
77 FUNC_FPTR_RELATIVE,
78 FUNC_GP_RELATIVE,
79 FUNC_LT_RELATIVE,
80 FUNC_PLT_RELATIVE,
81 FUNC_SEC_RELATIVE,
82 FUNC_SEG_RELATIVE,
83 FUNC_LTV_RELATIVE,
84 FUNC_LT_FPTR_RELATIVE,
85 };
86
87enum reg_symbol
88 {
89 REG_GR = 0,
90 REG_FR = (REG_GR + 128),
91 REG_AR = (REG_FR + 128),
92 REG_CR = (REG_AR + 128),
93 REG_P = (REG_CR + 128),
94 REG_BR = (REG_P + 64),
95 REG_IP = (REG_BR + 8),
96 REG_CFM,
97 REG_PR,
98 REG_PR_ROT,
99 REG_PSR,
100 REG_PSR_L,
101 REG_PSR_UM,
102 /* The following are pseudo-registers for use by gas only. */
103 IND_CPUID,
104 IND_DBR,
105 IND_DTR,
106 IND_ITR,
107 IND_IBR,
108 IND_MEM,
109 IND_MSR,
110 IND_PKR,
111 IND_PMC,
112 IND_PMD,
113 IND_RR,
114 REG_NUM
115 };
116
117enum dynreg_type
118 {
119 DYNREG_GR = 0, /* dynamic general purpose register */
120 DYNREG_FR, /* dynamic floating point register */
121 DYNREG_PR, /* dynamic predicate register */
122 DYNREG_NUM_TYPES
123 };
124
125/* On the ia64, we can't know the address of a text label until the
126 instructions are packed into a bundle. To handle this, we keep
127 track of the list of labels that appear in front of each
128 instruction. */
129struct label_fix
130 {
131 struct label_fix *next;
132 struct symbol *sym;
133 };
134
135extern int target_big_endian;
136
137/* Characters which always start a comment. */
138const char comment_chars[] = "";
139
140/* Characters which start a comment at the beginning of a line. */
141const char line_comment_chars[] = "#";
142
143/* Characters which may be used to separate multiple commands on a
144 single line. */
145const char line_separator_chars[] = ";";
146
147/* Characters which are used to indicate an exponent in a floating
148 point number. */
149const char EXP_CHARS[] = "eE";
150
151/* Characters which mean that a number is a floating point constant,
152 as in 0d1.0. */
153const char FLT_CHARS[] = "rRsSfFdDxXpP";
154
155/* ia64-specific option processing: */
156
157const char *md_shortopts = "M:N:x::";
158
159struct option md_longopts[] =
160 {
161 { NULL, no_argument, NULL, 0}
162 };
163
164size_t md_longopts_size = sizeof (md_longopts);
165
166static struct
167 {
168 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
169 struct hash_control *reg_hash; /* register name hash table */
170 struct hash_control *dynreg_hash; /* dynamic register hash table */
171 struct hash_control *const_hash; /* constant hash table */
172 struct hash_control *entry_hash; /* code entry hint hash table */
173
174 symbolS *regsym[REG_NUM];
175
176 /* If X_op is != O_absent, the registername for the instruction's
177 qualifying predicate. If NULL, p0 is assumed for instructions
178 that are predicatable. */
179 expressionS qp;
180
181 unsigned int
182 manual_bundling : 1,
183 debug_dv: 1,
184 detect_dv: 1,
185 explicit_mode : 1, /* which mode we're in */
186 default_explicit_mode : 1, /* which mode is the default */
187 mode_explicitly_set : 1, /* was the current mode explicitly set? */
188 auto_align : 1;
189
190 /* Each bundle consists of up to three instructions. We keep
191 track of four most recent instructions so we can correctly set
192 the end_of_insn_group for the last instruction in a bundle. */
193 int curr_slot;
194 int num_slots_in_use;
195 struct slot
196 {
197 unsigned int
198 end_of_insn_group : 1,
199 manual_bundling_on : 1,
200 manual_bundling_off : 1;
201 signed char user_template; /* user-selected template, if any */
202 unsigned char qp_regno; /* qualifying predicate */
203 /* This duplicates a good fraction of "struct fix" but we
204 can't use a "struct fix" instead since we can't call
205 fix_new_exp() until we know the address of the instruction. */
206 int num_fixups;
207 struct insn_fix
208 {
209 bfd_reloc_code_real_type code;
210 enum ia64_opnd opnd; /* type of operand in need of fix */
211 unsigned int is_pcrel : 1; /* is operand pc-relative? */
212 expressionS expr; /* the value to be inserted */
213 }
214 fixup[2]; /* at most two fixups per insn */
215 struct ia64_opcode *idesc;
216 struct label_fix *label_fixups;
217 struct unw_rec_list *unwind_record; /* Unwind directive. */
218 expressionS opnd[6];
219 char *src_file;
220 unsigned int src_line;
221 struct dwarf2_line_info debug_line;
222 }
223 slot[NUM_SLOTS];
224
225 segT last_text_seg;
226
227 struct dynreg
228 {
229 struct dynreg *next; /* next dynamic register */
230 const char *name;
231 unsigned short base; /* the base register number */
232 unsigned short num_regs; /* # of registers in this set */
233 }
234 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
235
236 flagword flags; /* ELF-header flags */
237
238 struct mem_offset {
239 unsigned hint:1; /* is this hint currently valid? */
240 bfd_vma offset; /* mem.offset offset */
241 bfd_vma base; /* mem.offset base */
242 } mem_offset;
243
244 int path; /* number of alt. entry points seen */
245 const char **entry_labels; /* labels of all alternate paths in
246 the current DV-checking block. */
247 int maxpaths; /* size currently allocated for
248 entry_labels */
249 }
250md;
251
252/* application registers: */
253
254#define AR_K0 0
255#define AR_K7 7
256#define AR_RSC 16
257#define AR_BSP 17
258#define AR_BSPSTORE 18
259#define AR_RNAT 19
260#define AR_UNAT 36
261#define AR_FPSR 40
262#define AR_ITC 44
263
264static const struct
265 {
266 const char *name;
267 int regnum;
268 }
269ar[] =
270 {
271 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
272 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
273 {"ar.rsc", 16}, {"ar.bsp", 17},
274 {"ar.bspstore", 18}, {"ar.rnat", 19},
275 {"ar.fcr", 21}, {"ar.eflag", 24},
276 {"ar.csd", 25}, {"ar.ssd", 26},
277 {"ar.cflg", 27}, {"ar.fsr", 28},
278 {"ar.fir", 29}, {"ar.fdr", 30},
279 {"ar.ccv", 32}, {"ar.unat", 36},
280 {"ar.fpsr", 40}, {"ar.itc", 44},
281 {"ar.pfs", 64}, {"ar.lc", 65},
282 {"ar.ec", 66},
283 };
284
285#define CR_IPSR 16
286#define CR_ISR 17
287#define CR_IIP 19
288#define CR_IFA 20
289#define CR_ITIR 21
290#define CR_IIPA 22
291#define CR_IFS 23
292#define CR_IIM 24
293#define CR_IHA 25
294#define CR_IVR 65
295#define CR_TPR 66
296#define CR_EOI 67
297#define CR_IRR0 68
298#define CR_IRR3 71
299#define CR_LRR0 80
300#define CR_LRR1 81
301
302/* control registers: */
303static const struct
304 {
305 const char *name;
306 int regnum;
307 }
308cr[] =
309 {
310 {"cr.dcr", 0},
311 {"cr.itm", 1},
312 {"cr.iva", 2},
313 {"cr.pta", 8},
314 {"cr.gpta", 9},
315 {"cr.ipsr", 16},
316 {"cr.isr", 17},
317 {"cr.iip", 19},
318 {"cr.ifa", 20},
319 {"cr.itir", 21},
320 {"cr.iipa", 22},
321 {"cr.ifs", 23},
322 {"cr.iim", 24},
323 {"cr.iha", 25},
324 {"cr.lid", 64},
325 {"cr.ivr", 65},
326 {"cr.tpr", 66},
327 {"cr.eoi", 67},
328 {"cr.irr0", 68},
329 {"cr.irr1", 69},
330 {"cr.irr2", 70},
331 {"cr.irr3", 71},
332 {"cr.itv", 72},
333 {"cr.pmv", 73},
334 {"cr.cmcv", 74},
335 {"cr.lrr0", 80},
336 {"cr.lrr1", 81}
337 };
338
339#define PSR_MFL 4
340#define PSR_IC 13
341#define PSR_DFL 18
342#define PSR_CPL 32
343
344static const struct const_desc
345 {
346 const char *name;
347 valueT value;
348 }
349const_bits[] =
350 {
351 /* PSR constant masks: */
352
353 /* 0: reserved */
354 {"psr.be", ((valueT) 1) << 1},
355 {"psr.up", ((valueT) 1) << 2},
356 {"psr.ac", ((valueT) 1) << 3},
357 {"psr.mfl", ((valueT) 1) << 4},
358 {"psr.mfh", ((valueT) 1) << 5},
359 /* 6-12: reserved */
360 {"psr.ic", ((valueT) 1) << 13},
361 {"psr.i", ((valueT) 1) << 14},
362 {"psr.pk", ((valueT) 1) << 15},
363 /* 16: reserved */
364 {"psr.dt", ((valueT) 1) << 17},
365 {"psr.dfl", ((valueT) 1) << 18},
366 {"psr.dfh", ((valueT) 1) << 19},
367 {"psr.sp", ((valueT) 1) << 20},
368 {"psr.pp", ((valueT) 1) << 21},
369 {"psr.di", ((valueT) 1) << 22},
370 {"psr.si", ((valueT) 1) << 23},
371 {"psr.db", ((valueT) 1) << 24},
372 {"psr.lp", ((valueT) 1) << 25},
373 {"psr.tb", ((valueT) 1) << 26},
374 {"psr.rt", ((valueT) 1) << 27},
375 /* 28-31: reserved */
376 /* 32-33: cpl (current privilege level) */
377 {"psr.is", ((valueT) 1) << 34},
378 {"psr.mc", ((valueT) 1) << 35},
379 {"psr.it", ((valueT) 1) << 36},
380 {"psr.id", ((valueT) 1) << 37},
381 {"psr.da", ((valueT) 1) << 38},
382 {"psr.dd", ((valueT) 1) << 39},
383 {"psr.ss", ((valueT) 1) << 40},
384 /* 41-42: ri (restart instruction) */
385 {"psr.ed", ((valueT) 1) << 43},
386 {"psr.bn", ((valueT) 1) << 44},
387 };
388
389/* indirect register-sets/memory: */
390
391static const struct
392 {
393 const char *name;
394 int regnum;
395 }
396indirect_reg[] =
397 {
398 { "CPUID", IND_CPUID },
399 { "cpuid", IND_CPUID },
400 { "dbr", IND_DBR },
401 { "dtr", IND_DTR },
402 { "itr", IND_ITR },
403 { "ibr", IND_IBR },
404 { "msr", IND_MSR },
405 { "pkr", IND_PKR },
406 { "pmc", IND_PMC },
407 { "pmd", IND_PMD },
408 { "rr", IND_RR },
409 };
410
411/* Pseudo functions used to indicate relocation types (these functions
412 start with an at sign (@). */
413static struct
414 {
415 const char *name;
416 enum pseudo_type
417 {
418 PSEUDO_FUNC_NONE,
419 PSEUDO_FUNC_RELOC,
420 PSEUDO_FUNC_CONST,
421 PSEUDO_FUNC_FLOAT
422 }
423 type;
424 union
425 {
426 unsigned long ival;
427 symbolS *sym;
428 }
429 u;
430 }
431pseudo_func[] =
432 {
433 /* reloc pseudo functions (these must come first!): */
434 { "fptr", PSEUDO_FUNC_RELOC },
435 { "gprel", PSEUDO_FUNC_RELOC },
436 { "ltoff", PSEUDO_FUNC_RELOC },
437 { "pltoff", PSEUDO_FUNC_RELOC },
438 { "secrel", PSEUDO_FUNC_RELOC },
439 { "segrel", PSEUDO_FUNC_RELOC },
440 { "ltv", PSEUDO_FUNC_RELOC },
441 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
442
443 /* mbtype4 constants: */
444 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
445 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
446 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
447 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
448 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
449
450 /* fclass constants: */
451 { "natval", PSEUDO_FUNC_CONST, { 0x100 } },
452 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
453 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
454 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
455 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
456 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
457 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
458 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
459 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
460 };
461
462/* 41-bit nop opcodes (one per unit): */
463static const bfd_vma nop[IA64_NUM_UNITS] =
464 {
465 0x0000000000LL, /* NIL => break 0 */
466 0x0008000000LL, /* I-unit nop */
467 0x0008000000LL, /* M-unit nop */
468 0x4000000000LL, /* B-unit nop */
469 0x0008000000LL, /* F-unit nop */
470 0x0008000000LL, /* L-"unit" nop */
471 0x0008000000LL, /* X-unit nop */
472 };
473
474/* Can't be `const' as it's passed to input routines (which have the
475 habit of setting temporary sentinels. */
476static char special_section_name[][20] =
477 {
478 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
479 {".IA_64.unwind"}, {".IA_64.unwind_info"}
480 };
481
482/* The best template for a particular sequence of up to three
483 instructions: */
484#define N IA64_NUM_TYPES
485static unsigned char best_template[N][N][N];
486#undef N
487
488/* Resource dependencies currently in effect */
489static struct rsrc {
490 int depind; /* dependency index */
491 const struct ia64_dependency *dependency; /* actual dependency */
492 unsigned specific:1, /* is this a specific bit/regno? */
493 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
494 int index; /* specific regno/bit within dependency */
495 int note; /* optional qualifying note (0 if none) */
496#define STATE_NONE 0
497#define STATE_STOP 1
498#define STATE_SRLZ 2
499 int insn_srlz; /* current insn serialization state */
500 int data_srlz; /* current data serialization state */
501 int qp_regno; /* qualifying predicate for this usage */
502 char *file; /* what file marked this dependency */
503 int line; /* what line marked this dependency */
504 struct mem_offset mem_offset; /* optional memory offset hint */
505 int path; /* corresponding code entry index */
506} *regdeps = NULL;
507static int regdepslen = 0;
508static int regdepstotlen = 0;
509static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
510static const char *dv_sem[] = { "none", "implied", "impliedf",
511 "data", "instr", "specific", "other" };
512
513/* Current state of PR mutexation */
514static struct qpmutex {
515 valueT prmask;
516 int path;
517} *qp_mutexes = NULL; /* QP mutex bitmasks */
518static int qp_mutexeslen = 0;
519static int qp_mutexestotlen = 0;
520static valueT qp_safe_across_calls = 0;
521
522/* Current state of PR implications */
523static struct qp_imply {
524 unsigned p1:6;
525 unsigned p2:6;
526 unsigned p2_branched:1;
527 int path;
528} *qp_implies = NULL;
529static int qp_implieslen = 0;
530static int qp_impliestotlen = 0;
531
532/* Keep track of static GR values so that indirect register usage can
533 sometimes be tracked. */
534static struct gr {
535 unsigned known:1;
536 int path;
537 valueT value;
538} gr_values[128] = {{ 1, 0 }};
539
540/* These are the routines required to output the various types of
541 unwind records. */
542
543typedef struct unw_rec_list {
544 unwind_record r;
545 unsigned long slot_number;
546 struct unw_rec_list *next;
547} unw_rec_list;
548
549#define SLOT_NUM_NOT_SET -1
550
551/* TRUE if processing unwind directives in a prologue region. */
552static int unwind_prologue = 0;
553
554/* Maintain a list of unwind entries for the current function. */
555static unw_rec_list *unwind_list = 0;
556static unw_rec_list *unwind_tail = 0;
557
558/* Any unwind entires that should be attached to the current
559 slot that an insn is being constructed for. */
560static unw_rec_list *current_unwind_entry = 0;
561
562/* These are used to create the unwind table entry for this function. */
563static symbolS *proc_start = 0;
564static symbolS *proc_end = 0;
565static symbolS *unwind_info = 0;
566static symbolS *personality_routine = 0;
567
568typedef void (*vbyte_func) PARAMS ((int, char *, char *));
569
570/* Forward delarations: */
571static int ar_is_in_integer_unit PARAMS ((int regnum));
572static void set_section PARAMS ((char *name));
573static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
574 unsigned int, unsigned int));
575static void dot_radix PARAMS ((int));
576static void dot_special_section PARAMS ((int));
577static void dot_proc PARAMS ((int));
578static void dot_fframe PARAMS ((int));
579static void dot_vframe PARAMS ((int));
580static void dot_save PARAMS ((int));
581static void dot_restore PARAMS ((int));
582static void dot_handlerdata PARAMS ((int));
583static void dot_unwentry PARAMS ((int));
584static void dot_altrp PARAMS ((int));
585static void dot_savesp PARAMS ((int));
586static void dot_savepsp PARAMS ((int));
587static void dot_saveg PARAMS ((int));
588static void dot_savef PARAMS ((int));
589static void dot_saveb PARAMS ((int));
590static void dot_savegf PARAMS ((int));
591static void dot_spill PARAMS ((int));
592static void dot_unwabi PARAMS ((int));
593static void dot_personality PARAMS ((int));
594static void dot_body PARAMS ((int));
595static void dot_prologue PARAMS ((int));
596static void dot_endp PARAMS ((int));
597static void dot_template PARAMS ((int));
598static void dot_regstk PARAMS ((int));
599static void dot_rot PARAMS ((int));
600static void dot_byteorder PARAMS ((int));
601static void dot_psr PARAMS ((int));
602static void dot_alias PARAMS ((int));
603static void dot_ln PARAMS ((int));
604static char *parse_section_name PARAMS ((void));
605static void dot_xdata PARAMS ((int));
606static void stmt_float_cons PARAMS ((int));
607static void stmt_cons_ua PARAMS ((int));
608static void dot_xfloat_cons PARAMS ((int));
609static void dot_xstringer PARAMS ((int));
610static void dot_xdata_ua PARAMS ((int));
611static void dot_xfloat_cons_ua PARAMS ((int));
612static void dot_pred_rel PARAMS ((int));
613static void dot_reg_val PARAMS ((int));
614static void dot_dv_mode PARAMS ((int));
615static void dot_entry PARAMS ((int));
616static void dot_mem_offset PARAMS ((int));
617static symbolS* declare_register PARAMS ((const char *name, int regnum));
618static void declare_register_set PARAMS ((const char *, int, int));
619static unsigned int operand_width PARAMS ((enum ia64_opnd));
620static int operand_match PARAMS ((const struct ia64_opcode *idesc,
621 int index, expressionS *e));
622static int parse_operand PARAMS ((expressionS *e));
623static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
624static void build_insn PARAMS ((struct slot *, bfd_vma *));
625static void emit_one_bundle PARAMS ((void));
626static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
627static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
628 bfd_reloc_code_real_type r_type));
629static void insn_group_break PARAMS ((int, int, int));
630static void add_qp_mutex PARAMS((valueT mask));
631static void add_qp_imply PARAMS((int p1, int p2));
632static void clear_qp_branch_flag PARAMS((valueT mask));
633static void clear_qp_mutex PARAMS((valueT mask));
634static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
635static void clear_register_values PARAMS ((void));
636static void print_dependency PARAMS ((const char *action, int depind));
637static int is_conditional_branch PARAMS ((struct ia64_opcode *));
638static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
639static int check_dv PARAMS((struct ia64_opcode *idesc));
640static void check_dependencies PARAMS((struct ia64_opcode *));
641static void mark_resources PARAMS((struct ia64_opcode *));
642static void update_dependencies PARAMS((struct ia64_opcode *));
643static void note_register_values PARAMS((struct ia64_opcode *));
644static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
645static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
646static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
647
648/* Determine if application register REGNUM resides in the integer
649 unit (as opposed to the memory unit). */
650static int
651ar_is_in_integer_unit (reg)
652 int reg;
653{
654 reg -= REG_AR;
655
656 return (reg == 64 /* pfs */
657 || reg == 65 /* lc */
658 || reg == 66 /* ec */
659 /* ??? ias accepts and puts these in the integer unit. */
660 || (reg >= 112 && reg <= 127));
661}
662
663/* Switch to section NAME and create section if necessary. It's
664 rather ugly that we have to manipulate input_line_pointer but I
665 don't see any other way to accomplish the same thing without
666 changing obj-elf.c (which may be the Right Thing, in the end). */
667static void
668set_section (name)
669 char *name;
670{
671 char *saved_input_line_pointer;
672
673 saved_input_line_pointer = input_line_pointer;
674 input_line_pointer = name;
675 obj_elf_section (0);
676 input_line_pointer = saved_input_line_pointer;
677}
678
679/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
680
681flagword
682ia64_elf_section_flags (flags, attr, type)
683 flagword flags;
684 int attr, type;
685{
686 if (attr & SHF_IA_64_SHORT)
687 flags |= SEC_SMALL_DATA;
688 return flags;
689}
690
691static unsigned int
692set_regstack (ins, locs, outs, rots)
693 unsigned int ins, locs, outs, rots;
694{
695 unsigned int sof; /* size of frame */
696
697 sof = ins + locs + outs;
698 if (sof > 96)
699 {
700 as_bad ("Size of frame exceeds maximum of 96 registers");
701 return 0;
702 }
703 if (rots > sof)
704 {
705 as_warn ("Size of rotating registers exceeds frame size");
706 return 0;
707 }
708 md.in.base = REG_GR + 32;
709 md.loc.base = md.in.base + ins;
710 md.out.base = md.loc.base + locs;
711
712 md.in.num_regs = ins;
713 md.loc.num_regs = locs;
714 md.out.num_regs = outs;
715 md.rot.num_regs = rots;
716 return sof;
717}
718
719void
720ia64_flush_insns ()
721{
722 struct label_fix *lfix;
723 segT saved_seg;
724 subsegT saved_subseg;
725
726 if (!md.last_text_seg)
727 return;
728
729 saved_seg = now_seg;
730 saved_subseg = now_subseg;
731
732 subseg_set (md.last_text_seg, 0);
733
734 while (md.num_slots_in_use > 0)
735 emit_one_bundle (); /* force out queued instructions */
736
737 /* In case there are labels following the last instruction, resolve
738 those now: */
739 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
740 {
741 S_SET_VALUE (lfix->sym, frag_now_fix ());
742 symbol_set_frag (lfix->sym, frag_now);
743 }
744 CURR_SLOT.label_fixups = 0;
745
746 subseg_set (saved_seg, saved_subseg);
747}
748
749void
750ia64_do_align (nbytes)
751 int nbytes;
752{
753 char *saved_input_line_pointer = input_line_pointer;
754
755 input_line_pointer = "";
756 s_align_bytes (nbytes);
757 input_line_pointer = saved_input_line_pointer;
758}
759
760void
761ia64_cons_align (nbytes)
762 int nbytes;
763{
764 if (md.auto_align)
765 {
766 char *saved_input_line_pointer = input_line_pointer;
767 input_line_pointer = "";
768 s_align_bytes (nbytes);
769 input_line_pointer = saved_input_line_pointer;
770 }
771}
772
773/* Output COUNT bytes to a memory location. */
774static unsigned char *vbyte_mem_ptr = NULL;
775
776void
777output_vbyte_mem (count, ptr, comment)
778 int count;
779 char *ptr;
780 char *comment;
781{
782 int x;
783 if (vbyte_mem_ptr == NULL)
784 abort ();
785
786 if (count == 0)
787 return;
788 for (x = 0; x < count; x++)
789 *(vbyte_mem_ptr++) = ptr[x];
790}
791
792/* Count the number of bytes required for records. */
793static int vbyte_count = 0;
794void
795count_output (count, ptr, comment)
796 int count;
797 char *ptr;
798 char *comment;
799{
800 vbyte_count += count;
801}
802
803static void
804output_R1_format (f, rtype, rlen)
805 vbyte_func f;
806 unw_record_type rtype;
807 int rlen;
808{
809 int r;
810 char byte;
811 if (rlen > 0x1f)
812 {
813 output_R3_format (f, rtype, rlen);
814 return;
815 }
816 if (rtype == prologue)
817 r = 0;
818 else
819 if (rtype == body)
820 r = 1;
821 else
822 as_bad ("record type is not valid");
823
824 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
825 (*f) (1, &byte, NULL);
826}
827
828static void
829output_R2_format (f, mask, grsave, rlen)
830 vbyte_func f;
831 int mask, grsave;
832 unsigned long rlen;
833{
834 char bytes[20];
835 int count = 2;
836 mask = (mask & 0x0f);
837 grsave = (grsave & 0x7f);
838
839 bytes[0] = (UNW_R2 | (mask >> 1));
840 bytes[1] = (((mask & 0x01) << 7) | grsave);
841 count += output_leb128 (bytes + 2, rlen, 0);
842 (*f) (count, bytes, NULL);
843}
844
845static void
846output_R3_format (f, rtype, rlen)
847 vbyte_func f;
848 unw_record_type rtype;
849 unsigned long rlen;
850{
851 int r, count;
852 char bytes[20];
853 if (rlen <= 0x1f)
854 {
855 output_R1_format (f, rtype, rlen);
856 return;
857 }
858 if (rtype == prologue)
859 r = 0;
860 else
861 if (rtype == body)
862 r = 1;
863 else
864 as_bad ("record type is not valid");
865 bytes[0] = (UNW_R3 | r);
866 count = output_leb128 (bytes + 1, rlen, 0);
867 (*f) (count + 1, bytes, NULL);
868}
869
870static void
871output_P1_format (f, brmask)
872 vbyte_func f;
873 int brmask;
874{
875 char byte;
876 byte = UNW_P1 | (brmask & 0x1f);
877 (*f) (1, &byte, NULL);
878}
879
880static void
881output_P2_format (f, brmask, gr)
882 vbyte_func f;
883 int brmask;
884 int gr;
885{
886 char bytes[2];
887 brmask = (brmask & 0x1f);
888 bytes[0] = UNW_P2 | (brmask >> 1);
889 bytes[1] = (((brmask & 1) << 7) | gr);
890 (*f) (2, bytes, NULL);
891}
892
893static void
894output_P3_format (f, rtype, reg)
895 vbyte_func f;
896 unw_record_type rtype;
897 int reg;
898{
899 char bytes[2];
900 int r;
901 reg = (reg & 0x7f);
902 switch (rtype)
903 {
904 case psp_gr:
905 r = 0;
906 break;
907 case rp_gr:
908 r = 1;
909 break;
910 case pfs_gr:
911 r = 2;
912 break;
913 case preds_gr:
914 r = 3;
915 break;
916 case unat_gr:
917 r = 4;
918 break;
919 case lc_gr:
920 r = 5;
921 break;
922 case rp_br:
923 r = 6;
924 break;
925 case rnat_gr:
926 r = 7;
927 break;
928 case bsp_gr:
929 r = 8;
930 break;
931 case bspstore_gr:
932 r = 9;
933 break;
934 case fpsr_gr:
935 r = 10;
936 break;
937 case priunat_gr:
938 r = 11;
939 break;
940 default:
941 as_bad ("Invalid record type for P3 format.");
942 }
943 bytes[0] = (UNW_P3 | (r >> 1));
944 bytes[1] = (((r & 1) << 7) | reg);
945 (*f) (2, bytes, NULL);
946}
947
948
949static void
950output_P4_format (f, count, imask)
951 vbyte_func f;
952 int count;
953 char *imask;
954{
955 char *bytes;
956 bytes = alloca (count + 1);
957 bytes[0] = UNW_P4;
958 memcpy (bytes + 1, imask, count);
959 (*f) (count + 1, bytes, NULL);
960}
961
962static void
963output_P5_format (f, grmask, frmask)
964 vbyte_func f;
965 int grmask;
966 unsigned long frmask;
967{
968 char bytes[4];
969 grmask = (grmask & 0x0f);
970
971 bytes[0] = UNW_P5;
972 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
973 bytes[2] = ((frmask & 0x0000ff00) >> 8);
974 bytes[3] = (frmask & 0x000000ff);
975 (*f) (4, bytes, NULL);
976}
977
978static void
979output_P6_format (f, rtype, rmask)
980 vbyte_func f;
981 unw_record_type rtype;
982 int rmask;
983{
984 char byte;
985 int r;
986 if (rtype == fr_mem)
987 r = 0;
988 else
989 if (rtype == gr_mem)
990 r = 1;
991 else
992 as_bad ("Invalid record type for format P6");
993 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
994 (*f) (1, &byte, NULL);
995}
996
997static void
998output_P7_format (f, rtype, w1, w2)
999 vbyte_func f;
1000 unw_record_type rtype;
1001 unsigned long w1;
1002 unsigned long w2;
1003{
1004 char bytes[20];
1005 int count = 1;
1006 int r;
1007 count += output_leb128 (bytes + 1, w1, 0);
1008 switch (rtype)
1009 {
1010 case mem_stack_f:
1011 r = 0;
1012 count += output_leb128 (bytes + count, w2, 0);
1013 break;
1014 case mem_stack_v:
1015 r = 1;
1016 break;
1017 case spill_base:
1018 r = 2;
1019 break;
1020 case psp_sprel:
1021 r = 3;
1022 break;
1023 case rp_when:
1024 r = 4;
1025 break;
1026 case rp_psprel:
1027 r = 5;
1028 break;
1029 case pfs_when:
1030 r = 6;
1031 break;
1032 case pfs_psprel:
1033 r = 7;
1034 break;
1035 case preds_when:
1036 r = 8;
1037 break;
1038 case preds_psprel:
1039 r = 9;
1040 break;
1041 case lc_when:
1042 r = 10;
1043 break;
1044 case lc_psprel:
1045 r = 11;
1046 break;
1047 case unat_when:
1048 r = 12;
1049 break;
1050 case unat_psprel:
1051 r = 13;
1052 break;
1053 case fpsr_when:
1054 r = 14;
1055 break;
1056 case fpsr_psprel:
1057 r = 15;
1058 break;
1059 }
1060 bytes[0] = (UNW_P7 | r);
1061 (*f) (count, bytes, NULL);
1062}
1063
1064static void
1065output_P8_format (f, rtype, t)
1066 vbyte_func f;
1067 unw_record_type rtype;
1068 unsigned long t;
1069{
1070 char bytes[20];
1071 int r;
1072 int count = 2;
1073 bytes[0] = UNW_P8;
1074 switch (rtype)
1075 {
1076 case rp_sprel:
1077 r = 1;
1078 break;
1079 case pfs_sprel:
1080 r = 2;
1081 break;
1082 case preds_sprel:
1083 r = 3;
1084 break;
1085 case lc_sprel:
1086 r = 4;
1087 break;
1088 case unat_sprel:
1089 r = 5;
1090 break;
1091 case fpsr_sprel:
1092 r = 6;
1093 break;
1094 case bsp_when:
1095 r = 7;
1096 break;
1097 case bsp_psprel:
1098 r = 8;
1099 break;
1100 case bsp_sprel:
1101 r = 9;
1102 break;
1103 case bspstore_when:
1104 r = 10;
1105 break;
1106 case bspstore_psprel:
1107 r = 11;
1108 break;
1109 case bspstore_sprel:
1110 r = 12;
1111 break;
1112 case rnat_when:
1113 r = 13;
1114 break;
1115 case rnat_psprel:
1116 r = 14;
1117 break;
1118 case rnat_sprel:
1119 r = 15;
1120 break;
1121 case priunat_when_gr:
1122 r = 16;
1123 break;
1124 case priunat_psprel:
1125 r = 17;
1126 break;
1127 case priunat_sprel:
1128 r = 18;
1129 break;
1130 case priunat_when_mem:
1131 r = 19;
1132 break;
1133 }
1134 bytes[1] = r;
1135 count += output_leb128 (bytes + 2, t, 0);
1136 (*f) (count, bytes, NULL);
1137}
1138
1139static void
1140output_P9_format (f, grmask, gr)
1141 vbyte_func f;
1142 int grmask;
1143 int gr;
1144{
1145 char bytes[3];
1146 bytes[0] = UNW_P9;
1147 bytes[1] = (grmask & 0x0f);
1148 bytes[2] = (gr & 0x7f);
1149 (*f) (3, bytes, NULL);
1150}
1151
1152static void
1153output_P10_format (f, abi, context)
1154 vbyte_func f;
1155 int abi;
1156 int context;
1157{
1158 char bytes[3];
1159 bytes[0] = UNW_P10;
1160 bytes[1] = (abi & 0xff);
1161 bytes[2] = (context & 0xff);
1162 (*f) (3, bytes, NULL);
1163}
1164
1165static void
1166output_B1_format (f, rtype, label)
1167 vbyte_func f;
1168 unw_record_type rtype;
1169 unsigned long label;
1170{
1171 char byte;
1172 int r;
1173 if (label > 0x1f)
1174 {
1175 output_B4_format (f, rtype, label);
1176 return;
1177 }
1178 if (rtype == label_state)
1179 r = 0;
1180 else
1181 if (rtype == copy_state)
1182 r = 1;
1183 else
1184 as_bad ("Invalid record type for format B1");
1185
1186 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1187 (*f) (1, &byte, NULL);
1188}
1189
1190static void
1191output_B2_format (f, ecount, t)
1192 vbyte_func f;
1193 unsigned long ecount;
1194 unsigned long t;
1195{
1196 char bytes[20];
1197 int count = 1;
1198 if (ecount > 0x1f)
1199 {
1200 output_B3_format (f, ecount, t);
1201 return;
1202 }
1203 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1204 count += output_leb128 (bytes + 1, t, 0);
1205 (*f) (count, bytes, NULL);
1206}
1207
1208static void
1209output_B3_format (f, ecount, t)
1210 vbyte_func f;
1211 unsigned long ecount;
1212 unsigned long t;
1213{
1214 char bytes[20];
1215 int count = 1;
1216 if (ecount <= 0x1f)
1217 {
1218 output_B2_format (f, ecount, t);
1219 return;
1220 }
1221 bytes[0] = UNW_B3;
1222 count += output_leb128 (bytes + 1, t, 0);
1223 count += output_leb128 (bytes + count, ecount, 0);
1224 (*f) (count, bytes, NULL);
1225}
1226
1227static void
1228output_B4_format (f, rtype, label)
1229 vbyte_func f;
1230 unw_record_type rtype;
1231 unsigned long label;
1232{
1233 char bytes[20];
1234 int r;
1235 int count = 1;
1236 if (label <= 0x1f)
1237 {
1238 output_B1_format (f, rtype, label);
1239 return;
1240 }
1241 if (rtype == label_state)
1242 r = 0;
1243 else
1244 if (rtype == copy_state)
1245 r = 1;
1246 else
1247 as_bad ("Invalid record type for format B1");
1248
1249 bytes[0] = (UNW_B4 | (r << 3));
1250 count += output_leb128 (bytes + 1, label, 0);
1251 (*f) (count, bytes, NULL);
1252}
1253
1254static char
1255format_a_b_reg (a, b, reg)
1256 int a, b;
1257 int reg;
1258{
1259 int ret;
1260 a = (a & 1);
1261 b = (b & 1);
1262 reg = (reg & 0x1f);
1263 ret = (a << 6) | (a << 5) | reg;
1264 return ret;
1265}
1266
1267static void
1268output_X1_format (f, rtype, a, b, reg, t, w1)
1269 vbyte_func f;
1270 unw_record_type rtype;
1271 int a, b, reg;
1272 unsigned long t;
1273 unsigned long w1;
1274{
1275 char bytes[20];
1276 int r;
1277 int count = 2;
1278 bytes[0] = UNW_X1;
1279 if (rtype == spill_psprel)
1280 r = 0;
1281 else
1282 if (rtype = spill_sprel)
1283 r = 1;
1284 else
1285 as_bad ("Invalid record type for format X1");
1286 bytes[1] = ((r << 7) | format_a_b_reg (a, b, reg));
1287 count += output_leb128 (bytes + 2, t, 0);
1288 count += output_leb128 (bytes + count, w1, 0);
1289 (*f) (count, bytes, NULL);
1290}
1291
1292static void
1293output_X2_format (f, a, b, reg, x, y, treg, t)
1294 vbyte_func f;
1295 int a, b, reg;
1296 int x, y, treg;
1297 unsigned long t;
1298{
1299 char bytes[20];
1300 int r;
1301 int count = 3;
1302 bytes[0] = UNW_X2;
1303 bytes[1] = (((x & 1) << 7) | format_a_b_reg (a, b, reg));
1304 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1305 count += output_leb128 (bytes + 3, t, 0);
1306 (*f) (count, bytes, NULL);
1307}
1308
1309static void
1310output_X3_format (f, rtype, qp, a, b, reg, t, w1)
1311 vbyte_func f;
1312 unw_record_type rtype;
1313 int qp;
1314 int a, b, reg;
1315 unsigned long t;
1316 unsigned long w1;
1317{
1318 char bytes[20];
1319 int r;
1320 int count = 3;
1321 bytes[0] = UNW_X1;
1322 if (rtype == spill_psprel_p)
1323 r = 0;
1324 else
1325 if (rtype = spill_sprel_p)
1326 r = 1;
1327 else
1328 as_bad ("Invalid record type for format X1");
1329 bytes[1] = ((r << 7) | (qp & 0x3f));
1330 bytes[2] = format_a_b_reg (a, b, reg);
1331 count += output_leb128 (bytes + 3, t, 0);
1332 count += output_leb128 (bytes + count, w1, 0);
1333 (*f) (count, bytes, NULL);
1334}
1335
1336static void
1337output_X4_format (f, qp, a, b, reg, x, y, treg, t)
1338 vbyte_func f;
1339 int qp;
1340 int a, b, reg;
1341 int x, y, treg;
1342 unsigned long t;
1343{
1344 char bytes[20];
1345 int r;
1346 int count = 4;
1347 bytes[0] = UNW_X2;
1348 bytes[1] = (qp & 0x3f);
1349 bytes[2] = (((x & 1) << 7) | format_a_b_reg (a, b, reg));
1350 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1351 count += output_leb128 (bytes + 4, t, 0);
1352 (*f) (count, bytes, NULL);
1353}
1354
1355/* This function allocates a record list structure, and initializes fields. */
1356static unw_rec_list *
1357alloc_record (unw_record_type t)
1358{
1359 unw_rec_list *ptr;
1360 ptr = xmalloc (sizeof (*ptr));
1361 ptr->next = NULL;
1362 ptr->slot_number = SLOT_NUM_NOT_SET;
1363 ptr->r.type = t;
1364 return ptr;
1365}
1366
1367/* This function frees a record list structure. */
1368static void
1369free_record (unw_rec_list *ptr)
1370{
1371 free (ptr);
1372}
1373
1374/* This function frees an entire list of record structures. */
1375void
1376free_list_records (unw_rec_list *first)
1377{
1378 unw_rec_list *ptr;
1379 for (ptr = first; ptr != NULL; )
1380 {
1381 unw_rec_list *tmp = ptr;
1382 ptr = ptr->next;
1383 free (tmp);
1384 }
1385}
1386
1387static unw_rec_list *
1388output_prologue ()
1389{
1390 unw_rec_list *ptr = alloc_record (prologue);
1391 return ptr;
1392}
1393
1394static unw_rec_list *
1395output_prologue_gr (saved_mask, reg)
1396 unsigned int saved_mask;
1397 unsigned int reg;
1398{
1399 unw_rec_list *ptr = alloc_record (prologue_gr);
1400 ptr->r.record.r.mask = saved_mask;
1401 ptr->r.record.r.grsave = reg;
1402 return ptr;
1403}
1404
1405static unw_rec_list *
1406output_body ()
1407{
1408 unw_rec_list *ptr = alloc_record (body);
1409 return ptr;
1410}
1411
1412static unw_rec_list *
1413output_mem_stack_f (size)
1414 unsigned int size;
1415{
1416 unw_rec_list *ptr = alloc_record (mem_stack_f);
1417 ptr->r.record.p.size = size;
1418 return ptr;
1419}
1420
1421static unw_rec_list *
1422output_mem_stack_v ()
1423{
1424 unw_rec_list *ptr = alloc_record (mem_stack_v);
1425 return ptr;
1426}
1427
1428static unw_rec_list *
1429output_psp_gr (gr)
1430 unsigned int gr;
1431{
1432 unw_rec_list *ptr = alloc_record (psp_gr);
1433 ptr->r.record.p.gr = gr;
1434 return ptr;
1435}
1436
1437static unw_rec_list *
1438output_psp_sprel (offset)
1439 unsigned int offset;
1440{
1441 unw_rec_list *ptr = alloc_record (psp_sprel);
1442 ptr->r.record.p.spoff = offset;
1443 return ptr;
1444}
1445
1446static unw_rec_list *
1447output_rp_when ()
1448{
1449 unw_rec_list *ptr = alloc_record (rp_when);
1450 return ptr;
1451}
1452
1453static unw_rec_list *
1454output_rp_gr (gr)
1455 unsigned int gr;
1456{
1457 unw_rec_list *ptr = alloc_record (rp_gr);
1458 ptr->r.record.p.gr = gr;
1459 return ptr;
1460}
1461
1462static unw_rec_list *
1463output_rp_br (br)
1464 unsigned int br;
1465{
1466 unw_rec_list *ptr = alloc_record (rp_br);
1467 ptr->r.record.p.br = br;
1468 return ptr;
1469}
1470
1471static unw_rec_list *
1472output_rp_psprel (offset)
1473 unsigned int offset;
1474{
1475 unw_rec_list *ptr = alloc_record (rp_psprel);
1476 ptr->r.record.p.pspoff = offset;
1477 return ptr;
1478}
1479
1480static unw_rec_list *
1481output_rp_sprel (offset)
1482 unsigned int offset;
1483{
1484 unw_rec_list *ptr = alloc_record (rp_sprel);
1485 ptr->r.record.p.spoff = offset;
1486 return ptr;
1487}
1488
1489static unw_rec_list *
1490output_pfs_when ()
1491{
1492 unw_rec_list *ptr = alloc_record (pfs_when);
1493 return ptr;
1494}
1495
1496static unw_rec_list *
1497output_pfs_gr (gr)
1498 unsigned int gr;
1499{
1500 unw_rec_list *ptr = alloc_record (pfs_gr);
1501 ptr->r.record.p.gr = gr;
1502 return ptr;
1503}
1504
1505static unw_rec_list *
1506output_pfs_psprel (offset)
1507 unsigned int offset;
1508{
1509 unw_rec_list *ptr = alloc_record (pfs_psprel);
1510 ptr->r.record.p.pspoff = offset;
1511 return ptr;
1512}
1513
1514static unw_rec_list *
1515output_pfs_sprel (offset)
1516 unsigned int offset;
1517{
1518 unw_rec_list *ptr = alloc_record (pfs_sprel);
1519 ptr->r.record.p.spoff = offset;
1520 return ptr;
1521}
1522
1523static unw_rec_list *
1524output_preds_when ()
1525{
1526 unw_rec_list *ptr = alloc_record (preds_when);
1527 return ptr;
1528}
1529
1530static unw_rec_list *
1531output_preds_gr (gr)
1532 unsigned int gr;
1533{
1534 unw_rec_list *ptr = alloc_record (preds_gr);
1535 ptr->r.record.p.gr = gr;
1536 return ptr;
1537}
1538
1539static unw_rec_list *
1540output_preds_psprel (offset)
1541 unsigned int offset;
1542{
1543 unw_rec_list *ptr = alloc_record (preds_psprel);
1544 ptr->r.record.p.pspoff = offset;
1545 return ptr;
1546}
1547
1548static unw_rec_list *
1549output_preds_sprel (offset)
1550 unsigned int offset;
1551{
1552 unw_rec_list *ptr = alloc_record (preds_sprel);
1553 ptr->r.record.p.spoff = offset;
1554 return ptr;
1555}
1556
1557static unw_rec_list *
1558output_fr_mem (mask)
1559 unsigned int mask;
1560{
1561 unw_rec_list *ptr = alloc_record (fr_mem);
1562 ptr->r.record.p.rmask = mask;
1563 return ptr;
1564}
1565
1566static unw_rec_list *
1567output_frgr_mem (gr_mask, fr_mask)
1568 unsigned int gr_mask;
1569 unsigned int fr_mask;
1570{
1571 unw_rec_list *ptr = alloc_record (frgr_mem);
1572 ptr->r.record.p.grmask = gr_mask;
1573 ptr->r.record.p.frmask = fr_mask;
1574 return ptr;
1575}
1576
1577static unw_rec_list *
1578output_gr_gr (mask, reg)
1579 unsigned int mask;
1580 unsigned int reg;
1581{
1582 unw_rec_list *ptr = alloc_record (gr_gr);
1583 ptr->r.record.p.grmask = mask;
1584 ptr->r.record.p.gr = reg;
1585 return ptr;
1586}
1587
1588static unw_rec_list *
1589output_gr_mem (mask)
1590 unsigned int mask;
1591{
1592 unw_rec_list *ptr = alloc_record (gr_mem);
1593 ptr->r.record.p.rmask = mask;
1594 return ptr;
1595}
1596
1597static unw_rec_list *
1598output_br_mem (unsigned int mask)
1599{
1600 unw_rec_list *ptr = alloc_record (br_mem);
1601 ptr->r.record.p.brmask = mask;
1602 return ptr;
1603}
1604
1605static unw_rec_list *
1606output_br_gr (save_mask, reg)
1607 unsigned int save_mask;
1608 unsigned int reg;
1609{
1610 unw_rec_list *ptr = alloc_record (br_gr);
1611 ptr->r.record.p.brmask = save_mask;
1612 ptr->r.record.p.gr = reg;
1613 return ptr;
1614}
1615
1616static unw_rec_list *
1617output_spill_base (offset)
1618 unsigned int offset;
1619{
1620 unw_rec_list *ptr = alloc_record (spill_base);
1621 ptr->r.record.p.pspoff = offset;
1622 return ptr;
1623}
1624
1625static unw_rec_list *
1626output_spill_mask ()
1627{
1628/* TODO - how to implement this record.... I guess GAS could fill in the
1629 correct fields from the record list and construct one of these
1630 after the symbols have been resolved and we know how big the
1631 region is. This could be done in fixup_unw_records. */
1632 unw_rec_list *ptr = NULL;
1633 return ptr;
1634}
1635
1636static unw_rec_list *
1637output_unat_when ()
1638{
1639 unw_rec_list *ptr = alloc_record (unat_when);
1640 return ptr;
1641}
1642
1643static unw_rec_list *
1644output_unat_gr (gr)
1645 unsigned int gr;
1646{
1647 unw_rec_list *ptr = alloc_record (unat_gr);
1648 ptr->r.record.p.gr = gr;
1649 return ptr;
1650}
1651
1652static unw_rec_list *
1653output_unat_psprel (offset)
1654 unsigned int offset;
1655{
1656 unw_rec_list *ptr = alloc_record (unat_psprel);
1657 ptr->r.record.p.pspoff = offset;
1658 return ptr;
1659}
1660
1661static unw_rec_list *
1662output_unat_sprel (offset)
1663 unsigned int offset;
1664{
1665 unw_rec_list *ptr = alloc_record (unat_sprel);
1666 ptr->r.record.p.spoff = offset;
1667 return ptr;
1668}
1669
1670static unw_rec_list *
1671output_lc_when ()
1672{
1673 unw_rec_list *ptr = alloc_record (lc_when);
1674 return ptr;
1675}
1676
1677static unw_rec_list *
1678output_lc_gr (gr)
1679 unsigned int gr;
1680{
1681 unw_rec_list *ptr = alloc_record (lc_gr);
1682 ptr->r.record.p.gr = gr;
1683 return ptr;
1684}
1685
1686static unw_rec_list *
1687output_lc_psprel (offset)
1688 unsigned int offset;
1689{
1690 unw_rec_list *ptr = alloc_record (lc_psprel);
1691 ptr->r.record.p.pspoff = offset;
1692 return ptr;
1693}
1694
1695static unw_rec_list *
1696output_lc_sprel (offset)
1697 unsigned int offset;
1698{
1699 unw_rec_list *ptr = alloc_record (lc_sprel);
1700 ptr->r.record.p.spoff = offset;
1701 return ptr;
1702}
1703
1704static unw_rec_list *
1705output_fpsr_when ()
1706{
1707 unw_rec_list *ptr = alloc_record (fpsr_when);
1708 return ptr;
1709}
1710
1711static unw_rec_list *
1712output_fpsr_gr (gr)
1713 unsigned int gr;
1714{
1715 unw_rec_list *ptr = alloc_record (fpsr_gr);
1716 ptr->r.record.p.gr = gr;
1717 return ptr;
1718}
1719
1720static unw_rec_list *
1721output_fpsr_psprel (offset)
1722 unsigned int offset;
1723{
1724 unw_rec_list *ptr = alloc_record (fpsr_psprel);
1725 ptr->r.record.p.pspoff = offset;
1726 return ptr;
1727}
1728
1729static unw_rec_list *
1730output_fpsr_sprel (offset)
1731 unsigned int offset;
1732{
1733 unw_rec_list *ptr = alloc_record (fpsr_sprel);
1734 ptr->r.record.p.spoff = offset;
1735 return ptr;
1736}
1737
1738static unw_rec_list *
1739output_priunat_when_gr ()
1740{
1741 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1742 return ptr;
1743}
1744
1745static unw_rec_list *
1746output_priunat_when_mem ()
1747{
1748 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1749 return ptr;
1750}
1751
1752static unw_rec_list *
1753output_priunat_gr (gr)
1754 unsigned int gr;
1755{
1756 unw_rec_list *ptr = alloc_record (priunat_gr);
1757 ptr->r.record.p.gr = gr;
1758 return ptr;
1759}
1760
1761static unw_rec_list *
1762output_priunat_psprel (offset)
1763 unsigned int offset;
1764{
1765 unw_rec_list *ptr = alloc_record (priunat_psprel);
1766 ptr->r.record.p.pspoff = offset;
1767 return ptr;
1768}
1769
1770static unw_rec_list *
1771output_priunat_sprel (offset)
1772 unsigned int offset;
1773{
1774 unw_rec_list *ptr = alloc_record (priunat_sprel);
1775 ptr->r.record.p.spoff = offset;
1776 return ptr;
1777}
1778
1779static unw_rec_list *
1780output_bsp_when ()
1781{
1782 unw_rec_list *ptr = alloc_record (bsp_when);
1783 return ptr;
1784}
1785
1786static unw_rec_list *
1787output_bsp_gr (gr)
1788 unsigned int gr;
1789{
1790 unw_rec_list *ptr = alloc_record (bsp_gr);
1791 ptr->r.record.p.gr = gr;
1792 return ptr;
1793}
1794
1795static unw_rec_list *
1796output_bsp_psprel (offset)
1797 unsigned int offset;
1798{
1799 unw_rec_list *ptr = alloc_record (bsp_psprel);
1800 ptr->r.record.p.pspoff = offset;
1801 return ptr;
1802}
1803
1804static unw_rec_list *
1805output_bsp_sprel (offset)
1806 unsigned int offset;
1807{
1808 unw_rec_list *ptr = alloc_record (bsp_sprel);
1809 ptr->r.record.p.spoff = offset;
1810 return ptr;
1811}
1812
1813static unw_rec_list *
1814output_bspstore_when ()
1815{
1816 unw_rec_list *ptr = alloc_record (bspstore_when);
1817 return ptr;
1818}
1819
1820static unw_rec_list *
1821output_bspstore_gr (gr)
1822 unsigned int gr;
1823{
1824 unw_rec_list *ptr = alloc_record (bspstore_gr);
1825 ptr->r.record.p.gr = gr;
1826 return ptr;
1827}
1828
1829static unw_rec_list *
1830output_bspstore_psprel (offset)
1831 unsigned int offset;
1832{
1833 unw_rec_list *ptr = alloc_record (bspstore_psprel);
1834 ptr->r.record.p.pspoff = offset;
1835 return ptr;
1836}
1837
1838static unw_rec_list *
1839output_bspstore_sprel (offset)
1840 unsigned int offset;
1841{
1842 unw_rec_list *ptr = alloc_record (bspstore_sprel);
1843 ptr->r.record.p.spoff = offset;
1844 return ptr;
1845}
1846
1847static unw_rec_list *
1848output_rnat_when ()
1849{
1850 unw_rec_list *ptr = alloc_record (rnat_when);
1851 return ptr;
1852}
1853
1854static unw_rec_list *
1855output_rnat_gr (gr)
1856 unsigned int gr;
1857{
1858 unw_rec_list *ptr = alloc_record (rnat_gr);
1859 ptr->r.record.p.gr = gr;
1860 return ptr;
1861}
1862
1863static unw_rec_list *
1864output_rnat_psprel (offset)
1865 unsigned int offset;
1866{
1867 unw_rec_list *ptr = alloc_record (rnat_psprel);
1868 ptr->r.record.p.pspoff = offset;
1869 return ptr;
1870}
1871
1872static unw_rec_list *
1873output_rnat_sprel (offset)
1874 unsigned int offset;
1875{
1876 unw_rec_list *ptr = alloc_record (rnat_sprel);
1877 ptr->r.record.p.spoff = offset;
1878 return ptr;
1879}
1880
1881static unw_rec_list *
1882output_epilogue ()
1883{
1884 unw_rec_list *ptr = NULL;
1885 return ptr;
1886}
1887
1888static unw_rec_list *
1889output_label_state ()
1890{
1891 unw_rec_list *ptr = NULL;
1892 return ptr;
1893}
1894
1895static unw_rec_list *
1896output_copy_state ()
1897{
1898 unw_rec_list *ptr = NULL;
1899 return ptr;
1900}
1901
1902static unw_rec_list *
1903output_spill_psprel (reg, offset)
1904 unsigned int reg;
1905 unsigned int offset;
1906{
1907 unw_rec_list *ptr = alloc_record (spill_psprel);
1908 ptr->r.record.x.reg = reg;
1909 ptr->r.record.x.pspoff = offset;
1910 return ptr;
1911}
1912
1913static unw_rec_list *
1914output_spill_sprel (reg, offset)
1915 unsigned int reg;
1916 unsigned int offset;
1917{
1918 unw_rec_list *ptr = alloc_record (spill_sprel);
1919 ptr->r.record.x.reg = reg;
1920 ptr->r.record.x.spoff = offset;
1921 return ptr;
1922}
1923
1924static unw_rec_list *
1925output_spill_psprel_p (reg, offset, predicate)
1926 unsigned int reg;
1927 unsigned int offset;
1928 unsigned int predicate;
1929{
1930 unw_rec_list *ptr = alloc_record (spill_psprel_p);
1931 ptr->r.record.x.reg = reg;
1932 ptr->r.record.x.pspoff = offset;
1933 ptr->r.record.x.qp = predicate;
1934 return ptr;
1935}
1936
1937static unw_rec_list *
1938output_spill_sprel_p (reg, offset, predicate)
1939 unsigned int reg;
1940 unsigned int offset;
1941 unsigned int predicate;
1942{
1943 unw_rec_list *ptr = alloc_record (spill_sprel_p);
1944 ptr->r.record.x.reg = reg;
1945 ptr->r.record.x.spoff = offset;
1946 ptr->r.record.x.qp = predicate;
1947 return ptr;
1948}
1949
1950static unw_rec_list *
1951output_spill_reg (reg, targ_reg, xy)
1952 unsigned int reg;
1953 unsigned int targ_reg;
1954 unsigned int xy;
1955{
1956 unw_rec_list *ptr = alloc_record (spill_reg);
1957 ptr->r.record.x.reg = reg;
1958 ptr->r.record.x.treg = targ_reg;
1959 ptr->r.record.x.xy = xy;
1960 return ptr;
1961}
1962
1963static unw_rec_list *
1964output_spill_reg_p (reg, targ_reg, xy, predicate)
1965 unsigned int reg;
1966 unsigned int targ_reg;
1967 unsigned int xy;
1968 unsigned int predicate;
1969{
1970 unw_rec_list *ptr = alloc_record (spill_reg_p);
1971 ptr->r.record.x.reg = reg;
1972 ptr->r.record.x.treg = targ_reg;
1973 ptr->r.record.x.xy = xy;
1974 ptr->r.record.x.qp = predicate;
1975 return ptr;
1976}
1977
1978/* Given a unw_rec_list process the correct format with the
1979 specified function. */
1980static void
1981process_one_record (ptr, f)
1982 unw_rec_list *ptr;
1983 vbyte_func f;
1984{
1985 switch (ptr->r.type)
1986 {
1987 case prologue:
1988 case body:
1989 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
1990 break;
1991 case prologue_gr:
1992 output_R2_format (f, ptr->r.record.r.mask,
1993 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
1994 break;
1995 case mem_stack_f:
1996 case mem_stack_v:
1997 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
1998 ptr->r.record.p.size);
1999 break;
2000 case psp_gr:
2001 case rp_gr:
2002 case pfs_gr:
2003 case preds_gr:
2004 case unat_gr:
2005 case lc_gr:
2006 case fpsr_gr:
2007 case priunat_gr:
2008 case bsp_gr:
2009 case bspstore_gr:
2010 case rnat_gr:
2011 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2012 break;
2013 case rp_br:
2014 output_P3_format (f, rp_br, ptr->r.record.p.br);
2015 break;
2016 case psp_sprel:
2017 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2018 break;
2019 case rp_when:
2020 case pfs_when:
2021 case preds_when:
2022 case unat_when:
2023 case lc_when:
2024 case fpsr_when:
2025 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2026 break;
2027 case rp_psprel:
2028 case pfs_psprel:
2029 case preds_psprel:
2030 case unat_psprel:
2031 case lc_psprel:
2032 case fpsr_psprel:
2033 case spill_base:
2034 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2035 break;
2036 case rp_sprel:
2037 case pfs_sprel:
2038 case preds_sprel:
2039 case unat_sprel:
2040 case lc_sprel:
2041 case fpsr_sprel:
2042 case priunat_sprel:
2043 case bsp_sprel:
2044 case bspstore_sprel:
2045 case rnat_sprel:
2046 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2047 break;
2048 case fr_mem:
2049 case gr_mem:
2050 output_P6_format (f, ptr->r.type, ptr->r.record.p.rmask);
2051 break;
2052 case frgr_mem:
2053 output_P5_format (f, ptr->r.record.p.grmask, ptr->r.record.p.frmask);
2054 break;
2055 case gr_gr:
2056 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2057 break;
2058 case br_mem:
2059 output_P1_format (f, ptr->r.record.p.brmask);
2060 break;
2061 case br_gr:
2062 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2063 break;
2064 case spill_mask:
2065 as_bad ("spill_mask record unimplemented.");
2066 break;
2067 case priunat_when_gr:
2068 case priunat_when_mem:
2069 case bsp_when:
2070 case bspstore_when:
2071 case rnat_when:
2072 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2073 break;
2074 case priunat_psprel:
2075 case bsp_psprel:
2076 case bspstore_psprel:
2077 case rnat_psprel:
2078 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2079 break;
2080 case epilogue:
2081 as_bad ("epilogue record unimplemented.");
2082 break;
2083 case label_state:
2084 as_bad ("label_state record unimplemented.");
2085 break;
2086 case copy_state:
2087 as_bad ("copy_state record unimplemented.");
2088 break;
2089 case spill_psprel:
2090 case spill_sprel:
2091 case spill_reg:
2092 case spill_psprel_p:
2093 case spill_sprel_p:
2094 case spill_reg_p:
2095 as_bad ("spill_* record unimplemented.");
2096 break;
2097 default:
2098 as_bad ("record_type_not_valid");
2099 break;
2100 }
2101}
2102
2103/* Given a unw_rec_list list, process all the records with
2104 the specified function. */
2105static void
2106process_unw_records (list, f)
2107 unw_rec_list *list;
2108 vbyte_func f;
2109{
2110 unw_rec_list *ptr;
2111 for (ptr = list; ptr; ptr = ptr->next)
2112 process_one_record (ptr, f);
2113}
2114
2115/* Determine the size of a record list in bytes. */
2116static int
2117calc_record_size (list)
2118 unw_rec_list *list;
2119{
2120 vbyte_count = 0;
2121 process_unw_records (list, count_output);
2122 return vbyte_count;
2123}
2124
2125/* Given a complete record list, process any records which have
2126 unresolved fields, (ie length counts for a prologue). After
2127 this has been run, all neccessary information should be available
2128 within each record to generate an image. */
2129static void
2130fixup_unw_records (list)
2131 unw_rec_list *list;
2132{
2133 unw_rec_list *ptr;
2134 unsigned long first_addr = 0;
2135 for (ptr = list; ptr; ptr = ptr->next)
2136 {
2137 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2138 as_bad (" Insn slot not set in unwind record.");
2139 switch (ptr->r.type)
2140 {
2141 case prologue:
2142 case prologue_gr:
2143 case body:
2144 {
2145 unw_rec_list *last;
2146 int size;
2147 unsigned long last_addr;
2148 first_addr = ptr->slot_number;
2149 ptr->slot_number = 0;
2150 /* Find either the next body/prologue start, or the end of
2151 the list, and determine the size of the region. */
2152 for (last = ptr; last->next != NULL; last = last->next)
2153 if (last->next->r.type == prologue
2154 || last->next->r.type == prologue_gr
2155 || last->next->r.type == body)
2156 {
2157 break;
2158 }
2159 last_addr = last->slot_number;
2160 size = ((last_addr - first_addr) / 16) * 3 + last_addr % 4;
2161 ptr->r.record.r.rlen = size;
2162 break;
2163 }
2164 case mem_stack_f:
2165 case mem_stack_v:
2166 case rp_when:
2167 case pfs_when:
2168 case preds_when:
2169 case unat_when:
2170 case lc_when:
2171 case fpsr_when:
2172 case priunat_when_gr:
2173 case priunat_when_mem:
2174 case bsp_when:
2175 case bspstore_when:
2176 case rnat_when:
2177 {
2178 /* All the time fields. */
2179 int x = ptr->slot_number - first_addr;
2180 ptr->r.record.p.t = (x / 16) * 3 + (ptr->slot_number % 4);
2181 break;
2182 }
2183 /* TODO. We also need to combine all the register masks into a single
2184 record. (Ie, all the save.g save.gf, save.f and save.br's) */
2185 }
2186 }
2187}
2188
2189/* Generate an unwind image from a record list. Returns the number of
2190 bytes in the resulting image. The memory image itselof is returned
2191 in the 'ptr' parameter. */
2192static int
2193output_unw_records (list, ptr)
2194 unw_rec_list *list;
2195 void **ptr;
2196{
2197 int size, x, extra = 0;
2198 unsigned char *mem;
2199
2200 fixup_unw_records (list);
2201 size = calc_record_size (list);
2202
2203 /* pad to 8 byte boundry. */
2204 x = size % 8;
2205 if (x != 0)
2206 extra = 8 - x;
2207 /* Add 8 for the header + 8 more bytes for the personality offset. */
2208 mem = xmalloc (size + extra + 16);
2209
2210 vbyte_mem_ptr = mem + 8;
2211 /* Clear the padding area and personality. */
2212 memset (mem + 8 + size, 0 , extra + 8);
2213 /* Initialize the header area. */
2214 md_number_to_chars (mem, 1, 2); /* version number. */
2215 md_number_to_chars (mem + 2, 0x03, 2); /* Set E and U handler bits. */
2216
2217 /* Length in double words. */
2218 md_number_to_chars (mem + 4, (size + extra) / 8, 4);
2219
2220 process_unw_records (list, output_vbyte_mem);
2221
2222 *ptr = mem;
2223 return size + extra + 16;
2224}
2225
2226static void
2227dot_radix (dummy)
2228 int dummy;
2229{
2230 int radix;
2231
2232 SKIP_WHITESPACE ();
2233 radix = *input_line_pointer++;
2234
2235 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2236 {
2237 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2238 ignore_rest_of_line ();
2239 return;
2240 }
2241}
2242
2243/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2244static void
2245dot_special_section (which)
2246 int which;
2247{
2248 set_section ((char *) special_section_name[which]);
2249}
2250
2251static void
2252add_unwind_entry (ptr)
2253 unw_rec_list *ptr;
2254{
2255 if (unwind_tail)
2256 unwind_tail->next = ptr;
2257 else
2258 unwind_list = ptr;
2259 unwind_tail = ptr;
2260
2261 /* The current entry can in fact be a chain of unwind entries. */
2262 if (current_unwind_entry == NULL)
2263 current_unwind_entry = ptr;
2264}
2265
2266static void
2267dot_fframe (dummy)
2268 int dummy;
2269{
2270 expressionS e;
2271 parse_operand (&e);
2272
2273 if (e.X_op != O_constant)
2274 as_bad ("Operand to .fframe must be a constant");
2275 else
2276 {
2277 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2278 }
2279}
2280
2281static void
2282dot_vframe (dummy)
2283 int dummy;
2284{
2285 discard_rest_of_line ();
2286}
2287
2288static void
2289dot_save (dummy)
2290 int dummy;
2291{
2292 expressionS e1, e2;
2293 int sep;
2294 int reg1, reg2;
2295
2296 sep = parse_operand (&e1);
2297 if (sep != ',')
2298 as_bad ("No second operand to .save");
2299 sep = parse_operand (&e2);
2300
2301 reg1 = e1.X_add_number - REG_AR;
2302 reg2 = e2.X_add_number - REG_GR;
2303
2304 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2305 if (e1.X_op == O_register
2306 && ((reg1 >=0 && reg1 < 128) || reg1 == REG_BR - REG_AR))
2307 {
2308 if (e2.X_op == O_register && reg2 >=0 && reg2 < 128)
2309 {
2310 switch (reg1)
2311 {
2312 case 17: /* ar.bsp */
2313 add_unwind_entry (output_bsp_when ());
2314 add_unwind_entry (output_bsp_gr (reg2));
2315 break;
2316 case 18: /* ar.bspstore */
2317 add_unwind_entry (output_bspstore_when ());
2318 add_unwind_entry (output_bspstore_gr (reg2));
2319 break;
2320 case 19: /* ar.rnat */
2321 add_unwind_entry (output_rnat_when ());
2322 add_unwind_entry (output_rnat_gr (reg2));
2323 break;
2324 case 36: /* ar.unat */
2325 add_unwind_entry (output_unat_when ());
2326 add_unwind_entry (output_unat_gr (reg2));
2327 break;
2328 case 40: /* ar.fpsr */
2329 add_unwind_entry (output_fpsr_when ());
2330 add_unwind_entry (output_fpsr_gr (reg2));
2331 break;
2332 case 64: /* ar.pfs */
2333 add_unwind_entry (output_pfs_when ());
2334 add_unwind_entry (output_pfs_gr (reg2));
2335 break;
2336 case 65: /* ar.lc */
2337 add_unwind_entry (output_lc_when ());
2338 add_unwind_entry (output_lc_gr (reg2));
2339 break;
2340 case REG_BR - REG_AR: /* rp */
2341 add_unwind_entry (output_rp_when ());
2342 add_unwind_entry (output_rp_gr (reg2));
2343 break;
2344 default:
2345 as_bad ("first operand is unknown application register");
2346 }
2347 }
2348 else
2349 as_bad (" Second operand not a valid register");
2350 }
2351 else
2352 as_bad ("First operand not a valid register");
2353}
2354
2355static void
2356dot_restore (dummy)
2357 int dummy;
2358{
2359 discard_rest_of_line ();
2360}
2361
2362static int
2363generate_unwind_image ()
2364{
2365 int size;
2366 unsigned char *unw_rec;
2367 int x;
2368
2369 /* Generate the unwind record. */
2370 size = output_unw_records (unwind_list, &unw_rec);
2371 if (size % 4 != 0)
2372 as_bad ("Unwind record is ont a multiple of 4 bytes.");
2373
2374 /* If there are unwind records, switch sections, and output the info. */
2375 if (size != 0)
2376 {
2377 int x;
2378 unsigned char *where;
2379 unsigned char *personality;
2380 expressionS exp;
2381 char *save;
2382 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
2383
2384 /* Set expression which points to start of unwind descriptor area. */
2385 unwind_info = expr_build_dot ();
2386
2387 where = (unsigned char *)frag_more (size);
2388
2389 /* Issue a label for this address, and keep track of it to put it
2390 in the unwind section. */
2391
2392 /* Copy the information from the unwind record into this section. The
2393 data is already in the correct byte order. */
2394 memcpy (where, unw_rec, size);
2395 /* Add the personality address to the image. */
2396 if (personality_routine != 0)
2397 {
2398 exp.X_op = O_symbol;
2399 exp.X_add_symbol = personality_routine;
2400 exp.X_add_number = 0;
2401 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
2402 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
2403 personality_routine = 0;
2404 }
2405 obj_elf_previous (0);
2406 }
2407
2408 free_list_records (unwind_list);
2409 unwind_list = unwind_tail = current_unwind_entry = NULL;
2410
2411 return size;
2412}
2413
2414static void
2415dot_handlerdata (dummy)
2416 int dummy;
2417{
2418 generate_unwind_image ();
2419}
2420
2421static void
2422dot_unwentry (dummy)
2423 int dummy;
2424{
2425 discard_rest_of_line ();
2426}
2427
2428static void
2429dot_altrp (dummy)
2430 int dummy;
2431{
2432 discard_rest_of_line ();
2433}
2434
2435static void
2436dot_savesp (dummy)
2437 int dummy;
2438{
2439 expressionS e1, e2;
2440 int sep;
2441 int reg1, val;
2442
2443 sep = parse_operand (&e1);
2444 if (sep != ',')
2445 as_bad ("No second operand to .savesp");
2446 sep = parse_operand (&e2);
2447
2448 reg1 = e1.X_add_number - REG_AR;
2449 val = e2.X_add_number;
2450
2451 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2452 if (e1.X_op == O_register
2453 && ((reg1 >=0 && reg1 < 128) || reg1 == REG_BR - REG_AR || reg1 == REG_PR - REG_AR))
2454 {
2455 if (e2.X_op == O_constant)
2456 {
2457 switch (reg1)
2458 {
2459 case 17: /* ar.bsp */
2460 add_unwind_entry (output_bsp_when ());
2461 add_unwind_entry (output_bsp_sprel (val));
2462 break;
2463 case 18: /* ar.bspstore */
2464 add_unwind_entry (output_bspstore_when ());
2465 add_unwind_entry (output_bspstore_sprel (val));
2466 break;
2467 case 19: /* ar.rnat */
2468 add_unwind_entry (output_rnat_when ());
2469 add_unwind_entry (output_rnat_sprel (val));
2470 break;
2471 case 36: /* ar.unat */
2472 add_unwind_entry (output_unat_when ());
2473 add_unwind_entry (output_unat_sprel (val));
2474 break;
2475 case 40: /* ar.fpsr */
2476 add_unwind_entry (output_fpsr_when ());
2477 add_unwind_entry (output_fpsr_sprel (val));
2478 break;
2479 case 64: /* ar.pfs */
2480 add_unwind_entry (output_pfs_when ());
2481 add_unwind_entry (output_pfs_sprel (val));
2482 break;
2483 case 65: /* ar.lc */
2484 add_unwind_entry (output_lc_when ());
2485 add_unwind_entry (output_lc_sprel (val));
2486 break;
2487 case REG_BR - REG_AR: /* rp */
2488 add_unwind_entry (output_rp_when ());
2489 add_unwind_entry (output_rp_sprel (val));
2490 break;
2491 case REG_PR - REG_AR: /* Predicate registers. */
2492 add_unwind_entry (output_preds_when ());
2493 add_unwind_entry (output_preds_sprel (val));
2494 break;
2495 default:
2496 as_bad ("first operand is unknown application register");
2497 }
2498 }
2499 else
2500 as_bad (" Second operand not a valid constant");
2501 }
2502 else
2503 as_bad ("First operand not a valid register");
2504}
2505
2506static void
2507dot_savepsp (dummy)
2508 int dummy;
2509{
2510 discard_rest_of_line ();
2511}
2512
2513static void
2514dot_saveg (dummy)
2515 int dummy;
2516{
2517 expressionS e1, e2;
2518 int sep;
2519 sep = parse_operand (&e1);
2520 if (sep == ',')
2521 parse_operand (&e2);
2522
2523 if (e1.X_op != O_constant)
2524 as_bad ("First operand to .save.g must be a constant.");
2525 else
2526 {
2527 int grmask = e1.X_add_number;
2528 if (sep != ',')
2529 add_unwind_entry (output_gr_mem (grmask));
2530 else
2531 {
2532 int reg = e2.X_add_number - REG_GR;
2533 if (e2.X_op == O_register && reg >=0 && reg < 128)
2534 add_unwind_entry (output_gr_gr (grmask, reg));
2535 else
2536 as_bad ("Second operand is an invalid register.");
2537 }
2538 }
2539}
2540
2541static void
2542dot_savef (dummy)
2543 int dummy;
2544{
2545 expressionS e1, e2;
2546 int sep;
2547 sep = parse_operand (&e1);
2548
2549 if (e1.X_op != O_constant)
2550 as_bad ("Operand to .save.f must be a constant.");
2551 else
2552 {
2553 int frmask = e1.X_add_number;
2554 add_unwind_entry (output_fr_mem (e1.X_add_number));
2555 }
2556}
2557
2558static void
2559dot_saveb (dummy)
2560 int dummy;
2561{
2562 expressionS e1;
2563 int sep;
2564 sep = parse_operand (&e1);
2565
2566 if (e1.X_op != O_constant)
2567 as_bad ("Operand to .save.b must be a constant.");
2568 else
2569 {
2570 int brmask = e1.X_add_number;
2571 add_unwind_entry (output_br_mem (brmask));
2572 }
2573}
2574
2575static void
2576dot_savegf (dummy)
2577 int dummy;
2578{
2579 expressionS e1, e2;
2580 int sep;
2581 sep = parse_operand (&e1);
2582 if (sep == ',')
2583 parse_operand (&e2);
2584
2585 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
2586 as_bad ("Both operands of .save.gf must be constants.");
2587 else
2588 {
2589 int grmask = e1.X_add_number;
2590 int frmask = e2.X_add_number;
2591 add_unwind_entry (output_frgr_mem (grmask, frmask));
2592 }
2593}
2594
2595static void
2596dot_spill (dummy)
2597 int dummy;
2598{
2599 expressionS e;
2600 parse_operand (&e);
2601
2602 if (e.X_op != O_constant)
2603 as_bad ("Operand to .spill must be a constant");
2604 else
2605 {
2606 add_unwind_entry (output_spill_base (e.X_add_number));
2607 }
2608}
2609
2610static void
2611dot_unwabi (dummy)
2612 int dummy;
2613{
2614 discard_rest_of_line ();
2615}
2616
2617static void
2618dot_personality (dummy)
2619 int dummy;
2620{
2621 char *name, *p, c;
2622 SKIP_WHITESPACE ();
2623 name = input_line_pointer;
2624 c = get_symbol_end ();
2625 p = input_line_pointer;
2626 personality_routine = symbol_find_or_make (name);
2627 *p = c;
2628 SKIP_WHITESPACE ();
2629 demand_empty_rest_of_line ();
2630}
2631
2632static void
2633dot_proc (dummy)
2634 int dummy;
2635{
2636 char *name, *p, c;
2637 symbolS *sym;
2638
2639 proc_start = expr_build_dot ();
2640 /* Parse names of main and alternate entry points and mark them s
2641 function symbols: */
2642 while (1)
2643 {
2644 SKIP_WHITESPACE ();
2645 name = input_line_pointer;
2646 c = get_symbol_end ();
2647 p = input_line_pointer;
2648 sym = symbol_find_or_make (name);
2649 if (proc_start == 0)
2650 {
2651 proc_start = sym;
2652 }
2653 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
2654 *p = c;
2655 SKIP_WHITESPACE ();
2656 if (*input_line_pointer != ',')
2657 break;
2658 ++input_line_pointer;
2659 }
2660 demand_empty_rest_of_line ();
2661 ia64_do_align (16);
2662
2663 unwind_list = unwind_tail = current_unwind_entry = NULL;
2664 personality_routine = 0;
2665}
2666
2667static void
2668dot_body (dummy)
2669 int dummy;
2670{
2671 unwind_prologue = 0;
2672 add_unwind_entry (output_body ());
2673}
2674
2675static void
2676dot_prologue (dummy)
2677 int dummy;
2678{
2679 unwind_prologue = 1;
2680 SKIP_WHITESPACE ();
2681 if (! is_end_of_line[(unsigned char) *input_line_pointer])
2682 {
2683 expressionS e1, e2;
2684 char sep;
2685 sep = parse_operand (&e1);
2686 if (sep != ',')
2687 as_bad ("No second operand to .prologue");
2688 sep = parse_operand (&e2);
2689
2690 if (e1.X_op == O_constant)
2691 {
2692 if (e2.X_op == O_constant)
2693 {
2694 int mask = e1.X_add_number;
2695 int reg = e2.X_add_number;
2696 add_unwind_entry (output_prologue_gr (mask, reg));
2697 }
2698 else
2699 as_bad ("Second operand not a constant");
2700 }
2701 else
2702 as_bad ("First operand not a constant");
2703 }
2704 else
2705 add_unwind_entry (output_prologue ());
2706}
2707
2708static void
2709dot_endp (dummy)
2710 int dummy;
2711{
2712 expressionS e;
2713 unsigned char *ptr;
2714 int size;
2715 long where;
2716 segT saved_seg;
2717 subsegT saved_subseg;
2718
2719 saved_seg = now_seg;
2720 saved_subseg = now_subseg;
2721
2722 expression (&e);
2723 demand_empty_rest_of_line ();
2724
2725 insn_group_break (1, 0, 0);
2726 ia64_flush_insns ();
2727
2728 /* If there was a .handlerdata, we haven't generated an image yet. */
2729 if (unwind_info == 0)
2730 {
2731 generate_unwind_image ();
2732 }
2733
2734 subseg_set (md.last_text_seg, 0);
2735 proc_end = expr_build_dot ();
2736
2737 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
2738 ptr = frag_more (24);
2739 where = frag_now_fix () - 24;
2740
2741 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
2742 e.X_op = O_pseudo_fixup;
2743 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
2744 e.X_add_number = 0;
2745 e.X_add_symbol = proc_start;
2746 ia64_cons_fix_new (frag_now, where, 8, &e);
2747
2748 e.X_op = O_pseudo_fixup;
2749 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
2750 e.X_add_number = 0;
2751 e.X_add_symbol = proc_end;
2752 ia64_cons_fix_new (frag_now, where + 8, 8, &e);
2753
2754 if (unwind_info != 0)
2755 {
2756 e.X_op = O_pseudo_fixup;
2757 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
2758 e.X_add_number = 0;
2759 e.X_add_symbol = unwind_info;
2760 ia64_cons_fix_new (frag_now, where + 16, 8, &e);
2761 }
2762 else
2763 md_number_to_chars (ptr + 16, 0, 8);
2764
2765 subseg_set (saved_seg, saved_subseg);
2766 proc_start = proc_end = unwind_info = 0;
2767}
2768
2769static void
2770dot_template (template)
2771 int template;
2772{
2773 CURR_SLOT.user_template = template;
2774}
2775
2776static void
2777dot_regstk (dummy)
2778 int dummy;
2779{
2780 int ins, locs, outs, rots;
2781
2782 if (is_it_end_of_statement ())
2783 ins = locs = outs = rots = 0;
2784 else
2785 {
2786 ins = get_absolute_expression ();
2787 if (*input_line_pointer++ != ',')
2788 goto err;
2789 locs = get_absolute_expression ();
2790 if (*input_line_pointer++ != ',')
2791 goto err;
2792 outs = get_absolute_expression ();
2793 if (*input_line_pointer++ != ',')
2794 goto err;
2795 rots = get_absolute_expression ();
2796 }
2797 set_regstack (ins, locs, outs, rots);
2798 return;
2799
2800 err:
2801 as_bad ("Comma expected");
2802 ignore_rest_of_line ();
2803}
2804
2805static void
2806dot_rot (type)
2807 int type;
2808{
2809 unsigned num_regs, num_alloced = 0;
2810 struct dynreg **drpp, *dr;
2811 int ch, base_reg = 0;
2812 char *name, *start;
2813 size_t len;
2814
2815 switch (type)
2816 {
2817 case DYNREG_GR: base_reg = REG_GR + 32; break;
2818 case DYNREG_FR: base_reg = REG_FR + 32; break;
2819 case DYNREG_PR: base_reg = REG_P + 16; break;
2820 default: break;
2821 }
2822
2823 /* first, remove existing names from hash table: */
2824 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
2825 {
2826 hash_delete (md.dynreg_hash, dr->name);
2827 dr->num_regs = 0;
2828 }
2829
2830 drpp = &md.dynreg[type];
2831 while (1)
2832 {
2833 start = input_line_pointer;
2834 ch = get_symbol_end ();
2835 *input_line_pointer = ch;
2836 len = (input_line_pointer - start);
2837
2838 SKIP_WHITESPACE ();
2839 if (*input_line_pointer != '[')
2840 {
2841 as_bad ("Expected '['");
2842 goto err;
2843 }
2844 ++input_line_pointer; /* skip '[' */
2845
2846 num_regs = get_absolute_expression ();
2847
2848 if (*input_line_pointer++ != ']')
2849 {
2850 as_bad ("Expected ']'");
2851 goto err;
2852 }
2853 SKIP_WHITESPACE ();
2854
2855 num_alloced += num_regs;
2856 switch (type)
2857 {
2858 case DYNREG_GR:
2859 if (num_alloced > md.rot.num_regs)
2860 {
2861 as_bad ("Used more than the declared %d rotating registers",
2862 md.rot.num_regs);
2863 goto err;
2864 }
2865 break;
2866 case DYNREG_FR:
2867 if (num_alloced > 96)
2868 {
2869 as_bad ("Used more than the available 96 rotating registers");
2870 goto err;
2871 }
2872 break;
2873 case DYNREG_PR:
2874 if (num_alloced > 48)
2875 {
2876 as_bad ("Used more than the available 48 rotating registers");
2877 goto err;
2878 }
2879 break;
2880
2881 default:
2882 break;
2883 }
2884
2885 name = obstack_alloc (&notes, len + 1);
2886 memcpy (name, start, len);
2887 name[len] = '\0';
2888
2889 if (!*drpp)
2890 {
2891 *drpp = obstack_alloc (&notes, sizeof (*dr));
2892 memset (*drpp, 0, sizeof (*dr));
2893 }
2894
2895 dr = *drpp;
2896 dr->name = name;
2897 dr->num_regs = num_regs;
2898 dr->base = base_reg;
2899 drpp = &dr->next;
2900 base_reg += num_regs;
2901
2902 if (hash_insert (md.dynreg_hash, name, dr))
2903 {
2904 as_bad ("Attempt to redefine register set `%s'", name);
2905 goto err;
2906 }
2907
2908 if (*input_line_pointer != ',')
2909 break;
2910 ++input_line_pointer; /* skip comma */
2911 SKIP_WHITESPACE ();
2912 }
2913 demand_empty_rest_of_line ();
2914 return;
2915
2916 err:
2917 ignore_rest_of_line ();
2918}
2919
2920static void
2921dot_byteorder (byteorder)
2922 int byteorder;
2923{
2924 target_big_endian = byteorder;
2925}
2926
2927static void
2928dot_psr (dummy)
2929 int dummy;
2930{
2931 char *option;
2932 int ch;
2933
2934 while (1)
2935 {
2936 option = input_line_pointer;
2937 ch = get_symbol_end ();
2938 if (strcmp (option, "lsb") == 0)
2939 md.flags &= ~EF_IA_64_BE;
2940 else if (strcmp (option, "msb") == 0)
2941 md.flags |= EF_IA_64_BE;
2942 else if (strcmp (option, "abi32") == 0)
2943 md.flags &= ~EF_IA_64_ABI64;
2944 else if (strcmp (option, "abi64") == 0)
2945 md.flags |= EF_IA_64_ABI64;
2946 else
2947 as_bad ("Unknown psr option `%s'", option);
2948 *input_line_pointer = ch;
2949
2950 SKIP_WHITESPACE ();
2951 if (*input_line_pointer != ',')
2952 break;
2953
2954 ++input_line_pointer;
2955 SKIP_WHITESPACE ();
2956 }
2957 demand_empty_rest_of_line ();
2958}
2959
2960static void
2961dot_alias (dummy)
2962 int dummy;
2963{
2964 as_bad (".alias not implemented yet");
2965}
2966
2967static void
2968dot_ln (dummy)
2969 int dummy;
2970{
2971 new_logical_line (0, get_absolute_expression ());
2972 demand_empty_rest_of_line ();
2973}
2974
2975static char*
2976parse_section_name ()
2977{
2978 char *name;
2979 int len;
2980
2981 SKIP_WHITESPACE ();
2982 if (*input_line_pointer != '"')
2983 {
2984 as_bad ("Missing section name");
2985 ignore_rest_of_line ();
2986 return 0;
2987 }
2988 name = demand_copy_C_string (&len);
2989 if (!name)
2990 {
2991 ignore_rest_of_line ();
2992 return 0;
2993 }
2994 SKIP_WHITESPACE ();
2995 if (*input_line_pointer != ',')
2996 {
2997 as_bad ("Comma expected after section name");
2998 ignore_rest_of_line ();
2999 return 0;
3000 }
3001 ++input_line_pointer; /* skip comma */
3002 return name;
3003}
3004
3005static void
3006dot_xdata (size)
3007 int size;
3008{
3009 char *name = parse_section_name ();
3010 if (!name)
3011 return;
3012
3013 set_section (name);
3014 cons (size);
3015 obj_elf_previous (0);
3016}
3017
3018/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3019static void
3020stmt_float_cons (kind)
3021 int kind;
3022{
3023 size_t size;
3024
3025 switch (kind)
3026 {
3027 case 'd': size = 8; break;
3028 case 'x': size = 10; break;
3029
3030 case 'f':
3031 default:
3032 size = 4;
3033 break;
3034 }
3035 ia64_do_align (size);
3036 float_cons (kind);
3037}
3038
3039static void
3040stmt_cons_ua (size)
3041 int size;
3042{
3043 int saved_auto_align = md.auto_align;
3044
3045 md.auto_align = 0;
3046 cons (size);
3047 md.auto_align = saved_auto_align;
3048}
3049
3050static void
3051dot_xfloat_cons (kind)
3052 int kind;
3053{
3054 char *name = parse_section_name ();
3055 if (!name)
3056 return;
3057
3058 set_section (name);
3059 stmt_float_cons (kind);
3060 obj_elf_previous (0);
3061}
3062
3063static void
3064dot_xstringer (zero)
3065 int zero;
3066{
3067 char *name = parse_section_name ();
3068 if (!name)
3069 return;
3070
3071 set_section (name);
3072 stringer (zero);
3073 obj_elf_previous (0);
3074}
3075
3076static void
3077dot_xdata_ua (size)
3078 int size;
3079{
3080 int saved_auto_align = md.auto_align;
3081 char *name = parse_section_name ();
3082 if (!name)
3083 return;
3084
3085 set_section (name);
3086 md.auto_align = 0;
3087 cons (size);
3088 md.auto_align = saved_auto_align;
3089 obj_elf_previous (0);
3090}
3091
3092static void
3093dot_xfloat_cons_ua (kind)
3094 int kind;
3095{
3096 int saved_auto_align = md.auto_align;
3097 char *name = parse_section_name ();
3098 if (!name)
3099 return;
3100
3101 set_section (name);
3102 md.auto_align = 0;
3103 stmt_float_cons (kind);
3104 md.auto_align = saved_auto_align;
3105 obj_elf_previous (0);
3106}
3107
3108/* .reg.val <regname>,value */
3109static void
3110dot_reg_val (dummy)
3111 int dummy;
3112{
3113 expressionS reg;
3114
3115 expression (&reg);
3116 if (reg.X_op != O_register)
3117 {
3118 as_bad (_("Register name expected"));
3119 ignore_rest_of_line ();
3120 }
3121 else if (*input_line_pointer++ != ',')
3122 {
3123 as_bad (_("Comma expected"));
3124 ignore_rest_of_line ();
3125 }
3126 else
3127 {
3128 valueT value = get_absolute_expression ();
3129 int regno = reg.X_add_number;
3130 if (regno < REG_GR || regno > REG_GR+128)
3131 as_warn (_("Register value annotation ignored"));
3132 else
3133 {
3134 gr_values[regno-REG_GR].known = 1;
3135 gr_values[regno-REG_GR].value = value;
3136 gr_values[regno-REG_GR].path = md.path;
3137 }
3138 }
3139 demand_empty_rest_of_line ();
3140}
3141
3142/* select dv checking mode
3143 .auto
3144 .explicit
3145 .default
3146
3147 A stop is inserted when changing modes
3148 */
3149static void
3150dot_dv_mode (type)
3151 int type;
3152{
3153 if (md.manual_bundling)
3154 as_warn (_("Directive invalid within a bundle"));
3155
3156 if (type == 'E' || type == 'A')
3157 md.mode_explicitly_set = 0;
3158 else
3159 md.mode_explicitly_set = 1;
3160
3161 md.detect_dv = 1;
3162 switch (type)
3163 {
3164 case 'A':
3165 case 'a':
3166 if (md.explicit_mode)
3167 insn_group_break (1, 0, 0);
3168 md.explicit_mode = 0;
3169 break;
3170 case 'E':
3171 case 'e':
3172 if (!md.explicit_mode)
3173 insn_group_break (1, 0, 0);
3174 md.explicit_mode = 1;
3175 break;
3176 default:
3177 case 'd':
3178 if (md.explicit_mode != md.default_explicit_mode)
3179 insn_group_break (1, 0, 0);
3180 md.explicit_mode = md.default_explicit_mode;
3181 md.mode_explicitly_set = 0;
3182 break;
3183 }
3184}
3185
3186static void
3187print_prmask (mask)
3188 valueT mask;
3189{
3190 int regno;
3191 char *comma = "";
3192 for (regno = 0;regno < 64;regno++)
3193 {
3194 if (mask & ((valueT)1<<regno))
3195 {
3196 fprintf (stderr, "%s p%d", comma, regno);
3197 comma = ",";
3198 }
3199 }
3200}
3201
3202/*
3203 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
3204 .pred.rel.imply p1, p2 (also .pred.rel "imply")
3205 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
3206 .pred.safe_across_calls p1 [, p2 [,...]]
3207 */
3208static void
3209dot_pred_rel (type)
3210 int type;
3211{
3212 valueT mask = 0;
3213 int count = 0;
3214 int p1 = -1, p2 = -1;
3215
3216 if (type == 0)
3217 {
3218 if (*input_line_pointer != '"')
3219 {
3220 as_bad (_("Missing predicate relation type"));
3221 ignore_rest_of_line ();
3222 return;
3223 }
3224 else
3225 {
3226 int len;
3227 char *form = demand_copy_C_string (&len);
3228 if (strcmp (form, "mutex") == 0)
3229 type = 'm';
3230 else if (strcmp (form, "clear") == 0)
3231 type = 'c';
3232 else if (strcmp (form, "imply") == 0)
3233 type = 'i';
3234 else
3235 {
3236 as_bad (_("Unrecognized predicate relation type"));
3237 ignore_rest_of_line ();
3238 return;
3239 }
3240 }
3241 if (*input_line_pointer == ',')
3242 ++input_line_pointer;
3243 SKIP_WHITESPACE ();
3244 }
3245
3246 SKIP_WHITESPACE ();
3247 while (1)
3248 {
3249 valueT bit = 1;
3250 int regno;
3251
3252 if (toupper (*input_line_pointer) != 'P'
3253 || (regno = atoi (++input_line_pointer)) < 0
3254 || regno > 63)
3255 {
3256 as_bad (_("Predicate register expected"));
3257 ignore_rest_of_line ();
3258 return;
3259 }
3260 while (isdigit (*input_line_pointer))
3261 ++input_line_pointer;
3262 if (p1 == -1)
3263 p1 = regno;
3264 else if (p2 == -1)
3265 p2 = regno;
3266 bit <<= regno;
3267 if (mask & bit)
3268 as_warn (_("Duplicate predicate register ignored"));
3269 mask |= bit; count++;
3270 /* see if it's a range */
3271 if (*input_line_pointer == '-')
3272 {
3273 valueT stop = 1;
3274 ++input_line_pointer;
3275
3276 if (toupper (*input_line_pointer) != 'P'
3277 || (regno = atoi (++input_line_pointer)) < 0
3278 || regno > 63)
3279 {
3280 as_bad (_("Predicate register expected"));
3281 ignore_rest_of_line ();
3282 return;
3283 }
3284 while (isdigit (*input_line_pointer))
3285 ++input_line_pointer;
3286 stop <<= regno;
3287 if (bit >= stop)
3288 {
3289 as_bad (_("Bad register range"));
3290 ignore_rest_of_line ();
3291 return;
3292 }
3293 while (bit < stop)
3294 {
3295 bit <<= 1;
3296 mask |= bit; count++;
3297 }
3298 SKIP_WHITESPACE ();
3299 }
3300 if (*input_line_pointer != ',')
3301 break;
3302 ++input_line_pointer;
3303 SKIP_WHITESPACE ();
3304 }
3305
3306 switch (type)
3307 {
3308 case 'c':
3309 if (count == 0)
3310 mask = ~(valueT)0;
3311 clear_qp_mutex (mask);
3312 clear_qp_implies (mask, (valueT)0);
3313 break;
3314 case 'i':
3315 if (count != 2 || p1 == -1 || p2 == -1)
3316 as_bad (_("Predicate source and target required"));
3317 else if (p1 == 0 || p2 == 0)
3318 as_bad (_("Use of p0 is not valid in this context"));
3319 else
3320 add_qp_imply (p1, p2);
3321 break;
3322 case 'm':
3323 if (count < 2)
3324 {
3325 as_bad (_("At least two PR arguments expected"));
3326 break;
3327 }
3328 else if (mask & 1)
3329 {
3330 as_bad (_("Use of p0 is not valid in this context"));
3331 break;
3332 }
3333 add_qp_mutex (mask);
3334 break;
3335 case 's':
3336 /* note that we don't override any existing relations */
3337 if (count == 0)
3338 {
3339 as_bad (_("At least one PR argument expected"));
3340 break;
3341 }
3342 if (md.debug_dv)
3343 {
3344 fprintf (stderr, "Safe across calls: ");
3345 print_prmask (mask);
3346 fprintf (stderr, "\n");
3347 }
3348 qp_safe_across_calls = mask;
3349 break;
3350 }
3351 demand_empty_rest_of_line ();
3352}
3353
3354/* .entry label [, label [, ...]]
3355 Hint to DV code that the given labels are to be considered entry points.
3356 Otherwise, only global labels are considered entry points.
3357 */
3358static void
3359dot_entry (dummy)
3360 int dummy;
3361{
3362 const char *err;
3363 char *name;
3364 int c;
3365 symbolS *symbolP;
3366
3367 do
3368 {
3369 name = input_line_pointer;
3370 c = get_symbol_end ();
3371 symbolP = symbol_find_or_make (name);
3372
3373 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
3374 if (err)
3375 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
3376 name, err);
3377
3378 *input_line_pointer = c;
3379 SKIP_WHITESPACE ();
3380 c = *input_line_pointer;
3381 if (c == ',')
3382 {
3383 input_line_pointer++;
3384 SKIP_WHITESPACE ();
3385 if (*input_line_pointer == '\n')
3386 c = '\n';
3387 }
3388 }
3389 while (c == ',');
3390
3391 demand_empty_rest_of_line ();
3392}
3393
3394/* .mem.offset offset, base
3395 "base" is used to distinguish between offsets from a different base.
3396 */
3397static void
3398dot_mem_offset (dummy)
3399 int dummy;
3400{
3401 md.mem_offset.hint = 1;
3402 md.mem_offset.offset = get_absolute_expression ();
3403 if (*input_line_pointer != ',')
3404 {
3405 as_bad (_("Comma expected"));
3406 ignore_rest_of_line ();
3407 return;
3408 }
3409 ++input_line_pointer;
3410 md.mem_offset.base = get_absolute_expression ();
3411 demand_empty_rest_of_line ();
3412}
3413
3414/* ia64-specific pseudo-ops: */
3415const pseudo_typeS md_pseudo_table[] =
3416 {
3417 { "radix", dot_radix, 0 },
3418 { "lcomm", s_lcomm_bytes, 1 },
3419 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
3420 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
3421 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
3422 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
3423 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
3424 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
3425 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
3426 { "proc", dot_proc, 0 },
3427 { "body", dot_body, 0 },
3428 { "prologue", dot_prologue, 0 },
3429 { "endp", dot_endp },
3430 { "file", dwarf2_directive_file },
3431 { "loc", dwarf2_directive_loc },
3432
3433 { "fframe", dot_fframe },
3434 { "vframe", dot_vframe },
3435 { "save", dot_save },
3436 { "restore", dot_restore },
3437 { "handlerdata", dot_handlerdata },
3438 { "unwentry", dot_unwentry },
3439 { "alprp", dot_altrp },
3440 { "savesp", dot_savesp },
3441 { "savepsp", dot_savepsp },
3442 { "save.g", dot_saveg },
3443 { "save.f", dot_savef },
3444 { "save.b", dot_saveb },
3445 { "save.gf", dot_savegf },
3446 { "spill", dot_spill },
3447 { "unwabi", dot_unwabi },
3448 { "personality", dot_personality },
3449#if 0
3450 { "estate", dot_estate },
3451#endif
3452 { "mii", dot_template, 0x0 },
3453 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
3454 { "mlx", dot_template, 0x2 },
3455 { "mmi", dot_template, 0x4 },
3456 { "mfi", dot_template, 0x6 },
3457 { "mmf", dot_template, 0x7 },
3458 { "mib", dot_template, 0x8 },
3459 { "mbb", dot_template, 0x9 },
3460 { "bbb", dot_template, 0xb },
3461 { "mmb", dot_template, 0xc },
3462 { "mfb", dot_template, 0xe },
3463#if 0
3464 { "lb", dot_scope, 0 },
3465 { "le", dot_scope, 1 },
3466#endif
3467 { "align", s_align_bytes, 0 },
3468 { "regstk", dot_regstk, 0 },
3469 { "rotr", dot_rot, DYNREG_GR },
3470 { "rotf", dot_rot, DYNREG_FR },
3471 { "rotp", dot_rot, DYNREG_PR },
3472 { "lsb", dot_byteorder, 0 },
3473 { "msb", dot_byteorder, 1 },
3474 { "psr", dot_psr, 0 },
3475 { "alias", dot_alias, 0 },
3476 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
3477
3478 { "xdata1", dot_xdata, 1 },
3479 { "xdata2", dot_xdata, 2 },
3480 { "xdata4", dot_xdata, 4 },
3481 { "xdata8", dot_xdata, 8 },
3482 { "xreal4", dot_xfloat_cons, 'f' },
3483 { "xreal8", dot_xfloat_cons, 'd' },
3484 { "xreal10", dot_xfloat_cons, 'x' },
3485 { "xstring", dot_xstringer, 0 },
3486 { "xstringz", dot_xstringer, 1 },
3487
3488 /* unaligned versions: */
3489 { "xdata2.ua", dot_xdata_ua, 2 },
3490 { "xdata4.ua", dot_xdata_ua, 4 },
3491 { "xdata8.ua", dot_xdata_ua, 8 },
3492 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
3493 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
3494 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
3495
3496 /* annotations/DV checking support */
3497 { "entry", dot_entry, 0 },
3498 { "mem.offset", dot_mem_offset },
3499 { "pred.rel", dot_pred_rel, 0 },
3500 { "pred.rel.clear", dot_pred_rel, 'c' },
3501 { "pred.rel.imply", dot_pred_rel, 'i' },
3502 { "pred.rel.mutex", dot_pred_rel, 'm' },
3503 { "pred.safe_across_calls", dot_pred_rel, 's' },
3504 { "reg.val", dot_reg_val },
3505 { "auto", dot_dv_mode, 'a' },
3506 { "explicit", dot_dv_mode, 'e' },
3507 { "default", dot_dv_mode, 'd' },
3508
3509 { NULL, 0, 0 }
3510 };
3511
3512static const struct pseudo_opcode
3513 {
3514 const char *name;
3515 void (*handler) (int);
3516 int arg;
3517 }
3518pseudo_opcode[] =
3519 {
3520 /* these are more like pseudo-ops, but don't start with a dot */
3521 { "data1", cons, 1 },
3522 { "data2", cons, 2 },
3523 { "data4", cons, 4 },
3524 { "data8", cons, 8 },
3525 { "real4", stmt_float_cons, 'f' },
3526 { "real8", stmt_float_cons, 'd' },
3527 { "real10", stmt_float_cons, 'x' },
3528 { "string", stringer, 0 },
3529 { "stringz", stringer, 1 },
3530
3531 /* unaligned versions: */
3532 { "data2.ua", stmt_cons_ua, 2 },
3533 { "data4.ua", stmt_cons_ua, 4 },
3534 { "data8.ua", stmt_cons_ua, 8 },
3535 { "real4.ua", float_cons, 'f' },
3536 { "real8.ua", float_cons, 'd' },
3537 { "real10.ua", float_cons, 'x' },
3538 };
3539
3540/* Declare a register by creating a symbol for it and entering it in
3541 the symbol table. */
3542static symbolS*
3543declare_register (name, regnum)
3544 const char *name;
3545 int regnum;
3546{
3547 const char *err;
3548 symbolS *sym;
3549
3550 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
3551
3552 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
3553 if (err)
3554 as_fatal ("Inserting \"%s\" into register table failed: %s",
3555 name, err);
3556
3557 return sym;
3558}
3559
3560static void
3561declare_register_set (prefix, num_regs, base_regnum)
3562 const char *prefix;
3563 int num_regs;
3564 int base_regnum;
3565{
3566 char name[8];
3567 int i;
3568
3569 for (i = 0; i < num_regs; ++i)
3570 {
3571 sprintf (name, "%s%u", prefix, i);
3572 declare_register (name, base_regnum + i);
3573 }
3574}
3575
3576static unsigned int
3577operand_width (opnd)
3578 enum ia64_opnd opnd;
3579{
3580 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
3581 unsigned int bits = 0;
3582 int i;
3583
3584 bits = 0;
3585 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
3586 bits += odesc->field[i].bits;
3587
3588 return bits;
3589}
3590
3591static int
3592operand_match (idesc, index, e)
3593 const struct ia64_opcode *idesc;
3594 int index;
3595 expressionS *e;
3596{
3597 enum ia64_opnd opnd = idesc->operands[index];
3598 int bits, relocatable = 0;
3599 struct insn_fix *fix;
3600 bfd_signed_vma val;
3601
3602 switch (opnd)
3603 {
3604 /* constants: */
3605
3606 case IA64_OPND_AR_CCV:
3607 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
3608 return 1;
3609 break;
3610
3611 case IA64_OPND_AR_PFS:
3612 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
3613 return 1;
3614 break;
3615
3616 case IA64_OPND_GR0:
3617 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
3618 return 1;
3619 break;
3620
3621 case IA64_OPND_IP:
3622 if (e->X_op == O_register && e->X_add_number == REG_IP)
3623 return 1;
3624 break;
3625
3626 case IA64_OPND_PR:
3627 if (e->X_op == O_register && e->X_add_number == REG_PR)
3628 return 1;
3629 break;
3630
3631 case IA64_OPND_PR_ROT:
3632 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
3633 return 1;
3634 break;
3635
3636 case IA64_OPND_PSR:
3637 if (e->X_op == O_register && e->X_add_number == REG_PSR)
3638 return 1;
3639 break;
3640
3641 case IA64_OPND_PSR_L:
3642 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
3643 return 1;
3644 break;
3645
3646 case IA64_OPND_PSR_UM:
3647 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
3648 return 1;
3649 break;
3650
3651 case IA64_OPND_C1:
3652 if (e->X_op == O_constant && e->X_add_number == 1)
3653 return 1;
3654 break;
3655
3656 case IA64_OPND_C8:
3657 if (e->X_op == O_constant && e->X_add_number == 8)
3658 return 1;
3659 break;
3660
3661 case IA64_OPND_C16:
3662 if (e->X_op == O_constant && e->X_add_number == 16)
3663 return 1;
3664 break;
3665
3666 /* register operands: */
3667
3668 case IA64_OPND_AR3:
3669 if (e->X_op == O_register && e->X_add_number >= REG_AR
3670 && e->X_add_number < REG_AR + 128)
3671 return 1;
3672 break;
3673
3674 case IA64_OPND_B1:
3675 case IA64_OPND_B2:
3676 if (e->X_op == O_register && e->X_add_number >= REG_BR
3677 && e->X_add_number < REG_BR + 8)
3678 return 1;
3679 break;
3680
3681 case IA64_OPND_CR3:
3682 if (e->X_op == O_register && e->X_add_number >= REG_CR
3683 && e->X_add_number < REG_CR + 128)
3684 return 1;
3685 break;
3686
3687 case IA64_OPND_F1:
3688 case IA64_OPND_F2:
3689 case IA64_OPND_F3:
3690 case IA64_OPND_F4:
3691 if (e->X_op == O_register && e->X_add_number >= REG_FR
3692 && e->X_add_number < REG_FR + 128)
3693 return 1;
3694 break;
3695
3696 case IA64_OPND_P1:
3697 case IA64_OPND_P2:
3698 if (e->X_op == O_register && e->X_add_number >= REG_P
3699 && e->X_add_number < REG_P + 64)
3700 return 1;
3701 break;
3702
3703 case IA64_OPND_R1:
3704 case IA64_OPND_R2:
3705 case IA64_OPND_R3:
3706 if (e->X_op == O_register && e->X_add_number >= REG_GR
3707 && e->X_add_number < REG_GR + 128)
3708 return 1;
3709 break;
3710
3711 case IA64_OPND_R3_2:
3712 if (e->X_op == O_register && e->X_add_number >= REG_GR
3713 && e->X_add_number < REG_GR + 4)
3714 return 1;
3715 break;
3716
3717 /* indirect operands: */
3718 case IA64_OPND_CPUID_R3:
3719 case IA64_OPND_DBR_R3:
3720 case IA64_OPND_DTR_R3:
3721 case IA64_OPND_ITR_R3:
3722 case IA64_OPND_IBR_R3:
3723 case IA64_OPND_MSR_R3:
3724 case IA64_OPND_PKR_R3:
3725 case IA64_OPND_PMC_R3:
3726 case IA64_OPND_PMD_R3:
3727 case IA64_OPND_RR_R3:
3728 if (e->X_op == O_index && e->X_op_symbol
3729 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
3730 == opnd - IA64_OPND_CPUID_R3))
3731 return 1;
3732 break;
3733
3734 case IA64_OPND_MR3:
3735 if (e->X_op == O_index && !e->X_op_symbol)
3736 return 1;
3737 break;
3738
3739 /* immediate operands: */
3740 case IA64_OPND_CNT2a:
3741 case IA64_OPND_LEN4:
3742 case IA64_OPND_LEN6:
3743 bits = operand_width (idesc->operands[index]);
3744 if (e->X_op == O_constant
3745 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
3746 return 1;
3747 break;
3748
3749 case IA64_OPND_CNT2b:
3750 if (e->X_op == O_constant
3751 && (bfd_vma) (e->X_add_number - 1) < 3)
3752 return 1;
3753 break;
3754
3755 case IA64_OPND_CNT2c:
3756 val = e->X_add_number;
3757 if (e->X_op == O_constant
3758 && (val == 0 || val == 7 || val == 15 || val == 16))
3759 return 1;
3760 break;
3761
3762 case IA64_OPND_SOR:
3763 /* SOR must be an integer multiple of 8 */
3764 if (e->X_add_number & 0x7)
3765 break;
3766 case IA64_OPND_SOF:
3767 case IA64_OPND_SOL:
3768 if (e->X_op == O_constant &&
3769 (bfd_vma) e->X_add_number <= 96)
3770 return 1;
3771 break;
3772
3773 case IA64_OPND_IMMU62:
3774 if (e->X_op == O_constant)
3775 {
3776 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
3777 return 1;
3778 }
3779 else
3780 {
3781 /* FIXME -- need 62-bit relocation type */
3782 as_bad (_("62-bit relocation not yet implemented"));
3783 }
3784 break;
3785
3786 case IA64_OPND_IMMU64:
3787 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
3788 || e->X_op == O_subtract)
3789 {
3790 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
3791 fix->code = BFD_RELOC_IA64_IMM64;
3792 if (e->X_op != O_subtract)
3793 {
3794 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
3795 if (e->X_op == O_pseudo_fixup)
3796 e->X_op = O_symbol;
3797 }
3798
3799 fix->opnd = idesc->operands[index];
3800 fix->expr = *e;
3801 fix->is_pcrel = 0;
3802 ++CURR_SLOT.num_fixups;
3803 return 1;
3804 }
3805 else if (e->X_op == O_constant)
3806 return 1;
3807 break;
3808
3809 case IA64_OPND_CCNT5:
3810 case IA64_OPND_CNT5:
3811 case IA64_OPND_CNT6:
3812 case IA64_OPND_CPOS6a:
3813 case IA64_OPND_CPOS6b:
3814 case IA64_OPND_CPOS6c:
3815 case IA64_OPND_IMMU2:
3816 case IA64_OPND_IMMU7a:
3817 case IA64_OPND_IMMU7b:
3818 case IA64_OPND_IMMU9:
3819 case IA64_OPND_IMMU21:
3820 case IA64_OPND_IMMU24:
3821 case IA64_OPND_MBTYPE4:
3822 case IA64_OPND_MHTYPE8:
3823 case IA64_OPND_POS6:
3824 bits = operand_width (idesc->operands[index]);
3825 if (e->X_op == O_constant
3826 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
3827 return 1;
3828 break;
3829
3830 case IA64_OPND_IMM44:
3831 /* least 16 bits must be zero */
3832 if ((e->X_add_number & 0xffff) != 0)
3833 as_warn (_("lower 16 bits of mask ignored"));
3834
3835 if (e->X_op == O_constant
3836 && ((e->X_add_number >= 0
3837 && e->X_add_number < ((bfd_vma) 1 << 44))
3838 || (e->X_add_number < 0
3839 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
3840 {
3841 /* sign-extend */
3842 if (e->X_add_number >= 0
3843 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
3844 {
3845 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
3846 }
3847 return 1;
3848 }
3849 break;
3850
3851 case IA64_OPND_IMM17:
3852 /* bit 0 is a don't care (pr0 is hardwired to 1) */
3853 if (e->X_op == O_constant
3854 && ((e->X_add_number >= 0
3855 && e->X_add_number < ((bfd_vma) 1 << 17))
3856 || (e->X_add_number < 0
3857 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
3858 {
3859 /* sign-extend */
3860 if (e->X_add_number >= 0
3861 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
3862 {
3863 e->X_add_number |= ~(((bfd_vma)1 << 17) - 1);
3864 }
3865 return 1;
3866 }
3867 break;
3868
3869 case IA64_OPND_IMM14:
3870 case IA64_OPND_IMM22:
3871 relocatable = 1;
3872 case IA64_OPND_IMM1:
3873 case IA64_OPND_IMM8:
3874 case IA64_OPND_IMM8U4:
3875 case IA64_OPND_IMM8M1:
3876 case IA64_OPND_IMM8M1U4:
3877 case IA64_OPND_IMM8M1U8:
3878 case IA64_OPND_IMM9a:
3879 case IA64_OPND_IMM9b:
3880 bits = operand_width (idesc->operands[index]);
3881 if (relocatable && (e->X_op == O_symbol
3882 || e->X_op == O_subtract
3883 || e->X_op == O_pseudo_fixup))
3884 {
3885 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
3886
3887 if (idesc->operands[index] == IA64_OPND_IMM14)
3888 fix->code = BFD_RELOC_IA64_IMM14;
3889 else
3890 fix->code = BFD_RELOC_IA64_IMM22;
3891
3892 if (e->X_op != O_subtract)
3893 {
3894 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
3895 if (e->X_op == O_pseudo_fixup)
3896 e->X_op = O_symbol;
3897 }
3898
3899 fix->opnd = idesc->operands[index];
3900 fix->expr = *e;
3901 fix->is_pcrel = 0;
3902 ++CURR_SLOT.num_fixups;
3903 return 1;
3904 }
3905 else if (e->X_op != O_constant
3906 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
3907 return 0;
3908
3909 if (opnd == IA64_OPND_IMM8M1U4)
3910 {
3911 /* Zero is not valid for unsigned compares that take an adjusted
3912 constant immediate range. */
3913 if (e->X_add_number == 0)
3914 return 0;
3915
3916 /* Sign-extend 32-bit unsigned numbers, so that the following range
3917 checks will work. */
3918 val = e->X_add_number;
3919 if (((val & (~(bfd_vma)0 << 32)) == 0)
3920 && ((val & ((bfd_vma)1 << 31)) != 0))
3921 val = ((val << 32) >> 32);
3922
3923 /* Check for 0x100000000. This is valid because
3924 0x100000000-1 is the same as ((uint32_t) -1). */
3925 if (val == ((bfd_signed_vma) 1 << 32))
3926 return 1;
3927
3928 val = val - 1;
3929 }
3930 else if (opnd == IA64_OPND_IMM8M1U8)
3931 {
3932 /* Zero is not valid for unsigned compares that take an adjusted
3933 constant immediate range. */
3934 if (e->X_add_number == 0)
3935 return 0;
3936
3937 /* Check for 0x10000000000000000. */
3938 if (e->X_op == O_big)
3939 {
3940 if (generic_bignum[0] == 0
3941 && generic_bignum[1] == 0
3942 && generic_bignum[2] == 0
3943 && generic_bignum[3] == 0
3944 && generic_bignum[4] == 1)
3945 return 1;
3946 else
3947 return 0;
3948 }
3949 else
3950 val = e->X_add_number - 1;
3951 }
3952 else if (opnd == IA64_OPND_IMM8M1)
3953 val = e->X_add_number - 1;
3954 else if (opnd == IA64_OPND_IMM8U4)
3955 {
3956 /* Sign-extend 32-bit unsigned numbers, so that the following range
3957 checks will work. */
3958 val = e->X_add_number;
3959 if (((val & (~(bfd_vma)0 << 32)) == 0)
3960 && ((val & ((bfd_vma)1 << 31)) != 0))
3961 val = ((val << 32) >> 32);
3962 }
3963 else
3964 val = e->X_add_number;
3965
3966 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
3967 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
3968 return 1;
3969 break;
3970
3971 case IA64_OPND_INC3:
3972 /* +/- 1, 4, 8, 16 */
3973 val = e->X_add_number;
3974 if (val < 0)
3975 val = -val;
3976 if (e->X_op == O_constant
3977 && (val == 1 || val == 4 || val == 8 || val == 16))
3978 return 1;
3979 break;
3980
3981 case IA64_OPND_TGT25:
3982 case IA64_OPND_TGT25b:
3983 case IA64_OPND_TGT25c:
3984 case IA64_OPND_TGT64:
3985 if (e->X_op == O_symbol)
3986 {
3987 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
3988 if (opnd == IA64_OPND_TGT25)
3989 fix->code = BFD_RELOC_IA64_PCREL21F;
3990 else if (opnd == IA64_OPND_TGT25b)
3991 fix->code = BFD_RELOC_IA64_PCREL21M;
3992 else if (opnd == IA64_OPND_TGT25c)
3993 fix->code = BFD_RELOC_IA64_PCREL21B;
3994 else
3995 /* FIXME -- use appropriate relocation type */
3996 as_bad (_("long branch targets not implemented"));
3997 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
3998 fix->opnd = idesc->operands[index];
3999 fix->expr = *e;
4000 fix->is_pcrel = 1;
4001 ++CURR_SLOT.num_fixups;
4002 return 1;
4003 }
4004 case IA64_OPND_TAG13:
4005 case IA64_OPND_TAG13b:
4006 switch (e->X_op)
4007 {
4008 case O_constant:
4009 return 1;
4010
4011 case O_symbol:
4012 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4013 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4014 fix->opnd = idesc->operands[index];
4015 fix->expr = *e;
4016 fix->is_pcrel = 1;
4017 ++CURR_SLOT.num_fixups;
4018 return 1;
4019
4020 default:
4021 break;
4022 }
4023 break;
4024
4025 default:
4026 break;
4027 }
4028 return 0;
4029}
4030
4031static int
4032parse_operand (e)
4033 expressionS *e;
4034{
4035 int sep = '\0';
4036
4037 memset (e, 0, sizeof (*e));
4038 e->X_op = O_absent;
4039 SKIP_WHITESPACE ();
4040 if (*input_line_pointer != '}')
4041 expression (e);
4042 sep = *input_line_pointer++;
4043
4044 if (sep == '}')
4045 {
4046 if (!md.manual_bundling)
4047 as_warn ("Found '}' when manual bundling is off");
4048 else
4049 CURR_SLOT.manual_bundling_off = 1;
4050 md.manual_bundling = 0;
4051 sep = '\0';
4052 }
4053 return sep;
4054}
4055
4056/* Returns the next entry in the opcode table that matches the one in
4057 IDESC, and frees the entry in IDESC. If no matching entry is
4058 found, NULL is returned instead. */
4059
4060static struct ia64_opcode *
4061get_next_opcode (struct ia64_opcode *idesc)
4062{
4063 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
4064 ia64_free_opcode (idesc);
4065 return next;
4066}
4067
4068/* Parse the operands for the opcode and find the opcode variant that
4069 matches the specified operands, or NULL if no match is possible. */
4070static struct ia64_opcode*
4071parse_operands (idesc)
4072 struct ia64_opcode *idesc;
4073{
4074 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
4075 int sep = 0;
4076 enum ia64_opnd expected_operand = IA64_OPND_NIL;
4077 char mnemonic[129];
4078 char *first_arg = 0, *end, *saved_input_pointer;
4079 unsigned int sof;
4080
4081 assert (strlen (idesc->name) <= 128);
4082
4083 strcpy (mnemonic, idesc->name);
4084 if (idesc->operands[2] == IA64_OPND_SOF)
4085 {
4086 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4087 can't parse the first operand until we have parsed the
4088 remaining operands of the "alloc" instruction. */
4089 SKIP_WHITESPACE ();
4090 first_arg = input_line_pointer;
4091 end = strchr (input_line_pointer, '=');
4092 if (!end)
4093 {
4094 as_bad ("Expected separator `='");
4095 return 0;
4096 }
4097 input_line_pointer = end + 1;
4098 ++i;
4099 ++num_outputs;
4100 }
4101
4102 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
4103 {
4104 sep = parse_operand (CURR_SLOT.opnd + i);
4105 if (CURR_SLOT.opnd[i].X_op == O_absent)
4106 break;
4107
4108 ++num_operands;
4109
4110 if (sep != '=' && sep != ',')
4111 break;
4112
4113 if (sep == '=')
4114 {
4115 if (num_outputs > 0)
4116 as_bad ("Duplicate equal sign (=) in instruction");
4117 else
4118 num_outputs = i + 1;
4119 }
4120 }
4121 if (sep != '\0')
4122 {
4123 as_bad ("Illegal operand separator `%c'", sep);
4124 return 0;
4125 }
4126
4127 if (idesc->operands[2] == IA64_OPND_SOF)
4128 {
4129 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
4130 know (strcmp (idesc->name, "alloc") == 0);
4131 if (num_operands == 5 /* first_arg not included in this count! */
4132 && CURR_SLOT.opnd[2].X_op == O_constant
4133 && CURR_SLOT.opnd[3].X_op == O_constant
4134 && CURR_SLOT.opnd[4].X_op == O_constant
4135 && CURR_SLOT.opnd[5].X_op == O_constant)
4136 {
4137 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
4138 CURR_SLOT.opnd[3].X_add_number,
4139 CURR_SLOT.opnd[4].X_add_number,
4140 CURR_SLOT.opnd[5].X_add_number);
4141
4142 /* now we can parse the first arg: */
4143 saved_input_pointer = input_line_pointer;
4144 input_line_pointer = first_arg;
4145 sep = parse_operand (CURR_SLOT.opnd + 0);
4146 if (sep != '=')
4147 --num_outputs; /* force error */
4148 input_line_pointer = saved_input_pointer;
4149
4150 CURR_SLOT.opnd[2].X_add_number = sof;
4151 CURR_SLOT.opnd[3].X_add_number
4152 = sof - CURR_SLOT.opnd[4].X_add_number;
4153 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
4154 }
4155 }
4156
4157 highest_unmatched_operand = 0;
4158 expected_operand = idesc->operands[0];
4159 for (; idesc; idesc = get_next_opcode (idesc))
4160 {
4161 if (num_outputs != idesc->num_outputs)
4162 continue; /* mismatch in # of outputs */
4163
4164 CURR_SLOT.num_fixups = 0;
4165 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
4166 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
4167 break;
4168
4169 if (i != num_operands)
4170 {
4171 if (i > highest_unmatched_operand)
4172 {
4173 highest_unmatched_operand = i;
4174 expected_operand = idesc->operands[i];
4175 }
4176 continue;
4177 }
4178
4179 if (num_operands < NELEMS (idesc->operands)
4180 && idesc->operands[num_operands])
4181 continue; /* mismatch in number of arguments */
4182
4183 break;
4184 }
4185 if (!idesc)
4186 {
4187 if (expected_operand)
4188 as_bad ("Operand %u of `%s' should be %s",
4189 highest_unmatched_operand + 1, mnemonic,
4190 elf64_ia64_operands[expected_operand].desc);
4191 else
4192 as_bad ("Operand mismatch");
4193 return 0;
4194 }
4195 return idesc;
4196}
4197
4198static void
4199build_insn (slot, insnp)
4200 struct slot *slot;
4201 bfd_vma *insnp;
4202{
4203 const struct ia64_operand *odesc, *o2desc;
4204 struct ia64_opcode *idesc = slot->idesc;
4205 bfd_signed_vma insn, val;
4206 const char *err;
4207 int i;
4208
4209 insn = idesc->opcode | slot->qp_regno;
4210
4211 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
4212 {
4213 if (idesc->operands[i] == IA64_OPND_IMMU64)
4214 {
4215 val = slot->opnd[i].X_add_number;
4216 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
4217 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
4218 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
4219 | (((val >> 63) & 0x1) << 36));
4220 }
4221 else if (idesc->operands[i] == IA64_OPND_IMMU62)
4222 {
4223 val = slot->opnd[i].X_add_number & 0x3fffffffffffffffULL;
4224 if (val != slot->opnd[i].X_add_number)
4225 as_warn (_("Value truncated to 62 bits"));
4226 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
4227 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
4228 }
4229 else if (idesc->operands[i] == IA64_OPND_TGT64)
4230 {
4231 // FIXME -- need to implement the target address encoding properly
4232 as_bad (_("long branch target encoding not implemented"));
4233 *insnp++ = 0;
4234 }
4235 else if (slot->opnd[i].X_op == O_register
4236 || slot->opnd[i].X_op == O_constant
4237 || slot->opnd[i].X_op == O_index
4238 || slot->opnd[i].X_op == O_big)
4239 {
4240 if (slot->opnd[i].X_op == O_big)
4241 {
4242 /* This must be the value 0x10000000000000000. */
4243 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
4244 val = 0;
4245 }
4246 else
4247 val = slot->opnd[i].X_add_number;
4248
4249 switch (idesc->operands[i])
4250 {
4251 case IA64_OPND_AR3: val -= REG_AR; break;
4252 case IA64_OPND_B1: case IA64_OPND_B2: val -= REG_BR; break;
4253 case IA64_OPND_CR3: val -= REG_CR; break;
4254 case IA64_OPND_F1: case IA64_OPND_F2:
4255 case IA64_OPND_F3: case IA64_OPND_F4: val -= REG_FR; break;
4256 case IA64_OPND_P1: case IA64_OPND_P2: val -= REG_P; break;
4257
4258 case IA64_OPND_R1: case IA64_OPND_R2:
4259 case IA64_OPND_R3: case IA64_OPND_R3_2:
4260 case IA64_OPND_CPUID_R3: case IA64_OPND_DBR_R3:
4261 case IA64_OPND_DTR_R3: case IA64_OPND_ITR_R3:
4262 case IA64_OPND_IBR_R3: case IA64_OPND_MR3:
4263 case IA64_OPND_MSR_R3: case IA64_OPND_PKR_R3:
4264 case IA64_OPND_PMC_R3: case IA64_OPND_PMD_R3:
4265 case IA64_OPND_RR_R3:
4266 val -= REG_GR;
4267 break;
4268
4269 default:
4270 break;
4271 }
4272 odesc = elf64_ia64_operands + idesc->operands[i];
4273 err = (*odesc->insert) (odesc, val, &insn);
4274 if (err)
4275 as_bad_where (slot->src_file, slot->src_line,
4276 "Bad operand value: %s", err);
4277 if (idesc->flags & IA64_OPCODE_PSEUDO)
4278 {
4279 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
4280 && odesc == elf64_ia64_operands + IA64_OPND_F3)
4281 {
4282 o2desc = elf64_ia64_operands + IA64_OPND_F2;
4283 (*o2desc->insert) (o2desc, val, &insn);
4284
4285 }
4286 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
4287 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
4288 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
4289 {
4290 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
4291 (*o2desc->insert) (o2desc, 64 - val, &insn);
4292 }
4293 }
4294 }
4295 }
4296 *insnp = insn;
4297}
4298
4299static void
4300emit_one_bundle ()
4301{
4302 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
4303 unsigned int manual_bundling = 0;
4304 enum ia64_unit required_unit, insn_unit = 0;
4305 enum ia64_insn_type type[3], insn_type;
4306 unsigned int template, orig_template;
4307 bfd_vma insn[3] = {-1, -1, -1};
4308 struct ia64_opcode *idesc;
4309 int end_of_insn_group = 0, user_template = -1;
4310 int n, i, j, first, curr;
4311 bfd_vma t0 = 0, t1 = 0;
4312 struct label_fix *lfix;
4313 struct insn_fix *ifix;
4314 char mnemonic[16];
4315 fixS *fix;
4316 char *f;
4317
4318 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
4319 know (first >= 0 & first < NUM_SLOTS);
4320 n = MIN (3, md.num_slots_in_use);
4321
4322 /* Determine template: user user_template if specified, best match
4323 otherwise: */
4324
4325 if (md.slot[first].user_template >= 0)
4326 user_template = template = md.slot[first].user_template;
4327 else
4328 {
4329 /* auto select appropriate template */
4330 memset (type, 0, sizeof (type));
4331 curr = first;
4332 for (i = 0; i < n; ++i)
4333 {
4334 type[i] = md.slot[curr].idesc->type;
4335 curr = (curr + 1) % NUM_SLOTS;
4336 }
4337 template = best_template[type[0]][type[1]][type[2]];
4338 }
4339
4340 /* initialize instructions with appropriate nops: */
4341 for (i = 0; i < 3; ++i)
4342 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
4343
4344 f = frag_more (16);
4345
4346 /* now fill in slots with as many insns as possible: */
4347 curr = first;
4348 idesc = md.slot[curr].idesc;
4349 end_of_insn_group = 0;
4350 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
4351 {
4352 if (idesc->flags & IA64_OPCODE_SLOT2)
4353 {
4354 if (manual_bundling && i != 2)
4355 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
4356 "`%s' must be last in bundle", idesc->name);
4357 else
4358 i = 2;
4359 }
4360 if (idesc->flags & IA64_OPCODE_LAST)
4361 {
4362 int required_slot, required_template;
4363
4364 /* If we need a stop bit after an M slot, our only choice is
4365 template 5 (M;;MI). If we need a stop bit after a B
4366 slot, our only choice is to place it at the end of the
4367 bundle, because the only available templates are MIB,
4368 MBB, BBB, MMB, and MFB. We don't handle anything other
4369 than M and B slots because these are the only kind of
4370 instructions that can have the IA64_OPCODE_LAST bit set. */
4371 required_template = template;
4372 switch (idesc->type)
4373 {
4374 case IA64_TYPE_M:
4375 required_slot = 0;
4376 required_template = 5;
4377 break;
4378
4379 case IA64_TYPE_B:
4380 required_slot = 2;
4381 break;
4382
4383 default:
4384 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
4385 "Internal error: don't know how to force %s to end"
4386 "of instruction group", idesc->name);
4387 required_slot = i;
4388 break;
4389 }
4390 if (manual_bundling && i != required_slot)
4391 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
4392 "`%s' must be last in instruction group",
4393 idesc->name);
4394 if (required_slot < i)
4395 /* Can't fit this instruction. */
4396 break;
4397
4398 i = required_slot;
4399 if (required_template != template)
4400 {
4401 /* If we switch the template, we need to reset the NOPs
4402 after slot i. The slot-types of the instructions ahead
4403 of i never change, so we don't need to worry about
4404 changing NOPs in front of this slot. */
4405 for (j = i; j < 3; ++j)
4406 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
4407 }
4408 template = required_template;
4409 }
4410 if (curr != first && md.slot[curr].label_fixups)
4411 {
4412 if (manual_bundling_on)
4413 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
4414 "Label must be first in a bundle");
4415 /* This insn must go into the first slot of a bundle. */
4416 break;
4417 }
4418
4419 manual_bundling_on = md.slot[curr].manual_bundling_on;
4420 manual_bundling_off = md.slot[curr].manual_bundling_off;
4421
4422 if (manual_bundling_on)
4423 {
4424 if (curr == first)
4425 manual_bundling = 1;
4426 else
4427 break; /* need to start a new bundle */
4428 }
4429
4430 if (end_of_insn_group && md.num_slots_in_use >= 1)
4431 {
4432 /* We need an instruction group boundary in the middle of a
4433 bundle. See if we can switch to an other template with
4434 an appropriate boundary. */
4435
4436 orig_template = template;
4437 if (i == 1 && (user_template == 4
4438 || (user_template < 0
4439 && (ia64_templ_desc[template].exec_unit[0]
4440 == IA64_UNIT_M))))
4441 {
4442 template = 5;
4443 end_of_insn_group = 0;
4444 }
4445 else if (i == 2 && (user_template == 0
4446 || (user_template < 0
4447 && (ia64_templ_desc[template].exec_unit[1]
4448 == IA64_UNIT_I)))
4449 /* This test makes sure we don't switch the template if
4450 the next instruction is one that needs to be first in
4451 an instruction group. Since all those instructions are
4452 in the M group, there is no way such an instruction can
4453 fit in this bundle even if we switch the template. The
4454 reason we have to check for this is that otherwise we
4455 may end up generating "MI;;I M.." which has the deadly
4456 effect that the second M instruction is no longer the
4457 first in the bundle! --davidm 99/12/16 */
4458 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
4459 {
4460 template = 1;
4461 end_of_insn_group = 0;
4462 }
4463 else if (curr != first)
4464 /* can't fit this insn */
4465 break;
4466
4467 if (template != orig_template)
4468 /* if we switch the template, we need to reset the NOPs
4469 after slot i. The slot-types of the instructions ahead
4470 of i never change, so we don't need to worry about
4471 changing NOPs in front of this slot. */
4472 for (j = i; j < 3; ++j)
4473 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
4474 }
4475 required_unit = ia64_templ_desc[template].exec_unit[i];
4476
4477 /* resolve dynamic opcodes such as "break" and "nop": */
4478 if (idesc->type == IA64_TYPE_DYN)
4479 {
4480 if ((strcmp (idesc->name, "nop") == 0)
4481 || (strcmp (idesc->name, "break") == 0))
4482 insn_unit = required_unit;
4483 else if (strcmp (idesc->name, "chk.s") == 0)
4484 {
4485 insn_unit = IA64_UNIT_M;
4486 if (required_unit == IA64_UNIT_I)
4487 insn_unit = IA64_UNIT_I;
4488 }
4489 else
4490 as_fatal ("emit_one_bundle: unexpected dynamic op");
4491
4492 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
4493 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
4494#if 0
4495 know (!idesc->next); /* no resolved dynamic ops have collisions */
4496#endif
4497 }
4498 else
4499 {
4500 insn_type = idesc->type;
4501 insn_unit = IA64_UNIT_NIL;
4502 switch (insn_type)
4503 {
4504 case IA64_TYPE_A:
4505 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
4506 insn_unit = required_unit;
4507 break;
4508 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
4509 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
4510 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
4511 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
4512 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
4513 default: break;
4514 }
4515 }
4516
4517 if (insn_unit != required_unit)
4518 {
4519 if (required_unit == IA64_UNIT_L
4520 && insn_unit == IA64_UNIT_I
4521 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
4522 {
4523 /* we got ourselves an MLX template but the current
4524 instruction isn't an X-unit, or an I-unit instruction
4525 that can go into the X slot of an MLX template. Duh. */
4526 if (md.num_slots_in_use >= NUM_SLOTS)
4527 {
4528 as_bad_where (md.slot[curr].src_file,
4529 md.slot[curr].src_line,
4530 "`%s' can't go in X slot of "
4531 "MLX template", idesc->name);
4532 /* drop this insn so we don't livelock: */
4533 --md.num_slots_in_use;
4534 }
4535 break;
4536 }
4537 continue; /* try next slot */
4538 }
4539
4540 if (debug_type == DEBUG_DWARF2)
4541 {
4542 bfd_vma addr;
4543
4544 addr = frag_now->fr_address + frag_now_fix () - 16 + 1*i;
4545 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
4546 }
4547
4548 build_insn (md.slot + curr, insn + i);
4549
4550 /* Set slot counts for unwind records. */
4551 while (md.slot[curr].unwind_record)
4552 {
4553 md.slot[curr].unwind_record->slot_number = (unsigned long) (f + i);
4554 md.slot[curr].unwind_record = md.slot[curr].unwind_record->next;
4555 }
4556 if (required_unit == IA64_UNIT_L)
4557 {
4558 know (i == 1);
4559 /* skip one slot for long/X-unit instructions */
4560 ++i;
4561 }
4562 --md.num_slots_in_use;
4563
4564 /* now is a good time to fix up the labels for this insn: */
4565 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
4566 {
4567 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
4568 symbol_set_frag (lfix->sym, frag_now);
4569 }
4570
4571 for (j = 0; j < md.slot[curr].num_fixups; ++j)
4572 {
4573 ifix = md.slot[curr].fixup + j;
4574 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
4575 &ifix->expr, ifix->is_pcrel, ifix->code);
4576 fix->tc_fix_data.opnd = ifix->opnd;
4577 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
4578 fix->fx_file = md.slot[curr].src_file;
4579 fix->fx_line = md.slot[curr].src_line;
4580 }
4581
4582 end_of_insn_group = md.slot[curr].end_of_insn_group;
4583
4584 /* clear slot: */
4585 ia64_free_opcode (md.slot[curr].idesc);
4586 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
4587 md.slot[curr].user_template = -1;
4588
4589 if (manual_bundling_off)
4590 {
4591 manual_bundling = 0;
4592 break;
4593 }
4594 curr = (curr + 1) % NUM_SLOTS;
4595 idesc = md.slot[curr].idesc;
4596 }
4597 if (manual_bundling)
4598 {
4599 if (md.num_slots_in_use > 0)
4600 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
4601 "`%s' does not fit into %s template",
4602 idesc->name, ia64_templ_desc[template].name);
4603 else
4604 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
4605 "Missing '}' at end of file");
4606 }
4607 know (md.num_slots_in_use < NUM_SLOTS);
4608
4609 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
4610 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
4611
4612 md_number_to_chars (f + 0, t0, 8);
4613 md_number_to_chars (f + 8, t1, 8);
4614}
4615
4616int
4617md_parse_option (c, arg)
4618 int c;
4619 char *arg;
4620{
4621 /* Switches from the Intel assembler. */
4622 switch (c)
4623 {
4624 case 'M':
4625 if (strcmp (arg, "ilp64") == 0
4626 || strcmp (arg, "lp64") == 0
4627 || strcmp (arg, "p64") == 0)
4628 {
4629 md.flags |= EF_IA_64_ABI64;
4630 }
4631 else if (strcmp (arg, "ilp32") == 0)
4632 {
4633 md.flags &= ~EF_IA_64_ABI64;
4634 }
4635 else if (strcmp (arg, "le") == 0)
4636 {
4637 md.flags &= ~EF_IA_64_BE;
4638 }
4639 else if (strcmp (arg, "be") == 0)
4640 {
4641 md.flags |= EF_IA_64_BE;
4642 }
4643 else
4644 return 0;
4645 break;
4646
4647 case 'N':
4648 if (strcmp (arg, "so") == 0)
4649 {
4650 /* Suppress signon message. */
4651 }
4652 else if (strcmp (arg, "pi") == 0)
4653 {
4654 /* Reject privileged instructions. FIXME */
4655 }
4656 else if (strcmp (arg, "us") == 0)
4657 {
4658 /* Allow union of signed and unsigned range. FIXME */
4659 }
4660 else if (strcmp (arg, "close_fcalls") == 0)
4661 {
4662 /* Do not resolve global function calls. */
4663 }
4664 else
4665 return 0;
4666 break;
4667
4668 case 'C':
4669 /* temp[="prefix"] Insert temporary labels into the object file
4670 symbol table prefixed by "prefix".
4671 Default prefix is ":temp:".
4672 */
4673 break;
4674
4675 case 'a':
4676 /* ??? Conflicts with gas' listing option. */
4677 /* indirect=<tgt> Assume unannotated indirect branches behavior
4678 according to <tgt> --
4679 exit: branch out from the current context (default)
4680 labels: all labels in context may be branch targets
4681 */
4682 break;
4683
4684 case 'x':
4685 /* -X conflicts with an ignored option, use -x instead */
4686 md.detect_dv = 1;
4687 if (!arg || strcmp (arg, "explicit") == 0)
4688 {
4689 /* set default mode to explicit */
4690 md.default_explicit_mode = 1;
4691 break;
4692 }
4693 else if (strcmp (arg, "auto") == 0)
4694 {
4695 md.default_explicit_mode = 0;
4696 }
4697 else if (strcmp (arg, "debug") == 0)
4698 {
4699 md.debug_dv = 1;
4700 }
4701 else if (strcmp (arg, "debugx") == 0)
4702 {
4703 md.default_explicit_mode = 1;
4704 md.debug_dv = 1;
4705 }
4706 else
4707 {
4708 as_bad (_("Unrecognized option '-x%s'"), arg);
4709 }
4710 break;
4711
4712 case 'S':
4713 /* nops Print nops statistics. */
4714 break;
4715
4716 default:
4717 return 0;
4718 }
4719
4720 return 1;
4721}
4722
4723void
4724md_show_usage (stream)
4725 FILE *stream;
4726{
4727 fputs(_("\
4728IA-64 options:\n\
4729 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
4730 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
4731 -x | -xexplicit turn on dependency violation checking (default)\n\
4732 -xauto automagically remove dependency violations\n\
4733 -xdebug debug dependency violation checker\n"),
4734 stream);
4735}
4736
4737static inline int
4738match (int templ, int type, int slot)
4739{
4740 enum ia64_unit unit;
4741 int result;
4742
4743 unit = ia64_templ_desc[templ].exec_unit[slot];
4744 switch (type)
4745 {
4746 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
4747 case IA64_TYPE_A:
4748 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
4749 break;
4750 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
4751 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
4752 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
4753 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
4754 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
4755 default: result = 0; break;
4756 }
4757 return result;
4758}
4759
4760/* This function is called once, at assembler startup time. It sets
4761 up all the tables, etc. that the MD part of the assembler will need
4762 that can be determined before arguments are parsed. */
4763void
4764md_begin ()
4765{
4766 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
4767 const char *err;
4768 char name[8];
4769
4770 md.auto_align = 1;
4771 md.explicit_mode = md.default_explicit_mode;
4772
4773 bfd_set_section_alignment (stdoutput, text_section, 4);
4774
4775 target_big_endian = 0;
4776 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
4777 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
4778 &zero_address_frag);
4779
4780 pseudo_func[FUNC_GP_RELATIVE].u.sym =
4781 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
4782 &zero_address_frag);
4783
4784 pseudo_func[FUNC_LT_RELATIVE].u.sym =
4785 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
4786 &zero_address_frag);
4787
4788 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
4789 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
4790 &zero_address_frag);
4791
4792 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
4793 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
4794 &zero_address_frag);
4795
4796 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
4797 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
4798 &zero_address_frag);
4799
4800 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
4801 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
4802 &zero_address_frag);
4803
4804 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
4805 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
4806 &zero_address_frag);
4807
4808 /* compute the table of best templates: */
4809 for (i = 0; i < IA64_NUM_TYPES; ++i)
4810 for (j = 0; j < IA64_NUM_TYPES; ++j)
4811 for (k = 0; k < IA64_NUM_TYPES; ++k)
4812 {
4813 best = 0;
4814 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
4815 {
4816 goodness = 0;
4817 if (match (t, i, 0))
4818 {
4819 if (match (t, j, 1))
4820 {
4821 if (match (t, k, 2))
4822 goodness = 3;
4823 else
4824 goodness = 2;
4825 }
4826 else if (match (t, j, 2))
4827 goodness = 2;
4828 else
4829 goodness = 1;
4830 }
4831 else if (match (t, i, 1))
4832 {
4833 if (match (t, j, 2))
4834 goodness = 2;
4835 else
4836 goodness = 1;
4837 }
4838 else if (match (t, i, 2))
4839 goodness = 1;
4840
4841 if (goodness > best)
4842 {
4843 best = goodness;
4844 best_template[i][j][k] = t;
4845 }
4846 }
4847 }
4848
4849 for (i = 0; i < NUM_SLOTS; ++i)
4850 md.slot[i].user_template = -1;
4851
4852 md.pseudo_hash = hash_new ();
4853 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
4854 {
4855 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
4856 (void *) (pseudo_opcode + i));
4857 if (err)
4858 as_fatal ("ia64.md_begin: can't hash `%s': %s",
4859 pseudo_opcode[i].name, err);
4860 }
4861
4862 md.reg_hash = hash_new ();
4863 md.dynreg_hash = hash_new ();
4864 md.const_hash = hash_new ();
4865 md.entry_hash = hash_new ();
4866
4867 /* general registers: */
4868
4869 total = 128;
4870 for (i = 0; i < total; ++i)
4871 {
4872 sprintf (name, "r%d", i - REG_GR);
4873 md.regsym[i] = declare_register (name, i);
4874 }
4875
4876 /* floating point registers: */
4877 total += 128;
4878 for (; i < total; ++i)
4879 {
4880 sprintf (name, "f%d", i - REG_FR);
4881 md.regsym[i] = declare_register (name, i);
4882 }
4883
4884 /* application registers: */
4885 total += 128;
4886 ar_base = i;
4887 for (; i < total; ++i)
4888 {
4889 sprintf (name, "ar%d", i - REG_AR);
4890 md.regsym[i] = declare_register (name, i);
4891 }
4892
4893 /* control registers: */
4894 total += 128;
4895 cr_base = i;
4896 for (; i < total; ++i)
4897 {
4898 sprintf (name, "cr%d", i - REG_CR);
4899 md.regsym[i] = declare_register (name, i);
4900 }
4901
4902 /* predicate registers: */
4903 total += 64;
4904 for (; i < total; ++i)
4905 {
4906 sprintf (name, "p%d", i - REG_P);
4907 md.regsym[i] = declare_register (name, i);
4908 }
4909
4910 /* branch registers: */
4911 total += 8;
4912 for (; i < total; ++i)
4913 {
4914 sprintf (name, "b%d", i - REG_BR);
4915 md.regsym[i] = declare_register (name, i);
4916 }
4917
4918 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
4919 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
4920 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
4921 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
4922 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
4923 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
4924 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
4925
4926 for (i = 0; i < NELEMS (indirect_reg); ++i)
4927 {
4928 regnum = indirect_reg[i].regnum;
4929 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
4930 }
4931
4932 /* define synonyms for application registers: */
4933 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
4934 md.regsym[i] = declare_register (ar[i - REG_AR].name,
4935 REG_AR + ar[i - REG_AR].regnum);
4936
4937 /* define synonyms for control registers: */
4938 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
4939 md.regsym[i] = declare_register (cr[i - REG_CR].name,
4940 REG_CR + cr[i - REG_CR].regnum);
4941
4942 declare_register ("gp", REG_GR + 1);
4943 declare_register ("sp", REG_GR + 12);
4944 declare_register ("rp", REG_BR + 0);
4945
4946 declare_register_set ("ret", 4, REG_GR + 8);
4947 declare_register_set ("farg", 8, REG_FR + 8);
4948 declare_register_set ("fret", 8, REG_FR + 8);
4949
4950 for (i = 0; i < NELEMS (const_bits); ++i)
4951 {
4952 err = hash_insert (md.const_hash, const_bits[i].name,
4953 (PTR) (const_bits + i));
4954 if (err)
4955 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
4956 name, err);
4957 }
4958
4959 /* Default to 64-bit mode. */
4960 md.flags = EF_IA_64_ABI64;
4961
4962 md.mem_offset.hint = 0;
4963 md.path = 0;
4964 md.maxpaths = 0;
4965 md.entry_labels = NULL;
4966}
4967
4968void
4969ia64_end_of_source ()
4970{
4971 /* terminate insn group upon reaching end of file: */
4972 insn_group_break (1, 0, 0);
4973
4974 /* emits slots we haven't written yet: */
4975 ia64_flush_insns ();
4976
4977 bfd_set_private_flags (stdoutput, md.flags);
4978
4979 if (debug_type == DEBUG_DWARF2)
4980 dwarf2_finish ();
4981
4982 md.mem_offset.hint = 0;
4983}
4984
4985void
4986ia64_start_line ()
4987{
4988 md.qp.X_op = O_absent;
4989
4990 if (ignore_input ())
4991 return;
4992
4993 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
4994 {
4995 if (md.detect_dv && !md.explicit_mode)
4996 as_warn (_("Explicit stops are ignored in auto mode"));
4997 else
4998 insn_group_break (1, 0, 0);
4999 }
5000}
5001
5002int
5003ia64_unrecognized_line (ch)
5004 int ch;
5005{
5006 switch (ch)
5007 {
5008 case '(':
5009 expression (&md.qp);
5010 if (*input_line_pointer++ != ')')
5011 {
5012 as_bad ("Expected ')'");
5013 return 0;
5014 }
5015 if (md.qp.X_op != O_register)
5016 {
5017 as_bad ("Qualifying predicate expected");
5018 return 0;
5019 }
5020 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
5021 {
5022 as_bad ("Predicate register expected");
5023 return 0;
5024 }
5025 return 1;
5026
5027 case '{':
5028 if (md.manual_bundling)
5029 as_warn ("Found '{' when manual bundling is already turned on");
5030 else
5031 CURR_SLOT.manual_bundling_on = 1;
5032 md.manual_bundling = 1;
5033
5034 /* bundling is only acceptable in explicit mode
5035 or when in default automatic mode */
5036 if (md.detect_dv && !md.explicit_mode)
5037 {
5038 if (!md.mode_explicitly_set
5039 && !md.default_explicit_mode)
5040 dot_dv_mode ('E');
5041 else
5042 as_warn (_("Found '{' after explicit switch to automatic mode"));
5043 }
5044 return 1;
5045
5046 case '}':
5047 if (!md.manual_bundling)
5048 as_warn ("Found '}' when manual bundling is off");
5049 else
5050 PREV_SLOT.manual_bundling_off = 1;
5051 md.manual_bundling = 0;
5052
5053 /* switch back to automatic mode, if applicable */
5054 if (md.detect_dv
5055 && md.explicit_mode
5056 && !md.mode_explicitly_set
5057 && !md.default_explicit_mode)
5058 dot_dv_mode ('A');
5059
5060 /* Allow '{' to follow on the same line. We also allow ";;", but that
5061 happens automatically because ';' is an end of line marker. */
5062 SKIP_WHITESPACE ();
5063 if (input_line_pointer[0] == '{')
5064 {
5065 input_line_pointer++;
5066 return ia64_unrecognized_line ('{');
5067 }
5068
5069 demand_empty_rest_of_line ();
5070 return 1;
5071
5072 default:
5073 break;
5074 }
5075 return 0; /* not a valid line */
5076}
5077
5078void
5079ia64_frob_label (sym)
5080 struct symbol *sym;
5081{
5082 struct label_fix *fix;
5083
5084 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
5085 {
5086 md.last_text_seg = now_seg;
5087 fix = obstack_alloc (&notes, sizeof (*fix));
5088 fix->sym = sym;
5089 fix->next = CURR_SLOT.label_fixups;
5090 CURR_SLOT.label_fixups = fix;
5091
5092 /* keep track of how many code entry points we've seen */
5093 if (md.path == md.maxpaths)
5094 {
5095 md.maxpaths += 20;
5096 md.entry_labels = (const char **)
5097 xrealloc ((void *)md.entry_labels, md.maxpaths * sizeof (char *));
5098 }
5099 md.entry_labels[md.path++] = S_GET_NAME (sym);
5100 }
5101}
5102
5103void
5104ia64_flush_pending_output ()
5105{
5106 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
5107 {
5108 /* ??? This causes many unnecessary stop bits to be emitted.
5109 Unfortunately, it isn't clear if it is safe to remove this. */
5110 insn_group_break (1, 0, 0);
5111 ia64_flush_insns ();
5112 }
5113}
5114
5115/* Do ia64-specific expression optimization. All that's done here is
5116 to transform index expressions that are either due to the indexing
5117 of rotating registers or due to the indexing of indirect register
5118 sets. */
5119int
5120ia64_optimize_expr (l, op, r)
5121 expressionS *l;
5122 operatorT op;
5123 expressionS *r;
5124{
5125 unsigned num_regs;
5126
5127 if (op == O_index)
5128 {
5129 if (l->X_op == O_register && r->X_op == O_constant)
5130 {
5131 num_regs = (l->X_add_number >> 16);
5132 if ((unsigned) r->X_add_number >= num_regs)
5133 {
5134 if (!num_regs)
5135 as_bad ("No current frame");
5136 else
5137 as_bad ("Index out of range 0..%u", num_regs - 1);
5138 r->X_add_number = 0;
5139 }
5140 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
5141 return 1;
5142 }
5143 else if (l->X_op == O_register && r->X_op == O_register)
5144 {
5145 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
5146 || l->X_add_number == IND_MEM)
5147 {
5148 as_bad ("Indirect register set name expected");
5149 l->X_add_number = IND_CPUID;
5150 }
5151 l->X_op = O_index;
5152 l->X_op_symbol = md.regsym[l->X_add_number];
5153 l->X_add_number = r->X_add_number;
5154 return 1;
5155 }
5156 }
5157 return 0;
5158}
5159
5160int
5161ia64_parse_name (name, e)
5162 char *name;
5163 expressionS *e;
5164{
5165 struct const_desc *cdesc;
5166 struct dynreg *dr = 0;
5167 unsigned int regnum;
5168 struct symbol *sym;
5169 char *end;
5170
5171 /* first see if NAME is a known register name: */
5172 sym = hash_find (md.reg_hash, name);
5173 if (sym)
5174 {
5175 e->X_op = O_register;
5176 e->X_add_number = S_GET_VALUE (sym);
5177 return 1;
5178 }
5179
5180 cdesc = hash_find (md.const_hash, name);
5181 if (cdesc)
5182 {
5183 e->X_op = O_constant;
5184 e->X_add_number = cdesc->value;
5185 return 1;
5186 }
5187
5188 /* check for inN, locN, or outN: */
5189 switch (name[0])
5190 {
5191 case 'i':
5192 if (name[1] == 'n' && isdigit (name[2]))
5193 {
5194 dr = &md.in;
5195 name += 2;
5196 }
5197 break;
5198
5199 case 'l':
5200 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
5201 {
5202 dr = &md.loc;
5203 name += 3;
5204 }
5205 break;
5206
5207 case 'o':
5208 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
5209 {
5210 dr = &md.out;
5211 name += 3;
5212 }
5213 break;
5214
5215 default:
5216 break;
5217 }
5218
5219 if (dr)
5220 {
5221 /* the name is inN, locN, or outN; parse the register number: */
5222 regnum = strtoul (name, &end, 10);
5223 if (end > name && *end == '\0')
5224 {
5225 if ((unsigned) regnum >= dr->num_regs)
5226 {
5227 if (!dr->num_regs)
5228 as_bad ("No current frame");
5229 else
5230 as_bad ("Register number out of range 0..%u", dr->num_regs-1);
5231 regnum = 0;
5232 }
5233 e->X_op = O_register;
5234 e->X_add_number = dr->base + regnum;
5235 return 1;
5236 }
5237 }
5238
5239 if ((dr = hash_find (md.dynreg_hash, name)))
5240 {
5241 /* We've got ourselves the name of a rotating register set.
5242 Store the base register number in the low 16 bits of
5243 X_add_number and the size of the register set in the top 16
5244 bits. */
5245 e->X_op = O_register;
5246 e->X_add_number = dr->base | (dr->num_regs << 16);
5247 return 1;
5248 }
5249 return 0;
5250}
5251
5252/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
5253
5254char *
5255ia64_canonicalize_symbol_name (name)
5256 char *name;
5257{
5258 size_t len = strlen(name);
5259 if (len > 1 && name[len-1] == '#')
5260 name[len-1] = '\0';
5261 return name;
5262}
5263
5264static int
5265is_conditional_branch (idesc)
5266 struct ia64_opcode *idesc;
5267{
5268 return (strncmp (idesc->name, "br", 2) == 0
5269 && (strcmp (idesc->name, "br") == 0
5270 || strncmp (idesc->name, "br.cond", 7) == 0
5271 || strncmp (idesc->name, "br.call", 7) == 0
5272 || strncmp (idesc->name, "br.ret", 6) == 0
5273 || strcmp (idesc->name, "brl") == 0
5274 || strncmp (idesc->name, "brl.cond", 7) == 0
5275 || strncmp (idesc->name, "brl.call", 7) == 0
5276 || strncmp (idesc->name, "brl.ret", 6) == 0));
5277}
5278
5279/* Return whether the given opcode is a taken branch. If there's any doubt,
5280 returns zero */
5281static int
5282is_taken_branch (idesc)
5283 struct ia64_opcode *idesc;
5284{
5285 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
5286 || strncmp (idesc->name, "br.ia", 5) == 0);
5287}
5288
5289/* Return whether the given opcode is an interruption or rfi. If there's any
5290 doubt, returns zero */
5291static int
5292is_interruption_or_rfi (idesc)
5293 struct ia64_opcode *idesc;
5294{
5295 if (strcmp (idesc->name, "rfi") == 0)
5296 return 1;
5297 return 0;
5298}
5299
5300/* Returns the index of the given dependency in the opcode's list of chks, or
5301 -1 if there is no dependency. */
5302static int
5303depends_on (depind, idesc)
5304 int depind;
5305 struct ia64_opcode *idesc;
5306{
5307 int i;
5308 const struct ia64_opcode_dependency *dep = idesc->dependencies;
5309 for (i = 0;i < dep->nchks; i++)
5310 {
5311 if (depind == DEP(dep->chks[i]))
5312 return i;
5313 }
5314 return -1;
5315}
5316
5317/* Determine a set of specific resources used for a particular resource
5318 class. Returns the number of specific resources identified For those
5319 cases which are not determinable statically, the resource returned is
5320 marked nonspecific.
5321
5322 Meanings of value in 'NOTE':
5323 1) only read/write when the register number is explicitly encoded in the
5324 insn.
5325 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
5326 accesses CFM when qualifying predicate is in the rotating region.
5327 3) general register value is used to specify an indirect register; not
5328 determinable statically.
5329 4) only read the given resource when bits 7:0 of the indirect index
5330 register value does not match the register number of the resource; not
5331 determinable statically.
5332 5) all rules are implementation specific.
5333 6) only when both the index specified by the reader and the index specified
5334 by the writer have the same value in bits 63:61; not determinable
5335 statically.
5336 7) only access the specified resource when the corresponding mask bit is
5337 set
5338 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
5339 only read when these insns reference FR2-31
5340 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
5341 written when these insns write FR32-127
5342 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
5343 instruction
5344 11) The target predicates are written independently of PR[qp], but source
5345 registers are only read if PR[qp] is true. Since the state of PR[qp]
5346 cannot statically be determined, all source registers are marked used.
5347 12) This insn only reads the specified predicate register when that
5348 register is the PR[qp].
5349 13) This reference to ld-c only applies to teh GR whose value is loaded
5350 with data returned from memory, not the post-incremented address register.
5351 14) The RSE resource includes the implementation-specific RSE internal
5352 state resources. At least one (and possibly more) of these resources are
5353 read by each instruction listed in IC:rse-readers. At least one (and
5354 possibly more) of these resources are written by each insn listed in
5355 IC:rse-writers.
5356 15+16) Represents reserved instructions, which the assembler does not
5357 generate.
5358
5359 Memory resources (i.e. locations in memory) are *not* marked or tracked by
5360 this code; there are no dependency violations based on memory access.
5361
5362*/
5363
5364#define MAX_SPECS 256
5365#define DV_CHK 1
5366#define DV_REG 0
5367
5368static int
5369specify_resource (dep, idesc, type, specs, note, path)
5370 const struct ia64_dependency *dep;
5371 struct ia64_opcode *idesc;
5372 int type; /* is this a DV chk or a DV reg? */
5373 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
5374 int note; /* resource note for this insn's usage */
5375 int path; /* which execution path to examine */
5376{
5377 int count = 0;
5378 int i;
5379 int rsrc_write = 0;
5380 struct rsrc tmpl;
5381
5382 if (dep->mode == IA64_DV_WAW
5383 || (dep->mode == IA64_DV_RAW && type == DV_REG)
5384 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
5385 rsrc_write = 1;
5386
5387 /* template for any resources we identify */
5388 tmpl.dependency = dep;
5389 tmpl.note = note;
5390 tmpl.insn_srlz = tmpl.data_srlz = 0;
5391 tmpl.qp_regno = CURR_SLOT.qp_regno;
5392 tmpl.link_to_qp_branch = 1;
5393 tmpl.mem_offset.hint = 0;
5394 tmpl.specific = 1;
5395 tmpl.index = 0;
5396
5397#define UNHANDLED \
5398as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
5399dep->name, idesc->name, (rsrc_write?"write":"read"), note)
5400#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
5401
5402 /* we don't need to track these */
5403 if (dep->semantics == IA64_DVS_NONE)
5404 return 0;
5405
5406 switch (dep->specifier)
5407 {
5408 case IA64_RS_AR_K:
5409 if (note == 1)
5410 {
5411 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
5412 {
5413 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
5414 if (regno >= 0 && regno <= 7)
5415 {
5416 specs[count] = tmpl;
5417 specs[count++].index = regno;
5418 }
5419 }
5420 }
5421 else if (note == 0)
5422 {
5423 for(i=0;i < 8;i++)
5424 {
5425 specs[count] = tmpl;
5426 specs[count++].index = i;
5427 }
5428 }
5429 else
5430 {
5431 UNHANDLED;
5432 }
5433 break;
5434
5435 case IA64_RS_AR_UNAT:
5436 /* This is a mov =AR or mov AR= instruction. */
5437 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
5438 {
5439 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
5440 if (regno == AR_UNAT)
5441 {
5442 specs[count++] = tmpl;
5443 }
5444 }
5445 else
5446 {
5447 /* This is a spill/fill, or other instruction that modifies the
5448 unat register. */
5449
5450 /* Unless we can determine the specific bits used, mark the whole
5451 thing; bits 8:3 of the memory address indicate the bit used in
5452 UNAT. The .mem.offset hint may be used to eliminate a small
5453 subset of conflicts. */
5454 specs[count] = tmpl;
5455 if (md.mem_offset.hint)
5456 {
5457 if (md.debug_dv)
5458 fprintf (stderr, " Using hint for spill/fill\n");
5459 /* the index isn't actually used, just set it to something
5460 approximating the bit index */
5461 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
5462 specs[count].mem_offset.hint = 1;
5463 specs[count].mem_offset.offset = md.mem_offset.offset;
5464 specs[count++].mem_offset.base = md.mem_offset.base;
5465 }
5466 else
5467 {
5468 specs[count++].specific = 0;
5469 }
5470 }
5471 break;
5472
5473 case IA64_RS_AR:
5474 if (note == 1)
5475 {
5476 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
5477 {
5478 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
5479 if ((regno >= 8 && regno <= 15)
5480 || (regno >= 20 && regno <= 23)
5481 || (regno >= 31 && regno <= 39)
5482 || (regno >= 41 && regno <= 47)
5483 || (regno >= 67 && regno <= 111))
5484 {
5485 specs[count] = tmpl;
5486 specs[count++].index = regno;
5487 }
5488 }
5489 }
5490 else
5491 {
5492 UNHANDLED;
5493 }
5494 break;
5495
5496 case IA64_RS_ARb:
5497 if (note == 1)
5498 {
5499 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
5500 {
5501 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
5502 if ((regno >= 48 && regno <= 63)
5503 || (regno >= 112 && regno <= 127))
5504 {
5505 specs[count] = tmpl;
5506 specs[count++].index = regno;
5507 }
5508 }
5509 }
5510 else if (note == 0)
5511 {
5512 for (i=48;i < 64;i++)
5513 {
5514 specs[count] = tmpl;
5515 specs[count++].index = i;
5516 }
5517 for (i=112;i < 128;i++)
5518 {
5519 specs[count] = tmpl;
5520 specs[count++].index = i;
5521 }
5522 }
5523 else
5524 {
5525 UNHANDLED;
5526 }
5527 break;
5528
5529 case IA64_RS_BR:
5530 if (note != 1)
5531 {
5532 UNHANDLED;
5533 }
5534 else
5535 {
5536 if (rsrc_write)
5537 {
5538 for (i=0;i < idesc->num_outputs;i++)
5539 if (idesc->operands[i] == IA64_OPND_B1
5540 || idesc->operands[i] == IA64_OPND_B2)
5541 {
5542 specs[count] = tmpl;
5543 specs[count++].index =
5544 CURR_SLOT.opnd[i].X_add_number - REG_BR;
5545 }
5546 }
5547 else
5548 {
5549 for (i = idesc->num_outputs;i < NELEMS(idesc->operands);i++)
5550 if (idesc->operands[i] == IA64_OPND_B1
5551 || idesc->operands[i] == IA64_OPND_B2)
5552 {
5553 specs[count] = tmpl;
5554 specs[count++].index =
5555 CURR_SLOT.opnd[i].X_add_number - REG_BR;
5556 }
5557 }
5558 }
5559 break;
5560
5561 case IA64_RS_CPUID: /* four or more registers */
5562 if (note == 3)
5563 {
5564 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
5565 {
5566 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
5567 if (regno >= 0 && regno < NELEMS(gr_values)
5568 && KNOWN(regno))
5569 {
5570 specs[count] = tmpl;
5571 specs[count++].index = gr_values[regno].value & 0xFF;
5572 }
5573 else
5574 {
5575 specs[count] = tmpl;
5576 specs[count++].specific = 0;
5577 }
5578 }
5579 }
5580 else
5581 {
5582 UNHANDLED;
5583 }
5584 break;
5585
5586 case IA64_RS_DBR: /* four or more registers */
5587 if (note == 3)
5588 {
5589 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
5590 {
5591 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
5592 if (regno >= 0 && regno < NELEMS(gr_values)
5593 && KNOWN(regno))
5594 {
5595 specs[count] = tmpl;
5596 specs[count++].index = gr_values[regno].value & 0xFF;
5597 }
5598 else
5599 {
5600 specs[count] = tmpl;
5601 specs[count++].specific = 0;
5602 }
5603 }
5604 }
5605 else if (note == 0 && !rsrc_write)
5606 {
5607 specs[count] = tmpl;
5608 specs[count++].specific = 0;
5609 }
5610 else
5611 {
5612 UNHANDLED;
5613 }
5614 break;
5615
5616 case IA64_RS_IBR: /* four or more registers */
5617 if (note == 3)
5618 {
5619 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
5620 {
5621 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
5622 if (regno >= 0 && regno < NELEMS(gr_values)
5623 && KNOWN(regno))
5624 {
5625 specs[count] = tmpl;
5626 specs[count++].index = gr_values[regno].value & 0xFF;
5627 }
5628 else
5629 {
5630 specs[count] = tmpl;
5631 specs[count++].specific = 0;
5632 }
5633 }
5634 }
5635 else
5636 {
5637 UNHANDLED;
5638 }
5639 break;
5640
5641 case IA64_RS_MSR:
5642 if (note == 5)
5643 {
5644 /* These are implementation specific. Force all references to
5645 conflict with all other references. */
5646 specs[count] = tmpl;
5647 specs[count++].specific = 0;
5648 }
5649 else
5650 {
5651 UNHANDLED;
5652 }
5653 break;
5654
5655 case IA64_RS_PKR: /* 16 or more registers */
5656 if (note == 3 || note == 4)
5657 {
5658 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
5659 {
5660 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
5661 if (regno >= 0 && regno < NELEMS(gr_values)
5662 && KNOWN(regno))
5663 {
5664 if (note == 3)
5665 {
5666 specs[count] = tmpl;
5667 specs[count++].index = gr_values[regno].value & 0xFF;
5668 }
5669 else for (i=0;i < NELEMS(gr_values);i++)
5670 {
5671 /* uses all registers *except* the one in R3 */
5672 if (i != (gr_values[regno].value & 0xFF))
5673 {
5674 specs[count] = tmpl;
5675 specs[count++].index = i;
5676 }
5677 }
5678 }
5679 else
5680 {
5681 specs[count] = tmpl;
5682 specs[count++].specific = 0;
5683 }
5684 }
5685 }
5686 else if (note == 0)
5687 {
5688 /* probe et al. */
5689 specs[count] = tmpl;
5690 specs[count++].specific = 0;
5691 }
5692 break;
5693
5694 case IA64_RS_PMC: /* four or more registers */
5695 if (note == 3)
5696 {
5697 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
5698 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
5699
5700 {
5701 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
5702 ? 1 : !rsrc_write);
5703 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
5704 if (regno >= 0 && regno < NELEMS(gr_values)
5705 && KNOWN(regno))
5706 {
5707 specs[count] = tmpl;
5708 specs[count++].index = gr_values[regno].value & 0xFF;
5709 }
5710 else
5711 {
5712 specs[count] = tmpl;
5713 specs[count++].specific = 0;
5714 }
5715 }
5716 }
5717 else
5718 {
5719 UNHANDLED;
5720 }
5721 break;
5722
5723 case IA64_RS_PMD: /* four or more registers */
5724 if (note == 3)
5725 {
5726 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
5727 {
5728 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
5729 if (regno >= 0 && regno < NELEMS(gr_values)
5730 && KNOWN(regno))
5731 {
5732 specs[count] = tmpl;
5733 specs[count++].index = gr_values[regno].value & 0xFF;
5734 }
5735 else
5736 {
5737 specs[count] = tmpl;
5738 specs[count++].specific = 0;
5739 }
5740 }
5741 }
5742 else
5743 {
5744 UNHANDLED;
5745 }
5746 break;
5747
5748 case IA64_RS_RR: /* eight registers */
5749 if (note == 6)
5750 {
5751 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
5752 {
5753 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
5754 if (regno >= 0 && regno < NELEMS(gr_values)
5755 && KNOWN(regno))
5756 {
5757 specs[count] = tmpl;
5758 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
5759 }
5760 else
5761 {
5762 specs[count] = tmpl;
5763 specs[count++].specific = 0;
5764 }
5765 }
5766 }
5767 else if (note == 0 && !rsrc_write)
5768 {
5769 specs[count] = tmpl;
5770 specs[count++].specific = 0;
5771 }
5772 else
5773 {
5774 UNHANDLED;
5775 }
5776 break;
5777
5778 case IA64_RS_CR_IRR:
5779 if (note == 0)
5780 {
5781 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
5782 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
5783 if (rsrc_write
5784 && idesc->operands[1] == IA64_OPND_CR3
5785 && regno == CR_IVR)
5786 {
5787 for(i=0;i < 4;i++)
5788 {
5789 specs[count] = tmpl;
5790 specs[count++].index = CR_IRR0 + i;
5791 }
5792 }
5793 }
5794 else if (note == 1)
5795 {
5796 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
5797 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
5798 && regno >= CR_IRR0
5799 && regno <= CR_IRR3)
5800 {
5801 specs[count] = tmpl;
5802 specs[count++].index = regno;
5803 }
5804 }
5805 else
5806 {
5807 UNHANDLED;
5808 }
5809 break;
5810
5811 case IA64_RS_CR_LRR:
5812 if (note != 1)
5813 {
5814 UNHANDLED;
5815 }
5816 else
5817 {
5818 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
5819 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
5820 && (regno == CR_LRR0 || regno == CR_LRR1))
5821 {
5822 specs[count] = tmpl;
5823 specs[count++].index = regno;
5824 }
5825 }
5826 break;
5827
5828 case IA64_RS_CR:
5829 if (note == 1)
5830 {
5831 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
5832 {
5833 specs[count] = tmpl;
5834 specs[count++].index =
5835 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
5836 }
5837 }
5838 else
5839 {
5840 UNHANDLED;
5841 }
5842 break;
5843
5844 case IA64_RS_FR:
5845 case IA64_RS_FRb:
5846 if (note != 1)
5847 {
5848 UNHANDLED;
5849 }
5850 else if (rsrc_write)
5851 {
5852 if (dep->specifier == IA64_RS_FRb
5853 && idesc->operands[0] == IA64_OPND_F1)
5854 {
5855 specs[count] = tmpl;
5856 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
5857 }
5858 }
5859 else
5860 {
5861 for (i=idesc->num_outputs;i < NELEMS(idesc->operands);i++)
5862 {
5863 if (idesc->operands[i] == IA64_OPND_F2
5864 || idesc->operands[i] == IA64_OPND_F3
5865 || idesc->operands[i] == IA64_OPND_F4)
5866 {
5867 specs[count] = tmpl;
5868 specs[count++].index =
5869 CURR_SLOT.opnd[i].X_add_number - REG_FR;
5870 }
5871 }
5872 }
5873 break;
5874
5875 case IA64_RS_GR:
5876 if (note == 13)
5877 {
5878 /* This reference applies only to the GR whose value is loaded with
5879 data returned from memory */
5880 specs[count] = tmpl;
5881 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
5882 }
5883 else if (note == 1)
5884 {
5885 if (rsrc_write)
5886 {
5887 for (i=0;i < idesc->num_outputs;i++)
5888 {
5889 if (idesc->operands[i] == IA64_OPND_R1
5890 || idesc->operands[i] == IA64_OPND_R2
5891 || idesc->operands[i] == IA64_OPND_R3)
5892 {
5893 specs[count] = tmpl;
5894 specs[count++].index =
5895 CURR_SLOT.opnd[i].X_add_number - REG_GR;
5896 }
5897 }
5898 }
5899 else
5900 {
5901 /* Look for anything that reads a GR */
5902 for (i=0;i < NELEMS(idesc->operands);i++)
5903 {
5904 if (idesc->operands[i] == IA64_OPND_MR3
5905 || idesc->operands[i] == IA64_OPND_CPUID_R3
5906 || idesc->operands[i] == IA64_OPND_DBR_R3
5907 || idesc->operands[i] == IA64_OPND_IBR_R3
5908 || idesc->operands[i] == IA64_OPND_MSR_R3
5909 || idesc->operands[i] == IA64_OPND_PKR_R3
5910 || idesc->operands[i] == IA64_OPND_PMC_R3
5911 || idesc->operands[i] == IA64_OPND_PMD_R3
5912 || idesc->operands[i] == IA64_OPND_RR_R3
5913 || ((i >= idesc->num_outputs)
5914 && (idesc->operands[i] == IA64_OPND_R1
5915 || idesc->operands[i] == IA64_OPND_R2
5916 || idesc->operands[i] == IA64_OPND_R3)))
5917 {
5918 specs[count] = tmpl;
5919 specs[count++].index =
5920 CURR_SLOT.opnd[i].X_add_number - REG_GR;
5921 }
5922 }
5923 }
5924 }
5925 else
5926 {
5927 UNHANDLED;
5928 }
5929 break;
5930
5931 case IA64_RS_PR:
5932 if (note == 0)
5933 {
5934 if (idesc->operands[0] == IA64_OPND_PR_ROT)
5935 {
5936 for (i=16;i < 63;i++)
5937 {
5938 specs[count] = tmpl;
5939 specs[count++].index = i;
5940 }
5941 }
5942 else
5943 {
5944 for (i=1;i < 63;i++)
5945 {
5946 specs[count] = tmpl;
5947 specs[count++].index = i;
5948 }
5949 }
5950 }
5951 else if (note == 7)
5952 {
5953 valueT mask = 0;
5954 /* mark only those registers indicated by the mask */
5955 if (rsrc_write
5956 && idesc->operands[0] == IA64_OPND_PR)
5957 {
5958 mask = CURR_SLOT.opnd[2].X_add_number;
5959 if (mask & ((valueT)1<<16))
5960 mask |= ~(valueT)0xffff;
5961 for (i=1;i < 63;i++)
5962 {
5963 if (mask & ((valueT)1<<i))
5964 {
5965 specs[count] = tmpl;
5966 specs[count++].index = i;
5967 }
5968 }
5969 }
5970 else if (rsrc_write
5971 && idesc->operands[0] == IA64_OPND_PR_ROT)
5972 {
5973 for (i=16;i < 63;i++)
5974 {
5975 specs[count] = tmpl;
5976 specs[count++].index = i;
5977 }
5978 }
5979 else
5980 {
5981 UNHANDLED;
5982 }
5983 }
5984 else if (note == 11) /* note 11 implies note 1 as well */
5985 {
5986 if (rsrc_write)
5987 {
5988 for (i=0;i < idesc->num_outputs;i++)
5989 {
5990 if (idesc->operands[i] == IA64_OPND_P1
5991 || idesc->operands[i] == IA64_OPND_P2)
5992 {
5993 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
5994 if (regno != 0)
5995 {
5996 specs[count] = tmpl;
5997 specs[count++].index = regno;
5998 }
5999 }
6000 }
6001 }
6002 else
6003 {
6004 UNHANDLED;
6005 }
6006 }
6007 else if (note == 12)
6008 {
6009 if (CURR_SLOT.qp_regno != 0)
6010 {
6011 specs[count] = tmpl;
6012 specs[count++].index = CURR_SLOT.qp_regno;
6013 }
6014 }
6015 else if (note == 1)
6016 {
6017 if (rsrc_write)
6018 {
6019 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
6020 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
6021 if ((idesc->operands[0] == IA64_OPND_P1
6022 || idesc->operands[0] == IA64_OPND_P2)
6023 && p1 != 0 && p1 != 63)
6024 {
6025 specs[count] = tmpl;
6026 specs[count++].index = p1;
6027 }
6028 if ((idesc->operands[1] == IA64_OPND_P1
6029 || idesc->operands[1] == IA64_OPND_P2)
6030 && p2 != 0 && p2 != 63)
6031 {
6032 specs[count] = tmpl;
6033 specs[count++].index = p2;
6034 }
6035 }
6036 else
6037 {
6038 if (CURR_SLOT.qp_regno != 0)
6039 {
6040 specs[count] = tmpl;
6041 specs[count++].index = CURR_SLOT.qp_regno;
6042 }
6043 if (idesc->operands[1] == IA64_OPND_PR)
6044 {
6045 for (i=1;i < 63;i++)
6046 {
6047 specs[count] = tmpl;
6048 specs[count++].index = i;
6049 }
6050 }
6051 }
6052 }
6053 else
6054 {
6055 UNHANDLED;
6056 }
6057 break;
6058
6059 case IA64_RS_PSR:
6060 /* Verify that the instruction is using the PSR bit indicated in
6061 dep->regindex */
6062 if (note == 0)
6063 {
6064 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
6065 {
6066 if (dep->regindex < 6)
6067 {
6068 specs[count++] = tmpl;
6069 }
6070 }
6071 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
6072 {
6073 if (dep->regindex < 32
6074 || dep->regindex == 35
6075 || dep->regindex == 36
6076 || (!rsrc_write && dep->regindex == PSR_CPL))
6077 {
6078 specs[count++] = tmpl;
6079 }
6080 }
6081 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
6082 {
6083 if (dep->regindex < 32
6084 || dep->regindex == 35
6085 || dep->regindex == 36
6086 || (rsrc_write && dep->regindex == PSR_CPL))
6087 {
6088 specs[count++] = tmpl;
6089 }
6090 }
6091 else
6092 {
6093 /* Several PSR bits have very specific dependencies. */
6094 switch (dep->regindex)
6095 {
6096 default:
6097 specs[count++] = tmpl;
6098 break;
6099 case PSR_IC:
6100 if (rsrc_write)
6101 {
6102 specs[count++] = tmpl;
6103 }
6104 else
6105 {
6106 /* Only certain CR accesses use PSR.ic */
6107 if (idesc->operands[0] == IA64_OPND_CR3
6108 || idesc->operands[1] == IA64_OPND_CR3)
6109 {
6110 int index =
6111 ((idesc->operands[0] == IA64_OPND_CR3)
6112 ? 0 : 1);
6113 int regno =
6114 CURR_SLOT.opnd[index].X_add_number - REG_CR;
6115
6116 switch (regno)
6117 {
6118 default:
6119 break;
6120 case CR_ITIR:
6121 case CR_IFS:
6122 case CR_IIM:
6123 case CR_IIP:
6124 case CR_IPSR:
6125 case CR_ISR:
6126 case CR_IFA:
6127 case CR_IHA:
6128 case CR_IIPA:
6129 specs[count++] = tmpl;
6130 break;
6131 }
6132 }
6133 }
6134 break;
6135 case PSR_CPL:
6136 if (rsrc_write)
6137 {
6138 specs[count++] = tmpl;
6139 }
6140 else
6141 {
6142 /* Only some AR accesses use cpl */
6143 if (idesc->operands[0] == IA64_OPND_AR3
6144 || idesc->operands[1] == IA64_OPND_AR3)
6145 {
6146 int index =
6147 ((idesc->operands[0] == IA64_OPND_AR3)
6148 ? 0 : 1);
6149 int regno =
6150 CURR_SLOT.opnd[index].X_add_number - REG_AR;
6151
6152 if (regno == AR_ITC
6153 || (index == 0
6154 && (regno == AR_ITC
6155 || regno == AR_RSC
6156 || (regno >= AR_K0
6157 && regno <= AR_K7))))
6158 {
6159 specs[count++] = tmpl;
6160 }
6161 }
6162 else
6163 {
6164 specs[count++] = tmpl;
6165 }
6166 break;
6167 }
6168 }
6169 }
6170 }
6171 else if (note == 7)
6172 {
6173 valueT mask = 0;
6174 if (idesc->operands[0] == IA64_OPND_IMMU24)
6175 {
6176 mask = CURR_SLOT.opnd[0].X_add_number;
6177 }
6178 else
6179 {
6180 UNHANDLED;
6181 }
6182 if (mask & ((valueT)1<<dep->regindex))
6183 {
6184 specs[count++] = tmpl;
6185 }
6186 }
6187 else if (note == 8)
6188 {
6189 int min = dep->regindex == PSR_DFL ? 2 : 32;
6190 int max = dep->regindex == PSR_DFL ? 31 : 127;
6191 /* dfh is read on FR32-127; dfl is read on FR2-31 */
6192 for (i=0;i < NELEMS(idesc->operands);i++)
6193 {
6194 if (idesc->operands[i] == IA64_OPND_F1
6195 || idesc->operands[i] == IA64_OPND_F2
6196 || idesc->operands[i] == IA64_OPND_F3
6197 || idesc->operands[i] == IA64_OPND_F4)
6198 {
6199 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
6200 if (reg >= min && reg <= max)
6201 {
6202 specs[count++] = tmpl;
6203 }
6204 }
6205 }
6206 }
6207 else if (note == 9)
6208 {
6209 int min = dep->regindex == PSR_MFL ? 2 : 32;
6210 int max = dep->regindex == PSR_MFL ? 31 : 127;
6211 /* mfh is read on writes to FR32-127; mfl is read on writes to
6212 FR2-31 */
6213 for (i=0;i < idesc->num_outputs;i++)
6214 {
6215 if (idesc->operands[i] == IA64_OPND_F1)
6216 {
6217 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
6218 if (reg >= min && reg <= max)
6219 {
6220 specs[count++] = tmpl;
6221 }
6222 }
6223 }
6224 }
6225 else if (note == 10)
6226 {
6227 for (i=0;i < NELEMS(idesc->operands);i++)
6228 {
6229 if (idesc->operands[i] == IA64_OPND_R1
6230 || idesc->operands[i] == IA64_OPND_R2
6231 || idesc->operands[i] == IA64_OPND_R3)
6232 {
6233 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
6234 if (regno >= 16 && regno <= 31)
6235 {
6236 specs[count++] = tmpl;
6237 }
6238 }
6239 }
6240 }
6241 else
6242 {
6243 UNHANDLED;
6244 }
6245 break;
6246
6247 case IA64_RS_AR_FPSR:
6248 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6249 {
6250 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6251 if (regno == AR_FPSR)
6252 {
6253 specs[count++] = tmpl;
6254 }
6255 }
6256 else
6257 {
6258 specs[count++] = tmpl;
6259 }
6260 break;
6261
6262 case IA64_RS_ARX:
6263 /* Handle all AR[REG] resources */
6264 if (note == 0 || note == 1)
6265 {
6266 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6267 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
6268 && regno == dep->regindex)
6269 {
6270 specs[count++] = tmpl;
6271 }
6272 /* other AR[REG] resources may be affected by AR accesses */
6273 else if (idesc->operands[0] == IA64_OPND_AR3)
6274 {
6275 /* AR[] writes */
6276 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
6277 switch (dep->regindex)
6278 {
6279 default:
6280 break;
6281 case AR_BSP:
6282 case AR_RNAT:
6283 if (regno == AR_BSPSTORE)
6284 {
6285 specs[count++] = tmpl;
6286 }
6287 case AR_RSC:
6288 if (!rsrc_write &&
6289 (regno == AR_BSPSTORE
6290 || regno == AR_RNAT))
6291 {
6292 specs[count++] = tmpl;
6293 }
6294 break;
6295 }
6296 }
6297 else if (idesc->operands[1] == IA64_OPND_AR3)
6298 {
6299 /* AR[] reads */
6300 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
6301 switch (dep->regindex)
6302 {
6303 default:
6304 break;
6305 case AR_RSC:
6306 if (regno == AR_BSPSTORE || regno == AR_RNAT)
6307 {
6308 specs[count++] = tmpl;
6309 }
6310 break;
6311 }
6312 }
6313 else
6314 {
6315 specs[count++] = tmpl;
6316 }
6317 }
6318 else
6319 {
6320 UNHANDLED;
6321 }
6322 break;
6323
6324 case IA64_RS_CRX:
6325 /* Handle all CR[REG] resources */
6326 if (note == 0 || note == 1)
6327 {
6328 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
6329 {
6330 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6331 if (regno == dep->regindex)
6332 {
6333 specs[count++] = tmpl;
6334 }
6335 else if (!rsrc_write)
6336 {
6337 /* Reads from CR[IVR] affect other resources. */
6338 if (regno == CR_IVR)
6339 {
6340 if ((dep->regindex >= CR_IRR0
6341 && dep->regindex <= CR_IRR3)
6342 || dep->regindex == CR_TPR)
6343 {
6344 specs[count++] = tmpl;
6345 }
6346 }
6347 }
6348 }
6349 else
6350 {
6351 specs[count++] = tmpl;
6352 }
6353 }
6354 else
6355 {
6356 UNHANDLED;
6357 }
6358 break;
6359
6360 case IA64_RS_INSERVICE:
6361 /* look for write of EOI (67) or read of IVR (65) */
6362 if ((idesc->operands[0] == IA64_OPND_CR3
6363 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
6364 || (idesc->operands[1] == IA64_OPND_CR3
6365 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
6366 {
6367 specs[count++] = tmpl;
6368 }
6369 break;
6370
6371 case IA64_RS_GR0:
6372 if (note == 1)
6373 {
6374 specs[count++] = tmpl;
6375 }
6376 else
6377 {
6378 UNHANDLED;
6379 }
6380 break;
6381
6382 case IA64_RS_CFM:
6383 if (note != 2)
6384 {
6385 specs[count++] = tmpl;
6386 }
6387 else
6388 {
6389 /* Check if any of the registers accessed are in the rotating region.
6390 mov to/from pr accesses CFM only when qp_regno is in the rotating
6391 region */
6392 for (i=0;i < NELEMS(idesc->operands);i++)
6393 {
6394 if (idesc->operands[i] == IA64_OPND_R1
6395 || idesc->operands[i] == IA64_OPND_R2
6396 || idesc->operands[i] == IA64_OPND_R3)
6397 {
6398 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
6399 /* Assumes that md.rot.num_regs is always valid */
6400 if (md.rot.num_regs > 0
6401 && num > 31
6402 && num < 31 + md.rot.num_regs)
6403 {
6404 specs[count] = tmpl;
6405 specs[count++].specific = 0;
6406 }
6407 }
6408 else if (idesc->operands[i] == IA64_OPND_F1
6409 || idesc->operands[i] == IA64_OPND_F2
6410 || idesc->operands[i] == IA64_OPND_F3
6411 || idesc->operands[i] == IA64_OPND_F4)
6412 {
6413 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
6414 if (num > 31)
6415 {
6416 specs[count] = tmpl;
6417 specs[count++].specific = 0;
6418 }
6419 }
6420 else if (idesc->operands[i] == IA64_OPND_P1
6421 || idesc->operands[i] == IA64_OPND_P2)
6422 {
6423 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
6424 if (num > 15)
6425 {
6426 specs[count] = tmpl;
6427 specs[count++].specific = 0;
6428 }
6429 }
6430 }
6431 if (CURR_SLOT.qp_regno > 15)
6432 {
6433 specs[count] = tmpl;
6434 specs[count++].specific = 0;
6435 }
6436 }
6437 break;
6438
6439 case IA64_RS_PR63:
6440 if (note == 0)
6441 {
6442 specs[count++] = tmpl;
6443 }
6444 else if (note == 11)
6445 {
6446 if ((idesc->operands[0] == IA64_OPND_P1
6447 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
6448 || (idesc->operands[1] == IA64_OPND_P2
6449 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
6450 {
6451 specs[count++] = tmpl;
6452 }
6453 }
6454 else if (note == 12)
6455 {
6456 if (CURR_SLOT.qp_regno == 63)
6457 {
6458 specs[count++] = tmpl;
6459 }
6460 }
6461 else if (note == 7)
6462 {
6463 valueT mask = 0;
6464 if (idesc->operands[2] == IA64_OPND_IMM17)
6465 mask = CURR_SLOT.opnd[2].X_add_number;
6466 if (mask & ((valueT)1<<63))
6467 {
6468 specs[count++] = tmpl;
6469 }
6470 }
6471 else if (note == 1)
6472 {
6473 if (rsrc_write)
6474 {
6475 for (i=0;i < idesc->num_outputs;i++)
6476 if ((idesc->operands[i] == IA64_OPND_P1
6477 || idesc->operands[i] == IA64_OPND_P2)
6478 && CURR_SLOT.opnd[i].X_add_number - REG_P == 63)
6479 {
6480 specs[count++] = tmpl;
6481 }
6482 }
6483 else
6484 {
6485 if (CURR_SLOT.qp_regno == 63)
6486 {
6487 specs[count++] = tmpl;
6488 }
6489 }
6490 }
6491 else
6492 {
6493 UNHANDLED;
6494 }
6495 break;
6496
6497 case IA64_RS_RSE:
6498 /* FIXME we can identify some individual RSE written resources, but RSE
6499 read resources have not yet been completely identified, so for now
6500 treat RSE as a single resource */
6501 if (strncmp (idesc->name, "mov", 3) == 0)
6502 {
6503 if (rsrc_write)
6504 {
6505 if (idesc->operands[0] == IA64_OPND_AR3
6506 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
6507 {
6508 specs[count] = tmpl;
6509 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
6510 }
6511 }
6512 else
6513 {
6514 if (idesc->operands[0] == IA64_OPND_AR3)
6515 {
6516 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
6517 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
6518 {
6519 specs[count++] = tmpl;
6520 }
6521 }
6522 else if (idesc->operands[1] == IA64_OPND_AR3)
6523 {
6524 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
6525 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
6526 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
6527 {
6528 specs[count++] = tmpl;
6529 }
6530 }
6531 }
6532 }
6533 else
6534 {
6535 specs[count++] = tmpl;
6536 }
6537 break;
6538
6539 case IA64_RS_ANY:
6540 /* FIXME -- do any of these need to be non-specific? */
6541 specs[count++] = tmpl;
6542 break;
6543
6544 default:
6545 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
6546 break;
6547 }
6548
6549 return count;
6550}
6551
6552/* Clear branch flags on marked resources. This breaks the link between the
6553 QP of the marking instruction and a subsequent branch on the same QP.
6554*/
6555static void
6556clear_qp_branch_flag (mask)
6557 valueT mask;
6558{
6559 int i;
6560 for (i = 0;i < regdepslen;i++)
6561 {
6562 valueT bit = ((valueT)1 << regdeps[i].qp_regno);
6563 if ((bit & mask) != 0)
6564 {
6565 regdeps[i].link_to_qp_branch = 0;
6566 }
6567 }
6568}
6569
6570/* Remove any mutexes which contain any of the PRs indicated in the mask.
6571
6572 Any changes to a PR clears the mutex relations which include that PR.
6573*/
6574static void
6575clear_qp_mutex (mask)
6576 valueT mask;
6577{
6578 int i;
6579
6580 i = 0;
6581 while (i < qp_mutexeslen)
6582 {
6583 if ((qp_mutexes[i].prmask & mask) != 0)
6584 {
6585 if (md.debug_dv)
6586 {
6587 fprintf (stderr, " Clearing mutex relation");
6588 print_prmask (qp_mutexes[i].prmask);
6589 fprintf (stderr, "\n");
6590 }
6591 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
6592 }
6593 else
6594 ++i;
6595 }
6596}
6597
6598/* Clear implies relations which contain PRs in the given masks.
6599 P1_MASK indicates the source of the implies relation, while P2_MASK
6600 indicates the implied PR.
6601*/
6602static void
6603clear_qp_implies (p1_mask, p2_mask)
6604 valueT p1_mask;
6605 valueT p2_mask;
6606{
6607 int i;
6608
6609 i = 0;
6610 while (i < qp_implieslen)
6611 {
6612 if ((((valueT)1 << qp_implies[i].p1) & p1_mask) != 0
6613 || (((valueT)1 << qp_implies[i].p2) & p2_mask) != 0)
6614 {
6615 if (md.debug_dv)
6616 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
6617 qp_implies[i].p1, qp_implies[i].p2);
6618 qp_implies[i] = qp_implies[--qp_implieslen];
6619 }
6620 else
6621 ++i;
6622 }
6623}
6624
6625/* add the PRs specified to the list of implied relations */
6626static void
6627add_qp_imply (p1, p2)
6628 int p1, p2;
6629{
6630 valueT mask;
6631 valueT bit;
6632 int i;
6633
6634 /* p0 is not meaningful here */
6635 if (p1 == 0 || p2 == 0)
6636 abort ();
6637
6638 if (p1 == p2)
6639 return;
6640
6641 /* if it exists already, ignore it */
6642 for (i=0;i < qp_implieslen;i++)
6643 {
6644 if (qp_implies[i].p1 == p1
6645 && qp_implies[i].p2 == p2
6646 && qp_implies[i].path == md.path
6647 && !qp_implies[i].p2_branched)
6648 return;
6649 }
6650
6651 if (qp_implieslen == qp_impliestotlen)
6652 {
6653 qp_impliestotlen += 20;
6654 qp_implies = (struct qp_imply *)
6655 xrealloc ((void *)qp_implies,
6656 qp_impliestotlen * sizeof (struct qp_imply));
6657 }
6658 if (md.debug_dv)
6659 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
6660 qp_implies[qp_implieslen].p1 = p1;
6661 qp_implies[qp_implieslen].p2 = p2;
6662 qp_implies[qp_implieslen].path = md.path;
6663 qp_implies[qp_implieslen++].p2_branched = 0;
6664
6665 /* Add in the implied transitive relations; for everything that p2 implies,
6666 make p1 imply that, too; for everything that implies p1, make it imply p2
6667 as well. */
6668 for (i=0;i < qp_implieslen;i++)
6669 {
6670 if (qp_implies[i].p1 == p2)
6671 add_qp_imply (p1, qp_implies[i].p2);
6672 if (qp_implies[i].p2 == p1)
6673 add_qp_imply (qp_implies[i].p1, p2);
6674 }
6675 /* Add in mutex relations implied by this implies relation; for each mutex
6676 relation containing p2, duplicate it and replace p2 with p1. */
6677 bit = (valueT)1 << p1;
6678 mask = (valueT)1 << p2;
6679 for (i=0;i < qp_mutexeslen;i++)
6680 {
6681 if (qp_mutexes[i].prmask & mask)
6682 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
6683 }
6684}
6685
6686
6687/* Add the PRs specified in the mask to the mutex list; this means that only
6688 one of the PRs can be true at any time. PR0 should never be included in
6689 the mask. */
6690static void
6691add_qp_mutex (mask)
6692 valueT mask;
6693{
6694 if (mask & 0x1)
6695 abort ();
6696
6697 if (qp_mutexeslen == qp_mutexestotlen)
6698 {
6699 qp_mutexestotlen += 20;
6700 qp_mutexes = (struct qpmutex *)
6701 xrealloc ((void *)qp_mutexes,
6702 qp_mutexestotlen * sizeof (struct qpmutex));
6703 }
6704 if (md.debug_dv)
6705 {
6706 fprintf (stderr, " Registering mutex on");
6707 print_prmask (mask);
6708 fprintf (stderr, "\n");
6709 }
6710 qp_mutexes[qp_mutexeslen].path = md.path;
6711 qp_mutexes[qp_mutexeslen++].prmask = mask;
6712}
6713
6714static void
6715clear_register_values ()
6716{
6717 int i;
6718 if (md.debug_dv)
6719 fprintf (stderr, " Clearing register values\n");
6720 for (i=1;i < NELEMS(gr_values);i++)
6721 gr_values[i].known = 0;
6722}
6723
6724/* Keep track of register values/changes which affect DV tracking.
6725
6726 optimization note: should add a flag to classes of insns where otherwise we
6727 have to examine a group of strings to identify them.
6728
6729 */
6730static void
6731note_register_values (idesc)
6732 struct ia64_opcode *idesc;
6733{
6734 valueT qp_changemask = 0;
6735 int i;
6736
6737 /* invalidate values for registers being written to */
6738 for (i=0;i < idesc->num_outputs;i++)
6739 {
6740 if (idesc->operands[i] == IA64_OPND_R1
6741 || idesc->operands[i] == IA64_OPND_R2
6742 || idesc->operands[i] == IA64_OPND_R3)
6743 {
6744 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
6745 if (regno > 0 && regno < NELEMS(gr_values))
6746 gr_values[regno].known = 0;
6747 }
6748 else if (idesc->operands[i] == IA64_OPND_P1
6749 || idesc->operands[i] == IA64_OPND_P2)
6750 {
6751 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
6752 qp_changemask |= (valueT)1 << regno;
6753 }
6754 else if (idesc->operands[i] == IA64_OPND_PR)
6755 {
6756 if (idesc->operands[2] & (valueT)0x10000)
6757 qp_changemask = ~(valueT)0x1FFFF | idesc->operands[2];
6758 else
6759 qp_changemask = idesc->operands[2];
6760 break;
6761 }
6762 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
6763 {
6764 if (idesc->operands[1] & ((valueT)1 << 43))
6765 qp_changemask = ~(valueT)0xFFFFFFFFFFF | idesc->operands[1];
6766 else
6767 qp_changemask = idesc->operands[1];
6768 qp_changemask &= ~(valueT)0xFFFF;
6769 break;
6770 }
6771 }
6772
6773 /* Always clear qp branch flags on any PR change */
6774 /* FIXME there may be exceptions for certain compares */
6775 clear_qp_branch_flag (qp_changemask);
6776
6777 /* invalidate rotating registers on insns which affect RRBs in CFM */
6778 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
6779 {
6780 qp_changemask |= ~(valueT)0xFFFF;
6781 if (strcmp (idesc->name, "clrrrb.pr") != 0)
6782 {
6783 for (i=32;i < 32+md.rot.num_regs;i++)
6784 gr_values[i].known = 0;
6785 }
6786 clear_qp_mutex (qp_changemask);
6787 clear_qp_implies (qp_changemask, qp_changemask);
6788 }
6789 /* after a call, all register values are undefined, except those marked
6790 as "safe" */
6791 else if (strncmp (idesc->name, "br.call", 6) == 0
6792 || strncmp (idesc->name, "brl.call", 7) == 0)
6793 {
6794 // FIXME keep GR values which are marked as "safe_across_calls"
6795 clear_register_values ();
6796 clear_qp_mutex (~qp_safe_across_calls);
6797 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
6798 clear_qp_branch_flag (~qp_safe_across_calls);
6799 }
6800 /* Look for mutex and implies relations */
6801 else if ((idesc->operands[0] == IA64_OPND_P1
6802 || idesc->operands[0] == IA64_OPND_P2)
6803 && (idesc->operands[1] == IA64_OPND_P1
6804 || idesc->operands[1] == IA64_OPND_P2))
6805 {
6806 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
6807 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
6808 valueT p1mask = (valueT)1 << p1;
6809 valueT p2mask = (valueT)1 << p2;
6810
6811 /* if one of the PRs is PR0, we can't really do anything */
6812 if (p1 == 0 || p2 == 0)
6813 {
6814 if (md.debug_dv)
6815 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
6816 }
6817 /* In general, clear mutexes and implies which include P1 or P2,
6818 with the following exceptions */
6819 else if (strstr (idesc->name, ".or.andcm") != NULL)
6820 {
6821 add_qp_mutex (p1mask | p2mask);
6822 clear_qp_implies (p2mask, p1mask);
6823 }
6824 else if (strstr (idesc->name, ".and.orcm") != NULL)
6825 {
6826 add_qp_mutex (p1mask | p2mask);
6827 clear_qp_implies (p1mask, p2mask);
6828 }
6829 else if (strstr (idesc->name, ".and") != NULL)
6830 {
6831 clear_qp_implies (0, p1mask | p2mask);
6832 }
6833 else if (strstr (idesc->name, ".or") != NULL)
6834 {
6835 clear_qp_mutex (p1mask | p2mask);
6836 clear_qp_implies (p1mask | p2mask, 0);
6837 }
6838 else
6839 {
6840 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
6841 if (strstr (idesc->name, ".unc") != NULL)
6842 {
6843 add_qp_mutex (p1mask | p2mask);
6844 if (CURR_SLOT.qp_regno != 0)
6845 {
6846 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
6847 CURR_SLOT.qp_regno);
6848 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
6849 CURR_SLOT.qp_regno);
6850 }
6851 }
6852 else if (CURR_SLOT.qp_regno == 0)
6853 {
6854 add_qp_mutex (p1mask | p2mask);
6855 }
6856 else
6857 {
6858 clear_qp_mutex (p1mask | p2mask);
6859 }
6860 }
6861 }
6862 /* Look for mov imm insns into GRs */
6863 else if (idesc->operands[0] == IA64_OPND_R1
6864 && (idesc->operands[1] == IA64_OPND_IMM22
6865 || idesc->operands[1] == IA64_OPND_IMMU64)
6866 && (strcmp(idesc->name, "mov") == 0
6867 || strcmp(idesc->name, "movl") == 0))
6868 {
6869 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
6870 if (regno > 0 && regno < NELEMS(gr_values))
6871 {
6872 gr_values[regno].known = 1;
6873 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
6874 gr_values[regno].path = md.path;
6875 if (md.debug_dv)
6876 fprintf (stderr, " Know gr%d = 0x%llx\n",
6877 regno, gr_values[regno].value);
6878 }
6879 }
6880 else
6881 {
6882 clear_qp_mutex (qp_changemask);
6883 clear_qp_implies (qp_changemask, qp_changemask);
6884 }
6885}
6886
6887/* Return whether the given predicate registers are currently mutex */
6888static int
6889qp_mutex (p1, p2, path)
6890 int p1;
6891 int p2;
6892 int path;
6893{
6894 int i;
6895 valueT mask;
6896
6897 if (p1 != p2)
6898 {
6899 mask = ((valueT)1<<p1) | (valueT)1<<p2;
6900 for (i=0;i < qp_mutexeslen;i++)
6901 {
6902 if (qp_mutexes[i].path >= path
6903 && (qp_mutexes[i].prmask & mask) == mask)
6904 return 1;
6905 }
6906 }
6907 return 0;
6908}
6909
6910/* Return whether the given resource is in the given insn's list of chks
6911 Return 1 if the conflict is absolutely determined, 2 if it's a potential
6912 conflict.
6913 */
6914static int
6915resources_match (rs, idesc, note, qp_regno, path)
6916 struct rsrc *rs;
6917 struct ia64_opcode *idesc;
6918 int note;
6919 int qp_regno;
6920 int path;
6921{
6922 struct rsrc specs[MAX_SPECS];
6923 int count;
6924
6925 /* If the marked resource's qp_regno and the given qp_regno are mutex,
6926 we don't need to check. One exception is note 11, which indicates that
6927 target predicates are written regardless of PR[qp]. */
6928 if (qp_mutex (rs->qp_regno, qp_regno, path)
6929 && note != 11)
6930 return 0;
6931
6932 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
6933 while (count-- > 0)
6934 {
6935 /* UNAT checking is a bit more specific than other resources */
6936 if (rs->dependency->specifier == IA64_RS_AR_UNAT
6937 && specs[count].mem_offset.hint
6938 && rs->mem_offset.hint)
6939 {
6940 if (rs->mem_offset.base == specs[count].mem_offset.base)
6941 {
6942 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
6943 ((specs[count].mem_offset.offset >> 3) & 0x3F))
6944 return 1;
6945 else
6946 continue;
6947 }
6948 }
6949
6950 /* If either resource is not specific, conservatively assume a conflict
6951 */
6952 if (!specs[count].specific || !rs->specific)
6953 return 2;
6954 else if (specs[count].index == rs->index)
6955 return 1;
6956 }
6957#if 0
6958 if (md.debug_dv)
6959 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
6960#endif
6961
6962 return 0;
6963}
6964
6965/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
6966 insert a stop to create the break. Update all resource dependencies
6967 appropriately. If QP_REGNO is non-zero, only apply the break to resources
6968 which use the same QP_REGNO and have the link_to_qp_branch flag set.
6969 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
6970 instruction.
6971*/
6972
6973static void
6974insn_group_break (insert_stop, qp_regno, save_current)
6975 int insert_stop;
6976 int qp_regno;
6977 int save_current;
6978{
6979 int i;
6980
6981 if (insert_stop && md.num_slots_in_use > 0)
6982 PREV_SLOT.end_of_insn_group = 1;
6983
6984 if (md.debug_dv)
6985 {
6986 fprintf (stderr, " Insn group break%s",
6987 (insert_stop ? " (w/stop)" : ""));
6988 if (qp_regno != 0)
6989 fprintf (stderr, " effective for QP=%d", qp_regno);
6990 fprintf (stderr, "\n");
6991 }
6992
6993 i = 0;
6994 while (i < regdepslen)
6995 {
6996 const struct ia64_dependency *dep = regdeps[i].dependency;
6997
6998 if (qp_regno != 0
6999 && regdeps[i].qp_regno != qp_regno)
7000 {
7001 ++i;
7002 continue;
7003 }
7004
7005 if (save_current
7006 && CURR_SLOT.src_file == regdeps[i].file
7007 && CURR_SLOT.src_line == regdeps[i].line)
7008 {
7009 ++i;
7010 continue;
7011 }
7012
7013 /* clear dependencies which are automatically cleared by a stop, or
7014 those that have reached the appropriate state of insn serialization */
7015 if (dep->semantics == IA64_DVS_IMPLIED
7016 || dep->semantics == IA64_DVS_IMPLIEDF
7017 || regdeps[i].insn_srlz == STATE_SRLZ)
7018 {
7019 print_dependency ("Removing", i);
7020 regdeps[i] = regdeps[--regdepslen];
7021 }
7022 else
7023 {
7024 if (dep->semantics == IA64_DVS_DATA
7025 || dep->semantics == IA64_DVS_INSTR
7026 || dep->semantics == IA64_DVS_SPECIFIC)
7027 {
7028 if (regdeps[i].insn_srlz == STATE_NONE)
7029 regdeps[i].insn_srlz = STATE_STOP;
7030 if (regdeps[i].data_srlz == STATE_NONE)
7031 regdeps[i].data_srlz = STATE_STOP;
7032 }
7033 ++i;
7034 }
7035 }
7036}
7037
7038/* Add the given resource usage spec to the list of active dependencies */
7039static void
7040mark_resource (idesc, dep, spec, depind, path)
7041 struct ia64_opcode *idesc;
7042 const struct ia64_dependency *dep;
7043 struct rsrc *spec;
7044 int depind;
7045 int path;
7046{
7047 if (regdepslen == regdepstotlen)
7048 {
7049 regdepstotlen += 20;
7050 regdeps = (struct rsrc *)
7051 xrealloc ((void *)regdeps,
7052 regdepstotlen * sizeof(struct rsrc));
7053 }
7054
7055 regdeps[regdepslen] = *spec;
7056 regdeps[regdepslen].depind = depind;
7057 regdeps[regdepslen].path = path;
7058 regdeps[regdepslen].file = CURR_SLOT.src_file;
7059 regdeps[regdepslen].line = CURR_SLOT.src_line;
7060
7061 print_dependency ("Adding", regdepslen);
7062
7063 ++regdepslen;
7064}
7065
7066static void
7067print_dependency (action, depind)
7068 const char *action;
7069 int depind;
7070{
7071 if (md.debug_dv)
7072 {
7073 fprintf (stderr, " %s %s '%s'",
7074 action, dv_mode[(regdeps[depind].dependency)->mode],
7075 (regdeps[depind].dependency)->name);
7076 if (regdeps[depind].specific && regdeps[depind].index != 0)
7077 fprintf (stderr, " (%d)", regdeps[depind].index);
7078 if (regdeps[depind].mem_offset.hint)
7079 fprintf (stderr, " 0x%llx+0x%llx",
7080 regdeps[depind].mem_offset.base,
7081 regdeps[depind].mem_offset.offset);
7082 fprintf (stderr, "\n");
7083 }
7084}
7085
7086static void
7087instruction_serialization ()
7088{
7089 int i;
7090 if (md.debug_dv)
7091 fprintf (stderr, " Instruction serialization\n");
7092 for (i=0;i < regdepslen;i++)
7093 if (regdeps[i].insn_srlz == STATE_STOP)
7094 regdeps[i].insn_srlz = STATE_SRLZ;
7095}
7096
7097static void
7098data_serialization ()
7099{
7100 int i = 0;
7101 if (md.debug_dv)
7102 fprintf (stderr, " Data serialization\n");
7103 while (i < regdepslen)
7104 {
7105 if (regdeps[i].data_srlz == STATE_STOP
7106 /* Note: as of 991210, all "other" dependencies are cleared by a
7107 data serialization. This might change with new tables */
7108 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
7109 {
7110 print_dependency ("Removing", i);
7111 regdeps[i] = regdeps[--regdepslen];
7112 }
7113 else
7114 ++i;
7115 }
7116}
7117
7118/* Insert stops and serializations as needed to avoid DVs */
7119static void
7120remove_marked_resource (rs)
7121 struct rsrc *rs;
7122{
7123 switch (rs->dependency->semantics)
7124 {
7125 case IA64_DVS_SPECIFIC:
7126 if (md.debug_dv)
7127 fprintf (stderr, "Implementation-specific, assume worst case...\n");
7128 /* ...fall through... */
7129 case IA64_DVS_INSTR:
7130 if (md.debug_dv)
7131 fprintf (stderr, "Inserting instr serialization\n");
7132 if (rs->insn_srlz < STATE_STOP)
7133 insn_group_break (1, 0, 0);
7134 if (rs->insn_srlz < STATE_SRLZ)
7135 {
7136 int oldqp = CURR_SLOT.qp_regno;
7137 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
7138 /* Manually jam a srlz.i insn into the stream */
7139 CURR_SLOT.qp_regno = 0;
7140 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
7141 instruction_serialization ();
7142 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
7143 if (++md.num_slots_in_use >= NUM_SLOTS)
7144 emit_one_bundle ();
7145 CURR_SLOT.qp_regno = oldqp;
7146 CURR_SLOT.idesc = oldidesc;
7147 }
7148 insn_group_break (1, 0, 0);
7149 break;
7150 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
7151 "other" types of DV are eliminated
7152 by a data serialization */
7153 case IA64_DVS_DATA:
7154 if (md.debug_dv)
7155 fprintf (stderr, "Inserting data serialization\n");
7156 if (rs->data_srlz < STATE_STOP)
7157 insn_group_break (1, 0, 0);
7158 {
7159 int oldqp = CURR_SLOT.qp_regno;
7160 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
7161 /* Manually jam a srlz.d insn into the stream */
7162 CURR_SLOT.qp_regno = 0;
7163 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
7164 data_serialization ();
7165 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
7166 if (++md.num_slots_in_use >= NUM_SLOTS)
7167 emit_one_bundle ();
7168 CURR_SLOT.qp_regno = oldqp;
7169 CURR_SLOT.idesc = oldidesc;
7170 }
7171 break;
7172 case IA64_DVS_IMPLIED:
7173 case IA64_DVS_IMPLIEDF:
7174 if (md.debug_dv)
7175 fprintf (stderr, "Inserting stop\n");
7176 insn_group_break (1, 0, 0);
7177 break;
7178 default:
7179 break;
7180 }
7181}
7182
7183/* Check the resources used by the given opcode against the current dependency
7184 list.
7185
7186 The check is run once for each execution path encountered. In this case,
7187 a unique execution path is the sequence of instructions following a code
7188 entry point, e.g. the following has three execution paths, one starting
7189 at L0, one at L1, and one at L2.
7190
7191 L0: nop
7192 L1: add
7193 L2: add
7194 br.ret
7195*/
7196static void
7197check_dependencies (idesc)
7198 struct ia64_opcode *idesc;
7199{
7200 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
7201 int path;
7202 int i;
7203
7204 /* Note that the number of marked resources may change within the
7205 loop if in auto mode. */
7206 i = 0;
7207 while (i < regdepslen)
7208 {
7209 struct rsrc *rs = &regdeps[i];
7210 const struct ia64_dependency *dep = rs->dependency;
7211 int chkind;
7212 int note;
7213 int start_over = 0;
7214
7215 if (dep->semantics == IA64_DVS_NONE
7216 || (chkind = depends_on (rs->depind, idesc)) == -1)
7217 {
7218 ++i; continue;
7219 }
7220
7221 note = NOTE(opdeps->chks[chkind]);
7222
7223 /* Check this resource against each execution path seen thus far */
7224 for (path=0;path <= md.path;path++)
7225 {
7226 int matchtype;
7227
7228 /* If the dependency wasn't on the path being checked, ignore it */
7229 if (rs->path < path)
7230 continue;
7231
7232 /* If the QP for this insn implies a QP which has branched, don't
7233 bother checking. Ed. NOTE: I don't think this check is terribly
7234 useful; what's the point of generating code which will only be
7235 reached if its QP is zero?
7236 This code was specifically inserted to handle the following code,
7237 based on notes from Intel's DV checking code, where p1 implies p2.
7238
7239 mov r4 = 2
7240 (p2) br.cond L
7241 (p1) mov r4 = 7
7242
7243 */
7244 if (CURR_SLOT.qp_regno != 0)
7245 {
7246 int skip = 0;
7247 int implies;
7248 for (implies=0;implies < qp_implieslen;implies++)
7249 {
7250 if (qp_implies[implies].path >= path
7251 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
7252 && qp_implies[implies].p2_branched)
7253 {
7254 skip = 1;
7255 break;
7256 }
7257 }
7258 if (skip)
7259 continue;
7260 }
7261
7262 if ((matchtype = resources_match (rs, idesc, note,
7263 CURR_SLOT.qp_regno, path)) != 0)
7264 {
7265 char msg[1024];
7266 char pathmsg[256] = "";
7267 char indexmsg[256] = "";
7268 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
7269
7270 if (path != 0)
7271 sprintf (pathmsg, " when entry is at label '%s'",
7272 md.entry_labels[path-1]);
7273 if (rs->specific && rs->index != 0)
7274 sprintf (indexmsg, ", specific resource number is %d",
7275 rs->index);
7276 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
7277 idesc->name,
7278 (certain ? "violates" : "may violate"),
7279 dv_mode[dep->mode], dep->name,
7280 dv_sem[dep->semantics],
7281 pathmsg, indexmsg);
7282
7283 if (md.explicit_mode)
7284 {
7285 as_warn ("%s", msg);
7286 if (path < md.path)
7287 as_warn (_("Only the first path encountering the conflict "
7288 "is reported"));
7289 as_warn_where (rs->file, rs->line,
7290 _("This is the location of the "
7291 "conflicting usage"));
7292 /* Don't bother checking other paths, to avoid duplicating
7293 the same warning */
7294 break;
7295 }
7296 else
7297 {
7298 if (md.debug_dv)
7299 fprintf(stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
7300
7301 remove_marked_resource (rs);
7302
7303 /* since the set of dependencies has changed, start over */
7304 /* FIXME -- since we're removing dvs as we go, we
7305 probably don't really need to start over... */
7306 start_over = 1;
7307 break;
7308 }
7309 }
7310 }
7311 if (start_over)
7312 i = 0;
7313 else
7314 ++i;
7315 }
7316}
7317
7318/* register new dependencies based on the given opcode */
7319static void
7320mark_resources (idesc)
7321 struct ia64_opcode *idesc;
7322{
7323 int i;
7324 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
7325 int add_only_qp_reads = 0;
7326
7327 /* A conditional branch only uses its resources if it is taken; if it is
7328 taken, we stop following that path. The other branch types effectively
7329 *always* write their resources. If it's not taken, register only QP
7330 reads. */
7331 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
7332 {
7333 add_only_qp_reads = 1;
7334 }
7335
7336 if (md.debug_dv)
7337 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
7338
7339 for (i=0;i < opdeps->nregs;i++)
7340 {
7341 const struct ia64_dependency *dep;
7342 struct rsrc specs[MAX_SPECS];
7343 int note;
7344 int path;
7345 int count;
7346
7347 dep = ia64_find_dependency (opdeps->regs[i]);
7348 note = NOTE(opdeps->regs[i]);
7349
7350 if (add_only_qp_reads
7351 && !(dep->mode == IA64_DV_WAR
7352 && (dep->specifier == IA64_RS_PR
7353 || dep->specifier == IA64_RS_PR63)))
7354 continue;
7355
7356 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
7357
7358#if 0
7359 if (md.debug_dv && !count)
7360 fprintf (stderr, " No %s %s usage found (path %d)\n",
7361 dv_mode[dep->mode], dep->name, md.path);
7362#endif
7363
7364 while (count-- > 0)
7365 {
7366 mark_resource (idesc, dep, &specs[count],
7367 DEP(opdeps->regs[i]), md.path);
7368 }
7369
7370 /* The execution path may affect register values, which may in turn
7371 affect which indirect-access resources are accessed. */
7372 switch (dep->specifier)
7373 {
7374 default:
7375 break;
7376 case IA64_RS_CPUID:
7377 case IA64_RS_DBR:
7378 case IA64_RS_IBR:
7379 case IA64_RS_MSR:
7380 case IA64_RS_PKR:
7381 case IA64_RS_PMC:
7382 case IA64_RS_PMD:
7383 case IA64_RS_RR:
7384 for (path=0;path < md.path;path++)
7385 {
7386 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
7387 while (count-- > 0)
7388 mark_resource (idesc, dep, &specs[count],
7389 DEP(opdeps->regs[i]), path);
7390 }
7391 break;
7392 }
7393 }
7394}
7395
7396/* remove dependencies when they no longer apply */
7397static void
7398update_dependencies (idesc)
7399 struct ia64_opcode *idesc;
7400{
7401 int i;
7402
7403 if (strcmp (idesc->name, "srlz.i") == 0)
7404 {
7405 instruction_serialization ();
7406 }
7407 else if (strcmp (idesc->name, "srlz.d") == 0)
7408 {
7409 data_serialization ();
7410 }
7411 else if (is_interruption_or_rfi (idesc)
7412 || is_taken_branch (idesc))
7413 {
7414 /* although technically the taken branch doesn't clear dependencies
7415 which require a srlz.[id], we don't follow the branch; the next
7416 instruction is assumed to start with a clean slate */
7417 regdepslen = 0;
7418 clear_register_values ();
7419 clear_qp_mutex (~(valueT)0);
7420 clear_qp_implies (~(valueT)0, ~(valueT)0);
7421 md.path = 0;
7422 }
7423 else if (is_conditional_branch (idesc)
7424 && CURR_SLOT.qp_regno != 0)
7425 {
7426 int is_call = strstr (idesc->name, ".call") != NULL;
7427
7428 for (i=0;i < qp_implieslen;i++)
7429 {
7430 /* if the conditional branch's predicate is implied by the predicate
7431 in an existing dependency, remove that dependency */
7432 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
7433 {
7434 int depind = 0;
7435 /* note that this implied predicate takes a branch so that if
7436 a later insn generates a DV but its predicate implies this
7437 one, we can avoid the false DV warning */
7438 qp_implies[i].p2_branched = 1;
7439 while (depind < regdepslen)
7440 {
7441 if (regdeps[depind].qp_regno == qp_implies[i].p1)
7442 {
7443 print_dependency ("Removing", depind);
7444 regdeps[depind] = regdeps[--regdepslen];
7445 }
7446 else
7447 ++depind;
7448 }
7449 }
7450 }
7451 /* Any marked resources which have this same predicate should be
7452 cleared, provided that the QP hasn't been modified between the
7453 marking instruction and the branch.
7454 */
7455 if (is_call)
7456 {
7457 insn_group_break (0, CURR_SLOT.qp_regno, 1);
7458 }
7459 else
7460 {
7461 i = 0;
7462 while (i < regdepslen)
7463 {
7464 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
7465 && regdeps[i].link_to_qp_branch
7466 && (regdeps[i].file != CURR_SLOT.src_file
7467 || regdeps[i].line != CURR_SLOT.src_line))
7468 {
7469 /* Treat like a taken branch */
7470 print_dependency ("Removing", i);
7471 regdeps[i] = regdeps[--regdepslen];
7472 }
7473 else
7474 ++i;
7475 }
7476 }
7477 }
7478}
7479
7480/* Examine the current instruction for dependency violations. */
7481static int
7482check_dv (idesc)
7483 struct ia64_opcode *idesc;
7484{
7485 if (md.debug_dv)
7486 {
7487 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
7488 idesc->name, CURR_SLOT.src_line,
7489 idesc->dependencies->nchks,
7490 idesc->dependencies->nregs);
7491 }
7492
7493 /* Look through the list of currently marked resources; if the current
7494 instruction has the dependency in its chks list which uses that resource,
7495 check against the specific resources used.
7496 */
7497 check_dependencies (idesc);
7498
7499 /*
7500 Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
7501 then add them to the list of marked resources.
7502 */
7503 mark_resources (idesc);
7504
7505 /* There are several types of dependency semantics, and each has its own
7506 requirements for being cleared
7507
7508 Instruction serialization (insns separated by interruption, rfi, or
7509 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
7510
7511 Data serialization (instruction serialization, or writer + srlz.d +
7512 reader, where writer and srlz.d are in separate groups) clears
7513 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
7514 always be the case).
7515
7516 Instruction group break (groups separated by stop, taken branch,
7517 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
7518 */
7519 update_dependencies (idesc);
7520
7521 /* Sometimes, knowing a register value allows us to avoid giving a false DV
7522 warning. Keep track of as many as possible that are useful. */
7523 note_register_values (idesc);
7524
7525 /* We don't need or want this anymore. */
7526 md.mem_offset.hint = 0;
7527
7528 return 0;
7529}
7530
7531/* Translate one line of assembly. Pseudo ops and labels do not show
7532 here. */
7533void
7534md_assemble (str)
7535 char *str;
7536{
7537 char *saved_input_line_pointer, *mnemonic;
7538 const struct pseudo_opcode *pdesc;
7539 struct ia64_opcode *idesc;
7540 unsigned char qp_regno;
7541 unsigned int flags;
7542 int ch;
7543
7544 saved_input_line_pointer = input_line_pointer;
7545 input_line_pointer = str;
7546
7547 /* extract the opcode (mnemonic): */
7548
7549 mnemonic = input_line_pointer;
7550 ch = get_symbol_end ();
7551 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
7552 if (pdesc)
7553 {
7554 *input_line_pointer = ch;
7555 (*pdesc->handler) (pdesc->arg);
7556 goto done;
7557 }
7558
7559 /* find the instruction descriptor matching the arguments: */
7560
7561 idesc = ia64_find_opcode (mnemonic);
7562 *input_line_pointer = ch;
7563 if (!idesc)
7564 {
7565 as_bad ("Unknown opcode `%s'", mnemonic);
7566 goto done;
7567 }
7568
7569 idesc = parse_operands (idesc);
7570 if (!idesc)
7571 goto done;
7572
7573 /* Handle the dynamic ops we can handle now: */
7574 if (idesc->type == IA64_TYPE_DYN)
7575 {
7576 if (strcmp (idesc->name, "add") == 0)
7577 {
7578 if (CURR_SLOT.opnd[2].X_op == O_register
7579 && CURR_SLOT.opnd[2].X_add_number < 4)
7580 mnemonic = "addl";
7581 else
7582 mnemonic = "adds";
7583 idesc = ia64_find_opcode (mnemonic);
7584#if 0
7585 know (!idesc->next);
7586#endif
7587 }
7588 else if (strcmp (idesc->name, "mov") == 0)
7589 {
7590 enum ia64_opnd opnd1, opnd2;
7591 int rop;
7592
7593 opnd1 = idesc->operands[0];
7594 opnd2 = idesc->operands[1];
7595 if (opnd1 == IA64_OPND_AR3)
7596 rop = 0;
7597 else if (opnd2 == IA64_OPND_AR3)
7598 rop = 1;
7599 else
7600 abort ();
7601 if (CURR_SLOT.opnd[rop].X_op == O_register
7602 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
7603 mnemonic = "mov.i";
7604 else
7605 mnemonic = "mov.m";
7606 idesc = ia64_find_opcode (mnemonic);
7607 while (idesc != NULL
7608 && (idesc->operands[0] != opnd1
7609 || idesc->operands[1] != opnd2))
7610 idesc = get_next_opcode (idesc);
7611 }
7612 }
7613
7614 qp_regno = 0;
7615 if (md.qp.X_op == O_register)
7616 qp_regno = md.qp.X_add_number - REG_P;
7617
7618 flags = idesc->flags;
7619
7620 if ((flags & IA64_OPCODE_FIRST) != 0)
7621 insn_group_break (1, 0, 0);
7622
7623 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
7624 {
7625 as_bad ("`%s' cannot be predicated", idesc->name);
7626 goto done;
7627 }
7628
7629 /* build the instruction: */
7630 CURR_SLOT.qp_regno = qp_regno;
7631 CURR_SLOT.idesc = idesc;
7632 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
7633 if (debug_type == DEBUG_DWARF2)
7634 dwarf2_where (&CURR_SLOT.debug_line);
7635
7636 /* Add unwind entry, if there is one. */
7637 if (current_unwind_entry)
7638 {
7639 CURR_SLOT.unwind_record = current_unwind_entry;
7640 current_unwind_entry = NULL;
7641 }
7642
7643 /* check for dependency violations */
7644 if (md.detect_dv)
7645 check_dv(idesc);
7646
7647 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
7648 if (++md.num_slots_in_use >= NUM_SLOTS)
7649 emit_one_bundle ();
7650
7651 if ((flags & IA64_OPCODE_LAST) != 0)
7652 insn_group_break (1, 0, 0);
7653
7654 md.last_text_seg = now_seg;
7655
7656 done:
7657 input_line_pointer = saved_input_line_pointer;
7658}
7659
7660/* Called when symbol NAME cannot be found in the symbol table.
7661 Should be used for dynamic valued symbols only. */
7662symbolS*
7663md_undefined_symbol (name)
7664 char *name;
7665{
7666 return 0;
7667}
7668
7669/* Called for any expression that can not be recognized. When the
7670 function is called, `input_line_pointer' will point to the start of
7671 the expression. */
7672void
7673md_operand (e)
7674 expressionS *e;
7675{
7676 enum pseudo_type pseudo_type;
7677 size_t len;
7678 int ch, i;
7679
7680 switch (*input_line_pointer)
7681 {
7682 case '@':
7683 /* find what relocation pseudo-function we're dealing with: */
7684 pseudo_type = 0;
7685 ch = *++input_line_pointer;
7686 for (i = 0; i < NELEMS (pseudo_func); ++i)
7687 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
7688 {
7689 len = strlen (pseudo_func[i].name);
7690 if (strncmp (pseudo_func[i].name + 1,
7691 input_line_pointer + 1, len - 1) == 0
7692 && !is_part_of_name (input_line_pointer[len]))
7693 {
7694 input_line_pointer += len;
7695 pseudo_type = pseudo_func[i].type;
7696 break;
7697 }
7698 }
7699 switch (pseudo_type)
7700 {
7701 case PSEUDO_FUNC_RELOC:
7702 SKIP_WHITESPACE ();
7703 if (*input_line_pointer != '(')
7704 {
7705 as_bad ("Expected '('");
7706 goto err;
7707 }
7708 ++input_line_pointer; /* skip '(' */
7709 expression (e);
7710 if (*input_line_pointer++ != ')')
7711 {
7712 as_bad ("Missing ')'");
7713 goto err;
7714 }
7715 if (e->X_op != O_symbol)
7716 {
7717 if (e->X_op != O_pseudo_fixup)
7718 {
7719 as_bad ("Not a symbolic expression");
7720 goto err;
7721 }
7722 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
7723 && i == FUNC_LT_RELATIVE)
7724 i = FUNC_LT_FPTR_RELATIVE;
7725 else
7726 {
7727 as_bad ("Illegal combination of relocation functions");
7728 goto err;
7729 }
7730 }
7731 /* make sure gas doesn't get rid of local symbols that are used
7732 in relocs: */
7733 e->X_op = O_pseudo_fixup;
7734 e->X_op_symbol = pseudo_func[i].u.sym;
7735 break;
7736
7737 case PSEUDO_FUNC_CONST:
7738 e->X_op = O_constant;
7739 e->X_add_number = pseudo_func[i].u.ival;
7740 break;
7741
7742 default:
7743 as_bad ("Unknown pseudo function `%s'", input_line_pointer - 1);
7744 goto err;
7745 }
7746 break;
7747
7748 case '[':
7749 ++input_line_pointer;
7750 expression (e);
7751 if (*input_line_pointer != ']')
7752 {
7753 as_bad ("Closing bracket misssing");
7754 goto err;
7755 }
7756 else
7757 {
7758 if (e->X_op != O_register)
7759 as_bad ("Register expected as index");
7760
7761 ++input_line_pointer;
7762 e->X_op = O_index;
7763 }
7764 break;
7765
7766 default:
7767 break;
7768 }
7769 return;
7770
7771 err:
7772 ignore_rest_of_line ();
7773}
7774
7775/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
7776 a section symbol plus some offset. For relocs involving @fptr(),
7777 directives we don't want such adjustments since we need to have the
7778 original symbol's name in the reloc. */
7779int
7780ia64_fix_adjustable (fix)
7781 fixS *fix;
7782{
7783 /* Prevent all adjustments to global symbols */
7784 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
7785 return 0;
7786
7787 switch (fix->fx_r_type)
7788 {
7789 case BFD_RELOC_IA64_FPTR64I:
7790 case BFD_RELOC_IA64_FPTR32MSB:
7791 case BFD_RELOC_IA64_FPTR32LSB:
7792 case BFD_RELOC_IA64_FPTR64MSB:
7793 case BFD_RELOC_IA64_FPTR64LSB:
7794 case BFD_RELOC_IA64_LTOFF_FPTR22:
7795 case BFD_RELOC_IA64_LTOFF_FPTR64I:
7796 return 0;
7797 default:
7798 break;
7799 }
7800
7801 return 1;
7802}
7803
7804int
7805ia64_force_relocation (fix)
7806 fixS *fix;
7807{
7808 switch (fix->fx_r_type)
7809 {
7810 case BFD_RELOC_IA64_FPTR64I:
7811 case BFD_RELOC_IA64_FPTR32MSB:
7812 case BFD_RELOC_IA64_FPTR32LSB:
7813 case BFD_RELOC_IA64_FPTR64MSB:
7814 case BFD_RELOC_IA64_FPTR64LSB:
7815
7816 case BFD_RELOC_IA64_LTOFF22:
7817 case BFD_RELOC_IA64_LTOFF64I:
7818 case BFD_RELOC_IA64_LTOFF_FPTR22:
7819 case BFD_RELOC_IA64_LTOFF_FPTR64I:
7820 case BFD_RELOC_IA64_PLTOFF22:
7821 case BFD_RELOC_IA64_PLTOFF64I:
7822 case BFD_RELOC_IA64_PLTOFF64MSB:
7823 case BFD_RELOC_IA64_PLTOFF64LSB:
7824 return 1;
7825
7826 default:
7827 return 0;
7828 }
7829 return 0;
7830}
7831
7832/* Decide from what point a pc-relative relocation is relative to,
7833 relative to the pc-relative fixup. Er, relatively speaking. */
7834long
7835ia64_pcrel_from_section (fix, sec)
7836 fixS *fix;
7837 segT sec;
7838{
7839 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
7840
7841 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
7842 off &= ~0xfUL;
7843
7844 return off;
7845}
7846
7847/* This is called whenever some data item (not an instruction) needs a
7848 fixup. We pick the right reloc code depending on the byteorder
7849 currently in effect. */
7850void
7851ia64_cons_fix_new (f, where, nbytes, exp)
7852 fragS *f;
7853 int where;
7854 int nbytes;
7855 expressionS *exp;
7856{
7857 bfd_reloc_code_real_type code;
7858 fixS *fix;
7859
7860 switch (nbytes)
7861 {
7862 /* There are no reloc for 8 and 16 bit quantities, but we allow
7863 them here since they will work fine as long as the expression
7864 is fully defined at the end of the pass over the source file. */
7865 case 1: code = BFD_RELOC_8; break;
7866 case 2: code = BFD_RELOC_16; break;
7867 case 4:
7868 if (target_big_endian)
7869 code = BFD_RELOC_IA64_DIR32MSB;
7870 else
7871 code = BFD_RELOC_IA64_DIR32LSB;
7872 break;
7873
7874 case 8:
7875 if (target_big_endian)
7876 code = BFD_RELOC_IA64_DIR64MSB;
7877 else
7878 code = BFD_RELOC_IA64_DIR64LSB;
7879 break;
7880
7881 default:
7882 as_bad ("Unsupported fixup size %d", nbytes);
7883 ignore_rest_of_line ();
7884 return;
7885 }
7886 if (exp->X_op == O_pseudo_fixup)
7887 {
7888 /* ??? */
7889 exp->X_op = O_symbol;
7890 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
7891 }
7892 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
7893 /* We need to store the byte order in effect in case we're going
7894 to fix an 8 or 16 bit relocation (for which there no real
7895 relocs available). See md_apply_fix(). */
7896 fix->tc_fix_data.bigendian = target_big_endian;
7897}
7898
7899/* Return the actual relocation we wish to associate with the pseudo
7900 reloc described by SYM and R_TYPE. SYM should be one of the
7901 symbols in the pseudo_func array, or NULL. */
7902
7903static bfd_reloc_code_real_type
7904ia64_gen_real_reloc_type (sym, r_type)
7905 struct symbol *sym;
7906 bfd_reloc_code_real_type r_type;
7907{
7908 bfd_reloc_code_real_type new = 0;
7909
7910 if (sym == NULL)
7911 {
7912 return r_type;
7913 }
7914
7915 switch (S_GET_VALUE (sym))
7916 {
7917 case FUNC_FPTR_RELATIVE:
7918 switch (r_type)
7919 {
7920 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
7921 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
7922 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
7923 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
7924 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
7925 default: break;
7926 }
7927 break;
7928
7929 case FUNC_GP_RELATIVE:
7930 switch (r_type)
7931 {
7932 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
7933 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
7934 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
7935 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
7936 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
7937 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
7938 default: break;
7939 }
7940 break;
7941
7942 case FUNC_LT_RELATIVE:
7943 switch (r_type)
7944 {
7945 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
7946 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
7947 default: break;
7948 }
7949 break;
7950
7951 case FUNC_PLT_RELATIVE:
7952 switch (r_type)
7953 {
7954 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
7955 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
7956 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
7957 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
7958 default: break;
7959 }
7960 break;
7961
7962 case FUNC_SEC_RELATIVE:
7963 switch (r_type)
7964 {
7965 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
7966 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
7967 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
7968 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
7969 default: break;
7970 }
7971 break;
7972
7973 case FUNC_SEG_RELATIVE:
7974 switch (r_type)
7975 {
7976 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
7977 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
7978 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
7979 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
7980 default: break;
7981 }
7982 break;
7983
7984 case FUNC_LTV_RELATIVE:
7985 switch (r_type)
7986 {
7987 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
7988 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
7989 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
7990 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
7991 default: break;
7992 }
7993 break;
7994
7995 case FUNC_LT_FPTR_RELATIVE:
7996 switch (r_type)
7997 {
7998 case BFD_RELOC_IA64_IMM22:
7999 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
8000 case BFD_RELOC_IA64_IMM64:
8001 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
8002 default:
8003 break;
8004 }
8005 break;
8006 default:
8007 abort ();
8008 }
8009 /* Hmmmm. Should this ever occur? */
8010 if (new)
8011 return new;
8012 else
8013 return r_type;
8014}
8015
8016/* Here is where generate the appropriate reloc for pseudo relocation
8017 functions. */
8018void
8019ia64_validate_fix (fix)
8020 fixS *fix;
8021{
8022 switch (fix->fx_r_type)
8023 {
8024 case BFD_RELOC_IA64_FPTR64I:
8025 case BFD_RELOC_IA64_FPTR32MSB:
8026 case BFD_RELOC_IA64_FPTR64LSB:
8027 case BFD_RELOC_IA64_LTOFF_FPTR22:
8028 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8029 if (fix->fx_offset != 0)
8030 as_bad_where (fix->fx_file, fix->fx_line,
8031 "No addend allowed in @fptr() relocation");
8032 break;
8033 default:
8034 break;
8035 }
8036
8037 return;
8038}
8039
8040static void
8041fix_insn (fix, odesc, value)
8042 fixS *fix;
8043 const struct ia64_operand *odesc;
8044 valueT value;
8045{
8046 bfd_vma insn[3], t0, t1, control_bits;
8047 const char *err;
8048 char *fixpos;
8049 long slot;
8050
8051 slot = fix->fx_where & 0x3;
8052 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
8053
8054 /* bundles are always in little-endian byte order */
8055 t0 = bfd_getl64 (fixpos);
8056 t1 = bfd_getl64 (fixpos + 8);
8057 control_bits = t0 & 0x1f;
8058 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
8059 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
8060 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
8061
8062 err = (*odesc->insert) (odesc, value, insn + slot);
8063 if (err)
8064 {
8065 as_bad_where (fix->fx_file, fix->fx_line, err);
8066 return;
8067 }
8068
8069 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
8070 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
8071 md_number_to_chars (fixpos + 0, t0, 8);
8072 md_number_to_chars (fixpos + 8, t1, 8);
8073
8074}
8075
8076/* Attempt to simplify or even eliminate a fixup. The return value is
8077 ignored; perhaps it was once meaningful, but now it is historical.
8078 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
8079
8080 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
8081 (if possible). */
8082int
8083md_apply_fix3 (fix, valuep, seg)
8084 fixS *fix;
8085 valueT *valuep;
8086 segT seg;
8087{
8088 char *fixpos;
8089 valueT value = *valuep;
8090 int adjust = 0;
8091
8092 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
8093
8094 if (fix->fx_pcrel)
8095 {
8096 switch (fix->fx_r_type)
8097 {
8098 case BFD_RELOC_IA64_DIR32MSB:
8099 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
8100 adjust = 1;
8101 break;
8102
8103 case BFD_RELOC_IA64_DIR32LSB:
8104 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
8105 adjust = 1;
8106 break;
8107
8108 case BFD_RELOC_IA64_DIR64MSB:
8109 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
8110 adjust = 1;
8111 break;
8112
8113 case BFD_RELOC_IA64_DIR64LSB:
8114 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
8115 adjust = 1;
8116 break;
8117
8118 default:
8119 break;
8120 }
8121 }
8122 if (fix->fx_addsy)
8123 {
8124 switch (fix->fx_r_type)
8125 {
8126 case 0:
8127 as_bad_where (fix->fx_file, fix->fx_line,
8128 "%s must have a constant value",
8129 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
8130 break;
8131
8132 default:
8133 break;
8134 }
8135
8136 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
8137 work. There should be a better way to handle this. */
8138 if (adjust)
8139 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
8140 }
8141 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
8142 {
8143 if (fix->tc_fix_data.bigendian)
8144 number_to_chars_bigendian (fixpos, value, fix->fx_size);
8145 else
8146 number_to_chars_littleendian (fixpos, value, fix->fx_size);
8147 fix->fx_done = 1;
8148 return 1;
8149 }
8150 else
8151 {
8152 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
8153 fix->fx_done = 1;
8154 return 1;
8155 }
8156 return 1;
8157}
8158
8159/* Generate the BFD reloc to be stuck in the object file from the
8160 fixup used internally in the assembler. */
8161arelent*
8162tc_gen_reloc (sec, fixp)
8163 asection *sec;
8164 fixS *fixp;
8165{
8166 arelent *reloc;
8167
8168 reloc = xmalloc (sizeof (*reloc));
8169 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8170 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8171 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
8172 reloc->addend = fixp->fx_offset;
8173 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
8174
8175 if (!reloc->howto)
8176 {
8177 as_bad_where (fixp->fx_file, fixp->fx_line,
8178 "Cannot represent %s relocation in object file",
8179 bfd_get_reloc_code_name (fixp->fx_r_type));
8180 }
8181 return reloc;
8182}
8183
8184/* Turn a string in input_line_pointer into a floating point constant
8185 of type type, and store the appropriate bytes in *lit. The number
8186 of LITTLENUMS emitted is stored in *size. An error message is
8187 returned, or NULL on OK. */
8188
8189#define MAX_LITTLENUMS 5
8190
8191char*
8192md_atof (type, lit, size)
8193 int type;
8194 char *lit;
8195 int *size;
8196{
8197 LITTLENUM_TYPE words[MAX_LITTLENUMS];
8198 LITTLENUM_TYPE *word;
8199 char *t;
8200 int prec;
8201
8202 switch (type)
8203 {
8204 /* IEEE floats */
8205 case 'f':
8206 case 'F':
8207 case 's':
8208 case 'S':
8209 prec = 2;
8210 break;
8211
8212 case 'd':
8213 case 'D':
8214 case 'r':
8215 case 'R':
8216 prec = 4;
8217 break;
8218
8219 case 'x':
8220 case 'X':
8221 case 'p':
8222 case 'P':
8223 prec = 5;
8224 break;
8225
8226 default:
8227 *size = 0;
8228 return "Bad call to MD_ATOF()";
8229 }
8230 t = atof_ieee (input_line_pointer, type, words);
8231 if (t)
8232 input_line_pointer = t;
8233 *size = prec * sizeof (LITTLENUM_TYPE);
8234
8235 for (word = words + prec - 1; prec--;)
8236 {
8237 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
8238 lit += sizeof (LITTLENUM_TYPE);
8239 }
8240 return 0;
8241}
8242
8243/* Round up a section's size to the appropriate boundary. */
8244valueT
8245md_section_align (seg, size)
8246 segT seg;
8247 valueT size;
8248{
8249 int align = bfd_get_section_alignment (stdoutput, seg);
8250 valueT mask = ((valueT)1 << align) - 1;
8251
8252 return (size + mask) & ~mask;
8253}
8254
8255/* Handle ia64 specific semantics of the align directive. */
8256
8257int
8258ia64_md_do_align (n, fill, len, max)
8259 int n;
8260 const char *fill;
8261 int len;
8262 int max;
8263{
8264 /* Fill any pending bundle with nops. */
8265 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
8266 ia64_flush_insns ();
8267
8268 /* When we align code in a text section, emit a bundle of 3 nops instead of
8269 zero bytes. We can only do this if a multiple of 16 bytes was requested.
8270 N is log base 2 of the requested alignment. */
8271 if (fill == NULL
8272 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
8273 && n > 4)
8274 {
8275 /* Use mfi bundle of nops with no stop bits. */
8276 static const unsigned char be_nop[]
8277 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
8278 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
8279 static const unsigned char le_nop[]
8280 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
8281 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
8282
8283 /* Make sure we are on a 16-byte boundary, in case someone has been
8284 putting data into a text section. */
8285 frag_align (4, 0, 0);
8286
8287 if (target_big_endian)
8288 frag_align_pattern (n, be_nop, 16, max);
8289 else
8290 frag_align_pattern (n, le_nop, 16, max);
8291 return 1;
8292 }
8293
8294 return 0;
8295}
GDB Binutils - Deliverables
This page took 0.384453 seconds and 4 git commands to generate.