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800eeca4 | 1 | /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. |
e0c9811a | 2 | Copyright (C) 1998, 1999, 2000 Free Software Foundation. |
800eeca4 JW |
3 | Contributed by David Mosberger-Tang <davidm@hpl.hp.com> |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | /* | |
23 | TODO: | |
24 | ||
25 | - optional operands | |
26 | - directives: | |
27 | .alias | |
28 | .eb | |
29 | .estate | |
30 | .lb | |
31 | .popsection | |
32 | .previous | |
33 | .psr | |
34 | .pushsection | |
800eeca4 JW |
35 | - labels are wrong if automatic alignment is introduced |
36 | (e.g., checkout the second real10 definition in test-data.s) | |
37 | - DV-related stuff: | |
542d6675 KH |
38 | <reg>.safe_across_calls and any other DV-related directives I don't |
39 | have documentation for. | |
40 | verify mod-sched-brs reads/writes are checked/marked (and other | |
41 | notes) | |
800eeca4 JW |
42 | |
43 | */ | |
44 | ||
45 | #include "as.h" | |
46 | #include "dwarf2dbg.h" | |
47 | #include "subsegs.h" | |
48 | ||
49 | #include "opcode/ia64.h" | |
50 | ||
51 | #include "elf/ia64.h" | |
52 | ||
53 | #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) | |
54 | #define MIN(a,b) ((a) < (b) ? (a) : (b)) | |
55 | ||
56 | #define NUM_SLOTS 4 | |
57 | #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] | |
58 | #define CURR_SLOT md.slot[md.curr_slot] | |
59 | ||
60 | #define O_pseudo_fixup (O_max + 1) | |
61 | ||
62 | enum special_section | |
63 | { | |
64 | SPECIAL_SECTION_BSS = 0, | |
65 | SPECIAL_SECTION_SBSS, | |
66 | SPECIAL_SECTION_SDATA, | |
67 | SPECIAL_SECTION_RODATA, | |
68 | SPECIAL_SECTION_COMMENT, | |
69 | SPECIAL_SECTION_UNWIND, | |
70 | SPECIAL_SECTION_UNWIND_INFO | |
71 | }; | |
72 | ||
73 | enum reloc_func | |
74 | { | |
75 | FUNC_FPTR_RELATIVE, | |
76 | FUNC_GP_RELATIVE, | |
77 | FUNC_LT_RELATIVE, | |
c67e42c9 | 78 | FUNC_PC_RELATIVE, |
800eeca4 JW |
79 | FUNC_PLT_RELATIVE, |
80 | FUNC_SEC_RELATIVE, | |
81 | FUNC_SEG_RELATIVE, | |
82 | FUNC_LTV_RELATIVE, | |
83 | FUNC_LT_FPTR_RELATIVE, | |
84 | }; | |
85 | ||
86 | enum reg_symbol | |
87 | { | |
88 | REG_GR = 0, | |
89 | REG_FR = (REG_GR + 128), | |
90 | REG_AR = (REG_FR + 128), | |
91 | REG_CR = (REG_AR + 128), | |
92 | REG_P = (REG_CR + 128), | |
93 | REG_BR = (REG_P + 64), | |
94 | REG_IP = (REG_BR + 8), | |
95 | REG_CFM, | |
96 | REG_PR, | |
97 | REG_PR_ROT, | |
98 | REG_PSR, | |
99 | REG_PSR_L, | |
100 | REG_PSR_UM, | |
101 | /* The following are pseudo-registers for use by gas only. */ | |
102 | IND_CPUID, | |
103 | IND_DBR, | |
104 | IND_DTR, | |
105 | IND_ITR, | |
106 | IND_IBR, | |
107 | IND_MEM, | |
108 | IND_MSR, | |
109 | IND_PKR, | |
110 | IND_PMC, | |
111 | IND_PMD, | |
112 | IND_RR, | |
542d6675 | 113 | /* The following pseudo-registers are used for unwind directives only: */ |
e0c9811a JW |
114 | REG_PSP, |
115 | REG_PRIUNAT, | |
800eeca4 JW |
116 | REG_NUM |
117 | }; | |
118 | ||
119 | enum dynreg_type | |
120 | { | |
121 | DYNREG_GR = 0, /* dynamic general purpose register */ | |
122 | DYNREG_FR, /* dynamic floating point register */ | |
123 | DYNREG_PR, /* dynamic predicate register */ | |
124 | DYNREG_NUM_TYPES | |
125 | }; | |
126 | ||
127 | /* On the ia64, we can't know the address of a text label until the | |
128 | instructions are packed into a bundle. To handle this, we keep | |
129 | track of the list of labels that appear in front of each | |
130 | instruction. */ | |
131 | struct label_fix | |
542d6675 KH |
132 | { |
133 | struct label_fix *next; | |
134 | struct symbol *sym; | |
135 | }; | |
800eeca4 JW |
136 | |
137 | extern int target_big_endian; | |
138 | ||
139 | /* Characters which always start a comment. */ | |
140 | const char comment_chars[] = ""; | |
141 | ||
142 | /* Characters which start a comment at the beginning of a line. */ | |
143 | const char line_comment_chars[] = "#"; | |
144 | ||
145 | /* Characters which may be used to separate multiple commands on a | |
146 | single line. */ | |
147 | const char line_separator_chars[] = ";"; | |
148 | ||
149 | /* Characters which are used to indicate an exponent in a floating | |
150 | point number. */ | |
151 | const char EXP_CHARS[] = "eE"; | |
152 | ||
153 | /* Characters which mean that a number is a floating point constant, | |
154 | as in 0d1.0. */ | |
155 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
156 | ||
542d6675 | 157 | /* ia64-specific option processing: */ |
800eeca4 | 158 | |
44f5c83a | 159 | const char *md_shortopts = "m:N:x::"; |
800eeca4 JW |
160 | |
161 | struct option md_longopts[] = | |
162 | { | |
c43c2cc5 JW |
163 | #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) |
164 | {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, | |
165 | #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) | |
166 | {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} | |
800eeca4 JW |
167 | }; |
168 | ||
169 | size_t md_longopts_size = sizeof (md_longopts); | |
170 | ||
171 | static struct | |
172 | { | |
173 | struct hash_control *pseudo_hash; /* pseudo opcode hash table */ | |
174 | struct hash_control *reg_hash; /* register name hash table */ | |
175 | struct hash_control *dynreg_hash; /* dynamic register hash table */ | |
176 | struct hash_control *const_hash; /* constant hash table */ | |
177 | struct hash_control *entry_hash; /* code entry hint hash table */ | |
178 | ||
179 | symbolS *regsym[REG_NUM]; | |
180 | ||
181 | /* If X_op is != O_absent, the registername for the instruction's | |
182 | qualifying predicate. If NULL, p0 is assumed for instructions | |
183 | that are predicatable. */ | |
184 | expressionS qp; | |
185 | ||
186 | unsigned int | |
197865e8 | 187 | manual_bundling : 1, |
800eeca4 JW |
188 | debug_dv: 1, |
189 | detect_dv: 1, | |
190 | explicit_mode : 1, /* which mode we're in */ | |
191 | default_explicit_mode : 1, /* which mode is the default */ | |
192 | mode_explicitly_set : 1, /* was the current mode explicitly set? */ | |
193 | auto_align : 1; | |
194 | ||
195 | /* Each bundle consists of up to three instructions. We keep | |
196 | track of four most recent instructions so we can correctly set | |
197865e8 | 197 | the end_of_insn_group for the last instruction in a bundle. */ |
800eeca4 JW |
198 | int curr_slot; |
199 | int num_slots_in_use; | |
200 | struct slot | |
201 | { | |
202 | unsigned int | |
203 | end_of_insn_group : 1, | |
204 | manual_bundling_on : 1, | |
205 | manual_bundling_off : 1; | |
206 | signed char user_template; /* user-selected template, if any */ | |
207 | unsigned char qp_regno; /* qualifying predicate */ | |
208 | /* This duplicates a good fraction of "struct fix" but we | |
209 | can't use a "struct fix" instead since we can't call | |
210 | fix_new_exp() until we know the address of the instruction. */ | |
211 | int num_fixups; | |
212 | struct insn_fix | |
213 | { | |
214 | bfd_reloc_code_real_type code; | |
215 | enum ia64_opnd opnd; /* type of operand in need of fix */ | |
216 | unsigned int is_pcrel : 1; /* is operand pc-relative? */ | |
217 | expressionS expr; /* the value to be inserted */ | |
218 | } | |
219 | fixup[2]; /* at most two fixups per insn */ | |
220 | struct ia64_opcode *idesc; | |
221 | struct label_fix *label_fixups; | |
f1bcba5b | 222 | struct label_fix *tag_fixups; |
800eeca4 JW |
223 | struct unw_rec_list *unwind_record; /* Unwind directive. */ |
224 | expressionS opnd[6]; | |
225 | char *src_file; | |
226 | unsigned int src_line; | |
227 | struct dwarf2_line_info debug_line; | |
228 | } | |
229 | slot[NUM_SLOTS]; | |
230 | ||
231 | segT last_text_seg; | |
232 | ||
233 | struct dynreg | |
234 | { | |
235 | struct dynreg *next; /* next dynamic register */ | |
236 | const char *name; | |
237 | unsigned short base; /* the base register number */ | |
238 | unsigned short num_regs; /* # of registers in this set */ | |
239 | } | |
240 | *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; | |
241 | ||
242 | flagword flags; /* ELF-header flags */ | |
243 | ||
244 | struct mem_offset { | |
245 | unsigned hint:1; /* is this hint currently valid? */ | |
246 | bfd_vma offset; /* mem.offset offset */ | |
247 | bfd_vma base; /* mem.offset base */ | |
248 | } mem_offset; | |
249 | ||
250 | int path; /* number of alt. entry points seen */ | |
251 | const char **entry_labels; /* labels of all alternate paths in | |
542d6675 | 252 | the current DV-checking block. */ |
800eeca4 | 253 | int maxpaths; /* size currently allocated for |
542d6675 | 254 | entry_labels */ |
88be23ec BS |
255 | /* Support for hardware errata workarounds. */ |
256 | ||
257 | /* Record data about the last three insn groups. */ | |
258 | struct group | |
259 | { | |
260 | /* B-step workaround. | |
261 | For each predicate register, this is set if the corresponding insn | |
262 | group conditionally sets this register with one of the affected | |
263 | instructions. */ | |
264 | int p_reg_set[64]; | |
265 | /* B-step workaround. | |
266 | For each general register, this is set if the corresponding insn | |
267 | a) is conditional one one of the predicate registers for which | |
268 | P_REG_SET is 1 in the corresponding entry of the previous group, | |
269 | b) sets this general register with one of the affected | |
270 | instructions. */ | |
271 | int g_reg_set_conditionally[128]; | |
272 | } last_groups[3]; | |
273 | int group_idx; | |
800eeca4 JW |
274 | } |
275 | md; | |
276 | ||
542d6675 | 277 | /* application registers: */ |
800eeca4 | 278 | |
e0c9811a JW |
279 | #define AR_K0 0 |
280 | #define AR_K7 7 | |
281 | #define AR_RSC 16 | |
282 | #define AR_BSP 17 | |
283 | #define AR_BSPSTORE 18 | |
284 | #define AR_RNAT 19 | |
285 | #define AR_UNAT 36 | |
286 | #define AR_FPSR 40 | |
287 | #define AR_ITC 44 | |
288 | #define AR_PFS 64 | |
289 | #define AR_LC 65 | |
800eeca4 JW |
290 | |
291 | static const struct | |
292 | { | |
293 | const char *name; | |
294 | int regnum; | |
295 | } | |
296 | ar[] = | |
297 | { | |
298 | {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, | |
299 | {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, | |
300 | {"ar.rsc", 16}, {"ar.bsp", 17}, | |
301 | {"ar.bspstore", 18}, {"ar.rnat", 19}, | |
302 | {"ar.fcr", 21}, {"ar.eflag", 24}, | |
303 | {"ar.csd", 25}, {"ar.ssd", 26}, | |
304 | {"ar.cflg", 27}, {"ar.fsr", 28}, | |
305 | {"ar.fir", 29}, {"ar.fdr", 30}, | |
306 | {"ar.ccv", 32}, {"ar.unat", 36}, | |
307 | {"ar.fpsr", 40}, {"ar.itc", 44}, | |
308 | {"ar.pfs", 64}, {"ar.lc", 65}, | |
197865e8 | 309 | {"ar.ec", 66}, |
800eeca4 JW |
310 | }; |
311 | ||
312 | #define CR_IPSR 16 | |
313 | #define CR_ISR 17 | |
314 | #define CR_IIP 19 | |
315 | #define CR_IFA 20 | |
316 | #define CR_ITIR 21 | |
317 | #define CR_IIPA 22 | |
318 | #define CR_IFS 23 | |
319 | #define CR_IIM 24 | |
320 | #define CR_IHA 25 | |
321 | #define CR_IVR 65 | |
322 | #define CR_TPR 66 | |
323 | #define CR_EOI 67 | |
324 | #define CR_IRR0 68 | |
325 | #define CR_IRR3 71 | |
326 | #define CR_LRR0 80 | |
327 | #define CR_LRR1 81 | |
328 | ||
542d6675 | 329 | /* control registers: */ |
800eeca4 JW |
330 | static const struct |
331 | { | |
332 | const char *name; | |
333 | int regnum; | |
334 | } | |
335 | cr[] = | |
336 | { | |
337 | {"cr.dcr", 0}, | |
338 | {"cr.itm", 1}, | |
339 | {"cr.iva", 2}, | |
340 | {"cr.pta", 8}, | |
341 | {"cr.gpta", 9}, | |
342 | {"cr.ipsr", 16}, | |
343 | {"cr.isr", 17}, | |
344 | {"cr.iip", 19}, | |
345 | {"cr.ifa", 20}, | |
346 | {"cr.itir", 21}, | |
347 | {"cr.iipa", 22}, | |
348 | {"cr.ifs", 23}, | |
349 | {"cr.iim", 24}, | |
350 | {"cr.iha", 25}, | |
351 | {"cr.lid", 64}, | |
352 | {"cr.ivr", 65}, | |
353 | {"cr.tpr", 66}, | |
354 | {"cr.eoi", 67}, | |
355 | {"cr.irr0", 68}, | |
356 | {"cr.irr1", 69}, | |
357 | {"cr.irr2", 70}, | |
358 | {"cr.irr3", 71}, | |
359 | {"cr.itv", 72}, | |
360 | {"cr.pmv", 73}, | |
361 | {"cr.cmcv", 74}, | |
362 | {"cr.lrr0", 80}, | |
363 | {"cr.lrr1", 81} | |
364 | }; | |
365 | ||
366 | #define PSR_MFL 4 | |
367 | #define PSR_IC 13 | |
368 | #define PSR_DFL 18 | |
369 | #define PSR_CPL 32 | |
370 | ||
371 | static const struct const_desc | |
372 | { | |
373 | const char *name; | |
374 | valueT value; | |
375 | } | |
376 | const_bits[] = | |
377 | { | |
542d6675 | 378 | /* PSR constant masks: */ |
800eeca4 JW |
379 | |
380 | /* 0: reserved */ | |
381 | {"psr.be", ((valueT) 1) << 1}, | |
382 | {"psr.up", ((valueT) 1) << 2}, | |
383 | {"psr.ac", ((valueT) 1) << 3}, | |
384 | {"psr.mfl", ((valueT) 1) << 4}, | |
385 | {"psr.mfh", ((valueT) 1) << 5}, | |
386 | /* 6-12: reserved */ | |
387 | {"psr.ic", ((valueT) 1) << 13}, | |
388 | {"psr.i", ((valueT) 1) << 14}, | |
389 | {"psr.pk", ((valueT) 1) << 15}, | |
390 | /* 16: reserved */ | |
391 | {"psr.dt", ((valueT) 1) << 17}, | |
392 | {"psr.dfl", ((valueT) 1) << 18}, | |
393 | {"psr.dfh", ((valueT) 1) << 19}, | |
394 | {"psr.sp", ((valueT) 1) << 20}, | |
395 | {"psr.pp", ((valueT) 1) << 21}, | |
396 | {"psr.di", ((valueT) 1) << 22}, | |
397 | {"psr.si", ((valueT) 1) << 23}, | |
398 | {"psr.db", ((valueT) 1) << 24}, | |
399 | {"psr.lp", ((valueT) 1) << 25}, | |
400 | {"psr.tb", ((valueT) 1) << 26}, | |
401 | {"psr.rt", ((valueT) 1) << 27}, | |
402 | /* 28-31: reserved */ | |
403 | /* 32-33: cpl (current privilege level) */ | |
404 | {"psr.is", ((valueT) 1) << 34}, | |
405 | {"psr.mc", ((valueT) 1) << 35}, | |
406 | {"psr.it", ((valueT) 1) << 36}, | |
407 | {"psr.id", ((valueT) 1) << 37}, | |
408 | {"psr.da", ((valueT) 1) << 38}, | |
409 | {"psr.dd", ((valueT) 1) << 39}, | |
410 | {"psr.ss", ((valueT) 1) << 40}, | |
411 | /* 41-42: ri (restart instruction) */ | |
412 | {"psr.ed", ((valueT) 1) << 43}, | |
413 | {"psr.bn", ((valueT) 1) << 44}, | |
414 | }; | |
415 | ||
542d6675 | 416 | /* indirect register-sets/memory: */ |
800eeca4 JW |
417 | |
418 | static const struct | |
419 | { | |
420 | const char *name; | |
421 | int regnum; | |
422 | } | |
423 | indirect_reg[] = | |
424 | { | |
425 | { "CPUID", IND_CPUID }, | |
426 | { "cpuid", IND_CPUID }, | |
427 | { "dbr", IND_DBR }, | |
428 | { "dtr", IND_DTR }, | |
429 | { "itr", IND_ITR }, | |
430 | { "ibr", IND_IBR }, | |
431 | { "msr", IND_MSR }, | |
432 | { "pkr", IND_PKR }, | |
433 | { "pmc", IND_PMC }, | |
434 | { "pmd", IND_PMD }, | |
435 | { "rr", IND_RR }, | |
436 | }; | |
437 | ||
438 | /* Pseudo functions used to indicate relocation types (these functions | |
439 | start with an at sign (@). */ | |
440 | static struct | |
441 | { | |
442 | const char *name; | |
443 | enum pseudo_type | |
444 | { | |
445 | PSEUDO_FUNC_NONE, | |
446 | PSEUDO_FUNC_RELOC, | |
447 | PSEUDO_FUNC_CONST, | |
e0c9811a | 448 | PSEUDO_FUNC_REG, |
800eeca4 JW |
449 | PSEUDO_FUNC_FLOAT |
450 | } | |
451 | type; | |
452 | union | |
453 | { | |
454 | unsigned long ival; | |
455 | symbolS *sym; | |
456 | } | |
457 | u; | |
458 | } | |
459 | pseudo_func[] = | |
460 | { | |
542d6675 | 461 | /* reloc pseudo functions (these must come first!): */ |
2434f565 JW |
462 | { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, |
463 | { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, | |
464 | { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, | |
465 | { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
466 | { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, | |
467 | { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
468 | { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
469 | { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, | |
470 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ | |
800eeca4 | 471 | |
542d6675 | 472 | /* mbtype4 constants: */ |
800eeca4 JW |
473 | { "alt", PSEUDO_FUNC_CONST, { 0xa } }, |
474 | { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, | |
475 | { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, | |
476 | { "rev", PSEUDO_FUNC_CONST, { 0xb } }, | |
477 | { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, | |
478 | ||
542d6675 | 479 | /* fclass constants: */ |
bf3ca999 | 480 | { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, |
800eeca4 JW |
481 | { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, |
482 | { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, | |
483 | { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, | |
484 | { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, | |
485 | { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, | |
486 | { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, | |
487 | { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, | |
488 | { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, | |
bf3ca999 TW |
489 | |
490 | { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ | |
e0c9811a | 491 | |
542d6675 | 492 | /* unwind-related constants: */ |
e0c9811a JW |
493 | { "svr4", PSEUDO_FUNC_CONST, { 0 } }, |
494 | { "hpux", PSEUDO_FUNC_CONST, { 1 } }, | |
495 | { "nt", PSEUDO_FUNC_CONST, { 2 } }, | |
496 | ||
542d6675 | 497 | /* unwind-related registers: */ |
e0c9811a | 498 | { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } |
800eeca4 JW |
499 | }; |
500 | ||
542d6675 | 501 | /* 41-bit nop opcodes (one per unit): */ |
800eeca4 JW |
502 | static const bfd_vma nop[IA64_NUM_UNITS] = |
503 | { | |
504 | 0x0000000000LL, /* NIL => break 0 */ | |
505 | 0x0008000000LL, /* I-unit nop */ | |
506 | 0x0008000000LL, /* M-unit nop */ | |
507 | 0x4000000000LL, /* B-unit nop */ | |
508 | 0x0008000000LL, /* F-unit nop */ | |
509 | 0x0008000000LL, /* L-"unit" nop */ | |
510 | 0x0008000000LL, /* X-unit nop */ | |
511 | }; | |
512 | ||
513 | /* Can't be `const' as it's passed to input routines (which have the | |
514 | habit of setting temporary sentinels. */ | |
515 | static char special_section_name[][20] = | |
516 | { | |
517 | {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, | |
518 | {".IA_64.unwind"}, {".IA_64.unwind_info"} | |
519 | }; | |
520 | ||
521 | /* The best template for a particular sequence of up to three | |
522 | instructions: */ | |
523 | #define N IA64_NUM_TYPES | |
524 | static unsigned char best_template[N][N][N]; | |
525 | #undef N | |
526 | ||
527 | /* Resource dependencies currently in effect */ | |
528 | static struct rsrc { | |
529 | int depind; /* dependency index */ | |
530 | const struct ia64_dependency *dependency; /* actual dependency */ | |
531 | unsigned specific:1, /* is this a specific bit/regno? */ | |
532 | link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ | |
533 | int index; /* specific regno/bit within dependency */ | |
534 | int note; /* optional qualifying note (0 if none) */ | |
535 | #define STATE_NONE 0 | |
536 | #define STATE_STOP 1 | |
537 | #define STATE_SRLZ 2 | |
538 | int insn_srlz; /* current insn serialization state */ | |
539 | int data_srlz; /* current data serialization state */ | |
540 | int qp_regno; /* qualifying predicate for this usage */ | |
541 | char *file; /* what file marked this dependency */ | |
2434f565 | 542 | unsigned int line; /* what line marked this dependency */ |
800eeca4 | 543 | struct mem_offset mem_offset; /* optional memory offset hint */ |
7484b8e6 | 544 | enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ |
800eeca4 JW |
545 | int path; /* corresponding code entry index */ |
546 | } *regdeps = NULL; | |
547 | static int regdepslen = 0; | |
548 | static int regdepstotlen = 0; | |
549 | static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; | |
550 | static const char *dv_sem[] = { "none", "implied", "impliedf", | |
139368c9 | 551 | "data", "instr", "specific", "stop", "other" }; |
7484b8e6 | 552 | static const char *dv_cmp_type[] = { "none", "OR", "AND" }; |
800eeca4 JW |
553 | |
554 | /* Current state of PR mutexation */ | |
555 | static struct qpmutex { | |
556 | valueT prmask; | |
557 | int path; | |
558 | } *qp_mutexes = NULL; /* QP mutex bitmasks */ | |
559 | static int qp_mutexeslen = 0; | |
560 | static int qp_mutexestotlen = 0; | |
197865e8 | 561 | static valueT qp_safe_across_calls = 0; |
800eeca4 JW |
562 | |
563 | /* Current state of PR implications */ | |
564 | static struct qp_imply { | |
565 | unsigned p1:6; | |
566 | unsigned p2:6; | |
567 | unsigned p2_branched:1; | |
568 | int path; | |
569 | } *qp_implies = NULL; | |
570 | static int qp_implieslen = 0; | |
571 | static int qp_impliestotlen = 0; | |
572 | ||
197865e8 KH |
573 | /* Keep track of static GR values so that indirect register usage can |
574 | sometimes be tracked. */ | |
800eeca4 JW |
575 | static struct gr { |
576 | unsigned known:1; | |
577 | int path; | |
578 | valueT value; | |
2434f565 | 579 | } gr_values[128] = {{ 1, 0, 0 }}; |
800eeca4 JW |
580 | |
581 | /* These are the routines required to output the various types of | |
582 | unwind records. */ | |
583 | ||
f5a30c2e JW |
584 | /* A slot_number is a frag address plus the slot index (0-2). We use the |
585 | frag address here so that if there is a section switch in the middle of | |
586 | a function, then instructions emitted to a different section are not | |
587 | counted. Since there may be more than one frag for a function, this | |
588 | means we also need to keep track of which frag this address belongs to | |
589 | so we can compute inter-frag distances. This also nicely solves the | |
590 | problem with nops emitted for align directives, which can't easily be | |
591 | counted, but can easily be derived from frag sizes. */ | |
592 | ||
800eeca4 JW |
593 | typedef struct unw_rec_list { |
594 | unwind_record r; | |
e0c9811a | 595 | unsigned long slot_number; |
f5a30c2e | 596 | fragS *slot_frag; |
800eeca4 JW |
597 | struct unw_rec_list *next; |
598 | } unw_rec_list; | |
599 | ||
2434f565 | 600 | #define SLOT_NUM_NOT_SET (unsigned)-1 |
800eeca4 | 601 | |
e0c9811a JW |
602 | static struct |
603 | { | |
604 | unsigned long next_slot_number; | |
f5a30c2e | 605 | fragS *next_slot_frag; |
e0c9811a JW |
606 | |
607 | /* Maintain a list of unwind entries for the current function. */ | |
608 | unw_rec_list *list; | |
609 | unw_rec_list *tail; | |
800eeca4 | 610 | |
e0c9811a JW |
611 | /* Any unwind entires that should be attached to the current slot |
612 | that an insn is being constructed for. */ | |
613 | unw_rec_list *current_entry; | |
800eeca4 | 614 | |
e0c9811a JW |
615 | /* These are used to create the unwind table entry for this function. */ |
616 | symbolS *proc_start; | |
617 | symbolS *proc_end; | |
618 | symbolS *info; /* pointer to unwind info */ | |
619 | symbolS *personality_routine; | |
800eeca4 | 620 | |
e0c9811a JW |
621 | /* TRUE if processing unwind directives in a prologue region. */ |
622 | int prologue; | |
30d25259 | 623 | int prologue_mask; |
e0c9811a | 624 | } unwind; |
800eeca4 JW |
625 | |
626 | typedef void (*vbyte_func) PARAMS ((int, char *, char *)); | |
627 | ||
542d6675 | 628 | /* Forward delarations: */ |
800eeca4 JW |
629 | static int ar_is_in_integer_unit PARAMS ((int regnum)); |
630 | static void set_section PARAMS ((char *name)); | |
631 | static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, | |
632 | unsigned int, unsigned int)); | |
633 | static void dot_radix PARAMS ((int)); | |
634 | static void dot_special_section PARAMS ((int)); | |
635 | static void dot_proc PARAMS ((int)); | |
636 | static void dot_fframe PARAMS ((int)); | |
637 | static void dot_vframe PARAMS ((int)); | |
150f24a2 JW |
638 | static void dot_vframesp PARAMS ((int)); |
639 | static void dot_vframepsp PARAMS ((int)); | |
800eeca4 JW |
640 | static void dot_save PARAMS ((int)); |
641 | static void dot_restore PARAMS ((int)); | |
150f24a2 JW |
642 | static void dot_restorereg PARAMS ((int)); |
643 | static void dot_restorereg_p PARAMS ((int)); | |
800eeca4 JW |
644 | static void dot_handlerdata PARAMS ((int)); |
645 | static void dot_unwentry PARAMS ((int)); | |
646 | static void dot_altrp PARAMS ((int)); | |
e0c9811a | 647 | static void dot_savemem PARAMS ((int)); |
800eeca4 JW |
648 | static void dot_saveg PARAMS ((int)); |
649 | static void dot_savef PARAMS ((int)); | |
650 | static void dot_saveb PARAMS ((int)); | |
651 | static void dot_savegf PARAMS ((int)); | |
652 | static void dot_spill PARAMS ((int)); | |
150f24a2 JW |
653 | static void dot_spillreg PARAMS ((int)); |
654 | static void dot_spillmem PARAMS ((int)); | |
655 | static void dot_spillreg_p PARAMS ((int)); | |
656 | static void dot_spillmem_p PARAMS ((int)); | |
657 | static void dot_label_state PARAMS ((int)); | |
658 | static void dot_copy_state PARAMS ((int)); | |
800eeca4 JW |
659 | static void dot_unwabi PARAMS ((int)); |
660 | static void dot_personality PARAMS ((int)); | |
661 | static void dot_body PARAMS ((int)); | |
662 | static void dot_prologue PARAMS ((int)); | |
663 | static void dot_endp PARAMS ((int)); | |
664 | static void dot_template PARAMS ((int)); | |
665 | static void dot_regstk PARAMS ((int)); | |
666 | static void dot_rot PARAMS ((int)); | |
667 | static void dot_byteorder PARAMS ((int)); | |
668 | static void dot_psr PARAMS ((int)); | |
669 | static void dot_alias PARAMS ((int)); | |
670 | static void dot_ln PARAMS ((int)); | |
671 | static char *parse_section_name PARAMS ((void)); | |
672 | static void dot_xdata PARAMS ((int)); | |
673 | static void stmt_float_cons PARAMS ((int)); | |
674 | static void stmt_cons_ua PARAMS ((int)); | |
675 | static void dot_xfloat_cons PARAMS ((int)); | |
676 | static void dot_xstringer PARAMS ((int)); | |
677 | static void dot_xdata_ua PARAMS ((int)); | |
678 | static void dot_xfloat_cons_ua PARAMS ((int)); | |
150f24a2 | 679 | static void print_prmask PARAMS ((valueT mask)); |
800eeca4 JW |
680 | static void dot_pred_rel PARAMS ((int)); |
681 | static void dot_reg_val PARAMS ((int)); | |
682 | static void dot_dv_mode PARAMS ((int)); | |
683 | static void dot_entry PARAMS ((int)); | |
684 | static void dot_mem_offset PARAMS ((int)); | |
e0c9811a | 685 | static void add_unwind_entry PARAMS((unw_rec_list *ptr)); |
542d6675 | 686 | static symbolS *declare_register PARAMS ((const char *name, int regnum)); |
800eeca4 JW |
687 | static void declare_register_set PARAMS ((const char *, int, int)); |
688 | static unsigned int operand_width PARAMS ((enum ia64_opnd)); | |
689 | static int operand_match PARAMS ((const struct ia64_opcode *idesc, | |
690 | int index, expressionS *e)); | |
691 | static int parse_operand PARAMS ((expressionS *e)); | |
692 | static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); | |
693 | static void build_insn PARAMS ((struct slot *, bfd_vma *)); | |
694 | static void emit_one_bundle PARAMS ((void)); | |
695 | static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); | |
197865e8 | 696 | static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, |
800eeca4 JW |
697 | bfd_reloc_code_real_type r_type)); |
698 | static void insn_group_break PARAMS ((int, int, int)); | |
150f24a2 JW |
699 | static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, |
700 | struct rsrc *, int depind, int path)); | |
800eeca4 JW |
701 | static void add_qp_mutex PARAMS((valueT mask)); |
702 | static void add_qp_imply PARAMS((int p1, int p2)); | |
703 | static void clear_qp_branch_flag PARAMS((valueT mask)); | |
704 | static void clear_qp_mutex PARAMS((valueT mask)); | |
705 | static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); | |
706 | static void clear_register_values PARAMS ((void)); | |
707 | static void print_dependency PARAMS ((const char *action, int depind)); | |
150f24a2 JW |
708 | static void instruction_serialization PARAMS ((void)); |
709 | static void data_serialization PARAMS ((void)); | |
710 | static void remove_marked_resource PARAMS ((struct rsrc *)); | |
800eeca4 | 711 | static int is_conditional_branch PARAMS ((struct ia64_opcode *)); |
150f24a2 | 712 | static int is_taken_branch PARAMS ((struct ia64_opcode *)); |
800eeca4 | 713 | static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); |
150f24a2 JW |
714 | static int depends_on PARAMS ((int, struct ia64_opcode *)); |
715 | static int specify_resource PARAMS ((const struct ia64_dependency *, | |
716 | struct ia64_opcode *, int, struct rsrc [], int, int)); | |
800eeca4 JW |
717 | static int check_dv PARAMS((struct ia64_opcode *idesc)); |
718 | static void check_dependencies PARAMS((struct ia64_opcode *)); | |
719 | static void mark_resources PARAMS((struct ia64_opcode *)); | |
720 | static void update_dependencies PARAMS((struct ia64_opcode *)); | |
721 | static void note_register_values PARAMS((struct ia64_opcode *)); | |
150f24a2 JW |
722 | static int qp_mutex PARAMS ((int, int, int)); |
723 | static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); | |
724 | static void output_vbyte_mem PARAMS ((int, char *, char *)); | |
725 | static void count_output PARAMS ((int, char *, char *)); | |
726 | static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); | |
727 | static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); | |
800eeca4 | 728 | static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
150f24a2 JW |
729 | static void output_P1_format PARAMS ((vbyte_func, int)); |
730 | static void output_P2_format PARAMS ((vbyte_func, int, int)); | |
731 | static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); | |
732 | static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); | |
733 | static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); | |
734 | static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); | |
735 | static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); | |
736 | static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
737 | static void output_P9_format PARAMS ((vbyte_func, int, int)); | |
738 | static void output_P10_format PARAMS ((vbyte_func, int, int)); | |
739 | static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
740 | static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); | |
800eeca4 JW |
741 | static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
742 | static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
150f24a2 JW |
743 | static char format_ab_reg PARAMS ((int, int)); |
744 | static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, | |
745 | unsigned long)); | |
746 | static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); | |
747 | static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, | |
748 | unsigned long)); | |
749 | static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); | |
750 | static void free_list_records PARAMS ((unw_rec_list *)); | |
751 | static unw_rec_list *output_prologue PARAMS ((void)); | |
752 | static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); | |
753 | static unw_rec_list *output_body PARAMS ((void)); | |
754 | static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); | |
755 | static unw_rec_list *output_mem_stack_v PARAMS ((void)); | |
756 | static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); | |
757 | static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); | |
758 | static unw_rec_list *output_rp_when PARAMS ((void)); | |
759 | static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); | |
760 | static unw_rec_list *output_rp_br PARAMS ((unsigned int)); | |
761 | static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); | |
762 | static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); | |
763 | static unw_rec_list *output_pfs_when PARAMS ((void)); | |
764 | static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); | |
765 | static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); | |
766 | static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); | |
767 | static unw_rec_list *output_preds_when PARAMS ((void)); | |
768 | static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); | |
769 | static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); | |
770 | static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); | |
771 | static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); | |
772 | static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); | |
773 | static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); | |
774 | static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); | |
775 | static unw_rec_list *output_br_mem PARAMS ((unsigned int)); | |
776 | static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); | |
777 | static unw_rec_list *output_spill_base PARAMS ((unsigned int)); | |
778 | static unw_rec_list *output_unat_when PARAMS ((void)); | |
779 | static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); | |
780 | static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); | |
781 | static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); | |
782 | static unw_rec_list *output_lc_when PARAMS ((void)); | |
783 | static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); | |
784 | static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); | |
785 | static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); | |
786 | static unw_rec_list *output_fpsr_when PARAMS ((void)); | |
787 | static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); | |
788 | static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); | |
789 | static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); | |
790 | static unw_rec_list *output_priunat_when_gr PARAMS ((void)); | |
791 | static unw_rec_list *output_priunat_when_mem PARAMS ((void)); | |
792 | static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); | |
793 | static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); | |
794 | static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); | |
795 | static unw_rec_list *output_bsp_when PARAMS ((void)); | |
796 | static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); | |
797 | static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); | |
798 | static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); | |
799 | static unw_rec_list *output_bspstore_when PARAMS ((void)); | |
800 | static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); | |
801 | static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); | |
802 | static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); | |
803 | static unw_rec_list *output_rnat_when PARAMS ((void)); | |
804 | static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); | |
805 | static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); | |
806 | static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); | |
807 | static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); | |
808 | static unw_rec_list *output_epilogue PARAMS ((unsigned long)); | |
809 | static unw_rec_list *output_label_state PARAMS ((unsigned long)); | |
810 | static unw_rec_list *output_copy_state PARAMS ((unsigned long)); | |
811 | static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
812 | static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
813 | static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
814 | unsigned int)); | |
815 | static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
816 | unsigned int)); | |
817 | static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, | |
818 | unsigned int)); | |
819 | static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
820 | unsigned int, unsigned int)); | |
821 | static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); | |
822 | static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); | |
823 | static int calc_record_size PARAMS ((unw_rec_list *)); | |
824 | static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); | |
825 | static int count_bits PARAMS ((unsigned long)); | |
f5a30c2e JW |
826 | static unsigned long slot_index PARAMS ((unsigned long, fragS *, |
827 | unsigned long, fragS *)); | |
150f24a2 JW |
828 | static void fixup_unw_records PARAMS ((unw_rec_list *)); |
829 | static int output_unw_records PARAMS ((unw_rec_list *, void **)); | |
830 | static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
831 | static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
832 | static int generate_unwind_image PARAMS ((void)); | |
800eeca4 JW |
833 | |
834 | /* Determine if application register REGNUM resides in the integer | |
835 | unit (as opposed to the memory unit). */ | |
836 | static int | |
837 | ar_is_in_integer_unit (reg) | |
838 | int reg; | |
839 | { | |
840 | reg -= REG_AR; | |
841 | ||
842 | return (reg == 64 /* pfs */ | |
843 | || reg == 65 /* lc */ | |
844 | || reg == 66 /* ec */ | |
845 | /* ??? ias accepts and puts these in the integer unit. */ | |
846 | || (reg >= 112 && reg <= 127)); | |
847 | } | |
848 | ||
849 | /* Switch to section NAME and create section if necessary. It's | |
850 | rather ugly that we have to manipulate input_line_pointer but I | |
851 | don't see any other way to accomplish the same thing without | |
852 | changing obj-elf.c (which may be the Right Thing, in the end). */ | |
853 | static void | |
854 | set_section (name) | |
855 | char *name; | |
856 | { | |
857 | char *saved_input_line_pointer; | |
858 | ||
859 | saved_input_line_pointer = input_line_pointer; | |
860 | input_line_pointer = name; | |
861 | obj_elf_section (0); | |
862 | input_line_pointer = saved_input_line_pointer; | |
863 | } | |
864 | ||
865 | /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ | |
866 | ||
867 | flagword | |
868 | ia64_elf_section_flags (flags, attr, type) | |
869 | flagword flags; | |
2434f565 | 870 | int attr, type ATTRIBUTE_UNUSED; |
800eeca4 JW |
871 | { |
872 | if (attr & SHF_IA_64_SHORT) | |
873 | flags |= SEC_SMALL_DATA; | |
874 | return flags; | |
875 | } | |
876 | ||
877 | static unsigned int | |
878 | set_regstack (ins, locs, outs, rots) | |
879 | unsigned int ins, locs, outs, rots; | |
880 | { | |
542d6675 KH |
881 | /* Size of frame. */ |
882 | unsigned int sof; | |
800eeca4 JW |
883 | |
884 | sof = ins + locs + outs; | |
885 | if (sof > 96) | |
886 | { | |
887 | as_bad ("Size of frame exceeds maximum of 96 registers"); | |
888 | return 0; | |
889 | } | |
890 | if (rots > sof) | |
891 | { | |
892 | as_warn ("Size of rotating registers exceeds frame size"); | |
893 | return 0; | |
894 | } | |
895 | md.in.base = REG_GR + 32; | |
896 | md.loc.base = md.in.base + ins; | |
897 | md.out.base = md.loc.base + locs; | |
898 | ||
899 | md.in.num_regs = ins; | |
900 | md.loc.num_regs = locs; | |
901 | md.out.num_regs = outs; | |
902 | md.rot.num_regs = rots; | |
903 | return sof; | |
904 | } | |
905 | ||
906 | void | |
907 | ia64_flush_insns () | |
908 | { | |
909 | struct label_fix *lfix; | |
910 | segT saved_seg; | |
911 | subsegT saved_subseg; | |
b44b1b85 | 912 | unw_rec_list *ptr; |
800eeca4 JW |
913 | |
914 | if (!md.last_text_seg) | |
915 | return; | |
916 | ||
917 | saved_seg = now_seg; | |
918 | saved_subseg = now_subseg; | |
919 | ||
920 | subseg_set (md.last_text_seg, 0); | |
921 | ||
922 | while (md.num_slots_in_use > 0) | |
923 | emit_one_bundle (); /* force out queued instructions */ | |
924 | ||
925 | /* In case there are labels following the last instruction, resolve | |
542d6675 | 926 | those now: */ |
800eeca4 JW |
927 | for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) |
928 | { | |
929 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
930 | symbol_set_frag (lfix->sym, frag_now); | |
931 | } | |
932 | CURR_SLOT.label_fixups = 0; | |
f1bcba5b JW |
933 | for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) |
934 | { | |
935 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
936 | symbol_set_frag (lfix->sym, frag_now); | |
937 | } | |
938 | CURR_SLOT.tag_fixups = 0; | |
800eeca4 | 939 | |
b44b1b85 JW |
940 | /* In case there are unwind directives following the last instruction, |
941 | resolve those now. We only handle body and prologue directives here. | |
942 | Give an error for others. */ | |
943 | for (ptr = unwind.current_entry; ptr; ptr = ptr->next) | |
944 | { | |
945 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr | |
946 | || ptr->r.type == body) | |
947 | { | |
948 | ptr->slot_number = (unsigned long) frag_more (0); | |
949 | ptr->slot_frag = frag_now; | |
950 | } | |
951 | else | |
952 | as_bad (_("Unwind directive not followed by an instruction.")); | |
953 | } | |
954 | unwind.current_entry = NULL; | |
955 | ||
800eeca4 | 956 | subseg_set (saved_seg, saved_subseg); |
f1bcba5b JW |
957 | |
958 | if (md.qp.X_op == O_register) | |
959 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
960 | } |
961 | ||
962 | void | |
963 | ia64_do_align (nbytes) | |
964 | int nbytes; | |
965 | { | |
966 | char *saved_input_line_pointer = input_line_pointer; | |
967 | ||
968 | input_line_pointer = ""; | |
969 | s_align_bytes (nbytes); | |
970 | input_line_pointer = saved_input_line_pointer; | |
971 | } | |
972 | ||
973 | void | |
974 | ia64_cons_align (nbytes) | |
975 | int nbytes; | |
976 | { | |
977 | if (md.auto_align) | |
978 | { | |
979 | char *saved_input_line_pointer = input_line_pointer; | |
980 | input_line_pointer = ""; | |
981 | s_align_bytes (nbytes); | |
982 | input_line_pointer = saved_input_line_pointer; | |
983 | } | |
984 | } | |
985 | ||
986 | /* Output COUNT bytes to a memory location. */ | |
987 | static unsigned char *vbyte_mem_ptr = NULL; | |
988 | ||
197865e8 | 989 | void |
800eeca4 JW |
990 | output_vbyte_mem (count, ptr, comment) |
991 | int count; | |
992 | char *ptr; | |
2434f565 | 993 | char *comment ATTRIBUTE_UNUSED; |
800eeca4 JW |
994 | { |
995 | int x; | |
996 | if (vbyte_mem_ptr == NULL) | |
997 | abort (); | |
998 | ||
999 | if (count == 0) | |
1000 | return; | |
1001 | for (x = 0; x < count; x++) | |
1002 | *(vbyte_mem_ptr++) = ptr[x]; | |
1003 | } | |
1004 | ||
1005 | /* Count the number of bytes required for records. */ | |
1006 | static int vbyte_count = 0; | |
197865e8 | 1007 | void |
800eeca4 JW |
1008 | count_output (count, ptr, comment) |
1009 | int count; | |
2434f565 JW |
1010 | char *ptr ATTRIBUTE_UNUSED; |
1011 | char *comment ATTRIBUTE_UNUSED; | |
800eeca4 JW |
1012 | { |
1013 | vbyte_count += count; | |
1014 | } | |
1015 | ||
1016 | static void | |
1017 | output_R1_format (f, rtype, rlen) | |
1018 | vbyte_func f; | |
1019 | unw_record_type rtype; | |
1020 | int rlen; | |
1021 | { | |
e0c9811a | 1022 | int r = 0; |
800eeca4 JW |
1023 | char byte; |
1024 | if (rlen > 0x1f) | |
1025 | { | |
1026 | output_R3_format (f, rtype, rlen); | |
1027 | return; | |
1028 | } | |
197865e8 | 1029 | |
e0c9811a JW |
1030 | if (rtype == body) |
1031 | r = 1; | |
1032 | else if (rtype != prologue) | |
1033 | as_bad ("record type is not valid"); | |
1034 | ||
800eeca4 JW |
1035 | byte = UNW_R1 | (r << 5) | (rlen & 0x1f); |
1036 | (*f) (1, &byte, NULL); | |
1037 | } | |
1038 | ||
1039 | static void | |
1040 | output_R2_format (f, mask, grsave, rlen) | |
1041 | vbyte_func f; | |
1042 | int mask, grsave; | |
1043 | unsigned long rlen; | |
1044 | { | |
1045 | char bytes[20]; | |
1046 | int count = 2; | |
1047 | mask = (mask & 0x0f); | |
1048 | grsave = (grsave & 0x7f); | |
1049 | ||
1050 | bytes[0] = (UNW_R2 | (mask >> 1)); | |
1051 | bytes[1] = (((mask & 0x01) << 7) | grsave); | |
1052 | count += output_leb128 (bytes + 2, rlen, 0); | |
1053 | (*f) (count, bytes, NULL); | |
1054 | } | |
1055 | ||
1056 | static void | |
1057 | output_R3_format (f, rtype, rlen) | |
1058 | vbyte_func f; | |
1059 | unw_record_type rtype; | |
1060 | unsigned long rlen; | |
1061 | { | |
e0c9811a | 1062 | int r = 0, count; |
800eeca4 JW |
1063 | char bytes[20]; |
1064 | if (rlen <= 0x1f) | |
1065 | { | |
1066 | output_R1_format (f, rtype, rlen); | |
1067 | return; | |
1068 | } | |
197865e8 | 1069 | |
e0c9811a JW |
1070 | if (rtype == body) |
1071 | r = 1; | |
1072 | else if (rtype != prologue) | |
1073 | as_bad ("record type is not valid"); | |
800eeca4 JW |
1074 | bytes[0] = (UNW_R3 | r); |
1075 | count = output_leb128 (bytes + 1, rlen, 0); | |
1076 | (*f) (count + 1, bytes, NULL); | |
1077 | } | |
1078 | ||
1079 | static void | |
1080 | output_P1_format (f, brmask) | |
1081 | vbyte_func f; | |
1082 | int brmask; | |
1083 | { | |
1084 | char byte; | |
1085 | byte = UNW_P1 | (brmask & 0x1f); | |
1086 | (*f) (1, &byte, NULL); | |
1087 | } | |
1088 | ||
1089 | static void | |
1090 | output_P2_format (f, brmask, gr) | |
1091 | vbyte_func f; | |
1092 | int brmask; | |
1093 | int gr; | |
1094 | { | |
1095 | char bytes[2]; | |
1096 | brmask = (brmask & 0x1f); | |
1097 | bytes[0] = UNW_P2 | (brmask >> 1); | |
1098 | bytes[1] = (((brmask & 1) << 7) | gr); | |
1099 | (*f) (2, bytes, NULL); | |
1100 | } | |
1101 | ||
1102 | static void | |
1103 | output_P3_format (f, rtype, reg) | |
1104 | vbyte_func f; | |
1105 | unw_record_type rtype; | |
1106 | int reg; | |
1107 | { | |
1108 | char bytes[2]; | |
e0c9811a | 1109 | int r = 0; |
800eeca4 JW |
1110 | reg = (reg & 0x7f); |
1111 | switch (rtype) | |
542d6675 | 1112 | { |
800eeca4 JW |
1113 | case psp_gr: |
1114 | r = 0; | |
1115 | break; | |
1116 | case rp_gr: | |
1117 | r = 1; | |
1118 | break; | |
1119 | case pfs_gr: | |
1120 | r = 2; | |
1121 | break; | |
1122 | case preds_gr: | |
1123 | r = 3; | |
1124 | break; | |
1125 | case unat_gr: | |
1126 | r = 4; | |
1127 | break; | |
1128 | case lc_gr: | |
1129 | r = 5; | |
1130 | break; | |
1131 | case rp_br: | |
1132 | r = 6; | |
1133 | break; | |
1134 | case rnat_gr: | |
1135 | r = 7; | |
1136 | break; | |
1137 | case bsp_gr: | |
1138 | r = 8; | |
1139 | break; | |
1140 | case bspstore_gr: | |
1141 | r = 9; | |
1142 | break; | |
1143 | case fpsr_gr: | |
1144 | r = 10; | |
1145 | break; | |
1146 | case priunat_gr: | |
1147 | r = 11; | |
1148 | break; | |
1149 | default: | |
1150 | as_bad ("Invalid record type for P3 format."); | |
542d6675 | 1151 | } |
800eeca4 JW |
1152 | bytes[0] = (UNW_P3 | (r >> 1)); |
1153 | bytes[1] = (((r & 1) << 7) | reg); | |
1154 | (*f) (2, bytes, NULL); | |
1155 | } | |
1156 | ||
800eeca4 | 1157 | static void |
e0c9811a | 1158 | output_P4_format (f, imask, imask_size) |
800eeca4 | 1159 | vbyte_func f; |
e0c9811a JW |
1160 | unsigned char *imask; |
1161 | unsigned long imask_size; | |
800eeca4 | 1162 | { |
e0c9811a JW |
1163 | imask[0] = UNW_P4; |
1164 | (*f) (imask_size, imask, NULL); | |
800eeca4 JW |
1165 | } |
1166 | ||
1167 | static void | |
1168 | output_P5_format (f, grmask, frmask) | |
1169 | vbyte_func f; | |
1170 | int grmask; | |
1171 | unsigned long frmask; | |
1172 | { | |
1173 | char bytes[4]; | |
1174 | grmask = (grmask & 0x0f); | |
1175 | ||
1176 | bytes[0] = UNW_P5; | |
1177 | bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); | |
1178 | bytes[2] = ((frmask & 0x0000ff00) >> 8); | |
1179 | bytes[3] = (frmask & 0x000000ff); | |
1180 | (*f) (4, bytes, NULL); | |
1181 | } | |
1182 | ||
1183 | static void | |
1184 | output_P6_format (f, rtype, rmask) | |
1185 | vbyte_func f; | |
1186 | unw_record_type rtype; | |
1187 | int rmask; | |
1188 | { | |
1189 | char byte; | |
e0c9811a | 1190 | int r = 0; |
197865e8 | 1191 | |
e0c9811a JW |
1192 | if (rtype == gr_mem) |
1193 | r = 1; | |
1194 | else if (rtype != fr_mem) | |
1195 | as_bad ("Invalid record type for format P6"); | |
800eeca4 JW |
1196 | byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); |
1197 | (*f) (1, &byte, NULL); | |
1198 | } | |
1199 | ||
1200 | static void | |
1201 | output_P7_format (f, rtype, w1, w2) | |
1202 | vbyte_func f; | |
1203 | unw_record_type rtype; | |
1204 | unsigned long w1; | |
1205 | unsigned long w2; | |
1206 | { | |
1207 | char bytes[20]; | |
1208 | int count = 1; | |
e0c9811a | 1209 | int r = 0; |
800eeca4 JW |
1210 | count += output_leb128 (bytes + 1, w1, 0); |
1211 | switch (rtype) | |
1212 | { | |
542d6675 KH |
1213 | case mem_stack_f: |
1214 | r = 0; | |
1215 | count += output_leb128 (bytes + count, w2 >> 4, 0); | |
1216 | break; | |
1217 | case mem_stack_v: | |
1218 | r = 1; | |
1219 | break; | |
1220 | case spill_base: | |
1221 | r = 2; | |
1222 | break; | |
1223 | case psp_sprel: | |
1224 | r = 3; | |
1225 | break; | |
1226 | case rp_when: | |
1227 | r = 4; | |
1228 | break; | |
1229 | case rp_psprel: | |
1230 | r = 5; | |
1231 | break; | |
1232 | case pfs_when: | |
1233 | r = 6; | |
1234 | break; | |
1235 | case pfs_psprel: | |
1236 | r = 7; | |
1237 | break; | |
1238 | case preds_when: | |
1239 | r = 8; | |
1240 | break; | |
1241 | case preds_psprel: | |
1242 | r = 9; | |
1243 | break; | |
1244 | case lc_when: | |
1245 | r = 10; | |
1246 | break; | |
1247 | case lc_psprel: | |
1248 | r = 11; | |
1249 | break; | |
1250 | case unat_when: | |
1251 | r = 12; | |
1252 | break; | |
1253 | case unat_psprel: | |
1254 | r = 13; | |
1255 | break; | |
1256 | case fpsr_when: | |
1257 | r = 14; | |
1258 | break; | |
1259 | case fpsr_psprel: | |
1260 | r = 15; | |
1261 | break; | |
1262 | default: | |
1263 | break; | |
800eeca4 JW |
1264 | } |
1265 | bytes[0] = (UNW_P7 | r); | |
1266 | (*f) (count, bytes, NULL); | |
1267 | } | |
1268 | ||
1269 | static void | |
1270 | output_P8_format (f, rtype, t) | |
1271 | vbyte_func f; | |
1272 | unw_record_type rtype; | |
1273 | unsigned long t; | |
1274 | { | |
1275 | char bytes[20]; | |
e0c9811a | 1276 | int r = 0; |
800eeca4 JW |
1277 | int count = 2; |
1278 | bytes[0] = UNW_P8; | |
1279 | switch (rtype) | |
1280 | { | |
542d6675 KH |
1281 | case rp_sprel: |
1282 | r = 1; | |
1283 | break; | |
1284 | case pfs_sprel: | |
1285 | r = 2; | |
1286 | break; | |
1287 | case preds_sprel: | |
1288 | r = 3; | |
1289 | break; | |
1290 | case lc_sprel: | |
1291 | r = 4; | |
1292 | break; | |
1293 | case unat_sprel: | |
1294 | r = 5; | |
1295 | break; | |
1296 | case fpsr_sprel: | |
1297 | r = 6; | |
1298 | break; | |
1299 | case bsp_when: | |
1300 | r = 7; | |
1301 | break; | |
1302 | case bsp_psprel: | |
1303 | r = 8; | |
1304 | break; | |
1305 | case bsp_sprel: | |
1306 | r = 9; | |
1307 | break; | |
1308 | case bspstore_when: | |
1309 | r = 10; | |
1310 | break; | |
1311 | case bspstore_psprel: | |
1312 | r = 11; | |
1313 | break; | |
1314 | case bspstore_sprel: | |
1315 | r = 12; | |
1316 | break; | |
1317 | case rnat_when: | |
1318 | r = 13; | |
1319 | break; | |
1320 | case rnat_psprel: | |
1321 | r = 14; | |
1322 | break; | |
1323 | case rnat_sprel: | |
1324 | r = 15; | |
1325 | break; | |
1326 | case priunat_when_gr: | |
1327 | r = 16; | |
1328 | break; | |
1329 | case priunat_psprel: | |
1330 | r = 17; | |
1331 | break; | |
1332 | case priunat_sprel: | |
1333 | r = 18; | |
1334 | break; | |
1335 | case priunat_when_mem: | |
1336 | r = 19; | |
1337 | break; | |
1338 | default: | |
1339 | break; | |
800eeca4 JW |
1340 | } |
1341 | bytes[1] = r; | |
1342 | count += output_leb128 (bytes + 2, t, 0); | |
1343 | (*f) (count, bytes, NULL); | |
1344 | } | |
1345 | ||
1346 | static void | |
1347 | output_P9_format (f, grmask, gr) | |
1348 | vbyte_func f; | |
1349 | int grmask; | |
1350 | int gr; | |
1351 | { | |
1352 | char bytes[3]; | |
1353 | bytes[0] = UNW_P9; | |
1354 | bytes[1] = (grmask & 0x0f); | |
1355 | bytes[2] = (gr & 0x7f); | |
1356 | (*f) (3, bytes, NULL); | |
1357 | } | |
1358 | ||
1359 | static void | |
1360 | output_P10_format (f, abi, context) | |
1361 | vbyte_func f; | |
1362 | int abi; | |
1363 | int context; | |
1364 | { | |
1365 | char bytes[3]; | |
1366 | bytes[0] = UNW_P10; | |
1367 | bytes[1] = (abi & 0xff); | |
1368 | bytes[2] = (context & 0xff); | |
1369 | (*f) (3, bytes, NULL); | |
1370 | } | |
1371 | ||
1372 | static void | |
1373 | output_B1_format (f, rtype, label) | |
1374 | vbyte_func f; | |
1375 | unw_record_type rtype; | |
1376 | unsigned long label; | |
1377 | { | |
1378 | char byte; | |
e0c9811a | 1379 | int r = 0; |
197865e8 | 1380 | if (label > 0x1f) |
800eeca4 JW |
1381 | { |
1382 | output_B4_format (f, rtype, label); | |
1383 | return; | |
1384 | } | |
e0c9811a JW |
1385 | if (rtype == copy_state) |
1386 | r = 1; | |
1387 | else if (rtype != label_state) | |
1388 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1389 | |
1390 | byte = (UNW_B1 | (r << 5) | (label & 0x1f)); | |
1391 | (*f) (1, &byte, NULL); | |
1392 | } | |
1393 | ||
1394 | static void | |
1395 | output_B2_format (f, ecount, t) | |
1396 | vbyte_func f; | |
1397 | unsigned long ecount; | |
1398 | unsigned long t; | |
1399 | { | |
1400 | char bytes[20]; | |
1401 | int count = 1; | |
1402 | if (ecount > 0x1f) | |
1403 | { | |
1404 | output_B3_format (f, ecount, t); | |
1405 | return; | |
1406 | } | |
1407 | bytes[0] = (UNW_B2 | (ecount & 0x1f)); | |
1408 | count += output_leb128 (bytes + 1, t, 0); | |
1409 | (*f) (count, bytes, NULL); | |
1410 | } | |
1411 | ||
1412 | static void | |
1413 | output_B3_format (f, ecount, t) | |
1414 | vbyte_func f; | |
1415 | unsigned long ecount; | |
1416 | unsigned long t; | |
1417 | { | |
1418 | char bytes[20]; | |
1419 | int count = 1; | |
1420 | if (ecount <= 0x1f) | |
1421 | { | |
1422 | output_B2_format (f, ecount, t); | |
1423 | return; | |
1424 | } | |
1425 | bytes[0] = UNW_B3; | |
1426 | count += output_leb128 (bytes + 1, t, 0); | |
1427 | count += output_leb128 (bytes + count, ecount, 0); | |
1428 | (*f) (count, bytes, NULL); | |
1429 | } | |
1430 | ||
1431 | static void | |
1432 | output_B4_format (f, rtype, label) | |
1433 | vbyte_func f; | |
1434 | unw_record_type rtype; | |
1435 | unsigned long label; | |
1436 | { | |
1437 | char bytes[20]; | |
e0c9811a | 1438 | int r = 0; |
800eeca4 | 1439 | int count = 1; |
197865e8 | 1440 | if (label <= 0x1f) |
800eeca4 JW |
1441 | { |
1442 | output_B1_format (f, rtype, label); | |
1443 | return; | |
1444 | } | |
197865e8 | 1445 | |
e0c9811a JW |
1446 | if (rtype == copy_state) |
1447 | r = 1; | |
1448 | else if (rtype != label_state) | |
1449 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1450 | |
1451 | bytes[0] = (UNW_B4 | (r << 3)); | |
1452 | count += output_leb128 (bytes + 1, label, 0); | |
1453 | (*f) (count, bytes, NULL); | |
1454 | } | |
1455 | ||
1456 | static char | |
e0c9811a | 1457 | format_ab_reg (ab, reg) |
542d6675 KH |
1458 | int ab; |
1459 | int reg; | |
800eeca4 JW |
1460 | { |
1461 | int ret; | |
e0c9811a | 1462 | ab = (ab & 3); |
800eeca4 | 1463 | reg = (reg & 0x1f); |
e0c9811a | 1464 | ret = (ab << 5) | reg; |
800eeca4 JW |
1465 | return ret; |
1466 | } | |
1467 | ||
1468 | static void | |
e0c9811a | 1469 | output_X1_format (f, rtype, ab, reg, t, w1) |
800eeca4 JW |
1470 | vbyte_func f; |
1471 | unw_record_type rtype; | |
e0c9811a | 1472 | int ab, reg; |
800eeca4 JW |
1473 | unsigned long t; |
1474 | unsigned long w1; | |
1475 | { | |
1476 | char bytes[20]; | |
e0c9811a | 1477 | int r = 0; |
800eeca4 JW |
1478 | int count = 2; |
1479 | bytes[0] = UNW_X1; | |
197865e8 | 1480 | |
e0c9811a JW |
1481 | if (rtype == spill_sprel) |
1482 | r = 1; | |
1483 | else if (rtype != spill_psprel) | |
1484 | as_bad ("Invalid record type for format X1"); | |
1485 | bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); | |
800eeca4 JW |
1486 | count += output_leb128 (bytes + 2, t, 0); |
1487 | count += output_leb128 (bytes + count, w1, 0); | |
1488 | (*f) (count, bytes, NULL); | |
1489 | } | |
1490 | ||
1491 | static void | |
e0c9811a | 1492 | output_X2_format (f, ab, reg, x, y, treg, t) |
800eeca4 | 1493 | vbyte_func f; |
e0c9811a | 1494 | int ab, reg; |
800eeca4 JW |
1495 | int x, y, treg; |
1496 | unsigned long t; | |
1497 | { | |
1498 | char bytes[20]; | |
800eeca4 JW |
1499 | int count = 3; |
1500 | bytes[0] = UNW_X2; | |
e0c9811a | 1501 | bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1502 | bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); |
1503 | count += output_leb128 (bytes + 3, t, 0); | |
1504 | (*f) (count, bytes, NULL); | |
1505 | } | |
1506 | ||
1507 | static void | |
e0c9811a | 1508 | output_X3_format (f, rtype, qp, ab, reg, t, w1) |
800eeca4 JW |
1509 | vbyte_func f; |
1510 | unw_record_type rtype; | |
1511 | int qp; | |
e0c9811a | 1512 | int ab, reg; |
800eeca4 JW |
1513 | unsigned long t; |
1514 | unsigned long w1; | |
1515 | { | |
1516 | char bytes[20]; | |
e0c9811a | 1517 | int r = 0; |
800eeca4 | 1518 | int count = 3; |
e0c9811a JW |
1519 | bytes[0] = UNW_X3; |
1520 | ||
1521 | if (rtype == spill_sprel_p) | |
1522 | r = 1; | |
1523 | else if (rtype != spill_psprel_p) | |
1524 | as_bad ("Invalid record type for format X3"); | |
800eeca4 | 1525 | bytes[1] = ((r << 7) | (qp & 0x3f)); |
e0c9811a | 1526 | bytes[2] = format_ab_reg (ab, reg); |
800eeca4 JW |
1527 | count += output_leb128 (bytes + 3, t, 0); |
1528 | count += output_leb128 (bytes + count, w1, 0); | |
1529 | (*f) (count, bytes, NULL); | |
1530 | } | |
1531 | ||
1532 | static void | |
e0c9811a | 1533 | output_X4_format (f, qp, ab, reg, x, y, treg, t) |
800eeca4 JW |
1534 | vbyte_func f; |
1535 | int qp; | |
e0c9811a | 1536 | int ab, reg; |
800eeca4 JW |
1537 | int x, y, treg; |
1538 | unsigned long t; | |
1539 | { | |
1540 | char bytes[20]; | |
800eeca4 | 1541 | int count = 4; |
e0c9811a | 1542 | bytes[0] = UNW_X4; |
800eeca4 | 1543 | bytes[1] = (qp & 0x3f); |
e0c9811a | 1544 | bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1545 | bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); |
1546 | count += output_leb128 (bytes + 4, t, 0); | |
1547 | (*f) (count, bytes, NULL); | |
1548 | } | |
1549 | ||
1550 | /* This function allocates a record list structure, and initializes fields. */ | |
542d6675 | 1551 | |
800eeca4 | 1552 | static unw_rec_list * |
197865e8 | 1553 | alloc_record (unw_record_type t) |
800eeca4 JW |
1554 | { |
1555 | unw_rec_list *ptr; | |
1556 | ptr = xmalloc (sizeof (*ptr)); | |
1557 | ptr->next = NULL; | |
1558 | ptr->slot_number = SLOT_NUM_NOT_SET; | |
1559 | ptr->r.type = t; | |
1560 | return ptr; | |
1561 | } | |
1562 | ||
800eeca4 | 1563 | /* This function frees an entire list of record structures. */ |
542d6675 | 1564 | |
800eeca4 JW |
1565 | void |
1566 | free_list_records (unw_rec_list *first) | |
1567 | { | |
1568 | unw_rec_list *ptr; | |
542d6675 | 1569 | for (ptr = first; ptr != NULL;) |
800eeca4 JW |
1570 | { |
1571 | unw_rec_list *tmp = ptr; | |
e0c9811a JW |
1572 | |
1573 | if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) | |
1574 | && tmp->r.record.r.mask.i) | |
1575 | free (tmp->r.record.r.mask.i); | |
1576 | ||
800eeca4 JW |
1577 | ptr = ptr->next; |
1578 | free (tmp); | |
1579 | } | |
1580 | } | |
1581 | ||
1582 | static unw_rec_list * | |
1583 | output_prologue () | |
1584 | { | |
1585 | unw_rec_list *ptr = alloc_record (prologue); | |
e0c9811a | 1586 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
800eeca4 JW |
1587 | return ptr; |
1588 | } | |
1589 | ||
1590 | static unw_rec_list * | |
1591 | output_prologue_gr (saved_mask, reg) | |
1592 | unsigned int saved_mask; | |
1593 | unsigned int reg; | |
1594 | { | |
1595 | unw_rec_list *ptr = alloc_record (prologue_gr); | |
e0c9811a JW |
1596 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
1597 | ptr->r.record.r.grmask = saved_mask; | |
800eeca4 JW |
1598 | ptr->r.record.r.grsave = reg; |
1599 | return ptr; | |
1600 | } | |
1601 | ||
1602 | static unw_rec_list * | |
1603 | output_body () | |
1604 | { | |
1605 | unw_rec_list *ptr = alloc_record (body); | |
1606 | return ptr; | |
1607 | } | |
1608 | ||
1609 | static unw_rec_list * | |
1610 | output_mem_stack_f (size) | |
1611 | unsigned int size; | |
1612 | { | |
1613 | unw_rec_list *ptr = alloc_record (mem_stack_f); | |
1614 | ptr->r.record.p.size = size; | |
1615 | return ptr; | |
1616 | } | |
1617 | ||
1618 | static unw_rec_list * | |
1619 | output_mem_stack_v () | |
1620 | { | |
1621 | unw_rec_list *ptr = alloc_record (mem_stack_v); | |
1622 | return ptr; | |
1623 | } | |
1624 | ||
1625 | static unw_rec_list * | |
1626 | output_psp_gr (gr) | |
1627 | unsigned int gr; | |
1628 | { | |
1629 | unw_rec_list *ptr = alloc_record (psp_gr); | |
1630 | ptr->r.record.p.gr = gr; | |
1631 | return ptr; | |
1632 | } | |
1633 | ||
1634 | static unw_rec_list * | |
1635 | output_psp_sprel (offset) | |
1636 | unsigned int offset; | |
1637 | { | |
1638 | unw_rec_list *ptr = alloc_record (psp_sprel); | |
542d6675 | 1639 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1640 | return ptr; |
1641 | } | |
1642 | ||
1643 | static unw_rec_list * | |
1644 | output_rp_when () | |
1645 | { | |
1646 | unw_rec_list *ptr = alloc_record (rp_when); | |
1647 | return ptr; | |
1648 | } | |
1649 | ||
1650 | static unw_rec_list * | |
1651 | output_rp_gr (gr) | |
1652 | unsigned int gr; | |
1653 | { | |
1654 | unw_rec_list *ptr = alloc_record (rp_gr); | |
1655 | ptr->r.record.p.gr = gr; | |
1656 | return ptr; | |
1657 | } | |
1658 | ||
1659 | static unw_rec_list * | |
1660 | output_rp_br (br) | |
1661 | unsigned int br; | |
1662 | { | |
1663 | unw_rec_list *ptr = alloc_record (rp_br); | |
1664 | ptr->r.record.p.br = br; | |
1665 | return ptr; | |
1666 | } | |
1667 | ||
1668 | static unw_rec_list * | |
1669 | output_rp_psprel (offset) | |
1670 | unsigned int offset; | |
1671 | { | |
1672 | unw_rec_list *ptr = alloc_record (rp_psprel); | |
542d6675 | 1673 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1674 | return ptr; |
1675 | } | |
1676 | ||
1677 | static unw_rec_list * | |
1678 | output_rp_sprel (offset) | |
1679 | unsigned int offset; | |
1680 | { | |
1681 | unw_rec_list *ptr = alloc_record (rp_sprel); | |
542d6675 | 1682 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1683 | return ptr; |
1684 | } | |
1685 | ||
1686 | static unw_rec_list * | |
1687 | output_pfs_when () | |
1688 | { | |
1689 | unw_rec_list *ptr = alloc_record (pfs_when); | |
1690 | return ptr; | |
1691 | } | |
1692 | ||
1693 | static unw_rec_list * | |
1694 | output_pfs_gr (gr) | |
1695 | unsigned int gr; | |
1696 | { | |
1697 | unw_rec_list *ptr = alloc_record (pfs_gr); | |
1698 | ptr->r.record.p.gr = gr; | |
1699 | return ptr; | |
1700 | } | |
1701 | ||
1702 | static unw_rec_list * | |
1703 | output_pfs_psprel (offset) | |
1704 | unsigned int offset; | |
1705 | { | |
1706 | unw_rec_list *ptr = alloc_record (pfs_psprel); | |
542d6675 | 1707 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1708 | return ptr; |
1709 | } | |
1710 | ||
1711 | static unw_rec_list * | |
1712 | output_pfs_sprel (offset) | |
1713 | unsigned int offset; | |
1714 | { | |
1715 | unw_rec_list *ptr = alloc_record (pfs_sprel); | |
542d6675 | 1716 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1717 | return ptr; |
1718 | } | |
1719 | ||
1720 | static unw_rec_list * | |
1721 | output_preds_when () | |
1722 | { | |
1723 | unw_rec_list *ptr = alloc_record (preds_when); | |
1724 | return ptr; | |
1725 | } | |
1726 | ||
1727 | static unw_rec_list * | |
1728 | output_preds_gr (gr) | |
1729 | unsigned int gr; | |
1730 | { | |
1731 | unw_rec_list *ptr = alloc_record (preds_gr); | |
1732 | ptr->r.record.p.gr = gr; | |
1733 | return ptr; | |
1734 | } | |
1735 | ||
1736 | static unw_rec_list * | |
1737 | output_preds_psprel (offset) | |
1738 | unsigned int offset; | |
1739 | { | |
1740 | unw_rec_list *ptr = alloc_record (preds_psprel); | |
542d6675 | 1741 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1742 | return ptr; |
1743 | } | |
1744 | ||
1745 | static unw_rec_list * | |
1746 | output_preds_sprel (offset) | |
1747 | unsigned int offset; | |
1748 | { | |
1749 | unw_rec_list *ptr = alloc_record (preds_sprel); | |
542d6675 | 1750 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1751 | return ptr; |
1752 | } | |
1753 | ||
1754 | static unw_rec_list * | |
1755 | output_fr_mem (mask) | |
1756 | unsigned int mask; | |
1757 | { | |
1758 | unw_rec_list *ptr = alloc_record (fr_mem); | |
1759 | ptr->r.record.p.rmask = mask; | |
1760 | return ptr; | |
1761 | } | |
1762 | ||
1763 | static unw_rec_list * | |
1764 | output_frgr_mem (gr_mask, fr_mask) | |
1765 | unsigned int gr_mask; | |
1766 | unsigned int fr_mask; | |
1767 | { | |
1768 | unw_rec_list *ptr = alloc_record (frgr_mem); | |
1769 | ptr->r.record.p.grmask = gr_mask; | |
1770 | ptr->r.record.p.frmask = fr_mask; | |
1771 | return ptr; | |
1772 | } | |
1773 | ||
1774 | static unw_rec_list * | |
1775 | output_gr_gr (mask, reg) | |
1776 | unsigned int mask; | |
1777 | unsigned int reg; | |
1778 | { | |
1779 | unw_rec_list *ptr = alloc_record (gr_gr); | |
1780 | ptr->r.record.p.grmask = mask; | |
1781 | ptr->r.record.p.gr = reg; | |
1782 | return ptr; | |
1783 | } | |
1784 | ||
1785 | static unw_rec_list * | |
1786 | output_gr_mem (mask) | |
1787 | unsigned int mask; | |
1788 | { | |
1789 | unw_rec_list *ptr = alloc_record (gr_mem); | |
1790 | ptr->r.record.p.rmask = mask; | |
1791 | return ptr; | |
1792 | } | |
1793 | ||
1794 | static unw_rec_list * | |
1795 | output_br_mem (unsigned int mask) | |
1796 | { | |
1797 | unw_rec_list *ptr = alloc_record (br_mem); | |
1798 | ptr->r.record.p.brmask = mask; | |
1799 | return ptr; | |
1800 | } | |
1801 | ||
1802 | static unw_rec_list * | |
1803 | output_br_gr (save_mask, reg) | |
1804 | unsigned int save_mask; | |
1805 | unsigned int reg; | |
1806 | { | |
1807 | unw_rec_list *ptr = alloc_record (br_gr); | |
1808 | ptr->r.record.p.brmask = save_mask; | |
1809 | ptr->r.record.p.gr = reg; | |
1810 | return ptr; | |
1811 | } | |
1812 | ||
1813 | static unw_rec_list * | |
1814 | output_spill_base (offset) | |
1815 | unsigned int offset; | |
1816 | { | |
1817 | unw_rec_list *ptr = alloc_record (spill_base); | |
542d6675 | 1818 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1819 | return ptr; |
1820 | } | |
1821 | ||
1822 | static unw_rec_list * | |
1823 | output_unat_when () | |
1824 | { | |
1825 | unw_rec_list *ptr = alloc_record (unat_when); | |
1826 | return ptr; | |
1827 | } | |
1828 | ||
1829 | static unw_rec_list * | |
1830 | output_unat_gr (gr) | |
1831 | unsigned int gr; | |
1832 | { | |
1833 | unw_rec_list *ptr = alloc_record (unat_gr); | |
1834 | ptr->r.record.p.gr = gr; | |
1835 | return ptr; | |
1836 | } | |
1837 | ||
1838 | static unw_rec_list * | |
1839 | output_unat_psprel (offset) | |
1840 | unsigned int offset; | |
1841 | { | |
1842 | unw_rec_list *ptr = alloc_record (unat_psprel); | |
542d6675 | 1843 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1844 | return ptr; |
1845 | } | |
1846 | ||
1847 | static unw_rec_list * | |
1848 | output_unat_sprel (offset) | |
1849 | unsigned int offset; | |
1850 | { | |
1851 | unw_rec_list *ptr = alloc_record (unat_sprel); | |
542d6675 | 1852 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1853 | return ptr; |
1854 | } | |
1855 | ||
1856 | static unw_rec_list * | |
1857 | output_lc_when () | |
1858 | { | |
1859 | unw_rec_list *ptr = alloc_record (lc_when); | |
1860 | return ptr; | |
1861 | } | |
1862 | ||
1863 | static unw_rec_list * | |
1864 | output_lc_gr (gr) | |
1865 | unsigned int gr; | |
1866 | { | |
1867 | unw_rec_list *ptr = alloc_record (lc_gr); | |
1868 | ptr->r.record.p.gr = gr; | |
1869 | return ptr; | |
1870 | } | |
1871 | ||
1872 | static unw_rec_list * | |
1873 | output_lc_psprel (offset) | |
1874 | unsigned int offset; | |
1875 | { | |
1876 | unw_rec_list *ptr = alloc_record (lc_psprel); | |
542d6675 | 1877 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1878 | return ptr; |
1879 | } | |
1880 | ||
1881 | static unw_rec_list * | |
1882 | output_lc_sprel (offset) | |
1883 | unsigned int offset; | |
1884 | { | |
1885 | unw_rec_list *ptr = alloc_record (lc_sprel); | |
542d6675 | 1886 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1887 | return ptr; |
1888 | } | |
1889 | ||
1890 | static unw_rec_list * | |
1891 | output_fpsr_when () | |
1892 | { | |
1893 | unw_rec_list *ptr = alloc_record (fpsr_when); | |
1894 | return ptr; | |
1895 | } | |
1896 | ||
1897 | static unw_rec_list * | |
1898 | output_fpsr_gr (gr) | |
1899 | unsigned int gr; | |
1900 | { | |
1901 | unw_rec_list *ptr = alloc_record (fpsr_gr); | |
1902 | ptr->r.record.p.gr = gr; | |
1903 | return ptr; | |
1904 | } | |
1905 | ||
1906 | static unw_rec_list * | |
1907 | output_fpsr_psprel (offset) | |
1908 | unsigned int offset; | |
1909 | { | |
1910 | unw_rec_list *ptr = alloc_record (fpsr_psprel); | |
542d6675 | 1911 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1912 | return ptr; |
1913 | } | |
1914 | ||
1915 | static unw_rec_list * | |
1916 | output_fpsr_sprel (offset) | |
1917 | unsigned int offset; | |
1918 | { | |
1919 | unw_rec_list *ptr = alloc_record (fpsr_sprel); | |
542d6675 | 1920 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1921 | return ptr; |
1922 | } | |
1923 | ||
1924 | static unw_rec_list * | |
1925 | output_priunat_when_gr () | |
1926 | { | |
1927 | unw_rec_list *ptr = alloc_record (priunat_when_gr); | |
1928 | return ptr; | |
1929 | } | |
1930 | ||
1931 | static unw_rec_list * | |
1932 | output_priunat_when_mem () | |
1933 | { | |
1934 | unw_rec_list *ptr = alloc_record (priunat_when_mem); | |
1935 | return ptr; | |
1936 | } | |
1937 | ||
1938 | static unw_rec_list * | |
1939 | output_priunat_gr (gr) | |
1940 | unsigned int gr; | |
1941 | { | |
1942 | unw_rec_list *ptr = alloc_record (priunat_gr); | |
1943 | ptr->r.record.p.gr = gr; | |
1944 | return ptr; | |
1945 | } | |
1946 | ||
1947 | static unw_rec_list * | |
1948 | output_priunat_psprel (offset) | |
1949 | unsigned int offset; | |
1950 | { | |
1951 | unw_rec_list *ptr = alloc_record (priunat_psprel); | |
542d6675 | 1952 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1953 | return ptr; |
1954 | } | |
1955 | ||
1956 | static unw_rec_list * | |
1957 | output_priunat_sprel (offset) | |
1958 | unsigned int offset; | |
1959 | { | |
1960 | unw_rec_list *ptr = alloc_record (priunat_sprel); | |
542d6675 | 1961 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1962 | return ptr; |
1963 | } | |
1964 | ||
1965 | static unw_rec_list * | |
1966 | output_bsp_when () | |
1967 | { | |
1968 | unw_rec_list *ptr = alloc_record (bsp_when); | |
1969 | return ptr; | |
1970 | } | |
1971 | ||
1972 | static unw_rec_list * | |
1973 | output_bsp_gr (gr) | |
1974 | unsigned int gr; | |
1975 | { | |
1976 | unw_rec_list *ptr = alloc_record (bsp_gr); | |
1977 | ptr->r.record.p.gr = gr; | |
1978 | return ptr; | |
1979 | } | |
1980 | ||
1981 | static unw_rec_list * | |
1982 | output_bsp_psprel (offset) | |
1983 | unsigned int offset; | |
1984 | { | |
1985 | unw_rec_list *ptr = alloc_record (bsp_psprel); | |
542d6675 | 1986 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1987 | return ptr; |
1988 | } | |
1989 | ||
1990 | static unw_rec_list * | |
1991 | output_bsp_sprel (offset) | |
1992 | unsigned int offset; | |
1993 | { | |
1994 | unw_rec_list *ptr = alloc_record (bsp_sprel); | |
542d6675 | 1995 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1996 | return ptr; |
1997 | } | |
1998 | ||
1999 | static unw_rec_list * | |
2000 | output_bspstore_when () | |
2001 | { | |
2002 | unw_rec_list *ptr = alloc_record (bspstore_when); | |
2003 | return ptr; | |
2004 | } | |
2005 | ||
2006 | static unw_rec_list * | |
2007 | output_bspstore_gr (gr) | |
2008 | unsigned int gr; | |
2009 | { | |
2010 | unw_rec_list *ptr = alloc_record (bspstore_gr); | |
2011 | ptr->r.record.p.gr = gr; | |
2012 | return ptr; | |
2013 | } | |
2014 | ||
2015 | static unw_rec_list * | |
2016 | output_bspstore_psprel (offset) | |
2017 | unsigned int offset; | |
2018 | { | |
2019 | unw_rec_list *ptr = alloc_record (bspstore_psprel); | |
542d6675 | 2020 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2021 | return ptr; |
2022 | } | |
2023 | ||
2024 | static unw_rec_list * | |
2025 | output_bspstore_sprel (offset) | |
2026 | unsigned int offset; | |
2027 | { | |
2028 | unw_rec_list *ptr = alloc_record (bspstore_sprel); | |
542d6675 | 2029 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2030 | return ptr; |
2031 | } | |
2032 | ||
2033 | static unw_rec_list * | |
2034 | output_rnat_when () | |
2035 | { | |
2036 | unw_rec_list *ptr = alloc_record (rnat_when); | |
2037 | return ptr; | |
2038 | } | |
2039 | ||
2040 | static unw_rec_list * | |
2041 | output_rnat_gr (gr) | |
2042 | unsigned int gr; | |
2043 | { | |
2044 | unw_rec_list *ptr = alloc_record (rnat_gr); | |
2045 | ptr->r.record.p.gr = gr; | |
2046 | return ptr; | |
2047 | } | |
2048 | ||
2049 | static unw_rec_list * | |
2050 | output_rnat_psprel (offset) | |
2051 | unsigned int offset; | |
2052 | { | |
2053 | unw_rec_list *ptr = alloc_record (rnat_psprel); | |
542d6675 | 2054 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2055 | return ptr; |
2056 | } | |
2057 | ||
2058 | static unw_rec_list * | |
2059 | output_rnat_sprel (offset) | |
2060 | unsigned int offset; | |
2061 | { | |
2062 | unw_rec_list *ptr = alloc_record (rnat_sprel); | |
542d6675 | 2063 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2064 | return ptr; |
2065 | } | |
2066 | ||
2067 | static unw_rec_list * | |
e0c9811a JW |
2068 | output_unwabi (abi, context) |
2069 | unsigned long abi; | |
2070 | unsigned long context; | |
800eeca4 | 2071 | { |
e0c9811a JW |
2072 | unw_rec_list *ptr = alloc_record (unwabi); |
2073 | ptr->r.record.p.abi = abi; | |
2074 | ptr->r.record.p.context = context; | |
800eeca4 JW |
2075 | return ptr; |
2076 | } | |
2077 | ||
2078 | static unw_rec_list * | |
e0c9811a | 2079 | output_epilogue (unsigned long ecount) |
800eeca4 | 2080 | { |
e0c9811a JW |
2081 | unw_rec_list *ptr = alloc_record (epilogue); |
2082 | ptr->r.record.b.ecount = ecount; | |
800eeca4 JW |
2083 | return ptr; |
2084 | } | |
2085 | ||
2086 | static unw_rec_list * | |
e0c9811a | 2087 | output_label_state (unsigned long label) |
800eeca4 | 2088 | { |
e0c9811a JW |
2089 | unw_rec_list *ptr = alloc_record (label_state); |
2090 | ptr->r.record.b.label = label; | |
800eeca4 JW |
2091 | return ptr; |
2092 | } | |
2093 | ||
2094 | static unw_rec_list * | |
e0c9811a JW |
2095 | output_copy_state (unsigned long label) |
2096 | { | |
2097 | unw_rec_list *ptr = alloc_record (copy_state); | |
2098 | ptr->r.record.b.label = label; | |
2099 | return ptr; | |
2100 | } | |
2101 | ||
2102 | static unw_rec_list * | |
2103 | output_spill_psprel (ab, reg, offset) | |
2104 | unsigned int ab; | |
800eeca4 JW |
2105 | unsigned int reg; |
2106 | unsigned int offset; | |
2107 | { | |
2108 | unw_rec_list *ptr = alloc_record (spill_psprel); | |
e0c9811a | 2109 | ptr->r.record.x.ab = ab; |
800eeca4 | 2110 | ptr->r.record.x.reg = reg; |
542d6675 | 2111 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2112 | return ptr; |
2113 | } | |
2114 | ||
2115 | static unw_rec_list * | |
e0c9811a JW |
2116 | output_spill_sprel (ab, reg, offset) |
2117 | unsigned int ab; | |
800eeca4 JW |
2118 | unsigned int reg; |
2119 | unsigned int offset; | |
2120 | { | |
2121 | unw_rec_list *ptr = alloc_record (spill_sprel); | |
e0c9811a | 2122 | ptr->r.record.x.ab = ab; |
800eeca4 | 2123 | ptr->r.record.x.reg = reg; |
542d6675 | 2124 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2125 | return ptr; |
2126 | } | |
2127 | ||
2128 | static unw_rec_list * | |
e0c9811a JW |
2129 | output_spill_psprel_p (ab, reg, offset, predicate) |
2130 | unsigned int ab; | |
800eeca4 JW |
2131 | unsigned int reg; |
2132 | unsigned int offset; | |
2133 | unsigned int predicate; | |
2134 | { | |
2135 | unw_rec_list *ptr = alloc_record (spill_psprel_p); | |
e0c9811a | 2136 | ptr->r.record.x.ab = ab; |
800eeca4 | 2137 | ptr->r.record.x.reg = reg; |
542d6675 | 2138 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2139 | ptr->r.record.x.qp = predicate; |
2140 | return ptr; | |
2141 | } | |
2142 | ||
2143 | static unw_rec_list * | |
e0c9811a JW |
2144 | output_spill_sprel_p (ab, reg, offset, predicate) |
2145 | unsigned int ab; | |
800eeca4 JW |
2146 | unsigned int reg; |
2147 | unsigned int offset; | |
2148 | unsigned int predicate; | |
2149 | { | |
2150 | unw_rec_list *ptr = alloc_record (spill_sprel_p); | |
e0c9811a | 2151 | ptr->r.record.x.ab = ab; |
800eeca4 | 2152 | ptr->r.record.x.reg = reg; |
542d6675 | 2153 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2154 | ptr->r.record.x.qp = predicate; |
2155 | return ptr; | |
2156 | } | |
2157 | ||
2158 | static unw_rec_list * | |
e0c9811a JW |
2159 | output_spill_reg (ab, reg, targ_reg, xy) |
2160 | unsigned int ab; | |
800eeca4 JW |
2161 | unsigned int reg; |
2162 | unsigned int targ_reg; | |
2163 | unsigned int xy; | |
2164 | { | |
2165 | unw_rec_list *ptr = alloc_record (spill_reg); | |
e0c9811a | 2166 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2167 | ptr->r.record.x.reg = reg; |
2168 | ptr->r.record.x.treg = targ_reg; | |
2169 | ptr->r.record.x.xy = xy; | |
2170 | return ptr; | |
2171 | } | |
2172 | ||
2173 | static unw_rec_list * | |
e0c9811a JW |
2174 | output_spill_reg_p (ab, reg, targ_reg, xy, predicate) |
2175 | unsigned int ab; | |
800eeca4 JW |
2176 | unsigned int reg; |
2177 | unsigned int targ_reg; | |
2178 | unsigned int xy; | |
2179 | unsigned int predicate; | |
2180 | { | |
2181 | unw_rec_list *ptr = alloc_record (spill_reg_p); | |
e0c9811a | 2182 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2183 | ptr->r.record.x.reg = reg; |
2184 | ptr->r.record.x.treg = targ_reg; | |
2185 | ptr->r.record.x.xy = xy; | |
2186 | ptr->r.record.x.qp = predicate; | |
2187 | return ptr; | |
2188 | } | |
2189 | ||
197865e8 | 2190 | /* Given a unw_rec_list process the correct format with the |
800eeca4 | 2191 | specified function. */ |
542d6675 | 2192 | |
800eeca4 JW |
2193 | static void |
2194 | process_one_record (ptr, f) | |
2195 | unw_rec_list *ptr; | |
2196 | vbyte_func f; | |
2197 | { | |
e0c9811a JW |
2198 | unsigned long fr_mask, gr_mask; |
2199 | ||
197865e8 | 2200 | switch (ptr->r.type) |
800eeca4 | 2201 | { |
542d6675 KH |
2202 | case gr_mem: |
2203 | case fr_mem: | |
2204 | case br_mem: | |
2205 | case frgr_mem: | |
2206 | /* These are taken care of by prologue/prologue_gr. */ | |
2207 | break; | |
e0c9811a | 2208 | |
542d6675 KH |
2209 | case prologue_gr: |
2210 | case prologue: | |
2211 | if (ptr->r.type == prologue_gr) | |
2212 | output_R2_format (f, ptr->r.record.r.grmask, | |
2213 | ptr->r.record.r.grsave, ptr->r.record.r.rlen); | |
2214 | else | |
800eeca4 | 2215 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
542d6675 KH |
2216 | |
2217 | /* Output descriptor(s) for union of register spills (if any). */ | |
2218 | gr_mask = ptr->r.record.r.mask.gr_mem; | |
2219 | fr_mask = ptr->r.record.r.mask.fr_mem; | |
2220 | if (fr_mask) | |
2221 | { | |
2222 | if ((fr_mask & ~0xfUL) == 0) | |
2223 | output_P6_format (f, fr_mem, fr_mask); | |
2224 | else | |
2225 | { | |
2226 | output_P5_format (f, gr_mask, fr_mask); | |
2227 | gr_mask = 0; | |
2228 | } | |
2229 | } | |
2230 | if (gr_mask) | |
2231 | output_P6_format (f, gr_mem, gr_mask); | |
2232 | if (ptr->r.record.r.mask.br_mem) | |
2233 | output_P1_format (f, ptr->r.record.r.mask.br_mem); | |
2234 | ||
2235 | /* output imask descriptor if necessary: */ | |
2236 | if (ptr->r.record.r.mask.i) | |
2237 | output_P4_format (f, ptr->r.record.r.mask.i, | |
2238 | ptr->r.record.r.imask_size); | |
2239 | break; | |
2240 | ||
2241 | case body: | |
2242 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); | |
2243 | break; | |
2244 | case mem_stack_f: | |
2245 | case mem_stack_v: | |
2246 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, | |
2247 | ptr->r.record.p.size); | |
2248 | break; | |
2249 | case psp_gr: | |
2250 | case rp_gr: | |
2251 | case pfs_gr: | |
2252 | case preds_gr: | |
2253 | case unat_gr: | |
2254 | case lc_gr: | |
2255 | case fpsr_gr: | |
2256 | case priunat_gr: | |
2257 | case bsp_gr: | |
2258 | case bspstore_gr: | |
2259 | case rnat_gr: | |
2260 | output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); | |
2261 | break; | |
2262 | case rp_br: | |
2263 | output_P3_format (f, rp_br, ptr->r.record.p.br); | |
2264 | break; | |
2265 | case psp_sprel: | |
2266 | output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); | |
2267 | break; | |
2268 | case rp_when: | |
2269 | case pfs_when: | |
2270 | case preds_when: | |
2271 | case unat_when: | |
2272 | case lc_when: | |
2273 | case fpsr_when: | |
2274 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); | |
2275 | break; | |
2276 | case rp_psprel: | |
2277 | case pfs_psprel: | |
2278 | case preds_psprel: | |
2279 | case unat_psprel: | |
2280 | case lc_psprel: | |
2281 | case fpsr_psprel: | |
2282 | case spill_base: | |
2283 | output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); | |
2284 | break; | |
2285 | case rp_sprel: | |
2286 | case pfs_sprel: | |
2287 | case preds_sprel: | |
2288 | case unat_sprel: | |
2289 | case lc_sprel: | |
2290 | case fpsr_sprel: | |
2291 | case priunat_sprel: | |
2292 | case bsp_sprel: | |
2293 | case bspstore_sprel: | |
2294 | case rnat_sprel: | |
2295 | output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); | |
2296 | break; | |
2297 | case gr_gr: | |
2298 | output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); | |
2299 | break; | |
2300 | case br_gr: | |
2301 | output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); | |
2302 | break; | |
2303 | case spill_mask: | |
2304 | as_bad ("spill_mask record unimplemented."); | |
2305 | break; | |
2306 | case priunat_when_gr: | |
2307 | case priunat_when_mem: | |
2308 | case bsp_when: | |
2309 | case bspstore_when: | |
2310 | case rnat_when: | |
2311 | output_P8_format (f, ptr->r.type, ptr->r.record.p.t); | |
2312 | break; | |
2313 | case priunat_psprel: | |
2314 | case bsp_psprel: | |
2315 | case bspstore_psprel: | |
2316 | case rnat_psprel: | |
2317 | output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); | |
2318 | break; | |
2319 | case unwabi: | |
2320 | output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); | |
2321 | break; | |
2322 | case epilogue: | |
2323 | output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); | |
2324 | break; | |
2325 | case label_state: | |
2326 | case copy_state: | |
2327 | output_B4_format (f, ptr->r.type, ptr->r.record.b.label); | |
2328 | break; | |
2329 | case spill_psprel: | |
2330 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2331 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2332 | ptr->r.record.x.pspoff); | |
2333 | break; | |
2334 | case spill_sprel: | |
2335 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2336 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2337 | ptr->r.record.x.spoff); | |
2338 | break; | |
2339 | case spill_reg: | |
2340 | output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2341 | ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, | |
2342 | ptr->r.record.x.treg, ptr->r.record.x.t); | |
2343 | break; | |
2344 | case spill_psprel_p: | |
2345 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2346 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2347 | ptr->r.record.x.t, ptr->r.record.x.pspoff); | |
2348 | break; | |
2349 | case spill_sprel_p: | |
2350 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2351 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2352 | ptr->r.record.x.t, ptr->r.record.x.spoff); | |
2353 | break; | |
2354 | case spill_reg_p: | |
2355 | output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, | |
2356 | ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, | |
2357 | ptr->r.record.x.xy, ptr->r.record.x.treg, | |
2358 | ptr->r.record.x.t); | |
2359 | break; | |
2360 | default: | |
2361 | as_bad ("record_type_not_valid"); | |
2362 | break; | |
800eeca4 JW |
2363 | } |
2364 | } | |
2365 | ||
197865e8 | 2366 | /* Given a unw_rec_list list, process all the records with |
800eeca4 JW |
2367 | the specified function. */ |
2368 | static void | |
2369 | process_unw_records (list, f) | |
2370 | unw_rec_list *list; | |
2371 | vbyte_func f; | |
2372 | { | |
2373 | unw_rec_list *ptr; | |
2374 | for (ptr = list; ptr; ptr = ptr->next) | |
2375 | process_one_record (ptr, f); | |
2376 | } | |
2377 | ||
2378 | /* Determine the size of a record list in bytes. */ | |
2379 | static int | |
2380 | calc_record_size (list) | |
2381 | unw_rec_list *list; | |
2382 | { | |
2383 | vbyte_count = 0; | |
2384 | process_unw_records (list, count_output); | |
2385 | return vbyte_count; | |
2386 | } | |
2387 | ||
e0c9811a JW |
2388 | /* Update IMASK bitmask to reflect the fact that one or more registers |
2389 | of type TYPE are saved starting at instruction with index T. If N | |
2390 | bits are set in REGMASK, it is assumed that instructions T through | |
2391 | T+N-1 save these registers. | |
2392 | ||
2393 | TYPE values: | |
2394 | 0: no save | |
2395 | 1: instruction saves next fp reg | |
2396 | 2: instruction saves next general reg | |
2397 | 3: instruction saves next branch reg */ | |
2398 | static void | |
2399 | set_imask (region, regmask, t, type) | |
2400 | unw_rec_list *region; | |
2401 | unsigned long regmask; | |
2402 | unsigned long t; | |
2403 | unsigned int type; | |
2404 | { | |
2405 | unsigned char *imask; | |
2406 | unsigned long imask_size; | |
2407 | unsigned int i; | |
2408 | int pos; | |
2409 | ||
2410 | imask = region->r.record.r.mask.i; | |
2411 | imask_size = region->r.record.r.imask_size; | |
2412 | if (!imask) | |
2413 | { | |
542d6675 | 2414 | imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; |
e0c9811a JW |
2415 | imask = xmalloc (imask_size); |
2416 | memset (imask, 0, imask_size); | |
2417 | ||
2418 | region->r.record.r.imask_size = imask_size; | |
2419 | region->r.record.r.mask.i = imask; | |
2420 | } | |
2421 | ||
542d6675 KH |
2422 | i = (t / 4) + 1; |
2423 | pos = 2 * (3 - t % 4); | |
e0c9811a JW |
2424 | while (regmask) |
2425 | { | |
2426 | if (i >= imask_size) | |
2427 | { | |
2428 | as_bad ("Ignoring attempt to spill beyond end of region"); | |
2429 | return; | |
2430 | } | |
2431 | ||
2432 | imask[i] |= (type & 0x3) << pos; | |
197865e8 | 2433 | |
e0c9811a JW |
2434 | regmask &= (regmask - 1); |
2435 | pos -= 2; | |
2436 | if (pos < 0) | |
2437 | { | |
2438 | pos = 0; | |
2439 | ++i; | |
2440 | } | |
2441 | } | |
2442 | } | |
2443 | ||
2444 | static int | |
2445 | count_bits (unsigned long mask) | |
2446 | { | |
2447 | int n = 0; | |
2448 | ||
2449 | while (mask) | |
2450 | { | |
2451 | mask &= mask - 1; | |
2452 | ++n; | |
2453 | } | |
2454 | return n; | |
2455 | } | |
2456 | ||
f5a30c2e JW |
2457 | /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. |
2458 | SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag | |
2459 | containing FIRST_ADDR. */ | |
2460 | ||
e0c9811a | 2461 | unsigned long |
f5a30c2e JW |
2462 | slot_index (slot_addr, slot_frag, first_addr, first_frag) |
2463 | unsigned long slot_addr; | |
2464 | fragS *slot_frag; | |
2465 | unsigned long first_addr; | |
2466 | fragS *first_frag; | |
e0c9811a | 2467 | { |
f5a30c2e JW |
2468 | unsigned long index = 0; |
2469 | ||
2470 | /* First time we are called, the initial address and frag are invalid. */ | |
2471 | if (first_addr == 0) | |
2472 | return 0; | |
2473 | ||
2474 | /* If the two addresses are in different frags, then we need to add in | |
2475 | the remaining size of this frag, and then the entire size of intermediate | |
2476 | frags. */ | |
2477 | while (slot_frag != first_frag) | |
2478 | { | |
2479 | unsigned long start_addr = (unsigned long) &first_frag->fr_literal; | |
2480 | ||
2481 | /* Add in the full size of the frag converted to instruction slots. */ | |
2482 | index += 3 * (first_frag->fr_fix >> 4); | |
2483 | /* Subtract away the initial part before first_addr. */ | |
2484 | index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) | |
2485 | + ((first_addr & 0x3) - (start_addr & 0x3))); | |
e0c9811a | 2486 | |
f5a30c2e JW |
2487 | /* Move to the beginning of the next frag. */ |
2488 | first_frag = first_frag->fr_next; | |
2489 | first_addr = (unsigned long) &first_frag->fr_literal; | |
2490 | } | |
2491 | ||
2492 | /* Add in the used part of the last frag. */ | |
2493 | index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) | |
2494 | + ((slot_addr & 0x3) - (first_addr & 0x3))); | |
2495 | return index; | |
2496 | } | |
4a1805b1 | 2497 | |
800eeca4 JW |
2498 | /* Given a complete record list, process any records which have |
2499 | unresolved fields, (ie length counts for a prologue). After | |
197865e8 | 2500 | this has been run, all neccessary information should be available |
800eeca4 | 2501 | within each record to generate an image. */ |
542d6675 | 2502 | |
800eeca4 JW |
2503 | static void |
2504 | fixup_unw_records (list) | |
2505 | unw_rec_list *list; | |
2506 | { | |
e0c9811a JW |
2507 | unw_rec_list *ptr, *region = 0; |
2508 | unsigned long first_addr = 0, rlen = 0, t; | |
f5a30c2e | 2509 | fragS *first_frag = 0; |
e0c9811a | 2510 | |
800eeca4 JW |
2511 | for (ptr = list; ptr; ptr = ptr->next) |
2512 | { | |
2513 | if (ptr->slot_number == SLOT_NUM_NOT_SET) | |
542d6675 | 2514 | as_bad (" Insn slot not set in unwind record."); |
f5a30c2e JW |
2515 | t = slot_index (ptr->slot_number, ptr->slot_frag, |
2516 | first_addr, first_frag); | |
800eeca4 JW |
2517 | switch (ptr->r.type) |
2518 | { | |
542d6675 KH |
2519 | case prologue: |
2520 | case prologue_gr: | |
2521 | case body: | |
2522 | { | |
2523 | unw_rec_list *last; | |
2524 | int size, dir_len = 0; | |
2525 | unsigned long last_addr; | |
f5a30c2e | 2526 | fragS *last_frag; |
542d6675 KH |
2527 | |
2528 | first_addr = ptr->slot_number; | |
f5a30c2e | 2529 | first_frag = ptr->slot_frag; |
542d6675 KH |
2530 | ptr->slot_number = 0; |
2531 | /* Find either the next body/prologue start, or the end of | |
2532 | the list, and determine the size of the region. */ | |
2533 | last_addr = unwind.next_slot_number; | |
f5a30c2e | 2534 | last_frag = unwind.next_slot_frag; |
542d6675 KH |
2535 | for (last = ptr->next; last != NULL; last = last->next) |
2536 | if (last->r.type == prologue || last->r.type == prologue_gr | |
2537 | || last->r.type == body) | |
2538 | { | |
2539 | last_addr = last->slot_number; | |
f5a30c2e | 2540 | last_frag = last->slot_frag; |
542d6675 KH |
2541 | break; |
2542 | } | |
2543 | else if (!last->next) | |
2544 | { | |
2545 | /* In the absence of an explicit .body directive, | |
2546 | the prologue ends after the last instruction | |
2547 | covered by an unwind directive. */ | |
2548 | if (ptr->r.type != body) | |
2549 | { | |
2550 | last_addr = last->slot_number; | |
f5a30c2e | 2551 | last_frag = last->slot_frag; |
542d6675 KH |
2552 | switch (last->r.type) |
2553 | { | |
2554 | case frgr_mem: | |
2555 | dir_len = (count_bits (last->r.record.p.frmask) | |
2556 | + count_bits (last->r.record.p.grmask)); | |
2557 | break; | |
2558 | case fr_mem: | |
2559 | case gr_mem: | |
2560 | dir_len += count_bits (last->r.record.p.rmask); | |
2561 | break; | |
2562 | case br_mem: | |
2563 | case br_gr: | |
2564 | dir_len += count_bits (last->r.record.p.brmask); | |
2565 | break; | |
2566 | case gr_gr: | |
2567 | dir_len += count_bits (last->r.record.p.grmask); | |
2568 | break; | |
2569 | default: | |
2570 | dir_len = 1; | |
2571 | break; | |
2572 | } | |
2573 | } | |
2574 | break; | |
2575 | } | |
f5a30c2e JW |
2576 | size = (slot_index (last_addr, last_frag, first_addr, first_frag) |
2577 | + dir_len); | |
542d6675 KH |
2578 | rlen = ptr->r.record.r.rlen = size; |
2579 | region = ptr; | |
e0c9811a | 2580 | break; |
542d6675 KH |
2581 | } |
2582 | case epilogue: | |
2583 | ptr->r.record.b.t = rlen - 1 - t; | |
2584 | break; | |
e0c9811a | 2585 | |
542d6675 KH |
2586 | case mem_stack_f: |
2587 | case mem_stack_v: | |
2588 | case rp_when: | |
2589 | case pfs_when: | |
2590 | case preds_when: | |
2591 | case unat_when: | |
2592 | case lc_when: | |
2593 | case fpsr_when: | |
2594 | case priunat_when_gr: | |
2595 | case priunat_when_mem: | |
2596 | case bsp_when: | |
2597 | case bspstore_when: | |
2598 | case rnat_when: | |
2599 | ptr->r.record.p.t = t; | |
2600 | break; | |
e0c9811a | 2601 | |
542d6675 KH |
2602 | case spill_reg: |
2603 | case spill_sprel: | |
2604 | case spill_psprel: | |
2605 | case spill_reg_p: | |
2606 | case spill_sprel_p: | |
2607 | case spill_psprel_p: | |
2608 | ptr->r.record.x.t = t; | |
2609 | break; | |
e0c9811a | 2610 | |
542d6675 KH |
2611 | case frgr_mem: |
2612 | if (!region) | |
2613 | { | |
2614 | as_bad ("frgr_mem record before region record!\n"); | |
2615 | return; | |
2616 | } | |
2617 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; | |
2618 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; | |
2619 | set_imask (region, ptr->r.record.p.frmask, t, 1); | |
2620 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2621 | break; | |
2622 | case fr_mem: | |
2623 | if (!region) | |
2624 | { | |
2625 | as_bad ("fr_mem record before region record!\n"); | |
2626 | return; | |
2627 | } | |
2628 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; | |
2629 | set_imask (region, ptr->r.record.p.rmask, t, 1); | |
2630 | break; | |
2631 | case gr_mem: | |
2632 | if (!region) | |
2633 | { | |
2634 | as_bad ("gr_mem record before region record!\n"); | |
2635 | return; | |
2636 | } | |
2637 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; | |
2638 | set_imask (region, ptr->r.record.p.rmask, t, 2); | |
2639 | break; | |
2640 | case br_mem: | |
2641 | if (!region) | |
2642 | { | |
2643 | as_bad ("br_mem record before region record!\n"); | |
2644 | return; | |
2645 | } | |
2646 | region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; | |
2647 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2648 | break; | |
e0c9811a | 2649 | |
542d6675 KH |
2650 | case gr_gr: |
2651 | if (!region) | |
2652 | { | |
2653 | as_bad ("gr_gr record before region record!\n"); | |
2654 | return; | |
2655 | } | |
2656 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2657 | break; | |
2658 | case br_gr: | |
2659 | if (!region) | |
2660 | { | |
2661 | as_bad ("br_gr record before region record!\n"); | |
2662 | return; | |
2663 | } | |
2664 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2665 | break; | |
e0c9811a | 2666 | |
542d6675 KH |
2667 | default: |
2668 | break; | |
800eeca4 JW |
2669 | } |
2670 | } | |
2671 | } | |
2672 | ||
2673 | /* Generate an unwind image from a record list. Returns the number of | |
2674 | bytes in the resulting image. The memory image itselof is returned | |
2675 | in the 'ptr' parameter. */ | |
2676 | static int | |
2677 | output_unw_records (list, ptr) | |
2678 | unw_rec_list *list; | |
2679 | void **ptr; | |
2680 | { | |
2681 | int size, x, extra = 0; | |
2682 | unsigned char *mem; | |
2683 | ||
2684 | fixup_unw_records (list); | |
2685 | size = calc_record_size (list); | |
2686 | ||
2687 | /* pad to 8 byte boundry. */ | |
2688 | x = size % 8; | |
2689 | if (x != 0) | |
2690 | extra = 8 - x; | |
2691 | /* Add 8 for the header + 8 more bytes for the personality offset. */ | |
2692 | mem = xmalloc (size + extra + 16); | |
2693 | ||
2694 | vbyte_mem_ptr = mem + 8; | |
2695 | /* Clear the padding area and personality. */ | |
2696 | memset (mem + 8 + size, 0 , extra + 8); | |
2697 | /* Initialize the header area. */ | |
efcc5914 JW |
2698 | md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */ |
2699 | | (unwind.personality_routine | |
2700 | ? ((bfd_vma) 3 << 32) /* U & E handler flags */ | |
2701 | : 0) | |
e4c58b25 JW |
2702 | | ((size + extra) / 8)), /* length (dwords) */ |
2703 | 8); | |
800eeca4 JW |
2704 | |
2705 | process_unw_records (list, output_vbyte_mem); | |
2706 | ||
2707 | *ptr = mem; | |
2708 | return size + extra + 16; | |
2709 | } | |
2710 | ||
e0c9811a JW |
2711 | static int |
2712 | convert_expr_to_ab_reg (e, ab, regp) | |
2713 | expressionS *e; | |
2714 | unsigned int *ab; | |
2715 | unsigned int *regp; | |
2716 | { | |
2717 | unsigned int reg; | |
2718 | ||
2719 | if (e->X_op != O_register) | |
2720 | return 0; | |
2721 | ||
2722 | reg = e->X_add_number; | |
2434f565 | 2723 | if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) |
e0c9811a JW |
2724 | { |
2725 | *ab = 0; | |
2726 | *regp = reg - REG_GR; | |
2727 | } | |
2434f565 JW |
2728 | else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) |
2729 | || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) | |
e0c9811a JW |
2730 | { |
2731 | *ab = 1; | |
2732 | *regp = reg - REG_FR; | |
2733 | } | |
2434f565 | 2734 | else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) |
e0c9811a JW |
2735 | { |
2736 | *ab = 2; | |
2737 | *regp = reg - REG_BR; | |
2738 | } | |
2739 | else | |
2740 | { | |
2741 | *ab = 3; | |
2742 | switch (reg) | |
2743 | { | |
2744 | case REG_PR: *regp = 0; break; | |
2745 | case REG_PSP: *regp = 1; break; | |
2746 | case REG_PRIUNAT: *regp = 2; break; | |
2747 | case REG_BR + 0: *regp = 3; break; | |
2748 | case REG_AR + AR_BSP: *regp = 4; break; | |
2749 | case REG_AR + AR_BSPSTORE: *regp = 5; break; | |
2750 | case REG_AR + AR_RNAT: *regp = 6; break; | |
2751 | case REG_AR + AR_UNAT: *regp = 7; break; | |
2752 | case REG_AR + AR_FPSR: *regp = 8; break; | |
2753 | case REG_AR + AR_PFS: *regp = 9; break; | |
2754 | case REG_AR + AR_LC: *regp = 10; break; | |
2755 | ||
2756 | default: | |
2757 | return 0; | |
2758 | } | |
2759 | } | |
2760 | return 1; | |
197865e8 | 2761 | } |
e0c9811a JW |
2762 | |
2763 | static int | |
2764 | convert_expr_to_xy_reg (e, xy, regp) | |
2765 | expressionS *e; | |
2766 | unsigned int *xy; | |
2767 | unsigned int *regp; | |
2768 | { | |
2769 | unsigned int reg; | |
2770 | ||
2771 | if (e->X_op != O_register) | |
2772 | return 0; | |
2773 | ||
2774 | reg = e->X_add_number; | |
2775 | ||
2434f565 | 2776 | if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) |
e0c9811a JW |
2777 | { |
2778 | *xy = 0; | |
2779 | *regp = reg - REG_GR; | |
2780 | } | |
2434f565 | 2781 | else if (reg >= REG_FR && reg <= (REG_FR + 127)) |
e0c9811a JW |
2782 | { |
2783 | *xy = 1; | |
2784 | *regp = reg - REG_FR; | |
2785 | } | |
2434f565 | 2786 | else if (reg >= REG_BR && reg <= (REG_BR + 7)) |
e0c9811a JW |
2787 | { |
2788 | *xy = 2; | |
2789 | *regp = reg - REG_BR; | |
2790 | } | |
2791 | else | |
2792 | return -1; | |
2793 | return 1; | |
197865e8 | 2794 | } |
e0c9811a | 2795 | |
800eeca4 JW |
2796 | static void |
2797 | dot_radix (dummy) | |
2434f565 | 2798 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
2799 | { |
2800 | int radix; | |
2801 | ||
2802 | SKIP_WHITESPACE (); | |
2803 | radix = *input_line_pointer++; | |
2804 | ||
2805 | if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) | |
2806 | { | |
2807 | as_bad ("Radix `%c' unsupported", *input_line_pointer); | |
542d6675 | 2808 | ignore_rest_of_line (); |
800eeca4 JW |
2809 | return; |
2810 | } | |
2811 | } | |
2812 | ||
2813 | /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ | |
2814 | static void | |
2815 | dot_special_section (which) | |
2816 | int which; | |
2817 | { | |
2818 | set_section ((char *) special_section_name[which]); | |
2819 | } | |
2820 | ||
2821 | static void | |
2822 | add_unwind_entry (ptr) | |
2823 | unw_rec_list *ptr; | |
2824 | { | |
e0c9811a JW |
2825 | if (unwind.tail) |
2826 | unwind.tail->next = ptr; | |
800eeca4 | 2827 | else |
e0c9811a JW |
2828 | unwind.list = ptr; |
2829 | unwind.tail = ptr; | |
800eeca4 JW |
2830 | |
2831 | /* The current entry can in fact be a chain of unwind entries. */ | |
e0c9811a JW |
2832 | if (unwind.current_entry == NULL) |
2833 | unwind.current_entry = ptr; | |
800eeca4 JW |
2834 | } |
2835 | ||
197865e8 | 2836 | static void |
800eeca4 | 2837 | dot_fframe (dummy) |
2434f565 | 2838 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
2839 | { |
2840 | expressionS e; | |
e0c9811a | 2841 | |
800eeca4 | 2842 | parse_operand (&e); |
197865e8 | 2843 | |
800eeca4 JW |
2844 | if (e.X_op != O_constant) |
2845 | as_bad ("Operand to .fframe must be a constant"); | |
2846 | else | |
e0c9811a JW |
2847 | add_unwind_entry (output_mem_stack_f (e.X_add_number)); |
2848 | } | |
2849 | ||
197865e8 | 2850 | static void |
e0c9811a | 2851 | dot_vframe (dummy) |
2434f565 | 2852 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
2853 | { |
2854 | expressionS e; | |
2855 | unsigned reg; | |
2856 | ||
2857 | parse_operand (&e); | |
2858 | reg = e.X_add_number - REG_GR; | |
2859 | if (e.X_op == O_register && reg < 128) | |
800eeca4 | 2860 | { |
e0c9811a | 2861 | add_unwind_entry (output_mem_stack_v ()); |
30d25259 RH |
2862 | if (! (unwind.prologue_mask & 2)) |
2863 | add_unwind_entry (output_psp_gr (reg)); | |
800eeca4 | 2864 | } |
e0c9811a JW |
2865 | else |
2866 | as_bad ("First operand to .vframe must be a general register"); | |
800eeca4 JW |
2867 | } |
2868 | ||
197865e8 | 2869 | static void |
e0c9811a | 2870 | dot_vframesp (dummy) |
2434f565 | 2871 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 2872 | { |
e0c9811a JW |
2873 | expressionS e; |
2874 | ||
2875 | parse_operand (&e); | |
2876 | if (e.X_op == O_constant) | |
2877 | { | |
2878 | add_unwind_entry (output_mem_stack_v ()); | |
2879 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
2880 | } | |
2881 | else | |
2882 | as_bad ("First operand to .vframesp must be a general register"); | |
2883 | } | |
2884 | ||
197865e8 | 2885 | static void |
e0c9811a | 2886 | dot_vframepsp (dummy) |
2434f565 | 2887 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
2888 | { |
2889 | expressionS e; | |
2890 | ||
2891 | parse_operand (&e); | |
2892 | if (e.X_op == O_constant) | |
2893 | { | |
2894 | add_unwind_entry (output_mem_stack_v ()); | |
2895 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
2896 | } | |
2897 | else | |
2898 | as_bad ("First operand to .vframepsp must be a general register"); | |
800eeca4 JW |
2899 | } |
2900 | ||
197865e8 | 2901 | static void |
800eeca4 | 2902 | dot_save (dummy) |
2434f565 | 2903 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
2904 | { |
2905 | expressionS e1, e2; | |
2906 | int sep; | |
2907 | int reg1, reg2; | |
2908 | ||
2909 | sep = parse_operand (&e1); | |
2910 | if (sep != ',') | |
2911 | as_bad ("No second operand to .save"); | |
2912 | sep = parse_operand (&e2); | |
2913 | ||
e0c9811a | 2914 | reg1 = e1.X_add_number; |
800eeca4 | 2915 | reg2 = e2.X_add_number - REG_GR; |
197865e8 | 2916 | |
800eeca4 | 2917 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 2918 | if (e1.X_op == O_register) |
800eeca4 | 2919 | { |
542d6675 | 2920 | if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) |
800eeca4 JW |
2921 | { |
2922 | switch (reg1) | |
2923 | { | |
542d6675 KH |
2924 | case REG_AR + AR_BSP: |
2925 | add_unwind_entry (output_bsp_when ()); | |
2926 | add_unwind_entry (output_bsp_gr (reg2)); | |
2927 | break; | |
2928 | case REG_AR + AR_BSPSTORE: | |
2929 | add_unwind_entry (output_bspstore_when ()); | |
2930 | add_unwind_entry (output_bspstore_gr (reg2)); | |
2931 | break; | |
2932 | case REG_AR + AR_RNAT: | |
2933 | add_unwind_entry (output_rnat_when ()); | |
2934 | add_unwind_entry (output_rnat_gr (reg2)); | |
2935 | break; | |
2936 | case REG_AR + AR_UNAT: | |
2937 | add_unwind_entry (output_unat_when ()); | |
2938 | add_unwind_entry (output_unat_gr (reg2)); | |
2939 | break; | |
2940 | case REG_AR + AR_FPSR: | |
2941 | add_unwind_entry (output_fpsr_when ()); | |
2942 | add_unwind_entry (output_fpsr_gr (reg2)); | |
2943 | break; | |
2944 | case REG_AR + AR_PFS: | |
2945 | add_unwind_entry (output_pfs_when ()); | |
2946 | if (! (unwind.prologue_mask & 4)) | |
2947 | add_unwind_entry (output_pfs_gr (reg2)); | |
2948 | break; | |
2949 | case REG_AR + AR_LC: | |
2950 | add_unwind_entry (output_lc_when ()); | |
2951 | add_unwind_entry (output_lc_gr (reg2)); | |
2952 | break; | |
2953 | case REG_BR: | |
2954 | add_unwind_entry (output_rp_when ()); | |
2955 | if (! (unwind.prologue_mask & 8)) | |
2956 | add_unwind_entry (output_rp_gr (reg2)); | |
2957 | break; | |
2958 | case REG_PR: | |
2959 | add_unwind_entry (output_preds_when ()); | |
2960 | if (! (unwind.prologue_mask & 1)) | |
2961 | add_unwind_entry (output_preds_gr (reg2)); | |
2962 | break; | |
2963 | case REG_PRIUNAT: | |
2964 | add_unwind_entry (output_priunat_when_gr ()); | |
2965 | add_unwind_entry (output_priunat_gr (reg2)); | |
2966 | break; | |
2967 | default: | |
2968 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
2969 | } |
2970 | } | |
2971 | else | |
2972 | as_bad (" Second operand not a valid register"); | |
2973 | } | |
2974 | else | |
e0c9811a | 2975 | as_bad ("First operand not a register"); |
800eeca4 JW |
2976 | } |
2977 | ||
197865e8 | 2978 | static void |
800eeca4 | 2979 | dot_restore (dummy) |
2434f565 | 2980 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 2981 | { |
e0c9811a JW |
2982 | expressionS e1, e2; |
2983 | unsigned long ecount = 0; | |
2984 | int sep; | |
2985 | ||
2986 | sep = parse_operand (&e1); | |
2987 | if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) | |
2988 | { | |
2989 | as_bad ("First operand to .restore must be stack pointer (sp)"); | |
2990 | return; | |
2991 | } | |
2992 | ||
2993 | if (sep == ',') | |
2994 | { | |
2995 | parse_operand (&e2); | |
2996 | if (e1.X_op != O_constant) | |
2997 | { | |
2998 | as_bad ("Second operand to .restore must be constant"); | |
2999 | return; | |
3000 | } | |
3001 | ecount = e1.X_op; | |
3002 | } | |
3003 | add_unwind_entry (output_epilogue (ecount)); | |
3004 | } | |
3005 | ||
197865e8 | 3006 | static void |
e0c9811a | 3007 | dot_restorereg (dummy) |
2434f565 | 3008 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3009 | { |
3010 | unsigned int ab, reg; | |
3011 | expressionS e; | |
3012 | ||
3013 | parse_operand (&e); | |
3014 | ||
3015 | if (!convert_expr_to_ab_reg (&e, &ab, ®)) | |
3016 | { | |
3017 | as_bad ("First operand to .restorereg must be a preserved register"); | |
3018 | return; | |
3019 | } | |
3020 | add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); | |
3021 | } | |
3022 | ||
197865e8 | 3023 | static void |
e0c9811a | 3024 | dot_restorereg_p (dummy) |
2434f565 | 3025 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3026 | { |
3027 | unsigned int qp, ab, reg; | |
3028 | expressionS e1, e2; | |
3029 | int sep; | |
3030 | ||
3031 | sep = parse_operand (&e1); | |
3032 | if (sep != ',') | |
3033 | { | |
3034 | as_bad ("No second operand to .restorereg.p"); | |
3035 | return; | |
3036 | } | |
3037 | ||
3038 | parse_operand (&e2); | |
3039 | ||
3040 | qp = e1.X_add_number - REG_P; | |
3041 | if (e1.X_op != O_register || qp > 63) | |
3042 | { | |
3043 | as_bad ("First operand to .restorereg.p must be a predicate"); | |
3044 | return; | |
3045 | } | |
3046 | ||
3047 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3048 | { | |
3049 | as_bad ("Second operand to .restorereg.p must be a preserved register"); | |
3050 | return; | |
3051 | } | |
3052 | add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); | |
800eeca4 JW |
3053 | } |
3054 | ||
3055 | static int | |
3056 | generate_unwind_image () | |
3057 | { | |
3058 | int size; | |
3059 | unsigned char *unw_rec; | |
800eeca4 | 3060 | |
10850f29 JW |
3061 | /* Force out pending instructions, to make sure all unwind records have |
3062 | a valid slot_number field. */ | |
3063 | ia64_flush_insns (); | |
3064 | ||
800eeca4 | 3065 | /* Generate the unwind record. */ |
150f24a2 | 3066 | size = output_unw_records (unwind.list, (void **) &unw_rec); |
e0c9811a JW |
3067 | if (size % 8 != 0) |
3068 | as_bad ("Unwind record is not a multiple of 8 bytes."); | |
800eeca4 JW |
3069 | |
3070 | /* If there are unwind records, switch sections, and output the info. */ | |
3071 | if (size != 0) | |
3072 | { | |
800eeca4 | 3073 | unsigned char *where; |
800eeca4 | 3074 | expressionS exp; |
800eeca4 JW |
3075 | set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]); |
3076 | ||
5e7474a7 JW |
3077 | /* Make sure the section has 8 byte alignment. */ |
3078 | record_alignment (now_seg, 3); | |
3079 | ||
800eeca4 | 3080 | /* Set expression which points to start of unwind descriptor area. */ |
e0c9811a | 3081 | unwind.info = expr_build_dot (); |
800eeca4 | 3082 | |
542d6675 | 3083 | where = (unsigned char *) frag_more (size); |
800eeca4 JW |
3084 | |
3085 | /* Issue a label for this address, and keep track of it to put it | |
3086 | in the unwind section. */ | |
3087 | ||
3088 | /* Copy the information from the unwind record into this section. The | |
3089 | data is already in the correct byte order. */ | |
3090 | memcpy (where, unw_rec, size); | |
3091 | /* Add the personality address to the image. */ | |
e0c9811a | 3092 | if (unwind.personality_routine != 0) |
542d6675 | 3093 | { |
800eeca4 | 3094 | exp.X_op = O_symbol; |
e0c9811a | 3095 | exp.X_add_symbol = unwind.personality_routine; |
800eeca4 JW |
3096 | exp.X_add_number = 0; |
3097 | fix_new_exp (frag_now, frag_now_fix () - 8, 8, | |
3098 | &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB); | |
e0c9811a | 3099 | unwind.personality_routine = 0; |
542d6675 | 3100 | } |
800eeca4 JW |
3101 | obj_elf_previous (0); |
3102 | } | |
3103 | ||
e0c9811a JW |
3104 | free_list_records (unwind.list); |
3105 | unwind.list = unwind.tail = unwind.current_entry = NULL; | |
800eeca4 JW |
3106 | |
3107 | return size; | |
3108 | } | |
3109 | ||
197865e8 | 3110 | static void |
542d6675 | 3111 | dot_handlerdata (dummy) |
2434f565 | 3112 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3113 | { |
3114 | generate_unwind_image (); | |
e0c9811a | 3115 | demand_empty_rest_of_line (); |
800eeca4 JW |
3116 | } |
3117 | ||
197865e8 | 3118 | static void |
800eeca4 | 3119 | dot_unwentry (dummy) |
2434f565 | 3120 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3121 | { |
e0c9811a | 3122 | demand_empty_rest_of_line (); |
800eeca4 JW |
3123 | } |
3124 | ||
197865e8 | 3125 | static void |
800eeca4 | 3126 | dot_altrp (dummy) |
2434f565 | 3127 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3128 | { |
e0c9811a JW |
3129 | expressionS e; |
3130 | unsigned reg; | |
3131 | ||
3132 | parse_operand (&e); | |
3133 | reg = e.X_add_number - REG_BR; | |
3134 | if (e.X_op == O_register && reg < 8) | |
3135 | add_unwind_entry (output_rp_br (reg)); | |
3136 | else | |
3137 | as_bad ("First operand not a valid branch register"); | |
800eeca4 JW |
3138 | } |
3139 | ||
197865e8 | 3140 | static void |
e0c9811a JW |
3141 | dot_savemem (psprel) |
3142 | int psprel; | |
800eeca4 JW |
3143 | { |
3144 | expressionS e1, e2; | |
3145 | int sep; | |
3146 | int reg1, val; | |
3147 | ||
3148 | sep = parse_operand (&e1); | |
3149 | if (sep != ',') | |
e0c9811a | 3150 | as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); |
800eeca4 JW |
3151 | sep = parse_operand (&e2); |
3152 | ||
e0c9811a | 3153 | reg1 = e1.X_add_number; |
800eeca4 | 3154 | val = e2.X_add_number; |
197865e8 | 3155 | |
800eeca4 | 3156 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 3157 | if (e1.X_op == O_register) |
800eeca4 JW |
3158 | { |
3159 | if (e2.X_op == O_constant) | |
3160 | { | |
3161 | switch (reg1) | |
3162 | { | |
542d6675 KH |
3163 | case REG_AR + AR_BSP: |
3164 | add_unwind_entry (output_bsp_when ()); | |
3165 | add_unwind_entry ((psprel | |
3166 | ? output_bsp_psprel | |
3167 | : output_bsp_sprel) (val)); | |
3168 | break; | |
3169 | case REG_AR + AR_BSPSTORE: | |
3170 | add_unwind_entry (output_bspstore_when ()); | |
3171 | add_unwind_entry ((psprel | |
3172 | ? output_bspstore_psprel | |
3173 | : output_bspstore_sprel) (val)); | |
3174 | break; | |
3175 | case REG_AR + AR_RNAT: | |
3176 | add_unwind_entry (output_rnat_when ()); | |
3177 | add_unwind_entry ((psprel | |
3178 | ? output_rnat_psprel | |
3179 | : output_rnat_sprel) (val)); | |
3180 | break; | |
3181 | case REG_AR + AR_UNAT: | |
3182 | add_unwind_entry (output_unat_when ()); | |
3183 | add_unwind_entry ((psprel | |
3184 | ? output_unat_psprel | |
3185 | : output_unat_sprel) (val)); | |
3186 | break; | |
3187 | case REG_AR + AR_FPSR: | |
3188 | add_unwind_entry (output_fpsr_when ()); | |
3189 | add_unwind_entry ((psprel | |
3190 | ? output_fpsr_psprel | |
3191 | : output_fpsr_sprel) (val)); | |
3192 | break; | |
3193 | case REG_AR + AR_PFS: | |
3194 | add_unwind_entry (output_pfs_when ()); | |
3195 | add_unwind_entry ((psprel | |
3196 | ? output_pfs_psprel | |
3197 | : output_pfs_sprel) (val)); | |
3198 | break; | |
3199 | case REG_AR + AR_LC: | |
3200 | add_unwind_entry (output_lc_when ()); | |
3201 | add_unwind_entry ((psprel | |
3202 | ? output_lc_psprel | |
3203 | : output_lc_sprel) (val)); | |
3204 | break; | |
3205 | case REG_BR: | |
3206 | add_unwind_entry (output_rp_when ()); | |
3207 | add_unwind_entry ((psprel | |
3208 | ? output_rp_psprel | |
3209 | : output_rp_sprel) (val)); | |
3210 | break; | |
3211 | case REG_PR: | |
3212 | add_unwind_entry (output_preds_when ()); | |
3213 | add_unwind_entry ((psprel | |
3214 | ? output_preds_psprel | |
3215 | : output_preds_sprel) (val)); | |
3216 | break; | |
3217 | case REG_PRIUNAT: | |
3218 | add_unwind_entry (output_priunat_when_mem ()); | |
3219 | add_unwind_entry ((psprel | |
3220 | ? output_priunat_psprel | |
3221 | : output_priunat_sprel) (val)); | |
3222 | break; | |
3223 | default: | |
3224 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
3225 | } |
3226 | } | |
3227 | else | |
3228 | as_bad (" Second operand not a valid constant"); | |
3229 | } | |
3230 | else | |
e0c9811a | 3231 | as_bad ("First operand not a register"); |
800eeca4 JW |
3232 | } |
3233 | ||
197865e8 | 3234 | static void |
800eeca4 | 3235 | dot_saveg (dummy) |
2434f565 | 3236 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3237 | { |
3238 | expressionS e1, e2; | |
3239 | int sep; | |
3240 | sep = parse_operand (&e1); | |
3241 | if (sep == ',') | |
3242 | parse_operand (&e2); | |
197865e8 | 3243 | |
800eeca4 JW |
3244 | if (e1.X_op != O_constant) |
3245 | as_bad ("First operand to .save.g must be a constant."); | |
3246 | else | |
3247 | { | |
3248 | int grmask = e1.X_add_number; | |
3249 | if (sep != ',') | |
3250 | add_unwind_entry (output_gr_mem (grmask)); | |
3251 | else | |
542d6675 | 3252 | { |
800eeca4 | 3253 | int reg = e2.X_add_number - REG_GR; |
542d6675 | 3254 | if (e2.X_op == O_register && reg >= 0 && reg < 128) |
800eeca4 JW |
3255 | add_unwind_entry (output_gr_gr (grmask, reg)); |
3256 | else | |
3257 | as_bad ("Second operand is an invalid register."); | |
3258 | } | |
3259 | } | |
3260 | } | |
3261 | ||
197865e8 | 3262 | static void |
800eeca4 | 3263 | dot_savef (dummy) |
2434f565 | 3264 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3265 | { |
e0c9811a | 3266 | expressionS e1; |
800eeca4 JW |
3267 | int sep; |
3268 | sep = parse_operand (&e1); | |
197865e8 | 3269 | |
800eeca4 JW |
3270 | if (e1.X_op != O_constant) |
3271 | as_bad ("Operand to .save.f must be a constant."); | |
3272 | else | |
e0c9811a | 3273 | add_unwind_entry (output_fr_mem (e1.X_add_number)); |
800eeca4 JW |
3274 | } |
3275 | ||
197865e8 | 3276 | static void |
800eeca4 | 3277 | dot_saveb (dummy) |
2434f565 | 3278 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3279 | { |
e0c9811a JW |
3280 | expressionS e1, e2; |
3281 | unsigned int reg; | |
3282 | unsigned char sep; | |
3283 | int brmask; | |
3284 | ||
800eeca4 | 3285 | sep = parse_operand (&e1); |
800eeca4 | 3286 | if (e1.X_op != O_constant) |
800eeca4 | 3287 | { |
e0c9811a JW |
3288 | as_bad ("First operand to .save.b must be a constant."); |
3289 | return; | |
800eeca4 | 3290 | } |
e0c9811a JW |
3291 | brmask = e1.X_add_number; |
3292 | ||
3293 | if (sep == ',') | |
3294 | { | |
3295 | sep = parse_operand (&e2); | |
3296 | reg = e2.X_add_number - REG_GR; | |
3297 | if (e2.X_op != O_register || reg > 127) | |
3298 | { | |
3299 | as_bad ("Second operand to .save.b must be a general register."); | |
3300 | return; | |
3301 | } | |
3302 | add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); | |
3303 | } | |
3304 | else | |
3305 | add_unwind_entry (output_br_mem (brmask)); | |
3306 | ||
3307 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3308 | ignore_rest_of_line (); | |
800eeca4 JW |
3309 | } |
3310 | ||
197865e8 | 3311 | static void |
800eeca4 | 3312 | dot_savegf (dummy) |
2434f565 | 3313 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3314 | { |
3315 | expressionS e1, e2; | |
3316 | int sep; | |
3317 | sep = parse_operand (&e1); | |
3318 | if (sep == ',') | |
3319 | parse_operand (&e2); | |
197865e8 | 3320 | |
800eeca4 JW |
3321 | if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) |
3322 | as_bad ("Both operands of .save.gf must be constants."); | |
3323 | else | |
3324 | { | |
3325 | int grmask = e1.X_add_number; | |
3326 | int frmask = e2.X_add_number; | |
3327 | add_unwind_entry (output_frgr_mem (grmask, frmask)); | |
3328 | } | |
3329 | } | |
3330 | ||
197865e8 | 3331 | static void |
800eeca4 | 3332 | dot_spill (dummy) |
2434f565 | 3333 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3334 | { |
3335 | expressionS e; | |
e0c9811a JW |
3336 | unsigned char sep; |
3337 | ||
3338 | sep = parse_operand (&e); | |
3339 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3340 | ignore_rest_of_line (); | |
197865e8 | 3341 | |
800eeca4 JW |
3342 | if (e.X_op != O_constant) |
3343 | as_bad ("Operand to .spill must be a constant"); | |
3344 | else | |
e0c9811a JW |
3345 | add_unwind_entry (output_spill_base (e.X_add_number)); |
3346 | } | |
3347 | ||
3348 | static void | |
3349 | dot_spillreg (dummy) | |
2434f565 | 3350 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3351 | { |
3352 | int sep, ab, xy, reg, treg; | |
3353 | expressionS e1, e2; | |
3354 | ||
3355 | sep = parse_operand (&e1); | |
3356 | if (sep != ',') | |
3357 | { | |
3358 | as_bad ("No second operand to .spillreg"); | |
3359 | return; | |
3360 | } | |
3361 | ||
3362 | parse_operand (&e2); | |
3363 | ||
3364 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
800eeca4 | 3365 | { |
e0c9811a JW |
3366 | as_bad ("First operand to .spillreg must be a preserved register"); |
3367 | return; | |
800eeca4 | 3368 | } |
e0c9811a JW |
3369 | |
3370 | if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) | |
3371 | { | |
3372 | as_bad ("Second operand to .spillreg must be a register"); | |
3373 | return; | |
3374 | } | |
3375 | ||
3376 | add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); | |
3377 | } | |
3378 | ||
3379 | static void | |
3380 | dot_spillmem (psprel) | |
3381 | int psprel; | |
3382 | { | |
3383 | expressionS e1, e2; | |
3384 | int sep, ab, reg; | |
3385 | ||
3386 | sep = parse_operand (&e1); | |
3387 | if (sep != ',') | |
3388 | { | |
3389 | as_bad ("Second operand missing"); | |
3390 | return; | |
3391 | } | |
3392 | ||
3393 | parse_operand (&e2); | |
3394 | ||
3395 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
3396 | { | |
3397 | as_bad ("First operand to .spill%s must be a preserved register", | |
3398 | psprel ? "psp" : "sp"); | |
3399 | return; | |
3400 | } | |
3401 | ||
3402 | if (e2.X_op != O_constant) | |
3403 | { | |
3404 | as_bad ("Second operand to .spill%s must be a constant", | |
3405 | psprel ? "psp" : "sp"); | |
3406 | return; | |
3407 | } | |
3408 | ||
3409 | if (psprel) | |
3410 | add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); | |
3411 | else | |
3412 | add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); | |
3413 | } | |
3414 | ||
3415 | static void | |
3416 | dot_spillreg_p (dummy) | |
2434f565 | 3417 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3418 | { |
3419 | int sep, ab, xy, reg, treg; | |
3420 | expressionS e1, e2, e3; | |
3421 | unsigned int qp; | |
3422 | ||
3423 | sep = parse_operand (&e1); | |
3424 | if (sep != ',') | |
3425 | { | |
3426 | as_bad ("No second and third operand to .spillreg.p"); | |
3427 | return; | |
3428 | } | |
3429 | ||
3430 | sep = parse_operand (&e2); | |
3431 | if (sep != ',') | |
3432 | { | |
3433 | as_bad ("No third operand to .spillreg.p"); | |
3434 | return; | |
3435 | } | |
3436 | ||
3437 | parse_operand (&e3); | |
3438 | ||
3439 | qp = e1.X_add_number - REG_P; | |
3440 | ||
3441 | if (e1.X_op != O_register || qp > 63) | |
3442 | { | |
3443 | as_bad ("First operand to .spillreg.p must be a predicate"); | |
3444 | return; | |
3445 | } | |
3446 | ||
3447 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3448 | { | |
3449 | as_bad ("Second operand to .spillreg.p must be a preserved register"); | |
3450 | return; | |
3451 | } | |
3452 | ||
3453 | if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) | |
3454 | { | |
3455 | as_bad ("Third operand to .spillreg.p must be a register"); | |
3456 | return; | |
3457 | } | |
3458 | ||
3459 | add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); | |
3460 | } | |
3461 | ||
3462 | static void | |
3463 | dot_spillmem_p (psprel) | |
3464 | int psprel; | |
3465 | { | |
3466 | expressionS e1, e2, e3; | |
3467 | int sep, ab, reg; | |
3468 | unsigned int qp; | |
3469 | ||
3470 | sep = parse_operand (&e1); | |
3471 | if (sep != ',') | |
3472 | { | |
3473 | as_bad ("Second operand missing"); | |
3474 | return; | |
3475 | } | |
3476 | ||
3477 | parse_operand (&e2); | |
3478 | if (sep != ',') | |
3479 | { | |
3480 | as_bad ("Second operand missing"); | |
3481 | return; | |
3482 | } | |
3483 | ||
3484 | parse_operand (&e3); | |
3485 | ||
3486 | qp = e1.X_add_number - REG_P; | |
3487 | if (e1.X_op != O_register || qp > 63) | |
3488 | { | |
3489 | as_bad ("First operand to .spill%s_p must be a predicate", | |
3490 | psprel ? "psp" : "sp"); | |
3491 | return; | |
3492 | } | |
3493 | ||
3494 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3495 | { | |
3496 | as_bad ("Second operand to .spill%s_p must be a preserved register", | |
3497 | psprel ? "psp" : "sp"); | |
3498 | return; | |
3499 | } | |
3500 | ||
3501 | if (e3.X_op != O_constant) | |
3502 | { | |
3503 | as_bad ("Third operand to .spill%s_p must be a constant", | |
3504 | psprel ? "psp" : "sp"); | |
3505 | return; | |
3506 | } | |
3507 | ||
3508 | if (psprel) | |
3509 | add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number)); | |
3510 | else | |
3511 | add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number)); | |
3512 | } | |
3513 | ||
3514 | static void | |
3515 | dot_label_state (dummy) | |
2434f565 | 3516 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3517 | { |
3518 | expressionS e; | |
3519 | ||
3520 | parse_operand (&e); | |
3521 | if (e.X_op != O_constant) | |
3522 | { | |
3523 | as_bad ("Operand to .label_state must be a constant"); | |
3524 | return; | |
3525 | } | |
3526 | add_unwind_entry (output_label_state (e.X_add_number)); | |
3527 | } | |
3528 | ||
3529 | static void | |
3530 | dot_copy_state (dummy) | |
2434f565 | 3531 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3532 | { |
3533 | expressionS e; | |
3534 | ||
3535 | parse_operand (&e); | |
3536 | if (e.X_op != O_constant) | |
3537 | { | |
3538 | as_bad ("Operand to .copy_state must be a constant"); | |
3539 | return; | |
3540 | } | |
3541 | add_unwind_entry (output_copy_state (e.X_add_number)); | |
800eeca4 JW |
3542 | } |
3543 | ||
197865e8 | 3544 | static void |
800eeca4 | 3545 | dot_unwabi (dummy) |
2434f565 | 3546 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3547 | { |
e0c9811a JW |
3548 | expressionS e1, e2; |
3549 | unsigned char sep; | |
3550 | ||
3551 | sep = parse_operand (&e1); | |
3552 | if (sep != ',') | |
3553 | { | |
3554 | as_bad ("Second operand to .unwabi missing"); | |
3555 | return; | |
3556 | } | |
3557 | sep = parse_operand (&e2); | |
3558 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3559 | ignore_rest_of_line (); | |
3560 | ||
3561 | if (e1.X_op != O_constant) | |
3562 | { | |
3563 | as_bad ("First operand to .unwabi must be a constant"); | |
3564 | return; | |
3565 | } | |
3566 | ||
3567 | if (e2.X_op != O_constant) | |
3568 | { | |
3569 | as_bad ("Second operand to .unwabi must be a constant"); | |
3570 | return; | |
3571 | } | |
3572 | ||
3573 | add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); | |
800eeca4 JW |
3574 | } |
3575 | ||
197865e8 | 3576 | static void |
800eeca4 | 3577 | dot_personality (dummy) |
2434f565 | 3578 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3579 | { |
3580 | char *name, *p, c; | |
3581 | SKIP_WHITESPACE (); | |
3582 | name = input_line_pointer; | |
3583 | c = get_symbol_end (); | |
3584 | p = input_line_pointer; | |
e0c9811a | 3585 | unwind.personality_routine = symbol_find_or_make (name); |
800eeca4 JW |
3586 | *p = c; |
3587 | SKIP_WHITESPACE (); | |
3588 | demand_empty_rest_of_line (); | |
3589 | } | |
3590 | ||
3591 | static void | |
3592 | dot_proc (dummy) | |
2434f565 | 3593 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3594 | { |
3595 | char *name, *p, c; | |
3596 | symbolS *sym; | |
3597 | ||
e0c9811a JW |
3598 | unwind.proc_start = expr_build_dot (); |
3599 | /* Parse names of main and alternate entry points and mark them as | |
542d6675 | 3600 | function symbols: */ |
800eeca4 JW |
3601 | while (1) |
3602 | { | |
3603 | SKIP_WHITESPACE (); | |
3604 | name = input_line_pointer; | |
3605 | c = get_symbol_end (); | |
3606 | p = input_line_pointer; | |
3607 | sym = symbol_find_or_make (name); | |
e0c9811a | 3608 | if (unwind.proc_start == 0) |
542d6675 | 3609 | { |
e0c9811a | 3610 | unwind.proc_start = sym; |
800eeca4 JW |
3611 | } |
3612 | symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; | |
3613 | *p = c; | |
3614 | SKIP_WHITESPACE (); | |
3615 | if (*input_line_pointer != ',') | |
3616 | break; | |
3617 | ++input_line_pointer; | |
3618 | } | |
3619 | demand_empty_rest_of_line (); | |
3620 | ia64_do_align (16); | |
3621 | ||
e0c9811a JW |
3622 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
3623 | unwind.personality_routine = 0; | |
800eeca4 JW |
3624 | } |
3625 | ||
3626 | static void | |
3627 | dot_body (dummy) | |
2434f565 | 3628 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3629 | { |
e0c9811a | 3630 | unwind.prologue = 0; |
30d25259 RH |
3631 | unwind.prologue_mask = 0; |
3632 | ||
800eeca4 | 3633 | add_unwind_entry (output_body ()); |
e0c9811a | 3634 | demand_empty_rest_of_line (); |
800eeca4 JW |
3635 | } |
3636 | ||
3637 | static void | |
3638 | dot_prologue (dummy) | |
2434f565 | 3639 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3640 | { |
e0c9811a | 3641 | unsigned char sep; |
2434f565 | 3642 | int mask = 0, grsave = 0; |
e0c9811a | 3643 | |
e0c9811a | 3644 | if (!is_it_end_of_statement ()) |
800eeca4 JW |
3645 | { |
3646 | expressionS e1, e2; | |
800eeca4 JW |
3647 | sep = parse_operand (&e1); |
3648 | if (sep != ',') | |
3649 | as_bad ("No second operand to .prologue"); | |
3650 | sep = parse_operand (&e2); | |
e0c9811a | 3651 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
542d6675 | 3652 | ignore_rest_of_line (); |
800eeca4 JW |
3653 | |
3654 | if (e1.X_op == O_constant) | |
542d6675 | 3655 | { |
30d25259 RH |
3656 | mask = e1.X_add_number; |
3657 | ||
800eeca4 | 3658 | if (e2.X_op == O_constant) |
30d25259 RH |
3659 | grsave = e2.X_add_number; |
3660 | else if (e2.X_op == O_register | |
3661 | && (grsave = e2.X_add_number - REG_GR) < 128) | |
3662 | ; | |
800eeca4 | 3663 | else |
30d25259 RH |
3664 | as_bad ("Second operand not a constant or general register"); |
3665 | ||
3666 | add_unwind_entry (output_prologue_gr (mask, grsave)); | |
800eeca4 JW |
3667 | } |
3668 | else | |
3669 | as_bad ("First operand not a constant"); | |
3670 | } | |
3671 | else | |
3672 | add_unwind_entry (output_prologue ()); | |
30d25259 RH |
3673 | |
3674 | unwind.prologue = 1; | |
3675 | unwind.prologue_mask = mask; | |
800eeca4 JW |
3676 | } |
3677 | ||
3678 | static void | |
3679 | dot_endp (dummy) | |
2434f565 | 3680 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3681 | { |
3682 | expressionS e; | |
3683 | unsigned char *ptr; | |
44f5c83a | 3684 | int bytes_per_address; |
800eeca4 JW |
3685 | long where; |
3686 | segT saved_seg; | |
3687 | subsegT saved_subseg; | |
3688 | ||
3689 | saved_seg = now_seg; | |
3690 | saved_subseg = now_subseg; | |
3691 | ||
3692 | expression (&e); | |
3693 | demand_empty_rest_of_line (); | |
3694 | ||
3695 | insn_group_break (1, 0, 0); | |
800eeca4 JW |
3696 | |
3697 | /* If there was a .handlerdata, we haven't generated an image yet. */ | |
e0c9811a | 3698 | if (unwind.info == 0) |
800eeca4 JW |
3699 | { |
3700 | generate_unwind_image (); | |
3701 | } | |
3702 | ||
3703 | subseg_set (md.last_text_seg, 0); | |
e0c9811a | 3704 | unwind.proc_end = expr_build_dot (); |
800eeca4 JW |
3705 | |
3706 | set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]); | |
5e7474a7 JW |
3707 | |
3708 | /* Make sure the section has 8 byte alignment. */ | |
3709 | record_alignment (now_seg, 3); | |
3710 | ||
800eeca4 JW |
3711 | ptr = frag_more (24); |
3712 | where = frag_now_fix () - 24; | |
44f5c83a | 3713 | bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; |
800eeca4 JW |
3714 | |
3715 | /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ | |
3716 | e.X_op = O_pseudo_fixup; | |
3717 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3718 | e.X_add_number = 0; | |
e0c9811a | 3719 | e.X_add_symbol = unwind.proc_start; |
44f5c83a | 3720 | ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); |
800eeca4 JW |
3721 | |
3722 | e.X_op = O_pseudo_fixup; | |
3723 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3724 | e.X_add_number = 0; | |
e0c9811a | 3725 | e.X_add_symbol = unwind.proc_end; |
44f5c83a | 3726 | ia64_cons_fix_new (frag_now, where + bytes_per_address, bytes_per_address, &e); |
800eeca4 | 3727 | |
e0c9811a | 3728 | if (unwind.info != 0) |
800eeca4 JW |
3729 | { |
3730 | e.X_op = O_pseudo_fixup; | |
3731 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3732 | e.X_add_number = 0; | |
e0c9811a | 3733 | e.X_add_symbol = unwind.info; |
44f5c83a | 3734 | ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), bytes_per_address, &e); |
800eeca4 JW |
3735 | } |
3736 | else | |
44f5c83a | 3737 | md_number_to_chars (ptr + (bytes_per_address * 2), 0, bytes_per_address); |
800eeca4 JW |
3738 | |
3739 | subseg_set (saved_seg, saved_subseg); | |
e0c9811a | 3740 | unwind.proc_start = unwind.proc_end = unwind.info = 0; |
800eeca4 JW |
3741 | } |
3742 | ||
3743 | static void | |
3744 | dot_template (template) | |
3745 | int template; | |
3746 | { | |
3747 | CURR_SLOT.user_template = template; | |
3748 | } | |
3749 | ||
3750 | static void | |
3751 | dot_regstk (dummy) | |
2434f565 | 3752 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3753 | { |
3754 | int ins, locs, outs, rots; | |
3755 | ||
3756 | if (is_it_end_of_statement ()) | |
3757 | ins = locs = outs = rots = 0; | |
3758 | else | |
3759 | { | |
3760 | ins = get_absolute_expression (); | |
3761 | if (*input_line_pointer++ != ',') | |
3762 | goto err; | |
3763 | locs = get_absolute_expression (); | |
3764 | if (*input_line_pointer++ != ',') | |
3765 | goto err; | |
3766 | outs = get_absolute_expression (); | |
3767 | if (*input_line_pointer++ != ',') | |
3768 | goto err; | |
3769 | rots = get_absolute_expression (); | |
3770 | } | |
3771 | set_regstack (ins, locs, outs, rots); | |
3772 | return; | |
3773 | ||
3774 | err: | |
3775 | as_bad ("Comma expected"); | |
3776 | ignore_rest_of_line (); | |
3777 | } | |
3778 | ||
3779 | static void | |
3780 | dot_rot (type) | |
3781 | int type; | |
3782 | { | |
3783 | unsigned num_regs, num_alloced = 0; | |
3784 | struct dynreg **drpp, *dr; | |
3785 | int ch, base_reg = 0; | |
3786 | char *name, *start; | |
3787 | size_t len; | |
3788 | ||
3789 | switch (type) | |
3790 | { | |
3791 | case DYNREG_GR: base_reg = REG_GR + 32; break; | |
3792 | case DYNREG_FR: base_reg = REG_FR + 32; break; | |
3793 | case DYNREG_PR: base_reg = REG_P + 16; break; | |
3794 | default: break; | |
3795 | } | |
3796 | ||
542d6675 | 3797 | /* First, remove existing names from hash table. */ |
800eeca4 JW |
3798 | for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) |
3799 | { | |
3800 | hash_delete (md.dynreg_hash, dr->name); | |
3801 | dr->num_regs = 0; | |
3802 | } | |
3803 | ||
3804 | drpp = &md.dynreg[type]; | |
3805 | while (1) | |
3806 | { | |
3807 | start = input_line_pointer; | |
3808 | ch = get_symbol_end (); | |
3809 | *input_line_pointer = ch; | |
3810 | len = (input_line_pointer - start); | |
3811 | ||
3812 | SKIP_WHITESPACE (); | |
3813 | if (*input_line_pointer != '[') | |
3814 | { | |
3815 | as_bad ("Expected '['"); | |
3816 | goto err; | |
3817 | } | |
3818 | ++input_line_pointer; /* skip '[' */ | |
3819 | ||
3820 | num_regs = get_absolute_expression (); | |
3821 | ||
3822 | if (*input_line_pointer++ != ']') | |
3823 | { | |
3824 | as_bad ("Expected ']'"); | |
3825 | goto err; | |
3826 | } | |
3827 | SKIP_WHITESPACE (); | |
3828 | ||
3829 | num_alloced += num_regs; | |
3830 | switch (type) | |
3831 | { | |
3832 | case DYNREG_GR: | |
3833 | if (num_alloced > md.rot.num_regs) | |
3834 | { | |
3835 | as_bad ("Used more than the declared %d rotating registers", | |
3836 | md.rot.num_regs); | |
3837 | goto err; | |
3838 | } | |
3839 | break; | |
3840 | case DYNREG_FR: | |
3841 | if (num_alloced > 96) | |
3842 | { | |
3843 | as_bad ("Used more than the available 96 rotating registers"); | |
3844 | goto err; | |
3845 | } | |
3846 | break; | |
3847 | case DYNREG_PR: | |
3848 | if (num_alloced > 48) | |
3849 | { | |
3850 | as_bad ("Used more than the available 48 rotating registers"); | |
3851 | goto err; | |
3852 | } | |
3853 | break; | |
3854 | ||
3855 | default: | |
3856 | break; | |
3857 | } | |
3858 | ||
3859 | name = obstack_alloc (¬es, len + 1); | |
3860 | memcpy (name, start, len); | |
3861 | name[len] = '\0'; | |
3862 | ||
3863 | if (!*drpp) | |
3864 | { | |
3865 | *drpp = obstack_alloc (¬es, sizeof (*dr)); | |
3866 | memset (*drpp, 0, sizeof (*dr)); | |
3867 | } | |
3868 | ||
3869 | dr = *drpp; | |
3870 | dr->name = name; | |
3871 | dr->num_regs = num_regs; | |
3872 | dr->base = base_reg; | |
3873 | drpp = &dr->next; | |
3874 | base_reg += num_regs; | |
3875 | ||
3876 | if (hash_insert (md.dynreg_hash, name, dr)) | |
3877 | { | |
3878 | as_bad ("Attempt to redefine register set `%s'", name); | |
3879 | goto err; | |
3880 | } | |
3881 | ||
3882 | if (*input_line_pointer != ',') | |
3883 | break; | |
3884 | ++input_line_pointer; /* skip comma */ | |
3885 | SKIP_WHITESPACE (); | |
3886 | } | |
3887 | demand_empty_rest_of_line (); | |
3888 | return; | |
3889 | ||
3890 | err: | |
3891 | ignore_rest_of_line (); | |
3892 | } | |
3893 | ||
3894 | static void | |
3895 | dot_byteorder (byteorder) | |
3896 | int byteorder; | |
3897 | { | |
3898 | target_big_endian = byteorder; | |
3899 | } | |
3900 | ||
3901 | static void | |
3902 | dot_psr (dummy) | |
2434f565 | 3903 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3904 | { |
3905 | char *option; | |
3906 | int ch; | |
3907 | ||
3908 | while (1) | |
3909 | { | |
3910 | option = input_line_pointer; | |
3911 | ch = get_symbol_end (); | |
3912 | if (strcmp (option, "lsb") == 0) | |
3913 | md.flags &= ~EF_IA_64_BE; | |
3914 | else if (strcmp (option, "msb") == 0) | |
3915 | md.flags |= EF_IA_64_BE; | |
3916 | else if (strcmp (option, "abi32") == 0) | |
3917 | md.flags &= ~EF_IA_64_ABI64; | |
3918 | else if (strcmp (option, "abi64") == 0) | |
3919 | md.flags |= EF_IA_64_ABI64; | |
3920 | else | |
3921 | as_bad ("Unknown psr option `%s'", option); | |
3922 | *input_line_pointer = ch; | |
3923 | ||
3924 | SKIP_WHITESPACE (); | |
3925 | if (*input_line_pointer != ',') | |
3926 | break; | |
3927 | ||
3928 | ++input_line_pointer; | |
3929 | SKIP_WHITESPACE (); | |
3930 | } | |
3931 | demand_empty_rest_of_line (); | |
3932 | } | |
3933 | ||
3934 | static void | |
3935 | dot_alias (dummy) | |
2434f565 | 3936 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3937 | { |
3938 | as_bad (".alias not implemented yet"); | |
3939 | } | |
3940 | ||
3941 | static void | |
3942 | dot_ln (dummy) | |
2434f565 | 3943 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3944 | { |
3945 | new_logical_line (0, get_absolute_expression ()); | |
3946 | demand_empty_rest_of_line (); | |
3947 | } | |
3948 | ||
542d6675 | 3949 | static char * |
800eeca4 JW |
3950 | parse_section_name () |
3951 | { | |
3952 | char *name; | |
3953 | int len; | |
3954 | ||
3955 | SKIP_WHITESPACE (); | |
3956 | if (*input_line_pointer != '"') | |
3957 | { | |
3958 | as_bad ("Missing section name"); | |
3959 | ignore_rest_of_line (); | |
3960 | return 0; | |
3961 | } | |
3962 | name = demand_copy_C_string (&len); | |
3963 | if (!name) | |
3964 | { | |
3965 | ignore_rest_of_line (); | |
3966 | return 0; | |
3967 | } | |
3968 | SKIP_WHITESPACE (); | |
3969 | if (*input_line_pointer != ',') | |
3970 | { | |
3971 | as_bad ("Comma expected after section name"); | |
3972 | ignore_rest_of_line (); | |
3973 | return 0; | |
3974 | } | |
3975 | ++input_line_pointer; /* skip comma */ | |
3976 | return name; | |
3977 | } | |
3978 | ||
3979 | static void | |
3980 | dot_xdata (size) | |
3981 | int size; | |
3982 | { | |
3983 | char *name = parse_section_name (); | |
3984 | if (!name) | |
3985 | return; | |
3986 | ||
3987 | set_section (name); | |
3988 | cons (size); | |
3989 | obj_elf_previous (0); | |
3990 | } | |
3991 | ||
3992 | /* Why doesn't float_cons() call md_cons_align() the way cons() does? */ | |
542d6675 | 3993 | |
800eeca4 JW |
3994 | static void |
3995 | stmt_float_cons (kind) | |
3996 | int kind; | |
3997 | { | |
3998 | size_t size; | |
3999 | ||
4000 | switch (kind) | |
4001 | { | |
4002 | case 'd': size = 8; break; | |
4003 | case 'x': size = 10; break; | |
4004 | ||
4005 | case 'f': | |
4006 | default: | |
4007 | size = 4; | |
4008 | break; | |
4009 | } | |
4010 | ia64_do_align (size); | |
4011 | float_cons (kind); | |
4012 | } | |
4013 | ||
4014 | static void | |
4015 | stmt_cons_ua (size) | |
4016 | int size; | |
4017 | { | |
4018 | int saved_auto_align = md.auto_align; | |
4019 | ||
4020 | md.auto_align = 0; | |
4021 | cons (size); | |
4022 | md.auto_align = saved_auto_align; | |
4023 | } | |
4024 | ||
4025 | static void | |
4026 | dot_xfloat_cons (kind) | |
4027 | int kind; | |
4028 | { | |
4029 | char *name = parse_section_name (); | |
4030 | if (!name) | |
4031 | return; | |
4032 | ||
4033 | set_section (name); | |
4034 | stmt_float_cons (kind); | |
4035 | obj_elf_previous (0); | |
4036 | } | |
4037 | ||
4038 | static void | |
4039 | dot_xstringer (zero) | |
4040 | int zero; | |
4041 | { | |
4042 | char *name = parse_section_name (); | |
4043 | if (!name) | |
4044 | return; | |
4045 | ||
4046 | set_section (name); | |
4047 | stringer (zero); | |
4048 | obj_elf_previous (0); | |
4049 | } | |
4050 | ||
4051 | static void | |
4052 | dot_xdata_ua (size) | |
4053 | int size; | |
4054 | { | |
4055 | int saved_auto_align = md.auto_align; | |
4056 | char *name = parse_section_name (); | |
4057 | if (!name) | |
4058 | return; | |
4059 | ||
4060 | set_section (name); | |
4061 | md.auto_align = 0; | |
4062 | cons (size); | |
4063 | md.auto_align = saved_auto_align; | |
4064 | obj_elf_previous (0); | |
4065 | } | |
4066 | ||
4067 | static void | |
4068 | dot_xfloat_cons_ua (kind) | |
4069 | int kind; | |
4070 | { | |
4071 | int saved_auto_align = md.auto_align; | |
4072 | char *name = parse_section_name (); | |
4073 | if (!name) | |
4074 | return; | |
4075 | ||
4076 | set_section (name); | |
4077 | md.auto_align = 0; | |
4078 | stmt_float_cons (kind); | |
4079 | md.auto_align = saved_auto_align; | |
4080 | obj_elf_previous (0); | |
4081 | } | |
4082 | ||
4083 | /* .reg.val <regname>,value */ | |
542d6675 | 4084 | |
800eeca4 JW |
4085 | static void |
4086 | dot_reg_val (dummy) | |
2434f565 | 4087 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4088 | { |
4089 | expressionS reg; | |
4090 | ||
4091 | expression (®); | |
4092 | if (reg.X_op != O_register) | |
4093 | { | |
4094 | as_bad (_("Register name expected")); | |
4095 | ignore_rest_of_line (); | |
4096 | } | |
4097 | else if (*input_line_pointer++ != ',') | |
4098 | { | |
4099 | as_bad (_("Comma expected")); | |
4100 | ignore_rest_of_line (); | |
4101 | } | |
197865e8 | 4102 | else |
800eeca4 JW |
4103 | { |
4104 | valueT value = get_absolute_expression (); | |
4105 | int regno = reg.X_add_number; | |
542d6675 KH |
4106 | if (regno < REG_GR || regno > REG_GR + 128) |
4107 | as_warn (_("Register value annotation ignored")); | |
800eeca4 | 4108 | else |
542d6675 KH |
4109 | { |
4110 | gr_values[regno - REG_GR].known = 1; | |
4111 | gr_values[regno - REG_GR].value = value; | |
4112 | gr_values[regno - REG_GR].path = md.path; | |
4113 | } | |
800eeca4 JW |
4114 | } |
4115 | demand_empty_rest_of_line (); | |
4116 | } | |
4117 | ||
197865e8 | 4118 | /* select dv checking mode |
800eeca4 JW |
4119 | .auto |
4120 | .explicit | |
4121 | .default | |
4122 | ||
197865e8 | 4123 | A stop is inserted when changing modes |
800eeca4 | 4124 | */ |
542d6675 | 4125 | |
800eeca4 JW |
4126 | static void |
4127 | dot_dv_mode (type) | |
542d6675 | 4128 | int type; |
800eeca4 JW |
4129 | { |
4130 | if (md.manual_bundling) | |
4131 | as_warn (_("Directive invalid within a bundle")); | |
4132 | ||
4133 | if (type == 'E' || type == 'A') | |
4134 | md.mode_explicitly_set = 0; | |
4135 | else | |
4136 | md.mode_explicitly_set = 1; | |
4137 | ||
4138 | md.detect_dv = 1; | |
4139 | switch (type) | |
4140 | { | |
4141 | case 'A': | |
4142 | case 'a': | |
4143 | if (md.explicit_mode) | |
542d6675 | 4144 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4145 | md.explicit_mode = 0; |
4146 | break; | |
4147 | case 'E': | |
4148 | case 'e': | |
4149 | if (!md.explicit_mode) | |
542d6675 | 4150 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4151 | md.explicit_mode = 1; |
4152 | break; | |
4153 | default: | |
4154 | case 'd': | |
4155 | if (md.explicit_mode != md.default_explicit_mode) | |
542d6675 | 4156 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4157 | md.explicit_mode = md.default_explicit_mode; |
4158 | md.mode_explicitly_set = 0; | |
4159 | break; | |
4160 | } | |
4161 | } | |
4162 | ||
4163 | static void | |
4164 | print_prmask (mask) | |
542d6675 | 4165 | valueT mask; |
800eeca4 JW |
4166 | { |
4167 | int regno; | |
4168 | char *comma = ""; | |
542d6675 | 4169 | for (regno = 0; regno < 64; regno++) |
800eeca4 | 4170 | { |
542d6675 KH |
4171 | if (mask & ((valueT) 1 << regno)) |
4172 | { | |
4173 | fprintf (stderr, "%s p%d", comma, regno); | |
4174 | comma = ","; | |
4175 | } | |
800eeca4 JW |
4176 | } |
4177 | } | |
4178 | ||
4179 | /* | |
4180 | .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") | |
4181 | .pred.rel.imply p1, p2 (also .pred.rel "imply") | |
4182 | .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") | |
4183 | .pred.safe_across_calls p1 [, p2 [,...]] | |
4184 | */ | |
542d6675 | 4185 | |
800eeca4 JW |
4186 | static void |
4187 | dot_pred_rel (type) | |
542d6675 | 4188 | int type; |
800eeca4 JW |
4189 | { |
4190 | valueT mask = 0; | |
4191 | int count = 0; | |
4192 | int p1 = -1, p2 = -1; | |
4193 | ||
4194 | if (type == 0) | |
4195 | { | |
4196 | if (*input_line_pointer != '"') | |
542d6675 KH |
4197 | { |
4198 | as_bad (_("Missing predicate relation type")); | |
4199 | ignore_rest_of_line (); | |
4200 | return; | |
4201 | } | |
197865e8 | 4202 | else |
542d6675 KH |
4203 | { |
4204 | int len; | |
4205 | char *form = demand_copy_C_string (&len); | |
4206 | if (strcmp (form, "mutex") == 0) | |
4207 | type = 'm'; | |
4208 | else if (strcmp (form, "clear") == 0) | |
4209 | type = 'c'; | |
4210 | else if (strcmp (form, "imply") == 0) | |
4211 | type = 'i'; | |
4212 | else | |
4213 | { | |
4214 | as_bad (_("Unrecognized predicate relation type")); | |
4215 | ignore_rest_of_line (); | |
4216 | return; | |
4217 | } | |
4218 | } | |
800eeca4 | 4219 | if (*input_line_pointer == ',') |
542d6675 | 4220 | ++input_line_pointer; |
800eeca4 JW |
4221 | SKIP_WHITESPACE (); |
4222 | } | |
4223 | ||
4224 | SKIP_WHITESPACE (); | |
4225 | while (1) | |
4226 | { | |
4227 | valueT bit = 1; | |
4228 | int regno; | |
197865e8 | 4229 | |
800eeca4 | 4230 | if (toupper (*input_line_pointer) != 'P' |
542d6675 KH |
4231 | || (regno = atoi (++input_line_pointer)) < 0 |
4232 | || regno > 63) | |
4233 | { | |
4234 | as_bad (_("Predicate register expected")); | |
4235 | ignore_rest_of_line (); | |
4236 | return; | |
4237 | } | |
800eeca4 | 4238 | while (isdigit (*input_line_pointer)) |
542d6675 | 4239 | ++input_line_pointer; |
800eeca4 | 4240 | if (p1 == -1) |
542d6675 | 4241 | p1 = regno; |
800eeca4 | 4242 | else if (p2 == -1) |
542d6675 | 4243 | p2 = regno; |
800eeca4 JW |
4244 | bit <<= regno; |
4245 | if (mask & bit) | |
542d6675 KH |
4246 | as_warn (_("Duplicate predicate register ignored")); |
4247 | mask |= bit; | |
4248 | count++; | |
4249 | /* See if it's a range. */ | |
800eeca4 | 4250 | if (*input_line_pointer == '-') |
542d6675 KH |
4251 | { |
4252 | valueT stop = 1; | |
4253 | ++input_line_pointer; | |
4254 | ||
4255 | if (toupper (*input_line_pointer) != 'P' | |
4256 | || (regno = atoi (++input_line_pointer)) < 0 | |
4257 | || regno > 63) | |
4258 | { | |
4259 | as_bad (_("Predicate register expected")); | |
4260 | ignore_rest_of_line (); | |
4261 | return; | |
4262 | } | |
4263 | while (isdigit (*input_line_pointer)) | |
4264 | ++input_line_pointer; | |
4265 | stop <<= regno; | |
4266 | if (bit >= stop) | |
4267 | { | |
4268 | as_bad (_("Bad register range")); | |
4269 | ignore_rest_of_line (); | |
4270 | return; | |
4271 | } | |
4272 | while (bit < stop) | |
4273 | { | |
4274 | bit <<= 1; | |
4275 | mask |= bit; | |
4276 | count++; | |
4277 | } | |
4278 | SKIP_WHITESPACE (); | |
4279 | } | |
800eeca4 | 4280 | if (*input_line_pointer != ',') |
542d6675 | 4281 | break; |
800eeca4 JW |
4282 | ++input_line_pointer; |
4283 | SKIP_WHITESPACE (); | |
4284 | } | |
4285 | ||
4286 | switch (type) | |
4287 | { | |
4288 | case 'c': | |
4289 | if (count == 0) | |
542d6675 | 4290 | mask = ~(valueT) 0; |
800eeca4 | 4291 | clear_qp_mutex (mask); |
197865e8 | 4292 | clear_qp_implies (mask, (valueT) 0); |
800eeca4 JW |
4293 | break; |
4294 | case 'i': | |
4295 | if (count != 2 || p1 == -1 || p2 == -1) | |
542d6675 | 4296 | as_bad (_("Predicate source and target required")); |
800eeca4 | 4297 | else if (p1 == 0 || p2 == 0) |
542d6675 | 4298 | as_bad (_("Use of p0 is not valid in this context")); |
800eeca4 | 4299 | else |
542d6675 | 4300 | add_qp_imply (p1, p2); |
800eeca4 JW |
4301 | break; |
4302 | case 'm': | |
4303 | if (count < 2) | |
542d6675 KH |
4304 | { |
4305 | as_bad (_("At least two PR arguments expected")); | |
4306 | break; | |
4307 | } | |
800eeca4 | 4308 | else if (mask & 1) |
542d6675 KH |
4309 | { |
4310 | as_bad (_("Use of p0 is not valid in this context")); | |
4311 | break; | |
4312 | } | |
800eeca4 JW |
4313 | add_qp_mutex (mask); |
4314 | break; | |
4315 | case 's': | |
4316 | /* note that we don't override any existing relations */ | |
4317 | if (count == 0) | |
542d6675 KH |
4318 | { |
4319 | as_bad (_("At least one PR argument expected")); | |
4320 | break; | |
4321 | } | |
800eeca4 | 4322 | if (md.debug_dv) |
542d6675 KH |
4323 | { |
4324 | fprintf (stderr, "Safe across calls: "); | |
4325 | print_prmask (mask); | |
4326 | fprintf (stderr, "\n"); | |
4327 | } | |
800eeca4 JW |
4328 | qp_safe_across_calls = mask; |
4329 | break; | |
4330 | } | |
4331 | demand_empty_rest_of_line (); | |
4332 | } | |
4333 | ||
4334 | /* .entry label [, label [, ...]] | |
4335 | Hint to DV code that the given labels are to be considered entry points. | |
542d6675 KH |
4336 | Otherwise, only global labels are considered entry points. */ |
4337 | ||
800eeca4 JW |
4338 | static void |
4339 | dot_entry (dummy) | |
2434f565 | 4340 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4341 | { |
4342 | const char *err; | |
4343 | char *name; | |
4344 | int c; | |
4345 | symbolS *symbolP; | |
4346 | ||
4347 | do | |
4348 | { | |
4349 | name = input_line_pointer; | |
4350 | c = get_symbol_end (); | |
4351 | symbolP = symbol_find_or_make (name); | |
4352 | ||
4353 | err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); | |
4354 | if (err) | |
542d6675 KH |
4355 | as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), |
4356 | name, err); | |
800eeca4 JW |
4357 | |
4358 | *input_line_pointer = c; | |
4359 | SKIP_WHITESPACE (); | |
4360 | c = *input_line_pointer; | |
4361 | if (c == ',') | |
4362 | { | |
4363 | input_line_pointer++; | |
4364 | SKIP_WHITESPACE (); | |
4365 | if (*input_line_pointer == '\n') | |
4366 | c = '\n'; | |
4367 | } | |
4368 | } | |
4369 | while (c == ','); | |
4370 | ||
4371 | demand_empty_rest_of_line (); | |
4372 | } | |
4373 | ||
197865e8 | 4374 | /* .mem.offset offset, base |
542d6675 KH |
4375 | "base" is used to distinguish between offsets from a different base. */ |
4376 | ||
800eeca4 JW |
4377 | static void |
4378 | dot_mem_offset (dummy) | |
2434f565 | 4379 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4380 | { |
4381 | md.mem_offset.hint = 1; | |
4382 | md.mem_offset.offset = get_absolute_expression (); | |
4383 | if (*input_line_pointer != ',') | |
4384 | { | |
4385 | as_bad (_("Comma expected")); | |
4386 | ignore_rest_of_line (); | |
4387 | return; | |
4388 | } | |
4389 | ++input_line_pointer; | |
4390 | md.mem_offset.base = get_absolute_expression (); | |
4391 | demand_empty_rest_of_line (); | |
4392 | } | |
4393 | ||
542d6675 | 4394 | /* ia64-specific pseudo-ops: */ |
800eeca4 JW |
4395 | const pseudo_typeS md_pseudo_table[] = |
4396 | { | |
4397 | { "radix", dot_radix, 0 }, | |
4398 | { "lcomm", s_lcomm_bytes, 1 }, | |
4399 | { "bss", dot_special_section, SPECIAL_SECTION_BSS }, | |
4400 | { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, | |
4401 | { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, | |
4402 | { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, | |
4403 | { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, | |
4404 | { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, | |
4405 | { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, | |
4406 | { "proc", dot_proc, 0 }, | |
4407 | { "body", dot_body, 0 }, | |
4408 | { "prologue", dot_prologue, 0 }, | |
2434f565 JW |
4409 | { "endp", dot_endp, 0 }, |
4410 | { "file", dwarf2_directive_file, 0 }, | |
4411 | { "loc", dwarf2_directive_loc, 0 }, | |
4412 | ||
4413 | { "fframe", dot_fframe, 0 }, | |
4414 | { "vframe", dot_vframe, 0 }, | |
4415 | { "vframesp", dot_vframesp, 0 }, | |
4416 | { "vframepsp", dot_vframepsp, 0 }, | |
4417 | { "save", dot_save, 0 }, | |
4418 | { "restore", dot_restore, 0 }, | |
4419 | { "restorereg", dot_restorereg, 0 }, | |
4420 | { "restorereg.p", dot_restorereg_p, 0 }, | |
4421 | { "handlerdata", dot_handlerdata, 0 }, | |
4422 | { "unwentry", dot_unwentry, 0 }, | |
4423 | { "altrp", dot_altrp, 0 }, | |
e0c9811a JW |
4424 | { "savesp", dot_savemem, 0 }, |
4425 | { "savepsp", dot_savemem, 1 }, | |
2434f565 JW |
4426 | { "save.g", dot_saveg, 0 }, |
4427 | { "save.f", dot_savef, 0 }, | |
4428 | { "save.b", dot_saveb, 0 }, | |
4429 | { "save.gf", dot_savegf, 0 }, | |
4430 | { "spill", dot_spill, 0 }, | |
4431 | { "spillreg", dot_spillreg, 0 }, | |
e0c9811a JW |
4432 | { "spillsp", dot_spillmem, 0 }, |
4433 | { "spillpsp", dot_spillmem, 1 }, | |
2434f565 | 4434 | { "spillreg.p", dot_spillreg_p, 0 }, |
e0c9811a JW |
4435 | { "spillsp.p", dot_spillmem_p, 0 }, |
4436 | { "spillpsp.p", dot_spillmem_p, 1 }, | |
2434f565 JW |
4437 | { "label_state", dot_label_state, 0 }, |
4438 | { "copy_state", dot_copy_state, 0 }, | |
4439 | { "unwabi", dot_unwabi, 0 }, | |
4440 | { "personality", dot_personality, 0 }, | |
800eeca4 | 4441 | #if 0 |
2434f565 | 4442 | { "estate", dot_estate, 0 }, |
800eeca4 JW |
4443 | #endif |
4444 | { "mii", dot_template, 0x0 }, | |
4445 | { "mli", dot_template, 0x2 }, /* old format, for compatibility */ | |
4446 | { "mlx", dot_template, 0x2 }, | |
4447 | { "mmi", dot_template, 0x4 }, | |
4448 | { "mfi", dot_template, 0x6 }, | |
4449 | { "mmf", dot_template, 0x7 }, | |
4450 | { "mib", dot_template, 0x8 }, | |
4451 | { "mbb", dot_template, 0x9 }, | |
4452 | { "bbb", dot_template, 0xb }, | |
4453 | { "mmb", dot_template, 0xc }, | |
4454 | { "mfb", dot_template, 0xe }, | |
4455 | #if 0 | |
4456 | { "lb", dot_scope, 0 }, | |
4457 | { "le", dot_scope, 1 }, | |
4458 | #endif | |
4459 | { "align", s_align_bytes, 0 }, | |
4460 | { "regstk", dot_regstk, 0 }, | |
4461 | { "rotr", dot_rot, DYNREG_GR }, | |
4462 | { "rotf", dot_rot, DYNREG_FR }, | |
4463 | { "rotp", dot_rot, DYNREG_PR }, | |
4464 | { "lsb", dot_byteorder, 0 }, | |
4465 | { "msb", dot_byteorder, 1 }, | |
4466 | { "psr", dot_psr, 0 }, | |
4467 | { "alias", dot_alias, 0 }, | |
4468 | { "ln", dot_ln, 0 }, /* source line info (for debugging) */ | |
4469 | ||
4470 | { "xdata1", dot_xdata, 1 }, | |
4471 | { "xdata2", dot_xdata, 2 }, | |
4472 | { "xdata4", dot_xdata, 4 }, | |
4473 | { "xdata8", dot_xdata, 8 }, | |
4474 | { "xreal4", dot_xfloat_cons, 'f' }, | |
4475 | { "xreal8", dot_xfloat_cons, 'd' }, | |
4476 | { "xreal10", dot_xfloat_cons, 'x' }, | |
4477 | { "xstring", dot_xstringer, 0 }, | |
4478 | { "xstringz", dot_xstringer, 1 }, | |
4479 | ||
542d6675 | 4480 | /* unaligned versions: */ |
800eeca4 JW |
4481 | { "xdata2.ua", dot_xdata_ua, 2 }, |
4482 | { "xdata4.ua", dot_xdata_ua, 4 }, | |
4483 | { "xdata8.ua", dot_xdata_ua, 8 }, | |
4484 | { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, | |
4485 | { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, | |
4486 | { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, | |
4487 | ||
4488 | /* annotations/DV checking support */ | |
4489 | { "entry", dot_entry, 0 }, | |
2434f565 | 4490 | { "mem.offset", dot_mem_offset, 0 }, |
800eeca4 JW |
4491 | { "pred.rel", dot_pred_rel, 0 }, |
4492 | { "pred.rel.clear", dot_pred_rel, 'c' }, | |
4493 | { "pred.rel.imply", dot_pred_rel, 'i' }, | |
4494 | { "pred.rel.mutex", dot_pred_rel, 'm' }, | |
4495 | { "pred.safe_across_calls", dot_pred_rel, 's' }, | |
2434f565 | 4496 | { "reg.val", dot_reg_val, 0 }, |
800eeca4 JW |
4497 | { "auto", dot_dv_mode, 'a' }, |
4498 | { "explicit", dot_dv_mode, 'e' }, | |
4499 | { "default", dot_dv_mode, 'd' }, | |
4500 | ||
4501 | { NULL, 0, 0 } | |
4502 | }; | |
4503 | ||
4504 | static const struct pseudo_opcode | |
4505 | { | |
4506 | const char *name; | |
4507 | void (*handler) (int); | |
4508 | int arg; | |
4509 | } | |
4510 | pseudo_opcode[] = | |
4511 | { | |
4512 | /* these are more like pseudo-ops, but don't start with a dot */ | |
4513 | { "data1", cons, 1 }, | |
4514 | { "data2", cons, 2 }, | |
4515 | { "data4", cons, 4 }, | |
4516 | { "data8", cons, 8 }, | |
4517 | { "real4", stmt_float_cons, 'f' }, | |
4518 | { "real8", stmt_float_cons, 'd' }, | |
4519 | { "real10", stmt_float_cons, 'x' }, | |
4520 | { "string", stringer, 0 }, | |
4521 | { "stringz", stringer, 1 }, | |
4522 | ||
542d6675 | 4523 | /* unaligned versions: */ |
800eeca4 JW |
4524 | { "data2.ua", stmt_cons_ua, 2 }, |
4525 | { "data4.ua", stmt_cons_ua, 4 }, | |
4526 | { "data8.ua", stmt_cons_ua, 8 }, | |
4527 | { "real4.ua", float_cons, 'f' }, | |
4528 | { "real8.ua", float_cons, 'd' }, | |
4529 | { "real10.ua", float_cons, 'x' }, | |
4530 | }; | |
4531 | ||
4532 | /* Declare a register by creating a symbol for it and entering it in | |
4533 | the symbol table. */ | |
542d6675 KH |
4534 | |
4535 | static symbolS * | |
800eeca4 JW |
4536 | declare_register (name, regnum) |
4537 | const char *name; | |
4538 | int regnum; | |
4539 | { | |
4540 | const char *err; | |
4541 | symbolS *sym; | |
4542 | ||
4543 | sym = symbol_new (name, reg_section, regnum, &zero_address_frag); | |
4544 | ||
4545 | err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); | |
4546 | if (err) | |
4547 | as_fatal ("Inserting \"%s\" into register table failed: %s", | |
4548 | name, err); | |
4549 | ||
4550 | return sym; | |
4551 | } | |
4552 | ||
4553 | static void | |
4554 | declare_register_set (prefix, num_regs, base_regnum) | |
4555 | const char *prefix; | |
4556 | int num_regs; | |
4557 | int base_regnum; | |
4558 | { | |
4559 | char name[8]; | |
4560 | int i; | |
4561 | ||
4562 | for (i = 0; i < num_regs; ++i) | |
4563 | { | |
4564 | sprintf (name, "%s%u", prefix, i); | |
4565 | declare_register (name, base_regnum + i); | |
4566 | } | |
4567 | } | |
4568 | ||
4569 | static unsigned int | |
4570 | operand_width (opnd) | |
4571 | enum ia64_opnd opnd; | |
4572 | { | |
4573 | const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; | |
4574 | unsigned int bits = 0; | |
4575 | int i; | |
4576 | ||
4577 | bits = 0; | |
4578 | for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) | |
4579 | bits += odesc->field[i].bits; | |
4580 | ||
4581 | return bits; | |
4582 | } | |
4583 | ||
4584 | static int | |
4585 | operand_match (idesc, index, e) | |
4586 | const struct ia64_opcode *idesc; | |
4587 | int index; | |
4588 | expressionS *e; | |
4589 | { | |
4590 | enum ia64_opnd opnd = idesc->operands[index]; | |
4591 | int bits, relocatable = 0; | |
4592 | struct insn_fix *fix; | |
4593 | bfd_signed_vma val; | |
4594 | ||
4595 | switch (opnd) | |
4596 | { | |
542d6675 | 4597 | /* constants: */ |
800eeca4 JW |
4598 | |
4599 | case IA64_OPND_AR_CCV: | |
4600 | if (e->X_op == O_register && e->X_add_number == REG_AR + 32) | |
4601 | return 1; | |
4602 | break; | |
4603 | ||
4604 | case IA64_OPND_AR_PFS: | |
4605 | if (e->X_op == O_register && e->X_add_number == REG_AR + 64) | |
4606 | return 1; | |
4607 | break; | |
4608 | ||
4609 | case IA64_OPND_GR0: | |
4610 | if (e->X_op == O_register && e->X_add_number == REG_GR + 0) | |
4611 | return 1; | |
4612 | break; | |
4613 | ||
4614 | case IA64_OPND_IP: | |
4615 | if (e->X_op == O_register && e->X_add_number == REG_IP) | |
4616 | return 1; | |
4617 | break; | |
4618 | ||
4619 | case IA64_OPND_PR: | |
4620 | if (e->X_op == O_register && e->X_add_number == REG_PR) | |
4621 | return 1; | |
4622 | break; | |
4623 | ||
4624 | case IA64_OPND_PR_ROT: | |
4625 | if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) | |
4626 | return 1; | |
4627 | break; | |
4628 | ||
4629 | case IA64_OPND_PSR: | |
4630 | if (e->X_op == O_register && e->X_add_number == REG_PSR) | |
4631 | return 1; | |
4632 | break; | |
4633 | ||
4634 | case IA64_OPND_PSR_L: | |
4635 | if (e->X_op == O_register && e->X_add_number == REG_PSR_L) | |
4636 | return 1; | |
4637 | break; | |
4638 | ||
4639 | case IA64_OPND_PSR_UM: | |
4640 | if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) | |
4641 | return 1; | |
4642 | break; | |
4643 | ||
4644 | case IA64_OPND_C1: | |
4645 | if (e->X_op == O_constant && e->X_add_number == 1) | |
4646 | return 1; | |
4647 | break; | |
4648 | ||
4649 | case IA64_OPND_C8: | |
4650 | if (e->X_op == O_constant && e->X_add_number == 8) | |
4651 | return 1; | |
4652 | break; | |
4653 | ||
4654 | case IA64_OPND_C16: | |
4655 | if (e->X_op == O_constant && e->X_add_number == 16) | |
4656 | return 1; | |
4657 | break; | |
4658 | ||
542d6675 | 4659 | /* register operands: */ |
800eeca4 JW |
4660 | |
4661 | case IA64_OPND_AR3: | |
4662 | if (e->X_op == O_register && e->X_add_number >= REG_AR | |
4663 | && e->X_add_number < REG_AR + 128) | |
4664 | return 1; | |
4665 | break; | |
4666 | ||
4667 | case IA64_OPND_B1: | |
4668 | case IA64_OPND_B2: | |
4669 | if (e->X_op == O_register && e->X_add_number >= REG_BR | |
4670 | && e->X_add_number < REG_BR + 8) | |
4671 | return 1; | |
4672 | break; | |
4673 | ||
4674 | case IA64_OPND_CR3: | |
4675 | if (e->X_op == O_register && e->X_add_number >= REG_CR | |
4676 | && e->X_add_number < REG_CR + 128) | |
4677 | return 1; | |
4678 | break; | |
4679 | ||
4680 | case IA64_OPND_F1: | |
4681 | case IA64_OPND_F2: | |
4682 | case IA64_OPND_F3: | |
4683 | case IA64_OPND_F4: | |
4684 | if (e->X_op == O_register && e->X_add_number >= REG_FR | |
4685 | && e->X_add_number < REG_FR + 128) | |
4686 | return 1; | |
4687 | break; | |
4688 | ||
4689 | case IA64_OPND_P1: | |
4690 | case IA64_OPND_P2: | |
4691 | if (e->X_op == O_register && e->X_add_number >= REG_P | |
4692 | && e->X_add_number < REG_P + 64) | |
4693 | return 1; | |
4694 | break; | |
4695 | ||
4696 | case IA64_OPND_R1: | |
4697 | case IA64_OPND_R2: | |
4698 | case IA64_OPND_R3: | |
4699 | if (e->X_op == O_register && e->X_add_number >= REG_GR | |
4700 | && e->X_add_number < REG_GR + 128) | |
4701 | return 1; | |
4702 | break; | |
4703 | ||
4704 | case IA64_OPND_R3_2: | |
4705 | if (e->X_op == O_register && e->X_add_number >= REG_GR | |
4706 | && e->X_add_number < REG_GR + 4) | |
4707 | return 1; | |
4708 | break; | |
4709 | ||
542d6675 | 4710 | /* indirect operands: */ |
800eeca4 JW |
4711 | case IA64_OPND_CPUID_R3: |
4712 | case IA64_OPND_DBR_R3: | |
4713 | case IA64_OPND_DTR_R3: | |
4714 | case IA64_OPND_ITR_R3: | |
4715 | case IA64_OPND_IBR_R3: | |
4716 | case IA64_OPND_MSR_R3: | |
4717 | case IA64_OPND_PKR_R3: | |
4718 | case IA64_OPND_PMC_R3: | |
4719 | case IA64_OPND_PMD_R3: | |
4720 | case IA64_OPND_RR_R3: | |
4721 | if (e->X_op == O_index && e->X_op_symbol | |
4722 | && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID | |
4723 | == opnd - IA64_OPND_CPUID_R3)) | |
4724 | return 1; | |
4725 | break; | |
4726 | ||
4727 | case IA64_OPND_MR3: | |
4728 | if (e->X_op == O_index && !e->X_op_symbol) | |
4729 | return 1; | |
4730 | break; | |
4731 | ||
542d6675 | 4732 | /* immediate operands: */ |
800eeca4 JW |
4733 | case IA64_OPND_CNT2a: |
4734 | case IA64_OPND_LEN4: | |
4735 | case IA64_OPND_LEN6: | |
4736 | bits = operand_width (idesc->operands[index]); | |
4737 | if (e->X_op == O_constant | |
4738 | && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) | |
4739 | return 1; | |
4740 | break; | |
4741 | ||
4742 | case IA64_OPND_CNT2b: | |
4743 | if (e->X_op == O_constant | |
4744 | && (bfd_vma) (e->X_add_number - 1) < 3) | |
4745 | return 1; | |
4746 | break; | |
4747 | ||
4748 | case IA64_OPND_CNT2c: | |
4749 | val = e->X_add_number; | |
4750 | if (e->X_op == O_constant | |
4751 | && (val == 0 || val == 7 || val == 15 || val == 16)) | |
4752 | return 1; | |
4753 | break; | |
4754 | ||
4755 | case IA64_OPND_SOR: | |
4756 | /* SOR must be an integer multiple of 8 */ | |
4757 | if (e->X_add_number & 0x7) | |
4758 | break; | |
4759 | case IA64_OPND_SOF: | |
4760 | case IA64_OPND_SOL: | |
4761 | if (e->X_op == O_constant && | |
4762 | (bfd_vma) e->X_add_number <= 96) | |
4763 | return 1; | |
4764 | break; | |
4765 | ||
4766 | case IA64_OPND_IMMU62: | |
4767 | if (e->X_op == O_constant) | |
542d6675 | 4768 | { |
800eeca4 | 4769 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) |
542d6675 KH |
4770 | return 1; |
4771 | } | |
197865e8 | 4772 | else |
542d6675 KH |
4773 | { |
4774 | /* FIXME -- need 62-bit relocation type */ | |
4775 | as_bad (_("62-bit relocation not yet implemented")); | |
4776 | } | |
800eeca4 JW |
4777 | break; |
4778 | ||
4779 | case IA64_OPND_IMMU64: | |
4780 | if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup | |
4781 | || e->X_op == O_subtract) | |
4782 | { | |
4783 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
4784 | fix->code = BFD_RELOC_IA64_IMM64; | |
4785 | if (e->X_op != O_subtract) | |
4786 | { | |
4787 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
4788 | if (e->X_op == O_pseudo_fixup) | |
4789 | e->X_op = O_symbol; | |
4790 | } | |
4791 | ||
4792 | fix->opnd = idesc->operands[index]; | |
4793 | fix->expr = *e; | |
4794 | fix->is_pcrel = 0; | |
4795 | ++CURR_SLOT.num_fixups; | |
4796 | return 1; | |
4797 | } | |
4798 | else if (e->X_op == O_constant) | |
4799 | return 1; | |
4800 | break; | |
4801 | ||
4802 | case IA64_OPND_CCNT5: | |
4803 | case IA64_OPND_CNT5: | |
4804 | case IA64_OPND_CNT6: | |
4805 | case IA64_OPND_CPOS6a: | |
4806 | case IA64_OPND_CPOS6b: | |
4807 | case IA64_OPND_CPOS6c: | |
4808 | case IA64_OPND_IMMU2: | |
4809 | case IA64_OPND_IMMU7a: | |
4810 | case IA64_OPND_IMMU7b: | |
800eeca4 JW |
4811 | case IA64_OPND_IMMU21: |
4812 | case IA64_OPND_IMMU24: | |
4813 | case IA64_OPND_MBTYPE4: | |
4814 | case IA64_OPND_MHTYPE8: | |
4815 | case IA64_OPND_POS6: | |
4816 | bits = operand_width (idesc->operands[index]); | |
4817 | if (e->X_op == O_constant | |
4818 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) | |
4819 | return 1; | |
4820 | break; | |
4821 | ||
bf3ca999 TW |
4822 | case IA64_OPND_IMMU9: |
4823 | bits = operand_width (idesc->operands[index]); | |
4824 | if (e->X_op == O_constant | |
4825 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) | |
542d6675 KH |
4826 | { |
4827 | int lobits = e->X_add_number & 0x3; | |
4828 | if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) | |
4829 | e->X_add_number |= (bfd_vma) 0x3; | |
4830 | return 1; | |
4831 | } | |
bf3ca999 TW |
4832 | break; |
4833 | ||
800eeca4 JW |
4834 | case IA64_OPND_IMM44: |
4835 | /* least 16 bits must be zero */ | |
4836 | if ((e->X_add_number & 0xffff) != 0) | |
542d6675 | 4837 | as_warn (_("lower 16 bits of mask ignored")); |
800eeca4 JW |
4838 | |
4839 | if (e->X_op == O_constant | |
4840 | && ((e->X_add_number >= 0 | |
2434f565 | 4841 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) |
800eeca4 | 4842 | || (e->X_add_number < 0 |
2434f565 | 4843 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) |
542d6675 KH |
4844 | { |
4845 | /* sign-extend */ | |
4846 | if (e->X_add_number >= 0 | |
4847 | && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) | |
4848 | { | |
4849 | e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); | |
4850 | } | |
4851 | return 1; | |
4852 | } | |
800eeca4 JW |
4853 | break; |
4854 | ||
4855 | case IA64_OPND_IMM17: | |
4856 | /* bit 0 is a don't care (pr0 is hardwired to 1) */ | |
4857 | if (e->X_op == O_constant | |
4858 | && ((e->X_add_number >= 0 | |
2434f565 | 4859 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) |
800eeca4 | 4860 | || (e->X_add_number < 0 |
2434f565 | 4861 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) |
542d6675 KH |
4862 | { |
4863 | /* sign-extend */ | |
4864 | if (e->X_add_number >= 0 | |
4865 | && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) | |
4866 | { | |
4867 | e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); | |
4868 | } | |
4869 | return 1; | |
4870 | } | |
800eeca4 JW |
4871 | break; |
4872 | ||
4873 | case IA64_OPND_IMM14: | |
4874 | case IA64_OPND_IMM22: | |
4875 | relocatable = 1; | |
4876 | case IA64_OPND_IMM1: | |
4877 | case IA64_OPND_IMM8: | |
4878 | case IA64_OPND_IMM8U4: | |
4879 | case IA64_OPND_IMM8M1: | |
4880 | case IA64_OPND_IMM8M1U4: | |
4881 | case IA64_OPND_IMM8M1U8: | |
4882 | case IA64_OPND_IMM9a: | |
4883 | case IA64_OPND_IMM9b: | |
4884 | bits = operand_width (idesc->operands[index]); | |
4885 | if (relocatable && (e->X_op == O_symbol | |
4886 | || e->X_op == O_subtract | |
4887 | || e->X_op == O_pseudo_fixup)) | |
4888 | { | |
4889 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
4890 | ||
4891 | if (idesc->operands[index] == IA64_OPND_IMM14) | |
4892 | fix->code = BFD_RELOC_IA64_IMM14; | |
4893 | else | |
4894 | fix->code = BFD_RELOC_IA64_IMM22; | |
4895 | ||
4896 | if (e->X_op != O_subtract) | |
4897 | { | |
4898 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
4899 | if (e->X_op == O_pseudo_fixup) | |
4900 | e->X_op = O_symbol; | |
4901 | } | |
4902 | ||
4903 | fix->opnd = idesc->operands[index]; | |
4904 | fix->expr = *e; | |
4905 | fix->is_pcrel = 0; | |
4906 | ++CURR_SLOT.num_fixups; | |
4907 | return 1; | |
4908 | } | |
4909 | else if (e->X_op != O_constant | |
4910 | && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) | |
4911 | return 0; | |
4912 | ||
4913 | if (opnd == IA64_OPND_IMM8M1U4) | |
4914 | { | |
4915 | /* Zero is not valid for unsigned compares that take an adjusted | |
4916 | constant immediate range. */ | |
4917 | if (e->X_add_number == 0) | |
4918 | return 0; | |
4919 | ||
4920 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
4921 | checks will work. */ | |
4922 | val = e->X_add_number; | |
197865e8 KH |
4923 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
4924 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
4925 | val = ((val << 32) >> 32); |
4926 | ||
4927 | /* Check for 0x100000000. This is valid because | |
4928 | 0x100000000-1 is the same as ((uint32_t) -1). */ | |
4929 | if (val == ((bfd_signed_vma) 1 << 32)) | |
4930 | return 1; | |
4931 | ||
4932 | val = val - 1; | |
4933 | } | |
4934 | else if (opnd == IA64_OPND_IMM8M1U8) | |
4935 | { | |
4936 | /* Zero is not valid for unsigned compares that take an adjusted | |
4937 | constant immediate range. */ | |
4938 | if (e->X_add_number == 0) | |
4939 | return 0; | |
4940 | ||
4941 | /* Check for 0x10000000000000000. */ | |
4942 | if (e->X_op == O_big) | |
4943 | { | |
4944 | if (generic_bignum[0] == 0 | |
4945 | && generic_bignum[1] == 0 | |
4946 | && generic_bignum[2] == 0 | |
4947 | && generic_bignum[3] == 0 | |
4948 | && generic_bignum[4] == 1) | |
4949 | return 1; | |
4950 | else | |
4951 | return 0; | |
4952 | } | |
4953 | else | |
4954 | val = e->X_add_number - 1; | |
4955 | } | |
4956 | else if (opnd == IA64_OPND_IMM8M1) | |
4957 | val = e->X_add_number - 1; | |
4958 | else if (opnd == IA64_OPND_IMM8U4) | |
4959 | { | |
4960 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
4961 | checks will work. */ | |
4962 | val = e->X_add_number; | |
197865e8 KH |
4963 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
4964 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
4965 | val = ((val << 32) >> 32); |
4966 | } | |
4967 | else | |
4968 | val = e->X_add_number; | |
4969 | ||
2434f565 JW |
4970 | if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) |
4971 | || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) | |
800eeca4 JW |
4972 | return 1; |
4973 | break; | |
4974 | ||
4975 | case IA64_OPND_INC3: | |
4976 | /* +/- 1, 4, 8, 16 */ | |
4977 | val = e->X_add_number; | |
4978 | if (val < 0) | |
4979 | val = -val; | |
4980 | if (e->X_op == O_constant | |
4981 | && (val == 1 || val == 4 || val == 8 || val == 16)) | |
4982 | return 1; | |
4983 | break; | |
4984 | ||
4985 | case IA64_OPND_TGT25: | |
4986 | case IA64_OPND_TGT25b: | |
4987 | case IA64_OPND_TGT25c: | |
4988 | case IA64_OPND_TGT64: | |
4989 | if (e->X_op == O_symbol) | |
4990 | { | |
4991 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
4992 | if (opnd == IA64_OPND_TGT25) | |
4993 | fix->code = BFD_RELOC_IA64_PCREL21F; | |
4994 | else if (opnd == IA64_OPND_TGT25b) | |
4995 | fix->code = BFD_RELOC_IA64_PCREL21M; | |
4996 | else if (opnd == IA64_OPND_TGT25c) | |
4997 | fix->code = BFD_RELOC_IA64_PCREL21B; | |
542d6675 | 4998 | else if (opnd == IA64_OPND_TGT64) |
c67e42c9 RH |
4999 | fix->code = BFD_RELOC_IA64_PCREL60B; |
5000 | else | |
5001 | abort (); | |
5002 | ||
800eeca4 JW |
5003 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
5004 | fix->opnd = idesc->operands[index]; | |
5005 | fix->expr = *e; | |
5006 | fix->is_pcrel = 1; | |
5007 | ++CURR_SLOT.num_fixups; | |
5008 | return 1; | |
5009 | } | |
5010 | case IA64_OPND_TAG13: | |
5011 | case IA64_OPND_TAG13b: | |
5012 | switch (e->X_op) | |
5013 | { | |
5014 | case O_constant: | |
5015 | return 1; | |
5016 | ||
5017 | case O_symbol: | |
5018 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5019 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0); | |
5020 | fix->opnd = idesc->operands[index]; | |
5021 | fix->expr = *e; | |
5022 | fix->is_pcrel = 1; | |
5023 | ++CURR_SLOT.num_fixups; | |
5024 | return 1; | |
5025 | ||
5026 | default: | |
5027 | break; | |
5028 | } | |
5029 | break; | |
5030 | ||
5031 | default: | |
5032 | break; | |
5033 | } | |
5034 | return 0; | |
5035 | } | |
5036 | ||
5037 | static int | |
5038 | parse_operand (e) | |
5039 | expressionS *e; | |
5040 | { | |
5041 | int sep = '\0'; | |
5042 | ||
5043 | memset (e, 0, sizeof (*e)); | |
5044 | e->X_op = O_absent; | |
5045 | SKIP_WHITESPACE (); | |
5046 | if (*input_line_pointer != '}') | |
5047 | expression (e); | |
5048 | sep = *input_line_pointer++; | |
5049 | ||
5050 | if (sep == '}') | |
5051 | { | |
5052 | if (!md.manual_bundling) | |
5053 | as_warn ("Found '}' when manual bundling is off"); | |
5054 | else | |
5055 | CURR_SLOT.manual_bundling_off = 1; | |
5056 | md.manual_bundling = 0; | |
5057 | sep = '\0'; | |
5058 | } | |
5059 | return sep; | |
5060 | } | |
5061 | ||
5062 | /* Returns the next entry in the opcode table that matches the one in | |
5063 | IDESC, and frees the entry in IDESC. If no matching entry is | |
197865e8 | 5064 | found, NULL is returned instead. */ |
800eeca4 JW |
5065 | |
5066 | static struct ia64_opcode * | |
5067 | get_next_opcode (struct ia64_opcode *idesc) | |
5068 | { | |
5069 | struct ia64_opcode *next = ia64_find_next_opcode (idesc); | |
5070 | ia64_free_opcode (idesc); | |
5071 | return next; | |
5072 | } | |
5073 | ||
5074 | /* Parse the operands for the opcode and find the opcode variant that | |
5075 | matches the specified operands, or NULL if no match is possible. */ | |
542d6675 KH |
5076 | |
5077 | static struct ia64_opcode * | |
800eeca4 JW |
5078 | parse_operands (idesc) |
5079 | struct ia64_opcode *idesc; | |
5080 | { | |
5081 | int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; | |
5082 | int sep = 0; | |
5083 | enum ia64_opnd expected_operand = IA64_OPND_NIL; | |
5084 | char mnemonic[129]; | |
5085 | char *first_arg = 0, *end, *saved_input_pointer; | |
5086 | unsigned int sof; | |
5087 | ||
5088 | assert (strlen (idesc->name) <= 128); | |
5089 | ||
5090 | strcpy (mnemonic, idesc->name); | |
5091 | if (idesc->operands[2] == IA64_OPND_SOF) | |
5092 | { | |
5093 | /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we | |
5094 | can't parse the first operand until we have parsed the | |
5095 | remaining operands of the "alloc" instruction. */ | |
5096 | SKIP_WHITESPACE (); | |
5097 | first_arg = input_line_pointer; | |
5098 | end = strchr (input_line_pointer, '='); | |
5099 | if (!end) | |
5100 | { | |
5101 | as_bad ("Expected separator `='"); | |
5102 | return 0; | |
5103 | } | |
5104 | input_line_pointer = end + 1; | |
5105 | ++i; | |
5106 | ++num_outputs; | |
5107 | } | |
5108 | ||
5109 | for (; i < NELEMS (CURR_SLOT.opnd); ++i) | |
5110 | { | |
5111 | sep = parse_operand (CURR_SLOT.opnd + i); | |
5112 | if (CURR_SLOT.opnd[i].X_op == O_absent) | |
5113 | break; | |
5114 | ||
5115 | ++num_operands; | |
5116 | ||
5117 | if (sep != '=' && sep != ',') | |
5118 | break; | |
5119 | ||
5120 | if (sep == '=') | |
5121 | { | |
5122 | if (num_outputs > 0) | |
5123 | as_bad ("Duplicate equal sign (=) in instruction"); | |
5124 | else | |
5125 | num_outputs = i + 1; | |
5126 | } | |
5127 | } | |
5128 | if (sep != '\0') | |
5129 | { | |
5130 | as_bad ("Illegal operand separator `%c'", sep); | |
5131 | return 0; | |
5132 | } | |
197865e8 | 5133 | |
800eeca4 JW |
5134 | if (idesc->operands[2] == IA64_OPND_SOF) |
5135 | { | |
5136 | /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ | |
5137 | know (strcmp (idesc->name, "alloc") == 0); | |
5138 | if (num_operands == 5 /* first_arg not included in this count! */ | |
5139 | && CURR_SLOT.opnd[2].X_op == O_constant | |
5140 | && CURR_SLOT.opnd[3].X_op == O_constant | |
5141 | && CURR_SLOT.opnd[4].X_op == O_constant | |
5142 | && CURR_SLOT.opnd[5].X_op == O_constant) | |
5143 | { | |
5144 | sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, | |
5145 | CURR_SLOT.opnd[3].X_add_number, | |
5146 | CURR_SLOT.opnd[4].X_add_number, | |
5147 | CURR_SLOT.opnd[5].X_add_number); | |
5148 | ||
542d6675 | 5149 | /* now we can parse the first arg: */ |
800eeca4 JW |
5150 | saved_input_pointer = input_line_pointer; |
5151 | input_line_pointer = first_arg; | |
5152 | sep = parse_operand (CURR_SLOT.opnd + 0); | |
5153 | if (sep != '=') | |
5154 | --num_outputs; /* force error */ | |
5155 | input_line_pointer = saved_input_pointer; | |
5156 | ||
5157 | CURR_SLOT.opnd[2].X_add_number = sof; | |
5158 | CURR_SLOT.opnd[3].X_add_number | |
5159 | = sof - CURR_SLOT.opnd[4].X_add_number; | |
5160 | CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; | |
5161 | } | |
5162 | } | |
5163 | ||
5164 | highest_unmatched_operand = 0; | |
5165 | expected_operand = idesc->operands[0]; | |
5166 | for (; idesc; idesc = get_next_opcode (idesc)) | |
5167 | { | |
5168 | if (num_outputs != idesc->num_outputs) | |
5169 | continue; /* mismatch in # of outputs */ | |
5170 | ||
5171 | CURR_SLOT.num_fixups = 0; | |
5172 | for (i = 0; i < num_operands && idesc->operands[i]; ++i) | |
5173 | if (!operand_match (idesc, i, CURR_SLOT.opnd + i)) | |
5174 | break; | |
5175 | ||
5176 | if (i != num_operands) | |
5177 | { | |
5178 | if (i > highest_unmatched_operand) | |
5179 | { | |
5180 | highest_unmatched_operand = i; | |
5181 | expected_operand = idesc->operands[i]; | |
5182 | } | |
5183 | continue; | |
5184 | } | |
5185 | ||
5186 | if (num_operands < NELEMS (idesc->operands) | |
5187 | && idesc->operands[num_operands]) | |
5188 | continue; /* mismatch in number of arguments */ | |
5189 | ||
5190 | break; | |
5191 | } | |
5192 | if (!idesc) | |
5193 | { | |
5194 | if (expected_operand) | |
5195 | as_bad ("Operand %u of `%s' should be %s", | |
5196 | highest_unmatched_operand + 1, mnemonic, | |
5197 | elf64_ia64_operands[expected_operand].desc); | |
5198 | else | |
5199 | as_bad ("Operand mismatch"); | |
5200 | return 0; | |
5201 | } | |
5202 | return idesc; | |
5203 | } | |
5204 | ||
88be23ec BS |
5205 | /* Keep track of state necessary to determine whether a NOP is necessary |
5206 | to avoid an erratum in A and B step Itanium chips, and return 1 if we | |
5207 | detect a case where additional NOPs may be necessary. */ | |
5208 | static int | |
5209 | errata_nop_necessary_p (slot, insn_unit) | |
5210 | struct slot *slot; | |
5211 | enum ia64_unit insn_unit; | |
5212 | { | |
5213 | int i; | |
5214 | struct group *this_group = md.last_groups + md.group_idx; | |
5215 | struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; | |
5216 | struct ia64_opcode *idesc = slot->idesc; | |
5217 | ||
5218 | /* Test whether this could be the first insn in a problematic sequence. */ | |
5219 | if (insn_unit == IA64_UNIT_F) | |
5220 | { | |
5221 | for (i = 0; i < idesc->num_outputs; i++) | |
5222 | if (idesc->operands[i] == IA64_OPND_P1 | |
5223 | || idesc->operands[i] == IA64_OPND_P2) | |
5224 | { | |
5225 | int regno = slot->opnd[i].X_add_number - REG_P; | |
3557da92 | 5226 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5227 | if (regno >= 64) |
3557da92 | 5228 | return 0; |
88be23ec BS |
5229 | this_group->p_reg_set[regno] = 1; |
5230 | } | |
5231 | } | |
5232 | ||
5233 | /* Test whether this could be the second insn in a problematic sequence. */ | |
5234 | if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 | |
5235 | && prev_group->p_reg_set[slot->qp_regno]) | |
5236 | { | |
5237 | for (i = 0; i < idesc->num_outputs; i++) | |
5238 | if (idesc->operands[i] == IA64_OPND_R1 | |
5239 | || idesc->operands[i] == IA64_OPND_R2 | |
5240 | || idesc->operands[i] == IA64_OPND_R3) | |
5241 | { | |
5242 | int regno = slot->opnd[i].X_add_number - REG_GR; | |
3557da92 | 5243 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5244 | if (regno >= 128) |
3557da92 | 5245 | return 0; |
88be23ec BS |
5246 | if (strncmp (idesc->name, "add", 3) != 0 |
5247 | && strncmp (idesc->name, "sub", 3) != 0 | |
5248 | && strncmp (idesc->name, "shladd", 6) != 0 | |
5249 | && (idesc->flags & IA64_OPCODE_POSTINC) == 0) | |
5250 | this_group->g_reg_set_conditionally[regno] = 1; | |
5251 | } | |
5252 | } | |
5253 | ||
5254 | /* Test whether this could be the third insn in a problematic sequence. */ | |
5255 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) | |
5256 | { | |
5257 | if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ | |
5258 | idesc->operands[i] == IA64_OPND_R3 | |
5259 | /* For mov indirect. */ | |
5260 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
5261 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
5262 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
5263 | || idesc->operands[i] == IA64_OPND_PKR_R3 | |
5264 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
5265 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
5266 | || idesc->operands[i] == IA64_OPND_MSR_R3 | |
5267 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
5268 | /* For itr. */ | |
5269 | || idesc->operands[i] == IA64_OPND_ITR_R3 | |
5270 | || idesc->operands[i] == IA64_OPND_DTR_R3 | |
5271 | /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ | |
5272 | || idesc->operands[i] == IA64_OPND_MR3) | |
5273 | { | |
5274 | int regno = slot->opnd[i].X_add_number - REG_GR; | |
3557da92 | 5275 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5276 | if (regno >= 128) |
3557da92 | 5277 | return 0; |
88be23ec BS |
5278 | if (idesc->operands[i] == IA64_OPND_R3) |
5279 | { | |
5280 | if (strcmp (idesc->name, "fc") != 0 | |
5281 | && strcmp (idesc->name, "tak") != 0 | |
5282 | && strcmp (idesc->name, "thash") != 0 | |
5283 | && strcmp (idesc->name, "tpa") != 0 | |
5284 | && strcmp (idesc->name, "ttag") != 0 | |
5285 | && strncmp (idesc->name, "ptr", 3) != 0 | |
5286 | && strncmp (idesc->name, "ptc", 3) != 0 | |
5287 | && strncmp (idesc->name, "probe", 5) != 0) | |
5288 | return 0; | |
5289 | } | |
bc805888 | 5290 | if (prev_group->g_reg_set_conditionally[regno]) |
88be23ec BS |
5291 | return 1; |
5292 | } | |
5293 | } | |
5294 | return 0; | |
5295 | } | |
5296 | ||
800eeca4 JW |
5297 | static void |
5298 | build_insn (slot, insnp) | |
5299 | struct slot *slot; | |
5300 | bfd_vma *insnp; | |
5301 | { | |
5302 | const struct ia64_operand *odesc, *o2desc; | |
5303 | struct ia64_opcode *idesc = slot->idesc; | |
5304 | bfd_signed_vma insn, val; | |
5305 | const char *err; | |
5306 | int i; | |
5307 | ||
5308 | insn = idesc->opcode | slot->qp_regno; | |
5309 | ||
5310 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) | |
5311 | { | |
c67e42c9 RH |
5312 | if (slot->opnd[i].X_op == O_register |
5313 | || slot->opnd[i].X_op == O_constant | |
5314 | || slot->opnd[i].X_op == O_index) | |
5315 | val = slot->opnd[i].X_add_number; | |
5316 | else if (slot->opnd[i].X_op == O_big) | |
800eeca4 | 5317 | { |
c67e42c9 RH |
5318 | /* This must be the value 0x10000000000000000. */ |
5319 | assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); | |
5320 | val = 0; | |
5321 | } | |
5322 | else | |
5323 | val = 0; | |
5324 | ||
5325 | switch (idesc->operands[i]) | |
5326 | { | |
5327 | case IA64_OPND_IMMU64: | |
800eeca4 JW |
5328 | *insnp++ = (val >> 22) & 0x1ffffffffffLL; |
5329 | insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) | |
5330 | | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) | |
5331 | | (((val >> 63) & 0x1) << 36)); | |
c67e42c9 RH |
5332 | continue; |
5333 | ||
5334 | case IA64_OPND_IMMU62: | |
542d6675 KH |
5335 | val &= 0x3fffffffffffffffULL; |
5336 | if (val != slot->opnd[i].X_add_number) | |
5337 | as_warn (_("Value truncated to 62 bits")); | |
5338 | *insnp++ = (val >> 21) & 0x1ffffffffffLL; | |
5339 | insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); | |
c67e42c9 | 5340 | continue; |
800eeca4 | 5341 | |
c67e42c9 RH |
5342 | case IA64_OPND_TGT64: |
5343 | val >>= 4; | |
5344 | *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; | |
5345 | insn |= ((((val >> 59) & 0x1) << 36) | |
5346 | | (((val >> 0) & 0xfffff) << 13)); | |
5347 | continue; | |
800eeca4 | 5348 | |
c67e42c9 RH |
5349 | case IA64_OPND_AR3: |
5350 | val -= REG_AR; | |
5351 | break; | |
5352 | ||
5353 | case IA64_OPND_B1: | |
5354 | case IA64_OPND_B2: | |
5355 | val -= REG_BR; | |
5356 | break; | |
5357 | ||
5358 | case IA64_OPND_CR3: | |
5359 | val -= REG_CR; | |
5360 | break; | |
5361 | ||
5362 | case IA64_OPND_F1: | |
5363 | case IA64_OPND_F2: | |
5364 | case IA64_OPND_F3: | |
5365 | case IA64_OPND_F4: | |
5366 | val -= REG_FR; | |
5367 | break; | |
5368 | ||
5369 | case IA64_OPND_P1: | |
5370 | case IA64_OPND_P2: | |
5371 | val -= REG_P; | |
5372 | break; | |
5373 | ||
5374 | case IA64_OPND_R1: | |
5375 | case IA64_OPND_R2: | |
5376 | case IA64_OPND_R3: | |
5377 | case IA64_OPND_R3_2: | |
5378 | case IA64_OPND_CPUID_R3: | |
5379 | case IA64_OPND_DBR_R3: | |
5380 | case IA64_OPND_DTR_R3: | |
5381 | case IA64_OPND_ITR_R3: | |
5382 | case IA64_OPND_IBR_R3: | |
5383 | case IA64_OPND_MR3: | |
5384 | case IA64_OPND_MSR_R3: | |
5385 | case IA64_OPND_PKR_R3: | |
5386 | case IA64_OPND_PMC_R3: | |
5387 | case IA64_OPND_PMD_R3: | |
197865e8 | 5388 | case IA64_OPND_RR_R3: |
c67e42c9 RH |
5389 | val -= REG_GR; |
5390 | break; | |
5391 | ||
5392 | default: | |
5393 | break; | |
5394 | } | |
5395 | ||
5396 | odesc = elf64_ia64_operands + idesc->operands[i]; | |
5397 | err = (*odesc->insert) (odesc, val, &insn); | |
5398 | if (err) | |
5399 | as_bad_where (slot->src_file, slot->src_line, | |
5400 | "Bad operand value: %s", err); | |
5401 | if (idesc->flags & IA64_OPCODE_PSEUDO) | |
5402 | { | |
5403 | if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) | |
5404 | && odesc == elf64_ia64_operands + IA64_OPND_F3) | |
5405 | { | |
5406 | o2desc = elf64_ia64_operands + IA64_OPND_F2; | |
5407 | (*o2desc->insert) (o2desc, val, &insn); | |
800eeca4 | 5408 | } |
c67e42c9 RH |
5409 | if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) |
5410 | && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a | |
5411 | || odesc == elf64_ia64_operands + IA64_OPND_POS6)) | |
800eeca4 | 5412 | { |
c67e42c9 RH |
5413 | o2desc = elf64_ia64_operands + IA64_OPND_LEN6; |
5414 | (*o2desc->insert) (o2desc, 64 - val, &insn); | |
800eeca4 JW |
5415 | } |
5416 | } | |
5417 | } | |
5418 | *insnp = insn; | |
5419 | } | |
5420 | ||
5421 | static void | |
5422 | emit_one_bundle () | |
5423 | { | |
5424 | unsigned int manual_bundling_on = 0, manual_bundling_off = 0; | |
5425 | unsigned int manual_bundling = 0; | |
5426 | enum ia64_unit required_unit, insn_unit = 0; | |
5427 | enum ia64_insn_type type[3], insn_type; | |
5428 | unsigned int template, orig_template; | |
542d6675 | 5429 | bfd_vma insn[3] = { -1, -1, -1 }; |
800eeca4 JW |
5430 | struct ia64_opcode *idesc; |
5431 | int end_of_insn_group = 0, user_template = -1; | |
5432 | int n, i, j, first, curr; | |
2434f565 | 5433 | unw_rec_list *ptr; |
800eeca4 JW |
5434 | bfd_vma t0 = 0, t1 = 0; |
5435 | struct label_fix *lfix; | |
5436 | struct insn_fix *ifix; | |
5437 | char mnemonic[16]; | |
5438 | fixS *fix; | |
5439 | char *f; | |
5440 | ||
5441 | first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; | |
5442 | know (first >= 0 & first < NUM_SLOTS); | |
5443 | n = MIN (3, md.num_slots_in_use); | |
5444 | ||
5445 | /* Determine template: user user_template if specified, best match | |
542d6675 | 5446 | otherwise: */ |
800eeca4 JW |
5447 | |
5448 | if (md.slot[first].user_template >= 0) | |
5449 | user_template = template = md.slot[first].user_template; | |
5450 | else | |
5451 | { | |
032efc85 | 5452 | /* Auto select appropriate template. */ |
800eeca4 JW |
5453 | memset (type, 0, sizeof (type)); |
5454 | curr = first; | |
5455 | for (i = 0; i < n; ++i) | |
5456 | { | |
032efc85 RH |
5457 | if (md.slot[curr].label_fixups && i != 0) |
5458 | break; | |
800eeca4 JW |
5459 | type[i] = md.slot[curr].idesc->type; |
5460 | curr = (curr + 1) % NUM_SLOTS; | |
5461 | } | |
5462 | template = best_template[type[0]][type[1]][type[2]]; | |
5463 | } | |
5464 | ||
542d6675 | 5465 | /* initialize instructions with appropriate nops: */ |
800eeca4 JW |
5466 | for (i = 0; i < 3; ++i) |
5467 | insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; | |
5468 | ||
5469 | f = frag_more (16); | |
5470 | ||
542d6675 | 5471 | /* now fill in slots with as many insns as possible: */ |
800eeca4 JW |
5472 | curr = first; |
5473 | idesc = md.slot[curr].idesc; | |
5474 | end_of_insn_group = 0; | |
5475 | for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) | |
5476 | { | |
e0c9811a JW |
5477 | /* Set the slot number for prologue/body records now as those |
5478 | refer to the current point, not the point after the | |
542d6675 | 5479 | instruction has been issued: */ |
10850f29 JW |
5480 | /* Don't try to delete prologue/body records here, as that will cause |
5481 | them to also be deleted from the master list of unwind records. */ | |
e0c9811a | 5482 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
10850f29 JW |
5483 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
5484 | || ptr->r.type == body) | |
f5a30c2e JW |
5485 | { |
5486 | ptr->slot_number = (unsigned long) f + i; | |
5487 | ptr->slot_frag = frag_now; | |
5488 | } | |
e0c9811a | 5489 | |
800eeca4 JW |
5490 | if (idesc->flags & IA64_OPCODE_SLOT2) |
5491 | { | |
5492 | if (manual_bundling && i != 2) | |
5493 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5494 | "`%s' must be last in bundle", idesc->name); | |
5495 | else | |
5496 | i = 2; | |
5497 | } | |
5498 | if (idesc->flags & IA64_OPCODE_LAST) | |
5499 | { | |
2434f565 JW |
5500 | int required_slot; |
5501 | unsigned int required_template; | |
800eeca4 JW |
5502 | |
5503 | /* If we need a stop bit after an M slot, our only choice is | |
5504 | template 5 (M;;MI). If we need a stop bit after a B | |
5505 | slot, our only choice is to place it at the end of the | |
5506 | bundle, because the only available templates are MIB, | |
5507 | MBB, BBB, MMB, and MFB. We don't handle anything other | |
5508 | than M and B slots because these are the only kind of | |
5509 | instructions that can have the IA64_OPCODE_LAST bit set. */ | |
5510 | required_template = template; | |
5511 | switch (idesc->type) | |
5512 | { | |
5513 | case IA64_TYPE_M: | |
5514 | required_slot = 0; | |
5515 | required_template = 5; | |
5516 | break; | |
5517 | ||
5518 | case IA64_TYPE_B: | |
5519 | required_slot = 2; | |
5520 | break; | |
5521 | ||
5522 | default: | |
5523 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5524 | "Internal error: don't know how to force %s to end" | |
5525 | "of instruction group", idesc->name); | |
5526 | required_slot = i; | |
5527 | break; | |
5528 | } | |
5529 | if (manual_bundling && i != required_slot) | |
5530 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5531 | "`%s' must be last in instruction group", | |
5532 | idesc->name); | |
5533 | if (required_slot < i) | |
5534 | /* Can't fit this instruction. */ | |
5535 | break; | |
5536 | ||
5537 | i = required_slot; | |
5538 | if (required_template != template) | |
5539 | { | |
5540 | /* If we switch the template, we need to reset the NOPs | |
5541 | after slot i. The slot-types of the instructions ahead | |
5542 | of i never change, so we don't need to worry about | |
5543 | changing NOPs in front of this slot. */ | |
5544 | for (j = i; j < 3; ++j) | |
5545 | insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; | |
5546 | } | |
5547 | template = required_template; | |
5548 | } | |
5549 | if (curr != first && md.slot[curr].label_fixups) | |
5550 | { | |
5551 | if (manual_bundling_on) | |
5552 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5553 | "Label must be first in a bundle"); | |
5554 | /* This insn must go into the first slot of a bundle. */ | |
5555 | break; | |
5556 | } | |
5557 | ||
5558 | manual_bundling_on = md.slot[curr].manual_bundling_on; | |
5559 | manual_bundling_off = md.slot[curr].manual_bundling_off; | |
5560 | ||
5561 | if (manual_bundling_on) | |
5562 | { | |
5563 | if (curr == first) | |
5564 | manual_bundling = 1; | |
5565 | else | |
5566 | break; /* need to start a new bundle */ | |
5567 | } | |
5568 | ||
5569 | if (end_of_insn_group && md.num_slots_in_use >= 1) | |
5570 | { | |
5571 | /* We need an instruction group boundary in the middle of a | |
5572 | bundle. See if we can switch to an other template with | |
5573 | an appropriate boundary. */ | |
5574 | ||
5575 | orig_template = template; | |
5576 | if (i == 1 && (user_template == 4 | |
5577 | || (user_template < 0 | |
5578 | && (ia64_templ_desc[template].exec_unit[0] | |
5579 | == IA64_UNIT_M)))) | |
5580 | { | |
5581 | template = 5; | |
5582 | end_of_insn_group = 0; | |
5583 | } | |
5584 | else if (i == 2 && (user_template == 0 | |
5585 | || (user_template < 0 | |
5586 | && (ia64_templ_desc[template].exec_unit[1] | |
5587 | == IA64_UNIT_I))) | |
5588 | /* This test makes sure we don't switch the template if | |
5589 | the next instruction is one that needs to be first in | |
5590 | an instruction group. Since all those instructions are | |
5591 | in the M group, there is no way such an instruction can | |
5592 | fit in this bundle even if we switch the template. The | |
5593 | reason we have to check for this is that otherwise we | |
5594 | may end up generating "MI;;I M.." which has the deadly | |
5595 | effect that the second M instruction is no longer the | |
5596 | first in the bundle! --davidm 99/12/16 */ | |
5597 | && (idesc->flags & IA64_OPCODE_FIRST) == 0) | |
5598 | { | |
5599 | template = 1; | |
5600 | end_of_insn_group = 0; | |
5601 | } | |
5602 | else if (curr != first) | |
5603 | /* can't fit this insn */ | |
5604 | break; | |
5605 | ||
5606 | if (template != orig_template) | |
5607 | /* if we switch the template, we need to reset the NOPs | |
5608 | after slot i. The slot-types of the instructions ahead | |
5609 | of i never change, so we don't need to worry about | |
5610 | changing NOPs in front of this slot. */ | |
5611 | for (j = i; j < 3; ++j) | |
5612 | insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; | |
5613 | } | |
5614 | required_unit = ia64_templ_desc[template].exec_unit[i]; | |
5615 | ||
542d6675 | 5616 | /* resolve dynamic opcodes such as "break" and "nop": */ |
800eeca4 JW |
5617 | if (idesc->type == IA64_TYPE_DYN) |
5618 | { | |
5619 | if ((strcmp (idesc->name, "nop") == 0) | |
5620 | || (strcmp (idesc->name, "break") == 0)) | |
5621 | insn_unit = required_unit; | |
5622 | else if (strcmp (idesc->name, "chk.s") == 0) | |
5623 | { | |
5624 | insn_unit = IA64_UNIT_M; | |
5625 | if (required_unit == IA64_UNIT_I) | |
5626 | insn_unit = IA64_UNIT_I; | |
5627 | } | |
5628 | else | |
5629 | as_fatal ("emit_one_bundle: unexpected dynamic op"); | |
5630 | ||
5631 | sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); | |
3d56ab85 | 5632 | ia64_free_opcode (idesc); |
800eeca4 JW |
5633 | md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); |
5634 | #if 0 | |
5635 | know (!idesc->next); /* no resolved dynamic ops have collisions */ | |
5636 | #endif | |
5637 | } | |
5638 | else | |
5639 | { | |
5640 | insn_type = idesc->type; | |
5641 | insn_unit = IA64_UNIT_NIL; | |
5642 | switch (insn_type) | |
5643 | { | |
5644 | case IA64_TYPE_A: | |
5645 | if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) | |
5646 | insn_unit = required_unit; | |
5647 | break; | |
542d6675 | 5648 | case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; |
800eeca4 JW |
5649 | case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; |
5650 | case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; | |
5651 | case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; | |
5652 | case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; | |
5653 | default: break; | |
5654 | } | |
5655 | } | |
5656 | ||
5657 | if (insn_unit != required_unit) | |
5658 | { | |
5659 | if (required_unit == IA64_UNIT_L | |
542d6675 | 5660 | && insn_unit == IA64_UNIT_I |
800eeca4 JW |
5661 | && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) |
5662 | { | |
5663 | /* we got ourselves an MLX template but the current | |
197865e8 | 5664 | instruction isn't an X-unit, or an I-unit instruction |
800eeca4 JW |
5665 | that can go into the X slot of an MLX template. Duh. */ |
5666 | if (md.num_slots_in_use >= NUM_SLOTS) | |
5667 | { | |
5668 | as_bad_where (md.slot[curr].src_file, | |
5669 | md.slot[curr].src_line, | |
5670 | "`%s' can't go in X slot of " | |
5671 | "MLX template", idesc->name); | |
542d6675 | 5672 | /* drop this insn so we don't livelock: */ |
800eeca4 JW |
5673 | --md.num_slots_in_use; |
5674 | } | |
5675 | break; | |
5676 | } | |
5677 | continue; /* try next slot */ | |
5678 | } | |
5679 | ||
800eeca4 JW |
5680 | { |
5681 | bfd_vma addr; | |
5682 | ||
f1bcba5b | 5683 | addr = frag_now->fr_address + frag_now_fix () - 16 + i; |
800eeca4 JW |
5684 | dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); |
5685 | } | |
5686 | ||
88be23ec BS |
5687 | if (errata_nop_necessary_p (md.slot + curr, insn_unit)) |
5688 | as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); | |
5689 | ||
800eeca4 JW |
5690 | build_insn (md.slot + curr, insn + i); |
5691 | ||
10850f29 JW |
5692 | /* Set slot counts for non prologue/body unwind records. */ |
5693 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) | |
5694 | if (ptr->r.type != prologue && ptr->r.type != prologue_gr | |
5695 | && ptr->r.type != body) | |
f5a30c2e JW |
5696 | { |
5697 | ptr->slot_number = (unsigned long) f + i; | |
5698 | ptr->slot_frag = frag_now; | |
5699 | } | |
10850f29 | 5700 | md.slot[curr].unwind_record = NULL; |
10850f29 | 5701 | |
800eeca4 JW |
5702 | if (required_unit == IA64_UNIT_L) |
5703 | { | |
5704 | know (i == 1); | |
5705 | /* skip one slot for long/X-unit instructions */ | |
5706 | ++i; | |
5707 | } | |
5708 | --md.num_slots_in_use; | |
5709 | ||
542d6675 | 5710 | /* now is a good time to fix up the labels for this insn: */ |
800eeca4 JW |
5711 | for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) |
5712 | { | |
5713 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16); | |
5714 | symbol_set_frag (lfix->sym, frag_now); | |
5715 | } | |
f1bcba5b JW |
5716 | /* and fix up the tags also. */ |
5717 | for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) | |
5718 | { | |
5719 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); | |
5720 | symbol_set_frag (lfix->sym, frag_now); | |
5721 | } | |
800eeca4 JW |
5722 | |
5723 | for (j = 0; j < md.slot[curr].num_fixups; ++j) | |
5724 | { | |
5725 | ifix = md.slot[curr].fixup + j; | |
5a080f89 | 5726 | fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, |
800eeca4 JW |
5727 | &ifix->expr, ifix->is_pcrel, ifix->code); |
5728 | fix->tc_fix_data.opnd = ifix->opnd; | |
5729 | fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); | |
5730 | fix->fx_file = md.slot[curr].src_file; | |
5731 | fix->fx_line = md.slot[curr].src_line; | |
5732 | } | |
5733 | ||
5734 | end_of_insn_group = md.slot[curr].end_of_insn_group; | |
5735 | ||
88be23ec BS |
5736 | if (end_of_insn_group) |
5737 | { | |
5738 | md.group_idx = (md.group_idx + 1) % 3; | |
5739 | memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); | |
5740 | } | |
5741 | ||
542d6675 | 5742 | /* clear slot: */ |
800eeca4 JW |
5743 | ia64_free_opcode (md.slot[curr].idesc); |
5744 | memset (md.slot + curr, 0, sizeof (md.slot[curr])); | |
5745 | md.slot[curr].user_template = -1; | |
5746 | ||
5747 | if (manual_bundling_off) | |
5748 | { | |
5749 | manual_bundling = 0; | |
5750 | break; | |
5751 | } | |
5752 | curr = (curr + 1) % NUM_SLOTS; | |
5753 | idesc = md.slot[curr].idesc; | |
5754 | } | |
5755 | if (manual_bundling) | |
5756 | { | |
5757 | if (md.num_slots_in_use > 0) | |
5758 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5759 | "`%s' does not fit into %s template", | |
5760 | idesc->name, ia64_templ_desc[template].name); | |
5761 | else | |
5762 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5763 | "Missing '}' at end of file"); | |
5764 | } | |
5765 | know (md.num_slots_in_use < NUM_SLOTS); | |
5766 | ||
5767 | t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); | |
5768 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
5769 | ||
44f5c83a JW |
5770 | number_to_chars_littleendian (f + 0, t0, 8); |
5771 | number_to_chars_littleendian (f + 8, t1, 8); | |
f5a30c2e JW |
5772 | |
5773 | unwind.next_slot_number = (unsigned long) f + 16; | |
5774 | unwind.next_slot_frag = frag_now; | |
800eeca4 JW |
5775 | } |
5776 | ||
5777 | int | |
5778 | md_parse_option (c, arg) | |
5779 | int c; | |
5780 | char *arg; | |
5781 | { | |
800eeca4 JW |
5782 | switch (c) |
5783 | { | |
c43c2cc5 | 5784 | /* Switches from the Intel assembler. */ |
44f5c83a | 5785 | case 'm': |
800eeca4 JW |
5786 | if (strcmp (arg, "ilp64") == 0 |
5787 | || strcmp (arg, "lp64") == 0 | |
5788 | || strcmp (arg, "p64") == 0) | |
5789 | { | |
5790 | md.flags |= EF_IA_64_ABI64; | |
5791 | } | |
5792 | else if (strcmp (arg, "ilp32") == 0) | |
5793 | { | |
5794 | md.flags &= ~EF_IA_64_ABI64; | |
5795 | } | |
5796 | else if (strcmp (arg, "le") == 0) | |
5797 | { | |
5798 | md.flags &= ~EF_IA_64_BE; | |
5799 | } | |
5800 | else if (strcmp (arg, "be") == 0) | |
5801 | { | |
5802 | md.flags |= EF_IA_64_BE; | |
5803 | } | |
5804 | else | |
5805 | return 0; | |
5806 | break; | |
5807 | ||
5808 | case 'N': | |
5809 | if (strcmp (arg, "so") == 0) | |
5810 | { | |
542d6675 | 5811 | /* Suppress signon message. */ |
800eeca4 JW |
5812 | } |
5813 | else if (strcmp (arg, "pi") == 0) | |
5814 | { | |
5815 | /* Reject privileged instructions. FIXME */ | |
5816 | } | |
5817 | else if (strcmp (arg, "us") == 0) | |
5818 | { | |
5819 | /* Allow union of signed and unsigned range. FIXME */ | |
5820 | } | |
5821 | else if (strcmp (arg, "close_fcalls") == 0) | |
5822 | { | |
5823 | /* Do not resolve global function calls. */ | |
5824 | } | |
5825 | else | |
5826 | return 0; | |
5827 | break; | |
5828 | ||
5829 | case 'C': | |
5830 | /* temp[="prefix"] Insert temporary labels into the object file | |
5831 | symbol table prefixed by "prefix". | |
5832 | Default prefix is ":temp:". | |
5833 | */ | |
5834 | break; | |
5835 | ||
5836 | case 'a': | |
800eeca4 JW |
5837 | /* indirect=<tgt> Assume unannotated indirect branches behavior |
5838 | according to <tgt> -- | |
5839 | exit: branch out from the current context (default) | |
5840 | labels: all labels in context may be branch targets | |
5841 | */ | |
85b40035 L |
5842 | if (strncmp (arg, "indirect=", 9) != 0) |
5843 | return 0; | |
800eeca4 JW |
5844 | break; |
5845 | ||
5846 | case 'x': | |
5847 | /* -X conflicts with an ignored option, use -x instead */ | |
5848 | md.detect_dv = 1; | |
5849 | if (!arg || strcmp (arg, "explicit") == 0) | |
542d6675 KH |
5850 | { |
5851 | /* set default mode to explicit */ | |
5852 | md.default_explicit_mode = 1; | |
5853 | break; | |
5854 | } | |
800eeca4 | 5855 | else if (strcmp (arg, "auto") == 0) |
542d6675 KH |
5856 | { |
5857 | md.default_explicit_mode = 0; | |
5858 | } | |
800eeca4 | 5859 | else if (strcmp (arg, "debug") == 0) |
542d6675 KH |
5860 | { |
5861 | md.debug_dv = 1; | |
5862 | } | |
800eeca4 | 5863 | else if (strcmp (arg, "debugx") == 0) |
542d6675 KH |
5864 | { |
5865 | md.default_explicit_mode = 1; | |
5866 | md.debug_dv = 1; | |
5867 | } | |
800eeca4 | 5868 | else |
542d6675 KH |
5869 | { |
5870 | as_bad (_("Unrecognized option '-x%s'"), arg); | |
5871 | } | |
800eeca4 JW |
5872 | break; |
5873 | ||
5874 | case 'S': | |
5875 | /* nops Print nops statistics. */ | |
5876 | break; | |
5877 | ||
c43c2cc5 JW |
5878 | /* GNU specific switches for gcc. */ |
5879 | case OPTION_MCONSTANT_GP: | |
5880 | md.flags |= EF_IA_64_CONS_GP; | |
5881 | break; | |
5882 | ||
5883 | case OPTION_MAUTO_PIC: | |
5884 | md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; | |
5885 | break; | |
5886 | ||
800eeca4 JW |
5887 | default: |
5888 | return 0; | |
5889 | } | |
5890 | ||
5891 | return 1; | |
5892 | } | |
5893 | ||
5894 | void | |
5895 | md_show_usage (stream) | |
5896 | FILE *stream; | |
5897 | { | |
542d6675 | 5898 | fputs (_("\ |
800eeca4 | 5899 | IA-64 options:\n\ |
44f5c83a JW |
5900 | -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ |
5901 | -mle | -mbe select little- or big-endian byte order (default -mle)\n\ | |
800eeca4 JW |
5902 | -x | -xexplicit turn on dependency violation checking (default)\n\ |
5903 | -xauto automagically remove dependency violations\n\ | |
5904 | -xdebug debug dependency violation checker\n"), | |
5905 | stream); | |
5906 | } | |
5907 | ||
44576e1f RH |
5908 | /* Return true if TYPE fits in TEMPL at SLOT. */ |
5909 | ||
5910 | static int | |
800eeca4 JW |
5911 | match (int templ, int type, int slot) |
5912 | { | |
5913 | enum ia64_unit unit; | |
5914 | int result; | |
5915 | ||
5916 | unit = ia64_templ_desc[templ].exec_unit[slot]; | |
5917 | switch (type) | |
5918 | { | |
5919 | case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ | |
5920 | case IA64_TYPE_A: | |
5921 | result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); | |
5922 | break; | |
5923 | case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; | |
5924 | case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; | |
5925 | case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; | |
5926 | case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; | |
5927 | case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; | |
5928 | default: result = 0; break; | |
5929 | } | |
5930 | return result; | |
5931 | } | |
5932 | ||
44576e1f RH |
5933 | /* Add a bit of extra goodness if a nop of type F or B would fit |
5934 | in TEMPL at SLOT. */ | |
5935 | ||
5936 | static inline int | |
5937 | extra_goodness (int templ, int slot) | |
5938 | { | |
ebeeafe6 | 5939 | if (slot == 1 && match (templ, IA64_TYPE_F, slot)) |
44576e1f | 5940 | return 2; |
ebeeafe6 | 5941 | if (slot == 2 && match (templ, IA64_TYPE_B, slot)) |
44576e1f RH |
5942 | return 1; |
5943 | return 0; | |
5944 | } | |
5945 | ||
800eeca4 JW |
5946 | /* This function is called once, at assembler startup time. It sets |
5947 | up all the tables, etc. that the MD part of the assembler will need | |
5948 | that can be determined before arguments are parsed. */ | |
5949 | void | |
5950 | md_begin () | |
5951 | { | |
44f5c83a | 5952 | int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; |
800eeca4 JW |
5953 | const char *err; |
5954 | char name[8]; | |
5955 | ||
5956 | md.auto_align = 1; | |
5957 | md.explicit_mode = md.default_explicit_mode; | |
5958 | ||
5959 | bfd_set_section_alignment (stdoutput, text_section, 4); | |
5960 | ||
44f5c83a | 5961 | target_big_endian = TARGET_BYTES_BIG_ENDIAN; |
800eeca4 | 5962 | pseudo_func[FUNC_FPTR_RELATIVE].u.sym = |
542d6675 KH |
5963 | symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, |
5964 | &zero_address_frag); | |
800eeca4 JW |
5965 | |
5966 | pseudo_func[FUNC_GP_RELATIVE].u.sym = | |
542d6675 KH |
5967 | symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, |
5968 | &zero_address_frag); | |
800eeca4 JW |
5969 | |
5970 | pseudo_func[FUNC_LT_RELATIVE].u.sym = | |
542d6675 KH |
5971 | symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, |
5972 | &zero_address_frag); | |
800eeca4 | 5973 | |
c67e42c9 | 5974 | pseudo_func[FUNC_PC_RELATIVE].u.sym = |
542d6675 KH |
5975 | symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, |
5976 | &zero_address_frag); | |
c67e42c9 | 5977 | |
800eeca4 | 5978 | pseudo_func[FUNC_PLT_RELATIVE].u.sym = |
542d6675 KH |
5979 | symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, |
5980 | &zero_address_frag); | |
800eeca4 JW |
5981 | |
5982 | pseudo_func[FUNC_SEC_RELATIVE].u.sym = | |
542d6675 KH |
5983 | symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, |
5984 | &zero_address_frag); | |
800eeca4 JW |
5985 | |
5986 | pseudo_func[FUNC_SEG_RELATIVE].u.sym = | |
542d6675 KH |
5987 | symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, |
5988 | &zero_address_frag); | |
800eeca4 JW |
5989 | |
5990 | pseudo_func[FUNC_LTV_RELATIVE].u.sym = | |
542d6675 KH |
5991 | symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, |
5992 | &zero_address_frag); | |
800eeca4 JW |
5993 | |
5994 | pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = | |
542d6675 KH |
5995 | symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, |
5996 | &zero_address_frag); | |
800eeca4 | 5997 | |
197865e8 | 5998 | /* Compute the table of best templates. We compute goodness as a |
44576e1f RH |
5999 | base 4 value, in which each match counts for 3, each F counts |
6000 | for 2, each B counts for 1. This should maximize the number of | |
6001 | F and B nops in the chosen bundles, which is good because these | |
6002 | pipelines are least likely to be overcommitted. */ | |
800eeca4 JW |
6003 | for (i = 0; i < IA64_NUM_TYPES; ++i) |
6004 | for (j = 0; j < IA64_NUM_TYPES; ++j) | |
6005 | for (k = 0; k < IA64_NUM_TYPES; ++k) | |
6006 | { | |
6007 | best = 0; | |
6008 | for (t = 0; t < NELEMS (ia64_templ_desc); ++t) | |
6009 | { | |
6010 | goodness = 0; | |
6011 | if (match (t, i, 0)) | |
6012 | { | |
6013 | if (match (t, j, 1)) | |
6014 | { | |
6015 | if (match (t, k, 2)) | |
44576e1f | 6016 | goodness = 3 + 3 + 3; |
800eeca4 | 6017 | else |
44576e1f | 6018 | goodness = 3 + 3 + extra_goodness (t, 2); |
800eeca4 JW |
6019 | } |
6020 | else if (match (t, j, 2)) | |
44576e1f | 6021 | goodness = 3 + 3 + extra_goodness (t, 1); |
800eeca4 | 6022 | else |
44576e1f RH |
6023 | { |
6024 | goodness = 3; | |
6025 | goodness += extra_goodness (t, 1); | |
6026 | goodness += extra_goodness (t, 2); | |
6027 | } | |
800eeca4 JW |
6028 | } |
6029 | else if (match (t, i, 1)) | |
6030 | { | |
6031 | if (match (t, j, 2)) | |
44576e1f | 6032 | goodness = 3 + 3; |
800eeca4 | 6033 | else |
44576e1f | 6034 | goodness = 3 + extra_goodness (t, 2); |
800eeca4 JW |
6035 | } |
6036 | else if (match (t, i, 2)) | |
44576e1f | 6037 | goodness = 3 + extra_goodness (t, 1); |
800eeca4 JW |
6038 | |
6039 | if (goodness > best) | |
6040 | { | |
6041 | best = goodness; | |
6042 | best_template[i][j][k] = t; | |
6043 | } | |
6044 | } | |
6045 | } | |
6046 | ||
6047 | for (i = 0; i < NUM_SLOTS; ++i) | |
6048 | md.slot[i].user_template = -1; | |
6049 | ||
6050 | md.pseudo_hash = hash_new (); | |
6051 | for (i = 0; i < NELEMS (pseudo_opcode); ++i) | |
6052 | { | |
6053 | err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, | |
6054 | (void *) (pseudo_opcode + i)); | |
6055 | if (err) | |
6056 | as_fatal ("ia64.md_begin: can't hash `%s': %s", | |
6057 | pseudo_opcode[i].name, err); | |
6058 | } | |
6059 | ||
6060 | md.reg_hash = hash_new (); | |
6061 | md.dynreg_hash = hash_new (); | |
6062 | md.const_hash = hash_new (); | |
6063 | md.entry_hash = hash_new (); | |
6064 | ||
542d6675 | 6065 | /* general registers: */ |
800eeca4 JW |
6066 | |
6067 | total = 128; | |
6068 | for (i = 0; i < total; ++i) | |
6069 | { | |
6070 | sprintf (name, "r%d", i - REG_GR); | |
6071 | md.regsym[i] = declare_register (name, i); | |
6072 | } | |
6073 | ||
542d6675 | 6074 | /* floating point registers: */ |
800eeca4 JW |
6075 | total += 128; |
6076 | for (; i < total; ++i) | |
6077 | { | |
6078 | sprintf (name, "f%d", i - REG_FR); | |
6079 | md.regsym[i] = declare_register (name, i); | |
6080 | } | |
6081 | ||
542d6675 | 6082 | /* application registers: */ |
800eeca4 JW |
6083 | total += 128; |
6084 | ar_base = i; | |
6085 | for (; i < total; ++i) | |
6086 | { | |
6087 | sprintf (name, "ar%d", i - REG_AR); | |
6088 | md.regsym[i] = declare_register (name, i); | |
6089 | } | |
6090 | ||
542d6675 | 6091 | /* control registers: */ |
800eeca4 JW |
6092 | total += 128; |
6093 | cr_base = i; | |
6094 | for (; i < total; ++i) | |
6095 | { | |
6096 | sprintf (name, "cr%d", i - REG_CR); | |
6097 | md.regsym[i] = declare_register (name, i); | |
6098 | } | |
6099 | ||
542d6675 | 6100 | /* predicate registers: */ |
800eeca4 JW |
6101 | total += 64; |
6102 | for (; i < total; ++i) | |
6103 | { | |
6104 | sprintf (name, "p%d", i - REG_P); | |
6105 | md.regsym[i] = declare_register (name, i); | |
6106 | } | |
6107 | ||
542d6675 | 6108 | /* branch registers: */ |
800eeca4 JW |
6109 | total += 8; |
6110 | for (; i < total; ++i) | |
6111 | { | |
6112 | sprintf (name, "b%d", i - REG_BR); | |
6113 | md.regsym[i] = declare_register (name, i); | |
6114 | } | |
6115 | ||
6116 | md.regsym[REG_IP] = declare_register ("ip", REG_IP); | |
6117 | md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); | |
6118 | md.regsym[REG_PR] = declare_register ("pr", REG_PR); | |
6119 | md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); | |
6120 | md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); | |
6121 | md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); | |
6122 | md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); | |
6123 | ||
6124 | for (i = 0; i < NELEMS (indirect_reg); ++i) | |
6125 | { | |
6126 | regnum = indirect_reg[i].regnum; | |
6127 | md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); | |
6128 | } | |
6129 | ||
542d6675 | 6130 | /* define synonyms for application registers: */ |
800eeca4 JW |
6131 | for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) |
6132 | md.regsym[i] = declare_register (ar[i - REG_AR].name, | |
6133 | REG_AR + ar[i - REG_AR].regnum); | |
6134 | ||
542d6675 | 6135 | /* define synonyms for control registers: */ |
800eeca4 JW |
6136 | for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) |
6137 | md.regsym[i] = declare_register (cr[i - REG_CR].name, | |
6138 | REG_CR + cr[i - REG_CR].regnum); | |
6139 | ||
6140 | declare_register ("gp", REG_GR + 1); | |
6141 | declare_register ("sp", REG_GR + 12); | |
6142 | declare_register ("rp", REG_BR + 0); | |
6143 | ||
542d6675 | 6144 | /* pseudo-registers used to specify unwind info: */ |
e0c9811a JW |
6145 | declare_register ("psp", REG_PSP); |
6146 | ||
800eeca4 JW |
6147 | declare_register_set ("ret", 4, REG_GR + 8); |
6148 | declare_register_set ("farg", 8, REG_FR + 8); | |
6149 | declare_register_set ("fret", 8, REG_FR + 8); | |
6150 | ||
6151 | for (i = 0; i < NELEMS (const_bits); ++i) | |
6152 | { | |
6153 | err = hash_insert (md.const_hash, const_bits[i].name, | |
6154 | (PTR) (const_bits + i)); | |
6155 | if (err) | |
6156 | as_fatal ("Inserting \"%s\" into constant hash table failed: %s", | |
6157 | name, err); | |
6158 | } | |
6159 | ||
44f5c83a JW |
6160 | /* Set the architecture and machine depending on defaults and command line |
6161 | options. */ | |
6162 | if (md.flags & EF_IA_64_ABI64) | |
6163 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); | |
6164 | else | |
6165 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); | |
6166 | ||
6167 | if (! ok) | |
6168 | as_warn (_("Could not set architecture and machine")); | |
800eeca4 JW |
6169 | |
6170 | md.mem_offset.hint = 0; | |
6171 | md.path = 0; | |
6172 | md.maxpaths = 0; | |
6173 | md.entry_labels = NULL; | |
6174 | } | |
6175 | ||
44f5c83a JW |
6176 | /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin |
6177 | because that is called after md_parse_option which is where we do the | |
6178 | dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the | |
6179 | default endianness. */ | |
6180 | ||
6181 | void | |
6182 | ia64_init (argc, argv) | |
2434f565 JW |
6183 | int argc ATTRIBUTE_UNUSED; |
6184 | char **argv ATTRIBUTE_UNUSED; | |
44f5c83a JW |
6185 | { |
6186 | md.flags = EF_IA_64_ABI64; | |
6187 | if (TARGET_BYTES_BIG_ENDIAN) | |
6188 | md.flags |= EF_IA_64_BE; | |
6189 | } | |
6190 | ||
6191 | /* Return a string for the target object file format. */ | |
6192 | ||
6193 | const char * | |
6194 | ia64_target_format () | |
6195 | { | |
6196 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
6197 | { | |
72a76794 JW |
6198 | if (md.flags & EF_IA_64_BE) |
6199 | { | |
6200 | if (md.flags & EF_IA_64_ABI64) | |
6201 | return "elf64-ia64-big"; | |
6202 | else | |
6203 | return "elf32-ia64-big"; | |
6204 | } | |
44f5c83a | 6205 | else |
72a76794 JW |
6206 | { |
6207 | if (md.flags & EF_IA_64_ABI64) | |
6208 | return "elf64-ia64-little"; | |
6209 | else | |
6210 | return "elf32-ia64-little"; | |
6211 | } | |
44f5c83a JW |
6212 | } |
6213 | else | |
6214 | return "unknown-format"; | |
6215 | } | |
6216 | ||
800eeca4 JW |
6217 | void |
6218 | ia64_end_of_source () | |
6219 | { | |
542d6675 | 6220 | /* terminate insn group upon reaching end of file: */ |
800eeca4 JW |
6221 | insn_group_break (1, 0, 0); |
6222 | ||
542d6675 | 6223 | /* emits slots we haven't written yet: */ |
800eeca4 JW |
6224 | ia64_flush_insns (); |
6225 | ||
6226 | bfd_set_private_flags (stdoutput, md.flags); | |
6227 | ||
800eeca4 JW |
6228 | md.mem_offset.hint = 0; |
6229 | } | |
6230 | ||
6231 | void | |
6232 | ia64_start_line () | |
6233 | { | |
f1bcba5b JW |
6234 | if (md.qp.X_op == O_register) |
6235 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
6236 | md.qp.X_op = O_absent; |
6237 | ||
6238 | if (ignore_input ()) | |
6239 | return; | |
6240 | ||
6241 | if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') | |
6242 | { | |
6243 | if (md.detect_dv && !md.explicit_mode) | |
542d6675 | 6244 | as_warn (_("Explicit stops are ignored in auto mode")); |
800eeca4 | 6245 | else |
542d6675 | 6246 | insn_group_break (1, 0, 0); |
800eeca4 JW |
6247 | } |
6248 | } | |
6249 | ||
f1bcba5b JW |
6250 | /* This is a hook for ia64_frob_label, so that it can distinguish tags from |
6251 | labels. */ | |
6252 | static int defining_tag = 0; | |
6253 | ||
800eeca4 JW |
6254 | int |
6255 | ia64_unrecognized_line (ch) | |
6256 | int ch; | |
6257 | { | |
6258 | switch (ch) | |
6259 | { | |
6260 | case '(': | |
6261 | expression (&md.qp); | |
6262 | if (*input_line_pointer++ != ')') | |
6263 | { | |
6264 | as_bad ("Expected ')'"); | |
6265 | return 0; | |
6266 | } | |
6267 | if (md.qp.X_op != O_register) | |
6268 | { | |
6269 | as_bad ("Qualifying predicate expected"); | |
6270 | return 0; | |
6271 | } | |
6272 | if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) | |
6273 | { | |
6274 | as_bad ("Predicate register expected"); | |
6275 | return 0; | |
6276 | } | |
6277 | return 1; | |
6278 | ||
6279 | case '{': | |
6280 | if (md.manual_bundling) | |
6281 | as_warn ("Found '{' when manual bundling is already turned on"); | |
6282 | else | |
6283 | CURR_SLOT.manual_bundling_on = 1; | |
6284 | md.manual_bundling = 1; | |
6285 | ||
542d6675 KH |
6286 | /* Bundling is only acceptable in explicit mode |
6287 | or when in default automatic mode. */ | |
800eeca4 | 6288 | if (md.detect_dv && !md.explicit_mode) |
542d6675 KH |
6289 | { |
6290 | if (!md.mode_explicitly_set | |
6291 | && !md.default_explicit_mode) | |
6292 | dot_dv_mode ('E'); | |
6293 | else | |
6294 | as_warn (_("Found '{' after explicit switch to automatic mode")); | |
6295 | } | |
800eeca4 JW |
6296 | return 1; |
6297 | ||
6298 | case '}': | |
6299 | if (!md.manual_bundling) | |
6300 | as_warn ("Found '}' when manual bundling is off"); | |
6301 | else | |
6302 | PREV_SLOT.manual_bundling_off = 1; | |
6303 | md.manual_bundling = 0; | |
6304 | ||
6305 | /* switch back to automatic mode, if applicable */ | |
197865e8 | 6306 | if (md.detect_dv |
542d6675 KH |
6307 | && md.explicit_mode |
6308 | && !md.mode_explicitly_set | |
6309 | && !md.default_explicit_mode) | |
6310 | dot_dv_mode ('A'); | |
800eeca4 JW |
6311 | |
6312 | /* Allow '{' to follow on the same line. We also allow ";;", but that | |
6313 | happens automatically because ';' is an end of line marker. */ | |
6314 | SKIP_WHITESPACE (); | |
6315 | if (input_line_pointer[0] == '{') | |
6316 | { | |
6317 | input_line_pointer++; | |
6318 | return ia64_unrecognized_line ('{'); | |
6319 | } | |
6320 | ||
6321 | demand_empty_rest_of_line (); | |
6322 | return 1; | |
6323 | ||
f1bcba5b JW |
6324 | case '[': |
6325 | { | |
6326 | char *s; | |
6327 | char c; | |
6328 | symbolS *tag; | |
6329 | ||
6330 | if (md.qp.X_op == O_register) | |
6331 | { | |
6332 | as_bad ("Tag must come before qualifying predicate."); | |
6333 | return 0; | |
6334 | } | |
6335 | s = input_line_pointer; | |
6336 | c = get_symbol_end (); | |
6337 | if (c != ':') | |
6338 | { | |
6339 | /* Put ':' back for error messages' sake. */ | |
6340 | *input_line_pointer++ = ':'; | |
6341 | as_bad ("Expected ':'"); | |
6342 | return 0; | |
6343 | } | |
6344 | defining_tag = 1; | |
6345 | tag = colon (s); | |
6346 | defining_tag = 0; | |
6347 | /* Put ':' back for error messages' sake. */ | |
6348 | *input_line_pointer++ = ':'; | |
6349 | if (*input_line_pointer++ != ']') | |
6350 | { | |
6351 | as_bad ("Expected ']'"); | |
6352 | return 0; | |
6353 | } | |
6354 | if (! tag) | |
6355 | { | |
6356 | as_bad ("Tag name expected"); | |
6357 | return 0; | |
6358 | } | |
6359 | return 1; | |
6360 | } | |
6361 | ||
800eeca4 JW |
6362 | default: |
6363 | break; | |
6364 | } | |
542d6675 KH |
6365 | |
6366 | /* Not a valid line. */ | |
6367 | return 0; | |
800eeca4 JW |
6368 | } |
6369 | ||
6370 | void | |
6371 | ia64_frob_label (sym) | |
6372 | struct symbol *sym; | |
6373 | { | |
6374 | struct label_fix *fix; | |
6375 | ||
f1bcba5b JW |
6376 | /* Tags need special handling since they are not bundle breaks like |
6377 | labels. */ | |
6378 | if (defining_tag) | |
6379 | { | |
6380 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
6381 | fix->sym = sym; | |
6382 | fix->next = CURR_SLOT.tag_fixups; | |
6383 | CURR_SLOT.tag_fixups = fix; | |
6384 | ||
6385 | return; | |
6386 | } | |
6387 | ||
800eeca4 JW |
6388 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
6389 | { | |
6390 | md.last_text_seg = now_seg; | |
6391 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
6392 | fix->sym = sym; | |
6393 | fix->next = CURR_SLOT.label_fixups; | |
6394 | CURR_SLOT.label_fixups = fix; | |
6395 | ||
542d6675 | 6396 | /* Keep track of how many code entry points we've seen. */ |
800eeca4 | 6397 | if (md.path == md.maxpaths) |
542d6675 KH |
6398 | { |
6399 | md.maxpaths += 20; | |
6400 | md.entry_labels = (const char **) | |
6401 | xrealloc ((void *) md.entry_labels, | |
6402 | md.maxpaths * sizeof (char *)); | |
6403 | } | |
800eeca4 JW |
6404 | md.entry_labels[md.path++] = S_GET_NAME (sym); |
6405 | } | |
6406 | } | |
6407 | ||
6408 | void | |
6409 | ia64_flush_pending_output () | |
6410 | { | |
6411 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) | |
6412 | { | |
6413 | /* ??? This causes many unnecessary stop bits to be emitted. | |
6414 | Unfortunately, it isn't clear if it is safe to remove this. */ | |
6415 | insn_group_break (1, 0, 0); | |
6416 | ia64_flush_insns (); | |
6417 | } | |
6418 | } | |
6419 | ||
6420 | /* Do ia64-specific expression optimization. All that's done here is | |
6421 | to transform index expressions that are either due to the indexing | |
6422 | of rotating registers or due to the indexing of indirect register | |
6423 | sets. */ | |
6424 | int | |
6425 | ia64_optimize_expr (l, op, r) | |
6426 | expressionS *l; | |
6427 | operatorT op; | |
6428 | expressionS *r; | |
6429 | { | |
6430 | unsigned num_regs; | |
6431 | ||
6432 | if (op == O_index) | |
6433 | { | |
6434 | if (l->X_op == O_register && r->X_op == O_constant) | |
6435 | { | |
6436 | num_regs = (l->X_add_number >> 16); | |
6437 | if ((unsigned) r->X_add_number >= num_regs) | |
6438 | { | |
6439 | if (!num_regs) | |
6440 | as_bad ("No current frame"); | |
6441 | else | |
6442 | as_bad ("Index out of range 0..%u", num_regs - 1); | |
6443 | r->X_add_number = 0; | |
6444 | } | |
6445 | l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; | |
6446 | return 1; | |
6447 | } | |
6448 | else if (l->X_op == O_register && r->X_op == O_register) | |
6449 | { | |
6450 | if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR | |
6451 | || l->X_add_number == IND_MEM) | |
6452 | { | |
6453 | as_bad ("Indirect register set name expected"); | |
6454 | l->X_add_number = IND_CPUID; | |
6455 | } | |
6456 | l->X_op = O_index; | |
6457 | l->X_op_symbol = md.regsym[l->X_add_number]; | |
6458 | l->X_add_number = r->X_add_number; | |
6459 | return 1; | |
6460 | } | |
6461 | } | |
6462 | return 0; | |
6463 | } | |
6464 | ||
6465 | int | |
6466 | ia64_parse_name (name, e) | |
6467 | char *name; | |
6468 | expressionS *e; | |
6469 | { | |
6470 | struct const_desc *cdesc; | |
6471 | struct dynreg *dr = 0; | |
6472 | unsigned int regnum; | |
6473 | struct symbol *sym; | |
6474 | char *end; | |
6475 | ||
542d6675 | 6476 | /* first see if NAME is a known register name: */ |
800eeca4 JW |
6477 | sym = hash_find (md.reg_hash, name); |
6478 | if (sym) | |
6479 | { | |
6480 | e->X_op = O_register; | |
6481 | e->X_add_number = S_GET_VALUE (sym); | |
6482 | return 1; | |
6483 | } | |
6484 | ||
6485 | cdesc = hash_find (md.const_hash, name); | |
6486 | if (cdesc) | |
6487 | { | |
6488 | e->X_op = O_constant; | |
6489 | e->X_add_number = cdesc->value; | |
6490 | return 1; | |
6491 | } | |
6492 | ||
542d6675 | 6493 | /* check for inN, locN, or outN: */ |
800eeca4 JW |
6494 | switch (name[0]) |
6495 | { | |
6496 | case 'i': | |
6497 | if (name[1] == 'n' && isdigit (name[2])) | |
6498 | { | |
6499 | dr = &md.in; | |
6500 | name += 2; | |
6501 | } | |
6502 | break; | |
6503 | ||
6504 | case 'l': | |
6505 | if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3])) | |
6506 | { | |
6507 | dr = &md.loc; | |
6508 | name += 3; | |
6509 | } | |
6510 | break; | |
6511 | ||
6512 | case 'o': | |
6513 | if (name[1] == 'u' && name[2] == 't' && isdigit (name[3])) | |
6514 | { | |
6515 | dr = &md.out; | |
6516 | name += 3; | |
6517 | } | |
6518 | break; | |
6519 | ||
6520 | default: | |
6521 | break; | |
6522 | } | |
6523 | ||
6524 | if (dr) | |
6525 | { | |
542d6675 | 6526 | /* The name is inN, locN, or outN; parse the register number. */ |
800eeca4 JW |
6527 | regnum = strtoul (name, &end, 10); |
6528 | if (end > name && *end == '\0') | |
6529 | { | |
6530 | if ((unsigned) regnum >= dr->num_regs) | |
6531 | { | |
6532 | if (!dr->num_regs) | |
6533 | as_bad ("No current frame"); | |
6534 | else | |
542d6675 KH |
6535 | as_bad ("Register number out of range 0..%u", |
6536 | dr->num_regs - 1); | |
800eeca4 JW |
6537 | regnum = 0; |
6538 | } | |
6539 | e->X_op = O_register; | |
6540 | e->X_add_number = dr->base + regnum; | |
6541 | return 1; | |
6542 | } | |
6543 | } | |
6544 | ||
6545 | if ((dr = hash_find (md.dynreg_hash, name))) | |
6546 | { | |
6547 | /* We've got ourselves the name of a rotating register set. | |
542d6675 KH |
6548 | Store the base register number in the low 16 bits of |
6549 | X_add_number and the size of the register set in the top 16 | |
6550 | bits. */ | |
800eeca4 JW |
6551 | e->X_op = O_register; |
6552 | e->X_add_number = dr->base | (dr->num_regs << 16); | |
6553 | return 1; | |
6554 | } | |
6555 | return 0; | |
6556 | } | |
6557 | ||
6558 | /* Remove the '#' suffix that indicates a symbol as opposed to a register. */ | |
6559 | ||
6560 | char * | |
6561 | ia64_canonicalize_symbol_name (name) | |
6562 | char *name; | |
6563 | { | |
542d6675 KH |
6564 | size_t len = strlen (name); |
6565 | if (len > 1 && name[len - 1] == '#') | |
6566 | name[len - 1] = '\0'; | |
800eeca4 JW |
6567 | return name; |
6568 | } | |
6569 | ||
6570 | static int | |
6571 | is_conditional_branch (idesc) | |
542d6675 | 6572 | struct ia64_opcode *idesc; |
800eeca4 JW |
6573 | { |
6574 | return (strncmp (idesc->name, "br", 2) == 0 | |
542d6675 KH |
6575 | && (strcmp (idesc->name, "br") == 0 |
6576 | || strncmp (idesc->name, "br.cond", 7) == 0 | |
6577 | || strncmp (idesc->name, "br.call", 7) == 0 | |
6578 | || strncmp (idesc->name, "br.ret", 6) == 0 | |
6579 | || strcmp (idesc->name, "brl") == 0 | |
6580 | || strncmp (idesc->name, "brl.cond", 7) == 0 | |
6581 | || strncmp (idesc->name, "brl.call", 7) == 0 | |
6582 | || strncmp (idesc->name, "brl.ret", 6) == 0)); | |
800eeca4 JW |
6583 | } |
6584 | ||
6585 | /* Return whether the given opcode is a taken branch. If there's any doubt, | |
542d6675 KH |
6586 | returns zero. */ |
6587 | ||
800eeca4 JW |
6588 | static int |
6589 | is_taken_branch (idesc) | |
542d6675 | 6590 | struct ia64_opcode *idesc; |
800eeca4 JW |
6591 | { |
6592 | return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) | |
542d6675 | 6593 | || strncmp (idesc->name, "br.ia", 5) == 0); |
800eeca4 JW |
6594 | } |
6595 | ||
6596 | /* Return whether the given opcode is an interruption or rfi. If there's any | |
542d6675 KH |
6597 | doubt, returns zero. */ |
6598 | ||
800eeca4 JW |
6599 | static int |
6600 | is_interruption_or_rfi (idesc) | |
542d6675 | 6601 | struct ia64_opcode *idesc; |
800eeca4 JW |
6602 | { |
6603 | if (strcmp (idesc->name, "rfi") == 0) | |
6604 | return 1; | |
6605 | return 0; | |
6606 | } | |
6607 | ||
6608 | /* Returns the index of the given dependency in the opcode's list of chks, or | |
6609 | -1 if there is no dependency. */ | |
542d6675 | 6610 | |
800eeca4 JW |
6611 | static int |
6612 | depends_on (depind, idesc) | |
542d6675 KH |
6613 | int depind; |
6614 | struct ia64_opcode *idesc; | |
800eeca4 JW |
6615 | { |
6616 | int i; | |
6617 | const struct ia64_opcode_dependency *dep = idesc->dependencies; | |
542d6675 | 6618 | for (i = 0; i < dep->nchks; i++) |
800eeca4 | 6619 | { |
542d6675 KH |
6620 | if (depind == DEP (dep->chks[i])) |
6621 | return i; | |
800eeca4 JW |
6622 | } |
6623 | return -1; | |
6624 | } | |
6625 | ||
6626 | /* Determine a set of specific resources used for a particular resource | |
6627 | class. Returns the number of specific resources identified For those | |
6628 | cases which are not determinable statically, the resource returned is | |
197865e8 | 6629 | marked nonspecific. |
800eeca4 JW |
6630 | |
6631 | Meanings of value in 'NOTE': | |
6632 | 1) only read/write when the register number is explicitly encoded in the | |
6633 | insn. | |
6634 | 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only | |
197865e8 | 6635 | accesses CFM when qualifying predicate is in the rotating region. |
800eeca4 JW |
6636 | 3) general register value is used to specify an indirect register; not |
6637 | determinable statically. | |
6638 | 4) only read the given resource when bits 7:0 of the indirect index | |
6639 | register value does not match the register number of the resource; not | |
6640 | determinable statically. | |
6641 | 5) all rules are implementation specific. | |
6642 | 6) only when both the index specified by the reader and the index specified | |
6643 | by the writer have the same value in bits 63:61; not determinable | |
197865e8 | 6644 | statically. |
800eeca4 | 6645 | 7) only access the specified resource when the corresponding mask bit is |
197865e8 | 6646 | set |
800eeca4 JW |
6647 | 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is |
6648 | only read when these insns reference FR2-31 | |
6649 | 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only | |
6650 | written when these insns write FR32-127 | |
6651 | 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the | |
6652 | instruction | |
6653 | 11) The target predicates are written independently of PR[qp], but source | |
6654 | registers are only read if PR[qp] is true. Since the state of PR[qp] | |
6655 | cannot statically be determined, all source registers are marked used. | |
6656 | 12) This insn only reads the specified predicate register when that | |
6657 | register is the PR[qp]. | |
6658 | 13) This reference to ld-c only applies to teh GR whose value is loaded | |
197865e8 | 6659 | with data returned from memory, not the post-incremented address register. |
800eeca4 JW |
6660 | 14) The RSE resource includes the implementation-specific RSE internal |
6661 | state resources. At least one (and possibly more) of these resources are | |
6662 | read by each instruction listed in IC:rse-readers. At least one (and | |
6663 | possibly more) of these resources are written by each insn listed in | |
197865e8 | 6664 | IC:rse-writers. |
800eeca4 | 6665 | 15+16) Represents reserved instructions, which the assembler does not |
197865e8 | 6666 | generate. |
800eeca4 JW |
6667 | |
6668 | Memory resources (i.e. locations in memory) are *not* marked or tracked by | |
6669 | this code; there are no dependency violations based on memory access. | |
800eeca4 JW |
6670 | */ |
6671 | ||
6672 | #define MAX_SPECS 256 | |
6673 | #define DV_CHK 1 | |
6674 | #define DV_REG 0 | |
6675 | ||
6676 | static int | |
6677 | specify_resource (dep, idesc, type, specs, note, path) | |
542d6675 KH |
6678 | const struct ia64_dependency *dep; |
6679 | struct ia64_opcode *idesc; | |
6680 | int type; /* is this a DV chk or a DV reg? */ | |
6681 | struct rsrc specs[MAX_SPECS]; /* returned specific resources */ | |
6682 | int note; /* resource note for this insn's usage */ | |
6683 | int path; /* which execution path to examine */ | |
800eeca4 JW |
6684 | { |
6685 | int count = 0; | |
6686 | int i; | |
6687 | int rsrc_write = 0; | |
6688 | struct rsrc tmpl; | |
197865e8 | 6689 | |
800eeca4 JW |
6690 | if (dep->mode == IA64_DV_WAW |
6691 | || (dep->mode == IA64_DV_RAW && type == DV_REG) | |
6692 | || (dep->mode == IA64_DV_WAR && type == DV_CHK)) | |
6693 | rsrc_write = 1; | |
6694 | ||
6695 | /* template for any resources we identify */ | |
6696 | tmpl.dependency = dep; | |
6697 | tmpl.note = note; | |
6698 | tmpl.insn_srlz = tmpl.data_srlz = 0; | |
6699 | tmpl.qp_regno = CURR_SLOT.qp_regno; | |
6700 | tmpl.link_to_qp_branch = 1; | |
6701 | tmpl.mem_offset.hint = 0; | |
6702 | tmpl.specific = 1; | |
6703 | tmpl.index = 0; | |
7484b8e6 | 6704 | tmpl.cmp_type = CMP_NONE; |
800eeca4 JW |
6705 | |
6706 | #define UNHANDLED \ | |
6707 | as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ | |
6708 | dep->name, idesc->name, (rsrc_write?"write":"read"), note) | |
6709 | #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) | |
6710 | ||
6711 | /* we don't need to track these */ | |
6712 | if (dep->semantics == IA64_DVS_NONE) | |
6713 | return 0; | |
6714 | ||
6715 | switch (dep->specifier) | |
6716 | { | |
6717 | case IA64_RS_AR_K: | |
6718 | if (note == 1) | |
542d6675 KH |
6719 | { |
6720 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
6721 | { | |
6722 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
6723 | if (regno >= 0 && regno <= 7) | |
6724 | { | |
6725 | specs[count] = tmpl; | |
6726 | specs[count++].index = regno; | |
6727 | } | |
6728 | } | |
6729 | } | |
800eeca4 | 6730 | else if (note == 0) |
542d6675 KH |
6731 | { |
6732 | for (i = 0; i < 8; i++) | |
6733 | { | |
6734 | specs[count] = tmpl; | |
6735 | specs[count++].index = i; | |
6736 | } | |
6737 | } | |
800eeca4 | 6738 | else |
542d6675 KH |
6739 | { |
6740 | UNHANDLED; | |
6741 | } | |
800eeca4 JW |
6742 | break; |
6743 | ||
6744 | case IA64_RS_AR_UNAT: | |
6745 | /* This is a mov =AR or mov AR= instruction. */ | |
6746 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
6747 | { | |
6748 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
6749 | if (regno == AR_UNAT) | |
6750 | { | |
6751 | specs[count++] = tmpl; | |
6752 | } | |
6753 | } | |
6754 | else | |
6755 | { | |
6756 | /* This is a spill/fill, or other instruction that modifies the | |
6757 | unat register. */ | |
6758 | ||
6759 | /* Unless we can determine the specific bits used, mark the whole | |
6760 | thing; bits 8:3 of the memory address indicate the bit used in | |
6761 | UNAT. The .mem.offset hint may be used to eliminate a small | |
6762 | subset of conflicts. */ | |
6763 | specs[count] = tmpl; | |
6764 | if (md.mem_offset.hint) | |
6765 | { | |
542d6675 KH |
6766 | if (md.debug_dv) |
6767 | fprintf (stderr, " Using hint for spill/fill\n"); | |
6768 | /* The index isn't actually used, just set it to something | |
6769 | approximating the bit index. */ | |
800eeca4 JW |
6770 | specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; |
6771 | specs[count].mem_offset.hint = 1; | |
6772 | specs[count].mem_offset.offset = md.mem_offset.offset; | |
6773 | specs[count++].mem_offset.base = md.mem_offset.base; | |
6774 | } | |
6775 | else | |
6776 | { | |
6777 | specs[count++].specific = 0; | |
6778 | } | |
6779 | } | |
6780 | break; | |
6781 | ||
6782 | case IA64_RS_AR: | |
6783 | if (note == 1) | |
542d6675 KH |
6784 | { |
6785 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
6786 | { | |
6787 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
6788 | if ((regno >= 8 && regno <= 15) | |
6789 | || (regno >= 20 && regno <= 23) | |
6790 | || (regno >= 31 && regno <= 39) | |
6791 | || (regno >= 41 && regno <= 47) | |
6792 | || (regno >= 67 && regno <= 111)) | |
6793 | { | |
6794 | specs[count] = tmpl; | |
6795 | specs[count++].index = regno; | |
6796 | } | |
6797 | } | |
6798 | } | |
800eeca4 | 6799 | else |
542d6675 KH |
6800 | { |
6801 | UNHANDLED; | |
6802 | } | |
800eeca4 JW |
6803 | break; |
6804 | ||
6805 | case IA64_RS_ARb: | |
6806 | if (note == 1) | |
542d6675 KH |
6807 | { |
6808 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
6809 | { | |
6810 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
6811 | if ((regno >= 48 && regno <= 63) | |
6812 | || (regno >= 112 && regno <= 127)) | |
6813 | { | |
6814 | specs[count] = tmpl; | |
6815 | specs[count++].index = regno; | |
6816 | } | |
6817 | } | |
6818 | } | |
800eeca4 | 6819 | else if (note == 0) |
542d6675 KH |
6820 | { |
6821 | for (i = 48; i < 64; i++) | |
6822 | { | |
6823 | specs[count] = tmpl; | |
6824 | specs[count++].index = i; | |
6825 | } | |
6826 | for (i = 112; i < 128; i++) | |
6827 | { | |
6828 | specs[count] = tmpl; | |
6829 | specs[count++].index = i; | |
6830 | } | |
6831 | } | |
197865e8 | 6832 | else |
542d6675 KH |
6833 | { |
6834 | UNHANDLED; | |
6835 | } | |
800eeca4 JW |
6836 | break; |
6837 | ||
6838 | case IA64_RS_BR: | |
6839 | if (note != 1) | |
542d6675 KH |
6840 | { |
6841 | UNHANDLED; | |
6842 | } | |
800eeca4 | 6843 | else |
542d6675 KH |
6844 | { |
6845 | if (rsrc_write) | |
6846 | { | |
6847 | for (i = 0; i < idesc->num_outputs; i++) | |
6848 | if (idesc->operands[i] == IA64_OPND_B1 | |
6849 | || idesc->operands[i] == IA64_OPND_B2) | |
6850 | { | |
6851 | specs[count] = tmpl; | |
6852 | specs[count++].index = | |
6853 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
6854 | } | |
6855 | } | |
6856 | else | |
6857 | { | |
6858 | for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++) | |
6859 | if (idesc->operands[i] == IA64_OPND_B1 | |
6860 | || idesc->operands[i] == IA64_OPND_B2) | |
6861 | { | |
6862 | specs[count] = tmpl; | |
6863 | specs[count++].index = | |
6864 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
6865 | } | |
6866 | } | |
6867 | } | |
800eeca4 JW |
6868 | break; |
6869 | ||
6870 | case IA64_RS_CPUID: /* four or more registers */ | |
6871 | if (note == 3) | |
542d6675 KH |
6872 | { |
6873 | if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) | |
6874 | { | |
6875 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6876 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6877 | && KNOWN (regno)) | |
6878 | { | |
6879 | specs[count] = tmpl; | |
6880 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6881 | } | |
6882 | else | |
6883 | { | |
6884 | specs[count] = tmpl; | |
6885 | specs[count++].specific = 0; | |
6886 | } | |
6887 | } | |
6888 | } | |
800eeca4 | 6889 | else |
542d6675 KH |
6890 | { |
6891 | UNHANDLED; | |
6892 | } | |
800eeca4 JW |
6893 | break; |
6894 | ||
6895 | case IA64_RS_DBR: /* four or more registers */ | |
6896 | if (note == 3) | |
542d6675 KH |
6897 | { |
6898 | if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) | |
6899 | { | |
6900 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6901 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6902 | && KNOWN (regno)) | |
6903 | { | |
6904 | specs[count] = tmpl; | |
6905 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6906 | } | |
6907 | else | |
6908 | { | |
6909 | specs[count] = tmpl; | |
6910 | specs[count++].specific = 0; | |
6911 | } | |
6912 | } | |
6913 | } | |
800eeca4 | 6914 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
6915 | { |
6916 | specs[count] = tmpl; | |
6917 | specs[count++].specific = 0; | |
6918 | } | |
800eeca4 | 6919 | else |
542d6675 KH |
6920 | { |
6921 | UNHANDLED; | |
6922 | } | |
800eeca4 JW |
6923 | break; |
6924 | ||
6925 | case IA64_RS_IBR: /* four or more registers */ | |
6926 | if (note == 3) | |
542d6675 KH |
6927 | { |
6928 | if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) | |
6929 | { | |
6930 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6931 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6932 | && KNOWN (regno)) | |
6933 | { | |
6934 | specs[count] = tmpl; | |
6935 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6936 | } | |
6937 | else | |
6938 | { | |
6939 | specs[count] = tmpl; | |
6940 | specs[count++].specific = 0; | |
6941 | } | |
6942 | } | |
6943 | } | |
800eeca4 | 6944 | else |
542d6675 KH |
6945 | { |
6946 | UNHANDLED; | |
6947 | } | |
800eeca4 JW |
6948 | break; |
6949 | ||
6950 | case IA64_RS_MSR: | |
6951 | if (note == 5) | |
6952 | { | |
6953 | /* These are implementation specific. Force all references to | |
6954 | conflict with all other references. */ | |
6955 | specs[count] = tmpl; | |
6956 | specs[count++].specific = 0; | |
6957 | } | |
6958 | else | |
6959 | { | |
6960 | UNHANDLED; | |
6961 | } | |
6962 | break; | |
6963 | ||
6964 | case IA64_RS_PKR: /* 16 or more registers */ | |
6965 | if (note == 3 || note == 4) | |
542d6675 KH |
6966 | { |
6967 | if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) | |
6968 | { | |
6969 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6970 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6971 | && KNOWN (regno)) | |
6972 | { | |
6973 | if (note == 3) | |
6974 | { | |
6975 | specs[count] = tmpl; | |
6976 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6977 | } | |
6978 | else | |
6979 | for (i = 0; i < NELEMS (gr_values); i++) | |
6980 | { | |
6981 | /* Uses all registers *except* the one in R3. */ | |
2434f565 | 6982 | if ((unsigned)i != (gr_values[regno].value & 0xFF)) |
542d6675 KH |
6983 | { |
6984 | specs[count] = tmpl; | |
6985 | specs[count++].index = i; | |
6986 | } | |
6987 | } | |
6988 | } | |
6989 | else | |
6990 | { | |
6991 | specs[count] = tmpl; | |
6992 | specs[count++].specific = 0; | |
6993 | } | |
6994 | } | |
6995 | } | |
6996 | else if (note == 0) | |
6997 | { | |
6998 | /* probe et al. */ | |
6999 | specs[count] = tmpl; | |
7000 | specs[count++].specific = 0; | |
7001 | } | |
7002 | break; | |
7003 | ||
7004 | case IA64_RS_PMC: /* four or more registers */ | |
7005 | if (note == 3) | |
7006 | { | |
7007 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 | |
7008 | || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) | |
7009 | ||
7010 | { | |
7011 | int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) | |
7012 | ? 1 : !rsrc_write); | |
7013 | int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; | |
7014 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7015 | && KNOWN (regno)) | |
7016 | { | |
7017 | specs[count] = tmpl; | |
7018 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7019 | } | |
7020 | else | |
7021 | { | |
7022 | specs[count] = tmpl; | |
7023 | specs[count++].specific = 0; | |
7024 | } | |
7025 | } | |
7026 | } | |
7027 | else | |
7028 | { | |
7029 | UNHANDLED; | |
7030 | } | |
800eeca4 JW |
7031 | break; |
7032 | ||
7033 | case IA64_RS_PMD: /* four or more registers */ | |
7034 | if (note == 3) | |
542d6675 KH |
7035 | { |
7036 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) | |
7037 | { | |
7038 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7039 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7040 | && KNOWN (regno)) | |
7041 | { | |
7042 | specs[count] = tmpl; | |
7043 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7044 | } | |
7045 | else | |
7046 | { | |
7047 | specs[count] = tmpl; | |
7048 | specs[count++].specific = 0; | |
7049 | } | |
7050 | } | |
7051 | } | |
800eeca4 | 7052 | else |
542d6675 KH |
7053 | { |
7054 | UNHANDLED; | |
7055 | } | |
800eeca4 JW |
7056 | break; |
7057 | ||
7058 | case IA64_RS_RR: /* eight registers */ | |
7059 | if (note == 6) | |
542d6675 KH |
7060 | { |
7061 | if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) | |
7062 | { | |
7063 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7064 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7065 | && KNOWN (regno)) | |
7066 | { | |
7067 | specs[count] = tmpl; | |
7068 | specs[count++].index = (gr_values[regno].value >> 61) & 0x7; | |
7069 | } | |
7070 | else | |
7071 | { | |
7072 | specs[count] = tmpl; | |
7073 | specs[count++].specific = 0; | |
7074 | } | |
7075 | } | |
7076 | } | |
800eeca4 | 7077 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
7078 | { |
7079 | specs[count] = tmpl; | |
7080 | specs[count++].specific = 0; | |
7081 | } | |
197865e8 | 7082 | else |
542d6675 KH |
7083 | { |
7084 | UNHANDLED; | |
7085 | } | |
800eeca4 JW |
7086 | break; |
7087 | ||
7088 | case IA64_RS_CR_IRR: | |
197865e8 | 7089 | if (note == 0) |
542d6675 KH |
7090 | { |
7091 | /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ | |
7092 | int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; | |
7093 | if (rsrc_write | |
7094 | && idesc->operands[1] == IA64_OPND_CR3 | |
7095 | && regno == CR_IVR) | |
7096 | { | |
7097 | for (i = 0; i < 4; i++) | |
7098 | { | |
7099 | specs[count] = tmpl; | |
7100 | specs[count++].index = CR_IRR0 + i; | |
7101 | } | |
7102 | } | |
7103 | } | |
800eeca4 | 7104 | else if (note == 1) |
542d6675 KH |
7105 | { |
7106 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7107 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
7108 | && regno >= CR_IRR0 | |
7109 | && regno <= CR_IRR3) | |
7110 | { | |
7111 | specs[count] = tmpl; | |
7112 | specs[count++].index = regno; | |
7113 | } | |
7114 | } | |
800eeca4 | 7115 | else |
542d6675 KH |
7116 | { |
7117 | UNHANDLED; | |
7118 | } | |
800eeca4 JW |
7119 | break; |
7120 | ||
7121 | case IA64_RS_CR_LRR: | |
7122 | if (note != 1) | |
542d6675 KH |
7123 | { |
7124 | UNHANDLED; | |
7125 | } | |
197865e8 | 7126 | else |
542d6675 KH |
7127 | { |
7128 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7129 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
7130 | && (regno == CR_LRR0 || regno == CR_LRR1)) | |
7131 | { | |
7132 | specs[count] = tmpl; | |
7133 | specs[count++].index = regno; | |
7134 | } | |
7135 | } | |
800eeca4 JW |
7136 | break; |
7137 | ||
7138 | case IA64_RS_CR: | |
7139 | if (note == 1) | |
542d6675 KH |
7140 | { |
7141 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
7142 | { | |
7143 | specs[count] = tmpl; | |
7144 | specs[count++].index = | |
7145 | CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7146 | } | |
7147 | } | |
800eeca4 | 7148 | else |
542d6675 KH |
7149 | { |
7150 | UNHANDLED; | |
7151 | } | |
800eeca4 JW |
7152 | break; |
7153 | ||
7154 | case IA64_RS_FR: | |
7155 | case IA64_RS_FRb: | |
7156 | if (note != 1) | |
542d6675 KH |
7157 | { |
7158 | UNHANDLED; | |
7159 | } | |
800eeca4 | 7160 | else if (rsrc_write) |
542d6675 KH |
7161 | { |
7162 | if (dep->specifier == IA64_RS_FRb | |
7163 | && idesc->operands[0] == IA64_OPND_F1) | |
7164 | { | |
7165 | specs[count] = tmpl; | |
7166 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; | |
7167 | } | |
7168 | } | |
800eeca4 | 7169 | else |
542d6675 KH |
7170 | { |
7171 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) | |
7172 | { | |
7173 | if (idesc->operands[i] == IA64_OPND_F2 | |
7174 | || idesc->operands[i] == IA64_OPND_F3 | |
7175 | || idesc->operands[i] == IA64_OPND_F4) | |
7176 | { | |
7177 | specs[count] = tmpl; | |
7178 | specs[count++].index = | |
7179 | CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7180 | } | |
7181 | } | |
7182 | } | |
800eeca4 JW |
7183 | break; |
7184 | ||
7185 | case IA64_RS_GR: | |
7186 | if (note == 13) | |
542d6675 KH |
7187 | { |
7188 | /* This reference applies only to the GR whose value is loaded with | |
7189 | data returned from memory. */ | |
7190 | specs[count] = tmpl; | |
7191 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
7192 | } | |
800eeca4 | 7193 | else if (note == 1) |
542d6675 KH |
7194 | { |
7195 | if (rsrc_write) | |
7196 | { | |
7197 | for (i = 0; i < idesc->num_outputs; i++) | |
50b81f19 JW |
7198 | if (idesc->operands[i] == IA64_OPND_R1 |
7199 | || idesc->operands[i] == IA64_OPND_R2 | |
7200 | || idesc->operands[i] == IA64_OPND_R3) | |
7201 | { | |
7202 | specs[count] = tmpl; | |
197865e8 | 7203 | specs[count++].index = |
50b81f19 JW |
7204 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
7205 | } | |
7206 | if (idesc->flags & IA64_OPCODE_POSTINC) | |
7207 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7208 | if (idesc->operands[i] == IA64_OPND_MR3) | |
7209 | { | |
7210 | specs[count] = tmpl; | |
7211 | specs[count++].index = | |
7212 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7213 | } | |
542d6675 KH |
7214 | } |
7215 | else | |
7216 | { | |
7217 | /* Look for anything that reads a GR. */ | |
7218 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7219 | { | |
7220 | if (idesc->operands[i] == IA64_OPND_MR3 | |
7221 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
7222 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
7223 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
800eeca4 | 7224 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
542d6675 KH |
7225 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
7226 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
7227 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
7228 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
7229 | || ((i >= idesc->num_outputs) | |
7230 | && (idesc->operands[i] == IA64_OPND_R1 | |
7231 | || idesc->operands[i] == IA64_OPND_R2 | |
7232 | || idesc->operands[i] == IA64_OPND_R3 | |
50b81f19 JW |
7233 | /* addl source register. */ |
7234 | || idesc->operands[i] == IA64_OPND_R3_2))) | |
542d6675 KH |
7235 | { |
7236 | specs[count] = tmpl; | |
7237 | specs[count++].index = | |
7238 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7239 | } | |
7240 | } | |
7241 | } | |
7242 | } | |
197865e8 | 7243 | else |
542d6675 KH |
7244 | { |
7245 | UNHANDLED; | |
7246 | } | |
800eeca4 JW |
7247 | break; |
7248 | ||
139368c9 JW |
7249 | /* This is the same as IA64_RS_PRr, except that the register range is |
7250 | from 1 - 15, and there are no rotating register reads/writes here. */ | |
800eeca4 JW |
7251 | case IA64_RS_PR: |
7252 | if (note == 0) | |
542d6675 | 7253 | { |
139368c9 | 7254 | for (i = 1; i < 16; i++) |
542d6675 | 7255 | { |
139368c9 JW |
7256 | specs[count] = tmpl; |
7257 | specs[count++].index = i; | |
7258 | } | |
7259 | } | |
7260 | else if (note == 7) | |
7261 | { | |
7262 | valueT mask = 0; | |
7263 | /* Mark only those registers indicated by the mask. */ | |
7264 | if (rsrc_write) | |
7265 | { | |
7266 | mask = CURR_SLOT.opnd[2].X_add_number; | |
7267 | for (i = 1; i < 16; i++) | |
7268 | if (mask & ((valueT) 1 << i)) | |
7269 | { | |
7270 | specs[count] = tmpl; | |
7271 | specs[count++].index = i; | |
7272 | } | |
7273 | } | |
7274 | else | |
7275 | { | |
7276 | UNHANDLED; | |
7277 | } | |
7278 | } | |
7279 | else if (note == 11) /* note 11 implies note 1 as well */ | |
7280 | { | |
7281 | if (rsrc_write) | |
7282 | { | |
7283 | for (i = 0; i < idesc->num_outputs; i++) | |
7284 | { | |
7285 | if (idesc->operands[i] == IA64_OPND_P1 | |
7286 | || idesc->operands[i] == IA64_OPND_P2) | |
7287 | { | |
7288 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
7289 | if (regno >= 1 && regno < 16) | |
7290 | { | |
7291 | specs[count] = tmpl; | |
7292 | specs[count++].index = regno; | |
7293 | } | |
7294 | } | |
7295 | } | |
7296 | } | |
7297 | else | |
7298 | { | |
7299 | UNHANDLED; | |
7300 | } | |
7301 | } | |
7302 | else if (note == 12) | |
7303 | { | |
7304 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) | |
7305 | { | |
7306 | specs[count] = tmpl; | |
7307 | specs[count++].index = CURR_SLOT.qp_regno; | |
7308 | } | |
7309 | } | |
7310 | else if (note == 1) | |
7311 | { | |
7312 | if (rsrc_write) | |
7313 | { | |
7314 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
7315 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
7316 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; | |
7317 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
7318 | ||
7319 | if ((idesc->operands[0] == IA64_OPND_P1 | |
7320 | || idesc->operands[0] == IA64_OPND_P2) | |
7321 | && p1 >= 1 && p1 < 16) | |
542d6675 KH |
7322 | { |
7323 | specs[count] = tmpl; | |
139368c9 JW |
7324 | specs[count].cmp_type = |
7325 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); | |
7326 | specs[count++].index = p1; | |
7327 | } | |
7328 | if ((idesc->operands[1] == IA64_OPND_P1 | |
7329 | || idesc->operands[1] == IA64_OPND_P2) | |
7330 | && p2 >= 1 && p2 < 16) | |
7331 | { | |
7332 | specs[count] = tmpl; | |
7333 | specs[count].cmp_type = | |
7334 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); | |
7335 | specs[count++].index = p2; | |
542d6675 KH |
7336 | } |
7337 | } | |
7338 | else | |
7339 | { | |
139368c9 | 7340 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
542d6675 KH |
7341 | { |
7342 | specs[count] = tmpl; | |
139368c9 JW |
7343 | specs[count++].index = CURR_SLOT.qp_regno; |
7344 | } | |
7345 | if (idesc->operands[1] == IA64_OPND_PR) | |
7346 | { | |
7347 | for (i = 1; i < 16; i++) | |
7348 | { | |
7349 | specs[count] = tmpl; | |
7350 | specs[count++].index = i; | |
7351 | } | |
542d6675 KH |
7352 | } |
7353 | } | |
7354 | } | |
139368c9 JW |
7355 | else |
7356 | { | |
7357 | UNHANDLED; | |
7358 | } | |
7359 | break; | |
7360 | ||
7361 | /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are | |
7362 | simplified cases of this. */ | |
7363 | case IA64_RS_PRr: | |
7364 | if (note == 0) | |
7365 | { | |
7366 | for (i = 16; i < 63; i++) | |
7367 | { | |
7368 | specs[count] = tmpl; | |
7369 | specs[count++].index = i; | |
7370 | } | |
7371 | } | |
800eeca4 | 7372 | else if (note == 7) |
542d6675 KH |
7373 | { |
7374 | valueT mask = 0; | |
7375 | /* Mark only those registers indicated by the mask. */ | |
7376 | if (rsrc_write | |
7377 | && idesc->operands[0] == IA64_OPND_PR) | |
7378 | { | |
7379 | mask = CURR_SLOT.opnd[2].X_add_number; | |
139368c9 JW |
7380 | if (mask & ((valueT) 1<<16)) |
7381 | for (i = 16; i < 63; i++) | |
7382 | { | |
7383 | specs[count] = tmpl; | |
7384 | specs[count++].index = i; | |
7385 | } | |
542d6675 KH |
7386 | } |
7387 | else if (rsrc_write | |
7388 | && idesc->operands[0] == IA64_OPND_PR_ROT) | |
7389 | { | |
7390 | for (i = 16; i < 63; i++) | |
7391 | { | |
7392 | specs[count] = tmpl; | |
7393 | specs[count++].index = i; | |
7394 | } | |
7395 | } | |
7396 | else | |
7397 | { | |
7398 | UNHANDLED; | |
7399 | } | |
7400 | } | |
800eeca4 | 7401 | else if (note == 11) /* note 11 implies note 1 as well */ |
542d6675 KH |
7402 | { |
7403 | if (rsrc_write) | |
7404 | { | |
7405 | for (i = 0; i < idesc->num_outputs; i++) | |
7406 | { | |
7407 | if (idesc->operands[i] == IA64_OPND_P1 | |
7408 | || idesc->operands[i] == IA64_OPND_P2) | |
7409 | { | |
7410 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
139368c9 | 7411 | if (regno >= 16 && regno < 63) |
542d6675 KH |
7412 | { |
7413 | specs[count] = tmpl; | |
7414 | specs[count++].index = regno; | |
7415 | } | |
7416 | } | |
7417 | } | |
7418 | } | |
7419 | else | |
7420 | { | |
7421 | UNHANDLED; | |
7422 | } | |
7423 | } | |
800eeca4 | 7424 | else if (note == 12) |
542d6675 | 7425 | { |
139368c9 | 7426 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
7427 | { |
7428 | specs[count] = tmpl; | |
7429 | specs[count++].index = CURR_SLOT.qp_regno; | |
7430 | } | |
7431 | } | |
800eeca4 | 7432 | else if (note == 1) |
542d6675 KH |
7433 | { |
7434 | if (rsrc_write) | |
7435 | { | |
7436 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
7437 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
7484b8e6 TW |
7438 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; |
7439 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
7440 | ||
542d6675 KH |
7441 | if ((idesc->operands[0] == IA64_OPND_P1 |
7442 | || idesc->operands[0] == IA64_OPND_P2) | |
139368c9 | 7443 | && p1 >= 16 && p1 < 63) |
542d6675 KH |
7444 | { |
7445 | specs[count] = tmpl; | |
4a4f25cf | 7446 | specs[count].cmp_type = |
7484b8e6 | 7447 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
542d6675 KH |
7448 | specs[count++].index = p1; |
7449 | } | |
7450 | if ((idesc->operands[1] == IA64_OPND_P1 | |
7451 | || idesc->operands[1] == IA64_OPND_P2) | |
139368c9 | 7452 | && p2 >= 16 && p2 < 63) |
542d6675 KH |
7453 | { |
7454 | specs[count] = tmpl; | |
4a4f25cf | 7455 | specs[count].cmp_type = |
7484b8e6 | 7456 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
542d6675 KH |
7457 | specs[count++].index = p2; |
7458 | } | |
7459 | } | |
7460 | else | |
7461 | { | |
139368c9 | 7462 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
7463 | { |
7464 | specs[count] = tmpl; | |
7465 | specs[count++].index = CURR_SLOT.qp_regno; | |
7466 | } | |
7467 | if (idesc->operands[1] == IA64_OPND_PR) | |
7468 | { | |
139368c9 | 7469 | for (i = 16; i < 63; i++) |
542d6675 KH |
7470 | { |
7471 | specs[count] = tmpl; | |
7472 | specs[count++].index = i; | |
7473 | } | |
7474 | } | |
7475 | } | |
7476 | } | |
197865e8 | 7477 | else |
542d6675 KH |
7478 | { |
7479 | UNHANDLED; | |
7480 | } | |
800eeca4 JW |
7481 | break; |
7482 | ||
7483 | case IA64_RS_PSR: | |
197865e8 | 7484 | /* Verify that the instruction is using the PSR bit indicated in |
542d6675 | 7485 | dep->regindex. */ |
800eeca4 | 7486 | if (note == 0) |
542d6675 KH |
7487 | { |
7488 | if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) | |
7489 | { | |
7490 | if (dep->regindex < 6) | |
7491 | { | |
7492 | specs[count++] = tmpl; | |
7493 | } | |
7494 | } | |
7495 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) | |
7496 | { | |
7497 | if (dep->regindex < 32 | |
7498 | || dep->regindex == 35 | |
7499 | || dep->regindex == 36 | |
7500 | || (!rsrc_write && dep->regindex == PSR_CPL)) | |
7501 | { | |
7502 | specs[count++] = tmpl; | |
7503 | } | |
7504 | } | |
7505 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) | |
7506 | { | |
7507 | if (dep->regindex < 32 | |
7508 | || dep->regindex == 35 | |
7509 | || dep->regindex == 36 | |
7510 | || (rsrc_write && dep->regindex == PSR_CPL)) | |
7511 | { | |
7512 | specs[count++] = tmpl; | |
7513 | } | |
7514 | } | |
7515 | else | |
7516 | { | |
7517 | /* Several PSR bits have very specific dependencies. */ | |
7518 | switch (dep->regindex) | |
7519 | { | |
7520 | default: | |
7521 | specs[count++] = tmpl; | |
7522 | break; | |
7523 | case PSR_IC: | |
7524 | if (rsrc_write) | |
7525 | { | |
7526 | specs[count++] = tmpl; | |
7527 | } | |
7528 | else | |
7529 | { | |
7530 | /* Only certain CR accesses use PSR.ic */ | |
7531 | if (idesc->operands[0] == IA64_OPND_CR3 | |
7532 | || idesc->operands[1] == IA64_OPND_CR3) | |
7533 | { | |
7534 | int index = | |
7535 | ((idesc->operands[0] == IA64_OPND_CR3) | |
7536 | ? 0 : 1); | |
7537 | int regno = | |
7538 | CURR_SLOT.opnd[index].X_add_number - REG_CR; | |
7539 | ||
7540 | switch (regno) | |
7541 | { | |
7542 | default: | |
7543 | break; | |
7544 | case CR_ITIR: | |
7545 | case CR_IFS: | |
7546 | case CR_IIM: | |
7547 | case CR_IIP: | |
7548 | case CR_IPSR: | |
7549 | case CR_ISR: | |
7550 | case CR_IFA: | |
7551 | case CR_IHA: | |
7552 | case CR_IIPA: | |
7553 | specs[count++] = tmpl; | |
7554 | break; | |
7555 | } | |
7556 | } | |
7557 | } | |
7558 | break; | |
7559 | case PSR_CPL: | |
7560 | if (rsrc_write) | |
7561 | { | |
7562 | specs[count++] = tmpl; | |
7563 | } | |
7564 | else | |
7565 | { | |
7566 | /* Only some AR accesses use cpl */ | |
7567 | if (idesc->operands[0] == IA64_OPND_AR3 | |
7568 | || idesc->operands[1] == IA64_OPND_AR3) | |
7569 | { | |
7570 | int index = | |
7571 | ((idesc->operands[0] == IA64_OPND_AR3) | |
7572 | ? 0 : 1); | |
7573 | int regno = | |
7574 | CURR_SLOT.opnd[index].X_add_number - REG_AR; | |
7575 | ||
7576 | if (regno == AR_ITC | |
7577 | || (index == 0 | |
7578 | && (regno == AR_ITC | |
7579 | || regno == AR_RSC | |
7580 | || (regno >= AR_K0 | |
7581 | && regno <= AR_K7)))) | |
7582 | { | |
7583 | specs[count++] = tmpl; | |
7584 | } | |
7585 | } | |
7586 | else | |
7587 | { | |
7588 | specs[count++] = tmpl; | |
7589 | } | |
7590 | break; | |
7591 | } | |
7592 | } | |
7593 | } | |
7594 | } | |
800eeca4 | 7595 | else if (note == 7) |
542d6675 KH |
7596 | { |
7597 | valueT mask = 0; | |
7598 | if (idesc->operands[0] == IA64_OPND_IMMU24) | |
7599 | { | |
7600 | mask = CURR_SLOT.opnd[0].X_add_number; | |
7601 | } | |
7602 | else | |
7603 | { | |
7604 | UNHANDLED; | |
7605 | } | |
7606 | if (mask & ((valueT) 1 << dep->regindex)) | |
7607 | { | |
7608 | specs[count++] = tmpl; | |
7609 | } | |
7610 | } | |
800eeca4 | 7611 | else if (note == 8) |
542d6675 KH |
7612 | { |
7613 | int min = dep->regindex == PSR_DFL ? 2 : 32; | |
7614 | int max = dep->regindex == PSR_DFL ? 31 : 127; | |
7615 | /* dfh is read on FR32-127; dfl is read on FR2-31 */ | |
7616 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7617 | { | |
7618 | if (idesc->operands[i] == IA64_OPND_F1 | |
7619 | || idesc->operands[i] == IA64_OPND_F2 | |
7620 | || idesc->operands[i] == IA64_OPND_F3 | |
7621 | || idesc->operands[i] == IA64_OPND_F4) | |
7622 | { | |
7623 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7624 | if (reg >= min && reg <= max) | |
7625 | { | |
7626 | specs[count++] = tmpl; | |
7627 | } | |
7628 | } | |
7629 | } | |
7630 | } | |
800eeca4 | 7631 | else if (note == 9) |
542d6675 KH |
7632 | { |
7633 | int min = dep->regindex == PSR_MFL ? 2 : 32; | |
7634 | int max = dep->regindex == PSR_MFL ? 31 : 127; | |
7635 | /* mfh is read on writes to FR32-127; mfl is read on writes to | |
7636 | FR2-31 */ | |
7637 | for (i = 0; i < idesc->num_outputs; i++) | |
7638 | { | |
7639 | if (idesc->operands[i] == IA64_OPND_F1) | |
7640 | { | |
7641 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7642 | if (reg >= min && reg <= max) | |
7643 | { | |
7644 | specs[count++] = tmpl; | |
7645 | } | |
7646 | } | |
7647 | } | |
7648 | } | |
800eeca4 | 7649 | else if (note == 10) |
542d6675 KH |
7650 | { |
7651 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7652 | { | |
7653 | if (idesc->operands[i] == IA64_OPND_R1 | |
7654 | || idesc->operands[i] == IA64_OPND_R2 | |
7655 | || idesc->operands[i] == IA64_OPND_R3) | |
7656 | { | |
7657 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7658 | if (regno >= 16 && regno <= 31) | |
7659 | { | |
7660 | specs[count++] = tmpl; | |
7661 | } | |
7662 | } | |
7663 | } | |
7664 | } | |
800eeca4 | 7665 | else |
542d6675 KH |
7666 | { |
7667 | UNHANDLED; | |
7668 | } | |
800eeca4 JW |
7669 | break; |
7670 | ||
7671 | case IA64_RS_AR_FPSR: | |
7672 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
542d6675 KH |
7673 | { |
7674 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7675 | if (regno == AR_FPSR) | |
7676 | { | |
7677 | specs[count++] = tmpl; | |
7678 | } | |
7679 | } | |
800eeca4 | 7680 | else |
542d6675 KH |
7681 | { |
7682 | specs[count++] = tmpl; | |
7683 | } | |
800eeca4 JW |
7684 | break; |
7685 | ||
197865e8 | 7686 | case IA64_RS_ARX: |
800eeca4 JW |
7687 | /* Handle all AR[REG] resources */ |
7688 | if (note == 0 || note == 1) | |
542d6675 KH |
7689 | { |
7690 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7691 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 | |
7692 | && regno == dep->regindex) | |
7693 | { | |
7694 | specs[count++] = tmpl; | |
7695 | } | |
7696 | /* other AR[REG] resources may be affected by AR accesses */ | |
7697 | else if (idesc->operands[0] == IA64_OPND_AR3) | |
7698 | { | |
7699 | /* AR[] writes */ | |
7700 | regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; | |
7701 | switch (dep->regindex) | |
7702 | { | |
7703 | default: | |
7704 | break; | |
7705 | case AR_BSP: | |
7706 | case AR_RNAT: | |
7707 | if (regno == AR_BSPSTORE) | |
7708 | { | |
7709 | specs[count++] = tmpl; | |
7710 | } | |
7711 | case AR_RSC: | |
7712 | if (!rsrc_write && | |
7713 | (regno == AR_BSPSTORE | |
7714 | || regno == AR_RNAT)) | |
7715 | { | |
7716 | specs[count++] = tmpl; | |
7717 | } | |
7718 | break; | |
7719 | } | |
7720 | } | |
7721 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
7722 | { | |
7723 | /* AR[] reads */ | |
7724 | regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; | |
7725 | switch (dep->regindex) | |
7726 | { | |
7727 | default: | |
7728 | break; | |
7729 | case AR_RSC: | |
7730 | if (regno == AR_BSPSTORE || regno == AR_RNAT) | |
7731 | { | |
7732 | specs[count++] = tmpl; | |
7733 | } | |
7734 | break; | |
7735 | } | |
7736 | } | |
7737 | else | |
7738 | { | |
7739 | specs[count++] = tmpl; | |
7740 | } | |
7741 | } | |
800eeca4 | 7742 | else |
542d6675 KH |
7743 | { |
7744 | UNHANDLED; | |
7745 | } | |
800eeca4 JW |
7746 | break; |
7747 | ||
7748 | case IA64_RS_CRX: | |
7749 | /* Handle all CR[REG] resources */ | |
7750 | if (note == 0 || note == 1) | |
542d6675 KH |
7751 | { |
7752 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
7753 | { | |
7754 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7755 | if (regno == dep->regindex) | |
7756 | { | |
7757 | specs[count++] = tmpl; | |
7758 | } | |
7759 | else if (!rsrc_write) | |
7760 | { | |
7761 | /* Reads from CR[IVR] affect other resources. */ | |
7762 | if (regno == CR_IVR) | |
7763 | { | |
7764 | if ((dep->regindex >= CR_IRR0 | |
7765 | && dep->regindex <= CR_IRR3) | |
7766 | || dep->regindex == CR_TPR) | |
7767 | { | |
7768 | specs[count++] = tmpl; | |
7769 | } | |
7770 | } | |
7771 | } | |
7772 | } | |
7773 | else | |
7774 | { | |
7775 | specs[count++] = tmpl; | |
7776 | } | |
7777 | } | |
800eeca4 | 7778 | else |
542d6675 KH |
7779 | { |
7780 | UNHANDLED; | |
7781 | } | |
800eeca4 JW |
7782 | break; |
7783 | ||
7784 | case IA64_RS_INSERVICE: | |
7785 | /* look for write of EOI (67) or read of IVR (65) */ | |
7786 | if ((idesc->operands[0] == IA64_OPND_CR3 | |
542d6675 KH |
7787 | && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) |
7788 | || (idesc->operands[1] == IA64_OPND_CR3 | |
7789 | && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) | |
7790 | { | |
7791 | specs[count++] = tmpl; | |
7792 | } | |
800eeca4 JW |
7793 | break; |
7794 | ||
7795 | case IA64_RS_GR0: | |
7796 | if (note == 1) | |
542d6675 KH |
7797 | { |
7798 | specs[count++] = tmpl; | |
7799 | } | |
800eeca4 | 7800 | else |
542d6675 KH |
7801 | { |
7802 | UNHANDLED; | |
7803 | } | |
800eeca4 JW |
7804 | break; |
7805 | ||
7806 | case IA64_RS_CFM: | |
7807 | if (note != 2) | |
542d6675 KH |
7808 | { |
7809 | specs[count++] = tmpl; | |
7810 | } | |
800eeca4 | 7811 | else |
542d6675 KH |
7812 | { |
7813 | /* Check if any of the registers accessed are in the rotating region. | |
7814 | mov to/from pr accesses CFM only when qp_regno is in the rotating | |
7815 | region */ | |
7816 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7817 | { | |
7818 | if (idesc->operands[i] == IA64_OPND_R1 | |
7819 | || idesc->operands[i] == IA64_OPND_R2 | |
7820 | || idesc->operands[i] == IA64_OPND_R3) | |
7821 | { | |
7822 | int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7823 | /* Assumes that md.rot.num_regs is always valid */ | |
7824 | if (md.rot.num_regs > 0 | |
7825 | && num > 31 | |
7826 | && num < 31 + md.rot.num_regs) | |
7827 | { | |
7828 | specs[count] = tmpl; | |
7829 | specs[count++].specific = 0; | |
7830 | } | |
7831 | } | |
7832 | else if (idesc->operands[i] == IA64_OPND_F1 | |
7833 | || idesc->operands[i] == IA64_OPND_F2 | |
7834 | || idesc->operands[i] == IA64_OPND_F3 | |
7835 | || idesc->operands[i] == IA64_OPND_F4) | |
7836 | { | |
7837 | int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7838 | if (num > 31) | |
7839 | { | |
7840 | specs[count] = tmpl; | |
7841 | specs[count++].specific = 0; | |
7842 | } | |
7843 | } | |
7844 | else if (idesc->operands[i] == IA64_OPND_P1 | |
7845 | || idesc->operands[i] == IA64_OPND_P2) | |
7846 | { | |
7847 | int num = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
7848 | if (num > 15) | |
7849 | { | |
7850 | specs[count] = tmpl; | |
7851 | specs[count++].specific = 0; | |
7852 | } | |
7853 | } | |
7854 | } | |
7855 | if (CURR_SLOT.qp_regno > 15) | |
7856 | { | |
7857 | specs[count] = tmpl; | |
7858 | specs[count++].specific = 0; | |
7859 | } | |
7860 | } | |
800eeca4 JW |
7861 | break; |
7862 | ||
139368c9 JW |
7863 | /* This is the same as IA64_RS_PRr, except simplified to account for |
7864 | the fact that there is only one register. */ | |
800eeca4 JW |
7865 | case IA64_RS_PR63: |
7866 | if (note == 0) | |
542d6675 KH |
7867 | { |
7868 | specs[count++] = tmpl; | |
7869 | } | |
139368c9 JW |
7870 | else if (note == 7) |
7871 | { | |
7872 | valueT mask = 0; | |
7873 | if (idesc->operands[2] == IA64_OPND_IMM17) | |
7874 | mask = CURR_SLOT.opnd[2].X_add_number; | |
7875 | if (mask & ((valueT) 1 << 63)) | |
7876 | specs[count++] = tmpl; | |
7877 | } | |
800eeca4 | 7878 | else if (note == 11) |
542d6675 KH |
7879 | { |
7880 | if ((idesc->operands[0] == IA64_OPND_P1 | |
7881 | && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) | |
7882 | || (idesc->operands[1] == IA64_OPND_P2 | |
7883 | && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) | |
7884 | { | |
7885 | specs[count++] = tmpl; | |
7886 | } | |
7887 | } | |
800eeca4 | 7888 | else if (note == 12) |
542d6675 KH |
7889 | { |
7890 | if (CURR_SLOT.qp_regno == 63) | |
7891 | { | |
7892 | specs[count++] = tmpl; | |
7893 | } | |
7894 | } | |
800eeca4 | 7895 | else if (note == 1) |
542d6675 KH |
7896 | { |
7897 | if (rsrc_write) | |
7898 | { | |
7484b8e6 TW |
7899 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
7900 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
7901 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; | |
7902 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
7903 | ||
4a4f25cf | 7904 | if (p1 == 63 |
7484b8e6 TW |
7905 | && (idesc->operands[0] == IA64_OPND_P1 |
7906 | || idesc->operands[0] == IA64_OPND_P2)) | |
7907 | { | |
7908 | specs[count] = tmpl; | |
4a4f25cf | 7909 | specs[count++].cmp_type = |
7484b8e6 TW |
7910 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
7911 | } | |
7912 | if (p2 == 63 | |
7913 | && (idesc->operands[1] == IA64_OPND_P1 | |
7914 | || idesc->operands[1] == IA64_OPND_P2)) | |
7915 | { | |
7916 | specs[count] = tmpl; | |
4a4f25cf | 7917 | specs[count++].cmp_type = |
7484b8e6 TW |
7918 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
7919 | } | |
542d6675 KH |
7920 | } |
7921 | else | |
7922 | { | |
7923 | if (CURR_SLOT.qp_regno == 63) | |
7924 | { | |
7925 | specs[count++] = tmpl; | |
7926 | } | |
7927 | } | |
7928 | } | |
800eeca4 | 7929 | else |
542d6675 KH |
7930 | { |
7931 | UNHANDLED; | |
7932 | } | |
800eeca4 JW |
7933 | break; |
7934 | ||
7935 | case IA64_RS_RSE: | |
7936 | /* FIXME we can identify some individual RSE written resources, but RSE | |
542d6675 KH |
7937 | read resources have not yet been completely identified, so for now |
7938 | treat RSE as a single resource */ | |
800eeca4 | 7939 | if (strncmp (idesc->name, "mov", 3) == 0) |
542d6675 KH |
7940 | { |
7941 | if (rsrc_write) | |
7942 | { | |
7943 | if (idesc->operands[0] == IA64_OPND_AR3 | |
7944 | && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) | |
7945 | { | |
7946 | specs[count] = tmpl; | |
7947 | specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ | |
7948 | } | |
7949 | } | |
7950 | else | |
7951 | { | |
7952 | if (idesc->operands[0] == IA64_OPND_AR3) | |
7953 | { | |
7954 | if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE | |
7955 | || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) | |
7956 | { | |
7957 | specs[count++] = tmpl; | |
7958 | } | |
7959 | } | |
7960 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
7961 | { | |
7962 | if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP | |
7963 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE | |
7964 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) | |
7965 | { | |
7966 | specs[count++] = tmpl; | |
7967 | } | |
7968 | } | |
7969 | } | |
7970 | } | |
197865e8 | 7971 | else |
542d6675 KH |
7972 | { |
7973 | specs[count++] = tmpl; | |
7974 | } | |
800eeca4 JW |
7975 | break; |
7976 | ||
7977 | case IA64_RS_ANY: | |
7978 | /* FIXME -- do any of these need to be non-specific? */ | |
7979 | specs[count++] = tmpl; | |
7980 | break; | |
7981 | ||
7982 | default: | |
7983 | as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); | |
7984 | break; | |
7985 | } | |
7986 | ||
7987 | return count; | |
7988 | } | |
7989 | ||
7990 | /* Clear branch flags on marked resources. This breaks the link between the | |
542d6675 KH |
7991 | QP of the marking instruction and a subsequent branch on the same QP. */ |
7992 | ||
800eeca4 JW |
7993 | static void |
7994 | clear_qp_branch_flag (mask) | |
542d6675 | 7995 | valueT mask; |
800eeca4 JW |
7996 | { |
7997 | int i; | |
542d6675 | 7998 | for (i = 0; i < regdepslen; i++) |
800eeca4 | 7999 | { |
197865e8 | 8000 | valueT bit = ((valueT) 1 << regdeps[i].qp_regno); |
800eeca4 | 8001 | if ((bit & mask) != 0) |
542d6675 KH |
8002 | { |
8003 | regdeps[i].link_to_qp_branch = 0; | |
8004 | } | |
800eeca4 JW |
8005 | } |
8006 | } | |
8007 | ||
197865e8 | 8008 | /* Remove any mutexes which contain any of the PRs indicated in the mask. |
800eeca4 | 8009 | |
542d6675 KH |
8010 | Any changes to a PR clears the mutex relations which include that PR. */ |
8011 | ||
800eeca4 JW |
8012 | static void |
8013 | clear_qp_mutex (mask) | |
542d6675 | 8014 | valueT mask; |
800eeca4 JW |
8015 | { |
8016 | int i; | |
8017 | ||
8018 | i = 0; | |
8019 | while (i < qp_mutexeslen) | |
8020 | { | |
8021 | if ((qp_mutexes[i].prmask & mask) != 0) | |
542d6675 KH |
8022 | { |
8023 | if (md.debug_dv) | |
8024 | { | |
8025 | fprintf (stderr, " Clearing mutex relation"); | |
8026 | print_prmask (qp_mutexes[i].prmask); | |
8027 | fprintf (stderr, "\n"); | |
8028 | } | |
8029 | qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; | |
8030 | } | |
800eeca4 | 8031 | else |
542d6675 | 8032 | ++i; |
800eeca4 JW |
8033 | } |
8034 | } | |
8035 | ||
8036 | /* Clear implies relations which contain PRs in the given masks. | |
8037 | P1_MASK indicates the source of the implies relation, while P2_MASK | |
542d6675 KH |
8038 | indicates the implied PR. */ |
8039 | ||
800eeca4 JW |
8040 | static void |
8041 | clear_qp_implies (p1_mask, p2_mask) | |
542d6675 KH |
8042 | valueT p1_mask; |
8043 | valueT p2_mask; | |
800eeca4 JW |
8044 | { |
8045 | int i; | |
8046 | ||
8047 | i = 0; | |
8048 | while (i < qp_implieslen) | |
8049 | { | |
197865e8 | 8050 | if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 |
542d6675 KH |
8051 | || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) |
8052 | { | |
8053 | if (md.debug_dv) | |
8054 | fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", | |
8055 | qp_implies[i].p1, qp_implies[i].p2); | |
8056 | qp_implies[i] = qp_implies[--qp_implieslen]; | |
8057 | } | |
197865e8 | 8058 | else |
542d6675 | 8059 | ++i; |
800eeca4 JW |
8060 | } |
8061 | } | |
8062 | ||
542d6675 KH |
8063 | /* Add the PRs specified to the list of implied relations. */ |
8064 | ||
800eeca4 JW |
8065 | static void |
8066 | add_qp_imply (p1, p2) | |
542d6675 | 8067 | int p1, p2; |
800eeca4 JW |
8068 | { |
8069 | valueT mask; | |
8070 | valueT bit; | |
8071 | int i; | |
8072 | ||
542d6675 | 8073 | /* p0 is not meaningful here. */ |
800eeca4 JW |
8074 | if (p1 == 0 || p2 == 0) |
8075 | abort (); | |
8076 | ||
8077 | if (p1 == p2) | |
8078 | return; | |
8079 | ||
542d6675 KH |
8080 | /* If it exists already, ignore it. */ |
8081 | for (i = 0; i < qp_implieslen; i++) | |
800eeca4 | 8082 | { |
197865e8 | 8083 | if (qp_implies[i].p1 == p1 |
542d6675 KH |
8084 | && qp_implies[i].p2 == p2 |
8085 | && qp_implies[i].path == md.path | |
8086 | && !qp_implies[i].p2_branched) | |
8087 | return; | |
800eeca4 JW |
8088 | } |
8089 | ||
8090 | if (qp_implieslen == qp_impliestotlen) | |
8091 | { | |
8092 | qp_impliestotlen += 20; | |
8093 | qp_implies = (struct qp_imply *) | |
542d6675 KH |
8094 | xrealloc ((void *) qp_implies, |
8095 | qp_impliestotlen * sizeof (struct qp_imply)); | |
800eeca4 JW |
8096 | } |
8097 | if (md.debug_dv) | |
8098 | fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); | |
8099 | qp_implies[qp_implieslen].p1 = p1; | |
8100 | qp_implies[qp_implieslen].p2 = p2; | |
8101 | qp_implies[qp_implieslen].path = md.path; | |
8102 | qp_implies[qp_implieslen++].p2_branched = 0; | |
8103 | ||
8104 | /* Add in the implied transitive relations; for everything that p2 implies, | |
8105 | make p1 imply that, too; for everything that implies p1, make it imply p2 | |
197865e8 | 8106 | as well. */ |
542d6675 | 8107 | for (i = 0; i < qp_implieslen; i++) |
800eeca4 JW |
8108 | { |
8109 | if (qp_implies[i].p1 == p2) | |
542d6675 | 8110 | add_qp_imply (p1, qp_implies[i].p2); |
800eeca4 | 8111 | if (qp_implies[i].p2 == p1) |
542d6675 | 8112 | add_qp_imply (qp_implies[i].p1, p2); |
800eeca4 JW |
8113 | } |
8114 | /* Add in mutex relations implied by this implies relation; for each mutex | |
197865e8 KH |
8115 | relation containing p2, duplicate it and replace p2 with p1. */ |
8116 | bit = (valueT) 1 << p1; | |
8117 | mask = (valueT) 1 << p2; | |
542d6675 | 8118 | for (i = 0; i < qp_mutexeslen; i++) |
800eeca4 JW |
8119 | { |
8120 | if (qp_mutexes[i].prmask & mask) | |
542d6675 | 8121 | add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); |
800eeca4 JW |
8122 | } |
8123 | } | |
8124 | ||
800eeca4 JW |
8125 | /* Add the PRs specified in the mask to the mutex list; this means that only |
8126 | one of the PRs can be true at any time. PR0 should never be included in | |
8127 | the mask. */ | |
542d6675 | 8128 | |
800eeca4 JW |
8129 | static void |
8130 | add_qp_mutex (mask) | |
542d6675 | 8131 | valueT mask; |
800eeca4 JW |
8132 | { |
8133 | if (mask & 0x1) | |
8134 | abort (); | |
8135 | ||
8136 | if (qp_mutexeslen == qp_mutexestotlen) | |
8137 | { | |
8138 | qp_mutexestotlen += 20; | |
8139 | qp_mutexes = (struct qpmutex *) | |
542d6675 KH |
8140 | xrealloc ((void *) qp_mutexes, |
8141 | qp_mutexestotlen * sizeof (struct qpmutex)); | |
800eeca4 JW |
8142 | } |
8143 | if (md.debug_dv) | |
8144 | { | |
8145 | fprintf (stderr, " Registering mutex on"); | |
8146 | print_prmask (mask); | |
8147 | fprintf (stderr, "\n"); | |
8148 | } | |
8149 | qp_mutexes[qp_mutexeslen].path = md.path; | |
8150 | qp_mutexes[qp_mutexeslen++].prmask = mask; | |
8151 | } | |
8152 | ||
8153 | static void | |
8154 | clear_register_values () | |
8155 | { | |
8156 | int i; | |
8157 | if (md.debug_dv) | |
8158 | fprintf (stderr, " Clearing register values\n"); | |
542d6675 | 8159 | for (i = 1; i < NELEMS (gr_values); i++) |
800eeca4 JW |
8160 | gr_values[i].known = 0; |
8161 | } | |
8162 | ||
8163 | /* Keep track of register values/changes which affect DV tracking. | |
8164 | ||
8165 | optimization note: should add a flag to classes of insns where otherwise we | |
542d6675 | 8166 | have to examine a group of strings to identify them. */ |
800eeca4 | 8167 | |
800eeca4 JW |
8168 | static void |
8169 | note_register_values (idesc) | |
542d6675 | 8170 | struct ia64_opcode *idesc; |
800eeca4 JW |
8171 | { |
8172 | valueT qp_changemask = 0; | |
8173 | int i; | |
8174 | ||
542d6675 KH |
8175 | /* Invalidate values for registers being written to. */ |
8176 | for (i = 0; i < idesc->num_outputs; i++) | |
800eeca4 | 8177 | { |
197865e8 | 8178 | if (idesc->operands[i] == IA64_OPND_R1 |
542d6675 KH |
8179 | || idesc->operands[i] == IA64_OPND_R2 |
8180 | || idesc->operands[i] == IA64_OPND_R3) | |
8181 | { | |
8182 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8183 | if (regno > 0 && regno < NELEMS (gr_values)) | |
8184 | gr_values[regno].known = 0; | |
8185 | } | |
50b81f19 JW |
8186 | else if (idesc->operands[i] == IA64_OPND_R3_2) |
8187 | { | |
8188 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8189 | if (regno > 0 && regno < 4) | |
8190 | gr_values[regno].known = 0; | |
8191 | } | |
197865e8 | 8192 | else if (idesc->operands[i] == IA64_OPND_P1 |
542d6675 KH |
8193 | || idesc->operands[i] == IA64_OPND_P2) |
8194 | { | |
8195 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8196 | qp_changemask |= (valueT) 1 << regno; | |
8197 | } | |
800eeca4 | 8198 | else if (idesc->operands[i] == IA64_OPND_PR) |
542d6675 KH |
8199 | { |
8200 | if (idesc->operands[2] & (valueT) 0x10000) | |
8201 | qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; | |
8202 | else | |
8203 | qp_changemask = idesc->operands[2]; | |
8204 | break; | |
8205 | } | |
800eeca4 | 8206 | else if (idesc->operands[i] == IA64_OPND_PR_ROT) |
542d6675 KH |
8207 | { |
8208 | if (idesc->operands[1] & ((valueT) 1 << 43)) | |
8209 | qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; | |
8210 | else | |
8211 | qp_changemask = idesc->operands[1]; | |
8212 | qp_changemask &= ~(valueT) 0xFFFF; | |
8213 | break; | |
8214 | } | |
8215 | } | |
8216 | ||
8217 | /* Always clear qp branch flags on any PR change. */ | |
8218 | /* FIXME there may be exceptions for certain compares. */ | |
800eeca4 JW |
8219 | clear_qp_branch_flag (qp_changemask); |
8220 | ||
542d6675 | 8221 | /* Invalidate rotating registers on insns which affect RRBs in CFM. */ |
800eeca4 JW |
8222 | if (idesc->flags & IA64_OPCODE_MOD_RRBS) |
8223 | { | |
197865e8 | 8224 | qp_changemask |= ~(valueT) 0xFFFF; |
800eeca4 | 8225 | if (strcmp (idesc->name, "clrrrb.pr") != 0) |
542d6675 KH |
8226 | { |
8227 | for (i = 32; i < 32 + md.rot.num_regs; i++) | |
8228 | gr_values[i].known = 0; | |
8229 | } | |
800eeca4 JW |
8230 | clear_qp_mutex (qp_changemask); |
8231 | clear_qp_implies (qp_changemask, qp_changemask); | |
8232 | } | |
542d6675 KH |
8233 | /* After a call, all register values are undefined, except those marked |
8234 | as "safe". */ | |
800eeca4 | 8235 | else if (strncmp (idesc->name, "br.call", 6) == 0 |
542d6675 | 8236 | || strncmp (idesc->name, "brl.call", 7) == 0) |
800eeca4 | 8237 | { |
56d27c17 | 8238 | /* FIXME keep GR values which are marked as "safe_across_calls" */ |
800eeca4 JW |
8239 | clear_register_values (); |
8240 | clear_qp_mutex (~qp_safe_across_calls); | |
8241 | clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); | |
8242 | clear_qp_branch_flag (~qp_safe_across_calls); | |
8243 | } | |
e9718fe1 | 8244 | else if (is_interruption_or_rfi (idesc) |
542d6675 | 8245 | || is_taken_branch (idesc)) |
e9718fe1 TW |
8246 | { |
8247 | clear_register_values (); | |
197865e8 KH |
8248 | clear_qp_mutex (~(valueT) 0); |
8249 | clear_qp_implies (~(valueT) 0, ~(valueT) 0); | |
e9718fe1 | 8250 | } |
542d6675 | 8251 | /* Look for mutex and implies relations. */ |
197865e8 | 8252 | else if ((idesc->operands[0] == IA64_OPND_P1 |
542d6675 KH |
8253 | || idesc->operands[0] == IA64_OPND_P2) |
8254 | && (idesc->operands[1] == IA64_OPND_P1 | |
8255 | || idesc->operands[1] == IA64_OPND_P2)) | |
800eeca4 JW |
8256 | { |
8257 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
197865e8 KH |
8258 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
8259 | valueT p1mask = (valueT) 1 << p1; | |
8260 | valueT p2mask = (valueT) 1 << p2; | |
800eeca4 | 8261 | |
542d6675 | 8262 | /* If one of the PRs is PR0, we can't really do anything. */ |
800eeca4 | 8263 | if (p1 == 0 || p2 == 0) |
542d6675 KH |
8264 | { |
8265 | if (md.debug_dv) | |
8266 | fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); | |
8267 | } | |
800eeca4 | 8268 | /* In general, clear mutexes and implies which include P1 or P2, |
542d6675 | 8269 | with the following exceptions. */ |
800eeca4 | 8270 | else if (strstr (idesc->name, ".or.andcm") != NULL) |
542d6675 KH |
8271 | { |
8272 | add_qp_mutex (p1mask | p2mask); | |
8273 | clear_qp_implies (p2mask, p1mask); | |
8274 | } | |
800eeca4 | 8275 | else if (strstr (idesc->name, ".and.orcm") != NULL) |
542d6675 KH |
8276 | { |
8277 | add_qp_mutex (p1mask | p2mask); | |
8278 | clear_qp_implies (p1mask, p2mask); | |
8279 | } | |
800eeca4 | 8280 | else if (strstr (idesc->name, ".and") != NULL) |
542d6675 KH |
8281 | { |
8282 | clear_qp_implies (0, p1mask | p2mask); | |
8283 | } | |
800eeca4 | 8284 | else if (strstr (idesc->name, ".or") != NULL) |
542d6675 KH |
8285 | { |
8286 | clear_qp_mutex (p1mask | p2mask); | |
8287 | clear_qp_implies (p1mask | p2mask, 0); | |
8288 | } | |
800eeca4 | 8289 | else |
542d6675 KH |
8290 | { |
8291 | clear_qp_implies (p1mask | p2mask, p1mask | p2mask); | |
8292 | if (strstr (idesc->name, ".unc") != NULL) | |
8293 | { | |
8294 | add_qp_mutex (p1mask | p2mask); | |
8295 | if (CURR_SLOT.qp_regno != 0) | |
8296 | { | |
8297 | add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, | |
8298 | CURR_SLOT.qp_regno); | |
8299 | add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, | |
8300 | CURR_SLOT.qp_regno); | |
8301 | } | |
8302 | } | |
8303 | else if (CURR_SLOT.qp_regno == 0) | |
8304 | { | |
8305 | add_qp_mutex (p1mask | p2mask); | |
8306 | } | |
8307 | else | |
8308 | { | |
8309 | clear_qp_mutex (p1mask | p2mask); | |
8310 | } | |
8311 | } | |
8312 | } | |
8313 | /* Look for mov imm insns into GRs. */ | |
800eeca4 | 8314 | else if (idesc->operands[0] == IA64_OPND_R1 |
542d6675 KH |
8315 | && (idesc->operands[1] == IA64_OPND_IMM22 |
8316 | || idesc->operands[1] == IA64_OPND_IMMU64) | |
8317 | && (strcmp (idesc->name, "mov") == 0 | |
8318 | || strcmp (idesc->name, "movl") == 0)) | |
800eeca4 JW |
8319 | { |
8320 | int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
542d6675 KH |
8321 | if (regno > 0 && regno < NELEMS (gr_values)) |
8322 | { | |
8323 | gr_values[regno].known = 1; | |
8324 | gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; | |
8325 | gr_values[regno].path = md.path; | |
8326 | if (md.debug_dv) | |
2434f565 JW |
8327 | { |
8328 | fprintf (stderr, " Know gr%d = ", regno); | |
8329 | fprintf_vma (stderr, gr_values[regno].value); | |
8330 | fputs ("\n", stderr); | |
8331 | } | |
542d6675 | 8332 | } |
800eeca4 | 8333 | } |
197865e8 | 8334 | else |
800eeca4 JW |
8335 | { |
8336 | clear_qp_mutex (qp_changemask); | |
8337 | clear_qp_implies (qp_changemask, qp_changemask); | |
8338 | } | |
8339 | } | |
8340 | ||
542d6675 KH |
8341 | /* Return whether the given predicate registers are currently mutex. */ |
8342 | ||
800eeca4 JW |
8343 | static int |
8344 | qp_mutex (p1, p2, path) | |
542d6675 KH |
8345 | int p1; |
8346 | int p2; | |
8347 | int path; | |
800eeca4 JW |
8348 | { |
8349 | int i; | |
8350 | valueT mask; | |
8351 | ||
8352 | if (p1 != p2) | |
8353 | { | |
542d6675 KH |
8354 | mask = ((valueT) 1 << p1) | (valueT) 1 << p2; |
8355 | for (i = 0; i < qp_mutexeslen; i++) | |
8356 | { | |
8357 | if (qp_mutexes[i].path >= path | |
8358 | && (qp_mutexes[i].prmask & mask) == mask) | |
8359 | return 1; | |
8360 | } | |
800eeca4 JW |
8361 | } |
8362 | return 0; | |
8363 | } | |
8364 | ||
8365 | /* Return whether the given resource is in the given insn's list of chks | |
8366 | Return 1 if the conflict is absolutely determined, 2 if it's a potential | |
542d6675 KH |
8367 | conflict. */ |
8368 | ||
800eeca4 JW |
8369 | static int |
8370 | resources_match (rs, idesc, note, qp_regno, path) | |
542d6675 KH |
8371 | struct rsrc *rs; |
8372 | struct ia64_opcode *idesc; | |
8373 | int note; | |
8374 | int qp_regno; | |
8375 | int path; | |
800eeca4 JW |
8376 | { |
8377 | struct rsrc specs[MAX_SPECS]; | |
8378 | int count; | |
8379 | ||
8380 | /* If the marked resource's qp_regno and the given qp_regno are mutex, | |
8381 | we don't need to check. One exception is note 11, which indicates that | |
8382 | target predicates are written regardless of PR[qp]. */ | |
197865e8 | 8383 | if (qp_mutex (rs->qp_regno, qp_regno, path) |
800eeca4 JW |
8384 | && note != 11) |
8385 | return 0; | |
8386 | ||
8387 | count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); | |
8388 | while (count-- > 0) | |
8389 | { | |
8390 | /* UNAT checking is a bit more specific than other resources */ | |
8391 | if (rs->dependency->specifier == IA64_RS_AR_UNAT | |
542d6675 KH |
8392 | && specs[count].mem_offset.hint |
8393 | && rs->mem_offset.hint) | |
8394 | { | |
8395 | if (rs->mem_offset.base == specs[count].mem_offset.base) | |
8396 | { | |
8397 | if (((rs->mem_offset.offset >> 3) & 0x3F) == | |
8398 | ((specs[count].mem_offset.offset >> 3) & 0x3F)) | |
8399 | return 1; | |
8400 | else | |
8401 | continue; | |
8402 | } | |
8403 | } | |
800eeca4 | 8404 | |
7484b8e6 | 8405 | /* Skip apparent PR write conflicts where both writes are an AND or both |
4a4f25cf | 8406 | writes are an OR. */ |
7484b8e6 | 8407 | if (rs->dependency->specifier == IA64_RS_PR |
afa680f8 | 8408 | || rs->dependency->specifier == IA64_RS_PRr |
7484b8e6 TW |
8409 | || rs->dependency->specifier == IA64_RS_PR63) |
8410 | { | |
8411 | if (specs[count].cmp_type != CMP_NONE | |
8412 | && specs[count].cmp_type == rs->cmp_type) | |
8413 | { | |
8414 | if (md.debug_dv) | |
8415 | fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", | |
8416 | dv_mode[rs->dependency->mode], | |
afa680f8 | 8417 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 TW |
8418 | specs[count].index : 63); |
8419 | continue; | |
8420 | } | |
8421 | if (md.debug_dv) | |
4a4f25cf | 8422 | fprintf (stderr, |
7484b8e6 TW |
8423 | " %s on parallel compare conflict %s vs %s on PR%d\n", |
8424 | dv_mode[rs->dependency->mode], | |
4a4f25cf | 8425 | dv_cmp_type[rs->cmp_type], |
7484b8e6 | 8426 | dv_cmp_type[specs[count].cmp_type], |
afa680f8 | 8427 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 | 8428 | specs[count].index : 63); |
4a4f25cf | 8429 | |
7484b8e6 TW |
8430 | } |
8431 | ||
800eeca4 | 8432 | /* If either resource is not specific, conservatively assume a conflict |
197865e8 | 8433 | */ |
800eeca4 | 8434 | if (!specs[count].specific || !rs->specific) |
542d6675 | 8435 | return 2; |
800eeca4 | 8436 | else if (specs[count].index == rs->index) |
542d6675 | 8437 | return 1; |
800eeca4 JW |
8438 | } |
8439 | #if 0 | |
8440 | if (md.debug_dv) | |
8441 | fprintf (stderr, " No %s conflicts\n", rs->dependency->name); | |
8442 | #endif | |
8443 | ||
8444 | return 0; | |
8445 | } | |
8446 | ||
8447 | /* Indicate an instruction group break; if INSERT_STOP is non-zero, then | |
8448 | insert a stop to create the break. Update all resource dependencies | |
8449 | appropriately. If QP_REGNO is non-zero, only apply the break to resources | |
8450 | which use the same QP_REGNO and have the link_to_qp_branch flag set. | |
8451 | If SAVE_CURRENT is non-zero, don't affect resources marked by the current | |
542d6675 | 8452 | instruction. */ |
800eeca4 JW |
8453 | |
8454 | static void | |
8455 | insn_group_break (insert_stop, qp_regno, save_current) | |
542d6675 KH |
8456 | int insert_stop; |
8457 | int qp_regno; | |
8458 | int save_current; | |
800eeca4 JW |
8459 | { |
8460 | int i; | |
8461 | ||
8462 | if (insert_stop && md.num_slots_in_use > 0) | |
8463 | PREV_SLOT.end_of_insn_group = 1; | |
8464 | ||
8465 | if (md.debug_dv) | |
8466 | { | |
197865e8 | 8467 | fprintf (stderr, " Insn group break%s", |
542d6675 | 8468 | (insert_stop ? " (w/stop)" : "")); |
800eeca4 | 8469 | if (qp_regno != 0) |
542d6675 | 8470 | fprintf (stderr, " effective for QP=%d", qp_regno); |
800eeca4 JW |
8471 | fprintf (stderr, "\n"); |
8472 | } | |
8473 | ||
8474 | i = 0; | |
8475 | while (i < regdepslen) | |
8476 | { | |
8477 | const struct ia64_dependency *dep = regdeps[i].dependency; | |
8478 | ||
8479 | if (qp_regno != 0 | |
542d6675 KH |
8480 | && regdeps[i].qp_regno != qp_regno) |
8481 | { | |
8482 | ++i; | |
8483 | continue; | |
8484 | } | |
800eeca4 JW |
8485 | |
8486 | if (save_current | |
542d6675 KH |
8487 | && CURR_SLOT.src_file == regdeps[i].file |
8488 | && CURR_SLOT.src_line == regdeps[i].line) | |
8489 | { | |
8490 | ++i; | |
8491 | continue; | |
8492 | } | |
800eeca4 JW |
8493 | |
8494 | /* clear dependencies which are automatically cleared by a stop, or | |
542d6675 | 8495 | those that have reached the appropriate state of insn serialization */ |
800eeca4 | 8496 | if (dep->semantics == IA64_DVS_IMPLIED |
542d6675 KH |
8497 | || dep->semantics == IA64_DVS_IMPLIEDF |
8498 | || regdeps[i].insn_srlz == STATE_SRLZ) | |
8499 | { | |
8500 | print_dependency ("Removing", i); | |
8501 | regdeps[i] = regdeps[--regdepslen]; | |
8502 | } | |
800eeca4 | 8503 | else |
542d6675 KH |
8504 | { |
8505 | if (dep->semantics == IA64_DVS_DATA | |
8506 | || dep->semantics == IA64_DVS_INSTR | |
800eeca4 | 8507 | || dep->semantics == IA64_DVS_SPECIFIC) |
542d6675 KH |
8508 | { |
8509 | if (regdeps[i].insn_srlz == STATE_NONE) | |
8510 | regdeps[i].insn_srlz = STATE_STOP; | |
8511 | if (regdeps[i].data_srlz == STATE_NONE) | |
8512 | regdeps[i].data_srlz = STATE_STOP; | |
8513 | } | |
8514 | ++i; | |
8515 | } | |
800eeca4 JW |
8516 | } |
8517 | } | |
8518 | ||
542d6675 KH |
8519 | /* Add the given resource usage spec to the list of active dependencies. */ |
8520 | ||
197865e8 | 8521 | static void |
800eeca4 | 8522 | mark_resource (idesc, dep, spec, depind, path) |
2434f565 JW |
8523 | struct ia64_opcode *idesc ATTRIBUTE_UNUSED; |
8524 | const struct ia64_dependency *dep ATTRIBUTE_UNUSED; | |
542d6675 KH |
8525 | struct rsrc *spec; |
8526 | int depind; | |
8527 | int path; | |
800eeca4 JW |
8528 | { |
8529 | if (regdepslen == regdepstotlen) | |
8530 | { | |
8531 | regdepstotlen += 20; | |
8532 | regdeps = (struct rsrc *) | |
542d6675 | 8533 | xrealloc ((void *) regdeps, |
bc805888 | 8534 | regdepstotlen * sizeof (struct rsrc)); |
800eeca4 JW |
8535 | } |
8536 | ||
8537 | regdeps[regdepslen] = *spec; | |
8538 | regdeps[regdepslen].depind = depind; | |
8539 | regdeps[regdepslen].path = path; | |
8540 | regdeps[regdepslen].file = CURR_SLOT.src_file; | |
8541 | regdeps[regdepslen].line = CURR_SLOT.src_line; | |
8542 | ||
8543 | print_dependency ("Adding", regdepslen); | |
8544 | ||
8545 | ++regdepslen; | |
8546 | } | |
8547 | ||
8548 | static void | |
8549 | print_dependency (action, depind) | |
542d6675 KH |
8550 | const char *action; |
8551 | int depind; | |
800eeca4 JW |
8552 | { |
8553 | if (md.debug_dv) | |
8554 | { | |
197865e8 | 8555 | fprintf (stderr, " %s %s '%s'", |
542d6675 KH |
8556 | action, dv_mode[(regdeps[depind].dependency)->mode], |
8557 | (regdeps[depind].dependency)->name); | |
800eeca4 | 8558 | if (regdeps[depind].specific && regdeps[depind].index != 0) |
542d6675 | 8559 | fprintf (stderr, " (%d)", regdeps[depind].index); |
800eeca4 | 8560 | if (regdeps[depind].mem_offset.hint) |
2434f565 JW |
8561 | { |
8562 | fputs (" ", stderr); | |
8563 | fprintf_vma (stderr, regdeps[depind].mem_offset.base); | |
8564 | fputs ("+", stderr); | |
8565 | fprintf_vma (stderr, regdeps[depind].mem_offset.offset); | |
8566 | } | |
800eeca4 JW |
8567 | fprintf (stderr, "\n"); |
8568 | } | |
8569 | } | |
8570 | ||
8571 | static void | |
8572 | instruction_serialization () | |
8573 | { | |
8574 | int i; | |
8575 | if (md.debug_dv) | |
8576 | fprintf (stderr, " Instruction serialization\n"); | |
542d6675 | 8577 | for (i = 0; i < regdepslen; i++) |
800eeca4 JW |
8578 | if (regdeps[i].insn_srlz == STATE_STOP) |
8579 | regdeps[i].insn_srlz = STATE_SRLZ; | |
8580 | } | |
8581 | ||
8582 | static void | |
8583 | data_serialization () | |
8584 | { | |
8585 | int i = 0; | |
8586 | if (md.debug_dv) | |
8587 | fprintf (stderr, " Data serialization\n"); | |
8588 | while (i < regdepslen) | |
8589 | { | |
8590 | if (regdeps[i].data_srlz == STATE_STOP | |
542d6675 KH |
8591 | /* Note: as of 991210, all "other" dependencies are cleared by a |
8592 | data serialization. This might change with new tables */ | |
8593 | || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) | |
8594 | { | |
8595 | print_dependency ("Removing", i); | |
8596 | regdeps[i] = regdeps[--regdepslen]; | |
8597 | } | |
800eeca4 | 8598 | else |
542d6675 | 8599 | ++i; |
800eeca4 JW |
8600 | } |
8601 | } | |
8602 | ||
542d6675 KH |
8603 | /* Insert stops and serializations as needed to avoid DVs. */ |
8604 | ||
800eeca4 JW |
8605 | static void |
8606 | remove_marked_resource (rs) | |
542d6675 | 8607 | struct rsrc *rs; |
800eeca4 JW |
8608 | { |
8609 | switch (rs->dependency->semantics) | |
8610 | { | |
8611 | case IA64_DVS_SPECIFIC: | |
8612 | if (md.debug_dv) | |
8613 | fprintf (stderr, "Implementation-specific, assume worst case...\n"); | |
197865e8 | 8614 | /* ...fall through... */ |
800eeca4 JW |
8615 | case IA64_DVS_INSTR: |
8616 | if (md.debug_dv) | |
542d6675 | 8617 | fprintf (stderr, "Inserting instr serialization\n"); |
800eeca4 | 8618 | if (rs->insn_srlz < STATE_STOP) |
542d6675 | 8619 | insn_group_break (1, 0, 0); |
800eeca4 | 8620 | if (rs->insn_srlz < STATE_SRLZ) |
542d6675 KH |
8621 | { |
8622 | int oldqp = CURR_SLOT.qp_regno; | |
8623 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
8624 | /* Manually jam a srlz.i insn into the stream */ | |
8625 | CURR_SLOT.qp_regno = 0; | |
8626 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); | |
8627 | instruction_serialization (); | |
8628 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
8629 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
8630 | emit_one_bundle (); | |
8631 | CURR_SLOT.qp_regno = oldqp; | |
8632 | CURR_SLOT.idesc = oldidesc; | |
8633 | } | |
800eeca4 JW |
8634 | insn_group_break (1, 0, 0); |
8635 | break; | |
8636 | case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all | |
542d6675 KH |
8637 | "other" types of DV are eliminated |
8638 | by a data serialization */ | |
800eeca4 JW |
8639 | case IA64_DVS_DATA: |
8640 | if (md.debug_dv) | |
542d6675 | 8641 | fprintf (stderr, "Inserting data serialization\n"); |
800eeca4 | 8642 | if (rs->data_srlz < STATE_STOP) |
542d6675 | 8643 | insn_group_break (1, 0, 0); |
800eeca4 | 8644 | { |
542d6675 KH |
8645 | int oldqp = CURR_SLOT.qp_regno; |
8646 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
8647 | /* Manually jam a srlz.d insn into the stream */ | |
8648 | CURR_SLOT.qp_regno = 0; | |
8649 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); | |
8650 | data_serialization (); | |
8651 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
8652 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
8653 | emit_one_bundle (); | |
8654 | CURR_SLOT.qp_regno = oldqp; | |
8655 | CURR_SLOT.idesc = oldidesc; | |
800eeca4 JW |
8656 | } |
8657 | break; | |
8658 | case IA64_DVS_IMPLIED: | |
8659 | case IA64_DVS_IMPLIEDF: | |
8660 | if (md.debug_dv) | |
542d6675 | 8661 | fprintf (stderr, "Inserting stop\n"); |
800eeca4 JW |
8662 | insn_group_break (1, 0, 0); |
8663 | break; | |
8664 | default: | |
8665 | break; | |
8666 | } | |
8667 | } | |
8668 | ||
8669 | /* Check the resources used by the given opcode against the current dependency | |
197865e8 | 8670 | list. |
800eeca4 JW |
8671 | |
8672 | The check is run once for each execution path encountered. In this case, | |
8673 | a unique execution path is the sequence of instructions following a code | |
8674 | entry point, e.g. the following has three execution paths, one starting | |
8675 | at L0, one at L1, and one at L2. | |
197865e8 | 8676 | |
800eeca4 JW |
8677 | L0: nop |
8678 | L1: add | |
8679 | L2: add | |
197865e8 | 8680 | br.ret |
800eeca4 | 8681 | */ |
542d6675 | 8682 | |
800eeca4 JW |
8683 | static void |
8684 | check_dependencies (idesc) | |
542d6675 | 8685 | struct ia64_opcode *idesc; |
800eeca4 JW |
8686 | { |
8687 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
8688 | int path; | |
8689 | int i; | |
8690 | ||
8691 | /* Note that the number of marked resources may change within the | |
197865e8 | 8692 | loop if in auto mode. */ |
800eeca4 JW |
8693 | i = 0; |
8694 | while (i < regdepslen) | |
8695 | { | |
8696 | struct rsrc *rs = ®deps[i]; | |
8697 | const struct ia64_dependency *dep = rs->dependency; | |
8698 | int chkind; | |
8699 | int note; | |
8700 | int start_over = 0; | |
8701 | ||
8702 | if (dep->semantics == IA64_DVS_NONE | |
542d6675 KH |
8703 | || (chkind = depends_on (rs->depind, idesc)) == -1) |
8704 | { | |
8705 | ++i; | |
8706 | continue; | |
8707 | } | |
8708 | ||
8709 | note = NOTE (opdeps->chks[chkind]); | |
8710 | ||
8711 | /* Check this resource against each execution path seen thus far. */ | |
8712 | for (path = 0; path <= md.path; path++) | |
8713 | { | |
8714 | int matchtype; | |
8715 | ||
8716 | /* If the dependency wasn't on the path being checked, ignore it. */ | |
8717 | if (rs->path < path) | |
8718 | continue; | |
8719 | ||
8720 | /* If the QP for this insn implies a QP which has branched, don't | |
8721 | bother checking. Ed. NOTE: I don't think this check is terribly | |
8722 | useful; what's the point of generating code which will only be | |
8723 | reached if its QP is zero? | |
8724 | This code was specifically inserted to handle the following code, | |
8725 | based on notes from Intel's DV checking code, where p1 implies p2. | |
8726 | ||
8727 | mov r4 = 2 | |
8728 | (p2) br.cond L | |
8729 | (p1) mov r4 = 7 | |
8730 | */ | |
8731 | if (CURR_SLOT.qp_regno != 0) | |
8732 | { | |
8733 | int skip = 0; | |
8734 | int implies; | |
8735 | for (implies = 0; implies < qp_implieslen; implies++) | |
8736 | { | |
8737 | if (qp_implies[implies].path >= path | |
8738 | && qp_implies[implies].p1 == CURR_SLOT.qp_regno | |
8739 | && qp_implies[implies].p2_branched) | |
8740 | { | |
8741 | skip = 1; | |
8742 | break; | |
8743 | } | |
8744 | } | |
8745 | if (skip) | |
8746 | continue; | |
8747 | } | |
8748 | ||
8749 | if ((matchtype = resources_match (rs, idesc, note, | |
8750 | CURR_SLOT.qp_regno, path)) != 0) | |
8751 | { | |
8752 | char msg[1024]; | |
8753 | char pathmsg[256] = ""; | |
8754 | char indexmsg[256] = ""; | |
8755 | int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); | |
8756 | ||
8757 | if (path != 0) | |
8758 | sprintf (pathmsg, " when entry is at label '%s'", | |
8759 | md.entry_labels[path - 1]); | |
8760 | if (rs->specific && rs->index != 0) | |
8761 | sprintf (indexmsg, ", specific resource number is %d", | |
8762 | rs->index); | |
8763 | sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", | |
8764 | idesc->name, | |
8765 | (certain ? "violates" : "may violate"), | |
8766 | dv_mode[dep->mode], dep->name, | |
8767 | dv_sem[dep->semantics], | |
8768 | pathmsg, indexmsg); | |
8769 | ||
8770 | if (md.explicit_mode) | |
8771 | { | |
8772 | as_warn ("%s", msg); | |
8773 | if (path < md.path) | |
8774 | as_warn (_("Only the first path encountering the conflict " | |
8775 | "is reported")); | |
8776 | as_warn_where (rs->file, rs->line, | |
8777 | _("This is the location of the " | |
8778 | "conflicting usage")); | |
8779 | /* Don't bother checking other paths, to avoid duplicating | |
8780 | the same warning */ | |
8781 | break; | |
8782 | } | |
8783 | else | |
8784 | { | |
8785 | if (md.debug_dv) | |
8786 | fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); | |
8787 | ||
8788 | remove_marked_resource (rs); | |
8789 | ||
8790 | /* since the set of dependencies has changed, start over */ | |
8791 | /* FIXME -- since we're removing dvs as we go, we | |
8792 | probably don't really need to start over... */ | |
8793 | start_over = 1; | |
8794 | break; | |
8795 | } | |
8796 | } | |
8797 | } | |
800eeca4 | 8798 | if (start_over) |
542d6675 | 8799 | i = 0; |
800eeca4 | 8800 | else |
542d6675 | 8801 | ++i; |
800eeca4 JW |
8802 | } |
8803 | } | |
8804 | ||
542d6675 KH |
8805 | /* Register new dependencies based on the given opcode. */ |
8806 | ||
800eeca4 JW |
8807 | static void |
8808 | mark_resources (idesc) | |
542d6675 | 8809 | struct ia64_opcode *idesc; |
800eeca4 JW |
8810 | { |
8811 | int i; | |
8812 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
8813 | int add_only_qp_reads = 0; | |
8814 | ||
8815 | /* A conditional branch only uses its resources if it is taken; if it is | |
8816 | taken, we stop following that path. The other branch types effectively | |
8817 | *always* write their resources. If it's not taken, register only QP | |
197865e8 | 8818 | reads. */ |
800eeca4 JW |
8819 | if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) |
8820 | { | |
8821 | add_only_qp_reads = 1; | |
8822 | } | |
8823 | ||
8824 | if (md.debug_dv) | |
8825 | fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); | |
8826 | ||
542d6675 | 8827 | for (i = 0; i < opdeps->nregs; i++) |
800eeca4 JW |
8828 | { |
8829 | const struct ia64_dependency *dep; | |
8830 | struct rsrc specs[MAX_SPECS]; | |
8831 | int note; | |
8832 | int path; | |
8833 | int count; | |
197865e8 | 8834 | |
800eeca4 | 8835 | dep = ia64_find_dependency (opdeps->regs[i]); |
542d6675 | 8836 | note = NOTE (opdeps->regs[i]); |
800eeca4 JW |
8837 | |
8838 | if (add_only_qp_reads | |
542d6675 KH |
8839 | && !(dep->mode == IA64_DV_WAR |
8840 | && (dep->specifier == IA64_RS_PR | |
139368c9 | 8841 | || dep->specifier == IA64_RS_PRr |
542d6675 KH |
8842 | || dep->specifier == IA64_RS_PR63))) |
8843 | continue; | |
800eeca4 JW |
8844 | |
8845 | count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); | |
8846 | ||
8847 | #if 0 | |
8848 | if (md.debug_dv && !count) | |
542d6675 KH |
8849 | fprintf (stderr, " No %s %s usage found (path %d)\n", |
8850 | dv_mode[dep->mode], dep->name, md.path); | |
800eeca4 | 8851 | #endif |
197865e8 | 8852 | |
800eeca4 | 8853 | while (count-- > 0) |
542d6675 KH |
8854 | { |
8855 | mark_resource (idesc, dep, &specs[count], | |
8856 | DEP (opdeps->regs[i]), md.path); | |
8857 | } | |
800eeca4 JW |
8858 | |
8859 | /* The execution path may affect register values, which may in turn | |
542d6675 | 8860 | affect which indirect-access resources are accessed. */ |
800eeca4 | 8861 | switch (dep->specifier) |
542d6675 KH |
8862 | { |
8863 | default: | |
8864 | break; | |
8865 | case IA64_RS_CPUID: | |
8866 | case IA64_RS_DBR: | |
8867 | case IA64_RS_IBR: | |
800eeca4 | 8868 | case IA64_RS_MSR: |
542d6675 KH |
8869 | case IA64_RS_PKR: |
8870 | case IA64_RS_PMC: | |
8871 | case IA64_RS_PMD: | |
8872 | case IA64_RS_RR: | |
8873 | for (path = 0; path < md.path; path++) | |
8874 | { | |
8875 | count = specify_resource (dep, idesc, DV_REG, specs, note, path); | |
8876 | while (count-- > 0) | |
8877 | mark_resource (idesc, dep, &specs[count], | |
8878 | DEP (opdeps->regs[i]), path); | |
8879 | } | |
8880 | break; | |
8881 | } | |
8882 | } | |
8883 | } | |
8884 | ||
8885 | /* Remove dependencies when they no longer apply. */ | |
8886 | ||
800eeca4 JW |
8887 | static void |
8888 | update_dependencies (idesc) | |
542d6675 | 8889 | struct ia64_opcode *idesc; |
800eeca4 JW |
8890 | { |
8891 | int i; | |
8892 | ||
8893 | if (strcmp (idesc->name, "srlz.i") == 0) | |
8894 | { | |
8895 | instruction_serialization (); | |
8896 | } | |
8897 | else if (strcmp (idesc->name, "srlz.d") == 0) | |
8898 | { | |
8899 | data_serialization (); | |
8900 | } | |
8901 | else if (is_interruption_or_rfi (idesc) | |
542d6675 | 8902 | || is_taken_branch (idesc)) |
800eeca4 | 8903 | { |
542d6675 KH |
8904 | /* Although technically the taken branch doesn't clear dependencies |
8905 | which require a srlz.[id], we don't follow the branch; the next | |
8906 | instruction is assumed to start with a clean slate. */ | |
800eeca4 | 8907 | regdepslen = 0; |
800eeca4 JW |
8908 | md.path = 0; |
8909 | } | |
8910 | else if (is_conditional_branch (idesc) | |
542d6675 | 8911 | && CURR_SLOT.qp_regno != 0) |
800eeca4 JW |
8912 | { |
8913 | int is_call = strstr (idesc->name, ".call") != NULL; | |
8914 | ||
542d6675 KH |
8915 | for (i = 0; i < qp_implieslen; i++) |
8916 | { | |
8917 | /* If the conditional branch's predicate is implied by the predicate | |
8918 | in an existing dependency, remove that dependency. */ | |
8919 | if (qp_implies[i].p2 == CURR_SLOT.qp_regno) | |
8920 | { | |
8921 | int depind = 0; | |
8922 | /* Note that this implied predicate takes a branch so that if | |
8923 | a later insn generates a DV but its predicate implies this | |
8924 | one, we can avoid the false DV warning. */ | |
8925 | qp_implies[i].p2_branched = 1; | |
8926 | while (depind < regdepslen) | |
8927 | { | |
8928 | if (regdeps[depind].qp_regno == qp_implies[i].p1) | |
8929 | { | |
8930 | print_dependency ("Removing", depind); | |
8931 | regdeps[depind] = regdeps[--regdepslen]; | |
8932 | } | |
8933 | else | |
8934 | ++depind; | |
8935 | } | |
8936 | } | |
8937 | } | |
800eeca4 | 8938 | /* Any marked resources which have this same predicate should be |
542d6675 KH |
8939 | cleared, provided that the QP hasn't been modified between the |
8940 | marking instruction and the branch. */ | |
800eeca4 | 8941 | if (is_call) |
542d6675 KH |
8942 | { |
8943 | insn_group_break (0, CURR_SLOT.qp_regno, 1); | |
8944 | } | |
800eeca4 | 8945 | else |
542d6675 KH |
8946 | { |
8947 | i = 0; | |
8948 | while (i < regdepslen) | |
8949 | { | |
8950 | if (regdeps[i].qp_regno == CURR_SLOT.qp_regno | |
8951 | && regdeps[i].link_to_qp_branch | |
8952 | && (regdeps[i].file != CURR_SLOT.src_file | |
8953 | || regdeps[i].line != CURR_SLOT.src_line)) | |
8954 | { | |
8955 | /* Treat like a taken branch */ | |
8956 | print_dependency ("Removing", i); | |
8957 | regdeps[i] = regdeps[--regdepslen]; | |
8958 | } | |
8959 | else | |
8960 | ++i; | |
8961 | } | |
8962 | } | |
800eeca4 JW |
8963 | } |
8964 | } | |
8965 | ||
8966 | /* Examine the current instruction for dependency violations. */ | |
542d6675 | 8967 | |
800eeca4 JW |
8968 | static int |
8969 | check_dv (idesc) | |
542d6675 | 8970 | struct ia64_opcode *idesc; |
800eeca4 JW |
8971 | { |
8972 | if (md.debug_dv) | |
8973 | { | |
197865e8 | 8974 | fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", |
542d6675 KH |
8975 | idesc->name, CURR_SLOT.src_line, |
8976 | idesc->dependencies->nchks, | |
8977 | idesc->dependencies->nregs); | |
800eeca4 JW |
8978 | } |
8979 | ||
197865e8 | 8980 | /* Look through the list of currently marked resources; if the current |
800eeca4 | 8981 | instruction has the dependency in its chks list which uses that resource, |
542d6675 | 8982 | check against the specific resources used. */ |
800eeca4 JW |
8983 | check_dependencies (idesc); |
8984 | ||
542d6675 KH |
8985 | /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), |
8986 | then add them to the list of marked resources. */ | |
800eeca4 JW |
8987 | mark_resources (idesc); |
8988 | ||
8989 | /* There are several types of dependency semantics, and each has its own | |
197865e8 KH |
8990 | requirements for being cleared |
8991 | ||
800eeca4 JW |
8992 | Instruction serialization (insns separated by interruption, rfi, or |
8993 | writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. | |
8994 | ||
8995 | Data serialization (instruction serialization, or writer + srlz.d + | |
8996 | reader, where writer and srlz.d are in separate groups) clears | |
8997 | DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to | |
8998 | always be the case). | |
8999 | ||
9000 | Instruction group break (groups separated by stop, taken branch, | |
9001 | interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. | |
9002 | */ | |
9003 | update_dependencies (idesc); | |
9004 | ||
9005 | /* Sometimes, knowing a register value allows us to avoid giving a false DV | |
197865e8 | 9006 | warning. Keep track of as many as possible that are useful. */ |
800eeca4 JW |
9007 | note_register_values (idesc); |
9008 | ||
197865e8 | 9009 | /* We don't need or want this anymore. */ |
800eeca4 JW |
9010 | md.mem_offset.hint = 0; |
9011 | ||
9012 | return 0; | |
9013 | } | |
9014 | ||
9015 | /* Translate one line of assembly. Pseudo ops and labels do not show | |
9016 | here. */ | |
9017 | void | |
9018 | md_assemble (str) | |
9019 | char *str; | |
9020 | { | |
9021 | char *saved_input_line_pointer, *mnemonic; | |
9022 | const struct pseudo_opcode *pdesc; | |
9023 | struct ia64_opcode *idesc; | |
9024 | unsigned char qp_regno; | |
9025 | unsigned int flags; | |
9026 | int ch; | |
9027 | ||
9028 | saved_input_line_pointer = input_line_pointer; | |
9029 | input_line_pointer = str; | |
9030 | ||
542d6675 | 9031 | /* extract the opcode (mnemonic): */ |
800eeca4 JW |
9032 | |
9033 | mnemonic = input_line_pointer; | |
9034 | ch = get_symbol_end (); | |
9035 | pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); | |
9036 | if (pdesc) | |
9037 | { | |
9038 | *input_line_pointer = ch; | |
9039 | (*pdesc->handler) (pdesc->arg); | |
9040 | goto done; | |
9041 | } | |
9042 | ||
542d6675 | 9043 | /* Find the instruction descriptor matching the arguments. */ |
800eeca4 JW |
9044 | |
9045 | idesc = ia64_find_opcode (mnemonic); | |
9046 | *input_line_pointer = ch; | |
9047 | if (!idesc) | |
9048 | { | |
9049 | as_bad ("Unknown opcode `%s'", mnemonic); | |
9050 | goto done; | |
9051 | } | |
9052 | ||
9053 | idesc = parse_operands (idesc); | |
9054 | if (!idesc) | |
9055 | goto done; | |
9056 | ||
542d6675 | 9057 | /* Handle the dynamic ops we can handle now: */ |
800eeca4 JW |
9058 | if (idesc->type == IA64_TYPE_DYN) |
9059 | { | |
9060 | if (strcmp (idesc->name, "add") == 0) | |
9061 | { | |
9062 | if (CURR_SLOT.opnd[2].X_op == O_register | |
9063 | && CURR_SLOT.opnd[2].X_add_number < 4) | |
9064 | mnemonic = "addl"; | |
9065 | else | |
9066 | mnemonic = "adds"; | |
3d56ab85 | 9067 | ia64_free_opcode (idesc); |
800eeca4 JW |
9068 | idesc = ia64_find_opcode (mnemonic); |
9069 | #if 0 | |
9070 | know (!idesc->next); | |
9071 | #endif | |
9072 | } | |
9073 | else if (strcmp (idesc->name, "mov") == 0) | |
9074 | { | |
9075 | enum ia64_opnd opnd1, opnd2; | |
9076 | int rop; | |
9077 | ||
9078 | opnd1 = idesc->operands[0]; | |
9079 | opnd2 = idesc->operands[1]; | |
9080 | if (opnd1 == IA64_OPND_AR3) | |
9081 | rop = 0; | |
9082 | else if (opnd2 == IA64_OPND_AR3) | |
9083 | rop = 1; | |
9084 | else | |
9085 | abort (); | |
9086 | if (CURR_SLOT.opnd[rop].X_op == O_register | |
9087 | && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) | |
9088 | mnemonic = "mov.i"; | |
9089 | else | |
9090 | mnemonic = "mov.m"; | |
3d56ab85 | 9091 | ia64_free_opcode (idesc); |
800eeca4 JW |
9092 | idesc = ia64_find_opcode (mnemonic); |
9093 | while (idesc != NULL | |
9094 | && (idesc->operands[0] != opnd1 | |
9095 | || idesc->operands[1] != opnd2)) | |
9096 | idesc = get_next_opcode (idesc); | |
9097 | } | |
9098 | } | |
9099 | ||
9100 | qp_regno = 0; | |
9101 | if (md.qp.X_op == O_register) | |
f1bcba5b JW |
9102 | { |
9103 | qp_regno = md.qp.X_add_number - REG_P; | |
9104 | md.qp.X_op = O_absent; | |
9105 | } | |
800eeca4 JW |
9106 | |
9107 | flags = idesc->flags; | |
9108 | ||
9109 | if ((flags & IA64_OPCODE_FIRST) != 0) | |
9110 | insn_group_break (1, 0, 0); | |
9111 | ||
9112 | if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) | |
9113 | { | |
9114 | as_bad ("`%s' cannot be predicated", idesc->name); | |
9115 | goto done; | |
9116 | } | |
9117 | ||
542d6675 | 9118 | /* Build the instruction. */ |
800eeca4 JW |
9119 | CURR_SLOT.qp_regno = qp_regno; |
9120 | CURR_SLOT.idesc = idesc; | |
9121 | as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); | |
4dc7ead9 | 9122 | dwarf2_where (&CURR_SLOT.debug_line); |
800eeca4 JW |
9123 | |
9124 | /* Add unwind entry, if there is one. */ | |
e0c9811a | 9125 | if (unwind.current_entry) |
800eeca4 | 9126 | { |
e0c9811a JW |
9127 | CURR_SLOT.unwind_record = unwind.current_entry; |
9128 | unwind.current_entry = NULL; | |
800eeca4 JW |
9129 | } |
9130 | ||
542d6675 | 9131 | /* Check for dependency violations. */ |
800eeca4 | 9132 | if (md.detect_dv) |
542d6675 | 9133 | check_dv (idesc); |
800eeca4 JW |
9134 | |
9135 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
9136 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
9137 | emit_one_bundle (); | |
9138 | ||
9139 | if ((flags & IA64_OPCODE_LAST) != 0) | |
9140 | insn_group_break (1, 0, 0); | |
9141 | ||
9142 | md.last_text_seg = now_seg; | |
9143 | ||
9144 | done: | |
9145 | input_line_pointer = saved_input_line_pointer; | |
9146 | } | |
9147 | ||
9148 | /* Called when symbol NAME cannot be found in the symbol table. | |
9149 | Should be used for dynamic valued symbols only. */ | |
542d6675 KH |
9150 | |
9151 | symbolS * | |
800eeca4 | 9152 | md_undefined_symbol (name) |
2434f565 | 9153 | char *name ATTRIBUTE_UNUSED; |
800eeca4 JW |
9154 | { |
9155 | return 0; | |
9156 | } | |
9157 | ||
9158 | /* Called for any expression that can not be recognized. When the | |
9159 | function is called, `input_line_pointer' will point to the start of | |
9160 | the expression. */ | |
542d6675 | 9161 | |
800eeca4 JW |
9162 | void |
9163 | md_operand (e) | |
9164 | expressionS *e; | |
9165 | { | |
9166 | enum pseudo_type pseudo_type; | |
e0c9811a | 9167 | const char *name; |
800eeca4 JW |
9168 | size_t len; |
9169 | int ch, i; | |
9170 | ||
9171 | switch (*input_line_pointer) | |
9172 | { | |
9173 | case '@': | |
542d6675 | 9174 | /* Find what relocation pseudo-function we're dealing with. */ |
800eeca4 JW |
9175 | pseudo_type = 0; |
9176 | ch = *++input_line_pointer; | |
9177 | for (i = 0; i < NELEMS (pseudo_func); ++i) | |
9178 | if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) | |
9179 | { | |
9180 | len = strlen (pseudo_func[i].name); | |
9181 | if (strncmp (pseudo_func[i].name + 1, | |
9182 | input_line_pointer + 1, len - 1) == 0 | |
9183 | && !is_part_of_name (input_line_pointer[len])) | |
9184 | { | |
9185 | input_line_pointer += len; | |
9186 | pseudo_type = pseudo_func[i].type; | |
9187 | break; | |
9188 | } | |
9189 | } | |
9190 | switch (pseudo_type) | |
9191 | { | |
9192 | case PSEUDO_FUNC_RELOC: | |
9193 | SKIP_WHITESPACE (); | |
9194 | if (*input_line_pointer != '(') | |
9195 | { | |
9196 | as_bad ("Expected '('"); | |
9197 | goto err; | |
9198 | } | |
542d6675 KH |
9199 | /* Skip '('. */ |
9200 | ++input_line_pointer; | |
800eeca4 JW |
9201 | expression (e); |
9202 | if (*input_line_pointer++ != ')') | |
9203 | { | |
9204 | as_bad ("Missing ')'"); | |
9205 | goto err; | |
9206 | } | |
9207 | if (e->X_op != O_symbol) | |
9208 | { | |
9209 | if (e->X_op != O_pseudo_fixup) | |
9210 | { | |
9211 | as_bad ("Not a symbolic expression"); | |
9212 | goto err; | |
9213 | } | |
9214 | if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE | |
9215 | && i == FUNC_LT_RELATIVE) | |
9216 | i = FUNC_LT_FPTR_RELATIVE; | |
9217 | else | |
9218 | { | |
9219 | as_bad ("Illegal combination of relocation functions"); | |
9220 | goto err; | |
9221 | } | |
9222 | } | |
542d6675 KH |
9223 | /* Make sure gas doesn't get rid of local symbols that are used |
9224 | in relocs. */ | |
800eeca4 JW |
9225 | e->X_op = O_pseudo_fixup; |
9226 | e->X_op_symbol = pseudo_func[i].u.sym; | |
9227 | break; | |
9228 | ||
9229 | case PSEUDO_FUNC_CONST: | |
9230 | e->X_op = O_constant; | |
9231 | e->X_add_number = pseudo_func[i].u.ival; | |
9232 | break; | |
9233 | ||
e0c9811a JW |
9234 | case PSEUDO_FUNC_REG: |
9235 | e->X_op = O_register; | |
9236 | e->X_add_number = pseudo_func[i].u.ival; | |
9237 | break; | |
9238 | ||
800eeca4 | 9239 | default: |
e0c9811a JW |
9240 | name = input_line_pointer - 1; |
9241 | get_symbol_end (); | |
9242 | as_bad ("Unknown pseudo function `%s'", name); | |
800eeca4 JW |
9243 | goto err; |
9244 | } | |
9245 | break; | |
9246 | ||
9247 | case '[': | |
9248 | ++input_line_pointer; | |
9249 | expression (e); | |
9250 | if (*input_line_pointer != ']') | |
9251 | { | |
9252 | as_bad ("Closing bracket misssing"); | |
9253 | goto err; | |
9254 | } | |
9255 | else | |
9256 | { | |
9257 | if (e->X_op != O_register) | |
9258 | as_bad ("Register expected as index"); | |
9259 | ||
9260 | ++input_line_pointer; | |
9261 | e->X_op = O_index; | |
9262 | } | |
9263 | break; | |
9264 | ||
9265 | default: | |
9266 | break; | |
9267 | } | |
9268 | return; | |
9269 | ||
9270 | err: | |
9271 | ignore_rest_of_line (); | |
9272 | } | |
9273 | ||
9274 | /* Return 1 if it's OK to adjust a reloc by replacing the symbol with | |
9275 | a section symbol plus some offset. For relocs involving @fptr(), | |
9276 | directives we don't want such adjustments since we need to have the | |
9277 | original symbol's name in the reloc. */ | |
9278 | int | |
9279 | ia64_fix_adjustable (fix) | |
9280 | fixS *fix; | |
9281 | { | |
9282 | /* Prevent all adjustments to global symbols */ | |
9283 | if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) | |
9284 | return 0; | |
9285 | ||
9286 | switch (fix->fx_r_type) | |
9287 | { | |
9288 | case BFD_RELOC_IA64_FPTR64I: | |
9289 | case BFD_RELOC_IA64_FPTR32MSB: | |
9290 | case BFD_RELOC_IA64_FPTR32LSB: | |
9291 | case BFD_RELOC_IA64_FPTR64MSB: | |
9292 | case BFD_RELOC_IA64_FPTR64LSB: | |
9293 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9294 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9295 | return 0; | |
9296 | default: | |
9297 | break; | |
9298 | } | |
9299 | ||
9300 | return 1; | |
9301 | } | |
9302 | ||
9303 | int | |
9304 | ia64_force_relocation (fix) | |
9305 | fixS *fix; | |
9306 | { | |
9307 | switch (fix->fx_r_type) | |
9308 | { | |
9309 | case BFD_RELOC_IA64_FPTR64I: | |
9310 | case BFD_RELOC_IA64_FPTR32MSB: | |
9311 | case BFD_RELOC_IA64_FPTR32LSB: | |
9312 | case BFD_RELOC_IA64_FPTR64MSB: | |
9313 | case BFD_RELOC_IA64_FPTR64LSB: | |
9314 | ||
9315 | case BFD_RELOC_IA64_LTOFF22: | |
9316 | case BFD_RELOC_IA64_LTOFF64I: | |
9317 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9318 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9319 | case BFD_RELOC_IA64_PLTOFF22: | |
9320 | case BFD_RELOC_IA64_PLTOFF64I: | |
9321 | case BFD_RELOC_IA64_PLTOFF64MSB: | |
9322 | case BFD_RELOC_IA64_PLTOFF64LSB: | |
9323 | return 1; | |
9324 | ||
9325 | default: | |
9326 | return 0; | |
9327 | } | |
9328 | return 0; | |
9329 | } | |
9330 | ||
9331 | /* Decide from what point a pc-relative relocation is relative to, | |
9332 | relative to the pc-relative fixup. Er, relatively speaking. */ | |
9333 | long | |
9334 | ia64_pcrel_from_section (fix, sec) | |
9335 | fixS *fix; | |
9336 | segT sec; | |
9337 | { | |
9338 | unsigned long off = fix->fx_frag->fr_address + fix->fx_where; | |
197865e8 | 9339 | |
800eeca4 JW |
9340 | if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) |
9341 | off &= ~0xfUL; | |
9342 | ||
9343 | return off; | |
9344 | } | |
9345 | ||
9346 | /* This is called whenever some data item (not an instruction) needs a | |
9347 | fixup. We pick the right reloc code depending on the byteorder | |
9348 | currently in effect. */ | |
9349 | void | |
9350 | ia64_cons_fix_new (f, where, nbytes, exp) | |
9351 | fragS *f; | |
9352 | int where; | |
9353 | int nbytes; | |
9354 | expressionS *exp; | |
9355 | { | |
9356 | bfd_reloc_code_real_type code; | |
9357 | fixS *fix; | |
9358 | ||
9359 | switch (nbytes) | |
9360 | { | |
9361 | /* There are no reloc for 8 and 16 bit quantities, but we allow | |
9362 | them here since they will work fine as long as the expression | |
9363 | is fully defined at the end of the pass over the source file. */ | |
9364 | case 1: code = BFD_RELOC_8; break; | |
9365 | case 2: code = BFD_RELOC_16; break; | |
9366 | case 4: | |
9367 | if (target_big_endian) | |
9368 | code = BFD_RELOC_IA64_DIR32MSB; | |
9369 | else | |
9370 | code = BFD_RELOC_IA64_DIR32LSB; | |
9371 | break; | |
9372 | ||
9373 | case 8: | |
9374 | if (target_big_endian) | |
9375 | code = BFD_RELOC_IA64_DIR64MSB; | |
9376 | else | |
9377 | code = BFD_RELOC_IA64_DIR64LSB; | |
9378 | break; | |
9379 | ||
9380 | default: | |
9381 | as_bad ("Unsupported fixup size %d", nbytes); | |
9382 | ignore_rest_of_line (); | |
9383 | return; | |
9384 | } | |
9385 | if (exp->X_op == O_pseudo_fixup) | |
9386 | { | |
9387 | /* ??? */ | |
9388 | exp->X_op = O_symbol; | |
9389 | code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); | |
9390 | } | |
9391 | fix = fix_new_exp (f, where, nbytes, exp, 0, code); | |
9392 | /* We need to store the byte order in effect in case we're going | |
9393 | to fix an 8 or 16 bit relocation (for which there no real | |
9394 | relocs available). See md_apply_fix(). */ | |
9395 | fix->tc_fix_data.bigendian = target_big_endian; | |
9396 | } | |
9397 | ||
9398 | /* Return the actual relocation we wish to associate with the pseudo | |
9399 | reloc described by SYM and R_TYPE. SYM should be one of the | |
197865e8 | 9400 | symbols in the pseudo_func array, or NULL. */ |
800eeca4 JW |
9401 | |
9402 | static bfd_reloc_code_real_type | |
9403 | ia64_gen_real_reloc_type (sym, r_type) | |
9404 | struct symbol *sym; | |
9405 | bfd_reloc_code_real_type r_type; | |
9406 | { | |
9407 | bfd_reloc_code_real_type new = 0; | |
9408 | ||
9409 | if (sym == NULL) | |
9410 | { | |
9411 | return r_type; | |
9412 | } | |
9413 | ||
9414 | switch (S_GET_VALUE (sym)) | |
9415 | { | |
9416 | case FUNC_FPTR_RELATIVE: | |
9417 | switch (r_type) | |
9418 | { | |
9419 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; | |
9420 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; | |
9421 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; | |
9422 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; | |
9423 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; | |
9424 | default: break; | |
9425 | } | |
9426 | break; | |
9427 | ||
9428 | case FUNC_GP_RELATIVE: | |
9429 | switch (r_type) | |
9430 | { | |
9431 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; | |
9432 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; | |
9433 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; | |
9434 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; | |
9435 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; | |
9436 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; | |
9437 | default: break; | |
9438 | } | |
9439 | break; | |
9440 | ||
9441 | case FUNC_LT_RELATIVE: | |
9442 | switch (r_type) | |
9443 | { | |
9444 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; | |
9445 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; | |
9446 | default: break; | |
9447 | } | |
9448 | break; | |
9449 | ||
c67e42c9 RH |
9450 | case FUNC_PC_RELATIVE: |
9451 | switch (r_type) | |
9452 | { | |
9453 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; | |
9454 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; | |
9455 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; | |
9456 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; | |
9457 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; | |
9458 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; | |
9459 | default: break; | |
9460 | } | |
9461 | break; | |
9462 | ||
800eeca4 JW |
9463 | case FUNC_PLT_RELATIVE: |
9464 | switch (r_type) | |
9465 | { | |
9466 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; | |
9467 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; | |
9468 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; | |
9469 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; | |
9470 | default: break; | |
9471 | } | |
9472 | break; | |
9473 | ||
9474 | case FUNC_SEC_RELATIVE: | |
9475 | switch (r_type) | |
9476 | { | |
9477 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; | |
9478 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; | |
9479 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; | |
9480 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; | |
9481 | default: break; | |
9482 | } | |
9483 | break; | |
9484 | ||
9485 | case FUNC_SEG_RELATIVE: | |
9486 | switch (r_type) | |
9487 | { | |
9488 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; | |
9489 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; | |
9490 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; | |
9491 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; | |
9492 | default: break; | |
9493 | } | |
9494 | break; | |
9495 | ||
9496 | case FUNC_LTV_RELATIVE: | |
9497 | switch (r_type) | |
9498 | { | |
9499 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; | |
9500 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; | |
9501 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; | |
9502 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; | |
9503 | default: break; | |
9504 | } | |
9505 | break; | |
9506 | ||
9507 | case FUNC_LT_FPTR_RELATIVE: | |
9508 | switch (r_type) | |
9509 | { | |
9510 | case BFD_RELOC_IA64_IMM22: | |
9511 | new = BFD_RELOC_IA64_LTOFF_FPTR22; break; | |
9512 | case BFD_RELOC_IA64_IMM64: | |
9513 | new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; | |
9514 | default: | |
9515 | break; | |
9516 | } | |
9517 | break; | |
9518 | default: | |
9519 | abort (); | |
9520 | } | |
9521 | /* Hmmmm. Should this ever occur? */ | |
9522 | if (new) | |
9523 | return new; | |
9524 | else | |
9525 | return r_type; | |
9526 | } | |
9527 | ||
9528 | /* Here is where generate the appropriate reloc for pseudo relocation | |
9529 | functions. */ | |
9530 | void | |
9531 | ia64_validate_fix (fix) | |
9532 | fixS *fix; | |
9533 | { | |
9534 | switch (fix->fx_r_type) | |
9535 | { | |
9536 | case BFD_RELOC_IA64_FPTR64I: | |
9537 | case BFD_RELOC_IA64_FPTR32MSB: | |
9538 | case BFD_RELOC_IA64_FPTR64LSB: | |
9539 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9540 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9541 | if (fix->fx_offset != 0) | |
9542 | as_bad_where (fix->fx_file, fix->fx_line, | |
9543 | "No addend allowed in @fptr() relocation"); | |
9544 | break; | |
9545 | default: | |
9546 | break; | |
9547 | } | |
9548 | ||
9549 | return; | |
9550 | } | |
9551 | ||
9552 | static void | |
9553 | fix_insn (fix, odesc, value) | |
9554 | fixS *fix; | |
9555 | const struct ia64_operand *odesc; | |
9556 | valueT value; | |
9557 | { | |
9558 | bfd_vma insn[3], t0, t1, control_bits; | |
9559 | const char *err; | |
9560 | char *fixpos; | |
9561 | long slot; | |
9562 | ||
9563 | slot = fix->fx_where & 0x3; | |
9564 | fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); | |
9565 | ||
c67e42c9 | 9566 | /* Bundles are always in little-endian byte order */ |
800eeca4 JW |
9567 | t0 = bfd_getl64 (fixpos); |
9568 | t1 = bfd_getl64 (fixpos + 8); | |
9569 | control_bits = t0 & 0x1f; | |
9570 | insn[0] = (t0 >> 5) & 0x1ffffffffffLL; | |
9571 | insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); | |
9572 | insn[2] = (t1 >> 23) & 0x1ffffffffffLL; | |
9573 | ||
c67e42c9 RH |
9574 | err = NULL; |
9575 | if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) | |
800eeca4 | 9576 | { |
c67e42c9 RH |
9577 | insn[1] = (value >> 22) & 0x1ffffffffffLL; |
9578 | insn[2] |= (((value & 0x7f) << 13) | |
9579 | | (((value >> 7) & 0x1ff) << 27) | |
9580 | | (((value >> 16) & 0x1f) << 22) | |
9581 | | (((value >> 21) & 0x1) << 21) | |
9582 | | (((value >> 63) & 0x1) << 36)); | |
800eeca4 | 9583 | } |
c67e42c9 RH |
9584 | else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) |
9585 | { | |
9586 | if (value & ~0x3fffffffffffffffULL) | |
9587 | err = "integer operand out of range"; | |
9588 | insn[1] = (value >> 21) & 0x1ffffffffffLL; | |
9589 | insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); | |
9590 | } | |
9591 | else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) | |
9592 | { | |
9593 | value >>= 4; | |
9594 | insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; | |
9595 | insn[2] |= ((((value >> 59) & 0x1) << 36) | |
9596 | | (((value >> 0) & 0xfffff) << 13)); | |
9597 | } | |
9598 | else | |
9599 | err = (*odesc->insert) (odesc, value, insn + slot); | |
9600 | ||
9601 | if (err) | |
9602 | as_bad_where (fix->fx_file, fix->fx_line, err); | |
800eeca4 JW |
9603 | |
9604 | t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); | |
9605 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
44f5c83a JW |
9606 | number_to_chars_littleendian (fixpos + 0, t0, 8); |
9607 | number_to_chars_littleendian (fixpos + 8, t1, 8); | |
800eeca4 JW |
9608 | } |
9609 | ||
9610 | /* Attempt to simplify or even eliminate a fixup. The return value is | |
9611 | ignored; perhaps it was once meaningful, but now it is historical. | |
9612 | To indicate that a fixup has been eliminated, set FIXP->FX_DONE. | |
9613 | ||
9614 | If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry | |
197865e8 | 9615 | (if possible). */ |
800eeca4 JW |
9616 | int |
9617 | md_apply_fix3 (fix, valuep, seg) | |
9618 | fixS *fix; | |
9619 | valueT *valuep; | |
2434f565 | 9620 | segT seg ATTRIBUTE_UNUSED; |
800eeca4 JW |
9621 | { |
9622 | char *fixpos; | |
9623 | valueT value = *valuep; | |
9624 | int adjust = 0; | |
9625 | ||
9626 | fixpos = fix->fx_frag->fr_literal + fix->fx_where; | |
9627 | ||
9628 | if (fix->fx_pcrel) | |
9629 | { | |
9630 | switch (fix->fx_r_type) | |
9631 | { | |
9632 | case BFD_RELOC_IA64_DIR32MSB: | |
9633 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; | |
9634 | adjust = 1; | |
9635 | break; | |
9636 | ||
9637 | case BFD_RELOC_IA64_DIR32LSB: | |
9638 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; | |
9639 | adjust = 1; | |
9640 | break; | |
9641 | ||
9642 | case BFD_RELOC_IA64_DIR64MSB: | |
9643 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; | |
9644 | adjust = 1; | |
9645 | break; | |
9646 | ||
9647 | case BFD_RELOC_IA64_DIR64LSB: | |
9648 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; | |
9649 | adjust = 1; | |
9650 | break; | |
9651 | ||
9652 | default: | |
9653 | break; | |
9654 | } | |
9655 | } | |
9656 | if (fix->fx_addsy) | |
9657 | { | |
9658 | switch (fix->fx_r_type) | |
9659 | { | |
9660 | case 0: | |
9661 | as_bad_where (fix->fx_file, fix->fx_line, | |
9662 | "%s must have a constant value", | |
9663 | elf64_ia64_operands[fix->tc_fix_data.opnd].desc); | |
9664 | break; | |
9665 | ||
9666 | default: | |
9667 | break; | |
9668 | } | |
9669 | ||
9670 | /* ??? This is a hack copied from tc-i386.c to make PCREL relocs | |
542d6675 | 9671 | work. There should be a better way to handle this. */ |
800eeca4 JW |
9672 | if (adjust) |
9673 | fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; | |
9674 | } | |
9675 | else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) | |
9676 | { | |
9677 | if (fix->tc_fix_data.bigendian) | |
9678 | number_to_chars_bigendian (fixpos, value, fix->fx_size); | |
9679 | else | |
9680 | number_to_chars_littleendian (fixpos, value, fix->fx_size); | |
9681 | fix->fx_done = 1; | |
9682 | return 1; | |
9683 | } | |
9684 | else | |
9685 | { | |
9686 | fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); | |
9687 | fix->fx_done = 1; | |
9688 | return 1; | |
9689 | } | |
9690 | return 1; | |
9691 | } | |
9692 | ||
9693 | /* Generate the BFD reloc to be stuck in the object file from the | |
9694 | fixup used internally in the assembler. */ | |
542d6675 KH |
9695 | |
9696 | arelent * | |
800eeca4 | 9697 | tc_gen_reloc (sec, fixp) |
2434f565 | 9698 | asection *sec ATTRIBUTE_UNUSED; |
800eeca4 JW |
9699 | fixS *fixp; |
9700 | { | |
9701 | arelent *reloc; | |
9702 | ||
9703 | reloc = xmalloc (sizeof (*reloc)); | |
9704 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
9705 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
9706 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9707 | reloc->addend = fixp->fx_offset; | |
9708 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
9709 | ||
9710 | if (!reloc->howto) | |
9711 | { | |
9712 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9713 | "Cannot represent %s relocation in object file", | |
9714 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
9715 | } | |
9716 | return reloc; | |
9717 | } | |
9718 | ||
9719 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9720 | of type TYPE, and store the appropriate bytes in *LIT. The number |
9721 | of LITTLENUMS emitted is stored in *SIZE. An error message is | |
800eeca4 JW |
9722 | returned, or NULL on OK. */ |
9723 | ||
9724 | #define MAX_LITTLENUMS 5 | |
9725 | ||
542d6675 | 9726 | char * |
800eeca4 JW |
9727 | md_atof (type, lit, size) |
9728 | int type; | |
9729 | char *lit; | |
9730 | int *size; | |
9731 | { | |
9732 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
9733 | LITTLENUM_TYPE *word; | |
9734 | char *t; | |
9735 | int prec; | |
9736 | ||
9737 | switch (type) | |
9738 | { | |
9739 | /* IEEE floats */ | |
9740 | case 'f': | |
9741 | case 'F': | |
9742 | case 's': | |
9743 | case 'S': | |
9744 | prec = 2; | |
9745 | break; | |
9746 | ||
9747 | case 'd': | |
9748 | case 'D': | |
9749 | case 'r': | |
9750 | case 'R': | |
9751 | prec = 4; | |
9752 | break; | |
9753 | ||
9754 | case 'x': | |
9755 | case 'X': | |
9756 | case 'p': | |
9757 | case 'P': | |
9758 | prec = 5; | |
9759 | break; | |
9760 | ||
9761 | default: | |
9762 | *size = 0; | |
9763 | return "Bad call to MD_ATOF()"; | |
9764 | } | |
9765 | t = atof_ieee (input_line_pointer, type, words); | |
9766 | if (t) | |
9767 | input_line_pointer = t; | |
9768 | *size = prec * sizeof (LITTLENUM_TYPE); | |
9769 | ||
9770 | for (word = words + prec - 1; prec--;) | |
9771 | { | |
9772 | md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); | |
9773 | lit += sizeof (LITTLENUM_TYPE); | |
9774 | } | |
9775 | return 0; | |
9776 | } | |
9777 | ||
9778 | /* Round up a section's size to the appropriate boundary. */ | |
9779 | valueT | |
9780 | md_section_align (seg, size) | |
9781 | segT seg; | |
9782 | valueT size; | |
9783 | { | |
9784 | int align = bfd_get_section_alignment (stdoutput, seg); | |
197865e8 | 9785 | valueT mask = ((valueT) 1 << align) - 1; |
800eeca4 JW |
9786 | |
9787 | return (size + mask) & ~mask; | |
9788 | } | |
9789 | ||
9790 | /* Handle ia64 specific semantics of the align directive. */ | |
9791 | ||
0a9ef439 | 9792 | void |
800eeca4 JW |
9793 | ia64_md_do_align (n, fill, len, max) |
9794 | int n; | |
9795 | const char *fill; | |
2434f565 | 9796 | int len ATTRIBUTE_UNUSED; |
800eeca4 JW |
9797 | int max; |
9798 | { | |
0a9ef439 | 9799 | if (subseg_text_p (now_seg)) |
800eeca4 | 9800 | ia64_flush_insns (); |
0a9ef439 | 9801 | } |
800eeca4 | 9802 | |
0a9ef439 RH |
9803 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
9804 | of an rs_align_code fragment. */ | |
800eeca4 | 9805 | |
0a9ef439 RH |
9806 | void |
9807 | ia64_handle_align (fragp) | |
9808 | fragS *fragp; | |
9809 | { | |
9810 | /* Use mfi bundle of nops with no stop bits. */ | |
9811 | static const unsigned char be_nop[] | |
9812 | = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, | |
9813 | 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; | |
9814 | static const unsigned char le_nop[] | |
9815 | = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, | |
9816 | 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; | |
9817 | ||
9818 | int bytes; | |
9819 | char *p; | |
9820 | ||
9821 | if (fragp->fr_type != rs_align_code) | |
9822 | return; | |
9823 | ||
9824 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
9825 | p = fragp->fr_literal + fragp->fr_fix; | |
9826 | ||
9827 | /* Make sure we are on a 16-byte boundary, in case someone has been | |
9828 | putting data into a text section. */ | |
9829 | if (bytes & 15) | |
9830 | { | |
9831 | int fix = bytes & 15; | |
9832 | memset (p, 0, fix); | |
9833 | p += fix; | |
9834 | bytes -= fix; | |
9835 | fragp->fr_fix += fix; | |
800eeca4 JW |
9836 | } |
9837 | ||
0a9ef439 RH |
9838 | memcpy (p, (target_big_endian ? be_nop : le_nop), 16); |
9839 | fragp->fr_var = 16; | |
800eeca4 | 9840 | } |