Commit | Line | Data |
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4bf4a882 | 1 | /* tc-m32r.c -- Assembler for the Renesas M32R. |
bd337dde | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 |
ab3e48dc | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
ab3e48dc | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "symcat.h" |
27 | #include "opcodes/m32r-desc.h" | |
28 | #include "opcodes/m32r-opc.h" | |
29 | #include "cgen.h" | |
88845958 | 30 | #include "elf/m32r.h" |
252b5132 RH |
31 | |
32 | /* Linked list of symbols that are debugging symbols to be defined as the | |
33 | beginning of the current instruction. */ | |
34 | typedef struct sym_link | |
35 | { | |
36 | struct sym_link *next; | |
ab3e48dc | 37 | symbolS *symbol; |
252b5132 RH |
38 | } sym_linkS; |
39 | ||
ab3e48dc KH |
40 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
41 | ||
252b5132 RH |
42 | /* Structure to hold all of the different components describing |
43 | an individual instruction. */ | |
44 | typedef struct | |
45 | { | |
ab3e48dc KH |
46 | const CGEN_INSN *insn; |
47 | const CGEN_INSN *orig_insn; | |
48 | CGEN_FIELDS fields; | |
252b5132 | 49 | #if CGEN_INT_INSN_P |
ab3e48dc | 50 | CGEN_INSN_INT buffer[1]; |
252b5132 RH |
51 | #define INSN_VALUE(buf) (*(buf)) |
52 | #else | |
ab3e48dc | 53 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
252b5132 RH |
54 | #define INSN_VALUE(buf) (buf) |
55 | #endif | |
ab3e48dc KH |
56 | char *addr; |
57 | fragS *frag; | |
58 | int num_fixups; | |
59 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; | |
60 | int indices[MAX_OPERAND_INSTANCES]; | |
61 | sym_linkS *debug_sym_link; | |
252b5132 RH |
62 | } |
63 | m32r_insn; | |
64 | ||
65 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
66 | boundary (i.e. was the first of two 16 bit insns). */ | |
ab3e48dc | 67 | static m32r_insn prev_insn; |
252b5132 RH |
68 | |
69 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
70 | alignment request. */ | |
71 | static int seen_relaxable_p = 0; | |
72 | ||
6edf0760 NC |
73 | /* Non-zero if we are generating PIC code. */ |
74 | int pic_code; | |
75 | ||
252b5132 RH |
76 | /* Non-zero if -relax specified, in which case sufficient relocs are output |
77 | for the linker to do relaxing. | |
78 | We do simple forms of relaxing internally, but they are always done. | |
79 | This flag does not apply to them. */ | |
80 | static int m32r_relax; | |
81 | ||
ab3e48dc KH |
82 | #if 0 |
83 | /* Not supported yet. */ | |
252b5132 RH |
84 | /* If non-NULL, pointer to cpu description file to read. |
85 | This allows runtime additions to the assembler. */ | |
ab3e48dc | 86 | static const char *m32r_cpu_desc; |
252b5132 RH |
87 | #endif |
88 | ||
89 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. | |
90 | Each high/shigh reloc must be paired with it's low cousin in order to | |
91 | properly calculate the addend in a relocatable link (since there is a | |
92 | potential carry from the low to the high/shigh). | |
93 | This option is off by default though for user-written assembler code it | |
94 | might make sense to make the default be on (i.e. have gcc pass a flag | |
95 | to turn it off). This warning must not be on for GCC created code as | |
96 | optimization may delete the low but not the high/shigh (at least we | |
97 | shouldn't assume or require it to). */ | |
98 | static int warn_unmatched_high = 0; | |
99 | ||
88845958 NC |
100 | /* 1 if -m32rx has been specified, in which case support for |
101 | the extended M32RX instruction set should be enabled. | |
102 | 2 if -m32r2 has been specified, in which case support for | |
103 | the extended M32R2 instruction set should be enabled. */ | |
104 | static int enable_m32rx = 0; /* Default to M32R. */ | |
925c058e DE |
105 | |
106 | /* Non-zero if -m32rx -hidden has been specified, in which case support for | |
107 | the special M32RX instruction set should be enabled. */ | |
108 | static int enable_special = 0; | |
109 | ||
88845958 NC |
110 | /* Non-zero if -bitinst has been specified, in which case support |
111 | for extended M32R bit-field instruction set should be enabled. */ | |
bd337dde | 112 | static int enable_special_m32r = 1; |
88845958 NC |
113 | |
114 | /* Non-zero if -float has been specified, in which case support for | |
115 | extended M32R floating point instruction set should be enabled. */ | |
116 | static int enable_special_float = 0; | |
117 | ||
925c058e DE |
118 | /* Non-zero if the programmer should be warned when an explicit parallel |
119 | instruction might have constraint violations. */ | |
120 | static int warn_explicit_parallel_conflicts = 1; | |
121 | ||
b145f546 NC |
122 | /* Non-zero if the programmer should not receive any messages about |
123 | parallel instruction with potential or real constraint violations. | |
124 | The ability to suppress these messages is intended only for hardware | |
125 | vendors testing the chip. It superceedes | |
126 | warn_explicit_parallel_conflicts. */ | |
127 | static int ignore_parallel_conflicts = 0; | |
88845958 | 128 | |
925c058e | 129 | /* Non-zero if insns can be made parallel. */ |
88845958 NC |
130 | static int use_parallel = 1; |
131 | ||
132 | /* Non-zero if optimizations should be performed. */ | |
925c058e | 133 | static int optimize; |
252b5132 | 134 | |
88845958 NC |
135 | /* m32r er_flags. */ |
136 | static int m32r_flags = 0; | |
137 | ||
ab3e48dc | 138 | /* Stuff for .scomm symbols. */ |
252b5132 RH |
139 | static segT sbss_section; |
140 | static asection scom_section; | |
141 | static asymbol scom_symbol; | |
142 | ||
143 | const char comment_chars[] = ";"; | |
144 | const char line_comment_chars[] = "#"; | |
88845958 | 145 | const char line_separator_chars[] = "!"; |
252b5132 RH |
146 | const char EXP_CHARS[] = "eE"; |
147 | const char FLT_CHARS[] = "dD"; | |
148 | ||
149 | /* Relocations against symbols are done in two | |
150 | parts, with a HI relocation and a LO relocation. Each relocation | |
151 | has only 16 bits of space to store an addend. This means that in | |
152 | order for the linker to handle carries correctly, it must be able | |
153 | to locate both the HI and the LO relocation. This means that the | |
154 | relocations must appear in order in the relocation table. | |
155 | ||
156 | In order to implement this, we keep track of each unmatched HI | |
157 | relocation. We then sort them so that they immediately precede the | |
82efde3a | 158 | corresponding LO relocation. */ |
252b5132 RH |
159 | |
160 | struct m32r_hi_fixup | |
161 | { | |
ab3e48dc KH |
162 | /* Next HI fixup. */ |
163 | struct m32r_hi_fixup *next; | |
164 | ||
165 | /* This fixup. */ | |
166 | fixS *fixp; | |
252b5132 | 167 | |
ab3e48dc KH |
168 | /* The section this fixup is in. */ |
169 | segT seg; | |
252b5132 RH |
170 | }; |
171 | ||
172 | /* The list of unmatched HI relocs. */ | |
173 | ||
ab3e48dc | 174 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
252b5132 | 175 | \f |
88845958 NC |
176 | struct { |
177 | enum bfd_architecture bfd_mach; | |
178 | int mach_flags; | |
179 | } mach_table[] = | |
180 | { | |
181 | { bfd_mach_m32r, (1<<MACH_M32R) }, | |
182 | { bfd_mach_m32rx, (1<<MACH_M32RX) }, | |
183 | { bfd_mach_m32r2, (1<<MACH_M32R2) } | |
184 | }; | |
185 | ||
186 | static void allow_m32rx (int); | |
78a0c6fb | 187 | |
925c058e | 188 | static void |
88845958 | 189 | allow_m32rx (int on) |
925c058e DE |
190 | { |
191 | enable_m32rx = on; | |
192 | ||
193 | if (stdoutput != NULL) | |
88845958 NC |
194 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach); |
195 | ||
196 | if (gas_cgen_cpu_desc != NULL) | |
197 | gas_cgen_cpu_desc->machs = mach_table[on].mach_flags; | |
925c058e | 198 | } |
252b5132 | 199 | \f |
6edf0760 | 200 | #define M32R_SHORTOPTS "O::K:" |
ab3e48dc KH |
201 | |
202 | const char *md_shortopts = M32R_SHORTOPTS; | |
252b5132 RH |
203 | |
204 | struct option md_longopts[] = | |
205 | { | |
b145f546 NC |
206 | #define OPTION_M32R (OPTION_MD_BASE) |
207 | #define OPTION_M32RX (OPTION_M32R + 1) | |
208 | #define OPTION_M32R2 (OPTION_M32RX + 1) | |
209 | #define OPTION_BIG (OPTION_M32R2 + 1) | |
210 | #define OPTION_LITTLE (OPTION_BIG + 1) | |
211 | #define OPTION_PARALLEL (OPTION_LITTLE + 1) | |
212 | #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1) | |
213 | #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1) | |
214 | #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) | |
215 | #define OPTION_IGNORE_PARALLEL (OPTION_NO_WARN_PARALLEL + 1) | |
216 | #define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1) | |
217 | #define OPTION_SPECIAL (OPTION_NO_IGNORE_PARALLEL + 1) | |
218 | #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1) | |
bd337dde NC |
219 | #define OPTION_NO_SPECIAL_M32R (OPTION_SPECIAL_M32R + 1) |
220 | #define OPTION_SPECIAL_FLOAT (OPTION_NO_SPECIAL_M32R + 1) | |
b145f546 NC |
221 | #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1) |
222 | #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) | |
8ad9e709 | 223 | {"m32r", no_argument, NULL, OPTION_M32R}, |
925c058e | 224 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
88845958 NC |
225 | {"m32r2", no_argument, NULL, OPTION_M32R2}, |
226 | {"big", no_argument, NULL, OPTION_BIG}, | |
227 | {"little", no_argument, NULL, OPTION_LITTLE}, | |
228 | {"EB", no_argument, NULL, OPTION_BIG}, | |
229 | {"EL", no_argument, NULL, OPTION_LITTLE}, | |
230 | {"parallel", no_argument, NULL, OPTION_PARALLEL}, | |
231 | {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL}, | |
925c058e DE |
232 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
233 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, | |
925c058e DE |
234 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
235 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, | |
b145f546 NC |
236 | {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL}, |
237 | {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL}, | |
238 | {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, | |
239 | {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, | |
925c058e | 240 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
88845958 | 241 | {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R}, |
bd337dde | 242 | {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R}, |
88845958 | 243 | {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT}, |
252b5132 | 244 | /* Sigh. I guess all warnings must now have both variants. */ |
2f3519a2 NC |
245 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
246 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, | |
d3388653 NC |
247 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
248 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, | |
252b5132 | 249 | |
ab3e48dc KH |
250 | #if 0 |
251 | /* Not supported yet. */ | |
8ad9e709 NC |
252 | #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1) |
253 | #define OPTION_CPU_DESC (OPTION_RELAX + 1) | |
252b5132 | 254 | {"relax", no_argument, NULL, OPTION_RELAX}, |
252b5132 RH |
255 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
256 | #endif | |
252b5132 RH |
257 | {NULL, no_argument, NULL, 0} |
258 | }; | |
ab3e48dc | 259 | |
252b5132 RH |
260 | size_t md_longopts_size = sizeof (md_longopts); |
261 | ||
88845958 NC |
262 | static void little (int); |
263 | static int parallel (void); | |
264 | ||
265 | static void | |
266 | little (int on) | |
267 | { | |
268 | target_big_endian = ! on; | |
269 | } | |
270 | ||
271 | /* Use parallel execution. */ | |
272 | ||
273 | static int | |
274 | parallel (void) | |
275 | { | |
276 | if (! enable_m32rx) | |
277 | return 0; | |
278 | ||
279 | if (use_parallel == 1) | |
280 | return 1; | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
252b5132 RH |
285 | int |
286 | md_parse_option (c, arg) | |
ab3e48dc | 287 | int c; |
78a0c6fb | 288 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
289 | { |
290 | switch (c) | |
291 | { | |
925c058e DE |
292 | case 'O': |
293 | optimize = 1; | |
88845958 | 294 | use_parallel = 1; |
925c058e DE |
295 | break; |
296 | ||
8ad9e709 NC |
297 | case OPTION_M32R: |
298 | allow_m32rx (0); | |
299 | break; | |
ab3e48dc | 300 | |
925c058e DE |
301 | case OPTION_M32RX: |
302 | allow_m32rx (1); | |
303 | break; | |
ab3e48dc | 304 | |
88845958 NC |
305 | case OPTION_M32R2: |
306 | allow_m32rx (2); | |
307 | enable_special = 1; | |
308 | enable_special_m32r = 1; | |
309 | break; | |
310 | ||
311 | case OPTION_BIG: | |
312 | target_big_endian = 1; | |
313 | break; | |
314 | ||
315 | case OPTION_LITTLE: | |
316 | target_big_endian = 0; | |
317 | break; | |
318 | ||
319 | case OPTION_PARALLEL: | |
320 | use_parallel = 1; | |
321 | break; | |
322 | ||
323 | case OPTION_NO_PARALLEL: | |
324 | use_parallel = 0; | |
325 | break; | |
326 | ||
925c058e DE |
327 | case OPTION_WARN_PARALLEL: |
328 | warn_explicit_parallel_conflicts = 1; | |
329 | break; | |
ab3e48dc | 330 | |
925c058e | 331 | case OPTION_NO_WARN_PARALLEL: |
88845958 | 332 | warn_explicit_parallel_conflicts = 0; |
88845958 NC |
333 | break; |
334 | ||
b145f546 NC |
335 | case OPTION_IGNORE_PARALLEL: |
336 | ignore_parallel_conflicts = 1; | |
88845958 NC |
337 | break; |
338 | ||
b145f546 NC |
339 | case OPTION_NO_IGNORE_PARALLEL: |
340 | ignore_parallel_conflicts = 0; | |
925c058e DE |
341 | break; |
342 | ||
343 | case OPTION_SPECIAL: | |
344 | if (enable_m32rx) | |
345 | enable_special = 1; | |
346 | else | |
347 | { | |
348 | /* Pretend that we do not recognise this option. */ | |
349 | as_bad (_("Unrecognised option: -hidden")); | |
350 | return 0; | |
351 | } | |
352 | break; | |
252b5132 | 353 | |
88845958 NC |
354 | case OPTION_SPECIAL_M32R: |
355 | enable_special_m32r = 1; | |
356 | break; | |
357 | ||
bd337dde NC |
358 | case OPTION_NO_SPECIAL_M32R: |
359 | enable_special_m32r = 0; | |
360 | break; | |
361 | ||
88845958 NC |
362 | case OPTION_SPECIAL_FLOAT: |
363 | enable_special_float = 1; | |
364 | break; | |
365 | ||
252b5132 RH |
366 | case OPTION_WARN_UNMATCHED: |
367 | warn_unmatched_high = 1; | |
368 | break; | |
369 | ||
370 | case OPTION_NO_WARN_UNMATCHED: | |
371 | warn_unmatched_high = 0; | |
372 | break; | |
ab3e48dc | 373 | |
6edf0760 NC |
374 | case 'K': |
375 | if (strcmp (arg, "PIC") != 0) | |
376 | as_warn (_("Unrecognized option following -K")); | |
377 | else | |
378 | pic_code = 1; | |
379 | break; | |
380 | ||
ab3e48dc KH |
381 | #if 0 |
382 | /* Not supported yet. */ | |
252b5132 RH |
383 | case OPTION_RELAX: |
384 | m32r_relax = 1; | |
385 | break; | |
386 | case OPTION_CPU_DESC: | |
387 | m32r_cpu_desc = arg; | |
388 | break; | |
389 | #endif | |
390 | ||
391 | default: | |
392 | return 0; | |
393 | } | |
ab3e48dc | 394 | |
252b5132 RH |
395 | return 1; |
396 | } | |
397 | ||
398 | void | |
399 | md_show_usage (stream) | |
ab3e48dc | 400 | FILE *stream; |
252b5132 RH |
401 | { |
402 | fprintf (stream, _(" M32R specific command line options:\n")); | |
403 | ||
ded0aeb7 NC |
404 | fprintf (stream, _("\ |
405 | -m32r disable support for the m32rx instruction set\n")); | |
925c058e DE |
406 | fprintf (stream, _("\ |
407 | -m32rx support the extended m32rx instruction set\n")); | |
408 | fprintf (stream, _("\ | |
88845958 NC |
409 | -m32r2 support the extended m32r2 instruction set\n")); |
410 | fprintf (stream, _("\ | |
411 | -EL,-little produce little endian code and data\n")); | |
412 | fprintf (stream, _("\ | |
413 | -EB,-big produce big endian code and data\n")); | |
414 | fprintf (stream, _("\ | |
415 | -parallel try to combine instructions in parallel\n")); | |
416 | fprintf (stream, _("\ | |
417 | -no-parallel disable -parallel\n")); | |
418 | fprintf (stream, _("\ | |
bd337dde NC |
419 | -no-bitinst disallow the M32R2's extended bit-field instructions\n")); |
420 | fprintf (stream, _("\ | |
88845958 | 421 | -O try to optimize code. Implies -parallel\n")); |
925c058e DE |
422 | |
423 | fprintf (stream, _("\ | |
424 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); | |
425 | fprintf (stream, _("\ | |
b145f546 | 426 | might violate contraints\n")); |
925c058e DE |
427 | fprintf (stream, _("\ |
428 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); | |
429 | fprintf (stream, _("\ | |
b145f546 | 430 | instructions might violate contraints\n")); |
925c058e DE |
431 | fprintf (stream, _("\ |
432 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); | |
433 | fprintf (stream, _("\ | |
434 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); | |
88845958 | 435 | fprintf (stream, _("\ |
b145f546 | 436 | -ignore-parallel-conflicts do not check parallel instructions\n")); |
88845958 | 437 | fprintf (stream, _("\ |
b145f546 | 438 | fo contraint violations\n")); |
88845958 | 439 | fprintf (stream, _("\ |
b145f546 | 440 | -no-ignore-parallel-conflicts check parallel instructions for\n")); |
88845958 | 441 | fprintf (stream, _("\ |
b145f546 | 442 | contraint violations\n")); |
88845958 | 443 | fprintf (stream, _("\ |
b145f546 | 444 | -Ip synonym for -ignore-parallel-conflicts\n")); |
88845958 | 445 | fprintf (stream, _("\ |
b145f546 | 446 | -nIp synonym for -no-ignore-parallel-conflicts\n")); |
252b5132 RH |
447 | |
448 | fprintf (stream, _("\ | |
449 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); | |
450 | fprintf (stream, _("\ | |
451 | -no-warn-unmatched-high do not warn about missing low relocs\n")); | |
452 | fprintf (stream, _("\ | |
453 | -Wuh synonym for -warn-unmatched-high\n")); | |
454 | fprintf (stream, _("\ | |
455 | -Wnuh synonym for -no-warn-unmatched-high\n")); | |
456 | ||
6edf0760 NC |
457 | fprintf (stream, _("\ |
458 | -KPIC generate PIC\n")); | |
459 | ||
252b5132 RH |
460 | #if 0 |
461 | fprintf (stream, _("\ | |
462 | -relax create linker relaxable code\n")); | |
463 | fprintf (stream, _("\ | |
464 | -cpu-desc provide runtime cpu description file\n")); | |
465 | #endif | |
ab3e48dc | 466 | } |
252b5132 RH |
467 | |
468 | static void fill_insn PARAMS ((int)); | |
469 | static void m32r_scomm PARAMS ((int)); | |
470 | static void debug_sym PARAMS ((int)); | |
471 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); | |
472 | ||
473 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
474 | static subsegT prev_subseg; | |
475 | static segT prev_seg; | |
476 | ||
477 | /* The target specific pseudo-ops which we support. */ | |
478 | const pseudo_typeS md_pseudo_table[] = | |
479 | { | |
480 | { "word", cons, 4 }, | |
481 | { "fillinsn", fill_insn, 0 }, | |
482 | { "scomm", m32r_scomm, 0 }, | |
483 | { "debugsym", debug_sym, 0 }, | |
925c058e DE |
484 | { "m32r", allow_m32rx, 0 }, |
485 | { "m32rx", allow_m32rx, 1 }, | |
88845958 NC |
486 | { "m32r2", allow_m32rx, 2 }, |
487 | { "little", little, 1 }, | |
488 | { "big", little, 0 }, | |
252b5132 RH |
489 | { NULL, NULL, 0 } |
490 | }; | |
491 | ||
097f809a NC |
492 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" |
493 | symbolS * GOT_symbol; | |
494 | ||
495 | static inline int | |
496 | m32r_PIC_related_p (symbolS *sym) | |
497 | { | |
498 | expressionS *exp; | |
499 | ||
500 | if (! sym) | |
501 | return 0; | |
502 | ||
503 | if (sym == GOT_symbol) | |
504 | return 1; | |
505 | ||
506 | exp = symbol_get_value_expression (sym); | |
507 | ||
508 | return (exp->X_op == O_PIC_reloc | |
509 | || exp->X_md == BFD_RELOC_M32R_26_PLTREL | |
510 | || m32r_PIC_related_p (exp->X_add_symbol) | |
511 | || m32r_PIC_related_p (exp->X_op_symbol)); | |
512 | } | |
513 | ||
514 | static inline int | |
515 | m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p) | |
516 | { | |
517 | expressionS *exp = main_exp; | |
518 | ||
519 | if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol)) | |
520 | return 1; | |
521 | ||
522 | if (exp->X_op == O_symbol && exp->X_add_symbol) | |
523 | { | |
524 | if (exp->X_add_symbol == GOT_symbol) | |
525 | { | |
526 | *r_type_p = BFD_RELOC_M32R_GOTPC24; | |
527 | return 0; | |
528 | } | |
529 | } | |
530 | else if (exp->X_op == O_add) | |
531 | { | |
532 | exp = symbol_get_value_expression (exp->X_add_symbol); | |
533 | if (! exp) | |
534 | return 0; | |
535 | } | |
536 | ||
537 | if (exp->X_op == O_PIC_reloc || exp->X_md != BFD_RELOC_UNUSED) | |
538 | { | |
539 | *r_type_p = exp->X_md; | |
540 | if (exp == main_exp) | |
541 | exp->X_op = O_symbol; | |
542 | else | |
543 | { | |
544 | main_exp->X_add_symbol = exp->X_add_symbol; | |
545 | main_exp->X_add_number += exp->X_add_number; | |
546 | } | |
547 | } | |
548 | else | |
549 | return (m32r_PIC_related_p (exp->X_add_symbol) | |
550 | || m32r_PIC_related_p (exp->X_op_symbol)); | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
252b5132 | 555 | /* FIXME: Should be machine generated. */ |
88845958 | 556 | #define NOP_INSN 0x7000 |
ab3e48dc | 557 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
252b5132 | 558 | |
0a9ef439 RH |
559 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
560 | of an rs_align_code fragment. */ | |
252b5132 | 561 | |
0a9ef439 RH |
562 | void |
563 | m32r_handle_align (fragp) | |
015c05c1 | 564 | fragS *fragp; |
252b5132 | 565 | { |
0a9ef439 RH |
566 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
567 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; | |
252b5132 | 568 | |
0a9ef439 RH |
569 | int bytes, fix; |
570 | char *p; | |
ab3e48dc | 571 | |
0a9ef439 RH |
572 | if (fragp->fr_type != rs_align_code) |
573 | return; | |
574 | ||
575 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
576 | p = fragp->fr_literal + fragp->fr_fix; | |
577 | fix = 0; | |
578 | ||
579 | if (bytes & 1) | |
580 | { | |
581 | fix = 1; | |
582 | *p++ = 0; | |
583 | bytes--; | |
252b5132 RH |
584 | } |
585 | ||
0a9ef439 RH |
586 | if (bytes & 2) |
587 | { | |
588 | memcpy (p, nop_pattern, 2); | |
589 | p += 2; | |
590 | bytes -= 2; | |
591 | fix += 2; | |
592 | } | |
593 | ||
594 | memcpy (p, multi_nop_pattern, 4); | |
595 | ||
596 | fragp->fr_fix += fix; | |
597 | fragp->fr_var = 4; | |
252b5132 RH |
598 | } |
599 | ||
600 | /* If the last instruction was the first of 2 16 bit insns, | |
601 | output a nop to move the PC to a 32 bit boundary. | |
602 | ||
603 | This is done via an alignment specification since branch relaxing | |
604 | may make it unnecessary. | |
605 | ||
606 | Internally, we need to output one of these each time a 32 bit insn is | |
607 | seen after an insn that is relaxable. */ | |
608 | ||
609 | static void | |
610 | fill_insn (ignore) | |
78a0c6fb | 611 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 612 | { |
0a9ef439 | 613 | frag_align_code (2, 0); |
252b5132 RH |
614 | prev_insn.insn = NULL; |
615 | seen_relaxable_p = 0; | |
616 | } | |
617 | ||
618 | /* Record the symbol so that when we output the insn, we can create | |
619 | a symbol that is at the start of the instruction. This is used | |
620 | to emit the label for the start of a breakpoint without causing | |
621 | the assembler to emit a NOP if the previous instruction was a | |
622 | 16 bit instruction. */ | |
623 | ||
624 | static void | |
625 | debug_sym (ignore) | |
78a0c6fb | 626 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
627 | { |
628 | register char *name; | |
629 | register char delim; | |
630 | register char *end_name; | |
631 | register symbolS *symbolP; | |
632 | register sym_linkS *link; | |
633 | ||
634 | name = input_line_pointer; | |
635 | delim = get_symbol_end (); | |
636 | end_name = input_line_pointer; | |
ab3e48dc | 637 | |
252b5132 RH |
638 | if ((symbolP = symbol_find (name)) == NULL |
639 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
640 | { | |
641 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
642 | } | |
643 | ||
644 | symbol_table_insert (symbolP); | |
6edf0760 NC |
645 | if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section |
646 | || S_IS_EXTERNAL (symbolP) | |
647 | || S_IS_WEAK (symbolP))) | |
252b5132 RH |
648 | /* xgettext:c-format */ |
649 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
650 | ||
651 | else | |
652 | { | |
653 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); | |
654 | link->symbol = symbolP; | |
655 | link->next = debug_sym_link; | |
656 | debug_sym_link = link; | |
f412ead8 | 657 | symbol_get_obj (symbolP)->local = 1; |
252b5132 RH |
658 | } |
659 | ||
660 | *end_name = delim; | |
661 | demand_empty_rest_of_line (); | |
662 | } | |
663 | ||
664 | /* Second pass to expanding the debug symbols, go through linked | |
665 | list of symbols and reassign the address. */ | |
666 | ||
667 | static void | |
668 | expand_debug_syms (syms, align) | |
669 | sym_linkS *syms; | |
670 | int align; | |
671 | { | |
672 | char *save_input_line = input_line_pointer; | |
673 | sym_linkS *next_syms; | |
674 | ||
675 | if (!syms) | |
676 | return; | |
677 | ||
a8150a88 | 678 | (void) frag_align_code (align, 0); |
ab3e48dc | 679 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
252b5132 RH |
680 | { |
681 | symbolS *symbolP = syms->symbol; | |
682 | next_syms = syms->next; | |
683 | input_line_pointer = ".\n"; | |
684 | pseudo_set (symbolP); | |
ab3e48dc | 685 | free ((char *) syms); |
252b5132 RH |
686 | } |
687 | ||
688 | input_line_pointer = save_input_line; | |
689 | } | |
690 | ||
88845958 NC |
691 | void |
692 | m32r_flush_pending_output() | |
693 | { | |
694 | if (debug_sym_link) | |
695 | { | |
696 | expand_debug_syms (debug_sym_link, 1); | |
697 | debug_sym_link = (sym_linkS *) 0; | |
698 | } | |
699 | } | |
700 | ||
252b5132 RH |
701 | /* Cover function to fill_insn called after a label and at end of assembly. |
702 | The result is always 1: we're called in a conditional to see if the | |
703 | current line is a label. */ | |
704 | ||
705 | int | |
706 | m32r_fill_insn (done) | |
707 | int done; | |
708 | { | |
709 | if (prev_seg != NULL) | |
710 | { | |
ab3e48dc | 711 | segT seg = now_seg; |
252b5132 RH |
712 | subsegT subseg = now_subseg; |
713 | ||
714 | subseg_set (prev_seg, prev_subseg); | |
ab3e48dc | 715 | |
252b5132 RH |
716 | fill_insn (0); |
717 | ||
718 | subseg_set (seg, subseg); | |
719 | } | |
720 | ||
721 | if (done && debug_sym_link) | |
722 | { | |
723 | expand_debug_syms (debug_sym_link, 1); | |
ab3e48dc | 724 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
725 | } |
726 | ||
727 | return 1; | |
728 | } | |
729 | \f | |
88845958 NC |
730 | /* The default target format to use. */ |
731 | ||
732 | const char * | |
733 | m32r_target_format () | |
734 | { | |
735 | #ifdef TE_LINUX | |
736 | if (target_big_endian) | |
737 | return "elf32-m32r-linux"; | |
738 | else | |
739 | return "elf32-m32rle-linux"; | |
740 | #else | |
741 | if (target_big_endian) | |
742 | return "elf32-m32r"; | |
743 | else | |
744 | return "elf32-m32rle"; | |
745 | #endif | |
746 | } | |
747 | ||
252b5132 RH |
748 | void |
749 | md_begin () | |
750 | { | |
751 | flagword applicable; | |
ab3e48dc KH |
752 | segT seg; |
753 | subsegT subseg; | |
252b5132 RH |
754 | |
755 | /* Initialize the `cgen' interface. */ | |
ab3e48dc | 756 | |
252b5132 RH |
757 | /* Set the machine number and endian. */ |
758 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, | |
759 | CGEN_CPU_OPEN_ENDIAN, | |
88845958 NC |
760 | (target_big_endian ? |
761 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE), | |
252b5132 RH |
762 | CGEN_CPU_OPEN_END); |
763 | m32r_cgen_init_asm (gas_cgen_cpu_desc); | |
764 | ||
765 | /* The operand instance table is used during optimization to determine | |
766 | which insns can be executed in parallel. It is also used to give | |
767 | warnings regarding operand interference in parallel insns. */ | |
768 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); | |
769 | ||
770 | /* This is a callback from cgen to gas to parse operands. */ | |
771 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
772 | ||
ab3e48dc KH |
773 | #if 0 |
774 | /* Not supported yet. */ | |
252b5132 RH |
775 | /* If a runtime cpu description file was provided, parse it. */ |
776 | if (m32r_cpu_desc != NULL) | |
777 | { | |
ab3e48dc | 778 | const char *errmsg; |
252b5132 RH |
779 | |
780 | errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); | |
781 | if (errmsg != NULL) | |
782 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
783 | } | |
784 | #endif | |
785 | ||
786 | /* Save the current subseg so we can restore it [it's the default one and | |
787 | we don't want the initial section to be .sbss]. */ | |
788 | seg = now_seg; | |
789 | subseg = now_subseg; | |
790 | ||
791 | /* The sbss section is for local .scomm symbols. */ | |
792 | sbss_section = subseg_new (".sbss", 0); | |
ab3e48dc | 793 | |
252b5132 RH |
794 | /* This is copied from perform_an_assembly_pass. */ |
795 | applicable = bfd_applicable_section_flags (stdoutput); | |
796 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ab3e48dc KH |
797 | |
798 | #if 0 | |
799 | /* What does this do? [see perform_an_assembly_pass] */ | |
252b5132 RH |
800 | seg_info (bss_section)->bss = 1; |
801 | #endif | |
802 | ||
803 | subseg_set (seg, subseg); | |
804 | ||
805 | /* We must construct a fake section similar to bfd_com_section | |
806 | but with the name .scommon. */ | |
807 | scom_section = bfd_com_section; | |
808 | scom_section.name = ".scommon"; | |
ab3e48dc KH |
809 | scom_section.output_section = &scom_section; |
810 | scom_section.symbol = &scom_symbol; | |
811 | scom_section.symbol_ptr_ptr = &scom_section.symbol; | |
812 | scom_symbol = *bfd_com_section.symbol; | |
252b5132 | 813 | scom_symbol.name = ".scommon"; |
ab3e48dc | 814 | scom_symbol.section = &scom_section; |
252b5132 | 815 | |
925c058e | 816 | allow_m32rx (enable_m32rx); |
002de68b | 817 | |
07726851 | 818 | gas_cgen_initialize_saved_fixups_array (); |
925c058e DE |
819 | } |
820 | ||
821 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ | |
822 | ((operand)->hw_type == HW_H_COND \ | |
823 | || ((operand)->hw_type == HW_H_PSW) \ | |
824 | || ((operand)->hw_type == HW_H_CR \ | |
825 | && (indices [index] == 0 || indices [index] == 1))) | |
826 | ||
827 | /* Returns true if an output of instruction 'a' is referenced by an operand | |
828 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
829 | checked, otherwise its inputs are examined. */ | |
830 | ||
78a0c6fb AM |
831 | static int first_writes_to_seconds_operands |
832 | PARAMS ((m32r_insn *, m32r_insn *, const int)); | |
833 | ||
925c058e DE |
834 | static int |
835 | first_writes_to_seconds_operands (a, b, check_outputs) | |
ab3e48dc KH |
836 | m32r_insn *a; |
837 | m32r_insn *b; | |
838 | const int check_outputs; | |
925c058e | 839 | { |
ab3e48dc KH |
840 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
841 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); | |
925c058e DE |
842 | int a_index; |
843 | ||
b145f546 NC |
844 | if (ignore_parallel_conflicts) |
845 | return 0; | |
846 | ||
925c058e DE |
847 | /* If at least one of the instructions takes no operands, then there is |
848 | nothing to check. There really are instructions without operands, | |
849 | eg 'nop'. */ | |
850 | if (a_operands == NULL || b_ops == NULL) | |
851 | return 0; | |
ab3e48dc | 852 | |
925c058e DE |
853 | /* Scan the operand list of 'a' looking for an output operand. */ |
854 | for (a_index = 0; | |
855 | a_operands->type != CGEN_OPINST_END; | |
856 | a_index ++, a_operands ++) | |
857 | { | |
858 | if (a_operands->type == CGEN_OPINST_OUTPUT) | |
859 | { | |
860 | int b_index; | |
ab3e48dc | 861 | const CGEN_OPINST *b_operands = b_ops; |
925c058e DE |
862 | |
863 | /* Special Case: | |
864 | The Condition bit 'C' is a shadow of the CBR register (control | |
865 | register 1) and also a shadow of bit 31 of the program status | |
866 | word (control register 0). For now this is handled here, rather | |
ab3e48dc KH |
867 | than by cgen.... */ |
868 | ||
925c058e DE |
869 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
870 | { | |
871 | /* Scan operand list of 'b' looking for another reference to the | |
872 | condition bit, which goes in the right direction. */ | |
873 | for (b_index = 0; | |
874 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 875 | b_index++, b_operands++) |
925c058e DE |
876 | { |
877 | if ((b_operands->type | |
878 | == (check_outputs | |
879 | ? CGEN_OPINST_OUTPUT | |
880 | : CGEN_OPINST_INPUT)) | |
881 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) | |
882 | return 1; | |
883 | } | |
884 | } | |
885 | else | |
886 | { | |
887 | /* Scan operand list of 'b' looking for an operand that | |
888 | references the same hardware element, and which goes in the | |
889 | right direction. */ | |
890 | for (b_index = 0; | |
891 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 892 | b_index++, b_operands++) |
925c058e DE |
893 | { |
894 | if ((b_operands->type | |
895 | == (check_outputs | |
896 | ? CGEN_OPINST_OUTPUT | |
897 | : CGEN_OPINST_INPUT)) | |
898 | && (b_operands->hw_type == a_operands->hw_type) | |
ab3e48dc | 899 | && (a->indices[a_index] == b->indices[b_index])) |
925c058e DE |
900 | return 1; |
901 | } | |
902 | } | |
903 | } | |
904 | } | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
909 | /* Returns true if the insn can (potentially) alter the program counter. */ | |
910 | ||
78a0c6fb AM |
911 | static int writes_to_pc PARAMS ((m32r_insn *)); |
912 | ||
925c058e DE |
913 | static int |
914 | writes_to_pc (a) | |
ab3e48dc | 915 | m32r_insn *a; |
925c058e | 916 | { |
ab3e48dc KH |
917 | #if 0 |
918 | /* Once PC operands are working.... */ | |
919 | const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc, | |
920 | a->insn); | |
925c058e DE |
921 | |
922 | if (a_operands == NULL) | |
923 | return 0; | |
924 | ||
925 | while (a_operands->type != CGEN_OPINST_END) | |
926 | { | |
927 | if (a_operands->operand != NULL | |
ab3e48dc KH |
928 | && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, |
929 | a_operands->operand) == M32R_OPERAND_PC) | |
925c058e | 930 | return 1; |
ab3e48dc KH |
931 | |
932 | a_operands++; | |
925c058e DE |
933 | } |
934 | #else | |
935 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) | |
936 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) | |
937 | return 1; | |
938 | #endif | |
939 | return 0; | |
940 | } | |
941 | ||
ab3e48dc KH |
942 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
943 | Otherwise return a pointer to an error message explaining why not. */ | |
925c058e | 944 | |
78a0c6fb AM |
945 | static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *)); |
946 | ||
925c058e DE |
947 | static const char * |
948 | can_make_parallel (a, b) | |
ab3e48dc KH |
949 | m32r_insn *a; |
950 | m32r_insn *b; | |
925c058e DE |
951 | { |
952 | PIPE_ATTR a_pipe; | |
953 | PIPE_ATTR b_pipe; | |
ab3e48dc | 954 | |
925c058e | 955 | /* Make sure the instructions are the right length. */ |
ab3e48dc KH |
956 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
957 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) | |
958 | abort (); | |
925c058e | 959 | |
b34976b6 | 960 | if (first_writes_to_seconds_operands (a, b, TRUE)) |
b145f546 | 961 | return _("instructions write to the same destination register."); |
ab3e48dc | 962 | |
925c058e DE |
963 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
964 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); | |
965 | ||
966 | /* Make sure that the instructions use the correct execution pipelines. */ | |
ab3e48dc | 967 | if (a_pipe == PIPE_NONE |
925c058e DE |
968 | || b_pipe == PIPE_NONE) |
969 | return _("Instructions do not use parallel execution pipelines."); | |
970 | ||
971 | /* Leave this test for last, since it is the only test that can | |
972 | go away if the instructions are swapped, and we want to make | |
973 | sure that any other errors are detected before this happens. */ | |
ab3e48dc | 974 | if (a_pipe == PIPE_S |
88845958 NC |
975 | || b_pipe == PIPE_O |
976 | || (b_pipe == PIPE_O_OS && (enable_m32rx != 2))) | |
925c058e | 977 | return _("Instructions share the same execution pipeline"); |
ab3e48dc | 978 | |
925c058e DE |
979 | return NULL; |
980 | } | |
981 | ||
982 | /* Force the top bit of the second 16-bit insn to be set. */ | |
983 | ||
78a0c6fb AM |
984 | static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR)); |
985 | ||
925c058e DE |
986 | static void |
987 | make_parallel (buffer) | |
988 | CGEN_INSN_BYTES_PTR buffer; | |
989 | { | |
990 | #if CGEN_INT_INSN_P | |
991 | *buffer |= 0x8000; | |
992 | #else | |
ab3e48dc | 993 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
994 | |= 0x80; |
995 | #endif | |
252b5132 RH |
996 | } |
997 | ||
925c058e | 998 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
252b5132 | 999 | |
78a0c6fb AM |
1000 | static void target_make_parallel PARAMS ((char *)); |
1001 | ||
925c058e DE |
1002 | static void |
1003 | target_make_parallel (buffer) | |
1004 | char *buffer; | |
1005 | { | |
ab3e48dc | 1006 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
1007 | |= 0x80; |
1008 | } | |
1009 | ||
1010 | /* Assemble two instructions with an explicit parallel operation (||) or | |
1011 | sequential operation (->). */ | |
1012 | ||
78a0c6fb AM |
1013 | static void assemble_two_insns PARAMS ((char *, char *, int)); |
1014 | ||
925c058e DE |
1015 | static void |
1016 | assemble_two_insns (str, str2, parallel_p) | |
ab3e48dc KH |
1017 | char *str; |
1018 | char *str2; | |
1019 | int parallel_p; | |
925c058e | 1020 | { |
ab3e48dc | 1021 | char *str3; |
925c058e DE |
1022 | m32r_insn first; |
1023 | m32r_insn second; | |
ab3e48dc KH |
1024 | char *errmsg; |
1025 | char save_str2 = *str2; | |
925c058e | 1026 | |
67c1ffbe | 1027 | /* Separate the two instructions. */ |
ab3e48dc | 1028 | *str2 = 0; |
925c058e DE |
1029 | |
1030 | /* Make sure the two insns begin on a 32 bit boundary. | |
1031 | This is also done for the serial case (foo -> bar), relaxing doesn't | |
1032 | affect insns written like this. | |
1033 | Note that we must always do this as we can't assume anything about | |
1034 | whether we're currently on a 32 bit boundary or not. Relaxing may | |
1035 | change this. */ | |
1036 | fill_insn (0); | |
1037 | ||
1038 | first.debug_sym_link = debug_sym_link; | |
ab3e48dc | 1039 | debug_sym_link = (sym_linkS *) 0; |
925c058e DE |
1040 | |
1041 | /* Parse the first instruction. */ | |
1042 | if (! (first.insn = m32r_cgen_assemble_insn | |
1043 | (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) | |
1044 | { | |
1045 | as_bad (errmsg); | |
1046 | return; | |
1047 | } | |
1048 | ||
1049 | /* Check it. */ | |
1050 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) | |
1051 | { | |
ab3e48dc | 1052 | /* xgettext:c-format */ |
925c058e DE |
1053 | as_bad (_("not a 16 bit instruction '%s'"), str); |
1054 | return; | |
1055 | } | |
88845958 NC |
1056 | #ifdef E_M32R2_ARCH |
1057 | else if ((enable_m32rx == 1) | |
1058 | /* FIXME: Need standard macro to perform this test. */ | |
1059 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1060 | & (1 << MACH_M32R2)) | |
1061 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1062 | & (1 << MACH_M32RX))))) | |
1063 | { | |
1064 | /* xgettext:c-format */ | |
1065 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1066 | return; | |
1067 | } | |
1068 | else if ((! enable_special | |
1069 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
1070 | || (! enable_special_m32r | |
1071 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R))) | |
1072 | #else | |
925c058e DE |
1073 | else if (! enable_special |
1074 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1075 | #endif |
925c058e | 1076 | { |
ab3e48dc | 1077 | /* xgettext:c-format */ |
925c058e DE |
1078 | as_bad (_("unknown instruction '%s'"), str); |
1079 | return; | |
1080 | } | |
1081 | else if (! enable_m32rx | |
ab3e48dc KH |
1082 | /* FIXME: Need standard macro to perform this test. */ |
1083 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1084 | == (1 << MACH_M32RX))) | |
925c058e | 1085 | { |
ab3e48dc | 1086 | /* xgettext:c-format */ |
925c058e DE |
1087 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1088 | return; | |
1089 | } | |
ab3e48dc | 1090 | |
925c058e | 1091 | /* Check to see if this is an allowable parallel insn. */ |
ab3e48dc KH |
1092 | if (parallel_p |
1093 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 1094 | { |
ab3e48dc | 1095 | /* xgettext:c-format */ |
925c058e DE |
1096 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
1097 | return; | |
1098 | } | |
ab3e48dc KH |
1099 | |
1100 | /* Restore the original assembly text, just in case it is needed. */ | |
1101 | *str2 = save_str2; | |
1102 | ||
1103 | /* Save the original string pointer. */ | |
1104 | str3 = str; | |
1105 | ||
1106 | /* Advanced past the parsed string. */ | |
1107 | str = str2 + 2; | |
1108 | ||
1109 | /* Remember the entire string in case it is needed for error | |
1110 | messages. */ | |
1111 | str2 = str3; | |
925c058e DE |
1112 | |
1113 | /* Convert the opcode to lower case. */ | |
1114 | { | |
1115 | char *s2 = str; | |
ab3e48dc | 1116 | |
3882b010 | 1117 | while (ISSPACE (*s2++)) |
925c058e DE |
1118 | continue; |
1119 | ||
1120 | --s2; | |
1121 | ||
3882b010 | 1122 | while (ISALNUM (*s2)) |
925c058e | 1123 | { |
3882b010 | 1124 | *s2 = TOLOWER (*s2); |
ab3e48dc | 1125 | s2++; |
925c058e DE |
1126 | } |
1127 | } | |
ab3e48dc KH |
1128 | |
1129 | /* Preserve any fixups that have been generated and reset the list | |
1130 | to empty. */ | |
002de68b | 1131 | gas_cgen_save_fixups (0); |
925c058e DE |
1132 | |
1133 | /* Get the indices of the operands of the instruction. */ | |
1134 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
1135 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
1136 | /* FIXME: ALIAS insns do not have operands, so we use this function | |
1137 | to find the equivalent insn and overwrite the value stored in our | |
1138 | structure. We still need the original insn, however, since this | |
1139 | may have certain attributes that are not present in the unaliased | |
1140 | version (eg relaxability). When aliases behave differently this | |
1141 | may have to change. */ | |
1142 | first.orig_insn = first.insn; | |
1143 | { | |
1144 | CGEN_FIELDS tmp_fields; | |
1145 | first.insn = cgen_lookup_get_insn_operands | |
1146 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, | |
1147 | first.indices, &tmp_fields); | |
1148 | } | |
ab3e48dc | 1149 | |
925c058e DE |
1150 | if (first.insn == NULL) |
1151 | as_fatal (_("internal error: lookup/get operands failed")); | |
1152 | ||
1153 | second.debug_sym_link = NULL; | |
1154 | ||
1155 | /* Parse the second instruction. */ | |
1156 | if (! (second.insn = m32r_cgen_assemble_insn | |
1157 | (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) | |
1158 | { | |
1159 | as_bad (errmsg); | |
1160 | return; | |
1161 | } | |
1162 | ||
1163 | /* Check it. */ | |
1164 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) | |
1165 | { | |
ab3e48dc | 1166 | /* xgettext:c-format */ |
925c058e DE |
1167 | as_bad (_("not a 16 bit instruction '%s'"), str); |
1168 | return; | |
1169 | } | |
88845958 NC |
1170 | #ifdef E_M32R2_ARCH |
1171 | else if ((enable_m32rx == 1) | |
1172 | /* FIXME: Need standard macro to perform this test. */ | |
1173 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1174 | & (1 << MACH_M32R2)) | |
1175 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1176 | & (1 << MACH_M32RX))))) | |
1177 | { | |
1178 | /* xgettext:c-format */ | |
1179 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1180 | return; | |
1181 | } | |
1182 | else if ((! enable_special | |
1183 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
1184 | || (! enable_special_m32r | |
1185 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))) | |
1186 | #else | |
925c058e DE |
1187 | else if (! enable_special |
1188 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1189 | #endif |
925c058e | 1190 | { |
ab3e48dc | 1191 | /* xgettext:c-format */ |
925c058e DE |
1192 | as_bad (_("unknown instruction '%s'"), str); |
1193 | return; | |
1194 | } | |
1195 | else if (! enable_m32rx | |
1196 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1197 | { | |
ab3e48dc | 1198 | /* xgettext:c-format */ |
925c058e DE |
1199 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1200 | return; | |
1201 | } | |
1202 | ||
1203 | /* Check to see if this is an allowable parallel insn. */ | |
ab3e48dc KH |
1204 | if (parallel_p |
1205 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 1206 | { |
ab3e48dc | 1207 | /* xgettext:c-format */ |
925c058e DE |
1208 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
1209 | return; | |
1210 | } | |
ab3e48dc | 1211 | |
925c058e DE |
1212 | if (parallel_p && ! enable_m32rx) |
1213 | { | |
1214 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP | |
1215 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) | |
1216 | { | |
ab3e48dc | 1217 | /* xgettext:c-format */ |
925c058e DE |
1218 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
1219 | return; | |
1220 | } | |
1221 | } | |
1222 | ||
1223 | /* Get the indices of the operands of the instruction. */ | |
1224 | second.orig_insn = second.insn; | |
1225 | { | |
1226 | CGEN_FIELDS tmp_fields; | |
1227 | second.insn = cgen_lookup_get_insn_operands | |
1228 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, | |
1229 | second.indices, &tmp_fields); | |
1230 | } | |
ab3e48dc | 1231 | |
925c058e DE |
1232 | if (second.insn == NULL) |
1233 | as_fatal (_("internal error: lookup/get operands failed")); | |
1234 | ||
1235 | /* We assume that if the first instruction writes to a register that is | |
1236 | read by the second instruction it is because the programmer intended | |
1237 | this to happen, (after all they have explicitly requested that these | |
1238 | two instructions be executed in parallel). Although if the global | |
1239 | variable warn_explicit_parallel_conflicts is true then we do generate | |
1240 | a warning message. Similarly we assume that parallel branch and jump | |
1241 | instructions are deliberate and should not produce errors. */ | |
ab3e48dc | 1242 | |
925c058e DE |
1243 | if (parallel_p && warn_explicit_parallel_conflicts) |
1244 | { | |
b34976b6 | 1245 | if (first_writes_to_seconds_operands (&first, &second, FALSE)) |
ab3e48dc | 1246 | /* xgettext:c-format */ |
b145f546 | 1247 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
ab3e48dc | 1248 | |
b34976b6 | 1249 | if (first_writes_to_seconds_operands (&second, &first, FALSE)) |
ab3e48dc | 1250 | /* xgettext:c-format */ |
b145f546 | 1251 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
925c058e | 1252 | } |
ab3e48dc | 1253 | |
925c058e | 1254 | if (!parallel_p |
ab3e48dc | 1255 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
925c058e DE |
1256 | { |
1257 | /* Get the fixups for the first instruction. */ | |
002de68b | 1258 | gas_cgen_swap_fixups (0); |
925c058e DE |
1259 | |
1260 | /* Write it out. */ | |
1261 | expand_debug_syms (first.debug_sym_link, 1); | |
1262 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc KH |
1263 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
1264 | ||
925c058e DE |
1265 | /* Force the top bit of the second insn to be set. */ |
1266 | if (parallel_p) | |
1267 | make_parallel (second.buffer); | |
1268 | ||
1269 | /* Get its fixups. */ | |
002de68b | 1270 | gas_cgen_restore_fixups (0); |
925c058e DE |
1271 | |
1272 | /* Write it out. */ | |
1273 | expand_debug_syms (second.debug_sym_link, 1); | |
1274 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc | 1275 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
925c058e DE |
1276 | } |
1277 | /* Try swapping the instructions to see if they work that way. */ | |
ab3e48dc | 1278 | else if (can_make_parallel (&second, &first) == NULL) |
925c058e DE |
1279 | { |
1280 | /* Write out the second instruction first. */ | |
1281 | expand_debug_syms (second.debug_sym_link, 1); | |
1282 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc KH |
1283 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
1284 | ||
925c058e DE |
1285 | /* Force the top bit of the first instruction to be set. */ |
1286 | make_parallel (first.buffer); | |
1287 | ||
1288 | /* Get the fixups for the first instruction. */ | |
002de68b | 1289 | gas_cgen_restore_fixups (0); |
925c058e DE |
1290 | |
1291 | /* Write out the first instruction. */ | |
1292 | expand_debug_syms (first.debug_sym_link, 1); | |
1293 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc | 1294 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
925c058e DE |
1295 | } |
1296 | else | |
1297 | { | |
1298 | as_bad ("'%s': %s", str2, errmsg); | |
1299 | return; | |
1300 | } | |
ab3e48dc | 1301 | |
88845958 NC |
1302 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL) |
1303 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
1304 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; | |
1305 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R) | |
1306 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)) | |
1307 | m32r_flags |= E_M32R_HAS_BIT_INST; | |
1308 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT) | |
1309 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT)) | |
1310 | m32r_flags |= E_M32R_HAS_FLOAT_INST; | |
1311 | ||
925c058e DE |
1312 | /* Set these so m32r_fill_insn can use them. */ |
1313 | prev_seg = now_seg; | |
1314 | prev_subseg = now_subseg; | |
1315 | } | |
252b5132 RH |
1316 | |
1317 | void | |
1318 | md_assemble (str) | |
ab3e48dc | 1319 | char *str; |
252b5132 RH |
1320 | { |
1321 | m32r_insn insn; | |
ab3e48dc KH |
1322 | char *errmsg; |
1323 | char *str2 = NULL; | |
252b5132 RH |
1324 | |
1325 | /* Initialize GAS's cgen interface for a new instruction. */ | |
1326 | gas_cgen_init_parse (); | |
1327 | ||
67c1ffbe | 1328 | /* Look for a parallel instruction separator. */ |
925c058e DE |
1329 | if ((str2 = strstr (str, "||")) != NULL) |
1330 | { | |
1331 | assemble_two_insns (str, str2, 1); | |
88845958 | 1332 | m32r_flags |= E_M32R_HAS_PARALLEL; |
925c058e DE |
1333 | return; |
1334 | } | |
1335 | ||
67c1ffbe | 1336 | /* Also look for a sequential instruction separator. */ |
925c058e DE |
1337 | if ((str2 = strstr (str, "->")) != NULL) |
1338 | { | |
1339 | assemble_two_insns (str, str2, 0); | |
1340 | return; | |
1341 | } | |
ab3e48dc | 1342 | |
252b5132 | 1343 | insn.debug_sym_link = debug_sym_link; |
ab3e48dc | 1344 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
1345 | |
1346 | insn.insn = m32r_cgen_assemble_insn | |
ab3e48dc KH |
1347 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
1348 | ||
252b5132 RH |
1349 | if (!insn.insn) |
1350 | { | |
1351 | as_bad (errmsg); | |
1352 | return; | |
1353 | } | |
1354 | ||
88845958 NC |
1355 | #ifdef E_M32R2_ARCH |
1356 | if ((enable_m32rx == 1) | |
1357 | /* FIXME: Need standard macro to perform this test. */ | |
1358 | && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) | |
1359 | & (1 << MACH_M32R2)) | |
1360 | && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) | |
1361 | & (1 << MACH_M32RX))))) | |
1362 | { | |
1363 | /* xgettext:c-format */ | |
1364 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1365 | return; | |
1366 | } | |
1367 | else if ((! enable_special | |
1368 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
1369 | || (! enable_special_m32r | |
1370 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))) | |
1371 | #else | |
925c058e DE |
1372 | if (! enable_special |
1373 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1374 | #endif |
925c058e | 1375 | { |
ab3e48dc | 1376 | /* xgettext:c-format */ |
925c058e DE |
1377 | as_bad (_("unknown instruction '%s'"), str); |
1378 | return; | |
1379 | } | |
1380 | else if (! enable_m32rx | |
1381 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1382 | { | |
ab3e48dc | 1383 | /* xgettext:c-format */ |
925c058e DE |
1384 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1385 | return; | |
1386 | } | |
ab3e48dc | 1387 | |
88845958 NC |
1388 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
1389 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; | |
1390 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)) | |
1391 | m32r_flags |= E_M32R_HAS_BIT_INST; | |
1392 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT)) | |
1393 | m32r_flags |= E_M32R_HAS_FLOAT_INST; | |
1394 | ||
252b5132 RH |
1395 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
1396 | { | |
1397 | /* 32 bit insns must live on 32 bit boundaries. */ | |
1398 | if (prev_insn.insn || seen_relaxable_p) | |
1399 | { | |
1400 | /* ??? If calling fill_insn too many times turns us into a memory | |
1401 | pig, can we call a fn to assemble a nop instead of | |
1402 | !seen_relaxable_p? */ | |
1403 | fill_insn (0); | |
1404 | } | |
1405 | ||
1406 | expand_debug_syms (insn.debug_sym_link, 2); | |
1407 | ||
1408 | /* Doesn't really matter what we pass for RELAX_P here. */ | |
1409 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
ab3e48dc | 1410 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
252b5132 RH |
1411 | } |
1412 | else | |
1413 | { | |
1414 | int on_32bit_boundary_p; | |
b34976b6 | 1415 | int swap = FALSE; |
252b5132 RH |
1416 | |
1417 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
ab3e48dc | 1418 | abort (); |
252b5132 RH |
1419 | |
1420 | insn.orig_insn = insn.insn; | |
1421 | ||
925c058e DE |
1422 | /* If the previous insn was relaxable, then it may be expanded |
1423 | to fill the current 16 bit slot. Emit a NOP here to occupy | |
1424 | this slot, so that we can start at optimizing at a 32 bit | |
1425 | boundary. */ | |
1426 | if (prev_insn.insn && seen_relaxable_p && optimize) | |
1427 | fill_insn (0); | |
ab3e48dc | 1428 | |
925c058e DE |
1429 | if (enable_m32rx) |
1430 | { | |
1431 | /* Get the indices of the operands of the instruction. | |
1432 | FIXME: See assemble_parallel for notes on orig_insn. */ | |
1433 | { | |
1434 | CGEN_FIELDS tmp_fields; | |
1435 | insn.insn = cgen_lookup_get_insn_operands | |
1436 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, | |
1437 | 16, insn.indices, &tmp_fields); | |
1438 | } | |
ab3e48dc | 1439 | |
925c058e DE |
1440 | if (insn.insn == NULL) |
1441 | as_fatal (_("internal error: lookup/get operands failed")); | |
1442 | } | |
1443 | ||
252b5132 RH |
1444 | /* Compute whether we're on a 32 bit boundary or not. |
1445 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1446 | on_32bit_boundary_p = prev_insn.insn == NULL; | |
1447 | ||
097dba13 NC |
1448 | /* Change a frag to, if each insn to swap is in a different frag. |
1449 | It must keep only one instruction in a frag. */ | |
1450 | if (parallel() && on_32bit_boundary_p) | |
1451 | { | |
1452 | frag_wane (frag_now); | |
1453 | frag_new (0); | |
1454 | } | |
1455 | ||
925c058e DE |
1456 | /* Look to see if this instruction can be combined with the |
1457 | previous instruction to make one, parallel, 32 bit instruction. | |
1458 | If the previous instruction (potentially) changed the flow of | |
1459 | program control, then it cannot be combined with the current | |
1460 | instruction. If the current instruction is relaxable, then it | |
1461 | might be replaced with a longer version, so we cannot combine it. | |
1462 | Also if the output of the previous instruction is used as an | |
1463 | input to the current instruction then it cannot be combined. | |
1464 | Otherwise call can_make_parallel() with both orderings of the | |
1465 | instructions to see if they can be combined. */ | |
ab3e48dc | 1466 | if (! on_32bit_boundary_p |
88845958 | 1467 | && parallel () |
ab3e48dc KH |
1468 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 |
1469 | && ! writes_to_pc (&prev_insn) | |
b34976b6 | 1470 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) |
925c058e | 1471 | { |
ab3e48dc | 1472 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
925c058e | 1473 | make_parallel (insn.buffer); |
ab3e48dc | 1474 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
b34976b6 | 1475 | swap = TRUE; |
925c058e | 1476 | } |
252b5132 RH |
1477 | |
1478 | expand_debug_syms (insn.debug_sym_link, 1); | |
1479 | ||
1480 | { | |
1481 | int i; | |
1482 | finished_insnS fi; | |
1483 | ||
1484 | /* Ensure each pair of 16 bit insns is in the same frag. */ | |
1485 | frag_grow (4); | |
1486 | ||
1487 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, | |
ab3e48dc KH |
1488 | CGEN_FIELDS_BITSIZE (&insn.fields), |
1489 | 1 /* relax_p */, &fi); | |
252b5132 RH |
1490 | insn.addr = fi.addr; |
1491 | insn.frag = fi.frag; | |
1492 | insn.num_fixups = fi.num_fixups; | |
1493 | for (i = 0; i < fi.num_fixups; ++i) | |
1494 | insn.fixups[i] = fi.fixups[i]; | |
1495 | } | |
1496 | ||
925c058e DE |
1497 | if (swap) |
1498 | { | |
ab3e48dc | 1499 | int i, tmp; |
925c058e DE |
1500 | |
1501 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
1502 | ||
1503 | /* Swap the two insns */ | |
ab3e48dc KH |
1504 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
1505 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); | |
925c058e DE |
1506 | |
1507 | target_make_parallel (insn.addr); | |
1508 | ||
1509 | /* Swap any relaxable frags recorded for the two insns. */ | |
1510 | /* FIXME: Clarify. relaxation precludes parallel insns */ | |
1511 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
1512 | prev_insn.frag->fr_opcode = insn.addr; | |
1513 | else if (insn.frag->fr_opcode == insn.addr) | |
1514 | insn.frag->fr_opcode = prev_insn.addr; | |
1515 | ||
097dba13 NC |
1516 | /* Change a frag to, if each insn is in a different frag. |
1517 | It must keep only one instruction in a frag. */ | |
1518 | if (prev_insn.frag != insn.frag) | |
1519 | { | |
1520 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1521 | prev_insn.fixups[i]->fx_frag = insn.frag; | |
1522 | for (i = 0; i < insn.num_fixups; ++i) | |
1523 | insn.fixups[i]->fx_frag = prev_insn.frag; | |
1524 | } | |
1525 | else | |
1526 | { | |
1527 | /* Update the addresses in any fixups. | |
1528 | Note that we don't have to handle the case where each insn is in | |
1529 | a different frag as we ensure they're in the same frag above. */ | |
1530 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1531 | prev_insn.fixups[i]->fx_where += 2; | |
1532 | for (i = 0; i < insn.num_fixups; ++i) | |
1533 | insn.fixups[i]->fx_where -= 2; | |
1534 | } | |
925c058e | 1535 | } |
252b5132 RH |
1536 | |
1537 | /* Keep track of whether we've seen a pair of 16 bit insns. | |
1538 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1539 | if (on_32bit_boundary_p) | |
1540 | prev_insn = insn; | |
1541 | else | |
1542 | prev_insn.insn = NULL; | |
ab3e48dc | 1543 | |
252b5132 RH |
1544 | /* If the insn needs the following one to be on a 32 bit boundary |
1545 | (e.g. subroutine calls), fill this insn's slot. */ | |
1546 | if (on_32bit_boundary_p | |
1547 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) | |
1548 | fill_insn (0); | |
1549 | ||
1550 | /* If this is a relaxable insn (can be replaced with a larger version) | |
1551 | mark the fact so that we can emit an alignment directive for a | |
1552 | following 32 bit insn if we see one. */ | |
1553 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) | |
1554 | seen_relaxable_p = 1; | |
1555 | } | |
1556 | ||
1557 | /* Set these so m32r_fill_insn can use them. */ | |
1558 | prev_seg = now_seg; | |
1559 | prev_subseg = now_subseg; | |
1560 | } | |
1561 | ||
1562 | /* The syntax in the manual says constants begin with '#'. | |
1563 | We just ignore it. */ | |
1564 | ||
ab3e48dc | 1565 | void |
252b5132 | 1566 | md_operand (expressionP) |
ab3e48dc | 1567 | expressionS *expressionP; |
252b5132 | 1568 | { |
ab3e48dc | 1569 | if (*input_line_pointer == '#') |
252b5132 | 1570 | { |
ab3e48dc | 1571 | input_line_pointer++; |
252b5132 RH |
1572 | expression (expressionP); |
1573 | } | |
1574 | } | |
1575 | ||
1576 | valueT | |
1577 | md_section_align (segment, size) | |
ab3e48dc | 1578 | segT segment; |
252b5132 RH |
1579 | valueT size; |
1580 | { | |
1581 | int align = bfd_get_section_alignment (stdoutput, segment); | |
1582 | return ((size + (1 << align) - 1) & (-1 << align)); | |
1583 | } | |
1584 | ||
1585 | symbolS * | |
1586 | md_undefined_symbol (name) | |
78a0c6fb | 1587 | char *name ATTRIBUTE_UNUSED; |
252b5132 RH |
1588 | { |
1589 | return 0; | |
1590 | } | |
1591 | \f | |
1592 | /* .scomm pseudo-op handler. | |
1593 | ||
1594 | This is a new pseudo-op to handle putting objects in .scommon. | |
ab3e48dc KH |
1595 | By doing this the linker won't need to do any work, |
1596 | and more importantly it removes the implicit -G arg necessary to | |
1597 | correctly link the object file. */ | |
252b5132 RH |
1598 | |
1599 | static void | |
1600 | m32r_scomm (ignore) | |
78a0c6fb | 1601 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 1602 | { |
ab3e48dc KH |
1603 | register char *name; |
1604 | register char c; | |
1605 | register char *p; | |
1606 | offsetT size; | |
1607 | register symbolS *symbolP; | |
1608 | offsetT align; | |
1609 | int align2; | |
252b5132 RH |
1610 | |
1611 | name = input_line_pointer; | |
1612 | c = get_symbol_end (); | |
1613 | ||
ab3e48dc | 1614 | /* Just after name is now '\0'. */ |
252b5132 | 1615 | p = input_line_pointer; |
ab3e48dc | 1616 | *p = c; |
252b5132 | 1617 | SKIP_WHITESPACE (); |
ab3e48dc | 1618 | if (*input_line_pointer != ',') |
252b5132 RH |
1619 | { |
1620 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); | |
1621 | ignore_rest_of_line (); | |
1622 | return; | |
1623 | } | |
1624 | ||
ab3e48dc KH |
1625 | /* Skip ','. */ |
1626 | input_line_pointer++; | |
252b5132 RH |
1627 | if ((size = get_absolute_expression ()) < 0) |
1628 | { | |
ab3e48dc | 1629 | /* xgettext:c-format */ |
252b5132 RH |
1630 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
1631 | ignore_rest_of_line (); | |
1632 | return; | |
1633 | } | |
1634 | ||
1635 | /* The third argument to .scomm is the alignment. */ | |
ab3e48dc | 1636 | if (*input_line_pointer != ',') |
252b5132 RH |
1637 | align = 8; |
1638 | else | |
1639 | { | |
ab3e48dc | 1640 | ++input_line_pointer; |
252b5132 RH |
1641 | align = get_absolute_expression (); |
1642 | if (align <= 0) | |
1643 | { | |
1644 | as_warn (_("ignoring bad alignment")); | |
1645 | align = 8; | |
1646 | } | |
1647 | } | |
ab3e48dc | 1648 | |
252b5132 RH |
1649 | /* Convert to a power of 2 alignment. */ |
1650 | if (align) | |
1651 | { | |
ab3e48dc | 1652 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
252b5132 RH |
1653 | continue; |
1654 | if (align != 1) | |
1655 | { | |
1656 | as_bad (_("Common alignment not a power of 2")); | |
1657 | ignore_rest_of_line (); | |
1658 | return; | |
1659 | } | |
1660 | } | |
1661 | else | |
1662 | align2 = 0; | |
1663 | ||
ab3e48dc | 1664 | *p = 0; |
252b5132 | 1665 | symbolP = symbol_find_or_make (name); |
ab3e48dc | 1666 | *p = c; |
252b5132 RH |
1667 | |
1668 | if (S_IS_DEFINED (symbolP)) | |
1669 | { | |
ab3e48dc | 1670 | /* xgettext:c-format */ |
252b5132 RH |
1671 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
1672 | S_GET_NAME (symbolP)); | |
1673 | ignore_rest_of_line (); | |
1674 | return; | |
1675 | } | |
1676 | ||
1677 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1678 | { | |
ab3e48dc | 1679 | /* xgettext:c-format */ |
252b5132 RH |
1680 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
1681 | S_GET_NAME (symbolP), | |
1682 | (long) S_GET_VALUE (symbolP), | |
1683 | (long) size); | |
1684 | ||
1685 | ignore_rest_of_line (); | |
1686 | return; | |
1687 | } | |
1688 | ||
f412ead8 | 1689 | if (symbol_get_obj (symbolP)->local) |
252b5132 | 1690 | { |
ab3e48dc KH |
1691 | segT old_sec = now_seg; |
1692 | int old_subsec = now_subseg; | |
1693 | char *pfrag; | |
252b5132 RH |
1694 | |
1695 | record_alignment (sbss_section, align2); | |
1696 | subseg_set (sbss_section, 0); | |
ab3e48dc | 1697 | |
252b5132 RH |
1698 | if (align2) |
1699 | frag_align (align2, 0, 0); | |
ab3e48dc | 1700 | |
252b5132 | 1701 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
f412ead8 | 1702 | symbol_get_frag (symbolP)->fr_symbol = 0; |
ab3e48dc | 1703 | |
f412ead8 | 1704 | symbol_set_frag (symbolP, frag_now); |
ab3e48dc | 1705 | |
252b5132 RH |
1706 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1707 | (char *) 0); | |
ab3e48dc | 1708 | *pfrag = 0; |
252b5132 RH |
1709 | S_SET_SIZE (symbolP, size); |
1710 | S_SET_SEGMENT (symbolP, sbss_section); | |
1711 | S_CLEAR_EXTERNAL (symbolP); | |
1712 | subseg_set (old_sec, old_subsec); | |
1713 | } | |
1714 | else | |
1715 | { | |
1716 | S_SET_VALUE (symbolP, (valueT) size); | |
1717 | S_SET_ALIGN (symbolP, align2); | |
1718 | S_SET_EXTERNAL (symbolP); | |
ab3e48dc | 1719 | S_SET_SEGMENT (symbolP, &scom_section); |
252b5132 RH |
1720 | } |
1721 | ||
1722 | demand_empty_rest_of_line (); | |
1723 | } | |
1724 | \f | |
1725 | /* Interface to relax_segment. */ | |
1726 | ||
1727 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1728 | ||
1729 | const relax_typeS md_relax_table[] = | |
1730 | { | |
1731 | /* The fields are: | |
1732 | 1) most positive reach of this state, | |
1733 | 2) most negative reach of this state, | |
1734 | 3) how many bytes this mode will add to the size of the current frag | |
1735 | 4) which index into the table to try if we can't fit into this one. */ | |
1736 | ||
1737 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1738 | each list. */ | |
1739 | {1, 1, 0, 0}, | |
1740 | ||
1741 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1742 | so we subtract 2 from the following. */ | |
1743 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1744 | This doesn't handle a branch in the right slot at the border: | |
1745 | the "& -4" isn't taken into account. It's not important enough to | |
1746 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1747 | case). */ | |
1748 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1749 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1750 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1751 | /* Same thing, but with leading nop for alignment. */ | |
1752 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1753 | }; | |
1754 | ||
1755 | long | |
c842b53a ILT |
1756 | m32r_relax_frag (segment, fragP, stretch) |
1757 | segT segment; | |
ab3e48dc KH |
1758 | fragS *fragP; |
1759 | long stretch; | |
252b5132 RH |
1760 | { |
1761 | /* Address of branch insn. */ | |
1762 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1763 | long growth = 0; | |
1764 | ||
1765 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1766 | if (fragP->fr_subtype == 2) | |
1767 | { | |
1768 | if ((address & 3) != 0) | |
1769 | { | |
1770 | fragP->fr_subtype = 3; | |
1771 | growth = 2; | |
1772 | } | |
1773 | } | |
1774 | else if (fragP->fr_subtype == 3) | |
1775 | { | |
1776 | if ((address & 3) == 0) | |
1777 | { | |
1778 | fragP->fr_subtype = 2; | |
1779 | growth = -2; | |
1780 | } | |
1781 | } | |
1782 | else | |
1783 | { | |
c842b53a | 1784 | growth = relax_frag (segment, fragP, stretch); |
252b5132 RH |
1785 | |
1786 | /* Long jump on odd halfword boundary? */ | |
1787 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1788 | { | |
1789 | fragP->fr_subtype = 3; | |
1790 | growth += 2; | |
1791 | } | |
1792 | } | |
1793 | ||
1794 | return growth; | |
1795 | } | |
1796 | ||
1797 | /* Return an initial guess of the length by which a fragment must grow to | |
1798 | hold a branch to reach its destination. | |
1799 | Also updates fr_type/fr_subtype as necessary. | |
1800 | ||
1801 | Called just before doing relaxation. | |
1802 | Any symbol that is now undefined will not become defined. | |
1803 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1804 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
ab3e48dc KH |
1805 | Although it may not be explicit in the frag, pretend fr_var starts |
1806 | with a 0 value. */ | |
252b5132 RH |
1807 | |
1808 | int | |
1809 | md_estimate_size_before_relax (fragP, segment) | |
ab3e48dc KH |
1810 | fragS *fragP; |
1811 | segT segment; | |
252b5132 | 1812 | { |
252b5132 RH |
1813 | /* The only thing we have to handle here are symbols outside of the |
1814 | current segment. They may be undefined or in a different segment in | |
1815 | which case linker scripts may place them anywhere. | |
1816 | However, we can't finish the fragment here and emit the reloc as insn | |
1817 | alignment requirements may move the insn about. */ | |
1818 | ||
6edf0760 NC |
1819 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
1820 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1821 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1822 | { |
78a0c6fb | 1823 | #if 0 |
606ab118 | 1824 | int old_fr_fix = fragP->fr_fix; |
78a0c6fb | 1825 | #endif |
606ab118 | 1826 | |
252b5132 RH |
1827 | /* The symbol is undefined in this segment. |
1828 | Change the relaxation subtype to the max allowable and leave | |
1829 | all further handling to md_convert_frag. */ | |
1830 | fragP->fr_subtype = 2; | |
1831 | ||
ab3e48dc KH |
1832 | #if 0 |
1833 | /* Can't use this, but leave in for illustration. */ | |
252b5132 RH |
1834 | /* Change 16 bit insn to 32 bit insn. */ |
1835 | fragP->fr_opcode[0] |= 0x80; | |
1836 | ||
1837 | /* Increase known (fixed) size of fragment. */ | |
1838 | fragP->fr_fix += 2; | |
1839 | ||
1840 | /* Create a relocation for it. */ | |
1841 | fix_new (fragP, old_fr_fix, 4, | |
1842 | fragP->fr_symbol, | |
ab3e48dc | 1843 | fragP->fr_offset, 1 /* pcrel */, |
252b5132 RH |
1844 | /* FIXME: Can't use a real BFD reloc here. |
1845 | gas_cgen_md_apply_fix3 can't handle it. */ | |
1846 | BFD_RELOC_M32R_26_PCREL); | |
1847 | ||
1848 | /* Mark this fragment as finished. */ | |
1849 | frag_wane (fragP); | |
606ab118 | 1850 | return fragP->fr_fix - old_fr_fix; |
252b5132 RH |
1851 | #else |
1852 | { | |
ab3e48dc KH |
1853 | const CGEN_INSN *insn; |
1854 | int i; | |
252b5132 RH |
1855 | |
1856 | /* Update the recorded insn. | |
1857 | Fortunately we don't have to look very far. | |
1858 | FIXME: Change this to record in the instruction the next higher | |
1859 | relaxable insn to use. */ | |
1860 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1861 | { | |
1862 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), | |
1863 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
1864 | == 0) | |
b11dcf4e | 1865 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) |
252b5132 RH |
1866 | break; |
1867 | } | |
1868 | if (i == 4) | |
1869 | abort (); | |
1870 | ||
1871 | fragP->fr_cgen.insn = insn; | |
1872 | return 2; | |
1873 | } | |
1874 | #endif | |
1875 | } | |
1876 | ||
606ab118 | 1877 | return md_relax_table[fragP->fr_subtype].rlx_length; |
ab3e48dc | 1878 | } |
252b5132 | 1879 | |
ab3e48dc | 1880 | /* *FRAGP has been relaxed to its final size, and now needs to have |
252b5132 RH |
1881 | the bytes inside it modified to conform to the new size. |
1882 | ||
1883 | Called after relaxation is finished. | |
1884 | fragP->fr_type == rs_machine_dependent. | |
1885 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1886 | ||
1887 | void | |
1888 | md_convert_frag (abfd, sec, fragP) | |
78a0c6fb | 1889 | bfd *abfd ATTRIBUTE_UNUSED; |
ab3e48dc KH |
1890 | segT sec; |
1891 | fragS *fragP; | |
252b5132 | 1892 | { |
ab3e48dc KH |
1893 | char *opcode; |
1894 | char *displacement; | |
1895 | int target_address; | |
1896 | int opcode_address; | |
1897 | int extension; | |
1898 | int addend; | |
252b5132 RH |
1899 | |
1900 | opcode = fragP->fr_opcode; | |
1901 | ||
1902 | /* Address opcode resides at in file space. */ | |
1903 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1904 | ||
1905 | switch (fragP->fr_subtype) | |
1906 | { | |
ab3e48dc | 1907 | case 1: |
252b5132 | 1908 | extension = 0; |
ab3e48dc | 1909 | displacement = &opcode[1]; |
252b5132 | 1910 | break; |
ab3e48dc | 1911 | case 2: |
252b5132 RH |
1912 | opcode[0] |= 0x80; |
1913 | extension = 2; | |
ab3e48dc | 1914 | displacement = &opcode[1]; |
252b5132 | 1915 | break; |
ab3e48dc | 1916 | case 3: |
252b5132 RH |
1917 | opcode[2] = opcode[0] | 0x80; |
1918 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1919 | opcode_address += 2; | |
1920 | extension = 4; | |
ab3e48dc | 1921 | displacement = &opcode[3]; |
252b5132 | 1922 | break; |
ab3e48dc | 1923 | default: |
252b5132 RH |
1924 | abort (); |
1925 | } | |
1926 | ||
6edf0760 NC |
1927 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
1928 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1929 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1930 | { |
ab3e48dc | 1931 | /* Symbol must be resolved by linker. */ |
252b5132 RH |
1932 | if (fragP->fr_offset & 3) |
1933 | as_warn (_("Addend to unresolved symbol not on word boundary.")); | |
6edf0760 NC |
1934 | #ifdef USE_M32R_OLD_RELOC |
1935 | addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */ | |
1936 | #else | |
1937 | addend = 0; | |
1938 | #endif | |
252b5132 RH |
1939 | } |
1940 | else | |
1941 | { | |
1942 | /* Address we want to reach in file space. */ | |
1943 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
252b5132 RH |
1944 | addend = (target_address - (opcode_address & -4)) >> 2; |
1945 | } | |
1946 | ||
1947 | /* Create a relocation for symbols that must be resolved by the linker. | |
1948 | Otherwise output the completed insn. */ | |
1949 | ||
6edf0760 NC |
1950 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
1951 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1952 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1953 | { |
097f809a NC |
1954 | fixS *fixP; |
1955 | ||
252b5132 RH |
1956 | assert (fragP->fr_subtype != 1); |
1957 | assert (fragP->fr_cgen.insn != 0); | |
097f809a NC |
1958 | |
1959 | fixP = gas_cgen_record_fixup (fragP, | |
1960 | /* Offset of branch insn in frag. */ | |
1961 | fragP->fr_fix + extension - 4, | |
1962 | fragP->fr_cgen.insn, | |
1963 | 4 /* Length. */, | |
1964 | /* FIXME: quick hack. */ | |
252b5132 | 1965 | #if 0 |
097f809a NC |
1966 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
1967 | fragP->fr_cgen.opindex), | |
252b5132 | 1968 | #else |
097f809a NC |
1969 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
1970 | M32R_OPERAND_DISP24), | |
252b5132 | 1971 | #endif |
097f809a NC |
1972 | fragP->fr_cgen.opinfo, |
1973 | fragP->fr_symbol, fragP->fr_offset); | |
1974 | if (fragP->fr_cgen.opinfo) | |
1975 | fixP->fx_r_type = fragP->fr_cgen.opinfo; | |
252b5132 RH |
1976 | } |
1977 | ||
1978 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1979 | ||
1980 | md_number_to_chars (displacement, (valueT) addend, | |
1981 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1982 | ||
1983 | fragP->fr_fix += extension; | |
1984 | } | |
1985 | \f | |
1986 | /* Functions concerning relocs. */ | |
1987 | ||
1988 | /* The location from which a PC relative jump should be calculated, | |
1989 | given a PC relative reloc. */ | |
1990 | ||
1991 | long | |
1992 | md_pcrel_from_section (fixP, sec) | |
ab3e48dc KH |
1993 | fixS *fixP; |
1994 | segT sec; | |
252b5132 RH |
1995 | { |
1996 | if (fixP->fx_addsy != (symbolS *) NULL | |
1997 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
6edf0760 NC |
1998 | || S_GET_SEGMENT (fixP->fx_addsy) != sec |
1999 | || S_IS_EXTERNAL (fixP->fx_addsy) | |
2000 | || S_IS_WEAK (fixP->fx_addsy))) | |
252b5132 RH |
2001 | { |
2002 | /* The symbol is undefined (or is defined but not in this section). | |
2003 | Let the linker figure it out. */ | |
2004 | return 0; | |
2005 | } | |
2006 | ||
2007 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
2008 | } | |
2009 | ||
2010 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
2011 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
2012 | *FIXP may be modified if desired. */ | |
2013 | ||
2014 | bfd_reloc_code_real_type | |
2015 | md_cgen_lookup_reloc (insn, operand, fixP) | |
78a0c6fb | 2016 | const CGEN_INSN *insn ATTRIBUTE_UNUSED; |
ab3e48dc KH |
2017 | const CGEN_OPERAND *operand; |
2018 | fixS *fixP; | |
252b5132 RH |
2019 | { |
2020 | switch (operand->type) | |
2021 | { | |
ab3e48dc KH |
2022 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
2023 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; | |
2024 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; | |
2025 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; | |
2026 | case M32R_OPERAND_HI16: | |
2027 | case M32R_OPERAND_SLO16: | |
2028 | case M32R_OPERAND_ULO16: | |
252b5132 RH |
2029 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
2030 | if (fixP->fx_cgen.opinfo != 0) | |
2031 | return fixP->fx_cgen.opinfo; | |
2032 | break; | |
ab3e48dc KH |
2033 | default: |
2034 | /* Avoid -Wall warning. */ | |
252b5132 RH |
2035 | break; |
2036 | } | |
2037 | return BFD_RELOC_NONE; | |
2038 | } | |
2039 | ||
2040 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ | |
2041 | ||
78a0c6fb AM |
2042 | static void m32r_record_hi16 PARAMS ((int, fixS *, segT)); |
2043 | ||
252b5132 RH |
2044 | static void |
2045 | m32r_record_hi16 (reloc_type, fixP, seg) | |
ab3e48dc KH |
2046 | int reloc_type; |
2047 | fixS *fixP; | |
78a0c6fb | 2048 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 2049 | { |
ab3e48dc | 2050 | struct m32r_hi_fixup *hi_fixup; |
252b5132 RH |
2051 | |
2052 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
2053 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
2054 | ||
2055 | hi_fixup = ((struct m32r_hi_fixup *) | |
2056 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
2057 | hi_fixup->fixp = fixP; | |
2058 | hi_fixup->seg = now_seg; | |
2059 | hi_fixup->next = m32r_hi_fixup_list; | |
ab3e48dc | 2060 | |
252b5132 RH |
2061 | m32r_hi_fixup_list = hi_fixup; |
2062 | } | |
2063 | ||
2064 | /* Called while parsing an instruction to create a fixup. | |
2065 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
2066 | ||
2067 | fixS * | |
2068 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ab3e48dc KH |
2069 | fragS *frag; |
2070 | int where; | |
2071 | const CGEN_INSN *insn; | |
2072 | int length; | |
2073 | const CGEN_OPERAND *operand; | |
2074 | int opinfo; | |
2075 | expressionS *exp; | |
252b5132 | 2076 | { |
097f809a NC |
2077 | fixS *fixP; |
2078 | bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED; | |
2079 | ||
2080 | if (m32r_check_fixup (exp, &r_type)) | |
2081 | as_bad (_("Invalid PIC expression.")); | |
2082 | ||
2083 | fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, | |
2084 | operand, opinfo, exp); | |
252b5132 RH |
2085 | |
2086 | switch (operand->type) | |
2087 | { | |
ab3e48dc | 2088 | case M32R_OPERAND_HI16: |
252b5132 RH |
2089 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
2090 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO | |
2091 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
2092 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); | |
2093 | break; | |
097f809a | 2094 | |
ab3e48dc | 2095 | default: |
097f809a | 2096 | /* Avoid -Wall warning. */ |
252b5132 RH |
2097 | break; |
2098 | } | |
2099 | ||
097f809a NC |
2100 | switch (r_type) |
2101 | { | |
2102 | case BFD_RELOC_UNUSED: | |
2103 | default: | |
2104 | return fixP; | |
2105 | ||
2106 | case BFD_RELOC_M32R_GOTPC24: | |
2107 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
2108 | r_type = BFD_RELOC_M32R_GOTPC_HI_SLO; | |
2109 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
2110 | r_type = BFD_RELOC_M32R_GOTPC_HI_ULO; | |
2111 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
2112 | r_type = BFD_RELOC_M32R_GOTPC_LO; | |
2113 | break; | |
2114 | case BFD_RELOC_M32R_GOT24: | |
2115 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
2116 | r_type = BFD_RELOC_M32R_GOT16_HI_SLO; | |
2117 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
2118 | r_type = BFD_RELOC_M32R_GOT16_HI_ULO; | |
2119 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
2120 | r_type = BFD_RELOC_M32R_GOT16_LO; | |
2121 | break; | |
2122 | case BFD_RELOC_M32R_GOTOFF: | |
2123 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
2124 | r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO; | |
2125 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
2126 | r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO; | |
2127 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
2128 | r_type = BFD_RELOC_M32R_GOTOFF_LO; | |
2129 | break; | |
2130 | case BFD_RELOC_M32R_26_PLTREL: | |
2131 | as_bad (_("Invalid PIC expression.")); | |
2132 | break; | |
2133 | } | |
2134 | ||
2135 | fixP->fx_r_type = r_type; | |
2136 | ||
252b5132 RH |
2137 | return fixP; |
2138 | } | |
2139 | ||
2140 | /* Return BFD reloc type from opinfo field in a fixS. | |
2141 | It's tricky using fx_r_type in m32r_frob_file because the values | |
2142 | are BFD_RELOC_UNUSED + operand number. */ | |
2143 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) | |
2144 | ||
2145 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
94f592af | 2146 | the corresponding LO16 reloc. This is called before md_apply_fix3 and |
252b5132 RH |
2147 | tc_gen_reloc. */ |
2148 | ||
2149 | void | |
2150 | m32r_frob_file () | |
2151 | { | |
ab3e48dc | 2152 | struct m32r_hi_fixup *l; |
252b5132 RH |
2153 | |
2154 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
2155 | { | |
ab3e48dc KH |
2156 | segment_info_type *seginfo; |
2157 | int pass; | |
252b5132 RH |
2158 | |
2159 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
2160 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
2161 | ||
2162 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
2163 | if (l->fixp->fx_next != NULL | |
2164 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
2165 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
2166 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
2167 | continue; | |
2168 | ||
2169 | /* Look through the fixups for this segment for a matching `low'. | |
2170 | When we find one, move the high/shigh just in front of it. We do | |
2171 | this in two passes. In the first pass, we try to find a | |
2172 | unique `low'. In the second pass, we permit multiple high's | |
2173 | relocs for a single `low'. */ | |
2174 | seginfo = seg_info (l->seg); | |
2175 | for (pass = 0; pass < 2; pass++) | |
2176 | { | |
ab3e48dc KH |
2177 | fixS *f; |
2178 | fixS *prev; | |
252b5132 RH |
2179 | |
2180 | prev = NULL; | |
2181 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
2182 | { | |
2183 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
2184 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
2185 | && f->fx_addsy == l->fixp->fx_addsy | |
2186 | && f->fx_offset == l->fixp->fx_offset | |
2187 | && (pass == 1 | |
2188 | || prev == NULL | |
2189 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
2190 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
2191 | || prev->fx_addsy != f->fx_addsy | |
ab3e48dc | 2192 | || prev->fx_offset != f->fx_offset)) |
252b5132 | 2193 | { |
ab3e48dc | 2194 | fixS **pf; |
252b5132 RH |
2195 | |
2196 | /* Move l->fixp before f. */ | |
2197 | for (pf = &seginfo->fix_root; | |
ab3e48dc KH |
2198 | *pf != l->fixp; |
2199 | pf = & (*pf)->fx_next) | |
2200 | assert (*pf != NULL); | |
252b5132 | 2201 | |
ab3e48dc | 2202 | *pf = l->fixp->fx_next; |
252b5132 RH |
2203 | |
2204 | l->fixp->fx_next = f; | |
2205 | if (prev == NULL) | |
2206 | seginfo->fix_root = l->fixp; | |
2207 | else | |
2208 | prev->fx_next = l->fixp; | |
2209 | ||
2210 | break; | |
2211 | } | |
2212 | ||
2213 | prev = f; | |
2214 | } | |
2215 | ||
2216 | if (f != NULL) | |
2217 | break; | |
2218 | ||
2219 | if (pass == 1 | |
2220 | && warn_unmatched_high) | |
2221 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
2222 | _("Unmatched high/shigh reloc")); | |
2223 | } | |
2224 | } | |
2225 | } | |
2226 | ||
2227 | /* See whether we need to force a relocation into the output file. | |
2228 | This is used to force out switch and PC relative relocations when | |
2229 | relaxing. */ | |
2230 | ||
2231 | int | |
2232 | m32r_force_relocation (fix) | |
ab3e48dc | 2233 | fixS *fix; |
252b5132 | 2234 | { |
ae6063d4 | 2235 | if (generic_force_reloc (fix)) |
252b5132 RH |
2236 | return 1; |
2237 | ||
2238 | if (! m32r_relax) | |
2239 | return 0; | |
2240 | ||
ab3e48dc | 2241 | return fix->fx_pcrel; |
252b5132 RH |
2242 | } |
2243 | \f | |
2244 | /* Write a value out to the object file, using the appropriate endianness. */ | |
2245 | ||
2246 | void | |
2247 | md_number_to_chars (buf, val, n) | |
ab3e48dc | 2248 | char *buf; |
252b5132 | 2249 | valueT val; |
ab3e48dc | 2250 | int n; |
252b5132 RH |
2251 | { |
2252 | if (target_big_endian) | |
2253 | number_to_chars_bigendian (buf, val, n); | |
2254 | else | |
2255 | number_to_chars_littleendian (buf, val, n); | |
2256 | } | |
2257 | ||
ab3e48dc KH |
2258 | /* Turn a string in input_line_pointer into a floating point constant |
2259 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
2260 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
2261 | returned, or NULL on OK. */ | |
252b5132 | 2262 | |
ab3e48dc | 2263 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
2264 | #define MAX_LITTLENUMS 6 |
2265 | ||
2266 | char * | |
2267 | md_atof (type, litP, sizeP) | |
2268 | char type; | |
2269 | char *litP; | |
2270 | int *sizeP; | |
2271 | { | |
ab3e48dc KH |
2272 | int i; |
2273 | int prec; | |
2274 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2275 | char *t; | |
252b5132 RH |
2276 | |
2277 | switch (type) | |
2278 | { | |
2279 | case 'f': | |
2280 | case 'F': | |
2281 | case 's': | |
2282 | case 'S': | |
2283 | prec = 2; | |
2284 | break; | |
2285 | ||
2286 | case 'd': | |
2287 | case 'D': | |
2288 | case 'r': | |
2289 | case 'R': | |
2290 | prec = 4; | |
2291 | break; | |
2292 | ||
ab3e48dc KH |
2293 | /* FIXME: Some targets allow other format chars for bigger sizes |
2294 | here. */ | |
252b5132 RH |
2295 | |
2296 | default: | |
ab3e48dc | 2297 | *sizeP = 0; |
252b5132 RH |
2298 | return _("Bad call to md_atof()"); |
2299 | } | |
2300 | ||
2301 | t = atof_ieee (input_line_pointer, type, words); | |
2302 | if (t) | |
2303 | input_line_pointer = t; | |
ab3e48dc | 2304 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
252b5132 RH |
2305 | |
2306 | if (target_big_endian) | |
2307 | { | |
2308 | for (i = 0; i < prec; i++) | |
2309 | { | |
2310 | md_number_to_chars (litP, (valueT) words[i], | |
2311 | sizeof (LITTLENUM_TYPE)); | |
2312 | litP += sizeof (LITTLENUM_TYPE); | |
2313 | } | |
2314 | } | |
2315 | else | |
2316 | { | |
2317 | for (i = prec - 1; i >= 0; i--) | |
2318 | { | |
2319 | md_number_to_chars (litP, (valueT) words[i], | |
2320 | sizeof (LITTLENUM_TYPE)); | |
2321 | litP += sizeof (LITTLENUM_TYPE); | |
2322 | } | |
2323 | } | |
ab3e48dc | 2324 | |
252b5132 RH |
2325 | return 0; |
2326 | } | |
2327 | ||
2328 | void | |
2329 | m32r_elf_section_change_hook () | |
2330 | { | |
2331 | /* If we have reached the end of a section and we have just emitted a | |
2332 | 16 bit insn, then emit a nop to make sure that the section ends on | |
2333 | a 32 bit boundary. */ | |
ab3e48dc | 2334 | |
252b5132 RH |
2335 | if (prev_insn.insn || seen_relaxable_p) |
2336 | (void) m32r_fill_insn (0); | |
2337 | } | |
2338 | ||
60bcf0fa | 2339 | /* Return true if can adjust the reloc to be relative to its section |
ab3e48dc | 2340 | (such as .data) instead of relative to some symbol. */ |
60bcf0fa | 2341 | |
b34976b6 | 2342 | bfd_boolean |
252b5132 RH |
2343 | m32r_fix_adjustable (fixP) |
2344 | fixS *fixP; | |
2345 | { | |
5c86cbc7 | 2346 | bfd_reloc_code_real_type reloc_type; |
ab3e48dc | 2347 | |
5c86cbc7 CM |
2348 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
2349 | { | |
2350 | const CGEN_INSN *insn = NULL; | |
2351 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; | |
ab3e48dc KH |
2352 | const CGEN_OPERAND *operand = |
2353 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); | |
5c86cbc7 CM |
2354 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
2355 | } | |
2356 | else | |
2357 | reloc_type = fixP->fx_r_type; | |
2358 | ||
6edf0760 NC |
2359 | if (fixP->fx_addsy == NULL) |
2360 | return 1; | |
2361 | ||
2362 | /* Prevent all adjustments to global symbols. */ | |
2363 | if (S_IS_EXTERN (fixP->fx_addsy)) | |
2364 | return 0; | |
2365 | if (S_IS_WEAK (fixP->fx_addsy)) | |
2366 | return 0; | |
2367 | ||
2368 | if (pic_code | |
2369 | && (reloc_type == BFD_RELOC_M32R_24 | |
2370 | || reloc_type == BFD_RELOC_M32R_26_PCREL | |
2371 | || reloc_type == BFD_RELOC_M32R_HI16_SLO | |
2372 | || reloc_type == BFD_RELOC_M32R_HI16_ULO | |
2373 | || reloc_type == BFD_RELOC_M32R_LO16)) | |
2374 | return 0; | |
2375 | ||
097f809a NC |
2376 | if (reloc_type == BFD_RELOC_M32R_GOT24 |
2377 | || reloc_type == BFD_RELOC_M32R_26_PLTREL | |
2378 | || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO | |
2379 | || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO | |
2380 | || reloc_type == BFD_RELOC_M32R_GOTPC_LO | |
2381 | || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO | |
2382 | || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO | |
2383 | || reloc_type == BFD_RELOC_M32R_GOT16_LO) | |
2384 | return 0; | |
2385 | ||
ab3e48dc | 2386 | /* We need the symbol name for the VTABLE entries. */ |
5c86cbc7 CM |
2387 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
2388 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
2389 | return 0; |
2390 | ||
2391 | return 1; | |
2392 | } | |
88845958 NC |
2393 | |
2394 | void | |
097f809a | 2395 | m32r_elf_final_processing (void) |
88845958 NC |
2396 | { |
2397 | if (use_parallel) | |
2398 | m32r_flags |= E_M32R_HAS_PARALLEL; | |
2399 | elf_elfheader (stdoutput)->e_flags |= m32r_flags; | |
2400 | } | |
6edf0760 | 2401 | |
6edf0760 NC |
2402 | /* Translate internal representation of relocation info to BFD target |
2403 | format. */ | |
097f809a | 2404 | |
6edf0760 NC |
2405 | arelent * |
2406 | tc_gen_reloc (section, fixP) | |
2407 | asection * section; | |
2408 | fixS * fixP; | |
2409 | { | |
2410 | arelent * reloc; | |
2411 | bfd_reloc_code_real_type code; | |
2412 | ||
2413 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
2414 | ||
2415 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2416 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
2417 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
2418 | ||
2419 | code = fixP->fx_r_type; | |
2420 | if (pic_code) | |
2421 | { | |
2422 | #ifdef DEBUG_PIC | |
2423 | printf("%s",bfd_get_reloc_code_name(code)); | |
2424 | #endif | |
2425 | switch (code) | |
2426 | { | |
2427 | case BFD_RELOC_M32R_26_PCREL: | |
2428 | code = BFD_RELOC_M32R_26_PLTREL; | |
2429 | break; | |
2430 | case BFD_RELOC_M32R_24: | |
2431 | if (fixP->fx_addsy != NULL | |
2432 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2433 | code = BFD_RELOC_M32R_GOTPC24; | |
2434 | else | |
2435 | code = BFD_RELOC_M32R_GOT24; | |
2436 | break; | |
2437 | case BFD_RELOC_M32R_HI16_ULO: | |
2438 | if (fixP->fx_addsy != NULL | |
2439 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2440 | code = BFD_RELOC_M32R_GOTPC_HI_ULO; | |
2441 | else | |
2442 | code = BFD_RELOC_M32R_GOT16_HI_ULO; | |
2443 | break; | |
2444 | case BFD_RELOC_M32R_HI16_SLO: | |
2445 | if (fixP->fx_addsy != NULL | |
2446 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2447 | code = BFD_RELOC_M32R_GOTPC_HI_SLO; | |
2448 | else | |
2449 | code = BFD_RELOC_M32R_GOT16_HI_SLO; | |
2450 | break; | |
2451 | case BFD_RELOC_M32R_LO16: | |
2452 | if (fixP->fx_addsy != NULL | |
2453 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2454 | code = BFD_RELOC_M32R_GOTPC_LO; | |
2455 | else | |
2456 | code = BFD_RELOC_M32R_GOT16_LO; | |
2457 | break; | |
2458 | default: | |
2459 | break; | |
2460 | } | |
2461 | #ifdef DEBUG_PIC | |
2462 | printf(" => %s",bfd_get_reloc_code_name(code)); | |
2463 | #endif | |
2464 | } | |
2465 | ||
2466 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
2467 | #ifdef DEBUG_PIC | |
2468 | printf(" => %s\n",reloc->howto->name); | |
2469 | #endif | |
2470 | if (reloc->howto == (reloc_howto_type *) NULL) | |
2471 | { | |
2472 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2473 | _("internal error: can't export reloc type %d (`%s')"), | |
2474 | fixP->fx_r_type, bfd_get_reloc_code_name (code)); | |
2475 | return NULL; | |
2476 | } | |
2477 | ||
097f809a | 2478 | /* Use fx_offset for these cases. */ |
6edf0760 NC |
2479 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
2480 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT) | |
2481 | reloc->addend = fixP->fx_offset; | |
097f809a NC |
2482 | else if ((!pic_code |
2483 | && code != BFD_RELOC_M32R_26_PLTREL) | |
6edf0760 NC |
2484 | && fixP->fx_pcrel |
2485 | && fixP->fx_addsy != NULL | |
2486 | && (S_GET_SEGMENT(fixP->fx_addsy) != section) | |
2487 | && S_IS_DEFINED (fixP->fx_addsy) | |
2488 | && ! S_IS_EXTERNAL(fixP->fx_addsy) | |
2489 | && ! S_IS_WEAK(fixP->fx_addsy)) | |
097f809a | 2490 | /* Already used fx_offset in the opcode field itseld. */ |
6edf0760 NC |
2491 | reloc->addend = 0; |
2492 | else | |
2493 | reloc->addend = fixP->fx_addnumber; | |
2494 | ||
2495 | return reloc; | |
2496 | } | |
097f809a NC |
2497 | |
2498 | inline static char * | |
2499 | m32r_end_of_match (char *cont, char *what) | |
2500 | { | |
2501 | int len = strlen (what); | |
2502 | ||
2503 | if (strncasecmp (cont, what, strlen (what)) == 0 | |
2504 | && ! is_part_of_name (cont[len])) | |
2505 | return cont + len; | |
2506 | ||
2507 | return NULL; | |
2508 | } | |
2509 | ||
2510 | int | |
2511 | m32r_parse_name (char const *name, expressionS *exprP, char *nextcharP) | |
2512 | { | |
2513 | char *next = input_line_pointer; | |
2514 | char *next_end; | |
2515 | int reloc_type; | |
2516 | operatorT op_type; | |
2517 | segT segment; | |
2518 | ||
2519 | exprP->X_op_symbol = NULL; | |
2520 | exprP->X_md = BFD_RELOC_UNUSED; | |
2521 | ||
2522 | if (strcmp (name, GOT_NAME) == 0) | |
2523 | { | |
2524 | if (! GOT_symbol) | |
2525 | GOT_symbol = symbol_find_or_make (name); | |
2526 | ||
2527 | exprP->X_add_symbol = GOT_symbol; | |
2528 | no_suffix: | |
2529 | /* If we have an absolute symbol or a | |
2530 | reg, then we know its value now. */ | |
2531 | segment = S_GET_SEGMENT (exprP->X_add_symbol); | |
2532 | if (segment == absolute_section) | |
2533 | { | |
2534 | exprP->X_op = O_constant; | |
2535 | exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); | |
2536 | exprP->X_add_symbol = NULL; | |
2537 | } | |
2538 | else if (segment == reg_section) | |
2539 | { | |
2540 | exprP->X_op = O_register; | |
2541 | exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); | |
2542 | exprP->X_add_symbol = NULL; | |
2543 | } | |
2544 | else | |
2545 | { | |
2546 | exprP->X_op = O_symbol; | |
2547 | exprP->X_add_number = 0; | |
2548 | } | |
2549 | ||
2550 | return 1; | |
2551 | } | |
2552 | ||
2553 | exprP->X_add_symbol = symbol_find_or_make (name); | |
2554 | ||
2555 | if (*nextcharP != '@') | |
2556 | goto no_suffix; | |
2557 | else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF"))) | |
2558 | { | |
2559 | reloc_type = BFD_RELOC_M32R_GOTOFF; | |
2560 | op_type = O_PIC_reloc; | |
2561 | } | |
2562 | else if ((next_end = m32r_end_of_match (next + 1, "GOT"))) | |
2563 | { | |
2564 | reloc_type = BFD_RELOC_M32R_GOT24; | |
2565 | op_type = O_PIC_reloc; | |
2566 | } | |
2567 | else if ((next_end = m32r_end_of_match (next + 1, "PLT"))) | |
2568 | { | |
2569 | reloc_type = BFD_RELOC_M32R_26_PLTREL; | |
2570 | op_type = O_PIC_reloc; | |
2571 | } | |
2572 | else | |
2573 | goto no_suffix; | |
2574 | ||
2575 | *input_line_pointer = *nextcharP; | |
2576 | input_line_pointer = next_end; | |
2577 | *nextcharP = *input_line_pointer; | |
2578 | *input_line_pointer = '\0'; | |
2579 | ||
2580 | exprP->X_op = op_type; | |
2581 | exprP->X_add_number = 0; | |
2582 | exprP->X_md = reloc_type; | |
2583 | ||
2584 | return 1; | |
2585 | } | |
2586 | ||
2587 | int | |
2588 | m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp) | |
2589 | { | |
2590 | if (exp->X_op == O_PIC_reloc | |
2591 | && exp->X_md == BFD_RELOC_M32R_26_PLTREL) | |
2592 | { | |
2593 | exp->X_op = O_symbol; | |
2594 | opinfo = exp->X_md; | |
2595 | } | |
2596 | ||
2597 | return opinfo; | |
2598 | } |