Commit | Line | Data |
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252b5132 | 1 | /* tc-m32r.c -- Assembler for the Mitsubishi M32R. |
a161fe53 | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
ab3e48dc | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
ab3e48dc | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "symcat.h" |
27 | #include "opcodes/m32r-desc.h" | |
28 | #include "opcodes/m32r-opc.h" | |
29 | #include "cgen.h" | |
30 | ||
31 | /* Linked list of symbols that are debugging symbols to be defined as the | |
32 | beginning of the current instruction. */ | |
33 | typedef struct sym_link | |
34 | { | |
35 | struct sym_link *next; | |
ab3e48dc | 36 | symbolS *symbol; |
252b5132 RH |
37 | } sym_linkS; |
38 | ||
ab3e48dc KH |
39 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
40 | ||
252b5132 RH |
41 | /* Structure to hold all of the different components describing |
42 | an individual instruction. */ | |
43 | typedef struct | |
44 | { | |
ab3e48dc KH |
45 | const CGEN_INSN *insn; |
46 | const CGEN_INSN *orig_insn; | |
47 | CGEN_FIELDS fields; | |
252b5132 | 48 | #if CGEN_INT_INSN_P |
ab3e48dc | 49 | CGEN_INSN_INT buffer[1]; |
252b5132 RH |
50 | #define INSN_VALUE(buf) (*(buf)) |
51 | #else | |
ab3e48dc | 52 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
252b5132 RH |
53 | #define INSN_VALUE(buf) (buf) |
54 | #endif | |
ab3e48dc KH |
55 | char *addr; |
56 | fragS *frag; | |
57 | int num_fixups; | |
58 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; | |
59 | int indices[MAX_OPERAND_INSTANCES]; | |
60 | sym_linkS *debug_sym_link; | |
252b5132 RH |
61 | } |
62 | m32r_insn; | |
63 | ||
64 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
65 | boundary (i.e. was the first of two 16 bit insns). */ | |
ab3e48dc | 66 | static m32r_insn prev_insn; |
252b5132 RH |
67 | |
68 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
69 | alignment request. */ | |
70 | static int seen_relaxable_p = 0; | |
71 | ||
72 | /* Non-zero if -relax specified, in which case sufficient relocs are output | |
73 | for the linker to do relaxing. | |
74 | We do simple forms of relaxing internally, but they are always done. | |
75 | This flag does not apply to them. */ | |
76 | static int m32r_relax; | |
77 | ||
ab3e48dc KH |
78 | #if 0 |
79 | /* Not supported yet. */ | |
252b5132 RH |
80 | /* If non-NULL, pointer to cpu description file to read. |
81 | This allows runtime additions to the assembler. */ | |
ab3e48dc | 82 | static const char *m32r_cpu_desc; |
252b5132 RH |
83 | #endif |
84 | ||
85 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. | |
86 | Each high/shigh reloc must be paired with it's low cousin in order to | |
87 | properly calculate the addend in a relocatable link (since there is a | |
88 | potential carry from the low to the high/shigh). | |
89 | This option is off by default though for user-written assembler code it | |
90 | might make sense to make the default be on (i.e. have gcc pass a flag | |
91 | to turn it off). This warning must not be on for GCC created code as | |
92 | optimization may delete the low but not the high/shigh (at least we | |
93 | shouldn't assume or require it to). */ | |
94 | static int warn_unmatched_high = 0; | |
95 | ||
925c058e DE |
96 | /* Non-zero if -m32rx has been specified, in which case support for the |
97 | extended M32RX instruction set should be enabled. */ | |
98 | static int enable_m32rx = 0; | |
99 | ||
100 | /* Non-zero if -m32rx -hidden has been specified, in which case support for | |
101 | the special M32RX instruction set should be enabled. */ | |
102 | static int enable_special = 0; | |
103 | ||
104 | /* Non-zero if the programmer should be warned when an explicit parallel | |
105 | instruction might have constraint violations. */ | |
106 | static int warn_explicit_parallel_conflicts = 1; | |
107 | ||
108 | /* Non-zero if insns can be made parallel. */ | |
109 | static int optimize; | |
252b5132 | 110 | |
ab3e48dc | 111 | /* Stuff for .scomm symbols. */ |
252b5132 RH |
112 | static segT sbss_section; |
113 | static asection scom_section; | |
114 | static asymbol scom_symbol; | |
115 | ||
116 | const char comment_chars[] = ";"; | |
117 | const char line_comment_chars[] = "#"; | |
118 | const char line_separator_chars[] = ""; | |
119 | const char EXP_CHARS[] = "eE"; | |
120 | const char FLT_CHARS[] = "dD"; | |
121 | ||
122 | /* Relocations against symbols are done in two | |
123 | parts, with a HI relocation and a LO relocation. Each relocation | |
124 | has only 16 bits of space to store an addend. This means that in | |
125 | order for the linker to handle carries correctly, it must be able | |
126 | to locate both the HI and the LO relocation. This means that the | |
127 | relocations must appear in order in the relocation table. | |
128 | ||
129 | In order to implement this, we keep track of each unmatched HI | |
130 | relocation. We then sort them so that they immediately precede the | |
82efde3a | 131 | corresponding LO relocation. */ |
252b5132 RH |
132 | |
133 | struct m32r_hi_fixup | |
134 | { | |
ab3e48dc KH |
135 | /* Next HI fixup. */ |
136 | struct m32r_hi_fixup *next; | |
137 | ||
138 | /* This fixup. */ | |
139 | fixS *fixp; | |
252b5132 | 140 | |
ab3e48dc KH |
141 | /* The section this fixup is in. */ |
142 | segT seg; | |
252b5132 RH |
143 | }; |
144 | ||
145 | /* The list of unmatched HI relocs. */ | |
146 | ||
ab3e48dc | 147 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
252b5132 | 148 | \f |
925c058e DE |
149 | static void |
150 | allow_m32rx (on) | |
151 | int on; | |
152 | { | |
153 | enable_m32rx = on; | |
154 | ||
155 | if (stdoutput != NULL) | |
156 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, | |
157 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); | |
158 | } | |
252b5132 | 159 | \f |
925c058e | 160 | #define M32R_SHORTOPTS "O" |
ab3e48dc KH |
161 | |
162 | const char *md_shortopts = M32R_SHORTOPTS; | |
252b5132 RH |
163 | |
164 | struct option md_longopts[] = | |
165 | { | |
8ad9e709 NC |
166 | #define OPTION_M32R (OPTION_MD_BASE) |
167 | #define OPTION_M32RX (OPTION_M32R + 1) | |
168 | #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1) | |
169 | #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) | |
170 | #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1) | |
171 | #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1) | |
172 | #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) | |
173 | {"m32r", no_argument, NULL, OPTION_M32R}, | |
925c058e | 174 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
925c058e DE |
175 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
176 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, | |
925c058e DE |
177 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
178 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, | |
925c058e | 179 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
252b5132 | 180 | /* Sigh. I guess all warnings must now have both variants. */ |
2f3519a2 NC |
181 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
182 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, | |
d3388653 NC |
183 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
184 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, | |
252b5132 | 185 | |
ab3e48dc KH |
186 | #if 0 |
187 | /* Not supported yet. */ | |
8ad9e709 NC |
188 | #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1) |
189 | #define OPTION_CPU_DESC (OPTION_RELAX + 1) | |
252b5132 | 190 | {"relax", no_argument, NULL, OPTION_RELAX}, |
252b5132 RH |
191 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
192 | #endif | |
252b5132 RH |
193 | {NULL, no_argument, NULL, 0} |
194 | }; | |
ab3e48dc | 195 | |
252b5132 RH |
196 | size_t md_longopts_size = sizeof (md_longopts); |
197 | ||
198 | int | |
199 | md_parse_option (c, arg) | |
ab3e48dc KH |
200 | int c; |
201 | char *arg; | |
252b5132 RH |
202 | { |
203 | switch (c) | |
204 | { | |
925c058e DE |
205 | case 'O': |
206 | optimize = 1; | |
207 | break; | |
208 | ||
8ad9e709 NC |
209 | case OPTION_M32R: |
210 | allow_m32rx (0); | |
211 | break; | |
ab3e48dc | 212 | |
925c058e DE |
213 | case OPTION_M32RX: |
214 | allow_m32rx (1); | |
215 | break; | |
ab3e48dc | 216 | |
925c058e DE |
217 | case OPTION_WARN_PARALLEL: |
218 | warn_explicit_parallel_conflicts = 1; | |
219 | break; | |
ab3e48dc | 220 | |
925c058e DE |
221 | case OPTION_NO_WARN_PARALLEL: |
222 | warn_explicit_parallel_conflicts = 0; | |
223 | break; | |
224 | ||
225 | case OPTION_SPECIAL: | |
226 | if (enable_m32rx) | |
227 | enable_special = 1; | |
228 | else | |
229 | { | |
230 | /* Pretend that we do not recognise this option. */ | |
231 | as_bad (_("Unrecognised option: -hidden")); | |
232 | return 0; | |
233 | } | |
234 | break; | |
252b5132 RH |
235 | |
236 | case OPTION_WARN_UNMATCHED: | |
237 | warn_unmatched_high = 1; | |
238 | break; | |
239 | ||
240 | case OPTION_NO_WARN_UNMATCHED: | |
241 | warn_unmatched_high = 0; | |
242 | break; | |
ab3e48dc KH |
243 | |
244 | #if 0 | |
245 | /* Not supported yet. */ | |
252b5132 RH |
246 | case OPTION_RELAX: |
247 | m32r_relax = 1; | |
248 | break; | |
249 | case OPTION_CPU_DESC: | |
250 | m32r_cpu_desc = arg; | |
251 | break; | |
252 | #endif | |
253 | ||
254 | default: | |
255 | return 0; | |
256 | } | |
ab3e48dc | 257 | |
252b5132 RH |
258 | return 1; |
259 | } | |
260 | ||
261 | void | |
262 | md_show_usage (stream) | |
ab3e48dc | 263 | FILE *stream; |
252b5132 RH |
264 | { |
265 | fprintf (stream, _(" M32R specific command line options:\n")); | |
266 | ||
ded0aeb7 NC |
267 | fprintf (stream, _("\ |
268 | -m32r disable support for the m32rx instruction set\n")); | |
925c058e DE |
269 | fprintf (stream, _("\ |
270 | -m32rx support the extended m32rx instruction set\n")); | |
271 | fprintf (stream, _("\ | |
272 | -O try to combine instructions in parallel\n")); | |
273 | ||
274 | fprintf (stream, _("\ | |
275 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); | |
276 | fprintf (stream, _("\ | |
277 | violate contraints\n")); | |
278 | fprintf (stream, _("\ | |
279 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); | |
280 | fprintf (stream, _("\ | |
281 | instructions violate contraints\n")); | |
282 | fprintf (stream, _("\ | |
283 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); | |
284 | fprintf (stream, _("\ | |
285 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); | |
252b5132 RH |
286 | |
287 | fprintf (stream, _("\ | |
288 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); | |
289 | fprintf (stream, _("\ | |
290 | -no-warn-unmatched-high do not warn about missing low relocs\n")); | |
291 | fprintf (stream, _("\ | |
292 | -Wuh synonym for -warn-unmatched-high\n")); | |
293 | fprintf (stream, _("\ | |
294 | -Wnuh synonym for -no-warn-unmatched-high\n")); | |
295 | ||
296 | #if 0 | |
297 | fprintf (stream, _("\ | |
298 | -relax create linker relaxable code\n")); | |
299 | fprintf (stream, _("\ | |
300 | -cpu-desc provide runtime cpu description file\n")); | |
301 | #endif | |
ab3e48dc | 302 | } |
252b5132 RH |
303 | |
304 | static void fill_insn PARAMS ((int)); | |
305 | static void m32r_scomm PARAMS ((int)); | |
306 | static void debug_sym PARAMS ((int)); | |
307 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); | |
308 | ||
309 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
310 | static subsegT prev_subseg; | |
311 | static segT prev_seg; | |
312 | ||
313 | /* The target specific pseudo-ops which we support. */ | |
314 | const pseudo_typeS md_pseudo_table[] = | |
315 | { | |
316 | { "word", cons, 4 }, | |
317 | { "fillinsn", fill_insn, 0 }, | |
318 | { "scomm", m32r_scomm, 0 }, | |
319 | { "debugsym", debug_sym, 0 }, | |
ab3e48dc | 320 | /* Not documented as so far there is no need for them.... */ |
925c058e DE |
321 | { "m32r", allow_m32rx, 0 }, |
322 | { "m32rx", allow_m32rx, 1 }, | |
252b5132 RH |
323 | { NULL, NULL, 0 } |
324 | }; | |
325 | ||
326 | /* FIXME: Should be machine generated. */ | |
327 | #define NOP_INSN 0x7000 | |
ab3e48dc | 328 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
252b5132 | 329 | |
0a9ef439 RH |
330 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
331 | of an rs_align_code fragment. */ | |
252b5132 | 332 | |
0a9ef439 RH |
333 | void |
334 | m32r_handle_align (fragp) | |
015c05c1 | 335 | fragS *fragp; |
252b5132 | 336 | { |
0a9ef439 RH |
337 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
338 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; | |
252b5132 | 339 | |
0a9ef439 RH |
340 | int bytes, fix; |
341 | char *p; | |
ab3e48dc | 342 | |
0a9ef439 RH |
343 | if (fragp->fr_type != rs_align_code) |
344 | return; | |
345 | ||
346 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
347 | p = fragp->fr_literal + fragp->fr_fix; | |
348 | fix = 0; | |
349 | ||
350 | if (bytes & 1) | |
351 | { | |
352 | fix = 1; | |
353 | *p++ = 0; | |
354 | bytes--; | |
252b5132 RH |
355 | } |
356 | ||
0a9ef439 RH |
357 | if (bytes & 2) |
358 | { | |
359 | memcpy (p, nop_pattern, 2); | |
360 | p += 2; | |
361 | bytes -= 2; | |
362 | fix += 2; | |
363 | } | |
364 | ||
365 | memcpy (p, multi_nop_pattern, 4); | |
366 | ||
367 | fragp->fr_fix += fix; | |
368 | fragp->fr_var = 4; | |
252b5132 RH |
369 | } |
370 | ||
371 | /* If the last instruction was the first of 2 16 bit insns, | |
372 | output a nop to move the PC to a 32 bit boundary. | |
373 | ||
374 | This is done via an alignment specification since branch relaxing | |
375 | may make it unnecessary. | |
376 | ||
377 | Internally, we need to output one of these each time a 32 bit insn is | |
378 | seen after an insn that is relaxable. */ | |
379 | ||
380 | static void | |
381 | fill_insn (ignore) | |
382 | int ignore; | |
383 | { | |
0a9ef439 | 384 | frag_align_code (2, 0); |
252b5132 RH |
385 | prev_insn.insn = NULL; |
386 | seen_relaxable_p = 0; | |
387 | } | |
388 | ||
389 | /* Record the symbol so that when we output the insn, we can create | |
390 | a symbol that is at the start of the instruction. This is used | |
391 | to emit the label for the start of a breakpoint without causing | |
392 | the assembler to emit a NOP if the previous instruction was a | |
393 | 16 bit instruction. */ | |
394 | ||
395 | static void | |
396 | debug_sym (ignore) | |
397 | int ignore; | |
398 | { | |
399 | register char *name; | |
400 | register char delim; | |
401 | register char *end_name; | |
402 | register symbolS *symbolP; | |
403 | register sym_linkS *link; | |
404 | ||
405 | name = input_line_pointer; | |
406 | delim = get_symbol_end (); | |
407 | end_name = input_line_pointer; | |
ab3e48dc | 408 | |
252b5132 RH |
409 | if ((symbolP = symbol_find (name)) == NULL |
410 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
411 | { | |
412 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
413 | } | |
414 | ||
415 | symbol_table_insert (symbolP); | |
416 | if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section) | |
417 | /* xgettext:c-format */ | |
418 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
419 | ||
420 | else | |
421 | { | |
422 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); | |
423 | link->symbol = symbolP; | |
424 | link->next = debug_sym_link; | |
425 | debug_sym_link = link; | |
f412ead8 | 426 | symbol_get_obj (symbolP)->local = 1; |
252b5132 RH |
427 | } |
428 | ||
429 | *end_name = delim; | |
430 | demand_empty_rest_of_line (); | |
431 | } | |
432 | ||
433 | /* Second pass to expanding the debug symbols, go through linked | |
434 | list of symbols and reassign the address. */ | |
435 | ||
436 | static void | |
437 | expand_debug_syms (syms, align) | |
438 | sym_linkS *syms; | |
439 | int align; | |
440 | { | |
441 | char *save_input_line = input_line_pointer; | |
442 | sym_linkS *next_syms; | |
443 | ||
444 | if (!syms) | |
445 | return; | |
446 | ||
a8150a88 | 447 | (void) frag_align_code (align, 0); |
ab3e48dc | 448 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
252b5132 RH |
449 | { |
450 | symbolS *symbolP = syms->symbol; | |
451 | next_syms = syms->next; | |
452 | input_line_pointer = ".\n"; | |
453 | pseudo_set (symbolP); | |
ab3e48dc | 454 | free ((char *) syms); |
252b5132 RH |
455 | } |
456 | ||
457 | input_line_pointer = save_input_line; | |
458 | } | |
459 | ||
460 | /* Cover function to fill_insn called after a label and at end of assembly. | |
461 | The result is always 1: we're called in a conditional to see if the | |
462 | current line is a label. */ | |
463 | ||
464 | int | |
465 | m32r_fill_insn (done) | |
466 | int done; | |
467 | { | |
468 | if (prev_seg != NULL) | |
469 | { | |
ab3e48dc | 470 | segT seg = now_seg; |
252b5132 RH |
471 | subsegT subseg = now_subseg; |
472 | ||
473 | subseg_set (prev_seg, prev_subseg); | |
ab3e48dc | 474 | |
252b5132 RH |
475 | fill_insn (0); |
476 | ||
477 | subseg_set (seg, subseg); | |
478 | } | |
479 | ||
480 | if (done && debug_sym_link) | |
481 | { | |
482 | expand_debug_syms (debug_sym_link, 1); | |
ab3e48dc | 483 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
484 | } |
485 | ||
486 | return 1; | |
487 | } | |
488 | \f | |
489 | void | |
490 | md_begin () | |
491 | { | |
492 | flagword applicable; | |
ab3e48dc KH |
493 | segT seg; |
494 | subsegT subseg; | |
252b5132 RH |
495 | |
496 | /* Initialize the `cgen' interface. */ | |
ab3e48dc | 497 | |
252b5132 RH |
498 | /* Set the machine number and endian. */ |
499 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, | |
500 | CGEN_CPU_OPEN_ENDIAN, | |
501 | CGEN_ENDIAN_BIG, | |
502 | CGEN_CPU_OPEN_END); | |
503 | m32r_cgen_init_asm (gas_cgen_cpu_desc); | |
504 | ||
505 | /* The operand instance table is used during optimization to determine | |
506 | which insns can be executed in parallel. It is also used to give | |
507 | warnings regarding operand interference in parallel insns. */ | |
508 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); | |
509 | ||
510 | /* This is a callback from cgen to gas to parse operands. */ | |
511 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
512 | ||
ab3e48dc KH |
513 | #if 0 |
514 | /* Not supported yet. */ | |
252b5132 RH |
515 | /* If a runtime cpu description file was provided, parse it. */ |
516 | if (m32r_cpu_desc != NULL) | |
517 | { | |
ab3e48dc | 518 | const char *errmsg; |
252b5132 RH |
519 | |
520 | errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); | |
521 | if (errmsg != NULL) | |
522 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); | |
523 | } | |
524 | #endif | |
525 | ||
526 | /* Save the current subseg so we can restore it [it's the default one and | |
527 | we don't want the initial section to be .sbss]. */ | |
528 | seg = now_seg; | |
529 | subseg = now_subseg; | |
530 | ||
531 | /* The sbss section is for local .scomm symbols. */ | |
532 | sbss_section = subseg_new (".sbss", 0); | |
ab3e48dc | 533 | |
252b5132 RH |
534 | /* This is copied from perform_an_assembly_pass. */ |
535 | applicable = bfd_applicable_section_flags (stdoutput); | |
536 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ab3e48dc KH |
537 | |
538 | #if 0 | |
539 | /* What does this do? [see perform_an_assembly_pass] */ | |
252b5132 RH |
540 | seg_info (bss_section)->bss = 1; |
541 | #endif | |
542 | ||
543 | subseg_set (seg, subseg); | |
544 | ||
545 | /* We must construct a fake section similar to bfd_com_section | |
546 | but with the name .scommon. */ | |
547 | scom_section = bfd_com_section; | |
548 | scom_section.name = ".scommon"; | |
ab3e48dc KH |
549 | scom_section.output_section = &scom_section; |
550 | scom_section.symbol = &scom_symbol; | |
551 | scom_section.symbol_ptr_ptr = &scom_section.symbol; | |
552 | scom_symbol = *bfd_com_section.symbol; | |
252b5132 | 553 | scom_symbol.name = ".scommon"; |
ab3e48dc | 554 | scom_symbol.section = &scom_section; |
252b5132 | 555 | |
925c058e | 556 | allow_m32rx (enable_m32rx); |
002de68b | 557 | |
07726851 | 558 | gas_cgen_initialize_saved_fixups_array (); |
925c058e DE |
559 | } |
560 | ||
561 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ | |
562 | ((operand)->hw_type == HW_H_COND \ | |
563 | || ((operand)->hw_type == HW_H_PSW) \ | |
564 | || ((operand)->hw_type == HW_H_CR \ | |
565 | && (indices [index] == 0 || indices [index] == 1))) | |
566 | ||
567 | /* Returns true if an output of instruction 'a' is referenced by an operand | |
568 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
569 | checked, otherwise its inputs are examined. */ | |
570 | ||
571 | static int | |
572 | first_writes_to_seconds_operands (a, b, check_outputs) | |
ab3e48dc KH |
573 | m32r_insn *a; |
574 | m32r_insn *b; | |
575 | const int check_outputs; | |
925c058e | 576 | { |
ab3e48dc KH |
577 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
578 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); | |
925c058e DE |
579 | int a_index; |
580 | ||
581 | /* If at least one of the instructions takes no operands, then there is | |
582 | nothing to check. There really are instructions without operands, | |
583 | eg 'nop'. */ | |
584 | if (a_operands == NULL || b_ops == NULL) | |
585 | return 0; | |
ab3e48dc | 586 | |
925c058e DE |
587 | /* Scan the operand list of 'a' looking for an output operand. */ |
588 | for (a_index = 0; | |
589 | a_operands->type != CGEN_OPINST_END; | |
590 | a_index ++, a_operands ++) | |
591 | { | |
592 | if (a_operands->type == CGEN_OPINST_OUTPUT) | |
593 | { | |
594 | int b_index; | |
ab3e48dc | 595 | const CGEN_OPINST *b_operands = b_ops; |
925c058e DE |
596 | |
597 | /* Special Case: | |
598 | The Condition bit 'C' is a shadow of the CBR register (control | |
599 | register 1) and also a shadow of bit 31 of the program status | |
600 | word (control register 0). For now this is handled here, rather | |
ab3e48dc KH |
601 | than by cgen.... */ |
602 | ||
925c058e DE |
603 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
604 | { | |
605 | /* Scan operand list of 'b' looking for another reference to the | |
606 | condition bit, which goes in the right direction. */ | |
607 | for (b_index = 0; | |
608 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 609 | b_index++, b_operands++) |
925c058e DE |
610 | { |
611 | if ((b_operands->type | |
612 | == (check_outputs | |
613 | ? CGEN_OPINST_OUTPUT | |
614 | : CGEN_OPINST_INPUT)) | |
615 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) | |
616 | return 1; | |
617 | } | |
618 | } | |
619 | else | |
620 | { | |
621 | /* Scan operand list of 'b' looking for an operand that | |
622 | references the same hardware element, and which goes in the | |
623 | right direction. */ | |
624 | for (b_index = 0; | |
625 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 626 | b_index++, b_operands++) |
925c058e DE |
627 | { |
628 | if ((b_operands->type | |
629 | == (check_outputs | |
630 | ? CGEN_OPINST_OUTPUT | |
631 | : CGEN_OPINST_INPUT)) | |
632 | && (b_operands->hw_type == a_operands->hw_type) | |
ab3e48dc | 633 | && (a->indices[a_index] == b->indices[b_index])) |
925c058e DE |
634 | return 1; |
635 | } | |
636 | } | |
637 | } | |
638 | } | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | /* Returns true if the insn can (potentially) alter the program counter. */ | |
644 | ||
645 | static int | |
646 | writes_to_pc (a) | |
ab3e48dc | 647 | m32r_insn *a; |
925c058e | 648 | { |
ab3e48dc KH |
649 | #if 0 |
650 | /* Once PC operands are working.... */ | |
651 | const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc, | |
652 | a->insn); | |
925c058e DE |
653 | |
654 | if (a_operands == NULL) | |
655 | return 0; | |
656 | ||
657 | while (a_operands->type != CGEN_OPINST_END) | |
658 | { | |
659 | if (a_operands->operand != NULL | |
ab3e48dc KH |
660 | && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, |
661 | a_operands->operand) == M32R_OPERAND_PC) | |
925c058e | 662 | return 1; |
ab3e48dc KH |
663 | |
664 | a_operands++; | |
925c058e DE |
665 | } |
666 | #else | |
667 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) | |
668 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) | |
669 | return 1; | |
670 | #endif | |
671 | return 0; | |
672 | } | |
673 | ||
ab3e48dc KH |
674 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
675 | Otherwise return a pointer to an error message explaining why not. */ | |
925c058e DE |
676 | |
677 | static const char * | |
678 | can_make_parallel (a, b) | |
ab3e48dc KH |
679 | m32r_insn *a; |
680 | m32r_insn *b; | |
925c058e DE |
681 | { |
682 | PIPE_ATTR a_pipe; | |
683 | PIPE_ATTR b_pipe; | |
ab3e48dc | 684 | |
925c058e | 685 | /* Make sure the instructions are the right length. */ |
ab3e48dc KH |
686 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
687 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) | |
688 | abort (); | |
925c058e DE |
689 | |
690 | if (first_writes_to_seconds_operands (a, b, true)) | |
691 | return _("Instructions write to the same destination register."); | |
ab3e48dc | 692 | |
925c058e DE |
693 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
694 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); | |
695 | ||
696 | /* Make sure that the instructions use the correct execution pipelines. */ | |
ab3e48dc | 697 | if (a_pipe == PIPE_NONE |
925c058e DE |
698 | || b_pipe == PIPE_NONE) |
699 | return _("Instructions do not use parallel execution pipelines."); | |
700 | ||
701 | /* Leave this test for last, since it is the only test that can | |
702 | go away if the instructions are swapped, and we want to make | |
703 | sure that any other errors are detected before this happens. */ | |
ab3e48dc | 704 | if (a_pipe == PIPE_S |
925c058e DE |
705 | || b_pipe == PIPE_O) |
706 | return _("Instructions share the same execution pipeline"); | |
ab3e48dc | 707 | |
925c058e DE |
708 | return NULL; |
709 | } | |
710 | ||
711 | /* Force the top bit of the second 16-bit insn to be set. */ | |
712 | ||
713 | static void | |
714 | make_parallel (buffer) | |
715 | CGEN_INSN_BYTES_PTR buffer; | |
716 | { | |
717 | #if CGEN_INT_INSN_P | |
718 | *buffer |= 0x8000; | |
719 | #else | |
ab3e48dc | 720 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
721 | |= 0x80; |
722 | #endif | |
252b5132 RH |
723 | } |
724 | ||
925c058e | 725 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
252b5132 | 726 | |
925c058e DE |
727 | static void |
728 | target_make_parallel (buffer) | |
729 | char *buffer; | |
730 | { | |
ab3e48dc | 731 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
732 | |= 0x80; |
733 | } | |
734 | ||
735 | /* Assemble two instructions with an explicit parallel operation (||) or | |
736 | sequential operation (->). */ | |
737 | ||
738 | static void | |
739 | assemble_two_insns (str, str2, parallel_p) | |
ab3e48dc KH |
740 | char *str; |
741 | char *str2; | |
742 | int parallel_p; | |
925c058e | 743 | { |
ab3e48dc | 744 | char *str3; |
925c058e DE |
745 | m32r_insn first; |
746 | m32r_insn second; | |
ab3e48dc KH |
747 | char *errmsg; |
748 | char save_str2 = *str2; | |
925c058e | 749 | |
ab3e48dc KH |
750 | /* Seperate the two instructions. */ |
751 | *str2 = 0; | |
925c058e DE |
752 | |
753 | /* Make sure the two insns begin on a 32 bit boundary. | |
754 | This is also done for the serial case (foo -> bar), relaxing doesn't | |
755 | affect insns written like this. | |
756 | Note that we must always do this as we can't assume anything about | |
757 | whether we're currently on a 32 bit boundary or not. Relaxing may | |
758 | change this. */ | |
759 | fill_insn (0); | |
760 | ||
761 | first.debug_sym_link = debug_sym_link; | |
ab3e48dc | 762 | debug_sym_link = (sym_linkS *) 0; |
925c058e DE |
763 | |
764 | /* Parse the first instruction. */ | |
765 | if (! (first.insn = m32r_cgen_assemble_insn | |
766 | (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) | |
767 | { | |
768 | as_bad (errmsg); | |
769 | return; | |
770 | } | |
771 | ||
772 | /* Check it. */ | |
773 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) | |
774 | { | |
ab3e48dc | 775 | /* xgettext:c-format */ |
925c058e DE |
776 | as_bad (_("not a 16 bit instruction '%s'"), str); |
777 | return; | |
778 | } | |
779 | else if (! enable_special | |
780 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
781 | { | |
ab3e48dc | 782 | /* xgettext:c-format */ |
925c058e DE |
783 | as_bad (_("unknown instruction '%s'"), str); |
784 | return; | |
785 | } | |
786 | else if (! enable_m32rx | |
ab3e48dc KH |
787 | /* FIXME: Need standard macro to perform this test. */ |
788 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
789 | == (1 << MACH_M32RX))) | |
925c058e | 790 | { |
ab3e48dc | 791 | /* xgettext:c-format */ |
925c058e DE |
792 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
793 | return; | |
794 | } | |
ab3e48dc | 795 | |
925c058e | 796 | /* Check to see if this is an allowable parallel insn. */ |
ab3e48dc KH |
797 | if (parallel_p |
798 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 799 | { |
ab3e48dc | 800 | /* xgettext:c-format */ |
925c058e DE |
801 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
802 | return; | |
803 | } | |
ab3e48dc KH |
804 | |
805 | /* Restore the original assembly text, just in case it is needed. */ | |
806 | *str2 = save_str2; | |
807 | ||
808 | /* Save the original string pointer. */ | |
809 | str3 = str; | |
810 | ||
811 | /* Advanced past the parsed string. */ | |
812 | str = str2 + 2; | |
813 | ||
814 | /* Remember the entire string in case it is needed for error | |
815 | messages. */ | |
816 | str2 = str3; | |
925c058e DE |
817 | |
818 | /* Convert the opcode to lower case. */ | |
819 | { | |
820 | char *s2 = str; | |
ab3e48dc | 821 | |
3882b010 | 822 | while (ISSPACE (*s2++)) |
925c058e DE |
823 | continue; |
824 | ||
825 | --s2; | |
826 | ||
3882b010 | 827 | while (ISALNUM (*s2)) |
925c058e | 828 | { |
3882b010 | 829 | *s2 = TOLOWER (*s2); |
ab3e48dc | 830 | s2++; |
925c058e DE |
831 | } |
832 | } | |
ab3e48dc KH |
833 | |
834 | /* Preserve any fixups that have been generated and reset the list | |
835 | to empty. */ | |
002de68b | 836 | gas_cgen_save_fixups (0); |
925c058e DE |
837 | |
838 | /* Get the indices of the operands of the instruction. */ | |
839 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
840 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
841 | /* FIXME: ALIAS insns do not have operands, so we use this function | |
842 | to find the equivalent insn and overwrite the value stored in our | |
843 | structure. We still need the original insn, however, since this | |
844 | may have certain attributes that are not present in the unaliased | |
845 | version (eg relaxability). When aliases behave differently this | |
846 | may have to change. */ | |
847 | first.orig_insn = first.insn; | |
848 | { | |
849 | CGEN_FIELDS tmp_fields; | |
850 | first.insn = cgen_lookup_get_insn_operands | |
851 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, | |
852 | first.indices, &tmp_fields); | |
853 | } | |
ab3e48dc | 854 | |
925c058e DE |
855 | if (first.insn == NULL) |
856 | as_fatal (_("internal error: lookup/get operands failed")); | |
857 | ||
858 | second.debug_sym_link = NULL; | |
859 | ||
860 | /* Parse the second instruction. */ | |
861 | if (! (second.insn = m32r_cgen_assemble_insn | |
862 | (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) | |
863 | { | |
864 | as_bad (errmsg); | |
865 | return; | |
866 | } | |
867 | ||
868 | /* Check it. */ | |
869 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) | |
870 | { | |
ab3e48dc | 871 | /* xgettext:c-format */ |
925c058e DE |
872 | as_bad (_("not a 16 bit instruction '%s'"), str); |
873 | return; | |
874 | } | |
875 | else if (! enable_special | |
876 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
877 | { | |
ab3e48dc | 878 | /* xgettext:c-format */ |
925c058e DE |
879 | as_bad (_("unknown instruction '%s'"), str); |
880 | return; | |
881 | } | |
882 | else if (! enable_m32rx | |
883 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
884 | { | |
ab3e48dc | 885 | /* xgettext:c-format */ |
925c058e DE |
886 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
887 | return; | |
888 | } | |
889 | ||
890 | /* Check to see if this is an allowable parallel insn. */ | |
ab3e48dc KH |
891 | if (parallel_p |
892 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 893 | { |
ab3e48dc | 894 | /* xgettext:c-format */ |
925c058e DE |
895 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
896 | return; | |
897 | } | |
ab3e48dc | 898 | |
925c058e DE |
899 | if (parallel_p && ! enable_m32rx) |
900 | { | |
901 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP | |
902 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) | |
903 | { | |
ab3e48dc | 904 | /* xgettext:c-format */ |
925c058e DE |
905 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
906 | return; | |
907 | } | |
908 | } | |
909 | ||
910 | /* Get the indices of the operands of the instruction. */ | |
911 | second.orig_insn = second.insn; | |
912 | { | |
913 | CGEN_FIELDS tmp_fields; | |
914 | second.insn = cgen_lookup_get_insn_operands | |
915 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, | |
916 | second.indices, &tmp_fields); | |
917 | } | |
ab3e48dc | 918 | |
925c058e DE |
919 | if (second.insn == NULL) |
920 | as_fatal (_("internal error: lookup/get operands failed")); | |
921 | ||
922 | /* We assume that if the first instruction writes to a register that is | |
923 | read by the second instruction it is because the programmer intended | |
924 | this to happen, (after all they have explicitly requested that these | |
925 | two instructions be executed in parallel). Although if the global | |
926 | variable warn_explicit_parallel_conflicts is true then we do generate | |
927 | a warning message. Similarly we assume that parallel branch and jump | |
928 | instructions are deliberate and should not produce errors. */ | |
ab3e48dc | 929 | |
925c058e DE |
930 | if (parallel_p && warn_explicit_parallel_conflicts) |
931 | { | |
ab3e48dc KH |
932 | if (first_writes_to_seconds_operands (&first, &second, false)) |
933 | /* xgettext:c-format */ | |
925c058e | 934 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
ab3e48dc KH |
935 | |
936 | if (first_writes_to_seconds_operands (&second, &first, false)) | |
937 | /* xgettext:c-format */ | |
925c058e DE |
938 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
939 | } | |
ab3e48dc | 940 | |
925c058e | 941 | if (!parallel_p |
ab3e48dc | 942 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
925c058e DE |
943 | { |
944 | /* Get the fixups for the first instruction. */ | |
002de68b | 945 | gas_cgen_swap_fixups (0); |
925c058e DE |
946 | |
947 | /* Write it out. */ | |
948 | expand_debug_syms (first.debug_sym_link, 1); | |
949 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc KH |
950 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
951 | ||
925c058e DE |
952 | /* Force the top bit of the second insn to be set. */ |
953 | if (parallel_p) | |
954 | make_parallel (second.buffer); | |
955 | ||
956 | /* Get its fixups. */ | |
002de68b | 957 | gas_cgen_restore_fixups (0); |
925c058e DE |
958 | |
959 | /* Write it out. */ | |
960 | expand_debug_syms (second.debug_sym_link, 1); | |
961 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc | 962 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
925c058e DE |
963 | } |
964 | /* Try swapping the instructions to see if they work that way. */ | |
ab3e48dc | 965 | else if (can_make_parallel (&second, &first) == NULL) |
925c058e DE |
966 | { |
967 | /* Write out the second instruction first. */ | |
968 | expand_debug_syms (second.debug_sym_link, 1); | |
969 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc KH |
970 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
971 | ||
925c058e DE |
972 | /* Force the top bit of the first instruction to be set. */ |
973 | make_parallel (first.buffer); | |
974 | ||
975 | /* Get the fixups for the first instruction. */ | |
002de68b | 976 | gas_cgen_restore_fixups (0); |
925c058e DE |
977 | |
978 | /* Write out the first instruction. */ | |
979 | expand_debug_syms (first.debug_sym_link, 1); | |
980 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc | 981 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
925c058e DE |
982 | } |
983 | else | |
984 | { | |
985 | as_bad ("'%s': %s", str2, errmsg); | |
986 | return; | |
987 | } | |
ab3e48dc | 988 | |
925c058e DE |
989 | /* Set these so m32r_fill_insn can use them. */ |
990 | prev_seg = now_seg; | |
991 | prev_subseg = now_subseg; | |
992 | } | |
252b5132 RH |
993 | |
994 | void | |
995 | md_assemble (str) | |
ab3e48dc | 996 | char *str; |
252b5132 RH |
997 | { |
998 | m32r_insn insn; | |
ab3e48dc KH |
999 | char *errmsg; |
1000 | char *str2 = NULL; | |
252b5132 RH |
1001 | |
1002 | /* Initialize GAS's cgen interface for a new instruction. */ | |
1003 | gas_cgen_init_parse (); | |
1004 | ||
925c058e DE |
1005 | /* Look for a parallel instruction seperator. */ |
1006 | if ((str2 = strstr (str, "||")) != NULL) | |
1007 | { | |
1008 | assemble_two_insns (str, str2, 1); | |
1009 | return; | |
1010 | } | |
1011 | ||
1012 | /* Also look for a sequential instruction seperator. */ | |
1013 | if ((str2 = strstr (str, "->")) != NULL) | |
1014 | { | |
1015 | assemble_two_insns (str, str2, 0); | |
1016 | return; | |
1017 | } | |
ab3e48dc | 1018 | |
252b5132 | 1019 | insn.debug_sym_link = debug_sym_link; |
ab3e48dc | 1020 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
1021 | |
1022 | insn.insn = m32r_cgen_assemble_insn | |
ab3e48dc KH |
1023 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
1024 | ||
252b5132 RH |
1025 | if (!insn.insn) |
1026 | { | |
1027 | as_bad (errmsg); | |
1028 | return; | |
1029 | } | |
1030 | ||
925c058e DE |
1031 | if (! enable_special |
1032 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
1033 | { | |
ab3e48dc | 1034 | /* xgettext:c-format */ |
925c058e DE |
1035 | as_bad (_("unknown instruction '%s'"), str); |
1036 | return; | |
1037 | } | |
1038 | else if (! enable_m32rx | |
1039 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1040 | { | |
ab3e48dc | 1041 | /* xgettext:c-format */ |
925c058e DE |
1042 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1043 | return; | |
1044 | } | |
ab3e48dc | 1045 | |
252b5132 RH |
1046 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
1047 | { | |
1048 | /* 32 bit insns must live on 32 bit boundaries. */ | |
1049 | if (prev_insn.insn || seen_relaxable_p) | |
1050 | { | |
1051 | /* ??? If calling fill_insn too many times turns us into a memory | |
1052 | pig, can we call a fn to assemble a nop instead of | |
1053 | !seen_relaxable_p? */ | |
1054 | fill_insn (0); | |
1055 | } | |
1056 | ||
1057 | expand_debug_syms (insn.debug_sym_link, 2); | |
1058 | ||
1059 | /* Doesn't really matter what we pass for RELAX_P here. */ | |
1060 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
ab3e48dc | 1061 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
252b5132 RH |
1062 | } |
1063 | else | |
1064 | { | |
1065 | int on_32bit_boundary_p; | |
925c058e | 1066 | int swap = false; |
252b5132 RH |
1067 | |
1068 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
ab3e48dc | 1069 | abort (); |
252b5132 RH |
1070 | |
1071 | insn.orig_insn = insn.insn; | |
1072 | ||
925c058e DE |
1073 | /* If the previous insn was relaxable, then it may be expanded |
1074 | to fill the current 16 bit slot. Emit a NOP here to occupy | |
1075 | this slot, so that we can start at optimizing at a 32 bit | |
1076 | boundary. */ | |
1077 | if (prev_insn.insn && seen_relaxable_p && optimize) | |
1078 | fill_insn (0); | |
ab3e48dc | 1079 | |
925c058e DE |
1080 | if (enable_m32rx) |
1081 | { | |
1082 | /* Get the indices of the operands of the instruction. | |
1083 | FIXME: See assemble_parallel for notes on orig_insn. */ | |
1084 | { | |
1085 | CGEN_FIELDS tmp_fields; | |
1086 | insn.insn = cgen_lookup_get_insn_operands | |
1087 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, | |
1088 | 16, insn.indices, &tmp_fields); | |
1089 | } | |
ab3e48dc | 1090 | |
925c058e DE |
1091 | if (insn.insn == NULL) |
1092 | as_fatal (_("internal error: lookup/get operands failed")); | |
1093 | } | |
1094 | ||
252b5132 RH |
1095 | /* Compute whether we're on a 32 bit boundary or not. |
1096 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1097 | on_32bit_boundary_p = prev_insn.insn == NULL; | |
1098 | ||
925c058e DE |
1099 | /* Look to see if this instruction can be combined with the |
1100 | previous instruction to make one, parallel, 32 bit instruction. | |
1101 | If the previous instruction (potentially) changed the flow of | |
1102 | program control, then it cannot be combined with the current | |
1103 | instruction. If the current instruction is relaxable, then it | |
1104 | might be replaced with a longer version, so we cannot combine it. | |
1105 | Also if the output of the previous instruction is used as an | |
1106 | input to the current instruction then it cannot be combined. | |
1107 | Otherwise call can_make_parallel() with both orderings of the | |
1108 | instructions to see if they can be combined. */ | |
ab3e48dc KH |
1109 | if (! on_32bit_boundary_p |
1110 | && enable_m32rx | |
1111 | && optimize | |
1112 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 | |
1113 | && ! writes_to_pc (&prev_insn) | |
1114 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, false)) | |
925c058e | 1115 | { |
ab3e48dc | 1116 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
925c058e | 1117 | make_parallel (insn.buffer); |
ab3e48dc | 1118 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
925c058e DE |
1119 | swap = true; |
1120 | } | |
252b5132 RH |
1121 | |
1122 | expand_debug_syms (insn.debug_sym_link, 1); | |
1123 | ||
1124 | { | |
1125 | int i; | |
1126 | finished_insnS fi; | |
1127 | ||
1128 | /* Ensure each pair of 16 bit insns is in the same frag. */ | |
1129 | frag_grow (4); | |
1130 | ||
1131 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, | |
ab3e48dc KH |
1132 | CGEN_FIELDS_BITSIZE (&insn.fields), |
1133 | 1 /* relax_p */, &fi); | |
252b5132 RH |
1134 | insn.addr = fi.addr; |
1135 | insn.frag = fi.frag; | |
1136 | insn.num_fixups = fi.num_fixups; | |
1137 | for (i = 0; i < fi.num_fixups; ++i) | |
1138 | insn.fixups[i] = fi.fixups[i]; | |
1139 | } | |
1140 | ||
925c058e DE |
1141 | if (swap) |
1142 | { | |
ab3e48dc | 1143 | int i, tmp; |
925c058e DE |
1144 | |
1145 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
1146 | ||
1147 | /* Swap the two insns */ | |
ab3e48dc KH |
1148 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
1149 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); | |
925c058e DE |
1150 | |
1151 | target_make_parallel (insn.addr); | |
1152 | ||
1153 | /* Swap any relaxable frags recorded for the two insns. */ | |
1154 | /* FIXME: Clarify. relaxation precludes parallel insns */ | |
1155 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
1156 | prev_insn.frag->fr_opcode = insn.addr; | |
1157 | else if (insn.frag->fr_opcode == insn.addr) | |
1158 | insn.frag->fr_opcode = prev_insn.addr; | |
1159 | ||
1160 | /* Update the addresses in any fixups. | |
1161 | Note that we don't have to handle the case where each insn is in | |
1162 | a different frag as we ensure they're in the same frag above. */ | |
1163 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1164 | prev_insn.fixups[i]->fx_where += 2; | |
1165 | for (i = 0; i < insn.num_fixups; ++i) | |
1166 | insn.fixups[i]->fx_where -= 2; | |
1167 | } | |
252b5132 RH |
1168 | |
1169 | /* Keep track of whether we've seen a pair of 16 bit insns. | |
1170 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1171 | if (on_32bit_boundary_p) | |
1172 | prev_insn = insn; | |
1173 | else | |
1174 | prev_insn.insn = NULL; | |
ab3e48dc | 1175 | |
252b5132 RH |
1176 | /* If the insn needs the following one to be on a 32 bit boundary |
1177 | (e.g. subroutine calls), fill this insn's slot. */ | |
1178 | if (on_32bit_boundary_p | |
1179 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) | |
1180 | fill_insn (0); | |
1181 | ||
1182 | /* If this is a relaxable insn (can be replaced with a larger version) | |
1183 | mark the fact so that we can emit an alignment directive for a | |
1184 | following 32 bit insn if we see one. */ | |
1185 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) | |
1186 | seen_relaxable_p = 1; | |
1187 | } | |
1188 | ||
1189 | /* Set these so m32r_fill_insn can use them. */ | |
1190 | prev_seg = now_seg; | |
1191 | prev_subseg = now_subseg; | |
1192 | } | |
1193 | ||
1194 | /* The syntax in the manual says constants begin with '#'. | |
1195 | We just ignore it. */ | |
1196 | ||
ab3e48dc | 1197 | void |
252b5132 | 1198 | md_operand (expressionP) |
ab3e48dc | 1199 | expressionS *expressionP; |
252b5132 | 1200 | { |
ab3e48dc | 1201 | if (*input_line_pointer == '#') |
252b5132 | 1202 | { |
ab3e48dc | 1203 | input_line_pointer++; |
252b5132 RH |
1204 | expression (expressionP); |
1205 | } | |
1206 | } | |
1207 | ||
1208 | valueT | |
1209 | md_section_align (segment, size) | |
ab3e48dc | 1210 | segT segment; |
252b5132 RH |
1211 | valueT size; |
1212 | { | |
1213 | int align = bfd_get_section_alignment (stdoutput, segment); | |
1214 | return ((size + (1 << align) - 1) & (-1 << align)); | |
1215 | } | |
1216 | ||
1217 | symbolS * | |
1218 | md_undefined_symbol (name) | |
ab3e48dc | 1219 | char *name; |
252b5132 RH |
1220 | { |
1221 | return 0; | |
1222 | } | |
1223 | \f | |
1224 | /* .scomm pseudo-op handler. | |
1225 | ||
1226 | This is a new pseudo-op to handle putting objects in .scommon. | |
ab3e48dc KH |
1227 | By doing this the linker won't need to do any work, |
1228 | and more importantly it removes the implicit -G arg necessary to | |
1229 | correctly link the object file. */ | |
252b5132 RH |
1230 | |
1231 | static void | |
1232 | m32r_scomm (ignore) | |
1233 | int ignore; | |
1234 | { | |
ab3e48dc KH |
1235 | register char *name; |
1236 | register char c; | |
1237 | register char *p; | |
1238 | offsetT size; | |
1239 | register symbolS *symbolP; | |
1240 | offsetT align; | |
1241 | int align2; | |
252b5132 RH |
1242 | |
1243 | name = input_line_pointer; | |
1244 | c = get_symbol_end (); | |
1245 | ||
ab3e48dc | 1246 | /* Just after name is now '\0'. */ |
252b5132 | 1247 | p = input_line_pointer; |
ab3e48dc | 1248 | *p = c; |
252b5132 | 1249 | SKIP_WHITESPACE (); |
ab3e48dc | 1250 | if (*input_line_pointer != ',') |
252b5132 RH |
1251 | { |
1252 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); | |
1253 | ignore_rest_of_line (); | |
1254 | return; | |
1255 | } | |
1256 | ||
ab3e48dc KH |
1257 | /* Skip ','. */ |
1258 | input_line_pointer++; | |
252b5132 RH |
1259 | if ((size = get_absolute_expression ()) < 0) |
1260 | { | |
ab3e48dc | 1261 | /* xgettext:c-format */ |
252b5132 RH |
1262 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
1263 | ignore_rest_of_line (); | |
1264 | return; | |
1265 | } | |
1266 | ||
1267 | /* The third argument to .scomm is the alignment. */ | |
ab3e48dc | 1268 | if (*input_line_pointer != ',') |
252b5132 RH |
1269 | align = 8; |
1270 | else | |
1271 | { | |
ab3e48dc | 1272 | ++input_line_pointer; |
252b5132 RH |
1273 | align = get_absolute_expression (); |
1274 | if (align <= 0) | |
1275 | { | |
1276 | as_warn (_("ignoring bad alignment")); | |
1277 | align = 8; | |
1278 | } | |
1279 | } | |
ab3e48dc | 1280 | |
252b5132 RH |
1281 | /* Convert to a power of 2 alignment. */ |
1282 | if (align) | |
1283 | { | |
ab3e48dc | 1284 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
252b5132 RH |
1285 | continue; |
1286 | if (align != 1) | |
1287 | { | |
1288 | as_bad (_("Common alignment not a power of 2")); | |
1289 | ignore_rest_of_line (); | |
1290 | return; | |
1291 | } | |
1292 | } | |
1293 | else | |
1294 | align2 = 0; | |
1295 | ||
ab3e48dc | 1296 | *p = 0; |
252b5132 | 1297 | symbolP = symbol_find_or_make (name); |
ab3e48dc | 1298 | *p = c; |
252b5132 RH |
1299 | |
1300 | if (S_IS_DEFINED (symbolP)) | |
1301 | { | |
ab3e48dc | 1302 | /* xgettext:c-format */ |
252b5132 RH |
1303 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
1304 | S_GET_NAME (symbolP)); | |
1305 | ignore_rest_of_line (); | |
1306 | return; | |
1307 | } | |
1308 | ||
1309 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1310 | { | |
ab3e48dc | 1311 | /* xgettext:c-format */ |
252b5132 RH |
1312 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
1313 | S_GET_NAME (symbolP), | |
1314 | (long) S_GET_VALUE (symbolP), | |
1315 | (long) size); | |
1316 | ||
1317 | ignore_rest_of_line (); | |
1318 | return; | |
1319 | } | |
1320 | ||
f412ead8 | 1321 | if (symbol_get_obj (symbolP)->local) |
252b5132 | 1322 | { |
ab3e48dc KH |
1323 | segT old_sec = now_seg; |
1324 | int old_subsec = now_subseg; | |
1325 | char *pfrag; | |
252b5132 RH |
1326 | |
1327 | record_alignment (sbss_section, align2); | |
1328 | subseg_set (sbss_section, 0); | |
ab3e48dc | 1329 | |
252b5132 RH |
1330 | if (align2) |
1331 | frag_align (align2, 0, 0); | |
ab3e48dc | 1332 | |
252b5132 | 1333 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
f412ead8 | 1334 | symbol_get_frag (symbolP)->fr_symbol = 0; |
ab3e48dc | 1335 | |
f412ead8 | 1336 | symbol_set_frag (symbolP, frag_now); |
ab3e48dc | 1337 | |
252b5132 RH |
1338 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1339 | (char *) 0); | |
ab3e48dc | 1340 | *pfrag = 0; |
252b5132 RH |
1341 | S_SET_SIZE (symbolP, size); |
1342 | S_SET_SEGMENT (symbolP, sbss_section); | |
1343 | S_CLEAR_EXTERNAL (symbolP); | |
1344 | subseg_set (old_sec, old_subsec); | |
1345 | } | |
1346 | else | |
1347 | { | |
1348 | S_SET_VALUE (symbolP, (valueT) size); | |
1349 | S_SET_ALIGN (symbolP, align2); | |
1350 | S_SET_EXTERNAL (symbolP); | |
ab3e48dc | 1351 | S_SET_SEGMENT (symbolP, &scom_section); |
252b5132 RH |
1352 | } |
1353 | ||
1354 | demand_empty_rest_of_line (); | |
1355 | } | |
1356 | \f | |
1357 | /* Interface to relax_segment. */ | |
1358 | ||
1359 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1360 | ||
1361 | const relax_typeS md_relax_table[] = | |
1362 | { | |
1363 | /* The fields are: | |
1364 | 1) most positive reach of this state, | |
1365 | 2) most negative reach of this state, | |
1366 | 3) how many bytes this mode will add to the size of the current frag | |
1367 | 4) which index into the table to try if we can't fit into this one. */ | |
1368 | ||
1369 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1370 | each list. */ | |
1371 | {1, 1, 0, 0}, | |
1372 | ||
1373 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1374 | so we subtract 2 from the following. */ | |
1375 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1376 | This doesn't handle a branch in the right slot at the border: | |
1377 | the "& -4" isn't taken into account. It's not important enough to | |
1378 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1379 | case). */ | |
1380 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1381 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1382 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1383 | /* Same thing, but with leading nop for alignment. */ | |
1384 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1385 | }; | |
1386 | ||
1387 | long | |
c842b53a ILT |
1388 | m32r_relax_frag (segment, fragP, stretch) |
1389 | segT segment; | |
ab3e48dc KH |
1390 | fragS *fragP; |
1391 | long stretch; | |
252b5132 RH |
1392 | { |
1393 | /* Address of branch insn. */ | |
1394 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1395 | long growth = 0; | |
1396 | ||
1397 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1398 | if (fragP->fr_subtype == 2) | |
1399 | { | |
1400 | if ((address & 3) != 0) | |
1401 | { | |
1402 | fragP->fr_subtype = 3; | |
1403 | growth = 2; | |
1404 | } | |
1405 | } | |
1406 | else if (fragP->fr_subtype == 3) | |
1407 | { | |
1408 | if ((address & 3) == 0) | |
1409 | { | |
1410 | fragP->fr_subtype = 2; | |
1411 | growth = -2; | |
1412 | } | |
1413 | } | |
1414 | else | |
1415 | { | |
c842b53a | 1416 | growth = relax_frag (segment, fragP, stretch); |
252b5132 RH |
1417 | |
1418 | /* Long jump on odd halfword boundary? */ | |
1419 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1420 | { | |
1421 | fragP->fr_subtype = 3; | |
1422 | growth += 2; | |
1423 | } | |
1424 | } | |
1425 | ||
1426 | return growth; | |
1427 | } | |
1428 | ||
1429 | /* Return an initial guess of the length by which a fragment must grow to | |
1430 | hold a branch to reach its destination. | |
1431 | Also updates fr_type/fr_subtype as necessary. | |
1432 | ||
1433 | Called just before doing relaxation. | |
1434 | Any symbol that is now undefined will not become defined. | |
1435 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1436 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
ab3e48dc KH |
1437 | Although it may not be explicit in the frag, pretend fr_var starts |
1438 | with a 0 value. */ | |
252b5132 RH |
1439 | |
1440 | int | |
1441 | md_estimate_size_before_relax (fragP, segment) | |
ab3e48dc KH |
1442 | fragS *fragP; |
1443 | segT segment; | |
252b5132 | 1444 | { |
252b5132 RH |
1445 | /* The only thing we have to handle here are symbols outside of the |
1446 | current segment. They may be undefined or in a different segment in | |
1447 | which case linker scripts may place them anywhere. | |
1448 | However, we can't finish the fragment here and emit the reloc as insn | |
1449 | alignment requirements may move the insn about. */ | |
1450 | ||
1451 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
1452 | { | |
606ab118 AM |
1453 | int old_fr_fix = fragP->fr_fix; |
1454 | ||
252b5132 RH |
1455 | /* The symbol is undefined in this segment. |
1456 | Change the relaxation subtype to the max allowable and leave | |
1457 | all further handling to md_convert_frag. */ | |
1458 | fragP->fr_subtype = 2; | |
1459 | ||
ab3e48dc KH |
1460 | #if 0 |
1461 | /* Can't use this, but leave in for illustration. */ | |
252b5132 RH |
1462 | /* Change 16 bit insn to 32 bit insn. */ |
1463 | fragP->fr_opcode[0] |= 0x80; | |
1464 | ||
1465 | /* Increase known (fixed) size of fragment. */ | |
1466 | fragP->fr_fix += 2; | |
1467 | ||
1468 | /* Create a relocation for it. */ | |
1469 | fix_new (fragP, old_fr_fix, 4, | |
1470 | fragP->fr_symbol, | |
ab3e48dc | 1471 | fragP->fr_offset, 1 /* pcrel */, |
252b5132 RH |
1472 | /* FIXME: Can't use a real BFD reloc here. |
1473 | gas_cgen_md_apply_fix3 can't handle it. */ | |
1474 | BFD_RELOC_M32R_26_PCREL); | |
1475 | ||
1476 | /* Mark this fragment as finished. */ | |
1477 | frag_wane (fragP); | |
606ab118 | 1478 | return fragP->fr_fix - old_fr_fix; |
252b5132 RH |
1479 | #else |
1480 | { | |
ab3e48dc KH |
1481 | const CGEN_INSN *insn; |
1482 | int i; | |
252b5132 RH |
1483 | |
1484 | /* Update the recorded insn. | |
1485 | Fortunately we don't have to look very far. | |
1486 | FIXME: Change this to record in the instruction the next higher | |
1487 | relaxable insn to use. */ | |
1488 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1489 | { | |
1490 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), | |
1491 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
1492 | == 0) | |
1493 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX)) | |
1494 | break; | |
1495 | } | |
1496 | if (i == 4) | |
1497 | abort (); | |
1498 | ||
1499 | fragP->fr_cgen.insn = insn; | |
1500 | return 2; | |
1501 | } | |
1502 | #endif | |
1503 | } | |
1504 | ||
606ab118 | 1505 | return md_relax_table[fragP->fr_subtype].rlx_length; |
ab3e48dc | 1506 | } |
252b5132 | 1507 | |
ab3e48dc | 1508 | /* *FRAGP has been relaxed to its final size, and now needs to have |
252b5132 RH |
1509 | the bytes inside it modified to conform to the new size. |
1510 | ||
1511 | Called after relaxation is finished. | |
1512 | fragP->fr_type == rs_machine_dependent. | |
1513 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1514 | ||
1515 | void | |
1516 | md_convert_frag (abfd, sec, fragP) | |
ab3e48dc KH |
1517 | bfd *abfd; |
1518 | segT sec; | |
1519 | fragS *fragP; | |
252b5132 | 1520 | { |
ab3e48dc KH |
1521 | char *opcode; |
1522 | char *displacement; | |
1523 | int target_address; | |
1524 | int opcode_address; | |
1525 | int extension; | |
1526 | int addend; | |
252b5132 RH |
1527 | |
1528 | opcode = fragP->fr_opcode; | |
1529 | ||
1530 | /* Address opcode resides at in file space. */ | |
1531 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1532 | ||
1533 | switch (fragP->fr_subtype) | |
1534 | { | |
ab3e48dc | 1535 | case 1: |
252b5132 | 1536 | extension = 0; |
ab3e48dc | 1537 | displacement = &opcode[1]; |
252b5132 | 1538 | break; |
ab3e48dc | 1539 | case 2: |
252b5132 RH |
1540 | opcode[0] |= 0x80; |
1541 | extension = 2; | |
ab3e48dc | 1542 | displacement = &opcode[1]; |
252b5132 | 1543 | break; |
ab3e48dc | 1544 | case 3: |
252b5132 RH |
1545 | opcode[2] = opcode[0] | 0x80; |
1546 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1547 | opcode_address += 2; | |
1548 | extension = 4; | |
ab3e48dc | 1549 | displacement = &opcode[3]; |
252b5132 | 1550 | break; |
ab3e48dc | 1551 | default: |
252b5132 RH |
1552 | abort (); |
1553 | } | |
1554 | ||
1555 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1556 | { | |
ab3e48dc | 1557 | /* Symbol must be resolved by linker. */ |
252b5132 RH |
1558 | if (fragP->fr_offset & 3) |
1559 | as_warn (_("Addend to unresolved symbol not on word boundary.")); | |
1560 | addend = fragP->fr_offset >> 2; | |
1561 | } | |
1562 | else | |
1563 | { | |
1564 | /* Address we want to reach in file space. */ | |
1565 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
252b5132 RH |
1566 | addend = (target_address - (opcode_address & -4)) >> 2; |
1567 | } | |
1568 | ||
1569 | /* Create a relocation for symbols that must be resolved by the linker. | |
1570 | Otherwise output the completed insn. */ | |
1571 | ||
1572 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) | |
1573 | { | |
1574 | assert (fragP->fr_subtype != 1); | |
1575 | assert (fragP->fr_cgen.insn != 0); | |
1576 | gas_cgen_record_fixup (fragP, | |
1577 | /* Offset of branch insn in frag. */ | |
1578 | fragP->fr_fix + extension - 4, | |
1579 | fragP->fr_cgen.insn, | |
ab3e48dc KH |
1580 | 4 /* Length. */, |
1581 | /* FIXME: quick hack. */ | |
252b5132 RH |
1582 | #if 0 |
1583 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
1584 | fragP->fr_cgen.opindex), | |
1585 | #else | |
1586 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
1587 | M32R_OPERAND_DISP24), | |
1588 | #endif | |
1589 | fragP->fr_cgen.opinfo, | |
1590 | fragP->fr_symbol, fragP->fr_offset); | |
1591 | } | |
1592 | ||
1593 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1594 | ||
1595 | md_number_to_chars (displacement, (valueT) addend, | |
1596 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1597 | ||
1598 | fragP->fr_fix += extension; | |
1599 | } | |
1600 | \f | |
1601 | /* Functions concerning relocs. */ | |
1602 | ||
1603 | /* The location from which a PC relative jump should be calculated, | |
1604 | given a PC relative reloc. */ | |
1605 | ||
1606 | long | |
1607 | md_pcrel_from_section (fixP, sec) | |
ab3e48dc KH |
1608 | fixS *fixP; |
1609 | segT sec; | |
252b5132 RH |
1610 | { |
1611 | if (fixP->fx_addsy != (symbolS *) NULL | |
1612 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
1613 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
1614 | { | |
1615 | /* The symbol is undefined (or is defined but not in this section). | |
1616 | Let the linker figure it out. */ | |
1617 | return 0; | |
1618 | } | |
1619 | ||
1620 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1621 | } | |
1622 | ||
1623 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1624 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1625 | *FIXP may be modified if desired. */ | |
1626 | ||
1627 | bfd_reloc_code_real_type | |
1628 | md_cgen_lookup_reloc (insn, operand, fixP) | |
ab3e48dc KH |
1629 | const CGEN_INSN *insn; |
1630 | const CGEN_OPERAND *operand; | |
1631 | fixS *fixP; | |
252b5132 RH |
1632 | { |
1633 | switch (operand->type) | |
1634 | { | |
ab3e48dc KH |
1635 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
1636 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; | |
1637 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; | |
1638 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; | |
1639 | case M32R_OPERAND_HI16: | |
1640 | case M32R_OPERAND_SLO16: | |
1641 | case M32R_OPERAND_ULO16: | |
252b5132 RH |
1642 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1643 | if (fixP->fx_cgen.opinfo != 0) | |
1644 | return fixP->fx_cgen.opinfo; | |
1645 | break; | |
ab3e48dc KH |
1646 | default: |
1647 | /* Avoid -Wall warning. */ | |
252b5132 RH |
1648 | break; |
1649 | } | |
1650 | return BFD_RELOC_NONE; | |
1651 | } | |
1652 | ||
1653 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ | |
1654 | ||
1655 | static void | |
1656 | m32r_record_hi16 (reloc_type, fixP, seg) | |
ab3e48dc KH |
1657 | int reloc_type; |
1658 | fixS *fixP; | |
1659 | segT seg; | |
252b5132 | 1660 | { |
ab3e48dc | 1661 | struct m32r_hi_fixup *hi_fixup; |
252b5132 RH |
1662 | |
1663 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1664 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1665 | ||
1666 | hi_fixup = ((struct m32r_hi_fixup *) | |
1667 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1668 | hi_fixup->fixp = fixP; | |
1669 | hi_fixup->seg = now_seg; | |
1670 | hi_fixup->next = m32r_hi_fixup_list; | |
ab3e48dc | 1671 | |
252b5132 RH |
1672 | m32r_hi_fixup_list = hi_fixup; |
1673 | } | |
1674 | ||
1675 | /* Called while parsing an instruction to create a fixup. | |
1676 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1677 | ||
1678 | fixS * | |
1679 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ab3e48dc KH |
1680 | fragS *frag; |
1681 | int where; | |
1682 | const CGEN_INSN *insn; | |
1683 | int length; | |
1684 | const CGEN_OPERAND *operand; | |
1685 | int opinfo; | |
1686 | expressionS *exp; | |
252b5132 | 1687 | { |
ab3e48dc KH |
1688 | fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, |
1689 | operand, opinfo, exp); | |
252b5132 RH |
1690 | |
1691 | switch (operand->type) | |
1692 | { | |
ab3e48dc | 1693 | case M32R_OPERAND_HI16: |
252b5132 RH |
1694 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1695 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1696 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1697 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); | |
1698 | break; | |
ab3e48dc KH |
1699 | default: |
1700 | /* Avoid -Wall warning */ | |
252b5132 RH |
1701 | break; |
1702 | } | |
1703 | ||
1704 | return fixP; | |
1705 | } | |
1706 | ||
1707 | /* Return BFD reloc type from opinfo field in a fixS. | |
1708 | It's tricky using fx_r_type in m32r_frob_file because the values | |
1709 | are BFD_RELOC_UNUSED + operand number. */ | |
1710 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) | |
1711 | ||
1712 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
94f592af | 1713 | the corresponding LO16 reloc. This is called before md_apply_fix3 and |
252b5132 RH |
1714 | tc_gen_reloc. */ |
1715 | ||
1716 | void | |
1717 | m32r_frob_file () | |
1718 | { | |
ab3e48dc | 1719 | struct m32r_hi_fixup *l; |
252b5132 RH |
1720 | |
1721 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
1722 | { | |
ab3e48dc KH |
1723 | segment_info_type *seginfo; |
1724 | int pass; | |
252b5132 RH |
1725 | |
1726 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
1727 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
1728 | ||
1729 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
1730 | if (l->fixp->fx_next != NULL | |
1731 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
1732 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
1733 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
1734 | continue; | |
1735 | ||
1736 | /* Look through the fixups for this segment for a matching `low'. | |
1737 | When we find one, move the high/shigh just in front of it. We do | |
1738 | this in two passes. In the first pass, we try to find a | |
1739 | unique `low'. In the second pass, we permit multiple high's | |
1740 | relocs for a single `low'. */ | |
1741 | seginfo = seg_info (l->seg); | |
1742 | for (pass = 0; pass < 2; pass++) | |
1743 | { | |
ab3e48dc KH |
1744 | fixS *f; |
1745 | fixS *prev; | |
252b5132 RH |
1746 | |
1747 | prev = NULL; | |
1748 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
1749 | { | |
1750 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
1751 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
1752 | && f->fx_addsy == l->fixp->fx_addsy | |
1753 | && f->fx_offset == l->fixp->fx_offset | |
1754 | && (pass == 1 | |
1755 | || prev == NULL | |
1756 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
1757 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
1758 | || prev->fx_addsy != f->fx_addsy | |
ab3e48dc | 1759 | || prev->fx_offset != f->fx_offset)) |
252b5132 | 1760 | { |
ab3e48dc | 1761 | fixS **pf; |
252b5132 RH |
1762 | |
1763 | /* Move l->fixp before f. */ | |
1764 | for (pf = &seginfo->fix_root; | |
ab3e48dc KH |
1765 | *pf != l->fixp; |
1766 | pf = & (*pf)->fx_next) | |
1767 | assert (*pf != NULL); | |
252b5132 | 1768 | |
ab3e48dc | 1769 | *pf = l->fixp->fx_next; |
252b5132 RH |
1770 | |
1771 | l->fixp->fx_next = f; | |
1772 | if (prev == NULL) | |
1773 | seginfo->fix_root = l->fixp; | |
1774 | else | |
1775 | prev->fx_next = l->fixp; | |
1776 | ||
1777 | break; | |
1778 | } | |
1779 | ||
1780 | prev = f; | |
1781 | } | |
1782 | ||
1783 | if (f != NULL) | |
1784 | break; | |
1785 | ||
1786 | if (pass == 1 | |
1787 | && warn_unmatched_high) | |
1788 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
1789 | _("Unmatched high/shigh reloc")); | |
1790 | } | |
1791 | } | |
1792 | } | |
1793 | ||
1794 | /* See whether we need to force a relocation into the output file. | |
1795 | This is used to force out switch and PC relative relocations when | |
1796 | relaxing. */ | |
1797 | ||
1798 | int | |
1799 | m32r_force_relocation (fix) | |
ab3e48dc | 1800 | fixS *fix; |
252b5132 RH |
1801 | { |
1802 | if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
a161fe53 AM |
1803 | || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
1804 | || S_FORCE_RELOC (fix->fx_addsy)) | |
252b5132 RH |
1805 | return 1; |
1806 | ||
1807 | if (! m32r_relax) | |
1808 | return 0; | |
1809 | ||
ab3e48dc | 1810 | return fix->fx_pcrel; |
252b5132 RH |
1811 | } |
1812 | \f | |
1813 | /* Write a value out to the object file, using the appropriate endianness. */ | |
1814 | ||
1815 | void | |
1816 | md_number_to_chars (buf, val, n) | |
ab3e48dc | 1817 | char *buf; |
252b5132 | 1818 | valueT val; |
ab3e48dc | 1819 | int n; |
252b5132 RH |
1820 | { |
1821 | if (target_big_endian) | |
1822 | number_to_chars_bigendian (buf, val, n); | |
1823 | else | |
1824 | number_to_chars_littleendian (buf, val, n); | |
1825 | } | |
1826 | ||
ab3e48dc KH |
1827 | /* Turn a string in input_line_pointer into a floating point constant |
1828 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
1829 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
1830 | returned, or NULL on OK. */ | |
252b5132 | 1831 | |
ab3e48dc | 1832 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
1833 | #define MAX_LITTLENUMS 6 |
1834 | ||
1835 | char * | |
1836 | md_atof (type, litP, sizeP) | |
1837 | char type; | |
1838 | char *litP; | |
1839 | int *sizeP; | |
1840 | { | |
ab3e48dc KH |
1841 | int i; |
1842 | int prec; | |
1843 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1844 | char *t; | |
1845 | char *atof_ieee (); | |
252b5132 RH |
1846 | |
1847 | switch (type) | |
1848 | { | |
1849 | case 'f': | |
1850 | case 'F': | |
1851 | case 's': | |
1852 | case 'S': | |
1853 | prec = 2; | |
1854 | break; | |
1855 | ||
1856 | case 'd': | |
1857 | case 'D': | |
1858 | case 'r': | |
1859 | case 'R': | |
1860 | prec = 4; | |
1861 | break; | |
1862 | ||
ab3e48dc KH |
1863 | /* FIXME: Some targets allow other format chars for bigger sizes |
1864 | here. */ | |
252b5132 RH |
1865 | |
1866 | default: | |
ab3e48dc | 1867 | *sizeP = 0; |
252b5132 RH |
1868 | return _("Bad call to md_atof()"); |
1869 | } | |
1870 | ||
1871 | t = atof_ieee (input_line_pointer, type, words); | |
1872 | if (t) | |
1873 | input_line_pointer = t; | |
ab3e48dc | 1874 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
252b5132 RH |
1875 | |
1876 | if (target_big_endian) | |
1877 | { | |
1878 | for (i = 0; i < prec; i++) | |
1879 | { | |
1880 | md_number_to_chars (litP, (valueT) words[i], | |
1881 | sizeof (LITTLENUM_TYPE)); | |
1882 | litP += sizeof (LITTLENUM_TYPE); | |
1883 | } | |
1884 | } | |
1885 | else | |
1886 | { | |
1887 | for (i = prec - 1; i >= 0; i--) | |
1888 | { | |
1889 | md_number_to_chars (litP, (valueT) words[i], | |
1890 | sizeof (LITTLENUM_TYPE)); | |
1891 | litP += sizeof (LITTLENUM_TYPE); | |
1892 | } | |
1893 | } | |
ab3e48dc | 1894 | |
252b5132 RH |
1895 | return 0; |
1896 | } | |
1897 | ||
1898 | void | |
1899 | m32r_elf_section_change_hook () | |
1900 | { | |
1901 | /* If we have reached the end of a section and we have just emitted a | |
1902 | 16 bit insn, then emit a nop to make sure that the section ends on | |
1903 | a 32 bit boundary. */ | |
ab3e48dc | 1904 | |
252b5132 RH |
1905 | if (prev_insn.insn || seen_relaxable_p) |
1906 | (void) m32r_fill_insn (0); | |
1907 | } | |
1908 | ||
60bcf0fa | 1909 | /* Return true if can adjust the reloc to be relative to its section |
ab3e48dc | 1910 | (such as .data) instead of relative to some symbol. */ |
60bcf0fa | 1911 | |
252b5132 RH |
1912 | boolean |
1913 | m32r_fix_adjustable (fixP) | |
1914 | fixS *fixP; | |
1915 | { | |
5c86cbc7 | 1916 | bfd_reloc_code_real_type reloc_type; |
ab3e48dc | 1917 | |
5c86cbc7 CM |
1918 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
1919 | { | |
1920 | const CGEN_INSN *insn = NULL; | |
1921 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; | |
ab3e48dc KH |
1922 | const CGEN_OPERAND *operand = |
1923 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); | |
5c86cbc7 CM |
1924 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
1925 | } | |
1926 | else | |
1927 | reloc_type = fixP->fx_r_type; | |
1928 | ||
ab3e48dc | 1929 | /* We need the symbol name for the VTABLE entries. */ |
5c86cbc7 CM |
1930 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
1931 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
1932 | return 0; |
1933 | ||
1934 | return 1; | |
1935 | } |