Commit | Line | Data |
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4bf4a882 | 1 | /* tc-m32r.c -- Assembler for the Renesas M32R. |
aef6203b | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
ab3e48dc | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
ab3e48dc | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "symcat.h" |
27 | #include "opcodes/m32r-desc.h" | |
28 | #include "opcodes/m32r-opc.h" | |
29 | #include "cgen.h" | |
88845958 | 30 | #include "elf/m32r.h" |
252b5132 RH |
31 | |
32 | /* Linked list of symbols that are debugging symbols to be defined as the | |
33 | beginning of the current instruction. */ | |
34 | typedef struct sym_link | |
35 | { | |
36 | struct sym_link *next; | |
ab3e48dc | 37 | symbolS *symbol; |
252b5132 RH |
38 | } sym_linkS; |
39 | ||
ab3e48dc KH |
40 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
41 | ||
252b5132 RH |
42 | /* Structure to hold all of the different components describing |
43 | an individual instruction. */ | |
44 | typedef struct | |
45 | { | |
ab3e48dc KH |
46 | const CGEN_INSN *insn; |
47 | const CGEN_INSN *orig_insn; | |
48 | CGEN_FIELDS fields; | |
252b5132 | 49 | #if CGEN_INT_INSN_P |
ab3e48dc | 50 | CGEN_INSN_INT buffer[1]; |
252b5132 RH |
51 | #define INSN_VALUE(buf) (*(buf)) |
52 | #else | |
ab3e48dc | 53 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
252b5132 RH |
54 | #define INSN_VALUE(buf) (buf) |
55 | #endif | |
ab3e48dc KH |
56 | char *addr; |
57 | fragS *frag; | |
58 | int num_fixups; | |
59 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; | |
60 | int indices[MAX_OPERAND_INSTANCES]; | |
61 | sym_linkS *debug_sym_link; | |
252b5132 RH |
62 | } |
63 | m32r_insn; | |
64 | ||
65 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit | |
66 | boundary (i.e. was the first of two 16 bit insns). */ | |
ab3e48dc | 67 | static m32r_insn prev_insn; |
252b5132 RH |
68 | |
69 | /* Non-zero if we've seen a relaxable insn since the last 32 bit | |
70 | alignment request. */ | |
71 | static int seen_relaxable_p = 0; | |
72 | ||
6edf0760 NC |
73 | /* Non-zero if we are generating PIC code. */ |
74 | int pic_code; | |
75 | ||
252b5132 RH |
76 | /* Non-zero if -relax specified, in which case sufficient relocs are output |
77 | for the linker to do relaxing. | |
78 | We do simple forms of relaxing internally, but they are always done. | |
79 | This flag does not apply to them. */ | |
80 | static int m32r_relax; | |
81 | ||
252b5132 RH |
82 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. |
83 | Each high/shigh reloc must be paired with it's low cousin in order to | |
84 | properly calculate the addend in a relocatable link (since there is a | |
85 | potential carry from the low to the high/shigh). | |
86 | This option is off by default though for user-written assembler code it | |
87 | might make sense to make the default be on (i.e. have gcc pass a flag | |
88 | to turn it off). This warning must not be on for GCC created code as | |
89 | optimization may delete the low but not the high/shigh (at least we | |
90 | shouldn't assume or require it to). */ | |
91 | static int warn_unmatched_high = 0; | |
92 | ||
88845958 NC |
93 | /* 1 if -m32rx has been specified, in which case support for |
94 | the extended M32RX instruction set should be enabled. | |
95 | 2 if -m32r2 has been specified, in which case support for | |
96 | the extended M32R2 instruction set should be enabled. */ | |
97 | static int enable_m32rx = 0; /* Default to M32R. */ | |
925c058e DE |
98 | |
99 | /* Non-zero if -m32rx -hidden has been specified, in which case support for | |
100 | the special M32RX instruction set should be enabled. */ | |
101 | static int enable_special = 0; | |
102 | ||
88845958 NC |
103 | /* Non-zero if -bitinst has been specified, in which case support |
104 | for extended M32R bit-field instruction set should be enabled. */ | |
bd337dde | 105 | static int enable_special_m32r = 1; |
88845958 NC |
106 | |
107 | /* Non-zero if -float has been specified, in which case support for | |
108 | extended M32R floating point instruction set should be enabled. */ | |
109 | static int enable_special_float = 0; | |
110 | ||
925c058e DE |
111 | /* Non-zero if the programmer should be warned when an explicit parallel |
112 | instruction might have constraint violations. */ | |
113 | static int warn_explicit_parallel_conflicts = 1; | |
114 | ||
b145f546 NC |
115 | /* Non-zero if the programmer should not receive any messages about |
116 | parallel instruction with potential or real constraint violations. | |
117 | The ability to suppress these messages is intended only for hardware | |
118 | vendors testing the chip. It superceedes | |
119 | warn_explicit_parallel_conflicts. */ | |
120 | static int ignore_parallel_conflicts = 0; | |
88845958 | 121 | |
925c058e | 122 | /* Non-zero if insns can be made parallel. */ |
88845958 NC |
123 | static int use_parallel = 1; |
124 | ||
125 | /* Non-zero if optimizations should be performed. */ | |
925c058e | 126 | static int optimize; |
252b5132 | 127 | |
88845958 NC |
128 | /* m32r er_flags. */ |
129 | static int m32r_flags = 0; | |
130 | ||
ab3e48dc | 131 | /* Stuff for .scomm symbols. */ |
252b5132 RH |
132 | static segT sbss_section; |
133 | static asection scom_section; | |
134 | static asymbol scom_symbol; | |
135 | ||
136 | const char comment_chars[] = ";"; | |
137 | const char line_comment_chars[] = "#"; | |
88845958 | 138 | const char line_separator_chars[] = "!"; |
252b5132 RH |
139 | const char EXP_CHARS[] = "eE"; |
140 | const char FLT_CHARS[] = "dD"; | |
141 | ||
142 | /* Relocations against symbols are done in two | |
143 | parts, with a HI relocation and a LO relocation. Each relocation | |
144 | has only 16 bits of space to store an addend. This means that in | |
145 | order for the linker to handle carries correctly, it must be able | |
146 | to locate both the HI and the LO relocation. This means that the | |
147 | relocations must appear in order in the relocation table. | |
148 | ||
149 | In order to implement this, we keep track of each unmatched HI | |
150 | relocation. We then sort them so that they immediately precede the | |
82efde3a | 151 | corresponding LO relocation. */ |
252b5132 RH |
152 | |
153 | struct m32r_hi_fixup | |
154 | { | |
ab3e48dc KH |
155 | /* Next HI fixup. */ |
156 | struct m32r_hi_fixup *next; | |
157 | ||
158 | /* This fixup. */ | |
159 | fixS *fixp; | |
252b5132 | 160 | |
ab3e48dc KH |
161 | /* The section this fixup is in. */ |
162 | segT seg; | |
252b5132 RH |
163 | }; |
164 | ||
165 | /* The list of unmatched HI relocs. */ | |
166 | ||
ab3e48dc | 167 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
252b5132 | 168 | \f |
88845958 NC |
169 | struct { |
170 | enum bfd_architecture bfd_mach; | |
171 | int mach_flags; | |
172 | } mach_table[] = | |
173 | { | |
174 | { bfd_mach_m32r, (1<<MACH_M32R) }, | |
175 | { bfd_mach_m32rx, (1<<MACH_M32RX) }, | |
176 | { bfd_mach_m32r2, (1<<MACH_M32R2) } | |
177 | }; | |
178 | ||
179 | static void allow_m32rx (int); | |
78a0c6fb | 180 | |
925c058e | 181 | static void |
88845958 | 182 | allow_m32rx (int on) |
925c058e DE |
183 | { |
184 | enable_m32rx = on; | |
185 | ||
186 | if (stdoutput != NULL) | |
88845958 NC |
187 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach); |
188 | ||
189 | if (gas_cgen_cpu_desc != NULL) | |
190 | gas_cgen_cpu_desc->machs = mach_table[on].mach_flags; | |
925c058e | 191 | } |
252b5132 | 192 | \f |
6edf0760 | 193 | #define M32R_SHORTOPTS "O::K:" |
ab3e48dc KH |
194 | |
195 | const char *md_shortopts = M32R_SHORTOPTS; | |
252b5132 RH |
196 | |
197 | struct option md_longopts[] = | |
198 | { | |
b145f546 NC |
199 | #define OPTION_M32R (OPTION_MD_BASE) |
200 | #define OPTION_M32RX (OPTION_M32R + 1) | |
201 | #define OPTION_M32R2 (OPTION_M32RX + 1) | |
202 | #define OPTION_BIG (OPTION_M32R2 + 1) | |
203 | #define OPTION_LITTLE (OPTION_BIG + 1) | |
204 | #define OPTION_PARALLEL (OPTION_LITTLE + 1) | |
205 | #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1) | |
206 | #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1) | |
207 | #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) | |
208 | #define OPTION_IGNORE_PARALLEL (OPTION_NO_WARN_PARALLEL + 1) | |
209 | #define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1) | |
210 | #define OPTION_SPECIAL (OPTION_NO_IGNORE_PARALLEL + 1) | |
211 | #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1) | |
bd337dde NC |
212 | #define OPTION_NO_SPECIAL_M32R (OPTION_SPECIAL_M32R + 1) |
213 | #define OPTION_SPECIAL_FLOAT (OPTION_NO_SPECIAL_M32R + 1) | |
b145f546 NC |
214 | #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1) |
215 | #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) | |
8ad9e709 | 216 | {"m32r", no_argument, NULL, OPTION_M32R}, |
925c058e | 217 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
88845958 NC |
218 | {"m32r2", no_argument, NULL, OPTION_M32R2}, |
219 | {"big", no_argument, NULL, OPTION_BIG}, | |
220 | {"little", no_argument, NULL, OPTION_LITTLE}, | |
221 | {"EB", no_argument, NULL, OPTION_BIG}, | |
222 | {"EL", no_argument, NULL, OPTION_LITTLE}, | |
223 | {"parallel", no_argument, NULL, OPTION_PARALLEL}, | |
224 | {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL}, | |
925c058e DE |
225 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
226 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, | |
925c058e DE |
227 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
228 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, | |
b145f546 NC |
229 | {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL}, |
230 | {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL}, | |
231 | {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, | |
232 | {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, | |
925c058e | 233 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
88845958 | 234 | {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R}, |
bd337dde | 235 | {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R}, |
88845958 | 236 | {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT}, |
252b5132 | 237 | /* Sigh. I guess all warnings must now have both variants. */ |
2f3519a2 NC |
238 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
239 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, | |
d3388653 NC |
240 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
241 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, | |
252b5132 RH |
242 | {NULL, no_argument, NULL, 0} |
243 | }; | |
ab3e48dc | 244 | |
252b5132 RH |
245 | size_t md_longopts_size = sizeof (md_longopts); |
246 | ||
88845958 NC |
247 | static void little (int); |
248 | static int parallel (void); | |
249 | ||
250 | static void | |
251 | little (int on) | |
252 | { | |
253 | target_big_endian = ! on; | |
254 | } | |
255 | ||
256 | /* Use parallel execution. */ | |
257 | ||
258 | static int | |
259 | parallel (void) | |
260 | { | |
261 | if (! enable_m32rx) | |
262 | return 0; | |
263 | ||
264 | if (use_parallel == 1) | |
265 | return 1; | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
252b5132 RH |
270 | int |
271 | md_parse_option (c, arg) | |
ab3e48dc | 272 | int c; |
78a0c6fb | 273 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
274 | { |
275 | switch (c) | |
276 | { | |
925c058e DE |
277 | case 'O': |
278 | optimize = 1; | |
88845958 | 279 | use_parallel = 1; |
925c058e DE |
280 | break; |
281 | ||
8ad9e709 NC |
282 | case OPTION_M32R: |
283 | allow_m32rx (0); | |
284 | break; | |
ab3e48dc | 285 | |
925c058e DE |
286 | case OPTION_M32RX: |
287 | allow_m32rx (1); | |
288 | break; | |
ab3e48dc | 289 | |
88845958 NC |
290 | case OPTION_M32R2: |
291 | allow_m32rx (2); | |
292 | enable_special = 1; | |
293 | enable_special_m32r = 1; | |
294 | break; | |
295 | ||
296 | case OPTION_BIG: | |
297 | target_big_endian = 1; | |
298 | break; | |
299 | ||
300 | case OPTION_LITTLE: | |
301 | target_big_endian = 0; | |
302 | break; | |
303 | ||
304 | case OPTION_PARALLEL: | |
305 | use_parallel = 1; | |
306 | break; | |
307 | ||
308 | case OPTION_NO_PARALLEL: | |
309 | use_parallel = 0; | |
310 | break; | |
311 | ||
925c058e DE |
312 | case OPTION_WARN_PARALLEL: |
313 | warn_explicit_parallel_conflicts = 1; | |
314 | break; | |
ab3e48dc | 315 | |
925c058e | 316 | case OPTION_NO_WARN_PARALLEL: |
88845958 | 317 | warn_explicit_parallel_conflicts = 0; |
88845958 NC |
318 | break; |
319 | ||
b145f546 NC |
320 | case OPTION_IGNORE_PARALLEL: |
321 | ignore_parallel_conflicts = 1; | |
88845958 NC |
322 | break; |
323 | ||
b145f546 NC |
324 | case OPTION_NO_IGNORE_PARALLEL: |
325 | ignore_parallel_conflicts = 0; | |
925c058e DE |
326 | break; |
327 | ||
328 | case OPTION_SPECIAL: | |
329 | if (enable_m32rx) | |
330 | enable_special = 1; | |
331 | else | |
332 | { | |
333 | /* Pretend that we do not recognise this option. */ | |
334 | as_bad (_("Unrecognised option: -hidden")); | |
335 | return 0; | |
336 | } | |
337 | break; | |
252b5132 | 338 | |
88845958 NC |
339 | case OPTION_SPECIAL_M32R: |
340 | enable_special_m32r = 1; | |
341 | break; | |
342 | ||
bd337dde NC |
343 | case OPTION_NO_SPECIAL_M32R: |
344 | enable_special_m32r = 0; | |
345 | break; | |
346 | ||
88845958 NC |
347 | case OPTION_SPECIAL_FLOAT: |
348 | enable_special_float = 1; | |
349 | break; | |
350 | ||
252b5132 RH |
351 | case OPTION_WARN_UNMATCHED: |
352 | warn_unmatched_high = 1; | |
353 | break; | |
354 | ||
355 | case OPTION_NO_WARN_UNMATCHED: | |
356 | warn_unmatched_high = 0; | |
357 | break; | |
ab3e48dc | 358 | |
6edf0760 NC |
359 | case 'K': |
360 | if (strcmp (arg, "PIC") != 0) | |
361 | as_warn (_("Unrecognized option following -K")); | |
362 | else | |
363 | pic_code = 1; | |
364 | break; | |
365 | ||
252b5132 RH |
366 | default: |
367 | return 0; | |
368 | } | |
ab3e48dc | 369 | |
252b5132 RH |
370 | return 1; |
371 | } | |
372 | ||
373 | void | |
374 | md_show_usage (stream) | |
ab3e48dc | 375 | FILE *stream; |
252b5132 RH |
376 | { |
377 | fprintf (stream, _(" M32R specific command line options:\n")); | |
378 | ||
ded0aeb7 NC |
379 | fprintf (stream, _("\ |
380 | -m32r disable support for the m32rx instruction set\n")); | |
925c058e DE |
381 | fprintf (stream, _("\ |
382 | -m32rx support the extended m32rx instruction set\n")); | |
383 | fprintf (stream, _("\ | |
88845958 NC |
384 | -m32r2 support the extended m32r2 instruction set\n")); |
385 | fprintf (stream, _("\ | |
386 | -EL,-little produce little endian code and data\n")); | |
387 | fprintf (stream, _("\ | |
388 | -EB,-big produce big endian code and data\n")); | |
389 | fprintf (stream, _("\ | |
390 | -parallel try to combine instructions in parallel\n")); | |
391 | fprintf (stream, _("\ | |
392 | -no-parallel disable -parallel\n")); | |
393 | fprintf (stream, _("\ | |
bd337dde NC |
394 | -no-bitinst disallow the M32R2's extended bit-field instructions\n")); |
395 | fprintf (stream, _("\ | |
88845958 | 396 | -O try to optimize code. Implies -parallel\n")); |
925c058e DE |
397 | |
398 | fprintf (stream, _("\ | |
399 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); | |
400 | fprintf (stream, _("\ | |
b145f546 | 401 | might violate contraints\n")); |
925c058e DE |
402 | fprintf (stream, _("\ |
403 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); | |
404 | fprintf (stream, _("\ | |
b145f546 | 405 | instructions might violate contraints\n")); |
925c058e DE |
406 | fprintf (stream, _("\ |
407 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); | |
408 | fprintf (stream, _("\ | |
409 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); | |
88845958 | 410 | fprintf (stream, _("\ |
b145f546 | 411 | -ignore-parallel-conflicts do not check parallel instructions\n")); |
88845958 | 412 | fprintf (stream, _("\ |
b145f546 | 413 | fo contraint violations\n")); |
88845958 | 414 | fprintf (stream, _("\ |
b145f546 | 415 | -no-ignore-parallel-conflicts check parallel instructions for\n")); |
88845958 | 416 | fprintf (stream, _("\ |
b145f546 | 417 | contraint violations\n")); |
88845958 | 418 | fprintf (stream, _("\ |
b145f546 | 419 | -Ip synonym for -ignore-parallel-conflicts\n")); |
88845958 | 420 | fprintf (stream, _("\ |
b145f546 | 421 | -nIp synonym for -no-ignore-parallel-conflicts\n")); |
252b5132 RH |
422 | |
423 | fprintf (stream, _("\ | |
424 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); | |
425 | fprintf (stream, _("\ | |
426 | -no-warn-unmatched-high do not warn about missing low relocs\n")); | |
427 | fprintf (stream, _("\ | |
428 | -Wuh synonym for -warn-unmatched-high\n")); | |
429 | fprintf (stream, _("\ | |
430 | -Wnuh synonym for -no-warn-unmatched-high\n")); | |
431 | ||
6edf0760 NC |
432 | fprintf (stream, _("\ |
433 | -KPIC generate PIC\n")); | |
ab3e48dc | 434 | } |
252b5132 RH |
435 | |
436 | static void fill_insn PARAMS ((int)); | |
437 | static void m32r_scomm PARAMS ((int)); | |
438 | static void debug_sym PARAMS ((int)); | |
439 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); | |
440 | ||
441 | /* Set by md_assemble for use by m32r_fill_insn. */ | |
442 | static subsegT prev_subseg; | |
443 | static segT prev_seg; | |
444 | ||
445 | /* The target specific pseudo-ops which we support. */ | |
446 | const pseudo_typeS md_pseudo_table[] = | |
447 | { | |
448 | { "word", cons, 4 }, | |
449 | { "fillinsn", fill_insn, 0 }, | |
450 | { "scomm", m32r_scomm, 0 }, | |
451 | { "debugsym", debug_sym, 0 }, | |
925c058e DE |
452 | { "m32r", allow_m32rx, 0 }, |
453 | { "m32rx", allow_m32rx, 1 }, | |
88845958 NC |
454 | { "m32r2", allow_m32rx, 2 }, |
455 | { "little", little, 1 }, | |
456 | { "big", little, 0 }, | |
252b5132 RH |
457 | { NULL, NULL, 0 } |
458 | }; | |
459 | ||
097f809a NC |
460 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" |
461 | symbolS * GOT_symbol; | |
462 | ||
463 | static inline int | |
464 | m32r_PIC_related_p (symbolS *sym) | |
465 | { | |
466 | expressionS *exp; | |
467 | ||
468 | if (! sym) | |
469 | return 0; | |
470 | ||
471 | if (sym == GOT_symbol) | |
472 | return 1; | |
473 | ||
474 | exp = symbol_get_value_expression (sym); | |
475 | ||
476 | return (exp->X_op == O_PIC_reloc | |
477 | || exp->X_md == BFD_RELOC_M32R_26_PLTREL | |
478 | || m32r_PIC_related_p (exp->X_add_symbol) | |
479 | || m32r_PIC_related_p (exp->X_op_symbol)); | |
480 | } | |
481 | ||
482 | static inline int | |
483 | m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p) | |
484 | { | |
485 | expressionS *exp = main_exp; | |
486 | ||
487 | if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol)) | |
488 | return 1; | |
489 | ||
490 | if (exp->X_op == O_symbol && exp->X_add_symbol) | |
491 | { | |
492 | if (exp->X_add_symbol == GOT_symbol) | |
493 | { | |
494 | *r_type_p = BFD_RELOC_M32R_GOTPC24; | |
495 | return 0; | |
496 | } | |
497 | } | |
498 | else if (exp->X_op == O_add) | |
499 | { | |
500 | exp = symbol_get_value_expression (exp->X_add_symbol); | |
501 | if (! exp) | |
502 | return 0; | |
503 | } | |
504 | ||
505 | if (exp->X_op == O_PIC_reloc || exp->X_md != BFD_RELOC_UNUSED) | |
506 | { | |
507 | *r_type_p = exp->X_md; | |
508 | if (exp == main_exp) | |
509 | exp->X_op = O_symbol; | |
510 | else | |
511 | { | |
512 | main_exp->X_add_symbol = exp->X_add_symbol; | |
513 | main_exp->X_add_number += exp->X_add_number; | |
514 | } | |
515 | } | |
516 | else | |
517 | return (m32r_PIC_related_p (exp->X_add_symbol) | |
518 | || m32r_PIC_related_p (exp->X_op_symbol)); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
252b5132 | 523 | /* FIXME: Should be machine generated. */ |
88845958 | 524 | #define NOP_INSN 0x7000 |
ab3e48dc | 525 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
252b5132 | 526 | |
0a9ef439 RH |
527 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
528 | of an rs_align_code fragment. */ | |
252b5132 | 529 | |
0a9ef439 RH |
530 | void |
531 | m32r_handle_align (fragp) | |
015c05c1 | 532 | fragS *fragp; |
252b5132 | 533 | { |
0a9ef439 RH |
534 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
535 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; | |
252b5132 | 536 | |
0a9ef439 RH |
537 | int bytes, fix; |
538 | char *p; | |
ab3e48dc | 539 | |
0a9ef439 RH |
540 | if (fragp->fr_type != rs_align_code) |
541 | return; | |
542 | ||
543 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
544 | p = fragp->fr_literal + fragp->fr_fix; | |
545 | fix = 0; | |
546 | ||
547 | if (bytes & 1) | |
548 | { | |
549 | fix = 1; | |
550 | *p++ = 0; | |
551 | bytes--; | |
252b5132 RH |
552 | } |
553 | ||
0a9ef439 RH |
554 | if (bytes & 2) |
555 | { | |
556 | memcpy (p, nop_pattern, 2); | |
557 | p += 2; | |
558 | bytes -= 2; | |
559 | fix += 2; | |
560 | } | |
561 | ||
562 | memcpy (p, multi_nop_pattern, 4); | |
563 | ||
564 | fragp->fr_fix += fix; | |
565 | fragp->fr_var = 4; | |
252b5132 RH |
566 | } |
567 | ||
568 | /* If the last instruction was the first of 2 16 bit insns, | |
569 | output a nop to move the PC to a 32 bit boundary. | |
570 | ||
571 | This is done via an alignment specification since branch relaxing | |
572 | may make it unnecessary. | |
573 | ||
574 | Internally, we need to output one of these each time a 32 bit insn is | |
575 | seen after an insn that is relaxable. */ | |
576 | ||
577 | static void | |
578 | fill_insn (ignore) | |
78a0c6fb | 579 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 580 | { |
0a9ef439 | 581 | frag_align_code (2, 0); |
252b5132 RH |
582 | prev_insn.insn = NULL; |
583 | seen_relaxable_p = 0; | |
584 | } | |
585 | ||
586 | /* Record the symbol so that when we output the insn, we can create | |
587 | a symbol that is at the start of the instruction. This is used | |
588 | to emit the label for the start of a breakpoint without causing | |
589 | the assembler to emit a NOP if the previous instruction was a | |
590 | 16 bit instruction. */ | |
591 | ||
592 | static void | |
593 | debug_sym (ignore) | |
78a0c6fb | 594 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
595 | { |
596 | register char *name; | |
597 | register char delim; | |
598 | register char *end_name; | |
599 | register symbolS *symbolP; | |
600 | register sym_linkS *link; | |
601 | ||
602 | name = input_line_pointer; | |
603 | delim = get_symbol_end (); | |
604 | end_name = input_line_pointer; | |
ab3e48dc | 605 | |
252b5132 RH |
606 | if ((symbolP = symbol_find (name)) == NULL |
607 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
608 | { | |
609 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
610 | } | |
611 | ||
612 | symbol_table_insert (symbolP); | |
6edf0760 NC |
613 | if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section |
614 | || S_IS_EXTERNAL (symbolP) | |
615 | || S_IS_WEAK (symbolP))) | |
252b5132 RH |
616 | /* xgettext:c-format */ |
617 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
618 | ||
619 | else | |
620 | { | |
621 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); | |
622 | link->symbol = symbolP; | |
623 | link->next = debug_sym_link; | |
624 | debug_sym_link = link; | |
f412ead8 | 625 | symbol_get_obj (symbolP)->local = 1; |
252b5132 RH |
626 | } |
627 | ||
628 | *end_name = delim; | |
629 | demand_empty_rest_of_line (); | |
630 | } | |
631 | ||
632 | /* Second pass to expanding the debug symbols, go through linked | |
633 | list of symbols and reassign the address. */ | |
634 | ||
635 | static void | |
636 | expand_debug_syms (syms, align) | |
637 | sym_linkS *syms; | |
638 | int align; | |
639 | { | |
640 | char *save_input_line = input_line_pointer; | |
641 | sym_linkS *next_syms; | |
642 | ||
643 | if (!syms) | |
644 | return; | |
645 | ||
a8150a88 | 646 | (void) frag_align_code (align, 0); |
ab3e48dc | 647 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
252b5132 RH |
648 | { |
649 | symbolS *symbolP = syms->symbol; | |
650 | next_syms = syms->next; | |
651 | input_line_pointer = ".\n"; | |
652 | pseudo_set (symbolP); | |
ab3e48dc | 653 | free ((char *) syms); |
252b5132 RH |
654 | } |
655 | ||
656 | input_line_pointer = save_input_line; | |
657 | } | |
658 | ||
88845958 NC |
659 | void |
660 | m32r_flush_pending_output() | |
661 | { | |
662 | if (debug_sym_link) | |
663 | { | |
664 | expand_debug_syms (debug_sym_link, 1); | |
665 | debug_sym_link = (sym_linkS *) 0; | |
666 | } | |
667 | } | |
668 | ||
252b5132 RH |
669 | /* Cover function to fill_insn called after a label and at end of assembly. |
670 | The result is always 1: we're called in a conditional to see if the | |
671 | current line is a label. */ | |
672 | ||
673 | int | |
674 | m32r_fill_insn (done) | |
675 | int done; | |
676 | { | |
677 | if (prev_seg != NULL) | |
678 | { | |
ab3e48dc | 679 | segT seg = now_seg; |
252b5132 RH |
680 | subsegT subseg = now_subseg; |
681 | ||
682 | subseg_set (prev_seg, prev_subseg); | |
ab3e48dc | 683 | |
252b5132 RH |
684 | fill_insn (0); |
685 | ||
686 | subseg_set (seg, subseg); | |
687 | } | |
688 | ||
689 | if (done && debug_sym_link) | |
690 | { | |
691 | expand_debug_syms (debug_sym_link, 1); | |
ab3e48dc | 692 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
693 | } |
694 | ||
695 | return 1; | |
696 | } | |
697 | \f | |
88845958 NC |
698 | /* The default target format to use. */ |
699 | ||
700 | const char * | |
701 | m32r_target_format () | |
702 | { | |
703 | #ifdef TE_LINUX | |
704 | if (target_big_endian) | |
705 | return "elf32-m32r-linux"; | |
706 | else | |
707 | return "elf32-m32rle-linux"; | |
708 | #else | |
709 | if (target_big_endian) | |
710 | return "elf32-m32r"; | |
711 | else | |
712 | return "elf32-m32rle"; | |
713 | #endif | |
714 | } | |
715 | ||
252b5132 RH |
716 | void |
717 | md_begin () | |
718 | { | |
719 | flagword applicable; | |
ab3e48dc KH |
720 | segT seg; |
721 | subsegT subseg; | |
252b5132 RH |
722 | |
723 | /* Initialize the `cgen' interface. */ | |
ab3e48dc | 724 | |
252b5132 RH |
725 | /* Set the machine number and endian. */ |
726 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, | |
727 | CGEN_CPU_OPEN_ENDIAN, | |
88845958 NC |
728 | (target_big_endian ? |
729 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE), | |
252b5132 RH |
730 | CGEN_CPU_OPEN_END); |
731 | m32r_cgen_init_asm (gas_cgen_cpu_desc); | |
732 | ||
733 | /* The operand instance table is used during optimization to determine | |
734 | which insns can be executed in parallel. It is also used to give | |
735 | warnings regarding operand interference in parallel insns. */ | |
736 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); | |
737 | ||
738 | /* This is a callback from cgen to gas to parse operands. */ | |
739 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
740 | ||
252b5132 RH |
741 | /* Save the current subseg so we can restore it [it's the default one and |
742 | we don't want the initial section to be .sbss]. */ | |
743 | seg = now_seg; | |
744 | subseg = now_subseg; | |
745 | ||
746 | /* The sbss section is for local .scomm symbols. */ | |
747 | sbss_section = subseg_new (".sbss", 0); | |
ab3e48dc | 748 | |
252b5132 RH |
749 | /* This is copied from perform_an_assembly_pass. */ |
750 | applicable = bfd_applicable_section_flags (stdoutput); | |
751 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); | |
ab3e48dc | 752 | |
252b5132 RH |
753 | subseg_set (seg, subseg); |
754 | ||
755 | /* We must construct a fake section similar to bfd_com_section | |
756 | but with the name .scommon. */ | |
757 | scom_section = bfd_com_section; | |
758 | scom_section.name = ".scommon"; | |
ab3e48dc KH |
759 | scom_section.output_section = &scom_section; |
760 | scom_section.symbol = &scom_symbol; | |
761 | scom_section.symbol_ptr_ptr = &scom_section.symbol; | |
762 | scom_symbol = *bfd_com_section.symbol; | |
252b5132 | 763 | scom_symbol.name = ".scommon"; |
ab3e48dc | 764 | scom_symbol.section = &scom_section; |
252b5132 | 765 | |
925c058e | 766 | allow_m32rx (enable_m32rx); |
002de68b | 767 | |
07726851 | 768 | gas_cgen_initialize_saved_fixups_array (); |
925c058e DE |
769 | } |
770 | ||
771 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ | |
772 | ((operand)->hw_type == HW_H_COND \ | |
773 | || ((operand)->hw_type == HW_H_PSW) \ | |
774 | || ((operand)->hw_type == HW_H_CR \ | |
775 | && (indices [index] == 0 || indices [index] == 1))) | |
776 | ||
777 | /* Returns true if an output of instruction 'a' is referenced by an operand | |
778 | of instruction 'b'. If 'check_outputs' is true then b's outputs are | |
779 | checked, otherwise its inputs are examined. */ | |
780 | ||
78a0c6fb AM |
781 | static int first_writes_to_seconds_operands |
782 | PARAMS ((m32r_insn *, m32r_insn *, const int)); | |
783 | ||
925c058e DE |
784 | static int |
785 | first_writes_to_seconds_operands (a, b, check_outputs) | |
ab3e48dc KH |
786 | m32r_insn *a; |
787 | m32r_insn *b; | |
788 | const int check_outputs; | |
925c058e | 789 | { |
ab3e48dc KH |
790 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
791 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); | |
925c058e DE |
792 | int a_index; |
793 | ||
b145f546 NC |
794 | if (ignore_parallel_conflicts) |
795 | return 0; | |
796 | ||
925c058e DE |
797 | /* If at least one of the instructions takes no operands, then there is |
798 | nothing to check. There really are instructions without operands, | |
799 | eg 'nop'. */ | |
800 | if (a_operands == NULL || b_ops == NULL) | |
801 | return 0; | |
ab3e48dc | 802 | |
925c058e DE |
803 | /* Scan the operand list of 'a' looking for an output operand. */ |
804 | for (a_index = 0; | |
805 | a_operands->type != CGEN_OPINST_END; | |
806 | a_index ++, a_operands ++) | |
807 | { | |
808 | if (a_operands->type == CGEN_OPINST_OUTPUT) | |
809 | { | |
810 | int b_index; | |
ab3e48dc | 811 | const CGEN_OPINST *b_operands = b_ops; |
925c058e DE |
812 | |
813 | /* Special Case: | |
814 | The Condition bit 'C' is a shadow of the CBR register (control | |
815 | register 1) and also a shadow of bit 31 of the program status | |
816 | word (control register 0). For now this is handled here, rather | |
ab3e48dc KH |
817 | than by cgen.... */ |
818 | ||
925c058e DE |
819 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
820 | { | |
821 | /* Scan operand list of 'b' looking for another reference to the | |
822 | condition bit, which goes in the right direction. */ | |
823 | for (b_index = 0; | |
824 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 825 | b_index++, b_operands++) |
925c058e DE |
826 | { |
827 | if ((b_operands->type | |
828 | == (check_outputs | |
829 | ? CGEN_OPINST_OUTPUT | |
830 | : CGEN_OPINST_INPUT)) | |
831 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) | |
832 | return 1; | |
833 | } | |
834 | } | |
835 | else | |
836 | { | |
837 | /* Scan operand list of 'b' looking for an operand that | |
838 | references the same hardware element, and which goes in the | |
839 | right direction. */ | |
840 | for (b_index = 0; | |
841 | b_operands->type != CGEN_OPINST_END; | |
ab3e48dc | 842 | b_index++, b_operands++) |
925c058e DE |
843 | { |
844 | if ((b_operands->type | |
845 | == (check_outputs | |
846 | ? CGEN_OPINST_OUTPUT | |
847 | : CGEN_OPINST_INPUT)) | |
848 | && (b_operands->hw_type == a_operands->hw_type) | |
ab3e48dc | 849 | && (a->indices[a_index] == b->indices[b_index])) |
925c058e DE |
850 | return 1; |
851 | } | |
852 | } | |
853 | } | |
854 | } | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | /* Returns true if the insn can (potentially) alter the program counter. */ | |
860 | ||
78a0c6fb AM |
861 | static int writes_to_pc PARAMS ((m32r_insn *)); |
862 | ||
925c058e DE |
863 | static int |
864 | writes_to_pc (a) | |
ab3e48dc | 865 | m32r_insn *a; |
925c058e | 866 | { |
925c058e DE |
867 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) |
868 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) | |
869 | return 1; | |
925c058e DE |
870 | return 0; |
871 | } | |
872 | ||
ab3e48dc KH |
873 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
874 | Otherwise return a pointer to an error message explaining why not. */ | |
925c058e | 875 | |
78a0c6fb AM |
876 | static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *)); |
877 | ||
925c058e DE |
878 | static const char * |
879 | can_make_parallel (a, b) | |
ab3e48dc KH |
880 | m32r_insn *a; |
881 | m32r_insn *b; | |
925c058e DE |
882 | { |
883 | PIPE_ATTR a_pipe; | |
884 | PIPE_ATTR b_pipe; | |
ab3e48dc | 885 | |
925c058e | 886 | /* Make sure the instructions are the right length. */ |
ab3e48dc KH |
887 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
888 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) | |
889 | abort (); | |
925c058e | 890 | |
b34976b6 | 891 | if (first_writes_to_seconds_operands (a, b, TRUE)) |
b145f546 | 892 | return _("instructions write to the same destination register."); |
ab3e48dc | 893 | |
925c058e DE |
894 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
895 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); | |
896 | ||
897 | /* Make sure that the instructions use the correct execution pipelines. */ | |
ab3e48dc | 898 | if (a_pipe == PIPE_NONE |
925c058e DE |
899 | || b_pipe == PIPE_NONE) |
900 | return _("Instructions do not use parallel execution pipelines."); | |
901 | ||
902 | /* Leave this test for last, since it is the only test that can | |
903 | go away if the instructions are swapped, and we want to make | |
904 | sure that any other errors are detected before this happens. */ | |
ab3e48dc | 905 | if (a_pipe == PIPE_S |
88845958 NC |
906 | || b_pipe == PIPE_O |
907 | || (b_pipe == PIPE_O_OS && (enable_m32rx != 2))) | |
925c058e | 908 | return _("Instructions share the same execution pipeline"); |
ab3e48dc | 909 | |
925c058e DE |
910 | return NULL; |
911 | } | |
912 | ||
913 | /* Force the top bit of the second 16-bit insn to be set. */ | |
914 | ||
78a0c6fb AM |
915 | static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR)); |
916 | ||
925c058e DE |
917 | static void |
918 | make_parallel (buffer) | |
919 | CGEN_INSN_BYTES_PTR buffer; | |
920 | { | |
921 | #if CGEN_INT_INSN_P | |
922 | *buffer |= 0x8000; | |
923 | #else | |
ab3e48dc | 924 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
925 | |= 0x80; |
926 | #endif | |
252b5132 RH |
927 | } |
928 | ||
925c058e | 929 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
252b5132 | 930 | |
78a0c6fb AM |
931 | static void target_make_parallel PARAMS ((char *)); |
932 | ||
925c058e DE |
933 | static void |
934 | target_make_parallel (buffer) | |
935 | char *buffer; | |
936 | { | |
ab3e48dc | 937 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
925c058e DE |
938 | |= 0x80; |
939 | } | |
940 | ||
941 | /* Assemble two instructions with an explicit parallel operation (||) or | |
942 | sequential operation (->). */ | |
943 | ||
78a0c6fb AM |
944 | static void assemble_two_insns PARAMS ((char *, char *, int)); |
945 | ||
925c058e DE |
946 | static void |
947 | assemble_two_insns (str, str2, parallel_p) | |
ab3e48dc KH |
948 | char *str; |
949 | char *str2; | |
950 | int parallel_p; | |
925c058e | 951 | { |
ab3e48dc | 952 | char *str3; |
925c058e DE |
953 | m32r_insn first; |
954 | m32r_insn second; | |
ab3e48dc KH |
955 | char *errmsg; |
956 | char save_str2 = *str2; | |
925c058e | 957 | |
67c1ffbe | 958 | /* Separate the two instructions. */ |
ab3e48dc | 959 | *str2 = 0; |
925c058e DE |
960 | |
961 | /* Make sure the two insns begin on a 32 bit boundary. | |
962 | This is also done for the serial case (foo -> bar), relaxing doesn't | |
963 | affect insns written like this. | |
964 | Note that we must always do this as we can't assume anything about | |
965 | whether we're currently on a 32 bit boundary or not. Relaxing may | |
966 | change this. */ | |
967 | fill_insn (0); | |
968 | ||
969 | first.debug_sym_link = debug_sym_link; | |
ab3e48dc | 970 | debug_sym_link = (sym_linkS *) 0; |
925c058e DE |
971 | |
972 | /* Parse the first instruction. */ | |
973 | if (! (first.insn = m32r_cgen_assemble_insn | |
974 | (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) | |
975 | { | |
976 | as_bad (errmsg); | |
977 | return; | |
978 | } | |
979 | ||
980 | /* Check it. */ | |
981 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) | |
982 | { | |
ab3e48dc | 983 | /* xgettext:c-format */ |
925c058e DE |
984 | as_bad (_("not a 16 bit instruction '%s'"), str); |
985 | return; | |
986 | } | |
88845958 NC |
987 | #ifdef E_M32R2_ARCH |
988 | else if ((enable_m32rx == 1) | |
989 | /* FIXME: Need standard macro to perform this test. */ | |
990 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
991 | & (1 << MACH_M32R2)) | |
992 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
993 | & (1 << MACH_M32RX))))) | |
994 | { | |
995 | /* xgettext:c-format */ | |
996 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
997 | return; | |
998 | } | |
999 | else if ((! enable_special | |
1000 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
1001 | || (! enable_special_m32r | |
1002 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R))) | |
1003 | #else | |
925c058e DE |
1004 | else if (! enable_special |
1005 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1006 | #endif |
925c058e | 1007 | { |
ab3e48dc | 1008 | /* xgettext:c-format */ |
925c058e DE |
1009 | as_bad (_("unknown instruction '%s'"), str); |
1010 | return; | |
1011 | } | |
1012 | else if (! enable_m32rx | |
ab3e48dc KH |
1013 | /* FIXME: Need standard macro to perform this test. */ |
1014 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1015 | == (1 << MACH_M32RX))) | |
925c058e | 1016 | { |
ab3e48dc | 1017 | /* xgettext:c-format */ |
925c058e DE |
1018 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1019 | return; | |
1020 | } | |
ab3e48dc | 1021 | |
925c058e | 1022 | /* Check to see if this is an allowable parallel insn. */ |
ab3e48dc KH |
1023 | if (parallel_p |
1024 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 1025 | { |
ab3e48dc | 1026 | /* xgettext:c-format */ |
925c058e DE |
1027 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
1028 | return; | |
1029 | } | |
ab3e48dc KH |
1030 | |
1031 | /* Restore the original assembly text, just in case it is needed. */ | |
1032 | *str2 = save_str2; | |
1033 | ||
1034 | /* Save the original string pointer. */ | |
1035 | str3 = str; | |
1036 | ||
1037 | /* Advanced past the parsed string. */ | |
1038 | str = str2 + 2; | |
1039 | ||
1040 | /* Remember the entire string in case it is needed for error | |
1041 | messages. */ | |
1042 | str2 = str3; | |
925c058e DE |
1043 | |
1044 | /* Convert the opcode to lower case. */ | |
1045 | { | |
1046 | char *s2 = str; | |
ab3e48dc | 1047 | |
3882b010 | 1048 | while (ISSPACE (*s2++)) |
925c058e DE |
1049 | continue; |
1050 | ||
1051 | --s2; | |
1052 | ||
3882b010 | 1053 | while (ISALNUM (*s2)) |
925c058e | 1054 | { |
3882b010 | 1055 | *s2 = TOLOWER (*s2); |
ab3e48dc | 1056 | s2++; |
925c058e DE |
1057 | } |
1058 | } | |
ab3e48dc KH |
1059 | |
1060 | /* Preserve any fixups that have been generated and reset the list | |
1061 | to empty. */ | |
002de68b | 1062 | gas_cgen_save_fixups (0); |
925c058e DE |
1063 | |
1064 | /* Get the indices of the operands of the instruction. */ | |
1065 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact | |
1066 | doesn't seem right. Perhaps allow passing fields like we do insn. */ | |
1067 | /* FIXME: ALIAS insns do not have operands, so we use this function | |
1068 | to find the equivalent insn and overwrite the value stored in our | |
1069 | structure. We still need the original insn, however, since this | |
1070 | may have certain attributes that are not present in the unaliased | |
1071 | version (eg relaxability). When aliases behave differently this | |
1072 | may have to change. */ | |
1073 | first.orig_insn = first.insn; | |
1074 | { | |
1075 | CGEN_FIELDS tmp_fields; | |
1076 | first.insn = cgen_lookup_get_insn_operands | |
1077 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, | |
1078 | first.indices, &tmp_fields); | |
1079 | } | |
ab3e48dc | 1080 | |
925c058e DE |
1081 | if (first.insn == NULL) |
1082 | as_fatal (_("internal error: lookup/get operands failed")); | |
1083 | ||
1084 | second.debug_sym_link = NULL; | |
1085 | ||
1086 | /* Parse the second instruction. */ | |
1087 | if (! (second.insn = m32r_cgen_assemble_insn | |
1088 | (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) | |
1089 | { | |
1090 | as_bad (errmsg); | |
1091 | return; | |
1092 | } | |
1093 | ||
1094 | /* Check it. */ | |
1095 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) | |
1096 | { | |
ab3e48dc | 1097 | /* xgettext:c-format */ |
925c058e DE |
1098 | as_bad (_("not a 16 bit instruction '%s'"), str); |
1099 | return; | |
1100 | } | |
88845958 NC |
1101 | #ifdef E_M32R2_ARCH |
1102 | else if ((enable_m32rx == 1) | |
1103 | /* FIXME: Need standard macro to perform this test. */ | |
1104 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1105 | & (1 << MACH_M32R2)) | |
1106 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) | |
1107 | & (1 << MACH_M32RX))))) | |
1108 | { | |
1109 | /* xgettext:c-format */ | |
1110 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1111 | return; | |
1112 | } | |
1113 | else if ((! enable_special | |
1114 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
1115 | || (! enable_special_m32r | |
1116 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))) | |
1117 | #else | |
925c058e DE |
1118 | else if (! enable_special |
1119 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1120 | #endif |
925c058e | 1121 | { |
ab3e48dc | 1122 | /* xgettext:c-format */ |
925c058e DE |
1123 | as_bad (_("unknown instruction '%s'"), str); |
1124 | return; | |
1125 | } | |
1126 | else if (! enable_m32rx | |
1127 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1128 | { | |
ab3e48dc | 1129 | /* xgettext:c-format */ |
925c058e DE |
1130 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1131 | return; | |
1132 | } | |
1133 | ||
1134 | /* Check to see if this is an allowable parallel insn. */ | |
ab3e48dc KH |
1135 | if (parallel_p |
1136 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) | |
925c058e | 1137 | { |
ab3e48dc | 1138 | /* xgettext:c-format */ |
925c058e DE |
1139 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
1140 | return; | |
1141 | } | |
ab3e48dc | 1142 | |
925c058e DE |
1143 | if (parallel_p && ! enable_m32rx) |
1144 | { | |
1145 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP | |
1146 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) | |
1147 | { | |
ab3e48dc | 1148 | /* xgettext:c-format */ |
925c058e DE |
1149 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
1150 | return; | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | /* Get the indices of the operands of the instruction. */ | |
1155 | second.orig_insn = second.insn; | |
1156 | { | |
1157 | CGEN_FIELDS tmp_fields; | |
1158 | second.insn = cgen_lookup_get_insn_operands | |
1159 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, | |
1160 | second.indices, &tmp_fields); | |
1161 | } | |
ab3e48dc | 1162 | |
925c058e DE |
1163 | if (second.insn == NULL) |
1164 | as_fatal (_("internal error: lookup/get operands failed")); | |
1165 | ||
1166 | /* We assume that if the first instruction writes to a register that is | |
1167 | read by the second instruction it is because the programmer intended | |
1168 | this to happen, (after all they have explicitly requested that these | |
1169 | two instructions be executed in parallel). Although if the global | |
1170 | variable warn_explicit_parallel_conflicts is true then we do generate | |
1171 | a warning message. Similarly we assume that parallel branch and jump | |
1172 | instructions are deliberate and should not produce errors. */ | |
ab3e48dc | 1173 | |
925c058e DE |
1174 | if (parallel_p && warn_explicit_parallel_conflicts) |
1175 | { | |
b34976b6 | 1176 | if (first_writes_to_seconds_operands (&first, &second, FALSE)) |
ab3e48dc | 1177 | /* xgettext:c-format */ |
b145f546 | 1178 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
ab3e48dc | 1179 | |
b34976b6 | 1180 | if (first_writes_to_seconds_operands (&second, &first, FALSE)) |
ab3e48dc | 1181 | /* xgettext:c-format */ |
b145f546 | 1182 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
925c058e | 1183 | } |
ab3e48dc | 1184 | |
925c058e | 1185 | if (!parallel_p |
ab3e48dc | 1186 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
925c058e DE |
1187 | { |
1188 | /* Get the fixups for the first instruction. */ | |
002de68b | 1189 | gas_cgen_swap_fixups (0); |
925c058e DE |
1190 | |
1191 | /* Write it out. */ | |
1192 | expand_debug_syms (first.debug_sym_link, 1); | |
1193 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc KH |
1194 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
1195 | ||
925c058e DE |
1196 | /* Force the top bit of the second insn to be set. */ |
1197 | if (parallel_p) | |
1198 | make_parallel (second.buffer); | |
1199 | ||
1200 | /* Get its fixups. */ | |
002de68b | 1201 | gas_cgen_restore_fixups (0); |
925c058e DE |
1202 | |
1203 | /* Write it out. */ | |
1204 | expand_debug_syms (second.debug_sym_link, 1); | |
1205 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc | 1206 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
925c058e DE |
1207 | } |
1208 | /* Try swapping the instructions to see if they work that way. */ | |
ab3e48dc | 1209 | else if (can_make_parallel (&second, &first) == NULL) |
925c058e DE |
1210 | { |
1211 | /* Write out the second instruction first. */ | |
1212 | expand_debug_syms (second.debug_sym_link, 1); | |
1213 | gas_cgen_finish_insn (second.orig_insn, second.buffer, | |
ab3e48dc KH |
1214 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
1215 | ||
925c058e DE |
1216 | /* Force the top bit of the first instruction to be set. */ |
1217 | make_parallel (first.buffer); | |
1218 | ||
1219 | /* Get the fixups for the first instruction. */ | |
002de68b | 1220 | gas_cgen_restore_fixups (0); |
925c058e DE |
1221 | |
1222 | /* Write out the first instruction. */ | |
1223 | expand_debug_syms (first.debug_sym_link, 1); | |
1224 | gas_cgen_finish_insn (first.orig_insn, first.buffer, | |
ab3e48dc | 1225 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
925c058e DE |
1226 | } |
1227 | else | |
1228 | { | |
1229 | as_bad ("'%s': %s", str2, errmsg); | |
1230 | return; | |
1231 | } | |
ab3e48dc | 1232 | |
88845958 NC |
1233 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL) |
1234 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) | |
1235 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; | |
1236 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R) | |
1237 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)) | |
1238 | m32r_flags |= E_M32R_HAS_BIT_INST; | |
1239 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT) | |
1240 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT)) | |
1241 | m32r_flags |= E_M32R_HAS_FLOAT_INST; | |
1242 | ||
925c058e DE |
1243 | /* Set these so m32r_fill_insn can use them. */ |
1244 | prev_seg = now_seg; | |
1245 | prev_subseg = now_subseg; | |
1246 | } | |
252b5132 RH |
1247 | |
1248 | void | |
1249 | md_assemble (str) | |
ab3e48dc | 1250 | char *str; |
252b5132 RH |
1251 | { |
1252 | m32r_insn insn; | |
ab3e48dc KH |
1253 | char *errmsg; |
1254 | char *str2 = NULL; | |
252b5132 RH |
1255 | |
1256 | /* Initialize GAS's cgen interface for a new instruction. */ | |
1257 | gas_cgen_init_parse (); | |
1258 | ||
67c1ffbe | 1259 | /* Look for a parallel instruction separator. */ |
925c058e DE |
1260 | if ((str2 = strstr (str, "||")) != NULL) |
1261 | { | |
1262 | assemble_two_insns (str, str2, 1); | |
88845958 | 1263 | m32r_flags |= E_M32R_HAS_PARALLEL; |
925c058e DE |
1264 | return; |
1265 | } | |
1266 | ||
67c1ffbe | 1267 | /* Also look for a sequential instruction separator. */ |
925c058e DE |
1268 | if ((str2 = strstr (str, "->")) != NULL) |
1269 | { | |
1270 | assemble_two_insns (str, str2, 0); | |
1271 | return; | |
1272 | } | |
ab3e48dc | 1273 | |
252b5132 | 1274 | insn.debug_sym_link = debug_sym_link; |
ab3e48dc | 1275 | debug_sym_link = (sym_linkS *) 0; |
252b5132 RH |
1276 | |
1277 | insn.insn = m32r_cgen_assemble_insn | |
ab3e48dc KH |
1278 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
1279 | ||
252b5132 RH |
1280 | if (!insn.insn) |
1281 | { | |
1282 | as_bad (errmsg); | |
1283 | return; | |
1284 | } | |
1285 | ||
88845958 NC |
1286 | #ifdef E_M32R2_ARCH |
1287 | if ((enable_m32rx == 1) | |
1288 | /* FIXME: Need standard macro to perform this test. */ | |
1289 | && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) | |
1290 | & (1 << MACH_M32R2)) | |
1291 | && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) | |
1292 | & (1 << MACH_M32RX))))) | |
1293 | { | |
1294 | /* xgettext:c-format */ | |
1295 | as_bad (_("instruction '%s' is for the M32R2 only"), str); | |
1296 | return; | |
1297 | } | |
1298 | else if ((! enable_special | |
1299 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
1300 | || (! enable_special_m32r | |
1301 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))) | |
1302 | #else | |
925c058e DE |
1303 | if (! enable_special |
1304 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) | |
88845958 | 1305 | #endif |
925c058e | 1306 | { |
ab3e48dc | 1307 | /* xgettext:c-format */ |
925c058e DE |
1308 | as_bad (_("unknown instruction '%s'"), str); |
1309 | return; | |
1310 | } | |
1311 | else if (! enable_m32rx | |
1312 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) | |
1313 | { | |
ab3e48dc | 1314 | /* xgettext:c-format */ |
925c058e DE |
1315 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
1316 | return; | |
1317 | } | |
ab3e48dc | 1318 | |
88845958 NC |
1319 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
1320 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; | |
1321 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)) | |
1322 | m32r_flags |= E_M32R_HAS_BIT_INST; | |
1323 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT)) | |
1324 | m32r_flags |= E_M32R_HAS_FLOAT_INST; | |
1325 | ||
252b5132 RH |
1326 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
1327 | { | |
1328 | /* 32 bit insns must live on 32 bit boundaries. */ | |
1329 | if (prev_insn.insn || seen_relaxable_p) | |
1330 | { | |
1331 | /* ??? If calling fill_insn too many times turns us into a memory | |
1332 | pig, can we call a fn to assemble a nop instead of | |
1333 | !seen_relaxable_p? */ | |
1334 | fill_insn (0); | |
1335 | } | |
1336 | ||
1337 | expand_debug_syms (insn.debug_sym_link, 2); | |
1338 | ||
1339 | /* Doesn't really matter what we pass for RELAX_P here. */ | |
1340 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
ab3e48dc | 1341 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
252b5132 RH |
1342 | } |
1343 | else | |
1344 | { | |
1345 | int on_32bit_boundary_p; | |
b34976b6 | 1346 | int swap = FALSE; |
252b5132 RH |
1347 | |
1348 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) | |
ab3e48dc | 1349 | abort (); |
252b5132 RH |
1350 | |
1351 | insn.orig_insn = insn.insn; | |
1352 | ||
925c058e DE |
1353 | /* If the previous insn was relaxable, then it may be expanded |
1354 | to fill the current 16 bit slot. Emit a NOP here to occupy | |
1355 | this slot, so that we can start at optimizing at a 32 bit | |
1356 | boundary. */ | |
1357 | if (prev_insn.insn && seen_relaxable_p && optimize) | |
1358 | fill_insn (0); | |
ab3e48dc | 1359 | |
925c058e DE |
1360 | if (enable_m32rx) |
1361 | { | |
1362 | /* Get the indices of the operands of the instruction. | |
1363 | FIXME: See assemble_parallel for notes on orig_insn. */ | |
1364 | { | |
1365 | CGEN_FIELDS tmp_fields; | |
1366 | insn.insn = cgen_lookup_get_insn_operands | |
1367 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, | |
1368 | 16, insn.indices, &tmp_fields); | |
1369 | } | |
ab3e48dc | 1370 | |
925c058e DE |
1371 | if (insn.insn == NULL) |
1372 | as_fatal (_("internal error: lookup/get operands failed")); | |
1373 | } | |
1374 | ||
252b5132 RH |
1375 | /* Compute whether we're on a 32 bit boundary or not. |
1376 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1377 | on_32bit_boundary_p = prev_insn.insn == NULL; | |
1378 | ||
097dba13 NC |
1379 | /* Change a frag to, if each insn to swap is in a different frag. |
1380 | It must keep only one instruction in a frag. */ | |
1381 | if (parallel() && on_32bit_boundary_p) | |
1382 | { | |
1383 | frag_wane (frag_now); | |
1384 | frag_new (0); | |
1385 | } | |
1386 | ||
925c058e DE |
1387 | /* Look to see if this instruction can be combined with the |
1388 | previous instruction to make one, parallel, 32 bit instruction. | |
1389 | If the previous instruction (potentially) changed the flow of | |
1390 | program control, then it cannot be combined with the current | |
1391 | instruction. If the current instruction is relaxable, then it | |
1392 | might be replaced with a longer version, so we cannot combine it. | |
1393 | Also if the output of the previous instruction is used as an | |
1394 | input to the current instruction then it cannot be combined. | |
1395 | Otherwise call can_make_parallel() with both orderings of the | |
1396 | instructions to see if they can be combined. */ | |
ab3e48dc | 1397 | if (! on_32bit_boundary_p |
88845958 | 1398 | && parallel () |
ab3e48dc KH |
1399 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 |
1400 | && ! writes_to_pc (&prev_insn) | |
b34976b6 | 1401 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) |
925c058e | 1402 | { |
ab3e48dc | 1403 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
925c058e | 1404 | make_parallel (insn.buffer); |
ab3e48dc | 1405 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
b34976b6 | 1406 | swap = TRUE; |
925c058e | 1407 | } |
252b5132 RH |
1408 | |
1409 | expand_debug_syms (insn.debug_sym_link, 1); | |
1410 | ||
1411 | { | |
1412 | int i; | |
1413 | finished_insnS fi; | |
1414 | ||
1415 | /* Ensure each pair of 16 bit insns is in the same frag. */ | |
1416 | frag_grow (4); | |
1417 | ||
1418 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, | |
ab3e48dc KH |
1419 | CGEN_FIELDS_BITSIZE (&insn.fields), |
1420 | 1 /* relax_p */, &fi); | |
252b5132 RH |
1421 | insn.addr = fi.addr; |
1422 | insn.frag = fi.frag; | |
1423 | insn.num_fixups = fi.num_fixups; | |
1424 | for (i = 0; i < fi.num_fixups; ++i) | |
1425 | insn.fixups[i] = fi.fixups[i]; | |
1426 | } | |
1427 | ||
925c058e DE |
1428 | if (swap) |
1429 | { | |
ab3e48dc | 1430 | int i, tmp; |
925c058e DE |
1431 | |
1432 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp | |
1433 | ||
1434 | /* Swap the two insns */ | |
ab3e48dc KH |
1435 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
1436 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); | |
925c058e DE |
1437 | |
1438 | target_make_parallel (insn.addr); | |
1439 | ||
1440 | /* Swap any relaxable frags recorded for the two insns. */ | |
1441 | /* FIXME: Clarify. relaxation precludes parallel insns */ | |
1442 | if (prev_insn.frag->fr_opcode == prev_insn.addr) | |
1443 | prev_insn.frag->fr_opcode = insn.addr; | |
1444 | else if (insn.frag->fr_opcode == insn.addr) | |
1445 | insn.frag->fr_opcode = prev_insn.addr; | |
1446 | ||
097dba13 NC |
1447 | /* Change a frag to, if each insn is in a different frag. |
1448 | It must keep only one instruction in a frag. */ | |
1449 | if (prev_insn.frag != insn.frag) | |
1450 | { | |
1451 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1452 | prev_insn.fixups[i]->fx_frag = insn.frag; | |
1453 | for (i = 0; i < insn.num_fixups; ++i) | |
1454 | insn.fixups[i]->fx_frag = prev_insn.frag; | |
1455 | } | |
1456 | else | |
1457 | { | |
1458 | /* Update the addresses in any fixups. | |
1459 | Note that we don't have to handle the case where each insn is in | |
1460 | a different frag as we ensure they're in the same frag above. */ | |
1461 | for (i = 0; i < prev_insn.num_fixups; ++i) | |
1462 | prev_insn.fixups[i]->fx_where += 2; | |
1463 | for (i = 0; i < insn.num_fixups; ++i) | |
1464 | insn.fixups[i]->fx_where -= 2; | |
1465 | } | |
925c058e | 1466 | } |
252b5132 RH |
1467 | |
1468 | /* Keep track of whether we've seen a pair of 16 bit insns. | |
1469 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ | |
1470 | if (on_32bit_boundary_p) | |
1471 | prev_insn = insn; | |
1472 | else | |
1473 | prev_insn.insn = NULL; | |
ab3e48dc | 1474 | |
252b5132 RH |
1475 | /* If the insn needs the following one to be on a 32 bit boundary |
1476 | (e.g. subroutine calls), fill this insn's slot. */ | |
1477 | if (on_32bit_boundary_p | |
1478 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) | |
1479 | fill_insn (0); | |
1480 | ||
1481 | /* If this is a relaxable insn (can be replaced with a larger version) | |
1482 | mark the fact so that we can emit an alignment directive for a | |
1483 | following 32 bit insn if we see one. */ | |
1484 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) | |
1485 | seen_relaxable_p = 1; | |
1486 | } | |
1487 | ||
1488 | /* Set these so m32r_fill_insn can use them. */ | |
1489 | prev_seg = now_seg; | |
1490 | prev_subseg = now_subseg; | |
1491 | } | |
1492 | ||
1493 | /* The syntax in the manual says constants begin with '#'. | |
1494 | We just ignore it. */ | |
1495 | ||
ab3e48dc | 1496 | void |
252b5132 | 1497 | md_operand (expressionP) |
ab3e48dc | 1498 | expressionS *expressionP; |
252b5132 | 1499 | { |
ab3e48dc | 1500 | if (*input_line_pointer == '#') |
252b5132 | 1501 | { |
ab3e48dc | 1502 | input_line_pointer++; |
252b5132 RH |
1503 | expression (expressionP); |
1504 | } | |
1505 | } | |
1506 | ||
1507 | valueT | |
1508 | md_section_align (segment, size) | |
ab3e48dc | 1509 | segT segment; |
252b5132 RH |
1510 | valueT size; |
1511 | { | |
1512 | int align = bfd_get_section_alignment (stdoutput, segment); | |
1513 | return ((size + (1 << align) - 1) & (-1 << align)); | |
1514 | } | |
1515 | ||
1516 | symbolS * | |
1517 | md_undefined_symbol (name) | |
78a0c6fb | 1518 | char *name ATTRIBUTE_UNUSED; |
252b5132 RH |
1519 | { |
1520 | return 0; | |
1521 | } | |
1522 | \f | |
1523 | /* .scomm pseudo-op handler. | |
1524 | ||
1525 | This is a new pseudo-op to handle putting objects in .scommon. | |
ab3e48dc KH |
1526 | By doing this the linker won't need to do any work, |
1527 | and more importantly it removes the implicit -G arg necessary to | |
1528 | correctly link the object file. */ | |
252b5132 RH |
1529 | |
1530 | static void | |
1531 | m32r_scomm (ignore) | |
78a0c6fb | 1532 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 1533 | { |
ab3e48dc KH |
1534 | register char *name; |
1535 | register char c; | |
1536 | register char *p; | |
1537 | offsetT size; | |
1538 | register symbolS *symbolP; | |
1539 | offsetT align; | |
1540 | int align2; | |
252b5132 RH |
1541 | |
1542 | name = input_line_pointer; | |
1543 | c = get_symbol_end (); | |
1544 | ||
ab3e48dc | 1545 | /* Just after name is now '\0'. */ |
252b5132 | 1546 | p = input_line_pointer; |
ab3e48dc | 1547 | *p = c; |
252b5132 | 1548 | SKIP_WHITESPACE (); |
ab3e48dc | 1549 | if (*input_line_pointer != ',') |
252b5132 RH |
1550 | { |
1551 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); | |
1552 | ignore_rest_of_line (); | |
1553 | return; | |
1554 | } | |
1555 | ||
ab3e48dc KH |
1556 | /* Skip ','. */ |
1557 | input_line_pointer++; | |
252b5132 RH |
1558 | if ((size = get_absolute_expression ()) < 0) |
1559 | { | |
ab3e48dc | 1560 | /* xgettext:c-format */ |
252b5132 RH |
1561 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
1562 | ignore_rest_of_line (); | |
1563 | return; | |
1564 | } | |
1565 | ||
1566 | /* The third argument to .scomm is the alignment. */ | |
ab3e48dc | 1567 | if (*input_line_pointer != ',') |
252b5132 RH |
1568 | align = 8; |
1569 | else | |
1570 | { | |
ab3e48dc | 1571 | ++input_line_pointer; |
252b5132 RH |
1572 | align = get_absolute_expression (); |
1573 | if (align <= 0) | |
1574 | { | |
1575 | as_warn (_("ignoring bad alignment")); | |
1576 | align = 8; | |
1577 | } | |
1578 | } | |
ab3e48dc | 1579 | |
252b5132 RH |
1580 | /* Convert to a power of 2 alignment. */ |
1581 | if (align) | |
1582 | { | |
ab3e48dc | 1583 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
252b5132 RH |
1584 | continue; |
1585 | if (align != 1) | |
1586 | { | |
1587 | as_bad (_("Common alignment not a power of 2")); | |
1588 | ignore_rest_of_line (); | |
1589 | return; | |
1590 | } | |
1591 | } | |
1592 | else | |
1593 | align2 = 0; | |
1594 | ||
ab3e48dc | 1595 | *p = 0; |
252b5132 | 1596 | symbolP = symbol_find_or_make (name); |
ab3e48dc | 1597 | *p = c; |
252b5132 RH |
1598 | |
1599 | if (S_IS_DEFINED (symbolP)) | |
1600 | { | |
ab3e48dc | 1601 | /* xgettext:c-format */ |
252b5132 RH |
1602 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
1603 | S_GET_NAME (symbolP)); | |
1604 | ignore_rest_of_line (); | |
1605 | return; | |
1606 | } | |
1607 | ||
1608 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
1609 | { | |
ab3e48dc | 1610 | /* xgettext:c-format */ |
252b5132 RH |
1611 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
1612 | S_GET_NAME (symbolP), | |
1613 | (long) S_GET_VALUE (symbolP), | |
1614 | (long) size); | |
1615 | ||
1616 | ignore_rest_of_line (); | |
1617 | return; | |
1618 | } | |
1619 | ||
f412ead8 | 1620 | if (symbol_get_obj (symbolP)->local) |
252b5132 | 1621 | { |
ab3e48dc KH |
1622 | segT old_sec = now_seg; |
1623 | int old_subsec = now_subseg; | |
1624 | char *pfrag; | |
252b5132 RH |
1625 | |
1626 | record_alignment (sbss_section, align2); | |
1627 | subseg_set (sbss_section, 0); | |
ab3e48dc | 1628 | |
252b5132 RH |
1629 | if (align2) |
1630 | frag_align (align2, 0, 0); | |
ab3e48dc | 1631 | |
252b5132 | 1632 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
f412ead8 | 1633 | symbol_get_frag (symbolP)->fr_symbol = 0; |
ab3e48dc | 1634 | |
f412ead8 | 1635 | symbol_set_frag (symbolP, frag_now); |
ab3e48dc | 1636 | |
252b5132 RH |
1637 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
1638 | (char *) 0); | |
ab3e48dc | 1639 | *pfrag = 0; |
252b5132 RH |
1640 | S_SET_SIZE (symbolP, size); |
1641 | S_SET_SEGMENT (symbolP, sbss_section); | |
1642 | S_CLEAR_EXTERNAL (symbolP); | |
1643 | subseg_set (old_sec, old_subsec); | |
1644 | } | |
1645 | else | |
1646 | { | |
1647 | S_SET_VALUE (symbolP, (valueT) size); | |
1648 | S_SET_ALIGN (symbolP, align2); | |
1649 | S_SET_EXTERNAL (symbolP); | |
ab3e48dc | 1650 | S_SET_SEGMENT (symbolP, &scom_section); |
252b5132 RH |
1651 | } |
1652 | ||
1653 | demand_empty_rest_of_line (); | |
1654 | } | |
1655 | \f | |
1656 | /* Interface to relax_segment. */ | |
1657 | ||
1658 | /* FIXME: Build table by hand, get it working, then machine generate. */ | |
1659 | ||
1660 | const relax_typeS md_relax_table[] = | |
1661 | { | |
1662 | /* The fields are: | |
1663 | 1) most positive reach of this state, | |
1664 | 2) most negative reach of this state, | |
1665 | 3) how many bytes this mode will add to the size of the current frag | |
1666 | 4) which index into the table to try if we can't fit into this one. */ | |
1667 | ||
1668 | /* The first entry must be unused because an `rlx_more' value of zero ends | |
1669 | each list. */ | |
1670 | {1, 1, 0, 0}, | |
1671 | ||
1672 | /* The displacement used by GAS is from the end of the 2 byte insn, | |
1673 | so we subtract 2 from the following. */ | |
1674 | /* 16 bit insn, 8 bit disp -> 10 bit range. | |
1675 | This doesn't handle a branch in the right slot at the border: | |
1676 | the "& -4" isn't taken into account. It's not important enough to | |
1677 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve | |
1678 | case). */ | |
1679 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, | |
1680 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ | |
1681 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, | |
1682 | /* Same thing, but with leading nop for alignment. */ | |
1683 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } | |
1684 | }; | |
1685 | ||
1686 | long | |
c842b53a ILT |
1687 | m32r_relax_frag (segment, fragP, stretch) |
1688 | segT segment; | |
ab3e48dc KH |
1689 | fragS *fragP; |
1690 | long stretch; | |
252b5132 RH |
1691 | { |
1692 | /* Address of branch insn. */ | |
1693 | long address = fragP->fr_address + fragP->fr_fix - 2; | |
1694 | long growth = 0; | |
1695 | ||
1696 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ | |
1697 | if (fragP->fr_subtype == 2) | |
1698 | { | |
1699 | if ((address & 3) != 0) | |
1700 | { | |
1701 | fragP->fr_subtype = 3; | |
1702 | growth = 2; | |
1703 | } | |
1704 | } | |
1705 | else if (fragP->fr_subtype == 3) | |
1706 | { | |
1707 | if ((address & 3) == 0) | |
1708 | { | |
1709 | fragP->fr_subtype = 2; | |
1710 | growth = -2; | |
1711 | } | |
1712 | } | |
1713 | else | |
1714 | { | |
c842b53a | 1715 | growth = relax_frag (segment, fragP, stretch); |
252b5132 RH |
1716 | |
1717 | /* Long jump on odd halfword boundary? */ | |
1718 | if (fragP->fr_subtype == 2 && (address & 3) != 0) | |
1719 | { | |
1720 | fragP->fr_subtype = 3; | |
1721 | growth += 2; | |
1722 | } | |
1723 | } | |
1724 | ||
1725 | return growth; | |
1726 | } | |
1727 | ||
1728 | /* Return an initial guess of the length by which a fragment must grow to | |
1729 | hold a branch to reach its destination. | |
1730 | Also updates fr_type/fr_subtype as necessary. | |
1731 | ||
1732 | Called just before doing relaxation. | |
1733 | Any symbol that is now undefined will not become defined. | |
1734 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
1735 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
ab3e48dc KH |
1736 | Although it may not be explicit in the frag, pretend fr_var starts |
1737 | with a 0 value. */ | |
252b5132 RH |
1738 | |
1739 | int | |
1740 | md_estimate_size_before_relax (fragP, segment) | |
ab3e48dc KH |
1741 | fragS *fragP; |
1742 | segT segment; | |
252b5132 | 1743 | { |
252b5132 RH |
1744 | /* The only thing we have to handle here are symbols outside of the |
1745 | current segment. They may be undefined or in a different segment in | |
1746 | which case linker scripts may place them anywhere. | |
1747 | However, we can't finish the fragment here and emit the reloc as insn | |
1748 | alignment requirements may move the insn about. */ | |
1749 | ||
6edf0760 NC |
1750 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
1751 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1752 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 RH |
1753 | { |
1754 | /* The symbol is undefined in this segment. | |
1755 | Change the relaxation subtype to the max allowable and leave | |
1756 | all further handling to md_convert_frag. */ | |
1757 | fragP->fr_subtype = 2; | |
1758 | ||
252b5132 | 1759 | { |
ab3e48dc KH |
1760 | const CGEN_INSN *insn; |
1761 | int i; | |
252b5132 RH |
1762 | |
1763 | /* Update the recorded insn. | |
1764 | Fortunately we don't have to look very far. | |
1765 | FIXME: Change this to record in the instruction the next higher | |
1766 | relaxable insn to use. */ | |
1767 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) | |
1768 | { | |
1769 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), | |
1770 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) | |
1771 | == 0) | |
b11dcf4e | 1772 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) |
252b5132 RH |
1773 | break; |
1774 | } | |
1775 | if (i == 4) | |
1776 | abort (); | |
1777 | ||
1778 | fragP->fr_cgen.insn = insn; | |
1779 | return 2; | |
1780 | } | |
252b5132 RH |
1781 | } |
1782 | ||
606ab118 | 1783 | return md_relax_table[fragP->fr_subtype].rlx_length; |
ab3e48dc | 1784 | } |
252b5132 | 1785 | |
ab3e48dc | 1786 | /* *FRAGP has been relaxed to its final size, and now needs to have |
252b5132 RH |
1787 | the bytes inside it modified to conform to the new size. |
1788 | ||
1789 | Called after relaxation is finished. | |
1790 | fragP->fr_type == rs_machine_dependent. | |
1791 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
1792 | ||
1793 | void | |
1794 | md_convert_frag (abfd, sec, fragP) | |
78a0c6fb | 1795 | bfd *abfd ATTRIBUTE_UNUSED; |
ab3e48dc KH |
1796 | segT sec; |
1797 | fragS *fragP; | |
252b5132 | 1798 | { |
ab3e48dc KH |
1799 | char *opcode; |
1800 | char *displacement; | |
1801 | int target_address; | |
1802 | int opcode_address; | |
1803 | int extension; | |
1804 | int addend; | |
252b5132 RH |
1805 | |
1806 | opcode = fragP->fr_opcode; | |
1807 | ||
1808 | /* Address opcode resides at in file space. */ | |
1809 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; | |
1810 | ||
1811 | switch (fragP->fr_subtype) | |
1812 | { | |
ab3e48dc | 1813 | case 1: |
252b5132 | 1814 | extension = 0; |
ab3e48dc | 1815 | displacement = &opcode[1]; |
252b5132 | 1816 | break; |
ab3e48dc | 1817 | case 2: |
252b5132 RH |
1818 | opcode[0] |= 0x80; |
1819 | extension = 2; | |
ab3e48dc | 1820 | displacement = &opcode[1]; |
252b5132 | 1821 | break; |
ab3e48dc | 1822 | case 3: |
252b5132 RH |
1823 | opcode[2] = opcode[0] | 0x80; |
1824 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); | |
1825 | opcode_address += 2; | |
1826 | extension = 4; | |
ab3e48dc | 1827 | displacement = &opcode[3]; |
252b5132 | 1828 | break; |
ab3e48dc | 1829 | default: |
252b5132 RH |
1830 | abort (); |
1831 | } | |
1832 | ||
6edf0760 NC |
1833 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
1834 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1835 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1836 | { |
ab3e48dc | 1837 | /* Symbol must be resolved by linker. */ |
252b5132 RH |
1838 | if (fragP->fr_offset & 3) |
1839 | as_warn (_("Addend to unresolved symbol not on word boundary.")); | |
6edf0760 NC |
1840 | #ifdef USE_M32R_OLD_RELOC |
1841 | addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */ | |
1842 | #else | |
1843 | addend = 0; | |
1844 | #endif | |
252b5132 RH |
1845 | } |
1846 | else | |
1847 | { | |
1848 | /* Address we want to reach in file space. */ | |
1849 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
252b5132 RH |
1850 | addend = (target_address - (opcode_address & -4)) >> 2; |
1851 | } | |
1852 | ||
1853 | /* Create a relocation for symbols that must be resolved by the linker. | |
1854 | Otherwise output the completed insn. */ | |
1855 | ||
6edf0760 NC |
1856 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
1857 | || S_IS_EXTERNAL (fragP->fr_symbol) | |
1858 | || S_IS_WEAK (fragP->fr_symbol)) | |
252b5132 | 1859 | { |
097f809a NC |
1860 | fixS *fixP; |
1861 | ||
252b5132 RH |
1862 | assert (fragP->fr_subtype != 1); |
1863 | assert (fragP->fr_cgen.insn != 0); | |
097f809a NC |
1864 | |
1865 | fixP = gas_cgen_record_fixup (fragP, | |
1866 | /* Offset of branch insn in frag. */ | |
1867 | fragP->fr_fix + extension - 4, | |
1868 | fragP->fr_cgen.insn, | |
1869 | 4 /* Length. */, | |
1870 | /* FIXME: quick hack. */ | |
097f809a NC |
1871 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
1872 | M32R_OPERAND_DISP24), | |
097f809a NC |
1873 | fragP->fr_cgen.opinfo, |
1874 | fragP->fr_symbol, fragP->fr_offset); | |
1875 | if (fragP->fr_cgen.opinfo) | |
1876 | fixP->fx_r_type = fragP->fr_cgen.opinfo; | |
252b5132 RH |
1877 | } |
1878 | ||
1879 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) | |
1880 | ||
1881 | md_number_to_chars (displacement, (valueT) addend, | |
1882 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
1883 | ||
1884 | fragP->fr_fix += extension; | |
1885 | } | |
1886 | \f | |
1887 | /* Functions concerning relocs. */ | |
1888 | ||
1889 | /* The location from which a PC relative jump should be calculated, | |
1890 | given a PC relative reloc. */ | |
1891 | ||
1892 | long | |
1893 | md_pcrel_from_section (fixP, sec) | |
ab3e48dc KH |
1894 | fixS *fixP; |
1895 | segT sec; | |
252b5132 RH |
1896 | { |
1897 | if (fixP->fx_addsy != (symbolS *) NULL | |
1898 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
6edf0760 NC |
1899 | || S_GET_SEGMENT (fixP->fx_addsy) != sec |
1900 | || S_IS_EXTERNAL (fixP->fx_addsy) | |
1901 | || S_IS_WEAK (fixP->fx_addsy))) | |
252b5132 | 1902 | { |
a7498ae6 NC |
1903 | if (S_GET_SEGMENT (fixP->fx_addsy) != sec |
1904 | && S_IS_DEFINED (fixP->fx_addsy) | |
1905 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
1906 | && ! S_IS_WEAK (fixP->fx_addsy)) | |
1907 | return fixP->fx_offset; | |
1908 | ||
252b5132 RH |
1909 | /* The symbol is undefined (or is defined but not in this section). |
1910 | Let the linker figure it out. */ | |
1911 | return 0; | |
1912 | } | |
1913 | ||
1914 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; | |
1915 | } | |
1916 | ||
1917 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
1918 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
1919 | *FIXP may be modified if desired. */ | |
1920 | ||
1921 | bfd_reloc_code_real_type | |
1922 | md_cgen_lookup_reloc (insn, operand, fixP) | |
78a0c6fb | 1923 | const CGEN_INSN *insn ATTRIBUTE_UNUSED; |
ab3e48dc KH |
1924 | const CGEN_OPERAND *operand; |
1925 | fixS *fixP; | |
252b5132 RH |
1926 | { |
1927 | switch (operand->type) | |
1928 | { | |
ab3e48dc KH |
1929 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
1930 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; | |
1931 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; | |
1932 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; | |
1933 | case M32R_OPERAND_HI16: | |
1934 | case M32R_OPERAND_SLO16: | |
1935 | case M32R_OPERAND_ULO16: | |
252b5132 RH |
1936 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1937 | if (fixP->fx_cgen.opinfo != 0) | |
1938 | return fixP->fx_cgen.opinfo; | |
1939 | break; | |
ab3e48dc KH |
1940 | default: |
1941 | /* Avoid -Wall warning. */ | |
252b5132 RH |
1942 | break; |
1943 | } | |
1944 | return BFD_RELOC_NONE; | |
1945 | } | |
1946 | ||
1947 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ | |
1948 | ||
78a0c6fb AM |
1949 | static void m32r_record_hi16 PARAMS ((int, fixS *, segT)); |
1950 | ||
252b5132 RH |
1951 | static void |
1952 | m32r_record_hi16 (reloc_type, fixP, seg) | |
ab3e48dc KH |
1953 | int reloc_type; |
1954 | fixS *fixP; | |
78a0c6fb | 1955 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 1956 | { |
ab3e48dc | 1957 | struct m32r_hi_fixup *hi_fixup; |
252b5132 RH |
1958 | |
1959 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO | |
1960 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); | |
1961 | ||
1962 | hi_fixup = ((struct m32r_hi_fixup *) | |
1963 | xmalloc (sizeof (struct m32r_hi_fixup))); | |
1964 | hi_fixup->fixp = fixP; | |
1965 | hi_fixup->seg = now_seg; | |
1966 | hi_fixup->next = m32r_hi_fixup_list; | |
ab3e48dc | 1967 | |
252b5132 RH |
1968 | m32r_hi_fixup_list = hi_fixup; |
1969 | } | |
1970 | ||
1971 | /* Called while parsing an instruction to create a fixup. | |
1972 | We need to check for HI16 relocs and queue them up for later sorting. */ | |
1973 | ||
1974 | fixS * | |
1975 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) | |
ab3e48dc KH |
1976 | fragS *frag; |
1977 | int where; | |
1978 | const CGEN_INSN *insn; | |
1979 | int length; | |
1980 | const CGEN_OPERAND *operand; | |
1981 | int opinfo; | |
1982 | expressionS *exp; | |
252b5132 | 1983 | { |
097f809a NC |
1984 | fixS *fixP; |
1985 | bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED; | |
1986 | ||
1987 | if (m32r_check_fixup (exp, &r_type)) | |
1988 | as_bad (_("Invalid PIC expression.")); | |
1989 | ||
1990 | fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, | |
1991 | operand, opinfo, exp); | |
252b5132 RH |
1992 | |
1993 | switch (operand->type) | |
1994 | { | |
ab3e48dc | 1995 | case M32R_OPERAND_HI16: |
252b5132 RH |
1996 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
1997 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO | |
1998 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
1999 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); | |
2000 | break; | |
097f809a | 2001 | |
ab3e48dc | 2002 | default: |
097f809a | 2003 | /* Avoid -Wall warning. */ |
252b5132 RH |
2004 | break; |
2005 | } | |
2006 | ||
097f809a NC |
2007 | switch (r_type) |
2008 | { | |
2009 | case BFD_RELOC_UNUSED: | |
2010 | default: | |
2011 | return fixP; | |
2012 | ||
2013 | case BFD_RELOC_M32R_GOTPC24: | |
2014 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
2015 | r_type = BFD_RELOC_M32R_GOTPC_HI_SLO; | |
2016 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
2017 | r_type = BFD_RELOC_M32R_GOTPC_HI_ULO; | |
2018 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
2019 | r_type = BFD_RELOC_M32R_GOTPC_LO; | |
2020 | break; | |
2021 | case BFD_RELOC_M32R_GOT24: | |
2022 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
2023 | r_type = BFD_RELOC_M32R_GOT16_HI_SLO; | |
2024 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
2025 | r_type = BFD_RELOC_M32R_GOT16_HI_ULO; | |
2026 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
2027 | r_type = BFD_RELOC_M32R_GOT16_LO; | |
2028 | break; | |
2029 | case BFD_RELOC_M32R_GOTOFF: | |
2030 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) | |
2031 | r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO; | |
2032 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) | |
2033 | r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO; | |
2034 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) | |
2035 | r_type = BFD_RELOC_M32R_GOTOFF_LO; | |
2036 | break; | |
2037 | case BFD_RELOC_M32R_26_PLTREL: | |
2038 | as_bad (_("Invalid PIC expression.")); | |
2039 | break; | |
2040 | } | |
2041 | ||
2042 | fixP->fx_r_type = r_type; | |
2043 | ||
252b5132 RH |
2044 | return fixP; |
2045 | } | |
2046 | ||
2047 | /* Return BFD reloc type from opinfo field in a fixS. | |
2048 | It's tricky using fx_r_type in m32r_frob_file because the values | |
2049 | are BFD_RELOC_UNUSED + operand number. */ | |
2050 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) | |
2051 | ||
2052 | /* Sort any unmatched HI16 relocs so that they immediately precede | |
94f592af | 2053 | the corresponding LO16 reloc. This is called before md_apply_fix3 and |
252b5132 RH |
2054 | tc_gen_reloc. */ |
2055 | ||
2056 | void | |
2057 | m32r_frob_file () | |
2058 | { | |
ab3e48dc | 2059 | struct m32r_hi_fixup *l; |
252b5132 RH |
2060 | |
2061 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) | |
2062 | { | |
ab3e48dc KH |
2063 | segment_info_type *seginfo; |
2064 | int pass; | |
252b5132 RH |
2065 | |
2066 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO | |
2067 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); | |
2068 | ||
2069 | /* Check quickly whether the next fixup happens to be a matching low. */ | |
2070 | if (l->fixp->fx_next != NULL | |
2071 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 | |
2072 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
2073 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
2074 | continue; | |
2075 | ||
2076 | /* Look through the fixups for this segment for a matching `low'. | |
2077 | When we find one, move the high/shigh just in front of it. We do | |
2078 | this in two passes. In the first pass, we try to find a | |
2079 | unique `low'. In the second pass, we permit multiple high's | |
2080 | relocs for a single `low'. */ | |
2081 | seginfo = seg_info (l->seg); | |
2082 | for (pass = 0; pass < 2; pass++) | |
2083 | { | |
ab3e48dc KH |
2084 | fixS *f; |
2085 | fixS *prev; | |
252b5132 RH |
2086 | |
2087 | prev = NULL; | |
2088 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
2089 | { | |
2090 | /* Check whether this is a `low' fixup which matches l->fixp. */ | |
2091 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 | |
2092 | && f->fx_addsy == l->fixp->fx_addsy | |
2093 | && f->fx_offset == l->fixp->fx_offset | |
2094 | && (pass == 1 | |
2095 | || prev == NULL | |
2096 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO | |
2097 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) | |
2098 | || prev->fx_addsy != f->fx_addsy | |
ab3e48dc | 2099 | || prev->fx_offset != f->fx_offset)) |
252b5132 | 2100 | { |
ab3e48dc | 2101 | fixS **pf; |
252b5132 RH |
2102 | |
2103 | /* Move l->fixp before f. */ | |
2104 | for (pf = &seginfo->fix_root; | |
ab3e48dc KH |
2105 | *pf != l->fixp; |
2106 | pf = & (*pf)->fx_next) | |
2107 | assert (*pf != NULL); | |
252b5132 | 2108 | |
ab3e48dc | 2109 | *pf = l->fixp->fx_next; |
252b5132 RH |
2110 | |
2111 | l->fixp->fx_next = f; | |
2112 | if (prev == NULL) | |
2113 | seginfo->fix_root = l->fixp; | |
2114 | else | |
2115 | prev->fx_next = l->fixp; | |
2116 | ||
2117 | break; | |
2118 | } | |
2119 | ||
2120 | prev = f; | |
2121 | } | |
2122 | ||
2123 | if (f != NULL) | |
2124 | break; | |
2125 | ||
2126 | if (pass == 1 | |
2127 | && warn_unmatched_high) | |
2128 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
2129 | _("Unmatched high/shigh reloc")); | |
2130 | } | |
2131 | } | |
2132 | } | |
2133 | ||
2134 | /* See whether we need to force a relocation into the output file. | |
2135 | This is used to force out switch and PC relative relocations when | |
2136 | relaxing. */ | |
2137 | ||
2138 | int | |
2139 | m32r_force_relocation (fix) | |
ab3e48dc | 2140 | fixS *fix; |
252b5132 | 2141 | { |
ae6063d4 | 2142 | if (generic_force_reloc (fix)) |
252b5132 RH |
2143 | return 1; |
2144 | ||
2145 | if (! m32r_relax) | |
2146 | return 0; | |
2147 | ||
ab3e48dc | 2148 | return fix->fx_pcrel; |
252b5132 RH |
2149 | } |
2150 | \f | |
2151 | /* Write a value out to the object file, using the appropriate endianness. */ | |
2152 | ||
2153 | void | |
2154 | md_number_to_chars (buf, val, n) | |
ab3e48dc | 2155 | char *buf; |
252b5132 | 2156 | valueT val; |
ab3e48dc | 2157 | int n; |
252b5132 RH |
2158 | { |
2159 | if (target_big_endian) | |
2160 | number_to_chars_bigendian (buf, val, n); | |
2161 | else | |
2162 | number_to_chars_littleendian (buf, val, n); | |
2163 | } | |
2164 | ||
ab3e48dc KH |
2165 | /* Turn a string in input_line_pointer into a floating point constant |
2166 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
2167 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
2168 | returned, or NULL on OK. */ | |
252b5132 | 2169 | |
ab3e48dc | 2170 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
2171 | #define MAX_LITTLENUMS 6 |
2172 | ||
2173 | char * | |
2174 | md_atof (type, litP, sizeP) | |
2175 | char type; | |
2176 | char *litP; | |
2177 | int *sizeP; | |
2178 | { | |
ab3e48dc KH |
2179 | int i; |
2180 | int prec; | |
2181 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2182 | char *t; | |
252b5132 RH |
2183 | |
2184 | switch (type) | |
2185 | { | |
2186 | case 'f': | |
2187 | case 'F': | |
2188 | case 's': | |
2189 | case 'S': | |
2190 | prec = 2; | |
2191 | break; | |
2192 | ||
2193 | case 'd': | |
2194 | case 'D': | |
2195 | case 'r': | |
2196 | case 'R': | |
2197 | prec = 4; | |
2198 | break; | |
2199 | ||
ab3e48dc KH |
2200 | /* FIXME: Some targets allow other format chars for bigger sizes |
2201 | here. */ | |
252b5132 RH |
2202 | |
2203 | default: | |
ab3e48dc | 2204 | *sizeP = 0; |
252b5132 RH |
2205 | return _("Bad call to md_atof()"); |
2206 | } | |
2207 | ||
2208 | t = atof_ieee (input_line_pointer, type, words); | |
2209 | if (t) | |
2210 | input_line_pointer = t; | |
ab3e48dc | 2211 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
252b5132 RH |
2212 | |
2213 | if (target_big_endian) | |
2214 | { | |
2215 | for (i = 0; i < prec; i++) | |
2216 | { | |
2217 | md_number_to_chars (litP, (valueT) words[i], | |
2218 | sizeof (LITTLENUM_TYPE)); | |
2219 | litP += sizeof (LITTLENUM_TYPE); | |
2220 | } | |
2221 | } | |
2222 | else | |
2223 | { | |
2224 | for (i = prec - 1; i >= 0; i--) | |
2225 | { | |
2226 | md_number_to_chars (litP, (valueT) words[i], | |
2227 | sizeof (LITTLENUM_TYPE)); | |
2228 | litP += sizeof (LITTLENUM_TYPE); | |
2229 | } | |
2230 | } | |
ab3e48dc | 2231 | |
252b5132 RH |
2232 | return 0; |
2233 | } | |
2234 | ||
2235 | void | |
2236 | m32r_elf_section_change_hook () | |
2237 | { | |
2238 | /* If we have reached the end of a section and we have just emitted a | |
2239 | 16 bit insn, then emit a nop to make sure that the section ends on | |
2240 | a 32 bit boundary. */ | |
ab3e48dc | 2241 | |
252b5132 RH |
2242 | if (prev_insn.insn || seen_relaxable_p) |
2243 | (void) m32r_fill_insn (0); | |
2244 | } | |
2245 | ||
60bcf0fa | 2246 | /* Return true if can adjust the reloc to be relative to its section |
ab3e48dc | 2247 | (such as .data) instead of relative to some symbol. */ |
60bcf0fa | 2248 | |
b34976b6 | 2249 | bfd_boolean |
252b5132 RH |
2250 | m32r_fix_adjustable (fixP) |
2251 | fixS *fixP; | |
2252 | { | |
5c86cbc7 | 2253 | bfd_reloc_code_real_type reloc_type; |
ab3e48dc | 2254 | |
5c86cbc7 CM |
2255 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
2256 | { | |
2257 | const CGEN_INSN *insn = NULL; | |
2258 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; | |
ab3e48dc KH |
2259 | const CGEN_OPERAND *operand = |
2260 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); | |
5c86cbc7 CM |
2261 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
2262 | } | |
2263 | else | |
2264 | reloc_type = fixP->fx_r_type; | |
2265 | ||
6edf0760 NC |
2266 | if (fixP->fx_addsy == NULL) |
2267 | return 1; | |
2268 | ||
2269 | /* Prevent all adjustments to global symbols. */ | |
2270 | if (S_IS_EXTERN (fixP->fx_addsy)) | |
2271 | return 0; | |
2272 | if (S_IS_WEAK (fixP->fx_addsy)) | |
2273 | return 0; | |
2274 | ||
2275 | if (pic_code | |
2276 | && (reloc_type == BFD_RELOC_M32R_24 | |
2277 | || reloc_type == BFD_RELOC_M32R_26_PCREL | |
2278 | || reloc_type == BFD_RELOC_M32R_HI16_SLO | |
2279 | || reloc_type == BFD_RELOC_M32R_HI16_ULO | |
2280 | || reloc_type == BFD_RELOC_M32R_LO16)) | |
2281 | return 0; | |
2282 | ||
097f809a NC |
2283 | if (reloc_type == BFD_RELOC_M32R_GOT24 |
2284 | || reloc_type == BFD_RELOC_M32R_26_PLTREL | |
2285 | || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO | |
2286 | || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO | |
2287 | || reloc_type == BFD_RELOC_M32R_GOTPC_LO | |
2288 | || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO | |
2289 | || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO | |
2290 | || reloc_type == BFD_RELOC_M32R_GOT16_LO) | |
2291 | return 0; | |
2292 | ||
ab3e48dc | 2293 | /* We need the symbol name for the VTABLE entries. */ |
5c86cbc7 CM |
2294 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
2295 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
2296 | return 0; |
2297 | ||
2298 | return 1; | |
2299 | } | |
88845958 NC |
2300 | |
2301 | void | |
097f809a | 2302 | m32r_elf_final_processing (void) |
88845958 NC |
2303 | { |
2304 | if (use_parallel) | |
2305 | m32r_flags |= E_M32R_HAS_PARALLEL; | |
2306 | elf_elfheader (stdoutput)->e_flags |= m32r_flags; | |
2307 | } | |
6edf0760 | 2308 | |
6edf0760 NC |
2309 | /* Translate internal representation of relocation info to BFD target |
2310 | format. */ | |
097f809a | 2311 | |
6edf0760 NC |
2312 | arelent * |
2313 | tc_gen_reloc (section, fixP) | |
2314 | asection * section; | |
2315 | fixS * fixP; | |
2316 | { | |
2317 | arelent * reloc; | |
2318 | bfd_reloc_code_real_type code; | |
2319 | ||
2320 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
2321 | ||
2322 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2323 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); | |
2324 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; | |
2325 | ||
2326 | code = fixP->fx_r_type; | |
2327 | if (pic_code) | |
2328 | { | |
2329 | #ifdef DEBUG_PIC | |
2330 | printf("%s",bfd_get_reloc_code_name(code)); | |
2331 | #endif | |
2332 | switch (code) | |
2333 | { | |
2334 | case BFD_RELOC_M32R_26_PCREL: | |
2335 | code = BFD_RELOC_M32R_26_PLTREL; | |
2336 | break; | |
2337 | case BFD_RELOC_M32R_24: | |
2338 | if (fixP->fx_addsy != NULL | |
2339 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2340 | code = BFD_RELOC_M32R_GOTPC24; | |
2341 | else | |
2342 | code = BFD_RELOC_M32R_GOT24; | |
2343 | break; | |
2344 | case BFD_RELOC_M32R_HI16_ULO: | |
2345 | if (fixP->fx_addsy != NULL | |
2346 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2347 | code = BFD_RELOC_M32R_GOTPC_HI_ULO; | |
2348 | else | |
2349 | code = BFD_RELOC_M32R_GOT16_HI_ULO; | |
2350 | break; | |
2351 | case BFD_RELOC_M32R_HI16_SLO: | |
2352 | if (fixP->fx_addsy != NULL | |
2353 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2354 | code = BFD_RELOC_M32R_GOTPC_HI_SLO; | |
2355 | else | |
2356 | code = BFD_RELOC_M32R_GOT16_HI_SLO; | |
2357 | break; | |
2358 | case BFD_RELOC_M32R_LO16: | |
2359 | if (fixP->fx_addsy != NULL | |
2360 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) | |
2361 | code = BFD_RELOC_M32R_GOTPC_LO; | |
2362 | else | |
2363 | code = BFD_RELOC_M32R_GOT16_LO; | |
2364 | break; | |
2365 | default: | |
2366 | break; | |
2367 | } | |
2368 | #ifdef DEBUG_PIC | |
2369 | printf(" => %s",bfd_get_reloc_code_name(code)); | |
2370 | #endif | |
2371 | } | |
2372 | ||
2373 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
2374 | #ifdef DEBUG_PIC | |
2375 | printf(" => %s\n",reloc->howto->name); | |
2376 | #endif | |
2377 | if (reloc->howto == (reloc_howto_type *) NULL) | |
2378 | { | |
2379 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2380 | _("internal error: can't export reloc type %d (`%s')"), | |
2381 | fixP->fx_r_type, bfd_get_reloc_code_name (code)); | |
2382 | return NULL; | |
2383 | } | |
2384 | ||
097f809a | 2385 | /* Use fx_offset for these cases. */ |
6edf0760 NC |
2386 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
2387 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT) | |
2388 | reloc->addend = fixP->fx_offset; | |
097f809a NC |
2389 | else if ((!pic_code |
2390 | && code != BFD_RELOC_M32R_26_PLTREL) | |
6edf0760 NC |
2391 | && fixP->fx_pcrel |
2392 | && fixP->fx_addsy != NULL | |
2393 | && (S_GET_SEGMENT(fixP->fx_addsy) != section) | |
2394 | && S_IS_DEFINED (fixP->fx_addsy) | |
2395 | && ! S_IS_EXTERNAL(fixP->fx_addsy) | |
2396 | && ! S_IS_WEAK(fixP->fx_addsy)) | |
097f809a | 2397 | /* Already used fx_offset in the opcode field itseld. */ |
a7498ae6 | 2398 | reloc->addend = fixP->fx_offset; |
6edf0760 NC |
2399 | else |
2400 | reloc->addend = fixP->fx_addnumber; | |
2401 | ||
2402 | return reloc; | |
2403 | } | |
097f809a NC |
2404 | |
2405 | inline static char * | |
2406 | m32r_end_of_match (char *cont, char *what) | |
2407 | { | |
2408 | int len = strlen (what); | |
2409 | ||
2410 | if (strncasecmp (cont, what, strlen (what)) == 0 | |
2411 | && ! is_part_of_name (cont[len])) | |
2412 | return cont + len; | |
2413 | ||
2414 | return NULL; | |
2415 | } | |
2416 | ||
2417 | int | |
2418 | m32r_parse_name (char const *name, expressionS *exprP, char *nextcharP) | |
2419 | { | |
2420 | char *next = input_line_pointer; | |
2421 | char *next_end; | |
2422 | int reloc_type; | |
2423 | operatorT op_type; | |
2424 | segT segment; | |
2425 | ||
2426 | exprP->X_op_symbol = NULL; | |
2427 | exprP->X_md = BFD_RELOC_UNUSED; | |
2428 | ||
2429 | if (strcmp (name, GOT_NAME) == 0) | |
2430 | { | |
2431 | if (! GOT_symbol) | |
2432 | GOT_symbol = symbol_find_or_make (name); | |
2433 | ||
2434 | exprP->X_add_symbol = GOT_symbol; | |
2435 | no_suffix: | |
2436 | /* If we have an absolute symbol or a | |
2437 | reg, then we know its value now. */ | |
2438 | segment = S_GET_SEGMENT (exprP->X_add_symbol); | |
2439 | if (segment == absolute_section) | |
2440 | { | |
2441 | exprP->X_op = O_constant; | |
2442 | exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); | |
2443 | exprP->X_add_symbol = NULL; | |
2444 | } | |
2445 | else if (segment == reg_section) | |
2446 | { | |
2447 | exprP->X_op = O_register; | |
2448 | exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); | |
2449 | exprP->X_add_symbol = NULL; | |
2450 | } | |
2451 | else | |
2452 | { | |
2453 | exprP->X_op = O_symbol; | |
2454 | exprP->X_add_number = 0; | |
2455 | } | |
2456 | ||
2457 | return 1; | |
2458 | } | |
2459 | ||
2460 | exprP->X_add_symbol = symbol_find_or_make (name); | |
2461 | ||
2462 | if (*nextcharP != '@') | |
2463 | goto no_suffix; | |
2464 | else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF"))) | |
2465 | { | |
2466 | reloc_type = BFD_RELOC_M32R_GOTOFF; | |
2467 | op_type = O_PIC_reloc; | |
2468 | } | |
2469 | else if ((next_end = m32r_end_of_match (next + 1, "GOT"))) | |
2470 | { | |
2471 | reloc_type = BFD_RELOC_M32R_GOT24; | |
2472 | op_type = O_PIC_reloc; | |
2473 | } | |
2474 | else if ((next_end = m32r_end_of_match (next + 1, "PLT"))) | |
2475 | { | |
2476 | reloc_type = BFD_RELOC_M32R_26_PLTREL; | |
2477 | op_type = O_PIC_reloc; | |
2478 | } | |
2479 | else | |
2480 | goto no_suffix; | |
2481 | ||
2482 | *input_line_pointer = *nextcharP; | |
2483 | input_line_pointer = next_end; | |
2484 | *nextcharP = *input_line_pointer; | |
2485 | *input_line_pointer = '\0'; | |
2486 | ||
2487 | exprP->X_op = op_type; | |
2488 | exprP->X_add_number = 0; | |
2489 | exprP->X_md = reloc_type; | |
2490 | ||
2491 | return 1; | |
2492 | } | |
2493 | ||
2494 | int | |
2495 | m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp) | |
2496 | { | |
2497 | if (exp->X_op == O_PIC_reloc | |
2498 | && exp->X_md == BFD_RELOC_M32R_26_PLTREL) | |
2499 | { | |
2500 | exp->X_op = O_symbol; | |
2501 | opinfo = exp->X_md; | |
2502 | } | |
2503 | ||
2504 | return opinfo; | |
2505 | } |