Commit | Line | Data |
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a87b3269 | 1 | /* tc-m68k.c All the m68020 specific stuff in one convenient, huge, |
fecd2382 | 2 | slow to compile, easy to find file. |
6d27d3a2 | 3 | |
bcb8dff8 | 4 | Copyright (C) 1987, 1991, 1992, 1993 Free Software Foundation, Inc. |
6d27d3a2 | 5 | |
a39116f1 | 6 | This file is part of GAS, the GNU Assembler. |
6d27d3a2 | 7 | |
a39116f1 RP |
8 | GAS is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
6d27d3a2 | 12 | |
a39116f1 RP |
13 | GAS is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
6d27d3a2 | 17 | |
a39116f1 RP |
18 | You should have received a copy of the GNU General Public License |
19 | along with GAS; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
fecd2382 RP |
21 | |
22 | #include <ctype.h> | |
f8701a3f | 23 | #define NO_RELOC 0 |
fecd2382 RP |
24 | #include "as.h" |
25 | ||
e284846a KR |
26 | /* need TARGET_CPU */ |
27 | #include "config.h" | |
28 | ||
fecd2382 RP |
29 | #include "obstack.h" |
30 | ||
e284846a KR |
31 | /* The opcode table is too big for gcc, which (currently) requires |
32 | exponential space at compile time for initialized arrays. */ | |
33 | #ifdef __GNUC__ | |
34 | #define DO_BREAK_UP_BIG_DECL | |
35 | #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = { | |
36 | #define AND_OTHER_PART sizeof (m68k_opcodes_2) | |
37 | #endif | |
38 | ||
39 | /* Note that this file includes real declarations and thus can only be | |
40 | included by one source file per executable. */ | |
e0982afe | 41 | #include "opcode/m68k.h" |
3ad9ec6a | 42 | |
49864cfa | 43 | #ifndef BFD_ASSEMBLER |
f6e504fe RP |
44 | #ifdef TE_SUN |
45 | /* This variable contains the value to write out at the beginning of | |
46 | the a.out file. The 2<<16 means that this is a 68020 file instead | |
47 | of an old-style 68000 file */ | |
48 | ||
355afbcd | 49 | long omagic = 2 << 16 | OMAGIC; /* Magic byte for header file */ |
f6e504fe RP |
50 | #else |
51 | long omagic = OMAGIC; | |
52 | #endif | |
49864cfa | 53 | #endif |
fecd2382 RP |
54 | |
55 | /* This array holds the chars that always start a comment. If the | |
56 | pre-processor is disabled, these aren't very useful */ | |
49864cfa | 57 | CONST char comment_chars[] = "|"; |
fecd2382 RP |
58 | |
59 | /* This array holds the chars that only start a comment at the beginning of | |
60 | a line. If the line seems to have the form '# 123 filename' | |
61 | .line and .file directives will appear in the pre-processed output */ | |
62 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
63 | first line of the input file. This is because the compiler outputs | |
64 | #NO_APP at the beginning of its output. */ | |
65 | /* Also note that comments like this one will always work. */ | |
49864cfa | 66 | CONST char line_comment_chars[] = "#"; |
fecd2382 | 67 | |
49864cfa | 68 | CONST char line_separator_chars[] = ""; |
587c4264 | 69 | |
fecd2382 | 70 | /* Chars that can be used to separate mant from exp in floating point nums */ |
49864cfa | 71 | CONST char EXP_CHARS[] = "eE"; |
fecd2382 | 72 | |
49864cfa KR |
73 | /* Chars that mean this number is a floating point constant, as |
74 | in "0f12.456" or "0d1.2345e12". */ | |
fecd2382 | 75 | |
49864cfa | 76 | CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
fecd2382 RP |
77 | |
78 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
79 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
49864cfa | 80 | but nothing is ideal around here. */ |
fecd2382 | 81 | |
49864cfa | 82 | const int md_reloc_size = 8; /* Size of relocation record */ |
fecd2382 | 83 | |
b80d39a0 KR |
84 | /* Are we trying to generate PIC code? If so, absolute references |
85 | ought to be made PC-relative. They aren't yet, but we can parse | |
86 | the option now so the user doesn't get an error... */ | |
87 | int flag_want_pic; | |
88 | ||
fecd2382 RP |
89 | /* Its an arbitrary name: This means I don't approve of it */ |
90 | /* See flames below */ | |
91 | static struct obstack robyn; | |
92 | ||
93 | #define TAB(x,y) (((x)<<2)+(y)) | |
94 | #define TABTYPE(xy) ((xy) >> 2) | |
95 | #define BYTE 0 | |
96 | #define SHORT 1 | |
97 | #define LONG 2 | |
98 | #define SZ_UNDEF 3 | |
3ad9ec6a ILT |
99 | #undef BRANCH |
100 | #define ABRANCH 1 | |
fecd2382 RP |
101 | #define FBRANCH 2 |
102 | #define PCREL 3 | |
103 | #define BCC68000 4 | |
104 | #define DBCC 5 | |
105 | #define PCLEA 6 | |
106 | ||
bcb8dff8 KR |
107 | struct m68k_incant |
108 | { | |
109 | char *m_operands; | |
110 | unsigned long m_opcode; | |
111 | short m_opnum; | |
112 | short m_codenum; | |
113 | int m_arch; | |
114 | struct m68k_incant *m_next; | |
115 | }; | |
116 | ||
117 | #define getone(x) ((((x)->m_opcode)>>16)&0xffff) | |
118 | #define gettwo(x) (((x)->m_opcode)&0xffff) | |
119 | ||
f6e504fe | 120 | /* Operands we can parse: (And associated modes) |
6d27d3a2 | 121 | |
a39116f1 RP |
122 | numb: 8 bit num |
123 | numw: 16 bit num | |
124 | numl: 32 bit num | |
125 | dreg: data reg 0-7 | |
126 | reg: address or data register | |
127 | areg: address register | |
128 | apc: address register, PC, ZPC or empty string | |
129 | num: 16 or 32 bit num | |
130 | num2: like num | |
131 | sz: w or l if omitted, l assumed | |
132 | scale: 1 2 4 or 8 if omitted, 1 assumed | |
6d27d3a2 | 133 | |
a39116f1 RP |
134 | 7.4 IMMED #num --> NUM |
135 | 0.? DREG dreg --> dreg | |
136 | 1.? AREG areg --> areg | |
137 | 2.? AINDR areg@ --> *(areg) | |
138 | 3.? AINC areg@+ --> *(areg++) | |
139 | 4.? ADEC areg@- --> *(--areg) | |
140 | 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here | |
141 | 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale) | |
142 | 6.? AINDX apc@(reg:sz:scale) --> same, with num=0 | |
143 | 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale) | |
144 | 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0 | |
145 | 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg) | |
146 | 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2) | |
147 | 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0 | |
148 | 7.0 ABSL num:sz --> *(num) | |
149 | num --> *(num) (sz L assumed) | |
150 | *** MSCR otherreg --> Magic | |
151 | With -l option | |
152 | 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still | |
c50140c8 | 153 | ?.? DINDR dreg@ --> (dreg) -- cas2 only |
6d27d3a2 | 154 | |
a39116f1 RP |
155 | examples: |
156 | #foo #0x35 #12 | |
157 | d2 | |
158 | a4 | |
159 | a3@ | |
160 | a5@+ | |
161 | a6@- | |
162 | a2@(12) pc@(14) | |
163 | a1@(5,d2:w:1) @(45,d6:l:4) | |
164 | pc@(a2) @(d4) | |
165 | etc . . . | |
6d27d3a2 KR |
166 | |
167 | ||
a39116f1 RP |
168 | #name@(numw) -->turn into PC rel mode |
169 | apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale) | |
6d27d3a2 | 170 | |
a39116f1 | 171 | */ |
f6e504fe | 172 | |
355afbcd KR |
173 | enum operand_type |
174 | { | |
175 | IMMED = 1, | |
176 | DREG, | |
177 | AREG, | |
178 | AINDR, | |
179 | ADEC, | |
180 | AINC, | |
181 | AOFF, | |
182 | AINDX, | |
183 | APODX, | |
184 | AMIND, | |
185 | APRDX, | |
186 | ABSL, | |
187 | MSCR, | |
188 | REGLST, | |
189 | DINDR | |
190 | }; | |
191 | ||
192 | ||
193 | struct m68k_exp | |
194 | { | |
195 | char *e_beg; | |
196 | char *e_end; | |
bcb8dff8 | 197 | segT e_seg; |
355afbcd KR |
198 | expressionS e_exp; |
199 | short e_siz; /* 0== default 1==short/byte 2==word 3==long */ | |
200 | }; | |
fecd2382 | 201 | |
7c15cbe8 RP |
202 | /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg, |
203 | 8-15==addr reg for operands that take both types */ | |
204 | ||
355afbcd KR |
205 | enum _register |
206 | { | |
207 | DATA = 1, /* 1- 8 == data registers 0-7 */ | |
208 | DATA0 = DATA, | |
209 | DATA1, | |
210 | DATA2, | |
211 | DATA3, | |
212 | DATA4, | |
213 | DATA5, | |
214 | DATA6, | |
215 | DATA7, | |
216 | ||
217 | ADDR, | |
218 | ADDR0 = ADDR, | |
219 | ADDR1, | |
220 | ADDR2, | |
221 | ADDR3, | |
222 | ADDR4, | |
223 | ADDR5, | |
224 | ADDR6, | |
225 | ADDR7, | |
226 | ||
227 | /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */ | |
228 | /* I think. . . */ | |
229 | ||
230 | SP = ADDR7, | |
231 | ||
232 | FPREG, /* Eight FP registers */ | |
233 | FP0 = FPREG, | |
234 | FP1, | |
235 | FP2, | |
236 | FP3, | |
237 | FP4, | |
238 | FP5, | |
239 | FP6, | |
240 | FP7, | |
241 | COPNUM = (FPREG + 8), /* Co-processor #1-#8 */ | |
242 | COP0 = COPNUM, | |
243 | COP1, | |
244 | COP2, | |
245 | COP3, | |
246 | COP4, | |
247 | COP5, | |
248 | COP6, | |
249 | COP7, | |
250 | PC, /* Program counter */ | |
251 | ZPC, /* Hack for Program space, but 0 addressing */ | |
252 | SR, /* Status Reg */ | |
253 | CCR, /* Condition code Reg */ | |
254 | ||
255 | /* These have to be in order for the movec instruction to work. */ | |
256 | USP, /* User Stack Pointer */ | |
257 | ISP, /* Interrupt stack pointer */ | |
258 | SFC, | |
259 | DFC, | |
260 | CACR, | |
261 | VBR, | |
262 | CAAR, | |
263 | MSP, | |
264 | ITT0, | |
265 | ITT1, | |
266 | DTT0, | |
267 | DTT1, | |
268 | MMUSR, | |
269 | TC, | |
270 | SRP, | |
271 | URP, | |
272 | /* end of movec ordering constraints */ | |
273 | ||
274 | FPI, | |
275 | FPS, | |
276 | FPC, | |
277 | ||
278 | DRP, /* 68851 or 68030 MMU regs */ | |
279 | CRP, | |
280 | CAL, | |
281 | VAL, | |
282 | SCC, | |
283 | AC, | |
284 | BAD, | |
285 | BAD0 = BAD, | |
286 | BAD1, | |
287 | BAD2, | |
288 | BAD3, | |
289 | BAD4, | |
290 | BAD5, | |
291 | BAD6, | |
292 | BAD7, | |
293 | BAC, | |
294 | BAC0 = BAC, | |
295 | BAC1, | |
296 | BAC2, | |
297 | BAC3, | |
298 | BAC4, | |
299 | BAC5, | |
300 | BAC6, | |
301 | BAC7, | |
302 | PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040) | |
1404ef23 | 303 | and ACUSR on 68ec030 */ |
355afbcd | 304 | PCSR, |
6d27d3a2 | 305 | |
355afbcd KR |
306 | IC, /* instruction cache token */ |
307 | DC, /* data cache token */ | |
308 | NC, /* no cache token */ | |
309 | BC, /* both caches token */ | |
6d27d3a2 | 310 | |
355afbcd KR |
311 | TT0, /* 68030 access control unit regs */ |
312 | TT1, | |
313 | }; | |
7c15cbe8 | 314 | |
fecd2382 | 315 | /* Internal form of an operand. */ |
355afbcd KR |
316 | struct m68k_op |
317 | { | |
318 | char *error; /* Couldn't parse it */ | |
319 | enum operand_type mode; /* What mode this instruction is in. */ | |
320 | enum _register reg; /* Base register */ | |
321 | struct m68k_exp *con1; | |
322 | int ireg; /* Index register */ | |
323 | int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */ | |
324 | int imul; /* Multipy ireg by this (1,2,4,or 8) */ | |
325 | struct m68k_exp *con2; | |
326 | }; | |
fecd2382 RP |
327 | |
328 | /* internal form of a 68020 instruction */ | |
355afbcd KR |
329 | struct m68k_it |
330 | { | |
331 | char *error; | |
332 | char *args; /* list of opcode info */ | |
333 | int numargs; | |
334 | ||
335 | int numo; /* Number of shorts in opcode */ | |
336 | short opcode[11]; | |
337 | ||
338 | struct m68k_op operands[6]; | |
339 | ||
340 | int nexp; /* number of exprs in use */ | |
341 | struct m68k_exp exprs[4]; | |
342 | ||
343 | int nfrag; /* Number of frags we have to produce */ | |
344 | struct | |
345 | { | |
346 | int fragoff; /* Where in the current opcode[] the frag ends */ | |
347 | symbolS *fadd; | |
348 | long foff; | |
349 | int fragty; | |
350 | } | |
351 | fragb[4]; | |
352 | ||
353 | int nrel; /* Num of reloc strucs in use */ | |
354 | struct | |
355 | { | |
356 | int n; | |
bcb8dff8 | 357 | expressionS exp; |
355afbcd KR |
358 | char wid; |
359 | char pcrel; | |
360 | } | |
361 | reloc[5]; /* Five is enough??? */ | |
362 | }; | |
fecd2382 | 363 | |
865a2edf MT |
364 | #define cpu_of_arch(x) ((x) & m68000up) |
365 | #define float_of_arch(x) ((x) & mfloat) | |
366 | #define mmu_of_arch(x) ((x) & mmmu) | |
367 | ||
355afbcd | 368 | static struct m68k_it the_ins; /* the instruction being assembled */ |
fecd2382 | 369 | |
bcb8dff8 KR |
370 | #define seg(exp) ((exp)->e_seg) |
371 | #define op(exp) ((exp)->e_exp.X_op) | |
49864cfa | 372 | #define adds(exp) ((exp)->e_exp.X_add_symbol) |
bcb8dff8 | 373 | #define subs(exp) ((exp)->e_exp.X_op_symbol) |
49864cfa KR |
374 | #define offs(exp) ((exp)->e_exp.X_add_number) |
375 | ||
7c15cbe8 | 376 | /* Macros for adding things to the m68k_it struct */ |
fecd2382 RP |
377 | |
378 | #define addword(w) the_ins.opcode[the_ins.numo++]=(w) | |
379 | ||
380 | /* Like addword, but goes BEFORE general operands */ | |
bcb8dff8 KR |
381 | static void |
382 | insop (w, opcode) | |
383 | int w; | |
384 | struct m68k_incant *opcode; | |
385 | { | |
386 | int z; | |
387 | for(z=the_ins.numo;z>opcode->m_codenum;--z) | |
388 | the_ins.opcode[z]=the_ins.opcode[z-1]; | |
389 | for(z=0;z<the_ins.nrel;z++) | |
390 | the_ins.reloc[z].n+=2; | |
391 | the_ins.opcode[opcode->m_codenum]=w; | |
392 | the_ins.numo++; | |
393 | } | |
fecd2382 | 394 | |
bcb8dff8 KR |
395 | static struct m68k_exp * |
396 | add_exp (beg, end) | |
397 | char *beg; | |
398 | char *end; | |
399 | { | |
400 | the_ins.exprs[the_ins.nexp].e_beg=beg; | |
401 | the_ins.exprs[the_ins.nexp].e_end=end; | |
402 | return &the_ins.exprs[the_ins.nexp++]; | |
403 | } | |
fecd2382 RP |
404 | |
405 | ||
1404ef23 KR |
406 | /* The numo+1 kludge is so we can hit the low order byte of the prev word. |
407 | Blecch. */ | |
49864cfa KR |
408 | static void |
409 | add_fix (width, exp, pc_rel) | |
410 | char width; | |
411 | struct m68k_exp *exp; | |
412 | int pc_rel; | |
413 | { | |
414 | the_ins.reloc[the_ins.nrel].n = (((width)=='B') | |
415 | ? (the_ins.numo*2-1) | |
416 | : (((width)=='b') | |
417 | ? ((the_ins.numo-1)*2) | |
418 | : (the_ins.numo*2))); | |
bcb8dff8 | 419 | the_ins.reloc[the_ins.nrel].exp = exp->e_exp; |
49864cfa KR |
420 | the_ins.reloc[the_ins.nrel].wid = width; |
421 | the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; | |
1404ef23 KR |
422 | } |
423 | ||
49864cfa KR |
424 | static void |
425 | add_frag(add,off,type) | |
426 | symbolS *add; | |
427 | long off; | |
428 | int type; | |
429 | { | |
430 | the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo; | |
431 | the_ins.fragb[the_ins.nfrag].fadd=add; | |
432 | the_ins.fragb[the_ins.nfrag].foff=off; | |
433 | the_ins.fragb[the_ins.nfrag++].fragty=type; | |
1404ef23 | 434 | } |
fecd2382 | 435 | |
bcb8dff8 KR |
436 | #define isvar(exp) \ |
437 | ((exp) && op (exp) != O_constant && op (exp) != O_big) | |
fecd2382 | 438 | |
49864cfa KR |
439 | static char *crack_operand PARAMS ((char *str, struct m68k_op *opP)); |
440 | static int get_num PARAMS ((struct m68k_exp *exp, int ok)); | |
441 | static int get_regs PARAMS ((int i, char *str, struct m68k_op *opP)); | |
442 | static int reverse_16_bits PARAMS ((int in)); | |
443 | static int reverse_8_bits PARAMS ((int in)); | |
444 | static int try_index PARAMS ((char **s, struct m68k_op *opP)); | |
445 | static void install_gen_operand PARAMS ((int mode, int val)); | |
446 | static void install_operand PARAMS ((int mode, int val)); | |
bcb8dff8 KR |
447 | static void s_bss PARAMS ((int)); |
448 | static void s_data1 PARAMS ((int)); | |
449 | static void s_data2 PARAMS ((int)); | |
450 | static void s_even PARAMS ((int)); | |
451 | static void s_proc PARAMS ((int)); | |
49864cfa KR |
452 | |
453 | static int current_architecture; | |
7c15cbe8 | 454 | |
fecd2382 RP |
455 | /* BCC68000 is for patching in an extra jmp instruction for long offsets |
456 | on the 68000. The 68000 doesn't support long branches with branchs */ | |
457 | ||
458 | /* This table desribes how you change sizes for the various types of variable | |
459 | size expressions. This version only supports two kinds. */ | |
460 | ||
49864cfa KR |
461 | /* Note that calls to frag_var need to specify the maximum expansion |
462 | needed; this is currently 10 bytes for DBCC. */ | |
fecd2382 RP |
463 | |
464 | /* The fields are: | |
a39116f1 RP |
465 | How far Forward this mode will reach: |
466 | How far Backward this mode will reach: | |
467 | How many bytes this mode will add to the size of the frag | |
468 | Which mode to go to if the offset won't fit in this one | |
469 | */ | |
49864cfa | 470 | CONST relax_typeS md_relax_table[] = |
355afbcd KR |
471 | { |
472 | {1, 1, 0, 0}, /* First entries aren't used */ | |
473 | {1, 1, 0, 0}, /* For no good reason except */ | |
474 | {1, 1, 0, 0}, /* that the VAX doesn't either */ | |
475 | {1, 1, 0, 0}, | |
476 | ||
477 | {(127), (-128), 0, TAB (ABRANCH, SHORT)}, | |
478 | {(32767), (-32768), 2, TAB (ABRANCH, LONG)}, | |
479 | {0, 0, 4, 0}, | |
480 | {1, 1, 0, 0}, | |
481 | ||
482 | {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */ | |
483 | {(32767), (-32768), 2, TAB (FBRANCH, LONG)}, | |
484 | {0, 0, 4, 0}, | |
485 | {1, 1, 0, 0}, | |
486 | ||
487 | {1, 1, 0, 0}, /* PCREL doesn't come BYTE */ | |
488 | {(32767), (-32768), 2, TAB (PCREL, LONG)}, | |
489 | {0, 0, 4, 0}, | |
490 | {1, 1, 0, 0}, | |
491 | ||
492 | {(127), (-128), 0, TAB (BCC68000, SHORT)}, | |
493 | {(32767), (-32768), 2, TAB (BCC68000, LONG)}, | |
494 | {0, 0, 6, 0}, /* jmp long space */ | |
495 | {1, 1, 0, 0}, | |
496 | ||
497 | {1, 1, 0, 0}, /* DBCC doesn't come BYTE */ | |
498 | {(32767), (-32768), 2, TAB (DBCC, LONG)}, | |
499 | {0, 0, 10, 0}, /* bra/jmp long space */ | |
500 | {1, 1, 0, 0}, | |
501 | ||
502 | {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */ | |
503 | {32767, -32768, 2, TAB (PCLEA, LONG)}, | |
504 | {0, 0, 6, 0}, | |
505 | {1, 1, 0, 0}, | |
506 | ||
507 | }; | |
fecd2382 RP |
508 | |
509 | /* These are the machine dependent pseudo-ops. These are included so | |
510 | the assembler can work on the output from the SUN C compiler, which | |
511 | generates these. | |
a39116f1 | 512 | */ |
fecd2382 RP |
513 | |
514 | /* This table describes all the machine specific pseudo-ops the assembler | |
515 | has to support. The fields are: | |
a39116f1 RP |
516 | pseudo-op name without dot |
517 | function to call to execute this pseudo-op | |
518 | Integer arg to pass to the function | |
519 | */ | |
49864cfa | 520 | CONST pseudo_typeS md_pseudo_table[] = |
355afbcd KR |
521 | { |
522 | {"data1", s_data1, 0}, | |
523 | {"data2", s_data2, 0}, | |
524 | {"bss", s_bss, 0}, | |
525 | {"even", s_even, 0}, | |
526 | {"skip", s_space, 0}, | |
527 | {"proc", s_proc, 0}, | |
bec66218 | 528 | #ifdef TE_SUN3 |
355afbcd | 529 | {"align", s_align_bytes, 0}, |
bec66218 | 530 | #endif |
355afbcd | 531 | {0, 0, 0} |
fecd2382 RP |
532 | }; |
533 | ||
534 | ||
3ad9ec6a | 535 | /* The mote pseudo ops are put into the opcode table, since they |
355afbcd | 536 | don't start with a . they look like opcodes to gas. |
3ad9ec6a | 537 | */ |
355afbcd | 538 | extern void obj_coff_section (); |
3ad9ec6a | 539 | |
49864cfa | 540 | CONST pseudo_typeS mote_pseudo_table[] = |
3ad9ec6a ILT |
541 | { |
542 | ||
355afbcd KR |
543 | {"dc.l", cons, 4}, |
544 | {"dc", cons, 2}, | |
545 | {"dc.w", cons, 2}, | |
546 | {"dc.b", cons, 1}, | |
3ad9ec6a | 547 | |
355afbcd KR |
548 | {"ds.l", s_space, 4}, |
549 | {"ds", s_space, 2}, | |
550 | {"ds.w", s_space, 2}, | |
551 | {"ds.b", s_space, 1}, | |
3ad9ec6a | 552 | |
355afbcd KR |
553 | {"xdef", s_globl, 0}, |
554 | {"align", s_align_ptwo, 0}, | |
3ad9ec6a | 555 | #ifdef M68KCOFF |
355afbcd KR |
556 | {"sect", obj_coff_section, 0}, |
557 | {"section", obj_coff_section, 0}, | |
3ad9ec6a | 558 | #endif |
bcb8dff8 | 559 | {0, 0, 0} |
3ad9ec6a ILT |
560 | }; |
561 | ||
fecd2382 RP |
562 | #define issbyte(x) ((x)>=-128 && (x)<=127) |
563 | #define isubyte(x) ((x)>=0 && (x)<=255) | |
564 | #define issword(x) ((x)>=-32768 && (x)<=32767) | |
565 | #define isuword(x) ((x)>=0 && (x)<=65535) | |
f8701a3f | 566 | |
e284846a | 567 | #define isbyte(x) ((x)>= -255 && (x)<=255) |
fecd2382 RP |
568 | #define isword(x) ((x)>=-32768 && (x)<=65535) |
569 | #define islong(x) (1) | |
f8701a3f SC |
570 | |
571 | extern char *input_line_pointer; | |
fecd2382 | 572 | |
355afbcd KR |
573 | enum |
574 | { | |
575 | FAIL = 0, | |
576 | OK = 1, | |
577 | }; | |
fecd2382 RP |
578 | |
579 | /* JF these tables here are for speed at the expense of size */ | |
580 | /* You can replace them with the #if 0 versions if you really | |
581 | need space and don't mind it running a bit slower */ | |
582 | ||
583 | static char mklower_table[256]; | |
584 | #define mklower(c) (mklower_table[(unsigned char)(c)]) | |
f8701a3f | 585 | static char notend_table[256]; |
fecd2382 RP |
586 | static char alt_notend_table[256]; |
587 | #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\ | |
a39116f1 | 588 | alt_notend_table[(unsigned char)(s[1])]))) |
fecd2382 RP |
589 | |
590 | #if 0 | |
591 | #define mklower(c) (isupper(c) ? tolower(c) : c) | |
592 | #endif | |
f8701a3f SC |
593 | |
594 | ||
595 | /* JF modified this to handle cases where the first part of a symbol name | |
596 | looks like a register */ | |
597 | ||
598 | /* | |
599 | * m68k_reg_parse() := if it looks like a register, return it's token & | |
600 | * advance the pointer. | |
601 | */ | |
602 | ||
355afbcd KR |
603 | enum _register |
604 | m68k_reg_parse (ccp) | |
605 | register char **ccp; | |
fecd2382 | 606 | { |
f8701a3f | 607 | char *start = *ccp; |
0069b1f6 ILT |
608 | char c; |
609 | char *p; | |
610 | symbolS *symbolP; | |
f8701a3f | 611 | |
587c4264 | 612 | #ifdef REGISTER_PREFIX |
0069b1f6 ILT |
613 | if (*start != REGISTER_PREFIX) |
614 | return FAIL; | |
615 | p = start + 1; | |
616 | #else | |
617 | p = start; | |
618 | if (*p == OPTIONAL_REGISTER_PREFIX) | |
619 | p++, start++; | |
587c4264 | 620 | #endif |
0069b1f6 ILT |
621 | if (!isalpha (*p) || !is_name_beginner (*p)) |
622 | return FAIL; | |
587c4264 | 623 | |
0069b1f6 | 624 | c = *p++; |
355afbcd | 625 | while (isalpha (c) || isdigit (c) || c == '_') |
0069b1f6 ILT |
626 | { |
627 | c = *p++; | |
628 | } | |
3ad9ec6a | 629 | |
355afbcd KR |
630 | *--p = 0; |
631 | symbolP = symbol_find (start); | |
632 | *p = c; | |
f8701a3f | 633 | |
49864cfa | 634 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
a39116f1 | 635 | { |
f8701a3f | 636 | *ccp = p; |
355afbcd | 637 | return S_GET_VALUE (symbolP); |
a39116f1 | 638 | } |
f8701a3f | 639 | |
0069b1f6 | 640 | return FAIL; |
fecd2382 RP |
641 | } |
642 | ||
643 | #define SKIP_WHITE() { str++; if(*str==' ') str++;} | |
3ad9ec6a ILT |
644 | #define SKIP_W() { ss++; if(*ss==' ') ss++;} |
645 | ||
646 | /* Parse an index specification using Motorola syntax. */ | |
647 | ||
648 | static int | |
355afbcd KR |
649 | try_moto_index (s, opP) |
650 | char **s; | |
651 | struct m68k_op *opP; | |
3ad9ec6a | 652 | { |
355afbcd KR |
653 | register int i; |
654 | char *ss; | |
655 | ||
656 | ss = *s; | |
657 | /* SKIP_W(); */ | |
658 | if (*ss == ' ') | |
659 | ss++; | |
660 | i = m68k_reg_parse (&ss); | |
661 | if (!(i >= DATA + 0 && i <= ADDR + 7)) | |
662 | { /* if i is not DATA or ADDR reg */ | |
663 | opP->error = "Invalid index register"; | |
664 | *s = ss; | |
665 | return FAIL; | |
666 | } | |
667 | opP->ireg = i; | |
668 | /* SKIP_W(); */ | |
669 | if (*ss == ')') | |
670 | { | |
671 | opP->isiz = 0; | |
672 | opP->imul = 1; | |
673 | SKIP_W (); | |
674 | *s = ss; | |
675 | return OK; | |
676 | } | |
677 | if (*ss != '.') | |
678 | { | |
679 | opP->error = "Missing . in index register"; | |
680 | *s = ss; | |
681 | return FAIL; | |
682 | } | |
683 | SKIP_W (); | |
684 | if (mklower (*ss) == 'w') | |
685 | opP->isiz = 2; | |
686 | else if (mklower (*ss) == 'l') | |
687 | opP->isiz = 3; | |
688 | else | |
689 | { | |
690 | opP->error = "Size spec not .W or .L"; | |
691 | *s = ss; | |
692 | return FAIL; | |
693 | } | |
694 | SKIP_W (); | |
695 | if (*ss == '.' || *ss == '*') | |
696 | { | |
697 | SKIP_W (); | |
698 | switch (*ss) | |
699 | { | |
700 | case '1': | |
701 | case '2': | |
702 | case '4': | |
703 | case '8': | |
704 | opP->imul = *ss - '0'; | |
705 | break; | |
706 | default: | |
707 | opP->error = "index multiplier not 1, 2, 4 or 8"; | |
708 | *s = ss; | |
709 | return FAIL; | |
3ad9ec6a | 710 | } |
355afbcd KR |
711 | SKIP_W (); |
712 | } | |
713 | else | |
714 | opP->imul = 1; | |
715 | if (*ss != ')') | |
716 | { | |
717 | opP->error = "Missing )"; | |
718 | *s = ss; | |
719 | return FAIL; | |
720 | } | |
721 | SKIP_W (); | |
722 | *s = ss; | |
723 | return OK; | |
3ad9ec6a | 724 | } |
fecd2382 | 725 | |
7c15cbe8 | 726 | /* |
3ad9ec6a ILT |
727 | * |
728 | * try_index := data_or_address_register + ')' + SKIP_W | |
729 | * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W | |
730 | * | |
731 | * multiplier := <empty> | |
732 | * | ':' + multiplier_number | |
7c15cbe8 | 733 | * ; |
6d27d3a2 | 734 | * |
3ad9ec6a | 735 | * multiplier_number := '1' | '2' | '4' | '8' ; |
7c15cbe8 | 736 | * |
3ad9ec6a ILT |
737 | * size_spec := 'l' | 'L' | 'w' | 'W' ; |
738 | * | |
739 | * SKIP_W := <empty> | ' ' ; | |
7c15cbe8 RP |
740 | * |
741 | */ | |
742 | ||
355afbcd KR |
743 | static int |
744 | try_index (s, opP) | |
745 | char **s; | |
746 | struct m68k_op *opP; | |
3ad9ec6a | 747 | { |
355afbcd KR |
748 | register int i; |
749 | char *ss; | |
750 | ||
751 | ss = *s; | |
752 | /* SKIP_W(); */ | |
753 | i = m68k_reg_parse (&ss); | |
754 | if (!(i >= DATA + 0 && i <= ADDR + 7)) | |
755 | { /* if i is not DATA or ADDR reg */ | |
756 | *s = ss; | |
757 | return FAIL; | |
758 | } | |
759 | opP->ireg = i; | |
760 | /* SKIP_W(); */ | |
761 | if (*ss == ')') | |
762 | { | |
763 | opP->isiz = 0; | |
764 | opP->imul = 1; | |
765 | SKIP_W (); | |
766 | *s = ss; | |
767 | return OK; | |
768 | } | |
769 | if (*ss != ':') | |
770 | { | |
771 | opP->error = "Missing : in index register"; | |
772 | *s = ss; | |
773 | return FAIL; | |
774 | } | |
775 | SKIP_W (); | |
776 | switch (*ss) | |
777 | { | |
778 | case 'w': | |
779 | case 'W': | |
780 | opP->isiz = 2; | |
781 | break; | |
782 | case 'l': | |
783 | case 'L': | |
784 | opP->isiz = 3; | |
785 | break; | |
786 | default: | |
787 | opP->error = "Index register size spec not :w or :l"; | |
788 | *s = ss; | |
789 | return FAIL; | |
790 | } | |
791 | SKIP_W (); | |
792 | if (*ss == ':') | |
793 | { | |
794 | SKIP_W (); | |
795 | switch (*ss) | |
796 | { | |
797 | case '1': | |
798 | case '2': | |
799 | case '4': | |
800 | case '8': | |
801 | if (cpu_of_arch (current_architecture) < m68020) | |
802 | { | |
803 | opP->error = "no index scaling in pre-68020's"; | |
804 | *s = ss; | |
805 | return FAIL; | |
806 | } | |
807 | opP->imul = *ss - '0'; | |
808 | break; | |
3ad9ec6a | 809 | default: |
355afbcd KR |
810 | opP->error = "index multiplier not 1, 2, 4 or 8"; |
811 | *s = ss; | |
812 | return FAIL; | |
3ad9ec6a | 813 | } |
355afbcd KR |
814 | SKIP_W (); |
815 | } | |
816 | else | |
817 | opP->imul = 1; | |
818 | if (*ss != ')') | |
819 | { | |
820 | opP->error = "Missing )"; | |
821 | *s = ss; | |
822 | return FAIL; | |
823 | } | |
824 | SKIP_W (); | |
825 | *s = ss; | |
826 | return OK; | |
827 | } /* try_index() */ | |
3ad9ec6a ILT |
828 | |
829 | /* Ian Taylor expanded this function to accept both MIT and Motorola | |
830 | syntax. I removed the old comment, since it was wrong. The syntax | |
831 | this accepted even before my changes was complex and undocumented. | |
832 | I mainly added a large case when the operand string does not | |
833 | contain an '@', since the Motorola syntax does not use the '@' | |
834 | character. */ | |
835 | ||
fecd2382 | 836 | int |
355afbcd KR |
837 | m68k_ip_op (str, opP) |
838 | char *str; | |
839 | register struct m68k_op *opP; | |
fecd2382 | 840 | { |
355afbcd KR |
841 | char *strend; |
842 | long i; | |
843 | char *parse_index (); | |
844 | int needp; | |
3ad9ec6a | 845 | |
355afbcd KR |
846 | if (*str == ' ') |
847 | { | |
848 | str++; | |
849 | } /* Find the beginning of the string */ | |
6d27d3a2 | 850 | |
355afbcd KR |
851 | if (!*str) |
852 | { | |
853 | opP->error = "Missing operand"; | |
854 | return FAIL; | |
855 | } /* Out of gas */ | |
6d27d3a2 | 856 | |
355afbcd KR |
857 | for (strend = str; *strend; strend++) |
858 | ; | |
859 | --strend; | |
6d27d3a2 | 860 | |
355afbcd KR |
861 | if (*str == '#') |
862 | { | |
863 | str++; | |
864 | opP->con1 = add_exp (str, strend); | |
865 | opP->mode = IMMED; | |
866 | return OK; | |
867 | } /* Guess what: A constant. Shar and enjoy */ | |
6d27d3a2 | 868 | |
355afbcd | 869 | i = m68k_reg_parse (&str); |
6d27d3a2 | 870 | |
355afbcd KR |
871 | if (i != FAIL) |
872 | { | |
873 | if (*str == '/' || *str == '-') | |
874 | { | |
875 | /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */ | |
876 | opP->mode = REGLST; | |
877 | return get_regs (i, str, opP); | |
878 | } | |
879 | if (*str == '\0') | |
880 | { | |
881 | opP->reg = i; | |
882 | /* "Rn" Register Direct mode */ | |
883 | if (i >= DATA + 0 && i <= DATA + 7) | |
884 | opP->mode = DREG; | |
885 | else if (i >= ADDR + 0 && i <= ADDR + 7) | |
886 | opP->mode = AREG; | |
887 | else | |
888 | opP->mode = MSCR; | |
889 | return OK; | |
890 | } | |
891 | } | |
6d27d3a2 | 892 | |
355afbcd KR |
893 | if (*str != '@') |
894 | { | |
895 | char *stmp; | |
6d27d3a2 | 896 | |
355afbcd KR |
897 | if ((stmp = strchr (str, '@')) != 0) |
898 | { | |
899 | opP->con1 = add_exp (str, stmp - 1); | |
900 | if (stmp == strend) | |
901 | { | |
902 | opP->mode = AINDX; | |
903 | return (OK); | |
904 | } | |
6d27d3a2 | 905 | |
355afbcd KR |
906 | if ((current_architecture & m68020up) == 0) |
907 | { | |
908 | return (FAIL); | |
909 | } /* if target is not a '20 or better */ | |
6d27d3a2 | 910 | |
355afbcd KR |
911 | stmp++; |
912 | if (*stmp++ != '(' || *strend-- != ')') | |
913 | { | |
914 | opP->error = "Malformed operand"; | |
915 | return (FAIL); | |
916 | } | |
917 | i = try_index (&stmp, opP); | |
918 | opP->con2 = add_exp (stmp, strend); | |
6d27d3a2 | 919 | |
355afbcd KR |
920 | if (i == FAIL) |
921 | { | |
922 | opP->mode = AMIND; | |
923 | } | |
924 | else | |
925 | { | |
926 | opP->mode = APODX; | |
927 | } | |
928 | return (OK); | |
929 | } /* if there's an '@' */ | |
6d27d3a2 | 930 | |
3ad9ec6a | 931 | #ifndef MIT_SYNTAX_ONLY |
355afbcd | 932 | /* The operand has no '@'. Try to parse it using |
49864cfa | 933 | Motorola syntax. */ |
355afbcd | 934 | /* Logic of the parsing switch(*str): |
3ad9ec6a ILT |
935 | case opP->mode = |
936 | ---- ----------- | |
937 | #anything IMMED 1 | |
938 | REG AREG or DREG or MSCR 3 or 2 or 13 | |
939 | REG- or REG/ REGLST 14 | |
940 | (REG) AINDR 4 | |
941 | (REG)+ AINC 6 | |
942 | (REG,INDX) AINDX 8 | |
943 | (EXPR,REG) AOFF 7 | |
944 | (EXPR,REG,INDX) AINDX 8 | |
945 | -(REG) ADEC 5 | |
946 | EXP2(REG) AOFF 7 | |
947 | EXP2(REG,INDX) AINDX 8 | |
948 | EXP2 ABSL 12 | |
949 | ||
950 | REG means truth(m68k_reg_parse(&str)) | |
951 | INDX means truth(try_moto_index(&str,opP)) | |
952 | EXPR means not REG | |
953 | EXP2 means not REG and not '(' and not '-(' | |
954 | */ | |
955 | ||
355afbcd KR |
956 | if (*str == '(') |
957 | { | |
958 | str++; | |
959 | i = m68k_reg_parse (&str); | |
960 | if ((i < ADDR + 0 || i > ADDR + 7) | |
961 | && (i < DATA + 0 || i > DATA + 7 | |
962 | || *str != ')' || str[1] != '0') | |
963 | && i != PC && i != ZPC && i != FAIL) | |
964 | { | |
965 | /* Can't indirect off non address regs */ | |
966 | opP->error = "Invalid indirect register"; | |
967 | return FAIL; | |
968 | } | |
969 | if (i != FAIL) | |
970 | { | |
971 | opP->reg = i; | |
972 | if (*str == ')') | |
973 | { | |
974 | str++; | |
975 | if (*str == '\0') | |
976 | { | |
977 | /* "(An)" Address Register Indirect mode | |
3ad9ec6a | 978 | or "(Dn)" for cas2. */ |
355afbcd KR |
979 | if (i >= DATA + 0 && i <= DATA + 7) |
980 | opP->mode = DINDR; | |
981 | else | |
982 | opP->mode = AINDR; | |
983 | return OK; | |
984 | } | |
985 | if (*str == '+') | |
986 | { | |
987 | if (str[1] == '\0') | |
988 | { | |
989 | /* "(An)+" Register Indirect w Postincrement */ | |
990 | opP->mode = AINC; | |
991 | return OK; | |
992 | } | |
993 | } | |
994 | opP->error = "Junk after indirect"; | |
995 | return FAIL; | |
996 | } | |
997 | if (*str == ',') | |
998 | { | |
999 | str++; | |
1000 | i = try_moto_index (&str, opP); | |
1001 | if (i == FAIL) | |
1002 | return FAIL; | |
1003 | /* "(An,Rn)" Register Indirect with Index mode*/ | |
1004 | opP->mode = AINDX; | |
1005 | return OK; | |
1006 | } | |
1007 | else | |
1008 | { | |
1009 | opP->error = "Bad indirect syntax"; | |
1010 | return FAIL; | |
1011 | } | |
1012 | } | |
1013 | else | |
1014 | { | |
1015 | /* "(EXPR,..." , a displacement */ | |
1016 | char *stmp; | |
1017 | char *index (); | |
1018 | ||
bcb8dff8 | 1019 | if ((stmp = index (str, ',')) != NULL) |
355afbcd KR |
1020 | { |
1021 | opP->con1 = add_exp (str, stmp - 1); | |
1022 | str = stmp; | |
1023 | SKIP_WHITE (); | |
1024 | i = m68k_reg_parse (&str); | |
1025 | if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC) | |
1026 | { | |
1027 | /* Can't indirect off non address regs */ | |
1028 | opP->error = "Invalid indirect register"; | |
1029 | return FAIL; | |
1030 | } | |
1031 | if (i != FAIL) | |
1032 | { | |
1033 | opP->reg = i; | |
1034 | if (*str == ')') | |
1035 | { | |
1036 | /* "(d,An)" Register Indirect w Displacement */ | |
1037 | opP->mode = AOFF; | |
1038 | return OK; | |
1039 | } | |
1040 | if (*str == ',') | |
1041 | { | |
1042 | str++; | |
1043 | i = try_moto_index (&str, opP); | |
1044 | if (i == FAIL) | |
1045 | return FAIL; | |
1046 | /* "(d,An,Rn)" Register Indirect with Index */ | |
1047 | opP->mode = AINDX; | |
1048 | return OK; | |
1049 | } | |
1050 | else | |
1051 | { | |
1052 | opP->error = "Bad indirect syntax"; | |
1053 | return FAIL; | |
1054 | } | |
1055 | } | |
1056 | else | |
1057 | { | |
1058 | opP->error = "Invalid register"; | |
1059 | return FAIL; | |
1060 | } | |
1061 | } | |
1062 | else | |
1063 | { | |
1064 | opP->mode = ABSL; | |
1065 | opP->con1 = add_exp (str - 1, strend); | |
1066 | return OK; | |
1067 | } | |
1068 | } | |
1069 | } | |
6d27d3a2 | 1070 | |
355afbcd KR |
1071 | if (*str == '-') |
1072 | { | |
1073 | if (str[1] == '(') | |
1074 | { | |
1075 | str = str + 2; | |
1076 | i = m68k_reg_parse (&str); | |
1077 | if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL) | |
1078 | { | |
1079 | /* Can't indirect off non address regs */ | |
1080 | opP->error = "Invalid indirect register"; | |
1081 | return FAIL; | |
1082 | } | |
1083 | if (i != FAIL) | |
1084 | { | |
1085 | opP->reg = i; | |
1086 | if (*str == ')') | |
1087 | { | |
1088 | str++; | |
1089 | if (*str == '\0') | |
1090 | { | |
1091 | /* "-(An)" Register Indirect with Predecrement */ | |
1092 | opP->mode = ADEC; | |
1093 | return OK; | |
1094 | } | |
1095 | opP->error = "Junk after indirect"; | |
1096 | return FAIL; | |
1097 | } | |
1098 | opP->error = "Bad indirect syntax"; | |
1099 | return FAIL; | |
1100 | } | |
1101 | opP->mode = ABSL; | |
1102 | opP->con1 = add_exp (str - 2, strend); | |
1103 | return OK; | |
1104 | } | |
1105 | /* if '-' but not "-(', do nothing */ | |
1106 | } | |
1107 | ||
1108 | /* whether *str=='-' or not */ | |
1109 | { | |
1110 | /* "EXP2" or "EXP2(REG..." */ | |
1111 | char *stmp; | |
1112 | char *index (); | |
bcb8dff8 | 1113 | if ((stmp = index (str, '(')) != NULL) |
355afbcd KR |
1114 | { |
1115 | char *ostr = str; | |
3ad9ec6a | 1116 | |
355afbcd KR |
1117 | opP->con1 = add_exp (str, stmp - 1); |
1118 | str = stmp + 1; | |
1119 | i = m68k_reg_parse (&str); | |
1120 | if ((i < ADDR + 0 || i > ADDR + 7) && i != PC | |
1121 | && i != ZPC && i != FAIL) | |
1122 | { | |
1123 | /* Can't indirect off non address regs */ | |
1124 | opP->error = "Invalid indirect register"; | |
1125 | return FAIL; | |
1126 | } | |
1127 | if (i != FAIL) | |
1128 | { | |
1129 | opP->reg = i; | |
1130 | if (*str == ')') | |
3ad9ec6a | 1131 | { |
355afbcd KR |
1132 | /* "d(An)" Register Indirect w Displacement */ |
1133 | opP->mode = AOFF; | |
1134 | return OK; | |
3ad9ec6a | 1135 | } |
355afbcd KR |
1136 | if (*str == ',') |
1137 | { | |
1138 | str++; | |
1139 | i = try_moto_index (&str, opP); | |
1140 | if (i == FAIL) | |
1141 | return FAIL; | |
1142 | /* "d(An,Rn)" Register Indirect with Index */ | |
1143 | opP->mode = AINDX; | |
1144 | return OK; | |
1145 | } | |
1146 | else | |
1147 | { | |
1148 | opP->error = "Bad indirect syntax"; | |
1149 | return FAIL; | |
1150 | } | |
1151 | } | |
1152 | else | |
1153 | { | |
1154 | opP->mode = ABSL; | |
1155 | opP->con1 = add_exp (ostr, strend); | |
f8701a3f | 1156 | return OK; |
3ad9ec6a | 1157 | } |
355afbcd KR |
1158 | } |
1159 | else | |
1160 | { | |
1161 | /* "EXP2" Absolute */ | |
1162 | opP->mode = ABSL; | |
1163 | opP->isiz = 0; | |
1164 | if (strend[-1] == '.' || strend[-1] == ':') | |
1165 | { | |
1166 | /* mode ==foo.[wl] */ | |
1167 | switch (*strend) | |
1168 | { | |
1169 | case 'w': | |
1170 | case 'W': | |
1171 | opP->isiz = 2; | |
355afbcd KR |
1172 | break; |
1173 | case 'l': | |
1174 | case 'L': | |
1175 | opP->isiz = 3; | |
355afbcd KR |
1176 | break; |
1177 | } | |
1178 | } | |
1179 | opP->con1 = add_exp (str, strend); | |
1180 | return OK; | |
1181 | } | |
1182 | } | |
1183 | /*NOTREACHED*/ | |
1184 | #else /* defined (MIT_SYNTAX_ONLY) */ | |
1185 | opP->mode = ABSL; | |
1186 | opP->con1 = add_exp (str, strend); | |
1187 | return OK; | |
1188 | #endif /* defined (MIT_SYNTAX_ONLY) */ | |
1189 | } | |
3ad9ec6a | 1190 | |
355afbcd | 1191 | opP->reg = i; |
6d27d3a2 | 1192 | |
355afbcd KR |
1193 | /* Can't indirect off non address regs, but Dx@ is OK for cas2 */ |
1194 | if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL | |
1195 | && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7)) | |
1196 | { | |
1197 | opP->error = "Invalid indirect register"; | |
1198 | return FAIL; | |
1199 | } | |
1200 | know (*str == '@'); | |
6d27d3a2 | 1201 | |
355afbcd KR |
1202 | str++; |
1203 | switch (*str) | |
1204 | { | |
1205 | case '\0': | |
1206 | if (i < DATA + 0 || i > DATA + 7) | |
1207 | opP->mode = AINDR; | |
1208 | else | |
1209 | opP->mode = DINDR; | |
1210 | return OK; | |
1211 | case '-': | |
1212 | opP->mode = ADEC; | |
1213 | return OK; | |
1214 | case '+': | |
1215 | opP->mode = AINC; | |
1216 | return OK; | |
1217 | case '(': | |
1218 | str++; | |
1219 | break; | |
1220 | default: | |
1221 | opP->error = "Junk after indirect"; | |
1222 | return FAIL; | |
1223 | } | |
1224 | /* Some kind of indexing involved. Lets find out how bad it is */ | |
1225 | i = try_index (&str, opP); | |
1226 | /* Didn't start with an index reg, maybe its offset or offset,reg */ | |
1227 | if (i == FAIL) | |
1228 | { | |
1229 | char *beg_str; | |
1230 | ||
1231 | beg_str = str; | |
1232 | for (i = 1; i;) | |
1233 | { | |
1234 | switch (*str++) | |
1235 | { | |
1236 | case '\0': | |
1237 | opP->error = "Missing )"; | |
1238 | return FAIL; | |
1239 | case ',': | |
1240 | i = 0; | |
1241 | break; | |
1242 | case '(': | |
1243 | i++; | |
1244 | break; | |
1245 | case ')': | |
1246 | --i; | |
1247 | break; | |
1248 | } | |
fecd2382 | 1249 | } |
49864cfa KR |
1250 | #if 0 |
1251 | if (str[-3]==':') | |
1252 | { | |
1253 | int siz; | |
1254 | ||
1255 | switch (str[-2]) | |
1256 | { | |
1257 | case 'b': | |
1258 | case 'B': | |
1259 | siz=1; | |
1260 | break; | |
1261 | case 'w': | |
1262 | case 'W': | |
1263 | siz=2; | |
1264 | break; | |
1265 | case 'l': | |
1266 | case 'L': | |
1267 | siz=3; | |
1268 | break; | |
1269 | default: | |
1270 | opP->error="Specified size isn't :w or :l"; | |
1271 | return FAIL; | |
1272 | } | |
1273 | opP->con1=add_exp(beg_str,str-4); | |
1274 | opP->con1->e_siz=siz; | |
1275 | } | |
1276 | else | |
1277 | #endif | |
1278 | opP->con1 = add_exp (beg_str, str - 2); | |
355afbcd KR |
1279 | /* Should be offset,reg */ |
1280 | if (str[-1] == ',') | |
1281 | { | |
1282 | i = try_index (&str, opP); | |
1283 | if (i == FAIL) | |
1284 | { | |
1285 | opP->error = "Malformed index reg"; | |
1286 | return FAIL; | |
1287 | } | |
f8701a3f | 1288 | } |
355afbcd KR |
1289 | } |
1290 | /* We've now got offset) offset,reg) or reg) */ | |
1291 | ||
1292 | if (*str == '\0') | |
1293 | { | |
1294 | /* Th-the-thats all folks */ | |
1295 | if (opP->reg == FAIL) | |
1296 | opP->mode = AINDX; /* Other form of indirect */ | |
1297 | else if (opP->ireg == FAIL) | |
1298 | opP->mode = AOFF; | |
1299 | else | |
1300 | opP->mode = AINDX; | |
1301 | return (OK); | |
1302 | } | |
1303 | /* Next thing had better be another @ */ | |
1304 | if (*str == '@') | |
1305 | { | |
1306 | if (str[1] == '(') | |
1307 | { | |
1308 | needp = 1; | |
1309 | str += 2; | |
f8701a3f | 1310 | } |
355afbcd KR |
1311 | else |
1312 | { | |
1313 | needp = 0; | |
1314 | str++; | |
fecd2382 | 1315 | } |
355afbcd | 1316 | } |
6d27d3a2 | 1317 | |
355afbcd KR |
1318 | if ((current_architecture & m68020up) == 0) |
1319 | { | |
1320 | return (FAIL); | |
1321 | } /* if target is not a '20 or better */ | |
6d27d3a2 KR |
1322 | |
1323 | ||
355afbcd KR |
1324 | if (opP->ireg != FAIL) |
1325 | { | |
1326 | opP->mode = APRDX; | |
6d27d3a2 | 1327 | |
355afbcd KR |
1328 | i = try_index (&str, opP); |
1329 | if (i != FAIL) | |
1330 | { | |
1331 | opP->error = "Two index registers! not allowed!"; | |
1332 | return (FAIL); | |
865a2edf | 1333 | } |
355afbcd KR |
1334 | } |
1335 | else | |
1336 | { | |
1337 | i = try_index (&str, opP); | |
1338 | } | |
6d27d3a2 | 1339 | |
355afbcd KR |
1340 | if (i == FAIL) |
1341 | { | |
1342 | char *beg_str; | |
6d27d3a2 | 1343 | |
355afbcd | 1344 | beg_str = str; |
6d27d3a2 | 1345 | |
355afbcd KR |
1346 | for (i = 1; i;) |
1347 | { | |
1348 | switch (*str++) | |
1349 | { | |
1350 | case '\0': | |
1351 | if (needp) | |
1352 | opP->error = "Missing )"; | |
1353 | return (FAIL); | |
1354 | break; | |
1355 | case ',': | |
1356 | i = 0; | |
1357 | break; | |
1358 | case '(': | |
1359 | i++; | |
1360 | break; | |
1361 | case ')': | |
1362 | --i; | |
1363 | break; | |
1364 | } | |
1365 | } | |
6d27d3a2 | 1366 | |
355afbcd | 1367 | opP->con2 = add_exp (beg_str, str - 2); |
6d27d3a2 | 1368 | |
355afbcd KR |
1369 | if (str[-1] == ',') |
1370 | { | |
1371 | if (opP->ireg != FAIL) | |
1372 | { | |
1373 | opP->error = "Can't have two index regs"; | |
1374 | return (FAIL); | |
1375 | } | |
6d27d3a2 | 1376 | |
355afbcd | 1377 | i = try_index (&str, opP); |
6d27d3a2 | 1378 | |
355afbcd KR |
1379 | if (i == FAIL) |
1380 | { | |
1381 | opP->error = "malformed index reg"; | |
1382 | return (FAIL); | |
1383 | } | |
6d27d3a2 | 1384 | |
355afbcd | 1385 | opP->mode = APODX; |
f8701a3f | 1386 | } |
355afbcd KR |
1387 | else if (opP->ireg != FAIL) |
1388 | { | |
1389 | opP->mode = APRDX; | |
1390 | } | |
1391 | else | |
1392 | { | |
1393 | opP->mode = AMIND; | |
f8701a3f | 1394 | } |
355afbcd KR |
1395 | } |
1396 | else | |
1397 | { | |
1398 | opP->mode = APODX; | |
1399 | } | |
1400 | ||
1401 | if (*str != '\0') | |
1402 | { | |
1403 | opP->error = "Junk after indirect"; | |
1404 | return FAIL; | |
1405 | } | |
1406 | return (OK); | |
1407 | } /* m68k_ip_op() */ | |
fecd2382 | 1408 | |
7c15cbe8 | 1409 | |
49864cfa | 1410 | #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER) |
3ad9ec6a | 1411 | |
355afbcd KR |
1412 | short |
1413 | tc_coff_fix2rtype (fixP) | |
1414 | fixS *fixP; | |
fecd2382 | 1415 | { |
355afbcd KR |
1416 | return (fixP->fx_pcrel ? |
1417 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
1418 | fixP->fx_size == 2 ? R_PCRWORD : | |
1419 | R_PCRLONG) : | |
1420 | (fixP->fx_size == 1 ? R_RELBYTE : | |
1421 | fixP->fx_size == 2 ? R_RELWORD : | |
1422 | R_RELLONG)); | |
6d27d3a2 | 1423 | |
3ad9ec6a ILT |
1424 | |
1425 | } | |
1426 | ||
1427 | #endif | |
fecd2382 | 1428 | |
49864cfa KR |
1429 | #ifdef BFD_ASSEMBLER |
1430 | ||
1431 | arelent * | |
1432 | tc_gen_reloc (section, fixp) | |
1433 | asection *section; | |
1434 | fixS *fixp; | |
1435 | { | |
1436 | arelent *reloc; | |
1437 | bfd_reloc_code_real_type code; | |
1438 | ||
1439 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) | |
1440 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
1441 | { | |
1442 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
1443 | MAP (1, 0, BFD_RELOC_8); | |
1444 | MAP (2, 0, BFD_RELOC_16); | |
1445 | MAP (4, 0, BFD_RELOC_32); | |
1446 | MAP (1, 1, BFD_RELOC_8_PCREL); | |
1447 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
1448 | MAP (4, 1, BFD_RELOC_32_PCREL); | |
1449 | default: | |
1450 | abort (); | |
1451 | } | |
1452 | ||
1453 | reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent)); | |
1454 | assert (reloc != 0); | |
1455 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
1456 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1457 | if (fixp->fx_pcrel) | |
1458 | reloc->addend = fixp->fx_addnumber; | |
1459 | else | |
1460 | reloc->addend = 0; | |
1461 | ||
1462 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
1463 | assert (reloc->howto != 0); | |
1464 | ||
1465 | return reloc; | |
1466 | } | |
1467 | ||
1468 | #endif /* BFD_ASSEMBLER */ | |
1469 | ||
355afbcd KR |
1470 | #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */ |
1471 | main () | |
fecd2382 | 1472 | { |
355afbcd KR |
1473 | char buf[128]; |
1474 | struct m68k_op thark; | |
6d27d3a2 | 1475 | |
355afbcd KR |
1476 | for (;;) |
1477 | { | |
1478 | if (!gets (buf)) | |
1479 | break; | |
1480 | memset (&thark, '\0', sizeof (thark)); | |
1481 | if (!m68k_ip_op (buf, &thark)) | |
1482 | printf ("FAIL:"); | |
1483 | if (thark.error) | |
1484 | printf ("op1 error %s in %s\n", thark.error, buf); | |
1485 | printf ("mode %d, reg %d, ", thark.mode, thark.reg); | |
1486 | if (thark.b_const) | |
1487 | printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const); | |
1488 | printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul); | |
1489 | if (thark.b_iadd) | |
1490 | printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd); | |
1491 | printf ("\n"); | |
1492 | } | |
1493 | exit (0); | |
fecd2382 RP |
1494 | } |
1495 | ||
1496 | #endif | |
1497 | ||
1498 | ||
49864cfa KR |
1499 | /* Handle of the OPCODE hash table. NULL means any use before |
1500 | m68k_ip_begin() will crash. */ | |
1501 | static struct hash_control *op_hash; | |
fecd2382 | 1502 | \f |
355afbcd | 1503 | |
fecd2382 | 1504 | /* |
7c15cbe8 | 1505 | * m 6 8 k _ i p ( ) |
fecd2382 RP |
1506 | * |
1507 | * This converts a string into a 68k instruction. | |
1508 | * The string must be a bare single instruction in sun format | |
1509 | * with RMS-style 68020 indirects | |
1510 | * (example: ) | |
1511 | * | |
1512 | * It provides some error messages: at most one fatal error message (which | |
1513 | * stops the scan) and at most one warning message for each operand. | |
1514 | * The 68k instruction is returned in exploded form, since we have no | |
1515 | * knowledge of how you parse (or evaluate) your expressions. | |
1516 | * We do however strip off and decode addressing modes and operation | |
1517 | * mnemonic. | |
1518 | * | |
1519 | * This function's value is a string. If it is not "" then an internal | |
1520 | * logic error was found: read this code to assign meaning to the string. | |
1521 | * No argument string should generate such an error string: | |
1522 | * it means a bug in our code, not in the user's text. | |
1523 | * | |
7c15cbe8 | 1524 | * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using |
fecd2382 RP |
1525 | * this function. |
1526 | */ | |
1527 | ||
1528 | /* JF this function no longer returns a useful value. Sorry */ | |
355afbcd KR |
1529 | void |
1530 | m68k_ip (instring) | |
6d27d3a2 | 1531 | char *instring; |
fecd2382 | 1532 | { |
6d27d3a2 KR |
1533 | register char *p; |
1534 | register struct m68k_op *opP; | |
1535 | register struct m68k_incant *opcode; | |
1536 | register char *s; | |
1537 | register int tmpreg = 0, baseo = 0, outro = 0, nextword; | |
3ad9ec6a | 1538 | char *pdot, *pdotmove; |
6d27d3a2 | 1539 | int siz1, siz2; |
355afbcd KR |
1540 | char c; |
1541 | int losing; | |
1542 | int opsfound; | |
1543 | char *crack_operand (); | |
6d27d3a2 KR |
1544 | LITTLENUM_TYPE words[6]; |
1545 | LITTLENUM_TYPE *wordp; | |
8be74775 | 1546 | unsigned long ok_arch = 0; |
6d27d3a2 KR |
1547 | |
1548 | if (*instring == ' ') | |
1549 | instring++; /* skip leading whitespace */ | |
1550 | ||
1551 | /* Scan up to end of operation-code, which MUST end in end-of-string | |
1552 | or exactly 1 space. */ | |
3ad9ec6a | 1553 | pdot = 0; |
355afbcd KR |
1554 | for (p = instring; *p != '\0'; p++) |
1555 | { | |
1556 | if (*p == ' ') | |
1557 | break; | |
1558 | if (*p == '.') | |
1559 | pdot = p; | |
1560 | } | |
6d27d3a2 | 1561 | |
355afbcd KR |
1562 | if (p == instring) |
1563 | { | |
1564 | the_ins.error = "No operator"; | |
bcb8dff8 | 1565 | the_ins.opcode[0] = 0; |
355afbcd KR |
1566 | /* the_ins.numo=1; */ |
1567 | return; | |
1568 | } | |
6d27d3a2 KR |
1569 | |
1570 | /* p now points to the end of the opcode name, probably whitespace. | |
1571 | make sure the name is null terminated by clobbering the whitespace, | |
3ad9ec6a ILT |
1572 | look it up in the hash table, then fix it back. |
1573 | Remove a dot, first, since the opcode tables have none. */ | |
355afbcd KR |
1574 | if (pdot != NULL) |
1575 | { | |
1576 | for (pdotmove = pdot; pdotmove < p; pdotmove++) | |
1577 | *pdotmove = pdotmove[1]; | |
1578 | p--; | |
1579 | } | |
3ad9ec6a | 1580 | |
6d27d3a2 KR |
1581 | c = *p; |
1582 | *p = '\0'; | |
355afbcd | 1583 | opcode = (struct m68k_incant *) hash_find (op_hash, instring); |
6d27d3a2 KR |
1584 | *p = c; |
1585 | ||
355afbcd KR |
1586 | if (pdot != NULL) |
1587 | { | |
1588 | for (pdotmove = p; pdotmove > pdot; pdotmove--) | |
1589 | *pdotmove = pdotmove[-1]; | |
1590 | *pdot = '.'; | |
1591 | ++p; | |
1592 | } | |
3ad9ec6a | 1593 | |
355afbcd KR |
1594 | if (opcode == NULL) |
1595 | { | |
1596 | the_ins.error = "Unknown operator"; | |
bcb8dff8 | 1597 | the_ins.opcode[0] = 0; |
355afbcd KR |
1598 | /* the_ins.numo=1; */ |
1599 | return; | |
1600 | } | |
6d27d3a2 KR |
1601 | |
1602 | /* found a legitimate opcode, start matching operands */ | |
355afbcd KR |
1603 | while (*p == ' ') |
1604 | ++p; | |
6d27d3a2 | 1605 | |
3ad9ec6a | 1606 | |
355afbcd KR |
1607 | if (opcode->m_operands == 0) |
1608 | { | |
1609 | char *old = input_line_pointer; | |
1610 | *old = '\n'; | |
1611 | input_line_pointer = p; | |
1612 | /* Ahh - it's a motorola style psuedo op */ | |
1613 | mote_pseudo_table[opcode->m_opnum].poc_handler | |
1614 | (mote_pseudo_table[opcode->m_opnum].poc_val); | |
1615 | input_line_pointer = old; | |
1616 | *old = 0; | |
3ad9ec6a | 1617 | |
355afbcd KR |
1618 | return; |
1619 | } | |
3ad9ec6a | 1620 | |
355afbcd KR |
1621 | for (opP = &the_ins.operands[0]; *p; opP++) |
1622 | { | |
6d27d3a2 | 1623 | |
355afbcd | 1624 | p = crack_operand (p, opP); |
6d27d3a2 | 1625 | |
355afbcd KR |
1626 | if (opP->error) |
1627 | { | |
1628 | the_ins.error = opP->error; | |
1629 | return; | |
1630 | } | |
6d27d3a2 | 1631 | } |
6d27d3a2 KR |
1632 | |
1633 | opsfound = opP - &the_ins.operands[0]; | |
1634 | ||
1635 | /* This ugly hack is to support the floating pt opcodes in their standard form */ | |
1636 | /* Essentially, we fake a first enty of type COP#1 */ | |
355afbcd KR |
1637 | if (opcode->m_operands[0] == 'I') |
1638 | { | |
1639 | int n; | |
6d27d3a2 | 1640 | |
355afbcd KR |
1641 | for (n = opsfound; n > 0; --n) |
1642 | the_ins.operands[n] = the_ins.operands[n - 1]; | |
6d27d3a2 | 1643 | |
355afbcd KR |
1644 | memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0])); |
1645 | the_ins.operands[0].mode = MSCR; | |
1646 | the_ins.operands[0].reg = COPNUM; /* COP #1 */ | |
1647 | opsfound++; | |
1648 | } | |
6d27d3a2 KR |
1649 | |
1650 | /* We've got the operands. Find an opcode that'll accept them */ | |
355afbcd KR |
1651 | for (losing = 0;;) |
1652 | { | |
49864cfa KR |
1653 | /* If we didn't get the right number of ops, or we have no |
1654 | common model with this pattern then reject this pattern. */ | |
6d27d3a2 | 1655 | |
355afbcd KR |
1656 | if (opsfound != opcode->m_opnum |
1657 | || ((opcode->m_arch & current_architecture) == 0)) | |
1658 | { | |
1659 | ++losing; | |
1660 | ok_arch |= opcode->m_arch; | |
1661 | } | |
1662 | else | |
1663 | { | |
1664 | for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) | |
1665 | { | |
1666 | /* Warning: this switch is huge! */ | |
49864cfa KR |
1667 | /* I've tried to organize the cases into this order: |
1668 | non-alpha first, then alpha by letter. Lower-case | |
1669 | goes directly before uppercase counterpart. */ | |
1670 | /* Code with multiple case ...: gets sorted by the lowest | |
1671 | case ... it belongs to. I hope this makes sense. */ | |
355afbcd KR |
1672 | switch (*s) |
1673 | { | |
1674 | case '!': | |
1675 | if (opP->mode == MSCR || opP->mode == IMMED | |
1676 | || opP->mode == DREG || opP->mode == AREG | |
1677 | || opP->mode == AINC || opP->mode == ADEC | |
1678 | || opP->mode == REGLST) | |
1679 | losing++; | |
1680 | break; | |
1681 | ||
1682 | case '`': | |
1683 | switch (opP->mode) | |
1684 | { | |
1685 | case MSCR: | |
1686 | case IMMED: | |
1687 | case DREG: | |
1688 | case AREG: | |
1689 | case AINC: | |
1690 | case REGLST: | |
1691 | case AINDR: | |
1692 | losing++; | |
bcb8dff8 KR |
1693 | break; |
1694 | default: | |
1695 | break; | |
355afbcd KR |
1696 | } |
1697 | break; | |
8be74775 | 1698 | |
355afbcd KR |
1699 | case '#': |
1700 | if (opP->mode != IMMED) | |
1701 | losing++; | |
1702 | else | |
1703 | { | |
1704 | long t; | |
1705 | ||
1706 | t = get_num (opP->con1, 80); | |
1707 | if (s[1] == 'b' && !isbyte (t)) | |
1708 | losing++; | |
1709 | else if (s[1] == 'w' && !isword (t)) | |
1710 | losing++; | |
1711 | } | |
1712 | break; | |
1713 | ||
1714 | case '^': | |
1715 | case 'T': | |
1716 | if (opP->mode != IMMED) | |
1717 | losing++; | |
1718 | break; | |
1719 | ||
1720 | case '$': | |
1721 | if (opP->mode == MSCR || opP->mode == AREG || | |
1722 | opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST) | |
1723 | losing++; | |
1724 | break; | |
1725 | ||
1726 | case '%': | |
1727 | if (opP->mode == MSCR || opP->reg == PC || | |
1728 | opP->reg == ZPC || opP->mode == REGLST) | |
1729 | losing++; | |
1730 | break; | |
1731 | ||
1732 | ||
1733 | case '&': | |
1734 | if (opP->mode == MSCR || opP->mode == DREG || | |
1735 | opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || | |
1736 | opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST) | |
1737 | losing++; | |
1738 | break; | |
1739 | ||
1740 | case '*': | |
1741 | if (opP->mode == MSCR || opP->mode == REGLST) | |
1742 | losing++; | |
1743 | break; | |
1744 | ||
1745 | case '+': | |
1746 | if (opP->mode != AINC) | |
1747 | losing++; | |
1748 | break; | |
1749 | ||
1750 | case '-': | |
1751 | if (opP->mode != ADEC) | |
1752 | losing++; | |
1753 | break; | |
1754 | ||
1755 | case '/': | |
1756 | if (opP->mode == MSCR || opP->mode == AREG || | |
1757 | opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST) | |
1758 | losing++; | |
1759 | break; | |
1760 | ||
1761 | case ';': | |
1762 | if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST) | |
1763 | losing++; | |
1764 | break; | |
1765 | ||
1766 | case '?': | |
1767 | if (opP->mode == MSCR || opP->mode == AREG || | |
1768 | opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC || | |
1769 | opP->reg == ZPC || opP->mode == REGLST) | |
1770 | losing++; | |
1771 | break; | |
1772 | ||
1773 | case '@': | |
1774 | if (opP->mode == MSCR || opP->mode == AREG || | |
1775 | opP->mode == IMMED || opP->mode == REGLST) | |
1776 | losing++; | |
1777 | break; | |
1778 | ||
1779 | case '~': /* For now! (JF FOO is this right?) */ | |
1780 | if (opP->mode == MSCR || opP->mode == DREG || | |
1781 | opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST) | |
1782 | losing++; | |
1783 | break; | |
1784 | ||
1785 | case '3': | |
1786 | if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1)) | |
1787 | losing++; | |
1788 | break; | |
1789 | ||
1790 | case 'A': | |
1791 | if (opP->mode != AREG) | |
1792 | losing++; | |
1793 | break; | |
1794 | case 'a': | |
1795 | if (opP->mode != AINDR) | |
1796 | { | |
1797 | ++losing; | |
1798 | } /* if not address register indirect */ | |
1799 | break; | |
1800 | case 'B': /* FOO */ | |
1801 | if (opP->mode != ABSL || (flagseen['S'] && instring[0] == 'j' | |
1802 | && instring[1] == 'b' | |
1803 | && instring[2] == 's' | |
1804 | && instring[3] == 'r')) | |
1805 | losing++; | |
1806 | break; | |
1807 | ||
1808 | case 'C': | |
1809 | if (opP->mode != MSCR || opP->reg != CCR) | |
1810 | losing++; | |
1811 | break; | |
1812 | ||
1813 | case 'd': /* FOO This mode is a KLUDGE!! */ | |
1814 | if (opP->mode != AOFF && (opP->mode != ABSL || | |
1815 | opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')')) | |
1816 | losing++; | |
1817 | break; | |
1818 | ||
1819 | case 'D': | |
1820 | if (opP->mode != DREG) | |
1821 | losing++; | |
1822 | break; | |
1823 | ||
1824 | case 'F': | |
1825 | if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7)) | |
1826 | losing++; | |
1827 | break; | |
1828 | ||
1829 | case 'I': | |
1830 | if (opP->mode != MSCR || opP->reg < COPNUM || | |
1831 | opP->reg >= COPNUM + 7) | |
1832 | losing++; | |
1833 | break; | |
1834 | ||
1835 | case 'J': | |
1836 | if (opP->mode != MSCR | |
1837 | || opP->reg < USP | |
1838 | || opP->reg > URP | |
1839 | || cpu_of_arch (current_architecture) < m68010 /* before 68010 had none */ | |
1840 | || (cpu_of_arch (current_architecture) < m68020 | |
1841 | && opP->reg != SFC | |
1842 | && opP->reg != DFC | |
1843 | && opP->reg != USP | |
1844 | && opP->reg != VBR) /* 68010's had only these */ | |
1845 | || (cpu_of_arch (current_architecture) < m68040 | |
1846 | && opP->reg != SFC | |
1847 | && opP->reg != DFC | |
1848 | && opP->reg != USP | |
1849 | && opP->reg != VBR | |
1850 | && opP->reg != CACR | |
1851 | && opP->reg != CAAR | |
1852 | && opP->reg != MSP | |
1853 | && opP->reg != ISP) /* 680[23]0's have only these */ | |
1854 | || (cpu_of_arch (current_architecture) == m68040 /* 68040 has all but this */ | |
1855 | && opP->reg == CAAR)) | |
1856 | { | |
1857 | losing++; | |
1858 | } /* doesn't cut it */ | |
1859 | break; | |
1860 | ||
1861 | case 'k': | |
1862 | if (opP->mode != IMMED) | |
1863 | losing++; | |
1864 | break; | |
8be74775 | 1865 | |
355afbcd KR |
1866 | case 'l': |
1867 | case 'L': | |
1868 | if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG) | |
1869 | { | |
1870 | if (s[1] == '8') | |
1871 | losing++; | |
1872 | else | |
1873 | { | |
1874 | opP->mode = REGLST; | |
1875 | opP->reg = 1 << (opP->reg - DATA); | |
1876 | } | |
1877 | } | |
1878 | else if (opP->mode != REGLST) | |
1879 | { | |
1880 | losing++; | |
1881 | } | |
1882 | else if (s[1] == '8' && opP->reg & 0x0FFffFF) | |
1883 | losing++; | |
1884 | else if (s[1] == '3' && opP->reg & 0x7000000) | |
1885 | losing++; | |
1886 | break; | |
1887 | ||
1888 | case 'M': | |
1889 | if (opP->mode != IMMED) | |
1890 | losing++; | |
1891 | else | |
1892 | { | |
1893 | long t; | |
6d27d3a2 | 1894 | |
49864cfa KR |
1895 | t = get_num (opP->con1, 0); |
1896 | if (!issbyte (t) | |
bcb8dff8 | 1897 | || isvar (opP->con1)) |
355afbcd KR |
1898 | losing++; |
1899 | } | |
1900 | break; | |
8be74775 | 1901 | |
355afbcd KR |
1902 | case 'O': |
1903 | if (opP->mode != DREG && opP->mode != IMMED) | |
1904 | losing++; | |
1905 | break; | |
6d27d3a2 | 1906 | |
355afbcd KR |
1907 | case 'Q': |
1908 | if (opP->mode != IMMED) | |
1909 | losing++; | |
1910 | else | |
1911 | { | |
1912 | long t; | |
6d27d3a2 | 1913 | |
355afbcd KR |
1914 | t = get_num (opP->con1, 80); |
1915 | if (t < 1 || t > 8 || isvar (opP->con1)) | |
1916 | losing++; | |
1917 | } | |
1918 | break; | |
8be74775 | 1919 | |
355afbcd KR |
1920 | case 'R': |
1921 | if (opP->mode != DREG && opP->mode != AREG) | |
1922 | losing++; | |
1923 | break; | |
8be74775 | 1924 | |
355afbcd KR |
1925 | case 'r': |
1926 | if (opP->mode != AINDR && opP->mode != DINDR) | |
1927 | losing++; | |
1928 | break; | |
c50140c8 | 1929 | |
355afbcd KR |
1930 | case 's': |
1931 | if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC)) | |
1932 | losing++; | |
1933 | break; | |
8be74775 | 1934 | |
355afbcd KR |
1935 | case 'S': |
1936 | if (opP->mode != MSCR || opP->reg != SR) | |
1937 | losing++; | |
1938 | break; | |
8be74775 | 1939 | |
355afbcd KR |
1940 | case 't': |
1941 | if (opP->mode != IMMED) | |
1942 | losing++; | |
1943 | else | |
1944 | { | |
1945 | long t = get_num (opP->con1, 80); | |
1946 | if (t < 0 || t > 7 || isvar (opP->con1)) | |
1947 | losing++; | |
1948 | } | |
1949 | break; | |
4134a793 | 1950 | |
355afbcd KR |
1951 | case 'U': |
1952 | if (opP->mode != MSCR || opP->reg != USP) | |
1953 | losing++; | |
1954 | break; | |
8be74775 | 1955 | |
355afbcd | 1956 | /* JF these are out of order. We could put them |
1404ef23 KR |
1957 | in order if we were willing to put up with |
1958 | bunches of #ifdef m68851s in the code. | |
4134a793 | 1959 | |
1404ef23 KR |
1960 | Don't forget that you need these operands |
1961 | to use 68030 MMU instructions. */ | |
f8701a3f | 1962 | #ifndef NO_68851 |
355afbcd KR |
1963 | /* Memory addressing mode used by pflushr */ |
1964 | case '|': | |
1965 | if (opP->mode == MSCR || opP->mode == DREG || | |
1966 | opP->mode == AREG || opP->mode == REGLST) | |
1967 | losing++; | |
1968 | break; | |
1969 | ||
1970 | case 'f': | |
1971 | if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC)) | |
1972 | losing++; | |
1973 | break; | |
1974 | ||
1975 | case 'P': | |
1976 | if (opP->mode != MSCR | |
1977 | || (opP->reg != TC && opP->reg != CAL | |
1978 | && opP->reg != VAL && opP->reg != SCC && opP->reg != AC)) | |
1979 | losing++; | |
1980 | break; | |
1981 | ||
1982 | case 'V': | |
1983 | if (opP->reg != VAL) | |
1984 | losing++; | |
1985 | break; | |
8be74775 | 1986 | |
355afbcd KR |
1987 | case 'W': |
1988 | if (opP->mode != MSCR | |
1989 | || (opP->reg != DRP && opP->reg != SRP | |
1990 | && opP->reg != CRP)) | |
1991 | losing++; | |
1992 | break; | |
1993 | ||
1994 | case 'X': | |
1995 | if (opP->mode != MSCR || | |
1996 | (!(opP->reg >= BAD && opP->reg <= BAD + 7) && | |
1997 | !(opP->reg >= BAC && opP->reg <= BAC + 7))) | |
1998 | losing++; | |
1999 | break; | |
2000 | ||
2001 | case 'Y': | |
2002 | if (opP->reg != PSR) | |
2003 | losing++; | |
2004 | break; | |
2005 | ||
2006 | case 'Z': | |
2007 | if (opP->reg != PCSR) | |
2008 | losing++; | |
2009 | break; | |
f8701a3f | 2010 | #endif |
355afbcd KR |
2011 | case 'c': |
2012 | if (opP->reg != NC | |
2013 | && opP->reg != IC | |
2014 | && opP->reg != DC | |
2015 | && opP->reg != BC) | |
2016 | { | |
2017 | losing++; | |
2018 | } /* not a cache specifier. */ | |
2019 | break; | |
2020 | ||
2021 | case '_': | |
2022 | if (opP->mode != ABSL) | |
2023 | { | |
2024 | ++losing; | |
2025 | } /* not absolute */ | |
2026 | break; | |
8be74775 | 2027 | |
355afbcd KR |
2028 | default: |
2029 | as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"", | |
2030 | *s, __LINE__, __FILE__); | |
2031 | } /* switch on type of operand */ | |
6d27d3a2 | 2032 | |
355afbcd KR |
2033 | if (losing) |
2034 | break; | |
2035 | } /* for each operand */ | |
2036 | } /* if immediately wrong */ | |
6d27d3a2 | 2037 | |
355afbcd KR |
2038 | if (!losing) |
2039 | { | |
8be74775 | 2040 | break; |
355afbcd | 2041 | } /* got it. */ |
6d27d3a2 | 2042 | |
355afbcd | 2043 | opcode = opcode->m_next; |
6d27d3a2 | 2044 | |
355afbcd | 2045 | if (!opcode) |
8be74775 | 2046 | { |
355afbcd KR |
2047 | if (ok_arch |
2048 | && !(ok_arch & current_architecture)) | |
8be74775 | 2049 | { |
355afbcd KR |
2050 | char buf[200], *cp; |
2051 | int len; | |
2052 | strcpy (buf, "invalid instruction for this architecture; needs "); | |
2053 | cp = buf + strlen (buf); | |
2054 | switch (ok_arch) | |
2055 | { | |
2056 | case mfloat: | |
2057 | strcpy (cp, "fpu (68040 or 68881/68882)"); | |
2058 | break; | |
2059 | case mmmu: | |
2060 | strcpy (cp, "mmu (68030 or 68851)"); | |
2061 | break; | |
2062 | case m68020up: | |
2063 | strcpy (cp, "68020 or higher"); | |
2064 | break; | |
2065 | case m68000up: | |
2066 | strcpy (cp, "68000 or higher"); | |
2067 | break; | |
2068 | case m68010up: | |
2069 | strcpy (cp, "68010 or higher"); | |
2070 | break; | |
2071 | default: | |
8be74775 | 2072 | { |
355afbcd | 2073 | int got_one = 0, idx; |
bcb8dff8 | 2074 | static const struct |
355afbcd KR |
2075 | { |
2076 | int arch; | |
bcb8dff8 | 2077 | const char *name; |
355afbcd KR |
2078 | } |
2079 | archs[] = | |
2080 | { | |
bcb8dff8 KR |
2081 | { m68000, "68000" }, |
2082 | { m68010, "68010" }, | |
2083 | { m68020, "68020" }, | |
2084 | { m68030, "68030" }, | |
2085 | { m68040, "68040" }, | |
2086 | { cpu32, "cpu32" }, | |
2087 | { m68881, "68881" }, | |
2088 | { m68851, "68851" } | |
355afbcd KR |
2089 | }; |
2090 | for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++) | |
8be74775 | 2091 | { |
355afbcd | 2092 | if (archs[idx].arch & ok_arch) |
8be74775 | 2093 | { |
355afbcd KR |
2094 | if (got_one) |
2095 | { | |
2096 | strcpy (cp, " or "); | |
2097 | cp += strlen (cp); | |
2098 | } | |
2099 | got_one = 1; | |
2100 | strcpy (cp, archs[idx].name); | |
8be74775 KR |
2101 | cp += strlen (cp); |
2102 | } | |
8be74775 KR |
2103 | } |
2104 | } | |
355afbcd KR |
2105 | } |
2106 | len = cp - buf + 1; | |
2107 | cp = malloc (len); | |
2108 | strcpy (cp, buf); | |
2109 | the_ins.error = cp; | |
8be74775 | 2110 | } |
355afbcd KR |
2111 | else |
2112 | the_ins.error = "operands mismatch"; | |
2113 | return; | |
2114 | } /* Fell off the end */ | |
6d27d3a2 | 2115 | |
355afbcd KR |
2116 | losing = 0; |
2117 | } | |
6d27d3a2 KR |
2118 | |
2119 | /* now assemble it */ | |
2120 | ||
355afbcd KR |
2121 | the_ins.args = opcode->m_operands; |
2122 | the_ins.numargs = opcode->m_opnum; | |
2123 | the_ins.numo = opcode->m_codenum; | |
2124 | the_ins.opcode[0] = getone (opcode); | |
2125 | the_ins.opcode[1] = gettwo (opcode); | |
6d27d3a2 | 2126 | |
355afbcd KR |
2127 | for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) |
2128 | { | |
2129 | /* This switch is a doozy. | |
6d27d3a2 | 2130 | Watch the first step; its a big one! */ |
355afbcd KR |
2131 | switch (s[0]) |
2132 | { | |
6d27d3a2 | 2133 | |
355afbcd KR |
2134 | case '*': |
2135 | case '~': | |
2136 | case '%': | |
2137 | case ';': | |
2138 | case '@': | |
2139 | case '!': | |
2140 | case '&': | |
2141 | case '$': | |
2142 | case '?': | |
2143 | case '/': | |
2144 | case '`': | |
2145 | #ifndef NO_68851 | |
2146 | case '|': | |
2147 | #endif | |
2148 | switch (opP->mode) | |
2149 | { | |
2150 | case IMMED: | |
2151 | tmpreg = 0x3c; /* 7.4 */ | |
2152 | if (strchr ("bwl", s[1])) | |
2153 | nextword = get_num (opP->con1, 80); | |
2154 | else | |
49864cfa | 2155 | nextword = get_num (opP->con1, 0); |
355afbcd KR |
2156 | if (isvar (opP->con1)) |
2157 | add_fix (s[1], opP->con1, 0); | |
2158 | switch (s[1]) | |
2159 | { | |
2160 | case 'b': | |
2161 | if (!isbyte (nextword)) | |
2162 | opP->error = "operand out of range"; | |
2163 | addword (nextword); | |
2164 | baseo = 0; | |
2165 | break; | |
2166 | case 'w': | |
2167 | if (!isword (nextword)) | |
2168 | opP->error = "operand out of range"; | |
2169 | addword (nextword); | |
2170 | baseo = 0; | |
2171 | break; | |
2172 | case 'l': | |
2173 | addword (nextword >> 16); | |
2174 | addword (nextword); | |
2175 | baseo = 0; | |
2176 | break; | |
2177 | ||
2178 | case 'f': | |
2179 | baseo = 2; | |
2180 | outro = 8; | |
2181 | break; | |
2182 | case 'F': | |
2183 | baseo = 4; | |
2184 | outro = 11; | |
2185 | break; | |
2186 | case 'x': | |
2187 | baseo = 6; | |
2188 | outro = 15; | |
2189 | break; | |
2190 | case 'p': | |
2191 | baseo = 6; | |
2192 | outro = -1; | |
2193 | break; | |
2194 | default: | |
bcb8dff8 | 2195 | as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"", |
355afbcd KR |
2196 | *s, s[1], __LINE__, __FILE__); |
2197 | } | |
2198 | if (!baseo) | |
2199 | break; | |
6d27d3a2 | 2200 | |
355afbcd | 2201 | /* We gotta put out some float */ |
bcb8dff8 | 2202 | if (op (opP->con1) != O_big) |
355afbcd | 2203 | { |
bcb8dff8 KR |
2204 | valueT val; |
2205 | int gencnt; | |
2206 | ||
2207 | /* Can other cases happen here? */ | |
2208 | if (op (opP->con1) != O_constant) | |
2209 | abort (); | |
2210 | ||
2211 | val = (valueT) offs (opP->con1); | |
2212 | gencnt = 0; | |
2213 | do | |
2214 | { | |
2215 | generic_bignum[gencnt] = (LITTLENUM_TYPE) val; | |
2216 | val >>= LITTLENUM_NUMBER_OF_BITS; | |
2217 | ++gencnt; | |
2218 | } | |
2219 | while (val != 0); | |
2220 | offs (opP->con1) = gencnt; | |
355afbcd | 2221 | } |
355afbcd KR |
2222 | if (offs (opP->con1) > 0) |
2223 | { | |
2224 | if (offs (opP->con1) > baseo) | |
2225 | { | |
2226 | as_warn ("Bignum too big for %c format; truncated", s[1]); | |
2227 | offs (opP->con1) = baseo; | |
2228 | } | |
2229 | baseo -= offs (opP->con1); | |
355afbcd KR |
2230 | while (baseo--) |
2231 | addword (0); | |
bcb8dff8 KR |
2232 | for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp) |
2233 | addword (*wordp); | |
355afbcd KR |
2234 | break; |
2235 | } | |
2236 | gen_to_words (words, baseo, (long) outro); | |
2237 | for (wordp = words; baseo--; wordp++) | |
2238 | addword (*wordp); | |
2239 | break; | |
2240 | case DREG: | |
2241 | tmpreg = opP->reg - DATA; /* 0.dreg */ | |
2242 | break; | |
2243 | case AREG: | |
2244 | tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ | |
2245 | break; | |
2246 | case AINDR: | |
2247 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2248 | break; | |
2249 | case ADEC: | |
2250 | tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ | |
2251 | break; | |
2252 | case AINC: | |
2253 | tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ | |
2254 | break; | |
2255 | case AOFF: | |
6d27d3a2 | 2256 | |
355afbcd KR |
2257 | nextword = get_num (opP->con1, 80); |
2258 | /* Force into index mode. Hope this works */ | |
6d27d3a2 | 2259 | |
1404ef23 KR |
2260 | /* We do the first bit for 32-bit displacements, and the |
2261 | second bit for 16 bit ones. It is possible that we | |
2262 | should make the default be WORD instead of LONG, but | |
2263 | I think that'd break GCC, so we put up with a little | |
2264 | inefficiency for the sake of working output. */ | |
6d27d3a2 | 2265 | |
355afbcd KR |
2266 | if (!issword (nextword) |
2267 | || (isvar (opP->con1) | |
2268 | && ((opP->con1->e_siz == 0 | |
2269 | && flagseen['l'] == 0) | |
2270 | || opP->con1->e_siz == 3))) | |
2271 | { | |
6d27d3a2 | 2272 | |
355afbcd KR |
2273 | if (opP->reg == PC) |
2274 | tmpreg = 0x3B; /* 7.3 */ | |
2275 | else | |
2276 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2277 | if (isvar (opP->con1)) | |
2278 | { | |
2279 | if (opP->reg == PC) | |
2280 | { | |
b80d39a0 | 2281 | #if 0 |
355afbcd | 2282 | add_frag (adds (opP->con1), |
1404ef23 | 2283 | offs (opP->con1) + 2, |
355afbcd | 2284 | TAB (PCLEA, SZ_UNDEF)); |
b80d39a0 KR |
2285 | #else |
2286 | addword (0x0170); | |
2287 | add_fix ('l', opP->con1, 0); | |
2288 | addword (0), addword (0); | |
2289 | #endif | |
355afbcd KR |
2290 | break; |
2291 | } | |
2292 | else | |
2293 | { | |
2294 | addword (0x0170); | |
2295 | add_fix ('l', opP->con1, 0); | |
2296 | } | |
2297 | } | |
2298 | else | |
2299 | addword (0x0170); | |
2300 | addword (nextword >> 16); | |
2301 | } | |
2302 | else | |
2303 | { | |
2304 | if (opP->reg == PC) | |
2305 | tmpreg = 0x3A; /* 7.2 */ | |
2306 | else | |
2307 | tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ | |
2308 | ||
2309 | if (isvar (opP->con1)) | |
2310 | { | |
2311 | if (opP->reg == PC) | |
2312 | { | |
2313 | add_fix ('w', opP->con1, 1); | |
2314 | } | |
2315 | else | |
2316 | add_fix ('w', opP->con1, 0); | |
2317 | } | |
2318 | } | |
2319 | addword (nextword); | |
6d27d3a2 | 2320 | break; |
6d27d3a2 | 2321 | |
355afbcd KR |
2322 | case APODX: |
2323 | case AMIND: | |
2324 | case APRDX: | |
2325 | know (current_architecture & m68020up); | |
2326 | /* intentional fall-through */ | |
2327 | case AINDX: | |
2328 | nextword = 0; | |
2329 | baseo = get_num (opP->con1, 80); | |
2330 | outro = get_num (opP->con2, 80); | |
49864cfa KR |
2331 | /* Figure out the `addressing mode'. |
2332 | Also turn on the BASE_DISABLE bit, if needed. */ | |
355afbcd KR |
2333 | if (opP->reg == PC || opP->reg == ZPC) |
2334 | { | |
2335 | tmpreg = 0x3b;/* 7.3 */ | |
2336 | if (opP->reg == ZPC) | |
2337 | nextword |= 0x80; | |
2338 | } | |
2339 | else if (opP->reg == FAIL) | |
2340 | { | |
2341 | nextword |= 0x80; | |
2342 | tmpreg = 0x30;/* 6.garbage */ | |
2343 | } | |
2344 | else | |
2345 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2346 | ||
2347 | siz1 = (opP->con1) ? opP->con1->e_siz : 0; | |
2348 | siz2 = (opP->con2) ? opP->con2->e_siz : 0; | |
2349 | ||
2350 | /* Index register stuff */ | |
2351 | if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7) | |
2352 | { | |
2353 | nextword |= (opP->ireg - DATA) << 12; | |
2354 | ||
2355 | if (opP->isiz == 0 || opP->isiz == 3) | |
2356 | nextword |= 0x800; | |
2357 | switch (opP->imul) | |
2358 | { | |
2359 | case 1: | |
2360 | break; | |
2361 | case 2: | |
2362 | nextword |= 0x200; | |
2363 | break; | |
2364 | case 4: | |
2365 | nextword |= 0x400; | |
2366 | break; | |
2367 | case 8: | |
2368 | nextword |= 0x600; | |
2369 | break; | |
2370 | default: | |
2371 | as_fatal ("failed sanity check."); | |
2372 | } | |
2373 | /* IF its simple, | |
49864cfa | 2374 | GET US OUT OF HERE! */ |
6d27d3a2 | 2375 | |
355afbcd | 2376 | /* Must be INDEX, with an index |
49864cfa KR |
2377 | register. Address register |
2378 | cannot be ZERO-PC, and either | |
2379 | :b was forced, or we know | |
2380 | it will fit */ | |
355afbcd KR |
2381 | if (opP->mode == AINDX |
2382 | && opP->reg != FAIL | |
2383 | && opP->reg != ZPC | |
2384 | && (siz1 == 1 | |
2385 | || (issbyte (baseo) | |
2386 | && !isvar (opP->con1)))) | |
2387 | { | |
2388 | nextword += baseo & 0xff; | |
2389 | addword (nextword); | |
2390 | if (isvar (opP->con1)) | |
2391 | add_fix ('B', opP->con1, 0); | |
2392 | break; | |
2393 | } | |
2394 | } | |
2395 | else | |
2396 | nextword |= 0x40; /* No index reg */ | |
6d27d3a2 | 2397 | |
49864cfa | 2398 | /* It isn't simple. */ |
355afbcd | 2399 | nextword |= 0x100; |
49864cfa KR |
2400 | /* If the guy specified a width, we assume that it is |
2401 | wide enough. Maybe it isn't. If so, we lose. */ | |
355afbcd KR |
2402 | switch (siz1) |
2403 | { | |
2404 | case 0: | |
2405 | if (isvar (opP->con1) || !issword (baseo)) | |
2406 | { | |
2407 | siz1 = 3; | |
2408 | nextword |= 0x30; | |
2409 | } | |
2410 | else if (baseo == 0) | |
2411 | nextword |= 0x10; | |
2412 | else | |
2413 | { | |
2414 | nextword |= 0x20; | |
2415 | siz1 = 2; | |
2416 | } | |
2417 | break; | |
2418 | case 1: | |
2419 | as_warn ("Byte dispacement won't work. Defaulting to :w"); | |
2420 | case 2: | |
2421 | nextword |= 0x20; | |
2422 | break; | |
2423 | case 3: | |
2424 | nextword |= 0x30; | |
2425 | break; | |
2426 | } | |
6d27d3a2 | 2427 | |
355afbcd KR |
2428 | /* Figure out innner displacement stuff */ |
2429 | if (opP->mode != AINDX) | |
2430 | { | |
2431 | switch (siz2) | |
2432 | { | |
2433 | case 0: | |
2434 | if (isvar (opP->con2) || !issword (outro)) | |
2435 | { | |
2436 | siz2 = 3; | |
2437 | nextword |= 0x3; | |
2438 | } | |
2439 | else if (outro == 0) | |
2440 | nextword |= 0x1; | |
2441 | else | |
2442 | { | |
2443 | nextword |= 0x2; | |
2444 | siz2 = 2; | |
2445 | } | |
2446 | break; | |
2447 | case 1: | |
2448 | as_warn ("Byte dispacement won't work. Defaulting to :w"); | |
2449 | case 2: | |
2450 | nextword |= 0x2; | |
2451 | break; | |
2452 | case 3: | |
2453 | nextword |= 0x3; | |
2454 | break; | |
2455 | } | |
2456 | if (opP->mode == APODX) | |
2457 | nextword |= 0x04; | |
2458 | else if (opP->mode == AMIND) | |
2459 | nextword |= 0x40; | |
2460 | } | |
2461 | addword (nextword); | |
2462 | ||
2463 | if (isvar (opP->con1)) | |
2464 | { | |
2465 | if (opP->reg == PC || opP->reg == ZPC) | |
2466 | { | |
355afbcd | 2467 | opP->con1->e_exp.X_add_number += 6; |
9d4dfbf3 | 2468 | add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1); |
355afbcd KR |
2469 | } |
2470 | else | |
2471 | add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0); | |
2472 | } | |
2473 | if (siz1 == 3) | |
2474 | addword (baseo >> 16); | |
2475 | if (siz1) | |
2476 | addword (baseo); | |
2477 | ||
2478 | if (isvar (opP->con2)) | |
2479 | { | |
2480 | if (opP->reg == PC || opP->reg == ZPC) | |
2481 | { | |
355afbcd | 2482 | opP->con1->e_exp.X_add_number += 6; |
9d4dfbf3 | 2483 | add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 1); |
355afbcd KR |
2484 | } |
2485 | else | |
2486 | add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0); | |
2487 | } | |
2488 | if (siz2 == 3) | |
2489 | addword (outro >> 16); | |
2490 | if (siz2) | |
2491 | addword (outro); | |
6d27d3a2 | 2492 | |
355afbcd | 2493 | break; |
6d27d3a2 | 2494 | |
355afbcd KR |
2495 | case ABSL: |
2496 | nextword = get_num (opP->con1, 80); | |
2497 | switch (opP->con1->e_siz) | |
2498 | { | |
2499 | default: | |
2500 | as_warn ("Unknown size for absolute reference"); | |
2501 | case 0: | |
2502 | if (!isvar (opP->con1) && issword (offs (opP->con1))) | |
2503 | { | |
2504 | tmpreg = 0x38; /* 7.0 */ | |
2505 | addword (nextword); | |
2506 | break; | |
2507 | } | |
bcb8dff8 KR |
2508 | /* Don't generate pc relative code on 68010 and |
2509 | 68000. */ | |
355afbcd KR |
2510 | if (isvar (opP->con1) |
2511 | && !subs (opP->con1) | |
49864cfa KR |
2512 | && seg (opP->con1) == text_section |
2513 | && now_seg == text_section | |
355afbcd KR |
2514 | && cpu_of_arch (current_architecture) >= m68020 |
2515 | && !flagseen['S'] | |
2516 | && !strchr ("~%&$?", s[0])) | |
2517 | { | |
2518 | tmpreg = 0x3A; /* 7.2 */ | |
2519 | add_frag (adds (opP->con1), | |
2520 | offs (opP->con1), | |
2521 | TAB (PCREL, SZ_UNDEF)); | |
2522 | break; | |
2523 | } | |
2524 | case 3: /* Fall through into long */ | |
2525 | if (isvar (opP->con1)) | |
2526 | add_fix ('l', opP->con1, 0); | |
2527 | ||
2528 | tmpreg = 0x39;/* 7.1 mode */ | |
2529 | addword (nextword >> 16); | |
2530 | addword (nextword); | |
2531 | break; | |
2532 | ||
2533 | case 2: /* Word */ | |
2534 | if (isvar (opP->con1)) | |
2535 | add_fix ('w', opP->con1, 0); | |
2536 | ||
2537 | tmpreg = 0x38;/* 7.0 mode */ | |
2538 | addword (nextword); | |
2539 | break; | |
2540 | } | |
2541 | break; | |
2542 | case DINDR: | |
2543 | as_bad ("invalid indirect register"); | |
2544 | break; | |
2545 | case MSCR: | |
2546 | default: | |
2547 | as_bad ("unknown/incorrect operand"); | |
2548 | /* abort(); */ | |
2549 | } | |
2550 | install_gen_operand (s[1], tmpreg); | |
6d27d3a2 | 2551 | break; |
6d27d3a2 | 2552 | |
355afbcd KR |
2553 | case '#': |
2554 | case '^': | |
2555 | switch (s[1]) | |
2556 | { /* JF: I hate floating point! */ | |
2557 | case 'j': | |
2558 | tmpreg = 70; | |
2559 | break; | |
2560 | case '8': | |
2561 | tmpreg = 20; | |
2562 | break; | |
2563 | case 'C': | |
2564 | tmpreg = 50; | |
2565 | break; | |
2566 | case '3': | |
2567 | default: | |
2568 | tmpreg = 80; | |
2569 | break; | |
2570 | } | |
2571 | tmpreg = get_num (opP->con1, tmpreg); | |
2572 | if (isvar (opP->con1)) | |
2573 | add_fix (s[1], opP->con1, 0); | |
2574 | switch (s[1]) | |
2575 | { | |
2576 | case 'b': /* Danger: These do no check for | |
6d27d3a2 KR |
2577 | certain types of overflow. |
2578 | user beware! */ | |
355afbcd KR |
2579 | if (!isbyte (tmpreg)) |
2580 | opP->error = "out of range"; | |
bcb8dff8 | 2581 | insop (tmpreg, opcode); |
355afbcd KR |
2582 | if (isvar (opP->con1)) |
2583 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2584 | break; | |
2585 | case 'w': | |
2586 | if (!isword (tmpreg)) | |
2587 | opP->error = "out of range"; | |
bcb8dff8 | 2588 | insop (tmpreg, opcode); |
355afbcd KR |
2589 | if (isvar (opP->con1)) |
2590 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2591 | break; | |
2592 | case 'l': | |
bcb8dff8 KR |
2593 | /* Because of the way insop works, we put these two out |
2594 | backwards. */ | |
2595 | insop (tmpreg, opcode); | |
2596 | insop (tmpreg >> 16, opcode); | |
355afbcd KR |
2597 | if (isvar (opP->con1)) |
2598 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2599 | break; | |
2600 | case '3': | |
2601 | tmpreg &= 0xFF; | |
2602 | case '8': | |
2603 | case 'C': | |
2604 | install_operand (s[1], tmpreg); | |
2605 | break; | |
2606 | default: | |
bcb8dff8 | 2607 | as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s[1], __LINE__, __FILE__); |
355afbcd KR |
2608 | } |
2609 | break; | |
6d27d3a2 | 2610 | |
355afbcd KR |
2611 | case '+': |
2612 | case '-': | |
2613 | case 'A': | |
2614 | case 'a': | |
2615 | install_operand (s[1], opP->reg - ADDR); | |
2616 | break; | |
6d27d3a2 | 2617 | |
355afbcd KR |
2618 | case 'B': |
2619 | tmpreg = get_num (opP->con1, 80); | |
2620 | switch (s[1]) | |
2621 | { | |
2622 | case 'B': | |
2623 | /* Needs no offsetting */ | |
2624 | add_fix ('B', opP->con1, 1); | |
2625 | break; | |
2626 | case 'W': | |
2627 | /* Offset the displacement to be relative to byte disp location */ | |
2628 | opP->con1->e_exp.X_add_number += 2; | |
2629 | add_fix ('w', opP->con1, 1); | |
2630 | addword (0); | |
2631 | break; | |
2632 | case 'L': | |
2633 | long_branch: | |
2634 | if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */ | |
2635 | as_warn ("Can't use long branches on 68000/68010"); | |
2636 | the_ins.opcode[the_ins.numo - 1] |= 0xff; | |
2637 | /* Offset the displacement to be relative to byte disp location */ | |
2638 | opP->con1->e_exp.X_add_number += 4; | |
2639 | add_fix ('l', opP->con1, 1); | |
2640 | addword (0); | |
2641 | addword (0); | |
2642 | break; | |
2643 | case 'g': | |
2644 | if (subs (opP->con1)) /* We can't relax it */ | |
2645 | goto long_branch; | |
6d27d3a2 | 2646 | |
355afbcd | 2647 | /* This could either be a symbol, or an |
1404ef23 KR |
2648 | absolute address. No matter, the |
2649 | frag hacking will finger it out. | |
2650 | Not quite: it can't switch from | |
2651 | BRANCH to BCC68000 for the case | |
2652 | where opnd is absolute (it needs | |
2653 | to use the 68000 hack since no | |
2654 | conditional abs jumps). */ | |
355afbcd KR |
2655 | if (((cpu_of_arch (current_architecture) < m68020) || (0 == adds (opP->con1))) |
2656 | && (the_ins.opcode[0] >= 0x6200) | |
2657 | && (the_ins.opcode[0] <= 0x6f00)) | |
2658 | { | |
2659 | add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF)); | |
2660 | } | |
2661 | else | |
2662 | { | |
2663 | add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF)); | |
2664 | } | |
2665 | break; | |
2666 | case 'w': | |
2667 | if (isvar (opP->con1)) | |
2668 | { | |
49864cfa | 2669 | #if 1 |
355afbcd KR |
2670 | /* check for DBcc instruction */ |
2671 | if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8) | |
2672 | { | |
2673 | /* size varies if patch */ | |
2674 | /* needed for long form */ | |
2675 | add_frag (adds (opP->con1), offs (opP->con1), TAB (DBCC, SZ_UNDEF)); | |
2676 | break; | |
2677 | } | |
49864cfa | 2678 | #endif |
355afbcd KR |
2679 | /* Don't ask! */ |
2680 | opP->con1->e_exp.X_add_number += 2; | |
2681 | add_fix ('w', opP->con1, 1); | |
2682 | } | |
2683 | addword (0); | |
2684 | break; | |
2685 | case 'C': /* Fixed size LONG coproc branches */ | |
2686 | the_ins.opcode[the_ins.numo - 1] |= 0x40; | |
2687 | /* Offset the displacement to be relative to byte disp location */ | |
2688 | /* Coproc branches don't have a byte disp option, but they are | |
6d27d3a2 | 2689 | compatible with the ordinary branches, which do... */ |
355afbcd KR |
2690 | opP->con1->e_exp.X_add_number += 4; |
2691 | add_fix ('l', opP->con1, 1); | |
2692 | addword (0); | |
2693 | addword (0); | |
2694 | break; | |
2695 | case 'c': /* Var size Coprocesssor branches */ | |
2696 | if (subs (opP->con1)) | |
2697 | { | |
2698 | add_fix ('l', opP->con1, 1); | |
2699 | add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG)); | |
2700 | } | |
2701 | else if (adds (opP->con1)) | |
2702 | { | |
2703 | add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF)); | |
2704 | } | |
2705 | else | |
2706 | { | |
2707 | /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */ | |
2708 | the_ins.opcode[the_ins.numo - 1] |= 0x40; | |
2709 | add_fix ('l', opP->con1, 1); | |
2710 | addword (0); | |
2711 | addword (4); | |
2712 | } | |
2713 | break; | |
2714 | default: | |
bcb8dff8 | 2715 | as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"", |
355afbcd KR |
2716 | s[1], __LINE__, __FILE__); |
2717 | } | |
2718 | break; | |
6d27d3a2 | 2719 | |
355afbcd KR |
2720 | case 'C': /* Ignore it */ |
2721 | break; | |
6d27d3a2 | 2722 | |
355afbcd KR |
2723 | case 'd': /* JF this is a kludge */ |
2724 | if (opP->mode == AOFF) | |
2725 | { | |
2726 | install_operand ('s', opP->reg - ADDR); | |
2727 | } | |
2728 | else | |
2729 | { | |
2730 | char *tmpP; | |
2731 | ||
2732 | tmpP = opP->con1->e_end - 2; | |
2733 | opP->con1->e_beg++; | |
2734 | opP->con1->e_end -= 4; /* point to the , */ | |
2735 | baseo = m68k_reg_parse (&tmpP); | |
2736 | if (baseo < ADDR + 0 || baseo > ADDR + 7) | |
2737 | { | |
2738 | as_bad ("Unknown address reg, using A0"); | |
2739 | baseo = 0; | |
2740 | } | |
2741 | else | |
2742 | baseo -= ADDR; | |
2743 | install_operand ('s', baseo); | |
2744 | } | |
2745 | tmpreg = get_num (opP->con1, 80); | |
2746 | if (!issword (tmpreg)) | |
2747 | { | |
2748 | as_warn ("Expression out of range, using 0"); | |
2749 | tmpreg = 0; | |
2750 | } | |
2751 | addword (tmpreg); | |
2752 | break; | |
6d27d3a2 | 2753 | |
355afbcd KR |
2754 | case 'D': |
2755 | install_operand (s[1], opP->reg - DATA); | |
2756 | break; | |
6d27d3a2 | 2757 | |
355afbcd KR |
2758 | case 'F': |
2759 | install_operand (s[1], opP->reg - FPREG); | |
2760 | break; | |
6d27d3a2 | 2761 | |
355afbcd KR |
2762 | case 'I': |
2763 | tmpreg = 1 + opP->reg - COPNUM; | |
2764 | if (tmpreg == 8) | |
2765 | tmpreg = 0; | |
2766 | install_operand (s[1], tmpreg); | |
2767 | break; | |
6d27d3a2 | 2768 | |
355afbcd KR |
2769 | case 'J': /* JF foo */ |
2770 | switch (opP->reg) | |
2771 | { | |
2772 | case SFC: | |
2773 | tmpreg = 0x000; | |
2774 | break; | |
2775 | case DFC: | |
2776 | tmpreg = 0x001; | |
2777 | break; | |
2778 | case CACR: | |
2779 | tmpreg = 0x002; | |
2780 | break; | |
2781 | case TC: | |
2782 | tmpreg = 0x003; | |
2783 | break; | |
2784 | case ITT0: | |
2785 | tmpreg = 0x004; | |
2786 | break; | |
2787 | case ITT1: | |
2788 | tmpreg = 0x005; | |
2789 | break; | |
2790 | case DTT0: | |
2791 | tmpreg = 0x006; | |
2792 | break; | |
2793 | case DTT1: | |
2794 | tmpreg = 0x007; | |
2795 | break; | |
6d27d3a2 | 2796 | |
355afbcd KR |
2797 | case USP: |
2798 | tmpreg = 0x800; | |
2799 | break; | |
2800 | case VBR: | |
2801 | tmpreg = 0x801; | |
2802 | break; | |
2803 | case CAAR: | |
2804 | tmpreg = 0x802; | |
2805 | break; | |
2806 | case MSP: | |
2807 | tmpreg = 0x803; | |
2808 | break; | |
2809 | case ISP: | |
2810 | tmpreg = 0x804; | |
2811 | break; | |
2812 | case MMUSR: | |
2813 | tmpreg = 0x805; | |
2814 | break; | |
2815 | case URP: | |
2816 | tmpreg = 0x806; | |
2817 | break; | |
2818 | case SRP: | |
2819 | tmpreg = 0x807; | |
2820 | break; | |
2821 | default: | |
2822 | as_fatal ("failed sanity check."); | |
2823 | } | |
2824 | install_operand (s[1], tmpreg); | |
2825 | break; | |
6d27d3a2 | 2826 | |
355afbcd KR |
2827 | case 'k': |
2828 | tmpreg = get_num (opP->con1, 55); | |
2829 | install_operand (s[1], tmpreg & 0x7f); | |
2830 | break; | |
6d27d3a2 | 2831 | |
355afbcd KR |
2832 | case 'l': |
2833 | tmpreg = opP->reg; | |
2834 | if (s[1] == 'w') | |
2835 | { | |
2836 | if (tmpreg & 0x7FF0000) | |
2837 | as_bad ("Floating point register in register list"); | |
bcb8dff8 | 2838 | insop (reverse_16_bits (tmpreg), opcode); |
355afbcd KR |
2839 | } |
2840 | else | |
2841 | { | |
2842 | if (tmpreg & 0x700FFFF) | |
2843 | as_bad ("Wrong register in floating-point reglist"); | |
2844 | install_operand (s[1], reverse_8_bits (tmpreg >> 16)); | |
2845 | } | |
2846 | break; | |
6d27d3a2 | 2847 | |
355afbcd KR |
2848 | case 'L': |
2849 | tmpreg = opP->reg; | |
2850 | if (s[1] == 'w') | |
2851 | { | |
2852 | if (tmpreg & 0x7FF0000) | |
2853 | as_bad ("Floating point register in register list"); | |
bcb8dff8 | 2854 | insop (tmpreg, opcode); |
355afbcd KR |
2855 | } |
2856 | else if (s[1] == '8') | |
2857 | { | |
2858 | if (tmpreg & 0x0FFFFFF) | |
2859 | as_bad ("incorrect register in reglist"); | |
2860 | install_operand (s[1], tmpreg >> 24); | |
2861 | } | |
2862 | else | |
2863 | { | |
2864 | if (tmpreg & 0x700FFFF) | |
2865 | as_bad ("wrong register in floating-point reglist"); | |
2866 | else | |
2867 | install_operand (s[1], tmpreg >> 16); | |
2868 | } | |
2869 | break; | |
6d27d3a2 | 2870 | |
355afbcd KR |
2871 | case 'M': |
2872 | install_operand (s[1], get_num (opP->con1, 60)); | |
2873 | break; | |
6d27d3a2 | 2874 | |
355afbcd KR |
2875 | case 'O': |
2876 | tmpreg = (opP->mode == DREG) | |
2877 | ? 0x20 + opP->reg - DATA | |
2878 | : (get_num (opP->con1, 40) & 0x1F); | |
2879 | install_operand (s[1], tmpreg); | |
2880 | break; | |
6d27d3a2 | 2881 | |
355afbcd KR |
2882 | case 'Q': |
2883 | tmpreg = get_num (opP->con1, 10); | |
2884 | if (tmpreg == 8) | |
2885 | tmpreg = 0; | |
2886 | install_operand (s[1], tmpreg); | |
2887 | break; | |
2888 | ||
2889 | case 'R': | |
2890 | case 'r': | |
2891 | /* This depends on the fact that ADDR registers are | |
6d27d3a2 KR |
2892 | eight more than their corresponding DATA regs, so |
2893 | the result will have the ADDR_REG bit set */ | |
355afbcd KR |
2894 | install_operand (s[1], opP->reg - DATA); |
2895 | break; | |
6d27d3a2 | 2896 | |
355afbcd KR |
2897 | case 's': |
2898 | if (opP->reg == FPI) | |
2899 | tmpreg = 0x1; | |
2900 | else if (opP->reg == FPS) | |
2901 | tmpreg = 0x2; | |
2902 | else if (opP->reg == FPC) | |
2903 | tmpreg = 0x4; | |
2904 | else | |
2905 | as_fatal ("failed sanity check."); | |
2906 | install_operand (s[1], tmpreg); | |
2907 | break; | |
6d27d3a2 | 2908 | |
355afbcd KR |
2909 | case 'S': /* Ignore it */ |
2910 | break; | |
6d27d3a2 | 2911 | |
355afbcd KR |
2912 | case 'T': |
2913 | install_operand (s[1], get_num (opP->con1, 30)); | |
2914 | break; | |
6d27d3a2 | 2915 | |
355afbcd KR |
2916 | case 'U': /* Ignore it */ |
2917 | break; | |
6d27d3a2 | 2918 | |
355afbcd KR |
2919 | case 'c': |
2920 | switch (opP->reg) | |
2921 | { | |
2922 | case NC: | |
2923 | tmpreg = 0; | |
2924 | break; | |
2925 | case DC: | |
2926 | tmpreg = 1; | |
2927 | break; | |
2928 | case IC: | |
2929 | tmpreg = 2; | |
2930 | break; | |
2931 | case BC: | |
2932 | tmpreg = 3; | |
2933 | break; | |
2934 | default: | |
2935 | as_fatal ("failed sanity check"); | |
2936 | } /* switch on cache token */ | |
2937 | install_operand (s[1], tmpreg); | |
2938 | break; | |
a39116f1 | 2939 | #ifndef NO_68851 |
355afbcd KR |
2940 | /* JF: These are out of order, I fear. */ |
2941 | case 'f': | |
2942 | switch (opP->reg) | |
2943 | { | |
2944 | case SFC: | |
2945 | tmpreg = 0; | |
2946 | break; | |
2947 | case DFC: | |
2948 | tmpreg = 1; | |
2949 | break; | |
2950 | default: | |
2951 | as_fatal ("failed sanity check."); | |
2952 | } | |
2953 | install_operand (s[1], tmpreg); | |
2954 | break; | |
6d27d3a2 | 2955 | |
355afbcd KR |
2956 | case 'P': |
2957 | switch (opP->reg) | |
2958 | { | |
2959 | case TC: | |
2960 | tmpreg = 0; | |
2961 | break; | |
2962 | case CAL: | |
2963 | tmpreg = 4; | |
2964 | break; | |
2965 | case VAL: | |
2966 | tmpreg = 5; | |
2967 | break; | |
2968 | case SCC: | |
2969 | tmpreg = 6; | |
2970 | break; | |
2971 | case AC: | |
2972 | tmpreg = 7; | |
2973 | break; | |
2974 | default: | |
2975 | as_fatal ("failed sanity check."); | |
2976 | } | |
2977 | install_operand (s[1], tmpreg); | |
2978 | break; | |
6d27d3a2 | 2979 | |
355afbcd KR |
2980 | case 'V': |
2981 | if (opP->reg == VAL) | |
2982 | break; | |
2983 | as_fatal ("failed sanity check."); | |
6d27d3a2 | 2984 | |
355afbcd KR |
2985 | case 'W': |
2986 | switch (opP->reg) | |
2987 | { | |
6d27d3a2 | 2988 | |
355afbcd KR |
2989 | case DRP: |
2990 | tmpreg = 1; | |
2991 | break; | |
2992 | case SRP: | |
2993 | tmpreg = 2; | |
2994 | break; | |
2995 | case CRP: | |
2996 | tmpreg = 3; | |
2997 | break; | |
2998 | default: | |
2999 | as_fatal ("failed sanity check."); | |
3000 | } | |
3001 | install_operand (s[1], tmpreg); | |
3002 | break; | |
6d27d3a2 | 3003 | |
355afbcd KR |
3004 | case 'X': |
3005 | switch (opP->reg) | |
3006 | { | |
3007 | case BAD: | |
3008 | case BAD + 1: | |
3009 | case BAD + 2: | |
3010 | case BAD + 3: | |
3011 | case BAD + 4: | |
3012 | case BAD + 5: | |
3013 | case BAD + 6: | |
3014 | case BAD + 7: | |
3015 | tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); | |
3016 | break; | |
6d27d3a2 | 3017 | |
355afbcd KR |
3018 | case BAC: |
3019 | case BAC + 1: | |
3020 | case BAC + 2: | |
3021 | case BAC + 3: | |
3022 | case BAC + 4: | |
3023 | case BAC + 5: | |
3024 | case BAC + 6: | |
3025 | case BAC + 7: | |
3026 | tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); | |
3027 | break; | |
6d27d3a2 | 3028 | |
355afbcd KR |
3029 | default: |
3030 | as_fatal ("failed sanity check."); | |
3031 | } | |
3032 | install_operand (s[1], tmpreg); | |
3033 | break; | |
3034 | case 'Y': | |
3035 | know (opP->reg == PSR); | |
3036 | break; | |
3037 | case 'Z': | |
3038 | know (opP->reg == PCSR); | |
3039 | break; | |
f8701a3f | 3040 | #endif /* m68851 */ |
355afbcd KR |
3041 | case '3': |
3042 | switch (opP->reg) | |
3043 | { | |
3044 | case TT0: | |
3045 | tmpreg = 2; | |
3046 | break; | |
3047 | case TT1: | |
3048 | tmpreg = 3; | |
3049 | break; | |
3050 | default: | |
3051 | as_fatal ("failed sanity check"); | |
3052 | } | |
3053 | install_operand (s[1], tmpreg); | |
3054 | break; | |
3055 | case 't': | |
3056 | tmpreg = get_num (opP->con1, 20); | |
3057 | install_operand (s[1], tmpreg); | |
4134a793 | 3058 | break; |
355afbcd KR |
3059 | case '_': /* used only for move16 absolute 32-bit address */ |
3060 | tmpreg = get_num (opP->con1, 80); | |
3061 | addword (tmpreg >> 16); | |
3062 | addword (tmpreg & 0xFFFF); | |
4134a793 KR |
3063 | break; |
3064 | default: | |
355afbcd KR |
3065 | as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"", |
3066 | s[0], __LINE__, __FILE__); | |
4134a793 | 3067 | } |
6d27d3a2 | 3068 | } |
3ad9ec6a | 3069 | |
6d27d3a2 KR |
3070 | /* By the time whe get here (FINALLY) the_ins contains the complete |
3071 | instruction, ready to be emitted. . . */ | |
355afbcd | 3072 | } /* m68k_ip() */ |
7c15cbe8 RP |
3073 | |
3074 | /* | |
3075 | * get_regs := '/' + ? | |
3076 | * | '-' + <register> | |
3077 | * | '-' + <register> + ? | |
3078 | * | <empty> | |
3079 | * ; | |
3080 | * | |
6d27d3a2 | 3081 | |
7c15cbe8 RP |
3082 | * The idea here must be to scan in a set of registers but I don't |
3083 | * understand it. Looks awfully sloppy to me but I don't have any doc on | |
3084 | * this format so... | |
6d27d3a2 KR |
3085 | |
3086 | * | |
7c15cbe8 RP |
3087 | * |
3088 | */ | |
fecd2382 | 3089 | |
355afbcd KR |
3090 | static int |
3091 | get_regs (i, str, opP) | |
3092 | int i; | |
3093 | struct m68k_op *opP; | |
3094 | char *str; | |
fecd2382 | 3095 | { |
355afbcd KR |
3096 | /* 26, 25, 24, 23-16, 15-8, 0-7 */ |
3097 | /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */ | |
3098 | unsigned long cur_regs = 0; | |
3099 | int reg1, reg2; | |
6d27d3a2 | 3100 | |
fecd2382 | 3101 | #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\ |
a39116f1 RP |
3102 | else if(x==FPS) cur_regs|=(1<<25);\ |
3103 | else if(x==FPC) cur_regs|=(1<<26);\ | |
3104 | else cur_regs|=(1<<(x-1)); } | |
6d27d3a2 | 3105 | |
355afbcd KR |
3106 | reg1 = i; |
3107 | for (;;) | |
3108 | { | |
3109 | if (*str == '/') | |
3110 | { | |
3111 | ADD_REG (reg1); | |
3112 | str++; | |
3113 | } | |
3114 | else if (*str == '-') | |
3115 | { | |
3116 | str++; | |
3117 | reg2 = m68k_reg_parse (&str); | |
3118 | if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC) | |
3119 | { | |
3120 | opP->error = "unknown register in register list"; | |
3121 | return FAIL; | |
3122 | } | |
3123 | while (reg1 <= reg2) | |
3124 | { | |
3125 | ADD_REG (reg1); | |
3126 | reg1++; | |
3127 | } | |
3128 | if (*str == '\0') | |
3129 | break; | |
3130 | } | |
3131 | else if (*str == '\0') | |
3132 | { | |
3133 | ADD_REG (reg1); | |
3134 | break; | |
3135 | } | |
3136 | else | |
3137 | { | |
3138 | opP->error = "unknow character in register list"; | |
3139 | return FAIL; | |
3140 | } | |
3141 | /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */ | |
3142 | if (*str == '/') | |
3143 | str++; | |
3144 | reg1 = m68k_reg_parse (&str); | |
3145 | if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC)) | |
3146 | { | |
3147 | opP->error = "unknown register in register list"; | |
3148 | return FAIL; | |
a39116f1 | 3149 | } |
355afbcd KR |
3150 | } |
3151 | opP->reg = cur_regs; | |
3152 | return OK; | |
3153 | } /* get_regs() */ | |
fecd2382 | 3154 | |
355afbcd KR |
3155 | static int |
3156 | reverse_16_bits (in) | |
3157 | int in; | |
fecd2382 | 3158 | { |
355afbcd KR |
3159 | int out = 0; |
3160 | int n; | |
6d27d3a2 | 3161 | |
355afbcd KR |
3162 | static int mask[16] = |
3163 | { | |
3164 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3165 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 | |
3166 | }; | |
3167 | for (n = 0; n < 16; n++) | |
3168 | { | |
3169 | if (in & mask[n]) | |
3170 | out |= mask[15 - n]; | |
3171 | } | |
3172 | return out; | |
3173 | } /* reverse_16_bits() */ | |
fecd2382 | 3174 | |
355afbcd KR |
3175 | static int |
3176 | reverse_8_bits (in) | |
3177 | int in; | |
fecd2382 | 3178 | { |
355afbcd KR |
3179 | int out = 0; |
3180 | int n; | |
6d27d3a2 | 3181 | |
355afbcd KR |
3182 | static int mask[8] = |
3183 | { | |
3184 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3185 | }; | |
6d27d3a2 | 3186 | |
355afbcd KR |
3187 | for (n = 0; n < 8; n++) |
3188 | { | |
3189 | if (in & mask[n]) | |
3190 | out |= mask[7 - n]; | |
3191 | } | |
3192 | return out; | |
3193 | } /* reverse_8_bits() */ | |
fecd2382 | 3194 | |
355afbcd KR |
3195 | static void |
3196 | install_operand (mode, val) | |
3197 | int mode; | |
3198 | int val; | |
fecd2382 | 3199 | { |
355afbcd KR |
3200 | switch (mode) |
3201 | { | |
3202 | case 's': | |
3203 | the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */ | |
3204 | break; | |
3205 | case 'd': | |
3206 | the_ins.opcode[0] |= val << 9; | |
3207 | break; | |
3208 | case '1': | |
3209 | the_ins.opcode[1] |= val << 12; | |
3210 | break; | |
3211 | case '2': | |
3212 | the_ins.opcode[1] |= val << 6; | |
3213 | break; | |
3214 | case '3': | |
3215 | the_ins.opcode[1] |= val; | |
3216 | break; | |
3217 | case '4': | |
3218 | the_ins.opcode[2] |= val << 12; | |
3219 | break; | |
3220 | case '5': | |
3221 | the_ins.opcode[2] |= val << 6; | |
3222 | break; | |
3223 | case '6': | |
bcb8dff8 KR |
3224 | /* DANGER! This is a hack to force cas2l and cas2w cmds to be |
3225 | three words long! */ | |
355afbcd KR |
3226 | the_ins.numo++; |
3227 | the_ins.opcode[2] |= val; | |
3228 | break; | |
3229 | case '7': | |
3230 | the_ins.opcode[1] |= val << 7; | |
3231 | break; | |
3232 | case '8': | |
3233 | the_ins.opcode[1] |= val << 10; | |
3234 | break; | |
f8701a3f | 3235 | #ifndef NO_68851 |
355afbcd KR |
3236 | case '9': |
3237 | the_ins.opcode[1] |= val << 5; | |
3238 | break; | |
f8701a3f | 3239 | #endif |
6d27d3a2 | 3240 | |
355afbcd KR |
3241 | case 't': |
3242 | the_ins.opcode[1] |= (val << 10) | (val << 7); | |
3243 | break; | |
3244 | case 'D': | |
3245 | the_ins.opcode[1] |= (val << 12) | val; | |
3246 | break; | |
3247 | case 'g': | |
3248 | the_ins.opcode[0] |= val = 0xff; | |
3249 | break; | |
3250 | case 'i': | |
3251 | the_ins.opcode[0] |= val << 9; | |
3252 | break; | |
3253 | case 'C': | |
3254 | the_ins.opcode[1] |= val; | |
3255 | break; | |
3256 | case 'j': | |
3257 | the_ins.opcode[1] |= val; | |
3258 | the_ins.numo++; /* What a hack */ | |
3259 | break; | |
3260 | case 'k': | |
3261 | the_ins.opcode[1] |= val << 4; | |
3262 | break; | |
3263 | case 'b': | |
3264 | case 'w': | |
3265 | case 'l': | |
3266 | break; | |
3267 | case 'e': | |
3268 | the_ins.opcode[0] |= (val << 6); | |
3269 | break; | |
3270 | case 'L': | |
3271 | the_ins.opcode[1] = (val >> 16); | |
3272 | the_ins.opcode[2] = val & 0xffff; | |
3273 | break; | |
3274 | case 'c': | |
3275 | default: | |
3276 | as_fatal ("failed sanity check."); | |
3277 | } | |
3278 | } /* install_operand() */ | |
fecd2382 | 3279 | |
355afbcd KR |
3280 | static void |
3281 | install_gen_operand (mode, val) | |
3282 | int mode; | |
3283 | int val; | |
fecd2382 | 3284 | { |
355afbcd KR |
3285 | switch (mode) |
3286 | { | |
3287 | case 's': | |
3288 | the_ins.opcode[0] |= val; | |
3289 | break; | |
3290 | case 'd': | |
3291 | /* This is a kludge!!! */ | |
3292 | the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; | |
3293 | break; | |
3294 | case 'b': | |
3295 | case 'w': | |
3296 | case 'l': | |
3297 | case 'f': | |
3298 | case 'F': | |
3299 | case 'x': | |
3300 | case 'p': | |
3301 | the_ins.opcode[0] |= val; | |
3302 | break; | |
3303 | /* more stuff goes here */ | |
3304 | default: | |
3305 | as_fatal ("failed sanity check."); | |
3306 | } | |
3307 | } /* install_gen_operand() */ | |
fecd2382 | 3308 | |
7c15cbe8 RP |
3309 | /* |
3310 | * verify that we have some number of paren pairs, do m68k_ip_op(), and | |
3311 | * then deal with the bitfield hack. | |
3312 | */ | |
3313 | ||
355afbcd KR |
3314 | static char * |
3315 | crack_operand (str, opP) | |
3316 | register char *str; | |
3317 | register struct m68k_op *opP; | |
fecd2382 | 3318 | { |
355afbcd KR |
3319 | register int parens; |
3320 | register int c; | |
3321 | register char *beg_str; | |
6d27d3a2 | 3322 | |
355afbcd KR |
3323 | if (!str) |
3324 | { | |
3325 | return str; | |
3326 | } | |
3327 | beg_str = str; | |
3328 | for (parens = 0; *str && (parens > 0 || notend (str)); str++) | |
3329 | { | |
3330 | if (*str == '(') | |
3331 | parens++; | |
3332 | else if (*str == ')') | |
3333 | { | |
3334 | if (!parens) | |
3335 | { /* ERROR */ | |
3336 | opP->error = "Extra )"; | |
3337 | return str; | |
3338 | } | |
3339 | --parens; | |
f8701a3f | 3340 | } |
355afbcd KR |
3341 | } |
3342 | if (!*str && parens) | |
3343 | { /* ERROR */ | |
3344 | opP->error = "Missing )"; | |
3345 | return str; | |
3346 | } | |
3347 | c = *str; | |
3348 | *str = '\0'; | |
3349 | if (m68k_ip_op (beg_str, opP) == FAIL) | |
3350 | { | |
3351 | *str = c; | |
3352 | return str; | |
3353 | } | |
3354 | *str = c; | |
3355 | if (c == '}') | |
3356 | c = *++str; /* JF bitfield hack */ | |
3357 | if (c) | |
3358 | { | |
3359 | c = *++str; | |
3360 | if (!c) | |
3361 | as_bad ("Missing operand"); | |
3362 | } | |
3363 | return str; | |
fecd2382 RP |
3364 | } |
3365 | ||
3366 | /* See the comment up above where the #define notend(... is */ | |
3367 | #if 0 | |
355afbcd KR |
3368 | notend (s) |
3369 | char *s; | |
fecd2382 | 3370 | { |
355afbcd KR |
3371 | if (*s == ',') |
3372 | return 0; | |
3373 | if (*s == '{' || *s == '}') | |
3374 | return 0; | |
3375 | if (*s != ':') | |
3376 | return 1; | |
3377 | /* This kludge here is for the division cmd, which is a kludge */ | |
3378 | if (index ("aAdD#", s[1])) | |
3379 | return 0; | |
3380 | return 1; | |
fecd2382 | 3381 | } |
355afbcd | 3382 | |
fecd2382 RP |
3383 | #endif |
3384 | ||
3385 | /* This is the guts of the machine-dependent assembler. STR points to a | |
7c15cbe8 | 3386 | machine dependent instruction. This function is supposed to emit |
fecd2382 | 3387 | the frags/bytes it assembles to. |
a39116f1 | 3388 | */ |
a933d598 SC |
3389 | |
3390 | void | |
355afbcd KR |
3391 | insert_reg (regname, regnum) |
3392 | char *regname; | |
3393 | int regnum; | |
a933d598 SC |
3394 | { |
3395 | char buf[100]; | |
3396 | int i; | |
49864cfa | 3397 | symbolS *s; |
355afbcd KR |
3398 | |
3399 | #ifdef REGISTER_PREFIX | |
3400 | buf[0] = REGISTER_PREFIX; | |
3401 | strcpy (buf + 1, regname); | |
3402 | regname = buf; | |
3403 | #endif | |
3404 | ||
49864cfa KR |
3405 | symbol_table_insert (s = symbol_new (regname, reg_section, regnum, &zero_address_frag)); |
3406 | ||
3407 | verify_symbol_chain_2 (s); | |
a933d598 SC |
3408 | |
3409 | for (i = 0; regname[i]; i++) | |
355afbcd | 3410 | buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i]; |
a933d598 | 3411 | buf[i] = '\0'; |
6d27d3a2 | 3412 | |
49864cfa KR |
3413 | symbol_table_insert (s = symbol_new (buf, reg_section, regnum, &zero_address_frag)); |
3414 | verify_symbol_chain_2 (s); | |
a933d598 SC |
3415 | } |
3416 | ||
49864cfa | 3417 | struct init_entry |
355afbcd | 3418 | { |
bcb8dff8 | 3419 | const char *name; |
355afbcd | 3420 | int number; |
49864cfa | 3421 | }; |
355afbcd | 3422 | |
bcb8dff8 | 3423 | static const struct init_entry init_table[] = |
355afbcd | 3424 | { |
bcb8dff8 KR |
3425 | { "d0", DATA0 }, |
3426 | { "d1", DATA1 }, | |
3427 | { "d2", DATA2 }, | |
3428 | { "d3", DATA3 }, | |
3429 | { "d4", DATA4 }, | |
3430 | { "d5", DATA5 }, | |
3431 | { "d6", DATA6 }, | |
3432 | { "d7", DATA7 }, | |
3433 | { "a0", ADDR0 }, | |
3434 | { "a1", ADDR1 }, | |
3435 | { "a2", ADDR2 }, | |
3436 | { "a3", ADDR3 }, | |
3437 | { "a4", ADDR4 }, | |
3438 | { "a5", ADDR5 }, | |
3439 | { "a6", ADDR6 }, | |
3440 | { "fp", ADDR6 }, | |
3441 | { "a7", ADDR7 }, | |
3442 | { "sp", ADDR7 }, | |
3443 | { "fp0", FP0 }, | |
3444 | { "fp1", FP1 }, | |
3445 | { "fp2", FP2 }, | |
3446 | { "fp3", FP3 }, | |
3447 | { "fp4", FP4 }, | |
3448 | { "fp5", FP5 }, | |
3449 | { "fp6", FP6 }, | |
3450 | { "fp7", FP7 }, | |
3451 | { "fpi", FPI }, | |
3452 | { "fpiar", FPI }, | |
3453 | { "fpc", FPI }, | |
3454 | { "fps", FPS }, | |
3455 | { "fpsr", FPS }, | |
3456 | { "fpc", FPC }, | |
3457 | { "fpcr", FPC }, | |
3458 | ||
3459 | { "cop0", COP0 }, | |
3460 | { "cop1", COP1 }, | |
3461 | { "cop2", COP2 }, | |
3462 | { "cop3", COP3 }, | |
3463 | { "cop4", COP4 }, | |
3464 | { "cop5", COP5 }, | |
3465 | { "cop6", COP6 }, | |
3466 | { "cop7", COP7 }, | |
3467 | { "pc", PC }, | |
3468 | { "zpc", ZPC }, | |
3469 | { "sr", SR }, | |
3470 | ||
3471 | { "ccr", CCR }, | |
3472 | { "cc", CCR }, | |
3473 | ||
3474 | { "usp", USP }, | |
3475 | { "isp", ISP }, | |
3476 | { "sfc", SFC }, | |
3477 | { "dfc", DFC }, | |
3478 | { "cacr", CACR }, | |
3479 | { "caar", CAAR }, | |
3480 | ||
3481 | { "vbr", VBR }, | |
3482 | ||
3483 | { "msp", MSP }, | |
3484 | { "itt0", ITT0 }, | |
3485 | { "itt1", ITT1 }, | |
3486 | { "dtt0", DTT0 }, | |
3487 | { "dtt1", DTT1 }, | |
3488 | { "mmusr", MMUSR }, | |
3489 | { "tc", TC }, | |
3490 | { "srp", SRP }, | |
3491 | { "urp", URP }, | |
3492 | ||
3493 | { "ac", AC }, | |
3494 | { "bc", BC }, | |
3495 | { "cal", CAL }, | |
3496 | { "crp", CRP }, | |
3497 | { "drp", DRP }, | |
3498 | { "pcsr", PCSR }, | |
3499 | { "psr", PSR }, | |
3500 | { "scc", SCC }, | |
3501 | { "val", VAL }, | |
3502 | { "bad0", BAD0 }, | |
3503 | { "bad1", BAD1 }, | |
3504 | { "bad2", BAD2 }, | |
3505 | { "bad3", BAD3 }, | |
3506 | { "bad4", BAD4 }, | |
3507 | { "bad5", BAD5 }, | |
3508 | { "bad6", BAD6 }, | |
3509 | { "bad7", BAD7 }, | |
3510 | { "bac0", BAC0 }, | |
3511 | { "bac1", BAC1 }, | |
3512 | { "bac2", BAC2 }, | |
3513 | { "bac3", BAC3 }, | |
3514 | { "bac4", BAC4 }, | |
3515 | { "bac5", BAC5 }, | |
3516 | { "bac6", BAC6 }, | |
3517 | { "bac7", BAC7 }, | |
3518 | ||
3519 | { "ic", IC }, | |
3520 | { "dc", DC }, | |
3521 | { "nc", NC }, | |
3522 | ||
3523 | { "tt0", TT0 }, | |
3524 | { "tt1", TT1 }, | |
4134a793 | 3525 | /* 68ec030 versions of same */ |
bcb8dff8 KR |
3526 | { "ac0", TT0 }, |
3527 | { "ac1", TT1 }, | |
4134a793 | 3528 | /* 68ec030 access control unit, identical to 030 MMU status reg */ |
bcb8dff8 | 3529 | { "acusr", PSR }, |
a933d598 | 3530 | |
bcb8dff8 | 3531 | { 0, 0 } |
a933d598 SC |
3532 | }; |
3533 | ||
a933d598 | 3534 | void |
355afbcd | 3535 | init_regtable () |
a933d598 SC |
3536 | { |
3537 | int i; | |
6d27d3a2 | 3538 | for (i = 0; init_table[i].name; i++) |
355afbcd | 3539 | insert_reg (init_table[i].name, init_table[i].number); |
a933d598 | 3540 | } |
6d27d3a2 | 3541 | |
df3768fb | 3542 | static int no_68851, no_68881; |
a933d598 | 3543 | |
fecd2382 | 3544 | void |
355afbcd | 3545 | md_assemble (str) |
6d27d3a2 | 3546 | char *str; |
fecd2382 | 3547 | { |
355afbcd KR |
3548 | char *er; |
3549 | short *fromP; | |
3550 | char *toP = NULL; | |
3551 | int m, n = 0; | |
3552 | char *to_beg_P; | |
3553 | int shorts_this_frag; | |
3554 | static int done_first_time; | |
3555 | ||
3556 | if (!done_first_time) | |
3557 | { | |
3558 | done_first_time = 1; | |
4134a793 | 3559 | |
355afbcd KR |
3560 | if (cpu_of_arch (current_architecture) == 0) |
3561 | { | |
3562 | int cpu_type; | |
148eb5dd | 3563 | |
e284846a KR |
3564 | if (strcmp (TARGET_CPU, "m68000") == 0 |
3565 | || strcmp (TARGET_CPU, "m68302") == 0) | |
355afbcd KR |
3566 | cpu_type = m68000; |
3567 | else if (strcmp (TARGET_CPU, "m68010") == 0) | |
3568 | cpu_type = m68010; | |
3569 | else if (strcmp (TARGET_CPU, "m68020") == 0 | |
3570 | || strcmp (TARGET_CPU, "m68k") == 0) | |
3571 | cpu_type = m68020; | |
3572 | else if (strcmp (TARGET_CPU, "m68030") == 0) | |
3573 | cpu_type = m68030; | |
3574 | else if (strcmp (TARGET_CPU, "m68040") == 0) | |
3575 | cpu_type = m68040; | |
e284846a KR |
3576 | else if (strcmp (TARGET_CPU, "cpu32") == 0 |
3577 | || strcmp (TARGET_CPU, "m68331") == 0 | |
3578 | || strcmp (TARGET_CPU, "m68332") == 0 | |
3579 | || strcmp (TARGET_CPU, "m68333") == 0 | |
3580 | || strcmp (TARGET_CPU, "m68340") == 0) | |
355afbcd KR |
3581 | cpu_type = cpu32; |
3582 | else | |
3583 | cpu_type = m68020; | |
148eb5dd | 3584 | |
355afbcd KR |
3585 | current_architecture |= cpu_type; |
3586 | } | |
3587 | #if 0 /* Could be doing emulation. */ | |
3588 | if (current_architecture & m68881) | |
3589 | { | |
3590 | if (current_architecture & m68000) | |
3591 | as_bad ("incompatible processors 68000 and 68881/2 specified"); | |
3592 | if (current_architecture & m68010) | |
3593 | as_bad ("incompatible processors 68010 and 68881/2 specified"); | |
3594 | if (current_architecture & m68040) | |
3595 | as_bad ("incompatible processors 68040 and 68881/2 specified"); | |
3596 | } | |
3597 | #endif | |
3598 | /* What other incompatibilities could we check for? */ | |
6d27d3a2 | 3599 | |
355afbcd KR |
3600 | /* Toss in some default assumptions about coprocessors. */ |
3601 | if (!no_68881 | |
3602 | && (cpu_of_arch (current_architecture) | |
3603 | /* Can CPU32 have a 68881 coprocessor?? */ | |
3604 | & (m68020 | m68030 | cpu32))) | |
3605 | { | |
3606 | current_architecture |= m68881; | |
fecd2382 | 3607 | } |
355afbcd | 3608 | if (!no_68851 |
025b0302 ME |
3609 | && (cpu_of_arch (current_architecture) & m68020up) != 0 |
3610 | && cpu_of_arch (current_architecture) != m68040) | |
355afbcd KR |
3611 | { |
3612 | current_architecture |= m68851; | |
fecd2382 | 3613 | } |
355afbcd KR |
3614 | if (no_68881 && (current_architecture & m68881)) |
3615 | as_bad ("options for 68881 and no-68881 both given"); | |
3616 | if (no_68851 && (current_architecture & m68851)) | |
3617 | as_bad ("options for 68851 and no-68851 both given"); | |
3618 | done_first_time = 1; | |
3619 | } | |
6d27d3a2 | 3620 | |
e284846a | 3621 | memset ((char *) (&the_ins), '\0', sizeof (the_ins)); |
355afbcd KR |
3622 | m68k_ip (str); |
3623 | er = the_ins.error; | |
3624 | if (!er) | |
3625 | { | |
3626 | for (n = the_ins.numargs; n; --n) | |
3627 | if (the_ins.operands[n].error) | |
3628 | { | |
3629 | er = the_ins.operands[n].error; | |
3630 | break; | |
3631 | } | |
3632 | } | |
3633 | if (er) | |
3634 | { | |
3635 | as_bad ("%s -- statement `%s' ignored", er, str); | |
3636 | return; | |
3637 | } | |
6d27d3a2 | 3638 | |
355afbcd | 3639 | if (the_ins.nfrag == 0) |
49864cfa KR |
3640 | { |
3641 | /* No frag hacking involved; just put it out */ | |
355afbcd KR |
3642 | toP = frag_more (2 * the_ins.numo); |
3643 | fromP = &the_ins.opcode[0]; | |
3644 | for (m = the_ins.numo; m; --m) | |
3645 | { | |
3646 | md_number_to_chars (toP, (long) (*fromP), 2); | |
3647 | toP += 2; | |
3648 | fromP++; | |
f8701a3f | 3649 | } |
355afbcd KR |
3650 | /* put out symbol-dependent info */ |
3651 | for (m = 0; m < the_ins.nrel; m++) | |
3652 | { | |
3653 | switch (the_ins.reloc[m].wid) | |
3654 | { | |
3655 | case 'B': | |
3656 | n = 1; | |
3657 | break; | |
3658 | case 'b': | |
3659 | n = 1; | |
3660 | break; | |
3661 | case '3': | |
3662 | n = 2; | |
3663 | break; | |
3664 | case 'w': | |
3665 | n = 2; | |
3666 | break; | |
3667 | case 'l': | |
3668 | n = 4; | |
3669 | break; | |
3670 | default: | |
49864cfa KR |
3671 | as_fatal ("Don't know how to figure width of %c in md_assemble()", |
3672 | the_ins.reloc[m].wid); | |
355afbcd | 3673 | } |
6d27d3a2 | 3674 | |
bcb8dff8 KR |
3675 | fix_new_exp (frag_now, |
3676 | ((toP - frag_now->fr_literal) | |
3677 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
3678 | n, | |
3679 | &the_ins.reloc[m].exp, | |
3680 | the_ins.reloc[m].pcrel, | |
3681 | NO_RELOC); | |
f8701a3f | 3682 | } |
355afbcd KR |
3683 | return; |
3684 | } | |
3685 | ||
3686 | /* There's some frag hacking */ | |
3687 | for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) | |
3688 | { | |
3689 | int wid; | |
3690 | ||
3691 | if (n == 0) | |
3692 | wid = 2 * the_ins.fragb[n].fragoff; | |
3693 | else | |
3694 | wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
3695 | toP = frag_more (wid); | |
3696 | to_beg_P = toP; | |
3697 | shorts_this_frag = 0; | |
3698 | for (m = wid / 2; m; --m) | |
3699 | { | |
3700 | md_number_to_chars (toP, (long) (*fromP), 2); | |
3701 | toP += 2; | |
3702 | fromP++; | |
3703 | shorts_this_frag++; | |
3704 | } | |
3705 | for (m = 0; m < the_ins.nrel; m++) | |
3706 | { | |
49864cfa | 3707 | if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) |
355afbcd | 3708 | { |
49864cfa | 3709 | the_ins.reloc[m].n -= 2 * shorts_this_frag; |
355afbcd KR |
3710 | break; |
3711 | } | |
3712 | wid = the_ins.reloc[m].wid; | |
3713 | if (wid == 0) | |
3714 | continue; | |
3715 | the_ins.reloc[m].wid = 0; | |
3716 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
3717 | ||
bcb8dff8 KR |
3718 | fix_new_exp (frag_now, |
3719 | ((toP - frag_now->fr_literal) | |
3720 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
3721 | wid, | |
3722 | &the_ins.reloc[m].exp, | |
3723 | the_ins.reloc[m].pcrel, | |
3724 | NO_RELOC); | |
fecd2382 | 3725 | } |
49864cfa KR |
3726 | (void) frag_var (rs_machine_dependent, 10, 0, |
3727 | (relax_substateT) (the_ins.fragb[n].fragty), | |
3728 | the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); | |
355afbcd KR |
3729 | } |
3730 | n = (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
3731 | shorts_this_frag = 0; | |
3732 | if (n) | |
3733 | { | |
3734 | toP = frag_more (n * sizeof (short)); | |
3735 | while (n--) | |
3736 | { | |
3737 | md_number_to_chars (toP, (long) (*fromP), 2); | |
3738 | toP += 2; | |
3739 | fromP++; | |
3740 | shorts_this_frag++; | |
fecd2382 | 3741 | } |
355afbcd KR |
3742 | } |
3743 | for (m = 0; m < the_ins.nrel; m++) | |
3744 | { | |
3745 | int wid; | |
3746 | ||
3747 | wid = the_ins.reloc[m].wid; | |
3748 | if (wid == 0) | |
3749 | continue; | |
3750 | the_ins.reloc[m].wid = 0; | |
3751 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
3752 | ||
bcb8dff8 KR |
3753 | fix_new_exp (frag_now, |
3754 | ((the_ins.reloc[m].n + toP - frag_now->fr_literal) | |
3755 | - shorts_this_frag * 2), | |
3756 | wid, | |
3757 | &the_ins.reloc[m].exp, | |
3758 | the_ins.reloc[m].pcrel, | |
3759 | NO_RELOC); | |
355afbcd | 3760 | } |
fecd2382 RP |
3761 | } |
3762 | ||
e284846a KR |
3763 | /* See BREAK_UP_BIG_DECL definition, above. */ |
3764 | static struct m68k_opcode * | |
3765 | opcode_ptr (i) | |
3766 | int i; | |
3767 | { | |
3768 | #ifdef DO_BREAK_UP_BIG_DECL | |
3769 | int lim1 = sizeof (m68k_opcodes) / sizeof (m68k_opcodes[0]); | |
3770 | if (i >= lim1) | |
3771 | return m68k_opcodes_2 + (i - lim1); | |
3772 | #endif | |
3773 | return m68k_opcodes + i; | |
3774 | } | |
f8701a3f | 3775 | |
fecd2382 | 3776 | void |
355afbcd | 3777 | md_begin () |
fecd2382 | 3778 | { |
355afbcd | 3779 | /* |
e284846a KR |
3780 | * md_begin -- set up hash tables with 68000 instructions. |
3781 | * similar to what the vax assembler does. ---phr | |
3782 | */ | |
355afbcd | 3783 | /* RMS claims the thing to do is take the m68k-opcode.h table, and make |
e284846a KR |
3784 | a copy of it at runtime, adding in the information we want but isn't |
3785 | there. I think it'd be better to have an awk script hack the table | |
3786 | at compile time. Or even just xstr the table and use it as-is. But | |
3787 | my lord ghod hath spoken, so we do it this way. Excuse the ugly var | |
3788 | names. */ | |
6d27d3a2 | 3789 | |
49864cfa | 3790 | register CONST struct m68k_opcode *ins; |
355afbcd | 3791 | register struct m68k_incant *hack, *slak; |
bcb8dff8 | 3792 | register const char *retval = 0; /* empty string, or error msg text */ |
355afbcd KR |
3793 | register unsigned int i; |
3794 | register char c; | |
3795 | ||
3796 | if ((op_hash = hash_new ()) == NULL) | |
3797 | as_fatal ("Virtual memory exhausted"); | |
3798 | ||
3799 | obstack_begin (&robyn, 4000); | |
e284846a | 3800 | for (i = 0; i < numopcodes; i++) |
355afbcd KR |
3801 | { |
3802 | hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant)); | |
3803 | do | |
3804 | { | |
e284846a KR |
3805 | ins = opcode_ptr (i); |
3806 | /* We *could* ignore insns that don't match our arch here | |
3807 | but just leaving them out of the hash. */ | |
355afbcd KR |
3808 | slak->m_operands = ins->args; |
3809 | slak->m_opnum = strlen (slak->m_operands) / 2; | |
3810 | slak->m_arch = ins->arch; | |
3811 | slak->m_opcode = ins->opcode; | |
3812 | /* This is kludgey */ | |
3813 | slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1; | |
e284846a KR |
3814 | if (i + 1 != numopcodes |
3815 | && !strcmp (ins->name, opcode_ptr (i + 1)->name)) | |
355afbcd KR |
3816 | { |
3817 | slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant)); | |
e284846a | 3818 | i++; |
355afbcd KR |
3819 | } |
3820 | else | |
3821 | slak->m_next = 0; | |
3822 | slak = slak->m_next; | |
f8701a3f | 3823 | } |
355afbcd KR |
3824 | while (slak); |
3825 | ||
3826 | retval = hash_insert (op_hash, ins->name, (char *) hack); | |
3827 | /* Didn't his mommy tell him about null pointers? */ | |
3828 | if (retval && *retval) | |
3829 | as_bad ("Internal Error: Can't hash %s: %s", ins->name, retval); | |
3830 | } | |
6d27d3a2 | 3831 | |
355afbcd KR |
3832 | for (i = 0; i < sizeof (mklower_table); i++) |
3833 | mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c; | |
6d27d3a2 | 3834 | |
355afbcd KR |
3835 | for (i = 0; i < sizeof (notend_table); i++) |
3836 | { | |
3837 | notend_table[i] = 0; | |
3838 | alt_notend_table[i] = 0; | |
3839 | } | |
3840 | notend_table[','] = 1; | |
3841 | notend_table['{'] = 1; | |
3842 | notend_table['}'] = 1; | |
3843 | alt_notend_table['a'] = 1; | |
3844 | alt_notend_table['A'] = 1; | |
3845 | alt_notend_table['d'] = 1; | |
3846 | alt_notend_table['D'] = 1; | |
3847 | alt_notend_table['#'] = 1; | |
3848 | alt_notend_table['f'] = 1; | |
3849 | alt_notend_table['F'] = 1; | |
fecd2382 | 3850 | #ifdef REGISTER_PREFIX |
355afbcd | 3851 | alt_notend_table[REGISTER_PREFIX] = 1; |
fecd2382 | 3852 | #endif |
0069b1f6 | 3853 | #ifdef OPTIONAL_REGISTER_PREFIX |
355afbcd | 3854 | alt_notend_table[OPTIONAL_REGISTER_PREFIX] = 1; |
0069b1f6 | 3855 | #endif |
f8701a3f | 3856 | |
3ad9ec6a | 3857 | #ifndef MIT_SYNTAX_ONLY |
355afbcd | 3858 | /* Insert pseudo ops, these have to go into the opcode table since |
bcb8dff8 | 3859 | gas expects pseudo ops to start with a dot */ |
355afbcd KR |
3860 | { |
3861 | int n = 0; | |
3862 | while (mote_pseudo_table[n].poc_name) | |
3863 | { | |
3864 | hack = (struct m68k_incant *) | |
3865 | obstack_alloc (&robyn, sizeof (struct m68k_incant)); | |
3866 | hash_insert (op_hash, | |
3867 | mote_pseudo_table[n].poc_name, (char *) hack); | |
3868 | hack->m_operands = 0; | |
3869 | hack->m_opnum = n; | |
3870 | n++; | |
3871 | } | |
3872 | } | |
3ad9ec6a ILT |
3873 | #endif |
3874 | ||
355afbcd | 3875 | init_regtable (); |
fecd2382 RP |
3876 | } |
3877 | ||
3878 | #if 0 | |
3879 | #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \ | |
a39116f1 RP |
3880 | || (*s == ':' && strchr("aAdD#", s[1]))) \ |
3881 | ? 0 : 1) | |
fecd2382 RP |
3882 | #endif |
3883 | ||
3884 | /* This funciton is called once, before the assembler exits. It is | |
3885 | supposed to do any final cleanup for this part of the assembler. | |
a39116f1 | 3886 | */ |
fecd2382 | 3887 | void |
355afbcd | 3888 | md_end () |
fecd2382 RP |
3889 | { |
3890 | } | |
3891 | ||
3892 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
3893 | #define MAX_LITTLENUMS 6 | |
3894 | ||
3895 | /* Turn a string in input_line_pointer into a floating point constant of type | |
3896 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
3897 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
a39116f1 | 3898 | */ |
fecd2382 | 3899 | char * |
355afbcd KR |
3900 | md_atof (type, litP, sizeP) |
3901 | char type; | |
3902 | char *litP; | |
3903 | int *sizeP; | |
fecd2382 | 3904 | { |
355afbcd KR |
3905 | int prec; |
3906 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
3907 | LITTLENUM_TYPE *wordP; | |
3908 | char *t; | |
3909 | char *atof_ieee (); | |
6d27d3a2 | 3910 | |
355afbcd KR |
3911 | switch (type) |
3912 | { | |
3913 | case 'f': | |
3914 | case 'F': | |
3915 | case 's': | |
3916 | case 'S': | |
3917 | prec = 2; | |
3918 | break; | |
6d27d3a2 | 3919 | |
355afbcd KR |
3920 | case 'd': |
3921 | case 'D': | |
3922 | case 'r': | |
3923 | case 'R': | |
3924 | prec = 4; | |
3925 | break; | |
6d27d3a2 | 3926 | |
355afbcd KR |
3927 | case 'x': |
3928 | case 'X': | |
3929 | prec = 6; | |
3930 | break; | |
6d27d3a2 | 3931 | |
355afbcd KR |
3932 | case 'p': |
3933 | case 'P': | |
3934 | prec = 6; | |
3935 | break; | |
6d27d3a2 | 3936 | |
355afbcd KR |
3937 | default: |
3938 | *sizeP = 0; | |
3939 | return "Bad call to MD_ATOF()"; | |
3940 | } | |
3941 | t = atof_ieee (input_line_pointer, type, words); | |
3942 | if (t) | |
3943 | input_line_pointer = t; | |
3944 | ||
3945 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
3946 | for (wordP = words; prec--;) | |
3947 | { | |
3948 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); | |
3949 | litP += sizeof (LITTLENUM_TYPE); | |
3950 | } | |
49864cfa | 3951 | return 0; |
fecd2382 RP |
3952 | } |
3953 | ||
3954 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate | |
3955 | for use in the a.out file, and stores them in the array pointed to by buf. | |
3956 | This knows about the endian-ness of the target machine and does | |
3957 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
3958 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
3959 | LITTLENUMS (shorts, here at least) | |
a39116f1 | 3960 | */ |
fecd2382 | 3961 | void |
355afbcd KR |
3962 | md_number_to_chars (buf, val, n) |
3963 | char *buf; | |
025b0302 | 3964 | valueT val; |
355afbcd | 3965 | int n; |
fecd2382 | 3966 | { |
355afbcd KR |
3967 | switch (n) |
3968 | { | |
3969 | case 1: | |
3970 | *buf++ = val; | |
3971 | break; | |
3972 | case 2: | |
3973 | *buf++ = (val >> 8); | |
3974 | *buf++ = val; | |
3975 | break; | |
3976 | case 4: | |
3977 | *buf++ = (val >> 24); | |
3978 | *buf++ = (val >> 16); | |
3979 | *buf++ = (val >> 8); | |
3980 | *buf++ = val; | |
3981 | break; | |
3982 | default: | |
3983 | as_fatal ("failed sanity check."); | |
3984 | } | |
fecd2382 RP |
3985 | } |
3986 | ||
49864cfa KR |
3987 | static void |
3988 | md_apply_fix_2 (fixP, val) | |
355afbcd KR |
3989 | fixS *fixP; |
3990 | long val; | |
fecd2382 | 3991 | { |
49864cfa KR |
3992 | unsigned long upper_limit; |
3993 | long lower_limit; | |
3994 | ||
587c4264 | 3995 | #ifdef IBM_COMPILER_SUX |
355afbcd | 3996 | /* This is unnecessary but it convinces the native rs6000 |
e284846a | 3997 | compiler to generate the code we want. */ |
355afbcd KR |
3998 | char *buf = fixP->fx_frag->fr_literal; |
3999 | buf += fixP->fx_where; | |
587c4264 | 4000 | #else /* IBM_COMPILER_SUX */ |
355afbcd | 4001 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
587c4264 | 4002 | #endif /* IBM_COMPILER_SUX */ |
6d27d3a2 | 4003 | |
355afbcd KR |
4004 | switch (fixP->fx_size) |
4005 | { | |
4006 | case 1: | |
4007 | *buf++ = val; | |
49864cfa KR |
4008 | upper_limit = 0x7f; |
4009 | lower_limit = -0x80; | |
355afbcd KR |
4010 | break; |
4011 | case 2: | |
4012 | *buf++ = (val >> 8); | |
4013 | *buf++ = val; | |
49864cfa KR |
4014 | upper_limit = 0x7fff; |
4015 | lower_limit = -0x8000; | |
355afbcd KR |
4016 | break; |
4017 | case 4: | |
4018 | *buf++ = (val >> 24); | |
4019 | *buf++ = (val >> 16); | |
4020 | *buf++ = (val >> 8); | |
4021 | *buf++ = val; | |
49864cfa KR |
4022 | upper_limit = 0x7fffffff; |
4023 | lower_limit = -0x80000000; | |
355afbcd KR |
4024 | break; |
4025 | default: | |
4026 | BAD_CASE (fixP->fx_size); | |
4027 | } | |
49864cfa KR |
4028 | |
4029 | /* For non-pc-relative values, it's conceivable we might get something | |
4030 | like "0xff" for a byte field. So extend the upper part of the range | |
4031 | to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", | |
4032 | so that we can do any range checking at all. */ | |
4033 | if (!fixP->fx_pcrel) | |
4034 | upper_limit = upper_limit * 2 + 1; | |
4035 | ||
4036 | if ((unsigned) val > upper_limit && (val > 0 || val < lower_limit)) | |
4037 | as_bad ("value out of range"); | |
fecd2382 RP |
4038 | } |
4039 | ||
49864cfa KR |
4040 | #ifdef BFD_ASSEMBLER |
4041 | int | |
4042 | md_apply_fix (fixP, valp) | |
4043 | fixS *fixP; | |
4044 | long *valp; | |
4045 | { | |
4046 | md_apply_fix_2 (fixP, *valp); | |
4047 | return 1; | |
4048 | } | |
4049 | #else | |
4050 | void md_apply_fix (fixP, val) | |
4051 | fixS *fixP; | |
4052 | long val; | |
4053 | { | |
4054 | md_apply_fix_2 (fixP, val); | |
4055 | } | |
4056 | #endif | |
fecd2382 RP |
4057 | |
4058 | /* *fragP has been relaxed to its final size, and now needs to have | |
4059 | the bytes inside it modified to conform to the new size There is UGLY | |
4060 | MAGIC here. .. | |
a39116f1 | 4061 | */ |
fecd2382 | 4062 | void |
49864cfa | 4063 | md_convert_frag_1 (fragP) |
355afbcd | 4064 | register fragS *fragP; |
fecd2382 | 4065 | { |
355afbcd KR |
4066 | long disp; |
4067 | long ext = 0; | |
6d27d3a2 | 4068 | |
355afbcd KR |
4069 | /* Address in object code of the displacement. */ |
4070 | register int object_address = fragP->fr_fix + fragP->fr_address; | |
6d27d3a2 | 4071 | |
f6e504fe | 4072 | #ifdef IBM_COMPILER_SUX |
355afbcd | 4073 | /* This is wrong but it convinces the native rs6000 compiler to |
e284846a | 4074 | generate the code we want. */ |
355afbcd KR |
4075 | register char *buffer_address = fragP->fr_literal; |
4076 | buffer_address += fragP->fr_fix; | |
f6e504fe | 4077 | #else /* IBM_COMPILER_SUX */ |
355afbcd KR |
4078 | /* Address in gas core of the place to store the displacement. */ |
4079 | register char *buffer_address = fragP->fr_fix + fragP->fr_literal; | |
f6e504fe | 4080 | #endif /* IBM_COMPILER_SUX */ |
6d27d3a2 | 4081 | |
355afbcd | 4082 | /* No longer true: know(fragP->fr_symbol); */ |
6d27d3a2 | 4083 | |
355afbcd KR |
4084 | /* The displacement of the address, from current location. */ |
4085 | disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; | |
4086 | disp = (disp + fragP->fr_offset) - object_address; | |
6d27d3a2 | 4087 | |
355afbcd KR |
4088 | switch (fragP->fr_subtype) |
4089 | { | |
4090 | case TAB (BCC68000, BYTE): | |
4091 | case TAB (ABRANCH, BYTE): | |
4092 | know (issbyte (disp)); | |
4093 | if (disp == 0) | |
4094 | as_bad ("short branch with zero offset: use :w"); | |
4095 | fragP->fr_opcode[1] = disp; | |
4096 | ext = 0; | |
4097 | break; | |
4098 | case TAB (DBCC, SHORT): | |
4099 | know (issword (disp)); | |
4100 | ext = 2; | |
4101 | break; | |
4102 | case TAB (BCC68000, SHORT): | |
4103 | case TAB (ABRANCH, SHORT): | |
4104 | know (issword (disp)); | |
4105 | fragP->fr_opcode[1] = 0x00; | |
4106 | ext = 2; | |
4107 | break; | |
4108 | case TAB (ABRANCH, LONG): | |
4109 | if (cpu_of_arch (current_architecture) < m68020) | |
4110 | { | |
4111 | if (fragP->fr_opcode[0] == 0x61) | |
4112 | { | |
4113 | fragP->fr_opcode[0] = 0x4E; | |
bcb8dff8 | 4114 | fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */ |
49864cfa | 4115 | subseg_change (text_section, 0); /* @@ */ |
355afbcd KR |
4116 | |
4117 | fix_new (fragP, | |
4118 | fragP->fr_fix, | |
4119 | 4, | |
4120 | fragP->fr_symbol, | |
355afbcd KR |
4121 | fragP->fr_offset, |
4122 | 0, | |
4123 | NO_RELOC); | |
4124 | ||
4125 | fragP->fr_fix += 4; | |
4126 | ext = 0; | |
4127 | } | |
4128 | else if (fragP->fr_opcode[0] == 0x60) | |
4129 | { | |
4130 | fragP->fr_opcode[0] = 0x4E; | |
bcb8dff8 | 4131 | fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */ |
49864cfa | 4132 | subseg_change (text_section, 0); /* @@ */ |
bcb8dff8 KR |
4133 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4134 | fragP->fr_offset, 0, NO_RELOC); | |
355afbcd KR |
4135 | fragP->fr_fix += 4; |
4136 | ext = 0; | |
4137 | } | |
4138 | else | |
4139 | { | |
4140 | as_bad ("Long branch offset not supported."); | |
4141 | } | |
4142 | } | |
4143 | else | |
4144 | { | |
bcb8dff8 | 4145 | fragP->fr_opcode[1] = (char) 0xff; |
355afbcd KR |
4146 | ext = 4; |
4147 | } | |
4148 | break; | |
4149 | case TAB (BCC68000, LONG): | |
4150 | /* only Bcc 68000 instructions can come here */ | |
4151 | /* change bcc into b!cc/jmp absl long */ | |
4152 | fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ | |
4153 | fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */ | |
6d27d3a2 | 4154 | |
355afbcd | 4155 | /* JF: these used to be fr_opcode[2,3], but they may be in a |
fecd2382 RP |
4156 | different frag, in which case refering to them is a no-no. |
4157 | Only fr_opcode[0,1] are guaranteed to work. */ | |
355afbcd | 4158 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ |
bcb8dff8 | 4159 | *buffer_address++ = (char) 0xf9; |
355afbcd | 4160 | fragP->fr_fix += 2; /* account for jmp instruction */ |
49864cfa | 4161 | subseg_change (text_section, 0); |
bcb8dff8 KR |
4162 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4163 | fragP->fr_offset, 0, NO_RELOC); | |
355afbcd KR |
4164 | fragP->fr_fix += 4; |
4165 | ext = 0; | |
4166 | break; | |
4167 | case TAB (DBCC, LONG): | |
4168 | /* only DBcc 68000 instructions can come here */ | |
4169 | /* change dbcc into dbcc/jmp absl long */ | |
4170 | /* JF: these used to be fr_opcode[2-7], but that's wrong */ | |
4171 | *buffer_address++ = 0x00; /* branch offset = 4 */ | |
4172 | *buffer_address++ = 0x04; | |
4173 | *buffer_address++ = 0x60; /* put in bra pc+6 */ | |
4174 | *buffer_address++ = 0x06; | |
4175 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ | |
bcb8dff8 | 4176 | *buffer_address++ = (char) 0xf9; |
355afbcd KR |
4177 | |
4178 | fragP->fr_fix += 6; /* account for bra/jmp instructions */ | |
49864cfa | 4179 | subseg_change (text_section, 0); |
bcb8dff8 | 4180 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
49864cfa | 4181 | fragP->fr_offset, 0, NO_RELOC); |
355afbcd KR |
4182 | fragP->fr_fix += 4; |
4183 | ext = 0; | |
4184 | break; | |
4185 | case TAB (FBRANCH, SHORT): | |
4186 | know ((fragP->fr_opcode[1] & 0x40) == 0); | |
4187 | ext = 2; | |
4188 | break; | |
4189 | case TAB (FBRANCH, LONG): | |
4190 | fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */ | |
4191 | ext = 4; | |
4192 | break; | |
4193 | case TAB (PCREL, SHORT): | |
4194 | ext = 2; | |
4195 | break; | |
4196 | case TAB (PCREL, LONG): | |
4197 | /* The thing to do here is force it to ABSOLUTE LONG, since | |
f8701a3f | 4198 | PCREL is really trying to shorten an ABSOLUTE address anyway */ |
355afbcd | 4199 | /* JF FOO This code has not been tested */ |
49864cfa | 4200 | subseg_change (text_section, 0); |
bcb8dff8 | 4201 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
49864cfa | 4202 | 0, NO_RELOC); |
355afbcd | 4203 | if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) |
bcb8dff8 KR |
4204 | as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx", |
4205 | (unsigned) fragP->fr_opcode[0], | |
4206 | (unsigned long) fragP->fr_address); | |
355afbcd KR |
4207 | fragP->fr_opcode[1] &= ~0x3F; |
4208 | fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ | |
4209 | fragP->fr_fix += 4; | |
355afbcd KR |
4210 | ext = 0; |
4211 | break; | |
4212 | case TAB (PCLEA, SHORT): | |
49864cfa KR |
4213 | subseg_change (text_section, 0); |
4214 | fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, | |
bcb8dff8 | 4215 | fragP->fr_offset, 1, NO_RELOC); |
355afbcd KR |
4216 | fragP->fr_opcode[1] &= ~0x3F; |
4217 | fragP->fr_opcode[1] |= 0x3A; | |
4218 | ext = 2; | |
4219 | break; | |
4220 | case TAB (PCLEA, LONG): | |
49864cfa KR |
4221 | subseg_change (text_section, 0); |
4222 | fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol, | |
bcb8dff8 | 4223 | fragP->fr_offset + 2, 1, NO_RELOC); |
355afbcd KR |
4224 | *buffer_address++ = 0x01; |
4225 | *buffer_address++ = 0x70; | |
4226 | fragP->fr_fix += 2; | |
355afbcd KR |
4227 | ext = 4; |
4228 | break; | |
49864cfa | 4229 | } |
355afbcd KR |
4230 | |
4231 | if (ext) | |
4232 | { | |
4233 | md_number_to_chars (buffer_address, (long) disp, (int) ext); | |
4234 | fragP->fr_fix += ext; | |
49864cfa KR |
4235 | } |
4236 | } | |
355afbcd | 4237 | |
49864cfa KR |
4238 | #ifndef BFD_ASSEMBLER |
4239 | ||
4240 | void | |
4241 | md_convert_frag (headers, fragP) | |
4242 | object_headers *headers; | |
4243 | fragS *fragP; | |
4244 | { | |
4245 | md_convert_frag_1 (fragP); | |
4246 | } | |
4247 | ||
4248 | #else | |
4249 | ||
4250 | void | |
4251 | md_convert_frag (abfd, sec, fragP) | |
4252 | bfd *abfd; | |
4253 | asection sec; | |
4254 | fragS *fragP; | |
4255 | { | |
4256 | md_convert_frag_1 (fragP); | |
4257 | } | |
4258 | #endif | |
355afbcd KR |
4259 | |
4260 | /* Force truly undefined symbols to their maximum size, and generally set up | |
4261 | the frag list to be relaxed | |
4262 | */ | |
4263 | int | |
4264 | md_estimate_size_before_relax (fragP, segment) | |
4265 | register fragS *fragP; | |
4266 | segT segment; | |
4267 | { | |
4268 | int old_fix; | |
4269 | register char *buffer_address = fragP->fr_fix + fragP->fr_literal; | |
4270 | ||
4271 | old_fix = fragP->fr_fix; | |
4272 | ||
4273 | /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */ | |
4274 | switch (fragP->fr_subtype) | |
4275 | { | |
4276 | ||
4277 | case TAB (ABRANCH, SZ_UNDEF): | |
4278 | { | |
4279 | if ((fragP->fr_symbol != NULL) /* Not absolute */ | |
4280 | && S_GET_SEGMENT (fragP->fr_symbol) == segment) | |
4281 | { | |
4282 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); | |
4283 | break; | |
4284 | } | |
4285 | else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020)) | |
4286 | { | |
4287 | /* On 68000, or for absolute value, switch to abs long */ | |
4288 | /* FIXME, we should check abs val, pick short or long */ | |
4289 | if (fragP->fr_opcode[0] == 0x61) | |
4290 | { | |
4291 | fragP->fr_opcode[0] = 0x4E; | |
bcb8dff8 | 4292 | fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */ |
49864cfa | 4293 | subseg_change (text_section, 0); |
355afbcd | 4294 | fix_new (fragP, fragP->fr_fix, 4, |
bcb8dff8 | 4295 | fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC); |
355afbcd KR |
4296 | fragP->fr_fix += 4; |
4297 | frag_wane (fragP); | |
4298 | } | |
4299 | else if (fragP->fr_opcode[0] == 0x60) | |
4300 | { | |
4301 | fragP->fr_opcode[0] = 0x4E; | |
bcb8dff8 | 4302 | fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */ |
49864cfa | 4303 | subseg_change (text_section, 0); |
355afbcd | 4304 | fix_new (fragP, fragP->fr_fix, 4, |
bcb8dff8 | 4305 | fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC); |
355afbcd KR |
4306 | fragP->fr_fix += 4; |
4307 | frag_wane (fragP); | |
4308 | } | |
4309 | else | |
4310 | { | |
4311 | as_warn ("Long branch offset to extern symbol not supported."); | |
4312 | } | |
4313 | } | |
4314 | else | |
4315 | { /* Symbol is still undefined. Make it simple */ | |
4316 | fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, | |
bcb8dff8 | 4317 | fragP->fr_offset + 4, 1, NO_RELOC); |
355afbcd | 4318 | fragP->fr_fix += 4; |
bcb8dff8 | 4319 | fragP->fr_opcode[1] = (char) 0xff; |
355afbcd KR |
4320 | frag_wane (fragP); |
4321 | break; | |
4322 | } | |
4323 | ||
a39116f1 | 4324 | break; |
355afbcd | 4325 | } /* case TAB(ABRANCH,SZ_UNDEF) */ |
6d27d3a2 | 4326 | |
355afbcd KR |
4327 | case TAB (FBRANCH, SZ_UNDEF): |
4328 | { | |
4329 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l']) | |
4330 | { | |
4331 | fragP->fr_subtype = TAB (FBRANCH, SHORT); | |
4332 | fragP->fr_var += 2; | |
4333 | } | |
4334 | else | |
4335 | { | |
4336 | fragP->fr_subtype = TAB (FBRANCH, LONG); | |
4337 | fragP->fr_var += 4; | |
4338 | } | |
4339 | break; | |
4340 | } /* TAB(FBRANCH,SZ_UNDEF) */ | |
6d27d3a2 | 4341 | |
355afbcd KR |
4342 | case TAB (PCREL, SZ_UNDEF): |
4343 | { | |
4344 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l']) | |
4345 | { | |
4346 | fragP->fr_subtype = TAB (PCREL, SHORT); | |
4347 | fragP->fr_var += 2; | |
4348 | } | |
4349 | else | |
4350 | { | |
4351 | fragP->fr_subtype = TAB (PCREL, LONG); | |
4352 | fragP->fr_var += 4; | |
4353 | } | |
4354 | break; | |
4355 | } /* TAB(PCREL,SZ_UNDEF) */ | |
6d27d3a2 | 4356 | |
355afbcd KR |
4357 | case TAB (BCC68000, SZ_UNDEF): |
4358 | { | |
4359 | if ((fragP->fr_symbol != NULL) | |
4360 | && S_GET_SEGMENT (fragP->fr_symbol) == segment) | |
4361 | { | |
4362 | fragP->fr_subtype = TAB (BCC68000, BYTE); | |
4363 | break; | |
4364 | } | |
4365 | /* only Bcc 68000 instructions can come here */ | |
4366 | /* change bcc into b!cc/jmp absl long */ | |
4367 | fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ | |
4368 | if (flagseen['l']) | |
4369 | { | |
4370 | fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */ | |
4371 | /* JF: these were fr_opcode[2,3] */ | |
4372 | buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */ | |
bcb8dff8 | 4373 | buffer_address[1] = (char) 0xf8; |
355afbcd | 4374 | fragP->fr_fix += 2; /* account for jmp instruction */ |
49864cfa | 4375 | subseg_change (text_section, 0); |
bcb8dff8 | 4376 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
355afbcd KR |
4377 | fragP->fr_offset, 0, NO_RELOC); |
4378 | fragP->fr_fix += 2; | |
4379 | } | |
4380 | else | |
4381 | { | |
4382 | fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */ | |
4383 | /* JF: these were fr_opcode[2,3] */ | |
4384 | buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */ | |
bcb8dff8 | 4385 | buffer_address[1] = (char) 0xf9; |
355afbcd | 4386 | fragP->fr_fix += 2; /* account for jmp instruction */ |
49864cfa | 4387 | subseg_change (text_section, 0); |
bcb8dff8 | 4388 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
355afbcd KR |
4389 | fragP->fr_offset, 0, NO_RELOC); |
4390 | fragP->fr_fix += 4; | |
4391 | } | |
4392 | frag_wane (fragP); | |
4393 | break; | |
4394 | } /* case TAB(BCC68000,SZ_UNDEF) */ | |
f8701a3f | 4395 | |
355afbcd KR |
4396 | case TAB (DBCC, SZ_UNDEF): |
4397 | { | |
4398 | if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment) | |
4399 | { | |
4400 | fragP->fr_subtype = TAB (DBCC, SHORT); | |
4401 | fragP->fr_var += 2; | |
4402 | break; | |
4403 | } | |
4404 | /* only DBcc 68000 instructions can come here */ | |
4405 | /* change dbcc into dbcc/jmp absl long */ | |
4406 | /* JF: these used to be fr_opcode[2-4], which is wrong. */ | |
4407 | buffer_address[0] = 0x00; /* branch offset = 4 */ | |
4408 | buffer_address[1] = 0x04; | |
4409 | buffer_address[2] = 0x60; /* put in bra pc + ... */ | |
4410 | ||
4411 | if (flagseen['l']) | |
4412 | { | |
4413 | /* JF: these were fr_opcode[5-7] */ | |
4414 | buffer_address[3] = 0x04; /* plus 4 */ | |
4415 | buffer_address[4] = 0x4e; /* Put in Jump Word */ | |
bcb8dff8 | 4416 | buffer_address[5] = (char) 0xf8; |
355afbcd | 4417 | fragP->fr_fix += 6; /* account for bra/jmp instruction */ |
49864cfa | 4418 | subseg_change (text_section, 0); |
bcb8dff8 | 4419 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
355afbcd KR |
4420 | fragP->fr_offset, 0, NO_RELOC); |
4421 | fragP->fr_fix += 2; | |
4422 | } | |
4423 | else | |
4424 | { | |
4425 | /* JF: these were fr_opcode[5-7] */ | |
4426 | buffer_address[3] = 0x06; /* Plus 6 */ | |
4427 | buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */ | |
bcb8dff8 | 4428 | buffer_address[5] = (char) 0xf9; |
355afbcd | 4429 | fragP->fr_fix += 6; /* account for bra/jmp instruction */ |
49864cfa | 4430 | subseg_change (text_section, 0); |
bcb8dff8 | 4431 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
355afbcd KR |
4432 | fragP->fr_offset, 0, NO_RELOC); |
4433 | fragP->fr_fix += 4; | |
4434 | } | |
6d27d3a2 | 4435 | |
355afbcd KR |
4436 | frag_wane (fragP); |
4437 | break; | |
4438 | } /* case TAB(DBCC,SZ_UNDEF) */ | |
6d27d3a2 | 4439 | |
355afbcd KR |
4440 | case TAB (PCLEA, SZ_UNDEF): |
4441 | { | |
4442 | if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment || flagseen['l']) | |
4443 | { | |
4444 | fragP->fr_subtype = TAB (PCLEA, SHORT); | |
4445 | fragP->fr_var += 2; | |
4446 | } | |
4447 | else | |
4448 | { | |
4449 | fragP->fr_subtype = TAB (PCLEA, LONG); | |
4450 | fragP->fr_var += 6; | |
4451 | } | |
4452 | break; | |
4453 | } /* TAB(PCLEA,SZ_UNDEF) */ | |
6d27d3a2 | 4454 | |
355afbcd KR |
4455 | default: |
4456 | break; | |
6d27d3a2 | 4457 | |
355afbcd | 4458 | } /* switch on subtype looking for SZ_UNDEF's. */ |
6d27d3a2 | 4459 | |
355afbcd KR |
4460 | /* now that SZ_UNDEF are taken care of, check others */ |
4461 | switch (fragP->fr_subtype) | |
4462 | { | |
4463 | case TAB (BCC68000, BYTE): | |
4464 | case TAB (ABRANCH, BYTE): | |
4465 | /* We can't do a short jump to the next instruction, | |
a39116f1 | 4466 | so we force word mode. */ |
355afbcd KR |
4467 | if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 && |
4468 | fragP->fr_symbol->sy_frag == fragP->fr_next) | |
4469 | { | |
4470 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
4471 | fragP->fr_var += 2; | |
fecd2382 | 4472 | } |
355afbcd KR |
4473 | break; |
4474 | default: | |
4475 | break; | |
4476 | } | |
4477 | return fragP->fr_var + fragP->fr_fix - old_fix; | |
fecd2382 RP |
4478 | } |
4479 | ||
4480 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
6d27d3a2 | 4481 | /* the bit-field entries in the relocation_info struct plays hell |
fecd2382 RP |
4482 | with the byte-order problems of cross-assembly. So as a hack, |
4483 | I added this mach. dependent ri twiddler. Ugly, but it gets | |
4484 | you there. -KWK */ | |
4485 | /* on m68k: first 4 bytes are normal unsigned long, next three bytes | |
a39116f1 RP |
4486 | are symbolnum, most sig. byte first. Last byte is broken up with |
4487 | bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower | |
4488 | nibble as nuthin. (on Sun 3 at least) */ | |
fecd2382 RP |
4489 | /* Translate the internal relocation information into target-specific |
4490 | format. */ | |
a79c6033 | 4491 | #ifdef comment |
fecd2382 | 4492 | void |
355afbcd KR |
4493 | md_ri_to_chars (the_bytes, ri) |
4494 | char *the_bytes; | |
4495 | struct reloc_info_generic *ri; | |
fecd2382 | 4496 | { |
355afbcd KR |
4497 | /* this is easy */ |
4498 | md_number_to_chars (the_bytes, ri->r_address, 4); | |
4499 | /* now the fun stuff */ | |
4500 | the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; | |
4501 | the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; | |
4502 | the_bytes[6] = ri->r_symbolnum & 0x0ff; | |
4503 | the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) | | |
4504 | ((ri->r_extern << 4) & 0x10)); | |
fecd2382 | 4505 | } |
355afbcd | 4506 | |
a79c6033 RP |
4507 | #endif /* comment */ |
4508 | ||
49864cfa | 4509 | #ifndef BFD_ASSEMBLER |
355afbcd KR |
4510 | void |
4511 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4512 | char *where; | |
4513 | fixS *fixP; | |
4514 | relax_addressT segment_address_in_file; | |
a79c6033 | 4515 | { |
355afbcd | 4516 | /* |
1404ef23 KR |
4517 | * In: length of relocation (or of address) in chars: 1, 2 or 4. |
4518 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
4519 | */ | |
6d27d3a2 | 4520 | |
1404ef23 | 4521 | static CONST unsigned char nbytes_r_length[] = |
355afbcd KR |
4522 | {42, 0, 1, 42, 2}; |
4523 | long r_symbolnum; | |
6d27d3a2 | 4524 | |
355afbcd | 4525 | know (fixP->fx_addsy != NULL); |
6d27d3a2 | 4526 | |
355afbcd KR |
4527 | md_number_to_chars (where, |
4528 | fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file, | |
4529 | 4); | |
6d27d3a2 | 4530 | |
355afbcd KR |
4531 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) |
4532 | ? S_GET_TYPE (fixP->fx_addsy) | |
4533 | : fixP->fx_addsy->sy_number); | |
6d27d3a2 | 4534 | |
355afbcd KR |
4535 | where[4] = (r_symbolnum >> 16) & 0x0ff; |
4536 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4537 | where[6] = r_symbolnum & 0x0ff; | |
4538 | where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) | | |
4539 | (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10)); | |
6d27d3a2 | 4540 | |
355afbcd | 4541 | return; |
49864cfa KR |
4542 | } |
4543 | #endif | |
a79c6033 | 4544 | |
fecd2382 RP |
4545 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
4546 | ||
4547 | #ifndef WORKING_DOT_WORD | |
49864cfa KR |
4548 | CONST int md_short_jump_size = 4; |
4549 | CONST int md_long_jump_size = 6; | |
fecd2382 RP |
4550 | |
4551 | void | |
355afbcd KR |
4552 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) |
4553 | char *ptr; | |
025b0302 | 4554 | addressT from_addr, to_addr; |
355afbcd KR |
4555 | fragS *frag; |
4556 | symbolS *to_symbol; | |
fecd2382 | 4557 | { |
025b0302 | 4558 | valueT offset; |
6d27d3a2 | 4559 | |
355afbcd | 4560 | offset = to_addr - (from_addr + 2); |
6d27d3a2 | 4561 | |
025b0302 ME |
4562 | md_number_to_chars (ptr, (valueT) 0x6000, 2); |
4563 | md_number_to_chars (ptr + 2, (valueT) offset, 2); | |
fecd2382 RP |
4564 | } |
4565 | ||
4566 | void | |
355afbcd KR |
4567 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) |
4568 | char *ptr; | |
025b0302 | 4569 | addressT from_addr, to_addr; |
355afbcd KR |
4570 | fragS *frag; |
4571 | symbolS *to_symbol; | |
fecd2382 | 4572 | { |
025b0302 | 4573 | valueT offset; |
355afbcd KR |
4574 | |
4575 | if (cpu_of_arch (current_architecture) < m68020) | |
4576 | { | |
4577 | offset = to_addr - S_GET_VALUE (to_symbol); | |
025b0302 ME |
4578 | md_number_to_chars (ptr, (valueT) 0x4EF9, 2); |
4579 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
bcb8dff8 KR |
4580 | fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, |
4581 | 0, NO_RELOC); | |
355afbcd KR |
4582 | } |
4583 | else | |
4584 | { | |
4585 | offset = to_addr - (from_addr + 2); | |
025b0302 ME |
4586 | md_number_to_chars (ptr, (valueT) 0x60ff, 2); |
4587 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
355afbcd | 4588 | } |
fecd2382 RP |
4589 | } |
4590 | ||
4591 | #endif | |
4592 | /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?) | |
6d27d3a2 | 4593 | |
a39116f1 RP |
4594 | 0: Everything is OK |
4595 | 10: Absolute 1:8 only | |
4596 | 20: Absolute 0:7 only | |
4597 | 30: absolute 0:15 only | |
4598 | 40: Absolute 0:31 only | |
4599 | 50: absolute 0:127 only | |
4600 | 55: absolute -64:63 only | |
4601 | 60: absolute -128:127 only | |
4602 | 70: absolute 0:4095 only | |
4603 | 80: No bignums | |
6d27d3a2 | 4604 | |
a39116f1 | 4605 | */ |
fecd2382 | 4606 | |
355afbcd KR |
4607 | static int |
4608 | get_num (exp, ok) | |
4609 | struct m68k_exp *exp; | |
4610 | int ok; | |
fecd2382 RP |
4611 | { |
4612 | #ifdef TEST2 | |
355afbcd | 4613 | long l = 0; |
6d27d3a2 | 4614 | |
355afbcd KR |
4615 | if (!exp->e_beg) |
4616 | return 0; | |
4617 | if (*exp->e_beg == '0') | |
4618 | { | |
4619 | if (exp->e_beg[1] == 'x') | |
4620 | sscanf (exp->e_beg + 2, "%x", &l); | |
4621 | else | |
4622 | sscanf (exp->e_beg + 1, "%O", &l); | |
4623 | return l; | |
4624 | } | |
4625 | return atol (exp->e_beg); | |
fecd2382 | 4626 | #else |
355afbcd KR |
4627 | char *save_in; |
4628 | char c_save; | |
49864cfa | 4629 | segT section; |
6d27d3a2 | 4630 | |
355afbcd KR |
4631 | if (!exp) |
4632 | { | |
4633 | /* Can't do anything */ | |
4634 | return 0; | |
4635 | } | |
4636 | if (!exp->e_beg || !exp->e_end) | |
4637 | { | |
49864cfa | 4638 | seg (exp) = absolute_section; |
355afbcd KR |
4639 | adds (exp) = 0; |
4640 | subs (exp) = 0; | |
4641 | offs (exp) = (ok == 10) ? 1 : 0; | |
4642 | as_warn ("Null expression defaults to %ld", offs (exp)); | |
4643 | return 0; | |
4644 | } | |
6d27d3a2 | 4645 | |
355afbcd KR |
4646 | exp->e_siz = 0; |
4647 | if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.') | |
4648 | && (exp->e_end - exp->e_beg) >= 2) | |
4649 | { | |
4650 | switch (exp->e_end[0]) | |
4651 | { | |
4652 | case 's': | |
4653 | case 'S': | |
4654 | case 'b': | |
4655 | case 'B': | |
4656 | exp->e_siz = 1; | |
4657 | exp->e_end -= 2; | |
4658 | break; | |
4659 | case 'w': | |
4660 | case 'W': | |
4661 | exp->e_siz = 2; | |
4662 | exp->e_end -= 2; | |
4663 | break; | |
4664 | case 'l': | |
4665 | case 'L': | |
4666 | exp->e_siz = 3; | |
4667 | exp->e_end -= 2; | |
4668 | break; | |
4669 | default: | |
4670 | if (exp->e_end[-1] == ':') | |
4671 | as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]); | |
4672 | break; | |
fecd2382 | 4673 | } |
355afbcd KR |
4674 | } |
4675 | c_save = exp->e_end[1]; | |
4676 | exp->e_end[1] = '\0'; | |
4677 | save_in = input_line_pointer; | |
4678 | input_line_pointer = exp->e_beg; | |
49864cfa | 4679 | section = expression (&exp->e_exp); |
bcb8dff8 KR |
4680 | seg (exp) = section; |
4681 | if (exp->e_exp.X_op == O_absent) | |
49864cfa | 4682 | { |
355afbcd | 4683 | /* Do the same thing the VAX asm does */ |
49864cfa | 4684 | seg (exp) = absolute_section; |
bcb8dff8 | 4685 | op (exp) = O_constant; |
355afbcd KR |
4686 | adds (exp) = 0; |
4687 | subs (exp) = 0; | |
4688 | offs (exp) = 0; | |
4689 | if (ok == 10) | |
4690 | { | |
4691 | as_warn ("expression out of range: defaulting to 1"); | |
4692 | offs (exp) = 1; | |
4693 | } | |
49864cfa | 4694 | } |
bcb8dff8 | 4695 | else if (exp->e_exp.X_op == O_constant) |
49864cfa | 4696 | { |
355afbcd KR |
4697 | switch (ok) |
4698 | { | |
4699 | case 10: | |
4700 | if (offs (exp) < 1 || offs (exp) > 8) | |
4701 | { | |
4702 | as_warn ("expression out of range: defaulting to 1"); | |
4703 | offs (exp) = 1; | |
4704 | } | |
4705 | break; | |
4706 | case 20: | |
4707 | if (offs (exp) < 0 || offs (exp) > 7) | |
4708 | goto outrange; | |
4709 | break; | |
4710 | case 30: | |
4711 | if (offs (exp) < 0 || offs (exp) > 15) | |
4712 | goto outrange; | |
4713 | break; | |
4714 | case 40: | |
4715 | if (offs (exp) < 0 || offs (exp) > 32) | |
4716 | goto outrange; | |
4717 | break; | |
4718 | case 50: | |
4719 | if (offs (exp) < 0 || offs (exp) > 127) | |
4720 | goto outrange; | |
4721 | break; | |
4722 | case 55: | |
4723 | if (offs (exp) < -64 || offs (exp) > 63) | |
4724 | goto outrange; | |
4725 | break; | |
4726 | case 60: | |
4727 | if (offs (exp) < -128 || offs (exp) > 127) | |
4728 | goto outrange; | |
4729 | break; | |
4730 | case 70: | |
4731 | if (offs (exp) < 0 || offs (exp) > 4095) | |
4732 | { | |
4733 | outrange: | |
4734 | as_warn ("expression out of range: defaulting to 0"); | |
4735 | offs (exp) = 0; | |
4736 | } | |
4737 | break; | |
fecd2382 | 4738 | default: |
355afbcd KR |
4739 | break; |
4740 | } | |
49864cfa | 4741 | } |
bcb8dff8 | 4742 | else if (exp->e_exp.X_op == O_big) |
49864cfa | 4743 | { |
bcb8dff8 | 4744 | if (offs (exp) <= 0 /* flonum */ |
355afbcd KR |
4745 | && (ok == 80 /* no bignums */ |
4746 | || (ok > 10 /* small-int ranges including 0 ok */ | |
1404ef23 KR |
4747 | /* If we have a flonum zero, a zero integer should |
4748 | do as well (e.g., in moveq). */ | |
355afbcd KR |
4749 | && generic_floating_point_number.exponent == 0 |
4750 | && generic_floating_point_number.low[0] == 0))) | |
4751 | { | |
4752 | /* HACK! Turn it into a long */ | |
4753 | LITTLENUM_TYPE words[6]; | |
4754 | ||
4755 | gen_to_words (words, 2, 8L); /* These numbers are magic! */ | |
49864cfa | 4756 | seg (exp) = absolute_section; |
bcb8dff8 | 4757 | op (exp) = O_constant; |
355afbcd KR |
4758 | adds (exp) = 0; |
4759 | subs (exp) = 0; | |
4760 | offs (exp) = words[1] | (words[0] << 16); | |
4761 | } | |
4762 | else if (ok != 0) | |
4763 | { | |
49864cfa | 4764 | seg (exp) = absolute_section; |
bcb8dff8 | 4765 | op (exp) = O_constant; |
355afbcd KR |
4766 | adds (exp) = 0; |
4767 | subs (exp) = 0; | |
4768 | offs (exp) = (ok == 10) ? 1 : 0; | |
4769 | as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp)); | |
4770 | } | |
49864cfa KR |
4771 | } |
4772 | else | |
4773 | { | |
355afbcd KR |
4774 | if (ok >= 10 && ok <= 70) |
4775 | { | |
49864cfa | 4776 | seg (exp) = absolute_section; |
bcb8dff8 | 4777 | op (exp) = O_constant; |
355afbcd KR |
4778 | adds (exp) = 0; |
4779 | subs (exp) = 0; | |
4780 | offs (exp) = (ok == 10) ? 1 : 0; | |
4781 | as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp)); | |
4782 | } | |
355afbcd | 4783 | } |
49864cfa | 4784 | |
355afbcd KR |
4785 | if (input_line_pointer != exp->e_end + 1) |
4786 | as_bad ("Ignoring junk after expression"); | |
4787 | exp->e_end[1] = c_save; | |
4788 | input_line_pointer = save_in; | |
4789 | if (exp->e_siz) | |
4790 | { | |
4791 | switch (exp->e_siz) | |
4792 | { | |
4793 | case 1: | |
4794 | if (!isbyte (offs (exp))) | |
4795 | as_warn ("expression doesn't fit in BYTE"); | |
4796 | break; | |
4797 | case 2: | |
4798 | if (!isword (offs (exp))) | |
4799 | as_warn ("expression doesn't fit in WORD"); | |
4800 | break; | |
a39116f1 | 4801 | } |
355afbcd KR |
4802 | } |
4803 | return offs (exp); | |
fecd2382 | 4804 | #endif |
49864cfa | 4805 | } |
fecd2382 RP |
4806 | |
4807 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
355afbcd | 4808 | void demand_empty_rest_of_line (); /* Hate those extra verbose names */ |
fecd2382 | 4809 | |
355afbcd | 4810 | static void |
bcb8dff8 KR |
4811 | s_data1 (ignore) |
4812 | int ignore; | |
355afbcd | 4813 | { |
bcb8dff8 | 4814 | subseg_set (data_section, 1); |
355afbcd | 4815 | demand_empty_rest_of_line (); |
49864cfa | 4816 | } |
fecd2382 | 4817 | |
355afbcd | 4818 | static void |
bcb8dff8 KR |
4819 | s_data2 (ignore) |
4820 | int ignore; | |
355afbcd | 4821 | { |
bcb8dff8 | 4822 | subseg_set (data_section, 2); |
355afbcd | 4823 | demand_empty_rest_of_line (); |
49864cfa | 4824 | } |
fecd2382 | 4825 | |
355afbcd | 4826 | static void |
bcb8dff8 KR |
4827 | s_bss (ignore) |
4828 | int ignore; | |
a1765cf0 | 4829 | { |
355afbcd | 4830 | /* We don't support putting frags in the BSS segment, we fake it |
49864cfa | 4831 | by marking in_bss, then looking at s_skip for clues. */ |
a1765cf0 | 4832 | |
bcb8dff8 | 4833 | subseg_set (bss_section, 0); |
355afbcd | 4834 | demand_empty_rest_of_line (); |
49864cfa | 4835 | } |
6d27d3a2 | 4836 | |
355afbcd | 4837 | static void |
bcb8dff8 KR |
4838 | s_even (ignore) |
4839 | int ignore; | |
355afbcd KR |
4840 | { |
4841 | register int temp; | |
4842 | register long temp_fill; | |
4843 | ||
4844 | temp = 1; /* JF should be 2? */ | |
4845 | temp_fill = get_absolute_expression (); | |
4846 | if (!need_pass_2) /* Never make frag if expect extra pass. */ | |
4847 | frag_align (temp, (int) temp_fill); | |
4848 | demand_empty_rest_of_line (); | |
49864cfa | 4849 | } |
355afbcd KR |
4850 | |
4851 | static void | |
bcb8dff8 KR |
4852 | s_proc (ignore) |
4853 | int ignore; | |
355afbcd KR |
4854 | { |
4855 | demand_empty_rest_of_line (); | |
49864cfa | 4856 | } |
fecd2382 RP |
4857 | |
4858 | /* s_space is defined in read.c .skip is simply an alias to it. */ | |
4859 | ||
7c15cbe8 RP |
4860 | /* |
4861 | * md_parse_option | |
4862 | * Invocation line includes a switch not recognized by the base assembler. | |
4863 | * See if it's a processor-specific option. These are: | |
4864 | * | |
4865 | * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040 | |
4866 | * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851 | |
4867 | * Select the architecture. Instructions or features not | |
4868 | * supported by the selected architecture cause fatal | |
4869 | * errors. More than one may be specified. The default is | |
4870 | * -m68020 -m68851 -m68881. Note that -m68008 is a synonym | |
4871 | * for -m68000, and -m68882 is a synonym for -m68881. | |
df3768fb KR |
4872 | * -[A]m[c]no-68851, -[A]m[c]no-68881 |
4873 | * Don't accept 688?1 instructions. (The "c" is kind of silly, | |
4874 | * so don't use or document it, but that's the way the parsing | |
4875 | * works). | |
7c15cbe8 | 4876 | * |
b80d39a0 KR |
4877 | * -k Ignored for now. (Sun 3 only. Indicates PIC.) |
4878 | * | |
a39116f1 RP |
4879 | * MAYBE_FLOAT_TOO is defined below so that specifying a processor type |
4880 | * (e.g. m68020) also requests that float instructions be included. This | |
4881 | * is the default setup, mostly to avoid hassling users. A better | |
4882 | * rearrangement of this structure would be to add an option to DENY | |
4883 | * floating point opcodes, for people who want to really know there's none | |
4884 | * of that funny floaty stuff going on. FIXME-later. | |
7c15cbe8 | 4885 | */ |
a39116f1 | 4886 | #ifndef MAYBE_FLOAT_TOO |
355afbcd | 4887 | #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */ |
a39116f1 | 4888 | #endif |
7c15cbe8 | 4889 | |
355afbcd KR |
4890 | int |
4891 | md_parse_option (argP, cntP, vecP) | |
4892 | char **argP; | |
4893 | int *cntP; | |
4894 | char ***vecP; | |
fecd2382 | 4895 | { |
355afbcd KR |
4896 | switch (**argP) |
4897 | { | |
4898 | case 'l': /* -l means keep external to 2 bit offset | |
e284846a | 4899 | rather than 16 bit one */ |
355afbcd | 4900 | break; |
6d27d3a2 | 4901 | |
e284846a KR |
4902 | case 'S': /* -S means that jbsr's always turn into |
4903 | jsr's. */ | |
355afbcd | 4904 | break; |
6d27d3a2 | 4905 | |
b80d39a0 KR |
4906 | #ifdef TE_SUN3 |
4907 | case 'k': | |
4908 | flag_want_pic = 1; | |
4909 | break; | |
4910 | #endif | |
4911 | ||
355afbcd KR |
4912 | case 'A': |
4913 | (*argP)++; | |
4914 | /* intentional fall-through */ | |
4915 | case 'm': | |
4916 | (*argP)++; | |
4917 | ||
4918 | if (**argP == 'c') | |
4919 | { | |
4920 | (*argP)++; | |
4921 | } /* allow an optional "c" */ | |
4922 | ||
4923 | if (!strcmp (*argP, "68000") | |
e284846a KR |
4924 | || !strcmp (*argP, "68008") |
4925 | || !strcmp (*argP, "68302")) | |
355afbcd KR |
4926 | { |
4927 | current_architecture |= m68000; | |
4928 | } | |
4929 | else if (!strcmp (*argP, "68010")) | |
4930 | { | |
fecd2382 | 4931 | #ifdef TE_SUN |
355afbcd | 4932 | omagic = 1 << 16 | OMAGIC; |
fecd2382 | 4933 | #endif |
355afbcd | 4934 | current_architecture |= m68010; |
355afbcd KR |
4935 | } |
4936 | else if (!strcmp (*argP, "68020")) | |
4937 | { | |
4938 | current_architecture |= m68020 | MAYBE_FLOAT_TOO; | |
355afbcd KR |
4939 | } |
4940 | else if (!strcmp (*argP, "68030")) | |
4941 | { | |
4942 | current_architecture |= m68030 | MAYBE_FLOAT_TOO; | |
355afbcd KR |
4943 | } |
4944 | else if (!strcmp (*argP, "68040")) | |
4945 | { | |
4946 | current_architecture |= m68040 | MAYBE_FLOAT_TOO; | |
355afbcd | 4947 | } |
e284846a | 4948 | #ifndef NO_68881 |
355afbcd KR |
4949 | else if (!strcmp (*argP, "68881")) |
4950 | { | |
4951 | current_architecture |= m68881; | |
355afbcd KR |
4952 | } |
4953 | else if (!strcmp (*argP, "68882")) | |
4954 | { | |
4955 | current_architecture |= m68882; | |
355afbcd | 4956 | } |
e284846a KR |
4957 | #endif /* NO_68881 */ |
4958 | /* Even if we aren't configured to support the processor, | |
4959 | it should still be possible to assert that the user | |
4960 | doesn't have it... */ | |
355afbcd KR |
4961 | else if (!strcmp (*argP, "no-68881") |
4962 | || !strcmp (*argP, "no-68882")) | |
4963 | { | |
4964 | no_68881 = 1; | |
355afbcd | 4965 | } |
e284846a | 4966 | #ifndef NO_68851 |
355afbcd KR |
4967 | else if (!strcmp (*argP, "68851")) |
4968 | { | |
4969 | current_architecture |= m68851; | |
355afbcd | 4970 | } |
e284846a | 4971 | #endif /* NO_68851 */ |
355afbcd KR |
4972 | else if (!strcmp (*argP, "no-68851")) |
4973 | { | |
4974 | no_68851 = 1; | |
4975 | } | |
e284846a KR |
4976 | else if (!strcmp (*argP, "pu32") /* "cpu32" minus 'c' */ |
4977 | || !strcmp (*argP, "68331") | |
4978 | || !strcmp (*argP, "68332") | |
4979 | || !strcmp (*argP, "68333") | |
4980 | || !strcmp (*argP, "68340")) | |
4981 | { | |
355afbcd KR |
4982 | current_architecture |= cpu32; |
4983 | } | |
4984 | else | |
4985 | { | |
4986 | as_warn ("Unknown architecture, \"%s\". option ignored", *argP); | |
4987 | } /* switch on architecture */ | |
6d27d3a2 | 4988 | |
355afbcd KR |
4989 | while (**argP) |
4990 | (*argP)++; | |
6d27d3a2 | 4991 | |
355afbcd | 4992 | break; |
6d27d3a2 | 4993 | |
355afbcd KR |
4994 | case 'p': |
4995 | if (!strcmp (*argP, "pic")) | |
4996 | { | |
4997 | (*argP) += 3; | |
4998 | break; /* -pic, Position Independent Code */ | |
f8701a3f | 4999 | } |
355afbcd KR |
5000 | else |
5001 | { | |
e284846a | 5002 | return 0; |
355afbcd KR |
5003 | } /* pic or not */ |
5004 | ||
5005 | default: | |
5006 | return 0; | |
5007 | } | |
5008 | return 1; | |
fecd2382 RP |
5009 | } |
5010 | ||
5011 | ||
5012 | #ifdef TEST2 | |
5013 | ||
5014 | /* TEST2: Test md_assemble() */ | |
5015 | /* Warning, this routine probably doesn't work anymore */ | |
5016 | ||
355afbcd | 5017 | main () |
fecd2382 | 5018 | { |
355afbcd KR |
5019 | struct m68k_it the_ins; |
5020 | char buf[120]; | |
5021 | char *cp; | |
5022 | int n; | |
5023 | ||
5024 | m68k_ip_begin (); | |
5025 | for (;;) | |
5026 | { | |
5027 | if (!gets (buf) || !*buf) | |
5028 | break; | |
5029 | if (buf[0] == '|' || buf[1] == '.') | |
5030 | continue; | |
5031 | for (cp = buf; *cp; cp++) | |
5032 | if (*cp == '\t') | |
5033 | *cp = ' '; | |
5034 | if (is_label (buf)) | |
5035 | continue; | |
5036 | memset (&the_ins, '\0', sizeof (the_ins)); | |
5037 | m68k_ip (&the_ins, buf); | |
5038 | if (the_ins.error) | |
5039 | { | |
5040 | printf ("Error %s in %s\n", the_ins.error, buf); | |
5041 | } | |
5042 | else | |
5043 | { | |
5044 | printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args); | |
5045 | for (n = 0; n < the_ins.numo; n++) | |
5046 | printf (" 0x%x", the_ins.opcode[n] & 0xffff); | |
5047 | printf (" "); | |
5048 | print_the_insn (&the_ins.opcode[0], stdout); | |
5049 | (void) putchar ('\n'); | |
5050 | } | |
5051 | for (n = 0; n < strlen (the_ins.args) / 2; n++) | |
5052 | { | |
5053 | if (the_ins.operands[n].error) | |
5054 | { | |
5055 | printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); | |
5056 | continue; | |
5057 | } | |
5058 | printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg); | |
5059 | if (the_ins.operands[n].b_const) | |
5060 | printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const); | |
5061 | printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul); | |
5062 | if (the_ins.operands[n].b_iadd) | |
5063 | printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd); | |
5064 | (void) putchar ('\n'); | |
a39116f1 | 5065 | } |
355afbcd KR |
5066 | } |
5067 | m68k_ip_end (); | |
5068 | return 0; | |
fecd2382 RP |
5069 | } |
5070 | ||
355afbcd KR |
5071 | is_label (str) |
5072 | char *str; | |
fecd2382 | 5073 | { |
355afbcd KR |
5074 | while (*str == ' ') |
5075 | str++; | |
5076 | while (*str && *str != ' ') | |
5077 | str++; | |
5078 | if (str[-1] == ':' || str[1] == '=') | |
5079 | return 1; | |
5080 | return 0; | |
fecd2382 RP |
5081 | } |
5082 | ||
5083 | #endif | |
5084 | ||
5085 | /* Possible states for relaxation: | |
6d27d3a2 | 5086 | |
a39116f1 RP |
5087 | 0 0 branch offset byte (bra, etc) |
5088 | 0 1 word | |
5089 | 0 2 long | |
6d27d3a2 | 5090 | |
a39116f1 RP |
5091 | 1 0 indexed offsets byte a0@(32,d4:w:1) etc |
5092 | 1 1 word | |
5093 | 1 2 long | |
6d27d3a2 | 5094 | |
a39116f1 RP |
5095 | 2 0 two-offset index word-word a0@(32,d4)@(45) etc |
5096 | 2 1 word-long | |
5097 | 2 2 long-word | |
5098 | 2 3 long-long | |
6d27d3a2 | 5099 | |
a39116f1 | 5100 | */ |
fecd2382 | 5101 | |
fecd2382 RP |
5102 | /* We have no need to default values of symbols. */ |
5103 | ||
5104 | /* ARGSUSED */ | |
5105 | symbolS * | |
355afbcd KR |
5106 | md_undefined_symbol (name) |
5107 | char *name; | |
fecd2382 | 5108 | { |
355afbcd | 5109 | return 0; |
fecd2382 RP |
5110 | } |
5111 | ||
6d27d3a2 | 5112 | /* Parse an operand that is machine-specific. |
fecd2382 RP |
5113 | We just return without modifying the expression if we have nothing |
5114 | to do. */ | |
5115 | ||
5116 | /* ARGSUSED */ | |
5117 | void | |
355afbcd KR |
5118 | md_operand (expressionP) |
5119 | expressionS *expressionP; | |
fecd2382 RP |
5120 | { |
5121 | } | |
5122 | ||
5123 | /* Round up a section size to the appropriate boundary. */ | |
025b0302 | 5124 | valueT |
355afbcd KR |
5125 | md_section_align (segment, size) |
5126 | segT segment; | |
025b0302 | 5127 | valueT size; |
fecd2382 | 5128 | { |
355afbcd | 5129 | return size; /* Byte alignment is fine */ |
fecd2382 RP |
5130 | } |
5131 | ||
5132 | /* Exactly what point is a PC-relative offset relative TO? | |
5133 | On the 68k, they're relative to the address of the offset, plus | |
5134 | its size. (??? Is this right? FIXME-SOON!) */ | |
5135 | long | |
355afbcd KR |
5136 | md_pcrel_from (fixP) |
5137 | fixS *fixP; | |
fecd2382 | 5138 | { |
355afbcd | 5139 | return (fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address); |
fecd2382 RP |
5140 | } |
5141 | ||
49864cfa | 5142 | #ifndef BFD_ASSEMBLER |
355afbcd | 5143 | void |
3ad9ec6a ILT |
5144 | tc_coff_symbol_emit_hook () |
5145 | { | |
5146 | } | |
5147 | ||
355afbcd KR |
5148 | int |
5149 | tc_coff_sizemachdep (frag) | |
5150 | fragS *frag; | |
3ad9ec6a | 5151 | { |
355afbcd KR |
5152 | switch (frag->fr_subtype & 0x3) |
5153 | { | |
5154 | case BYTE: | |
5155 | return 1; | |
5156 | case SHORT: | |
5157 | return 2; | |
5158 | case LONG: | |
5159 | return 4; | |
5160 | default: | |
5161 | abort (); | |
5162 | } | |
3ad9ec6a | 5163 | } |
49864cfa | 5164 | #endif |
355afbcd | 5165 | |
fecd2382 | 5166 | /* end of tc-m68k.c */ |