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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
87975d2a 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5a49b8ac 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
c04898f8 28#include "dw2gencfi.h"
252b5132
RH		 29
30#include "opcode/m68k.h"
31#include "m68k-parse.h"
32
0d96863f
CM		 33#if defined (OBJ_ELF)
34#include "elf/m68k.h"
35#endif
36
31302357
AS		 37#ifdef M68KCOFF
38#include "obj-coff.h"
39#endif
40
cf869cce
NC		 41#ifdef OBJ_ELF
42static void m68k_elf_cons (int);
43#endif
44
252b5132
RH		 45/* This string holds the chars that always start a comment. If the
46 pre-processor is disabled, these aren't very useful. The macro
47 tc_comment_chars points to this. We use this, rather than the
48 usual comment_chars, so that the --bitwise-or option will work. */
49#if defined (TE_SVR4) || defined (TE_DELTA)
50const char *m68k_comment_chars = "|#";
51#else
52const char *m68k_comment_chars = "|";
53#endif
54
55/* This array holds the chars that only start a comment at the beginning of
56 a line. If the line seems to have the form '# 123 filename'
57 .line and .file directives will appear in the pre-processed output */
58/* Note that input_file.c hand checks for '#' at the beginning of the
59 first line of the input file. This is because the compiler outputs
92774660
KH		 60 #NO_APP at the beginning of its output. */
61/* Also note that comments like this one will always work. */
252b5132
RH		 62const char line_comment_chars[] = "#*";
63
63a0b638 64const char line_separator_chars[] = ";";
252b5132 65
36759679 66/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 67const char EXP_CHARS[] = "eE";
252b5132
RH		 68
69/* Chars that mean this number is a floating point constant, as
70 in "0f12.456" or "0d1.2345e12". */
71
5a38dc70 72const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 73
74/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
75 changed in read.c . Ideally it shouldn't have to know about it at all,
76 but nothing is ideal around here. */
77
252b5132
RH		 78/* Are we trying to generate PIC code? If so, absolute references
79 ought to be made into linkage table references or pc-relative
92774660 80 references. Not implemented. For ELF there are other means
252b5132
RH		 81 to denote pic relocations. */
82int flag_want_pic;
83
36759679
NC		 84static int flag_short_refs; /* -l option. */
85static int flag_long_jumps; /* -S option. */
28e7409f 86static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 87
88#ifdef REGISTER_PREFIX_OPTIONAL
89int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
90#else
91int flag_reg_prefix_optional;
92#endif
93
94/* Whether --register-prefix-optional was used on the command line. */
95static int reg_prefix_optional_seen;
96
97/* The floating point coprocessor to use by default. */
98static enum m68k_register m68k_float_copnum = COP1;
99
100/* If this is non-zero, then references to number(%pc) will be taken
101 to refer to number, rather than to %pc + number. */
102static int m68k_abspcadd;
103
104/* If this is non-zero, then the quick forms of the move, add, and sub
105 instructions are used when possible. */
106static int m68k_quick = 1;
107
108/* If this is non-zero, then if the size is not specified for a base
109 or outer displacement, the assembler assumes that the size should
110 be 32 bits. */
111static int m68k_rel32 = 1;
112
113/* This is non-zero if m68k_rel32 was set from the command line. */
114static int m68k_rel32_from_cmdline;
115
116/* The default width to use for an index register when using a base
117 displacement. */
118static enum m68k_size m68k_index_width_default = SIZE_LONG;
119
120/* We want to warn if any text labels are misaligned. In order to get
121 the right line number, we need to record the line number for each
122 label. */
252b5132
RH		 123struct label_line
124{
125 struct label_line *next;
126 symbolS *label;
127 char *file;
128 unsigned int line;
129 int text;
130};
131
132/* The list of labels. */
133
134static struct label_line *labels;
135
136/* The current label. */
137
138static struct label_line *current_label;
139
60fed2d3
NC		 140/* Pointer to list holding the opcodes sorted by name. */
141static struct m68k_opcode const ** m68k_sorted_opcodes;
142
36759679
NC		 143/* Its an arbitrary name: This means I don't approve of it.
144 See flames below. */
252b5132
RH		 145static struct obstack robyn;
146
252b5132
RH		 147struct m68k_incant
148 {
149 const char *m_operands;
150 unsigned long m_opcode;
151 short m_opnum;
152 short m_codenum;
153 int m_arch;
154 struct m68k_incant *m_next;
155 };
156
157#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
158#define gettwo(x) (((x)->m_opcode)&0xffff)
159
2da12c60
NS		 160static const enum m68k_register m68000_ctrl[] = { 0 };
161static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 162 SFC, DFC, USP, VBR,
163 0
164};
2da12c60 165static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 166 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
167 0
168};
2da12c60 169static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
171 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
172 0
173};
2da12c60 174static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 175 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
176 USP, VBR, URP, SRP, PCR,
177 0
178};
2da12c60 179static const enum m68k_register mcf_ctrl[] = {
3e602632 180 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 181 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
182 0
183};
87298967
NS		 184static const enum m68k_register mcf51_ctrl[] = {
185 VBR, CPUCR,
f75192f2
KH		 186 0
187};
78336706 188static const enum m68k_register mcf5206_ctrl[] = {
0d999f33 189 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 190 0
191};
2da12c60 192static const enum m68k_register mcf5208_ctrl[] = {
78336706 193 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 194 0
195};
96e0bbcc 196static const enum m68k_register mcf5210a_ctrl[] = {
78336706 197 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 198 0
199};
2da12c60 200static const enum m68k_register mcf5213_ctrl[] = {
78336706 201 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 202 0
203};
2da12c60 204static const enum m68k_register mcf5216_ctrl[] = {
78336706 205 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 206 0
207};
46203761
MK		 208static const enum m68k_register mcf5221x_ctrl[] = {
209 VBR, FLASHBAR, RAMBAR, RAMBAR1,
210 0
211};
d5be9593 212static const enum m68k_register mcf52223_ctrl[] = {
0d999f33 213 VBR, FLASHBAR, RAMBAR, RAMBAR1,
d5be9593
NS		 214 0
215};
96e0bbcc 216static const enum m68k_register mcf52235_ctrl[] = {
b345c8c2 217 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 218 0
219};
220static const enum m68k_register mcf5225_ctrl[] = {
78336706 221 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 222 0
223};
87298967
NS		 224static const enum m68k_register mcf52259_ctrl[] = {
225 VBR, FLASHBAR, RAMBAR, RAMBAR1,
226 0
227};
228static const enum m68k_register mcf52277_ctrl[] = {
229 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
230 0
231};
2da12c60 232static const enum m68k_register mcf5235_ctrl[] = {
78336706 233 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 234 0
235};
2da12c60 236static const enum m68k_register mcf5249_ctrl[] = {
78336706 237 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 238 0
239};
2da12c60
NS		 240static const enum m68k_register mcf5250_ctrl[] = {
241 VBR,
242 0
243};
d5be9593 244static const enum m68k_register mcf5253_ctrl[] = {
def8fc92 245 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
d5be9593
NS		 246 0
247};
2da12c60 248static const enum m68k_register mcf5271_ctrl[] = {
78336706 249 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 250 0
251};
252static const enum m68k_register mcf5272_ctrl[] = {
78336706 253 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 254 0
255};
256static const enum m68k_register mcf5275_ctrl[] = {
78336706 257 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 258 0
259};
260static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 261 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
262 0
263};
87298967 264static const enum m68k_register mcf53017_ctrl[] = {
b345c8c2 265 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
87298967
NS		 266 0
267};
78336706 268static const enum m68k_register mcf5307_ctrl[] = {
87298967 269 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 270 0
271};
272static const enum m68k_register mcf5329_ctrl[] = {
78336706 273 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 274 0
275};
276static const enum m68k_register mcf5373_ctrl[] = {
78336706 277 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 278 0
279};
280static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
283 MBAR, SECMBAR,
284 MPCR /* Multiprocessor Control register */,
285 EDRAMBAR /* Embedded DRAM Base Address Register */,
286 /* Permutation control registers. */
3e602632
NC		 287 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
288 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 289 /* Legacy names */
290 TC /* ASID */, BUSCR /* MMUBAR */,
291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
292 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 293 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 294 0
295};
def8fc92
KH		 296static const enum m68k_register mcf5407_ctrl[] = {
297 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
298 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
299 /* Legacy names */
300 TC /* ASID */,
301 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
302 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
303 0
304};
0d999f33
MK		 305static const enum m68k_register mcf54418_ctrl[] = {
306 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
307 VBR, PC, RAMBAR1,
308 /* Legacy names */
309 TC /* ASID */, BUSCR /* MMUBAR */,
310 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
311 RAMBAR /* RAMBAR1 */,
312 0
313};
9a2e615a
NS		 314static const enum m68k_register mcf54455_ctrl[] = {
315 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
0d999f33 316 VBR, PC, RAMBAR1,
9a2e615a
NS		 317 /* Legacy names */
318 TC /* ASID */, BUSCR /* MMUBAR */,
319 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
0d999f33 320 RAMBAR /* RAMBAR1 */,
9a2e615a
NS		 321 0
322};
a8e24a56
NS		 323static const enum m68k_register mcf5475_ctrl[] = {
324 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
325 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
326 /* Legacy names */
327 TC /* ASID */, BUSCR /* MMUBAR */,
328 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 329 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 330 0
331};
332static const enum m68k_register mcf5485_ctrl[] = {
333 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
334 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
335 /* Legacy names */
336 TC /* ASID */, BUSCR /* MMUBAR */,
337 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 338 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 339 0
340};
f7ec513b 341static const enum m68k_register fido_ctrl[] = {
d0fa1372 342 SFC, DFC, USP, VBR, CAC, MBO,
f7ec513b
KH		 343 0
344};
2da12c60 345#define cpu32_ctrl m68010_ctrl
252b5132
RH		 346
347static const enum m68k_register *control_regs;
348
36759679 349/* Internal form of a 68020 instruction. */
252b5132
RH		 350struct m68k_it
351{
352 const char *error;
36759679 353 const char *args; /* List of opcode info. */
252b5132
RH		 354 int numargs;
355
36759679 356 int numo; /* Number of shorts in opcode. */
252b5132
RH		 357 short opcode[11];
358
359 struct m68k_op operands[6];
360
36759679 361 int nexp; /* Number of exprs in use. */
252b5132
RH		 362 struct m68k_exp exprs[4];
363
36759679 364 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 365 struct
366 {
36759679 367 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 368 symbolS *fadd;
369 offsetT foff;
370 int fragty;
371 }
372 fragb[4];
373
36759679 374 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 375 struct
376 {
377 int n;
378 expressionS exp;
379 char wid;
380 char pcrel;
381 /* In a pc relative address the difference between the address
382 of the offset and the address that the offset is relative
383 to. This depends on the addressing mode. Basically this
384 is the value to put in the offset field to address the
385 first byte of the offset, without regarding the special
386 significance of some values (in the branch instruction, for
387 example). */
388 int pcrel_fix;
389#ifdef OBJ_ELF
390 /* Whether this expression needs special pic relocation, and if
391 so, which. */
392 enum pic_relocation pic_reloc;
393#endif
394 }
36759679 395 reloc[5]; /* Five is enough??? */
252b5132
RH		 396};
397
9840d27e 398#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 399#define float_of_arch(x) ((x) & mfloat)
400#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 401#define arch_coldfire_p(x) ((x) & mcfisa_a)
402#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 403
36759679 404/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 405#define HAVE_LONG_DISP(x) \
406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
407#define HAVE_LONG_CALL(x) \
408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
409#define HAVE_LONG_COND(x) \
410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
411#define HAVE_LONG_BRANCH(x) \
412 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
cac27205 413#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
252b5132 414
36759679 415static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 416
417#define op(ex) ((ex)->exp.X_op)
418#define adds(ex) ((ex)->exp.X_add_symbol)
419#define subs(ex) ((ex)->exp.X_op_symbol)
420#define offs(ex) ((ex)->exp.X_add_number)
421
36759679 422/* Macros for adding things to the m68k_it struct. */
31302357 423#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 424
36759679
NC		 425/* Like addword, but goes BEFORE general operands. */
426
252b5132 427static void
31302357 428insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 429{
430 int z;
07726851 431 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 432 the_ins.opcode[z] = the_ins.opcode[z - 1];
433 for (z = 0; z < the_ins.nrel; z++)
434 the_ins.reloc[z].n += 2;
252b5132
RH		 435 for (z = 0; z < the_ins.nfrag; z++)
436 the_ins.fragb[z].fragoff++;
8a104df9 437 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 438 the_ins.numo++;
439}
440
441/* The numo+1 kludge is so we can hit the low order byte of the prev word.
442 Blecch. */
443static void
31302357 444add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 445{
31302357
AS		 446 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
447 ? the_ins.numo * 2 - 1
448 : (width == 'b'
449 ? the_ins.numo * 2 + 1
450 : the_ins.numo * 2));
252b5132
RH		 451 the_ins.reloc[the_ins.nrel].exp = exp->exp;
452 the_ins.reloc[the_ins.nrel].wid = width;
453 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
454#ifdef OBJ_ELF
455 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
456#endif
457 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
458}
459
460/* Cause an extra frag to be generated here, inserting up to 10 bytes
461 (that value is chosen in the frag_var call in md_assemble). TYPE
462 is the subtype of the frag to be generated; its primary type is
463 rs_machine_dependent.
464
465 The TYPE parameter is also used by md_convert_frag_1 and
466 md_estimate_size_before_relax. The appropriate type of fixup will
467 be emitted by md_convert_frag_1.
468
469 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
470static void
31302357 471add_frag (symbolS *add, offsetT off, int type)
252b5132 472{
8a104df9
KH		 473 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
474 the_ins.fragb[the_ins.nfrag].fadd = add;
475 the_ins.fragb[the_ins.nfrag].foff = off;
476 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 477}
478
479#define isvar(ex) \
480 (op (ex) != O_constant && op (ex) != O_big)
481
31302357
AS		 482static char *crack_operand (char *str, struct m68k_op *opP);
483static int get_num (struct m68k_exp *exp, int ok);
484static int reverse_16_bits (int in);
485static int reverse_8_bits (int in);
486static void install_gen_operand (int mode, int val);
487static void install_operand (int mode, int val);
488static void s_bss (int);
489static void s_data1 (int);
490static void s_data2 (int);
491static void s_even (int);
492static void s_proc (int);
493static void s_chip (int);
494static void s_fopt (int);
495static void s_opt (int);
496static void s_reg (int);
497static void s_restore (int);
498static void s_save (int);
499static void s_mri_if (int);
500static void s_mri_else (int);
501static void s_mri_endi (int);
502static void s_mri_break (int);
503static void s_mri_next (int);
504static void s_mri_for (int);
505static void s_mri_endf (int);
506static void s_mri_repeat (int);
507static void s_mri_until (int);
508static void s_mri_while (int);
509static void s_mri_endw (int);
266abb8f
NS		 510static void s_m68k_cpu (int);
511static void s_m68k_arch (int);
512
513struct m68k_cpu
514{
515 unsigned long arch; /* Architecture features. */
2da12c60 516 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 517 const char *name; /* Name */
0b2e31dc
NS		 518 int alias; /* Alias for a cannonical name. If 1, then
519 succeeds canonical name, if -1 then
520 succeeds canonical name, if <-1 ||>1 this is a
521 deprecated name, and the next/previous name
522 should be used. */
266abb8f 523};
252b5132 524
266abb8f
NS		 525/* We hold flags for features explicitly enabled and explicitly
526 disabled. */
252b5132 527static int current_architecture;
266abb8f 528static int not_current_architecture;
266abb8f
NS		 529static const struct m68k_cpu *selected_arch;
530static const struct m68k_cpu *selected_cpu;
531static int initialized;
252b5132 532
266abb8f
NS		 533/* Architecture models. */
534static const struct m68k_cpu m68k_archs[] =
535{
2da12c60
NS		 536 {m68000, m68000_ctrl, "68000", 0},
537 {m68010, m68010_ctrl, "68010", 0},
538 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
539 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
540 {m68040, m68040_ctrl, "68040", 0},
541 {m68060, m68060_ctrl, "68060", 0},
542 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 543 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 544 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
545 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
546 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 547 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 548 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
549 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 550 {0,0,NULL, 0}
551};
252b5132 552
87298967
NS		 553/* For -mno-mac we want to turn off all types of mac. */
554static const unsigned no_mac = mcfmac | mcfemac;
555
0b2e31dc
NS		 556/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
557 for either. */
266abb8f
NS		 558static const struct m68k_cpu m68k_extensions[] =
559{
2da12c60
NS		 560 {m68851, NULL, "68851", -1},
561 {m68881, NULL, "68881", -1},
562 {m68881, NULL, "68882", -1},
cf869cce 563
2da12c60 564 {cfloat|m68881, NULL, "float", 0},
cf869cce 565
2da12c60
NS		 566 {mcfhwdiv, NULL, "div", 1},
567 {mcfusp, NULL, "usp", 1},
87298967 568 {mcfmac, (void *)&no_mac, "mac", 1},
2da12c60 569 {mcfemac, NULL, "emac", 1},
cf869cce 570
2da12c60 571 {0,NULL,NULL, 0}
266abb8f
NS		 572};
573
574/* Processor list */
575static const struct m68k_cpu m68k_cpus[] =
576{
2da12c60
NS		 577 {m68000, m68000_ctrl, "68000", 0},
578 {m68000, m68000_ctrl, "68ec000", 1},
579 {m68000, m68000_ctrl, "68hc000", 1},
580 {m68000, m68000_ctrl, "68hc001", 1},
581 {m68000, m68000_ctrl, "68008", 1},
582 {m68000, m68000_ctrl, "68302", 1},
583 {m68000, m68000_ctrl, "68306", 1},
584 {m68000, m68000_ctrl, "68307", 1},
585 {m68000, m68000_ctrl, "68322", 1},
586 {m68000, m68000_ctrl, "68356", 1},
587 {m68010, m68010_ctrl, "68010", 0},
588 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
589 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
590 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
591 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
592 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
593 {m68040, m68040_ctrl, "68040", 0},
594 {m68040, m68040_ctrl, "68ec040", 1},
595 {m68060, m68060_ctrl, "68060", 0},
596 {m68060, m68060_ctrl, "68ec060", 1},
cf869cce 597
2da12c60
NS		 598 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
599 {cpu32|m68881, cpu32_ctrl, "68330", 1},
600 {cpu32|m68881, cpu32_ctrl, "68331", 1},
601 {cpu32|m68881, cpu32_ctrl, "68332", 1},
602 {cpu32|m68881, cpu32_ctrl, "68333", 1},
603 {cpu32|m68881, cpu32_ctrl, "68334", 1},
604 {cpu32|m68881, cpu32_ctrl, "68336", 1},
605 {cpu32|m68881, cpu32_ctrl, "68340", 1},
606 {cpu32|m68881, cpu32_ctrl, "68341", 1},
607 {cpu32|m68881, cpu32_ctrl, "68349", 1},
608 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2 609
87298967
NS		 610 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
611 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
c1c30076 612 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1},
87298967
NS		 613 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
614 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
c1c30076
NS		 615 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1},
616 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1},
617 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1},
87298967 618 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
c1c30076 619 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1},
87298967 620 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
c1c30076 621 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1},
cf869cce 622
2da12c60
NS		 623 {mcfisa_a, mcf_ctrl, "5200", 0},
624 {mcfisa_a, mcf_ctrl, "5202", 1},
625 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 626 {mcfisa_a, mcf5206_ctrl, "5206", 1},
cf869cce 627
78336706 628 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
cf869cce 629
2da12c60
NS		 630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
cf869cce 632
96e0bbcc
NS		 633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
cf869cce 635
2da12c60
NS		 636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
cf869cce 639
2da12c60
NS		 640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
643
46203761
MK		 644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
645
d5be9593
NS		 646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
648
96e0bbcc
NS		 649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
651 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
cf869cce 653
96e0bbcc
NS		 654 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
cf869cce 656
87298967
NS		 657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
659
2da12c60
NS		 660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
665
666 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
667 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 668 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
87298967
NS		 669
670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
674 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
676
2da12c60
NS		 677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
678 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
679
680 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
681
682 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
683 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
684
685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
689
87298967
NS		 690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
694 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
695 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
696 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
697
78336706 698 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
2da12c60
NS		 699
700 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
701 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
702 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
703 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
704
705 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
706 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
707 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
708
def8fc92 709 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
9a2e615a 710
0d999f33
MK		 711 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
712 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
713 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
714 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
715 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
716
9a2e615a
NS		 717 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
718 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
719 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
720 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
721 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
722 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
2da12c60 723
a8e24a56
NS		 724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
725 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
726 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
727 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
728 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
729 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
730 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 731
a8e24a56
NS		 732 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
733 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
734 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
735 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
736 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
737 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
738 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 739
b3768379 740 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 741 {fido_a, fido_ctrl, "fido", 1},
9840d27e 742
2da12c60 743 {0,NULL,NULL, 0}
dc84e067 744 };
252b5132 745
266abb8f
NS		 746static const struct m68k_cpu *m68k_lookup_cpu
747(const char *, const struct m68k_cpu *, int, int *);
748static int m68k_set_arch (const char *, int, int);
749static int m68k_set_cpu (const char *, int, int);
750static int m68k_set_extension (const char *, int, int);
751static void m68k_init_arch (void);
252b5132 752
151337e8
NC		 753/* This is the assembler relaxation table for m68k. m68k is a rich CISC
754 architecture and we have a lot of relaxation modes. */
252b5132 755
151337e8
NC		 756/* Macros used in the relaxation code. */
757#define TAB(x,y) (((x) << 2) + (y))
758#define TABTYPE(x) ((x) >> 2)
759
760/* Relaxation states. */
761#define BYTE 0
762#define SHORT 1
763#define LONG 2
764#define SZ_UNDEF 3
765
766/* Here are all the relaxation modes we support. First we can relax ordinary
767 branches. On 68020 and higher and on CPU32 all branch instructions take
768 three forms, so on these CPUs all branches always remain as such. When we
769 have to expand to the LONG form on a 68000, though, we substitute an
770 absolute jump instead. This is a direct replacement for unconditional
771 branches and a branch over a jump for conditional branches. However, if the
772 user requires PIC and disables this with --pcrel, we can only relax between
773 BYTE and SHORT forms, punting if that isn't enough. This gives us four
774 different relaxation modes for branches: */
775
36759679
NC		 776#define BRANCHBWL 0 /* Branch byte, word, or long. */
777#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
778#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
779#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 780
781/* We also relax coprocessor branches and DBcc's. All CPUs that support
782 coprocessor branches support them in word and long forms, so we have only
783 one relaxation mode for them. DBcc's are word only on all CPUs. We can
784 relax them to the LONG form with a branch-around sequence. This sequence
785 can use a long branch (if available) or an absolute jump (if acceptable).
786 This gives us two relaxation modes. If long branches are not available and
787 absolute jumps are not acceptable, we don't relax DBcc's. */
788
36759679
NC		 789#define FBRANCH 4 /* Coprocessor branch. */
790#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
791#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 792
793/* That's all for instruction relaxation. However, we also relax PC-relative
794 operands. Specifically, we have three operand relaxation modes. On the
795 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
796 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
797 two. Also PC+displacement+index operands in their simple form (with a non-
798 suppressed index without memory indirection) are supported on all CPUs, but
799 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
800 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
801 form of the PC+displacement+index operand. Finally, some absolute operands
802 can be relaxed down to 16-bit PC-relative. */
803
36759679
NC		 804#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
805#define PCINDEX 8 /* PC + displacement + index. */
806#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132 807
cac27205
NC		 808/* This relaxation is required for branches where there is no long
809 branch and we are in pcrel mode. We generate a bne/beq pair. */
810#define BRANCHBWPL 10 /* Branch byte, word or pair of longs
811 */
812
252b5132 813/* Note that calls to frag_var need to specify the maximum expansion
cac27205
NC		 814 needed; this is currently 12 bytes for bne/beq pair. */
815#define FRAG_VAR_SIZE 12
252b5132
RH		 816
817/* The fields are:
818 How far Forward this mode will reach:
819 How far Backward this mode will reach:
820 How many bytes this mode will add to the size of the frag
821 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 822
823 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 824relax_typeS md_relax_table[] =
825{
ac62c346
AM		 826 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
827 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
828 { 0, 0, 4, 0 },
829 { 1, 1, 0, 0 },
830
831 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
832 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
833 { 0, 0, 4, 0 },
834 { 1, 1, 0, 0 },
835
836 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
837 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
838 { 0, 0, 6, 0 },
839 { 1, 1, 0, 0 },
840
841 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
842 { 0, 0, 2, 0 },
843 { 1, 1, 0, 0 },
844 { 1, 1, 0, 0 },
845
36759679 846 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 847 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
848 { 0, 0, 4, 0 },
849 { 1, 1, 0, 0 },
850
36759679 851 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 852 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
853 { 0, 0, 10, 0 },
854 { 1, 1, 0, 0 },
855
36759679 856 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 857 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
858 { 0, 0, 10, 0 },
859 { 1, 1, 0, 0 },
860
36759679 861 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 862 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
863 { 0, 0, 6, 0 },
864 { 1, 1, 0, 0 },
865
866 { 125, -130, 0, TAB (PCINDEX, SHORT) },
867 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
868 { 0, 0, 4, 0 },
869 { 1, 1, 0, 0 },
870
36759679 871 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 872 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
873 { 0, 0, 4, 0 },
874 { 1, 1, 0, 0 },
cac27205
NC		 875
876 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
877 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
878 { 0, 0, 10, 0 },
879 { 1, 1, 0, 0 },
252b5132
RH		 880};
881
882/* These are the machine dependent pseudo-ops. These are included so
883 the assembler can work on the output from the SUN C compiler, which
36759679 884 generates these. */
252b5132
RH		 885
886/* This table describes all the machine specific pseudo-ops the assembler
887 has to support. The fields are:
888 pseudo-op name without dot
889 function to call to execute this pseudo-op
36759679 890 Integer arg to pass to the function. */
252b5132
RH		 891const pseudo_typeS md_pseudo_table[] =
892{
893 {"data1", s_data1, 0},
894 {"data2", s_data2, 0},
895 {"bss", s_bss, 0},
896 {"even", s_even, 0},
897 {"skip", s_space, 0},
898 {"proc", s_proc, 0},
899#if defined (TE_SUN3) || defined (OBJ_ELF)
900 {"align", s_align_bytes, 0},
901#endif
902#ifdef OBJ_ELF
903 {"swbeg", s_ignore, 0},
cf869cce 904 {"long", m68k_elf_cons, 4},
252b5132
RH		 905#endif
906 {"extend", float_cons, 'x'},
907 {"ldouble", float_cons, 'x'},
908
266abb8f
NS		 909 {"arch", s_m68k_arch, 0},
910 {"cpu", s_m68k_cpu, 0},
911
252b5132
RH		 912 /* The following pseudo-ops are supported for MRI compatibility. */
913 {"chip", s_chip, 0},
914 {"comline", s_space, 1},
915 {"fopt", s_fopt, 0},
916 {"mask2", s_ignore, 0},
917 {"opt", s_opt, 0},
918 {"reg", s_reg, 0},
919 {"restore", s_restore, 0},
920 {"save", s_save, 0},
921
922 {"if", s_mri_if, 0},
923 {"if.b", s_mri_if, 'b'},
924 {"if.w", s_mri_if, 'w'},
925 {"if.l", s_mri_if, 'l'},
926 {"else", s_mri_else, 0},
927 {"else.s", s_mri_else, 's'},
928 {"else.l", s_mri_else, 'l'},
929 {"endi", s_mri_endi, 0},
930 {"break", s_mri_break, 0},
931 {"break.s", s_mri_break, 's'},
932 {"break.l", s_mri_break, 'l'},
933 {"next", s_mri_next, 0},
934 {"next.s", s_mri_next, 's'},
935 {"next.l", s_mri_next, 'l'},
936 {"for", s_mri_for, 0},
937 {"for.b", s_mri_for, 'b'},
938 {"for.w", s_mri_for, 'w'},
939 {"for.l", s_mri_for, 'l'},
940 {"endf", s_mri_endf, 0},
941 {"repeat", s_mri_repeat, 0},
942 {"until", s_mri_until, 0},
943 {"until.b", s_mri_until, 'b'},
944 {"until.w", s_mri_until, 'w'},
945 {"until.l", s_mri_until, 'l'},
946 {"while", s_mri_while, 0},
947 {"while.b", s_mri_while, 'b'},
948 {"while.w", s_mri_while, 'w'},
949 {"while.l", s_mri_while, 'l'},
950 {"endw", s_mri_endw, 0},
951
952 {0, 0, 0}
953};
954
252b5132 955/* The mote pseudo ops are put into the opcode table, since they
31302357 956 don't start with a . they look like opcodes to gas. */
252b5132 957
5a38dc70 958const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 959{
960
961 {"dcl", cons, 4},
962 {"dc", cons, 2},
963 {"dcw", cons, 2},
964 {"dcb", cons, 1},
965
966 {"dsl", s_space, 4},
967 {"ds", s_space, 2},
968 {"dsw", s_space, 2},
969 {"dsb", s_space, 1},
970
971 {"xdef", s_globl, 0},
972#ifdef OBJ_ELF
973 {"align", s_align_bytes, 0},
974#else
975 {"align", s_align_ptwo, 0},
976#endif
977#ifdef M68KCOFF
978 {"sect", obj_coff_section, 0},
979 {"section", obj_coff_section, 0},
980#endif
981 {0, 0, 0}
982};
983
bd17c2c3
AM		 984/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
985 gives identical results to a 32-bit host. */
986#define TRUNC(X) ((valueT) (X) & 0xffffffff)
987#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
988
989#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
990#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
991#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
992#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
993
994#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
995#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 996#define islong(x) (1)
997
252b5132
RH		 998static char notend_table[256];
999static char alt_notend_table[256];
1000#define notend(s) \
1001 (! (notend_table[(unsigned char) *s] \
1002 || (*s == ':' \
1003 && alt_notend_table[(unsigned char) s[1]])))
1004
252b5132
RH		 1005#ifdef OBJ_ELF
1006
c801568a
AM		 1007/* Return zero if the reference to SYMBOL from within the same segment may
1008 be relaxed. */
1009
1010/* On an ELF system, we can't relax an externally visible symbol,
1011 because it may be overridden by a shared library. However, if
1012 TARGET_OS is "elf", then we presume that we are assembling for an
1013 embedded system, in which case we don't have to worry about shared
1014 libraries, and we can relax any external sym. */
1015
1016#define relaxable_symbol(symbol) \
6358301e 1017 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 1018 || S_IS_WEAK (symbol)))
1019
252b5132
RH		 1020/* Compute the relocation code for a fixup of SIZE bytes, using pc
1021 relative relocation if PCREL is non-zero. PIC says whether a special
1022 pic relocation was requested. */
1023
252b5132 1024static bfd_reloc_code_real_type
31302357 1025get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 1026{
1027 switch (pic)
1028 {
1029 case pic_got_pcrel:
1030 switch (size)
1031 {
1032 case 1:
1033 return BFD_RELOC_8_GOT_PCREL;
1034 case 2:
1035 return BFD_RELOC_16_GOT_PCREL;
1036 case 4:
1037 return BFD_RELOC_32_GOT_PCREL;
1038 }
1039 break;
1040
1041 case pic_got_off:
1042 switch (size)
1043 {
1044 case 1:
1045 return BFD_RELOC_8_GOTOFF;
1046 case 2:
1047 return BFD_RELOC_16_GOTOFF;
1048 case 4:
1049 return BFD_RELOC_32_GOTOFF;
1050 }
1051 break;
1052
1053 case pic_plt_pcrel:
1054 switch (size)
1055 {
1056 case 1:
1057 return BFD_RELOC_8_PLT_PCREL;
1058 case 2:
1059 return BFD_RELOC_16_PLT_PCREL;
1060 case 4:
1061 return BFD_RELOC_32_PLT_PCREL;
1062 }
1063 break;
1064
1065 case pic_plt_off:
1066 switch (size)
1067 {
1068 case 1:
1069 return BFD_RELOC_8_PLTOFF;
1070 case 2:
1071 return BFD_RELOC_16_PLTOFF;
1072 case 4:
1073 return BFD_RELOC_32_PLTOFF;
1074 }
1075 break;
1076
cf869cce
NC		 1077 case pic_tls_gd:
1078 switch (size)
1079 {
1080 case 1:
1081 return BFD_RELOC_68K_TLS_GD8;
1082 case 2:
1083 return BFD_RELOC_68K_TLS_GD16;
1084 case 4:
1085 return BFD_RELOC_68K_TLS_GD32;
1086 }
1087 break;
1088
1089 case pic_tls_ldm:
1090 switch (size)
1091 {
1092 case 1:
1093 return BFD_RELOC_68K_TLS_LDM8;
1094 case 2:
1095 return BFD_RELOC_68K_TLS_LDM16;
1096 case 4:
1097 return BFD_RELOC_68K_TLS_LDM32;
1098 }
1099 break;
1100
1101 case pic_tls_ldo:
1102 switch (size)
1103 {
1104 case 1:
1105 return BFD_RELOC_68K_TLS_LDO8;
1106 case 2:
1107 return BFD_RELOC_68K_TLS_LDO16;
1108 case 4:
1109 return BFD_RELOC_68K_TLS_LDO32;
1110 }
1111 break;
1112
1113 case pic_tls_ie:
1114 switch (size)
1115 {
1116 case 1:
1117 return BFD_RELOC_68K_TLS_IE8;
1118 case 2:
1119 return BFD_RELOC_68K_TLS_IE16;
1120 case 4:
1121 return BFD_RELOC_68K_TLS_IE32;
1122 }
1123 break;
1124
1125 case pic_tls_le:
1126 switch (size)
1127 {
1128 case 1:
1129 return BFD_RELOC_68K_TLS_LE8;
1130 case 2:
1131 return BFD_RELOC_68K_TLS_LE16;
1132 case 4:
1133 return BFD_RELOC_68K_TLS_LE32;
1134 }
1135 break;
1136
252b5132
RH		 1137 case pic_none:
1138 if (pcrel)
1139 {
1140 switch (size)
1141 {
1142 case 1:
1143 return BFD_RELOC_8_PCREL;
1144 case 2:
1145 return BFD_RELOC_16_PCREL;
1146 case 4:
1147 return BFD_RELOC_32_PCREL;
1148 }
1149 }
1150 else
1151 {
1152 switch (size)
1153 {
1154 case 1:
1155 return BFD_RELOC_8;
1156 case 2:
1157 return BFD_RELOC_16;
1158 case 4:
1159 return BFD_RELOC_32;
1160 }
1161 }
1162 }
1163
1164 if (pcrel)
1165 {
1166 if (pic == pic_none)
1167 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1168 else
1169 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1170 }
1171 else
1172 {
1173 if (pic == pic_none)
1174 as_bad (_("Can not do %d byte relocation"), size);
1175 else
1176 as_bad (_("Can not do %d byte pic relocation"), size);
1177 }
1178
1179 return BFD_RELOC_NONE;
1180}
1181
1182/* Here we decide which fixups can be adjusted to make them relative
1183 to the beginning of the section instead of the symbol. Basically
1184 we need to make sure that the dynamic relocations are done
1185 correctly, so in some cases we force the original symbol to be
1186 used. */
1187int
31302357 1188tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1189{
36759679 1190 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1191 switch (fixP->fx_r_type)
1192 {
1193 case BFD_RELOC_8_GOT_PCREL:
1194 case BFD_RELOC_16_GOT_PCREL:
1195 case BFD_RELOC_32_GOT_PCREL:
1196 case BFD_RELOC_8_GOTOFF:
1197 case BFD_RELOC_16_GOTOFF:
1198 case BFD_RELOC_32_GOTOFF:
1199 case BFD_RELOC_8_PLT_PCREL:
1200 case BFD_RELOC_16_PLT_PCREL:
1201 case BFD_RELOC_32_PLT_PCREL:
1202 case BFD_RELOC_8_PLTOFF:
1203 case BFD_RELOC_16_PLTOFF:
1204 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1205 case BFD_RELOC_68K_TLS_GD32:
1206 case BFD_RELOC_68K_TLS_GD16:
1207 case BFD_RELOC_68K_TLS_GD8:
1208 case BFD_RELOC_68K_TLS_LDM32:
1209 case BFD_RELOC_68K_TLS_LDM16:
1210 case BFD_RELOC_68K_TLS_LDM8:
1211 case BFD_RELOC_68K_TLS_LDO32:
1212 case BFD_RELOC_68K_TLS_LDO16:
1213 case BFD_RELOC_68K_TLS_LDO8:
1214 case BFD_RELOC_68K_TLS_IE32:
1215 case BFD_RELOC_68K_TLS_IE16:
1216 case BFD_RELOC_68K_TLS_IE8:
1217 case BFD_RELOC_68K_TLS_LE32:
1218 case BFD_RELOC_68K_TLS_LE16:
1219 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1220 return 0;
1221
1222 case BFD_RELOC_VTABLE_INHERIT:
1223 case BFD_RELOC_VTABLE_ENTRY:
1224 return 0;
1225
1226 default:
1227 return 1;
1228 }
1229}
1230
1231#else /* !OBJ_ELF */
1232
1233#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1234
22184a77
NC		 1235/* PR gas/3041 Weak symbols are not relaxable
1236 because they must be treated as extern. */
1237#define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
c801568a 1238
252b5132
RH		 1239#endif /* OBJ_ELF */
1240
252b5132 1241arelent *
31302357 1242tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1243{
1244 arelent *reloc;
1245 bfd_reloc_code_real_type code;
1246
8ec6253e
NC		 1247 /* If the tcbit is set, then this was a fixup of a negative value
1248 that was never resolved. We do not have a reloc to handle this,
1249 so just return. We assume that other code will have detected this
1250 situation and produced a helpful error message, so we just tell the
1251 user that the reloc cannot be produced. */
252b5132 1252 if (fixp->fx_tcbit)
8ec6253e
NC		 1253 {
1254 if (fixp->fx_addsy)
b091f402
AM		 1255 as_bad_where (fixp->fx_file, fixp->fx_line,
1256 _("Unable to produce reloc against symbol '%s'"),
1257 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1258 return NULL;
1259 }
252b5132
RH		 1260
1261 if (fixp->fx_r_type != BFD_RELOC_NONE)
1262 {
1263 code = fixp->fx_r_type;
1264
1265 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1266 that fixup_segment converted a non-PC relative reloc into a
1267 PC relative reloc. In such a case, we need to convert the
1268 reloc code. */
1269 if (fixp->fx_pcrel)
1270 {
1271 switch (code)
1272 {
1273 case BFD_RELOC_8:
1274 code = BFD_RELOC_8_PCREL;
1275 break;
1276 case BFD_RELOC_16:
1277 code = BFD_RELOC_16_PCREL;
1278 break;
1279 case BFD_RELOC_32:
1280 code = BFD_RELOC_32_PCREL;
1281 break;
1282 case BFD_RELOC_8_PCREL:
1283 case BFD_RELOC_16_PCREL:
1284 case BFD_RELOC_32_PCREL:
1285 case BFD_RELOC_8_GOT_PCREL:
1286 case BFD_RELOC_16_GOT_PCREL:
1287 case BFD_RELOC_32_GOT_PCREL:
1288 case BFD_RELOC_8_GOTOFF:
1289 case BFD_RELOC_16_GOTOFF:
1290 case BFD_RELOC_32_GOTOFF:
1291 case BFD_RELOC_8_PLT_PCREL:
1292 case BFD_RELOC_16_PLT_PCREL:
1293 case BFD_RELOC_32_PLT_PCREL:
1294 case BFD_RELOC_8_PLTOFF:
1295 case BFD_RELOC_16_PLTOFF:
1296 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1297 case BFD_RELOC_68K_TLS_GD32:
1298 case BFD_RELOC_68K_TLS_GD16:
1299 case BFD_RELOC_68K_TLS_GD8:
1300 case BFD_RELOC_68K_TLS_LDM32:
1301 case BFD_RELOC_68K_TLS_LDM16:
1302 case BFD_RELOC_68K_TLS_LDM8:
1303 case BFD_RELOC_68K_TLS_LDO32:
1304 case BFD_RELOC_68K_TLS_LDO16:
1305 case BFD_RELOC_68K_TLS_LDO8:
1306 case BFD_RELOC_68K_TLS_IE32:
1307 case BFD_RELOC_68K_TLS_IE16:
1308 case BFD_RELOC_68K_TLS_IE8:
1309 case BFD_RELOC_68K_TLS_LE32:
1310 case BFD_RELOC_68K_TLS_LE16:
1311 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1312 break;
1313 default:
1314 as_bad_where (fixp->fx_file, fixp->fx_line,
1315 _("Cannot make %s relocation PC relative"),
1316 bfd_get_reloc_code_name (code));
1317 }
1318 }
1319 }
1320 else
1321 {
1322#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1323 switch (F (fixp->fx_size, fixp->fx_pcrel))
1324 {
1325#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1326 MAP (1, 0, BFD_RELOC_8);
1327 MAP (2, 0, BFD_RELOC_16);
1328 MAP (4, 0, BFD_RELOC_32);
1329 MAP (1, 1, BFD_RELOC_8_PCREL);
1330 MAP (2, 1, BFD_RELOC_16_PCREL);
1331 MAP (4, 1, BFD_RELOC_32_PCREL);
1332 default:
1333 abort ();
1334 }
1335 }
1336#undef F
1337#undef MAP
1338
1339 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1340 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1341 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1342 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1343#ifndef OBJ_ELF
33f0727f
NC		 1344 if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1345 && fixp->fx_addsy
1346 && S_IS_WEAK (fixp->fx_addsy)
1347 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
b2b74248
NC		 1348 {
1349 /* PR gas/3041 References to weak symbols must be treated as extern
1350 in order to be overridable by the linker, even if they are defined
1351 in the same object file. So the original addend must be written
1352 "as is" into the output section without further processing.
1353 The addend value must be hacked here in order to force
1354 bfd_install_relocation() to write the original value into the
1355 output section.
1356 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1357 value has already been added to the addend in fixup_segment(). We
1358 have to remove it.
1359 2) bfd_install_relocation() will incorrectly treat this symbol as
1360 resolved, so it will write the symbol value plus its addend and
1361 section VMA. As a workaround we can tweak the addend value here in
1362 order to get the original value in the section after the call to
1363 bfd_install_relocation(). */
1364 reloc->addend = fixp->fx_addnumber
1365 /* Fix because of MD_APPLY_SYM_VALUE() */
1366 - S_GET_VALUE (fixp->fx_addsy)
1367 /* Fix for bfd_install_relocation() */
1368 - (S_GET_VALUE (fixp->fx_addsy)
1369 + S_GET_SEGMENT (fixp->fx_addsy)->vma);
1370 }
33f0727f
NC		 1371 else if (fixp->fx_pcrel)
1372 reloc->addend = fixp->fx_addnumber;
252b5132
RH		 1373 else
1374 reloc->addend = 0;
1375#else
1376 if (!fixp->fx_pcrel)
1377 reloc->addend = fixp->fx_addnumber;
1378 else
1379 reloc->addend = (section->vma
552c607f 1380 + fixp->fx_pcrel_adjust
252b5132
RH		 1381 + fixp->fx_addnumber
1382 + md_pcrel_from (fixp));
1383#endif
1384
1385 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
9c2799c2 1386 gas_assert (reloc->howto != 0);
252b5132
RH		 1387
1388 return reloc;
1389}
1390
252b5132
RH		 1391/* Handle of the OPCODE hash table. NULL means any use before
1392 m68k_ip_begin() will crash. */
1393static struct hash_control *op_hash;
1394\f
1395/* Assemble an m68k instruction. */
1396
1397static void
31302357 1398m68k_ip (char *instring)
252b5132
RH		 1399{
1400 register char *p;
1401 register struct m68k_op *opP;
1402 register const struct m68k_incant *opcode;
1403 register const char *s;
1404 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1405 char *pdot, *pdotmove;
1406 enum m68k_size siz1, siz2;
1407 char c;
1408 int losing;
1409 int opsfound;
03b13e59 1410 struct m68k_op operands_backup[6];
252b5132
RH		 1411 LITTLENUM_TYPE words[6];
1412 LITTLENUM_TYPE *wordp;
1413 unsigned long ok_arch = 0;
1414
1415 if (*instring == ' ')
36759679 1416 instring++; /* Skip leading whitespace. */
252b5132
RH		 1417
1418 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1419 or exactly 1 space. */
252b5132
RH		 1420 pdot = 0;
1421 for (p = instring; *p != '\0'; p++)
1422 {
1423 if (*p == ' ')
1424 break;
1425 if (*p == '.')
1426 pdot = p;
1427 }
1428
1429 if (p == instring)
1430 {
1431 the_ins.error = _("No operator");
1432 return;
1433 }
1434
1435 /* p now points to the end of the opcode name, probably whitespace.
1436 Make sure the name is null terminated by clobbering the
1437 whitespace, look it up in the hash table, then fix it back.
1438 Remove a dot, first, since the opcode tables have none. */
1439 if (pdot != NULL)
1440 {
1441 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1442 *pdotmove = pdotmove[1];
1443 p--;
1444 }
1445
1446 c = *p;
1447 *p = '\0';
1448 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1449 *p = c;
1450
1451 if (pdot != NULL)
1452 {
1453 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1454 *pdotmove = pdotmove[-1];
1455 *pdot = '.';
1456 ++p;
1457 }
1458
1459 if (opcode == NULL)
1460 {
1461 the_ins.error = _("Unknown operator");
1462 return;
1463 }
1464
36759679 1465 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1466 while (*p == ' ')
1467 ++p;
1468
1469 if (opcode->m_operands == 0)
1470 {
1471 char *old = input_line_pointer;
1472 *old = '\n';
1473 input_line_pointer = p;
36759679 1474 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1475 mote_pseudo_table[opcode->m_opnum].poc_handler
1476 (mote_pseudo_table[opcode->m_opnum].poc_val);
1477 input_line_pointer = old;
1478 *old = 0;
1479
1480 return;
1481 }
1482
1483 if (flag_mri && opcode->m_opnum == 0)
1484 {
1485 /* In MRI mode, random garbage is allowed after an instruction
1486 which accepts no operands. */
1487 the_ins.args = opcode->m_operands;
1488 the_ins.numargs = opcode->m_opnum;
1489 the_ins.numo = opcode->m_codenum;
1490 the_ins.opcode[0] = getone (opcode);
1491 the_ins.opcode[1] = gettwo (opcode);
1492 return;
1493 }
1494
1495 for (opP = &the_ins.operands[0]; *p; opP++)
1496 {
1497 p = crack_operand (p, opP);
1498
1499 if (opP->error)
1500 {
1501 the_ins.error = opP->error;
1502 return;
1503 }
1504 }
1505
1506 opsfound = opP - &the_ins.operands[0];
1507
1508 /* This ugly hack is to support the floating pt opcodes in their
1509 standard form. Essentially, we fake a first enty of type COP#1 */
1510 if (opcode->m_operands[0] == 'I')
1511 {
1512 int n;
1513
1514 for (n = opsfound; n > 0; --n)
1515 the_ins.operands[n] = the_ins.operands[n - 1];
1516
31302357 1517 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1518 the_ins.operands[0].mode = CONTROL;
1519 the_ins.operands[0].reg = m68k_float_copnum;
1520 opsfound++;
1521 }
1522
36759679 1523 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1524 for (losing = 0;;)
1525 {
1526 /* If we didn't get the right number of ops, or we have no
92774660 1527 common model with this pattern then reject this pattern. */
252b5132
RH		 1528
1529 ok_arch |= opcode->m_arch;
1530 if (opsfound != opcode->m_opnum
1531 || ((opcode->m_arch & current_architecture) == 0))
1532 ++losing;
1533 else
1534 {
03b13e59
NC		 1535 int i;
1536
1537 /* Make a copy of the operands of this insn so that
1538 we can modify them safely, should we want to. */
9c2799c2 1539 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
03b13e59
NC		 1540 for (i = 0; i < opsfound; i++)
1541 operands_backup[i] = the_ins.operands[i];
1542
1543 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1544 *s && !losing;
1545 s += 2, opP++)
1546 {
1547 /* Warning: this switch is huge! */
1548 /* I've tried to organize the cases into this order:
1549 non-alpha first, then alpha by letter. Lower-case
1550 goes directly before uppercase counterpart. */
1551 /* Code with multiple case ...: gets sorted by the lowest
1552 case ... it belongs to. I hope this makes sense. */
1553 switch (*s)
1554 {
1555 case '!':
1556 switch (opP->mode)
1557 {
1558 case IMMED:
1559 case DREG:
1560 case AREG:
1561 case FPREG:
1562 case CONTROL:
1563 case AINC:
1564 case ADEC:
1565 case REGLST:
1566 losing++;
1567 break;
1568 default:
1569 break;
1570 }
1571 break;
1572
1573 case '<':
1574 switch (opP->mode)
1575 {
1576 case DREG:
1577 case AREG:
1578 case FPREG:
1579 case CONTROL:
1580 case IMMED:
1581 case ADEC:
1582 case REGLST:
1583 losing++;
1584 break;
1585 default:
1586 break;
1587 }
1588 break;
1589
1590 case '>':
1591 switch (opP->mode)
1592 {
1593 case DREG:
1594 case AREG:
1595 case FPREG:
1596 case CONTROL:
1597 case IMMED:
1598 case AINC:
1599 case REGLST:
1600 losing++;
1601 break;
1602 case ABSL:
1603 break;
1604 default:
1605 if (opP->reg == PC
1606 || opP->reg == ZPC)
1607 losing++;
1608 break;
1609 }
1610 break;
1611
1612 case 'm':
1613 switch (opP->mode)
1614 {
1615 case DREG:
1616 case AREG:
1617 case AINDR:
1618 case AINC:
1619 case ADEC:
1620 break;
1621 default:
1622 losing++;
1623 }
8a104df9 1624 break;
252b5132
RH		 1625
1626 case 'n':
1627 switch (opP->mode)
1628 {
1629 case DISP:
1630 break;
1631 default:
1632 losing++;
1633 }
8a104df9 1634 break;
252b5132
RH		 1635
1636 case 'o':
1637 switch (opP->mode)
1638 {
1639 case BASE:
1640 case ABSL:
1641 case IMMED:
1642 break;
1643 default:
1644 losing++;
1645 }
8a104df9 1646 break;
252b5132
RH		 1647
1648 case 'p':
1649 switch (opP->mode)
1650 {
1651 case DREG:
1652 case AREG:
1653 case AINDR:
1654 case AINC:
1655 case ADEC:
1656 break;
1657 case DISP:
1658 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1659 losing++;
252b5132
RH		 1660 break;
1661 default:
1662 losing++;
1663 }
8a104df9 1664 break;
252b5132
RH		 1665
1666 case 'q':
1667 switch (opP->mode)
1668 {
1669 case DREG:
1670 case AINDR:
1671 case AINC:
1672 case ADEC:
1673 break;
1674 case DISP:
1675 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1676 losing++;
252b5132
RH		 1677 break;
1678 default:
1679 losing++;
1680 break;
1681 }
8a104df9 1682 break;
252b5132
RH		 1683
1684 case 'v':
1685 switch (opP->mode)
1686 {
1687 case DREG:
1688 case AINDR:
1689 case AINC:
1690 case ADEC:
1691 case ABSL:
1692 break;
1693 case DISP:
1694 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1695 losing++;
252b5132
RH		 1696 break;
1697 default:
1698 losing++;
1699 break;
1700 }
1701 break;
1702
1703 case '#':
1704 if (opP->mode != IMMED)
1705 losing++;
1706 else if (s[1] == 'b'
1707 && ! isvar (&opP->disp)
1708 && (opP->disp.exp.X_op != O_constant
1709 || ! isbyte (opP->disp.exp.X_add_number)))
1710 losing++;
1711 else if (s[1] == 'B'
1712 && ! isvar (&opP->disp)
1713 && (opP->disp.exp.X_op != O_constant
1714 || ! issbyte (opP->disp.exp.X_add_number)))
1715 losing++;
1716 else if (s[1] == 'w'
1717 && ! isvar (&opP->disp)
1718 && (opP->disp.exp.X_op != O_constant
1719 || ! isword (opP->disp.exp.X_add_number)))
1720 losing++;
1721 else if (s[1] == 'W'
1722 && ! isvar (&opP->disp)
1723 && (opP->disp.exp.X_op != O_constant
1724 || ! issword (opP->disp.exp.X_add_number)))
1725 losing++;
1726 break;
1727
1728 case '^':
1729 case 'T':
1730 if (opP->mode != IMMED)
1731 losing++;
1732 break;
1733
1734 case '$':
1735 if (opP->mode == AREG
1736 || opP->mode == CONTROL
1737 || opP->mode == FPREG
1738 || opP->mode == IMMED
1739 || opP->mode == REGLST
1740 || (opP->mode != ABSL
1741 && (opP->reg == PC
1742 || opP->reg == ZPC)))
1743 losing++;
1744 break;
1745
1746 case '%':
1747 if (opP->mode == CONTROL
1748 || opP->mode == FPREG
1749 || opP->mode == REGLST
1750 || opP->mode == IMMED
1751 || (opP->mode != ABSL
1752 && (opP->reg == PC
1753 || opP->reg == ZPC)))
1754 losing++;
1755 break;
1756
1757 case '&':
1758 switch (opP->mode)
1759 {
1760 case DREG:
1761 case AREG:
1762 case FPREG:
1763 case CONTROL:
1764 case IMMED:
1765 case AINC:
1766 case ADEC:
1767 case REGLST:
1768 losing++;
1769 break;
1770 case ABSL:
1771 break;
1772 default:
1773 if (opP->reg == PC
1774 || opP->reg == ZPC)
1775 losing++;
1776 break;
1777 }
1778 break;
1779
1780 case '*':
1781 if (opP->mode == CONTROL
1782 || opP->mode == FPREG
1783 || opP->mode == REGLST)
1784 losing++;
1785 break;
1786
1787 case '+':
1788 if (opP->mode != AINC)
1789 losing++;
1790 break;
1791
1792 case '-':
1793 if (opP->mode != ADEC)
1794 losing++;
1795 break;
1796
1797 case '/':
1798 switch (opP->mode)
1799 {
1800 case AREG:
1801 case CONTROL:
1802 case FPREG:
1803 case AINC:
1804 case ADEC:
1805 case IMMED:
1806 case REGLST:
1807 losing++;
1808 break;
1809 default:
1810 break;
1811 }
1812 break;
1813
1814 case ';':
1815 switch (opP->mode)
1816 {
1817 case AREG:
1818 case CONTROL:
1819 case FPREG:
1820 case REGLST:
1821 losing++;
1822 break;
1823 default:
1824 break;
1825 }
1826 break;
1827
1828 case '?':
1829 switch (opP->mode)
1830 {
1831 case AREG:
1832 case CONTROL:
1833 case FPREG:
1834 case AINC:
1835 case ADEC:
1836 case IMMED:
1837 case REGLST:
1838 losing++;
1839 break;
1840 case ABSL:
1841 break;
1842 default:
1843 if (opP->reg == PC || opP->reg == ZPC)
1844 losing++;
1845 break;
1846 }
1847 break;
1848
1849 case '@':
1850 switch (opP->mode)
1851 {
1852 case AREG:
1853 case CONTROL:
1854 case FPREG:
1855 case IMMED:
1856 case REGLST:
1857 losing++;
1858 break;
1859 default:
1860 break;
1861 }
1862 break;
1863
1864 case '~': /* For now! (JF FOO is this right?) */
1865 switch (opP->mode)
1866 {
1867 case DREG:
1868 case AREG:
1869 case CONTROL:
1870 case FPREG:
1871 case IMMED:
1872 case REGLST:
1873 losing++;
1874 break;
1875 case ABSL:
1876 break;
1877 default:
1878 if (opP->reg == PC
1879 || opP->reg == ZPC)
1880 losing++;
1881 break;
1882 }
1883 break;
1884
1885 case '3':
1886 if (opP->mode != CONTROL
1887 || (opP->reg != TT0 && opP->reg != TT1))
1888 losing++;
1889 break;
1890
1891 case 'A':
1892 if (opP->mode != AREG)
1893 losing++;
1894 break;
1895
1896 case 'a':
1897 if (opP->mode != AINDR)
1898 ++losing;
1899 break;
1900
fd99574b
NC		 1901 case '4':
1902 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1903 && (opP->mode != DISP
1904 || opP->reg < ADDR0
1905 || opP->reg > ADDR7))
1906 ++losing;
1907 break;
1908
252b5132
RH		 1909 case 'B': /* FOO */
1910 if (opP->mode != ABSL
1911 || (flag_long_jumps
1912 && strncmp (instring, "jbsr", 4) == 0))
1913 losing++;
1914 break;
1915
3e602632
NC		 1916 case 'b':
1917 switch (opP->mode)
1918 {
1919 case IMMED:
1920 case ABSL:
1921 case AREG:
1922 case FPREG:
1923 case CONTROL:
1924 case POST:
1925 case PRE:
1926 case REGLST:
1927 losing++;
1928 break;
1929 default:
1930 break;
1931 }
1932 break;
1933
252b5132
RH		 1934 case 'C':
1935 if (opP->mode != CONTROL || opP->reg != CCR)
1936 losing++;
1937 break;
1938
1939 case 'd':
1940 if (opP->mode != DISP
1941 || opP->reg < ADDR0
1942 || opP->reg > ADDR7)
1943 losing++;
1944 break;
1945
1946 case 'D':
1947 if (opP->mode != DREG)
1948 losing++;
1949 break;
1950
6da466c7
ILT		 1951 case 'E':
1952 if (opP->reg != ACC)
1953 losing++;
1954 break;
1955
fd99574b
NC		 1956 case 'e':
1957 if (opP->reg != ACC && opP->reg != ACC1
1958 && opP->reg != ACC2 && opP->reg != ACC3)
1959 losing++;
1960 break;
1961
252b5132
RH		 1962 case 'F':
1963 if (opP->mode != FPREG)
1964 losing++;
1965 break;
1966
6da466c7
ILT		 1967 case 'G':
1968 if (opP->reg != MACSR)
1969 losing++;
1970 break;
1971
fd99574b
NC		 1972 case 'g':
1973 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1974 losing++;
1975 break;
1976
6da466c7
ILT		 1977 case 'H':
1978 if (opP->reg != MASK)
1979 losing++;
1980 break;
1981
252b5132
RH		 1982 case 'I':
1983 if (opP->mode != CONTROL
1984 || opP->reg < COP0
1985 || opP->reg > COP7)
1986 losing++;
1987 break;
1988
fd99574b
NC		 1989 case 'i':
1990 if (opP->mode != LSH && opP->mode != RSH)
1991 losing++;
1992 break;
1993
252b5132
RH		 1994 case 'J':
1995 if (opP->mode != CONTROL
1996 || opP->reg < USP
0b2e31dc
NS		 1997 || opP->reg > last_movec_reg
1998 || !control_regs)
252b5132
RH		 1999 losing++;
2000 else
2001 {
2002 const enum m68k_register *rp;
0b2e31dc 2003
252b5132 2004 for (rp = control_regs; *rp; rp++)
78336706
NS		 2005 {
2006 if (*rp == opP->reg)
2007 break;
2008 /* In most CPUs RAMBAR refers to control reg
2009 c05 (RAMBAR1), but a few CPUs have it
2010 refer to c04 (RAMBAR0). */
2011 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
2012 {
2013 opP->reg = RAMBAR_ALT;
2014 break;
2015 }
2016 }
252b5132
RH		 2017 if (*rp == 0)
2018 losing++;
2019 }
2020 break;
2021
2022 case 'k':
2023 if (opP->mode != IMMED)
2024 losing++;
2025 break;
2026
2027 case 'l':
2028 case 'L':
2029 if (opP->mode == DREG
2030 || opP->mode == AREG
2031 || opP->mode == FPREG)
2032 {
2033 if (s[1] == '8')
2034 losing++;
2035 else
2036 {
2037 switch (opP->mode)
2038 {
2039 case DREG:
2040 opP->mask = 1 << (opP->reg - DATA0);
2041 break;
2042 case AREG:
2043 opP->mask = 1 << (opP->reg - ADDR0 + 8);
2044 break;
2045 case FPREG:
2046 opP->mask = 1 << (opP->reg - FP0 + 16);
2047 break;
2048 default:
2049 abort ();
2050 }
2051 opP->mode = REGLST;
2052 }
2053 }
2054 else if (opP->mode == CONTROL)
2055 {
2056 if (s[1] != '8')
2057 losing++;
2058 else
2059 {
2060 switch (opP->reg)
2061 {
2062 case FPI:
2063 opP->mask = 1 << 24;
2064 break;
2065 case FPS:
2066 opP->mask = 1 << 25;
2067 break;
2068 case FPC:
2069 opP->mask = 1 << 26;
2070 break;
2071 default:
2072 losing++;
2073 break;
2074 }
2075 opP->mode = REGLST;
2076 }
2077 }
2078 else if (opP->mode != REGLST)
2079 losing++;
2080 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2081 losing++;
2082 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2083 losing++;
2084 break;
2085
2086 case 'M':
2087 if (opP->mode != IMMED)
2088 losing++;
2089 else if (opP->disp.exp.X_op != O_constant
2090 || ! issbyte (opP->disp.exp.X_add_number))
2091 losing++;
2092 else if (! m68k_quick
2093 && instring[3] != 'q'
2094 && instring[4] != 'q')
2095 losing++;
2096 break;
2097
2098 case 'O':
2099 if (opP->mode != DREG
2100 && opP->mode != IMMED
2101 && opP->mode != ABSL)
2102 losing++;
2103 break;
2104
2105 case 'Q':
2106 if (opP->mode != IMMED)
2107 losing++;
2108 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2109 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 2110 losing++;
2111 else if (! m68k_quick
2112 && (strncmp (instring, "add", 3) == 0
2113 || strncmp (instring, "sub", 3) == 0)
2114 && instring[3] != 'q')
2115 losing++;
2116 break;
2117
2118 case 'R':
2119 if (opP->mode != DREG && opP->mode != AREG)
2120 losing++;
2121 break;
2122
2123 case 'r':
2124 if (opP->mode != AINDR
2125 && (opP->mode != BASE
2126 || (opP->reg != 0
2127 && opP->reg != ZADDR0)
2128 || opP->disp.exp.X_op != O_absent
2129 || ((opP->index.reg < DATA0
2130 || opP->index.reg > DATA7)
2131 && (opP->index.reg < ADDR0
2132 || opP->index.reg > ADDR7))
2133 || opP->index.size != SIZE_UNSPEC
2134 || opP->index.scale != 1))
2135 losing++;
2136 break;
2137
2138 case 's':
2139 if (opP->mode != CONTROL
2140 || ! (opP->reg == FPI
2141 || opP->reg == FPS
2142 || opP->reg == FPC))
2143 losing++;
2144 break;
2145
2146 case 'S':
2147 if (opP->mode != CONTROL || opP->reg != SR)
2148 losing++;
2149 break;
2150
2151 case 't':
2152 if (opP->mode != IMMED)
2153 losing++;
2154 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2155 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 2156 losing++;
2157 break;
2158
2159 case 'U':
2160 if (opP->mode != CONTROL || opP->reg != USP)
2161 losing++;
2162 break;
2163
3e602632
NC		 2164 case 'x':
2165 if (opP->mode != IMMED)
2166 losing++;
2167 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 2168 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2169 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 2170 losing++;
2171 break;
2172
afa2158f
NS		 2173 case 'j':
2174 if (opP->mode != IMMED)
2175 losing++;
2176 else if (opP->disp.exp.X_op != O_constant
2177 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2178 losing++;
2179 break;
2180
2181 case 'K':
2182 if (opP->mode != IMMED)
2183 losing++;
2184 else if (opP->disp.exp.X_op != O_constant
2185 || TRUNC (opP->disp.exp.X_add_number) > 511)
2186 losing++;
2187 break;
2188
252b5132
RH		 2189 /* JF these are out of order. We could put them
2190 in order if we were willing to put up with
2191 bunches of #ifdef m68851s in the code.
2192
2193 Don't forget that you need these operands
2194 to use 68030 MMU instructions. */
2195#ifndef NO_68851
36759679 2196 /* Memory addressing mode used by pflushr. */
252b5132
RH		 2197 case '|':
2198 if (opP->mode == CONTROL
2199 || opP->mode == FPREG
2200 || opP->mode == DREG
2201 || opP->mode == AREG
2202 || opP->mode == REGLST)
2203 losing++;
2204 /* We should accept immediate operands, but they
2205 supposedly have to be quad word, and we don't
2206 handle that. I would like to see what a Motorola
2207 assembler does before doing something here. */
2208 if (opP->mode == IMMED)
2209 losing++;
2210 break;
2211
2212 case 'f':
2213 if (opP->mode != CONTROL
2214 || (opP->reg != SFC && opP->reg != DFC))
2215 losing++;
2216 break;
2217
2218 case '0':
2219 if (opP->mode != CONTROL || opP->reg != TC)
2220 losing++;
2221 break;
2222
2223 case '1':
2224 if (opP->mode != CONTROL || opP->reg != AC)
2225 losing++;
2226 break;
2227
2228 case '2':
2229 if (opP->mode != CONTROL
2230 || (opP->reg != CAL
2231 && opP->reg != VAL
2232 && opP->reg != SCC))
2233 losing++;
2234 break;
2235
2236 case 'V':
2237 if (opP->mode != CONTROL
2238 || opP->reg != VAL)
2239 losing++;
2240 break;
2241
2242 case 'W':
2243 if (opP->mode != CONTROL
2244 || (opP->reg != DRP
2245 && opP->reg != SRP
2246 && opP->reg != CRP))
2247 losing++;
2248 break;
2249
3e602632
NC		 2250 case 'w':
2251 switch (opP->mode)
2252 {
2253 case IMMED:
2254 case ABSL:
2255 case AREG:
2256 case DREG:
2257 case FPREG:
2258 case CONTROL:
2259 case POST:
2260 case PRE:
2261 case REGLST:
2262 losing++;
2263 break;
2264 default:
2265 break;
2266 }
2267 break;
2268
252b5132
RH		 2269 case 'X':
2270 if (opP->mode != CONTROL
2271 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2272 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2273 losing++;
2274 break;
2275
2276 case 'Y':
2277 if (opP->mode != CONTROL || opP->reg != PSR)
2278 losing++;
2279 break;
2280
2281 case 'Z':
2282 if (opP->mode != CONTROL || opP->reg != PCSR)
2283 losing++;
2284 break;
2285#endif
2286 case 'c':
2287 if (opP->mode != CONTROL
2288 || (opP->reg != NC
2289 && opP->reg != IC
2290 && opP->reg != DC
2291 && opP->reg != BC))
36759679 2292 losing++;
252b5132
RH		 2293 break;
2294
2295 case '_':
2296 if (opP->mode != ABSL)
2297 ++losing;
2298 break;
2299
6da466c7
ILT		 2300 case 'u':
2301 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2302 losing++;
2303 /* FIXME: kludge instead of fixing parser:
2304 upper/lower registers are *not* CONTROL
92774660 2305 registers, but ordinary ones. */
6da466c7
ILT		 2306 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2307 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2308 opP->mode = DREG;
2309 else
2310 opP->mode = AREG;
2311 break;
2312
3e602632
NC		 2313 case 'y':
2314 if (!(opP->mode == AINDR
31302357
AS		 2315 || (opP->mode == DISP
2316 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2317 losing++;
2318 break;
2319
2320 case 'z':
2321 if (!(opP->mode == AINDR || opP->mode == DISP))
2322 losing++;
2323 break;
2324
252b5132
RH		 2325 default:
2326 abort ();
36759679 2327 }
252b5132
RH		 2328
2329 if (losing)
2330 break;
36759679 2331 }
03b13e59
NC		 2332
2333 /* Since we have found the correct instruction, copy
2334 in the modifications that we may have made. */
2335 if (!losing)
2336 for (i = 0; i < opsfound; i++)
2337 the_ins.operands[i] = operands_backup[i];
36759679 2338 }
252b5132
RH		 2339
2340 if (!losing)
36759679 2341 break;
252b5132
RH		 2342
2343 opcode = opcode->m_next;
2344
2345 if (!opcode)
2346 {
2347 if (ok_arch
2348 && !(ok_arch & current_architecture))
2349 {
6d89cc8f
NS		 2350 const struct m68k_cpu *cpu;
2351 int any = 0;
2352 size_t space = 400;
2353 char *buf = xmalloc (space + 1);
2354 size_t len;
2355 int paren = 1;
2356
2357 the_ins.error = buf;
2358 /* Make sure there's a NUL at the end of the buffer -- strncpy
b2f58c0c 2359 won't write one when it runs out of buffer. */
6d89cc8f
NS		 2360 buf[space] = 0;
2361#define APPEND(STRING) \
2362 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2363
2364 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2365 switch (ok_arch)
2366 {
6b6e92f4 2367 case mcfisa_a:
b2f58c0c 2368 APPEND ("ColdFire ISA_A");
6b6e92f4
NC		 2369 break;
2370 case mcfhwdiv:
b2f58c0c
NC		 2371 APPEND ("ColdFire ");
2372 APPEND (_("hardware divide"));
6b6e92f4
NC		 2373 break;
2374 case mcfisa_aa:
b2f58c0c 2375 APPEND ("ColdFire ISA_A+");
6b6e92f4
NC		 2376 break;
2377 case mcfisa_b:
b2f58c0c 2378 APPEND ("ColdFire ISA_B");
6b6e92f4 2379 break;
8d100c32 2380 case mcfisa_c:
b2f58c0c 2381 APPEND ("ColdFire ISA_C");
8d100c32 2382 break;
3e602632 2383 case cfloat:
b2f58c0c 2384 APPEND ("ColdFire fpu");
3e602632 2385 break;
252b5132 2386 case mfloat:
b2f58c0c 2387 APPEND ("M68K fpu");
252b5132
RH		 2388 break;
2389 case mmmu:
b2f58c0c 2390 APPEND ("M68K mmu");
252b5132
RH		 2391 break;
2392 case m68020up:
b2f58c0c
NC		 2393 APPEND ("68020 ");
2394 APPEND (_("or higher"));
252b5132
RH		 2395 break;
2396 case m68000up:
b2f58c0c
NC		 2397 APPEND ("68000 ");
2398 APPEND (_("or higher"));
252b5132
RH		 2399 break;
2400 case m68010up:
b2f58c0c
NC		 2401 APPEND ("68010 ");
2402 APPEND (_("or higher"));
252b5132
RH		 2403 break;
2404 default:
6d89cc8f
NS		 2405 paren = 0;
2406 }
2407 if (paren)
2408 APPEND (" (");
6b6e92f4 2409
6d89cc8f
NS		 2410 for (cpu = m68k_cpus; cpu->name; cpu++)
2411 if (!cpu->alias && (cpu->arch & ok_arch))
2412 {
2413 const struct m68k_cpu *alias;
869ddf2a
NS		 2414 int seen_master = 0;
2415
6d89cc8f
NS		 2416 if (any)
2417 APPEND (", ");
2418 any = 0;
2419 APPEND (cpu->name);
869ddf2a
NS		 2420 for (alias = cpu; alias != m68k_cpus; alias--)
2421 if (alias[-1].alias >= 0)
2422 break;
2423 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2424 {
869ddf2a
NS		 2425 if (!alias->alias)
2426 seen_master = 1;
2427 else
2428 {
2429 if (any)
2430 APPEND (", ");
2431 else
2432 APPEND (" [");
2433 APPEND (alias->name);
2434 any = 1;
2435 }
6d89cc8f 2436 }
869ddf2a
NS		 2437 if (any)
2438 APPEND ("]");
6d89cc8f 2439 any = 1;
252b5132 2440 }
6d89cc8f
NS		 2441 if (paren)
2442 APPEND (")");
2443#undef APPEND
2444 if (!space)
2445 {
b2f58c0c 2446 /* We ran out of space, so replace the end of the list
6d89cc8f
NS		 2447 with ellipsis. */
2448 buf -= 4;
2449 while (*buf != ' ')
2450 buf--;
2451 strcpy (buf, " ...");
252b5132 2452 }
252b5132
RH		 2453 }
2454 else
2455 the_ins.error = _("operands mismatch");
2456 return;
36759679 2457 }
252b5132
RH		 2458
2459 losing = 0;
2460 }
2461
36759679 2462 /* Now assemble it. */
252b5132
RH		 2463 the_ins.args = opcode->m_operands;
2464 the_ins.numargs = opcode->m_opnum;
2465 the_ins.numo = opcode->m_codenum;
2466 the_ins.opcode[0] = getone (opcode);
2467 the_ins.opcode[1] = gettwo (opcode);
2468
2469 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2470 {
9a2e615a 2471 int have_disp = 0;
cac27205 2472 int use_pl = 0;
9a2e615a 2473
252b5132 2474 /* This switch is a doozy.
31302357 2475 Watch the first step; its a big one! */
252b5132
RH		 2476 switch (s[0])
2477 {
2478
2479 case '*':
2480 case '~':
2481 case '%':
2482 case ';':
2483 case '@':
2484 case '!':
2485 case '&':
2486 case '$':
2487 case '?':
2488 case '/':
2489 case '<':
2490 case '>':
3e602632 2491 case 'b':
252b5132
RH		 2492 case 'm':
2493 case 'n':
2494 case 'o':
2495 case 'p':
2496 case 'q':
2497 case 'v':
3e602632
NC		 2498 case 'w':
2499 case 'y':
2500 case 'z':
fd99574b 2501 case '4':
252b5132
RH		 2502#ifndef NO_68851
2503 case '|':
2504#endif
2505 switch (opP->mode)
2506 {
2507 case IMMED:
2508 tmpreg = 0x3c; /* 7.4 */
2509 if (strchr ("bwl", s[1]))
3e602632 2510 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2511 else
2512 nextword = get_num (&opP->disp, 0);
2513 if (isvar (&opP->disp))
2514 add_fix (s[1], &opP->disp, 0, 0);
2515 switch (s[1])
2516 {
2517 case 'b':
2518 if (!isbyte (nextword))
2519 opP->error = _("operand out of range");
2520 addword (nextword);
2521 baseo = 0;
2522 break;
2523 case 'w':
2524 if (!isword (nextword))
2525 opP->error = _("operand out of range");
2526 addword (nextword);
2527 baseo = 0;
2528 break;
2529 case 'W':
2530 if (!issword (nextword))
2531 opP->error = _("operand out of range");
2532 addword (nextword);
2533 baseo = 0;
2534 break;
2535 case 'l':
2536 addword (nextword >> 16);
2537 addword (nextword);
2538 baseo = 0;
2539 break;
2540
2541 case 'f':
2542 baseo = 2;
2543 outro = 8;
2544 break;
2545 case 'F':
2546 baseo = 4;
2547 outro = 11;
2548 break;
2549 case 'x':
2550 baseo = 6;
2551 outro = 15;
2552 break;
2553 case 'p':
2554 baseo = 6;
2555 outro = -1;
2556 break;
2557 default:
2558 abort ();
2559 }
2560 if (!baseo)
2561 break;
2562
36759679 2563 /* We gotta put out some float. */
252b5132
RH		 2564 if (op (&opP->disp) != O_big)
2565 {
2566 valueT val;
2567 int gencnt;
2568
2569 /* Can other cases happen here? */
2570 if (op (&opP->disp) != O_constant)
2571 abort ();
2572
2573 val = (valueT) offs (&opP->disp);
2574 gencnt = 0;
2575 do
2576 {
2577 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2578 val >>= LITTLENUM_NUMBER_OF_BITS;
2579 ++gencnt;
2580 }
2581 while (val != 0);
2582 offs (&opP->disp) = gencnt;
2583 }
2584 if (offs (&opP->disp) > 0)
2585 {
2586 if (offs (&opP->disp) > baseo)
2587 {
2588 as_warn (_("Bignum too big for %c format; truncated"),
2589 s[1]);
2590 offs (&opP->disp) = baseo;
2591 }
2592 baseo -= offs (&opP->disp);
2593 while (baseo--)
2594 addword (0);
2595 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2596 offs (&opP->disp)--;
2597 --wordp)
2598 addword (*wordp);
2599 break;
2600 }
2601 gen_to_words (words, baseo, (long) outro);
2602 for (wordp = words; baseo--; wordp++)
2603 addword (*wordp);
2604 break;
2605 case DREG:
2606 tmpreg = opP->reg - DATA; /* 0.dreg */
2607 break;
2608 case AREG:
2609 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2610 break;
2611 case AINDR:
2612 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2613 break;
2614 case ADEC:
2615 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2616 break;
2617 case AINC:
2618 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2619 break;
2620 case DISP:
2621
3e602632 2622 nextword = get_num (&opP->disp, 90);
252b5132 2623
580b9172
NC		 2624 /* Convert mode 5 addressing with a zero offset into
2625 mode 2 addressing to reduce the instruction size by a
2626 word. */
2627 if (! isvar (&opP->disp)
2628 && (nextword == 0)
2629 && (opP->disp.size == SIZE_UNSPEC)
2630 && (opP->reg >= ADDR0)
2631 && (opP->reg <= ADDR7))
2632 {
2633 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2634 break;
2635 }
2636
252b5132
RH		 2637 if (opP->reg == PC
2638 && ! isvar (&opP->disp)
2639 && m68k_abspcadd)
2640 {
2641 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2642 opP->disp.exp.X_add_symbol =
2643 section_symbol (absolute_section);
252b5132
RH		 2644 }
2645
36759679 2646 /* Force into index mode. Hope this works. */
252b5132
RH		 2647
2648 /* We do the first bit for 32-bit displacements, and the
2649 second bit for 16 bit ones. It is possible that we
2650 should make the default be WORD instead of LONG, but
2651 I think that'd break GCC, so we put up with a little
2652 inefficiency for the sake of working output. */
2653
2654 if (!issword (nextword)
2655 || (isvar (&opP->disp)
2656 && ((opP->disp.size == SIZE_UNSPEC
2657 && flag_short_refs == 0
2658 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2659 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2660 || opP->disp.size == SIZE_LONG)))
2661 {
2662 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2663 || arch_coldfire_p (current_architecture))
252b5132
RH		 2664 opP->error =
2665 _("displacement too large for this architecture; needs 68020 or higher");
2666 if (opP->reg == PC)
2667 tmpreg = 0x3B; /* 7.3 */
2668 else
2669 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2670 if (isvar (&opP->disp))
2671 {
2672 if (opP->reg == PC)
2673 {
2674 if (opP->disp.size == SIZE_LONG
2675#ifdef OBJ_ELF
2676 /* If the displacement needs pic
2677 relocation it cannot be relaxed. */
2678 || opP->disp.pic_reloc != pic_none
2679#endif
2680 )
2681 {
2682 addword (0x0170);
2683 add_fix ('l', &opP->disp, 1, 2);
2684 }
2685 else
2686 {
2687 add_frag (adds (&opP->disp),
bd17c2c3 2688 SEXT (offs (&opP->disp)),
151337e8 2689 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2690 break;
2691 }
2692 }
2693 else
2694 {
2695 addword (0x0170);
2696 add_fix ('l', &opP->disp, 0, 0);
2697 }
2698 }
2699 else
2700 addword (0x0170);
2701 addword (nextword >> 16);
2702 }
2703 else
2704 {
2705 if (opP->reg == PC)
2706 tmpreg = 0x3A; /* 7.2 */
2707 else
2708 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2709
2710 if (isvar (&opP->disp))
2711 {
2712 if (opP->reg == PC)
2713 {
2714 add_fix ('w', &opP->disp, 1, 0);
2715 }
2716 else
2717 add_fix ('w', &opP->disp, 0, 0);
2718 }
2719 }
2720 addword (nextword);
2721 break;
2722
2723 case POST:
2724 case PRE:
2725 case BASE:
2726 nextword = 0;
3e602632 2727 baseo = get_num (&opP->disp, 90);
252b5132 2728 if (opP->mode == POST || opP->mode == PRE)
3e602632 2729 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2730 /* Figure out the `addressing mode'.
2731 Also turn on the BASE_DISABLE bit, if needed. */
2732 if (opP->reg == PC || opP->reg == ZPC)
2733 {
2734 tmpreg = 0x3b; /* 7.3 */
2735 if (opP->reg == ZPC)
2736 nextword |= 0x80;
2737 }
2738 else if (opP->reg == 0)
2739 {
2740 nextword |= 0x80;
2741 tmpreg = 0x30; /* 6.garbage */
2742 }
2743 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2744 {
2745 nextword |= 0x80;
2746 tmpreg = 0x30 + opP->reg - ZADDR0;
2747 }
2748 else
2749 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2750
2751 siz1 = opP->disp.size;
2752 if (opP->mode == POST || opP->mode == PRE)
2753 siz2 = opP->odisp.size;
2754 else
2755 siz2 = SIZE_UNSPEC;
2756
36759679 2757 /* Index register stuff. */
252b5132
RH		 2758 if (opP->index.reg != 0
2759 && opP->index.reg >= DATA
2760 && opP->index.reg <= ADDR7)
2761 {
2762 nextword |= (opP->index.reg - DATA) << 12;
2763
2764 if (opP->index.size == SIZE_LONG
2765 || (opP->index.size == SIZE_UNSPEC
2766 && m68k_index_width_default == SIZE_LONG))
2767 nextword |= 0x800;
2768
92774660 2769 if ((opP->index.scale != 1
252b5132 2770 && cpu_of_arch (current_architecture) < m68020)
92774660 2771 || (opP->index.scale == 8
3e602632 2772 && (arch_coldfire_p (current_architecture)
6b6e92f4 2773 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2774 {
2775 opP->error =
2776 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2777 }
2778
6da466c7
ILT		 2779 if (arch_coldfire_p (current_architecture)
2780 && opP->index.size == SIZE_WORD)
2781 opP->error = _("invalid index size for coldfire");
2782
252b5132
RH		 2783 switch (opP->index.scale)
2784 {
2785 case 1:
2786 break;
2787 case 2:
2788 nextword |= 0x200;
2789 break;
2790 case 4:
2791 nextword |= 0x400;
2792 break;
2793 case 8:
2794 nextword |= 0x600;
2795 break;
2796 default:
2797 abort ();
2798 }
2799 /* IF its simple,
2800 GET US OUT OF HERE! */
2801
2802 /* Must be INDEX, with an index register. Address
2803 register cannot be ZERO-PC, and either :b was
2804 forced, or we know it will fit. For a 68000 or
2805 68010, force this mode anyways, because the
2806 larger modes aren't supported. */
2807 if (opP->mode == BASE
2808 && ((opP->reg >= ADDR0
2809 && opP->reg <= ADDR7)
2810 || opP->reg == PC))
2811 {
2812 if (siz1 == SIZE_BYTE
2813 || cpu_of_arch (current_architecture) < m68020
6da466c7 2814 || arch_coldfire_p (current_architecture)
252b5132
RH		 2815 || (siz1 == SIZE_UNSPEC
2816 && ! isvar (&opP->disp)
2817 && issbyte (baseo)))
2818 {
2819 nextword += baseo & 0xff;
2820 addword (nextword);
2821 if (isvar (&opP->disp))
2822 {
2823 /* Do a byte relocation. If it doesn't
2824 fit (possible on m68000) let the
2825 fixup processing complain later. */
2826 if (opP->reg == PC)
2827 add_fix ('B', &opP->disp, 1, 1);
2828 else
2829 add_fix ('B', &opP->disp, 0, 0);
2830 }
2831 else if (siz1 != SIZE_BYTE)
2832 {
2833 if (siz1 != SIZE_UNSPEC)
2834 as_warn (_("Forcing byte displacement"));
2835 if (! issbyte (baseo))
2836 opP->error = _("byte displacement out of range");
2837 }
2838
2839 break;
2840 }
2841 else if (siz1 == SIZE_UNSPEC
2842 && opP->reg == PC
2843 && isvar (&opP->disp)
2844 && subs (&opP->disp) == NULL
2845#ifdef OBJ_ELF
2846 /* If the displacement needs pic
2847 relocation it cannot be relaxed. */
2848 && opP->disp.pic_reloc == pic_none
2849#endif
2850 )
2851 {
2852 /* The code in md_convert_frag_1 needs to be
2853 able to adjust nextword. Call frag_grow
2854 to ensure that we have enough space in
2855 the frag obstack to make all the bytes
2856 contiguous. */
2857 frag_grow (14);
8a104df9
KH		 2858 nextword += baseo & 0xff;
2859 addword (nextword);
bd17c2c3
AM		 2860 add_frag (adds (&opP->disp),
2861 SEXT (offs (&opP->disp)),
8a104df9 2862 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2863
2864 break;
8a104df9 2865 }
252b5132
RH		 2866 }
2867 }
2868 else
2869 {
36759679 2870 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2871 if (opP->index.reg >= ZDATA0
2872 && opP->index.reg <= ZDATA7)
2873 nextword |= (opP->index.reg - ZDATA0) << 12;
2874 else if (opP->index.reg >= ZADDR0
2875 || opP->index.reg <= ZADDR7)
2876 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2877 }
2878
2879 /* It isn't simple. */
2880
2881 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2882 || arch_coldfire_p (current_architecture))
252b5132
RH		 2883 opP->error =
2884 _("invalid operand mode for this architecture; needs 68020 or higher");
2885
2886 nextword |= 0x100;
2887 /* If the guy specified a width, we assume that it is
2888 wide enough. Maybe it isn't. If so, we lose. */
2889 switch (siz1)
2890 {
2891 case SIZE_UNSPEC:
2892 if (isvar (&opP->disp)
2893 ? m68k_rel32
2894 : ! issword (baseo))
2895 {
2896 siz1 = SIZE_LONG;
2897 nextword |= 0x30;
2898 }
2899 else if (! isvar (&opP->disp) && baseo == 0)
2900 nextword |= 0x10;
2901 else
2902 {
2903 nextword |= 0x20;
2904 siz1 = SIZE_WORD;
2905 }
2906 break;
2907 case SIZE_BYTE:
2908 as_warn (_(":b not permitted; defaulting to :w"));
2909 /* Fall through. */
2910 case SIZE_WORD:
2911 nextword |= 0x20;
2912 break;
2913 case SIZE_LONG:
2914 nextword |= 0x30;
2915 break;
2916 }
2917
67c1ffbe 2918 /* Figure out inner displacement stuff. */
252b5132
RH		 2919 if (opP->mode == POST || opP->mode == PRE)
2920 {
2921 if (cpu_of_arch (current_architecture) & cpu32)
2922 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2923 switch (siz2)
2924 {
2925 case SIZE_UNSPEC:
2926 if (isvar (&opP->odisp)
2927 ? m68k_rel32
2928 : ! issword (outro))
2929 {
2930 siz2 = SIZE_LONG;
2931 nextword |= 0x3;
2932 }
2933 else if (! isvar (&opP->odisp) && outro == 0)
2934 nextword |= 0x1;
2935 else
2936 {
2937 nextword |= 0x2;
2938 siz2 = SIZE_WORD;
2939 }
2940 break;
2941 case 1:
2942 as_warn (_(":b not permitted; defaulting to :w"));
2943 /* Fall through. */
2944 case 2:
2945 nextword |= 0x2;
2946 break;
2947 case 3:
2948 nextword |= 0x3;
2949 break;
2950 }
2951 if (opP->mode == POST
2952 && (nextword & 0x40) == 0)
2953 nextword |= 0x04;
2954 }
2955 addword (nextword);
2956
2957 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2958 {
2959 if (opP->reg == PC || opP->reg == ZPC)
2960 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2961 else
2962 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2963 }
2964 if (siz1 == SIZE_LONG)
2965 addword (baseo >> 16);
2966 if (siz1 != SIZE_UNSPEC)
2967 addword (baseo);
2968
2969 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2970 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2971 if (siz2 == SIZE_LONG)
2972 addword (outro >> 16);
2973 if (siz2 != SIZE_UNSPEC)
2974 addword (outro);
2975
2976 break;
2977
2978 case ABSL:
3e602632 2979 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2980 switch (opP->disp.size)
2981 {
2982 default:
2983 abort ();
2984 case SIZE_UNSPEC:
2985 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2986 {
2987 tmpreg = 0x38; /* 7.0 */
2988 addword (nextword);
2989 break;
2990 }
252b5132
RH		 2991 if (isvar (&opP->disp)
2992 && !subs (&opP->disp)
2993 && adds (&opP->disp)
2994#ifdef OBJ_ELF
2995 /* If the displacement needs pic relocation it
2996 cannot be relaxed. */
2997 && opP->disp.pic_reloc == pic_none
2998#endif
252b5132
RH		 2999 && !flag_long_jumps
3000 && !strchr ("~%&$?", s[0]))
3001 {
3002 tmpreg = 0x3A; /* 7.2 */
3003 add_frag (adds (&opP->disp),
bd17c2c3 3004 SEXT (offs (&opP->disp)),
151337e8 3005 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 3006 break;
3007 }
36759679 3008 /* Fall through into long. */
252b5132
RH		 3009 case SIZE_LONG:
3010 if (isvar (&opP->disp))
3011 add_fix ('l', &opP->disp, 0, 0);
3012
3013 tmpreg = 0x39;/* 7.1 mode */
3014 addword (nextword >> 16);
3015 addword (nextword);
3016 break;
3017
3018 case SIZE_BYTE:
3019 as_bad (_("unsupported byte value; use a different suffix"));
3020 /* Fall through. */
36759679
NC		 3021
3022 case SIZE_WORD:
252b5132
RH		 3023 if (isvar (&opP->disp))
3024 add_fix ('w', &opP->disp, 0, 0);
3025
3026 tmpreg = 0x38;/* 7.0 mode */
3027 addword (nextword);
3028 break;
3029 }
3030 break;
3031 case CONTROL:
3032 case FPREG:
3033 default:
3034 as_bad (_("unknown/incorrect operand"));
bc805888 3035 /* abort (); */
252b5132 3036 }
fd99574b
NC		 3037
3038 /* If s[0] is '4', then this is for the mac instructions
3039 that can have a trailing_ampersand set. If so, set 0x100
3040 bit on tmpreg so install_gen_operand can check for it and
3041 set the appropriate bit (word2, bit 5). */
3042 if (s[0] == '4')
3043 {
3044 if (opP->trailing_ampersand)
3045 tmpreg |= 0x100;
3046 }
252b5132
RH		 3047 install_gen_operand (s[1], tmpreg);
3048 break;
3049
3050 case '#':
3051 case '^':
3052 switch (s[1])
3053 { /* JF: I hate floating point! */
3054 case 'j':
3055 tmpreg = 70;
3056 break;
3057 case '8':
3058 tmpreg = 20;
3059 break;
3060 case 'C':
3061 tmpreg = 50;
3062 break;
3063 case '3':
3064 default:
3e602632 3065 tmpreg = 90;
252b5132
RH		 3066 break;
3067 }
3068 tmpreg = get_num (&opP->disp, tmpreg);
3069 if (isvar (&opP->disp))
3070 add_fix (s[1], &opP->disp, 0, 0);
3071 switch (s[1])
3072 {
3073 case 'b': /* Danger: These do no check for
3074 certain types of overflow.
3075 user beware! */
3076 if (!isbyte (tmpreg))
3077 opP->error = _("out of range");
3078 insop (tmpreg, opcode);
3079 if (isvar (&opP->disp))
3080 the_ins.reloc[the_ins.nrel - 1].n =
3081 (opcode->m_codenum) * 2 + 1;
3082 break;
3083 case 'B':
3084 if (!issbyte (tmpreg))
3085 opP->error = _("out of range");
3086 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3087 if (isvar (&opP->disp))
3088 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3089 break;
3090 case 'w':
3091 if (!isword (tmpreg))
3092 opP->error = _("out of range");
3093 insop (tmpreg, opcode);
3094 if (isvar (&opP->disp))
3095 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3096 break;
3097 case 'W':
3098 if (!issword (tmpreg))
3099 opP->error = _("out of range");
3100 insop (tmpreg, opcode);
3101 if (isvar (&opP->disp))
3102 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3103 break;
3104 case 'l':
3105 /* Because of the way insop works, we put these two out
3106 backwards. */
3107 insop (tmpreg, opcode);
3108 insop (tmpreg >> 16, opcode);
3109 if (isvar (&opP->disp))
3110 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3111 break;
3112 case '3':
3113 tmpreg &= 0xFF;
3114 case '8':
3115 case 'C':
3116 case 'j':
3117 install_operand (s[1], tmpreg);
3118 break;
3119 default:
3120 abort ();
3121 }
3122 break;
3123
3124 case '+':
3125 case '-':
3126 case 'A':
3127 case 'a':
3128 install_operand (s[1], opP->reg - ADDR);
3129 break;
3130
3131 case 'B':
3e602632 3132 tmpreg = get_num (&opP->disp, 90);
9a2e615a 3133
252b5132
RH		 3134 switch (s[1])
3135 {
3136 case 'B':
8390138c 3137 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 3138 break;
3139 case 'W':
3140 add_fix ('w', &opP->disp, 1, 0);
3141 addword (0);
3142 break;
3143 case 'L':
3144 long_branch:
151337e8 3145 the_ins.opcode[0] |= 0xff;
252b5132
RH		 3146 add_fix ('l', &opP->disp, 1, 0);
3147 addword (0);
3148 addword (0);
3149 break;
9a2e615a
NS		 3150 case 'g': /* Conditional branch */
3151 have_disp = HAVE_LONG_CALL (current_architecture);
3152 goto var_branch;
3153
3154 case 'b': /* Unconditional branch */
3155 have_disp = HAVE_LONG_BRANCH (current_architecture);
cac27205 3156 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
9a2e615a
NS		 3157 goto var_branch;
3158
3159 case 's': /* Unconditional subroutine */
3160 have_disp = HAVE_LONG_CALL (current_architecture);
3161
3162 var_branch:
3163 if (subs (&opP->disp) /* We can't relax it. */
252b5132 3164#ifdef OBJ_ELF
9a2e615a
NS		 3165 /* If the displacement needs pic relocation it cannot be
3166 relaxed. */
3167 || opP->disp.pic_reloc != pic_none
252b5132 3168#endif
9a2e615a
NS		 3169 || 0)
3170 {
3171 if (!have_disp)
3172 as_warn (_("Can't use long branches on this architecture"));
3173 goto long_branch;
3174 }
3175
252b5132 3176 /* This could either be a symbol, or an absolute
151337e8
NC		 3177 address. If it's an absolute address, turn it into
3178 an absolute jump right here and keep it out of the
3179 relaxer. */
3180 if (adds (&opP->disp) == 0)
3181 {
3182 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 3183 the_ins.opcode[0] = 0x4EF9;
151337e8 3184 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 3185 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 3186 else /* jCC */
3187 {
3188 the_ins.opcode[0] ^= 0x0100;
3189 the_ins.opcode[0] |= 0x0006;
18566f55 3190 addword (0x4EF9);
151337e8
NC		 3191 }
3192 add_fix ('l', &opP->disp, 0, 0);
3193 addword (0);
3194 addword (0);
3195 break;
3196 }
3197
3198 /* Now we know it's going into the relaxer. Now figure
3199 out which mode. We try in this order of preference:
3200 long branch, absolute jump, byte/word branches only. */
9a2e615a 3201 if (have_disp)
bd17c2c3
AM		 3202 add_frag (adds (&opP->disp),
3203 SEXT (offs (&opP->disp)),
151337e8
NC		 3204 TAB (BRANCHBWL, SZ_UNDEF));
3205 else if (! flag_keep_pcrel)
3206 {
3207 if ((the_ins.opcode[0] == 0x6000)
3208 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3209 add_frag (adds (&opP->disp),
3210 SEXT (offs (&opP->disp)),
151337e8
NC		 3211 TAB (BRABSJUNC, SZ_UNDEF));
3212 else
bd17c2c3
AM		 3213 add_frag (adds (&opP->disp),
3214 SEXT (offs (&opP->disp)),
151337e8
NC		 3215 TAB (BRABSJCOND, SZ_UNDEF));
3216 }
252b5132 3217 else
bd17c2c3
AM		 3218 add_frag (adds (&opP->disp),
3219 SEXT (offs (&opP->disp)),
cac27205
NC		 3220 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3221 : TAB (BRANCHBW, SZ_UNDEF)));
252b5132
RH		 3222 break;
3223 case 'w':
3224 if (isvar (&opP->disp))
3225 {
151337e8
NC		 3226 /* Check for DBcc instructions. We can relax them,
3227 but only if we have long branches and/or absolute
3228 jumps. */
3229 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3230 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3231 || ! flag_keep_pcrel))
252b5132 3232 {
151337e8 3233 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3234 add_frag (adds (&opP->disp),
3235 SEXT (offs (&opP->disp)),
151337e8
NC		 3236 TAB (DBCCLBR, SZ_UNDEF));
3237 else
bd17c2c3
AM		 3238 add_frag (adds (&opP->disp),
3239 SEXT (offs (&opP->disp)),
151337e8 3240 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3241 break;
3242 }
252b5132
RH		 3243 add_fix ('w', &opP->disp, 1, 0);
3244 }
3245 addword (0);
3246 break;
36759679 3247 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3248 add_fix ('l', &opP->disp, 1, 0);
3249 addword (0);
3250 addword (0);
3251 break;
36759679 3252 case 'c': /* Var size Coprocesssor branches. */
151337e8 3253 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3254 {
252b5132
RH		 3255 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3256 add_fix ('l', &opP->disp, 1, 0);
3257 addword (0);
3258 addword (0);
3259 }
151337e8 3260 else
bd17c2c3
AM		 3261 add_frag (adds (&opP->disp),
3262 SEXT (offs (&opP->disp)),
151337e8 3263 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3264 break;
3265 default:
3266 abort ();
3267 }
3268 break;
3269
36759679 3270 case 'C': /* Ignore it. */
252b5132
RH		 3271 break;
3272
36759679 3273 case 'd': /* JF this is a kludge. */
252b5132 3274 install_operand ('s', opP->reg - ADDR);
3e602632 3275 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3276 if (!issword (tmpreg))
3277 {
3278 as_warn (_("Expression out of range, using 0"));
3279 tmpreg = 0;
3280 }
3281 addword (tmpreg);
3282 break;
3283
3284 case 'D':
3285 install_operand (s[1], opP->reg - DATA);
3286 break;
3287
fd99574b
NC		 3288 case 'e': /* EMAC ACCx, reg/reg. */
3289 install_operand (s[1], opP->reg - ACC);
3290 break;
3291
36759679 3292 case 'E': /* Ignore it. */
6da466c7
ILT		 3293 break;
3294
252b5132
RH		 3295 case 'F':
3296 install_operand (s[1], opP->reg - FP0);
3297 break;
3298
fd99574b
NC		 3299 case 'g': /* EMAC ACCEXTx. */
3300 install_operand (s[1], opP->reg - ACCEXT01);
3301 break;
3302
36759679 3303 case 'G': /* Ignore it. */
6da466c7
ILT		 3304 case 'H':
3305 break;
3306
252b5132
RH		 3307 case 'I':
3308 tmpreg = opP->reg - COP0;
3309 install_operand (s[1], tmpreg);
3310 break;
3311
fd99574b
NC		 3312 case 'i': /* MAC/EMAC scale factor. */
3313 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3314 break;
3315
36759679 3316 case 'J': /* JF foo. */
252b5132
RH		 3317 switch (opP->reg)
3318 {
3319 case SFC:
3320 tmpreg = 0x000;
3321 break;
3322 case DFC:
3323 tmpreg = 0x001;
3324 break;
3325 case CACR:
3326 tmpreg = 0x002;
3327 break;
3328 case TC:
a8e24a56 3329 case ASID:
252b5132
RH		 3330 tmpreg = 0x003;
3331 break;
3e602632 3332 case ACR0:
252b5132
RH		 3333 case ITT0:
3334 tmpreg = 0x004;
3335 break;
3e602632 3336 case ACR1:
252b5132
RH		 3337 case ITT1:
3338 tmpreg = 0x005;
3339 break;
3e602632 3340 case ACR2:
252b5132
RH		 3341 case DTT0:
3342 tmpreg = 0x006;
3343 break;
3e602632 3344 case ACR3:
252b5132
RH		 3345 case DTT1:
3346 tmpreg = 0x007;
3347 break;
3348 case BUSCR:
a8e24a56 3349 case MMUBAR:
252b5132
RH		 3350 tmpreg = 0x008;
3351 break;
0d999f33
MK		 3352 case RGPIOBAR:
3353 tmpreg = 0x009;
3354 break;
3355 case ACR4:
3356 case ACR5:
3357 case ACR6:
3358 case ACR7:
3359 tmpreg = 0x00c + (opP->reg - ACR4);
3360 break;
252b5132
RH		 3361
3362 case USP:
3363 tmpreg = 0x800;
3364 break;
3365 case VBR:
3366 tmpreg = 0x801;
3367 break;
3368 case CAAR:
87298967 3369 case CPUCR:
252b5132
RH		 3370 tmpreg = 0x802;
3371 break;
3372 case MSP:
3373 tmpreg = 0x803;
3374 break;
3375 case ISP:
3376 tmpreg = 0x804;
3377 break;
3378 case MMUSR:
3379 tmpreg = 0x805;
3380 break;
3381 case URP:
3382 tmpreg = 0x806;
3383 break;
3384 case SRP:
3385 tmpreg = 0x807;
3386 break;
3387 case PCR:
3388 tmpreg = 0x808;
3389 break;
3390 case ROMBAR:
a8e24a56 3391 case ROMBAR0:
252b5132
RH		 3392 tmpreg = 0xC00;
3393 break;
3e602632
NC		 3394 case ROMBAR1:
3395 tmpreg = 0xC01;
3396 break;
3397 case FLASHBAR:
252b5132 3398 case RAMBAR0:
78336706 3399 case RAMBAR_ALT:
252b5132
RH		 3400 tmpreg = 0xC04;
3401 break;
3e602632 3402 case RAMBAR:
252b5132
RH		 3403 case RAMBAR1:
3404 tmpreg = 0xC05;
3405 break;
3e602632
NC		 3406 case MPCR:
3407 tmpreg = 0xC0C;
3408 break;
3409 case EDRAMBAR:
3410 tmpreg = 0xC0D;
3411 break;
3412 case MBAR0:
e80e0390 3413 case MBAR2:
3e602632
NC		 3414 case SECMBAR:
3415 tmpreg = 0xC0E;
3416 break;
3417 case MBAR1:
252b5132
RH		 3418 case MBAR:
3419 tmpreg = 0xC0F;
3420 break;
3e602632
NC		 3421 case PCR1U0:
3422 tmpreg = 0xD02;
3423 break;
3424 case PCR1L0:
3425 tmpreg = 0xD03;
3426 break;
3427 case PCR2U0:
3428 tmpreg = 0xD04;
3429 break;
3430 case PCR2L0:
3431 tmpreg = 0xD05;
3432 break;
3433 case PCR3U0:
3434 tmpreg = 0xD06;
3435 break;
3436 case PCR3L0:
3437 tmpreg = 0xD07;
3438 break;
3439 case PCR1L1:
3440 tmpreg = 0xD0A;
3441 break;
3442 case PCR1U1:
3443 tmpreg = 0xD0B;
3444 break;
3445 case PCR2L1:
3446 tmpreg = 0xD0C;
3447 break;
3448 case PCR2U1:
3449 tmpreg = 0xD0D;
3450 break;
3451 case PCR3L1:
3452 tmpreg = 0xD0E;
3453 break;
3454 case PCR3U1:
3455 tmpreg = 0xD0F;
3456 break;
f7ec513b
KH		 3457 case CAC:
3458 tmpreg = 0xFFE;
3459 break;
d0fa1372 3460 case MBO:
f7ec513b
KH		 3461 tmpreg = 0xFFF;
3462 break;
252b5132
RH		 3463 default:
3464 abort ();
3465 }
3466 install_operand (s[1], tmpreg);
3467 break;
3468
3469 case 'k':
3470 tmpreg = get_num (&opP->disp, 55);
3471 install_operand (s[1], tmpreg & 0x7f);
3472 break;
3473
3474 case 'l':
3475 tmpreg = opP->mask;
3476 if (s[1] == 'w')
3477 {
3478 if (tmpreg & 0x7FF0000)
3479 as_bad (_("Floating point register in register list"));
3480 insop (reverse_16_bits (tmpreg), opcode);
3481 }
3482 else
3483 {
3484 if (tmpreg & 0x700FFFF)
3485 as_bad (_("Wrong register in floating-point reglist"));
3486 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3487 }
3488 break;
3489
3490 case 'L':
3491 tmpreg = opP->mask;
3492 if (s[1] == 'w')
3493 {
3494 if (tmpreg & 0x7FF0000)
3495 as_bad (_("Floating point register in register list"));
3496 insop (tmpreg, opcode);
3497 }
3498 else if (s[1] == '8')
3499 {
3500 if (tmpreg & 0x0FFFFFF)
3501 as_bad (_("incorrect register in reglist"));
3502 install_operand (s[1], tmpreg >> 24);
3503 }
3504 else
3505 {
3506 if (tmpreg & 0x700FFFF)
3507 as_bad (_("wrong register in floating-point reglist"));
3508 else
3509 install_operand (s[1], tmpreg >> 16);
3510 }
3511 break;
3512
3513 case 'M':
3514 install_operand (s[1], get_num (&opP->disp, 60));
3515 break;
3516
3517 case 'O':
3518 tmpreg = ((opP->mode == DREG)
8fce3f5e 3519 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3520 : (get_num (&opP->disp, 40) & 0x1F));
3521 install_operand (s[1], tmpreg);
3522 break;
3523
3524 case 'Q':
3525 tmpreg = get_num (&opP->disp, 10);
3526 if (tmpreg == 8)
3527 tmpreg = 0;
3528 install_operand (s[1], tmpreg);
3529 break;
3530
3531 case 'R':
3532 /* This depends on the fact that ADDR registers are eight
3533 more than their corresponding DATA regs, so the result
36759679 3534 will have the ADDR_REG bit set. */
252b5132
RH		 3535 install_operand (s[1], opP->reg - DATA);
3536 break;
3537
3538 case 'r':
3539 if (opP->mode == AINDR)
3540 install_operand (s[1], opP->reg - DATA);
3541 else
3542 install_operand (s[1], opP->index.reg - DATA);
3543 break;
3544
3545 case 's':
3546 if (opP->reg == FPI)
3547 tmpreg = 0x1;
3548 else if (opP->reg == FPS)
3549 tmpreg = 0x2;
3550 else if (opP->reg == FPC)
3551 tmpreg = 0x4;
3552 else
3553 abort ();
3554 install_operand (s[1], tmpreg);
3555 break;
3556
36759679 3557 case 'S': /* Ignore it. */
252b5132
RH		 3558 break;
3559
3560 case 'T':
3561 install_operand (s[1], get_num (&opP->disp, 30));
3562 break;
3563
36759679 3564 case 'U': /* Ignore it. */
252b5132
RH		 3565 break;
3566
3567 case 'c':
3568 switch (opP->reg)
3569 {
3570 case NC:
3571 tmpreg = 0;
3572 break;
3573 case DC:
3574 tmpreg = 1;
3575 break;
3576 case IC:
3577 tmpreg = 2;
3578 break;
3579 case BC:
3580 tmpreg = 3;
3581 break;
3582 default:
3583 as_fatal (_("failed sanity check"));
36759679 3584 } /* switch on cache token. */
252b5132
RH		 3585 install_operand (s[1], tmpreg);
3586 break;
3587#ifndef NO_68851
92774660 3588 /* JF: These are out of order, I fear. */
252b5132
RH		 3589 case 'f':
3590 switch (opP->reg)
3591 {
3592 case SFC:
3593 tmpreg = 0;
3594 break;
3595 case DFC:
3596 tmpreg = 1;
3597 break;
3598 default:
3599 abort ();
3600 }
3601 install_operand (s[1], tmpreg);
3602 break;
3603
3604 case '0':
3605 case '1':
3606 case '2':
3607 switch (opP->reg)
3608 {
3609 case TC:
3610 tmpreg = 0;
3611 break;
3612 case CAL:
3613 tmpreg = 4;
3614 break;
3615 case VAL:
3616 tmpreg = 5;
3617 break;
3618 case SCC:
3619 tmpreg = 6;
3620 break;
3621 case AC:
3622 tmpreg = 7;
3623 break;
3624 default:
3625 abort ();
3626 }
3627 install_operand (s[1], tmpreg);
3628 break;
3629
3630 case 'V':
3631 if (opP->reg == VAL)
3632 break;
3633 abort ();
3634
3635 case 'W':
3636 switch (opP->reg)
3637 {
3638 case DRP:
3639 tmpreg = 1;
3640 break;
3641 case SRP:
3642 tmpreg = 2;
3643 break;
3644 case CRP:
3645 tmpreg = 3;
3646 break;
3647 default:
3648 abort ();
3649 }
3650 install_operand (s[1], tmpreg);
3651 break;
3652
3653 case 'X':
3654 switch (opP->reg)
3655 {
3656 case BAD:
3657 case BAD + 1:
3658 case BAD + 2:
3659 case BAD + 3:
3660 case BAD + 4:
3661 case BAD + 5:
3662 case BAD + 6:
3663 case BAD + 7:
3664 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3665 break;
3666
3667 case BAC:
3668 case BAC + 1:
3669 case BAC + 2:
3670 case BAC + 3:
3671 case BAC + 4:
3672 case BAC + 5:
3673 case BAC + 6:
3674 case BAC + 7:
3675 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3676 break;
3677
3678 default:
3679 abort ();
3680 }
3681 install_operand (s[1], tmpreg);
3682 break;
3683 case 'Y':
3684 know (opP->reg == PSR);
3685 break;
3686 case 'Z':
3687 know (opP->reg == PCSR);
3688 break;
3689#endif /* m68851 */
3690 case '3':
3691 switch (opP->reg)
3692 {
3693 case TT0:
3694 tmpreg = 2;
3695 break;
3696 case TT1:
3697 tmpreg = 3;
3698 break;
3699 default:
3700 abort ();
3701 }
3702 install_operand (s[1], tmpreg);
3703 break;
3704 case 't':
3705 tmpreg = get_num (&opP->disp, 20);
3706 install_operand (s[1], tmpreg);
3707 break;
36759679 3708 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3709 if (isvar (&opP->disp))
3710 add_fix ('l', &opP->disp, 0, 0);
3e602632 3711 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3712 addword (tmpreg >> 16);
3713 addword (tmpreg & 0xFFFF);
3714 break;
6da466c7
ILT		 3715 case 'u':
3716 install_operand (s[1], opP->reg - DATA0L);
3717 opP->reg -= (DATA0L);
36759679 3718 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3719 break;
3e602632
NC		 3720 case 'x':
3721 tmpreg = get_num (&opP->disp, 80);
3722 if (tmpreg == -1)
3723 tmpreg = 0;
3724 install_operand (s[1], tmpreg);
3725 break;
afa2158f
NS		 3726 case 'j':
3727 tmpreg = get_num (&opP->disp, 10);
3728 install_operand (s[1], tmpreg - 1);
3729 break;
3730 case 'K':
3731 tmpreg = get_num (&opP->disp, 65);
3732 install_operand (s[1], tmpreg);
3733 break;
252b5132
RH		 3734 default:
3735 abort ();
3736 }
3737 }
3738
3739 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3740 instruction, ready to be emitted. . . */
252b5132
RH		 3741}
3742
3743static int
31302357 3744reverse_16_bits (int in)
252b5132
RH		 3745{
3746 int out = 0;
3747 int n;
3748
3749 static int mask[16] =
3750 {
3751 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3752 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3753 };
3754 for (n = 0; n < 16; n++)
3755 {
3756 if (in & mask[n])
3757 out |= mask[15 - n];
3758 }
3759 return out;
3760} /* reverse_16_bits() */
3761
3762static int
31302357 3763reverse_8_bits (int in)
252b5132
RH		 3764{
3765 int out = 0;
3766 int n;
3767
3768 static int mask[8] =
3769 {
3770 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3771 };
3772
3773 for (n = 0; n < 8; n++)
3774 {
3775 if (in & mask[n])
3776 out |= mask[7 - n];
3777 }
3778 return out;
3779} /* reverse_8_bits() */
3780
cac27205
NC		 3781/* Cause an extra frag to be generated here, inserting up to
3782 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3783 generated; its primary type is rs_machine_dependent.
252b5132
RH		 3784
3785 The TYPE parameter is also used by md_convert_frag_1 and
3786 md_estimate_size_before_relax. The appropriate type of fixup will
3787 be emitted by md_convert_frag_1.
3788
3789 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3790static void
31302357 3791install_operand (int mode, int val)
252b5132
RH		 3792{
3793 switch (mode)
3794 {
3795 case 's':
36759679 3796 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3797 break;
3798 case 'd':
3799 the_ins.opcode[0] |= val << 9;
3800 break;
afa2158f
NS		 3801 case 'E':
3802 the_ins.opcode[1] |= val << 9;
3803 break;
252b5132
RH		 3804 case '1':
3805 the_ins.opcode[1] |= val << 12;
3806 break;
3807 case '2':
3808 the_ins.opcode[1] |= val << 6;
3809 break;
3810 case '3':
3811 the_ins.opcode[1] |= val;
3812 break;
3813 case '4':
3814 the_ins.opcode[2] |= val << 12;
3815 break;
3816 case '5':
3817 the_ins.opcode[2] |= val << 6;
3818 break;
3819 case '6':
3820 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3821 three words long! */
3822 the_ins.numo++;
3823 the_ins.opcode[2] |= val;
3824 break;
3825 case '7':
3826 the_ins.opcode[1] |= val << 7;
3827 break;
3828 case '8':
3829 the_ins.opcode[1] |= val << 10;
3830 break;
3831#ifndef NO_68851
3832 case '9':
3833 the_ins.opcode[1] |= val << 5;
3834 break;
3835#endif
3836
3837 case 't':
3838 the_ins.opcode[1] |= (val << 10) | (val << 7);
3839 break;
3840 case 'D':
3841 the_ins.opcode[1] |= (val << 12) | val;
3842 break;
3843 case 'g':
3844 the_ins.opcode[0] |= val = 0xff;
3845 break;
3846 case 'i':
3847 the_ins.opcode[0] |= val << 9;
3848 break;
3849 case 'C':
3850 the_ins.opcode[1] |= val;
3851 break;
3852 case 'j':
3853 the_ins.opcode[1] |= val;
36759679 3854 the_ins.numo++; /* What a hack. */
252b5132
RH		 3855 break;
3856 case 'k':
3857 the_ins.opcode[1] |= val << 4;
3858 break;
3859 case 'b':
3860 case 'w':
3861 case 'W':
3862 case 'l':
3863 break;
3864 case 'e':
3865 the_ins.opcode[0] |= (val << 6);
3866 break;
3867 case 'L':
3868 the_ins.opcode[1] = (val >> 16);
3869 the_ins.opcode[2] = val & 0xffff;
3870 break;
6da466c7
ILT		 3871 case 'm':
3872 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3873 the_ins.opcode[0] |= ((val & 0x7) << 9);
3874 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3875 break;
fd99574b 3876 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3877 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3878 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3879 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3880 break;
fd99574b 3881 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3882 the_ins.opcode[1] |= val << 12;
3883 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3884 break;
fd99574b 3885 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3886 the_ins.opcode[0] |= (val & 0xF);
3887 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3888 break;
fd99574b 3889 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3890 the_ins.opcode[1] |= (val & 0xF);
3891 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3892 break;
3893 case 'h':
3894 the_ins.opcode[1] |= ((val != 1) << 10);
3895 break;
fd99574b
NC		 3896 case 'F':
3897 the_ins.opcode[0] |= ((val & 0x3) << 9);
3898 break;
3899 case 'f':
3900 the_ins.opcode[0] |= ((val & 0x3) << 0);
3901 break;
be8c092b 3902 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3903 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3904 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3905 break;
be8c092b 3906 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3907 the_ins.opcode[0] |= ((val & 0x1) << 7);
3908 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3909 break;
3910 case 'I':
3911 the_ins.opcode[1] |= ((val & 0x3) << 9);
3912 break;
3913 case ']':
3914 the_ins.opcode[0] |= (val & 0x1) <<10;
3915 break;
252b5132
RH		 3916 case 'c':
3917 default:
3918 as_fatal (_("failed sanity check."));
3919 }
6b6e92f4 3920}
252b5132
RH		 3921
3922static void
31302357 3923install_gen_operand (int mode, int val)
252b5132
RH		 3924{
3925 switch (mode)
3926 {
fd99574b
NC		 3927 case '/': /* Special for mask loads for mac/msac insns with
3928 possible mask; trailing_ampersend set in bit 8. */
3929 the_ins.opcode[0] |= (val & 0x3f);
3930 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3931 break;
252b5132
RH		 3932 case 's':
3933 the_ins.opcode[0] |= val;
3934 break;
3935 case 'd':
3936 /* This is a kludge!!! */
3937 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3938 break;
3939 case 'b':
3940 case 'w':
3941 case 'l':
3942 case 'f':
3943 case 'F':
3944 case 'x':
3945 case 'p':
3946 the_ins.opcode[0] |= val;
3947 break;
36759679 3948 /* more stuff goes here. */
252b5132
RH		 3949 default:
3950 as_fatal (_("failed sanity check."));
3951 }
6b6e92f4 3952}
252b5132 3953
6b6e92f4
NC		 3954/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3955 then deal with the bitfield hack. */
252b5132
RH		 3956
3957static char *
31302357 3958crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3959{
3960 register int parens;
3961 register int c;
3962 register char *beg_str;
3963 int inquote = 0;
3964
3965 if (!str)
3966 {
3967 return str;
3968 }
3969 beg_str = str;
3970 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3971 {
3972 if (! inquote)
3973 {
3974 if (*str == '(')
3975 parens++;
3976 else if (*str == ')')
3977 {
3978 if (!parens)
36759679 3979 { /* ERROR. */
252b5132
RH		 3980 opP->error = _("Extra )");
3981 return str;
3982 }
3983 --parens;
3984 }
3985 }
3986 if (flag_mri && *str == '\'')
3987 inquote = ! inquote;
3988 }
3989 if (!*str && parens)
36759679 3990 { /* ERROR. */
252b5132
RH		 3991 opP->error = _("Missing )");
3992 return str;
3993 }
3994 c = *str;
3995 *str = '\0';
3996 if (m68k_ip_op (beg_str, opP) != 0)
3997 {
3998 *str = c;
3999 return str;
4000 }
4001 *str = c;
4002 if (c == '}')
36759679 4003 c = *++str; /* JF bitfield hack. */
252b5132
RH		 4004 if (c)
4005 {
4006 c = *++str;
4007 if (!c)
4008 as_bad (_("Missing operand"));
4009 }
4010
4011 /* Detect MRI REG symbols and convert them to REGLSTs. */
4012 if (opP->mode == CONTROL && (int)opP->reg < 0)
4013 {
4014 opP->mode = REGLST;
4015 opP->mask = ~(int)opP->reg;
4016 opP->reg = 0;
4017 }
4018
4019 return str;
4020}
4021
4022/* This is the guts of the machine-dependent assembler. STR points to a
4023 machine dependent instruction. This function is supposed to emit
4024 the frags/bytes it assembles to.
4025 */
4026
4027static void
31302357 4028insert_reg (const char *regname, int regnum)
252b5132
RH		 4029{
4030 char buf[100];
4031 int i;
4032
4033#ifdef REGISTER_PREFIX
4034 if (!flag_reg_prefix_optional)
4035 {
4036 buf[0] = REGISTER_PREFIX;
4037 strcpy (buf + 1, regname);
4038 regname = buf;
4039 }
4040#endif
4041
4042 symbol_table_insert (symbol_new (regname, reg_section, regnum,
4043 &zero_address_frag));
4044
4045 for (i = 0; regname[i]; i++)
3882b010 4046 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 4047 buf[i] = '\0';
4048
4049 symbol_table_insert (symbol_new (buf, reg_section, regnum,
4050 &zero_address_frag));
4051}
4052
4053struct init_entry
4054 {
4055 const char *name;
4056 int number;
4057 };
4058
4059static const struct init_entry init_table[] =
4060{
4061 { "d0", DATA0 },
4062 { "d1", DATA1 },
4063 { "d2", DATA2 },
4064 { "d3", DATA3 },
4065 { "d4", DATA4 },
4066 { "d5", DATA5 },
4067 { "d6", DATA6 },
4068 { "d7", DATA7 },
4069 { "a0", ADDR0 },
4070 { "a1", ADDR1 },
4071 { "a2", ADDR2 },
4072 { "a3", ADDR3 },
4073 { "a4", ADDR4 },
4074 { "a5", ADDR5 },
4075 { "a6", ADDR6 },
4076 { "fp", ADDR6 },
4077 { "a7", ADDR7 },
4078 { "sp", ADDR7 },
4079 { "ssp", ADDR7 },
4080 { "fp0", FP0 },
4081 { "fp1", FP1 },
4082 { "fp2", FP2 },
4083 { "fp3", FP3 },
4084 { "fp4", FP4 },
4085 { "fp5", FP5 },
4086 { "fp6", FP6 },
4087 { "fp7", FP7 },
4088 { "fpi", FPI },
4089 { "fpiar", FPI },
4090 { "fpc", FPI },
4091 { "fps", FPS },
4092 { "fpsr", FPS },
4093 { "fpc", FPC },
4094 { "fpcr", FPC },
4095 { "control", FPC },
4096 { "status", FPS },
4097 { "iaddr", FPI },
4098
4099 { "cop0", COP0 },
4100 { "cop1", COP1 },
4101 { "cop2", COP2 },
4102 { "cop3", COP3 },
4103 { "cop4", COP4 },
4104 { "cop5", COP5 },
4105 { "cop6", COP6 },
4106 { "cop7", COP7 },
4107 { "pc", PC },
4108 { "zpc", ZPC },
4109 { "sr", SR },
4110
4111 { "ccr", CCR },
4112 { "cc", CCR },
4113
6da466c7 4114 { "acc", ACC },
fd99574b
NC		 4115 { "acc0", ACC },
4116 { "acc1", ACC1 },
4117 { "acc2", ACC2 },
4118 { "acc3", ACC3 },
4119 { "accext01", ACCEXT01 },
4120 { "accext23", ACCEXT23 },
6da466c7
ILT		 4121 { "macsr", MACSR },
4122 { "mask", MASK },
4123
36759679
NC		 4124 /* Control registers. */
4125 { "sfc", SFC }, /* Source Function Code. */
252b5132 4126 { "sfcr", SFC },
36759679 4127 { "dfc", DFC }, /* Destination Function Code. */
252b5132 4128 { "dfcr", DFC },
36759679
NC		 4129 { "cacr", CACR }, /* Cache Control Register. */
4130 { "caar", CAAR }, /* Cache Address Register. */
87298967 4131 { "cpucr", CPUCR }, /* CPU Control Register. */
252b5132 4132
36759679
NC		 4133 { "usp", USP }, /* User Stack Pointer. */
4134 { "vbr", VBR }, /* Vector Base Register. */
4135 { "msp", MSP }, /* Master Stack Pointer. */
4136 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 4137
36759679
NC		 4138 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4139 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4140 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4141 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 4142
4143 /* 68ec040 versions of same */
36759679
NC		 4144 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4145 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4146 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4147 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 4148
a8e24a56 4149 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 4150 manual indicated that the order is 2,3,0,1, but Ken Rose
4151 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 4152 { "acr0", ACR0 }, /* Access Control Unit 0. */
4153 { "acr1", ACR1 }, /* Access Control Unit 1. */
4154 { "acr2", ACR2 }, /* Access Control Unit 2. */
4155 { "acr3", ACR3 }, /* Access Control Unit 3. */
0d999f33
MK		 4156 { "acr4", ACR4 }, /* Access Control Unit 4. */
4157 { "acr5", ACR5 }, /* Access Control Unit 5. */
4158 { "acr6", ACR6 }, /* Access Control Unit 6. */
4159 { "acr7", ACR7 }, /* Access Control Unit 7. */
252b5132 4160
36759679 4161 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 4162 { "tcr", TC },
a8e24a56 4163 { "asid", ASID },
252b5132 4164
36759679
NC		 4165 { "mmusr", MMUSR }, /* MMU Status Register. */
4166 { "srp", SRP }, /* User Root Pointer. */
4167 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 4168
4169 { "buscr", BUSCR },
a8e24a56 4170 { "mmubar", MMUBAR },
252b5132
RH		 4171 { "pcr", PCR },
4172
36759679
NC		 4173 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4174 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4175 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4176 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 4177
4178 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4179 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 4180 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 4181 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4182 { "mpcr", MPCR }, /* mcfv4e registers. */
4183 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4184 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4185 { "asid", TC }, /* mcfv4e registers. */
4186 { "mmubar", BUSCR }, /* mcfv4e registers. */
4187 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4188 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4189 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4190 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4191 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4192 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4193 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4194 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4195 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4196 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4197 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4198 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4199
4200 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4201 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 4202
4203 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b 4204
0d999f33
MK		 4205 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4206
f7ec513b 4207 { "cac", CAC }, /* fido registers. */
d0fa1372
KH		 4208 { "mbb", MBO }, /* fido registers (obsolete). */
4209 { "mbo", MBO }, /* fido registers. */
36759679 4210 /* End of control registers. */
252b5132
RH		 4211
4212 { "ac", AC },
4213 { "bc", BC },
4214 { "cal", CAL },
4215 { "crp", CRP },
4216 { "drp", DRP },
4217 { "pcsr", PCSR },
4218 { "psr", PSR },
4219 { "scc", SCC },
4220 { "val", VAL },
4221 { "bad0", BAD0 },
4222 { "bad1", BAD1 },
4223 { "bad2", BAD2 },
4224 { "bad3", BAD3 },
4225 { "bad4", BAD4 },
4226 { "bad5", BAD5 },
4227 { "bad6", BAD6 },
4228 { "bad7", BAD7 },
4229 { "bac0", BAC0 },
4230 { "bac1", BAC1 },
4231 { "bac2", BAC2 },
4232 { "bac3", BAC3 },
4233 { "bac4", BAC4 },
4234 { "bac5", BAC5 },
4235 { "bac6", BAC6 },
4236 { "bac7", BAC7 },
4237
4238 { "ic", IC },
4239 { "dc", DC },
4240 { "nc", NC },
4241
4242 { "tt0", TT0 },
4243 { "tt1", TT1 },
36759679 4244 /* 68ec030 versions of same. */
252b5132
RH		 4245 { "ac0", TT0 },
4246 { "ac1", TT1 },
36759679 4247 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4248 { "acusr", PSR },
4249
4250 /* Suppressed data and address registers. */
4251 { "zd0", ZDATA0 },
4252 { "zd1", ZDATA1 },
4253 { "zd2", ZDATA2 },
4254 { "zd3", ZDATA3 },
4255 { "zd4", ZDATA4 },
4256 { "zd5", ZDATA5 },
4257 { "zd6", ZDATA6 },
4258 { "zd7", ZDATA7 },
4259 { "za0", ZADDR0 },
4260 { "za1", ZADDR1 },
4261 { "za2", ZADDR2 },
4262 { "za3", ZADDR3 },
4263 { "za4", ZADDR4 },
4264 { "za5", ZADDR5 },
4265 { "za6", ZADDR6 },
4266 { "za7", ZADDR7 },
4267
92774660 4268 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4269 { "d0l", DATA0L },
4270 { "d1l", DATA1L },
4271 { "d2l", DATA2L },
4272 { "d3l", DATA3L },
4273 { "d4l", DATA4L },
4274 { "d5l", DATA5L },
4275 { "d6l", DATA6L },
4276 { "d7l", DATA7L },
4277
4278 { "a0l", ADDR0L },
4279 { "a1l", ADDR1L },
4280 { "a2l", ADDR2L },
4281 { "a3l", ADDR3L },
4282 { "a4l", ADDR4L },
4283 { "a5l", ADDR5L },
4284 { "a6l", ADDR6L },
4285 { "a7l", ADDR7L },
4286
4287 { "d0u", DATA0U },
4288 { "d1u", DATA1U },
4289 { "d2u", DATA2U },
4290 { "d3u", DATA3U },
4291 { "d4u", DATA4U },
4292 { "d5u", DATA5U },
4293 { "d6u", DATA6U },
4294 { "d7u", DATA7U },
4295
4296 { "a0u", ADDR0U },
4297 { "a1u", ADDR1U },
4298 { "a2u", ADDR2U },
4299 { "a3u", ADDR3U },
4300 { "a4u", ADDR4U },
4301 { "a5u", ADDR5U },
4302 { "a6u", ADDR6U },
4303 { "a7u", ADDR7U },
4304
252b5132
RH		 4305 { 0, 0 }
4306};
4307
4308static void
31302357 4309init_regtable (void)
252b5132
RH		 4310{
4311 int i;
4312 for (i = 0; init_table[i].name; i++)
4313 insert_reg (init_table[i].name, init_table[i].number);
4314}
4315
252b5132 4316void
31302357 4317md_assemble (char *str)
252b5132
RH		 4318{
4319 const char *er;
4320 short *fromP;
4321 char *toP = NULL;
4322 int m, n = 0;
4323 char *to_beg_P;
4324 int shorts_this_frag;
4325 fixS *fixP;
4326
266abb8f
NS		 4327 if (!selected_cpu && !selected_arch)
4328 {
4329 /* We've not selected an architecture yet. Set the default
4330 now. We do this lazily so that an initial .cpu or .arch directive
4331 can specify. */
4332 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4333 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4334 }
4335 if (!initialized)
4336 m68k_init_arch ();
4337
252b5132
RH		 4338 /* In MRI mode, the instruction and operands are separated by a
4339 space. Anything following the operands is a comment. The label
4340 has already been removed. */
4341 if (flag_mri)
4342 {
4343 char *s;
4344 int fields = 0;
4345 int infield = 0;
4346 int inquote = 0;
4347
4348 for (s = str; *s != '\0'; s++)
4349 {
4350 if ((*s == ' ' || *s == '\t') && ! inquote)
4351 {
4352 if (infield)
4353 {
4354 ++fields;
4355 if (fields >= 2)
4356 {
4357 *s = '\0';
4358 break;
4359 }
4360 infield = 0;
4361 }
4362 }
4363 else
4364 {
4365 if (! infield)
4366 infield = 1;
4367 if (*s == '\'')
4368 inquote = ! inquote;
4369 }
4370 }
4371 }
4372
31302357 4373 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4374 m68k_ip (str);
4375 er = the_ins.error;
4376 if (!er)
4377 {
4378 for (n = 0; n < the_ins.numargs; n++)
4379 if (the_ins.operands[n].error)
4380 {
4381 er = the_ins.operands[n].error;
4382 break;
4383 }
4384 }
4385 if (er)
4386 {
4387 as_bad (_("%s -- statement `%s' ignored"), er, str);
4388 return;
4389 }
4390
4391 /* If there is a current label, record that it marks an instruction. */
4392 if (current_label != NULL)
4393 {
4394 current_label->text = 1;
4395 current_label = NULL;
4396 }
4397
f27a3839
AS		 4398#ifdef OBJ_ELF
4399 /* Tie dwarf2 debug info to the address at the start of the insn. */
4400 dwarf2_emit_insn (0);
4401#endif
4402
252b5132
RH		 4403 if (the_ins.nfrag == 0)
4404 {
36759679 4405 /* No frag hacking involved; just put it out. */
252b5132
RH		 4406 toP = frag_more (2 * the_ins.numo);
4407 fromP = &the_ins.opcode[0];
4408 for (m = the_ins.numo; m; --m)
4409 {
4410 md_number_to_chars (toP, (long) (*fromP), 2);
4411 toP += 2;
4412 fromP++;
4413 }
36759679 4414 /* Put out symbol-dependent info. */
252b5132
RH		 4415 for (m = 0; m < the_ins.nrel; m++)
4416 {
4417 switch (the_ins.reloc[m].wid)
4418 {
4419 case 'B':
4420 n = 1;
4421 break;
4422 case 'b':
4423 n = 1;
4424 break;
4425 case '3':
4426 n = 1;
4427 break;
4428 case 'w':
4429 case 'W':
4430 n = 2;
4431 break;
4432 case 'l':
4433 n = 4;
4434 break;
4435 default:
4436 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4437 the_ins.reloc[m].wid);
4438 }
4439
4440 fixP = fix_new_exp (frag_now,
4441 ((toP - frag_now->fr_literal)
4442 - the_ins.numo * 2 + the_ins.reloc[m].n),
4443 n,
4444 &the_ins.reloc[m].exp,
4445 the_ins.reloc[m].pcrel,
4446 get_reloc_code (n, the_ins.reloc[m].pcrel,
4447 the_ins.reloc[m].pic_reloc));
4448 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4449 if (the_ins.reloc[m].wid == 'B')
4450 fixP->fx_signed = 1;
4451 }
4452 return;
4453 }
4454
36759679 4455 /* There's some frag hacking. */
fbe572f9
AM		 4456 {
4457 /* Calculate the max frag size. */
4458 int wid;
4459
4460 wid = 2 * the_ins.fragb[0].fragoff;
4461 for (n = 1; n < the_ins.nfrag; n++)
4462 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4463 /* frag_var part. */
cac27205 4464 wid += FRAG_VAR_SIZE;
fbe572f9
AM		 4465 /* Make sure the whole insn fits in one chunk, in particular that
4466 the var part is attached, as we access one byte before the
4467 variable frag for byte branches. */
4468 frag_grow (wid);
4469 }
4470
252b5132
RH		 4471 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4472 {
4473 int wid;
4474
4475 if (n == 0)
4476 wid = 2 * the_ins.fragb[n].fragoff;
4477 else
4478 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4479 toP = frag_more (wid);
4480 to_beg_P = toP;
4481 shorts_this_frag = 0;
4482 for (m = wid / 2; m; --m)
4483 {
4484 md_number_to_chars (toP, (long) (*fromP), 2);
4485 toP += 2;
4486 fromP++;
4487 shorts_this_frag++;
4488 }
4489 for (m = 0; m < the_ins.nrel; m++)
4490 {
4491 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4492 {
4493 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4494 break;
4495 }
4496 wid = the_ins.reloc[m].wid;
4497 if (wid == 0)
4498 continue;
4499 the_ins.reloc[m].wid = 0;
4500 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4501
4502 fixP = fix_new_exp (frag_now,
4503 ((toP - frag_now->fr_literal)
4504 - the_ins.numo * 2 + the_ins.reloc[m].n),
4505 wid,
4506 &the_ins.reloc[m].exp,
4507 the_ins.reloc[m].pcrel,
4508 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4509 the_ins.reloc[m].pic_reloc));
4510 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4511 }
cac27205 4512 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
252b5132
RH		 4513 (relax_substateT) (the_ins.fragb[n].fragty),
4514 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4515 }
4516 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4517 shorts_this_frag = 0;
4518 if (n)
4519 {
055d1eb0 4520 toP = frag_more (n * 2);
252b5132
RH		 4521 while (n--)
4522 {
4523 md_number_to_chars (toP, (long) (*fromP), 2);
4524 toP += 2;
4525 fromP++;
4526 shorts_this_frag++;
4527 }
4528 }
4529 for (m = 0; m < the_ins.nrel; m++)
4530 {
4531 int wid;
4532
4533 wid = the_ins.reloc[m].wid;
4534 if (wid == 0)
4535 continue;
4536 the_ins.reloc[m].wid = 0;
4537 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4538
4539 fixP = fix_new_exp (frag_now,
4540 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4541 - shorts_this_frag * 2),
4542 wid,
4543 &the_ins.reloc[m].exp,
4544 the_ins.reloc[m].pcrel,
4545 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4546 the_ins.reloc[m].pic_reloc));
4547 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4548 }
4549}
4550
60fed2d3
NC		 4551/* Comparison function used by qsort to rank the opcode entries by name. */
4552
4553static int
4554m68k_compare_opcode (const void * v1, const void * v2)
4555{
4556 struct m68k_opcode * op1, * op2;
4557 int ret;
4558
03b13e59
NC		 4559 if (v1 == v2)
4560 return 0;
4561
60fed2d3
NC		 4562 op1 = *(struct m68k_opcode **) v1;
4563 op2 = *(struct m68k_opcode **) v2;
4564
4565 /* Compare the two names. If different, return the comparison.
4566 If the same, return the order they are in the opcode table. */
4567 ret = strcmp (op1->name, op2->name);
4568 if (ret)
4569 return ret;
4570 if (op1 < op2)
4571 return -1;
03b13e59 4572 return 1;
60fed2d3
NC		 4573}
4574
252b5132 4575void
60fed2d3 4576md_begin (void)
252b5132 4577{
60fed2d3
NC		 4578 const struct m68k_opcode *ins;
4579 struct m68k_incant *hack, *slak;
4580 const char *retval = 0; /* Empty string, or error msg text. */
4581 int i;
4582
4583 /* Set up hash tables with 68000 instructions.
4584 similar to what the vax assembler does. */
252b5132
RH		 4585 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4586 a copy of it at runtime, adding in the information we want but isn't
4587 there. I think it'd be better to have an awk script hack the table
4588 at compile time. Or even just xstr the table and use it as-is. But
4589 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4590 names. */
4591
252b5132
RH		 4592 if (flag_mri)
4593 {
4594 flag_reg_prefix_optional = 1;
4595 m68k_abspcadd = 1;
4596 if (! m68k_rel32_from_cmdline)
4597 m68k_rel32 = 0;
4598 }
4599
60fed2d3
NC		 4600 /* First sort the opcode table into alphabetical order to seperate
4601 the order that the assembler wants to see the opcodes from the
4602 order that the disassembler wants to see them. */
4603 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4604 if (!m68k_sorted_opcodes)
4605 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4606 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4607
4608 for (i = m68k_numopcodes; i--;)
4609 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4610
4611 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4612 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4613
252b5132
RH		 4614 op_hash = hash_new ();
4615
4616 obstack_begin (&robyn, 4000);
4617 for (i = 0; i < m68k_numopcodes; i++)
4618 {
78aff5a5 4619 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4620 do
4621 {
60fed2d3
NC		 4622 ins = m68k_sorted_opcodes[i];
4623
afa2158f
NS		 4624 /* We must enter all insns into the table, because .arch and
4625 .cpu directives can change things. */
252b5132 4626 slak->m_operands = ins->args;
252b5132
RH		 4627 slak->m_arch = ins->arch;
4628 slak->m_opcode = ins->opcode;
afa2158f
NS		 4629
4630 /* In most cases we can determine the number of opcode words
4631 by checking the second word of the mask. Unfortunately
4632 some instructions have 2 opcode words, but no fixed bits
4633 in the second word. A leading dot in the operands
4634 string also indicates 2 opcodes. */
4635 if (*slak->m_operands == '.')
4636 {
4637 slak->m_operands++;
4638 slak->m_codenum = 2;
4639 }
4640 else if (ins->match & 0xffffL)
4641 slak->m_codenum = 2;
4642 else
4643 slak->m_codenum = 1;
4644 slak->m_opnum = strlen (slak->m_operands) / 2;
4645
252b5132 4646 if (i + 1 != m68k_numopcodes
60fed2d3 4647 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4648 {
60fed2d3 4649 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4650 i++;
4651 }
4652 else
4653 slak->m_next = 0;
4654 slak = slak->m_next;
4655 }
4656 while (slak);
4657
4658 retval = hash_insert (op_hash, ins->name, (char *) hack);
4659 if (retval)
4660 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4661 }
4662
4663 for (i = 0; i < m68k_numaliases; i++)
4664 {
4665 const char *name = m68k_opcode_aliases[i].primary;
4666 const char *alias = m68k_opcode_aliases[i].alias;
5a49b8ac 4667 void *val = hash_find (op_hash, name);
60fed2d3 4668
252b5132
RH		 4669 if (!val)
4670 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4671 retval = hash_insert (op_hash, alias, val);
4672 if (retval)
4673 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4674 }
4675
4676 /* In MRI mode, all unsized branches are variable sized. Normally,
4677 they are word sized. */
4678 if (flag_mri)
4679 {
4680 static struct m68k_opcode_alias mri_aliases[] =
4681 {
4682 { "bhi", "jhi", },
4683 { "bls", "jls", },
4684 { "bcc", "jcc", },
4685 { "bcs", "jcs", },
4686 { "bne", "jne", },
4687 { "beq", "jeq", },
4688 { "bvc", "jvc", },
4689 { "bvs", "jvs", },
4690 { "bpl", "jpl", },
4691 { "bmi", "jmi", },
4692 { "bge", "jge", },
4693 { "blt", "jlt", },
4694 { "bgt", "jgt", },
4695 { "ble", "jle", },
4696 { "bra", "jra", },
4697 { "bsr", "jbsr", },
4698 };
4699
8fce3f5e
AM		 4700 for (i = 0;
4701 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4702 i++)
252b5132
RH		 4703 {
4704 const char *name = mri_aliases[i].primary;
4705 const char *alias = mri_aliases[i].alias;
5a49b8ac 4706 void *val = hash_find (op_hash, name);
60fed2d3 4707
252b5132
RH		 4708 if (!val)
4709 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4710 retval = hash_jam (op_hash, alias, val);
4711 if (retval)
4712 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4713 }
4714 }
4715
8fce3f5e 4716 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4717 {
4718 notend_table[i] = 0;
4719 alt_notend_table[i] = 0;
4720 }
60fed2d3 4721
252b5132
RH		 4722 notend_table[','] = 1;
4723 notend_table['{'] = 1;
4724 notend_table['}'] = 1;
4725 alt_notend_table['a'] = 1;
4726 alt_notend_table['A'] = 1;
4727 alt_notend_table['d'] = 1;
4728 alt_notend_table['D'] = 1;
4729 alt_notend_table['#'] = 1;
4730 alt_notend_table['&'] = 1;
4731 alt_notend_table['f'] = 1;
4732 alt_notend_table['F'] = 1;
4733#ifdef REGISTER_PREFIX
4734 alt_notend_table[REGISTER_PREFIX] = 1;
4735#endif
4736
4737 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4738 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4739 alt_notend_table['('] = 1;
4740
4741 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4742 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4743 alt_notend_table['@'] = 1;
4744
4745 /* We need to put digits in alt_notend_table to handle
60fed2d3 4746 bfextu %d0{24:1},%d0 */
252b5132
RH		 4747 alt_notend_table['0'] = 1;
4748 alt_notend_table['1'] = 1;
4749 alt_notend_table['2'] = 1;
4750 alt_notend_table['3'] = 1;
4751 alt_notend_table['4'] = 1;
4752 alt_notend_table['5'] = 1;
4753 alt_notend_table['6'] = 1;
4754 alt_notend_table['7'] = 1;
4755 alt_notend_table['8'] = 1;
4756 alt_notend_table['9'] = 1;
4757
4758#ifndef MIT_SYNTAX_ONLY
4759 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4760 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4761 {
4762 int n = 0;
60fed2d3 4763
252b5132
RH		 4764 while (mote_pseudo_table[n].poc_name)
4765 {
60fed2d3 4766 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4767 hash_insert (op_hash,
4768 mote_pseudo_table[n].poc_name, (char *) hack);
4769 hack->m_operands = 0;
4770 hack->m_opnum = n;
4771 n++;
4772 }
4773 }
4774#endif
4775
4776 init_regtable ();
4777
4778#ifdef OBJ_ELF
4779 record_alignment (text_section, 2);
4780 record_alignment (data_section, 2);
4781 record_alignment (bss_section, 2);
4782#endif
4783}
4784
252b5132
RH		 4785\f
4786/* This is called when a label is defined. */
4787
4788void
31302357 4789m68k_frob_label (symbolS *sym)
252b5132
RH		 4790{
4791 struct label_line *n;
4792
4793 n = (struct label_line *) xmalloc (sizeof *n);
4794 n->next = labels;
4795 n->label = sym;
4796 as_where (&n->file, &n->line);
4797 n->text = 0;
4798 labels = n;
4799 current_label = n;
07a53e5c
RH		 4800
4801#ifdef OBJ_ELF
4802 dwarf2_emit_label (sym);
4803#endif
252b5132
RH		 4804}
4805
4806/* This is called when a value that is not an instruction is emitted. */
4807
4808void
31302357 4809m68k_flush_pending_output (void)
252b5132
RH		 4810{
4811 current_label = NULL;
4812}
4813
4814/* This is called at the end of the assembly, when the final value of
4815 the label is known. We warn if this is a text symbol aligned at an
4816 odd location. */
4817
4818void
31302357 4819m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4820{
4821 if (S_GET_SEGMENT (sym) == reg_section
4822 && (int) S_GET_VALUE (sym) < 0)
4823 {
4824 S_SET_SEGMENT (sym, absolute_section);
4825 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4826 }
4827 else if ((S_GET_VALUE (sym) & 1) != 0)
4828 {
4829 struct label_line *l;
4830
4831 for (l = labels; l != NULL; l = l->next)
4832 {
4833 if (l->label == sym)
4834 {
4835 if (l->text)
4836 as_warn_where (l->file, l->line,
4837 _("text label `%s' aligned to odd boundary"),
4838 S_GET_NAME (sym));
4839 break;
4840 }
4841 }
4842 }
4843}
4844\f
4845/* This is called if we go in or out of MRI mode because of the .mri
4846 pseudo-op. */
4847
4848void
31302357 4849m68k_mri_mode_change (int on)
252b5132
RH		 4850{
4851 if (on)
4852 {
4853 if (! flag_reg_prefix_optional)
4854 {
4855 flag_reg_prefix_optional = 1;
4856#ifdef REGISTER_PREFIX
4857 init_regtable ();
4858#endif
4859 }
4860 m68k_abspcadd = 1;
4861 if (! m68k_rel32_from_cmdline)
4862 m68k_rel32 = 0;
4863 }
4864 else
4865 {
4866 if (! reg_prefix_optional_seen)
4867 {
4868#ifdef REGISTER_PREFIX_OPTIONAL
4869 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4870#else
4871 flag_reg_prefix_optional = 0;
4872#endif
4873#ifdef REGISTER_PREFIX
4874 init_regtable ();
4875#endif
4876 }
4877 m68k_abspcadd = 0;
4878 if (! m68k_rel32_from_cmdline)
4879 m68k_rel32 = 1;
4880 }
4881}
4882
252b5132 4883char *
31302357 4884md_atof (int type, char *litP, int *sizeP)
252b5132 4885{
499ac353 4886 return ieee_md_atof (type, litP, sizeP, TRUE);
252b5132
RH		 4887}
4888
4889void
31302357 4890md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4891{
4892 number_to_chars_bigendian (buf, val, n);
4893}
4894
94f592af 4895void
55cf6793 4896md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4897{
bbe8ef22 4898 offsetT val = *valP;
252b5132
RH		 4899 addressT upper_limit;
4900 offsetT lower_limit;
4901
4902 /* This is unnecessary but it convinces the native rs6000 compiler
4903 to generate the code we want. */
4904 char *buf = fixP->fx_frag->fr_literal;
4905 buf += fixP->fx_where;
36759679 4906 /* End ibm compiler workaround. */
252b5132 4907
bd17c2c3 4908 val = SEXT (val);
252b5132 4909
94f592af
NC		 4910 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4911 fixP->fx_done = 1;
4912
252b5132
RH		 4913#ifdef OBJ_ELF
4914 if (fixP->fx_addsy)
4915 {
4916 memset (buf, 0, fixP->fx_size);
36759679 4917 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4918
4919 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4920 && !S_IS_DEFINED (fixP->fx_addsy)
4921 && !S_IS_WEAK (fixP->fx_addsy))
4922 S_SET_WEAK (fixP->fx_addsy);
cf869cce
NC		 4923
4924 switch (fixP->fx_r_type)
4925 {
4926 case BFD_RELOC_68K_TLS_GD32:
4927 case BFD_RELOC_68K_TLS_GD16:
4928 case BFD_RELOC_68K_TLS_GD8:
4929 case BFD_RELOC_68K_TLS_LDM32:
4930 case BFD_RELOC_68K_TLS_LDM16:
4931 case BFD_RELOC_68K_TLS_LDM8:
4932 case BFD_RELOC_68K_TLS_LDO32:
4933 case BFD_RELOC_68K_TLS_LDO16:
4934 case BFD_RELOC_68K_TLS_LDO8:
4935 case BFD_RELOC_68K_TLS_IE32:
4936 case BFD_RELOC_68K_TLS_IE16:
4937 case BFD_RELOC_68K_TLS_IE8:
4938 case BFD_RELOC_68K_TLS_LE32:
4939 case BFD_RELOC_68K_TLS_LE16:
4940 case BFD_RELOC_68K_TLS_LE8:
4941 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4942 break;
4943
4944 default:
4945 break;
4946 }
4947
252b5132
RH		 4948 return;
4949 }
22184a77 4950#elif defined(OBJ_AOUT)
1c3f20b4 4951 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
22184a77
NC		 4952 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4953 {
4954 memset (buf, 0, fixP->fx_size);
1c3f20b4 4955 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
22184a77
NC		 4956 return;
4957 }
252b5132
RH		 4958#endif
4959
252b5132
RH		 4960 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4961 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4962 return;
252b5132
RH		 4963
4964 switch (fixP->fx_size)
4965 {
94f592af
NC		 4966 /* The cast to offsetT below are necessary to make code
4967 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4968 case 1:
4969 *buf++ = val;
4970 upper_limit = 0x7f;
4971 lower_limit = - (offsetT) 0x80;
4972 break;
4973 case 2:
4974 *buf++ = (val >> 8);
4975 *buf++ = val;
4976 upper_limit = 0x7fff;
4977 lower_limit = - (offsetT) 0x8000;
4978 break;
4979 case 4:
4980 *buf++ = (val >> 24);
4981 *buf++ = (val >> 16);
4982 *buf++ = (val >> 8);
4983 *buf++ = val;
4984 upper_limit = 0x7fffffff;
36759679 4985 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4986 break;
4987 default:
4988 BAD_CASE (fixP->fx_size);
4989 }
4990
4991 /* Fix up a negative reloc. */
4992 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4993 {
4994 fixP->fx_addsy = fixP->fx_subsy;
4995 fixP->fx_subsy = NULL;
4996 fixP->fx_tcbit = 1;
4997 }
4998
4999 /* For non-pc-relative values, it's conceivable we might get something
5000 like "0xff" for a byte field. So extend the upper part of the range
5001 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
5002 so that we can do any range checking at all. */
5003 if (! fixP->fx_pcrel && ! fixP->fx_signed)
5004 upper_limit = upper_limit * 2 + 1;
5005
5006 if ((addressT) val > upper_limit
5007 && (val > 0 || val < lower_limit))
2b878742
NS		 5008 as_bad_where (fixP->fx_file, fixP->fx_line,
5009 _("value %ld out of range"), (long)val);
252b5132
RH		 5010
5011 /* A one byte PC-relative reloc means a short branch. We can't use
5012 a short branch with a value of 0 or -1, because those indicate
5013 different opcodes (branches with longer offsets). fixup_segment
5014 in write.c may have clobbered fx_pcrel, so we need to examine the
5015 reloc type. */
5016 if ((fixP->fx_pcrel
7be1c489 5017 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 5018 && fixP->fx_size == 1
5019 && (fixP->fx_addsy == NULL
5020 || S_IS_DEFINED (fixP->fx_addsy))
5021 && (val == 0 || val == -1))
2b878742
NS		 5022 as_bad_where (fixP->fx_file, fixP->fx_line,
5023 _("invalid byte branch offset"));
252b5132
RH		 5024}
5025
252b5132
RH		 5026/* *fragP has been relaxed to its final size, and now needs to have
5027 the bytes inside it modified to conform to the new size There is UGLY
5028 MAGIC here. ..
5029 */
5030static void
31302357 5031md_convert_frag_1 (fragS *fragP)
252b5132
RH		 5032{
5033 long disp;
2b878742 5034 fixS *fixP = NULL;
252b5132
RH		 5035
5036 /* Address in object code of the displacement. */
5037 register int object_address = fragP->fr_fix + fragP->fr_address;
5038
5039 /* Address in gas core of the place to store the displacement. */
5040 /* This convinces the native rs6000 compiler to generate the code we
92774660 5041 want. */
252b5132
RH		 5042 register char *buffer_address = fragP->fr_literal;
5043 buffer_address += fragP->fr_fix;
36759679 5044 /* End ibm compiler workaround. */
252b5132
RH		 5045
5046 /* The displacement of the address, from current location. */
5047 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
5048 disp = (disp + fragP->fr_offset) - object_address;
5049
252b5132
RH		 5050 switch (fragP->fr_subtype)
5051 {
151337e8
NC		 5052 case TAB (BRANCHBWL, BYTE):
5053 case TAB (BRABSJUNC, BYTE):
5054 case TAB (BRABSJCOND, BYTE):
5055 case TAB (BRANCHBW, BYTE):
cac27205 5056 case TAB (BRANCHBWPL, BYTE):
252b5132
RH		 5057 know (issbyte (disp));
5058 if (disp == 0)
b091f402
AM		 5059 as_bad_where (fragP->fr_file, fragP->fr_line,
5060 _("short branch with zero offset: use :w"));
151337e8 5061 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5062 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5063 fixP->fx_pcrel_adjust = -1;
252b5132 5064 break;
151337e8
NC		 5065 case TAB (BRANCHBWL, SHORT):
5066 case TAB (BRABSJUNC, SHORT):
5067 case TAB (BRABSJCOND, SHORT):
5068 case TAB (BRANCHBW, SHORT):
cac27205 5069 case TAB (BRANCHBWPL, SHORT):
252b5132 5070 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 5071 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5072 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5073 fragP->fr_fix += 2;
5074 break;
5075 case TAB (BRANCHBWL, LONG):
5076 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 5077 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5078 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 5079 fragP->fr_fix += 4;
252b5132 5080 break;
cac27205
NC		 5081 case TAB (BRANCHBWPL, LONG):
5082 /* Here we are converting an unconditional branch into a pair of
5083 conditional branches, in order to get the range. */
5084 fragP->fr_opcode[0] = 0x66; /* bne */
5085 fragP->fr_opcode[1] = 0xFF;
5086 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5087 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5088 fixP->fx_file = fragP->fr_file;
5089 fixP->fx_line = fragP->fr_line;
5090 fragP->fr_fix += 4; /* Skip first offset */
5091 buffer_address += 4;
5092 *buffer_address++ = 0x67; /* beq */
5093 *buffer_address++ = 0xff;
5094 fragP->fr_fix += 2; /* Skip second branch opcode */
5095 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5096 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5097 fragP->fr_fix += 4;
5098 break;
151337e8
NC		 5099 case TAB (BRABSJUNC, LONG):
5100 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 5101 {
36759679 5102 if (flag_keep_pcrel)
2b878742
NS		 5103 as_bad_where (fragP->fr_file, fragP->fr_line,
5104 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 5105 fragP->fr_opcode[0] = 0x4E;
36759679 5106 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 5107 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5108 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5109 fragP->fr_fix += 4;
5110 }
5111 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5112 {
36759679 5113 if (flag_keep_pcrel)
2b878742
NS		 5114 as_bad_where (fragP->fr_file, fragP->fr_line,
5115 _("Conversion of PC relative branch to absolute jump"));
151337e8 5116 fragP->fr_opcode[0] = 0x4E;
36759679 5117 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 5118 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5119 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5120 fragP->fr_fix += 4;
252b5132
RH		 5121 }
5122 else
5123 {
151337e8
NC		 5124 /* This cannot happen, because jbsr and jbra are the only two
5125 unconditional branches. */
5126 abort ();
252b5132
RH		 5127 }
5128 break;
151337e8 5129 case TAB (BRABSJCOND, LONG):
36759679 5130 if (flag_keep_pcrel)
2b878742
NS		 5131 as_bad_where (fragP->fr_file, fragP->fr_line,
5132 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 5133
36759679
NC		 5134 /* Only Bcc 68000 instructions can come here
5135 Change bcc into b!cc/jmp absl long. */
5136 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5137 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 5138
5139 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 5140 different frag, in which case referring to them is a no-no.
92774660 5141 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 5142 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5143 *buffer_address++ = (char) 0xf9;
36759679 5144 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 5145 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5146 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5147 fragP->fr_fix += 4;
5148 break;
5149 case TAB (FBRANCH, SHORT):
5150 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 5151 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5152 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5153 fragP->fr_fix += 2;
5154 break;
5155 case TAB (FBRANCH, LONG):
36759679 5156 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 5157 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5158 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5159 fragP->fr_fix += 4;
252b5132 5160 break;
151337e8
NC		 5161 case TAB (DBCCLBR, SHORT):
5162 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 5163 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5164 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5165 fragP->fr_fix += 2;
5166 break;
5167 case TAB (DBCCLBR, LONG):
36759679
NC		 5168 /* Only DBcc instructions can come here.
5169 Change dbcc into dbcc/bral.
5170 JF: these used to be fr_opcode[2-7], but that's wrong. */
5171 if (flag_keep_pcrel)
2b878742
NS		 5172 as_bad_where (fragP->fr_file, fragP->fr_line,
5173 _("Conversion of DBcc to absolute jump"));
28e7409f 5174
36759679 5175 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 5176 *buffer_address++ = 0x04;
36759679 5177 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 5178 *buffer_address++ = 0x06;
151337e8
NC		 5179 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5180 *buffer_address++ = (char) 0xff;
252b5132 5181
36759679 5182 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5183 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5184 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5185 fragP->fr_fix += 4;
252b5132 5186 break;
151337e8 5187 case TAB (DBCCABSJ, LONG):
36759679
NC		 5188 /* Only DBcc instructions can come here.
5189 Change dbcc into dbcc/jmp.
5190 JF: these used to be fr_opcode[2-7], but that's wrong. */
5191 if (flag_keep_pcrel)
2b878742
NS		 5192 as_bad_where (fragP->fr_file, fragP->fr_line,
5193 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 5194
36759679 5195 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 5196 *buffer_address++ = 0x04;
36759679 5197 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 5198 *buffer_address++ = 0x06;
36759679 5199 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 5200 *buffer_address++ = (char) 0xf9;
5201
36759679 5202 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5203 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5204 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 5205 fragP->fr_fix += 4;
252b5132 5206 break;
151337e8 5207 case TAB (PCREL1632, SHORT):
252b5132
RH		 5208 fragP->fr_opcode[1] &= ~0x3F;
5209 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 5210 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5211 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 5212 fragP->fr_fix += 2;
252b5132 5213 break;
151337e8 5214 case TAB (PCREL1632, LONG):
252b5132
RH		 5215 /* Already set to mode 7.3; this indicates: PC indirect with
5216 suppressed index, 32-bit displacement. */
5217 *buffer_address++ = 0x01;
5218 *buffer_address++ = 0x70;
5219 fragP->fr_fix += 2;
151337e8 5220 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5221 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5222 fixP->fx_pcrel_adjust = 2;
5223 fragP->fr_fix += 4;
252b5132 5224 break;
252b5132 5225 case TAB (PCINDEX, BYTE):
9c2799c2 5226 gas_assert (fragP->fr_fix >= 2);
252b5132 5227 buffer_address[-2] &= ~1;
151337e8 5228 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5229 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5230 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5231 break;
5232 case TAB (PCINDEX, SHORT):
9c2799c2 5233 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5234 buffer_address[-2] |= 0x1;
5235 buffer_address[-1] = 0x20;
5236 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5237 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5238 fixP->fx_pcrel_adjust = 2;
151337e8 5239 fragP->fr_fix += 2;
252b5132
RH		 5240 break;
5241 case TAB (PCINDEX, LONG):
9c2799c2 5242 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5243 buffer_address[-2] |= 0x1;
5244 buffer_address[-1] = 0x30;
151337e8 5245 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5246 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5247 fixP->fx_pcrel_adjust = 2;
5248 fragP->fr_fix += 4;
5249 break;
5250 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5251 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5252 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5253 fragP->fr_fix += 2;
5254 break;
5255 case TAB (ABSTOPCREL, LONG):
36759679 5256 if (flag_keep_pcrel)
025987ea
NS		 5257 as_bad_where (fragP->fr_file, fragP->fr_line,
5258 _("Conversion of PC relative displacement to absolute"));
151337e8 5259 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5260 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5261 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5262 abort ();
5263 fragP->fr_opcode[1] &= ~0x3F;
5264 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5265 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5266 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5267 fragP->fr_fix += 4;
252b5132 5268 break;
252b5132 5269 }
2b878742
NS		 5270 if (fixP)
5271 {
5272 fixP->fx_file = fragP->fr_file;
5273 fixP->fx_line = fragP->fr_line;
5274 }
252b5132
RH		 5275}
5276
252b5132 5277void
31302357
AS		 5278md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5279 segT sec ATTRIBUTE_UNUSED,
5280 fragS *fragP)
252b5132
RH		 5281{
5282 md_convert_frag_1 (fragP);
5283}
252b5132
RH		 5284
5285/* Force truly undefined symbols to their maximum size, and generally set up
5286 the frag list to be relaxed
5287 */
5288int
31302357 5289md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5290{
151337e8 5291 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5292 switch (fragP->fr_subtype)
5293 {
151337e8 5294 case TAB (BRANCHBWL, SZ_UNDEF):
cac27205 5295 case TAB (BRANCHBWPL, SZ_UNDEF):
151337e8 5296 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5297 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5298 {
151337e8
NC		 5299 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5300 && relaxable_symbol (fragP->fr_symbol))
252b5132 5301 {
151337e8
NC		 5302 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5303 }
5304 else if (flag_short_refs)
5305 {
5306 /* Symbol is undefined and we want short ref. */
5307 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5308 }
5309 else
5310 {
151337e8
NC		 5311 /* Symbol is still undefined. Make it LONG. */
5312 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5313 }
5314 break;
151337e8 5315 }
252b5132 5316
151337e8 5317 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5318 {
151337e8
NC		 5319 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5320 && relaxable_symbol (fragP->fr_symbol))
252b5132 5321 {
151337e8 5322 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5323 }
5324 else
5325 {
151337e8
NC		 5326 /* Symbol is undefined and we don't have long branches. */
5327 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5328 }
5329 break;
151337e8 5330 }
252b5132 5331
151337e8 5332 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5333 case TAB (DBCCLBR, SZ_UNDEF):
5334 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5335 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5336 {
8ec6253e
NC		 5337 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5338 && relaxable_symbol (fragP->fr_symbol))
151337e8 5339 || flag_short_refs)
252b5132 5340 {
151337e8 5341 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5342 }
5343 else
5344 {
151337e8 5345 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5346 }
5347 break;
151337e8 5348 }
81d4177b 5349
252b5132
RH		 5350 case TAB (PCINDEX, SZ_UNDEF):
5351 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5352 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5353 {
5354 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5355 }
5356 else
5357 {
5358 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5359 }
5360 break;
5361
151337e8
NC		 5362 case TAB (ABSTOPCREL, SZ_UNDEF):
5363 {
5364 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5365 && relaxable_symbol (fragP->fr_symbol)))
5366 {
5367 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5368 }
5369 else
5370 {
5371 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5372 }
5373 break;
5374 }
5375
252b5132
RH		 5376 default:
5377 break;
5378 }
5379
151337e8 5380 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5381 switch (fragP->fr_subtype)
5382 {
151337e8
NC		 5383 case TAB (BRANCHBWL, BYTE):
5384 case TAB (BRABSJUNC, BYTE):
5385 case TAB (BRABSJCOND, BYTE):
5386 case TAB (BRANCHBW, BYTE):
252b5132 5387 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5388 case we force word mode. If the symbol is at the start of a
5389 frag, and it is the next frag with any data in it (usually
5390 this is just the next frag, but assembler listings may
5391 introduce empty frags), we must use word mode. */
5392 if (fragP->fr_symbol)
252b5132 5393 {
ac62c346 5394 fragS *sym_frag;
252b5132 5395
ac62c346
AM		 5396 sym_frag = symbol_get_frag (fragP->fr_symbol);
5397 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5398 {
ac62c346
AM		 5399 fragS *l;
5400
23b7f870 5401 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5402 if (l->fr_fix != 0)
5403 break;
5404 if (l == sym_frag)
5405 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5406 }
5407 }
5408 break;
5409 default:
5410 break;
5411 }
ac62c346 5412 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5413}
5414
5415#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5416/* the bit-field entries in the relocation_info struct plays hell
5417 with the byte-order problems of cross-assembly. So as a hack,
5418 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5419 you there. -KWK */
252b5132
RH		 5420/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5421 are symbolnum, most sig. byte first. Last byte is broken up with
5422 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5423 nibble as nuthin. (on Sun 3 at least) */
5424/* Translate the internal relocation information into target-specific
92774660 5425 format. */
252b5132
RH		 5426#ifdef comment
5427void
31302357 5428md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5429{
36759679 5430 /* This is easy. */
252b5132 5431 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5432 /* Now the fun stuff. */
252b5132 5433 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5434 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5435 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5436 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5437 | ((ri->r_length << 5) & 0x60)
5438 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5439}
5440
36759679 5441#endif
252b5132 5442
252b5132
RH		 5443#endif /* OBJ_AOUT or OBJ_BOUT */
5444
5445#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5446int md_short_jump_size = 4;
5447int md_long_jump_size = 6;
252b5132
RH		 5448
5449void
31302357
AS		 5450md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5451 fragS *frag ATTRIBUTE_UNUSED,
5452 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5453{
5454 valueT offset;
5455
5456 offset = to_addr - (from_addr + 2);
5457
5458 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5459 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5460}
5461
5462void
31302357
AS		 5463md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5464 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5465{
5466 valueT offset;
5467
6b6e92f4 5468 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5469 {
36759679 5470 if (flag_keep_pcrel)
6b6e92f4 5471 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5472 offset = to_addr - S_GET_VALUE (to_symbol);
5473 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5474 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5475 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5476 0, NO_RELOC);
5477 }
5478 else
5479 {
5480 offset = to_addr - (from_addr + 2);
5481 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5482 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5483 }
5484}
5485
5486#endif
5487
5488/* Different values of OK tell what its OK to return. Things that
5489 aren't OK are an error (what a shock, no?)
5490
5491 0: Everything is OK
3e602632
NC		 5492 10: Absolute 1:8 only
5493 20: Absolute 0:7 only
5494 30: absolute 0:15 only
5495 40: Absolute 0:31 only
5496 50: absolute 0:127 only
252b5132 5497 55: absolute -64:63 only
3e602632 5498 60: absolute -128:127 only
afa2158f 5499 65: absolute 0:511 only
3e602632
NC		 5500 70: absolute 0:4095 only
5501 80: absolute -1, 1:7 only
5502 90: No bignums. */
252b5132
RH		 5503
5504static int
31302357 5505get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5506{
5507 if (exp->exp.X_op == O_absent)
5508 {
36759679 5509 /* Do the same thing the VAX asm does. */
252b5132
RH		 5510 op (exp) = O_constant;
5511 adds (exp) = 0;
5512 subs (exp) = 0;
5513 offs (exp) = 0;
5514 if (ok == 10)
5515 {
5516 as_warn (_("expression out of range: defaulting to 1"));
5517 offs (exp) = 1;
5518 }
5519 }
5520 else if (exp->exp.X_op == O_constant)
5521 {
5522 switch (ok)
5523 {
5524 case 10:
bd17c2c3 5525 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5526 {
5527 as_warn (_("expression out of range: defaulting to 1"));
5528 offs (exp) = 1;
5529 }
5530 break;
5531 case 20:
bd17c2c3 5532 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5533 goto outrange;
5534 break;
5535 case 30:
bd17c2c3 5536 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5537 goto outrange;
5538 break;
5539 case 40:
bd17c2c3 5540 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5541 goto outrange;
5542 break;
5543 case 50:
bd17c2c3 5544 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5545 goto outrange;
5546 break;
5547 case 55:
bd17c2c3 5548 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5549 goto outrange;
5550 break;
5551 case 60:
bd17c2c3 5552 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5553 goto outrange;
afa2158f
NS		 5554 break;
5555 case 65:
5556 if ((valueT) TRUNC (offs (exp)) > 511)
5557 goto outrange;
252b5132
RH		 5558 break;
5559 case 70:
bd17c2c3 5560 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5561 {
5562 outrange:
5563 as_warn (_("expression out of range: defaulting to 0"));
5564 offs (exp) = 0;
5565 }
5566 break;
3e602632 5567 case 80:
bd17c2c3
AM		 5568 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5569 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5570 {
5571 as_warn (_("expression out of range: defaulting to 1"));
5572 offs (exp) = 1;
5573 }
5574 break;
252b5132
RH		 5575 default:
5576 break;
5577 }
5578 }
5579 else if (exp->exp.X_op == O_big)
5580 {
36759679 5581 if (offs (exp) <= 0 /* flonum. */
3e602632 5582 && (ok == 90 /* no bignums */
36759679 5583 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5584 /* If we have a flonum zero, a zero integer should
5585 do as well (e.g., in moveq). */
5586 && generic_floating_point_number.exponent == 0
5587 && generic_floating_point_number.low[0] == 0)))
5588 {
36759679 5589 /* HACK! Turn it into a long. */
252b5132
RH		 5590 LITTLENUM_TYPE words[6];
5591
36759679 5592 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5593 op (exp) = O_constant;
5594 adds (exp) = 0;
5595 subs (exp) = 0;
5596 offs (exp) = words[1] | (words[0] << 16);
5597 }
5598 else if (ok != 0)
5599 {
5600 op (exp) = O_constant;
5601 adds (exp) = 0;
5602 subs (exp) = 0;
5603 offs (exp) = (ok == 10) ? 1 : 0;
5604 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5605 (long) offs (exp));
252b5132
RH		 5606 }
5607 }
5608 else
5609 {
3e602632 5610 if (ok >= 10 && ok <= 80)
252b5132
RH		 5611 {
5612 op (exp) = O_constant;
5613 adds (exp) = 0;
5614 subs (exp) = 0;
5615 offs (exp) = (ok == 10) ? 1 : 0;
5616 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5617 (long) offs (exp));
252b5132
RH		 5618 }
5619 }
5620
5621 if (exp->size != SIZE_UNSPEC)
5622 {
5623 switch (exp->size)
5624 {
5625 case SIZE_UNSPEC:
5626 case SIZE_LONG:
5627 break;
5628 case SIZE_BYTE:
5629 if (!isbyte (offs (exp)))
5630 as_warn (_("expression doesn't fit in BYTE"));
5631 break;
5632 case SIZE_WORD:
5633 if (!isword (offs (exp)))
5634 as_warn (_("expression doesn't fit in WORD"));
5635 break;
5636 }
5637 }
5638
5639 return offs (exp);
5640}
5641
5642/* These are the back-ends for the various machine dependent pseudo-ops. */
5643
5644static void
31302357 5645s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5646{
5647 subseg_set (data_section, 1);
5648 demand_empty_rest_of_line ();
5649}
5650
5651static void
31302357 5652s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5653{
5654 subseg_set (data_section, 2);
5655 demand_empty_rest_of_line ();
5656}
5657
5658static void
31302357 5659s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5660{
5661 /* We don't support putting frags in the BSS segment, we fake it
5662 by marking in_bss, then looking at s_skip for clues. */
5663
5664 subseg_set (bss_section, 0);
5665 demand_empty_rest_of_line ();
5666}
5667
5668static void
31302357 5669s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5670{
5671 register int temp;
5672 register long temp_fill;
5673
5674 temp = 1; /* JF should be 2? */
5675 temp_fill = get_absolute_expression ();
92774660 5676 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5677 frag_align (temp, (int) temp_fill, 0);
5678 demand_empty_rest_of_line ();
5679 record_alignment (now_seg, temp);
5680}
5681
5682static void
31302357 5683s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5684{
5685 demand_empty_rest_of_line ();
5686}
5687\f
5688/* Pseudo-ops handled for MRI compatibility. */
5689
5690/* This function returns non-zero if the argument is a conditional
5691 pseudo-op. This is called when checking whether a pending
5692 alignment is needed. */
5693
5694int
31302357 5695m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5696{
5697 return (pop->poc_handler == s_mri_if
5698 || pop->poc_handler == s_mri_else);
5699}
5700
5701/* Handle an MRI style chip specification. */
5702
5703static void
31302357 5704mri_chip (void)
252b5132
RH		 5705{
5706 char *s;
5707 char c;
5708 int i;
5709
5710 s = input_line_pointer;
5711 /* We can't use get_symbol_end since the processor names are not proper
5712 symbols. */
5713 while (is_part_of_name (c = *input_line_pointer++))
5714 ;
5715 *--input_line_pointer = 0;
266abb8f
NS		 5716 for (i = 0; m68k_cpus[i].name; i++)
5717 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5718 break;
266abb8f 5719 if (!m68k_cpus[i].name)
252b5132
RH		 5720 {
5721 as_bad (_("%s: unrecognized processor name"), s);
5722 *input_line_pointer = c;
5723 ignore_rest_of_line ();
5724 return;
5725 }
5726 *input_line_pointer = c;
5727
5728 if (*input_line_pointer == '/')
5729 current_architecture = 0;
5730 else
5731 current_architecture &= m68881 | m68851;
266abb8f 5732 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5733 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5734
5735 while (*input_line_pointer == '/')
5736 {
5737 ++input_line_pointer;
5738 s = input_line_pointer;
5739 /* We can't use get_symbol_end since the processor names are not
5740 proper symbols. */
5741 while (is_part_of_name (c = *input_line_pointer++))
5742 ;
5743 *--input_line_pointer = 0;
5744 if (strcmp (s, "68881") == 0)
5745 current_architecture |= m68881;
5746 else if (strcmp (s, "68851") == 0)
5747 current_architecture |= m68851;
5748 *input_line_pointer = c;
5749 }
252b5132
RH		 5750}
5751
5752/* The MRI CHIP pseudo-op. */
5753
5754static void
31302357 5755s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5756{
5757 char *stop = NULL;
5758 char stopc;
5759
5760 if (flag_mri)
5761 stop = mri_comment_field (&stopc);
5762 mri_chip ();
5763 if (flag_mri)
5764 mri_comment_end (stop, stopc);
5765 demand_empty_rest_of_line ();
5766}
5767
5768/* The MRI FOPT pseudo-op. */
5769
5770static void
31302357 5771s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5772{
5773 SKIP_WHITESPACE ();
5774
5775 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5776 {
5777 int temp;
5778
5779 input_line_pointer += 3;
5780 temp = get_absolute_expression ();
5781 if (temp < 0 || temp > 7)
5782 as_bad (_("bad coprocessor id"));
5783 else
5784 m68k_float_copnum = COP0 + temp;
5785 }
5786 else
5787 {
5788 as_bad (_("unrecognized fopt option"));
5789 ignore_rest_of_line ();
5790 return;
5791 }
5792
5793 demand_empty_rest_of_line ();
5794}
5795
5796/* The structure used to handle the MRI OPT pseudo-op. */
5797
5798struct opt_action
5799{
5800 /* The name of the option. */
5801 const char *name;
5802
5803 /* If this is not NULL, just call this function. The first argument
5804 is the ARG field of this structure, the second argument is
5805 whether the option was negated. */
31302357 5806 void (*pfn) (int arg, int on);
252b5132
RH		 5807
5808 /* If this is not NULL, and the PFN field is NULL, set the variable
5809 this points to. Set it to the ARG field if the option was not
5810 negated, and the NOTARG field otherwise. */
5811 int *pvar;
5812
5813 /* The value to pass to PFN or to assign to *PVAR. */
5814 int arg;
5815
5816 /* The value to assign to *PVAR if the option is negated. If PFN is
5817 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5818 the option may not be negated. */
5819 int notarg;
5820};
5821
5822/* The table used to handle the MRI OPT pseudo-op. */
5823
31302357
AS		 5824static void skip_to_comma (int, int);
5825static void opt_nest (int, int);
5826static void opt_chip (int, int);
5827static void opt_list (int, int);
5828static void opt_list_symbols (int, int);
252b5132
RH		 5829
5830static const struct opt_action opt_table[] =
5831{
5832 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5833
5834 /* We do relaxing, so there is little use for these options. */
5835 { "b", 0, 0, 0, 0 },
5836 { "brs", 0, 0, 0, 0 },
5837 { "brb", 0, 0, 0, 0 },
5838 { "brl", 0, 0, 0, 0 },
5839 { "brw", 0, 0, 0, 0 },
5840
5841 { "c", 0, 0, 0, 0 },
5842 { "cex", 0, 0, 0, 0 },
5843 { "case", 0, &symbols_case_sensitive, 1, 0 },
5844 { "cl", 0, 0, 0, 0 },
5845 { "cre", 0, 0, 0, 0 },
5846 { "d", 0, &flag_keep_locals, 1, 0 },
5847 { "e", 0, 0, 0, 0 },
5848 { "f", 0, &flag_short_refs, 1, 0 },
5849 { "frs", 0, &flag_short_refs, 1, 0 },
5850 { "frl", 0, &flag_short_refs, 0, 1 },
5851 { "g", 0, 0, 0, 0 },
5852 { "i", 0, 0, 0, 0 },
5853 { "m", 0, 0, 0, 0 },
5854 { "mex", 0, 0, 0, 0 },
5855 { "mc", 0, 0, 0, 0 },
5856 { "md", 0, 0, 0, 0 },
5857 { "nest", opt_nest, 0, 0, 0 },
5858 { "next", skip_to_comma, 0, 0, 0 },
5859 { "o", 0, 0, 0, 0 },
5860 { "old", 0, 0, 0, 0 },
5861 { "op", skip_to_comma, 0, 0, 0 },
5862 { "pco", 0, 0, 0, 0 },
5863 { "p", opt_chip, 0, 0, 0 },
5864 { "pcr", 0, 0, 0, 0 },
5865 { "pcs", 0, 0, 0, 0 },
5866 { "r", 0, 0, 0, 0 },
5867 { "quick", 0, &m68k_quick, 1, 0 },
5868 { "rel32", 0, &m68k_rel32, 1, 0 },
5869 { "s", opt_list, 0, 0, 0 },
5870 { "t", opt_list_symbols, 0, 0, 0 },
5871 { "w", 0, &flag_no_warnings, 0, 1 },
5872 { "x", 0, 0, 0, 0 }
5873};
5874
8fce3f5e 5875#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5876
5877/* The MRI OPT pseudo-op. */
5878
5879static void
31302357 5880s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5881{
5882 do
5883 {
5884 int t;
5885 char *s;
5886 char c;
5887 int i;
5888 const struct opt_action *o;
5889
5890 SKIP_WHITESPACE ();
5891
5892 t = 1;
5893 if (*input_line_pointer == '-')
5894 {
5895 ++input_line_pointer;
5896 t = 0;
5897 }
5898 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5899 {
5900 input_line_pointer += 2;
5901 t = 0;
5902 }
5903
5904 s = input_line_pointer;
5905 c = get_symbol_end ();
5906
5907 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5908 {
5909 if (strcasecmp (s, o->name) == 0)
5910 {
5911 if (o->pfn)
5912 {
5913 /* Restore input_line_pointer now in case the option
5914 takes arguments. */
5915 *input_line_pointer = c;
5916 (*o->pfn) (o->arg, t);
5917 }
5918 else if (o->pvar != NULL)
5919 {
5920 if (! t && o->arg == o->notarg)
5921 as_bad (_("option `%s' may not be negated"), s);
5922 *input_line_pointer = c;
5923 *o->pvar = t ? o->arg : o->notarg;
5924 }
5925 else
5926 *input_line_pointer = c;
5927 break;
5928 }
5929 }
5930 if (i >= OPTCOUNT)
5931 {
5932 as_bad (_("option `%s' not recognized"), s);
5933 *input_line_pointer = c;
5934 }
5935 }
5936 while (*input_line_pointer++ == ',');
5937
5938 /* Move back to terminating character. */
5939 --input_line_pointer;
5940 demand_empty_rest_of_line ();
5941}
5942
5943/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5944 not support and which take arguments. */
252b5132
RH		 5945
5946static void
31302357 5947skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5948{
5949 while (*input_line_pointer != ','
5950 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5951 ++input_line_pointer;
5952}
5953
5954/* Handle the OPT NEST=depth option. */
5955
5956static void
31302357 5957opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5958{
5959 if (*input_line_pointer != '=')
5960 {
5961 as_bad (_("bad format of OPT NEST=depth"));
5962 return;
5963 }
5964
5965 ++input_line_pointer;
5966 max_macro_nest = get_absolute_expression ();
5967}
5968
5969/* Handle the OPT P=chip option. */
5970
5971static void
31302357 5972opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5973{
5974 if (*input_line_pointer != '=')
5975 {
5976 /* This is just OPT P, which we do not support. */
5977 return;
5978 }
5979
5980 ++input_line_pointer;
5981 mri_chip ();
5982}
5983
5984/* Handle the OPT S option. */
5985
5986static void
31302357 5987opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5988{
5989 listing_list (on);
5990}
5991
5992/* Handle the OPT T option. */
5993
5994static void
31302357 5995opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5996{
5997 if (on)
5998 listing |= LISTING_SYMBOLS;
5999 else
8a104df9 6000 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 6001}
6002
6003/* Handle the MRI REG pseudo-op. */
6004
6005static void
31302357 6006s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6007{
6008 char *s;
6009 int c;
6010 struct m68k_op rop;
6011 int mask;
6012 char *stop = NULL;
6013 char stopc;
6014
6015 if (line_label == NULL)
6016 {
6017 as_bad (_("missing label"));
6018 ignore_rest_of_line ();
6019 return;
6020 }
6021
6022 if (flag_mri)
6023 stop = mri_comment_field (&stopc);
6024
6025 SKIP_WHITESPACE ();
6026
6027 s = input_line_pointer;
3882b010 6028 while (ISALNUM (*input_line_pointer)
252b5132
RH		 6029#ifdef REGISTER_PREFIX
6030 || *input_line_pointer == REGISTER_PREFIX
6031#endif
6032 || *input_line_pointer == '/'
6033 || *input_line_pointer == '-')
6034 ++input_line_pointer;
6035 c = *input_line_pointer;
6036 *input_line_pointer = '\0';
6037
6038 if (m68k_ip_op (s, &rop) != 0)
6039 {
6040 if (rop.error == NULL)
6041 as_bad (_("bad register list"));
6042 else
6043 as_bad (_("bad register list: %s"), rop.error);
6044 *input_line_pointer = c;
6045 ignore_rest_of_line ();
6046 return;
6047 }
6048
6049 *input_line_pointer = c;
6050
6051 if (rop.mode == REGLST)
6052 mask = rop.mask;
6053 else if (rop.mode == DREG)
6054 mask = 1 << (rop.reg - DATA0);
6055 else if (rop.mode == AREG)
6056 mask = 1 << (rop.reg - ADDR0 + 8);
6057 else if (rop.mode == FPREG)
6058 mask = 1 << (rop.reg - FP0 + 16);
6059 else if (rop.mode == CONTROL
6060 && rop.reg == FPI)
6061 mask = 1 << 24;
6062 else if (rop.mode == CONTROL
6063 && rop.reg == FPS)
6064 mask = 1 << 25;
6065 else if (rop.mode == CONTROL
6066 && rop.reg == FPC)
6067 mask = 1 << 26;
6068 else
6069 {
6070 as_bad (_("bad register list"));
6071 ignore_rest_of_line ();
6072 return;
6073 }
6074
6075 S_SET_SEGMENT (line_label, reg_section);
6076 S_SET_VALUE (line_label, ~mask);
49309057 6077 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 6078
6079 if (flag_mri)
6080 mri_comment_end (stop, stopc);
6081
6082 demand_empty_rest_of_line ();
6083}
6084
6085/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6086
6087struct save_opts
6088{
6089 struct save_opts *next;
6090 int abspcadd;
6091 int symbols_case_sensitive;
6092 int keep_locals;
6093 int short_refs;
6094 int architecture;
2da12c60 6095 const enum m68k_register *control_regs;
252b5132
RH		 6096 int quick;
6097 int rel32;
6098 int listing;
6099 int no_warnings;
6100 /* FIXME: We don't save OPT S. */
6101};
6102
6103/* This variable holds the stack of saved options. */
6104
6105static struct save_opts *save_stack;
6106
6107/* The MRI SAVE pseudo-op. */
6108
6109static void
31302357 6110s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6111{
6112 struct save_opts *s;
6113
6114 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
6115 s->abspcadd = m68k_abspcadd;
6116 s->symbols_case_sensitive = symbols_case_sensitive;
6117 s->keep_locals = flag_keep_locals;
6118 s->short_refs = flag_short_refs;
6119 s->architecture = current_architecture;
2da12c60 6120 s->control_regs = control_regs;
252b5132
RH		 6121 s->quick = m68k_quick;
6122 s->rel32 = m68k_rel32;
6123 s->listing = listing;
6124 s->no_warnings = flag_no_warnings;
6125
6126 s->next = save_stack;
6127 save_stack = s;
6128
6129 demand_empty_rest_of_line ();
6130}
6131
6132/* The MRI RESTORE pseudo-op. */
6133
6134static void
31302357 6135s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6136{
6137 struct save_opts *s;
6138
6139 if (save_stack == NULL)
6140 {
6141 as_bad (_("restore without save"));
6142 ignore_rest_of_line ();
6143 return;
6144 }
6145
6146 s = save_stack;
6147 save_stack = s->next;
6148
6149 m68k_abspcadd = s->abspcadd;
6150 symbols_case_sensitive = s->symbols_case_sensitive;
6151 flag_keep_locals = s->keep_locals;
6152 flag_short_refs = s->short_refs;
6153 current_architecture = s->architecture;
2da12c60 6154 control_regs = s->control_regs;
252b5132
RH		 6155 m68k_quick = s->quick;
6156 m68k_rel32 = s->rel32;
6157 listing = s->listing;
6158 flag_no_warnings = s->no_warnings;
6159
6160 free (s);
6161
6162 demand_empty_rest_of_line ();
6163}
6164
6165/* Types of MRI structured control directives. */
6166
6167enum mri_control_type
6168{
6169 mri_for,
6170 mri_if,
6171 mri_repeat,
6172 mri_while
6173};
6174
6175/* This structure is used to stack the MRI structured control
6176 directives. */
6177
6178struct mri_control_info
6179{
6180 /* The directive within which this one is enclosed. */
6181 struct mri_control_info *outer;
6182
6183 /* The type of directive. */
6184 enum mri_control_type type;
6185
6186 /* Whether an ELSE has been in an IF. */
6187 int else_seen;
6188
6189 /* The add or sub statement at the end of a FOR. */
6190 char *incr;
6191
6192 /* The label of the top of a FOR or REPEAT loop. */
6193 char *top;
6194
6195 /* The label to jump to for the next iteration, or the else
6196 expression of a conditional. */
6197 char *next;
6198
6199 /* The label to jump to to break out of the loop, or the label past
6200 the end of a conditional. */
6201 char *bottom;
6202};
6203
6204/* The stack of MRI structured control directives. */
6205
6206static struct mri_control_info *mri_control_stack;
6207
6208/* The current MRI structured control directive index number, used to
6209 generate label names. */
6210
6211static int mri_control_index;
6212
252b5132
RH		 6213/* Assemble an instruction for an MRI structured control directive. */
6214
6215static void
31302357 6216mri_assemble (char *str)
252b5132
RH		 6217{
6218 char *s;
6219
6220 /* md_assemble expects the opcode to be in lower case. */
6221 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6222 *s = TOLOWER (*s);
252b5132
RH		 6223
6224 md_assemble (str);
6225}
6226
6227/* Generate a new MRI label structured control directive label name. */
6228
6229static char *
31302357 6230mri_control_label (void)
252b5132
RH		 6231{
6232 char *n;
6233
6234 n = (char *) xmalloc (20);
6235 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6236 ++mri_control_index;
6237 return n;
6238}
6239
6240/* Create a new MRI structured control directive. */
6241
6242static struct mri_control_info *
31302357 6243push_mri_control (enum mri_control_type type)
252b5132
RH		 6244{
6245 struct mri_control_info *n;
6246
6247 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6248
6249 n->type = type;
6250 n->else_seen = 0;
6251 if (type == mri_if || type == mri_while)
6252 n->top = NULL;
6253 else
6254 n->top = mri_control_label ();
6255 n->next = mri_control_label ();
6256 n->bottom = mri_control_label ();
6257
6258 n->outer = mri_control_stack;
6259 mri_control_stack = n;
6260
6261 return n;
6262}
6263
6264/* Pop off the stack of MRI structured control directives. */
6265
6266static void
31302357 6267pop_mri_control (void)
252b5132
RH		 6268{
6269 struct mri_control_info *n;
6270
6271 n = mri_control_stack;
6272 mri_control_stack = n->outer;
6273 if (n->top != NULL)
6274 free (n->top);
6275 free (n->next);
6276 free (n->bottom);
6277 free (n);
6278}
6279
6280/* Recognize a condition code in an MRI structured control expression. */
6281
6282static int
31302357 6283parse_mri_condition (int *pcc)
252b5132
RH		 6284{
6285 char c1, c2;
6286
6287 know (*input_line_pointer == '<');
6288
6289 ++input_line_pointer;
6290 c1 = *input_line_pointer++;
6291 c2 = *input_line_pointer++;
6292
6293 if (*input_line_pointer != '>')
6294 {
6295 as_bad (_("syntax error in structured control directive"));
6296 return 0;
6297 }
6298
6299 ++input_line_pointer;
6300 SKIP_WHITESPACE ();
6301
3882b010
L		 6302 c1 = TOLOWER (c1);
6303 c2 = TOLOWER (c2);
252b5132
RH		 6304
6305 *pcc = (c1 << 8) | c2;
6306
6307 return 1;
6308}
6309
6310/* Parse a single operand in an MRI structured control expression. */
6311
6312static int
31302357
AS		 6313parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6314 char **rightstart, char **rightstop)
252b5132
RH		 6315{
6316 char *s;
6317
6318 SKIP_WHITESPACE ();
6319
6320 *pcc = -1;
6321 *leftstart = NULL;
6322 *leftstop = NULL;
6323 *rightstart = NULL;
6324 *rightstop = NULL;
6325
6326 if (*input_line_pointer == '<')
6327 {
6328 /* It's just a condition code. */
6329 return parse_mri_condition (pcc);
6330 }
6331
6332 /* Look ahead for the condition code. */
6333 for (s = input_line_pointer; *s != '\0'; ++s)
6334 {
6335 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6336 break;
6337 }
6338 if (*s == '\0')
6339 {
6340 as_bad (_("missing condition code in structured control directive"));
6341 return 0;
6342 }
6343
6344 *leftstart = input_line_pointer;
6345 *leftstop = s;
6346 if (*leftstop > *leftstart
6347 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6348 --*leftstop;
6349
6350 input_line_pointer = s;
6351 if (! parse_mri_condition (pcc))
6352 return 0;
6353
6354 /* Look ahead for AND or OR or end of line. */
6355 for (s = input_line_pointer; *s != '\0'; ++s)
6356 {
e1f44d10
NC		 6357 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6358 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6359 ^^^ ^^ */
8a104df9
KH		 6360 if ((s == input_line_pointer
6361 || *(s-1) == ' '
6362 || *(s-1) == '\t')
6363 && ((strncasecmp (s, "AND", 3) == 0
6364 && (s[3] == '.' || ! is_part_of_name (s[3])))
6365 || (strncasecmp (s, "OR", 2) == 0
6366 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6367 break;
252b5132
RH		 6368 }
6369
6370 *rightstart = input_line_pointer;
6371 *rightstop = s;
6372 if (*rightstop > *rightstart
6373 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6374 --*rightstop;
6375
6376 input_line_pointer = s;
6377
6378 return 1;
6379}
6380
6381#define MCC(b1, b2) (((b1) << 8) | (b2))
6382
6383/* Swap the sense of a condition. This changes the condition so that
6384 it generates the same result when the operands are swapped. */
6385
6386static int
31302357 6387swap_mri_condition (int cc)
252b5132
RH		 6388{
6389 switch (cc)
6390 {
6391 case MCC ('h', 'i'): return MCC ('c', 's');
6392 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6393 /* <HS> is an alias for <CC>. */
e1f44d10 6394 case MCC ('h', 's'):
252b5132 6395 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6396 /* <LO> is an alias for <CS>. */
e1f44d10 6397 case MCC ('l', 'o'):
252b5132
RH		 6398 case MCC ('c', 's'): return MCC ('h', 'i');
6399 case MCC ('p', 'l'): return MCC ('m', 'i');
6400 case MCC ('m', 'i'): return MCC ('p', 'l');
6401 case MCC ('g', 'e'): return MCC ('l', 'e');
6402 case MCC ('l', 't'): return MCC ('g', 't');
6403 case MCC ('g', 't'): return MCC ('l', 't');
6404 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6405 /* Issue a warning for conditions we can not swap. */
8fc4ee9b
AM		 6406 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6407 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
e1f44d10
NC		 6408 case MCC ('v', 'c'):
6409 case MCC ('v', 's'):
6410 default :
6411 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6412 (char) (cc >> 8), (char) (cc));
6413 break;
252b5132
RH		 6414 }
6415 return cc;
6416}
6417
6418/* Reverse the sense of a condition. */
6419
6420static int
31302357 6421reverse_mri_condition (int cc)
252b5132
RH		 6422{
6423 switch (cc)
6424 {
6425 case MCC ('h', 'i'): return MCC ('l', 's');
6426 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6427 /* <HS> is an alias for <CC> */
6428 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6429 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6430 /* <LO> is an alias for <CS> */
6431 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6432 case MCC ('c', 's'): return MCC ('c', 'c');
6433 case MCC ('n', 'e'): return MCC ('e', 'q');
6434 case MCC ('e', 'q'): return MCC ('n', 'e');
6435 case MCC ('v', 'c'): return MCC ('v', 's');
6436 case MCC ('v', 's'): return MCC ('v', 'c');
6437 case MCC ('p', 'l'): return MCC ('m', 'i');
6438 case MCC ('m', 'i'): return MCC ('p', 'l');
6439 case MCC ('g', 'e'): return MCC ('l', 't');
6440 case MCC ('l', 't'): return MCC ('g', 'e');
6441 case MCC ('g', 't'): return MCC ('l', 'e');
6442 case MCC ('l', 'e'): return MCC ('g', 't');
6443 }
6444 return cc;
6445}
6446
6447/* Build an MRI structured control expression. This generates test
6448 and branch instructions. It goes to TRUELAB if the condition is
6449 true, and to FALSELAB if the condition is false. Exactly one of
6450 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6451 is the size qualifier for the expression. EXTENT is the size to
6452 use for the branch. */
6453
6454static void
31302357
AS		 6455build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6456 char *rightstart, char *rightstop,
6457 const char *truelab, const char *falselab,
6458 int extent)
252b5132
RH		 6459{
6460 char *buf;
6461 char *s;
6462
6463 if (leftstart != NULL)
6464 {
6465 struct m68k_op leftop, rightop;
6466 char c;
6467
6468 /* Swap the compare operands, if necessary, to produce a legal
6469 m68k compare instruction. Comparing a register operand with
6470 a non-register operand requires the register to be on the
6471 right (cmp, cmpa). Comparing an immediate value with
6472 anything requires the immediate value to be on the left
6473 (cmpi). */
6474
6475 c = *leftstop;
6476 *leftstop = '\0';
6477 (void) m68k_ip_op (leftstart, &leftop);
6478 *leftstop = c;
6479
6480 c = *rightstop;
6481 *rightstop = '\0';
6482 (void) m68k_ip_op (rightstart, &rightop);
6483 *rightstop = c;
6484
6485 if (rightop.mode == IMMED
6486 || ((leftop.mode == DREG || leftop.mode == AREG)
6487 && (rightop.mode != DREG && rightop.mode != AREG)))
6488 {
6489 char *temp;
6490
31302357
AS		 6491 /* Correct conditional handling:
6492 if #1 <lt> d0 then ;means if (1 < d0)
6493 ...
6494 endi
e1f44d10 6495
31302357 6496 should assemble to:
e1f44d10 6497
31302357
AS		 6498 cmp #1,d0 if we do *not* swap the operands
6499 bgt true we need the swapped condition!
6500 ble false
6501 true:
6502 ...
6503 false:
6504 */
252b5132
RH		 6505 temp = leftstart;
6506 leftstart = rightstart;
6507 rightstart = temp;
6508 temp = leftstop;
6509 leftstop = rightstop;
6510 rightstop = temp;
8a104df9
KH		 6511 }
6512 else
6513 {
e1f44d10 6514 cc = swap_mri_condition (cc);
252b5132
RH		 6515 }
6516 }
6517
6518 if (truelab == NULL)
6519 {
6520 cc = reverse_mri_condition (cc);
6521 truelab = falselab;
6522 }
92774660 6523
252b5132
RH		 6524 if (leftstart != NULL)
6525 {
6526 buf = (char *) xmalloc (20
6527 + (leftstop - leftstart)
6528 + (rightstop - rightstart));
6529 s = buf;
6530 *s++ = 'c';
6531 *s++ = 'm';
6532 *s++ = 'p';
6533 if (qual != '\0')
3882b010 6534 *s++ = TOLOWER (qual);
252b5132
RH		 6535 *s++ = ' ';
6536 memcpy (s, leftstart, leftstop - leftstart);
6537 s += leftstop - leftstart;
6538 *s++ = ',';
6539 memcpy (s, rightstart, rightstop - rightstart);
6540 s += rightstop - rightstart;
6541 *s = '\0';
6542 mri_assemble (buf);
6543 free (buf);
6544 }
92774660 6545
252b5132
RH		 6546 buf = (char *) xmalloc (20 + strlen (truelab));
6547 s = buf;
6548 *s++ = 'b';
6549 *s++ = cc >> 8;
6550 *s++ = cc & 0xff;
6551 if (extent != '\0')
3882b010 6552 *s++ = TOLOWER (extent);
252b5132
RH		 6553 *s++ = ' ';
6554 strcpy (s, truelab);
6555 mri_assemble (buf);
6556 free (buf);
6557}
6558
6559/* Parse an MRI structured control expression. This generates test
6560 and branch instructions. STOP is where the expression ends. It
6561 goes to TRUELAB if the condition is true, and to FALSELAB if the
6562 condition is false. Exactly one of TRUELAB and FALSELAB will be
6563 NULL, meaning to fall through. QUAL is the size qualifier for the
6564 expression. EXTENT is the size to use for the branch. */
6565
6566static void
31302357
AS		 6567parse_mri_control_expression (char *stop, int qual, const char *truelab,
6568 const char *falselab, int extent)
252b5132
RH		 6569{
6570 int c;
6571 int cc;
6572 char *leftstart;
6573 char *leftstop;
6574 char *rightstart;
6575 char *rightstop;
6576
6577 c = *stop;
6578 *stop = '\0';
6579
6580 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6581 &rightstart, &rightstop))
6582 {
6583 *stop = c;
6584 return;
6585 }
6586
6587 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6588 {
6589 const char *flab;
6590
6591 if (falselab != NULL)
6592 flab = falselab;
6593 else
6594 flab = mri_control_label ();
6595
6596 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6597 rightstop, (const char *) NULL, flab, extent);
6598
6599 input_line_pointer += 3;
6600 if (*input_line_pointer != '.'
6601 || input_line_pointer[1] == '\0')
6602 qual = '\0';
6603 else
6604 {
6605 qual = input_line_pointer[1];
6606 input_line_pointer += 2;
6607 }
6608
6609 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6610 &rightstart, &rightstop))
6611 {
6612 *stop = c;
6613 return;
6614 }
6615
6616 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6617 rightstop, truelab, falselab, extent);
6618
6619 if (falselab == NULL)
6620 colon (flab);
6621 }
6622 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6623 {
6624 const char *tlab;
6625
6626 if (truelab != NULL)
6627 tlab = truelab;
6628 else
6629 tlab = mri_control_label ();
6630
6631 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6632 rightstop, tlab, (const char *) NULL, extent);
6633
6634 input_line_pointer += 2;
6635 if (*input_line_pointer != '.'
6636 || input_line_pointer[1] == '\0')
6637 qual = '\0';
6638 else
6639 {
6640 qual = input_line_pointer[1];
6641 input_line_pointer += 2;
6642 }
6643
6644 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6645 &rightstart, &rightstop))
6646 {
6647 *stop = c;
6648 return;
6649 }
6650
6651 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6652 rightstop, truelab, falselab, extent);
6653
6654 if (truelab == NULL)
6655 colon (tlab);
6656 }
6657 else
6658 {
6659 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6660 rightstop, truelab, falselab, extent);
6661 }
6662
6663 *stop = c;
6664 if (input_line_pointer != stop)
6665 as_bad (_("syntax error in structured control directive"));
6666}
6667
6668/* Handle the MRI IF pseudo-op. This may be a structured control
6669 directive, or it may be a regular assembler conditional, depending
6670 on its operands. */
6671
6672static void
31302357 6673s_mri_if (int qual)
252b5132
RH		 6674{
6675 char *s;
6676 int c;
6677 struct mri_control_info *n;
6678
6679 /* A structured control directive must end with THEN with an
6680 optional qualifier. */
6681 s = input_line_pointer;
e1f44d10
NC		 6682 /* We only accept '*' as introduction of comments if preceded by white space
6683 or at first column of a line (I think this can't actually happen here?)
6684 This is important when assembling:
6685 if d0 <ne> 12(a0,d0*2) then
36759679 6686 if d0 <ne> #CONST*20 then. */
31302357
AS		 6687 while (! (is_end_of_line[(unsigned char) *s]
6688 || (flag_mri
6689 && *s == '*'
6690 && (s == input_line_pointer
6691 || *(s-1) == ' '
6692 || *(s-1) == '\t'))))
252b5132
RH		 6693 ++s;
6694 --s;
6695 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6696 --s;
6697
6698 if (s - input_line_pointer > 1
6699 && s[-1] == '.')
6700 s -= 2;
6701
6702 if (s - input_line_pointer < 3
6703 || strncasecmp (s - 3, "THEN", 4) != 0)
6704 {
6705 if (qual != '\0')
6706 {
6707 as_bad (_("missing then"));
6708 ignore_rest_of_line ();
6709 return;
6710 }
6711
6712 /* It's a conditional. */
6713 s_if (O_ne);
6714 return;
6715 }
6716
6717 /* Since this might be a conditional if, this pseudo-op will be
6718 called even if we are supported to be ignoring input. Double
6719 check now. Clobber *input_line_pointer so that ignore_input
6720 thinks that this is not a special pseudo-op. */
6721 c = *input_line_pointer;
6722 *input_line_pointer = 0;
6723 if (ignore_input ())
6724 {
6725 *input_line_pointer = c;
6726 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6727 ++input_line_pointer;
6728 demand_empty_rest_of_line ();
6729 return;
6730 }
6731 *input_line_pointer = c;
6732
6733 n = push_mri_control (mri_if);
6734
6735 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6736 n->next, s[1] == '.' ? s[2] : '\0');
6737
6738 if (s[1] == '.')
6739 input_line_pointer = s + 3;
6740 else
6741 input_line_pointer = s + 1;
6742
6743 if (flag_mri)
6744 {
6745 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6746 ++input_line_pointer;
6747 }
6748
6749 demand_empty_rest_of_line ();
6750}
6751
6752/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6753 structured IF, associate the ELSE with the IF. Otherwise, assume
6754 it is a conditional else. */
6755
6756static void
31302357 6757s_mri_else (int qual)
252b5132
RH		 6758{
6759 int c;
6760 char *buf;
6761 char q[2];
6762
6763 if (qual == '\0'
6764 && (mri_control_stack == NULL
6765 || mri_control_stack->type != mri_if
6766 || mri_control_stack->else_seen))
6767 {
6768 s_else (0);
6769 return;
6770 }
6771
6772 c = *input_line_pointer;
6773 *input_line_pointer = 0;
6774 if (ignore_input ())
6775 {
6776 *input_line_pointer = c;
6777 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6778 ++input_line_pointer;
6779 demand_empty_rest_of_line ();
6780 return;
6781 }
6782 *input_line_pointer = c;
6783
6784 if (mri_control_stack == NULL
6785 || mri_control_stack->type != mri_if
6786 || mri_control_stack->else_seen)
6787 {
6788 as_bad (_("else without matching if"));
6789 ignore_rest_of_line ();
6790 return;
6791 }
6792
6793 mri_control_stack->else_seen = 1;
6794
6795 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6796 q[0] = TOLOWER (qual);
252b5132
RH		 6797 q[1] = '\0';
6798 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6799 mri_assemble (buf);
6800 free (buf);
6801
6802 colon (mri_control_stack->next);
6803
6804 if (flag_mri)
6805 {
6806 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6807 ++input_line_pointer;
6808 }
6809
6810 demand_empty_rest_of_line ();
6811}
6812
6813/* Handle the MRI ENDI pseudo-op. */
6814
6815static void
31302357 6816s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6817{
6818 if (mri_control_stack == NULL
6819 || mri_control_stack->type != mri_if)
6820 {
6821 as_bad (_("endi without matching if"));
6822 ignore_rest_of_line ();
6823 return;
6824 }
6825
6826 /* ignore_input will not return true for ENDI, so we don't need to
6827 worry about checking it again here. */
6828
6829 if (! mri_control_stack->else_seen)
6830 colon (mri_control_stack->next);
6831 colon (mri_control_stack->bottom);
6832
6833 pop_mri_control ();
6834
6835 if (flag_mri)
6836 {
6837 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6838 ++input_line_pointer;
6839 }
6840
6841 demand_empty_rest_of_line ();
6842}
6843
6844/* Handle the MRI BREAK pseudo-op. */
6845
6846static void
31302357 6847s_mri_break (int extent)
252b5132
RH		 6848{
6849 struct mri_control_info *n;
6850 char *buf;
6851 char ex[2];
6852
6853 n = mri_control_stack;
6854 while (n != NULL
6855 && n->type != mri_for
6856 && n->type != mri_repeat
6857 && n->type != mri_while)
6858 n = n->outer;
6859 if (n == NULL)
6860 {
6861 as_bad (_("break outside of structured loop"));
6862 ignore_rest_of_line ();
6863 return;
6864 }
6865
6866 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6867 ex[0] = TOLOWER (extent);
252b5132
RH		 6868 ex[1] = '\0';
6869 sprintf (buf, "bra%s %s", ex, n->bottom);
6870 mri_assemble (buf);
6871 free (buf);
6872
6873 if (flag_mri)
6874 {
6875 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6876 ++input_line_pointer;
6877 }
6878
6879 demand_empty_rest_of_line ();
6880}
6881
6882/* Handle the MRI NEXT pseudo-op. */
6883
6884static void
31302357 6885s_mri_next (int extent)
252b5132
RH		 6886{
6887 struct mri_control_info *n;
6888 char *buf;
6889 char ex[2];
6890
6891 n = mri_control_stack;
6892 while (n != NULL
6893 && n->type != mri_for
6894 && n->type != mri_repeat
6895 && n->type != mri_while)
6896 n = n->outer;
6897 if (n == NULL)
6898 {
6899 as_bad (_("next outside of structured loop"));
6900 ignore_rest_of_line ();
6901 return;
6902 }
6903
6904 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6905 ex[0] = TOLOWER (extent);
252b5132
RH		 6906 ex[1] = '\0';
6907 sprintf (buf, "bra%s %s", ex, n->next);
6908 mri_assemble (buf);
6909 free (buf);
6910
6911 if (flag_mri)
6912 {
6913 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6914 ++input_line_pointer;
6915 }
6916
6917 demand_empty_rest_of_line ();
6918}
6919
6920/* Handle the MRI FOR pseudo-op. */
6921
6922static void
31302357 6923s_mri_for (int qual)
252b5132
RH		 6924{
6925 const char *varstart, *varstop;
6926 const char *initstart, *initstop;
6927 const char *endstart, *endstop;
6928 const char *bystart, *bystop;
6929 int up;
6930 int by;
6931 int extent;
6932 struct mri_control_info *n;
6933 char *buf;
6934 char *s;
6935 char ex[2];
6936
6937 /* The syntax is
6938 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6939 */
6940
6941 SKIP_WHITESPACE ();
6942 varstart = input_line_pointer;
6943
6944 /* Look for the '='. */
6945 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6946 && *input_line_pointer != '=')
6947 ++input_line_pointer;
6948 if (*input_line_pointer != '=')
6949 {
6950 as_bad (_("missing ="));
6951 ignore_rest_of_line ();
6952 return;
6953 }
6954
6955 varstop = input_line_pointer;
6956 if (varstop > varstart
6957 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6958 --varstop;
6959
6960 ++input_line_pointer;
6961
6962 initstart = input_line_pointer;
6963
6964 /* Look for TO or DOWNTO. */
6965 up = 1;
6966 initstop = NULL;
6967 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6968 {
6969 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6970 && ! is_part_of_name (input_line_pointer[2]))
6971 {
6972 initstop = input_line_pointer;
6973 input_line_pointer += 2;
6974 break;
6975 }
6976 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6977 && ! is_part_of_name (input_line_pointer[6]))
6978 {
6979 initstop = input_line_pointer;
6980 up = 0;
6981 input_line_pointer += 6;
6982 break;
6983 }
6984 ++input_line_pointer;
6985 }
6986 if (initstop == NULL)
6987 {
6988 as_bad (_("missing to or downto"));
6989 ignore_rest_of_line ();
6990 return;
6991 }
6992 if (initstop > initstart
6993 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6994 --initstop;
6995
6996 SKIP_WHITESPACE ();
6997 endstart = input_line_pointer;
6998
6999 /* Look for BY or DO. */
7000 by = 0;
7001 endstop = NULL;
7002 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7003 {
7004 if (strncasecmp (input_line_pointer, "BY", 2) == 0
7005 && ! is_part_of_name (input_line_pointer[2]))
7006 {
7007 endstop = input_line_pointer;
7008 by = 1;
7009 input_line_pointer += 2;
7010 break;
7011 }
7012 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7013 && (input_line_pointer[2] == '.'
7014 || ! is_part_of_name (input_line_pointer[2])))
7015 {
7016 endstop = input_line_pointer;
7017 input_line_pointer += 2;
7018 break;
7019 }
7020 ++input_line_pointer;
7021 }
7022 if (endstop == NULL)
7023 {
7024 as_bad (_("missing do"));
7025 ignore_rest_of_line ();
7026 return;
7027 }
7028 if (endstop > endstart
7029 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
7030 --endstop;
7031
7032 if (! by)
7033 {
7034 bystart = "#1";
7035 bystop = bystart + 2;
7036 }
7037 else
7038 {
7039 SKIP_WHITESPACE ();
7040 bystart = input_line_pointer;
7041
7042 /* Look for DO. */
7043 bystop = NULL;
7044 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7045 {
7046 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7047 && (input_line_pointer[2] == '.'
7048 || ! is_part_of_name (input_line_pointer[2])))
7049 {
7050 bystop = input_line_pointer;
7051 input_line_pointer += 2;
7052 break;
7053 }
7054 ++input_line_pointer;
7055 }
7056 if (bystop == NULL)
7057 {
7058 as_bad (_("missing do"));
7059 ignore_rest_of_line ();
7060 return;
7061 }
7062 if (bystop > bystart
7063 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
7064 --bystop;
7065 }
7066
7067 if (*input_line_pointer != '.')
7068 extent = '\0';
7069 else
7070 {
7071 extent = input_line_pointer[1];
7072 input_line_pointer += 2;
7073 }
7074
7075 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 7076 n = push_mri_control (mri_for);
7077
7078 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
7079
36759679 7080 /* Move init,var. */
252b5132
RH		 7081 s = buf;
7082 *s++ = 'm';
7083 *s++ = 'o';
7084 *s++ = 'v';
7085 *s++ = 'e';
7086 if (qual != '\0')
3882b010 7087 *s++ = TOLOWER (qual);
252b5132
RH		 7088 *s++ = ' ';
7089 memcpy (s, initstart, initstop - initstart);
7090 s += initstop - initstart;
7091 *s++ = ',';
7092 memcpy (s, varstart, varstop - varstart);
7093 s += varstop - varstart;
7094 *s = '\0';
7095 mri_assemble (buf);
7096
7097 colon (n->top);
7098
36759679 7099 /* cmp end,var. */
252b5132
RH		 7100 s = buf;
7101 *s++ = 'c';
7102 *s++ = 'm';
7103 *s++ = 'p';
7104 if (qual != '\0')
3882b010 7105 *s++ = TOLOWER (qual);
252b5132
RH		 7106 *s++ = ' ';
7107 memcpy (s, endstart, endstop - endstart);
7108 s += endstop - endstart;
7109 *s++ = ',';
7110 memcpy (s, varstart, varstop - varstart);
7111 s += varstop - varstart;
7112 *s = '\0';
7113 mri_assemble (buf);
7114
36759679 7115 /* bcc bottom. */
3882b010 7116 ex[0] = TOLOWER (extent);
252b5132
RH		 7117 ex[1] = '\0';
7118 if (up)
7119 sprintf (buf, "blt%s %s", ex, n->bottom);
7120 else
7121 sprintf (buf, "bgt%s %s", ex, n->bottom);
7122 mri_assemble (buf);
7123
7124 /* Put together the add or sub instruction used by ENDF. */
7125 s = buf;
7126 if (up)
7127 strcpy (s, "add");
7128 else
7129 strcpy (s, "sub");
7130 s += 3;
7131 if (qual != '\0')
3882b010 7132 *s++ = TOLOWER (qual);
252b5132
RH		 7133 *s++ = ' ';
7134 memcpy (s, bystart, bystop - bystart);
7135 s += bystop - bystart;
7136 *s++ = ',';
7137 memcpy (s, varstart, varstop - varstart);
7138 s += varstop - varstart;
7139 *s = '\0';
7140 n->incr = buf;
7141
7142 if (flag_mri)
7143 {
7144 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7145 ++input_line_pointer;
7146 }
7147
7148 demand_empty_rest_of_line ();
7149}
7150
7151/* Handle the MRI ENDF pseudo-op. */
7152
7153static void
31302357 7154s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7155{
7156 if (mri_control_stack == NULL
7157 || mri_control_stack->type != mri_for)
7158 {
7159 as_bad (_("endf without for"));
7160 ignore_rest_of_line ();
7161 return;
7162 }
7163
7164 colon (mri_control_stack->next);
7165
7166 mri_assemble (mri_control_stack->incr);
7167
7168 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7169 mri_assemble (mri_control_stack->incr);
7170
7171 free (mri_control_stack->incr);
7172
7173 colon (mri_control_stack->bottom);
7174
7175 pop_mri_control ();
7176
7177 if (flag_mri)
7178 {
7179 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7180 ++input_line_pointer;
7181 }
7182
7183 demand_empty_rest_of_line ();
7184}
7185
7186/* Handle the MRI REPEAT pseudo-op. */
7187
7188static void
31302357 7189s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7190{
7191 struct mri_control_info *n;
7192
7193 n = push_mri_control (mri_repeat);
7194 colon (n->top);
7195 if (flag_mri)
7196 {
7197 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7198 ++input_line_pointer;
7199 }
7200 demand_empty_rest_of_line ();
7201}
7202
7203/* Handle the MRI UNTIL pseudo-op. */
7204
7205static void
31302357 7206s_mri_until (int qual)
252b5132
RH		 7207{
7208 char *s;
7209
7210 if (mri_control_stack == NULL
7211 || mri_control_stack->type != mri_repeat)
7212 {
7213 as_bad (_("until without repeat"));
7214 ignore_rest_of_line ();
7215 return;
7216 }
7217
7218 colon (mri_control_stack->next);
7219
7220 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7221 ;
7222
7223 parse_mri_control_expression (s, qual, (const char *) NULL,
7224 mri_control_stack->top, '\0');
7225
7226 colon (mri_control_stack->bottom);
7227
7228 input_line_pointer = s;
7229
7230 pop_mri_control ();
7231
7232 if (flag_mri)
7233 {
7234 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7235 ++input_line_pointer;
7236 }
7237
7238 demand_empty_rest_of_line ();
7239}
7240
7241/* Handle the MRI WHILE pseudo-op. */
7242
7243static void
31302357 7244s_mri_while (int qual)
252b5132
RH		 7245{
7246 char *s;
7247
7248 struct mri_control_info *n;
7249
7250 s = input_line_pointer;
e1f44d10
NC		 7251 /* We only accept '*' as introduction of comments if preceded by white space
7252 or at first column of a line (I think this can't actually happen here?)
7253 This is important when assembling:
7254 while d0 <ne> 12(a0,d0*2) do
36759679 7255 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7256 while (! (is_end_of_line[(unsigned char) *s]
7257 || (flag_mri
7258 && *s == '*'
7259 && (s == input_line_pointer
7260 || *(s-1) == ' '
7261 || *(s-1) == '\t'))))
252b5132
RH		 7262 s++;
7263 --s;
7264 while (*s == ' ' || *s == '\t')
7265 --s;
7266 if (s - input_line_pointer > 1
7267 && s[-1] == '.')
7268 s -= 2;
7269 if (s - input_line_pointer < 2
7270 || strncasecmp (s - 1, "DO", 2) != 0)
7271 {
7272 as_bad (_("missing do"));
7273 ignore_rest_of_line ();
7274 return;
7275 }
7276
7277 n = push_mri_control (mri_while);
7278
7279 colon (n->next);
7280
7281 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7282 s[1] == '.' ? s[2] : '\0');
7283
7284 input_line_pointer = s + 1;
7285 if (*input_line_pointer == '.')
7286 input_line_pointer += 2;
7287
7288 if (flag_mri)
7289 {
7290 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7291 ++input_line_pointer;
7292 }
7293
7294 demand_empty_rest_of_line ();
7295}
7296
7297/* Handle the MRI ENDW pseudo-op. */
7298
7299static void
31302357 7300s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7301{
7302 char *buf;
7303
7304 if (mri_control_stack == NULL
7305 || mri_control_stack->type != mri_while)
7306 {
7307 as_bad (_("endw without while"));
7308 ignore_rest_of_line ();
7309 return;
7310 }
7311
7312 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7313 sprintf (buf, "bra %s", mri_control_stack->next);
7314 mri_assemble (buf);
7315 free (buf);
7316
7317 colon (mri_control_stack->bottom);
7318
7319 pop_mri_control ();
7320
7321 if (flag_mri)
7322 {
7323 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7324 ++input_line_pointer;
7325 }
7326
7327 demand_empty_rest_of_line ();
7328}
7329\f
266abb8f
NS		 7330/* Parse a .cpu directive. */
7331
7332static void
7333s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7334{
7335 char saved_char;
7336 char *name;
7337
7338 if (initialized)
7339 {
7340 as_bad (_("already assembled instructions"));
7341 ignore_rest_of_line ();
7342 return;
7343 }
7344
7345 name = input_line_pointer;
7346 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7347 input_line_pointer++;
7348 saved_char = *input_line_pointer;
7349 *input_line_pointer = 0;
7350
7351 m68k_set_cpu (name, 1, 0);
7352
7353 *input_line_pointer = saved_char;
7354 demand_empty_rest_of_line ();
7355 return;
7356}
7357
7358/* Parse a .arch directive. */
7359
7360static void
7361s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7362{
7363 char saved_char;
7364 char *name;
7365
7366 if (initialized)
7367 {
7368 as_bad (_("already assembled instructions"));
7369 ignore_rest_of_line ();
7370 return;
7371 }
7372
7373 name = input_line_pointer;
7374 while (*input_line_pointer && *input_line_pointer != ','
7375 && !ISSPACE (*input_line_pointer))
7376 input_line_pointer++;
7377 saved_char = *input_line_pointer;
7378 *input_line_pointer = 0;
7379
7380 if (m68k_set_arch (name, 1, 0))
7381 {
7382 /* Scan extensions. */
7383 do
7384 {
7385 *input_line_pointer++ = saved_char;
7386 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7387 break;
7388 name = input_line_pointer;
7389 while (*input_line_pointer && *input_line_pointer != ','
7390 && !ISSPACE (*input_line_pointer))
7391 input_line_pointer++;
7392 saved_char = *input_line_pointer;
7393 *input_line_pointer = 0;
7394 }
7395 while (m68k_set_extension (name, 1, 0));
7396 }
7397
7398 *input_line_pointer = saved_char;
7399 demand_empty_rest_of_line ();
7400 return;
7401}
7402\f
7403/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7404 if none is found, the caller is responsible for emitting an error
7405 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7406 cpu name, if it begins with a '6' (possibly skipping an intervening
7407 'c'. We also allow a 'c' in the same place. if NEGATED is
7408 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7409 the option is indeed negated. */
7410
7411static const struct m68k_cpu *
7412m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7413 int allow_m, int *negated)
7414{
7415 /* allow negated value? */
7416 if (negated)
7417 {
7418 *negated = 0;
7419
7420 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7421 {
7422 arg += 3;
7423 *negated = 1;
7424 }
7425 }
7426
7427 /* Remove 'm' or 'mc' prefix from 68k variants. */
7428 if (allow_m)
7429 {
7430 if (arg[0] == 'm')
7431 {
7432 if (arg[1] == '6')
7433 arg += 1;
7434 else if (arg[1] == 'c' && arg[2] == '6')
7435 arg += 2;
7436 }
7437 }
7438 else if (arg[0] == 'c' && arg[1] == '6')
7439 arg += 1;
7440
7441 for (; table->name; table++)
7442 if (!strcmp (arg, table->name))
2da12c60
NS		 7443 {
7444 if (table->alias < -1 || table->alias > 1)
7445 as_bad (_("`%s' is deprecated, use `%s'"),
7446 table->name, table[table->alias < 0 ? 1 : -1].name);
7447 return table;
7448 }
266abb8f
NS		 7449 return 0;
7450}
7451
bfbba8e4 7452/* Set the cpu, issuing errors if it is unrecognized. */
266abb8f
NS		 7453
7454static int
7455m68k_set_cpu (char const *name, int allow_m, int silent)
7456{
7457 const struct m68k_cpu *cpu;
7458
7459 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7460
7461 if (!cpu)
7462 {
7463 if (!silent)
7464 as_bad (_("cpu `%s' unrecognized"), name);
7465 return 0;
7466 }
266abb8f
NS		 7467 selected_cpu = cpu;
7468 return 1;
7469}
7470
bfbba8e4 7471/* Set the architecture, issuing errors if it is unrecognized. */
266abb8f
NS		 7472
7473static int
7474m68k_set_arch (char const *name, int allow_m, int silent)
7475{
7476 const struct m68k_cpu *arch;
7477
7478 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7479
7480 if (!arch)
7481 {
7482 if (!silent)
7483 as_bad (_("architecture `%s' unrecognized"), name);
7484 return 0;
7485 }
266abb8f
NS		 7486 selected_arch = arch;
7487 return 1;
7488}
7489
7490/* Set the architecture extension, issuing errors if it is
7491 unrecognized, or invalid */
7492
7493static int
7494m68k_set_extension (char const *name, int allow_m, int silent)
7495{
7496 int negated;
7497 const struct m68k_cpu *ext;
7498
7499 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7500
7501 if (!ext)
7502 {
7503 if (!silent)
7504 as_bad (_("extension `%s' unrecognized"), name);
7505 return 0;
7506 }
7507
7508 if (negated)
87298967
NS		 7509 not_current_architecture |= (ext->control_regs
7510 ? *(unsigned *)ext->control_regs: ext->arch);
266abb8f
NS		 7511 else
7512 current_architecture |= ext->arch;
7513 return 1;
7514}
7515
31302357
AS		 7516/* md_parse_option
7517 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7518 */
252b5132
RH		 7519
7520#ifdef OBJ_ELF
5a38dc70 7521const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7522#else
5a38dc70 7523const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7524#endif
7525
7526struct option md_longopts[] = {
7527#define OPTION_PIC (OPTION_MD_BASE)
7528 {"pic", no_argument, NULL, OPTION_PIC},
7529#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7530 {"register-prefix-optional", no_argument, NULL,
7531 OPTION_REGISTER_PREFIX_OPTIONAL},
7532#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7533 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7534#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7535 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7536#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7537 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7538#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7539 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7540#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7541 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7542#define OPTION_PCREL (OPTION_MD_BASE + 7)
7543 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7544 {NULL, no_argument, NULL, 0}
7545};
bc805888 7546size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7547
7548int
31302357 7549md_parse_option (int c, char *arg)
252b5132
RH		 7550{
7551 switch (c)
7552 {
7553 case 'l': /* -l means keep external to 2 bit offset
36759679 7554 rather than 16 bit one. */
252b5132
RH		 7555 flag_short_refs = 1;
7556 break;
7557
7558 case 'S': /* -S means that jbsr's always turn into
7559 jsr's. */
7560 flag_long_jumps = 1;
7561 break;
7562
28e7409f
NC		 7563 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7564 branches into absolute jumps. */
7565 flag_keep_pcrel = 1;
7566 break;
7567
252b5132
RH		 7568 case OPTION_PIC:
7569 case 'k':
7570 flag_want_pic = 1;
36759679 7571 break; /* -pic, Position Independent Code. */
252b5132
RH		 7572
7573 case OPTION_REGISTER_PREFIX_OPTIONAL:
7574 flag_reg_prefix_optional = 1;
7575 reg_prefix_optional_seen = 1;
7576 break;
7577
7578 /* -V: SVR4 argument to print version ID. */
7579 case 'V':
7580 print_version_id ();
7581 break;
7582
7583 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7584 should be emitted or not. FIXME: Not implemented. */
7585 case 'Q':
7586 break;
7587
7588 case OPTION_BITWISE_OR:
7589 {
7590 char *n, *t;
7591 const char *s;
7592
7593 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7594 t = n;
7595 for (s = m68k_comment_chars; *s != '\0'; s++)
7596 if (*s != '|')
7597 *t++ = *s;
7598 *t = '\0';
7599 m68k_comment_chars = n;
7600 }
7601 break;
7602
7603 case OPTION_BASE_SIZE_DEFAULT_16:
7604 m68k_index_width_default = SIZE_WORD;
7605 break;
7606
7607 case OPTION_BASE_SIZE_DEFAULT_32:
7608 m68k_index_width_default = SIZE_LONG;
7609 break;
7610
7611 case OPTION_DISP_SIZE_DEFAULT_16:
7612 m68k_rel32 = 0;
7613 m68k_rel32_from_cmdline = 1;
7614 break;
7615
7616 case OPTION_DISP_SIZE_DEFAULT_32:
7617 m68k_rel32 = 1;
7618 m68k_rel32_from_cmdline = 1;
7619 break;
7620
266abb8f
NS		 7621 case 'A':
7622#if WARN_DEPRECATED
7623 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7624 arg, arg));
7625#endif
7626 /* Intentional fall-through. */
7627 case 'm':
7628 if (!strncmp (arg, "arch=", 5))
7629 m68k_set_arch (arg + 5, 1, 0);
7630 else if (!strncmp (arg, "cpu=", 4))
7631 m68k_set_cpu (arg + 4, 1, 0);
7632 else if (m68k_set_extension (arg, 0, 1))
7633 ;
0b2e31dc
NS		 7634 else if (m68k_set_arch (arg, 0, 1))
7635 ;
266abb8f
NS		 7636 else if (m68k_set_cpu (arg, 0, 1))
7637 ;
7638 else
7639 return 0;
7640 break;
7641
252b5132
RH		 7642 default:
7643 return 0;
7644 }
7645
7646 return 1;
7647}
7648
266abb8f
NS		 7649/* Setup tables from the selected arch and/or cpu */
7650
7651static void
7652m68k_init_arch (void)
7653{
266abb8f
NS		 7654 if (not_current_architecture & current_architecture)
7655 {
7656 as_bad (_("architecture features both enabled and disabled"));
7657 not_current_architecture &= ~current_architecture;
7658 }
7659 if (selected_arch)
2da12c60
NS		 7660 {
7661 current_architecture |= selected_arch->arch;
7662 control_regs = selected_arch->control_regs;
7663 }
0b2e31dc
NS		 7664 else
7665 current_architecture |= selected_cpu->arch;
0b2e31dc 7666
2da12c60
NS		 7667 current_architecture &= ~not_current_architecture;
7668
377260ba
NS		 7669 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7670 {
7671 /* Determine which float is really meant. */
7672 if (current_architecture & (m68k_mask & ~m68881))
7673 current_architecture ^= cfloat;
7674 else
7675 current_architecture ^= m68881;
7676 }
7677
0b2e31dc 7678 if (selected_cpu)
266abb8f 7679 {
2da12c60 7680 control_regs = selected_cpu->control_regs;
0b2e31dc 7681 if (current_architecture & ~selected_cpu->arch)
266abb8f 7682 {
0b2e31dc
NS		 7683 as_bad (_("selected processor does not have all features of selected architecture"));
7684 current_architecture
7685 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7686 }
7687 }
266abb8f 7688
266abb8f
NS		 7689 if ((current_architecture & m68k_mask)
7690 && (current_architecture & ~m68k_mask))
7691 {
7692 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7693 if (current_architecture & m68k_mask)
266abb8f
NS		 7694 current_architecture &= m68k_mask;
7695 else
7696 current_architecture &= ~m68k_mask;
7697 }
7698
7699 /* Permit m68881 specification with all cpus; those that can't work
7700 with a coprocessor could be doing emulation. */
7701 if (current_architecture & m68851)
7702 {
7703 if (current_architecture & m68040)
7704 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7705 }
7706 /* What other incompatibilities could we check for? */
7707
266abb8f
NS		 7708 if (cpu_of_arch (current_architecture) < m68020
7709 || arch_coldfire_p (current_architecture))
7710 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7711
7712 initialized = 1;
7713}
7714
252b5132 7715void
31302357 7716md_show_usage (FILE *stream)
252b5132 7717{
76f57f3a 7718 const char *default_cpu = TARGET_CPU;
f1f5ef86 7719 int i;
76f57f3a 7720
8a104df9 7721 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7722 if (*default_cpu == 'm')
7723 default_cpu++;
266abb8f 7724 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7725 {
266abb8f 7726 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7727 {
2da12c60
NS		 7728 while (m68k_cpus[i].alias > 0)
7729 i--;
7730 while (m68k_cpus[i].alias < 0)
7731 i++;
7732 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7733 }
7734 }
7735
bc805888 7736 fprintf (stream, _("\
266abb8f
NS		 7737-march=<arch> set architecture\n\
7738-mcpu=<cpu> set cpu [default %s]\n\
7739"), default_cpu);
7740 for (i = 0; m68k_extensions[i].name; i++)
7741 fprintf (stream, _("\
0b2e31dc
NS		 7742-m[no-]%-16s enable/disable%s architecture extension\n\
7743"), m68k_extensions[i].name,
7744 m68k_extensions[i].alias > 0 ? " ColdFire"
7745 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7746
bc805888 7747 fprintf (stream, _("\
266abb8f 7748-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7749-pic, -k generate position independent code\n\
7750-S turn jbsr into jsr\n\
28e7409f 7751--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7752--register-prefix-optional\n\
7753 recognize register names without prefix character\n\
266abb8f 7754--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7755--base-size-default-16 base reg without size is 16 bits\n\
7756--base-size-default-32 base reg without size is 32 bits (default)\n\
7757--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7758--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7759"));
7760
7761 fprintf (stream, _("Architecture variants are: "));
7762 for (i = 0; m68k_archs[i].name; i++)
7763 {
7764 if (i)
7765 fprintf (stream, " | ");
87298967 7766 fprintf (stream, "%s", m68k_archs[i].name);
266abb8f
NS		 7767 }
7768 fprintf (stream, "\n");
7769
7770 fprintf (stream, _("Processor variants are: "));
7771 for (i = 0; m68k_cpus[i].name; i++)
7772 {
7773 if (i)
7774 fprintf (stream, " | ");
87298967 7775 fprintf (stream, "%s", m68k_cpus[i].name);
266abb8f
NS		 7776 }
7777 fprintf (stream, _("\n"));
252b5132
RH		 7778}
7779\f
7780#ifdef TEST2
7781
7782/* TEST2: Test md_assemble() */
36759679
NC		 7783/* Warning, this routine probably doesn't work anymore. */
7784int
31302357 7785main (void)
252b5132
RH		 7786{
7787 struct m68k_it the_ins;
7788 char buf[120];
7789 char *cp;
7790 int n;
7791
7792 m68k_ip_begin ();
7793 for (;;)
7794 {
7795 if (!gets (buf) || !*buf)
7796 break;
7797 if (buf[0] == '|' || buf[1] == '.')
7798 continue;
7799 for (cp = buf; *cp; cp++)
7800 if (*cp == '\t')
7801 *cp = ' ';
7802 if (is_label (buf))
7803 continue;
7804 memset (&the_ins, '\0', sizeof (the_ins));
7805 m68k_ip (&the_ins, buf);
7806 if (the_ins.error)
7807 {
7808 printf (_("Error %s in %s\n"), the_ins.error, buf);
7809 }
7810 else
7811 {
7812 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7813 for (n = 0; n < the_ins.numo; n++)
7814 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7815 printf (" ");
7816 print_the_insn (&the_ins.opcode[0], stdout);
7817 (void) putchar ('\n');
7818 }
7819 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7820 {
7821 if (the_ins.operands[n].error)
7822 {
7823 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7824 continue;
7825 }
31302357
AS		 7826 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7827 the_ins.operands[n].reg);
252b5132 7828 if (the_ins.operands[n].b_const)
31302357
AS		 7829 printf ("Constant: '%.*s', ",
7830 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7831 the_ins.operands[n].b_const);
7832 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7833 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7834 if (the_ins.operands[n].b_iadd)
31302357
AS		 7835 printf ("Iadd: '%.*s',",
7836 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7837 the_ins.operands[n].b_iadd);
7838 putchar ('\n');
252b5132
RH		 7839 }
7840 }
7841 m68k_ip_end ();
7842 return 0;
7843}
7844
31302357
AS		 7845int
7846is_label (char *str)
252b5132
RH		 7847{
7848 while (*str == ' ')
7849 str++;
7850 while (*str && *str != ' ')
7851 str++;
7852 if (str[-1] == ':' || str[1] == '=')
7853 return 1;
7854 return 0;
7855}
7856
7857#endif
7858
7859/* Possible states for relaxation:
7860
7861 0 0 branch offset byte (bra, etc)
7862 0 1 word
7863 0 2 long
7864
7865 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7866 1 1 word
7867 1 2 long
7868
7869 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7870 2 1 word-long
7871 2 2 long-word
7872 2 3 long-long
7873
7874 */
7875
7876/* We have no need to default values of symbols. */
7877
252b5132 7878symbolS *
31302357 7879md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7880{
7881 return 0;
7882}
7883
7884/* Round up a section size to the appropriate boundary. */
7885valueT
31302357 7886md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7887{
7888#ifdef OBJ_AOUT
252b5132
RH		 7889 /* For a.out, force the section size to be aligned. If we don't do
7890 this, BFD will align it for us, but it will not write out the
7891 final bytes of the section. This may be a bug in BFD, but it is
7892 easier to fix it here since that is how the other a.out targets
7893 work. */
7894 int align;
7895
7896 align = bfd_get_section_alignment (stdoutput, segment);
7897 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7898#endif
7899
7900 return size;
7901}
7902
7903/* Exactly what point is a PC-relative offset relative TO?
7904 On the 68k, it is relative to the address of the first extension
7905 word. The difference between the addresses of the offset and the
92774660 7906 first extension word is stored in fx_pcrel_adjust. */
252b5132 7907long
31302357 7908md_pcrel_from (fixS *fixP)
252b5132
RH		 7909{
7910 int adjust;
7911
552c607f 7912 adjust = fixP->fx_pcrel_adjust;
252b5132
RH		 7913 if (adjust == 64)
7914 adjust = -1;
7915 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7916}
7917
0d96863f 7918#ifdef OBJ_ELF
8a104df9 7919void
31302357 7920m68k_elf_final_processing (void)
0d96863f 7921{
266abb8f
NS		 7922 unsigned flags = 0;
7923
238d258f 7924 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7925 flags |= EF_M68K_CFV4E;
7926 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7927 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7928 flags |= EF_M68K_CPU32;
7929 else if (cpu_of_arch (current_architecture) & fido_a)
7930 flags |= EF_M68K_FIDO;
8a104df9
KH		 7931 else if ((cpu_of_arch (current_architecture) & m68000up)
7932 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7933 flags |= EF_M68K_M68000;
7934
7935 if (current_architecture & mcfisa_a)
7936 {
0b2e31dc
NS		 7937 static const unsigned isa_features[][2] =
7938 {
9a2e615a 7939 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7940 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7941 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7942 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7943 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7944 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
8d100c32 7945 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
0b2e31dc
NS		 7946 {0,0},
7947 };
7948 static const unsigned mac_features[][2] =
7949 {
c694fd50
KH		 7950 {EF_M68K_CF_MAC, mcfmac},
7951 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7952 {0,0},
7953 };
7954 unsigned ix;
7955 unsigned pattern;
266abb8f 7956
0b2e31dc 7957 pattern = (current_architecture
9a2e615a 7958 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7959 for (ix = 0; isa_features[ix][1]; ix++)
7960 {
7961 if (pattern == isa_features[ix][1])
7962 {
7963 flags |= isa_features[ix][0];
7964 break;
7965 }
7966 }
7967 if (!isa_features[ix][1])
7968 {
7969 cf_bad:
7970 as_warn (_("Not a defined coldfire architecture"));
7971 }
7972 else
7973 {
7974 if (current_architecture & cfloat)
c694fd50 7975 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7976
0b2e31dc
NS		 7977 pattern = current_architecture & (mcfmac|mcfemac);
7978 if (pattern)
7979 {
7980 for (ix = 0; mac_features[ix][1]; ix++)
7981 {
7982 if (pattern == mac_features[ix][1])
7983 {
7984 flags |= mac_features[ix][0];
7985 break;
7986 }
7987 }
7988 if (!mac_features[ix][1])
7989 goto cf_bad;
7990 }
7991 }
266abb8f
NS		 7992 }
7993 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f 7994}
cf869cce
NC		 7995
7996/* Parse @TLSLDO and return the desired relocation. */
7997static bfd_reloc_code_real_type
7998m68k_elf_suffix (char **str_p, expressionS *exp_p)
7999{
8000 char ident[20];
8001 char *str = *str_p;
8002 char *str2;
8003 int ch;
8004 int len;
8005
8006 if (*str++ != '@')
8007 return BFD_RELOC_UNUSED;
8008
8009 for (ch = *str, str2 = ident;
8010 (str2 < ident + sizeof (ident) - 1
8011 && (ISALNUM (ch) || ch == '@'));
8012 ch = *++str)
8013 {
8014 *str2++ = ch;
8015 }
8016
8017 *str2 = '\0';
8018 len = str2 - ident;
8019
8020 if (strncmp (ident, "TLSLDO", 6) == 0
8021 && len == 6)
8022 {
8023 /* Now check for identifier@suffix+constant. */
8024 if (*str == '-' || *str == '+')
8025 {
8026 char *orig_line = input_line_pointer;
8027 expressionS new_exp;
8028
8029 input_line_pointer = str;
8030 expression (&new_exp);
8031 if (new_exp.X_op == O_constant)
8032 {
8033 exp_p->X_add_number += new_exp.X_add_number;
8034 str = input_line_pointer;
8035 }
8036
8037 if (&input_line_pointer != str_p)
8038 input_line_pointer = orig_line;
8039 }
8040 *str_p = str;
8041
8042 return BFD_RELOC_68K_TLS_LDO32;
8043 }
8044
8045 return BFD_RELOC_UNUSED;
8046}
8047
8048/* Handles .long <tls_symbol>+0x8000 debug info.
8049 Clobbers input_line_pointer, checks end-of-line.
8050 Adapted from tc-ppc.c:ppc_elf_cons. */
8051static void
8052m68k_elf_cons (int nbytes /* 4=.long */)
8053{
8054 if (is_it_end_of_statement ())
8055 {
8056 demand_empty_rest_of_line ();
8057 return;
8058 }
8059
8060 do
8061 {
8062 expressionS exp;
8063 bfd_reloc_code_real_type reloc;
8064
8065 expression (&exp);
8066 if (exp.X_op == O_symbol
8067 && *input_line_pointer == '@'
8068 && (reloc = m68k_elf_suffix (&input_line_pointer,
8069 &exp)) != BFD_RELOC_UNUSED)
8070 {
8071 reloc_howto_type *reloc_howto;
8072 int size;
8073
8074 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
8075 size = bfd_get_reloc_size (reloc_howto);
8076
8077 if (size > nbytes)
8078 {
8079 as_bad (_("%s relocations do not fit in %d bytes\n"),
8080 reloc_howto->name, nbytes);
8081 }
8082 else
8083 {
8084 char *p;
8085 int offset;
8086
8087 p = frag_more (nbytes);
8088 offset = 0;
8089 if (target_big_endian)
8090 offset = nbytes - size;
8091 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8092 &exp, 0, reloc);
8093 }
8094 }
8095 else
8096 emit_expr (&exp, (unsigned int) nbytes);
8097 }
8098 while (*input_line_pointer++ == ',');
8099
8100 /* Put terminator back into stream. */
8101 input_line_pointer--;
8102 demand_empty_rest_of_line ();
8103}
0d96863f 8104#endif
c04898f8
AS		 8105
8106int
1df69f4f 8107tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 8108{
8109 unsigned int regnum;
8110 static const char *const regnames[] =
8111 {
8112 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8113 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8114 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8115 "pc"
8116 };
8117
8118 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8119 if (strcmp (regname, regnames[regnum]) == 0)
8120 return regnum;
8121
8122 return -1;
8123}
8124
8125void
8126tc_m68k_frame_initial_instructions (void)
8127{
8128 static int sp_regno = -1;
8129
8130 if (sp_regno < 0)
8131 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8132
8133 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8134 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8135}
GDB Binutils - Deliverables
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