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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4
NC		 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
252b5132
RH		 4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
252b5132
RH		 36/* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40#if defined (TE_SVR4) || defined (TE_DELTA)
41const char *m68k_comment_chars = "|#";
42#else
43const char *m68k_comment_chars = "|";
44#endif
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
92774660
KH		 51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
252b5132
RH		 53const char line_comment_chars[] = "#*";
54
63a0b638 55const char line_separator_chars[] = ";";
252b5132
RH		 56
57/* Chars that can be used to separate mant from exp in floating point nums */
58CONST char EXP_CHARS[] = "eE";
59
60/* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
63CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
64
65/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
69const int md_reloc_size = 8; /* Size of relocation record */
70
71/* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
92774660 73 references. Not implemented. For ELF there are other means
252b5132
RH		 74 to denote pic relocations. */
75int flag_want_pic;
76
77static int flag_short_refs; /* -l option */
78static int flag_long_jumps; /* -S option */
28e7409f 79static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 80
81#ifdef REGISTER_PREFIX_OPTIONAL
82int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83#else
84int flag_reg_prefix_optional;
85#endif
86
87/* Whether --register-prefix-optional was used on the command line. */
88static int reg_prefix_optional_seen;
89
90/* The floating point coprocessor to use by default. */
91static enum m68k_register m68k_float_copnum = COP1;
92
93/* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95static int m68k_abspcadd;
96
97/* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99static int m68k_quick = 1;
100
101/* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104static int m68k_rel32 = 1;
105
106/* This is non-zero if m68k_rel32 was set from the command line. */
107static int m68k_rel32_from_cmdline;
108
109/* The default width to use for an index register when using a base
110 displacement. */
111static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113/* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
116
117struct label_line
118{
119 struct label_line *next;
120 symbolS *label;
121 char *file;
122 unsigned int line;
123 int text;
124};
125
126/* The list of labels. */
127
128static struct label_line *labels;
129
130/* The current label. */
131
132static struct label_line *current_label;
133
134/* Its an arbitrary name: This means I don't approve of it */
135/* See flames below */
136static struct obstack robyn;
137
252b5132
RH		 138struct m68k_incant
139 {
140 const char *m_operands;
141 unsigned long m_opcode;
142 short m_opnum;
143 short m_codenum;
144 int m_arch;
145 struct m68k_incant *m_next;
146 };
147
148#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149#define gettwo(x) (((x)->m_opcode)&0xffff)
150
151static const enum m68k_register m68000_control_regs[] = { 0 };
152static const enum m68k_register m68010_control_regs[] = {
153 SFC, DFC, USP, VBR,
154 0
155};
156static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 0
159};
160static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 0
164};
165static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
168 0
169};
6da466c7 170static const enum m68k_register mcf_control_regs[] = {
92774660 171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 172 RAMBAR0, RAMBAR1, MBAR,
173 0
174};
175#define cpu32_control_regs m68010_control_regs
176
177static const enum m68k_register *control_regs;
178
179/* internal form of a 68020 instruction */
180struct m68k_it
181{
182 const char *error;
183 const char *args; /* list of opcode info */
184 int numargs;
185
186 int numo; /* Number of shorts in opcode */
187 short opcode[11];
188
189 struct m68k_op operands[6];
190
191 int nexp; /* number of exprs in use */
192 struct m68k_exp exprs[4];
193
194 int nfrag; /* Number of frags we have to produce */
195 struct
196 {
197 int fragoff; /* Where in the current opcode the frag ends */
198 symbolS *fadd;
199 offsetT foff;
200 int fragty;
201 }
202 fragb[4];
203
204 int nrel; /* Num of reloc strucs in use */
205 struct
206 {
207 int n;
208 expressionS exp;
209 char wid;
210 char pcrel;
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
217 example). */
218 int pcrel_fix;
219#ifdef OBJ_ELF
220 /* Whether this expression needs special pic relocation, and if
221 so, which. */
222 enum pic_relocation pic_reloc;
223#endif
224 }
225 reloc[5]; /* Five is enough??? */
226};
227
6da466c7 228#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 229#define float_of_arch(x) ((x) & mfloat)
230#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 231#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 232
233/* Macros for determining if cpu supports a specific addressing mode */
dc84e067 234#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
252b5132
RH		 235
236static struct m68k_it the_ins; /* the instruction being assembled */
237
238#define op(ex) ((ex)->exp.X_op)
239#define adds(ex) ((ex)->exp.X_add_symbol)
240#define subs(ex) ((ex)->exp.X_op_symbol)
241#define offs(ex) ((ex)->exp.X_add_number)
242
243/* Macros for adding things to the m68k_it struct */
244
245#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246
247/* Static functions. */
248
249static void insop PARAMS ((int, const struct m68k_incant *));
250static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
251static void add_frag PARAMS ((symbolS *, offsetT, int));
252
253/* Like addword, but goes BEFORE general operands */
254static void
255insop (w, opcode)
256 int w;
257 const struct m68k_incant *opcode;
258{
259 int z;
07726851 260 for (z = the_ins.numo; z > opcode->m_codenum; --z)
252b5132 261 the_ins.opcode[z]=the_ins.opcode[z-1];
07726851 262 for (z = 0;z < the_ins.nrel; z++)
252b5132
RH		 263 the_ins.reloc[z].n+=2;
264 for (z = 0; z < the_ins.nfrag; z++)
265 the_ins.fragb[z].fragoff++;
266 the_ins.opcode[opcode->m_codenum]=w;
267 the_ins.numo++;
268}
269
270/* The numo+1 kludge is so we can hit the low order byte of the prev word.
271 Blecch. */
272static void
273add_fix (width, exp, pc_rel, pc_fix)
274 int width;
275 struct m68k_exp *exp;
276 int pc_rel;
277 int pc_fix;
278{
279 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
280 ? (the_ins.numo*2-1)
281 : (((width)=='b')
282 ? (the_ins.numo*2+1)
283 : (the_ins.numo*2)));
284 the_ins.reloc[the_ins.nrel].exp = exp->exp;
285 the_ins.reloc[the_ins.nrel].wid = width;
286 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287#ifdef OBJ_ELF
288 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289#endif
290 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
291}
292
293/* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
297
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
301
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303static void
304add_frag (add, off, type)
305 symbolS *add;
306 offsetT off;
307 int type;
308{
309 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
310 the_ins.fragb[the_ins.nfrag].fadd=add;
311 the_ins.fragb[the_ins.nfrag].foff=off;
312 the_ins.fragb[the_ins.nfrag++].fragty=type;
313}
314
315#define isvar(ex) \
316 (op (ex) != O_constant && op (ex) != O_big)
317
318static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
319static int get_num PARAMS ((struct m68k_exp *exp, int ok));
320static void m68k_ip PARAMS ((char *));
321static void insert_reg PARAMS ((const char *, int));
322static void select_control_regs PARAMS ((void));
323static void init_regtable PARAMS ((void));
324static int reverse_16_bits PARAMS ((int in));
325static int reverse_8_bits PARAMS ((int in));
326static void install_gen_operand PARAMS ((int mode, int val));
327static void install_operand PARAMS ((int mode, int val));
328static void s_bss PARAMS ((int));
329static void s_data1 PARAMS ((int));
330static void s_data2 PARAMS ((int));
331static void s_even PARAMS ((int));
332static void s_proc PARAMS ((int));
333static void mri_chip PARAMS ((void));
334static void s_chip PARAMS ((int));
335static void s_fopt PARAMS ((int));
336static void s_opt PARAMS ((int));
337static void s_reg PARAMS ((int));
338static void s_restore PARAMS ((int));
339static void s_save PARAMS ((int));
340static void s_mri_if PARAMS ((int));
341static void s_mri_else PARAMS ((int));
342static void s_mri_endi PARAMS ((int));
343static void s_mri_break PARAMS ((int));
344static void s_mri_next PARAMS ((int));
345static void s_mri_for PARAMS ((int));
346static void s_mri_endf PARAMS ((int));
347static void s_mri_repeat PARAMS ((int));
348static void s_mri_until PARAMS ((int));
349static void s_mri_while PARAMS ((int));
350static void s_mri_endw PARAMS ((int));
252b5132
RH		 351static void md_convert_frag_1 PARAMS ((fragS *));
352
353static int current_architecture;
354
dc84e067
NC		 355struct m68k_cpu
356 {
357 unsigned long arch;
358 const char *name;
359 int alias;
360 };
252b5132 361
dc84e067
NC		 362static const struct m68k_cpu archs[] =
363 {
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
378 cpus. */
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
407 };
252b5132
RH		 408
409static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410
151337e8
NC		 411/* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
252b5132 413
151337e8
NC		 414/* Macros used in the relaxation code. */
415#define TAB(x,y) (((x) << 2) + (y))
416#define TABTYPE(x) ((x) >> 2)
417
418/* Relaxation states. */
419#define BYTE 0
420#define SHORT 1
421#define LONG 2
422#define SZ_UNDEF 3
423
424/* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
433
ac62c346
AM		 434#define BRANCHBWL 0 /* branch byte, word, or long */
435#define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
436#define BRABSJCOND 2 /* absolute jump for LONG, conditional */
437#define BRANCHBW 3 /* branch byte or word */
151337e8
NC		 438
439/* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
446
ac62c346
AM		 447#define FBRANCH 4 /* coprocessor branch */
448#define DBCCLBR 5 /* DBcc relaxable with a long branch */
449#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
151337e8
NC		 450
451/* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
461
ac62c346
AM		 462#define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
463#define PCINDEX 8 /* PC+displacement+index */
464#define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 465
466/* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
468
469/* The fields are:
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
474 */
475relax_typeS md_relax_table[] =
476{
ac62c346
AM		 477 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
478 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
479 { 0, 0, 4, 0 },
480 { 1, 1, 0, 0 },
481
482 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
483 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
484 { 0, 0, 4, 0 },
485 { 1, 1, 0, 0 },
486
487 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
488 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
489 { 0, 0, 6, 0 },
490 { 1, 1, 0, 0 },
491
492 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
493 { 0, 0, 2, 0 },
494 { 1, 1, 0, 0 },
495 { 1, 1, 0, 0 },
496
497 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
498 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
499 { 0, 0, 4, 0 },
500 { 1, 1, 0, 0 },
501
502 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
503 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
504 { 0, 0, 10, 0 },
505 { 1, 1, 0, 0 },
506
507 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
508 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
509 { 0, 0, 10, 0 },
510 { 1, 1, 0, 0 },
511
512 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
513 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
514 { 0, 0, 6, 0 },
515 { 1, 1, 0, 0 },
516
517 { 125, -130, 0, TAB (PCINDEX, SHORT) },
518 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
519 { 0, 0, 4, 0 },
520 { 1, 1, 0, 0 },
521
522 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
523 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
524 { 0, 0, 4, 0 },
525 { 1, 1, 0, 0 },
252b5132
RH		 526};
527
528/* These are the machine dependent pseudo-ops. These are included so
529 the assembler can work on the output from the SUN C compiler, which
530 generates these.
531 */
532
533/* This table describes all the machine specific pseudo-ops the assembler
534 has to support. The fields are:
535 pseudo-op name without dot
536 function to call to execute this pseudo-op
537 Integer arg to pass to the function
538 */
539const pseudo_typeS md_pseudo_table[] =
540{
541 {"data1", s_data1, 0},
542 {"data2", s_data2, 0},
543 {"bss", s_bss, 0},
544 {"even", s_even, 0},
545 {"skip", s_space, 0},
546 {"proc", s_proc, 0},
547#if defined (TE_SUN3) || defined (OBJ_ELF)
548 {"align", s_align_bytes, 0},
549#endif
550#ifdef OBJ_ELF
551 {"swbeg", s_ignore, 0},
552#endif
553 {"extend", float_cons, 'x'},
554 {"ldouble", float_cons, 'x'},
555
f27a3839
AS		 556#ifdef OBJ_ELF
557 /* Dwarf2 support for Gcc. */
558 {"file", dwarf2_directive_file, 0},
559 {"loc", dwarf2_directive_loc, 0},
560#endif
561
252b5132
RH		 562 /* The following pseudo-ops are supported for MRI compatibility. */
563 {"chip", s_chip, 0},
564 {"comline", s_space, 1},
565 {"fopt", s_fopt, 0},
566 {"mask2", s_ignore, 0},
567 {"opt", s_opt, 0},
568 {"reg", s_reg, 0},
569 {"restore", s_restore, 0},
570 {"save", s_save, 0},
571
572 {"if", s_mri_if, 0},
573 {"if.b", s_mri_if, 'b'},
574 {"if.w", s_mri_if, 'w'},
575 {"if.l", s_mri_if, 'l'},
576 {"else", s_mri_else, 0},
577 {"else.s", s_mri_else, 's'},
578 {"else.l", s_mri_else, 'l'},
579 {"endi", s_mri_endi, 0},
580 {"break", s_mri_break, 0},
581 {"break.s", s_mri_break, 's'},
582 {"break.l", s_mri_break, 'l'},
583 {"next", s_mri_next, 0},
584 {"next.s", s_mri_next, 's'},
585 {"next.l", s_mri_next, 'l'},
586 {"for", s_mri_for, 0},
587 {"for.b", s_mri_for, 'b'},
588 {"for.w", s_mri_for, 'w'},
589 {"for.l", s_mri_for, 'l'},
590 {"endf", s_mri_endf, 0},
591 {"repeat", s_mri_repeat, 0},
592 {"until", s_mri_until, 0},
593 {"until.b", s_mri_until, 'b'},
594 {"until.w", s_mri_until, 'w'},
595 {"until.l", s_mri_until, 'l'},
596 {"while", s_mri_while, 0},
597 {"while.b", s_mri_while, 'b'},
598 {"while.w", s_mri_while, 'w'},
599 {"while.l", s_mri_while, 'l'},
600 {"endw", s_mri_endw, 0},
601
602 {0, 0, 0}
603};
604
252b5132
RH		 605/* The mote pseudo ops are put into the opcode table, since they
606 don't start with a . they look like opcodes to gas.
607 */
608
609#ifdef M68KCOFF
610extern void obj_coff_section PARAMS ((int));
611#endif
612
613CONST pseudo_typeS mote_pseudo_table[] =
614{
615
616 {"dcl", cons, 4},
617 {"dc", cons, 2},
618 {"dcw", cons, 2},
619 {"dcb", cons, 1},
620
621 {"dsl", s_space, 4},
622 {"ds", s_space, 2},
623 {"dsw", s_space, 2},
624 {"dsb", s_space, 1},
625
626 {"xdef", s_globl, 0},
627#ifdef OBJ_ELF
628 {"align", s_align_bytes, 0},
629#else
630 {"align", s_align_ptwo, 0},
631#endif
632#ifdef M68KCOFF
633 {"sect", obj_coff_section, 0},
634 {"section", obj_coff_section, 0},
635#endif
636 {0, 0, 0}
637};
638
639#define issbyte(x) ((x)>=-128 && (x)<=127)
640#define isubyte(x) ((x)>=0 && (x)<=255)
641#define issword(x) ((x)>=-32768 && (x)<=32767)
642#define isuword(x) ((x)>=0 && (x)<=65535)
643
644#define isbyte(x) ((x)>= -255 && (x)<=255)
645#define isword(x) ((x)>=-65536 && (x)<=65535)
646#define islong(x) (1)
647
648extern char *input_line_pointer;
649
252b5132
RH		 650static char notend_table[256];
651static char alt_notend_table[256];
652#define notend(s) \
653 (! (notend_table[(unsigned char) *s] \
654 || (*s == ':' \
655 && alt_notend_table[(unsigned char) s[1]])))
656
657#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
658
659#ifdef NO_PCREL_RELOCS
660
661int
662make_pcrel_absolute(fixP, add_number)
663 fixS *fixP;
664 long *add_number;
665{
666 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
667
668 /* rewrite the PC relative instructions to absolute address ones.
669 * these are rumoured to be faster, and the apollo linker refuses
670 * to deal with the PC relative relocations.
671 */
672 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
673 {
674 opcode[0] = 0x4e;
675 opcode[1] = 0xf9;
676 }
677 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
678 {
679 opcode[0] = 0x4e;
680 opcode[1] = 0xb9;
681 }
682 else
683 as_fatal (_("Unknown PC relative instruction"));
684 *add_number -= 4;
685 return 0;
686}
687
688#endif /* NO_PCREL_RELOCS */
689
690short
691tc_coff_fix2rtype (fixP)
692 fixS *fixP;
693{
694 if (fixP->fx_tcbit && fixP->fx_size == 4)
695 return R_RELLONG_NEG;
696#ifdef NO_PCREL_RELOCS
697 know (fixP->fx_pcrel == 0);
698 return (fixP->fx_size == 1 ? R_RELBYTE
699 : fixP->fx_size == 2 ? R_DIR16
700 : R_DIR32);
701#else
702 return (fixP->fx_pcrel ?
703 (fixP->fx_size == 1 ? R_PCRBYTE :
704 fixP->fx_size == 2 ? R_PCRWORD :
705 R_PCRLONG) :
706 (fixP->fx_size == 1 ? R_RELBYTE :
707 fixP->fx_size == 2 ? R_RELWORD :
708 R_RELLONG));
709#endif
710}
711
712#endif
713
714#ifdef OBJ_ELF
715
c801568a
AM		 716/* Return zero if the reference to SYMBOL from within the same segment may
717 be relaxed. */
718
719/* On an ELF system, we can't relax an externally visible symbol,
720 because it may be overridden by a shared library. However, if
721 TARGET_OS is "elf", then we presume that we are assembling for an
722 embedded system, in which case we don't have to worry about shared
723 libraries, and we can relax any external sym. */
724
725#define relaxable_symbol(symbol) \
726 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
727 || S_IS_WEAK (symbol)))
728
252b5132
RH		 729/* Compute the relocation code for a fixup of SIZE bytes, using pc
730 relative relocation if PCREL is non-zero. PIC says whether a special
731 pic relocation was requested. */
732
733static bfd_reloc_code_real_type get_reloc_code
734 PARAMS ((int, int, enum pic_relocation));
735
736static bfd_reloc_code_real_type
737get_reloc_code (size, pcrel, pic)
738 int size;
739 int pcrel;
740 enum pic_relocation pic;
741{
742 switch (pic)
743 {
744 case pic_got_pcrel:
745 switch (size)
746 {
747 case 1:
748 return BFD_RELOC_8_GOT_PCREL;
749 case 2:
750 return BFD_RELOC_16_GOT_PCREL;
751 case 4:
752 return BFD_RELOC_32_GOT_PCREL;
753 }
754 break;
755
756 case pic_got_off:
757 switch (size)
758 {
759 case 1:
760 return BFD_RELOC_8_GOTOFF;
761 case 2:
762 return BFD_RELOC_16_GOTOFF;
763 case 4:
764 return BFD_RELOC_32_GOTOFF;
765 }
766 break;
767
768 case pic_plt_pcrel:
769 switch (size)
770 {
771 case 1:
772 return BFD_RELOC_8_PLT_PCREL;
773 case 2:
774 return BFD_RELOC_16_PLT_PCREL;
775 case 4:
776 return BFD_RELOC_32_PLT_PCREL;
777 }
778 break;
779
780 case pic_plt_off:
781 switch (size)
782 {
783 case 1:
784 return BFD_RELOC_8_PLTOFF;
785 case 2:
786 return BFD_RELOC_16_PLTOFF;
787 case 4:
788 return BFD_RELOC_32_PLTOFF;
789 }
790 break;
791
792 case pic_none:
793 if (pcrel)
794 {
795 switch (size)
796 {
797 case 1:
798 return BFD_RELOC_8_PCREL;
799 case 2:
800 return BFD_RELOC_16_PCREL;
801 case 4:
802 return BFD_RELOC_32_PCREL;
803 }
804 }
805 else
806 {
807 switch (size)
808 {
809 case 1:
810 return BFD_RELOC_8;
811 case 2:
812 return BFD_RELOC_16;
813 case 4:
814 return BFD_RELOC_32;
815 }
816 }
817 }
818
819 if (pcrel)
820 {
821 if (pic == pic_none)
822 as_bad (_("Can not do %d byte pc-relative relocation"), size);
823 else
824 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
825 }
826 else
827 {
828 if (pic == pic_none)
829 as_bad (_("Can not do %d byte relocation"), size);
830 else
831 as_bad (_("Can not do %d byte pic relocation"), size);
832 }
833
834 return BFD_RELOC_NONE;
835}
836
837/* Here we decide which fixups can be adjusted to make them relative
838 to the beginning of the section instead of the symbol. Basically
839 we need to make sure that the dynamic relocations are done
840 correctly, so in some cases we force the original symbol to be
841 used. */
842int
843tc_m68k_fix_adjustable (fixP)
844 fixS *fixP;
845{
92774660 846 /* Prevent all adjustments to global symbols. */
c801568a 847 if (! relaxable_symbol (fixP->fx_addsy))
252b5132
RH		 848 return 0;
849
850 /* adjust_reloc_syms doesn't know about the GOT */
851 switch (fixP->fx_r_type)
852 {
853 case BFD_RELOC_8_GOT_PCREL:
854 case BFD_RELOC_16_GOT_PCREL:
855 case BFD_RELOC_32_GOT_PCREL:
856 case BFD_RELOC_8_GOTOFF:
857 case BFD_RELOC_16_GOTOFF:
858 case BFD_RELOC_32_GOTOFF:
859 case BFD_RELOC_8_PLT_PCREL:
860 case BFD_RELOC_16_PLT_PCREL:
861 case BFD_RELOC_32_PLT_PCREL:
862 case BFD_RELOC_8_PLTOFF:
863 case BFD_RELOC_16_PLTOFF:
864 case BFD_RELOC_32_PLTOFF:
865 return 0;
866
867 case BFD_RELOC_VTABLE_INHERIT:
868 case BFD_RELOC_VTABLE_ENTRY:
869 return 0;
870
871 default:
872 return 1;
873 }
874}
875
876#else /* !OBJ_ELF */
877
878#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
879
c801568a
AM		 880#define relaxable_symbol(symbol) 1
881
252b5132
RH		 882#endif /* OBJ_ELF */
883
884#ifdef BFD_ASSEMBLER
885
886arelent *
887tc_gen_reloc (section, fixp)
888 asection *section;
889 fixS *fixp;
890{
891 arelent *reloc;
892 bfd_reloc_code_real_type code;
893
8ec6253e
NC		 894 /* If the tcbit is set, then this was a fixup of a negative value
895 that was never resolved. We do not have a reloc to handle this,
896 so just return. We assume that other code will have detected this
897 situation and produced a helpful error message, so we just tell the
898 user that the reloc cannot be produced. */
252b5132 899 if (fixp->fx_tcbit)
8ec6253e
NC		 900 {
901 if (fixp->fx_addsy)
b091f402
AM		 902 as_bad_where (fixp->fx_file, fixp->fx_line,
903 _("Unable to produce reloc against symbol '%s'"),
904 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 905 return NULL;
906 }
252b5132
RH		 907
908 if (fixp->fx_r_type != BFD_RELOC_NONE)
909 {
910 code = fixp->fx_r_type;
911
912 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
913 that fixup_segment converted a non-PC relative reloc into a
914 PC relative reloc. In such a case, we need to convert the
915 reloc code. */
916 if (fixp->fx_pcrel)
917 {
918 switch (code)
919 {
920 case BFD_RELOC_8:
921 code = BFD_RELOC_8_PCREL;
922 break;
923 case BFD_RELOC_16:
924 code = BFD_RELOC_16_PCREL;
925 break;
926 case BFD_RELOC_32:
927 code = BFD_RELOC_32_PCREL;
928 break;
929 case BFD_RELOC_8_PCREL:
930 case BFD_RELOC_16_PCREL:
931 case BFD_RELOC_32_PCREL:
932 case BFD_RELOC_8_GOT_PCREL:
933 case BFD_RELOC_16_GOT_PCREL:
934 case BFD_RELOC_32_GOT_PCREL:
935 case BFD_RELOC_8_GOTOFF:
936 case BFD_RELOC_16_GOTOFF:
937 case BFD_RELOC_32_GOTOFF:
938 case BFD_RELOC_8_PLT_PCREL:
939 case BFD_RELOC_16_PLT_PCREL:
940 case BFD_RELOC_32_PLT_PCREL:
941 case BFD_RELOC_8_PLTOFF:
942 case BFD_RELOC_16_PLTOFF:
943 case BFD_RELOC_32_PLTOFF:
944 break;
945 default:
946 as_bad_where (fixp->fx_file, fixp->fx_line,
947 _("Cannot make %s relocation PC relative"),
948 bfd_get_reloc_code_name (code));
949 }
950 }
951 }
952 else
953 {
954#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
955 switch (F (fixp->fx_size, fixp->fx_pcrel))
956 {
957#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
958 MAP (1, 0, BFD_RELOC_8);
959 MAP (2, 0, BFD_RELOC_16);
960 MAP (4, 0, BFD_RELOC_32);
961 MAP (1, 1, BFD_RELOC_8_PCREL);
962 MAP (2, 1, BFD_RELOC_16_PCREL);
963 MAP (4, 1, BFD_RELOC_32_PCREL);
964 default:
965 abort ();
966 }
967 }
968#undef F
969#undef MAP
970
971 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 972 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
973 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 974 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
975#ifndef OBJ_ELF
976 if (fixp->fx_pcrel)
977 reloc->addend = fixp->fx_addnumber;
978 else
979 reloc->addend = 0;
980#else
981 if (!fixp->fx_pcrel)
982 reloc->addend = fixp->fx_addnumber;
983 else
984 reloc->addend = (section->vma
8390138c
AS		 985 /* Explicit sign extension in case char is
986 unsigned. */
987 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 988 + fixp->fx_addnumber
989 + md_pcrel_from (fixp));
990#endif
991
992 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
993 assert (reloc->howto != 0);
994
995 return reloc;
996}
997
998#endif /* BFD_ASSEMBLER */
999
252b5132
RH		 1000/* Handle of the OPCODE hash table. NULL means any use before
1001 m68k_ip_begin() will crash. */
1002static struct hash_control *op_hash;
1003\f
1004/* Assemble an m68k instruction. */
1005
1006static void
1007m68k_ip (instring)
1008 char *instring;
1009{
1010 register char *p;
1011 register struct m68k_op *opP;
1012 register const struct m68k_incant *opcode;
1013 register const char *s;
1014 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1015 char *pdot, *pdotmove;
1016 enum m68k_size siz1, siz2;
1017 char c;
1018 int losing;
1019 int opsfound;
1020 LITTLENUM_TYPE words[6];
1021 LITTLENUM_TYPE *wordp;
1022 unsigned long ok_arch = 0;
1023
1024 if (*instring == ' ')
1025 instring++; /* skip leading whitespace */
1026
1027 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1028 or exactly 1 space. */
252b5132
RH		 1029 pdot = 0;
1030 for (p = instring; *p != '\0'; p++)
1031 {
1032 if (*p == ' ')
1033 break;
1034 if (*p == '.')
1035 pdot = p;
1036 }
1037
1038 if (p == instring)
1039 {
1040 the_ins.error = _("No operator");
1041 return;
1042 }
1043
1044 /* p now points to the end of the opcode name, probably whitespace.
1045 Make sure the name is null terminated by clobbering the
1046 whitespace, look it up in the hash table, then fix it back.
1047 Remove a dot, first, since the opcode tables have none. */
1048 if (pdot != NULL)
1049 {
1050 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1051 *pdotmove = pdotmove[1];
1052 p--;
1053 }
1054
1055 c = *p;
1056 *p = '\0';
1057 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1058 *p = c;
1059
1060 if (pdot != NULL)
1061 {
1062 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1063 *pdotmove = pdotmove[-1];
1064 *pdot = '.';
1065 ++p;
1066 }
1067
1068 if (opcode == NULL)
1069 {
1070 the_ins.error = _("Unknown operator");
1071 return;
1072 }
1073
1074 /* found a legitimate opcode, start matching operands */
1075 while (*p == ' ')
1076 ++p;
1077
1078 if (opcode->m_operands == 0)
1079 {
1080 char *old = input_line_pointer;
1081 *old = '\n';
1082 input_line_pointer = p;
1083 /* Ahh - it's a motorola style psuedo op */
1084 mote_pseudo_table[opcode->m_opnum].poc_handler
1085 (mote_pseudo_table[opcode->m_opnum].poc_val);
1086 input_line_pointer = old;
1087 *old = 0;
1088
1089 return;
1090 }
1091
1092 if (flag_mri && opcode->m_opnum == 0)
1093 {
1094 /* In MRI mode, random garbage is allowed after an instruction
1095 which accepts no operands. */
1096 the_ins.args = opcode->m_operands;
1097 the_ins.numargs = opcode->m_opnum;
1098 the_ins.numo = opcode->m_codenum;
1099 the_ins.opcode[0] = getone (opcode);
1100 the_ins.opcode[1] = gettwo (opcode);
1101 return;
1102 }
1103
1104 for (opP = &the_ins.operands[0]; *p; opP++)
1105 {
1106 p = crack_operand (p, opP);
1107
1108 if (opP->error)
1109 {
1110 the_ins.error = opP->error;
1111 return;
1112 }
1113 }
1114
1115 opsfound = opP - &the_ins.operands[0];
1116
1117 /* This ugly hack is to support the floating pt opcodes in their
1118 standard form. Essentially, we fake a first enty of type COP#1 */
1119 if (opcode->m_operands[0] == 'I')
1120 {
1121 int n;
1122
1123 for (n = opsfound; n > 0; --n)
1124 the_ins.operands[n] = the_ins.operands[n - 1];
1125
1126 memset ((char *) (&the_ins.operands[0]), '\0',
1127 sizeof (the_ins.operands[0]));
1128 the_ins.operands[0].mode = CONTROL;
1129 the_ins.operands[0].reg = m68k_float_copnum;
1130 opsfound++;
1131 }
1132
1133 /* We've got the operands. Find an opcode that'll accept them */
1134 for (losing = 0;;)
1135 {
1136 /* If we didn't get the right number of ops, or we have no
92774660 1137 common model with this pattern then reject this pattern. */
252b5132
RH		 1138
1139 ok_arch |= opcode->m_arch;
1140 if (opsfound != opcode->m_opnum
1141 || ((opcode->m_arch & current_architecture) == 0))
1142 ++losing;
1143 else
1144 {
1145 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1146 *s && !losing;
1147 s += 2, opP++)
1148 {
1149 /* Warning: this switch is huge! */
1150 /* I've tried to organize the cases into this order:
1151 non-alpha first, then alpha by letter. Lower-case
1152 goes directly before uppercase counterpart. */
1153 /* Code with multiple case ...: gets sorted by the lowest
1154 case ... it belongs to. I hope this makes sense. */
1155 switch (*s)
1156 {
1157 case '!':
1158 switch (opP->mode)
1159 {
1160 case IMMED:
1161 case DREG:
1162 case AREG:
1163 case FPREG:
1164 case CONTROL:
1165 case AINC:
1166 case ADEC:
1167 case REGLST:
1168 losing++;
1169 break;
1170 default:
1171 break;
1172 }
1173 break;
1174
1175 case '<':
1176 switch (opP->mode)
1177 {
1178 case DREG:
1179 case AREG:
1180 case FPREG:
1181 case CONTROL:
1182 case IMMED:
1183 case ADEC:
1184 case REGLST:
1185 losing++;
1186 break;
1187 default:
1188 break;
1189 }
1190 break;
1191
1192 case '>':
1193 switch (opP->mode)
1194 {
1195 case DREG:
1196 case AREG:
1197 case FPREG:
1198 case CONTROL:
1199 case IMMED:
1200 case AINC:
1201 case REGLST:
1202 losing++;
1203 break;
1204 case ABSL:
1205 break;
1206 default:
1207 if (opP->reg == PC
1208 || opP->reg == ZPC)
1209 losing++;
1210 break;
1211 }
1212 break;
1213
1214 case 'm':
1215 switch (opP->mode)
1216 {
1217 case DREG:
1218 case AREG:
1219 case AINDR:
1220 case AINC:
1221 case ADEC:
1222 break;
1223 default:
1224 losing++;
1225 }
1226 break;
1227
1228 case 'n':
1229 switch (opP->mode)
1230 {
1231 case DISP:
1232 break;
1233 default:
1234 losing++;
1235 }
1236 break;
1237
1238 case 'o':
1239 switch (opP->mode)
1240 {
1241 case BASE:
1242 case ABSL:
1243 case IMMED:
1244 break;
1245 default:
1246 losing++;
1247 }
1248 break;
1249
1250 case 'p':
1251 switch (opP->mode)
1252 {
1253 case DREG:
1254 case AREG:
1255 case AINDR:
1256 case AINC:
1257 case ADEC:
1258 break;
1259 case DISP:
1260 if (opP->reg == PC || opP->reg == ZPC)
1261 losing++;
1262 break;
1263 default:
1264 losing++;
1265 }
1266 break;
1267
1268 case 'q':
1269 switch (opP->mode)
1270 {
1271 case DREG:
1272 case AINDR:
1273 case AINC:
1274 case ADEC:
1275 break;
1276 case DISP:
1277 if (opP->reg == PC || opP->reg == ZPC)
1278 losing++;
1279 break;
1280 default:
1281 losing++;
1282 break;
1283 }
1284 break;
1285
1286 case 'v':
1287 switch (opP->mode)
1288 {
1289 case DREG:
1290 case AINDR:
1291 case AINC:
1292 case ADEC:
1293 case ABSL:
1294 break;
1295 case DISP:
1296 if (opP->reg == PC || opP->reg == ZPC)
1297 losing++;
1298 break;
1299 default:
1300 losing++;
1301 break;
1302 }
1303 break;
1304
1305 case '#':
1306 if (opP->mode != IMMED)
1307 losing++;
1308 else if (s[1] == 'b'
1309 && ! isvar (&opP->disp)
1310 && (opP->disp.exp.X_op != O_constant
1311 || ! isbyte (opP->disp.exp.X_add_number)))
1312 losing++;
1313 else if (s[1] == 'B'
1314 && ! isvar (&opP->disp)
1315 && (opP->disp.exp.X_op != O_constant
1316 || ! issbyte (opP->disp.exp.X_add_number)))
1317 losing++;
1318 else if (s[1] == 'w'
1319 && ! isvar (&opP->disp)
1320 && (opP->disp.exp.X_op != O_constant
1321 || ! isword (opP->disp.exp.X_add_number)))
1322 losing++;
1323 else if (s[1] == 'W'
1324 && ! isvar (&opP->disp)
1325 && (opP->disp.exp.X_op != O_constant
1326 || ! issword (opP->disp.exp.X_add_number)))
1327 losing++;
1328 break;
1329
1330 case '^':
1331 case 'T':
1332 if (opP->mode != IMMED)
1333 losing++;
1334 break;
1335
1336 case '$':
1337 if (opP->mode == AREG
1338 || opP->mode == CONTROL
1339 || opP->mode == FPREG
1340 || opP->mode == IMMED
1341 || opP->mode == REGLST
1342 || (opP->mode != ABSL
1343 && (opP->reg == PC
1344 || opP->reg == ZPC)))
1345 losing++;
1346 break;
1347
1348 case '%':
1349 if (opP->mode == CONTROL
1350 || opP->mode == FPREG
1351 || opP->mode == REGLST
1352 || opP->mode == IMMED
1353 || (opP->mode != ABSL
1354 && (opP->reg == PC
1355 || opP->reg == ZPC)))
1356 losing++;
1357 break;
1358
1359 case '&':
1360 switch (opP->mode)
1361 {
1362 case DREG:
1363 case AREG:
1364 case FPREG:
1365 case CONTROL:
1366 case IMMED:
1367 case AINC:
1368 case ADEC:
1369 case REGLST:
1370 losing++;
1371 break;
1372 case ABSL:
1373 break;
1374 default:
1375 if (opP->reg == PC
1376 || opP->reg == ZPC)
1377 losing++;
1378 break;
1379 }
1380 break;
1381
1382 case '*':
1383 if (opP->mode == CONTROL
1384 || opP->mode == FPREG
1385 || opP->mode == REGLST)
1386 losing++;
1387 break;
1388
1389 case '+':
1390 if (opP->mode != AINC)
1391 losing++;
1392 break;
1393
1394 case '-':
1395 if (opP->mode != ADEC)
1396 losing++;
1397 break;
1398
1399 case '/':
1400 switch (opP->mode)
1401 {
1402 case AREG:
1403 case CONTROL:
1404 case FPREG:
1405 case AINC:
1406 case ADEC:
1407 case IMMED:
1408 case REGLST:
1409 losing++;
1410 break;
1411 default:
1412 break;
1413 }
1414 break;
1415
1416 case ';':
1417 switch (opP->mode)
1418 {
1419 case AREG:
1420 case CONTROL:
1421 case FPREG:
1422 case REGLST:
1423 losing++;
1424 break;
1425 default:
1426 break;
1427 }
1428 break;
1429
1430 case '?':
1431 switch (opP->mode)
1432 {
1433 case AREG:
1434 case CONTROL:
1435 case FPREG:
1436 case AINC:
1437 case ADEC:
1438 case IMMED:
1439 case REGLST:
1440 losing++;
1441 break;
1442 case ABSL:
1443 break;
1444 default:
1445 if (opP->reg == PC || opP->reg == ZPC)
1446 losing++;
1447 break;
1448 }
1449 break;
1450
1451 case '@':
1452 switch (opP->mode)
1453 {
1454 case AREG:
1455 case CONTROL:
1456 case FPREG:
1457 case IMMED:
1458 case REGLST:
1459 losing++;
1460 break;
1461 default:
1462 break;
1463 }
1464 break;
1465
1466 case '~': /* For now! (JF FOO is this right?) */
1467 switch (opP->mode)
1468 {
1469 case DREG:
1470 case AREG:
1471 case CONTROL:
1472 case FPREG:
1473 case IMMED:
1474 case REGLST:
1475 losing++;
1476 break;
1477 case ABSL:
1478 break;
1479 default:
1480 if (opP->reg == PC
1481 || opP->reg == ZPC)
1482 losing++;
1483 break;
1484 }
1485 break;
1486
1487 case '3':
1488 if (opP->mode != CONTROL
1489 || (opP->reg != TT0 && opP->reg != TT1))
1490 losing++;
1491 break;
1492
1493 case 'A':
1494 if (opP->mode != AREG)
1495 losing++;
1496 break;
1497
1498 case 'a':
1499 if (opP->mode != AINDR)
1500 ++losing;
1501 break;
1502
1503 case 'B': /* FOO */
1504 if (opP->mode != ABSL
1505 || (flag_long_jumps
1506 && strncmp (instring, "jbsr", 4) == 0))
1507 losing++;
1508 break;
1509
1510 case 'C':
1511 if (opP->mode != CONTROL || opP->reg != CCR)
1512 losing++;
1513 break;
1514
1515 case 'd':
1516 if (opP->mode != DISP
1517 || opP->reg < ADDR0
1518 || opP->reg > ADDR7)
1519 losing++;
1520 break;
1521
1522 case 'D':
1523 if (opP->mode != DREG)
1524 losing++;
1525 break;
1526
6da466c7
ILT		 1527 case 'E':
1528 if (opP->reg != ACC)
1529 losing++;
1530 break;
1531
252b5132
RH		 1532 case 'F':
1533 if (opP->mode != FPREG)
1534 losing++;
1535 break;
1536
6da466c7
ILT		 1537 case 'G':
1538 if (opP->reg != MACSR)
1539 losing++;
1540 break;
1541
1542 case 'H':
1543 if (opP->reg != MASK)
1544 losing++;
1545 break;
1546
252b5132
RH		 1547 case 'I':
1548 if (opP->mode != CONTROL
1549 || opP->reg < COP0
1550 || opP->reg > COP7)
1551 losing++;
1552 break;
1553
1554 case 'J':
1555 if (opP->mode != CONTROL
1556 || opP->reg < USP
1557 || opP->reg > last_movec_reg)
1558 losing++;
1559 else
1560 {
1561 const enum m68k_register *rp;
1562 for (rp = control_regs; *rp; rp++)
1563 if (*rp == opP->reg)
1564 break;
1565 if (*rp == 0)
1566 losing++;
1567 }
1568 break;
1569
1570 case 'k':
1571 if (opP->mode != IMMED)
1572 losing++;
1573 break;
1574
1575 case 'l':
1576 case 'L':
1577 if (opP->mode == DREG
1578 || opP->mode == AREG
1579 || opP->mode == FPREG)
1580 {
1581 if (s[1] == '8')
1582 losing++;
1583 else
1584 {
1585 switch (opP->mode)
1586 {
1587 case DREG:
1588 opP->mask = 1 << (opP->reg - DATA0);
1589 break;
1590 case AREG:
1591 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1592 break;
1593 case FPREG:
1594 opP->mask = 1 << (opP->reg - FP0 + 16);
1595 break;
1596 default:
1597 abort ();
1598 }
1599 opP->mode = REGLST;
1600 }
1601 }
1602 else if (opP->mode == CONTROL)
1603 {
1604 if (s[1] != '8')
1605 losing++;
1606 else
1607 {
1608 switch (opP->reg)
1609 {
1610 case FPI:
1611 opP->mask = 1 << 24;
1612 break;
1613 case FPS:
1614 opP->mask = 1 << 25;
1615 break;
1616 case FPC:
1617 opP->mask = 1 << 26;
1618 break;
1619 default:
1620 losing++;
1621 break;
1622 }
1623 opP->mode = REGLST;
1624 }
1625 }
1626 else if (opP->mode != REGLST)
1627 losing++;
1628 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1629 losing++;
1630 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1631 losing++;
1632 break;
1633
1634 case 'M':
1635 if (opP->mode != IMMED)
1636 losing++;
1637 else if (opP->disp.exp.X_op != O_constant
1638 || ! issbyte (opP->disp.exp.X_add_number))
1639 losing++;
1640 else if (! m68k_quick
1641 && instring[3] != 'q'
1642 && instring[4] != 'q')
1643 losing++;
1644 break;
1645
1646 case 'O':
1647 if (opP->mode != DREG
1648 && opP->mode != IMMED
1649 && opP->mode != ABSL)
1650 losing++;
1651 break;
1652
1653 case 'Q':
1654 if (opP->mode != IMMED)
1655 losing++;
1656 else if (opP->disp.exp.X_op != O_constant
1657 || opP->disp.exp.X_add_number < 1
1658 || opP->disp.exp.X_add_number > 8)
1659 losing++;
1660 else if (! m68k_quick
1661 && (strncmp (instring, "add", 3) == 0
1662 || strncmp (instring, "sub", 3) == 0)
1663 && instring[3] != 'q')
1664 losing++;
1665 break;
1666
1667 case 'R':
1668 if (opP->mode != DREG && opP->mode != AREG)
1669 losing++;
1670 break;
1671
1672 case 'r':
1673 if (opP->mode != AINDR
1674 && (opP->mode != BASE
1675 || (opP->reg != 0
1676 && opP->reg != ZADDR0)
1677 || opP->disp.exp.X_op != O_absent
1678 || ((opP->index.reg < DATA0
1679 || opP->index.reg > DATA7)
1680 && (opP->index.reg < ADDR0
1681 || opP->index.reg > ADDR7))
1682 || opP->index.size != SIZE_UNSPEC
1683 || opP->index.scale != 1))
1684 losing++;
1685 break;
1686
1687 case 's':
1688 if (opP->mode != CONTROL
1689 || ! (opP->reg == FPI
1690 || opP->reg == FPS
1691 || opP->reg == FPC))
1692 losing++;
1693 break;
1694
1695 case 'S':
1696 if (opP->mode != CONTROL || opP->reg != SR)
1697 losing++;
1698 break;
1699
1700 case 't':
1701 if (opP->mode != IMMED)
1702 losing++;
1703 else if (opP->disp.exp.X_op != O_constant
1704 || opP->disp.exp.X_add_number < 0
1705 || opP->disp.exp.X_add_number > 7)
1706 losing++;
1707 break;
1708
1709 case 'U':
1710 if (opP->mode != CONTROL || opP->reg != USP)
1711 losing++;
1712 break;
1713
1714 /* JF these are out of order. We could put them
1715 in order if we were willing to put up with
1716 bunches of #ifdef m68851s in the code.
1717
1718 Don't forget that you need these operands
1719 to use 68030 MMU instructions. */
1720#ifndef NO_68851
1721 /* Memory addressing mode used by pflushr */
1722 case '|':
1723 if (opP->mode == CONTROL
1724 || opP->mode == FPREG
1725 || opP->mode == DREG
1726 || opP->mode == AREG
1727 || opP->mode == REGLST)
1728 losing++;
1729 /* We should accept immediate operands, but they
1730 supposedly have to be quad word, and we don't
1731 handle that. I would like to see what a Motorola
1732 assembler does before doing something here. */
1733 if (opP->mode == IMMED)
1734 losing++;
1735 break;
1736
1737 case 'f':
1738 if (opP->mode != CONTROL
1739 || (opP->reg != SFC && opP->reg != DFC))
1740 losing++;
1741 break;
1742
1743 case '0':
1744 if (opP->mode != CONTROL || opP->reg != TC)
1745 losing++;
1746 break;
1747
1748 case '1':
1749 if (opP->mode != CONTROL || opP->reg != AC)
1750 losing++;
1751 break;
1752
1753 case '2':
1754 if (opP->mode != CONTROL
1755 || (opP->reg != CAL
1756 && opP->reg != VAL
1757 && opP->reg != SCC))
1758 losing++;
1759 break;
1760
1761 case 'V':
1762 if (opP->mode != CONTROL
1763 || opP->reg != VAL)
1764 losing++;
1765 break;
1766
1767 case 'W':
1768 if (opP->mode != CONTROL
1769 || (opP->reg != DRP
1770 && opP->reg != SRP
1771 && opP->reg != CRP))
1772 losing++;
1773 break;
1774
1775 case 'X':
1776 if (opP->mode != CONTROL
1777 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1778 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1779 losing++;
1780 break;
1781
1782 case 'Y':
1783 if (opP->mode != CONTROL || opP->reg != PSR)
1784 losing++;
1785 break;
1786
1787 case 'Z':
1788 if (opP->mode != CONTROL || opP->reg != PCSR)
1789 losing++;
1790 break;
1791#endif
1792 case 'c':
1793 if (opP->mode != CONTROL
1794 || (opP->reg != NC
1795 && opP->reg != IC
1796 && opP->reg != DC
1797 && opP->reg != BC))
1798 {
1799 losing++;
92774660 1800 } /* not a cache specifier. */
252b5132
RH		 1801 break;
1802
1803 case '_':
1804 if (opP->mode != ABSL)
1805 ++losing;
1806 break;
1807
6da466c7
ILT		 1808 case 'u':
1809 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1810 losing++;
1811 /* FIXME: kludge instead of fixing parser:
1812 upper/lower registers are *not* CONTROL
92774660 1813 registers, but ordinary ones. */
6da466c7
ILT		 1814 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1815 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1816 opP->mode = DREG;
1817 else
1818 opP->mode = AREG;
1819 break;
1820
252b5132
RH		 1821 default:
1822 abort ();
1823 } /* switch on type of operand */
1824
1825 if (losing)
1826 break;
1827 } /* for each operand */
1828 } /* if immediately wrong */
1829
1830 if (!losing)
1831 {
1832 break;
92774660 1833 } /* got it. */
252b5132
RH		 1834
1835 opcode = opcode->m_next;
1836
1837 if (!opcode)
1838 {
1839 if (ok_arch
1840 && !(ok_arch & current_architecture))
1841 {
1842 char buf[200], *cp;
1843
1844 strcpy (buf,
1845 _("invalid instruction for this architecture; needs "));
1846 cp = buf + strlen (buf);
1847 switch (ok_arch)
1848 {
1849 case mfloat:
1850 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1851 break;
1852 case mmmu:
1853 strcpy (cp, _("mmu (68030 or 68851)"));
1854 break;
1855 case m68020up:
1856 strcpy (cp, _("68020 or higher"));
1857 break;
1858 case m68000up:
1859 strcpy (cp, _("68000 or higher"));
1860 break;
1861 case m68010up:
1862 strcpy (cp, _("68010 or higher"));
1863 break;
1864 default:
1865 {
1866 int got_one = 0, idx;
8fce3f5e
AM		 1867 for (idx = 0;
1868 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1869 idx++)
1870 {
1871 if ((archs[idx].arch & ok_arch)
1872 && ! archs[idx].alias)
1873 {
1874 if (got_one)
1875 {
1876 strcpy (cp, " or ");
1877 cp += strlen (cp);
1878 }
1879 got_one = 1;
1880 strcpy (cp, archs[idx].name);
1881 cp += strlen (cp);
1882 }
1883 }
1884 }
1885 }
1886 cp = xmalloc (strlen (buf) + 1);
1887 strcpy (cp, buf);
1888 the_ins.error = cp;
1889 }
1890 else
1891 the_ins.error = _("operands mismatch");
1892 return;
1893 } /* Fell off the end */
1894
1895 losing = 0;
1896 }
1897
1898 /* now assemble it */
1899
1900 the_ins.args = opcode->m_operands;
1901 the_ins.numargs = opcode->m_opnum;
1902 the_ins.numo = opcode->m_codenum;
1903 the_ins.opcode[0] = getone (opcode);
1904 the_ins.opcode[1] = gettwo (opcode);
1905
1906 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1907 {
1908 /* This switch is a doozy.
1909 Watch the first step; its a big one! */
1910 switch (s[0])
1911 {
1912
1913 case '*':
1914 case '~':
1915 case '%':
1916 case ';':
1917 case '@':
1918 case '!':
1919 case '&':
1920 case '$':
1921 case '?':
1922 case '/':
1923 case '<':
1924 case '>':
1925 case 'm':
1926 case 'n':
1927 case 'o':
1928 case 'p':
1929 case 'q':
1930 case 'v':
1931#ifndef NO_68851
1932 case '|':
1933#endif
1934 switch (opP->mode)
1935 {
1936 case IMMED:
1937 tmpreg = 0x3c; /* 7.4 */
1938 if (strchr ("bwl", s[1]))
1939 nextword = get_num (&opP->disp, 80);
1940 else
1941 nextword = get_num (&opP->disp, 0);
1942 if (isvar (&opP->disp))
1943 add_fix (s[1], &opP->disp, 0, 0);
1944 switch (s[1])
1945 {
1946 case 'b':
1947 if (!isbyte (nextword))
1948 opP->error = _("operand out of range");
1949 addword (nextword);
1950 baseo = 0;
1951 break;
1952 case 'w':
1953 if (!isword (nextword))
1954 opP->error = _("operand out of range");
1955 addword (nextword);
1956 baseo = 0;
1957 break;
1958 case 'W':
1959 if (!issword (nextword))
1960 opP->error = _("operand out of range");
1961 addword (nextword);
1962 baseo = 0;
1963 break;
1964 case 'l':
1965 addword (nextword >> 16);
1966 addword (nextword);
1967 baseo = 0;
1968 break;
1969
1970 case 'f':
1971 baseo = 2;
1972 outro = 8;
1973 break;
1974 case 'F':
1975 baseo = 4;
1976 outro = 11;
1977 break;
1978 case 'x':
1979 baseo = 6;
1980 outro = 15;
1981 break;
1982 case 'p':
1983 baseo = 6;
1984 outro = -1;
1985 break;
1986 default:
1987 abort ();
1988 }
1989 if (!baseo)
1990 break;
1991
1992 /* We gotta put out some float */
1993 if (op (&opP->disp) != O_big)
1994 {
1995 valueT val;
1996 int gencnt;
1997
1998 /* Can other cases happen here? */
1999 if (op (&opP->disp) != O_constant)
2000 abort ();
2001
2002 val = (valueT) offs (&opP->disp);
2003 gencnt = 0;
2004 do
2005 {
2006 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2007 val >>= LITTLENUM_NUMBER_OF_BITS;
2008 ++gencnt;
2009 }
2010 while (val != 0);
2011 offs (&opP->disp) = gencnt;
2012 }
2013 if (offs (&opP->disp) > 0)
2014 {
2015 if (offs (&opP->disp) > baseo)
2016 {
2017 as_warn (_("Bignum too big for %c format; truncated"),
2018 s[1]);
2019 offs (&opP->disp) = baseo;
2020 }
2021 baseo -= offs (&opP->disp);
2022 while (baseo--)
2023 addword (0);
2024 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2025 offs (&opP->disp)--;
2026 --wordp)
2027 addword (*wordp);
2028 break;
2029 }
2030 gen_to_words (words, baseo, (long) outro);
2031 for (wordp = words; baseo--; wordp++)
2032 addword (*wordp);
2033 break;
2034 case DREG:
2035 tmpreg = opP->reg - DATA; /* 0.dreg */
2036 break;
2037 case AREG:
2038 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2039 break;
2040 case AINDR:
2041 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2042 break;
2043 case ADEC:
2044 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2045 break;
2046 case AINC:
2047 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2048 break;
2049 case DISP:
2050
2051 nextword = get_num (&opP->disp, 80);
2052
2053 if (opP->reg == PC
2054 && ! isvar (&opP->disp)
2055 && m68k_abspcadd)
2056 {
2057 opP->disp.exp.X_op = O_symbol;
2058#ifndef BFD_ASSEMBLER
2059 opP->disp.exp.X_add_symbol = &abs_symbol;
2060#else
2061 opP->disp.exp.X_add_symbol =
2062 section_symbol (absolute_section);
2063#endif
2064 }
2065
2066 /* Force into index mode. Hope this works */
2067
2068 /* We do the first bit for 32-bit displacements, and the
2069 second bit for 16 bit ones. It is possible that we
2070 should make the default be WORD instead of LONG, but
2071 I think that'd break GCC, so we put up with a little
2072 inefficiency for the sake of working output. */
2073
2074 if (!issword (nextword)
2075 || (isvar (&opP->disp)
2076 && ((opP->disp.size == SIZE_UNSPEC
2077 && flag_short_refs == 0
2078 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2079 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2080 || opP->disp.size == SIZE_LONG)))
2081 {
2082 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2083 || arch_coldfire_p (current_architecture))
252b5132
RH		 2084 opP->error =
2085 _("displacement too large for this architecture; needs 68020 or higher");
2086 if (opP->reg == PC)
2087 tmpreg = 0x3B; /* 7.3 */
2088 else
2089 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2090 if (isvar (&opP->disp))
2091 {
2092 if (opP->reg == PC)
2093 {
2094 if (opP->disp.size == SIZE_LONG
2095#ifdef OBJ_ELF
2096 /* If the displacement needs pic
2097 relocation it cannot be relaxed. */
2098 || opP->disp.pic_reloc != pic_none
2099#endif
2100 )
2101 {
2102 addword (0x0170);
2103 add_fix ('l', &opP->disp, 1, 2);
2104 }
2105 else
2106 {
2107 add_frag (adds (&opP->disp),
2108 offs (&opP->disp),
151337e8 2109 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2110 break;
2111 }
2112 }
2113 else
2114 {
2115 addword (0x0170);
2116 add_fix ('l', &opP->disp, 0, 0);
2117 }
2118 }
2119 else
2120 addword (0x0170);
2121 addword (nextword >> 16);
2122 }
2123 else
2124 {
2125 if (opP->reg == PC)
2126 tmpreg = 0x3A; /* 7.2 */
2127 else
2128 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2129
2130 if (isvar (&opP->disp))
2131 {
2132 if (opP->reg == PC)
2133 {
2134 add_fix ('w', &opP->disp, 1, 0);
2135 }
2136 else
2137 add_fix ('w', &opP->disp, 0, 0);
2138 }
2139 }
2140 addword (nextword);
2141 break;
2142
2143 case POST:
2144 case PRE:
2145 case BASE:
2146 nextword = 0;
2147 baseo = get_num (&opP->disp, 80);
2148 if (opP->mode == POST || opP->mode == PRE)
2149 outro = get_num (&opP->odisp, 80);
2150 /* Figure out the `addressing mode'.
2151 Also turn on the BASE_DISABLE bit, if needed. */
2152 if (opP->reg == PC || opP->reg == ZPC)
2153 {
2154 tmpreg = 0x3b; /* 7.3 */
2155 if (opP->reg == ZPC)
2156 nextword |= 0x80;
2157 }
2158 else if (opP->reg == 0)
2159 {
2160 nextword |= 0x80;
2161 tmpreg = 0x30; /* 6.garbage */
2162 }
2163 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2164 {
2165 nextword |= 0x80;
2166 tmpreg = 0x30 + opP->reg - ZADDR0;
2167 }
2168 else
2169 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2170
2171 siz1 = opP->disp.size;
2172 if (opP->mode == POST || opP->mode == PRE)
2173 siz2 = opP->odisp.size;
2174 else
2175 siz2 = SIZE_UNSPEC;
2176
2177 /* Index register stuff */
2178 if (opP->index.reg != 0
2179 && opP->index.reg >= DATA
2180 && opP->index.reg <= ADDR7)
2181 {
2182 nextword |= (opP->index.reg - DATA) << 12;
2183
2184 if (opP->index.size == SIZE_LONG
2185 || (opP->index.size == SIZE_UNSPEC
2186 && m68k_index_width_default == SIZE_LONG))
2187 nextword |= 0x800;
2188
92774660 2189 if ((opP->index.scale != 1
252b5132 2190 && cpu_of_arch (current_architecture) < m68020)
92774660 2191 || (opP->index.scale == 8
6da466c7 2192 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2193 {
2194 opP->error =
2195 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2196 }
2197
6da466c7
ILT		 2198 if (arch_coldfire_p (current_architecture)
2199 && opP->index.size == SIZE_WORD)
2200 opP->error = _("invalid index size for coldfire");
2201
252b5132
RH		 2202 switch (opP->index.scale)
2203 {
2204 case 1:
2205 break;
2206 case 2:
2207 nextword |= 0x200;
2208 break;
2209 case 4:
2210 nextword |= 0x400;
2211 break;
2212 case 8:
2213 nextword |= 0x600;
2214 break;
2215 default:
2216 abort ();
2217 }
2218 /* IF its simple,
2219 GET US OUT OF HERE! */
2220
2221 /* Must be INDEX, with an index register. Address
2222 register cannot be ZERO-PC, and either :b was
2223 forced, or we know it will fit. For a 68000 or
2224 68010, force this mode anyways, because the
2225 larger modes aren't supported. */
2226 if (opP->mode == BASE
2227 && ((opP->reg >= ADDR0
2228 && opP->reg <= ADDR7)
2229 || opP->reg == PC))
2230 {
2231 if (siz1 == SIZE_BYTE
2232 || cpu_of_arch (current_architecture) < m68020
6da466c7 2233 || arch_coldfire_p (current_architecture)
252b5132
RH		 2234 || (siz1 == SIZE_UNSPEC
2235 && ! isvar (&opP->disp)
2236 && issbyte (baseo)))
2237 {
2238 nextword += baseo & 0xff;
2239 addword (nextword);
2240 if (isvar (&opP->disp))
2241 {
2242 /* Do a byte relocation. If it doesn't
2243 fit (possible on m68000) let the
2244 fixup processing complain later. */
2245 if (opP->reg == PC)
2246 add_fix ('B', &opP->disp, 1, 1);
2247 else
2248 add_fix ('B', &opP->disp, 0, 0);
2249 }
2250 else if (siz1 != SIZE_BYTE)
2251 {
2252 if (siz1 != SIZE_UNSPEC)
2253 as_warn (_("Forcing byte displacement"));
2254 if (! issbyte (baseo))
2255 opP->error = _("byte displacement out of range");
2256 }
2257
2258 break;
2259 }
2260 else if (siz1 == SIZE_UNSPEC
2261 && opP->reg == PC
2262 && isvar (&opP->disp)
2263 && subs (&opP->disp) == NULL
2264#ifdef OBJ_ELF
2265 /* If the displacement needs pic
2266 relocation it cannot be relaxed. */
2267 && opP->disp.pic_reloc == pic_none
2268#endif
2269 )
2270 {
2271 /* The code in md_convert_frag_1 needs to be
2272 able to adjust nextword. Call frag_grow
2273 to ensure that we have enough space in
2274 the frag obstack to make all the bytes
2275 contiguous. */
2276 frag_grow (14);
2277 nextword += baseo & 0xff;
2278 addword (nextword);
2279 add_frag (adds (&opP->disp), offs (&opP->disp),
2280 TAB (PCINDEX, SZ_UNDEF));
2281
2282 break;
2283 }
2284 }
2285 }
2286 else
2287 {
2288 nextword |= 0x40; /* No index reg */
2289 if (opP->index.reg >= ZDATA0
2290 && opP->index.reg <= ZDATA7)
2291 nextword |= (opP->index.reg - ZDATA0) << 12;
2292 else if (opP->index.reg >= ZADDR0
2293 || opP->index.reg <= ZADDR7)
2294 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2295 }
2296
2297 /* It isn't simple. */
2298
2299 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2300 || arch_coldfire_p (current_architecture))
252b5132
RH		 2301 opP->error =
2302 _("invalid operand mode for this architecture; needs 68020 or higher");
2303
2304 nextword |= 0x100;
2305 /* If the guy specified a width, we assume that it is
2306 wide enough. Maybe it isn't. If so, we lose. */
2307 switch (siz1)
2308 {
2309 case SIZE_UNSPEC:
2310 if (isvar (&opP->disp)
2311 ? m68k_rel32
2312 : ! issword (baseo))
2313 {
2314 siz1 = SIZE_LONG;
2315 nextword |= 0x30;
2316 }
2317 else if (! isvar (&opP->disp) && baseo == 0)
2318 nextword |= 0x10;
2319 else
2320 {
2321 nextword |= 0x20;
2322 siz1 = SIZE_WORD;
2323 }
2324 break;
2325 case SIZE_BYTE:
2326 as_warn (_(":b not permitted; defaulting to :w"));
2327 /* Fall through. */
2328 case SIZE_WORD:
2329 nextword |= 0x20;
2330 break;
2331 case SIZE_LONG:
2332 nextword |= 0x30;
2333 break;
2334 }
2335
2336 /* Figure out innner displacement stuff */
2337 if (opP->mode == POST || opP->mode == PRE)
2338 {
2339 if (cpu_of_arch (current_architecture) & cpu32)
2340 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2341 switch (siz2)
2342 {
2343 case SIZE_UNSPEC:
2344 if (isvar (&opP->odisp)
2345 ? m68k_rel32
2346 : ! issword (outro))
2347 {
2348 siz2 = SIZE_LONG;
2349 nextword |= 0x3;
2350 }
2351 else if (! isvar (&opP->odisp) && outro == 0)
2352 nextword |= 0x1;
2353 else
2354 {
2355 nextword |= 0x2;
2356 siz2 = SIZE_WORD;
2357 }
2358 break;
2359 case 1:
2360 as_warn (_(":b not permitted; defaulting to :w"));
2361 /* Fall through. */
2362 case 2:
2363 nextword |= 0x2;
2364 break;
2365 case 3:
2366 nextword |= 0x3;
2367 break;
2368 }
2369 if (opP->mode == POST
2370 && (nextword & 0x40) == 0)
2371 nextword |= 0x04;
2372 }
2373 addword (nextword);
2374
2375 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2376 {
2377 if (opP->reg == PC || opP->reg == ZPC)
2378 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2379 else
2380 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2381 }
2382 if (siz1 == SIZE_LONG)
2383 addword (baseo >> 16);
2384 if (siz1 != SIZE_UNSPEC)
2385 addword (baseo);
2386
2387 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2388 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2389 if (siz2 == SIZE_LONG)
2390 addword (outro >> 16);
2391 if (siz2 != SIZE_UNSPEC)
2392 addword (outro);
2393
2394 break;
2395
2396 case ABSL:
2397 nextword = get_num (&opP->disp, 80);
2398 switch (opP->disp.size)
2399 {
2400 default:
2401 abort ();
2402 case SIZE_UNSPEC:
2403 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2404 {
2405 tmpreg = 0x38; /* 7.0 */
2406 addword (nextword);
2407 break;
2408 }
252b5132
RH		 2409 if (isvar (&opP->disp)
2410 && !subs (&opP->disp)
2411 && adds (&opP->disp)
2412#ifdef OBJ_ELF
2413 /* If the displacement needs pic relocation it
2414 cannot be relaxed. */
2415 && opP->disp.pic_reloc == pic_none
2416#endif
252b5132
RH		 2417 && !flag_long_jumps
2418 && !strchr ("~%&$?", s[0]))
2419 {
2420 tmpreg = 0x3A; /* 7.2 */
2421 add_frag (adds (&opP->disp),
2422 offs (&opP->disp),
151337e8 2423 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2424 break;
2425 }
2426 /* Fall through into long */
2427 case SIZE_LONG:
2428 if (isvar (&opP->disp))
2429 add_fix ('l', &opP->disp, 0, 0);
2430
2431 tmpreg = 0x39;/* 7.1 mode */
2432 addword (nextword >> 16);
2433 addword (nextword);
2434 break;
2435
2436 case SIZE_BYTE:
2437 as_bad (_("unsupported byte value; use a different suffix"));
2438 /* Fall through. */
2439 case SIZE_WORD: /* Word */
2440 if (isvar (&opP->disp))
2441 add_fix ('w', &opP->disp, 0, 0);
2442
2443 tmpreg = 0x38;/* 7.0 mode */
2444 addword (nextword);
2445 break;
2446 }
2447 break;
2448 case CONTROL:
2449 case FPREG:
2450 default:
2451 as_bad (_("unknown/incorrect operand"));
bc805888 2452 /* abort (); */
252b5132
RH		 2453 }
2454 install_gen_operand (s[1], tmpreg);
2455 break;
2456
2457 case '#':
2458 case '^':
2459 switch (s[1])
2460 { /* JF: I hate floating point! */
2461 case 'j':
2462 tmpreg = 70;
2463 break;
2464 case '8':
2465 tmpreg = 20;
2466 break;
2467 case 'C':
2468 tmpreg = 50;
2469 break;
2470 case '3':
2471 default:
2472 tmpreg = 80;
2473 break;
2474 }
2475 tmpreg = get_num (&opP->disp, tmpreg);
2476 if (isvar (&opP->disp))
2477 add_fix (s[1], &opP->disp, 0, 0);
2478 switch (s[1])
2479 {
2480 case 'b': /* Danger: These do no check for
2481 certain types of overflow.
2482 user beware! */
2483 if (!isbyte (tmpreg))
2484 opP->error = _("out of range");
2485 insop (tmpreg, opcode);
2486 if (isvar (&opP->disp))
2487 the_ins.reloc[the_ins.nrel - 1].n =
2488 (opcode->m_codenum) * 2 + 1;
2489 break;
2490 case 'B':
2491 if (!issbyte (tmpreg))
2492 opP->error = _("out of range");
2493 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2494 if (isvar (&opP->disp))
2495 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2496 break;
2497 case 'w':
2498 if (!isword (tmpreg))
2499 opP->error = _("out of range");
2500 insop (tmpreg, opcode);
2501 if (isvar (&opP->disp))
2502 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2503 break;
2504 case 'W':
2505 if (!issword (tmpreg))
2506 opP->error = _("out of range");
2507 insop (tmpreg, opcode);
2508 if (isvar (&opP->disp))
2509 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2510 break;
2511 case 'l':
2512 /* Because of the way insop works, we put these two out
2513 backwards. */
2514 insop (tmpreg, opcode);
2515 insop (tmpreg >> 16, opcode);
2516 if (isvar (&opP->disp))
2517 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2518 break;
2519 case '3':
2520 tmpreg &= 0xFF;
2521 case '8':
2522 case 'C':
2523 case 'j':
2524 install_operand (s[1], tmpreg);
2525 break;
2526 default:
2527 abort ();
2528 }
2529 break;
2530
2531 case '+':
2532 case '-':
2533 case 'A':
2534 case 'a':
2535 install_operand (s[1], opP->reg - ADDR);
2536 break;
2537
2538 case 'B':
2539 tmpreg = get_num (&opP->disp, 80);
2540 switch (s[1])
2541 {
2542 case 'B':
8390138c 2543 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2544 break;
2545 case 'W':
2546 add_fix ('w', &opP->disp, 1, 0);
2547 addword (0);
2548 break;
2549 case 'L':
2550 long_branch:
151337e8 2551 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2552 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2553 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2554 add_fix ('l', &opP->disp, 1, 0);
2555 addword (0);
2556 addword (0);
2557 break;
2558 case 'g':
2559 if (subs (&opP->disp)) /* We can't relax it */
2560 goto long_branch;
2561
2562#ifdef OBJ_ELF
2563 /* If the displacement needs pic relocation it cannot be
2564 relaxed. */
2565 if (opP->disp.pic_reloc != pic_none)
2566 goto long_branch;
2567#endif
252b5132 2568 /* This could either be a symbol, or an absolute
151337e8
NC		 2569 address. If it's an absolute address, turn it into
2570 an absolute jump right here and keep it out of the
2571 relaxer. */
2572 if (adds (&opP->disp) == 0)
2573 {
2574 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2575 the_ins.opcode[0] = 0x4EF9;
151337e8 2576 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2577 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2578 else /* jCC */
2579 {
2580 the_ins.opcode[0] ^= 0x0100;
2581 the_ins.opcode[0] |= 0x0006;
18566f55 2582 addword (0x4EF9);
151337e8
NC		 2583 }
2584 add_fix ('l', &opP->disp, 0, 0);
2585 addword (0);
2586 addword (0);
2587 break;
2588 }
2589
2590 /* Now we know it's going into the relaxer. Now figure
2591 out which mode. We try in this order of preference:
2592 long branch, absolute jump, byte/word branches only. */
2593 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2594 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2595 TAB (BRANCHBWL, SZ_UNDEF));
2596 else if (! flag_keep_pcrel)
2597 {
2598 if ((the_ins.opcode[0] == 0x6000)
2599 || (the_ins.opcode[0] == 0x6100))
2600 add_frag (adds (&opP->disp), offs (&opP->disp),
2601 TAB (BRABSJUNC, SZ_UNDEF));
2602 else
2603 add_frag (adds (&opP->disp), offs (&opP->disp),
2604 TAB (BRABSJCOND, SZ_UNDEF));
2605 }
252b5132
RH		 2606 else
2607 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2608 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2609 break;
2610 case 'w':
2611 if (isvar (&opP->disp))
2612 {
151337e8
NC		 2613 /* Check for DBcc instructions. We can relax them,
2614 but only if we have long branches and/or absolute
2615 jumps. */
2616 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2617 && (HAVE_LONG_BRANCH (current_architecture)
2618 || (! flag_keep_pcrel)))
252b5132 2619 {
151337e8
NC		 2620 if (HAVE_LONG_BRANCH (current_architecture))
2621 add_frag (adds (&opP->disp), offs (&opP->disp),
2622 TAB (DBCCLBR, SZ_UNDEF));
2623 else
2624 add_frag (adds (&opP->disp), offs (&opP->disp),
2625 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2626 break;
2627 }
252b5132
RH		 2628 add_fix ('w', &opP->disp, 1, 0);
2629 }
2630 addword (0);
2631 break;
2632 case 'C': /* Fixed size LONG coproc branches */
2633 add_fix ('l', &opP->disp, 1, 0);
2634 addword (0);
2635 addword (0);
2636 break;
2637 case 'c': /* Var size Coprocesssor branches */
151337e8 2638 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2639 {
252b5132
RH		 2640 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2641 add_fix ('l', &opP->disp, 1, 0);
2642 addword (0);
2643 addword (0);
2644 }
151337e8
NC		 2645 else
2646 add_frag (adds (&opP->disp), offs (&opP->disp),
2647 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2648 break;
2649 default:
2650 abort ();
2651 }
2652 break;
2653
2654 case 'C': /* Ignore it */
2655 break;
2656
2657 case 'd': /* JF this is a kludge */
2658 install_operand ('s', opP->reg - ADDR);
2659 tmpreg = get_num (&opP->disp, 80);
2660 if (!issword (tmpreg))
2661 {
2662 as_warn (_("Expression out of range, using 0"));
2663 tmpreg = 0;
2664 }
2665 addword (tmpreg);
2666 break;
2667
2668 case 'D':
2669 install_operand (s[1], opP->reg - DATA);
2670 break;
2671
6da466c7
ILT		 2672 case 'E': /* Ignore it */
2673 break;
2674
252b5132
RH		 2675 case 'F':
2676 install_operand (s[1], opP->reg - FP0);
2677 break;
2678
6da466c7
ILT		 2679 case 'G': /* Ignore it */
2680 case 'H':
2681 break;
2682
252b5132
RH		 2683 case 'I':
2684 tmpreg = opP->reg - COP0;
2685 install_operand (s[1], tmpreg);
2686 break;
2687
2688 case 'J': /* JF foo */
2689 switch (opP->reg)
2690 {
2691 case SFC:
2692 tmpreg = 0x000;
2693 break;
2694 case DFC:
2695 tmpreg = 0x001;
2696 break;
2697 case CACR:
2698 tmpreg = 0x002;
2699 break;
2700 case TC:
2701 tmpreg = 0x003;
2702 break;
2703 case ITT0:
2704 tmpreg = 0x004;
2705 break;
2706 case ITT1:
2707 tmpreg = 0x005;
2708 break;
2709 case DTT0:
2710 tmpreg = 0x006;
2711 break;
2712 case DTT1:
2713 tmpreg = 0x007;
2714 break;
2715 case BUSCR:
2716 tmpreg = 0x008;
2717 break;
2718
2719 case USP:
2720 tmpreg = 0x800;
2721 break;
2722 case VBR:
2723 tmpreg = 0x801;
2724 break;
2725 case CAAR:
2726 tmpreg = 0x802;
2727 break;
2728 case MSP:
2729 tmpreg = 0x803;
2730 break;
2731 case ISP:
2732 tmpreg = 0x804;
2733 break;
2734 case MMUSR:
2735 tmpreg = 0x805;
2736 break;
2737 case URP:
2738 tmpreg = 0x806;
2739 break;
2740 case SRP:
2741 tmpreg = 0x807;
2742 break;
2743 case PCR:
2744 tmpreg = 0x808;
2745 break;
2746 case ROMBAR:
2747 tmpreg = 0xC00;
2748 break;
2749 case RAMBAR0:
2750 tmpreg = 0xC04;
2751 break;
2752 case RAMBAR1:
2753 tmpreg = 0xC05;
2754 break;
2755 case MBAR:
2756 tmpreg = 0xC0F;
2757 break;
2758 default:
2759 abort ();
2760 }
2761 install_operand (s[1], tmpreg);
2762 break;
2763
2764 case 'k':
2765 tmpreg = get_num (&opP->disp, 55);
2766 install_operand (s[1], tmpreg & 0x7f);
2767 break;
2768
2769 case 'l':
2770 tmpreg = opP->mask;
2771 if (s[1] == 'w')
2772 {
2773 if (tmpreg & 0x7FF0000)
2774 as_bad (_("Floating point register in register list"));
2775 insop (reverse_16_bits (tmpreg), opcode);
2776 }
2777 else
2778 {
2779 if (tmpreg & 0x700FFFF)
2780 as_bad (_("Wrong register in floating-point reglist"));
2781 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2782 }
2783 break;
2784
2785 case 'L':
2786 tmpreg = opP->mask;
2787 if (s[1] == 'w')
2788 {
2789 if (tmpreg & 0x7FF0000)
2790 as_bad (_("Floating point register in register list"));
2791 insop (tmpreg, opcode);
2792 }
2793 else if (s[1] == '8')
2794 {
2795 if (tmpreg & 0x0FFFFFF)
2796 as_bad (_("incorrect register in reglist"));
2797 install_operand (s[1], tmpreg >> 24);
2798 }
2799 else
2800 {
2801 if (tmpreg & 0x700FFFF)
2802 as_bad (_("wrong register in floating-point reglist"));
2803 else
2804 install_operand (s[1], tmpreg >> 16);
2805 }
2806 break;
2807
2808 case 'M':
2809 install_operand (s[1], get_num (&opP->disp, 60));
2810 break;
2811
2812 case 'O':
2813 tmpreg = ((opP->mode == DREG)
8fce3f5e 2814 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2815 : (get_num (&opP->disp, 40) & 0x1F));
2816 install_operand (s[1], tmpreg);
2817 break;
2818
2819 case 'Q':
2820 tmpreg = get_num (&opP->disp, 10);
2821 if (tmpreg == 8)
2822 tmpreg = 0;
2823 install_operand (s[1], tmpreg);
2824 break;
2825
2826 case 'R':
2827 /* This depends on the fact that ADDR registers are eight
2828 more than their corresponding DATA regs, so the result
2829 will have the ADDR_REG bit set */
2830 install_operand (s[1], opP->reg - DATA);
2831 break;
2832
2833 case 'r':
2834 if (opP->mode == AINDR)
2835 install_operand (s[1], opP->reg - DATA);
2836 else
2837 install_operand (s[1], opP->index.reg - DATA);
2838 break;
2839
2840 case 's':
2841 if (opP->reg == FPI)
2842 tmpreg = 0x1;
2843 else if (opP->reg == FPS)
2844 tmpreg = 0x2;
2845 else if (opP->reg == FPC)
2846 tmpreg = 0x4;
2847 else
2848 abort ();
2849 install_operand (s[1], tmpreg);
2850 break;
2851
2852 case 'S': /* Ignore it */
2853 break;
2854
2855 case 'T':
2856 install_operand (s[1], get_num (&opP->disp, 30));
2857 break;
2858
2859 case 'U': /* Ignore it */
2860 break;
2861
2862 case 'c':
2863 switch (opP->reg)
2864 {
2865 case NC:
2866 tmpreg = 0;
2867 break;
2868 case DC:
2869 tmpreg = 1;
2870 break;
2871 case IC:
2872 tmpreg = 2;
2873 break;
2874 case BC:
2875 tmpreg = 3;
2876 break;
2877 default:
2878 as_fatal (_("failed sanity check"));
2879 } /* switch on cache token */
2880 install_operand (s[1], tmpreg);
2881 break;
2882#ifndef NO_68851
92774660 2883 /* JF: These are out of order, I fear. */
252b5132
RH		 2884 case 'f':
2885 switch (opP->reg)
2886 {
2887 case SFC:
2888 tmpreg = 0;
2889 break;
2890 case DFC:
2891 tmpreg = 1;
2892 break;
2893 default:
2894 abort ();
2895 }
2896 install_operand (s[1], tmpreg);
2897 break;
2898
2899 case '0':
2900 case '1':
2901 case '2':
2902 switch (opP->reg)
2903 {
2904 case TC:
2905 tmpreg = 0;
2906 break;
2907 case CAL:
2908 tmpreg = 4;
2909 break;
2910 case VAL:
2911 tmpreg = 5;
2912 break;
2913 case SCC:
2914 tmpreg = 6;
2915 break;
2916 case AC:
2917 tmpreg = 7;
2918 break;
2919 default:
2920 abort ();
2921 }
2922 install_operand (s[1], tmpreg);
2923 break;
2924
2925 case 'V':
2926 if (opP->reg == VAL)
2927 break;
2928 abort ();
2929
2930 case 'W':
2931 switch (opP->reg)
2932 {
2933 case DRP:
2934 tmpreg = 1;
2935 break;
2936 case SRP:
2937 tmpreg = 2;
2938 break;
2939 case CRP:
2940 tmpreg = 3;
2941 break;
2942 default:
2943 abort ();
2944 }
2945 install_operand (s[1], tmpreg);
2946 break;
2947
2948 case 'X':
2949 switch (opP->reg)
2950 {
2951 case BAD:
2952 case BAD + 1:
2953 case BAD + 2:
2954 case BAD + 3:
2955 case BAD + 4:
2956 case BAD + 5:
2957 case BAD + 6:
2958 case BAD + 7:
2959 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2960 break;
2961
2962 case BAC:
2963 case BAC + 1:
2964 case BAC + 2:
2965 case BAC + 3:
2966 case BAC + 4:
2967 case BAC + 5:
2968 case BAC + 6:
2969 case BAC + 7:
2970 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2971 break;
2972
2973 default:
2974 abort ();
2975 }
2976 install_operand (s[1], tmpreg);
2977 break;
2978 case 'Y':
2979 know (opP->reg == PSR);
2980 break;
2981 case 'Z':
2982 know (opP->reg == PCSR);
2983 break;
2984#endif /* m68851 */
2985 case '3':
2986 switch (opP->reg)
2987 {
2988 case TT0:
2989 tmpreg = 2;
2990 break;
2991 case TT1:
2992 tmpreg = 3;
2993 break;
2994 default:
2995 abort ();
2996 }
2997 install_operand (s[1], tmpreg);
2998 break;
2999 case 't':
3000 tmpreg = get_num (&opP->disp, 20);
3001 install_operand (s[1], tmpreg);
3002 break;
3003 case '_': /* used only for move16 absolute 32-bit address */
3004 if (isvar (&opP->disp))
3005 add_fix ('l', &opP->disp, 0, 0);
3006 tmpreg = get_num (&opP->disp, 80);
3007 addword (tmpreg >> 16);
3008 addword (tmpreg & 0xFFFF);
3009 break;
6da466c7
ILT		 3010 case 'u':
3011 install_operand (s[1], opP->reg - DATA0L);
3012 opP->reg -= (DATA0L);
3013 opP->reg &= 0x0F; /* remove upper/lower bit */
3014 break;
252b5132
RH		 3015 default:
3016 abort ();
3017 }
3018 }
3019
3020 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3021 instruction, ready to be emitted. . . */
252b5132
RH		 3022}
3023
3024static int
3025reverse_16_bits (in)
3026 int in;
3027{
3028 int out = 0;
3029 int n;
3030
3031 static int mask[16] =
3032 {
3033 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3034 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3035 };
3036 for (n = 0; n < 16; n++)
3037 {
3038 if (in & mask[n])
3039 out |= mask[15 - n];
3040 }
3041 return out;
3042} /* reverse_16_bits() */
3043
3044static int
3045reverse_8_bits (in)
3046 int in;
3047{
3048 int out = 0;
3049 int n;
3050
3051 static int mask[8] =
3052 {
3053 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3054 };
3055
3056 for (n = 0; n < 8; n++)
3057 {
3058 if (in & mask[n])
3059 out |= mask[7 - n];
3060 }
3061 return out;
3062} /* reverse_8_bits() */
3063
3064/* Cause an extra frag to be generated here, inserting up to 10 bytes
3065 (that value is chosen in the frag_var call in md_assemble). TYPE
3066 is the subtype of the frag to be generated; its primary type is
3067 rs_machine_dependent.
3068
3069 The TYPE parameter is also used by md_convert_frag_1 and
3070 md_estimate_size_before_relax. The appropriate type of fixup will
3071 be emitted by md_convert_frag_1.
3072
3073 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3074static void
3075install_operand (mode, val)
3076 int mode;
3077 int val;
3078{
3079 switch (mode)
3080 {
3081 case 's':
3082 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3083 break;
3084 case 'd':
3085 the_ins.opcode[0] |= val << 9;
3086 break;
3087 case '1':
3088 the_ins.opcode[1] |= val << 12;
3089 break;
3090 case '2':
3091 the_ins.opcode[1] |= val << 6;
3092 break;
3093 case '3':
3094 the_ins.opcode[1] |= val;
3095 break;
3096 case '4':
3097 the_ins.opcode[2] |= val << 12;
3098 break;
3099 case '5':
3100 the_ins.opcode[2] |= val << 6;
3101 break;
3102 case '6':
3103 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3104 three words long! */
3105 the_ins.numo++;
3106 the_ins.opcode[2] |= val;
3107 break;
3108 case '7':
3109 the_ins.opcode[1] |= val << 7;
3110 break;
3111 case '8':
3112 the_ins.opcode[1] |= val << 10;
3113 break;
3114#ifndef NO_68851
3115 case '9':
3116 the_ins.opcode[1] |= val << 5;
3117 break;
3118#endif
3119
3120 case 't':
3121 the_ins.opcode[1] |= (val << 10) | (val << 7);
3122 break;
3123 case 'D':
3124 the_ins.opcode[1] |= (val << 12) | val;
3125 break;
3126 case 'g':
3127 the_ins.opcode[0] |= val = 0xff;
3128 break;
3129 case 'i':
3130 the_ins.opcode[0] |= val << 9;
3131 break;
3132 case 'C':
3133 the_ins.opcode[1] |= val;
3134 break;
3135 case 'j':
3136 the_ins.opcode[1] |= val;
3137 the_ins.numo++; /* What a hack */
3138 break;
3139 case 'k':
3140 the_ins.opcode[1] |= val << 4;
3141 break;
3142 case 'b':
3143 case 'w':
3144 case 'W':
3145 case 'l':
3146 break;
3147 case 'e':
3148 the_ins.opcode[0] |= (val << 6);
3149 break;
3150 case 'L':
3151 the_ins.opcode[1] = (val >> 16);
3152 the_ins.opcode[2] = val & 0xffff;
3153 break;
6da466c7
ILT		 3154 case 'm':
3155 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3156 the_ins.opcode[0] |= ((val & 0x7) << 9);
3157 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3158 break;
3159 case 'n':
3160 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3161 the_ins.opcode[0] |= ((val & 0x7) << 9);
3162 break;
3163 case 'o':
3164 the_ins.opcode[1] |= val << 12;
3165 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3166 break;
3167 case 'M':
3168 the_ins.opcode[0] |= (val & 0xF);
3169 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3170 break;
3171 case 'N':
3172 the_ins.opcode[1] |= (val & 0xF);
3173 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3174 break;
3175 case 'h':
3176 the_ins.opcode[1] |= ((val != 1) << 10);
3177 break;
252b5132
RH		 3178 case 'c':
3179 default:
3180 as_fatal (_("failed sanity check."));
3181 }
3182} /* install_operand() */
3183
3184static void
3185install_gen_operand (mode, val)
3186 int mode;
3187 int val;
3188{
3189 switch (mode)
3190 {
3191 case 's':
3192 the_ins.opcode[0] |= val;
3193 break;
3194 case 'd':
3195 /* This is a kludge!!! */
3196 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3197 break;
3198 case 'b':
3199 case 'w':
3200 case 'l':
3201 case 'f':
3202 case 'F':
3203 case 'x':
3204 case 'p':
3205 the_ins.opcode[0] |= val;
3206 break;
3207 /* more stuff goes here */
3208 default:
3209 as_fatal (_("failed sanity check."));
3210 }
3211} /* install_gen_operand() */
3212
3213/*
3214 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3215 * then deal with the bitfield hack.
3216 */
3217
3218static char *
3219crack_operand (str, opP)
3220 register char *str;
3221 register struct m68k_op *opP;
3222{
3223 register int parens;
3224 register int c;
3225 register char *beg_str;
3226 int inquote = 0;
3227
3228 if (!str)
3229 {
3230 return str;
3231 }
3232 beg_str = str;
3233 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3234 {
3235 if (! inquote)
3236 {
3237 if (*str == '(')
3238 parens++;
3239 else if (*str == ')')
3240 {
3241 if (!parens)
3242 { /* ERROR */
3243 opP->error = _("Extra )");
3244 return str;
3245 }
3246 --parens;
3247 }
3248 }
3249 if (flag_mri && *str == '\'')
3250 inquote = ! inquote;
3251 }
3252 if (!*str && parens)
3253 { /* ERROR */
3254 opP->error = _("Missing )");
3255 return str;
3256 }
3257 c = *str;
3258 *str = '\0';
3259 if (m68k_ip_op (beg_str, opP) != 0)
3260 {
3261 *str = c;
3262 return str;
3263 }
3264 *str = c;
3265 if (c == '}')
3266 c = *++str; /* JF bitfield hack */
3267 if (c)
3268 {
3269 c = *++str;
3270 if (!c)
3271 as_bad (_("Missing operand"));
3272 }
3273
3274 /* Detect MRI REG symbols and convert them to REGLSTs. */
3275 if (opP->mode == CONTROL && (int)opP->reg < 0)
3276 {
3277 opP->mode = REGLST;
3278 opP->mask = ~(int)opP->reg;
3279 opP->reg = 0;
3280 }
3281
3282 return str;
3283}
3284
3285/* This is the guts of the machine-dependent assembler. STR points to a
3286 machine dependent instruction. This function is supposed to emit
3287 the frags/bytes it assembles to.
3288 */
3289
3290static void
3291insert_reg (regname, regnum)
3292 const char *regname;
3293 int regnum;
3294{
3295 char buf[100];
3296 int i;
3297
3298#ifdef REGISTER_PREFIX
3299 if (!flag_reg_prefix_optional)
3300 {
3301 buf[0] = REGISTER_PREFIX;
3302 strcpy (buf + 1, regname);
3303 regname = buf;
3304 }
3305#endif
3306
3307 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3308 &zero_address_frag));
3309
3310 for (i = 0; regname[i]; i++)
3882b010 3311 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3312 buf[i] = '\0';
3313
3314 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3315 &zero_address_frag));
3316}
3317
3318struct init_entry
3319 {
3320 const char *name;
3321 int number;
3322 };
3323
3324static const struct init_entry init_table[] =
3325{
3326 { "d0", DATA0 },
3327 { "d1", DATA1 },
3328 { "d2", DATA2 },
3329 { "d3", DATA3 },
3330 { "d4", DATA4 },
3331 { "d5", DATA5 },
3332 { "d6", DATA6 },
3333 { "d7", DATA7 },
3334 { "a0", ADDR0 },
3335 { "a1", ADDR1 },
3336 { "a2", ADDR2 },
3337 { "a3", ADDR3 },
3338 { "a4", ADDR4 },
3339 { "a5", ADDR5 },
3340 { "a6", ADDR6 },
3341 { "fp", ADDR6 },
3342 { "a7", ADDR7 },
3343 { "sp", ADDR7 },
3344 { "ssp", ADDR7 },
3345 { "fp0", FP0 },
3346 { "fp1", FP1 },
3347 { "fp2", FP2 },
3348 { "fp3", FP3 },
3349 { "fp4", FP4 },
3350 { "fp5", FP5 },
3351 { "fp6", FP6 },
3352 { "fp7", FP7 },
3353 { "fpi", FPI },
3354 { "fpiar", FPI },
3355 { "fpc", FPI },
3356 { "fps", FPS },
3357 { "fpsr", FPS },
3358 { "fpc", FPC },
3359 { "fpcr", FPC },
3360 { "control", FPC },
3361 { "status", FPS },
3362 { "iaddr", FPI },
3363
3364 { "cop0", COP0 },
3365 { "cop1", COP1 },
3366 { "cop2", COP2 },
3367 { "cop3", COP3 },
3368 { "cop4", COP4 },
3369 { "cop5", COP5 },
3370 { "cop6", COP6 },
3371 { "cop7", COP7 },
3372 { "pc", PC },
3373 { "zpc", ZPC },
3374 { "sr", SR },
3375
3376 { "ccr", CCR },
3377 { "cc", CCR },
3378
6da466c7
ILT		 3379 { "acc", ACC },
3380 { "macsr", MACSR },
3381 { "mask", MASK },
3382
252b5132
RH		 3383 /* control registers */
3384 { "sfc", SFC }, /* Source Function Code */
3385 { "sfcr", SFC },
3386 { "dfc", DFC }, /* Destination Function Code */
3387 { "dfcr", DFC },
3388 { "cacr", CACR }, /* Cache Control Register */
3389 { "caar", CAAR }, /* Cache Address Register */
3390
3391 { "usp", USP }, /* User Stack Pointer */
3392 { "vbr", VBR }, /* Vector Base Register */
3393 { "msp", MSP }, /* Master Stack Pointer */
3394 { "isp", ISP }, /* Interrupt Stack Pointer */
3395
3396 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3397 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3398 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3399 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3400
3401 /* 68ec040 versions of same */
3402 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3403 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3404 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3405 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3406
3407 /* mcf5200 versions of same. The ColdFire programmer's reference
3408 manual indicated that the order is 2,3,0,1, but Ken Rose
3409 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3410 { "acr0", ITT0 }, /* Access Control Unit 0 */
3411 { "acr1", ITT1 }, /* Access Control Unit 1 */
3412 { "acr2", DTT0 }, /* Access Control Unit 2 */
3413 { "acr3", DTT1 }, /* Access Control Unit 3 */
3414
3415 { "tc", TC }, /* MMU Translation Control Register */
3416 { "tcr", TC },
3417
3418 { "mmusr", MMUSR }, /* MMU Status Register */
3419 { "srp", SRP }, /* User Root Pointer */
3420 { "urp", URP }, /* Supervisor Root Pointer */
3421
3422 { "buscr", BUSCR },
3423 { "pcr", PCR },
3424
3425 { "rombar", ROMBAR }, /* ROM Base Address Register */
3426 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3427 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3428 { "mbar", MBAR }, /* Module Base Address Register */
3429 /* end of control registers */
3430
3431 { "ac", AC },
3432 { "bc", BC },
3433 { "cal", CAL },
3434 { "crp", CRP },
3435 { "drp", DRP },
3436 { "pcsr", PCSR },
3437 { "psr", PSR },
3438 { "scc", SCC },
3439 { "val", VAL },
3440 { "bad0", BAD0 },
3441 { "bad1", BAD1 },
3442 { "bad2", BAD2 },
3443 { "bad3", BAD3 },
3444 { "bad4", BAD4 },
3445 { "bad5", BAD5 },
3446 { "bad6", BAD6 },
3447 { "bad7", BAD7 },
3448 { "bac0", BAC0 },
3449 { "bac1", BAC1 },
3450 { "bac2", BAC2 },
3451 { "bac3", BAC3 },
3452 { "bac4", BAC4 },
3453 { "bac5", BAC5 },
3454 { "bac6", BAC6 },
3455 { "bac7", BAC7 },
3456
3457 { "ic", IC },
3458 { "dc", DC },
3459 { "nc", NC },
3460
3461 { "tt0", TT0 },
3462 { "tt1", TT1 },
3463 /* 68ec030 versions of same */
3464 { "ac0", TT0 },
3465 { "ac1", TT1 },
3466 /* 68ec030 access control unit, identical to 030 MMU status reg */
3467 { "acusr", PSR },
3468
3469 /* Suppressed data and address registers. */
3470 { "zd0", ZDATA0 },
3471 { "zd1", ZDATA1 },
3472 { "zd2", ZDATA2 },
3473 { "zd3", ZDATA3 },
3474 { "zd4", ZDATA4 },
3475 { "zd5", ZDATA5 },
3476 { "zd6", ZDATA6 },
3477 { "zd7", ZDATA7 },
3478 { "za0", ZADDR0 },
3479 { "za1", ZADDR1 },
3480 { "za2", ZADDR2 },
3481 { "za3", ZADDR3 },
3482 { "za4", ZADDR4 },
3483 { "za5", ZADDR5 },
3484 { "za6", ZADDR6 },
3485 { "za7", ZADDR7 },
3486
92774660 3487 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3488 { "d0l", DATA0L },
3489 { "d1l", DATA1L },
3490 { "d2l", DATA2L },
3491 { "d3l", DATA3L },
3492 { "d4l", DATA4L },
3493 { "d5l", DATA5L },
3494 { "d6l", DATA6L },
3495 { "d7l", DATA7L },
3496
3497 { "a0l", ADDR0L },
3498 { "a1l", ADDR1L },
3499 { "a2l", ADDR2L },
3500 { "a3l", ADDR3L },
3501 { "a4l", ADDR4L },
3502 { "a5l", ADDR5L },
3503 { "a6l", ADDR6L },
3504 { "a7l", ADDR7L },
3505
3506 { "d0u", DATA0U },
3507 { "d1u", DATA1U },
3508 { "d2u", DATA2U },
3509 { "d3u", DATA3U },
3510 { "d4u", DATA4U },
3511 { "d5u", DATA5U },
3512 { "d6u", DATA6U },
3513 { "d7u", DATA7U },
3514
3515 { "a0u", ADDR0U },
3516 { "a1u", ADDR1U },
3517 { "a2u", ADDR2U },
3518 { "a3u", ADDR3U },
3519 { "a4u", ADDR4U },
3520 { "a5u", ADDR5U },
3521 { "a6u", ADDR6U },
3522 { "a7u", ADDR7U },
3523
252b5132
RH		 3524 { 0, 0 }
3525};
3526
3527static void
3528init_regtable ()
3529{
3530 int i;
3531 for (i = 0; init_table[i].name; i++)
3532 insert_reg (init_table[i].name, init_table[i].number);
3533}
3534
3535static int no_68851, no_68881;
3536
3537#ifdef OBJ_AOUT
3538/* a.out machine type. Default to 68020. */
3539int m68k_aout_machtype = 2;
3540#endif
3541
3542void
3543md_assemble (str)
3544 char *str;
3545{
3546 const char *er;
3547 short *fromP;
3548 char *toP = NULL;
3549 int m, n = 0;
3550 char *to_beg_P;
3551 int shorts_this_frag;
3552 fixS *fixP;
3553
3554 /* In MRI mode, the instruction and operands are separated by a
3555 space. Anything following the operands is a comment. The label
3556 has already been removed. */
3557 if (flag_mri)
3558 {
3559 char *s;
3560 int fields = 0;
3561 int infield = 0;
3562 int inquote = 0;
3563
3564 for (s = str; *s != '\0'; s++)
3565 {
3566 if ((*s == ' ' || *s == '\t') && ! inquote)
3567 {
3568 if (infield)
3569 {
3570 ++fields;
3571 if (fields >= 2)
3572 {
3573 *s = '\0';
3574 break;
3575 }
3576 infield = 0;
3577 }
3578 }
3579 else
3580 {
3581 if (! infield)
3582 infield = 1;
3583 if (*s == '\'')
3584 inquote = ! inquote;
3585 }
3586 }
3587 }
3588
3589 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3590 m68k_ip (str);
3591 er = the_ins.error;
3592 if (!er)
3593 {
3594 for (n = 0; n < the_ins.numargs; n++)
3595 if (the_ins.operands[n].error)
3596 {
3597 er = the_ins.operands[n].error;
3598 break;
3599 }
3600 }
3601 if (er)
3602 {
3603 as_bad (_("%s -- statement `%s' ignored"), er, str);
3604 return;
3605 }
3606
3607 /* If there is a current label, record that it marks an instruction. */
3608 if (current_label != NULL)
3609 {
3610 current_label->text = 1;
3611 current_label = NULL;
3612 }
3613
f27a3839
AS		 3614#ifdef OBJ_ELF
3615 /* Tie dwarf2 debug info to the address at the start of the insn. */
3616 dwarf2_emit_insn (0);
3617#endif
3618
252b5132
RH		 3619 if (the_ins.nfrag == 0)
3620 {
3621 /* No frag hacking involved; just put it out */
3622 toP = frag_more (2 * the_ins.numo);
3623 fromP = &the_ins.opcode[0];
3624 for (m = the_ins.numo; m; --m)
3625 {
3626 md_number_to_chars (toP, (long) (*fromP), 2);
3627 toP += 2;
3628 fromP++;
3629 }
3630 /* put out symbol-dependent info */
3631 for (m = 0; m < the_ins.nrel; m++)
3632 {
3633 switch (the_ins.reloc[m].wid)
3634 {
3635 case 'B':
3636 n = 1;
3637 break;
3638 case 'b':
3639 n = 1;
3640 break;
3641 case '3':
3642 n = 1;
3643 break;
3644 case 'w':
3645 case 'W':
3646 n = 2;
3647 break;
3648 case 'l':
3649 n = 4;
3650 break;
3651 default:
3652 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3653 the_ins.reloc[m].wid);
3654 }
3655
3656 fixP = fix_new_exp (frag_now,
3657 ((toP - frag_now->fr_literal)
3658 - the_ins.numo * 2 + the_ins.reloc[m].n),
3659 n,
3660 &the_ins.reloc[m].exp,
3661 the_ins.reloc[m].pcrel,
3662 get_reloc_code (n, the_ins.reloc[m].pcrel,
3663 the_ins.reloc[m].pic_reloc));
3664 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3665 if (the_ins.reloc[m].wid == 'B')
3666 fixP->fx_signed = 1;
3667 }
3668 return;
3669 }
3670
3671 /* There's some frag hacking */
fbe572f9
AM		 3672 {
3673 /* Calculate the max frag size. */
3674 int wid;
3675
3676 wid = 2 * the_ins.fragb[0].fragoff;
3677 for (n = 1; n < the_ins.nfrag; n++)
3678 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3679 /* frag_var part. */
3680 wid += 10;
3681 /* Make sure the whole insn fits in one chunk, in particular that
3682 the var part is attached, as we access one byte before the
3683 variable frag for byte branches. */
3684 frag_grow (wid);
3685 }
3686
252b5132
RH		 3687 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3688 {
3689 int wid;
3690
3691 if (n == 0)
3692 wid = 2 * the_ins.fragb[n].fragoff;
3693 else
3694 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3695 toP = frag_more (wid);
3696 to_beg_P = toP;
3697 shorts_this_frag = 0;
3698 for (m = wid / 2; m; --m)
3699 {
3700 md_number_to_chars (toP, (long) (*fromP), 2);
3701 toP += 2;
3702 fromP++;
3703 shorts_this_frag++;
3704 }
3705 for (m = 0; m < the_ins.nrel; m++)
3706 {
3707 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3708 {
3709 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3710 break;
3711 }
3712 wid = the_ins.reloc[m].wid;
3713 if (wid == 0)
3714 continue;
3715 the_ins.reloc[m].wid = 0;
3716 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3717
3718 fixP = fix_new_exp (frag_now,
3719 ((toP - frag_now->fr_literal)
3720 - the_ins.numo * 2 + the_ins.reloc[m].n),
3721 wid,
3722 &the_ins.reloc[m].exp,
3723 the_ins.reloc[m].pcrel,
3724 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3725 the_ins.reloc[m].pic_reloc));
3726 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3727 }
3728 (void) frag_var (rs_machine_dependent, 10, 0,
3729 (relax_substateT) (the_ins.fragb[n].fragty),
3730 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3731 }
3732 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3733 shorts_this_frag = 0;
3734 if (n)
3735 {
3736 toP = frag_more (n * sizeof (short));
3737 while (n--)
3738 {
3739 md_number_to_chars (toP, (long) (*fromP), 2);
3740 toP += 2;
3741 fromP++;
3742 shorts_this_frag++;
3743 }
3744 }
3745 for (m = 0; m < the_ins.nrel; m++)
3746 {
3747 int wid;
3748
3749 wid = the_ins.reloc[m].wid;
3750 if (wid == 0)
3751 continue;
3752 the_ins.reloc[m].wid = 0;
3753 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3754
3755 fixP = fix_new_exp (frag_now,
3756 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3757 - shorts_this_frag * 2),
3758 wid,
3759 &the_ins.reloc[m].exp,
3760 the_ins.reloc[m].pcrel,
3761 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3762 the_ins.reloc[m].pic_reloc));
3763 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3764 }
3765}
3766
3767void
3768md_begin ()
3769{
3770 /*
3771 * md_begin -- set up hash tables with 68000 instructions.
3772 * similar to what the vax assembler does. ---phr
3773 */
3774 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3775 a copy of it at runtime, adding in the information we want but isn't
3776 there. I think it'd be better to have an awk script hack the table
3777 at compile time. Or even just xstr the table and use it as-is. But
3778 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3779 names. */
3780
94f592af
NC		 3781 const struct m68k_opcode *ins;
3782 struct m68k_incant *hack, *slak;
3783 const char *retval = 0; /* empty string, or error msg text */
3784 int i;
252b5132
RH		 3785
3786 if (flag_mri)
3787 {
3788 flag_reg_prefix_optional = 1;
3789 m68k_abspcadd = 1;
3790 if (! m68k_rel32_from_cmdline)
3791 m68k_rel32 = 0;
3792 }
3793
3794 op_hash = hash_new ();
3795
3796 obstack_begin (&robyn, 4000);
3797 for (i = 0; i < m68k_numopcodes; i++)
3798 {
3799 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3800 do
3801 {
3802 ins = &m68k_opcodes[i];
3803 /* We *could* ignore insns that don't match our arch here
92774660 3804 but just leaving them out of the hash. */
252b5132
RH		 3805 slak->m_operands = ins->args;
3806 slak->m_opnum = strlen (slak->m_operands) / 2;
3807 slak->m_arch = ins->arch;
3808 slak->m_opcode = ins->opcode;
3809 /* This is kludgey */
3810 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3811 if (i + 1 != m68k_numopcodes
3812 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3813 {
3814 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3815 i++;
3816 }
3817 else
3818 slak->m_next = 0;
3819 slak = slak->m_next;
3820 }
3821 while (slak);
3822
3823 retval = hash_insert (op_hash, ins->name, (char *) hack);
3824 if (retval)
3825 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3826 }
3827
3828 for (i = 0; i < m68k_numaliases; i++)
3829 {
3830 const char *name = m68k_opcode_aliases[i].primary;
3831 const char *alias = m68k_opcode_aliases[i].alias;
3832 PTR val = hash_find (op_hash, name);
3833 if (!val)
3834 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3835 retval = hash_insert (op_hash, alias, val);
3836 if (retval)
3837 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3838 }
3839
3840 /* In MRI mode, all unsized branches are variable sized. Normally,
3841 they are word sized. */
3842 if (flag_mri)
3843 {
3844 static struct m68k_opcode_alias mri_aliases[] =
3845 {
3846 { "bhi", "jhi", },
3847 { "bls", "jls", },
3848 { "bcc", "jcc", },
3849 { "bcs", "jcs", },
3850 { "bne", "jne", },
3851 { "beq", "jeq", },
3852 { "bvc", "jvc", },
3853 { "bvs", "jvs", },
3854 { "bpl", "jpl", },
3855 { "bmi", "jmi", },
3856 { "bge", "jge", },
3857 { "blt", "jlt", },
3858 { "bgt", "jgt", },
3859 { "ble", "jle", },
3860 { "bra", "jra", },
3861 { "bsr", "jbsr", },
3862 };
3863
8fce3f5e
AM		 3864 for (i = 0;
3865 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3866 i++)
252b5132
RH		 3867 {
3868 const char *name = mri_aliases[i].primary;
3869 const char *alias = mri_aliases[i].alias;
3870 PTR val = hash_find (op_hash, name);
3871 if (!val)
3872 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3873 retval = hash_jam (op_hash, alias, val);
3874 if (retval)
3875 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3876 }
3877 }
3878
8fce3f5e 3879 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3880 {
3881 notend_table[i] = 0;
3882 alt_notend_table[i] = 0;
3883 }
3884 notend_table[','] = 1;
3885 notend_table['{'] = 1;
3886 notend_table['}'] = 1;
3887 alt_notend_table['a'] = 1;
3888 alt_notend_table['A'] = 1;
3889 alt_notend_table['d'] = 1;
3890 alt_notend_table['D'] = 1;
3891 alt_notend_table['#'] = 1;
3892 alt_notend_table['&'] = 1;
3893 alt_notend_table['f'] = 1;
3894 alt_notend_table['F'] = 1;
3895#ifdef REGISTER_PREFIX
3896 alt_notend_table[REGISTER_PREFIX] = 1;
3897#endif
3898
3899 /* We need to put '(' in alt_notend_table to handle
3900 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3901 */
3902 alt_notend_table['('] = 1;
3903
3904 /* We need to put '@' in alt_notend_table to handle
3905 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3906 */
3907 alt_notend_table['@'] = 1;
3908
3909 /* We need to put digits in alt_notend_table to handle
3910 bfextu %d0{24:1},%d0
3911 */
3912 alt_notend_table['0'] = 1;
3913 alt_notend_table['1'] = 1;
3914 alt_notend_table['2'] = 1;
3915 alt_notend_table['3'] = 1;
3916 alt_notend_table['4'] = 1;
3917 alt_notend_table['5'] = 1;
3918 alt_notend_table['6'] = 1;
3919 alt_notend_table['7'] = 1;
3920 alt_notend_table['8'] = 1;
3921 alt_notend_table['9'] = 1;
3922
3923#ifndef MIT_SYNTAX_ONLY
3924 /* Insert pseudo ops, these have to go into the opcode table since
3925 gas expects pseudo ops to start with a dot */
3926 {
3927 int n = 0;
3928 while (mote_pseudo_table[n].poc_name)
3929 {
3930 hack = (struct m68k_incant *)
3931 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3932 hash_insert (op_hash,
3933 mote_pseudo_table[n].poc_name, (char *) hack);
3934 hack->m_operands = 0;
3935 hack->m_opnum = n;
3936 n++;
3937 }
3938 }
3939#endif
3940
3941 init_regtable ();
3942
3943#ifdef OBJ_ELF
3944 record_alignment (text_section, 2);
3945 record_alignment (data_section, 2);
3946 record_alignment (bss_section, 2);
3947#endif
3948}
3949
3950static void
3951select_control_regs ()
3952{
3953 /* Note which set of "movec" control registers is available. */
3954 switch (cpu_of_arch (current_architecture))
3955 {
3956 case m68000:
3957 control_regs = m68000_control_regs;
3958 break;
3959 case m68010:
3960 control_regs = m68010_control_regs;
3961 break;
3962 case m68020:
3963 case m68030:
3964 control_regs = m68020_control_regs;
3965 break;
3966 case m68040:
3967 control_regs = m68040_control_regs;
3968 break;
3969 case m68060:
3970 control_regs = m68060_control_regs;
3971 break;
3972 case cpu32:
3973 control_regs = cpu32_control_regs;
3974 break;
3975 case mcf5200:
6da466c7
ILT		 3976 case mcf5206e:
3977 case mcf5307:
dc84e067 3978 case mcf5407:
6da466c7 3979 control_regs = mcf_control_regs;
252b5132
RH		 3980 break;
3981 default:
3982 abort ();
3983 }
3984}
3985
3986void
3987m68k_init_after_args ()
3988{
3989 if (cpu_of_arch (current_architecture) == 0)
3990 {
3991 int i;
3992 const char *default_cpu = TARGET_CPU;
3993
3994 if (*default_cpu == 'm')
3995 default_cpu++;
3996 for (i = 0; i < n_archs; i++)
3997 if (strcasecmp (default_cpu, archs[i].name) == 0)
3998 break;
3999 if (i == n_archs)
4000 {
4001 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4002 current_architecture |= m68020;
4003 }
4004 else
4005 current_architecture |= archs[i].arch;
4006 }
4007 /* Permit m68881 specification with all cpus; those that can't work
4008 with a coprocessor could be doing emulation. */
4009 if (current_architecture & m68851)
4010 {
4011 if (current_architecture & m68040)
4012 {
4013 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4014 }
4015 }
4016 /* What other incompatibilities could we check for? */
4017
4018 /* Toss in some default assumptions about coprocessors. */
4019 if (!no_68881
4020 && (cpu_of_arch (current_architecture)
4021 /* Can CPU32 have a 68881 coprocessor?? */
4022 & (m68020 | m68030 | cpu32)))
4023 {
4024 current_architecture |= m68881;
4025 }
4026 if (!no_68851
4027 && (cpu_of_arch (current_architecture) & m68020up) != 0
4028 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4029 {
4030 current_architecture |= m68851;
4031 }
4032 if (no_68881 && (current_architecture & m68881))
4033 as_bad (_("options for 68881 and no-68881 both given"));
4034 if (no_68851 && (current_architecture & m68851))
4035 as_bad (_("options for 68851 and no-68851 both given"));
4036
4037#ifdef OBJ_AOUT
4038 /* Work out the magic number. This isn't very general. */
4039 if (current_architecture & m68000)
4040 m68k_aout_machtype = 0;
4041 else if (current_architecture & m68010)
4042 m68k_aout_machtype = 1;
4043 else if (current_architecture & m68020)
4044 m68k_aout_machtype = 2;
4045 else
4046 m68k_aout_machtype = 2;
4047#endif
4048
4049 /* Note which set of "movec" control registers is available. */
4050 select_control_regs ();
4051
4052 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4053 || arch_coldfire_p (current_architecture))
252b5132
RH		 4054 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4055}
4056\f
4057/* This is called when a label is defined. */
4058
4059void
4060m68k_frob_label (sym)
4061 symbolS *sym;
4062{
4063 struct label_line *n;
4064
4065 n = (struct label_line *) xmalloc (sizeof *n);
4066 n->next = labels;
4067 n->label = sym;
4068 as_where (&n->file, &n->line);
4069 n->text = 0;
4070 labels = n;
4071 current_label = n;
4072}
4073
4074/* This is called when a value that is not an instruction is emitted. */
4075
4076void
4077m68k_flush_pending_output ()
4078{
4079 current_label = NULL;
4080}
4081
4082/* This is called at the end of the assembly, when the final value of
4083 the label is known. We warn if this is a text symbol aligned at an
4084 odd location. */
4085
4086void
4087m68k_frob_symbol (sym)
4088 symbolS *sym;
4089{
4090 if (S_GET_SEGMENT (sym) == reg_section
4091 && (int) S_GET_VALUE (sym) < 0)
4092 {
4093 S_SET_SEGMENT (sym, absolute_section);
4094 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4095 }
4096 else if ((S_GET_VALUE (sym) & 1) != 0)
4097 {
4098 struct label_line *l;
4099
4100 for (l = labels; l != NULL; l = l->next)
4101 {
4102 if (l->label == sym)
4103 {
4104 if (l->text)
4105 as_warn_where (l->file, l->line,
4106 _("text label `%s' aligned to odd boundary"),
4107 S_GET_NAME (sym));
4108 break;
4109 }
4110 }
4111 }
4112}
4113\f
4114/* This is called if we go in or out of MRI mode because of the .mri
4115 pseudo-op. */
4116
4117void
4118m68k_mri_mode_change (on)
4119 int on;
4120{
4121 if (on)
4122 {
4123 if (! flag_reg_prefix_optional)
4124 {
4125 flag_reg_prefix_optional = 1;
4126#ifdef REGISTER_PREFIX
4127 init_regtable ();
4128#endif
4129 }
4130 m68k_abspcadd = 1;
4131 if (! m68k_rel32_from_cmdline)
4132 m68k_rel32 = 0;
4133 }
4134 else
4135 {
4136 if (! reg_prefix_optional_seen)
4137 {
4138#ifdef REGISTER_PREFIX_OPTIONAL
4139 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4140#else
4141 flag_reg_prefix_optional = 0;
4142#endif
4143#ifdef REGISTER_PREFIX
4144 init_regtable ();
4145#endif
4146 }
4147 m68k_abspcadd = 0;
4148 if (! m68k_rel32_from_cmdline)
4149 m68k_rel32 = 1;
4150 }
4151}
4152
4153/* Equal to MAX_PRECISION in atof-ieee.c */
4154#define MAX_LITTLENUMS 6
4155
4156/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4157 of type TYPE, and store the appropriate bytes in *LITP. The number
4158 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4159 returned, or NULL on OK. */
4160
4161char *
4162md_atof (type, litP, sizeP)
4163 char type;
4164 char *litP;
4165 int *sizeP;
4166{
4167 int prec;
4168 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4169 LITTLENUM_TYPE *wordP;
4170 char *t;
4171
4172 switch (type)
4173 {
4174 case 'f':
4175 case 'F':
4176 case 's':
4177 case 'S':
4178 prec = 2;
4179 break;
4180
4181 case 'd':
4182 case 'D':
4183 case 'r':
4184 case 'R':
4185 prec = 4;
4186 break;
4187
4188 case 'x':
4189 case 'X':
4190 prec = 6;
4191 break;
4192
4193 case 'p':
4194 case 'P':
4195 prec = 6;
4196 break;
4197
4198 default:
4199 *sizeP = 0;
4200 return _("Bad call to MD_ATOF()");
4201 }
4202 t = atof_ieee (input_line_pointer, type, words);
4203 if (t)
4204 input_line_pointer = t;
4205
4206 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4207 for (wordP = words; prec--;)
4208 {
4209 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4210 litP += sizeof (LITTLENUM_TYPE);
4211 }
4212 return 0;
4213}
4214
4215void
4216md_number_to_chars (buf, val, n)
4217 char *buf;
4218 valueT val;
4219 int n;
4220{
4221 number_to_chars_bigendian (buf, val, n);
4222}
4223
94f592af
NC		 4224void
4225md_apply_fix3 (fixP, valP, seg)
252b5132 4226 fixS *fixP;
bbe8ef22 4227 valueT *valP;
94f592af 4228 segT seg ATTRIBUTE_UNUSED;
252b5132 4229{
bbe8ef22 4230 offsetT val = *valP;
252b5132
RH		 4231 addressT upper_limit;
4232 offsetT lower_limit;
4233
4234 /* This is unnecessary but it convinces the native rs6000 compiler
4235 to generate the code we want. */
4236 char *buf = fixP->fx_frag->fr_literal;
4237 buf += fixP->fx_where;
4238 /* end ibm compiler workaround */
4239
c801568a 4240 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132 4241
94f592af
NC		 4242 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4243 fixP->fx_done = 1;
4244
252b5132
RH		 4245#ifdef OBJ_ELF
4246 if (fixP->fx_addsy)
4247 {
4248 memset (buf, 0, fixP->fx_size);
4249 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4250
4251 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4252 && !S_IS_DEFINED (fixP->fx_addsy)
4253 && !S_IS_WEAK (fixP->fx_addsy))
4254 S_SET_WEAK (fixP->fx_addsy);
4255 return;
4256 }
4257#endif
4258
4259#ifdef BFD_ASSEMBLER
4260 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4261 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4262 return;
4263#endif
4264
4265 switch (fixP->fx_size)
4266 {
94f592af
NC		 4267 /* The cast to offsetT below are necessary to make code
4268 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4269 case 1:
4270 *buf++ = val;
4271 upper_limit = 0x7f;
4272 lower_limit = - (offsetT) 0x80;
4273 break;
4274 case 2:
4275 *buf++ = (val >> 8);
4276 *buf++ = val;
4277 upper_limit = 0x7fff;
4278 lower_limit = - (offsetT) 0x8000;
4279 break;
4280 case 4:
4281 *buf++ = (val >> 24);
4282 *buf++ = (val >> 16);
4283 *buf++ = (val >> 8);
4284 *buf++ = val;
4285 upper_limit = 0x7fffffff;
4286 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4287 break;
4288 default:
4289 BAD_CASE (fixP->fx_size);
4290 }
4291
4292 /* Fix up a negative reloc. */
4293 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4294 {
4295 fixP->fx_addsy = fixP->fx_subsy;
4296 fixP->fx_subsy = NULL;
4297 fixP->fx_tcbit = 1;
4298 }
4299
4300 /* For non-pc-relative values, it's conceivable we might get something
4301 like "0xff" for a byte field. So extend the upper part of the range
4302 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4303 so that we can do any range checking at all. */
4304 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4305 upper_limit = upper_limit * 2 + 1;
4306
4307 if ((addressT) val > upper_limit
4308 && (val > 0 || val < lower_limit))
4309 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4310
4311 /* A one byte PC-relative reloc means a short branch. We can't use
4312 a short branch with a value of 0 or -1, because those indicate
4313 different opcodes (branches with longer offsets). fixup_segment
4314 in write.c may have clobbered fx_pcrel, so we need to examine the
4315 reloc type. */
4316 if ((fixP->fx_pcrel
4317#ifdef BFD_ASSEMBLER
4318 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4319#endif
4320 )
4321 && fixP->fx_size == 1
4322 && (fixP->fx_addsy == NULL
4323 || S_IS_DEFINED (fixP->fx_addsy))
4324 && (val == 0 || val == -1))
4325 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4326}
4327
252b5132
RH		 4328/* *fragP has been relaxed to its final size, and now needs to have
4329 the bytes inside it modified to conform to the new size There is UGLY
4330 MAGIC here. ..
4331 */
4332static void
4333md_convert_frag_1 (fragP)
4334 register fragS *fragP;
4335{
4336 long disp;
252b5132
RH		 4337 fixS *fixP;
4338
4339 /* Address in object code of the displacement. */
4340 register int object_address = fragP->fr_fix + fragP->fr_address;
4341
4342 /* Address in gas core of the place to store the displacement. */
4343 /* This convinces the native rs6000 compiler to generate the code we
92774660 4344 want. */
252b5132
RH		 4345 register char *buffer_address = fragP->fr_literal;
4346 buffer_address += fragP->fr_fix;
4347 /* end ibm compiler workaround */
4348
4349 /* The displacement of the address, from current location. */
4350 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4351 disp = (disp + fragP->fr_offset) - object_address;
4352
252b5132
RH		 4353 switch (fragP->fr_subtype)
4354 {
151337e8
NC		 4355 case TAB (BRANCHBWL, BYTE):
4356 case TAB (BRABSJUNC, BYTE):
4357 case TAB (BRABSJCOND, BYTE):
4358 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4359 know (issbyte (disp));
4360 if (disp == 0)
b091f402
AM		 4361 as_bad_where (fragP->fr_file, fragP->fr_line,
4362 _("short branch with zero offset: use :w"));
151337e8 4363 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4364 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4365 fixP->fx_pcrel_adjust = -1;
252b5132 4366 break;
151337e8
NC		 4367 case TAB (BRANCHBWL, SHORT):
4368 case TAB (BRABSJUNC, SHORT):
4369 case TAB (BRABSJCOND, SHORT):
4370 case TAB (BRANCHBW, SHORT):
252b5132 4371 fragP->fr_opcode[1] = 0x00;
151337e8 4372 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4373 1, RELAX_RELOC_PC16);
151337e8
NC		 4374 fragP->fr_fix += 2;
4375 break;
4376 case TAB (BRANCHBWL, LONG):
4377 fragP->fr_opcode[1] = (char) 0xFF;
4378 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4379 1, RELAX_RELOC_PC32);
151337e8 4380 fragP->fr_fix += 4;
252b5132 4381 break;
151337e8
NC		 4382 case TAB (BRABSJUNC, LONG):
4383 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4384 {
151337e8
NC		 4385 fragP->fr_opcode[0] = 0x4E;
4386 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4387 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4388 0, RELAX_RELOC_ABS32);
151337e8
NC		 4389 fragP->fr_fix += 4;
4390 }
4391 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4392 {
4393 fragP->fr_opcode[0] = 0x4E;
4394 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4395 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4396 0, RELAX_RELOC_ABS32);
151337e8 4397 fragP->fr_fix += 4;
252b5132
RH		 4398 }
4399 else
4400 {
151337e8
NC		 4401 /* This cannot happen, because jbsr and jbra are the only two
4402 unconditional branches. */
4403 abort ();
252b5132
RH		 4404 }
4405 break;
151337e8
NC		 4406 case TAB (BRABSJCOND, LONG):
4407 /* Only Bcc 68000 instructions can come here. */
4408 /* Change bcc into b!cc/jmp absl long. */
92774660 4409
252b5132
RH		 4410 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4411 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4412
4413 /* JF: these used to be fr_opcode[2,3], but they may be in a
4414 different frag, in which case refering to them is a no-no.
92774660 4415 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4416 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4417 *buffer_address++ = (char) 0xf9;
4418 fragP->fr_fix += 2; /* account for jmp instruction */
4419 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4420 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4421 fragP->fr_fix += 4;
4422 break;
4423 case TAB (FBRANCH, SHORT):
4424 know ((fragP->fr_opcode[1] & 0x40) == 0);
4425 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4426 1, RELAX_RELOC_PC16);
151337e8
NC		 4427 fragP->fr_fix += 2;
4428 break;
4429 case TAB (FBRANCH, LONG):
4430 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4431 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4432 1, RELAX_RELOC_PC32);
252b5132 4433 fragP->fr_fix += 4;
252b5132 4434 break;
151337e8
NC		 4435 case TAB (DBCCLBR, SHORT):
4436 case TAB (DBCCABSJ, SHORT):
4437 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4438 1, RELAX_RELOC_PC16);
151337e8
NC		 4439 fragP->fr_fix += 2;
4440 break;
4441 case TAB (DBCCLBR, LONG):
4442 /* only DBcc instructions can come here */
28e7409f 4443 /* Change dbcc into dbcc/bral. */
28e7409f 4444
252b5132
RH		 4445 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4446 *buffer_address++ = 0x00; /* branch offset = 4 */
4447 *buffer_address++ = 0x04;
4448 *buffer_address++ = 0x60; /* put in bra pc+6 */
4449 *buffer_address++ = 0x06;
151337e8
NC		 4450 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4451 *buffer_address++ = (char) 0xff;
252b5132
RH		 4452
4453 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8 4454 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4455 RELAX_RELOC_PC32);
252b5132 4456 fragP->fr_fix += 4;
252b5132 4457 break;
151337e8
NC		 4458 case TAB (DBCCABSJ, LONG):
4459 /* only DBcc instructions can come here */
4460 /* Change dbcc into dbcc/jmp. */
4461
4462 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4463 *buffer_address++ = 0x00; /* branch offset = 4 */
4464 *buffer_address++ = 0x04;
4465 *buffer_address++ = 0x60; /* put in bra pc+6 */
4466 *buffer_address++ = 0x06;
4467 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4468 *buffer_address++ = (char) 0xf9;
4469
4470 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4471 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4472 RELAX_RELOC_ABS32);
252b5132 4473 fragP->fr_fix += 4;
252b5132 4474 break;
151337e8 4475 case TAB (PCREL1632, SHORT):
252b5132
RH		 4476 fragP->fr_opcode[1] &= ~0x3F;
4477 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4478 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4479 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4480 fragP->fr_fix += 2;
252b5132 4481 break;
151337e8 4482 case TAB (PCREL1632, LONG):
252b5132
RH		 4483 /* Already set to mode 7.3; this indicates: PC indirect with
4484 suppressed index, 32-bit displacement. */
4485 *buffer_address++ = 0x01;
4486 *buffer_address++ = 0x70;
4487 fragP->fr_fix += 2;
151337e8 4488 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4489 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4490 fixP->fx_pcrel_adjust = 2;
4491 fragP->fr_fix += 4;
252b5132 4492 break;
252b5132 4493 case TAB (PCINDEX, BYTE):
252b5132
RH		 4494 assert (fragP->fr_fix >= 2);
4495 buffer_address[-2] &= ~1;
151337e8 4496 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4497 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4498 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4499 break;
4500 case TAB (PCINDEX, SHORT):
252b5132
RH		 4501 assert (fragP->fr_fix >= 2);
4502 buffer_address[-2] |= 0x1;
4503 buffer_address[-1] = 0x20;
4504 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4505 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4506 fixP->fx_pcrel_adjust = 2;
151337e8 4507 fragP->fr_fix += 2;
252b5132
RH		 4508 break;
4509 case TAB (PCINDEX, LONG):
252b5132
RH		 4510 assert (fragP->fr_fix >= 2);
4511 buffer_address[-2] |= 0x1;
4512 buffer_address[-1] = 0x30;
151337e8 4513 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4514 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4515 fixP->fx_pcrel_adjust = 2;
4516 fragP->fr_fix += 4;
4517 break;
4518 case TAB (ABSTOPCREL, SHORT):
4519 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4520 1, RELAX_RELOC_PC16);
151337e8
NC		 4521 fragP->fr_fix += 2;
4522 break;
4523 case TAB (ABSTOPCREL, LONG):
4524 /* The thing to do here is force it to ABSOLUTE LONG, since
4525 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4526 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4527 abort ();
4528 fragP->fr_opcode[1] &= ~0x3F;
4529 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4530 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4531 0, RELAX_RELOC_ABS32);
151337e8 4532 fragP->fr_fix += 4;
252b5132 4533 break;
252b5132
RH		 4534 }
4535}
4536
4537#ifndef BFD_ASSEMBLER
4538
4539void
4540md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4541 object_headers *headers ATTRIBUTE_UNUSED;
4542 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4543 fragS *fragP;
4544{
4545 md_convert_frag_1 (fragP);
4546}
4547
4548#else
4549
4550void
4551md_convert_frag (abfd, sec, fragP)
36823076
AS		 4552 bfd *abfd ATTRIBUTE_UNUSED;
4553 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4554 fragS *fragP;
4555{
4556 md_convert_frag_1 (fragP);
4557}
4558#endif
4559
4560/* Force truly undefined symbols to their maximum size, and generally set up
4561 the frag list to be relaxed
4562 */
4563int
4564md_estimate_size_before_relax (fragP, segment)
4565 register fragS *fragP;
4566 segT segment;
4567{
151337e8 4568 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4569 switch (fragP->fr_subtype)
4570 {
151337e8
NC		 4571 case TAB (BRANCHBWL, SZ_UNDEF):
4572 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4573 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4574 {
151337e8
NC		 4575 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4576 && relaxable_symbol (fragP->fr_symbol))
252b5132 4577 {
151337e8
NC		 4578 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4579 }
4580 else if (flag_short_refs)
4581 {
4582 /* Symbol is undefined and we want short ref. */
4583 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4584 }
4585 else
4586 {
151337e8
NC		 4587 /* Symbol is still undefined. Make it LONG. */
4588 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4589 }
4590 break;
151337e8 4591 }
252b5132 4592
151337e8 4593 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4594 {
151337e8
NC		 4595 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4596 && relaxable_symbol (fragP->fr_symbol))
252b5132 4597 {
151337e8 4598 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4599 }
4600 else
4601 {
151337e8
NC		 4602 /* Symbol is undefined and we don't have long branches. */
4603 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4604 }
4605 break;
151337e8 4606 }
252b5132 4607
151337e8 4608 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4609 case TAB (DBCCLBR, SZ_UNDEF):
4610 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4611 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4612 {
8ec6253e
NC		 4613 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4614 && relaxable_symbol (fragP->fr_symbol))
151337e8 4615 || flag_short_refs)
252b5132 4616 {
151337e8 4617 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4618 }
4619 else
4620 {
151337e8 4621 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4622 }
4623 break;
151337e8 4624 }
81d4177b 4625
252b5132
RH		 4626 case TAB (PCINDEX, SZ_UNDEF):
4627 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4628 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4629 {
4630 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4631 }
4632 else
4633 {
4634 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4635 }
4636 break;
4637
151337e8
NC		 4638 case TAB (ABSTOPCREL, SZ_UNDEF):
4639 {
4640 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4641 && relaxable_symbol (fragP->fr_symbol)))
4642 {
4643 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4644 }
4645 else
4646 {
4647 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4648 }
4649 break;
4650 }
4651
252b5132
RH		 4652 default:
4653 break;
4654 }
4655
151337e8 4656 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4657 switch (fragP->fr_subtype)
4658 {
151337e8
NC		 4659 case TAB (BRANCHBWL, BYTE):
4660 case TAB (BRABSJUNC, BYTE):
4661 case TAB (BRABSJCOND, BYTE):
4662 case TAB (BRANCHBW, BYTE):
252b5132 4663 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4664 case we force word mode. If the symbol is at the start of a
4665 frag, and it is the next frag with any data in it (usually
4666 this is just the next frag, but assembler listings may
4667 introduce empty frags), we must use word mode. */
4668 if (fragP->fr_symbol)
252b5132 4669 {
ac62c346 4670 fragS *sym_frag;
252b5132 4671
ac62c346
AM		 4672 sym_frag = symbol_get_frag (fragP->fr_symbol);
4673 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4674 {
ac62c346
AM		 4675 fragS *l;
4676
4677 for (l = fragP->fr_next; l != sym_frag; l = l->fr_next)
4678 if (l->fr_fix != 0)
4679 break;
4680 if (l == sym_frag)
4681 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4682 }
4683 }
4684 break;
4685 default:
4686 break;
4687 }
ac62c346 4688 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4689}
4690
4691#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4692/* the bit-field entries in the relocation_info struct plays hell
4693 with the byte-order problems of cross-assembly. So as a hack,
4694 I added this mach. dependent ri twiddler. Ugly, but it gets
4695 you there. -KWK */
4696/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4697 are symbolnum, most sig. byte first. Last byte is broken up with
4698 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4699 nibble as nuthin. (on Sun 3 at least) */
4700/* Translate the internal relocation information into target-specific
92774660 4701 format. */
252b5132
RH		 4702#ifdef comment
4703void
4704md_ri_to_chars (the_bytes, ri)
4705 char *the_bytes;
4706 struct reloc_info_generic *ri;
4707{
4708 /* this is easy */
4709 md_number_to_chars (the_bytes, ri->r_address, 4);
4710 /* now the fun stuff */
4711 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4712 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4713 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4714 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4715 ((ri->r_extern << 4) & 0x10));
4716}
4717
4718#endif /* comment */
4719
4720#ifndef BFD_ASSEMBLER
4721void
4722tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4723 char *where;
4724 fixS *fixP;
4725 relax_addressT segment_address_in_file;
4726{
4727 /*
4728 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4729 * Out: GNU LD relocation length code: 0, 1, or 2.
4730 */
4731
4732 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4733 long r_symbolnum;
4734
4735 know (fixP->fx_addsy != NULL);
4736
4737 md_number_to_chars (where,
4738 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4739 4);
4740
4741 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4742 ? S_GET_TYPE (fixP->fx_addsy)
4743 : fixP->fx_addsy->sy_number);
4744
4745 where[4] = (r_symbolnum >> 16) & 0x0ff;
4746 where[5] = (r_symbolnum >> 8) & 0x0ff;
4747 where[6] = r_symbolnum & 0x0ff;
4748 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4749 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4750}
4751#endif
4752
4753#endif /* OBJ_AOUT or OBJ_BOUT */
4754
4755#ifndef WORKING_DOT_WORD
4756CONST int md_short_jump_size = 4;
4757CONST int md_long_jump_size = 6;
4758
4759void
4760md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4761 char *ptr;
4762 addressT from_addr, to_addr;
36823076
AS		 4763 fragS *frag ATTRIBUTE_UNUSED;
4764 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4765{
4766 valueT offset;
4767
4768 offset = to_addr - (from_addr + 2);
4769
4770 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4771 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4772}
4773
4774void
4775md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4776 char *ptr;
4777 addressT from_addr, to_addr;
4778 fragS *frag;
4779 symbolS *to_symbol;
4780{
4781 valueT offset;
4782
4783 if (!HAVE_LONG_BRANCH(current_architecture))
4784 {
4785 offset = to_addr - S_GET_VALUE (to_symbol);
4786 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4787 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4788 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4789 0, NO_RELOC);
4790 }
4791 else
4792 {
4793 offset = to_addr - (from_addr + 2);
4794 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4795 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4796 }
4797}
4798
4799#endif
4800
4801/* Different values of OK tell what its OK to return. Things that
4802 aren't OK are an error (what a shock, no?)
4803
4804 0: Everything is OK
4805 10: Absolute 1:8 only
4806 20: Absolute 0:7 only
4807 30: absolute 0:15 only
4808 40: Absolute 0:31 only
4809 50: absolute 0:127 only
4810 55: absolute -64:63 only
4811 60: absolute -128:127 only
4812 70: absolute 0:4095 only
4813 80: No bignums
4814
4815 */
4816
4817static int
4818get_num (exp, ok)
4819 struct m68k_exp *exp;
4820 int ok;
4821{
4822 if (exp->exp.X_op == O_absent)
4823 {
4824 /* Do the same thing the VAX asm does */
4825 op (exp) = O_constant;
4826 adds (exp) = 0;
4827 subs (exp) = 0;
4828 offs (exp) = 0;
4829 if (ok == 10)
4830 {
4831 as_warn (_("expression out of range: defaulting to 1"));
4832 offs (exp) = 1;
4833 }
4834 }
4835 else if (exp->exp.X_op == O_constant)
4836 {
4837 switch (ok)
4838 {
4839 case 10:
4840 if (offs (exp) < 1 || offs (exp) > 8)
4841 {
4842 as_warn (_("expression out of range: defaulting to 1"));
4843 offs (exp) = 1;
4844 }
4845 break;
4846 case 20:
4847 if (offs (exp) < 0 || offs (exp) > 7)
4848 goto outrange;
4849 break;
4850 case 30:
4851 if (offs (exp) < 0 || offs (exp) > 15)
4852 goto outrange;
4853 break;
4854 case 40:
4855 if (offs (exp) < 0 || offs (exp) > 32)
4856 goto outrange;
4857 break;
4858 case 50:
4859 if (offs (exp) < 0 || offs (exp) > 127)
4860 goto outrange;
4861 break;
4862 case 55:
4863 if (offs (exp) < -64 || offs (exp) > 63)
4864 goto outrange;
4865 break;
4866 case 60:
4867 if (offs (exp) < -128 || offs (exp) > 127)
4868 goto outrange;
4869 break;
4870 case 70:
4871 if (offs (exp) < 0 || offs (exp) > 4095)
4872 {
4873 outrange:
4874 as_warn (_("expression out of range: defaulting to 0"));
4875 offs (exp) = 0;
4876 }
4877 break;
4878 default:
4879 break;
4880 }
4881 }
4882 else if (exp->exp.X_op == O_big)
4883 {
4884 if (offs (exp) <= 0 /* flonum */
4885 && (ok == 80 /* no bignums */
4886 || (ok > 10 /* small-int ranges including 0 ok */
4887 /* If we have a flonum zero, a zero integer should
4888 do as well (e.g., in moveq). */
4889 && generic_floating_point_number.exponent == 0
4890 && generic_floating_point_number.low[0] == 0)))
4891 {
4892 /* HACK! Turn it into a long */
4893 LITTLENUM_TYPE words[6];
4894
4895 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4896 op (exp) = O_constant;
4897 adds (exp) = 0;
4898 subs (exp) = 0;
4899 offs (exp) = words[1] | (words[0] << 16);
4900 }
4901 else if (ok != 0)
4902 {
4903 op (exp) = O_constant;
4904 adds (exp) = 0;
4905 subs (exp) = 0;
4906 offs (exp) = (ok == 10) ? 1 : 0;
4907 as_warn (_("Can't deal with expression; defaulting to %ld"),
4908 offs (exp));
4909 }
4910 }
4911 else
4912 {
4913 if (ok >= 10 && ok <= 70)
4914 {
4915 op (exp) = O_constant;
4916 adds (exp) = 0;
4917 subs (exp) = 0;
4918 offs (exp) = (ok == 10) ? 1 : 0;
4919 as_warn (_("Can't deal with expression; defaulting to %ld"),
4920 offs (exp));
4921 }
4922 }
4923
4924 if (exp->size != SIZE_UNSPEC)
4925 {
4926 switch (exp->size)
4927 {
4928 case SIZE_UNSPEC:
4929 case SIZE_LONG:
4930 break;
4931 case SIZE_BYTE:
4932 if (!isbyte (offs (exp)))
4933 as_warn (_("expression doesn't fit in BYTE"));
4934 break;
4935 case SIZE_WORD:
4936 if (!isword (offs (exp)))
4937 as_warn (_("expression doesn't fit in WORD"));
4938 break;
4939 }
4940 }
4941
4942 return offs (exp);
4943}
4944
4945/* These are the back-ends for the various machine dependent pseudo-ops. */
4946
4947static void
4948s_data1 (ignore)
36823076 4949 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4950{
4951 subseg_set (data_section, 1);
4952 demand_empty_rest_of_line ();
4953}
4954
4955static void
4956s_data2 (ignore)
36823076 4957 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4958{
4959 subseg_set (data_section, 2);
4960 demand_empty_rest_of_line ();
4961}
4962
4963static void
4964s_bss (ignore)
36823076 4965 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4966{
4967 /* We don't support putting frags in the BSS segment, we fake it
4968 by marking in_bss, then looking at s_skip for clues. */
4969
4970 subseg_set (bss_section, 0);
4971 demand_empty_rest_of_line ();
4972}
4973
4974static void
4975s_even (ignore)
36823076 4976 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4977{
4978 register int temp;
4979 register long temp_fill;
4980
4981 temp = 1; /* JF should be 2? */
4982 temp_fill = get_absolute_expression ();
92774660 4983 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 4984 frag_align (temp, (int) temp_fill, 0);
4985 demand_empty_rest_of_line ();
4986 record_alignment (now_seg, temp);
4987}
4988
4989static void
4990s_proc (ignore)
36823076 4991 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4992{
4993 demand_empty_rest_of_line ();
4994}
4995\f
4996/* Pseudo-ops handled for MRI compatibility. */
4997
4998/* This function returns non-zero if the argument is a conditional
4999 pseudo-op. This is called when checking whether a pending
5000 alignment is needed. */
5001
5002int
5003m68k_conditional_pseudoop (pop)
5004 pseudo_typeS *pop;
5005{
5006 return (pop->poc_handler == s_mri_if
5007 || pop->poc_handler == s_mri_else);
5008}
5009
5010/* Handle an MRI style chip specification. */
5011
5012static void
5013mri_chip ()
5014{
5015 char *s;
5016 char c;
5017 int i;
5018
5019 s = input_line_pointer;
5020 /* We can't use get_symbol_end since the processor names are not proper
5021 symbols. */
5022 while (is_part_of_name (c = *input_line_pointer++))
5023 ;
5024 *--input_line_pointer = 0;
5025 for (i = 0; i < n_archs; i++)
5026 if (strcasecmp (s, archs[i].name) == 0)
5027 break;
5028 if (i >= n_archs)
5029 {
5030 as_bad (_("%s: unrecognized processor name"), s);
5031 *input_line_pointer = c;
5032 ignore_rest_of_line ();
5033 return;
5034 }
5035 *input_line_pointer = c;
5036
5037 if (*input_line_pointer == '/')
5038 current_architecture = 0;
5039 else
5040 current_architecture &= m68881 | m68851;
5041 current_architecture |= archs[i].arch;
5042
5043 while (*input_line_pointer == '/')
5044 {
5045 ++input_line_pointer;
5046 s = input_line_pointer;
5047 /* We can't use get_symbol_end since the processor names are not
5048 proper symbols. */
5049 while (is_part_of_name (c = *input_line_pointer++))
5050 ;
5051 *--input_line_pointer = 0;
5052 if (strcmp (s, "68881") == 0)
5053 current_architecture |= m68881;
5054 else if (strcmp (s, "68851") == 0)
5055 current_architecture |= m68851;
5056 *input_line_pointer = c;
5057 }
5058
5059 /* Update info about available control registers. */
5060 select_control_regs ();
5061}
5062
5063/* The MRI CHIP pseudo-op. */
5064
5065static void
5066s_chip (ignore)
36823076 5067 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5068{
5069 char *stop = NULL;
5070 char stopc;
5071
5072 if (flag_mri)
5073 stop = mri_comment_field (&stopc);
5074 mri_chip ();
5075 if (flag_mri)
5076 mri_comment_end (stop, stopc);
5077 demand_empty_rest_of_line ();
5078}
5079
5080/* The MRI FOPT pseudo-op. */
5081
5082static void
5083s_fopt (ignore)
36823076 5084 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5085{
5086 SKIP_WHITESPACE ();
5087
5088 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5089 {
5090 int temp;
5091
5092 input_line_pointer += 3;
5093 temp = get_absolute_expression ();
5094 if (temp < 0 || temp > 7)
5095 as_bad (_("bad coprocessor id"));
5096 else
5097 m68k_float_copnum = COP0 + temp;
5098 }
5099 else
5100 {
5101 as_bad (_("unrecognized fopt option"));
5102 ignore_rest_of_line ();
5103 return;
5104 }
5105
5106 demand_empty_rest_of_line ();
5107}
5108
5109/* The structure used to handle the MRI OPT pseudo-op. */
5110
5111struct opt_action
5112{
5113 /* The name of the option. */
5114 const char *name;
5115
5116 /* If this is not NULL, just call this function. The first argument
5117 is the ARG field of this structure, the second argument is
5118 whether the option was negated. */
5119 void (*pfn) PARAMS ((int arg, int on));
5120
5121 /* If this is not NULL, and the PFN field is NULL, set the variable
5122 this points to. Set it to the ARG field if the option was not
5123 negated, and the NOTARG field otherwise. */
5124 int *pvar;
5125
5126 /* The value to pass to PFN or to assign to *PVAR. */
5127 int arg;
5128
5129 /* The value to assign to *PVAR if the option is negated. If PFN is
5130 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5131 the option may not be negated. */
5132 int notarg;
5133};
5134
5135/* The table used to handle the MRI OPT pseudo-op. */
5136
5137static void skip_to_comma PARAMS ((int, int));
5138static void opt_nest PARAMS ((int, int));
5139static void opt_chip PARAMS ((int, int));
5140static void opt_list PARAMS ((int, int));
5141static void opt_list_symbols PARAMS ((int, int));
5142
5143static const struct opt_action opt_table[] =
5144{
5145 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5146
5147 /* We do relaxing, so there is little use for these options. */
5148 { "b", 0, 0, 0, 0 },
5149 { "brs", 0, 0, 0, 0 },
5150 { "brb", 0, 0, 0, 0 },
5151 { "brl", 0, 0, 0, 0 },
5152 { "brw", 0, 0, 0, 0 },
5153
5154 { "c", 0, 0, 0, 0 },
5155 { "cex", 0, 0, 0, 0 },
5156 { "case", 0, &symbols_case_sensitive, 1, 0 },
5157 { "cl", 0, 0, 0, 0 },
5158 { "cre", 0, 0, 0, 0 },
5159 { "d", 0, &flag_keep_locals, 1, 0 },
5160 { "e", 0, 0, 0, 0 },
5161 { "f", 0, &flag_short_refs, 1, 0 },
5162 { "frs", 0, &flag_short_refs, 1, 0 },
5163 { "frl", 0, &flag_short_refs, 0, 1 },
5164 { "g", 0, 0, 0, 0 },
5165 { "i", 0, 0, 0, 0 },
5166 { "m", 0, 0, 0, 0 },
5167 { "mex", 0, 0, 0, 0 },
5168 { "mc", 0, 0, 0, 0 },
5169 { "md", 0, 0, 0, 0 },
5170 { "nest", opt_nest, 0, 0, 0 },
5171 { "next", skip_to_comma, 0, 0, 0 },
5172 { "o", 0, 0, 0, 0 },
5173 { "old", 0, 0, 0, 0 },
5174 { "op", skip_to_comma, 0, 0, 0 },
5175 { "pco", 0, 0, 0, 0 },
5176 { "p", opt_chip, 0, 0, 0 },
5177 { "pcr", 0, 0, 0, 0 },
5178 { "pcs", 0, 0, 0, 0 },
5179 { "r", 0, 0, 0, 0 },
5180 { "quick", 0, &m68k_quick, 1, 0 },
5181 { "rel32", 0, &m68k_rel32, 1, 0 },
5182 { "s", opt_list, 0, 0, 0 },
5183 { "t", opt_list_symbols, 0, 0, 0 },
5184 { "w", 0, &flag_no_warnings, 0, 1 },
5185 { "x", 0, 0, 0, 0 }
5186};
5187
8fce3f5e 5188#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5189
5190/* The MRI OPT pseudo-op. */
5191
5192static void
5193s_opt (ignore)
36823076 5194 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5195{
5196 do
5197 {
5198 int t;
5199 char *s;
5200 char c;
5201 int i;
5202 const struct opt_action *o;
5203
5204 SKIP_WHITESPACE ();
5205
5206 t = 1;
5207 if (*input_line_pointer == '-')
5208 {
5209 ++input_line_pointer;
5210 t = 0;
5211 }
5212 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5213 {
5214 input_line_pointer += 2;
5215 t = 0;
5216 }
5217
5218 s = input_line_pointer;
5219 c = get_symbol_end ();
5220
5221 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5222 {
5223 if (strcasecmp (s, o->name) == 0)
5224 {
5225 if (o->pfn)
5226 {
5227 /* Restore input_line_pointer now in case the option
5228 takes arguments. */
5229 *input_line_pointer = c;
5230 (*o->pfn) (o->arg, t);
5231 }
5232 else if (o->pvar != NULL)
5233 {
5234 if (! t && o->arg == o->notarg)
5235 as_bad (_("option `%s' may not be negated"), s);
5236 *input_line_pointer = c;
5237 *o->pvar = t ? o->arg : o->notarg;
5238 }
5239 else
5240 *input_line_pointer = c;
5241 break;
5242 }
5243 }
5244 if (i >= OPTCOUNT)
5245 {
5246 as_bad (_("option `%s' not recognized"), s);
5247 *input_line_pointer = c;
5248 }
5249 }
5250 while (*input_line_pointer++ == ',');
5251
5252 /* Move back to terminating character. */
5253 --input_line_pointer;
5254 demand_empty_rest_of_line ();
5255}
5256
5257/* Skip ahead to a comma. This is used for OPT options which we do
5258 not suppor tand which take arguments. */
5259
5260static void
5261skip_to_comma (arg, on)
36823076
AS		 5262 int arg ATTRIBUTE_UNUSED;
5263 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5264{
5265 while (*input_line_pointer != ','
5266 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5267 ++input_line_pointer;
5268}
5269
5270/* Handle the OPT NEST=depth option. */
5271
5272static void
5273opt_nest (arg, on)
36823076
AS		 5274 int arg ATTRIBUTE_UNUSED;
5275 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5276{
5277 if (*input_line_pointer != '=')
5278 {
5279 as_bad (_("bad format of OPT NEST=depth"));
5280 return;
5281 }
5282
5283 ++input_line_pointer;
5284 max_macro_nest = get_absolute_expression ();
5285}
5286
5287/* Handle the OPT P=chip option. */
5288
5289static void
5290opt_chip (arg, on)
36823076
AS		 5291 int arg ATTRIBUTE_UNUSED;
5292 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5293{
5294 if (*input_line_pointer != '=')
5295 {
5296 /* This is just OPT P, which we do not support. */
5297 return;
5298 }
5299
5300 ++input_line_pointer;
5301 mri_chip ();
5302}
5303
5304/* Handle the OPT S option. */
5305
5306static void
5307opt_list (arg, on)
36823076 5308 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5309 int on;
5310{
5311 listing_list (on);
5312}
5313
5314/* Handle the OPT T option. */
5315
5316static void
5317opt_list_symbols (arg, on)
36823076 5318 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5319 int on;
5320{
5321 if (on)
5322 listing |= LISTING_SYMBOLS;
5323 else
5324 listing &=~ LISTING_SYMBOLS;
5325}
5326
5327/* Handle the MRI REG pseudo-op. */
5328
5329static void
5330s_reg (ignore)
36823076 5331 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5332{
5333 char *s;
5334 int c;
5335 struct m68k_op rop;
5336 int mask;
5337 char *stop = NULL;
5338 char stopc;
5339
5340 if (line_label == NULL)
5341 {
5342 as_bad (_("missing label"));
5343 ignore_rest_of_line ();
5344 return;
5345 }
5346
5347 if (flag_mri)
5348 stop = mri_comment_field (&stopc);
5349
5350 SKIP_WHITESPACE ();
5351
5352 s = input_line_pointer;
3882b010 5353 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5354#ifdef REGISTER_PREFIX
5355 || *input_line_pointer == REGISTER_PREFIX
5356#endif
5357 || *input_line_pointer == '/'
5358 || *input_line_pointer == '-')
5359 ++input_line_pointer;
5360 c = *input_line_pointer;
5361 *input_line_pointer = '\0';
5362
5363 if (m68k_ip_op (s, &rop) != 0)
5364 {
5365 if (rop.error == NULL)
5366 as_bad (_("bad register list"));
5367 else
5368 as_bad (_("bad register list: %s"), rop.error);
5369 *input_line_pointer = c;
5370 ignore_rest_of_line ();
5371 return;
5372 }
5373
5374 *input_line_pointer = c;
5375
5376 if (rop.mode == REGLST)
5377 mask = rop.mask;
5378 else if (rop.mode == DREG)
5379 mask = 1 << (rop.reg - DATA0);
5380 else if (rop.mode == AREG)
5381 mask = 1 << (rop.reg - ADDR0 + 8);
5382 else if (rop.mode == FPREG)
5383 mask = 1 << (rop.reg - FP0 + 16);
5384 else if (rop.mode == CONTROL
5385 && rop.reg == FPI)
5386 mask = 1 << 24;
5387 else if (rop.mode == CONTROL
5388 && rop.reg == FPS)
5389 mask = 1 << 25;
5390 else if (rop.mode == CONTROL
5391 && rop.reg == FPC)
5392 mask = 1 << 26;
5393 else
5394 {
5395 as_bad (_("bad register list"));
5396 ignore_rest_of_line ();
5397 return;
5398 }
5399
5400 S_SET_SEGMENT (line_label, reg_section);
5401 S_SET_VALUE (line_label, ~mask);
49309057 5402 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5403
5404 if (flag_mri)
5405 mri_comment_end (stop, stopc);
5406
5407 demand_empty_rest_of_line ();
5408}
5409
5410/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5411
5412struct save_opts
5413{
5414 struct save_opts *next;
5415 int abspcadd;
5416 int symbols_case_sensitive;
5417 int keep_locals;
5418 int short_refs;
5419 int architecture;
5420 int quick;
5421 int rel32;
5422 int listing;
5423 int no_warnings;
5424 /* FIXME: We don't save OPT S. */
5425};
5426
5427/* This variable holds the stack of saved options. */
5428
5429static struct save_opts *save_stack;
5430
5431/* The MRI SAVE pseudo-op. */
5432
5433static void
5434s_save (ignore)
36823076 5435 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5436{
5437 struct save_opts *s;
5438
5439 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5440 s->abspcadd = m68k_abspcadd;
5441 s->symbols_case_sensitive = symbols_case_sensitive;
5442 s->keep_locals = flag_keep_locals;
5443 s->short_refs = flag_short_refs;
5444 s->architecture = current_architecture;
5445 s->quick = m68k_quick;
5446 s->rel32 = m68k_rel32;
5447 s->listing = listing;
5448 s->no_warnings = flag_no_warnings;
5449
5450 s->next = save_stack;
5451 save_stack = s;
5452
5453 demand_empty_rest_of_line ();
5454}
5455
5456/* The MRI RESTORE pseudo-op. */
5457
5458static void
5459s_restore (ignore)
36823076 5460 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5461{
5462 struct save_opts *s;
5463
5464 if (save_stack == NULL)
5465 {
5466 as_bad (_("restore without save"));
5467 ignore_rest_of_line ();
5468 return;
5469 }
5470
5471 s = save_stack;
5472 save_stack = s->next;
5473
5474 m68k_abspcadd = s->abspcadd;
5475 symbols_case_sensitive = s->symbols_case_sensitive;
5476 flag_keep_locals = s->keep_locals;
5477 flag_short_refs = s->short_refs;
5478 current_architecture = s->architecture;
5479 m68k_quick = s->quick;
5480 m68k_rel32 = s->rel32;
5481 listing = s->listing;
5482 flag_no_warnings = s->no_warnings;
5483
5484 free (s);
5485
5486 demand_empty_rest_of_line ();
5487}
5488
5489/* Types of MRI structured control directives. */
5490
5491enum mri_control_type
5492{
5493 mri_for,
5494 mri_if,
5495 mri_repeat,
5496 mri_while
5497};
5498
5499/* This structure is used to stack the MRI structured control
5500 directives. */
5501
5502struct mri_control_info
5503{
5504 /* The directive within which this one is enclosed. */
5505 struct mri_control_info *outer;
5506
5507 /* The type of directive. */
5508 enum mri_control_type type;
5509
5510 /* Whether an ELSE has been in an IF. */
5511 int else_seen;
5512
5513 /* The add or sub statement at the end of a FOR. */
5514 char *incr;
5515
5516 /* The label of the top of a FOR or REPEAT loop. */
5517 char *top;
5518
5519 /* The label to jump to for the next iteration, or the else
5520 expression of a conditional. */
5521 char *next;
5522
5523 /* The label to jump to to break out of the loop, or the label past
5524 the end of a conditional. */
5525 char *bottom;
5526};
5527
5528/* The stack of MRI structured control directives. */
5529
5530static struct mri_control_info *mri_control_stack;
5531
5532/* The current MRI structured control directive index number, used to
5533 generate label names. */
5534
5535static int mri_control_index;
5536
5537/* Some function prototypes. */
5538
5539static void mri_assemble PARAMS ((char *));
5540static char *mri_control_label PARAMS ((void));
5541static struct mri_control_info *push_mri_control
5542 PARAMS ((enum mri_control_type));
5543static void pop_mri_control PARAMS ((void));
5544static int parse_mri_condition PARAMS ((int *));
5545static int parse_mri_control_operand
5546 PARAMS ((int *, char **, char **, char **, char **));
5547static int swap_mri_condition PARAMS ((int));
5548static int reverse_mri_condition PARAMS ((int));
5549static void build_mri_control_operand
5550 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5551 const char *, int));
5552static void parse_mri_control_expression
5553 PARAMS ((char *, int, const char *, const char *, int));
5554
5555/* Assemble an instruction for an MRI structured control directive. */
5556
5557static void
5558mri_assemble (str)
5559 char *str;
5560{
5561 char *s;
5562
5563 /* md_assemble expects the opcode to be in lower case. */
5564 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5565 *s = TOLOWER (*s);
252b5132
RH		 5566
5567 md_assemble (str);
5568}
5569
5570/* Generate a new MRI label structured control directive label name. */
5571
5572static char *
5573mri_control_label ()
5574{
5575 char *n;
5576
5577 n = (char *) xmalloc (20);
5578 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5579 ++mri_control_index;
5580 return n;
5581}
5582
5583/* Create a new MRI structured control directive. */
5584
5585static struct mri_control_info *
5586push_mri_control (type)
5587 enum mri_control_type type;
5588{
5589 struct mri_control_info *n;
5590
5591 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5592
5593 n->type = type;
5594 n->else_seen = 0;
5595 if (type == mri_if || type == mri_while)
5596 n->top = NULL;
5597 else
5598 n->top = mri_control_label ();
5599 n->next = mri_control_label ();
5600 n->bottom = mri_control_label ();
5601
5602 n->outer = mri_control_stack;
5603 mri_control_stack = n;
5604
5605 return n;
5606}
5607
5608/* Pop off the stack of MRI structured control directives. */
5609
5610static void
5611pop_mri_control ()
5612{
5613 struct mri_control_info *n;
5614
5615 n = mri_control_stack;
5616 mri_control_stack = n->outer;
5617 if (n->top != NULL)
5618 free (n->top);
5619 free (n->next);
5620 free (n->bottom);
5621 free (n);
5622}
5623
5624/* Recognize a condition code in an MRI structured control expression. */
5625
5626static int
5627parse_mri_condition (pcc)
5628 int *pcc;
5629{
5630 char c1, c2;
5631
5632 know (*input_line_pointer == '<');
5633
5634 ++input_line_pointer;
5635 c1 = *input_line_pointer++;
5636 c2 = *input_line_pointer++;
5637
5638 if (*input_line_pointer != '>')
5639 {
5640 as_bad (_("syntax error in structured control directive"));
5641 return 0;
5642 }
5643
5644 ++input_line_pointer;
5645 SKIP_WHITESPACE ();
5646
3882b010
L		 5647 c1 = TOLOWER (c1);
5648 c2 = TOLOWER (c2);
252b5132
RH		 5649
5650 *pcc = (c1 << 8) | c2;
5651
5652 return 1;
5653}
5654
5655/* Parse a single operand in an MRI structured control expression. */
5656
5657static int
5658parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5659 int *pcc;
5660 char **leftstart;
5661 char **leftstop;
5662 char **rightstart;
5663 char **rightstop;
5664{
5665 char *s;
5666
5667 SKIP_WHITESPACE ();
5668
5669 *pcc = -1;
5670 *leftstart = NULL;
5671 *leftstop = NULL;
5672 *rightstart = NULL;
5673 *rightstop = NULL;
5674
5675 if (*input_line_pointer == '<')
5676 {
5677 /* It's just a condition code. */
5678 return parse_mri_condition (pcc);
5679 }
5680
5681 /* Look ahead for the condition code. */
5682 for (s = input_line_pointer; *s != '\0'; ++s)
5683 {
5684 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5685 break;
5686 }
5687 if (*s == '\0')
5688 {
5689 as_bad (_("missing condition code in structured control directive"));
5690 return 0;
5691 }
5692
5693 *leftstart = input_line_pointer;
5694 *leftstop = s;
5695 if (*leftstop > *leftstart
5696 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5697 --*leftstop;
5698
5699 input_line_pointer = s;
5700 if (! parse_mri_condition (pcc))
5701 return 0;
5702
5703 /* Look ahead for AND or OR or end of line. */
5704 for (s = input_line_pointer; *s != '\0'; ++s)
5705 {
e1f44d10
NC		 5706 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5707 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5708 ^^^ ^^ */
5709 if ( ( s == input_line_pointer
5710 || *(s-1) == ' '
5711 || *(s-1) == '\t')
5712 && ( ( strncasecmp (s, "AND", 3) == 0
5713 && (s[3] == '.' || ! is_part_of_name (s[3])))
5714 || ( strncasecmp (s, "OR", 2) == 0
5715 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5716 break;
252b5132
RH		 5717 }
5718
5719 *rightstart = input_line_pointer;
5720 *rightstop = s;
5721 if (*rightstop > *rightstart
5722 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5723 --*rightstop;
5724
5725 input_line_pointer = s;
5726
5727 return 1;
5728}
5729
5730#define MCC(b1, b2) (((b1) << 8) | (b2))
5731
5732/* Swap the sense of a condition. This changes the condition so that
5733 it generates the same result when the operands are swapped. */
5734
5735static int
5736swap_mri_condition (cc)
5737 int cc;
5738{
5739 switch (cc)
5740 {
5741 case MCC ('h', 'i'): return MCC ('c', 's');
5742 case MCC ('l', 's'): return MCC ('c', 'c');
e1f44d10
NC		 5743 /* <HS> is an alias for <CC> */
5744 case MCC ('h', 's'):
252b5132 5745 case MCC ('c', 'c'): return MCC ('l', 's');
e1f44d10
NC		 5746 /* <LO> is an alias for <CS> */
5747 case MCC ('l', 'o'):
252b5132
RH		 5748 case MCC ('c', 's'): return MCC ('h', 'i');
5749 case MCC ('p', 'l'): return MCC ('m', 'i');
5750 case MCC ('m', 'i'): return MCC ('p', 'l');
5751 case MCC ('g', 'e'): return MCC ('l', 'e');
5752 case MCC ('l', 't'): return MCC ('g', 't');
5753 case MCC ('g', 't'): return MCC ('l', 't');
5754 case MCC ('l', 'e'): return MCC ('g', 'e');
e1f44d10
NC		 5755 /* issue a warning for conditions we can not swap */
5756 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5757 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5758 case MCC ('v', 'c'):
5759 case MCC ('v', 's'):
5760 default :
5761 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5762 (char) (cc >> 8), (char) (cc));
5763 break;
252b5132
RH		 5764 }
5765 return cc;
5766}
5767
5768/* Reverse the sense of a condition. */
5769
5770static int
5771reverse_mri_condition (cc)
5772 int cc;
5773{
5774 switch (cc)
5775 {
5776 case MCC ('h', 'i'): return MCC ('l', 's');
5777 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5778 /* <HS> is an alias for <CC> */
5779 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5780 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5781 /* <LO> is an alias for <CS> */
5782 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5783 case MCC ('c', 's'): return MCC ('c', 'c');
5784 case MCC ('n', 'e'): return MCC ('e', 'q');
5785 case MCC ('e', 'q'): return MCC ('n', 'e');
5786 case MCC ('v', 'c'): return MCC ('v', 's');
5787 case MCC ('v', 's'): return MCC ('v', 'c');
5788 case MCC ('p', 'l'): return MCC ('m', 'i');
5789 case MCC ('m', 'i'): return MCC ('p', 'l');
5790 case MCC ('g', 'e'): return MCC ('l', 't');
5791 case MCC ('l', 't'): return MCC ('g', 'e');
5792 case MCC ('g', 't'): return MCC ('l', 'e');
5793 case MCC ('l', 'e'): return MCC ('g', 't');
5794 }
5795 return cc;
5796}
5797
5798/* Build an MRI structured control expression. This generates test
5799 and branch instructions. It goes to TRUELAB if the condition is
5800 true, and to FALSELAB if the condition is false. Exactly one of
5801 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5802 is the size qualifier for the expression. EXTENT is the size to
5803 use for the branch. */
5804
5805static void
5806build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5807 rightstop, truelab, falselab, extent)
5808 int qual;
5809 int cc;
5810 char *leftstart;
5811 char *leftstop;
5812 char *rightstart;
5813 char *rightstop;
5814 const char *truelab;
5815 const char *falselab;
5816 int extent;
5817{
5818 char *buf;
5819 char *s;
5820
5821 if (leftstart != NULL)
5822 {
5823 struct m68k_op leftop, rightop;
5824 char c;
5825
5826 /* Swap the compare operands, if necessary, to produce a legal
5827 m68k compare instruction. Comparing a register operand with
5828 a non-register operand requires the register to be on the
5829 right (cmp, cmpa). Comparing an immediate value with
5830 anything requires the immediate value to be on the left
5831 (cmpi). */
5832
5833 c = *leftstop;
5834 *leftstop = '\0';
5835 (void) m68k_ip_op (leftstart, &leftop);
5836 *leftstop = c;
5837
5838 c = *rightstop;
5839 *rightstop = '\0';
5840 (void) m68k_ip_op (rightstart, &rightop);
5841 *rightstop = c;
5842
5843 if (rightop.mode == IMMED
5844 || ((leftop.mode == DREG || leftop.mode == AREG)
5845 && (rightop.mode != DREG && rightop.mode != AREG)))
5846 {
5847 char *temp;
5848
e1f44d10
NC		 5849 /* Correct conditional handling:
5850 if #1 <lt> d0 then ;means if (1 < d0)
5851 ...
5852 endi
5853
5854 should assemble to:
5855
5856 cmp #1,d0 if we do *not* swap the operands
5857 bgt true we need the swapped condition!
5858 ble false
5859 true:
5860 ...
5861 false:
5862 */
252b5132
RH		 5863 temp = leftstart;
5864 leftstart = rightstart;
5865 rightstart = temp;
5866 temp = leftstop;
5867 leftstop = rightstop;
5868 rightstop = temp;
e1f44d10
NC		 5869 } else {
5870 cc = swap_mri_condition (cc);
252b5132
RH		 5871 }
5872 }
5873
5874 if (truelab == NULL)
5875 {
5876 cc = reverse_mri_condition (cc);
5877 truelab = falselab;
5878 }
92774660 5879
252b5132
RH		 5880 if (leftstart != NULL)
5881 {
5882 buf = (char *) xmalloc (20
5883 + (leftstop - leftstart)
5884 + (rightstop - rightstart));
5885 s = buf;
5886 *s++ = 'c';
5887 *s++ = 'm';
5888 *s++ = 'p';
5889 if (qual != '\0')
3882b010 5890 *s++ = TOLOWER (qual);
252b5132
RH		 5891 *s++ = ' ';
5892 memcpy (s, leftstart, leftstop - leftstart);
5893 s += leftstop - leftstart;
5894 *s++ = ',';
5895 memcpy (s, rightstart, rightstop - rightstart);
5896 s += rightstop - rightstart;
5897 *s = '\0';
5898 mri_assemble (buf);
5899 free (buf);
5900 }
92774660 5901
252b5132
RH		 5902 buf = (char *) xmalloc (20 + strlen (truelab));
5903 s = buf;
5904 *s++ = 'b';
5905 *s++ = cc >> 8;
5906 *s++ = cc & 0xff;
5907 if (extent != '\0')
3882b010 5908 *s++ = TOLOWER (extent);
252b5132
RH		 5909 *s++ = ' ';
5910 strcpy (s, truelab);
5911 mri_assemble (buf);
5912 free (buf);
5913}
5914
5915/* Parse an MRI structured control expression. This generates test
5916 and branch instructions. STOP is where the expression ends. It
5917 goes to TRUELAB if the condition is true, and to FALSELAB if the
5918 condition is false. Exactly one of TRUELAB and FALSELAB will be
5919 NULL, meaning to fall through. QUAL is the size qualifier for the
5920 expression. EXTENT is the size to use for the branch. */
5921
5922static void
5923parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5924 char *stop;
5925 int qual;
5926 const char *truelab;
5927 const char *falselab;
5928 int extent;
5929{
5930 int c;
5931 int cc;
5932 char *leftstart;
5933 char *leftstop;
5934 char *rightstart;
5935 char *rightstop;
5936
5937 c = *stop;
5938 *stop = '\0';
5939
5940 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5941 &rightstart, &rightstop))
5942 {
5943 *stop = c;
5944 return;
5945 }
5946
5947 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5948 {
5949 const char *flab;
5950
5951 if (falselab != NULL)
5952 flab = falselab;
5953 else
5954 flab = mri_control_label ();
5955
5956 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5957 rightstop, (const char *) NULL, flab, extent);
5958
5959 input_line_pointer += 3;
5960 if (*input_line_pointer != '.'
5961 || input_line_pointer[1] == '\0')
5962 qual = '\0';
5963 else
5964 {
5965 qual = input_line_pointer[1];
5966 input_line_pointer += 2;
5967 }
5968
5969 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5970 &rightstart, &rightstop))
5971 {
5972 *stop = c;
5973 return;
5974 }
5975
5976 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5977 rightstop, truelab, falselab, extent);
5978
5979 if (falselab == NULL)
5980 colon (flab);
5981 }
5982 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5983 {
5984 const char *tlab;
5985
5986 if (truelab != NULL)
5987 tlab = truelab;
5988 else
5989 tlab = mri_control_label ();
5990
5991 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5992 rightstop, tlab, (const char *) NULL, extent);
5993
5994 input_line_pointer += 2;
5995 if (*input_line_pointer != '.'
5996 || input_line_pointer[1] == '\0')
5997 qual = '\0';
5998 else
5999 {
6000 qual = input_line_pointer[1];
6001 input_line_pointer += 2;
6002 }
6003
6004 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6005 &rightstart, &rightstop))
6006 {
6007 *stop = c;
6008 return;
6009 }
6010
6011 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6012 rightstop, truelab, falselab, extent);
6013
6014 if (truelab == NULL)
6015 colon (tlab);
6016 }
6017 else
6018 {
6019 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6020 rightstop, truelab, falselab, extent);
6021 }
6022
6023 *stop = c;
6024 if (input_line_pointer != stop)
6025 as_bad (_("syntax error in structured control directive"));
6026}
6027
6028/* Handle the MRI IF pseudo-op. This may be a structured control
6029 directive, or it may be a regular assembler conditional, depending
6030 on its operands. */
6031
6032static void
6033s_mri_if (qual)
6034 int qual;
6035{
6036 char *s;
6037 int c;
6038 struct mri_control_info *n;
6039
6040 /* A structured control directive must end with THEN with an
6041 optional qualifier. */
6042 s = input_line_pointer;
e1f44d10
NC		 6043 /* We only accept '*' as introduction of comments if preceded by white space
6044 or at first column of a line (I think this can't actually happen here?)
6045 This is important when assembling:
6046 if d0 <ne> 12(a0,d0*2) then
6047 if d0 <ne> #CONST*20 then */
6048 while ( ! ( is_end_of_line[(unsigned char) *s]
6049 || ( flag_mri
6050 && *s == '*'
6051 && ( s == input_line_pointer
6052 || *(s-1) == ' '
6053 || *(s-1) == '\t'))))
252b5132
RH		 6054 ++s;
6055 --s;
6056 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6057 --s;
6058
6059 if (s - input_line_pointer > 1
6060 && s[-1] == '.')
6061 s -= 2;
6062
6063 if (s - input_line_pointer < 3
6064 || strncasecmp (s - 3, "THEN", 4) != 0)
6065 {
6066 if (qual != '\0')
6067 {
6068 as_bad (_("missing then"));
6069 ignore_rest_of_line ();
6070 return;
6071 }
6072
6073 /* It's a conditional. */
6074 s_if (O_ne);
6075 return;
6076 }
6077
6078 /* Since this might be a conditional if, this pseudo-op will be
6079 called even if we are supported to be ignoring input. Double
6080 check now. Clobber *input_line_pointer so that ignore_input
6081 thinks that this is not a special pseudo-op. */
6082 c = *input_line_pointer;
6083 *input_line_pointer = 0;
6084 if (ignore_input ())
6085 {
6086 *input_line_pointer = c;
6087 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6088 ++input_line_pointer;
6089 demand_empty_rest_of_line ();
6090 return;
6091 }
6092 *input_line_pointer = c;
6093
6094 n = push_mri_control (mri_if);
6095
6096 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6097 n->next, s[1] == '.' ? s[2] : '\0');
6098
6099 if (s[1] == '.')
6100 input_line_pointer = s + 3;
6101 else
6102 input_line_pointer = s + 1;
6103
6104 if (flag_mri)
6105 {
6106 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6107 ++input_line_pointer;
6108 }
6109
6110 demand_empty_rest_of_line ();
6111}
6112
6113/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6114 structured IF, associate the ELSE with the IF. Otherwise, assume
6115 it is a conditional else. */
6116
6117static void
6118s_mri_else (qual)
6119 int qual;
6120{
6121 int c;
6122 char *buf;
6123 char q[2];
6124
6125 if (qual == '\0'
6126 && (mri_control_stack == NULL
6127 || mri_control_stack->type != mri_if
6128 || mri_control_stack->else_seen))
6129 {
6130 s_else (0);
6131 return;
6132 }
6133
6134 c = *input_line_pointer;
6135 *input_line_pointer = 0;
6136 if (ignore_input ())
6137 {
6138 *input_line_pointer = c;
6139 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6140 ++input_line_pointer;
6141 demand_empty_rest_of_line ();
6142 return;
6143 }
6144 *input_line_pointer = c;
6145
6146 if (mri_control_stack == NULL
6147 || mri_control_stack->type != mri_if
6148 || mri_control_stack->else_seen)
6149 {
6150 as_bad (_("else without matching if"));
6151 ignore_rest_of_line ();
6152 return;
6153 }
6154
6155 mri_control_stack->else_seen = 1;
6156
6157 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6158 q[0] = TOLOWER (qual);
252b5132
RH		 6159 q[1] = '\0';
6160 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6161 mri_assemble (buf);
6162 free (buf);
6163
6164 colon (mri_control_stack->next);
6165
6166 if (flag_mri)
6167 {
6168 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6169 ++input_line_pointer;
6170 }
6171
6172 demand_empty_rest_of_line ();
6173}
6174
6175/* Handle the MRI ENDI pseudo-op. */
6176
6177static void
6178s_mri_endi (ignore)
36823076 6179 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6180{
6181 if (mri_control_stack == NULL
6182 || mri_control_stack->type != mri_if)
6183 {
6184 as_bad (_("endi without matching if"));
6185 ignore_rest_of_line ();
6186 return;
6187 }
6188
6189 /* ignore_input will not return true for ENDI, so we don't need to
6190 worry about checking it again here. */
6191
6192 if (! mri_control_stack->else_seen)
6193 colon (mri_control_stack->next);
6194 colon (mri_control_stack->bottom);
6195
6196 pop_mri_control ();
6197
6198 if (flag_mri)
6199 {
6200 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6201 ++input_line_pointer;
6202 }
6203
6204 demand_empty_rest_of_line ();
6205}
6206
6207/* Handle the MRI BREAK pseudo-op. */
6208
6209static void
6210s_mri_break (extent)
6211 int extent;
6212{
6213 struct mri_control_info *n;
6214 char *buf;
6215 char ex[2];
6216
6217 n = mri_control_stack;
6218 while (n != NULL
6219 && n->type != mri_for
6220 && n->type != mri_repeat
6221 && n->type != mri_while)
6222 n = n->outer;
6223 if (n == NULL)
6224 {
6225 as_bad (_("break outside of structured loop"));
6226 ignore_rest_of_line ();
6227 return;
6228 }
6229
6230 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6231 ex[0] = TOLOWER (extent);
252b5132
RH		 6232 ex[1] = '\0';
6233 sprintf (buf, "bra%s %s", ex, n->bottom);
6234 mri_assemble (buf);
6235 free (buf);
6236
6237 if (flag_mri)
6238 {
6239 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6240 ++input_line_pointer;
6241 }
6242
6243 demand_empty_rest_of_line ();
6244}
6245
6246/* Handle the MRI NEXT pseudo-op. */
6247
6248static void
6249s_mri_next (extent)
6250 int extent;
6251{
6252 struct mri_control_info *n;
6253 char *buf;
6254 char ex[2];
6255
6256 n = mri_control_stack;
6257 while (n != NULL
6258 && n->type != mri_for
6259 && n->type != mri_repeat
6260 && n->type != mri_while)
6261 n = n->outer;
6262 if (n == NULL)
6263 {
6264 as_bad (_("next outside of structured loop"));
6265 ignore_rest_of_line ();
6266 return;
6267 }
6268
6269 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6270 ex[0] = TOLOWER (extent);
252b5132
RH		 6271 ex[1] = '\0';
6272 sprintf (buf, "bra%s %s", ex, n->next);
6273 mri_assemble (buf);
6274 free (buf);
6275
6276 if (flag_mri)
6277 {
6278 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6279 ++input_line_pointer;
6280 }
6281
6282 demand_empty_rest_of_line ();
6283}
6284
6285/* Handle the MRI FOR pseudo-op. */
6286
6287static void
6288s_mri_for (qual)
6289 int qual;
6290{
6291 const char *varstart, *varstop;
6292 const char *initstart, *initstop;
6293 const char *endstart, *endstop;
6294 const char *bystart, *bystop;
6295 int up;
6296 int by;
6297 int extent;
6298 struct mri_control_info *n;
6299 char *buf;
6300 char *s;
6301 char ex[2];
6302
6303 /* The syntax is
6304 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6305 */
6306
6307 SKIP_WHITESPACE ();
6308 varstart = input_line_pointer;
6309
6310 /* Look for the '='. */
6311 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6312 && *input_line_pointer != '=')
6313 ++input_line_pointer;
6314 if (*input_line_pointer != '=')
6315 {
6316 as_bad (_("missing ="));
6317 ignore_rest_of_line ();
6318 return;
6319 }
6320
6321 varstop = input_line_pointer;
6322 if (varstop > varstart
6323 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6324 --varstop;
6325
6326 ++input_line_pointer;
6327
6328 initstart = input_line_pointer;
6329
6330 /* Look for TO or DOWNTO. */
6331 up = 1;
6332 initstop = NULL;
6333 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6334 {
6335 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6336 && ! is_part_of_name (input_line_pointer[2]))
6337 {
6338 initstop = input_line_pointer;
6339 input_line_pointer += 2;
6340 break;
6341 }
6342 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6343 && ! is_part_of_name (input_line_pointer[6]))
6344 {
6345 initstop = input_line_pointer;
6346 up = 0;
6347 input_line_pointer += 6;
6348 break;
6349 }
6350 ++input_line_pointer;
6351 }
6352 if (initstop == NULL)
6353 {
6354 as_bad (_("missing to or downto"));
6355 ignore_rest_of_line ();
6356 return;
6357 }
6358 if (initstop > initstart
6359 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6360 --initstop;
6361
6362 SKIP_WHITESPACE ();
6363 endstart = input_line_pointer;
6364
6365 /* Look for BY or DO. */
6366 by = 0;
6367 endstop = NULL;
6368 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6369 {
6370 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6371 && ! is_part_of_name (input_line_pointer[2]))
6372 {
6373 endstop = input_line_pointer;
6374 by = 1;
6375 input_line_pointer += 2;
6376 break;
6377 }
6378 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6379 && (input_line_pointer[2] == '.'
6380 || ! is_part_of_name (input_line_pointer[2])))
6381 {
6382 endstop = input_line_pointer;
6383 input_line_pointer += 2;
6384 break;
6385 }
6386 ++input_line_pointer;
6387 }
6388 if (endstop == NULL)
6389 {
6390 as_bad (_("missing do"));
6391 ignore_rest_of_line ();
6392 return;
6393 }
6394 if (endstop > endstart
6395 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6396 --endstop;
6397
6398 if (! by)
6399 {
6400 bystart = "#1";
6401 bystop = bystart + 2;
6402 }
6403 else
6404 {
6405 SKIP_WHITESPACE ();
6406 bystart = input_line_pointer;
6407
6408 /* Look for DO. */
6409 bystop = NULL;
6410 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6411 {
6412 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6413 && (input_line_pointer[2] == '.'
6414 || ! is_part_of_name (input_line_pointer[2])))
6415 {
6416 bystop = input_line_pointer;
6417 input_line_pointer += 2;
6418 break;
6419 }
6420 ++input_line_pointer;
6421 }
6422 if (bystop == NULL)
6423 {
6424 as_bad (_("missing do"));
6425 ignore_rest_of_line ();
6426 return;
6427 }
6428 if (bystop > bystart
6429 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6430 --bystop;
6431 }
6432
6433 if (*input_line_pointer != '.')
6434 extent = '\0';
6435 else
6436 {
6437 extent = input_line_pointer[1];
6438 input_line_pointer += 2;
6439 }
6440
6441 /* We have fully parsed the FOR operands. Now build the loop. */
6442
6443 n = push_mri_control (mri_for);
6444
6445 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6446
6447 /* move init,var */
6448 s = buf;
6449 *s++ = 'm';
6450 *s++ = 'o';
6451 *s++ = 'v';
6452 *s++ = 'e';
6453 if (qual != '\0')
3882b010 6454 *s++ = TOLOWER (qual);
252b5132
RH		 6455 *s++ = ' ';
6456 memcpy (s, initstart, initstop - initstart);
6457 s += initstop - initstart;
6458 *s++ = ',';
6459 memcpy (s, varstart, varstop - varstart);
6460 s += varstop - varstart;
6461 *s = '\0';
6462 mri_assemble (buf);
6463
6464 colon (n->top);
6465
6466 /* cmp end,var */
6467 s = buf;
6468 *s++ = 'c';
6469 *s++ = 'm';
6470 *s++ = 'p';
6471 if (qual != '\0')
3882b010 6472 *s++ = TOLOWER (qual);
252b5132
RH		 6473 *s++ = ' ';
6474 memcpy (s, endstart, endstop - endstart);
6475 s += endstop - endstart;
6476 *s++ = ',';
6477 memcpy (s, varstart, varstop - varstart);
6478 s += varstop - varstart;
6479 *s = '\0';
6480 mri_assemble (buf);
6481
6482 /* bcc bottom */
3882b010 6483 ex[0] = TOLOWER (extent);
252b5132
RH		 6484 ex[1] = '\0';
6485 if (up)
6486 sprintf (buf, "blt%s %s", ex, n->bottom);
6487 else
6488 sprintf (buf, "bgt%s %s", ex, n->bottom);
6489 mri_assemble (buf);
6490
6491 /* Put together the add or sub instruction used by ENDF. */
6492 s = buf;
6493 if (up)
6494 strcpy (s, "add");
6495 else
6496 strcpy (s, "sub");
6497 s += 3;
6498 if (qual != '\0')
3882b010 6499 *s++ = TOLOWER (qual);
252b5132
RH		 6500 *s++ = ' ';
6501 memcpy (s, bystart, bystop - bystart);
6502 s += bystop - bystart;
6503 *s++ = ',';
6504 memcpy (s, varstart, varstop - varstart);
6505 s += varstop - varstart;
6506 *s = '\0';
6507 n->incr = buf;
6508
6509 if (flag_mri)
6510 {
6511 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6512 ++input_line_pointer;
6513 }
6514
6515 demand_empty_rest_of_line ();
6516}
6517
6518/* Handle the MRI ENDF pseudo-op. */
6519
6520static void
6521s_mri_endf (ignore)
36823076 6522 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6523{
6524 if (mri_control_stack == NULL
6525 || mri_control_stack->type != mri_for)
6526 {
6527 as_bad (_("endf without for"));
6528 ignore_rest_of_line ();
6529 return;
6530 }
6531
6532 colon (mri_control_stack->next);
6533
6534 mri_assemble (mri_control_stack->incr);
6535
6536 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6537 mri_assemble (mri_control_stack->incr);
6538
6539 free (mri_control_stack->incr);
6540
6541 colon (mri_control_stack->bottom);
6542
6543 pop_mri_control ();
6544
6545 if (flag_mri)
6546 {
6547 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6548 ++input_line_pointer;
6549 }
6550
6551 demand_empty_rest_of_line ();
6552}
6553
6554/* Handle the MRI REPEAT pseudo-op. */
6555
6556static void
6557s_mri_repeat (ignore)
36823076 6558 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6559{
6560 struct mri_control_info *n;
6561
6562 n = push_mri_control (mri_repeat);
6563 colon (n->top);
6564 if (flag_mri)
6565 {
6566 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6567 ++input_line_pointer;
6568 }
6569 demand_empty_rest_of_line ();
6570}
6571
6572/* Handle the MRI UNTIL pseudo-op. */
6573
6574static void
6575s_mri_until (qual)
6576 int qual;
6577{
6578 char *s;
6579
6580 if (mri_control_stack == NULL
6581 || mri_control_stack->type != mri_repeat)
6582 {
6583 as_bad (_("until without repeat"));
6584 ignore_rest_of_line ();
6585 return;
6586 }
6587
6588 colon (mri_control_stack->next);
6589
6590 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6591 ;
6592
6593 parse_mri_control_expression (s, qual, (const char *) NULL,
6594 mri_control_stack->top, '\0');
6595
6596 colon (mri_control_stack->bottom);
6597
6598 input_line_pointer = s;
6599
6600 pop_mri_control ();
6601
6602 if (flag_mri)
6603 {
6604 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6605 ++input_line_pointer;
6606 }
6607
6608 demand_empty_rest_of_line ();
6609}
6610
6611/* Handle the MRI WHILE pseudo-op. */
6612
6613static void
6614s_mri_while (qual)
6615 int qual;
6616{
6617 char *s;
6618
6619 struct mri_control_info *n;
6620
6621 s = input_line_pointer;
e1f44d10
NC		 6622 /* We only accept '*' as introduction of comments if preceded by white space
6623 or at first column of a line (I think this can't actually happen here?)
6624 This is important when assembling:
6625 while d0 <ne> 12(a0,d0*2) do
6626 while d0 <ne> #CONST*20 do */
6627 while ( ! ( is_end_of_line[(unsigned char) *s]
6628 || ( flag_mri
6629 && *s == '*'
6630 && ( s == input_line_pointer
6631 || *(s-1) == ' '
6632 || *(s-1) == '\t'))))
252b5132
RH		 6633 s++;
6634 --s;
6635 while (*s == ' ' || *s == '\t')
6636 --s;
6637 if (s - input_line_pointer > 1
6638 && s[-1] == '.')
6639 s -= 2;
6640 if (s - input_line_pointer < 2
6641 || strncasecmp (s - 1, "DO", 2) != 0)
6642 {
6643 as_bad (_("missing do"));
6644 ignore_rest_of_line ();
6645 return;
6646 }
6647
6648 n = push_mri_control (mri_while);
6649
6650 colon (n->next);
6651
6652 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6653 s[1] == '.' ? s[2] : '\0');
6654
6655 input_line_pointer = s + 1;
6656 if (*input_line_pointer == '.')
6657 input_line_pointer += 2;
6658
6659 if (flag_mri)
6660 {
6661 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6662 ++input_line_pointer;
6663 }
6664
6665 demand_empty_rest_of_line ();
6666}
6667
6668/* Handle the MRI ENDW pseudo-op. */
6669
6670static void
6671s_mri_endw (ignore)
36823076 6672 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6673{
6674 char *buf;
6675
6676 if (mri_control_stack == NULL
6677 || mri_control_stack->type != mri_while)
6678 {
6679 as_bad (_("endw without while"));
6680 ignore_rest_of_line ();
6681 return;
6682 }
6683
6684 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6685 sprintf (buf, "bra %s", mri_control_stack->next);
6686 mri_assemble (buf);
6687 free (buf);
6688
6689 colon (mri_control_stack->bottom);
6690
6691 pop_mri_control ();
6692
6693 if (flag_mri)
6694 {
6695 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6696 ++input_line_pointer;
6697 }
6698
6699 demand_empty_rest_of_line ();
6700}
6701\f
6702/*
6703 * md_parse_option
6704 * Invocation line includes a switch not recognized by the base assembler.
6705 * See if it's a processor-specific option. These are:
6706 *
6707 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6708 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6709 * Select the architecture. Instructions or features not
6710 * supported by the selected architecture cause fatal
6711 * errors. More than one may be specified. The default is
6712 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6713 * for -m68000, and -m68882 is a synonym for -m68881.
6714 * -[A]m[c]no-68851, -[A]m[c]no-68881
6715 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6716 * so don't use or document it, but that's the way the parsing
6717 * works).
6718 *
6719 * -pic Indicates PIC.
6720 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6721 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6722 *
6723 * --bitwise-or
6724 * Permit `|' to be used in expressions.
6725 *
6726 */
6727
6728#ifdef OBJ_ELF
6729CONST char *md_shortopts = "lSA:m:kQ:V";
6730#else
6731CONST char *md_shortopts = "lSA:m:k";
6732#endif
6733
6734struct option md_longopts[] = {
6735#define OPTION_PIC (OPTION_MD_BASE)
6736 {"pic", no_argument, NULL, OPTION_PIC},
6737#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6738 {"register-prefix-optional", no_argument, NULL,
6739 OPTION_REGISTER_PREFIX_OPTIONAL},
6740#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6741 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6742#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6743 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6744#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6745 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6746#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6747 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6748#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6749 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6750#define OPTION_PCREL (OPTION_MD_BASE + 7)
6751 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6752 {NULL, no_argument, NULL, 0}
6753};
bc805888 6754size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6755
6756int
6757md_parse_option (c, arg)
6758 int c;
6759 char *arg;
6760{
6761 switch (c)
6762 {
6763 case 'l': /* -l means keep external to 2 bit offset
6764 rather than 16 bit one */
6765 flag_short_refs = 1;
6766 break;
6767
6768 case 'S': /* -S means that jbsr's always turn into
6769 jsr's. */
6770 flag_long_jumps = 1;
6771 break;
6772
28e7409f
NC		 6773 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6774 branches into absolute jumps. */
6775 flag_keep_pcrel = 1;
6776 break;
6777
252b5132
RH		 6778 case 'A':
6779 if (*arg == 'm')
6780 arg++;
6781 /* intentional fall-through */
6782 case 'm':
6783
6784 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6785 {
6786 int i;
6787 unsigned long arch;
6788 const char *oarg = arg;
6789
6790 arg += 3;
6791 if (*arg == 'm')
6792 {
6793 arg++;
6794 if (arg[0] == 'c' && arg[1] == '6')
6795 arg++;
6796 }
6797 for (i = 0; i < n_archs; i++)
6798 if (!strcmp (arg, archs[i].name))
6799 break;
6800 if (i == n_archs)
6801 {
6802 unknown:
6803 as_bad (_("unrecognized option `%s'"), oarg);
6804 return 0;
6805 }
6806 arch = archs[i].arch;
6807 if (arch == m68881)
6808 no_68881 = 1;
6809 else if (arch == m68851)
6810 no_68851 = 1;
6811 else
6812 goto unknown;
6813 }
6814 else
6815 {
6816 int i;
6817
6818 if (arg[0] == 'c' && arg[1] == '6')
6819 arg++;
6820
6821 for (i = 0; i < n_archs; i++)
6822 if (!strcmp (arg, archs[i].name))
6823 {
6824 unsigned long arch = archs[i].arch;
6825 if (cpu_of_arch (arch))
6826 /* It's a cpu spec. */
6827 {
6828 current_architecture &= ~m68000up;
6829 current_architecture |= arch;
6830 }
6831 else if (arch == m68881)
6832 {
6833 current_architecture |= m68881;
6834 no_68881 = 0;
6835 }
6836 else if (arch == m68851)
6837 {
6838 current_architecture |= m68851;
6839 no_68851 = 0;
6840 }
6841 else
6842 /* ??? */
6843 abort ();
6844 break;
6845 }
6846 if (i == n_archs)
6847 {
6848 as_bad (_("unrecognized architecture specification `%s'"), arg);
6849 return 0;
6850 }
6851 }
6852 break;
6853
6854 case OPTION_PIC:
6855 case 'k':
6856 flag_want_pic = 1;
6857 break; /* -pic, Position Independent Code */
6858
6859 case OPTION_REGISTER_PREFIX_OPTIONAL:
6860 flag_reg_prefix_optional = 1;
6861 reg_prefix_optional_seen = 1;
6862 break;
6863
6864 /* -V: SVR4 argument to print version ID. */
6865 case 'V':
6866 print_version_id ();
6867 break;
6868
6869 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6870 should be emitted or not. FIXME: Not implemented. */
6871 case 'Q':
6872 break;
6873
6874 case OPTION_BITWISE_OR:
6875 {
6876 char *n, *t;
6877 const char *s;
6878
6879 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6880 t = n;
6881 for (s = m68k_comment_chars; *s != '\0'; s++)
6882 if (*s != '|')
6883 *t++ = *s;
6884 *t = '\0';
6885 m68k_comment_chars = n;
6886 }
6887 break;
6888
6889 case OPTION_BASE_SIZE_DEFAULT_16:
6890 m68k_index_width_default = SIZE_WORD;
6891 break;
6892
6893 case OPTION_BASE_SIZE_DEFAULT_32:
6894 m68k_index_width_default = SIZE_LONG;
6895 break;
6896
6897 case OPTION_DISP_SIZE_DEFAULT_16:
6898 m68k_rel32 = 0;
6899 m68k_rel32_from_cmdline = 1;
6900 break;
6901
6902 case OPTION_DISP_SIZE_DEFAULT_32:
6903 m68k_rel32 = 1;
6904 m68k_rel32_from_cmdline = 1;
6905 break;
6906
6907 default:
6908 return 0;
6909 }
6910
6911 return 1;
6912}
6913
6914void
6915md_show_usage (stream)
6916 FILE *stream;
6917{
bc805888 6918 fprintf (stream, _("\
252b5132
RH		 6919680X0 options:\n\
6920-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 6921-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6922-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6923-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
252b5132
RH		 6924 specify variant of 680X0 architecture [default 68020]\n\
6925-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6926 target has/lacks floating-point coprocessor\n\
6927 [default yes for 68020, 68030, and cpu32]\n"));
bc805888 6928 fprintf (stream, _("\
252b5132
RH		 6929-m68851 | -mno-68851\n\
6930 target has/lacks memory-management unit coprocessor\n\
6931 [default yes for 68020 and up]\n\
6932-pic, -k generate position independent code\n\
6933-S turn jbsr into jsr\n\
28e7409f 6934--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6935--register-prefix-optional\n\
6936 recognize register names without prefix character\n\
6937--bitwise-or do not treat `|' as a comment character\n"));
6938 fprintf (stream, _("\
6939--base-size-default-16 base reg without size is 16 bits\n\
6940--base-size-default-32 base reg without size is 32 bits (default)\n\
6941--disp-size-default-16 displacement with unknown size is 16 bits\n\
6942--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6943}
6944\f
6945#ifdef TEST2
6946
6947/* TEST2: Test md_assemble() */
6948/* Warning, this routine probably doesn't work anymore */
6949
6950main ()
6951{
6952 struct m68k_it the_ins;
6953 char buf[120];
6954 char *cp;
6955 int n;
6956
6957 m68k_ip_begin ();
6958 for (;;)
6959 {
6960 if (!gets (buf) || !*buf)
6961 break;
6962 if (buf[0] == '|' || buf[1] == '.')
6963 continue;
6964 for (cp = buf; *cp; cp++)
6965 if (*cp == '\t')
6966 *cp = ' ';
6967 if (is_label (buf))
6968 continue;
6969 memset (&the_ins, '\0', sizeof (the_ins));
6970 m68k_ip (&the_ins, buf);
6971 if (the_ins.error)
6972 {
6973 printf (_("Error %s in %s\n"), the_ins.error, buf);
6974 }
6975 else
6976 {
6977 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6978 for (n = 0; n < the_ins.numo; n++)
6979 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6980 printf (" ");
6981 print_the_insn (&the_ins.opcode[0], stdout);
6982 (void) putchar ('\n');
6983 }
6984 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6985 {
6986 if (the_ins.operands[n].error)
6987 {
6988 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6989 continue;
6990 }
6991 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6992 if (the_ins.operands[n].b_const)
6993 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6994 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6995 if (the_ins.operands[n].b_iadd)
6996 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6997 (void) putchar ('\n');
6998 }
6999 }
7000 m68k_ip_end ();
7001 return 0;
7002}
7003
7004is_label (str)
7005 char *str;
7006{
7007 while (*str == ' ')
7008 str++;
7009 while (*str && *str != ' ')
7010 str++;
7011 if (str[-1] == ':' || str[1] == '=')
7012 return 1;
7013 return 0;
7014}
7015
7016#endif
7017
7018/* Possible states for relaxation:
7019
7020 0 0 branch offset byte (bra, etc)
7021 0 1 word
7022 0 2 long
7023
7024 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7025 1 1 word
7026 1 2 long
7027
7028 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7029 2 1 word-long
7030 2 2 long-word
7031 2 3 long-long
7032
7033 */
7034
7035/* We have no need to default values of symbols. */
7036
252b5132
RH		 7037symbolS *
7038md_undefined_symbol (name)
36823076 7039 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7040{
7041 return 0;
7042}
7043
7044/* Round up a section size to the appropriate boundary. */
7045valueT
7046md_section_align (segment, size)
36823076 7047 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7048 valueT size;
7049{
7050#ifdef OBJ_AOUT
7051#ifdef BFD_ASSEMBLER
7052 /* For a.out, force the section size to be aligned. If we don't do
7053 this, BFD will align it for us, but it will not write out the
7054 final bytes of the section. This may be a bug in BFD, but it is
7055 easier to fix it here since that is how the other a.out targets
7056 work. */
7057 int align;
7058
7059 align = bfd_get_section_alignment (stdoutput, segment);
7060 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7061#endif
7062#endif
7063
7064 return size;
7065}
7066
7067/* Exactly what point is a PC-relative offset relative TO?
7068 On the 68k, it is relative to the address of the first extension
7069 word. The difference between the addresses of the offset and the
92774660 7070 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7071long
7072md_pcrel_from (fixP)
7073 fixS *fixP;
7074{
7075 int adjust;
7076
8390138c
AS		 7077 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7078 sign extend the value here. */
7079 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7080 if (adjust == 64)
7081 adjust = -1;
7082 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7083}
7084
7085#ifndef BFD_ASSEMBLER
7086#ifdef OBJ_COFF
7087
252b5132
RH		 7088void
7089tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7090 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7091{
7092}
7093
7094int
7095tc_coff_sizemachdep (frag)
7096 fragS *frag;
7097{
7098 switch (frag->fr_subtype & 0x3)
7099 {
7100 case BYTE:
7101 return 1;
7102 case SHORT:
7103 return 2;
7104 case LONG:
7105 return 4;
7106 default:
7107 abort ();
7108 return 0;
7109 }
7110}
7111
7112#endif
7113#endif
0d96863f
CM		 7114#ifdef OBJ_ELF
7115void m68k_elf_final_processing()
7116{
7117 /* Set file-specific flags if this is a cpu32 processor */
7118 if (cpu_of_arch (current_architecture) & cpu32)
7119 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7120}
7121#endif
GDB Binutils - Deliverables
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