Commit | Line | Data |
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252b5132 | 1 | /* tc-m68k.c -- Assemble for the m68k family |
f7e42eb4 | 2 | Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
6358301e | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 RH |
24 | #include "obstack.h" |
25 | #include "subsegs.h" | |
f27a3839 | 26 | #include "dwarf2dbg.h" |
c04898f8 | 27 | #include "dw2gencfi.h" |
252b5132 RH |
28 | |
29 | #include "opcode/m68k.h" | |
30 | #include "m68k-parse.h" | |
31 | ||
0d96863f CM |
32 | #if defined (OBJ_ELF) |
33 | #include "elf/m68k.h" | |
34 | #endif | |
35 | ||
31302357 AS |
36 | #ifdef M68KCOFF |
37 | #include "obj-coff.h" | |
38 | #endif | |
39 | ||
252b5132 RH |
40 | /* This string holds the chars that always start a comment. If the |
41 | pre-processor is disabled, these aren't very useful. The macro | |
42 | tc_comment_chars points to this. We use this, rather than the | |
43 | usual comment_chars, so that the --bitwise-or option will work. */ | |
44 | #if defined (TE_SVR4) || defined (TE_DELTA) | |
45 | const char *m68k_comment_chars = "|#"; | |
46 | #else | |
47 | const char *m68k_comment_chars = "|"; | |
48 | #endif | |
49 | ||
50 | /* This array holds the chars that only start a comment at the beginning of | |
51 | a line. If the line seems to have the form '# 123 filename' | |
52 | .line and .file directives will appear in the pre-processed output */ | |
53 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
54 | first line of the input file. This is because the compiler outputs | |
92774660 KH |
55 | #NO_APP at the beginning of its output. */ |
56 | /* Also note that comments like this one will always work. */ | |
252b5132 RH |
57 | const char line_comment_chars[] = "#*"; |
58 | ||
63a0b638 | 59 | const char line_separator_chars[] = ";"; |
252b5132 | 60 | |
36759679 | 61 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
5a38dc70 | 62 | const char EXP_CHARS[] = "eE"; |
252b5132 RH |
63 | |
64 | /* Chars that mean this number is a floating point constant, as | |
65 | in "0f12.456" or "0d1.2345e12". */ | |
66 | ||
5a38dc70 | 67 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
252b5132 RH |
68 | |
69 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
70 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
71 | but nothing is ideal around here. */ | |
72 | ||
36759679 | 73 | const int md_reloc_size = 8; /* Size of relocation record. */ |
252b5132 RH |
74 | |
75 | /* Are we trying to generate PIC code? If so, absolute references | |
76 | ought to be made into linkage table references or pc-relative | |
92774660 | 77 | references. Not implemented. For ELF there are other means |
252b5132 RH |
78 | to denote pic relocations. */ |
79 | int flag_want_pic; | |
80 | ||
36759679 NC |
81 | static int flag_short_refs; /* -l option. */ |
82 | static int flag_long_jumps; /* -S option. */ | |
28e7409f | 83 | static int flag_keep_pcrel; /* --pcrel option. */ |
252b5132 RH |
84 | |
85 | #ifdef REGISTER_PREFIX_OPTIONAL | |
86 | int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; | |
87 | #else | |
88 | int flag_reg_prefix_optional; | |
89 | #endif | |
90 | ||
91 | /* Whether --register-prefix-optional was used on the command line. */ | |
92 | static int reg_prefix_optional_seen; | |
93 | ||
94 | /* The floating point coprocessor to use by default. */ | |
95 | static enum m68k_register m68k_float_copnum = COP1; | |
96 | ||
97 | /* If this is non-zero, then references to number(%pc) will be taken | |
98 | to refer to number, rather than to %pc + number. */ | |
99 | static int m68k_abspcadd; | |
100 | ||
101 | /* If this is non-zero, then the quick forms of the move, add, and sub | |
102 | instructions are used when possible. */ | |
103 | static int m68k_quick = 1; | |
104 | ||
105 | /* If this is non-zero, then if the size is not specified for a base | |
106 | or outer displacement, the assembler assumes that the size should | |
107 | be 32 bits. */ | |
108 | static int m68k_rel32 = 1; | |
109 | ||
110 | /* This is non-zero if m68k_rel32 was set from the command line. */ | |
111 | static int m68k_rel32_from_cmdline; | |
112 | ||
113 | /* The default width to use for an index register when using a base | |
114 | displacement. */ | |
115 | static enum m68k_size m68k_index_width_default = SIZE_LONG; | |
116 | ||
117 | /* We want to warn if any text labels are misaligned. In order to get | |
118 | the right line number, we need to record the line number for each | |
119 | label. */ | |
252b5132 RH |
120 | struct label_line |
121 | { | |
122 | struct label_line *next; | |
123 | symbolS *label; | |
124 | char *file; | |
125 | unsigned int line; | |
126 | int text; | |
127 | }; | |
128 | ||
129 | /* The list of labels. */ | |
130 | ||
131 | static struct label_line *labels; | |
132 | ||
133 | /* The current label. */ | |
134 | ||
135 | static struct label_line *current_label; | |
136 | ||
60fed2d3 NC |
137 | /* Pointer to list holding the opcodes sorted by name. */ |
138 | static struct m68k_opcode const ** m68k_sorted_opcodes; | |
139 | ||
36759679 NC |
140 | /* Its an arbitrary name: This means I don't approve of it. |
141 | See flames below. */ | |
252b5132 RH |
142 | static struct obstack robyn; |
143 | ||
252b5132 RH |
144 | struct m68k_incant |
145 | { | |
146 | const char *m_operands; | |
147 | unsigned long m_opcode; | |
148 | short m_opnum; | |
149 | short m_codenum; | |
150 | int m_arch; | |
151 | struct m68k_incant *m_next; | |
152 | }; | |
153 | ||
154 | #define getone(x) ((((x)->m_opcode)>>16)&0xffff) | |
155 | #define gettwo(x) (((x)->m_opcode)&0xffff) | |
156 | ||
157 | static const enum m68k_register m68000_control_regs[] = { 0 }; | |
158 | static const enum m68k_register m68010_control_regs[] = { | |
159 | SFC, DFC, USP, VBR, | |
160 | 0 | |
161 | }; | |
162 | static const enum m68k_register m68020_control_regs[] = { | |
163 | SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, | |
164 | 0 | |
165 | }; | |
166 | static const enum m68k_register m68040_control_regs[] = { | |
167 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, | |
168 | USP, VBR, MSP, ISP, MMUSR, URP, SRP, | |
169 | 0 | |
170 | }; | |
171 | static const enum m68k_register m68060_control_regs[] = { | |
172 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, | |
173 | USP, VBR, URP, SRP, PCR, | |
174 | 0 | |
175 | }; | |
6da466c7 | 176 | static const enum m68k_register mcf_control_regs[] = { |
3e602632 | 177 | CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, |
252b5132 RH |
178 | RAMBAR0, RAMBAR1, MBAR, |
179 | 0 | |
180 | }; | |
3e602632 NC |
181 | static const enum m68k_register mcf528x_control_regs[] = { |
182 | CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR, | |
183 | 0 | |
184 | }; | |
185 | static const enum m68k_register mcfv4e_control_regs[] = { | |
186 | CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR, | |
187 | ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1, | |
188 | PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, | |
189 | PCR3U0, PCR3L0, PCR3U1, PCR3L1, | |
190 | 0 | |
191 | }; | |
252b5132 RH |
192 | #define cpu32_control_regs m68010_control_regs |
193 | ||
194 | static const enum m68k_register *control_regs; | |
195 | ||
36759679 | 196 | /* Internal form of a 68020 instruction. */ |
252b5132 RH |
197 | struct m68k_it |
198 | { | |
199 | const char *error; | |
36759679 | 200 | const char *args; /* List of opcode info. */ |
252b5132 RH |
201 | int numargs; |
202 | ||
36759679 | 203 | int numo; /* Number of shorts in opcode. */ |
252b5132 RH |
204 | short opcode[11]; |
205 | ||
206 | struct m68k_op operands[6]; | |
207 | ||
36759679 | 208 | int nexp; /* Number of exprs in use. */ |
252b5132 RH |
209 | struct m68k_exp exprs[4]; |
210 | ||
36759679 | 211 | int nfrag; /* Number of frags we have to produce. */ |
252b5132 RH |
212 | struct |
213 | { | |
36759679 | 214 | int fragoff; /* Where in the current opcode the frag ends. */ |
252b5132 RH |
215 | symbolS *fadd; |
216 | offsetT foff; | |
217 | int fragty; | |
218 | } | |
219 | fragb[4]; | |
220 | ||
36759679 | 221 | int nrel; /* Num of reloc strucs in use. */ |
252b5132 RH |
222 | struct |
223 | { | |
224 | int n; | |
225 | expressionS exp; | |
226 | char wid; | |
227 | char pcrel; | |
228 | /* In a pc relative address the difference between the address | |
229 | of the offset and the address that the offset is relative | |
230 | to. This depends on the addressing mode. Basically this | |
231 | is the value to put in the offset field to address the | |
232 | first byte of the offset, without regarding the special | |
233 | significance of some values (in the branch instruction, for | |
234 | example). */ | |
235 | int pcrel_fix; | |
236 | #ifdef OBJ_ELF | |
237 | /* Whether this expression needs special pic relocation, and if | |
238 | so, which. */ | |
239 | enum pic_relocation pic_reloc; | |
240 | #endif | |
241 | } | |
36759679 | 242 | reloc[5]; /* Five is enough??? */ |
252b5132 RH |
243 | }; |
244 | ||
6b6e92f4 | 245 | #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a)) |
252b5132 RH |
246 | #define float_of_arch(x) ((x) & mfloat) |
247 | #define mmu_of_arch(x) ((x) & mmmu) | |
6b6e92f4 NC |
248 | #define arch_coldfire_p(x) ((x) & mcfisa_a) |
249 | #define arch_coldfire_fpu(x) ((x) & cfloat) | |
252b5132 | 250 | |
36759679 | 251 | /* Macros for determining if cpu supports a specific addressing mode. */ |
6b6e92f4 | 252 | #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b)) |
252b5132 | 253 | |
36759679 | 254 | static struct m68k_it the_ins; /* The instruction being assembled. */ |
252b5132 RH |
255 | |
256 | #define op(ex) ((ex)->exp.X_op) | |
257 | #define adds(ex) ((ex)->exp.X_add_symbol) | |
258 | #define subs(ex) ((ex)->exp.X_op_symbol) | |
259 | #define offs(ex) ((ex)->exp.X_add_number) | |
260 | ||
36759679 | 261 | /* Macros for adding things to the m68k_it struct. */ |
31302357 | 262 | #define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) |
252b5132 | 263 | |
36759679 NC |
264 | /* Like addword, but goes BEFORE general operands. */ |
265 | ||
252b5132 | 266 | static void |
31302357 | 267 | insop (int w, const struct m68k_incant *opcode) |
252b5132 RH |
268 | { |
269 | int z; | |
07726851 | 270 | for (z = the_ins.numo; z > opcode->m_codenum; --z) |
8a104df9 KH |
271 | the_ins.opcode[z] = the_ins.opcode[z - 1]; |
272 | for (z = 0; z < the_ins.nrel; z++) | |
273 | the_ins.reloc[z].n += 2; | |
252b5132 RH |
274 | for (z = 0; z < the_ins.nfrag; z++) |
275 | the_ins.fragb[z].fragoff++; | |
8a104df9 | 276 | the_ins.opcode[opcode->m_codenum] = w; |
252b5132 RH |
277 | the_ins.numo++; |
278 | } | |
279 | ||
280 | /* The numo+1 kludge is so we can hit the low order byte of the prev word. | |
281 | Blecch. */ | |
282 | static void | |
31302357 | 283 | add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) |
252b5132 | 284 | { |
31302357 AS |
285 | the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' |
286 | ? the_ins.numo * 2 - 1 | |
287 | : (width == 'b' | |
288 | ? the_ins.numo * 2 + 1 | |
289 | : the_ins.numo * 2)); | |
252b5132 RH |
290 | the_ins.reloc[the_ins.nrel].exp = exp->exp; |
291 | the_ins.reloc[the_ins.nrel].wid = width; | |
292 | the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; | |
293 | #ifdef OBJ_ELF | |
294 | the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; | |
295 | #endif | |
296 | the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; | |
297 | } | |
298 | ||
299 | /* Cause an extra frag to be generated here, inserting up to 10 bytes | |
300 | (that value is chosen in the frag_var call in md_assemble). TYPE | |
301 | is the subtype of the frag to be generated; its primary type is | |
302 | rs_machine_dependent. | |
303 | ||
304 | The TYPE parameter is also used by md_convert_frag_1 and | |
305 | md_estimate_size_before_relax. The appropriate type of fixup will | |
306 | be emitted by md_convert_frag_1. | |
307 | ||
308 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ | |
309 | static void | |
31302357 | 310 | add_frag (symbolS *add, offsetT off, int type) |
252b5132 | 311 | { |
8a104df9 KH |
312 | the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; |
313 | the_ins.fragb[the_ins.nfrag].fadd = add; | |
314 | the_ins.fragb[the_ins.nfrag].foff = off; | |
315 | the_ins.fragb[the_ins.nfrag++].fragty = type; | |
252b5132 RH |
316 | } |
317 | ||
318 | #define isvar(ex) \ | |
319 | (op (ex) != O_constant && op (ex) != O_big) | |
320 | ||
31302357 AS |
321 | static char *crack_operand (char *str, struct m68k_op *opP); |
322 | static int get_num (struct m68k_exp *exp, int ok); | |
323 | static int reverse_16_bits (int in); | |
324 | static int reverse_8_bits (int in); | |
325 | static void install_gen_operand (int mode, int val); | |
326 | static void install_operand (int mode, int val); | |
327 | static void s_bss (int); | |
328 | static void s_data1 (int); | |
329 | static void s_data2 (int); | |
330 | static void s_even (int); | |
331 | static void s_proc (int); | |
332 | static void s_chip (int); | |
333 | static void s_fopt (int); | |
334 | static void s_opt (int); | |
335 | static void s_reg (int); | |
336 | static void s_restore (int); | |
337 | static void s_save (int); | |
338 | static void s_mri_if (int); | |
339 | static void s_mri_else (int); | |
340 | static void s_mri_endi (int); | |
341 | static void s_mri_break (int); | |
342 | static void s_mri_next (int); | |
343 | static void s_mri_for (int); | |
344 | static void s_mri_endf (int); | |
345 | static void s_mri_repeat (int); | |
346 | static void s_mri_until (int); | |
347 | static void s_mri_while (int); | |
348 | static void s_mri_endw (int); | |
252b5132 RH |
349 | |
350 | static int current_architecture; | |
6b6e92f4 | 351 | static int current_chip; |
252b5132 | 352 | |
dc84e067 NC |
353 | struct m68k_cpu |
354 | { | |
355 | unsigned long arch; | |
6b6e92f4 | 356 | unsigned long chip; |
dc84e067 NC |
357 | const char *name; |
358 | int alias; | |
359 | }; | |
252b5132 | 360 | |
dc84e067 NC |
361 | static const struct m68k_cpu archs[] = |
362 | { | |
6b6e92f4 NC |
363 | { m68000, m68000, "68000", 0 }, |
364 | { m68010, m68010, "68010", 0 }, | |
365 | { m68020, m68020, "68020", 0 }, | |
366 | { m68030, m68030, "68030", 0 }, | |
367 | { m68040, m68040, "68040", 0 }, | |
368 | { m68060, m68060, "68060", 0 }, | |
369 | { cpu32, cpu32, "cpu32", 0 }, | |
370 | { m68881, m68881, "68881", 0 }, | |
371 | { m68851, m68851, "68851", 0 }, | |
372 | { mcfisa_a, mcf5200, "5200", 0 }, | |
373 | { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 }, | |
374 | { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 }, | |
375 | { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 }, | |
376 | { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 }, | |
377 | { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 }, | |
378 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 }, | |
379 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 }, | |
380 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 }, | |
dc84e067 NC |
381 | /* Aliases (effectively, so far as gas is concerned) for the above |
382 | cpus. */ | |
6b6e92f4 NC |
383 | { m68020, m68020, "68k", 1 }, |
384 | { m68000, m68000, "68008", 1 }, | |
385 | { m68000, m68000, "68302", 1 }, | |
386 | { m68000, m68000, "68306", 1 }, | |
387 | { m68000, m68000, "68307", 1 }, | |
388 | { m68000, m68000, "68322", 1 }, | |
389 | { m68000, m68000, "68356", 1 }, | |
390 | { m68000, m68000, "68ec000", 1 }, | |
391 | { m68000, m68000, "68hc000", 1 }, | |
392 | { m68000, m68000, "68hc001", 1 }, | |
393 | { m68020, m68020, "68ec020", 1 }, | |
394 | { m68030, m68030, "68ec030", 1 }, | |
395 | { m68040, m68040, "68ec040", 1 }, | |
396 | { m68060, m68060, "68ec060", 1 }, | |
397 | { cpu32, cpu32, "68330", 1 }, | |
398 | { cpu32, cpu32, "68331", 1 }, | |
399 | { cpu32, cpu32, "68332", 1 }, | |
400 | { cpu32, cpu32, "68333", 1 }, | |
401 | { cpu32, cpu32, "68334", 1 }, | |
402 | { cpu32, cpu32, "68336", 1 }, | |
403 | { cpu32, cpu32, "68340", 1 }, | |
404 | { cpu32, cpu32, "68341", 1 }, | |
405 | { cpu32, cpu32, "68349", 1 }, | |
406 | { cpu32, cpu32, "68360", 1 }, | |
407 | { m68881, m68881, "68882", 1 }, | |
408 | { mcfisa_a, mcf5200, "5202", 1 }, | |
409 | { mcfisa_a, mcf5200, "5204", 1 }, | |
410 | { mcfisa_a, mcf5200, "5206", 1 }, | |
411 | { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 }, | |
412 | { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 }, | |
413 | { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 }, | |
414 | { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 }, | |
415 | { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 }, | |
416 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 }, | |
417 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 }, | |
418 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 }, | |
419 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 }, | |
420 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 }, | |
421 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 }, | |
422 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 }, | |
423 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 }, | |
424 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 }, | |
425 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 }, | |
426 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 }, | |
427 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 }, | |
428 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 }, | |
429 | { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 }, | |
dc84e067 | 430 | }; |
252b5132 RH |
431 | |
432 | static const int n_archs = sizeof (archs) / sizeof (archs[0]); | |
433 | ||
151337e8 NC |
434 | /* This is the assembler relaxation table for m68k. m68k is a rich CISC |
435 | architecture and we have a lot of relaxation modes. */ | |
252b5132 | 436 | |
151337e8 NC |
437 | /* Macros used in the relaxation code. */ |
438 | #define TAB(x,y) (((x) << 2) + (y)) | |
439 | #define TABTYPE(x) ((x) >> 2) | |
440 | ||
441 | /* Relaxation states. */ | |
442 | #define BYTE 0 | |
443 | #define SHORT 1 | |
444 | #define LONG 2 | |
445 | #define SZ_UNDEF 3 | |
446 | ||
447 | /* Here are all the relaxation modes we support. First we can relax ordinary | |
448 | branches. On 68020 and higher and on CPU32 all branch instructions take | |
449 | three forms, so on these CPUs all branches always remain as such. When we | |
450 | have to expand to the LONG form on a 68000, though, we substitute an | |
451 | absolute jump instead. This is a direct replacement for unconditional | |
452 | branches and a branch over a jump for conditional branches. However, if the | |
453 | user requires PIC and disables this with --pcrel, we can only relax between | |
454 | BYTE and SHORT forms, punting if that isn't enough. This gives us four | |
455 | different relaxation modes for branches: */ | |
456 | ||
36759679 NC |
457 | #define BRANCHBWL 0 /* Branch byte, word, or long. */ |
458 | #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ | |
459 | #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ | |
460 | #define BRANCHBW 3 /* Branch byte or word. */ | |
151337e8 NC |
461 | |
462 | /* We also relax coprocessor branches and DBcc's. All CPUs that support | |
463 | coprocessor branches support them in word and long forms, so we have only | |
464 | one relaxation mode for them. DBcc's are word only on all CPUs. We can | |
465 | relax them to the LONG form with a branch-around sequence. This sequence | |
466 | can use a long branch (if available) or an absolute jump (if acceptable). | |
467 | This gives us two relaxation modes. If long branches are not available and | |
468 | absolute jumps are not acceptable, we don't relax DBcc's. */ | |
469 | ||
36759679 NC |
470 | #define FBRANCH 4 /* Coprocessor branch. */ |
471 | #define DBCCLBR 5 /* DBcc relaxable with a long branch. */ | |
472 | #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ | |
151337e8 NC |
473 | |
474 | /* That's all for instruction relaxation. However, we also relax PC-relative | |
475 | operands. Specifically, we have three operand relaxation modes. On the | |
476 | 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and | |
477 | on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the | |
478 | two. Also PC+displacement+index operands in their simple form (with a non- | |
479 | suppressed index without memory indirection) are supported on all CPUs, but | |
480 | on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher | |
481 | and on CPU32 we relax it to SHORT and LONG forms as well using the extended | |
482 | form of the PC+displacement+index operand. Finally, some absolute operands | |
483 | can be relaxed down to 16-bit PC-relative. */ | |
484 | ||
36759679 NC |
485 | #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ |
486 | #define PCINDEX 8 /* PC + displacement + index. */ | |
487 | #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ | |
252b5132 RH |
488 | |
489 | /* Note that calls to frag_var need to specify the maximum expansion | |
490 | needed; this is currently 10 bytes for DBCC. */ | |
491 | ||
492 | /* The fields are: | |
493 | How far Forward this mode will reach: | |
494 | How far Backward this mode will reach: | |
495 | How many bytes this mode will add to the size of the frag | |
496 | Which mode to go to if the offset won't fit in this one | |
d7861ad2 AM |
497 | |
498 | Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ | |
252b5132 RH |
499 | relax_typeS md_relax_table[] = |
500 | { | |
ac62c346 AM |
501 | { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, |
502 | { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, | |
503 | { 0, 0, 4, 0 }, | |
504 | { 1, 1, 0, 0 }, | |
505 | ||
506 | { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, | |
507 | { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, | |
508 | { 0, 0, 4, 0 }, | |
509 | { 1, 1, 0, 0 }, | |
510 | ||
511 | { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, | |
512 | { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, | |
513 | { 0, 0, 6, 0 }, | |
514 | { 1, 1, 0, 0 }, | |
515 | ||
516 | { 127, -128, 0, TAB (BRANCHBW, SHORT) }, | |
517 | { 0, 0, 2, 0 }, | |
518 | { 1, 1, 0, 0 }, | |
519 | { 1, 1, 0, 0 }, | |
520 | ||
36759679 | 521 | { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ |
ac62c346 AM |
522 | { 32767, -32768, 2, TAB (FBRANCH, LONG) }, |
523 | { 0, 0, 4, 0 }, | |
524 | { 1, 1, 0, 0 }, | |
525 | ||
36759679 | 526 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ |
ac62c346 AM |
527 | { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, |
528 | { 0, 0, 10, 0 }, | |
529 | { 1, 1, 0, 0 }, | |
530 | ||
36759679 | 531 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ |
ac62c346 AM |
532 | { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, |
533 | { 0, 0, 10, 0 }, | |
534 | { 1, 1, 0, 0 }, | |
535 | ||
36759679 | 536 | { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ |
ac62c346 AM |
537 | { 32767, -32768, 2, TAB (PCREL1632, LONG) }, |
538 | { 0, 0, 6, 0 }, | |
539 | { 1, 1, 0, 0 }, | |
540 | ||
541 | { 125, -130, 0, TAB (PCINDEX, SHORT) }, | |
542 | { 32765, -32770, 2, TAB (PCINDEX, LONG) }, | |
543 | { 0, 0, 4, 0 }, | |
544 | { 1, 1, 0, 0 }, | |
545 | ||
36759679 | 546 | { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ |
ac62c346 AM |
547 | { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, |
548 | { 0, 0, 4, 0 }, | |
549 | { 1, 1, 0, 0 }, | |
252b5132 RH |
550 | }; |
551 | ||
552 | /* These are the machine dependent pseudo-ops. These are included so | |
553 | the assembler can work on the output from the SUN C compiler, which | |
36759679 | 554 | generates these. */ |
252b5132 RH |
555 | |
556 | /* This table describes all the machine specific pseudo-ops the assembler | |
557 | has to support. The fields are: | |
558 | pseudo-op name without dot | |
559 | function to call to execute this pseudo-op | |
36759679 | 560 | Integer arg to pass to the function. */ |
252b5132 RH |
561 | const pseudo_typeS md_pseudo_table[] = |
562 | { | |
563 | {"data1", s_data1, 0}, | |
564 | {"data2", s_data2, 0}, | |
565 | {"bss", s_bss, 0}, | |
566 | {"even", s_even, 0}, | |
567 | {"skip", s_space, 0}, | |
568 | {"proc", s_proc, 0}, | |
569 | #if defined (TE_SUN3) || defined (OBJ_ELF) | |
570 | {"align", s_align_bytes, 0}, | |
571 | #endif | |
572 | #ifdef OBJ_ELF | |
573 | {"swbeg", s_ignore, 0}, | |
574 | #endif | |
575 | {"extend", float_cons, 'x'}, | |
576 | {"ldouble", float_cons, 'x'}, | |
577 | ||
578 | /* The following pseudo-ops are supported for MRI compatibility. */ | |
579 | {"chip", s_chip, 0}, | |
580 | {"comline", s_space, 1}, | |
581 | {"fopt", s_fopt, 0}, | |
582 | {"mask2", s_ignore, 0}, | |
583 | {"opt", s_opt, 0}, | |
584 | {"reg", s_reg, 0}, | |
585 | {"restore", s_restore, 0}, | |
586 | {"save", s_save, 0}, | |
587 | ||
588 | {"if", s_mri_if, 0}, | |
589 | {"if.b", s_mri_if, 'b'}, | |
590 | {"if.w", s_mri_if, 'w'}, | |
591 | {"if.l", s_mri_if, 'l'}, | |
592 | {"else", s_mri_else, 0}, | |
593 | {"else.s", s_mri_else, 's'}, | |
594 | {"else.l", s_mri_else, 'l'}, | |
595 | {"endi", s_mri_endi, 0}, | |
596 | {"break", s_mri_break, 0}, | |
597 | {"break.s", s_mri_break, 's'}, | |
598 | {"break.l", s_mri_break, 'l'}, | |
599 | {"next", s_mri_next, 0}, | |
600 | {"next.s", s_mri_next, 's'}, | |
601 | {"next.l", s_mri_next, 'l'}, | |
602 | {"for", s_mri_for, 0}, | |
603 | {"for.b", s_mri_for, 'b'}, | |
604 | {"for.w", s_mri_for, 'w'}, | |
605 | {"for.l", s_mri_for, 'l'}, | |
606 | {"endf", s_mri_endf, 0}, | |
607 | {"repeat", s_mri_repeat, 0}, | |
608 | {"until", s_mri_until, 0}, | |
609 | {"until.b", s_mri_until, 'b'}, | |
610 | {"until.w", s_mri_until, 'w'}, | |
611 | {"until.l", s_mri_until, 'l'}, | |
612 | {"while", s_mri_while, 0}, | |
613 | {"while.b", s_mri_while, 'b'}, | |
614 | {"while.w", s_mri_while, 'w'}, | |
615 | {"while.l", s_mri_while, 'l'}, | |
616 | {"endw", s_mri_endw, 0}, | |
617 | ||
618 | {0, 0, 0} | |
619 | }; | |
620 | ||
252b5132 | 621 | /* The mote pseudo ops are put into the opcode table, since they |
31302357 | 622 | don't start with a . they look like opcodes to gas. */ |
252b5132 | 623 | |
5a38dc70 | 624 | const pseudo_typeS mote_pseudo_table[] = |
252b5132 RH |
625 | { |
626 | ||
627 | {"dcl", cons, 4}, | |
628 | {"dc", cons, 2}, | |
629 | {"dcw", cons, 2}, | |
630 | {"dcb", cons, 1}, | |
631 | ||
632 | {"dsl", s_space, 4}, | |
633 | {"ds", s_space, 2}, | |
634 | {"dsw", s_space, 2}, | |
635 | {"dsb", s_space, 1}, | |
636 | ||
637 | {"xdef", s_globl, 0}, | |
638 | #ifdef OBJ_ELF | |
639 | {"align", s_align_bytes, 0}, | |
640 | #else | |
641 | {"align", s_align_ptwo, 0}, | |
642 | #endif | |
643 | #ifdef M68KCOFF | |
644 | {"sect", obj_coff_section, 0}, | |
645 | {"section", obj_coff_section, 0}, | |
646 | #endif | |
647 | {0, 0, 0} | |
648 | }; | |
649 | ||
31302357 AS |
650 | #define issbyte(x) ((x) >= -128 && (x) <= 127) |
651 | #define isubyte(x) ((x) >= 0 && (x) <= 255) | |
652 | #define issword(x) ((x) >= -32768 && (x) <= 32767) | |
653 | #define isuword(x) ((x) >= 0 && (x) <= 65535) | |
252b5132 | 654 | |
31302357 AS |
655 | #define isbyte(x) ((x) >= -255 && (x) <= 255) |
656 | #define isword(x) ((x) >= -65536 && (x) <= 65535) | |
252b5132 RH |
657 | #define islong(x) (1) |
658 | ||
252b5132 RH |
659 | static char notend_table[256]; |
660 | static char alt_notend_table[256]; | |
661 | #define notend(s) \ | |
662 | (! (notend_table[(unsigned char) *s] \ | |
663 | || (*s == ':' \ | |
664 | && alt_notend_table[(unsigned char) s[1]]))) | |
665 | ||
6b6e92f4 NC |
666 | /* Return a human readable string holding the list of chips that are |
667 | valid for a particular architecture, suppressing aliases (unless | |
668 | there is only one of them). */ | |
669 | ||
670 | static char * | |
671 | find_cf_chip (int architecture) | |
672 | { | |
673 | static char buf[1024]; | |
674 | int i, j, n_chips, n_alias; | |
675 | char *cp; | |
676 | ||
677 | strcpy (buf, " ("); | |
678 | cp = buf + strlen (buf); | |
679 | ||
680 | for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i) | |
681 | if (archs[i].arch & architecture) | |
682 | { | |
683 | n_chips++; | |
684 | if (archs[i].alias) | |
685 | n_alias++; | |
686 | } | |
687 | ||
688 | if (n_chips == 0) | |
689 | as_fatal (_("no matching ColdFire architectures found")); | |
690 | ||
691 | if (n_alias > 1) | |
692 | n_chips -= n_alias; | |
693 | ||
694 | for (i = 0, j = 0; i < n_archs && j < n_chips; ++i) | |
695 | if (archs[i].arch & architecture) | |
696 | { | |
697 | if (j) | |
698 | { | |
31302357 | 699 | if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias) |
6b6e92f4 NC |
700 | { |
701 | if (n_chips == 2) | |
702 | { | |
703 | strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf))); | |
704 | cp += strlen (cp); | |
705 | } | |
706 | else | |
707 | { | |
708 | strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf))); | |
709 | cp += strlen (cp); | |
710 | } | |
711 | } | |
712 | else | |
713 | { | |
714 | strncpy (cp, ", ", (sizeof (buf) - (cp - buf))); | |
715 | cp += strlen (cp); | |
716 | } | |
717 | } | |
718 | strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf))); | |
719 | cp += strlen (cp); | |
720 | j++; | |
721 | } | |
722 | ||
723 | if (n_alias > 1) | |
724 | { | |
725 | strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf))); | |
726 | cp += strlen (cp); | |
727 | } | |
728 | ||
729 | strncpy (cp, ")", (sizeof (buf) - (cp - buf))); | |
730 | ||
731 | return buf; | |
732 | } | |
733 | ||
252b5132 RH |
734 | #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER) |
735 | ||
736 | #ifdef NO_PCREL_RELOCS | |
737 | ||
738 | int | |
31302357 | 739 | make_pcrel_absolute (fixS *fixP, long *add_number) |
252b5132 RH |
740 | { |
741 | register unsigned char *opcode = fixP->fx_frag->fr_opcode; | |
742 | ||
36759679 | 743 | /* Rewrite the PC relative instructions to absolute address ones. |
67c1ffbe | 744 | these are rumored to be faster, and the apollo linker refuses |
36759679 NC |
745 | to deal with the PC relative relocations. */ |
746 | if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */ | |
252b5132 | 747 | { |
36759679 | 748 | if (flag_keep_pcrel) |
6b6e92f4 | 749 | as_fatal (_("Tried to convert PC relative branch to absolute jump")); |
252b5132 RH |
750 | opcode[0] = 0x4e; |
751 | opcode[1] = 0xf9; | |
752 | } | |
36759679 | 753 | else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */ |
252b5132 | 754 | { |
36759679 | 755 | if (flag_keep_pcrel) |
6b6e92f4 | 756 | as_fatal (_("Tried to convert PC relative BSR to absolute JSR")); |
252b5132 RH |
757 | opcode[0] = 0x4e; |
758 | opcode[1] = 0xb9; | |
759 | } | |
760 | else | |
761 | as_fatal (_("Unknown PC relative instruction")); | |
762 | *add_number -= 4; | |
763 | return 0; | |
764 | } | |
765 | ||
766 | #endif /* NO_PCREL_RELOCS */ | |
767 | ||
768 | short | |
31302357 | 769 | tc_coff_fix2rtype (fixS *fixP) |
252b5132 RH |
770 | { |
771 | if (fixP->fx_tcbit && fixP->fx_size == 4) | |
772 | return R_RELLONG_NEG; | |
773 | #ifdef NO_PCREL_RELOCS | |
774 | know (fixP->fx_pcrel == 0); | |
775 | return (fixP->fx_size == 1 ? R_RELBYTE | |
776 | : fixP->fx_size == 2 ? R_DIR16 | |
777 | : R_DIR32); | |
778 | #else | |
31302357 AS |
779 | return (fixP->fx_pcrel |
780 | ? (fixP->fx_size == 1 ? R_PCRBYTE | |
781 | : fixP->fx_size == 2 ? R_PCRWORD | |
782 | : R_PCRLONG) | |
783 | : (fixP->fx_size == 1 ? R_RELBYTE | |
784 | : fixP->fx_size == 2 ? R_RELWORD | |
785 | : R_RELLONG)); | |
252b5132 RH |
786 | #endif |
787 | } | |
788 | ||
789 | #endif | |
790 | ||
791 | #ifdef OBJ_ELF | |
792 | ||
c801568a AM |
793 | /* Return zero if the reference to SYMBOL from within the same segment may |
794 | be relaxed. */ | |
795 | ||
796 | /* On an ELF system, we can't relax an externally visible symbol, | |
797 | because it may be overridden by a shared library. However, if | |
798 | TARGET_OS is "elf", then we presume that we are assembling for an | |
799 | embedded system, in which case we don't have to worry about shared | |
800 | libraries, and we can relax any external sym. */ | |
801 | ||
802 | #define relaxable_symbol(symbol) \ | |
6358301e | 803 | (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ |
c801568a AM |
804 | || S_IS_WEAK (symbol))) |
805 | ||
252b5132 RH |
806 | /* Compute the relocation code for a fixup of SIZE bytes, using pc |
807 | relative relocation if PCREL is non-zero. PIC says whether a special | |
808 | pic relocation was requested. */ | |
809 | ||
252b5132 | 810 | static bfd_reloc_code_real_type |
31302357 | 811 | get_reloc_code (int size, int pcrel, enum pic_relocation pic) |
252b5132 RH |
812 | { |
813 | switch (pic) | |
814 | { | |
815 | case pic_got_pcrel: | |
816 | switch (size) | |
817 | { | |
818 | case 1: | |
819 | return BFD_RELOC_8_GOT_PCREL; | |
820 | case 2: | |
821 | return BFD_RELOC_16_GOT_PCREL; | |
822 | case 4: | |
823 | return BFD_RELOC_32_GOT_PCREL; | |
824 | } | |
825 | break; | |
826 | ||
827 | case pic_got_off: | |
828 | switch (size) | |
829 | { | |
830 | case 1: | |
831 | return BFD_RELOC_8_GOTOFF; | |
832 | case 2: | |
833 | return BFD_RELOC_16_GOTOFF; | |
834 | case 4: | |
835 | return BFD_RELOC_32_GOTOFF; | |
836 | } | |
837 | break; | |
838 | ||
839 | case pic_plt_pcrel: | |
840 | switch (size) | |
841 | { | |
842 | case 1: | |
843 | return BFD_RELOC_8_PLT_PCREL; | |
844 | case 2: | |
845 | return BFD_RELOC_16_PLT_PCREL; | |
846 | case 4: | |
847 | return BFD_RELOC_32_PLT_PCREL; | |
848 | } | |
849 | break; | |
850 | ||
851 | case pic_plt_off: | |
852 | switch (size) | |
853 | { | |
854 | case 1: | |
855 | return BFD_RELOC_8_PLTOFF; | |
856 | case 2: | |
857 | return BFD_RELOC_16_PLTOFF; | |
858 | case 4: | |
859 | return BFD_RELOC_32_PLTOFF; | |
860 | } | |
861 | break; | |
862 | ||
863 | case pic_none: | |
864 | if (pcrel) | |
865 | { | |
866 | switch (size) | |
867 | { | |
868 | case 1: | |
869 | return BFD_RELOC_8_PCREL; | |
870 | case 2: | |
871 | return BFD_RELOC_16_PCREL; | |
872 | case 4: | |
873 | return BFD_RELOC_32_PCREL; | |
874 | } | |
875 | } | |
876 | else | |
877 | { | |
878 | switch (size) | |
879 | { | |
880 | case 1: | |
881 | return BFD_RELOC_8; | |
882 | case 2: | |
883 | return BFD_RELOC_16; | |
884 | case 4: | |
885 | return BFD_RELOC_32; | |
886 | } | |
887 | } | |
888 | } | |
889 | ||
890 | if (pcrel) | |
891 | { | |
892 | if (pic == pic_none) | |
893 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
894 | else | |
895 | as_bad (_("Can not do %d byte pc-relative pic relocation"), size); | |
896 | } | |
897 | else | |
898 | { | |
899 | if (pic == pic_none) | |
900 | as_bad (_("Can not do %d byte relocation"), size); | |
901 | else | |
902 | as_bad (_("Can not do %d byte pic relocation"), size); | |
903 | } | |
904 | ||
905 | return BFD_RELOC_NONE; | |
906 | } | |
907 | ||
908 | /* Here we decide which fixups can be adjusted to make them relative | |
909 | to the beginning of the section instead of the symbol. Basically | |
910 | we need to make sure that the dynamic relocations are done | |
911 | correctly, so in some cases we force the original symbol to be | |
912 | used. */ | |
913 | int | |
31302357 | 914 | tc_m68k_fix_adjustable (fixS *fixP) |
252b5132 | 915 | { |
36759679 | 916 | /* Adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
917 | switch (fixP->fx_r_type) |
918 | { | |
919 | case BFD_RELOC_8_GOT_PCREL: | |
920 | case BFD_RELOC_16_GOT_PCREL: | |
921 | case BFD_RELOC_32_GOT_PCREL: | |
922 | case BFD_RELOC_8_GOTOFF: | |
923 | case BFD_RELOC_16_GOTOFF: | |
924 | case BFD_RELOC_32_GOTOFF: | |
925 | case BFD_RELOC_8_PLT_PCREL: | |
926 | case BFD_RELOC_16_PLT_PCREL: | |
927 | case BFD_RELOC_32_PLT_PCREL: | |
928 | case BFD_RELOC_8_PLTOFF: | |
929 | case BFD_RELOC_16_PLTOFF: | |
930 | case BFD_RELOC_32_PLTOFF: | |
931 | return 0; | |
932 | ||
933 | case BFD_RELOC_VTABLE_INHERIT: | |
934 | case BFD_RELOC_VTABLE_ENTRY: | |
935 | return 0; | |
936 | ||
937 | default: | |
938 | return 1; | |
939 | } | |
940 | } | |
941 | ||
942 | #else /* !OBJ_ELF */ | |
943 | ||
944 | #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC | |
945 | ||
c801568a AM |
946 | #define relaxable_symbol(symbol) 1 |
947 | ||
252b5132 RH |
948 | #endif /* OBJ_ELF */ |
949 | ||
950 | #ifdef BFD_ASSEMBLER | |
951 | ||
952 | arelent * | |
31302357 | 953 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
954 | { |
955 | arelent *reloc; | |
956 | bfd_reloc_code_real_type code; | |
957 | ||
8ec6253e NC |
958 | /* If the tcbit is set, then this was a fixup of a negative value |
959 | that was never resolved. We do not have a reloc to handle this, | |
960 | so just return. We assume that other code will have detected this | |
961 | situation and produced a helpful error message, so we just tell the | |
962 | user that the reloc cannot be produced. */ | |
252b5132 | 963 | if (fixp->fx_tcbit) |
8ec6253e NC |
964 | { |
965 | if (fixp->fx_addsy) | |
b091f402 AM |
966 | as_bad_where (fixp->fx_file, fixp->fx_line, |
967 | _("Unable to produce reloc against symbol '%s'"), | |
968 | S_GET_NAME (fixp->fx_addsy)); | |
8ec6253e NC |
969 | return NULL; |
970 | } | |
252b5132 RH |
971 | |
972 | if (fixp->fx_r_type != BFD_RELOC_NONE) | |
973 | { | |
974 | code = fixp->fx_r_type; | |
975 | ||
976 | /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible | |
977 | that fixup_segment converted a non-PC relative reloc into a | |
978 | PC relative reloc. In such a case, we need to convert the | |
979 | reloc code. */ | |
980 | if (fixp->fx_pcrel) | |
981 | { | |
982 | switch (code) | |
983 | { | |
984 | case BFD_RELOC_8: | |
985 | code = BFD_RELOC_8_PCREL; | |
986 | break; | |
987 | case BFD_RELOC_16: | |
988 | code = BFD_RELOC_16_PCREL; | |
989 | break; | |
990 | case BFD_RELOC_32: | |
991 | code = BFD_RELOC_32_PCREL; | |
992 | break; | |
993 | case BFD_RELOC_8_PCREL: | |
994 | case BFD_RELOC_16_PCREL: | |
995 | case BFD_RELOC_32_PCREL: | |
996 | case BFD_RELOC_8_GOT_PCREL: | |
997 | case BFD_RELOC_16_GOT_PCREL: | |
998 | case BFD_RELOC_32_GOT_PCREL: | |
999 | case BFD_RELOC_8_GOTOFF: | |
1000 | case BFD_RELOC_16_GOTOFF: | |
1001 | case BFD_RELOC_32_GOTOFF: | |
1002 | case BFD_RELOC_8_PLT_PCREL: | |
1003 | case BFD_RELOC_16_PLT_PCREL: | |
1004 | case BFD_RELOC_32_PLT_PCREL: | |
1005 | case BFD_RELOC_8_PLTOFF: | |
1006 | case BFD_RELOC_16_PLTOFF: | |
1007 | case BFD_RELOC_32_PLTOFF: | |
1008 | break; | |
1009 | default: | |
1010 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1011 | _("Cannot make %s relocation PC relative"), | |
1012 | bfd_get_reloc_code_name (code)); | |
1013 | } | |
1014 | } | |
1015 | } | |
1016 | else | |
1017 | { | |
1018 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) | |
1019 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
1020 | { | |
1021 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
1022 | MAP (1, 0, BFD_RELOC_8); | |
1023 | MAP (2, 0, BFD_RELOC_16); | |
1024 | MAP (4, 0, BFD_RELOC_32); | |
1025 | MAP (1, 1, BFD_RELOC_8_PCREL); | |
1026 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
1027 | MAP (4, 1, BFD_RELOC_32_PCREL); | |
1028 | default: | |
1029 | abort (); | |
1030 | } | |
1031 | } | |
1032 | #undef F | |
1033 | #undef MAP | |
1034 | ||
1035 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
1036 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1037 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1038 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1039 | #ifndef OBJ_ELF | |
1040 | if (fixp->fx_pcrel) | |
1041 | reloc->addend = fixp->fx_addnumber; | |
1042 | else | |
1043 | reloc->addend = 0; | |
1044 | #else | |
1045 | if (!fixp->fx_pcrel) | |
1046 | reloc->addend = fixp->fx_addnumber; | |
1047 | else | |
1048 | reloc->addend = (section->vma | |
8390138c AS |
1049 | /* Explicit sign extension in case char is |
1050 | unsigned. */ | |
1051 | + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80 | |
252b5132 RH |
1052 | + fixp->fx_addnumber |
1053 | + md_pcrel_from (fixp)); | |
1054 | #endif | |
1055 | ||
1056 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
1057 | assert (reloc->howto != 0); | |
1058 | ||
1059 | return reloc; | |
1060 | } | |
1061 | ||
1062 | #endif /* BFD_ASSEMBLER */ | |
1063 | ||
252b5132 RH |
1064 | /* Handle of the OPCODE hash table. NULL means any use before |
1065 | m68k_ip_begin() will crash. */ | |
1066 | static struct hash_control *op_hash; | |
1067 | \f | |
1068 | /* Assemble an m68k instruction. */ | |
1069 | ||
1070 | static void | |
31302357 | 1071 | m68k_ip (char *instring) |
252b5132 RH |
1072 | { |
1073 | register char *p; | |
1074 | register struct m68k_op *opP; | |
1075 | register const struct m68k_incant *opcode; | |
1076 | register const char *s; | |
1077 | register int tmpreg = 0, baseo = 0, outro = 0, nextword; | |
1078 | char *pdot, *pdotmove; | |
1079 | enum m68k_size siz1, siz2; | |
1080 | char c; | |
1081 | int losing; | |
1082 | int opsfound; | |
1083 | LITTLENUM_TYPE words[6]; | |
1084 | LITTLENUM_TYPE *wordp; | |
1085 | unsigned long ok_arch = 0; | |
1086 | ||
1087 | if (*instring == ' ') | |
36759679 | 1088 | instring++; /* Skip leading whitespace. */ |
252b5132 RH |
1089 | |
1090 | /* Scan up to end of operation-code, which MUST end in end-of-string | |
92774660 | 1091 | or exactly 1 space. */ |
252b5132 RH |
1092 | pdot = 0; |
1093 | for (p = instring; *p != '\0'; p++) | |
1094 | { | |
1095 | if (*p == ' ') | |
1096 | break; | |
1097 | if (*p == '.') | |
1098 | pdot = p; | |
1099 | } | |
1100 | ||
1101 | if (p == instring) | |
1102 | { | |
1103 | the_ins.error = _("No operator"); | |
1104 | return; | |
1105 | } | |
1106 | ||
1107 | /* p now points to the end of the opcode name, probably whitespace. | |
1108 | Make sure the name is null terminated by clobbering the | |
1109 | whitespace, look it up in the hash table, then fix it back. | |
1110 | Remove a dot, first, since the opcode tables have none. */ | |
1111 | if (pdot != NULL) | |
1112 | { | |
1113 | for (pdotmove = pdot; pdotmove < p; pdotmove++) | |
1114 | *pdotmove = pdotmove[1]; | |
1115 | p--; | |
1116 | } | |
1117 | ||
1118 | c = *p; | |
1119 | *p = '\0'; | |
1120 | opcode = (const struct m68k_incant *) hash_find (op_hash, instring); | |
1121 | *p = c; | |
1122 | ||
1123 | if (pdot != NULL) | |
1124 | { | |
1125 | for (pdotmove = p; pdotmove > pdot; pdotmove--) | |
1126 | *pdotmove = pdotmove[-1]; | |
1127 | *pdot = '.'; | |
1128 | ++p; | |
1129 | } | |
1130 | ||
1131 | if (opcode == NULL) | |
1132 | { | |
1133 | the_ins.error = _("Unknown operator"); | |
1134 | return; | |
1135 | } | |
1136 | ||
36759679 | 1137 | /* Found a legitimate opcode, start matching operands. */ |
252b5132 RH |
1138 | while (*p == ' ') |
1139 | ++p; | |
1140 | ||
1141 | if (opcode->m_operands == 0) | |
1142 | { | |
1143 | char *old = input_line_pointer; | |
1144 | *old = '\n'; | |
1145 | input_line_pointer = p; | |
36759679 | 1146 | /* Ahh - it's a motorola style psuedo op. */ |
252b5132 RH |
1147 | mote_pseudo_table[opcode->m_opnum].poc_handler |
1148 | (mote_pseudo_table[opcode->m_opnum].poc_val); | |
1149 | input_line_pointer = old; | |
1150 | *old = 0; | |
1151 | ||
1152 | return; | |
1153 | } | |
1154 | ||
1155 | if (flag_mri && opcode->m_opnum == 0) | |
1156 | { | |
1157 | /* In MRI mode, random garbage is allowed after an instruction | |
1158 | which accepts no operands. */ | |
1159 | the_ins.args = opcode->m_operands; | |
1160 | the_ins.numargs = opcode->m_opnum; | |
1161 | the_ins.numo = opcode->m_codenum; | |
1162 | the_ins.opcode[0] = getone (opcode); | |
1163 | the_ins.opcode[1] = gettwo (opcode); | |
1164 | return; | |
1165 | } | |
1166 | ||
1167 | for (opP = &the_ins.operands[0]; *p; opP++) | |
1168 | { | |
1169 | p = crack_operand (p, opP); | |
1170 | ||
1171 | if (opP->error) | |
1172 | { | |
1173 | the_ins.error = opP->error; | |
1174 | return; | |
1175 | } | |
1176 | } | |
1177 | ||
1178 | opsfound = opP - &the_ins.operands[0]; | |
1179 | ||
1180 | /* This ugly hack is to support the floating pt opcodes in their | |
1181 | standard form. Essentially, we fake a first enty of type COP#1 */ | |
1182 | if (opcode->m_operands[0] == 'I') | |
1183 | { | |
1184 | int n; | |
1185 | ||
1186 | for (n = opsfound; n > 0; --n) | |
1187 | the_ins.operands[n] = the_ins.operands[n - 1]; | |
1188 | ||
31302357 | 1189 | memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); |
252b5132 RH |
1190 | the_ins.operands[0].mode = CONTROL; |
1191 | the_ins.operands[0].reg = m68k_float_copnum; | |
1192 | opsfound++; | |
1193 | } | |
1194 | ||
36759679 | 1195 | /* We've got the operands. Find an opcode that'll accept them. */ |
252b5132 RH |
1196 | for (losing = 0;;) |
1197 | { | |
1198 | /* If we didn't get the right number of ops, or we have no | |
92774660 | 1199 | common model with this pattern then reject this pattern. */ |
252b5132 RH |
1200 | |
1201 | ok_arch |= opcode->m_arch; | |
1202 | if (opsfound != opcode->m_opnum | |
1203 | || ((opcode->m_arch & current_architecture) == 0)) | |
1204 | ++losing; | |
1205 | else | |
1206 | { | |
1207 | for (s = opcode->m_operands, opP = &the_ins.operands[0]; | |
1208 | *s && !losing; | |
1209 | s += 2, opP++) | |
1210 | { | |
1211 | /* Warning: this switch is huge! */ | |
1212 | /* I've tried to organize the cases into this order: | |
1213 | non-alpha first, then alpha by letter. Lower-case | |
1214 | goes directly before uppercase counterpart. */ | |
1215 | /* Code with multiple case ...: gets sorted by the lowest | |
1216 | case ... it belongs to. I hope this makes sense. */ | |
1217 | switch (*s) | |
1218 | { | |
1219 | case '!': | |
1220 | switch (opP->mode) | |
1221 | { | |
1222 | case IMMED: | |
1223 | case DREG: | |
1224 | case AREG: | |
1225 | case FPREG: | |
1226 | case CONTROL: | |
1227 | case AINC: | |
1228 | case ADEC: | |
1229 | case REGLST: | |
1230 | losing++; | |
1231 | break; | |
1232 | default: | |
1233 | break; | |
1234 | } | |
1235 | break; | |
1236 | ||
1237 | case '<': | |
1238 | switch (opP->mode) | |
1239 | { | |
1240 | case DREG: | |
1241 | case AREG: | |
1242 | case FPREG: | |
1243 | case CONTROL: | |
1244 | case IMMED: | |
1245 | case ADEC: | |
1246 | case REGLST: | |
1247 | losing++; | |
1248 | break; | |
1249 | default: | |
1250 | break; | |
1251 | } | |
1252 | break; | |
1253 | ||
1254 | case '>': | |
1255 | switch (opP->mode) | |
1256 | { | |
1257 | case DREG: | |
1258 | case AREG: | |
1259 | case FPREG: | |
1260 | case CONTROL: | |
1261 | case IMMED: | |
1262 | case AINC: | |
1263 | case REGLST: | |
1264 | losing++; | |
1265 | break; | |
1266 | case ABSL: | |
1267 | break; | |
1268 | default: | |
1269 | if (opP->reg == PC | |
1270 | || opP->reg == ZPC) | |
1271 | losing++; | |
1272 | break; | |
1273 | } | |
1274 | break; | |
1275 | ||
1276 | case 'm': | |
1277 | switch (opP->mode) | |
1278 | { | |
1279 | case DREG: | |
1280 | case AREG: | |
1281 | case AINDR: | |
1282 | case AINC: | |
1283 | case ADEC: | |
1284 | break; | |
1285 | default: | |
1286 | losing++; | |
1287 | } | |
8a104df9 | 1288 | break; |
252b5132 RH |
1289 | |
1290 | case 'n': | |
1291 | switch (opP->mode) | |
1292 | { | |
1293 | case DISP: | |
1294 | break; | |
1295 | default: | |
1296 | losing++; | |
1297 | } | |
8a104df9 | 1298 | break; |
252b5132 RH |
1299 | |
1300 | case 'o': | |
1301 | switch (opP->mode) | |
1302 | { | |
1303 | case BASE: | |
1304 | case ABSL: | |
1305 | case IMMED: | |
1306 | break; | |
1307 | default: | |
1308 | losing++; | |
1309 | } | |
8a104df9 | 1310 | break; |
252b5132 RH |
1311 | |
1312 | case 'p': | |
1313 | switch (opP->mode) | |
1314 | { | |
1315 | case DREG: | |
1316 | case AREG: | |
1317 | case AINDR: | |
1318 | case AINC: | |
1319 | case ADEC: | |
1320 | break; | |
1321 | case DISP: | |
1322 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1323 | losing++; |
252b5132 RH |
1324 | break; |
1325 | default: | |
1326 | losing++; | |
1327 | } | |
8a104df9 | 1328 | break; |
252b5132 RH |
1329 | |
1330 | case 'q': | |
1331 | switch (opP->mode) | |
1332 | { | |
1333 | case DREG: | |
1334 | case AINDR: | |
1335 | case AINC: | |
1336 | case ADEC: | |
1337 | break; | |
1338 | case DISP: | |
1339 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1340 | losing++; |
252b5132 RH |
1341 | break; |
1342 | default: | |
1343 | losing++; | |
1344 | break; | |
1345 | } | |
8a104df9 | 1346 | break; |
252b5132 RH |
1347 | |
1348 | case 'v': | |
1349 | switch (opP->mode) | |
1350 | { | |
1351 | case DREG: | |
1352 | case AINDR: | |
1353 | case AINC: | |
1354 | case ADEC: | |
1355 | case ABSL: | |
1356 | break; | |
1357 | case DISP: | |
1358 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1359 | losing++; |
252b5132 RH |
1360 | break; |
1361 | default: | |
1362 | losing++; | |
1363 | break; | |
1364 | } | |
1365 | break; | |
1366 | ||
1367 | case '#': | |
1368 | if (opP->mode != IMMED) | |
1369 | losing++; | |
1370 | else if (s[1] == 'b' | |
1371 | && ! isvar (&opP->disp) | |
1372 | && (opP->disp.exp.X_op != O_constant | |
1373 | || ! isbyte (opP->disp.exp.X_add_number))) | |
1374 | losing++; | |
1375 | else if (s[1] == 'B' | |
1376 | && ! isvar (&opP->disp) | |
1377 | && (opP->disp.exp.X_op != O_constant | |
1378 | || ! issbyte (opP->disp.exp.X_add_number))) | |
1379 | losing++; | |
1380 | else if (s[1] == 'w' | |
1381 | && ! isvar (&opP->disp) | |
1382 | && (opP->disp.exp.X_op != O_constant | |
1383 | || ! isword (opP->disp.exp.X_add_number))) | |
1384 | losing++; | |
1385 | else if (s[1] == 'W' | |
1386 | && ! isvar (&opP->disp) | |
1387 | && (opP->disp.exp.X_op != O_constant | |
1388 | || ! issword (opP->disp.exp.X_add_number))) | |
1389 | losing++; | |
1390 | break; | |
1391 | ||
1392 | case '^': | |
1393 | case 'T': | |
1394 | if (opP->mode != IMMED) | |
1395 | losing++; | |
1396 | break; | |
1397 | ||
1398 | case '$': | |
1399 | if (opP->mode == AREG | |
1400 | || opP->mode == CONTROL | |
1401 | || opP->mode == FPREG | |
1402 | || opP->mode == IMMED | |
1403 | || opP->mode == REGLST | |
1404 | || (opP->mode != ABSL | |
1405 | && (opP->reg == PC | |
1406 | || opP->reg == ZPC))) | |
1407 | losing++; | |
1408 | break; | |
1409 | ||
1410 | case '%': | |
1411 | if (opP->mode == CONTROL | |
1412 | || opP->mode == FPREG | |
1413 | || opP->mode == REGLST | |
1414 | || opP->mode == IMMED | |
1415 | || (opP->mode != ABSL | |
1416 | && (opP->reg == PC | |
1417 | || opP->reg == ZPC))) | |
1418 | losing++; | |
1419 | break; | |
1420 | ||
1421 | case '&': | |
1422 | switch (opP->mode) | |
1423 | { | |
1424 | case DREG: | |
1425 | case AREG: | |
1426 | case FPREG: | |
1427 | case CONTROL: | |
1428 | case IMMED: | |
1429 | case AINC: | |
1430 | case ADEC: | |
1431 | case REGLST: | |
1432 | losing++; | |
1433 | break; | |
1434 | case ABSL: | |
1435 | break; | |
1436 | default: | |
1437 | if (opP->reg == PC | |
1438 | || opP->reg == ZPC) | |
1439 | losing++; | |
1440 | break; | |
1441 | } | |
1442 | break; | |
1443 | ||
1444 | case '*': | |
1445 | if (opP->mode == CONTROL | |
1446 | || opP->mode == FPREG | |
1447 | || opP->mode == REGLST) | |
1448 | losing++; | |
1449 | break; | |
1450 | ||
1451 | case '+': | |
1452 | if (opP->mode != AINC) | |
1453 | losing++; | |
1454 | break; | |
1455 | ||
1456 | case '-': | |
1457 | if (opP->mode != ADEC) | |
1458 | losing++; | |
1459 | break; | |
1460 | ||
1461 | case '/': | |
1462 | switch (opP->mode) | |
1463 | { | |
1464 | case AREG: | |
1465 | case CONTROL: | |
1466 | case FPREG: | |
1467 | case AINC: | |
1468 | case ADEC: | |
1469 | case IMMED: | |
1470 | case REGLST: | |
1471 | losing++; | |
1472 | break; | |
1473 | default: | |
1474 | break; | |
1475 | } | |
1476 | break; | |
1477 | ||
1478 | case ';': | |
1479 | switch (opP->mode) | |
1480 | { | |
1481 | case AREG: | |
1482 | case CONTROL: | |
1483 | case FPREG: | |
1484 | case REGLST: | |
1485 | losing++; | |
1486 | break; | |
1487 | default: | |
1488 | break; | |
1489 | } | |
1490 | break; | |
1491 | ||
1492 | case '?': | |
1493 | switch (opP->mode) | |
1494 | { | |
1495 | case AREG: | |
1496 | case CONTROL: | |
1497 | case FPREG: | |
1498 | case AINC: | |
1499 | case ADEC: | |
1500 | case IMMED: | |
1501 | case REGLST: | |
1502 | losing++; | |
1503 | break; | |
1504 | case ABSL: | |
1505 | break; | |
1506 | default: | |
1507 | if (opP->reg == PC || opP->reg == ZPC) | |
1508 | losing++; | |
1509 | break; | |
1510 | } | |
1511 | break; | |
1512 | ||
1513 | case '@': | |
1514 | switch (opP->mode) | |
1515 | { | |
1516 | case AREG: | |
1517 | case CONTROL: | |
1518 | case FPREG: | |
1519 | case IMMED: | |
1520 | case REGLST: | |
1521 | losing++; | |
1522 | break; | |
1523 | default: | |
1524 | break; | |
1525 | } | |
1526 | break; | |
1527 | ||
1528 | case '~': /* For now! (JF FOO is this right?) */ | |
1529 | switch (opP->mode) | |
1530 | { | |
1531 | case DREG: | |
1532 | case AREG: | |
1533 | case CONTROL: | |
1534 | case FPREG: | |
1535 | case IMMED: | |
1536 | case REGLST: | |
1537 | losing++; | |
1538 | break; | |
1539 | case ABSL: | |
1540 | break; | |
1541 | default: | |
1542 | if (opP->reg == PC | |
1543 | || opP->reg == ZPC) | |
1544 | losing++; | |
1545 | break; | |
1546 | } | |
1547 | break; | |
1548 | ||
1549 | case '3': | |
1550 | if (opP->mode != CONTROL | |
1551 | || (opP->reg != TT0 && opP->reg != TT1)) | |
1552 | losing++; | |
1553 | break; | |
1554 | ||
1555 | case 'A': | |
1556 | if (opP->mode != AREG) | |
1557 | losing++; | |
1558 | break; | |
1559 | ||
1560 | case 'a': | |
1561 | if (opP->mode != AINDR) | |
1562 | ++losing; | |
1563 | break; | |
1564 | ||
fd99574b NC |
1565 | case '4': |
1566 | if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC | |
1567 | && (opP->mode != DISP | |
1568 | || opP->reg < ADDR0 | |
1569 | || opP->reg > ADDR7)) | |
1570 | ++losing; | |
1571 | break; | |
1572 | ||
252b5132 RH |
1573 | case 'B': /* FOO */ |
1574 | if (opP->mode != ABSL | |
1575 | || (flag_long_jumps | |
1576 | && strncmp (instring, "jbsr", 4) == 0)) | |
1577 | losing++; | |
1578 | break; | |
1579 | ||
3e602632 NC |
1580 | case 'b': |
1581 | switch (opP->mode) | |
1582 | { | |
1583 | case IMMED: | |
1584 | case ABSL: | |
1585 | case AREG: | |
1586 | case FPREG: | |
1587 | case CONTROL: | |
1588 | case POST: | |
1589 | case PRE: | |
1590 | case REGLST: | |
1591 | losing++; | |
1592 | break; | |
1593 | default: | |
1594 | break; | |
1595 | } | |
1596 | break; | |
1597 | ||
252b5132 RH |
1598 | case 'C': |
1599 | if (opP->mode != CONTROL || opP->reg != CCR) | |
1600 | losing++; | |
1601 | break; | |
1602 | ||
1603 | case 'd': | |
1604 | if (opP->mode != DISP | |
1605 | || opP->reg < ADDR0 | |
1606 | || opP->reg > ADDR7) | |
1607 | losing++; | |
1608 | break; | |
1609 | ||
1610 | case 'D': | |
1611 | if (opP->mode != DREG) | |
1612 | losing++; | |
1613 | break; | |
1614 | ||
6da466c7 ILT |
1615 | case 'E': |
1616 | if (opP->reg != ACC) | |
1617 | losing++; | |
1618 | break; | |
1619 | ||
fd99574b NC |
1620 | case 'e': |
1621 | if (opP->reg != ACC && opP->reg != ACC1 | |
1622 | && opP->reg != ACC2 && opP->reg != ACC3) | |
1623 | losing++; | |
1624 | break; | |
1625 | ||
252b5132 RH |
1626 | case 'F': |
1627 | if (opP->mode != FPREG) | |
1628 | losing++; | |
1629 | break; | |
1630 | ||
6da466c7 ILT |
1631 | case 'G': |
1632 | if (opP->reg != MACSR) | |
1633 | losing++; | |
1634 | break; | |
1635 | ||
fd99574b NC |
1636 | case 'g': |
1637 | if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) | |
1638 | losing++; | |
1639 | break; | |
1640 | ||
6da466c7 ILT |
1641 | case 'H': |
1642 | if (opP->reg != MASK) | |
1643 | losing++; | |
1644 | break; | |
1645 | ||
252b5132 RH |
1646 | case 'I': |
1647 | if (opP->mode != CONTROL | |
1648 | || opP->reg < COP0 | |
1649 | || opP->reg > COP7) | |
1650 | losing++; | |
1651 | break; | |
1652 | ||
fd99574b NC |
1653 | case 'i': |
1654 | if (opP->mode != LSH && opP->mode != RSH) | |
1655 | losing++; | |
1656 | break; | |
1657 | ||
252b5132 RH |
1658 | case 'J': |
1659 | if (opP->mode != CONTROL | |
1660 | || opP->reg < USP | |
1661 | || opP->reg > last_movec_reg) | |
1662 | losing++; | |
1663 | else | |
1664 | { | |
1665 | const enum m68k_register *rp; | |
1666 | for (rp = control_regs; *rp; rp++) | |
1667 | if (*rp == opP->reg) | |
1668 | break; | |
1669 | if (*rp == 0) | |
1670 | losing++; | |
1671 | } | |
1672 | break; | |
1673 | ||
1674 | case 'k': | |
1675 | if (opP->mode != IMMED) | |
1676 | losing++; | |
1677 | break; | |
1678 | ||
1679 | case 'l': | |
1680 | case 'L': | |
1681 | if (opP->mode == DREG | |
1682 | || opP->mode == AREG | |
1683 | || opP->mode == FPREG) | |
1684 | { | |
1685 | if (s[1] == '8') | |
1686 | losing++; | |
1687 | else | |
1688 | { | |
1689 | switch (opP->mode) | |
1690 | { | |
1691 | case DREG: | |
1692 | opP->mask = 1 << (opP->reg - DATA0); | |
1693 | break; | |
1694 | case AREG: | |
1695 | opP->mask = 1 << (opP->reg - ADDR0 + 8); | |
1696 | break; | |
1697 | case FPREG: | |
1698 | opP->mask = 1 << (opP->reg - FP0 + 16); | |
1699 | break; | |
1700 | default: | |
1701 | abort (); | |
1702 | } | |
1703 | opP->mode = REGLST; | |
1704 | } | |
1705 | } | |
1706 | else if (opP->mode == CONTROL) | |
1707 | { | |
1708 | if (s[1] != '8') | |
1709 | losing++; | |
1710 | else | |
1711 | { | |
1712 | switch (opP->reg) | |
1713 | { | |
1714 | case FPI: | |
1715 | opP->mask = 1 << 24; | |
1716 | break; | |
1717 | case FPS: | |
1718 | opP->mask = 1 << 25; | |
1719 | break; | |
1720 | case FPC: | |
1721 | opP->mask = 1 << 26; | |
1722 | break; | |
1723 | default: | |
1724 | losing++; | |
1725 | break; | |
1726 | } | |
1727 | opP->mode = REGLST; | |
1728 | } | |
1729 | } | |
1730 | else if (opP->mode != REGLST) | |
1731 | losing++; | |
1732 | else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) | |
1733 | losing++; | |
1734 | else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) | |
1735 | losing++; | |
1736 | break; | |
1737 | ||
1738 | case 'M': | |
1739 | if (opP->mode != IMMED) | |
1740 | losing++; | |
1741 | else if (opP->disp.exp.X_op != O_constant | |
1742 | || ! issbyte (opP->disp.exp.X_add_number)) | |
1743 | losing++; | |
1744 | else if (! m68k_quick | |
1745 | && instring[3] != 'q' | |
1746 | && instring[4] != 'q') | |
1747 | losing++; | |
1748 | break; | |
1749 | ||
1750 | case 'O': | |
1751 | if (opP->mode != DREG | |
1752 | && opP->mode != IMMED | |
1753 | && opP->mode != ABSL) | |
1754 | losing++; | |
1755 | break; | |
1756 | ||
1757 | case 'Q': | |
1758 | if (opP->mode != IMMED) | |
1759 | losing++; | |
1760 | else if (opP->disp.exp.X_op != O_constant | |
1761 | || opP->disp.exp.X_add_number < 1 | |
1762 | || opP->disp.exp.X_add_number > 8) | |
1763 | losing++; | |
1764 | else if (! m68k_quick | |
1765 | && (strncmp (instring, "add", 3) == 0 | |
1766 | || strncmp (instring, "sub", 3) == 0) | |
1767 | && instring[3] != 'q') | |
1768 | losing++; | |
1769 | break; | |
1770 | ||
1771 | case 'R': | |
1772 | if (opP->mode != DREG && opP->mode != AREG) | |
1773 | losing++; | |
1774 | break; | |
1775 | ||
1776 | case 'r': | |
1777 | if (opP->mode != AINDR | |
1778 | && (opP->mode != BASE | |
1779 | || (opP->reg != 0 | |
1780 | && opP->reg != ZADDR0) | |
1781 | || opP->disp.exp.X_op != O_absent | |
1782 | || ((opP->index.reg < DATA0 | |
1783 | || opP->index.reg > DATA7) | |
1784 | && (opP->index.reg < ADDR0 | |
1785 | || opP->index.reg > ADDR7)) | |
1786 | || opP->index.size != SIZE_UNSPEC | |
1787 | || opP->index.scale != 1)) | |
1788 | losing++; | |
1789 | break; | |
1790 | ||
1791 | case 's': | |
1792 | if (opP->mode != CONTROL | |
1793 | || ! (opP->reg == FPI | |
1794 | || opP->reg == FPS | |
1795 | || opP->reg == FPC)) | |
1796 | losing++; | |
1797 | break; | |
1798 | ||
1799 | case 'S': | |
1800 | if (opP->mode != CONTROL || opP->reg != SR) | |
1801 | losing++; | |
1802 | break; | |
1803 | ||
1804 | case 't': | |
1805 | if (opP->mode != IMMED) | |
1806 | losing++; | |
1807 | else if (opP->disp.exp.X_op != O_constant | |
1808 | || opP->disp.exp.X_add_number < 0 | |
1809 | || opP->disp.exp.X_add_number > 7) | |
1810 | losing++; | |
1811 | break; | |
1812 | ||
1813 | case 'U': | |
1814 | if (opP->mode != CONTROL || opP->reg != USP) | |
1815 | losing++; | |
1816 | break; | |
1817 | ||
3e602632 NC |
1818 | case 'x': |
1819 | if (opP->mode != IMMED) | |
1820 | losing++; | |
1821 | else if (opP->disp.exp.X_op != O_constant | |
1822 | || opP->disp.exp.X_add_number < -1 | |
1823 | || opP->disp.exp.X_add_number > 7 | |
1824 | || opP->disp.exp.X_add_number == 0) | |
1825 | losing++; | |
1826 | break; | |
1827 | ||
252b5132 RH |
1828 | /* JF these are out of order. We could put them |
1829 | in order if we were willing to put up with | |
1830 | bunches of #ifdef m68851s in the code. | |
1831 | ||
1832 | Don't forget that you need these operands | |
1833 | to use 68030 MMU instructions. */ | |
1834 | #ifndef NO_68851 | |
36759679 | 1835 | /* Memory addressing mode used by pflushr. */ |
252b5132 RH |
1836 | case '|': |
1837 | if (opP->mode == CONTROL | |
1838 | || opP->mode == FPREG | |
1839 | || opP->mode == DREG | |
1840 | || opP->mode == AREG | |
1841 | || opP->mode == REGLST) | |
1842 | losing++; | |
1843 | /* We should accept immediate operands, but they | |
1844 | supposedly have to be quad word, and we don't | |
1845 | handle that. I would like to see what a Motorola | |
1846 | assembler does before doing something here. */ | |
1847 | if (opP->mode == IMMED) | |
1848 | losing++; | |
1849 | break; | |
1850 | ||
1851 | case 'f': | |
1852 | if (opP->mode != CONTROL | |
1853 | || (opP->reg != SFC && opP->reg != DFC)) | |
1854 | losing++; | |
1855 | break; | |
1856 | ||
1857 | case '0': | |
1858 | if (opP->mode != CONTROL || opP->reg != TC) | |
1859 | losing++; | |
1860 | break; | |
1861 | ||
1862 | case '1': | |
1863 | if (opP->mode != CONTROL || opP->reg != AC) | |
1864 | losing++; | |
1865 | break; | |
1866 | ||
1867 | case '2': | |
1868 | if (opP->mode != CONTROL | |
1869 | || (opP->reg != CAL | |
1870 | && opP->reg != VAL | |
1871 | && opP->reg != SCC)) | |
1872 | losing++; | |
1873 | break; | |
1874 | ||
1875 | case 'V': | |
1876 | if (opP->mode != CONTROL | |
1877 | || opP->reg != VAL) | |
1878 | losing++; | |
1879 | break; | |
1880 | ||
1881 | case 'W': | |
1882 | if (opP->mode != CONTROL | |
1883 | || (opP->reg != DRP | |
1884 | && opP->reg != SRP | |
1885 | && opP->reg != CRP)) | |
1886 | losing++; | |
1887 | break; | |
1888 | ||
3e602632 NC |
1889 | case 'w': |
1890 | switch (opP->mode) | |
1891 | { | |
1892 | case IMMED: | |
1893 | case ABSL: | |
1894 | case AREG: | |
1895 | case DREG: | |
1896 | case FPREG: | |
1897 | case CONTROL: | |
1898 | case POST: | |
1899 | case PRE: | |
1900 | case REGLST: | |
1901 | losing++; | |
1902 | break; | |
1903 | default: | |
1904 | break; | |
1905 | } | |
1906 | break; | |
1907 | ||
252b5132 RH |
1908 | case 'X': |
1909 | if (opP->mode != CONTROL | |
1910 | || (!(opP->reg >= BAD && opP->reg <= BAD + 7) | |
1911 | && !(opP->reg >= BAC && opP->reg <= BAC + 7))) | |
1912 | losing++; | |
1913 | break; | |
1914 | ||
1915 | case 'Y': | |
1916 | if (opP->mode != CONTROL || opP->reg != PSR) | |
1917 | losing++; | |
1918 | break; | |
1919 | ||
1920 | case 'Z': | |
1921 | if (opP->mode != CONTROL || opP->reg != PCSR) | |
1922 | losing++; | |
1923 | break; | |
1924 | #endif | |
1925 | case 'c': | |
1926 | if (opP->mode != CONTROL | |
1927 | || (opP->reg != NC | |
1928 | && opP->reg != IC | |
1929 | && opP->reg != DC | |
1930 | && opP->reg != BC)) | |
36759679 | 1931 | losing++; |
252b5132 RH |
1932 | break; |
1933 | ||
1934 | case '_': | |
1935 | if (opP->mode != ABSL) | |
1936 | ++losing; | |
1937 | break; | |
1938 | ||
6da466c7 ILT |
1939 | case 'u': |
1940 | if (opP->reg < DATA0L || opP->reg > ADDR7U) | |
1941 | losing++; | |
1942 | /* FIXME: kludge instead of fixing parser: | |
1943 | upper/lower registers are *not* CONTROL | |
92774660 | 1944 | registers, but ordinary ones. */ |
6da466c7 ILT |
1945 | if ((opP->reg >= DATA0L && opP->reg <= DATA7L) |
1946 | || (opP->reg >= DATA0U && opP->reg <= DATA7U)) | |
1947 | opP->mode = DREG; | |
1948 | else | |
1949 | opP->mode = AREG; | |
1950 | break; | |
1951 | ||
3e602632 NC |
1952 | case 'y': |
1953 | if (!(opP->mode == AINDR | |
31302357 AS |
1954 | || (opP->mode == DISP |
1955 | && !(opP->reg == PC || opP->reg == ZPC)))) | |
3e602632 NC |
1956 | losing++; |
1957 | break; | |
1958 | ||
1959 | case 'z': | |
1960 | if (!(opP->mode == AINDR || opP->mode == DISP)) | |
1961 | losing++; | |
1962 | break; | |
1963 | ||
252b5132 RH |
1964 | default: |
1965 | abort (); | |
36759679 | 1966 | } |
252b5132 RH |
1967 | |
1968 | if (losing) | |
1969 | break; | |
36759679 NC |
1970 | } |
1971 | } | |
252b5132 RH |
1972 | |
1973 | if (!losing) | |
36759679 | 1974 | break; |
252b5132 RH |
1975 | |
1976 | opcode = opcode->m_next; | |
1977 | ||
1978 | if (!opcode) | |
1979 | { | |
1980 | if (ok_arch | |
1981 | && !(ok_arch & current_architecture)) | |
1982 | { | |
1983 | char buf[200], *cp; | |
1984 | ||
6b6e92f4 | 1985 | strncpy (buf, |
31302357 AS |
1986 | _("invalid instruction for this architecture; needs "), |
1987 | sizeof (buf)); | |
252b5132 RH |
1988 | cp = buf + strlen (buf); |
1989 | switch (ok_arch) | |
1990 | { | |
6b6e92f4 | 1991 | case mcfisa_a: |
31302357 AS |
1992 | strncpy (cp, _("ColdFire ISA_A"), |
1993 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 | 1994 | cp += strlen (cp); |
31302357 AS |
1995 | strncpy (cp, find_cf_chip (ok_arch), |
1996 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 NC |
1997 | cp += strlen (cp); |
1998 | break; | |
1999 | case mcfhwdiv: | |
31302357 AS |
2000 | strncpy (cp, _("ColdFire hardware divide"), |
2001 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 | 2002 | cp += strlen (cp); |
31302357 AS |
2003 | strncpy (cp, find_cf_chip (ok_arch), |
2004 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 NC |
2005 | cp += strlen (cp); |
2006 | break; | |
2007 | case mcfisa_aa: | |
31302357 AS |
2008 | strncpy (cp, _("ColdFire ISA_A+"), |
2009 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 | 2010 | cp += strlen (cp); |
31302357 AS |
2011 | strncpy (cp, find_cf_chip (ok_arch), |
2012 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 NC |
2013 | cp += strlen (cp); |
2014 | break; | |
2015 | case mcfisa_b: | |
31302357 AS |
2016 | strncpy (cp, _("ColdFire ISA_B"), |
2017 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 | 2018 | cp += strlen (cp); |
31302357 AS |
2019 | strncpy (cp, find_cf_chip (ok_arch), |
2020 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 NC |
2021 | cp += strlen (cp); |
2022 | break; | |
3e602632 | 2023 | case cfloat: |
31302357 | 2024 | strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf)); |
6b6e92f4 | 2025 | cp += strlen (cp); |
31302357 AS |
2026 | strncpy (cp, find_cf_chip (ok_arch), |
2027 | sizeof (buf) - (cp - buf)); | |
6b6e92f4 | 2028 | cp += strlen (cp); |
3e602632 | 2029 | break; |
252b5132 RH |
2030 | case mfloat: |
2031 | strcpy (cp, _("fpu (68040, 68060 or 68881/68882)")); | |
2032 | break; | |
2033 | case mmmu: | |
2034 | strcpy (cp, _("mmu (68030 or 68851)")); | |
2035 | break; | |
2036 | case m68020up: | |
2037 | strcpy (cp, _("68020 or higher")); | |
2038 | break; | |
2039 | case m68000up: | |
2040 | strcpy (cp, _("68000 or higher")); | |
2041 | break; | |
2042 | case m68010up: | |
2043 | strcpy (cp, _("68010 or higher")); | |
2044 | break; | |
2045 | default: | |
2046 | { | |
2047 | int got_one = 0, idx; | |
6b6e92f4 NC |
2048 | |
2049 | for (idx = 0; idx < n_archs; idx++) | |
252b5132 RH |
2050 | { |
2051 | if ((archs[idx].arch & ok_arch) | |
2052 | && ! archs[idx].alias) | |
2053 | { | |
2054 | if (got_one) | |
2055 | { | |
2056 | strcpy (cp, " or "); | |
2057 | cp += strlen (cp); | |
2058 | } | |
2059 | got_one = 1; | |
2060 | strcpy (cp, archs[idx].name); | |
2061 | cp += strlen (cp); | |
2062 | } | |
2063 | } | |
2064 | } | |
2065 | } | |
2066 | cp = xmalloc (strlen (buf) + 1); | |
2067 | strcpy (cp, buf); | |
2068 | the_ins.error = cp; | |
2069 | } | |
2070 | else | |
2071 | the_ins.error = _("operands mismatch"); | |
2072 | return; | |
36759679 | 2073 | } |
252b5132 RH |
2074 | |
2075 | losing = 0; | |
2076 | } | |
2077 | ||
36759679 | 2078 | /* Now assemble it. */ |
252b5132 RH |
2079 | the_ins.args = opcode->m_operands; |
2080 | the_ins.numargs = opcode->m_opnum; | |
2081 | the_ins.numo = opcode->m_codenum; | |
2082 | the_ins.opcode[0] = getone (opcode); | |
2083 | the_ins.opcode[1] = gettwo (opcode); | |
2084 | ||
2085 | for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) | |
2086 | { | |
2087 | /* This switch is a doozy. | |
31302357 | 2088 | Watch the first step; its a big one! */ |
252b5132 RH |
2089 | switch (s[0]) |
2090 | { | |
2091 | ||
2092 | case '*': | |
2093 | case '~': | |
2094 | case '%': | |
2095 | case ';': | |
2096 | case '@': | |
2097 | case '!': | |
2098 | case '&': | |
2099 | case '$': | |
2100 | case '?': | |
2101 | case '/': | |
2102 | case '<': | |
2103 | case '>': | |
3e602632 | 2104 | case 'b': |
252b5132 RH |
2105 | case 'm': |
2106 | case 'n': | |
2107 | case 'o': | |
2108 | case 'p': | |
2109 | case 'q': | |
2110 | case 'v': | |
3e602632 NC |
2111 | case 'w': |
2112 | case 'y': | |
2113 | case 'z': | |
fd99574b | 2114 | case '4': |
252b5132 RH |
2115 | #ifndef NO_68851 |
2116 | case '|': | |
2117 | #endif | |
2118 | switch (opP->mode) | |
2119 | { | |
2120 | case IMMED: | |
2121 | tmpreg = 0x3c; /* 7.4 */ | |
2122 | if (strchr ("bwl", s[1])) | |
3e602632 | 2123 | nextword = get_num (&opP->disp, 90); |
252b5132 RH |
2124 | else |
2125 | nextword = get_num (&opP->disp, 0); | |
2126 | if (isvar (&opP->disp)) | |
2127 | add_fix (s[1], &opP->disp, 0, 0); | |
2128 | switch (s[1]) | |
2129 | { | |
2130 | case 'b': | |
2131 | if (!isbyte (nextword)) | |
2132 | opP->error = _("operand out of range"); | |
2133 | addword (nextword); | |
2134 | baseo = 0; | |
2135 | break; | |
2136 | case 'w': | |
2137 | if (!isword (nextword)) | |
2138 | opP->error = _("operand out of range"); | |
2139 | addword (nextword); | |
2140 | baseo = 0; | |
2141 | break; | |
2142 | case 'W': | |
2143 | if (!issword (nextword)) | |
2144 | opP->error = _("operand out of range"); | |
2145 | addword (nextword); | |
2146 | baseo = 0; | |
2147 | break; | |
2148 | case 'l': | |
2149 | addword (nextword >> 16); | |
2150 | addword (nextword); | |
2151 | baseo = 0; | |
2152 | break; | |
2153 | ||
2154 | case 'f': | |
2155 | baseo = 2; | |
2156 | outro = 8; | |
2157 | break; | |
2158 | case 'F': | |
2159 | baseo = 4; | |
2160 | outro = 11; | |
2161 | break; | |
2162 | case 'x': | |
2163 | baseo = 6; | |
2164 | outro = 15; | |
2165 | break; | |
2166 | case 'p': | |
2167 | baseo = 6; | |
2168 | outro = -1; | |
2169 | break; | |
2170 | default: | |
2171 | abort (); | |
2172 | } | |
2173 | if (!baseo) | |
2174 | break; | |
2175 | ||
36759679 | 2176 | /* We gotta put out some float. */ |
252b5132 RH |
2177 | if (op (&opP->disp) != O_big) |
2178 | { | |
2179 | valueT val; | |
2180 | int gencnt; | |
2181 | ||
2182 | /* Can other cases happen here? */ | |
2183 | if (op (&opP->disp) != O_constant) | |
2184 | abort (); | |
2185 | ||
2186 | val = (valueT) offs (&opP->disp); | |
2187 | gencnt = 0; | |
2188 | do | |
2189 | { | |
2190 | generic_bignum[gencnt] = (LITTLENUM_TYPE) val; | |
2191 | val >>= LITTLENUM_NUMBER_OF_BITS; | |
2192 | ++gencnt; | |
2193 | } | |
2194 | while (val != 0); | |
2195 | offs (&opP->disp) = gencnt; | |
2196 | } | |
2197 | if (offs (&opP->disp) > 0) | |
2198 | { | |
2199 | if (offs (&opP->disp) > baseo) | |
2200 | { | |
2201 | as_warn (_("Bignum too big for %c format; truncated"), | |
2202 | s[1]); | |
2203 | offs (&opP->disp) = baseo; | |
2204 | } | |
2205 | baseo -= offs (&opP->disp); | |
2206 | while (baseo--) | |
2207 | addword (0); | |
2208 | for (wordp = generic_bignum + offs (&opP->disp) - 1; | |
2209 | offs (&opP->disp)--; | |
2210 | --wordp) | |
2211 | addword (*wordp); | |
2212 | break; | |
2213 | } | |
2214 | gen_to_words (words, baseo, (long) outro); | |
2215 | for (wordp = words; baseo--; wordp++) | |
2216 | addword (*wordp); | |
2217 | break; | |
2218 | case DREG: | |
2219 | tmpreg = opP->reg - DATA; /* 0.dreg */ | |
2220 | break; | |
2221 | case AREG: | |
2222 | tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ | |
2223 | break; | |
2224 | case AINDR: | |
2225 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2226 | break; | |
2227 | case ADEC: | |
2228 | tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ | |
2229 | break; | |
2230 | case AINC: | |
2231 | tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ | |
2232 | break; | |
2233 | case DISP: | |
2234 | ||
3e602632 | 2235 | nextword = get_num (&opP->disp, 90); |
252b5132 | 2236 | |
580b9172 NC |
2237 | /* Convert mode 5 addressing with a zero offset into |
2238 | mode 2 addressing to reduce the instruction size by a | |
2239 | word. */ | |
2240 | if (! isvar (&opP->disp) | |
2241 | && (nextword == 0) | |
2242 | && (opP->disp.size == SIZE_UNSPEC) | |
2243 | && (opP->reg >= ADDR0) | |
2244 | && (opP->reg <= ADDR7)) | |
2245 | { | |
2246 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2247 | break; | |
2248 | } | |
2249 | ||
252b5132 RH |
2250 | if (opP->reg == PC |
2251 | && ! isvar (&opP->disp) | |
2252 | && m68k_abspcadd) | |
2253 | { | |
2254 | opP->disp.exp.X_op = O_symbol; | |
2255 | #ifndef BFD_ASSEMBLER | |
2256 | opP->disp.exp.X_add_symbol = &abs_symbol; | |
2257 | #else | |
2258 | opP->disp.exp.X_add_symbol = | |
2259 | section_symbol (absolute_section); | |
2260 | #endif | |
2261 | } | |
2262 | ||
36759679 | 2263 | /* Force into index mode. Hope this works. */ |
252b5132 RH |
2264 | |
2265 | /* We do the first bit for 32-bit displacements, and the | |
2266 | second bit for 16 bit ones. It is possible that we | |
2267 | should make the default be WORD instead of LONG, but | |
2268 | I think that'd break GCC, so we put up with a little | |
2269 | inefficiency for the sake of working output. */ | |
2270 | ||
2271 | if (!issword (nextword) | |
2272 | || (isvar (&opP->disp) | |
2273 | && ((opP->disp.size == SIZE_UNSPEC | |
2274 | && flag_short_refs == 0 | |
2275 | && cpu_of_arch (current_architecture) >= m68020 | |
6da466c7 | 2276 | && ! arch_coldfire_p (current_architecture)) |
252b5132 RH |
2277 | || opP->disp.size == SIZE_LONG))) |
2278 | { | |
2279 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2280 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
2281 | opP->error = |
2282 | _("displacement too large for this architecture; needs 68020 or higher"); | |
2283 | if (opP->reg == PC) | |
2284 | tmpreg = 0x3B; /* 7.3 */ | |
2285 | else | |
2286 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2287 | if (isvar (&opP->disp)) | |
2288 | { | |
2289 | if (opP->reg == PC) | |
2290 | { | |
2291 | if (opP->disp.size == SIZE_LONG | |
2292 | #ifdef OBJ_ELF | |
2293 | /* If the displacement needs pic | |
2294 | relocation it cannot be relaxed. */ | |
2295 | || opP->disp.pic_reloc != pic_none | |
2296 | #endif | |
2297 | ) | |
2298 | { | |
2299 | addword (0x0170); | |
2300 | add_fix ('l', &opP->disp, 1, 2); | |
2301 | } | |
2302 | else | |
2303 | { | |
2304 | add_frag (adds (&opP->disp), | |
2305 | offs (&opP->disp), | |
151337e8 | 2306 | TAB (PCREL1632, SZ_UNDEF)); |
252b5132 RH |
2307 | break; |
2308 | } | |
2309 | } | |
2310 | else | |
2311 | { | |
2312 | addword (0x0170); | |
2313 | add_fix ('l', &opP->disp, 0, 0); | |
2314 | } | |
2315 | } | |
2316 | else | |
2317 | addword (0x0170); | |
2318 | addword (nextword >> 16); | |
2319 | } | |
2320 | else | |
2321 | { | |
2322 | if (opP->reg == PC) | |
2323 | tmpreg = 0x3A; /* 7.2 */ | |
2324 | else | |
2325 | tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ | |
2326 | ||
2327 | if (isvar (&opP->disp)) | |
2328 | { | |
2329 | if (opP->reg == PC) | |
2330 | { | |
2331 | add_fix ('w', &opP->disp, 1, 0); | |
2332 | } | |
2333 | else | |
2334 | add_fix ('w', &opP->disp, 0, 0); | |
2335 | } | |
2336 | } | |
2337 | addword (nextword); | |
2338 | break; | |
2339 | ||
2340 | case POST: | |
2341 | case PRE: | |
2342 | case BASE: | |
2343 | nextword = 0; | |
3e602632 | 2344 | baseo = get_num (&opP->disp, 90); |
252b5132 | 2345 | if (opP->mode == POST || opP->mode == PRE) |
3e602632 | 2346 | outro = get_num (&opP->odisp, 90); |
252b5132 RH |
2347 | /* Figure out the `addressing mode'. |
2348 | Also turn on the BASE_DISABLE bit, if needed. */ | |
2349 | if (opP->reg == PC || opP->reg == ZPC) | |
2350 | { | |
2351 | tmpreg = 0x3b; /* 7.3 */ | |
2352 | if (opP->reg == ZPC) | |
2353 | nextword |= 0x80; | |
2354 | } | |
2355 | else if (opP->reg == 0) | |
2356 | { | |
2357 | nextword |= 0x80; | |
2358 | tmpreg = 0x30; /* 6.garbage */ | |
2359 | } | |
2360 | else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) | |
2361 | { | |
2362 | nextword |= 0x80; | |
2363 | tmpreg = 0x30 + opP->reg - ZADDR0; | |
2364 | } | |
2365 | else | |
2366 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2367 | ||
2368 | siz1 = opP->disp.size; | |
2369 | if (opP->mode == POST || opP->mode == PRE) | |
2370 | siz2 = opP->odisp.size; | |
2371 | else | |
2372 | siz2 = SIZE_UNSPEC; | |
2373 | ||
36759679 | 2374 | /* Index register stuff. */ |
252b5132 RH |
2375 | if (opP->index.reg != 0 |
2376 | && opP->index.reg >= DATA | |
2377 | && opP->index.reg <= ADDR7) | |
2378 | { | |
2379 | nextword |= (opP->index.reg - DATA) << 12; | |
2380 | ||
2381 | if (opP->index.size == SIZE_LONG | |
2382 | || (opP->index.size == SIZE_UNSPEC | |
2383 | && m68k_index_width_default == SIZE_LONG)) | |
2384 | nextword |= 0x800; | |
2385 | ||
92774660 | 2386 | if ((opP->index.scale != 1 |
252b5132 | 2387 | && cpu_of_arch (current_architecture) < m68020) |
92774660 | 2388 | || (opP->index.scale == 8 |
3e602632 | 2389 | && (arch_coldfire_p (current_architecture) |
6b6e92f4 | 2390 | && !arch_coldfire_fpu (current_architecture)))) |
252b5132 RH |
2391 | { |
2392 | opP->error = | |
2393 | _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); | |
2394 | } | |
2395 | ||
6da466c7 ILT |
2396 | if (arch_coldfire_p (current_architecture) |
2397 | && opP->index.size == SIZE_WORD) | |
2398 | opP->error = _("invalid index size for coldfire"); | |
2399 | ||
252b5132 RH |
2400 | switch (opP->index.scale) |
2401 | { | |
2402 | case 1: | |
2403 | break; | |
2404 | case 2: | |
2405 | nextword |= 0x200; | |
2406 | break; | |
2407 | case 4: | |
2408 | nextword |= 0x400; | |
2409 | break; | |
2410 | case 8: | |
2411 | nextword |= 0x600; | |
2412 | break; | |
2413 | default: | |
2414 | abort (); | |
2415 | } | |
2416 | /* IF its simple, | |
2417 | GET US OUT OF HERE! */ | |
2418 | ||
2419 | /* Must be INDEX, with an index register. Address | |
2420 | register cannot be ZERO-PC, and either :b was | |
2421 | forced, or we know it will fit. For a 68000 or | |
2422 | 68010, force this mode anyways, because the | |
2423 | larger modes aren't supported. */ | |
2424 | if (opP->mode == BASE | |
2425 | && ((opP->reg >= ADDR0 | |
2426 | && opP->reg <= ADDR7) | |
2427 | || opP->reg == PC)) | |
2428 | { | |
2429 | if (siz1 == SIZE_BYTE | |
2430 | || cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2431 | || arch_coldfire_p (current_architecture) |
252b5132 RH |
2432 | || (siz1 == SIZE_UNSPEC |
2433 | && ! isvar (&opP->disp) | |
2434 | && issbyte (baseo))) | |
2435 | { | |
2436 | nextword += baseo & 0xff; | |
2437 | addword (nextword); | |
2438 | if (isvar (&opP->disp)) | |
2439 | { | |
2440 | /* Do a byte relocation. If it doesn't | |
2441 | fit (possible on m68000) let the | |
2442 | fixup processing complain later. */ | |
2443 | if (opP->reg == PC) | |
2444 | add_fix ('B', &opP->disp, 1, 1); | |
2445 | else | |
2446 | add_fix ('B', &opP->disp, 0, 0); | |
2447 | } | |
2448 | else if (siz1 != SIZE_BYTE) | |
2449 | { | |
2450 | if (siz1 != SIZE_UNSPEC) | |
2451 | as_warn (_("Forcing byte displacement")); | |
2452 | if (! issbyte (baseo)) | |
2453 | opP->error = _("byte displacement out of range"); | |
2454 | } | |
2455 | ||
2456 | break; | |
2457 | } | |
2458 | else if (siz1 == SIZE_UNSPEC | |
2459 | && opP->reg == PC | |
2460 | && isvar (&opP->disp) | |
2461 | && subs (&opP->disp) == NULL | |
2462 | #ifdef OBJ_ELF | |
2463 | /* If the displacement needs pic | |
2464 | relocation it cannot be relaxed. */ | |
2465 | && opP->disp.pic_reloc == pic_none | |
2466 | #endif | |
2467 | ) | |
2468 | { | |
2469 | /* The code in md_convert_frag_1 needs to be | |
2470 | able to adjust nextword. Call frag_grow | |
2471 | to ensure that we have enough space in | |
2472 | the frag obstack to make all the bytes | |
2473 | contiguous. */ | |
2474 | frag_grow (14); | |
8a104df9 KH |
2475 | nextword += baseo & 0xff; |
2476 | addword (nextword); | |
2477 | add_frag (adds (&opP->disp), offs (&opP->disp), | |
2478 | TAB (PCINDEX, SZ_UNDEF)); | |
252b5132 RH |
2479 | |
2480 | break; | |
8a104df9 | 2481 | } |
252b5132 RH |
2482 | } |
2483 | } | |
2484 | else | |
2485 | { | |
36759679 | 2486 | nextword |= 0x40; /* No index reg. */ |
252b5132 RH |
2487 | if (opP->index.reg >= ZDATA0 |
2488 | && opP->index.reg <= ZDATA7) | |
2489 | nextword |= (opP->index.reg - ZDATA0) << 12; | |
2490 | else if (opP->index.reg >= ZADDR0 | |
2491 | || opP->index.reg <= ZADDR7) | |
2492 | nextword |= (opP->index.reg - ZADDR0 + 8) << 12; | |
2493 | } | |
2494 | ||
2495 | /* It isn't simple. */ | |
2496 | ||
2497 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2498 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
2499 | opP->error = |
2500 | _("invalid operand mode for this architecture; needs 68020 or higher"); | |
2501 | ||
2502 | nextword |= 0x100; | |
2503 | /* If the guy specified a width, we assume that it is | |
2504 | wide enough. Maybe it isn't. If so, we lose. */ | |
2505 | switch (siz1) | |
2506 | { | |
2507 | case SIZE_UNSPEC: | |
2508 | if (isvar (&opP->disp) | |
2509 | ? m68k_rel32 | |
2510 | : ! issword (baseo)) | |
2511 | { | |
2512 | siz1 = SIZE_LONG; | |
2513 | nextword |= 0x30; | |
2514 | } | |
2515 | else if (! isvar (&opP->disp) && baseo == 0) | |
2516 | nextword |= 0x10; | |
2517 | else | |
2518 | { | |
2519 | nextword |= 0x20; | |
2520 | siz1 = SIZE_WORD; | |
2521 | } | |
2522 | break; | |
2523 | case SIZE_BYTE: | |
2524 | as_warn (_(":b not permitted; defaulting to :w")); | |
2525 | /* Fall through. */ | |
2526 | case SIZE_WORD: | |
2527 | nextword |= 0x20; | |
2528 | break; | |
2529 | case SIZE_LONG: | |
2530 | nextword |= 0x30; | |
2531 | break; | |
2532 | } | |
2533 | ||
67c1ffbe | 2534 | /* Figure out inner displacement stuff. */ |
252b5132 RH |
2535 | if (opP->mode == POST || opP->mode == PRE) |
2536 | { | |
2537 | if (cpu_of_arch (current_architecture) & cpu32) | |
2538 | opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); | |
2539 | switch (siz2) | |
2540 | { | |
2541 | case SIZE_UNSPEC: | |
2542 | if (isvar (&opP->odisp) | |
2543 | ? m68k_rel32 | |
2544 | : ! issword (outro)) | |
2545 | { | |
2546 | siz2 = SIZE_LONG; | |
2547 | nextword |= 0x3; | |
2548 | } | |
2549 | else if (! isvar (&opP->odisp) && outro == 0) | |
2550 | nextword |= 0x1; | |
2551 | else | |
2552 | { | |
2553 | nextword |= 0x2; | |
2554 | siz2 = SIZE_WORD; | |
2555 | } | |
2556 | break; | |
2557 | case 1: | |
2558 | as_warn (_(":b not permitted; defaulting to :w")); | |
2559 | /* Fall through. */ | |
2560 | case 2: | |
2561 | nextword |= 0x2; | |
2562 | break; | |
2563 | case 3: | |
2564 | nextword |= 0x3; | |
2565 | break; | |
2566 | } | |
2567 | if (opP->mode == POST | |
2568 | && (nextword & 0x40) == 0) | |
2569 | nextword |= 0x04; | |
2570 | } | |
2571 | addword (nextword); | |
2572 | ||
2573 | if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) | |
2574 | { | |
2575 | if (opP->reg == PC || opP->reg == ZPC) | |
2576 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); | |
2577 | else | |
2578 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); | |
2579 | } | |
2580 | if (siz1 == SIZE_LONG) | |
2581 | addword (baseo >> 16); | |
2582 | if (siz1 != SIZE_UNSPEC) | |
2583 | addword (baseo); | |
2584 | ||
2585 | if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) | |
2586 | add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); | |
2587 | if (siz2 == SIZE_LONG) | |
2588 | addword (outro >> 16); | |
2589 | if (siz2 != SIZE_UNSPEC) | |
2590 | addword (outro); | |
2591 | ||
2592 | break; | |
2593 | ||
2594 | case ABSL: | |
3e602632 | 2595 | nextword = get_num (&opP->disp, 90); |
252b5132 RH |
2596 | switch (opP->disp.size) |
2597 | { | |
2598 | default: | |
2599 | abort (); | |
2600 | case SIZE_UNSPEC: | |
2601 | if (!isvar (&opP->disp) && issword (offs (&opP->disp))) | |
2602 | { | |
2603 | tmpreg = 0x38; /* 7.0 */ | |
2604 | addword (nextword); | |
2605 | break; | |
2606 | } | |
252b5132 RH |
2607 | if (isvar (&opP->disp) |
2608 | && !subs (&opP->disp) | |
2609 | && adds (&opP->disp) | |
2610 | #ifdef OBJ_ELF | |
2611 | /* If the displacement needs pic relocation it | |
2612 | cannot be relaxed. */ | |
2613 | && opP->disp.pic_reloc == pic_none | |
2614 | #endif | |
252b5132 RH |
2615 | && !flag_long_jumps |
2616 | && !strchr ("~%&$?", s[0])) | |
2617 | { | |
2618 | tmpreg = 0x3A; /* 7.2 */ | |
2619 | add_frag (adds (&opP->disp), | |
2620 | offs (&opP->disp), | |
151337e8 | 2621 | TAB (ABSTOPCREL, SZ_UNDEF)); |
252b5132 RH |
2622 | break; |
2623 | } | |
36759679 | 2624 | /* Fall through into long. */ |
252b5132 RH |
2625 | case SIZE_LONG: |
2626 | if (isvar (&opP->disp)) | |
2627 | add_fix ('l', &opP->disp, 0, 0); | |
2628 | ||
2629 | tmpreg = 0x39;/* 7.1 mode */ | |
2630 | addword (nextword >> 16); | |
2631 | addword (nextword); | |
2632 | break; | |
2633 | ||
2634 | case SIZE_BYTE: | |
2635 | as_bad (_("unsupported byte value; use a different suffix")); | |
2636 | /* Fall through. */ | |
36759679 NC |
2637 | |
2638 | case SIZE_WORD: | |
252b5132 RH |
2639 | if (isvar (&opP->disp)) |
2640 | add_fix ('w', &opP->disp, 0, 0); | |
2641 | ||
2642 | tmpreg = 0x38;/* 7.0 mode */ | |
2643 | addword (nextword); | |
2644 | break; | |
2645 | } | |
2646 | break; | |
2647 | case CONTROL: | |
2648 | case FPREG: | |
2649 | default: | |
2650 | as_bad (_("unknown/incorrect operand")); | |
bc805888 | 2651 | /* abort (); */ |
252b5132 | 2652 | } |
fd99574b NC |
2653 | |
2654 | /* If s[0] is '4', then this is for the mac instructions | |
2655 | that can have a trailing_ampersand set. If so, set 0x100 | |
2656 | bit on tmpreg so install_gen_operand can check for it and | |
2657 | set the appropriate bit (word2, bit 5). */ | |
2658 | if (s[0] == '4') | |
2659 | { | |
2660 | if (opP->trailing_ampersand) | |
2661 | tmpreg |= 0x100; | |
2662 | } | |
252b5132 RH |
2663 | install_gen_operand (s[1], tmpreg); |
2664 | break; | |
2665 | ||
2666 | case '#': | |
2667 | case '^': | |
2668 | switch (s[1]) | |
2669 | { /* JF: I hate floating point! */ | |
2670 | case 'j': | |
2671 | tmpreg = 70; | |
2672 | break; | |
2673 | case '8': | |
2674 | tmpreg = 20; | |
2675 | break; | |
2676 | case 'C': | |
2677 | tmpreg = 50; | |
2678 | break; | |
2679 | case '3': | |
2680 | default: | |
3e602632 | 2681 | tmpreg = 90; |
252b5132 RH |
2682 | break; |
2683 | } | |
2684 | tmpreg = get_num (&opP->disp, tmpreg); | |
2685 | if (isvar (&opP->disp)) | |
2686 | add_fix (s[1], &opP->disp, 0, 0); | |
2687 | switch (s[1]) | |
2688 | { | |
2689 | case 'b': /* Danger: These do no check for | |
2690 | certain types of overflow. | |
2691 | user beware! */ | |
2692 | if (!isbyte (tmpreg)) | |
2693 | opP->error = _("out of range"); | |
2694 | insop (tmpreg, opcode); | |
2695 | if (isvar (&opP->disp)) | |
2696 | the_ins.reloc[the_ins.nrel - 1].n = | |
2697 | (opcode->m_codenum) * 2 + 1; | |
2698 | break; | |
2699 | case 'B': | |
2700 | if (!issbyte (tmpreg)) | |
2701 | opP->error = _("out of range"); | |
2702 | the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; | |
2703 | if (isvar (&opP->disp)) | |
2704 | the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; | |
2705 | break; | |
2706 | case 'w': | |
2707 | if (!isword (tmpreg)) | |
2708 | opP->error = _("out of range"); | |
2709 | insop (tmpreg, opcode); | |
2710 | if (isvar (&opP->disp)) | |
2711 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2712 | break; | |
2713 | case 'W': | |
2714 | if (!issword (tmpreg)) | |
2715 | opP->error = _("out of range"); | |
2716 | insop (tmpreg, opcode); | |
2717 | if (isvar (&opP->disp)) | |
2718 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2719 | break; | |
2720 | case 'l': | |
2721 | /* Because of the way insop works, we put these two out | |
2722 | backwards. */ | |
2723 | insop (tmpreg, opcode); | |
2724 | insop (tmpreg >> 16, opcode); | |
2725 | if (isvar (&opP->disp)) | |
2726 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2727 | break; | |
2728 | case '3': | |
2729 | tmpreg &= 0xFF; | |
2730 | case '8': | |
2731 | case 'C': | |
2732 | case 'j': | |
2733 | install_operand (s[1], tmpreg); | |
2734 | break; | |
2735 | default: | |
2736 | abort (); | |
2737 | } | |
2738 | break; | |
2739 | ||
2740 | case '+': | |
2741 | case '-': | |
2742 | case 'A': | |
2743 | case 'a': | |
2744 | install_operand (s[1], opP->reg - ADDR); | |
2745 | break; | |
2746 | ||
2747 | case 'B': | |
3e602632 | 2748 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
2749 | switch (s[1]) |
2750 | { | |
2751 | case 'B': | |
8390138c | 2752 | add_fix ('B', &opP->disp, 1, -1); |
252b5132 RH |
2753 | break; |
2754 | case 'W': | |
2755 | add_fix ('w', &opP->disp, 1, 0); | |
2756 | addword (0); | |
2757 | break; | |
2758 | case 'L': | |
2759 | long_branch: | |
151337e8 | 2760 | if (! HAVE_LONG_BRANCH (current_architecture)) |
81d4177b | 2761 | as_warn (_("Can't use long branches on 68000/68010/5200")); |
151337e8 | 2762 | the_ins.opcode[0] |= 0xff; |
252b5132 RH |
2763 | add_fix ('l', &opP->disp, 1, 0); |
2764 | addword (0); | |
2765 | addword (0); | |
2766 | break; | |
2767 | case 'g': | |
36759679 | 2768 | if (subs (&opP->disp)) /* We can't relax it. */ |
252b5132 RH |
2769 | goto long_branch; |
2770 | ||
2771 | #ifdef OBJ_ELF | |
2772 | /* If the displacement needs pic relocation it cannot be | |
2773 | relaxed. */ | |
2774 | if (opP->disp.pic_reloc != pic_none) | |
2775 | goto long_branch; | |
2776 | #endif | |
252b5132 | 2777 | /* This could either be a symbol, or an absolute |
151337e8 NC |
2778 | address. If it's an absolute address, turn it into |
2779 | an absolute jump right here and keep it out of the | |
2780 | relaxer. */ | |
2781 | if (adds (&opP->disp) == 0) | |
2782 | { | |
2783 | if (the_ins.opcode[0] == 0x6000) /* jbra */ | |
18566f55 | 2784 | the_ins.opcode[0] = 0x4EF9; |
151337e8 | 2785 | else if (the_ins.opcode[0] == 0x6100) /* jbsr */ |
18566f55 | 2786 | the_ins.opcode[0] = 0x4EB9; |
151337e8 NC |
2787 | else /* jCC */ |
2788 | { | |
2789 | the_ins.opcode[0] ^= 0x0100; | |
2790 | the_ins.opcode[0] |= 0x0006; | |
18566f55 | 2791 | addword (0x4EF9); |
151337e8 NC |
2792 | } |
2793 | add_fix ('l', &opP->disp, 0, 0); | |
2794 | addword (0); | |
2795 | addword (0); | |
2796 | break; | |
2797 | } | |
2798 | ||
2799 | /* Now we know it's going into the relaxer. Now figure | |
2800 | out which mode. We try in this order of preference: | |
2801 | long branch, absolute jump, byte/word branches only. */ | |
2802 | if (HAVE_LONG_BRANCH (current_architecture)) | |
252b5132 | 2803 | add_frag (adds (&opP->disp), offs (&opP->disp), |
151337e8 NC |
2804 | TAB (BRANCHBWL, SZ_UNDEF)); |
2805 | else if (! flag_keep_pcrel) | |
2806 | { | |
2807 | if ((the_ins.opcode[0] == 0x6000) | |
2808 | || (the_ins.opcode[0] == 0x6100)) | |
2809 | add_frag (adds (&opP->disp), offs (&opP->disp), | |
2810 | TAB (BRABSJUNC, SZ_UNDEF)); | |
2811 | else | |
2812 | add_frag (adds (&opP->disp), offs (&opP->disp), | |
2813 | TAB (BRABSJCOND, SZ_UNDEF)); | |
2814 | } | |
252b5132 RH |
2815 | else |
2816 | add_frag (adds (&opP->disp), offs (&opP->disp), | |
151337e8 | 2817 | TAB (BRANCHBW, SZ_UNDEF)); |
252b5132 RH |
2818 | break; |
2819 | case 'w': | |
2820 | if (isvar (&opP->disp)) | |
2821 | { | |
151337e8 NC |
2822 | /* Check for DBcc instructions. We can relax them, |
2823 | but only if we have long branches and/or absolute | |
2824 | jumps. */ | |
2825 | if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) | |
2826 | && (HAVE_LONG_BRANCH (current_architecture) | |
2827 | || (! flag_keep_pcrel))) | |
252b5132 | 2828 | { |
151337e8 NC |
2829 | if (HAVE_LONG_BRANCH (current_architecture)) |
2830 | add_frag (adds (&opP->disp), offs (&opP->disp), | |
2831 | TAB (DBCCLBR, SZ_UNDEF)); | |
2832 | else | |
2833 | add_frag (adds (&opP->disp), offs (&opP->disp), | |
2834 | TAB (DBCCABSJ, SZ_UNDEF)); | |
252b5132 RH |
2835 | break; |
2836 | } | |
252b5132 RH |
2837 | add_fix ('w', &opP->disp, 1, 0); |
2838 | } | |
2839 | addword (0); | |
2840 | break; | |
36759679 | 2841 | case 'C': /* Fixed size LONG coproc branches. */ |
252b5132 RH |
2842 | add_fix ('l', &opP->disp, 1, 0); |
2843 | addword (0); | |
2844 | addword (0); | |
2845 | break; | |
36759679 | 2846 | case 'c': /* Var size Coprocesssor branches. */ |
151337e8 | 2847 | if (subs (&opP->disp) || (adds (&opP->disp) == 0)) |
252b5132 | 2848 | { |
252b5132 RH |
2849 | the_ins.opcode[the_ins.numo - 1] |= 0x40; |
2850 | add_fix ('l', &opP->disp, 1, 0); | |
2851 | addword (0); | |
2852 | addword (0); | |
2853 | } | |
151337e8 NC |
2854 | else |
2855 | add_frag (adds (&opP->disp), offs (&opP->disp), | |
2856 | TAB (FBRANCH, SZ_UNDEF)); | |
252b5132 RH |
2857 | break; |
2858 | default: | |
2859 | abort (); | |
2860 | } | |
2861 | break; | |
2862 | ||
36759679 | 2863 | case 'C': /* Ignore it. */ |
252b5132 RH |
2864 | break; |
2865 | ||
36759679 | 2866 | case 'd': /* JF this is a kludge. */ |
252b5132 | 2867 | install_operand ('s', opP->reg - ADDR); |
3e602632 | 2868 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
2869 | if (!issword (tmpreg)) |
2870 | { | |
2871 | as_warn (_("Expression out of range, using 0")); | |
2872 | tmpreg = 0; | |
2873 | } | |
2874 | addword (tmpreg); | |
2875 | break; | |
2876 | ||
2877 | case 'D': | |
2878 | install_operand (s[1], opP->reg - DATA); | |
2879 | break; | |
2880 | ||
fd99574b NC |
2881 | case 'e': /* EMAC ACCx, reg/reg. */ |
2882 | install_operand (s[1], opP->reg - ACC); | |
2883 | break; | |
2884 | ||
36759679 | 2885 | case 'E': /* Ignore it. */ |
6da466c7 ILT |
2886 | break; |
2887 | ||
252b5132 RH |
2888 | case 'F': |
2889 | install_operand (s[1], opP->reg - FP0); | |
2890 | break; | |
2891 | ||
fd99574b NC |
2892 | case 'g': /* EMAC ACCEXTx. */ |
2893 | install_operand (s[1], opP->reg - ACCEXT01); | |
2894 | break; | |
2895 | ||
36759679 | 2896 | case 'G': /* Ignore it. */ |
6da466c7 ILT |
2897 | case 'H': |
2898 | break; | |
2899 | ||
252b5132 RH |
2900 | case 'I': |
2901 | tmpreg = opP->reg - COP0; | |
2902 | install_operand (s[1], tmpreg); | |
2903 | break; | |
2904 | ||
fd99574b NC |
2905 | case 'i': /* MAC/EMAC scale factor. */ |
2906 | install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); | |
2907 | break; | |
2908 | ||
36759679 | 2909 | case 'J': /* JF foo. */ |
252b5132 RH |
2910 | switch (opP->reg) |
2911 | { | |
2912 | case SFC: | |
2913 | tmpreg = 0x000; | |
2914 | break; | |
2915 | case DFC: | |
2916 | tmpreg = 0x001; | |
2917 | break; | |
2918 | case CACR: | |
2919 | tmpreg = 0x002; | |
2920 | break; | |
2921 | case TC: | |
2922 | tmpreg = 0x003; | |
2923 | break; | |
3e602632 | 2924 | case ACR0: |
252b5132 RH |
2925 | case ITT0: |
2926 | tmpreg = 0x004; | |
2927 | break; | |
3e602632 | 2928 | case ACR1: |
252b5132 RH |
2929 | case ITT1: |
2930 | tmpreg = 0x005; | |
2931 | break; | |
3e602632 | 2932 | case ACR2: |
252b5132 RH |
2933 | case DTT0: |
2934 | tmpreg = 0x006; | |
2935 | break; | |
3e602632 | 2936 | case ACR3: |
252b5132 RH |
2937 | case DTT1: |
2938 | tmpreg = 0x007; | |
2939 | break; | |
2940 | case BUSCR: | |
2941 | tmpreg = 0x008; | |
2942 | break; | |
2943 | ||
2944 | case USP: | |
2945 | tmpreg = 0x800; | |
2946 | break; | |
2947 | case VBR: | |
2948 | tmpreg = 0x801; | |
2949 | break; | |
2950 | case CAAR: | |
2951 | tmpreg = 0x802; | |
2952 | break; | |
2953 | case MSP: | |
2954 | tmpreg = 0x803; | |
2955 | break; | |
2956 | case ISP: | |
2957 | tmpreg = 0x804; | |
2958 | break; | |
2959 | case MMUSR: | |
2960 | tmpreg = 0x805; | |
2961 | break; | |
2962 | case URP: | |
2963 | tmpreg = 0x806; | |
2964 | break; | |
2965 | case SRP: | |
2966 | tmpreg = 0x807; | |
2967 | break; | |
2968 | case PCR: | |
2969 | tmpreg = 0x808; | |
2970 | break; | |
2971 | case ROMBAR: | |
2972 | tmpreg = 0xC00; | |
2973 | break; | |
3e602632 NC |
2974 | case ROMBAR1: |
2975 | tmpreg = 0xC01; | |
2976 | break; | |
2977 | case FLASHBAR: | |
252b5132 RH |
2978 | case RAMBAR0: |
2979 | tmpreg = 0xC04; | |
2980 | break; | |
3e602632 | 2981 | case RAMBAR: |
252b5132 RH |
2982 | case RAMBAR1: |
2983 | tmpreg = 0xC05; | |
2984 | break; | |
3e602632 NC |
2985 | case MPCR: |
2986 | tmpreg = 0xC0C; | |
2987 | break; | |
2988 | case EDRAMBAR: | |
2989 | tmpreg = 0xC0D; | |
2990 | break; | |
2991 | case MBAR0: | |
2992 | case SECMBAR: | |
2993 | tmpreg = 0xC0E; | |
2994 | break; | |
2995 | case MBAR1: | |
252b5132 RH |
2996 | case MBAR: |
2997 | tmpreg = 0xC0F; | |
2998 | break; | |
3e602632 NC |
2999 | case PCR1U0: |
3000 | tmpreg = 0xD02; | |
3001 | break; | |
3002 | case PCR1L0: | |
3003 | tmpreg = 0xD03; | |
3004 | break; | |
3005 | case PCR2U0: | |
3006 | tmpreg = 0xD04; | |
3007 | break; | |
3008 | case PCR2L0: | |
3009 | tmpreg = 0xD05; | |
3010 | break; | |
3011 | case PCR3U0: | |
3012 | tmpreg = 0xD06; | |
3013 | break; | |
3014 | case PCR3L0: | |
3015 | tmpreg = 0xD07; | |
3016 | break; | |
3017 | case PCR1L1: | |
3018 | tmpreg = 0xD0A; | |
3019 | break; | |
3020 | case PCR1U1: | |
3021 | tmpreg = 0xD0B; | |
3022 | break; | |
3023 | case PCR2L1: | |
3024 | tmpreg = 0xD0C; | |
3025 | break; | |
3026 | case PCR2U1: | |
3027 | tmpreg = 0xD0D; | |
3028 | break; | |
3029 | case PCR3L1: | |
3030 | tmpreg = 0xD0E; | |
3031 | break; | |
3032 | case PCR3U1: | |
3033 | tmpreg = 0xD0F; | |
3034 | break; | |
252b5132 RH |
3035 | default: |
3036 | abort (); | |
3037 | } | |
3038 | install_operand (s[1], tmpreg); | |
3039 | break; | |
3040 | ||
3041 | case 'k': | |
3042 | tmpreg = get_num (&opP->disp, 55); | |
3043 | install_operand (s[1], tmpreg & 0x7f); | |
3044 | break; | |
3045 | ||
3046 | case 'l': | |
3047 | tmpreg = opP->mask; | |
3048 | if (s[1] == 'w') | |
3049 | { | |
3050 | if (tmpreg & 0x7FF0000) | |
3051 | as_bad (_("Floating point register in register list")); | |
3052 | insop (reverse_16_bits (tmpreg), opcode); | |
3053 | } | |
3054 | else | |
3055 | { | |
3056 | if (tmpreg & 0x700FFFF) | |
3057 | as_bad (_("Wrong register in floating-point reglist")); | |
3058 | install_operand (s[1], reverse_8_bits (tmpreg >> 16)); | |
3059 | } | |
3060 | break; | |
3061 | ||
3062 | case 'L': | |
3063 | tmpreg = opP->mask; | |
3064 | if (s[1] == 'w') | |
3065 | { | |
3066 | if (tmpreg & 0x7FF0000) | |
3067 | as_bad (_("Floating point register in register list")); | |
3068 | insop (tmpreg, opcode); | |
3069 | } | |
3070 | else if (s[1] == '8') | |
3071 | { | |
3072 | if (tmpreg & 0x0FFFFFF) | |
3073 | as_bad (_("incorrect register in reglist")); | |
3074 | install_operand (s[1], tmpreg >> 24); | |
3075 | } | |
3076 | else | |
3077 | { | |
3078 | if (tmpreg & 0x700FFFF) | |
3079 | as_bad (_("wrong register in floating-point reglist")); | |
3080 | else | |
3081 | install_operand (s[1], tmpreg >> 16); | |
3082 | } | |
3083 | break; | |
3084 | ||
3085 | case 'M': | |
3086 | install_operand (s[1], get_num (&opP->disp, 60)); | |
3087 | break; | |
3088 | ||
3089 | case 'O': | |
3090 | tmpreg = ((opP->mode == DREG) | |
8fce3f5e | 3091 | ? 0x20 + (int) (opP->reg - DATA) |
252b5132 RH |
3092 | : (get_num (&opP->disp, 40) & 0x1F)); |
3093 | install_operand (s[1], tmpreg); | |
3094 | break; | |
3095 | ||
3096 | case 'Q': | |
3097 | tmpreg = get_num (&opP->disp, 10); | |
3098 | if (tmpreg == 8) | |
3099 | tmpreg = 0; | |
3100 | install_operand (s[1], tmpreg); | |
3101 | break; | |
3102 | ||
3103 | case 'R': | |
3104 | /* This depends on the fact that ADDR registers are eight | |
3105 | more than their corresponding DATA regs, so the result | |
36759679 | 3106 | will have the ADDR_REG bit set. */ |
252b5132 RH |
3107 | install_operand (s[1], opP->reg - DATA); |
3108 | break; | |
3109 | ||
3110 | case 'r': | |
3111 | if (opP->mode == AINDR) | |
3112 | install_operand (s[1], opP->reg - DATA); | |
3113 | else | |
3114 | install_operand (s[1], opP->index.reg - DATA); | |
3115 | break; | |
3116 | ||
3117 | case 's': | |
3118 | if (opP->reg == FPI) | |
3119 | tmpreg = 0x1; | |
3120 | else if (opP->reg == FPS) | |
3121 | tmpreg = 0x2; | |
3122 | else if (opP->reg == FPC) | |
3123 | tmpreg = 0x4; | |
3124 | else | |
3125 | abort (); | |
3126 | install_operand (s[1], tmpreg); | |
3127 | break; | |
3128 | ||
36759679 | 3129 | case 'S': /* Ignore it. */ |
252b5132 RH |
3130 | break; |
3131 | ||
3132 | case 'T': | |
3133 | install_operand (s[1], get_num (&opP->disp, 30)); | |
3134 | break; | |
3135 | ||
36759679 | 3136 | case 'U': /* Ignore it. */ |
252b5132 RH |
3137 | break; |
3138 | ||
3139 | case 'c': | |
3140 | switch (opP->reg) | |
3141 | { | |
3142 | case NC: | |
3143 | tmpreg = 0; | |
3144 | break; | |
3145 | case DC: | |
3146 | tmpreg = 1; | |
3147 | break; | |
3148 | case IC: | |
3149 | tmpreg = 2; | |
3150 | break; | |
3151 | case BC: | |
3152 | tmpreg = 3; | |
3153 | break; | |
3154 | default: | |
3155 | as_fatal (_("failed sanity check")); | |
36759679 | 3156 | } /* switch on cache token. */ |
252b5132 RH |
3157 | install_operand (s[1], tmpreg); |
3158 | break; | |
3159 | #ifndef NO_68851 | |
92774660 | 3160 | /* JF: These are out of order, I fear. */ |
252b5132 RH |
3161 | case 'f': |
3162 | switch (opP->reg) | |
3163 | { | |
3164 | case SFC: | |
3165 | tmpreg = 0; | |
3166 | break; | |
3167 | case DFC: | |
3168 | tmpreg = 1; | |
3169 | break; | |
3170 | default: | |
3171 | abort (); | |
3172 | } | |
3173 | install_operand (s[1], tmpreg); | |
3174 | break; | |
3175 | ||
3176 | case '0': | |
3177 | case '1': | |
3178 | case '2': | |
3179 | switch (opP->reg) | |
3180 | { | |
3181 | case TC: | |
3182 | tmpreg = 0; | |
3183 | break; | |
3184 | case CAL: | |
3185 | tmpreg = 4; | |
3186 | break; | |
3187 | case VAL: | |
3188 | tmpreg = 5; | |
3189 | break; | |
3190 | case SCC: | |
3191 | tmpreg = 6; | |
3192 | break; | |
3193 | case AC: | |
3194 | tmpreg = 7; | |
3195 | break; | |
3196 | default: | |
3197 | abort (); | |
3198 | } | |
3199 | install_operand (s[1], tmpreg); | |
3200 | break; | |
3201 | ||
3202 | case 'V': | |
3203 | if (opP->reg == VAL) | |
3204 | break; | |
3205 | abort (); | |
3206 | ||
3207 | case 'W': | |
3208 | switch (opP->reg) | |
3209 | { | |
3210 | case DRP: | |
3211 | tmpreg = 1; | |
3212 | break; | |
3213 | case SRP: | |
3214 | tmpreg = 2; | |
3215 | break; | |
3216 | case CRP: | |
3217 | tmpreg = 3; | |
3218 | break; | |
3219 | default: | |
3220 | abort (); | |
3221 | } | |
3222 | install_operand (s[1], tmpreg); | |
3223 | break; | |
3224 | ||
3225 | case 'X': | |
3226 | switch (opP->reg) | |
3227 | { | |
3228 | case BAD: | |
3229 | case BAD + 1: | |
3230 | case BAD + 2: | |
3231 | case BAD + 3: | |
3232 | case BAD + 4: | |
3233 | case BAD + 5: | |
3234 | case BAD + 6: | |
3235 | case BAD + 7: | |
3236 | tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); | |
3237 | break; | |
3238 | ||
3239 | case BAC: | |
3240 | case BAC + 1: | |
3241 | case BAC + 2: | |
3242 | case BAC + 3: | |
3243 | case BAC + 4: | |
3244 | case BAC + 5: | |
3245 | case BAC + 6: | |
3246 | case BAC + 7: | |
3247 | tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); | |
3248 | break; | |
3249 | ||
3250 | default: | |
3251 | abort (); | |
3252 | } | |
3253 | install_operand (s[1], tmpreg); | |
3254 | break; | |
3255 | case 'Y': | |
3256 | know (opP->reg == PSR); | |
3257 | break; | |
3258 | case 'Z': | |
3259 | know (opP->reg == PCSR); | |
3260 | break; | |
3261 | #endif /* m68851 */ | |
3262 | case '3': | |
3263 | switch (opP->reg) | |
3264 | { | |
3265 | case TT0: | |
3266 | tmpreg = 2; | |
3267 | break; | |
3268 | case TT1: | |
3269 | tmpreg = 3; | |
3270 | break; | |
3271 | default: | |
3272 | abort (); | |
3273 | } | |
3274 | install_operand (s[1], tmpreg); | |
3275 | break; | |
3276 | case 't': | |
3277 | tmpreg = get_num (&opP->disp, 20); | |
3278 | install_operand (s[1], tmpreg); | |
3279 | break; | |
36759679 | 3280 | case '_': /* used only for move16 absolute 32-bit address. */ |
252b5132 RH |
3281 | if (isvar (&opP->disp)) |
3282 | add_fix ('l', &opP->disp, 0, 0); | |
3e602632 | 3283 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
3284 | addword (tmpreg >> 16); |
3285 | addword (tmpreg & 0xFFFF); | |
3286 | break; | |
6da466c7 ILT |
3287 | case 'u': |
3288 | install_operand (s[1], opP->reg - DATA0L); | |
3289 | opP->reg -= (DATA0L); | |
36759679 | 3290 | opP->reg &= 0x0F; /* remove upper/lower bit. */ |
6da466c7 | 3291 | break; |
3e602632 NC |
3292 | case 'x': |
3293 | tmpreg = get_num (&opP->disp, 80); | |
3294 | if (tmpreg == -1) | |
3295 | tmpreg = 0; | |
3296 | install_operand (s[1], tmpreg); | |
3297 | break; | |
252b5132 RH |
3298 | default: |
3299 | abort (); | |
3300 | } | |
3301 | } | |
3302 | ||
3303 | /* By the time whe get here (FINALLY) the_ins contains the complete | |
92774660 | 3304 | instruction, ready to be emitted. . . */ |
252b5132 RH |
3305 | } |
3306 | ||
3307 | static int | |
31302357 | 3308 | reverse_16_bits (int in) |
252b5132 RH |
3309 | { |
3310 | int out = 0; | |
3311 | int n; | |
3312 | ||
3313 | static int mask[16] = | |
3314 | { | |
3315 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3316 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 | |
3317 | }; | |
3318 | for (n = 0; n < 16; n++) | |
3319 | { | |
3320 | if (in & mask[n]) | |
3321 | out |= mask[15 - n]; | |
3322 | } | |
3323 | return out; | |
3324 | } /* reverse_16_bits() */ | |
3325 | ||
3326 | static int | |
31302357 | 3327 | reverse_8_bits (int in) |
252b5132 RH |
3328 | { |
3329 | int out = 0; | |
3330 | int n; | |
3331 | ||
3332 | static int mask[8] = | |
3333 | { | |
3334 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3335 | }; | |
3336 | ||
3337 | for (n = 0; n < 8; n++) | |
3338 | { | |
3339 | if (in & mask[n]) | |
3340 | out |= mask[7 - n]; | |
3341 | } | |
3342 | return out; | |
3343 | } /* reverse_8_bits() */ | |
3344 | ||
3345 | /* Cause an extra frag to be generated here, inserting up to 10 bytes | |
3346 | (that value is chosen in the frag_var call in md_assemble). TYPE | |
3347 | is the subtype of the frag to be generated; its primary type is | |
3348 | rs_machine_dependent. | |
3349 | ||
3350 | The TYPE parameter is also used by md_convert_frag_1 and | |
3351 | md_estimate_size_before_relax. The appropriate type of fixup will | |
3352 | be emitted by md_convert_frag_1. | |
3353 | ||
3354 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ | |
3355 | static void | |
31302357 | 3356 | install_operand (int mode, int val) |
252b5132 RH |
3357 | { |
3358 | switch (mode) | |
3359 | { | |
3360 | case 's': | |
36759679 | 3361 | the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ |
252b5132 RH |
3362 | break; |
3363 | case 'd': | |
3364 | the_ins.opcode[0] |= val << 9; | |
3365 | break; | |
3366 | case '1': | |
3367 | the_ins.opcode[1] |= val << 12; | |
3368 | break; | |
3369 | case '2': | |
3370 | the_ins.opcode[1] |= val << 6; | |
3371 | break; | |
3372 | case '3': | |
3373 | the_ins.opcode[1] |= val; | |
3374 | break; | |
3375 | case '4': | |
3376 | the_ins.opcode[2] |= val << 12; | |
3377 | break; | |
3378 | case '5': | |
3379 | the_ins.opcode[2] |= val << 6; | |
3380 | break; | |
3381 | case '6': | |
3382 | /* DANGER! This is a hack to force cas2l and cas2w cmds to be | |
3383 | three words long! */ | |
3384 | the_ins.numo++; | |
3385 | the_ins.opcode[2] |= val; | |
3386 | break; | |
3387 | case '7': | |
3388 | the_ins.opcode[1] |= val << 7; | |
3389 | break; | |
3390 | case '8': | |
3391 | the_ins.opcode[1] |= val << 10; | |
3392 | break; | |
3393 | #ifndef NO_68851 | |
3394 | case '9': | |
3395 | the_ins.opcode[1] |= val << 5; | |
3396 | break; | |
3397 | #endif | |
3398 | ||
3399 | case 't': | |
3400 | the_ins.opcode[1] |= (val << 10) | (val << 7); | |
3401 | break; | |
3402 | case 'D': | |
3403 | the_ins.opcode[1] |= (val << 12) | val; | |
3404 | break; | |
3405 | case 'g': | |
3406 | the_ins.opcode[0] |= val = 0xff; | |
3407 | break; | |
3408 | case 'i': | |
3409 | the_ins.opcode[0] |= val << 9; | |
3410 | break; | |
3411 | case 'C': | |
3412 | the_ins.opcode[1] |= val; | |
3413 | break; | |
3414 | case 'j': | |
3415 | the_ins.opcode[1] |= val; | |
36759679 | 3416 | the_ins.numo++; /* What a hack. */ |
252b5132 RH |
3417 | break; |
3418 | case 'k': | |
3419 | the_ins.opcode[1] |= val << 4; | |
3420 | break; | |
3421 | case 'b': | |
3422 | case 'w': | |
3423 | case 'W': | |
3424 | case 'l': | |
3425 | break; | |
3426 | case 'e': | |
3427 | the_ins.opcode[0] |= (val << 6); | |
3428 | break; | |
3429 | case 'L': | |
3430 | the_ins.opcode[1] = (val >> 16); | |
3431 | the_ins.opcode[2] = val & 0xffff; | |
3432 | break; | |
6da466c7 ILT |
3433 | case 'm': |
3434 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); | |
3435 | the_ins.opcode[0] |= ((val & 0x7) << 9); | |
3436 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); | |
3437 | break; | |
fd99574b | 3438 | case 'n': /* MAC/EMAC Rx on !load. */ |
6da466c7 ILT |
3439 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); |
3440 | the_ins.opcode[0] |= ((val & 0x7) << 9); | |
fd99574b | 3441 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); |
6da466c7 | 3442 | break; |
fd99574b | 3443 | case 'o': /* MAC/EMAC Rx on load. */ |
6da466c7 ILT |
3444 | the_ins.opcode[1] |= val << 12; |
3445 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); | |
3446 | break; | |
fd99574b | 3447 | case 'M': /* MAC/EMAC Ry on !load. */ |
6da466c7 ILT |
3448 | the_ins.opcode[0] |= (val & 0xF); |
3449 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); | |
3450 | break; | |
fd99574b | 3451 | case 'N': /* MAC/EMAC Ry on load. */ |
6da466c7 ILT |
3452 | the_ins.opcode[1] |= (val & 0xF); |
3453 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); | |
3454 | break; | |
3455 | case 'h': | |
3456 | the_ins.opcode[1] |= ((val != 1) << 10); | |
3457 | break; | |
fd99574b NC |
3458 | case 'F': |
3459 | the_ins.opcode[0] |= ((val & 0x3) << 9); | |
3460 | break; | |
3461 | case 'f': | |
3462 | the_ins.opcode[0] |= ((val & 0x3) << 0); | |
3463 | break; | |
be8c092b | 3464 | case 'G': /* EMAC accumulator in a EMAC load instruction. */ |
fd99574b NC |
3465 | the_ins.opcode[0] |= ((~val & 0x1) << 7); |
3466 | the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); | |
3467 | break; | |
be8c092b | 3468 | case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ |
fd99574b NC |
3469 | the_ins.opcode[0] |= ((val & 0x1) << 7); |
3470 | the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); | |
3471 | break; | |
3472 | case 'I': | |
3473 | the_ins.opcode[1] |= ((val & 0x3) << 9); | |
3474 | break; | |
3475 | case ']': | |
3476 | the_ins.opcode[0] |= (val & 0x1) <<10; | |
3477 | break; | |
252b5132 RH |
3478 | case 'c': |
3479 | default: | |
3480 | as_fatal (_("failed sanity check.")); | |
3481 | } | |
6b6e92f4 | 3482 | } |
252b5132 RH |
3483 | |
3484 | static void | |
31302357 | 3485 | install_gen_operand (int mode, int val) |
252b5132 RH |
3486 | { |
3487 | switch (mode) | |
3488 | { | |
fd99574b NC |
3489 | case '/': /* Special for mask loads for mac/msac insns with |
3490 | possible mask; trailing_ampersend set in bit 8. */ | |
3491 | the_ins.opcode[0] |= (val & 0x3f); | |
3492 | the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); | |
3493 | break; | |
252b5132 RH |
3494 | case 's': |
3495 | the_ins.opcode[0] |= val; | |
3496 | break; | |
3497 | case 'd': | |
3498 | /* This is a kludge!!! */ | |
3499 | the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; | |
3500 | break; | |
3501 | case 'b': | |
3502 | case 'w': | |
3503 | case 'l': | |
3504 | case 'f': | |
3505 | case 'F': | |
3506 | case 'x': | |
3507 | case 'p': | |
3508 | the_ins.opcode[0] |= val; | |
3509 | break; | |
36759679 | 3510 | /* more stuff goes here. */ |
252b5132 RH |
3511 | default: |
3512 | as_fatal (_("failed sanity check.")); | |
3513 | } | |
6b6e92f4 | 3514 | } |
252b5132 | 3515 | |
6b6e92f4 NC |
3516 | /* Verify that we have some number of paren pairs, do m68k_ip_op(), and |
3517 | then deal with the bitfield hack. */ | |
252b5132 RH |
3518 | |
3519 | static char * | |
31302357 | 3520 | crack_operand (char *str, struct m68k_op *opP) |
252b5132 RH |
3521 | { |
3522 | register int parens; | |
3523 | register int c; | |
3524 | register char *beg_str; | |
3525 | int inquote = 0; | |
3526 | ||
3527 | if (!str) | |
3528 | { | |
3529 | return str; | |
3530 | } | |
3531 | beg_str = str; | |
3532 | for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) | |
3533 | { | |
3534 | if (! inquote) | |
3535 | { | |
3536 | if (*str == '(') | |
3537 | parens++; | |
3538 | else if (*str == ')') | |
3539 | { | |
3540 | if (!parens) | |
36759679 | 3541 | { /* ERROR. */ |
252b5132 RH |
3542 | opP->error = _("Extra )"); |
3543 | return str; | |
3544 | } | |
3545 | --parens; | |
3546 | } | |
3547 | } | |
3548 | if (flag_mri && *str == '\'') | |
3549 | inquote = ! inquote; | |
3550 | } | |
3551 | if (!*str && parens) | |
36759679 | 3552 | { /* ERROR. */ |
252b5132 RH |
3553 | opP->error = _("Missing )"); |
3554 | return str; | |
3555 | } | |
3556 | c = *str; | |
3557 | *str = '\0'; | |
3558 | if (m68k_ip_op (beg_str, opP) != 0) | |
3559 | { | |
3560 | *str = c; | |
3561 | return str; | |
3562 | } | |
3563 | *str = c; | |
3564 | if (c == '}') | |
36759679 | 3565 | c = *++str; /* JF bitfield hack. */ |
252b5132 RH |
3566 | if (c) |
3567 | { | |
3568 | c = *++str; | |
3569 | if (!c) | |
3570 | as_bad (_("Missing operand")); | |
3571 | } | |
3572 | ||
3573 | /* Detect MRI REG symbols and convert them to REGLSTs. */ | |
3574 | if (opP->mode == CONTROL && (int)opP->reg < 0) | |
3575 | { | |
3576 | opP->mode = REGLST; | |
3577 | opP->mask = ~(int)opP->reg; | |
3578 | opP->reg = 0; | |
3579 | } | |
3580 | ||
3581 | return str; | |
3582 | } | |
3583 | ||
3584 | /* This is the guts of the machine-dependent assembler. STR points to a | |
3585 | machine dependent instruction. This function is supposed to emit | |
3586 | the frags/bytes it assembles to. | |
3587 | */ | |
3588 | ||
3589 | static void | |
31302357 | 3590 | insert_reg (const char *regname, int regnum) |
252b5132 RH |
3591 | { |
3592 | char buf[100]; | |
3593 | int i; | |
3594 | ||
3595 | #ifdef REGISTER_PREFIX | |
3596 | if (!flag_reg_prefix_optional) | |
3597 | { | |
3598 | buf[0] = REGISTER_PREFIX; | |
3599 | strcpy (buf + 1, regname); | |
3600 | regname = buf; | |
3601 | } | |
3602 | #endif | |
3603 | ||
3604 | symbol_table_insert (symbol_new (regname, reg_section, regnum, | |
3605 | &zero_address_frag)); | |
3606 | ||
3607 | for (i = 0; regname[i]; i++) | |
3882b010 | 3608 | buf[i] = TOUPPER (regname[i]); |
252b5132 RH |
3609 | buf[i] = '\0'; |
3610 | ||
3611 | symbol_table_insert (symbol_new (buf, reg_section, regnum, | |
3612 | &zero_address_frag)); | |
3613 | } | |
3614 | ||
3615 | struct init_entry | |
3616 | { | |
3617 | const char *name; | |
3618 | int number; | |
3619 | }; | |
3620 | ||
3621 | static const struct init_entry init_table[] = | |
3622 | { | |
3623 | { "d0", DATA0 }, | |
3624 | { "d1", DATA1 }, | |
3625 | { "d2", DATA2 }, | |
3626 | { "d3", DATA3 }, | |
3627 | { "d4", DATA4 }, | |
3628 | { "d5", DATA5 }, | |
3629 | { "d6", DATA6 }, | |
3630 | { "d7", DATA7 }, | |
3631 | { "a0", ADDR0 }, | |
3632 | { "a1", ADDR1 }, | |
3633 | { "a2", ADDR2 }, | |
3634 | { "a3", ADDR3 }, | |
3635 | { "a4", ADDR4 }, | |
3636 | { "a5", ADDR5 }, | |
3637 | { "a6", ADDR6 }, | |
3638 | { "fp", ADDR6 }, | |
3639 | { "a7", ADDR7 }, | |
3640 | { "sp", ADDR7 }, | |
3641 | { "ssp", ADDR7 }, | |
3642 | { "fp0", FP0 }, | |
3643 | { "fp1", FP1 }, | |
3644 | { "fp2", FP2 }, | |
3645 | { "fp3", FP3 }, | |
3646 | { "fp4", FP4 }, | |
3647 | { "fp5", FP5 }, | |
3648 | { "fp6", FP6 }, | |
3649 | { "fp7", FP7 }, | |
3650 | { "fpi", FPI }, | |
3651 | { "fpiar", FPI }, | |
3652 | { "fpc", FPI }, | |
3653 | { "fps", FPS }, | |
3654 | { "fpsr", FPS }, | |
3655 | { "fpc", FPC }, | |
3656 | { "fpcr", FPC }, | |
3657 | { "control", FPC }, | |
3658 | { "status", FPS }, | |
3659 | { "iaddr", FPI }, | |
3660 | ||
3661 | { "cop0", COP0 }, | |
3662 | { "cop1", COP1 }, | |
3663 | { "cop2", COP2 }, | |
3664 | { "cop3", COP3 }, | |
3665 | { "cop4", COP4 }, | |
3666 | { "cop5", COP5 }, | |
3667 | { "cop6", COP6 }, | |
3668 | { "cop7", COP7 }, | |
3669 | { "pc", PC }, | |
3670 | { "zpc", ZPC }, | |
3671 | { "sr", SR }, | |
3672 | ||
3673 | { "ccr", CCR }, | |
3674 | { "cc", CCR }, | |
3675 | ||
6da466c7 | 3676 | { "acc", ACC }, |
fd99574b NC |
3677 | { "acc0", ACC }, |
3678 | { "acc1", ACC1 }, | |
3679 | { "acc2", ACC2 }, | |
3680 | { "acc3", ACC3 }, | |
3681 | { "accext01", ACCEXT01 }, | |
3682 | { "accext23", ACCEXT23 }, | |
6da466c7 ILT |
3683 | { "macsr", MACSR }, |
3684 | { "mask", MASK }, | |
3685 | ||
36759679 NC |
3686 | /* Control registers. */ |
3687 | { "sfc", SFC }, /* Source Function Code. */ | |
252b5132 | 3688 | { "sfcr", SFC }, |
36759679 | 3689 | { "dfc", DFC }, /* Destination Function Code. */ |
252b5132 | 3690 | { "dfcr", DFC }, |
36759679 NC |
3691 | { "cacr", CACR }, /* Cache Control Register. */ |
3692 | { "caar", CAAR }, /* Cache Address Register. */ | |
252b5132 | 3693 | |
36759679 NC |
3694 | { "usp", USP }, /* User Stack Pointer. */ |
3695 | { "vbr", VBR }, /* Vector Base Register. */ | |
3696 | { "msp", MSP }, /* Master Stack Pointer. */ | |
3697 | { "isp", ISP }, /* Interrupt Stack Pointer. */ | |
252b5132 | 3698 | |
36759679 NC |
3699 | { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ |
3700 | { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ | |
3701 | { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ | |
3702 | { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ | |
252b5132 RH |
3703 | |
3704 | /* 68ec040 versions of same */ | |
36759679 NC |
3705 | { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ |
3706 | { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ | |
3707 | { "dacr0", DTT0 }, /* Data Access Control Register 0. */ | |
3708 | { "dacr1", DTT1 }, /* Data Access Control Register 0. */ | |
252b5132 RH |
3709 | |
3710 | /* mcf5200 versions of same. The ColdFire programmer's reference | |
3711 | manual indicated that the order is 2,3,0,1, but Ken Rose | |
3712 | <rose@netcom.com> says that 0,1,2,3 is the correct order. */ | |
3e602632 NC |
3713 | { "acr0", ACR0 }, /* Access Control Unit 0. */ |
3714 | { "acr1", ACR1 }, /* Access Control Unit 1. */ | |
3715 | { "acr2", ACR2 }, /* Access Control Unit 2. */ | |
3716 | { "acr3", ACR3 }, /* Access Control Unit 3. */ | |
252b5132 | 3717 | |
36759679 | 3718 | { "tc", TC }, /* MMU Translation Control Register. */ |
252b5132 RH |
3719 | { "tcr", TC }, |
3720 | ||
36759679 NC |
3721 | { "mmusr", MMUSR }, /* MMU Status Register. */ |
3722 | { "srp", SRP }, /* User Root Pointer. */ | |
3723 | { "urp", URP }, /* Supervisor Root Pointer. */ | |
252b5132 RH |
3724 | |
3725 | { "buscr", BUSCR }, | |
3726 | { "pcr", PCR }, | |
3727 | ||
36759679 NC |
3728 | { "rombar", ROMBAR }, /* ROM Base Address Register. */ |
3729 | { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ | |
3730 | { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ | |
3731 | { "mbar", MBAR }, /* Module Base Address Register. */ | |
3e602632 NC |
3732 | |
3733 | { "mbar0", MBAR0 }, /* mcfv4e registers. */ | |
3734 | { "mbar1", MBAR1 }, /* mcfv4e registers. */ | |
3735 | { "rombar0", ROMBAR }, /* mcfv4e registers. */ | |
3736 | { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ | |
3737 | { "mpcr", MPCR }, /* mcfv4e registers. */ | |
3738 | { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ | |
3739 | { "secmbar", SECMBAR }, /* mcfv4e registers. */ | |
3740 | { "asid", TC }, /* mcfv4e registers. */ | |
3741 | { "mmubar", BUSCR }, /* mcfv4e registers. */ | |
3742 | { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ | |
3743 | { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ | |
3744 | { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ | |
3745 | { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ | |
3746 | { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ | |
3747 | { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ | |
3748 | { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ | |
3749 | { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ | |
3750 | { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ | |
3751 | { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ | |
3752 | { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ | |
3753 | { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ | |
3754 | ||
3755 | { "flashbar", FLASHBAR }, /* mcf528x registers. */ | |
3756 | { "rambar", RAMBAR }, /* mcf528x registers. */ | |
36759679 | 3757 | /* End of control registers. */ |
252b5132 RH |
3758 | |
3759 | { "ac", AC }, | |
3760 | { "bc", BC }, | |
3761 | { "cal", CAL }, | |
3762 | { "crp", CRP }, | |
3763 | { "drp", DRP }, | |
3764 | { "pcsr", PCSR }, | |
3765 | { "psr", PSR }, | |
3766 | { "scc", SCC }, | |
3767 | { "val", VAL }, | |
3768 | { "bad0", BAD0 }, | |
3769 | { "bad1", BAD1 }, | |
3770 | { "bad2", BAD2 }, | |
3771 | { "bad3", BAD3 }, | |
3772 | { "bad4", BAD4 }, | |
3773 | { "bad5", BAD5 }, | |
3774 | { "bad6", BAD6 }, | |
3775 | { "bad7", BAD7 }, | |
3776 | { "bac0", BAC0 }, | |
3777 | { "bac1", BAC1 }, | |
3778 | { "bac2", BAC2 }, | |
3779 | { "bac3", BAC3 }, | |
3780 | { "bac4", BAC4 }, | |
3781 | { "bac5", BAC5 }, | |
3782 | { "bac6", BAC6 }, | |
3783 | { "bac7", BAC7 }, | |
3784 | ||
3785 | { "ic", IC }, | |
3786 | { "dc", DC }, | |
3787 | { "nc", NC }, | |
3788 | ||
3789 | { "tt0", TT0 }, | |
3790 | { "tt1", TT1 }, | |
36759679 | 3791 | /* 68ec030 versions of same. */ |
252b5132 RH |
3792 | { "ac0", TT0 }, |
3793 | { "ac1", TT1 }, | |
36759679 | 3794 | /* 68ec030 access control unit, identical to 030 MMU status reg. */ |
252b5132 RH |
3795 | { "acusr", PSR }, |
3796 | ||
3797 | /* Suppressed data and address registers. */ | |
3798 | { "zd0", ZDATA0 }, | |
3799 | { "zd1", ZDATA1 }, | |
3800 | { "zd2", ZDATA2 }, | |
3801 | { "zd3", ZDATA3 }, | |
3802 | { "zd4", ZDATA4 }, | |
3803 | { "zd5", ZDATA5 }, | |
3804 | { "zd6", ZDATA6 }, | |
3805 | { "zd7", ZDATA7 }, | |
3806 | { "za0", ZADDR0 }, | |
3807 | { "za1", ZADDR1 }, | |
3808 | { "za2", ZADDR2 }, | |
3809 | { "za3", ZADDR3 }, | |
3810 | { "za4", ZADDR4 }, | |
3811 | { "za5", ZADDR5 }, | |
3812 | { "za6", ZADDR6 }, | |
3813 | { "za7", ZADDR7 }, | |
3814 | ||
92774660 | 3815 | /* Upper and lower data and address registers, used by macw and msacw. */ |
6da466c7 ILT |
3816 | { "d0l", DATA0L }, |
3817 | { "d1l", DATA1L }, | |
3818 | { "d2l", DATA2L }, | |
3819 | { "d3l", DATA3L }, | |
3820 | { "d4l", DATA4L }, | |
3821 | { "d5l", DATA5L }, | |
3822 | { "d6l", DATA6L }, | |
3823 | { "d7l", DATA7L }, | |
3824 | ||
3825 | { "a0l", ADDR0L }, | |
3826 | { "a1l", ADDR1L }, | |
3827 | { "a2l", ADDR2L }, | |
3828 | { "a3l", ADDR3L }, | |
3829 | { "a4l", ADDR4L }, | |
3830 | { "a5l", ADDR5L }, | |
3831 | { "a6l", ADDR6L }, | |
3832 | { "a7l", ADDR7L }, | |
3833 | ||
3834 | { "d0u", DATA0U }, | |
3835 | { "d1u", DATA1U }, | |
3836 | { "d2u", DATA2U }, | |
3837 | { "d3u", DATA3U }, | |
3838 | { "d4u", DATA4U }, | |
3839 | { "d5u", DATA5U }, | |
3840 | { "d6u", DATA6U }, | |
3841 | { "d7u", DATA7U }, | |
3842 | ||
3843 | { "a0u", ADDR0U }, | |
3844 | { "a1u", ADDR1U }, | |
3845 | { "a2u", ADDR2U }, | |
3846 | { "a3u", ADDR3U }, | |
3847 | { "a4u", ADDR4U }, | |
3848 | { "a5u", ADDR5U }, | |
3849 | { "a6u", ADDR6U }, | |
3850 | { "a7u", ADDR7U }, | |
3851 | ||
252b5132 RH |
3852 | { 0, 0 } |
3853 | }; | |
3854 | ||
3855 | static void | |
31302357 | 3856 | init_regtable (void) |
252b5132 RH |
3857 | { |
3858 | int i; | |
3859 | for (i = 0; init_table[i].name; i++) | |
3860 | insert_reg (init_table[i].name, init_table[i].number); | |
3861 | } | |
3862 | ||
3863 | static int no_68851, no_68881; | |
3864 | ||
3865 | #ifdef OBJ_AOUT | |
3866 | /* a.out machine type. Default to 68020. */ | |
3867 | int m68k_aout_machtype = 2; | |
3868 | #endif | |
3869 | ||
3870 | void | |
31302357 | 3871 | md_assemble (char *str) |
252b5132 RH |
3872 | { |
3873 | const char *er; | |
3874 | short *fromP; | |
3875 | char *toP = NULL; | |
3876 | int m, n = 0; | |
3877 | char *to_beg_P; | |
3878 | int shorts_this_frag; | |
3879 | fixS *fixP; | |
3880 | ||
3881 | /* In MRI mode, the instruction and operands are separated by a | |
3882 | space. Anything following the operands is a comment. The label | |
3883 | has already been removed. */ | |
3884 | if (flag_mri) | |
3885 | { | |
3886 | char *s; | |
3887 | int fields = 0; | |
3888 | int infield = 0; | |
3889 | int inquote = 0; | |
3890 | ||
3891 | for (s = str; *s != '\0'; s++) | |
3892 | { | |
3893 | if ((*s == ' ' || *s == '\t') && ! inquote) | |
3894 | { | |
3895 | if (infield) | |
3896 | { | |
3897 | ++fields; | |
3898 | if (fields >= 2) | |
3899 | { | |
3900 | *s = '\0'; | |
3901 | break; | |
3902 | } | |
3903 | infield = 0; | |
3904 | } | |
3905 | } | |
3906 | else | |
3907 | { | |
3908 | if (! infield) | |
3909 | infield = 1; | |
3910 | if (*s == '\'') | |
3911 | inquote = ! inquote; | |
3912 | } | |
3913 | } | |
3914 | } | |
3915 | ||
31302357 | 3916 | memset (&the_ins, '\0', sizeof (the_ins)); |
252b5132 RH |
3917 | m68k_ip (str); |
3918 | er = the_ins.error; | |
3919 | if (!er) | |
3920 | { | |
3921 | for (n = 0; n < the_ins.numargs; n++) | |
3922 | if (the_ins.operands[n].error) | |
3923 | { | |
3924 | er = the_ins.operands[n].error; | |
3925 | break; | |
3926 | } | |
3927 | } | |
3928 | if (er) | |
3929 | { | |
3930 | as_bad (_("%s -- statement `%s' ignored"), er, str); | |
3931 | return; | |
3932 | } | |
3933 | ||
3934 | /* If there is a current label, record that it marks an instruction. */ | |
3935 | if (current_label != NULL) | |
3936 | { | |
3937 | current_label->text = 1; | |
3938 | current_label = NULL; | |
3939 | } | |
3940 | ||
f27a3839 AS |
3941 | #ifdef OBJ_ELF |
3942 | /* Tie dwarf2 debug info to the address at the start of the insn. */ | |
3943 | dwarf2_emit_insn (0); | |
3944 | #endif | |
3945 | ||
252b5132 RH |
3946 | if (the_ins.nfrag == 0) |
3947 | { | |
36759679 | 3948 | /* No frag hacking involved; just put it out. */ |
252b5132 RH |
3949 | toP = frag_more (2 * the_ins.numo); |
3950 | fromP = &the_ins.opcode[0]; | |
3951 | for (m = the_ins.numo; m; --m) | |
3952 | { | |
3953 | md_number_to_chars (toP, (long) (*fromP), 2); | |
3954 | toP += 2; | |
3955 | fromP++; | |
3956 | } | |
36759679 | 3957 | /* Put out symbol-dependent info. */ |
252b5132 RH |
3958 | for (m = 0; m < the_ins.nrel; m++) |
3959 | { | |
3960 | switch (the_ins.reloc[m].wid) | |
3961 | { | |
3962 | case 'B': | |
3963 | n = 1; | |
3964 | break; | |
3965 | case 'b': | |
3966 | n = 1; | |
3967 | break; | |
3968 | case '3': | |
3969 | n = 1; | |
3970 | break; | |
3971 | case 'w': | |
3972 | case 'W': | |
3973 | n = 2; | |
3974 | break; | |
3975 | case 'l': | |
3976 | n = 4; | |
3977 | break; | |
3978 | default: | |
3979 | as_fatal (_("Don't know how to figure width of %c in md_assemble()"), | |
3980 | the_ins.reloc[m].wid); | |
3981 | } | |
3982 | ||
3983 | fixP = fix_new_exp (frag_now, | |
3984 | ((toP - frag_now->fr_literal) | |
3985 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
3986 | n, | |
3987 | &the_ins.reloc[m].exp, | |
3988 | the_ins.reloc[m].pcrel, | |
3989 | get_reloc_code (n, the_ins.reloc[m].pcrel, | |
3990 | the_ins.reloc[m].pic_reloc)); | |
3991 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
3992 | if (the_ins.reloc[m].wid == 'B') | |
3993 | fixP->fx_signed = 1; | |
3994 | } | |
3995 | return; | |
3996 | } | |
3997 | ||
36759679 | 3998 | /* There's some frag hacking. */ |
fbe572f9 AM |
3999 | { |
4000 | /* Calculate the max frag size. */ | |
4001 | int wid; | |
4002 | ||
4003 | wid = 2 * the_ins.fragb[0].fragoff; | |
4004 | for (n = 1; n < the_ins.nfrag; n++) | |
4005 | wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4006 | /* frag_var part. */ | |
4007 | wid += 10; | |
4008 | /* Make sure the whole insn fits in one chunk, in particular that | |
4009 | the var part is attached, as we access one byte before the | |
4010 | variable frag for byte branches. */ | |
4011 | frag_grow (wid); | |
4012 | } | |
4013 | ||
252b5132 RH |
4014 | for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) |
4015 | { | |
4016 | int wid; | |
4017 | ||
4018 | if (n == 0) | |
4019 | wid = 2 * the_ins.fragb[n].fragoff; | |
4020 | else | |
4021 | wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4022 | toP = frag_more (wid); | |
4023 | to_beg_P = toP; | |
4024 | shorts_this_frag = 0; | |
4025 | for (m = wid / 2; m; --m) | |
4026 | { | |
4027 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4028 | toP += 2; | |
4029 | fromP++; | |
4030 | shorts_this_frag++; | |
4031 | } | |
4032 | for (m = 0; m < the_ins.nrel; m++) | |
4033 | { | |
4034 | if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) | |
4035 | { | |
4036 | the_ins.reloc[m].n -= 2 * shorts_this_frag; | |
4037 | break; | |
4038 | } | |
4039 | wid = the_ins.reloc[m].wid; | |
4040 | if (wid == 0) | |
4041 | continue; | |
4042 | the_ins.reloc[m].wid = 0; | |
4043 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
4044 | ||
4045 | fixP = fix_new_exp (frag_now, | |
4046 | ((toP - frag_now->fr_literal) | |
4047 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
4048 | wid, | |
4049 | &the_ins.reloc[m].exp, | |
4050 | the_ins.reloc[m].pcrel, | |
4051 | get_reloc_code (wid, the_ins.reloc[m].pcrel, | |
4052 | the_ins.reloc[m].pic_reloc)); | |
4053 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4054 | } | |
4055 | (void) frag_var (rs_machine_dependent, 10, 0, | |
4056 | (relax_substateT) (the_ins.fragb[n].fragty), | |
4057 | the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); | |
4058 | } | |
4059 | n = (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4060 | shorts_this_frag = 0; | |
4061 | if (n) | |
4062 | { | |
4063 | toP = frag_more (n * sizeof (short)); | |
4064 | while (n--) | |
4065 | { | |
4066 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4067 | toP += 2; | |
4068 | fromP++; | |
4069 | shorts_this_frag++; | |
4070 | } | |
4071 | } | |
4072 | for (m = 0; m < the_ins.nrel; m++) | |
4073 | { | |
4074 | int wid; | |
4075 | ||
4076 | wid = the_ins.reloc[m].wid; | |
4077 | if (wid == 0) | |
4078 | continue; | |
4079 | the_ins.reloc[m].wid = 0; | |
4080 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
4081 | ||
4082 | fixP = fix_new_exp (frag_now, | |
4083 | ((the_ins.reloc[m].n + toP - frag_now->fr_literal) | |
4084 | - shorts_this_frag * 2), | |
4085 | wid, | |
4086 | &the_ins.reloc[m].exp, | |
4087 | the_ins.reloc[m].pcrel, | |
4088 | get_reloc_code (wid, the_ins.reloc[m].pcrel, | |
4089 | the_ins.reloc[m].pic_reloc)); | |
4090 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4091 | } | |
4092 | } | |
4093 | ||
60fed2d3 NC |
4094 | /* Comparison function used by qsort to rank the opcode entries by name. */ |
4095 | ||
4096 | static int | |
4097 | m68k_compare_opcode (const void * v1, const void * v2) | |
4098 | { | |
4099 | struct m68k_opcode * op1, * op2; | |
4100 | int ret; | |
4101 | ||
4102 | op1 = *(struct m68k_opcode **) v1; | |
4103 | op2 = *(struct m68k_opcode **) v2; | |
4104 | ||
4105 | /* Compare the two names. If different, return the comparison. | |
4106 | If the same, return the order they are in the opcode table. */ | |
4107 | ret = strcmp (op1->name, op2->name); | |
4108 | if (ret) | |
4109 | return ret; | |
4110 | if (op1 < op2) | |
4111 | return -1; | |
4112 | return 0; | |
4113 | } | |
4114 | ||
252b5132 | 4115 | void |
60fed2d3 | 4116 | md_begin (void) |
252b5132 | 4117 | { |
60fed2d3 NC |
4118 | const struct m68k_opcode *ins; |
4119 | struct m68k_incant *hack, *slak; | |
4120 | const char *retval = 0; /* Empty string, or error msg text. */ | |
4121 | int i; | |
4122 | ||
4123 | /* Set up hash tables with 68000 instructions. | |
4124 | similar to what the vax assembler does. */ | |
252b5132 RH |
4125 | /* RMS claims the thing to do is take the m68k-opcode.h table, and make |
4126 | a copy of it at runtime, adding in the information we want but isn't | |
4127 | there. I think it'd be better to have an awk script hack the table | |
4128 | at compile time. Or even just xstr the table and use it as-is. But | |
4129 | my lord ghod hath spoken, so we do it this way. Excuse the ugly var | |
4130 | names. */ | |
4131 | ||
252b5132 RH |
4132 | if (flag_mri) |
4133 | { | |
4134 | flag_reg_prefix_optional = 1; | |
4135 | m68k_abspcadd = 1; | |
4136 | if (! m68k_rel32_from_cmdline) | |
4137 | m68k_rel32 = 0; | |
4138 | } | |
4139 | ||
60fed2d3 NC |
4140 | /* First sort the opcode table into alphabetical order to seperate |
4141 | the order that the assembler wants to see the opcodes from the | |
4142 | order that the disassembler wants to see them. */ | |
4143 | m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes)); | |
4144 | if (!m68k_sorted_opcodes) | |
4145 | as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"), | |
4146 | m68k_numopcodes * sizeof (* m68k_sorted_opcodes)); | |
4147 | ||
4148 | for (i = m68k_numopcodes; i--;) | |
4149 | m68k_sorted_opcodes[i] = m68k_opcodes + i; | |
4150 | ||
4151 | qsort (m68k_sorted_opcodes, m68k_numopcodes, | |
4152 | sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); | |
4153 | ||
252b5132 RH |
4154 | op_hash = hash_new (); |
4155 | ||
4156 | obstack_begin (&robyn, 4000); | |
4157 | for (i = 0; i < m68k_numopcodes; i++) | |
4158 | { | |
4159 | hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant)); | |
4160 | do | |
4161 | { | |
60fed2d3 NC |
4162 | ins = m68k_sorted_opcodes[i]; |
4163 | ||
4164 | /* We *could* ignore insns that don't match our | |
4165 | arch here by just leaving them out of the hash. */ | |
252b5132 RH |
4166 | slak->m_operands = ins->args; |
4167 | slak->m_opnum = strlen (slak->m_operands) / 2; | |
4168 | slak->m_arch = ins->arch; | |
4169 | slak->m_opcode = ins->opcode; | |
36759679 | 4170 | /* This is kludgey. */ |
252b5132 RH |
4171 | slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1; |
4172 | if (i + 1 != m68k_numopcodes | |
60fed2d3 | 4173 | && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) |
252b5132 | 4174 | { |
60fed2d3 | 4175 | slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4176 | i++; |
4177 | } | |
4178 | else | |
4179 | slak->m_next = 0; | |
4180 | slak = slak->m_next; | |
4181 | } | |
4182 | while (slak); | |
4183 | ||
4184 | retval = hash_insert (op_hash, ins->name, (char *) hack); | |
4185 | if (retval) | |
4186 | as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval); | |
4187 | } | |
4188 | ||
4189 | for (i = 0; i < m68k_numaliases; i++) | |
4190 | { | |
4191 | const char *name = m68k_opcode_aliases[i].primary; | |
4192 | const char *alias = m68k_opcode_aliases[i].alias; | |
4193 | PTR val = hash_find (op_hash, name); | |
60fed2d3 | 4194 | |
252b5132 RH |
4195 | if (!val) |
4196 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); | |
4197 | retval = hash_insert (op_hash, alias, val); | |
4198 | if (retval) | |
4199 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); | |
4200 | } | |
4201 | ||
4202 | /* In MRI mode, all unsized branches are variable sized. Normally, | |
4203 | they are word sized. */ | |
4204 | if (flag_mri) | |
4205 | { | |
4206 | static struct m68k_opcode_alias mri_aliases[] = | |
4207 | { | |
4208 | { "bhi", "jhi", }, | |
4209 | { "bls", "jls", }, | |
4210 | { "bcc", "jcc", }, | |
4211 | { "bcs", "jcs", }, | |
4212 | { "bne", "jne", }, | |
4213 | { "beq", "jeq", }, | |
4214 | { "bvc", "jvc", }, | |
4215 | { "bvs", "jvs", }, | |
4216 | { "bpl", "jpl", }, | |
4217 | { "bmi", "jmi", }, | |
4218 | { "bge", "jge", }, | |
4219 | { "blt", "jlt", }, | |
4220 | { "bgt", "jgt", }, | |
4221 | { "ble", "jle", }, | |
4222 | { "bra", "jra", }, | |
4223 | { "bsr", "jbsr", }, | |
4224 | }; | |
4225 | ||
8fce3f5e AM |
4226 | for (i = 0; |
4227 | i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); | |
4228 | i++) | |
252b5132 RH |
4229 | { |
4230 | const char *name = mri_aliases[i].primary; | |
4231 | const char *alias = mri_aliases[i].alias; | |
4232 | PTR val = hash_find (op_hash, name); | |
60fed2d3 | 4233 | |
252b5132 RH |
4234 | if (!val) |
4235 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); | |
4236 | retval = hash_jam (op_hash, alias, val); | |
4237 | if (retval) | |
4238 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); | |
4239 | } | |
4240 | } | |
4241 | ||
8fce3f5e | 4242 | for (i = 0; i < (int) sizeof (notend_table); i++) |
252b5132 RH |
4243 | { |
4244 | notend_table[i] = 0; | |
4245 | alt_notend_table[i] = 0; | |
4246 | } | |
60fed2d3 | 4247 | |
252b5132 RH |
4248 | notend_table[','] = 1; |
4249 | notend_table['{'] = 1; | |
4250 | notend_table['}'] = 1; | |
4251 | alt_notend_table['a'] = 1; | |
4252 | alt_notend_table['A'] = 1; | |
4253 | alt_notend_table['d'] = 1; | |
4254 | alt_notend_table['D'] = 1; | |
4255 | alt_notend_table['#'] = 1; | |
4256 | alt_notend_table['&'] = 1; | |
4257 | alt_notend_table['f'] = 1; | |
4258 | alt_notend_table['F'] = 1; | |
4259 | #ifdef REGISTER_PREFIX | |
4260 | alt_notend_table[REGISTER_PREFIX] = 1; | |
4261 | #endif | |
4262 | ||
4263 | /* We need to put '(' in alt_notend_table to handle | |
60fed2d3 | 4264 | cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ |
252b5132 RH |
4265 | alt_notend_table['('] = 1; |
4266 | ||
4267 | /* We need to put '@' in alt_notend_table to handle | |
60fed2d3 | 4268 | cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ |
252b5132 RH |
4269 | alt_notend_table['@'] = 1; |
4270 | ||
4271 | /* We need to put digits in alt_notend_table to handle | |
60fed2d3 | 4272 | bfextu %d0{24:1},%d0 */ |
252b5132 RH |
4273 | alt_notend_table['0'] = 1; |
4274 | alt_notend_table['1'] = 1; | |
4275 | alt_notend_table['2'] = 1; | |
4276 | alt_notend_table['3'] = 1; | |
4277 | alt_notend_table['4'] = 1; | |
4278 | alt_notend_table['5'] = 1; | |
4279 | alt_notend_table['6'] = 1; | |
4280 | alt_notend_table['7'] = 1; | |
4281 | alt_notend_table['8'] = 1; | |
4282 | alt_notend_table['9'] = 1; | |
4283 | ||
4284 | #ifndef MIT_SYNTAX_ONLY | |
4285 | /* Insert pseudo ops, these have to go into the opcode table since | |
36759679 | 4286 | gas expects pseudo ops to start with a dot. */ |
252b5132 RH |
4287 | { |
4288 | int n = 0; | |
60fed2d3 | 4289 | |
252b5132 RH |
4290 | while (mote_pseudo_table[n].poc_name) |
4291 | { | |
60fed2d3 | 4292 | hack = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4293 | hash_insert (op_hash, |
4294 | mote_pseudo_table[n].poc_name, (char *) hack); | |
4295 | hack->m_operands = 0; | |
4296 | hack->m_opnum = n; | |
4297 | n++; | |
4298 | } | |
4299 | } | |
4300 | #endif | |
4301 | ||
4302 | init_regtable (); | |
4303 | ||
4304 | #ifdef OBJ_ELF | |
4305 | record_alignment (text_section, 2); | |
4306 | record_alignment (data_section, 2); | |
4307 | record_alignment (bss_section, 2); | |
4308 | #endif | |
4309 | } | |
4310 | ||
4311 | static void | |
31302357 | 4312 | select_control_regs (void) |
252b5132 RH |
4313 | { |
4314 | /* Note which set of "movec" control registers is available. */ | |
6b6e92f4 | 4315 | switch (current_chip) |
252b5132 | 4316 | { |
4f2a7c9e | 4317 | case 0: |
6b6e92f4 NC |
4318 | if (verbose) |
4319 | as_warn (_("architecture not yet selected: defaulting to 68020")); | |
4f2a7c9e NC |
4320 | control_regs = m68020_control_regs; |
4321 | break; | |
4322 | ||
252b5132 RH |
4323 | case m68000: |
4324 | control_regs = m68000_control_regs; | |
4325 | break; | |
4326 | case m68010: | |
4327 | control_regs = m68010_control_regs; | |
4328 | break; | |
4329 | case m68020: | |
4330 | case m68030: | |
4331 | control_regs = m68020_control_regs; | |
4332 | break; | |
4333 | case m68040: | |
4334 | control_regs = m68040_control_regs; | |
4335 | break; | |
4336 | case m68060: | |
4337 | control_regs = m68060_control_regs; | |
4338 | break; | |
4339 | case cpu32: | |
4340 | control_regs = cpu32_control_regs; | |
4341 | break; | |
4342 | case mcf5200: | |
6da466c7 ILT |
4343 | case mcf5206e: |
4344 | case mcf5307: | |
dc84e067 | 4345 | case mcf5407: |
6da466c7 | 4346 | control_regs = mcf_control_regs; |
252b5132 | 4347 | break; |
3e602632 | 4348 | case mcf528x: |
6b6e92f4 | 4349 | case mcf521x: |
3e602632 NC |
4350 | control_regs = mcf528x_control_regs; |
4351 | break; | |
6b6e92f4 NC |
4352 | case mcf5470: |
4353 | case mcf5480: | |
3e602632 NC |
4354 | control_regs = mcfv4e_control_regs; |
4355 | break; | |
252b5132 RH |
4356 | default: |
4357 | abort (); | |
4358 | } | |
4359 | } | |
4360 | ||
4361 | void | |
31302357 | 4362 | m68k_init_after_args (void) |
252b5132 RH |
4363 | { |
4364 | if (cpu_of_arch (current_architecture) == 0) | |
4365 | { | |
4366 | int i; | |
4367 | const char *default_cpu = TARGET_CPU; | |
4368 | ||
4369 | if (*default_cpu == 'm') | |
4370 | default_cpu++; | |
4371 | for (i = 0; i < n_archs; i++) | |
4372 | if (strcasecmp (default_cpu, archs[i].name) == 0) | |
4373 | break; | |
4374 | if (i == n_archs) | |
4375 | { | |
4376 | as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU); | |
4377 | current_architecture |= m68020; | |
4378 | } | |
4379 | else | |
4380 | current_architecture |= archs[i].arch; | |
4381 | } | |
4382 | /* Permit m68881 specification with all cpus; those that can't work | |
4383 | with a coprocessor could be doing emulation. */ | |
4384 | if (current_architecture & m68851) | |
4385 | { | |
4386 | if (current_architecture & m68040) | |
60fed2d3 | 4387 | as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); |
252b5132 RH |
4388 | } |
4389 | /* What other incompatibilities could we check for? */ | |
4390 | ||
4391 | /* Toss in some default assumptions about coprocessors. */ | |
4392 | if (!no_68881 | |
4393 | && (cpu_of_arch (current_architecture) | |
4394 | /* Can CPU32 have a 68881 coprocessor?? */ | |
4395 | & (m68020 | m68030 | cpu32))) | |
60fed2d3 NC |
4396 | current_architecture |= m68881; |
4397 | ||
252b5132 RH |
4398 | if (!no_68851 |
4399 | && (cpu_of_arch (current_architecture) & m68020up) != 0 | |
4400 | && (cpu_of_arch (current_architecture) & m68040up) == 0) | |
60fed2d3 NC |
4401 | current_architecture |= m68851; |
4402 | ||
252b5132 RH |
4403 | if (no_68881 && (current_architecture & m68881)) |
4404 | as_bad (_("options for 68881 and no-68881 both given")); | |
60fed2d3 | 4405 | |
252b5132 RH |
4406 | if (no_68851 && (current_architecture & m68851)) |
4407 | as_bad (_("options for 68851 and no-68851 both given")); | |
4408 | ||
4409 | #ifdef OBJ_AOUT | |
4410 | /* Work out the magic number. This isn't very general. */ | |
4411 | if (current_architecture & m68000) | |
4412 | m68k_aout_machtype = 0; | |
4413 | else if (current_architecture & m68010) | |
4414 | m68k_aout_machtype = 1; | |
4415 | else if (current_architecture & m68020) | |
4416 | m68k_aout_machtype = 2; | |
4417 | else | |
4418 | m68k_aout_machtype = 2; | |
4419 | #endif | |
4420 | ||
4421 | /* Note which set of "movec" control registers is available. */ | |
4422 | select_control_regs (); | |
4423 | ||
4424 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 4425 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
4426 | md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; |
4427 | } | |
4428 | \f | |
4429 | /* This is called when a label is defined. */ | |
4430 | ||
4431 | void | |
31302357 | 4432 | m68k_frob_label (symbolS *sym) |
252b5132 RH |
4433 | { |
4434 | struct label_line *n; | |
4435 | ||
4436 | n = (struct label_line *) xmalloc (sizeof *n); | |
4437 | n->next = labels; | |
4438 | n->label = sym; | |
4439 | as_where (&n->file, &n->line); | |
4440 | n->text = 0; | |
4441 | labels = n; | |
4442 | current_label = n; | |
4443 | } | |
4444 | ||
4445 | /* This is called when a value that is not an instruction is emitted. */ | |
4446 | ||
4447 | void | |
31302357 | 4448 | m68k_flush_pending_output (void) |
252b5132 RH |
4449 | { |
4450 | current_label = NULL; | |
4451 | } | |
4452 | ||
4453 | /* This is called at the end of the assembly, when the final value of | |
4454 | the label is known. We warn if this is a text symbol aligned at an | |
4455 | odd location. */ | |
4456 | ||
4457 | void | |
31302357 | 4458 | m68k_frob_symbol (symbolS *sym) |
252b5132 RH |
4459 | { |
4460 | if (S_GET_SEGMENT (sym) == reg_section | |
4461 | && (int) S_GET_VALUE (sym) < 0) | |
4462 | { | |
4463 | S_SET_SEGMENT (sym, absolute_section); | |
4464 | S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); | |
4465 | } | |
4466 | else if ((S_GET_VALUE (sym) & 1) != 0) | |
4467 | { | |
4468 | struct label_line *l; | |
4469 | ||
4470 | for (l = labels; l != NULL; l = l->next) | |
4471 | { | |
4472 | if (l->label == sym) | |
4473 | { | |
4474 | if (l->text) | |
4475 | as_warn_where (l->file, l->line, | |
4476 | _("text label `%s' aligned to odd boundary"), | |
4477 | S_GET_NAME (sym)); | |
4478 | break; | |
4479 | } | |
4480 | } | |
4481 | } | |
4482 | } | |
4483 | \f | |
4484 | /* This is called if we go in or out of MRI mode because of the .mri | |
4485 | pseudo-op. */ | |
4486 | ||
4487 | void | |
31302357 | 4488 | m68k_mri_mode_change (int on) |
252b5132 RH |
4489 | { |
4490 | if (on) | |
4491 | { | |
4492 | if (! flag_reg_prefix_optional) | |
4493 | { | |
4494 | flag_reg_prefix_optional = 1; | |
4495 | #ifdef REGISTER_PREFIX | |
4496 | init_regtable (); | |
4497 | #endif | |
4498 | } | |
4499 | m68k_abspcadd = 1; | |
4500 | if (! m68k_rel32_from_cmdline) | |
4501 | m68k_rel32 = 0; | |
4502 | } | |
4503 | else | |
4504 | { | |
4505 | if (! reg_prefix_optional_seen) | |
4506 | { | |
4507 | #ifdef REGISTER_PREFIX_OPTIONAL | |
4508 | flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; | |
4509 | #else | |
4510 | flag_reg_prefix_optional = 0; | |
4511 | #endif | |
4512 | #ifdef REGISTER_PREFIX | |
4513 | init_regtable (); | |
4514 | #endif | |
4515 | } | |
4516 | m68k_abspcadd = 0; | |
4517 | if (! m68k_rel32_from_cmdline) | |
4518 | m68k_rel32 = 1; | |
4519 | } | |
4520 | } | |
4521 | ||
36759679 | 4522 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
252b5132 RH |
4523 | #define MAX_LITTLENUMS 6 |
4524 | ||
4525 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
4526 | of type TYPE, and store the appropriate bytes in *LITP. The number |
4527 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
4528 | returned, or NULL on OK. */ |
4529 | ||
4530 | char * | |
31302357 | 4531 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
4532 | { |
4533 | int prec; | |
4534 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4535 | LITTLENUM_TYPE *wordP; | |
4536 | char *t; | |
4537 | ||
4538 | switch (type) | |
4539 | { | |
4540 | case 'f': | |
4541 | case 'F': | |
4542 | case 's': | |
4543 | case 'S': | |
4544 | prec = 2; | |
4545 | break; | |
4546 | ||
4547 | case 'd': | |
4548 | case 'D': | |
4549 | case 'r': | |
4550 | case 'R': | |
4551 | prec = 4; | |
4552 | break; | |
4553 | ||
4554 | case 'x': | |
4555 | case 'X': | |
4556 | prec = 6; | |
4557 | break; | |
4558 | ||
4559 | case 'p': | |
4560 | case 'P': | |
4561 | prec = 6; | |
4562 | break; | |
4563 | ||
4564 | default: | |
4565 | *sizeP = 0; | |
4566 | return _("Bad call to MD_ATOF()"); | |
4567 | } | |
4568 | t = atof_ieee (input_line_pointer, type, words); | |
4569 | if (t) | |
4570 | input_line_pointer = t; | |
4571 | ||
4572 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4573 | for (wordP = words; prec--;) | |
4574 | { | |
4575 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); | |
4576 | litP += sizeof (LITTLENUM_TYPE); | |
4577 | } | |
4578 | return 0; | |
4579 | } | |
4580 | ||
4581 | void | |
31302357 | 4582 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
4583 | { |
4584 | number_to_chars_bigendian (buf, val, n); | |
4585 | } | |
4586 | ||
94f592af | 4587 | void |
31302357 | 4588 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 4589 | { |
bbe8ef22 | 4590 | offsetT val = *valP; |
252b5132 RH |
4591 | addressT upper_limit; |
4592 | offsetT lower_limit; | |
4593 | ||
4594 | /* This is unnecessary but it convinces the native rs6000 compiler | |
4595 | to generate the code we want. */ | |
4596 | char *buf = fixP->fx_frag->fr_literal; | |
4597 | buf += fixP->fx_where; | |
36759679 | 4598 | /* End ibm compiler workaround. */ |
252b5132 | 4599 | |
c801568a | 4600 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
252b5132 | 4601 | |
94f592af NC |
4602 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) |
4603 | fixP->fx_done = 1; | |
4604 | ||
252b5132 RH |
4605 | #ifdef OBJ_ELF |
4606 | if (fixP->fx_addsy) | |
4607 | { | |
4608 | memset (buf, 0, fixP->fx_size); | |
36759679 | 4609 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
4610 | |
4611 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
4612 | && !S_IS_DEFINED (fixP->fx_addsy) | |
4613 | && !S_IS_WEAK (fixP->fx_addsy)) | |
4614 | S_SET_WEAK (fixP->fx_addsy); | |
4615 | return; | |
4616 | } | |
4617 | #endif | |
4618 | ||
4619 | #ifdef BFD_ASSEMBLER | |
4620 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
4621 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4622 | return; | |
4623 | #endif | |
4624 | ||
4625 | switch (fixP->fx_size) | |
4626 | { | |
94f592af NC |
4627 | /* The cast to offsetT below are necessary to make code |
4628 | correct for machines where ints are smaller than offsetT. */ | |
252b5132 RH |
4629 | case 1: |
4630 | *buf++ = val; | |
4631 | upper_limit = 0x7f; | |
4632 | lower_limit = - (offsetT) 0x80; | |
4633 | break; | |
4634 | case 2: | |
4635 | *buf++ = (val >> 8); | |
4636 | *buf++ = val; | |
4637 | upper_limit = 0x7fff; | |
4638 | lower_limit = - (offsetT) 0x8000; | |
4639 | break; | |
4640 | case 4: | |
4641 | *buf++ = (val >> 24); | |
4642 | *buf++ = (val >> 16); | |
4643 | *buf++ = (val >> 8); | |
4644 | *buf++ = val; | |
4645 | upper_limit = 0x7fffffff; | |
36759679 | 4646 | lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ |
252b5132 RH |
4647 | break; |
4648 | default: | |
4649 | BAD_CASE (fixP->fx_size); | |
4650 | } | |
4651 | ||
4652 | /* Fix up a negative reloc. */ | |
4653 | if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) | |
4654 | { | |
4655 | fixP->fx_addsy = fixP->fx_subsy; | |
4656 | fixP->fx_subsy = NULL; | |
4657 | fixP->fx_tcbit = 1; | |
4658 | } | |
4659 | ||
4660 | /* For non-pc-relative values, it's conceivable we might get something | |
4661 | like "0xff" for a byte field. So extend the upper part of the range | |
4662 | to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", | |
4663 | so that we can do any range checking at all. */ | |
4664 | if (! fixP->fx_pcrel && ! fixP->fx_signed) | |
4665 | upper_limit = upper_limit * 2 + 1; | |
4666 | ||
4667 | if ((addressT) val > upper_limit | |
4668 | && (val > 0 || val < lower_limit)) | |
4669 | as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range")); | |
4670 | ||
4671 | /* A one byte PC-relative reloc means a short branch. We can't use | |
4672 | a short branch with a value of 0 or -1, because those indicate | |
4673 | different opcodes (branches with longer offsets). fixup_segment | |
4674 | in write.c may have clobbered fx_pcrel, so we need to examine the | |
4675 | reloc type. */ | |
4676 | if ((fixP->fx_pcrel | |
4677 | #ifdef BFD_ASSEMBLER | |
4678 | || fixP->fx_r_type == BFD_RELOC_8_PCREL | |
4679 | #endif | |
4680 | ) | |
4681 | && fixP->fx_size == 1 | |
4682 | && (fixP->fx_addsy == NULL | |
4683 | || S_IS_DEFINED (fixP->fx_addsy)) | |
4684 | && (val == 0 || val == -1)) | |
4685 | as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset")); | |
4686 | } | |
4687 | ||
252b5132 RH |
4688 | /* *fragP has been relaxed to its final size, and now needs to have |
4689 | the bytes inside it modified to conform to the new size There is UGLY | |
4690 | MAGIC here. .. | |
4691 | */ | |
4692 | static void | |
31302357 | 4693 | md_convert_frag_1 (fragS *fragP) |
252b5132 RH |
4694 | { |
4695 | long disp; | |
252b5132 RH |
4696 | fixS *fixP; |
4697 | ||
4698 | /* Address in object code of the displacement. */ | |
4699 | register int object_address = fragP->fr_fix + fragP->fr_address; | |
4700 | ||
4701 | /* Address in gas core of the place to store the displacement. */ | |
4702 | /* This convinces the native rs6000 compiler to generate the code we | |
92774660 | 4703 | want. */ |
252b5132 RH |
4704 | register char *buffer_address = fragP->fr_literal; |
4705 | buffer_address += fragP->fr_fix; | |
36759679 | 4706 | /* End ibm compiler workaround. */ |
252b5132 RH |
4707 | |
4708 | /* The displacement of the address, from current location. */ | |
4709 | disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; | |
4710 | disp = (disp + fragP->fr_offset) - object_address; | |
4711 | ||
252b5132 RH |
4712 | switch (fragP->fr_subtype) |
4713 | { | |
151337e8 NC |
4714 | case TAB (BRANCHBWL, BYTE): |
4715 | case TAB (BRABSJUNC, BYTE): | |
4716 | case TAB (BRABSJCOND, BYTE): | |
4717 | case TAB (BRANCHBW, BYTE): | |
252b5132 RH |
4718 | know (issbyte (disp)); |
4719 | if (disp == 0) | |
b091f402 AM |
4720 | as_bad_where (fragP->fr_file, fragP->fr_line, |
4721 | _("short branch with zero offset: use :w")); | |
151337e8 | 4722 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
5cbdaa77 | 4723 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
151337e8 | 4724 | fixP->fx_pcrel_adjust = -1; |
252b5132 | 4725 | break; |
151337e8 NC |
4726 | case TAB (BRANCHBWL, SHORT): |
4727 | case TAB (BRABSJUNC, SHORT): | |
4728 | case TAB (BRABSJCOND, SHORT): | |
4729 | case TAB (BRANCHBW, SHORT): | |
252b5132 | 4730 | fragP->fr_opcode[1] = 0x00; |
151337e8 | 4731 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset, |
5cbdaa77 | 4732 | 1, RELAX_RELOC_PC16); |
151337e8 NC |
4733 | fragP->fr_fix += 2; |
4734 | break; | |
4735 | case TAB (BRANCHBWL, LONG): | |
4736 | fragP->fr_opcode[1] = (char) 0xFF; | |
4737 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, | |
5cbdaa77 | 4738 | 1, RELAX_RELOC_PC32); |
151337e8 | 4739 | fragP->fr_fix += 4; |
252b5132 | 4740 | break; |
151337e8 NC |
4741 | case TAB (BRABSJUNC, LONG): |
4742 | if (fragP->fr_opcode[0] == 0x61) /* jbsr */ | |
252b5132 | 4743 | { |
36759679 | 4744 | if (flag_keep_pcrel) |
6b6e92f4 | 4745 | as_fatal (_("Tried to convert PC relative BSR to absolute JSR")); |
151337e8 | 4746 | fragP->fr_opcode[0] = 0x4E; |
36759679 | 4747 | fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ |
151337e8 | 4748 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
3ae647a0 | 4749 | 0, RELAX_RELOC_ABS32); |
151337e8 NC |
4750 | fragP->fr_fix += 4; |
4751 | } | |
4752 | else if (fragP->fr_opcode[0] == 0x60) /* jbra */ | |
4753 | { | |
36759679 | 4754 | if (flag_keep_pcrel) |
6b6e92f4 | 4755 | as_fatal (_("Tried to convert PC relative branch to absolute jump")); |
151337e8 | 4756 | fragP->fr_opcode[0] = 0x4E; |
36759679 | 4757 | fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ |
151337e8 | 4758 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
5cbdaa77 | 4759 | 0, RELAX_RELOC_ABS32); |
151337e8 | 4760 | fragP->fr_fix += 4; |
252b5132 RH |
4761 | } |
4762 | else | |
4763 | { | |
151337e8 NC |
4764 | /* This cannot happen, because jbsr and jbra are the only two |
4765 | unconditional branches. */ | |
4766 | abort (); | |
252b5132 RH |
4767 | } |
4768 | break; | |
151337e8 | 4769 | case TAB (BRABSJCOND, LONG): |
36759679 | 4770 | if (flag_keep_pcrel) |
6b6e92f4 | 4771 | as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); |
92774660 | 4772 | |
36759679 NC |
4773 | /* Only Bcc 68000 instructions can come here |
4774 | Change bcc into b!cc/jmp absl long. */ | |
4775 | fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ | |
4776 | fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ | |
252b5132 RH |
4777 | |
4778 | /* JF: these used to be fr_opcode[2,3], but they may be in a | |
67c1ffbe | 4779 | different frag, in which case referring to them is a no-no. |
92774660 | 4780 | Only fr_opcode[0,1] are guaranteed to work. */ |
252b5132 RH |
4781 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ |
4782 | *buffer_address++ = (char) 0xf9; | |
36759679 | 4783 | fragP->fr_fix += 2; /* Account for jmp instruction. */ |
252b5132 | 4784 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5cbdaa77 | 4785 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); |
151337e8 NC |
4786 | fragP->fr_fix += 4; |
4787 | break; | |
4788 | case TAB (FBRANCH, SHORT): | |
4789 | know ((fragP->fr_opcode[1] & 0x40) == 0); | |
4790 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset, | |
5cbdaa77 | 4791 | 1, RELAX_RELOC_PC16); |
151337e8 NC |
4792 | fragP->fr_fix += 2; |
4793 | break; | |
4794 | case TAB (FBRANCH, LONG): | |
36759679 | 4795 | fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ |
151337e8 | 4796 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, |
5cbdaa77 | 4797 | 1, RELAX_RELOC_PC32); |
252b5132 | 4798 | fragP->fr_fix += 4; |
252b5132 | 4799 | break; |
151337e8 NC |
4800 | case TAB (DBCCLBR, SHORT): |
4801 | case TAB (DBCCABSJ, SHORT): | |
4802 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset, | |
5cbdaa77 | 4803 | 1, RELAX_RELOC_PC16); |
151337e8 NC |
4804 | fragP->fr_fix += 2; |
4805 | break; | |
4806 | case TAB (DBCCLBR, LONG): | |
36759679 NC |
4807 | /* Only DBcc instructions can come here. |
4808 | Change dbcc into dbcc/bral. | |
4809 | JF: these used to be fr_opcode[2-7], but that's wrong. */ | |
4810 | if (flag_keep_pcrel) | |
6b6e92f4 | 4811 | as_fatal (_("Tried to convert DBcc to absolute jump")); |
28e7409f | 4812 | |
36759679 | 4813 | *buffer_address++ = 0x00; /* Branch offset = 4. */ |
252b5132 | 4814 | *buffer_address++ = 0x04; |
36759679 | 4815 | *buffer_address++ = 0x60; /* Put in bra pc+6. */ |
252b5132 | 4816 | *buffer_address++ = 0x06; |
151337e8 NC |
4817 | *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ |
4818 | *buffer_address++ = (char) 0xff; | |
252b5132 | 4819 | |
36759679 | 4820 | fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ |
151337e8 | 4821 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1, |
5cbdaa77 | 4822 | RELAX_RELOC_PC32); |
252b5132 | 4823 | fragP->fr_fix += 4; |
252b5132 | 4824 | break; |
151337e8 | 4825 | case TAB (DBCCABSJ, LONG): |
36759679 NC |
4826 | /* Only DBcc instructions can come here. |
4827 | Change dbcc into dbcc/jmp. | |
4828 | JF: these used to be fr_opcode[2-7], but that's wrong. */ | |
4829 | if (flag_keep_pcrel) | |
6b6e92f4 | 4830 | as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); |
151337e8 | 4831 | |
36759679 | 4832 | *buffer_address++ = 0x00; /* Branch offset = 4. */ |
151337e8 | 4833 | *buffer_address++ = 0x04; |
36759679 | 4834 | *buffer_address++ = 0x60; /* Put in bra pc + 6. */ |
151337e8 | 4835 | *buffer_address++ = 0x06; |
36759679 | 4836 | *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ |
151337e8 NC |
4837 | *buffer_address++ = (char) 0xf9; |
4838 | ||
36759679 | 4839 | fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ |
151337e8 | 4840 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, |
5cbdaa77 | 4841 | RELAX_RELOC_ABS32); |
252b5132 | 4842 | fragP->fr_fix += 4; |
252b5132 | 4843 | break; |
151337e8 | 4844 | case TAB (PCREL1632, SHORT): |
252b5132 RH |
4845 | fragP->fr_opcode[1] &= ~0x3F; |
4846 | fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ | |
151337e8 | 4847 | fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, |
5cbdaa77 | 4848 | fragP->fr_offset, 1, RELAX_RELOC_PC16); |
151337e8 | 4849 | fragP->fr_fix += 2; |
252b5132 | 4850 | break; |
151337e8 | 4851 | case TAB (PCREL1632, LONG): |
252b5132 RH |
4852 | /* Already set to mode 7.3; this indicates: PC indirect with |
4853 | suppressed index, 32-bit displacement. */ | |
4854 | *buffer_address++ = 0x01; | |
4855 | *buffer_address++ = 0x70; | |
4856 | fragP->fr_fix += 2; | |
151337e8 | 4857 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
5cbdaa77 | 4858 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
151337e8 NC |
4859 | fixP->fx_pcrel_adjust = 2; |
4860 | fragP->fr_fix += 4; | |
252b5132 | 4861 | break; |
252b5132 | 4862 | case TAB (PCINDEX, BYTE): |
252b5132 RH |
4863 | assert (fragP->fr_fix >= 2); |
4864 | buffer_address[-2] &= ~1; | |
151337e8 | 4865 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
5cbdaa77 | 4866 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
151337e8 | 4867 | fixP->fx_pcrel_adjust = 1; |
252b5132 RH |
4868 | break; |
4869 | case TAB (PCINDEX, SHORT): | |
252b5132 RH |
4870 | assert (fragP->fr_fix >= 2); |
4871 | buffer_address[-2] |= 0x1; | |
4872 | buffer_address[-1] = 0x20; | |
4873 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, | |
5cbdaa77 | 4874 | fragP->fr_offset, 1, RELAX_RELOC_PC16); |
252b5132 | 4875 | fixP->fx_pcrel_adjust = 2; |
151337e8 | 4876 | fragP->fr_fix += 2; |
252b5132 RH |
4877 | break; |
4878 | case TAB (PCINDEX, LONG): | |
252b5132 RH |
4879 | assert (fragP->fr_fix >= 2); |
4880 | buffer_address[-2] |= 0x1; | |
4881 | buffer_address[-1] = 0x30; | |
151337e8 | 4882 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
5cbdaa77 | 4883 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
151337e8 NC |
4884 | fixP->fx_pcrel_adjust = 2; |
4885 | fragP->fr_fix += 4; | |
4886 | break; | |
4887 | case TAB (ABSTOPCREL, SHORT): | |
4888 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset, | |
5cbdaa77 | 4889 | 1, RELAX_RELOC_PC16); |
151337e8 NC |
4890 | fragP->fr_fix += 2; |
4891 | break; | |
4892 | case TAB (ABSTOPCREL, LONG): | |
36759679 | 4893 | if (flag_keep_pcrel) |
6b6e92f4 | 4894 | as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); |
151337e8 | 4895 | /* The thing to do here is force it to ABSOLUTE LONG, since |
36759679 | 4896 | ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ |
151337e8 NC |
4897 | if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) |
4898 | abort (); | |
4899 | fragP->fr_opcode[1] &= ~0x3F; | |
4900 | fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ | |
4901 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, | |
5cbdaa77 | 4902 | 0, RELAX_RELOC_ABS32); |
151337e8 | 4903 | fragP->fr_fix += 4; |
252b5132 | 4904 | break; |
252b5132 RH |
4905 | } |
4906 | } | |
4907 | ||
4908 | #ifndef BFD_ASSEMBLER | |
4909 | ||
4910 | void | |
31302357 AS |
4911 | md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED, |
4912 | segT sec ATTRIBUTE_UNUSED, | |
4913 | fragS *fragP) | |
252b5132 RH |
4914 | { |
4915 | md_convert_frag_1 (fragP); | |
4916 | } | |
4917 | ||
4918 | #else | |
4919 | ||
4920 | void | |
31302357 AS |
4921 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
4922 | segT sec ATTRIBUTE_UNUSED, | |
4923 | fragS *fragP) | |
252b5132 RH |
4924 | { |
4925 | md_convert_frag_1 (fragP); | |
4926 | } | |
4927 | #endif | |
4928 | ||
4929 | /* Force truly undefined symbols to their maximum size, and generally set up | |
4930 | the frag list to be relaxed | |
4931 | */ | |
4932 | int | |
31302357 | 4933 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 4934 | { |
151337e8 | 4935 | /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ |
252b5132 RH |
4936 | switch (fragP->fr_subtype) |
4937 | { | |
151337e8 NC |
4938 | case TAB (BRANCHBWL, SZ_UNDEF): |
4939 | case TAB (BRABSJUNC, SZ_UNDEF): | |
151337e8 | 4940 | case TAB (BRABSJCOND, SZ_UNDEF): |
252b5132 | 4941 | { |
151337e8 NC |
4942 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
4943 | && relaxable_symbol (fragP->fr_symbol)) | |
252b5132 | 4944 | { |
151337e8 NC |
4945 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
4946 | } | |
4947 | else if (flag_short_refs) | |
4948 | { | |
4949 | /* Symbol is undefined and we want short ref. */ | |
4950 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
4951 | } |
4952 | else | |
4953 | { | |
151337e8 NC |
4954 | /* Symbol is still undefined. Make it LONG. */ |
4955 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); | |
252b5132 RH |
4956 | } |
4957 | break; | |
151337e8 | 4958 | } |
252b5132 | 4959 | |
151337e8 | 4960 | case TAB (BRANCHBW, SZ_UNDEF): |
252b5132 | 4961 | { |
151337e8 NC |
4962 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
4963 | && relaxable_symbol (fragP->fr_symbol)) | |
252b5132 | 4964 | { |
151337e8 | 4965 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
252b5132 RH |
4966 | } |
4967 | else | |
4968 | { | |
151337e8 NC |
4969 | /* Symbol is undefined and we don't have long branches. */ |
4970 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
4971 | } |
4972 | break; | |
151337e8 | 4973 | } |
252b5132 | 4974 | |
151337e8 | 4975 | case TAB (FBRANCH, SZ_UNDEF): |
151337e8 NC |
4976 | case TAB (DBCCLBR, SZ_UNDEF): |
4977 | case TAB (DBCCABSJ, SZ_UNDEF): | |
5c65dbc1 | 4978 | case TAB (PCREL1632, SZ_UNDEF): |
252b5132 | 4979 | { |
8ec6253e NC |
4980 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment |
4981 | && relaxable_symbol (fragP->fr_symbol)) | |
151337e8 | 4982 | || flag_short_refs) |
252b5132 | 4983 | { |
151337e8 | 4984 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); |
252b5132 RH |
4985 | } |
4986 | else | |
4987 | { | |
151337e8 | 4988 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); |
252b5132 RH |
4989 | } |
4990 | break; | |
151337e8 | 4991 | } |
81d4177b | 4992 | |
252b5132 RH |
4993 | case TAB (PCINDEX, SZ_UNDEF): |
4994 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment | |
151337e8 | 4995 | && relaxable_symbol (fragP->fr_symbol))) |
252b5132 RH |
4996 | { |
4997 | fragP->fr_subtype = TAB (PCINDEX, BYTE); | |
4998 | } | |
4999 | else | |
5000 | { | |
5001 | fragP->fr_subtype = TAB (PCINDEX, LONG); | |
252b5132 RH |
5002 | } |
5003 | break; | |
5004 | ||
151337e8 NC |
5005 | case TAB (ABSTOPCREL, SZ_UNDEF): |
5006 | { | |
5007 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment | |
5008 | && relaxable_symbol (fragP->fr_symbol))) | |
5009 | { | |
5010 | fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); | |
151337e8 NC |
5011 | } |
5012 | else | |
5013 | { | |
5014 | fragP->fr_subtype = TAB (ABSTOPCREL, LONG); | |
151337e8 NC |
5015 | } |
5016 | break; | |
5017 | } | |
5018 | ||
252b5132 RH |
5019 | default: |
5020 | break; | |
5021 | } | |
5022 | ||
151337e8 | 5023 | /* Now that SZ_UNDEF are taken care of, check others. */ |
252b5132 RH |
5024 | switch (fragP->fr_subtype) |
5025 | { | |
151337e8 NC |
5026 | case TAB (BRANCHBWL, BYTE): |
5027 | case TAB (BRABSJUNC, BYTE): | |
5028 | case TAB (BRABSJCOND, BYTE): | |
5029 | case TAB (BRANCHBW, BYTE): | |
252b5132 | 5030 | /* We can't do a short jump to the next instruction, so in that |
ac62c346 AM |
5031 | case we force word mode. If the symbol is at the start of a |
5032 | frag, and it is the next frag with any data in it (usually | |
5033 | this is just the next frag, but assembler listings may | |
5034 | introduce empty frags), we must use word mode. */ | |
5035 | if (fragP->fr_symbol) | |
252b5132 | 5036 | { |
ac62c346 | 5037 | fragS *sym_frag; |
252b5132 | 5038 | |
ac62c346 AM |
5039 | sym_frag = symbol_get_frag (fragP->fr_symbol); |
5040 | if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) | |
252b5132 | 5041 | { |
ac62c346 AM |
5042 | fragS *l; |
5043 | ||
23b7f870 | 5044 | for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) |
ac62c346 AM |
5045 | if (l->fr_fix != 0) |
5046 | break; | |
5047 | if (l == sym_frag) | |
5048 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5049 | } |
5050 | } | |
5051 | break; | |
5052 | default: | |
5053 | break; | |
5054 | } | |
ac62c346 | 5055 | return md_relax_table[fragP->fr_subtype].rlx_length; |
252b5132 RH |
5056 | } |
5057 | ||
5058 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
5059 | /* the bit-field entries in the relocation_info struct plays hell | |
5060 | with the byte-order problems of cross-assembly. So as a hack, | |
5061 | I added this mach. dependent ri twiddler. Ugly, but it gets | |
36759679 | 5062 | you there. -KWK */ |
252b5132 RH |
5063 | /* on m68k: first 4 bytes are normal unsigned long, next three bytes |
5064 | are symbolnum, most sig. byte first. Last byte is broken up with | |
5065 | bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower | |
5066 | nibble as nuthin. (on Sun 3 at least) */ | |
5067 | /* Translate the internal relocation information into target-specific | |
92774660 | 5068 | format. */ |
252b5132 RH |
5069 | #ifdef comment |
5070 | void | |
31302357 | 5071 | md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri) |
252b5132 | 5072 | { |
36759679 | 5073 | /* This is easy. */ |
252b5132 | 5074 | md_number_to_chars (the_bytes, ri->r_address, 4); |
36759679 | 5075 | /* Now the fun stuff. */ |
252b5132 | 5076 | the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; |
36759679 NC |
5077 | the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; |
5078 | the_bytes[6] = ri->r_symbolnum & 0x0ff; | |
31302357 AS |
5079 | the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) |
5080 | | ((ri->r_length << 5) & 0x60) | |
5081 | | ((ri->r_extern << 4) & 0x10)); | |
252b5132 RH |
5082 | } |
5083 | ||
36759679 | 5084 | #endif |
252b5132 RH |
5085 | |
5086 | #ifndef BFD_ASSEMBLER | |
5087 | void | |
31302357 AS |
5088 | tc_aout_fix_to_chars (char *where, fixS *fixP, |
5089 | relax_addressT segment_address_in_file) | |
252b5132 RH |
5090 | { |
5091 | /* | |
5092 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
5093 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
5094 | */ | |
5095 | ||
5a38dc70 | 5096 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
252b5132 RH |
5097 | long r_symbolnum; |
5098 | ||
5099 | know (fixP->fx_addsy != NULL); | |
5100 | ||
5101 | md_number_to_chars (where, | |
31302357 AS |
5102 | (fixP->fx_frag->fr_address |
5103 | + fixP->fx_where - segment_address_in_file), 4); | |
252b5132 RH |
5104 | |
5105 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
5106 | ? S_GET_TYPE (fixP->fx_addsy) | |
5107 | : fixP->fx_addsy->sy_number); | |
5108 | ||
5109 | where[4] = (r_symbolnum >> 16) & 0x0ff; | |
5110 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
5111 | where[6] = r_symbolnum & 0x0ff; | |
31302357 AS |
5112 | where[7] = (((fixP->fx_pcrel << 7) & 0x80) |
5113 | | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) | |
5114 | | ((!S_IS_DEFINED (fixP->fx_addsy) << 4) & 0x10)); | |
252b5132 RH |
5115 | } |
5116 | #endif | |
5117 | ||
5118 | #endif /* OBJ_AOUT or OBJ_BOUT */ | |
5119 | ||
5120 | #ifndef WORKING_DOT_WORD | |
5a38dc70 AM |
5121 | const int md_short_jump_size = 4; |
5122 | const int md_long_jump_size = 6; | |
252b5132 RH |
5123 | |
5124 | void | |
31302357 AS |
5125 | md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, |
5126 | fragS *frag ATTRIBUTE_UNUSED, | |
5127 | symbolS *to_symbol ATTRIBUTE_UNUSED) | |
252b5132 RH |
5128 | { |
5129 | valueT offset; | |
5130 | ||
5131 | offset = to_addr - (from_addr + 2); | |
5132 | ||
5133 | md_number_to_chars (ptr, (valueT) 0x6000, 2); | |
5134 | md_number_to_chars (ptr + 2, (valueT) offset, 2); | |
5135 | } | |
5136 | ||
5137 | void | |
31302357 AS |
5138 | md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, |
5139 | fragS *frag, symbolS *to_symbol) | |
252b5132 RH |
5140 | { |
5141 | valueT offset; | |
5142 | ||
6b6e92f4 | 5143 | if (!HAVE_LONG_BRANCH (current_architecture)) |
252b5132 | 5144 | { |
36759679 | 5145 | if (flag_keep_pcrel) |
6b6e92f4 | 5146 | as_fatal (_("Tried to convert PC relative branch to absolute jump")); |
252b5132 RH |
5147 | offset = to_addr - S_GET_VALUE (to_symbol); |
5148 | md_number_to_chars (ptr, (valueT) 0x4EF9, 2); | |
5149 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
5150 | fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, | |
5151 | 0, NO_RELOC); | |
5152 | } | |
5153 | else | |
5154 | { | |
5155 | offset = to_addr - (from_addr + 2); | |
5156 | md_number_to_chars (ptr, (valueT) 0x60ff, 2); | |
5157 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
5158 | } | |
5159 | } | |
5160 | ||
5161 | #endif | |
5162 | ||
5163 | /* Different values of OK tell what its OK to return. Things that | |
5164 | aren't OK are an error (what a shock, no?) | |
5165 | ||
5166 | 0: Everything is OK | |
3e602632 NC |
5167 | 10: Absolute 1:8 only |
5168 | 20: Absolute 0:7 only | |
5169 | 30: absolute 0:15 only | |
5170 | 40: Absolute 0:31 only | |
5171 | 50: absolute 0:127 only | |
252b5132 | 5172 | 55: absolute -64:63 only |
3e602632 NC |
5173 | 60: absolute -128:127 only |
5174 | 70: absolute 0:4095 only | |
5175 | 80: absolute -1, 1:7 only | |
5176 | 90: No bignums. */ | |
252b5132 RH |
5177 | |
5178 | static int | |
31302357 | 5179 | get_num (struct m68k_exp *exp, int ok) |
252b5132 RH |
5180 | { |
5181 | if (exp->exp.X_op == O_absent) | |
5182 | { | |
36759679 | 5183 | /* Do the same thing the VAX asm does. */ |
252b5132 RH |
5184 | op (exp) = O_constant; |
5185 | adds (exp) = 0; | |
5186 | subs (exp) = 0; | |
5187 | offs (exp) = 0; | |
5188 | if (ok == 10) | |
5189 | { | |
5190 | as_warn (_("expression out of range: defaulting to 1")); | |
5191 | offs (exp) = 1; | |
5192 | } | |
5193 | } | |
5194 | else if (exp->exp.X_op == O_constant) | |
5195 | { | |
5196 | switch (ok) | |
5197 | { | |
5198 | case 10: | |
5199 | if (offs (exp) < 1 || offs (exp) > 8) | |
5200 | { | |
5201 | as_warn (_("expression out of range: defaulting to 1")); | |
5202 | offs (exp) = 1; | |
5203 | } | |
5204 | break; | |
5205 | case 20: | |
5206 | if (offs (exp) < 0 || offs (exp) > 7) | |
5207 | goto outrange; | |
5208 | break; | |
5209 | case 30: | |
5210 | if (offs (exp) < 0 || offs (exp) > 15) | |
5211 | goto outrange; | |
5212 | break; | |
5213 | case 40: | |
5214 | if (offs (exp) < 0 || offs (exp) > 32) | |
5215 | goto outrange; | |
5216 | break; | |
5217 | case 50: | |
5218 | if (offs (exp) < 0 || offs (exp) > 127) | |
5219 | goto outrange; | |
5220 | break; | |
5221 | case 55: | |
5222 | if (offs (exp) < -64 || offs (exp) > 63) | |
5223 | goto outrange; | |
5224 | break; | |
5225 | case 60: | |
5226 | if (offs (exp) < -128 || offs (exp) > 127) | |
5227 | goto outrange; | |
5228 | break; | |
5229 | case 70: | |
5230 | if (offs (exp) < 0 || offs (exp) > 4095) | |
5231 | { | |
5232 | outrange: | |
5233 | as_warn (_("expression out of range: defaulting to 0")); | |
5234 | offs (exp) = 0; | |
5235 | } | |
5236 | break; | |
3e602632 NC |
5237 | case 80: |
5238 | if (offs (exp) < -1 | |
5239 | || offs (exp) > 7 | |
5240 | || offs (exp) == 0) | |
5241 | { | |
5242 | as_warn (_("expression out of range: defaulting to 1")); | |
5243 | offs (exp) = 1; | |
5244 | } | |
5245 | break; | |
252b5132 RH |
5246 | default: |
5247 | break; | |
5248 | } | |
5249 | } | |
5250 | else if (exp->exp.X_op == O_big) | |
5251 | { | |
36759679 | 5252 | if (offs (exp) <= 0 /* flonum. */ |
3e602632 | 5253 | && (ok == 90 /* no bignums */ |
36759679 | 5254 | || (ok > 10 /* Small-int ranges including 0 ok. */ |
252b5132 RH |
5255 | /* If we have a flonum zero, a zero integer should |
5256 | do as well (e.g., in moveq). */ | |
5257 | && generic_floating_point_number.exponent == 0 | |
5258 | && generic_floating_point_number.low[0] == 0))) | |
5259 | { | |
36759679 | 5260 | /* HACK! Turn it into a long. */ |
252b5132 RH |
5261 | LITTLENUM_TYPE words[6]; |
5262 | ||
36759679 | 5263 | gen_to_words (words, 2, 8L); /* These numbers are magic! */ |
252b5132 RH |
5264 | op (exp) = O_constant; |
5265 | adds (exp) = 0; | |
5266 | subs (exp) = 0; | |
5267 | offs (exp) = words[1] | (words[0] << 16); | |
5268 | } | |
5269 | else if (ok != 0) | |
5270 | { | |
5271 | op (exp) = O_constant; | |
5272 | adds (exp) = 0; | |
5273 | subs (exp) = 0; | |
5274 | offs (exp) = (ok == 10) ? 1 : 0; | |
5275 | as_warn (_("Can't deal with expression; defaulting to %ld"), | |
5276 | offs (exp)); | |
5277 | } | |
5278 | } | |
5279 | else | |
5280 | { | |
3e602632 | 5281 | if (ok >= 10 && ok <= 80) |
252b5132 RH |
5282 | { |
5283 | op (exp) = O_constant; | |
5284 | adds (exp) = 0; | |
5285 | subs (exp) = 0; | |
5286 | offs (exp) = (ok == 10) ? 1 : 0; | |
5287 | as_warn (_("Can't deal with expression; defaulting to %ld"), | |
5288 | offs (exp)); | |
5289 | } | |
5290 | } | |
5291 | ||
5292 | if (exp->size != SIZE_UNSPEC) | |
5293 | { | |
5294 | switch (exp->size) | |
5295 | { | |
5296 | case SIZE_UNSPEC: | |
5297 | case SIZE_LONG: | |
5298 | break; | |
5299 | case SIZE_BYTE: | |
5300 | if (!isbyte (offs (exp))) | |
5301 | as_warn (_("expression doesn't fit in BYTE")); | |
5302 | break; | |
5303 | case SIZE_WORD: | |
5304 | if (!isword (offs (exp))) | |
5305 | as_warn (_("expression doesn't fit in WORD")); | |
5306 | break; | |
5307 | } | |
5308 | } | |
5309 | ||
5310 | return offs (exp); | |
5311 | } | |
5312 | ||
5313 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
5314 | ||
5315 | static void | |
31302357 | 5316 | s_data1 (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5317 | { |
5318 | subseg_set (data_section, 1); | |
5319 | demand_empty_rest_of_line (); | |
5320 | } | |
5321 | ||
5322 | static void | |
31302357 | 5323 | s_data2 (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5324 | { |
5325 | subseg_set (data_section, 2); | |
5326 | demand_empty_rest_of_line (); | |
5327 | } | |
5328 | ||
5329 | static void | |
31302357 | 5330 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5331 | { |
5332 | /* We don't support putting frags in the BSS segment, we fake it | |
5333 | by marking in_bss, then looking at s_skip for clues. */ | |
5334 | ||
5335 | subseg_set (bss_section, 0); | |
5336 | demand_empty_rest_of_line (); | |
5337 | } | |
5338 | ||
5339 | static void | |
31302357 | 5340 | s_even (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5341 | { |
5342 | register int temp; | |
5343 | register long temp_fill; | |
5344 | ||
5345 | temp = 1; /* JF should be 2? */ | |
5346 | temp_fill = get_absolute_expression (); | |
92774660 | 5347 | if (!need_pass_2) /* Never make frag if expect extra pass. */ |
252b5132 RH |
5348 | frag_align (temp, (int) temp_fill, 0); |
5349 | demand_empty_rest_of_line (); | |
5350 | record_alignment (now_seg, temp); | |
5351 | } | |
5352 | ||
5353 | static void | |
31302357 | 5354 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5355 | { |
5356 | demand_empty_rest_of_line (); | |
5357 | } | |
5358 | \f | |
5359 | /* Pseudo-ops handled for MRI compatibility. */ | |
5360 | ||
5361 | /* This function returns non-zero if the argument is a conditional | |
5362 | pseudo-op. This is called when checking whether a pending | |
5363 | alignment is needed. */ | |
5364 | ||
5365 | int | |
31302357 | 5366 | m68k_conditional_pseudoop (pseudo_typeS *pop) |
252b5132 RH |
5367 | { |
5368 | return (pop->poc_handler == s_mri_if | |
5369 | || pop->poc_handler == s_mri_else); | |
5370 | } | |
5371 | ||
5372 | /* Handle an MRI style chip specification. */ | |
5373 | ||
5374 | static void | |
31302357 | 5375 | mri_chip (void) |
252b5132 RH |
5376 | { |
5377 | char *s; | |
5378 | char c; | |
5379 | int i; | |
5380 | ||
5381 | s = input_line_pointer; | |
5382 | /* We can't use get_symbol_end since the processor names are not proper | |
5383 | symbols. */ | |
5384 | while (is_part_of_name (c = *input_line_pointer++)) | |
5385 | ; | |
5386 | *--input_line_pointer = 0; | |
5387 | for (i = 0; i < n_archs; i++) | |
5388 | if (strcasecmp (s, archs[i].name) == 0) | |
5389 | break; | |
5390 | if (i >= n_archs) | |
5391 | { | |
5392 | as_bad (_("%s: unrecognized processor name"), s); | |
5393 | *input_line_pointer = c; | |
5394 | ignore_rest_of_line (); | |
5395 | return; | |
5396 | } | |
5397 | *input_line_pointer = c; | |
5398 | ||
5399 | if (*input_line_pointer == '/') | |
5400 | current_architecture = 0; | |
5401 | else | |
5402 | current_architecture &= m68881 | m68851; | |
5403 | current_architecture |= archs[i].arch; | |
990ae22a | 5404 | current_chip = archs[i].chip; |
252b5132 RH |
5405 | |
5406 | while (*input_line_pointer == '/') | |
5407 | { | |
5408 | ++input_line_pointer; | |
5409 | s = input_line_pointer; | |
5410 | /* We can't use get_symbol_end since the processor names are not | |
5411 | proper symbols. */ | |
5412 | while (is_part_of_name (c = *input_line_pointer++)) | |
5413 | ; | |
5414 | *--input_line_pointer = 0; | |
5415 | if (strcmp (s, "68881") == 0) | |
5416 | current_architecture |= m68881; | |
5417 | else if (strcmp (s, "68851") == 0) | |
5418 | current_architecture |= m68851; | |
5419 | *input_line_pointer = c; | |
5420 | } | |
5421 | ||
5422 | /* Update info about available control registers. */ | |
5423 | select_control_regs (); | |
5424 | } | |
5425 | ||
5426 | /* The MRI CHIP pseudo-op. */ | |
5427 | ||
5428 | static void | |
31302357 | 5429 | s_chip (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5430 | { |
5431 | char *stop = NULL; | |
5432 | char stopc; | |
5433 | ||
5434 | if (flag_mri) | |
5435 | stop = mri_comment_field (&stopc); | |
5436 | mri_chip (); | |
5437 | if (flag_mri) | |
5438 | mri_comment_end (stop, stopc); | |
5439 | demand_empty_rest_of_line (); | |
5440 | } | |
5441 | ||
5442 | /* The MRI FOPT pseudo-op. */ | |
5443 | ||
5444 | static void | |
31302357 | 5445 | s_fopt (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5446 | { |
5447 | SKIP_WHITESPACE (); | |
5448 | ||
5449 | if (strncasecmp (input_line_pointer, "ID=", 3) == 0) | |
5450 | { | |
5451 | int temp; | |
5452 | ||
5453 | input_line_pointer += 3; | |
5454 | temp = get_absolute_expression (); | |
5455 | if (temp < 0 || temp > 7) | |
5456 | as_bad (_("bad coprocessor id")); | |
5457 | else | |
5458 | m68k_float_copnum = COP0 + temp; | |
5459 | } | |
5460 | else | |
5461 | { | |
5462 | as_bad (_("unrecognized fopt option")); | |
5463 | ignore_rest_of_line (); | |
5464 | return; | |
5465 | } | |
5466 | ||
5467 | demand_empty_rest_of_line (); | |
5468 | } | |
5469 | ||
5470 | /* The structure used to handle the MRI OPT pseudo-op. */ | |
5471 | ||
5472 | struct opt_action | |
5473 | { | |
5474 | /* The name of the option. */ | |
5475 | const char *name; | |
5476 | ||
5477 | /* If this is not NULL, just call this function. The first argument | |
5478 | is the ARG field of this structure, the second argument is | |
5479 | whether the option was negated. */ | |
31302357 | 5480 | void (*pfn) (int arg, int on); |
252b5132 RH |
5481 | |
5482 | /* If this is not NULL, and the PFN field is NULL, set the variable | |
5483 | this points to. Set it to the ARG field if the option was not | |
5484 | negated, and the NOTARG field otherwise. */ | |
5485 | int *pvar; | |
5486 | ||
5487 | /* The value to pass to PFN or to assign to *PVAR. */ | |
5488 | int arg; | |
5489 | ||
5490 | /* The value to assign to *PVAR if the option is negated. If PFN is | |
5491 | NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then | |
5492 | the option may not be negated. */ | |
5493 | int notarg; | |
5494 | }; | |
5495 | ||
5496 | /* The table used to handle the MRI OPT pseudo-op. */ | |
5497 | ||
31302357 AS |
5498 | static void skip_to_comma (int, int); |
5499 | static void opt_nest (int, int); | |
5500 | static void opt_chip (int, int); | |
5501 | static void opt_list (int, int); | |
5502 | static void opt_list_symbols (int, int); | |
252b5132 RH |
5503 | |
5504 | static const struct opt_action opt_table[] = | |
5505 | { | |
5506 | { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, | |
5507 | ||
5508 | /* We do relaxing, so there is little use for these options. */ | |
5509 | { "b", 0, 0, 0, 0 }, | |
5510 | { "brs", 0, 0, 0, 0 }, | |
5511 | { "brb", 0, 0, 0, 0 }, | |
5512 | { "brl", 0, 0, 0, 0 }, | |
5513 | { "brw", 0, 0, 0, 0 }, | |
5514 | ||
5515 | { "c", 0, 0, 0, 0 }, | |
5516 | { "cex", 0, 0, 0, 0 }, | |
5517 | { "case", 0, &symbols_case_sensitive, 1, 0 }, | |
5518 | { "cl", 0, 0, 0, 0 }, | |
5519 | { "cre", 0, 0, 0, 0 }, | |
5520 | { "d", 0, &flag_keep_locals, 1, 0 }, | |
5521 | { "e", 0, 0, 0, 0 }, | |
5522 | { "f", 0, &flag_short_refs, 1, 0 }, | |
5523 | { "frs", 0, &flag_short_refs, 1, 0 }, | |
5524 | { "frl", 0, &flag_short_refs, 0, 1 }, | |
5525 | { "g", 0, 0, 0, 0 }, | |
5526 | { "i", 0, 0, 0, 0 }, | |
5527 | { "m", 0, 0, 0, 0 }, | |
5528 | { "mex", 0, 0, 0, 0 }, | |
5529 | { "mc", 0, 0, 0, 0 }, | |
5530 | { "md", 0, 0, 0, 0 }, | |
5531 | { "nest", opt_nest, 0, 0, 0 }, | |
5532 | { "next", skip_to_comma, 0, 0, 0 }, | |
5533 | { "o", 0, 0, 0, 0 }, | |
5534 | { "old", 0, 0, 0, 0 }, | |
5535 | { "op", skip_to_comma, 0, 0, 0 }, | |
5536 | { "pco", 0, 0, 0, 0 }, | |
5537 | { "p", opt_chip, 0, 0, 0 }, | |
5538 | { "pcr", 0, 0, 0, 0 }, | |
5539 | { "pcs", 0, 0, 0, 0 }, | |
5540 | { "r", 0, 0, 0, 0 }, | |
5541 | { "quick", 0, &m68k_quick, 1, 0 }, | |
5542 | { "rel32", 0, &m68k_rel32, 1, 0 }, | |
5543 | { "s", opt_list, 0, 0, 0 }, | |
5544 | { "t", opt_list_symbols, 0, 0, 0 }, | |
5545 | { "w", 0, &flag_no_warnings, 0, 1 }, | |
5546 | { "x", 0, 0, 0, 0 } | |
5547 | }; | |
5548 | ||
8fce3f5e | 5549 | #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) |
252b5132 RH |
5550 | |
5551 | /* The MRI OPT pseudo-op. */ | |
5552 | ||
5553 | static void | |
31302357 | 5554 | s_opt (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5555 | { |
5556 | do | |
5557 | { | |
5558 | int t; | |
5559 | char *s; | |
5560 | char c; | |
5561 | int i; | |
5562 | const struct opt_action *o; | |
5563 | ||
5564 | SKIP_WHITESPACE (); | |
5565 | ||
5566 | t = 1; | |
5567 | if (*input_line_pointer == '-') | |
5568 | { | |
5569 | ++input_line_pointer; | |
5570 | t = 0; | |
5571 | } | |
5572 | else if (strncasecmp (input_line_pointer, "NO", 2) == 0) | |
5573 | { | |
5574 | input_line_pointer += 2; | |
5575 | t = 0; | |
5576 | } | |
5577 | ||
5578 | s = input_line_pointer; | |
5579 | c = get_symbol_end (); | |
5580 | ||
5581 | for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) | |
5582 | { | |
5583 | if (strcasecmp (s, o->name) == 0) | |
5584 | { | |
5585 | if (o->pfn) | |
5586 | { | |
5587 | /* Restore input_line_pointer now in case the option | |
5588 | takes arguments. */ | |
5589 | *input_line_pointer = c; | |
5590 | (*o->pfn) (o->arg, t); | |
5591 | } | |
5592 | else if (o->pvar != NULL) | |
5593 | { | |
5594 | if (! t && o->arg == o->notarg) | |
5595 | as_bad (_("option `%s' may not be negated"), s); | |
5596 | *input_line_pointer = c; | |
5597 | *o->pvar = t ? o->arg : o->notarg; | |
5598 | } | |
5599 | else | |
5600 | *input_line_pointer = c; | |
5601 | break; | |
5602 | } | |
5603 | } | |
5604 | if (i >= OPTCOUNT) | |
5605 | { | |
5606 | as_bad (_("option `%s' not recognized"), s); | |
5607 | *input_line_pointer = c; | |
5608 | } | |
5609 | } | |
5610 | while (*input_line_pointer++ == ','); | |
5611 | ||
5612 | /* Move back to terminating character. */ | |
5613 | --input_line_pointer; | |
5614 | demand_empty_rest_of_line (); | |
5615 | } | |
5616 | ||
5617 | /* Skip ahead to a comma. This is used for OPT options which we do | |
67c1ffbe | 5618 | not support and which take arguments. */ |
252b5132 RH |
5619 | |
5620 | static void | |
31302357 | 5621 | skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5622 | { |
5623 | while (*input_line_pointer != ',' | |
5624 | && ! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5625 | ++input_line_pointer; | |
5626 | } | |
5627 | ||
5628 | /* Handle the OPT NEST=depth option. */ | |
5629 | ||
5630 | static void | |
31302357 | 5631 | opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5632 | { |
5633 | if (*input_line_pointer != '=') | |
5634 | { | |
5635 | as_bad (_("bad format of OPT NEST=depth")); | |
5636 | return; | |
5637 | } | |
5638 | ||
5639 | ++input_line_pointer; | |
5640 | max_macro_nest = get_absolute_expression (); | |
5641 | } | |
5642 | ||
5643 | /* Handle the OPT P=chip option. */ | |
5644 | ||
5645 | static void | |
31302357 | 5646 | opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5647 | { |
5648 | if (*input_line_pointer != '=') | |
5649 | { | |
5650 | /* This is just OPT P, which we do not support. */ | |
5651 | return; | |
5652 | } | |
5653 | ||
5654 | ++input_line_pointer; | |
5655 | mri_chip (); | |
5656 | } | |
5657 | ||
5658 | /* Handle the OPT S option. */ | |
5659 | ||
5660 | static void | |
31302357 | 5661 | opt_list (int arg ATTRIBUTE_UNUSED, int on) |
252b5132 RH |
5662 | { |
5663 | listing_list (on); | |
5664 | } | |
5665 | ||
5666 | /* Handle the OPT T option. */ | |
5667 | ||
5668 | static void | |
31302357 | 5669 | opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) |
252b5132 RH |
5670 | { |
5671 | if (on) | |
5672 | listing |= LISTING_SYMBOLS; | |
5673 | else | |
8a104df9 | 5674 | listing &= ~LISTING_SYMBOLS; |
252b5132 RH |
5675 | } |
5676 | ||
5677 | /* Handle the MRI REG pseudo-op. */ | |
5678 | ||
5679 | static void | |
31302357 | 5680 | s_reg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5681 | { |
5682 | char *s; | |
5683 | int c; | |
5684 | struct m68k_op rop; | |
5685 | int mask; | |
5686 | char *stop = NULL; | |
5687 | char stopc; | |
5688 | ||
5689 | if (line_label == NULL) | |
5690 | { | |
5691 | as_bad (_("missing label")); | |
5692 | ignore_rest_of_line (); | |
5693 | return; | |
5694 | } | |
5695 | ||
5696 | if (flag_mri) | |
5697 | stop = mri_comment_field (&stopc); | |
5698 | ||
5699 | SKIP_WHITESPACE (); | |
5700 | ||
5701 | s = input_line_pointer; | |
3882b010 | 5702 | while (ISALNUM (*input_line_pointer) |
252b5132 RH |
5703 | #ifdef REGISTER_PREFIX |
5704 | || *input_line_pointer == REGISTER_PREFIX | |
5705 | #endif | |
5706 | || *input_line_pointer == '/' | |
5707 | || *input_line_pointer == '-') | |
5708 | ++input_line_pointer; | |
5709 | c = *input_line_pointer; | |
5710 | *input_line_pointer = '\0'; | |
5711 | ||
5712 | if (m68k_ip_op (s, &rop) != 0) | |
5713 | { | |
5714 | if (rop.error == NULL) | |
5715 | as_bad (_("bad register list")); | |
5716 | else | |
5717 | as_bad (_("bad register list: %s"), rop.error); | |
5718 | *input_line_pointer = c; | |
5719 | ignore_rest_of_line (); | |
5720 | return; | |
5721 | } | |
5722 | ||
5723 | *input_line_pointer = c; | |
5724 | ||
5725 | if (rop.mode == REGLST) | |
5726 | mask = rop.mask; | |
5727 | else if (rop.mode == DREG) | |
5728 | mask = 1 << (rop.reg - DATA0); | |
5729 | else if (rop.mode == AREG) | |
5730 | mask = 1 << (rop.reg - ADDR0 + 8); | |
5731 | else if (rop.mode == FPREG) | |
5732 | mask = 1 << (rop.reg - FP0 + 16); | |
5733 | else if (rop.mode == CONTROL | |
5734 | && rop.reg == FPI) | |
5735 | mask = 1 << 24; | |
5736 | else if (rop.mode == CONTROL | |
5737 | && rop.reg == FPS) | |
5738 | mask = 1 << 25; | |
5739 | else if (rop.mode == CONTROL | |
5740 | && rop.reg == FPC) | |
5741 | mask = 1 << 26; | |
5742 | else | |
5743 | { | |
5744 | as_bad (_("bad register list")); | |
5745 | ignore_rest_of_line (); | |
5746 | return; | |
5747 | } | |
5748 | ||
5749 | S_SET_SEGMENT (line_label, reg_section); | |
5750 | S_SET_VALUE (line_label, ~mask); | |
49309057 | 5751 | symbol_set_frag (line_label, &zero_address_frag); |
252b5132 RH |
5752 | |
5753 | if (flag_mri) | |
5754 | mri_comment_end (stop, stopc); | |
5755 | ||
5756 | demand_empty_rest_of_line (); | |
5757 | } | |
5758 | ||
5759 | /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ | |
5760 | ||
5761 | struct save_opts | |
5762 | { | |
5763 | struct save_opts *next; | |
5764 | int abspcadd; | |
5765 | int symbols_case_sensitive; | |
5766 | int keep_locals; | |
5767 | int short_refs; | |
5768 | int architecture; | |
6b6e92f4 | 5769 | int chip; |
252b5132 RH |
5770 | int quick; |
5771 | int rel32; | |
5772 | int listing; | |
5773 | int no_warnings; | |
5774 | /* FIXME: We don't save OPT S. */ | |
5775 | }; | |
5776 | ||
5777 | /* This variable holds the stack of saved options. */ | |
5778 | ||
5779 | static struct save_opts *save_stack; | |
5780 | ||
5781 | /* The MRI SAVE pseudo-op. */ | |
5782 | ||
5783 | static void | |
31302357 | 5784 | s_save (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5785 | { |
5786 | struct save_opts *s; | |
5787 | ||
5788 | s = (struct save_opts *) xmalloc (sizeof (struct save_opts)); | |
5789 | s->abspcadd = m68k_abspcadd; | |
5790 | s->symbols_case_sensitive = symbols_case_sensitive; | |
5791 | s->keep_locals = flag_keep_locals; | |
5792 | s->short_refs = flag_short_refs; | |
5793 | s->architecture = current_architecture; | |
6b6e92f4 | 5794 | s->chip = current_chip; |
252b5132 RH |
5795 | s->quick = m68k_quick; |
5796 | s->rel32 = m68k_rel32; | |
5797 | s->listing = listing; | |
5798 | s->no_warnings = flag_no_warnings; | |
5799 | ||
5800 | s->next = save_stack; | |
5801 | save_stack = s; | |
5802 | ||
5803 | demand_empty_rest_of_line (); | |
5804 | } | |
5805 | ||
5806 | /* The MRI RESTORE pseudo-op. */ | |
5807 | ||
5808 | static void | |
31302357 | 5809 | s_restore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5810 | { |
5811 | struct save_opts *s; | |
5812 | ||
5813 | if (save_stack == NULL) | |
5814 | { | |
5815 | as_bad (_("restore without save")); | |
5816 | ignore_rest_of_line (); | |
5817 | return; | |
5818 | } | |
5819 | ||
5820 | s = save_stack; | |
5821 | save_stack = s->next; | |
5822 | ||
5823 | m68k_abspcadd = s->abspcadd; | |
5824 | symbols_case_sensitive = s->symbols_case_sensitive; | |
5825 | flag_keep_locals = s->keep_locals; | |
5826 | flag_short_refs = s->short_refs; | |
5827 | current_architecture = s->architecture; | |
6b6e92f4 | 5828 | current_chip = s->chip; |
252b5132 RH |
5829 | m68k_quick = s->quick; |
5830 | m68k_rel32 = s->rel32; | |
5831 | listing = s->listing; | |
5832 | flag_no_warnings = s->no_warnings; | |
5833 | ||
5834 | free (s); | |
5835 | ||
5836 | demand_empty_rest_of_line (); | |
5837 | } | |
5838 | ||
5839 | /* Types of MRI structured control directives. */ | |
5840 | ||
5841 | enum mri_control_type | |
5842 | { | |
5843 | mri_for, | |
5844 | mri_if, | |
5845 | mri_repeat, | |
5846 | mri_while | |
5847 | }; | |
5848 | ||
5849 | /* This structure is used to stack the MRI structured control | |
5850 | directives. */ | |
5851 | ||
5852 | struct mri_control_info | |
5853 | { | |
5854 | /* The directive within which this one is enclosed. */ | |
5855 | struct mri_control_info *outer; | |
5856 | ||
5857 | /* The type of directive. */ | |
5858 | enum mri_control_type type; | |
5859 | ||
5860 | /* Whether an ELSE has been in an IF. */ | |
5861 | int else_seen; | |
5862 | ||
5863 | /* The add or sub statement at the end of a FOR. */ | |
5864 | char *incr; | |
5865 | ||
5866 | /* The label of the top of a FOR or REPEAT loop. */ | |
5867 | char *top; | |
5868 | ||
5869 | /* The label to jump to for the next iteration, or the else | |
5870 | expression of a conditional. */ | |
5871 | char *next; | |
5872 | ||
5873 | /* The label to jump to to break out of the loop, or the label past | |
5874 | the end of a conditional. */ | |
5875 | char *bottom; | |
5876 | }; | |
5877 | ||
5878 | /* The stack of MRI structured control directives. */ | |
5879 | ||
5880 | static struct mri_control_info *mri_control_stack; | |
5881 | ||
5882 | /* The current MRI structured control directive index number, used to | |
5883 | generate label names. */ | |
5884 | ||
5885 | static int mri_control_index; | |
5886 | ||
252b5132 RH |
5887 | /* Assemble an instruction for an MRI structured control directive. */ |
5888 | ||
5889 | static void | |
31302357 | 5890 | mri_assemble (char *str) |
252b5132 RH |
5891 | { |
5892 | char *s; | |
5893 | ||
5894 | /* md_assemble expects the opcode to be in lower case. */ | |
5895 | for (s = str; *s != ' ' && *s != '\0'; s++) | |
3882b010 | 5896 | *s = TOLOWER (*s); |
252b5132 RH |
5897 | |
5898 | md_assemble (str); | |
5899 | } | |
5900 | ||
5901 | /* Generate a new MRI label structured control directive label name. */ | |
5902 | ||
5903 | static char * | |
31302357 | 5904 | mri_control_label (void) |
252b5132 RH |
5905 | { |
5906 | char *n; | |
5907 | ||
5908 | n = (char *) xmalloc (20); | |
5909 | sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); | |
5910 | ++mri_control_index; | |
5911 | return n; | |
5912 | } | |
5913 | ||
5914 | /* Create a new MRI structured control directive. */ | |
5915 | ||
5916 | static struct mri_control_info * | |
31302357 | 5917 | push_mri_control (enum mri_control_type type) |
252b5132 RH |
5918 | { |
5919 | struct mri_control_info *n; | |
5920 | ||
5921 | n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info)); | |
5922 | ||
5923 | n->type = type; | |
5924 | n->else_seen = 0; | |
5925 | if (type == mri_if || type == mri_while) | |
5926 | n->top = NULL; | |
5927 | else | |
5928 | n->top = mri_control_label (); | |
5929 | n->next = mri_control_label (); | |
5930 | n->bottom = mri_control_label (); | |
5931 | ||
5932 | n->outer = mri_control_stack; | |
5933 | mri_control_stack = n; | |
5934 | ||
5935 | return n; | |
5936 | } | |
5937 | ||
5938 | /* Pop off the stack of MRI structured control directives. */ | |
5939 | ||
5940 | static void | |
31302357 | 5941 | pop_mri_control (void) |
252b5132 RH |
5942 | { |
5943 | struct mri_control_info *n; | |
5944 | ||
5945 | n = mri_control_stack; | |
5946 | mri_control_stack = n->outer; | |
5947 | if (n->top != NULL) | |
5948 | free (n->top); | |
5949 | free (n->next); | |
5950 | free (n->bottom); | |
5951 | free (n); | |
5952 | } | |
5953 | ||
5954 | /* Recognize a condition code in an MRI structured control expression. */ | |
5955 | ||
5956 | static int | |
31302357 | 5957 | parse_mri_condition (int *pcc) |
252b5132 RH |
5958 | { |
5959 | char c1, c2; | |
5960 | ||
5961 | know (*input_line_pointer == '<'); | |
5962 | ||
5963 | ++input_line_pointer; | |
5964 | c1 = *input_line_pointer++; | |
5965 | c2 = *input_line_pointer++; | |
5966 | ||
5967 | if (*input_line_pointer != '>') | |
5968 | { | |
5969 | as_bad (_("syntax error in structured control directive")); | |
5970 | return 0; | |
5971 | } | |
5972 | ||
5973 | ++input_line_pointer; | |
5974 | SKIP_WHITESPACE (); | |
5975 | ||
3882b010 L |
5976 | c1 = TOLOWER (c1); |
5977 | c2 = TOLOWER (c2); | |
252b5132 RH |
5978 | |
5979 | *pcc = (c1 << 8) | c2; | |
5980 | ||
5981 | return 1; | |
5982 | } | |
5983 | ||
5984 | /* Parse a single operand in an MRI structured control expression. */ | |
5985 | ||
5986 | static int | |
31302357 AS |
5987 | parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, |
5988 | char **rightstart, char **rightstop) | |
252b5132 RH |
5989 | { |
5990 | char *s; | |
5991 | ||
5992 | SKIP_WHITESPACE (); | |
5993 | ||
5994 | *pcc = -1; | |
5995 | *leftstart = NULL; | |
5996 | *leftstop = NULL; | |
5997 | *rightstart = NULL; | |
5998 | *rightstop = NULL; | |
5999 | ||
6000 | if (*input_line_pointer == '<') | |
6001 | { | |
6002 | /* It's just a condition code. */ | |
6003 | return parse_mri_condition (pcc); | |
6004 | } | |
6005 | ||
6006 | /* Look ahead for the condition code. */ | |
6007 | for (s = input_line_pointer; *s != '\0'; ++s) | |
6008 | { | |
6009 | if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') | |
6010 | break; | |
6011 | } | |
6012 | if (*s == '\0') | |
6013 | { | |
6014 | as_bad (_("missing condition code in structured control directive")); | |
6015 | return 0; | |
6016 | } | |
6017 | ||
6018 | *leftstart = input_line_pointer; | |
6019 | *leftstop = s; | |
6020 | if (*leftstop > *leftstart | |
6021 | && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) | |
6022 | --*leftstop; | |
6023 | ||
6024 | input_line_pointer = s; | |
6025 | if (! parse_mri_condition (pcc)) | |
6026 | return 0; | |
6027 | ||
6028 | /* Look ahead for AND or OR or end of line. */ | |
6029 | for (s = input_line_pointer; *s != '\0'; ++s) | |
6030 | { | |
e1f44d10 NC |
6031 | /* We must make sure we don't misinterpret AND/OR at the end of labels! |
6032 | if d0 <eq> #FOOAND and d1 <ne> #BAROR then | |
6033 | ^^^ ^^ */ | |
8a104df9 KH |
6034 | if ((s == input_line_pointer |
6035 | || *(s-1) == ' ' | |
6036 | || *(s-1) == '\t') | |
6037 | && ((strncasecmp (s, "AND", 3) == 0 | |
6038 | && (s[3] == '.' || ! is_part_of_name (s[3]))) | |
6039 | || (strncasecmp (s, "OR", 2) == 0 | |
6040 | && (s[2] == '.' || ! is_part_of_name (s[2]))))) | |
6041 | break; | |
252b5132 RH |
6042 | } |
6043 | ||
6044 | *rightstart = input_line_pointer; | |
6045 | *rightstop = s; | |
6046 | if (*rightstop > *rightstart | |
6047 | && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) | |
6048 | --*rightstop; | |
6049 | ||
6050 | input_line_pointer = s; | |
6051 | ||
6052 | return 1; | |
6053 | } | |
6054 | ||
6055 | #define MCC(b1, b2) (((b1) << 8) | (b2)) | |
6056 | ||
6057 | /* Swap the sense of a condition. This changes the condition so that | |
6058 | it generates the same result when the operands are swapped. */ | |
6059 | ||
6060 | static int | |
31302357 | 6061 | swap_mri_condition (int cc) |
252b5132 RH |
6062 | { |
6063 | switch (cc) | |
6064 | { | |
6065 | case MCC ('h', 'i'): return MCC ('c', 's'); | |
6066 | case MCC ('l', 's'): return MCC ('c', 'c'); | |
36759679 | 6067 | /* <HS> is an alias for <CC>. */ |
e1f44d10 | 6068 | case MCC ('h', 's'): |
252b5132 | 6069 | case MCC ('c', 'c'): return MCC ('l', 's'); |
36759679 | 6070 | /* <LO> is an alias for <CS>. */ |
e1f44d10 | 6071 | case MCC ('l', 'o'): |
252b5132 RH |
6072 | case MCC ('c', 's'): return MCC ('h', 'i'); |
6073 | case MCC ('p', 'l'): return MCC ('m', 'i'); | |
6074 | case MCC ('m', 'i'): return MCC ('p', 'l'); | |
6075 | case MCC ('g', 'e'): return MCC ('l', 'e'); | |
6076 | case MCC ('l', 't'): return MCC ('g', 't'); | |
6077 | case MCC ('g', 't'): return MCC ('l', 't'); | |
6078 | case MCC ('l', 'e'): return MCC ('g', 'e'); | |
36759679 | 6079 | /* Issue a warning for conditions we can not swap. */ |
e1f44d10 NC |
6080 | case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here |
6081 | case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem | |
6082 | case MCC ('v', 'c'): | |
6083 | case MCC ('v', 's'): | |
6084 | default : | |
6085 | as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), | |
6086 | (char) (cc >> 8), (char) (cc)); | |
6087 | break; | |
252b5132 RH |
6088 | } |
6089 | return cc; | |
6090 | } | |
6091 | ||
6092 | /* Reverse the sense of a condition. */ | |
6093 | ||
6094 | static int | |
31302357 | 6095 | reverse_mri_condition (int cc) |
252b5132 RH |
6096 | { |
6097 | switch (cc) | |
6098 | { | |
6099 | case MCC ('h', 'i'): return MCC ('l', 's'); | |
6100 | case MCC ('l', 's'): return MCC ('h', 'i'); | |
e1f44d10 NC |
6101 | /* <HS> is an alias for <CC> */ |
6102 | case MCC ('h', 's'): return MCC ('l', 'o'); | |
252b5132 | 6103 | case MCC ('c', 'c'): return MCC ('c', 's'); |
e1f44d10 NC |
6104 | /* <LO> is an alias for <CS> */ |
6105 | case MCC ('l', 'o'): return MCC ('h', 's'); | |
252b5132 RH |
6106 | case MCC ('c', 's'): return MCC ('c', 'c'); |
6107 | case MCC ('n', 'e'): return MCC ('e', 'q'); | |
6108 | case MCC ('e', 'q'): return MCC ('n', 'e'); | |
6109 | case MCC ('v', 'c'): return MCC ('v', 's'); | |
6110 | case MCC ('v', 's'): return MCC ('v', 'c'); | |
6111 | case MCC ('p', 'l'): return MCC ('m', 'i'); | |
6112 | case MCC ('m', 'i'): return MCC ('p', 'l'); | |
6113 | case MCC ('g', 'e'): return MCC ('l', 't'); | |
6114 | case MCC ('l', 't'): return MCC ('g', 'e'); | |
6115 | case MCC ('g', 't'): return MCC ('l', 'e'); | |
6116 | case MCC ('l', 'e'): return MCC ('g', 't'); | |
6117 | } | |
6118 | return cc; | |
6119 | } | |
6120 | ||
6121 | /* Build an MRI structured control expression. This generates test | |
6122 | and branch instructions. It goes to TRUELAB if the condition is | |
6123 | true, and to FALSELAB if the condition is false. Exactly one of | |
6124 | TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL | |
6125 | is the size qualifier for the expression. EXTENT is the size to | |
6126 | use for the branch. */ | |
6127 | ||
6128 | static void | |
31302357 AS |
6129 | build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, |
6130 | char *rightstart, char *rightstop, | |
6131 | const char *truelab, const char *falselab, | |
6132 | int extent) | |
252b5132 RH |
6133 | { |
6134 | char *buf; | |
6135 | char *s; | |
6136 | ||
6137 | if (leftstart != NULL) | |
6138 | { | |
6139 | struct m68k_op leftop, rightop; | |
6140 | char c; | |
6141 | ||
6142 | /* Swap the compare operands, if necessary, to produce a legal | |
6143 | m68k compare instruction. Comparing a register operand with | |
6144 | a non-register operand requires the register to be on the | |
6145 | right (cmp, cmpa). Comparing an immediate value with | |
6146 | anything requires the immediate value to be on the left | |
6147 | (cmpi). */ | |
6148 | ||
6149 | c = *leftstop; | |
6150 | *leftstop = '\0'; | |
6151 | (void) m68k_ip_op (leftstart, &leftop); | |
6152 | *leftstop = c; | |
6153 | ||
6154 | c = *rightstop; | |
6155 | *rightstop = '\0'; | |
6156 | (void) m68k_ip_op (rightstart, &rightop); | |
6157 | *rightstop = c; | |
6158 | ||
6159 | if (rightop.mode == IMMED | |
6160 | || ((leftop.mode == DREG || leftop.mode == AREG) | |
6161 | && (rightop.mode != DREG && rightop.mode != AREG))) | |
6162 | { | |
6163 | char *temp; | |
6164 | ||
31302357 AS |
6165 | /* Correct conditional handling: |
6166 | if #1 <lt> d0 then ;means if (1 < d0) | |
6167 | ... | |
6168 | endi | |
e1f44d10 | 6169 | |
31302357 | 6170 | should assemble to: |
e1f44d10 | 6171 | |
31302357 AS |
6172 | cmp #1,d0 if we do *not* swap the operands |
6173 | bgt true we need the swapped condition! | |
6174 | ble false | |
6175 | true: | |
6176 | ... | |
6177 | false: | |
6178 | */ | |
252b5132 RH |
6179 | temp = leftstart; |
6180 | leftstart = rightstart; | |
6181 | rightstart = temp; | |
6182 | temp = leftstop; | |
6183 | leftstop = rightstop; | |
6184 | rightstop = temp; | |
8a104df9 KH |
6185 | } |
6186 | else | |
6187 | { | |
e1f44d10 | 6188 | cc = swap_mri_condition (cc); |
252b5132 RH |
6189 | } |
6190 | } | |
6191 | ||
6192 | if (truelab == NULL) | |
6193 | { | |
6194 | cc = reverse_mri_condition (cc); | |
6195 | truelab = falselab; | |
6196 | } | |
92774660 | 6197 | |
252b5132 RH |
6198 | if (leftstart != NULL) |
6199 | { | |
6200 | buf = (char *) xmalloc (20 | |
6201 | + (leftstop - leftstart) | |
6202 | + (rightstop - rightstart)); | |
6203 | s = buf; | |
6204 | *s++ = 'c'; | |
6205 | *s++ = 'm'; | |
6206 | *s++ = 'p'; | |
6207 | if (qual != '\0') | |
3882b010 | 6208 | *s++ = TOLOWER (qual); |
252b5132 RH |
6209 | *s++ = ' '; |
6210 | memcpy (s, leftstart, leftstop - leftstart); | |
6211 | s += leftstop - leftstart; | |
6212 | *s++ = ','; | |
6213 | memcpy (s, rightstart, rightstop - rightstart); | |
6214 | s += rightstop - rightstart; | |
6215 | *s = '\0'; | |
6216 | mri_assemble (buf); | |
6217 | free (buf); | |
6218 | } | |
92774660 | 6219 | |
252b5132 RH |
6220 | buf = (char *) xmalloc (20 + strlen (truelab)); |
6221 | s = buf; | |
6222 | *s++ = 'b'; | |
6223 | *s++ = cc >> 8; | |
6224 | *s++ = cc & 0xff; | |
6225 | if (extent != '\0') | |
3882b010 | 6226 | *s++ = TOLOWER (extent); |
252b5132 RH |
6227 | *s++ = ' '; |
6228 | strcpy (s, truelab); | |
6229 | mri_assemble (buf); | |
6230 | free (buf); | |
6231 | } | |
6232 | ||
6233 | /* Parse an MRI structured control expression. This generates test | |
6234 | and branch instructions. STOP is where the expression ends. It | |
6235 | goes to TRUELAB if the condition is true, and to FALSELAB if the | |
6236 | condition is false. Exactly one of TRUELAB and FALSELAB will be | |
6237 | NULL, meaning to fall through. QUAL is the size qualifier for the | |
6238 | expression. EXTENT is the size to use for the branch. */ | |
6239 | ||
6240 | static void | |
31302357 AS |
6241 | parse_mri_control_expression (char *stop, int qual, const char *truelab, |
6242 | const char *falselab, int extent) | |
252b5132 RH |
6243 | { |
6244 | int c; | |
6245 | int cc; | |
6246 | char *leftstart; | |
6247 | char *leftstop; | |
6248 | char *rightstart; | |
6249 | char *rightstop; | |
6250 | ||
6251 | c = *stop; | |
6252 | *stop = '\0'; | |
6253 | ||
6254 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6255 | &rightstart, &rightstop)) | |
6256 | { | |
6257 | *stop = c; | |
6258 | return; | |
6259 | } | |
6260 | ||
6261 | if (strncasecmp (input_line_pointer, "AND", 3) == 0) | |
6262 | { | |
6263 | const char *flab; | |
6264 | ||
6265 | if (falselab != NULL) | |
6266 | flab = falselab; | |
6267 | else | |
6268 | flab = mri_control_label (); | |
6269 | ||
6270 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6271 | rightstop, (const char *) NULL, flab, extent); | |
6272 | ||
6273 | input_line_pointer += 3; | |
6274 | if (*input_line_pointer != '.' | |
6275 | || input_line_pointer[1] == '\0') | |
6276 | qual = '\0'; | |
6277 | else | |
6278 | { | |
6279 | qual = input_line_pointer[1]; | |
6280 | input_line_pointer += 2; | |
6281 | } | |
6282 | ||
6283 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6284 | &rightstart, &rightstop)) | |
6285 | { | |
6286 | *stop = c; | |
6287 | return; | |
6288 | } | |
6289 | ||
6290 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6291 | rightstop, truelab, falselab, extent); | |
6292 | ||
6293 | if (falselab == NULL) | |
6294 | colon (flab); | |
6295 | } | |
6296 | else if (strncasecmp (input_line_pointer, "OR", 2) == 0) | |
6297 | { | |
6298 | const char *tlab; | |
6299 | ||
6300 | if (truelab != NULL) | |
6301 | tlab = truelab; | |
6302 | else | |
6303 | tlab = mri_control_label (); | |
6304 | ||
6305 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6306 | rightstop, tlab, (const char *) NULL, extent); | |
6307 | ||
6308 | input_line_pointer += 2; | |
6309 | if (*input_line_pointer != '.' | |
6310 | || input_line_pointer[1] == '\0') | |
6311 | qual = '\0'; | |
6312 | else | |
6313 | { | |
6314 | qual = input_line_pointer[1]; | |
6315 | input_line_pointer += 2; | |
6316 | } | |
6317 | ||
6318 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6319 | &rightstart, &rightstop)) | |
6320 | { | |
6321 | *stop = c; | |
6322 | return; | |
6323 | } | |
6324 | ||
6325 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6326 | rightstop, truelab, falselab, extent); | |
6327 | ||
6328 | if (truelab == NULL) | |
6329 | colon (tlab); | |
6330 | } | |
6331 | else | |
6332 | { | |
6333 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6334 | rightstop, truelab, falselab, extent); | |
6335 | } | |
6336 | ||
6337 | *stop = c; | |
6338 | if (input_line_pointer != stop) | |
6339 | as_bad (_("syntax error in structured control directive")); | |
6340 | } | |
6341 | ||
6342 | /* Handle the MRI IF pseudo-op. This may be a structured control | |
6343 | directive, or it may be a regular assembler conditional, depending | |
6344 | on its operands. */ | |
6345 | ||
6346 | static void | |
31302357 | 6347 | s_mri_if (int qual) |
252b5132 RH |
6348 | { |
6349 | char *s; | |
6350 | int c; | |
6351 | struct mri_control_info *n; | |
6352 | ||
6353 | /* A structured control directive must end with THEN with an | |
6354 | optional qualifier. */ | |
6355 | s = input_line_pointer; | |
e1f44d10 NC |
6356 | /* We only accept '*' as introduction of comments if preceded by white space |
6357 | or at first column of a line (I think this can't actually happen here?) | |
6358 | This is important when assembling: | |
6359 | if d0 <ne> 12(a0,d0*2) then | |
36759679 | 6360 | if d0 <ne> #CONST*20 then. */ |
31302357 AS |
6361 | while (! (is_end_of_line[(unsigned char) *s] |
6362 | || (flag_mri | |
6363 | && *s == '*' | |
6364 | && (s == input_line_pointer | |
6365 | || *(s-1) == ' ' | |
6366 | || *(s-1) == '\t')))) | |
252b5132 RH |
6367 | ++s; |
6368 | --s; | |
6369 | while (s > input_line_pointer && (*s == ' ' || *s == '\t')) | |
6370 | --s; | |
6371 | ||
6372 | if (s - input_line_pointer > 1 | |
6373 | && s[-1] == '.') | |
6374 | s -= 2; | |
6375 | ||
6376 | if (s - input_line_pointer < 3 | |
6377 | || strncasecmp (s - 3, "THEN", 4) != 0) | |
6378 | { | |
6379 | if (qual != '\0') | |
6380 | { | |
6381 | as_bad (_("missing then")); | |
6382 | ignore_rest_of_line (); | |
6383 | return; | |
6384 | } | |
6385 | ||
6386 | /* It's a conditional. */ | |
6387 | s_if (O_ne); | |
6388 | return; | |
6389 | } | |
6390 | ||
6391 | /* Since this might be a conditional if, this pseudo-op will be | |
6392 | called even if we are supported to be ignoring input. Double | |
6393 | check now. Clobber *input_line_pointer so that ignore_input | |
6394 | thinks that this is not a special pseudo-op. */ | |
6395 | c = *input_line_pointer; | |
6396 | *input_line_pointer = 0; | |
6397 | if (ignore_input ()) | |
6398 | { | |
6399 | *input_line_pointer = c; | |
6400 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6401 | ++input_line_pointer; | |
6402 | demand_empty_rest_of_line (); | |
6403 | return; | |
6404 | } | |
6405 | *input_line_pointer = c; | |
6406 | ||
6407 | n = push_mri_control (mri_if); | |
6408 | ||
6409 | parse_mri_control_expression (s - 3, qual, (const char *) NULL, | |
6410 | n->next, s[1] == '.' ? s[2] : '\0'); | |
6411 | ||
6412 | if (s[1] == '.') | |
6413 | input_line_pointer = s + 3; | |
6414 | else | |
6415 | input_line_pointer = s + 1; | |
6416 | ||
6417 | if (flag_mri) | |
6418 | { | |
6419 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6420 | ++input_line_pointer; | |
6421 | } | |
6422 | ||
6423 | demand_empty_rest_of_line (); | |
6424 | } | |
6425 | ||
6426 | /* Handle the MRI else pseudo-op. If we are currently doing an MRI | |
6427 | structured IF, associate the ELSE with the IF. Otherwise, assume | |
6428 | it is a conditional else. */ | |
6429 | ||
6430 | static void | |
31302357 | 6431 | s_mri_else (int qual) |
252b5132 RH |
6432 | { |
6433 | int c; | |
6434 | char *buf; | |
6435 | char q[2]; | |
6436 | ||
6437 | if (qual == '\0' | |
6438 | && (mri_control_stack == NULL | |
6439 | || mri_control_stack->type != mri_if | |
6440 | || mri_control_stack->else_seen)) | |
6441 | { | |
6442 | s_else (0); | |
6443 | return; | |
6444 | } | |
6445 | ||
6446 | c = *input_line_pointer; | |
6447 | *input_line_pointer = 0; | |
6448 | if (ignore_input ()) | |
6449 | { | |
6450 | *input_line_pointer = c; | |
6451 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6452 | ++input_line_pointer; | |
6453 | demand_empty_rest_of_line (); | |
6454 | return; | |
6455 | } | |
6456 | *input_line_pointer = c; | |
6457 | ||
6458 | if (mri_control_stack == NULL | |
6459 | || mri_control_stack->type != mri_if | |
6460 | || mri_control_stack->else_seen) | |
6461 | { | |
6462 | as_bad (_("else without matching if")); | |
6463 | ignore_rest_of_line (); | |
6464 | return; | |
6465 | } | |
6466 | ||
6467 | mri_control_stack->else_seen = 1; | |
6468 | ||
6469 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom)); | |
3882b010 | 6470 | q[0] = TOLOWER (qual); |
252b5132 RH |
6471 | q[1] = '\0'; |
6472 | sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); | |
6473 | mri_assemble (buf); | |
6474 | free (buf); | |
6475 | ||
6476 | colon (mri_control_stack->next); | |
6477 | ||
6478 | if (flag_mri) | |
6479 | { | |
6480 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6481 | ++input_line_pointer; | |
6482 | } | |
6483 | ||
6484 | demand_empty_rest_of_line (); | |
6485 | } | |
6486 | ||
6487 | /* Handle the MRI ENDI pseudo-op. */ | |
6488 | ||
6489 | static void | |
31302357 | 6490 | s_mri_endi (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6491 | { |
6492 | if (mri_control_stack == NULL | |
6493 | || mri_control_stack->type != mri_if) | |
6494 | { | |
6495 | as_bad (_("endi without matching if")); | |
6496 | ignore_rest_of_line (); | |
6497 | return; | |
6498 | } | |
6499 | ||
6500 | /* ignore_input will not return true for ENDI, so we don't need to | |
6501 | worry about checking it again here. */ | |
6502 | ||
6503 | if (! mri_control_stack->else_seen) | |
6504 | colon (mri_control_stack->next); | |
6505 | colon (mri_control_stack->bottom); | |
6506 | ||
6507 | pop_mri_control (); | |
6508 | ||
6509 | if (flag_mri) | |
6510 | { | |
6511 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6512 | ++input_line_pointer; | |
6513 | } | |
6514 | ||
6515 | demand_empty_rest_of_line (); | |
6516 | } | |
6517 | ||
6518 | /* Handle the MRI BREAK pseudo-op. */ | |
6519 | ||
6520 | static void | |
31302357 | 6521 | s_mri_break (int extent) |
252b5132 RH |
6522 | { |
6523 | struct mri_control_info *n; | |
6524 | char *buf; | |
6525 | char ex[2]; | |
6526 | ||
6527 | n = mri_control_stack; | |
6528 | while (n != NULL | |
6529 | && n->type != mri_for | |
6530 | && n->type != mri_repeat | |
6531 | && n->type != mri_while) | |
6532 | n = n->outer; | |
6533 | if (n == NULL) | |
6534 | { | |
6535 | as_bad (_("break outside of structured loop")); | |
6536 | ignore_rest_of_line (); | |
6537 | return; | |
6538 | } | |
6539 | ||
6540 | buf = (char *) xmalloc (20 + strlen (n->bottom)); | |
3882b010 | 6541 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6542 | ex[1] = '\0'; |
6543 | sprintf (buf, "bra%s %s", ex, n->bottom); | |
6544 | mri_assemble (buf); | |
6545 | free (buf); | |
6546 | ||
6547 | if (flag_mri) | |
6548 | { | |
6549 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6550 | ++input_line_pointer; | |
6551 | } | |
6552 | ||
6553 | demand_empty_rest_of_line (); | |
6554 | } | |
6555 | ||
6556 | /* Handle the MRI NEXT pseudo-op. */ | |
6557 | ||
6558 | static void | |
31302357 | 6559 | s_mri_next (int extent) |
252b5132 RH |
6560 | { |
6561 | struct mri_control_info *n; | |
6562 | char *buf; | |
6563 | char ex[2]; | |
6564 | ||
6565 | n = mri_control_stack; | |
6566 | while (n != NULL | |
6567 | && n->type != mri_for | |
6568 | && n->type != mri_repeat | |
6569 | && n->type != mri_while) | |
6570 | n = n->outer; | |
6571 | if (n == NULL) | |
6572 | { | |
6573 | as_bad (_("next outside of structured loop")); | |
6574 | ignore_rest_of_line (); | |
6575 | return; | |
6576 | } | |
6577 | ||
6578 | buf = (char *) xmalloc (20 + strlen (n->next)); | |
3882b010 | 6579 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6580 | ex[1] = '\0'; |
6581 | sprintf (buf, "bra%s %s", ex, n->next); | |
6582 | mri_assemble (buf); | |
6583 | free (buf); | |
6584 | ||
6585 | if (flag_mri) | |
6586 | { | |
6587 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6588 | ++input_line_pointer; | |
6589 | } | |
6590 | ||
6591 | demand_empty_rest_of_line (); | |
6592 | } | |
6593 | ||
6594 | /* Handle the MRI FOR pseudo-op. */ | |
6595 | ||
6596 | static void | |
31302357 | 6597 | s_mri_for (int qual) |
252b5132 RH |
6598 | { |
6599 | const char *varstart, *varstop; | |
6600 | const char *initstart, *initstop; | |
6601 | const char *endstart, *endstop; | |
6602 | const char *bystart, *bystop; | |
6603 | int up; | |
6604 | int by; | |
6605 | int extent; | |
6606 | struct mri_control_info *n; | |
6607 | char *buf; | |
6608 | char *s; | |
6609 | char ex[2]; | |
6610 | ||
6611 | /* The syntax is | |
6612 | FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e | |
6613 | */ | |
6614 | ||
6615 | SKIP_WHITESPACE (); | |
6616 | varstart = input_line_pointer; | |
6617 | ||
6618 | /* Look for the '='. */ | |
6619 | while (! is_end_of_line[(unsigned char) *input_line_pointer] | |
6620 | && *input_line_pointer != '=') | |
6621 | ++input_line_pointer; | |
6622 | if (*input_line_pointer != '=') | |
6623 | { | |
6624 | as_bad (_("missing =")); | |
6625 | ignore_rest_of_line (); | |
6626 | return; | |
6627 | } | |
6628 | ||
6629 | varstop = input_line_pointer; | |
6630 | if (varstop > varstart | |
6631 | && (varstop[-1] == ' ' || varstop[-1] == '\t')) | |
6632 | --varstop; | |
6633 | ||
6634 | ++input_line_pointer; | |
6635 | ||
6636 | initstart = input_line_pointer; | |
6637 | ||
6638 | /* Look for TO or DOWNTO. */ | |
6639 | up = 1; | |
6640 | initstop = NULL; | |
6641 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6642 | { | |
6643 | if (strncasecmp (input_line_pointer, "TO", 2) == 0 | |
6644 | && ! is_part_of_name (input_line_pointer[2])) | |
6645 | { | |
6646 | initstop = input_line_pointer; | |
6647 | input_line_pointer += 2; | |
6648 | break; | |
6649 | } | |
6650 | if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 | |
6651 | && ! is_part_of_name (input_line_pointer[6])) | |
6652 | { | |
6653 | initstop = input_line_pointer; | |
6654 | up = 0; | |
6655 | input_line_pointer += 6; | |
6656 | break; | |
6657 | } | |
6658 | ++input_line_pointer; | |
6659 | } | |
6660 | if (initstop == NULL) | |
6661 | { | |
6662 | as_bad (_("missing to or downto")); | |
6663 | ignore_rest_of_line (); | |
6664 | return; | |
6665 | } | |
6666 | if (initstop > initstart | |
6667 | && (initstop[-1] == ' ' || initstop[-1] == '\t')) | |
6668 | --initstop; | |
6669 | ||
6670 | SKIP_WHITESPACE (); | |
6671 | endstart = input_line_pointer; | |
6672 | ||
6673 | /* Look for BY or DO. */ | |
6674 | by = 0; | |
6675 | endstop = NULL; | |
6676 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6677 | { | |
6678 | if (strncasecmp (input_line_pointer, "BY", 2) == 0 | |
6679 | && ! is_part_of_name (input_line_pointer[2])) | |
6680 | { | |
6681 | endstop = input_line_pointer; | |
6682 | by = 1; | |
6683 | input_line_pointer += 2; | |
6684 | break; | |
6685 | } | |
6686 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 | |
6687 | && (input_line_pointer[2] == '.' | |
6688 | || ! is_part_of_name (input_line_pointer[2]))) | |
6689 | { | |
6690 | endstop = input_line_pointer; | |
6691 | input_line_pointer += 2; | |
6692 | break; | |
6693 | } | |
6694 | ++input_line_pointer; | |
6695 | } | |
6696 | if (endstop == NULL) | |
6697 | { | |
6698 | as_bad (_("missing do")); | |
6699 | ignore_rest_of_line (); | |
6700 | return; | |
6701 | } | |
6702 | if (endstop > endstart | |
6703 | && (endstop[-1] == ' ' || endstop[-1] == '\t')) | |
6704 | --endstop; | |
6705 | ||
6706 | if (! by) | |
6707 | { | |
6708 | bystart = "#1"; | |
6709 | bystop = bystart + 2; | |
6710 | } | |
6711 | else | |
6712 | { | |
6713 | SKIP_WHITESPACE (); | |
6714 | bystart = input_line_pointer; | |
6715 | ||
6716 | /* Look for DO. */ | |
6717 | bystop = NULL; | |
6718 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6719 | { | |
6720 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 | |
6721 | && (input_line_pointer[2] == '.' | |
6722 | || ! is_part_of_name (input_line_pointer[2]))) | |
6723 | { | |
6724 | bystop = input_line_pointer; | |
6725 | input_line_pointer += 2; | |
6726 | break; | |
6727 | } | |
6728 | ++input_line_pointer; | |
6729 | } | |
6730 | if (bystop == NULL) | |
6731 | { | |
6732 | as_bad (_("missing do")); | |
6733 | ignore_rest_of_line (); | |
6734 | return; | |
6735 | } | |
6736 | if (bystop > bystart | |
6737 | && (bystop[-1] == ' ' || bystop[-1] == '\t')) | |
6738 | --bystop; | |
6739 | } | |
6740 | ||
6741 | if (*input_line_pointer != '.') | |
6742 | extent = '\0'; | |
6743 | else | |
6744 | { | |
6745 | extent = input_line_pointer[1]; | |
6746 | input_line_pointer += 2; | |
6747 | } | |
6748 | ||
6749 | /* We have fully parsed the FOR operands. Now build the loop. */ | |
252b5132 RH |
6750 | n = push_mri_control (mri_for); |
6751 | ||
6752 | buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); | |
6753 | ||
36759679 | 6754 | /* Move init,var. */ |
252b5132 RH |
6755 | s = buf; |
6756 | *s++ = 'm'; | |
6757 | *s++ = 'o'; | |
6758 | *s++ = 'v'; | |
6759 | *s++ = 'e'; | |
6760 | if (qual != '\0') | |
3882b010 | 6761 | *s++ = TOLOWER (qual); |
252b5132 RH |
6762 | *s++ = ' '; |
6763 | memcpy (s, initstart, initstop - initstart); | |
6764 | s += initstop - initstart; | |
6765 | *s++ = ','; | |
6766 | memcpy (s, varstart, varstop - varstart); | |
6767 | s += varstop - varstart; | |
6768 | *s = '\0'; | |
6769 | mri_assemble (buf); | |
6770 | ||
6771 | colon (n->top); | |
6772 | ||
36759679 | 6773 | /* cmp end,var. */ |
252b5132 RH |
6774 | s = buf; |
6775 | *s++ = 'c'; | |
6776 | *s++ = 'm'; | |
6777 | *s++ = 'p'; | |
6778 | if (qual != '\0') | |
3882b010 | 6779 | *s++ = TOLOWER (qual); |
252b5132 RH |
6780 | *s++ = ' '; |
6781 | memcpy (s, endstart, endstop - endstart); | |
6782 | s += endstop - endstart; | |
6783 | *s++ = ','; | |
6784 | memcpy (s, varstart, varstop - varstart); | |
6785 | s += varstop - varstart; | |
6786 | *s = '\0'; | |
6787 | mri_assemble (buf); | |
6788 | ||
36759679 | 6789 | /* bcc bottom. */ |
3882b010 | 6790 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6791 | ex[1] = '\0'; |
6792 | if (up) | |
6793 | sprintf (buf, "blt%s %s", ex, n->bottom); | |
6794 | else | |
6795 | sprintf (buf, "bgt%s %s", ex, n->bottom); | |
6796 | mri_assemble (buf); | |
6797 | ||
6798 | /* Put together the add or sub instruction used by ENDF. */ | |
6799 | s = buf; | |
6800 | if (up) | |
6801 | strcpy (s, "add"); | |
6802 | else | |
6803 | strcpy (s, "sub"); | |
6804 | s += 3; | |
6805 | if (qual != '\0') | |
3882b010 | 6806 | *s++ = TOLOWER (qual); |
252b5132 RH |
6807 | *s++ = ' '; |
6808 | memcpy (s, bystart, bystop - bystart); | |
6809 | s += bystop - bystart; | |
6810 | *s++ = ','; | |
6811 | memcpy (s, varstart, varstop - varstart); | |
6812 | s += varstop - varstart; | |
6813 | *s = '\0'; | |
6814 | n->incr = buf; | |
6815 | ||
6816 | if (flag_mri) | |
6817 | { | |
6818 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6819 | ++input_line_pointer; | |
6820 | } | |
6821 | ||
6822 | demand_empty_rest_of_line (); | |
6823 | } | |
6824 | ||
6825 | /* Handle the MRI ENDF pseudo-op. */ | |
6826 | ||
6827 | static void | |
31302357 | 6828 | s_mri_endf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6829 | { |
6830 | if (mri_control_stack == NULL | |
6831 | || mri_control_stack->type != mri_for) | |
6832 | { | |
6833 | as_bad (_("endf without for")); | |
6834 | ignore_rest_of_line (); | |
6835 | return; | |
6836 | } | |
6837 | ||
6838 | colon (mri_control_stack->next); | |
6839 | ||
6840 | mri_assemble (mri_control_stack->incr); | |
6841 | ||
6842 | sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); | |
6843 | mri_assemble (mri_control_stack->incr); | |
6844 | ||
6845 | free (mri_control_stack->incr); | |
6846 | ||
6847 | colon (mri_control_stack->bottom); | |
6848 | ||
6849 | pop_mri_control (); | |
6850 | ||
6851 | if (flag_mri) | |
6852 | { | |
6853 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6854 | ++input_line_pointer; | |
6855 | } | |
6856 | ||
6857 | demand_empty_rest_of_line (); | |
6858 | } | |
6859 | ||
6860 | /* Handle the MRI REPEAT pseudo-op. */ | |
6861 | ||
6862 | static void | |
31302357 | 6863 | s_mri_repeat (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6864 | { |
6865 | struct mri_control_info *n; | |
6866 | ||
6867 | n = push_mri_control (mri_repeat); | |
6868 | colon (n->top); | |
6869 | if (flag_mri) | |
6870 | { | |
6871 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6872 | ++input_line_pointer; | |
6873 | } | |
6874 | demand_empty_rest_of_line (); | |
6875 | } | |
6876 | ||
6877 | /* Handle the MRI UNTIL pseudo-op. */ | |
6878 | ||
6879 | static void | |
31302357 | 6880 | s_mri_until (int qual) |
252b5132 RH |
6881 | { |
6882 | char *s; | |
6883 | ||
6884 | if (mri_control_stack == NULL | |
6885 | || mri_control_stack->type != mri_repeat) | |
6886 | { | |
6887 | as_bad (_("until without repeat")); | |
6888 | ignore_rest_of_line (); | |
6889 | return; | |
6890 | } | |
6891 | ||
6892 | colon (mri_control_stack->next); | |
6893 | ||
6894 | for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) | |
6895 | ; | |
6896 | ||
6897 | parse_mri_control_expression (s, qual, (const char *) NULL, | |
6898 | mri_control_stack->top, '\0'); | |
6899 | ||
6900 | colon (mri_control_stack->bottom); | |
6901 | ||
6902 | input_line_pointer = s; | |
6903 | ||
6904 | pop_mri_control (); | |
6905 | ||
6906 | if (flag_mri) | |
6907 | { | |
6908 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6909 | ++input_line_pointer; | |
6910 | } | |
6911 | ||
6912 | demand_empty_rest_of_line (); | |
6913 | } | |
6914 | ||
6915 | /* Handle the MRI WHILE pseudo-op. */ | |
6916 | ||
6917 | static void | |
31302357 | 6918 | s_mri_while (int qual) |
252b5132 RH |
6919 | { |
6920 | char *s; | |
6921 | ||
6922 | struct mri_control_info *n; | |
6923 | ||
6924 | s = input_line_pointer; | |
e1f44d10 NC |
6925 | /* We only accept '*' as introduction of comments if preceded by white space |
6926 | or at first column of a line (I think this can't actually happen here?) | |
6927 | This is important when assembling: | |
6928 | while d0 <ne> 12(a0,d0*2) do | |
36759679 | 6929 | while d0 <ne> #CONST*20 do. */ |
8a104df9 KH |
6930 | while (! (is_end_of_line[(unsigned char) *s] |
6931 | || (flag_mri | |
6932 | && *s == '*' | |
6933 | && (s == input_line_pointer | |
6934 | || *(s-1) == ' ' | |
6935 | || *(s-1) == '\t')))) | |
252b5132 RH |
6936 | s++; |
6937 | --s; | |
6938 | while (*s == ' ' || *s == '\t') | |
6939 | --s; | |
6940 | if (s - input_line_pointer > 1 | |
6941 | && s[-1] == '.') | |
6942 | s -= 2; | |
6943 | if (s - input_line_pointer < 2 | |
6944 | || strncasecmp (s - 1, "DO", 2) != 0) | |
6945 | { | |
6946 | as_bad (_("missing do")); | |
6947 | ignore_rest_of_line (); | |
6948 | return; | |
6949 | } | |
6950 | ||
6951 | n = push_mri_control (mri_while); | |
6952 | ||
6953 | colon (n->next); | |
6954 | ||
6955 | parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, | |
6956 | s[1] == '.' ? s[2] : '\0'); | |
6957 | ||
6958 | input_line_pointer = s + 1; | |
6959 | if (*input_line_pointer == '.') | |
6960 | input_line_pointer += 2; | |
6961 | ||
6962 | if (flag_mri) | |
6963 | { | |
6964 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6965 | ++input_line_pointer; | |
6966 | } | |
6967 | ||
6968 | demand_empty_rest_of_line (); | |
6969 | } | |
6970 | ||
6971 | /* Handle the MRI ENDW pseudo-op. */ | |
6972 | ||
6973 | static void | |
31302357 | 6974 | s_mri_endw (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6975 | { |
6976 | char *buf; | |
6977 | ||
6978 | if (mri_control_stack == NULL | |
6979 | || mri_control_stack->type != mri_while) | |
6980 | { | |
6981 | as_bad (_("endw without while")); | |
6982 | ignore_rest_of_line (); | |
6983 | return; | |
6984 | } | |
6985 | ||
6986 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->next)); | |
6987 | sprintf (buf, "bra %s", mri_control_stack->next); | |
6988 | mri_assemble (buf); | |
6989 | free (buf); | |
6990 | ||
6991 | colon (mri_control_stack->bottom); | |
6992 | ||
6993 | pop_mri_control (); | |
6994 | ||
6995 | if (flag_mri) | |
6996 | { | |
6997 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6998 | ++input_line_pointer; | |
6999 | } | |
7000 | ||
7001 | demand_empty_rest_of_line (); | |
7002 | } | |
7003 | \f | |
31302357 AS |
7004 | /* md_parse_option |
7005 | Invocation line includes a switch not recognized by the base assembler. | |
7006 | See if it's a processor-specific option. These are: | |
7007 | ||
7008 | -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040 | |
7009 | -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851 | |
7010 | Select the architecture. Instructions or features not | |
7011 | supported by the selected architecture cause fatal | |
7012 | errors. More than one may be specified. The default is | |
7013 | -m68020 -m68851 -m68881. Note that -m68008 is a synonym | |
7014 | for -m68000, and -m68882 is a synonym for -m68881. | |
7015 | -[A]m[c]no-68851, -[A]m[c]no-68881 | |
7016 | Don't accept 688?1 instructions. (The "c" is kind of silly, | |
7017 | so don't use or document it, but that's the way the parsing | |
7018 | works). | |
7019 | ||
7020 | -pic Indicates PIC. | |
7021 | -k Indicates PIC. (Sun 3 only.) | |
7022 | --pcrel | |
7023 | Never turn PC-relative branches into absolute jumps. | |
7024 | --bitwise-or | |
7025 | Permit `|' to be used in expressions. */ | |
252b5132 RH |
7026 | |
7027 | #ifdef OBJ_ELF | |
5a38dc70 | 7028 | const char *md_shortopts = "lSA:m:kQ:V"; |
252b5132 | 7029 | #else |
5a38dc70 | 7030 | const char *md_shortopts = "lSA:m:k"; |
252b5132 RH |
7031 | #endif |
7032 | ||
7033 | struct option md_longopts[] = { | |
7034 | #define OPTION_PIC (OPTION_MD_BASE) | |
7035 | {"pic", no_argument, NULL, OPTION_PIC}, | |
7036 | #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) | |
7037 | {"register-prefix-optional", no_argument, NULL, | |
7038 | OPTION_REGISTER_PREFIX_OPTIONAL}, | |
7039 | #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) | |
7040 | {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, | |
7041 | #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) | |
7042 | {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, | |
7043 | #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) | |
7044 | {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, | |
7045 | #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) | |
7046 | {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, | |
7047 | #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) | |
7048 | {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, | |
28e7409f NC |
7049 | #define OPTION_PCREL (OPTION_MD_BASE + 7) |
7050 | {"pcrel", no_argument, NULL, OPTION_PCREL}, | |
252b5132 RH |
7051 | {NULL, no_argument, NULL, 0} |
7052 | }; | |
bc805888 | 7053 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
7054 | |
7055 | int | |
31302357 | 7056 | md_parse_option (int c, char *arg) |
252b5132 RH |
7057 | { |
7058 | switch (c) | |
7059 | { | |
7060 | case 'l': /* -l means keep external to 2 bit offset | |
36759679 | 7061 | rather than 16 bit one. */ |
252b5132 RH |
7062 | flag_short_refs = 1; |
7063 | break; | |
7064 | ||
7065 | case 'S': /* -S means that jbsr's always turn into | |
7066 | jsr's. */ | |
7067 | flag_long_jumps = 1; | |
7068 | break; | |
7069 | ||
28e7409f NC |
7070 | case OPTION_PCREL: /* --pcrel means never turn PC-relative |
7071 | branches into absolute jumps. */ | |
7072 | flag_keep_pcrel = 1; | |
7073 | break; | |
7074 | ||
252b5132 RH |
7075 | case 'A': |
7076 | if (*arg == 'm') | |
8a104df9 | 7077 | arg++; |
36759679 | 7078 | /* Intentional fall-through. */ |
252b5132 RH |
7079 | case 'm': |
7080 | ||
7081 | if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') | |
7082 | { | |
7083 | int i; | |
7084 | unsigned long arch; | |
7085 | const char *oarg = arg; | |
7086 | ||
7087 | arg += 3; | |
7088 | if (*arg == 'm') | |
7089 | { | |
7090 | arg++; | |
7091 | if (arg[0] == 'c' && arg[1] == '6') | |
7092 | arg++; | |
7093 | } | |
7094 | for (i = 0; i < n_archs; i++) | |
7095 | if (!strcmp (arg, archs[i].name)) | |
7096 | break; | |
7097 | if (i == n_archs) | |
329e276d NC |
7098 | return 0; |
7099 | ||
252b5132 RH |
7100 | arch = archs[i].arch; |
7101 | if (arch == m68881) | |
7102 | no_68881 = 1; | |
7103 | else if (arch == m68851) | |
7104 | no_68851 = 1; | |
7105 | else | |
329e276d | 7106 | return 0; |
252b5132 RH |
7107 | } |
7108 | else | |
7109 | { | |
7110 | int i; | |
7111 | ||
7112 | if (arg[0] == 'c' && arg[1] == '6') | |
7113 | arg++; | |
7114 | ||
7115 | for (i = 0; i < n_archs; i++) | |
7116 | if (!strcmp (arg, archs[i].name)) | |
7117 | { | |
7118 | unsigned long arch = archs[i].arch; | |
329e276d | 7119 | |
252b5132 RH |
7120 | if (cpu_of_arch (arch)) |
7121 | /* It's a cpu spec. */ | |
7122 | { | |
7123 | current_architecture &= ~m68000up; | |
7124 | current_architecture |= arch; | |
990ae22a | 7125 | current_chip = archs[i].chip; |
252b5132 RH |
7126 | } |
7127 | else if (arch == m68881) | |
7128 | { | |
7129 | current_architecture |= m68881; | |
7130 | no_68881 = 0; | |
7131 | } | |
7132 | else if (arch == m68851) | |
7133 | { | |
7134 | current_architecture |= m68851; | |
7135 | no_68851 = 0; | |
7136 | } | |
7137 | else | |
7138 | /* ??? */ | |
7139 | abort (); | |
7140 | break; | |
7141 | } | |
7142 | if (i == n_archs) | |
7143 | { | |
7144 | as_bad (_("unrecognized architecture specification `%s'"), arg); | |
7145 | return 0; | |
7146 | } | |
7147 | } | |
7148 | break; | |
7149 | ||
7150 | case OPTION_PIC: | |
7151 | case 'k': | |
7152 | flag_want_pic = 1; | |
36759679 | 7153 | break; /* -pic, Position Independent Code. */ |
252b5132 RH |
7154 | |
7155 | case OPTION_REGISTER_PREFIX_OPTIONAL: | |
7156 | flag_reg_prefix_optional = 1; | |
7157 | reg_prefix_optional_seen = 1; | |
7158 | break; | |
7159 | ||
7160 | /* -V: SVR4 argument to print version ID. */ | |
7161 | case 'V': | |
7162 | print_version_id (); | |
7163 | break; | |
7164 | ||
7165 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
7166 | should be emitted or not. FIXME: Not implemented. */ | |
7167 | case 'Q': | |
7168 | break; | |
7169 | ||
7170 | case OPTION_BITWISE_OR: | |
7171 | { | |
7172 | char *n, *t; | |
7173 | const char *s; | |
7174 | ||
7175 | n = (char *) xmalloc (strlen (m68k_comment_chars) + 1); | |
7176 | t = n; | |
7177 | for (s = m68k_comment_chars; *s != '\0'; s++) | |
7178 | if (*s != '|') | |
7179 | *t++ = *s; | |
7180 | *t = '\0'; | |
7181 | m68k_comment_chars = n; | |
7182 | } | |
7183 | break; | |
7184 | ||
7185 | case OPTION_BASE_SIZE_DEFAULT_16: | |
7186 | m68k_index_width_default = SIZE_WORD; | |
7187 | break; | |
7188 | ||
7189 | case OPTION_BASE_SIZE_DEFAULT_32: | |
7190 | m68k_index_width_default = SIZE_LONG; | |
7191 | break; | |
7192 | ||
7193 | case OPTION_DISP_SIZE_DEFAULT_16: | |
7194 | m68k_rel32 = 0; | |
7195 | m68k_rel32_from_cmdline = 1; | |
7196 | break; | |
7197 | ||
7198 | case OPTION_DISP_SIZE_DEFAULT_32: | |
7199 | m68k_rel32 = 1; | |
7200 | m68k_rel32_from_cmdline = 1; | |
7201 | break; | |
7202 | ||
7203 | default: | |
7204 | return 0; | |
7205 | } | |
7206 | ||
7207 | return 1; | |
7208 | } | |
7209 | ||
7210 | void | |
31302357 | 7211 | md_show_usage (FILE *stream) |
252b5132 | 7212 | { |
76f57f3a | 7213 | const char *default_cpu = TARGET_CPU; |
f1f5ef86 AM |
7214 | int i; |
7215 | unsigned int default_arch; | |
76f57f3a | 7216 | |
8a104df9 | 7217 | /* Get the canonical name for the default target CPU. */ |
76f57f3a JT |
7218 | if (*default_cpu == 'm') |
7219 | default_cpu++; | |
7220 | for (i = 0; i < n_archs; i++) | |
7221 | { | |
7222 | if (strcasecmp (default_cpu, archs[i].name) == 0) | |
7223 | { | |
7224 | default_arch = archs[i].arch; | |
7225 | for (i = 0; i < n_archs; i++) | |
7226 | { | |
7227 | if (archs[i].arch == default_arch | |
7228 | && !archs[i].alias) | |
7229 | { | |
7230 | default_cpu = archs[i].name; | |
7231 | break; | |
7232 | } | |
7233 | } | |
7234 | } | |
7235 | } | |
7236 | ||
bc805888 | 7237 | fprintf (stream, _("\ |
252b5132 RH |
7238 | 680X0 options:\n\ |
7239 | -l use 1 word for refs to undefined symbols [default 2]\n\ | |
98b32482 NC |
7240 | -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\ |
7241 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\ | |
6b6e92f4 NC |
7242 | -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\ |
7243 | -m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\ | |
76f57f3a | 7244 | specify variant of 680X0 architecture [default %s]\n\ |
252b5132 RH |
7245 | -m68881 | -m68882 | -mno-68881 | -mno-68882\n\ |
7246 | target has/lacks floating-point coprocessor\n\ | |
76f57f3a JT |
7247 | [default yes for 68020, 68030, and cpu32]\n"), |
7248 | default_cpu); | |
bc805888 | 7249 | fprintf (stream, _("\ |
252b5132 RH |
7250 | -m68851 | -mno-68851\n\ |
7251 | target has/lacks memory-management unit coprocessor\n\ | |
7252 | [default yes for 68020 and up]\n\ | |
7253 | -pic, -k generate position independent code\n\ | |
7254 | -S turn jbsr into jsr\n\ | |
28e7409f | 7255 | --pcrel never turn PC-relative branches into absolute jumps\n\ |
252b5132 RH |
7256 | --register-prefix-optional\n\ |
7257 | recognize register names without prefix character\n\ | |
7258 | --bitwise-or do not treat `|' as a comment character\n")); | |
7259 | fprintf (stream, _("\ | |
7260 | --base-size-default-16 base reg without size is 16 bits\n\ | |
7261 | --base-size-default-32 base reg without size is 32 bits (default)\n\ | |
7262 | --disp-size-default-16 displacement with unknown size is 16 bits\n\ | |
7263 | --disp-size-default-32 displacement with unknown size is 32 bits (default)\n")); | |
7264 | } | |
7265 | \f | |
7266 | #ifdef TEST2 | |
7267 | ||
7268 | /* TEST2: Test md_assemble() */ | |
36759679 NC |
7269 | /* Warning, this routine probably doesn't work anymore. */ |
7270 | int | |
31302357 | 7271 | main (void) |
252b5132 RH |
7272 | { |
7273 | struct m68k_it the_ins; | |
7274 | char buf[120]; | |
7275 | char *cp; | |
7276 | int n; | |
7277 | ||
7278 | m68k_ip_begin (); | |
7279 | for (;;) | |
7280 | { | |
7281 | if (!gets (buf) || !*buf) | |
7282 | break; | |
7283 | if (buf[0] == '|' || buf[1] == '.') | |
7284 | continue; | |
7285 | for (cp = buf; *cp; cp++) | |
7286 | if (*cp == '\t') | |
7287 | *cp = ' '; | |
7288 | if (is_label (buf)) | |
7289 | continue; | |
7290 | memset (&the_ins, '\0', sizeof (the_ins)); | |
7291 | m68k_ip (&the_ins, buf); | |
7292 | if (the_ins.error) | |
7293 | { | |
7294 | printf (_("Error %s in %s\n"), the_ins.error, buf); | |
7295 | } | |
7296 | else | |
7297 | { | |
7298 | printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); | |
7299 | for (n = 0; n < the_ins.numo; n++) | |
7300 | printf (" 0x%x", the_ins.opcode[n] & 0xffff); | |
7301 | printf (" "); | |
7302 | print_the_insn (&the_ins.opcode[0], stdout); | |
7303 | (void) putchar ('\n'); | |
7304 | } | |
7305 | for (n = 0; n < strlen (the_ins.args) / 2; n++) | |
7306 | { | |
7307 | if (the_ins.operands[n].error) | |
7308 | { | |
7309 | printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); | |
7310 | continue; | |
7311 | } | |
31302357 AS |
7312 | printf ("mode %d, reg %d, ", the_ins.operands[n].mode, |
7313 | the_ins.operands[n].reg); | |
252b5132 | 7314 | if (the_ins.operands[n].b_const) |
31302357 AS |
7315 | printf ("Constant: '%.*s', ", |
7316 | 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, | |
7317 | the_ins.operands[n].b_const); | |
7318 | printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, | |
7319 | the_ins.operands[n].isiz, the_ins.operands[n].imul); | |
252b5132 | 7320 | if (the_ins.operands[n].b_iadd) |
31302357 AS |
7321 | printf ("Iadd: '%.*s',", |
7322 | 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, | |
7323 | the_ins.operands[n].b_iadd); | |
7324 | putchar ('\n'); | |
252b5132 RH |
7325 | } |
7326 | } | |
7327 | m68k_ip_end (); | |
7328 | return 0; | |
7329 | } | |
7330 | ||
31302357 AS |
7331 | int |
7332 | is_label (char *str) | |
252b5132 RH |
7333 | { |
7334 | while (*str == ' ') | |
7335 | str++; | |
7336 | while (*str && *str != ' ') | |
7337 | str++; | |
7338 | if (str[-1] == ':' || str[1] == '=') | |
7339 | return 1; | |
7340 | return 0; | |
7341 | } | |
7342 | ||
7343 | #endif | |
7344 | ||
7345 | /* Possible states for relaxation: | |
7346 | ||
7347 | 0 0 branch offset byte (bra, etc) | |
7348 | 0 1 word | |
7349 | 0 2 long | |
7350 | ||
7351 | 1 0 indexed offsets byte a0@(32,d4:w:1) etc | |
7352 | 1 1 word | |
7353 | 1 2 long | |
7354 | ||
7355 | 2 0 two-offset index word-word a0@(32,d4)@(45) etc | |
7356 | 2 1 word-long | |
7357 | 2 2 long-word | |
7358 | 2 3 long-long | |
7359 | ||
7360 | */ | |
7361 | ||
7362 | /* We have no need to default values of symbols. */ | |
7363 | ||
252b5132 | 7364 | symbolS * |
31302357 | 7365 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
7366 | { |
7367 | return 0; | |
7368 | } | |
7369 | ||
7370 | /* Round up a section size to the appropriate boundary. */ | |
7371 | valueT | |
31302357 | 7372 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
7373 | { |
7374 | #ifdef OBJ_AOUT | |
7375 | #ifdef BFD_ASSEMBLER | |
7376 | /* For a.out, force the section size to be aligned. If we don't do | |
7377 | this, BFD will align it for us, but it will not write out the | |
7378 | final bytes of the section. This may be a bug in BFD, but it is | |
7379 | easier to fix it here since that is how the other a.out targets | |
7380 | work. */ | |
7381 | int align; | |
7382 | ||
7383 | align = bfd_get_section_alignment (stdoutput, segment); | |
7384 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
7385 | #endif | |
7386 | #endif | |
7387 | ||
7388 | return size; | |
7389 | } | |
7390 | ||
7391 | /* Exactly what point is a PC-relative offset relative TO? | |
7392 | On the 68k, it is relative to the address of the first extension | |
7393 | word. The difference between the addresses of the offset and the | |
92774660 | 7394 | first extension word is stored in fx_pcrel_adjust. */ |
252b5132 | 7395 | long |
31302357 | 7396 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
7397 | { |
7398 | int adjust; | |
7399 | ||
8390138c AS |
7400 | /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly |
7401 | sign extend the value here. */ | |
7402 | adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80; | |
252b5132 RH |
7403 | if (adjust == 64) |
7404 | adjust = -1; | |
7405 | return fixP->fx_where + fixP->fx_frag->fr_address - adjust; | |
7406 | } | |
7407 | ||
7408 | #ifndef BFD_ASSEMBLER | |
7409 | #ifdef OBJ_COFF | |
7410 | ||
252b5132 | 7411 | void |
31302357 | 7412 | tc_coff_symbol_emit_hook (symbolS *ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
7413 | { |
7414 | } | |
7415 | ||
7416 | int | |
31302357 | 7417 | tc_coff_sizemachdep (fragS *frag) |
252b5132 RH |
7418 | { |
7419 | switch (frag->fr_subtype & 0x3) | |
7420 | { | |
7421 | case BYTE: | |
7422 | return 1; | |
7423 | case SHORT: | |
7424 | return 2; | |
7425 | case LONG: | |
7426 | return 4; | |
7427 | default: | |
7428 | abort (); | |
7429 | return 0; | |
7430 | } | |
7431 | } | |
7432 | ||
7433 | #endif | |
7434 | #endif | |
31302357 | 7435 | |
0d96863f | 7436 | #ifdef OBJ_ELF |
8a104df9 | 7437 | void |
31302357 | 7438 | m68k_elf_final_processing (void) |
0d96863f | 7439 | { |
36759679 | 7440 | /* Set file-specific flags if this is a cpu32 processor. */ |
8a104df9 KH |
7441 | if (cpu_of_arch (current_architecture) & cpu32) |
7442 | elf_elfheader (stdoutput)->e_flags |= EF_CPU32; | |
7443 | else if ((cpu_of_arch (current_architecture) & m68000up) | |
7444 | && !(cpu_of_arch (current_architecture) & m68020up)) | |
7445 | elf_elfheader (stdoutput)->e_flags |= EF_M68000; | |
0d96863f CM |
7446 | } |
7447 | #endif | |
c04898f8 AS |
7448 | |
7449 | int | |
7450 | tc_m68k_regname_to_dw2regnum (const char *regname) | |
7451 | { | |
7452 | unsigned int regnum; | |
7453 | static const char *const regnames[] = | |
7454 | { | |
7455 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
7456 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", | |
7457 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", | |
7458 | "pc" | |
7459 | }; | |
7460 | ||
7461 | for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) | |
7462 | if (strcmp (regname, regnames[regnum]) == 0) | |
7463 | return regnum; | |
7464 | ||
7465 | return -1; | |
7466 | } | |
7467 | ||
7468 | void | |
7469 | tc_m68k_frame_initial_instructions (void) | |
7470 | { | |
7471 | static int sp_regno = -1; | |
7472 | ||
7473 | if (sp_regno < 0) | |
7474 | sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); | |
7475 | ||
7476 | cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); | |
7477 | cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); | |
7478 | } |