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* targets.c (target_vector): Remove SCO_CORE. On Sep 11 1993,
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
a87b3269 1/* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
fecd2382 2 slow to compile, easy to find file.
6d27d3a2 3
bcb8dff8 4 Copyright (C) 1987, 1991, 1992, 1993 Free Software Foundation, Inc.
6d27d3a2 5
a39116f1 6 This file is part of GAS, the GNU Assembler.
6d27d3a2 7
a39116f1
RP		 8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
6d27d3a2 12
a39116f1
RP		 13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
6d27d3a2 17
a39116f1
RP		 18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
fecd2382
RP		 21
22#include <ctype.h>
f8701a3f 23#define NO_RELOC 0
fecd2382
RP		 24#include "as.h"
25
e284846a
KR		 26/* need TARGET_CPU */
27#include "config.h"
28
fecd2382
RP		 29#include "obstack.h"
30
e284846a
KR		 31/* The opcode table is too big for gcc, which (currently) requires
32 exponential space at compile time for initialized arrays. */
33#ifdef __GNUC__
34#define DO_BREAK_UP_BIG_DECL
35#define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
36#define AND_OTHER_PART sizeof (m68k_opcodes_2)
37#endif
38
39/* Note that this file includes real declarations and thus can only be
40 included by one source file per executable. */
e0982afe 41#include "opcode/m68k.h"
3ad9ec6a 42
fecd2382
RP		 43/* This array holds the chars that always start a comment. If the
44 pre-processor is disabled, these aren't very useful */
49864cfa 45CONST char comment_chars[] = "|";
fecd2382
RP		 46
47/* This array holds the chars that only start a comment at the beginning of
48 a line. If the line seems to have the form '# 123 filename'
49 .line and .file directives will appear in the pre-processed output */
50/* Note that input_file.c hand checks for '#' at the beginning of the
51 first line of the input file. This is because the compiler outputs
52 #NO_APP at the beginning of its output. */
53/* Also note that comments like this one will always work. */
49864cfa 54CONST char line_comment_chars[] = "#";
fecd2382 55
49864cfa 56CONST char line_separator_chars[] = "";
587c4264 57
fecd2382 58/* Chars that can be used to separate mant from exp in floating point nums */
49864cfa 59CONST char EXP_CHARS[] = "eE";
fecd2382 60
49864cfa
KR		 61/* Chars that mean this number is a floating point constant, as
62 in "0f12.456" or "0d1.2345e12". */
fecd2382 63
49864cfa 64CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
fecd2382
RP		 65
66/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
49864cfa 68 but nothing is ideal around here. */
fecd2382 69
49864cfa 70const int md_reloc_size = 8; /* Size of relocation record */
fecd2382 71
b80d39a0 72/* Are we trying to generate PIC code? If so, absolute references
dff60b7d
ILT		 73 ought to be made into linkage table references or pc-relative
74 references. */
b80d39a0
KR		 75int flag_want_pic;
76
fecd2382
RP		 77/* Its an arbitrary name: This means I don't approve of it */
78/* See flames below */
79static struct obstack robyn;
80
81#define TAB(x,y) (((x)<<2)+(y))
82#define TABTYPE(xy) ((xy) >> 2)
83#define BYTE 0
84#define SHORT 1
85#define LONG 2
86#define SZ_UNDEF 3
3ad9ec6a
ILT		 87#undef BRANCH
88#define ABRANCH 1
fecd2382
RP		 89#define FBRANCH 2
90#define PCREL 3
91#define BCC68000 4
92#define DBCC 5
93#define PCLEA 6
94
bcb8dff8
KR		 95struct m68k_incant
96 {
97 char *m_operands;
98 unsigned long m_opcode;
99 short m_opnum;
100 short m_codenum;
101 int m_arch;
102 struct m68k_incant *m_next;
103 };
104
105#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
106#define gettwo(x) (((x)->m_opcode)&0xffff)
107
f6e504fe 108/* Operands we can parse: (And associated modes)
6d27d3a2 109
a39116f1
RP		 110 numb: 8 bit num
111 numw: 16 bit num
112 numl: 32 bit num
113 dreg: data reg 0-7
114 reg: address or data register
115 areg: address register
116 apc: address register, PC, ZPC or empty string
117 num: 16 or 32 bit num
118 num2: like num
119 sz: w or l if omitted, l assumed
120 scale: 1 2 4 or 8 if omitted, 1 assumed
6d27d3a2 121
a39116f1
RP		 122 7.4 IMMED #num --> NUM
123 0.? DREG dreg --> dreg
124 1.? AREG areg --> areg
125 2.? AINDR areg@ --> *(areg)
126 3.? AINC areg@+ --> *(areg++)
127 4.? ADEC areg@- --> *(--areg)
128 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
129 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
130 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
131 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
132 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
133 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
134 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
135 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
136 7.0 ABSL num:sz --> *(num)
137 num --> *(num) (sz L assumed)
138 *** MSCR otherreg --> Magic
139 With -l option
140 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
c50140c8 141 ?.? DINDR dreg@ --> (dreg) -- cas2 only
6d27d3a2 142
a39116f1
RP		 143 examples:
144 #foo #0x35 #12
145 d2
146 a4
147 a3@
148 a5@+
149 a6@-
150 a2@(12) pc@(14)
151 a1@(5,d2:w:1) @(45,d6:l:4)
152 pc@(a2) @(d4)
153 etc . . .
6d27d3a2
KR		 154
155
a39116f1
RP		 156 #name@(numw) -->turn into PC rel mode
157 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
6d27d3a2 158
a39116f1 159 */
f6e504fe 160
355afbcd
KR		 161enum operand_type
162 {
163 IMMED = 1,
164 DREG,
165 AREG,
166 AINDR,
167 ADEC,
168 AINC,
169 AOFF,
170 AINDX,
171 APODX,
172 AMIND,
173 APRDX,
174 ABSL,
175 MSCR,
176 REGLST,
177 DINDR
178 };
179
180
181struct m68k_exp
182 {
183 char *e_beg;
184 char *e_end;
bcb8dff8 185 segT e_seg;
355afbcd
KR		 186 expressionS e_exp;
187 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
188 };
fecd2382 189
7c15cbe8
RP		 190/* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
191 8-15==addr reg for operands that take both types */
192
355afbcd
KR		 193enum _register
194 {
195 DATA = 1, /* 1- 8 == data registers 0-7 */
196 DATA0 = DATA,
197 DATA1,
198 DATA2,
199 DATA3,
200 DATA4,
201 DATA5,
202 DATA6,
203 DATA7,
204
205 ADDR,
206 ADDR0 = ADDR,
207 ADDR1,
208 ADDR2,
209 ADDR3,
210 ADDR4,
211 ADDR5,
212 ADDR6,
213 ADDR7,
214
215 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
216 /* I think. . . */
217
218 SP = ADDR7,
219
220 FPREG, /* Eight FP registers */
221 FP0 = FPREG,
222 FP1,
223 FP2,
224 FP3,
225 FP4,
226 FP5,
227 FP6,
228 FP7,
229 COPNUM = (FPREG + 8), /* Co-processor #1-#8 */
230 COP0 = COPNUM,
231 COP1,
232 COP2,
233 COP3,
234 COP4,
235 COP5,
236 COP6,
237 COP7,
238 PC, /* Program counter */
239 ZPC, /* Hack for Program space, but 0 addressing */
240 SR, /* Status Reg */
241 CCR, /* Condition code Reg */
242
243 /* These have to be in order for the movec instruction to work. */
244 USP, /* User Stack Pointer */
245 ISP, /* Interrupt stack pointer */
246 SFC,
247 DFC,
248 CACR,
249 VBR,
250 CAAR,
251 MSP,
252 ITT0,
253 ITT1,
254 DTT0,
255 DTT1,
256 MMUSR,
257 TC,
258 SRP,
259 URP,
260 /* end of movec ordering constraints */
261
262 FPI,
263 FPS,
264 FPC,
265
266 DRP, /* 68851 or 68030 MMU regs */
267 CRP,
268 CAL,
269 VAL,
270 SCC,
271 AC,
272 BAD,
273 BAD0 = BAD,
274 BAD1,
275 BAD2,
276 BAD3,
277 BAD4,
278 BAD5,
279 BAD6,
280 BAD7,
281 BAC,
282 BAC0 = BAC,
283 BAC1,
284 BAC2,
285 BAC3,
286 BAC4,
287 BAC5,
288 BAC6,
289 BAC7,
290 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
1404ef23 291 and ACUSR on 68ec030 */
355afbcd 292 PCSR,
6d27d3a2 293
355afbcd
KR		 294 IC, /* instruction cache token */
295 DC, /* data cache token */
296 NC, /* no cache token */
297 BC, /* both caches token */
6d27d3a2 298
355afbcd
KR		 299 TT0, /* 68030 access control unit regs */
300 TT1,
301 };
7c15cbe8 302
fecd2382 303/* Internal form of an operand. */
355afbcd
KR		 304struct m68k_op
305 {
306 char *error; /* Couldn't parse it */
307 enum operand_type mode; /* What mode this instruction is in. */
308 enum _register reg; /* Base register */
309 struct m68k_exp *con1;
310 int ireg; /* Index register */
311 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
312 int imul; /* Multipy ireg by this (1,2,4,or 8) */
313 struct m68k_exp *con2;
314 };
fecd2382
RP		 315
316/* internal form of a 68020 instruction */
355afbcd
KR		 317struct m68k_it
318 {
319 char *error;
320 char *args; /* list of opcode info */
321 int numargs;
322
323 int numo; /* Number of shorts in opcode */
324 short opcode[11];
325
326 struct m68k_op operands[6];
327
328 int nexp; /* number of exprs in use */
329 struct m68k_exp exprs[4];
330
331 int nfrag; /* Number of frags we have to produce */
332 struct
333 {
334 int fragoff; /* Where in the current opcode[] the frag ends */
335 symbolS *fadd;
336 long foff;
337 int fragty;
338 }
339 fragb[4];
340
341 int nrel; /* Num of reloc strucs in use */
342 struct
343 {
344 int n;
bcb8dff8 345 expressionS exp;
355afbcd
KR		 346 char wid;
347 char pcrel;
348 }
349 reloc[5]; /* Five is enough??? */
350 };
fecd2382 351
865a2edf
MT		 352#define cpu_of_arch(x) ((x) & m68000up)
353#define float_of_arch(x) ((x) & mfloat)
354#define mmu_of_arch(x) ((x) & mmmu)
355
355afbcd 356static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 357
bcb8dff8
KR		 358#define seg(exp) ((exp)->e_seg)
359#define op(exp) ((exp)->e_exp.X_op)
49864cfa 360#define adds(exp) ((exp)->e_exp.X_add_symbol)
bcb8dff8 361#define subs(exp) ((exp)->e_exp.X_op_symbol)
49864cfa
KR		 362#define offs(exp) ((exp)->e_exp.X_add_number)
363
7c15cbe8 364/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 365
366#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
367
368/* Like addword, but goes BEFORE general operands */
bcb8dff8
KR		 369static void
370insop (w, opcode)
371 int w;
372 struct m68k_incant *opcode;
373{
374 int z;
375 for(z=the_ins.numo;z>opcode->m_codenum;--z)
376 the_ins.opcode[z]=the_ins.opcode[z-1];
377 for(z=0;z<the_ins.nrel;z++)
378 the_ins.reloc[z].n+=2;
379 the_ins.opcode[opcode->m_codenum]=w;
380 the_ins.numo++;
381}
fecd2382 382
bcb8dff8
KR		 383static struct m68k_exp *
384add_exp (beg, end)
385 char *beg;
386 char *end;
387{
388 the_ins.exprs[the_ins.nexp].e_beg=beg;
389 the_ins.exprs[the_ins.nexp].e_end=end;
390 return &the_ins.exprs[the_ins.nexp++];
391}
fecd2382
RP		 392
393
1404ef23
KR		 394/* The numo+1 kludge is so we can hit the low order byte of the prev word.
395 Blecch. */
49864cfa
KR		 396static void
397add_fix (width, exp, pc_rel)
398 char width;
399 struct m68k_exp *exp;
400 int pc_rel;
401{
402 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
403 ? (the_ins.numo*2-1)
404 : (((width)=='b')
405 ? ((the_ins.numo-1)*2)
406 : (the_ins.numo*2)));
bcb8dff8 407 the_ins.reloc[the_ins.nrel].exp = exp->e_exp;
49864cfa
KR		 408 the_ins.reloc[the_ins.nrel].wid = width;
409 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
1404ef23
KR		 410}
411
49864cfa
KR		 412static void
413add_frag(add,off,type)
414 symbolS *add;
415 long off;
416 int type;
417{
418 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
419 the_ins.fragb[the_ins.nfrag].fadd=add;
420 the_ins.fragb[the_ins.nfrag].foff=off;
421 the_ins.fragb[the_ins.nfrag++].fragty=type;
1404ef23 422}
fecd2382 423
bcb8dff8
KR		 424#define isvar(exp) \
425 ((exp) && op (exp) != O_constant && op (exp) != O_big)
fecd2382 426
49864cfa
KR		 427static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
428static int get_num PARAMS ((struct m68k_exp *exp, int ok));
429static int get_regs PARAMS ((int i, char *str, struct m68k_op *opP));
430static int reverse_16_bits PARAMS ((int in));
431static int reverse_8_bits PARAMS ((int in));
432static int try_index PARAMS ((char **s, struct m68k_op *opP));
433static void install_gen_operand PARAMS ((int mode, int val));
434static void install_operand PARAMS ((int mode, int val));
bcb8dff8
KR		 435static void s_bss PARAMS ((int));
436static void s_data1 PARAMS ((int));
437static void s_data2 PARAMS ((int));
438static void s_even PARAMS ((int));
439static void s_proc PARAMS ((int));
49864cfa
KR		 440
441static int current_architecture;
7c15cbe8 442
fecd2382
RP		 443/* BCC68000 is for patching in an extra jmp instruction for long offsets
444 on the 68000. The 68000 doesn't support long branches with branchs */
445
446/* This table desribes how you change sizes for the various types of variable
447 size expressions. This version only supports two kinds. */
448
49864cfa
KR		 449/* Note that calls to frag_var need to specify the maximum expansion
450 needed; this is currently 10 bytes for DBCC. */
fecd2382
RP		 451
452/* The fields are:
a39116f1
RP		 453 How far Forward this mode will reach:
454 How far Backward this mode will reach:
455 How many bytes this mode will add to the size of the frag
456 Which mode to go to if the offset won't fit in this one
457 */
49864cfa 458CONST relax_typeS md_relax_table[] =
355afbcd
KR		 459{
460 {1, 1, 0, 0}, /* First entries aren't used */
461 {1, 1, 0, 0}, /* For no good reason except */
462 {1, 1, 0, 0}, /* that the VAX doesn't either */
463 {1, 1, 0, 0},
464
465 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
466 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
467 {0, 0, 4, 0},
468 {1, 1, 0, 0},
469
470 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
471 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
472 {0, 0, 4, 0},
473 {1, 1, 0, 0},
474
475 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
476 {(32767), (-32768), 2, TAB (PCREL, LONG)},
477 {0, 0, 4, 0},
478 {1, 1, 0, 0},
479
480 {(127), (-128), 0, TAB (BCC68000, SHORT)},
481 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
482 {0, 0, 6, 0}, /* jmp long space */
483 {1, 1, 0, 0},
484
485 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
486 {(32767), (-32768), 2, TAB (DBCC, LONG)},
487 {0, 0, 10, 0}, /* bra/jmp long space */
488 {1, 1, 0, 0},
489
490 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
491 {32767, -32768, 2, TAB (PCLEA, LONG)},
492 {0, 0, 6, 0},
493 {1, 1, 0, 0},
494
495};
fecd2382
RP		 496
497/* These are the machine dependent pseudo-ops. These are included so
498 the assembler can work on the output from the SUN C compiler, which
499 generates these.
a39116f1 500 */
fecd2382
RP		 501
502/* This table describes all the machine specific pseudo-ops the assembler
503 has to support. The fields are:
a39116f1
RP		 504 pseudo-op name without dot
505 function to call to execute this pseudo-op
506 Integer arg to pass to the function
507 */
49864cfa 508CONST pseudo_typeS md_pseudo_table[] =
355afbcd
KR		 509{
510 {"data1", s_data1, 0},
511 {"data2", s_data2, 0},
512 {"bss", s_bss, 0},
513 {"even", s_even, 0},
514 {"skip", s_space, 0},
515 {"proc", s_proc, 0},
bec66218 516#ifdef TE_SUN3
355afbcd 517 {"align", s_align_bytes, 0},
bec66218 518#endif
355afbcd 519 {0, 0, 0}
fecd2382
RP		 520};
521
522
3ad9ec6a 523/* The mote pseudo ops are put into the opcode table, since they
355afbcd 524 don't start with a . they look like opcodes to gas.
3ad9ec6a 525 */
355afbcd 526extern void obj_coff_section ();
3ad9ec6a 527
49864cfa 528CONST pseudo_typeS mote_pseudo_table[] =
3ad9ec6a
ILT		 529{
530
355afbcd
KR		 531 {"dc.l", cons, 4},
532 {"dc", cons, 2},
533 {"dc.w", cons, 2},
534 {"dc.b", cons, 1},
3ad9ec6a 535
355afbcd
KR		 536 {"ds.l", s_space, 4},
537 {"ds", s_space, 2},
538 {"ds.w", s_space, 2},
539 {"ds.b", s_space, 1},
3ad9ec6a 540
355afbcd
KR		 541 {"xdef", s_globl, 0},
542 {"align", s_align_ptwo, 0},
3ad9ec6a 543#ifdef M68KCOFF
355afbcd
KR		 544 {"sect", obj_coff_section, 0},
545 {"section", obj_coff_section, 0},
3ad9ec6a 546#endif
bcb8dff8 547 {0, 0, 0}
3ad9ec6a
ILT		 548};
549
fecd2382
RP		 550#define issbyte(x) ((x)>=-128 && (x)<=127)
551#define isubyte(x) ((x)>=0 && (x)<=255)
552#define issword(x) ((x)>=-32768 && (x)<=32767)
553#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 554
e284846a 555#define isbyte(x) ((x)>= -255 && (x)<=255)
fecd2382
RP		 556#define isword(x) ((x)>=-32768 && (x)<=65535)
557#define islong(x) (1)
f8701a3f
SC		 558
559extern char *input_line_pointer;
fecd2382 560
355afbcd
KR		 561enum
562 {
563 FAIL = 0,
564 OK = 1,
565 };
fecd2382
RP		 566
567/* JF these tables here are for speed at the expense of size */
568/* You can replace them with the #if 0 versions if you really
569 need space and don't mind it running a bit slower */
570
571static char mklower_table[256];
572#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 573static char notend_table[256];
fecd2382
RP		 574static char alt_notend_table[256];
575#define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
a39116f1 576 alt_notend_table[(unsigned char)(s[1])])))
fecd2382
RP		 577
578#if 0
579#define mklower(c) (isupper(c) ? tolower(c) : c)
580#endif
f8701a3f
SC		 581
582
583/* JF modified this to handle cases where the first part of a symbol name
584 looks like a register */
585
586/*
587 * m68k_reg_parse() := if it looks like a register, return it's token &
588 * advance the pointer.
589 */
590
355afbcd
KR		 591enum _register
592m68k_reg_parse (ccp)
593 register char **ccp;
fecd2382 594{
f8701a3f 595 char *start = *ccp;
0069b1f6
ILT		 596 char c;
597 char *p;
598 symbolS *symbolP;
f8701a3f 599
587c4264 600#ifdef REGISTER_PREFIX
0069b1f6
ILT		 601 if (*start != REGISTER_PREFIX)
602 return FAIL;
603 p = start + 1;
604#else
605 p = start;
606 if (*p == OPTIONAL_REGISTER_PREFIX)
607 p++, start++;
587c4264 608#endif
0069b1f6
ILT		 609 if (!isalpha (*p) || !is_name_beginner (*p))
610 return FAIL;
587c4264 611
0069b1f6 612 c = *p++;
355afbcd 613 while (isalpha (c) || isdigit (c) || c == '_')
0069b1f6
ILT		 614 {
615 c = *p++;
616 }
3ad9ec6a 617
355afbcd
KR		 618 *--p = 0;
619 symbolP = symbol_find (start);
620 *p = c;
f8701a3f 621
49864cfa 622 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
a39116f1 623 {
f8701a3f 624 *ccp = p;
355afbcd 625 return S_GET_VALUE (symbolP);
a39116f1 626 }
f8701a3f 627
0069b1f6 628 return FAIL;
fecd2382
RP		 629}
630
631#define SKIP_WHITE() { str++; if(*str==' ') str++;}
3ad9ec6a
ILT		 632#define SKIP_W() { ss++; if(*ss==' ') ss++;}
633
634/* Parse an index specification using Motorola syntax. */
635
636static int
355afbcd
KR		 637try_moto_index (s, opP)
638 char **s;
639 struct m68k_op *opP;
3ad9ec6a 640{
355afbcd
KR		 641 register int i;
642 char *ss;
643
644 ss = *s;
645 /* SKIP_W(); */
646 if (*ss == ' ')
647 ss++;
648 i = m68k_reg_parse (&ss);
649 if (!(i >= DATA + 0 && i <= ADDR + 7))
650 { /* if i is not DATA or ADDR reg */
651 opP->error = "Invalid index register";
652 *s = ss;
653 return FAIL;
654 }
655 opP->ireg = i;
656 /* SKIP_W(); */
657 if (*ss == ')')
658 {
659 opP->isiz = 0;
660 opP->imul = 1;
661 SKIP_W ();
662 *s = ss;
663 return OK;
664 }
665 if (*ss != '.')
666 {
667 opP->error = "Missing . in index register";
668 *s = ss;
669 return FAIL;
670 }
671 SKIP_W ();
672 if (mklower (*ss) == 'w')
673 opP->isiz = 2;
674 else if (mklower (*ss) == 'l')
675 opP->isiz = 3;
676 else
677 {
678 opP->error = "Size spec not .W or .L";
679 *s = ss;
680 return FAIL;
681 }
682 SKIP_W ();
683 if (*ss == '.' || *ss == '*')
684 {
685 SKIP_W ();
686 switch (*ss)
687 {
688 case '1':
689 case '2':
690 case '4':
691 case '8':
692 opP->imul = *ss - '0';
693 break;
694 default:
695 opP->error = "index multiplier not 1, 2, 4 or 8";
696 *s = ss;
697 return FAIL;
3ad9ec6a 698 }
355afbcd
KR		 699 SKIP_W ();
700 }
701 else
702 opP->imul = 1;
703 if (*ss != ')')
704 {
705 opP->error = "Missing )";
706 *s = ss;
707 return FAIL;
708 }
709 SKIP_W ();
710 *s = ss;
711 return OK;
3ad9ec6a 712}
fecd2382 713
7c15cbe8 714/*
3ad9ec6a
ILT		 715 *
716 * try_index := data_or_address_register + ')' + SKIP_W
717 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
718 *
719 * multiplier := <empty>
720 * | ':' + multiplier_number
7c15cbe8 721 * ;
6d27d3a2 722 *
3ad9ec6a 723 * multiplier_number := '1' | '2' | '4' | '8' ;
7c15cbe8 724 *
3ad9ec6a
ILT		 725 * size_spec := 'l' | 'L' | 'w' | 'W' ;
726 *
727 * SKIP_W := <empty> | ' ' ;
7c15cbe8
RP		 728 *
729 */
730
355afbcd
KR		 731static int
732try_index (s, opP)
733 char **s;
734 struct m68k_op *opP;
3ad9ec6a 735{
355afbcd
KR		 736 register int i;
737 char *ss;
738
739 ss = *s;
740 /* SKIP_W(); */
741 i = m68k_reg_parse (&ss);
742 if (!(i >= DATA + 0 && i <= ADDR + 7))
743 { /* if i is not DATA or ADDR reg */
744 *s = ss;
745 return FAIL;
746 }
747 opP->ireg = i;
748 /* SKIP_W(); */
749 if (*ss == ')')
750 {
751 opP->isiz = 0;
752 opP->imul = 1;
753 SKIP_W ();
754 *s = ss;
755 return OK;
756 }
757 if (*ss != ':')
758 {
759 opP->error = "Missing : in index register";
760 *s = ss;
761 return FAIL;
762 }
763 SKIP_W ();
764 switch (*ss)
765 {
766 case 'w':
767 case 'W':
768 opP->isiz = 2;
769 break;
770 case 'l':
771 case 'L':
772 opP->isiz = 3;
773 break;
774 default:
775 opP->error = "Index register size spec not :w or :l";
776 *s = ss;
777 return FAIL;
778 }
779 SKIP_W ();
780 if (*ss == ':')
781 {
782 SKIP_W ();
783 switch (*ss)
784 {
785 case '1':
786 case '2':
787 case '4':
788 case '8':
789 if (cpu_of_arch (current_architecture) < m68020)
790 {
791 opP->error = "no index scaling in pre-68020's";
792 *s = ss;
793 return FAIL;
794 }
795 opP->imul = *ss - '0';
796 break;
3ad9ec6a 797 default:
355afbcd
KR		 798 opP->error = "index multiplier not 1, 2, 4 or 8";
799 *s = ss;
800 return FAIL;
3ad9ec6a 801 }
355afbcd
KR		 802 SKIP_W ();
803 }
804 else
805 opP->imul = 1;
806 if (*ss != ')')
807 {
808 opP->error = "Missing )";
809 *s = ss;
810 return FAIL;
811 }
812 SKIP_W ();
813 *s = ss;
814 return OK;
815} /* try_index() */
3ad9ec6a
ILT		 816
817/* Ian Taylor expanded this function to accept both MIT and Motorola
818 syntax. I removed the old comment, since it was wrong. The syntax
819 this accepted even before my changes was complex and undocumented.
820 I mainly added a large case when the operand string does not
821 contain an '@', since the Motorola syntax does not use the '@'
822 character. */
823
fecd2382 824int
355afbcd
KR		 825m68k_ip_op (str, opP)
826 char *str;
827 register struct m68k_op *opP;
fecd2382 828{
355afbcd
KR		 829 char *strend;
830 long i;
831 char *parse_index ();
832 int needp;
3ad9ec6a 833
355afbcd
KR		 834 if (*str == ' ')
835 {
836 str++;
837 } /* Find the beginning of the string */
6d27d3a2 838
355afbcd
KR		 839 if (!*str)
840 {
841 opP->error = "Missing operand";
842 return FAIL;
843 } /* Out of gas */
6d27d3a2 844
355afbcd
KR		 845 for (strend = str; *strend; strend++)
846 ;
847 --strend;
6d27d3a2 848
355afbcd
KR		 849 if (*str == '#')
850 {
851 str++;
852 opP->con1 = add_exp (str, strend);
853 opP->mode = IMMED;
854 return OK;
855 } /* Guess what: A constant. Shar and enjoy */
6d27d3a2 856
355afbcd 857 i = m68k_reg_parse (&str);
6d27d3a2 858
355afbcd
KR		 859 if (i != FAIL)
860 {
861 if (*str == '/' || *str == '-')
862 {
863 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
864 opP->mode = REGLST;
865 return get_regs (i, str, opP);
866 }
867 if (*str == '\0')
868 {
869 opP->reg = i;
870 /* "Rn" Register Direct mode */
871 if (i >= DATA + 0 && i <= DATA + 7)
872 opP->mode = DREG;
873 else if (i >= ADDR + 0 && i <= ADDR + 7)
874 opP->mode = AREG;
875 else
876 opP->mode = MSCR;
877 return OK;
878 }
879 }
6d27d3a2 880
355afbcd
KR		 881 if (*str != '@')
882 {
883 char *stmp;
6d27d3a2 884
355afbcd
KR		 885 if ((stmp = strchr (str, '@')) != 0)
886 {
887 opP->con1 = add_exp (str, stmp - 1);
888 if (stmp == strend)
889 {
890 opP->mode = AINDX;
891 return (OK);
892 }
6d27d3a2 893
355afbcd
KR		 894 if ((current_architecture & m68020up) == 0)
895 {
896 return (FAIL);
897 } /* if target is not a '20 or better */
6d27d3a2 898
355afbcd
KR		 899 stmp++;
900 if (*stmp++ != '(' || *strend-- != ')')
901 {
902 opP->error = "Malformed operand";
903 return (FAIL);
904 }
905 i = try_index (&stmp, opP);
906 opP->con2 = add_exp (stmp, strend);
6d27d3a2 907
355afbcd
KR		 908 if (i == FAIL)
909 {
910 opP->mode = AMIND;
911 }
912 else
913 {
914 opP->mode = APODX;
915 }
916 return (OK);
917 } /* if there's an '@' */
6d27d3a2 918
3ad9ec6a 919#ifndef MIT_SYNTAX_ONLY
355afbcd 920 /* The operand has no '@'. Try to parse it using
49864cfa 921 Motorola syntax. */
355afbcd 922 /* Logic of the parsing switch(*str):
3ad9ec6a
ILT		 923 case opP->mode =
924 ---- -----------
925 #anything IMMED 1
926 REG AREG or DREG or MSCR 3 or 2 or 13
927 REG- or REG/ REGLST 14
928 (REG) AINDR 4
929 (REG)+ AINC 6
930 (REG,INDX) AINDX 8
931 (EXPR,REG) AOFF 7
932 (EXPR,REG,INDX) AINDX 8
933 -(REG) ADEC 5
934 EXP2(REG) AOFF 7
935 EXP2(REG,INDX) AINDX 8
936 EXP2 ABSL 12
937
938 REG means truth(m68k_reg_parse(&str))
939 INDX means truth(try_moto_index(&str,opP))
940 EXPR means not REG
941 EXP2 means not REG and not '(' and not '-('
942 */
943
355afbcd
KR		 944 if (*str == '(')
945 {
946 str++;
947 i = m68k_reg_parse (&str);
948 if ((i < ADDR + 0 || i > ADDR + 7)
949 && (i < DATA + 0 || i > DATA + 7
950 || *str != ')' || str[1] != '0')
951 && i != PC && i != ZPC && i != FAIL)
952 {
953 /* Can't indirect off non address regs */
954 opP->error = "Invalid indirect register";
955 return FAIL;
956 }
957 if (i != FAIL)
958 {
959 opP->reg = i;
960 if (*str == ')')
961 {
962 str++;
963 if (*str == '\0')
964 {
965 /* "(An)" Address Register Indirect mode
3ad9ec6a 966 or "(Dn)" for cas2. */
355afbcd
KR		 967 if (i >= DATA + 0 && i <= DATA + 7)
968 opP->mode = DINDR;
969 else
970 opP->mode = AINDR;
971 return OK;
972 }
973 if (*str == '+')
974 {
975 if (str[1] == '\0')
976 {
977 /* "(An)+" Register Indirect w Postincrement */
978 opP->mode = AINC;
979 return OK;
980 }
981 }
982 opP->error = "Junk after indirect";
983 return FAIL;
984 }
985 if (*str == ',')
986 {
987 str++;
988 i = try_moto_index (&str, opP);
989 if (i == FAIL)
990 return FAIL;
991 /* "(An,Rn)" Register Indirect with Index mode*/
992 opP->mode = AINDX;
993 return OK;
994 }
995 else
996 {
997 opP->error = "Bad indirect syntax";
998 return FAIL;
999 }
1000 }
1001 else
1002 {
1003 /* "(EXPR,..." , a displacement */
1004 char *stmp;
1005 char *index ();
1006
bcb8dff8 1007 if ((stmp = index (str, ',')) != NULL)
355afbcd
KR		 1008 {
1009 opP->con1 = add_exp (str, stmp - 1);
1010 str = stmp;
1011 SKIP_WHITE ();
1012 i = m68k_reg_parse (&str);
1013 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC)
1014 {
1015 /* Can't indirect off non address regs */
1016 opP->error = "Invalid indirect register";
1017 return FAIL;
1018 }
1019 if (i != FAIL)
1020 {
1021 opP->reg = i;
1022 if (*str == ')')
1023 {
1024 /* "(d,An)" Register Indirect w Displacement */
1025 opP->mode = AOFF;
1026 return OK;
1027 }
1028 if (*str == ',')
1029 {
1030 str++;
1031 i = try_moto_index (&str, opP);
1032 if (i == FAIL)
1033 return FAIL;
1034 /* "(d,An,Rn)" Register Indirect with Index */
1035 opP->mode = AINDX;
1036 return OK;
1037 }
1038 else
1039 {
1040 opP->error = "Bad indirect syntax";
1041 return FAIL;
1042 }
1043 }
1044 else
1045 {
1046 opP->error = "Invalid register";
1047 return FAIL;
1048 }
1049 }
1050 else
1051 {
1052 opP->mode = ABSL;
1053 opP->con1 = add_exp (str - 1, strend);
1054 return OK;
1055 }
1056 }
1057 }
6d27d3a2 1058
355afbcd
KR		 1059 if (*str == '-')
1060 {
1061 if (str[1] == '(')
1062 {
1063 str = str + 2;
1064 i = m68k_reg_parse (&str);
1065 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL)
1066 {
1067 /* Can't indirect off non address regs */
1068 opP->error = "Invalid indirect register";
1069 return FAIL;
1070 }
1071 if (i != FAIL)
1072 {
1073 opP->reg = i;
1074 if (*str == ')')
1075 {
1076 str++;
1077 if (*str == '\0')
1078 {
1079 /* "-(An)" Register Indirect with Predecrement */
1080 opP->mode = ADEC;
1081 return OK;
1082 }
1083 opP->error = "Junk after indirect";
1084 return FAIL;
1085 }
1086 opP->error = "Bad indirect syntax";
1087 return FAIL;
1088 }
1089 opP->mode = ABSL;
1090 opP->con1 = add_exp (str - 2, strend);
1091 return OK;
1092 }
1093 /* if '-' but not "-(', do nothing */
1094 }
1095
1096 /* whether *str=='-' or not */
1097 {
1098 /* "EXP2" or "EXP2(REG..." */
1099 char *stmp;
1100 char *index ();
bcb8dff8 1101 if ((stmp = index (str, '(')) != NULL)
355afbcd
KR		 1102 {
1103 char *ostr = str;
3ad9ec6a 1104
355afbcd
KR		 1105 opP->con1 = add_exp (str, stmp - 1);
1106 str = stmp + 1;
1107 i = m68k_reg_parse (&str);
1108 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC
1109 && i != ZPC && i != FAIL)
1110 {
1111 /* Can't indirect off non address regs */
1112 opP->error = "Invalid indirect register";
1113 return FAIL;
1114 }
1115 if (i != FAIL)
1116 {
1117 opP->reg = i;
1118 if (*str == ')')
3ad9ec6a 1119 {
355afbcd
KR		 1120 /* "d(An)" Register Indirect w Displacement */
1121 opP->mode = AOFF;
1122 return OK;
3ad9ec6a 1123 }
355afbcd
KR		 1124 if (*str == ',')
1125 {
1126 str++;
1127 i = try_moto_index (&str, opP);
1128 if (i == FAIL)
1129 return FAIL;
1130 /* "d(An,Rn)" Register Indirect with Index */
1131 opP->mode = AINDX;
1132 return OK;
1133 }
1134 else
1135 {
1136 opP->error = "Bad indirect syntax";
1137 return FAIL;
1138 }
1139 }
1140 else
1141 {
1142 opP->mode = ABSL;
1143 opP->con1 = add_exp (ostr, strend);
f8701a3f 1144 return OK;
3ad9ec6a 1145 }
355afbcd
KR		 1146 }
1147 else
1148 {
1149 /* "EXP2" Absolute */
1150 opP->mode = ABSL;
1151 opP->isiz = 0;
1152 if (strend[-1] == '.' || strend[-1] == ':')
1153 {
1154 /* mode ==foo.[wl] */
1155 switch (*strend)
1156 {
1157 case 'w':
1158 case 'W':
1159 opP->isiz = 2;
355afbcd
KR		 1160 break;
1161 case 'l':
1162 case 'L':
1163 opP->isiz = 3;
355afbcd
KR		 1164 break;
1165 }
1166 }
1167 opP->con1 = add_exp (str, strend);
1168 return OK;
1169 }
1170 }
1171 /*NOTREACHED*/
1172#else /* defined (MIT_SYNTAX_ONLY) */
1173 opP->mode = ABSL;
1174 opP->con1 = add_exp (str, strend);
1175 return OK;
1176#endif /* defined (MIT_SYNTAX_ONLY) */
1177 }
3ad9ec6a 1178
355afbcd 1179 opP->reg = i;
6d27d3a2 1180
355afbcd
KR		 1181 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1182 if ((i < ADDR + 0 || i > ADDR + 7) && i != PC && i != ZPC && i != FAIL
1183 && (str[1] != '\0' || i < DATA + 0 || i > DATA + 7))
1184 {
1185 opP->error = "Invalid indirect register";
1186 return FAIL;
1187 }
1188 know (*str == '@');
6d27d3a2 1189
355afbcd
KR		 1190 str++;
1191 switch (*str)
1192 {
1193 case '\0':
1194 if (i < DATA + 0 || i > DATA + 7)
1195 opP->mode = AINDR;
1196 else
1197 opP->mode = DINDR;
1198 return OK;
1199 case '-':
1200 opP->mode = ADEC;
1201 return OK;
1202 case '+':
1203 opP->mode = AINC;
1204 return OK;
1205 case '(':
1206 str++;
1207 break;
1208 default:
1209 opP->error = "Junk after indirect";
1210 return FAIL;
1211 }
1212 /* Some kind of indexing involved. Lets find out how bad it is */
1213 i = try_index (&str, opP);
1214 /* Didn't start with an index reg, maybe its offset or offset,reg */
1215 if (i == FAIL)
1216 {
1217 char *beg_str;
1218
1219 beg_str = str;
1220 for (i = 1; i;)
1221 {
1222 switch (*str++)
1223 {
1224 case '\0':
1225 opP->error = "Missing )";
1226 return FAIL;
1227 case ',':
1228 i = 0;
1229 break;
1230 case '(':
1231 i++;
1232 break;
1233 case ')':
1234 --i;
1235 break;
1236 }
fecd2382 1237 }
49864cfa
KR		 1238#if 0
1239 if (str[-3]==':')
1240 {
1241 int siz;
1242
1243 switch (str[-2])
1244 {
1245 case 'b':
1246 case 'B':
1247 siz=1;
1248 break;
1249 case 'w':
1250 case 'W':
1251 siz=2;
1252 break;
1253 case 'l':
1254 case 'L':
1255 siz=3;
1256 break;
1257 default:
1258 opP->error="Specified size isn't :w or :l";
1259 return FAIL;
1260 }
1261 opP->con1=add_exp(beg_str,str-4);
1262 opP->con1->e_siz=siz;
1263 }
1264 else
1265#endif
1266 opP->con1 = add_exp (beg_str, str - 2);
355afbcd
KR		 1267 /* Should be offset,reg */
1268 if (str[-1] == ',')
1269 {
1270 i = try_index (&str, opP);
1271 if (i == FAIL)
1272 {
1273 opP->error = "Malformed index reg";
1274 return FAIL;
1275 }
f8701a3f 1276 }
355afbcd
KR		 1277 }
1278 /* We've now got offset) offset,reg) or reg) */
1279
1280 if (*str == '\0')
1281 {
1282 /* Th-the-thats all folks */
1283 if (opP->reg == FAIL)
1284 opP->mode = AINDX; /* Other form of indirect */
1285 else if (opP->ireg == FAIL)
1286 opP->mode = AOFF;
1287 else
1288 opP->mode = AINDX;
1289 return (OK);
1290 }
1291 /* Next thing had better be another @ */
1292 if (*str == '@')
1293 {
1294 if (str[1] == '(')
1295 {
1296 needp = 1;
1297 str += 2;
f8701a3f 1298 }
355afbcd
KR		 1299 else
1300 {
1301 needp = 0;
1302 str++;
fecd2382 1303 }
355afbcd 1304 }
6d27d3a2 1305
355afbcd
KR		 1306 if ((current_architecture & m68020up) == 0)
1307 {
1308 return (FAIL);
1309 } /* if target is not a '20 or better */
6d27d3a2
KR		 1310
1311
355afbcd
KR		 1312 if (opP->ireg != FAIL)
1313 {
1314 opP->mode = APRDX;
6d27d3a2 1315
355afbcd
KR		 1316 i = try_index (&str, opP);
1317 if (i != FAIL)
1318 {
1319 opP->error = "Two index registers! not allowed!";
1320 return (FAIL);
865a2edf 1321 }
355afbcd
KR		 1322 }
1323 else
1324 {
1325 i = try_index (&str, opP);
1326 }
6d27d3a2 1327
355afbcd
KR		 1328 if (i == FAIL)
1329 {
1330 char *beg_str;
6d27d3a2 1331
355afbcd 1332 beg_str = str;
6d27d3a2 1333
355afbcd
KR		 1334 for (i = 1; i;)
1335 {
1336 switch (*str++)
1337 {
1338 case '\0':
1339 if (needp)
1340 opP->error = "Missing )";
1341 return (FAIL);
1342 break;
1343 case ',':
1344 i = 0;
1345 break;
1346 case '(':
1347 i++;
1348 break;
1349 case ')':
1350 --i;
1351 break;
1352 }
1353 }
6d27d3a2 1354
355afbcd 1355 opP->con2 = add_exp (beg_str, str - 2);
6d27d3a2 1356
355afbcd
KR		 1357 if (str[-1] == ',')
1358 {
1359 if (opP->ireg != FAIL)
1360 {
1361 opP->error = "Can't have two index regs";
1362 return (FAIL);
1363 }
6d27d3a2 1364
355afbcd 1365 i = try_index (&str, opP);
6d27d3a2 1366
355afbcd
KR		 1367 if (i == FAIL)
1368 {
1369 opP->error = "malformed index reg";
1370 return (FAIL);
1371 }
6d27d3a2 1372
355afbcd 1373 opP->mode = APODX;
f8701a3f 1374 }
355afbcd
KR		 1375 else if (opP->ireg != FAIL)
1376 {
1377 opP->mode = APRDX;
1378 }
1379 else
1380 {
1381 opP->mode = AMIND;
f8701a3f 1382 }
355afbcd
KR		 1383 }
1384 else
1385 {
1386 opP->mode = APODX;
1387 }
1388
1389 if (*str != '\0')
1390 {
1391 opP->error = "Junk after indirect";
1392 return FAIL;
1393 }
1394 return (OK);
1395} /* m68k_ip_op() */
fecd2382 1396
7c15cbe8 1397
49864cfa 1398#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
3ad9ec6a 1399
355afbcd
KR		 1400short
1401tc_coff_fix2rtype (fixP)
1402 fixS *fixP;
fecd2382 1403{
355afbcd
KR		 1404 return (fixP->fx_pcrel ?
1405 (fixP->fx_size == 1 ? R_PCRBYTE :
1406 fixP->fx_size == 2 ? R_PCRWORD :
1407 R_PCRLONG) :
1408 (fixP->fx_size == 1 ? R_RELBYTE :
1409 fixP->fx_size == 2 ? R_RELWORD :
1410 R_RELLONG));
6d27d3a2 1411
3ad9ec6a
ILT		 1412
1413}
1414
1415#endif
fecd2382 1416
49864cfa
KR		 1417#ifdef BFD_ASSEMBLER
1418
1419arelent *
1420tc_gen_reloc (section, fixp)
1421 asection *section;
1422 fixS *fixp;
1423{
1424 arelent *reloc;
1425 bfd_reloc_code_real_type code;
1426
1427#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1428 switch (F (fixp->fx_size, fixp->fx_pcrel))
1429 {
1430#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1431 MAP (1, 0, BFD_RELOC_8);
1432 MAP (2, 0, BFD_RELOC_16);
1433 MAP (4, 0, BFD_RELOC_32);
1434 MAP (1, 1, BFD_RELOC_8_PCREL);
1435 MAP (2, 1, BFD_RELOC_16_PCREL);
1436 MAP (4, 1, BFD_RELOC_32_PCREL);
1437 default:
1438 abort ();
1439 }
1440
1441 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1442 assert (reloc != 0);
1443 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1444 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1445 if (fixp->fx_pcrel)
1446 reloc->addend = fixp->fx_addnumber;
1447 else
1448 reloc->addend = 0;
1449
1450 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1451 assert (reloc->howto != 0);
1452
1453 return reloc;
1454}
1455
1456#endif /* BFD_ASSEMBLER */
1457
355afbcd
KR		 1458#ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1459main ()
fecd2382 1460{
355afbcd
KR		 1461 char buf[128];
1462 struct m68k_op thark;
6d27d3a2 1463
355afbcd
KR		 1464 for (;;)
1465 {
1466 if (!gets (buf))
1467 break;
1468 memset (&thark, '\0', sizeof (thark));
1469 if (!m68k_ip_op (buf, &thark))
1470 printf ("FAIL:");
1471 if (thark.error)
1472 printf ("op1 error %s in %s\n", thark.error, buf);
1473 printf ("mode %d, reg %d, ", thark.mode, thark.reg);
1474 if (thark.b_const)
1475 printf ("Constant: '%.*s',", 1 + thark.e_const - thark.b_const, thark.b_const);
1476 printf ("ireg %d, isiz %d, imul %d ", thark.ireg, thark.isiz, thark.imul);
1477 if (thark.b_iadd)
1478 printf ("Iadd: '%.*s'", 1 + thark.e_iadd - thark.b_iadd, thark.b_iadd);
1479 printf ("\n");
1480 }
1481 exit (0);
fecd2382
RP		 1482}
1483
1484#endif
1485
1486
49864cfa
KR		 1487/* Handle of the OPCODE hash table. NULL means any use before
1488 m68k_ip_begin() will crash. */
1489static struct hash_control *op_hash;
fecd2382 1490\f
355afbcd 1491
fecd2382 1492/*
7c15cbe8 1493 * m 6 8 k _ i p ( )
fecd2382
RP		 1494 *
1495 * This converts a string into a 68k instruction.
1496 * The string must be a bare single instruction in sun format
1497 * with RMS-style 68020 indirects
1498 * (example: )
1499 *
1500 * It provides some error messages: at most one fatal error message (which
1501 * stops the scan) and at most one warning message for each operand.
1502 * The 68k instruction is returned in exploded form, since we have no
1503 * knowledge of how you parse (or evaluate) your expressions.
1504 * We do however strip off and decode addressing modes and operation
1505 * mnemonic.
1506 *
1507 * This function's value is a string. If it is not "" then an internal
1508 * logic error was found: read this code to assign meaning to the string.
1509 * No argument string should generate such an error string:
1510 * it means a bug in our code, not in the user's text.
1511 *
7c15cbe8 1512 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
fecd2382
RP		 1513 * this function.
1514 */
1515
1516/* JF this function no longer returns a useful value. Sorry */
355afbcd
KR		 1517void
1518m68k_ip (instring)
6d27d3a2 1519 char *instring;
fecd2382 1520{
6d27d3a2
KR		 1521 register char *p;
1522 register struct m68k_op *opP;
1523 register struct m68k_incant *opcode;
1524 register char *s;
1525 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 1526 char *pdot, *pdotmove;
6d27d3a2 1527 int siz1, siz2;
355afbcd
KR		 1528 char c;
1529 int losing;
1530 int opsfound;
1531 char *crack_operand ();
6d27d3a2
KR		 1532 LITTLENUM_TYPE words[6];
1533 LITTLENUM_TYPE *wordp;
8be74775 1534 unsigned long ok_arch = 0;
6d27d3a2
KR		 1535
1536 if (*instring == ' ')
1537 instring++; /* skip leading whitespace */
1538
1539 /* Scan up to end of operation-code, which MUST end in end-of-string
1540 or exactly 1 space. */
3ad9ec6a 1541 pdot = 0;
355afbcd
KR		 1542 for (p = instring; *p != '\0'; p++)
1543 {
1544 if (*p == ' ')
1545 break;
1546 if (*p == '.')
1547 pdot = p;
1548 }
6d27d3a2 1549
355afbcd
KR		 1550 if (p == instring)
1551 {
1552 the_ins.error = "No operator";
bcb8dff8 1553 the_ins.opcode[0] = 0;
355afbcd
KR		 1554 /* the_ins.numo=1; */
1555 return;
1556 }
6d27d3a2
KR		 1557
1558 /* p now points to the end of the opcode name, probably whitespace.
1559 make sure the name is null terminated by clobbering the whitespace,
3ad9ec6a
ILT		 1560 look it up in the hash table, then fix it back.
1561 Remove a dot, first, since the opcode tables have none. */
355afbcd
KR		 1562 if (pdot != NULL)
1563 {
1564 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1565 *pdotmove = pdotmove[1];
1566 p--;
1567 }
3ad9ec6a 1568
6d27d3a2
KR		 1569 c = *p;
1570 *p = '\0';
355afbcd 1571 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
6d27d3a2
KR		 1572 *p = c;
1573
355afbcd
KR		 1574 if (pdot != NULL)
1575 {
1576 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1577 *pdotmove = pdotmove[-1];
1578 *pdot = '.';
1579 ++p;
1580 }
3ad9ec6a 1581
355afbcd
KR		 1582 if (opcode == NULL)
1583 {
1584 the_ins.error = "Unknown operator";
bcb8dff8 1585 the_ins.opcode[0] = 0;
355afbcd
KR		 1586 /* the_ins.numo=1; */
1587 return;
1588 }
6d27d3a2
KR		 1589
1590 /* found a legitimate opcode, start matching operands */
355afbcd
KR		 1591 while (*p == ' ')
1592 ++p;
6d27d3a2 1593
3ad9ec6a 1594
355afbcd
KR		 1595 if (opcode->m_operands == 0)
1596 {
1597 char *old = input_line_pointer;
1598 *old = '\n';
1599 input_line_pointer = p;
1600 /* Ahh - it's a motorola style psuedo op */
1601 mote_pseudo_table[opcode->m_opnum].poc_handler
1602 (mote_pseudo_table[opcode->m_opnum].poc_val);
1603 input_line_pointer = old;
1604 *old = 0;
3ad9ec6a 1605
355afbcd
KR		 1606 return;
1607 }
3ad9ec6a 1608
355afbcd
KR		 1609 for (opP = &the_ins.operands[0]; *p; opP++)
1610 {
6d27d3a2 1611
355afbcd 1612 p = crack_operand (p, opP);
6d27d3a2 1613
355afbcd
KR		 1614 if (opP->error)
1615 {
1616 the_ins.error = opP->error;
1617 return;
1618 }
6d27d3a2 1619 }
6d27d3a2
KR		 1620
1621 opsfound = opP - &the_ins.operands[0];
1622
1623 /* This ugly hack is to support the floating pt opcodes in their standard form */
1624 /* Essentially, we fake a first enty of type COP#1 */
355afbcd
KR		 1625 if (opcode->m_operands[0] == 'I')
1626 {
1627 int n;
6d27d3a2 1628
355afbcd
KR		 1629 for (n = opsfound; n > 0; --n)
1630 the_ins.operands[n] = the_ins.operands[n - 1];
6d27d3a2 1631
355afbcd
KR		 1632 memset ((char *) (&the_ins.operands[0]), '\0', sizeof (the_ins.operands[0]));
1633 the_ins.operands[0].mode = MSCR;
1634 the_ins.operands[0].reg = COPNUM; /* COP #1 */
1635 opsfound++;
1636 }
6d27d3a2
KR		 1637
1638 /* We've got the operands. Find an opcode that'll accept them */
355afbcd
KR		 1639 for (losing = 0;;)
1640 {
49864cfa
KR		 1641 /* If we didn't get the right number of ops, or we have no
1642 common model with this pattern then reject this pattern. */
6d27d3a2 1643
355afbcd
KR		 1644 if (opsfound != opcode->m_opnum
1645 || ((opcode->m_arch & current_architecture) == 0))
1646 {
1647 ++losing;
1648 ok_arch |= opcode->m_arch;
1649 }
1650 else
1651 {
1652 for (s = opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++)
1653 {
1654 /* Warning: this switch is huge! */
49864cfa
KR		 1655 /* I've tried to organize the cases into this order:
1656 non-alpha first, then alpha by letter. Lower-case
1657 goes directly before uppercase counterpart. */
1658 /* Code with multiple case ...: gets sorted by the lowest
1659 case ... it belongs to. I hope this makes sense. */
355afbcd
KR		 1660 switch (*s)
1661 {
1662 case '!':
1663 if (opP->mode == MSCR || opP->mode == IMMED
1664 || opP->mode == DREG || opP->mode == AREG
1665 || opP->mode == AINC || opP->mode == ADEC
1666 || opP->mode == REGLST)
1667 losing++;
1668 break;
1669
1670 case '`':
1671 switch (opP->mode)
1672 {
1673 case MSCR:
1674 case IMMED:
1675 case DREG:
1676 case AREG:
1677 case AINC:
1678 case REGLST:
1679 case AINDR:
1680 losing++;
bcb8dff8
KR		 1681 break;
1682 default:
1683 break;
355afbcd
KR		 1684 }
1685 break;
8be74775 1686
355afbcd
KR		 1687 case '#':
1688 if (opP->mode != IMMED)
1689 losing++;
1690 else
1691 {
1692 long t;
1693
1694 t = get_num (opP->con1, 80);
1695 if (s[1] == 'b' && !isbyte (t))
1696 losing++;
1697 else if (s[1] == 'w' && !isword (t))
1698 losing++;
1699 }
1700 break;
1701
1702 case '^':
1703 case 'T':
1704 if (opP->mode != IMMED)
1705 losing++;
1706 break;
1707
1708 case '$':
1709 if (opP->mode == MSCR || opP->mode == AREG ||
1710 opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1711 losing++;
1712 break;
1713
1714 case '%':
1715 if (opP->mode == MSCR || opP->reg == PC ||
1716 opP->reg == ZPC || opP->mode == REGLST)
1717 losing++;
1718 break;
1719
1720
1721 case '&':
1722 if (opP->mode == MSCR || opP->mode == DREG ||
1723 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC ||
1724 opP->mode == AINC || opP->mode == ADEC || opP->mode == REGLST)
1725 losing++;
1726 break;
1727
1728 case '*':
1729 if (opP->mode == MSCR || opP->mode == REGLST)
1730 losing++;
1731 break;
1732
1733 case '+':
1734 if (opP->mode != AINC)
1735 losing++;
1736 break;
1737
1738 case '-':
1739 if (opP->mode != ADEC)
1740 losing++;
1741 break;
1742
1743 case '/':
1744 if (opP->mode == MSCR || opP->mode == AREG ||
1745 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->mode == REGLST)
1746 losing++;
1747 break;
1748
1749 case ';':
1750 if (opP->mode == MSCR || opP->mode == AREG || opP->mode == REGLST)
1751 losing++;
1752 break;
1753
1754 case '?':
1755 if (opP->mode == MSCR || opP->mode == AREG ||
1756 opP->mode == AINC || opP->mode == ADEC || opP->mode == IMMED || opP->reg == PC ||
1757 opP->reg == ZPC || opP->mode == REGLST)
1758 losing++;
1759 break;
1760
1761 case '@':
1762 if (opP->mode == MSCR || opP->mode == AREG ||
1763 opP->mode == IMMED || opP->mode == REGLST)
1764 losing++;
1765 break;
1766
1767 case '~': /* For now! (JF FOO is this right?) */
1768 if (opP->mode == MSCR || opP->mode == DREG ||
1769 opP->mode == AREG || opP->mode == IMMED || opP->reg == PC || opP->reg == ZPC || opP->mode == REGLST)
1770 losing++;
1771 break;
1772
1773 case '3':
1774 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1775 losing++;
1776 break;
1777
1778 case 'A':
1779 if (opP->mode != AREG)
1780 losing++;
1781 break;
1782 case 'a':
1783 if (opP->mode != AINDR)
1784 {
1785 ++losing;
1786 } /* if not address register indirect */
1787 break;
1788 case 'B': /* FOO */
1789 if (opP->mode != ABSL || (flagseen['S'] && instring[0] == 'j'
1790 && instring[1] == 'b'
1791 && instring[2] == 's'
1792 && instring[3] == 'r'))
1793 losing++;
1794 break;
1795
1796 case 'C':
1797 if (opP->mode != MSCR || opP->reg != CCR)
1798 losing++;
1799 break;
1800
1801 case 'd': /* FOO This mode is a KLUDGE!! */
1802 if (opP->mode != AOFF && (opP->mode != ABSL ||
1803 opP->con1->e_beg[0] != '(' || opP->con1->e_end[0] != ')'))
1804 losing++;
1805 break;
1806
1807 case 'D':
1808 if (opP->mode != DREG)
1809 losing++;
1810 break;
1811
1812 case 'F':
1813 if (opP->mode != MSCR || opP->reg < (FPREG + 0) || opP->reg > (FPREG + 7))
1814 losing++;
1815 break;
1816
1817 case 'I':
1818 if (opP->mode != MSCR || opP->reg < COPNUM ||
1819 opP->reg >= COPNUM + 7)
1820 losing++;
1821 break;
1822
1823 case 'J':
1824 if (opP->mode != MSCR
1825 || opP->reg < USP
1826 || opP->reg > URP
1827 || cpu_of_arch (current_architecture) < m68010 /* before 68010 had none */
1828 || (cpu_of_arch (current_architecture) < m68020
1829 && opP->reg != SFC
1830 && opP->reg != DFC
1831 && opP->reg != USP
1832 && opP->reg != VBR) /* 68010's had only these */
1833 || (cpu_of_arch (current_architecture) < m68040
1834 && opP->reg != SFC
1835 && opP->reg != DFC
1836 && opP->reg != USP
1837 && opP->reg != VBR
1838 && opP->reg != CACR
1839 && opP->reg != CAAR
1840 && opP->reg != MSP
1841 && opP->reg != ISP) /* 680[23]0's have only these */
1842 || (cpu_of_arch (current_architecture) == m68040 /* 68040 has all but this */
1843 && opP->reg == CAAR))
1844 {
1845 losing++;
1846 } /* doesn't cut it */
1847 break;
1848
1849 case 'k':
1850 if (opP->mode != IMMED)
1851 losing++;
1852 break;
8be74775 1853
355afbcd
KR		 1854 case 'l':
1855 case 'L':
1856 if (opP->mode == DREG || opP->mode == AREG || opP->mode == FPREG)
1857 {
1858 if (s[1] == '8')
1859 losing++;
1860 else
1861 {
1862 opP->mode = REGLST;
1863 opP->reg = 1 << (opP->reg - DATA);
1864 }
1865 }
1866 else if (opP->mode != REGLST)
1867 {
1868 losing++;
1869 }
1870 else if (s[1] == '8' && opP->reg & 0x0FFffFF)
1871 losing++;
1872 else if (s[1] == '3' && opP->reg & 0x7000000)
1873 losing++;
1874 break;
1875
1876 case 'M':
1877 if (opP->mode != IMMED)
1878 losing++;
1879 else
1880 {
1881 long t;
6d27d3a2 1882
49864cfa
KR		 1883 t = get_num (opP->con1, 0);
1884 if (!issbyte (t)
bcb8dff8 1885 || isvar (opP->con1))
355afbcd
KR		 1886 losing++;
1887 }
1888 break;
8be74775 1889
355afbcd
KR		 1890 case 'O':
1891 if (opP->mode != DREG && opP->mode != IMMED)
1892 losing++;
1893 break;
6d27d3a2 1894
355afbcd
KR		 1895 case 'Q':
1896 if (opP->mode != IMMED)
1897 losing++;
1898 else
1899 {
1900 long t;
6d27d3a2 1901
355afbcd
KR		 1902 t = get_num (opP->con1, 80);
1903 if (t < 1 || t > 8 || isvar (opP->con1))
1904 losing++;
1905 }
1906 break;
8be74775 1907
355afbcd
KR		 1908 case 'R':
1909 if (opP->mode != DREG && opP->mode != AREG)
1910 losing++;
1911 break;
8be74775 1912
355afbcd
KR		 1913 case 'r':
1914 if (opP->mode != AINDR && opP->mode != DINDR)
1915 losing++;
1916 break;
c50140c8 1917
355afbcd
KR		 1918 case 's':
1919 if (opP->mode != MSCR || !(opP->reg == FPI || opP->reg == FPS || opP->reg == FPC))
1920 losing++;
1921 break;
8be74775 1922
355afbcd
KR		 1923 case 'S':
1924 if (opP->mode != MSCR || opP->reg != SR)
1925 losing++;
1926 break;
8be74775 1927
355afbcd
KR		 1928 case 't':
1929 if (opP->mode != IMMED)
1930 losing++;
1931 else
1932 {
1933 long t = get_num (opP->con1, 80);
1934 if (t < 0 || t > 7 || isvar (opP->con1))
1935 losing++;
1936 }
1937 break;
4134a793 1938
355afbcd
KR		 1939 case 'U':
1940 if (opP->mode != MSCR || opP->reg != USP)
1941 losing++;
1942 break;
8be74775 1943
355afbcd 1944 /* JF these are out of order. We could put them
1404ef23
KR		 1945 in order if we were willing to put up with
1946 bunches of #ifdef m68851s in the code.
4134a793 1947
1404ef23
KR		 1948 Don't forget that you need these operands
1949 to use 68030 MMU instructions. */
f8701a3f 1950#ifndef NO_68851
355afbcd
KR		 1951 /* Memory addressing mode used by pflushr */
1952 case '|':
1953 if (opP->mode == MSCR || opP->mode == DREG ||
1954 opP->mode == AREG || opP->mode == REGLST)
1955 losing++;
1956 break;
1957
1958 case 'f':
1959 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1960 losing++;
1961 break;
1962
1963 case 'P':
1964 if (opP->mode != MSCR
1965 || (opP->reg != TC && opP->reg != CAL
1966 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
1967 losing++;
1968 break;
1969
1970 case 'V':
1971 if (opP->reg != VAL)
1972 losing++;
1973 break;
8be74775 1974
355afbcd
KR		 1975 case 'W':
1976 if (opP->mode != MSCR
1977 || (opP->reg != DRP && opP->reg != SRP
1978 && opP->reg != CRP))
1979 losing++;
1980 break;
1981
1982 case 'X':
1983 if (opP->mode != MSCR ||
1984 (!(opP->reg >= BAD && opP->reg <= BAD + 7) &&
1985 !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1986 losing++;
1987 break;
1988
1989 case 'Y':
1990 if (opP->reg != PSR)
1991 losing++;
1992 break;
1993
1994 case 'Z':
1995 if (opP->reg != PCSR)
1996 losing++;
1997 break;
f8701a3f 1998#endif
355afbcd
KR		 1999 case 'c':
2000 if (opP->reg != NC
2001 && opP->reg != IC
2002 && opP->reg != DC
2003 && opP->reg != BC)
2004 {
2005 losing++;
2006 } /* not a cache specifier. */
2007 break;
2008
2009 case '_':
2010 if (opP->mode != ABSL)
2011 {
2012 ++losing;
2013 } /* not absolute */
2014 break;
8be74775 2015
355afbcd
KR		 2016 default:
2017 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2018 *s, __LINE__, __FILE__);
2019 } /* switch on type of operand */
6d27d3a2 2020
355afbcd
KR		 2021 if (losing)
2022 break;
2023 } /* for each operand */
2024 } /* if immediately wrong */
6d27d3a2 2025
355afbcd
KR		 2026 if (!losing)
2027 {
8be74775 2028 break;
355afbcd 2029 } /* got it. */
6d27d3a2 2030
355afbcd 2031 opcode = opcode->m_next;
6d27d3a2 2032
355afbcd 2033 if (!opcode)
8be74775 2034 {
355afbcd
KR		 2035 if (ok_arch
2036 && !(ok_arch & current_architecture))
8be74775 2037 {
355afbcd
KR		 2038 char buf[200], *cp;
2039 int len;
2040 strcpy (buf, "invalid instruction for this architecture; needs ");
2041 cp = buf + strlen (buf);
2042 switch (ok_arch)
2043 {
2044 case mfloat:
2045 strcpy (cp, "fpu (68040 or 68881/68882)");
2046 break;
2047 case mmmu:
2048 strcpy (cp, "mmu (68030 or 68851)");
2049 break;
2050 case m68020up:
2051 strcpy (cp, "68020 or higher");
2052 break;
2053 case m68000up:
2054 strcpy (cp, "68000 or higher");
2055 break;
2056 case m68010up:
2057 strcpy (cp, "68010 or higher");
2058 break;
2059 default:
8be74775 2060 {
355afbcd 2061 int got_one = 0, idx;
bcb8dff8 2062 static const struct
355afbcd
KR		 2063 {
2064 int arch;
bcb8dff8 2065 const char *name;
355afbcd
KR		 2066 }
2067 archs[] =
2068 {
bcb8dff8
KR		 2069 { m68000, "68000" },
2070 { m68010, "68010" },
2071 { m68020, "68020" },
2072 { m68030, "68030" },
2073 { m68040, "68040" },
2074 { cpu32, "cpu32" },
2075 { m68881, "68881" },
2076 { m68851, "68851" }
355afbcd
KR		 2077 };
2078 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]); idx++)
8be74775 2079 {
355afbcd 2080 if (archs[idx].arch & ok_arch)
8be74775 2081 {
355afbcd
KR		 2082 if (got_one)
2083 {
2084 strcpy (cp, " or ");
2085 cp += strlen (cp);
2086 }
2087 got_one = 1;
2088 strcpy (cp, archs[idx].name);
8be74775
KR		 2089 cp += strlen (cp);
2090 }
8be74775
KR		 2091 }
2092 }
355afbcd
KR		 2093 }
2094 len = cp - buf + 1;
2095 cp = malloc (len);
2096 strcpy (cp, buf);
2097 the_ins.error = cp;
8be74775 2098 }
355afbcd
KR		 2099 else
2100 the_ins.error = "operands mismatch";
2101 return;
2102 } /* Fell off the end */
6d27d3a2 2103
355afbcd
KR		 2104 losing = 0;
2105 }
6d27d3a2
KR		 2106
2107 /* now assemble it */
2108
355afbcd
KR		 2109 the_ins.args = opcode->m_operands;
2110 the_ins.numargs = opcode->m_opnum;
2111 the_ins.numo = opcode->m_codenum;
2112 the_ins.opcode[0] = getone (opcode);
2113 the_ins.opcode[1] = gettwo (opcode);
6d27d3a2 2114
355afbcd
KR		 2115 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2116 {
2117 /* This switch is a doozy.
6d27d3a2 2118 Watch the first step; its a big one! */
355afbcd
KR		 2119 switch (s[0])
2120 {
6d27d3a2 2121
355afbcd
KR		 2122 case '*':
2123 case '~':
2124 case '%':
2125 case ';':
2126 case '@':
2127 case '!':
2128 case '&':
2129 case '$':
2130 case '?':
2131 case '/':
2132 case '`':
2133#ifndef NO_68851
2134 case '|':
2135#endif
2136 switch (opP->mode)
2137 {
2138 case IMMED:
2139 tmpreg = 0x3c; /* 7.4 */
2140 if (strchr ("bwl", s[1]))
2141 nextword = get_num (opP->con1, 80);
2142 else
49864cfa 2143 nextword = get_num (opP->con1, 0);
355afbcd
KR		 2144 if (isvar (opP->con1))
2145 add_fix (s[1], opP->con1, 0);
2146 switch (s[1])
2147 {
2148 case 'b':
2149 if (!isbyte (nextword))
2150 opP->error = "operand out of range";
2151 addword (nextword);
2152 baseo = 0;
2153 break;
2154 case 'w':
2155 if (!isword (nextword))
2156 opP->error = "operand out of range";
2157 addword (nextword);
2158 baseo = 0;
2159 break;
2160 case 'l':
2161 addword (nextword >> 16);
2162 addword (nextword);
2163 baseo = 0;
2164 break;
2165
2166 case 'f':
2167 baseo = 2;
2168 outro = 8;
2169 break;
2170 case 'F':
2171 baseo = 4;
2172 outro = 11;
2173 break;
2174 case 'x':
2175 baseo = 6;
2176 outro = 15;
2177 break;
2178 case 'p':
2179 baseo = 6;
2180 outro = -1;
2181 break;
2182 default:
bcb8dff8 2183 as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"",
355afbcd
KR		 2184 *s, s[1], __LINE__, __FILE__);
2185 }
2186 if (!baseo)
2187 break;
6d27d3a2 2188
355afbcd 2189 /* We gotta put out some float */
bcb8dff8 2190 if (op (opP->con1) != O_big)
355afbcd 2191 {
bcb8dff8
KR		 2192 valueT val;
2193 int gencnt;
2194
2195 /* Can other cases happen here? */
2196 if (op (opP->con1) != O_constant)
2197 abort ();
2198
2199 val = (valueT) offs (opP->con1);
2200 gencnt = 0;
2201 do
2202 {
2203 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2204 val >>= LITTLENUM_NUMBER_OF_BITS;
2205 ++gencnt;
2206 }
2207 while (val != 0);
2208 offs (opP->con1) = gencnt;
355afbcd 2209 }
355afbcd
KR		 2210 if (offs (opP->con1) > 0)
2211 {
2212 if (offs (opP->con1) > baseo)
2213 {
2214 as_warn ("Bignum too big for %c format; truncated", s[1]);
2215 offs (opP->con1) = baseo;
2216 }
2217 baseo -= offs (opP->con1);
355afbcd
KR		 2218 while (baseo--)
2219 addword (0);
bcb8dff8
KR		 2220 for (wordp = generic_bignum + offs (opP->con1) - 1; offs (opP->con1)--; --wordp)
2221 addword (*wordp);
355afbcd
KR		 2222 break;
2223 }
2224 gen_to_words (words, baseo, (long) outro);
2225 for (wordp = words; baseo--; wordp++)
2226 addword (*wordp);
2227 break;
2228 case DREG:
2229 tmpreg = opP->reg - DATA; /* 0.dreg */
2230 break;
2231 case AREG:
2232 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2233 break;
2234 case AINDR:
2235 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2236 break;
2237 case ADEC:
2238 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2239 break;
2240 case AINC:
2241 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2242 break;
2243 case AOFF:
6d27d3a2 2244
355afbcd
KR		 2245 nextword = get_num (opP->con1, 80);
2246 /* Force into index mode. Hope this works */
6d27d3a2 2247
1404ef23
KR		 2248 /* We do the first bit for 32-bit displacements, and the
2249 second bit for 16 bit ones. It is possible that we
2250 should make the default be WORD instead of LONG, but
2251 I think that'd break GCC, so we put up with a little
2252 inefficiency for the sake of working output. */
6d27d3a2 2253
355afbcd
KR		 2254 if (!issword (nextword)
2255 || (isvar (opP->con1)
2256 && ((opP->con1->e_siz == 0
2257 && flagseen['l'] == 0)
2258 || opP->con1->e_siz == 3)))
2259 {
6d27d3a2 2260
355afbcd
KR		 2261 if (opP->reg == PC)
2262 tmpreg = 0x3B; /* 7.3 */
2263 else
2264 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2265 if (isvar (opP->con1))
2266 {
2267 if (opP->reg == PC)
2268 {
b80d39a0 2269 addword (0x0170);
dff60b7d 2270 add_fix ('l', opP->con1, 1);
b80d39a0 2271 addword (0), addword (0);
355afbcd
KR		 2272 break;
2273 }
2274 else
2275 {
2276 addword (0x0170);
2277 add_fix ('l', opP->con1, 0);
2278 }
2279 }
2280 else
2281 addword (0x0170);
2282 addword (nextword >> 16);
2283 }
2284 else
2285 {
2286 if (opP->reg == PC)
2287 tmpreg = 0x3A; /* 7.2 */
2288 else
2289 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2290
2291 if (isvar (opP->con1))
2292 {
2293 if (opP->reg == PC)
2294 {
2295 add_fix ('w', opP->con1, 1);
2296 }
2297 else
2298 add_fix ('w', opP->con1, 0);
2299 }
2300 }
2301 addword (nextword);
6d27d3a2 2302 break;
6d27d3a2 2303
355afbcd
KR		 2304 case APODX:
2305 case AMIND:
2306 case APRDX:
2307 know (current_architecture & m68020up);
2308 /* intentional fall-through */
2309 case AINDX:
2310 nextword = 0;
2311 baseo = get_num (opP->con1, 80);
2312 outro = get_num (opP->con2, 80);
49864cfa
KR		 2313 /* Figure out the `addressing mode'.
2314 Also turn on the BASE_DISABLE bit, if needed. */
355afbcd
KR		 2315 if (opP->reg == PC || opP->reg == ZPC)
2316 {
2317 tmpreg = 0x3b;/* 7.3 */
2318 if (opP->reg == ZPC)
2319 nextword |= 0x80;
2320 }
2321 else if (opP->reg == FAIL)
2322 {
2323 nextword |= 0x80;
2324 tmpreg = 0x30;/* 6.garbage */
2325 }
2326 else
2327 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2328
2329 siz1 = (opP->con1) ? opP->con1->e_siz : 0;
2330 siz2 = (opP->con2) ? opP->con2->e_siz : 0;
2331
2332 /* Index register stuff */
2333 if (opP->ireg >= DATA + 0 && opP->ireg <= ADDR + 7)
2334 {
2335 nextword |= (opP->ireg - DATA) << 12;
2336
2337 if (opP->isiz == 0 || opP->isiz == 3)
2338 nextword |= 0x800;
2339 switch (opP->imul)
2340 {
2341 case 1:
2342 break;
2343 case 2:
2344 nextword |= 0x200;
2345 break;
2346 case 4:
2347 nextword |= 0x400;
2348 break;
2349 case 8:
2350 nextword |= 0x600;
2351 break;
2352 default:
2353 as_fatal ("failed sanity check.");
2354 }
2355 /* IF its simple,
49864cfa 2356 GET US OUT OF HERE! */
6d27d3a2 2357
355afbcd 2358 /* Must be INDEX, with an index
49864cfa
KR		 2359 register. Address register
2360 cannot be ZERO-PC, and either
2361 :b was forced, or we know
2362 it will fit */
355afbcd
KR		 2363 if (opP->mode == AINDX
2364 && opP->reg != FAIL
2365 && opP->reg != ZPC
2366 && (siz1 == 1
2367 || (issbyte (baseo)
2368 && !isvar (opP->con1))))
2369 {
2370 nextword += baseo & 0xff;
2371 addword (nextword);
2372 if (isvar (opP->con1))
2373 add_fix ('B', opP->con1, 0);
2374 break;
2375 }
2376 }
2377 else
2378 nextword |= 0x40; /* No index reg */
6d27d3a2 2379
49864cfa 2380 /* It isn't simple. */
355afbcd 2381 nextword |= 0x100;
49864cfa
KR		 2382 /* If the guy specified a width, we assume that it is
2383 wide enough. Maybe it isn't. If so, we lose. */
355afbcd
KR		 2384 switch (siz1)
2385 {
2386 case 0:
2387 if (isvar (opP->con1) || !issword (baseo))
2388 {
2389 siz1 = 3;
2390 nextword |= 0x30;
2391 }
2392 else if (baseo == 0)
2393 nextword |= 0x10;
2394 else
2395 {
2396 nextword |= 0x20;
2397 siz1 = 2;
2398 }
2399 break;
2400 case 1:
2401 as_warn ("Byte dispacement won't work. Defaulting to :w");
2402 case 2:
2403 nextword |= 0x20;
2404 break;
2405 case 3:
2406 nextword |= 0x30;
2407 break;
2408 }
6d27d3a2 2409
355afbcd
KR		 2410 /* Figure out innner displacement stuff */
2411 if (opP->mode != AINDX)
2412 {
2413 switch (siz2)
2414 {
2415 case 0:
2416 if (isvar (opP->con2) || !issword (outro))
2417 {
2418 siz2 = 3;
2419 nextword |= 0x3;
2420 }
2421 else if (outro == 0)
2422 nextword |= 0x1;
2423 else
2424 {
2425 nextword |= 0x2;
2426 siz2 = 2;
2427 }
2428 break;
2429 case 1:
2430 as_warn ("Byte dispacement won't work. Defaulting to :w");
2431 case 2:
2432 nextword |= 0x2;
2433 break;
2434 case 3:
2435 nextword |= 0x3;
2436 break;
2437 }
2438 if (opP->mode == APODX)
2439 nextword |= 0x04;
2440 else if (opP->mode == AMIND)
2441 nextword |= 0x40;
2442 }
2443 addword (nextword);
2444
2445 if (isvar (opP->con1))
2446 {
2447 if (opP->reg == PC || opP->reg == ZPC)
2448 {
355afbcd 2449 opP->con1->e_exp.X_add_number += 6;
9d4dfbf3 2450 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 1);
355afbcd
KR		 2451 }
2452 else
2453 add_fix (siz1 == 3 ? 'l' : 'w', opP->con1, 0);
2454 }
2455 if (siz1 == 3)
2456 addword (baseo >> 16);
2457 if (siz1)
2458 addword (baseo);
2459
2460 if (isvar (opP->con2))
2461 {
2462 if (opP->reg == PC || opP->reg == ZPC)
2463 {
355afbcd 2464 opP->con1->e_exp.X_add_number += 6;
9d4dfbf3 2465 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 1);
355afbcd
KR		 2466 }
2467 else
2468 add_fix (siz2 == 3 ? 'l' : 'w', opP->con2, 0);
2469 }
2470 if (siz2 == 3)
2471 addword (outro >> 16);
2472 if (siz2)
2473 addword (outro);
6d27d3a2 2474
355afbcd 2475 break;
6d27d3a2 2476
355afbcd
KR		 2477 case ABSL:
2478 nextword = get_num (opP->con1, 80);
2479 switch (opP->con1->e_siz)
2480 {
2481 default:
2482 as_warn ("Unknown size for absolute reference");
2483 case 0:
2484 if (!isvar (opP->con1) && issword (offs (opP->con1)))
2485 {
2486 tmpreg = 0x38; /* 7.0 */
2487 addword (nextword);
2488 break;
2489 }
bcb8dff8
KR		 2490 /* Don't generate pc relative code on 68010 and
2491 68000. */
355afbcd
KR		 2492 if (isvar (opP->con1)
2493 && !subs (opP->con1)
49864cfa
KR		 2494 && seg (opP->con1) == text_section
2495 && now_seg == text_section
355afbcd
KR		 2496 && cpu_of_arch (current_architecture) >= m68020
2497 && !flagseen['S']
2498 && !strchr ("~%&$?", s[0]))
2499 {
2500 tmpreg = 0x3A; /* 7.2 */
2501 add_frag (adds (opP->con1),
2502 offs (opP->con1),
2503 TAB (PCREL, SZ_UNDEF));
2504 break;
2505 }
2506 case 3: /* Fall through into long */
2507 if (isvar (opP->con1))
2508 add_fix ('l', opP->con1, 0);
2509
2510 tmpreg = 0x39;/* 7.1 mode */
2511 addword (nextword >> 16);
2512 addword (nextword);
2513 break;
2514
2515 case 2: /* Word */
2516 if (isvar (opP->con1))
2517 add_fix ('w', opP->con1, 0);
2518
2519 tmpreg = 0x38;/* 7.0 mode */
2520 addword (nextword);
2521 break;
2522 }
2523 break;
2524 case DINDR:
2525 as_bad ("invalid indirect register");
2526 break;
2527 case MSCR:
2528 default:
2529 as_bad ("unknown/incorrect operand");
2530 /* abort(); */
2531 }
2532 install_gen_operand (s[1], tmpreg);
6d27d3a2 2533 break;
6d27d3a2 2534
355afbcd
KR		 2535 case '#':
2536 case '^':
2537 switch (s[1])
2538 { /* JF: I hate floating point! */
2539 case 'j':
2540 tmpreg = 70;
2541 break;
2542 case '8':
2543 tmpreg = 20;
2544 break;
2545 case 'C':
2546 tmpreg = 50;
2547 break;
2548 case '3':
2549 default:
2550 tmpreg = 80;
2551 break;
2552 }
2553 tmpreg = get_num (opP->con1, tmpreg);
2554 if (isvar (opP->con1))
2555 add_fix (s[1], opP->con1, 0);
2556 switch (s[1])
2557 {
2558 case 'b': /* Danger: These do no check for
6d27d3a2
KR		 2559 certain types of overflow.
2560 user beware! */
355afbcd
KR		 2561 if (!isbyte (tmpreg))
2562 opP->error = "out of range";
bcb8dff8 2563 insop (tmpreg, opcode);
355afbcd
KR		 2564 if (isvar (opP->con1))
2565 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2566 break;
2567 case 'w':
2568 if (!isword (tmpreg))
2569 opP->error = "out of range";
bcb8dff8 2570 insop (tmpreg, opcode);
355afbcd
KR		 2571 if (isvar (opP->con1))
2572 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2573 break;
2574 case 'l':
bcb8dff8
KR		 2575 /* Because of the way insop works, we put these two out
2576 backwards. */
2577 insop (tmpreg, opcode);
2578 insop (tmpreg >> 16, opcode);
355afbcd
KR		 2579 if (isvar (opP->con1))
2580 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2581 break;
2582 case '3':
2583 tmpreg &= 0xFF;
2584 case '8':
2585 case 'C':
2586 install_operand (s[1], tmpreg);
2587 break;
2588 default:
bcb8dff8 2589 as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s[1], __LINE__, __FILE__);
355afbcd
KR		 2590 }
2591 break;
6d27d3a2 2592
355afbcd
KR		 2593 case '+':
2594 case '-':
2595 case 'A':
2596 case 'a':
2597 install_operand (s[1], opP->reg - ADDR);
2598 break;
6d27d3a2 2599
355afbcd
KR		 2600 case 'B':
2601 tmpreg = get_num (opP->con1, 80);
2602 switch (s[1])
2603 {
2604 case 'B':
2605 /* Needs no offsetting */
2606 add_fix ('B', opP->con1, 1);
2607 break;
2608 case 'W':
2609 /* Offset the displacement to be relative to byte disp location */
2610 opP->con1->e_exp.X_add_number += 2;
2611 add_fix ('w', opP->con1, 1);
2612 addword (0);
2613 break;
2614 case 'L':
2615 long_branch:
2616 if (cpu_of_arch (current_architecture) < m68020) /* 68000 or 010 */
2617 as_warn ("Can't use long branches on 68000/68010");
2618 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2619 /* Offset the displacement to be relative to byte disp location */
2620 opP->con1->e_exp.X_add_number += 4;
2621 add_fix ('l', opP->con1, 1);
2622 addword (0);
2623 addword (0);
2624 break;
2625 case 'g':
2626 if (subs (opP->con1)) /* We can't relax it */
2627 goto long_branch;
6d27d3a2 2628
355afbcd 2629 /* This could either be a symbol, or an
1404ef23
KR		 2630 absolute address. No matter, the
2631 frag hacking will finger it out.
2632 Not quite: it can't switch from
2633 BRANCH to BCC68000 for the case
2634 where opnd is absolute (it needs
2635 to use the 68000 hack since no
2636 conditional abs jumps). */
355afbcd
KR		 2637 if (((cpu_of_arch (current_architecture) < m68020) || (0 == adds (opP->con1)))
2638 && (the_ins.opcode[0] >= 0x6200)
2639 && (the_ins.opcode[0] <= 0x6f00))
2640 {
2641 add_frag (adds (opP->con1), offs (opP->con1), TAB (BCC68000, SZ_UNDEF));
2642 }
2643 else
2644 {
2645 add_frag (adds (opP->con1), offs (opP->con1), TAB (ABRANCH, SZ_UNDEF));
2646 }
2647 break;
2648 case 'w':
2649 if (isvar (opP->con1))
2650 {
49864cfa 2651#if 1
355afbcd
KR		 2652 /* check for DBcc instruction */
2653 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2654 {
2655 /* size varies if patch */
2656 /* needed for long form */
2657 add_frag (adds (opP->con1), offs (opP->con1), TAB (DBCC, SZ_UNDEF));
2658 break;
2659 }
49864cfa 2660#endif
355afbcd
KR		 2661 /* Don't ask! */
2662 opP->con1->e_exp.X_add_number += 2;
2663 add_fix ('w', opP->con1, 1);
2664 }
2665 addword (0);
2666 break;
2667 case 'C': /* Fixed size LONG coproc branches */
2668 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2669 /* Offset the displacement to be relative to byte disp location */
2670 /* Coproc branches don't have a byte disp option, but they are
6d27d3a2 2671 compatible with the ordinary branches, which do... */
355afbcd
KR		 2672 opP->con1->e_exp.X_add_number += 4;
2673 add_fix ('l', opP->con1, 1);
2674 addword (0);
2675 addword (0);
2676 break;
2677 case 'c': /* Var size Coprocesssor branches */
2678 if (subs (opP->con1))
2679 {
2680 add_fix ('l', opP->con1, 1);
2681 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2682 }
2683 else if (adds (opP->con1))
2684 {
2685 add_frag (adds (opP->con1), offs (opP->con1), TAB (FBRANCH, SZ_UNDEF));
2686 }
2687 else
2688 {
2689 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2690 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2691 add_fix ('l', opP->con1, 1);
2692 addword (0);
2693 addword (4);
2694 }
2695 break;
2696 default:
bcb8dff8 2697 as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"",
355afbcd
KR		 2698 s[1], __LINE__, __FILE__);
2699 }
2700 break;
6d27d3a2 2701
355afbcd
KR		 2702 case 'C': /* Ignore it */
2703 break;
6d27d3a2 2704
355afbcd
KR		 2705 case 'd': /* JF this is a kludge */
2706 if (opP->mode == AOFF)
2707 {
2708 install_operand ('s', opP->reg - ADDR);
2709 }
2710 else
2711 {
2712 char *tmpP;
2713
2714 tmpP = opP->con1->e_end - 2;
2715 opP->con1->e_beg++;
2716 opP->con1->e_end -= 4; /* point to the , */
2717 baseo = m68k_reg_parse (&tmpP);
2718 if (baseo < ADDR + 0 || baseo > ADDR + 7)
2719 {
2720 as_bad ("Unknown address reg, using A0");
2721 baseo = 0;
2722 }
2723 else
2724 baseo -= ADDR;
2725 install_operand ('s', baseo);
2726 }
2727 tmpreg = get_num (opP->con1, 80);
2728 if (!issword (tmpreg))
2729 {
2730 as_warn ("Expression out of range, using 0");
2731 tmpreg = 0;
2732 }
2733 addword (tmpreg);
2734 break;
6d27d3a2 2735
355afbcd
KR		 2736 case 'D':
2737 install_operand (s[1], opP->reg - DATA);
2738 break;
6d27d3a2 2739
355afbcd
KR		 2740 case 'F':
2741 install_operand (s[1], opP->reg - FPREG);
2742 break;
6d27d3a2 2743
355afbcd
KR		 2744 case 'I':
2745 tmpreg = 1 + opP->reg - COPNUM;
2746 if (tmpreg == 8)
2747 tmpreg = 0;
2748 install_operand (s[1], tmpreg);
2749 break;
6d27d3a2 2750
355afbcd
KR		 2751 case 'J': /* JF foo */
2752 switch (opP->reg)
2753 {
2754 case SFC:
2755 tmpreg = 0x000;
2756 break;
2757 case DFC:
2758 tmpreg = 0x001;
2759 break;
2760 case CACR:
2761 tmpreg = 0x002;
2762 break;
2763 case TC:
2764 tmpreg = 0x003;
2765 break;
2766 case ITT0:
2767 tmpreg = 0x004;
2768 break;
2769 case ITT1:
2770 tmpreg = 0x005;
2771 break;
2772 case DTT0:
2773 tmpreg = 0x006;
2774 break;
2775 case DTT1:
2776 tmpreg = 0x007;
2777 break;
6d27d3a2 2778
355afbcd
KR		 2779 case USP:
2780 tmpreg = 0x800;
2781 break;
2782 case VBR:
2783 tmpreg = 0x801;
2784 break;
2785 case CAAR:
2786 tmpreg = 0x802;
2787 break;
2788 case MSP:
2789 tmpreg = 0x803;
2790 break;
2791 case ISP:
2792 tmpreg = 0x804;
2793 break;
2794 case MMUSR:
2795 tmpreg = 0x805;
2796 break;
2797 case URP:
2798 tmpreg = 0x806;
2799 break;
2800 case SRP:
2801 tmpreg = 0x807;
2802 break;
2803 default:
2804 as_fatal ("failed sanity check.");
2805 }
2806 install_operand (s[1], tmpreg);
2807 break;
6d27d3a2 2808
355afbcd
KR		 2809 case 'k':
2810 tmpreg = get_num (opP->con1, 55);
2811 install_operand (s[1], tmpreg & 0x7f);
2812 break;
6d27d3a2 2813
355afbcd
KR		 2814 case 'l':
2815 tmpreg = opP->reg;
2816 if (s[1] == 'w')
2817 {
2818 if (tmpreg & 0x7FF0000)
2819 as_bad ("Floating point register in register list");
bcb8dff8 2820 insop (reverse_16_bits (tmpreg), opcode);
355afbcd
KR		 2821 }
2822 else
2823 {
2824 if (tmpreg & 0x700FFFF)
2825 as_bad ("Wrong register in floating-point reglist");
2826 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2827 }
2828 break;
6d27d3a2 2829
355afbcd
KR		 2830 case 'L':
2831 tmpreg = opP->reg;
2832 if (s[1] == 'w')
2833 {
2834 if (tmpreg & 0x7FF0000)
2835 as_bad ("Floating point register in register list");
bcb8dff8 2836 insop (tmpreg, opcode);
355afbcd
KR		 2837 }
2838 else if (s[1] == '8')
2839 {
2840 if (tmpreg & 0x0FFFFFF)
2841 as_bad ("incorrect register in reglist");
2842 install_operand (s[1], tmpreg >> 24);
2843 }
2844 else
2845 {
2846 if (tmpreg & 0x700FFFF)
2847 as_bad ("wrong register in floating-point reglist");
2848 else
2849 install_operand (s[1], tmpreg >> 16);
2850 }
2851 break;
6d27d3a2 2852
355afbcd
KR		 2853 case 'M':
2854 install_operand (s[1], get_num (opP->con1, 60));
2855 break;
6d27d3a2 2856
355afbcd
KR		 2857 case 'O':
2858 tmpreg = (opP->mode == DREG)
2859 ? 0x20 + opP->reg - DATA
2860 : (get_num (opP->con1, 40) & 0x1F);
2861 install_operand (s[1], tmpreg);
2862 break;
6d27d3a2 2863
355afbcd
KR		 2864 case 'Q':
2865 tmpreg = get_num (opP->con1, 10);
2866 if (tmpreg == 8)
2867 tmpreg = 0;
2868 install_operand (s[1], tmpreg);
2869 break;
2870
2871 case 'R':
2872 case 'r':
2873 /* This depends on the fact that ADDR registers are
6d27d3a2
KR		 2874 eight more than their corresponding DATA regs, so
2875 the result will have the ADDR_REG bit set */
355afbcd
KR		 2876 install_operand (s[1], opP->reg - DATA);
2877 break;
6d27d3a2 2878
355afbcd
KR		 2879 case 's':
2880 if (opP->reg == FPI)
2881 tmpreg = 0x1;
2882 else if (opP->reg == FPS)
2883 tmpreg = 0x2;
2884 else if (opP->reg == FPC)
2885 tmpreg = 0x4;
2886 else
2887 as_fatal ("failed sanity check.");
2888 install_operand (s[1], tmpreg);
2889 break;
6d27d3a2 2890
355afbcd
KR		 2891 case 'S': /* Ignore it */
2892 break;
6d27d3a2 2893
355afbcd
KR		 2894 case 'T':
2895 install_operand (s[1], get_num (opP->con1, 30));
2896 break;
6d27d3a2 2897
355afbcd
KR		 2898 case 'U': /* Ignore it */
2899 break;
6d27d3a2 2900
355afbcd
KR		 2901 case 'c':
2902 switch (opP->reg)
2903 {
2904 case NC:
2905 tmpreg = 0;
2906 break;
2907 case DC:
2908 tmpreg = 1;
2909 break;
2910 case IC:
2911 tmpreg = 2;
2912 break;
2913 case BC:
2914 tmpreg = 3;
2915 break;
2916 default:
2917 as_fatal ("failed sanity check");
2918 } /* switch on cache token */
2919 install_operand (s[1], tmpreg);
2920 break;
a39116f1 2921#ifndef NO_68851
355afbcd
KR		 2922 /* JF: These are out of order, I fear. */
2923 case 'f':
2924 switch (opP->reg)
2925 {
2926 case SFC:
2927 tmpreg = 0;
2928 break;
2929 case DFC:
2930 tmpreg = 1;
2931 break;
2932 default:
2933 as_fatal ("failed sanity check.");
2934 }
2935 install_operand (s[1], tmpreg);
2936 break;
6d27d3a2 2937
355afbcd
KR		 2938 case 'P':
2939 switch (opP->reg)
2940 {
2941 case TC:
2942 tmpreg = 0;
2943 break;
2944 case CAL:
2945 tmpreg = 4;
2946 break;
2947 case VAL:
2948 tmpreg = 5;
2949 break;
2950 case SCC:
2951 tmpreg = 6;
2952 break;
2953 case AC:
2954 tmpreg = 7;
2955 break;
2956 default:
2957 as_fatal ("failed sanity check.");
2958 }
2959 install_operand (s[1], tmpreg);
2960 break;
6d27d3a2 2961
355afbcd
KR		 2962 case 'V':
2963 if (opP->reg == VAL)
2964 break;
2965 as_fatal ("failed sanity check.");
6d27d3a2 2966
355afbcd
KR		 2967 case 'W':
2968 switch (opP->reg)
2969 {
6d27d3a2 2970
355afbcd
KR		 2971 case DRP:
2972 tmpreg = 1;
2973 break;
2974 case SRP:
2975 tmpreg = 2;
2976 break;
2977 case CRP:
2978 tmpreg = 3;
2979 break;
2980 default:
2981 as_fatal ("failed sanity check.");
2982 }
2983 install_operand (s[1], tmpreg);
2984 break;
6d27d3a2 2985
355afbcd
KR		 2986 case 'X':
2987 switch (opP->reg)
2988 {
2989 case BAD:
2990 case BAD + 1:
2991 case BAD + 2:
2992 case BAD + 3:
2993 case BAD + 4:
2994 case BAD + 5:
2995 case BAD + 6:
2996 case BAD + 7:
2997 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2998 break;
6d27d3a2 2999
355afbcd
KR		 3000 case BAC:
3001 case BAC + 1:
3002 case BAC + 2:
3003 case BAC + 3:
3004 case BAC + 4:
3005 case BAC + 5:
3006 case BAC + 6:
3007 case BAC + 7:
3008 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3009 break;
6d27d3a2 3010
355afbcd
KR		 3011 default:
3012 as_fatal ("failed sanity check.");
3013 }
3014 install_operand (s[1], tmpreg);
3015 break;
3016 case 'Y':
3017 know (opP->reg == PSR);
3018 break;
3019 case 'Z':
3020 know (opP->reg == PCSR);
3021 break;
f8701a3f 3022#endif /* m68851 */
355afbcd
KR		 3023 case '3':
3024 switch (opP->reg)
3025 {
3026 case TT0:
3027 tmpreg = 2;
3028 break;
3029 case TT1:
3030 tmpreg = 3;
3031 break;
3032 default:
3033 as_fatal ("failed sanity check");
3034 }
3035 install_operand (s[1], tmpreg);
3036 break;
3037 case 't':
3038 tmpreg = get_num (opP->con1, 20);
3039 install_operand (s[1], tmpreg);
4134a793 3040 break;
355afbcd
KR		 3041 case '_': /* used only for move16 absolute 32-bit address */
3042 tmpreg = get_num (opP->con1, 80);
3043 addword (tmpreg >> 16);
3044 addword (tmpreg & 0xFFFF);
4134a793
KR		 3045 break;
3046 default:
355afbcd
KR		 3047 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3048 s[0], __LINE__, __FILE__);
4134a793 3049 }
6d27d3a2 3050 }
3ad9ec6a 3051
6d27d3a2
KR		 3052 /* By the time whe get here (FINALLY) the_ins contains the complete
3053 instruction, ready to be emitted. . . */
355afbcd 3054} /* m68k_ip() */
7c15cbe8
RP		 3055
3056/*
3057 * get_regs := '/' + ?
3058 * | '-' + <register>
3059 * | '-' + <register> + ?
3060 * | <empty>
3061 * ;
3062 *
6d27d3a2 3063
7c15cbe8
RP		 3064 * The idea here must be to scan in a set of registers but I don't
3065 * understand it. Looks awfully sloppy to me but I don't have any doc on
3066 * this format so...
6d27d3a2
KR		 3067
3068 *
7c15cbe8
RP		 3069 *
3070 */
fecd2382 3071
355afbcd
KR		 3072static int
3073get_regs (i, str, opP)
3074 int i;
3075 struct m68k_op *opP;
3076 char *str;
fecd2382 3077{
355afbcd
KR		 3078 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3079 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3080 unsigned long cur_regs = 0;
3081 int reg1, reg2;
6d27d3a2 3082
fecd2382 3083#define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
a39116f1
RP		 3084else if(x==FPS) cur_regs|=(1<<25);\
3085else if(x==FPC) cur_regs|=(1<<26);\
3086else cur_regs|=(1<<(x-1)); }
6d27d3a2 3087
355afbcd
KR		 3088 reg1 = i;
3089 for (;;)
3090 {
3091 if (*str == '/')
3092 {
3093 ADD_REG (reg1);
3094 str++;
3095 }
3096 else if (*str == '-')
3097 {
3098 str++;
3099 reg2 = m68k_reg_parse (&str);
3100 if (reg2 < DATA || reg2 >= FPREG + 8 || reg1 == FPI || reg1 == FPS || reg1 == FPC)
3101 {
3102 opP->error = "unknown register in register list";
3103 return FAIL;
3104 }
3105 while (reg1 <= reg2)
3106 {
3107 ADD_REG (reg1);
3108 reg1++;
3109 }
3110 if (*str == '\0')
3111 break;
3112 }
3113 else if (*str == '\0')
3114 {
3115 ADD_REG (reg1);
3116 break;
3117 }
3118 else
3119 {
3120 opP->error = "unknow character in register list";
3121 return FAIL;
3122 }
3123 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3124 if (*str == '/')
3125 str++;
3126 reg1 = m68k_reg_parse (&str);
3127 if ((reg1 < DATA || reg1 >= FPREG + 8) && !(reg1 == FPI || reg1 == FPS || reg1 == FPC))
3128 {
3129 opP->error = "unknown register in register list";
3130 return FAIL;
a39116f1 3131 }
355afbcd
KR		 3132 }
3133 opP->reg = cur_regs;
3134 return OK;
3135} /* get_regs() */
fecd2382 3136
355afbcd
KR		 3137static int
3138reverse_16_bits (in)
3139 int in;
fecd2382 3140{
355afbcd
KR		 3141 int out = 0;
3142 int n;
6d27d3a2 3143
355afbcd
KR		 3144 static int mask[16] =
3145 {
3146 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3147 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3148 };
3149 for (n = 0; n < 16; n++)
3150 {
3151 if (in & mask[n])
3152 out |= mask[15 - n];
3153 }
3154 return out;
3155} /* reverse_16_bits() */
fecd2382 3156
355afbcd
KR		 3157static int
3158reverse_8_bits (in)
3159 int in;
fecd2382 3160{
355afbcd
KR		 3161 int out = 0;
3162 int n;
6d27d3a2 3163
355afbcd
KR		 3164 static int mask[8] =
3165 {
3166 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3167 };
6d27d3a2 3168
355afbcd
KR		 3169 for (n = 0; n < 8; n++)
3170 {
3171 if (in & mask[n])
3172 out |= mask[7 - n];
3173 }
3174 return out;
3175} /* reverse_8_bits() */
fecd2382 3176
355afbcd
KR		 3177static void
3178install_operand (mode, val)
3179 int mode;
3180 int val;
fecd2382 3181{
355afbcd
KR		 3182 switch (mode)
3183 {
3184 case 's':
3185 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3186 break;
3187 case 'd':
3188 the_ins.opcode[0] |= val << 9;
3189 break;
3190 case '1':
3191 the_ins.opcode[1] |= val << 12;
3192 break;
3193 case '2':
3194 the_ins.opcode[1] |= val << 6;
3195 break;
3196 case '3':
3197 the_ins.opcode[1] |= val;
3198 break;
3199 case '4':
3200 the_ins.opcode[2] |= val << 12;
3201 break;
3202 case '5':
3203 the_ins.opcode[2] |= val << 6;
3204 break;
3205 case '6':
bcb8dff8
KR		 3206 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3207 three words long! */
355afbcd
KR		 3208 the_ins.numo++;
3209 the_ins.opcode[2] |= val;
3210 break;
3211 case '7':
3212 the_ins.opcode[1] |= val << 7;
3213 break;
3214 case '8':
3215 the_ins.opcode[1] |= val << 10;
3216 break;
f8701a3f 3217#ifndef NO_68851
355afbcd
KR		 3218 case '9':
3219 the_ins.opcode[1] |= val << 5;
3220 break;
f8701a3f 3221#endif
6d27d3a2 3222
355afbcd
KR		 3223 case 't':
3224 the_ins.opcode[1] |= (val << 10) | (val << 7);
3225 break;
3226 case 'D':
3227 the_ins.opcode[1] |= (val << 12) | val;
3228 break;
3229 case 'g':
3230 the_ins.opcode[0] |= val = 0xff;
3231 break;
3232 case 'i':
3233 the_ins.opcode[0] |= val << 9;
3234 break;
3235 case 'C':
3236 the_ins.opcode[1] |= val;
3237 break;
3238 case 'j':
3239 the_ins.opcode[1] |= val;
3240 the_ins.numo++; /* What a hack */
3241 break;
3242 case 'k':
3243 the_ins.opcode[1] |= val << 4;
3244 break;
3245 case 'b':
3246 case 'w':
3247 case 'l':
3248 break;
3249 case 'e':
3250 the_ins.opcode[0] |= (val << 6);
3251 break;
3252 case 'L':
3253 the_ins.opcode[1] = (val >> 16);
3254 the_ins.opcode[2] = val & 0xffff;
3255 break;
3256 case 'c':
3257 default:
3258 as_fatal ("failed sanity check.");
3259 }
3260} /* install_operand() */
fecd2382 3261
355afbcd
KR		 3262static void
3263install_gen_operand (mode, val)
3264 int mode;
3265 int val;
fecd2382 3266{
355afbcd
KR		 3267 switch (mode)
3268 {
3269 case 's':
3270 the_ins.opcode[0] |= val;
3271 break;
3272 case 'd':
3273 /* This is a kludge!!! */
3274 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3275 break;
3276 case 'b':
3277 case 'w':
3278 case 'l':
3279 case 'f':
3280 case 'F':
3281 case 'x':
3282 case 'p':
3283 the_ins.opcode[0] |= val;
3284 break;
3285 /* more stuff goes here */
3286 default:
3287 as_fatal ("failed sanity check.");
3288 }
3289} /* install_gen_operand() */
fecd2382 3290
7c15cbe8
RP		 3291/*
3292 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3293 * then deal with the bitfield hack.
3294 */
3295
355afbcd
KR		 3296static char *
3297crack_operand (str, opP)
3298 register char *str;
3299 register struct m68k_op *opP;
fecd2382 3300{
355afbcd
KR		 3301 register int parens;
3302 register int c;
3303 register char *beg_str;
6d27d3a2 3304
355afbcd
KR		 3305 if (!str)
3306 {
3307 return str;
3308 }
3309 beg_str = str;
3310 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
3311 {
3312 if (*str == '(')
3313 parens++;
3314 else if (*str == ')')
3315 {
3316 if (!parens)
3317 { /* ERROR */
3318 opP->error = "Extra )";
3319 return str;
3320 }
3321 --parens;
f8701a3f 3322 }
355afbcd
KR		 3323 }
3324 if (!*str && parens)
3325 { /* ERROR */
3326 opP->error = "Missing )";
3327 return str;
3328 }
3329 c = *str;
3330 *str = '\0';
3331 if (m68k_ip_op (beg_str, opP) == FAIL)
3332 {
3333 *str = c;
3334 return str;
3335 }
3336 *str = c;
3337 if (c == '}')
3338 c = *++str; /* JF bitfield hack */
3339 if (c)
3340 {
3341 c = *++str;
3342 if (!c)
3343 as_bad ("Missing operand");
3344 }
3345 return str;
fecd2382
RP		 3346}
3347
3348/* See the comment up above where the #define notend(... is */
3349#if 0
355afbcd
KR		 3350notend (s)
3351 char *s;
fecd2382 3352{
355afbcd
KR		 3353 if (*s == ',')
3354 return 0;
3355 if (*s == '{' || *s == '}')
3356 return 0;
3357 if (*s != ':')
3358 return 1;
3359 /* This kludge here is for the division cmd, which is a kludge */
3360 if (index ("aAdD#", s[1]))
3361 return 0;
3362 return 1;
fecd2382 3363}
355afbcd 3364
fecd2382
RP		 3365#endif
3366
3367/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 3368 machine dependent instruction. This function is supposed to emit
fecd2382 3369 the frags/bytes it assembles to.
a39116f1 3370 */
a933d598
SC		 3371
3372void
355afbcd
KR		 3373insert_reg (regname, regnum)
3374 char *regname;
3375 int regnum;
a933d598
SC		 3376{
3377 char buf[100];
3378 int i;
49864cfa 3379symbolS *s;
355afbcd
KR		 3380
3381#ifdef REGISTER_PREFIX
3382 buf[0] = REGISTER_PREFIX;
3383 strcpy (buf + 1, regname);
3384 regname = buf;
3385#endif
3386
49864cfa
KR		 3387 symbol_table_insert (s = symbol_new (regname, reg_section, regnum, &zero_address_frag));
3388
3389verify_symbol_chain_2 (s);
a933d598
SC		 3390
3391 for (i = 0; regname[i]; i++)
355afbcd 3392 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
a933d598 3393 buf[i] = '\0';
6d27d3a2 3394
49864cfa
KR		 3395 symbol_table_insert (s = symbol_new (buf, reg_section, regnum, &zero_address_frag));
3396verify_symbol_chain_2 (s);
a933d598
SC		 3397}
3398
49864cfa 3399struct init_entry
355afbcd 3400 {
bcb8dff8 3401 const char *name;
355afbcd 3402 int number;
49864cfa 3403 };
355afbcd 3404
bcb8dff8 3405static const struct init_entry init_table[] =
355afbcd 3406{
bcb8dff8
KR		 3407 { "d0", DATA0 },
3408 { "d1", DATA1 },
3409 { "d2", DATA2 },
3410 { "d3", DATA3 },
3411 { "d4", DATA4 },
3412 { "d5", DATA5 },
3413 { "d6", DATA6 },
3414 { "d7", DATA7 },
3415 { "a0", ADDR0 },
3416 { "a1", ADDR1 },
3417 { "a2", ADDR2 },
3418 { "a3", ADDR3 },
3419 { "a4", ADDR4 },
3420 { "a5", ADDR5 },
3421 { "a6", ADDR6 },
3422 { "fp", ADDR6 },
3423 { "a7", ADDR7 },
3424 { "sp", ADDR7 },
3425 { "fp0", FP0 },
3426 { "fp1", FP1 },
3427 { "fp2", FP2 },
3428 { "fp3", FP3 },
3429 { "fp4", FP4 },
3430 { "fp5", FP5 },
3431 { "fp6", FP6 },
3432 { "fp7", FP7 },
3433 { "fpi", FPI },
3434 { "fpiar", FPI },
3435 { "fpc", FPI },
3436 { "fps", FPS },
3437 { "fpsr", FPS },
3438 { "fpc", FPC },
3439 { "fpcr", FPC },
3440
3441 { "cop0", COP0 },
3442 { "cop1", COP1 },
3443 { "cop2", COP2 },
3444 { "cop3", COP3 },
3445 { "cop4", COP4 },
3446 { "cop5", COP5 },
3447 { "cop6", COP6 },
3448 { "cop7", COP7 },
3449 { "pc", PC },
3450 { "zpc", ZPC },
3451 { "sr", SR },
3452
3453 { "ccr", CCR },
3454 { "cc", CCR },
3455
3456 { "usp", USP },
3457 { "isp", ISP },
3458 { "sfc", SFC },
3459 { "dfc", DFC },
3460 { "cacr", CACR },
3461 { "caar", CAAR },
3462
3463 { "vbr", VBR },
3464
3465 { "msp", MSP },
3466 { "itt0", ITT0 },
3467 { "itt1", ITT1 },
3468 { "dtt0", DTT0 },
3469 { "dtt1", DTT1 },
3470 { "mmusr", MMUSR },
3471 { "tc", TC },
3472 { "srp", SRP },
3473 { "urp", URP },
3474
3475 { "ac", AC },
3476 { "bc", BC },
3477 { "cal", CAL },
3478 { "crp", CRP },
3479 { "drp", DRP },
3480 { "pcsr", PCSR },
3481 { "psr", PSR },
3482 { "scc", SCC },
3483 { "val", VAL },
3484 { "bad0", BAD0 },
3485 { "bad1", BAD1 },
3486 { "bad2", BAD2 },
3487 { "bad3", BAD3 },
3488 { "bad4", BAD4 },
3489 { "bad5", BAD5 },
3490 { "bad6", BAD6 },
3491 { "bad7", BAD7 },
3492 { "bac0", BAC0 },
3493 { "bac1", BAC1 },
3494 { "bac2", BAC2 },
3495 { "bac3", BAC3 },
3496 { "bac4", BAC4 },
3497 { "bac5", BAC5 },
3498 { "bac6", BAC6 },
3499 { "bac7", BAC7 },
3500
3501 { "ic", IC },
3502 { "dc", DC },
3503 { "nc", NC },
3504
3505 { "tt0", TT0 },
3506 { "tt1", TT1 },
4134a793 3507 /* 68ec030 versions of same */
bcb8dff8
KR		 3508 { "ac0", TT0 },
3509 { "ac1", TT1 },
4134a793 3510 /* 68ec030 access control unit, identical to 030 MMU status reg */
bcb8dff8 3511 { "acusr", PSR },
a933d598 3512
bcb8dff8 3513 { 0, 0 }
a933d598
SC		 3514};
3515
a933d598 3516void
355afbcd 3517init_regtable ()
a933d598
SC		 3518{
3519 int i;
6d27d3a2 3520 for (i = 0; init_table[i].name; i++)
355afbcd 3521 insert_reg (init_table[i].name, init_table[i].number);
a933d598 3522}
6d27d3a2 3523
df3768fb 3524static int no_68851, no_68881;
a933d598 3525
dff60b7d
ILT		 3526#ifdef OBJ_AOUT
3527/* a.out machine type. Default to 68020. */
3528int m68k_aout_machtype = 2;
3529#endif
3530
fecd2382 3531void
355afbcd 3532md_assemble (str)
6d27d3a2 3533 char *str;
fecd2382 3534{
355afbcd
KR		 3535 char *er;
3536 short *fromP;
3537 char *toP = NULL;
3538 int m, n = 0;
3539 char *to_beg_P;
3540 int shorts_this_frag;
3541 static int done_first_time;
3542
3543 if (!done_first_time)
3544 {
3545 done_first_time = 1;
4134a793 3546
355afbcd
KR		 3547 if (cpu_of_arch (current_architecture) == 0)
3548 {
3549 int cpu_type;
148eb5dd 3550
e284846a
KR		 3551 if (strcmp (TARGET_CPU, "m68000") == 0
3552 || strcmp (TARGET_CPU, "m68302") == 0)
355afbcd
KR		 3553 cpu_type = m68000;
3554 else if (strcmp (TARGET_CPU, "m68010") == 0)
3555 cpu_type = m68010;
3556 else if (strcmp (TARGET_CPU, "m68020") == 0
3557 || strcmp (TARGET_CPU, "m68k") == 0)
3558 cpu_type = m68020;
3559 else if (strcmp (TARGET_CPU, "m68030") == 0)
3560 cpu_type = m68030;
3561 else if (strcmp (TARGET_CPU, "m68040") == 0)
3562 cpu_type = m68040;
e284846a
KR		 3563 else if (strcmp (TARGET_CPU, "cpu32") == 0
3564 || strcmp (TARGET_CPU, "m68331") == 0
3565 || strcmp (TARGET_CPU, "m68332") == 0
3566 || strcmp (TARGET_CPU, "m68333") == 0
3567 || strcmp (TARGET_CPU, "m68340") == 0)
355afbcd
KR		 3568 cpu_type = cpu32;
3569 else
3570 cpu_type = m68020;
148eb5dd 3571
355afbcd
KR		 3572 current_architecture |= cpu_type;
3573 }
3574#if 0 /* Could be doing emulation. */
3575 if (current_architecture & m68881)
3576 {
3577 if (current_architecture & m68000)
3578 as_bad ("incompatible processors 68000 and 68881/2 specified");
3579 if (current_architecture & m68010)
3580 as_bad ("incompatible processors 68010 and 68881/2 specified");
3581 if (current_architecture & m68040)
3582 as_bad ("incompatible processors 68040 and 68881/2 specified");
3583 }
3584#endif
3585 /* What other incompatibilities could we check for? */
6d27d3a2 3586
355afbcd
KR		 3587 /* Toss in some default assumptions about coprocessors. */
3588 if (!no_68881
3589 && (cpu_of_arch (current_architecture)
3590 /* Can CPU32 have a 68881 coprocessor?? */
3591 & (m68020 | m68030 | cpu32)))
3592 {
3593 current_architecture |= m68881;
fecd2382 3594 }
355afbcd 3595 if (!no_68851
025b0302
ME		 3596 && (cpu_of_arch (current_architecture) & m68020up) != 0
3597 && cpu_of_arch (current_architecture) != m68040)
355afbcd
KR		 3598 {
3599 current_architecture |= m68851;
fecd2382 3600 }
355afbcd
KR		 3601 if (no_68881 && (current_architecture & m68881))
3602 as_bad ("options for 68881 and no-68881 both given");
3603 if (no_68851 && (current_architecture & m68851))
3604 as_bad ("options for 68851 and no-68851 both given");
dff60b7d
ILT		 3605
3606#ifdef OBJ_AOUT
3607 /* Work out the magic number. This isn't very general. */
3608 if (current_architecture & m68000)
3609 m68k_aout_machtype = 0;
3610 else if (current_architecture & m68010)
3611 m68k_aout_machtype = 1;
3612 else if (current_architecture & m68020)
3613 m68k_aout_machtype = 2;
3614 else
3615 m68k_aout_machtype = 2;
3616#endif
355afbcd 3617 }
6d27d3a2 3618
e284846a 3619 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
355afbcd
KR		 3620 m68k_ip (str);
3621 er = the_ins.error;
3622 if (!er)
3623 {
3624 for (n = the_ins.numargs; n; --n)
3625 if (the_ins.operands[n].error)
3626 {
3627 er = the_ins.operands[n].error;
3628 break;
3629 }
3630 }
3631 if (er)
3632 {
3633 as_bad ("%s -- statement `%s' ignored", er, str);
3634 return;
3635 }
6d27d3a2 3636
355afbcd 3637 if (the_ins.nfrag == 0)
49864cfa
KR		 3638 {
3639 /* No frag hacking involved; just put it out */
355afbcd
KR		 3640 toP = frag_more (2 * the_ins.numo);
3641 fromP = &the_ins.opcode[0];
3642 for (m = the_ins.numo; m; --m)
3643 {
3644 md_number_to_chars (toP, (long) (*fromP), 2);
3645 toP += 2;
3646 fromP++;
f8701a3f 3647 }
355afbcd
KR		 3648 /* put out symbol-dependent info */
3649 for (m = 0; m < the_ins.nrel; m++)
3650 {
3651 switch (the_ins.reloc[m].wid)
3652 {
3653 case 'B':
3654 n = 1;
3655 break;
3656 case 'b':
3657 n = 1;
3658 break;
3659 case '3':
3660 n = 2;
3661 break;
3662 case 'w':
3663 n = 2;
3664 break;
3665 case 'l':
3666 n = 4;
3667 break;
3668 default:
49864cfa
KR		 3669 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3670 the_ins.reloc[m].wid);
355afbcd 3671 }
6d27d3a2 3672
bcb8dff8
KR		 3673 fix_new_exp (frag_now,
3674 ((toP - frag_now->fr_literal)
3675 - the_ins.numo * 2 + the_ins.reloc[m].n),
3676 n,
3677 &the_ins.reloc[m].exp,
3678 the_ins.reloc[m].pcrel,
3679 NO_RELOC);
f8701a3f 3680 }
355afbcd
KR		 3681 return;
3682 }
3683
3684 /* There's some frag hacking */
3685 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3686 {
3687 int wid;
3688
3689 if (n == 0)
3690 wid = 2 * the_ins.fragb[n].fragoff;
3691 else
3692 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3693 toP = frag_more (wid);
3694 to_beg_P = toP;
3695 shorts_this_frag = 0;
3696 for (m = wid / 2; m; --m)
3697 {
3698 md_number_to_chars (toP, (long) (*fromP), 2);
3699 toP += 2;
3700 fromP++;
3701 shorts_this_frag++;
3702 }
3703 for (m = 0; m < the_ins.nrel; m++)
3704 {
49864cfa 3705 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
355afbcd 3706 {
49864cfa 3707 the_ins.reloc[m].n -= 2 * shorts_this_frag;
355afbcd
KR		 3708 break;
3709 }
3710 wid = the_ins.reloc[m].wid;
3711 if (wid == 0)
3712 continue;
3713 the_ins.reloc[m].wid = 0;
3714 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3715
bcb8dff8
KR		 3716 fix_new_exp (frag_now,
3717 ((toP - frag_now->fr_literal)
3718 - the_ins.numo * 2 + the_ins.reloc[m].n),
3719 wid,
3720 &the_ins.reloc[m].exp,
3721 the_ins.reloc[m].pcrel,
3722 NO_RELOC);
fecd2382 3723 }
49864cfa
KR		 3724 (void) frag_var (rs_machine_dependent, 10, 0,
3725 (relax_substateT) (the_ins.fragb[n].fragty),
3726 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
355afbcd
KR		 3727 }
3728 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3729 shorts_this_frag = 0;
3730 if (n)
3731 {
3732 toP = frag_more (n * sizeof (short));
3733 while (n--)
3734 {
3735 md_number_to_chars (toP, (long) (*fromP), 2);
3736 toP += 2;
3737 fromP++;
3738 shorts_this_frag++;
fecd2382 3739 }
355afbcd
KR		 3740 }
3741 for (m = 0; m < the_ins.nrel; m++)
3742 {
3743 int wid;
3744
3745 wid = the_ins.reloc[m].wid;
3746 if (wid == 0)
3747 continue;
3748 the_ins.reloc[m].wid = 0;
3749 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3750
bcb8dff8
KR		 3751 fix_new_exp (frag_now,
3752 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3753 - shorts_this_frag * 2),
3754 wid,
3755 &the_ins.reloc[m].exp,
3756 the_ins.reloc[m].pcrel,
3757 NO_RELOC);
355afbcd 3758 }
fecd2382
RP		 3759}
3760
e284846a
KR		 3761/* See BREAK_UP_BIG_DECL definition, above. */
3762static struct m68k_opcode *
3763opcode_ptr (i)
3764 int i;
3765{
3766#ifdef DO_BREAK_UP_BIG_DECL
3767 int lim1 = sizeof (m68k_opcodes) / sizeof (m68k_opcodes[0]);
3768 if (i >= lim1)
3769 return m68k_opcodes_2 + (i - lim1);
3770#endif
3771 return m68k_opcodes + i;
3772}
f8701a3f 3773
fecd2382 3774void
355afbcd 3775md_begin ()
fecd2382 3776{
355afbcd 3777 /*
e284846a
KR		 3778 * md_begin -- set up hash tables with 68000 instructions.
3779 * similar to what the vax assembler does. ---phr
3780 */
355afbcd 3781 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
e284846a
KR		 3782 a copy of it at runtime, adding in the information we want but isn't
3783 there. I think it'd be better to have an awk script hack the table
3784 at compile time. Or even just xstr the table and use it as-is. But
3785 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3786 names. */
6d27d3a2 3787
49864cfa 3788 register CONST struct m68k_opcode *ins;
355afbcd 3789 register struct m68k_incant *hack, *slak;
bcb8dff8 3790 register const char *retval = 0; /* empty string, or error msg text */
355afbcd
KR		 3791 register unsigned int i;
3792 register char c;
3793
3794 if ((op_hash = hash_new ()) == NULL)
3795 as_fatal ("Virtual memory exhausted");
3796
3797 obstack_begin (&robyn, 4000);
e284846a 3798 for (i = 0; i < numopcodes; i++)
355afbcd
KR		 3799 {
3800 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3801 do
3802 {
e284846a
KR		 3803 ins = opcode_ptr (i);
3804 /* We *could* ignore insns that don't match our arch here
3805 but just leaving them out of the hash. */
355afbcd
KR		 3806 slak->m_operands = ins->args;
3807 slak->m_opnum = strlen (slak->m_operands) / 2;
3808 slak->m_arch = ins->arch;
3809 slak->m_opcode = ins->opcode;
3810 /* This is kludgey */
3811 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
e284846a
KR		 3812 if (i + 1 != numopcodes
3813 && !strcmp (ins->name, opcode_ptr (i + 1)->name))
355afbcd
KR		 3814 {
3815 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
e284846a 3816 i++;
355afbcd
KR		 3817 }
3818 else
3819 slak->m_next = 0;
3820 slak = slak->m_next;
f8701a3f 3821 }
355afbcd
KR		 3822 while (slak);
3823
3824 retval = hash_insert (op_hash, ins->name, (char *) hack);
3825 /* Didn't his mommy tell him about null pointers? */
dff60b7d 3826 if (retval)
355afbcd
KR		 3827 as_bad ("Internal Error: Can't hash %s: %s", ins->name, retval);
3828 }
6d27d3a2 3829
355afbcd
KR		 3830 for (i = 0; i < sizeof (mklower_table); i++)
3831 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
6d27d3a2 3832
355afbcd
KR		 3833 for (i = 0; i < sizeof (notend_table); i++)
3834 {
3835 notend_table[i] = 0;
3836 alt_notend_table[i] = 0;
3837 }
3838 notend_table[','] = 1;
3839 notend_table['{'] = 1;
3840 notend_table['}'] = 1;
3841 alt_notend_table['a'] = 1;
3842 alt_notend_table['A'] = 1;
3843 alt_notend_table['d'] = 1;
3844 alt_notend_table['D'] = 1;
3845 alt_notend_table['#'] = 1;
3846 alt_notend_table['f'] = 1;
3847 alt_notend_table['F'] = 1;
fecd2382 3848#ifdef REGISTER_PREFIX
355afbcd 3849 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3850#endif
0069b1f6 3851#ifdef OPTIONAL_REGISTER_PREFIX
355afbcd 3852 alt_notend_table[OPTIONAL_REGISTER_PREFIX] = 1;
0069b1f6 3853#endif
f8701a3f 3854
3ad9ec6a 3855#ifndef MIT_SYNTAX_ONLY
355afbcd 3856 /* Insert pseudo ops, these have to go into the opcode table since
bcb8dff8 3857 gas expects pseudo ops to start with a dot */
355afbcd
KR		 3858 {
3859 int n = 0;
3860 while (mote_pseudo_table[n].poc_name)
3861 {
3862 hack = (struct m68k_incant *)
3863 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3864 hash_insert (op_hash,
3865 mote_pseudo_table[n].poc_name, (char *) hack);
3866 hack->m_operands = 0;
3867 hack->m_opnum = n;
3868 n++;
3869 }
3870 }
3ad9ec6a
ILT		 3871#endif
3872
355afbcd 3873 init_regtable ();
fecd2382
RP		 3874}
3875
3876#if 0
3877#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
a39116f1
RP		 3878 || (*s == ':' && strchr("aAdD#", s[1]))) \
3879 ? 0 : 1)
fecd2382
RP		 3880#endif
3881
3882/* This funciton is called once, before the assembler exits. It is
3883 supposed to do any final cleanup for this part of the assembler.
a39116f1 3884 */
fecd2382 3885void
355afbcd 3886md_end ()
fecd2382
RP		 3887{
3888}
3889
3890/* Equal to MAX_PRECISION in atof-ieee.c */
3891#define MAX_LITTLENUMS 6
3892
3893/* Turn a string in input_line_pointer into a floating point constant of type
3894 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3895 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
a39116f1 3896 */
fecd2382 3897char *
355afbcd
KR		 3898md_atof (type, litP, sizeP)
3899 char type;
3900 char *litP;
3901 int *sizeP;
fecd2382 3902{
355afbcd
KR		 3903 int prec;
3904 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3905 LITTLENUM_TYPE *wordP;
3906 char *t;
3907 char *atof_ieee ();
6d27d3a2 3908
355afbcd
KR		 3909 switch (type)
3910 {
3911 case 'f':
3912 case 'F':
3913 case 's':
3914 case 'S':
3915 prec = 2;
3916 break;
6d27d3a2 3917
355afbcd
KR		 3918 case 'd':
3919 case 'D':
3920 case 'r':
3921 case 'R':
3922 prec = 4;
3923 break;
6d27d3a2 3924
355afbcd
KR		 3925 case 'x':
3926 case 'X':
3927 prec = 6;
3928 break;
6d27d3a2 3929
355afbcd
KR		 3930 case 'p':
3931 case 'P':
3932 prec = 6;
3933 break;
6d27d3a2 3934
355afbcd
KR		 3935 default:
3936 *sizeP = 0;
3937 return "Bad call to MD_ATOF()";
3938 }
3939 t = atof_ieee (input_line_pointer, type, words);
3940 if (t)
3941 input_line_pointer = t;
3942
3943 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3944 for (wordP = words; prec--;)
3945 {
3946 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3947 litP += sizeof (LITTLENUM_TYPE);
3948 }
49864cfa 3949 return 0;
fecd2382
RP		 3950}
3951
3952/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3953 for use in the a.out file, and stores them in the array pointed to by buf.
3954 This knows about the endian-ness of the target machine and does
3955 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3956 2 (short) and 4 (long) Floating numbers are put out as a series of
3957 LITTLENUMS (shorts, here at least)
a39116f1 3958 */
fecd2382 3959void
355afbcd
KR		 3960md_number_to_chars (buf, val, n)
3961 char *buf;
025b0302 3962 valueT val;
355afbcd 3963 int n;
fecd2382 3964{
355afbcd
KR		 3965 switch (n)
3966 {
3967 case 1:
3968 *buf++ = val;
3969 break;
3970 case 2:
3971 *buf++ = (val >> 8);
3972 *buf++ = val;
3973 break;
3974 case 4:
3975 *buf++ = (val >> 24);
3976 *buf++ = (val >> 16);
3977 *buf++ = (val >> 8);
3978 *buf++ = val;
3979 break;
3980 default:
3981 as_fatal ("failed sanity check.");
3982 }
fecd2382
RP		 3983}
3984
49864cfa
KR		 3985static void
3986md_apply_fix_2 (fixP, val)
355afbcd
KR		 3987 fixS *fixP;
3988 long val;
fecd2382 3989{
49864cfa
KR		 3990 unsigned long upper_limit;
3991 long lower_limit;
3992
587c4264 3993#ifdef IBM_COMPILER_SUX
355afbcd 3994 /* This is unnecessary but it convinces the native rs6000
e284846a 3995 compiler to generate the code we want. */
355afbcd
KR		 3996 char *buf = fixP->fx_frag->fr_literal;
3997 buf += fixP->fx_where;
587c4264 3998#else /* IBM_COMPILER_SUX */
355afbcd 3999 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
587c4264 4000#endif /* IBM_COMPILER_SUX */
6d27d3a2 4001
355afbcd
KR		 4002 switch (fixP->fx_size)
4003 {
4004 case 1:
4005 *buf++ = val;
49864cfa
KR		 4006 upper_limit = 0x7f;
4007 lower_limit = -0x80;
355afbcd
KR		 4008 break;
4009 case 2:
4010 *buf++ = (val >> 8);
4011 *buf++ = val;
49864cfa
KR		 4012 upper_limit = 0x7fff;
4013 lower_limit = -0x8000;
355afbcd
KR		 4014 break;
4015 case 4:
4016 *buf++ = (val >> 24);
4017 *buf++ = (val >> 16);
4018 *buf++ = (val >> 8);
4019 *buf++ = val;
49864cfa
KR		 4020 upper_limit = 0x7fffffff;
4021 lower_limit = -0x80000000;
355afbcd
KR		 4022 break;
4023 default:
4024 BAD_CASE (fixP->fx_size);
4025 }
49864cfa
KR		 4026
4027 /* For non-pc-relative values, it's conceivable we might get something
4028 like "0xff" for a byte field. So extend the upper part of the range
4029 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4030 so that we can do any range checking at all. */
4031 if (!fixP->fx_pcrel)
4032 upper_limit = upper_limit * 2 + 1;
4033
4034 if ((unsigned) val > upper_limit && (val > 0 || val < lower_limit))
4035 as_bad ("value out of range");
fecd2382
RP		 4036}
4037
49864cfa
KR		 4038#ifdef BFD_ASSEMBLER
4039int
4040md_apply_fix (fixP, valp)
4041 fixS *fixP;
4042 long *valp;
4043{
4044 md_apply_fix_2 (fixP, *valp);
4045 return 1;
4046}
4047#else
4048void md_apply_fix (fixP, val)
4049 fixS *fixP;
4050 long val;
4051{
4052 md_apply_fix_2 (fixP, val);
4053}
4054#endif
fecd2382
RP		 4055
4056/* *fragP has been relaxed to its final size, and now needs to have
4057 the bytes inside it modified to conform to the new size There is UGLY
4058 MAGIC here. ..
a39116f1 4059 */
fecd2382 4060void
49864cfa 4061md_convert_frag_1 (fragP)
355afbcd 4062 register fragS *fragP;
fecd2382 4063{
355afbcd
KR		 4064 long disp;
4065 long ext = 0;
6d27d3a2 4066
355afbcd
KR		 4067 /* Address in object code of the displacement. */
4068 register int object_address = fragP->fr_fix + fragP->fr_address;
6d27d3a2 4069
f6e504fe 4070#ifdef IBM_COMPILER_SUX
355afbcd 4071 /* This is wrong but it convinces the native rs6000 compiler to
e284846a 4072 generate the code we want. */
355afbcd
KR		 4073 register char *buffer_address = fragP->fr_literal;
4074 buffer_address += fragP->fr_fix;
f6e504fe 4075#else /* IBM_COMPILER_SUX */
355afbcd
KR		 4076 /* Address in gas core of the place to store the displacement. */
4077 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
f6e504fe 4078#endif /* IBM_COMPILER_SUX */
6d27d3a2 4079
355afbcd 4080 /* No longer true: know(fragP->fr_symbol); */
6d27d3a2 4081
355afbcd
KR		 4082 /* The displacement of the address, from current location. */
4083 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4084 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 4085
355afbcd
KR		 4086 switch (fragP->fr_subtype)
4087 {
4088 case TAB (BCC68000, BYTE):
4089 case TAB (ABRANCH, BYTE):
4090 know (issbyte (disp));
4091 if (disp == 0)
4092 as_bad ("short branch with zero offset: use :w");
4093 fragP->fr_opcode[1] = disp;
4094 ext = 0;
4095 break;
4096 case TAB (DBCC, SHORT):
4097 know (issword (disp));
4098 ext = 2;
4099 break;
4100 case TAB (BCC68000, SHORT):
4101 case TAB (ABRANCH, SHORT):
4102 know (issword (disp));
4103 fragP->fr_opcode[1] = 0x00;
4104 ext = 2;
4105 break;
4106 case TAB (ABRANCH, LONG):
4107 if (cpu_of_arch (current_architecture) < m68020)
4108 {
4109 if (fragP->fr_opcode[0] == 0x61)
4110 {
4111 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4112 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
49864cfa 4113 subseg_change (text_section, 0); /* @@ */
355afbcd
KR		 4114
4115 fix_new (fragP,
4116 fragP->fr_fix,
4117 4,
4118 fragP->fr_symbol,
355afbcd
KR		 4119 fragP->fr_offset,
4120 0,
4121 NO_RELOC);
4122
4123 fragP->fr_fix += 4;
4124 ext = 0;
4125 }
4126 else if (fragP->fr_opcode[0] == 0x60)
4127 {
4128 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4129 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
49864cfa 4130 subseg_change (text_section, 0); /* @@ */
bcb8dff8
KR		 4131 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4132 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4133 fragP->fr_fix += 4;
4134 ext = 0;
4135 }
4136 else
4137 {
4138 as_bad ("Long branch offset not supported.");
4139 }
4140 }
4141 else
4142 {
bcb8dff8 4143 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4144 ext = 4;
4145 }
4146 break;
4147 case TAB (BCC68000, LONG):
4148 /* only Bcc 68000 instructions can come here */
4149 /* change bcc into b!cc/jmp absl long */
4150 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4151 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
6d27d3a2 4152
355afbcd 4153 /* JF: these used to be fr_opcode[2,3], but they may be in a
fecd2382
RP		 4154 different frag, in which case refering to them is a no-no.
4155 Only fr_opcode[0,1] are guaranteed to work. */
355afbcd 4156 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4157 *buffer_address++ = (char) 0xf9;
355afbcd 4158 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 4159 subseg_change (text_section, 0);
bcb8dff8
KR		 4160 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4161 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4162 fragP->fr_fix += 4;
4163 ext = 0;
4164 break;
4165 case TAB (DBCC, LONG):
4166 /* only DBcc 68000 instructions can come here */
4167 /* change dbcc into dbcc/jmp absl long */
4168 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4169 *buffer_address++ = 0x00; /* branch offset = 4 */
4170 *buffer_address++ = 0x04;
4171 *buffer_address++ = 0x60; /* put in bra pc+6 */
4172 *buffer_address++ = 0x06;
4173 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4174 *buffer_address++ = (char) 0xf9;
355afbcd
KR		 4175
4176 fragP->fr_fix += 6; /* account for bra/jmp instructions */
49864cfa 4177 subseg_change (text_section, 0);
bcb8dff8 4178 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
49864cfa 4179 fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4180 fragP->fr_fix += 4;
4181 ext = 0;
4182 break;
4183 case TAB (FBRANCH, SHORT):
4184 know ((fragP->fr_opcode[1] & 0x40) == 0);
4185 ext = 2;
4186 break;
4187 case TAB (FBRANCH, LONG):
4188 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4189 ext = 4;
4190 break;
4191 case TAB (PCREL, SHORT):
4192 ext = 2;
4193 break;
4194 case TAB (PCREL, LONG):
4195 /* The thing to do here is force it to ABSOLUTE LONG, since
f8701a3f 4196 PCREL is really trying to shorten an ABSOLUTE address anyway */
355afbcd 4197 /* JF FOO This code has not been tested */
49864cfa 4198 subseg_change (text_section, 0);
bcb8dff8 4199 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
49864cfa 4200 0, NO_RELOC);
355afbcd 4201 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
bcb8dff8
KR		 4202 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4203 (unsigned) fragP->fr_opcode[0],
4204 (unsigned long) fragP->fr_address);
355afbcd
KR		 4205 fragP->fr_opcode[1] &= ~0x3F;
4206 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4207 fragP->fr_fix += 4;
355afbcd
KR		 4208 ext = 0;
4209 break;
4210 case TAB (PCLEA, SHORT):
49864cfa
KR		 4211 subseg_change (text_section, 0);
4212 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
bcb8dff8 4213 fragP->fr_offset, 1, NO_RELOC);
355afbcd
KR		 4214 fragP->fr_opcode[1] &= ~0x3F;
4215 fragP->fr_opcode[1] |= 0x3A;
4216 ext = 2;
4217 break;
4218 case TAB (PCLEA, LONG):
49864cfa
KR		 4219 subseg_change (text_section, 0);
4220 fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
bcb8dff8 4221 fragP->fr_offset + 2, 1, NO_RELOC);
355afbcd
KR		 4222 *buffer_address++ = 0x01;
4223 *buffer_address++ = 0x70;
4224 fragP->fr_fix += 2;
355afbcd
KR		 4225 ext = 4;
4226 break;
49864cfa 4227 }
355afbcd
KR		 4228
4229 if (ext)
4230 {
4231 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4232 fragP->fr_fix += ext;
49864cfa
KR		 4233 }
4234}
355afbcd 4235
49864cfa
KR		 4236#ifndef BFD_ASSEMBLER
4237
4238void
4239md_convert_frag (headers, fragP)
4240 object_headers *headers;
4241 fragS *fragP;
4242{
4243 md_convert_frag_1 (fragP);
4244}
4245
4246#else
4247
4248void
4249md_convert_frag (abfd, sec, fragP)
4250 bfd *abfd;
4251 asection sec;
4252 fragS *fragP;
4253{
4254 md_convert_frag_1 (fragP);
4255}
4256#endif
355afbcd
KR		 4257
4258/* Force truly undefined symbols to their maximum size, and generally set up
4259 the frag list to be relaxed
4260 */
4261int
4262md_estimate_size_before_relax (fragP, segment)
4263 register fragS *fragP;
4264 segT segment;
4265{
4266 int old_fix;
4267 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4268
4269 old_fix = fragP->fr_fix;
4270
4271 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4272 switch (fragP->fr_subtype)
4273 {
4274
4275 case TAB (ABRANCH, SZ_UNDEF):
4276 {
4277 if ((fragP->fr_symbol != NULL) /* Not absolute */
4278 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4279 {
4280 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4281 break;
4282 }
4283 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4284 {
4285 /* On 68000, or for absolute value, switch to abs long */
4286 /* FIXME, we should check abs val, pick short or long */
4287 if (fragP->fr_opcode[0] == 0x61)
4288 {
4289 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4290 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
49864cfa 4291 subseg_change (text_section, 0);
355afbcd 4292 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4293 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4294 fragP->fr_fix += 4;
4295 frag_wane (fragP);
4296 }
4297 else if (fragP->fr_opcode[0] == 0x60)
4298 {
4299 fragP->fr_opcode[0] = 0x4E;
bcb8dff8 4300 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
49864cfa 4301 subseg_change (text_section, 0);
355afbcd 4302 fix_new (fragP, fragP->fr_fix, 4,
bcb8dff8 4303 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
355afbcd
KR		 4304 fragP->fr_fix += 4;
4305 frag_wane (fragP);
4306 }
4307 else
4308 {
4309 as_warn ("Long branch offset to extern symbol not supported.");
4310 }
4311 }
4312 else
4313 { /* Symbol is still undefined. Make it simple */
4314 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
bcb8dff8 4315 fragP->fr_offset + 4, 1, NO_RELOC);
355afbcd 4316 fragP->fr_fix += 4;
bcb8dff8 4317 fragP->fr_opcode[1] = (char) 0xff;
355afbcd
KR		 4318 frag_wane (fragP);
4319 break;
4320 }
4321
a39116f1 4322 break;
355afbcd 4323 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 4324
355afbcd
KR		 4325 case TAB (FBRANCH, SZ_UNDEF):
4326 {
4327 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4328 {
4329 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4330 fragP->fr_var += 2;
4331 }
4332 else
4333 {
4334 fragP->fr_subtype = TAB (FBRANCH, LONG);
4335 fragP->fr_var += 4;
4336 }
4337 break;
4338 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 4339
355afbcd
KR		 4340 case TAB (PCREL, SZ_UNDEF):
4341 {
4342 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flagseen['l'])
4343 {
4344 fragP->fr_subtype = TAB (PCREL, SHORT);
4345 fragP->fr_var += 2;
4346 }
4347 else
4348 {
4349 fragP->fr_subtype = TAB (PCREL, LONG);
4350 fragP->fr_var += 4;
4351 }
4352 break;
4353 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 4354
355afbcd
KR		 4355 case TAB (BCC68000, SZ_UNDEF):
4356 {
4357 if ((fragP->fr_symbol != NULL)
4358 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4359 {
4360 fragP->fr_subtype = TAB (BCC68000, BYTE);
4361 break;
4362 }
4363 /* only Bcc 68000 instructions can come here */
4364 /* change bcc into b!cc/jmp absl long */
4365 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4366 if (flagseen['l'])
4367 {
4368 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4369 /* JF: these were fr_opcode[2,3] */
4370 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4371 buffer_address[1] = (char) 0xf8;
355afbcd 4372 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 4373 subseg_change (text_section, 0);
bcb8dff8 4374 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4375 fragP->fr_offset, 0, NO_RELOC);
4376 fragP->fr_fix += 2;
4377 }
4378 else
4379 {
4380 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4381 /* JF: these were fr_opcode[2,3] */
4382 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4383 buffer_address[1] = (char) 0xf9;
355afbcd 4384 fragP->fr_fix += 2; /* account for jmp instruction */
49864cfa 4385 subseg_change (text_section, 0);
bcb8dff8 4386 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4387 fragP->fr_offset, 0, NO_RELOC);
4388 fragP->fr_fix += 4;
4389 }
4390 frag_wane (fragP);
4391 break;
4392 } /* case TAB(BCC68000,SZ_UNDEF) */
f8701a3f 4393
355afbcd
KR		 4394 case TAB (DBCC, SZ_UNDEF):
4395 {
4396 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4397 {
4398 fragP->fr_subtype = TAB (DBCC, SHORT);
4399 fragP->fr_var += 2;
4400 break;
4401 }
4402 /* only DBcc 68000 instructions can come here */
4403 /* change dbcc into dbcc/jmp absl long */
4404 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4405 buffer_address[0] = 0x00; /* branch offset = 4 */
4406 buffer_address[1] = 0x04;
4407 buffer_address[2] = 0x60; /* put in bra pc + ... */
4408
4409 if (flagseen['l'])
4410 {
4411 /* JF: these were fr_opcode[5-7] */
4412 buffer_address[3] = 0x04; /* plus 4 */
4413 buffer_address[4] = 0x4e; /* Put in Jump Word */
bcb8dff8 4414 buffer_address[5] = (char) 0xf8;
355afbcd 4415 fragP->fr_fix += 6; /* account for bra/jmp instruction */
49864cfa 4416 subseg_change (text_section, 0);
bcb8dff8 4417 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
355afbcd
KR		 4418 fragP->fr_offset, 0, NO_RELOC);
4419 fragP->fr_fix += 2;
4420 }
4421 else
4422 {
4423 /* JF: these were fr_opcode[5-7] */
4424 buffer_address[3] = 0x06; /* Plus 6 */
4425 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
bcb8dff8 4426 buffer_address[5] = (char) 0xf9;
355afbcd 4427 fragP->fr_fix += 6; /* account for bra/jmp instruction */
49864cfa 4428 subseg_change (text_section, 0);
bcb8dff8 4429 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
355afbcd
KR		 4430 fragP->fr_offset, 0, NO_RELOC);
4431 fragP->fr_fix += 4;
4432 }
6d27d3a2 4433
355afbcd
KR		 4434 frag_wane (fragP);
4435 break;
4436 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 4437
355afbcd
KR		 4438 case TAB (PCLEA, SZ_UNDEF):
4439 {
4440 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment || flagseen['l'])
4441 {
4442 fragP->fr_subtype = TAB (PCLEA, SHORT);
4443 fragP->fr_var += 2;
4444 }
4445 else
4446 {
4447 fragP->fr_subtype = TAB (PCLEA, LONG);
4448 fragP->fr_var += 6;
4449 }
4450 break;
4451 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 4452
355afbcd
KR		 4453 default:
4454 break;
6d27d3a2 4455
355afbcd 4456 } /* switch on subtype looking for SZ_UNDEF's. */
6d27d3a2 4457
355afbcd
KR		 4458 /* now that SZ_UNDEF are taken care of, check others */
4459 switch (fragP->fr_subtype)
4460 {
4461 case TAB (BCC68000, BYTE):
4462 case TAB (ABRANCH, BYTE):
4463 /* We can't do a short jump to the next instruction,
a39116f1 4464 so we force word mode. */
355afbcd
KR		 4465 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4466 fragP->fr_symbol->sy_frag == fragP->fr_next)
4467 {
4468 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4469 fragP->fr_var += 2;
fecd2382 4470 }
355afbcd
KR		 4471 break;
4472 default:
4473 break;
4474 }
4475 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 4476}
4477
4478#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 4479/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 4480 with the byte-order problems of cross-assembly. So as a hack,
4481 I added this mach. dependent ri twiddler. Ugly, but it gets
4482 you there. -KWK */
4483/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 4484 are symbolnum, most sig. byte first. Last byte is broken up with
4485 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4486 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 4487/* Translate the internal relocation information into target-specific
4488 format. */
a79c6033 4489#ifdef comment
fecd2382 4490void
355afbcd
KR		 4491md_ri_to_chars (the_bytes, ri)
4492 char *the_bytes;
4493 struct reloc_info_generic *ri;
fecd2382 4494{
355afbcd
KR		 4495 /* this is easy */
4496 md_number_to_chars (the_bytes, ri->r_address, 4);
4497 /* now the fun stuff */
4498 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4499 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4500 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4501 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4502 ((ri->r_extern << 4) & 0x10));
fecd2382 4503}
355afbcd 4504
a79c6033
RP		 4505#endif /* comment */
4506
49864cfa 4507#ifndef BFD_ASSEMBLER
355afbcd
KR		 4508void
4509tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4510 char *where;
4511 fixS *fixP;
4512 relax_addressT segment_address_in_file;
a79c6033 4513{
355afbcd 4514 /*
1404ef23
KR		 4515 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4516 * Out: GNU LD relocation length code: 0, 1, or 2.
4517 */
6d27d3a2 4518
1404ef23 4519 static CONST unsigned char nbytes_r_length[] =
355afbcd
KR		 4520 {42, 0, 1, 42, 2};
4521 long r_symbolnum;
6d27d3a2 4522
355afbcd 4523 know (fixP->fx_addsy != NULL);
6d27d3a2 4524
355afbcd
KR		 4525 md_number_to_chars (where,
4526 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4527 4);
6d27d3a2 4528
355afbcd
KR		 4529 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4530 ? S_GET_TYPE (fixP->fx_addsy)
4531 : fixP->fx_addsy->sy_number);
6d27d3a2 4532
355afbcd
KR		 4533 where[4] = (r_symbolnum >> 16) & 0x0ff;
4534 where[5] = (r_symbolnum >> 8) & 0x0ff;
4535 where[6] = r_symbolnum & 0x0ff;
4536 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4537 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
6d27d3a2 4538
355afbcd 4539 return;
49864cfa
KR		 4540}
4541#endif
a79c6033 4542
fecd2382
RP		 4543#endif /* OBJ_AOUT or OBJ_BOUT */
4544
4545#ifndef WORKING_DOT_WORD
49864cfa
KR		 4546CONST int md_short_jump_size = 4;
4547CONST int md_long_jump_size = 6;
fecd2382
RP		 4548
4549void
355afbcd
KR		 4550md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4551 char *ptr;
025b0302 4552 addressT from_addr, to_addr;
355afbcd
KR		 4553 fragS *frag;
4554 symbolS *to_symbol;
fecd2382 4555{
025b0302 4556 valueT offset;
6d27d3a2 4557
355afbcd 4558 offset = to_addr - (from_addr + 2);
6d27d3a2 4559
025b0302
ME		 4560 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4561 md_number_to_chars (ptr + 2, (valueT) offset, 2);
fecd2382
RP		 4562}
4563
4564void
355afbcd
KR		 4565md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4566 char *ptr;
025b0302 4567 addressT from_addr, to_addr;
355afbcd
KR		 4568 fragS *frag;
4569 symbolS *to_symbol;
fecd2382 4570{
025b0302 4571 valueT offset;
355afbcd
KR		 4572
4573 if (cpu_of_arch (current_architecture) < m68020)
4574 {
4575 offset = to_addr - S_GET_VALUE (to_symbol);
025b0302
ME		 4576 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4577 md_number_to_chars (ptr + 2, (valueT) offset, 4);
bcb8dff8
KR		 4578 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4579 0, NO_RELOC);
355afbcd
KR		 4580 }
4581 else
4582 {
4583 offset = to_addr - (from_addr + 2);
025b0302
ME		 4584 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4585 md_number_to_chars (ptr + 2, (valueT) offset, 4);
355afbcd 4586 }
fecd2382
RP		 4587}
4588
4589#endif
4590/* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
6d27d3a2 4591
a39116f1
RP		 4592 0: Everything is OK
4593 10: Absolute 1:8 only
4594 20: Absolute 0:7 only
4595 30: absolute 0:15 only
4596 40: Absolute 0:31 only
4597 50: absolute 0:127 only
4598 55: absolute -64:63 only
4599 60: absolute -128:127 only
4600 70: absolute 0:4095 only
4601 80: No bignums
6d27d3a2 4602
a39116f1 4603 */
fecd2382 4604
355afbcd
KR		 4605static int
4606get_num (exp, ok)
4607 struct m68k_exp *exp;
4608 int ok;
fecd2382
RP		 4609{
4610#ifdef TEST2
355afbcd 4611 long l = 0;
6d27d3a2 4612
355afbcd
KR		 4613 if (!exp->e_beg)
4614 return 0;
4615 if (*exp->e_beg == '0')
4616 {
4617 if (exp->e_beg[1] == 'x')
4618 sscanf (exp->e_beg + 2, "%x", &l);
4619 else
4620 sscanf (exp->e_beg + 1, "%O", &l);
4621 return l;
4622 }
4623 return atol (exp->e_beg);
fecd2382 4624#else
355afbcd
KR		 4625 char *save_in;
4626 char c_save;
49864cfa 4627 segT section;
6d27d3a2 4628
355afbcd
KR		 4629 if (!exp)
4630 {
4631 /* Can't do anything */
4632 return 0;
4633 }
4634 if (!exp->e_beg || !exp->e_end)
4635 {
49864cfa 4636 seg (exp) = absolute_section;
355afbcd
KR		 4637 adds (exp) = 0;
4638 subs (exp) = 0;
4639 offs (exp) = (ok == 10) ? 1 : 0;
4640 as_warn ("Null expression defaults to %ld", offs (exp));
4641 return 0;
4642 }
6d27d3a2 4643
355afbcd
KR		 4644 exp->e_siz = 0;
4645 if ( /* ok!=80 && */ (exp->e_end[-1] == ':' || exp->e_end[-1] == '.')
4646 && (exp->e_end - exp->e_beg) >= 2)
4647 {
4648 switch (exp->e_end[0])
4649 {
4650 case 's':
4651 case 'S':
4652 case 'b':
4653 case 'B':
4654 exp->e_siz = 1;
4655 exp->e_end -= 2;
4656 break;
4657 case 'w':
4658 case 'W':
4659 exp->e_siz = 2;
4660 exp->e_end -= 2;
4661 break;
4662 case 'l':
4663 case 'L':
4664 exp->e_siz = 3;
4665 exp->e_end -= 2;
4666 break;
4667 default:
4668 if (exp->e_end[-1] == ':')
4669 as_bad ("Unknown size for expression \"%c\"", exp->e_end[0]);
4670 break;
fecd2382 4671 }
355afbcd
KR		 4672 }
4673 c_save = exp->e_end[1];
4674 exp->e_end[1] = '\0';
4675 save_in = input_line_pointer;
4676 input_line_pointer = exp->e_beg;
49864cfa 4677 section = expression (&exp->e_exp);
bcb8dff8
KR		 4678 seg (exp) = section;
4679 if (exp->e_exp.X_op == O_absent)
49864cfa 4680 {
355afbcd 4681 /* Do the same thing the VAX asm does */
49864cfa 4682 seg (exp) = absolute_section;
bcb8dff8 4683 op (exp) = O_constant;
355afbcd
KR		 4684 adds (exp) = 0;
4685 subs (exp) = 0;
4686 offs (exp) = 0;
4687 if (ok == 10)
4688 {
4689 as_warn ("expression out of range: defaulting to 1");
4690 offs (exp) = 1;
4691 }
49864cfa 4692 }
bcb8dff8 4693 else if (exp->e_exp.X_op == O_constant)
49864cfa 4694 {
355afbcd
KR		 4695 switch (ok)
4696 {
4697 case 10:
4698 if (offs (exp) < 1 || offs (exp) > 8)
4699 {
4700 as_warn ("expression out of range: defaulting to 1");
4701 offs (exp) = 1;
4702 }
4703 break;
4704 case 20:
4705 if (offs (exp) < 0 || offs (exp) > 7)
4706 goto outrange;
4707 break;
4708 case 30:
4709 if (offs (exp) < 0 || offs (exp) > 15)
4710 goto outrange;
4711 break;
4712 case 40:
4713 if (offs (exp) < 0 || offs (exp) > 32)
4714 goto outrange;
4715 break;
4716 case 50:
4717 if (offs (exp) < 0 || offs (exp) > 127)
4718 goto outrange;
4719 break;
4720 case 55:
4721 if (offs (exp) < -64 || offs (exp) > 63)
4722 goto outrange;
4723 break;
4724 case 60:
4725 if (offs (exp) < -128 || offs (exp) > 127)
4726 goto outrange;
4727 break;
4728 case 70:
4729 if (offs (exp) < 0 || offs (exp) > 4095)
4730 {
4731 outrange:
4732 as_warn ("expression out of range: defaulting to 0");
4733 offs (exp) = 0;
4734 }
4735 break;
fecd2382 4736 default:
355afbcd
KR		 4737 break;
4738 }
49864cfa 4739 }
bcb8dff8 4740 else if (exp->e_exp.X_op == O_big)
49864cfa 4741 {
bcb8dff8 4742 if (offs (exp) <= 0 /* flonum */
355afbcd
KR		 4743 && (ok == 80 /* no bignums */
4744 || (ok > 10 /* small-int ranges including 0 ok */
1404ef23
KR		 4745 /* If we have a flonum zero, a zero integer should
4746 do as well (e.g., in moveq). */
355afbcd
KR		 4747 && generic_floating_point_number.exponent == 0
4748 && generic_floating_point_number.low[0] == 0)))
4749 {
4750 /* HACK! Turn it into a long */
4751 LITTLENUM_TYPE words[6];
4752
4753 gen_to_words (words, 2, 8L); /* These numbers are magic! */
49864cfa 4754 seg (exp) = absolute_section;
bcb8dff8 4755 op (exp) = O_constant;
355afbcd
KR		 4756 adds (exp) = 0;
4757 subs (exp) = 0;
4758 offs (exp) = words[1] | (words[0] << 16);
4759 }
4760 else if (ok != 0)
4761 {
49864cfa 4762 seg (exp) = absolute_section;
bcb8dff8 4763 op (exp) = O_constant;
355afbcd
KR		 4764 adds (exp) = 0;
4765 subs (exp) = 0;
4766 offs (exp) = (ok == 10) ? 1 : 0;
4767 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4768 }
49864cfa
KR		 4769 }
4770 else
4771 {
355afbcd
KR		 4772 if (ok >= 10 && ok <= 70)
4773 {
49864cfa 4774 seg (exp) = absolute_section;
bcb8dff8 4775 op (exp) = O_constant;
355afbcd
KR		 4776 adds (exp) = 0;
4777 subs (exp) = 0;
4778 offs (exp) = (ok == 10) ? 1 : 0;
4779 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp->e_beg, offs (exp));
4780 }
355afbcd 4781 }
49864cfa 4782
355afbcd
KR		 4783 if (input_line_pointer != exp->e_end + 1)
4784 as_bad ("Ignoring junk after expression");
4785 exp->e_end[1] = c_save;
4786 input_line_pointer = save_in;
4787 if (exp->e_siz)
4788 {
4789 switch (exp->e_siz)
4790 {
4791 case 1:
4792 if (!isbyte (offs (exp)))
4793 as_warn ("expression doesn't fit in BYTE");
4794 break;
4795 case 2:
4796 if (!isword (offs (exp)))
4797 as_warn ("expression doesn't fit in WORD");
4798 break;
a39116f1 4799 }
355afbcd
KR		 4800 }
4801 return offs (exp);
fecd2382 4802#endif
49864cfa 4803}
fecd2382
RP		 4804
4805/* These are the back-ends for the various machine dependent pseudo-ops. */
355afbcd 4806void demand_empty_rest_of_line (); /* Hate those extra verbose names */
fecd2382 4807
355afbcd 4808static void
bcb8dff8
KR		 4809s_data1 (ignore)
4810 int ignore;
355afbcd 4811{
bcb8dff8 4812 subseg_set (data_section, 1);
355afbcd 4813 demand_empty_rest_of_line ();
49864cfa 4814}
fecd2382 4815
355afbcd 4816static void
bcb8dff8
KR		 4817s_data2 (ignore)
4818 int ignore;
355afbcd 4819{
bcb8dff8 4820 subseg_set (data_section, 2);
355afbcd 4821 demand_empty_rest_of_line ();
49864cfa 4822}
fecd2382 4823
355afbcd 4824static void
bcb8dff8
KR		 4825s_bss (ignore)
4826 int ignore;
a1765cf0 4827{
355afbcd 4828 /* We don't support putting frags in the BSS segment, we fake it
49864cfa 4829 by marking in_bss, then looking at s_skip for clues. */
a1765cf0 4830
bcb8dff8 4831 subseg_set (bss_section, 0);
355afbcd 4832 demand_empty_rest_of_line ();
49864cfa 4833}
6d27d3a2 4834
355afbcd 4835static void
bcb8dff8
KR		 4836s_even (ignore)
4837 int ignore;
355afbcd
KR		 4838{
4839 register int temp;
4840 register long temp_fill;
4841
4842 temp = 1; /* JF should be 2? */
4843 temp_fill = get_absolute_expression ();
4844 if (!need_pass_2) /* Never make frag if expect extra pass. */
4845 frag_align (temp, (int) temp_fill);
4846 demand_empty_rest_of_line ();
49864cfa 4847}
355afbcd
KR		 4848
4849static void
bcb8dff8
KR		 4850s_proc (ignore)
4851 int ignore;
355afbcd
KR		 4852{
4853 demand_empty_rest_of_line ();
49864cfa 4854}
fecd2382
RP		 4855
4856/* s_space is defined in read.c .skip is simply an alias to it. */
4857
7c15cbe8
RP		 4858/*
4859 * md_parse_option
4860 * Invocation line includes a switch not recognized by the base assembler.
4861 * See if it's a processor-specific option. These are:
4862 *
4863 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4864 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4865 * Select the architecture. Instructions or features not
4866 * supported by the selected architecture cause fatal
4867 * errors. More than one may be specified. The default is
4868 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4869 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 4870 * -[A]m[c]no-68851, -[A]m[c]no-68881
4871 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4872 * so don't use or document it, but that's the way the parsing
4873 * works).
7c15cbe8 4874 *
dff60b7d
ILT		 4875 * -pic Indicates PIC.
4876 * -k Indicates PIC. (Sun 3 only.)
b80d39a0 4877 *
a39116f1
RP		 4878 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4879 * (e.g. m68020) also requests that float instructions be included. This
4880 * is the default setup, mostly to avoid hassling users. A better
4881 * rearrangement of this structure would be to add an option to DENY
4882 * floating point opcodes, for people who want to really know there's none
4883 * of that funny floaty stuff going on. FIXME-later.
7c15cbe8 4884 */
a39116f1 4885#ifndef MAYBE_FLOAT_TOO
355afbcd 4886#define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
a39116f1 4887#endif
7c15cbe8 4888
355afbcd
KR		 4889int
4890md_parse_option (argP, cntP, vecP)
4891 char **argP;
4892 int *cntP;
4893 char ***vecP;
fecd2382 4894{
355afbcd
KR		 4895 switch (**argP)
4896 {
4897 case 'l': /* -l means keep external to 2 bit offset
e284846a 4898 rather than 16 bit one */
355afbcd 4899 break;
6d27d3a2 4900
e284846a
KR		 4901 case 'S': /* -S means that jbsr's always turn into
4902 jsr's. */
355afbcd 4903 break;
6d27d3a2 4904
355afbcd
KR		 4905 case 'A':
4906 (*argP)++;
4907 /* intentional fall-through */
4908 case 'm':
4909 (*argP)++;
4910
4911 if (**argP == 'c')
4912 {
4913 (*argP)++;
4914 } /* allow an optional "c" */
4915
4916 if (!strcmp (*argP, "68000")
e284846a
KR		 4917 || !strcmp (*argP, "68008")
4918 || !strcmp (*argP, "68302"))
355afbcd
KR		 4919 {
4920 current_architecture |= m68000;
4921 }
4922 else if (!strcmp (*argP, "68010"))
4923 {
355afbcd 4924 current_architecture |= m68010;
355afbcd
KR		 4925 }
4926 else if (!strcmp (*argP, "68020"))
4927 {
4928 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
355afbcd
KR		 4929 }
4930 else if (!strcmp (*argP, "68030"))
4931 {
4932 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
355afbcd
KR		 4933 }
4934 else if (!strcmp (*argP, "68040"))
4935 {
4936 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
355afbcd 4937 }
e284846a 4938#ifndef NO_68881
355afbcd
KR		 4939 else if (!strcmp (*argP, "68881"))
4940 {
4941 current_architecture |= m68881;
355afbcd
KR		 4942 }
4943 else if (!strcmp (*argP, "68882"))
4944 {
4945 current_architecture |= m68882;
355afbcd 4946 }
e284846a
KR		 4947#endif /* NO_68881 */
4948 /* Even if we aren't configured to support the processor,
4949 it should still be possible to assert that the user
4950 doesn't have it... */
355afbcd
KR		 4951 else if (!strcmp (*argP, "no-68881")
4952 || !strcmp (*argP, "no-68882"))
4953 {
4954 no_68881 = 1;
355afbcd 4955 }
e284846a 4956#ifndef NO_68851
355afbcd
KR		 4957 else if (!strcmp (*argP, "68851"))
4958 {
4959 current_architecture |= m68851;
355afbcd 4960 }
e284846a 4961#endif /* NO_68851 */
355afbcd
KR		 4962 else if (!strcmp (*argP, "no-68851"))
4963 {
4964 no_68851 = 1;
4965 }
e284846a
KR		 4966 else if (!strcmp (*argP, "pu32") /* "cpu32" minus 'c' */
4967 || !strcmp (*argP, "68331")
4968 || !strcmp (*argP, "68332")
4969 || !strcmp (*argP, "68333")
4970 || !strcmp (*argP, "68340"))
4971 {
355afbcd
KR		 4972 current_architecture |= cpu32;
4973 }
4974 else
4975 {
4976 as_warn ("Unknown architecture, \"%s\". option ignored", *argP);
4977 } /* switch on architecture */
6d27d3a2 4978
355afbcd
KR		 4979 while (**argP)
4980 (*argP)++;
6d27d3a2 4981
355afbcd 4982 break;
6d27d3a2 4983
355afbcd
KR		 4984 case 'p':
4985 if (!strcmp (*argP, "pic"))
4986 {
dff60b7d
ILT		 4987 *argP += 3;
4988 flag_want_pic = 1;
355afbcd 4989 break; /* -pic, Position Independent Code */
f8701a3f 4990 }
355afbcd 4991 else
dff60b7d
ILT		 4992 goto bad_arg;
4993
4994#ifdef TE_SUN3
4995 case 'k':
4996 flag_want_pic = 1;
4997 break;
4998#endif
355afbcd
KR		 4999
5000 default:
dff60b7d 5001 bad_arg:
355afbcd
KR		 5002 return 0;
5003 }
5004 return 1;
fecd2382
RP		 5005}
5006
5007
5008#ifdef TEST2
5009
5010/* TEST2: Test md_assemble() */
5011/* Warning, this routine probably doesn't work anymore */
5012
355afbcd 5013main ()
fecd2382 5014{
355afbcd
KR		 5015 struct m68k_it the_ins;
5016 char buf[120];
5017 char *cp;
5018 int n;
5019
5020 m68k_ip_begin ();
5021 for (;;)
5022 {
5023 if (!gets (buf) || !*buf)
5024 break;
5025 if (buf[0] == '|' || buf[1] == '.')
5026 continue;
5027 for (cp = buf; *cp; cp++)
5028 if (*cp == '\t')
5029 *cp = ' ';
5030 if (is_label (buf))
5031 continue;
5032 memset (&the_ins, '\0', sizeof (the_ins));
5033 m68k_ip (&the_ins, buf);
5034 if (the_ins.error)
5035 {
5036 printf ("Error %s in %s\n", the_ins.error, buf);
5037 }
5038 else
5039 {
5040 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5041 for (n = 0; n < the_ins.numo; n++)
5042 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5043 printf (" ");
5044 print_the_insn (&the_ins.opcode[0], stdout);
5045 (void) putchar ('\n');
5046 }
5047 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5048 {
5049 if (the_ins.operands[n].error)
5050 {
5051 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5052 continue;
5053 }
5054 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5055 if (the_ins.operands[n].b_const)
5056 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5057 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5058 if (the_ins.operands[n].b_iadd)
5059 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5060 (void) putchar ('\n');
a39116f1 5061 }
355afbcd
KR		 5062 }
5063 m68k_ip_end ();
5064 return 0;
fecd2382
RP		 5065}
5066
355afbcd
KR		 5067is_label (str)
5068 char *str;
fecd2382 5069{
355afbcd
KR		 5070 while (*str == ' ')
5071 str++;
5072 while (*str && *str != ' ')
5073 str++;
5074 if (str[-1] == ':' || str[1] == '=')
5075 return 1;
5076 return 0;
fecd2382
RP		 5077}
5078
5079#endif
5080
5081/* Possible states for relaxation:
6d27d3a2 5082
a39116f1
RP		 5083 0 0 branch offset byte (bra, etc)
5084 0 1 word
5085 0 2 long
6d27d3a2 5086
a39116f1
RP		 5087 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5088 1 1 word
5089 1 2 long
6d27d3a2 5090
a39116f1
RP		 5091 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5092 2 1 word-long
5093 2 2 long-word
5094 2 3 long-long
6d27d3a2 5095
a39116f1 5096 */
fecd2382 5097
fecd2382
RP		 5098/* We have no need to default values of symbols. */
5099
5100/* ARGSUSED */
5101symbolS *
355afbcd
KR		 5102md_undefined_symbol (name)
5103 char *name;
fecd2382 5104{
355afbcd 5105 return 0;
fecd2382
RP		 5106}
5107
6d27d3a2 5108/* Parse an operand that is machine-specific.
fecd2382
RP		 5109 We just return without modifying the expression if we have nothing
5110 to do. */
5111
5112/* ARGSUSED */
5113void
355afbcd
KR		 5114md_operand (expressionP)
5115 expressionS *expressionP;
fecd2382
RP		 5116{
5117}
5118
5119/* Round up a section size to the appropriate boundary. */
025b0302 5120valueT
355afbcd
KR		 5121md_section_align (segment, size)
5122 segT segment;
025b0302 5123 valueT size;
fecd2382 5124{
355afbcd 5125 return size; /* Byte alignment is fine */
fecd2382
RP		 5126}
5127
5128/* Exactly what point is a PC-relative offset relative TO?
5129 On the 68k, they're relative to the address of the offset, plus
5130 its size. (??? Is this right? FIXME-SOON!) */
5131long
355afbcd
KR		 5132md_pcrel_from (fixP)
5133 fixS *fixP;
fecd2382 5134{
355afbcd 5135 return (fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
fecd2382
RP		 5136}
5137
49864cfa 5138#ifndef BFD_ASSEMBLER
355afbcd 5139void
3ad9ec6a
ILT		 5140tc_coff_symbol_emit_hook ()
5141{
5142}
5143
355afbcd
KR		 5144int
5145tc_coff_sizemachdep (frag)
5146 fragS *frag;
3ad9ec6a 5147{
355afbcd
KR		 5148 switch (frag->fr_subtype & 0x3)
5149 {
5150 case BYTE:
5151 return 1;
5152 case SHORT:
5153 return 2;
5154 case LONG:
5155 return 4;
5156 default:
5157 abort ();
5158 }
3ad9ec6a 5159}
49864cfa 5160#endif
355afbcd 5161
fecd2382 5162/* end of tc-m68k.c */
GDB Binutils - Deliverables
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