projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Ran "indent", for GNU coding style; some code & comments still need fixup.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
a87b3269 1/* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
fecd2382 2 slow to compile, easy to find file.
6d27d3a2 3
a87b3269 4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
6d27d3a2 5
a39116f1 6 This file is part of GAS, the GNU Assembler.
6d27d3a2 7
a39116f1
RP		 8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
6d27d3a2 12
a39116f1
RP		 13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
6d27d3a2 17
a39116f1
RP		 18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
fecd2382
RP		 21
22#include <ctype.h>
f8701a3f 23#define NO_RELOC 0
fecd2382 24#include "as.h"
3ad9ec6a 25#include "read.h"
fecd2382
RP		 26
27#include "obstack.h"
28
a39116f1 29/* note that this file includes real declarations and thus can only be included by one source file per executable. */
e0982afe 30#include "opcode/m68k.h"
3ad9ec6a 31
f6e504fe
RP		 32#ifdef TE_SUN
33/* This variable contains the value to write out at the beginning of
34 the a.out file. The 2<<16 means that this is a 68020 file instead
35 of an old-style 68000 file */
36
37long omagic = 2<<16|OMAGIC; /* Magic byte for header file */
38#else
39long omagic = OMAGIC;
40#endif
fecd2382
RP		 41
42/* This array holds the chars that always start a comment. If the
43 pre-processor is disabled, these aren't very useful */
44const char comment_chars[] = "|";
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
53const char line_comment_chars[] = "#";
54
587c4264
ILT		 55const char line_separator_chars[] = "";
56
fecd2382
RP		 57/* Chars that can be used to separate mant from exp in floating point nums */
58const char EXP_CHARS[] = "eE";
59
60/* Chars that mean this number is a floating point constant */
61/* As in 0f12.456 */
62/* or 0d1.2345e12 */
63
64const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
65
66/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here.
a39116f1 69 */
fecd2382
RP		 70
71int md_reloc_size = 8; /* Size of relocation record */
72
73/* Its an arbitrary name: This means I don't approve of it */
74/* See flames below */
75static struct obstack robyn;
76
77#define TAB(x,y) (((x)<<2)+(y))
78#define TABTYPE(xy) ((xy) >> 2)
79#define BYTE 0
80#define SHORT 1
81#define LONG 2
82#define SZ_UNDEF 3
3ad9ec6a
ILT		 83#undef BRANCH
84#define ABRANCH 1
fecd2382
RP		 85#define FBRANCH 2
86#define PCREL 3
87#define BCC68000 4
88#define DBCC 5
89#define PCLEA 6
90
f6e504fe 91/* Operands we can parse: (And associated modes)
6d27d3a2 92
a39116f1
RP		 93 numb: 8 bit num
94 numw: 16 bit num
95 numl: 32 bit num
96 dreg: data reg 0-7
97 reg: address or data register
98 areg: address register
99 apc: address register, PC, ZPC or empty string
100 num: 16 or 32 bit num
101 num2: like num
102 sz: w or l if omitted, l assumed
103 scale: 1 2 4 or 8 if omitted, 1 assumed
6d27d3a2 104
a39116f1
RP		 105 7.4 IMMED #num --> NUM
106 0.? DREG dreg --> dreg
107 1.? AREG areg --> areg
108 2.? AINDR areg@ --> *(areg)
109 3.? AINC areg@+ --> *(areg++)
110 4.? ADEC areg@- --> *(--areg)
111 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
112 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
113 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
114 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
115 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
116 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
117 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
118 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
119 7.0 ABSL num:sz --> *(num)
120 num --> *(num) (sz L assumed)
121 *** MSCR otherreg --> Magic
122 With -l option
123 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
c50140c8 124 ?.? DINDR dreg@ --> (dreg) -- cas2 only
6d27d3a2 125
a39116f1
RP		 126 examples:
127 #foo #0x35 #12
128 d2
129 a4
130 a3@
131 a5@+
132 a6@-
133 a2@(12) pc@(14)
134 a1@(5,d2:w:1) @(45,d6:l:4)
135 pc@(a2) @(d4)
136 etc . . .
6d27d3a2
KR		 137
138
a39116f1
RP		 139 #name@(numw) -->turn into PC rel mode
140 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
6d27d3a2 141
a39116f1 142 */
f6e504fe
RP		 143
144enum operand_type {
f8701a3f
SC		 145 IMMED = 1,
146 DREG,
147 AREG,
148 AINDR,
149 ADEC,
150 AINC,
151 AOFF,
152 AINDX,
153 APODX,
154 AMIND,
155 APRDX,
156 ABSL,
157 MSCR,
158 REGLST,
c50140c8 159 DINDR
f6e504fe
RP		 160};
161
162
fecd2382 163struct m68k_exp {
f8701a3f
SC		 164 char *e_beg;
165 char *e_end;
166 expressionS e_exp;
167 short e_siz; /* 0== default 1==short/byte 2==word 3==long */
fecd2382
RP		 168};
169
7c15cbe8
RP		 170/* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
171 8-15==addr reg for operands that take both types */
172
173enum _register {
f8701a3f
SC		 174 DATA = 1, /* 1- 8 == data registers 0-7 */
175 DATA0 = DATA,
176 DATA1,
177 DATA2,
178 DATA3,
179 DATA4,
180 DATA5,
181 DATA6,
182 DATA7,
6d27d3a2 183
f8701a3f
SC		 184 ADDR,
185 ADDR0 = ADDR,
186 ADDR1,
187 ADDR2,
188 ADDR3,
189 ADDR4,
190 ADDR5,
191 ADDR6,
192 ADDR7,
6d27d3a2 193
f8701a3f
SC		 194 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
195 /* I think. . . */
6d27d3a2 196
f8701a3f 197 SP = ADDR7,
6d27d3a2 198
f8701a3f
SC		 199 FPREG, /* Eight FP registers */
200 FP0 = FPREG,
201 FP1,
202 FP2,
203 FP3,
204 FP4,
205 FP5,
206 FP6,
207 FP7,
208 COPNUM = (FPREG+8), /* Co-processor #1-#8 */
209 COP0 = COPNUM,
210 COP1,
211 COP2,
212 COP3,
213 COP4,
214 COP5,
215 COP6,
216 COP7,
217 PC, /* Program counter */
218 ZPC, /* Hack for Program space, but 0 addressing */
219 SR, /* Status Reg */
220 CCR, /* Condition code Reg */
6d27d3a2 221
f8701a3f
SC		 222 /* These have to be in order for the movec instruction to work. */
223 USP, /* User Stack Pointer */
224 ISP, /* Interrupt stack pointer */
225 SFC,
226 DFC,
227 CACR,
228 VBR,
229 CAAR,
230 MSP,
231 ITT0,
232 ITT1,
233 DTT0,
234 DTT1,
235 MMUSR,
236 TC,
237 SRP,
238 URP,
239 /* end of movec ordering constraints */
6d27d3a2 240
f8701a3f
SC		 241 FPI,
242 FPS,
243 FPC,
6d27d3a2 244
4134a793 245 DRP, /* 68851 or 68030 MMU regs */
f8701a3f
SC		 246 CRP,
247 CAL,
248 VAL,
249 SCC,
250 AC,
251 BAD,
252 BAD0 = BAD,
253 BAD1,
254 BAD2,
255 BAD3,
256 BAD4,
257 BAD5,
258 BAD6,
259 BAD7,
260 BAC,
261 BAC0 = BAC,
262 BAC1,
263 BAC2,
264 BAC3,
265 BAC4,
266 BAC5,
267 BAC6,
268 BAC7,
4134a793
KR		 269 PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040)
270 and ACUSR on 68ec030 */
f8701a3f 271 PCSR,
6d27d3a2 272
f8701a3f
SC		 273 IC, /* instruction cache token */
274 DC, /* data cache token */
275 NC, /* no cache token */
276 BC, /* both caches token */
6d27d3a2 277
4134a793
KR		 278 TT0, /* 68030 access control unit regs */
279 TT1,
7c15cbe8
RP		 280};
281
fecd2382
RP		 282/* Internal form of an operand. */
283struct m68k_op {
f8701a3f
SC		 284 char *error; /* Couldn't parse it */
285 enum operand_type mode; /* What mode this instruction is in. */
286 enum _register reg; /* Base register */
287 struct m68k_exp *con1;
288 int ireg; /* Index register */
289 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */
290 int imul; /* Multipy ireg by this (1,2,4,or 8) */
291 struct m68k_exp *con2;
fecd2382
RP		 292};
293
294/* internal form of a 68020 instruction */
7c15cbe8 295struct m68k_it {
f8701a3f
SC		 296 char *error;
297 char *args; /* list of opcode info */
298 int numargs;
6d27d3a2 299
f8701a3f
SC		 300 int numo; /* Number of shorts in opcode */
301 short opcode[11];
6d27d3a2 302
f8701a3f 303 struct m68k_op operands[6];
6d27d3a2 304
f8701a3f
SC		 305 int nexp; /* number of exprs in use */
306 struct m68k_exp exprs[4];
6d27d3a2 307
f8701a3f
SC		 308 int nfrag; /* Number of frags we have to produce */
309 struct {
310 int fragoff; /* Where in the current opcode[] the frag ends */
311 symbolS *fadd;
312 long foff;
313 int fragty;
314 } fragb[4];
6d27d3a2 315
f8701a3f
SC		 316 int nrel; /* Num of reloc strucs in use */
317 struct {
318 int n;
319 symbolS *add,
320 *sub;
321 long off;
322 char wid;
323 char pcrel;
324 } reloc[5]; /* Five is enough??? */
fecd2382
RP		 325};
326
865a2edf
MT		 327#define cpu_of_arch(x) ((x) & m68000up)
328#define float_of_arch(x) ((x) & mfloat)
329#define mmu_of_arch(x) ((x) & mmmu)
330
7c15cbe8 331static struct m68k_it the_ins; /* the instruction being assembled */
fecd2382 332
7c15cbe8 333/* Macros for adding things to the m68k_it struct */
fecd2382
RP		 334
335#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
336
337/* Like addword, but goes BEFORE general operands */
338#define insop(w) {int z;\
a39116f1
RP		 339 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
340 the_ins.opcode[z]=the_ins.opcode[z-1];\
341 for(z=0;z<the_ins.nrel;z++)\
342 the_ins.reloc[z].n+=2;\
343 the_ins.opcode[opcode->m_codenum]=w;\
344 the_ins.numo++;\
f8701a3f 345 }
fecd2382
RP		 346
347
348#define add_exp(beg,end) (\
a39116f1
RP		 349 the_ins.exprs[the_ins.nexp].e_beg=beg,\
350 the_ins.exprs[the_ins.nexp].e_end=end,\
351 &the_ins.exprs[the_ins.nexp++]\
352 )
fecd2382
RP		 353
354
355/* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
356#define add_fix(width,exp,pc_rel) {\
a39116f1
RP		 357 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
358 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
359 the_ins.reloc[the_ins.nrel].add=adds((exp));\
360 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
361 the_ins.reloc[the_ins.nrel].off=offs((exp));\
362 the_ins.reloc[the_ins.nrel].wid=width;\
363 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
f8701a3f 364 }
fecd2382
RP		 365
366#define add_frag(add,off,type) {\
a39116f1
RP		 367 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
368 the_ins.fragb[the_ins.nfrag].fadd=add;\
369 the_ins.fragb[the_ins.nfrag].foff=off;\
370 the_ins.fragb[the_ins.nfrag++].fragty=type;\
f8701a3f 371 }
fecd2382
RP		 372
373#define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
374
375#define seg(exp) ((exp)->e_exp.X_seg)
376#define adds(exp) ((exp)->e_exp.X_add_symbol)
377#define subs(exp) ((exp)->e_exp.X_subtract_symbol)
378#define offs(exp) ((exp)->e_exp.X_add_number)
379
380
7c15cbe8 381struct m68k_incant {
f8701a3f
SC		 382 char *m_operands;
383 unsigned long m_opcode;
384 short m_opnum;
385 short m_codenum;
df3768fb 386 int m_arch;
f8701a3f 387 struct m68k_incant *m_next;
fecd2382
RP		 388};
389
3ad9ec6a
ILT		 390
391
fecd2382
RP		 392#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
393#define gettwo(x) (((x)->m_opcode)&0xffff)
394
395
a87b3269 396#if __STDC__ == 1
fecd2382
RP		 397
398static char *crack_operand(char *str, struct m68k_op *opP);
399static int get_num(struct m68k_exp *exp, int ok);
400static int get_regs(int i, char *str, struct m68k_op *opP);
401static int reverse_16_bits(int in);
402static int reverse_8_bits(int in);
403static int try_index(char **s, struct m68k_op *opP);
404static void install_gen_operand(int mode, int val);
405static void install_operand(int mode, int val);
3ad9ec6a 406static void s_bss(void);
fecd2382
RP		 407static void s_data1(void);
408static void s_data2(void);
409static void s_even(void);
410static void s_proc(void);
411
a87b3269 412#else /* not __STDC__ */
fecd2382
RP		 413
414static char *crack_operand();
415static int get_num();
416static int get_regs();
417static int reverse_16_bits();
418static int reverse_8_bits();
419static int try_index();
420static void install_gen_operand();
421static void install_operand();
3ad9ec6a 422static void s_bss();
9e43698e 423void s_align_bytes();
fecd2382
RP		 424static void s_data1();
425static void s_data2();
426static void s_even();
427static void s_proc();
428
a87b3269 429#endif /* not __STDC__ */
fecd2382 430
df3768fb 431static int current_architecture = 0;
7c15cbe8 432
fecd2382
RP		 433/* BCC68000 is for patching in an extra jmp instruction for long offsets
434 on the 68000. The 68000 doesn't support long branches with branchs */
435
436/* This table desribes how you change sizes for the various types of variable
437 size expressions. This version only supports two kinds. */
438
439/* Note that calls to frag_var need to specify the maximum expansion needed */
440/* This is currently 10 bytes for DBCC */
441
442/* The fields are:
a39116f1
RP		 443 How far Forward this mode will reach:
444 How far Backward this mode will reach:
445 How many bytes this mode will add to the size of the frag
446 Which mode to go to if the offset won't fit in this one
447 */
fecd2382 448const relax_typeS
a39116f1 449 md_relax_table[] = {
f8701a3f
SC		 450 { 1, 1, 0, 0 }, /* First entries aren't used */
451 { 1, 1, 0, 0 }, /* For no good reason except */
452 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
453 { 1, 1, 0, 0 },
6d27d3a2 454
3ad9ec6a
ILT		 455 { (127), (-128), 0, TAB(ABRANCH,SHORT)},
456 { (32767), (-32768), 2, TAB(ABRANCH,LONG) },
f8701a3f
SC		 457 { 0, 0, 4, 0 },
458 { 1, 1, 0, 0 },
6d27d3a2 459
f8701a3f
SC		 460 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
461 { (32767), (-32768), 2, TAB(FBRANCH,LONG)},
462 { 0, 0, 4, 0 },
463 { 1, 1, 0, 0 },
6d27d3a2 464
f8701a3f
SC		 465 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
466 { (32767), (-32768), 2, TAB(PCREL,LONG)},
467 { 0, 0, 4, 0 },
468 { 1, 1, 0, 0 },
6d27d3a2 469
f8701a3f
SC		 470 { (127), (-128), 0, TAB(BCC68000,SHORT)},
471 { (32767), (-32768), 2, TAB(BCC68000,LONG) },
472 { 0, 0, 6, 0 }, /* jmp long space */
473 { 1, 1, 0, 0 },
6d27d3a2 474
f8701a3f
SC		 475 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
476 { (32767), (-32768), 2, TAB(DBCC,LONG) },
477 { 0, 0, 10, 0 }, /* bra/jmp long space */
478 { 1, 1, 0, 0 },
6d27d3a2 479
f8701a3f
SC		 480 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
481 { 32767, -32768, 2, TAB(PCLEA,LONG) },
482 { 0, 0, 6, 0 },
483 { 1, 1, 0, 0 },
6d27d3a2 484
f8701a3f 485 };
fecd2382
RP		 486
487/* These are the machine dependent pseudo-ops. These are included so
488 the assembler can work on the output from the SUN C compiler, which
489 generates these.
a39116f1 490 */
fecd2382
RP		 491
492/* This table describes all the machine specific pseudo-ops the assembler
493 has to support. The fields are:
a39116f1
RP		 494 pseudo-op name without dot
495 function to call to execute this pseudo-op
496 Integer arg to pass to the function
497 */
fecd2382 498const pseudo_typeS md_pseudo_table[] = {
f8701a3f
SC		 499 { "data1", s_data1, 0 },
500 { "data2", s_data2, 0 },
501 { "bss", s_bss, 0 },
502 { "even", s_even, 0 },
503 { "skip", s_space, 0 },
504 { "proc", s_proc, 0 },
bec66218 505#ifdef TE_SUN3
9e43698e 506 { "align", s_align_bytes, 0 },
bec66218 507#endif
f8701a3f 508 { 0, 0, 0 }
fecd2382
RP		 509};
510
511
3ad9ec6a
ILT		 512/* The mote pseudo ops are put into the opcode table, since they
513 don't start with a . they look like opcodes to gas.
514 */
515extern void obj_coff_section();
516
517const pseudo_typeS mote_pseudo_table[] =
518{
519
520 { "dc.l", cons,4},
521 { "dc", cons,2},
522 { "dc.w", cons,2},
523 { "dc.b", cons,1},
524
525 { "ds.l", s_space,4},
526 { "ds", s_space,2},
527 { "ds.w", s_space,2},
528 { "ds.b", s_space,1},
529
530 { "xdef", s_globl, 0},
531 { "align", s_align_ptwo, 0},
532#ifdef M68KCOFF
533 { "sect", obj_coff_section,0},
534 { "section", obj_coff_section,0},
535#endif
536 0,
537};
538
fecd2382
RP		 539/* #define isbyte(x) ((x)>=-128 && (x)<=127) */
540/* #define isword(x) ((x)>=-32768 && (x)<=32767) */
541
542#define issbyte(x) ((x)>=-128 && (x)<=127)
543#define isubyte(x) ((x)>=0 && (x)<=255)
544#define issword(x) ((x)>=-32768 && (x)<=32767)
545#define isuword(x) ((x)>=0 && (x)<=65535)
f8701a3f 546
fecd2382
RP		 547#define isbyte(x) ((x)>=-128 && (x)<=255)
548#define isword(x) ((x)>=-32768 && (x)<=65535)
549#define islong(x) (1)
f8701a3f
SC		 550
551extern char *input_line_pointer;
fecd2382 552
7c15cbe8 553enum {
f8701a3f
SC		 554 FAIL = 0,
555 OK = 1,
7c15cbe8 556};
fecd2382
RP		 557
558/* JF these tables here are for speed at the expense of size */
559/* You can replace them with the #if 0 versions if you really
560 need space and don't mind it running a bit slower */
561
562static char mklower_table[256];
563#define mklower(c) (mklower_table[(unsigned char)(c)])
f8701a3f 564static char notend_table[256];
fecd2382
RP		 565static char alt_notend_table[256];
566#define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
a39116f1 567 alt_notend_table[(unsigned char)(s[1])])))
fecd2382
RP		 568
569#if 0
570#define mklower(c) (isupper(c) ? tolower(c) : c)
571#endif
f8701a3f
SC		 572
573
574/* JF modified this to handle cases where the first part of a symbol name
575 looks like a register */
576
577/*
578 * m68k_reg_parse() := if it looks like a register, return it's token &
579 * advance the pointer.
580 */
581
0069b1f6
ILT		 582enum _register m68k_reg_parse(ccp)
583register char **ccp;
fecd2382 584{
f8701a3f 585 char *start = *ccp;
0069b1f6
ILT		 586 char c;
587 char *p;
588 symbolS *symbolP;
f8701a3f 589
587c4264 590#ifdef REGISTER_PREFIX
0069b1f6
ILT		 591 if (*start != REGISTER_PREFIX)
592 return FAIL;
593 p = start + 1;
594#else
595 p = start;
596 if (*p == OPTIONAL_REGISTER_PREFIX)
597 p++, start++;
587c4264 598#endif
0069b1f6
ILT		 599 if (!isalpha (*p) || !is_name_beginner (*p))
600 return FAIL;
587c4264 601
0069b1f6
ILT		 602 c = *p++;
603 while (isalpha(c) || isdigit(c) || c == '_')
604 {
605 c = *p++;
606 }
3ad9ec6a 607
0069b1f6
ILT		 608 * -- p = 0;
609 symbolP = symbol_find(start);
610 *p = c;
f8701a3f 611
0069b1f6 612 if (symbolP && S_GET_SEGMENT(symbolP) == SEG_REGISTER)
a39116f1 613 {
f8701a3f
SC		 614 *ccp = p;
615 return S_GET_VALUE(symbolP);
a39116f1 616 }
f8701a3f 617
0069b1f6 618 return FAIL;
fecd2382
RP		 619}
620
621#define SKIP_WHITE() { str++; if(*str==' ') str++;}
3ad9ec6a
ILT		 622#define SKIP_W() { ss++; if(*ss==' ') ss++;}
623
624/* Parse an index specification using Motorola syntax. */
625
626static int
627try_moto_index(s,opP)
628char **s;
629struct m68k_op *opP;
630{
631 register int i;
632 char *ss;
633
634 ss= *s;
635 /* SKIP_W(); */
636 if(*ss==' ') ss++;
637 i=m68k_reg_parse(&ss);
638 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
639 opP->error="Invalid index register";
640 *s=ss;
641 return FAIL;
642 }
643 opP->ireg=i;
644 /* SKIP_W(); */
645 if(*ss==')') {
646 opP->isiz=0;
647 opP->imul=1;
648 SKIP_W();
649 *s=ss;
650 return OK;
651 }
652 if(*ss!='.') {
653 opP->error="Missing . in index register";
654 *s=ss;
655 return FAIL;
656 }
657 SKIP_W();
658 if(mklower(*ss)=='w') opP->isiz=2;
659 else if(mklower(*ss)=='l') opP->isiz=3;
660 else {
661 opP->error="Size spec not .W or .L";
662 *s=ss;
663 return FAIL;
664 }
665 SKIP_W();
666 if(*ss=='.' || *ss=='*') {
667 SKIP_W();
668 switch(*ss) {
669 case '1':
670 case '2':
671 case '4':
672 case '8':
673 opP->imul= *ss-'0';
674 break;
675 default:
676 opP->error="index multiplier not 1, 2, 4 or 8";
677 *s=ss;
678 return FAIL;
679 }
680 SKIP_W();
681 } else opP->imul=1;
682 if(*ss!=')') {
683 opP->error="Missing )";
684 *s=ss;
685 return FAIL;
686 }
687 SKIP_W();
688 *s=ss;
689 return OK;
690}
fecd2382 691
7c15cbe8 692/*
3ad9ec6a
ILT		 693 *
694 * try_index := data_or_address_register + ')' + SKIP_W
695 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
696 *
697 * multiplier := <empty>
698 * | ':' + multiplier_number
7c15cbe8 699 * ;
6d27d3a2 700 *
3ad9ec6a 701 * multiplier_number := '1' | '2' | '4' | '8' ;
7c15cbe8 702 *
3ad9ec6a
ILT		 703 * size_spec := 'l' | 'L' | 'w' | 'W' ;
704 *
705 * SKIP_W := <empty> | ' ' ;
7c15cbe8
RP		 706 *
707 */
708
3ad9ec6a
ILT		 709static int try_index(s,opP)
710char **s;
711struct m68k_op *opP;
712{
713 register int i;
714 char *ss;
715
716 ss= *s;
717 /* SKIP_W(); */
718 i=m68k_reg_parse(&ss);
719 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */
720 *s=ss;
721 return FAIL;
722 }
723 opP->ireg=i;
724 /* SKIP_W(); */
725 if(*ss==')') {
726 opP->isiz=0;
727 opP->imul=1;
728 SKIP_W();
729 *s=ss;
730 return OK;
731 }
732 if(*ss!=':') {
733 opP->error="Missing : in index register";
734 *s=ss;
735 return FAIL;
736 }
737 SKIP_W();
738 switch(*ss) {
739 case 'w':
740 case 'W':
741 opP->isiz=2;
742 break;
743 case 'l':
744 case 'L':
745 opP->isiz=3;
746 break;
747 default:
748 opP->error="Index register size spec not :w or :l";
749 *s=ss;
750 return FAIL;
751 }
752 SKIP_W();
753 if(*ss==':') {
754 SKIP_W();
755 switch(*ss) {
756 case '1':
757 case '2':
758 case '4':
759 case '8':
760 if (cpu_of_arch(current_architecture) < m68020) {
761 opP->error="no index scaling in pre-68020's";
762 *s=ss;
763 return FAIL;
764 }
765 opP->imul= *ss-'0';
766 break;
767 default:
768 opP->error="index multiplier not 1, 2, 4 or 8";
769 *s=ss;
770 return FAIL;
771 }
772 SKIP_W();
773 } else opP->imul=1;
774 if(*ss!=')') {
775 opP->error="Missing )";
776 *s=ss;
777 return FAIL;
778 }
779 SKIP_W();
780 *s=ss;
781 return OK;
782} /* try_index() */
783
784/* Ian Taylor expanded this function to accept both MIT and Motorola
785 syntax. I removed the old comment, since it was wrong. The syntax
786 this accepted even before my changes was complex and undocumented.
787 I mainly added a large case when the operand string does not
788 contain an '@', since the Motorola syntax does not use the '@'
789 character. */
790
fecd2382 791int
a39116f1 792 m68k_ip_op(str,opP)
fecd2382
RP		 793char *str;
794register struct m68k_op *opP;
795{
f8701a3f
SC		 796 char *strend;
797 long i;
798 char *parse_index();
a933d598 799 int needp;
3ad9ec6a 800
f8701a3f
SC		 801 if (*str==' ') {
802 str++;
803 } /* Find the beginning of the string */
6d27d3a2 804
f8701a3f
SC		 805 if(!*str) {
806 opP->error="Missing operand";
fecd2382 807 return FAIL;
f8701a3f 808 } /* Out of gas */
6d27d3a2 809
3ad9ec6a
ILT		 810 for(strend = str; *strend; strend++)
811 ;
f8701a3f 812 --strend;
6d27d3a2 813
f8701a3f
SC		 814 if(*str=='#') {
815 str++;
816 opP->con1=add_exp(str,strend);
817 opP->mode=IMMED;
818 return OK;
819 } /* Guess what: A constant. Shar and enjoy */
6d27d3a2 820
f8701a3f 821 i = m68k_reg_parse(&str);
6d27d3a2 822
3ad9ec6a
ILT		 823 if (i!=FAIL) {
824 if(*str=='/' || *str=='-') {
825 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
826 opP->mode=REGLST;
827 return get_regs(i,str,opP);
828 }
829 if(*str=='\0') {
830 opP->reg=i;
831 /* "Rn" Register Direct mode */
832 if(i>=DATA+0 && i<=DATA+7)
833 opP->mode=DREG;
834 else if(i>=ADDR+0 && i<=ADDR+7)
835 opP->mode=AREG;
836 else
837 opP->mode=MSCR;
838 return OK;
839 }
840 }
6d27d3a2 841
3ad9ec6a 842 if (*str!='@') {
f8701a3f 843 char *stmp;
6d27d3a2 844
3ad9ec6a 845 if ((stmp=strchr(str,'@')) != 0) {
f8701a3f
SC		 846 opP->con1=add_exp(str,stmp-1);
847 if(stmp==strend) {
848 opP->mode=AINDX;
849 return(OK);
850 }
6d27d3a2 851
f8701a3f
SC		 852 if ((current_architecture & m68020up) == 0) {
853 return(FAIL);
854 } /* if target is not a '20 or better */
6d27d3a2 855
f8701a3f
SC		 856 stmp++;
857 if(*stmp++!='(' || *strend--!=')') {
858 opP->error="Malformed operand";
859 return(FAIL);
860 }
861 i=try_index(&stmp,opP);
862 opP->con2=add_exp(stmp,strend);
6d27d3a2 863
f8701a3f
SC		 864 if (i == FAIL) {
865 opP->mode=AMIND;
866 } else {
867 opP->mode=APODX;
868 }
869 return(OK);
870 } /* if there's an '@' */
6d27d3a2 871
3ad9ec6a
ILT		 872#ifndef MIT_SYNTAX_ONLY
873 /* The operand has no '@'. Try to parse it using
874 Motorola syntax. */
875 /* Logic of the parsing switch(*str):
876 case opP->mode =
877 ---- -----------
878 #anything IMMED 1
879 REG AREG or DREG or MSCR 3 or 2 or 13
880 REG- or REG/ REGLST 14
881 (REG) AINDR 4
882 (REG)+ AINC 6
883 (REG,INDX) AINDX 8
884 (EXPR,REG) AOFF 7
885 (EXPR,REG,INDX) AINDX 8
886 -(REG) ADEC 5
887 EXP2(REG) AOFF 7
888 EXP2(REG,INDX) AINDX 8
889 EXP2 ABSL 12
890
891 REG means truth(m68k_reg_parse(&str))
892 INDX means truth(try_moto_index(&str,opP))
893 EXPR means not REG
894 EXP2 means not REG and not '(' and not '-('
895 */
896
897 if(*str=='(') {
898 str++;
899 i=m68k_reg_parse(&str);
900 if((i<ADDR+0 || i>ADDR+7)
901 && (i<DATA+0 || i>DATA+7
902 || *str != ')' || str[1] != '0')
903 && i!=PC && i!=ZPC && i!=FAIL) {
904 /* Can't indirect off non address regs */
905 opP->error="Invalid indirect register";
906 return FAIL;
907 }
908 if(i!=FAIL) {
909 opP->reg=i;
910 if(*str==')') {
911 str++;
912 if(*str=='\0') {
913 /* "(An)" Address Register Indirect mode
914 or "(Dn)" for cas2. */
915 if (i>=DATA+0 && i<=DATA+7)
916 opP->mode=DINDR;
917 else
918 opP->mode=AINDR;
919 return OK;
920 }
921 if(*str=='+') {
922 if(str[1]=='\0') {
923 /* "(An)+" Register Indirect w Postincrement */
924 opP->mode=AINC;
925 return OK;
926 }
927 }
928 opP->error="Junk after indirect";
929 return FAIL;
930 }
931 if(*str==',') {
932 str++;
933 i=try_moto_index(&str,opP);
934 if(i==FAIL) return FAIL;
935 /* "(An,Rn)" Register Indirect with Index mode*/
936 opP->mode=AINDX;
937 return OK;
938 }
939 else {
940 opP->error="Bad indirect syntax";
941 return FAIL;
942 }
943 }
944 else {
945 /* "(EXPR,..." , a displacement */
946 char *stmp;
947 char *index();
948
949 if(stmp=index(str,',')) {
950 opP->con1=add_exp(str,stmp-1);
951 str=stmp;
952 SKIP_WHITE();
953 i=m68k_reg_parse(&str);
954 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC) {
955 /* Can't indirect off non address regs */
956 opP->error="Invalid indirect register";
957 return FAIL;
958 }
959 if(i!=FAIL) {
960 opP->reg=i;
961 if(*str==')') {
962 /* "(d,An)" Register Indirect w Displacement */
963 opP->mode=AOFF;
964 return OK;
965 }
966 if(*str==',') {
967 str++;
968 i=try_moto_index(&str,opP);
969 if(i==FAIL) return FAIL;
970 /* "(d,An,Rn)" Register Indirect with Index */
971 opP->mode=AINDX;
972 return OK;
973 }
974 else {
975 opP->error="Bad indirect syntax";
976 return FAIL;
977 }
978 }
979 else {
980 opP->error="Invalid register";
981 return FAIL;
982 }
983 }
984 else {
985 opP->mode = ABSL;
986 opP->con1 = add_exp(str-1,strend);
987 return OK;
988 }
989 }
990 }
6d27d3a2 991
3ad9ec6a
ILT		 992 if(*str=='-') {
993 if(str[1]=='(') {
994 str = str+2;
995 i=m68k_reg_parse(&str);
996 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) {
997 /* Can't indirect off non address regs */
998 opP->error="Invalid indirect register";
999 return FAIL;
1000 }
1001 if(i!=FAIL) {
1002 opP->reg=i;
1003 if(*str==')') {
1004 str++;
1005 if(*str=='\0') {
1006 /* "-(An)" Register Indirect with Predecrement */
1007 opP->mode=ADEC;
1008 return OK;
1009 }
1010 opP->error="Junk after indirect";
1011 return FAIL;
1012 }
1013 opP->error="Bad indirect syntax";
1014 return FAIL;
1015 }
1016 opP->mode = ABSL;
1017 opP->con1 = add_exp(str-2,strend);
1018 return OK;
1019 }
1020 /* if '-' but not "-(', do nothing */
1021 }
1022
1023 /* whether *str=='-' or not */
1024 {
1025 /* "EXP2" or "EXP2(REG..." */
1026 char *stmp;
1027 char *index();
1028 if(stmp=index(str,'(')) {
1029 char *ostr=str;
1030
1031 opP->con1=add_exp(str,stmp-1);
1032 str=stmp+1;
1033 i=m68k_reg_parse(&str);
1034 if((i<ADDR+0 || i>ADDR+7) && i!=PC
1035 && i!=ZPC && i!=FAIL) {
1036 /* Can't indirect off non address regs */
1037 opP->error="Invalid indirect register";
1038 return FAIL;
1039 }
1040 if(i!=FAIL) {
1041 opP->reg=i;
1042 if(*str==')') {
1043 /* "d(An)" Register Indirect w Displacement */
1044 opP->mode=AOFF;
1045 return OK;
1046 }
1047 if(*str==',') {
1048 str++;
1049 i=try_moto_index(&str,opP);
1050 if(i==FAIL) return FAIL;
1051 /* "d(An,Rn)" Register Indirect with Index */
1052 opP->mode=AINDX;
1053 return OK;
1054 }
1055 else {
1056 opP->error="Bad indirect syntax";
1057 return FAIL;
1058 }
1059 }
1060 else {
1061 opP->mode = ABSL;
1062 opP->con1 = add_exp(ostr,strend);
1063 return OK;
1064 }
1065 }
1066 else {
1067 /* "EXP2" Absolute */
1068 opP->mode=ABSL;
1069 opP->isiz=0;
1070 if(strend[-1]=='.' || strend[-1]==':') {
1071 /* mode ==foo.[wl] */
1072 switch(*strend) {
1073 case 'w':
1074 case 'W':
1075 opP->isiz=2;
1076 strend-=2;
1077 break;
1078 case 'l':
1079 case 'L':
1080 opP->isiz=3;
1081 strend-=2;
1082 break;
1083 }
1084 }
1085 opP->con1=add_exp(str,strend);
1086 return OK;
1087 }
1088 }
1089 /*NOTREACHED*/
1090#else /* defined (MIT_SYNTAX_ONLY) */
1091 opP->mode=ABSL;
1092 opP->con1=add_exp(str,strend);
f8701a3f 1093 return OK;
3ad9ec6a
ILT		 1094#endif /* defined (MIT_SYNTAX_ONLY) */
1095 }
1096
1097 opP->reg=i;
6d27d3a2 1098
c50140c8
ILT		 1099 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1100 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL
1101 && (str[1] != '\0' || i<DATA+0 || i>DATA+7)) {
f8701a3f 1102 opP->error="Invalid indirect register";
a39116f1 1103 return FAIL;
fecd2382 1104 }
f8701a3f 1105 know(*str == '@');
6d27d3a2 1106
f8701a3f
SC		 1107 str++;
1108 switch(*str) {
1109 case '\0':
3ad9ec6a 1110 if (i<DATA+0 || i>DATA+7)
c50140c8
ILT		 1111 opP->mode=AINDR;
1112 else
1113 opP->mode=DINDR;
f8701a3f
SC		 1114 return OK;
1115 case '-':
1116 opP->mode=ADEC;
1117 return OK;
1118 case '+':
1119 opP->mode=AINC;
1120 return OK;
1121 case '(':
1122 str++;
1123 break;
1124 default:
1125 opP->error="Junk after indirect";
1126 return FAIL;
fecd2382 1127 }
f8701a3f
SC		 1128 /* Some kind of indexing involved. Lets find out how bad it is */
1129 i=try_index(&str,opP);
1130 /* Didn't start with an index reg, maybe its offset or offset,reg */
1131 if(i==FAIL) {
1132 char *beg_str;
6d27d3a2 1133
f8701a3f
SC		 1134 beg_str=str;
1135 for(i=1;i;) {
1136 switch(*str++) {
1137 case '\0':
1138 opP->error="Missing )";
1139 return FAIL;
1140 case ',': i=0; break;
1141 case '(': i++; break;
1142 case ')': --i; break;
1143 }
1144 }
1145 /* if(str[-3]==':') {
1146 int siz;
6d27d3a2 1147
f8701a3f
SC		 1148 switch(str[-2]) {
1149 case 'b':
1150 case 'B':
1151 siz=1;
1152 break;
1153 case 'w':
1154 case 'W':
1155 siz=2;
1156 break;
1157 case 'l':
1158 case 'L':
1159 siz=3;
1160 break;
1161 default:
1162 opP->error="Specified size isn't :w or :l";
1163 return FAIL;
1164 }
1165 opP->con1=add_exp(beg_str,str-4);
1166 opP->con1->e_siz=siz;
1167 } else */
1168 opP->con1=add_exp(beg_str,str-2);
1169 /* Should be offset,reg */
1170 if(str[-1]==',') {
1171 i=try_index(&str,opP);
1172 if(i==FAIL) {
1173 opP->error="Malformed index reg";
1174 return FAIL;
1175 }
1176 }
1177 }
1178 /* We've now got offset) offset,reg) or reg) */
6d27d3a2 1179
f8701a3f
SC		 1180 if (*str == '\0') {
1181 /* Th-the-thats all folks */
1182 if (opP->reg == FAIL) opP->mode = AINDX; /* Other form of indirect */
1183 else if(opP->ireg == FAIL) opP->mode = AOFF;
1184 else opP->mode = AINDX;
1185 return(OK);
1186 }
1187 /* Next thing had better be another @ */
a933d598
SC		 1188 if (*str == '@') {
1189 if (str[1] == '(') {
1190 needp = 1;
1191 str+=2;
1192 }
1193 else {
1194 needp = 0;
1195 str++;
1196 }
fecd2382 1197 }
6d27d3a2 1198
f8701a3f 1199 if ((current_architecture & m68020up) == 0) {
a39116f1 1200 return(FAIL);
f8701a3f 1201 } /* if target is not a '20 or better */
6d27d3a2
KR		 1202
1203
f8701a3f
SC		 1204 if(opP->ireg != FAIL) {
1205 opP->mode = APRDX;
6d27d3a2 1206
f8701a3f
SC		 1207 i = try_index(&str, opP);
1208 if (i != FAIL) {
1209 opP->error = "Two index registers! not allowed!";
1210 return(FAIL);
1211 }
865a2edf 1212 } else {
f8701a3f 1213 i = try_index(&str, opP);
865a2edf 1214 }
6d27d3a2 1215
f8701a3f
SC		 1216 if (i == FAIL) {
1217 char *beg_str;
6d27d3a2 1218
f8701a3f 1219 beg_str = str;
6d27d3a2 1220
f8701a3f
SC		 1221 for (i = 1; i; ) {
1222 switch(*str++) {
1223 case '\0':
a933d598 1224 if (needp)
f8701a3f
SC		 1225 opP->error="Missing )";
1226 return(FAIL);
a933d598 1227 break;
f8701a3f
SC		 1228 case ',': i=0; break;
1229 case '(': i++; break;
1230 case ')': --i; break;
1231 }
1232 }
6d27d3a2 1233
f8701a3f 1234 opP->con2=add_exp(beg_str,str-2);
6d27d3a2 1235
f8701a3f
SC		 1236 if (str[-1] == ',') {
1237 if (opP->ireg != FAIL) {
1238 opP->error = "Can't have two index regs";
1239 return(FAIL);
1240 }
6d27d3a2 1241
f8701a3f 1242 i = try_index(&str, opP);
6d27d3a2 1243
f8701a3f
SC		 1244 if (i == FAIL) {
1245 opP->error = "malformed index reg";
1246 return(FAIL);
1247 }
6d27d3a2 1248
f8701a3f
SC		 1249 opP->mode = APODX;
1250 } else if (opP->ireg != FAIL) {
1251 opP->mode = APRDX;
1252 } else {
1253 opP->mode = AMIND;
1254 }
1255 } else {
1256 opP->mode = APODX;
1257 }
6d27d3a2 1258
f8701a3f
SC		 1259 if(*str!='\0') {
1260 opP->error="Junk after indirect";
1261 return FAIL;
1262 }
1263 return(OK);
a39116f1 1264} /* m68k_ip_op() */
fecd2382 1265
7c15cbe8 1266
3ad9ec6a
ILT		 1267#ifdef M68KCOFF
1268
1269short tc_coff_fix2rtype(fixP)
1270fixS *fixP;
fecd2382 1271{
3ad9ec6a
ILT		 1272 return (fixP->fx_pcrel ?
1273 (fixP->fx_size == 1 ? R_PCRBYTE :
1274 fixP->fx_size == 2 ? R_PCRWORD :
1275 R_PCRLONG):
1276 (fixP->fx_size == 1 ? R_RELBYTE :
1277 fixP->fx_size == 2 ? R_RELWORD :
1278 R_RELLONG));
6d27d3a2 1279
3ad9ec6a
ILT		 1280
1281}
1282
1283#endif
fecd2382
RP		 1284
1285#ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1286main()
1287{
f8701a3f
SC		 1288 char buf[128];
1289 struct m68k_op thark;
6d27d3a2 1290
f8701a3f
SC		 1291 for(;;) {
1292 if(!gets(buf))
1293 break;
1294 memset(&thark, '\0', sizeof(thark));
1295 if(!m68k_ip_op(buf,&thark)) printf("FAIL:");
1296 if(thark.error)
1297 printf("op1 error %s in %s\n",thark.error,buf);
1298 printf("mode %d, reg %d, ",thark.mode,thark.reg);
1299 if(thark.b_const)
1300 printf("Constant: '%.*s',",1+thark.e_const-thark.b_const,thark.b_const);
1301 printf("ireg %d, isiz %d, imul %d ",thark.ireg,thark.isiz,thark.imul);
1302 if(thark.b_iadd)
1303 printf("Iadd: '%.*s'",1+thark.e_iadd-thark.b_iadd,thark.b_iadd);
1304 printf("\n");
1305 }
1306 exit(0);
fecd2382
RP		 1307}
1308
1309#endif
1310
1311
1312static struct hash_control* op_hash = NULL; /* handle of the OPCODE hash table
a39116f1
RP		 1313 NULL means any use before m68k_ip_begin()
1314 will crash */
fecd2382
RP		 1315
1316\f
1317/*
7c15cbe8 1318 * m 6 8 k _ i p ( )
fecd2382
RP		 1319 *
1320 * This converts a string into a 68k instruction.
1321 * The string must be a bare single instruction in sun format
1322 * with RMS-style 68020 indirects
1323 * (example: )
1324 *
1325 * It provides some error messages: at most one fatal error message (which
1326 * stops the scan) and at most one warning message for each operand.
1327 * The 68k instruction is returned in exploded form, since we have no
1328 * knowledge of how you parse (or evaluate) your expressions.
1329 * We do however strip off and decode addressing modes and operation
1330 * mnemonic.
1331 *
1332 * This function's value is a string. If it is not "" then an internal
1333 * logic error was found: read this code to assign meaning to the string.
1334 * No argument string should generate such an error string:
1335 * it means a bug in our code, not in the user's text.
1336 *
7c15cbe8 1337 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
fecd2382
RP		 1338 * this function.
1339 */
1340
1341/* JF this function no longer returns a useful value. Sorry */
7c15cbe8 1342void m68k_ip (instring)
6d27d3a2 1343 char *instring;
fecd2382 1344{
6d27d3a2
KR		 1345 register char *p;
1346 register struct m68k_op *opP;
1347 register struct m68k_incant *opcode;
1348 register char *s;
1349 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
3ad9ec6a 1350 char *pdot, *pdotmove;
6d27d3a2
KR		 1351 int siz1, siz2;
1352 char c;
1353 int losing;
1354 int opsfound;
1355 char *crack_operand();
1356 LITTLENUM_TYPE words[6];
1357 LITTLENUM_TYPE *wordp;
8be74775 1358 unsigned long ok_arch = 0;
6d27d3a2
KR		 1359
1360 if (*instring == ' ')
1361 instring++; /* skip leading whitespace */
1362
1363 /* Scan up to end of operation-code, which MUST end in end-of-string
1364 or exactly 1 space. */
3ad9ec6a
ILT		 1365 pdot = 0;
1366 for (p = instring; *p != '\0'; p++) {
6d27d3a2
KR		 1367 if (*p == ' ')
1368 break;
3ad9ec6a
ILT		 1369 if (*p == '.')
1370 pdot = p;
1371 }
6d27d3a2
KR		 1372
1373 if (p == instring) {
1374 the_ins.error = "No operator";
1375 the_ins.opcode[0] = NULL;
1376 /* the_ins.numo=1; */
1377 return;
1378 }
1379
1380 /* p now points to the end of the opcode name, probably whitespace.
1381 make sure the name is null terminated by clobbering the whitespace,
3ad9ec6a
ILT		 1382 look it up in the hash table, then fix it back.
1383 Remove a dot, first, since the opcode tables have none. */
1384 if (pdot != NULL) {
1385 for (pdotmove=pdot; pdotmove<p; pdotmove++)
1386 *pdotmove=pdotmove[1];
1387 p--;
1388 }
1389
6d27d3a2
KR		 1390 c = *p;
1391 *p = '\0';
1392 opcode = (struct m68k_incant *)hash_find (op_hash, instring);
1393 *p = c;
1394
3ad9ec6a
ILT		 1395 if (pdot != NULL) {
1396 for (pdotmove=p; pdotmove>pdot; pdotmove--)
1397 *pdotmove=pdotmove[-1];
1398 *pdot='.';
1399 ++p;
1400 }
1401
6d27d3a2
KR		 1402 if (opcode == NULL) {
1403 the_ins.error = "Unknown operator";
1404 the_ins.opcode[0] = NULL;
1405 /* the_ins.numo=1; */
1406 return;
1407 }
1408
1409 /* found a legitimate opcode, start matching operands */
1410 while (*p == ' ') ++p;
1411
3ad9ec6a
ILT		 1412
1413 if (opcode->m_operands == 0) {
1414 char *old = input_line_pointer;
1415 *old = '\n';
1416 input_line_pointer = p;
1417 /* Ahh - it's a motorola style psuedo op */
1418 mote_pseudo_table[opcode->m_opnum].poc_handler
1419 ( mote_pseudo_table[opcode->m_opnum].poc_val);
1420 input_line_pointer = old;
1421 *old = 0;
1422
1423 return;
1424 }
1425
6d27d3a2
KR		 1426 for(opP = &the_ins.operands[0]; *p; opP++) {
1427
1428 p = crack_operand(p, opP);
1429
1430 if (opP->error) {
1431 the_ins.error=opP->error;
1432 return;
1433 }
1434 }
1435
1436 opsfound = opP - &the_ins.operands[0];
1437
1438 /* This ugly hack is to support the floating pt opcodes in their standard form */
1439 /* Essentially, we fake a first enty of type COP#1 */
1440 if (opcode->m_operands[0]=='I') {
1441 int n;
1442
1443 for(n=opsfound;n>0;--n)
1444 the_ins.operands[n]=the_ins.operands[n-1];
1445
6d27d3a2
KR		 1446 memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
1447 the_ins.operands[0].mode=MSCR;
1448 the_ins.operands[0].reg=COPNUM; /* COP #1 */
1449 opsfound++;
1450 }
1451
1452 /* We've got the operands. Find an opcode that'll accept them */
1453 for (losing = 0; ; ) {
1454 /* if we didn't get the right number of ops,
1455 or we have no common model with this pattern
1456 then reject this pattern. */
1457
1458 if (opsfound != opcode->m_opnum
8be74775
KR		 1459 || ((opcode->m_arch & current_architecture) == 0))
1460 {
1461 ++losing;
1462 ok_arch |= opcode->m_arch;
1463 }
1464 else {
1465 for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
1466 /* Warning: this switch is huge! */
1467 /* I've tried to organize the cases into this order:
1468 non-alpha first, then alpha by letter. lower-case goes directly
1469 before uppercase counterpart. */
1470 /* Code with multiple case ...: gets sorted by the lowest case ...
1471 it belongs to. I hope this makes sense. */
1472 switch(*s) {
1473 case '!':
1474 if (opP->mode == MSCR || opP->mode == IMMED
1475 || opP->mode == DREG || opP->mode == AREG
1476 || opP->mode == AINC || opP->mode == ADEC
1477 || opP->mode == REGLST)
1478 losing++;
1479 break;
1480
df3768fb
KR		 1481 case '`':
1482 switch (opP->mode) {
1483 case MSCR: case IMMED: case DREG: case AREG:
1484 case AINC: case REGLST: case AINDR:
1485 losing++;
1486 }
1487 break;
1488
8be74775
KR		 1489 case '#':
1490 if(opP->mode!=IMMED)
1491 losing++;
1492 else {
1493 long t;
6d27d3a2 1494
8be74775
KR		 1495 t=get_num(opP->con1,80);
1496 if(s[1]=='b' && !isbyte(t))
1497 losing++;
1498 else if(s[1]=='w' && !isword(t))
1499 losing++;
1500 }
1501 break;
1502
1503 case '^':
1504 case 'T':
1505 if(opP->mode!=IMMED)
1506 losing++;
1507 break;
1508
1509 case '$':
1510 if(opP->mode==MSCR || opP->mode==AREG ||
1511 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1512 losing++;
1513 break;
1514
1515 case '%':
1516 if(opP->mode==MSCR || opP->reg==PC ||
1517 opP->reg==ZPC || opP->mode==REGLST)
1518 losing++;
1519 break;
1520
1521
1522 case '&':
1523 if(opP->mode==MSCR || opP->mode==DREG ||
1524 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
1525 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
1526 losing++;
1527 break;
1528
1529 case '*':
1530 if(opP->mode==MSCR || opP->mode==REGLST)
1531 losing++;
1532 break;
6d27d3a2 1533
8be74775
KR		 1534 case '+':
1535 if(opP->mode!=AINC)
1536 losing++;
1537 break;
6d27d3a2 1538
8be74775
KR		 1539 case '-':
1540 if(opP->mode!=ADEC)
1541 losing++;
1542 break;
1543
1544 case '/':
1545 if(opP->mode==MSCR || opP->mode==AREG ||
1546 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
1547 losing++;
1548 break;
1549
1550 case ';':
1551 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
1552 losing++;
1553 break;
1554
1555 case '?':
1556 if(opP->mode==MSCR || opP->mode==AREG ||
1557 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
1558 opP->reg==ZPC || opP->mode==REGLST)
1559 losing++;
1560 break;
1561
1562 case '@':
1563 if(opP->mode==MSCR || opP->mode==AREG ||
1564 opP->mode==IMMED || opP->mode==REGLST)
1565 losing++;
1566 break;
1567
1568 case '~': /* For now! (JF FOO is this right?) */
1569 if(opP->mode==MSCR || opP->mode==DREG ||
1570 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
1571 losing++;
1572 break;
1573
4134a793
KR		 1574 case '3':
1575 if (opP->mode != MSCR || (opP->reg != TT0 && opP->reg != TT1))
1576 losing++;
1577 break;
1578
8be74775
KR		 1579 case 'A':
1580 if(opP->mode!=AREG)
1581 losing++;
1582 break;
1583 case 'a':
1584 if (opP->mode != AINDR) {
1585 ++losing;
1586 } /* if not address register indirect */
1587 break;
1588 case 'B': /* FOO */
1589 if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
1590 && instring[1] == 'b'
1591 && instring[2] == 's'
1592 && instring[3] == 'r'))
1593 losing++;
1594 break;
1595
1596 case 'C':
1597 if(opP->mode!=MSCR || opP->reg!=CCR)
1598 losing++;
1599 break;
1600
1601 case 'd': /* FOO This mode is a KLUDGE!! */
1602 if(opP->mode!=AOFF && (opP->mode!=ABSL ||
1603 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
1604 losing++;
1605 break;
1606
1607 case 'D':
1608 if(opP->mode!=DREG)
1609 losing++;
1610 break;
1611
1612 case 'F':
1613 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
1614 losing++;
1615 break;
1616
1617 case 'I':
1618 if(opP->mode!=MSCR || opP->reg<COPNUM ||
1619 opP->reg>=COPNUM+7)
1620 losing++;
1621 break;
1622
1623 case 'J':
1624 if (opP->mode != MSCR
1625 || opP->reg < USP
1626 || opP->reg > URP
1627 || cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
1628 || (cpu_of_arch(current_architecture) < m68020
1629 && opP->reg != SFC
1630 && opP->reg != DFC
1631 && opP->reg != USP
1632 && opP->reg != VBR) /* 68010's had only these */
1633 || (cpu_of_arch(current_architecture) < m68040
1634 && opP->reg != SFC
1635 && opP->reg != DFC
1636 && opP->reg != USP
1637 && opP->reg != VBR
1638 && opP->reg != CACR
1639 && opP->reg != CAAR
1640 && opP->reg != MSP
1641 && opP->reg != ISP) /* 680[23]0's have only these */
1642 || (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
1643 && opP->reg == CAAR)) {
1644 losing++;
1645 } /* doesn't cut it */
1646 break;
1647
1648 case 'k':
1649 if(opP->mode!=IMMED)
1650 losing++;
1651 break;
6d27d3a2 1652
8be74775
KR		 1653 case 'l':
1654 case 'L':
1655 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
1656 if(s[1]=='8')
1657 losing++;
1658 else {
1659 opP->mode=REGLST;
1660 opP->reg=1<<(opP->reg-DATA);
1661 }
1662 } else if(opP->mode!=REGLST) {
1663 losing++;
1664 } else if(s[1]=='8' && opP->reg&0x0FFffFF)
1665 losing++;
1666 else if(s[1]=='3' && opP->reg&0x7000000)
1667 losing++;
1668 break;
1669
1670 case 'M':
1671 if(opP->mode!=IMMED)
1672 losing++;
1673 else {
1674 long t;
6d27d3a2 1675
8be74775
KR		 1676 t=get_num(opP->con1,80);
1677 if(!issbyte(t) || isvar(opP->con1))
1678 losing++;
1679 }
1680 break;
6d27d3a2 1681
8be74775
KR		 1682 case 'O':
1683 if(opP->mode!=DREG && opP->mode!=IMMED)
1684 losing++;
1685 break;
6d27d3a2 1686
8be74775
KR		 1687 case 'Q':
1688 if(opP->mode!=IMMED)
1689 losing++;
1690 else {
1691 long t;
6d27d3a2 1692
8be74775
KR		 1693 t=get_num(opP->con1,80);
1694 if(t<1 || t>8 || isvar(opP->con1))
1695 losing++;
1696 }
1697 break;
1698
1699 case 'R':
1700 if(opP->mode!=DREG && opP->mode!=AREG)
1701 losing++;
1702 break;
1703
c50140c8
ILT		 1704 case 'r':
1705 if (opP->mode!=AINDR && opP->mode!=DINDR)
1706 losing++;
1707 break;
1708
8be74775
KR		 1709 case 's':
1710 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
1711 losing++;
1712 break;
1713
1714 case 'S':
1715 if(opP->mode!=MSCR || opP->reg!=SR)
1716 losing++;
1717 break;
1718
4134a793
KR		 1719 case 't':
1720 if (opP->mode != IMMED)
1721 losing++;
1722 else
1723 {
1724 long t = get_num (opP->con1, 80);
1725 if (t < 0 || t > 7 || isvar (opP->con1))
1726 losing++;
1727 }
1728 break;
1729
8be74775
KR		 1730 case 'U':
1731 if(opP->mode!=MSCR || opP->reg!=USP)
1732 losing++;
1733 break;
1734
1735 /* JF these are out of order. We could put them
1736 in order if we were willing to put up with
4134a793
KR		 1737 bunches of #ifdef m68851s in the code.
1738
1739 Don't forget that you need these operands
1740 to use 68030 MMU instructions. */
f8701a3f 1741#ifndef NO_68851
8be74775
KR		 1742 /* Memory addressing mode used by pflushr */
1743 case '|':
1744 if(opP->mode==MSCR || opP->mode==DREG ||
1745 opP->mode==AREG || opP->mode==REGLST)
1746 losing++;
1747 break;
1748
1749 case 'f':
1750 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
1751 losing++;
1752 break;
1753
1754 case 'P':
4134a793
KR		 1755 if (opP->mode != MSCR
1756 || (opP->reg != TC && opP->reg != CAL
1757 && opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
8be74775
KR		 1758 losing++;
1759 break;
1760
1761 case 'V':
1762 if (opP->reg != VAL)
1763 losing++;
1764 break;
6d27d3a2 1765
8be74775 1766 case 'W':
4134a793
KR		 1767 if (opP->mode != MSCR
1768 || (opP->reg != DRP && opP->reg != SRP
1769 && opP->reg != CRP))
8be74775
KR		 1770 losing++;
1771 break;
1772
1773 case 'X':
1774 if (opP->mode != MSCR ||
1775 (!(opP->reg >= BAD && opP->reg <= BAD+7) &&
1776 !(opP->reg >= BAC && opP->reg <= BAC+7)))
1777 losing++;
1778 break;
1779
1780 case 'Y':
1781 if (opP->reg != PSR)
1782 losing++;
1783 break;
1784
1785 case 'Z':
1786 if (opP->reg != PCSR)
1787 losing++;
1788 break;
f8701a3f 1789#endif
8be74775
KR		 1790 case 'c':
1791 if (opP->reg != NC
1792 && opP->reg != IC
1793 && opP->reg != DC
1794 && opP->reg != BC) {
1795 losing++;
1796 } /* not a cache specifier. */
1797 break;
1798
1799 case '_':
1800 if (opP->mode != ABSL) {
1801 ++losing;
1802 } /* not absolute */
1803 break;
6d27d3a2 1804
8be74775 1805 default:
4134a793 1806 as_fatal("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
8be74775
KR		 1807 *s, __LINE__, __FILE__);
1808 } /* switch on type of operand */
6d27d3a2 1809
8be74775
KR		 1810 if (losing)
1811 break;
1812 } /* for each operand */
1813 } /* if immediately wrong */
6d27d3a2
KR		 1814
1815 if (!losing) {
1816 break;
1817 } /* got it. */
1818
1819 opcode = opcode->m_next;
1820
1821 if (!opcode) {
4134a793
KR		 1822 if (ok_arch
1823 && !(ok_arch & current_architecture))
8be74775
KR		 1824 {
1825 char buf[200], *cp;
1826 int len;
1827 strcpy (buf, "invalid instruction for this architecture; needs ");
1828 cp = buf + strlen (buf);
1829 switch (ok_arch)
1830 {
1831 case mfloat:
4134a793 1832 strcpy (cp, "fpu (68040 or 68881/68882)");
8be74775
KR		 1833 break;
1834 case mmmu:
4134a793 1835 strcpy (cp, "mmu (68030 or 68851)");
8be74775
KR		 1836 break;
1837 case m68020up:
1838 strcpy (cp, "68020 or higher");
1839 break;
1840 case m68000up:
1841 strcpy (cp, "68000 or higher");
1842 break;
1843 case m68010up:
1844 strcpy (cp, "68010 or higher");
1845 break;
1846 default:
1847 {
1848 int got_one = 0, idx;
1849 const static struct {
df3768fb 1850 int arch;
8be74775
KR		 1851 const char *name;
1852 } archs[] = {
1853 m68000, "68000",
1854 m68010, "68010",
1855 m68020, "68020",
1856 m68030, "68030",
1857 m68040, "68040",
df3768fb 1858 cpu32, "cpu32",
8be74775
KR		 1859 m68881, "68881",
1860 m68851, "68851",
1861 };
1862 for (idx = 0; idx < sizeof (archs)/sizeof (archs[0]); idx++)
1863 {
1864 if (archs[idx].arch & ok_arch)
1865 {
1866 if (got_one)
1867 {
1868 strcpy (cp, " or ");
1869 cp += strlen (cp);
1870 }
1871 got_one = 1;
1872 strcpy (cp, archs[idx].name);
1873 cp += strlen (cp);
1874 }
1875 }
1876 }
1877 }
1878 len = cp - buf + 1;
1879 cp = malloc (len);
1880 strcpy (cp, buf);
1881 the_ins.error = cp;
1882 }
1883 else
1884 the_ins.error = "operands mismatch";
6d27d3a2
KR		 1885 return;
1886 } /* Fell off the end */
1887
1888 losing = 0;
1889 }
1890
1891 /* now assemble it */
1892
1893 the_ins.args=opcode->m_operands;
1894 the_ins.numargs=opcode->m_opnum;
1895 the_ins.numo=opcode->m_codenum;
1896 the_ins.opcode[0]=getone(opcode);
1897 the_ins.opcode[1]=gettwo(opcode);
1898
1899 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) {
1900 /* This switch is a doozy.
1901 Watch the first step; its a big one! */
1902 switch(s[0]) {
1903
1904 case '*':
1905 case '~':
1906 case '%':
1907 case ';':
1908 case '@':
1909 case '!':
1910 case '&':
1911 case '$':
1912 case '?':
1913 case '/':
df3768fb 1914 case '`':
f8701a3f 1915#ifndef NO_68851
6d27d3a2 1916 case '|':
f8701a3f 1917#endif
6d27d3a2
KR		 1918 switch(opP->mode) {
1919 case IMMED:
1920 tmpreg=0x3c; /* 7.4 */
1921 if (strchr("bwl",s[1])) nextword=get_num(opP->con1,80);
1922 else nextword=nextword=get_num(opP->con1,0);
1923 if(isvar(opP->con1))
1924 add_fix(s[1],opP->con1,0);
1925 switch(s[1]) {
1926 case 'b':
1927 if(!isbyte(nextword))
1928 opP->error="operand out of range";
1929 addword(nextword);
1930 baseo=0;
1931 break;
1932 case 'w':
1933 if(!isword(nextword))
1934 opP->error="operand out of range";
1935 addword(nextword);
1936 baseo=0;
1937 break;
1938 case 'l':
1939 addword(nextword>>16);
1940 addword(nextword);
1941 baseo=0;
1942 break;
1943
1944 case 'f':
1945 baseo=2;
1946 outro=8;
1947 break;
1948 case 'F':
1949 baseo=4;
1950 outro=11;
1951 break;
1952 case 'x':
1953 baseo=6;
1954 outro=15;
1955 break;
1956 case 'p':
1957 baseo=6;
1958 outro= -1;
1959 break;
1960 default:
1961 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1962 *s, s[1], __LINE__, __FILE__);
1963 }
1964 if(!baseo)
1965 break;
1966
1967 /* We gotta put out some float */
1968 if(seg(opP->con1)!=SEG_BIG) {
1969 int_to_gen(nextword);
1970 gen_to_words(words,baseo,(long int)outro);
1971 for(wordp=words;baseo--;wordp++)
1972 addword(*wordp);
1973 break;
1974 } /* Its BIG */
1975 if(offs(opP->con1)>0) {
6d27d3a2
KR		 1976 if(offs(opP->con1)>baseo) {
1977 as_warn("Bignum too big for %c format; truncated",s[1]);
1978 offs(opP->con1)=baseo;
1979 }
1980 baseo-=offs(opP->con1);
1981 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp)
1982 addword(*wordp);
1983 while(baseo--)
1984 addword(0);
1985 break;
1986 }
1987 gen_to_words(words,baseo,(long)outro);
1988 for (wordp=words;baseo--;wordp++)
1989 addword(*wordp);
1990 break;
1991 case DREG:
1992 tmpreg=opP->reg-DATA; /* 0.dreg */
1993 break;
1994 case AREG:
1995 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */
1996 break;
1997 case AINDR:
1998 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */
1999 break;
2000 case ADEC:
2001 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */
2002 break;
2003 case AINC:
2004 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */
2005 break;
2006 case AOFF:
2007
2008 nextword=get_num(opP->con1,80);
2009 /* Force into index mode. Hope this works */
2010
2011 /* We do the first bit for 32-bit displacements,
2012 and the second bit for 16 bit ones. It is
2013 possible that we should make the default be
2014 WORD instead of LONG, but I think that'd
2015 break GCC, so we put up with a little
2016 inefficiency for the sake of working output.
2017 */
2018
2019 if( !issword(nextword)
2020 || ( isvar(opP->con1)
2021 && ( ( opP->con1->e_siz==0
2022 && flagseen['l']==0)
2023 || opP->con1->e_siz==3))) {
2024
2025 if(opP->reg==PC)
2026 tmpreg=0x3B; /* 7.3 */
2027 else
2028 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2029 if(isvar(opP->con1)) {
2030 if(opP->reg==PC) {
2031 add_frag(adds(opP->con1),
2032 offs(opP->con1),
2033 TAB(PCLEA,SZ_UNDEF));
2034 break;
2035 } else {
2036 addword(0x0170);
04b07d16 2037 add_fix('l',opP->con1,0);
6d27d3a2
KR		 2038 }
2039 } else
2040 addword(0x0170);
2041 addword(nextword>>16);
2042 } else {
2043 if(opP->reg==PC)
2044 tmpreg=0x3A; /* 7.2 */
2045 else
2046 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */
2047
2048 if(isvar(opP->con1)) {
2049 if(opP->reg==PC) {
2050 add_fix('w',opP->con1,1);
2051 } else
2052 add_fix('w',opP->con1,0);
2053 }
2054 }
2055 addword(nextword);
2056 break;
2057
2058 case APODX:
2059 case AMIND:
2060 case APRDX:
2061 know(current_architecture & m68020up);
2062 /* intentional fall-through */
2063 case AINDX:
2064 nextword=0;
2065 baseo=get_num(opP->con1,80);
2066 outro=get_num(opP->con2,80);
2067 /* Figure out the 'addressing mode' */
2068 /* Also turn on the BASE_DISABLE bit, if needed */
2069 if(opP->reg==PC || opP->reg==ZPC) {
2070 tmpreg=0x3b; /* 7.3 */
2071 if(opP->reg==ZPC)
2072 nextword|=0x80;
2073 } else if(opP->reg==FAIL) {
2074 nextword|=0x80;
2075 tmpreg=0x30; /* 6.garbage */
2076 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */
2077
2078 siz1= (opP->con1) ? opP->con1->e_siz : 0;
2079 siz2= (opP->con2) ? opP->con2->e_siz : 0;
2080
2081 /* Index register stuff */
2082 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) {
2083 nextword|=(opP->ireg-DATA)<<12;
2084
2085 if(opP->isiz==0 || opP->isiz==3)
2086 nextword|=0x800;
2087 switch(opP->imul) {
2088 case 1: break;
2089 case 2: nextword|=0x200; break;
2090 case 4: nextword|=0x400; break;
2091 case 8: nextword|=0x600; break;
2092 default: as_fatal("failed sanity check.");
2093 }
2094 /* IF its simple,
2095 GET US OUT OF HERE! */
2096
2097 /* Must be INDEX, with an index
2098 register. Address register
2099 cannot be ZERO-PC, and either
2100 :b was forced, or we know
2101 it will fit */
2102 if( opP->mode==AINDX
2103 && opP->reg!=FAIL
2104 && opP->reg!=ZPC
2105 && ( siz1==1
2106 || ( issbyte(baseo)
2107 && !isvar(opP->con1)))) {
2108 nextword +=baseo&0xff;
2109 addword(nextword);
2110 if(isvar(opP->con1))
2111 add_fix('B',opP->con1,0);
2112 break;
2113 }
2114 } else
2115 nextword|=0x40; /* No index reg */
2116
2117 /* It aint simple */
2118 nextword|=0x100;
2119 /* If the guy specified a width, we assume that
2120 it is wide enough. Maybe it isn't. If so, we lose
2121 */
2122 switch(siz1) {
2123 case 0:
2124 if(isvar(opP->con1) || !issword(baseo)) {
2125 siz1=3;
2126 nextword|=0x30;
2127 } else if(baseo==0)
2128 nextword|=0x10;
2129 else {
2130 nextword|=0x20;
2131 siz1=2;
2132 }
2133 break;
2134 case 1:
2135 as_warn("Byte dispacement won't work. Defaulting to :w");
2136 case 2:
2137 nextword|=0x20;
2138 break;
2139 case 3:
2140 nextword|=0x30;
2141 break;
2142 }
2143
2144 /* Figure out innner displacement stuff */
2145 if(opP->mode!=AINDX) {
2146 switch(siz2) {
2147 case 0:
2148 if(isvar(opP->con2) || !issword(outro)) {
2149 siz2=3;
2150 nextword|=0x3;
2151 } else if(outro==0)
2152 nextword|=0x1;
2153 else {
2154 nextword|=0x2;
2155 siz2=2;
2156 }
2157 break;
2158 case 1:
2159 as_warn("Byte dispacement won't work. Defaulting to :w");
2160 case 2:
2161 nextword|=0x2;
2162 break;
2163 case 3:
2164 nextword|=0x3;
2165 break;
2166 }
2167 if(opP->mode==APODX) nextword|=0x04;
2168 else if(opP->mode==AMIND) nextword|=0x40;
2169 }
2170 addword(nextword);
2171
2172 if(isvar(opP->con1)) {
2173 if(opP->reg==PC || opP->reg==ZPC) {
2174 add_fix(siz1==3 ? 'l' : 'w',opP->con1,1);
2175 opP->con1->e_exp.X_add_number+=6;
2176 } else
2177 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0);
2178 }
2179 if(siz1==3)
2180 addword(baseo>>16);
2181 if(siz1)
2182 addword(baseo);
2183
2184 if(isvar(opP->con2)) {
2185 if(opP->reg==PC || opP->reg==ZPC) {
2186 add_fix(siz2==3 ? 'l' : 'w',opP->con2,1);
2187 opP->con1->e_exp.X_add_number+=6;
2188 } else
2189 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0);
2190 }
2191 if(siz2==3)
2192 addword(outro>>16);
2193 if(siz2)
2194 addword(outro);
2195
2196 break;
2197
2198 case ABSL:
2199 nextword=get_num(opP->con1,80);
2200 switch(opP->con1->e_siz) {
2201 default:
2202 as_warn("Unknown size for absolute reference");
2203 case 0:
2204 if(!isvar(opP->con1) && issword(offs(opP->con1))) {
2205 tmpreg=0x38; /* 7.0 */
2206 addword(nextword);
2207 break;
2208 }
2209 /* Don't generate pc relative code
2210 on 68010 and 68000 */
2211 if(isvar(opP->con1)
2212 && !subs(opP->con1)
2213 && seg(opP->con1) == SEG_TEXT
2214 && now_seg == SEG_TEXT
2215 && cpu_of_arch(current_architecture) >= m68020
2216 && !flagseen['S']
2217 && !strchr("~%&$?", s[0])) {
2218 tmpreg=0x3A; /* 7.2 */
2219 add_frag(adds(opP->con1),
2220 offs(opP->con1),
2221 TAB(PCREL,SZ_UNDEF));
2222 break;
2223 }
2224 case 3: /* Fall through into long */
2225 if(isvar(opP->con1))
2226 add_fix('l',opP->con1,0);
2227
2228 tmpreg=0x39; /* 7.1 mode */
2229 addword(nextword>>16);
2230 addword(nextword);
2231 break;
2232
2233 case 2: /* Word */
2234 if(isvar(opP->con1))
2235 add_fix('w',opP->con1,0);
2236
2237 tmpreg=0x38; /* 7.0 mode */
2238 addword(nextword);
2239 break;
2240 }
2241 break;
c50140c8
ILT		 2242 case DINDR:
2243 as_bad("invalid indirect register");
2244 break;
6d27d3a2
KR		 2245 case MSCR:
2246 default:
2247 as_bad("unknown/incorrect operand");
2248 /* abort(); */
2249 }
2250 install_gen_operand(s[1],tmpreg);
2251 break;
2252
2253 case '#':
2254 case '^':
2255 switch(s[1]) { /* JF: I hate floating point! */
2256 case 'j':
2257 tmpreg=70;
2258 break;
2259 case '8':
2260 tmpreg=20;
2261 break;
2262 case 'C':
2263 tmpreg=50;
2264 break;
2265 case '3':
2266 default:
2267 tmpreg=80;
2268 break;
2269 }
2270 tmpreg=get_num(opP->con1,tmpreg);
2271 if(isvar(opP->con1))
2272 add_fix(s[1],opP->con1,0);
2273 switch(s[1]) {
2274 case 'b': /* Danger: These do no check for
2275 certain types of overflow.
2276 user beware! */
2277 if(!isbyte(tmpreg))
2278 opP->error="out of range";
2279 insop(tmpreg);
2280 if(isvar(opP->con1))
2281 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2282 break;
2283 case 'w':
2284 if(!isword(tmpreg))
2285 opP->error="out of range";
2286 insop(tmpreg);
2287 if(isvar(opP->con1))
2288 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2289 break;
2290 case 'l':
2291 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */
2292 insop(tmpreg>>16);
2293 if(isvar(opP->con1))
2294 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2;
2295 break;
2296 case '3':
2297 tmpreg&=0xFF;
2298 case '8':
2299 case 'C':
2300 install_operand(s[1],tmpreg);
2301 break;
2302 default:
2303 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s[1], __LINE__, __FILE__);
2304 }
2305 break;
2306
2307 case '+':
2308 case '-':
2309 case 'A':
2310 case 'a':
2311 install_operand(s[1],opP->reg-ADDR);
2312 break;
2313
2314 case 'B':
2315 tmpreg=get_num(opP->con1,80);
2316 switch(s[1]) {
2317 case 'B':
2318 /* Needs no offsetting */
2319 add_fix('B',opP->con1,1);
2320 break;
2321 case 'W':
2322 /* Offset the displacement to be relative to byte disp location */
2323 opP->con1->e_exp.X_add_number+=2;
2324 add_fix('w',opP->con1,1);
2325 addword(0);
2326 break;
2327 case 'L':
2328 long_branch:
2329 if (cpu_of_arch(current_architecture) < m68020) /* 68000 or 010 */
2330 as_warn("Can't use long branches on 68000/68010");
2331 the_ins.opcode[the_ins.numo-1]|=0xff;
2332 /* Offset the displacement to be relative to byte disp location */
2333 opP->con1->e_exp.X_add_number+=4;
2334 add_fix('l',opP->con1,1);
2335 addword(0);
2336 addword(0);
2337 break;
2338 case 'g':
2339 if(subs(opP->con1)) /* We can't relax it */
2340 goto long_branch;
2341
2342 /* This could either be a symbol, or an
2343 absolute address. No matter, the
2344 frag hacking will finger it out.
2345 Not quite: it can't switch from
2346 BRANCH to BCC68000 for the case
2347 where opnd is absolute (it needs
2348 to use the 68000 hack since no
2349 conditional abs jumps). */
2350 if (((cpu_of_arch(current_architecture) < m68020) || (0==adds(opP->con1)))
2351 && (the_ins.opcode[0] >= 0x6200)
2352 && (the_ins.opcode[0] <= 0x6f00)) {
2353 add_frag(adds(opP->con1),offs(opP->con1),TAB(BCC68000,SZ_UNDEF));
2354 } else {
3ad9ec6a 2355 add_frag(adds(opP->con1),offs(opP->con1),TAB(ABRANCH,SZ_UNDEF));
6d27d3a2
KR		 2356 }
2357 break;
2358 case 'w':
2359 if(isvar(opP->con1)) {
2360 /* check for DBcc instruction */
2361 if ((the_ins.opcode[0] & 0xf0f8) ==0x50c8) {
2362 /* size varies if patch */
2363 /* needed for long form */
2364 add_frag(adds(opP->con1),offs(opP->con1),TAB(DBCC,SZ_UNDEF));
2365 break;
2366 }
2367
2368 /* Don't ask! */
2369 opP->con1->e_exp.X_add_number+=2;
2370 add_fix('w',opP->con1,1);
2371 }
2372 addword(0);
2373 break;
2374 case 'C': /* Fixed size LONG coproc branches */
2375 the_ins.opcode[the_ins.numo-1]|=0x40;
2376 /* Offset the displacement to be relative to byte disp location */
2377 /* Coproc branches don't have a byte disp option, but they are
2378 compatible with the ordinary branches, which do... */
2379 opP->con1->e_exp.X_add_number+=4;
2380 add_fix('l',opP->con1,1);
2381 addword(0);
2382 addword(0);
2383 break;
2384 case 'c': /* Var size Coprocesssor branches */
2385 if(subs(opP->con1)) {
2386 add_fix('l',opP->con1,1);
2387 add_frag((symbolS *)0,(long)0,TAB(FBRANCH,LONG));
2388 } else if(adds(opP->con1)) {
2389 add_frag(adds(opP->con1),offs(opP->con1),TAB(FBRANCH,SZ_UNDEF));
2390 } else {
2391 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2392 the_ins.opcode[the_ins.numo-1]|=0x40;
2393 add_fix('l',opP->con1,1);
2394 addword(0);
2395 addword(4);
2396 }
2397 break;
2398 default:
2399 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2400 s[1], __LINE__, __FILE__);
2401 }
2402 break;
2403
2404 case 'C': /* Ignore it */
2405 break;
2406
2407 case 'd': /* JF this is a kludge */
2408 if(opP->mode==AOFF) {
2409 install_operand('s',opP->reg-ADDR);
2410 } else {
2411 char *tmpP;
2412
2413 tmpP=opP->con1->e_end-2;
2414 opP->con1->e_beg++;
2415 opP->con1->e_end-=4; /* point to the , */
2416 baseo=m68k_reg_parse(&tmpP);
2417 if(baseo<ADDR+0 || baseo>ADDR+7) {
2418 as_bad("Unknown address reg, using A0");
2419 baseo=0;
2420 } else baseo-=ADDR;
2421 install_operand('s',baseo);
2422 }
2423 tmpreg=get_num(opP->con1,80);
2424 if(!issword(tmpreg)) {
2425 as_warn("Expression out of range, using 0");
2426 tmpreg=0;
2427 }
2428 addword(tmpreg);
2429 break;
2430
2431 case 'D':
2432 install_operand(s[1],opP->reg-DATA);
2433 break;
2434
2435 case 'F':
2436 install_operand(s[1],opP->reg-FPREG);
2437 break;
2438
2439 case 'I':
2440 tmpreg=1+opP->reg-COPNUM;
2441 if(tmpreg==8)
2442 tmpreg=0;
2443 install_operand(s[1],tmpreg);
2444 break;
2445
2446 case 'J': /* JF foo */
2447 switch(opP->reg) {
2448 case SFC: tmpreg=0x000; break;
2449 case DFC: tmpreg=0x001; break;
2450 case CACR: tmpreg=0x002; break;
2451 case TC: tmpreg=0x003; break;
2452 case ITT0: tmpreg=0x004; break;
2453 case ITT1: tmpreg=0x005; break;
2454 case DTT0: tmpreg=0x006; break;
2455 case DTT1: tmpreg=0x007; break;
2456
2457 case USP: tmpreg=0x800; break;
2458 case VBR: tmpreg=0x801; break;
2459 case CAAR: tmpreg=0x802; break;
2460 case MSP: tmpreg=0x803; break;
2461 case ISP: tmpreg=0x804; break;
2462 case MMUSR: tmpreg=0x805; break;
2463 case URP: tmpreg=0x806; break;
2464 case SRP: tmpreg=0x807; break;
2465 default:
2466 as_fatal("failed sanity check.");
2467 }
2468 install_operand(s[1],tmpreg);
2469 break;
2470
2471 case 'k':
2472 tmpreg=get_num(opP->con1,55);
2473 install_operand(s[1],tmpreg&0x7f);
2474 break;
2475
2476 case 'l':
2477 tmpreg=opP->reg;
2478 if(s[1]=='w') {
2479 if(tmpreg&0x7FF0000)
2480 as_bad("Floating point register in register list");
2481 insop(reverse_16_bits(tmpreg));
2482 } else {
2483 if(tmpreg&0x700FFFF)
2484 as_bad("Wrong register in floating-point reglist");
2485 install_operand(s[1],reverse_8_bits(tmpreg>>16));
2486 }
2487 break;
2488
2489 case 'L':
2490 tmpreg=opP->reg;
2491 if(s[1]=='w') {
2492 if(tmpreg&0x7FF0000)
2493 as_bad("Floating point register in register list");
2494 insop(tmpreg);
2495 } else if(s[1]=='8') {
2496 if(tmpreg&0x0FFFFFF)
2497 as_bad("incorrect register in reglist");
2498 install_operand(s[1],tmpreg>>24);
2499 } else {
2500 if(tmpreg&0x700FFFF)
2501 as_bad("wrong register in floating-point reglist");
2502 else
2503 install_operand(s[1],tmpreg>>16);
2504 }
2505 break;
2506
2507 case 'M':
2508 install_operand(s[1],get_num(opP->con1,60));
2509 break;
2510
2511 case 'O':
2512 tmpreg= (opP->mode==DREG)
2513 ? 0x20+opP->reg-DATA
2514 : (get_num(opP->con1,40)&0x1F);
2515 install_operand(s[1],tmpreg);
2516 break;
2517
2518 case 'Q':
2519 tmpreg=get_num(opP->con1,10);
2520 if(tmpreg==8)
2521 tmpreg=0;
2522 install_operand(s[1],tmpreg);
2523 break;
2524
2525 case 'R':
c50140c8 2526 case 'r':
6d27d3a2
KR		 2527 /* This depends on the fact that ADDR registers are
2528 eight more than their corresponding DATA regs, so
2529 the result will have the ADDR_REG bit set */
2530 install_operand(s[1],opP->reg-DATA);
2531 break;
2532
2533 case 's':
2534 if(opP->reg==FPI) tmpreg=0x1;
2535 else if(opP->reg==FPS) tmpreg=0x2;
2536 else if(opP->reg==FPC) tmpreg=0x4;
2537 else as_fatal("failed sanity check.");
2538 install_operand(s[1],tmpreg);
2539 break;
2540
2541 case 'S': /* Ignore it */
2542 break;
2543
2544 case 'T':
2545 install_operand(s[1],get_num(opP->con1,30));
2546 break;
2547
2548 case 'U': /* Ignore it */
2549 break;
2550
2551 case 'c':
2552 switch (opP->reg) {
2553 case NC: tmpreg = 0; break;
2554 case DC: tmpreg = 1; break;
2555 case IC: tmpreg = 2; break;
2556 case BC: tmpreg = 3; break;
2557 default:
2558 as_fatal("failed sanity check");
2559 } /* switch on cache token */
2560 install_operand(s[1], tmpreg);
2561 break;
a39116f1 2562#ifndef NO_68851
6d27d3a2
KR		 2563 /* JF: These are out of order, I fear. */
2564 case 'f':
2565 switch (opP->reg) {
2566 case SFC:
2567 tmpreg=0;
2568 break;
2569 case DFC:
2570 tmpreg=1;
2571 break;
2572 default:
2573 as_fatal("failed sanity check.");
2574 }
2575 install_operand(s[1],tmpreg);
2576 break;
2577
2578 case 'P':
2579 switch(opP->reg) {
2580 case TC:
2581 tmpreg=0;
2582 break;
2583 case CAL:
2584 tmpreg=4;
2585 break;
2586 case VAL:
2587 tmpreg=5;
2588 break;
2589 case SCC:
2590 tmpreg=6;
2591 break;
2592 case AC:
2593 tmpreg=7;
2594 break;
2595 default:
2596 as_fatal("failed sanity check.");
2597 }
2598 install_operand(s[1],tmpreg);
2599 break;
2600
2601 case 'V':
2602 if (opP->reg == VAL)
2603 break;
2604 as_fatal("failed sanity check.");
2605
2606 case 'W':
2607 switch(opP->reg) {
2608
2609 case DRP:
2610 tmpreg=1;
2611 break;
2612 case SRP:
2613 tmpreg=2;
2614 break;
2615 case CRP:
2616 tmpreg=3;
2617 break;
2618 default:
2619 as_fatal("failed sanity check.");
2620 }
2621 install_operand(s[1],tmpreg);
2622 break;
2623
2624 case 'X':
2625 switch (opP->reg) {
2626 case BAD: case BAD+1: case BAD+2: case BAD+3:
2627 case BAD+4: case BAD+5: case BAD+6: case BAD+7:
2628 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2629 break;
2630
2631 case BAC: case BAC+1: case BAC+2: case BAC+3:
2632 case BAC+4: case BAC+5: case BAC+6: case BAC+7:
2633 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2634 break;
2635
2636 default:
2637 as_fatal("failed sanity check.");
2638 }
2639 install_operand(s[1], tmpreg);
2640 break;
2641 case 'Y':
2642 know(opP->reg == PSR);
2643 break;
2644 case 'Z':
2645 know(opP->reg == PCSR);
2646 break;
f8701a3f 2647#endif /* m68851 */
4134a793
KR		 2648 case '3':
2649 switch (opP->reg)
2650 {
2651 case TT0:
2652 tmpreg = 2;
2653 break;
2654 case TT1:
2655 tmpreg = 3;
2656 break;
2657 default:
2658 as_fatal ("failed sanity check");
2659 }
2660 install_operand (s[1], tmpreg);
2661 break;
2662 case 't':
2663 tmpreg = get_num (opP->con1, 20);
2664 install_operand (s[1], tmpreg);
2665 break;
2666 case '_': /* used only for move16 absolute 32-bit address */
6d27d3a2 2667 tmpreg=get_num(opP->con1,80);
065b6303
ILT		 2668 addword (tmpreg >> 16);
2669 addword (tmpreg & 0xFFFF);
6d27d3a2
KR		 2670 break;
2671 default:
4134a793
KR		 2672 as_fatal("Internal error: Operand type %c unknown in line %d of file \"%s\"",
2673 s[0], __LINE__, __FILE__);
6d27d3a2
KR		 2674 }
2675 }
3ad9ec6a 2676
6d27d3a2
KR		 2677 /* By the time whe get here (FINALLY) the_ins contains the complete
2678 instruction, ready to be emitted. . . */
7c15cbe8
RP		 2679} /* m68k_ip() */
2680
2681/*
2682 * get_regs := '/' + ?
2683 * | '-' + <register>
2684 * | '-' + <register> + ?
2685 * | <empty>
2686 * ;
2687 *
6d27d3a2 2688
7c15cbe8
RP		 2689 * The idea here must be to scan in a set of registers but I don't
2690 * understand it. Looks awfully sloppy to me but I don't have any doc on
2691 * this format so...
6d27d3a2
KR		 2692
2693 *
7c15cbe8
RP		 2694 *
2695 */
fecd2382
RP		 2696
2697static int get_regs(i,str,opP)
f8701a3f
SC		 2698int i;
2699struct m68k_op *opP;
2700char *str;
fecd2382 2701{
f8701a3f
SC		 2702 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2703 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2704 unsigned long cur_regs = 0;
2705 int reg1,
2706 reg2;
6d27d3a2 2707
fecd2382 2708#define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
a39116f1
RP		 2709else if(x==FPS) cur_regs|=(1<<25);\
2710else if(x==FPC) cur_regs|=(1<<26);\
2711else cur_regs|=(1<<(x-1)); }
6d27d3a2 2712
f8701a3f
SC		 2713 reg1=i;
2714 for(;;) {
2715 if(*str=='/') {
2716 ADD_REG(reg1);
2717 str++;
2718 } else if(*str=='-') {
2719 str++;
2720 reg2=m68k_reg_parse(&str);
2721 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) {
2722 opP->error="unknown register in register list";
2723 return FAIL;
2724 }
2725 while(reg1<=reg2) {
2726 ADD_REG(reg1);
2727 reg1++;
2728 }
2729 if(*str=='\0')
2730 break;
2731 } else if(*str=='\0') {
2732 ADD_REG(reg1);
2733 break;
2734 } else {
2735 opP->error="unknow character in register list";
2736 return FAIL;
2737 }
2738 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2739 if (*str=='/')
2740 str ++;
2741 reg1=m68k_reg_parse(&str);
2742 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) {
2743 opP->error="unknown register in register list";
2744 return FAIL;
2745 }
a39116f1 2746 }
f8701a3f
SC		 2747 opP->reg=cur_regs;
2748 return OK;
fecd2382
RP		 2749} /* get_regs() */
2750
2751static int reverse_16_bits(in)
f8701a3f 2752int in;
fecd2382 2753{
f8701a3f
SC		 2754 int out=0;
2755 int n;
6d27d3a2 2756
f8701a3f
SC		 2757 static int mask[16] = {
2758 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2759 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2760 };
2761 for(n=0;n<16;n++) {
2762 if(in&mask[n])
2763 out|=mask[15-n];
2764 }
2765 return out;
fecd2382
RP		 2766} /* reverse_16_bits() */
2767
2768static int reverse_8_bits(in)
f8701a3f 2769int in;
fecd2382 2770{
f8701a3f
SC		 2771 int out=0;
2772 int n;
6d27d3a2 2773
f8701a3f
SC		 2774 static int mask[8] = {
2775 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2776 };
6d27d3a2 2777
f8701a3f
SC		 2778 for(n=0;n<8;n++) {
2779 if(in&mask[n])
2780 out|=mask[7-n];
2781 }
2782 return out;
fecd2382
RP		 2783} /* reverse_8_bits() */
2784
2785static void install_operand(mode,val)
f8701a3f
SC		 2786int mode;
2787int val;
fecd2382 2788{
f8701a3f
SC		 2789 switch(mode) {
2790 case 's':
2791 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */
2792 break;
2793 case 'd':
2794 the_ins.opcode[0]|=val<<9;
2795 break;
2796 case '1':
2797 the_ins.opcode[1]|=val<<12;
2798 break;
2799 case '2':
2800 the_ins.opcode[1]|=val<<6;
2801 break;
2802 case '3':
2803 the_ins.opcode[1]|=val;
2804 break;
2805 case '4':
2806 the_ins.opcode[2]|=val<<12;
2807 break;
2808 case '5':
2809 the_ins.opcode[2]|=val<<6;
2810 break;
2811 case '6':
2812 /* DANGER! This is a hack to force cas2l and cas2w cmds
2813 to be three words long! */
2814 the_ins.numo++;
2815 the_ins.opcode[2]|=val;
2816 break;
2817 case '7':
2818 the_ins.opcode[1]|=val<<7;
2819 break;
2820 case '8':
2821 the_ins.opcode[1]|=val<<10;
2822 break;
2823#ifndef NO_68851
2824 case '9':
2825 the_ins.opcode[1]|=val<<5;
2826 break;
2827#endif
6d27d3a2 2828
f8701a3f
SC		 2829 case 't':
2830 the_ins.opcode[1]|=(val<<10)|(val<<7);
2831 break;
2832 case 'D':
2833 the_ins.opcode[1]|=(val<<12)|val;
2834 break;
2835 case 'g':
2836 the_ins.opcode[0]|=val=0xff;
2837 break;
2838 case 'i':
2839 the_ins.opcode[0]|=val<<9;
2840 break;
2841 case 'C':
2842 the_ins.opcode[1]|=val;
2843 break;
2844 case 'j':
2845 the_ins.opcode[1]|=val;
2846 the_ins.numo++; /* What a hack */
2847 break;
2848 case 'k':
2849 the_ins.opcode[1]|=val<<4;
2850 break;
2851 case 'b':
2852 case 'w':
2853 case 'l':
2854 break;
2855 case 'e':
2856 the_ins.opcode[0] |= (val << 6);
2857 break;
2858 case 'L':
2859 the_ins.opcode[1] = (val >> 16);
2860 the_ins.opcode[2] = val & 0xffff;
2861 break;
2862 case 'c':
2863 default:
2864 as_fatal("failed sanity check.");
2865 }
fecd2382
RP		 2866} /* install_operand() */
2867
2868static void install_gen_operand(mode,val)
f8701a3f
SC		 2869int mode;
2870int val;
fecd2382 2871{
f8701a3f
SC		 2872 switch(mode) {
2873 case 's':
2874 the_ins.opcode[0]|=val;
2875 break;
2876 case 'd':
2877 /* This is a kludge!!! */
2878 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3;
2879 break;
2880 case 'b':
2881 case 'w':
2882 case 'l':
2883 case 'f':
2884 case 'F':
2885 case 'x':
2886 case 'p':
2887 the_ins.opcode[0]|=val;
2888 break;
2889 /* more stuff goes here */
2890 default:
2891 as_fatal("failed sanity check.");
2892 }
fecd2382
RP		 2893} /* install_gen_operand() */
2894
7c15cbe8
RP		 2895/*
2896 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2897 * then deal with the bitfield hack.
2898 */
2899
fecd2382 2900static char *crack_operand(str,opP)
f8701a3f
SC		 2901register char *str;
2902register struct m68k_op *opP;
fecd2382 2903{
f8701a3f
SC		 2904 register int parens;
2905 register int c;
2906 register char *beg_str;
6d27d3a2 2907
f8701a3f
SC		 2908 if(!str) {
2909 return str;
2910 }
2911 beg_str=str;
2912 for(parens=0;*str && (parens>0 || notend(str));str++) {
2913 if(*str=='(') parens++;
2914 else if(*str==')') {
2915 if(!parens) { /* ERROR */
2916 opP->error="Extra )";
2917 return str;
2918 }
2919 --parens;
2920 }
2921 }
2922 if(!*str && parens) { /* ERROR */
2923 opP->error="Missing )";
2924 return str;
2925 }
2926 c= *str;
2927 *str='\0';
2928 if(m68k_ip_op(beg_str,opP)==FAIL) {
2929 *str=c;
fecd2382
RP		 2930 return str;
2931 }
2932 *str=c;
f8701a3f
SC		 2933 if(c=='}')
2934 c= *++str; /* JF bitfield hack */
2935 if(c) {
2936 c= *++str;
2937 if(!c)
2938 as_bad("Missing operand");
2939 }
fecd2382
RP		 2940 return str;
2941}
2942
2943/* See the comment up above where the #define notend(... is */
2944#if 0
2945notend(s)
f8701a3f 2946char *s;
fecd2382 2947{
f8701a3f
SC		 2948 if(*s==',') return 0;
2949 if(*s=='{' || *s=='}')
2950 return 0;
2951 if(*s!=':') return 1;
2952 /* This kludge here is for the division cmd, which is a kludge */
2953 if(index("aAdD#",s[1])) return 0;
2954 return 1;
fecd2382
RP		 2955}
2956#endif
2957
2958/* This is the guts of the machine-dependent assembler. STR points to a
7c15cbe8 2959 machine dependent instruction. This function is supposed to emit
fecd2382 2960 the frags/bytes it assembles to.
a39116f1 2961 */
a933d598
SC		 2962
2963void
2964insert_reg(regname, regnum)
2965char *regname;
2966int regnum;
2967{
2968 char buf[100];
2969 int i;
2970 symbol_table_insert(symbol_new(regname, SEG_REGISTER, regnum, &zero_address_frag));
2971
2972 for (i = 0; regname[i]; i++)
2973 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2974 buf[i] = '\0';
6d27d3a2 2975
a933d598
SC		 2976 symbol_table_insert(symbol_new(buf, SEG_REGISTER, regnum, &zero_address_frag));
2977}
2978
4134a793 2979static const struct {
6d27d3a2 2980char *name;
a933d598 2981int number;
4134a793 2982} init_table[] = {
a933d598
SC		 2983 "d0", DATA0,
2984 "d1", DATA1,
2985 "d2", DATA2,
2986 "d3", DATA3,
2987 "d4", DATA4,
2988 "d5", DATA5,
2989 "d6", DATA6,
2990 "d7", DATA7,
2991 "a0", ADDR0,
2992 "a1", ADDR1,
2993 "a2", ADDR2,
2994 "a3", ADDR3,
2995 "a4", ADDR4,
2996 "a5", ADDR5,
2997 "a6", ADDR6,
2998 "fp", ADDR6,
2999 "a7", ADDR7,
3000 "sp", ADDR7,
3001 "fp0", FP0,
3002 "fp1", FP1,
3003 "fp2", FP2,
3004 "fp3", FP3,
3005 "fp4", FP4,
3006 "fp5", FP5,
3007 "fp6", FP6,
3008 "fp7", FP7,
3009 "fpi", FPI,
3010 "fpiar", FPI,
3011 "fpc", FPI,
3012 "fps", FPS,
3013 "fpsr", FPS,
3014 "fpc", FPC,
3015 "fpcr", FPC,
3016
3017 "cop0", COP0,
3018 "cop1", COP1,
3019 "cop2", COP2,
3020 "cop3", COP3,
3021 "cop4", COP4,
3022 "cop5", COP5,
3023 "cop6", COP6,
3024 "cop7", COP7,
6d27d3a2
KR		 3025 "pc", PC,
3026 "zpc", ZPC,
3027 "sr", SR,
a933d598 3028
6d27d3a2
KR		 3029 "ccr", CCR,
3030 "cc", CCR,
a933d598 3031
6d27d3a2
KR		 3032 "usp", USP,
3033 "isp", ISP,
a933d598
SC		 3034 "sfc", SFC,
3035 "dfc", DFC,
3036 "cacr", CACR,
3037 "caar", CAAR,
3038
3039 "vbr", VBR,
3040
3041 "msp", MSP,
3042 "itt0", ITT0,
3043 "itt1", ITT1,
3044 "dtt0", DTT0,
3045 "dtt1", DTT1,
3046 "mmusr", MMUSR,
3047 "tc", TC,
3048 "srp", SRP,
3049 "urp", URP,
3050
a933d598
SC		 3051 "ac", AC,
3052 "bc", BC,
3053 "cal", CAL,
3054 "crp", CRP,
3055 "drp", DRP,
3056 "pcsr", PCSR,
3057 "psr", PSR,
3058 "scc", SCC,
3059 "val", VAL,
3060 "bad0", BAD0,
3061 "bad1", BAD1,
3062 "bad2", BAD2,
3063 "bad3", BAD3,
3064 "bad4", BAD4,
3065 "bad5", BAD5,
3066 "bad6", BAD6,
3067 "bad7", BAD7,
3068 "bac0", BAC0,
3069 "bac1", BAC1,
3070 "bac2", BAC2,
3071 "bac3", BAC3,
3072 "bac4", BAC4,
3073 "bac5", BAC5,
3074 "bac6", BAC6,
3075 "bac7", BAC7,
a933d598
SC		 3076
3077 "ic", IC,
3078 "dc", DC,
3079 "nc", NC,
3080
4134a793
KR		 3081 "tt0", TT0,
3082 "tt1", TT1,
3083 /* 68ec030 versions of same */
3084 "ac0", TT0,
3085 "ac1", TT1,
3086 /* 68ec030 access control unit, identical to 030 MMU status reg */
3087 "acusr", PSR,
3088
a933d598
SC		 3089 0,
3090
3091};
3092
3093
3094void
3095init_regtable()
3096{
3097 int i;
6d27d3a2 3098 for (i = 0; init_table[i].name; i++)
a933d598 3099 insert_reg(init_table[i].name, init_table[i].number);
a933d598 3100}
6d27d3a2 3101
df3768fb 3102static int no_68851, no_68881;
a933d598 3103
fecd2382 3104void
6d27d3a2
KR		 3105md_assemble(str)
3106 char *str;
fecd2382 3107{
f8701a3f
SC		 3108 char *er;
3109 short *fromP;
3110 char *toP = NULL;
3111 int m,n = 0;
3112 char *to_beg_P;
3113 int shorts_this_frag;
4134a793 3114 static int done_first_time;
6d27d3a2 3115
4134a793 3116 if (!done_first_time)
148eb5dd 3117 {
4134a793
KR		 3118 done_first_time = 1;
3119
3120 if (cpu_of_arch (current_architecture) == 0)
3121 {
df3768fb 3122 int cpu_type;
148eb5dd
ILT		 3123
3124#ifndef TARGET_CPU
4134a793 3125 cpu_type = m68020;
148eb5dd 3126#else
4134a793
KR		 3127 if (strcmp (TARGET_CPU, "m68000") == 0)
3128 cpu_type = m68000;
3129 else if (strcmp (TARGET_CPU, "m68010") == 0)
3130 cpu_type = m68010;
3131 else if (strcmp (TARGET_CPU, "m68020") == 0
3132 || strcmp (TARGET_CPU, "m68k") == 0)
3133 cpu_type = m68020;
3134 else if (strcmp (TARGET_CPU, "m68030") == 0)
3135 cpu_type = m68030;
3136 else if (strcmp (TARGET_CPU, "m68040") == 0)
3137 cpu_type = m68040;
df3768fb
KR		 3138 else if (strcmp (TARGET_CPU, "cpu32") == 0)
3139 cpu_type = cpu32;
4134a793
KR		 3140 else
3141 cpu_type = m68020;
148eb5dd
ILT		 3142#endif
3143
df3768fb 3144 current_architecture |= cpu_type;
4134a793 3145 }
df3768fb
KR		 3146 if (current_architecture & m68881)
3147 {
3148 if (current_architecture & m68000)
3149 as_bad ("incompatible processors 68000 and 68881/2 specified");
3150 if (current_architecture & m68010)
3151 as_bad ("incompatible processors 68010 and 68881/2 specified");
3152 if (current_architecture & m68040)
3153 as_bad ("incompatible processors 68040 and 68881/2 specified");
3154 }
3155 /* What other incompatibilities ought we to check for? */
3156
3157 /* Toss in some default assumptions about coprocessors. */
3158 if (!no_68881
3159 && (cpu_of_arch (current_architecture)
3160 /* Can CPU32 have a 68881 coprocessor?? */
3161 & (m68020 | m68030 | cpu32)))
4134a793 3162 {
df3768fb 3163 current_architecture |= m68881;
148eb5dd 3164 }
df3768fb
KR		 3165 if (!no_68851
3166 && (cpu_of_arch (current_architecture) & m68020up) != 0)
3167 {
3168 current_architecture |= m68851;
3169 }
3170 if (no_68881 && (current_architecture & m68881))
3171 as_bad ("options for 68881 and no-68881 both given");
3172 if (no_68851 && (current_architecture & m68851))
3173 as_bad ("options for 68851 and no-68851 both given");
4134a793 3174 done_first_time = 1;
148eb5dd 3175 }
6d27d3a2 3176
f8701a3f
SC		 3177 memset((char *)(&the_ins), '\0', sizeof(the_ins)); /* JF for paranoia sake */
3178 m68k_ip(str);
3179 er=the_ins.error;
3180 if(!er) {
3181 for(n=the_ins.numargs;n;--n)
3182 if(the_ins.operands[n].error) {
3183 er=the_ins.operands[n].error;
3184 break;
3185 }
fecd2382 3186 }
f8701a3f 3187 if(er) {
6d27d3a2 3188 as_bad("%s -- statement `%s' ignored",er,str);
f8701a3f 3189 return;
fecd2382 3190 }
6d27d3a2 3191
f8701a3f
SC		 3192 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */
3193 toP=frag_more(2*the_ins.numo);
3194 fromP= &the_ins.opcode[0];
3195 for(m=the_ins.numo;m;--m) {
3196 md_number_to_chars(toP,(long)(*fromP),2);
3197 toP+=2;
3198 fromP++;
3199 }
3200 /* put out symbol-dependent info */
3201 for(m=0;m<the_ins.nrel;m++) {
3202 switch(the_ins.reloc[m].wid) {
3203 case 'B':
3204 n=1;
3205 break;
3206 case 'b':
3207 n=1;
3208 break;
3209 case '3':
3210 n=2;
3211 break;
3212 case 'w':
3213 n=2;
3214 break;
3215 case 'l':
3216 n=4;
3217 break;
3218 default:
3219 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid);
3220 }
6d27d3a2 3221
f8701a3f
SC		 3222 fix_new(frag_now,
3223 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3224 n,
3225 the_ins.reloc[m].add,
3226 the_ins.reloc[m].sub,
3227 the_ins.reloc[m].off,
3228 the_ins.reloc[m].pcrel,
3229 NO_RELOC);
3230 }
3231 return;
3232 }
6d27d3a2 3233
f8701a3f
SC		 3234 /* There's some frag hacking */
3235 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) {
3236 int wid;
6d27d3a2 3237
f8701a3f
SC		 3238 if(n==0) wid=2*the_ins.fragb[n].fragoff;
3239 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff);
3240 toP=frag_more(wid);
3241 to_beg_P=toP;
3242 shorts_this_frag=0;
3243 for(m=wid/2;m;--m) {
3244 md_number_to_chars(toP,(long)(*fromP),2);
3245 toP+=2;
3246 fromP++;
3247 shorts_this_frag++;
3248 }
3249 for(m=0;m<the_ins.nrel;m++) {
3250 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) {
3251 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */;
3252 break;
3253 }
3254 wid=the_ins.reloc[m].wid;
3255 if(wid==0)
3256 continue;
3257 the_ins.reloc[m].wid=0;
3258 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
6d27d3a2 3259
f8701a3f
SC		 3260 fix_new(frag_now,
3261 (toP-frag_now->fr_literal)-the_ins.numo*2+the_ins.reloc[m].n,
3262 wid,
3263 the_ins.reloc[m].add,
3264 the_ins.reloc[m].sub,
3265 the_ins.reloc[m].off,
3266 the_ins.reloc[m].pcrel,
3267 NO_RELOC);
3268 }
3269 /* know(the_ins.fragb[n].fadd); */
3270 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty),
3271 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P);
3272 }
3273 n=(the_ins.numo-the_ins.fragb[n-1].fragoff);
fecd2382 3274 shorts_this_frag=0;
f8701a3f
SC		 3275 if(n) {
3276 toP=frag_more(n*sizeof(short));
3277 while(n--) {
3278 md_number_to_chars(toP,(long)(*fromP),2);
3279 toP+=2;
3280 fromP++;
3281 shorts_this_frag++;
3282 }
fecd2382
RP		 3283 }
3284 for(m=0;m<the_ins.nrel;m++) {
f8701a3f 3285 int wid;
6d27d3a2 3286
f8701a3f
SC		 3287 wid=the_ins.reloc[m].wid;
3288 if(wid==0)
3289 continue;
3290 the_ins.reloc[m].wid=0;
3291 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000;
6d27d3a2 3292
f8701a3f
SC		 3293 fix_new(frag_now,
3294 (the_ins.reloc[m].n + toP-frag_now->fr_literal)-/* the_ins.numo */ shorts_this_frag*2,
3295 wid,
3296 the_ins.reloc[m].add,
3297 the_ins.reloc[m].sub,
3298 the_ins.reloc[m].off,
3299 the_ins.reloc[m].pcrel,
3300 NO_RELOC);
fecd2382
RP		 3301 }
3302}
3303
f8701a3f 3304
f8701a3f 3305
fecd2382 3306void
a39116f1 3307 md_begin()
fecd2382 3308{
f8701a3f
SC		 3309 /*
3310 * md_begin -- set up hash tables with 68000 instructions.
3311 * similar to what the vax assembler does. ---phr
3312 */
3313 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3314 a copy of it at runtime, adding in the information we want but isn't
3315 there. I think it'd be better to have an awk script hack the table
3316 at compile time. Or even just xstr the table and use it as-is. But
3317 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3318 names. */
6d27d3a2 3319
f8701a3f
SC		 3320 register const struct m68k_opcode *ins;
3321 register struct m68k_incant *hack,
3322 *slak;
3323 register char *retval = 0; /* empty string, or error msg text */
3324 register unsigned int i;
3325 register char c;
6d27d3a2 3326
f8701a3f
SC		 3327 if ((op_hash = hash_new()) == NULL)
3328 as_fatal("Virtual memory exhausted");
6d27d3a2 3329
f8701a3f
SC		 3330 obstack_begin(&robyn,4000);
3331 for (ins = m68k_opcodes; ins < endop; ins++) {
3332 hack=slak=(struct m68k_incant *)obstack_alloc(&robyn,sizeof(struct m68k_incant));
3333 do {
3334 /* we *could* ignore insns that don't match our
3335 arch here but just leaving them out of the
3336 hash. */
3337 slak->m_operands=ins->args;
3338 slak->m_opnum=strlen(slak->m_operands)/2;
3339 slak->m_arch = ins->arch;
3340 slak->m_opcode=ins->opcode;
3341 /* This is kludgey */
3342 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1;
3343 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) {
3344 slak->m_next=(struct m68k_incant *) obstack_alloc(&robyn,sizeof(struct m68k_incant));
3345 ins++;
3346 } else
3347 slak->m_next=0;
3348 slak=slak->m_next;
3349 } while(slak);
6d27d3a2 3350
f8701a3f
SC		 3351 retval = hash_insert (op_hash, ins->name,(char *)hack);
3352 /* Didn't his mommy tell him about null pointers? */
3353 if(retval && *retval)
3ad9ec6a 3354 as_bad("Internal Error: Can't hash %s: %s",ins->name,retval);
f8701a3f 3355 }
6d27d3a2 3356
f8701a3f
SC		 3357 for (i = 0; i < sizeof(mklower_table) ; i++)
3358 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c;
6d27d3a2 3359
f8701a3f
SC		 3360 for (i = 0 ; i < sizeof(notend_table) ; i++) {
3361 notend_table[i] = 0;
3362 alt_notend_table[i] = 0;
3363 }
3364 notend_table[','] = 1;
3365 notend_table['{'] = 1;
3366 notend_table['}'] = 1;
3367 alt_notend_table['a'] = 1;
3368 alt_notend_table['A'] = 1;
3369 alt_notend_table['d'] = 1;
3370 alt_notend_table['D'] = 1;
3371 alt_notend_table['#'] = 1;
3372 alt_notend_table['f'] = 1;
3373 alt_notend_table['F'] = 1;
fecd2382 3374#ifdef REGISTER_PREFIX
f8701a3f 3375 alt_notend_table[REGISTER_PREFIX] = 1;
fecd2382 3376#endif
0069b1f6
ILT		 3377#ifdef OPTIONAL_REGISTER_PREFIX
3378 alt_notend_table[OPTIONAL_REGISTER_PREFIX] = 1;
3379#endif
f8701a3f 3380
3ad9ec6a
ILT		 3381#ifndef MIT_SYNTAX_ONLY
3382 /* Insert pseudo ops, these have to go into the opcode table since
3383 gas expects pseudo ops to start with a dot */
3384 {
3385 int n = 0;
3386 while (mote_pseudo_table[n].poc_name)
3387 {
3388 hack=(struct m68k_incant *)
3389 obstack_alloc(&robyn,sizeof(struct m68k_incant));
3390 hash_insert(op_hash,
3391 mote_pseudo_table[n].poc_name, (char *)hack);
3392 hack->m_operands = 0;
3393 hack->m_opnum = n;
3394 n++;
3395 }
3396 }
3397#endif
3398
f8701a3f 3399 init_regtable();
fecd2382
RP		 3400}
3401
3402#if 0
3403#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
a39116f1
RP		 3404 || (*s == ':' && strchr("aAdD#", s[1]))) \
3405 ? 0 : 1)
fecd2382
RP		 3406#endif
3407
3408/* This funciton is called once, before the assembler exits. It is
3409 supposed to do any final cleanup for this part of the assembler.
a39116f1 3410 */
fecd2382 3411void
a39116f1 3412 md_end()
fecd2382
RP		 3413{
3414}
3415
3416/* Equal to MAX_PRECISION in atof-ieee.c */
3417#define MAX_LITTLENUMS 6
3418
3419/* Turn a string in input_line_pointer into a floating point constant of type
3420 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3421 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
a39116f1 3422 */
fecd2382 3423char *
a39116f1 3424 md_atof(type,litP,sizeP)
fecd2382
RP		 3425char type;
3426char *litP;
3427int *sizeP;
3428{
f8701a3f
SC		 3429 int prec;
3430 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3431 LITTLENUM_TYPE *wordP;
3432 char *t;
3433 char *atof_ieee();
6d27d3a2 3434
f8701a3f
SC		 3435 switch(type) {
3436 case 'f':
3437 case 'F':
3438 case 's':
3439 case 'S':
3440 prec = 2;
3441 break;
6d27d3a2 3442
f8701a3f
SC		 3443 case 'd':
3444 case 'D':
3445 case 'r':
3446 case 'R':
3447 prec = 4;
3448 break;
6d27d3a2 3449
f8701a3f
SC		 3450 case 'x':
3451 case 'X':
3452 prec = 6;
3453 break;
6d27d3a2 3454
f8701a3f
SC		 3455 case 'p':
3456 case 'P':
3457 prec = 6;
3458 break;
6d27d3a2 3459
f8701a3f
SC		 3460 default:
3461 *sizeP=0;
3462 return "Bad call to MD_ATOF()";
3463 }
3464 t=atof_ieee(input_line_pointer,type,words);
3465 if(t)
3466 input_line_pointer=t;
6d27d3a2 3467
f8701a3f
SC		 3468 *sizeP=prec * sizeof(LITTLENUM_TYPE);
3469 for(wordP=words;prec--;) {
3470 md_number_to_chars(litP,(long)(*wordP++),sizeof(LITTLENUM_TYPE));
3471 litP+=sizeof(LITTLENUM_TYPE);
3472 }
3473 return ""; /* Someone should teach Dean about null pointers */
fecd2382
RP		 3474}
3475
3476/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3477 for use in the a.out file, and stores them in the array pointed to by buf.
3478 This knows about the endian-ness of the target machine and does
3479 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3480 2 (short) and 4 (long) Floating numbers are put out as a series of
3481 LITTLENUMS (shorts, here at least)
a39116f1 3482 */
fecd2382 3483void
a39116f1 3484 md_number_to_chars(buf,val,n)
fecd2382
RP		 3485char *buf;
3486long val;
3487int n;
3488{
f8701a3f
SC		 3489 switch(n) {
3490 case 1:
3491 *buf++=val;
3492 break;
3493 case 2:
3494 *buf++=(val>>8);
3495 *buf++=val;
3496 break;
3497 case 4:
3498 *buf++=(val>>24);
3499 *buf++=(val>>16);
3500 *buf++=(val>>8);
3501 *buf++=val;
3502 break;
3503 default:
3504 as_fatal("failed sanity check.");
3505 }
fecd2382
RP		 3506}
3507
3508void
a39116f1
RP		 3509 md_apply_fix(fixP, val)
3510fixS *fixP;
3511long val;
fecd2382 3512{
587c4264
ILT		 3513#ifdef IBM_COMPILER_SUX
3514 /* This is unnecessary but it convinces the native rs6000
3515 compiler to generate the code we want. */
3516 char *buf = fixP->fx_frag->fr_literal;
3517 buf += fixP->fx_where;
3518#else /* IBM_COMPILER_SUX */
f8701a3f 3519 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
587c4264 3520#endif /* IBM_COMPILER_SUX */
6d27d3a2 3521
f8701a3f
SC		 3522 switch(fixP->fx_size) {
3523 case 1:
3524 *buf++=val;
3525 break;
3526 case 2:
3527 *buf++=(val>>8);
3528 *buf++=val;
3529 break;
3530 case 4:
3531 *buf++=(val>>24);
3532 *buf++=(val>>16);
3533 *buf++=(val>>8);
3534 *buf++=val;
3535 break;
3536 default:
3537 BAD_CASE (fixP->fx_size);
3538 }
fecd2382
RP		 3539}
3540
3541
3542/* *fragP has been relaxed to its final size, and now needs to have
3543 the bytes inside it modified to conform to the new size There is UGLY
3544 MAGIC here. ..
a39116f1 3545 */
fecd2382 3546void
a39116f1 3547 md_convert_frag(headers, fragP)
f6e504fe 3548object_headers *headers;
fecd2382
RP		 3549register fragS *fragP;
3550{
f8701a3f
SC		 3551 long disp;
3552 long ext = 0;
6d27d3a2 3553
f8701a3f
SC		 3554 /* Address in object code of the displacement. */
3555 register int object_address = fragP -> fr_fix + fragP -> fr_address;
6d27d3a2 3556
f6e504fe 3557#ifdef IBM_COMPILER_SUX
f8701a3f
SC		 3558 /* This is wrong but it convinces the native rs6000 compiler to
3559 generate the code we want. */
3560 register char *buffer_address = fragP -> fr_literal;
3561 buffer_address += fragP -> fr_fix;
f6e504fe 3562#else /* IBM_COMPILER_SUX */
f8701a3f
SC		 3563 /* Address in gas core of the place to store the displacement. */
3564 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
f6e504fe 3565#endif /* IBM_COMPILER_SUX */
6d27d3a2 3566
f8701a3f 3567 /* No longer true: know(fragP->fr_symbol); */
6d27d3a2 3568
f8701a3f
SC		 3569 /* The displacement of the address, from current location. */
3570 disp = fragP->fr_symbol ? S_GET_VALUE(fragP->fr_symbol) : 0;
3571 disp = (disp + fragP->fr_offset) - object_address;
6d27d3a2 3572
f8701a3f
SC		 3573 switch(fragP->fr_subtype) {
3574 case TAB(BCC68000,BYTE):
3ad9ec6a 3575 case TAB(ABRANCH,BYTE):
a39116f1
RP		 3576 know(issbyte(disp));
3577 if(disp==0)
3578 as_bad("short branch with zero offset: use :w");
3579 fragP->fr_opcode[1]=disp;
fecd2382 3580 ext=0;
a39116f1 3581 break;
f8701a3f
SC		 3582 case TAB(DBCC,SHORT):
3583 know(issword(disp));
a39116f1
RP		 3584 ext=2;
3585 break;
f8701a3f 3586 case TAB(BCC68000,SHORT):
3ad9ec6a 3587 case TAB(ABRANCH,SHORT):
f8701a3f 3588 know(issword(disp));
a39116f1
RP		 3589 fragP->fr_opcode[1]=0x00;
3590 ext=2;
3591 break;
3ad9ec6a 3592 case TAB(ABRANCH,LONG):
f8701a3f
SC		 3593 if (cpu_of_arch(current_architecture) < m68020) {
3594 if (fragP->fr_opcode[0]==0x61) {
3595 fragP->fr_opcode[0]= 0x4E;
3596 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3597 subseg_change(SEG_TEXT, 0);
6d27d3a2 3598
f8701a3f
SC		 3599 fix_new(fragP,
3600 fragP->fr_fix,
3601 4,
3602 fragP->fr_symbol,
3603 0,
3604 fragP->fr_offset,
3605 0,
3606 NO_RELOC);
6d27d3a2 3607
f8701a3f
SC		 3608 fragP->fr_fix+=4;
3609 ext=0;
3610 } else if (fragP->fr_opcode[0]==0x60) {
3611 fragP->fr_opcode[0]= 0x4E;
3612 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3613 subseg_change(SEG_TEXT, 0);
3614 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset,0,
3615 NO_RELOC);
3616 fragP->fr_fix+=4;
3617 ext=0;
3618 } else {
3619 as_bad("Long branch offset not supported.");
3620 }
3621 } else {
3622 fragP->fr_opcode[1]=0xff;
3623 ext=4;
3624 }
3625 break;
3626 case TAB(BCC68000,LONG):
3627 /* only Bcc 68000 instructions can come here */
3628 /* change bcc into b!cc/jmp absl long */
3629 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
fecd2382 3630 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */
6d27d3a2 3631
fecd2382
RP		 3632 /* JF: these used to be fr_opcode[2,3], but they may be in a
3633 different frag, in which case refering to them is a no-no.
3634 Only fr_opcode[0,1] are guaranteed to work. */
6d27d3a2
KR		 3635 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3636 *buffer_address++ = 0xf9;
fecd2382
RP		 3637 fragP->fr_fix += 2; /* account for jmp instruction */
3638 subseg_change(SEG_TEXT,0);
6d27d3a2 3639 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
a39116f1
RP		 3640 fragP->fr_offset,0,
3641 NO_RELOC);
fecd2382
RP		 3642 fragP->fr_fix += 4;
3643 ext=0;
3644 break;
f8701a3f
SC		 3645 case TAB(DBCC,LONG):
3646 /* only DBcc 68000 instructions can come here */
3647 /* change dbcc into dbcc/jmp absl long */
3648 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3649 *buffer_address++ = 0x00; /* branch offset = 4 */
6d27d3a2
KR		 3650 *buffer_address++ = 0x04;
3651 *buffer_address++ = 0x60; /* put in bra pc+6 */
3652 *buffer_address++ = 0x06;
3653 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3654 *buffer_address++ = 0xf9;
3655
fecd2382
RP		 3656 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3657 subseg_change(SEG_TEXT,0);
6d27d3a2 3658 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
a39116f1
RP		 3659 fragP->fr_offset,0,
3660 NO_RELOC);
fecd2382
RP		 3661 fragP->fr_fix += 4;
3662 ext=0;
a39116f1 3663 break;
f8701a3f
SC		 3664 case TAB(FBRANCH,SHORT):
3665 know((fragP->fr_opcode[1]&0x40)==0);
a39116f1
RP		 3666 ext=2;
3667 break;
f8701a3f
SC		 3668 case TAB(FBRANCH,LONG):
3669 fragP->fr_opcode[1]|=0x40; /* Turn on LONG bit */
a39116f1
RP		 3670 ext=4;
3671 break;
f8701a3f
SC		 3672 case TAB(PCREL,SHORT):
3673 ext=2;
a39116f1 3674 break;
f8701a3f
SC		 3675 case TAB(PCREL,LONG):
3676 /* The thing to do here is force it to ABSOLUTE LONG, since
3677 PCREL is really trying to shorten an ABSOLUTE address anyway */
3678 /* JF FOO This code has not been tested */
3679 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3680 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3681 if((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3682 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3683 fragP->fr_opcode[0],fragP->fr_address);
3684 fragP->fr_opcode[1]&= ~0x3F;
3685 fragP->fr_opcode[1]|=0x39; /* Mode 7.1 */
3686 fragP->fr_fix+=4;
3687 /* md_number_to_chars(buffer_address,
3688 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3689 4); */
3690 ext=0;
3691 break;
f8701a3f
SC		 3692 case TAB(PCLEA,SHORT):
3693 subseg_change(SEG_TEXT,0);
a39116f1
RP		 3694 fix_new(fragP,(int)(fragP->fr_fix),2,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset,1,
3695 NO_RELOC);
3696 fragP->fr_opcode[1] &= ~0x3F;
3697 fragP->fr_opcode[1] |= 0x3A;
3698 ext=2;
3699 break;
f8701a3f
SC		 3700 case TAB(PCLEA,LONG):
3701 subseg_change(SEG_TEXT,0);
3702 fix_new(fragP,(int)(fragP->fr_fix)+2,4,fragP->fr_symbol,(symbolS *)0,fragP->fr_offset+2,1,
3703 NO_RELOC);
3704 *buffer_address++ = 0x01;
3705 *buffer_address++ = 0x70;
3706 fragP->fr_fix+=2;
3707 /* buffer_address+=2; */
3708 ext=4;
a39116f1 3709 break;
6d27d3a2 3710
f8701a3f 3711} /* switch on subtype */
6d27d3a2 3712
f8701a3f
SC		 3713 if (ext) {
3714 md_number_to_chars(buffer_address, (long) disp, (int) ext);
3715 fragP->fr_fix += ext;
3716 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3717 } /* if extending */
6d27d3a2 3718
f8701a3f
SC		 3719 return;
3720} /* md_convert_frag() */
3721
3722/* Force truly undefined symbols to their maximum size, and generally set up
3723 the frag list to be relaxed
3724 */
3725int md_estimate_size_before_relax(fragP, segment)
3726register fragS *fragP;
3727segT segment;
3728{
3729 int old_fix;
3730 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
6d27d3a2 3731
f8701a3f 3732 old_fix = fragP->fr_fix;
6d27d3a2 3733
f8701a3f
SC		 3734 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3735 switch (fragP->fr_subtype) {
6d27d3a2 3736
3ad9ec6a 3737 case TAB(ABRANCH,SZ_UNDEF): {
f8701a3f
SC		 3738 if((fragP->fr_symbol != NULL) /* Not absolute */
3739 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3740 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),BYTE);
3741 break;
3742 } else if((fragP->fr_symbol == 0) || (cpu_of_arch(current_architecture) < m68020)) {
3743 /* On 68000, or for absolute value, switch to abs long */
3744 /* FIXME, we should check abs val, pick short or long */
3745 if(fragP->fr_opcode[0]==0x61) {
3746 fragP->fr_opcode[0]= 0x4E;
3747 fragP->fr_opcode[1]= 0xB9; /* JBSR with ABSL LONG offset */
3748 subseg_change(SEG_TEXT, 0);
6d27d3a2 3749 fix_new(fragP, fragP->fr_fix, 4,
f8701a3f
SC		 3750 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3751 fragP->fr_fix+=4;
3752 frag_wane(fragP);
3753 } else if(fragP->fr_opcode[0]==0x60) {
3754 fragP->fr_opcode[0]= 0x4E;
3755 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */
3756 subseg_change(SEG_TEXT, 0);
6d27d3a2 3757 fix_new(fragP, fragP->fr_fix, 4,
f8701a3f
SC		 3758 fragP->fr_symbol, 0, fragP->fr_offset, 0, NO_RELOC);
3759 fragP->fr_fix+=4;
3760 frag_wane(fragP);
3761 } else {
3762 as_warn("Long branch offset to extern symbol not supported.");
3763 }
3764 } else { /* Symbol is still undefined. Make it simple */
3765 fix_new(fragP, (int)(fragP->fr_fix), 4, fragP->fr_symbol,
3766 (symbolS *)0, fragP->fr_offset+4, 1, NO_RELOC);
3767 fragP->fr_fix+=4;
3768 fragP->fr_opcode[1]=0xff;
3769 frag_wane(fragP);
3770 break;
3771 }
6d27d3a2 3772
f8701a3f 3773 break;
3ad9ec6a 3774 } /* case TAB(ABRANCH,SZ_UNDEF) */
6d27d3a2 3775
f8701a3f
SC		 3776 case TAB(FBRANCH,SZ_UNDEF): {
3777 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3778 fragP->fr_subtype = TAB(FBRANCH,SHORT);
3779 fragP->fr_var += 2;
3780 } else {
3781 fragP->fr_subtype = TAB(FBRANCH,LONG);
3782 fragP->fr_var += 4;
3783 }
3784 break;
3785 } /* TAB(FBRANCH,SZ_UNDEF) */
6d27d3a2 3786
f8701a3f
SC		 3787 case TAB(PCREL,SZ_UNDEF): {
3788 if(S_GET_SEGMENT(fragP->fr_symbol) == segment || flagseen['l']) {
3789 fragP->fr_subtype = TAB(PCREL,SHORT);
3790 fragP->fr_var += 2;
3791 } else {
3792 fragP->fr_subtype = TAB(PCREL,LONG);
3793 fragP->fr_var += 4;
3794 }
3795 break;
3796 } /* TAB(PCREL,SZ_UNDEF) */
6d27d3a2 3797
f8701a3f
SC		 3798 case TAB(BCC68000,SZ_UNDEF): {
3799 if((fragP->fr_symbol != NULL)
3800 && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3801 fragP->fr_subtype=TAB(BCC68000,BYTE);
3802 break;
3803 }
3804 /* only Bcc 68000 instructions can come here */
3805 /* change bcc into b!cc/jmp absl long */
3806 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3807 if(flagseen['l']) {
3808 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3809 /* JF: these were fr_opcode[2,3] */
6d27d3a2 3810 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
f8701a3f
SC		 3811 buffer_address[1] = 0xf8;
3812 fragP->fr_fix += 2; /* account for jmp instruction */
3813 subseg_change(SEG_TEXT,0);
6d27d3a2 3814 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
f8701a3f
SC		 3815 fragP->fr_offset, 0, NO_RELOC);
3816 fragP->fr_fix += 2;
3817 } else {
3818 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3819 /* JF: these were fr_opcode[2,3] */
6d27d3a2 3820 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
a1765cf0 3821 buffer_address[1] = 0xf9;
f8701a3f
SC		 3822 fragP->fr_fix += 2; /* account for jmp instruction */
3823 subseg_change(SEG_TEXT,0);
6d27d3a2 3824 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
f8701a3f
SC		 3825 fragP->fr_offset, 0, NO_RELOC);
3826 fragP->fr_fix += 4;
3827 }
3828 frag_wane(fragP);
3829 break;
3830 } /* case TAB(BCC68000,SZ_UNDEF) */
6d27d3a2 3831
f8701a3f
SC		 3832 case TAB(DBCC,SZ_UNDEF): {
3833 if (fragP->fr_symbol != NULL && S_GET_SEGMENT(fragP->fr_symbol) == segment) {
3834 fragP->fr_subtype=TAB(DBCC,SHORT);
3835 fragP->fr_var+=2;
3836 break;
3837 }
3838 /* only DBcc 68000 instructions can come here */
3839 /* change dbcc into dbcc/jmp absl long */
3840 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3841 buffer_address[0] = 0x00; /* branch offset = 4 */
6d27d3a2 3842 buffer_address[1] = 0x04;
f8701a3f 3843 buffer_address[2] = 0x60; /* put in bra pc + ... */
6d27d3a2 3844
f8701a3f
SC		 3845 if(flagseen['l']) {
3846 /* JF: these were fr_opcode[5-7] */
3847 buffer_address[3] = 0x04; /* plus 4 */
3848 buffer_address[4] = 0x4e;/* Put in Jump Word */
3849 buffer_address[5] = 0xf8;
3850 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3851 subseg_change(SEG_TEXT,0);
6d27d3a2 3852 fix_new(fragP, fragP->fr_fix, 2, fragP->fr_symbol, 0,
a933d598
SC		 3853
3854
f8701a3f
SC		 3855 fragP->fr_offset, 0, NO_RELOC);
3856 fragP->fr_fix += 2;
3857 } else {
3858 /* JF: these were fr_opcode[5-7] */
3859 buffer_address[3] = 0x06; /* Plus 6 */
6d27d3a2
KR		 3860 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3861 buffer_address[5] = 0xf9;
f8701a3f
SC		 3862 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3863 subseg_change(SEG_TEXT,0);
6d27d3a2 3864 fix_new(fragP, fragP->fr_fix, 4, fragP->fr_symbol, 0,
f8701a3f
SC		 3865 fragP->fr_offset, 0, NO_RELOC);
3866 fragP->fr_fix += 4;
3867 }
6d27d3a2 3868
f8701a3f
SC		 3869 frag_wane(fragP);
3870 break;
3871 } /* case TAB(DBCC,SZ_UNDEF) */
6d27d3a2 3872
f8701a3f
SC		 3873 case TAB(PCLEA,SZ_UNDEF): {
3874 if ((S_GET_SEGMENT(fragP->fr_symbol))==segment || flagseen['l']) {
3875 fragP->fr_subtype=TAB(PCLEA,SHORT);
3876 fragP->fr_var+=2;
3877 } else {
3878 fragP->fr_subtype=TAB(PCLEA,LONG);
3879 fragP->fr_var+=6;
3880 }
3881 break;
3882 } /* TAB(PCLEA,SZ_UNDEF) */
6d27d3a2 3883
f8701a3f
SC		 3884 default:
3885 break;
6d27d3a2 3886
f8701a3f 3887 } /* switch on subtype looking for SZ_UNDEF's. */
6d27d3a2 3888
f8701a3f
SC		 3889 /* now that SZ_UNDEF are taken care of, check others */
3890 switch (fragP->fr_subtype) {
3891 case TAB(BCC68000,BYTE):
3ad9ec6a 3892 case TAB(ABRANCH,BYTE):
a39116f1
RP		 3893 /* We can't do a short jump to the next instruction,
3894 so we force word mode. */
3895 if (fragP->fr_symbol && S_GET_VALUE(fragP->fr_symbol)==0 &&
3896 fragP->fr_symbol->sy_frag==fragP->fr_next) {
f8701a3f
SC		 3897 fragP->fr_subtype=TAB(TABTYPE(fragP->fr_subtype),SHORT);
3898 fragP->fr_var+=2;
fecd2382 3899 }
a39116f1 3900 break;
f8701a3f 3901 default:
a39116f1 3902 break;
f8701a3f
SC		 3903}
3904 return fragP->fr_var + fragP->fr_fix - old_fix;
fecd2382
RP		 3905}
3906
3907#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
6d27d3a2 3908/* the bit-field entries in the relocation_info struct plays hell
fecd2382
RP		 3909 with the byte-order problems of cross-assembly. So as a hack,
3910 I added this mach. dependent ri twiddler. Ugly, but it gets
3911 you there. -KWK */
3912/* on m68k: first 4 bytes are normal unsigned long, next three bytes
a39116f1
RP		 3913 are symbolnum, most sig. byte first. Last byte is broken up with
3914 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3915 nibble as nuthin. (on Sun 3 at least) */
fecd2382
RP		 3916/* Translate the internal relocation information into target-specific
3917 format. */
a79c6033 3918#ifdef comment
fecd2382 3919void
a39116f1
RP		 3920 md_ri_to_chars(the_bytes, ri)
3921char *the_bytes;
3922struct reloc_info_generic *ri;
fecd2382 3923{
f8701a3f
SC		 3924 /* this is easy */
3925 md_number_to_chars(the_bytes, ri->r_address, 4);
3926 /* now the fun stuff */
3927 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3928 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3929 the_bytes[6] = ri->r_symbolnum & 0x0ff;
6d27d3a2
KR		 3930 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3931 ((ri->r_extern << 4) & 0x10));
fecd2382 3932}
a79c6033
RP		 3933#endif /* comment */
3934
3935void tc_aout_fix_to_chars(where, fixP, segment_address_in_file)
f8701a3f
SC		 3936char *where;
3937fixS *fixP;
3938relax_addressT segment_address_in_file;
a79c6033 3939{
f8701a3f
SC		 3940 /*
3941 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3942 * Out: GNU LD relocation length code: 0, 1, or 2.
3943 */
6d27d3a2 3944
f8701a3f
SC		 3945 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
3946 long r_symbolnum;
6d27d3a2 3947
f8701a3f 3948 know(fixP->fx_addsy != NULL);
6d27d3a2 3949
f8701a3f
SC		 3950 md_number_to_chars(where,
3951 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3952 4);
6d27d3a2 3953
f8701a3f
SC		 3954 r_symbolnum = (S_IS_DEFINED(fixP->fx_addsy)
3955 ? S_GET_TYPE(fixP->fx_addsy)
3956 : fixP->fx_addsy->sy_number);
6d27d3a2 3957
f8701a3f
SC		 3958 where[4] = (r_symbolnum >> 16) & 0x0ff;
3959 where[5] = (r_symbolnum >> 8) & 0x0ff;
3960 where[6] = r_symbolnum & 0x0ff;
6d27d3a2 3961 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
f8701a3f 3962 (((!S_IS_DEFINED(fixP->fx_addsy)) << 4) & 0x10));
6d27d3a2 3963
f8701a3f 3964 return;
a79c6033
RP		 3965} /* tc_aout_fix_to_chars() */
3966
fecd2382
RP		 3967#endif /* OBJ_AOUT or OBJ_BOUT */
3968
3969#ifndef WORKING_DOT_WORD
3970const int md_short_jump_size = 4;
3971const int md_long_jump_size = 6;
3972
3973void
a39116f1 3974 md_create_short_jump(ptr,from_addr,to_addr,frag,to_symbol)
fecd2382
RP		 3975char *ptr;
3976long from_addr,
a39116f1 3977 to_addr;
fecd2382
RP		 3978fragS *frag;
3979symbolS *to_symbol;
3980{
f8701a3f 3981 long offset;
6d27d3a2 3982
f8701a3f 3983 offset = to_addr - (from_addr+2);
6d27d3a2 3984
f8701a3f
SC		 3985 md_number_to_chars(ptr ,(long)0x6000,2);
3986 md_number_to_chars(ptr+2,(long)offset,2);
fecd2382
RP		 3987}
3988
3989void
a39116f1 3990 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
fecd2382
RP		 3991char *ptr;
3992long from_addr,
a39116f1 3993 to_addr;
fecd2382
RP		 3994fragS *frag;
3995symbolS *to_symbol;
3996{
f8701a3f 3997 long offset;
6d27d3a2 3998
f8701a3f
SC		 3999 if (cpu_of_arch(current_architecture) < m68020) {
4000 offset=to_addr-S_GET_VALUE(to_symbol);
4001 md_number_to_chars(ptr ,(long)0x4EF9,2);
4002 md_number_to_chars(ptr+2,(long)offset,4);
4003 fix_new(frag,(ptr+2)-frag->fr_literal,4,to_symbol,(symbolS *)0,(long)0,0,
4004 NO_RELOC);
4005 } else {
4006 offset=to_addr - (from_addr+2);
4007 md_number_to_chars(ptr ,(long)0x60ff,2);
4008 md_number_to_chars(ptr+2,(long)offset,4);
4009 }
fecd2382
RP		 4010}
4011
4012#endif
4013/* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
6d27d3a2 4014
a39116f1
RP		 4015 0: Everything is OK
4016 10: Absolute 1:8 only
4017 20: Absolute 0:7 only
4018 30: absolute 0:15 only
4019 40: Absolute 0:31 only
4020 50: absolute 0:127 only
4021 55: absolute -64:63 only
4022 60: absolute -128:127 only
4023 70: absolute 0:4095 only
4024 80: No bignums
6d27d3a2 4025
a39116f1 4026 */
fecd2382
RP		 4027
4028static int get_num(exp,ok)
f8701a3f
SC		 4029struct m68k_exp *exp;
4030int ok;
fecd2382
RP		 4031{
4032#ifdef TEST2
f8701a3f 4033 long l = 0;
6d27d3a2 4034
f8701a3f
SC		 4035 if(!exp->e_beg)
4036 return 0;
4037 if(*exp->e_beg=='0') {
4038 if(exp->e_beg[1]=='x')
4039 sscanf(exp->e_beg+2,"%x",&l);
4040 else
4041 sscanf(exp->e_beg+1,"%O",&l);
4042 return l;
4043 }
4044 return atol(exp->e_beg);
fecd2382 4045#else
f8701a3f
SC		 4046 char *save_in;
4047 char c_save;
6d27d3a2 4048
f8701a3f
SC		 4049 if(!exp) {
4050 /* Can't do anything */
4051 return 0;
4052 }
4053 if(!exp->e_beg || !exp->e_end) {
4054 seg(exp)=SEG_ABSOLUTE;
4055 adds(exp)=0;
4056 subs(exp)=0;
4057 offs(exp)= (ok==10) ? 1 : 0;
4058 as_warn("Null expression defaults to %ld",offs(exp));
4059 return 0;
fecd2382 4060 }
6d27d3a2 4061
f8701a3f 4062 exp->e_siz=0;
3ad9ec6a
ILT		 4063 if(/* ok!=80 && */ (exp->e_end[-1]==':' || exp->e_end[-1]=='.')
4064 && (exp->e_end-exp->e_beg)>=2) {
f8701a3f
SC		 4065 switch(exp->e_end[0]) {
4066 case 's':
4067 case 'S':
4068 case 'b':
4069 case 'B':
4070 exp->e_siz=1;
3ad9ec6a 4071 exp->e_end-=2;
f8701a3f
SC		 4072 break;
4073 case 'w':
4074 case 'W':
4075 exp->e_siz=2;
3ad9ec6a 4076 exp->e_end-=2;
f8701a3f
SC		 4077 break;
4078 case 'l':
4079 case 'L':
4080 exp->e_siz=3;
3ad9ec6a 4081 exp->e_end-=2;
f8701a3f
SC		 4082 break;
4083 default:
3ad9ec6a
ILT		 4084 if (exp->e_end[-1] == ':')
4085 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]);
4086 break;
f8701a3f 4087 }
fecd2382 4088 }
f8701a3f
SC		 4089 c_save=exp->e_end[1];
4090 exp->e_end[1]='\0';
4091 save_in=input_line_pointer;
4092 input_line_pointer=exp->e_beg;
4093 switch(expression(&(exp->e_exp))) {
4094 case SEG_PASS1:
4095 seg(exp)=SEG_ABSOLUTE;
4096 adds(exp)=0;
4097 subs(exp)=0;
4098 offs(exp)= (ok==10) ? 1 : 0;
4099 as_warn("Unknown expression: '%s' defaulting to %d",exp->e_beg,offs(exp));
4100 break;
6d27d3a2 4101
f8701a3f
SC		 4102 case SEG_ABSENT:
4103 /* Do the same thing the VAX asm does */
4104 seg(exp)=SEG_ABSOLUTE;
4105 adds(exp)=0;
4106 subs(exp)=0;
fecd2382 4107 offs(exp)=0;
f8701a3f
SC		 4108 if(ok==10) {
4109 as_warn("expression out of range: defaulting to 1");
4110 offs(exp)=1;
4111 }
4112 break;
4113 case SEG_ABSOLUTE:
4114 switch(ok) {
4115 case 10:
4116 if(offs(exp)<1 || offs(exp)>8) {
4117 as_warn("expression out of range: defaulting to 1");
4118 offs(exp)=1;
4119 }
4120 break;
4121 case 20:
4122 if(offs(exp)<0 || offs(exp)>7)
4123 goto outrange;
4124 break;
4125 case 30:
4126 if(offs(exp)<0 || offs(exp)>15)
4127 goto outrange;
4128 break;
4129 case 40:
4130 if(offs(exp)<0 || offs(exp)>32)
4131 goto outrange;
4132 break;
4133 case 50:
4134 if(offs(exp)<0 || offs(exp)>127)
4135 goto outrange;
4136 break;
4137 case 55:
4138 if(offs(exp)<-64 || offs(exp)>63)
4139 goto outrange;
4140 break;
4141 case 60:
4142 if(offs(exp)<-128 || offs(exp)>127)
4143 goto outrange;
4144 break;
4145 case 70:
4146 if(offs(exp)<0 || offs(exp)>4095) {
4147 outrange:
4148 as_warn("expression out of range: defaulting to 0");
4149 offs(exp)=0;
4150 }
4151 break;
4152 default:
4153 break;
4154 }
4155 break;
f8701a3f 4156 case SEG_BIG:
e53ab768
KR		 4157 if (offs (exp) < 0 /* flonum */
4158 && (ok == 80 /* no bignums */
4159 || (ok > 10 /* small-int ranges including 0 ok */
4160 /* If we have a flonum zero, a zero integer should
4161 do as well (e.g., in moveq). */
4162 && generic_floating_point_number.exponent == 0
4163 && generic_floating_point_number.low[0] == 0)))
4164 {
4165 /* HACK! Turn it into a long */
4166 LITTLENUM_TYPE words[6];
4167
4168 gen_to_words(words,2,8L);/* These numbers are magic! */
4169 seg(exp)=SEG_ABSOLUTE;
4170 adds(exp)=0;
4171 subs(exp)=0;
4172 offs(exp)=words[1]|(words[0]<<16);
4173 }
4174 else if(ok!=0) {
f8701a3f
SC		 4175 seg(exp)=SEG_ABSOLUTE;
4176 adds(exp)=0;
4177 subs(exp)=0;
4178 offs(exp)= (ok==10) ? 1 : 0;
4179 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4180 }
4181 break;
fecd2382 4182 default:
587c4264
ILT		 4183 case SEG_TEXT:
4184 case SEG_DATA:
4185 case SEG_BSS:
4186 case SEG_UNKNOWN:
4187 case SEG_DIFFERENCE:
4188 if(ok>=10 && ok<=70) {
4189 seg(exp)=SEG_ABSOLUTE;
4190 adds(exp)=0;
4191 subs(exp)=0;
4192 offs(exp)= (ok==10) ? 1 : 0;
4193 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp->e_beg,offs(exp));
4194 }
4195 break;
4196
4197
a39116f1 4198 }
f8701a3f
SC		 4199 if(input_line_pointer!=exp->e_end+1)
4200 as_bad("Ignoring junk after expression");
4201 exp->e_end[1]=c_save;
4202 input_line_pointer=save_in;
4203 if(exp->e_siz) {
4204 switch(exp->e_siz) {
4205 case 1:
4206 if(!isbyte(offs(exp)))
4207 as_warn("expression doesn't fit in BYTE");
4208 break;
4209 case 2:
4210 if(!isword(offs(exp)))
4211 as_warn("expression doesn't fit in WORD");
4212 break;
4213 }
a39116f1 4214 }
f8701a3f 4215 return offs(exp);
fecd2382
RP		 4216#endif
4217} /* get_num() */
4218
4219/* These are the back-ends for the various machine dependent pseudo-ops. */
f6e504fe 4220void demand_empty_rest_of_line(); /* Hate those extra verbose names */
fecd2382
RP		 4221
4222static void s_data1() {
f8701a3f
SC		 4223 subseg_new(SEG_DATA,1);
4224 demand_empty_rest_of_line();
fecd2382
RP		 4225} /* s_data1() */
4226
4227static void s_data2() {
f8701a3f
SC		 4228 subseg_new(SEG_DATA,2);
4229 demand_empty_rest_of_line();
fecd2382
RP		 4230} /* s_data2() */
4231
6d27d3a2 4232static void s_bss()
a1765cf0 4233{
6d27d3a2 4234 /* We don't support putting frags in the BSS segment, we fake it
a1765cf0
SC		 4235 by marking in_bss, then looking at s_skip for clues */
4236
4237 subseg_new(SEG_BSS, 0);
f8701a3f 4238 demand_empty_rest_of_line();
fecd2382
RP		 4239} /* s_bss() */
4240
4241static void s_even() {
f8701a3f
SC		 4242 register int temp;
4243 register long temp_fill;
6d27d3a2 4244
f8701a3f
SC		 4245 temp = 1; /* JF should be 2? */
4246 temp_fill = get_absolute_expression ();
4247 if ( ! need_pass_2 ) /* Never make frag if expect extra pass. */
4248 frag_align (temp, (int)temp_fill);
4249 demand_empty_rest_of_line();
fecd2382
RP		 4250} /* s_even() */
4251
4252static void s_proc() {
f8701a3f 4253 demand_empty_rest_of_line();
fecd2382
RP		 4254} /* s_proc() */
4255
4256/* s_space is defined in read.c .skip is simply an alias to it. */
4257
7c15cbe8
RP		 4258/*
4259 * md_parse_option
4260 * Invocation line includes a switch not recognized by the base assembler.
4261 * See if it's a processor-specific option. These are:
4262 *
4263 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4264 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4265 * Select the architecture. Instructions or features not
4266 * supported by the selected architecture cause fatal
4267 * errors. More than one may be specified. The default is
4268 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4269 * for -m68000, and -m68882 is a synonym for -m68881.
df3768fb
KR		 4270 * -[A]m[c]no-68851, -[A]m[c]no-68881
4271 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4272 * so don't use or document it, but that's the way the parsing
4273 * works).
7c15cbe8 4274 *
a39116f1
RP		 4275 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4276 * (e.g. m68020) also requests that float instructions be included. This
4277 * is the default setup, mostly to avoid hassling users. A better
4278 * rearrangement of this structure would be to add an option to DENY
4279 * floating point opcodes, for people who want to really know there's none
4280 * of that funny floaty stuff going on. FIXME-later.
7c15cbe8 4281 */
a39116f1 4282#ifndef MAYBE_FLOAT_TOO
df3768fb 4283#define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
a39116f1 4284#endif
7c15cbe8
RP		 4285
4286int md_parse_option(argP,cntP,vecP)
f8701a3f
SC		 4287char **argP;
4288int *cntP;
4289char ***vecP;
fecd2382 4290{
f8701a3f
SC		 4291 switch(**argP) {
4292 case 'l': /* -l means keep external to 2 bit offset
4293 rather than 16 bit one */
4294 break;
6d27d3a2 4295
f8701a3f
SC		 4296 case 'S': /* -S means that jbsr's always turn into jsr's. */
4297 break;
6d27d3a2 4298
f8701a3f
SC		 4299 case 'A':
4300 (*argP)++;
4301 /* intentional fall-through */
4302 case 'm':
4303 (*argP)++;
6d27d3a2 4304
f8701a3f
SC		 4305 if (**argP=='c') {
4306 (*argP)++;
4307 } /* allow an optional "c" */
6d27d3a2 4308
f8701a3f
SC		 4309 if (!strcmp(*argP, "68000")
4310 || !strcmp(*argP, "68008")) {
4311 current_architecture |= m68000;
4312 } else if (!strcmp(*argP, "68010")) {
fecd2382 4313#ifdef TE_SUN
f8701a3f 4314 omagic= 1<<16|OMAGIC;
fecd2382 4315#endif
f8701a3f 4316 current_architecture |= m68010;
6d27d3a2
KR		 4317
4318 } else if (!strcmp(*argP, "68020")) {
f8701a3f 4319 current_architecture |= m68020 | MAYBE_FLOAT_TOO;
6d27d3a2
KR		 4320
4321 } else if (!strcmp(*argP, "68030")) {
f8701a3f 4322 current_architecture |= m68030 | MAYBE_FLOAT_TOO;
6d27d3a2
KR		 4323
4324 } else if (!strcmp(*argP, "68040")) {
f8701a3f 4325 current_architecture |= m68040 | MAYBE_FLOAT_TOO;
6d27d3a2 4326
7c15cbe8 4327#ifndef NO_68881
f8701a3f
SC		 4328 } else if (!strcmp(*argP, "68881")) {
4329 current_architecture |= m68881;
6d27d3a2 4330
f8701a3f
SC		 4331 } else if (!strcmp(*argP, "68882")) {
4332 current_architecture |= m68882;
7c15cbe8 4333#endif /* NO_68881 */
df3768fb
KR		 4334 /* Even if we aren't configured to support the processor,
4335 it should still be possible to assert that the user
4336 doesn't have it... */
4337 } else if (!strcmp (*argP, "no-68881")
4338 || !strcmp (*argP, "no-68882")) {
4339 no_68881 = 1;
7c15cbe8 4340#ifndef NO_68851
6d27d3a2 4341 } else if (!strcmp(*argP,"68851")) {
f8701a3f 4342 current_architecture |= m68851;
7c15cbe8 4343#endif /* NO_68851 */
df3768fb
KR		 4344 } else if (!strcmp (*argP, "no-68851")) {
4345 no_68851 = 1;
4346 } else if (!strcmp (*argP, "pu32")) { /* "-mcpu32" */
4347 current_architecture |= cpu32;
f8701a3f
SC		 4348 } else {
4349 as_warn("Unknown architecture, \"%s\". option ignored", *argP);
4350 } /* switch on architecture */
6d27d3a2 4351
f8701a3f 4352 while(**argP) (*argP)++;
6d27d3a2 4353
f8701a3f 4354 break;
6d27d3a2 4355
f8701a3f
SC		 4356 case 'p':
4357 if (!strcmp(*argP,"pic")) {
4358 (*argP) += 3;
4359 break; /* -pic, Position Independent Code */
4360 } else {
4361 return(0);
4362 } /* pic or not */
6d27d3a2 4363
f8701a3f
SC		 4364 default:
4365 return 0;
4366 }
4367 return 1;
fecd2382
RP		 4368}
4369
4370
4371#ifdef TEST2
4372
4373/* TEST2: Test md_assemble() */
4374/* Warning, this routine probably doesn't work anymore */
4375
4376main()
4377{
f8701a3f
SC		 4378 struct m68k_it the_ins;
4379 char buf[120];
4380 char *cp;
4381 int n;
6d27d3a2 4382
f8701a3f
SC		 4383 m68k_ip_begin();
4384 for(;;) {
4385 if(!gets(buf) || !*buf)
4386 break;
4387 if(buf[0]=='|' || buf[1]=='.')
4388 continue;
4389 for(cp=buf;*cp;cp++)
4390 if(*cp=='\t')
4391 *cp=' ';
4392 if(is_label(buf))
4393 continue;
4394 memset(&the_ins, '\0', sizeof(the_ins));
4395 m68k_ip(&the_ins,buf);
4396 if(the_ins.error) {
4397 printf("Error %s in %s\n",the_ins.error,buf);
4398 } else {
4399 printf("Opcode(%d.%s): ",the_ins.numo,the_ins.args);
4400 for(n=0;n<the_ins.numo;n++)
4401 printf(" 0x%x",the_ins.opcode[n]&0xffff);
4402 printf(" ");
4403 print_the_insn(&the_ins.opcode[0],stdout);
4404 (void)putchar('\n');
4405 }
4406 for(n=0;n<strlen(the_ins.args)/2;n++) {
4407 if(the_ins.operands[n].error) {
4408 printf("op%d Error %s in %s\n",n,the_ins.operands[n].error,buf);
4409 continue;
4410 }
4411 printf("mode %d, reg %d, ",the_ins.operands[n].mode,the_ins.operands[n].reg);
4412 if(the_ins.operands[n].b_const)
4413 printf("Constant: '%.*s', ",1+the_ins.operands[n].e_const-the_ins.operands[n].b_const,the_ins.operands[n].b_const);
4414 printf("ireg %d, isiz %d, imul %d, ",the_ins.operands[n].ireg,the_ins.operands[n].isiz,the_ins.operands[n].imul);
4415 if(the_ins.operands[n].b_iadd)
4416 printf("Iadd: '%.*s',",1+the_ins.operands[n].e_iadd-the_ins.operands[n].b_iadd,the_ins.operands[n].b_iadd);
4417 (void)putchar('\n');
4418 }
a39116f1 4419 }
f8701a3f
SC		 4420 m68k_ip_end();
4421 return 0;
fecd2382
RP		 4422}
4423
4424is_label(str)
f8701a3f 4425char *str;
fecd2382 4426{
f8701a3f
SC		 4427 while(*str==' ')
4428 str++;
4429 while(*str && *str!=' ')
4430 str++;
4431 if(str[-1]==':' || str[1]=='=')
4432 return 1;
4433 return 0;
fecd2382
RP		 4434}
4435
4436#endif
4437
4438/* Possible states for relaxation:
6d27d3a2 4439
a39116f1
RP		 4440 0 0 branch offset byte (bra, etc)
4441 0 1 word
4442 0 2 long
6d27d3a2 4443
a39116f1
RP		 4444 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4445 1 1 word
4446 1 2 long
6d27d3a2 4447
a39116f1
RP		 4448 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4449 2 1 word-long
4450 2 2 long-word
4451 2 3 long-long
6d27d3a2 4452
a39116f1 4453 */
fecd2382
RP		 4454
4455
4456
4457#ifdef DONTDEF
4458abort()
4459{
f8701a3f
SC		 4460 printf("ABORT!\n");
4461 exit(12);
fecd2382
RP		 4462}
4463
4464print_frags()
4465{
f8701a3f
SC		 4466 fragS *fragP;
4467 extern fragS *text_frag_root;
6d27d3a2 4468
f8701a3f
SC		 4469 for(fragP=text_frag_root;fragP;fragP=fragP->fr_next) {
4470 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
4471 fragP->fr_address,fragP->fr_next,fragP->fr_fix,fragP->fr_var,fragP->fr_symbol,fragP->fr_offset);
4472 printf("opcode 0x%x type %d subtype %d\n\n",fragP->fr_opcode,fragP->fr_type,fragP->fr_subtype);
4473 }
4474 fflush(stdout);
4475 return 0;
fecd2382
RP		 4476}
4477#endif
4478
4479#ifdef DONTDEF
4480/*VARARGS1*/
4481panic(format,args)
f8701a3f 4482char *format;
fecd2382 4483{
f8701a3f
SC		 4484 fputs("Internal error:",stderr);
4485 _doprnt(format,&args,stderr);
4486 (void)putc('\n',stderr);
4487 as_where();
4488 abort();
fecd2382
RP		 4489}
4490#endif
4491
4492/* We have no need to default values of symbols. */
4493
4494/* ARGSUSED */
4495symbolS *
a39116f1
RP		 4496 md_undefined_symbol (name)
4497char *name;
fecd2382 4498{
f8701a3f 4499 return 0;
fecd2382
RP		 4500}
4501
6d27d3a2 4502/* Parse an operand that is machine-specific.
fecd2382
RP		 4503 We just return without modifying the expression if we have nothing
4504 to do. */
4505
4506/* ARGSUSED */
4507void
a39116f1
RP		 4508 md_operand (expressionP)
4509expressionS *expressionP;
fecd2382
RP		 4510{
4511}
4512
4513/* Round up a section size to the appropriate boundary. */
4514long
a39116f1
RP		 4515 md_section_align (segment, size)
4516segT segment;
4517long size;
fecd2382 4518{
f8701a3f 4519 return size; /* Byte alignment is fine */
fecd2382
RP		 4520}
4521
4522/* Exactly what point is a PC-relative offset relative TO?
4523 On the 68k, they're relative to the address of the offset, plus
4524 its size. (??? Is this right? FIXME-SOON!) */
4525long
a39116f1
RP		 4526 md_pcrel_from (fixP)
4527fixS *fixP;
fecd2382 4528{
f8701a3f 4529 return(fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address);
fecd2382
RP		 4530}
4531
3ad9ec6a
ILT		 4532void
4533tc_coff_symbol_emit_hook ()
4534{
4535}
4536
4537int
4538tc_coff_sizemachdep(frag)
4539fragS *frag;
4540{
4541 switch (frag->fr_subtype & 0x3)
4542 {
4543 case BYTE: return 1;
4544 case SHORT: return 2;
4545 case LONG: return 4;
4546 default: abort();
4547 }
4548
4549}
fecd2382
RP		 4550/*
4551 * Local Variables:
4552 * comment-column: 0
4553 * fill-column: 131
4554 * End:
4555 */
4556
4557/* end of tc-m68k.c */
3ad9ec6a 4558
GDB Binutils - Deliverables
This page took 0.267967 seconds and 4 git commands to generate.