Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-m68k.c -- Assemble for the m68k family |
f7e42eb4 | 2 | Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
5a49b8ac AM |
3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
252b5132 RH |
25 | #include "obstack.h" |
26 | #include "subsegs.h" | |
f27a3839 | 27 | #include "dwarf2dbg.h" |
c04898f8 | 28 | #include "dw2gencfi.h" |
252b5132 RH |
29 | |
30 | #include "opcode/m68k.h" | |
31 | #include "m68k-parse.h" | |
32 | ||
0d96863f CM |
33 | #if defined (OBJ_ELF) |
34 | #include "elf/m68k.h" | |
35 | #endif | |
36 | ||
31302357 AS |
37 | #ifdef M68KCOFF |
38 | #include "obj-coff.h" | |
39 | #endif | |
40 | ||
252b5132 RH |
41 | /* This string holds the chars that always start a comment. If the |
42 | pre-processor is disabled, these aren't very useful. The macro | |
43 | tc_comment_chars points to this. We use this, rather than the | |
44 | usual comment_chars, so that the --bitwise-or option will work. */ | |
45 | #if defined (TE_SVR4) || defined (TE_DELTA) | |
46 | const char *m68k_comment_chars = "|#"; | |
47 | #else | |
48 | const char *m68k_comment_chars = "|"; | |
49 | #endif | |
50 | ||
51 | /* This array holds the chars that only start a comment at the beginning of | |
52 | a line. If the line seems to have the form '# 123 filename' | |
53 | .line and .file directives will appear in the pre-processed output */ | |
54 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
55 | first line of the input file. This is because the compiler outputs | |
92774660 KH |
56 | #NO_APP at the beginning of its output. */ |
57 | /* Also note that comments like this one will always work. */ | |
252b5132 RH |
58 | const char line_comment_chars[] = "#*"; |
59 | ||
63a0b638 | 60 | const char line_separator_chars[] = ";"; |
252b5132 | 61 | |
36759679 | 62 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
5a38dc70 | 63 | const char EXP_CHARS[] = "eE"; |
252b5132 RH |
64 | |
65 | /* Chars that mean this number is a floating point constant, as | |
66 | in "0f12.456" or "0d1.2345e12". */ | |
67 | ||
5a38dc70 | 68 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
252b5132 RH |
69 | |
70 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
71 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
72 | but nothing is ideal around here. */ | |
73 | ||
252b5132 RH |
74 | /* Are we trying to generate PIC code? If so, absolute references |
75 | ought to be made into linkage table references or pc-relative | |
92774660 | 76 | references. Not implemented. For ELF there are other means |
252b5132 RH |
77 | to denote pic relocations. */ |
78 | int flag_want_pic; | |
79 | ||
36759679 NC |
80 | static int flag_short_refs; /* -l option. */ |
81 | static int flag_long_jumps; /* -S option. */ | |
28e7409f | 82 | static int flag_keep_pcrel; /* --pcrel option. */ |
252b5132 RH |
83 | |
84 | #ifdef REGISTER_PREFIX_OPTIONAL | |
85 | int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; | |
86 | #else | |
87 | int flag_reg_prefix_optional; | |
88 | #endif | |
89 | ||
90 | /* Whether --register-prefix-optional was used on the command line. */ | |
91 | static int reg_prefix_optional_seen; | |
92 | ||
93 | /* The floating point coprocessor to use by default. */ | |
94 | static enum m68k_register m68k_float_copnum = COP1; | |
95 | ||
96 | /* If this is non-zero, then references to number(%pc) will be taken | |
97 | to refer to number, rather than to %pc + number. */ | |
98 | static int m68k_abspcadd; | |
99 | ||
100 | /* If this is non-zero, then the quick forms of the move, add, and sub | |
101 | instructions are used when possible. */ | |
102 | static int m68k_quick = 1; | |
103 | ||
104 | /* If this is non-zero, then if the size is not specified for a base | |
105 | or outer displacement, the assembler assumes that the size should | |
106 | be 32 bits. */ | |
107 | static int m68k_rel32 = 1; | |
108 | ||
109 | /* This is non-zero if m68k_rel32 was set from the command line. */ | |
110 | static int m68k_rel32_from_cmdline; | |
111 | ||
112 | /* The default width to use for an index register when using a base | |
113 | displacement. */ | |
114 | static enum m68k_size m68k_index_width_default = SIZE_LONG; | |
115 | ||
116 | /* We want to warn if any text labels are misaligned. In order to get | |
117 | the right line number, we need to record the line number for each | |
118 | label. */ | |
252b5132 RH |
119 | struct label_line |
120 | { | |
121 | struct label_line *next; | |
122 | symbolS *label; | |
123 | char *file; | |
124 | unsigned int line; | |
125 | int text; | |
126 | }; | |
127 | ||
128 | /* The list of labels. */ | |
129 | ||
130 | static struct label_line *labels; | |
131 | ||
132 | /* The current label. */ | |
133 | ||
134 | static struct label_line *current_label; | |
135 | ||
60fed2d3 NC |
136 | /* Pointer to list holding the opcodes sorted by name. */ |
137 | static struct m68k_opcode const ** m68k_sorted_opcodes; | |
138 | ||
36759679 NC |
139 | /* Its an arbitrary name: This means I don't approve of it. |
140 | See flames below. */ | |
252b5132 RH |
141 | static struct obstack robyn; |
142 | ||
252b5132 RH |
143 | struct m68k_incant |
144 | { | |
145 | const char *m_operands; | |
146 | unsigned long m_opcode; | |
147 | short m_opnum; | |
148 | short m_codenum; | |
149 | int m_arch; | |
150 | struct m68k_incant *m_next; | |
151 | }; | |
152 | ||
153 | #define getone(x) ((((x)->m_opcode)>>16)&0xffff) | |
154 | #define gettwo(x) (((x)->m_opcode)&0xffff) | |
155 | ||
2da12c60 NS |
156 | static const enum m68k_register m68000_ctrl[] = { 0 }; |
157 | static const enum m68k_register m68010_ctrl[] = { | |
252b5132 RH |
158 | SFC, DFC, USP, VBR, |
159 | 0 | |
160 | }; | |
2da12c60 | 161 | static const enum m68k_register m68020_ctrl[] = { |
252b5132 RH |
162 | SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, |
163 | 0 | |
164 | }; | |
2da12c60 | 165 | static const enum m68k_register m68040_ctrl[] = { |
252b5132 RH |
166 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, |
167 | USP, VBR, MSP, ISP, MMUSR, URP, SRP, | |
168 | 0 | |
169 | }; | |
2da12c60 | 170 | static const enum m68k_register m68060_ctrl[] = { |
252b5132 RH |
171 | SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, |
172 | USP, VBR, URP, SRP, PCR, | |
173 | 0 | |
174 | }; | |
2da12c60 | 175 | static const enum m68k_register mcf_ctrl[] = { |
3e602632 | 176 | CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, |
78336706 NS |
177 | RAMBAR0, RAMBAR1, RAMBAR, MBAR, |
178 | 0 | |
179 | }; | |
f75192f2 KH |
180 | static const enum m68k_register mcf51qe_ctrl[] = { |
181 | VBR, | |
182 | 0 | |
183 | }; | |
78336706 NS |
184 | static const enum m68k_register mcf5206_ctrl[] = { |
185 | CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, | |
252b5132 RH |
186 | 0 |
187 | }; | |
2da12c60 | 188 | static const enum m68k_register mcf5208_ctrl[] = { |
78336706 | 189 | CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1, |
266abb8f NS |
190 | 0 |
191 | }; | |
96e0bbcc | 192 | static const enum m68k_register mcf5210a_ctrl[] = { |
78336706 | 193 | VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR, |
96e0bbcc NS |
194 | 0 |
195 | }; | |
2da12c60 | 196 | static const enum m68k_register mcf5213_ctrl[] = { |
78336706 | 197 | VBR, RAMBAR, RAMBAR1, FLASHBAR, |
266abb8f NS |
198 | 0 |
199 | }; | |
2da12c60 | 200 | static const enum m68k_register mcf5216_ctrl[] = { |
78336706 | 201 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, |
266abb8f NS |
202 | 0 |
203 | }; | |
d5be9593 NS |
204 | static const enum m68k_register mcf52223_ctrl[] = { |
205 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, | |
206 | 0 | |
207 | }; | |
96e0bbcc | 208 | static const enum m68k_register mcf52235_ctrl[] = { |
def8fc92 | 209 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, |
96e0bbcc NS |
210 | 0 |
211 | }; | |
212 | static const enum m68k_register mcf5225_ctrl[] = { | |
78336706 | 213 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1, |
96e0bbcc NS |
214 | 0 |
215 | }; | |
2da12c60 | 216 | static const enum m68k_register mcf5235_ctrl[] = { |
78336706 | 217 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
e80e0390 NC |
218 | 0 |
219 | }; | |
2da12c60 | 220 | static const enum m68k_register mcf5249_ctrl[] = { |
78336706 | 221 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, |
3e602632 NC |
222 | 0 |
223 | }; | |
2da12c60 NS |
224 | static const enum m68k_register mcf5250_ctrl[] = { |
225 | VBR, | |
226 | 0 | |
227 | }; | |
d5be9593 | 228 | static const enum m68k_register mcf5253_ctrl[] = { |
def8fc92 | 229 | VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, |
d5be9593 NS |
230 | 0 |
231 | }; | |
2da12c60 | 232 | static const enum m68k_register mcf5271_ctrl[] = { |
78336706 | 233 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
234 | 0 |
235 | }; | |
236 | static const enum m68k_register mcf5272_ctrl[] = { | |
78336706 | 237 | VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR, |
2da12c60 NS |
238 | 0 |
239 | }; | |
240 | static const enum m68k_register mcf5275_ctrl[] = { | |
78336706 | 241 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
242 | 0 |
243 | }; | |
244 | static const enum m68k_register mcf5282_ctrl[] = { | |
78336706 NS |
245 | VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, |
246 | 0 | |
247 | }; | |
248 | static const enum m68k_register mcf5307_ctrl[] = { | |
249 | CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, | |
2da12c60 NS |
250 | 0 |
251 | }; | |
252 | static const enum m68k_register mcf5329_ctrl[] = { | |
78336706 | 253 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
254 | 0 |
255 | }; | |
256 | static const enum m68k_register mcf5373_ctrl[] = { | |
78336706 | 257 | VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, |
2da12c60 NS |
258 | 0 |
259 | }; | |
260 | static const enum m68k_register mcfv4e_ctrl[] = { | |
a8e24a56 NS |
261 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, |
262 | VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1, | |
263 | MBAR, SECMBAR, | |
264 | MPCR /* Multiprocessor Control register */, | |
265 | EDRAMBAR /* Embedded DRAM Base Address Register */, | |
266 | /* Permutation control registers. */ | |
3e602632 NC |
267 | PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, |
268 | PCR3U0, PCR3L0, PCR3U1, PCR3L1, | |
a8e24a56 NS |
269 | /* Legacy names */ |
270 | TC /* ASID */, BUSCR /* MMUBAR */, | |
271 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
272 | MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */, | |
78336706 | 273 | ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, |
a8e24a56 NS |
274 | 0 |
275 | }; | |
def8fc92 KH |
276 | static const enum m68k_register mcf5407_ctrl[] = { |
277 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, | |
278 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
279 | /* Legacy names */ | |
280 | TC /* ASID */, | |
281 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
282 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, | |
283 | 0 | |
284 | }; | |
9a2e615a NS |
285 | static const enum m68k_register mcf54455_ctrl[] = { |
286 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
287 | VBR, PC, RAMBAR1, MBAR, | |
288 | /* Legacy names */ | |
289 | TC /* ASID */, BUSCR /* MMUBAR */, | |
290 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
291 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, | |
292 | 0 | |
293 | }; | |
a8e24a56 NS |
294 | static const enum m68k_register mcf5475_ctrl[] = { |
295 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
296 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
297 | /* Legacy names */ | |
298 | TC /* ASID */, BUSCR /* MMUBAR */, | |
299 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
78336706 | 300 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, |
a8e24a56 NS |
301 | 0 |
302 | }; | |
303 | static const enum m68k_register mcf5485_ctrl[] = { | |
304 | CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, | |
305 | VBR, PC, RAMBAR0, RAMBAR1, MBAR, | |
306 | /* Legacy names */ | |
307 | TC /* ASID */, BUSCR /* MMUBAR */, | |
308 | ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, | |
78336706 | 309 | MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, |
3e602632 NC |
310 | 0 |
311 | }; | |
f7ec513b | 312 | static const enum m68k_register fido_ctrl[] = { |
d0fa1372 | 313 | SFC, DFC, USP, VBR, CAC, MBO, |
f7ec513b KH |
314 | 0 |
315 | }; | |
2da12c60 | 316 | #define cpu32_ctrl m68010_ctrl |
252b5132 RH |
317 | |
318 | static const enum m68k_register *control_regs; | |
319 | ||
36759679 | 320 | /* Internal form of a 68020 instruction. */ |
252b5132 RH |
321 | struct m68k_it |
322 | { | |
323 | const char *error; | |
36759679 | 324 | const char *args; /* List of opcode info. */ |
252b5132 RH |
325 | int numargs; |
326 | ||
36759679 | 327 | int numo; /* Number of shorts in opcode. */ |
252b5132 RH |
328 | short opcode[11]; |
329 | ||
330 | struct m68k_op operands[6]; | |
331 | ||
36759679 | 332 | int nexp; /* Number of exprs in use. */ |
252b5132 RH |
333 | struct m68k_exp exprs[4]; |
334 | ||
36759679 | 335 | int nfrag; /* Number of frags we have to produce. */ |
252b5132 RH |
336 | struct |
337 | { | |
36759679 | 338 | int fragoff; /* Where in the current opcode the frag ends. */ |
252b5132 RH |
339 | symbolS *fadd; |
340 | offsetT foff; | |
341 | int fragty; | |
342 | } | |
343 | fragb[4]; | |
344 | ||
36759679 | 345 | int nrel; /* Num of reloc strucs in use. */ |
252b5132 RH |
346 | struct |
347 | { | |
348 | int n; | |
349 | expressionS exp; | |
350 | char wid; | |
351 | char pcrel; | |
352 | /* In a pc relative address the difference between the address | |
353 | of the offset and the address that the offset is relative | |
354 | to. This depends on the addressing mode. Basically this | |
355 | is the value to put in the offset field to address the | |
356 | first byte of the offset, without regarding the special | |
357 | significance of some values (in the branch instruction, for | |
358 | example). */ | |
359 | int pcrel_fix; | |
360 | #ifdef OBJ_ELF | |
361 | /* Whether this expression needs special pic relocation, and if | |
362 | so, which. */ | |
363 | enum pic_relocation pic_reloc; | |
364 | #endif | |
365 | } | |
36759679 | 366 | reloc[5]; /* Five is enough??? */ |
252b5132 RH |
367 | }; |
368 | ||
9840d27e | 369 | #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a)) |
252b5132 RH |
370 | #define float_of_arch(x) ((x) & mfloat) |
371 | #define mmu_of_arch(x) ((x) & mmmu) | |
6b6e92f4 NC |
372 | #define arch_coldfire_p(x) ((x) & mcfisa_a) |
373 | #define arch_coldfire_fpu(x) ((x) & cfloat) | |
252b5132 | 374 | |
36759679 | 375 | /* Macros for determining if cpu supports a specific addressing mode. */ |
9a2e615a NS |
376 | #define HAVE_LONG_DISP(x) \ |
377 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
378 | #define HAVE_LONG_CALL(x) \ | |
379 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
380 | #define HAVE_LONG_COND(x) \ | |
381 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) | |
382 | #define HAVE_LONG_BRANCH(x) \ | |
383 | ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) | |
cac27205 | 384 | #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x)) |
252b5132 | 385 | |
36759679 | 386 | static struct m68k_it the_ins; /* The instruction being assembled. */ |
252b5132 RH |
387 | |
388 | #define op(ex) ((ex)->exp.X_op) | |
389 | #define adds(ex) ((ex)->exp.X_add_symbol) | |
390 | #define subs(ex) ((ex)->exp.X_op_symbol) | |
391 | #define offs(ex) ((ex)->exp.X_add_number) | |
392 | ||
36759679 | 393 | /* Macros for adding things to the m68k_it struct. */ |
31302357 | 394 | #define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) |
252b5132 | 395 | |
36759679 NC |
396 | /* Like addword, but goes BEFORE general operands. */ |
397 | ||
252b5132 | 398 | static void |
31302357 | 399 | insop (int w, const struct m68k_incant *opcode) |
252b5132 RH |
400 | { |
401 | int z; | |
07726851 | 402 | for (z = the_ins.numo; z > opcode->m_codenum; --z) |
8a104df9 KH |
403 | the_ins.opcode[z] = the_ins.opcode[z - 1]; |
404 | for (z = 0; z < the_ins.nrel; z++) | |
405 | the_ins.reloc[z].n += 2; | |
252b5132 RH |
406 | for (z = 0; z < the_ins.nfrag; z++) |
407 | the_ins.fragb[z].fragoff++; | |
8a104df9 | 408 | the_ins.opcode[opcode->m_codenum] = w; |
252b5132 RH |
409 | the_ins.numo++; |
410 | } | |
411 | ||
412 | /* The numo+1 kludge is so we can hit the low order byte of the prev word. | |
413 | Blecch. */ | |
414 | static void | |
31302357 | 415 | add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) |
252b5132 | 416 | { |
31302357 AS |
417 | the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' |
418 | ? the_ins.numo * 2 - 1 | |
419 | : (width == 'b' | |
420 | ? the_ins.numo * 2 + 1 | |
421 | : the_ins.numo * 2)); | |
252b5132 RH |
422 | the_ins.reloc[the_ins.nrel].exp = exp->exp; |
423 | the_ins.reloc[the_ins.nrel].wid = width; | |
424 | the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; | |
425 | #ifdef OBJ_ELF | |
426 | the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; | |
427 | #endif | |
428 | the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; | |
429 | } | |
430 | ||
431 | /* Cause an extra frag to be generated here, inserting up to 10 bytes | |
432 | (that value is chosen in the frag_var call in md_assemble). TYPE | |
433 | is the subtype of the frag to be generated; its primary type is | |
434 | rs_machine_dependent. | |
435 | ||
436 | The TYPE parameter is also used by md_convert_frag_1 and | |
437 | md_estimate_size_before_relax. The appropriate type of fixup will | |
438 | be emitted by md_convert_frag_1. | |
439 | ||
440 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ | |
441 | static void | |
31302357 | 442 | add_frag (symbolS *add, offsetT off, int type) |
252b5132 | 443 | { |
8a104df9 KH |
444 | the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; |
445 | the_ins.fragb[the_ins.nfrag].fadd = add; | |
446 | the_ins.fragb[the_ins.nfrag].foff = off; | |
447 | the_ins.fragb[the_ins.nfrag++].fragty = type; | |
252b5132 RH |
448 | } |
449 | ||
450 | #define isvar(ex) \ | |
451 | (op (ex) != O_constant && op (ex) != O_big) | |
452 | ||
31302357 AS |
453 | static char *crack_operand (char *str, struct m68k_op *opP); |
454 | static int get_num (struct m68k_exp *exp, int ok); | |
455 | static int reverse_16_bits (int in); | |
456 | static int reverse_8_bits (int in); | |
457 | static void install_gen_operand (int mode, int val); | |
458 | static void install_operand (int mode, int val); | |
459 | static void s_bss (int); | |
460 | static void s_data1 (int); | |
461 | static void s_data2 (int); | |
462 | static void s_even (int); | |
463 | static void s_proc (int); | |
464 | static void s_chip (int); | |
465 | static void s_fopt (int); | |
466 | static void s_opt (int); | |
467 | static void s_reg (int); | |
468 | static void s_restore (int); | |
469 | static void s_save (int); | |
470 | static void s_mri_if (int); | |
471 | static void s_mri_else (int); | |
472 | static void s_mri_endi (int); | |
473 | static void s_mri_break (int); | |
474 | static void s_mri_next (int); | |
475 | static void s_mri_for (int); | |
476 | static void s_mri_endf (int); | |
477 | static void s_mri_repeat (int); | |
478 | static void s_mri_until (int); | |
479 | static void s_mri_while (int); | |
480 | static void s_mri_endw (int); | |
266abb8f NS |
481 | static void s_m68k_cpu (int); |
482 | static void s_m68k_arch (int); | |
483 | ||
484 | struct m68k_cpu | |
485 | { | |
486 | unsigned long arch; /* Architecture features. */ | |
2da12c60 | 487 | const enum m68k_register *control_regs; /* Control regs on chip */ |
266abb8f | 488 | const char *name; /* Name */ |
0b2e31dc NS |
489 | int alias; /* Alias for a cannonical name. If 1, then |
490 | succeeds canonical name, if -1 then | |
491 | succeeds canonical name, if <-1 ||>1 this is a | |
492 | deprecated name, and the next/previous name | |
493 | should be used. */ | |
266abb8f | 494 | }; |
252b5132 | 495 | |
266abb8f NS |
496 | /* We hold flags for features explicitly enabled and explicitly |
497 | disabled. */ | |
252b5132 | 498 | static int current_architecture; |
266abb8f | 499 | static int not_current_architecture; |
266abb8f NS |
500 | static const struct m68k_cpu *selected_arch; |
501 | static const struct m68k_cpu *selected_cpu; | |
502 | static int initialized; | |
252b5132 | 503 | |
266abb8f NS |
504 | /* Architecture models. */ |
505 | static const struct m68k_cpu m68k_archs[] = | |
506 | { | |
2da12c60 NS |
507 | {m68000, m68000_ctrl, "68000", 0}, |
508 | {m68010, m68010_ctrl, "68010", 0}, | |
509 | {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, | |
510 | {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, | |
511 | {m68040, m68040_ctrl, "68040", 0}, | |
512 | {m68060, m68060_ctrl, "68060", 0}, | |
513 | {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, | |
3bdcfdf4 | 514 | {fido_a, fido_ctrl, "fidoa", 0}, |
2da12c60 NS |
515 | {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, |
516 | {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, | |
517 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, | |
9a2e615a | 518 | {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, |
2da12c60 NS |
519 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, |
520 | {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, | |
266abb8f NS |
521 | {0,0,NULL, 0} |
522 | }; | |
252b5132 | 523 | |
0b2e31dc NS |
524 | /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0 |
525 | for either. */ | |
266abb8f NS |
526 | static const struct m68k_cpu m68k_extensions[] = |
527 | { | |
2da12c60 NS |
528 | {m68851, NULL, "68851", -1}, |
529 | {m68881, NULL, "68881", -1}, | |
530 | {m68881, NULL, "68882", -1}, | |
0b2e31dc | 531 | |
2da12c60 | 532 | {cfloat|m68881, NULL, "float", 0}, |
266abb8f | 533 | |
2da12c60 NS |
534 | {mcfhwdiv, NULL, "div", 1}, |
535 | {mcfusp, NULL, "usp", 1}, | |
536 | {mcfmac, NULL, "mac", 1}, | |
537 | {mcfemac, NULL, "emac", 1}, | |
266abb8f | 538 | |
2da12c60 | 539 | {0,NULL,NULL, 0} |
266abb8f NS |
540 | }; |
541 | ||
542 | /* Processor list */ | |
543 | static const struct m68k_cpu m68k_cpus[] = | |
544 | { | |
2da12c60 NS |
545 | {m68000, m68000_ctrl, "68000", 0}, |
546 | {m68000, m68000_ctrl, "68ec000", 1}, | |
547 | {m68000, m68000_ctrl, "68hc000", 1}, | |
548 | {m68000, m68000_ctrl, "68hc001", 1}, | |
549 | {m68000, m68000_ctrl, "68008", 1}, | |
550 | {m68000, m68000_ctrl, "68302", 1}, | |
551 | {m68000, m68000_ctrl, "68306", 1}, | |
552 | {m68000, m68000_ctrl, "68307", 1}, | |
553 | {m68000, m68000_ctrl, "68322", 1}, | |
554 | {m68000, m68000_ctrl, "68356", 1}, | |
555 | {m68010, m68010_ctrl, "68010", 0}, | |
556 | {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, | |
557 | {m68020|m68881|m68851, m68020_ctrl, "68k", 1}, | |
558 | {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1}, | |
559 | {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, | |
560 | {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1}, | |
561 | {m68040, m68040_ctrl, "68040", 0}, | |
562 | {m68040, m68040_ctrl, "68ec040", 1}, | |
563 | {m68060, m68060_ctrl, "68060", 0}, | |
564 | {m68060, m68060_ctrl, "68ec060", 1}, | |
565 | ||
566 | {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, | |
567 | {cpu32|m68881, cpu32_ctrl, "68330", 1}, | |
568 | {cpu32|m68881, cpu32_ctrl, "68331", 1}, | |
569 | {cpu32|m68881, cpu32_ctrl, "68332", 1}, | |
570 | {cpu32|m68881, cpu32_ctrl, "68333", 1}, | |
571 | {cpu32|m68881, cpu32_ctrl, "68334", 1}, | |
572 | {cpu32|m68881, cpu32_ctrl, "68336", 1}, | |
573 | {cpu32|m68881, cpu32_ctrl, "68340", 1}, | |
574 | {cpu32|m68881, cpu32_ctrl, "68341", 1}, | |
575 | {cpu32|m68881, cpu32_ctrl, "68349", 1}, | |
576 | {cpu32|m68881, cpu32_ctrl, "68360", 1}, | |
f75192f2 KH |
577 | |
578 | {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0}, | |
2da12c60 NS |
579 | |
580 | {mcfisa_a, mcf_ctrl, "5200", 0}, | |
581 | {mcfisa_a, mcf_ctrl, "5202", 1}, | |
582 | {mcfisa_a, mcf_ctrl, "5204", 1}, | |
78336706 | 583 | {mcfisa_a, mcf5206_ctrl, "5206", 1}, |
2da12c60 | 584 | |
78336706 | 585 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0}, |
2da12c60 NS |
586 | |
587 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1}, | |
588 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0}, | |
589 | ||
96e0bbcc NS |
590 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0}, |
591 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1}, | |
592 | ||
2da12c60 NS |
593 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1}, |
594 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1}, | |
595 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0}, | |
596 | ||
597 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1}, | |
598 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0}, | |
599 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2}, | |
600 | ||
d5be9593 NS |
601 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1}, |
602 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0}, | |
603 | ||
96e0bbcc NS |
604 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1}, |
605 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1}, | |
606 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1}, | |
607 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0}, | |
608 | ||
609 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1}, | |
610 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0}, | |
611 | ||
2da12c60 NS |
612 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1}, |
613 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1}, | |
614 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1}, | |
615 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1}, | |
616 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0}, | |
617 | ||
618 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0}, | |
619 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0}, | |
d5be9593 | 620 | {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0}, |
2da12c60 NS |
621 | |
622 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1}, | |
623 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0}, | |
624 | ||
625 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0}, | |
626 | ||
627 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1}, | |
628 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0}, | |
629 | ||
630 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1}, | |
631 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1}, | |
632 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1}, | |
633 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0}, | |
634 | ||
78336706 | 635 | {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0}, |
2da12c60 NS |
636 | |
637 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1}, | |
638 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1}, | |
639 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1}, | |
640 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0}, | |
641 | ||
642 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1}, | |
643 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1}, | |
644 | {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, | |
645 | ||
def8fc92 | 646 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0}, |
9a2e615a NS |
647 | |
648 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, | |
649 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, | |
650 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, | |
651 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, | |
652 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, | |
653 | {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, | |
2da12c60 | 654 | |
a8e24a56 NS |
655 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, |
656 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, | |
657 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1}, | |
658 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1}, | |
659 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1}, | |
660 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1}, | |
661 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0}, | |
2da12c60 | 662 | |
a8e24a56 NS |
663 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1}, |
664 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1}, | |
665 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1}, | |
666 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1}, | |
667 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1}, | |
668 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1}, | |
669 | {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0}, | |
2da12c60 | 670 | |
b3768379 | 671 | {fido_a, fido_ctrl, "fidoa", 0}, |
3bdcfdf4 | 672 | {fido_a, fido_ctrl, "fido", 1}, |
9840d27e | 673 | |
2da12c60 | 674 | {0,NULL,NULL, 0} |
dc84e067 | 675 | }; |
252b5132 | 676 | |
266abb8f NS |
677 | static const struct m68k_cpu *m68k_lookup_cpu |
678 | (const char *, const struct m68k_cpu *, int, int *); | |
679 | static int m68k_set_arch (const char *, int, int); | |
680 | static int m68k_set_cpu (const char *, int, int); | |
681 | static int m68k_set_extension (const char *, int, int); | |
682 | static void m68k_init_arch (void); | |
252b5132 | 683 | |
151337e8 NC |
684 | /* This is the assembler relaxation table for m68k. m68k is a rich CISC |
685 | architecture and we have a lot of relaxation modes. */ | |
252b5132 | 686 | |
151337e8 NC |
687 | /* Macros used in the relaxation code. */ |
688 | #define TAB(x,y) (((x) << 2) + (y)) | |
689 | #define TABTYPE(x) ((x) >> 2) | |
690 | ||
691 | /* Relaxation states. */ | |
692 | #define BYTE 0 | |
693 | #define SHORT 1 | |
694 | #define LONG 2 | |
695 | #define SZ_UNDEF 3 | |
696 | ||
697 | /* Here are all the relaxation modes we support. First we can relax ordinary | |
698 | branches. On 68020 and higher and on CPU32 all branch instructions take | |
699 | three forms, so on these CPUs all branches always remain as such. When we | |
700 | have to expand to the LONG form on a 68000, though, we substitute an | |
701 | absolute jump instead. This is a direct replacement for unconditional | |
702 | branches and a branch over a jump for conditional branches. However, if the | |
703 | user requires PIC and disables this with --pcrel, we can only relax between | |
704 | BYTE and SHORT forms, punting if that isn't enough. This gives us four | |
705 | different relaxation modes for branches: */ | |
706 | ||
36759679 NC |
707 | #define BRANCHBWL 0 /* Branch byte, word, or long. */ |
708 | #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ | |
709 | #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ | |
710 | #define BRANCHBW 3 /* Branch byte or word. */ | |
151337e8 NC |
711 | |
712 | /* We also relax coprocessor branches and DBcc's. All CPUs that support | |
713 | coprocessor branches support them in word and long forms, so we have only | |
714 | one relaxation mode for them. DBcc's are word only on all CPUs. We can | |
715 | relax them to the LONG form with a branch-around sequence. This sequence | |
716 | can use a long branch (if available) or an absolute jump (if acceptable). | |
717 | This gives us two relaxation modes. If long branches are not available and | |
718 | absolute jumps are not acceptable, we don't relax DBcc's. */ | |
719 | ||
36759679 NC |
720 | #define FBRANCH 4 /* Coprocessor branch. */ |
721 | #define DBCCLBR 5 /* DBcc relaxable with a long branch. */ | |
722 | #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ | |
151337e8 NC |
723 | |
724 | /* That's all for instruction relaxation. However, we also relax PC-relative | |
725 | operands. Specifically, we have three operand relaxation modes. On the | |
726 | 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and | |
727 | on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the | |
728 | two. Also PC+displacement+index operands in their simple form (with a non- | |
729 | suppressed index without memory indirection) are supported on all CPUs, but | |
730 | on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher | |
731 | and on CPU32 we relax it to SHORT and LONG forms as well using the extended | |
732 | form of the PC+displacement+index operand. Finally, some absolute operands | |
733 | can be relaxed down to 16-bit PC-relative. */ | |
734 | ||
36759679 NC |
735 | #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ |
736 | #define PCINDEX 8 /* PC + displacement + index. */ | |
737 | #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ | |
252b5132 | 738 | |
cac27205 NC |
739 | /* This relaxation is required for branches where there is no long |
740 | branch and we are in pcrel mode. We generate a bne/beq pair. */ | |
741 | #define BRANCHBWPL 10 /* Branch byte, word or pair of longs | |
742 | */ | |
743 | ||
252b5132 | 744 | /* Note that calls to frag_var need to specify the maximum expansion |
cac27205 NC |
745 | needed; this is currently 12 bytes for bne/beq pair. */ |
746 | #define FRAG_VAR_SIZE 12 | |
252b5132 RH |
747 | |
748 | /* The fields are: | |
749 | How far Forward this mode will reach: | |
750 | How far Backward this mode will reach: | |
751 | How many bytes this mode will add to the size of the frag | |
752 | Which mode to go to if the offset won't fit in this one | |
d7861ad2 AM |
753 | |
754 | Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ | |
252b5132 RH |
755 | relax_typeS md_relax_table[] = |
756 | { | |
ac62c346 AM |
757 | { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, |
758 | { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, | |
759 | { 0, 0, 4, 0 }, | |
760 | { 1, 1, 0, 0 }, | |
761 | ||
762 | { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, | |
763 | { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, | |
764 | { 0, 0, 4, 0 }, | |
765 | { 1, 1, 0, 0 }, | |
766 | ||
767 | { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, | |
768 | { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, | |
769 | { 0, 0, 6, 0 }, | |
770 | { 1, 1, 0, 0 }, | |
771 | ||
772 | { 127, -128, 0, TAB (BRANCHBW, SHORT) }, | |
773 | { 0, 0, 2, 0 }, | |
774 | { 1, 1, 0, 0 }, | |
775 | { 1, 1, 0, 0 }, | |
776 | ||
36759679 | 777 | { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ |
ac62c346 AM |
778 | { 32767, -32768, 2, TAB (FBRANCH, LONG) }, |
779 | { 0, 0, 4, 0 }, | |
780 | { 1, 1, 0, 0 }, | |
781 | ||
36759679 | 782 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ |
ac62c346 AM |
783 | { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, |
784 | { 0, 0, 10, 0 }, | |
785 | { 1, 1, 0, 0 }, | |
786 | ||
36759679 | 787 | { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ |
ac62c346 AM |
788 | { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, |
789 | { 0, 0, 10, 0 }, | |
790 | { 1, 1, 0, 0 }, | |
791 | ||
36759679 | 792 | { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ |
ac62c346 AM |
793 | { 32767, -32768, 2, TAB (PCREL1632, LONG) }, |
794 | { 0, 0, 6, 0 }, | |
795 | { 1, 1, 0, 0 }, | |
796 | ||
797 | { 125, -130, 0, TAB (PCINDEX, SHORT) }, | |
798 | { 32765, -32770, 2, TAB (PCINDEX, LONG) }, | |
799 | { 0, 0, 4, 0 }, | |
800 | { 1, 1, 0, 0 }, | |
801 | ||
36759679 | 802 | { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ |
ac62c346 AM |
803 | { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, |
804 | { 0, 0, 4, 0 }, | |
805 | { 1, 1, 0, 0 }, | |
cac27205 NC |
806 | |
807 | { 127, -128, 0, TAB (BRANCHBWPL, SHORT) }, | |
808 | { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) }, | |
809 | { 0, 0, 10, 0 }, | |
810 | { 1, 1, 0, 0 }, | |
252b5132 RH |
811 | }; |
812 | ||
813 | /* These are the machine dependent pseudo-ops. These are included so | |
814 | the assembler can work on the output from the SUN C compiler, which | |
36759679 | 815 | generates these. */ |
252b5132 RH |
816 | |
817 | /* This table describes all the machine specific pseudo-ops the assembler | |
818 | has to support. The fields are: | |
819 | pseudo-op name without dot | |
820 | function to call to execute this pseudo-op | |
36759679 | 821 | Integer arg to pass to the function. */ |
252b5132 RH |
822 | const pseudo_typeS md_pseudo_table[] = |
823 | { | |
824 | {"data1", s_data1, 0}, | |
825 | {"data2", s_data2, 0}, | |
826 | {"bss", s_bss, 0}, | |
827 | {"even", s_even, 0}, | |
828 | {"skip", s_space, 0}, | |
829 | {"proc", s_proc, 0}, | |
830 | #if defined (TE_SUN3) || defined (OBJ_ELF) | |
831 | {"align", s_align_bytes, 0}, | |
832 | #endif | |
833 | #ifdef OBJ_ELF | |
834 | {"swbeg", s_ignore, 0}, | |
835 | #endif | |
836 | {"extend", float_cons, 'x'}, | |
837 | {"ldouble", float_cons, 'x'}, | |
838 | ||
266abb8f NS |
839 | {"arch", s_m68k_arch, 0}, |
840 | {"cpu", s_m68k_cpu, 0}, | |
841 | ||
252b5132 RH |
842 | /* The following pseudo-ops are supported for MRI compatibility. */ |
843 | {"chip", s_chip, 0}, | |
844 | {"comline", s_space, 1}, | |
845 | {"fopt", s_fopt, 0}, | |
846 | {"mask2", s_ignore, 0}, | |
847 | {"opt", s_opt, 0}, | |
848 | {"reg", s_reg, 0}, | |
849 | {"restore", s_restore, 0}, | |
850 | {"save", s_save, 0}, | |
851 | ||
852 | {"if", s_mri_if, 0}, | |
853 | {"if.b", s_mri_if, 'b'}, | |
854 | {"if.w", s_mri_if, 'w'}, | |
855 | {"if.l", s_mri_if, 'l'}, | |
856 | {"else", s_mri_else, 0}, | |
857 | {"else.s", s_mri_else, 's'}, | |
858 | {"else.l", s_mri_else, 'l'}, | |
859 | {"endi", s_mri_endi, 0}, | |
860 | {"break", s_mri_break, 0}, | |
861 | {"break.s", s_mri_break, 's'}, | |
862 | {"break.l", s_mri_break, 'l'}, | |
863 | {"next", s_mri_next, 0}, | |
864 | {"next.s", s_mri_next, 's'}, | |
865 | {"next.l", s_mri_next, 'l'}, | |
866 | {"for", s_mri_for, 0}, | |
867 | {"for.b", s_mri_for, 'b'}, | |
868 | {"for.w", s_mri_for, 'w'}, | |
869 | {"for.l", s_mri_for, 'l'}, | |
870 | {"endf", s_mri_endf, 0}, | |
871 | {"repeat", s_mri_repeat, 0}, | |
872 | {"until", s_mri_until, 0}, | |
873 | {"until.b", s_mri_until, 'b'}, | |
874 | {"until.w", s_mri_until, 'w'}, | |
875 | {"until.l", s_mri_until, 'l'}, | |
876 | {"while", s_mri_while, 0}, | |
877 | {"while.b", s_mri_while, 'b'}, | |
878 | {"while.w", s_mri_while, 'w'}, | |
879 | {"while.l", s_mri_while, 'l'}, | |
880 | {"endw", s_mri_endw, 0}, | |
881 | ||
882 | {0, 0, 0} | |
883 | }; | |
884 | ||
252b5132 | 885 | /* The mote pseudo ops are put into the opcode table, since they |
31302357 | 886 | don't start with a . they look like opcodes to gas. */ |
252b5132 | 887 | |
5a38dc70 | 888 | const pseudo_typeS mote_pseudo_table[] = |
252b5132 RH |
889 | { |
890 | ||
891 | {"dcl", cons, 4}, | |
892 | {"dc", cons, 2}, | |
893 | {"dcw", cons, 2}, | |
894 | {"dcb", cons, 1}, | |
895 | ||
896 | {"dsl", s_space, 4}, | |
897 | {"ds", s_space, 2}, | |
898 | {"dsw", s_space, 2}, | |
899 | {"dsb", s_space, 1}, | |
900 | ||
901 | {"xdef", s_globl, 0}, | |
902 | #ifdef OBJ_ELF | |
903 | {"align", s_align_bytes, 0}, | |
904 | #else | |
905 | {"align", s_align_ptwo, 0}, | |
906 | #endif | |
907 | #ifdef M68KCOFF | |
908 | {"sect", obj_coff_section, 0}, | |
909 | {"section", obj_coff_section, 0}, | |
910 | #endif | |
911 | {0, 0, 0} | |
912 | }; | |
913 | ||
bd17c2c3 AM |
914 | /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host |
915 | gives identical results to a 32-bit host. */ | |
916 | #define TRUNC(X) ((valueT) (X) & 0xffffffff) | |
917 | #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000) | |
918 | ||
919 | #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100) | |
920 | #define isubyte(x) ((valueT) TRUNC (x) < 0x100) | |
921 | #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000) | |
922 | #define isuword(x) ((valueT) TRUNC (x) < 0x10000) | |
923 | ||
924 | #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff) | |
925 | #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff) | |
252b5132 RH |
926 | #define islong(x) (1) |
927 | ||
252b5132 RH |
928 | static char notend_table[256]; |
929 | static char alt_notend_table[256]; | |
930 | #define notend(s) \ | |
931 | (! (notend_table[(unsigned char) *s] \ | |
932 | || (*s == ':' \ | |
933 | && alt_notend_table[(unsigned char) s[1]]))) | |
934 | ||
252b5132 RH |
935 | #ifdef OBJ_ELF |
936 | ||
c801568a AM |
937 | /* Return zero if the reference to SYMBOL from within the same segment may |
938 | be relaxed. */ | |
939 | ||
940 | /* On an ELF system, we can't relax an externally visible symbol, | |
941 | because it may be overridden by a shared library. However, if | |
942 | TARGET_OS is "elf", then we presume that we are assembling for an | |
943 | embedded system, in which case we don't have to worry about shared | |
944 | libraries, and we can relax any external sym. */ | |
945 | ||
946 | #define relaxable_symbol(symbol) \ | |
6358301e | 947 | (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ |
c801568a AM |
948 | || S_IS_WEAK (symbol))) |
949 | ||
252b5132 RH |
950 | /* Compute the relocation code for a fixup of SIZE bytes, using pc |
951 | relative relocation if PCREL is non-zero. PIC says whether a special | |
952 | pic relocation was requested. */ | |
953 | ||
252b5132 | 954 | static bfd_reloc_code_real_type |
31302357 | 955 | get_reloc_code (int size, int pcrel, enum pic_relocation pic) |
252b5132 RH |
956 | { |
957 | switch (pic) | |
958 | { | |
959 | case pic_got_pcrel: | |
960 | switch (size) | |
961 | { | |
962 | case 1: | |
963 | return BFD_RELOC_8_GOT_PCREL; | |
964 | case 2: | |
965 | return BFD_RELOC_16_GOT_PCREL; | |
966 | case 4: | |
967 | return BFD_RELOC_32_GOT_PCREL; | |
968 | } | |
969 | break; | |
970 | ||
971 | case pic_got_off: | |
972 | switch (size) | |
973 | { | |
974 | case 1: | |
975 | return BFD_RELOC_8_GOTOFF; | |
976 | case 2: | |
977 | return BFD_RELOC_16_GOTOFF; | |
978 | case 4: | |
979 | return BFD_RELOC_32_GOTOFF; | |
980 | } | |
981 | break; | |
982 | ||
983 | case pic_plt_pcrel: | |
984 | switch (size) | |
985 | { | |
986 | case 1: | |
987 | return BFD_RELOC_8_PLT_PCREL; | |
988 | case 2: | |
989 | return BFD_RELOC_16_PLT_PCREL; | |
990 | case 4: | |
991 | return BFD_RELOC_32_PLT_PCREL; | |
992 | } | |
993 | break; | |
994 | ||
995 | case pic_plt_off: | |
996 | switch (size) | |
997 | { | |
998 | case 1: | |
999 | return BFD_RELOC_8_PLTOFF; | |
1000 | case 2: | |
1001 | return BFD_RELOC_16_PLTOFF; | |
1002 | case 4: | |
1003 | return BFD_RELOC_32_PLTOFF; | |
1004 | } | |
1005 | break; | |
1006 | ||
1007 | case pic_none: | |
1008 | if (pcrel) | |
1009 | { | |
1010 | switch (size) | |
1011 | { | |
1012 | case 1: | |
1013 | return BFD_RELOC_8_PCREL; | |
1014 | case 2: | |
1015 | return BFD_RELOC_16_PCREL; | |
1016 | case 4: | |
1017 | return BFD_RELOC_32_PCREL; | |
1018 | } | |
1019 | } | |
1020 | else | |
1021 | { | |
1022 | switch (size) | |
1023 | { | |
1024 | case 1: | |
1025 | return BFD_RELOC_8; | |
1026 | case 2: | |
1027 | return BFD_RELOC_16; | |
1028 | case 4: | |
1029 | return BFD_RELOC_32; | |
1030 | } | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | if (pcrel) | |
1035 | { | |
1036 | if (pic == pic_none) | |
1037 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
1038 | else | |
1039 | as_bad (_("Can not do %d byte pc-relative pic relocation"), size); | |
1040 | } | |
1041 | else | |
1042 | { | |
1043 | if (pic == pic_none) | |
1044 | as_bad (_("Can not do %d byte relocation"), size); | |
1045 | else | |
1046 | as_bad (_("Can not do %d byte pic relocation"), size); | |
1047 | } | |
1048 | ||
1049 | return BFD_RELOC_NONE; | |
1050 | } | |
1051 | ||
1052 | /* Here we decide which fixups can be adjusted to make them relative | |
1053 | to the beginning of the section instead of the symbol. Basically | |
1054 | we need to make sure that the dynamic relocations are done | |
1055 | correctly, so in some cases we force the original symbol to be | |
1056 | used. */ | |
1057 | int | |
31302357 | 1058 | tc_m68k_fix_adjustable (fixS *fixP) |
252b5132 | 1059 | { |
36759679 | 1060 | /* Adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1061 | switch (fixP->fx_r_type) |
1062 | { | |
1063 | case BFD_RELOC_8_GOT_PCREL: | |
1064 | case BFD_RELOC_16_GOT_PCREL: | |
1065 | case BFD_RELOC_32_GOT_PCREL: | |
1066 | case BFD_RELOC_8_GOTOFF: | |
1067 | case BFD_RELOC_16_GOTOFF: | |
1068 | case BFD_RELOC_32_GOTOFF: | |
1069 | case BFD_RELOC_8_PLT_PCREL: | |
1070 | case BFD_RELOC_16_PLT_PCREL: | |
1071 | case BFD_RELOC_32_PLT_PCREL: | |
1072 | case BFD_RELOC_8_PLTOFF: | |
1073 | case BFD_RELOC_16_PLTOFF: | |
1074 | case BFD_RELOC_32_PLTOFF: | |
1075 | return 0; | |
1076 | ||
1077 | case BFD_RELOC_VTABLE_INHERIT: | |
1078 | case BFD_RELOC_VTABLE_ENTRY: | |
1079 | return 0; | |
1080 | ||
1081 | default: | |
1082 | return 1; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | #else /* !OBJ_ELF */ | |
1087 | ||
1088 | #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC | |
1089 | ||
22184a77 NC |
1090 | /* PR gas/3041 Weak symbols are not relaxable |
1091 | because they must be treated as extern. */ | |
1092 | #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol))) | |
c801568a | 1093 | |
252b5132 RH |
1094 | #endif /* OBJ_ELF */ |
1095 | ||
252b5132 | 1096 | arelent * |
31302357 | 1097 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
1098 | { |
1099 | arelent *reloc; | |
1100 | bfd_reloc_code_real_type code; | |
1101 | ||
8ec6253e NC |
1102 | /* If the tcbit is set, then this was a fixup of a negative value |
1103 | that was never resolved. We do not have a reloc to handle this, | |
1104 | so just return. We assume that other code will have detected this | |
1105 | situation and produced a helpful error message, so we just tell the | |
1106 | user that the reloc cannot be produced. */ | |
252b5132 | 1107 | if (fixp->fx_tcbit) |
8ec6253e NC |
1108 | { |
1109 | if (fixp->fx_addsy) | |
b091f402 AM |
1110 | as_bad_where (fixp->fx_file, fixp->fx_line, |
1111 | _("Unable to produce reloc against symbol '%s'"), | |
1112 | S_GET_NAME (fixp->fx_addsy)); | |
8ec6253e NC |
1113 | return NULL; |
1114 | } | |
252b5132 RH |
1115 | |
1116 | if (fixp->fx_r_type != BFD_RELOC_NONE) | |
1117 | { | |
1118 | code = fixp->fx_r_type; | |
1119 | ||
1120 | /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible | |
1121 | that fixup_segment converted a non-PC relative reloc into a | |
1122 | PC relative reloc. In such a case, we need to convert the | |
1123 | reloc code. */ | |
1124 | if (fixp->fx_pcrel) | |
1125 | { | |
1126 | switch (code) | |
1127 | { | |
1128 | case BFD_RELOC_8: | |
1129 | code = BFD_RELOC_8_PCREL; | |
1130 | break; | |
1131 | case BFD_RELOC_16: | |
1132 | code = BFD_RELOC_16_PCREL; | |
1133 | break; | |
1134 | case BFD_RELOC_32: | |
1135 | code = BFD_RELOC_32_PCREL; | |
1136 | break; | |
1137 | case BFD_RELOC_8_PCREL: | |
1138 | case BFD_RELOC_16_PCREL: | |
1139 | case BFD_RELOC_32_PCREL: | |
1140 | case BFD_RELOC_8_GOT_PCREL: | |
1141 | case BFD_RELOC_16_GOT_PCREL: | |
1142 | case BFD_RELOC_32_GOT_PCREL: | |
1143 | case BFD_RELOC_8_GOTOFF: | |
1144 | case BFD_RELOC_16_GOTOFF: | |
1145 | case BFD_RELOC_32_GOTOFF: | |
1146 | case BFD_RELOC_8_PLT_PCREL: | |
1147 | case BFD_RELOC_16_PLT_PCREL: | |
1148 | case BFD_RELOC_32_PLT_PCREL: | |
1149 | case BFD_RELOC_8_PLTOFF: | |
1150 | case BFD_RELOC_16_PLTOFF: | |
1151 | case BFD_RELOC_32_PLTOFF: | |
1152 | break; | |
1153 | default: | |
1154 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1155 | _("Cannot make %s relocation PC relative"), | |
1156 | bfd_get_reloc_code_name (code)); | |
1157 | } | |
1158 | } | |
1159 | } | |
1160 | else | |
1161 | { | |
1162 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) | |
1163 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
1164 | { | |
1165 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
1166 | MAP (1, 0, BFD_RELOC_8); | |
1167 | MAP (2, 0, BFD_RELOC_16); | |
1168 | MAP (4, 0, BFD_RELOC_32); | |
1169 | MAP (1, 1, BFD_RELOC_8_PCREL); | |
1170 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
1171 | MAP (4, 1, BFD_RELOC_32_PCREL); | |
1172 | default: | |
1173 | abort (); | |
1174 | } | |
1175 | } | |
1176 | #undef F | |
1177 | #undef MAP | |
1178 | ||
1179 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
1180 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1181 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1182 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1183 | #ifndef OBJ_ELF | |
1184 | if (fixp->fx_pcrel) | |
1185 | reloc->addend = fixp->fx_addnumber; | |
22184a77 NC |
1186 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
1187 | && fixp->fx_addsy | |
1188 | && S_IS_WEAK (fixp->fx_addsy) | |
1189 | && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy))) | |
1190 | /* PR gas/3041 Adjust addend in order to force bfd_install_relocation() | |
1c3f20b4 NC |
1191 | to put the symbol offset into frags referencing a weak symbol. */ |
1192 | reloc->addend = fixp->fx_addnumber | |
1193 | - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
252b5132 RH |
1194 | else |
1195 | reloc->addend = 0; | |
1196 | #else | |
1197 | if (!fixp->fx_pcrel) | |
1198 | reloc->addend = fixp->fx_addnumber; | |
1199 | else | |
1200 | reloc->addend = (section->vma | |
8390138c AS |
1201 | /* Explicit sign extension in case char is |
1202 | unsigned. */ | |
1203 | + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80 | |
252b5132 RH |
1204 | + fixp->fx_addnumber |
1205 | + md_pcrel_from (fixp)); | |
1206 | #endif | |
1207 | ||
1208 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
1209 | assert (reloc->howto != 0); | |
1210 | ||
1211 | return reloc; | |
1212 | } | |
1213 | ||
252b5132 RH |
1214 | /* Handle of the OPCODE hash table. NULL means any use before |
1215 | m68k_ip_begin() will crash. */ | |
1216 | static struct hash_control *op_hash; | |
1217 | \f | |
1218 | /* Assemble an m68k instruction. */ | |
1219 | ||
1220 | static void | |
31302357 | 1221 | m68k_ip (char *instring) |
252b5132 RH |
1222 | { |
1223 | register char *p; | |
1224 | register struct m68k_op *opP; | |
1225 | register const struct m68k_incant *opcode; | |
1226 | register const char *s; | |
1227 | register int tmpreg = 0, baseo = 0, outro = 0, nextword; | |
1228 | char *pdot, *pdotmove; | |
1229 | enum m68k_size siz1, siz2; | |
1230 | char c; | |
1231 | int losing; | |
1232 | int opsfound; | |
03b13e59 | 1233 | struct m68k_op operands_backup[6]; |
252b5132 RH |
1234 | LITTLENUM_TYPE words[6]; |
1235 | LITTLENUM_TYPE *wordp; | |
1236 | unsigned long ok_arch = 0; | |
1237 | ||
1238 | if (*instring == ' ') | |
36759679 | 1239 | instring++; /* Skip leading whitespace. */ |
252b5132 RH |
1240 | |
1241 | /* Scan up to end of operation-code, which MUST end in end-of-string | |
92774660 | 1242 | or exactly 1 space. */ |
252b5132 RH |
1243 | pdot = 0; |
1244 | for (p = instring; *p != '\0'; p++) | |
1245 | { | |
1246 | if (*p == ' ') | |
1247 | break; | |
1248 | if (*p == '.') | |
1249 | pdot = p; | |
1250 | } | |
1251 | ||
1252 | if (p == instring) | |
1253 | { | |
1254 | the_ins.error = _("No operator"); | |
1255 | return; | |
1256 | } | |
1257 | ||
1258 | /* p now points to the end of the opcode name, probably whitespace. | |
1259 | Make sure the name is null terminated by clobbering the | |
1260 | whitespace, look it up in the hash table, then fix it back. | |
1261 | Remove a dot, first, since the opcode tables have none. */ | |
1262 | if (pdot != NULL) | |
1263 | { | |
1264 | for (pdotmove = pdot; pdotmove < p; pdotmove++) | |
1265 | *pdotmove = pdotmove[1]; | |
1266 | p--; | |
1267 | } | |
1268 | ||
1269 | c = *p; | |
1270 | *p = '\0'; | |
1271 | opcode = (const struct m68k_incant *) hash_find (op_hash, instring); | |
1272 | *p = c; | |
1273 | ||
1274 | if (pdot != NULL) | |
1275 | { | |
1276 | for (pdotmove = p; pdotmove > pdot; pdotmove--) | |
1277 | *pdotmove = pdotmove[-1]; | |
1278 | *pdot = '.'; | |
1279 | ++p; | |
1280 | } | |
1281 | ||
1282 | if (opcode == NULL) | |
1283 | { | |
1284 | the_ins.error = _("Unknown operator"); | |
1285 | return; | |
1286 | } | |
1287 | ||
36759679 | 1288 | /* Found a legitimate opcode, start matching operands. */ |
252b5132 RH |
1289 | while (*p == ' ') |
1290 | ++p; | |
1291 | ||
1292 | if (opcode->m_operands == 0) | |
1293 | { | |
1294 | char *old = input_line_pointer; | |
1295 | *old = '\n'; | |
1296 | input_line_pointer = p; | |
36759679 | 1297 | /* Ahh - it's a motorola style psuedo op. */ |
252b5132 RH |
1298 | mote_pseudo_table[opcode->m_opnum].poc_handler |
1299 | (mote_pseudo_table[opcode->m_opnum].poc_val); | |
1300 | input_line_pointer = old; | |
1301 | *old = 0; | |
1302 | ||
1303 | return; | |
1304 | } | |
1305 | ||
1306 | if (flag_mri && opcode->m_opnum == 0) | |
1307 | { | |
1308 | /* In MRI mode, random garbage is allowed after an instruction | |
1309 | which accepts no operands. */ | |
1310 | the_ins.args = opcode->m_operands; | |
1311 | the_ins.numargs = opcode->m_opnum; | |
1312 | the_ins.numo = opcode->m_codenum; | |
1313 | the_ins.opcode[0] = getone (opcode); | |
1314 | the_ins.opcode[1] = gettwo (opcode); | |
1315 | return; | |
1316 | } | |
1317 | ||
1318 | for (opP = &the_ins.operands[0]; *p; opP++) | |
1319 | { | |
1320 | p = crack_operand (p, opP); | |
1321 | ||
1322 | if (opP->error) | |
1323 | { | |
1324 | the_ins.error = opP->error; | |
1325 | return; | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | opsfound = opP - &the_ins.operands[0]; | |
1330 | ||
1331 | /* This ugly hack is to support the floating pt opcodes in their | |
1332 | standard form. Essentially, we fake a first enty of type COP#1 */ | |
1333 | if (opcode->m_operands[0] == 'I') | |
1334 | { | |
1335 | int n; | |
1336 | ||
1337 | for (n = opsfound; n > 0; --n) | |
1338 | the_ins.operands[n] = the_ins.operands[n - 1]; | |
1339 | ||
31302357 | 1340 | memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); |
252b5132 RH |
1341 | the_ins.operands[0].mode = CONTROL; |
1342 | the_ins.operands[0].reg = m68k_float_copnum; | |
1343 | opsfound++; | |
1344 | } | |
1345 | ||
36759679 | 1346 | /* We've got the operands. Find an opcode that'll accept them. */ |
252b5132 RH |
1347 | for (losing = 0;;) |
1348 | { | |
1349 | /* If we didn't get the right number of ops, or we have no | |
92774660 | 1350 | common model with this pattern then reject this pattern. */ |
252b5132 RH |
1351 | |
1352 | ok_arch |= opcode->m_arch; | |
1353 | if (opsfound != opcode->m_opnum | |
1354 | || ((opcode->m_arch & current_architecture) == 0)) | |
1355 | ++losing; | |
1356 | else | |
1357 | { | |
03b13e59 NC |
1358 | int i; |
1359 | ||
1360 | /* Make a copy of the operands of this insn so that | |
1361 | we can modify them safely, should we want to. */ | |
1362 | assert (opsfound <= (int) ARRAY_SIZE (operands_backup)); | |
1363 | for (i = 0; i < opsfound; i++) | |
1364 | operands_backup[i] = the_ins.operands[i]; | |
1365 | ||
1366 | for (s = opcode->m_operands, opP = &operands_backup[0]; | |
252b5132 RH |
1367 | *s && !losing; |
1368 | s += 2, opP++) | |
1369 | { | |
1370 | /* Warning: this switch is huge! */ | |
1371 | /* I've tried to organize the cases into this order: | |
1372 | non-alpha first, then alpha by letter. Lower-case | |
1373 | goes directly before uppercase counterpart. */ | |
1374 | /* Code with multiple case ...: gets sorted by the lowest | |
1375 | case ... it belongs to. I hope this makes sense. */ | |
1376 | switch (*s) | |
1377 | { | |
1378 | case '!': | |
1379 | switch (opP->mode) | |
1380 | { | |
1381 | case IMMED: | |
1382 | case DREG: | |
1383 | case AREG: | |
1384 | case FPREG: | |
1385 | case CONTROL: | |
1386 | case AINC: | |
1387 | case ADEC: | |
1388 | case REGLST: | |
1389 | losing++; | |
1390 | break; | |
1391 | default: | |
1392 | break; | |
1393 | } | |
1394 | break; | |
1395 | ||
1396 | case '<': | |
1397 | switch (opP->mode) | |
1398 | { | |
1399 | case DREG: | |
1400 | case AREG: | |
1401 | case FPREG: | |
1402 | case CONTROL: | |
1403 | case IMMED: | |
1404 | case ADEC: | |
1405 | case REGLST: | |
1406 | losing++; | |
1407 | break; | |
1408 | default: | |
1409 | break; | |
1410 | } | |
1411 | break; | |
1412 | ||
1413 | case '>': | |
1414 | switch (opP->mode) | |
1415 | { | |
1416 | case DREG: | |
1417 | case AREG: | |
1418 | case FPREG: | |
1419 | case CONTROL: | |
1420 | case IMMED: | |
1421 | case AINC: | |
1422 | case REGLST: | |
1423 | losing++; | |
1424 | break; | |
1425 | case ABSL: | |
1426 | break; | |
1427 | default: | |
1428 | if (opP->reg == PC | |
1429 | || opP->reg == ZPC) | |
1430 | losing++; | |
1431 | break; | |
1432 | } | |
1433 | break; | |
1434 | ||
1435 | case 'm': | |
1436 | switch (opP->mode) | |
1437 | { | |
1438 | case DREG: | |
1439 | case AREG: | |
1440 | case AINDR: | |
1441 | case AINC: | |
1442 | case ADEC: | |
1443 | break; | |
1444 | default: | |
1445 | losing++; | |
1446 | } | |
8a104df9 | 1447 | break; |
252b5132 RH |
1448 | |
1449 | case 'n': | |
1450 | switch (opP->mode) | |
1451 | { | |
1452 | case DISP: | |
1453 | break; | |
1454 | default: | |
1455 | losing++; | |
1456 | } | |
8a104df9 | 1457 | break; |
252b5132 RH |
1458 | |
1459 | case 'o': | |
1460 | switch (opP->mode) | |
1461 | { | |
1462 | case BASE: | |
1463 | case ABSL: | |
1464 | case IMMED: | |
1465 | break; | |
1466 | default: | |
1467 | losing++; | |
1468 | } | |
8a104df9 | 1469 | break; |
252b5132 RH |
1470 | |
1471 | case 'p': | |
1472 | switch (opP->mode) | |
1473 | { | |
1474 | case DREG: | |
1475 | case AREG: | |
1476 | case AINDR: | |
1477 | case AINC: | |
1478 | case ADEC: | |
1479 | break; | |
1480 | case DISP: | |
1481 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1482 | losing++; |
252b5132 RH |
1483 | break; |
1484 | default: | |
1485 | losing++; | |
1486 | } | |
8a104df9 | 1487 | break; |
252b5132 RH |
1488 | |
1489 | case 'q': | |
1490 | switch (opP->mode) | |
1491 | { | |
1492 | case DREG: | |
1493 | case AINDR: | |
1494 | case AINC: | |
1495 | case ADEC: | |
1496 | break; | |
1497 | case DISP: | |
1498 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1499 | losing++; |
252b5132 RH |
1500 | break; |
1501 | default: | |
1502 | losing++; | |
1503 | break; | |
1504 | } | |
8a104df9 | 1505 | break; |
252b5132 RH |
1506 | |
1507 | case 'v': | |
1508 | switch (opP->mode) | |
1509 | { | |
1510 | case DREG: | |
1511 | case AINDR: | |
1512 | case AINC: | |
1513 | case ADEC: | |
1514 | case ABSL: | |
1515 | break; | |
1516 | case DISP: | |
1517 | if (opP->reg == PC || opP->reg == ZPC) | |
8a104df9 | 1518 | losing++; |
252b5132 RH |
1519 | break; |
1520 | default: | |
1521 | losing++; | |
1522 | break; | |
1523 | } | |
1524 | break; | |
1525 | ||
1526 | case '#': | |
1527 | if (opP->mode != IMMED) | |
1528 | losing++; | |
1529 | else if (s[1] == 'b' | |
1530 | && ! isvar (&opP->disp) | |
1531 | && (opP->disp.exp.X_op != O_constant | |
1532 | || ! isbyte (opP->disp.exp.X_add_number))) | |
1533 | losing++; | |
1534 | else if (s[1] == 'B' | |
1535 | && ! isvar (&opP->disp) | |
1536 | && (opP->disp.exp.X_op != O_constant | |
1537 | || ! issbyte (opP->disp.exp.X_add_number))) | |
1538 | losing++; | |
1539 | else if (s[1] == 'w' | |
1540 | && ! isvar (&opP->disp) | |
1541 | && (opP->disp.exp.X_op != O_constant | |
1542 | || ! isword (opP->disp.exp.X_add_number))) | |
1543 | losing++; | |
1544 | else if (s[1] == 'W' | |
1545 | && ! isvar (&opP->disp) | |
1546 | && (opP->disp.exp.X_op != O_constant | |
1547 | || ! issword (opP->disp.exp.X_add_number))) | |
1548 | losing++; | |
1549 | break; | |
1550 | ||
1551 | case '^': | |
1552 | case 'T': | |
1553 | if (opP->mode != IMMED) | |
1554 | losing++; | |
1555 | break; | |
1556 | ||
1557 | case '$': | |
1558 | if (opP->mode == AREG | |
1559 | || opP->mode == CONTROL | |
1560 | || opP->mode == FPREG | |
1561 | || opP->mode == IMMED | |
1562 | || opP->mode == REGLST | |
1563 | || (opP->mode != ABSL | |
1564 | && (opP->reg == PC | |
1565 | || opP->reg == ZPC))) | |
1566 | losing++; | |
1567 | break; | |
1568 | ||
1569 | case '%': | |
1570 | if (opP->mode == CONTROL | |
1571 | || opP->mode == FPREG | |
1572 | || opP->mode == REGLST | |
1573 | || opP->mode == IMMED | |
1574 | || (opP->mode != ABSL | |
1575 | && (opP->reg == PC | |
1576 | || opP->reg == ZPC))) | |
1577 | losing++; | |
1578 | break; | |
1579 | ||
1580 | case '&': | |
1581 | switch (opP->mode) | |
1582 | { | |
1583 | case DREG: | |
1584 | case AREG: | |
1585 | case FPREG: | |
1586 | case CONTROL: | |
1587 | case IMMED: | |
1588 | case AINC: | |
1589 | case ADEC: | |
1590 | case REGLST: | |
1591 | losing++; | |
1592 | break; | |
1593 | case ABSL: | |
1594 | break; | |
1595 | default: | |
1596 | if (opP->reg == PC | |
1597 | || opP->reg == ZPC) | |
1598 | losing++; | |
1599 | break; | |
1600 | } | |
1601 | break; | |
1602 | ||
1603 | case '*': | |
1604 | if (opP->mode == CONTROL | |
1605 | || opP->mode == FPREG | |
1606 | || opP->mode == REGLST) | |
1607 | losing++; | |
1608 | break; | |
1609 | ||
1610 | case '+': | |
1611 | if (opP->mode != AINC) | |
1612 | losing++; | |
1613 | break; | |
1614 | ||
1615 | case '-': | |
1616 | if (opP->mode != ADEC) | |
1617 | losing++; | |
1618 | break; | |
1619 | ||
1620 | case '/': | |
1621 | switch (opP->mode) | |
1622 | { | |
1623 | case AREG: | |
1624 | case CONTROL: | |
1625 | case FPREG: | |
1626 | case AINC: | |
1627 | case ADEC: | |
1628 | case IMMED: | |
1629 | case REGLST: | |
1630 | losing++; | |
1631 | break; | |
1632 | default: | |
1633 | break; | |
1634 | } | |
1635 | break; | |
1636 | ||
1637 | case ';': | |
1638 | switch (opP->mode) | |
1639 | { | |
1640 | case AREG: | |
1641 | case CONTROL: | |
1642 | case FPREG: | |
1643 | case REGLST: | |
1644 | losing++; | |
1645 | break; | |
1646 | default: | |
1647 | break; | |
1648 | } | |
1649 | break; | |
1650 | ||
1651 | case '?': | |
1652 | switch (opP->mode) | |
1653 | { | |
1654 | case AREG: | |
1655 | case CONTROL: | |
1656 | case FPREG: | |
1657 | case AINC: | |
1658 | case ADEC: | |
1659 | case IMMED: | |
1660 | case REGLST: | |
1661 | losing++; | |
1662 | break; | |
1663 | case ABSL: | |
1664 | break; | |
1665 | default: | |
1666 | if (opP->reg == PC || opP->reg == ZPC) | |
1667 | losing++; | |
1668 | break; | |
1669 | } | |
1670 | break; | |
1671 | ||
1672 | case '@': | |
1673 | switch (opP->mode) | |
1674 | { | |
1675 | case AREG: | |
1676 | case CONTROL: | |
1677 | case FPREG: | |
1678 | case IMMED: | |
1679 | case REGLST: | |
1680 | losing++; | |
1681 | break; | |
1682 | default: | |
1683 | break; | |
1684 | } | |
1685 | break; | |
1686 | ||
1687 | case '~': /* For now! (JF FOO is this right?) */ | |
1688 | switch (opP->mode) | |
1689 | { | |
1690 | case DREG: | |
1691 | case AREG: | |
1692 | case CONTROL: | |
1693 | case FPREG: | |
1694 | case IMMED: | |
1695 | case REGLST: | |
1696 | losing++; | |
1697 | break; | |
1698 | case ABSL: | |
1699 | break; | |
1700 | default: | |
1701 | if (opP->reg == PC | |
1702 | || opP->reg == ZPC) | |
1703 | losing++; | |
1704 | break; | |
1705 | } | |
1706 | break; | |
1707 | ||
1708 | case '3': | |
1709 | if (opP->mode != CONTROL | |
1710 | || (opP->reg != TT0 && opP->reg != TT1)) | |
1711 | losing++; | |
1712 | break; | |
1713 | ||
1714 | case 'A': | |
1715 | if (opP->mode != AREG) | |
1716 | losing++; | |
1717 | break; | |
1718 | ||
1719 | case 'a': | |
1720 | if (opP->mode != AINDR) | |
1721 | ++losing; | |
1722 | break; | |
1723 | ||
fd99574b NC |
1724 | case '4': |
1725 | if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC | |
1726 | && (opP->mode != DISP | |
1727 | || opP->reg < ADDR0 | |
1728 | || opP->reg > ADDR7)) | |
1729 | ++losing; | |
1730 | break; | |
1731 | ||
252b5132 RH |
1732 | case 'B': /* FOO */ |
1733 | if (opP->mode != ABSL | |
1734 | || (flag_long_jumps | |
1735 | && strncmp (instring, "jbsr", 4) == 0)) | |
1736 | losing++; | |
1737 | break; | |
1738 | ||
3e602632 NC |
1739 | case 'b': |
1740 | switch (opP->mode) | |
1741 | { | |
1742 | case IMMED: | |
1743 | case ABSL: | |
1744 | case AREG: | |
1745 | case FPREG: | |
1746 | case CONTROL: | |
1747 | case POST: | |
1748 | case PRE: | |
1749 | case REGLST: | |
1750 | losing++; | |
1751 | break; | |
1752 | default: | |
1753 | break; | |
1754 | } | |
1755 | break; | |
1756 | ||
252b5132 RH |
1757 | case 'C': |
1758 | if (opP->mode != CONTROL || opP->reg != CCR) | |
1759 | losing++; | |
1760 | break; | |
1761 | ||
1762 | case 'd': | |
1763 | if (opP->mode != DISP | |
1764 | || opP->reg < ADDR0 | |
1765 | || opP->reg > ADDR7) | |
1766 | losing++; | |
1767 | break; | |
1768 | ||
1769 | case 'D': | |
1770 | if (opP->mode != DREG) | |
1771 | losing++; | |
1772 | break; | |
1773 | ||
6da466c7 ILT |
1774 | case 'E': |
1775 | if (opP->reg != ACC) | |
1776 | losing++; | |
1777 | break; | |
1778 | ||
fd99574b NC |
1779 | case 'e': |
1780 | if (opP->reg != ACC && opP->reg != ACC1 | |
1781 | && opP->reg != ACC2 && opP->reg != ACC3) | |
1782 | losing++; | |
1783 | break; | |
1784 | ||
252b5132 RH |
1785 | case 'F': |
1786 | if (opP->mode != FPREG) | |
1787 | losing++; | |
1788 | break; | |
1789 | ||
6da466c7 ILT |
1790 | case 'G': |
1791 | if (opP->reg != MACSR) | |
1792 | losing++; | |
1793 | break; | |
1794 | ||
fd99574b NC |
1795 | case 'g': |
1796 | if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) | |
1797 | losing++; | |
1798 | break; | |
1799 | ||
6da466c7 ILT |
1800 | case 'H': |
1801 | if (opP->reg != MASK) | |
1802 | losing++; | |
1803 | break; | |
1804 | ||
252b5132 RH |
1805 | case 'I': |
1806 | if (opP->mode != CONTROL | |
1807 | || opP->reg < COP0 | |
1808 | || opP->reg > COP7) | |
1809 | losing++; | |
1810 | break; | |
1811 | ||
fd99574b NC |
1812 | case 'i': |
1813 | if (opP->mode != LSH && opP->mode != RSH) | |
1814 | losing++; | |
1815 | break; | |
1816 | ||
252b5132 RH |
1817 | case 'J': |
1818 | if (opP->mode != CONTROL | |
1819 | || opP->reg < USP | |
0b2e31dc NS |
1820 | || opP->reg > last_movec_reg |
1821 | || !control_regs) | |
252b5132 RH |
1822 | losing++; |
1823 | else | |
1824 | { | |
1825 | const enum m68k_register *rp; | |
0b2e31dc | 1826 | |
252b5132 | 1827 | for (rp = control_regs; *rp; rp++) |
78336706 NS |
1828 | { |
1829 | if (*rp == opP->reg) | |
1830 | break; | |
1831 | /* In most CPUs RAMBAR refers to control reg | |
1832 | c05 (RAMBAR1), but a few CPUs have it | |
1833 | refer to c04 (RAMBAR0). */ | |
1834 | else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR) | |
1835 | { | |
1836 | opP->reg = RAMBAR_ALT; | |
1837 | break; | |
1838 | } | |
1839 | } | |
252b5132 RH |
1840 | if (*rp == 0) |
1841 | losing++; | |
1842 | } | |
1843 | break; | |
1844 | ||
1845 | case 'k': | |
1846 | if (opP->mode != IMMED) | |
1847 | losing++; | |
1848 | break; | |
1849 | ||
1850 | case 'l': | |
1851 | case 'L': | |
1852 | if (opP->mode == DREG | |
1853 | || opP->mode == AREG | |
1854 | || opP->mode == FPREG) | |
1855 | { | |
1856 | if (s[1] == '8') | |
1857 | losing++; | |
1858 | else | |
1859 | { | |
1860 | switch (opP->mode) | |
1861 | { | |
1862 | case DREG: | |
1863 | opP->mask = 1 << (opP->reg - DATA0); | |
1864 | break; | |
1865 | case AREG: | |
1866 | opP->mask = 1 << (opP->reg - ADDR0 + 8); | |
1867 | break; | |
1868 | case FPREG: | |
1869 | opP->mask = 1 << (opP->reg - FP0 + 16); | |
1870 | break; | |
1871 | default: | |
1872 | abort (); | |
1873 | } | |
1874 | opP->mode = REGLST; | |
1875 | } | |
1876 | } | |
1877 | else if (opP->mode == CONTROL) | |
1878 | { | |
1879 | if (s[1] != '8') | |
1880 | losing++; | |
1881 | else | |
1882 | { | |
1883 | switch (opP->reg) | |
1884 | { | |
1885 | case FPI: | |
1886 | opP->mask = 1 << 24; | |
1887 | break; | |
1888 | case FPS: | |
1889 | opP->mask = 1 << 25; | |
1890 | break; | |
1891 | case FPC: | |
1892 | opP->mask = 1 << 26; | |
1893 | break; | |
1894 | default: | |
1895 | losing++; | |
1896 | break; | |
1897 | } | |
1898 | opP->mode = REGLST; | |
1899 | } | |
1900 | } | |
1901 | else if (opP->mode != REGLST) | |
1902 | losing++; | |
1903 | else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) | |
1904 | losing++; | |
1905 | else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) | |
1906 | losing++; | |
1907 | break; | |
1908 | ||
1909 | case 'M': | |
1910 | if (opP->mode != IMMED) | |
1911 | losing++; | |
1912 | else if (opP->disp.exp.X_op != O_constant | |
1913 | || ! issbyte (opP->disp.exp.X_add_number)) | |
1914 | losing++; | |
1915 | else if (! m68k_quick | |
1916 | && instring[3] != 'q' | |
1917 | && instring[4] != 'q') | |
1918 | losing++; | |
1919 | break; | |
1920 | ||
1921 | case 'O': | |
1922 | if (opP->mode != DREG | |
1923 | && opP->mode != IMMED | |
1924 | && opP->mode != ABSL) | |
1925 | losing++; | |
1926 | break; | |
1927 | ||
1928 | case 'Q': | |
1929 | if (opP->mode != IMMED) | |
1930 | losing++; | |
1931 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 | 1932 | || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) |
252b5132 RH |
1933 | losing++; |
1934 | else if (! m68k_quick | |
1935 | && (strncmp (instring, "add", 3) == 0 | |
1936 | || strncmp (instring, "sub", 3) == 0) | |
1937 | && instring[3] != 'q') | |
1938 | losing++; | |
1939 | break; | |
1940 | ||
1941 | case 'R': | |
1942 | if (opP->mode != DREG && opP->mode != AREG) | |
1943 | losing++; | |
1944 | break; | |
1945 | ||
1946 | case 'r': | |
1947 | if (opP->mode != AINDR | |
1948 | && (opP->mode != BASE | |
1949 | || (opP->reg != 0 | |
1950 | && opP->reg != ZADDR0) | |
1951 | || opP->disp.exp.X_op != O_absent | |
1952 | || ((opP->index.reg < DATA0 | |
1953 | || opP->index.reg > DATA7) | |
1954 | && (opP->index.reg < ADDR0 | |
1955 | || opP->index.reg > ADDR7)) | |
1956 | || opP->index.size != SIZE_UNSPEC | |
1957 | || opP->index.scale != 1)) | |
1958 | losing++; | |
1959 | break; | |
1960 | ||
1961 | case 's': | |
1962 | if (opP->mode != CONTROL | |
1963 | || ! (opP->reg == FPI | |
1964 | || opP->reg == FPS | |
1965 | || opP->reg == FPC)) | |
1966 | losing++; | |
1967 | break; | |
1968 | ||
1969 | case 'S': | |
1970 | if (opP->mode != CONTROL || opP->reg != SR) | |
1971 | losing++; | |
1972 | break; | |
1973 | ||
1974 | case 't': | |
1975 | if (opP->mode != IMMED) | |
1976 | losing++; | |
1977 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 | 1978 | || TRUNC (opP->disp.exp.X_add_number) > 7) |
252b5132 RH |
1979 | losing++; |
1980 | break; | |
1981 | ||
1982 | case 'U': | |
1983 | if (opP->mode != CONTROL || opP->reg != USP) | |
1984 | losing++; | |
1985 | break; | |
1986 | ||
3e602632 NC |
1987 | case 'x': |
1988 | if (opP->mode != IMMED) | |
1989 | losing++; | |
1990 | else if (opP->disp.exp.X_op != O_constant | |
bd17c2c3 AM |
1991 | || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff |
1992 | && TRUNC (opP->disp.exp.X_add_number) - 1 > 6)) | |
3e602632 NC |
1993 | losing++; |
1994 | break; | |
1995 | ||
afa2158f NS |
1996 | case 'j': |
1997 | if (opP->mode != IMMED) | |
1998 | losing++; | |
1999 | else if (opP->disp.exp.X_op != O_constant | |
2000 | || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) | |
2001 | losing++; | |
2002 | break; | |
2003 | ||
2004 | case 'K': | |
2005 | if (opP->mode != IMMED) | |
2006 | losing++; | |
2007 | else if (opP->disp.exp.X_op != O_constant | |
2008 | || TRUNC (opP->disp.exp.X_add_number) > 511) | |
2009 | losing++; | |
2010 | break; | |
2011 | ||
252b5132 RH |
2012 | /* JF these are out of order. We could put them |
2013 | in order if we were willing to put up with | |
2014 | bunches of #ifdef m68851s in the code. | |
2015 | ||
2016 | Don't forget that you need these operands | |
2017 | to use 68030 MMU instructions. */ | |
2018 | #ifndef NO_68851 | |
36759679 | 2019 | /* Memory addressing mode used by pflushr. */ |
252b5132 RH |
2020 | case '|': |
2021 | if (opP->mode == CONTROL | |
2022 | || opP->mode == FPREG | |
2023 | || opP->mode == DREG | |
2024 | || opP->mode == AREG | |
2025 | || opP->mode == REGLST) | |
2026 | losing++; | |
2027 | /* We should accept immediate operands, but they | |
2028 | supposedly have to be quad word, and we don't | |
2029 | handle that. I would like to see what a Motorola | |
2030 | assembler does before doing something here. */ | |
2031 | if (opP->mode == IMMED) | |
2032 | losing++; | |
2033 | break; | |
2034 | ||
2035 | case 'f': | |
2036 | if (opP->mode != CONTROL | |
2037 | || (opP->reg != SFC && opP->reg != DFC)) | |
2038 | losing++; | |
2039 | break; | |
2040 | ||
2041 | case '0': | |
2042 | if (opP->mode != CONTROL || opP->reg != TC) | |
2043 | losing++; | |
2044 | break; | |
2045 | ||
2046 | case '1': | |
2047 | if (opP->mode != CONTROL || opP->reg != AC) | |
2048 | losing++; | |
2049 | break; | |
2050 | ||
2051 | case '2': | |
2052 | if (opP->mode != CONTROL | |
2053 | || (opP->reg != CAL | |
2054 | && opP->reg != VAL | |
2055 | && opP->reg != SCC)) | |
2056 | losing++; | |
2057 | break; | |
2058 | ||
2059 | case 'V': | |
2060 | if (opP->mode != CONTROL | |
2061 | || opP->reg != VAL) | |
2062 | losing++; | |
2063 | break; | |
2064 | ||
2065 | case 'W': | |
2066 | if (opP->mode != CONTROL | |
2067 | || (opP->reg != DRP | |
2068 | && opP->reg != SRP | |
2069 | && opP->reg != CRP)) | |
2070 | losing++; | |
2071 | break; | |
2072 | ||
3e602632 NC |
2073 | case 'w': |
2074 | switch (opP->mode) | |
2075 | { | |
2076 | case IMMED: | |
2077 | case ABSL: | |
2078 | case AREG: | |
2079 | case DREG: | |
2080 | case FPREG: | |
2081 | case CONTROL: | |
2082 | case POST: | |
2083 | case PRE: | |
2084 | case REGLST: | |
2085 | losing++; | |
2086 | break; | |
2087 | default: | |
2088 | break; | |
2089 | } | |
2090 | break; | |
2091 | ||
252b5132 RH |
2092 | case 'X': |
2093 | if (opP->mode != CONTROL | |
2094 | || (!(opP->reg >= BAD && opP->reg <= BAD + 7) | |
2095 | && !(opP->reg >= BAC && opP->reg <= BAC + 7))) | |
2096 | losing++; | |
2097 | break; | |
2098 | ||
2099 | case 'Y': | |
2100 | if (opP->mode != CONTROL || opP->reg != PSR) | |
2101 | losing++; | |
2102 | break; | |
2103 | ||
2104 | case 'Z': | |
2105 | if (opP->mode != CONTROL || opP->reg != PCSR) | |
2106 | losing++; | |
2107 | break; | |
2108 | #endif | |
2109 | case 'c': | |
2110 | if (opP->mode != CONTROL | |
2111 | || (opP->reg != NC | |
2112 | && opP->reg != IC | |
2113 | && opP->reg != DC | |
2114 | && opP->reg != BC)) | |
36759679 | 2115 | losing++; |
252b5132 RH |
2116 | break; |
2117 | ||
2118 | case '_': | |
2119 | if (opP->mode != ABSL) | |
2120 | ++losing; | |
2121 | break; | |
2122 | ||
6da466c7 ILT |
2123 | case 'u': |
2124 | if (opP->reg < DATA0L || opP->reg > ADDR7U) | |
2125 | losing++; | |
2126 | /* FIXME: kludge instead of fixing parser: | |
2127 | upper/lower registers are *not* CONTROL | |
92774660 | 2128 | registers, but ordinary ones. */ |
6da466c7 ILT |
2129 | if ((opP->reg >= DATA0L && opP->reg <= DATA7L) |
2130 | || (opP->reg >= DATA0U && opP->reg <= DATA7U)) | |
2131 | opP->mode = DREG; | |
2132 | else | |
2133 | opP->mode = AREG; | |
2134 | break; | |
2135 | ||
3e602632 NC |
2136 | case 'y': |
2137 | if (!(opP->mode == AINDR | |
31302357 AS |
2138 | || (opP->mode == DISP |
2139 | && !(opP->reg == PC || opP->reg == ZPC)))) | |
3e602632 NC |
2140 | losing++; |
2141 | break; | |
2142 | ||
2143 | case 'z': | |
2144 | if (!(opP->mode == AINDR || opP->mode == DISP)) | |
2145 | losing++; | |
2146 | break; | |
2147 | ||
252b5132 RH |
2148 | default: |
2149 | abort (); | |
36759679 | 2150 | } |
252b5132 RH |
2151 | |
2152 | if (losing) | |
2153 | break; | |
36759679 | 2154 | } |
03b13e59 NC |
2155 | |
2156 | /* Since we have found the correct instruction, copy | |
2157 | in the modifications that we may have made. */ | |
2158 | if (!losing) | |
2159 | for (i = 0; i < opsfound; i++) | |
2160 | the_ins.operands[i] = operands_backup[i]; | |
36759679 | 2161 | } |
252b5132 RH |
2162 | |
2163 | if (!losing) | |
36759679 | 2164 | break; |
252b5132 RH |
2165 | |
2166 | opcode = opcode->m_next; | |
2167 | ||
2168 | if (!opcode) | |
2169 | { | |
2170 | if (ok_arch | |
2171 | && !(ok_arch & current_architecture)) | |
2172 | { | |
6d89cc8f NS |
2173 | const struct m68k_cpu *cpu; |
2174 | int any = 0; | |
2175 | size_t space = 400; | |
2176 | char *buf = xmalloc (space + 1); | |
2177 | size_t len; | |
2178 | int paren = 1; | |
2179 | ||
2180 | the_ins.error = buf; | |
2181 | /* Make sure there's a NUL at the end of the buffer -- strncpy | |
b2f58c0c | 2182 | won't write one when it runs out of buffer. */ |
6d89cc8f NS |
2183 | buf[space] = 0; |
2184 | #define APPEND(STRING) \ | |
2185 | (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len) | |
2186 | ||
2187 | APPEND (_("invalid instruction for this architecture; needs ")); | |
252b5132 RH |
2188 | switch (ok_arch) |
2189 | { | |
6b6e92f4 | 2190 | case mcfisa_a: |
b2f58c0c | 2191 | APPEND ("ColdFire ISA_A"); |
6b6e92f4 NC |
2192 | break; |
2193 | case mcfhwdiv: | |
b2f58c0c NC |
2194 | APPEND ("ColdFire "); |
2195 | APPEND (_("hardware divide")); | |
6b6e92f4 NC |
2196 | break; |
2197 | case mcfisa_aa: | |
b2f58c0c | 2198 | APPEND ("ColdFire ISA_A+"); |
6b6e92f4 NC |
2199 | break; |
2200 | case mcfisa_b: | |
b2f58c0c | 2201 | APPEND ("ColdFire ISA_B"); |
6b6e92f4 | 2202 | break; |
8d100c32 | 2203 | case mcfisa_c: |
b2f58c0c | 2204 | APPEND ("ColdFire ISA_C"); |
8d100c32 | 2205 | break; |
3e602632 | 2206 | case cfloat: |
b2f58c0c | 2207 | APPEND ("ColdFire fpu"); |
3e602632 | 2208 | break; |
252b5132 | 2209 | case mfloat: |
b2f58c0c | 2210 | APPEND ("M68K fpu"); |
252b5132 RH |
2211 | break; |
2212 | case mmmu: | |
b2f58c0c | 2213 | APPEND ("M68K mmu"); |
252b5132 RH |
2214 | break; |
2215 | case m68020up: | |
b2f58c0c NC |
2216 | APPEND ("68020 "); |
2217 | APPEND (_("or higher")); | |
252b5132 RH |
2218 | break; |
2219 | case m68000up: | |
b2f58c0c NC |
2220 | APPEND ("68000 "); |
2221 | APPEND (_("or higher")); | |
252b5132 RH |
2222 | break; |
2223 | case m68010up: | |
b2f58c0c NC |
2224 | APPEND ("68010 "); |
2225 | APPEND (_("or higher")); | |
252b5132 RH |
2226 | break; |
2227 | default: | |
6d89cc8f NS |
2228 | paren = 0; |
2229 | } | |
2230 | if (paren) | |
2231 | APPEND (" ("); | |
6b6e92f4 | 2232 | |
6d89cc8f NS |
2233 | for (cpu = m68k_cpus; cpu->name; cpu++) |
2234 | if (!cpu->alias && (cpu->arch & ok_arch)) | |
2235 | { | |
2236 | const struct m68k_cpu *alias; | |
869ddf2a NS |
2237 | int seen_master = 0; |
2238 | ||
6d89cc8f NS |
2239 | if (any) |
2240 | APPEND (", "); | |
2241 | any = 0; | |
2242 | APPEND (cpu->name); | |
869ddf2a NS |
2243 | for (alias = cpu; alias != m68k_cpus; alias--) |
2244 | if (alias[-1].alias >= 0) | |
2245 | break; | |
2246 | for (; !seen_master || alias->alias > 0; alias++) | |
6d89cc8f | 2247 | { |
869ddf2a NS |
2248 | if (!alias->alias) |
2249 | seen_master = 1; | |
2250 | else | |
2251 | { | |
2252 | if (any) | |
2253 | APPEND (", "); | |
2254 | else | |
2255 | APPEND (" ["); | |
2256 | APPEND (alias->name); | |
2257 | any = 1; | |
2258 | } | |
6d89cc8f | 2259 | } |
869ddf2a NS |
2260 | if (any) |
2261 | APPEND ("]"); | |
6d89cc8f | 2262 | any = 1; |
252b5132 | 2263 | } |
6d89cc8f NS |
2264 | if (paren) |
2265 | APPEND (")"); | |
2266 | #undef APPEND | |
2267 | if (!space) | |
2268 | { | |
b2f58c0c | 2269 | /* We ran out of space, so replace the end of the list |
6d89cc8f NS |
2270 | with ellipsis. */ |
2271 | buf -= 4; | |
2272 | while (*buf != ' ') | |
2273 | buf--; | |
2274 | strcpy (buf, " ..."); | |
252b5132 | 2275 | } |
252b5132 RH |
2276 | } |
2277 | else | |
2278 | the_ins.error = _("operands mismatch"); | |
2279 | return; | |
36759679 | 2280 | } |
252b5132 RH |
2281 | |
2282 | losing = 0; | |
2283 | } | |
2284 | ||
36759679 | 2285 | /* Now assemble it. */ |
252b5132 RH |
2286 | the_ins.args = opcode->m_operands; |
2287 | the_ins.numargs = opcode->m_opnum; | |
2288 | the_ins.numo = opcode->m_codenum; | |
2289 | the_ins.opcode[0] = getone (opcode); | |
2290 | the_ins.opcode[1] = gettwo (opcode); | |
2291 | ||
2292 | for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) | |
2293 | { | |
9a2e615a | 2294 | int have_disp = 0; |
cac27205 | 2295 | int use_pl = 0; |
9a2e615a | 2296 | |
252b5132 | 2297 | /* This switch is a doozy. |
31302357 | 2298 | Watch the first step; its a big one! */ |
252b5132 RH |
2299 | switch (s[0]) |
2300 | { | |
2301 | ||
2302 | case '*': | |
2303 | case '~': | |
2304 | case '%': | |
2305 | case ';': | |
2306 | case '@': | |
2307 | case '!': | |
2308 | case '&': | |
2309 | case '$': | |
2310 | case '?': | |
2311 | case '/': | |
2312 | case '<': | |
2313 | case '>': | |
3e602632 | 2314 | case 'b': |
252b5132 RH |
2315 | case 'm': |
2316 | case 'n': | |
2317 | case 'o': | |
2318 | case 'p': | |
2319 | case 'q': | |
2320 | case 'v': | |
3e602632 NC |
2321 | case 'w': |
2322 | case 'y': | |
2323 | case 'z': | |
fd99574b | 2324 | case '4': |
252b5132 RH |
2325 | #ifndef NO_68851 |
2326 | case '|': | |
2327 | #endif | |
2328 | switch (opP->mode) | |
2329 | { | |
2330 | case IMMED: | |
2331 | tmpreg = 0x3c; /* 7.4 */ | |
2332 | if (strchr ("bwl", s[1])) | |
3e602632 | 2333 | nextword = get_num (&opP->disp, 90); |
252b5132 RH |
2334 | else |
2335 | nextword = get_num (&opP->disp, 0); | |
2336 | if (isvar (&opP->disp)) | |
2337 | add_fix (s[1], &opP->disp, 0, 0); | |
2338 | switch (s[1]) | |
2339 | { | |
2340 | case 'b': | |
2341 | if (!isbyte (nextword)) | |
2342 | opP->error = _("operand out of range"); | |
2343 | addword (nextword); | |
2344 | baseo = 0; | |
2345 | break; | |
2346 | case 'w': | |
2347 | if (!isword (nextword)) | |
2348 | opP->error = _("operand out of range"); | |
2349 | addword (nextword); | |
2350 | baseo = 0; | |
2351 | break; | |
2352 | case 'W': | |
2353 | if (!issword (nextword)) | |
2354 | opP->error = _("operand out of range"); | |
2355 | addword (nextword); | |
2356 | baseo = 0; | |
2357 | break; | |
2358 | case 'l': | |
2359 | addword (nextword >> 16); | |
2360 | addword (nextword); | |
2361 | baseo = 0; | |
2362 | break; | |
2363 | ||
2364 | case 'f': | |
2365 | baseo = 2; | |
2366 | outro = 8; | |
2367 | break; | |
2368 | case 'F': | |
2369 | baseo = 4; | |
2370 | outro = 11; | |
2371 | break; | |
2372 | case 'x': | |
2373 | baseo = 6; | |
2374 | outro = 15; | |
2375 | break; | |
2376 | case 'p': | |
2377 | baseo = 6; | |
2378 | outro = -1; | |
2379 | break; | |
2380 | default: | |
2381 | abort (); | |
2382 | } | |
2383 | if (!baseo) | |
2384 | break; | |
2385 | ||
36759679 | 2386 | /* We gotta put out some float. */ |
252b5132 RH |
2387 | if (op (&opP->disp) != O_big) |
2388 | { | |
2389 | valueT val; | |
2390 | int gencnt; | |
2391 | ||
2392 | /* Can other cases happen here? */ | |
2393 | if (op (&opP->disp) != O_constant) | |
2394 | abort (); | |
2395 | ||
2396 | val = (valueT) offs (&opP->disp); | |
2397 | gencnt = 0; | |
2398 | do | |
2399 | { | |
2400 | generic_bignum[gencnt] = (LITTLENUM_TYPE) val; | |
2401 | val >>= LITTLENUM_NUMBER_OF_BITS; | |
2402 | ++gencnt; | |
2403 | } | |
2404 | while (val != 0); | |
2405 | offs (&opP->disp) = gencnt; | |
2406 | } | |
2407 | if (offs (&opP->disp) > 0) | |
2408 | { | |
2409 | if (offs (&opP->disp) > baseo) | |
2410 | { | |
2411 | as_warn (_("Bignum too big for %c format; truncated"), | |
2412 | s[1]); | |
2413 | offs (&opP->disp) = baseo; | |
2414 | } | |
2415 | baseo -= offs (&opP->disp); | |
2416 | while (baseo--) | |
2417 | addword (0); | |
2418 | for (wordp = generic_bignum + offs (&opP->disp) - 1; | |
2419 | offs (&opP->disp)--; | |
2420 | --wordp) | |
2421 | addword (*wordp); | |
2422 | break; | |
2423 | } | |
2424 | gen_to_words (words, baseo, (long) outro); | |
2425 | for (wordp = words; baseo--; wordp++) | |
2426 | addword (*wordp); | |
2427 | break; | |
2428 | case DREG: | |
2429 | tmpreg = opP->reg - DATA; /* 0.dreg */ | |
2430 | break; | |
2431 | case AREG: | |
2432 | tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ | |
2433 | break; | |
2434 | case AINDR: | |
2435 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2436 | break; | |
2437 | case ADEC: | |
2438 | tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ | |
2439 | break; | |
2440 | case AINC: | |
2441 | tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ | |
2442 | break; | |
2443 | case DISP: | |
2444 | ||
3e602632 | 2445 | nextword = get_num (&opP->disp, 90); |
252b5132 | 2446 | |
580b9172 NC |
2447 | /* Convert mode 5 addressing with a zero offset into |
2448 | mode 2 addressing to reduce the instruction size by a | |
2449 | word. */ | |
2450 | if (! isvar (&opP->disp) | |
2451 | && (nextword == 0) | |
2452 | && (opP->disp.size == SIZE_UNSPEC) | |
2453 | && (opP->reg >= ADDR0) | |
2454 | && (opP->reg <= ADDR7)) | |
2455 | { | |
2456 | tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ | |
2457 | break; | |
2458 | } | |
2459 | ||
252b5132 RH |
2460 | if (opP->reg == PC |
2461 | && ! isvar (&opP->disp) | |
2462 | && m68k_abspcadd) | |
2463 | { | |
2464 | opP->disp.exp.X_op = O_symbol; | |
252b5132 RH |
2465 | opP->disp.exp.X_add_symbol = |
2466 | section_symbol (absolute_section); | |
252b5132 RH |
2467 | } |
2468 | ||
36759679 | 2469 | /* Force into index mode. Hope this works. */ |
252b5132 RH |
2470 | |
2471 | /* We do the first bit for 32-bit displacements, and the | |
2472 | second bit for 16 bit ones. It is possible that we | |
2473 | should make the default be WORD instead of LONG, but | |
2474 | I think that'd break GCC, so we put up with a little | |
2475 | inefficiency for the sake of working output. */ | |
2476 | ||
2477 | if (!issword (nextword) | |
2478 | || (isvar (&opP->disp) | |
2479 | && ((opP->disp.size == SIZE_UNSPEC | |
2480 | && flag_short_refs == 0 | |
2481 | && cpu_of_arch (current_architecture) >= m68020 | |
6da466c7 | 2482 | && ! arch_coldfire_p (current_architecture)) |
252b5132 RH |
2483 | || opP->disp.size == SIZE_LONG))) |
2484 | { | |
2485 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2486 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
2487 | opP->error = |
2488 | _("displacement too large for this architecture; needs 68020 or higher"); | |
2489 | if (opP->reg == PC) | |
2490 | tmpreg = 0x3B; /* 7.3 */ | |
2491 | else | |
2492 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2493 | if (isvar (&opP->disp)) | |
2494 | { | |
2495 | if (opP->reg == PC) | |
2496 | { | |
2497 | if (opP->disp.size == SIZE_LONG | |
2498 | #ifdef OBJ_ELF | |
2499 | /* If the displacement needs pic | |
2500 | relocation it cannot be relaxed. */ | |
2501 | || opP->disp.pic_reloc != pic_none | |
2502 | #endif | |
2503 | ) | |
2504 | { | |
2505 | addword (0x0170); | |
2506 | add_fix ('l', &opP->disp, 1, 2); | |
2507 | } | |
2508 | else | |
2509 | { | |
2510 | add_frag (adds (&opP->disp), | |
bd17c2c3 | 2511 | SEXT (offs (&opP->disp)), |
151337e8 | 2512 | TAB (PCREL1632, SZ_UNDEF)); |
252b5132 RH |
2513 | break; |
2514 | } | |
2515 | } | |
2516 | else | |
2517 | { | |
2518 | addword (0x0170); | |
2519 | add_fix ('l', &opP->disp, 0, 0); | |
2520 | } | |
2521 | } | |
2522 | else | |
2523 | addword (0x0170); | |
2524 | addword (nextword >> 16); | |
2525 | } | |
2526 | else | |
2527 | { | |
2528 | if (opP->reg == PC) | |
2529 | tmpreg = 0x3A; /* 7.2 */ | |
2530 | else | |
2531 | tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ | |
2532 | ||
2533 | if (isvar (&opP->disp)) | |
2534 | { | |
2535 | if (opP->reg == PC) | |
2536 | { | |
2537 | add_fix ('w', &opP->disp, 1, 0); | |
2538 | } | |
2539 | else | |
2540 | add_fix ('w', &opP->disp, 0, 0); | |
2541 | } | |
2542 | } | |
2543 | addword (nextword); | |
2544 | break; | |
2545 | ||
2546 | case POST: | |
2547 | case PRE: | |
2548 | case BASE: | |
2549 | nextword = 0; | |
3e602632 | 2550 | baseo = get_num (&opP->disp, 90); |
252b5132 | 2551 | if (opP->mode == POST || opP->mode == PRE) |
3e602632 | 2552 | outro = get_num (&opP->odisp, 90); |
252b5132 RH |
2553 | /* Figure out the `addressing mode'. |
2554 | Also turn on the BASE_DISABLE bit, if needed. */ | |
2555 | if (opP->reg == PC || opP->reg == ZPC) | |
2556 | { | |
2557 | tmpreg = 0x3b; /* 7.3 */ | |
2558 | if (opP->reg == ZPC) | |
2559 | nextword |= 0x80; | |
2560 | } | |
2561 | else if (opP->reg == 0) | |
2562 | { | |
2563 | nextword |= 0x80; | |
2564 | tmpreg = 0x30; /* 6.garbage */ | |
2565 | } | |
2566 | else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) | |
2567 | { | |
2568 | nextword |= 0x80; | |
2569 | tmpreg = 0x30 + opP->reg - ZADDR0; | |
2570 | } | |
2571 | else | |
2572 | tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ | |
2573 | ||
2574 | siz1 = opP->disp.size; | |
2575 | if (opP->mode == POST || opP->mode == PRE) | |
2576 | siz2 = opP->odisp.size; | |
2577 | else | |
2578 | siz2 = SIZE_UNSPEC; | |
2579 | ||
36759679 | 2580 | /* Index register stuff. */ |
252b5132 RH |
2581 | if (opP->index.reg != 0 |
2582 | && opP->index.reg >= DATA | |
2583 | && opP->index.reg <= ADDR7) | |
2584 | { | |
2585 | nextword |= (opP->index.reg - DATA) << 12; | |
2586 | ||
2587 | if (opP->index.size == SIZE_LONG | |
2588 | || (opP->index.size == SIZE_UNSPEC | |
2589 | && m68k_index_width_default == SIZE_LONG)) | |
2590 | nextword |= 0x800; | |
2591 | ||
92774660 | 2592 | if ((opP->index.scale != 1 |
252b5132 | 2593 | && cpu_of_arch (current_architecture) < m68020) |
92774660 | 2594 | || (opP->index.scale == 8 |
3e602632 | 2595 | && (arch_coldfire_p (current_architecture) |
6b6e92f4 | 2596 | && !arch_coldfire_fpu (current_architecture)))) |
252b5132 RH |
2597 | { |
2598 | opP->error = | |
2599 | _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); | |
2600 | } | |
2601 | ||
6da466c7 ILT |
2602 | if (arch_coldfire_p (current_architecture) |
2603 | && opP->index.size == SIZE_WORD) | |
2604 | opP->error = _("invalid index size for coldfire"); | |
2605 | ||
252b5132 RH |
2606 | switch (opP->index.scale) |
2607 | { | |
2608 | case 1: | |
2609 | break; | |
2610 | case 2: | |
2611 | nextword |= 0x200; | |
2612 | break; | |
2613 | case 4: | |
2614 | nextword |= 0x400; | |
2615 | break; | |
2616 | case 8: | |
2617 | nextword |= 0x600; | |
2618 | break; | |
2619 | default: | |
2620 | abort (); | |
2621 | } | |
2622 | /* IF its simple, | |
2623 | GET US OUT OF HERE! */ | |
2624 | ||
2625 | /* Must be INDEX, with an index register. Address | |
2626 | register cannot be ZERO-PC, and either :b was | |
2627 | forced, or we know it will fit. For a 68000 or | |
2628 | 68010, force this mode anyways, because the | |
2629 | larger modes aren't supported. */ | |
2630 | if (opP->mode == BASE | |
2631 | && ((opP->reg >= ADDR0 | |
2632 | && opP->reg <= ADDR7) | |
2633 | || opP->reg == PC)) | |
2634 | { | |
2635 | if (siz1 == SIZE_BYTE | |
2636 | || cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2637 | || arch_coldfire_p (current_architecture) |
252b5132 RH |
2638 | || (siz1 == SIZE_UNSPEC |
2639 | && ! isvar (&opP->disp) | |
2640 | && issbyte (baseo))) | |
2641 | { | |
2642 | nextword += baseo & 0xff; | |
2643 | addword (nextword); | |
2644 | if (isvar (&opP->disp)) | |
2645 | { | |
2646 | /* Do a byte relocation. If it doesn't | |
2647 | fit (possible on m68000) let the | |
2648 | fixup processing complain later. */ | |
2649 | if (opP->reg == PC) | |
2650 | add_fix ('B', &opP->disp, 1, 1); | |
2651 | else | |
2652 | add_fix ('B', &opP->disp, 0, 0); | |
2653 | } | |
2654 | else if (siz1 != SIZE_BYTE) | |
2655 | { | |
2656 | if (siz1 != SIZE_UNSPEC) | |
2657 | as_warn (_("Forcing byte displacement")); | |
2658 | if (! issbyte (baseo)) | |
2659 | opP->error = _("byte displacement out of range"); | |
2660 | } | |
2661 | ||
2662 | break; | |
2663 | } | |
2664 | else if (siz1 == SIZE_UNSPEC | |
2665 | && opP->reg == PC | |
2666 | && isvar (&opP->disp) | |
2667 | && subs (&opP->disp) == NULL | |
2668 | #ifdef OBJ_ELF | |
2669 | /* If the displacement needs pic | |
2670 | relocation it cannot be relaxed. */ | |
2671 | && opP->disp.pic_reloc == pic_none | |
2672 | #endif | |
2673 | ) | |
2674 | { | |
2675 | /* The code in md_convert_frag_1 needs to be | |
2676 | able to adjust nextword. Call frag_grow | |
2677 | to ensure that we have enough space in | |
2678 | the frag obstack to make all the bytes | |
2679 | contiguous. */ | |
2680 | frag_grow (14); | |
8a104df9 KH |
2681 | nextword += baseo & 0xff; |
2682 | addword (nextword); | |
bd17c2c3 AM |
2683 | add_frag (adds (&opP->disp), |
2684 | SEXT (offs (&opP->disp)), | |
8a104df9 | 2685 | TAB (PCINDEX, SZ_UNDEF)); |
252b5132 RH |
2686 | |
2687 | break; | |
8a104df9 | 2688 | } |
252b5132 RH |
2689 | } |
2690 | } | |
2691 | else | |
2692 | { | |
36759679 | 2693 | nextword |= 0x40; /* No index reg. */ |
252b5132 RH |
2694 | if (opP->index.reg >= ZDATA0 |
2695 | && opP->index.reg <= ZDATA7) | |
2696 | nextword |= (opP->index.reg - ZDATA0) << 12; | |
2697 | else if (opP->index.reg >= ZADDR0 | |
2698 | || opP->index.reg <= ZADDR7) | |
2699 | nextword |= (opP->index.reg - ZADDR0 + 8) << 12; | |
2700 | } | |
2701 | ||
2702 | /* It isn't simple. */ | |
2703 | ||
2704 | if (cpu_of_arch (current_architecture) < m68020 | |
6da466c7 | 2705 | || arch_coldfire_p (current_architecture)) |
252b5132 RH |
2706 | opP->error = |
2707 | _("invalid operand mode for this architecture; needs 68020 or higher"); | |
2708 | ||
2709 | nextword |= 0x100; | |
2710 | /* If the guy specified a width, we assume that it is | |
2711 | wide enough. Maybe it isn't. If so, we lose. */ | |
2712 | switch (siz1) | |
2713 | { | |
2714 | case SIZE_UNSPEC: | |
2715 | if (isvar (&opP->disp) | |
2716 | ? m68k_rel32 | |
2717 | : ! issword (baseo)) | |
2718 | { | |
2719 | siz1 = SIZE_LONG; | |
2720 | nextword |= 0x30; | |
2721 | } | |
2722 | else if (! isvar (&opP->disp) && baseo == 0) | |
2723 | nextword |= 0x10; | |
2724 | else | |
2725 | { | |
2726 | nextword |= 0x20; | |
2727 | siz1 = SIZE_WORD; | |
2728 | } | |
2729 | break; | |
2730 | case SIZE_BYTE: | |
2731 | as_warn (_(":b not permitted; defaulting to :w")); | |
2732 | /* Fall through. */ | |
2733 | case SIZE_WORD: | |
2734 | nextword |= 0x20; | |
2735 | break; | |
2736 | case SIZE_LONG: | |
2737 | nextword |= 0x30; | |
2738 | break; | |
2739 | } | |
2740 | ||
67c1ffbe | 2741 | /* Figure out inner displacement stuff. */ |
252b5132 RH |
2742 | if (opP->mode == POST || opP->mode == PRE) |
2743 | { | |
2744 | if (cpu_of_arch (current_architecture) & cpu32) | |
2745 | opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); | |
2746 | switch (siz2) | |
2747 | { | |
2748 | case SIZE_UNSPEC: | |
2749 | if (isvar (&opP->odisp) | |
2750 | ? m68k_rel32 | |
2751 | : ! issword (outro)) | |
2752 | { | |
2753 | siz2 = SIZE_LONG; | |
2754 | nextword |= 0x3; | |
2755 | } | |
2756 | else if (! isvar (&opP->odisp) && outro == 0) | |
2757 | nextword |= 0x1; | |
2758 | else | |
2759 | { | |
2760 | nextword |= 0x2; | |
2761 | siz2 = SIZE_WORD; | |
2762 | } | |
2763 | break; | |
2764 | case 1: | |
2765 | as_warn (_(":b not permitted; defaulting to :w")); | |
2766 | /* Fall through. */ | |
2767 | case 2: | |
2768 | nextword |= 0x2; | |
2769 | break; | |
2770 | case 3: | |
2771 | nextword |= 0x3; | |
2772 | break; | |
2773 | } | |
2774 | if (opP->mode == POST | |
2775 | && (nextword & 0x40) == 0) | |
2776 | nextword |= 0x04; | |
2777 | } | |
2778 | addword (nextword); | |
2779 | ||
2780 | if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) | |
2781 | { | |
2782 | if (opP->reg == PC || opP->reg == ZPC) | |
2783 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); | |
2784 | else | |
2785 | add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); | |
2786 | } | |
2787 | if (siz1 == SIZE_LONG) | |
2788 | addword (baseo >> 16); | |
2789 | if (siz1 != SIZE_UNSPEC) | |
2790 | addword (baseo); | |
2791 | ||
2792 | if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) | |
2793 | add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); | |
2794 | if (siz2 == SIZE_LONG) | |
2795 | addword (outro >> 16); | |
2796 | if (siz2 != SIZE_UNSPEC) | |
2797 | addword (outro); | |
2798 | ||
2799 | break; | |
2800 | ||
2801 | case ABSL: | |
3e602632 | 2802 | nextword = get_num (&opP->disp, 90); |
252b5132 RH |
2803 | switch (opP->disp.size) |
2804 | { | |
2805 | default: | |
2806 | abort (); | |
2807 | case SIZE_UNSPEC: | |
2808 | if (!isvar (&opP->disp) && issword (offs (&opP->disp))) | |
2809 | { | |
2810 | tmpreg = 0x38; /* 7.0 */ | |
2811 | addword (nextword); | |
2812 | break; | |
2813 | } | |
252b5132 RH |
2814 | if (isvar (&opP->disp) |
2815 | && !subs (&opP->disp) | |
2816 | && adds (&opP->disp) | |
2817 | #ifdef OBJ_ELF | |
2818 | /* If the displacement needs pic relocation it | |
2819 | cannot be relaxed. */ | |
2820 | && opP->disp.pic_reloc == pic_none | |
2821 | #endif | |
252b5132 RH |
2822 | && !flag_long_jumps |
2823 | && !strchr ("~%&$?", s[0])) | |
2824 | { | |
2825 | tmpreg = 0x3A; /* 7.2 */ | |
2826 | add_frag (adds (&opP->disp), | |
bd17c2c3 | 2827 | SEXT (offs (&opP->disp)), |
151337e8 | 2828 | TAB (ABSTOPCREL, SZ_UNDEF)); |
252b5132 RH |
2829 | break; |
2830 | } | |
36759679 | 2831 | /* Fall through into long. */ |
252b5132 RH |
2832 | case SIZE_LONG: |
2833 | if (isvar (&opP->disp)) | |
2834 | add_fix ('l', &opP->disp, 0, 0); | |
2835 | ||
2836 | tmpreg = 0x39;/* 7.1 mode */ | |
2837 | addword (nextword >> 16); | |
2838 | addword (nextword); | |
2839 | break; | |
2840 | ||
2841 | case SIZE_BYTE: | |
2842 | as_bad (_("unsupported byte value; use a different suffix")); | |
2843 | /* Fall through. */ | |
36759679 NC |
2844 | |
2845 | case SIZE_WORD: | |
252b5132 RH |
2846 | if (isvar (&opP->disp)) |
2847 | add_fix ('w', &opP->disp, 0, 0); | |
2848 | ||
2849 | tmpreg = 0x38;/* 7.0 mode */ | |
2850 | addword (nextword); | |
2851 | break; | |
2852 | } | |
2853 | break; | |
2854 | case CONTROL: | |
2855 | case FPREG: | |
2856 | default: | |
2857 | as_bad (_("unknown/incorrect operand")); | |
bc805888 | 2858 | /* abort (); */ |
252b5132 | 2859 | } |
fd99574b NC |
2860 | |
2861 | /* If s[0] is '4', then this is for the mac instructions | |
2862 | that can have a trailing_ampersand set. If so, set 0x100 | |
2863 | bit on tmpreg so install_gen_operand can check for it and | |
2864 | set the appropriate bit (word2, bit 5). */ | |
2865 | if (s[0] == '4') | |
2866 | { | |
2867 | if (opP->trailing_ampersand) | |
2868 | tmpreg |= 0x100; | |
2869 | } | |
252b5132 RH |
2870 | install_gen_operand (s[1], tmpreg); |
2871 | break; | |
2872 | ||
2873 | case '#': | |
2874 | case '^': | |
2875 | switch (s[1]) | |
2876 | { /* JF: I hate floating point! */ | |
2877 | case 'j': | |
2878 | tmpreg = 70; | |
2879 | break; | |
2880 | case '8': | |
2881 | tmpreg = 20; | |
2882 | break; | |
2883 | case 'C': | |
2884 | tmpreg = 50; | |
2885 | break; | |
2886 | case '3': | |
2887 | default: | |
3e602632 | 2888 | tmpreg = 90; |
252b5132 RH |
2889 | break; |
2890 | } | |
2891 | tmpreg = get_num (&opP->disp, tmpreg); | |
2892 | if (isvar (&opP->disp)) | |
2893 | add_fix (s[1], &opP->disp, 0, 0); | |
2894 | switch (s[1]) | |
2895 | { | |
2896 | case 'b': /* Danger: These do no check for | |
2897 | certain types of overflow. | |
2898 | user beware! */ | |
2899 | if (!isbyte (tmpreg)) | |
2900 | opP->error = _("out of range"); | |
2901 | insop (tmpreg, opcode); | |
2902 | if (isvar (&opP->disp)) | |
2903 | the_ins.reloc[the_ins.nrel - 1].n = | |
2904 | (opcode->m_codenum) * 2 + 1; | |
2905 | break; | |
2906 | case 'B': | |
2907 | if (!issbyte (tmpreg)) | |
2908 | opP->error = _("out of range"); | |
2909 | the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; | |
2910 | if (isvar (&opP->disp)) | |
2911 | the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; | |
2912 | break; | |
2913 | case 'w': | |
2914 | if (!isword (tmpreg)) | |
2915 | opP->error = _("out of range"); | |
2916 | insop (tmpreg, opcode); | |
2917 | if (isvar (&opP->disp)) | |
2918 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2919 | break; | |
2920 | case 'W': | |
2921 | if (!issword (tmpreg)) | |
2922 | opP->error = _("out of range"); | |
2923 | insop (tmpreg, opcode); | |
2924 | if (isvar (&opP->disp)) | |
2925 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2926 | break; | |
2927 | case 'l': | |
2928 | /* Because of the way insop works, we put these two out | |
2929 | backwards. */ | |
2930 | insop (tmpreg, opcode); | |
2931 | insop (tmpreg >> 16, opcode); | |
2932 | if (isvar (&opP->disp)) | |
2933 | the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; | |
2934 | break; | |
2935 | case '3': | |
2936 | tmpreg &= 0xFF; | |
2937 | case '8': | |
2938 | case 'C': | |
2939 | case 'j': | |
2940 | install_operand (s[1], tmpreg); | |
2941 | break; | |
2942 | default: | |
2943 | abort (); | |
2944 | } | |
2945 | break; | |
2946 | ||
2947 | case '+': | |
2948 | case '-': | |
2949 | case 'A': | |
2950 | case 'a': | |
2951 | install_operand (s[1], opP->reg - ADDR); | |
2952 | break; | |
2953 | ||
2954 | case 'B': | |
3e602632 | 2955 | tmpreg = get_num (&opP->disp, 90); |
9a2e615a | 2956 | |
252b5132 RH |
2957 | switch (s[1]) |
2958 | { | |
2959 | case 'B': | |
8390138c | 2960 | add_fix ('B', &opP->disp, 1, -1); |
252b5132 RH |
2961 | break; |
2962 | case 'W': | |
2963 | add_fix ('w', &opP->disp, 1, 0); | |
2964 | addword (0); | |
2965 | break; | |
2966 | case 'L': | |
2967 | long_branch: | |
151337e8 | 2968 | the_ins.opcode[0] |= 0xff; |
252b5132 RH |
2969 | add_fix ('l', &opP->disp, 1, 0); |
2970 | addword (0); | |
2971 | addword (0); | |
2972 | break; | |
9a2e615a NS |
2973 | case 'g': /* Conditional branch */ |
2974 | have_disp = HAVE_LONG_CALL (current_architecture); | |
2975 | goto var_branch; | |
2976 | ||
2977 | case 'b': /* Unconditional branch */ | |
2978 | have_disp = HAVE_LONG_BRANCH (current_architecture); | |
cac27205 | 2979 | use_pl = LONG_BRANCH_VIA_COND (current_architecture); |
9a2e615a NS |
2980 | goto var_branch; |
2981 | ||
2982 | case 's': /* Unconditional subroutine */ | |
2983 | have_disp = HAVE_LONG_CALL (current_architecture); | |
2984 | ||
2985 | var_branch: | |
2986 | if (subs (&opP->disp) /* We can't relax it. */ | |
252b5132 | 2987 | #ifdef OBJ_ELF |
9a2e615a NS |
2988 | /* If the displacement needs pic relocation it cannot be |
2989 | relaxed. */ | |
2990 | || opP->disp.pic_reloc != pic_none | |
252b5132 | 2991 | #endif |
9a2e615a NS |
2992 | || 0) |
2993 | { | |
2994 | if (!have_disp) | |
2995 | as_warn (_("Can't use long branches on this architecture")); | |
2996 | goto long_branch; | |
2997 | } | |
2998 | ||
252b5132 | 2999 | /* This could either be a symbol, or an absolute |
151337e8 NC |
3000 | address. If it's an absolute address, turn it into |
3001 | an absolute jump right here and keep it out of the | |
3002 | relaxer. */ | |
3003 | if (adds (&opP->disp) == 0) | |
3004 | { | |
3005 | if (the_ins.opcode[0] == 0x6000) /* jbra */ | |
18566f55 | 3006 | the_ins.opcode[0] = 0x4EF9; |
151337e8 | 3007 | else if (the_ins.opcode[0] == 0x6100) /* jbsr */ |
18566f55 | 3008 | the_ins.opcode[0] = 0x4EB9; |
151337e8 NC |
3009 | else /* jCC */ |
3010 | { | |
3011 | the_ins.opcode[0] ^= 0x0100; | |
3012 | the_ins.opcode[0] |= 0x0006; | |
18566f55 | 3013 | addword (0x4EF9); |
151337e8 NC |
3014 | } |
3015 | add_fix ('l', &opP->disp, 0, 0); | |
3016 | addword (0); | |
3017 | addword (0); | |
3018 | break; | |
3019 | } | |
3020 | ||
3021 | /* Now we know it's going into the relaxer. Now figure | |
3022 | out which mode. We try in this order of preference: | |
3023 | long branch, absolute jump, byte/word branches only. */ | |
9a2e615a | 3024 | if (have_disp) |
bd17c2c3 AM |
3025 | add_frag (adds (&opP->disp), |
3026 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3027 | TAB (BRANCHBWL, SZ_UNDEF)); |
3028 | else if (! flag_keep_pcrel) | |
3029 | { | |
3030 | if ((the_ins.opcode[0] == 0x6000) | |
3031 | || (the_ins.opcode[0] == 0x6100)) | |
bd17c2c3 AM |
3032 | add_frag (adds (&opP->disp), |
3033 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3034 | TAB (BRABSJUNC, SZ_UNDEF)); |
3035 | else | |
bd17c2c3 AM |
3036 | add_frag (adds (&opP->disp), |
3037 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3038 | TAB (BRABSJCOND, SZ_UNDEF)); |
3039 | } | |
252b5132 | 3040 | else |
bd17c2c3 AM |
3041 | add_frag (adds (&opP->disp), |
3042 | SEXT (offs (&opP->disp)), | |
cac27205 NC |
3043 | (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF) |
3044 | : TAB (BRANCHBW, SZ_UNDEF))); | |
252b5132 RH |
3045 | break; |
3046 | case 'w': | |
3047 | if (isvar (&opP->disp)) | |
3048 | { | |
151337e8 NC |
3049 | /* Check for DBcc instructions. We can relax them, |
3050 | but only if we have long branches and/or absolute | |
3051 | jumps. */ | |
3052 | if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) | |
3053 | && (HAVE_LONG_BRANCH (current_architecture) | |
9a2e615a | 3054 | || ! flag_keep_pcrel)) |
252b5132 | 3055 | { |
151337e8 | 3056 | if (HAVE_LONG_BRANCH (current_architecture)) |
bd17c2c3 AM |
3057 | add_frag (adds (&opP->disp), |
3058 | SEXT (offs (&opP->disp)), | |
151337e8 NC |
3059 | TAB (DBCCLBR, SZ_UNDEF)); |
3060 | else | |
bd17c2c3 AM |
3061 | add_frag (adds (&opP->disp), |
3062 | SEXT (offs (&opP->disp)), | |
151337e8 | 3063 | TAB (DBCCABSJ, SZ_UNDEF)); |
252b5132 RH |
3064 | break; |
3065 | } | |
252b5132 RH |
3066 | add_fix ('w', &opP->disp, 1, 0); |
3067 | } | |
3068 | addword (0); | |
3069 | break; | |
36759679 | 3070 | case 'C': /* Fixed size LONG coproc branches. */ |
252b5132 RH |
3071 | add_fix ('l', &opP->disp, 1, 0); |
3072 | addword (0); | |
3073 | addword (0); | |
3074 | break; | |
36759679 | 3075 | case 'c': /* Var size Coprocesssor branches. */ |
151337e8 | 3076 | if (subs (&opP->disp) || (adds (&opP->disp) == 0)) |
252b5132 | 3077 | { |
252b5132 RH |
3078 | the_ins.opcode[the_ins.numo - 1] |= 0x40; |
3079 | add_fix ('l', &opP->disp, 1, 0); | |
3080 | addword (0); | |
3081 | addword (0); | |
3082 | } | |
151337e8 | 3083 | else |
bd17c2c3 AM |
3084 | add_frag (adds (&opP->disp), |
3085 | SEXT (offs (&opP->disp)), | |
151337e8 | 3086 | TAB (FBRANCH, SZ_UNDEF)); |
252b5132 RH |
3087 | break; |
3088 | default: | |
3089 | abort (); | |
3090 | } | |
3091 | break; | |
3092 | ||
36759679 | 3093 | case 'C': /* Ignore it. */ |
252b5132 RH |
3094 | break; |
3095 | ||
36759679 | 3096 | case 'd': /* JF this is a kludge. */ |
252b5132 | 3097 | install_operand ('s', opP->reg - ADDR); |
3e602632 | 3098 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
3099 | if (!issword (tmpreg)) |
3100 | { | |
3101 | as_warn (_("Expression out of range, using 0")); | |
3102 | tmpreg = 0; | |
3103 | } | |
3104 | addword (tmpreg); | |
3105 | break; | |
3106 | ||
3107 | case 'D': | |
3108 | install_operand (s[1], opP->reg - DATA); | |
3109 | break; | |
3110 | ||
fd99574b NC |
3111 | case 'e': /* EMAC ACCx, reg/reg. */ |
3112 | install_operand (s[1], opP->reg - ACC); | |
3113 | break; | |
3114 | ||
36759679 | 3115 | case 'E': /* Ignore it. */ |
6da466c7 ILT |
3116 | break; |
3117 | ||
252b5132 RH |
3118 | case 'F': |
3119 | install_operand (s[1], opP->reg - FP0); | |
3120 | break; | |
3121 | ||
fd99574b NC |
3122 | case 'g': /* EMAC ACCEXTx. */ |
3123 | install_operand (s[1], opP->reg - ACCEXT01); | |
3124 | break; | |
3125 | ||
36759679 | 3126 | case 'G': /* Ignore it. */ |
6da466c7 ILT |
3127 | case 'H': |
3128 | break; | |
3129 | ||
252b5132 RH |
3130 | case 'I': |
3131 | tmpreg = opP->reg - COP0; | |
3132 | install_operand (s[1], tmpreg); | |
3133 | break; | |
3134 | ||
fd99574b NC |
3135 | case 'i': /* MAC/EMAC scale factor. */ |
3136 | install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); | |
3137 | break; | |
3138 | ||
36759679 | 3139 | case 'J': /* JF foo. */ |
252b5132 RH |
3140 | switch (opP->reg) |
3141 | { | |
3142 | case SFC: | |
3143 | tmpreg = 0x000; | |
3144 | break; | |
3145 | case DFC: | |
3146 | tmpreg = 0x001; | |
3147 | break; | |
3148 | case CACR: | |
3149 | tmpreg = 0x002; | |
3150 | break; | |
3151 | case TC: | |
a8e24a56 | 3152 | case ASID: |
252b5132 RH |
3153 | tmpreg = 0x003; |
3154 | break; | |
3e602632 | 3155 | case ACR0: |
252b5132 RH |
3156 | case ITT0: |
3157 | tmpreg = 0x004; | |
3158 | break; | |
3e602632 | 3159 | case ACR1: |
252b5132 RH |
3160 | case ITT1: |
3161 | tmpreg = 0x005; | |
3162 | break; | |
3e602632 | 3163 | case ACR2: |
252b5132 RH |
3164 | case DTT0: |
3165 | tmpreg = 0x006; | |
3166 | break; | |
3e602632 | 3167 | case ACR3: |
252b5132 RH |
3168 | case DTT1: |
3169 | tmpreg = 0x007; | |
3170 | break; | |
3171 | case BUSCR: | |
a8e24a56 | 3172 | case MMUBAR: |
252b5132 RH |
3173 | tmpreg = 0x008; |
3174 | break; | |
3175 | ||
3176 | case USP: | |
3177 | tmpreg = 0x800; | |
3178 | break; | |
3179 | case VBR: | |
3180 | tmpreg = 0x801; | |
3181 | break; | |
3182 | case CAAR: | |
3183 | tmpreg = 0x802; | |
3184 | break; | |
3185 | case MSP: | |
3186 | tmpreg = 0x803; | |
3187 | break; | |
3188 | case ISP: | |
3189 | tmpreg = 0x804; | |
3190 | break; | |
3191 | case MMUSR: | |
3192 | tmpreg = 0x805; | |
3193 | break; | |
3194 | case URP: | |
3195 | tmpreg = 0x806; | |
3196 | break; | |
3197 | case SRP: | |
3198 | tmpreg = 0x807; | |
3199 | break; | |
3200 | case PCR: | |
3201 | tmpreg = 0x808; | |
3202 | break; | |
3203 | case ROMBAR: | |
a8e24a56 | 3204 | case ROMBAR0: |
252b5132 RH |
3205 | tmpreg = 0xC00; |
3206 | break; | |
3e602632 NC |
3207 | case ROMBAR1: |
3208 | tmpreg = 0xC01; | |
3209 | break; | |
3210 | case FLASHBAR: | |
252b5132 | 3211 | case RAMBAR0: |
78336706 | 3212 | case RAMBAR_ALT: |
252b5132 RH |
3213 | tmpreg = 0xC04; |
3214 | break; | |
3e602632 | 3215 | case RAMBAR: |
252b5132 RH |
3216 | case RAMBAR1: |
3217 | tmpreg = 0xC05; | |
3218 | break; | |
3e602632 NC |
3219 | case MPCR: |
3220 | tmpreg = 0xC0C; | |
3221 | break; | |
3222 | case EDRAMBAR: | |
3223 | tmpreg = 0xC0D; | |
3224 | break; | |
3225 | case MBAR0: | |
e80e0390 | 3226 | case MBAR2: |
3e602632 NC |
3227 | case SECMBAR: |
3228 | tmpreg = 0xC0E; | |
3229 | break; | |
3230 | case MBAR1: | |
252b5132 RH |
3231 | case MBAR: |
3232 | tmpreg = 0xC0F; | |
3233 | break; | |
3e602632 NC |
3234 | case PCR1U0: |
3235 | tmpreg = 0xD02; | |
3236 | break; | |
3237 | case PCR1L0: | |
3238 | tmpreg = 0xD03; | |
3239 | break; | |
3240 | case PCR2U0: | |
3241 | tmpreg = 0xD04; | |
3242 | break; | |
3243 | case PCR2L0: | |
3244 | tmpreg = 0xD05; | |
3245 | break; | |
3246 | case PCR3U0: | |
3247 | tmpreg = 0xD06; | |
3248 | break; | |
3249 | case PCR3L0: | |
3250 | tmpreg = 0xD07; | |
3251 | break; | |
3252 | case PCR1L1: | |
3253 | tmpreg = 0xD0A; | |
3254 | break; | |
3255 | case PCR1U1: | |
3256 | tmpreg = 0xD0B; | |
3257 | break; | |
3258 | case PCR2L1: | |
3259 | tmpreg = 0xD0C; | |
3260 | break; | |
3261 | case PCR2U1: | |
3262 | tmpreg = 0xD0D; | |
3263 | break; | |
3264 | case PCR3L1: | |
3265 | tmpreg = 0xD0E; | |
3266 | break; | |
3267 | case PCR3U1: | |
3268 | tmpreg = 0xD0F; | |
3269 | break; | |
f7ec513b KH |
3270 | case CAC: |
3271 | tmpreg = 0xFFE; | |
3272 | break; | |
d0fa1372 | 3273 | case MBO: |
f7ec513b KH |
3274 | tmpreg = 0xFFF; |
3275 | break; | |
252b5132 RH |
3276 | default: |
3277 | abort (); | |
3278 | } | |
3279 | install_operand (s[1], tmpreg); | |
3280 | break; | |
3281 | ||
3282 | case 'k': | |
3283 | tmpreg = get_num (&opP->disp, 55); | |
3284 | install_operand (s[1], tmpreg & 0x7f); | |
3285 | break; | |
3286 | ||
3287 | case 'l': | |
3288 | tmpreg = opP->mask; | |
3289 | if (s[1] == 'w') | |
3290 | { | |
3291 | if (tmpreg & 0x7FF0000) | |
3292 | as_bad (_("Floating point register in register list")); | |
3293 | insop (reverse_16_bits (tmpreg), opcode); | |
3294 | } | |
3295 | else | |
3296 | { | |
3297 | if (tmpreg & 0x700FFFF) | |
3298 | as_bad (_("Wrong register in floating-point reglist")); | |
3299 | install_operand (s[1], reverse_8_bits (tmpreg >> 16)); | |
3300 | } | |
3301 | break; | |
3302 | ||
3303 | case 'L': | |
3304 | tmpreg = opP->mask; | |
3305 | if (s[1] == 'w') | |
3306 | { | |
3307 | if (tmpreg & 0x7FF0000) | |
3308 | as_bad (_("Floating point register in register list")); | |
3309 | insop (tmpreg, opcode); | |
3310 | } | |
3311 | else if (s[1] == '8') | |
3312 | { | |
3313 | if (tmpreg & 0x0FFFFFF) | |
3314 | as_bad (_("incorrect register in reglist")); | |
3315 | install_operand (s[1], tmpreg >> 24); | |
3316 | } | |
3317 | else | |
3318 | { | |
3319 | if (tmpreg & 0x700FFFF) | |
3320 | as_bad (_("wrong register in floating-point reglist")); | |
3321 | else | |
3322 | install_operand (s[1], tmpreg >> 16); | |
3323 | } | |
3324 | break; | |
3325 | ||
3326 | case 'M': | |
3327 | install_operand (s[1], get_num (&opP->disp, 60)); | |
3328 | break; | |
3329 | ||
3330 | case 'O': | |
3331 | tmpreg = ((opP->mode == DREG) | |
8fce3f5e | 3332 | ? 0x20 + (int) (opP->reg - DATA) |
252b5132 RH |
3333 | : (get_num (&opP->disp, 40) & 0x1F)); |
3334 | install_operand (s[1], tmpreg); | |
3335 | break; | |
3336 | ||
3337 | case 'Q': | |
3338 | tmpreg = get_num (&opP->disp, 10); | |
3339 | if (tmpreg == 8) | |
3340 | tmpreg = 0; | |
3341 | install_operand (s[1], tmpreg); | |
3342 | break; | |
3343 | ||
3344 | case 'R': | |
3345 | /* This depends on the fact that ADDR registers are eight | |
3346 | more than their corresponding DATA regs, so the result | |
36759679 | 3347 | will have the ADDR_REG bit set. */ |
252b5132 RH |
3348 | install_operand (s[1], opP->reg - DATA); |
3349 | break; | |
3350 | ||
3351 | case 'r': | |
3352 | if (opP->mode == AINDR) | |
3353 | install_operand (s[1], opP->reg - DATA); | |
3354 | else | |
3355 | install_operand (s[1], opP->index.reg - DATA); | |
3356 | break; | |
3357 | ||
3358 | case 's': | |
3359 | if (opP->reg == FPI) | |
3360 | tmpreg = 0x1; | |
3361 | else if (opP->reg == FPS) | |
3362 | tmpreg = 0x2; | |
3363 | else if (opP->reg == FPC) | |
3364 | tmpreg = 0x4; | |
3365 | else | |
3366 | abort (); | |
3367 | install_operand (s[1], tmpreg); | |
3368 | break; | |
3369 | ||
36759679 | 3370 | case 'S': /* Ignore it. */ |
252b5132 RH |
3371 | break; |
3372 | ||
3373 | case 'T': | |
3374 | install_operand (s[1], get_num (&opP->disp, 30)); | |
3375 | break; | |
3376 | ||
36759679 | 3377 | case 'U': /* Ignore it. */ |
252b5132 RH |
3378 | break; |
3379 | ||
3380 | case 'c': | |
3381 | switch (opP->reg) | |
3382 | { | |
3383 | case NC: | |
3384 | tmpreg = 0; | |
3385 | break; | |
3386 | case DC: | |
3387 | tmpreg = 1; | |
3388 | break; | |
3389 | case IC: | |
3390 | tmpreg = 2; | |
3391 | break; | |
3392 | case BC: | |
3393 | tmpreg = 3; | |
3394 | break; | |
3395 | default: | |
3396 | as_fatal (_("failed sanity check")); | |
36759679 | 3397 | } /* switch on cache token. */ |
252b5132 RH |
3398 | install_operand (s[1], tmpreg); |
3399 | break; | |
3400 | #ifndef NO_68851 | |
92774660 | 3401 | /* JF: These are out of order, I fear. */ |
252b5132 RH |
3402 | case 'f': |
3403 | switch (opP->reg) | |
3404 | { | |
3405 | case SFC: | |
3406 | tmpreg = 0; | |
3407 | break; | |
3408 | case DFC: | |
3409 | tmpreg = 1; | |
3410 | break; | |
3411 | default: | |
3412 | abort (); | |
3413 | } | |
3414 | install_operand (s[1], tmpreg); | |
3415 | break; | |
3416 | ||
3417 | case '0': | |
3418 | case '1': | |
3419 | case '2': | |
3420 | switch (opP->reg) | |
3421 | { | |
3422 | case TC: | |
3423 | tmpreg = 0; | |
3424 | break; | |
3425 | case CAL: | |
3426 | tmpreg = 4; | |
3427 | break; | |
3428 | case VAL: | |
3429 | tmpreg = 5; | |
3430 | break; | |
3431 | case SCC: | |
3432 | tmpreg = 6; | |
3433 | break; | |
3434 | case AC: | |
3435 | tmpreg = 7; | |
3436 | break; | |
3437 | default: | |
3438 | abort (); | |
3439 | } | |
3440 | install_operand (s[1], tmpreg); | |
3441 | break; | |
3442 | ||
3443 | case 'V': | |
3444 | if (opP->reg == VAL) | |
3445 | break; | |
3446 | abort (); | |
3447 | ||
3448 | case 'W': | |
3449 | switch (opP->reg) | |
3450 | { | |
3451 | case DRP: | |
3452 | tmpreg = 1; | |
3453 | break; | |
3454 | case SRP: | |
3455 | tmpreg = 2; | |
3456 | break; | |
3457 | case CRP: | |
3458 | tmpreg = 3; | |
3459 | break; | |
3460 | default: | |
3461 | abort (); | |
3462 | } | |
3463 | install_operand (s[1], tmpreg); | |
3464 | break; | |
3465 | ||
3466 | case 'X': | |
3467 | switch (opP->reg) | |
3468 | { | |
3469 | case BAD: | |
3470 | case BAD + 1: | |
3471 | case BAD + 2: | |
3472 | case BAD + 3: | |
3473 | case BAD + 4: | |
3474 | case BAD + 5: | |
3475 | case BAD + 6: | |
3476 | case BAD + 7: | |
3477 | tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); | |
3478 | break; | |
3479 | ||
3480 | case BAC: | |
3481 | case BAC + 1: | |
3482 | case BAC + 2: | |
3483 | case BAC + 3: | |
3484 | case BAC + 4: | |
3485 | case BAC + 5: | |
3486 | case BAC + 6: | |
3487 | case BAC + 7: | |
3488 | tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); | |
3489 | break; | |
3490 | ||
3491 | default: | |
3492 | abort (); | |
3493 | } | |
3494 | install_operand (s[1], tmpreg); | |
3495 | break; | |
3496 | case 'Y': | |
3497 | know (opP->reg == PSR); | |
3498 | break; | |
3499 | case 'Z': | |
3500 | know (opP->reg == PCSR); | |
3501 | break; | |
3502 | #endif /* m68851 */ | |
3503 | case '3': | |
3504 | switch (opP->reg) | |
3505 | { | |
3506 | case TT0: | |
3507 | tmpreg = 2; | |
3508 | break; | |
3509 | case TT1: | |
3510 | tmpreg = 3; | |
3511 | break; | |
3512 | default: | |
3513 | abort (); | |
3514 | } | |
3515 | install_operand (s[1], tmpreg); | |
3516 | break; | |
3517 | case 't': | |
3518 | tmpreg = get_num (&opP->disp, 20); | |
3519 | install_operand (s[1], tmpreg); | |
3520 | break; | |
36759679 | 3521 | case '_': /* used only for move16 absolute 32-bit address. */ |
252b5132 RH |
3522 | if (isvar (&opP->disp)) |
3523 | add_fix ('l', &opP->disp, 0, 0); | |
3e602632 | 3524 | tmpreg = get_num (&opP->disp, 90); |
252b5132 RH |
3525 | addword (tmpreg >> 16); |
3526 | addword (tmpreg & 0xFFFF); | |
3527 | break; | |
6da466c7 ILT |
3528 | case 'u': |
3529 | install_operand (s[1], opP->reg - DATA0L); | |
3530 | opP->reg -= (DATA0L); | |
36759679 | 3531 | opP->reg &= 0x0F; /* remove upper/lower bit. */ |
6da466c7 | 3532 | break; |
3e602632 NC |
3533 | case 'x': |
3534 | tmpreg = get_num (&opP->disp, 80); | |
3535 | if (tmpreg == -1) | |
3536 | tmpreg = 0; | |
3537 | install_operand (s[1], tmpreg); | |
3538 | break; | |
afa2158f NS |
3539 | case 'j': |
3540 | tmpreg = get_num (&opP->disp, 10); | |
3541 | install_operand (s[1], tmpreg - 1); | |
3542 | break; | |
3543 | case 'K': | |
3544 | tmpreg = get_num (&opP->disp, 65); | |
3545 | install_operand (s[1], tmpreg); | |
3546 | break; | |
252b5132 RH |
3547 | default: |
3548 | abort (); | |
3549 | } | |
3550 | } | |
3551 | ||
3552 | /* By the time whe get here (FINALLY) the_ins contains the complete | |
92774660 | 3553 | instruction, ready to be emitted. . . */ |
252b5132 RH |
3554 | } |
3555 | ||
3556 | static int | |
31302357 | 3557 | reverse_16_bits (int in) |
252b5132 RH |
3558 | { |
3559 | int out = 0; | |
3560 | int n; | |
3561 | ||
3562 | static int mask[16] = | |
3563 | { | |
3564 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3565 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 | |
3566 | }; | |
3567 | for (n = 0; n < 16; n++) | |
3568 | { | |
3569 | if (in & mask[n]) | |
3570 | out |= mask[15 - n]; | |
3571 | } | |
3572 | return out; | |
3573 | } /* reverse_16_bits() */ | |
3574 | ||
3575 | static int | |
31302357 | 3576 | reverse_8_bits (int in) |
252b5132 RH |
3577 | { |
3578 | int out = 0; | |
3579 | int n; | |
3580 | ||
3581 | static int mask[8] = | |
3582 | { | |
3583 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
3584 | }; | |
3585 | ||
3586 | for (n = 0; n < 8; n++) | |
3587 | { | |
3588 | if (in & mask[n]) | |
3589 | out |= mask[7 - n]; | |
3590 | } | |
3591 | return out; | |
3592 | } /* reverse_8_bits() */ | |
3593 | ||
cac27205 NC |
3594 | /* Cause an extra frag to be generated here, inserting up to |
3595 | FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be | |
3596 | generated; its primary type is rs_machine_dependent. | |
252b5132 RH |
3597 | |
3598 | The TYPE parameter is also used by md_convert_frag_1 and | |
3599 | md_estimate_size_before_relax. The appropriate type of fixup will | |
3600 | be emitted by md_convert_frag_1. | |
3601 | ||
3602 | ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ | |
3603 | static void | |
31302357 | 3604 | install_operand (int mode, int val) |
252b5132 RH |
3605 | { |
3606 | switch (mode) | |
3607 | { | |
3608 | case 's': | |
36759679 | 3609 | the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ |
252b5132 RH |
3610 | break; |
3611 | case 'd': | |
3612 | the_ins.opcode[0] |= val << 9; | |
3613 | break; | |
afa2158f NS |
3614 | case 'E': |
3615 | the_ins.opcode[1] |= val << 9; | |
3616 | break; | |
252b5132 RH |
3617 | case '1': |
3618 | the_ins.opcode[1] |= val << 12; | |
3619 | break; | |
3620 | case '2': | |
3621 | the_ins.opcode[1] |= val << 6; | |
3622 | break; | |
3623 | case '3': | |
3624 | the_ins.opcode[1] |= val; | |
3625 | break; | |
3626 | case '4': | |
3627 | the_ins.opcode[2] |= val << 12; | |
3628 | break; | |
3629 | case '5': | |
3630 | the_ins.opcode[2] |= val << 6; | |
3631 | break; | |
3632 | case '6': | |
3633 | /* DANGER! This is a hack to force cas2l and cas2w cmds to be | |
3634 | three words long! */ | |
3635 | the_ins.numo++; | |
3636 | the_ins.opcode[2] |= val; | |
3637 | break; | |
3638 | case '7': | |
3639 | the_ins.opcode[1] |= val << 7; | |
3640 | break; | |
3641 | case '8': | |
3642 | the_ins.opcode[1] |= val << 10; | |
3643 | break; | |
3644 | #ifndef NO_68851 | |
3645 | case '9': | |
3646 | the_ins.opcode[1] |= val << 5; | |
3647 | break; | |
3648 | #endif | |
3649 | ||
3650 | case 't': | |
3651 | the_ins.opcode[1] |= (val << 10) | (val << 7); | |
3652 | break; | |
3653 | case 'D': | |
3654 | the_ins.opcode[1] |= (val << 12) | val; | |
3655 | break; | |
3656 | case 'g': | |
3657 | the_ins.opcode[0] |= val = 0xff; | |
3658 | break; | |
3659 | case 'i': | |
3660 | the_ins.opcode[0] |= val << 9; | |
3661 | break; | |
3662 | case 'C': | |
3663 | the_ins.opcode[1] |= val; | |
3664 | break; | |
3665 | case 'j': | |
3666 | the_ins.opcode[1] |= val; | |
36759679 | 3667 | the_ins.numo++; /* What a hack. */ |
252b5132 RH |
3668 | break; |
3669 | case 'k': | |
3670 | the_ins.opcode[1] |= val << 4; | |
3671 | break; | |
3672 | case 'b': | |
3673 | case 'w': | |
3674 | case 'W': | |
3675 | case 'l': | |
3676 | break; | |
3677 | case 'e': | |
3678 | the_ins.opcode[0] |= (val << 6); | |
3679 | break; | |
3680 | case 'L': | |
3681 | the_ins.opcode[1] = (val >> 16); | |
3682 | the_ins.opcode[2] = val & 0xffff; | |
3683 | break; | |
6da466c7 ILT |
3684 | case 'm': |
3685 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); | |
3686 | the_ins.opcode[0] |= ((val & 0x7) << 9); | |
3687 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); | |
3688 | break; | |
fd99574b | 3689 | case 'n': /* MAC/EMAC Rx on !load. */ |
6da466c7 ILT |
3690 | the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); |
3691 | the_ins.opcode[0] |= ((val & 0x7) << 9); | |
fd99574b | 3692 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); |
6da466c7 | 3693 | break; |
fd99574b | 3694 | case 'o': /* MAC/EMAC Rx on load. */ |
6da466c7 ILT |
3695 | the_ins.opcode[1] |= val << 12; |
3696 | the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); | |
3697 | break; | |
fd99574b | 3698 | case 'M': /* MAC/EMAC Ry on !load. */ |
6da466c7 ILT |
3699 | the_ins.opcode[0] |= (val & 0xF); |
3700 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); | |
3701 | break; | |
fd99574b | 3702 | case 'N': /* MAC/EMAC Ry on load. */ |
6da466c7 ILT |
3703 | the_ins.opcode[1] |= (val & 0xF); |
3704 | the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); | |
3705 | break; | |
3706 | case 'h': | |
3707 | the_ins.opcode[1] |= ((val != 1) << 10); | |
3708 | break; | |
fd99574b NC |
3709 | case 'F': |
3710 | the_ins.opcode[0] |= ((val & 0x3) << 9); | |
3711 | break; | |
3712 | case 'f': | |
3713 | the_ins.opcode[0] |= ((val & 0x3) << 0); | |
3714 | break; | |
be8c092b | 3715 | case 'G': /* EMAC accumulator in a EMAC load instruction. */ |
fd99574b NC |
3716 | the_ins.opcode[0] |= ((~val & 0x1) << 7); |
3717 | the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); | |
3718 | break; | |
be8c092b | 3719 | case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ |
fd99574b NC |
3720 | the_ins.opcode[0] |= ((val & 0x1) << 7); |
3721 | the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); | |
3722 | break; | |
3723 | case 'I': | |
3724 | the_ins.opcode[1] |= ((val & 0x3) << 9); | |
3725 | break; | |
3726 | case ']': | |
3727 | the_ins.opcode[0] |= (val & 0x1) <<10; | |
3728 | break; | |
252b5132 RH |
3729 | case 'c': |
3730 | default: | |
3731 | as_fatal (_("failed sanity check.")); | |
3732 | } | |
6b6e92f4 | 3733 | } |
252b5132 RH |
3734 | |
3735 | static void | |
31302357 | 3736 | install_gen_operand (int mode, int val) |
252b5132 RH |
3737 | { |
3738 | switch (mode) | |
3739 | { | |
fd99574b NC |
3740 | case '/': /* Special for mask loads for mac/msac insns with |
3741 | possible mask; trailing_ampersend set in bit 8. */ | |
3742 | the_ins.opcode[0] |= (val & 0x3f); | |
3743 | the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); | |
3744 | break; | |
252b5132 RH |
3745 | case 's': |
3746 | the_ins.opcode[0] |= val; | |
3747 | break; | |
3748 | case 'd': | |
3749 | /* This is a kludge!!! */ | |
3750 | the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; | |
3751 | break; | |
3752 | case 'b': | |
3753 | case 'w': | |
3754 | case 'l': | |
3755 | case 'f': | |
3756 | case 'F': | |
3757 | case 'x': | |
3758 | case 'p': | |
3759 | the_ins.opcode[0] |= val; | |
3760 | break; | |
36759679 | 3761 | /* more stuff goes here. */ |
252b5132 RH |
3762 | default: |
3763 | as_fatal (_("failed sanity check.")); | |
3764 | } | |
6b6e92f4 | 3765 | } |
252b5132 | 3766 | |
6b6e92f4 NC |
3767 | /* Verify that we have some number of paren pairs, do m68k_ip_op(), and |
3768 | then deal with the bitfield hack. */ | |
252b5132 RH |
3769 | |
3770 | static char * | |
31302357 | 3771 | crack_operand (char *str, struct m68k_op *opP) |
252b5132 RH |
3772 | { |
3773 | register int parens; | |
3774 | register int c; | |
3775 | register char *beg_str; | |
3776 | int inquote = 0; | |
3777 | ||
3778 | if (!str) | |
3779 | { | |
3780 | return str; | |
3781 | } | |
3782 | beg_str = str; | |
3783 | for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) | |
3784 | { | |
3785 | if (! inquote) | |
3786 | { | |
3787 | if (*str == '(') | |
3788 | parens++; | |
3789 | else if (*str == ')') | |
3790 | { | |
3791 | if (!parens) | |
36759679 | 3792 | { /* ERROR. */ |
252b5132 RH |
3793 | opP->error = _("Extra )"); |
3794 | return str; | |
3795 | } | |
3796 | --parens; | |
3797 | } | |
3798 | } | |
3799 | if (flag_mri && *str == '\'') | |
3800 | inquote = ! inquote; | |
3801 | } | |
3802 | if (!*str && parens) | |
36759679 | 3803 | { /* ERROR. */ |
252b5132 RH |
3804 | opP->error = _("Missing )"); |
3805 | return str; | |
3806 | } | |
3807 | c = *str; | |
3808 | *str = '\0'; | |
3809 | if (m68k_ip_op (beg_str, opP) != 0) | |
3810 | { | |
3811 | *str = c; | |
3812 | return str; | |
3813 | } | |
3814 | *str = c; | |
3815 | if (c == '}') | |
36759679 | 3816 | c = *++str; /* JF bitfield hack. */ |
252b5132 RH |
3817 | if (c) |
3818 | { | |
3819 | c = *++str; | |
3820 | if (!c) | |
3821 | as_bad (_("Missing operand")); | |
3822 | } | |
3823 | ||
3824 | /* Detect MRI REG symbols and convert them to REGLSTs. */ | |
3825 | if (opP->mode == CONTROL && (int)opP->reg < 0) | |
3826 | { | |
3827 | opP->mode = REGLST; | |
3828 | opP->mask = ~(int)opP->reg; | |
3829 | opP->reg = 0; | |
3830 | } | |
3831 | ||
3832 | return str; | |
3833 | } | |
3834 | ||
3835 | /* This is the guts of the machine-dependent assembler. STR points to a | |
3836 | machine dependent instruction. This function is supposed to emit | |
3837 | the frags/bytes it assembles to. | |
3838 | */ | |
3839 | ||
3840 | static void | |
31302357 | 3841 | insert_reg (const char *regname, int regnum) |
252b5132 RH |
3842 | { |
3843 | char buf[100]; | |
3844 | int i; | |
3845 | ||
3846 | #ifdef REGISTER_PREFIX | |
3847 | if (!flag_reg_prefix_optional) | |
3848 | { | |
3849 | buf[0] = REGISTER_PREFIX; | |
3850 | strcpy (buf + 1, regname); | |
3851 | regname = buf; | |
3852 | } | |
3853 | #endif | |
3854 | ||
3855 | symbol_table_insert (symbol_new (regname, reg_section, regnum, | |
3856 | &zero_address_frag)); | |
3857 | ||
3858 | for (i = 0; regname[i]; i++) | |
3882b010 | 3859 | buf[i] = TOUPPER (regname[i]); |
252b5132 RH |
3860 | buf[i] = '\0'; |
3861 | ||
3862 | symbol_table_insert (symbol_new (buf, reg_section, regnum, | |
3863 | &zero_address_frag)); | |
3864 | } | |
3865 | ||
3866 | struct init_entry | |
3867 | { | |
3868 | const char *name; | |
3869 | int number; | |
3870 | }; | |
3871 | ||
3872 | static const struct init_entry init_table[] = | |
3873 | { | |
3874 | { "d0", DATA0 }, | |
3875 | { "d1", DATA1 }, | |
3876 | { "d2", DATA2 }, | |
3877 | { "d3", DATA3 }, | |
3878 | { "d4", DATA4 }, | |
3879 | { "d5", DATA5 }, | |
3880 | { "d6", DATA6 }, | |
3881 | { "d7", DATA7 }, | |
3882 | { "a0", ADDR0 }, | |
3883 | { "a1", ADDR1 }, | |
3884 | { "a2", ADDR2 }, | |
3885 | { "a3", ADDR3 }, | |
3886 | { "a4", ADDR4 }, | |
3887 | { "a5", ADDR5 }, | |
3888 | { "a6", ADDR6 }, | |
3889 | { "fp", ADDR6 }, | |
3890 | { "a7", ADDR7 }, | |
3891 | { "sp", ADDR7 }, | |
3892 | { "ssp", ADDR7 }, | |
3893 | { "fp0", FP0 }, | |
3894 | { "fp1", FP1 }, | |
3895 | { "fp2", FP2 }, | |
3896 | { "fp3", FP3 }, | |
3897 | { "fp4", FP4 }, | |
3898 | { "fp5", FP5 }, | |
3899 | { "fp6", FP6 }, | |
3900 | { "fp7", FP7 }, | |
3901 | { "fpi", FPI }, | |
3902 | { "fpiar", FPI }, | |
3903 | { "fpc", FPI }, | |
3904 | { "fps", FPS }, | |
3905 | { "fpsr", FPS }, | |
3906 | { "fpc", FPC }, | |
3907 | { "fpcr", FPC }, | |
3908 | { "control", FPC }, | |
3909 | { "status", FPS }, | |
3910 | { "iaddr", FPI }, | |
3911 | ||
3912 | { "cop0", COP0 }, | |
3913 | { "cop1", COP1 }, | |
3914 | { "cop2", COP2 }, | |
3915 | { "cop3", COP3 }, | |
3916 | { "cop4", COP4 }, | |
3917 | { "cop5", COP5 }, | |
3918 | { "cop6", COP6 }, | |
3919 | { "cop7", COP7 }, | |
3920 | { "pc", PC }, | |
3921 | { "zpc", ZPC }, | |
3922 | { "sr", SR }, | |
3923 | ||
3924 | { "ccr", CCR }, | |
3925 | { "cc", CCR }, | |
3926 | ||
6da466c7 | 3927 | { "acc", ACC }, |
fd99574b NC |
3928 | { "acc0", ACC }, |
3929 | { "acc1", ACC1 }, | |
3930 | { "acc2", ACC2 }, | |
3931 | { "acc3", ACC3 }, | |
3932 | { "accext01", ACCEXT01 }, | |
3933 | { "accext23", ACCEXT23 }, | |
6da466c7 ILT |
3934 | { "macsr", MACSR }, |
3935 | { "mask", MASK }, | |
3936 | ||
36759679 NC |
3937 | /* Control registers. */ |
3938 | { "sfc", SFC }, /* Source Function Code. */ | |
252b5132 | 3939 | { "sfcr", SFC }, |
36759679 | 3940 | { "dfc", DFC }, /* Destination Function Code. */ |
252b5132 | 3941 | { "dfcr", DFC }, |
36759679 NC |
3942 | { "cacr", CACR }, /* Cache Control Register. */ |
3943 | { "caar", CAAR }, /* Cache Address Register. */ | |
252b5132 | 3944 | |
36759679 NC |
3945 | { "usp", USP }, /* User Stack Pointer. */ |
3946 | { "vbr", VBR }, /* Vector Base Register. */ | |
3947 | { "msp", MSP }, /* Master Stack Pointer. */ | |
3948 | { "isp", ISP }, /* Interrupt Stack Pointer. */ | |
252b5132 | 3949 | |
36759679 NC |
3950 | { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ |
3951 | { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ | |
3952 | { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ | |
3953 | { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ | |
252b5132 RH |
3954 | |
3955 | /* 68ec040 versions of same */ | |
36759679 NC |
3956 | { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ |
3957 | { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ | |
3958 | { "dacr0", DTT0 }, /* Data Access Control Register 0. */ | |
3959 | { "dacr1", DTT1 }, /* Data Access Control Register 0. */ | |
252b5132 | 3960 | |
a8e24a56 | 3961 | /* Coldfire versions of same. The ColdFire programmer's reference |
252b5132 RH |
3962 | manual indicated that the order is 2,3,0,1, but Ken Rose |
3963 | <rose@netcom.com> says that 0,1,2,3 is the correct order. */ | |
3e602632 NC |
3964 | { "acr0", ACR0 }, /* Access Control Unit 0. */ |
3965 | { "acr1", ACR1 }, /* Access Control Unit 1. */ | |
3966 | { "acr2", ACR2 }, /* Access Control Unit 2. */ | |
3967 | { "acr3", ACR3 }, /* Access Control Unit 3. */ | |
252b5132 | 3968 | |
36759679 | 3969 | { "tc", TC }, /* MMU Translation Control Register. */ |
252b5132 | 3970 | { "tcr", TC }, |
a8e24a56 | 3971 | { "asid", ASID }, |
252b5132 | 3972 | |
36759679 NC |
3973 | { "mmusr", MMUSR }, /* MMU Status Register. */ |
3974 | { "srp", SRP }, /* User Root Pointer. */ | |
3975 | { "urp", URP }, /* Supervisor Root Pointer. */ | |
252b5132 RH |
3976 | |
3977 | { "buscr", BUSCR }, | |
a8e24a56 | 3978 | { "mmubar", MMUBAR }, |
252b5132 RH |
3979 | { "pcr", PCR }, |
3980 | ||
36759679 NC |
3981 | { "rombar", ROMBAR }, /* ROM Base Address Register. */ |
3982 | { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ | |
3983 | { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ | |
3984 | { "mbar", MBAR }, /* Module Base Address Register. */ | |
3e602632 NC |
3985 | |
3986 | { "mbar0", MBAR0 }, /* mcfv4e registers. */ | |
3987 | { "mbar1", MBAR1 }, /* mcfv4e registers. */ | |
a8e24a56 | 3988 | { "rombar0", ROMBAR0 }, /* mcfv4e registers. */ |
3e602632 NC |
3989 | { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ |
3990 | { "mpcr", MPCR }, /* mcfv4e registers. */ | |
3991 | { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ | |
3992 | { "secmbar", SECMBAR }, /* mcfv4e registers. */ | |
3993 | { "asid", TC }, /* mcfv4e registers. */ | |
3994 | { "mmubar", BUSCR }, /* mcfv4e registers. */ | |
3995 | { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ | |
3996 | { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ | |
3997 | { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ | |
3998 | { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ | |
3999 | { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ | |
4000 | { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ | |
4001 | { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ | |
4002 | { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ | |
4003 | { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ | |
4004 | { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ | |
4005 | { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ | |
4006 | { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ | |
4007 | ||
4008 | { "flashbar", FLASHBAR }, /* mcf528x registers. */ | |
4009 | { "rambar", RAMBAR }, /* mcf528x registers. */ | |
e80e0390 NC |
4010 | |
4011 | { "mbar2", MBAR2 }, /* mcf5249 registers. */ | |
f7ec513b KH |
4012 | |
4013 | { "cac", CAC }, /* fido registers. */ | |
d0fa1372 KH |
4014 | { "mbb", MBO }, /* fido registers (obsolete). */ |
4015 | { "mbo", MBO }, /* fido registers. */ | |
36759679 | 4016 | /* End of control registers. */ |
252b5132 RH |
4017 | |
4018 | { "ac", AC }, | |
4019 | { "bc", BC }, | |
4020 | { "cal", CAL }, | |
4021 | { "crp", CRP }, | |
4022 | { "drp", DRP }, | |
4023 | { "pcsr", PCSR }, | |
4024 | { "psr", PSR }, | |
4025 | { "scc", SCC }, | |
4026 | { "val", VAL }, | |
4027 | { "bad0", BAD0 }, | |
4028 | { "bad1", BAD1 }, | |
4029 | { "bad2", BAD2 }, | |
4030 | { "bad3", BAD3 }, | |
4031 | { "bad4", BAD4 }, | |
4032 | { "bad5", BAD5 }, | |
4033 | { "bad6", BAD6 }, | |
4034 | { "bad7", BAD7 }, | |
4035 | { "bac0", BAC0 }, | |
4036 | { "bac1", BAC1 }, | |
4037 | { "bac2", BAC2 }, | |
4038 | { "bac3", BAC3 }, | |
4039 | { "bac4", BAC4 }, | |
4040 | { "bac5", BAC5 }, | |
4041 | { "bac6", BAC6 }, | |
4042 | { "bac7", BAC7 }, | |
4043 | ||
4044 | { "ic", IC }, | |
4045 | { "dc", DC }, | |
4046 | { "nc", NC }, | |
4047 | ||
4048 | { "tt0", TT0 }, | |
4049 | { "tt1", TT1 }, | |
36759679 | 4050 | /* 68ec030 versions of same. */ |
252b5132 RH |
4051 | { "ac0", TT0 }, |
4052 | { "ac1", TT1 }, | |
36759679 | 4053 | /* 68ec030 access control unit, identical to 030 MMU status reg. */ |
252b5132 RH |
4054 | { "acusr", PSR }, |
4055 | ||
4056 | /* Suppressed data and address registers. */ | |
4057 | { "zd0", ZDATA0 }, | |
4058 | { "zd1", ZDATA1 }, | |
4059 | { "zd2", ZDATA2 }, | |
4060 | { "zd3", ZDATA3 }, | |
4061 | { "zd4", ZDATA4 }, | |
4062 | { "zd5", ZDATA5 }, | |
4063 | { "zd6", ZDATA6 }, | |
4064 | { "zd7", ZDATA7 }, | |
4065 | { "za0", ZADDR0 }, | |
4066 | { "za1", ZADDR1 }, | |
4067 | { "za2", ZADDR2 }, | |
4068 | { "za3", ZADDR3 }, | |
4069 | { "za4", ZADDR4 }, | |
4070 | { "za5", ZADDR5 }, | |
4071 | { "za6", ZADDR6 }, | |
4072 | { "za7", ZADDR7 }, | |
4073 | ||
92774660 | 4074 | /* Upper and lower data and address registers, used by macw and msacw. */ |
6da466c7 ILT |
4075 | { "d0l", DATA0L }, |
4076 | { "d1l", DATA1L }, | |
4077 | { "d2l", DATA2L }, | |
4078 | { "d3l", DATA3L }, | |
4079 | { "d4l", DATA4L }, | |
4080 | { "d5l", DATA5L }, | |
4081 | { "d6l", DATA6L }, | |
4082 | { "d7l", DATA7L }, | |
4083 | ||
4084 | { "a0l", ADDR0L }, | |
4085 | { "a1l", ADDR1L }, | |
4086 | { "a2l", ADDR2L }, | |
4087 | { "a3l", ADDR3L }, | |
4088 | { "a4l", ADDR4L }, | |
4089 | { "a5l", ADDR5L }, | |
4090 | { "a6l", ADDR6L }, | |
4091 | { "a7l", ADDR7L }, | |
4092 | ||
4093 | { "d0u", DATA0U }, | |
4094 | { "d1u", DATA1U }, | |
4095 | { "d2u", DATA2U }, | |
4096 | { "d3u", DATA3U }, | |
4097 | { "d4u", DATA4U }, | |
4098 | { "d5u", DATA5U }, | |
4099 | { "d6u", DATA6U }, | |
4100 | { "d7u", DATA7U }, | |
4101 | ||
4102 | { "a0u", ADDR0U }, | |
4103 | { "a1u", ADDR1U }, | |
4104 | { "a2u", ADDR2U }, | |
4105 | { "a3u", ADDR3U }, | |
4106 | { "a4u", ADDR4U }, | |
4107 | { "a5u", ADDR5U }, | |
4108 | { "a6u", ADDR6U }, | |
4109 | { "a7u", ADDR7U }, | |
4110 | ||
252b5132 RH |
4111 | { 0, 0 } |
4112 | }; | |
4113 | ||
4114 | static void | |
31302357 | 4115 | init_regtable (void) |
252b5132 RH |
4116 | { |
4117 | int i; | |
4118 | for (i = 0; init_table[i].name; i++) | |
4119 | insert_reg (init_table[i].name, init_table[i].number); | |
4120 | } | |
4121 | ||
252b5132 | 4122 | void |
31302357 | 4123 | md_assemble (char *str) |
252b5132 RH |
4124 | { |
4125 | const char *er; | |
4126 | short *fromP; | |
4127 | char *toP = NULL; | |
4128 | int m, n = 0; | |
4129 | char *to_beg_P; | |
4130 | int shorts_this_frag; | |
4131 | fixS *fixP; | |
4132 | ||
266abb8f NS |
4133 | if (!selected_cpu && !selected_arch) |
4134 | { | |
4135 | /* We've not selected an architecture yet. Set the default | |
4136 | now. We do this lazily so that an initial .cpu or .arch directive | |
4137 | can specify. */ | |
4138 | if (!m68k_set_cpu (TARGET_CPU, 1, 1)) | |
4139 | as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU); | |
4140 | } | |
4141 | if (!initialized) | |
4142 | m68k_init_arch (); | |
4143 | ||
252b5132 RH |
4144 | /* In MRI mode, the instruction and operands are separated by a |
4145 | space. Anything following the operands is a comment. The label | |
4146 | has already been removed. */ | |
4147 | if (flag_mri) | |
4148 | { | |
4149 | char *s; | |
4150 | int fields = 0; | |
4151 | int infield = 0; | |
4152 | int inquote = 0; | |
4153 | ||
4154 | for (s = str; *s != '\0'; s++) | |
4155 | { | |
4156 | if ((*s == ' ' || *s == '\t') && ! inquote) | |
4157 | { | |
4158 | if (infield) | |
4159 | { | |
4160 | ++fields; | |
4161 | if (fields >= 2) | |
4162 | { | |
4163 | *s = '\0'; | |
4164 | break; | |
4165 | } | |
4166 | infield = 0; | |
4167 | } | |
4168 | } | |
4169 | else | |
4170 | { | |
4171 | if (! infield) | |
4172 | infield = 1; | |
4173 | if (*s == '\'') | |
4174 | inquote = ! inquote; | |
4175 | } | |
4176 | } | |
4177 | } | |
4178 | ||
31302357 | 4179 | memset (&the_ins, '\0', sizeof (the_ins)); |
252b5132 RH |
4180 | m68k_ip (str); |
4181 | er = the_ins.error; | |
4182 | if (!er) | |
4183 | { | |
4184 | for (n = 0; n < the_ins.numargs; n++) | |
4185 | if (the_ins.operands[n].error) | |
4186 | { | |
4187 | er = the_ins.operands[n].error; | |
4188 | break; | |
4189 | } | |
4190 | } | |
4191 | if (er) | |
4192 | { | |
4193 | as_bad (_("%s -- statement `%s' ignored"), er, str); | |
4194 | return; | |
4195 | } | |
4196 | ||
4197 | /* If there is a current label, record that it marks an instruction. */ | |
4198 | if (current_label != NULL) | |
4199 | { | |
4200 | current_label->text = 1; | |
4201 | current_label = NULL; | |
4202 | } | |
4203 | ||
f27a3839 AS |
4204 | #ifdef OBJ_ELF |
4205 | /* Tie dwarf2 debug info to the address at the start of the insn. */ | |
4206 | dwarf2_emit_insn (0); | |
4207 | #endif | |
4208 | ||
252b5132 RH |
4209 | if (the_ins.nfrag == 0) |
4210 | { | |
36759679 | 4211 | /* No frag hacking involved; just put it out. */ |
252b5132 RH |
4212 | toP = frag_more (2 * the_ins.numo); |
4213 | fromP = &the_ins.opcode[0]; | |
4214 | for (m = the_ins.numo; m; --m) | |
4215 | { | |
4216 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4217 | toP += 2; | |
4218 | fromP++; | |
4219 | } | |
36759679 | 4220 | /* Put out symbol-dependent info. */ |
252b5132 RH |
4221 | for (m = 0; m < the_ins.nrel; m++) |
4222 | { | |
4223 | switch (the_ins.reloc[m].wid) | |
4224 | { | |
4225 | case 'B': | |
4226 | n = 1; | |
4227 | break; | |
4228 | case 'b': | |
4229 | n = 1; | |
4230 | break; | |
4231 | case '3': | |
4232 | n = 1; | |
4233 | break; | |
4234 | case 'w': | |
4235 | case 'W': | |
4236 | n = 2; | |
4237 | break; | |
4238 | case 'l': | |
4239 | n = 4; | |
4240 | break; | |
4241 | default: | |
4242 | as_fatal (_("Don't know how to figure width of %c in md_assemble()"), | |
4243 | the_ins.reloc[m].wid); | |
4244 | } | |
4245 | ||
4246 | fixP = fix_new_exp (frag_now, | |
4247 | ((toP - frag_now->fr_literal) | |
4248 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
4249 | n, | |
4250 | &the_ins.reloc[m].exp, | |
4251 | the_ins.reloc[m].pcrel, | |
4252 | get_reloc_code (n, the_ins.reloc[m].pcrel, | |
4253 | the_ins.reloc[m].pic_reloc)); | |
4254 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4255 | if (the_ins.reloc[m].wid == 'B') | |
4256 | fixP->fx_signed = 1; | |
4257 | } | |
4258 | return; | |
4259 | } | |
4260 | ||
36759679 | 4261 | /* There's some frag hacking. */ |
fbe572f9 AM |
4262 | { |
4263 | /* Calculate the max frag size. */ | |
4264 | int wid; | |
4265 | ||
4266 | wid = 2 * the_ins.fragb[0].fragoff; | |
4267 | for (n = 1; n < the_ins.nfrag; n++) | |
4268 | wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4269 | /* frag_var part. */ | |
cac27205 | 4270 | wid += FRAG_VAR_SIZE; |
fbe572f9 AM |
4271 | /* Make sure the whole insn fits in one chunk, in particular that |
4272 | the var part is attached, as we access one byte before the | |
4273 | variable frag for byte branches. */ | |
4274 | frag_grow (wid); | |
4275 | } | |
4276 | ||
252b5132 RH |
4277 | for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) |
4278 | { | |
4279 | int wid; | |
4280 | ||
4281 | if (n == 0) | |
4282 | wid = 2 * the_ins.fragb[n].fragoff; | |
4283 | else | |
4284 | wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4285 | toP = frag_more (wid); | |
4286 | to_beg_P = toP; | |
4287 | shorts_this_frag = 0; | |
4288 | for (m = wid / 2; m; --m) | |
4289 | { | |
4290 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4291 | toP += 2; | |
4292 | fromP++; | |
4293 | shorts_this_frag++; | |
4294 | } | |
4295 | for (m = 0; m < the_ins.nrel; m++) | |
4296 | { | |
4297 | if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) | |
4298 | { | |
4299 | the_ins.reloc[m].n -= 2 * shorts_this_frag; | |
4300 | break; | |
4301 | } | |
4302 | wid = the_ins.reloc[m].wid; | |
4303 | if (wid == 0) | |
4304 | continue; | |
4305 | the_ins.reloc[m].wid = 0; | |
4306 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
4307 | ||
4308 | fixP = fix_new_exp (frag_now, | |
4309 | ((toP - frag_now->fr_literal) | |
4310 | - the_ins.numo * 2 + the_ins.reloc[m].n), | |
4311 | wid, | |
4312 | &the_ins.reloc[m].exp, | |
4313 | the_ins.reloc[m].pcrel, | |
4314 | get_reloc_code (wid, the_ins.reloc[m].pcrel, | |
4315 | the_ins.reloc[m].pic_reloc)); | |
4316 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4317 | } | |
cac27205 | 4318 | (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0, |
252b5132 RH |
4319 | (relax_substateT) (the_ins.fragb[n].fragty), |
4320 | the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); | |
4321 | } | |
4322 | n = (the_ins.numo - the_ins.fragb[n - 1].fragoff); | |
4323 | shorts_this_frag = 0; | |
4324 | if (n) | |
4325 | { | |
055d1eb0 | 4326 | toP = frag_more (n * 2); |
252b5132 RH |
4327 | while (n--) |
4328 | { | |
4329 | md_number_to_chars (toP, (long) (*fromP), 2); | |
4330 | toP += 2; | |
4331 | fromP++; | |
4332 | shorts_this_frag++; | |
4333 | } | |
4334 | } | |
4335 | for (m = 0; m < the_ins.nrel; m++) | |
4336 | { | |
4337 | int wid; | |
4338 | ||
4339 | wid = the_ins.reloc[m].wid; | |
4340 | if (wid == 0) | |
4341 | continue; | |
4342 | the_ins.reloc[m].wid = 0; | |
4343 | wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; | |
4344 | ||
4345 | fixP = fix_new_exp (frag_now, | |
4346 | ((the_ins.reloc[m].n + toP - frag_now->fr_literal) | |
4347 | - shorts_this_frag * 2), | |
4348 | wid, | |
4349 | &the_ins.reloc[m].exp, | |
4350 | the_ins.reloc[m].pcrel, | |
4351 | get_reloc_code (wid, the_ins.reloc[m].pcrel, | |
4352 | the_ins.reloc[m].pic_reloc)); | |
4353 | fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; | |
4354 | } | |
4355 | } | |
4356 | ||
60fed2d3 NC |
4357 | /* Comparison function used by qsort to rank the opcode entries by name. */ |
4358 | ||
4359 | static int | |
4360 | m68k_compare_opcode (const void * v1, const void * v2) | |
4361 | { | |
4362 | struct m68k_opcode * op1, * op2; | |
4363 | int ret; | |
4364 | ||
03b13e59 NC |
4365 | if (v1 == v2) |
4366 | return 0; | |
4367 | ||
60fed2d3 NC |
4368 | op1 = *(struct m68k_opcode **) v1; |
4369 | op2 = *(struct m68k_opcode **) v2; | |
4370 | ||
4371 | /* Compare the two names. If different, return the comparison. | |
4372 | If the same, return the order they are in the opcode table. */ | |
4373 | ret = strcmp (op1->name, op2->name); | |
4374 | if (ret) | |
4375 | return ret; | |
4376 | if (op1 < op2) | |
4377 | return -1; | |
03b13e59 | 4378 | return 1; |
60fed2d3 NC |
4379 | } |
4380 | ||
252b5132 | 4381 | void |
60fed2d3 | 4382 | md_begin (void) |
252b5132 | 4383 | { |
60fed2d3 NC |
4384 | const struct m68k_opcode *ins; |
4385 | struct m68k_incant *hack, *slak; | |
4386 | const char *retval = 0; /* Empty string, or error msg text. */ | |
4387 | int i; | |
4388 | ||
4389 | /* Set up hash tables with 68000 instructions. | |
4390 | similar to what the vax assembler does. */ | |
252b5132 RH |
4391 | /* RMS claims the thing to do is take the m68k-opcode.h table, and make |
4392 | a copy of it at runtime, adding in the information we want but isn't | |
4393 | there. I think it'd be better to have an awk script hack the table | |
4394 | at compile time. Or even just xstr the table and use it as-is. But | |
4395 | my lord ghod hath spoken, so we do it this way. Excuse the ugly var | |
4396 | names. */ | |
4397 | ||
252b5132 RH |
4398 | if (flag_mri) |
4399 | { | |
4400 | flag_reg_prefix_optional = 1; | |
4401 | m68k_abspcadd = 1; | |
4402 | if (! m68k_rel32_from_cmdline) | |
4403 | m68k_rel32 = 0; | |
4404 | } | |
4405 | ||
60fed2d3 NC |
4406 | /* First sort the opcode table into alphabetical order to seperate |
4407 | the order that the assembler wants to see the opcodes from the | |
4408 | order that the disassembler wants to see them. */ | |
4409 | m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes)); | |
4410 | if (!m68k_sorted_opcodes) | |
4411 | as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"), | |
045b540e | 4412 | m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes))); |
60fed2d3 NC |
4413 | |
4414 | for (i = m68k_numopcodes; i--;) | |
4415 | m68k_sorted_opcodes[i] = m68k_opcodes + i; | |
4416 | ||
4417 | qsort (m68k_sorted_opcodes, m68k_numopcodes, | |
4418 | sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); | |
4419 | ||
252b5132 RH |
4420 | op_hash = hash_new (); |
4421 | ||
4422 | obstack_begin (&robyn, 4000); | |
4423 | for (i = 0; i < m68k_numopcodes; i++) | |
4424 | { | |
78aff5a5 | 4425 | hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4426 | do |
4427 | { | |
60fed2d3 NC |
4428 | ins = m68k_sorted_opcodes[i]; |
4429 | ||
afa2158f NS |
4430 | /* We must enter all insns into the table, because .arch and |
4431 | .cpu directives can change things. */ | |
252b5132 | 4432 | slak->m_operands = ins->args; |
252b5132 RH |
4433 | slak->m_arch = ins->arch; |
4434 | slak->m_opcode = ins->opcode; | |
afa2158f NS |
4435 | |
4436 | /* In most cases we can determine the number of opcode words | |
4437 | by checking the second word of the mask. Unfortunately | |
4438 | some instructions have 2 opcode words, but no fixed bits | |
4439 | in the second word. A leading dot in the operands | |
4440 | string also indicates 2 opcodes. */ | |
4441 | if (*slak->m_operands == '.') | |
4442 | { | |
4443 | slak->m_operands++; | |
4444 | slak->m_codenum = 2; | |
4445 | } | |
4446 | else if (ins->match & 0xffffL) | |
4447 | slak->m_codenum = 2; | |
4448 | else | |
4449 | slak->m_codenum = 1; | |
4450 | slak->m_opnum = strlen (slak->m_operands) / 2; | |
4451 | ||
252b5132 | 4452 | if (i + 1 != m68k_numopcodes |
60fed2d3 | 4453 | && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) |
252b5132 | 4454 | { |
60fed2d3 | 4455 | slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4456 | i++; |
4457 | } | |
4458 | else | |
4459 | slak->m_next = 0; | |
4460 | slak = slak->m_next; | |
4461 | } | |
4462 | while (slak); | |
4463 | ||
4464 | retval = hash_insert (op_hash, ins->name, (char *) hack); | |
4465 | if (retval) | |
4466 | as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval); | |
4467 | } | |
4468 | ||
4469 | for (i = 0; i < m68k_numaliases; i++) | |
4470 | { | |
4471 | const char *name = m68k_opcode_aliases[i].primary; | |
4472 | const char *alias = m68k_opcode_aliases[i].alias; | |
5a49b8ac | 4473 | void *val = hash_find (op_hash, name); |
60fed2d3 | 4474 | |
252b5132 RH |
4475 | if (!val) |
4476 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); | |
4477 | retval = hash_insert (op_hash, alias, val); | |
4478 | if (retval) | |
4479 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); | |
4480 | } | |
4481 | ||
4482 | /* In MRI mode, all unsized branches are variable sized. Normally, | |
4483 | they are word sized. */ | |
4484 | if (flag_mri) | |
4485 | { | |
4486 | static struct m68k_opcode_alias mri_aliases[] = | |
4487 | { | |
4488 | { "bhi", "jhi", }, | |
4489 | { "bls", "jls", }, | |
4490 | { "bcc", "jcc", }, | |
4491 | { "bcs", "jcs", }, | |
4492 | { "bne", "jne", }, | |
4493 | { "beq", "jeq", }, | |
4494 | { "bvc", "jvc", }, | |
4495 | { "bvs", "jvs", }, | |
4496 | { "bpl", "jpl", }, | |
4497 | { "bmi", "jmi", }, | |
4498 | { "bge", "jge", }, | |
4499 | { "blt", "jlt", }, | |
4500 | { "bgt", "jgt", }, | |
4501 | { "ble", "jle", }, | |
4502 | { "bra", "jra", }, | |
4503 | { "bsr", "jbsr", }, | |
4504 | }; | |
4505 | ||
8fce3f5e AM |
4506 | for (i = 0; |
4507 | i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); | |
4508 | i++) | |
252b5132 RH |
4509 | { |
4510 | const char *name = mri_aliases[i].primary; | |
4511 | const char *alias = mri_aliases[i].alias; | |
5a49b8ac | 4512 | void *val = hash_find (op_hash, name); |
60fed2d3 | 4513 | |
252b5132 RH |
4514 | if (!val) |
4515 | as_fatal (_("Internal Error: Can't find %s in hash table"), name); | |
4516 | retval = hash_jam (op_hash, alias, val); | |
4517 | if (retval) | |
4518 | as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); | |
4519 | } | |
4520 | } | |
4521 | ||
8fce3f5e | 4522 | for (i = 0; i < (int) sizeof (notend_table); i++) |
252b5132 RH |
4523 | { |
4524 | notend_table[i] = 0; | |
4525 | alt_notend_table[i] = 0; | |
4526 | } | |
60fed2d3 | 4527 | |
252b5132 RH |
4528 | notend_table[','] = 1; |
4529 | notend_table['{'] = 1; | |
4530 | notend_table['}'] = 1; | |
4531 | alt_notend_table['a'] = 1; | |
4532 | alt_notend_table['A'] = 1; | |
4533 | alt_notend_table['d'] = 1; | |
4534 | alt_notend_table['D'] = 1; | |
4535 | alt_notend_table['#'] = 1; | |
4536 | alt_notend_table['&'] = 1; | |
4537 | alt_notend_table['f'] = 1; | |
4538 | alt_notend_table['F'] = 1; | |
4539 | #ifdef REGISTER_PREFIX | |
4540 | alt_notend_table[REGISTER_PREFIX] = 1; | |
4541 | #endif | |
4542 | ||
4543 | /* We need to put '(' in alt_notend_table to handle | |
60fed2d3 | 4544 | cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ |
252b5132 RH |
4545 | alt_notend_table['('] = 1; |
4546 | ||
4547 | /* We need to put '@' in alt_notend_table to handle | |
60fed2d3 | 4548 | cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ |
252b5132 RH |
4549 | alt_notend_table['@'] = 1; |
4550 | ||
4551 | /* We need to put digits in alt_notend_table to handle | |
60fed2d3 | 4552 | bfextu %d0{24:1},%d0 */ |
252b5132 RH |
4553 | alt_notend_table['0'] = 1; |
4554 | alt_notend_table['1'] = 1; | |
4555 | alt_notend_table['2'] = 1; | |
4556 | alt_notend_table['3'] = 1; | |
4557 | alt_notend_table['4'] = 1; | |
4558 | alt_notend_table['5'] = 1; | |
4559 | alt_notend_table['6'] = 1; | |
4560 | alt_notend_table['7'] = 1; | |
4561 | alt_notend_table['8'] = 1; | |
4562 | alt_notend_table['9'] = 1; | |
4563 | ||
4564 | #ifndef MIT_SYNTAX_ONLY | |
4565 | /* Insert pseudo ops, these have to go into the opcode table since | |
36759679 | 4566 | gas expects pseudo ops to start with a dot. */ |
252b5132 RH |
4567 | { |
4568 | int n = 0; | |
60fed2d3 | 4569 | |
252b5132 RH |
4570 | while (mote_pseudo_table[n].poc_name) |
4571 | { | |
60fed2d3 | 4572 | hack = obstack_alloc (&robyn, sizeof (struct m68k_incant)); |
252b5132 RH |
4573 | hash_insert (op_hash, |
4574 | mote_pseudo_table[n].poc_name, (char *) hack); | |
4575 | hack->m_operands = 0; | |
4576 | hack->m_opnum = n; | |
4577 | n++; | |
4578 | } | |
4579 | } | |
4580 | #endif | |
4581 | ||
4582 | init_regtable (); | |
4583 | ||
4584 | #ifdef OBJ_ELF | |
4585 | record_alignment (text_section, 2); | |
4586 | record_alignment (data_section, 2); | |
4587 | record_alignment (bss_section, 2); | |
4588 | #endif | |
4589 | } | |
4590 | ||
252b5132 RH |
4591 | \f |
4592 | /* This is called when a label is defined. */ | |
4593 | ||
4594 | void | |
31302357 | 4595 | m68k_frob_label (symbolS *sym) |
252b5132 RH |
4596 | { |
4597 | struct label_line *n; | |
4598 | ||
4599 | n = (struct label_line *) xmalloc (sizeof *n); | |
4600 | n->next = labels; | |
4601 | n->label = sym; | |
4602 | as_where (&n->file, &n->line); | |
4603 | n->text = 0; | |
4604 | labels = n; | |
4605 | current_label = n; | |
07a53e5c RH |
4606 | |
4607 | #ifdef OBJ_ELF | |
4608 | dwarf2_emit_label (sym); | |
4609 | #endif | |
252b5132 RH |
4610 | } |
4611 | ||
4612 | /* This is called when a value that is not an instruction is emitted. */ | |
4613 | ||
4614 | void | |
31302357 | 4615 | m68k_flush_pending_output (void) |
252b5132 RH |
4616 | { |
4617 | current_label = NULL; | |
4618 | } | |
4619 | ||
4620 | /* This is called at the end of the assembly, when the final value of | |
4621 | the label is known. We warn if this is a text symbol aligned at an | |
4622 | odd location. */ | |
4623 | ||
4624 | void | |
31302357 | 4625 | m68k_frob_symbol (symbolS *sym) |
252b5132 RH |
4626 | { |
4627 | if (S_GET_SEGMENT (sym) == reg_section | |
4628 | && (int) S_GET_VALUE (sym) < 0) | |
4629 | { | |
4630 | S_SET_SEGMENT (sym, absolute_section); | |
4631 | S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); | |
4632 | } | |
4633 | else if ((S_GET_VALUE (sym) & 1) != 0) | |
4634 | { | |
4635 | struct label_line *l; | |
4636 | ||
4637 | for (l = labels; l != NULL; l = l->next) | |
4638 | { | |
4639 | if (l->label == sym) | |
4640 | { | |
4641 | if (l->text) | |
4642 | as_warn_where (l->file, l->line, | |
4643 | _("text label `%s' aligned to odd boundary"), | |
4644 | S_GET_NAME (sym)); | |
4645 | break; | |
4646 | } | |
4647 | } | |
4648 | } | |
4649 | } | |
4650 | \f | |
4651 | /* This is called if we go in or out of MRI mode because of the .mri | |
4652 | pseudo-op. */ | |
4653 | ||
4654 | void | |
31302357 | 4655 | m68k_mri_mode_change (int on) |
252b5132 RH |
4656 | { |
4657 | if (on) | |
4658 | { | |
4659 | if (! flag_reg_prefix_optional) | |
4660 | { | |
4661 | flag_reg_prefix_optional = 1; | |
4662 | #ifdef REGISTER_PREFIX | |
4663 | init_regtable (); | |
4664 | #endif | |
4665 | } | |
4666 | m68k_abspcadd = 1; | |
4667 | if (! m68k_rel32_from_cmdline) | |
4668 | m68k_rel32 = 0; | |
4669 | } | |
4670 | else | |
4671 | { | |
4672 | if (! reg_prefix_optional_seen) | |
4673 | { | |
4674 | #ifdef REGISTER_PREFIX_OPTIONAL | |
4675 | flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; | |
4676 | #else | |
4677 | flag_reg_prefix_optional = 0; | |
4678 | #endif | |
4679 | #ifdef REGISTER_PREFIX | |
4680 | init_regtable (); | |
4681 | #endif | |
4682 | } | |
4683 | m68k_abspcadd = 0; | |
4684 | if (! m68k_rel32_from_cmdline) | |
4685 | m68k_rel32 = 1; | |
4686 | } | |
4687 | } | |
4688 | ||
252b5132 | 4689 | char * |
31302357 | 4690 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 4691 | { |
499ac353 | 4692 | return ieee_md_atof (type, litP, sizeP, TRUE); |
252b5132 RH |
4693 | } |
4694 | ||
4695 | void | |
31302357 | 4696 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
4697 | { |
4698 | number_to_chars_bigendian (buf, val, n); | |
4699 | } | |
4700 | ||
94f592af | 4701 | void |
55cf6793 | 4702 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 4703 | { |
bbe8ef22 | 4704 | offsetT val = *valP; |
252b5132 RH |
4705 | addressT upper_limit; |
4706 | offsetT lower_limit; | |
4707 | ||
4708 | /* This is unnecessary but it convinces the native rs6000 compiler | |
4709 | to generate the code we want. */ | |
4710 | char *buf = fixP->fx_frag->fr_literal; | |
4711 | buf += fixP->fx_where; | |
36759679 | 4712 | /* End ibm compiler workaround. */ |
252b5132 | 4713 | |
bd17c2c3 | 4714 | val = SEXT (val); |
252b5132 | 4715 | |
94f592af NC |
4716 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) |
4717 | fixP->fx_done = 1; | |
4718 | ||
252b5132 RH |
4719 | #ifdef OBJ_ELF |
4720 | if (fixP->fx_addsy) | |
4721 | { | |
4722 | memset (buf, 0, fixP->fx_size); | |
36759679 | 4723 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
4724 | |
4725 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
4726 | && !S_IS_DEFINED (fixP->fx_addsy) | |
4727 | && !S_IS_WEAK (fixP->fx_addsy)) | |
4728 | S_SET_WEAK (fixP->fx_addsy); | |
4729 | return; | |
4730 | } | |
22184a77 | 4731 | #elif defined(OBJ_AOUT) |
1c3f20b4 | 4732 | /* PR gas/3041 Do not fix frags referencing a weak symbol. */ |
22184a77 NC |
4733 | if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy)) |
4734 | { | |
4735 | memset (buf, 0, fixP->fx_size); | |
1c3f20b4 | 4736 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
22184a77 NC |
4737 | return; |
4738 | } | |
252b5132 RH |
4739 | #endif |
4740 | ||
252b5132 RH |
4741 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
4742 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4743 | return; | |
252b5132 RH |
4744 | |
4745 | switch (fixP->fx_size) | |
4746 | { | |
94f592af NC |
4747 | /* The cast to offsetT below are necessary to make code |
4748 | correct for machines where ints are smaller than offsetT. */ | |
252b5132 RH |
4749 | case 1: |
4750 | *buf++ = val; | |
4751 | upper_limit = 0x7f; | |
4752 | lower_limit = - (offsetT) 0x80; | |
4753 | break; | |
4754 | case 2: | |
4755 | *buf++ = (val >> 8); | |
4756 | *buf++ = val; | |
4757 | upper_limit = 0x7fff; | |
4758 | lower_limit = - (offsetT) 0x8000; | |
4759 | break; | |
4760 | case 4: | |
4761 | *buf++ = (val >> 24); | |
4762 | *buf++ = (val >> 16); | |
4763 | *buf++ = (val >> 8); | |
4764 | *buf++ = val; | |
4765 | upper_limit = 0x7fffffff; | |
36759679 | 4766 | lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ |
252b5132 RH |
4767 | break; |
4768 | default: | |
4769 | BAD_CASE (fixP->fx_size); | |
4770 | } | |
4771 | ||
4772 | /* Fix up a negative reloc. */ | |
4773 | if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) | |
4774 | { | |
4775 | fixP->fx_addsy = fixP->fx_subsy; | |
4776 | fixP->fx_subsy = NULL; | |
4777 | fixP->fx_tcbit = 1; | |
4778 | } | |
4779 | ||
4780 | /* For non-pc-relative values, it's conceivable we might get something | |
4781 | like "0xff" for a byte field. So extend the upper part of the range | |
4782 | to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", | |
4783 | so that we can do any range checking at all. */ | |
4784 | if (! fixP->fx_pcrel && ! fixP->fx_signed) | |
4785 | upper_limit = upper_limit * 2 + 1; | |
4786 | ||
4787 | if ((addressT) val > upper_limit | |
4788 | && (val > 0 || val < lower_limit)) | |
2b878742 NS |
4789 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4790 | _("value %ld out of range"), (long)val); | |
252b5132 RH |
4791 | |
4792 | /* A one byte PC-relative reloc means a short branch. We can't use | |
4793 | a short branch with a value of 0 or -1, because those indicate | |
4794 | different opcodes (branches with longer offsets). fixup_segment | |
4795 | in write.c may have clobbered fx_pcrel, so we need to examine the | |
4796 | reloc type. */ | |
4797 | if ((fixP->fx_pcrel | |
7be1c489 | 4798 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
252b5132 RH |
4799 | && fixP->fx_size == 1 |
4800 | && (fixP->fx_addsy == NULL | |
4801 | || S_IS_DEFINED (fixP->fx_addsy)) | |
4802 | && (val == 0 || val == -1)) | |
2b878742 NS |
4803 | as_bad_where (fixP->fx_file, fixP->fx_line, |
4804 | _("invalid byte branch offset")); | |
252b5132 RH |
4805 | } |
4806 | ||
252b5132 RH |
4807 | /* *fragP has been relaxed to its final size, and now needs to have |
4808 | the bytes inside it modified to conform to the new size There is UGLY | |
4809 | MAGIC here. .. | |
4810 | */ | |
4811 | static void | |
31302357 | 4812 | md_convert_frag_1 (fragS *fragP) |
252b5132 RH |
4813 | { |
4814 | long disp; | |
2b878742 | 4815 | fixS *fixP = NULL; |
252b5132 RH |
4816 | |
4817 | /* Address in object code of the displacement. */ | |
4818 | register int object_address = fragP->fr_fix + fragP->fr_address; | |
4819 | ||
4820 | /* Address in gas core of the place to store the displacement. */ | |
4821 | /* This convinces the native rs6000 compiler to generate the code we | |
92774660 | 4822 | want. */ |
252b5132 RH |
4823 | register char *buffer_address = fragP->fr_literal; |
4824 | buffer_address += fragP->fr_fix; | |
36759679 | 4825 | /* End ibm compiler workaround. */ |
252b5132 RH |
4826 | |
4827 | /* The displacement of the address, from current location. */ | |
4828 | disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; | |
4829 | disp = (disp + fragP->fr_offset) - object_address; | |
4830 | ||
252b5132 RH |
4831 | switch (fragP->fr_subtype) |
4832 | { | |
151337e8 NC |
4833 | case TAB (BRANCHBWL, BYTE): |
4834 | case TAB (BRABSJUNC, BYTE): | |
4835 | case TAB (BRABSJCOND, BYTE): | |
4836 | case TAB (BRANCHBW, BYTE): | |
cac27205 | 4837 | case TAB (BRANCHBWPL, BYTE): |
252b5132 RH |
4838 | know (issbyte (disp)); |
4839 | if (disp == 0) | |
b091f402 AM |
4840 | as_bad_where (fragP->fr_file, fragP->fr_line, |
4841 | _("short branch with zero offset: use :w")); | |
151337e8 | 4842 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
5cbdaa77 | 4843 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
151337e8 | 4844 | fixP->fx_pcrel_adjust = -1; |
252b5132 | 4845 | break; |
151337e8 NC |
4846 | case TAB (BRANCHBWL, SHORT): |
4847 | case TAB (BRABSJUNC, SHORT): | |
4848 | case TAB (BRABSJCOND, SHORT): | |
4849 | case TAB (BRANCHBW, SHORT): | |
cac27205 | 4850 | case TAB (BRANCHBWPL, SHORT): |
252b5132 | 4851 | fragP->fr_opcode[1] = 0x00; |
2b878742 NS |
4852 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
4853 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
4854 | fragP->fr_fix += 2; |
4855 | break; | |
4856 | case TAB (BRANCHBWL, LONG): | |
4857 | fragP->fr_opcode[1] = (char) 0xFF; | |
2b878742 NS |
4858 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4859 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
151337e8 | 4860 | fragP->fr_fix += 4; |
252b5132 | 4861 | break; |
cac27205 NC |
4862 | case TAB (BRANCHBWPL, LONG): |
4863 | /* Here we are converting an unconditional branch into a pair of | |
4864 | conditional branches, in order to get the range. */ | |
4865 | fragP->fr_opcode[0] = 0x66; /* bne */ | |
4866 | fragP->fr_opcode[1] = 0xFF; | |
4867 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
4868 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
4869 | fixP->fx_file = fragP->fr_file; | |
4870 | fixP->fx_line = fragP->fr_line; | |
4871 | fragP->fr_fix += 4; /* Skip first offset */ | |
4872 | buffer_address += 4; | |
4873 | *buffer_address++ = 0x67; /* beq */ | |
4874 | *buffer_address++ = 0xff; | |
4875 | fragP->fr_fix += 2; /* Skip second branch opcode */ | |
4876 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
4877 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
4878 | fragP->fr_fix += 4; | |
4879 | break; | |
151337e8 NC |
4880 | case TAB (BRABSJUNC, LONG): |
4881 | if (fragP->fr_opcode[0] == 0x61) /* jbsr */ | |
252b5132 | 4882 | { |
36759679 | 4883 | if (flag_keep_pcrel) |
2b878742 NS |
4884 | as_bad_where (fragP->fr_file, fragP->fr_line, |
4885 | _("Conversion of PC relative BSR to absolute JSR")); | |
151337e8 | 4886 | fragP->fr_opcode[0] = 0x4E; |
36759679 | 4887 | fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ |
2b878742 NS |
4888 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4889 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 NC |
4890 | fragP->fr_fix += 4; |
4891 | } | |
4892 | else if (fragP->fr_opcode[0] == 0x60) /* jbra */ | |
4893 | { | |
36759679 | 4894 | if (flag_keep_pcrel) |
2b878742 NS |
4895 | as_bad_where (fragP->fr_file, fragP->fr_line, |
4896 | _("Conversion of PC relative branch to absolute jump")); | |
151337e8 | 4897 | fragP->fr_opcode[0] = 0x4E; |
36759679 | 4898 | fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ |
2b878742 NS |
4899 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4900 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 | 4901 | fragP->fr_fix += 4; |
252b5132 RH |
4902 | } |
4903 | else | |
4904 | { | |
151337e8 NC |
4905 | /* This cannot happen, because jbsr and jbra are the only two |
4906 | unconditional branches. */ | |
4907 | abort (); | |
252b5132 RH |
4908 | } |
4909 | break; | |
151337e8 | 4910 | case TAB (BRABSJCOND, LONG): |
36759679 | 4911 | if (flag_keep_pcrel) |
2b878742 NS |
4912 | as_bad_where (fragP->fr_file, fragP->fr_line, |
4913 | _("Conversion of PC relative conditional branch to absolute jump")); | |
92774660 | 4914 | |
36759679 NC |
4915 | /* Only Bcc 68000 instructions can come here |
4916 | Change bcc into b!cc/jmp absl long. */ | |
4917 | fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ | |
4918 | fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ | |
252b5132 RH |
4919 | |
4920 | /* JF: these used to be fr_opcode[2,3], but they may be in a | |
67c1ffbe | 4921 | different frag, in which case referring to them is a no-no. |
92774660 | 4922 | Only fr_opcode[0,1] are guaranteed to work. */ |
252b5132 RH |
4923 | *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ |
4924 | *buffer_address++ = (char) 0xf9; | |
36759679 | 4925 | fragP->fr_fix += 2; /* Account for jmp instruction. */ |
2b878742 NS |
4926 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4927 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 NC |
4928 | fragP->fr_fix += 4; |
4929 | break; | |
4930 | case TAB (FBRANCH, SHORT): | |
4931 | know ((fragP->fr_opcode[1] & 0x40) == 0); | |
2b878742 NS |
4932 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
4933 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
4934 | fragP->fr_fix += 2; |
4935 | break; | |
4936 | case TAB (FBRANCH, LONG): | |
36759679 | 4937 | fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ |
2b878742 NS |
4938 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4939 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
252b5132 | 4940 | fragP->fr_fix += 4; |
252b5132 | 4941 | break; |
151337e8 NC |
4942 | case TAB (DBCCLBR, SHORT): |
4943 | case TAB (DBCCABSJ, SHORT): | |
2b878742 NS |
4944 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
4945 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
4946 | fragP->fr_fix += 2; |
4947 | break; | |
4948 | case TAB (DBCCLBR, LONG): | |
36759679 NC |
4949 | /* Only DBcc instructions can come here. |
4950 | Change dbcc into dbcc/bral. | |
4951 | JF: these used to be fr_opcode[2-7], but that's wrong. */ | |
4952 | if (flag_keep_pcrel) | |
2b878742 NS |
4953 | as_bad_where (fragP->fr_file, fragP->fr_line, |
4954 | _("Conversion of DBcc to absolute jump")); | |
28e7409f | 4955 | |
36759679 | 4956 | *buffer_address++ = 0x00; /* Branch offset = 4. */ |
252b5132 | 4957 | *buffer_address++ = 0x04; |
36759679 | 4958 | *buffer_address++ = 0x60; /* Put in bra pc+6. */ |
252b5132 | 4959 | *buffer_address++ = 0x06; |
151337e8 NC |
4960 | *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ |
4961 | *buffer_address++ = (char) 0xff; | |
252b5132 | 4962 | |
36759679 | 4963 | fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ |
2b878742 NS |
4964 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4965 | fragP->fr_offset, 1, RELAX_RELOC_PC32); | |
252b5132 | 4966 | fragP->fr_fix += 4; |
252b5132 | 4967 | break; |
151337e8 | 4968 | case TAB (DBCCABSJ, LONG): |
36759679 NC |
4969 | /* Only DBcc instructions can come here. |
4970 | Change dbcc into dbcc/jmp. | |
4971 | JF: these used to be fr_opcode[2-7], but that's wrong. */ | |
4972 | if (flag_keep_pcrel) | |
2b878742 NS |
4973 | as_bad_where (fragP->fr_file, fragP->fr_line, |
4974 | _("Conversion of PC relative conditional branch to absolute jump")); | |
151337e8 | 4975 | |
36759679 | 4976 | *buffer_address++ = 0x00; /* Branch offset = 4. */ |
151337e8 | 4977 | *buffer_address++ = 0x04; |
36759679 | 4978 | *buffer_address++ = 0x60; /* Put in bra pc + 6. */ |
151337e8 | 4979 | *buffer_address++ = 0x06; |
36759679 | 4980 | *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ |
151337e8 NC |
4981 | *buffer_address++ = (char) 0xf9; |
4982 | ||
36759679 | 4983 | fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ |
2b878742 NS |
4984 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
4985 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
252b5132 | 4986 | fragP->fr_fix += 4; |
252b5132 | 4987 | break; |
151337e8 | 4988 | case TAB (PCREL1632, SHORT): |
252b5132 RH |
4989 | fragP->fr_opcode[1] &= ~0x3F; |
4990 | fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ | |
2b878742 NS |
4991 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, |
4992 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 | 4993 | fragP->fr_fix += 2; |
252b5132 | 4994 | break; |
151337e8 | 4995 | case TAB (PCREL1632, LONG): |
252b5132 RH |
4996 | /* Already set to mode 7.3; this indicates: PC indirect with |
4997 | suppressed index, 32-bit displacement. */ | |
4998 | *buffer_address++ = 0x01; | |
4999 | *buffer_address++ = 0x70; | |
5000 | fragP->fr_fix += 2; | |
151337e8 | 5001 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
5cbdaa77 | 5002 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
151337e8 NC |
5003 | fixP->fx_pcrel_adjust = 2; |
5004 | fragP->fr_fix += 4; | |
252b5132 | 5005 | break; |
252b5132 | 5006 | case TAB (PCINDEX, BYTE): |
252b5132 RH |
5007 | assert (fragP->fr_fix >= 2); |
5008 | buffer_address[-2] &= ~1; | |
151337e8 | 5009 | fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, |
5cbdaa77 | 5010 | fragP->fr_offset, 1, RELAX_RELOC_PC8); |
151337e8 | 5011 | fixP->fx_pcrel_adjust = 1; |
252b5132 RH |
5012 | break; |
5013 | case TAB (PCINDEX, SHORT): | |
252b5132 RH |
5014 | assert (fragP->fr_fix >= 2); |
5015 | buffer_address[-2] |= 0x1; | |
5016 | buffer_address[-1] = 0x20; | |
5017 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, | |
5cbdaa77 | 5018 | fragP->fr_offset, 1, RELAX_RELOC_PC16); |
252b5132 | 5019 | fixP->fx_pcrel_adjust = 2; |
151337e8 | 5020 | fragP->fr_fix += 2; |
252b5132 RH |
5021 | break; |
5022 | case TAB (PCINDEX, LONG): | |
252b5132 RH |
5023 | assert (fragP->fr_fix >= 2); |
5024 | buffer_address[-2] |= 0x1; | |
5025 | buffer_address[-1] = 0x30; | |
151337e8 | 5026 | fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, |
5cbdaa77 | 5027 | fragP->fr_offset, 1, RELAX_RELOC_PC32); |
151337e8 NC |
5028 | fixP->fx_pcrel_adjust = 2; |
5029 | fragP->fr_fix += 4; | |
5030 | break; | |
5031 | case TAB (ABSTOPCREL, SHORT): | |
2b878742 NS |
5032 | fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
5033 | fragP->fr_offset, 1, RELAX_RELOC_PC16); | |
151337e8 NC |
5034 | fragP->fr_fix += 2; |
5035 | break; | |
5036 | case TAB (ABSTOPCREL, LONG): | |
36759679 | 5037 | if (flag_keep_pcrel) |
025987ea NS |
5038 | as_bad_where (fragP->fr_file, fragP->fr_line, |
5039 | _("Conversion of PC relative displacement to absolute")); | |
151337e8 | 5040 | /* The thing to do here is force it to ABSOLUTE LONG, since |
36759679 | 5041 | ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ |
151337e8 NC |
5042 | if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) |
5043 | abort (); | |
5044 | fragP->fr_opcode[1] &= ~0x3F; | |
5045 | fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ | |
2b878742 NS |
5046 | fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, |
5047 | fragP->fr_offset, 0, RELAX_RELOC_ABS32); | |
151337e8 | 5048 | fragP->fr_fix += 4; |
252b5132 | 5049 | break; |
252b5132 | 5050 | } |
2b878742 NS |
5051 | if (fixP) |
5052 | { | |
5053 | fixP->fx_file = fragP->fr_file; | |
5054 | fixP->fx_line = fragP->fr_line; | |
5055 | } | |
252b5132 RH |
5056 | } |
5057 | ||
252b5132 | 5058 | void |
31302357 AS |
5059 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
5060 | segT sec ATTRIBUTE_UNUSED, | |
5061 | fragS *fragP) | |
252b5132 RH |
5062 | { |
5063 | md_convert_frag_1 (fragP); | |
5064 | } | |
252b5132 RH |
5065 | |
5066 | /* Force truly undefined symbols to their maximum size, and generally set up | |
5067 | the frag list to be relaxed | |
5068 | */ | |
5069 | int | |
31302357 | 5070 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 5071 | { |
151337e8 | 5072 | /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ |
252b5132 RH |
5073 | switch (fragP->fr_subtype) |
5074 | { | |
151337e8 | 5075 | case TAB (BRANCHBWL, SZ_UNDEF): |
cac27205 | 5076 | case TAB (BRANCHBWPL, SZ_UNDEF): |
151337e8 | 5077 | case TAB (BRABSJUNC, SZ_UNDEF): |
151337e8 | 5078 | case TAB (BRABSJCOND, SZ_UNDEF): |
252b5132 | 5079 | { |
151337e8 NC |
5080 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
5081 | && relaxable_symbol (fragP->fr_symbol)) | |
252b5132 | 5082 | { |
151337e8 NC |
5083 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
5084 | } | |
5085 | else if (flag_short_refs) | |
5086 | { | |
5087 | /* Symbol is undefined and we want short ref. */ | |
5088 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5089 | } |
5090 | else | |
5091 | { | |
151337e8 NC |
5092 | /* Symbol is still undefined. Make it LONG. */ |
5093 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); | |
252b5132 RH |
5094 | } |
5095 | break; | |
151337e8 | 5096 | } |
252b5132 | 5097 | |
151337e8 | 5098 | case TAB (BRANCHBW, SZ_UNDEF): |
252b5132 | 5099 | { |
151337e8 NC |
5100 | if (S_GET_SEGMENT (fragP->fr_symbol) == segment |
5101 | && relaxable_symbol (fragP->fr_symbol)) | |
252b5132 | 5102 | { |
151337e8 | 5103 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); |
252b5132 RH |
5104 | } |
5105 | else | |
5106 | { | |
151337e8 NC |
5107 | /* Symbol is undefined and we don't have long branches. */ |
5108 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5109 | } |
5110 | break; | |
151337e8 | 5111 | } |
252b5132 | 5112 | |
151337e8 | 5113 | case TAB (FBRANCH, SZ_UNDEF): |
151337e8 NC |
5114 | case TAB (DBCCLBR, SZ_UNDEF): |
5115 | case TAB (DBCCABSJ, SZ_UNDEF): | |
5c65dbc1 | 5116 | case TAB (PCREL1632, SZ_UNDEF): |
252b5132 | 5117 | { |
8ec6253e NC |
5118 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment |
5119 | && relaxable_symbol (fragP->fr_symbol)) | |
151337e8 | 5120 | || flag_short_refs) |
252b5132 | 5121 | { |
151337e8 | 5122 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); |
252b5132 RH |
5123 | } |
5124 | else | |
5125 | { | |
151337e8 | 5126 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); |
252b5132 RH |
5127 | } |
5128 | break; | |
151337e8 | 5129 | } |
81d4177b | 5130 | |
252b5132 RH |
5131 | case TAB (PCINDEX, SZ_UNDEF): |
5132 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment | |
151337e8 | 5133 | && relaxable_symbol (fragP->fr_symbol))) |
252b5132 RH |
5134 | { |
5135 | fragP->fr_subtype = TAB (PCINDEX, BYTE); | |
5136 | } | |
5137 | else | |
5138 | { | |
5139 | fragP->fr_subtype = TAB (PCINDEX, LONG); | |
252b5132 RH |
5140 | } |
5141 | break; | |
5142 | ||
151337e8 NC |
5143 | case TAB (ABSTOPCREL, SZ_UNDEF): |
5144 | { | |
5145 | if ((S_GET_SEGMENT (fragP->fr_symbol) == segment | |
5146 | && relaxable_symbol (fragP->fr_symbol))) | |
5147 | { | |
5148 | fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); | |
151337e8 NC |
5149 | } |
5150 | else | |
5151 | { | |
5152 | fragP->fr_subtype = TAB (ABSTOPCREL, LONG); | |
151337e8 NC |
5153 | } |
5154 | break; | |
5155 | } | |
5156 | ||
252b5132 RH |
5157 | default: |
5158 | break; | |
5159 | } | |
5160 | ||
151337e8 | 5161 | /* Now that SZ_UNDEF are taken care of, check others. */ |
252b5132 RH |
5162 | switch (fragP->fr_subtype) |
5163 | { | |
151337e8 NC |
5164 | case TAB (BRANCHBWL, BYTE): |
5165 | case TAB (BRABSJUNC, BYTE): | |
5166 | case TAB (BRABSJCOND, BYTE): | |
5167 | case TAB (BRANCHBW, BYTE): | |
252b5132 | 5168 | /* We can't do a short jump to the next instruction, so in that |
ac62c346 AM |
5169 | case we force word mode. If the symbol is at the start of a |
5170 | frag, and it is the next frag with any data in it (usually | |
5171 | this is just the next frag, but assembler listings may | |
5172 | introduce empty frags), we must use word mode. */ | |
5173 | if (fragP->fr_symbol) | |
252b5132 | 5174 | { |
ac62c346 | 5175 | fragS *sym_frag; |
252b5132 | 5176 | |
ac62c346 AM |
5177 | sym_frag = symbol_get_frag (fragP->fr_symbol); |
5178 | if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) | |
252b5132 | 5179 | { |
ac62c346 AM |
5180 | fragS *l; |
5181 | ||
23b7f870 | 5182 | for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) |
ac62c346 AM |
5183 | if (l->fr_fix != 0) |
5184 | break; | |
5185 | if (l == sym_frag) | |
5186 | fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); | |
252b5132 RH |
5187 | } |
5188 | } | |
5189 | break; | |
5190 | default: | |
5191 | break; | |
5192 | } | |
ac62c346 | 5193 | return md_relax_table[fragP->fr_subtype].rlx_length; |
252b5132 RH |
5194 | } |
5195 | ||
5196 | #if defined(OBJ_AOUT) | defined(OBJ_BOUT) | |
5197 | /* the bit-field entries in the relocation_info struct plays hell | |
5198 | with the byte-order problems of cross-assembly. So as a hack, | |
5199 | I added this mach. dependent ri twiddler. Ugly, but it gets | |
36759679 | 5200 | you there. -KWK */ |
252b5132 RH |
5201 | /* on m68k: first 4 bytes are normal unsigned long, next three bytes |
5202 | are symbolnum, most sig. byte first. Last byte is broken up with | |
5203 | bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower | |
5204 | nibble as nuthin. (on Sun 3 at least) */ | |
5205 | /* Translate the internal relocation information into target-specific | |
92774660 | 5206 | format. */ |
252b5132 RH |
5207 | #ifdef comment |
5208 | void | |
31302357 | 5209 | md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri) |
252b5132 | 5210 | { |
36759679 | 5211 | /* This is easy. */ |
252b5132 | 5212 | md_number_to_chars (the_bytes, ri->r_address, 4); |
36759679 | 5213 | /* Now the fun stuff. */ |
252b5132 | 5214 | the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; |
36759679 NC |
5215 | the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; |
5216 | the_bytes[6] = ri->r_symbolnum & 0x0ff; | |
31302357 AS |
5217 | the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) |
5218 | | ((ri->r_length << 5) & 0x60) | |
5219 | | ((ri->r_extern << 4) & 0x10)); | |
252b5132 RH |
5220 | } |
5221 | ||
36759679 | 5222 | #endif |
252b5132 | 5223 | |
252b5132 RH |
5224 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
5225 | ||
5226 | #ifndef WORKING_DOT_WORD | |
2b4f075a HPN |
5227 | int md_short_jump_size = 4; |
5228 | int md_long_jump_size = 6; | |
252b5132 RH |
5229 | |
5230 | void | |
31302357 AS |
5231 | md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, |
5232 | fragS *frag ATTRIBUTE_UNUSED, | |
5233 | symbolS *to_symbol ATTRIBUTE_UNUSED) | |
252b5132 RH |
5234 | { |
5235 | valueT offset; | |
5236 | ||
5237 | offset = to_addr - (from_addr + 2); | |
5238 | ||
5239 | md_number_to_chars (ptr, (valueT) 0x6000, 2); | |
5240 | md_number_to_chars (ptr + 2, (valueT) offset, 2); | |
5241 | } | |
5242 | ||
5243 | void | |
31302357 AS |
5244 | md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, |
5245 | fragS *frag, symbolS *to_symbol) | |
252b5132 RH |
5246 | { |
5247 | valueT offset; | |
5248 | ||
6b6e92f4 | 5249 | if (!HAVE_LONG_BRANCH (current_architecture)) |
252b5132 | 5250 | { |
36759679 | 5251 | if (flag_keep_pcrel) |
6b6e92f4 | 5252 | as_fatal (_("Tried to convert PC relative branch to absolute jump")); |
252b5132 RH |
5253 | offset = to_addr - S_GET_VALUE (to_symbol); |
5254 | md_number_to_chars (ptr, (valueT) 0x4EF9, 2); | |
5255 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
5256 | fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, | |
5257 | 0, NO_RELOC); | |
5258 | } | |
5259 | else | |
5260 | { | |
5261 | offset = to_addr - (from_addr + 2); | |
5262 | md_number_to_chars (ptr, (valueT) 0x60ff, 2); | |
5263 | md_number_to_chars (ptr + 2, (valueT) offset, 4); | |
5264 | } | |
5265 | } | |
5266 | ||
5267 | #endif | |
5268 | ||
5269 | /* Different values of OK tell what its OK to return. Things that | |
5270 | aren't OK are an error (what a shock, no?) | |
5271 | ||
5272 | 0: Everything is OK | |
3e602632 NC |
5273 | 10: Absolute 1:8 only |
5274 | 20: Absolute 0:7 only | |
5275 | 30: absolute 0:15 only | |
5276 | 40: Absolute 0:31 only | |
5277 | 50: absolute 0:127 only | |
252b5132 | 5278 | 55: absolute -64:63 only |
3e602632 | 5279 | 60: absolute -128:127 only |
afa2158f | 5280 | 65: absolute 0:511 only |
3e602632 NC |
5281 | 70: absolute 0:4095 only |
5282 | 80: absolute -1, 1:7 only | |
5283 | 90: No bignums. */ | |
252b5132 RH |
5284 | |
5285 | static int | |
31302357 | 5286 | get_num (struct m68k_exp *exp, int ok) |
252b5132 RH |
5287 | { |
5288 | if (exp->exp.X_op == O_absent) | |
5289 | { | |
36759679 | 5290 | /* Do the same thing the VAX asm does. */ |
252b5132 RH |
5291 | op (exp) = O_constant; |
5292 | adds (exp) = 0; | |
5293 | subs (exp) = 0; | |
5294 | offs (exp) = 0; | |
5295 | if (ok == 10) | |
5296 | { | |
5297 | as_warn (_("expression out of range: defaulting to 1")); | |
5298 | offs (exp) = 1; | |
5299 | } | |
5300 | } | |
5301 | else if (exp->exp.X_op == O_constant) | |
5302 | { | |
5303 | switch (ok) | |
5304 | { | |
5305 | case 10: | |
bd17c2c3 | 5306 | if ((valueT) TRUNC (offs (exp)) - 1 > 7) |
252b5132 RH |
5307 | { |
5308 | as_warn (_("expression out of range: defaulting to 1")); | |
5309 | offs (exp) = 1; | |
5310 | } | |
5311 | break; | |
5312 | case 20: | |
bd17c2c3 | 5313 | if ((valueT) TRUNC (offs (exp)) > 7) |
252b5132 RH |
5314 | goto outrange; |
5315 | break; | |
5316 | case 30: | |
bd17c2c3 | 5317 | if ((valueT) TRUNC (offs (exp)) > 15) |
252b5132 RH |
5318 | goto outrange; |
5319 | break; | |
5320 | case 40: | |
bd17c2c3 | 5321 | if ((valueT) TRUNC (offs (exp)) > 32) |
252b5132 RH |
5322 | goto outrange; |
5323 | break; | |
5324 | case 50: | |
bd17c2c3 | 5325 | if ((valueT) TRUNC (offs (exp)) > 127) |
252b5132 RH |
5326 | goto outrange; |
5327 | break; | |
5328 | case 55: | |
bd17c2c3 | 5329 | if ((valueT) SEXT (offs (exp)) + 64 > 127) |
252b5132 RH |
5330 | goto outrange; |
5331 | break; | |
5332 | case 60: | |
bd17c2c3 | 5333 | if ((valueT) SEXT (offs (exp)) + 128 > 255) |
252b5132 | 5334 | goto outrange; |
afa2158f NS |
5335 | break; |
5336 | case 65: | |
5337 | if ((valueT) TRUNC (offs (exp)) > 511) | |
5338 | goto outrange; | |
252b5132 RH |
5339 | break; |
5340 | case 70: | |
bd17c2c3 | 5341 | if ((valueT) TRUNC (offs (exp)) > 4095) |
252b5132 RH |
5342 | { |
5343 | outrange: | |
5344 | as_warn (_("expression out of range: defaulting to 0")); | |
5345 | offs (exp) = 0; | |
5346 | } | |
5347 | break; | |
3e602632 | 5348 | case 80: |
bd17c2c3 AM |
5349 | if ((valueT) TRUNC (offs (exp)) != 0xffffffff |
5350 | && (valueT) TRUNC (offs (exp)) - 1 > 6) | |
3e602632 NC |
5351 | { |
5352 | as_warn (_("expression out of range: defaulting to 1")); | |
5353 | offs (exp) = 1; | |
5354 | } | |
5355 | break; | |
252b5132 RH |
5356 | default: |
5357 | break; | |
5358 | } | |
5359 | } | |
5360 | else if (exp->exp.X_op == O_big) | |
5361 | { | |
36759679 | 5362 | if (offs (exp) <= 0 /* flonum. */ |
3e602632 | 5363 | && (ok == 90 /* no bignums */ |
36759679 | 5364 | || (ok > 10 /* Small-int ranges including 0 ok. */ |
252b5132 RH |
5365 | /* If we have a flonum zero, a zero integer should |
5366 | do as well (e.g., in moveq). */ | |
5367 | && generic_floating_point_number.exponent == 0 | |
5368 | && generic_floating_point_number.low[0] == 0))) | |
5369 | { | |
36759679 | 5370 | /* HACK! Turn it into a long. */ |
252b5132 RH |
5371 | LITTLENUM_TYPE words[6]; |
5372 | ||
36759679 | 5373 | gen_to_words (words, 2, 8L); /* These numbers are magic! */ |
252b5132 RH |
5374 | op (exp) = O_constant; |
5375 | adds (exp) = 0; | |
5376 | subs (exp) = 0; | |
5377 | offs (exp) = words[1] | (words[0] << 16); | |
5378 | } | |
5379 | else if (ok != 0) | |
5380 | { | |
5381 | op (exp) = O_constant; | |
5382 | adds (exp) = 0; | |
5383 | subs (exp) = 0; | |
5384 | offs (exp) = (ok == 10) ? 1 : 0; | |
5385 | as_warn (_("Can't deal with expression; defaulting to %ld"), | |
045b540e | 5386 | (long) offs (exp)); |
252b5132 RH |
5387 | } |
5388 | } | |
5389 | else | |
5390 | { | |
3e602632 | 5391 | if (ok >= 10 && ok <= 80) |
252b5132 RH |
5392 | { |
5393 | op (exp) = O_constant; | |
5394 | adds (exp) = 0; | |
5395 | subs (exp) = 0; | |
5396 | offs (exp) = (ok == 10) ? 1 : 0; | |
5397 | as_warn (_("Can't deal with expression; defaulting to %ld"), | |
045b540e | 5398 | (long) offs (exp)); |
252b5132 RH |
5399 | } |
5400 | } | |
5401 | ||
5402 | if (exp->size != SIZE_UNSPEC) | |
5403 | { | |
5404 | switch (exp->size) | |
5405 | { | |
5406 | case SIZE_UNSPEC: | |
5407 | case SIZE_LONG: | |
5408 | break; | |
5409 | case SIZE_BYTE: | |
5410 | if (!isbyte (offs (exp))) | |
5411 | as_warn (_("expression doesn't fit in BYTE")); | |
5412 | break; | |
5413 | case SIZE_WORD: | |
5414 | if (!isword (offs (exp))) | |
5415 | as_warn (_("expression doesn't fit in WORD")); | |
5416 | break; | |
5417 | } | |
5418 | } | |
5419 | ||
5420 | return offs (exp); | |
5421 | } | |
5422 | ||
5423 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
5424 | ||
5425 | static void | |
31302357 | 5426 | s_data1 (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5427 | { |
5428 | subseg_set (data_section, 1); | |
5429 | demand_empty_rest_of_line (); | |
5430 | } | |
5431 | ||
5432 | static void | |
31302357 | 5433 | s_data2 (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5434 | { |
5435 | subseg_set (data_section, 2); | |
5436 | demand_empty_rest_of_line (); | |
5437 | } | |
5438 | ||
5439 | static void | |
31302357 | 5440 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5441 | { |
5442 | /* We don't support putting frags in the BSS segment, we fake it | |
5443 | by marking in_bss, then looking at s_skip for clues. */ | |
5444 | ||
5445 | subseg_set (bss_section, 0); | |
5446 | demand_empty_rest_of_line (); | |
5447 | } | |
5448 | ||
5449 | static void | |
31302357 | 5450 | s_even (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5451 | { |
5452 | register int temp; | |
5453 | register long temp_fill; | |
5454 | ||
5455 | temp = 1; /* JF should be 2? */ | |
5456 | temp_fill = get_absolute_expression (); | |
92774660 | 5457 | if (!need_pass_2) /* Never make frag if expect extra pass. */ |
252b5132 RH |
5458 | frag_align (temp, (int) temp_fill, 0); |
5459 | demand_empty_rest_of_line (); | |
5460 | record_alignment (now_seg, temp); | |
5461 | } | |
5462 | ||
5463 | static void | |
31302357 | 5464 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5465 | { |
5466 | demand_empty_rest_of_line (); | |
5467 | } | |
5468 | \f | |
5469 | /* Pseudo-ops handled for MRI compatibility. */ | |
5470 | ||
5471 | /* This function returns non-zero if the argument is a conditional | |
5472 | pseudo-op. This is called when checking whether a pending | |
5473 | alignment is needed. */ | |
5474 | ||
5475 | int | |
31302357 | 5476 | m68k_conditional_pseudoop (pseudo_typeS *pop) |
252b5132 RH |
5477 | { |
5478 | return (pop->poc_handler == s_mri_if | |
5479 | || pop->poc_handler == s_mri_else); | |
5480 | } | |
5481 | ||
5482 | /* Handle an MRI style chip specification. */ | |
5483 | ||
5484 | static void | |
31302357 | 5485 | mri_chip (void) |
252b5132 RH |
5486 | { |
5487 | char *s; | |
5488 | char c; | |
5489 | int i; | |
5490 | ||
5491 | s = input_line_pointer; | |
5492 | /* We can't use get_symbol_end since the processor names are not proper | |
5493 | symbols. */ | |
5494 | while (is_part_of_name (c = *input_line_pointer++)) | |
5495 | ; | |
5496 | *--input_line_pointer = 0; | |
266abb8f NS |
5497 | for (i = 0; m68k_cpus[i].name; i++) |
5498 | if (strcasecmp (s, m68k_cpus[i].name) == 0) | |
252b5132 | 5499 | break; |
266abb8f | 5500 | if (!m68k_cpus[i].name) |
252b5132 RH |
5501 | { |
5502 | as_bad (_("%s: unrecognized processor name"), s); | |
5503 | *input_line_pointer = c; | |
5504 | ignore_rest_of_line (); | |
5505 | return; | |
5506 | } | |
5507 | *input_line_pointer = c; | |
5508 | ||
5509 | if (*input_line_pointer == '/') | |
5510 | current_architecture = 0; | |
5511 | else | |
5512 | current_architecture &= m68881 | m68851; | |
266abb8f | 5513 | current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851); |
2da12c60 | 5514 | control_regs = m68k_cpus[i].control_regs; |
252b5132 RH |
5515 | |
5516 | while (*input_line_pointer == '/') | |
5517 | { | |
5518 | ++input_line_pointer; | |
5519 | s = input_line_pointer; | |
5520 | /* We can't use get_symbol_end since the processor names are not | |
5521 | proper symbols. */ | |
5522 | while (is_part_of_name (c = *input_line_pointer++)) | |
5523 | ; | |
5524 | *--input_line_pointer = 0; | |
5525 | if (strcmp (s, "68881") == 0) | |
5526 | current_architecture |= m68881; | |
5527 | else if (strcmp (s, "68851") == 0) | |
5528 | current_architecture |= m68851; | |
5529 | *input_line_pointer = c; | |
5530 | } | |
252b5132 RH |
5531 | } |
5532 | ||
5533 | /* The MRI CHIP pseudo-op. */ | |
5534 | ||
5535 | static void | |
31302357 | 5536 | s_chip (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5537 | { |
5538 | char *stop = NULL; | |
5539 | char stopc; | |
5540 | ||
5541 | if (flag_mri) | |
5542 | stop = mri_comment_field (&stopc); | |
5543 | mri_chip (); | |
5544 | if (flag_mri) | |
5545 | mri_comment_end (stop, stopc); | |
5546 | demand_empty_rest_of_line (); | |
5547 | } | |
5548 | ||
5549 | /* The MRI FOPT pseudo-op. */ | |
5550 | ||
5551 | static void | |
31302357 | 5552 | s_fopt (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5553 | { |
5554 | SKIP_WHITESPACE (); | |
5555 | ||
5556 | if (strncasecmp (input_line_pointer, "ID=", 3) == 0) | |
5557 | { | |
5558 | int temp; | |
5559 | ||
5560 | input_line_pointer += 3; | |
5561 | temp = get_absolute_expression (); | |
5562 | if (temp < 0 || temp > 7) | |
5563 | as_bad (_("bad coprocessor id")); | |
5564 | else | |
5565 | m68k_float_copnum = COP0 + temp; | |
5566 | } | |
5567 | else | |
5568 | { | |
5569 | as_bad (_("unrecognized fopt option")); | |
5570 | ignore_rest_of_line (); | |
5571 | return; | |
5572 | } | |
5573 | ||
5574 | demand_empty_rest_of_line (); | |
5575 | } | |
5576 | ||
5577 | /* The structure used to handle the MRI OPT pseudo-op. */ | |
5578 | ||
5579 | struct opt_action | |
5580 | { | |
5581 | /* The name of the option. */ | |
5582 | const char *name; | |
5583 | ||
5584 | /* If this is not NULL, just call this function. The first argument | |
5585 | is the ARG field of this structure, the second argument is | |
5586 | whether the option was negated. */ | |
31302357 | 5587 | void (*pfn) (int arg, int on); |
252b5132 RH |
5588 | |
5589 | /* If this is not NULL, and the PFN field is NULL, set the variable | |
5590 | this points to. Set it to the ARG field if the option was not | |
5591 | negated, and the NOTARG field otherwise. */ | |
5592 | int *pvar; | |
5593 | ||
5594 | /* The value to pass to PFN or to assign to *PVAR. */ | |
5595 | int arg; | |
5596 | ||
5597 | /* The value to assign to *PVAR if the option is negated. If PFN is | |
5598 | NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then | |
5599 | the option may not be negated. */ | |
5600 | int notarg; | |
5601 | }; | |
5602 | ||
5603 | /* The table used to handle the MRI OPT pseudo-op. */ | |
5604 | ||
31302357 AS |
5605 | static void skip_to_comma (int, int); |
5606 | static void opt_nest (int, int); | |
5607 | static void opt_chip (int, int); | |
5608 | static void opt_list (int, int); | |
5609 | static void opt_list_symbols (int, int); | |
252b5132 RH |
5610 | |
5611 | static const struct opt_action opt_table[] = | |
5612 | { | |
5613 | { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, | |
5614 | ||
5615 | /* We do relaxing, so there is little use for these options. */ | |
5616 | { "b", 0, 0, 0, 0 }, | |
5617 | { "brs", 0, 0, 0, 0 }, | |
5618 | { "brb", 0, 0, 0, 0 }, | |
5619 | { "brl", 0, 0, 0, 0 }, | |
5620 | { "brw", 0, 0, 0, 0 }, | |
5621 | ||
5622 | { "c", 0, 0, 0, 0 }, | |
5623 | { "cex", 0, 0, 0, 0 }, | |
5624 | { "case", 0, &symbols_case_sensitive, 1, 0 }, | |
5625 | { "cl", 0, 0, 0, 0 }, | |
5626 | { "cre", 0, 0, 0, 0 }, | |
5627 | { "d", 0, &flag_keep_locals, 1, 0 }, | |
5628 | { "e", 0, 0, 0, 0 }, | |
5629 | { "f", 0, &flag_short_refs, 1, 0 }, | |
5630 | { "frs", 0, &flag_short_refs, 1, 0 }, | |
5631 | { "frl", 0, &flag_short_refs, 0, 1 }, | |
5632 | { "g", 0, 0, 0, 0 }, | |
5633 | { "i", 0, 0, 0, 0 }, | |
5634 | { "m", 0, 0, 0, 0 }, | |
5635 | { "mex", 0, 0, 0, 0 }, | |
5636 | { "mc", 0, 0, 0, 0 }, | |
5637 | { "md", 0, 0, 0, 0 }, | |
5638 | { "nest", opt_nest, 0, 0, 0 }, | |
5639 | { "next", skip_to_comma, 0, 0, 0 }, | |
5640 | { "o", 0, 0, 0, 0 }, | |
5641 | { "old", 0, 0, 0, 0 }, | |
5642 | { "op", skip_to_comma, 0, 0, 0 }, | |
5643 | { "pco", 0, 0, 0, 0 }, | |
5644 | { "p", opt_chip, 0, 0, 0 }, | |
5645 | { "pcr", 0, 0, 0, 0 }, | |
5646 | { "pcs", 0, 0, 0, 0 }, | |
5647 | { "r", 0, 0, 0, 0 }, | |
5648 | { "quick", 0, &m68k_quick, 1, 0 }, | |
5649 | { "rel32", 0, &m68k_rel32, 1, 0 }, | |
5650 | { "s", opt_list, 0, 0, 0 }, | |
5651 | { "t", opt_list_symbols, 0, 0, 0 }, | |
5652 | { "w", 0, &flag_no_warnings, 0, 1 }, | |
5653 | { "x", 0, 0, 0, 0 } | |
5654 | }; | |
5655 | ||
8fce3f5e | 5656 | #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) |
252b5132 RH |
5657 | |
5658 | /* The MRI OPT pseudo-op. */ | |
5659 | ||
5660 | static void | |
31302357 | 5661 | s_opt (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5662 | { |
5663 | do | |
5664 | { | |
5665 | int t; | |
5666 | char *s; | |
5667 | char c; | |
5668 | int i; | |
5669 | const struct opt_action *o; | |
5670 | ||
5671 | SKIP_WHITESPACE (); | |
5672 | ||
5673 | t = 1; | |
5674 | if (*input_line_pointer == '-') | |
5675 | { | |
5676 | ++input_line_pointer; | |
5677 | t = 0; | |
5678 | } | |
5679 | else if (strncasecmp (input_line_pointer, "NO", 2) == 0) | |
5680 | { | |
5681 | input_line_pointer += 2; | |
5682 | t = 0; | |
5683 | } | |
5684 | ||
5685 | s = input_line_pointer; | |
5686 | c = get_symbol_end (); | |
5687 | ||
5688 | for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) | |
5689 | { | |
5690 | if (strcasecmp (s, o->name) == 0) | |
5691 | { | |
5692 | if (o->pfn) | |
5693 | { | |
5694 | /* Restore input_line_pointer now in case the option | |
5695 | takes arguments. */ | |
5696 | *input_line_pointer = c; | |
5697 | (*o->pfn) (o->arg, t); | |
5698 | } | |
5699 | else if (o->pvar != NULL) | |
5700 | { | |
5701 | if (! t && o->arg == o->notarg) | |
5702 | as_bad (_("option `%s' may not be negated"), s); | |
5703 | *input_line_pointer = c; | |
5704 | *o->pvar = t ? o->arg : o->notarg; | |
5705 | } | |
5706 | else | |
5707 | *input_line_pointer = c; | |
5708 | break; | |
5709 | } | |
5710 | } | |
5711 | if (i >= OPTCOUNT) | |
5712 | { | |
5713 | as_bad (_("option `%s' not recognized"), s); | |
5714 | *input_line_pointer = c; | |
5715 | } | |
5716 | } | |
5717 | while (*input_line_pointer++ == ','); | |
5718 | ||
5719 | /* Move back to terminating character. */ | |
5720 | --input_line_pointer; | |
5721 | demand_empty_rest_of_line (); | |
5722 | } | |
5723 | ||
5724 | /* Skip ahead to a comma. This is used for OPT options which we do | |
67c1ffbe | 5725 | not support and which take arguments. */ |
252b5132 RH |
5726 | |
5727 | static void | |
31302357 | 5728 | skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5729 | { |
5730 | while (*input_line_pointer != ',' | |
5731 | && ! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5732 | ++input_line_pointer; | |
5733 | } | |
5734 | ||
5735 | /* Handle the OPT NEST=depth option. */ | |
5736 | ||
5737 | static void | |
31302357 | 5738 | opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5739 | { |
5740 | if (*input_line_pointer != '=') | |
5741 | { | |
5742 | as_bad (_("bad format of OPT NEST=depth")); | |
5743 | return; | |
5744 | } | |
5745 | ||
5746 | ++input_line_pointer; | |
5747 | max_macro_nest = get_absolute_expression (); | |
5748 | } | |
5749 | ||
5750 | /* Handle the OPT P=chip option. */ | |
5751 | ||
5752 | static void | |
31302357 | 5753 | opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) |
252b5132 RH |
5754 | { |
5755 | if (*input_line_pointer != '=') | |
5756 | { | |
5757 | /* This is just OPT P, which we do not support. */ | |
5758 | return; | |
5759 | } | |
5760 | ||
5761 | ++input_line_pointer; | |
5762 | mri_chip (); | |
5763 | } | |
5764 | ||
5765 | /* Handle the OPT S option. */ | |
5766 | ||
5767 | static void | |
31302357 | 5768 | opt_list (int arg ATTRIBUTE_UNUSED, int on) |
252b5132 RH |
5769 | { |
5770 | listing_list (on); | |
5771 | } | |
5772 | ||
5773 | /* Handle the OPT T option. */ | |
5774 | ||
5775 | static void | |
31302357 | 5776 | opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) |
252b5132 RH |
5777 | { |
5778 | if (on) | |
5779 | listing |= LISTING_SYMBOLS; | |
5780 | else | |
8a104df9 | 5781 | listing &= ~LISTING_SYMBOLS; |
252b5132 RH |
5782 | } |
5783 | ||
5784 | /* Handle the MRI REG pseudo-op. */ | |
5785 | ||
5786 | static void | |
31302357 | 5787 | s_reg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5788 | { |
5789 | char *s; | |
5790 | int c; | |
5791 | struct m68k_op rop; | |
5792 | int mask; | |
5793 | char *stop = NULL; | |
5794 | char stopc; | |
5795 | ||
5796 | if (line_label == NULL) | |
5797 | { | |
5798 | as_bad (_("missing label")); | |
5799 | ignore_rest_of_line (); | |
5800 | return; | |
5801 | } | |
5802 | ||
5803 | if (flag_mri) | |
5804 | stop = mri_comment_field (&stopc); | |
5805 | ||
5806 | SKIP_WHITESPACE (); | |
5807 | ||
5808 | s = input_line_pointer; | |
3882b010 | 5809 | while (ISALNUM (*input_line_pointer) |
252b5132 RH |
5810 | #ifdef REGISTER_PREFIX |
5811 | || *input_line_pointer == REGISTER_PREFIX | |
5812 | #endif | |
5813 | || *input_line_pointer == '/' | |
5814 | || *input_line_pointer == '-') | |
5815 | ++input_line_pointer; | |
5816 | c = *input_line_pointer; | |
5817 | *input_line_pointer = '\0'; | |
5818 | ||
5819 | if (m68k_ip_op (s, &rop) != 0) | |
5820 | { | |
5821 | if (rop.error == NULL) | |
5822 | as_bad (_("bad register list")); | |
5823 | else | |
5824 | as_bad (_("bad register list: %s"), rop.error); | |
5825 | *input_line_pointer = c; | |
5826 | ignore_rest_of_line (); | |
5827 | return; | |
5828 | } | |
5829 | ||
5830 | *input_line_pointer = c; | |
5831 | ||
5832 | if (rop.mode == REGLST) | |
5833 | mask = rop.mask; | |
5834 | else if (rop.mode == DREG) | |
5835 | mask = 1 << (rop.reg - DATA0); | |
5836 | else if (rop.mode == AREG) | |
5837 | mask = 1 << (rop.reg - ADDR0 + 8); | |
5838 | else if (rop.mode == FPREG) | |
5839 | mask = 1 << (rop.reg - FP0 + 16); | |
5840 | else if (rop.mode == CONTROL | |
5841 | && rop.reg == FPI) | |
5842 | mask = 1 << 24; | |
5843 | else if (rop.mode == CONTROL | |
5844 | && rop.reg == FPS) | |
5845 | mask = 1 << 25; | |
5846 | else if (rop.mode == CONTROL | |
5847 | && rop.reg == FPC) | |
5848 | mask = 1 << 26; | |
5849 | else | |
5850 | { | |
5851 | as_bad (_("bad register list")); | |
5852 | ignore_rest_of_line (); | |
5853 | return; | |
5854 | } | |
5855 | ||
5856 | S_SET_SEGMENT (line_label, reg_section); | |
5857 | S_SET_VALUE (line_label, ~mask); | |
49309057 | 5858 | symbol_set_frag (line_label, &zero_address_frag); |
252b5132 RH |
5859 | |
5860 | if (flag_mri) | |
5861 | mri_comment_end (stop, stopc); | |
5862 | ||
5863 | demand_empty_rest_of_line (); | |
5864 | } | |
5865 | ||
5866 | /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ | |
5867 | ||
5868 | struct save_opts | |
5869 | { | |
5870 | struct save_opts *next; | |
5871 | int abspcadd; | |
5872 | int symbols_case_sensitive; | |
5873 | int keep_locals; | |
5874 | int short_refs; | |
5875 | int architecture; | |
2da12c60 | 5876 | const enum m68k_register *control_regs; |
252b5132 RH |
5877 | int quick; |
5878 | int rel32; | |
5879 | int listing; | |
5880 | int no_warnings; | |
5881 | /* FIXME: We don't save OPT S. */ | |
5882 | }; | |
5883 | ||
5884 | /* This variable holds the stack of saved options. */ | |
5885 | ||
5886 | static struct save_opts *save_stack; | |
5887 | ||
5888 | /* The MRI SAVE pseudo-op. */ | |
5889 | ||
5890 | static void | |
31302357 | 5891 | s_save (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5892 | { |
5893 | struct save_opts *s; | |
5894 | ||
5895 | s = (struct save_opts *) xmalloc (sizeof (struct save_opts)); | |
5896 | s->abspcadd = m68k_abspcadd; | |
5897 | s->symbols_case_sensitive = symbols_case_sensitive; | |
5898 | s->keep_locals = flag_keep_locals; | |
5899 | s->short_refs = flag_short_refs; | |
5900 | s->architecture = current_architecture; | |
2da12c60 | 5901 | s->control_regs = control_regs; |
252b5132 RH |
5902 | s->quick = m68k_quick; |
5903 | s->rel32 = m68k_rel32; | |
5904 | s->listing = listing; | |
5905 | s->no_warnings = flag_no_warnings; | |
5906 | ||
5907 | s->next = save_stack; | |
5908 | save_stack = s; | |
5909 | ||
5910 | demand_empty_rest_of_line (); | |
5911 | } | |
5912 | ||
5913 | /* The MRI RESTORE pseudo-op. */ | |
5914 | ||
5915 | static void | |
31302357 | 5916 | s_restore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5917 | { |
5918 | struct save_opts *s; | |
5919 | ||
5920 | if (save_stack == NULL) | |
5921 | { | |
5922 | as_bad (_("restore without save")); | |
5923 | ignore_rest_of_line (); | |
5924 | return; | |
5925 | } | |
5926 | ||
5927 | s = save_stack; | |
5928 | save_stack = s->next; | |
5929 | ||
5930 | m68k_abspcadd = s->abspcadd; | |
5931 | symbols_case_sensitive = s->symbols_case_sensitive; | |
5932 | flag_keep_locals = s->keep_locals; | |
5933 | flag_short_refs = s->short_refs; | |
5934 | current_architecture = s->architecture; | |
2da12c60 | 5935 | control_regs = s->control_regs; |
252b5132 RH |
5936 | m68k_quick = s->quick; |
5937 | m68k_rel32 = s->rel32; | |
5938 | listing = s->listing; | |
5939 | flag_no_warnings = s->no_warnings; | |
5940 | ||
5941 | free (s); | |
5942 | ||
5943 | demand_empty_rest_of_line (); | |
5944 | } | |
5945 | ||
5946 | /* Types of MRI structured control directives. */ | |
5947 | ||
5948 | enum mri_control_type | |
5949 | { | |
5950 | mri_for, | |
5951 | mri_if, | |
5952 | mri_repeat, | |
5953 | mri_while | |
5954 | }; | |
5955 | ||
5956 | /* This structure is used to stack the MRI structured control | |
5957 | directives. */ | |
5958 | ||
5959 | struct mri_control_info | |
5960 | { | |
5961 | /* The directive within which this one is enclosed. */ | |
5962 | struct mri_control_info *outer; | |
5963 | ||
5964 | /* The type of directive. */ | |
5965 | enum mri_control_type type; | |
5966 | ||
5967 | /* Whether an ELSE has been in an IF. */ | |
5968 | int else_seen; | |
5969 | ||
5970 | /* The add or sub statement at the end of a FOR. */ | |
5971 | char *incr; | |
5972 | ||
5973 | /* The label of the top of a FOR or REPEAT loop. */ | |
5974 | char *top; | |
5975 | ||
5976 | /* The label to jump to for the next iteration, or the else | |
5977 | expression of a conditional. */ | |
5978 | char *next; | |
5979 | ||
5980 | /* The label to jump to to break out of the loop, or the label past | |
5981 | the end of a conditional. */ | |
5982 | char *bottom; | |
5983 | }; | |
5984 | ||
5985 | /* The stack of MRI structured control directives. */ | |
5986 | ||
5987 | static struct mri_control_info *mri_control_stack; | |
5988 | ||
5989 | /* The current MRI structured control directive index number, used to | |
5990 | generate label names. */ | |
5991 | ||
5992 | static int mri_control_index; | |
5993 | ||
252b5132 RH |
5994 | /* Assemble an instruction for an MRI structured control directive. */ |
5995 | ||
5996 | static void | |
31302357 | 5997 | mri_assemble (char *str) |
252b5132 RH |
5998 | { |
5999 | char *s; | |
6000 | ||
6001 | /* md_assemble expects the opcode to be in lower case. */ | |
6002 | for (s = str; *s != ' ' && *s != '\0'; s++) | |
3882b010 | 6003 | *s = TOLOWER (*s); |
252b5132 RH |
6004 | |
6005 | md_assemble (str); | |
6006 | } | |
6007 | ||
6008 | /* Generate a new MRI label structured control directive label name. */ | |
6009 | ||
6010 | static char * | |
31302357 | 6011 | mri_control_label (void) |
252b5132 RH |
6012 | { |
6013 | char *n; | |
6014 | ||
6015 | n = (char *) xmalloc (20); | |
6016 | sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); | |
6017 | ++mri_control_index; | |
6018 | return n; | |
6019 | } | |
6020 | ||
6021 | /* Create a new MRI structured control directive. */ | |
6022 | ||
6023 | static struct mri_control_info * | |
31302357 | 6024 | push_mri_control (enum mri_control_type type) |
252b5132 RH |
6025 | { |
6026 | struct mri_control_info *n; | |
6027 | ||
6028 | n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info)); | |
6029 | ||
6030 | n->type = type; | |
6031 | n->else_seen = 0; | |
6032 | if (type == mri_if || type == mri_while) | |
6033 | n->top = NULL; | |
6034 | else | |
6035 | n->top = mri_control_label (); | |
6036 | n->next = mri_control_label (); | |
6037 | n->bottom = mri_control_label (); | |
6038 | ||
6039 | n->outer = mri_control_stack; | |
6040 | mri_control_stack = n; | |
6041 | ||
6042 | return n; | |
6043 | } | |
6044 | ||
6045 | /* Pop off the stack of MRI structured control directives. */ | |
6046 | ||
6047 | static void | |
31302357 | 6048 | pop_mri_control (void) |
252b5132 RH |
6049 | { |
6050 | struct mri_control_info *n; | |
6051 | ||
6052 | n = mri_control_stack; | |
6053 | mri_control_stack = n->outer; | |
6054 | if (n->top != NULL) | |
6055 | free (n->top); | |
6056 | free (n->next); | |
6057 | free (n->bottom); | |
6058 | free (n); | |
6059 | } | |
6060 | ||
6061 | /* Recognize a condition code in an MRI structured control expression. */ | |
6062 | ||
6063 | static int | |
31302357 | 6064 | parse_mri_condition (int *pcc) |
252b5132 RH |
6065 | { |
6066 | char c1, c2; | |
6067 | ||
6068 | know (*input_line_pointer == '<'); | |
6069 | ||
6070 | ++input_line_pointer; | |
6071 | c1 = *input_line_pointer++; | |
6072 | c2 = *input_line_pointer++; | |
6073 | ||
6074 | if (*input_line_pointer != '>') | |
6075 | { | |
6076 | as_bad (_("syntax error in structured control directive")); | |
6077 | return 0; | |
6078 | } | |
6079 | ||
6080 | ++input_line_pointer; | |
6081 | SKIP_WHITESPACE (); | |
6082 | ||
3882b010 L |
6083 | c1 = TOLOWER (c1); |
6084 | c2 = TOLOWER (c2); | |
252b5132 RH |
6085 | |
6086 | *pcc = (c1 << 8) | c2; | |
6087 | ||
6088 | return 1; | |
6089 | } | |
6090 | ||
6091 | /* Parse a single operand in an MRI structured control expression. */ | |
6092 | ||
6093 | static int | |
31302357 AS |
6094 | parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, |
6095 | char **rightstart, char **rightstop) | |
252b5132 RH |
6096 | { |
6097 | char *s; | |
6098 | ||
6099 | SKIP_WHITESPACE (); | |
6100 | ||
6101 | *pcc = -1; | |
6102 | *leftstart = NULL; | |
6103 | *leftstop = NULL; | |
6104 | *rightstart = NULL; | |
6105 | *rightstop = NULL; | |
6106 | ||
6107 | if (*input_line_pointer == '<') | |
6108 | { | |
6109 | /* It's just a condition code. */ | |
6110 | return parse_mri_condition (pcc); | |
6111 | } | |
6112 | ||
6113 | /* Look ahead for the condition code. */ | |
6114 | for (s = input_line_pointer; *s != '\0'; ++s) | |
6115 | { | |
6116 | if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') | |
6117 | break; | |
6118 | } | |
6119 | if (*s == '\0') | |
6120 | { | |
6121 | as_bad (_("missing condition code in structured control directive")); | |
6122 | return 0; | |
6123 | } | |
6124 | ||
6125 | *leftstart = input_line_pointer; | |
6126 | *leftstop = s; | |
6127 | if (*leftstop > *leftstart | |
6128 | && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) | |
6129 | --*leftstop; | |
6130 | ||
6131 | input_line_pointer = s; | |
6132 | if (! parse_mri_condition (pcc)) | |
6133 | return 0; | |
6134 | ||
6135 | /* Look ahead for AND or OR or end of line. */ | |
6136 | for (s = input_line_pointer; *s != '\0'; ++s) | |
6137 | { | |
e1f44d10 NC |
6138 | /* We must make sure we don't misinterpret AND/OR at the end of labels! |
6139 | if d0 <eq> #FOOAND and d1 <ne> #BAROR then | |
6140 | ^^^ ^^ */ | |
8a104df9 KH |
6141 | if ((s == input_line_pointer |
6142 | || *(s-1) == ' ' | |
6143 | || *(s-1) == '\t') | |
6144 | && ((strncasecmp (s, "AND", 3) == 0 | |
6145 | && (s[3] == '.' || ! is_part_of_name (s[3]))) | |
6146 | || (strncasecmp (s, "OR", 2) == 0 | |
6147 | && (s[2] == '.' || ! is_part_of_name (s[2]))))) | |
6148 | break; | |
252b5132 RH |
6149 | } |
6150 | ||
6151 | *rightstart = input_line_pointer; | |
6152 | *rightstop = s; | |
6153 | if (*rightstop > *rightstart | |
6154 | && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) | |
6155 | --*rightstop; | |
6156 | ||
6157 | input_line_pointer = s; | |
6158 | ||
6159 | return 1; | |
6160 | } | |
6161 | ||
6162 | #define MCC(b1, b2) (((b1) << 8) | (b2)) | |
6163 | ||
6164 | /* Swap the sense of a condition. This changes the condition so that | |
6165 | it generates the same result when the operands are swapped. */ | |
6166 | ||
6167 | static int | |
31302357 | 6168 | swap_mri_condition (int cc) |
252b5132 RH |
6169 | { |
6170 | switch (cc) | |
6171 | { | |
6172 | case MCC ('h', 'i'): return MCC ('c', 's'); | |
6173 | case MCC ('l', 's'): return MCC ('c', 'c'); | |
36759679 | 6174 | /* <HS> is an alias for <CC>. */ |
e1f44d10 | 6175 | case MCC ('h', 's'): |
252b5132 | 6176 | case MCC ('c', 'c'): return MCC ('l', 's'); |
36759679 | 6177 | /* <LO> is an alias for <CS>. */ |
e1f44d10 | 6178 | case MCC ('l', 'o'): |
252b5132 RH |
6179 | case MCC ('c', 's'): return MCC ('h', 'i'); |
6180 | case MCC ('p', 'l'): return MCC ('m', 'i'); | |
6181 | case MCC ('m', 'i'): return MCC ('p', 'l'); | |
6182 | case MCC ('g', 'e'): return MCC ('l', 'e'); | |
6183 | case MCC ('l', 't'): return MCC ('g', 't'); | |
6184 | case MCC ('g', 't'): return MCC ('l', 't'); | |
6185 | case MCC ('l', 'e'): return MCC ('g', 'e'); | |
36759679 | 6186 | /* Issue a warning for conditions we can not swap. */ |
8fc4ee9b AM |
6187 | case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ |
6188 | case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ | |
e1f44d10 NC |
6189 | case MCC ('v', 'c'): |
6190 | case MCC ('v', 's'): | |
6191 | default : | |
6192 | as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), | |
6193 | (char) (cc >> 8), (char) (cc)); | |
6194 | break; | |
252b5132 RH |
6195 | } |
6196 | return cc; | |
6197 | } | |
6198 | ||
6199 | /* Reverse the sense of a condition. */ | |
6200 | ||
6201 | static int | |
31302357 | 6202 | reverse_mri_condition (int cc) |
252b5132 RH |
6203 | { |
6204 | switch (cc) | |
6205 | { | |
6206 | case MCC ('h', 'i'): return MCC ('l', 's'); | |
6207 | case MCC ('l', 's'): return MCC ('h', 'i'); | |
e1f44d10 NC |
6208 | /* <HS> is an alias for <CC> */ |
6209 | case MCC ('h', 's'): return MCC ('l', 'o'); | |
252b5132 | 6210 | case MCC ('c', 'c'): return MCC ('c', 's'); |
e1f44d10 NC |
6211 | /* <LO> is an alias for <CS> */ |
6212 | case MCC ('l', 'o'): return MCC ('h', 's'); | |
252b5132 RH |
6213 | case MCC ('c', 's'): return MCC ('c', 'c'); |
6214 | case MCC ('n', 'e'): return MCC ('e', 'q'); | |
6215 | case MCC ('e', 'q'): return MCC ('n', 'e'); | |
6216 | case MCC ('v', 'c'): return MCC ('v', 's'); | |
6217 | case MCC ('v', 's'): return MCC ('v', 'c'); | |
6218 | case MCC ('p', 'l'): return MCC ('m', 'i'); | |
6219 | case MCC ('m', 'i'): return MCC ('p', 'l'); | |
6220 | case MCC ('g', 'e'): return MCC ('l', 't'); | |
6221 | case MCC ('l', 't'): return MCC ('g', 'e'); | |
6222 | case MCC ('g', 't'): return MCC ('l', 'e'); | |
6223 | case MCC ('l', 'e'): return MCC ('g', 't'); | |
6224 | } | |
6225 | return cc; | |
6226 | } | |
6227 | ||
6228 | /* Build an MRI structured control expression. This generates test | |
6229 | and branch instructions. It goes to TRUELAB if the condition is | |
6230 | true, and to FALSELAB if the condition is false. Exactly one of | |
6231 | TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL | |
6232 | is the size qualifier for the expression. EXTENT is the size to | |
6233 | use for the branch. */ | |
6234 | ||
6235 | static void | |
31302357 AS |
6236 | build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, |
6237 | char *rightstart, char *rightstop, | |
6238 | const char *truelab, const char *falselab, | |
6239 | int extent) | |
252b5132 RH |
6240 | { |
6241 | char *buf; | |
6242 | char *s; | |
6243 | ||
6244 | if (leftstart != NULL) | |
6245 | { | |
6246 | struct m68k_op leftop, rightop; | |
6247 | char c; | |
6248 | ||
6249 | /* Swap the compare operands, if necessary, to produce a legal | |
6250 | m68k compare instruction. Comparing a register operand with | |
6251 | a non-register operand requires the register to be on the | |
6252 | right (cmp, cmpa). Comparing an immediate value with | |
6253 | anything requires the immediate value to be on the left | |
6254 | (cmpi). */ | |
6255 | ||
6256 | c = *leftstop; | |
6257 | *leftstop = '\0'; | |
6258 | (void) m68k_ip_op (leftstart, &leftop); | |
6259 | *leftstop = c; | |
6260 | ||
6261 | c = *rightstop; | |
6262 | *rightstop = '\0'; | |
6263 | (void) m68k_ip_op (rightstart, &rightop); | |
6264 | *rightstop = c; | |
6265 | ||
6266 | if (rightop.mode == IMMED | |
6267 | || ((leftop.mode == DREG || leftop.mode == AREG) | |
6268 | && (rightop.mode != DREG && rightop.mode != AREG))) | |
6269 | { | |
6270 | char *temp; | |
6271 | ||
31302357 AS |
6272 | /* Correct conditional handling: |
6273 | if #1 <lt> d0 then ;means if (1 < d0) | |
6274 | ... | |
6275 | endi | |
e1f44d10 | 6276 | |
31302357 | 6277 | should assemble to: |
e1f44d10 | 6278 | |
31302357 AS |
6279 | cmp #1,d0 if we do *not* swap the operands |
6280 | bgt true we need the swapped condition! | |
6281 | ble false | |
6282 | true: | |
6283 | ... | |
6284 | false: | |
6285 | */ | |
252b5132 RH |
6286 | temp = leftstart; |
6287 | leftstart = rightstart; | |
6288 | rightstart = temp; | |
6289 | temp = leftstop; | |
6290 | leftstop = rightstop; | |
6291 | rightstop = temp; | |
8a104df9 KH |
6292 | } |
6293 | else | |
6294 | { | |
e1f44d10 | 6295 | cc = swap_mri_condition (cc); |
252b5132 RH |
6296 | } |
6297 | } | |
6298 | ||
6299 | if (truelab == NULL) | |
6300 | { | |
6301 | cc = reverse_mri_condition (cc); | |
6302 | truelab = falselab; | |
6303 | } | |
92774660 | 6304 | |
252b5132 RH |
6305 | if (leftstart != NULL) |
6306 | { | |
6307 | buf = (char *) xmalloc (20 | |
6308 | + (leftstop - leftstart) | |
6309 | + (rightstop - rightstart)); | |
6310 | s = buf; | |
6311 | *s++ = 'c'; | |
6312 | *s++ = 'm'; | |
6313 | *s++ = 'p'; | |
6314 | if (qual != '\0') | |
3882b010 | 6315 | *s++ = TOLOWER (qual); |
252b5132 RH |
6316 | *s++ = ' '; |
6317 | memcpy (s, leftstart, leftstop - leftstart); | |
6318 | s += leftstop - leftstart; | |
6319 | *s++ = ','; | |
6320 | memcpy (s, rightstart, rightstop - rightstart); | |
6321 | s += rightstop - rightstart; | |
6322 | *s = '\0'; | |
6323 | mri_assemble (buf); | |
6324 | free (buf); | |
6325 | } | |
92774660 | 6326 | |
252b5132 RH |
6327 | buf = (char *) xmalloc (20 + strlen (truelab)); |
6328 | s = buf; | |
6329 | *s++ = 'b'; | |
6330 | *s++ = cc >> 8; | |
6331 | *s++ = cc & 0xff; | |
6332 | if (extent != '\0') | |
3882b010 | 6333 | *s++ = TOLOWER (extent); |
252b5132 RH |
6334 | *s++ = ' '; |
6335 | strcpy (s, truelab); | |
6336 | mri_assemble (buf); | |
6337 | free (buf); | |
6338 | } | |
6339 | ||
6340 | /* Parse an MRI structured control expression. This generates test | |
6341 | and branch instructions. STOP is where the expression ends. It | |
6342 | goes to TRUELAB if the condition is true, and to FALSELAB if the | |
6343 | condition is false. Exactly one of TRUELAB and FALSELAB will be | |
6344 | NULL, meaning to fall through. QUAL is the size qualifier for the | |
6345 | expression. EXTENT is the size to use for the branch. */ | |
6346 | ||
6347 | static void | |
31302357 AS |
6348 | parse_mri_control_expression (char *stop, int qual, const char *truelab, |
6349 | const char *falselab, int extent) | |
252b5132 RH |
6350 | { |
6351 | int c; | |
6352 | int cc; | |
6353 | char *leftstart; | |
6354 | char *leftstop; | |
6355 | char *rightstart; | |
6356 | char *rightstop; | |
6357 | ||
6358 | c = *stop; | |
6359 | *stop = '\0'; | |
6360 | ||
6361 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6362 | &rightstart, &rightstop)) | |
6363 | { | |
6364 | *stop = c; | |
6365 | return; | |
6366 | } | |
6367 | ||
6368 | if (strncasecmp (input_line_pointer, "AND", 3) == 0) | |
6369 | { | |
6370 | const char *flab; | |
6371 | ||
6372 | if (falselab != NULL) | |
6373 | flab = falselab; | |
6374 | else | |
6375 | flab = mri_control_label (); | |
6376 | ||
6377 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6378 | rightstop, (const char *) NULL, flab, extent); | |
6379 | ||
6380 | input_line_pointer += 3; | |
6381 | if (*input_line_pointer != '.' | |
6382 | || input_line_pointer[1] == '\0') | |
6383 | qual = '\0'; | |
6384 | else | |
6385 | { | |
6386 | qual = input_line_pointer[1]; | |
6387 | input_line_pointer += 2; | |
6388 | } | |
6389 | ||
6390 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6391 | &rightstart, &rightstop)) | |
6392 | { | |
6393 | *stop = c; | |
6394 | return; | |
6395 | } | |
6396 | ||
6397 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6398 | rightstop, truelab, falselab, extent); | |
6399 | ||
6400 | if (falselab == NULL) | |
6401 | colon (flab); | |
6402 | } | |
6403 | else if (strncasecmp (input_line_pointer, "OR", 2) == 0) | |
6404 | { | |
6405 | const char *tlab; | |
6406 | ||
6407 | if (truelab != NULL) | |
6408 | tlab = truelab; | |
6409 | else | |
6410 | tlab = mri_control_label (); | |
6411 | ||
6412 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6413 | rightstop, tlab, (const char *) NULL, extent); | |
6414 | ||
6415 | input_line_pointer += 2; | |
6416 | if (*input_line_pointer != '.' | |
6417 | || input_line_pointer[1] == '\0') | |
6418 | qual = '\0'; | |
6419 | else | |
6420 | { | |
6421 | qual = input_line_pointer[1]; | |
6422 | input_line_pointer += 2; | |
6423 | } | |
6424 | ||
6425 | if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, | |
6426 | &rightstart, &rightstop)) | |
6427 | { | |
6428 | *stop = c; | |
6429 | return; | |
6430 | } | |
6431 | ||
6432 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6433 | rightstop, truelab, falselab, extent); | |
6434 | ||
6435 | if (truelab == NULL) | |
6436 | colon (tlab); | |
6437 | } | |
6438 | else | |
6439 | { | |
6440 | build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, | |
6441 | rightstop, truelab, falselab, extent); | |
6442 | } | |
6443 | ||
6444 | *stop = c; | |
6445 | if (input_line_pointer != stop) | |
6446 | as_bad (_("syntax error in structured control directive")); | |
6447 | } | |
6448 | ||
6449 | /* Handle the MRI IF pseudo-op. This may be a structured control | |
6450 | directive, or it may be a regular assembler conditional, depending | |
6451 | on its operands. */ | |
6452 | ||
6453 | static void | |
31302357 | 6454 | s_mri_if (int qual) |
252b5132 RH |
6455 | { |
6456 | char *s; | |
6457 | int c; | |
6458 | struct mri_control_info *n; | |
6459 | ||
6460 | /* A structured control directive must end with THEN with an | |
6461 | optional qualifier. */ | |
6462 | s = input_line_pointer; | |
e1f44d10 NC |
6463 | /* We only accept '*' as introduction of comments if preceded by white space |
6464 | or at first column of a line (I think this can't actually happen here?) | |
6465 | This is important when assembling: | |
6466 | if d0 <ne> 12(a0,d0*2) then | |
36759679 | 6467 | if d0 <ne> #CONST*20 then. */ |
31302357 AS |
6468 | while (! (is_end_of_line[(unsigned char) *s] |
6469 | || (flag_mri | |
6470 | && *s == '*' | |
6471 | && (s == input_line_pointer | |
6472 | || *(s-1) == ' ' | |
6473 | || *(s-1) == '\t')))) | |
252b5132 RH |
6474 | ++s; |
6475 | --s; | |
6476 | while (s > input_line_pointer && (*s == ' ' || *s == '\t')) | |
6477 | --s; | |
6478 | ||
6479 | if (s - input_line_pointer > 1 | |
6480 | && s[-1] == '.') | |
6481 | s -= 2; | |
6482 | ||
6483 | if (s - input_line_pointer < 3 | |
6484 | || strncasecmp (s - 3, "THEN", 4) != 0) | |
6485 | { | |
6486 | if (qual != '\0') | |
6487 | { | |
6488 | as_bad (_("missing then")); | |
6489 | ignore_rest_of_line (); | |
6490 | return; | |
6491 | } | |
6492 | ||
6493 | /* It's a conditional. */ | |
6494 | s_if (O_ne); | |
6495 | return; | |
6496 | } | |
6497 | ||
6498 | /* Since this might be a conditional if, this pseudo-op will be | |
6499 | called even if we are supported to be ignoring input. Double | |
6500 | check now. Clobber *input_line_pointer so that ignore_input | |
6501 | thinks that this is not a special pseudo-op. */ | |
6502 | c = *input_line_pointer; | |
6503 | *input_line_pointer = 0; | |
6504 | if (ignore_input ()) | |
6505 | { | |
6506 | *input_line_pointer = c; | |
6507 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6508 | ++input_line_pointer; | |
6509 | demand_empty_rest_of_line (); | |
6510 | return; | |
6511 | } | |
6512 | *input_line_pointer = c; | |
6513 | ||
6514 | n = push_mri_control (mri_if); | |
6515 | ||
6516 | parse_mri_control_expression (s - 3, qual, (const char *) NULL, | |
6517 | n->next, s[1] == '.' ? s[2] : '\0'); | |
6518 | ||
6519 | if (s[1] == '.') | |
6520 | input_line_pointer = s + 3; | |
6521 | else | |
6522 | input_line_pointer = s + 1; | |
6523 | ||
6524 | if (flag_mri) | |
6525 | { | |
6526 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6527 | ++input_line_pointer; | |
6528 | } | |
6529 | ||
6530 | demand_empty_rest_of_line (); | |
6531 | } | |
6532 | ||
6533 | /* Handle the MRI else pseudo-op. If we are currently doing an MRI | |
6534 | structured IF, associate the ELSE with the IF. Otherwise, assume | |
6535 | it is a conditional else. */ | |
6536 | ||
6537 | static void | |
31302357 | 6538 | s_mri_else (int qual) |
252b5132 RH |
6539 | { |
6540 | int c; | |
6541 | char *buf; | |
6542 | char q[2]; | |
6543 | ||
6544 | if (qual == '\0' | |
6545 | && (mri_control_stack == NULL | |
6546 | || mri_control_stack->type != mri_if | |
6547 | || mri_control_stack->else_seen)) | |
6548 | { | |
6549 | s_else (0); | |
6550 | return; | |
6551 | } | |
6552 | ||
6553 | c = *input_line_pointer; | |
6554 | *input_line_pointer = 0; | |
6555 | if (ignore_input ()) | |
6556 | { | |
6557 | *input_line_pointer = c; | |
6558 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6559 | ++input_line_pointer; | |
6560 | demand_empty_rest_of_line (); | |
6561 | return; | |
6562 | } | |
6563 | *input_line_pointer = c; | |
6564 | ||
6565 | if (mri_control_stack == NULL | |
6566 | || mri_control_stack->type != mri_if | |
6567 | || mri_control_stack->else_seen) | |
6568 | { | |
6569 | as_bad (_("else without matching if")); | |
6570 | ignore_rest_of_line (); | |
6571 | return; | |
6572 | } | |
6573 | ||
6574 | mri_control_stack->else_seen = 1; | |
6575 | ||
6576 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom)); | |
3882b010 | 6577 | q[0] = TOLOWER (qual); |
252b5132 RH |
6578 | q[1] = '\0'; |
6579 | sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); | |
6580 | mri_assemble (buf); | |
6581 | free (buf); | |
6582 | ||
6583 | colon (mri_control_stack->next); | |
6584 | ||
6585 | if (flag_mri) | |
6586 | { | |
6587 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6588 | ++input_line_pointer; | |
6589 | } | |
6590 | ||
6591 | demand_empty_rest_of_line (); | |
6592 | } | |
6593 | ||
6594 | /* Handle the MRI ENDI pseudo-op. */ | |
6595 | ||
6596 | static void | |
31302357 | 6597 | s_mri_endi (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6598 | { |
6599 | if (mri_control_stack == NULL | |
6600 | || mri_control_stack->type != mri_if) | |
6601 | { | |
6602 | as_bad (_("endi without matching if")); | |
6603 | ignore_rest_of_line (); | |
6604 | return; | |
6605 | } | |
6606 | ||
6607 | /* ignore_input will not return true for ENDI, so we don't need to | |
6608 | worry about checking it again here. */ | |
6609 | ||
6610 | if (! mri_control_stack->else_seen) | |
6611 | colon (mri_control_stack->next); | |
6612 | colon (mri_control_stack->bottom); | |
6613 | ||
6614 | pop_mri_control (); | |
6615 | ||
6616 | if (flag_mri) | |
6617 | { | |
6618 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6619 | ++input_line_pointer; | |
6620 | } | |
6621 | ||
6622 | demand_empty_rest_of_line (); | |
6623 | } | |
6624 | ||
6625 | /* Handle the MRI BREAK pseudo-op. */ | |
6626 | ||
6627 | static void | |
31302357 | 6628 | s_mri_break (int extent) |
252b5132 RH |
6629 | { |
6630 | struct mri_control_info *n; | |
6631 | char *buf; | |
6632 | char ex[2]; | |
6633 | ||
6634 | n = mri_control_stack; | |
6635 | while (n != NULL | |
6636 | && n->type != mri_for | |
6637 | && n->type != mri_repeat | |
6638 | && n->type != mri_while) | |
6639 | n = n->outer; | |
6640 | if (n == NULL) | |
6641 | { | |
6642 | as_bad (_("break outside of structured loop")); | |
6643 | ignore_rest_of_line (); | |
6644 | return; | |
6645 | } | |
6646 | ||
6647 | buf = (char *) xmalloc (20 + strlen (n->bottom)); | |
3882b010 | 6648 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6649 | ex[1] = '\0'; |
6650 | sprintf (buf, "bra%s %s", ex, n->bottom); | |
6651 | mri_assemble (buf); | |
6652 | free (buf); | |
6653 | ||
6654 | if (flag_mri) | |
6655 | { | |
6656 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6657 | ++input_line_pointer; | |
6658 | } | |
6659 | ||
6660 | demand_empty_rest_of_line (); | |
6661 | } | |
6662 | ||
6663 | /* Handle the MRI NEXT pseudo-op. */ | |
6664 | ||
6665 | static void | |
31302357 | 6666 | s_mri_next (int extent) |
252b5132 RH |
6667 | { |
6668 | struct mri_control_info *n; | |
6669 | char *buf; | |
6670 | char ex[2]; | |
6671 | ||
6672 | n = mri_control_stack; | |
6673 | while (n != NULL | |
6674 | && n->type != mri_for | |
6675 | && n->type != mri_repeat | |
6676 | && n->type != mri_while) | |
6677 | n = n->outer; | |
6678 | if (n == NULL) | |
6679 | { | |
6680 | as_bad (_("next outside of structured loop")); | |
6681 | ignore_rest_of_line (); | |
6682 | return; | |
6683 | } | |
6684 | ||
6685 | buf = (char *) xmalloc (20 + strlen (n->next)); | |
3882b010 | 6686 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6687 | ex[1] = '\0'; |
6688 | sprintf (buf, "bra%s %s", ex, n->next); | |
6689 | mri_assemble (buf); | |
6690 | free (buf); | |
6691 | ||
6692 | if (flag_mri) | |
6693 | { | |
6694 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6695 | ++input_line_pointer; | |
6696 | } | |
6697 | ||
6698 | demand_empty_rest_of_line (); | |
6699 | } | |
6700 | ||
6701 | /* Handle the MRI FOR pseudo-op. */ | |
6702 | ||
6703 | static void | |
31302357 | 6704 | s_mri_for (int qual) |
252b5132 RH |
6705 | { |
6706 | const char *varstart, *varstop; | |
6707 | const char *initstart, *initstop; | |
6708 | const char *endstart, *endstop; | |
6709 | const char *bystart, *bystop; | |
6710 | int up; | |
6711 | int by; | |
6712 | int extent; | |
6713 | struct mri_control_info *n; | |
6714 | char *buf; | |
6715 | char *s; | |
6716 | char ex[2]; | |
6717 | ||
6718 | /* The syntax is | |
6719 | FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e | |
6720 | */ | |
6721 | ||
6722 | SKIP_WHITESPACE (); | |
6723 | varstart = input_line_pointer; | |
6724 | ||
6725 | /* Look for the '='. */ | |
6726 | while (! is_end_of_line[(unsigned char) *input_line_pointer] | |
6727 | && *input_line_pointer != '=') | |
6728 | ++input_line_pointer; | |
6729 | if (*input_line_pointer != '=') | |
6730 | { | |
6731 | as_bad (_("missing =")); | |
6732 | ignore_rest_of_line (); | |
6733 | return; | |
6734 | } | |
6735 | ||
6736 | varstop = input_line_pointer; | |
6737 | if (varstop > varstart | |
6738 | && (varstop[-1] == ' ' || varstop[-1] == '\t')) | |
6739 | --varstop; | |
6740 | ||
6741 | ++input_line_pointer; | |
6742 | ||
6743 | initstart = input_line_pointer; | |
6744 | ||
6745 | /* Look for TO or DOWNTO. */ | |
6746 | up = 1; | |
6747 | initstop = NULL; | |
6748 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6749 | { | |
6750 | if (strncasecmp (input_line_pointer, "TO", 2) == 0 | |
6751 | && ! is_part_of_name (input_line_pointer[2])) | |
6752 | { | |
6753 | initstop = input_line_pointer; | |
6754 | input_line_pointer += 2; | |
6755 | break; | |
6756 | } | |
6757 | if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 | |
6758 | && ! is_part_of_name (input_line_pointer[6])) | |
6759 | { | |
6760 | initstop = input_line_pointer; | |
6761 | up = 0; | |
6762 | input_line_pointer += 6; | |
6763 | break; | |
6764 | } | |
6765 | ++input_line_pointer; | |
6766 | } | |
6767 | if (initstop == NULL) | |
6768 | { | |
6769 | as_bad (_("missing to or downto")); | |
6770 | ignore_rest_of_line (); | |
6771 | return; | |
6772 | } | |
6773 | if (initstop > initstart | |
6774 | && (initstop[-1] == ' ' || initstop[-1] == '\t')) | |
6775 | --initstop; | |
6776 | ||
6777 | SKIP_WHITESPACE (); | |
6778 | endstart = input_line_pointer; | |
6779 | ||
6780 | /* Look for BY or DO. */ | |
6781 | by = 0; | |
6782 | endstop = NULL; | |
6783 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6784 | { | |
6785 | if (strncasecmp (input_line_pointer, "BY", 2) == 0 | |
6786 | && ! is_part_of_name (input_line_pointer[2])) | |
6787 | { | |
6788 | endstop = input_line_pointer; | |
6789 | by = 1; | |
6790 | input_line_pointer += 2; | |
6791 | break; | |
6792 | } | |
6793 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 | |
6794 | && (input_line_pointer[2] == '.' | |
6795 | || ! is_part_of_name (input_line_pointer[2]))) | |
6796 | { | |
6797 | endstop = input_line_pointer; | |
6798 | input_line_pointer += 2; | |
6799 | break; | |
6800 | } | |
6801 | ++input_line_pointer; | |
6802 | } | |
6803 | if (endstop == NULL) | |
6804 | { | |
6805 | as_bad (_("missing do")); | |
6806 | ignore_rest_of_line (); | |
6807 | return; | |
6808 | } | |
6809 | if (endstop > endstart | |
6810 | && (endstop[-1] == ' ' || endstop[-1] == '\t')) | |
6811 | --endstop; | |
6812 | ||
6813 | if (! by) | |
6814 | { | |
6815 | bystart = "#1"; | |
6816 | bystop = bystart + 2; | |
6817 | } | |
6818 | else | |
6819 | { | |
6820 | SKIP_WHITESPACE (); | |
6821 | bystart = input_line_pointer; | |
6822 | ||
6823 | /* Look for DO. */ | |
6824 | bystop = NULL; | |
6825 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6826 | { | |
6827 | if (strncasecmp (input_line_pointer, "DO", 2) == 0 | |
6828 | && (input_line_pointer[2] == '.' | |
6829 | || ! is_part_of_name (input_line_pointer[2]))) | |
6830 | { | |
6831 | bystop = input_line_pointer; | |
6832 | input_line_pointer += 2; | |
6833 | break; | |
6834 | } | |
6835 | ++input_line_pointer; | |
6836 | } | |
6837 | if (bystop == NULL) | |
6838 | { | |
6839 | as_bad (_("missing do")); | |
6840 | ignore_rest_of_line (); | |
6841 | return; | |
6842 | } | |
6843 | if (bystop > bystart | |
6844 | && (bystop[-1] == ' ' || bystop[-1] == '\t')) | |
6845 | --bystop; | |
6846 | } | |
6847 | ||
6848 | if (*input_line_pointer != '.') | |
6849 | extent = '\0'; | |
6850 | else | |
6851 | { | |
6852 | extent = input_line_pointer[1]; | |
6853 | input_line_pointer += 2; | |
6854 | } | |
6855 | ||
6856 | /* We have fully parsed the FOR operands. Now build the loop. */ | |
252b5132 RH |
6857 | n = push_mri_control (mri_for); |
6858 | ||
6859 | buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); | |
6860 | ||
36759679 | 6861 | /* Move init,var. */ |
252b5132 RH |
6862 | s = buf; |
6863 | *s++ = 'm'; | |
6864 | *s++ = 'o'; | |
6865 | *s++ = 'v'; | |
6866 | *s++ = 'e'; | |
6867 | if (qual != '\0') | |
3882b010 | 6868 | *s++ = TOLOWER (qual); |
252b5132 RH |
6869 | *s++ = ' '; |
6870 | memcpy (s, initstart, initstop - initstart); | |
6871 | s += initstop - initstart; | |
6872 | *s++ = ','; | |
6873 | memcpy (s, varstart, varstop - varstart); | |
6874 | s += varstop - varstart; | |
6875 | *s = '\0'; | |
6876 | mri_assemble (buf); | |
6877 | ||
6878 | colon (n->top); | |
6879 | ||
36759679 | 6880 | /* cmp end,var. */ |
252b5132 RH |
6881 | s = buf; |
6882 | *s++ = 'c'; | |
6883 | *s++ = 'm'; | |
6884 | *s++ = 'p'; | |
6885 | if (qual != '\0') | |
3882b010 | 6886 | *s++ = TOLOWER (qual); |
252b5132 RH |
6887 | *s++ = ' '; |
6888 | memcpy (s, endstart, endstop - endstart); | |
6889 | s += endstop - endstart; | |
6890 | *s++ = ','; | |
6891 | memcpy (s, varstart, varstop - varstart); | |
6892 | s += varstop - varstart; | |
6893 | *s = '\0'; | |
6894 | mri_assemble (buf); | |
6895 | ||
36759679 | 6896 | /* bcc bottom. */ |
3882b010 | 6897 | ex[0] = TOLOWER (extent); |
252b5132 RH |
6898 | ex[1] = '\0'; |
6899 | if (up) | |
6900 | sprintf (buf, "blt%s %s", ex, n->bottom); | |
6901 | else | |
6902 | sprintf (buf, "bgt%s %s", ex, n->bottom); | |
6903 | mri_assemble (buf); | |
6904 | ||
6905 | /* Put together the add or sub instruction used by ENDF. */ | |
6906 | s = buf; | |
6907 | if (up) | |
6908 | strcpy (s, "add"); | |
6909 | else | |
6910 | strcpy (s, "sub"); | |
6911 | s += 3; | |
6912 | if (qual != '\0') | |
3882b010 | 6913 | *s++ = TOLOWER (qual); |
252b5132 RH |
6914 | *s++ = ' '; |
6915 | memcpy (s, bystart, bystop - bystart); | |
6916 | s += bystop - bystart; | |
6917 | *s++ = ','; | |
6918 | memcpy (s, varstart, varstop - varstart); | |
6919 | s += varstop - varstart; | |
6920 | *s = '\0'; | |
6921 | n->incr = buf; | |
6922 | ||
6923 | if (flag_mri) | |
6924 | { | |
6925 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6926 | ++input_line_pointer; | |
6927 | } | |
6928 | ||
6929 | demand_empty_rest_of_line (); | |
6930 | } | |
6931 | ||
6932 | /* Handle the MRI ENDF pseudo-op. */ | |
6933 | ||
6934 | static void | |
31302357 | 6935 | s_mri_endf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6936 | { |
6937 | if (mri_control_stack == NULL | |
6938 | || mri_control_stack->type != mri_for) | |
6939 | { | |
6940 | as_bad (_("endf without for")); | |
6941 | ignore_rest_of_line (); | |
6942 | return; | |
6943 | } | |
6944 | ||
6945 | colon (mri_control_stack->next); | |
6946 | ||
6947 | mri_assemble (mri_control_stack->incr); | |
6948 | ||
6949 | sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); | |
6950 | mri_assemble (mri_control_stack->incr); | |
6951 | ||
6952 | free (mri_control_stack->incr); | |
6953 | ||
6954 | colon (mri_control_stack->bottom); | |
6955 | ||
6956 | pop_mri_control (); | |
6957 | ||
6958 | if (flag_mri) | |
6959 | { | |
6960 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6961 | ++input_line_pointer; | |
6962 | } | |
6963 | ||
6964 | demand_empty_rest_of_line (); | |
6965 | } | |
6966 | ||
6967 | /* Handle the MRI REPEAT pseudo-op. */ | |
6968 | ||
6969 | static void | |
31302357 | 6970 | s_mri_repeat (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6971 | { |
6972 | struct mri_control_info *n; | |
6973 | ||
6974 | n = push_mri_control (mri_repeat); | |
6975 | colon (n->top); | |
6976 | if (flag_mri) | |
6977 | { | |
6978 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6979 | ++input_line_pointer; | |
6980 | } | |
6981 | demand_empty_rest_of_line (); | |
6982 | } | |
6983 | ||
6984 | /* Handle the MRI UNTIL pseudo-op. */ | |
6985 | ||
6986 | static void | |
31302357 | 6987 | s_mri_until (int qual) |
252b5132 RH |
6988 | { |
6989 | char *s; | |
6990 | ||
6991 | if (mri_control_stack == NULL | |
6992 | || mri_control_stack->type != mri_repeat) | |
6993 | { | |
6994 | as_bad (_("until without repeat")); | |
6995 | ignore_rest_of_line (); | |
6996 | return; | |
6997 | } | |
6998 | ||
6999 | colon (mri_control_stack->next); | |
7000 | ||
7001 | for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) | |
7002 | ; | |
7003 | ||
7004 | parse_mri_control_expression (s, qual, (const char *) NULL, | |
7005 | mri_control_stack->top, '\0'); | |
7006 | ||
7007 | colon (mri_control_stack->bottom); | |
7008 | ||
7009 | input_line_pointer = s; | |
7010 | ||
7011 | pop_mri_control (); | |
7012 | ||
7013 | if (flag_mri) | |
7014 | { | |
7015 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7016 | ++input_line_pointer; | |
7017 | } | |
7018 | ||
7019 | demand_empty_rest_of_line (); | |
7020 | } | |
7021 | ||
7022 | /* Handle the MRI WHILE pseudo-op. */ | |
7023 | ||
7024 | static void | |
31302357 | 7025 | s_mri_while (int qual) |
252b5132 RH |
7026 | { |
7027 | char *s; | |
7028 | ||
7029 | struct mri_control_info *n; | |
7030 | ||
7031 | s = input_line_pointer; | |
e1f44d10 NC |
7032 | /* We only accept '*' as introduction of comments if preceded by white space |
7033 | or at first column of a line (I think this can't actually happen here?) | |
7034 | This is important when assembling: | |
7035 | while d0 <ne> 12(a0,d0*2) do | |
36759679 | 7036 | while d0 <ne> #CONST*20 do. */ |
8a104df9 KH |
7037 | while (! (is_end_of_line[(unsigned char) *s] |
7038 | || (flag_mri | |
7039 | && *s == '*' | |
7040 | && (s == input_line_pointer | |
7041 | || *(s-1) == ' ' | |
7042 | || *(s-1) == '\t')))) | |
252b5132 RH |
7043 | s++; |
7044 | --s; | |
7045 | while (*s == ' ' || *s == '\t') | |
7046 | --s; | |
7047 | if (s - input_line_pointer > 1 | |
7048 | && s[-1] == '.') | |
7049 | s -= 2; | |
7050 | if (s - input_line_pointer < 2 | |
7051 | || strncasecmp (s - 1, "DO", 2) != 0) | |
7052 | { | |
7053 | as_bad (_("missing do")); | |
7054 | ignore_rest_of_line (); | |
7055 | return; | |
7056 | } | |
7057 | ||
7058 | n = push_mri_control (mri_while); | |
7059 | ||
7060 | colon (n->next); | |
7061 | ||
7062 | parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, | |
7063 | s[1] == '.' ? s[2] : '\0'); | |
7064 | ||
7065 | input_line_pointer = s + 1; | |
7066 | if (*input_line_pointer == '.') | |
7067 | input_line_pointer += 2; | |
7068 | ||
7069 | if (flag_mri) | |
7070 | { | |
7071 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7072 | ++input_line_pointer; | |
7073 | } | |
7074 | ||
7075 | demand_empty_rest_of_line (); | |
7076 | } | |
7077 | ||
7078 | /* Handle the MRI ENDW pseudo-op. */ | |
7079 | ||
7080 | static void | |
31302357 | 7081 | s_mri_endw (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
7082 | { |
7083 | char *buf; | |
7084 | ||
7085 | if (mri_control_stack == NULL | |
7086 | || mri_control_stack->type != mri_while) | |
7087 | { | |
7088 | as_bad (_("endw without while")); | |
7089 | ignore_rest_of_line (); | |
7090 | return; | |
7091 | } | |
7092 | ||
7093 | buf = (char *) xmalloc (20 + strlen (mri_control_stack->next)); | |
7094 | sprintf (buf, "bra %s", mri_control_stack->next); | |
7095 | mri_assemble (buf); | |
7096 | free (buf); | |
7097 | ||
7098 | colon (mri_control_stack->bottom); | |
7099 | ||
7100 | pop_mri_control (); | |
7101 | ||
7102 | if (flag_mri) | |
7103 | { | |
7104 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
7105 | ++input_line_pointer; | |
7106 | } | |
7107 | ||
7108 | demand_empty_rest_of_line (); | |
7109 | } | |
7110 | \f | |
266abb8f NS |
7111 | /* Parse a .cpu directive. */ |
7112 | ||
7113 | static void | |
7114 | s_m68k_cpu (int ignored ATTRIBUTE_UNUSED) | |
7115 | { | |
7116 | char saved_char; | |
7117 | char *name; | |
7118 | ||
7119 | if (initialized) | |
7120 | { | |
7121 | as_bad (_("already assembled instructions")); | |
7122 | ignore_rest_of_line (); | |
7123 | return; | |
7124 | } | |
7125 | ||
7126 | name = input_line_pointer; | |
7127 | while (*input_line_pointer && !ISSPACE(*input_line_pointer)) | |
7128 | input_line_pointer++; | |
7129 | saved_char = *input_line_pointer; | |
7130 | *input_line_pointer = 0; | |
7131 | ||
7132 | m68k_set_cpu (name, 1, 0); | |
7133 | ||
7134 | *input_line_pointer = saved_char; | |
7135 | demand_empty_rest_of_line (); | |
7136 | return; | |
7137 | } | |
7138 | ||
7139 | /* Parse a .arch directive. */ | |
7140 | ||
7141 | static void | |
7142 | s_m68k_arch (int ignored ATTRIBUTE_UNUSED) | |
7143 | { | |
7144 | char saved_char; | |
7145 | char *name; | |
7146 | ||
7147 | if (initialized) | |
7148 | { | |
7149 | as_bad (_("already assembled instructions")); | |
7150 | ignore_rest_of_line (); | |
7151 | return; | |
7152 | } | |
7153 | ||
7154 | name = input_line_pointer; | |
7155 | while (*input_line_pointer && *input_line_pointer != ',' | |
7156 | && !ISSPACE (*input_line_pointer)) | |
7157 | input_line_pointer++; | |
7158 | saved_char = *input_line_pointer; | |
7159 | *input_line_pointer = 0; | |
7160 | ||
7161 | if (m68k_set_arch (name, 1, 0)) | |
7162 | { | |
7163 | /* Scan extensions. */ | |
7164 | do | |
7165 | { | |
7166 | *input_line_pointer++ = saved_char; | |
7167 | if (!*input_line_pointer || ISSPACE (*input_line_pointer)) | |
7168 | break; | |
7169 | name = input_line_pointer; | |
7170 | while (*input_line_pointer && *input_line_pointer != ',' | |
7171 | && !ISSPACE (*input_line_pointer)) | |
7172 | input_line_pointer++; | |
7173 | saved_char = *input_line_pointer; | |
7174 | *input_line_pointer = 0; | |
7175 | } | |
7176 | while (m68k_set_extension (name, 1, 0)); | |
7177 | } | |
7178 | ||
7179 | *input_line_pointer = saved_char; | |
7180 | demand_empty_rest_of_line (); | |
7181 | return; | |
7182 | } | |
7183 | \f | |
7184 | /* Lookup a cpu name in TABLE and return the slot found. Return NULL | |
7185 | if none is found, the caller is responsible for emitting an error | |
7186 | message. If ALLOW_M is non-zero, we allow an initial 'm' on the | |
7187 | cpu name, if it begins with a '6' (possibly skipping an intervening | |
7188 | 'c'. We also allow a 'c' in the same place. if NEGATED is | |
7189 | non-zero, we accept a leading 'no-' and *NEGATED is set to true, if | |
7190 | the option is indeed negated. */ | |
7191 | ||
7192 | static const struct m68k_cpu * | |
7193 | m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table, | |
7194 | int allow_m, int *negated) | |
7195 | { | |
7196 | /* allow negated value? */ | |
7197 | if (negated) | |
7198 | { | |
7199 | *negated = 0; | |
7200 | ||
7201 | if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') | |
7202 | { | |
7203 | arg += 3; | |
7204 | *negated = 1; | |
7205 | } | |
7206 | } | |
7207 | ||
7208 | /* Remove 'm' or 'mc' prefix from 68k variants. */ | |
7209 | if (allow_m) | |
7210 | { | |
7211 | if (arg[0] == 'm') | |
7212 | { | |
7213 | if (arg[1] == '6') | |
7214 | arg += 1; | |
7215 | else if (arg[1] == 'c' && arg[2] == '6') | |
7216 | arg += 2; | |
7217 | } | |
7218 | } | |
7219 | else if (arg[0] == 'c' && arg[1] == '6') | |
7220 | arg += 1; | |
7221 | ||
7222 | for (; table->name; table++) | |
7223 | if (!strcmp (arg, table->name)) | |
2da12c60 NS |
7224 | { |
7225 | if (table->alias < -1 || table->alias > 1) | |
7226 | as_bad (_("`%s' is deprecated, use `%s'"), | |
7227 | table->name, table[table->alias < 0 ? 1 : -1].name); | |
7228 | return table; | |
7229 | } | |
266abb8f NS |
7230 | return 0; |
7231 | } | |
7232 | ||
bfbba8e4 | 7233 | /* Set the cpu, issuing errors if it is unrecognized. */ |
266abb8f NS |
7234 | |
7235 | static int | |
7236 | m68k_set_cpu (char const *name, int allow_m, int silent) | |
7237 | { | |
7238 | const struct m68k_cpu *cpu; | |
7239 | ||
7240 | cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL); | |
7241 | ||
7242 | if (!cpu) | |
7243 | { | |
7244 | if (!silent) | |
7245 | as_bad (_("cpu `%s' unrecognized"), name); | |
7246 | return 0; | |
7247 | } | |
266abb8f NS |
7248 | selected_cpu = cpu; |
7249 | return 1; | |
7250 | } | |
7251 | ||
bfbba8e4 | 7252 | /* Set the architecture, issuing errors if it is unrecognized. */ |
266abb8f NS |
7253 | |
7254 | static int | |
7255 | m68k_set_arch (char const *name, int allow_m, int silent) | |
7256 | { | |
7257 | const struct m68k_cpu *arch; | |
7258 | ||
7259 | arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL); | |
7260 | ||
7261 | if (!arch) | |
7262 | { | |
7263 | if (!silent) | |
7264 | as_bad (_("architecture `%s' unrecognized"), name); | |
7265 | return 0; | |
7266 | } | |
266abb8f NS |
7267 | selected_arch = arch; |
7268 | return 1; | |
7269 | } | |
7270 | ||
7271 | /* Set the architecture extension, issuing errors if it is | |
7272 | unrecognized, or invalid */ | |
7273 | ||
7274 | static int | |
7275 | m68k_set_extension (char const *name, int allow_m, int silent) | |
7276 | { | |
7277 | int negated; | |
7278 | const struct m68k_cpu *ext; | |
7279 | ||
7280 | ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated); | |
7281 | ||
7282 | if (!ext) | |
7283 | { | |
7284 | if (!silent) | |
7285 | as_bad (_("extension `%s' unrecognized"), name); | |
7286 | return 0; | |
7287 | } | |
7288 | ||
7289 | if (negated) | |
7290 | not_current_architecture |= ext->arch; | |
7291 | else | |
7292 | current_architecture |= ext->arch; | |
7293 | return 1; | |
7294 | } | |
7295 | ||
31302357 AS |
7296 | /* md_parse_option |
7297 | Invocation line includes a switch not recognized by the base assembler. | |
266abb8f | 7298 | */ |
252b5132 RH |
7299 | |
7300 | #ifdef OBJ_ELF | |
5a38dc70 | 7301 | const char *md_shortopts = "lSA:m:kQ:V"; |
252b5132 | 7302 | #else |
5a38dc70 | 7303 | const char *md_shortopts = "lSA:m:k"; |
252b5132 RH |
7304 | #endif |
7305 | ||
7306 | struct option md_longopts[] = { | |
7307 | #define OPTION_PIC (OPTION_MD_BASE) | |
7308 | {"pic", no_argument, NULL, OPTION_PIC}, | |
7309 | #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) | |
7310 | {"register-prefix-optional", no_argument, NULL, | |
7311 | OPTION_REGISTER_PREFIX_OPTIONAL}, | |
7312 | #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) | |
7313 | {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, | |
7314 | #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) | |
7315 | {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, | |
7316 | #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) | |
7317 | {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, | |
7318 | #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) | |
7319 | {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, | |
7320 | #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) | |
7321 | {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, | |
28e7409f NC |
7322 | #define OPTION_PCREL (OPTION_MD_BASE + 7) |
7323 | {"pcrel", no_argument, NULL, OPTION_PCREL}, | |
252b5132 RH |
7324 | {NULL, no_argument, NULL, 0} |
7325 | }; | |
bc805888 | 7326 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
7327 | |
7328 | int | |
31302357 | 7329 | md_parse_option (int c, char *arg) |
252b5132 RH |
7330 | { |
7331 | switch (c) | |
7332 | { | |
7333 | case 'l': /* -l means keep external to 2 bit offset | |
36759679 | 7334 | rather than 16 bit one. */ |
252b5132 RH |
7335 | flag_short_refs = 1; |
7336 | break; | |
7337 | ||
7338 | case 'S': /* -S means that jbsr's always turn into | |
7339 | jsr's. */ | |
7340 | flag_long_jumps = 1; | |
7341 | break; | |
7342 | ||
28e7409f NC |
7343 | case OPTION_PCREL: /* --pcrel means never turn PC-relative |
7344 | branches into absolute jumps. */ | |
7345 | flag_keep_pcrel = 1; | |
7346 | break; | |
7347 | ||
252b5132 RH |
7348 | case OPTION_PIC: |
7349 | case 'k': | |
7350 | flag_want_pic = 1; | |
36759679 | 7351 | break; /* -pic, Position Independent Code. */ |
252b5132 RH |
7352 | |
7353 | case OPTION_REGISTER_PREFIX_OPTIONAL: | |
7354 | flag_reg_prefix_optional = 1; | |
7355 | reg_prefix_optional_seen = 1; | |
7356 | break; | |
7357 | ||
7358 | /* -V: SVR4 argument to print version ID. */ | |
7359 | case 'V': | |
7360 | print_version_id (); | |
7361 | break; | |
7362 | ||
7363 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
7364 | should be emitted or not. FIXME: Not implemented. */ | |
7365 | case 'Q': | |
7366 | break; | |
7367 | ||
7368 | case OPTION_BITWISE_OR: | |
7369 | { | |
7370 | char *n, *t; | |
7371 | const char *s; | |
7372 | ||
7373 | n = (char *) xmalloc (strlen (m68k_comment_chars) + 1); | |
7374 | t = n; | |
7375 | for (s = m68k_comment_chars; *s != '\0'; s++) | |
7376 | if (*s != '|') | |
7377 | *t++ = *s; | |
7378 | *t = '\0'; | |
7379 | m68k_comment_chars = n; | |
7380 | } | |
7381 | break; | |
7382 | ||
7383 | case OPTION_BASE_SIZE_DEFAULT_16: | |
7384 | m68k_index_width_default = SIZE_WORD; | |
7385 | break; | |
7386 | ||
7387 | case OPTION_BASE_SIZE_DEFAULT_32: | |
7388 | m68k_index_width_default = SIZE_LONG; | |
7389 | break; | |
7390 | ||
7391 | case OPTION_DISP_SIZE_DEFAULT_16: | |
7392 | m68k_rel32 = 0; | |
7393 | m68k_rel32_from_cmdline = 1; | |
7394 | break; | |
7395 | ||
7396 | case OPTION_DISP_SIZE_DEFAULT_32: | |
7397 | m68k_rel32 = 1; | |
7398 | m68k_rel32_from_cmdline = 1; | |
7399 | break; | |
7400 | ||
266abb8f NS |
7401 | case 'A': |
7402 | #if WARN_DEPRECATED | |
7403 | as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'", | |
7404 | arg, arg)); | |
7405 | #endif | |
7406 | /* Intentional fall-through. */ | |
7407 | case 'm': | |
7408 | if (!strncmp (arg, "arch=", 5)) | |
7409 | m68k_set_arch (arg + 5, 1, 0); | |
7410 | else if (!strncmp (arg, "cpu=", 4)) | |
7411 | m68k_set_cpu (arg + 4, 1, 0); | |
7412 | else if (m68k_set_extension (arg, 0, 1)) | |
7413 | ; | |
0b2e31dc NS |
7414 | else if (m68k_set_arch (arg, 0, 1)) |
7415 | ; | |
266abb8f NS |
7416 | else if (m68k_set_cpu (arg, 0, 1)) |
7417 | ; | |
7418 | else | |
7419 | return 0; | |
7420 | break; | |
7421 | ||
252b5132 RH |
7422 | default: |
7423 | return 0; | |
7424 | } | |
7425 | ||
7426 | return 1; | |
7427 | } | |
7428 | ||
266abb8f NS |
7429 | /* Setup tables from the selected arch and/or cpu */ |
7430 | ||
7431 | static void | |
7432 | m68k_init_arch (void) | |
7433 | { | |
266abb8f NS |
7434 | if (not_current_architecture & current_architecture) |
7435 | { | |
7436 | as_bad (_("architecture features both enabled and disabled")); | |
7437 | not_current_architecture &= ~current_architecture; | |
7438 | } | |
7439 | if (selected_arch) | |
2da12c60 NS |
7440 | { |
7441 | current_architecture |= selected_arch->arch; | |
7442 | control_regs = selected_arch->control_regs; | |
7443 | } | |
0b2e31dc NS |
7444 | else |
7445 | current_architecture |= selected_cpu->arch; | |
0b2e31dc | 7446 | |
2da12c60 NS |
7447 | current_architecture &= ~not_current_architecture; |
7448 | ||
377260ba NS |
7449 | if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881)) |
7450 | { | |
7451 | /* Determine which float is really meant. */ | |
7452 | if (current_architecture & (m68k_mask & ~m68881)) | |
7453 | current_architecture ^= cfloat; | |
7454 | else | |
7455 | current_architecture ^= m68881; | |
7456 | } | |
7457 | ||
0b2e31dc | 7458 | if (selected_cpu) |
266abb8f | 7459 | { |
2da12c60 | 7460 | control_regs = selected_cpu->control_regs; |
0b2e31dc | 7461 | if (current_architecture & ~selected_cpu->arch) |
266abb8f | 7462 | { |
0b2e31dc NS |
7463 | as_bad (_("selected processor does not have all features of selected architecture")); |
7464 | current_architecture | |
7465 | = selected_cpu->arch & ~not_current_architecture; | |
266abb8f NS |
7466 | } |
7467 | } | |
266abb8f | 7468 | |
266abb8f NS |
7469 | if ((current_architecture & m68k_mask) |
7470 | && (current_architecture & ~m68k_mask)) | |
7471 | { | |
7472 | as_bad (_ ("m68k and cf features both selected")); | |
0b2e31dc | 7473 | if (current_architecture & m68k_mask) |
266abb8f NS |
7474 | current_architecture &= m68k_mask; |
7475 | else | |
7476 | current_architecture &= ~m68k_mask; | |
7477 | } | |
7478 | ||
7479 | /* Permit m68881 specification with all cpus; those that can't work | |
7480 | with a coprocessor could be doing emulation. */ | |
7481 | if (current_architecture & m68851) | |
7482 | { | |
7483 | if (current_architecture & m68040) | |
7484 | as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); | |
7485 | } | |
7486 | /* What other incompatibilities could we check for? */ | |
7487 | ||
266abb8f NS |
7488 | if (cpu_of_arch (current_architecture) < m68020 |
7489 | || arch_coldfire_p (current_architecture)) | |
7490 | md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; | |
7491 | ||
7492 | initialized = 1; | |
7493 | } | |
7494 | ||
252b5132 | 7495 | void |
31302357 | 7496 | md_show_usage (FILE *stream) |
252b5132 | 7497 | { |
76f57f3a | 7498 | const char *default_cpu = TARGET_CPU; |
f1f5ef86 AM |
7499 | int i; |
7500 | unsigned int default_arch; | |
76f57f3a | 7501 | |
8a104df9 | 7502 | /* Get the canonical name for the default target CPU. */ |
76f57f3a JT |
7503 | if (*default_cpu == 'm') |
7504 | default_cpu++; | |
266abb8f | 7505 | for (i = 0; m68k_cpus[i].name; i++) |
76f57f3a | 7506 | { |
266abb8f | 7507 | if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0) |
76f57f3a | 7508 | { |
266abb8f | 7509 | default_arch = m68k_cpus[i].arch; |
2da12c60 NS |
7510 | while (m68k_cpus[i].alias > 0) |
7511 | i--; | |
7512 | while (m68k_cpus[i].alias < 0) | |
7513 | i++; | |
7514 | default_cpu = m68k_cpus[i].name; | |
76f57f3a JT |
7515 | } |
7516 | } | |
7517 | ||
bc805888 | 7518 | fprintf (stream, _("\ |
266abb8f NS |
7519 | -march=<arch> set architecture\n\ |
7520 | -mcpu=<cpu> set cpu [default %s]\n\ | |
7521 | "), default_cpu); | |
7522 | for (i = 0; m68k_extensions[i].name; i++) | |
7523 | fprintf (stream, _("\ | |
0b2e31dc NS |
7524 | -m[no-]%-16s enable/disable%s architecture extension\n\ |
7525 | "), m68k_extensions[i].name, | |
7526 | m68k_extensions[i].alias > 0 ? " ColdFire" | |
7527 | : m68k_extensions[i].alias < 0 ? " m68k" : ""); | |
266abb8f | 7528 | |
bc805888 | 7529 | fprintf (stream, _("\ |
266abb8f | 7530 | -l use 1 word for refs to undefined symbols [default 2]\n\ |
252b5132 RH |
7531 | -pic, -k generate position independent code\n\ |
7532 | -S turn jbsr into jsr\n\ | |
28e7409f | 7533 | --pcrel never turn PC-relative branches into absolute jumps\n\ |
252b5132 RH |
7534 | --register-prefix-optional\n\ |
7535 | recognize register names without prefix character\n\ | |
266abb8f | 7536 | --bitwise-or do not treat `|' as a comment character\n\ |
252b5132 RH |
7537 | --base-size-default-16 base reg without size is 16 bits\n\ |
7538 | --base-size-default-32 base reg without size is 32 bits (default)\n\ | |
7539 | --disp-size-default-16 displacement with unknown size is 16 bits\n\ | |
266abb8f NS |
7540 | --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ |
7541 | ")); | |
7542 | ||
7543 | fprintf (stream, _("Architecture variants are: ")); | |
7544 | for (i = 0; m68k_archs[i].name; i++) | |
7545 | { | |
7546 | if (i) | |
7547 | fprintf (stream, " | "); | |
7548 | fprintf (stream, m68k_archs[i].name); | |
7549 | } | |
7550 | fprintf (stream, "\n"); | |
7551 | ||
7552 | fprintf (stream, _("Processor variants are: ")); | |
7553 | for (i = 0; m68k_cpus[i].name; i++) | |
7554 | { | |
7555 | if (i) | |
7556 | fprintf (stream, " | "); | |
7557 | fprintf (stream, m68k_cpus[i].name); | |
7558 | } | |
7559 | fprintf (stream, _("\n")); | |
252b5132 RH |
7560 | } |
7561 | \f | |
7562 | #ifdef TEST2 | |
7563 | ||
7564 | /* TEST2: Test md_assemble() */ | |
36759679 NC |
7565 | /* Warning, this routine probably doesn't work anymore. */ |
7566 | int | |
31302357 | 7567 | main (void) |
252b5132 RH |
7568 | { |
7569 | struct m68k_it the_ins; | |
7570 | char buf[120]; | |
7571 | char *cp; | |
7572 | int n; | |
7573 | ||
7574 | m68k_ip_begin (); | |
7575 | for (;;) | |
7576 | { | |
7577 | if (!gets (buf) || !*buf) | |
7578 | break; | |
7579 | if (buf[0] == '|' || buf[1] == '.') | |
7580 | continue; | |
7581 | for (cp = buf; *cp; cp++) | |
7582 | if (*cp == '\t') | |
7583 | *cp = ' '; | |
7584 | if (is_label (buf)) | |
7585 | continue; | |
7586 | memset (&the_ins, '\0', sizeof (the_ins)); | |
7587 | m68k_ip (&the_ins, buf); | |
7588 | if (the_ins.error) | |
7589 | { | |
7590 | printf (_("Error %s in %s\n"), the_ins.error, buf); | |
7591 | } | |
7592 | else | |
7593 | { | |
7594 | printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); | |
7595 | for (n = 0; n < the_ins.numo; n++) | |
7596 | printf (" 0x%x", the_ins.opcode[n] & 0xffff); | |
7597 | printf (" "); | |
7598 | print_the_insn (&the_ins.opcode[0], stdout); | |
7599 | (void) putchar ('\n'); | |
7600 | } | |
7601 | for (n = 0; n < strlen (the_ins.args) / 2; n++) | |
7602 | { | |
7603 | if (the_ins.operands[n].error) | |
7604 | { | |
7605 | printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); | |
7606 | continue; | |
7607 | } | |
31302357 AS |
7608 | printf ("mode %d, reg %d, ", the_ins.operands[n].mode, |
7609 | the_ins.operands[n].reg); | |
252b5132 | 7610 | if (the_ins.operands[n].b_const) |
31302357 AS |
7611 | printf ("Constant: '%.*s', ", |
7612 | 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, | |
7613 | the_ins.operands[n].b_const); | |
7614 | printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, | |
7615 | the_ins.operands[n].isiz, the_ins.operands[n].imul); | |
252b5132 | 7616 | if (the_ins.operands[n].b_iadd) |
31302357 AS |
7617 | printf ("Iadd: '%.*s',", |
7618 | 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, | |
7619 | the_ins.operands[n].b_iadd); | |
7620 | putchar ('\n'); | |
252b5132 RH |
7621 | } |
7622 | } | |
7623 | m68k_ip_end (); | |
7624 | return 0; | |
7625 | } | |
7626 | ||
31302357 AS |
7627 | int |
7628 | is_label (char *str) | |
252b5132 RH |
7629 | { |
7630 | while (*str == ' ') | |
7631 | str++; | |
7632 | while (*str && *str != ' ') | |
7633 | str++; | |
7634 | if (str[-1] == ':' || str[1] == '=') | |
7635 | return 1; | |
7636 | return 0; | |
7637 | } | |
7638 | ||
7639 | #endif | |
7640 | ||
7641 | /* Possible states for relaxation: | |
7642 | ||
7643 | 0 0 branch offset byte (bra, etc) | |
7644 | 0 1 word | |
7645 | 0 2 long | |
7646 | ||
7647 | 1 0 indexed offsets byte a0@(32,d4:w:1) etc | |
7648 | 1 1 word | |
7649 | 1 2 long | |
7650 | ||
7651 | 2 0 two-offset index word-word a0@(32,d4)@(45) etc | |
7652 | 2 1 word-long | |
7653 | 2 2 long-word | |
7654 | 2 3 long-long | |
7655 | ||
7656 | */ | |
7657 | ||
7658 | /* We have no need to default values of symbols. */ | |
7659 | ||
252b5132 | 7660 | symbolS * |
31302357 | 7661 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
7662 | { |
7663 | return 0; | |
7664 | } | |
7665 | ||
7666 | /* Round up a section size to the appropriate boundary. */ | |
7667 | valueT | |
31302357 | 7668 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
7669 | { |
7670 | #ifdef OBJ_AOUT | |
252b5132 RH |
7671 | /* For a.out, force the section size to be aligned. If we don't do |
7672 | this, BFD will align it for us, but it will not write out the | |
7673 | final bytes of the section. This may be a bug in BFD, but it is | |
7674 | easier to fix it here since that is how the other a.out targets | |
7675 | work. */ | |
7676 | int align; | |
7677 | ||
7678 | align = bfd_get_section_alignment (stdoutput, segment); | |
7679 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
252b5132 RH |
7680 | #endif |
7681 | ||
7682 | return size; | |
7683 | } | |
7684 | ||
7685 | /* Exactly what point is a PC-relative offset relative TO? | |
7686 | On the 68k, it is relative to the address of the first extension | |
7687 | word. The difference between the addresses of the offset and the | |
92774660 | 7688 | first extension word is stored in fx_pcrel_adjust. */ |
252b5132 | 7689 | long |
31302357 | 7690 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
7691 | { |
7692 | int adjust; | |
7693 | ||
8390138c AS |
7694 | /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly |
7695 | sign extend the value here. */ | |
7696 | adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80; | |
252b5132 RH |
7697 | if (adjust == 64) |
7698 | adjust = -1; | |
7699 | return fixP->fx_where + fixP->fx_frag->fr_address - adjust; | |
7700 | } | |
7701 | ||
0d96863f | 7702 | #ifdef OBJ_ELF |
8a104df9 | 7703 | void |
31302357 | 7704 | m68k_elf_final_processing (void) |
0d96863f | 7705 | { |
266abb8f NS |
7706 | unsigned flags = 0; |
7707 | ||
238d258f | 7708 | if (arch_coldfire_fpu (current_architecture)) |
266abb8f NS |
7709 | flags |= EF_M68K_CFV4E; |
7710 | /* Set file-specific flags if this is a cpu32 processor. */ | |
8a104df9 | 7711 | if (cpu_of_arch (current_architecture) & cpu32) |
3bdcfdf4 KH |
7712 | flags |= EF_M68K_CPU32; |
7713 | else if (cpu_of_arch (current_architecture) & fido_a) | |
7714 | flags |= EF_M68K_FIDO; | |
8a104df9 KH |
7715 | else if ((cpu_of_arch (current_architecture) & m68000up) |
7716 | && !(cpu_of_arch (current_architecture) & m68020up)) | |
266abb8f NS |
7717 | flags |= EF_M68K_M68000; |
7718 | ||
7719 | if (current_architecture & mcfisa_a) | |
7720 | { | |
0b2e31dc NS |
7721 | static const unsigned isa_features[][2] = |
7722 | { | |
9a2e615a | 7723 | {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, |
c694fd50 | 7724 | {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, |
9a2e615a | 7725 | {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, |
c694fd50 KH |
7726 | {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, |
7727 | {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, | |
9a2e615a | 7728 | {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, |
8d100c32 | 7729 | {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp}, |
0b2e31dc NS |
7730 | {0,0}, |
7731 | }; | |
7732 | static const unsigned mac_features[][2] = | |
7733 | { | |
c694fd50 KH |
7734 | {EF_M68K_CF_MAC, mcfmac}, |
7735 | {EF_M68K_CF_EMAC, mcfemac}, | |
0b2e31dc NS |
7736 | {0,0}, |
7737 | }; | |
7738 | unsigned ix; | |
7739 | unsigned pattern; | |
266abb8f | 7740 | |
0b2e31dc | 7741 | pattern = (current_architecture |
9a2e615a | 7742 | & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); |
0b2e31dc NS |
7743 | for (ix = 0; isa_features[ix][1]; ix++) |
7744 | { | |
7745 | if (pattern == isa_features[ix][1]) | |
7746 | { | |
7747 | flags |= isa_features[ix][0]; | |
7748 | break; | |
7749 | } | |
7750 | } | |
7751 | if (!isa_features[ix][1]) | |
7752 | { | |
7753 | cf_bad: | |
7754 | as_warn (_("Not a defined coldfire architecture")); | |
7755 | } | |
7756 | else | |
7757 | { | |
7758 | if (current_architecture & cfloat) | |
c694fd50 | 7759 | flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E; |
266abb8f | 7760 | |
0b2e31dc NS |
7761 | pattern = current_architecture & (mcfmac|mcfemac); |
7762 | if (pattern) | |
7763 | { | |
7764 | for (ix = 0; mac_features[ix][1]; ix++) | |
7765 | { | |
7766 | if (pattern == mac_features[ix][1]) | |
7767 | { | |
7768 | flags |= mac_features[ix][0]; | |
7769 | break; | |
7770 | } | |
7771 | } | |
7772 | if (!mac_features[ix][1]) | |
7773 | goto cf_bad; | |
7774 | } | |
7775 | } | |
266abb8f NS |
7776 | } |
7777 | elf_elfheader (stdoutput)->e_flags |= flags; | |
0d96863f CM |
7778 | } |
7779 | #endif | |
c04898f8 AS |
7780 | |
7781 | int | |
1df69f4f | 7782 | tc_m68k_regname_to_dw2regnum (char *regname) |
c04898f8 AS |
7783 | { |
7784 | unsigned int regnum; | |
7785 | static const char *const regnames[] = | |
7786 | { | |
7787 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", | |
7788 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", | |
7789 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", | |
7790 | "pc" | |
7791 | }; | |
7792 | ||
7793 | for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) | |
7794 | if (strcmp (regname, regnames[regnum]) == 0) | |
7795 | return regnum; | |
7796 | ||
7797 | return -1; | |
7798 | } | |
7799 | ||
7800 | void | |
7801 | tc_m68k_frame_initial_instructions (void) | |
7802 | { | |
7803 | static int sp_regno = -1; | |
7804 | ||
7805 | if (sp_regno < 0) | |
7806 | sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); | |
7807 | ||
7808 | cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); | |
7809 | cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); | |
7810 | } |