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[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
266abb8f 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
2da12c60
NS		 155static const enum m68k_register m68000_ctrl[] = { 0 };
156static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 157 SFC, DFC, USP, VBR,
158 0
159};
2da12c60 160static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
2da12c60 164static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
2da12c60 169static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
2da12c60 174static const enum m68k_register mcf_ctrl[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 176 RAMBAR0, RAMBAR1, MBAR,
177 0
178};
2da12c60 179static const enum m68k_register mcf5208_ctrl[] = {
266abb8f
NS		 180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182};
2da12c60 183static const enum m68k_register mcf5213_ctrl[] = {
266abb8f
NS		 184 VBR, RAMBAR, FLASHBAR,
185 0
186};
2da12c60
NS		 187static const enum m68k_register mcf5216_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
266abb8f
NS		 189 0
190};
2da12c60
NS		 191static const enum m68k_register mcf5235_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, RAMBAR,
e80e0390
NC		 193 0
194};
2da12c60
NS		 195static const enum m68k_register mcf5249_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
3e602632
NC		 197 0
198};
2da12c60
NS		 199static const enum m68k_register mcf5250_ctrl[] = {
200 VBR,
201 0
202};
203static const enum m68k_register mcf5271_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
205 0
206};
207static const enum m68k_register mcf5272_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
209 0
210};
211static const enum m68k_register mcf5275_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR,
213 0
214};
215static const enum m68k_register mcf5282_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
217 0
218};
219static const enum m68k_register mcf5329_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR,
221 0
222};
223static const enum m68k_register mcf5373_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226};
227static const enum m68k_register mcfv4e_ctrl[] = {
3e602632
NC		 228 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
229 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
230 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
231 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
232 0
233};
2da12c60 234#define cpu32_ctrl m68010_ctrl
252b5132
RH		 235
236static const enum m68k_register *control_regs;
237
36759679 238/* Internal form of a 68020 instruction. */
252b5132
RH		 239struct m68k_it
240{
241 const char *error;
36759679 242 const char *args; /* List of opcode info. */
252b5132
RH		 243 int numargs;
244
36759679 245 int numo; /* Number of shorts in opcode. */
252b5132
RH		 246 short opcode[11];
247
248 struct m68k_op operands[6];
249
36759679 250 int nexp; /* Number of exprs in use. */
252b5132
RH		 251 struct m68k_exp exprs[4];
252
36759679 253 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 254 struct
255 {
36759679 256 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 257 symbolS *fadd;
258 offsetT foff;
259 int fragty;
260 }
261 fragb[4];
262
36759679 263 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 264 struct
265 {
266 int n;
267 expressionS exp;
268 char wid;
269 char pcrel;
270 /* In a pc relative address the difference between the address
271 of the offset and the address that the offset is relative
272 to. This depends on the addressing mode. Basically this
273 is the value to put in the offset field to address the
274 first byte of the offset, without regarding the special
275 significance of some values (in the branch instruction, for
276 example). */
277 int pcrel_fix;
278#ifdef OBJ_ELF
279 /* Whether this expression needs special pic relocation, and if
280 so, which. */
281 enum pic_relocation pic_reloc;
282#endif
283 }
36759679 284 reloc[5]; /* Five is enough??? */
252b5132
RH		 285};
286
9840d27e 287#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 288#define float_of_arch(x) ((x) & mfloat)
289#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 290#define arch_coldfire_p(x) ((x) & mcfisa_a)
291#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 292
36759679 293/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 294#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 295
36759679 296static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 297
298#define op(ex) ((ex)->exp.X_op)
299#define adds(ex) ((ex)->exp.X_add_symbol)
300#define subs(ex) ((ex)->exp.X_op_symbol)
301#define offs(ex) ((ex)->exp.X_add_number)
302
36759679 303/* Macros for adding things to the m68k_it struct. */
31302357 304#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 305
36759679
NC		 306/* Like addword, but goes BEFORE general operands. */
307
252b5132 308static void
31302357 309insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 310{
311 int z;
07726851 312 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 313 the_ins.opcode[z] = the_ins.opcode[z - 1];
314 for (z = 0; z < the_ins.nrel; z++)
315 the_ins.reloc[z].n += 2;
252b5132
RH		 316 for (z = 0; z < the_ins.nfrag; z++)
317 the_ins.fragb[z].fragoff++;
8a104df9 318 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 319 the_ins.numo++;
320}
321
322/* The numo+1 kludge is so we can hit the low order byte of the prev word.
323 Blecch. */
324static void
31302357 325add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 326{
31302357
AS		 327 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
328 ? the_ins.numo * 2 - 1
329 : (width == 'b'
330 ? the_ins.numo * 2 + 1
331 : the_ins.numo * 2));
252b5132
RH		 332 the_ins.reloc[the_ins.nrel].exp = exp->exp;
333 the_ins.reloc[the_ins.nrel].wid = width;
334 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
335#ifdef OBJ_ELF
336 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
337#endif
338 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
339}
340
341/* Cause an extra frag to be generated here, inserting up to 10 bytes
342 (that value is chosen in the frag_var call in md_assemble). TYPE
343 is the subtype of the frag to be generated; its primary type is
344 rs_machine_dependent.
345
346 The TYPE parameter is also used by md_convert_frag_1 and
347 md_estimate_size_before_relax. The appropriate type of fixup will
348 be emitted by md_convert_frag_1.
349
350 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
351static void
31302357 352add_frag (symbolS *add, offsetT off, int type)
252b5132 353{
8a104df9
KH		 354 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
355 the_ins.fragb[the_ins.nfrag].fadd = add;
356 the_ins.fragb[the_ins.nfrag].foff = off;
357 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 358}
359
360#define isvar(ex) \
361 (op (ex) != O_constant && op (ex) != O_big)
362
31302357
AS		 363static char *crack_operand (char *str, struct m68k_op *opP);
364static int get_num (struct m68k_exp *exp, int ok);
365static int reverse_16_bits (int in);
366static int reverse_8_bits (int in);
367static void install_gen_operand (int mode, int val);
368static void install_operand (int mode, int val);
369static void s_bss (int);
370static void s_data1 (int);
371static void s_data2 (int);
372static void s_even (int);
373static void s_proc (int);
374static void s_chip (int);
375static void s_fopt (int);
376static void s_opt (int);
377static void s_reg (int);
378static void s_restore (int);
379static void s_save (int);
380static void s_mri_if (int);
381static void s_mri_else (int);
382static void s_mri_endi (int);
383static void s_mri_break (int);
384static void s_mri_next (int);
385static void s_mri_for (int);
386static void s_mri_endf (int);
387static void s_mri_repeat (int);
388static void s_mri_until (int);
389static void s_mri_while (int);
390static void s_mri_endw (int);
266abb8f
NS		 391static void s_m68k_cpu (int);
392static void s_m68k_arch (int);
393
394struct m68k_cpu
395{
396 unsigned long arch; /* Architecture features. */
2da12c60 397 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 398 const char *name; /* Name */
0b2e31dc
NS		 399 int alias; /* Alias for a cannonical name. If 1, then
400 succeeds canonical name, if -1 then
401 succeeds canonical name, if <-1 ||>1 this is a
402 deprecated name, and the next/previous name
403 should be used. */
266abb8f 404};
252b5132 405
266abb8f
NS		 406/* We hold flags for features explicitly enabled and explicitly
407 disabled. */
252b5132 408static int current_architecture;
266abb8f 409static int not_current_architecture;
266abb8f
NS		 410static const struct m68k_cpu *selected_arch;
411static const struct m68k_cpu *selected_cpu;
412static int initialized;
252b5132 413
266abb8f
NS		 414/* Architecture models. */
415static const struct m68k_cpu m68k_archs[] =
416{
2da12c60
NS		 417 {m68000, m68000_ctrl, "68000", 0},
418 {m68010, m68010_ctrl, "68010", 0},
419 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
420 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
421 {m68040, m68040_ctrl, "68040", 0},
422 {m68060, m68060_ctrl, "68060", 0},
423 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
9840d27e 424 {cpu32|fido_a, cpu32_ctrl, "fidoa", 0},
2da12c60
NS		 425 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
426 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
427 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
428 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
429 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 430 {0,0,NULL, 0}
431};
252b5132 432
0b2e31dc
NS		 433/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
434 for either. */
266abb8f
NS		 435static const struct m68k_cpu m68k_extensions[] =
436{
2da12c60
NS		 437 {m68851, NULL, "68851", -1},
438 {m68881, NULL, "68881", -1},
439 {m68881, NULL, "68882", -1},
0b2e31dc 440
2da12c60 441 {cfloat|m68881, NULL, "float", 0},
266abb8f 442
2da12c60
NS		 443 {mcfhwdiv, NULL, "div", 1},
444 {mcfusp, NULL, "usp", 1},
445 {mcfmac, NULL, "mac", 1},
446 {mcfemac, NULL, "emac", 1},
266abb8f 447
2da12c60 448 {0,NULL,NULL, 0}
266abb8f
NS		 449};
450
451/* Processor list */
452static const struct m68k_cpu m68k_cpus[] =
453{
2da12c60
NS		 454 {m68000, m68000_ctrl, "68000", 0},
455 {m68000, m68000_ctrl, "68ec000", 1},
456 {m68000, m68000_ctrl, "68hc000", 1},
457 {m68000, m68000_ctrl, "68hc001", 1},
458 {m68000, m68000_ctrl, "68008", 1},
459 {m68000, m68000_ctrl, "68302", 1},
460 {m68000, m68000_ctrl, "68306", 1},
461 {m68000, m68000_ctrl, "68307", 1},
462 {m68000, m68000_ctrl, "68322", 1},
463 {m68000, m68000_ctrl, "68356", 1},
464 {m68010, m68010_ctrl, "68010", 0},
465 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
466 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
467 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
468 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
469 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
470 {m68040, m68040_ctrl, "68040", 0},
471 {m68040, m68040_ctrl, "68ec040", 1},
472 {m68060, m68060_ctrl, "68060", 0},
473 {m68060, m68060_ctrl, "68ec060", 1},
474
475 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
476 {cpu32|m68881, cpu32_ctrl, "68330", 1},
477 {cpu32|m68881, cpu32_ctrl, "68331", 1},
478 {cpu32|m68881, cpu32_ctrl, "68332", 1},
479 {cpu32|m68881, cpu32_ctrl, "68333", 1},
480 {cpu32|m68881, cpu32_ctrl, "68334", 1},
481 {cpu32|m68881, cpu32_ctrl, "68336", 1},
482 {cpu32|m68881, cpu32_ctrl, "68340", 1},
483 {cpu32|m68881, cpu32_ctrl, "68341", 1},
484 {cpu32|m68881, cpu32_ctrl, "68349", 1},
485 {cpu32|m68881, cpu32_ctrl, "68360", 1},
486
487 {mcfisa_a, mcf_ctrl, "5200", 0},
488 {mcfisa_a, mcf_ctrl, "5202", 1},
489 {mcfisa_a, mcf_ctrl, "5204", 1},
490 {mcfisa_a, mcf_ctrl, "5206", 1},
491
492 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
493
494 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
495 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
496
497 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
498 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
499 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
500
501 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
502 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
503 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
504
505 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
506 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
507 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
508 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
509 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
510
511 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
512 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
513
514 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
515 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
516
517 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
518
519 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
520 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
521
522 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
523 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
524 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
525 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
526
527 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
528
529 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
530 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
531 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
532 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
533
534 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
535 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
536 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
537
538 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
539
540 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
541 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
542 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
543 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
544 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
545 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
546 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
547
548 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
549 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
550 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
551 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
552 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
553 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
554 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
555
9840d27e
KH		 556 {cpu32|fido_a, cpu32_ctrl, "fido", 1},
557
2da12c60 558 {0,NULL,NULL, 0}
dc84e067 559 };
252b5132 560
266abb8f
NS		 561static const struct m68k_cpu *m68k_lookup_cpu
562(const char *, const struct m68k_cpu *, int, int *);
563static int m68k_set_arch (const char *, int, int);
564static int m68k_set_cpu (const char *, int, int);
565static int m68k_set_extension (const char *, int, int);
566static void m68k_init_arch (void);
252b5132 567
151337e8
NC		 568/* This is the assembler relaxation table for m68k. m68k is a rich CISC
569 architecture and we have a lot of relaxation modes. */
252b5132 570
151337e8
NC		 571/* Macros used in the relaxation code. */
572#define TAB(x,y) (((x) << 2) + (y))
573#define TABTYPE(x) ((x) >> 2)
574
575/* Relaxation states. */
576#define BYTE 0
577#define SHORT 1
578#define LONG 2
579#define SZ_UNDEF 3
580
581/* Here are all the relaxation modes we support. First we can relax ordinary
582 branches. On 68020 and higher and on CPU32 all branch instructions take
583 three forms, so on these CPUs all branches always remain as such. When we
584 have to expand to the LONG form on a 68000, though, we substitute an
585 absolute jump instead. This is a direct replacement for unconditional
586 branches and a branch over a jump for conditional branches. However, if the
587 user requires PIC and disables this with --pcrel, we can only relax between
588 BYTE and SHORT forms, punting if that isn't enough. This gives us four
589 different relaxation modes for branches: */
590
36759679
NC		 591#define BRANCHBWL 0 /* Branch byte, word, or long. */
592#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
593#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
594#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 595
596/* We also relax coprocessor branches and DBcc's. All CPUs that support
597 coprocessor branches support them in word and long forms, so we have only
598 one relaxation mode for them. DBcc's are word only on all CPUs. We can
599 relax them to the LONG form with a branch-around sequence. This sequence
600 can use a long branch (if available) or an absolute jump (if acceptable).
601 This gives us two relaxation modes. If long branches are not available and
602 absolute jumps are not acceptable, we don't relax DBcc's. */
603
36759679
NC		 604#define FBRANCH 4 /* Coprocessor branch. */
605#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
606#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 607
608/* That's all for instruction relaxation. However, we also relax PC-relative
609 operands. Specifically, we have three operand relaxation modes. On the
610 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
611 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
612 two. Also PC+displacement+index operands in their simple form (with a non-
613 suppressed index without memory indirection) are supported on all CPUs, but
614 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
615 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
616 form of the PC+displacement+index operand. Finally, some absolute operands
617 can be relaxed down to 16-bit PC-relative. */
618
36759679
NC		 619#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
620#define PCINDEX 8 /* PC + displacement + index. */
621#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 622
623/* Note that calls to frag_var need to specify the maximum expansion
624 needed; this is currently 10 bytes for DBCC. */
625
626/* The fields are:
627 How far Forward this mode will reach:
628 How far Backward this mode will reach:
629 How many bytes this mode will add to the size of the frag
630 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 631
632 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 633relax_typeS md_relax_table[] =
634{
ac62c346
AM		 635 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
636 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
637 { 0, 0, 4, 0 },
638 { 1, 1, 0, 0 },
639
640 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
641 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
642 { 0, 0, 4, 0 },
643 { 1, 1, 0, 0 },
644
645 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
646 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
647 { 0, 0, 6, 0 },
648 { 1, 1, 0, 0 },
649
650 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
651 { 0, 0, 2, 0 },
652 { 1, 1, 0, 0 },
653 { 1, 1, 0, 0 },
654
36759679 655 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 656 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
657 { 0, 0, 4, 0 },
658 { 1, 1, 0, 0 },
659
36759679 660 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 661 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
662 { 0, 0, 10, 0 },
663 { 1, 1, 0, 0 },
664
36759679 665 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 666 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
667 { 0, 0, 10, 0 },
668 { 1, 1, 0, 0 },
669
36759679 670 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 671 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
672 { 0, 0, 6, 0 },
673 { 1, 1, 0, 0 },
674
675 { 125, -130, 0, TAB (PCINDEX, SHORT) },
676 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
677 { 0, 0, 4, 0 },
678 { 1, 1, 0, 0 },
679
36759679 680 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 681 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
682 { 0, 0, 4, 0 },
683 { 1, 1, 0, 0 },
252b5132
RH		 684};
685
686/* These are the machine dependent pseudo-ops. These are included so
687 the assembler can work on the output from the SUN C compiler, which
36759679 688 generates these. */
252b5132
RH		 689
690/* This table describes all the machine specific pseudo-ops the assembler
691 has to support. The fields are:
692 pseudo-op name without dot
693 function to call to execute this pseudo-op
36759679 694 Integer arg to pass to the function. */
252b5132
RH		 695const pseudo_typeS md_pseudo_table[] =
696{
697 {"data1", s_data1, 0},
698 {"data2", s_data2, 0},
699 {"bss", s_bss, 0},
700 {"even", s_even, 0},
701 {"skip", s_space, 0},
702 {"proc", s_proc, 0},
703#if defined (TE_SUN3) || defined (OBJ_ELF)
704 {"align", s_align_bytes, 0},
705#endif
706#ifdef OBJ_ELF
707 {"swbeg", s_ignore, 0},
708#endif
709 {"extend", float_cons, 'x'},
710 {"ldouble", float_cons, 'x'},
711
266abb8f
NS		 712 {"arch", s_m68k_arch, 0},
713 {"cpu", s_m68k_cpu, 0},
714
252b5132
RH		 715 /* The following pseudo-ops are supported for MRI compatibility. */
716 {"chip", s_chip, 0},
717 {"comline", s_space, 1},
718 {"fopt", s_fopt, 0},
719 {"mask2", s_ignore, 0},
720 {"opt", s_opt, 0},
721 {"reg", s_reg, 0},
722 {"restore", s_restore, 0},
723 {"save", s_save, 0},
724
725 {"if", s_mri_if, 0},
726 {"if.b", s_mri_if, 'b'},
727 {"if.w", s_mri_if, 'w'},
728 {"if.l", s_mri_if, 'l'},
729 {"else", s_mri_else, 0},
730 {"else.s", s_mri_else, 's'},
731 {"else.l", s_mri_else, 'l'},
732 {"endi", s_mri_endi, 0},
733 {"break", s_mri_break, 0},
734 {"break.s", s_mri_break, 's'},
735 {"break.l", s_mri_break, 'l'},
736 {"next", s_mri_next, 0},
737 {"next.s", s_mri_next, 's'},
738 {"next.l", s_mri_next, 'l'},
739 {"for", s_mri_for, 0},
740 {"for.b", s_mri_for, 'b'},
741 {"for.w", s_mri_for, 'w'},
742 {"for.l", s_mri_for, 'l'},
743 {"endf", s_mri_endf, 0},
744 {"repeat", s_mri_repeat, 0},
745 {"until", s_mri_until, 0},
746 {"until.b", s_mri_until, 'b'},
747 {"until.w", s_mri_until, 'w'},
748 {"until.l", s_mri_until, 'l'},
749 {"while", s_mri_while, 0},
750 {"while.b", s_mri_while, 'b'},
751 {"while.w", s_mri_while, 'w'},
752 {"while.l", s_mri_while, 'l'},
753 {"endw", s_mri_endw, 0},
754
755 {0, 0, 0}
756};
757
252b5132 758/* The mote pseudo ops are put into the opcode table, since they
31302357 759 don't start with a . they look like opcodes to gas. */
252b5132 760
5a38dc70 761const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 762{
763
764 {"dcl", cons, 4},
765 {"dc", cons, 2},
766 {"dcw", cons, 2},
767 {"dcb", cons, 1},
768
769 {"dsl", s_space, 4},
770 {"ds", s_space, 2},
771 {"dsw", s_space, 2},
772 {"dsb", s_space, 1},
773
774 {"xdef", s_globl, 0},
775#ifdef OBJ_ELF
776 {"align", s_align_bytes, 0},
777#else
778 {"align", s_align_ptwo, 0},
779#endif
780#ifdef M68KCOFF
781 {"sect", obj_coff_section, 0},
782 {"section", obj_coff_section, 0},
783#endif
784 {0, 0, 0}
785};
786
bd17c2c3
AM		 787/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
788 gives identical results to a 32-bit host. */
789#define TRUNC(X) ((valueT) (X) & 0xffffffff)
790#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
791
792#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
793#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
794#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
795#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
796
797#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
798#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 799#define islong(x) (1)
800
252b5132
RH		 801static char notend_table[256];
802static char alt_notend_table[256];
803#define notend(s) \
804 (! (notend_table[(unsigned char) *s] \
805 || (*s == ':' \
806 && alt_notend_table[(unsigned char) s[1]])))
807
252b5132
RH		 808#ifdef OBJ_ELF
809
c801568a
AM		 810/* Return zero if the reference to SYMBOL from within the same segment may
811 be relaxed. */
812
813/* On an ELF system, we can't relax an externally visible symbol,
814 because it may be overridden by a shared library. However, if
815 TARGET_OS is "elf", then we presume that we are assembling for an
816 embedded system, in which case we don't have to worry about shared
817 libraries, and we can relax any external sym. */
818
819#define relaxable_symbol(symbol) \
6358301e 820 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 821 || S_IS_WEAK (symbol)))
822
252b5132
RH		 823/* Compute the relocation code for a fixup of SIZE bytes, using pc
824 relative relocation if PCREL is non-zero. PIC says whether a special
825 pic relocation was requested. */
826
252b5132 827static bfd_reloc_code_real_type
31302357 828get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 829{
830 switch (pic)
831 {
832 case pic_got_pcrel:
833 switch (size)
834 {
835 case 1:
836 return BFD_RELOC_8_GOT_PCREL;
837 case 2:
838 return BFD_RELOC_16_GOT_PCREL;
839 case 4:
840 return BFD_RELOC_32_GOT_PCREL;
841 }
842 break;
843
844 case pic_got_off:
845 switch (size)
846 {
847 case 1:
848 return BFD_RELOC_8_GOTOFF;
849 case 2:
850 return BFD_RELOC_16_GOTOFF;
851 case 4:
852 return BFD_RELOC_32_GOTOFF;
853 }
854 break;
855
856 case pic_plt_pcrel:
857 switch (size)
858 {
859 case 1:
860 return BFD_RELOC_8_PLT_PCREL;
861 case 2:
862 return BFD_RELOC_16_PLT_PCREL;
863 case 4:
864 return BFD_RELOC_32_PLT_PCREL;
865 }
866 break;
867
868 case pic_plt_off:
869 switch (size)
870 {
871 case 1:
872 return BFD_RELOC_8_PLTOFF;
873 case 2:
874 return BFD_RELOC_16_PLTOFF;
875 case 4:
876 return BFD_RELOC_32_PLTOFF;
877 }
878 break;
879
880 case pic_none:
881 if (pcrel)
882 {
883 switch (size)
884 {
885 case 1:
886 return BFD_RELOC_8_PCREL;
887 case 2:
888 return BFD_RELOC_16_PCREL;
889 case 4:
890 return BFD_RELOC_32_PCREL;
891 }
892 }
893 else
894 {
895 switch (size)
896 {
897 case 1:
898 return BFD_RELOC_8;
899 case 2:
900 return BFD_RELOC_16;
901 case 4:
902 return BFD_RELOC_32;
903 }
904 }
905 }
906
907 if (pcrel)
908 {
909 if (pic == pic_none)
910 as_bad (_("Can not do %d byte pc-relative relocation"), size);
911 else
912 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
913 }
914 else
915 {
916 if (pic == pic_none)
917 as_bad (_("Can not do %d byte relocation"), size);
918 else
919 as_bad (_("Can not do %d byte pic relocation"), size);
920 }
921
922 return BFD_RELOC_NONE;
923}
924
925/* Here we decide which fixups can be adjusted to make them relative
926 to the beginning of the section instead of the symbol. Basically
927 we need to make sure that the dynamic relocations are done
928 correctly, so in some cases we force the original symbol to be
929 used. */
930int
31302357 931tc_m68k_fix_adjustable (fixS *fixP)
252b5132 932{
36759679 933 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 934 switch (fixP->fx_r_type)
935 {
936 case BFD_RELOC_8_GOT_PCREL:
937 case BFD_RELOC_16_GOT_PCREL:
938 case BFD_RELOC_32_GOT_PCREL:
939 case BFD_RELOC_8_GOTOFF:
940 case BFD_RELOC_16_GOTOFF:
941 case BFD_RELOC_32_GOTOFF:
942 case BFD_RELOC_8_PLT_PCREL:
943 case BFD_RELOC_16_PLT_PCREL:
944 case BFD_RELOC_32_PLT_PCREL:
945 case BFD_RELOC_8_PLTOFF:
946 case BFD_RELOC_16_PLTOFF:
947 case BFD_RELOC_32_PLTOFF:
948 return 0;
949
950 case BFD_RELOC_VTABLE_INHERIT:
951 case BFD_RELOC_VTABLE_ENTRY:
952 return 0;
953
954 default:
955 return 1;
956 }
957}
958
959#else /* !OBJ_ELF */
960
961#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
962
c801568a
AM		 963#define relaxable_symbol(symbol) 1
964
252b5132
RH		 965#endif /* OBJ_ELF */
966
252b5132 967arelent *
31302357 968tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 969{
970 arelent *reloc;
971 bfd_reloc_code_real_type code;
972
8ec6253e
NC		 973 /* If the tcbit is set, then this was a fixup of a negative value
974 that was never resolved. We do not have a reloc to handle this,
975 so just return. We assume that other code will have detected this
976 situation and produced a helpful error message, so we just tell the
977 user that the reloc cannot be produced. */
252b5132 978 if (fixp->fx_tcbit)
8ec6253e
NC		 979 {
980 if (fixp->fx_addsy)
b091f402
AM		 981 as_bad_where (fixp->fx_file, fixp->fx_line,
982 _("Unable to produce reloc against symbol '%s'"),
983 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 984 return NULL;
985 }
252b5132
RH		 986
987 if (fixp->fx_r_type != BFD_RELOC_NONE)
988 {
989 code = fixp->fx_r_type;
990
991 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
992 that fixup_segment converted a non-PC relative reloc into a
993 PC relative reloc. In such a case, we need to convert the
994 reloc code. */
995 if (fixp->fx_pcrel)
996 {
997 switch (code)
998 {
999 case BFD_RELOC_8:
1000 code = BFD_RELOC_8_PCREL;
1001 break;
1002 case BFD_RELOC_16:
1003 code = BFD_RELOC_16_PCREL;
1004 break;
1005 case BFD_RELOC_32:
1006 code = BFD_RELOC_32_PCREL;
1007 break;
1008 case BFD_RELOC_8_PCREL:
1009 case BFD_RELOC_16_PCREL:
1010 case BFD_RELOC_32_PCREL:
1011 case BFD_RELOC_8_GOT_PCREL:
1012 case BFD_RELOC_16_GOT_PCREL:
1013 case BFD_RELOC_32_GOT_PCREL:
1014 case BFD_RELOC_8_GOTOFF:
1015 case BFD_RELOC_16_GOTOFF:
1016 case BFD_RELOC_32_GOTOFF:
1017 case BFD_RELOC_8_PLT_PCREL:
1018 case BFD_RELOC_16_PLT_PCREL:
1019 case BFD_RELOC_32_PLT_PCREL:
1020 case BFD_RELOC_8_PLTOFF:
1021 case BFD_RELOC_16_PLTOFF:
1022 case BFD_RELOC_32_PLTOFF:
1023 break;
1024 default:
1025 as_bad_where (fixp->fx_file, fixp->fx_line,
1026 _("Cannot make %s relocation PC relative"),
1027 bfd_get_reloc_code_name (code));
1028 }
1029 }
1030 }
1031 else
1032 {
1033#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1034 switch (F (fixp->fx_size, fixp->fx_pcrel))
1035 {
1036#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1037 MAP (1, 0, BFD_RELOC_8);
1038 MAP (2, 0, BFD_RELOC_16);
1039 MAP (4, 0, BFD_RELOC_32);
1040 MAP (1, 1, BFD_RELOC_8_PCREL);
1041 MAP (2, 1, BFD_RELOC_16_PCREL);
1042 MAP (4, 1, BFD_RELOC_32_PCREL);
1043 default:
1044 abort ();
1045 }
1046 }
1047#undef F
1048#undef MAP
1049
1050 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1051 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1052 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1053 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1054#ifndef OBJ_ELF
1055 if (fixp->fx_pcrel)
1056 reloc->addend = fixp->fx_addnumber;
1057 else
1058 reloc->addend = 0;
1059#else
1060 if (!fixp->fx_pcrel)
1061 reloc->addend = fixp->fx_addnumber;
1062 else
1063 reloc->addend = (section->vma
8390138c
AS		 1064 /* Explicit sign extension in case char is
1065 unsigned. */
1066 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1067 + fixp->fx_addnumber
1068 + md_pcrel_from (fixp));
1069#endif
1070
1071 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1072 assert (reloc->howto != 0);
1073
1074 return reloc;
1075}
1076
252b5132
RH		 1077/* Handle of the OPCODE hash table. NULL means any use before
1078 m68k_ip_begin() will crash. */
1079static struct hash_control *op_hash;
1080\f
1081/* Assemble an m68k instruction. */
1082
1083static void
31302357 1084m68k_ip (char *instring)
252b5132
RH		 1085{
1086 register char *p;
1087 register struct m68k_op *opP;
1088 register const struct m68k_incant *opcode;
1089 register const char *s;
1090 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1091 char *pdot, *pdotmove;
1092 enum m68k_size siz1, siz2;
1093 char c;
1094 int losing;
1095 int opsfound;
03b13e59 1096 struct m68k_op operands_backup[6];
252b5132
RH		 1097 LITTLENUM_TYPE words[6];
1098 LITTLENUM_TYPE *wordp;
1099 unsigned long ok_arch = 0;
1100
1101 if (*instring == ' ')
36759679 1102 instring++; /* Skip leading whitespace. */
252b5132
RH		 1103
1104 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1105 or exactly 1 space. */
252b5132
RH		 1106 pdot = 0;
1107 for (p = instring; *p != '\0'; p++)
1108 {
1109 if (*p == ' ')
1110 break;
1111 if (*p == '.')
1112 pdot = p;
1113 }
1114
1115 if (p == instring)
1116 {
1117 the_ins.error = _("No operator");
1118 return;
1119 }
1120
1121 /* p now points to the end of the opcode name, probably whitespace.
1122 Make sure the name is null terminated by clobbering the
1123 whitespace, look it up in the hash table, then fix it back.
1124 Remove a dot, first, since the opcode tables have none. */
1125 if (pdot != NULL)
1126 {
1127 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1128 *pdotmove = pdotmove[1];
1129 p--;
1130 }
1131
1132 c = *p;
1133 *p = '\0';
1134 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1135 *p = c;
1136
1137 if (pdot != NULL)
1138 {
1139 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1140 *pdotmove = pdotmove[-1];
1141 *pdot = '.';
1142 ++p;
1143 }
1144
1145 if (opcode == NULL)
1146 {
1147 the_ins.error = _("Unknown operator");
1148 return;
1149 }
1150
36759679 1151 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1152 while (*p == ' ')
1153 ++p;
1154
1155 if (opcode->m_operands == 0)
1156 {
1157 char *old = input_line_pointer;
1158 *old = '\n';
1159 input_line_pointer = p;
36759679 1160 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1161 mote_pseudo_table[opcode->m_opnum].poc_handler
1162 (mote_pseudo_table[opcode->m_opnum].poc_val);
1163 input_line_pointer = old;
1164 *old = 0;
1165
1166 return;
1167 }
1168
1169 if (flag_mri && opcode->m_opnum == 0)
1170 {
1171 /* In MRI mode, random garbage is allowed after an instruction
1172 which accepts no operands. */
1173 the_ins.args = opcode->m_operands;
1174 the_ins.numargs = opcode->m_opnum;
1175 the_ins.numo = opcode->m_codenum;
1176 the_ins.opcode[0] = getone (opcode);
1177 the_ins.opcode[1] = gettwo (opcode);
1178 return;
1179 }
1180
1181 for (opP = &the_ins.operands[0]; *p; opP++)
1182 {
1183 p = crack_operand (p, opP);
1184
1185 if (opP->error)
1186 {
1187 the_ins.error = opP->error;
1188 return;
1189 }
1190 }
1191
1192 opsfound = opP - &the_ins.operands[0];
1193
1194 /* This ugly hack is to support the floating pt opcodes in their
1195 standard form. Essentially, we fake a first enty of type COP#1 */
1196 if (opcode->m_operands[0] == 'I')
1197 {
1198 int n;
1199
1200 for (n = opsfound; n > 0; --n)
1201 the_ins.operands[n] = the_ins.operands[n - 1];
1202
31302357 1203 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1204 the_ins.operands[0].mode = CONTROL;
1205 the_ins.operands[0].reg = m68k_float_copnum;
1206 opsfound++;
1207 }
1208
36759679 1209 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1210 for (losing = 0;;)
1211 {
1212 /* If we didn't get the right number of ops, or we have no
92774660 1213 common model with this pattern then reject this pattern. */
252b5132
RH		 1214
1215 ok_arch |= opcode->m_arch;
1216 if (opsfound != opcode->m_opnum
1217 || ((opcode->m_arch & current_architecture) == 0))
1218 ++losing;
1219 else
1220 {
03b13e59
NC		 1221 int i;
1222
1223 /* Make a copy of the operands of this insn so that
1224 we can modify them safely, should we want to. */
1225 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1226 for (i = 0; i < opsfound; i++)
1227 operands_backup[i] = the_ins.operands[i];
1228
1229 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1230 *s && !losing;
1231 s += 2, opP++)
1232 {
1233 /* Warning: this switch is huge! */
1234 /* I've tried to organize the cases into this order:
1235 non-alpha first, then alpha by letter. Lower-case
1236 goes directly before uppercase counterpart. */
1237 /* Code with multiple case ...: gets sorted by the lowest
1238 case ... it belongs to. I hope this makes sense. */
1239 switch (*s)
1240 {
1241 case '!':
1242 switch (opP->mode)
1243 {
1244 case IMMED:
1245 case DREG:
1246 case AREG:
1247 case FPREG:
1248 case CONTROL:
1249 case AINC:
1250 case ADEC:
1251 case REGLST:
1252 losing++;
1253 break;
1254 default:
1255 break;
1256 }
1257 break;
1258
1259 case '<':
1260 switch (opP->mode)
1261 {
1262 case DREG:
1263 case AREG:
1264 case FPREG:
1265 case CONTROL:
1266 case IMMED:
1267 case ADEC:
1268 case REGLST:
1269 losing++;
1270 break;
1271 default:
1272 break;
1273 }
1274 break;
1275
1276 case '>':
1277 switch (opP->mode)
1278 {
1279 case DREG:
1280 case AREG:
1281 case FPREG:
1282 case CONTROL:
1283 case IMMED:
1284 case AINC:
1285 case REGLST:
1286 losing++;
1287 break;
1288 case ABSL:
1289 break;
1290 default:
1291 if (opP->reg == PC
1292 || opP->reg == ZPC)
1293 losing++;
1294 break;
1295 }
1296 break;
1297
1298 case 'm':
1299 switch (opP->mode)
1300 {
1301 case DREG:
1302 case AREG:
1303 case AINDR:
1304 case AINC:
1305 case ADEC:
1306 break;
1307 default:
1308 losing++;
1309 }
8a104df9 1310 break;
252b5132
RH		 1311
1312 case 'n':
1313 switch (opP->mode)
1314 {
1315 case DISP:
1316 break;
1317 default:
1318 losing++;
1319 }
8a104df9 1320 break;
252b5132
RH		 1321
1322 case 'o':
1323 switch (opP->mode)
1324 {
1325 case BASE:
1326 case ABSL:
1327 case IMMED:
1328 break;
1329 default:
1330 losing++;
1331 }
8a104df9 1332 break;
252b5132
RH		 1333
1334 case 'p':
1335 switch (opP->mode)
1336 {
1337 case DREG:
1338 case AREG:
1339 case AINDR:
1340 case AINC:
1341 case ADEC:
1342 break;
1343 case DISP:
1344 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1345 losing++;
252b5132
RH		 1346 break;
1347 default:
1348 losing++;
1349 }
8a104df9 1350 break;
252b5132
RH		 1351
1352 case 'q':
1353 switch (opP->mode)
1354 {
1355 case DREG:
1356 case AINDR:
1357 case AINC:
1358 case ADEC:
1359 break;
1360 case DISP:
1361 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1362 losing++;
252b5132
RH		 1363 break;
1364 default:
1365 losing++;
1366 break;
1367 }
8a104df9 1368 break;
252b5132
RH		 1369
1370 case 'v':
1371 switch (opP->mode)
1372 {
1373 case DREG:
1374 case AINDR:
1375 case AINC:
1376 case ADEC:
1377 case ABSL:
1378 break;
1379 case DISP:
1380 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1381 losing++;
252b5132
RH		 1382 break;
1383 default:
1384 losing++;
1385 break;
1386 }
1387 break;
1388
1389 case '#':
1390 if (opP->mode != IMMED)
1391 losing++;
1392 else if (s[1] == 'b'
1393 && ! isvar (&opP->disp)
1394 && (opP->disp.exp.X_op != O_constant
1395 || ! isbyte (opP->disp.exp.X_add_number)))
1396 losing++;
1397 else if (s[1] == 'B'
1398 && ! isvar (&opP->disp)
1399 && (opP->disp.exp.X_op != O_constant
1400 || ! issbyte (opP->disp.exp.X_add_number)))
1401 losing++;
1402 else if (s[1] == 'w'
1403 && ! isvar (&opP->disp)
1404 && (opP->disp.exp.X_op != O_constant
1405 || ! isword (opP->disp.exp.X_add_number)))
1406 losing++;
1407 else if (s[1] == 'W'
1408 && ! isvar (&opP->disp)
1409 && (opP->disp.exp.X_op != O_constant
1410 || ! issword (opP->disp.exp.X_add_number)))
1411 losing++;
1412 break;
1413
1414 case '^':
1415 case 'T':
1416 if (opP->mode != IMMED)
1417 losing++;
1418 break;
1419
1420 case '$':
1421 if (opP->mode == AREG
1422 || opP->mode == CONTROL
1423 || opP->mode == FPREG
1424 || opP->mode == IMMED
1425 || opP->mode == REGLST
1426 || (opP->mode != ABSL
1427 && (opP->reg == PC
1428 || opP->reg == ZPC)))
1429 losing++;
1430 break;
1431
1432 case '%':
1433 if (opP->mode == CONTROL
1434 || opP->mode == FPREG
1435 || opP->mode == REGLST
1436 || opP->mode == IMMED
1437 || (opP->mode != ABSL
1438 && (opP->reg == PC
1439 || opP->reg == ZPC)))
1440 losing++;
1441 break;
1442
1443 case '&':
1444 switch (opP->mode)
1445 {
1446 case DREG:
1447 case AREG:
1448 case FPREG:
1449 case CONTROL:
1450 case IMMED:
1451 case AINC:
1452 case ADEC:
1453 case REGLST:
1454 losing++;
1455 break;
1456 case ABSL:
1457 break;
1458 default:
1459 if (opP->reg == PC
1460 || opP->reg == ZPC)
1461 losing++;
1462 break;
1463 }
1464 break;
1465
1466 case '*':
1467 if (opP->mode == CONTROL
1468 || opP->mode == FPREG
1469 || opP->mode == REGLST)
1470 losing++;
1471 break;
1472
1473 case '+':
1474 if (opP->mode != AINC)
1475 losing++;
1476 break;
1477
1478 case '-':
1479 if (opP->mode != ADEC)
1480 losing++;
1481 break;
1482
1483 case '/':
1484 switch (opP->mode)
1485 {
1486 case AREG:
1487 case CONTROL:
1488 case FPREG:
1489 case AINC:
1490 case ADEC:
1491 case IMMED:
1492 case REGLST:
1493 losing++;
1494 break;
1495 default:
1496 break;
1497 }
1498 break;
1499
1500 case ';':
1501 switch (opP->mode)
1502 {
1503 case AREG:
1504 case CONTROL:
1505 case FPREG:
1506 case REGLST:
1507 losing++;
1508 break;
1509 default:
1510 break;
1511 }
1512 break;
1513
1514 case '?':
1515 switch (opP->mode)
1516 {
1517 case AREG:
1518 case CONTROL:
1519 case FPREG:
1520 case AINC:
1521 case ADEC:
1522 case IMMED:
1523 case REGLST:
1524 losing++;
1525 break;
1526 case ABSL:
1527 break;
1528 default:
1529 if (opP->reg == PC || opP->reg == ZPC)
1530 losing++;
1531 break;
1532 }
1533 break;
1534
1535 case '@':
1536 switch (opP->mode)
1537 {
1538 case AREG:
1539 case CONTROL:
1540 case FPREG:
1541 case IMMED:
1542 case REGLST:
1543 losing++;
1544 break;
1545 default:
1546 break;
1547 }
1548 break;
1549
1550 case '~': /* For now! (JF FOO is this right?) */
1551 switch (opP->mode)
1552 {
1553 case DREG:
1554 case AREG:
1555 case CONTROL:
1556 case FPREG:
1557 case IMMED:
1558 case REGLST:
1559 losing++;
1560 break;
1561 case ABSL:
1562 break;
1563 default:
1564 if (opP->reg == PC
1565 || opP->reg == ZPC)
1566 losing++;
1567 break;
1568 }
1569 break;
1570
1571 case '3':
1572 if (opP->mode != CONTROL
1573 || (opP->reg != TT0 && opP->reg != TT1))
1574 losing++;
1575 break;
1576
1577 case 'A':
1578 if (opP->mode != AREG)
1579 losing++;
1580 break;
1581
1582 case 'a':
1583 if (opP->mode != AINDR)
1584 ++losing;
1585 break;
1586
fd99574b
NC		 1587 case '4':
1588 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1589 && (opP->mode != DISP
1590 || opP->reg < ADDR0
1591 || opP->reg > ADDR7))
1592 ++losing;
1593 break;
1594
252b5132
RH		 1595 case 'B': /* FOO */
1596 if (opP->mode != ABSL
1597 || (flag_long_jumps
1598 && strncmp (instring, "jbsr", 4) == 0))
1599 losing++;
1600 break;
1601
3e602632
NC		 1602 case 'b':
1603 switch (opP->mode)
1604 {
1605 case IMMED:
1606 case ABSL:
1607 case AREG:
1608 case FPREG:
1609 case CONTROL:
1610 case POST:
1611 case PRE:
1612 case REGLST:
1613 losing++;
1614 break;
1615 default:
1616 break;
1617 }
1618 break;
1619
252b5132
RH		 1620 case 'C':
1621 if (opP->mode != CONTROL || opP->reg != CCR)
1622 losing++;
1623 break;
1624
1625 case 'd':
1626 if (opP->mode != DISP
1627 || opP->reg < ADDR0
1628 || opP->reg > ADDR7)
1629 losing++;
1630 break;
1631
1632 case 'D':
1633 if (opP->mode != DREG)
1634 losing++;
1635 break;
1636
6da466c7
ILT		 1637 case 'E':
1638 if (opP->reg != ACC)
1639 losing++;
1640 break;
1641
fd99574b
NC		 1642 case 'e':
1643 if (opP->reg != ACC && opP->reg != ACC1
1644 && opP->reg != ACC2 && opP->reg != ACC3)
1645 losing++;
1646 break;
1647
252b5132
RH		 1648 case 'F':
1649 if (opP->mode != FPREG)
1650 losing++;
1651 break;
1652
6da466c7
ILT		 1653 case 'G':
1654 if (opP->reg != MACSR)
1655 losing++;
1656 break;
1657
fd99574b
NC		 1658 case 'g':
1659 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1660 losing++;
1661 break;
1662
6da466c7
ILT		 1663 case 'H':
1664 if (opP->reg != MASK)
1665 losing++;
1666 break;
1667
252b5132
RH		 1668 case 'I':
1669 if (opP->mode != CONTROL
1670 || opP->reg < COP0
1671 || opP->reg > COP7)
1672 losing++;
1673 break;
1674
fd99574b
NC		 1675 case 'i':
1676 if (opP->mode != LSH && opP->mode != RSH)
1677 losing++;
1678 break;
1679
252b5132
RH		 1680 case 'J':
1681 if (opP->mode != CONTROL
1682 || opP->reg < USP
0b2e31dc
NS		 1683 || opP->reg > last_movec_reg
1684 || !control_regs)
252b5132
RH		 1685 losing++;
1686 else
1687 {
1688 const enum m68k_register *rp;
0b2e31dc 1689
252b5132
RH		 1690 for (rp = control_regs; *rp; rp++)
1691 if (*rp == opP->reg)
1692 break;
1693 if (*rp == 0)
1694 losing++;
1695 }
1696 break;
1697
1698 case 'k':
1699 if (opP->mode != IMMED)
1700 losing++;
1701 break;
1702
1703 case 'l':
1704 case 'L':
1705 if (opP->mode == DREG
1706 || opP->mode == AREG
1707 || opP->mode == FPREG)
1708 {
1709 if (s[1] == '8')
1710 losing++;
1711 else
1712 {
1713 switch (opP->mode)
1714 {
1715 case DREG:
1716 opP->mask = 1 << (opP->reg - DATA0);
1717 break;
1718 case AREG:
1719 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1720 break;
1721 case FPREG:
1722 opP->mask = 1 << (opP->reg - FP0 + 16);
1723 break;
1724 default:
1725 abort ();
1726 }
1727 opP->mode = REGLST;
1728 }
1729 }
1730 else if (opP->mode == CONTROL)
1731 {
1732 if (s[1] != '8')
1733 losing++;
1734 else
1735 {
1736 switch (opP->reg)
1737 {
1738 case FPI:
1739 opP->mask = 1 << 24;
1740 break;
1741 case FPS:
1742 opP->mask = 1 << 25;
1743 break;
1744 case FPC:
1745 opP->mask = 1 << 26;
1746 break;
1747 default:
1748 losing++;
1749 break;
1750 }
1751 opP->mode = REGLST;
1752 }
1753 }
1754 else if (opP->mode != REGLST)
1755 losing++;
1756 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1757 losing++;
1758 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1759 losing++;
1760 break;
1761
1762 case 'M':
1763 if (opP->mode != IMMED)
1764 losing++;
1765 else if (opP->disp.exp.X_op != O_constant
1766 || ! issbyte (opP->disp.exp.X_add_number))
1767 losing++;
1768 else if (! m68k_quick
1769 && instring[3] != 'q'
1770 && instring[4] != 'q')
1771 losing++;
1772 break;
1773
1774 case 'O':
1775 if (opP->mode != DREG
1776 && opP->mode != IMMED
1777 && opP->mode != ABSL)
1778 losing++;
1779 break;
1780
1781 case 'Q':
1782 if (opP->mode != IMMED)
1783 losing++;
1784 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1785 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1786 losing++;
1787 else if (! m68k_quick
1788 && (strncmp (instring, "add", 3) == 0
1789 || strncmp (instring, "sub", 3) == 0)
1790 && instring[3] != 'q')
1791 losing++;
1792 break;
1793
1794 case 'R':
1795 if (opP->mode != DREG && opP->mode != AREG)
1796 losing++;
1797 break;
1798
1799 case 'r':
1800 if (opP->mode != AINDR
1801 && (opP->mode != BASE
1802 || (opP->reg != 0
1803 && opP->reg != ZADDR0)
1804 || opP->disp.exp.X_op != O_absent
1805 || ((opP->index.reg < DATA0
1806 || opP->index.reg > DATA7)
1807 && (opP->index.reg < ADDR0
1808 || opP->index.reg > ADDR7))
1809 || opP->index.size != SIZE_UNSPEC
1810 || opP->index.scale != 1))
1811 losing++;
1812 break;
1813
1814 case 's':
1815 if (opP->mode != CONTROL
1816 || ! (opP->reg == FPI
1817 || opP->reg == FPS
1818 || opP->reg == FPC))
1819 losing++;
1820 break;
1821
1822 case 'S':
1823 if (opP->mode != CONTROL || opP->reg != SR)
1824 losing++;
1825 break;
1826
1827 case 't':
1828 if (opP->mode != IMMED)
1829 losing++;
1830 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1831 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1832 losing++;
1833 break;
1834
1835 case 'U':
1836 if (opP->mode != CONTROL || opP->reg != USP)
1837 losing++;
1838 break;
1839
3e602632
NC		 1840 case 'x':
1841 if (opP->mode != IMMED)
1842 losing++;
1843 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1844 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1845 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1846 losing++;
1847 break;
1848
252b5132
RH		 1849 /* JF these are out of order. We could put them
1850 in order if we were willing to put up with
1851 bunches of #ifdef m68851s in the code.
1852
1853 Don't forget that you need these operands
1854 to use 68030 MMU instructions. */
1855#ifndef NO_68851
36759679 1856 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1857 case '|':
1858 if (opP->mode == CONTROL
1859 || opP->mode == FPREG
1860 || opP->mode == DREG
1861 || opP->mode == AREG
1862 || opP->mode == REGLST)
1863 losing++;
1864 /* We should accept immediate operands, but they
1865 supposedly have to be quad word, and we don't
1866 handle that. I would like to see what a Motorola
1867 assembler does before doing something here. */
1868 if (opP->mode == IMMED)
1869 losing++;
1870 break;
1871
1872 case 'f':
1873 if (opP->mode != CONTROL
1874 || (opP->reg != SFC && opP->reg != DFC))
1875 losing++;
1876 break;
1877
1878 case '0':
1879 if (opP->mode != CONTROL || opP->reg != TC)
1880 losing++;
1881 break;
1882
1883 case '1':
1884 if (opP->mode != CONTROL || opP->reg != AC)
1885 losing++;
1886 break;
1887
1888 case '2':
1889 if (opP->mode != CONTROL
1890 || (opP->reg != CAL
1891 && opP->reg != VAL
1892 && opP->reg != SCC))
1893 losing++;
1894 break;
1895
1896 case 'V':
1897 if (opP->mode != CONTROL
1898 || opP->reg != VAL)
1899 losing++;
1900 break;
1901
1902 case 'W':
1903 if (opP->mode != CONTROL
1904 || (opP->reg != DRP
1905 && opP->reg != SRP
1906 && opP->reg != CRP))
1907 losing++;
1908 break;
1909
3e602632
NC		 1910 case 'w':
1911 switch (opP->mode)
1912 {
1913 case IMMED:
1914 case ABSL:
1915 case AREG:
1916 case DREG:
1917 case FPREG:
1918 case CONTROL:
1919 case POST:
1920 case PRE:
1921 case REGLST:
1922 losing++;
1923 break;
1924 default:
1925 break;
1926 }
1927 break;
1928
252b5132
RH		 1929 case 'X':
1930 if (opP->mode != CONTROL
1931 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1932 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1933 losing++;
1934 break;
1935
1936 case 'Y':
1937 if (opP->mode != CONTROL || opP->reg != PSR)
1938 losing++;
1939 break;
1940
1941 case 'Z':
1942 if (opP->mode != CONTROL || opP->reg != PCSR)
1943 losing++;
1944 break;
1945#endif
1946 case 'c':
1947 if (opP->mode != CONTROL
1948 || (opP->reg != NC
1949 && opP->reg != IC
1950 && opP->reg != DC
1951 && opP->reg != BC))
36759679 1952 losing++;
252b5132
RH		 1953 break;
1954
1955 case '_':
1956 if (opP->mode != ABSL)
1957 ++losing;
1958 break;
1959
6da466c7
ILT		 1960 case 'u':
1961 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1962 losing++;
1963 /* FIXME: kludge instead of fixing parser:
1964 upper/lower registers are *not* CONTROL
92774660 1965 registers, but ordinary ones. */
6da466c7
ILT		 1966 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1967 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1968 opP->mode = DREG;
1969 else
1970 opP->mode = AREG;
1971 break;
1972
3e602632
NC		 1973 case 'y':
1974 if (!(opP->mode == AINDR
31302357
AS		 1975 || (opP->mode == DISP
1976 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 1977 losing++;
1978 break;
1979
1980 case 'z':
1981 if (!(opP->mode == AINDR || opP->mode == DISP))
1982 losing++;
1983 break;
1984
252b5132
RH		 1985 default:
1986 abort ();
36759679 1987 }
252b5132
RH		 1988
1989 if (losing)
1990 break;
36759679 1991 }
03b13e59
NC		 1992
1993 /* Since we have found the correct instruction, copy
1994 in the modifications that we may have made. */
1995 if (!losing)
1996 for (i = 0; i < opsfound; i++)
1997 the_ins.operands[i] = operands_backup[i];
36759679 1998 }
252b5132
RH		 1999
2000 if (!losing)
36759679 2001 break;
252b5132
RH		 2002
2003 opcode = opcode->m_next;
2004
2005 if (!opcode)
2006 {
2007 if (ok_arch
2008 && !(ok_arch & current_architecture))
2009 {
6d89cc8f
NS		 2010 const struct m68k_cpu *cpu;
2011 int any = 0;
2012 size_t space = 400;
2013 char *buf = xmalloc (space + 1);
2014 size_t len;
2015 int paren = 1;
2016
2017 the_ins.error = buf;
2018 /* Make sure there's a NUL at the end of the buffer -- strncpy
2019 won't write one when it runs out of buffer */
2020 buf[space] = 0;
2021#define APPEND(STRING) \
2022 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2023
2024 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2025 switch (ok_arch)
2026 {
6b6e92f4 2027 case mcfisa_a:
6d89cc8f 2028 APPEND (_("ColdFire ISA_A"));
6b6e92f4
NC		 2029 break;
2030 case mcfhwdiv:
6d89cc8f 2031 APPEND (_("ColdFire hardware divide"));
6b6e92f4
NC		 2032 break;
2033 case mcfisa_aa:
6d89cc8f 2034 APPEND (_("ColdFire ISA_A+"));
6b6e92f4
NC		 2035 break;
2036 case mcfisa_b:
6d89cc8f 2037 APPEND (_("ColdFire ISA_B"));
6b6e92f4 2038 break;
3e602632 2039 case cfloat:
6d89cc8f 2040 APPEND (_("ColdFire fpu"));
3e602632 2041 break;
252b5132 2042 case mfloat:
6d89cc8f 2043 APPEND (_("M68K fpu"));
252b5132
RH		 2044 break;
2045 case mmmu:
6d89cc8f 2046 APPEND (_("M68K mmu"));
252b5132
RH		 2047 break;
2048 case m68020up:
6d89cc8f 2049 APPEND (_("68020 or higher"));
252b5132
RH		 2050 break;
2051 case m68000up:
6d89cc8f 2052 APPEND (_("68000 or higher"));
252b5132
RH		 2053 break;
2054 case m68010up:
6d89cc8f 2055 APPEND (_("68010 or higher"));
252b5132
RH		 2056 break;
2057 default:
6d89cc8f
NS		 2058 paren = 0;
2059 }
2060 if (paren)
2061 APPEND (" (");
6b6e92f4 2062
6d89cc8f
NS		 2063 for (cpu = m68k_cpus; cpu->name; cpu++)
2064 if (!cpu->alias && (cpu->arch & ok_arch))
2065 {
2066 const struct m68k_cpu *alias;
869ddf2a
NS		 2067 int seen_master = 0;
2068
6d89cc8f
NS		 2069 if (any)
2070 APPEND (", ");
2071 any = 0;
2072 APPEND (cpu->name);
869ddf2a
NS		 2073 for (alias = cpu; alias != m68k_cpus; alias--)
2074 if (alias[-1].alias >= 0)
2075 break;
2076 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2077 {
869ddf2a
NS		 2078 if (!alias->alias)
2079 seen_master = 1;
2080 else
2081 {
2082 if (any)
2083 APPEND (", ");
2084 else
2085 APPEND (" [");
2086 APPEND (alias->name);
2087 any = 1;
2088 }
6d89cc8f 2089 }
869ddf2a
NS		 2090 if (any)
2091 APPEND ("]");
6d89cc8f 2092 any = 1;
252b5132 2093 }
6d89cc8f
NS		 2094 if (paren)
2095 APPEND (")");
2096#undef APPEND
2097 if (!space)
2098 {
2099 /* we ran out of space, so replace the end of the list
2100 with ellipsis. */
2101 buf -= 4;
2102 while (*buf != ' ')
2103 buf--;
2104 strcpy (buf, " ...");
252b5132 2105 }
252b5132
RH		 2106 }
2107 else
2108 the_ins.error = _("operands mismatch");
2109 return;
36759679 2110 }
252b5132
RH		 2111
2112 losing = 0;
2113 }
2114
36759679 2115 /* Now assemble it. */
252b5132
RH		 2116 the_ins.args = opcode->m_operands;
2117 the_ins.numargs = opcode->m_opnum;
2118 the_ins.numo = opcode->m_codenum;
2119 the_ins.opcode[0] = getone (opcode);
2120 the_ins.opcode[1] = gettwo (opcode);
2121
2122 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2123 {
2124 /* This switch is a doozy.
31302357 2125 Watch the first step; its a big one! */
252b5132
RH		 2126 switch (s[0])
2127 {
2128
2129 case '*':
2130 case '~':
2131 case '%':
2132 case ';':
2133 case '@':
2134 case '!':
2135 case '&':
2136 case '$':
2137 case '?':
2138 case '/':
2139 case '<':
2140 case '>':
3e602632 2141 case 'b':
252b5132
RH		 2142 case 'm':
2143 case 'n':
2144 case 'o':
2145 case 'p':
2146 case 'q':
2147 case 'v':
3e602632
NC		 2148 case 'w':
2149 case 'y':
2150 case 'z':
fd99574b 2151 case '4':
252b5132
RH		 2152#ifndef NO_68851
2153 case '|':
2154#endif
2155 switch (opP->mode)
2156 {
2157 case IMMED:
2158 tmpreg = 0x3c; /* 7.4 */
2159 if (strchr ("bwl", s[1]))
3e602632 2160 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2161 else
2162 nextword = get_num (&opP->disp, 0);
2163 if (isvar (&opP->disp))
2164 add_fix (s[1], &opP->disp, 0, 0);
2165 switch (s[1])
2166 {
2167 case 'b':
2168 if (!isbyte (nextword))
2169 opP->error = _("operand out of range");
2170 addword (nextword);
2171 baseo = 0;
2172 break;
2173 case 'w':
2174 if (!isword (nextword))
2175 opP->error = _("operand out of range");
2176 addword (nextword);
2177 baseo = 0;
2178 break;
2179 case 'W':
2180 if (!issword (nextword))
2181 opP->error = _("operand out of range");
2182 addword (nextword);
2183 baseo = 0;
2184 break;
2185 case 'l':
2186 addword (nextword >> 16);
2187 addword (nextword);
2188 baseo = 0;
2189 break;
2190
2191 case 'f':
2192 baseo = 2;
2193 outro = 8;
2194 break;
2195 case 'F':
2196 baseo = 4;
2197 outro = 11;
2198 break;
2199 case 'x':
2200 baseo = 6;
2201 outro = 15;
2202 break;
2203 case 'p':
2204 baseo = 6;
2205 outro = -1;
2206 break;
2207 default:
2208 abort ();
2209 }
2210 if (!baseo)
2211 break;
2212
36759679 2213 /* We gotta put out some float. */
252b5132
RH		 2214 if (op (&opP->disp) != O_big)
2215 {
2216 valueT val;
2217 int gencnt;
2218
2219 /* Can other cases happen here? */
2220 if (op (&opP->disp) != O_constant)
2221 abort ();
2222
2223 val = (valueT) offs (&opP->disp);
2224 gencnt = 0;
2225 do
2226 {
2227 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2228 val >>= LITTLENUM_NUMBER_OF_BITS;
2229 ++gencnt;
2230 }
2231 while (val != 0);
2232 offs (&opP->disp) = gencnt;
2233 }
2234 if (offs (&opP->disp) > 0)
2235 {
2236 if (offs (&opP->disp) > baseo)
2237 {
2238 as_warn (_("Bignum too big for %c format; truncated"),
2239 s[1]);
2240 offs (&opP->disp) = baseo;
2241 }
2242 baseo -= offs (&opP->disp);
2243 while (baseo--)
2244 addword (0);
2245 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2246 offs (&opP->disp)--;
2247 --wordp)
2248 addword (*wordp);
2249 break;
2250 }
2251 gen_to_words (words, baseo, (long) outro);
2252 for (wordp = words; baseo--; wordp++)
2253 addword (*wordp);
2254 break;
2255 case DREG:
2256 tmpreg = opP->reg - DATA; /* 0.dreg */
2257 break;
2258 case AREG:
2259 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2260 break;
2261 case AINDR:
2262 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2263 break;
2264 case ADEC:
2265 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2266 break;
2267 case AINC:
2268 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2269 break;
2270 case DISP:
2271
3e602632 2272 nextword = get_num (&opP->disp, 90);
252b5132 2273
580b9172
NC		 2274 /* Convert mode 5 addressing with a zero offset into
2275 mode 2 addressing to reduce the instruction size by a
2276 word. */
2277 if (! isvar (&opP->disp)
2278 && (nextword == 0)
2279 && (opP->disp.size == SIZE_UNSPEC)
2280 && (opP->reg >= ADDR0)
2281 && (opP->reg <= ADDR7))
2282 {
2283 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2284 break;
2285 }
2286
252b5132
RH		 2287 if (opP->reg == PC
2288 && ! isvar (&opP->disp)
2289 && m68k_abspcadd)
2290 {
2291 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2292 opP->disp.exp.X_add_symbol =
2293 section_symbol (absolute_section);
252b5132
RH		 2294 }
2295
36759679 2296 /* Force into index mode. Hope this works. */
252b5132
RH		 2297
2298 /* We do the first bit for 32-bit displacements, and the
2299 second bit for 16 bit ones. It is possible that we
2300 should make the default be WORD instead of LONG, but
2301 I think that'd break GCC, so we put up with a little
2302 inefficiency for the sake of working output. */
2303
2304 if (!issword (nextword)
2305 || (isvar (&opP->disp)
2306 && ((opP->disp.size == SIZE_UNSPEC
2307 && flag_short_refs == 0
2308 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2309 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2310 || opP->disp.size == SIZE_LONG)))
2311 {
2312 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2313 || arch_coldfire_p (current_architecture))
252b5132
RH		 2314 opP->error =
2315 _("displacement too large for this architecture; needs 68020 or higher");
2316 if (opP->reg == PC)
2317 tmpreg = 0x3B; /* 7.3 */
2318 else
2319 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2320 if (isvar (&opP->disp))
2321 {
2322 if (opP->reg == PC)
2323 {
2324 if (opP->disp.size == SIZE_LONG
2325#ifdef OBJ_ELF
2326 /* If the displacement needs pic
2327 relocation it cannot be relaxed. */
2328 || opP->disp.pic_reloc != pic_none
2329#endif
2330 )
2331 {
2332 addword (0x0170);
2333 add_fix ('l', &opP->disp, 1, 2);
2334 }
2335 else
2336 {
2337 add_frag (adds (&opP->disp),
bd17c2c3 2338 SEXT (offs (&opP->disp)),
151337e8 2339 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2340 break;
2341 }
2342 }
2343 else
2344 {
2345 addword (0x0170);
2346 add_fix ('l', &opP->disp, 0, 0);
2347 }
2348 }
2349 else
2350 addword (0x0170);
2351 addword (nextword >> 16);
2352 }
2353 else
2354 {
2355 if (opP->reg == PC)
2356 tmpreg = 0x3A; /* 7.2 */
2357 else
2358 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2359
2360 if (isvar (&opP->disp))
2361 {
2362 if (opP->reg == PC)
2363 {
2364 add_fix ('w', &opP->disp, 1, 0);
2365 }
2366 else
2367 add_fix ('w', &opP->disp, 0, 0);
2368 }
2369 }
2370 addword (nextword);
2371 break;
2372
2373 case POST:
2374 case PRE:
2375 case BASE:
2376 nextword = 0;
3e602632 2377 baseo = get_num (&opP->disp, 90);
252b5132 2378 if (opP->mode == POST || opP->mode == PRE)
3e602632 2379 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2380 /* Figure out the `addressing mode'.
2381 Also turn on the BASE_DISABLE bit, if needed. */
2382 if (opP->reg == PC || opP->reg == ZPC)
2383 {
2384 tmpreg = 0x3b; /* 7.3 */
2385 if (opP->reg == ZPC)
2386 nextword |= 0x80;
2387 }
2388 else if (opP->reg == 0)
2389 {
2390 nextword |= 0x80;
2391 tmpreg = 0x30; /* 6.garbage */
2392 }
2393 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2394 {
2395 nextword |= 0x80;
2396 tmpreg = 0x30 + opP->reg - ZADDR0;
2397 }
2398 else
2399 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2400
2401 siz1 = opP->disp.size;
2402 if (opP->mode == POST || opP->mode == PRE)
2403 siz2 = opP->odisp.size;
2404 else
2405 siz2 = SIZE_UNSPEC;
2406
36759679 2407 /* Index register stuff. */
252b5132
RH		 2408 if (opP->index.reg != 0
2409 && opP->index.reg >= DATA
2410 && opP->index.reg <= ADDR7)
2411 {
2412 nextword |= (opP->index.reg - DATA) << 12;
2413
2414 if (opP->index.size == SIZE_LONG
2415 || (opP->index.size == SIZE_UNSPEC
2416 && m68k_index_width_default == SIZE_LONG))
2417 nextword |= 0x800;
2418
92774660 2419 if ((opP->index.scale != 1
252b5132 2420 && cpu_of_arch (current_architecture) < m68020)
92774660 2421 || (opP->index.scale == 8
3e602632 2422 && (arch_coldfire_p (current_architecture)
6b6e92f4 2423 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2424 {
2425 opP->error =
2426 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2427 }
2428
6da466c7
ILT		 2429 if (arch_coldfire_p (current_architecture)
2430 && opP->index.size == SIZE_WORD)
2431 opP->error = _("invalid index size for coldfire");
2432
252b5132
RH		 2433 switch (opP->index.scale)
2434 {
2435 case 1:
2436 break;
2437 case 2:
2438 nextword |= 0x200;
2439 break;
2440 case 4:
2441 nextword |= 0x400;
2442 break;
2443 case 8:
2444 nextword |= 0x600;
2445 break;
2446 default:
2447 abort ();
2448 }
2449 /* IF its simple,
2450 GET US OUT OF HERE! */
2451
2452 /* Must be INDEX, with an index register. Address
2453 register cannot be ZERO-PC, and either :b was
2454 forced, or we know it will fit. For a 68000 or
2455 68010, force this mode anyways, because the
2456 larger modes aren't supported. */
2457 if (opP->mode == BASE
2458 && ((opP->reg >= ADDR0
2459 && opP->reg <= ADDR7)
2460 || opP->reg == PC))
2461 {
2462 if (siz1 == SIZE_BYTE
2463 || cpu_of_arch (current_architecture) < m68020
6da466c7 2464 || arch_coldfire_p (current_architecture)
252b5132
RH		 2465 || (siz1 == SIZE_UNSPEC
2466 && ! isvar (&opP->disp)
2467 && issbyte (baseo)))
2468 {
2469 nextword += baseo & 0xff;
2470 addword (nextword);
2471 if (isvar (&opP->disp))
2472 {
2473 /* Do a byte relocation. If it doesn't
2474 fit (possible on m68000) let the
2475 fixup processing complain later. */
2476 if (opP->reg == PC)
2477 add_fix ('B', &opP->disp, 1, 1);
2478 else
2479 add_fix ('B', &opP->disp, 0, 0);
2480 }
2481 else if (siz1 != SIZE_BYTE)
2482 {
2483 if (siz1 != SIZE_UNSPEC)
2484 as_warn (_("Forcing byte displacement"));
2485 if (! issbyte (baseo))
2486 opP->error = _("byte displacement out of range");
2487 }
2488
2489 break;
2490 }
2491 else if (siz1 == SIZE_UNSPEC
2492 && opP->reg == PC
2493 && isvar (&opP->disp)
2494 && subs (&opP->disp) == NULL
2495#ifdef OBJ_ELF
2496 /* If the displacement needs pic
2497 relocation it cannot be relaxed. */
2498 && opP->disp.pic_reloc == pic_none
2499#endif
2500 )
2501 {
2502 /* The code in md_convert_frag_1 needs to be
2503 able to adjust nextword. Call frag_grow
2504 to ensure that we have enough space in
2505 the frag obstack to make all the bytes
2506 contiguous. */
2507 frag_grow (14);
8a104df9
KH		 2508 nextword += baseo & 0xff;
2509 addword (nextword);
bd17c2c3
AM		 2510 add_frag (adds (&opP->disp),
2511 SEXT (offs (&opP->disp)),
8a104df9 2512 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2513
2514 break;
8a104df9 2515 }
252b5132
RH		 2516 }
2517 }
2518 else
2519 {
36759679 2520 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2521 if (opP->index.reg >= ZDATA0
2522 && opP->index.reg <= ZDATA7)
2523 nextword |= (opP->index.reg - ZDATA0) << 12;
2524 else if (opP->index.reg >= ZADDR0
2525 || opP->index.reg <= ZADDR7)
2526 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2527 }
2528
2529 /* It isn't simple. */
2530
2531 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2532 || arch_coldfire_p (current_architecture))
252b5132
RH		 2533 opP->error =
2534 _("invalid operand mode for this architecture; needs 68020 or higher");
2535
2536 nextword |= 0x100;
2537 /* If the guy specified a width, we assume that it is
2538 wide enough. Maybe it isn't. If so, we lose. */
2539 switch (siz1)
2540 {
2541 case SIZE_UNSPEC:
2542 if (isvar (&opP->disp)
2543 ? m68k_rel32
2544 : ! issword (baseo))
2545 {
2546 siz1 = SIZE_LONG;
2547 nextword |= 0x30;
2548 }
2549 else if (! isvar (&opP->disp) && baseo == 0)
2550 nextword |= 0x10;
2551 else
2552 {
2553 nextword |= 0x20;
2554 siz1 = SIZE_WORD;
2555 }
2556 break;
2557 case SIZE_BYTE:
2558 as_warn (_(":b not permitted; defaulting to :w"));
2559 /* Fall through. */
2560 case SIZE_WORD:
2561 nextword |= 0x20;
2562 break;
2563 case SIZE_LONG:
2564 nextword |= 0x30;
2565 break;
2566 }
2567
67c1ffbe 2568 /* Figure out inner displacement stuff. */
252b5132
RH		 2569 if (opP->mode == POST || opP->mode == PRE)
2570 {
2571 if (cpu_of_arch (current_architecture) & cpu32)
2572 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2573 switch (siz2)
2574 {
2575 case SIZE_UNSPEC:
2576 if (isvar (&opP->odisp)
2577 ? m68k_rel32
2578 : ! issword (outro))
2579 {
2580 siz2 = SIZE_LONG;
2581 nextword |= 0x3;
2582 }
2583 else if (! isvar (&opP->odisp) && outro == 0)
2584 nextword |= 0x1;
2585 else
2586 {
2587 nextword |= 0x2;
2588 siz2 = SIZE_WORD;
2589 }
2590 break;
2591 case 1:
2592 as_warn (_(":b not permitted; defaulting to :w"));
2593 /* Fall through. */
2594 case 2:
2595 nextword |= 0x2;
2596 break;
2597 case 3:
2598 nextword |= 0x3;
2599 break;
2600 }
2601 if (opP->mode == POST
2602 && (nextword & 0x40) == 0)
2603 nextword |= 0x04;
2604 }
2605 addword (nextword);
2606
2607 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2608 {
2609 if (opP->reg == PC || opP->reg == ZPC)
2610 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2611 else
2612 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2613 }
2614 if (siz1 == SIZE_LONG)
2615 addword (baseo >> 16);
2616 if (siz1 != SIZE_UNSPEC)
2617 addword (baseo);
2618
2619 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2620 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2621 if (siz2 == SIZE_LONG)
2622 addword (outro >> 16);
2623 if (siz2 != SIZE_UNSPEC)
2624 addword (outro);
2625
2626 break;
2627
2628 case ABSL:
3e602632 2629 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2630 switch (opP->disp.size)
2631 {
2632 default:
2633 abort ();
2634 case SIZE_UNSPEC:
2635 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2636 {
2637 tmpreg = 0x38; /* 7.0 */
2638 addword (nextword);
2639 break;
2640 }
252b5132
RH		 2641 if (isvar (&opP->disp)
2642 && !subs (&opP->disp)
2643 && adds (&opP->disp)
2644#ifdef OBJ_ELF
2645 /* If the displacement needs pic relocation it
2646 cannot be relaxed. */
2647 && opP->disp.pic_reloc == pic_none
2648#endif
252b5132
RH		 2649 && !flag_long_jumps
2650 && !strchr ("~%&$?", s[0]))
2651 {
2652 tmpreg = 0x3A; /* 7.2 */
2653 add_frag (adds (&opP->disp),
bd17c2c3 2654 SEXT (offs (&opP->disp)),
151337e8 2655 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2656 break;
2657 }
36759679 2658 /* Fall through into long. */
252b5132
RH		 2659 case SIZE_LONG:
2660 if (isvar (&opP->disp))
2661 add_fix ('l', &opP->disp, 0, 0);
2662
2663 tmpreg = 0x39;/* 7.1 mode */
2664 addword (nextword >> 16);
2665 addword (nextword);
2666 break;
2667
2668 case SIZE_BYTE:
2669 as_bad (_("unsupported byte value; use a different suffix"));
2670 /* Fall through. */
36759679
NC		 2671
2672 case SIZE_WORD:
252b5132
RH		 2673 if (isvar (&opP->disp))
2674 add_fix ('w', &opP->disp, 0, 0);
2675
2676 tmpreg = 0x38;/* 7.0 mode */
2677 addword (nextword);
2678 break;
2679 }
2680 break;
2681 case CONTROL:
2682 case FPREG:
2683 default:
2684 as_bad (_("unknown/incorrect operand"));
bc805888 2685 /* abort (); */
252b5132 2686 }
fd99574b
NC		 2687
2688 /* If s[0] is '4', then this is for the mac instructions
2689 that can have a trailing_ampersand set. If so, set 0x100
2690 bit on tmpreg so install_gen_operand can check for it and
2691 set the appropriate bit (word2, bit 5). */
2692 if (s[0] == '4')
2693 {
2694 if (opP->trailing_ampersand)
2695 tmpreg |= 0x100;
2696 }
252b5132
RH		 2697 install_gen_operand (s[1], tmpreg);
2698 break;
2699
2700 case '#':
2701 case '^':
2702 switch (s[1])
2703 { /* JF: I hate floating point! */
2704 case 'j':
2705 tmpreg = 70;
2706 break;
2707 case '8':
2708 tmpreg = 20;
2709 break;
2710 case 'C':
2711 tmpreg = 50;
2712 break;
2713 case '3':
2714 default:
3e602632 2715 tmpreg = 90;
252b5132
RH		 2716 break;
2717 }
2718 tmpreg = get_num (&opP->disp, tmpreg);
2719 if (isvar (&opP->disp))
2720 add_fix (s[1], &opP->disp, 0, 0);
2721 switch (s[1])
2722 {
2723 case 'b': /* Danger: These do no check for
2724 certain types of overflow.
2725 user beware! */
2726 if (!isbyte (tmpreg))
2727 opP->error = _("out of range");
2728 insop (tmpreg, opcode);
2729 if (isvar (&opP->disp))
2730 the_ins.reloc[the_ins.nrel - 1].n =
2731 (opcode->m_codenum) * 2 + 1;
2732 break;
2733 case 'B':
2734 if (!issbyte (tmpreg))
2735 opP->error = _("out of range");
2736 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2737 if (isvar (&opP->disp))
2738 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2739 break;
2740 case 'w':
2741 if (!isword (tmpreg))
2742 opP->error = _("out of range");
2743 insop (tmpreg, opcode);
2744 if (isvar (&opP->disp))
2745 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2746 break;
2747 case 'W':
2748 if (!issword (tmpreg))
2749 opP->error = _("out of range");
2750 insop (tmpreg, opcode);
2751 if (isvar (&opP->disp))
2752 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2753 break;
2754 case 'l':
2755 /* Because of the way insop works, we put these two out
2756 backwards. */
2757 insop (tmpreg, opcode);
2758 insop (tmpreg >> 16, opcode);
2759 if (isvar (&opP->disp))
2760 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2761 break;
2762 case '3':
2763 tmpreg &= 0xFF;
2764 case '8':
2765 case 'C':
2766 case 'j':
2767 install_operand (s[1], tmpreg);
2768 break;
2769 default:
2770 abort ();
2771 }
2772 break;
2773
2774 case '+':
2775 case '-':
2776 case 'A':
2777 case 'a':
2778 install_operand (s[1], opP->reg - ADDR);
2779 break;
2780
2781 case 'B':
3e602632 2782 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2783 switch (s[1])
2784 {
2785 case 'B':
8390138c 2786 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2787 break;
2788 case 'W':
2789 add_fix ('w', &opP->disp, 1, 0);
2790 addword (0);
2791 break;
2792 case 'L':
2793 long_branch:
151337e8 2794 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2795 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2796 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2797 add_fix ('l', &opP->disp, 1, 0);
2798 addword (0);
2799 addword (0);
2800 break;
2801 case 'g':
36759679 2802 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2803 goto long_branch;
2804
2805#ifdef OBJ_ELF
2806 /* If the displacement needs pic relocation it cannot be
2807 relaxed. */
2808 if (opP->disp.pic_reloc != pic_none)
2809 goto long_branch;
2810#endif
252b5132 2811 /* This could either be a symbol, or an absolute
151337e8
NC		 2812 address. If it's an absolute address, turn it into
2813 an absolute jump right here and keep it out of the
2814 relaxer. */
2815 if (adds (&opP->disp) == 0)
2816 {
2817 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2818 the_ins.opcode[0] = 0x4EF9;
151337e8 2819 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2820 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2821 else /* jCC */
2822 {
2823 the_ins.opcode[0] ^= 0x0100;
2824 the_ins.opcode[0] |= 0x0006;
18566f55 2825 addword (0x4EF9);
151337e8
NC		 2826 }
2827 add_fix ('l', &opP->disp, 0, 0);
2828 addword (0);
2829 addword (0);
2830 break;
2831 }
2832
2833 /* Now we know it's going into the relaxer. Now figure
2834 out which mode. We try in this order of preference:
2835 long branch, absolute jump, byte/word branches only. */
2836 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2837 add_frag (adds (&opP->disp),
2838 SEXT (offs (&opP->disp)),
151337e8
NC		 2839 TAB (BRANCHBWL, SZ_UNDEF));
2840 else if (! flag_keep_pcrel)
2841 {
2842 if ((the_ins.opcode[0] == 0x6000)
2843 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2844 add_frag (adds (&opP->disp),
2845 SEXT (offs (&opP->disp)),
151337e8
NC		 2846 TAB (BRABSJUNC, SZ_UNDEF));
2847 else
bd17c2c3
AM		 2848 add_frag (adds (&opP->disp),
2849 SEXT (offs (&opP->disp)),
151337e8
NC		 2850 TAB (BRABSJCOND, SZ_UNDEF));
2851 }
252b5132 2852 else
bd17c2c3
AM		 2853 add_frag (adds (&opP->disp),
2854 SEXT (offs (&opP->disp)),
151337e8 2855 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2856 break;
2857 case 'w':
2858 if (isvar (&opP->disp))
2859 {
151337e8
NC		 2860 /* Check for DBcc instructions. We can relax them,
2861 but only if we have long branches and/or absolute
2862 jumps. */
2863 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2864 && (HAVE_LONG_BRANCH (current_architecture)
2865 || (! flag_keep_pcrel)))
252b5132 2866 {
151337e8 2867 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2868 add_frag (adds (&opP->disp),
2869 SEXT (offs (&opP->disp)),
151337e8
NC		 2870 TAB (DBCCLBR, SZ_UNDEF));
2871 else
bd17c2c3
AM		 2872 add_frag (adds (&opP->disp),
2873 SEXT (offs (&opP->disp)),
151337e8 2874 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2875 break;
2876 }
252b5132
RH		 2877 add_fix ('w', &opP->disp, 1, 0);
2878 }
2879 addword (0);
2880 break;
36759679 2881 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2882 add_fix ('l', &opP->disp, 1, 0);
2883 addword (0);
2884 addword (0);
2885 break;
36759679 2886 case 'c': /* Var size Coprocesssor branches. */
151337e8 2887 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2888 {
252b5132
RH		 2889 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2890 add_fix ('l', &opP->disp, 1, 0);
2891 addword (0);
2892 addword (0);
2893 }
151337e8 2894 else
bd17c2c3
AM		 2895 add_frag (adds (&opP->disp),
2896 SEXT (offs (&opP->disp)),
151337e8 2897 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2898 break;
2899 default:
2900 abort ();
2901 }
2902 break;
2903
36759679 2904 case 'C': /* Ignore it. */
252b5132
RH		 2905 break;
2906
36759679 2907 case 'd': /* JF this is a kludge. */
252b5132 2908 install_operand ('s', opP->reg - ADDR);
3e602632 2909 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2910 if (!issword (tmpreg))
2911 {
2912 as_warn (_("Expression out of range, using 0"));
2913 tmpreg = 0;
2914 }
2915 addword (tmpreg);
2916 break;
2917
2918 case 'D':
2919 install_operand (s[1], opP->reg - DATA);
2920 break;
2921
fd99574b
NC		 2922 case 'e': /* EMAC ACCx, reg/reg. */
2923 install_operand (s[1], opP->reg - ACC);
2924 break;
2925
36759679 2926 case 'E': /* Ignore it. */
6da466c7
ILT		 2927 break;
2928
252b5132
RH		 2929 case 'F':
2930 install_operand (s[1], opP->reg - FP0);
2931 break;
2932
fd99574b
NC		 2933 case 'g': /* EMAC ACCEXTx. */
2934 install_operand (s[1], opP->reg - ACCEXT01);
2935 break;
2936
36759679 2937 case 'G': /* Ignore it. */
6da466c7
ILT		 2938 case 'H':
2939 break;
2940
252b5132
RH		 2941 case 'I':
2942 tmpreg = opP->reg - COP0;
2943 install_operand (s[1], tmpreg);
2944 break;
2945
fd99574b
NC		 2946 case 'i': /* MAC/EMAC scale factor. */
2947 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2948 break;
2949
36759679 2950 case 'J': /* JF foo. */
252b5132
RH		 2951 switch (opP->reg)
2952 {
2953 case SFC:
2954 tmpreg = 0x000;
2955 break;
2956 case DFC:
2957 tmpreg = 0x001;
2958 break;
2959 case CACR:
2960 tmpreg = 0x002;
2961 break;
2962 case TC:
2963 tmpreg = 0x003;
2964 break;
3e602632 2965 case ACR0:
252b5132
RH		 2966 case ITT0:
2967 tmpreg = 0x004;
2968 break;
3e602632 2969 case ACR1:
252b5132
RH		 2970 case ITT1:
2971 tmpreg = 0x005;
2972 break;
3e602632 2973 case ACR2:
252b5132
RH		 2974 case DTT0:
2975 tmpreg = 0x006;
2976 break;
3e602632 2977 case ACR3:
252b5132
RH		 2978 case DTT1:
2979 tmpreg = 0x007;
2980 break;
2981 case BUSCR:
2982 tmpreg = 0x008;
2983 break;
2984
2985 case USP:
2986 tmpreg = 0x800;
2987 break;
2988 case VBR:
2989 tmpreg = 0x801;
2990 break;
2991 case CAAR:
2992 tmpreg = 0x802;
2993 break;
2994 case MSP:
2995 tmpreg = 0x803;
2996 break;
2997 case ISP:
2998 tmpreg = 0x804;
2999 break;
3000 case MMUSR:
3001 tmpreg = 0x805;
3002 break;
3003 case URP:
3004 tmpreg = 0x806;
3005 break;
3006 case SRP:
3007 tmpreg = 0x807;
3008 break;
3009 case PCR:
3010 tmpreg = 0x808;
3011 break;
3012 case ROMBAR:
3013 tmpreg = 0xC00;
3014 break;
3e602632
NC		 3015 case ROMBAR1:
3016 tmpreg = 0xC01;
3017 break;
3018 case FLASHBAR:
252b5132
RH		 3019 case RAMBAR0:
3020 tmpreg = 0xC04;
3021 break;
3e602632 3022 case RAMBAR:
252b5132
RH		 3023 case RAMBAR1:
3024 tmpreg = 0xC05;
3025 break;
3e602632
NC		 3026 case MPCR:
3027 tmpreg = 0xC0C;
3028 break;
3029 case EDRAMBAR:
3030 tmpreg = 0xC0D;
3031 break;
3032 case MBAR0:
e80e0390 3033 case MBAR2:
3e602632
NC		 3034 case SECMBAR:
3035 tmpreg = 0xC0E;
3036 break;
3037 case MBAR1:
252b5132
RH		 3038 case MBAR:
3039 tmpreg = 0xC0F;
3040 break;
3e602632
NC		 3041 case PCR1U0:
3042 tmpreg = 0xD02;
3043 break;
3044 case PCR1L0:
3045 tmpreg = 0xD03;
3046 break;
3047 case PCR2U0:
3048 tmpreg = 0xD04;
3049 break;
3050 case PCR2L0:
3051 tmpreg = 0xD05;
3052 break;
3053 case PCR3U0:
3054 tmpreg = 0xD06;
3055 break;
3056 case PCR3L0:
3057 tmpreg = 0xD07;
3058 break;
3059 case PCR1L1:
3060 tmpreg = 0xD0A;
3061 break;
3062 case PCR1U1:
3063 tmpreg = 0xD0B;
3064 break;
3065 case PCR2L1:
3066 tmpreg = 0xD0C;
3067 break;
3068 case PCR2U1:
3069 tmpreg = 0xD0D;
3070 break;
3071 case PCR3L1:
3072 tmpreg = 0xD0E;
3073 break;
3074 case PCR3U1:
3075 tmpreg = 0xD0F;
3076 break;
252b5132
RH		 3077 default:
3078 abort ();
3079 }
3080 install_operand (s[1], tmpreg);
3081 break;
3082
3083 case 'k':
3084 tmpreg = get_num (&opP->disp, 55);
3085 install_operand (s[1], tmpreg & 0x7f);
3086 break;
3087
3088 case 'l':
3089 tmpreg = opP->mask;
3090 if (s[1] == 'w')
3091 {
3092 if (tmpreg & 0x7FF0000)
3093 as_bad (_("Floating point register in register list"));
3094 insop (reverse_16_bits (tmpreg), opcode);
3095 }
3096 else
3097 {
3098 if (tmpreg & 0x700FFFF)
3099 as_bad (_("Wrong register in floating-point reglist"));
3100 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3101 }
3102 break;
3103
3104 case 'L':
3105 tmpreg = opP->mask;
3106 if (s[1] == 'w')
3107 {
3108 if (tmpreg & 0x7FF0000)
3109 as_bad (_("Floating point register in register list"));
3110 insop (tmpreg, opcode);
3111 }
3112 else if (s[1] == '8')
3113 {
3114 if (tmpreg & 0x0FFFFFF)
3115 as_bad (_("incorrect register in reglist"));
3116 install_operand (s[1], tmpreg >> 24);
3117 }
3118 else
3119 {
3120 if (tmpreg & 0x700FFFF)
3121 as_bad (_("wrong register in floating-point reglist"));
3122 else
3123 install_operand (s[1], tmpreg >> 16);
3124 }
3125 break;
3126
3127 case 'M':
3128 install_operand (s[1], get_num (&opP->disp, 60));
3129 break;
3130
3131 case 'O':
3132 tmpreg = ((opP->mode == DREG)
8fce3f5e 3133 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3134 : (get_num (&opP->disp, 40) & 0x1F));
3135 install_operand (s[1], tmpreg);
3136 break;
3137
3138 case 'Q':
3139 tmpreg = get_num (&opP->disp, 10);
3140 if (tmpreg == 8)
3141 tmpreg = 0;
3142 install_operand (s[1], tmpreg);
3143 break;
3144
3145 case 'R':
3146 /* This depends on the fact that ADDR registers are eight
3147 more than their corresponding DATA regs, so the result
36759679 3148 will have the ADDR_REG bit set. */
252b5132
RH		 3149 install_operand (s[1], opP->reg - DATA);
3150 break;
3151
3152 case 'r':
3153 if (opP->mode == AINDR)
3154 install_operand (s[1], opP->reg - DATA);
3155 else
3156 install_operand (s[1], opP->index.reg - DATA);
3157 break;
3158
3159 case 's':
3160 if (opP->reg == FPI)
3161 tmpreg = 0x1;
3162 else if (opP->reg == FPS)
3163 tmpreg = 0x2;
3164 else if (opP->reg == FPC)
3165 tmpreg = 0x4;
3166 else
3167 abort ();
3168 install_operand (s[1], tmpreg);
3169 break;
3170
36759679 3171 case 'S': /* Ignore it. */
252b5132
RH		 3172 break;
3173
3174 case 'T':
3175 install_operand (s[1], get_num (&opP->disp, 30));
3176 break;
3177
36759679 3178 case 'U': /* Ignore it. */
252b5132
RH		 3179 break;
3180
3181 case 'c':
3182 switch (opP->reg)
3183 {
3184 case NC:
3185 tmpreg = 0;
3186 break;
3187 case DC:
3188 tmpreg = 1;
3189 break;
3190 case IC:
3191 tmpreg = 2;
3192 break;
3193 case BC:
3194 tmpreg = 3;
3195 break;
3196 default:
3197 as_fatal (_("failed sanity check"));
36759679 3198 } /* switch on cache token. */
252b5132
RH		 3199 install_operand (s[1], tmpreg);
3200 break;
3201#ifndef NO_68851
92774660 3202 /* JF: These are out of order, I fear. */
252b5132
RH		 3203 case 'f':
3204 switch (opP->reg)
3205 {
3206 case SFC:
3207 tmpreg = 0;
3208 break;
3209 case DFC:
3210 tmpreg = 1;
3211 break;
3212 default:
3213 abort ();
3214 }
3215 install_operand (s[1], tmpreg);
3216 break;
3217
3218 case '0':
3219 case '1':
3220 case '2':
3221 switch (opP->reg)
3222 {
3223 case TC:
3224 tmpreg = 0;
3225 break;
3226 case CAL:
3227 tmpreg = 4;
3228 break;
3229 case VAL:
3230 tmpreg = 5;
3231 break;
3232 case SCC:
3233 tmpreg = 6;
3234 break;
3235 case AC:
3236 tmpreg = 7;
3237 break;
3238 default:
3239 abort ();
3240 }
3241 install_operand (s[1], tmpreg);
3242 break;
3243
3244 case 'V':
3245 if (opP->reg == VAL)
3246 break;
3247 abort ();
3248
3249 case 'W':
3250 switch (opP->reg)
3251 {
3252 case DRP:
3253 tmpreg = 1;
3254 break;
3255 case SRP:
3256 tmpreg = 2;
3257 break;
3258 case CRP:
3259 tmpreg = 3;
3260 break;
3261 default:
3262 abort ();
3263 }
3264 install_operand (s[1], tmpreg);
3265 break;
3266
3267 case 'X':
3268 switch (opP->reg)
3269 {
3270 case BAD:
3271 case BAD + 1:
3272 case BAD + 2:
3273 case BAD + 3:
3274 case BAD + 4:
3275 case BAD + 5:
3276 case BAD + 6:
3277 case BAD + 7:
3278 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3279 break;
3280
3281 case BAC:
3282 case BAC + 1:
3283 case BAC + 2:
3284 case BAC + 3:
3285 case BAC + 4:
3286 case BAC + 5:
3287 case BAC + 6:
3288 case BAC + 7:
3289 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3290 break;
3291
3292 default:
3293 abort ();
3294 }
3295 install_operand (s[1], tmpreg);
3296 break;
3297 case 'Y':
3298 know (opP->reg == PSR);
3299 break;
3300 case 'Z':
3301 know (opP->reg == PCSR);
3302 break;
3303#endif /* m68851 */
3304 case '3':
3305 switch (opP->reg)
3306 {
3307 case TT0:
3308 tmpreg = 2;
3309 break;
3310 case TT1:
3311 tmpreg = 3;
3312 break;
3313 default:
3314 abort ();
3315 }
3316 install_operand (s[1], tmpreg);
3317 break;
3318 case 't':
3319 tmpreg = get_num (&opP->disp, 20);
3320 install_operand (s[1], tmpreg);
3321 break;
36759679 3322 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3323 if (isvar (&opP->disp))
3324 add_fix ('l', &opP->disp, 0, 0);
3e602632 3325 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3326 addword (tmpreg >> 16);
3327 addword (tmpreg & 0xFFFF);
3328 break;
6da466c7
ILT		 3329 case 'u':
3330 install_operand (s[1], opP->reg - DATA0L);
3331 opP->reg -= (DATA0L);
36759679 3332 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3333 break;
3e602632
NC		 3334 case 'x':
3335 tmpreg = get_num (&opP->disp, 80);
3336 if (tmpreg == -1)
3337 tmpreg = 0;
3338 install_operand (s[1], tmpreg);
3339 break;
252b5132
RH		 3340 default:
3341 abort ();
3342 }
3343 }
3344
3345 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3346 instruction, ready to be emitted. . . */
252b5132
RH		 3347}
3348
3349static int
31302357 3350reverse_16_bits (int in)
252b5132
RH		 3351{
3352 int out = 0;
3353 int n;
3354
3355 static int mask[16] =
3356 {
3357 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3358 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3359 };
3360 for (n = 0; n < 16; n++)
3361 {
3362 if (in & mask[n])
3363 out |= mask[15 - n];
3364 }
3365 return out;
3366} /* reverse_16_bits() */
3367
3368static int
31302357 3369reverse_8_bits (int in)
252b5132
RH		 3370{
3371 int out = 0;
3372 int n;
3373
3374 static int mask[8] =
3375 {
3376 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3377 };
3378
3379 for (n = 0; n < 8; n++)
3380 {
3381 if (in & mask[n])
3382 out |= mask[7 - n];
3383 }
3384 return out;
3385} /* reverse_8_bits() */
3386
3387/* Cause an extra frag to be generated here, inserting up to 10 bytes
3388 (that value is chosen in the frag_var call in md_assemble). TYPE
3389 is the subtype of the frag to be generated; its primary type is
3390 rs_machine_dependent.
3391
3392 The TYPE parameter is also used by md_convert_frag_1 and
3393 md_estimate_size_before_relax. The appropriate type of fixup will
3394 be emitted by md_convert_frag_1.
3395
3396 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3397static void
31302357 3398install_operand (int mode, int val)
252b5132
RH		 3399{
3400 switch (mode)
3401 {
3402 case 's':
36759679 3403 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3404 break;
3405 case 'd':
3406 the_ins.opcode[0] |= val << 9;
3407 break;
3408 case '1':
3409 the_ins.opcode[1] |= val << 12;
3410 break;
3411 case '2':
3412 the_ins.opcode[1] |= val << 6;
3413 break;
3414 case '3':
3415 the_ins.opcode[1] |= val;
3416 break;
3417 case '4':
3418 the_ins.opcode[2] |= val << 12;
3419 break;
3420 case '5':
3421 the_ins.opcode[2] |= val << 6;
3422 break;
3423 case '6':
3424 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3425 three words long! */
3426 the_ins.numo++;
3427 the_ins.opcode[2] |= val;
3428 break;
3429 case '7':
3430 the_ins.opcode[1] |= val << 7;
3431 break;
3432 case '8':
3433 the_ins.opcode[1] |= val << 10;
3434 break;
3435#ifndef NO_68851
3436 case '9':
3437 the_ins.opcode[1] |= val << 5;
3438 break;
3439#endif
3440
3441 case 't':
3442 the_ins.opcode[1] |= (val << 10) | (val << 7);
3443 break;
3444 case 'D':
3445 the_ins.opcode[1] |= (val << 12) | val;
3446 break;
3447 case 'g':
3448 the_ins.opcode[0] |= val = 0xff;
3449 break;
3450 case 'i':
3451 the_ins.opcode[0] |= val << 9;
3452 break;
3453 case 'C':
3454 the_ins.opcode[1] |= val;
3455 break;
3456 case 'j':
3457 the_ins.opcode[1] |= val;
36759679 3458 the_ins.numo++; /* What a hack. */
252b5132
RH		 3459 break;
3460 case 'k':
3461 the_ins.opcode[1] |= val << 4;
3462 break;
3463 case 'b':
3464 case 'w':
3465 case 'W':
3466 case 'l':
3467 break;
3468 case 'e':
3469 the_ins.opcode[0] |= (val << 6);
3470 break;
3471 case 'L':
3472 the_ins.opcode[1] = (val >> 16);
3473 the_ins.opcode[2] = val & 0xffff;
3474 break;
6da466c7
ILT		 3475 case 'm':
3476 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3477 the_ins.opcode[0] |= ((val & 0x7) << 9);
3478 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3479 break;
fd99574b 3480 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3481 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3482 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3483 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3484 break;
fd99574b 3485 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3486 the_ins.opcode[1] |= val << 12;
3487 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3488 break;
fd99574b 3489 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3490 the_ins.opcode[0] |= (val & 0xF);
3491 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3492 break;
fd99574b 3493 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3494 the_ins.opcode[1] |= (val & 0xF);
3495 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3496 break;
3497 case 'h':
3498 the_ins.opcode[1] |= ((val != 1) << 10);
3499 break;
fd99574b
NC		 3500 case 'F':
3501 the_ins.opcode[0] |= ((val & 0x3) << 9);
3502 break;
3503 case 'f':
3504 the_ins.opcode[0] |= ((val & 0x3) << 0);
3505 break;
be8c092b 3506 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3507 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3508 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3509 break;
be8c092b 3510 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3511 the_ins.opcode[0] |= ((val & 0x1) << 7);
3512 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3513 break;
3514 case 'I':
3515 the_ins.opcode[1] |= ((val & 0x3) << 9);
3516 break;
3517 case ']':
3518 the_ins.opcode[0] |= (val & 0x1) <<10;
3519 break;
252b5132
RH		 3520 case 'c':
3521 default:
3522 as_fatal (_("failed sanity check."));
3523 }
6b6e92f4 3524}
252b5132
RH		 3525
3526static void
31302357 3527install_gen_operand (int mode, int val)
252b5132
RH		 3528{
3529 switch (mode)
3530 {
fd99574b
NC		 3531 case '/': /* Special for mask loads for mac/msac insns with
3532 possible mask; trailing_ampersend set in bit 8. */
3533 the_ins.opcode[0] |= (val & 0x3f);
3534 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3535 break;
252b5132
RH		 3536 case 's':
3537 the_ins.opcode[0] |= val;
3538 break;
3539 case 'd':
3540 /* This is a kludge!!! */
3541 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3542 break;
3543 case 'b':
3544 case 'w':
3545 case 'l':
3546 case 'f':
3547 case 'F':
3548 case 'x':
3549 case 'p':
3550 the_ins.opcode[0] |= val;
3551 break;
36759679 3552 /* more stuff goes here. */
252b5132
RH		 3553 default:
3554 as_fatal (_("failed sanity check."));
3555 }
6b6e92f4 3556}
252b5132 3557
6b6e92f4
NC		 3558/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3559 then deal with the bitfield hack. */
252b5132
RH		 3560
3561static char *
31302357 3562crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3563{
3564 register int parens;
3565 register int c;
3566 register char *beg_str;
3567 int inquote = 0;
3568
3569 if (!str)
3570 {
3571 return str;
3572 }
3573 beg_str = str;
3574 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3575 {
3576 if (! inquote)
3577 {
3578 if (*str == '(')
3579 parens++;
3580 else if (*str == ')')
3581 {
3582 if (!parens)
36759679 3583 { /* ERROR. */
252b5132
RH		 3584 opP->error = _("Extra )");
3585 return str;
3586 }
3587 --parens;
3588 }
3589 }
3590 if (flag_mri && *str == '\'')
3591 inquote = ! inquote;
3592 }
3593 if (!*str && parens)
36759679 3594 { /* ERROR. */
252b5132
RH		 3595 opP->error = _("Missing )");
3596 return str;
3597 }
3598 c = *str;
3599 *str = '\0';
3600 if (m68k_ip_op (beg_str, opP) != 0)
3601 {
3602 *str = c;
3603 return str;
3604 }
3605 *str = c;
3606 if (c == '}')
36759679 3607 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3608 if (c)
3609 {
3610 c = *++str;
3611 if (!c)
3612 as_bad (_("Missing operand"));
3613 }
3614
3615 /* Detect MRI REG symbols and convert them to REGLSTs. */
3616 if (opP->mode == CONTROL && (int)opP->reg < 0)
3617 {
3618 opP->mode = REGLST;
3619 opP->mask = ~(int)opP->reg;
3620 opP->reg = 0;
3621 }
3622
3623 return str;
3624}
3625
3626/* This is the guts of the machine-dependent assembler. STR points to a
3627 machine dependent instruction. This function is supposed to emit
3628 the frags/bytes it assembles to.
3629 */
3630
3631static void
31302357 3632insert_reg (const char *regname, int regnum)
252b5132
RH		 3633{
3634 char buf[100];
3635 int i;
3636
3637#ifdef REGISTER_PREFIX
3638 if (!flag_reg_prefix_optional)
3639 {
3640 buf[0] = REGISTER_PREFIX;
3641 strcpy (buf + 1, regname);
3642 regname = buf;
3643 }
3644#endif
3645
3646 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3647 &zero_address_frag));
3648
3649 for (i = 0; regname[i]; i++)
3882b010 3650 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3651 buf[i] = '\0';
3652
3653 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3654 &zero_address_frag));
3655}
3656
3657struct init_entry
3658 {
3659 const char *name;
3660 int number;
3661 };
3662
3663static const struct init_entry init_table[] =
3664{
3665 { "d0", DATA0 },
3666 { "d1", DATA1 },
3667 { "d2", DATA2 },
3668 { "d3", DATA3 },
3669 { "d4", DATA4 },
3670 { "d5", DATA5 },
3671 { "d6", DATA6 },
3672 { "d7", DATA7 },
3673 { "a0", ADDR0 },
3674 { "a1", ADDR1 },
3675 { "a2", ADDR2 },
3676 { "a3", ADDR3 },
3677 { "a4", ADDR4 },
3678 { "a5", ADDR5 },
3679 { "a6", ADDR6 },
3680 { "fp", ADDR6 },
3681 { "a7", ADDR7 },
3682 { "sp", ADDR7 },
3683 { "ssp", ADDR7 },
3684 { "fp0", FP0 },
3685 { "fp1", FP1 },
3686 { "fp2", FP2 },
3687 { "fp3", FP3 },
3688 { "fp4", FP4 },
3689 { "fp5", FP5 },
3690 { "fp6", FP6 },
3691 { "fp7", FP7 },
3692 { "fpi", FPI },
3693 { "fpiar", FPI },
3694 { "fpc", FPI },
3695 { "fps", FPS },
3696 { "fpsr", FPS },
3697 { "fpc", FPC },
3698 { "fpcr", FPC },
3699 { "control", FPC },
3700 { "status", FPS },
3701 { "iaddr", FPI },
3702
3703 { "cop0", COP0 },
3704 { "cop1", COP1 },
3705 { "cop2", COP2 },
3706 { "cop3", COP3 },
3707 { "cop4", COP4 },
3708 { "cop5", COP5 },
3709 { "cop6", COP6 },
3710 { "cop7", COP7 },
3711 { "pc", PC },
3712 { "zpc", ZPC },
3713 { "sr", SR },
3714
3715 { "ccr", CCR },
3716 { "cc", CCR },
3717
6da466c7 3718 { "acc", ACC },
fd99574b
NC		 3719 { "acc0", ACC },
3720 { "acc1", ACC1 },
3721 { "acc2", ACC2 },
3722 { "acc3", ACC3 },
3723 { "accext01", ACCEXT01 },
3724 { "accext23", ACCEXT23 },
6da466c7
ILT		 3725 { "macsr", MACSR },
3726 { "mask", MASK },
3727
36759679
NC		 3728 /* Control registers. */
3729 { "sfc", SFC }, /* Source Function Code. */
252b5132 3730 { "sfcr", SFC },
36759679 3731 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3732 { "dfcr", DFC },
36759679
NC		 3733 { "cacr", CACR }, /* Cache Control Register. */
3734 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3735
36759679
NC		 3736 { "usp", USP }, /* User Stack Pointer. */
3737 { "vbr", VBR }, /* Vector Base Register. */
3738 { "msp", MSP }, /* Master Stack Pointer. */
3739 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3740
36759679
NC		 3741 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3742 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3743 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3744 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3745
3746 /* 68ec040 versions of same */
36759679
NC		 3747 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3748 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3749 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3750 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3751
3752 /* mcf5200 versions of same. The ColdFire programmer's reference
3753 manual indicated that the order is 2,3,0,1, but Ken Rose
3754 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3755 { "acr0", ACR0 }, /* Access Control Unit 0. */
3756 { "acr1", ACR1 }, /* Access Control Unit 1. */
3757 { "acr2", ACR2 }, /* Access Control Unit 2. */
3758 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3759
36759679 3760 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3761 { "tcr", TC },
3762
36759679
NC		 3763 { "mmusr", MMUSR }, /* MMU Status Register. */
3764 { "srp", SRP }, /* User Root Pointer. */
3765 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3766
3767 { "buscr", BUSCR },
3768 { "pcr", PCR },
3769
36759679
NC		 3770 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3771 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3772 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3773 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3774
3775 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3776 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3777 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3778 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3779 { "mpcr", MPCR }, /* mcfv4e registers. */
3780 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3781 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3782 { "asid", TC }, /* mcfv4e registers. */
3783 { "mmubar", BUSCR }, /* mcfv4e registers. */
3784 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3785 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3786 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3787 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3788 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3789 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3790 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3791 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3792 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3793 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3794 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3795 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3796
3797 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3798 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3799
3800 { "mbar2", MBAR2 }, /* mcf5249 registers. */
36759679 3801 /* End of control registers. */
252b5132
RH		 3802
3803 { "ac", AC },
3804 { "bc", BC },
3805 { "cal", CAL },
3806 { "crp", CRP },
3807 { "drp", DRP },
3808 { "pcsr", PCSR },
3809 { "psr", PSR },
3810 { "scc", SCC },
3811 { "val", VAL },
3812 { "bad0", BAD0 },
3813 { "bad1", BAD1 },
3814 { "bad2", BAD2 },
3815 { "bad3", BAD3 },
3816 { "bad4", BAD4 },
3817 { "bad5", BAD5 },
3818 { "bad6", BAD6 },
3819 { "bad7", BAD7 },
3820 { "bac0", BAC0 },
3821 { "bac1", BAC1 },
3822 { "bac2", BAC2 },
3823 { "bac3", BAC3 },
3824 { "bac4", BAC4 },
3825 { "bac5", BAC5 },
3826 { "bac6", BAC6 },
3827 { "bac7", BAC7 },
3828
3829 { "ic", IC },
3830 { "dc", DC },
3831 { "nc", NC },
3832
3833 { "tt0", TT0 },
3834 { "tt1", TT1 },
36759679 3835 /* 68ec030 versions of same. */
252b5132
RH		 3836 { "ac0", TT0 },
3837 { "ac1", TT1 },
36759679 3838 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3839 { "acusr", PSR },
3840
3841 /* Suppressed data and address registers. */
3842 { "zd0", ZDATA0 },
3843 { "zd1", ZDATA1 },
3844 { "zd2", ZDATA2 },
3845 { "zd3", ZDATA3 },
3846 { "zd4", ZDATA4 },
3847 { "zd5", ZDATA5 },
3848 { "zd6", ZDATA6 },
3849 { "zd7", ZDATA7 },
3850 { "za0", ZADDR0 },
3851 { "za1", ZADDR1 },
3852 { "za2", ZADDR2 },
3853 { "za3", ZADDR3 },
3854 { "za4", ZADDR4 },
3855 { "za5", ZADDR5 },
3856 { "za6", ZADDR6 },
3857 { "za7", ZADDR7 },
3858
92774660 3859 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3860 { "d0l", DATA0L },
3861 { "d1l", DATA1L },
3862 { "d2l", DATA2L },
3863 { "d3l", DATA3L },
3864 { "d4l", DATA4L },
3865 { "d5l", DATA5L },
3866 { "d6l", DATA6L },
3867 { "d7l", DATA7L },
3868
3869 { "a0l", ADDR0L },
3870 { "a1l", ADDR1L },
3871 { "a2l", ADDR2L },
3872 { "a3l", ADDR3L },
3873 { "a4l", ADDR4L },
3874 { "a5l", ADDR5L },
3875 { "a6l", ADDR6L },
3876 { "a7l", ADDR7L },
3877
3878 { "d0u", DATA0U },
3879 { "d1u", DATA1U },
3880 { "d2u", DATA2U },
3881 { "d3u", DATA3U },
3882 { "d4u", DATA4U },
3883 { "d5u", DATA5U },
3884 { "d6u", DATA6U },
3885 { "d7u", DATA7U },
3886
3887 { "a0u", ADDR0U },
3888 { "a1u", ADDR1U },
3889 { "a2u", ADDR2U },
3890 { "a3u", ADDR3U },
3891 { "a4u", ADDR4U },
3892 { "a5u", ADDR5U },
3893 { "a6u", ADDR6U },
3894 { "a7u", ADDR7U },
3895
252b5132
RH		 3896 { 0, 0 }
3897};
3898
3899static void
31302357 3900init_regtable (void)
252b5132
RH		 3901{
3902 int i;
3903 for (i = 0; init_table[i].name; i++)
3904 insert_reg (init_table[i].name, init_table[i].number);
3905}
3906
252b5132 3907void
31302357 3908md_assemble (char *str)
252b5132
RH		 3909{
3910 const char *er;
3911 short *fromP;
3912 char *toP = NULL;
3913 int m, n = 0;
3914 char *to_beg_P;
3915 int shorts_this_frag;
3916 fixS *fixP;
3917
266abb8f
NS		 3918 if (!selected_cpu && !selected_arch)
3919 {
3920 /* We've not selected an architecture yet. Set the default
3921 now. We do this lazily so that an initial .cpu or .arch directive
3922 can specify. */
3923 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3924 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3925 }
3926 if (!initialized)
3927 m68k_init_arch ();
3928
252b5132
RH		 3929 /* In MRI mode, the instruction and operands are separated by a
3930 space. Anything following the operands is a comment. The label
3931 has already been removed. */
3932 if (flag_mri)
3933 {
3934 char *s;
3935 int fields = 0;
3936 int infield = 0;
3937 int inquote = 0;
3938
3939 for (s = str; *s != '\0'; s++)
3940 {
3941 if ((*s == ' ' || *s == '\t') && ! inquote)
3942 {
3943 if (infield)
3944 {
3945 ++fields;
3946 if (fields >= 2)
3947 {
3948 *s = '\0';
3949 break;
3950 }
3951 infield = 0;
3952 }
3953 }
3954 else
3955 {
3956 if (! infield)
3957 infield = 1;
3958 if (*s == '\'')
3959 inquote = ! inquote;
3960 }
3961 }
3962 }
3963
31302357 3964 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 3965 m68k_ip (str);
3966 er = the_ins.error;
3967 if (!er)
3968 {
3969 for (n = 0; n < the_ins.numargs; n++)
3970 if (the_ins.operands[n].error)
3971 {
3972 er = the_ins.operands[n].error;
3973 break;
3974 }
3975 }
3976 if (er)
3977 {
3978 as_bad (_("%s -- statement `%s' ignored"), er, str);
3979 return;
3980 }
3981
3982 /* If there is a current label, record that it marks an instruction. */
3983 if (current_label != NULL)
3984 {
3985 current_label->text = 1;
3986 current_label = NULL;
3987 }
3988
f27a3839
AS		 3989#ifdef OBJ_ELF
3990 /* Tie dwarf2 debug info to the address at the start of the insn. */
3991 dwarf2_emit_insn (0);
3992#endif
3993
252b5132
RH		 3994 if (the_ins.nfrag == 0)
3995 {
36759679 3996 /* No frag hacking involved; just put it out. */
252b5132
RH		 3997 toP = frag_more (2 * the_ins.numo);
3998 fromP = &the_ins.opcode[0];
3999 for (m = the_ins.numo; m; --m)
4000 {
4001 md_number_to_chars (toP, (long) (*fromP), 2);
4002 toP += 2;
4003 fromP++;
4004 }
36759679 4005 /* Put out symbol-dependent info. */
252b5132
RH		 4006 for (m = 0; m < the_ins.nrel; m++)
4007 {
4008 switch (the_ins.reloc[m].wid)
4009 {
4010 case 'B':
4011 n = 1;
4012 break;
4013 case 'b':
4014 n = 1;
4015 break;
4016 case '3':
4017 n = 1;
4018 break;
4019 case 'w':
4020 case 'W':
4021 n = 2;
4022 break;
4023 case 'l':
4024 n = 4;
4025 break;
4026 default:
4027 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4028 the_ins.reloc[m].wid);
4029 }
4030
4031 fixP = fix_new_exp (frag_now,
4032 ((toP - frag_now->fr_literal)
4033 - the_ins.numo * 2 + the_ins.reloc[m].n),
4034 n,
4035 &the_ins.reloc[m].exp,
4036 the_ins.reloc[m].pcrel,
4037 get_reloc_code (n, the_ins.reloc[m].pcrel,
4038 the_ins.reloc[m].pic_reloc));
4039 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4040 if (the_ins.reloc[m].wid == 'B')
4041 fixP->fx_signed = 1;
4042 }
4043 return;
4044 }
4045
36759679 4046 /* There's some frag hacking. */
fbe572f9
AM		 4047 {
4048 /* Calculate the max frag size. */
4049 int wid;
4050
4051 wid = 2 * the_ins.fragb[0].fragoff;
4052 for (n = 1; n < the_ins.nfrag; n++)
4053 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4054 /* frag_var part. */
4055 wid += 10;
4056 /* Make sure the whole insn fits in one chunk, in particular that
4057 the var part is attached, as we access one byte before the
4058 variable frag for byte branches. */
4059 frag_grow (wid);
4060 }
4061
252b5132
RH		 4062 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4063 {
4064 int wid;
4065
4066 if (n == 0)
4067 wid = 2 * the_ins.fragb[n].fragoff;
4068 else
4069 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4070 toP = frag_more (wid);
4071 to_beg_P = toP;
4072 shorts_this_frag = 0;
4073 for (m = wid / 2; m; --m)
4074 {
4075 md_number_to_chars (toP, (long) (*fromP), 2);
4076 toP += 2;
4077 fromP++;
4078 shorts_this_frag++;
4079 }
4080 for (m = 0; m < the_ins.nrel; m++)
4081 {
4082 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4083 {
4084 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4085 break;
4086 }
4087 wid = the_ins.reloc[m].wid;
4088 if (wid == 0)
4089 continue;
4090 the_ins.reloc[m].wid = 0;
4091 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4092
4093 fixP = fix_new_exp (frag_now,
4094 ((toP - frag_now->fr_literal)
4095 - the_ins.numo * 2 + the_ins.reloc[m].n),
4096 wid,
4097 &the_ins.reloc[m].exp,
4098 the_ins.reloc[m].pcrel,
4099 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4100 the_ins.reloc[m].pic_reloc));
4101 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4102 }
4103 (void) frag_var (rs_machine_dependent, 10, 0,
4104 (relax_substateT) (the_ins.fragb[n].fragty),
4105 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4106 }
4107 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4108 shorts_this_frag = 0;
4109 if (n)
4110 {
055d1eb0 4111 toP = frag_more (n * 2);
252b5132
RH		 4112 while (n--)
4113 {
4114 md_number_to_chars (toP, (long) (*fromP), 2);
4115 toP += 2;
4116 fromP++;
4117 shorts_this_frag++;
4118 }
4119 }
4120 for (m = 0; m < the_ins.nrel; m++)
4121 {
4122 int wid;
4123
4124 wid = the_ins.reloc[m].wid;
4125 if (wid == 0)
4126 continue;
4127 the_ins.reloc[m].wid = 0;
4128 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4129
4130 fixP = fix_new_exp (frag_now,
4131 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4132 - shorts_this_frag * 2),
4133 wid,
4134 &the_ins.reloc[m].exp,
4135 the_ins.reloc[m].pcrel,
4136 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4137 the_ins.reloc[m].pic_reloc));
4138 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4139 }
4140}
4141
60fed2d3
NC		 4142/* Comparison function used by qsort to rank the opcode entries by name. */
4143
4144static int
4145m68k_compare_opcode (const void * v1, const void * v2)
4146{
4147 struct m68k_opcode * op1, * op2;
4148 int ret;
4149
03b13e59
NC		 4150 if (v1 == v2)
4151 return 0;
4152
60fed2d3
NC		 4153 op1 = *(struct m68k_opcode **) v1;
4154 op2 = *(struct m68k_opcode **) v2;
4155
4156 /* Compare the two names. If different, return the comparison.
4157 If the same, return the order they are in the opcode table. */
4158 ret = strcmp (op1->name, op2->name);
4159 if (ret)
4160 return ret;
4161 if (op1 < op2)
4162 return -1;
03b13e59 4163 return 1;
60fed2d3
NC		 4164}
4165
252b5132 4166void
60fed2d3 4167md_begin (void)
252b5132 4168{
60fed2d3
NC		 4169 const struct m68k_opcode *ins;
4170 struct m68k_incant *hack, *slak;
4171 const char *retval = 0; /* Empty string, or error msg text. */
4172 int i;
4173
4174 /* Set up hash tables with 68000 instructions.
4175 similar to what the vax assembler does. */
252b5132
RH		 4176 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4177 a copy of it at runtime, adding in the information we want but isn't
4178 there. I think it'd be better to have an awk script hack the table
4179 at compile time. Or even just xstr the table and use it as-is. But
4180 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4181 names. */
4182
252b5132
RH		 4183 if (flag_mri)
4184 {
4185 flag_reg_prefix_optional = 1;
4186 m68k_abspcadd = 1;
4187 if (! m68k_rel32_from_cmdline)
4188 m68k_rel32 = 0;
4189 }
4190
60fed2d3
NC		 4191 /* First sort the opcode table into alphabetical order to seperate
4192 the order that the assembler wants to see the opcodes from the
4193 order that the disassembler wants to see them. */
4194 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4195 if (!m68k_sorted_opcodes)
4196 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4197 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4198
4199 for (i = m68k_numopcodes; i--;)
4200 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4201
4202 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4203 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4204
252b5132
RH		 4205 op_hash = hash_new ();
4206
4207 obstack_begin (&robyn, 4000);
4208 for (i = 0; i < m68k_numopcodes; i++)
4209 {
4210 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4211 do
4212 {
60fed2d3
NC		 4213 ins = m68k_sorted_opcodes[i];
4214
4215 /* We *could* ignore insns that don't match our
4216 arch here by just leaving them out of the hash. */
252b5132
RH		 4217 slak->m_operands = ins->args;
4218 slak->m_opnum = strlen (slak->m_operands) / 2;
4219 slak->m_arch = ins->arch;
4220 slak->m_opcode = ins->opcode;
36759679 4221 /* This is kludgey. */
252b5132
RH		 4222 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4223 if (i + 1 != m68k_numopcodes
60fed2d3 4224 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4225 {
60fed2d3 4226 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4227 i++;
4228 }
4229 else
4230 slak->m_next = 0;
4231 slak = slak->m_next;
4232 }
4233 while (slak);
4234
4235 retval = hash_insert (op_hash, ins->name, (char *) hack);
4236 if (retval)
4237 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4238 }
4239
4240 for (i = 0; i < m68k_numaliases; i++)
4241 {
4242 const char *name = m68k_opcode_aliases[i].primary;
4243 const char *alias = m68k_opcode_aliases[i].alias;
4244 PTR val = hash_find (op_hash, name);
60fed2d3 4245
252b5132
RH		 4246 if (!val)
4247 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4248 retval = hash_insert (op_hash, alias, val);
4249 if (retval)
4250 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4251 }
4252
4253 /* In MRI mode, all unsized branches are variable sized. Normally,
4254 they are word sized. */
4255 if (flag_mri)
4256 {
4257 static struct m68k_opcode_alias mri_aliases[] =
4258 {
4259 { "bhi", "jhi", },
4260 { "bls", "jls", },
4261 { "bcc", "jcc", },
4262 { "bcs", "jcs", },
4263 { "bne", "jne", },
4264 { "beq", "jeq", },
4265 { "bvc", "jvc", },
4266 { "bvs", "jvs", },
4267 { "bpl", "jpl", },
4268 { "bmi", "jmi", },
4269 { "bge", "jge", },
4270 { "blt", "jlt", },
4271 { "bgt", "jgt", },
4272 { "ble", "jle", },
4273 { "bra", "jra", },
4274 { "bsr", "jbsr", },
4275 };
4276
8fce3f5e
AM		 4277 for (i = 0;
4278 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4279 i++)
252b5132
RH		 4280 {
4281 const char *name = mri_aliases[i].primary;
4282 const char *alias = mri_aliases[i].alias;
4283 PTR val = hash_find (op_hash, name);
60fed2d3 4284
252b5132
RH		 4285 if (!val)
4286 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4287 retval = hash_jam (op_hash, alias, val);
4288 if (retval)
4289 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4290 }
4291 }
4292
8fce3f5e 4293 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4294 {
4295 notend_table[i] = 0;
4296 alt_notend_table[i] = 0;
4297 }
60fed2d3 4298
252b5132
RH		 4299 notend_table[','] = 1;
4300 notend_table['{'] = 1;
4301 notend_table['}'] = 1;
4302 alt_notend_table['a'] = 1;
4303 alt_notend_table['A'] = 1;
4304 alt_notend_table['d'] = 1;
4305 alt_notend_table['D'] = 1;
4306 alt_notend_table['#'] = 1;
4307 alt_notend_table['&'] = 1;
4308 alt_notend_table['f'] = 1;
4309 alt_notend_table['F'] = 1;
4310#ifdef REGISTER_PREFIX
4311 alt_notend_table[REGISTER_PREFIX] = 1;
4312#endif
4313
4314 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4315 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4316 alt_notend_table['('] = 1;
4317
4318 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4319 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4320 alt_notend_table['@'] = 1;
4321
4322 /* We need to put digits in alt_notend_table to handle
60fed2d3 4323 bfextu %d0{24:1},%d0 */
252b5132
RH		 4324 alt_notend_table['0'] = 1;
4325 alt_notend_table['1'] = 1;
4326 alt_notend_table['2'] = 1;
4327 alt_notend_table['3'] = 1;
4328 alt_notend_table['4'] = 1;
4329 alt_notend_table['5'] = 1;
4330 alt_notend_table['6'] = 1;
4331 alt_notend_table['7'] = 1;
4332 alt_notend_table['8'] = 1;
4333 alt_notend_table['9'] = 1;
4334
4335#ifndef MIT_SYNTAX_ONLY
4336 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4337 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4338 {
4339 int n = 0;
60fed2d3 4340
252b5132
RH		 4341 while (mote_pseudo_table[n].poc_name)
4342 {
60fed2d3 4343 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4344 hash_insert (op_hash,
4345 mote_pseudo_table[n].poc_name, (char *) hack);
4346 hack->m_operands = 0;
4347 hack->m_opnum = n;
4348 n++;
4349 }
4350 }
4351#endif
4352
4353 init_regtable ();
4354
4355#ifdef OBJ_ELF
4356 record_alignment (text_section, 2);
4357 record_alignment (data_section, 2);
4358 record_alignment (bss_section, 2);
4359#endif
4360}
4361
252b5132
RH		 4362\f
4363/* This is called when a label is defined. */
4364
4365void
31302357 4366m68k_frob_label (symbolS *sym)
252b5132
RH		 4367{
4368 struct label_line *n;
4369
4370 n = (struct label_line *) xmalloc (sizeof *n);
4371 n->next = labels;
4372 n->label = sym;
4373 as_where (&n->file, &n->line);
4374 n->text = 0;
4375 labels = n;
4376 current_label = n;
07a53e5c
RH		 4377
4378#ifdef OBJ_ELF
4379 dwarf2_emit_label (sym);
4380#endif
252b5132
RH		 4381}
4382
4383/* This is called when a value that is not an instruction is emitted. */
4384
4385void
31302357 4386m68k_flush_pending_output (void)
252b5132
RH		 4387{
4388 current_label = NULL;
4389}
4390
4391/* This is called at the end of the assembly, when the final value of
4392 the label is known. We warn if this is a text symbol aligned at an
4393 odd location. */
4394
4395void
31302357 4396m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4397{
4398 if (S_GET_SEGMENT (sym) == reg_section
4399 && (int) S_GET_VALUE (sym) < 0)
4400 {
4401 S_SET_SEGMENT (sym, absolute_section);
4402 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4403 }
4404 else if ((S_GET_VALUE (sym) & 1) != 0)
4405 {
4406 struct label_line *l;
4407
4408 for (l = labels; l != NULL; l = l->next)
4409 {
4410 if (l->label == sym)
4411 {
4412 if (l->text)
4413 as_warn_where (l->file, l->line,
4414 _("text label `%s' aligned to odd boundary"),
4415 S_GET_NAME (sym));
4416 break;
4417 }
4418 }
4419 }
4420}
4421\f
4422/* This is called if we go in or out of MRI mode because of the .mri
4423 pseudo-op. */
4424
4425void
31302357 4426m68k_mri_mode_change (int on)
252b5132
RH		 4427{
4428 if (on)
4429 {
4430 if (! flag_reg_prefix_optional)
4431 {
4432 flag_reg_prefix_optional = 1;
4433#ifdef REGISTER_PREFIX
4434 init_regtable ();
4435#endif
4436 }
4437 m68k_abspcadd = 1;
4438 if (! m68k_rel32_from_cmdline)
4439 m68k_rel32 = 0;
4440 }
4441 else
4442 {
4443 if (! reg_prefix_optional_seen)
4444 {
4445#ifdef REGISTER_PREFIX_OPTIONAL
4446 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4447#else
4448 flag_reg_prefix_optional = 0;
4449#endif
4450#ifdef REGISTER_PREFIX
4451 init_regtable ();
4452#endif
4453 }
4454 m68k_abspcadd = 0;
4455 if (! m68k_rel32_from_cmdline)
4456 m68k_rel32 = 1;
4457 }
4458}
4459
36759679 4460/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4461#define MAX_LITTLENUMS 6
4462
4463/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4464 of type TYPE, and store the appropriate bytes in *LITP. The number
4465 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4466 returned, or NULL on OK. */
4467
4468char *
31302357 4469md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4470{
4471 int prec;
4472 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4473 LITTLENUM_TYPE *wordP;
4474 char *t;
4475
4476 switch (type)
4477 {
4478 case 'f':
4479 case 'F':
4480 case 's':
4481 case 'S':
4482 prec = 2;
4483 break;
4484
4485 case 'd':
4486 case 'D':
4487 case 'r':
4488 case 'R':
4489 prec = 4;
4490 break;
4491
4492 case 'x':
4493 case 'X':
4494 prec = 6;
4495 break;
4496
4497 case 'p':
4498 case 'P':
4499 prec = 6;
4500 break;
4501
4502 default:
4503 *sizeP = 0;
4504 return _("Bad call to MD_ATOF()");
4505 }
4506 t = atof_ieee (input_line_pointer, type, words);
4507 if (t)
4508 input_line_pointer = t;
4509
4510 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4511 for (wordP = words; prec--;)
4512 {
4513 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4514 litP += sizeof (LITTLENUM_TYPE);
4515 }
4516 return 0;
4517}
4518
4519void
31302357 4520md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4521{
4522 number_to_chars_bigendian (buf, val, n);
4523}
4524
94f592af 4525void
55cf6793 4526md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4527{
bbe8ef22 4528 offsetT val = *valP;
252b5132
RH		 4529 addressT upper_limit;
4530 offsetT lower_limit;
4531
4532 /* This is unnecessary but it convinces the native rs6000 compiler
4533 to generate the code we want. */
4534 char *buf = fixP->fx_frag->fr_literal;
4535 buf += fixP->fx_where;
36759679 4536 /* End ibm compiler workaround. */
252b5132 4537
bd17c2c3 4538 val = SEXT (val);
252b5132 4539
94f592af
NC		 4540 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4541 fixP->fx_done = 1;
4542
252b5132
RH		 4543#ifdef OBJ_ELF
4544 if (fixP->fx_addsy)
4545 {
4546 memset (buf, 0, fixP->fx_size);
36759679 4547 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4548
4549 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4550 && !S_IS_DEFINED (fixP->fx_addsy)
4551 && !S_IS_WEAK (fixP->fx_addsy))
4552 S_SET_WEAK (fixP->fx_addsy);
4553 return;
4554 }
4555#endif
4556
252b5132
RH		 4557 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4558 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4559 return;
252b5132
RH		 4560
4561 switch (fixP->fx_size)
4562 {
94f592af
NC		 4563 /* The cast to offsetT below are necessary to make code
4564 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4565 case 1:
4566 *buf++ = val;
4567 upper_limit = 0x7f;
4568 lower_limit = - (offsetT) 0x80;
4569 break;
4570 case 2:
4571 *buf++ = (val >> 8);
4572 *buf++ = val;
4573 upper_limit = 0x7fff;
4574 lower_limit = - (offsetT) 0x8000;
4575 break;
4576 case 4:
4577 *buf++ = (val >> 24);
4578 *buf++ = (val >> 16);
4579 *buf++ = (val >> 8);
4580 *buf++ = val;
4581 upper_limit = 0x7fffffff;
36759679 4582 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4583 break;
4584 default:
4585 BAD_CASE (fixP->fx_size);
4586 }
4587
4588 /* Fix up a negative reloc. */
4589 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4590 {
4591 fixP->fx_addsy = fixP->fx_subsy;
4592 fixP->fx_subsy = NULL;
4593 fixP->fx_tcbit = 1;
4594 }
4595
4596 /* For non-pc-relative values, it's conceivable we might get something
4597 like "0xff" for a byte field. So extend the upper part of the range
4598 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4599 so that we can do any range checking at all. */
4600 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4601 upper_limit = upper_limit * 2 + 1;
4602
4603 if ((addressT) val > upper_limit
4604 && (val > 0 || val < lower_limit))
4605 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4606
4607 /* A one byte PC-relative reloc means a short branch. We can't use
4608 a short branch with a value of 0 or -1, because those indicate
4609 different opcodes (branches with longer offsets). fixup_segment
4610 in write.c may have clobbered fx_pcrel, so we need to examine the
4611 reloc type. */
4612 if ((fixP->fx_pcrel
7be1c489 4613 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4614 && fixP->fx_size == 1
4615 && (fixP->fx_addsy == NULL
4616 || S_IS_DEFINED (fixP->fx_addsy))
4617 && (val == 0 || val == -1))
4618 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4619}
4620
252b5132
RH		 4621/* *fragP has been relaxed to its final size, and now needs to have
4622 the bytes inside it modified to conform to the new size There is UGLY
4623 MAGIC here. ..
4624 */
4625static void
31302357 4626md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4627{
4628 long disp;
252b5132
RH		 4629 fixS *fixP;
4630
4631 /* Address in object code of the displacement. */
4632 register int object_address = fragP->fr_fix + fragP->fr_address;
4633
4634 /* Address in gas core of the place to store the displacement. */
4635 /* This convinces the native rs6000 compiler to generate the code we
92774660 4636 want. */
252b5132
RH		 4637 register char *buffer_address = fragP->fr_literal;
4638 buffer_address += fragP->fr_fix;
36759679 4639 /* End ibm compiler workaround. */
252b5132
RH		 4640
4641 /* The displacement of the address, from current location. */
4642 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4643 disp = (disp + fragP->fr_offset) - object_address;
4644
252b5132
RH		 4645 switch (fragP->fr_subtype)
4646 {
151337e8
NC		 4647 case TAB (BRANCHBWL, BYTE):
4648 case TAB (BRABSJUNC, BYTE):
4649 case TAB (BRABSJCOND, BYTE):
4650 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4651 know (issbyte (disp));
4652 if (disp == 0)
b091f402
AM		 4653 as_bad_where (fragP->fr_file, fragP->fr_line,
4654 _("short branch with zero offset: use :w"));
151337e8 4655 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4656 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4657 fixP->fx_pcrel_adjust = -1;
252b5132 4658 break;
151337e8
NC		 4659 case TAB (BRANCHBWL, SHORT):
4660 case TAB (BRABSJUNC, SHORT):
4661 case TAB (BRABSJCOND, SHORT):
4662 case TAB (BRANCHBW, SHORT):
252b5132 4663 fragP->fr_opcode[1] = 0x00;
151337e8 4664 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4665 1, RELAX_RELOC_PC16);
151337e8
NC		 4666 fragP->fr_fix += 2;
4667 break;
4668 case TAB (BRANCHBWL, LONG):
4669 fragP->fr_opcode[1] = (char) 0xFF;
4670 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4671 1, RELAX_RELOC_PC32);
151337e8 4672 fragP->fr_fix += 4;
252b5132 4673 break;
151337e8
NC		 4674 case TAB (BRABSJUNC, LONG):
4675 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4676 {
36759679 4677 if (flag_keep_pcrel)
6b6e92f4 4678 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4679 fragP->fr_opcode[0] = 0x4E;
36759679 4680 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4681 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4682 0, RELAX_RELOC_ABS32);
151337e8
NC		 4683 fragP->fr_fix += 4;
4684 }
4685 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4686 {
36759679 4687 if (flag_keep_pcrel)
6b6e92f4 4688 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4689 fragP->fr_opcode[0] = 0x4E;
36759679 4690 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4691 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4692 0, RELAX_RELOC_ABS32);
151337e8 4693 fragP->fr_fix += 4;
252b5132
RH		 4694 }
4695 else
4696 {
151337e8
NC		 4697 /* This cannot happen, because jbsr and jbra are the only two
4698 unconditional branches. */
4699 abort ();
252b5132
RH		 4700 }
4701 break;
151337e8 4702 case TAB (BRABSJCOND, LONG):
36759679 4703 if (flag_keep_pcrel)
6b6e92f4 4704 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4705
36759679
NC		 4706 /* Only Bcc 68000 instructions can come here
4707 Change bcc into b!cc/jmp absl long. */
4708 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4709 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4710
4711 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4712 different frag, in which case referring to them is a no-no.
92774660 4713 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4714 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4715 *buffer_address++ = (char) 0xf9;
36759679 4716 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4717 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4718 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4719 fragP->fr_fix += 4;
4720 break;
4721 case TAB (FBRANCH, SHORT):
4722 know ((fragP->fr_opcode[1] & 0x40) == 0);
4723 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4724 1, RELAX_RELOC_PC16);
151337e8
NC		 4725 fragP->fr_fix += 2;
4726 break;
4727 case TAB (FBRANCH, LONG):
36759679 4728 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4729 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4730 1, RELAX_RELOC_PC32);
252b5132 4731 fragP->fr_fix += 4;
252b5132 4732 break;
151337e8
NC		 4733 case TAB (DBCCLBR, SHORT):
4734 case TAB (DBCCABSJ, SHORT):
4735 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4736 1, RELAX_RELOC_PC16);
151337e8
NC		 4737 fragP->fr_fix += 2;
4738 break;
4739 case TAB (DBCCLBR, LONG):
36759679
NC		 4740 /* Only DBcc instructions can come here.
4741 Change dbcc into dbcc/bral.
4742 JF: these used to be fr_opcode[2-7], but that's wrong. */
4743 if (flag_keep_pcrel)
6b6e92f4 4744 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4745
36759679 4746 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4747 *buffer_address++ = 0x04;
36759679 4748 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4749 *buffer_address++ = 0x06;
151337e8
NC		 4750 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4751 *buffer_address++ = (char) 0xff;
252b5132 4752
36759679 4753 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4754 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4755 RELAX_RELOC_PC32);
252b5132 4756 fragP->fr_fix += 4;
252b5132 4757 break;
151337e8 4758 case TAB (DBCCABSJ, LONG):
36759679
NC		 4759 /* Only DBcc instructions can come here.
4760 Change dbcc into dbcc/jmp.
4761 JF: these used to be fr_opcode[2-7], but that's wrong. */
4762 if (flag_keep_pcrel)
6b6e92f4 4763 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4764
36759679 4765 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4766 *buffer_address++ = 0x04;
36759679 4767 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4768 *buffer_address++ = 0x06;
36759679 4769 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4770 *buffer_address++ = (char) 0xf9;
4771
36759679 4772 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4773 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4774 RELAX_RELOC_ABS32);
252b5132 4775 fragP->fr_fix += 4;
252b5132 4776 break;
151337e8 4777 case TAB (PCREL1632, SHORT):
252b5132
RH		 4778 fragP->fr_opcode[1] &= ~0x3F;
4779 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4780 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4781 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4782 fragP->fr_fix += 2;
252b5132 4783 break;
151337e8 4784 case TAB (PCREL1632, LONG):
252b5132
RH		 4785 /* Already set to mode 7.3; this indicates: PC indirect with
4786 suppressed index, 32-bit displacement. */
4787 *buffer_address++ = 0x01;
4788 *buffer_address++ = 0x70;
4789 fragP->fr_fix += 2;
151337e8 4790 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4791 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4792 fixP->fx_pcrel_adjust = 2;
4793 fragP->fr_fix += 4;
252b5132 4794 break;
252b5132 4795 case TAB (PCINDEX, BYTE):
252b5132
RH		 4796 assert (fragP->fr_fix >= 2);
4797 buffer_address[-2] &= ~1;
151337e8 4798 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4799 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4800 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4801 break;
4802 case TAB (PCINDEX, SHORT):
252b5132
RH		 4803 assert (fragP->fr_fix >= 2);
4804 buffer_address[-2] |= 0x1;
4805 buffer_address[-1] = 0x20;
4806 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4807 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4808 fixP->fx_pcrel_adjust = 2;
151337e8 4809 fragP->fr_fix += 2;
252b5132
RH		 4810 break;
4811 case TAB (PCINDEX, LONG):
252b5132
RH		 4812 assert (fragP->fr_fix >= 2);
4813 buffer_address[-2] |= 0x1;
4814 buffer_address[-1] = 0x30;
151337e8 4815 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4816 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4817 fixP->fx_pcrel_adjust = 2;
4818 fragP->fr_fix += 4;
4819 break;
4820 case TAB (ABSTOPCREL, SHORT):
4821 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4822 1, RELAX_RELOC_PC16);
151337e8
NC		 4823 fragP->fr_fix += 2;
4824 break;
4825 case TAB (ABSTOPCREL, LONG):
36759679 4826 if (flag_keep_pcrel)
6b6e92f4 4827 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4828 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4829 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4830 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4831 abort ();
4832 fragP->fr_opcode[1] &= ~0x3F;
4833 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4834 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4835 0, RELAX_RELOC_ABS32);
151337e8 4836 fragP->fr_fix += 4;
252b5132 4837 break;
252b5132
RH		 4838 }
4839}
4840
252b5132 4841void
31302357
AS		 4842md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4843 segT sec ATTRIBUTE_UNUSED,
4844 fragS *fragP)
252b5132
RH		 4845{
4846 md_convert_frag_1 (fragP);
4847}
252b5132
RH		 4848
4849/* Force truly undefined symbols to their maximum size, and generally set up
4850 the frag list to be relaxed
4851 */
4852int
31302357 4853md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4854{
151337e8 4855 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4856 switch (fragP->fr_subtype)
4857 {
151337e8
NC		 4858 case TAB (BRANCHBWL, SZ_UNDEF):
4859 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4860 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4861 {
151337e8
NC		 4862 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4863 && relaxable_symbol (fragP->fr_symbol))
252b5132 4864 {
151337e8
NC		 4865 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4866 }
4867 else if (flag_short_refs)
4868 {
4869 /* Symbol is undefined and we want short ref. */
4870 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4871 }
4872 else
4873 {
151337e8
NC		 4874 /* Symbol is still undefined. Make it LONG. */
4875 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4876 }
4877 break;
151337e8 4878 }
252b5132 4879
151337e8 4880 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4881 {
151337e8
NC		 4882 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4883 && relaxable_symbol (fragP->fr_symbol))
252b5132 4884 {
151337e8 4885 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4886 }
4887 else
4888 {
151337e8
NC		 4889 /* Symbol is undefined and we don't have long branches. */
4890 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4891 }
4892 break;
151337e8 4893 }
252b5132 4894
151337e8 4895 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4896 case TAB (DBCCLBR, SZ_UNDEF):
4897 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4898 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4899 {
8ec6253e
NC		 4900 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4901 && relaxable_symbol (fragP->fr_symbol))
151337e8 4902 || flag_short_refs)
252b5132 4903 {
151337e8 4904 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4905 }
4906 else
4907 {
151337e8 4908 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4909 }
4910 break;
151337e8 4911 }
81d4177b 4912
252b5132
RH		 4913 case TAB (PCINDEX, SZ_UNDEF):
4914 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4915 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4916 {
4917 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4918 }
4919 else
4920 {
4921 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4922 }
4923 break;
4924
151337e8
NC		 4925 case TAB (ABSTOPCREL, SZ_UNDEF):
4926 {
4927 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4928 && relaxable_symbol (fragP->fr_symbol)))
4929 {
4930 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4931 }
4932 else
4933 {
4934 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4935 }
4936 break;
4937 }
4938
252b5132
RH		 4939 default:
4940 break;
4941 }
4942
151337e8 4943 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4944 switch (fragP->fr_subtype)
4945 {
151337e8
NC		 4946 case TAB (BRANCHBWL, BYTE):
4947 case TAB (BRABSJUNC, BYTE):
4948 case TAB (BRABSJCOND, BYTE):
4949 case TAB (BRANCHBW, BYTE):
252b5132 4950 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4951 case we force word mode. If the symbol is at the start of a
4952 frag, and it is the next frag with any data in it (usually
4953 this is just the next frag, but assembler listings may
4954 introduce empty frags), we must use word mode. */
4955 if (fragP->fr_symbol)
252b5132 4956 {
ac62c346 4957 fragS *sym_frag;
252b5132 4958
ac62c346
AM		 4959 sym_frag = symbol_get_frag (fragP->fr_symbol);
4960 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4961 {
ac62c346
AM		 4962 fragS *l;
4963
23b7f870 4964 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4965 if (l->fr_fix != 0)
4966 break;
4967 if (l == sym_frag)
4968 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4969 }
4970 }
4971 break;
4972 default:
4973 break;
4974 }
ac62c346 4975 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4976}
4977
4978#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4979/* the bit-field entries in the relocation_info struct plays hell
4980 with the byte-order problems of cross-assembly. So as a hack,
4981 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 4982 you there. -KWK */
252b5132
RH		 4983/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4984 are symbolnum, most sig. byte first. Last byte is broken up with
4985 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4986 nibble as nuthin. (on Sun 3 at least) */
4987/* Translate the internal relocation information into target-specific
92774660 4988 format. */
252b5132
RH		 4989#ifdef comment
4990void
31302357 4991md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 4992{
36759679 4993 /* This is easy. */
252b5132 4994 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 4995 /* Now the fun stuff. */
252b5132 4996 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 4997 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4998 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 4999 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5000 | ((ri->r_length << 5) & 0x60)
5001 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5002}
5003
36759679 5004#endif
252b5132 5005
252b5132
RH		 5006#endif /* OBJ_AOUT or OBJ_BOUT */
5007
5008#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5009int md_short_jump_size = 4;
5010int md_long_jump_size = 6;
252b5132
RH		 5011
5012void
31302357
AS		 5013md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5014 fragS *frag ATTRIBUTE_UNUSED,
5015 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5016{
5017 valueT offset;
5018
5019 offset = to_addr - (from_addr + 2);
5020
5021 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5022 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5023}
5024
5025void
31302357
AS		 5026md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5027 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5028{
5029 valueT offset;
5030
6b6e92f4 5031 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5032 {
36759679 5033 if (flag_keep_pcrel)
6b6e92f4 5034 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5035 offset = to_addr - S_GET_VALUE (to_symbol);
5036 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5037 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5038 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5039 0, NO_RELOC);
5040 }
5041 else
5042 {
5043 offset = to_addr - (from_addr + 2);
5044 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5045 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5046 }
5047}
5048
5049#endif
5050
5051/* Different values of OK tell what its OK to return. Things that
5052 aren't OK are an error (what a shock, no?)
5053
5054 0: Everything is OK
3e602632
NC		 5055 10: Absolute 1:8 only
5056 20: Absolute 0:7 only
5057 30: absolute 0:15 only
5058 40: Absolute 0:31 only
5059 50: absolute 0:127 only
252b5132 5060 55: absolute -64:63 only
3e602632
NC		 5061 60: absolute -128:127 only
5062 70: absolute 0:4095 only
5063 80: absolute -1, 1:7 only
5064 90: No bignums. */
252b5132
RH		 5065
5066static int
31302357 5067get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5068{
5069 if (exp->exp.X_op == O_absent)
5070 {
36759679 5071 /* Do the same thing the VAX asm does. */
252b5132
RH		 5072 op (exp) = O_constant;
5073 adds (exp) = 0;
5074 subs (exp) = 0;
5075 offs (exp) = 0;
5076 if (ok == 10)
5077 {
5078 as_warn (_("expression out of range: defaulting to 1"));
5079 offs (exp) = 1;
5080 }
5081 }
5082 else if (exp->exp.X_op == O_constant)
5083 {
5084 switch (ok)
5085 {
5086 case 10:
bd17c2c3 5087 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5088 {
5089 as_warn (_("expression out of range: defaulting to 1"));
5090 offs (exp) = 1;
5091 }
5092 break;
5093 case 20:
bd17c2c3 5094 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5095 goto outrange;
5096 break;
5097 case 30:
bd17c2c3 5098 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5099 goto outrange;
5100 break;
5101 case 40:
bd17c2c3 5102 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5103 goto outrange;
5104 break;
5105 case 50:
bd17c2c3 5106 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5107 goto outrange;
5108 break;
5109 case 55:
bd17c2c3 5110 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5111 goto outrange;
5112 break;
5113 case 60:
bd17c2c3 5114 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5115 goto outrange;
5116 break;
5117 case 70:
bd17c2c3 5118 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5119 {
5120 outrange:
5121 as_warn (_("expression out of range: defaulting to 0"));
5122 offs (exp) = 0;
5123 }
5124 break;
3e602632 5125 case 80:
bd17c2c3
AM		 5126 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5127 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5128 {
5129 as_warn (_("expression out of range: defaulting to 1"));
5130 offs (exp) = 1;
5131 }
5132 break;
252b5132
RH		 5133 default:
5134 break;
5135 }
5136 }
5137 else if (exp->exp.X_op == O_big)
5138 {
36759679 5139 if (offs (exp) <= 0 /* flonum. */
3e602632 5140 && (ok == 90 /* no bignums */
36759679 5141 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5142 /* If we have a flonum zero, a zero integer should
5143 do as well (e.g., in moveq). */
5144 && generic_floating_point_number.exponent == 0
5145 && generic_floating_point_number.low[0] == 0)))
5146 {
36759679 5147 /* HACK! Turn it into a long. */
252b5132
RH		 5148 LITTLENUM_TYPE words[6];
5149
36759679 5150 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5151 op (exp) = O_constant;
5152 adds (exp) = 0;
5153 subs (exp) = 0;
5154 offs (exp) = words[1] | (words[0] << 16);
5155 }
5156 else if (ok != 0)
5157 {
5158 op (exp) = O_constant;
5159 adds (exp) = 0;
5160 subs (exp) = 0;
5161 offs (exp) = (ok == 10) ? 1 : 0;
5162 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5163 (long) offs (exp));
252b5132
RH		 5164 }
5165 }
5166 else
5167 {
3e602632 5168 if (ok >= 10 && ok <= 80)
252b5132
RH		 5169 {
5170 op (exp) = O_constant;
5171 adds (exp) = 0;
5172 subs (exp) = 0;
5173 offs (exp) = (ok == 10) ? 1 : 0;
5174 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5175 (long) offs (exp));
252b5132
RH		 5176 }
5177 }
5178
5179 if (exp->size != SIZE_UNSPEC)
5180 {
5181 switch (exp->size)
5182 {
5183 case SIZE_UNSPEC:
5184 case SIZE_LONG:
5185 break;
5186 case SIZE_BYTE:
5187 if (!isbyte (offs (exp)))
5188 as_warn (_("expression doesn't fit in BYTE"));
5189 break;
5190 case SIZE_WORD:
5191 if (!isword (offs (exp)))
5192 as_warn (_("expression doesn't fit in WORD"));
5193 break;
5194 }
5195 }
5196
5197 return offs (exp);
5198}
5199
5200/* These are the back-ends for the various machine dependent pseudo-ops. */
5201
5202static void
31302357 5203s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5204{
5205 subseg_set (data_section, 1);
5206 demand_empty_rest_of_line ();
5207}
5208
5209static void
31302357 5210s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5211{
5212 subseg_set (data_section, 2);
5213 demand_empty_rest_of_line ();
5214}
5215
5216static void
31302357 5217s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5218{
5219 /* We don't support putting frags in the BSS segment, we fake it
5220 by marking in_bss, then looking at s_skip for clues. */
5221
5222 subseg_set (bss_section, 0);
5223 demand_empty_rest_of_line ();
5224}
5225
5226static void
31302357 5227s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5228{
5229 register int temp;
5230 register long temp_fill;
5231
5232 temp = 1; /* JF should be 2? */
5233 temp_fill = get_absolute_expression ();
92774660 5234 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5235 frag_align (temp, (int) temp_fill, 0);
5236 demand_empty_rest_of_line ();
5237 record_alignment (now_seg, temp);
5238}
5239
5240static void
31302357 5241s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5242{
5243 demand_empty_rest_of_line ();
5244}
5245\f
5246/* Pseudo-ops handled for MRI compatibility. */
5247
5248/* This function returns non-zero if the argument is a conditional
5249 pseudo-op. This is called when checking whether a pending
5250 alignment is needed. */
5251
5252int
31302357 5253m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5254{
5255 return (pop->poc_handler == s_mri_if
5256 || pop->poc_handler == s_mri_else);
5257}
5258
5259/* Handle an MRI style chip specification. */
5260
5261static void
31302357 5262mri_chip (void)
252b5132
RH		 5263{
5264 char *s;
5265 char c;
5266 int i;
5267
5268 s = input_line_pointer;
5269 /* We can't use get_symbol_end since the processor names are not proper
5270 symbols. */
5271 while (is_part_of_name (c = *input_line_pointer++))
5272 ;
5273 *--input_line_pointer = 0;
266abb8f
NS		 5274 for (i = 0; m68k_cpus[i].name; i++)
5275 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5276 break;
266abb8f 5277 if (!m68k_cpus[i].name)
252b5132
RH		 5278 {
5279 as_bad (_("%s: unrecognized processor name"), s);
5280 *input_line_pointer = c;
5281 ignore_rest_of_line ();
5282 return;
5283 }
5284 *input_line_pointer = c;
5285
5286 if (*input_line_pointer == '/')
5287 current_architecture = 0;
5288 else
5289 current_architecture &= m68881 | m68851;
266abb8f 5290 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5291 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5292
5293 while (*input_line_pointer == '/')
5294 {
5295 ++input_line_pointer;
5296 s = input_line_pointer;
5297 /* We can't use get_symbol_end since the processor names are not
5298 proper symbols. */
5299 while (is_part_of_name (c = *input_line_pointer++))
5300 ;
5301 *--input_line_pointer = 0;
5302 if (strcmp (s, "68881") == 0)
5303 current_architecture |= m68881;
5304 else if (strcmp (s, "68851") == 0)
5305 current_architecture |= m68851;
5306 *input_line_pointer = c;
5307 }
252b5132
RH		 5308}
5309
5310/* The MRI CHIP pseudo-op. */
5311
5312static void
31302357 5313s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5314{
5315 char *stop = NULL;
5316 char stopc;
5317
5318 if (flag_mri)
5319 stop = mri_comment_field (&stopc);
5320 mri_chip ();
5321 if (flag_mri)
5322 mri_comment_end (stop, stopc);
5323 demand_empty_rest_of_line ();
5324}
5325
5326/* The MRI FOPT pseudo-op. */
5327
5328static void
31302357 5329s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5330{
5331 SKIP_WHITESPACE ();
5332
5333 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5334 {
5335 int temp;
5336
5337 input_line_pointer += 3;
5338 temp = get_absolute_expression ();
5339 if (temp < 0 || temp > 7)
5340 as_bad (_("bad coprocessor id"));
5341 else
5342 m68k_float_copnum = COP0 + temp;
5343 }
5344 else
5345 {
5346 as_bad (_("unrecognized fopt option"));
5347 ignore_rest_of_line ();
5348 return;
5349 }
5350
5351 demand_empty_rest_of_line ();
5352}
5353
5354/* The structure used to handle the MRI OPT pseudo-op. */
5355
5356struct opt_action
5357{
5358 /* The name of the option. */
5359 const char *name;
5360
5361 /* If this is not NULL, just call this function. The first argument
5362 is the ARG field of this structure, the second argument is
5363 whether the option was negated. */
31302357 5364 void (*pfn) (int arg, int on);
252b5132
RH		 5365
5366 /* If this is not NULL, and the PFN field is NULL, set the variable
5367 this points to. Set it to the ARG field if the option was not
5368 negated, and the NOTARG field otherwise. */
5369 int *pvar;
5370
5371 /* The value to pass to PFN or to assign to *PVAR. */
5372 int arg;
5373
5374 /* The value to assign to *PVAR if the option is negated. If PFN is
5375 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5376 the option may not be negated. */
5377 int notarg;
5378};
5379
5380/* The table used to handle the MRI OPT pseudo-op. */
5381
31302357
AS		 5382static void skip_to_comma (int, int);
5383static void opt_nest (int, int);
5384static void opt_chip (int, int);
5385static void opt_list (int, int);
5386static void opt_list_symbols (int, int);
252b5132
RH		 5387
5388static const struct opt_action opt_table[] =
5389{
5390 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5391
5392 /* We do relaxing, so there is little use for these options. */
5393 { "b", 0, 0, 0, 0 },
5394 { "brs", 0, 0, 0, 0 },
5395 { "brb", 0, 0, 0, 0 },
5396 { "brl", 0, 0, 0, 0 },
5397 { "brw", 0, 0, 0, 0 },
5398
5399 { "c", 0, 0, 0, 0 },
5400 { "cex", 0, 0, 0, 0 },
5401 { "case", 0, &symbols_case_sensitive, 1, 0 },
5402 { "cl", 0, 0, 0, 0 },
5403 { "cre", 0, 0, 0, 0 },
5404 { "d", 0, &flag_keep_locals, 1, 0 },
5405 { "e", 0, 0, 0, 0 },
5406 { "f", 0, &flag_short_refs, 1, 0 },
5407 { "frs", 0, &flag_short_refs, 1, 0 },
5408 { "frl", 0, &flag_short_refs, 0, 1 },
5409 { "g", 0, 0, 0, 0 },
5410 { "i", 0, 0, 0, 0 },
5411 { "m", 0, 0, 0, 0 },
5412 { "mex", 0, 0, 0, 0 },
5413 { "mc", 0, 0, 0, 0 },
5414 { "md", 0, 0, 0, 0 },
5415 { "nest", opt_nest, 0, 0, 0 },
5416 { "next", skip_to_comma, 0, 0, 0 },
5417 { "o", 0, 0, 0, 0 },
5418 { "old", 0, 0, 0, 0 },
5419 { "op", skip_to_comma, 0, 0, 0 },
5420 { "pco", 0, 0, 0, 0 },
5421 { "p", opt_chip, 0, 0, 0 },
5422 { "pcr", 0, 0, 0, 0 },
5423 { "pcs", 0, 0, 0, 0 },
5424 { "r", 0, 0, 0, 0 },
5425 { "quick", 0, &m68k_quick, 1, 0 },
5426 { "rel32", 0, &m68k_rel32, 1, 0 },
5427 { "s", opt_list, 0, 0, 0 },
5428 { "t", opt_list_symbols, 0, 0, 0 },
5429 { "w", 0, &flag_no_warnings, 0, 1 },
5430 { "x", 0, 0, 0, 0 }
5431};
5432
8fce3f5e 5433#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5434
5435/* The MRI OPT pseudo-op. */
5436
5437static void
31302357 5438s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5439{
5440 do
5441 {
5442 int t;
5443 char *s;
5444 char c;
5445 int i;
5446 const struct opt_action *o;
5447
5448 SKIP_WHITESPACE ();
5449
5450 t = 1;
5451 if (*input_line_pointer == '-')
5452 {
5453 ++input_line_pointer;
5454 t = 0;
5455 }
5456 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5457 {
5458 input_line_pointer += 2;
5459 t = 0;
5460 }
5461
5462 s = input_line_pointer;
5463 c = get_symbol_end ();
5464
5465 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5466 {
5467 if (strcasecmp (s, o->name) == 0)
5468 {
5469 if (o->pfn)
5470 {
5471 /* Restore input_line_pointer now in case the option
5472 takes arguments. */
5473 *input_line_pointer = c;
5474 (*o->pfn) (o->arg, t);
5475 }
5476 else if (o->pvar != NULL)
5477 {
5478 if (! t && o->arg == o->notarg)
5479 as_bad (_("option `%s' may not be negated"), s);
5480 *input_line_pointer = c;
5481 *o->pvar = t ? o->arg : o->notarg;
5482 }
5483 else
5484 *input_line_pointer = c;
5485 break;
5486 }
5487 }
5488 if (i >= OPTCOUNT)
5489 {
5490 as_bad (_("option `%s' not recognized"), s);
5491 *input_line_pointer = c;
5492 }
5493 }
5494 while (*input_line_pointer++ == ',');
5495
5496 /* Move back to terminating character. */
5497 --input_line_pointer;
5498 demand_empty_rest_of_line ();
5499}
5500
5501/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5502 not support and which take arguments. */
252b5132
RH		 5503
5504static void
31302357 5505skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5506{
5507 while (*input_line_pointer != ','
5508 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5509 ++input_line_pointer;
5510}
5511
5512/* Handle the OPT NEST=depth option. */
5513
5514static void
31302357 5515opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5516{
5517 if (*input_line_pointer != '=')
5518 {
5519 as_bad (_("bad format of OPT NEST=depth"));
5520 return;
5521 }
5522
5523 ++input_line_pointer;
5524 max_macro_nest = get_absolute_expression ();
5525}
5526
5527/* Handle the OPT P=chip option. */
5528
5529static void
31302357 5530opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5531{
5532 if (*input_line_pointer != '=')
5533 {
5534 /* This is just OPT P, which we do not support. */
5535 return;
5536 }
5537
5538 ++input_line_pointer;
5539 mri_chip ();
5540}
5541
5542/* Handle the OPT S option. */
5543
5544static void
31302357 5545opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5546{
5547 listing_list (on);
5548}
5549
5550/* Handle the OPT T option. */
5551
5552static void
31302357 5553opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5554{
5555 if (on)
5556 listing |= LISTING_SYMBOLS;
5557 else
8a104df9 5558 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5559}
5560
5561/* Handle the MRI REG pseudo-op. */
5562
5563static void
31302357 5564s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5565{
5566 char *s;
5567 int c;
5568 struct m68k_op rop;
5569 int mask;
5570 char *stop = NULL;
5571 char stopc;
5572
5573 if (line_label == NULL)
5574 {
5575 as_bad (_("missing label"));
5576 ignore_rest_of_line ();
5577 return;
5578 }
5579
5580 if (flag_mri)
5581 stop = mri_comment_field (&stopc);
5582
5583 SKIP_WHITESPACE ();
5584
5585 s = input_line_pointer;
3882b010 5586 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5587#ifdef REGISTER_PREFIX
5588 || *input_line_pointer == REGISTER_PREFIX
5589#endif
5590 || *input_line_pointer == '/'
5591 || *input_line_pointer == '-')
5592 ++input_line_pointer;
5593 c = *input_line_pointer;
5594 *input_line_pointer = '\0';
5595
5596 if (m68k_ip_op (s, &rop) != 0)
5597 {
5598 if (rop.error == NULL)
5599 as_bad (_("bad register list"));
5600 else
5601 as_bad (_("bad register list: %s"), rop.error);
5602 *input_line_pointer = c;
5603 ignore_rest_of_line ();
5604 return;
5605 }
5606
5607 *input_line_pointer = c;
5608
5609 if (rop.mode == REGLST)
5610 mask = rop.mask;
5611 else if (rop.mode == DREG)
5612 mask = 1 << (rop.reg - DATA0);
5613 else if (rop.mode == AREG)
5614 mask = 1 << (rop.reg - ADDR0 + 8);
5615 else if (rop.mode == FPREG)
5616 mask = 1 << (rop.reg - FP0 + 16);
5617 else if (rop.mode == CONTROL
5618 && rop.reg == FPI)
5619 mask = 1 << 24;
5620 else if (rop.mode == CONTROL
5621 && rop.reg == FPS)
5622 mask = 1 << 25;
5623 else if (rop.mode == CONTROL
5624 && rop.reg == FPC)
5625 mask = 1 << 26;
5626 else
5627 {
5628 as_bad (_("bad register list"));
5629 ignore_rest_of_line ();
5630 return;
5631 }
5632
5633 S_SET_SEGMENT (line_label, reg_section);
5634 S_SET_VALUE (line_label, ~mask);
49309057 5635 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5636
5637 if (flag_mri)
5638 mri_comment_end (stop, stopc);
5639
5640 demand_empty_rest_of_line ();
5641}
5642
5643/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5644
5645struct save_opts
5646{
5647 struct save_opts *next;
5648 int abspcadd;
5649 int symbols_case_sensitive;
5650 int keep_locals;
5651 int short_refs;
5652 int architecture;
2da12c60 5653 const enum m68k_register *control_regs;
252b5132
RH		 5654 int quick;
5655 int rel32;
5656 int listing;
5657 int no_warnings;
5658 /* FIXME: We don't save OPT S. */
5659};
5660
5661/* This variable holds the stack of saved options. */
5662
5663static struct save_opts *save_stack;
5664
5665/* The MRI SAVE pseudo-op. */
5666
5667static void
31302357 5668s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5669{
5670 struct save_opts *s;
5671
5672 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5673 s->abspcadd = m68k_abspcadd;
5674 s->symbols_case_sensitive = symbols_case_sensitive;
5675 s->keep_locals = flag_keep_locals;
5676 s->short_refs = flag_short_refs;
5677 s->architecture = current_architecture;
2da12c60 5678 s->control_regs = control_regs;
252b5132
RH		 5679 s->quick = m68k_quick;
5680 s->rel32 = m68k_rel32;
5681 s->listing = listing;
5682 s->no_warnings = flag_no_warnings;
5683
5684 s->next = save_stack;
5685 save_stack = s;
5686
5687 demand_empty_rest_of_line ();
5688}
5689
5690/* The MRI RESTORE pseudo-op. */
5691
5692static void
31302357 5693s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5694{
5695 struct save_opts *s;
5696
5697 if (save_stack == NULL)
5698 {
5699 as_bad (_("restore without save"));
5700 ignore_rest_of_line ();
5701 return;
5702 }
5703
5704 s = save_stack;
5705 save_stack = s->next;
5706
5707 m68k_abspcadd = s->abspcadd;
5708 symbols_case_sensitive = s->symbols_case_sensitive;
5709 flag_keep_locals = s->keep_locals;
5710 flag_short_refs = s->short_refs;
5711 current_architecture = s->architecture;
2da12c60 5712 control_regs = s->control_regs;
252b5132
RH		 5713 m68k_quick = s->quick;
5714 m68k_rel32 = s->rel32;
5715 listing = s->listing;
5716 flag_no_warnings = s->no_warnings;
5717
5718 free (s);
5719
5720 demand_empty_rest_of_line ();
5721}
5722
5723/* Types of MRI structured control directives. */
5724
5725enum mri_control_type
5726{
5727 mri_for,
5728 mri_if,
5729 mri_repeat,
5730 mri_while
5731};
5732
5733/* This structure is used to stack the MRI structured control
5734 directives. */
5735
5736struct mri_control_info
5737{
5738 /* The directive within which this one is enclosed. */
5739 struct mri_control_info *outer;
5740
5741 /* The type of directive. */
5742 enum mri_control_type type;
5743
5744 /* Whether an ELSE has been in an IF. */
5745 int else_seen;
5746
5747 /* The add or sub statement at the end of a FOR. */
5748 char *incr;
5749
5750 /* The label of the top of a FOR or REPEAT loop. */
5751 char *top;
5752
5753 /* The label to jump to for the next iteration, or the else
5754 expression of a conditional. */
5755 char *next;
5756
5757 /* The label to jump to to break out of the loop, or the label past
5758 the end of a conditional. */
5759 char *bottom;
5760};
5761
5762/* The stack of MRI structured control directives. */
5763
5764static struct mri_control_info *mri_control_stack;
5765
5766/* The current MRI structured control directive index number, used to
5767 generate label names. */
5768
5769static int mri_control_index;
5770
252b5132
RH		 5771/* Assemble an instruction for an MRI structured control directive. */
5772
5773static void
31302357 5774mri_assemble (char *str)
252b5132
RH		 5775{
5776 char *s;
5777
5778 /* md_assemble expects the opcode to be in lower case. */
5779 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5780 *s = TOLOWER (*s);
252b5132
RH		 5781
5782 md_assemble (str);
5783}
5784
5785/* Generate a new MRI label structured control directive label name. */
5786
5787static char *
31302357 5788mri_control_label (void)
252b5132
RH		 5789{
5790 char *n;
5791
5792 n = (char *) xmalloc (20);
5793 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5794 ++mri_control_index;
5795 return n;
5796}
5797
5798/* Create a new MRI structured control directive. */
5799
5800static struct mri_control_info *
31302357 5801push_mri_control (enum mri_control_type type)
252b5132
RH		 5802{
5803 struct mri_control_info *n;
5804
5805 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5806
5807 n->type = type;
5808 n->else_seen = 0;
5809 if (type == mri_if || type == mri_while)
5810 n->top = NULL;
5811 else
5812 n->top = mri_control_label ();
5813 n->next = mri_control_label ();
5814 n->bottom = mri_control_label ();
5815
5816 n->outer = mri_control_stack;
5817 mri_control_stack = n;
5818
5819 return n;
5820}
5821
5822/* Pop off the stack of MRI structured control directives. */
5823
5824static void
31302357 5825pop_mri_control (void)
252b5132
RH		 5826{
5827 struct mri_control_info *n;
5828
5829 n = mri_control_stack;
5830 mri_control_stack = n->outer;
5831 if (n->top != NULL)
5832 free (n->top);
5833 free (n->next);
5834 free (n->bottom);
5835 free (n);
5836}
5837
5838/* Recognize a condition code in an MRI structured control expression. */
5839
5840static int
31302357 5841parse_mri_condition (int *pcc)
252b5132
RH		 5842{
5843 char c1, c2;
5844
5845 know (*input_line_pointer == '<');
5846
5847 ++input_line_pointer;
5848 c1 = *input_line_pointer++;
5849 c2 = *input_line_pointer++;
5850
5851 if (*input_line_pointer != '>')
5852 {
5853 as_bad (_("syntax error in structured control directive"));
5854 return 0;
5855 }
5856
5857 ++input_line_pointer;
5858 SKIP_WHITESPACE ();
5859
3882b010
L		 5860 c1 = TOLOWER (c1);
5861 c2 = TOLOWER (c2);
252b5132
RH		 5862
5863 *pcc = (c1 << 8) | c2;
5864
5865 return 1;
5866}
5867
5868/* Parse a single operand in an MRI structured control expression. */
5869
5870static int
31302357
AS		 5871parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5872 char **rightstart, char **rightstop)
252b5132
RH		 5873{
5874 char *s;
5875
5876 SKIP_WHITESPACE ();
5877
5878 *pcc = -1;
5879 *leftstart = NULL;
5880 *leftstop = NULL;
5881 *rightstart = NULL;
5882 *rightstop = NULL;
5883
5884 if (*input_line_pointer == '<')
5885 {
5886 /* It's just a condition code. */
5887 return parse_mri_condition (pcc);
5888 }
5889
5890 /* Look ahead for the condition code. */
5891 for (s = input_line_pointer; *s != '\0'; ++s)
5892 {
5893 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5894 break;
5895 }
5896 if (*s == '\0')
5897 {
5898 as_bad (_("missing condition code in structured control directive"));
5899 return 0;
5900 }
5901
5902 *leftstart = input_line_pointer;
5903 *leftstop = s;
5904 if (*leftstop > *leftstart
5905 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5906 --*leftstop;
5907
5908 input_line_pointer = s;
5909 if (! parse_mri_condition (pcc))
5910 return 0;
5911
5912 /* Look ahead for AND or OR or end of line. */
5913 for (s = input_line_pointer; *s != '\0'; ++s)
5914 {
e1f44d10
NC		 5915 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5916 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5917 ^^^ ^^ */
8a104df9
KH		 5918 if ((s == input_line_pointer
5919 || *(s-1) == ' '
5920 || *(s-1) == '\t')
5921 && ((strncasecmp (s, "AND", 3) == 0
5922 && (s[3] == '.' || ! is_part_of_name (s[3])))
5923 || (strncasecmp (s, "OR", 2) == 0
5924 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5925 break;
252b5132
RH		 5926 }
5927
5928 *rightstart = input_line_pointer;
5929 *rightstop = s;
5930 if (*rightstop > *rightstart
5931 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5932 --*rightstop;
5933
5934 input_line_pointer = s;
5935
5936 return 1;
5937}
5938
5939#define MCC(b1, b2) (((b1) << 8) | (b2))
5940
5941/* Swap the sense of a condition. This changes the condition so that
5942 it generates the same result when the operands are swapped. */
5943
5944static int
31302357 5945swap_mri_condition (int cc)
252b5132
RH		 5946{
5947 switch (cc)
5948 {
5949 case MCC ('h', 'i'): return MCC ('c', 's');
5950 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 5951 /* <HS> is an alias for <CC>. */
e1f44d10 5952 case MCC ('h', 's'):
252b5132 5953 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 5954 /* <LO> is an alias for <CS>. */
e1f44d10 5955 case MCC ('l', 'o'):
252b5132
RH		 5956 case MCC ('c', 's'): return MCC ('h', 'i');
5957 case MCC ('p', 'l'): return MCC ('m', 'i');
5958 case MCC ('m', 'i'): return MCC ('p', 'l');
5959 case MCC ('g', 'e'): return MCC ('l', 'e');
5960 case MCC ('l', 't'): return MCC ('g', 't');
5961 case MCC ('g', 't'): return MCC ('l', 't');
5962 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 5963 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 5964 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5965 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5966 case MCC ('v', 'c'):
5967 case MCC ('v', 's'):
5968 default :
5969 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5970 (char) (cc >> 8), (char) (cc));
5971 break;
252b5132
RH		 5972 }
5973 return cc;
5974}
5975
5976/* Reverse the sense of a condition. */
5977
5978static int
31302357 5979reverse_mri_condition (int cc)
252b5132
RH		 5980{
5981 switch (cc)
5982 {
5983 case MCC ('h', 'i'): return MCC ('l', 's');
5984 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5985 /* <HS> is an alias for <CC> */
5986 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5987 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5988 /* <LO> is an alias for <CS> */
5989 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5990 case MCC ('c', 's'): return MCC ('c', 'c');
5991 case MCC ('n', 'e'): return MCC ('e', 'q');
5992 case MCC ('e', 'q'): return MCC ('n', 'e');
5993 case MCC ('v', 'c'): return MCC ('v', 's');
5994 case MCC ('v', 's'): return MCC ('v', 'c');
5995 case MCC ('p', 'l'): return MCC ('m', 'i');
5996 case MCC ('m', 'i'): return MCC ('p', 'l');
5997 case MCC ('g', 'e'): return MCC ('l', 't');
5998 case MCC ('l', 't'): return MCC ('g', 'e');
5999 case MCC ('g', 't'): return MCC ('l', 'e');
6000 case MCC ('l', 'e'): return MCC ('g', 't');
6001 }
6002 return cc;
6003}
6004
6005/* Build an MRI structured control expression. This generates test
6006 and branch instructions. It goes to TRUELAB if the condition is
6007 true, and to FALSELAB if the condition is false. Exactly one of
6008 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6009 is the size qualifier for the expression. EXTENT is the size to
6010 use for the branch. */
6011
6012static void
31302357
AS		 6013build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6014 char *rightstart, char *rightstop,
6015 const char *truelab, const char *falselab,
6016 int extent)
252b5132
RH		 6017{
6018 char *buf;
6019 char *s;
6020
6021 if (leftstart != NULL)
6022 {
6023 struct m68k_op leftop, rightop;
6024 char c;
6025
6026 /* Swap the compare operands, if necessary, to produce a legal
6027 m68k compare instruction. Comparing a register operand with
6028 a non-register operand requires the register to be on the
6029 right (cmp, cmpa). Comparing an immediate value with
6030 anything requires the immediate value to be on the left
6031 (cmpi). */
6032
6033 c = *leftstop;
6034 *leftstop = '\0';
6035 (void) m68k_ip_op (leftstart, &leftop);
6036 *leftstop = c;
6037
6038 c = *rightstop;
6039 *rightstop = '\0';
6040 (void) m68k_ip_op (rightstart, &rightop);
6041 *rightstop = c;
6042
6043 if (rightop.mode == IMMED
6044 || ((leftop.mode == DREG || leftop.mode == AREG)
6045 && (rightop.mode != DREG && rightop.mode != AREG)))
6046 {
6047 char *temp;
6048
31302357
AS		 6049 /* Correct conditional handling:
6050 if #1 <lt> d0 then ;means if (1 < d0)
6051 ...
6052 endi
e1f44d10 6053
31302357 6054 should assemble to:
e1f44d10 6055
31302357
AS		 6056 cmp #1,d0 if we do *not* swap the operands
6057 bgt true we need the swapped condition!
6058 ble false
6059 true:
6060 ...
6061 false:
6062 */
252b5132
RH		 6063 temp = leftstart;
6064 leftstart = rightstart;
6065 rightstart = temp;
6066 temp = leftstop;
6067 leftstop = rightstop;
6068 rightstop = temp;
8a104df9
KH		 6069 }
6070 else
6071 {
e1f44d10 6072 cc = swap_mri_condition (cc);
252b5132
RH		 6073 }
6074 }
6075
6076 if (truelab == NULL)
6077 {
6078 cc = reverse_mri_condition (cc);
6079 truelab = falselab;
6080 }
92774660 6081
252b5132
RH		 6082 if (leftstart != NULL)
6083 {
6084 buf = (char *) xmalloc (20
6085 + (leftstop - leftstart)
6086 + (rightstop - rightstart));
6087 s = buf;
6088 *s++ = 'c';
6089 *s++ = 'm';
6090 *s++ = 'p';
6091 if (qual != '\0')
3882b010 6092 *s++ = TOLOWER (qual);
252b5132
RH		 6093 *s++ = ' ';
6094 memcpy (s, leftstart, leftstop - leftstart);
6095 s += leftstop - leftstart;
6096 *s++ = ',';
6097 memcpy (s, rightstart, rightstop - rightstart);
6098 s += rightstop - rightstart;
6099 *s = '\0';
6100 mri_assemble (buf);
6101 free (buf);
6102 }
92774660 6103
252b5132
RH		 6104 buf = (char *) xmalloc (20 + strlen (truelab));
6105 s = buf;
6106 *s++ = 'b';
6107 *s++ = cc >> 8;
6108 *s++ = cc & 0xff;
6109 if (extent != '\0')
3882b010 6110 *s++ = TOLOWER (extent);
252b5132
RH		 6111 *s++ = ' ';
6112 strcpy (s, truelab);
6113 mri_assemble (buf);
6114 free (buf);
6115}
6116
6117/* Parse an MRI structured control expression. This generates test
6118 and branch instructions. STOP is where the expression ends. It
6119 goes to TRUELAB if the condition is true, and to FALSELAB if the
6120 condition is false. Exactly one of TRUELAB and FALSELAB will be
6121 NULL, meaning to fall through. QUAL is the size qualifier for the
6122 expression. EXTENT is the size to use for the branch. */
6123
6124static void
31302357
AS		 6125parse_mri_control_expression (char *stop, int qual, const char *truelab,
6126 const char *falselab, int extent)
252b5132
RH		 6127{
6128 int c;
6129 int cc;
6130 char *leftstart;
6131 char *leftstop;
6132 char *rightstart;
6133 char *rightstop;
6134
6135 c = *stop;
6136 *stop = '\0';
6137
6138 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6139 &rightstart, &rightstop))
6140 {
6141 *stop = c;
6142 return;
6143 }
6144
6145 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6146 {
6147 const char *flab;
6148
6149 if (falselab != NULL)
6150 flab = falselab;
6151 else
6152 flab = mri_control_label ();
6153
6154 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6155 rightstop, (const char *) NULL, flab, extent);
6156
6157 input_line_pointer += 3;
6158 if (*input_line_pointer != '.'
6159 || input_line_pointer[1] == '\0')
6160 qual = '\0';
6161 else
6162 {
6163 qual = input_line_pointer[1];
6164 input_line_pointer += 2;
6165 }
6166
6167 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6168 &rightstart, &rightstop))
6169 {
6170 *stop = c;
6171 return;
6172 }
6173
6174 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6175 rightstop, truelab, falselab, extent);
6176
6177 if (falselab == NULL)
6178 colon (flab);
6179 }
6180 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6181 {
6182 const char *tlab;
6183
6184 if (truelab != NULL)
6185 tlab = truelab;
6186 else
6187 tlab = mri_control_label ();
6188
6189 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6190 rightstop, tlab, (const char *) NULL, extent);
6191
6192 input_line_pointer += 2;
6193 if (*input_line_pointer != '.'
6194 || input_line_pointer[1] == '\0')
6195 qual = '\0';
6196 else
6197 {
6198 qual = input_line_pointer[1];
6199 input_line_pointer += 2;
6200 }
6201
6202 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6203 &rightstart, &rightstop))
6204 {
6205 *stop = c;
6206 return;
6207 }
6208
6209 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6210 rightstop, truelab, falselab, extent);
6211
6212 if (truelab == NULL)
6213 colon (tlab);
6214 }
6215 else
6216 {
6217 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6218 rightstop, truelab, falselab, extent);
6219 }
6220
6221 *stop = c;
6222 if (input_line_pointer != stop)
6223 as_bad (_("syntax error in structured control directive"));
6224}
6225
6226/* Handle the MRI IF pseudo-op. This may be a structured control
6227 directive, or it may be a regular assembler conditional, depending
6228 on its operands. */
6229
6230static void
31302357 6231s_mri_if (int qual)
252b5132
RH		 6232{
6233 char *s;
6234 int c;
6235 struct mri_control_info *n;
6236
6237 /* A structured control directive must end with THEN with an
6238 optional qualifier. */
6239 s = input_line_pointer;
e1f44d10
NC		 6240 /* We only accept '*' as introduction of comments if preceded by white space
6241 or at first column of a line (I think this can't actually happen here?)
6242 This is important when assembling:
6243 if d0 <ne> 12(a0,d0*2) then
36759679 6244 if d0 <ne> #CONST*20 then. */
31302357
AS		 6245 while (! (is_end_of_line[(unsigned char) *s]
6246 || (flag_mri
6247 && *s == '*'
6248 && (s == input_line_pointer
6249 || *(s-1) == ' '
6250 || *(s-1) == '\t'))))
252b5132
RH		 6251 ++s;
6252 --s;
6253 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6254 --s;
6255
6256 if (s - input_line_pointer > 1
6257 && s[-1] == '.')
6258 s -= 2;
6259
6260 if (s - input_line_pointer < 3
6261 || strncasecmp (s - 3, "THEN", 4) != 0)
6262 {
6263 if (qual != '\0')
6264 {
6265 as_bad (_("missing then"));
6266 ignore_rest_of_line ();
6267 return;
6268 }
6269
6270 /* It's a conditional. */
6271 s_if (O_ne);
6272 return;
6273 }
6274
6275 /* Since this might be a conditional if, this pseudo-op will be
6276 called even if we are supported to be ignoring input. Double
6277 check now. Clobber *input_line_pointer so that ignore_input
6278 thinks that this is not a special pseudo-op. */
6279 c = *input_line_pointer;
6280 *input_line_pointer = 0;
6281 if (ignore_input ())
6282 {
6283 *input_line_pointer = c;
6284 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6285 ++input_line_pointer;
6286 demand_empty_rest_of_line ();
6287 return;
6288 }
6289 *input_line_pointer = c;
6290
6291 n = push_mri_control (mri_if);
6292
6293 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6294 n->next, s[1] == '.' ? s[2] : '\0');
6295
6296 if (s[1] == '.')
6297 input_line_pointer = s + 3;
6298 else
6299 input_line_pointer = s + 1;
6300
6301 if (flag_mri)
6302 {
6303 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6304 ++input_line_pointer;
6305 }
6306
6307 demand_empty_rest_of_line ();
6308}
6309
6310/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6311 structured IF, associate the ELSE with the IF. Otherwise, assume
6312 it is a conditional else. */
6313
6314static void
31302357 6315s_mri_else (int qual)
252b5132
RH		 6316{
6317 int c;
6318 char *buf;
6319 char q[2];
6320
6321 if (qual == '\0'
6322 && (mri_control_stack == NULL
6323 || mri_control_stack->type != mri_if
6324 || mri_control_stack->else_seen))
6325 {
6326 s_else (0);
6327 return;
6328 }
6329
6330 c = *input_line_pointer;
6331 *input_line_pointer = 0;
6332 if (ignore_input ())
6333 {
6334 *input_line_pointer = c;
6335 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6336 ++input_line_pointer;
6337 demand_empty_rest_of_line ();
6338 return;
6339 }
6340 *input_line_pointer = c;
6341
6342 if (mri_control_stack == NULL
6343 || mri_control_stack->type != mri_if
6344 || mri_control_stack->else_seen)
6345 {
6346 as_bad (_("else without matching if"));
6347 ignore_rest_of_line ();
6348 return;
6349 }
6350
6351 mri_control_stack->else_seen = 1;
6352
6353 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6354 q[0] = TOLOWER (qual);
252b5132
RH		 6355 q[1] = '\0';
6356 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6357 mri_assemble (buf);
6358 free (buf);
6359
6360 colon (mri_control_stack->next);
6361
6362 if (flag_mri)
6363 {
6364 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6365 ++input_line_pointer;
6366 }
6367
6368 demand_empty_rest_of_line ();
6369}
6370
6371/* Handle the MRI ENDI pseudo-op. */
6372
6373static void
31302357 6374s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6375{
6376 if (mri_control_stack == NULL
6377 || mri_control_stack->type != mri_if)
6378 {
6379 as_bad (_("endi without matching if"));
6380 ignore_rest_of_line ();
6381 return;
6382 }
6383
6384 /* ignore_input will not return true for ENDI, so we don't need to
6385 worry about checking it again here. */
6386
6387 if (! mri_control_stack->else_seen)
6388 colon (mri_control_stack->next);
6389 colon (mri_control_stack->bottom);
6390
6391 pop_mri_control ();
6392
6393 if (flag_mri)
6394 {
6395 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6396 ++input_line_pointer;
6397 }
6398
6399 demand_empty_rest_of_line ();
6400}
6401
6402/* Handle the MRI BREAK pseudo-op. */
6403
6404static void
31302357 6405s_mri_break (int extent)
252b5132
RH		 6406{
6407 struct mri_control_info *n;
6408 char *buf;
6409 char ex[2];
6410
6411 n = mri_control_stack;
6412 while (n != NULL
6413 && n->type != mri_for
6414 && n->type != mri_repeat
6415 && n->type != mri_while)
6416 n = n->outer;
6417 if (n == NULL)
6418 {
6419 as_bad (_("break outside of structured loop"));
6420 ignore_rest_of_line ();
6421 return;
6422 }
6423
6424 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6425 ex[0] = TOLOWER (extent);
252b5132
RH		 6426 ex[1] = '\0';
6427 sprintf (buf, "bra%s %s", ex, n->bottom);
6428 mri_assemble (buf);
6429 free (buf);
6430
6431 if (flag_mri)
6432 {
6433 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6434 ++input_line_pointer;
6435 }
6436
6437 demand_empty_rest_of_line ();
6438}
6439
6440/* Handle the MRI NEXT pseudo-op. */
6441
6442static void
31302357 6443s_mri_next (int extent)
252b5132
RH		 6444{
6445 struct mri_control_info *n;
6446 char *buf;
6447 char ex[2];
6448
6449 n = mri_control_stack;
6450 while (n != NULL
6451 && n->type != mri_for
6452 && n->type != mri_repeat
6453 && n->type != mri_while)
6454 n = n->outer;
6455 if (n == NULL)
6456 {
6457 as_bad (_("next outside of structured loop"));
6458 ignore_rest_of_line ();
6459 return;
6460 }
6461
6462 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6463 ex[0] = TOLOWER (extent);
252b5132
RH		 6464 ex[1] = '\0';
6465 sprintf (buf, "bra%s %s", ex, n->next);
6466 mri_assemble (buf);
6467 free (buf);
6468
6469 if (flag_mri)
6470 {
6471 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6472 ++input_line_pointer;
6473 }
6474
6475 demand_empty_rest_of_line ();
6476}
6477
6478/* Handle the MRI FOR pseudo-op. */
6479
6480static void
31302357 6481s_mri_for (int qual)
252b5132
RH		 6482{
6483 const char *varstart, *varstop;
6484 const char *initstart, *initstop;
6485 const char *endstart, *endstop;
6486 const char *bystart, *bystop;
6487 int up;
6488 int by;
6489 int extent;
6490 struct mri_control_info *n;
6491 char *buf;
6492 char *s;
6493 char ex[2];
6494
6495 /* The syntax is
6496 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6497 */
6498
6499 SKIP_WHITESPACE ();
6500 varstart = input_line_pointer;
6501
6502 /* Look for the '='. */
6503 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6504 && *input_line_pointer != '=')
6505 ++input_line_pointer;
6506 if (*input_line_pointer != '=')
6507 {
6508 as_bad (_("missing ="));
6509 ignore_rest_of_line ();
6510 return;
6511 }
6512
6513 varstop = input_line_pointer;
6514 if (varstop > varstart
6515 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6516 --varstop;
6517
6518 ++input_line_pointer;
6519
6520 initstart = input_line_pointer;
6521
6522 /* Look for TO or DOWNTO. */
6523 up = 1;
6524 initstop = NULL;
6525 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6526 {
6527 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6528 && ! is_part_of_name (input_line_pointer[2]))
6529 {
6530 initstop = input_line_pointer;
6531 input_line_pointer += 2;
6532 break;
6533 }
6534 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6535 && ! is_part_of_name (input_line_pointer[6]))
6536 {
6537 initstop = input_line_pointer;
6538 up = 0;
6539 input_line_pointer += 6;
6540 break;
6541 }
6542 ++input_line_pointer;
6543 }
6544 if (initstop == NULL)
6545 {
6546 as_bad (_("missing to or downto"));
6547 ignore_rest_of_line ();
6548 return;
6549 }
6550 if (initstop > initstart
6551 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6552 --initstop;
6553
6554 SKIP_WHITESPACE ();
6555 endstart = input_line_pointer;
6556
6557 /* Look for BY or DO. */
6558 by = 0;
6559 endstop = NULL;
6560 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6561 {
6562 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6563 && ! is_part_of_name (input_line_pointer[2]))
6564 {
6565 endstop = input_line_pointer;
6566 by = 1;
6567 input_line_pointer += 2;
6568 break;
6569 }
6570 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6571 && (input_line_pointer[2] == '.'
6572 || ! is_part_of_name (input_line_pointer[2])))
6573 {
6574 endstop = input_line_pointer;
6575 input_line_pointer += 2;
6576 break;
6577 }
6578 ++input_line_pointer;
6579 }
6580 if (endstop == NULL)
6581 {
6582 as_bad (_("missing do"));
6583 ignore_rest_of_line ();
6584 return;
6585 }
6586 if (endstop > endstart
6587 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6588 --endstop;
6589
6590 if (! by)
6591 {
6592 bystart = "#1";
6593 bystop = bystart + 2;
6594 }
6595 else
6596 {
6597 SKIP_WHITESPACE ();
6598 bystart = input_line_pointer;
6599
6600 /* Look for DO. */
6601 bystop = NULL;
6602 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6603 {
6604 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6605 && (input_line_pointer[2] == '.'
6606 || ! is_part_of_name (input_line_pointer[2])))
6607 {
6608 bystop = input_line_pointer;
6609 input_line_pointer += 2;
6610 break;
6611 }
6612 ++input_line_pointer;
6613 }
6614 if (bystop == NULL)
6615 {
6616 as_bad (_("missing do"));
6617 ignore_rest_of_line ();
6618 return;
6619 }
6620 if (bystop > bystart
6621 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6622 --bystop;
6623 }
6624
6625 if (*input_line_pointer != '.')
6626 extent = '\0';
6627 else
6628 {
6629 extent = input_line_pointer[1];
6630 input_line_pointer += 2;
6631 }
6632
6633 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6634 n = push_mri_control (mri_for);
6635
6636 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6637
36759679 6638 /* Move init,var. */
252b5132
RH		 6639 s = buf;
6640 *s++ = 'm';
6641 *s++ = 'o';
6642 *s++ = 'v';
6643 *s++ = 'e';
6644 if (qual != '\0')
3882b010 6645 *s++ = TOLOWER (qual);
252b5132
RH		 6646 *s++ = ' ';
6647 memcpy (s, initstart, initstop - initstart);
6648 s += initstop - initstart;
6649 *s++ = ',';
6650 memcpy (s, varstart, varstop - varstart);
6651 s += varstop - varstart;
6652 *s = '\0';
6653 mri_assemble (buf);
6654
6655 colon (n->top);
6656
36759679 6657 /* cmp end,var. */
252b5132
RH		 6658 s = buf;
6659 *s++ = 'c';
6660 *s++ = 'm';
6661 *s++ = 'p';
6662 if (qual != '\0')
3882b010 6663 *s++ = TOLOWER (qual);
252b5132
RH		 6664 *s++ = ' ';
6665 memcpy (s, endstart, endstop - endstart);
6666 s += endstop - endstart;
6667 *s++ = ',';
6668 memcpy (s, varstart, varstop - varstart);
6669 s += varstop - varstart;
6670 *s = '\0';
6671 mri_assemble (buf);
6672
36759679 6673 /* bcc bottom. */
3882b010 6674 ex[0] = TOLOWER (extent);
252b5132
RH		 6675 ex[1] = '\0';
6676 if (up)
6677 sprintf (buf, "blt%s %s", ex, n->bottom);
6678 else
6679 sprintf (buf, "bgt%s %s", ex, n->bottom);
6680 mri_assemble (buf);
6681
6682 /* Put together the add or sub instruction used by ENDF. */
6683 s = buf;
6684 if (up)
6685 strcpy (s, "add");
6686 else
6687 strcpy (s, "sub");
6688 s += 3;
6689 if (qual != '\0')
3882b010 6690 *s++ = TOLOWER (qual);
252b5132
RH		 6691 *s++ = ' ';
6692 memcpy (s, bystart, bystop - bystart);
6693 s += bystop - bystart;
6694 *s++ = ',';
6695 memcpy (s, varstart, varstop - varstart);
6696 s += varstop - varstart;
6697 *s = '\0';
6698 n->incr = buf;
6699
6700 if (flag_mri)
6701 {
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6703 ++input_line_pointer;
6704 }
6705
6706 demand_empty_rest_of_line ();
6707}
6708
6709/* Handle the MRI ENDF pseudo-op. */
6710
6711static void
31302357 6712s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6713{
6714 if (mri_control_stack == NULL
6715 || mri_control_stack->type != mri_for)
6716 {
6717 as_bad (_("endf without for"));
6718 ignore_rest_of_line ();
6719 return;
6720 }
6721
6722 colon (mri_control_stack->next);
6723
6724 mri_assemble (mri_control_stack->incr);
6725
6726 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6727 mri_assemble (mri_control_stack->incr);
6728
6729 free (mri_control_stack->incr);
6730
6731 colon (mri_control_stack->bottom);
6732
6733 pop_mri_control ();
6734
6735 if (flag_mri)
6736 {
6737 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6738 ++input_line_pointer;
6739 }
6740
6741 demand_empty_rest_of_line ();
6742}
6743
6744/* Handle the MRI REPEAT pseudo-op. */
6745
6746static void
31302357 6747s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6748{
6749 struct mri_control_info *n;
6750
6751 n = push_mri_control (mri_repeat);
6752 colon (n->top);
6753 if (flag_mri)
6754 {
6755 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6756 ++input_line_pointer;
6757 }
6758 demand_empty_rest_of_line ();
6759}
6760
6761/* Handle the MRI UNTIL pseudo-op. */
6762
6763static void
31302357 6764s_mri_until (int qual)
252b5132
RH		 6765{
6766 char *s;
6767
6768 if (mri_control_stack == NULL
6769 || mri_control_stack->type != mri_repeat)
6770 {
6771 as_bad (_("until without repeat"));
6772 ignore_rest_of_line ();
6773 return;
6774 }
6775
6776 colon (mri_control_stack->next);
6777
6778 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6779 ;
6780
6781 parse_mri_control_expression (s, qual, (const char *) NULL,
6782 mri_control_stack->top, '\0');
6783
6784 colon (mri_control_stack->bottom);
6785
6786 input_line_pointer = s;
6787
6788 pop_mri_control ();
6789
6790 if (flag_mri)
6791 {
6792 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6793 ++input_line_pointer;
6794 }
6795
6796 demand_empty_rest_of_line ();
6797}
6798
6799/* Handle the MRI WHILE pseudo-op. */
6800
6801static void
31302357 6802s_mri_while (int qual)
252b5132
RH		 6803{
6804 char *s;
6805
6806 struct mri_control_info *n;
6807
6808 s = input_line_pointer;
e1f44d10
NC		 6809 /* We only accept '*' as introduction of comments if preceded by white space
6810 or at first column of a line (I think this can't actually happen here?)
6811 This is important when assembling:
6812 while d0 <ne> 12(a0,d0*2) do
36759679 6813 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6814 while (! (is_end_of_line[(unsigned char) *s]
6815 || (flag_mri
6816 && *s == '*'
6817 && (s == input_line_pointer
6818 || *(s-1) == ' '
6819 || *(s-1) == '\t'))))
252b5132
RH		 6820 s++;
6821 --s;
6822 while (*s == ' ' || *s == '\t')
6823 --s;
6824 if (s - input_line_pointer > 1
6825 && s[-1] == '.')
6826 s -= 2;
6827 if (s - input_line_pointer < 2
6828 || strncasecmp (s - 1, "DO", 2) != 0)
6829 {
6830 as_bad (_("missing do"));
6831 ignore_rest_of_line ();
6832 return;
6833 }
6834
6835 n = push_mri_control (mri_while);
6836
6837 colon (n->next);
6838
6839 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6840 s[1] == '.' ? s[2] : '\0');
6841
6842 input_line_pointer = s + 1;
6843 if (*input_line_pointer == '.')
6844 input_line_pointer += 2;
6845
6846 if (flag_mri)
6847 {
6848 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6849 ++input_line_pointer;
6850 }
6851
6852 demand_empty_rest_of_line ();
6853}
6854
6855/* Handle the MRI ENDW pseudo-op. */
6856
6857static void
31302357 6858s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6859{
6860 char *buf;
6861
6862 if (mri_control_stack == NULL
6863 || mri_control_stack->type != mri_while)
6864 {
6865 as_bad (_("endw without while"));
6866 ignore_rest_of_line ();
6867 return;
6868 }
6869
6870 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6871 sprintf (buf, "bra %s", mri_control_stack->next);
6872 mri_assemble (buf);
6873 free (buf);
6874
6875 colon (mri_control_stack->bottom);
6876
6877 pop_mri_control ();
6878
6879 if (flag_mri)
6880 {
6881 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6882 ++input_line_pointer;
6883 }
6884
6885 demand_empty_rest_of_line ();
6886}
6887\f
266abb8f
NS		 6888/* Parse a .cpu directive. */
6889
6890static void
6891s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6892{
6893 char saved_char;
6894 char *name;
6895
6896 if (initialized)
6897 {
6898 as_bad (_("already assembled instructions"));
6899 ignore_rest_of_line ();
6900 return;
6901 }
6902
6903 name = input_line_pointer;
6904 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6905 input_line_pointer++;
6906 saved_char = *input_line_pointer;
6907 *input_line_pointer = 0;
6908
6909 m68k_set_cpu (name, 1, 0);
6910
6911 *input_line_pointer = saved_char;
6912 demand_empty_rest_of_line ();
6913 return;
6914}
6915
6916/* Parse a .arch directive. */
6917
6918static void
6919s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6920{
6921 char saved_char;
6922 char *name;
6923
6924 if (initialized)
6925 {
6926 as_bad (_("already assembled instructions"));
6927 ignore_rest_of_line ();
6928 return;
6929 }
6930
6931 name = input_line_pointer;
6932 while (*input_line_pointer && *input_line_pointer != ','
6933 && !ISSPACE (*input_line_pointer))
6934 input_line_pointer++;
6935 saved_char = *input_line_pointer;
6936 *input_line_pointer = 0;
6937
6938 if (m68k_set_arch (name, 1, 0))
6939 {
6940 /* Scan extensions. */
6941 do
6942 {
6943 *input_line_pointer++ = saved_char;
6944 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
6945 break;
6946 name = input_line_pointer;
6947 while (*input_line_pointer && *input_line_pointer != ','
6948 && !ISSPACE (*input_line_pointer))
6949 input_line_pointer++;
6950 saved_char = *input_line_pointer;
6951 *input_line_pointer = 0;
6952 }
6953 while (m68k_set_extension (name, 1, 0));
6954 }
6955
6956 *input_line_pointer = saved_char;
6957 demand_empty_rest_of_line ();
6958 return;
6959}
6960\f
6961/* Lookup a cpu name in TABLE and return the slot found. Return NULL
6962 if none is found, the caller is responsible for emitting an error
6963 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
6964 cpu name, if it begins with a '6' (possibly skipping an intervening
6965 'c'. We also allow a 'c' in the same place. if NEGATED is
6966 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
6967 the option is indeed negated. */
6968
6969static const struct m68k_cpu *
6970m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
6971 int allow_m, int *negated)
6972{
6973 /* allow negated value? */
6974 if (negated)
6975 {
6976 *negated = 0;
6977
6978 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6979 {
6980 arg += 3;
6981 *negated = 1;
6982 }
6983 }
6984
6985 /* Remove 'm' or 'mc' prefix from 68k variants. */
6986 if (allow_m)
6987 {
6988 if (arg[0] == 'm')
6989 {
6990 if (arg[1] == '6')
6991 arg += 1;
6992 else if (arg[1] == 'c' && arg[2] == '6')
6993 arg += 2;
6994 }
6995 }
6996 else if (arg[0] == 'c' && arg[1] == '6')
6997 arg += 1;
6998
6999 for (; table->name; table++)
7000 if (!strcmp (arg, table->name))
2da12c60
NS		 7001 {
7002 if (table->alias < -1 || table->alias > 1)
7003 as_bad (_("`%s' is deprecated, use `%s'"),
7004 table->name, table[table->alias < 0 ? 1 : -1].name);
7005 return table;
7006 }
266abb8f
NS		 7007 return 0;
7008}
7009
7010/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7011
7012static int
7013m68k_set_cpu (char const *name, int allow_m, int silent)
7014{
7015 const struct m68k_cpu *cpu;
7016
7017 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7018
7019 if (!cpu)
7020 {
7021 if (!silent)
7022 as_bad (_("cpu `%s' unrecognized"), name);
7023 return 0;
7024 }
7025
7026 if (selected_cpu && selected_cpu != cpu)
7027 {
7028 as_bad (_("already selected `%s' processor"),
7029 selected_cpu->name);
7030 return 0;
7031 }
7032 selected_cpu = cpu;
7033 return 1;
7034}
7035
7036/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7037
7038static int
7039m68k_set_arch (char const *name, int allow_m, int silent)
7040{
7041 const struct m68k_cpu *arch;
7042
7043 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7044
7045 if (!arch)
7046 {
7047 if (!silent)
7048 as_bad (_("architecture `%s' unrecognized"), name);
7049 return 0;
7050 }
7051
7052 if (selected_arch && selected_arch != arch)
7053 {
7054 as_bad (_("already selected `%s' architecture"),
7055 selected_arch->name);
7056 return 0;
7057 }
7058
7059 selected_arch = arch;
7060 return 1;
7061}
7062
7063/* Set the architecture extension, issuing errors if it is
7064 unrecognized, or invalid */
7065
7066static int
7067m68k_set_extension (char const *name, int allow_m, int silent)
7068{
7069 int negated;
7070 const struct m68k_cpu *ext;
7071
7072 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7073
7074 if (!ext)
7075 {
7076 if (!silent)
7077 as_bad (_("extension `%s' unrecognized"), name);
7078 return 0;
7079 }
7080
7081 if (negated)
7082 not_current_architecture |= ext->arch;
7083 else
7084 current_architecture |= ext->arch;
7085 return 1;
7086}
7087
31302357
AS		 7088/* md_parse_option
7089 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7090 */
252b5132
RH		 7091
7092#ifdef OBJ_ELF
5a38dc70 7093const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7094#else
5a38dc70 7095const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7096#endif
7097
7098struct option md_longopts[] = {
7099#define OPTION_PIC (OPTION_MD_BASE)
7100 {"pic", no_argument, NULL, OPTION_PIC},
7101#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7102 {"register-prefix-optional", no_argument, NULL,
7103 OPTION_REGISTER_PREFIX_OPTIONAL},
7104#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7105 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7106#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7107 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7108#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7109 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7110#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7111 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7112#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7113 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7114#define OPTION_PCREL (OPTION_MD_BASE + 7)
7115 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7116 {NULL, no_argument, NULL, 0}
7117};
bc805888 7118size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7119
7120int
31302357 7121md_parse_option (int c, char *arg)
252b5132
RH		 7122{
7123 switch (c)
7124 {
7125 case 'l': /* -l means keep external to 2 bit offset
36759679 7126 rather than 16 bit one. */
252b5132
RH		 7127 flag_short_refs = 1;
7128 break;
7129
7130 case 'S': /* -S means that jbsr's always turn into
7131 jsr's. */
7132 flag_long_jumps = 1;
7133 break;
7134
28e7409f
NC		 7135 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7136 branches into absolute jumps. */
7137 flag_keep_pcrel = 1;
7138 break;
7139
252b5132
RH		 7140 case OPTION_PIC:
7141 case 'k':
7142 flag_want_pic = 1;
36759679 7143 break; /* -pic, Position Independent Code. */
252b5132
RH		 7144
7145 case OPTION_REGISTER_PREFIX_OPTIONAL:
7146 flag_reg_prefix_optional = 1;
7147 reg_prefix_optional_seen = 1;
7148 break;
7149
7150 /* -V: SVR4 argument to print version ID. */
7151 case 'V':
7152 print_version_id ();
7153 break;
7154
7155 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7156 should be emitted or not. FIXME: Not implemented. */
7157 case 'Q':
7158 break;
7159
7160 case OPTION_BITWISE_OR:
7161 {
7162 char *n, *t;
7163 const char *s;
7164
7165 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7166 t = n;
7167 for (s = m68k_comment_chars; *s != '\0'; s++)
7168 if (*s != '|')
7169 *t++ = *s;
7170 *t = '\0';
7171 m68k_comment_chars = n;
7172 }
7173 break;
7174
7175 case OPTION_BASE_SIZE_DEFAULT_16:
7176 m68k_index_width_default = SIZE_WORD;
7177 break;
7178
7179 case OPTION_BASE_SIZE_DEFAULT_32:
7180 m68k_index_width_default = SIZE_LONG;
7181 break;
7182
7183 case OPTION_DISP_SIZE_DEFAULT_16:
7184 m68k_rel32 = 0;
7185 m68k_rel32_from_cmdline = 1;
7186 break;
7187
7188 case OPTION_DISP_SIZE_DEFAULT_32:
7189 m68k_rel32 = 1;
7190 m68k_rel32_from_cmdline = 1;
7191 break;
7192
266abb8f
NS		 7193 case 'A':
7194#if WARN_DEPRECATED
7195 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7196 arg, arg));
7197#endif
7198 /* Intentional fall-through. */
7199 case 'm':
7200 if (!strncmp (arg, "arch=", 5))
7201 m68k_set_arch (arg + 5, 1, 0);
7202 else if (!strncmp (arg, "cpu=", 4))
7203 m68k_set_cpu (arg + 4, 1, 0);
7204 else if (m68k_set_extension (arg, 0, 1))
7205 ;
0b2e31dc
NS		 7206 else if (m68k_set_arch (arg, 0, 1))
7207 ;
266abb8f
NS		 7208 else if (m68k_set_cpu (arg, 0, 1))
7209 ;
7210 else
7211 return 0;
7212 break;
7213
252b5132
RH		 7214 default:
7215 return 0;
7216 }
7217
7218 return 1;
7219}
7220
266abb8f
NS		 7221/* Setup tables from the selected arch and/or cpu */
7222
7223static void
7224m68k_init_arch (void)
7225{
266abb8f
NS		 7226 if (not_current_architecture & current_architecture)
7227 {
7228 as_bad (_("architecture features both enabled and disabled"));
7229 not_current_architecture &= ~current_architecture;
7230 }
7231 if (selected_arch)
2da12c60
NS		 7232 {
7233 current_architecture |= selected_arch->arch;
7234 control_regs = selected_arch->control_regs;
7235 }
0b2e31dc
NS		 7236 else
7237 current_architecture |= selected_cpu->arch;
0b2e31dc 7238
2da12c60
NS		 7239 current_architecture &= ~not_current_architecture;
7240
377260ba
NS		 7241 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7242 {
7243 /* Determine which float is really meant. */
7244 if (current_architecture & (m68k_mask & ~m68881))
7245 current_architecture ^= cfloat;
7246 else
7247 current_architecture ^= m68881;
7248 }
7249
0b2e31dc 7250 if (selected_cpu)
266abb8f 7251 {
2da12c60 7252 control_regs = selected_cpu->control_regs;
0b2e31dc 7253 if (current_architecture & ~selected_cpu->arch)
266abb8f 7254 {
0b2e31dc
NS		 7255 as_bad (_("selected processor does not have all features of selected architecture"));
7256 current_architecture
7257 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7258 }
7259 }
266abb8f 7260
266abb8f
NS		 7261 if ((current_architecture & m68k_mask)
7262 && (current_architecture & ~m68k_mask))
7263 {
7264 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7265 if (current_architecture & m68k_mask)
266abb8f
NS		 7266 current_architecture &= m68k_mask;
7267 else
7268 current_architecture &= ~m68k_mask;
7269 }
7270
7271 /* Permit m68881 specification with all cpus; those that can't work
7272 with a coprocessor could be doing emulation. */
7273 if (current_architecture & m68851)
7274 {
7275 if (current_architecture & m68040)
7276 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7277 }
7278 /* What other incompatibilities could we check for? */
7279
266abb8f
NS		 7280 if (cpu_of_arch (current_architecture) < m68020
7281 || arch_coldfire_p (current_architecture))
7282 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7283
7284 initialized = 1;
7285}
7286
252b5132 7287void
31302357 7288md_show_usage (FILE *stream)
252b5132 7289{
76f57f3a 7290 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7291 int i;
7292 unsigned int default_arch;
76f57f3a 7293
8a104df9 7294 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7295 if (*default_cpu == 'm')
7296 default_cpu++;
266abb8f 7297 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7298 {
266abb8f 7299 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7300 {
266abb8f 7301 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7302 while (m68k_cpus[i].alias > 0)
7303 i--;
7304 while (m68k_cpus[i].alias < 0)
7305 i++;
7306 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7307 }
7308 }
7309
bc805888 7310 fprintf (stream, _("\
266abb8f
NS		 7311-march=<arch> set architecture\n\
7312-mcpu=<cpu> set cpu [default %s]\n\
7313"), default_cpu);
7314 for (i = 0; m68k_extensions[i].name; i++)
7315 fprintf (stream, _("\
0b2e31dc
NS		 7316-m[no-]%-16s enable/disable%s architecture extension\n\
7317"), m68k_extensions[i].name,
7318 m68k_extensions[i].alias > 0 ? " ColdFire"
7319 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7320
bc805888 7321 fprintf (stream, _("\
266abb8f 7322-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7323-pic, -k generate position independent code\n\
7324-S turn jbsr into jsr\n\
28e7409f 7325--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7326--register-prefix-optional\n\
7327 recognize register names without prefix character\n\
266abb8f 7328--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7329--base-size-default-16 base reg without size is 16 bits\n\
7330--base-size-default-32 base reg without size is 32 bits (default)\n\
7331--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7332--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7333"));
7334
7335 fprintf (stream, _("Architecture variants are: "));
7336 for (i = 0; m68k_archs[i].name; i++)
7337 {
7338 if (i)
7339 fprintf (stream, " | ");
7340 fprintf (stream, m68k_archs[i].name);
7341 }
7342 fprintf (stream, "\n");
7343
7344 fprintf (stream, _("Processor variants are: "));
7345 for (i = 0; m68k_cpus[i].name; i++)
7346 {
7347 if (i)
7348 fprintf (stream, " | ");
7349 fprintf (stream, m68k_cpus[i].name);
7350 }
7351 fprintf (stream, _("\n"));
252b5132
RH		 7352}
7353\f
7354#ifdef TEST2
7355
7356/* TEST2: Test md_assemble() */
36759679
NC		 7357/* Warning, this routine probably doesn't work anymore. */
7358int
31302357 7359main (void)
252b5132
RH		 7360{
7361 struct m68k_it the_ins;
7362 char buf[120];
7363 char *cp;
7364 int n;
7365
7366 m68k_ip_begin ();
7367 for (;;)
7368 {
7369 if (!gets (buf) || !*buf)
7370 break;
7371 if (buf[0] == '|' || buf[1] == '.')
7372 continue;
7373 for (cp = buf; *cp; cp++)
7374 if (*cp == '\t')
7375 *cp = ' ';
7376 if (is_label (buf))
7377 continue;
7378 memset (&the_ins, '\0', sizeof (the_ins));
7379 m68k_ip (&the_ins, buf);
7380 if (the_ins.error)
7381 {
7382 printf (_("Error %s in %s\n"), the_ins.error, buf);
7383 }
7384 else
7385 {
7386 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7387 for (n = 0; n < the_ins.numo; n++)
7388 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7389 printf (" ");
7390 print_the_insn (&the_ins.opcode[0], stdout);
7391 (void) putchar ('\n');
7392 }
7393 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7394 {
7395 if (the_ins.operands[n].error)
7396 {
7397 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7398 continue;
7399 }
31302357
AS		 7400 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7401 the_ins.operands[n].reg);
252b5132 7402 if (the_ins.operands[n].b_const)
31302357
AS		 7403 printf ("Constant: '%.*s', ",
7404 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7405 the_ins.operands[n].b_const);
7406 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7407 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7408 if (the_ins.operands[n].b_iadd)
31302357
AS		 7409 printf ("Iadd: '%.*s',",
7410 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7411 the_ins.operands[n].b_iadd);
7412 putchar ('\n');
252b5132
RH		 7413 }
7414 }
7415 m68k_ip_end ();
7416 return 0;
7417}
7418
31302357
AS		 7419int
7420is_label (char *str)
252b5132
RH		 7421{
7422 while (*str == ' ')
7423 str++;
7424 while (*str && *str != ' ')
7425 str++;
7426 if (str[-1] == ':' || str[1] == '=')
7427 return 1;
7428 return 0;
7429}
7430
7431#endif
7432
7433/* Possible states for relaxation:
7434
7435 0 0 branch offset byte (bra, etc)
7436 0 1 word
7437 0 2 long
7438
7439 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7440 1 1 word
7441 1 2 long
7442
7443 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7444 2 1 word-long
7445 2 2 long-word
7446 2 3 long-long
7447
7448 */
7449
7450/* We have no need to default values of symbols. */
7451
252b5132 7452symbolS *
31302357 7453md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7454{
7455 return 0;
7456}
7457
7458/* Round up a section size to the appropriate boundary. */
7459valueT
31302357 7460md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7461{
7462#ifdef OBJ_AOUT
252b5132
RH		 7463 /* For a.out, force the section size to be aligned. If we don't do
7464 this, BFD will align it for us, but it will not write out the
7465 final bytes of the section. This may be a bug in BFD, but it is
7466 easier to fix it here since that is how the other a.out targets
7467 work. */
7468 int align;
7469
7470 align = bfd_get_section_alignment (stdoutput, segment);
7471 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7472#endif
7473
7474 return size;
7475}
7476
7477/* Exactly what point is a PC-relative offset relative TO?
7478 On the 68k, it is relative to the address of the first extension
7479 word. The difference between the addresses of the offset and the
92774660 7480 first extension word is stored in fx_pcrel_adjust. */
252b5132 7481long
31302357 7482md_pcrel_from (fixS *fixP)
252b5132
RH		 7483{
7484 int adjust;
7485
8390138c
AS		 7486 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7487 sign extend the value here. */
7488 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7489 if (adjust == 64)
7490 adjust = -1;
7491 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7492}
7493
0d96863f 7494#ifdef OBJ_ELF
8a104df9 7495void
31302357 7496m68k_elf_final_processing (void)
0d96863f 7497{
266abb8f
NS		 7498 unsigned flags = 0;
7499
238d258f 7500 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7501 flags |= EF_M68K_CFV4E;
7502 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7503 if (cpu_of_arch (current_architecture) & cpu32)
9840d27e
KH		 7504 {
7505 flags |= EF_M68K_CPU32;
7506 if (cpu_of_arch (current_architecture) & fido_a)
7507 flags |= EF_M68K_CPU32_FIDO_A;
7508 }
8a104df9
KH		 7509 else if ((cpu_of_arch (current_architecture) & m68000up)
7510 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7511 flags |= EF_M68K_M68000;
7512
7513 if (current_architecture & mcfisa_a)
7514 {
0b2e31dc
NS		 7515 static const unsigned isa_features[][2] =
7516 {
c694fd50
KH		 7517 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7518 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7519 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7520 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7521 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
0b2e31dc
NS		 7522 {0,0},
7523 };
7524 static const unsigned mac_features[][2] =
7525 {
c694fd50
KH		 7526 {EF_M68K_CF_MAC, mcfmac},
7527 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7528 {0,0},
7529 };
7530 unsigned ix;
7531 unsigned pattern;
266abb8f 7532
0b2e31dc
NS		 7533 pattern = (current_architecture
7534 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7535 for (ix = 0; isa_features[ix][1]; ix++)
7536 {
7537 if (pattern == isa_features[ix][1])
7538 {
7539 flags |= isa_features[ix][0];
7540 break;
7541 }
7542 }
7543 if (!isa_features[ix][1])
7544 {
7545 cf_bad:
7546 as_warn (_("Not a defined coldfire architecture"));
7547 }
7548 else
7549 {
7550 if (current_architecture & cfloat)
c694fd50 7551 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7552
0b2e31dc
NS		 7553 pattern = current_architecture & (mcfmac|mcfemac);
7554 if (pattern)
7555 {
7556 for (ix = 0; mac_features[ix][1]; ix++)
7557 {
7558 if (pattern == mac_features[ix][1])
7559 {
7560 flags |= mac_features[ix][0];
7561 break;
7562 }
7563 }
7564 if (!mac_features[ix][1])
7565 goto cf_bad;
7566 }
7567 }
266abb8f
NS		 7568 }
7569 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f
CM		 7570}
7571#endif
c04898f8
AS		 7572
7573int
1df69f4f 7574tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 7575{
7576 unsigned int regnum;
7577 static const char *const regnames[] =
7578 {
7579 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7580 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7581 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7582 "pc"
7583 };
7584
7585 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7586 if (strcmp (regname, regnames[regnum]) == 0)
7587 return regnum;
7588
7589 return -1;
7590}
7591
7592void
7593tc_m68k_frame_initial_instructions (void)
7594{
7595 static int sp_regno = -1;
7596
7597 if (sp_regno < 0)
7598 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7599
7600 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7601 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7602}
GDB Binutils - Deliverables
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