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* ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
[deliverable/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
6358301e 3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
252b5132
RH		 36/* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40#if defined (TE_SVR4) || defined (TE_DELTA)
41const char *m68k_comment_chars = "|#";
42#else
43const char *m68k_comment_chars = "|";
44#endif
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
92774660
KH		 51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
252b5132
RH		 53const char line_comment_chars[] = "#*";
54
63a0b638 55const char line_separator_chars[] = ";";
252b5132 56
36759679 57/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 58const char EXP_CHARS[] = "eE";
252b5132
RH		 59
60/* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
5a38dc70 63const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 64
65/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
36759679 69const int md_reloc_size = 8; /* Size of relocation record. */
252b5132
RH		 70
71/* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
92774660 73 references. Not implemented. For ELF there are other means
252b5132
RH		 74 to denote pic relocations. */
75int flag_want_pic;
76
36759679
NC		 77static int flag_short_refs; /* -l option. */
78static int flag_long_jumps; /* -S option. */
28e7409f 79static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 80
81#ifdef REGISTER_PREFIX_OPTIONAL
82int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83#else
84int flag_reg_prefix_optional;
85#endif
86
87/* Whether --register-prefix-optional was used on the command line. */
88static int reg_prefix_optional_seen;
89
90/* The floating point coprocessor to use by default. */
91static enum m68k_register m68k_float_copnum = COP1;
92
93/* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95static int m68k_abspcadd;
96
97/* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99static int m68k_quick = 1;
100
101/* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104static int m68k_rel32 = 1;
105
106/* This is non-zero if m68k_rel32 was set from the command line. */
107static int m68k_rel32_from_cmdline;
108
109/* The default width to use for an index register when using a base
110 displacement. */
111static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113/* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
252b5132
RH		 116struct label_line
117{
118 struct label_line *next;
119 symbolS *label;
120 char *file;
121 unsigned int line;
122 int text;
123};
124
125/* The list of labels. */
126
127static struct label_line *labels;
128
129/* The current label. */
130
131static struct label_line *current_label;
132
36759679
NC		 133/* Its an arbitrary name: This means I don't approve of it.
134 See flames below. */
252b5132
RH		 135static struct obstack robyn;
136
252b5132
RH		 137struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148#define gettwo(x) (((x)->m_opcode)&0xffff)
149
150static const enum m68k_register m68000_control_regs[] = { 0 };
151static const enum m68k_register m68010_control_regs[] = {
152 SFC, DFC, USP, VBR,
153 0
154};
155static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158};
159static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163};
164static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168};
6da466c7 169static const enum m68k_register mcf_control_regs[] = {
3e602632 170 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 171 RAMBAR0, RAMBAR1, MBAR,
172 0
173};
3e602632
NC		 174static const enum m68k_register mcf528x_control_regs[] = {
175 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
176 0
177};
178static const enum m68k_register mcfv4e_control_regs[] = {
179 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
180 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
181 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
182 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
183 0
184};
252b5132
RH		 185#define cpu32_control_regs m68010_control_regs
186
187static const enum m68k_register *control_regs;
188
36759679 189/* Internal form of a 68020 instruction. */
252b5132
RH		 190struct m68k_it
191{
192 const char *error;
36759679 193 const char *args; /* List of opcode info. */
252b5132
RH		 194 int numargs;
195
36759679 196 int numo; /* Number of shorts in opcode. */
252b5132
RH		 197 short opcode[11];
198
199 struct m68k_op operands[6];
200
36759679 201 int nexp; /* Number of exprs in use. */
252b5132
RH		 202 struct m68k_exp exprs[4];
203
36759679 204 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 205 struct
206 {
36759679 207 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 208 symbolS *fadd;
209 offsetT foff;
210 int fragty;
211 }
212 fragb[4];
213
36759679 214 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 215 struct
216 {
217 int n;
218 expressionS exp;
219 char wid;
220 char pcrel;
221 /* In a pc relative address the difference between the address
222 of the offset and the address that the offset is relative
223 to. This depends on the addressing mode. Basically this
224 is the value to put in the offset field to address the
225 first byte of the offset, without regarding the special
226 significance of some values (in the branch instruction, for
227 example). */
228 int pcrel_fix;
229#ifdef OBJ_ELF
230 /* Whether this expression needs special pic relocation, and if
231 so, which. */
232 enum pic_relocation pic_reloc;
233#endif
234 }
36759679 235 reloc[5]; /* Five is enough??? */
252b5132
RH		 236};
237
3e602632 238#define cpu_of_arch(x) ((x) & (m68000up | mcf))
252b5132
RH		 239#define float_of_arch(x) ((x) & mfloat)
240#define mmu_of_arch(x) ((x) & mmmu)
3e602632
NC		 241#define arch_coldfire_p(x) ((x) & mcf)
242#define arch_coldfire_v4e_p(x) ((x) & mcfv4e)
252b5132 243
36759679 244/* Macros for determining if cpu supports a specific addressing mode. */
3e602632 245#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407|mcfv4e))
252b5132 246
36759679 247static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 248
249#define op(ex) ((ex)->exp.X_op)
250#define adds(ex) ((ex)->exp.X_add_symbol)
251#define subs(ex) ((ex)->exp.X_op_symbol)
252#define offs(ex) ((ex)->exp.X_add_number)
253
36759679 254/* Macros for adding things to the m68k_it struct. */
252b5132
RH		 255#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
256
257/* Static functions. */
252b5132
RH		 258static void insop PARAMS ((int, const struct m68k_incant *));
259static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
260static void add_frag PARAMS ((symbolS *, offsetT, int));
261
36759679
NC		 262/* Like addword, but goes BEFORE general operands. */
263
252b5132
RH		 264static void
265insop (w, opcode)
266 int w;
267 const struct m68k_incant *opcode;
268{
269 int z;
07726851 270 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 271 the_ins.opcode[z] = the_ins.opcode[z - 1];
272 for (z = 0; z < the_ins.nrel; z++)
273 the_ins.reloc[z].n += 2;
252b5132
RH		 274 for (z = 0; z < the_ins.nfrag; z++)
275 the_ins.fragb[z].fragoff++;
8a104df9 276 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 277 the_ins.numo++;
278}
279
280/* The numo+1 kludge is so we can hit the low order byte of the prev word.
281 Blecch. */
282static void
283add_fix (width, exp, pc_rel, pc_fix)
284 int width;
285 struct m68k_exp *exp;
286 int pc_rel;
287 int pc_fix;
288{
289 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
290 ? (the_ins.numo*2-1)
291 : (((width)=='b')
292 ? (the_ins.numo*2+1)
293 : (the_ins.numo*2)));
294 the_ins.reloc[the_ins.nrel].exp = exp->exp;
295 the_ins.reloc[the_ins.nrel].wid = width;
296 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
297#ifdef OBJ_ELF
298 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
299#endif
300 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
301}
302
303/* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
307
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
311
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
313static void
314add_frag (add, off, type)
315 symbolS *add;
316 offsetT off;
317 int type;
318{
8a104df9
KH		 319 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
320 the_ins.fragb[the_ins.nfrag].fadd = add;
321 the_ins.fragb[the_ins.nfrag].foff = off;
322 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 323}
324
325#define isvar(ex) \
326 (op (ex) != O_constant && op (ex) != O_big)
327
328static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
329static int get_num PARAMS ((struct m68k_exp *exp, int ok));
330static void m68k_ip PARAMS ((char *));
331static void insert_reg PARAMS ((const char *, int));
332static void select_control_regs PARAMS ((void));
333static void init_regtable PARAMS ((void));
334static int reverse_16_bits PARAMS ((int in));
335static int reverse_8_bits PARAMS ((int in));
336static void install_gen_operand PARAMS ((int mode, int val));
337static void install_operand PARAMS ((int mode, int val));
338static void s_bss PARAMS ((int));
339static void s_data1 PARAMS ((int));
340static void s_data2 PARAMS ((int));
341static void s_even PARAMS ((int));
342static void s_proc PARAMS ((int));
343static void mri_chip PARAMS ((void));
344static void s_chip PARAMS ((int));
345static void s_fopt PARAMS ((int));
346static void s_opt PARAMS ((int));
347static void s_reg PARAMS ((int));
348static void s_restore PARAMS ((int));
349static void s_save PARAMS ((int));
350static void s_mri_if PARAMS ((int));
351static void s_mri_else PARAMS ((int));
352static void s_mri_endi PARAMS ((int));
353static void s_mri_break PARAMS ((int));
354static void s_mri_next PARAMS ((int));
355static void s_mri_for PARAMS ((int));
356static void s_mri_endf PARAMS ((int));
357static void s_mri_repeat PARAMS ((int));
358static void s_mri_until PARAMS ((int));
359static void s_mri_while PARAMS ((int));
360static void s_mri_endw PARAMS ((int));
252b5132
RH		 361static void md_convert_frag_1 PARAMS ((fragS *));
362
363static int current_architecture;
364
dc84e067
NC		 365struct m68k_cpu
366 {
367 unsigned long arch;
368 const char *name;
369 int alias;
370 };
252b5132 371
dc84e067
NC		 372static const struct m68k_cpu archs[] =
373 {
fd99574b
NC		 374 { m68000, "68000", 0 },
375 { m68010, "68010", 0 },
376 { m68020, "68020", 0 },
377 { m68030, "68030", 0 },
378 { m68040, "68040", 0 },
379 { m68060, "68060", 0 },
380 { cpu32, "cpu32", 0 },
381 { m68881, "68881", 0 },
382 { m68851, "68851", 0 },
383 { mcf5200, "5200", 0 },
384 { mcf5206e, "5206e", 0 },
385 { mcf528x|mcfmac, "528x", 0 },
386 { mcf5307|mcfmac, "5307", 0 },
387 { mcf5407|mcfmac, "5407", 0 },
388 { mcfv4e|mcfemac, "cfv4e", 0 },
dc84e067
NC		 389 /* Aliases (effectively, so far as gas is concerned) for the above
390 cpus. */
fd99574b
NC		 391 { m68020, "68k", 1 },
392 { m68000, "68008", 1 },
393 { m68000, "68302", 1 },
394 { m68000, "68306", 1 },
395 { m68000, "68307", 1 },
396 { m68000, "68322", 1 },
397 { m68000, "68356", 1 },
398 { m68000, "68ec000", 1 },
399 { m68000, "68hc000", 1 },
400 { m68000, "68hc001", 1 },
401 { m68020, "68ec020", 1 },
402 { m68030, "68ec030", 1 },
403 { m68040, "68ec040", 1 },
404 { m68060, "68ec060", 1 },
405 { cpu32, "68330", 1 },
406 { cpu32, "68331", 1 },
407 { cpu32, "68332", 1 },
408 { cpu32, "68333", 1 },
409 { cpu32, "68334", 1 },
410 { cpu32, "68336", 1 },
411 { cpu32, "68340", 1 },
412 { cpu32, "68341", 1 },
413 { cpu32, "68349", 1 },
414 { cpu32, "68360", 1 },
415 { m68881, "68882", 1 },
416 { mcf5200, "5202", 1 },
417 { mcf5200, "5204", 1 },
418 { mcf5200, "5206", 1 },
419 { mcf5407|mcfmac, "cfv4", 1 },
dc84e067 420 };
252b5132
RH		 421
422static const int n_archs = sizeof (archs) / sizeof (archs[0]);
423
151337e8
NC		 424/* This is the assembler relaxation table for m68k. m68k is a rich CISC
425 architecture and we have a lot of relaxation modes. */
252b5132 426
151337e8
NC		 427/* Macros used in the relaxation code. */
428#define TAB(x,y) (((x) << 2) + (y))
429#define TABTYPE(x) ((x) >> 2)
430
431/* Relaxation states. */
432#define BYTE 0
433#define SHORT 1
434#define LONG 2
435#define SZ_UNDEF 3
436
437/* Here are all the relaxation modes we support. First we can relax ordinary
438 branches. On 68020 and higher and on CPU32 all branch instructions take
439 three forms, so on these CPUs all branches always remain as such. When we
440 have to expand to the LONG form on a 68000, though, we substitute an
441 absolute jump instead. This is a direct replacement for unconditional
442 branches and a branch over a jump for conditional branches. However, if the
443 user requires PIC and disables this with --pcrel, we can only relax between
444 BYTE and SHORT forms, punting if that isn't enough. This gives us four
445 different relaxation modes for branches: */
446
36759679
NC		 447#define BRANCHBWL 0 /* Branch byte, word, or long. */
448#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
449#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
450#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 451
452/* We also relax coprocessor branches and DBcc's. All CPUs that support
453 coprocessor branches support them in word and long forms, so we have only
454 one relaxation mode for them. DBcc's are word only on all CPUs. We can
455 relax them to the LONG form with a branch-around sequence. This sequence
456 can use a long branch (if available) or an absolute jump (if acceptable).
457 This gives us two relaxation modes. If long branches are not available and
458 absolute jumps are not acceptable, we don't relax DBcc's. */
459
36759679
NC		 460#define FBRANCH 4 /* Coprocessor branch. */
461#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
462#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 463
464/* That's all for instruction relaxation. However, we also relax PC-relative
465 operands. Specifically, we have three operand relaxation modes. On the
466 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
467 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
468 two. Also PC+displacement+index operands in their simple form (with a non-
469 suppressed index without memory indirection) are supported on all CPUs, but
470 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
471 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
472 form of the PC+displacement+index operand. Finally, some absolute operands
473 can be relaxed down to 16-bit PC-relative. */
474
36759679
NC		 475#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
476#define PCINDEX 8 /* PC + displacement + index. */
477#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 478
479/* Note that calls to frag_var need to specify the maximum expansion
480 needed; this is currently 10 bytes for DBCC. */
481
482/* The fields are:
483 How far Forward this mode will reach:
484 How far Backward this mode will reach:
485 How many bytes this mode will add to the size of the frag
486 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 487
488 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 489relax_typeS md_relax_table[] =
490{
ac62c346
AM		 491 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
492 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
493 { 0, 0, 4, 0 },
494 { 1, 1, 0, 0 },
495
496 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
497 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
498 { 0, 0, 4, 0 },
499 { 1, 1, 0, 0 },
500
501 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
502 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
503 { 0, 0, 6, 0 },
504 { 1, 1, 0, 0 },
505
506 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
507 { 0, 0, 2, 0 },
508 { 1, 1, 0, 0 },
509 { 1, 1, 0, 0 },
510
36759679 511 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 512 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
513 { 0, 0, 4, 0 },
514 { 1, 1, 0, 0 },
515
36759679 516 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 517 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
518 { 0, 0, 10, 0 },
519 { 1, 1, 0, 0 },
520
36759679 521 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 522 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
523 { 0, 0, 10, 0 },
524 { 1, 1, 0, 0 },
525
36759679 526 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 527 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
528 { 0, 0, 6, 0 },
529 { 1, 1, 0, 0 },
530
531 { 125, -130, 0, TAB (PCINDEX, SHORT) },
532 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
533 { 0, 0, 4, 0 },
534 { 1, 1, 0, 0 },
535
36759679 536 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 537 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
538 { 0, 0, 4, 0 },
539 { 1, 1, 0, 0 },
252b5132
RH		 540};
541
542/* These are the machine dependent pseudo-ops. These are included so
543 the assembler can work on the output from the SUN C compiler, which
36759679 544 generates these. */
252b5132
RH		 545
546/* This table describes all the machine specific pseudo-ops the assembler
547 has to support. The fields are:
548 pseudo-op name without dot
549 function to call to execute this pseudo-op
36759679 550 Integer arg to pass to the function. */
252b5132
RH		 551const pseudo_typeS md_pseudo_table[] =
552{
553 {"data1", s_data1, 0},
554 {"data2", s_data2, 0},
555 {"bss", s_bss, 0},
556 {"even", s_even, 0},
557 {"skip", s_space, 0},
558 {"proc", s_proc, 0},
559#if defined (TE_SUN3) || defined (OBJ_ELF)
560 {"align", s_align_bytes, 0},
561#endif
562#ifdef OBJ_ELF
563 {"swbeg", s_ignore, 0},
564#endif
565 {"extend", float_cons, 'x'},
566 {"ldouble", float_cons, 'x'},
567
568 /* The following pseudo-ops are supported for MRI compatibility. */
569 {"chip", s_chip, 0},
570 {"comline", s_space, 1},
571 {"fopt", s_fopt, 0},
572 {"mask2", s_ignore, 0},
573 {"opt", s_opt, 0},
574 {"reg", s_reg, 0},
575 {"restore", s_restore, 0},
576 {"save", s_save, 0},
577
578 {"if", s_mri_if, 0},
579 {"if.b", s_mri_if, 'b'},
580 {"if.w", s_mri_if, 'w'},
581 {"if.l", s_mri_if, 'l'},
582 {"else", s_mri_else, 0},
583 {"else.s", s_mri_else, 's'},
584 {"else.l", s_mri_else, 'l'},
585 {"endi", s_mri_endi, 0},
586 {"break", s_mri_break, 0},
587 {"break.s", s_mri_break, 's'},
588 {"break.l", s_mri_break, 'l'},
589 {"next", s_mri_next, 0},
590 {"next.s", s_mri_next, 's'},
591 {"next.l", s_mri_next, 'l'},
592 {"for", s_mri_for, 0},
593 {"for.b", s_mri_for, 'b'},
594 {"for.w", s_mri_for, 'w'},
595 {"for.l", s_mri_for, 'l'},
596 {"endf", s_mri_endf, 0},
597 {"repeat", s_mri_repeat, 0},
598 {"until", s_mri_until, 0},
599 {"until.b", s_mri_until, 'b'},
600 {"until.w", s_mri_until, 'w'},
601 {"until.l", s_mri_until, 'l'},
602 {"while", s_mri_while, 0},
603 {"while.b", s_mri_while, 'b'},
604 {"while.w", s_mri_while, 'w'},
605 {"while.l", s_mri_while, 'l'},
606 {"endw", s_mri_endw, 0},
607
608 {0, 0, 0}
609};
610
252b5132
RH		 611/* The mote pseudo ops are put into the opcode table, since they
612 don't start with a . they look like opcodes to gas.
613 */
614
615#ifdef M68KCOFF
616extern void obj_coff_section PARAMS ((int));
617#endif
618
5a38dc70 619const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 620{
621
622 {"dcl", cons, 4},
623 {"dc", cons, 2},
624 {"dcw", cons, 2},
625 {"dcb", cons, 1},
626
627 {"dsl", s_space, 4},
628 {"ds", s_space, 2},
629 {"dsw", s_space, 2},
630 {"dsb", s_space, 1},
631
632 {"xdef", s_globl, 0},
633#ifdef OBJ_ELF
634 {"align", s_align_bytes, 0},
635#else
636 {"align", s_align_ptwo, 0},
637#endif
638#ifdef M68KCOFF
639 {"sect", obj_coff_section, 0},
640 {"section", obj_coff_section, 0},
641#endif
642 {0, 0, 0}
643};
644
645#define issbyte(x) ((x)>=-128 && (x)<=127)
646#define isubyte(x) ((x)>=0 && (x)<=255)
647#define issword(x) ((x)>=-32768 && (x)<=32767)
648#define isuword(x) ((x)>=0 && (x)<=65535)
649
650#define isbyte(x) ((x)>= -255 && (x)<=255)
651#define isword(x) ((x)>=-65536 && (x)<=65535)
652#define islong(x) (1)
653
654extern char *input_line_pointer;
655
252b5132
RH		 656static char notend_table[256];
657static char alt_notend_table[256];
658#define notend(s) \
659 (! (notend_table[(unsigned char) *s] \
660 || (*s == ':' \
661 && alt_notend_table[(unsigned char) s[1]])))
662
663#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
664
665#ifdef NO_PCREL_RELOCS
666
667int
668make_pcrel_absolute(fixP, add_number)
669 fixS *fixP;
670 long *add_number;
671{
672 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
673
36759679 674 /* Rewrite the PC relative instructions to absolute address ones.
67c1ffbe 675 these are rumored to be faster, and the apollo linker refuses
36759679
NC		 676 to deal with the PC relative relocations. */
677 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
252b5132 678 {
36759679
NC		 679 if (flag_keep_pcrel)
680 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 681 opcode[0] = 0x4e;
682 opcode[1] = 0xf9;
683 }
36759679 684 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
252b5132 685 {
36759679
NC		 686 if (flag_keep_pcrel)
687 as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
252b5132
RH		 688 opcode[0] = 0x4e;
689 opcode[1] = 0xb9;
690 }
691 else
692 as_fatal (_("Unknown PC relative instruction"));
693 *add_number -= 4;
694 return 0;
695}
696
697#endif /* NO_PCREL_RELOCS */
698
699short
700tc_coff_fix2rtype (fixP)
701 fixS *fixP;
702{
703 if (fixP->fx_tcbit && fixP->fx_size == 4)
704 return R_RELLONG_NEG;
705#ifdef NO_PCREL_RELOCS
706 know (fixP->fx_pcrel == 0);
707 return (fixP->fx_size == 1 ? R_RELBYTE
708 : fixP->fx_size == 2 ? R_DIR16
709 : R_DIR32);
710#else
711 return (fixP->fx_pcrel ?
712 (fixP->fx_size == 1 ? R_PCRBYTE :
713 fixP->fx_size == 2 ? R_PCRWORD :
714 R_PCRLONG) :
715 (fixP->fx_size == 1 ? R_RELBYTE :
716 fixP->fx_size == 2 ? R_RELWORD :
717 R_RELLONG));
718#endif
719}
720
721#endif
722
723#ifdef OBJ_ELF
724
c801568a
AM		 725/* Return zero if the reference to SYMBOL from within the same segment may
726 be relaxed. */
727
728/* On an ELF system, we can't relax an externally visible symbol,
729 because it may be overridden by a shared library. However, if
730 TARGET_OS is "elf", then we presume that we are assembling for an
731 embedded system, in which case we don't have to worry about shared
732 libraries, and we can relax any external sym. */
733
734#define relaxable_symbol(symbol) \
6358301e 735 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 736 || S_IS_WEAK (symbol)))
737
252b5132
RH		 738/* Compute the relocation code for a fixup of SIZE bytes, using pc
739 relative relocation if PCREL is non-zero. PIC says whether a special
740 pic relocation was requested. */
741
742static bfd_reloc_code_real_type get_reloc_code
743 PARAMS ((int, int, enum pic_relocation));
744
745static bfd_reloc_code_real_type
746get_reloc_code (size, pcrel, pic)
747 int size;
748 int pcrel;
749 enum pic_relocation pic;
750{
751 switch (pic)
752 {
753 case pic_got_pcrel:
754 switch (size)
755 {
756 case 1:
757 return BFD_RELOC_8_GOT_PCREL;
758 case 2:
759 return BFD_RELOC_16_GOT_PCREL;
760 case 4:
761 return BFD_RELOC_32_GOT_PCREL;
762 }
763 break;
764
765 case pic_got_off:
766 switch (size)
767 {
768 case 1:
769 return BFD_RELOC_8_GOTOFF;
770 case 2:
771 return BFD_RELOC_16_GOTOFF;
772 case 4:
773 return BFD_RELOC_32_GOTOFF;
774 }
775 break;
776
777 case pic_plt_pcrel:
778 switch (size)
779 {
780 case 1:
781 return BFD_RELOC_8_PLT_PCREL;
782 case 2:
783 return BFD_RELOC_16_PLT_PCREL;
784 case 4:
785 return BFD_RELOC_32_PLT_PCREL;
786 }
787 break;
788
789 case pic_plt_off:
790 switch (size)
791 {
792 case 1:
793 return BFD_RELOC_8_PLTOFF;
794 case 2:
795 return BFD_RELOC_16_PLTOFF;
796 case 4:
797 return BFD_RELOC_32_PLTOFF;
798 }
799 break;
800
801 case pic_none:
802 if (pcrel)
803 {
804 switch (size)
805 {
806 case 1:
807 return BFD_RELOC_8_PCREL;
808 case 2:
809 return BFD_RELOC_16_PCREL;
810 case 4:
811 return BFD_RELOC_32_PCREL;
812 }
813 }
814 else
815 {
816 switch (size)
817 {
818 case 1:
819 return BFD_RELOC_8;
820 case 2:
821 return BFD_RELOC_16;
822 case 4:
823 return BFD_RELOC_32;
824 }
825 }
826 }
827
828 if (pcrel)
829 {
830 if (pic == pic_none)
831 as_bad (_("Can not do %d byte pc-relative relocation"), size);
832 else
833 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
834 }
835 else
836 {
837 if (pic == pic_none)
838 as_bad (_("Can not do %d byte relocation"), size);
839 else
840 as_bad (_("Can not do %d byte pic relocation"), size);
841 }
842
843 return BFD_RELOC_NONE;
844}
845
846/* Here we decide which fixups can be adjusted to make them relative
847 to the beginning of the section instead of the symbol. Basically
848 we need to make sure that the dynamic relocations are done
849 correctly, so in some cases we force the original symbol to be
850 used. */
851int
852tc_m68k_fix_adjustable (fixP)
853 fixS *fixP;
854{
36759679 855 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 856 switch (fixP->fx_r_type)
857 {
858 case BFD_RELOC_8_GOT_PCREL:
859 case BFD_RELOC_16_GOT_PCREL:
860 case BFD_RELOC_32_GOT_PCREL:
861 case BFD_RELOC_8_GOTOFF:
862 case BFD_RELOC_16_GOTOFF:
863 case BFD_RELOC_32_GOTOFF:
864 case BFD_RELOC_8_PLT_PCREL:
865 case BFD_RELOC_16_PLT_PCREL:
866 case BFD_RELOC_32_PLT_PCREL:
867 case BFD_RELOC_8_PLTOFF:
868 case BFD_RELOC_16_PLTOFF:
869 case BFD_RELOC_32_PLTOFF:
870 return 0;
871
872 case BFD_RELOC_VTABLE_INHERIT:
873 case BFD_RELOC_VTABLE_ENTRY:
874 return 0;
875
876 default:
877 return 1;
878 }
879}
880
881#else /* !OBJ_ELF */
882
883#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
884
c801568a
AM		 885#define relaxable_symbol(symbol) 1
886
252b5132
RH		 887#endif /* OBJ_ELF */
888
889#ifdef BFD_ASSEMBLER
890
891arelent *
892tc_gen_reloc (section, fixp)
f1f5ef86 893 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 894 fixS *fixp;
895{
896 arelent *reloc;
897 bfd_reloc_code_real_type code;
898
8ec6253e
NC		 899 /* If the tcbit is set, then this was a fixup of a negative value
900 that was never resolved. We do not have a reloc to handle this,
901 so just return. We assume that other code will have detected this
902 situation and produced a helpful error message, so we just tell the
903 user that the reloc cannot be produced. */
252b5132 904 if (fixp->fx_tcbit)
8ec6253e
NC		 905 {
906 if (fixp->fx_addsy)
b091f402
AM		 907 as_bad_where (fixp->fx_file, fixp->fx_line,
908 _("Unable to produce reloc against symbol '%s'"),
909 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 910 return NULL;
911 }
252b5132
RH		 912
913 if (fixp->fx_r_type != BFD_RELOC_NONE)
914 {
915 code = fixp->fx_r_type;
916
917 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
918 that fixup_segment converted a non-PC relative reloc into a
919 PC relative reloc. In such a case, we need to convert the
920 reloc code. */
921 if (fixp->fx_pcrel)
922 {
923 switch (code)
924 {
925 case BFD_RELOC_8:
926 code = BFD_RELOC_8_PCREL;
927 break;
928 case BFD_RELOC_16:
929 code = BFD_RELOC_16_PCREL;
930 break;
931 case BFD_RELOC_32:
932 code = BFD_RELOC_32_PCREL;
933 break;
934 case BFD_RELOC_8_PCREL:
935 case BFD_RELOC_16_PCREL:
936 case BFD_RELOC_32_PCREL:
937 case BFD_RELOC_8_GOT_PCREL:
938 case BFD_RELOC_16_GOT_PCREL:
939 case BFD_RELOC_32_GOT_PCREL:
940 case BFD_RELOC_8_GOTOFF:
941 case BFD_RELOC_16_GOTOFF:
942 case BFD_RELOC_32_GOTOFF:
943 case BFD_RELOC_8_PLT_PCREL:
944 case BFD_RELOC_16_PLT_PCREL:
945 case BFD_RELOC_32_PLT_PCREL:
946 case BFD_RELOC_8_PLTOFF:
947 case BFD_RELOC_16_PLTOFF:
948 case BFD_RELOC_32_PLTOFF:
949 break;
950 default:
951 as_bad_where (fixp->fx_file, fixp->fx_line,
952 _("Cannot make %s relocation PC relative"),
953 bfd_get_reloc_code_name (code));
954 }
955 }
956 }
957 else
958 {
959#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
960 switch (F (fixp->fx_size, fixp->fx_pcrel))
961 {
962#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
963 MAP (1, 0, BFD_RELOC_8);
964 MAP (2, 0, BFD_RELOC_16);
965 MAP (4, 0, BFD_RELOC_32);
966 MAP (1, 1, BFD_RELOC_8_PCREL);
967 MAP (2, 1, BFD_RELOC_16_PCREL);
968 MAP (4, 1, BFD_RELOC_32_PCREL);
969 default:
970 abort ();
971 }
972 }
973#undef F
974#undef MAP
975
976 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 977 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
978 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 979 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
980#ifndef OBJ_ELF
981 if (fixp->fx_pcrel)
982 reloc->addend = fixp->fx_addnumber;
983 else
984 reloc->addend = 0;
985#else
986 if (!fixp->fx_pcrel)
987 reloc->addend = fixp->fx_addnumber;
988 else
989 reloc->addend = (section->vma
8390138c
AS		 990 /* Explicit sign extension in case char is
991 unsigned. */
992 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 993 + fixp->fx_addnumber
994 + md_pcrel_from (fixp));
995#endif
996
997 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
998 assert (reloc->howto != 0);
999
1000 return reloc;
1001}
1002
1003#endif /* BFD_ASSEMBLER */
1004
252b5132
RH		 1005/* Handle of the OPCODE hash table. NULL means any use before
1006 m68k_ip_begin() will crash. */
1007static struct hash_control *op_hash;
1008\f
1009/* Assemble an m68k instruction. */
1010
1011static void
1012m68k_ip (instring)
1013 char *instring;
1014{
1015 register char *p;
1016 register struct m68k_op *opP;
1017 register const struct m68k_incant *opcode;
1018 register const char *s;
1019 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1020 char *pdot, *pdotmove;
1021 enum m68k_size siz1, siz2;
1022 char c;
1023 int losing;
1024 int opsfound;
1025 LITTLENUM_TYPE words[6];
1026 LITTLENUM_TYPE *wordp;
1027 unsigned long ok_arch = 0;
1028
1029 if (*instring == ' ')
36759679 1030 instring++; /* Skip leading whitespace. */
252b5132
RH		 1031
1032 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1033 or exactly 1 space. */
252b5132
RH		 1034 pdot = 0;
1035 for (p = instring; *p != '\0'; p++)
1036 {
1037 if (*p == ' ')
1038 break;
1039 if (*p == '.')
1040 pdot = p;
1041 }
1042
1043 if (p == instring)
1044 {
1045 the_ins.error = _("No operator");
1046 return;
1047 }
1048
1049 /* p now points to the end of the opcode name, probably whitespace.
1050 Make sure the name is null terminated by clobbering the
1051 whitespace, look it up in the hash table, then fix it back.
1052 Remove a dot, first, since the opcode tables have none. */
1053 if (pdot != NULL)
1054 {
1055 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1056 *pdotmove = pdotmove[1];
1057 p--;
1058 }
1059
1060 c = *p;
1061 *p = '\0';
1062 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1063 *p = c;
1064
1065 if (pdot != NULL)
1066 {
1067 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1068 *pdotmove = pdotmove[-1];
1069 *pdot = '.';
1070 ++p;
1071 }
1072
1073 if (opcode == NULL)
1074 {
1075 the_ins.error = _("Unknown operator");
1076 return;
1077 }
1078
36759679 1079 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1080 while (*p == ' ')
1081 ++p;
1082
1083 if (opcode->m_operands == 0)
1084 {
1085 char *old = input_line_pointer;
1086 *old = '\n';
1087 input_line_pointer = p;
36759679 1088 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1089 mote_pseudo_table[opcode->m_opnum].poc_handler
1090 (mote_pseudo_table[opcode->m_opnum].poc_val);
1091 input_line_pointer = old;
1092 *old = 0;
1093
1094 return;
1095 }
1096
1097 if (flag_mri && opcode->m_opnum == 0)
1098 {
1099 /* In MRI mode, random garbage is allowed after an instruction
1100 which accepts no operands. */
1101 the_ins.args = opcode->m_operands;
1102 the_ins.numargs = opcode->m_opnum;
1103 the_ins.numo = opcode->m_codenum;
1104 the_ins.opcode[0] = getone (opcode);
1105 the_ins.opcode[1] = gettwo (opcode);
1106 return;
1107 }
1108
1109 for (opP = &the_ins.operands[0]; *p; opP++)
1110 {
1111 p = crack_operand (p, opP);
1112
1113 if (opP->error)
1114 {
1115 the_ins.error = opP->error;
1116 return;
1117 }
1118 }
1119
1120 opsfound = opP - &the_ins.operands[0];
1121
1122 /* This ugly hack is to support the floating pt opcodes in their
1123 standard form. Essentially, we fake a first enty of type COP#1 */
1124 if (opcode->m_operands[0] == 'I')
1125 {
1126 int n;
1127
1128 for (n = opsfound; n > 0; --n)
1129 the_ins.operands[n] = the_ins.operands[n - 1];
1130
1131 memset ((char *) (&the_ins.operands[0]), '\0',
1132 sizeof (the_ins.operands[0]));
1133 the_ins.operands[0].mode = CONTROL;
1134 the_ins.operands[0].reg = m68k_float_copnum;
1135 opsfound++;
1136 }
1137
36759679 1138 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1139 for (losing = 0;;)
1140 {
1141 /* If we didn't get the right number of ops, or we have no
92774660 1142 common model with this pattern then reject this pattern. */
252b5132
RH		 1143
1144 ok_arch |= opcode->m_arch;
1145 if (opsfound != opcode->m_opnum
1146 || ((opcode->m_arch & current_architecture) == 0))
1147 ++losing;
1148 else
1149 {
1150 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1151 *s && !losing;
1152 s += 2, opP++)
1153 {
1154 /* Warning: this switch is huge! */
1155 /* I've tried to organize the cases into this order:
1156 non-alpha first, then alpha by letter. Lower-case
1157 goes directly before uppercase counterpart. */
1158 /* Code with multiple case ...: gets sorted by the lowest
1159 case ... it belongs to. I hope this makes sense. */
1160 switch (*s)
1161 {
1162 case '!':
1163 switch (opP->mode)
1164 {
1165 case IMMED:
1166 case DREG:
1167 case AREG:
1168 case FPREG:
1169 case CONTROL:
1170 case AINC:
1171 case ADEC:
1172 case REGLST:
1173 losing++;
1174 break;
1175 default:
1176 break;
1177 }
1178 break;
1179
1180 case '<':
1181 switch (opP->mode)
1182 {
1183 case DREG:
1184 case AREG:
1185 case FPREG:
1186 case CONTROL:
1187 case IMMED:
1188 case ADEC:
1189 case REGLST:
1190 losing++;
1191 break;
1192 default:
1193 break;
1194 }
1195 break;
1196
1197 case '>':
1198 switch (opP->mode)
1199 {
1200 case DREG:
1201 case AREG:
1202 case FPREG:
1203 case CONTROL:
1204 case IMMED:
1205 case AINC:
1206 case REGLST:
1207 losing++;
1208 break;
1209 case ABSL:
1210 break;
1211 default:
1212 if (opP->reg == PC
1213 || opP->reg == ZPC)
1214 losing++;
1215 break;
1216 }
1217 break;
1218
1219 case 'm':
1220 switch (opP->mode)
1221 {
1222 case DREG:
1223 case AREG:
1224 case AINDR:
1225 case AINC:
1226 case ADEC:
1227 break;
1228 default:
1229 losing++;
1230 }
8a104df9 1231 break;
252b5132
RH		 1232
1233 case 'n':
1234 switch (opP->mode)
1235 {
1236 case DISP:
1237 break;
1238 default:
1239 losing++;
1240 }
8a104df9 1241 break;
252b5132
RH		 1242
1243 case 'o':
1244 switch (opP->mode)
1245 {
1246 case BASE:
1247 case ABSL:
1248 case IMMED:
1249 break;
1250 default:
1251 losing++;
1252 }
8a104df9 1253 break;
252b5132
RH		 1254
1255 case 'p':
1256 switch (opP->mode)
1257 {
1258 case DREG:
1259 case AREG:
1260 case AINDR:
1261 case AINC:
1262 case ADEC:
1263 break;
1264 case DISP:
1265 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1266 losing++;
252b5132
RH		 1267 break;
1268 default:
1269 losing++;
1270 }
8a104df9 1271 break;
252b5132
RH		 1272
1273 case 'q':
1274 switch (opP->mode)
1275 {
1276 case DREG:
1277 case AINDR:
1278 case AINC:
1279 case ADEC:
1280 break;
1281 case DISP:
1282 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1283 losing++;
252b5132
RH		 1284 break;
1285 default:
1286 losing++;
1287 break;
1288 }
8a104df9 1289 break;
252b5132
RH		 1290
1291 case 'v':
1292 switch (opP->mode)
1293 {
1294 case DREG:
1295 case AINDR:
1296 case AINC:
1297 case ADEC:
1298 case ABSL:
1299 break;
1300 case DISP:
1301 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1302 losing++;
252b5132
RH		 1303 break;
1304 default:
1305 losing++;
1306 break;
1307 }
1308 break;
1309
1310 case '#':
1311 if (opP->mode != IMMED)
1312 losing++;
1313 else if (s[1] == 'b'
1314 && ! isvar (&opP->disp)
1315 && (opP->disp.exp.X_op != O_constant
1316 || ! isbyte (opP->disp.exp.X_add_number)))
1317 losing++;
1318 else if (s[1] == 'B'
1319 && ! isvar (&opP->disp)
1320 && (opP->disp.exp.X_op != O_constant
1321 || ! issbyte (opP->disp.exp.X_add_number)))
1322 losing++;
1323 else if (s[1] == 'w'
1324 && ! isvar (&opP->disp)
1325 && (opP->disp.exp.X_op != O_constant
1326 || ! isword (opP->disp.exp.X_add_number)))
1327 losing++;
1328 else if (s[1] == 'W'
1329 && ! isvar (&opP->disp)
1330 && (opP->disp.exp.X_op != O_constant
1331 || ! issword (opP->disp.exp.X_add_number)))
1332 losing++;
1333 break;
1334
1335 case '^':
1336 case 'T':
1337 if (opP->mode != IMMED)
1338 losing++;
1339 break;
1340
1341 case '$':
1342 if (opP->mode == AREG
1343 || opP->mode == CONTROL
1344 || opP->mode == FPREG
1345 || opP->mode == IMMED
1346 || opP->mode == REGLST
1347 || (opP->mode != ABSL
1348 && (opP->reg == PC
1349 || opP->reg == ZPC)))
1350 losing++;
1351 break;
1352
1353 case '%':
1354 if (opP->mode == CONTROL
1355 || opP->mode == FPREG
1356 || opP->mode == REGLST
1357 || opP->mode == IMMED
1358 || (opP->mode != ABSL
1359 && (opP->reg == PC
1360 || opP->reg == ZPC)))
1361 losing++;
1362 break;
1363
1364 case '&':
1365 switch (opP->mode)
1366 {
1367 case DREG:
1368 case AREG:
1369 case FPREG:
1370 case CONTROL:
1371 case IMMED:
1372 case AINC:
1373 case ADEC:
1374 case REGLST:
1375 losing++;
1376 break;
1377 case ABSL:
1378 break;
1379 default:
1380 if (opP->reg == PC
1381 || opP->reg == ZPC)
1382 losing++;
1383 break;
1384 }
1385 break;
1386
1387 case '*':
1388 if (opP->mode == CONTROL
1389 || opP->mode == FPREG
1390 || opP->mode == REGLST)
1391 losing++;
1392 break;
1393
1394 case '+':
1395 if (opP->mode != AINC)
1396 losing++;
1397 break;
1398
1399 case '-':
1400 if (opP->mode != ADEC)
1401 losing++;
1402 break;
1403
1404 case '/':
1405 switch (opP->mode)
1406 {
1407 case AREG:
1408 case CONTROL:
1409 case FPREG:
1410 case AINC:
1411 case ADEC:
1412 case IMMED:
1413 case REGLST:
1414 losing++;
1415 break;
1416 default:
1417 break;
1418 }
1419 break;
1420
1421 case ';':
1422 switch (opP->mode)
1423 {
1424 case AREG:
1425 case CONTROL:
1426 case FPREG:
1427 case REGLST:
1428 losing++;
1429 break;
1430 default:
1431 break;
1432 }
1433 break;
1434
1435 case '?':
1436 switch (opP->mode)
1437 {
1438 case AREG:
1439 case CONTROL:
1440 case FPREG:
1441 case AINC:
1442 case ADEC:
1443 case IMMED:
1444 case REGLST:
1445 losing++;
1446 break;
1447 case ABSL:
1448 break;
1449 default:
1450 if (opP->reg == PC || opP->reg == ZPC)
1451 losing++;
1452 break;
1453 }
1454 break;
1455
1456 case '@':
1457 switch (opP->mode)
1458 {
1459 case AREG:
1460 case CONTROL:
1461 case FPREG:
1462 case IMMED:
1463 case REGLST:
1464 losing++;
1465 break;
1466 default:
1467 break;
1468 }
1469 break;
1470
1471 case '~': /* For now! (JF FOO is this right?) */
1472 switch (opP->mode)
1473 {
1474 case DREG:
1475 case AREG:
1476 case CONTROL:
1477 case FPREG:
1478 case IMMED:
1479 case REGLST:
1480 losing++;
1481 break;
1482 case ABSL:
1483 break;
1484 default:
1485 if (opP->reg == PC
1486 || opP->reg == ZPC)
1487 losing++;
1488 break;
1489 }
1490 break;
1491
1492 case '3':
1493 if (opP->mode != CONTROL
1494 || (opP->reg != TT0 && opP->reg != TT1))
1495 losing++;
1496 break;
1497
1498 case 'A':
1499 if (opP->mode != AREG)
1500 losing++;
1501 break;
1502
1503 case 'a':
1504 if (opP->mode != AINDR)
1505 ++losing;
1506 break;
1507
fd99574b
NC		 1508 case '4':
1509 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1510 && (opP->mode != DISP
1511 || opP->reg < ADDR0
1512 || opP->reg > ADDR7))
1513 ++losing;
1514 break;
1515
252b5132
RH		 1516 case 'B': /* FOO */
1517 if (opP->mode != ABSL
1518 || (flag_long_jumps
1519 && strncmp (instring, "jbsr", 4) == 0))
1520 losing++;
1521 break;
1522
3e602632
NC		 1523 case 'b':
1524 switch (opP->mode)
1525 {
1526 case IMMED:
1527 case ABSL:
1528 case AREG:
1529 case FPREG:
1530 case CONTROL:
1531 case POST:
1532 case PRE:
1533 case REGLST:
1534 losing++;
1535 break;
1536 default:
1537 break;
1538 }
1539 break;
1540
252b5132
RH		 1541 case 'C':
1542 if (opP->mode != CONTROL || opP->reg != CCR)
1543 losing++;
1544 break;
1545
1546 case 'd':
1547 if (opP->mode != DISP
1548 || opP->reg < ADDR0
1549 || opP->reg > ADDR7)
1550 losing++;
1551 break;
1552
1553 case 'D':
1554 if (opP->mode != DREG)
1555 losing++;
1556 break;
1557
6da466c7
ILT		 1558 case 'E':
1559 if (opP->reg != ACC)
1560 losing++;
1561 break;
1562
fd99574b
NC		 1563 case 'e':
1564 if (opP->reg != ACC && opP->reg != ACC1
1565 && opP->reg != ACC2 && opP->reg != ACC3)
1566 losing++;
1567 break;
1568
252b5132
RH		 1569 case 'F':
1570 if (opP->mode != FPREG)
1571 losing++;
1572 break;
1573
6da466c7
ILT		 1574 case 'G':
1575 if (opP->reg != MACSR)
1576 losing++;
1577 break;
1578
fd99574b
NC		 1579 case 'g':
1580 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1581 losing++;
1582 break;
1583
6da466c7
ILT		 1584 case 'H':
1585 if (opP->reg != MASK)
1586 losing++;
1587 break;
1588
252b5132
RH		 1589 case 'I':
1590 if (opP->mode != CONTROL
1591 || opP->reg < COP0
1592 || opP->reg > COP7)
1593 losing++;
1594 break;
1595
fd99574b
NC		 1596 case 'i':
1597 if (opP->mode != LSH && opP->mode != RSH)
1598 losing++;
1599 break;
1600
252b5132
RH		 1601 case 'J':
1602 if (opP->mode != CONTROL
1603 || opP->reg < USP
1604 || opP->reg > last_movec_reg)
1605 losing++;
1606 else
1607 {
1608 const enum m68k_register *rp;
1609 for (rp = control_regs; *rp; rp++)
1610 if (*rp == opP->reg)
1611 break;
1612 if (*rp == 0)
1613 losing++;
1614 }
1615 break;
1616
1617 case 'k':
1618 if (opP->mode != IMMED)
1619 losing++;
1620 break;
1621
1622 case 'l':
1623 case 'L':
1624 if (opP->mode == DREG
1625 || opP->mode == AREG
1626 || opP->mode == FPREG)
1627 {
1628 if (s[1] == '8')
1629 losing++;
1630 else
1631 {
1632 switch (opP->mode)
1633 {
1634 case DREG:
1635 opP->mask = 1 << (opP->reg - DATA0);
1636 break;
1637 case AREG:
1638 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1639 break;
1640 case FPREG:
1641 opP->mask = 1 << (opP->reg - FP0 + 16);
1642 break;
1643 default:
1644 abort ();
1645 }
1646 opP->mode = REGLST;
1647 }
1648 }
1649 else if (opP->mode == CONTROL)
1650 {
1651 if (s[1] != '8')
1652 losing++;
1653 else
1654 {
1655 switch (opP->reg)
1656 {
1657 case FPI:
1658 opP->mask = 1 << 24;
1659 break;
1660 case FPS:
1661 opP->mask = 1 << 25;
1662 break;
1663 case FPC:
1664 opP->mask = 1 << 26;
1665 break;
1666 default:
1667 losing++;
1668 break;
1669 }
1670 opP->mode = REGLST;
1671 }
1672 }
1673 else if (opP->mode != REGLST)
1674 losing++;
1675 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1676 losing++;
1677 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1678 losing++;
1679 break;
1680
1681 case 'M':
1682 if (opP->mode != IMMED)
1683 losing++;
1684 else if (opP->disp.exp.X_op != O_constant
1685 || ! issbyte (opP->disp.exp.X_add_number))
1686 losing++;
1687 else if (! m68k_quick
1688 && instring[3] != 'q'
1689 && instring[4] != 'q')
1690 losing++;
1691 break;
1692
1693 case 'O':
1694 if (opP->mode != DREG
1695 && opP->mode != IMMED
1696 && opP->mode != ABSL)
1697 losing++;
1698 break;
1699
1700 case 'Q':
1701 if (opP->mode != IMMED)
1702 losing++;
1703 else if (opP->disp.exp.X_op != O_constant
1704 || opP->disp.exp.X_add_number < 1
1705 || opP->disp.exp.X_add_number > 8)
1706 losing++;
1707 else if (! m68k_quick
1708 && (strncmp (instring, "add", 3) == 0
1709 || strncmp (instring, "sub", 3) == 0)
1710 && instring[3] != 'q')
1711 losing++;
1712 break;
1713
1714 case 'R':
1715 if (opP->mode != DREG && opP->mode != AREG)
1716 losing++;
1717 break;
1718
1719 case 'r':
1720 if (opP->mode != AINDR
1721 && (opP->mode != BASE
1722 || (opP->reg != 0
1723 && opP->reg != ZADDR0)
1724 || opP->disp.exp.X_op != O_absent
1725 || ((opP->index.reg < DATA0
1726 || opP->index.reg > DATA7)
1727 && (opP->index.reg < ADDR0
1728 || opP->index.reg > ADDR7))
1729 || opP->index.size != SIZE_UNSPEC
1730 || opP->index.scale != 1))
1731 losing++;
1732 break;
1733
1734 case 's':
1735 if (opP->mode != CONTROL
1736 || ! (opP->reg == FPI
1737 || opP->reg == FPS
1738 || opP->reg == FPC))
1739 losing++;
1740 break;
1741
1742 case 'S':
1743 if (opP->mode != CONTROL || opP->reg != SR)
1744 losing++;
1745 break;
1746
1747 case 't':
1748 if (opP->mode != IMMED)
1749 losing++;
1750 else if (opP->disp.exp.X_op != O_constant
1751 || opP->disp.exp.X_add_number < 0
1752 || opP->disp.exp.X_add_number > 7)
1753 losing++;
1754 break;
1755
1756 case 'U':
1757 if (opP->mode != CONTROL || opP->reg != USP)
1758 losing++;
1759 break;
1760
3e602632
NC		 1761 case 'x':
1762 if (opP->mode != IMMED)
1763 losing++;
1764 else if (opP->disp.exp.X_op != O_constant
1765 || opP->disp.exp.X_add_number < -1
1766 || opP->disp.exp.X_add_number > 7
1767 || opP->disp.exp.X_add_number == 0)
1768 losing++;
1769 break;
1770
252b5132
RH		 1771 /* JF these are out of order. We could put them
1772 in order if we were willing to put up with
1773 bunches of #ifdef m68851s in the code.
1774
1775 Don't forget that you need these operands
1776 to use 68030 MMU instructions. */
1777#ifndef NO_68851
36759679 1778 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1779 case '|':
1780 if (opP->mode == CONTROL
1781 || opP->mode == FPREG
1782 || opP->mode == DREG
1783 || opP->mode == AREG
1784 || opP->mode == REGLST)
1785 losing++;
1786 /* We should accept immediate operands, but they
1787 supposedly have to be quad word, and we don't
1788 handle that. I would like to see what a Motorola
1789 assembler does before doing something here. */
1790 if (opP->mode == IMMED)
1791 losing++;
1792 break;
1793
1794 case 'f':
1795 if (opP->mode != CONTROL
1796 || (opP->reg != SFC && opP->reg != DFC))
1797 losing++;
1798 break;
1799
1800 case '0':
1801 if (opP->mode != CONTROL || opP->reg != TC)
1802 losing++;
1803 break;
1804
1805 case '1':
1806 if (opP->mode != CONTROL || opP->reg != AC)
1807 losing++;
1808 break;
1809
1810 case '2':
1811 if (opP->mode != CONTROL
1812 || (opP->reg != CAL
1813 && opP->reg != VAL
1814 && opP->reg != SCC))
1815 losing++;
1816 break;
1817
1818 case 'V':
1819 if (opP->mode != CONTROL
1820 || opP->reg != VAL)
1821 losing++;
1822 break;
1823
1824 case 'W':
1825 if (opP->mode != CONTROL
1826 || (opP->reg != DRP
1827 && opP->reg != SRP
1828 && opP->reg != CRP))
1829 losing++;
1830 break;
1831
3e602632
NC		 1832 case 'w':
1833 switch (opP->mode)
1834 {
1835 case IMMED:
1836 case ABSL:
1837 case AREG:
1838 case DREG:
1839 case FPREG:
1840 case CONTROL:
1841 case POST:
1842 case PRE:
1843 case REGLST:
1844 losing++;
1845 break;
1846 default:
1847 break;
1848 }
1849 break;
1850
252b5132
RH		 1851 case 'X':
1852 if (opP->mode != CONTROL
1853 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1854 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1855 losing++;
1856 break;
1857
1858 case 'Y':
1859 if (opP->mode != CONTROL || opP->reg != PSR)
1860 losing++;
1861 break;
1862
1863 case 'Z':
1864 if (opP->mode != CONTROL || opP->reg != PCSR)
1865 losing++;
1866 break;
1867#endif
1868 case 'c':
1869 if (opP->mode != CONTROL
1870 || (opP->reg != NC
1871 && opP->reg != IC
1872 && opP->reg != DC
1873 && opP->reg != BC))
36759679 1874 losing++;
252b5132
RH		 1875 break;
1876
1877 case '_':
1878 if (opP->mode != ABSL)
1879 ++losing;
1880 break;
1881
6da466c7
ILT		 1882 case 'u':
1883 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1884 losing++;
1885 /* FIXME: kludge instead of fixing parser:
1886 upper/lower registers are *not* CONTROL
92774660 1887 registers, but ordinary ones. */
6da466c7
ILT		 1888 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1889 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1890 opP->mode = DREG;
1891 else
1892 opP->mode = AREG;
1893 break;
1894
3e602632
NC		 1895 case 'y':
1896 if (!(opP->mode == AINDR
1897 || (opP->mode == DISP && !(opP->reg == PC ||
1898 opP->reg == ZPC))))
1899 losing++;
1900 break;
1901
1902 case 'z':
1903 if (!(opP->mode == AINDR || opP->mode == DISP))
1904 losing++;
1905 break;
1906
252b5132
RH		 1907 default:
1908 abort ();
36759679 1909 }
252b5132
RH		 1910
1911 if (losing)
1912 break;
36759679
NC		 1913 }
1914 }
252b5132
RH		 1915
1916 if (!losing)
36759679 1917 break;
252b5132
RH		 1918
1919 opcode = opcode->m_next;
1920
1921 if (!opcode)
1922 {
1923 if (ok_arch
1924 && !(ok_arch & current_architecture))
1925 {
1926 char buf[200], *cp;
1927
1928 strcpy (buf,
1929 _("invalid instruction for this architecture; needs "));
1930 cp = buf + strlen (buf);
1931 switch (ok_arch)
1932 {
3e602632
NC		 1933 case cfloat:
1934 strcpy (cp, _("ColdFire fpu (cfv4e)"));
1935 break;
252b5132
RH		 1936 case mfloat:
1937 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1938 break;
1939 case mmmu:
1940 strcpy (cp, _("mmu (68030 or 68851)"));
1941 break;
1942 case m68020up:
1943 strcpy (cp, _("68020 or higher"));
1944 break;
1945 case m68000up:
1946 strcpy (cp, _("68000 or higher"));
1947 break;
1948 case m68010up:
1949 strcpy (cp, _("68010 or higher"));
1950 break;
1951 default:
1952 {
1953 int got_one = 0, idx;
8fce3f5e
AM		 1954 for (idx = 0;
1955 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1956 idx++)
1957 {
1958 if ((archs[idx].arch & ok_arch)
1959 && ! archs[idx].alias)
1960 {
1961 if (got_one)
1962 {
1963 strcpy (cp, " or ");
1964 cp += strlen (cp);
1965 }
1966 got_one = 1;
1967 strcpy (cp, archs[idx].name);
1968 cp += strlen (cp);
1969 }
1970 }
1971 }
1972 }
1973 cp = xmalloc (strlen (buf) + 1);
1974 strcpy (cp, buf);
1975 the_ins.error = cp;
1976 }
1977 else
1978 the_ins.error = _("operands mismatch");
1979 return;
36759679 1980 }
252b5132
RH		 1981
1982 losing = 0;
1983 }
1984
36759679 1985 /* Now assemble it. */
252b5132
RH		 1986 the_ins.args = opcode->m_operands;
1987 the_ins.numargs = opcode->m_opnum;
1988 the_ins.numo = opcode->m_codenum;
1989 the_ins.opcode[0] = getone (opcode);
1990 the_ins.opcode[1] = gettwo (opcode);
1991
1992 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1993 {
1994 /* This switch is a doozy.
1995 Watch the first step; its a big one! */
1996 switch (s[0])
1997 {
1998
1999 case '*':
2000 case '~':
2001 case '%':
2002 case ';':
2003 case '@':
2004 case '!':
2005 case '&':
2006 case '$':
2007 case '?':
2008 case '/':
2009 case '<':
2010 case '>':
3e602632 2011 case 'b':
252b5132
RH		 2012 case 'm':
2013 case 'n':
2014 case 'o':
2015 case 'p':
2016 case 'q':
2017 case 'v':
3e602632
NC		 2018 case 'w':
2019 case 'y':
2020 case 'z':
fd99574b 2021 case '4':
252b5132
RH		 2022#ifndef NO_68851
2023 case '|':
2024#endif
2025 switch (opP->mode)
2026 {
2027 case IMMED:
2028 tmpreg = 0x3c; /* 7.4 */
2029 if (strchr ("bwl", s[1]))
3e602632 2030 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2031 else
2032 nextword = get_num (&opP->disp, 0);
2033 if (isvar (&opP->disp))
2034 add_fix (s[1], &opP->disp, 0, 0);
2035 switch (s[1])
2036 {
2037 case 'b':
2038 if (!isbyte (nextword))
2039 opP->error = _("operand out of range");
2040 addword (nextword);
2041 baseo = 0;
2042 break;
2043 case 'w':
2044 if (!isword (nextword))
2045 opP->error = _("operand out of range");
2046 addword (nextword);
2047 baseo = 0;
2048 break;
2049 case 'W':
2050 if (!issword (nextword))
2051 opP->error = _("operand out of range");
2052 addword (nextword);
2053 baseo = 0;
2054 break;
2055 case 'l':
2056 addword (nextword >> 16);
2057 addword (nextword);
2058 baseo = 0;
2059 break;
2060
2061 case 'f':
2062 baseo = 2;
2063 outro = 8;
2064 break;
2065 case 'F':
2066 baseo = 4;
2067 outro = 11;
2068 break;
2069 case 'x':
2070 baseo = 6;
2071 outro = 15;
2072 break;
2073 case 'p':
2074 baseo = 6;
2075 outro = -1;
2076 break;
2077 default:
2078 abort ();
2079 }
2080 if (!baseo)
2081 break;
2082
36759679 2083 /* We gotta put out some float. */
252b5132
RH		 2084 if (op (&opP->disp) != O_big)
2085 {
2086 valueT val;
2087 int gencnt;
2088
2089 /* Can other cases happen here? */
2090 if (op (&opP->disp) != O_constant)
2091 abort ();
2092
2093 val = (valueT) offs (&opP->disp);
2094 gencnt = 0;
2095 do
2096 {
2097 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2098 val >>= LITTLENUM_NUMBER_OF_BITS;
2099 ++gencnt;
2100 }
2101 while (val != 0);
2102 offs (&opP->disp) = gencnt;
2103 }
2104 if (offs (&opP->disp) > 0)
2105 {
2106 if (offs (&opP->disp) > baseo)
2107 {
2108 as_warn (_("Bignum too big for %c format; truncated"),
2109 s[1]);
2110 offs (&opP->disp) = baseo;
2111 }
2112 baseo -= offs (&opP->disp);
2113 while (baseo--)
2114 addword (0);
2115 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2116 offs (&opP->disp)--;
2117 --wordp)
2118 addword (*wordp);
2119 break;
2120 }
2121 gen_to_words (words, baseo, (long) outro);
2122 for (wordp = words; baseo--; wordp++)
2123 addword (*wordp);
2124 break;
2125 case DREG:
2126 tmpreg = opP->reg - DATA; /* 0.dreg */
2127 break;
2128 case AREG:
2129 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2130 break;
2131 case AINDR:
2132 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2133 break;
2134 case ADEC:
2135 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2136 break;
2137 case AINC:
2138 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2139 break;
2140 case DISP:
2141
3e602632 2142 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2143
2144 if (opP->reg == PC
2145 && ! isvar (&opP->disp)
2146 && m68k_abspcadd)
2147 {
2148 opP->disp.exp.X_op = O_symbol;
2149#ifndef BFD_ASSEMBLER
2150 opP->disp.exp.X_add_symbol = &abs_symbol;
2151#else
2152 opP->disp.exp.X_add_symbol =
2153 section_symbol (absolute_section);
2154#endif
2155 }
2156
36759679 2157 /* Force into index mode. Hope this works. */
252b5132
RH		 2158
2159 /* We do the first bit for 32-bit displacements, and the
2160 second bit for 16 bit ones. It is possible that we
2161 should make the default be WORD instead of LONG, but
2162 I think that'd break GCC, so we put up with a little
2163 inefficiency for the sake of working output. */
2164
2165 if (!issword (nextword)
2166 || (isvar (&opP->disp)
2167 && ((opP->disp.size == SIZE_UNSPEC
2168 && flag_short_refs == 0
2169 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2170 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2171 || opP->disp.size == SIZE_LONG)))
2172 {
2173 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2174 || arch_coldfire_p (current_architecture))
252b5132
RH		 2175 opP->error =
2176 _("displacement too large for this architecture; needs 68020 or higher");
2177 if (opP->reg == PC)
2178 tmpreg = 0x3B; /* 7.3 */
2179 else
2180 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2181 if (isvar (&opP->disp))
2182 {
2183 if (opP->reg == PC)
2184 {
2185 if (opP->disp.size == SIZE_LONG
2186#ifdef OBJ_ELF
2187 /* If the displacement needs pic
2188 relocation it cannot be relaxed. */
2189 || opP->disp.pic_reloc != pic_none
2190#endif
2191 )
2192 {
2193 addword (0x0170);
2194 add_fix ('l', &opP->disp, 1, 2);
2195 }
2196 else
2197 {
2198 add_frag (adds (&opP->disp),
2199 offs (&opP->disp),
151337e8 2200 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2201 break;
2202 }
2203 }
2204 else
2205 {
2206 addword (0x0170);
2207 add_fix ('l', &opP->disp, 0, 0);
2208 }
2209 }
2210 else
2211 addword (0x0170);
2212 addword (nextword >> 16);
2213 }
2214 else
2215 {
2216 if (opP->reg == PC)
2217 tmpreg = 0x3A; /* 7.2 */
2218 else
2219 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2220
2221 if (isvar (&opP->disp))
2222 {
2223 if (opP->reg == PC)
2224 {
2225 add_fix ('w', &opP->disp, 1, 0);
2226 }
2227 else
2228 add_fix ('w', &opP->disp, 0, 0);
2229 }
2230 }
2231 addword (nextword);
2232 break;
2233
2234 case POST:
2235 case PRE:
2236 case BASE:
2237 nextword = 0;
3e602632 2238 baseo = get_num (&opP->disp, 90);
252b5132 2239 if (opP->mode == POST || opP->mode == PRE)
3e602632 2240 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2241 /* Figure out the `addressing mode'.
2242 Also turn on the BASE_DISABLE bit, if needed. */
2243 if (opP->reg == PC || opP->reg == ZPC)
2244 {
2245 tmpreg = 0x3b; /* 7.3 */
2246 if (opP->reg == ZPC)
2247 nextword |= 0x80;
2248 }
2249 else if (opP->reg == 0)
2250 {
2251 nextword |= 0x80;
2252 tmpreg = 0x30; /* 6.garbage */
2253 }
2254 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2255 {
2256 nextword |= 0x80;
2257 tmpreg = 0x30 + opP->reg - ZADDR0;
2258 }
2259 else
2260 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2261
2262 siz1 = opP->disp.size;
2263 if (opP->mode == POST || opP->mode == PRE)
2264 siz2 = opP->odisp.size;
2265 else
2266 siz2 = SIZE_UNSPEC;
2267
36759679 2268 /* Index register stuff. */
252b5132
RH		 2269 if (opP->index.reg != 0
2270 && opP->index.reg >= DATA
2271 && opP->index.reg <= ADDR7)
2272 {
2273 nextword |= (opP->index.reg - DATA) << 12;
2274
2275 if (opP->index.size == SIZE_LONG
2276 || (opP->index.size == SIZE_UNSPEC
2277 && m68k_index_width_default == SIZE_LONG))
2278 nextword |= 0x800;
2279
92774660 2280 if ((opP->index.scale != 1
252b5132 2281 && cpu_of_arch (current_architecture) < m68020)
92774660 2282 || (opP->index.scale == 8
3e602632
NC		 2283 && (arch_coldfire_p (current_architecture)
2284 && !arch_coldfire_v4e_p(current_architecture))))
252b5132
RH		 2285 {
2286 opP->error =
2287 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2288 }
2289
6da466c7
ILT		 2290 if (arch_coldfire_p (current_architecture)
2291 && opP->index.size == SIZE_WORD)
2292 opP->error = _("invalid index size for coldfire");
2293
252b5132
RH		 2294 switch (opP->index.scale)
2295 {
2296 case 1:
2297 break;
2298 case 2:
2299 nextword |= 0x200;
2300 break;
2301 case 4:
2302 nextword |= 0x400;
2303 break;
2304 case 8:
2305 nextword |= 0x600;
2306 break;
2307 default:
2308 abort ();
2309 }
2310 /* IF its simple,
2311 GET US OUT OF HERE! */
2312
2313 /* Must be INDEX, with an index register. Address
2314 register cannot be ZERO-PC, and either :b was
2315 forced, or we know it will fit. For a 68000 or
2316 68010, force this mode anyways, because the
2317 larger modes aren't supported. */
2318 if (opP->mode == BASE
2319 && ((opP->reg >= ADDR0
2320 && opP->reg <= ADDR7)
2321 || opP->reg == PC))
2322 {
2323 if (siz1 == SIZE_BYTE
2324 || cpu_of_arch (current_architecture) < m68020
6da466c7 2325 || arch_coldfire_p (current_architecture)
252b5132
RH		 2326 || (siz1 == SIZE_UNSPEC
2327 && ! isvar (&opP->disp)
2328 && issbyte (baseo)))
2329 {
2330 nextword += baseo & 0xff;
2331 addword (nextword);
2332 if (isvar (&opP->disp))
2333 {
2334 /* Do a byte relocation. If it doesn't
2335 fit (possible on m68000) let the
2336 fixup processing complain later. */
2337 if (opP->reg == PC)
2338 add_fix ('B', &opP->disp, 1, 1);
2339 else
2340 add_fix ('B', &opP->disp, 0, 0);
2341 }
2342 else if (siz1 != SIZE_BYTE)
2343 {
2344 if (siz1 != SIZE_UNSPEC)
2345 as_warn (_("Forcing byte displacement"));
2346 if (! issbyte (baseo))
2347 opP->error = _("byte displacement out of range");
2348 }
2349
2350 break;
2351 }
2352 else if (siz1 == SIZE_UNSPEC
2353 && opP->reg == PC
2354 && isvar (&opP->disp)
2355 && subs (&opP->disp) == NULL
2356#ifdef OBJ_ELF
2357 /* If the displacement needs pic
2358 relocation it cannot be relaxed. */
2359 && opP->disp.pic_reloc == pic_none
2360#endif
2361 )
2362 {
2363 /* The code in md_convert_frag_1 needs to be
2364 able to adjust nextword. Call frag_grow
2365 to ensure that we have enough space in
2366 the frag obstack to make all the bytes
2367 contiguous. */
2368 frag_grow (14);
8a104df9
KH		 2369 nextword += baseo & 0xff;
2370 addword (nextword);
2371 add_frag (adds (&opP->disp), offs (&opP->disp),
2372 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2373
2374 break;
8a104df9 2375 }
252b5132
RH		 2376 }
2377 }
2378 else
2379 {
36759679 2380 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2381 if (opP->index.reg >= ZDATA0
2382 && opP->index.reg <= ZDATA7)
2383 nextword |= (opP->index.reg - ZDATA0) << 12;
2384 else if (opP->index.reg >= ZADDR0
2385 || opP->index.reg <= ZADDR7)
2386 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2387 }
2388
2389 /* It isn't simple. */
2390
2391 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2392 || arch_coldfire_p (current_architecture))
252b5132
RH		 2393 opP->error =
2394 _("invalid operand mode for this architecture; needs 68020 or higher");
2395
2396 nextword |= 0x100;
2397 /* If the guy specified a width, we assume that it is
2398 wide enough. Maybe it isn't. If so, we lose. */
2399 switch (siz1)
2400 {
2401 case SIZE_UNSPEC:
2402 if (isvar (&opP->disp)
2403 ? m68k_rel32
2404 : ! issword (baseo))
2405 {
2406 siz1 = SIZE_LONG;
2407 nextword |= 0x30;
2408 }
2409 else if (! isvar (&opP->disp) && baseo == 0)
2410 nextword |= 0x10;
2411 else
2412 {
2413 nextword |= 0x20;
2414 siz1 = SIZE_WORD;
2415 }
2416 break;
2417 case SIZE_BYTE:
2418 as_warn (_(":b not permitted; defaulting to :w"));
2419 /* Fall through. */
2420 case SIZE_WORD:
2421 nextword |= 0x20;
2422 break;
2423 case SIZE_LONG:
2424 nextword |= 0x30;
2425 break;
2426 }
2427
67c1ffbe 2428 /* Figure out inner displacement stuff. */
252b5132
RH		 2429 if (opP->mode == POST || opP->mode == PRE)
2430 {
2431 if (cpu_of_arch (current_architecture) & cpu32)
2432 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2433 switch (siz2)
2434 {
2435 case SIZE_UNSPEC:
2436 if (isvar (&opP->odisp)
2437 ? m68k_rel32
2438 : ! issword (outro))
2439 {
2440 siz2 = SIZE_LONG;
2441 nextword |= 0x3;
2442 }
2443 else if (! isvar (&opP->odisp) && outro == 0)
2444 nextword |= 0x1;
2445 else
2446 {
2447 nextword |= 0x2;
2448 siz2 = SIZE_WORD;
2449 }
2450 break;
2451 case 1:
2452 as_warn (_(":b not permitted; defaulting to :w"));
2453 /* Fall through. */
2454 case 2:
2455 nextword |= 0x2;
2456 break;
2457 case 3:
2458 nextword |= 0x3;
2459 break;
2460 }
2461 if (opP->mode == POST
2462 && (nextword & 0x40) == 0)
2463 nextword |= 0x04;
2464 }
2465 addword (nextword);
2466
2467 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2468 {
2469 if (opP->reg == PC || opP->reg == ZPC)
2470 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2471 else
2472 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2473 }
2474 if (siz1 == SIZE_LONG)
2475 addword (baseo >> 16);
2476 if (siz1 != SIZE_UNSPEC)
2477 addword (baseo);
2478
2479 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2480 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2481 if (siz2 == SIZE_LONG)
2482 addword (outro >> 16);
2483 if (siz2 != SIZE_UNSPEC)
2484 addword (outro);
2485
2486 break;
2487
2488 case ABSL:
3e602632 2489 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2490 switch (opP->disp.size)
2491 {
2492 default:
2493 abort ();
2494 case SIZE_UNSPEC:
2495 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2496 {
2497 tmpreg = 0x38; /* 7.0 */
2498 addword (nextword);
2499 break;
2500 }
252b5132
RH		 2501 if (isvar (&opP->disp)
2502 && !subs (&opP->disp)
2503 && adds (&opP->disp)
2504#ifdef OBJ_ELF
2505 /* If the displacement needs pic relocation it
2506 cannot be relaxed. */
2507 && opP->disp.pic_reloc == pic_none
2508#endif
252b5132
RH		 2509 && !flag_long_jumps
2510 && !strchr ("~%&$?", s[0]))
2511 {
2512 tmpreg = 0x3A; /* 7.2 */
2513 add_frag (adds (&opP->disp),
2514 offs (&opP->disp),
151337e8 2515 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2516 break;
2517 }
36759679 2518 /* Fall through into long. */
252b5132
RH		 2519 case SIZE_LONG:
2520 if (isvar (&opP->disp))
2521 add_fix ('l', &opP->disp, 0, 0);
2522
2523 tmpreg = 0x39;/* 7.1 mode */
2524 addword (nextword >> 16);
2525 addword (nextword);
2526 break;
2527
2528 case SIZE_BYTE:
2529 as_bad (_("unsupported byte value; use a different suffix"));
2530 /* Fall through. */
36759679
NC		 2531
2532 case SIZE_WORD:
252b5132
RH		 2533 if (isvar (&opP->disp))
2534 add_fix ('w', &opP->disp, 0, 0);
2535
2536 tmpreg = 0x38;/* 7.0 mode */
2537 addword (nextword);
2538 break;
2539 }
2540 break;
2541 case CONTROL:
2542 case FPREG:
2543 default:
2544 as_bad (_("unknown/incorrect operand"));
bc805888 2545 /* abort (); */
252b5132 2546 }
fd99574b
NC		 2547
2548 /* If s[0] is '4', then this is for the mac instructions
2549 that can have a trailing_ampersand set. If so, set 0x100
2550 bit on tmpreg so install_gen_operand can check for it and
2551 set the appropriate bit (word2, bit 5). */
2552 if (s[0] == '4')
2553 {
2554 if (opP->trailing_ampersand)
2555 tmpreg |= 0x100;
2556 }
252b5132
RH		 2557 install_gen_operand (s[1], tmpreg);
2558 break;
2559
2560 case '#':
2561 case '^':
2562 switch (s[1])
2563 { /* JF: I hate floating point! */
2564 case 'j':
2565 tmpreg = 70;
2566 break;
2567 case '8':
2568 tmpreg = 20;
2569 break;
2570 case 'C':
2571 tmpreg = 50;
2572 break;
2573 case '3':
2574 default:
3e602632 2575 tmpreg = 90;
252b5132
RH		 2576 break;
2577 }
2578 tmpreg = get_num (&opP->disp, tmpreg);
2579 if (isvar (&opP->disp))
2580 add_fix (s[1], &opP->disp, 0, 0);
2581 switch (s[1])
2582 {
2583 case 'b': /* Danger: These do no check for
2584 certain types of overflow.
2585 user beware! */
2586 if (!isbyte (tmpreg))
2587 opP->error = _("out of range");
2588 insop (tmpreg, opcode);
2589 if (isvar (&opP->disp))
2590 the_ins.reloc[the_ins.nrel - 1].n =
2591 (opcode->m_codenum) * 2 + 1;
2592 break;
2593 case 'B':
2594 if (!issbyte (tmpreg))
2595 opP->error = _("out of range");
2596 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2597 if (isvar (&opP->disp))
2598 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2599 break;
2600 case 'w':
2601 if (!isword (tmpreg))
2602 opP->error = _("out of range");
2603 insop (tmpreg, opcode);
2604 if (isvar (&opP->disp))
2605 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2606 break;
2607 case 'W':
2608 if (!issword (tmpreg))
2609 opP->error = _("out of range");
2610 insop (tmpreg, opcode);
2611 if (isvar (&opP->disp))
2612 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2613 break;
2614 case 'l':
2615 /* Because of the way insop works, we put these two out
2616 backwards. */
2617 insop (tmpreg, opcode);
2618 insop (tmpreg >> 16, opcode);
2619 if (isvar (&opP->disp))
2620 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2621 break;
2622 case '3':
2623 tmpreg &= 0xFF;
2624 case '8':
2625 case 'C':
2626 case 'j':
2627 install_operand (s[1], tmpreg);
2628 break;
2629 default:
2630 abort ();
2631 }
2632 break;
2633
2634 case '+':
2635 case '-':
2636 case 'A':
2637 case 'a':
2638 install_operand (s[1], opP->reg - ADDR);
2639 break;
2640
2641 case 'B':
3e602632 2642 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2643 switch (s[1])
2644 {
2645 case 'B':
8390138c 2646 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2647 break;
2648 case 'W':
2649 add_fix ('w', &opP->disp, 1, 0);
2650 addword (0);
2651 break;
2652 case 'L':
2653 long_branch:
151337e8 2654 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2655 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2656 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2657 add_fix ('l', &opP->disp, 1, 0);
2658 addword (0);
2659 addword (0);
2660 break;
2661 case 'g':
36759679 2662 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2663 goto long_branch;
2664
2665#ifdef OBJ_ELF
2666 /* If the displacement needs pic relocation it cannot be
2667 relaxed. */
2668 if (opP->disp.pic_reloc != pic_none)
2669 goto long_branch;
2670#endif
252b5132 2671 /* This could either be a symbol, or an absolute
151337e8
NC		 2672 address. If it's an absolute address, turn it into
2673 an absolute jump right here and keep it out of the
2674 relaxer. */
2675 if (adds (&opP->disp) == 0)
2676 {
2677 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2678 the_ins.opcode[0] = 0x4EF9;
151337e8 2679 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2680 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2681 else /* jCC */
2682 {
2683 the_ins.opcode[0] ^= 0x0100;
2684 the_ins.opcode[0] |= 0x0006;
18566f55 2685 addword (0x4EF9);
151337e8
NC		 2686 }
2687 add_fix ('l', &opP->disp, 0, 0);
2688 addword (0);
2689 addword (0);
2690 break;
2691 }
2692
2693 /* Now we know it's going into the relaxer. Now figure
2694 out which mode. We try in this order of preference:
2695 long branch, absolute jump, byte/word branches only. */
2696 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2697 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2698 TAB (BRANCHBWL, SZ_UNDEF));
2699 else if (! flag_keep_pcrel)
2700 {
2701 if ((the_ins.opcode[0] == 0x6000)
2702 || (the_ins.opcode[0] == 0x6100))
2703 add_frag (adds (&opP->disp), offs (&opP->disp),
2704 TAB (BRABSJUNC, SZ_UNDEF));
2705 else
2706 add_frag (adds (&opP->disp), offs (&opP->disp),
2707 TAB (BRABSJCOND, SZ_UNDEF));
2708 }
252b5132
RH		 2709 else
2710 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2711 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2712 break;
2713 case 'w':
2714 if (isvar (&opP->disp))
2715 {
151337e8
NC		 2716 /* Check for DBcc instructions. We can relax them,
2717 but only if we have long branches and/or absolute
2718 jumps. */
2719 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2720 && (HAVE_LONG_BRANCH (current_architecture)
2721 || (! flag_keep_pcrel)))
252b5132 2722 {
151337e8
NC		 2723 if (HAVE_LONG_BRANCH (current_architecture))
2724 add_frag (adds (&opP->disp), offs (&opP->disp),
2725 TAB (DBCCLBR, SZ_UNDEF));
2726 else
2727 add_frag (adds (&opP->disp), offs (&opP->disp),
2728 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2729 break;
2730 }
252b5132
RH		 2731 add_fix ('w', &opP->disp, 1, 0);
2732 }
2733 addword (0);
2734 break;
36759679 2735 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2736 add_fix ('l', &opP->disp, 1, 0);
2737 addword (0);
2738 addword (0);
2739 break;
36759679 2740 case 'c': /* Var size Coprocesssor branches. */
151337e8 2741 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2742 {
252b5132
RH		 2743 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2744 add_fix ('l', &opP->disp, 1, 0);
2745 addword (0);
2746 addword (0);
2747 }
151337e8
NC		 2748 else
2749 add_frag (adds (&opP->disp), offs (&opP->disp),
2750 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2751 break;
2752 default:
2753 abort ();
2754 }
2755 break;
2756
36759679 2757 case 'C': /* Ignore it. */
252b5132
RH		 2758 break;
2759
36759679 2760 case 'd': /* JF this is a kludge. */
252b5132 2761 install_operand ('s', opP->reg - ADDR);
3e602632 2762 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2763 if (!issword (tmpreg))
2764 {
2765 as_warn (_("Expression out of range, using 0"));
2766 tmpreg = 0;
2767 }
2768 addword (tmpreg);
2769 break;
2770
2771 case 'D':
2772 install_operand (s[1], opP->reg - DATA);
2773 break;
2774
fd99574b
NC		 2775 case 'e': /* EMAC ACCx, reg/reg. */
2776 install_operand (s[1], opP->reg - ACC);
2777 break;
2778
36759679 2779 case 'E': /* Ignore it. */
6da466c7
ILT		 2780 break;
2781
252b5132
RH		 2782 case 'F':
2783 install_operand (s[1], opP->reg - FP0);
2784 break;
2785
fd99574b
NC		 2786 case 'g': /* EMAC ACCEXTx. */
2787 install_operand (s[1], opP->reg - ACCEXT01);
2788 break;
2789
36759679 2790 case 'G': /* Ignore it. */
6da466c7
ILT		 2791 case 'H':
2792 break;
2793
252b5132
RH		 2794 case 'I':
2795 tmpreg = opP->reg - COP0;
2796 install_operand (s[1], tmpreg);
2797 break;
2798
fd99574b
NC		 2799 case 'i': /* MAC/EMAC scale factor. */
2800 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2801 break;
2802
36759679 2803 case 'J': /* JF foo. */
252b5132
RH		 2804 switch (opP->reg)
2805 {
2806 case SFC:
2807 tmpreg = 0x000;
2808 break;
2809 case DFC:
2810 tmpreg = 0x001;
2811 break;
2812 case CACR:
2813 tmpreg = 0x002;
2814 break;
2815 case TC:
2816 tmpreg = 0x003;
2817 break;
3e602632 2818 case ACR0:
252b5132
RH		 2819 case ITT0:
2820 tmpreg = 0x004;
2821 break;
3e602632 2822 case ACR1:
252b5132
RH		 2823 case ITT1:
2824 tmpreg = 0x005;
2825 break;
3e602632 2826 case ACR2:
252b5132
RH		 2827 case DTT0:
2828 tmpreg = 0x006;
2829 break;
3e602632 2830 case ACR3:
252b5132
RH		 2831 case DTT1:
2832 tmpreg = 0x007;
2833 break;
2834 case BUSCR:
2835 tmpreg = 0x008;
2836 break;
2837
2838 case USP:
2839 tmpreg = 0x800;
2840 break;
2841 case VBR:
2842 tmpreg = 0x801;
2843 break;
2844 case CAAR:
2845 tmpreg = 0x802;
2846 break;
2847 case MSP:
2848 tmpreg = 0x803;
2849 break;
2850 case ISP:
2851 tmpreg = 0x804;
2852 break;
2853 case MMUSR:
2854 tmpreg = 0x805;
2855 break;
2856 case URP:
2857 tmpreg = 0x806;
2858 break;
2859 case SRP:
2860 tmpreg = 0x807;
2861 break;
2862 case PCR:
2863 tmpreg = 0x808;
2864 break;
2865 case ROMBAR:
2866 tmpreg = 0xC00;
2867 break;
3e602632
NC		 2868 case ROMBAR1:
2869 tmpreg = 0xC01;
2870 break;
2871 case FLASHBAR:
252b5132
RH		 2872 case RAMBAR0:
2873 tmpreg = 0xC04;
2874 break;
3e602632 2875 case RAMBAR:
252b5132
RH		 2876 case RAMBAR1:
2877 tmpreg = 0xC05;
2878 break;
3e602632
NC		 2879 case MPCR:
2880 tmpreg = 0xC0C;
2881 break;
2882 case EDRAMBAR:
2883 tmpreg = 0xC0D;
2884 break;
2885 case MBAR0:
2886 case SECMBAR:
2887 tmpreg = 0xC0E;
2888 break;
2889 case MBAR1:
252b5132
RH		 2890 case MBAR:
2891 tmpreg = 0xC0F;
2892 break;
3e602632
NC		 2893 case PCR1U0:
2894 tmpreg = 0xD02;
2895 break;
2896 case PCR1L0:
2897 tmpreg = 0xD03;
2898 break;
2899 case PCR2U0:
2900 tmpreg = 0xD04;
2901 break;
2902 case PCR2L0:
2903 tmpreg = 0xD05;
2904 break;
2905 case PCR3U0:
2906 tmpreg = 0xD06;
2907 break;
2908 case PCR3L0:
2909 tmpreg = 0xD07;
2910 break;
2911 case PCR1L1:
2912 tmpreg = 0xD0A;
2913 break;
2914 case PCR1U1:
2915 tmpreg = 0xD0B;
2916 break;
2917 case PCR2L1:
2918 tmpreg = 0xD0C;
2919 break;
2920 case PCR2U1:
2921 tmpreg = 0xD0D;
2922 break;
2923 case PCR3L1:
2924 tmpreg = 0xD0E;
2925 break;
2926 case PCR3U1:
2927 tmpreg = 0xD0F;
2928 break;
252b5132
RH		 2929 default:
2930 abort ();
2931 }
2932 install_operand (s[1], tmpreg);
2933 break;
2934
2935 case 'k':
2936 tmpreg = get_num (&opP->disp, 55);
2937 install_operand (s[1], tmpreg & 0x7f);
2938 break;
2939
2940 case 'l':
2941 tmpreg = opP->mask;
2942 if (s[1] == 'w')
2943 {
2944 if (tmpreg & 0x7FF0000)
2945 as_bad (_("Floating point register in register list"));
2946 insop (reverse_16_bits (tmpreg), opcode);
2947 }
2948 else
2949 {
2950 if (tmpreg & 0x700FFFF)
2951 as_bad (_("Wrong register in floating-point reglist"));
2952 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2953 }
2954 break;
2955
2956 case 'L':
2957 tmpreg = opP->mask;
2958 if (s[1] == 'w')
2959 {
2960 if (tmpreg & 0x7FF0000)
2961 as_bad (_("Floating point register in register list"));
2962 insop (tmpreg, opcode);
2963 }
2964 else if (s[1] == '8')
2965 {
2966 if (tmpreg & 0x0FFFFFF)
2967 as_bad (_("incorrect register in reglist"));
2968 install_operand (s[1], tmpreg >> 24);
2969 }
2970 else
2971 {
2972 if (tmpreg & 0x700FFFF)
2973 as_bad (_("wrong register in floating-point reglist"));
2974 else
2975 install_operand (s[1], tmpreg >> 16);
2976 }
2977 break;
2978
2979 case 'M':
2980 install_operand (s[1], get_num (&opP->disp, 60));
2981 break;
2982
2983 case 'O':
2984 tmpreg = ((opP->mode == DREG)
8fce3f5e 2985 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2986 : (get_num (&opP->disp, 40) & 0x1F));
2987 install_operand (s[1], tmpreg);
2988 break;
2989
2990 case 'Q':
2991 tmpreg = get_num (&opP->disp, 10);
2992 if (tmpreg == 8)
2993 tmpreg = 0;
2994 install_operand (s[1], tmpreg);
2995 break;
2996
2997 case 'R':
2998 /* This depends on the fact that ADDR registers are eight
2999 more than their corresponding DATA regs, so the result
36759679 3000 will have the ADDR_REG bit set. */
252b5132
RH		 3001 install_operand (s[1], opP->reg - DATA);
3002 break;
3003
3004 case 'r':
3005 if (opP->mode == AINDR)
3006 install_operand (s[1], opP->reg - DATA);
3007 else
3008 install_operand (s[1], opP->index.reg - DATA);
3009 break;
3010
3011 case 's':
3012 if (opP->reg == FPI)
3013 tmpreg = 0x1;
3014 else if (opP->reg == FPS)
3015 tmpreg = 0x2;
3016 else if (opP->reg == FPC)
3017 tmpreg = 0x4;
3018 else
3019 abort ();
3020 install_operand (s[1], tmpreg);
3021 break;
3022
36759679 3023 case 'S': /* Ignore it. */
252b5132
RH		 3024 break;
3025
3026 case 'T':
3027 install_operand (s[1], get_num (&opP->disp, 30));
3028 break;
3029
36759679 3030 case 'U': /* Ignore it. */
252b5132
RH		 3031 break;
3032
3033 case 'c':
3034 switch (opP->reg)
3035 {
3036 case NC:
3037 tmpreg = 0;
3038 break;
3039 case DC:
3040 tmpreg = 1;
3041 break;
3042 case IC:
3043 tmpreg = 2;
3044 break;
3045 case BC:
3046 tmpreg = 3;
3047 break;
3048 default:
3049 as_fatal (_("failed sanity check"));
36759679 3050 } /* switch on cache token. */
252b5132
RH		 3051 install_operand (s[1], tmpreg);
3052 break;
3053#ifndef NO_68851
92774660 3054 /* JF: These are out of order, I fear. */
252b5132
RH		 3055 case 'f':
3056 switch (opP->reg)
3057 {
3058 case SFC:
3059 tmpreg = 0;
3060 break;
3061 case DFC:
3062 tmpreg = 1;
3063 break;
3064 default:
3065 abort ();
3066 }
3067 install_operand (s[1], tmpreg);
3068 break;
3069
3070 case '0':
3071 case '1':
3072 case '2':
3073 switch (opP->reg)
3074 {
3075 case TC:
3076 tmpreg = 0;
3077 break;
3078 case CAL:
3079 tmpreg = 4;
3080 break;
3081 case VAL:
3082 tmpreg = 5;
3083 break;
3084 case SCC:
3085 tmpreg = 6;
3086 break;
3087 case AC:
3088 tmpreg = 7;
3089 break;
3090 default:
3091 abort ();
3092 }
3093 install_operand (s[1], tmpreg);
3094 break;
3095
3096 case 'V':
3097 if (opP->reg == VAL)
3098 break;
3099 abort ();
3100
3101 case 'W':
3102 switch (opP->reg)
3103 {
3104 case DRP:
3105 tmpreg = 1;
3106 break;
3107 case SRP:
3108 tmpreg = 2;
3109 break;
3110 case CRP:
3111 tmpreg = 3;
3112 break;
3113 default:
3114 abort ();
3115 }
3116 install_operand (s[1], tmpreg);
3117 break;
3118
3119 case 'X':
3120 switch (opP->reg)
3121 {
3122 case BAD:
3123 case BAD + 1:
3124 case BAD + 2:
3125 case BAD + 3:
3126 case BAD + 4:
3127 case BAD + 5:
3128 case BAD + 6:
3129 case BAD + 7:
3130 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3131 break;
3132
3133 case BAC:
3134 case BAC + 1:
3135 case BAC + 2:
3136 case BAC + 3:
3137 case BAC + 4:
3138 case BAC + 5:
3139 case BAC + 6:
3140 case BAC + 7:
3141 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3142 break;
3143
3144 default:
3145 abort ();
3146 }
3147 install_operand (s[1], tmpreg);
3148 break;
3149 case 'Y':
3150 know (opP->reg == PSR);
3151 break;
3152 case 'Z':
3153 know (opP->reg == PCSR);
3154 break;
3155#endif /* m68851 */
3156 case '3':
3157 switch (opP->reg)
3158 {
3159 case TT0:
3160 tmpreg = 2;
3161 break;
3162 case TT1:
3163 tmpreg = 3;
3164 break;
3165 default:
3166 abort ();
3167 }
3168 install_operand (s[1], tmpreg);
3169 break;
3170 case 't':
3171 tmpreg = get_num (&opP->disp, 20);
3172 install_operand (s[1], tmpreg);
3173 break;
36759679 3174 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3175 if (isvar (&opP->disp))
3176 add_fix ('l', &opP->disp, 0, 0);
3e602632 3177 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3178 addword (tmpreg >> 16);
3179 addword (tmpreg & 0xFFFF);
3180 break;
6da466c7
ILT		 3181 case 'u':
3182 install_operand (s[1], opP->reg - DATA0L);
3183 opP->reg -= (DATA0L);
36759679 3184 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3185 break;
3e602632
NC		 3186 case 'x':
3187 tmpreg = get_num (&opP->disp, 80);
3188 if (tmpreg == -1)
3189 tmpreg = 0;
3190 install_operand (s[1], tmpreg);
3191 break;
252b5132
RH		 3192 default:
3193 abort ();
3194 }
3195 }
3196
3197 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3198 instruction, ready to be emitted. . . */
252b5132
RH		 3199}
3200
3201static int
3202reverse_16_bits (in)
3203 int in;
3204{
3205 int out = 0;
3206 int n;
3207
3208 static int mask[16] =
3209 {
3210 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3211 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3212 };
3213 for (n = 0; n < 16; n++)
3214 {
3215 if (in & mask[n])
3216 out |= mask[15 - n];
3217 }
3218 return out;
3219} /* reverse_16_bits() */
3220
3221static int
3222reverse_8_bits (in)
3223 int in;
3224{
3225 int out = 0;
3226 int n;
3227
3228 static int mask[8] =
3229 {
3230 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3231 };
3232
3233 for (n = 0; n < 8; n++)
3234 {
3235 if (in & mask[n])
3236 out |= mask[7 - n];
3237 }
3238 return out;
3239} /* reverse_8_bits() */
3240
3241/* Cause an extra frag to be generated here, inserting up to 10 bytes
3242 (that value is chosen in the frag_var call in md_assemble). TYPE
3243 is the subtype of the frag to be generated; its primary type is
3244 rs_machine_dependent.
3245
3246 The TYPE parameter is also used by md_convert_frag_1 and
3247 md_estimate_size_before_relax. The appropriate type of fixup will
3248 be emitted by md_convert_frag_1.
3249
3250 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3251static void
3252install_operand (mode, val)
3253 int mode;
3254 int val;
3255{
3256 switch (mode)
3257 {
3258 case 's':
36759679 3259 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3260 break;
3261 case 'd':
3262 the_ins.opcode[0] |= val << 9;
3263 break;
3264 case '1':
3265 the_ins.opcode[1] |= val << 12;
3266 break;
3267 case '2':
3268 the_ins.opcode[1] |= val << 6;
3269 break;
3270 case '3':
3271 the_ins.opcode[1] |= val;
3272 break;
3273 case '4':
3274 the_ins.opcode[2] |= val << 12;
3275 break;
3276 case '5':
3277 the_ins.opcode[2] |= val << 6;
3278 break;
3279 case '6':
3280 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3281 three words long! */
3282 the_ins.numo++;
3283 the_ins.opcode[2] |= val;
3284 break;
3285 case '7':
3286 the_ins.opcode[1] |= val << 7;
3287 break;
3288 case '8':
3289 the_ins.opcode[1] |= val << 10;
3290 break;
3291#ifndef NO_68851
3292 case '9':
3293 the_ins.opcode[1] |= val << 5;
3294 break;
3295#endif
3296
3297 case 't':
3298 the_ins.opcode[1] |= (val << 10) | (val << 7);
3299 break;
3300 case 'D':
3301 the_ins.opcode[1] |= (val << 12) | val;
3302 break;
3303 case 'g':
3304 the_ins.opcode[0] |= val = 0xff;
3305 break;
3306 case 'i':
3307 the_ins.opcode[0] |= val << 9;
3308 break;
3309 case 'C':
3310 the_ins.opcode[1] |= val;
3311 break;
3312 case 'j':
3313 the_ins.opcode[1] |= val;
36759679 3314 the_ins.numo++; /* What a hack. */
252b5132
RH		 3315 break;
3316 case 'k':
3317 the_ins.opcode[1] |= val << 4;
3318 break;
3319 case 'b':
3320 case 'w':
3321 case 'W':
3322 case 'l':
3323 break;
3324 case 'e':
3325 the_ins.opcode[0] |= (val << 6);
3326 break;
3327 case 'L':
3328 the_ins.opcode[1] = (val >> 16);
3329 the_ins.opcode[2] = val & 0xffff;
3330 break;
6da466c7
ILT		 3331 case 'm':
3332 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3333 the_ins.opcode[0] |= ((val & 0x7) << 9);
3334 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3335 break;
fd99574b 3336 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3337 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3338 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3339 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3340 break;
fd99574b 3341 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3342 the_ins.opcode[1] |= val << 12;
3343 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3344 break;
fd99574b 3345 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3346 the_ins.opcode[0] |= (val & 0xF);
3347 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3348 break;
fd99574b 3349 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3350 the_ins.opcode[1] |= (val & 0xF);
3351 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3352 break;
3353 case 'h':
3354 the_ins.opcode[1] |= ((val != 1) << 10);
3355 break;
fd99574b
NC		 3356 case 'F':
3357 the_ins.opcode[0] |= ((val & 0x3) << 9);
3358 break;
3359 case 'f':
3360 the_ins.opcode[0] |= ((val & 0x3) << 0);
3361 break;
3362 case 'G':
3363 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3364 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3365 break;
3366 case 'H':
3367 the_ins.opcode[0] |= ((val & 0x1) << 7);
3368 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3369 break;
3370 case 'I':
3371 the_ins.opcode[1] |= ((val & 0x3) << 9);
3372 break;
3373 case ']':
3374 the_ins.opcode[0] |= (val & 0x1) <<10;
3375 break;
252b5132
RH		 3376 case 'c':
3377 default:
3378 as_fatal (_("failed sanity check."));
3379 }
3380} /* install_operand() */
3381
3382static void
3383install_gen_operand (mode, val)
3384 int mode;
3385 int val;
3386{
3387 switch (mode)
3388 {
fd99574b
NC		 3389 case '/': /* Special for mask loads for mac/msac insns with
3390 possible mask; trailing_ampersend set in bit 8. */
3391 the_ins.opcode[0] |= (val & 0x3f);
3392 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3393 break;
252b5132
RH		 3394 case 's':
3395 the_ins.opcode[0] |= val;
3396 break;
3397 case 'd':
3398 /* This is a kludge!!! */
3399 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3400 break;
3401 case 'b':
3402 case 'w':
3403 case 'l':
3404 case 'f':
3405 case 'F':
3406 case 'x':
3407 case 'p':
3408 the_ins.opcode[0] |= val;
3409 break;
36759679 3410 /* more stuff goes here. */
252b5132
RH		 3411 default:
3412 as_fatal (_("failed sanity check."));
3413 }
3414} /* install_gen_operand() */
3415
3416/*
3417 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3418 * then deal with the bitfield hack.
3419 */
3420
3421static char *
3422crack_operand (str, opP)
3423 register char *str;
3424 register struct m68k_op *opP;
3425{
3426 register int parens;
3427 register int c;
3428 register char *beg_str;
3429 int inquote = 0;
3430
3431 if (!str)
3432 {
3433 return str;
3434 }
3435 beg_str = str;
3436 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3437 {
3438 if (! inquote)
3439 {
3440 if (*str == '(')
3441 parens++;
3442 else if (*str == ')')
3443 {
3444 if (!parens)
36759679 3445 { /* ERROR. */
252b5132
RH		 3446 opP->error = _("Extra )");
3447 return str;
3448 }
3449 --parens;
3450 }
3451 }
3452 if (flag_mri && *str == '\'')
3453 inquote = ! inquote;
3454 }
3455 if (!*str && parens)
36759679 3456 { /* ERROR. */
252b5132
RH		 3457 opP->error = _("Missing )");
3458 return str;
3459 }
3460 c = *str;
3461 *str = '\0';
3462 if (m68k_ip_op (beg_str, opP) != 0)
3463 {
3464 *str = c;
3465 return str;
3466 }
3467 *str = c;
3468 if (c == '}')
36759679 3469 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3470 if (c)
3471 {
3472 c = *++str;
3473 if (!c)
3474 as_bad (_("Missing operand"));
3475 }
3476
3477 /* Detect MRI REG symbols and convert them to REGLSTs. */
3478 if (opP->mode == CONTROL && (int)opP->reg < 0)
3479 {
3480 opP->mode = REGLST;
3481 opP->mask = ~(int)opP->reg;
3482 opP->reg = 0;
3483 }
3484
3485 return str;
3486}
3487
3488/* This is the guts of the machine-dependent assembler. STR points to a
3489 machine dependent instruction. This function is supposed to emit
3490 the frags/bytes it assembles to.
3491 */
3492
3493static void
3494insert_reg (regname, regnum)
3495 const char *regname;
3496 int regnum;
3497{
3498 char buf[100];
3499 int i;
3500
3501#ifdef REGISTER_PREFIX
3502 if (!flag_reg_prefix_optional)
3503 {
3504 buf[0] = REGISTER_PREFIX;
3505 strcpy (buf + 1, regname);
3506 regname = buf;
3507 }
3508#endif
3509
3510 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3511 &zero_address_frag));
3512
3513 for (i = 0; regname[i]; i++)
3882b010 3514 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3515 buf[i] = '\0';
3516
3517 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3518 &zero_address_frag));
3519}
3520
3521struct init_entry
3522 {
3523 const char *name;
3524 int number;
3525 };
3526
3527static const struct init_entry init_table[] =
3528{
3529 { "d0", DATA0 },
3530 { "d1", DATA1 },
3531 { "d2", DATA2 },
3532 { "d3", DATA3 },
3533 { "d4", DATA4 },
3534 { "d5", DATA5 },
3535 { "d6", DATA6 },
3536 { "d7", DATA7 },
3537 { "a0", ADDR0 },
3538 { "a1", ADDR1 },
3539 { "a2", ADDR2 },
3540 { "a3", ADDR3 },
3541 { "a4", ADDR4 },
3542 { "a5", ADDR5 },
3543 { "a6", ADDR6 },
3544 { "fp", ADDR6 },
3545 { "a7", ADDR7 },
3546 { "sp", ADDR7 },
3547 { "ssp", ADDR7 },
3548 { "fp0", FP0 },
3549 { "fp1", FP1 },
3550 { "fp2", FP2 },
3551 { "fp3", FP3 },
3552 { "fp4", FP4 },
3553 { "fp5", FP5 },
3554 { "fp6", FP6 },
3555 { "fp7", FP7 },
3556 { "fpi", FPI },
3557 { "fpiar", FPI },
3558 { "fpc", FPI },
3559 { "fps", FPS },
3560 { "fpsr", FPS },
3561 { "fpc", FPC },
3562 { "fpcr", FPC },
3563 { "control", FPC },
3564 { "status", FPS },
3565 { "iaddr", FPI },
3566
3567 { "cop0", COP0 },
3568 { "cop1", COP1 },
3569 { "cop2", COP2 },
3570 { "cop3", COP3 },
3571 { "cop4", COP4 },
3572 { "cop5", COP5 },
3573 { "cop6", COP6 },
3574 { "cop7", COP7 },
3575 { "pc", PC },
3576 { "zpc", ZPC },
3577 { "sr", SR },
3578
3579 { "ccr", CCR },
3580 { "cc", CCR },
3581
6da466c7 3582 { "acc", ACC },
fd99574b
NC		 3583 { "acc0", ACC },
3584 { "acc1", ACC1 },
3585 { "acc2", ACC2 },
3586 { "acc3", ACC3 },
3587 { "accext01", ACCEXT01 },
3588 { "accext23", ACCEXT23 },
6da466c7
ILT		 3589 { "macsr", MACSR },
3590 { "mask", MASK },
3591
36759679
NC		 3592 /* Control registers. */
3593 { "sfc", SFC }, /* Source Function Code. */
252b5132 3594 { "sfcr", SFC },
36759679 3595 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3596 { "dfcr", DFC },
36759679
NC		 3597 { "cacr", CACR }, /* Cache Control Register. */
3598 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3599
36759679
NC		 3600 { "usp", USP }, /* User Stack Pointer. */
3601 { "vbr", VBR }, /* Vector Base Register. */
3602 { "msp", MSP }, /* Master Stack Pointer. */
3603 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3604
36759679
NC		 3605 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3606 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3607 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3608 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3609
3610 /* 68ec040 versions of same */
36759679
NC		 3611 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3612 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3613 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3614 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3615
3616 /* mcf5200 versions of same. The ColdFire programmer's reference
3617 manual indicated that the order is 2,3,0,1, but Ken Rose
3618 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3619 { "acr0", ACR0 }, /* Access Control Unit 0. */
3620 { "acr1", ACR1 }, /* Access Control Unit 1. */
3621 { "acr2", ACR2 }, /* Access Control Unit 2. */
3622 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3623
36759679 3624 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3625 { "tcr", TC },
3626
36759679
NC		 3627 { "mmusr", MMUSR }, /* MMU Status Register. */
3628 { "srp", SRP }, /* User Root Pointer. */
3629 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3630
3631 { "buscr", BUSCR },
3632 { "pcr", PCR },
3633
36759679
NC		 3634 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3635 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3636 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3637 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3638
3639 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3640 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3641 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3642 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3643 { "mpcr", MPCR }, /* mcfv4e registers. */
3644 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3645 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3646 { "asid", TC }, /* mcfv4e registers. */
3647 { "mmubar", BUSCR }, /* mcfv4e registers. */
3648 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3649 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3650 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3651 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3652 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3653 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3654 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3655 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3656 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3657 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3658 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3659 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3660
3661 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3662 { "rambar", RAMBAR }, /* mcf528x registers. */
36759679 3663 /* End of control registers. */
252b5132
RH		 3664
3665 { "ac", AC },
3666 { "bc", BC },
3667 { "cal", CAL },
3668 { "crp", CRP },
3669 { "drp", DRP },
3670 { "pcsr", PCSR },
3671 { "psr", PSR },
3672 { "scc", SCC },
3673 { "val", VAL },
3674 { "bad0", BAD0 },
3675 { "bad1", BAD1 },
3676 { "bad2", BAD2 },
3677 { "bad3", BAD3 },
3678 { "bad4", BAD4 },
3679 { "bad5", BAD5 },
3680 { "bad6", BAD6 },
3681 { "bad7", BAD7 },
3682 { "bac0", BAC0 },
3683 { "bac1", BAC1 },
3684 { "bac2", BAC2 },
3685 { "bac3", BAC3 },
3686 { "bac4", BAC4 },
3687 { "bac5", BAC5 },
3688 { "bac6", BAC6 },
3689 { "bac7", BAC7 },
3690
3691 { "ic", IC },
3692 { "dc", DC },
3693 { "nc", NC },
3694
3695 { "tt0", TT0 },
3696 { "tt1", TT1 },
36759679 3697 /* 68ec030 versions of same. */
252b5132
RH		 3698 { "ac0", TT0 },
3699 { "ac1", TT1 },
36759679 3700 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3701 { "acusr", PSR },
3702
3703 /* Suppressed data and address registers. */
3704 { "zd0", ZDATA0 },
3705 { "zd1", ZDATA1 },
3706 { "zd2", ZDATA2 },
3707 { "zd3", ZDATA3 },
3708 { "zd4", ZDATA4 },
3709 { "zd5", ZDATA5 },
3710 { "zd6", ZDATA6 },
3711 { "zd7", ZDATA7 },
3712 { "za0", ZADDR0 },
3713 { "za1", ZADDR1 },
3714 { "za2", ZADDR2 },
3715 { "za3", ZADDR3 },
3716 { "za4", ZADDR4 },
3717 { "za5", ZADDR5 },
3718 { "za6", ZADDR6 },
3719 { "za7", ZADDR7 },
3720
92774660 3721 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3722 { "d0l", DATA0L },
3723 { "d1l", DATA1L },
3724 { "d2l", DATA2L },
3725 { "d3l", DATA3L },
3726 { "d4l", DATA4L },
3727 { "d5l", DATA5L },
3728 { "d6l", DATA6L },
3729 { "d7l", DATA7L },
3730
3731 { "a0l", ADDR0L },
3732 { "a1l", ADDR1L },
3733 { "a2l", ADDR2L },
3734 { "a3l", ADDR3L },
3735 { "a4l", ADDR4L },
3736 { "a5l", ADDR5L },
3737 { "a6l", ADDR6L },
3738 { "a7l", ADDR7L },
3739
3740 { "d0u", DATA0U },
3741 { "d1u", DATA1U },
3742 { "d2u", DATA2U },
3743 { "d3u", DATA3U },
3744 { "d4u", DATA4U },
3745 { "d5u", DATA5U },
3746 { "d6u", DATA6U },
3747 { "d7u", DATA7U },
3748
3749 { "a0u", ADDR0U },
3750 { "a1u", ADDR1U },
3751 { "a2u", ADDR2U },
3752 { "a3u", ADDR3U },
3753 { "a4u", ADDR4U },
3754 { "a5u", ADDR5U },
3755 { "a6u", ADDR6U },
3756 { "a7u", ADDR7U },
3757
252b5132
RH		 3758 { 0, 0 }
3759};
3760
3761static void
3762init_regtable ()
3763{
3764 int i;
3765 for (i = 0; init_table[i].name; i++)
3766 insert_reg (init_table[i].name, init_table[i].number);
3767}
3768
3769static int no_68851, no_68881;
3770
3771#ifdef OBJ_AOUT
3772/* a.out machine type. Default to 68020. */
3773int m68k_aout_machtype = 2;
3774#endif
3775
3776void
3777md_assemble (str)
3778 char *str;
3779{
3780 const char *er;
3781 short *fromP;
3782 char *toP = NULL;
3783 int m, n = 0;
3784 char *to_beg_P;
3785 int shorts_this_frag;
3786 fixS *fixP;
3787
3788 /* In MRI mode, the instruction and operands are separated by a
3789 space. Anything following the operands is a comment. The label
3790 has already been removed. */
3791 if (flag_mri)
3792 {
3793 char *s;
3794 int fields = 0;
3795 int infield = 0;
3796 int inquote = 0;
3797
3798 for (s = str; *s != '\0'; s++)
3799 {
3800 if ((*s == ' ' || *s == '\t') && ! inquote)
3801 {
3802 if (infield)
3803 {
3804 ++fields;
3805 if (fields >= 2)
3806 {
3807 *s = '\0';
3808 break;
3809 }
3810 infield = 0;
3811 }
3812 }
3813 else
3814 {
3815 if (! infield)
3816 infield = 1;
3817 if (*s == '\'')
3818 inquote = ! inquote;
3819 }
3820 }
3821 }
3822
3823 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3824 m68k_ip (str);
3825 er = the_ins.error;
3826 if (!er)
3827 {
3828 for (n = 0; n < the_ins.numargs; n++)
3829 if (the_ins.operands[n].error)
3830 {
3831 er = the_ins.operands[n].error;
3832 break;
3833 }
3834 }
3835 if (er)
3836 {
3837 as_bad (_("%s -- statement `%s' ignored"), er, str);
3838 return;
3839 }
3840
3841 /* If there is a current label, record that it marks an instruction. */
3842 if (current_label != NULL)
3843 {
3844 current_label->text = 1;
3845 current_label = NULL;
3846 }
3847
f27a3839
AS		 3848#ifdef OBJ_ELF
3849 /* Tie dwarf2 debug info to the address at the start of the insn. */
3850 dwarf2_emit_insn (0);
3851#endif
3852
252b5132
RH		 3853 if (the_ins.nfrag == 0)
3854 {
36759679 3855 /* No frag hacking involved; just put it out. */
252b5132
RH		 3856 toP = frag_more (2 * the_ins.numo);
3857 fromP = &the_ins.opcode[0];
3858 for (m = the_ins.numo; m; --m)
3859 {
3860 md_number_to_chars (toP, (long) (*fromP), 2);
3861 toP += 2;
3862 fromP++;
3863 }
36759679 3864 /* Put out symbol-dependent info. */
252b5132
RH		 3865 for (m = 0; m < the_ins.nrel; m++)
3866 {
3867 switch (the_ins.reloc[m].wid)
3868 {
3869 case 'B':
3870 n = 1;
3871 break;
3872 case 'b':
3873 n = 1;
3874 break;
3875 case '3':
3876 n = 1;
3877 break;
3878 case 'w':
3879 case 'W':
3880 n = 2;
3881 break;
3882 case 'l':
3883 n = 4;
3884 break;
3885 default:
3886 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3887 the_ins.reloc[m].wid);
3888 }
3889
3890 fixP = fix_new_exp (frag_now,
3891 ((toP - frag_now->fr_literal)
3892 - the_ins.numo * 2 + the_ins.reloc[m].n),
3893 n,
3894 &the_ins.reloc[m].exp,
3895 the_ins.reloc[m].pcrel,
3896 get_reloc_code (n, the_ins.reloc[m].pcrel,
3897 the_ins.reloc[m].pic_reloc));
3898 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3899 if (the_ins.reloc[m].wid == 'B')
3900 fixP->fx_signed = 1;
3901 }
3902 return;
3903 }
3904
36759679 3905 /* There's some frag hacking. */
fbe572f9
AM		 3906 {
3907 /* Calculate the max frag size. */
3908 int wid;
3909
3910 wid = 2 * the_ins.fragb[0].fragoff;
3911 for (n = 1; n < the_ins.nfrag; n++)
3912 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3913 /* frag_var part. */
3914 wid += 10;
3915 /* Make sure the whole insn fits in one chunk, in particular that
3916 the var part is attached, as we access one byte before the
3917 variable frag for byte branches. */
3918 frag_grow (wid);
3919 }
3920
252b5132
RH		 3921 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3922 {
3923 int wid;
3924
3925 if (n == 0)
3926 wid = 2 * the_ins.fragb[n].fragoff;
3927 else
3928 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3929 toP = frag_more (wid);
3930 to_beg_P = toP;
3931 shorts_this_frag = 0;
3932 for (m = wid / 2; m; --m)
3933 {
3934 md_number_to_chars (toP, (long) (*fromP), 2);
3935 toP += 2;
3936 fromP++;
3937 shorts_this_frag++;
3938 }
3939 for (m = 0; m < the_ins.nrel; m++)
3940 {
3941 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3942 {
3943 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3944 break;
3945 }
3946 wid = the_ins.reloc[m].wid;
3947 if (wid == 0)
3948 continue;
3949 the_ins.reloc[m].wid = 0;
3950 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3951
3952 fixP = fix_new_exp (frag_now,
3953 ((toP - frag_now->fr_literal)
3954 - the_ins.numo * 2 + the_ins.reloc[m].n),
3955 wid,
3956 &the_ins.reloc[m].exp,
3957 the_ins.reloc[m].pcrel,
3958 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3959 the_ins.reloc[m].pic_reloc));
3960 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3961 }
3962 (void) frag_var (rs_machine_dependent, 10, 0,
3963 (relax_substateT) (the_ins.fragb[n].fragty),
3964 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3965 }
3966 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3967 shorts_this_frag = 0;
3968 if (n)
3969 {
3970 toP = frag_more (n * sizeof (short));
3971 while (n--)
3972 {
3973 md_number_to_chars (toP, (long) (*fromP), 2);
3974 toP += 2;
3975 fromP++;
3976 shorts_this_frag++;
3977 }
3978 }
3979 for (m = 0; m < the_ins.nrel; m++)
3980 {
3981 int wid;
3982
3983 wid = the_ins.reloc[m].wid;
3984 if (wid == 0)
3985 continue;
3986 the_ins.reloc[m].wid = 0;
3987 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3988
3989 fixP = fix_new_exp (frag_now,
3990 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3991 - shorts_this_frag * 2),
3992 wid,
3993 &the_ins.reloc[m].exp,
3994 the_ins.reloc[m].pcrel,
3995 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3996 the_ins.reloc[m].pic_reloc));
3997 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3998 }
3999}
4000
4001void
4002md_begin ()
4003{
4004 /*
4005 * md_begin -- set up hash tables with 68000 instructions.
4006 * similar to what the vax assembler does. ---phr
4007 */
4008 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4009 a copy of it at runtime, adding in the information we want but isn't
4010 there. I think it'd be better to have an awk script hack the table
4011 at compile time. Or even just xstr the table and use it as-is. But
4012 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4013 names. */
4014
94f592af
NC		 4015 const struct m68k_opcode *ins;
4016 struct m68k_incant *hack, *slak;
36759679 4017 const char *retval = 0; /* Empty string, or error msg text. */
94f592af 4018 int i;
252b5132
RH		 4019
4020 if (flag_mri)
4021 {
4022 flag_reg_prefix_optional = 1;
4023 m68k_abspcadd = 1;
4024 if (! m68k_rel32_from_cmdline)
4025 m68k_rel32 = 0;
4026 }
4027
4028 op_hash = hash_new ();
4029
4030 obstack_begin (&robyn, 4000);
4031 for (i = 0; i < m68k_numopcodes; i++)
4032 {
4033 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4034 do
4035 {
4036 ins = &m68k_opcodes[i];
4037 /* We *could* ignore insns that don't match our arch here
92774660 4038 but just leaving them out of the hash. */
252b5132
RH		 4039 slak->m_operands = ins->args;
4040 slak->m_opnum = strlen (slak->m_operands) / 2;
4041 slak->m_arch = ins->arch;
4042 slak->m_opcode = ins->opcode;
36759679 4043 /* This is kludgey. */
252b5132
RH		 4044 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4045 if (i + 1 != m68k_numopcodes
4046 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
4047 {
4048 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4049 i++;
4050 }
4051 else
4052 slak->m_next = 0;
4053 slak = slak->m_next;
4054 }
4055 while (slak);
4056
4057 retval = hash_insert (op_hash, ins->name, (char *) hack);
4058 if (retval)
4059 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4060 }
4061
4062 for (i = 0; i < m68k_numaliases; i++)
4063 {
4064 const char *name = m68k_opcode_aliases[i].primary;
4065 const char *alias = m68k_opcode_aliases[i].alias;
4066 PTR val = hash_find (op_hash, name);
4067 if (!val)
4068 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4069 retval = hash_insert (op_hash, alias, val);
4070 if (retval)
4071 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4072 }
4073
4074 /* In MRI mode, all unsized branches are variable sized. Normally,
4075 they are word sized. */
4076 if (flag_mri)
4077 {
4078 static struct m68k_opcode_alias mri_aliases[] =
4079 {
4080 { "bhi", "jhi", },
4081 { "bls", "jls", },
4082 { "bcc", "jcc", },
4083 { "bcs", "jcs", },
4084 { "bne", "jne", },
4085 { "beq", "jeq", },
4086 { "bvc", "jvc", },
4087 { "bvs", "jvs", },
4088 { "bpl", "jpl", },
4089 { "bmi", "jmi", },
4090 { "bge", "jge", },
4091 { "blt", "jlt", },
4092 { "bgt", "jgt", },
4093 { "ble", "jle", },
4094 { "bra", "jra", },
4095 { "bsr", "jbsr", },
4096 };
4097
8fce3f5e
AM		 4098 for (i = 0;
4099 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4100 i++)
252b5132
RH		 4101 {
4102 const char *name = mri_aliases[i].primary;
4103 const char *alias = mri_aliases[i].alias;
4104 PTR val = hash_find (op_hash, name);
4105 if (!val)
4106 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4107 retval = hash_jam (op_hash, alias, val);
4108 if (retval)
4109 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4110 }
4111 }
4112
8fce3f5e 4113 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4114 {
4115 notend_table[i] = 0;
4116 alt_notend_table[i] = 0;
4117 }
4118 notend_table[','] = 1;
4119 notend_table['{'] = 1;
4120 notend_table['}'] = 1;
4121 alt_notend_table['a'] = 1;
4122 alt_notend_table['A'] = 1;
4123 alt_notend_table['d'] = 1;
4124 alt_notend_table['D'] = 1;
4125 alt_notend_table['#'] = 1;
4126 alt_notend_table['&'] = 1;
4127 alt_notend_table['f'] = 1;
4128 alt_notend_table['F'] = 1;
4129#ifdef REGISTER_PREFIX
4130 alt_notend_table[REGISTER_PREFIX] = 1;
4131#endif
4132
4133 /* We need to put '(' in alt_notend_table to handle
4134 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
4135 */
4136 alt_notend_table['('] = 1;
4137
4138 /* We need to put '@' in alt_notend_table to handle
4139 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
4140 */
4141 alt_notend_table['@'] = 1;
4142
4143 /* We need to put digits in alt_notend_table to handle
4144 bfextu %d0{24:1},%d0
4145 */
4146 alt_notend_table['0'] = 1;
4147 alt_notend_table['1'] = 1;
4148 alt_notend_table['2'] = 1;
4149 alt_notend_table['3'] = 1;
4150 alt_notend_table['4'] = 1;
4151 alt_notend_table['5'] = 1;
4152 alt_notend_table['6'] = 1;
4153 alt_notend_table['7'] = 1;
4154 alt_notend_table['8'] = 1;
4155 alt_notend_table['9'] = 1;
4156
4157#ifndef MIT_SYNTAX_ONLY
4158 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4159 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4160 {
4161 int n = 0;
4162 while (mote_pseudo_table[n].poc_name)
4163 {
4164 hack = (struct m68k_incant *)
4165 obstack_alloc (&robyn, sizeof (struct m68k_incant));
4166 hash_insert (op_hash,
4167 mote_pseudo_table[n].poc_name, (char *) hack);
4168 hack->m_operands = 0;
4169 hack->m_opnum = n;
4170 n++;
4171 }
4172 }
4173#endif
4174
4175 init_regtable ();
4176
4177#ifdef OBJ_ELF
4178 record_alignment (text_section, 2);
4179 record_alignment (data_section, 2);
4180 record_alignment (bss_section, 2);
4181#endif
4182}
4183
4184static void
4185select_control_regs ()
4186{
4187 /* Note which set of "movec" control registers is available. */
4188 switch (cpu_of_arch (current_architecture))
4189 {
4f2a7c9e
NC		 4190 case 0:
4191 as_warn (_("architecture not yet selected: defaulting to 68020"));
4192 control_regs = m68020_control_regs;
4193 break;
4194
252b5132
RH		 4195 case m68000:
4196 control_regs = m68000_control_regs;
4197 break;
4198 case m68010:
4199 control_regs = m68010_control_regs;
4200 break;
4201 case m68020:
4202 case m68030:
4203 control_regs = m68020_control_regs;
4204 break;
4205 case m68040:
4206 control_regs = m68040_control_regs;
4207 break;
4208 case m68060:
4209 control_regs = m68060_control_regs;
4210 break;
4211 case cpu32:
4212 control_regs = cpu32_control_regs;
4213 break;
4214 case mcf5200:
6da466c7
ILT		 4215 case mcf5206e:
4216 case mcf5307:
dc84e067 4217 case mcf5407:
6da466c7 4218 control_regs = mcf_control_regs;
252b5132 4219 break;
3e602632
NC		 4220 case mcf528x:
4221 control_regs = mcf528x_control_regs;
4222 break;
4223 case mcfv4e:
4224 control_regs = mcfv4e_control_regs;
4225 break;
252b5132
RH		 4226 default:
4227 abort ();
4228 }
4229}
4230
4231void
4232m68k_init_after_args ()
4233{
4234 if (cpu_of_arch (current_architecture) == 0)
4235 {
4236 int i;
4237 const char *default_cpu = TARGET_CPU;
4238
4239 if (*default_cpu == 'm')
4240 default_cpu++;
4241 for (i = 0; i < n_archs; i++)
4242 if (strcasecmp (default_cpu, archs[i].name) == 0)
4243 break;
4244 if (i == n_archs)
4245 {
4246 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4247 current_architecture |= m68020;
4248 }
4249 else
4250 current_architecture |= archs[i].arch;
4251 }
4252 /* Permit m68881 specification with all cpus; those that can't work
4253 with a coprocessor could be doing emulation. */
4254 if (current_architecture & m68851)
4255 {
4256 if (current_architecture & m68040)
4257 {
4258 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4259 }
4260 }
4261 /* What other incompatibilities could we check for? */
4262
4263 /* Toss in some default assumptions about coprocessors. */
4264 if (!no_68881
4265 && (cpu_of_arch (current_architecture)
4266 /* Can CPU32 have a 68881 coprocessor?? */
4267 & (m68020 | m68030 | cpu32)))
4268 {
4269 current_architecture |= m68881;
4270 }
4271 if (!no_68851
4272 && (cpu_of_arch (current_architecture) & m68020up) != 0
4273 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4274 {
4275 current_architecture |= m68851;
4276 }
4277 if (no_68881 && (current_architecture & m68881))
4278 as_bad (_("options for 68881 and no-68881 both given"));
4279 if (no_68851 && (current_architecture & m68851))
4280 as_bad (_("options for 68851 and no-68851 both given"));
4281
4282#ifdef OBJ_AOUT
4283 /* Work out the magic number. This isn't very general. */
4284 if (current_architecture & m68000)
4285 m68k_aout_machtype = 0;
4286 else if (current_architecture & m68010)
4287 m68k_aout_machtype = 1;
4288 else if (current_architecture & m68020)
4289 m68k_aout_machtype = 2;
4290 else
4291 m68k_aout_machtype = 2;
4292#endif
4293
4294 /* Note which set of "movec" control registers is available. */
4295 select_control_regs ();
4296
4297 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4298 || arch_coldfire_p (current_architecture))
252b5132
RH		 4299 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4300}
4301\f
4302/* This is called when a label is defined. */
4303
4304void
4305m68k_frob_label (sym)
4306 symbolS *sym;
4307{
4308 struct label_line *n;
4309
4310 n = (struct label_line *) xmalloc (sizeof *n);
4311 n->next = labels;
4312 n->label = sym;
4313 as_where (&n->file, &n->line);
4314 n->text = 0;
4315 labels = n;
4316 current_label = n;
4317}
4318
4319/* This is called when a value that is not an instruction is emitted. */
4320
4321void
4322m68k_flush_pending_output ()
4323{
4324 current_label = NULL;
4325}
4326
4327/* This is called at the end of the assembly, when the final value of
4328 the label is known. We warn if this is a text symbol aligned at an
4329 odd location. */
4330
4331void
4332m68k_frob_symbol (sym)
4333 symbolS *sym;
4334{
4335 if (S_GET_SEGMENT (sym) == reg_section
4336 && (int) S_GET_VALUE (sym) < 0)
4337 {
4338 S_SET_SEGMENT (sym, absolute_section);
4339 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4340 }
4341 else if ((S_GET_VALUE (sym) & 1) != 0)
4342 {
4343 struct label_line *l;
4344
4345 for (l = labels; l != NULL; l = l->next)
4346 {
4347 if (l->label == sym)
4348 {
4349 if (l->text)
4350 as_warn_where (l->file, l->line,
4351 _("text label `%s' aligned to odd boundary"),
4352 S_GET_NAME (sym));
4353 break;
4354 }
4355 }
4356 }
4357}
4358\f
4359/* This is called if we go in or out of MRI mode because of the .mri
4360 pseudo-op. */
4361
4362void
4363m68k_mri_mode_change (on)
4364 int on;
4365{
4366 if (on)
4367 {
4368 if (! flag_reg_prefix_optional)
4369 {
4370 flag_reg_prefix_optional = 1;
4371#ifdef REGISTER_PREFIX
4372 init_regtable ();
4373#endif
4374 }
4375 m68k_abspcadd = 1;
4376 if (! m68k_rel32_from_cmdline)
4377 m68k_rel32 = 0;
4378 }
4379 else
4380 {
4381 if (! reg_prefix_optional_seen)
4382 {
4383#ifdef REGISTER_PREFIX_OPTIONAL
4384 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4385#else
4386 flag_reg_prefix_optional = 0;
4387#endif
4388#ifdef REGISTER_PREFIX
4389 init_regtable ();
4390#endif
4391 }
4392 m68k_abspcadd = 0;
4393 if (! m68k_rel32_from_cmdline)
4394 m68k_rel32 = 1;
4395 }
4396}
4397
36759679 4398/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4399#define MAX_LITTLENUMS 6
4400
4401/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4402 of type TYPE, and store the appropriate bytes in *LITP. The number
4403 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4404 returned, or NULL on OK. */
4405
4406char *
4407md_atof (type, litP, sizeP)
4408 char type;
4409 char *litP;
4410 int *sizeP;
4411{
4412 int prec;
4413 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4414 LITTLENUM_TYPE *wordP;
4415 char *t;
4416
4417 switch (type)
4418 {
4419 case 'f':
4420 case 'F':
4421 case 's':
4422 case 'S':
4423 prec = 2;
4424 break;
4425
4426 case 'd':
4427 case 'D':
4428 case 'r':
4429 case 'R':
4430 prec = 4;
4431 break;
4432
4433 case 'x':
4434 case 'X':
4435 prec = 6;
4436 break;
4437
4438 case 'p':
4439 case 'P':
4440 prec = 6;
4441 break;
4442
4443 default:
4444 *sizeP = 0;
4445 return _("Bad call to MD_ATOF()");
4446 }
4447 t = atof_ieee (input_line_pointer, type, words);
4448 if (t)
4449 input_line_pointer = t;
4450
4451 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4452 for (wordP = words; prec--;)
4453 {
4454 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4455 litP += sizeof (LITTLENUM_TYPE);
4456 }
4457 return 0;
4458}
4459
4460void
4461md_number_to_chars (buf, val, n)
4462 char *buf;
4463 valueT val;
4464 int n;
4465{
4466 number_to_chars_bigendian (buf, val, n);
4467}
4468
94f592af
NC		 4469void
4470md_apply_fix3 (fixP, valP, seg)
252b5132 4471 fixS *fixP;
bbe8ef22 4472 valueT *valP;
94f592af 4473 segT seg ATTRIBUTE_UNUSED;
252b5132 4474{
bbe8ef22 4475 offsetT val = *valP;
252b5132
RH		 4476 addressT upper_limit;
4477 offsetT lower_limit;
4478
4479 /* This is unnecessary but it convinces the native rs6000 compiler
4480 to generate the code we want. */
4481 char *buf = fixP->fx_frag->fr_literal;
4482 buf += fixP->fx_where;
36759679 4483 /* End ibm compiler workaround. */
252b5132 4484
c801568a 4485 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132 4486
94f592af
NC		 4487 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4488 fixP->fx_done = 1;
4489
252b5132
RH		 4490#ifdef OBJ_ELF
4491 if (fixP->fx_addsy)
4492 {
4493 memset (buf, 0, fixP->fx_size);
36759679 4494 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4495
4496 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4497 && !S_IS_DEFINED (fixP->fx_addsy)
4498 && !S_IS_WEAK (fixP->fx_addsy))
4499 S_SET_WEAK (fixP->fx_addsy);
4500 return;
4501 }
4502#endif
4503
4504#ifdef BFD_ASSEMBLER
4505 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4506 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4507 return;
4508#endif
4509
4510 switch (fixP->fx_size)
4511 {
94f592af
NC		 4512 /* The cast to offsetT below are necessary to make code
4513 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4514 case 1:
4515 *buf++ = val;
4516 upper_limit = 0x7f;
4517 lower_limit = - (offsetT) 0x80;
4518 break;
4519 case 2:
4520 *buf++ = (val >> 8);
4521 *buf++ = val;
4522 upper_limit = 0x7fff;
4523 lower_limit = - (offsetT) 0x8000;
4524 break;
4525 case 4:
4526 *buf++ = (val >> 24);
4527 *buf++ = (val >> 16);
4528 *buf++ = (val >> 8);
4529 *buf++ = val;
4530 upper_limit = 0x7fffffff;
36759679 4531 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4532 break;
4533 default:
4534 BAD_CASE (fixP->fx_size);
4535 }
4536
4537 /* Fix up a negative reloc. */
4538 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4539 {
4540 fixP->fx_addsy = fixP->fx_subsy;
4541 fixP->fx_subsy = NULL;
4542 fixP->fx_tcbit = 1;
4543 }
4544
4545 /* For non-pc-relative values, it's conceivable we might get something
4546 like "0xff" for a byte field. So extend the upper part of the range
4547 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4548 so that we can do any range checking at all. */
4549 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4550 upper_limit = upper_limit * 2 + 1;
4551
4552 if ((addressT) val > upper_limit
4553 && (val > 0 || val < lower_limit))
4554 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4555
4556 /* A one byte PC-relative reloc means a short branch. We can't use
4557 a short branch with a value of 0 or -1, because those indicate
4558 different opcodes (branches with longer offsets). fixup_segment
4559 in write.c may have clobbered fx_pcrel, so we need to examine the
4560 reloc type. */
4561 if ((fixP->fx_pcrel
4562#ifdef BFD_ASSEMBLER
4563 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4564#endif
4565 )
4566 && fixP->fx_size == 1
4567 && (fixP->fx_addsy == NULL
4568 || S_IS_DEFINED (fixP->fx_addsy))
4569 && (val == 0 || val == -1))
4570 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4571}
4572
252b5132
RH		 4573/* *fragP has been relaxed to its final size, and now needs to have
4574 the bytes inside it modified to conform to the new size There is UGLY
4575 MAGIC here. ..
4576 */
4577static void
4578md_convert_frag_1 (fragP)
4579 register fragS *fragP;
4580{
4581 long disp;
252b5132
RH		 4582 fixS *fixP;
4583
4584 /* Address in object code of the displacement. */
4585 register int object_address = fragP->fr_fix + fragP->fr_address;
4586
4587 /* Address in gas core of the place to store the displacement. */
4588 /* This convinces the native rs6000 compiler to generate the code we
92774660 4589 want. */
252b5132
RH		 4590 register char *buffer_address = fragP->fr_literal;
4591 buffer_address += fragP->fr_fix;
36759679 4592 /* End ibm compiler workaround. */
252b5132
RH		 4593
4594 /* The displacement of the address, from current location. */
4595 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4596 disp = (disp + fragP->fr_offset) - object_address;
4597
252b5132
RH		 4598 switch (fragP->fr_subtype)
4599 {
151337e8
NC		 4600 case TAB (BRANCHBWL, BYTE):
4601 case TAB (BRABSJUNC, BYTE):
4602 case TAB (BRABSJCOND, BYTE):
4603 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4604 know (issbyte (disp));
4605 if (disp == 0)
b091f402
AM		 4606 as_bad_where (fragP->fr_file, fragP->fr_line,
4607 _("short branch with zero offset: use :w"));
151337e8 4608 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4609 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4610 fixP->fx_pcrel_adjust = -1;
252b5132 4611 break;
151337e8
NC		 4612 case TAB (BRANCHBWL, SHORT):
4613 case TAB (BRABSJUNC, SHORT):
4614 case TAB (BRABSJCOND, SHORT):
4615 case TAB (BRANCHBW, SHORT):
252b5132 4616 fragP->fr_opcode[1] = 0x00;
151337e8 4617 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4618 1, RELAX_RELOC_PC16);
151337e8
NC		 4619 fragP->fr_fix += 2;
4620 break;
4621 case TAB (BRANCHBWL, LONG):
4622 fragP->fr_opcode[1] = (char) 0xFF;
4623 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4624 1, RELAX_RELOC_PC32);
151337e8 4625 fragP->fr_fix += 4;
252b5132 4626 break;
151337e8
NC		 4627 case TAB (BRABSJUNC, LONG):
4628 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4629 {
36759679
NC		 4630 if (flag_keep_pcrel)
4631 as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4632 fragP->fr_opcode[0] = 0x4E;
36759679 4633 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4634 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4635 0, RELAX_RELOC_ABS32);
151337e8
NC		 4636 fragP->fr_fix += 4;
4637 }
4638 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4639 {
36759679
NC		 4640 if (flag_keep_pcrel)
4641 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
151337e8 4642 fragP->fr_opcode[0] = 0x4E;
36759679 4643 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4644 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4645 0, RELAX_RELOC_ABS32);
151337e8 4646 fragP->fr_fix += 4;
252b5132
RH		 4647 }
4648 else
4649 {
151337e8
NC		 4650 /* This cannot happen, because jbsr and jbra are the only two
4651 unconditional branches. */
4652 abort ();
252b5132
RH		 4653 }
4654 break;
151337e8 4655 case TAB (BRABSJCOND, LONG):
36759679
NC		 4656 if (flag_keep_pcrel)
4657 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4658
36759679
NC		 4659 /* Only Bcc 68000 instructions can come here
4660 Change bcc into b!cc/jmp absl long. */
4661 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4662 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4663
4664 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4665 different frag, in which case referring to them is a no-no.
92774660 4666 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4667 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4668 *buffer_address++ = (char) 0xf9;
36759679 4669 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4670 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4671 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4672 fragP->fr_fix += 4;
4673 break;
4674 case TAB (FBRANCH, SHORT):
4675 know ((fragP->fr_opcode[1] & 0x40) == 0);
4676 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4677 1, RELAX_RELOC_PC16);
151337e8
NC		 4678 fragP->fr_fix += 2;
4679 break;
4680 case TAB (FBRANCH, LONG):
36759679 4681 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4682 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4683 1, RELAX_RELOC_PC32);
252b5132 4684 fragP->fr_fix += 4;
252b5132 4685 break;
151337e8
NC		 4686 case TAB (DBCCLBR, SHORT):
4687 case TAB (DBCCABSJ, SHORT):
4688 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4689 1, RELAX_RELOC_PC16);
151337e8
NC		 4690 fragP->fr_fix += 2;
4691 break;
4692 case TAB (DBCCLBR, LONG):
36759679
NC		 4693 /* Only DBcc instructions can come here.
4694 Change dbcc into dbcc/bral.
4695 JF: these used to be fr_opcode[2-7], but that's wrong. */
4696 if (flag_keep_pcrel)
4697 as_fatal(_("Tried to convert DBcc to absolute jump"));
28e7409f 4698
36759679 4699 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4700 *buffer_address++ = 0x04;
36759679 4701 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4702 *buffer_address++ = 0x06;
151337e8
NC		 4703 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4704 *buffer_address++ = (char) 0xff;
252b5132 4705
36759679 4706 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4707 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4708 RELAX_RELOC_PC32);
252b5132 4709 fragP->fr_fix += 4;
252b5132 4710 break;
151337e8 4711 case TAB (DBCCABSJ, LONG):
36759679
NC		 4712 /* Only DBcc instructions can come here.
4713 Change dbcc into dbcc/jmp.
4714 JF: these used to be fr_opcode[2-7], but that's wrong. */
4715 if (flag_keep_pcrel)
4716 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4717
36759679 4718 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4719 *buffer_address++ = 0x04;
36759679 4720 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4721 *buffer_address++ = 0x06;
36759679 4722 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4723 *buffer_address++ = (char) 0xf9;
4724
36759679 4725 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4726 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4727 RELAX_RELOC_ABS32);
252b5132 4728 fragP->fr_fix += 4;
252b5132 4729 break;
151337e8 4730 case TAB (PCREL1632, SHORT):
252b5132
RH		 4731 fragP->fr_opcode[1] &= ~0x3F;
4732 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4733 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4734 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4735 fragP->fr_fix += 2;
252b5132 4736 break;
151337e8 4737 case TAB (PCREL1632, LONG):
252b5132
RH		 4738 /* Already set to mode 7.3; this indicates: PC indirect with
4739 suppressed index, 32-bit displacement. */
4740 *buffer_address++ = 0x01;
4741 *buffer_address++ = 0x70;
4742 fragP->fr_fix += 2;
151337e8 4743 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4744 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4745 fixP->fx_pcrel_adjust = 2;
4746 fragP->fr_fix += 4;
252b5132 4747 break;
252b5132 4748 case TAB (PCINDEX, BYTE):
252b5132
RH		 4749 assert (fragP->fr_fix >= 2);
4750 buffer_address[-2] &= ~1;
151337e8 4751 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4752 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4753 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4754 break;
4755 case TAB (PCINDEX, SHORT):
252b5132
RH		 4756 assert (fragP->fr_fix >= 2);
4757 buffer_address[-2] |= 0x1;
4758 buffer_address[-1] = 0x20;
4759 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4760 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4761 fixP->fx_pcrel_adjust = 2;
151337e8 4762 fragP->fr_fix += 2;
252b5132
RH		 4763 break;
4764 case TAB (PCINDEX, LONG):
252b5132
RH		 4765 assert (fragP->fr_fix >= 2);
4766 buffer_address[-2] |= 0x1;
4767 buffer_address[-1] = 0x30;
151337e8 4768 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4769 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4770 fixP->fx_pcrel_adjust = 2;
4771 fragP->fr_fix += 4;
4772 break;
4773 case TAB (ABSTOPCREL, SHORT):
4774 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4775 1, RELAX_RELOC_PC16);
151337e8
NC		 4776 fragP->fr_fix += 2;
4777 break;
4778 case TAB (ABSTOPCREL, LONG):
36759679
NC		 4779 if (flag_keep_pcrel)
4780 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4781 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4782 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4783 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4784 abort ();
4785 fragP->fr_opcode[1] &= ~0x3F;
4786 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4787 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4788 0, RELAX_RELOC_ABS32);
151337e8 4789 fragP->fr_fix += 4;
252b5132 4790 break;
252b5132
RH		 4791 }
4792}
4793
4794#ifndef BFD_ASSEMBLER
4795
4796void
4797md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4798 object_headers *headers ATTRIBUTE_UNUSED;
4799 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4800 fragS *fragP;
4801{
4802 md_convert_frag_1 (fragP);
4803}
4804
4805#else
4806
4807void
4808md_convert_frag (abfd, sec, fragP)
36823076
AS		 4809 bfd *abfd ATTRIBUTE_UNUSED;
4810 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4811 fragS *fragP;
4812{
4813 md_convert_frag_1 (fragP);
4814}
4815#endif
4816
4817/* Force truly undefined symbols to their maximum size, and generally set up
4818 the frag list to be relaxed
4819 */
4820int
4821md_estimate_size_before_relax (fragP, segment)
4822 register fragS *fragP;
4823 segT segment;
4824{
151337e8 4825 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4826 switch (fragP->fr_subtype)
4827 {
151337e8
NC		 4828 case TAB (BRANCHBWL, SZ_UNDEF):
4829 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4830 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4831 {
151337e8
NC		 4832 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4833 && relaxable_symbol (fragP->fr_symbol))
252b5132 4834 {
151337e8
NC		 4835 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4836 }
4837 else if (flag_short_refs)
4838 {
4839 /* Symbol is undefined and we want short ref. */
4840 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4841 }
4842 else
4843 {
151337e8
NC		 4844 /* Symbol is still undefined. Make it LONG. */
4845 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4846 }
4847 break;
151337e8 4848 }
252b5132 4849
151337e8 4850 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4851 {
151337e8
NC		 4852 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4853 && relaxable_symbol (fragP->fr_symbol))
252b5132 4854 {
151337e8 4855 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4856 }
4857 else
4858 {
151337e8
NC		 4859 /* Symbol is undefined and we don't have long branches. */
4860 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4861 }
4862 break;
151337e8 4863 }
252b5132 4864
151337e8 4865 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4866 case TAB (DBCCLBR, SZ_UNDEF):
4867 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4868 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4869 {
8ec6253e
NC		 4870 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4871 && relaxable_symbol (fragP->fr_symbol))
151337e8 4872 || flag_short_refs)
252b5132 4873 {
151337e8 4874 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4875 }
4876 else
4877 {
151337e8 4878 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4879 }
4880 break;
151337e8 4881 }
81d4177b 4882
252b5132
RH		 4883 case TAB (PCINDEX, SZ_UNDEF):
4884 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4885 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4886 {
4887 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4888 }
4889 else
4890 {
4891 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4892 }
4893 break;
4894
151337e8
NC		 4895 case TAB (ABSTOPCREL, SZ_UNDEF):
4896 {
4897 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4898 && relaxable_symbol (fragP->fr_symbol)))
4899 {
4900 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4901 }
4902 else
4903 {
4904 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4905 }
4906 break;
4907 }
4908
252b5132
RH		 4909 default:
4910 break;
4911 }
4912
151337e8 4913 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4914 switch (fragP->fr_subtype)
4915 {
151337e8
NC		 4916 case TAB (BRANCHBWL, BYTE):
4917 case TAB (BRABSJUNC, BYTE):
4918 case TAB (BRABSJCOND, BYTE):
4919 case TAB (BRANCHBW, BYTE):
252b5132 4920 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4921 case we force word mode. If the symbol is at the start of a
4922 frag, and it is the next frag with any data in it (usually
4923 this is just the next frag, but assembler listings may
4924 introduce empty frags), we must use word mode. */
4925 if (fragP->fr_symbol)
252b5132 4926 {
ac62c346 4927 fragS *sym_frag;
252b5132 4928
ac62c346
AM		 4929 sym_frag = symbol_get_frag (fragP->fr_symbol);
4930 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4931 {
ac62c346
AM		 4932 fragS *l;
4933
23b7f870 4934 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4935 if (l->fr_fix != 0)
4936 break;
4937 if (l == sym_frag)
4938 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4939 }
4940 }
4941 break;
4942 default:
4943 break;
4944 }
ac62c346 4945 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4946}
4947
4948#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4949/* the bit-field entries in the relocation_info struct plays hell
4950 with the byte-order problems of cross-assembly. So as a hack,
4951 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 4952 you there. -KWK */
252b5132
RH		 4953/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4954 are symbolnum, most sig. byte first. Last byte is broken up with
4955 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4956 nibble as nuthin. (on Sun 3 at least) */
4957/* Translate the internal relocation information into target-specific
92774660 4958 format. */
252b5132
RH		 4959#ifdef comment
4960void
4961md_ri_to_chars (the_bytes, ri)
4962 char *the_bytes;
4963 struct reloc_info_generic *ri;
4964{
36759679 4965 /* This is easy. */
252b5132 4966 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 4967 /* Now the fun stuff. */
252b5132 4968 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 4969 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4970 the_bytes[6] = ri->r_symbolnum & 0x0ff;
252b5132
RH		 4971 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4972 ((ri->r_extern << 4) & 0x10));
4973}
4974
36759679 4975#endif
252b5132
RH		 4976
4977#ifndef BFD_ASSEMBLER
4978void
4979tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4980 char *where;
4981 fixS *fixP;
4982 relax_addressT segment_address_in_file;
4983{
4984 /*
4985 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4986 * Out: GNU LD relocation length code: 0, 1, or 2.
4987 */
4988
5a38dc70 4989 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
252b5132
RH		 4990 long r_symbolnum;
4991
4992 know (fixP->fx_addsy != NULL);
4993
4994 md_number_to_chars (where,
4995 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4996 4);
4997
4998 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4999 ? S_GET_TYPE (fixP->fx_addsy)
5000 : fixP->fx_addsy->sy_number);
5001
5002 where[4] = (r_symbolnum >> 16) & 0x0ff;
5003 where[5] = (r_symbolnum >> 8) & 0x0ff;
5004 where[6] = r_symbolnum & 0x0ff;
5005 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
5006 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
5007}
5008#endif
5009
5010#endif /* OBJ_AOUT or OBJ_BOUT */
5011
5012#ifndef WORKING_DOT_WORD
5a38dc70
AM		 5013const int md_short_jump_size = 4;
5014const int md_long_jump_size = 6;
252b5132
RH		 5015
5016void
5017md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5018 char *ptr;
5019 addressT from_addr, to_addr;
36823076
AS		 5020 fragS *frag ATTRIBUTE_UNUSED;
5021 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 5022{
5023 valueT offset;
5024
5025 offset = to_addr - (from_addr + 2);
5026
5027 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5028 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5029}
5030
5031void
5032md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5033 char *ptr;
5034 addressT from_addr, to_addr;
5035 fragS *frag;
5036 symbolS *to_symbol;
5037{
5038 valueT offset;
5039
5040 if (!HAVE_LONG_BRANCH(current_architecture))
5041 {
36759679
NC		 5042 if (flag_keep_pcrel)
5043 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5044 offset = to_addr - S_GET_VALUE (to_symbol);
5045 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5046 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5047 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5048 0, NO_RELOC);
5049 }
5050 else
5051 {
5052 offset = to_addr - (from_addr + 2);
5053 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5054 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5055 }
5056}
5057
5058#endif
5059
5060/* Different values of OK tell what its OK to return. Things that
5061 aren't OK are an error (what a shock, no?)
5062
5063 0: Everything is OK
3e602632
NC		 5064 10: Absolute 1:8 only
5065 20: Absolute 0:7 only
5066 30: absolute 0:15 only
5067 40: Absolute 0:31 only
5068 50: absolute 0:127 only
252b5132 5069 55: absolute -64:63 only
3e602632
NC		 5070 60: absolute -128:127 only
5071 70: absolute 0:4095 only
5072 80: absolute -1, 1:7 only
5073 90: No bignums. */
252b5132
RH		 5074
5075static int
5076get_num (exp, ok)
5077 struct m68k_exp *exp;
5078 int ok;
5079{
5080 if (exp->exp.X_op == O_absent)
5081 {
36759679 5082 /* Do the same thing the VAX asm does. */
252b5132
RH		 5083 op (exp) = O_constant;
5084 adds (exp) = 0;
5085 subs (exp) = 0;
5086 offs (exp) = 0;
5087 if (ok == 10)
5088 {
5089 as_warn (_("expression out of range: defaulting to 1"));
5090 offs (exp) = 1;
5091 }
5092 }
5093 else if (exp->exp.X_op == O_constant)
5094 {
5095 switch (ok)
5096 {
5097 case 10:
5098 if (offs (exp) < 1 || offs (exp) > 8)
5099 {
5100 as_warn (_("expression out of range: defaulting to 1"));
5101 offs (exp) = 1;
5102 }
5103 break;
5104 case 20:
5105 if (offs (exp) < 0 || offs (exp) > 7)
5106 goto outrange;
5107 break;
5108 case 30:
5109 if (offs (exp) < 0 || offs (exp) > 15)
5110 goto outrange;
5111 break;
5112 case 40:
5113 if (offs (exp) < 0 || offs (exp) > 32)
5114 goto outrange;
5115 break;
5116 case 50:
5117 if (offs (exp) < 0 || offs (exp) > 127)
5118 goto outrange;
5119 break;
5120 case 55:
5121 if (offs (exp) < -64 || offs (exp) > 63)
5122 goto outrange;
5123 break;
5124 case 60:
5125 if (offs (exp) < -128 || offs (exp) > 127)
5126 goto outrange;
5127 break;
5128 case 70:
5129 if (offs (exp) < 0 || offs (exp) > 4095)
5130 {
5131 outrange:
5132 as_warn (_("expression out of range: defaulting to 0"));
5133 offs (exp) = 0;
5134 }
5135 break;
3e602632
NC		 5136 case 80:
5137 if (offs (exp) < -1
5138 || offs (exp) > 7
5139 || offs (exp) == 0)
5140 {
5141 as_warn (_("expression out of range: defaulting to 1"));
5142 offs (exp) = 1;
5143 }
5144 break;
252b5132
RH		 5145 default:
5146 break;
5147 }
5148 }
5149 else if (exp->exp.X_op == O_big)
5150 {
36759679 5151 if (offs (exp) <= 0 /* flonum. */
3e602632 5152 && (ok == 90 /* no bignums */
36759679 5153 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5154 /* If we have a flonum zero, a zero integer should
5155 do as well (e.g., in moveq). */
5156 && generic_floating_point_number.exponent == 0
5157 && generic_floating_point_number.low[0] == 0)))
5158 {
36759679 5159 /* HACK! Turn it into a long. */
252b5132
RH		 5160 LITTLENUM_TYPE words[6];
5161
36759679 5162 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5163 op (exp) = O_constant;
5164 adds (exp) = 0;
5165 subs (exp) = 0;
5166 offs (exp) = words[1] | (words[0] << 16);
5167 }
5168 else if (ok != 0)
5169 {
5170 op (exp) = O_constant;
5171 adds (exp) = 0;
5172 subs (exp) = 0;
5173 offs (exp) = (ok == 10) ? 1 : 0;
5174 as_warn (_("Can't deal with expression; defaulting to %ld"),
5175 offs (exp));
5176 }
5177 }
5178 else
5179 {
3e602632 5180 if (ok >= 10 && ok <= 80)
252b5132
RH		 5181 {
5182 op (exp) = O_constant;
5183 adds (exp) = 0;
5184 subs (exp) = 0;
5185 offs (exp) = (ok == 10) ? 1 : 0;
5186 as_warn (_("Can't deal with expression; defaulting to %ld"),
5187 offs (exp));
5188 }
5189 }
5190
5191 if (exp->size != SIZE_UNSPEC)
5192 {
5193 switch (exp->size)
5194 {
5195 case SIZE_UNSPEC:
5196 case SIZE_LONG:
5197 break;
5198 case SIZE_BYTE:
5199 if (!isbyte (offs (exp)))
5200 as_warn (_("expression doesn't fit in BYTE"));
5201 break;
5202 case SIZE_WORD:
5203 if (!isword (offs (exp)))
5204 as_warn (_("expression doesn't fit in WORD"));
5205 break;
5206 }
5207 }
5208
5209 return offs (exp);
5210}
5211
5212/* These are the back-ends for the various machine dependent pseudo-ops. */
5213
5214static void
5215s_data1 (ignore)
36823076 5216 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5217{
5218 subseg_set (data_section, 1);
5219 demand_empty_rest_of_line ();
5220}
5221
5222static void
5223s_data2 (ignore)
36823076 5224 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5225{
5226 subseg_set (data_section, 2);
5227 demand_empty_rest_of_line ();
5228}
5229
5230static void
5231s_bss (ignore)
36823076 5232 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5233{
5234 /* We don't support putting frags in the BSS segment, we fake it
5235 by marking in_bss, then looking at s_skip for clues. */
5236
5237 subseg_set (bss_section, 0);
5238 demand_empty_rest_of_line ();
5239}
5240
5241static void
5242s_even (ignore)
36823076 5243 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5244{
5245 register int temp;
5246 register long temp_fill;
5247
5248 temp = 1; /* JF should be 2? */
5249 temp_fill = get_absolute_expression ();
92774660 5250 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5251 frag_align (temp, (int) temp_fill, 0);
5252 demand_empty_rest_of_line ();
5253 record_alignment (now_seg, temp);
5254}
5255
5256static void
5257s_proc (ignore)
36823076 5258 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5259{
5260 demand_empty_rest_of_line ();
5261}
5262\f
5263/* Pseudo-ops handled for MRI compatibility. */
5264
5265/* This function returns non-zero if the argument is a conditional
5266 pseudo-op. This is called when checking whether a pending
5267 alignment is needed. */
5268
5269int
5270m68k_conditional_pseudoop (pop)
5271 pseudo_typeS *pop;
5272{
5273 return (pop->poc_handler == s_mri_if
5274 || pop->poc_handler == s_mri_else);
5275}
5276
5277/* Handle an MRI style chip specification. */
5278
5279static void
5280mri_chip ()
5281{
5282 char *s;
5283 char c;
5284 int i;
5285
5286 s = input_line_pointer;
5287 /* We can't use get_symbol_end since the processor names are not proper
5288 symbols. */
5289 while (is_part_of_name (c = *input_line_pointer++))
5290 ;
5291 *--input_line_pointer = 0;
5292 for (i = 0; i < n_archs; i++)
5293 if (strcasecmp (s, archs[i].name) == 0)
5294 break;
5295 if (i >= n_archs)
5296 {
5297 as_bad (_("%s: unrecognized processor name"), s);
5298 *input_line_pointer = c;
5299 ignore_rest_of_line ();
5300 return;
5301 }
5302 *input_line_pointer = c;
5303
5304 if (*input_line_pointer == '/')
5305 current_architecture = 0;
5306 else
5307 current_architecture &= m68881 | m68851;
5308 current_architecture |= archs[i].arch;
5309
5310 while (*input_line_pointer == '/')
5311 {
5312 ++input_line_pointer;
5313 s = input_line_pointer;
5314 /* We can't use get_symbol_end since the processor names are not
5315 proper symbols. */
5316 while (is_part_of_name (c = *input_line_pointer++))
5317 ;
5318 *--input_line_pointer = 0;
5319 if (strcmp (s, "68881") == 0)
5320 current_architecture |= m68881;
5321 else if (strcmp (s, "68851") == 0)
5322 current_architecture |= m68851;
5323 *input_line_pointer = c;
5324 }
5325
5326 /* Update info about available control registers. */
5327 select_control_regs ();
5328}
5329
5330/* The MRI CHIP pseudo-op. */
5331
5332static void
5333s_chip (ignore)
36823076 5334 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5335{
5336 char *stop = NULL;
5337 char stopc;
5338
5339 if (flag_mri)
5340 stop = mri_comment_field (&stopc);
5341 mri_chip ();
5342 if (flag_mri)
5343 mri_comment_end (stop, stopc);
5344 demand_empty_rest_of_line ();
5345}
5346
5347/* The MRI FOPT pseudo-op. */
5348
5349static void
5350s_fopt (ignore)
36823076 5351 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5352{
5353 SKIP_WHITESPACE ();
5354
5355 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5356 {
5357 int temp;
5358
5359 input_line_pointer += 3;
5360 temp = get_absolute_expression ();
5361 if (temp < 0 || temp > 7)
5362 as_bad (_("bad coprocessor id"));
5363 else
5364 m68k_float_copnum = COP0 + temp;
5365 }
5366 else
5367 {
5368 as_bad (_("unrecognized fopt option"));
5369 ignore_rest_of_line ();
5370 return;
5371 }
5372
5373 demand_empty_rest_of_line ();
5374}
5375
5376/* The structure used to handle the MRI OPT pseudo-op. */
5377
5378struct opt_action
5379{
5380 /* The name of the option. */
5381 const char *name;
5382
5383 /* If this is not NULL, just call this function. The first argument
5384 is the ARG field of this structure, the second argument is
5385 whether the option was negated. */
5386 void (*pfn) PARAMS ((int arg, int on));
5387
5388 /* If this is not NULL, and the PFN field is NULL, set the variable
5389 this points to. Set it to the ARG field if the option was not
5390 negated, and the NOTARG field otherwise. */
5391 int *pvar;
5392
5393 /* The value to pass to PFN or to assign to *PVAR. */
5394 int arg;
5395
5396 /* The value to assign to *PVAR if the option is negated. If PFN is
5397 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5398 the option may not be negated. */
5399 int notarg;
5400};
5401
5402/* The table used to handle the MRI OPT pseudo-op. */
5403
5404static void skip_to_comma PARAMS ((int, int));
5405static void opt_nest PARAMS ((int, int));
5406static void opt_chip PARAMS ((int, int));
5407static void opt_list PARAMS ((int, int));
5408static void opt_list_symbols PARAMS ((int, int));
5409
5410static const struct opt_action opt_table[] =
5411{
5412 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5413
5414 /* We do relaxing, so there is little use for these options. */
5415 { "b", 0, 0, 0, 0 },
5416 { "brs", 0, 0, 0, 0 },
5417 { "brb", 0, 0, 0, 0 },
5418 { "brl", 0, 0, 0, 0 },
5419 { "brw", 0, 0, 0, 0 },
5420
5421 { "c", 0, 0, 0, 0 },
5422 { "cex", 0, 0, 0, 0 },
5423 { "case", 0, &symbols_case_sensitive, 1, 0 },
5424 { "cl", 0, 0, 0, 0 },
5425 { "cre", 0, 0, 0, 0 },
5426 { "d", 0, &flag_keep_locals, 1, 0 },
5427 { "e", 0, 0, 0, 0 },
5428 { "f", 0, &flag_short_refs, 1, 0 },
5429 { "frs", 0, &flag_short_refs, 1, 0 },
5430 { "frl", 0, &flag_short_refs, 0, 1 },
5431 { "g", 0, 0, 0, 0 },
5432 { "i", 0, 0, 0, 0 },
5433 { "m", 0, 0, 0, 0 },
5434 { "mex", 0, 0, 0, 0 },
5435 { "mc", 0, 0, 0, 0 },
5436 { "md", 0, 0, 0, 0 },
5437 { "nest", opt_nest, 0, 0, 0 },
5438 { "next", skip_to_comma, 0, 0, 0 },
5439 { "o", 0, 0, 0, 0 },
5440 { "old", 0, 0, 0, 0 },
5441 { "op", skip_to_comma, 0, 0, 0 },
5442 { "pco", 0, 0, 0, 0 },
5443 { "p", opt_chip, 0, 0, 0 },
5444 { "pcr", 0, 0, 0, 0 },
5445 { "pcs", 0, 0, 0, 0 },
5446 { "r", 0, 0, 0, 0 },
5447 { "quick", 0, &m68k_quick, 1, 0 },
5448 { "rel32", 0, &m68k_rel32, 1, 0 },
5449 { "s", opt_list, 0, 0, 0 },
5450 { "t", opt_list_symbols, 0, 0, 0 },
5451 { "w", 0, &flag_no_warnings, 0, 1 },
5452 { "x", 0, 0, 0, 0 }
5453};
5454
8fce3f5e 5455#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5456
5457/* The MRI OPT pseudo-op. */
5458
5459static void
5460s_opt (ignore)
36823076 5461 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5462{
5463 do
5464 {
5465 int t;
5466 char *s;
5467 char c;
5468 int i;
5469 const struct opt_action *o;
5470
5471 SKIP_WHITESPACE ();
5472
5473 t = 1;
5474 if (*input_line_pointer == '-')
5475 {
5476 ++input_line_pointer;
5477 t = 0;
5478 }
5479 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5480 {
5481 input_line_pointer += 2;
5482 t = 0;
5483 }
5484
5485 s = input_line_pointer;
5486 c = get_symbol_end ();
5487
5488 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5489 {
5490 if (strcasecmp (s, o->name) == 0)
5491 {
5492 if (o->pfn)
5493 {
5494 /* Restore input_line_pointer now in case the option
5495 takes arguments. */
5496 *input_line_pointer = c;
5497 (*o->pfn) (o->arg, t);
5498 }
5499 else if (o->pvar != NULL)
5500 {
5501 if (! t && o->arg == o->notarg)
5502 as_bad (_("option `%s' may not be negated"), s);
5503 *input_line_pointer = c;
5504 *o->pvar = t ? o->arg : o->notarg;
5505 }
5506 else
5507 *input_line_pointer = c;
5508 break;
5509 }
5510 }
5511 if (i >= OPTCOUNT)
5512 {
5513 as_bad (_("option `%s' not recognized"), s);
5514 *input_line_pointer = c;
5515 }
5516 }
5517 while (*input_line_pointer++ == ',');
5518
5519 /* Move back to terminating character. */
5520 --input_line_pointer;
5521 demand_empty_rest_of_line ();
5522}
5523
5524/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5525 not support and which take arguments. */
252b5132
RH		 5526
5527static void
5528skip_to_comma (arg, on)
36823076
AS		 5529 int arg ATTRIBUTE_UNUSED;
5530 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5531{
5532 while (*input_line_pointer != ','
5533 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5534 ++input_line_pointer;
5535}
5536
5537/* Handle the OPT NEST=depth option. */
5538
5539static void
5540opt_nest (arg, on)
36823076
AS		 5541 int arg ATTRIBUTE_UNUSED;
5542 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5543{
5544 if (*input_line_pointer != '=')
5545 {
5546 as_bad (_("bad format of OPT NEST=depth"));
5547 return;
5548 }
5549
5550 ++input_line_pointer;
5551 max_macro_nest = get_absolute_expression ();
5552}
5553
5554/* Handle the OPT P=chip option. */
5555
5556static void
5557opt_chip (arg, on)
36823076
AS		 5558 int arg ATTRIBUTE_UNUSED;
5559 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5560{
5561 if (*input_line_pointer != '=')
5562 {
5563 /* This is just OPT P, which we do not support. */
5564 return;
5565 }
5566
5567 ++input_line_pointer;
5568 mri_chip ();
5569}
5570
5571/* Handle the OPT S option. */
5572
5573static void
5574opt_list (arg, on)
36823076 5575 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5576 int on;
5577{
5578 listing_list (on);
5579}
5580
5581/* Handle the OPT T option. */
5582
5583static void
5584opt_list_symbols (arg, on)
36823076 5585 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5586 int on;
5587{
5588 if (on)
5589 listing |= LISTING_SYMBOLS;
5590 else
8a104df9 5591 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5592}
5593
5594/* Handle the MRI REG pseudo-op. */
5595
5596static void
5597s_reg (ignore)
36823076 5598 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5599{
5600 char *s;
5601 int c;
5602 struct m68k_op rop;
5603 int mask;
5604 char *stop = NULL;
5605 char stopc;
5606
5607 if (line_label == NULL)
5608 {
5609 as_bad (_("missing label"));
5610 ignore_rest_of_line ();
5611 return;
5612 }
5613
5614 if (flag_mri)
5615 stop = mri_comment_field (&stopc);
5616
5617 SKIP_WHITESPACE ();
5618
5619 s = input_line_pointer;
3882b010 5620 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5621#ifdef REGISTER_PREFIX
5622 || *input_line_pointer == REGISTER_PREFIX
5623#endif
5624 || *input_line_pointer == '/'
5625 || *input_line_pointer == '-')
5626 ++input_line_pointer;
5627 c = *input_line_pointer;
5628 *input_line_pointer = '\0';
5629
5630 if (m68k_ip_op (s, &rop) != 0)
5631 {
5632 if (rop.error == NULL)
5633 as_bad (_("bad register list"));
5634 else
5635 as_bad (_("bad register list: %s"), rop.error);
5636 *input_line_pointer = c;
5637 ignore_rest_of_line ();
5638 return;
5639 }
5640
5641 *input_line_pointer = c;
5642
5643 if (rop.mode == REGLST)
5644 mask = rop.mask;
5645 else if (rop.mode == DREG)
5646 mask = 1 << (rop.reg - DATA0);
5647 else if (rop.mode == AREG)
5648 mask = 1 << (rop.reg - ADDR0 + 8);
5649 else if (rop.mode == FPREG)
5650 mask = 1 << (rop.reg - FP0 + 16);
5651 else if (rop.mode == CONTROL
5652 && rop.reg == FPI)
5653 mask = 1 << 24;
5654 else if (rop.mode == CONTROL
5655 && rop.reg == FPS)
5656 mask = 1 << 25;
5657 else if (rop.mode == CONTROL
5658 && rop.reg == FPC)
5659 mask = 1 << 26;
5660 else
5661 {
5662 as_bad (_("bad register list"));
5663 ignore_rest_of_line ();
5664 return;
5665 }
5666
5667 S_SET_SEGMENT (line_label, reg_section);
5668 S_SET_VALUE (line_label, ~mask);
49309057 5669 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5670
5671 if (flag_mri)
5672 mri_comment_end (stop, stopc);
5673
5674 demand_empty_rest_of_line ();
5675}
5676
5677/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5678
5679struct save_opts
5680{
5681 struct save_opts *next;
5682 int abspcadd;
5683 int symbols_case_sensitive;
5684 int keep_locals;
5685 int short_refs;
5686 int architecture;
5687 int quick;
5688 int rel32;
5689 int listing;
5690 int no_warnings;
5691 /* FIXME: We don't save OPT S. */
5692};
5693
5694/* This variable holds the stack of saved options. */
5695
5696static struct save_opts *save_stack;
5697
5698/* The MRI SAVE pseudo-op. */
5699
5700static void
5701s_save (ignore)
36823076 5702 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5703{
5704 struct save_opts *s;
5705
5706 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5707 s->abspcadd = m68k_abspcadd;
5708 s->symbols_case_sensitive = symbols_case_sensitive;
5709 s->keep_locals = flag_keep_locals;
5710 s->short_refs = flag_short_refs;
5711 s->architecture = current_architecture;
5712 s->quick = m68k_quick;
5713 s->rel32 = m68k_rel32;
5714 s->listing = listing;
5715 s->no_warnings = flag_no_warnings;
5716
5717 s->next = save_stack;
5718 save_stack = s;
5719
5720 demand_empty_rest_of_line ();
5721}
5722
5723/* The MRI RESTORE pseudo-op. */
5724
5725static void
5726s_restore (ignore)
36823076 5727 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5728{
5729 struct save_opts *s;
5730
5731 if (save_stack == NULL)
5732 {
5733 as_bad (_("restore without save"));
5734 ignore_rest_of_line ();
5735 return;
5736 }
5737
5738 s = save_stack;
5739 save_stack = s->next;
5740
5741 m68k_abspcadd = s->abspcadd;
5742 symbols_case_sensitive = s->symbols_case_sensitive;
5743 flag_keep_locals = s->keep_locals;
5744 flag_short_refs = s->short_refs;
5745 current_architecture = s->architecture;
5746 m68k_quick = s->quick;
5747 m68k_rel32 = s->rel32;
5748 listing = s->listing;
5749 flag_no_warnings = s->no_warnings;
5750
5751 free (s);
5752
5753 demand_empty_rest_of_line ();
5754}
5755
5756/* Types of MRI structured control directives. */
5757
5758enum mri_control_type
5759{
5760 mri_for,
5761 mri_if,
5762 mri_repeat,
5763 mri_while
5764};
5765
5766/* This structure is used to stack the MRI structured control
5767 directives. */
5768
5769struct mri_control_info
5770{
5771 /* The directive within which this one is enclosed. */
5772 struct mri_control_info *outer;
5773
5774 /* The type of directive. */
5775 enum mri_control_type type;
5776
5777 /* Whether an ELSE has been in an IF. */
5778 int else_seen;
5779
5780 /* The add or sub statement at the end of a FOR. */
5781 char *incr;
5782
5783 /* The label of the top of a FOR or REPEAT loop. */
5784 char *top;
5785
5786 /* The label to jump to for the next iteration, or the else
5787 expression of a conditional. */
5788 char *next;
5789
5790 /* The label to jump to to break out of the loop, or the label past
5791 the end of a conditional. */
5792 char *bottom;
5793};
5794
5795/* The stack of MRI structured control directives. */
5796
5797static struct mri_control_info *mri_control_stack;
5798
5799/* The current MRI structured control directive index number, used to
5800 generate label names. */
5801
5802static int mri_control_index;
5803
5804/* Some function prototypes. */
5805
5806static void mri_assemble PARAMS ((char *));
5807static char *mri_control_label PARAMS ((void));
5808static struct mri_control_info *push_mri_control
5809 PARAMS ((enum mri_control_type));
5810static void pop_mri_control PARAMS ((void));
5811static int parse_mri_condition PARAMS ((int *));
5812static int parse_mri_control_operand
5813 PARAMS ((int *, char **, char **, char **, char **));
5814static int swap_mri_condition PARAMS ((int));
5815static int reverse_mri_condition PARAMS ((int));
5816static void build_mri_control_operand
5817 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5818 const char *, int));
5819static void parse_mri_control_expression
5820 PARAMS ((char *, int, const char *, const char *, int));
5821
5822/* Assemble an instruction for an MRI structured control directive. */
5823
5824static void
5825mri_assemble (str)
5826 char *str;
5827{
5828 char *s;
5829
5830 /* md_assemble expects the opcode to be in lower case. */
5831 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5832 *s = TOLOWER (*s);
252b5132
RH		 5833
5834 md_assemble (str);
5835}
5836
5837/* Generate a new MRI label structured control directive label name. */
5838
5839static char *
5840mri_control_label ()
5841{
5842 char *n;
5843
5844 n = (char *) xmalloc (20);
5845 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5846 ++mri_control_index;
5847 return n;
5848}
5849
5850/* Create a new MRI structured control directive. */
5851
5852static struct mri_control_info *
5853push_mri_control (type)
5854 enum mri_control_type type;
5855{
5856 struct mri_control_info *n;
5857
5858 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5859
5860 n->type = type;
5861 n->else_seen = 0;
5862 if (type == mri_if || type == mri_while)
5863 n->top = NULL;
5864 else
5865 n->top = mri_control_label ();
5866 n->next = mri_control_label ();
5867 n->bottom = mri_control_label ();
5868
5869 n->outer = mri_control_stack;
5870 mri_control_stack = n;
5871
5872 return n;
5873}
5874
5875/* Pop off the stack of MRI structured control directives. */
5876
5877static void
5878pop_mri_control ()
5879{
5880 struct mri_control_info *n;
5881
5882 n = mri_control_stack;
5883 mri_control_stack = n->outer;
5884 if (n->top != NULL)
5885 free (n->top);
5886 free (n->next);
5887 free (n->bottom);
5888 free (n);
5889}
5890
5891/* Recognize a condition code in an MRI structured control expression. */
5892
5893static int
5894parse_mri_condition (pcc)
5895 int *pcc;
5896{
5897 char c1, c2;
5898
5899 know (*input_line_pointer == '<');
5900
5901 ++input_line_pointer;
5902 c1 = *input_line_pointer++;
5903 c2 = *input_line_pointer++;
5904
5905 if (*input_line_pointer != '>')
5906 {
5907 as_bad (_("syntax error in structured control directive"));
5908 return 0;
5909 }
5910
5911 ++input_line_pointer;
5912 SKIP_WHITESPACE ();
5913
3882b010
L		 5914 c1 = TOLOWER (c1);
5915 c2 = TOLOWER (c2);
252b5132
RH		 5916
5917 *pcc = (c1 << 8) | c2;
5918
5919 return 1;
5920}
5921
5922/* Parse a single operand in an MRI structured control expression. */
5923
5924static int
5925parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5926 int *pcc;
5927 char **leftstart;
5928 char **leftstop;
5929 char **rightstart;
5930 char **rightstop;
5931{
5932 char *s;
5933
5934 SKIP_WHITESPACE ();
5935
5936 *pcc = -1;
5937 *leftstart = NULL;
5938 *leftstop = NULL;
5939 *rightstart = NULL;
5940 *rightstop = NULL;
5941
5942 if (*input_line_pointer == '<')
5943 {
5944 /* It's just a condition code. */
5945 return parse_mri_condition (pcc);
5946 }
5947
5948 /* Look ahead for the condition code. */
5949 for (s = input_line_pointer; *s != '\0'; ++s)
5950 {
5951 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5952 break;
5953 }
5954 if (*s == '\0')
5955 {
5956 as_bad (_("missing condition code in structured control directive"));
5957 return 0;
5958 }
5959
5960 *leftstart = input_line_pointer;
5961 *leftstop = s;
5962 if (*leftstop > *leftstart
5963 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5964 --*leftstop;
5965
5966 input_line_pointer = s;
5967 if (! parse_mri_condition (pcc))
5968 return 0;
5969
5970 /* Look ahead for AND or OR or end of line. */
5971 for (s = input_line_pointer; *s != '\0'; ++s)
5972 {
e1f44d10
NC		 5973 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5974 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5975 ^^^ ^^ */
8a104df9
KH		 5976 if ((s == input_line_pointer
5977 || *(s-1) == ' '
5978 || *(s-1) == '\t')
5979 && ((strncasecmp (s, "AND", 3) == 0
5980 && (s[3] == '.' || ! is_part_of_name (s[3])))
5981 || (strncasecmp (s, "OR", 2) == 0
5982 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5983 break;
252b5132
RH		 5984 }
5985
5986 *rightstart = input_line_pointer;
5987 *rightstop = s;
5988 if (*rightstop > *rightstart
5989 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5990 --*rightstop;
5991
5992 input_line_pointer = s;
5993
5994 return 1;
5995}
5996
5997#define MCC(b1, b2) (((b1) << 8) | (b2))
5998
5999/* Swap the sense of a condition. This changes the condition so that
6000 it generates the same result when the operands are swapped. */
6001
6002static int
6003swap_mri_condition (cc)
6004 int cc;
6005{
6006 switch (cc)
6007 {
6008 case MCC ('h', 'i'): return MCC ('c', 's');
6009 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6010 /* <HS> is an alias for <CC>. */
e1f44d10 6011 case MCC ('h', 's'):
252b5132 6012 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6013 /* <LO> is an alias for <CS>. */
e1f44d10 6014 case MCC ('l', 'o'):
252b5132
RH		 6015 case MCC ('c', 's'): return MCC ('h', 'i');
6016 case MCC ('p', 'l'): return MCC ('m', 'i');
6017 case MCC ('m', 'i'): return MCC ('p', 'l');
6018 case MCC ('g', 'e'): return MCC ('l', 'e');
6019 case MCC ('l', 't'): return MCC ('g', 't');
6020 case MCC ('g', 't'): return MCC ('l', 't');
6021 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6022 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6023 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6024 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6025 case MCC ('v', 'c'):
6026 case MCC ('v', 's'):
6027 default :
6028 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6029 (char) (cc >> 8), (char) (cc));
6030 break;
252b5132
RH		 6031 }
6032 return cc;
6033}
6034
6035/* Reverse the sense of a condition. */
6036
6037static int
6038reverse_mri_condition (cc)
6039 int cc;
6040{
6041 switch (cc)
6042 {
6043 case MCC ('h', 'i'): return MCC ('l', 's');
6044 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6045 /* <HS> is an alias for <CC> */
6046 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6047 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6048 /* <LO> is an alias for <CS> */
6049 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6050 case MCC ('c', 's'): return MCC ('c', 'c');
6051 case MCC ('n', 'e'): return MCC ('e', 'q');
6052 case MCC ('e', 'q'): return MCC ('n', 'e');
6053 case MCC ('v', 'c'): return MCC ('v', 's');
6054 case MCC ('v', 's'): return MCC ('v', 'c');
6055 case MCC ('p', 'l'): return MCC ('m', 'i');
6056 case MCC ('m', 'i'): return MCC ('p', 'l');
6057 case MCC ('g', 'e'): return MCC ('l', 't');
6058 case MCC ('l', 't'): return MCC ('g', 'e');
6059 case MCC ('g', 't'): return MCC ('l', 'e');
6060 case MCC ('l', 'e'): return MCC ('g', 't');
6061 }
6062 return cc;
6063}
6064
6065/* Build an MRI structured control expression. This generates test
6066 and branch instructions. It goes to TRUELAB if the condition is
6067 true, and to FALSELAB if the condition is false. Exactly one of
6068 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6069 is the size qualifier for the expression. EXTENT is the size to
6070 use for the branch. */
6071
6072static void
6073build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6074 rightstop, truelab, falselab, extent)
6075 int qual;
6076 int cc;
6077 char *leftstart;
6078 char *leftstop;
6079 char *rightstart;
6080 char *rightstop;
6081 const char *truelab;
6082 const char *falselab;
6083 int extent;
6084{
6085 char *buf;
6086 char *s;
6087
6088 if (leftstart != NULL)
6089 {
6090 struct m68k_op leftop, rightop;
6091 char c;
6092
6093 /* Swap the compare operands, if necessary, to produce a legal
6094 m68k compare instruction. Comparing a register operand with
6095 a non-register operand requires the register to be on the
6096 right (cmp, cmpa). Comparing an immediate value with
6097 anything requires the immediate value to be on the left
6098 (cmpi). */
6099
6100 c = *leftstop;
6101 *leftstop = '\0';
6102 (void) m68k_ip_op (leftstart, &leftop);
6103 *leftstop = c;
6104
6105 c = *rightstop;
6106 *rightstop = '\0';
6107 (void) m68k_ip_op (rightstart, &rightop);
6108 *rightstop = c;
6109
6110 if (rightop.mode == IMMED
6111 || ((leftop.mode == DREG || leftop.mode == AREG)
6112 && (rightop.mode != DREG && rightop.mode != AREG)))
6113 {
6114 char *temp;
6115
e1f44d10
NC		 6116 /* Correct conditional handling:
6117 if #1 <lt> d0 then ;means if (1 < d0)
6118 ...
6119 endi
6120
6121 should assemble to:
6122
6123 cmp #1,d0 if we do *not* swap the operands
6124 bgt true we need the swapped condition!
6125 ble false
6126 true:
6127 ...
6128 false:
6129 */
252b5132
RH		 6130 temp = leftstart;
6131 leftstart = rightstart;
6132 rightstart = temp;
6133 temp = leftstop;
6134 leftstop = rightstop;
6135 rightstop = temp;
8a104df9
KH		 6136 }
6137 else
6138 {
e1f44d10 6139 cc = swap_mri_condition (cc);
252b5132
RH		 6140 }
6141 }
6142
6143 if (truelab == NULL)
6144 {
6145 cc = reverse_mri_condition (cc);
6146 truelab = falselab;
6147 }
92774660 6148
252b5132
RH		 6149 if (leftstart != NULL)
6150 {
6151 buf = (char *) xmalloc (20
6152 + (leftstop - leftstart)
6153 + (rightstop - rightstart));
6154 s = buf;
6155 *s++ = 'c';
6156 *s++ = 'm';
6157 *s++ = 'p';
6158 if (qual != '\0')
3882b010 6159 *s++ = TOLOWER (qual);
252b5132
RH		 6160 *s++ = ' ';
6161 memcpy (s, leftstart, leftstop - leftstart);
6162 s += leftstop - leftstart;
6163 *s++ = ',';
6164 memcpy (s, rightstart, rightstop - rightstart);
6165 s += rightstop - rightstart;
6166 *s = '\0';
6167 mri_assemble (buf);
6168 free (buf);
6169 }
92774660 6170
252b5132
RH		 6171 buf = (char *) xmalloc (20 + strlen (truelab));
6172 s = buf;
6173 *s++ = 'b';
6174 *s++ = cc >> 8;
6175 *s++ = cc & 0xff;
6176 if (extent != '\0')
3882b010 6177 *s++ = TOLOWER (extent);
252b5132
RH		 6178 *s++ = ' ';
6179 strcpy (s, truelab);
6180 mri_assemble (buf);
6181 free (buf);
6182}
6183
6184/* Parse an MRI structured control expression. This generates test
6185 and branch instructions. STOP is where the expression ends. It
6186 goes to TRUELAB if the condition is true, and to FALSELAB if the
6187 condition is false. Exactly one of TRUELAB and FALSELAB will be
6188 NULL, meaning to fall through. QUAL is the size qualifier for the
6189 expression. EXTENT is the size to use for the branch. */
6190
6191static void
6192parse_mri_control_expression (stop, qual, truelab, falselab, extent)
6193 char *stop;
6194 int qual;
6195 const char *truelab;
6196 const char *falselab;
6197 int extent;
6198{
6199 int c;
6200 int cc;
6201 char *leftstart;
6202 char *leftstop;
6203 char *rightstart;
6204 char *rightstop;
6205
6206 c = *stop;
6207 *stop = '\0';
6208
6209 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6210 &rightstart, &rightstop))
6211 {
6212 *stop = c;
6213 return;
6214 }
6215
6216 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6217 {
6218 const char *flab;
6219
6220 if (falselab != NULL)
6221 flab = falselab;
6222 else
6223 flab = mri_control_label ();
6224
6225 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6226 rightstop, (const char *) NULL, flab, extent);
6227
6228 input_line_pointer += 3;
6229 if (*input_line_pointer != '.'
6230 || input_line_pointer[1] == '\0')
6231 qual = '\0';
6232 else
6233 {
6234 qual = input_line_pointer[1];
6235 input_line_pointer += 2;
6236 }
6237
6238 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6239 &rightstart, &rightstop))
6240 {
6241 *stop = c;
6242 return;
6243 }
6244
6245 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6246 rightstop, truelab, falselab, extent);
6247
6248 if (falselab == NULL)
6249 colon (flab);
6250 }
6251 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6252 {
6253 const char *tlab;
6254
6255 if (truelab != NULL)
6256 tlab = truelab;
6257 else
6258 tlab = mri_control_label ();
6259
6260 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6261 rightstop, tlab, (const char *) NULL, extent);
6262
6263 input_line_pointer += 2;
6264 if (*input_line_pointer != '.'
6265 || input_line_pointer[1] == '\0')
6266 qual = '\0';
6267 else
6268 {
6269 qual = input_line_pointer[1];
6270 input_line_pointer += 2;
6271 }
6272
6273 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6274 &rightstart, &rightstop))
6275 {
6276 *stop = c;
6277 return;
6278 }
6279
6280 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6281 rightstop, truelab, falselab, extent);
6282
6283 if (truelab == NULL)
6284 colon (tlab);
6285 }
6286 else
6287 {
6288 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6289 rightstop, truelab, falselab, extent);
6290 }
6291
6292 *stop = c;
6293 if (input_line_pointer != stop)
6294 as_bad (_("syntax error in structured control directive"));
6295}
6296
6297/* Handle the MRI IF pseudo-op. This may be a structured control
6298 directive, or it may be a regular assembler conditional, depending
6299 on its operands. */
6300
6301static void
6302s_mri_if (qual)
6303 int qual;
6304{
6305 char *s;
6306 int c;
6307 struct mri_control_info *n;
6308
6309 /* A structured control directive must end with THEN with an
6310 optional qualifier. */
6311 s = input_line_pointer;
e1f44d10
NC		 6312 /* We only accept '*' as introduction of comments if preceded by white space
6313 or at first column of a line (I think this can't actually happen here?)
6314 This is important when assembling:
6315 if d0 <ne> 12(a0,d0*2) then
36759679 6316 if d0 <ne> #CONST*20 then. */
e1f44d10
NC		 6317 while ( ! ( is_end_of_line[(unsigned char) *s]
6318 || ( flag_mri
6319 && *s == '*'
6320 && ( s == input_line_pointer
6321 || *(s-1) == ' '
6322 || *(s-1) == '\t'))))
252b5132
RH		 6323 ++s;
6324 --s;
6325 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6326 --s;
6327
6328 if (s - input_line_pointer > 1
6329 && s[-1] == '.')
6330 s -= 2;
6331
6332 if (s - input_line_pointer < 3
6333 || strncasecmp (s - 3, "THEN", 4) != 0)
6334 {
6335 if (qual != '\0')
6336 {
6337 as_bad (_("missing then"));
6338 ignore_rest_of_line ();
6339 return;
6340 }
6341
6342 /* It's a conditional. */
6343 s_if (O_ne);
6344 return;
6345 }
6346
6347 /* Since this might be a conditional if, this pseudo-op will be
6348 called even if we are supported to be ignoring input. Double
6349 check now. Clobber *input_line_pointer so that ignore_input
6350 thinks that this is not a special pseudo-op. */
6351 c = *input_line_pointer;
6352 *input_line_pointer = 0;
6353 if (ignore_input ())
6354 {
6355 *input_line_pointer = c;
6356 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6357 ++input_line_pointer;
6358 demand_empty_rest_of_line ();
6359 return;
6360 }
6361 *input_line_pointer = c;
6362
6363 n = push_mri_control (mri_if);
6364
6365 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6366 n->next, s[1] == '.' ? s[2] : '\0');
6367
6368 if (s[1] == '.')
6369 input_line_pointer = s + 3;
6370 else
6371 input_line_pointer = s + 1;
6372
6373 if (flag_mri)
6374 {
6375 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6376 ++input_line_pointer;
6377 }
6378
6379 demand_empty_rest_of_line ();
6380}
6381
6382/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6383 structured IF, associate the ELSE with the IF. Otherwise, assume
6384 it is a conditional else. */
6385
6386static void
6387s_mri_else (qual)
6388 int qual;
6389{
6390 int c;
6391 char *buf;
6392 char q[2];
6393
6394 if (qual == '\0'
6395 && (mri_control_stack == NULL
6396 || mri_control_stack->type != mri_if
6397 || mri_control_stack->else_seen))
6398 {
6399 s_else (0);
6400 return;
6401 }
6402
6403 c = *input_line_pointer;
6404 *input_line_pointer = 0;
6405 if (ignore_input ())
6406 {
6407 *input_line_pointer = c;
6408 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6409 ++input_line_pointer;
6410 demand_empty_rest_of_line ();
6411 return;
6412 }
6413 *input_line_pointer = c;
6414
6415 if (mri_control_stack == NULL
6416 || mri_control_stack->type != mri_if
6417 || mri_control_stack->else_seen)
6418 {
6419 as_bad (_("else without matching if"));
6420 ignore_rest_of_line ();
6421 return;
6422 }
6423
6424 mri_control_stack->else_seen = 1;
6425
6426 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6427 q[0] = TOLOWER (qual);
252b5132
RH		 6428 q[1] = '\0';
6429 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6430 mri_assemble (buf);
6431 free (buf);
6432
6433 colon (mri_control_stack->next);
6434
6435 if (flag_mri)
6436 {
6437 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6438 ++input_line_pointer;
6439 }
6440
6441 demand_empty_rest_of_line ();
6442}
6443
6444/* Handle the MRI ENDI pseudo-op. */
6445
6446static void
6447s_mri_endi (ignore)
36823076 6448 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6449{
6450 if (mri_control_stack == NULL
6451 || mri_control_stack->type != mri_if)
6452 {
6453 as_bad (_("endi without matching if"));
6454 ignore_rest_of_line ();
6455 return;
6456 }
6457
6458 /* ignore_input will not return true for ENDI, so we don't need to
6459 worry about checking it again here. */
6460
6461 if (! mri_control_stack->else_seen)
6462 colon (mri_control_stack->next);
6463 colon (mri_control_stack->bottom);
6464
6465 pop_mri_control ();
6466
6467 if (flag_mri)
6468 {
6469 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6470 ++input_line_pointer;
6471 }
6472
6473 demand_empty_rest_of_line ();
6474}
6475
6476/* Handle the MRI BREAK pseudo-op. */
6477
6478static void
6479s_mri_break (extent)
6480 int extent;
6481{
6482 struct mri_control_info *n;
6483 char *buf;
6484 char ex[2];
6485
6486 n = mri_control_stack;
6487 while (n != NULL
6488 && n->type != mri_for
6489 && n->type != mri_repeat
6490 && n->type != mri_while)
6491 n = n->outer;
6492 if (n == NULL)
6493 {
6494 as_bad (_("break outside of structured loop"));
6495 ignore_rest_of_line ();
6496 return;
6497 }
6498
6499 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6500 ex[0] = TOLOWER (extent);
252b5132
RH		 6501 ex[1] = '\0';
6502 sprintf (buf, "bra%s %s", ex, n->bottom);
6503 mri_assemble (buf);
6504 free (buf);
6505
6506 if (flag_mri)
6507 {
6508 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6509 ++input_line_pointer;
6510 }
6511
6512 demand_empty_rest_of_line ();
6513}
6514
6515/* Handle the MRI NEXT pseudo-op. */
6516
6517static void
6518s_mri_next (extent)
6519 int extent;
6520{
6521 struct mri_control_info *n;
6522 char *buf;
6523 char ex[2];
6524
6525 n = mri_control_stack;
6526 while (n != NULL
6527 && n->type != mri_for
6528 && n->type != mri_repeat
6529 && n->type != mri_while)
6530 n = n->outer;
6531 if (n == NULL)
6532 {
6533 as_bad (_("next outside of structured loop"));
6534 ignore_rest_of_line ();
6535 return;
6536 }
6537
6538 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6539 ex[0] = TOLOWER (extent);
252b5132
RH		 6540 ex[1] = '\0';
6541 sprintf (buf, "bra%s %s", ex, n->next);
6542 mri_assemble (buf);
6543 free (buf);
6544
6545 if (flag_mri)
6546 {
6547 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6548 ++input_line_pointer;
6549 }
6550
6551 demand_empty_rest_of_line ();
6552}
6553
6554/* Handle the MRI FOR pseudo-op. */
6555
6556static void
6557s_mri_for (qual)
6558 int qual;
6559{
6560 const char *varstart, *varstop;
6561 const char *initstart, *initstop;
6562 const char *endstart, *endstop;
6563 const char *bystart, *bystop;
6564 int up;
6565 int by;
6566 int extent;
6567 struct mri_control_info *n;
6568 char *buf;
6569 char *s;
6570 char ex[2];
6571
6572 /* The syntax is
6573 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6574 */
6575
6576 SKIP_WHITESPACE ();
6577 varstart = input_line_pointer;
6578
6579 /* Look for the '='. */
6580 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6581 && *input_line_pointer != '=')
6582 ++input_line_pointer;
6583 if (*input_line_pointer != '=')
6584 {
6585 as_bad (_("missing ="));
6586 ignore_rest_of_line ();
6587 return;
6588 }
6589
6590 varstop = input_line_pointer;
6591 if (varstop > varstart
6592 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6593 --varstop;
6594
6595 ++input_line_pointer;
6596
6597 initstart = input_line_pointer;
6598
6599 /* Look for TO or DOWNTO. */
6600 up = 1;
6601 initstop = NULL;
6602 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6603 {
6604 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6605 && ! is_part_of_name (input_line_pointer[2]))
6606 {
6607 initstop = input_line_pointer;
6608 input_line_pointer += 2;
6609 break;
6610 }
6611 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6612 && ! is_part_of_name (input_line_pointer[6]))
6613 {
6614 initstop = input_line_pointer;
6615 up = 0;
6616 input_line_pointer += 6;
6617 break;
6618 }
6619 ++input_line_pointer;
6620 }
6621 if (initstop == NULL)
6622 {
6623 as_bad (_("missing to or downto"));
6624 ignore_rest_of_line ();
6625 return;
6626 }
6627 if (initstop > initstart
6628 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6629 --initstop;
6630
6631 SKIP_WHITESPACE ();
6632 endstart = input_line_pointer;
6633
6634 /* Look for BY or DO. */
6635 by = 0;
6636 endstop = NULL;
6637 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6638 {
6639 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6640 && ! is_part_of_name (input_line_pointer[2]))
6641 {
6642 endstop = input_line_pointer;
6643 by = 1;
6644 input_line_pointer += 2;
6645 break;
6646 }
6647 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6648 && (input_line_pointer[2] == '.'
6649 || ! is_part_of_name (input_line_pointer[2])))
6650 {
6651 endstop = input_line_pointer;
6652 input_line_pointer += 2;
6653 break;
6654 }
6655 ++input_line_pointer;
6656 }
6657 if (endstop == NULL)
6658 {
6659 as_bad (_("missing do"));
6660 ignore_rest_of_line ();
6661 return;
6662 }
6663 if (endstop > endstart
6664 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6665 --endstop;
6666
6667 if (! by)
6668 {
6669 bystart = "#1";
6670 bystop = bystart + 2;
6671 }
6672 else
6673 {
6674 SKIP_WHITESPACE ();
6675 bystart = input_line_pointer;
6676
6677 /* Look for DO. */
6678 bystop = NULL;
6679 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6680 {
6681 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6682 && (input_line_pointer[2] == '.'
6683 || ! is_part_of_name (input_line_pointer[2])))
6684 {
6685 bystop = input_line_pointer;
6686 input_line_pointer += 2;
6687 break;
6688 }
6689 ++input_line_pointer;
6690 }
6691 if (bystop == NULL)
6692 {
6693 as_bad (_("missing do"));
6694 ignore_rest_of_line ();
6695 return;
6696 }
6697 if (bystop > bystart
6698 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6699 --bystop;
6700 }
6701
6702 if (*input_line_pointer != '.')
6703 extent = '\0';
6704 else
6705 {
6706 extent = input_line_pointer[1];
6707 input_line_pointer += 2;
6708 }
6709
6710 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6711 n = push_mri_control (mri_for);
6712
6713 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6714
36759679 6715 /* Move init,var. */
252b5132
RH		 6716 s = buf;
6717 *s++ = 'm';
6718 *s++ = 'o';
6719 *s++ = 'v';
6720 *s++ = 'e';
6721 if (qual != '\0')
3882b010 6722 *s++ = TOLOWER (qual);
252b5132
RH		 6723 *s++ = ' ';
6724 memcpy (s, initstart, initstop - initstart);
6725 s += initstop - initstart;
6726 *s++ = ',';
6727 memcpy (s, varstart, varstop - varstart);
6728 s += varstop - varstart;
6729 *s = '\0';
6730 mri_assemble (buf);
6731
6732 colon (n->top);
6733
36759679 6734 /* cmp end,var. */
252b5132
RH		 6735 s = buf;
6736 *s++ = 'c';
6737 *s++ = 'm';
6738 *s++ = 'p';
6739 if (qual != '\0')
3882b010 6740 *s++ = TOLOWER (qual);
252b5132
RH		 6741 *s++ = ' ';
6742 memcpy (s, endstart, endstop - endstart);
6743 s += endstop - endstart;
6744 *s++ = ',';
6745 memcpy (s, varstart, varstop - varstart);
6746 s += varstop - varstart;
6747 *s = '\0';
6748 mri_assemble (buf);
6749
36759679 6750 /* bcc bottom. */
3882b010 6751 ex[0] = TOLOWER (extent);
252b5132
RH		 6752 ex[1] = '\0';
6753 if (up)
6754 sprintf (buf, "blt%s %s", ex, n->bottom);
6755 else
6756 sprintf (buf, "bgt%s %s", ex, n->bottom);
6757 mri_assemble (buf);
6758
6759 /* Put together the add or sub instruction used by ENDF. */
6760 s = buf;
6761 if (up)
6762 strcpy (s, "add");
6763 else
6764 strcpy (s, "sub");
6765 s += 3;
6766 if (qual != '\0')
3882b010 6767 *s++ = TOLOWER (qual);
252b5132
RH		 6768 *s++ = ' ';
6769 memcpy (s, bystart, bystop - bystart);
6770 s += bystop - bystart;
6771 *s++ = ',';
6772 memcpy (s, varstart, varstop - varstart);
6773 s += varstop - varstart;
6774 *s = '\0';
6775 n->incr = buf;
6776
6777 if (flag_mri)
6778 {
6779 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6780 ++input_line_pointer;
6781 }
6782
6783 demand_empty_rest_of_line ();
6784}
6785
6786/* Handle the MRI ENDF pseudo-op. */
6787
6788static void
6789s_mri_endf (ignore)
36823076 6790 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6791{
6792 if (mri_control_stack == NULL
6793 || mri_control_stack->type != mri_for)
6794 {
6795 as_bad (_("endf without for"));
6796 ignore_rest_of_line ();
6797 return;
6798 }
6799
6800 colon (mri_control_stack->next);
6801
6802 mri_assemble (mri_control_stack->incr);
6803
6804 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6805 mri_assemble (mri_control_stack->incr);
6806
6807 free (mri_control_stack->incr);
6808
6809 colon (mri_control_stack->bottom);
6810
6811 pop_mri_control ();
6812
6813 if (flag_mri)
6814 {
6815 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6816 ++input_line_pointer;
6817 }
6818
6819 demand_empty_rest_of_line ();
6820}
6821
6822/* Handle the MRI REPEAT pseudo-op. */
6823
6824static void
6825s_mri_repeat (ignore)
36823076 6826 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6827{
6828 struct mri_control_info *n;
6829
6830 n = push_mri_control (mri_repeat);
6831 colon (n->top);
6832 if (flag_mri)
6833 {
6834 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6835 ++input_line_pointer;
6836 }
6837 demand_empty_rest_of_line ();
6838}
6839
6840/* Handle the MRI UNTIL pseudo-op. */
6841
6842static void
6843s_mri_until (qual)
6844 int qual;
6845{
6846 char *s;
6847
6848 if (mri_control_stack == NULL
6849 || mri_control_stack->type != mri_repeat)
6850 {
6851 as_bad (_("until without repeat"));
6852 ignore_rest_of_line ();
6853 return;
6854 }
6855
6856 colon (mri_control_stack->next);
6857
6858 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6859 ;
6860
6861 parse_mri_control_expression (s, qual, (const char *) NULL,
6862 mri_control_stack->top, '\0');
6863
6864 colon (mri_control_stack->bottom);
6865
6866 input_line_pointer = s;
6867
6868 pop_mri_control ();
6869
6870 if (flag_mri)
6871 {
6872 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6873 ++input_line_pointer;
6874 }
6875
6876 demand_empty_rest_of_line ();
6877}
6878
6879/* Handle the MRI WHILE pseudo-op. */
6880
6881static void
6882s_mri_while (qual)
6883 int qual;
6884{
6885 char *s;
6886
6887 struct mri_control_info *n;
6888
6889 s = input_line_pointer;
e1f44d10
NC		 6890 /* We only accept '*' as introduction of comments if preceded by white space
6891 or at first column of a line (I think this can't actually happen here?)
6892 This is important when assembling:
6893 while d0 <ne> 12(a0,d0*2) do
36759679 6894 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6895 while (! (is_end_of_line[(unsigned char) *s]
6896 || (flag_mri
6897 && *s == '*'
6898 && (s == input_line_pointer
6899 || *(s-1) == ' '
6900 || *(s-1) == '\t'))))
252b5132
RH		 6901 s++;
6902 --s;
6903 while (*s == ' ' || *s == '\t')
6904 --s;
6905 if (s - input_line_pointer > 1
6906 && s[-1] == '.')
6907 s -= 2;
6908 if (s - input_line_pointer < 2
6909 || strncasecmp (s - 1, "DO", 2) != 0)
6910 {
6911 as_bad (_("missing do"));
6912 ignore_rest_of_line ();
6913 return;
6914 }
6915
6916 n = push_mri_control (mri_while);
6917
6918 colon (n->next);
6919
6920 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6921 s[1] == '.' ? s[2] : '\0');
6922
6923 input_line_pointer = s + 1;
6924 if (*input_line_pointer == '.')
6925 input_line_pointer += 2;
6926
6927 if (flag_mri)
6928 {
6929 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6930 ++input_line_pointer;
6931 }
6932
6933 demand_empty_rest_of_line ();
6934}
6935
6936/* Handle the MRI ENDW pseudo-op. */
6937
6938static void
6939s_mri_endw (ignore)
36823076 6940 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6941{
6942 char *buf;
6943
6944 if (mri_control_stack == NULL
6945 || mri_control_stack->type != mri_while)
6946 {
6947 as_bad (_("endw without while"));
6948 ignore_rest_of_line ();
6949 return;
6950 }
6951
6952 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6953 sprintf (buf, "bra %s", mri_control_stack->next);
6954 mri_assemble (buf);
6955 free (buf);
6956
6957 colon (mri_control_stack->bottom);
6958
6959 pop_mri_control ();
6960
6961 if (flag_mri)
6962 {
6963 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6964 ++input_line_pointer;
6965 }
6966
6967 demand_empty_rest_of_line ();
6968}
6969\f
6970/*
6971 * md_parse_option
6972 * Invocation line includes a switch not recognized by the base assembler.
6973 * See if it's a processor-specific option. These are:
6974 *
6975 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6976 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6977 * Select the architecture. Instructions or features not
6978 * supported by the selected architecture cause fatal
6979 * errors. More than one may be specified. The default is
6980 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6981 * for -m68000, and -m68882 is a synonym for -m68881.
6982 * -[A]m[c]no-68851, -[A]m[c]no-68881
6983 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6984 * so don't use or document it, but that's the way the parsing
6985 * works).
6986 *
6987 * -pic Indicates PIC.
6988 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6989 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6990 *
6991 * --bitwise-or
6992 * Permit `|' to be used in expressions.
6993 *
6994 */
6995
6996#ifdef OBJ_ELF
5a38dc70 6997const char *md_shortopts = "lSA:m:kQ:V";
252b5132 6998#else
5a38dc70 6999const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7000#endif
7001
7002struct option md_longopts[] = {
7003#define OPTION_PIC (OPTION_MD_BASE)
7004 {"pic", no_argument, NULL, OPTION_PIC},
7005#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7006 {"register-prefix-optional", no_argument, NULL,
7007 OPTION_REGISTER_PREFIX_OPTIONAL},
7008#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7009 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7010#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7011 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7012#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7013 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7014#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7015 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7016#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7017 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7018#define OPTION_PCREL (OPTION_MD_BASE + 7)
7019 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7020 {NULL, no_argument, NULL, 0}
7021};
bc805888 7022size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7023
7024int
7025md_parse_option (c, arg)
7026 int c;
7027 char *arg;
7028{
7029 switch (c)
7030 {
7031 case 'l': /* -l means keep external to 2 bit offset
36759679 7032 rather than 16 bit one. */
252b5132
RH		 7033 flag_short_refs = 1;
7034 break;
7035
7036 case 'S': /* -S means that jbsr's always turn into
7037 jsr's. */
7038 flag_long_jumps = 1;
7039 break;
7040
28e7409f
NC		 7041 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7042 branches into absolute jumps. */
7043 flag_keep_pcrel = 1;
7044 break;
7045
252b5132
RH		 7046 case 'A':
7047 if (*arg == 'm')
8a104df9 7048 arg++;
36759679 7049 /* Intentional fall-through. */
252b5132
RH		 7050 case 'm':
7051
7052 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7053 {
7054 int i;
7055 unsigned long arch;
7056 const char *oarg = arg;
7057
7058 arg += 3;
7059 if (*arg == 'm')
7060 {
7061 arg++;
7062 if (arg[0] == 'c' && arg[1] == '6')
7063 arg++;
7064 }
7065 for (i = 0; i < n_archs; i++)
7066 if (!strcmp (arg, archs[i].name))
7067 break;
7068 if (i == n_archs)
7069 {
7070 unknown:
7071 as_bad (_("unrecognized option `%s'"), oarg);
7072 return 0;
7073 }
7074 arch = archs[i].arch;
7075 if (arch == m68881)
7076 no_68881 = 1;
7077 else if (arch == m68851)
7078 no_68851 = 1;
7079 else
7080 goto unknown;
7081 }
7082 else
7083 {
7084 int i;
7085
7086 if (arg[0] == 'c' && arg[1] == '6')
7087 arg++;
7088
7089 for (i = 0; i < n_archs; i++)
7090 if (!strcmp (arg, archs[i].name))
7091 {
7092 unsigned long arch = archs[i].arch;
7093 if (cpu_of_arch (arch))
7094 /* It's a cpu spec. */
7095 {
7096 current_architecture &= ~m68000up;
7097 current_architecture |= arch;
7098 }
7099 else if (arch == m68881)
7100 {
7101 current_architecture |= m68881;
7102 no_68881 = 0;
7103 }
7104 else if (arch == m68851)
7105 {
7106 current_architecture |= m68851;
7107 no_68851 = 0;
7108 }
7109 else
7110 /* ??? */
7111 abort ();
7112 break;
7113 }
7114 if (i == n_archs)
7115 {
7116 as_bad (_("unrecognized architecture specification `%s'"), arg);
7117 return 0;
7118 }
7119 }
7120 break;
7121
7122 case OPTION_PIC:
7123 case 'k':
7124 flag_want_pic = 1;
36759679 7125 break; /* -pic, Position Independent Code. */
252b5132
RH		 7126
7127 case OPTION_REGISTER_PREFIX_OPTIONAL:
7128 flag_reg_prefix_optional = 1;
7129 reg_prefix_optional_seen = 1;
7130 break;
7131
7132 /* -V: SVR4 argument to print version ID. */
7133 case 'V':
7134 print_version_id ();
7135 break;
7136
7137 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7138 should be emitted or not. FIXME: Not implemented. */
7139 case 'Q':
7140 break;
7141
7142 case OPTION_BITWISE_OR:
7143 {
7144 char *n, *t;
7145 const char *s;
7146
7147 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7148 t = n;
7149 for (s = m68k_comment_chars; *s != '\0'; s++)
7150 if (*s != '|')
7151 *t++ = *s;
7152 *t = '\0';
7153 m68k_comment_chars = n;
7154 }
7155 break;
7156
7157 case OPTION_BASE_SIZE_DEFAULT_16:
7158 m68k_index_width_default = SIZE_WORD;
7159 break;
7160
7161 case OPTION_BASE_SIZE_DEFAULT_32:
7162 m68k_index_width_default = SIZE_LONG;
7163 break;
7164
7165 case OPTION_DISP_SIZE_DEFAULT_16:
7166 m68k_rel32 = 0;
7167 m68k_rel32_from_cmdline = 1;
7168 break;
7169
7170 case OPTION_DISP_SIZE_DEFAULT_32:
7171 m68k_rel32 = 1;
7172 m68k_rel32_from_cmdline = 1;
7173 break;
7174
7175 default:
7176 return 0;
7177 }
7178
7179 return 1;
7180}
7181
7182void
7183md_show_usage (stream)
7184 FILE *stream;
7185{
76f57f3a 7186 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7187 int i;
7188 unsigned int default_arch;
76f57f3a 7189
8a104df9 7190 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7191 if (*default_cpu == 'm')
7192 default_cpu++;
7193 for (i = 0; i < n_archs; i++)
7194 {
7195 if (strcasecmp (default_cpu, archs[i].name) == 0)
7196 {
7197 default_arch = archs[i].arch;
7198 for (i = 0; i < n_archs; i++)
7199 {
7200 if (archs[i].arch == default_arch
7201 && !archs[i].alias)
7202 {
7203 default_cpu = archs[i].name;
7204 break;
7205 }
7206 }
7207 }
7208 }
7209
bc805888 7210 fprintf (stream, _("\
252b5132
RH		 7211680X0 options:\n\
7212-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 7213-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7214-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
3e602632
NC		 7215-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m528x | -m5307 |\n\
7216-m5407 | -mcfv4 | -mcfv4e\n\
76f57f3a 7217 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 7218-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7219 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 7220 [default yes for 68020, 68030, and cpu32]\n"),
7221 default_cpu);
bc805888 7222 fprintf (stream, _("\
252b5132
RH		 7223-m68851 | -mno-68851\n\
7224 target has/lacks memory-management unit coprocessor\n\
7225 [default yes for 68020 and up]\n\
7226-pic, -k generate position independent code\n\
7227-S turn jbsr into jsr\n\
28e7409f 7228--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7229--register-prefix-optional\n\
7230 recognize register names without prefix character\n\
7231--bitwise-or do not treat `|' as a comment character\n"));
7232 fprintf (stream, _("\
7233--base-size-default-16 base reg without size is 16 bits\n\
7234--base-size-default-32 base reg without size is 32 bits (default)\n\
7235--disp-size-default-16 displacement with unknown size is 16 bits\n\
7236--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7237}
7238\f
7239#ifdef TEST2
7240
7241/* TEST2: Test md_assemble() */
36759679
NC		 7242/* Warning, this routine probably doesn't work anymore. */
7243int
252b5132
RH		 7244main ()
7245{
7246 struct m68k_it the_ins;
7247 char buf[120];
7248 char *cp;
7249 int n;
7250
7251 m68k_ip_begin ();
7252 for (;;)
7253 {
7254 if (!gets (buf) || !*buf)
7255 break;
7256 if (buf[0] == '|' || buf[1] == '.')
7257 continue;
7258 for (cp = buf; *cp; cp++)
7259 if (*cp == '\t')
7260 *cp = ' ';
7261 if (is_label (buf))
7262 continue;
7263 memset (&the_ins, '\0', sizeof (the_ins));
7264 m68k_ip (&the_ins, buf);
7265 if (the_ins.error)
7266 {
7267 printf (_("Error %s in %s\n"), the_ins.error, buf);
7268 }
7269 else
7270 {
7271 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7272 for (n = 0; n < the_ins.numo; n++)
7273 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7274 printf (" ");
7275 print_the_insn (&the_ins.opcode[0], stdout);
7276 (void) putchar ('\n');
7277 }
7278 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7279 {
7280 if (the_ins.operands[n].error)
7281 {
7282 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7283 continue;
7284 }
7285 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7286 if (the_ins.operands[n].b_const)
7287 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7288 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7289 if (the_ins.operands[n].b_iadd)
7290 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7291 (void) putchar ('\n');
7292 }
7293 }
7294 m68k_ip_end ();
7295 return 0;
7296}
7297
7298is_label (str)
7299 char *str;
7300{
7301 while (*str == ' ')
7302 str++;
7303 while (*str && *str != ' ')
7304 str++;
7305 if (str[-1] == ':' || str[1] == '=')
7306 return 1;
7307 return 0;
7308}
7309
7310#endif
7311
7312/* Possible states for relaxation:
7313
7314 0 0 branch offset byte (bra, etc)
7315 0 1 word
7316 0 2 long
7317
7318 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7319 1 1 word
7320 1 2 long
7321
7322 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7323 2 1 word-long
7324 2 2 long-word
7325 2 3 long-long
7326
7327 */
7328
7329/* We have no need to default values of symbols. */
7330
252b5132
RH		 7331symbolS *
7332md_undefined_symbol (name)
36823076 7333 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7334{
7335 return 0;
7336}
7337
7338/* Round up a section size to the appropriate boundary. */
7339valueT
7340md_section_align (segment, size)
36823076 7341 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7342 valueT size;
7343{
7344#ifdef OBJ_AOUT
7345#ifdef BFD_ASSEMBLER
7346 /* For a.out, force the section size to be aligned. If we don't do
7347 this, BFD will align it for us, but it will not write out the
7348 final bytes of the section. This may be a bug in BFD, but it is
7349 easier to fix it here since that is how the other a.out targets
7350 work. */
7351 int align;
7352
7353 align = bfd_get_section_alignment (stdoutput, segment);
7354 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7355#endif
7356#endif
7357
7358 return size;
7359}
7360
7361/* Exactly what point is a PC-relative offset relative TO?
7362 On the 68k, it is relative to the address of the first extension
7363 word. The difference between the addresses of the offset and the
92774660 7364 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7365long
7366md_pcrel_from (fixP)
7367 fixS *fixP;
7368{
7369 int adjust;
7370
8390138c
AS		 7371 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7372 sign extend the value here. */
7373 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7374 if (adjust == 64)
7375 adjust = -1;
7376 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7377}
7378
7379#ifndef BFD_ASSEMBLER
7380#ifdef OBJ_COFF
7381
252b5132
RH		 7382void
7383tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7384 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7385{
7386}
7387
7388int
7389tc_coff_sizemachdep (frag)
7390 fragS *frag;
7391{
7392 switch (frag->fr_subtype & 0x3)
7393 {
7394 case BYTE:
7395 return 1;
7396 case SHORT:
7397 return 2;
7398 case LONG:
7399 return 4;
7400 default:
7401 abort ();
7402 return 0;
7403 }
7404}
7405
7406#endif
7407#endif
0d96863f 7408#ifdef OBJ_ELF
8a104df9
KH		 7409void
7410m68k_elf_final_processing ()
0d96863f 7411{
36759679 7412 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9
KH		 7413 if (cpu_of_arch (current_architecture) & cpu32)
7414 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7415 else if ((cpu_of_arch (current_architecture) & m68000up)
7416 && !(cpu_of_arch (current_architecture) & m68020up))
7417 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7418}
7419#endif
c04898f8
AS		 7420
7421int
7422tc_m68k_regname_to_dw2regnum (const char *regname)
7423{
7424 unsigned int regnum;
7425 static const char *const regnames[] =
7426 {
7427 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7428 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7429 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7430 "pc"
7431 };
7432
7433 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7434 if (strcmp (regname, regnames[regnum]) == 0)
7435 return regnum;
7436
7437 return -1;
7438}
7439
7440void
7441tc_m68k_frame_initial_instructions (void)
7442{
7443 static int sp_regno = -1;
7444
7445 if (sp_regno < 0)
7446 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7447
7448 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7449 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7450}
GDB Binutils - Deliverables
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